From ef600bc63fbc23d7fb4371051593114bc6934a69 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 12 Jul 2019 15:57:41 -0600 Subject: [PATCH 001/482] Save workspace --- ERI_demo/ERI.sh | 49 ---- ERI_demo/eri_demo.sh | 52 ----- ERI_demo/my_eri_demo.sh | 42 ---- ERI_demo/pipelined_8b_adder.act | 95 -------- ERI_demo/pipelined_8b_adder.blif | 137 ----------- ERI_demo/pipelined_8b_adder.v | 63 ----- .../pipelined_8b_adder_formal_random_top_tb.v | 219 ------------------ .../k6_N10_sram_chain_HC_DPRAM_template.xml | 2 +- .../k6_N10_sram_chain_HC_template.xml | 2 +- .../Blif/Test_Modes/test_modes.blif | 1 + fpga_flow/benchmarks/List/mcnc_benchmark.txt | 38 +-- vpr7_x2p/vpr/regression_verilog.sh | 6 +- 12 files changed, 25 insertions(+), 681 deletions(-) delete mode 100755 ERI_demo/ERI.sh delete mode 100644 ERI_demo/eri_demo.sh delete mode 100644 ERI_demo/my_eri_demo.sh delete mode 100644 ERI_demo/pipelined_8b_adder.act delete mode 100644 ERI_demo/pipelined_8b_adder.blif delete mode 100644 ERI_demo/pipelined_8b_adder.v delete mode 100644 ERI_demo/pipelined_8b_adder_formal_random_top_tb.v diff --git a/ERI_demo/ERI.sh b/ERI_demo/ERI.sh deleted file mode 100755 index 75211050a..000000000 --- a/ERI_demo/ERI.sh +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/bash -# Regression test version 1.0 - -# Set variables -my_pwd=$PWD -fpga_flow_scripts=${my_pwd}/fpga_flow/scripts -vpr_path=${my_pwd}/vpr7_x2p/vpr -benchmark="pipelined_8b_adder" -include_netlists="_include_netlists.v" -compiled_file="compiled_$benchmark" -tb_formal_postfix="_top_formal_verification_random_tb" -verilog_output_dirname="${vpr_path}${benchmark}_Verilog" -log_file="${benchmark}_sim.log" -new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh" -template_sh="${PWD}/ERI_demo/eri_demo.sh" - - -# Remove former log file -rm -f $log_file -rm -f $compiled_file - -# Rewite script -cd $fpga_flow_scripts - -perl rewrite_path_in_file.pl -i $template_sh -o $new_reg_sh - -cd $my_pwd - -# Start the script -> run the fpga generation -> run the simulation -> check the log file -source $new_reg_sh # Leave us in vpr folder -iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix -vvp $compiled_file -j 64 >> $log_file - -result=`grep "Succeed" $log_file` -if ["$result" = ""]; then - result=`grep "Failed" $log_file` - if ["$result" = ""]; then - echo "Unexpected error, Verification didn't run" - cd $my_pwd - exit 1 - else - echo "Verification failed" - cd $my_pwd - exit 2 - fi -else - echo "Verification succeed" - cd $my_pwd -fi diff --git a/ERI_demo/eri_demo.sh b/ERI_demo/eri_demo.sh deleted file mode 100644 index 807c5110b..000000000 --- a/ERI_demo/eri_demo.sh +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/bash -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -benchmark="pipelined_8b_adder" -OpenFPGA_path="OPENFPGAPATHKEYWORD" -verilog_output_dirname="${benchmark}_Verilog" -verilog_output_dirpath="$vpr_path" -tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" -# VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" -blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" -act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act " -verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v" -vpr_route_chan_width="300" -fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" -ff_path="$vpr_path/VerilogNetlists/ff.v" -new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" -ff_keyword="GENERATED_DIR_KEYWORD" -ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" -arch_ff_keyword="FFPATHKEYWORD" -tb_formal_ext="_formal_random_top_tb.v" -formal_postfix="_top_formal_verification" -clk_unmapped="clk\[0:0\]" -clk_mapped="clk_fm" - -# Remove previous designs -rm -rf $verilog_output_dirpath/$verilog_output_dirname - -mkdir ${OpenFPGA_path}/fpga_flow/arch/generated - -#cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file -perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path - -# Move to vpr folder -cd $vpr_path - -# Run VPR -./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path - -rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext} -perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext} -cd - - -sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v - diff --git a/ERI_demo/my_eri_demo.sh b/ERI_demo/my_eri_demo.sh deleted file mode 100644 index 2e6220ba3..000000000 --- a/ERI_demo/my_eri_demo.sh +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/bash -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -benchmark="pipelined_32b_adder" -OpenFPGA_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA" -verilog_output_dirname="${benchmark}_Verilog" -verilog_output_dirpath="$vpr_path" -tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" -# VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" -blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" -act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act " -verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v" -vpr_route_chan_width="300" -fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" -ff_path="$vpr_path/VerilogNetlists/ff.v" -new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" -ff_keyword="GENERATED_DIR_KEYWORD" -ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" -arch_ff_keyword="FFPATHKEYWORD" - -# Remove previous designs -#rm -rf $verilog_output_dirpath/$verilog_output_dirname - -mkdir ${OpenFPGA_path}/fpga_flow/arch/generated - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file -perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path - -# Move to vpr folder -cd $vpr_path - -# Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path -cd - diff --git a/ERI_demo/pipelined_8b_adder.act b/ERI_demo/pipelined_8b_adder.act deleted file mode 100644 index c7a502a2d..000000000 --- a/ERI_demo/pipelined_8b_adder.act +++ /dev/null @@ -1,95 +0,0 @@ -clk 0.5 0.2 -wen 0.5 0.2 -wen_st0 0.5 0.2 -wen_st1 0.5 0.2 -ren 0.5 0.2 -raddr[0] 0.5 0.2 -raddr[1] 0.5 0.2 -raddr[2] 0.5 0.2 -raddr[3] 0.5 0.2 -raddr[4] 0.5 0.2 -raddr[5] 0.5 0.2 -waddr[0] 0.5 0.2 -waddr[1] 0.5 0.2 -waddr[2] 0.5 0.2 -waddr[3] 0.5 0.2 -waddr[4] 0.5 0.2 -waddr[5] 0.5 0.2 -waddr_st0[0] 0.5 0.2 -waddr_st0[1] 0.5 0.2 -waddr_st0[2] 0.5 0.2 -waddr_st0[3] 0.5 0.2 -waddr_st0[4] 0.5 0.2 -waddr_st0[5] 0.5 0.2 -waddr_st1[0] 0.5 0.2 -waddr_st1[1] 0.5 0.2 -waddr_st1[2] 0.5 0.2 -waddr_st1[3] 0.5 0.2 -waddr_st1[4] 0.5 0.2 -waddr_st1[5] 0.5 0.2 -a[0] 0.5 0.2 -a[1] 0.5 0.2 -a[2] 0.5 0.2 -a[3] 0.5 0.2 -a[4] 0.5 0.2 -a[5] 0.5 0.2 -a[6] 0.5 0.2 -a_st0[0] 0.5 0.2 -a_st0[1] 0.5 0.2 -a_st0[2] 0.5 0.2 -a_st0[3] 0.5 0.2 -a_st0[4] 0.5 0.2 -a_st0[5] 0.5 0.2 -a_st0[6] 0.5 0.2 -a_st1[0] 0.5 0.2 -a_st1[1] 0.5 0.2 -a_st1[2] 0.5 0.2 -a_st1[3] 0.5 0.2 -a_st1[4] 0.5 0.2 -a_st1[5] 0.5 0.2 -a_st1[6] 0.5 0.2 -b[0] 0.5 0.2 -b[1] 0.5 0.2 -b[2] 0.5 0.2 -b[3] 0.5 0.2 -b[4] 0.5 0.2 -b[5] 0.5 0.2 -b[6] 0.5 0.2 -b_st0[0] 0.5 0.2 -b_st0[1] 0.5 0.2 -b_st0[2] 0.5 0.2 -b_st0[3] 0.5 0.2 -b_st0[4] 0.5 0.2 -b_st0[5] 0.5 0.2 -b_st0[6] 0.5 0.2 -b_st1[0] 0.5 0.2 -b_st1[1] 0.5 0.2 -b_st1[2] 0.5 0.2 -b_st1[3] 0.5 0.2 -b_st1[4] 0.5 0.2 -b_st1[5] 0.5 0.2 -b_st1[6] 0.5 0.2 -q[0] 0.5 0.2 -q[1] 0.5 0.2 -q[2] 0.5 0.2 -q[3] 0.5 0.2 -q[4] 0.5 0.2 -q[5] 0.5 0.2 -q[6] 0.5 0.2 -q[7] 0.5 0.2 -AplusB[0] 0.5 0.2 -AplusB[1] 0.5 0.2 -AplusB[2] 0.5 0.2 -AplusB[3] 0.5 0.2 -AplusB[4] 0.5 0.2 -AplusB[5] 0.5 0.2 -AplusB[6] 0.5 0.2 -AplusB[7] 0.5 0.2 -cint01 0.5 0.2 -cint02 0.5 0.2 -cint03 0.5 0.2 -cint04 0.5 0.2 -cint05 0.5 0.2 -cint06 0.5 0.2 -cint07 0.5 0.2 -zero00 0 0 diff --git a/ERI_demo/pipelined_8b_adder.blif b/ERI_demo/pipelined_8b_adder.blif deleted file mode 100644 index 7f47b1661..000000000 --- a/ERI_demo/pipelined_8b_adder.blif +++ /dev/null @@ -1,137 +0,0 @@ -# Benchmark pipelined_32b_adder -.model pipelined_32b_adder -.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6] -.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7] - -# Start pipeline -# Pipeline a -.subckt shift D=a[0] clk=clk Q=a_st0[0] -.subckt shift D=a_st0[0] clk=clk Q=a_st1[0] -.subckt shift D=a[1] clk=clk Q=a_st0[1] -.subckt shift D=a_st0[1] clk=clk Q=a_st1[1] -.subckt shift D=a[2] clk=clk Q=a_st0[2] -.subckt shift D=a_st0[2] clk=clk Q=a_st1[2] -.subckt shift D=a[3] clk=clk Q=a_st0[3] -.subckt shift D=a_st0[3] clk=clk Q=a_st1[3] -.subckt shift D=a[4] clk=clk Q=a_st0[4] -.subckt shift D=a_st0[4] clk=clk Q=a_st1[4] -.subckt shift D=a[5] clk=clk Q=a_st0[5] -.subckt shift D=a_st0[5] clk=clk Q=a_st1[5] -.subckt shift D=a[6] clk=clk Q=a_st0[6] -.subckt shift D=a_st0[6] clk=clk Q=a_st1[6] - -# Pipeline b -.subckt shift D=b[0] clk=clk Q=b_st0[0] -.subckt shift D=b_st0[0] clk=clk Q=b_st1[0] -.subckt shift D=b[1] clk=clk Q=b_st0[1] -.subckt shift D=b_st0[1] clk=clk Q=b_st1[1] -.subckt shift D=b[2] clk=clk Q=b_st0[2] -.subckt shift D=b_st0[2] clk=clk Q=b_st1[2] -.subckt shift D=b[3] clk=clk Q=b_st0[3] -.subckt shift D=b_st0[3] clk=clk Q=b_st1[3] -.subckt shift D=b[4] clk=clk Q=b_st0[4] -.subckt shift D=b_st0[4] clk=clk Q=b_st1[4] -.subckt shift D=b[5] clk=clk Q=b_st0[5] -.subckt shift D=b_st0[5] clk=clk Q=b_st1[5] -.subckt shift D=b[6] clk=clk Q=b_st0[6] -.subckt shift D=b_st0[6] clk=clk Q=b_st1[6] - -# Pipeline waddr -.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0] -.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0] -.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1] -.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1] -.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2] -.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2] -.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3] -.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3] -.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4] -.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4] -.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5] -.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5] -# Pipeline wen -.subckt shift D=wen clk=clk Q=wen_st0 -.subckt shift D=wen_st0 clk=clk Q=wen_st1 -# End pipeline - -# Start adder -.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0] -.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1] -.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2] -.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3] -.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4] -.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5] -.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6] -.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7] -# End adder - -# Start DPRAM -.subckt dpram clk=clk wen=wen_st1 ren=ren \ -waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \ -waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \ -raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \ -raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \ -d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \ -d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \ -d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \ -d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \ -d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \ -d_in[30]=zero00 d_in[31]=zero00 \ -d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \ -d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \ -d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \ -d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \ -d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \ -d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \ -d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \ -d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn -# End DPRAM - -# Start global variable -.names zero00 -0 -# End global variable - - -.end - -# Start blackbox definition -.model dpram -.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ - waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \ - raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ - d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ - d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \ - d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \ - d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \ - d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \ - d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \ - d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \ - d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63] -.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \ - d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \ - d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \ - d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \ - d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \ - d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \ - d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \ - d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \ - d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \ - d_out[63] -.blackbox -.end - - -.model adder -.inputs a b cin -.outputs cout sumout -.blackbox -.end - - -.model shift -.inputs D clk -.outputs Q -.blackbox -.end -# End blackbox definition diff --git a/ERI_demo/pipelined_8b_adder.v b/ERI_demo/pipelined_8b_adder.v deleted file mode 100644 index 4d8e975cd..000000000 --- a/ERI_demo/pipelined_8b_adder.v +++ /dev/null @@ -1,63 +0,0 @@ -///////////////////////////////////// -// // -// ERI summit demo-benchmark // -// pipelined_8b_adder.v // -// by Aurelien // -// // -///////////////////////////////////// - -`timescale 1 ns/ 1 ps - -module pipelined_8b_adder( - clk, - raddr, - waddr, - ren, - wen, - a, - b, - q ); - - input clk; - input[5:0] raddr; - input[5:0] waddr; - input ren; - input wen; - input[6:0] a; - input[6:0] b; - output[7:0] q; - - reg[63:0] ram[7:0]; - reg[6:0] a_st0; - reg[6:0] a_st1; - reg[6:0] b_st0; - reg[6:0] b_st1; - reg[8:0] waddr_st0; - reg[8:0] waddr_st1; - reg wen_st0; - reg wen_st1; - reg[7:0] q_int; - - wire[7:0] AplusB; - - assign AplusB = a_st1 + b_st1; - assign q = q_int; - - always@(posedge clk) begin - waddr_st0 <= waddr; - waddr_st1 <= waddr_st0; - a_st0 <= a; - a_st1 <= a_st0; - b_st0 <= b; - b_st1 <= b_st0; - wen_st0 <= wen; - wen_st1 <= wen_st0; - if(wen_st1) begin - ram[waddr_st1] <= AplusB; - end - if(ren) begin - q_int <= ram[raddr]; - end - end - -endmodule diff --git a/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v b/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v deleted file mode 100644 index d43a5b694..000000000 --- a/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v +++ /dev/null @@ -1,219 +0,0 @@ -`timescale 1 ns/ 100 ps - -`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v" - -module pipelined_8b_adder_top_formal_verification_random_tb(); - reg clk; - reg[5:0] raddr; - reg[5:0] waddr; - reg ren; - reg wen; - reg[6:0] a; - reg[6:0] b; - wire[7:0] q_gfpga; - wire[7:0] q_bench; - reg[7:0] q_flag; - - pipelined_8b_adder_top_formal_verification DUT( - .clk_fm (clk), - .raddr_0__fm (raddr[0]), - .raddr_1__fm (raddr[1]), - .raddr_2__fm (raddr[2]), - .raddr_3__fm (raddr[3]), - .raddr_4__fm (raddr[4]), - .raddr_5__fm (raddr[5]), - .waddr_0__fm (waddr[0]), - .waddr_1__fm (waddr[1]), - .waddr_2__fm (waddr[2]), - .waddr_3__fm (waddr[3]), - .waddr_4__fm (waddr[4]), - .waddr_5__fm (waddr[5]), - .ren_fm (ren), - .wen_fm (wen), - .a_0__fm (a[0]), - .a_1__fm (a[1]), - .a_2__fm (a[2]), - .a_3__fm (a[3]), - .a_4__fm (a[4]), - .a_5__fm (a[5]), - .a_6__fm (a[6]), - .b_0__fm (b[0]), - .b_1__fm (b[1]), - .b_2__fm (b[2]), - .b_3__fm (b[3]), - .b_4__fm (b[4]), - .b_5__fm (b[5]), - .b_6__fm (b[6]), - .out_q_0__fm (q_gfpga[0]), - .out_q_1__fm (q_gfpga[1]), - .out_q_2__fm (q_gfpga[2]), - .out_q_3__fm (q_gfpga[3]), - .out_q_4__fm (q_gfpga[4]), - .out_q_5__fm (q_gfpga[5]), - .out_q_6__fm (q_gfpga[6]), - .out_q_7__fm (q_gfpga[7]) - ); - - pipelined_8b_adder ref0( - .clk (clk), - .raddr (raddr), - .waddr (waddr), - .ren (ren), - .wen (wen), - .a (a), - .b (b), - .q (q_bench) - ); - - integer nb_error = 0; - integer count = 0; - integer lim_max = 64 - 1; - integer write_complete = 0; - -//----- Initialization - initial begin - clk <= 1'b0; - a <= 7'h00; - b <= 7'h00; - wen <= 1'b0; - ren <= 1'b0; - waddr <= 9'h000; - raddr <= 9'h000; - while(1) begin - #2.5 - clk <= !clk; - end - end - -//----- Input Stimulis - always@(negedge clk) begin - if(write_complete == 0) begin - wen <= 1'b1; - ren <= 1'b0; - count <= count + 1; - waddr <= waddr + 1; - if(count == lim_max) begin - write_complete = 1; - end - end else begin - wen <= $random; - ren <= $random; - waddr <= $random; - raddr <= $random; - end - a <= $random; - b <= $random; - end - - - always@(negedge clk) begin - if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin - q_flag[0] <= 1'b1; - end else begin - q_flag[0] <= 1'b0; - end - if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin - q_flag[1] <= 1'b1; - end else begin - q_flag[1] <= 1'b0; - end - if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin - q_flag[2] <= 1'b1; - end else begin - q_flag[2] <= 1'b0; - end - if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin - q_flag[3] <= 1'b1; - end else begin - q_flag[3] <= 1'b0; - end - if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin - q_flag[4] <= 1'b1; - end else begin - q_flag[4] <= 1'b0; - end - if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin - q_flag[5] <= 1'b1; - end else begin - q_flag[5] <= 1'b0; - end - if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin - q_flag[6] <= 1'b1; - end else begin - q_flag[6] <= 1'b0; - end - if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin - q_flag[7] <= 1'b1; - end else begin - q_flag[7] <= 1'b0; - end - end - - - always@(posedge q_flag[0]) begin - if(q_flag[0]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[0] at time = %t", $realtime); - end - end - always@(posedge q_flag[1]) begin - if(q_flag[1]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[1] at time = %t", $realtime); - end - end - always@(posedge q_flag[2]) begin - if(q_flag[2]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[2] at time = %t", $realtime); - end - end - always@(posedge q_flag[3]) begin - if(q_flag[3]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[3] at time = %t", $realtime); - end - end - always@(posedge q_flag[4]) begin - if(q_flag[4]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[4] at time = %t", $realtime); - end - end - always@(posedge q_flag[5]) begin - if(q_flag[5]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[5] at time = %t", $realtime); - end - end - always@(posedge q_flag[6]) begin - if(q_flag[6]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[6] at time = %t", $realtime); - end - end - always@(posedge q_flag[7]) begin - if(q_flag[7]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[7] at time = %t", $realtime); - end - end - - initial begin - $dumpfile("pipelined_8b_adder_formal.vcd"); - $dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb); - end - - initial begin - $timeformat(-9, 2, "ns", 20); - $display("Simulation start"); - #1500 // Can be changed by the user for his need - if(nb_error == 0) begin - $display("Simulation Succeed"); - end else begin - $display("Simulation Failed with %d error(s)", nb_error); - end - $finish; - end - -endmodule diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml index 95f6f8f1f..07fb84b33 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -164,7 +164,7 @@ - + diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index 0b2aa02f9..06e75d911 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -150,7 +150,7 @@ - + diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif index d63bca69d..f7ed4cb33 100644 --- a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif +++ b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif @@ -24,6 +24,7 @@ .subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03 .subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04 .subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05 + .subckt shift D=d0 clk=clk Q=reg0 .subckt shift D=reg0 clk=clk Q=reg1 .subckt shift D=reg1 clk=clk Q=reg2 diff --git a/fpga_flow/benchmarks/List/mcnc_benchmark.txt b/fpga_flow/benchmarks/List/mcnc_benchmark.txt index 799289cea..2a505ce5d 100644 --- a/fpga_flow/benchmarks/List/mcnc_benchmark.txt +++ b/fpga_flow/benchmarks/List/mcnc_benchmark.txt @@ -1,21 +1,21 @@ # Circuit Names, fixed routing channel width, -alu4/*.v, 300 -apex2/*.v, 300 -apex4/*.v, 300 -bigkey/*.v, 300 -clma/*.v, 300 -des/*.v, 300 -diffeq/*.v, 300 -dsip/*.v, 300 -elliptic/*.v, 300 -ex1010/*.v, 300 -ex5p/*.v, 300 -frisc/*.v, 300 -misex3/*.v, 300 -pdc/*.v, 300 +#alu4/*.v, 300 +#apex2/*.v, 300 +#apex4/*.v, 300 +#bigkey/*.v, 300 +#clma/*.v, 300 +#des/*.v, 300 +#diffeq/*.v, 300 +#dsip/*.v, 300 +#elliptic/*.v, 300 +#ex1010/*.v, 300 +#ex5p/*.v, 300 +#frisc/*.v, 300 +#misex3/*.v, 300 +#pdc/*.v, 300 s298/*.v, 30 -s38417/*.v, 300 -s38584/*.v, 300 -seq/*.v, 300 -spla/*.v, 300 -tseng/*.v, 300 +#s38417/*.v, 300 +#s38584/*.v, 300 +#seq/*.v, 300 +#spla/*.v, 300 +#tseng/*.v, 300 diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 293d9e551..7ef1e43af 100644 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -9,8 +9,8 @@ verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirpath="$PWD" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" # VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml" +template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" +arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_x2p_compact_routing_hierarchy --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path From 434c0d9683633cf5333d286a8b043ae6f2e7ef87 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 18 Jul 2019 13:39:47 -0600 Subject: [PATCH 002/482] hot fix on tutorial --- fpga_flow/configs/tutorial/tuto.conf | 34 ++++++++++++++-------------- fpga_flow/tuto_fpga_flow.sh | 5 ++-- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf index 85104383a..35a15f032 100644 --- a/fpga_flow/configs/tutorial/tuto.conf +++ b/fpga_flow/configs/tutorial/tuto.conf @@ -1,27 +1,27 @@ # Standard Configuration Example [dir_path] -script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys -odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe -cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit -abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc -abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 -m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net -mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 -vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial -ace_path = OPENFPGAPATHKEYWORD/ace2/ace +script_base = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/scripts/ +benchmark_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC +yosys_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys +odin2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/odin2.exe +cirkit_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/cirkit +abc_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys-abc +abc_mccl_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack1 +m2net_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/m2net +mpack2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack2 +vpr_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/results_tutorial +ace_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/ace2/ace [flow_conf] flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml +vpr_arch = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +m2net_conf = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK +power_tech_xml = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK [csv_tags] mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 7d70423cd..155f8bc74 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -12,7 +12,8 @@ architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml" architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml" ff_keyword="FFPATHKEYWORD" -ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v" +ff_template_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v" +ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff_${task_name}.v" dir_keyword="GENERATED_DIR_KEYWORD" rm -rf ${pwd_path}/results_OpenPithon @@ -26,7 +27,7 @@ perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in th perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path" -perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file +perl rewrite_path_in_file.pl -i ${ff_template_path} -o ${ff_path} -k $dir_keyword $verilog_path # Set the define path in the ff.v file # SRAM FPGA From 0854161a63cdce3920b513fd8269632036a6ab32 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 22 Jul 2019 09:42:31 -0600 Subject: [PATCH 003/482] Docker update --- Dockerfile | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/Dockerfile b/Dockerfile index 6d59a5ce6..0ed8749c0 100755 --- a/Dockerfile +++ b/Dockerfile @@ -5,12 +5,11 @@ RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default -RUN echo "git clone https://github.com/LNIS-Projects/OpenFPGA.git" >> build.sh -RUN echo "cd OpenFPGA" >> build.sh -RUN echo "mkdir -p build && cd build" >> build.sh -RUN echo "cmake .. -DCMAKE_BUILD_TYPE=debug" >> build.sh -RUN echo "make" >> build.sh -RUN chmod +x build.sh +RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git +RUN cd OpenFPGA +RUN mkdir -p build && cd build +RUN cmake .. -DCMAKE_BUILD_TYPE=debug +RUN make RUN ./build.sh -VOLUME /OpenFPGA + From 52b754f9c12dec69ad27354831e64c5dadb9590c Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 22 Jul 2019 10:14:03 -0600 Subject: [PATCH 004/482] Update --- Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 0ed8749c0..fa8c95d35 100755 --- a/Dockerfile +++ b/Dockerfile @@ -12,4 +12,4 @@ RUN cmake .. -DCMAKE_BUILD_TYPE=debug RUN make RUN ./build.sh - +WORKDIR /OpenFPGA From 7d469d8b4f692eb3857d89307d75f94e3077121c Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 22 Jul 2019 13:06:46 -0600 Subject: [PATCH 005/482] Docker try 2 --- Dockerfile | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Dockerfile b/Dockerfile index fa8c95d35..084aba126 100755 --- a/Dockerfile +++ b/Dockerfile @@ -5,11 +5,12 @@ RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default -RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git -RUN cd OpenFPGA -RUN mkdir -p build && cd build -RUN cmake .. -DCMAKE_BUILD_TYPE=debug -RUN make +RUN echo "git clone https://github.com/LNIS-Projects/OpenFPGA.git" >> build.sh +RUN echo "cd OpenFPGA" >> build.sh +RUN echo "mkdir -p build && cd build" >> build.sh +RUN echo "cmake .. -DCMAKE_BUILD_TYPE=debug" >> build.sh +RUN echo "make" >> build.sh +RUN chmod +x build.sh RUN ./build.sh WORKDIR /OpenFPGA From 8a046394f8077d4f75730342fcd0ad7421eaf0c1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 30 Jul 2019 16:47:41 -0600 Subject: [PATCH 006/482] add documentation for multi-mode configurable block support --- docs/source/arch_lang/index.rst | 2 - .../source/arch_lang/link_circuit_modules.rst | 112 ++++++++++++++---- docs/source/arch_lang/multimode_support.rst | 4 - docs/source/motivation.rst | 6 +- docs/source/z_reference.bib | 15 ++- 5 files changed, 108 insertions(+), 31 deletions(-) delete mode 100644 docs/source/arch_lang/multimode_support.rst diff --git a/docs/source/arch_lang/index.rst b/docs/source/arch_lang/index.rst index c5412a372..bafd8f6e2 100644 --- a/docs/source/arch_lang/index.rst +++ b/docs/source/arch_lang/index.rst @@ -19,6 +19,4 @@ Extended Architecture Description Language link_circuit_modules - .. multimode_support - diff --git a/docs/source/arch_lang/link_circuit_modules.rst b/docs/source/arch_lang/link_circuit_modules.rst index 29362fd9e..fc2a27256 100644 --- a/docs/source/arch_lang/link_circuit_modules.rst +++ b/docs/source/arch_lang/link_circuit_modules.rst @@ -1,6 +1,6 @@ Link circuit modules -------------------- -Each defined SPICE model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models. +Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models. SRAM ==== @@ -30,7 +30,7 @@ To link the defined circuit model of SRAM into the FPGA architecture description Example of a memory organization using memory decoders -.. note:: Currently SPICE only supports standalone memory organization. +.. note:: Currently circuit only supports standalone memory organization. .. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator. @@ -45,7 +45,7 @@ Switch Boxes ============= Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described. -To link a defined SPICE model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions. +To link a defined circuit model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions. Here is an example: @@ -59,10 +59,10 @@ Here is an example: Connection Blocks -================ +================== -To link the defined SPICE model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks. -Therefore, FPGA-SPICE requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined. +To link the defined circuit model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks. +Therefore, FPGA-circuit requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined. Here is the example: @@ -87,30 +87,98 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in * circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models. -Primitive Blocks inside Configurable Logic Blocks -================================================= +Primitive Blocks inside Multi-mode Configurable Logic Blocks +============================================================= -The architecture description employs a hierarchy of pb_types to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model. +The architecture description employs a hierarchy of ``pb_types`` to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model. +Each primitive block, i.e., the leaf ``pb_types``, should be linked to a valid circuit model, using the XML syntax ``circuit_model_name``. +The ``circuit_model_name`` should match the given name of a ``circuit_model`` defined by users. .. code-block:: xml - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -* **circuit_model_name:** should match a SPICE model defined under module_circuit_models. For the interconnection type direct, the type of the linked SPICE model should be wire. For mux, the type of linked SPICE model should be mux. For complete, the type of the linked SPICE model can be either mux or wire, depending on the case. +* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the configurable block. This is critical in modeling actual circuit designs and architecture of an FPGA. Typically, only one physical_mode should be specified for each multi-mode ``pb_type``. -* **idle_mode_name:** tell the name of the mode that the pb_type is configured to be by default. This is critical in building SPICE netlists for unused logic blocks. +* **idle_mode_name:** tell the name of the mode that the ``pb_type`` is configured to be by default. This is critical in building circuit netlists for unused logic blocks. -* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the block. This is critical in modeling actual circuit designs and architecture of an FPGA. +* **circuit_model_name:** should match a circuit model defined under ``module_circuit_models``. The ``circuit_model_name`` is mandatory for every leaf ``pb_type`` in a physical_mode ``pb_type``. For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case. + +* **mode_bits** specifies the configuration bits for the ``circuit_model`` when operating at an operating mode. The length of ``mode_bits`` should match the ``port`` size defined in ``circuit_model``. The ``mode_bits`` should be derived from circuit designs while users are responsible for its correctness. FPGA-Bitstreamm will add the ``mode_bits`` during bitstream generation. + +* **physical_pb_type_name** creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of leaf ``pb_type`` in physical mode. + +* **physical_pb_type_index_factor** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be multipled by the given factor. + +* **physical_pb_type_index_offset** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be shifted by the given factor. + +* **physical_mode_pin** creates the linke on ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match. + +* **physical_mode_pin_rotate_offset** aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. + +.. note:: + It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description. + +.. note:: + Be careful in using ``physical_pb_type_index_factor``, ``physical_pb_type_index_offset`` and ``physical_mode_pin_rotate_offset``! Try to avoid using them unless for highly complex configuration blocks with very deep hierarchy. diff --git a/docs/source/arch_lang/multimode_support.rst b/docs/source/arch_lang/multimode_support.rst deleted file mode 100644 index de12a8c1b..000000000 --- a/docs/source/arch_lang/multimode_support.rst +++ /dev/null @@ -1,4 +0,0 @@ -Modeling Physical Design of Multi-mode Configurable Logic Block Architectures -============================================================================= - -Under construction diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst index 960079773..1ac7ec214 100644 --- a/docs/source/motivation.rst +++ b/docs/source/motivation.rst @@ -15,7 +15,7 @@ In this manual, we will introduce how to use FPGA-SPICE to conduct an accurate p In the appendix, we introduce the hierarchy of the generated SPICE netlists and testbenches, to help you customize the SPICE netlists. We also attach an example of an architecture XML file for your interest. -The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015`. +The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`. FPGA-Verilog ------------ @@ -24,7 +24,9 @@ On a second note, it is becoming more and more necessary to have fast access to This motivates us to generate the Verilog code of the architecture to enable a second level of research concerning the architectures to be explored. This Verilog code encompasses the whole design and is divided into multiple sub-directories for targetted analysis or a global one. This is left to the choice of the user. -In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section +In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section. + +The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019`. FPGA-Bitstream -------------- diff --git a/docs/source/z_reference.bib b/docs/source/z_reference.bib index 6f7d2995c..4dd51edf4 100644 --- a/docs/source/z_reference.bib +++ b/docs/source/z_reference.bib @@ -38,7 +38,7 @@ month={Sept},} @article{XTang_TCAS1_2016, title={{A Study on the Programming Structures for RRAM-based FPGA Architectures}}, - author={Tang, Xifan and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, + author={X. Tang and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, volume={63}, number={4}, @@ -106,3 +106,16 @@ month={Sept},} address = {New York, NY, USA}, keywords = {CAD, FPGA, architecture}, } + +@ARTICLE{XTang_TVLSI_2019, + author={X. Tang and E. Giacomin and G. D. Micheli and P. Gaillardon}, + journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}, + title={{FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs}}, + year={2019}, + volume={27}, + number={3}, + pages={637-650}, + doi={10.1109/TVLSI.2018.2883923}, + ISSN={1063-8210}, + month={March}, +} From 0a5546e43c4bed8e67838b13ddfa313678df6218 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 5 Aug 2019 14:06:07 -0600 Subject: [PATCH 007/482] Fully functional --- .../SRC/fpga_x2p/verilog/verilog_decoder.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 8 +-- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 20 +++++--- .../SRC/fpga_x2p/verilog/verilog_routing.c | 8 +-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 50 +++++++++---------- .../verilog/verilog_top_netlist_utils.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 31 +++++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 +- 8 files changed, 70 insertions(+), 54 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c index 3cb4f9a5a..4204a24f5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c @@ -372,7 +372,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp, inv_spice_model->name, inv_spice_model->prefix, instance_tag, inv_index); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 5db74a44f..35ac9bf60 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1142,7 +1142,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print the pin names! Input and output @@ -1278,7 +1278,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in); fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Inputs */ @@ -1873,7 +1873,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } else { if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, - FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), + FALSE)) { + fprintf(fp, ",\n"); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 446897397..fb0a98ef0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -123,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -228,13 +228,17 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, } /* Call the subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ /*if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {*/ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } @@ -535,7 +539,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, formatted_subckt_prefix, cur_pb_type->name); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ @@ -610,14 +614,18 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, subckt_require_explicit_port_map = TRUE; } /* Call LUT subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* if we have to add global ports when dumping submodules of LUTs * otherwise, the port map here does not match that of submodules * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Connect inputs*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index eb736e27e..14d200038 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -836,7 +836,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1093,7 +1093,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -2975,7 +2975,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3222,7 +3222,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index c66c00f67..f3bf3d585 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -642,7 +642,7 @@ void dump_verilog_cmos_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -760,7 +760,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -863,7 +863,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -928,7 +928,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -1264,7 +1264,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map), TRUE)) { fprintf(fp, ",\n"); } if (true == use_explicit_port_map) { @@ -1307,7 +1307,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1361,7 +1361,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, spice_model.lut_intermediate_buffer->spice_model_name, nextlevel, out_idx); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1456,7 +1456,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1495,7 +1495,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1561,7 +1561,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, - my_bool_to_boolean(is_explicit_mapping))) { + my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -1715,7 +1715,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.name, mux_size); fprintf(fp, "module %s_mux(\n", spice_model.name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -1797,7 +1797,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1863,7 +1863,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, iport, ipin); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* check */ @@ -1973,7 +1973,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ @@ -2052,7 +2052,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(\n", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* inputs */ @@ -2070,7 +2070,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ @@ -2115,7 +2115,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -2199,7 +2199,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, gen_verilog_one_mux_module_name(&spice_model, mux_size)); } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -2255,7 +2255,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2318,7 +2318,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, spice_model.output_buffer->spice_model_name); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2729,7 +2729,7 @@ void dump_verilog_wire_module(FILE* fp, /* Add an output at middle point for connecting CB inputs */ fprintf(fp, "module %s (\n", wire_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n", @@ -2742,7 +2742,7 @@ void dump_verilog_wire_module(FILE* fp, fprintf(fp, "module %s (\n", wire_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "input wire %s, output wire %s);\n", @@ -2807,7 +2807,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, fprintf(fp, "//-----LUT module, verilog_model_name=%s -----\n", verilog_model->name); fprintf(fp, "module %s (", verilog_model->name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print module port list */ @@ -3058,7 +3058,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_buffer->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -3102,7 +3102,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_inverter->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index fc8e5a206..f3cc2c5b9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -934,7 +934,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, fprintf(fp, "%s ", cur_direct->spice_model->name); fprintf(fp, "%s_%d_ (", cur_direct->spice_model->prefix, cur_direct->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input: Print the source grid pin */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index f280af78d..84c28c8a3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -852,7 +852,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map) { + boolean require_explicit_port_map, + boolean is_lib_name) { int dumped_port_cnt; boolean dump_comma = FALSE; t_spice_model_port* cur_spice_model_port = NULL; @@ -901,9 +902,13 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, } else { /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { - fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); - //cur_spice_model_port->prefix); + if (TRUE == is_lib_name) { + fprintf(fp, ".%s(", + cur_spice_model_port->lib_name); + } else { + fprintf(fp, ".%s(", + cur_spice_model_port->prefix); + } } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -1861,7 +1866,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -1914,7 +1919,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -1931,7 +1936,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -2027,7 +2032,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_num_sram); /* Input*/ @@ -2067,7 +2072,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -2084,7 +2089,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -3047,7 +3052,7 @@ void dump_verilog_mem_module_port_map(FILE* fp, * Other ports are not accepted!!! */ /* 1. Global ports! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map, TRUE)) { dump_first_comma = TRUE; } @@ -3164,7 +3169,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3212,7 +3217,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, case SPICE_SRAM_STANDALONE: /* SRAM subckts*/ /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_in[%d:%d], ", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 47b780804..50859c949 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -73,7 +73,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map); + boolean require_explicit_port_map, + boolean is_lib_name); int dump_verilog_global_ports(FILE* fp, t_llist* head, boolean dump_port_type, From 7748340314b2a3c3cfa67a55355d3bf1b83d1542 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 18 Jul 2019 13:39:47 -0600 Subject: [PATCH 008/482] hot fix on tutorial --- fpga_flow/configs/tutorial/tuto.conf | 34 ++++++++++++++-------------- fpga_flow/tuto_fpga_flow.sh | 3 +-- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf index 85104383a..35a15f032 100644 --- a/fpga_flow/configs/tutorial/tuto.conf +++ b/fpga_flow/configs/tutorial/tuto.conf @@ -1,27 +1,27 @@ # Standard Configuration Example [dir_path] -script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys -odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe -cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit -abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc -abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 -m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net -mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 -vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial -ace_path = OPENFPGAPATHKEYWORD/ace2/ace +script_base = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/scripts/ +benchmark_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC +yosys_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys +odin2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/odin2.exe +cirkit_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/cirkit +abc_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys-abc +abc_mccl_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack1 +m2net_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/m2net +mpack2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack2 +vpr_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/results_tutorial +ace_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/ace2/ace [flow_conf] flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml +vpr_arch = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +m2net_conf = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK +power_tech_xml = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK [csv_tags] mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index eb0c33265..d60a1e177 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -27,8 +27,7 @@ perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in th perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path" -perl rewrite_path_in_file.pl -i $ff_template_path -o $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file - +perl rewrite_path_in_file.pl -i ${ff_template_path} -o ${ff_path} -k $dir_keyword $verilog_path # Set the define path in the ff.v file # SRAM FPGA # TT case From 33f3a991b5616651cf3ef9c7ca1090e224e67c1e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Aug 2019 14:28:35 -0600 Subject: [PATCH 009/482] init effort to start developing mux local encoders --- .../SRC/fpga_spice_include/spice_types.h | 9 ++++++--- vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.c | 2 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index 76b58c744..d5ce520c6 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -93,9 +93,10 @@ enum e_process_corner { /* For SRAM */ enum e_sram_orgz { - SPICE_SRAM_STANDALONE, - SPICE_SRAM_SCAN_CHAIN, - SPICE_SRAM_MEMORY_BANK + SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ + SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ + SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ + SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */ }; enum e_spice_accuracy_type { @@ -240,6 +241,8 @@ struct s_spice_model_port { /* Timing edeges linked to other t_model_ports */ int* num_tedges; /* 1-D Array, show number of tedges of each pin */ t_spice_model_tedge*** tedge; /* 3-D array, considering the each pin in this port, [pin_number][num_edges[iedge]] is an edge pointor */ + /* SRAM organization only applicable SRAM ports */ + enum e_sram_orgz organization; }; struct s_spice_model_wire_param { diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.c b/vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.c index 60905e871..c4ce60183 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.c @@ -120,7 +120,7 @@ ProcessWireBuffer(INOUTP ezxml_t Node, return; } -void +static void ProcessTechComp(INOUTP ezxml_t Node, OUTP struct s_arch *arch) { const char *Prop; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index c0a79aa23..b4a51652f 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -765,6 +765,26 @@ static void ProcessSpiceModelPort(ezxml_t Node, port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_circuit_model_name", FALSE)); ezxml_set_attr(Node, "inv_circuit_model_name", NULL); } + + /* Add a feature to enable/disable the configuration encoders for multiplexers */ + const char* Prop = FindProperty(Node, "organization", FALSE); + if (NULL == Prop) { + port->organization = SPICE_SRAM_STANDALONE; /* Default */ + } else if (0 == strcmp("scan-chain", Prop)) { + port->organization = SPICE_SRAM_SCAN_CHAIN; + } else if (0 == strcmp("memory-bank", Prop)) { + port->organization = SPICE_SRAM_MEMORY_BANK; + } else if (0 == strcmp("standalone", Prop)) { + port->organization = SPICE_SRAM_STANDALONE; + } else if (0 == strcmp("local-encoder", Prop)) { + port->organization = SPICE_SRAM_LOCAL_ENCODER; + } else { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Unknown property %s for SRAM organization\n", + Node->line, FindProperty(Node, "organization", FALSE)); + exit(1); + } + ezxml_set_attr(Node, "organization", NULL); return; } From fb2ca66ce9df904d503d7926f8cd579f32e4672a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Aug 2019 16:22:52 -0600 Subject: [PATCH 010/482] start adding submodules of local encoders to multiplexer --- .../fpga_spice_include/read_xml_spice_util.h | 16 ++++--- .../SRC/fpga_spice_include/spice_types.h | 3 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 4 ++ .../libarchfpga/SRC/read_xml_spice_util.c | 26 +++++------ .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 3 ++ .../SRC/fpga_x2p/verilog/verilog_submodules.c | 45 ++++++++++++++++--- .../SRC/fpga_x2p/verilog/verilog_submodules.h | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 5 ++- 8 files changed, 78 insertions(+), 28 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h index b54880fd1..9b590d947 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h @@ -5,16 +5,20 @@ #include "my_free_fwd.h" void InitSpiceMeasParams(t_spice_meas_params* meas_params); -void FreeSpiceMeasParams(t_spice_meas_params* meas_params); +void FreeSpiceMeasParams(); void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params); -void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params); +void FreeSpiceStimulateParams(); +void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params); +void FreeSpiceVariationParams(); +void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params); +void FreeSpiceMonteCarloParams(); void InitSpiceParams(t_spice_params* spice_params); -void FreeSpiceParams(t_spice_params* params); +void FreeSpiceParams(); void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist); -void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer); -void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic); +void FreeSpiceModelBuffer(); +void FreeSpiceModelPassGateLogic(); void FreeSpiceModelPort(t_spice_model_port* spice_model_port); -void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param); +void FreeSpiceModelWireParam(); void FreeSpiceModel(t_spice_model* spice_model); void InitSpice(t_spice* spice); void FreeSpice(t_spice* spice); diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index d5ce520c6..722816380 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -96,7 +96,7 @@ enum e_sram_orgz { SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ - SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */ + SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */ }; enum e_spice_accuracy_type { @@ -274,6 +274,7 @@ struct s_spice_model_mux { boolean add_const_input; int const_input_val; boolean advanced_rram_design; + boolean local_encoder; /* Define if a local encoder should be added to this mux */ }; struct s_spice_model_lut { diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index b4a51652f..89c3995a8 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -600,6 +600,10 @@ static void ProcessSpiceModelMUX(ezxml_t Node, mux_info->advanced_rram_design = GetBooleanProperty(Node,"advanced_rram_design", FALSE, FALSE); ezxml_set_attr(Node, "advanced_rram_design", NULL); + /* Specify if should use a local encoder for this multiplexer */ + mux_info->local_encoder = GetBooleanProperty(Node, "local_encoder", FALSE, FALSE); + ezxml_set_attr(Node, "local_encoder", NULL); + return; } diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.c index fe39ec379..72e4776ab 100755 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.c @@ -41,7 +41,7 @@ void InitSpiceMeasParams(t_spice_meas_params* meas_params) { return; } -void FreeSpiceMeasParams(t_spice_meas_params* meas_params) { +void FreeSpiceMeasParams() { return; } @@ -64,7 +64,7 @@ void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) { return; } -void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) { +void FreeSpiceStimulateParams() { return; } @@ -74,7 +74,7 @@ void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) mc_variation_params->num_sigma = 1; } -void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) { +void FreeSpiceVariationParams() { return; } @@ -86,7 +86,7 @@ void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) { return; } -void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) { +void FreeSpiceMonteCarloParams() { return; } @@ -110,7 +110,7 @@ void InitSpiceParams(t_spice_params* params) { return; } -void FreeSpiceParams(t_spice_params* params) { +void FreeSpiceParams() { return; } @@ -121,12 +121,12 @@ void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) { return; } -void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) { +void FreeSpiceModelBuffer() { return; } -void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) { +void FreeSpiceModelPassGateLogic() { return; } @@ -137,8 +137,7 @@ void FreeSpiceModelPort(t_spice_model_port* spice_model_port) { return; } -void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) { - +void FreeSpiceModelWireParam() { return; } @@ -152,14 +151,14 @@ void FreeSpiceModel(t_spice_model* spice_model) { spice_model->include_netlist = NULL; /* Free the buffers */ - FreeSpiceModelBuffer(spice_model->input_buffer); - FreeSpiceModelBuffer(spice_model->output_buffer); + FreeSpiceModelBuffer(); + FreeSpiceModelBuffer(); my_free(spice_model->input_buffer); my_free(spice_model->output_buffer); spice_model->input_buffer = NULL; spice_model->output_buffer = NULL; - FreeSpiceModelPassGateLogic(spice_model->pass_gate_logic); + FreeSpiceModelPassGateLogic(); my_free(spice_model->pass_gate_logic); spice_model->pass_gate_logic = NULL; @@ -173,7 +172,7 @@ void FreeSpiceModel(t_spice_model* spice_model) { /* Free wire parameters */ if (NULL != spice_model->wire_param) { - FreeSpiceModelWireParam(spice_model->wire_param); + FreeSpiceModelWireParam(); my_free(spice_model->wire_param); spice_model->wire_param = NULL; } @@ -220,6 +219,7 @@ void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) { return; } +static void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) { my_free(sram_inf_orgz->spice_model_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index a300ded24..e3e046875 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -199,6 +199,9 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, exit(1); } + /* When a local encoder is added + */ + /* Free */ return num_sram_bits; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index c66c00f67..c0eb9f7f0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -34,8 +34,11 @@ #include "verilog_pbtypes.h" #include "verilog_decoder.h" +#include "verilog_submodules.h" + /***** Subroutines *****/ +static void dump_verilog_submodule_timing(FILE* fp, t_spice_model* cur_spice_model) { int iport, ipin, iedge; @@ -85,6 +88,7 @@ void dump_verilog_submodule_timing(FILE* fp, return; } +static void dump_verilog_submodule_signal_init(FILE* fp, t_spice_model* cur_spice_model) { int iport; @@ -124,6 +128,7 @@ void dump_verilog_submodule_signal_init(FILE* fp, /* Dump a module of inverter or buffer or tapered buffer */ +static void dump_verilog_invbuf_module(FILE* fp, t_spice_model* invbuf_spice_model) { int ipin, iport, port_cnt; @@ -344,6 +349,7 @@ void dump_verilog_invbuf_module(FILE* fp, } /* Dump a module of pass-gate logic */ +static void dump_verilog_passgate_module(FILE* fp, t_spice_model* passgate_spice_model) { int iport; @@ -448,6 +454,7 @@ void dump_verilog_passgate_module(FILE* fp, } /* Dump a module of pass-gate logic */ +static void dump_verilog_gate_module(FILE* fp, t_spice_model* gate_spice_model) { int iport, ipin, jport, jpin; @@ -568,10 +575,10 @@ void dump_verilog_gate_module(FILE* fp, * 1. inverters * 2. buffers * 3. pass-gate logics */ +static void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir, int num_spice_model, - t_spice_model* spice_models, - t_syn_verilog_opts fpga_verilog_opts) { + t_spice_model* spice_models) { int imodel; char* verilog_name = my_strcat(submodule_dir, essentials_verilog_file_name); FILE* fp = NULL; @@ -616,6 +623,7 @@ void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir, } /* Dump a CMOS MUX basis module */ +static void dump_verilog_cmos_mux_one_basis_module(FILE* fp, char* mux_basis_subckt_name, int mux_size, @@ -906,6 +914,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, /* Dump a RRAM MUX basis module */ +static void dump_verilog_rram_mux_one_basis_module(FILE* fp, char* mux_basis_subckt_name, int num_input_basis_subckt, @@ -1021,6 +1030,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp, } /* Print a basis submodule */ +static void dump_verilog_mux_one_basis_module(FILE* fp, char* mux_basis_subckt_name, int mux_size, @@ -1073,6 +1083,7 @@ void dump_verilog_mux_one_basis_module(FILE* fp, /** * Dump a verilog module for the basis circuit of a MUX */ +static void dump_verilog_mux_basis_module(FILE* fp, t_spice_mux_model* spice_mux_model) { /** Act depends on the structure of MUX @@ -1165,6 +1176,7 @@ void dump_verilog_mux_basis_module(FILE* fp, return; } +static void dump_verilog_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, @@ -1195,7 +1207,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, inter_buf_loc[i] = FALSE; } if (NULL != spice_model.lut_intermediate_buffer->location_map) { - assert (spice_mux_arch.num_level - 1 == strlen(spice_model.lut_intermediate_buffer->location_map)); + assert ((size_t)spice_mux_arch.num_level - 1 == strlen(spice_model.lut_intermediate_buffer->location_map)); /* For intermediate buffers */ for (i = 0; i < spice_mux_arch.num_level - 1; i++) { if ('1' == spice_model.lut_intermediate_buffer->location_map[i]) { @@ -1404,6 +1416,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, return; } +static void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, char* mux_basis_subckt_name, char* mux_special_basis_subckt_name, @@ -1541,6 +1554,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, return; } +static void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, @@ -1622,6 +1636,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, return; } +static void dump_verilog_cmos_mux_submodule(FILE* fp, int mux_size, t_spice_model spice_model, @@ -1927,6 +1942,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, * However I use another function, because in future the internal structure may change. * We will suffer less software problems. */ +static void dump_verilog_rram_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, @@ -1995,6 +2011,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp, return; } +static void dump_verilog_rram_mux_multilevel_structure(FILE* fp, char* mux_basis_subckt_name, char* mux_special_basis_subckt_name, @@ -2095,6 +2112,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, return; } +static void dump_verilog_rram_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, @@ -2133,6 +2151,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, return; } +static void dump_verilog_rram_mux_submodule(FILE* fp, int mux_size, t_spice_model spice_model, @@ -2366,6 +2385,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, } /* Dump a memory submodule for the MUX */ +static void dump_verilog_cmos_mux_mem_submodule(FILE* fp, int mux_size, t_spice_model spice_model, @@ -2428,6 +2448,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, * 3. output ports * 4. bl/wl ports */ + /* Local Encoding support */ dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); @@ -2453,6 +2474,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, * We always dump a basis submodule for a MUX * whatever structure it is: one-level, two-level or multi-level */ +static void dump_verilog_mux_mem_module(FILE* fp, t_spice_mux_model* spice_mux_model, bool is_explicit_mapping) { @@ -2506,6 +2528,7 @@ void dump_verilog_mux_mem_module(FILE* fp, * We always dump a basis submodule for a MUX * whatever structure it is: one-level, two-level or multi-level */ +static void dump_verilog_mux_module(FILE* fp, t_spice_mux_model* spice_mux_model, bool is_explicit_mapping) { @@ -2568,7 +2591,7 @@ void dump_verilog_mux_module(FILE* fp, /*** Top-level function *****/ /* We should count how many multiplexers with different sizes are needed */ - +static void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, @@ -2696,6 +2719,7 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, return; } +static void dump_verilog_wire_module(FILE* fp, char* wire_subckt_name, t_spice_model verilog_model) { @@ -2765,6 +2789,7 @@ void dump_verilog_wire_module(FILE* fp, } /* Dump one module of a LUT */ +static void dump_verilog_submodule_one_lut(FILE* fp, t_spice_model* verilog_model, bool is_explicit_mapping) { @@ -3203,6 +3228,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, } /* Dump one module of a LUT */ +static void dump_verilog_submodule_one_mem(FILE* fp, t_spice_model* verilog_model) { int iport, ipin, pin_index; @@ -3275,6 +3301,7 @@ void dump_verilog_submodule_one_mem(FILE* fp, } /* Dump verilog top-level module for LUTs */ +static void dump_verilog_submodule_luts(char* verilog_dir, char* submodule_dir, int num_spice_model, @@ -3317,6 +3344,7 @@ void dump_verilog_submodule_luts(char* verilog_dir, } /* Dump a submodule which is a constant vdd */ +static void dump_verilog_hard_wired_vdd(FILE* fp, t_spice_model verilog_model) { int num_output_port = 0; @@ -3349,6 +3377,7 @@ void dump_verilog_hard_wired_vdd(FILE* fp, } /* Dump a submodule which is a constant vdd */ +static void dump_verilog_hard_wired_gnd(FILE* fp, t_spice_model verilog_model) { int num_output_port = 0; @@ -3380,6 +3409,7 @@ void dump_verilog_hard_wired_gnd(FILE* fp, return; } +static void dump_verilog_submodule_wires(char* verilog_dir, char* subckt_dir, int num_segments, @@ -3461,6 +3491,7 @@ void dump_verilog_submodule_wires(char* verilog_dir, return; } +static void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, @@ -3581,6 +3612,7 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, /* Print a non-global port for the template */ +static void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt, t_spice_model* cur_spice_model, enum e_spice_model_port_type port_type) { @@ -3607,6 +3639,7 @@ void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt, } /* Give a template for a user-defined module */ +static void dump_one_verilog_template_module(FILE* fp, t_spice_model* cur_spice_model) { int iport; @@ -3663,6 +3696,7 @@ void dump_one_verilog_template_module(FILE* fp, } /* Give a template of all the submodules that are user-defined */ +static void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, @@ -3714,8 +3748,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); dump_verilog_submodule_essentials(verilog_dir, submodule_dir, Arch.spice->num_spice_model, - Arch.spice->spice_models, - fpga_verilog_opts); + Arch.spice->spice_models); /* 1. MUXes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h index 155c87543..a7a384501 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h @@ -1,7 +1,9 @@ - +#ifndef VERILOG_SUBMODULES_H +#define VERILOG_SUBMODULES_H void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, t_arch Arch, t_det_routing_arch* routing_arch, t_syn_verilog_opts fpga_verilog_opts); +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index f280af78d..fa68118a1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -3029,7 +3029,10 @@ int dump_verilog_mem_module_one_port_map(FILE* fp, return cnt; } -/* Output the ports of a SRAM MUX */ +/* + * Dump the port map of a memory module + * which consist of a number of SRAMs/SCFFs etc. + */ void dump_verilog_mem_module_port_map(FILE* fp, t_spice_model* mem_model, boolean dump_port_type, From 003883b13b242cd1e80e4dbdcd6c8812d80842c3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Aug 2019 18:25:00 -0600 Subject: [PATCH 011/482] implementing the local encoders --- .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 27 +- .../vpr/SRC/fpga_x2p/verilog/verilog_global.c | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_global.h | 1 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 300 ++++++++++++------ .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 13 + .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 2 + 6 files changed, 246 insertions(+), 98 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index e3e046875..127cc0adb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -192,6 +192,18 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, } break; case SPICE_MODEL_DESIGN_CMOS: + /* When a local encoder is added, the number of sram bits will be reduced + * to N * log_2{X}, where N is the number of levels and X is the number of inputs per level + * Note that: we only apply this to one-level and multi-level multiplexers + */ + if ( (TRUE == cur_spice_model->design_tech_info.mux_info->local_encoder) + && (2 < num_input_size) ) { + if (SPICE_MODEL_STRUCTURE_ONELEVEL == cur_spice_model->design_tech_info.mux_info->structure) { + num_sram_bits = ceil(log(num_sram_bits + 1) / log(2)); + } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { + num_sram_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * ceil(log(num_sram_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level + 1) / log(2)); + } + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", @@ -199,9 +211,6 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, exit(1); } - /* When a local encoder is added - */ - /* Free */ return num_sram_bits; @@ -705,6 +714,18 @@ int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, } break; case SPICE_MODEL_DESIGN_CMOS: + /* When a local encoder is added, the number of sram bits will be reduced + * to N * log_2{X}, where N is the number of levels and X is the number of inputs per level + * Note that: we only apply this to one-level and multi-level multiplexers + */ + if ( (TRUE == cur_spice_model->design_tech_info.mux_info->local_encoder) + && (2 < num_input_size) ) { + if (SPICE_MODEL_STRUCTURE_ONELEVEL == cur_spice_model->design_tech_info.mux_info->structure) { + num_conf_bits = ceil(log(num_conf_bits + 1) / log(2)); + } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { + num_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * ceil(log(num_conf_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level + 1) / log(2)); + } + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c index ab9d935d1..7bc682ad7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c @@ -63,6 +63,7 @@ char* logic_block_verilog_file_name = "logic_blocks.v"; char* luts_verilog_file_name = "luts.v"; char* routing_verilog_file_name = "routing.v"; char* muxes_verilog_file_name = "muxes.v"; +char* local_encoder_verilog_file_name = "local_encoder.v"; char* memories_verilog_file_name = "memories.v"; char* wires_verilog_file_name = "wires.v"; char* essentials_verilog_file_name = "inv_buf_passgate.v"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h index b9183393c..4701b18de 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h @@ -55,6 +55,7 @@ extern char* logic_block_verilog_file_name; extern char* luts_verilog_file_name; extern char* routing_verilog_file_name; extern char* muxes_verilog_file_name; +extern char* local_encoder_verilog_file_name; extern char* memories_verilog_file_name; extern char* wires_verilog_file_name; extern char* essentials_verilog_file_name; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index c0eb9f7f0..19fb75551 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include /* Include vpr structs*/ #include "util.h" @@ -1770,7 +1772,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, if (2 == spice_mux_arch.num_input) { cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL; } - + /* Print internal architecture*/ switch (cur_mux_structure) { case SPICE_MODEL_STRUCTURE_TREE: @@ -1921,6 +1923,8 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, } } + /* Instanciate local encoder circuit here */ + fprintf(fp, "endmodule\n"); fprintf(fp, "//----- END CMOS MUX info: spice_model_name=%s, size=%d -----\n\n", spice_model.name, mux_size); @@ -2719,6 +2723,203 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, return; } +/*************************************************************************************** + * Create a Verilog module for a encoder with a given output size + * Inputs + * | | | | | + * +-----------+ + * / \ + * / Encoder \ + * +-----------------+ + * | | | | | | | | + * Outputs + * + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) + * We plus 1, which is all-zero condition for outputs + ***************************************************************************************/ +static +void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { + /* Make sure we have a encoder which is at least 2 ! */ + assert (2 <= num_outputs); + + /* Get the number of inputs */ + int num_inputs = ceil(log(num_outputs + 1) / log(2)); + + /* Validate the FILE handler */ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]Invalid file handler!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Print the name of encoder */ + fprintf(fp, "module %s(", generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); + fprintf(fp, "\n"); + /* Inputs */ + dump_verilog_generic_port(fp, VERILOG_PORT_INPUT, + "addr", + num_inputs - 1, 0); + fprintf(fp, ",\n"); + /* Outputs */ + dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, + "data", + num_outputs - 1, 0); + fprintf(fp, "\n);\n"); + + dump_verilog_generic_port(fp, VERILOG_PORT_REG, + "data_reg", + num_outputs - 1, 0); + fprintf(fp, ";\n"); + + /* Print the truth table of this encoder */ + /* Internal logics */ + fprintf(fp, "always@(addr, data)\n"); + fprintf(fp, "begin\n"); + fprintf(fp, "\tdata_reg = %d'b0;\n", num_outputs); + fprintf(fp, "\tif (0 < addr) begin\n"); + fprintf(fp, "\t\tdata_reg = 1'b1 << addr;\n"); + fprintf(fp, "\tend\n"); + fprintf(fp, "end\n"); + + fprintf(fp, "assign data = data_reg;\n"); + + /* Finish */ + fprintf(fp, "endmodule\n"); + + return; +} + +/* We should count how many multiplexers with different sizes are needed */ +static +void dump_verilog_submodule_local_encoders(t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* submodule_dir, + int num_switch, + t_switch_inf* switches, + t_spice* spice, + t_det_routing_arch* routing_arch, + bool is_explicit_mapping) { + + /* Statisitcs for input sizes and structures of MUXes + * used in FPGA architecture + */ + /* We have linked list whichs stores spice model information of multiplexer*/ + t_llist* muxes_head = NULL; + t_llist* temp = NULL; + FILE* fp = NULL; + char* verilog_name = my_strcat(submodule_dir, local_encoder_verilog_file_name); + int num_input_ports = 0; + t_spice_model_port** input_ports = NULL; + int num_sram_ports = 0; + t_spice_model_port** sram_ports = NULL; + + int num_input_basis = 0; + t_spice_mux_model* cur_spice_mux_model = NULL; + + /* Alloc the muxes*/ + muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); + + /* Print the muxes netlist*/ + fp = fopen(verilog_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, verilog_name); + exit(1); + } + /* Generate the descriptions*/ + dump_verilog_file_header(fp,"MUXes used in FPGA"); + + verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a vector for local encoders with different sizes */ + std::vector encoder_sizes; + /* Make sure a clean start */ + encoder_sizes.clear(); + + /* Print mux netlist one by one*/ + temp = muxes_head; + while(temp) { + assert(NULL != temp->dptr); + cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); + /* Bypass the spice models who has a user-defined subckt */ + if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) { + input_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE); + sram_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_ports, TRUE); + assert(0 != num_input_ports); + assert(0 != num_sram_ports); + /* Check the Input port size */ + if (cur_spice_mux_model->size != input_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) size(%d) unmatch with the architecture needs(%d)!\n", + __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, input_ports[0]->size,cur_spice_mux_model->size); + exit(1); + } + /* Check the SRAM port size */ + num_input_basis = determine_num_input_basis_multilevel_mux(cur_spice_mux_model->size, + cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level); + if ((num_input_basis * cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level) != sram_ports[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) SRAM size(%d) unmatch with the num of level(%d)!\n", + __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, sram_ports[0]->size, cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level*num_input_basis); + exit(1); + } + /* Move on to the next*/ + temp = temp->next; + continue; + } + /* Bypass those without local encoders */ + if (FALSE == cur_spice_mux_model->spice_model->design_tech_info.mux_info->local_encoder) { + /* Move on to the next*/ + temp = temp->next; + continue; + } + /* Reach here, we need to generate a local encoder Verilog module */ + /* Generate the spice_mux_arch */ + cur_spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); + init_spice_mux_arch(cur_spice_mux_model->spice_model, cur_spice_mux_model->spice_mux_arch, cur_spice_mux_model->size); + /* We will bypass all the TREE-LIKE multiplexers and those with 2-inputs */ + if ( (SPICE_MODEL_STRUCTURE_TREE == cur_spice_mux_model->spice_mux_arch->structure) + || ( 2 == cur_spice_mux_model->spice_mux_arch->num_input) ) { + /* Move on to the next*/ + temp = temp->next; + continue; + } + /* Find the size of local encoders */ + std::vector::iterator it = std::find(encoder_sizes.begin(), encoder_sizes.end(), cur_spice_mux_model->spice_mux_arch->num_input_basis); + /* See if a same-sized local encoder is already in the list */ + if (it == encoder_sizes.end()) { + /* Need to add to the list */ + encoder_sizes.push_back(cur_spice_mux_model->spice_mux_arch->num_input_basis); + } + /* Move on to the next*/ + temp = temp->next; + } + + + /* Print the local encoder subckt */ + for (size_t i = 0; i < encoder_sizes.size(); ++i) { + dump_verilog_mux_local_encoder_module(fp, encoder_sizes[i]); + } + + vpr_printf(TIO_MESSAGE_INFO,"Generated %d local encoders for Multiplexers.\n", + encoder_sizes.size()); + + /* Add fname to the linked list */ + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); + + /* Close the file*/ + fclose(fp); + + /* remember to free the linked list*/ + free_muxes_llist(muxes_head); + /* Free strings */ + free(verilog_name); + + return; +} + static void dump_verilog_wire_module(FILE* fp, char* wire_subckt_name, @@ -3343,72 +3544,6 @@ void dump_verilog_submodule_luts(char* verilog_dir, return; } -/* Dump a submodule which is a constant vdd */ -static -void dump_verilog_hard_wired_vdd(FILE* fp, - t_spice_model verilog_model) { - int num_output_port = 0; - t_spice_model_port** output_port = NULL; - - /* Find the input port, output port*/ - output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - - /* Asserts*/ - assert(1 == num_output_port); - assert(1 == output_port[0]->size); - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* print the spice model*/ - fprintf(fp, "//-----Hard-wired VDD module, verilog_model_name=%s -----\n", verilog_model.name); - fprintf(fp, "module %s(output wire %s);\n", verilog_model.name, output_port[0]->prefix); - /* Constant logic 1*/ - fprintf(fp, "assign %s = 1\'b1;\n", output_port[0]->prefix); - /* Finish*/ - fprintf(fp, "endmodule\n"); - fprintf(fp, "//-----END VDD module, verilog_model_name=%s -----\n", verilog_model.name); - fprintf(fp, "\n"); - return; -} - -/* Dump a submodule which is a constant vdd */ -static -void dump_verilog_hard_wired_gnd(FILE* fp, - t_spice_model verilog_model) { - int num_output_port = 0; - t_spice_model_port** output_port = NULL; - - /* Find the input port, output port*/ - output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - - /* Asserts*/ - assert(1 == num_output_port); - assert(1 == output_port[0]->size); - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* print the spice model*/ - fprintf(fp, "//-----Hard-wired GND module, verilog_model_name=%s -----\n", verilog_model.name); - fprintf(fp, "module %s(output wire %s);\n", verilog_model.name, output_port[0]->prefix); - /* Constant logic 1*/ - fprintf(fp, "assign %s = 1\'b0;\n", output_port[0]->prefix); - /* Finish*/ - fprintf(fp, "endmodule\n"); - fprintf(fp, "//-----END GND module, verilog_model_name=%s -----\n", verilog_model.name); - fprintf(fp, "\n"); - return; -} - static void dump_verilog_submodule_wires(char* verilog_dir, char* subckt_dir, @@ -3610,34 +3745,6 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, return; } - -/* Print a non-global port for the template */ -static -void dump_one_verilog_template_module_one_port(FILE* fp, int* cnt, - t_spice_model* cur_spice_model, - enum e_spice_model_port_type port_type) { - int iport; - int num_port_to_dump= 0; - t_spice_model_port** port_to_dump = NULL; - - port_to_dump = find_spice_model_ports(cur_spice_model, port_type, &num_port_to_dump, TRUE); - for (iport = 0; iport < num_port_to_dump; iport++) { - if (0 < *cnt) { - fprintf(fp, ",\n"); - } - dump_verilog_generic_port(fp, - convert_spice_model_port_type_to_verilog_port_type(port_to_dump[iport]->type), - port_to_dump[iport]->lib_name, - port_to_dump[iport]->size - 1, 0); - (*cnt)++; - } - - /* Free */ - my_free(port_to_dump); - - return; -} - /* Give a template for a user-defined module */ static void dump_one_verilog_template_module(FILE* fp, @@ -3754,6 +3861,9 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); + dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, + switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); /* 2. LUTes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index fa68118a1..65a708892 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2915,6 +2915,19 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, return subckt_name; } +/* Generate the subckt name for a decoder submodule */ +char* generate_verilog_decoder_subckt_name(int addr_len, int data_len) { + char* subckt_name = NULL; + + subckt_name = (char*)my_malloc(sizeof(char)*(strlen("decoder") + + strlen(my_itoa(addr_len)) + 1 + + strlen(my_itoa(data_len)) + 1)); + sprintf(subckt_name, "%s%d_%d", + "decoder", addr_len, data_len); + + return subckt_name; +} + /* Generate the subckt name for a MUX module/submodule */ char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model, int mux_size, char* postfix) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 47b780804..0a10d29a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -221,6 +221,8 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, t_spice_model* mem_model, char* postfix); +char* generate_verilog_decoder_subckt_name(int addr_len, int data_len); + char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model, int mux_size, char* postfix); From 557b1af6339e072ee84293c0c5e437a0ee1c8004 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Aug 2019 21:04:57 -0600 Subject: [PATCH 012/482] add Verilog generation for local encoders, bitstream upgrade TODO --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 117 +++++++++++++++--- 1 file changed, 102 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 19fb75551..2343ce128 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1452,6 +1452,16 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, } fprintf(fp, "wire [%d:%d] mux2_l%d_in; \n", 0, 0, 0); + + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + /* Print local wires for local encoders */ + fprintf(fp, "wire [%d:0] %s_data;\n", + spice_mux_arch.num_level * spice_mux_arch.num_input_basis - 1, + sram_port[0]->prefix); + fprintf(fp, "wire [%d:0] %s_data_inv;\n", + spice_mux_arch.num_level * spice_mux_arch.num_input_basis - 1, + sram_port[0]->prefix); + } for (i = 0; i < spice_mux_arch.num_level; i++) { level = spice_mux_arch.num_level - i; @@ -1459,6 +1469,24 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, sram_idx = nextlevel * spice_mux_arch.num_input_basis; /* Check */ assert(nextlevel > -1); + /* Determine the number of input of this basis */ + cur_num_input_basis = spice_mux_arch.num_input_basis; + /* Instanciate local encoder circuit here */ + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + /* Get the number of inputs */ + int num_outputs = spice_mux_arch.num_input - 1; + int num_inputs = ceil(log(num_outputs + 1) / log(2)); + /* Find the decoder name */ + fprintf(fp, "%s %s_0_ (", + generate_verilog_decoder_subckt_name(num_inputs, num_outputs), + generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); + if (true == is_explicit_mapping) { + fprintf(fp, ".addr(%s), .data(%s_data[%d:%d]), .data_inv(%s_data_inv[%d:%d]) );\n", + sram_port[0]->prefix, + sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx, + sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx); + } + } /* Print basis muxQto1 for each level*/ for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j + cur_num_input_basis) { /* output index */ @@ -1489,15 +1517,25 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, } else { fprintf(fp, ", "); } - fprintf(fp, "%s[%d:%d]", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + fprintf(fp, "%s_data[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } else { + fprintf(fp, "%s[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } if (true == is_explicit_mapping) { fprintf(fp, "), .mem_inv("); } else { fprintf(fp, ", "); } - fprintf(fp, "%s_inv[%d:%d]", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + fprintf(fp, "%s_data_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } else { + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } if (true == is_explicit_mapping) { fprintf(fp, ")"); } @@ -1529,15 +1567,25 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, } else { fprintf(fp, ", "); } - fprintf(fp, "%s[%d:%d]", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + fprintf(fp, "%s_data[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } else { + fprintf(fp, "%s[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } if (true == is_explicit_mapping) { fprintf(fp, "), .mem_inv("); } else { fprintf(fp, ", "); } - fprintf(fp, "%s_inv[%d:%d]", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + fprintf(fp, "%s_data_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } else { + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + } if (true == is_explicit_mapping) { fprintf(fp, ")"); } @@ -1619,21 +1667,57 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, if (true == is_explicit_mapping) { fprintf(fp, ".mem("); } - fprintf(fp, "%s[0:%d]", - sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */ + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + fprintf(fp, "%s_data[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */ + } else { + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */ + } if (true == is_explicit_mapping) { fprintf(fp, "), .mem_inv("); } else { fprintf(fp, ", "); } - fprintf(fp, "%s_inv[0:%d]", - sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */ + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + fprintf(fp, "%s_data_inv[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */ + } else { + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */ + } if (true == is_explicit_mapping) { fprintf(fp, ")"); } } fprintf(fp, "\n"); fprintf(fp, ");\n"); + + if (2 < spice_mux_arch.num_input) { + /* Instanciate local encoder circuit here */ + if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { + /* Get the number of inputs */ + int num_outputs = spice_mux_arch.num_input - 1; + int num_inputs = ceil(log(num_outputs + 1) / log(2)); + /* Print local wires for local encoders */ + fprintf(fp, "wire [%d:0] %s_data;\n", + spice_mux_arch.num_input - 1, + sram_port[0]->prefix); + fprintf(fp, "wire [%d:0] %s_data_inv;\n", + spice_mux_arch.num_input - 1, + sram_port[0]->prefix); + /* Find the decoder name */ + fprintf(fp, "%s %s_0_ (", + generate_verilog_decoder_subckt_name(num_inputs, num_outputs), + generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); + if (true == is_explicit_mapping) { + fprintf(fp, ".addr(%s), .data(%s_data), .data_inv(%s_data_inv) );\n", + sram_port[0]->prefix, + sram_port[0]->prefix, + sram_port[0]->prefix); + } + } + } return; } @@ -1923,9 +2007,6 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, } } - /* Instanciate local encoder circuit here */ - - fprintf(fp, "endmodule\n"); fprintf(fp, "//----- END CMOS MUX info: spice_model_name=%s, size=%d -----\n\n", spice_model.name, mux_size); fprintf(fp, "\n"); @@ -2767,6 +2848,10 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, "data", num_outputs - 1, 0); + fprintf(fp, ",\n"); + dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, + "data_inv", + num_outputs - 1, 0); fprintf(fp, "\n);\n"); dump_verilog_generic_port(fp, VERILOG_PORT_REG, @@ -2785,6 +2870,8 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { fprintf(fp, "end\n"); fprintf(fp, "assign data = data_reg;\n"); + fprintf(fp, "assign data_inv = ~data;\n"); + /* Finish */ fprintf(fp, "endmodule\n"); From 386bddacd1bb67231d7bfd9ebff57608b174a312 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 2 Aug 2019 22:55:21 -0600 Subject: [PATCH 013/482] updated bitstream generator for local encoders --- .../SRC/fpga_x2p/base/fpga_x2p_mux_utils.c | 108 +++++++++++++++--- .../SRC/fpga_x2p/base/fpga_x2p_mux_utils.h | 8 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 20 ++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 2 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 7 +- 5 files changed, 121 insertions(+), 24 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c index 9ae14af6c..54c554342 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c @@ -187,6 +187,26 @@ int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, return ret; } +/*************************************************************************************** + * Find the number of inputs for a encoder with a given output size + * Inputs + * | | | | | + * +-----------+ + * / \ + * / Encoder \ + * +-----------------+ + * | | | | | | | | + * Outputs + * + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) + * We plus 1, which is all-zero condition for outputs + ***************************************************************************************/ +int determine_mux_local_encoder_num_inputs(int num_outputs) { + return ceil(log(num_outputs + 1) / log(2)); +} + /* Decoding a one-level MUX: * SPICE/Verilog model declare the sram port sequence as follows: * sel0, sel1, ... , selN, @@ -198,24 +218,36 @@ int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, */ int* decode_onelevel_mux_sram_bits(int fan_in, int mux_level, - int path_id) { - int* ret = (int*)my_malloc(sizeof(int)*fan_in); - int i; - + int path_id, + boolean use_local_encoder) { /* Check */ assert( (!(0 > path_id)) && (path_id < fan_in) ); - for (i = 0; i < fan_in; i++) { - ret[i] = 0; + /* If we use local encoder, we have a different number of sram bits! */ + int num_sram_bits = fan_in; + if (TRUE == use_local_encoder) { + num_sram_bits = determine_mux_local_encoder_num_inputs(fan_in); + } + /* Allocate sram_bits array to return */ + int* ret = (int*)my_calloc(num_sram_bits, sizeof(int)); + + if (TRUE == use_local_encoder) { + /* The encoder will convert the path_id to a binary number + * For example: when path_id=3, using a 4-input encoder + * the sram_bits will be the 4-digit binary number of 3: 0011 + */ + ret = my_itobin_int(path_id, num_sram_bits); + } else { + ret[path_id] = 1; } - ret[path_id] = 1; /* ret[fan_in - 1 - path_id] = 1; */ return ret; } int* decode_multilevel_mux_sram_bits(int fan_in, int mux_level, - int path_id) { + int path_id, + boolean use_local_encoder) { int* ret = NULL; int i, j, path_differ, temp; int num_last_level_input, active_mux_level, active_path_id, num_input_basis; @@ -228,7 +260,7 @@ int* decode_multilevel_mux_sram_bits(int fan_in, switch (mux_level) { case 1: /* Special: 1-level should be have special care !!! */ - return decode_onelevel_mux_sram_bits(fan_in, mux_level, path_id); + return decode_onelevel_mux_sram_bits(fan_in, mux_level, path_id, use_local_encoder); default: assert(1 < mux_level); num_input_basis = determine_num_input_basis_multilevel_mux(fan_in, mux_level); @@ -258,12 +290,7 @@ int* decode_multilevel_mux_sram_bits(int fan_in, } else { assert(num_last_level_input == fan_in); } - /* - if ((41 == fan_in) && (40 == path_id)) { - printf("num_last_level_input=%d, active_mux_lvl=%d, active_path_id=%d\n", - num_last_level_input, active_mux_level, active_path_id); - } - */ + temp = active_path_id; for (i = mux_level - 1; i > (mux_level - active_mux_level - 1); i--) { for (j = 0; j < num_input_basis; j++) { @@ -283,8 +310,49 @@ int* decode_multilevel_mux_sram_bits(int fan_in, /* Check */ assert(0 == temp); - - return ret; + + /* If we do not use a local encoder, these are the sram bits we want */ + if (FALSE == use_local_encoder) { + return ret; + } + + /* If we use local encoder, we have a different number of sram bits! */ + int num_bits_per_level = determine_mux_local_encoder_num_inputs(num_input_basis); + int num_sram_bits = mux_level * num_bits_per_level; + /* Allocate sram_bits array to return */ + int* encoded_ret = (int*)my_calloc(num_sram_bits, sizeof(int)); + + /* Walk through each level and find the path_id and encode it */ + for (int ilvl = 0; ilvl < mux_level; ++ilvl) { + int start_idx = num_input_basis * ilvl; + int end_idx = num_input_basis * (ilvl + 1) - 1; + int encoded_path_id = 0; + int checker = 0; + for (int idx = start_idx; idx < end_idx; ++idx) { + if ('1' == ret[idx]) { + checker++; + encoded_path_id = idx; + } + } + /* There should be at most one '1' */ + assert( (0 == checker) || (1 == checker)); + /* The encoder will convert the path_id to a binary number + * For example: when path_id=3, using a 4-input encoder + * the sram_bits will be the 4-digit binary number of 3: 0011 + */ + int* tmp_bits = my_itobin_int(path_id, num_bits_per_level); + /* Copy tmp_bits to encoded bits */ + for (int idx = 0; idx < num_bits_per_level; ++idx) { + encoded_ret[idx + ilvl* num_bits_per_level] = tmp_bits[idx]; + } + /* Free */ + my_free(tmp_bits); + } + + /* Free ret */ + my_free(ret); + + return encoded_ret; } /* Decode the configuration to sram_bits @@ -428,12 +496,14 @@ void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model, case SPICE_MODEL_STRUCTURE_ONELEVEL: (*mux_level) = 1; (*bit_len) = num_mux_input; - (*conf_bits) = decode_onelevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id); + (*conf_bits) = decode_onelevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id, + mux_spice_model->design_tech_info.mux_info->local_encoder); break; case SPICE_MODEL_STRUCTURE_MULTILEVEL: (*mux_level) = mux_spice_model->design_tech_info.mux_info->mux_num_level; (*bit_len) = determine_num_input_basis_multilevel_mux(num_mux_input, (*mux_level)) * (*mux_level); - (*conf_bits) = decode_multilevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id); + (*conf_bits) = decode_multilevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id, + mux_spice_model->design_tech_info.mux_info->local_encoder); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for mux_spice_model (%s)!\n", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h index 598a1ece4..6c8c6a4b8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h @@ -17,13 +17,17 @@ int tree_mux_last_level_input_num(int num_level, int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, int mux_size); +int determine_mux_local_encoder_num_inputs(int num_outputs); + int* decode_onelevel_mux_sram_bits(int fan_in, int mux_level, - int path_id); + int path_id, + boolean use_local_encoder); int* decode_multilevel_mux_sram_bits(int fan_in, int mux_level, - int path_id); + int path_id, + boolean use_local_encoder); int* decode_tree_mux_sram_bits(int fan_in, int mux_level, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 7304a25b6..8527cf43f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -576,6 +576,26 @@ t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, return ret; } +/* Converter an integer to a binary string */ +int* my_itobin_int(int in_int, int bin_len) { + int* ret = (int*) my_calloc (bin_len, sizeof(int)); + int i, temp; + + /* Make sure we do not have any overflow! */ + assert ( (-1 < in_int) && (in_int < pow(2., bin_len)) ); + + temp = in_int; + for (i = 0; i < bin_len; i++) { + if (1 == temp % 2) { + ret[i] = 1; + } + temp = temp / 2; + } + + return ret; +} + + /* Converter an integer to a binary string */ char* my_itobin(int in_int, int bin_len) { char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 2f28cbf2a..b488456e6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -60,6 +60,8 @@ t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, char* my_itobin(int in_int, int bin_len); +int* my_itobin_int(int in_int, int bin_len); + char* my_itoa(int input); char* fpga_spice_create_one_subckt_filename(const char* file_name_prefix, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 2343ce128..93cb38e4b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1475,7 +1475,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { /* Get the number of inputs */ int num_outputs = spice_mux_arch.num_input - 1; - int num_inputs = ceil(log(num_outputs + 1) / log(2)); + int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); /* Find the decoder name */ fprintf(fp, "%s %s_0_ (", generate_verilog_decoder_subckt_name(num_inputs, num_outputs), @@ -1698,7 +1698,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { /* Get the number of inputs */ int num_outputs = spice_mux_arch.num_input - 1; - int num_inputs = ceil(log(num_outputs + 1) / log(2)); + int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); + /* Print local wires for local encoders */ fprintf(fp, "wire [%d:0] %s_data;\n", spice_mux_arch.num_input - 1, @@ -2826,7 +2827,7 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { assert (2 <= num_outputs); /* Get the number of inputs */ - int num_inputs = ceil(log(num_outputs + 1) / log(2)); + int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); /* Validate the FILE handler */ if (NULL == fp) { From c08c136844c5cd50befd54cc4b8013a08c9090ca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 3 Aug 2019 16:07:59 -0600 Subject: [PATCH 014/482] set a working range for the encoders --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 93cb38e4b..a59cfce0d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2848,25 +2848,41 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { /* Outputs */ dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, "data", - num_outputs - 1, 0); + 0, num_outputs - 1); fprintf(fp, ",\n"); dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, "data_inv", - num_outputs - 1, 0); + 0, num_outputs - 1); fprintf(fp, "\n);\n"); dump_verilog_generic_port(fp, VERILOG_PORT_REG, "data_reg", - num_outputs - 1, 0); + 0, num_outputs - 1); fprintf(fp, ";\n"); /* Print the truth table of this encoder */ /* Internal logics */ + /* We use a magic number -1 as the addr=1 should be mapped to ...1 + * Otherwise addr will map addr=1 to ..10 + * Note that there should be a range for the shift operators + * We should narrow the encoding to be applied to a given set of data + * This will lead to that any addr which falls out of the op code of data + * will give a all-zero code + * For example: + * data is 5-bit while addr is 3-bit + * data=8'b0_0000 is reserved by addr=3'b000; + * data=8'b0_0001 will be encoded to addr=3'b001; + * data=8'b0_0010 will be encoded to addr=3'b010; + * data=8'b0_0100 will be encoded to addr=3'b011; + * data=8'b0_1000 will be encoded to addr=3'b100; + * data=8'b1_0000 will be encoded to addr=3'b101; + * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000; + */ fprintf(fp, "always@(addr, data)\n"); fprintf(fp, "begin\n"); fprintf(fp, "\tdata_reg = %d'b0;\n", num_outputs); - fprintf(fp, "\tif (0 < addr) begin\n"); - fprintf(fp, "\t\tdata_reg = 1'b1 << addr;\n"); + fprintf(fp, "\tif ((0 < addr) && (addr < %d) ) begin\n", num_outputs); + fprintf(fp, "\t\tdata_reg = 1'b1 << (addr - 1)\n"); fprintf(fp, "\tend\n"); fprintf(fp, "end\n"); From 890ff0562874138b25a8be679eb5d9cf6283e829 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 3 Aug 2019 16:29:21 -0600 Subject: [PATCH 015/482] bug fixing and get ready for testing --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 1 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 17 ++++++++++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 4 ++-- 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c index 54c554342..1dd1b1af5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c @@ -340,7 +340,7 @@ int* decode_multilevel_mux_sram_bits(int fan_in, * For example: when path_id=3, using a 4-input encoder * the sram_bits will be the 4-digit binary number of 3: 0011 */ - int* tmp_bits = my_itobin_int(path_id, num_bits_per_level); + int* tmp_bits = my_itobin_int(encoded_path_id, num_bits_per_level); /* Copy tmp_bits to encoded bits */ for (int idx = 0; idx < num_bits_per_level; ++idx) { encoded_ret[idx + ilvl* num_bits_per_level] = tmp_bits[idx]; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 8527cf43f..c30ac6926 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -582,6 +582,7 @@ int* my_itobin_int(int in_int, int bin_len) { int i, temp; /* Make sure we do not have any overflow! */ + if (! ( (-1 < in_int) && (in_int < pow(2., bin_len)) ) ) assert ( (-1 < in_int) && (in_int < pow(2., bin_len)) ); temp = in_int; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index a59cfce0d..b0606718a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1485,6 +1485,11 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, sram_port[0]->prefix, sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx, sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx); + } else { + fprintf(fp, "%s, %s_data[%d:%d], %s_data_inv[%d:%d]);\n", + sram_port[0]->prefix, + sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx, + sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx); } } /* Print basis muxQto1 for each level*/ @@ -1716,6 +1721,11 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, sram_port[0]->prefix, sram_port[0]->prefix, sram_port[0]->prefix); + } else { + fprintf(fp, "%s, %s_data, %s_data_inv);\n", + sram_port[0]->prefix, + sram_port[0]->prefix, + sram_port[0]->prefix); } } } @@ -2838,12 +2848,14 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { } /* Print the name of encoder */ + fprintf(fp, "//-------- Local Decoder convert %d-bit addr to %d-bit data \n", + num_inputs, num_outputs); fprintf(fp, "module %s(", generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); fprintf(fp, "\n"); /* Inputs */ dump_verilog_generic_port(fp, VERILOG_PORT_INPUT, "addr", - num_inputs - 1, 0); + 0, num_inputs - 1); fprintf(fp, ",\n"); /* Outputs */ dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, @@ -2893,6 +2905,9 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { /* Finish */ fprintf(fp, "endmodule\n"); + fprintf(fp, "//-------- END Local Decoder convert %d-bit addr to %d-bit data \n\n", + num_inputs, num_outputs); + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 65a708892..947bee272 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2920,9 +2920,9 @@ char* generate_verilog_decoder_subckt_name(int addr_len, int data_len) { char* subckt_name = NULL; subckt_name = (char*)my_malloc(sizeof(char)*(strlen("decoder") - + strlen(my_itoa(addr_len)) + 1 + + strlen(my_itoa(addr_len)) + 2 + strlen(my_itoa(data_len)) + 1)); - sprintf(subckt_name, "%s%d_%d", + sprintf(subckt_name, "%s%dto%d", "decoder", addr_len, data_len); return subckt_name; From 3a490fdd5953b85bc404e174dd6e2034814187ac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 3 Aug 2019 16:50:35 -0600 Subject: [PATCH 016/482] bug fixing on the port map alignment --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index b0606718a..78ef46f0d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1474,22 +1474,23 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Instanciate local encoder circuit here */ if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { /* Get the number of inputs */ - int num_outputs = spice_mux_arch.num_input - 1; + int num_outputs = cur_num_input_basis; int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); /* Find the decoder name */ - fprintf(fp, "%s %s_0_ (", + fprintf(fp, "%s %s_%d_ (", generate_verilog_decoder_subckt_name(num_inputs, num_outputs), - generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); + generate_verilog_decoder_subckt_name(num_inputs, num_outputs), + i); if (true == is_explicit_mapping) { - fprintf(fp, ".addr(%s), .data(%s_data[%d:%d]), .data_inv(%s_data_inv[%d:%d]) );\n", - sram_port[0]->prefix, - sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx, - sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx); + fprintf(fp, ".addr(%s[%d:%d]), .data(%s_data[%d:%d]), .data_inv(%s_data_inv[%d:%d]) );\n", + sram_port[0]->prefix, nextlevel * num_inputs, (nextlevel + 1) * num_inputs - 1, + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis - 1, + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis - 1); } else { - fprintf(fp, "%s, %s_data[%d:%d], %s_data_inv[%d:%d]);\n", - sram_port[0]->prefix, - sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx, - sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx); + fprintf(fp, "%s[%d:%d], %s_data[%d:%d], %s_data_inv[%d:%d]);\n", + sram_port[0]->prefix, nextlevel * num_inputs, (nextlevel + 1) * num_inputs - 1, + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis - 1, + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis - 1); } } /* Print basis muxQto1 for each level*/ From 7603850d724505334c2fbf92a76d01698472fbc6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 3 Aug 2019 17:51:06 -0600 Subject: [PATCH 017/482] complete documentation for new features --- docs/Makefile | 2 +- .../arch_lang/circuit_model_examples.rst | 75 ++++++++++--------- docs/source/arch_lang/circuit_modules.rst | 24 +++--- 3 files changed, 54 insertions(+), 47 deletions(-) diff --git a/docs/Makefile b/docs/Makefile index 7f7d4d5a3..9d20886ea 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -3,7 +3,7 @@ # You can set these variables from the command line. SPHINXOPTS = -SPHINXBUILD = sphinx-build-3.6 +SPHINXBUILD = sphinx-build SOURCEDIR = source BUILDDIR = build diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst index dd86441e1..72b3eccd9 100644 --- a/docs/source/arch_lang/circuit_model_examples.rst +++ b/docs/source/arch_lang/circuit_model_examples.rst @@ -13,7 +13,7 @@ Inverters and Buffers -.. note:: customized SPICE netlists are not currently supported for inverters and buffers. +.. note:: customized Verilog/SPICE netlists are not currently supported for inverters and buffers. * design_technology: @@ -128,7 +128,7 @@ Pass-gate Logic -.. note:: customized SPICE netlists are not currently supported for pass-gate logics. +.. note:: customized Verilog/SPICE netlists are not currently supported for pass-gate logics. * design_technology: @@ -209,9 +209,9 @@ SRAMs -.. note:: The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-SPICE requires users to provide their customized SRAM SPICE/Verilog netlists. A sample SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined. +.. note:: The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized SRAM Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-Verilog/SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined. -.. note:: The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. +.. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. .. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input. @@ -230,9 +230,9 @@ Logic gates .. note:: The circuit model in the type of gate aims to support direct mapping to standard cells or customized cells provided by technology vendors or users. -.. note:: The logic functionality of a gate can be defined through the XML keyword topology. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported. +.. note:: The logic functionality of a gate can be defined through the XML keyword ``topology``. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported. -.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword dump_explicit_port_map to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword lib_name. +.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword ``dump_explicit_port_map`` to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword ``lib_name``. Multiplexers ------------ @@ -240,8 +240,7 @@ Multiplexers .. code-block:: xml - + @@ -250,14 +249,18 @@ Multiplexers -.. note:: customized SPICE netlists are not currently supported for multiplexers. +.. note:: customized Verilog/SPICE netlists are not currently supported for multiplexers. * design_technology: - * **structure:** can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If *multi-level* the following parameter is required: + * **structure:** can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required: * **num_level:** specify the number of levels when multi-level structure is selected, only. - + + * **add_const_input:** can be [true|false]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead. + * **const_input_val:** specify the constant value, to which the extra input will be connected. This syntax is only valid when the ``add_const_input`` is set to true. + + * **local_encoder:** can be [true|false]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead. * **prog_transistor_size:** valid only when the type of design technology is rram. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node . @@ -269,6 +272,8 @@ Multiplexers * port: for a multiplexer, the three types of ports, input, output and sram should be defined. +.. note:: For tree-like multiplexers, they can be built with standard cell MUX2. To enable this, users should define a ``circuit_model``, which describes a 2-input multiplexer (See details and examples in how to define a logic gate using ``circuit_model``. In this case, the ``circuit_model_name`` in the ``pass_gate_logic`` should be the name of MUX2 ``circuit_model``. + **Mux 1 level example** :numref:`fig_mux1` illustrates an example of multiplexer modelling, which consists of input/output buffers and a transmission-gate-based tree structure. @@ -349,9 +354,9 @@ Look-Up Tables -.. note:: The SPICE netlists of LUT can be auto-generated or customized. +.. note:: The Verilog/SPICE netlists of LUT can be auto-generated or customized. The auto-generated LUTs are based on a tree-like multiplexer, whose gates of the transistors are used as the inputs of LUTs and the drains/sources of the transistors are used for configurable memories (SRAMs). - The LUT provided in customized SPICE netlist should have the same decoding methodology as the traditional LUT. + The LUT provided in customized Verilog/SPICE netlist should have the same decoding methodology as the traditional LUT. Additional design parameters for LUTs: @@ -369,7 +374,7 @@ Instructions of defining design parameters: * **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers. -* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask. +* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask. * **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the tri_state_map. @@ -400,7 +405,7 @@ The code describing this LUT is: **This example shows:** - * The difference between *input_buffer* and *lut_input_buffer* and that they are independent. + * The difference between ``input_buffer`` and ``lut_input_buffer`` and that they are independent. * How each blocks is defined Flip-Flops @@ -417,17 +422,17 @@ Flip-Flops -.. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-SPICE requires users to provide their customized FF SPICE/Verilog netlists. A sample SPICE netlist of FF can be found in the directory SpiceNetlists in the released package. +.. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package. - The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. + The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. - FPGA-SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1. + FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1. Instructions of defining design parameters: * **circuit_model type:** can be ff or scff. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop -* **port:** three types of ports (input, output and clock) should be defined. If the user provides a customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. +* **port:** three types of ports (input, output and clock) should be defined. If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. **FF example** @@ -454,9 +459,9 @@ The code describing this FF is: **This example shows:** - * Circuit model type as ff - * The verilog netlist file associated to this component *ff.v* - * 3 ports, *Set*, *Reset* and *clk*, defined as global + * Circuit model type as ``ff`` + * The verilog netlist file associated to this component ``ff.v`` + * 3 ports, ``Set``, ``Reset`` and ``clk``, defined as global **SCFF example** @@ -481,9 +486,9 @@ The code describing this FF is: **This example shows:** - * Circuit model type as scff - * The verilog netlist file associated to this component *scff.v* - * 1 port, *clk*, defined as global + * Circuit model type as ``scff`` + * The verilog netlist file associated to this component ``scff.v`` + * 1 port, ``clk``, defined as global Hard Logics ----------- @@ -501,18 +506,18 @@ Hard Logics .. note:: Hard logics are defined for non-configurable resources in FPGA architectures, such as adders, multipliers and RAM blocks. Their circuit designs are highly dependent on the technology node and well optimized by engineers. As more functional units are included in FPGA architecture, it is impossible to auto-generate these functional units [3]. - Therefore, FPGA-SPICE requires users to provide their customized SPICE netlists. A sample SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package. + Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE netlists. A sample Verilog/SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package. - The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. + The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. Instructions of defining design parameters: -* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. +* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. Routing Wire Segments --------------------- -FPGA-SPICE provides two types of SPICE models for the wire segments in FPGA architecture: +FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segments in FPGA architecture: * One type is called **wire**, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively * The other type is called **chan_wire**, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point. @@ -528,15 +533,15 @@ FPGA-SPICE provides two types of SPICE models for the wire segments in FPGA arch -.. note:: FPGA-SPICE can auto-generate the SPICE model for wires while also allows users to provide their customized SPICE netlists. +.. note:: FPGA-Verilog/SPICE can auto-generate the Verilog/SPICE model for wires while also allows users to provide their customized Verilog/SPICE netlists. The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. Instructions of defining design parameters: -* **type:** can be [wire|chan_wire]. The SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing. +* **type:** can be [wire|chan_wire]. The Verilog/SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing. -* **port:** two types of ports (input and output) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. +* **port:** two types of ports (input and output) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. * **wire_param:** @@ -570,7 +575,7 @@ The code describing this wire is: **This example shows** * How to use the *wire_param* for a π-type RC wire model - * How to use this circuit_model to auto-generate the SPICE netlist + * How to use this circuit_model to auto-generate the Verilog/SPICE netlist I/O pads -------- @@ -588,13 +593,13 @@ I/O pads .. note:: The circuit designs of I/O pads are highly dependent on the technology node and well optimized by engineers. - Therefore, FPGA-SPICE requires users to provide their customized SPICE/Verilog netlists. A sample SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package. + Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package. The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. Instructions of defining design parameters: -* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. +* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. **IO-pad example** diff --git a/docs/source/arch_lang/circuit_modules.rst b/docs/source/arch_lang/circuit_modules.rst index 7076112df..b4ab2b201 100644 --- a/docs/source/arch_lang/circuit_modules.rst +++ b/docs/source/arch_lang/circuit_modules.rst @@ -1,10 +1,10 @@ Define Circuit-level Modules ============================ -To support FPGA SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks. +To support FPGA Verilog/SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks. The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language. -For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the SPICE netlist of the module is either auto-generated or user-defined. +For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the Verilog/SPICE netlist of the module is either auto-generated or user-defined. Define circuit_models --------------------- @@ -22,21 +22,21 @@ Define circuit_models * **circuit_model**: the child node defining transistor-level modeling parameters. - * **type**: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | scff | hard_logic | iopad ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-SPICE can auto-generate SPICE netlists. For the rest, FPGA-SPICE requires a user-defined SPICE netlist. + * **type**: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | scff | hard_logic | iopad ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-Verilog/SPICE can auto-generate Verilog/SPICE netlists. For the rest, FPGA-Verilog/SPICE requires a user-defined Verilog/SPICE netlist. - * **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in SPICE netlists. Note that for a customized SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized SPICE netlist. FPGA-SPICE will check if the given name is conflicted with any reserved words. + * **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in Verilog/SPICE netlists. Note that for a customized Verilog/SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized Verilog/SPICE netlist. FPGA-Verilog/SPICE will check if the given name is conflicted with any reserved words. - * **prefix**: specify the name of the circuit_model to shown in the auto-generated SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique. + * **prefix**: specify the name of the circuit_model to shown in the auto-generated Verilog/SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique. - * **is_default**: can be [1|0], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default. + * **is_default**: can be [1|0], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-Verilog/SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default. - * **spice_netlist**: specify the path and file name of a customized SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. + * **spice_netlist**: specify the path and file name of a customized Verilog/SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. - * **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. + * **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. * **dump_structural_verilog**: when the value of this keyword is set to be true, Verilog generator will output gate-level netlists of this module, instead of behavior-level. Gate-level netlists bring more opportunities in layout-level optimization while behavior-level is more suitable for high-speed formal verification and easier in debugging with HDL simulators. -.. note:: If netlist is not specified, FPGA-SPICE auto-generates the SPICE netlists for multiplexers, wires, and LUTs. +.. note:: If netlist is not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs. .. note:: The user-defined netlists, such as LUTs, the decoding methodology should comply with the auto-generated LUTs (See Section 4.5) @@ -67,7 +67,7 @@ Transistor level * input_buffer and output_buffer: - * **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist. + * **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined Verilog/SPICE netlist. * **circuit_model_name:** Specify the name of circuit model which is used to implement input/output buffer, the type of specified circuit model should be inv_buf. @@ -79,7 +79,7 @@ Transistor level * **type:** can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined. - * **prefix:** the name of the port. Each port will be shown as [i], 0≤i[i] in Verilog/SPICE netlists. * **size:** bandwidth of the port. @@ -96,3 +96,5 @@ Transistor level * **is_reset:** can be either true or false. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches. * **is_config_enable:** can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to global configuration-enable voltage stimuli in testbenches. + +.. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details. From fc93a4941a17ae61bc48849480922d8aec914555 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 5 Aug 2019 14:50:33 -0600 Subject: [PATCH 018/482] update documentation --- docs/source/arch_lang/circuit_model_examples.rst | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst index 72b3eccd9..7b55e257b 100644 --- a/docs/source/arch_lang/circuit_model_examples.rst +++ b/docs/source/arch_lang/circuit_model_examples.rst @@ -253,24 +253,25 @@ Multiplexers * design_technology: - * **structure:** can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required: + * **structure:** can be [``tree``\|``multi-level``\|``one-level``]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required: * **num_level:** specify the number of levels when multi-level structure is selected, only. - * **add_const_input:** can be [true|false]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead. + * **add_const_input:** can be [``true``\|``false``]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead. + * **const_input_val:** specify the constant value, to which the extra input will be connected. This syntax is only valid when the ``add_const_input`` is set to true. - * **local_encoder:** can be [true|false]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead. + * **local_encoder:** can be [``true``\|``false``]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead. - * **prog_transistor_size:** valid only when the type of design technology is rram. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node . + .. note:: Local encoders are only applicable for one-level and multi-level multiplexers. Tree-like multiplexers are already encoded in their nature. - * If type of design technology is **rram**, then the following parameters are required: + * **prog_transistor_size:** valid only when the type of design technology is ``rram``. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node ``transistors``. If type of design technology is ``rram``, then the following parameters are required: * **ron:** valid only when the type of design technology is rram. Specify the on-resistance of the RRAM device used in the RRAM-based multiplexer. * **roff:** valid only when the type of design technology is rram. Specify the off-resistance of the RRAM device used in the RRAM-based multiplexer. -* port: for a multiplexer, the three types of ports, input, output and sram should be defined. +* port: for a multiplexer, the three types of ports, ``input``, ``output`` and ``sram`` should be defined. .. note:: For tree-like multiplexers, they can be built with standard cell MUX2. To enable this, users should define a ``circuit_model``, which describes a 2-input multiplexer (See details and examples in how to define a logic gate using ``circuit_model``. In this case, the ``circuit_model_name`` in the ``pass_gate_logic`` should be the name of MUX2 ``circuit_model``. From b4f3dfc82dec503dbe0ef5e0e8e9d31735f7d90f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 5 Aug 2019 16:35:36 -0600 Subject: [PATCH 019/482] bug fixing for local encoder's bitstream generation --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c | 12 +++++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 5 +++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c index 1dd1b1af5..f47574b08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c @@ -496,12 +496,22 @@ void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model, case SPICE_MODEL_STRUCTURE_ONELEVEL: (*mux_level) = 1; (*bit_len) = num_mux_input; + /* Mux has local encoders are different in the number of bits */ + if (TRUE == mux_spice_model->design_tech_info.mux_info->local_encoder) { + (*bit_len) = determine_mux_local_encoder_num_inputs(*bit_len); + } (*conf_bits) = decode_onelevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id, mux_spice_model->design_tech_info.mux_info->local_encoder); break; case SPICE_MODEL_STRUCTURE_MULTILEVEL: (*mux_level) = mux_spice_model->design_tech_info.mux_info->mux_num_level; - (*bit_len) = determine_num_input_basis_multilevel_mux(num_mux_input, (*mux_level)) * (*mux_level); + /* Mux has local encoders are different in the number of bits */ + if (TRUE == mux_spice_model->design_tech_info.mux_info->local_encoder) { + int num_bits_per_level = determine_mux_local_encoder_num_inputs(determine_num_input_basis_multilevel_mux(num_mux_input, (*mux_level))); + (*bit_len) = (*mux_level) * num_bits_per_level; + } else { + (*bit_len) = (*mux_level) * determine_num_input_basis_multilevel_mux(num_mux_input, (*mux_level)); + } (*conf_bits) = decode_multilevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id, mux_spice_model->design_tech_info.mux_info->local_encoder); break; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 78ef46f0d..aae1ec553 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2989,8 +2989,9 @@ void dump_verilog_submodule_local_encoders(t_sram_orgz_info* cur_sram_orgz_info, temp = temp->next; continue; } - /* Bypass those without local encoders */ - if (FALSE == cur_spice_mux_model->spice_model->design_tech_info.mux_info->local_encoder) { + /* Bypass those without local encoders, we only care SPICE models whose type is MUX! */ + if ( (SPICE_MODEL_MUX != cur_spice_mux_model->spice_model->type) + || (FALSE == cur_spice_mux_model->spice_model->design_tech_info.mux_info->local_encoder) ) { /* Move on to the next*/ temp = temp->next; continue; From b207050b036bf07d99ac3edae2f8c427c6cec08d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Aug 2019 11:57:09 -0600 Subject: [PATCH 020/482] minor fix in documentation --- docs/source/arch_lang/circuit_model_examples.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst index 7b55e257b..9cde3e5cf 100644 --- a/docs/source/arch_lang/circuit_model_examples.rst +++ b/docs/source/arch_lang/circuit_model_examples.rst @@ -253,15 +253,15 @@ Multiplexers * design_technology: - * **structure:** can be [``tree``\|``multi-level``\|``one-level``]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required: + * **structure:** can be [``tree`` \| ``multi-level`` \| ``one-level``]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required: * **num_level:** specify the number of levels when multi-level structure is selected, only. - * **add_const_input:** can be [``true``\|``false``]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead. + * **add_const_input:** can be [``true`` \| ``false``]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead. * **const_input_val:** specify the constant value, to which the extra input will be connected. This syntax is only valid when the ``add_const_input`` is set to true. - * **local_encoder:** can be [``true``\|``false``]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead. + * **local_encoder:** can be [``true`` \| ``false``]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead. .. note:: Local encoders are only applicable for one-level and multi-level multiplexers. Tree-like multiplexers are already encoded in their nature. From afa468a442e5465b28b9a4c5d616803e0faa8aa3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Aug 2019 11:58:27 -0600 Subject: [PATCH 021/482] hotfix in minor Verilog generation --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index aae1ec553..9a224c3c1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2895,7 +2895,7 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { fprintf(fp, "begin\n"); fprintf(fp, "\tdata_reg = %d'b0;\n", num_outputs); fprintf(fp, "\tif ((0 < addr) && (addr < %d) ) begin\n", num_outputs); - fprintf(fp, "\t\tdata_reg = 1'b1 << (addr - 1)\n"); + fprintf(fp, "\t\tdata_reg = 1'b1 << (addr - 1);\n"); fprintf(fp, "\tend\n"); fprintf(fp, "end\n"); From f57495febac45e07017b3af8f55e111a88aa30c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Aug 2019 15:19:01 -0600 Subject: [PATCH 022/482] Now we can also auto-generate the Verilog for a mux2 std cell --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 44 ++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 9a224c3c1..a820a5102 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -547,7 +547,49 @@ void dump_verilog_gate_module(FILE* fp, fprintf(fp, ";\n"); } } - + break; + case SPICE_MODEL_GATE_MUX2: + /* Check on the port sequence and map */ + /* MUX2 should only have 1 output port with size 1 */ + if (1 != num_output_port) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) MUX2 circuit model must have only 1 output!\n", + __FILE__, __LINE__); + exit(1); + } else if (1 != output_port[0]->size) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Output size of a MUX2 circuit model must be 1!\n", + __FILE__, __LINE__); + exit(1); + } + /* MUX2 should only have 3 output port, each of which has a port size of 1 */ + if (3 != num_input_port) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) MUX2 circuit model must have only 3 input!\n", + __FILE__, __LINE__); + exit(1); + } else { + for (iport = 0; iport < num_input_port; iport++) { + /* Bypass port size of 1 */ + if (1 == input_port[iport]->size) { + continue; + } + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Input size MUX2 circuit model must be 1!\n", + __FILE__, __LINE__); + exit(1); + } + } + /* Now, we output the logic of MUX2 + * IMPORTANT Restriction: + * We always assum the first two inputs are data inputs + * the third input is the select port + */ + fprintf(fp, "assign %s[%d] = %s[%d] ? %s[%d] : %s[%d];\n", + output_port[0]->lib_name, 0, + input_port[2]->lib_name, 0, + input_port[0]->lib_name, 0, + input_port[1]->lib_name, 0); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", From 74da4ed51adf702fe2713611b7655aa7a42bb212 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 11:38:45 -0600 Subject: [PATCH 023/482] start creating the class for circuit models --- vpr7_x2p/libarchfpga/CMakeLists.txt | 3 +- .../fpga_spice_include/circuit_library.cpp | 58 ++++ .../SRC/fpga_spice_include/circuit_library.h | 316 ++++++++++++++++++ vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 4 + 4 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h diff --git a/vpr7_x2p/libarchfpga/CMakeLists.txt b/vpr7_x2p/libarchfpga/CMakeLists.txt index 714349130..528310c1d 100644 --- a/vpr7_x2p/libarchfpga/CMakeLists.txt +++ b/vpr7_x2p/libarchfpga/CMakeLists.txt @@ -35,11 +35,12 @@ set_target_properties(libarchfpga PROPERTIES PREFIX "") #Avoid extra 'lib' prefi # Specify dependency target_link_libraries(libarchfpga + libvtrutil libpcre libprinthandler) add_executable(read_arch ${EXEC_SOURCES}) -target_link_libraries(read_arch libarchfpga) +target_link_libraries(read_arch libarchfpga libvtrutil) # install: TO BE TESTED diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp new file mode 100644 index 000000000..d873d716a --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -0,0 +1,58 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: circuit_library.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/07 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +#include "circuit_library.h" + +/************************************************************************ + * Member functions for class CircuitLibrary + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ + +/************************************************************************ + * Accessors + ***********************************************************************/ + +/* Aggregates */ +CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { + return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); +} + + +/************************************************************************ + * End of file : circuit_library.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h new file mode 100644 index 000000000..3c4a5aebb --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -0,0 +1,316 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: circuit_library.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/06 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef CIRCUIT_LIBRARY_H +#define CIRCUIT_LIBRARY_H + +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include "vtr_strong_id.h" + +#include "vtr_vector.h" +#include "vtr_range.h" + +#include "spice_types.h" + +/************************************************************************ + * Create strong id for Circuit Models/Ports to avoid illegal type casting + ***********************************************************************/ +struct circuit_model_id_tag; +struct circuit_port_id_tag; +struct circuit_edge_id_tag; + +typedef vtr::StrongId CircuitModelId; +typedef vtr::StrongId CircuitPortId; +typedef vtr::StrongId CircuitEdgeId; + +/************************************************************************ + * The class CircuitLibrary is a critical data structure for OpenFPGA + * It stores all the circuit-level details from XML architecture file + * + * It includes the following data: + * + * ------ Fundamental Information ----- + * 1. circuit_model_ids_ : unique identifier to find a circuit model + * Use a strong id for search, to avoid illegal type casting + * 2. circuit_model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type + * 3. circuit_model_names_: unique names for each circuit models. + * It should be the same as user-defined Verilog modules, if it is not auto-generated + * 4. circuit_model_prefix_: the prefix of a circuit model when it is instanciated + * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated + * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated + * 7. is_default_: indicate if the circuit model is the default one among all those in the same type + * + * ------ Verilog generation options ----- + * 1. dump_structural_verilog_: if Verilog generator will output structural Verilog syntax for the circuit model + * 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model + * + * ------ Design technology information ----- + * 1. design_tech_: the design technology [cmos|rram] for each circuit model + * 2. power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND) + * + * ------ Buffer existence ----- + * Use vectors to simplify the defition of buffer existence: + * index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER + * 1. buffer_existence_: specify if this circuit model has an buffer + * 2. buffer_circuit_model_name_: specify the name of circuit model for the buffer + * 3. buffer_circuit_model_id_: specify the id of circuit model for the buffer + * + * ------ Pass-gate-related parameters ------ + * 1. pass_gate_logic_circuit_model_name_: specify the name of circuit model for the pass gate logic + * 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic + * + * ------ Port information ------ + * 1. port_types_: types of ports belonging to a circuit model + * 2. port_sizes_: width of ports belonging to a circuit model + * 3. port_prefix_: prefix of a port when instance of a circuit model + * 4. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled + * 5. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port + * 6. port_is_mode_select: specify if this port is used to select operating modes of the circuit model + * 7. port_is_global: specify if this port is a global signal shared by other circuit model + * 8. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches + * 9. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches + * 10. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches + * 11. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 12. port_circuit_model_name: the name of circuit model linked to the port + * 13. port_circuit_model_ids_: the Id of circuit model linked to the port + * 14. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port + * 15. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port + * 16. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 17. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 18. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 19. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * + * ------ Delay information ------ + * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge + * 2. delay_in_port_names_: name of input ports that the pin-to-pin delay is linked to + * 3. delay_in_port_names_: name of output ports that the pin-to-pin delay is linked to + * 4. delay_values_: delay values of the pin-to-pin delay + * + * ------ Timing graph information: TODO: consider using tatum? ------ + * Timing graph is allocated when delay information is made + * 1. edge_ids_ : ids of edges in the timing graph + * 2. port_in_edge_ids_: ids of input edges for each pin of a circuit port + * 3. port_out_edge_ids_: ids of output edges for each pin of a circuit port + * 4. edge_src_port_ids_: ids of source ports that each edge is connected to + * 5. edge_src_pin_ids_: ids of source pin that each edge is connected to + * 6. edge_sink_port_ids_: ids of sink ports that each edge is connected to + * 7. edge_sink_pin_ids_: ids of sink pin that each edge is connected to + * 8. edge_trise_: rising delay of the edge + * 9. edge_tfall_: falling delay of the edge + * + * ------ Buffer/Inverter-related parameters ------ + * Note: only applicable to circuit models whose type is buffer or inverter + * 1. buffer_types_: type of the buffer, either buffer or inverter + * 2. buffer_location_maps_: location of the buffer, only applicable to LUTs + * 3. buffer_sizes_: size of buffer (transistor size for the first stage) + * 4. buffer_is_tapered_: specify if this buffer has multiple stages + * 5. buffer_num_levels: specify the number of levels of this buffer (if this is defined as multi-level buffer) + * 6. buffer_f_per_stage: specify the driving strength of the buffer by stage + * + * ------ Pass-gate-logic-related parameters ------ + * Note: only applicable to circuit models whose type is pass-gate-logic + * 1. pass_gate_logic_types_: types of the pass-gate-logic, either transmission-gate or pass-transistor + * 2. pass_gate_logic_nmos_sizes_: size of NMOS transistor in the pass-gate-logic + * 3. pass_gate_logic_pmos_sizes_: size of PMOS transistor in the pass-gate-logic, only applicable for transmission-gates + * + * ------ Multiplexer-related parameters ------ + * Note: only applicable to circuit models whose type is MUX + * 1. mux_structure_: specify the structure of a multiplexer, one-level, multi-level or tree-like + * 2. mux_num_levels_: specify the number of levels for a multiplexer + * 3. mux_add_const_input_: specify if this multiplexer has a constant input + * 4. mux_const_input_values_: specify the value of the constant input for this multiplexer (valid only when mux_add_const_input is true) + * 5. mux_use_local_encoder_: specify if the mux as a local encoder between SRAMs and multiplexing structure + * 6. mux_advanced_rram_design_: specify if the multiplexer will use advanced RRAM circuit design topology + * + * ------ LUT-related parameters ------ + * Note: only applicable to circuit models whose type is LUT + * 1. lut_is_fracturable_: specify if this LUT is built with fracturable structure + * + * ------ RRAM-related parameters ------ + * Note: only applicable to circuit models whose design technology is RRAM + * 1. rlrs: RRAM resistance in Low-Resistance State (LRS) + * 2. rhrs: RRAM resistance in High-Resistance State (HRS) + * The following transistor sizes are applicable for 4T1R programming structures + * 3. wprog_set_nmos: size of n-type programming transistor used to set a RRAM + * 4. wprog_set_pmos: size of p-type programming transistor used to set a RRAM + * 5. wprog_reset_nmos: size of n-type programming transistor used to reset a RRAM + * 6. wprog_reset_pmos: size of p-type programming transistor used to reset a RRAM + * + * ------ Metal wire-related parameters ------ + * Note: only applicable to circuit models whose type is wires or channel wires + * 1. wire_types_: types of the metal wire for the circuit_model + * 2. wire_res_val_: resistance value of the metal wire for the circuit model + * 3. wire_cap_val_: capacitance value of the metal wire for the circuit model + * 4. wire_num_levels_: number of levels of the metal wire model for the circuit model + ***********************************************************************/ +class CircuitLibrary { + public: /* Types */ + typedef vtr::vector::const_iterator circuit_model_iterator; + typedef vtr::vector::const_iterator circuit_port_iterator; + typedef vtr::vector::const_iterator circuit_edge_iterator; + /* Create range */ + typedef vtr::Range circuit_model_range; + typedef vtr::Range circuit_port_range; + typedef vtr::Range circuit_edge_range; + /* local enumeration for buffer existence */ + enum e_buffer_type: unsigned char{ + INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INV, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ + }; + public: /* Constructors */ + public: /* Accessors */ + /* Aggregates */ + circuit_model_range circuit_models() const; + public: /* Mutators */ + private: /* Internal functions */ + private: /* Internal data */ + /* Fundamental information */ + vtr::vector circuit_model_ids_; + vtr::vector circuit_model_types_; + vtr::vector circuit_model_names_; + vtr::vector circuit_model_prefix_; + vtr::vector verilog_netlists_; + vtr::vector spice_netlists_; + vtr::vector is_default_; + + /* Verilog generator options */ + vtr::vector dump_structural_verilog_; + vtr::vector dump_explicit_port_map_; + + /* Design technology information */ + vtr::vector design_tech_; + vtr::vector power_gated_; + + /* Buffer existence */ + vtr::vector> buffer_existence_; + vtr::vector> buffer_circuit_model_name_; + vtr::vector> buffer_circuit_model_id_; + + /* Pass-gate-related parameters */ + vtr::vector pass_gate_logic_circuit_model_name_; + vtr::vector pass_gate_logic_circuit_model_id_; + + /* Port information */ + vtr::vector> port_types_; + vtr::vector> port_sizes_; + vtr::vector> port_prefix_; + vtr::vector> port_lib_names_; + vtr::vector> port_inv_prefix_; + vtr::vector> port_is_mode_select_; + vtr::vector> port_is_global_; + vtr::vector> port_is_reset_; + vtr::vector> port_is_set_; + vtr::vector> port_is_config_enable_; + vtr::vector> port_is_prog_; + vtr::vector> port_circuit_model_names_; + vtr::vector> port_circuit_model_ids_; + vtr::vector> port_inv_circuit_model_names_; + vtr::vector> port_inv_circuit_model_ids_; + vtr::vector> port_tri_state_map_; + vtr::vector> port_lut_frac_level_; + vtr::vector>> port_lut_output_mask_; + vtr::vector> port_sram_orgz_; + + /* Timing graphs */ + vtr::vector> edge_ids_; + vtr::vector>> port_in_edge_ids_; + vtr::vector>> port_out_edge_ids_; + vtr::vector> edge_src_ports_; + vtr::vector> edge_src_pin_ids_; + vtr::vector> edge_sink_ports_; + vtr::vector> edge_sink_pin_ids_; + vtr::vector> edge_trise_; + vtr::vector> edge_tfall_; + + /* Delay information */ + vtr::vector> delay_types_; + vtr::vector> delay_in_port_names_; + vtr::vector> delay_out_port_names_; + vtr::vector> delay_values_; + + /* Buffer/Inverter-related parameters */ + vtr::vector buffer_types_; + vtr::vector buffer_location_maps_; + vtr::vector buffer_sizes_; + vtr::vector buffer_is_tapered_; + vtr::vector buffer_num_levels_; + vtr::vector buffer_f_per_stage_; + + /* Pass-gate-related parameters */ + vtr::vector pass_gate_logic_types_; + vtr::vector pass_gate_logic_nmos_sizes_; + vtr::vector pass_gate_logic_pmos_sizes_; + + /* Multiplexer-related parameters */ + vtr::vector mux_structure_; + vtr::vector mux_num_levels_; + vtr::vector mux_add_const_input_; + vtr::vector mux_const_input_values_; + vtr::vector mux_use_local_encoder_; + vtr::vector mux_advanced_rram_design_; + + /* LUT-related parameters */ + vtr::vector lut_is_fracturable_; + + /* RRAM-related design technology information */ + vtr::vector rlrs_; + vtr::vector rhrs_; + vtr::vector wprog_set_nmos_; + vtr::vector wprog_set_pmos_; + vtr::vector wprog_reset_nmos_; + vtr::vector wprog_reset_pmos_; + + /* Wire parameters */ + vtr::vector wire_types_; + vtr::vector wire_res_val_; + vtr::vector wire_cap_val_; + vtr::vector wire_num_levels_; + +}; + +#endif + +/************************************************************************ + * End of file : circuit_library.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index 49c1d78f4..6dd2437fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -411,3 +411,7 @@ class DeviceRRGSB { #endif +/************************************************************************ + * End of file : rr_blocks.h + ***********************************************************************/ + From 38962c4607f19f6052d551721ac8db8afa89f4e4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 15:45:27 -0600 Subject: [PATCH 024/482] adding member functions for circuit library --- libs/libvtrutil/src/vtr_geometry.h | 1 + libs/libvtrutil/src/vtr_geometry.tpp | 6 + .../fpga_spice_include/circuit_library.cpp | 160 +++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 65 ++++--- .../SRC/fpga_spice_include/spice_types.h | 18 +- 5 files changed, 221 insertions(+), 29 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 2ff45e6d0..e19dff1c0 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -49,6 +49,7 @@ template class Point { public: //Constructors Point(T x_val, T y_val); + Point(); public: //Accessors diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 658f564fe..b06f29189 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -10,6 +10,12 @@ namespace vtr { //pass } + template + Point::Point() { + //pass + } + + template T Point::x() const { return x_; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index d873d716a..e192cb6af 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -33,6 +33,8 @@ * +-------------------------------------+ ***********************************************************************/ +#include "vtr_assert.h" + #include "circuit_library.h" /************************************************************************ @@ -44,15 +46,167 @@ ***********************************************************************/ /************************************************************************ - * Accessors + * Accessors : aggregates ***********************************************************************/ - -/* Aggregates */ CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); } +/************************************************************************ + * Accessors : Methods to find circuit model + ***********************************************************************/ +/* Find a circuit model by a given name and return its id */ +CircuitModelId CircuitLibrary::get_circuit_model_id_by_name(const std::string& name) const { + CircuitModelId ret = CIRCUIT_MODEL_OPEN_ID; + size_t num_found = 0; + for (circuit_model_string_iterator it = circuit_model_names_.begin(); + it != circuit_model_names_.end(); + it++) { + /* Bypass unmatched names */ + if ( 0 != name.compare(*it) ) { + continue; + } + /* Find one and record it + * FIXME: I feel that we may have a better way in getting the CircuitModelId + */ + ret = CircuitModelId(it - circuit_model_names_.begin()); + num_found++; + } + VTR_ASSERT((0 == num_found) || (1 == num_found)); + return ret; +} + +/* Get the CircuitModelId of a default circuit model with a given type */ +CircuitModelId CircuitLibrary::get_default_circuit_model_id(const enum e_spice_model_type& type) const { + /* Default circuit model id is the first element by type in the fast look-up */ + return circuit_model_lookup_[size_t(type)].front(); +} + +/************************************************************************ + * Mutators + ***********************************************************************/ +/* Add a circuit model to the library, and return it Id */ +CircuitModelId CircuitLibrary::add_circuit_model() { + /* Create a new id*/ + CircuitModelId circuit_model_id = CircuitModelId(circuit_model_ids_.size()); + /* Update the id list */ + circuit_model_ids_.push_back(circuit_model_id); + + /* Initialize other attributes */ + /* Fundamental information */ + circuit_model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES); + circuit_model_names_.emplace_back(); + circuit_model_prefix_.emplace_back(); + circuit_model_verilog_netlists_.emplace_back(); + circuit_model_spice_netlists_.emplace_back(); + circuit_model_is_default_.push_back(false); + + /* Verilog generator options */ + dump_structural_verilog_.push_back(false); + dump_explicit_port_map_.push_back(false); + + /* Design technology information */ + design_tech_.push_back(NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES); + power_gated_.push_back(false); + + /* Buffer existence */ + buffer_existence_.emplace_back(); + buffer_circuit_model_names_.emplace_back(); + buffer_circuit_model_ids_.emplace_back(); + + /* Pass-gate-related parameters */ + pass_gate_logic_circuit_model_names_.emplace_back(); + pass_gate_logic_circuit_model_ids_.emplace_back(); + + /* Port information */ + port_types_.emplace_back(); + port_sizes_.emplace_back(); + port_prefix_.emplace_back(); + port_lib_names_.emplace_back(); + port_is_mode_select_.emplace_back(); + port_is_global_.emplace_back(); + port_is_reset_.emplace_back(); + port_is_set_.emplace_back(); + port_is_config_enable_.emplace_back(); + port_is_prog_.emplace_back(); + port_circuit_model_names_.emplace_back(); + port_circuit_model_ids_.emplace_back(); + port_inv_circuit_model_names_.emplace_back(); + port_inv_circuit_model_ids_.emplace_back(); + port_tri_state_maps_.emplace_back(); + port_lut_frac_level_.emplace_back(); + port_lut_output_masks_.emplace_back(); + port_sram_orgz_.emplace_back(); + + /* Timing graphs */ + edge_ids_.emplace_back(); + port_in_edge_ids_.emplace_back(); + port_out_edge_ids_.emplace_back(); + edge_src_ports_.emplace_back(); + edge_src_pin_ids_.emplace_back(); + edge_sink_ports_.emplace_back(); + edge_sink_pin_ids_.emplace_back(); + edge_trise_.emplace_back(); + edge_tfall_.emplace_back(); + + /* Delay information */ + delay_types_.emplace_back(); + delay_in_port_names_.emplace_back(); + delay_out_port_names_.emplace_back(); + delay_values_.emplace_back(); + + /* Buffer/Inverter-related parameters */ + buffer_types_.push_back(NUM_CIRCUIT_MODEL_BUF_TYPES); + buffer_location_maps_.emplace_back(); + buffer_sizes_.push_back(-1); + buffer_is_tapered_.push_back(false); + buffer_num_levels_.push_back(-1); + buffer_f_per_stage_.push_back(-1); + + /* Pass-gate-related parameters */ + pass_gate_logic_types_.push_back(NUM_CIRCUIT_MODEL_PASS_GATE_TYPES); + pass_gate_logic_nmos_sizes_.push_back(-1); + pass_gate_logic_pmos_sizes_.push_back(-1); + + /* Multiplexer-related parameters */ + mux_structure_.push_back(NUM_CIRCUIT_MODEL_STRUCTURE_TYPES); + mux_num_levels_.push_back(-1); + mux_add_const_input_.push_back(false); + mux_const_input_values_.push_back(-1); + mux_use_local_encoder_.push_back(false); + mux_advanced_rram_design_.push_back(false); + + /* LUT-related parameters */ + lut_is_fracturable_.push_back(false); + + /* RRAM-related design technology information */ + rram_res_.emplace_back(); + wprog_set_.emplace_back(); + wprog_reset_.emplace_back(); + + /* Wire parameters */ + wire_types_.push_back(NUM_WIRE_MODEL_TYPES); + wire_rc_.emplace_back(); + wire_num_levels_.push_back(-1); + + /* Invalidate fast look-up*/ + + + return circuit_model_id; +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +/* Link the inv_circuit_model_id for each port of a circuit model. + * We search the inv_circuit_model_name in the CircuitLibrary and + * configure the port inv_circuit_model_id + */ +void CircuitLibrary::set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { + return; +} + /************************************************************************ * End of file : circuit_library.cpp ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 3c4a5aebb..bedfabb7f 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -48,6 +48,7 @@ /* Header files should be included in a sequence */ /* Standard header files required go first */ #include "vtr_strong_id.h" +#include "vtr_geometry.h" #include "vtr_vector.h" #include "vtr_range.h" @@ -65,6 +66,12 @@ typedef vtr::StrongId CircuitModelId; typedef vtr::StrongId CircuitPortId; typedef vtr::StrongId CircuitEdgeId; + +/* Alias for open ids */ +#define CIRCUIT_MODEL_OPEN_ID CircuitModelId(-1) +#define CIRCUIT_PORT_OPEN_ID CircuitPortId(-1) +#define CIRCUIT_EDGE_OPEN_ID CircuitEdgeId(-1) + /************************************************************************ * The class CircuitLibrary is a critical data structure for OpenFPGA * It stores all the circuit-level details from XML architecture file @@ -82,6 +89,12 @@ typedef vtr::StrongId CircuitEdgeId; * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated * 7. is_default_: indicate if the circuit model is the default one among all those in the same type * + * ------ Fast look-ups----- + * 1. circuit_model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users + * It classifies CircuitModelIds by their type and set the default model in the first element for each type. + * 2. circuit_model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users + * It classifies Ports by their types + * * ------ Verilog generation options ----- * 1. dump_structural_verilog_: if Verilog generator will output structural Verilog syntax for the circuit model * 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model @@ -188,6 +201,7 @@ typedef vtr::StrongId CircuitEdgeId; class CircuitLibrary { public: /* Types */ typedef vtr::vector::const_iterator circuit_model_iterator; + typedef vtr::vector::const_iterator circuit_model_string_iterator; typedef vtr::vector::const_iterator circuit_port_iterator; typedef vtr::vector::const_iterator circuit_edge_iterator; /* Create range */ @@ -199,20 +213,35 @@ class CircuitLibrary { INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INV, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ }; public: /* Constructors */ - public: /* Accessors */ - /* Aggregates */ + public: /* Accessors: aggregates */ circuit_model_range circuit_models() const; + public: /* Accessors: Basic data query */ + public: /* Accessors: Methods to find circuit model */ + CircuitModelId get_circuit_model_id_by_name(const std::string& name) const ; + CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const; public: /* Mutators */ - private: /* Internal functions */ + CircuitModelId add_circuit_model(); + public: /* Internal mutators */ + void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); + private: /* Internal validators */ private: /* Internal data */ /* Fundamental information */ vtr::vector circuit_model_ids_; vtr::vector circuit_model_types_; vtr::vector circuit_model_names_; vtr::vector circuit_model_prefix_; - vtr::vector verilog_netlists_; - vtr::vector spice_netlists_; - vtr::vector is_default_; + vtr::vector circuit_model_verilog_netlists_; + vtr::vector circuit_model_spice_netlists_; + vtr::vector circuit_model_is_default_; + + /* fast look-up for circuit models to categorize by types + * [type][num_ids] + * Important: we force the default circuit model in the first element for each type + */ + typedef std::vector> CircuitModelLookup; + mutable CircuitModelLookup circuit_model_lookup_; /* [circuit_model_type][circuit_model_ids] */ + typedef std::vector>>> CircuitModelPortLookup; + mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_type][circuit_model_id][port_type][port_ids] */ /* Verilog generator options */ vtr::vector dump_structural_verilog_; @@ -224,12 +253,12 @@ class CircuitLibrary { /* Buffer existence */ vtr::vector> buffer_existence_; - vtr::vector> buffer_circuit_model_name_; - vtr::vector> buffer_circuit_model_id_; + vtr::vector> buffer_circuit_model_names_; + vtr::vector> buffer_circuit_model_ids_; /* Pass-gate-related parameters */ - vtr::vector pass_gate_logic_circuit_model_name_; - vtr::vector pass_gate_logic_circuit_model_id_; + vtr::vector pass_gate_logic_circuit_model_names_; + vtr::vector pass_gate_logic_circuit_model_ids_; /* Port information */ vtr::vector> port_types_; @@ -247,9 +276,9 @@ class CircuitLibrary { vtr::vector> port_circuit_model_ids_; vtr::vector> port_inv_circuit_model_names_; vtr::vector> port_inv_circuit_model_ids_; - vtr::vector> port_tri_state_map_; + vtr::vector> port_tri_state_maps_; vtr::vector> port_lut_frac_level_; - vtr::vector>> port_lut_output_mask_; + vtr::vector>> port_lut_output_masks_; vtr::vector> port_sram_orgz_; /* Timing graphs */ @@ -294,17 +323,13 @@ class CircuitLibrary { vtr::vector lut_is_fracturable_; /* RRAM-related design technology information */ - vtr::vector rlrs_; - vtr::vector rhrs_; - vtr::vector wprog_set_nmos_; - vtr::vector wprog_set_pmos_; - vtr::vector wprog_reset_nmos_; - vtr::vector wprog_reset_pmos_; + vtr::vector> rram_res_; /* x => R_LRS, y => R_HRS */ + vtr::vector> wprog_set_; /* x => wprog_set_nmos, y=> wprog_set_pmos */ + vtr::vector> wprog_reset_; /* x => wprog_reset_nmos, y=> wprog_reset_pmos */ /* Wire parameters */ vtr::vector wire_types_; - vtr::vector wire_res_val_; - vtr::vector wire_cap_val_; + vtr::vector> wire_rc_; /* x => wire_res_val, y=> wire_cap_val */ vtr::vector wire_num_levels_; }; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index 722816380..d3ad32ae7 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -28,29 +28,34 @@ enum e_spice_model_type { SPICE_MODEL_IOPAD, SPICE_MODEL_INVBUF, SPICE_MODEL_PASSGATE, - SPICE_MODEL_GATE + SPICE_MODEL_GATE, + NUM_CIRCUIT_MODEL_TYPES }; enum e_spice_model_design_tech { SPICE_MODEL_DESIGN_CMOS, - SPICE_MODEL_DESIGN_RRAM + SPICE_MODEL_DESIGN_RRAM, + NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES }; enum e_spice_model_structure { SPICE_MODEL_STRUCTURE_TREE, SPICE_MODEL_STRUCTURE_ONELEVEL, SPICE_MODEL_STRUCTURE_MULTILEVEL, - SPICE_MODEL_STRUCTURE_CROSSBAR + SPICE_MODEL_STRUCTURE_CROSSBAR, + NUM_CIRCUIT_MODEL_STRUCTURE_TYPES }; enum e_spice_model_buffer_type { SPICE_MODEL_BUF_INV, - SPICE_MODEL_BUF_BUF + SPICE_MODEL_BUF_BUF, + NUM_CIRCUIT_MODEL_BUF_TYPES }; enum e_spice_model_pass_gate_logic_type { SPICE_MODEL_PASS_GATE_TRANSMISSION, - SPICE_MODEL_PASS_GATE_TRANSISTOR + SPICE_MODEL_PASS_GATE_TRANSISTOR, + NUM_CIRCUIT_MODEL_PASS_GATE_TYPES }; enum e_spice_model_gate_type { @@ -69,7 +74,8 @@ enum e_spice_trans_type { enum e_wire_model_type { WIRE_MODEL_PIE, - WIRE_MODEL_T + WIRE_MODEL_T, + NUM_WIRE_MODEL_TYPES, }; enum e_spice_model_port_type { From ed4642a23f7e06b2538db11c234b431638a9a763 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 17:12:05 -0600 Subject: [PATCH 025/482] adding basic mutators --- .../fpga_spice_include/circuit_library.cpp | 229 +++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 45 +++- 2 files changed, 259 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index e192cb6af..2a6e32756 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -33,6 +33,8 @@ * +-------------------------------------+ ***********************************************************************/ +#include + #include "vtr_assert.h" #include "circuit_library.h" @@ -46,7 +48,7 @@ ***********************************************************************/ /************************************************************************ - * Accessors : aggregates + * Public Accessors : aggregates ***********************************************************************/ CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); @@ -54,7 +56,7 @@ CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { /************************************************************************ - * Accessors : Methods to find circuit model + * Public Accessors : Methods to find circuit model ***********************************************************************/ /* Find a circuit model by a given name and return its id */ CircuitModelId CircuitLibrary::get_circuit_model_id_by_name(const std::string& name) const { @@ -84,7 +86,7 @@ CircuitModelId CircuitLibrary::get_default_circuit_model_id(const enum e_spice_m } /************************************************************************ - * Mutators + * Public Mutators ***********************************************************************/ /* Add a circuit model to the library, and return it Id */ CircuitModelId CircuitLibrary::add_circuit_model() { @@ -107,7 +109,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() { dump_explicit_port_map_.push_back(false); /* Design technology information */ - design_tech_.push_back(NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES); + design_tech_types_.push_back(NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES); power_gated_.push_back(false); /* Buffer existence */ @@ -190,23 +192,240 @@ CircuitModelId CircuitLibrary::add_circuit_model() { wire_rc_.emplace_back(); wire_num_levels_.push_back(-1); - /* Invalidate fast look-up*/ + /* Update circuit port fast look-up */ + circuit_model_port_lookup_.emplace_back(); + /* Invalidate fast look-up*/ + invalidate_circuit_model_lookup(); return circuit_model_id; } +/* Set the type of a Circuit Model */ +void CircuitLibrary::set_circuit_model_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_type& type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_types_[circuit_model_id] = type; + return; +} + +/* Set the name of a Circuit Model */ +void CircuitLibrary::set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_names_[circuit_model_id] = name; + return; +} + +/* Set the prefix of a Circuit Model */ +void CircuitLibrary::set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_prefix_[circuit_model_id] = prefix; + return; +} + +/* Set the verilog_netlist of a Circuit Model */ +void CircuitLibrary::set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_verilog_netlists_[circuit_model_id] = verilog_netlist; + return; +} + +/* Set the spice_netlist of a Circuit Model */ +void CircuitLibrary::set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_spice_netlists_[circuit_model_id] = spice_netlist; + return; +} + +/* Set the is_default of a Circuit Model */ +void CircuitLibrary::set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_is_default_[circuit_model_id] = is_default; + return; +} + +/* Set the dump_structural_verilog of a Circuit Model */ +void CircuitLibrary::set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + dump_structural_verilog_[circuit_model_id] = dump_structural_verilog; + return; +} + +/* Set the dump_explicit_port_map of a Circuit Model */ +void CircuitLibrary::set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + dump_explicit_port_map_[circuit_model_id] = dump_explicit_port_map; + return; +} + +/* Set the type of design technology of a Circuit Model */ +void CircuitLibrary::set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + design_tech_types_[circuit_model_id] = design_tech_type; + return; +} + +/* Set the power-gated flag of a Circuit Model */ +void CircuitLibrary::set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + power_gated_[circuit_model_id] = power_gated; + return; +} + +/* Set input buffer information for the circuit model */ +void CircuitLibrary::set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name) { + /* Just call the base function and give the proper type */ + set_circuit_model_buffer(circuit_model_id, INPUT, existence, circuit_model_name); + return; +} + +/* Set output buffer information for the circuit model */ +void CircuitLibrary::set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name) { + /* Just call the base function and give the proper type */ + set_circuit_model_buffer(circuit_model_id, OUTPUT, existence, circuit_model_name); + return; +} + +/* Set input buffer information for the circuit model, only applicable to LUTs! */ +void CircuitLibrary::set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Make sure the circuit model is a LUT! */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + /* Just call the base function and give the proper type */ + set_circuit_model_buffer(circuit_model_id, LUT_INPUT_BUFFER, existence, circuit_model_name); + return; +} + +/* Set input inverter information for the circuit model, only applicable to LUTs! */ +void CircuitLibrary::set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Make sure the circuit model is a LUT! */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + /* Just call the base function and give the proper type */ + set_circuit_model_buffer(circuit_model_id, LUT_INPUT_INVERTER, existence, circuit_model_name); + return; +} + +/* Set intermediate buffer information for the circuit model, only applicable to LUTs! */ +void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Make sure the circuit model is a LUT! */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + /* Just call the base function and give the proper type */ + set_circuit_model_buffer(circuit_model_id, LUT_INTER_BUFFER, existence, circuit_model_name); + return; +} + /************************************************************************ * Internal Mutators ***********************************************************************/ +/* Set the information for a buffer + * For a buffer type, we check if it is in the range of vector + * If yes, just assign values + * If no, resize the vector and then assign values + */ +void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, + const bool& existence, const std::string& circuit_model_name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Check the range of vector */ + if (size_t(buffer_type) >= buffer_existence_[circuit_model_id].size()) { + /* Resize and assign values */ + buffer_existence_[circuit_model_id].resize(size_t(buffer_type) + 1); + buffer_circuit_model_names_[circuit_model_id].resize(size_t(buffer_type) + 1); + buffer_circuit_model_ids_[circuit_model_id].resize(size_t(buffer_type) + 1); + } + /* Now we are in the range, assign values */ + buffer_existence_[circuit_model_id][size_t(buffer_type)] = existence; + buffer_circuit_model_names_[circuit_model_id][size_t(buffer_type)] = circuit_model_name; + buffer_circuit_model_ids_[circuit_model_id][size_t(buffer_type)] = CIRCUIT_MODEL_OPEN_ID; /* Set an OPEN id here, which will be linked later */ + return; +} + /* Link the inv_circuit_model_id for each port of a circuit model. * We search the inv_circuit_model_name in the CircuitLibrary and * configure the port inv_circuit_model_id */ void CircuitLibrary::set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* TODO: complete this function when port mutators are finished */ return; } + +/************************************************************************ + * Internal mutators: build fast look-ups + ***********************************************************************/ +void CircuitLibrary::build_circuit_model_lookup() { + /* invalidate fast look-up */ + invalidate_circuit_model_lookup(); + /* Classify circuit models by type */ + circuit_model_lookup_.resize(NUM_CIRCUIT_MODEL_TYPES); + /* Walk through circuit_models and categorize */ + for (auto& id : circuit_model_ids_) { + circuit_model_lookup_[circuit_model_types_[id]].push_back(id); + } + /* Make the default circuit_model to be the first element for each type */ + for (auto& type : circuit_model_lookup_) { + /* if the first element is already a default model, we skip this */ + if (true == circuit_model_is_default_[type[0]]) { + continue; + } + /* Check the array, and try to find a default model */ + for (size_t id = 0; id < type.size(); ++id) { + if (false == circuit_model_is_default_[type[id]]) { + continue; + } + /* Once we find a default model, swap with the first element and finish the loop */ + std::swap(type[0], type[id]); + break; + } + } + return; +} + +/************************************************************************ + * Internal invalidators/validators + ***********************************************************************/ +/* Validators */ +bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_id) const { + return ( size_t(circuit_model_id) < circuit_model_ids_.size() ) && ( circuit_model_id == circuit_model_ids_[circuit_model_id] ); +} + +/* Invalidators */ +/* Empty fast lookup for circuit_models*/ +void CircuitLibrary::invalidate_circuit_model_lookup() const { + circuit_model_lookup_.clear(); + return; +} + +/* Empty fast lookup for circuit ports for a circuit_model */ +void CircuitLibrary::invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + circuit_model_port_lookup_[size_t(circuit_model_id)].clear(); + return; +} + /************************************************************************ * End of file : circuit_library.cpp ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index bedfabb7f..b6a5464b4 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -47,6 +47,8 @@ */ /* Header files should be included in a sequence */ /* Standard header files required go first */ +#include + #include "vtr_strong_id.h" #include "vtr_geometry.h" @@ -100,7 +102,7 @@ typedef vtr::StrongId CircuitEdgeId; * 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model * * ------ Design technology information ----- - * 1. design_tech_: the design technology [cmos|rram] for each circuit model + * 1. design_tech_types_: the design technology [cmos|rram] for each circuit model * 2. power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND) * * ------ Buffer existence ----- @@ -210,20 +212,43 @@ class CircuitLibrary { typedef vtr::Range circuit_edge_range; /* local enumeration for buffer existence */ enum e_buffer_type: unsigned char{ - INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INV, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ + INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INVERTER, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ }; public: /* Constructors */ public: /* Accessors: aggregates */ circuit_model_range circuit_models() const; - public: /* Accessors: Basic data query */ - public: /* Accessors: Methods to find circuit model */ + public: /* Public Accessors: Basic data query */ + public: /* Public Accessors: Methods to find circuit model */ CircuitModelId get_circuit_model_id_by_name(const std::string& name) const ; CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const; - public: /* Mutators */ + public: /* Public Mutators */ CircuitModelId add_circuit_model(); - public: /* Internal mutators */ + void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type); + void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name); + void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix); + void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist); + void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist); + void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default); + void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog); + void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); + void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); + void set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated); + void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + public: /* Internal mutators: link circuit_models */ + void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); - private: /* Internal validators */ + public: /* Internal mutators: build fast look-ups */ + void build_circuit_model_lookup(); + private: /* Internal invalidators/validators */ + /* Validators */ + bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; + /* Invalidators */ + void invalidate_circuit_model_lookup() const; + void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; private: /* Internal data */ /* Fundamental information */ vtr::vector circuit_model_ids_; @@ -240,15 +265,15 @@ class CircuitLibrary { */ typedef std::vector> CircuitModelLookup; mutable CircuitModelLookup circuit_model_lookup_; /* [circuit_model_type][circuit_model_ids] */ - typedef std::vector>>> CircuitModelPortLookup; - mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_type][circuit_model_id][port_type][port_ids] */ + typedef std::vector>> CircuitModelPortLookup; + mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_id][port_type][port_ids] */ /* Verilog generator options */ vtr::vector dump_structural_verilog_; vtr::vector dump_explicit_port_map_; /* Design technology information */ - vtr::vector design_tech_; + vtr::vector design_tech_types_; vtr::vector power_gated_; /* Buffer existence */ From 9f8c7a3fc74e86142f199f65ad883a2ecb6a8593 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 17:47:39 -0600 Subject: [PATCH 026/482] adding port mutators --- .../fpga_spice_include/circuit_library.cpp | 80 ++++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 73 +++++++++++------ .../SRC/fpga_spice_include/spice_types.h | 6 +- 3 files changed, 132 insertions(+), 27 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 2a6e32756..3bc99a079 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -117,11 +117,12 @@ CircuitModelId CircuitLibrary::add_circuit_model() { buffer_circuit_model_names_.emplace_back(); buffer_circuit_model_ids_.emplace_back(); - /* Pass-gate-related parameters */ + /* Pass-gate-related parameters */ pass_gate_logic_circuit_model_names_.emplace_back(); pass_gate_logic_circuit_model_ids_.emplace_back(); /* Port information */ + port_ids_.emplace_back(); port_types_.emplace_back(); port_sizes_.emplace_back(); port_prefix_.emplace_back(); @@ -334,6 +335,77 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitMode return; } +/* Set pass-gate logic information of a circuit model */ +void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + pass_gate_logic_circuit_model_names_[circuit_model_id] = circuit_model_name; + return; +} + +/* Add a port to a circuit model */ +CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Create a port id */ + CircuitPortId circuit_port_id = CircuitPortId(port_ids_[circuit_model_id].size()); + /* Update the id list */ + port_ids_[circuit_model_id].push_back(circuit_port_id); + + /* Initialize other attributes */ + port_types_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); + port_sizes_[circuit_model_id].push_back(-1); + port_prefix_[circuit_model_id].emplace_back(); + port_lib_names_[circuit_model_id].emplace_back(); + port_inv_prefix_[circuit_model_id].emplace_back(); + port_is_mode_select_[circuit_model_id].push_back(false); + port_is_global_[circuit_model_id].push_back(false); + port_is_reset_[circuit_model_id].push_back(false); + port_is_set_[circuit_model_id].push_back(false); + port_is_config_enable_[circuit_model_id].push_back(false); + port_is_prog_[circuit_model_id].push_back(false); + port_circuit_model_names_[circuit_model_id].emplace_back(); + port_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); + port_inv_circuit_model_names_[circuit_model_id].emplace_back(); + port_inv_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); + port_tri_state_maps_[circuit_model_id].emplace_back(); + port_lut_frac_level_[circuit_model_id].push_back(-1); + port_lut_output_masks_[circuit_model_id].emplace_back(); + port_sram_orgz_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); + + return circuit_port_id; +} + +/* Set the type for a port of a circuit model */ +void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_spice_model_port_type& port_type) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_types_[circuit_model_id][circuit_port_id] = port_type; + return; +} + +/* Set the size for a port of a circuit model */ +void CircuitLibrary::set_port_sizes(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& port_size) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_sizes_[circuit_model_id][circuit_port_id] = port_size; + return; +} + +/* Set the prefix for a port of a circuit model */ +void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& port_prefix) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_prefix_[circuit_model_id][circuit_port_id] = port_prefix; + return; +} + /************************************************************************ * Internal Mutators ***********************************************************************/ @@ -411,6 +483,12 @@ bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_ return ( size_t(circuit_model_id) < circuit_model_ids_.size() ) && ( circuit_model_id == circuit_model_ids_[circuit_model_id] ); } +bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); +} + /* Invalidators */ /* Empty fast lookup for circuit_models*/ void CircuitLibrary::invalidate_circuit_model_lookup() const { diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index b6a5464b4..4a0e791a1 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -117,25 +117,26 @@ typedef vtr::StrongId CircuitEdgeId; * 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic * * ------ Port information ------ - * 1. port_types_: types of ports belonging to a circuit model - * 2. port_sizes_: width of ports belonging to a circuit model - * 3. port_prefix_: prefix of a port when instance of a circuit model - * 4. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled - * 5. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port - * 6. port_is_mode_select: specify if this port is used to select operating modes of the circuit model - * 7. port_is_global: specify if this port is a global signal shared by other circuit model - * 8. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches - * 9. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches - * 10. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 11. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 12. port_circuit_model_name: the name of circuit model linked to the port - * 13. port_circuit_model_ids_: the Id of circuit model linked to the port - * 14. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port - * 15. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port - * 16. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 17. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 18. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 19. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 1. port_ids_: unique id of ports belonging to a circuit model + * 2. port_types_: types of ports belonging to a circuit model + * 3. port_sizes_: width of ports belonging to a circuit model + * 4. port_prefix_: prefix of a port when instance of a circuit model + * 5. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled + * 6. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port + * 7. port_is_mode_select: specify if this port is used to select operating modes of the circuit model + * 8. port_is_global: specify if this port is a global signal shared by other circuit model + * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches + * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches + * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches + * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 13. port_circuit_model_name: the name of circuit model linked to the port + * 14. port_circuit_model_ids_: the Id of circuit model linked to the port + * 15. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port + * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -223,21 +224,43 @@ class CircuitLibrary { CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const; public: /* Public Mutators */ CircuitModelId add_circuit_model(); + /* Fundamental information */ void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type); void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name); void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix); void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist); void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist); void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default); + /* Verilog generator options */ void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog); void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); + /* Design technology information */ void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); void set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated); - void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + /* Buffer existence */ + void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, + const bool& existence, const std::string& circuit_model_name); + /* Pass-gate-related parameters */ + void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name); + /* Port information */ + CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id); + void set_port_types(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_spice_model_port_type& port_type); + void set_port_sizes(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& port_size); + void set_port_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& port_prefix); public: /* Internal mutators: link circuit_models */ void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); @@ -246,6 +269,7 @@ class CircuitLibrary { private: /* Internal invalidators/validators */ /* Validators */ bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; + bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; /* Invalidators */ void invalidate_circuit_model_lookup() const; void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; @@ -286,6 +310,7 @@ class CircuitLibrary { vtr::vector pass_gate_logic_circuit_model_ids_; /* Port information */ + vtr::vector> port_ids_; vtr::vector> port_types_; vtr::vector> port_sizes_; vtr::vector> port_prefix_; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index d3ad32ae7..7711285a2 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -87,7 +87,8 @@ enum e_spice_model_port_type { SPICE_MODEL_PORT_BL, SPICE_MODEL_PORT_BLB, SPICE_MODEL_PORT_WL, - SPICE_MODEL_PORT_WLB + SPICE_MODEL_PORT_WLB, + NUM_CIRCUIT_MODEL_PORT_TYPES }; /* For process corner */ @@ -102,7 +103,8 @@ enum e_sram_orgz { SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ - SPICE_SRAM_LOCAL_ENCODER /* SRAMs are organized and accessed by a local encoder */ + SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */ + NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES }; enum e_spice_accuracy_type { From 03a64e2ad815222fc5db169373a4576273a566aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 20:54:27 -0600 Subject: [PATCH 027/482] complete the mutators for ports --- .../fpga_spice_include/circuit_library.cpp | 167 ++++++++++++++++++ .../SRC/fpga_spice_include/circuit_library.h | 48 +++++ 2 files changed, 215 insertions(+) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 3bc99a079..8a3943b18 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -406,6 +406,173 @@ void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id, return; } +/* Set the lib_name for a port of a circuit model */ +void CircuitLibrary::set_port_lib_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& lib_name) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_lib_names_[circuit_model_id][circuit_port_id] = lib_name; + return; +} + +/* Set the inv_prefix for a port of a circuit model */ +void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& inv_prefix) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_inv_prefix_[circuit_model_id][circuit_port_id] = inv_prefix; + return; +} + +/* Set the is_mode_select for a port of a circuit model */ +void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_mode_select) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_is_mode_select_[circuit_model_id][circuit_port_id] = is_mode_select; + return; +} + +/* Set the is_global for a port of a circuit model */ +void CircuitLibrary::set_port_is_global(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_global) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_is_global_[circuit_model_id][circuit_port_id] = is_global; + return; +} + +/* Set the is_reset for a port of a circuit model */ +void CircuitLibrary::set_port_is_reset(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_reset) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_is_reset_[circuit_model_id][circuit_port_id] = is_reset; + return; +} + +/* Set the is_set for a port of a circuit model */ +void CircuitLibrary::set_port_is_set(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_set) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_is_set_[circuit_model_id][circuit_port_id] = is_set; + return; +} + +/* Set the is_config_enable for a port of a circuit model */ +void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_config_enable) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_is_config_enable_[circuit_model_id][circuit_port_id] = is_config_enable; + return; +} + +/* Set the is_prog for a port of a circuit model */ +void CircuitLibrary::set_port_is_prog(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_prog) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_is_prog_[circuit_model_id][circuit_port_id] = is_prog; + return; +} + +/* Set the circuit_model_name for a port of a circuit model */ +void CircuitLibrary::set_port_circuit_model_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& circuit_model_name) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_circuit_model_names_[circuit_model_id][circuit_port_id] = circuit_model_name; + return; +} + +/* Set the circuit_model_id for a port of a circuit model */ +void CircuitLibrary::set_port_circuit_model_id(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const CircuitModelId& port_circuit_model_id) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_circuit_model_ids_[circuit_model_id][circuit_port_id] = port_circuit_model_id; + return; +} + +/* Set the inv_circuit_model_name for a port of a circuit model */ +void CircuitLibrary::set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& inv_circuit_model_name) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_inv_circuit_model_names_[circuit_model_id][circuit_port_id] = inv_circuit_model_name; + return; +} + +/* Set the inv_circuit_model_id for a port of a circuit model */ +void CircuitLibrary::set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const CircuitModelId& inv_circuit_model_id) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_inv_circuit_model_ids_[circuit_model_id][circuit_port_id] = inv_circuit_model_id; + return; +} + +/* Set the tri-state map for a port of a circuit model */ +void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& tri_state_map) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_tri_state_maps_[circuit_model_id][circuit_port_id] = tri_state_map; + return; +} + +/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ +void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& lut_frac_level) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Make sure this is a LUT */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + port_lut_frac_level_[circuit_model_id][circuit_port_id] = lut_frac_level; + return; +} + +/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ +void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::vector& lut_output_masks) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Make sure this is a LUT */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + port_lut_output_masks_[circuit_model_id][circuit_port_id] = lut_output_masks; + return; +} + +/* Set the SRAM organization for a port of a circuit model, only applicable to SRAM ports */ +void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_sram_orgz& sram_orgz) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Make sure this is a SRAM port */ + VTR_ASSERT_SAFE(SPICE_MODEL_PORT_SRAM == port_types_[circuit_model_id][circuit_port_id]); + port_sram_orgz_[circuit_model_id][circuit_port_id] = sram_orgz; + return; +} + + /************************************************************************ * Internal Mutators ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 4a0e791a1..b9918fbeb 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -261,6 +261,54 @@ class CircuitLibrary { void set_port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix); + void set_port_lib_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& lib_name); + void set_port_inv_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& inv_prefix); + void set_port_is_mode_select(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_mode_select); + void set_port_is_global(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_global); + void set_port_is_reset(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_reset); + void set_port_is_set(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_set); + void set_port_is_config_enable(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_config_enable); + void set_port_is_prog(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const bool& is_prog); + void set_port_circuit_model_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& circuit_model_name); + void set_port_circuit_model_id(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const CircuitModelId& port_circuit_model_id); + void set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& inv_circuit_model_name); + void set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const CircuitModelId& inv_circuit_model_id); + void set_port_tri_state_map(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::string& tri_state_map); + void set_port_lut_frac_level(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& lut_frac_level); + void set_port_lut_output_mask(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const std::vector& lut_output_masks); + void set_port_sram_orgz(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_sram_orgz& sram_orgz); public: /* Internal mutators: link circuit_models */ void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); From 5b0c9572c3347c5b4e012fa94212c7b8755e85b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 7 Aug 2019 21:19:16 -0600 Subject: [PATCH 028/482] add mutators for delay_info --- .../fpga_spice_include/circuit_library.cpp | 62 +++++++++++++++++++ .../SRC/fpga_spice_include/circuit_library.h | 13 ++++ .../SRC/fpga_spice_include/spice_types.h | 3 +- 3 files changed, 77 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 8a3943b18..74270df51 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -572,6 +572,62 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, return; } +/* Delay information */ +/* Add a delay info: + * Check if the delay type is in the range of vector + * if yes, assign values + * if no, resize and assign values + */ +void CircuitLibrary::add_delay_info(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Check the range of vector */ + if (size_t(delay_type) >= delay_types_[circuit_model_id].size()) { + /* Resize */ + delay_types_[circuit_model_id].resize(size_t(delay_type) + 1); + delay_in_port_names_[circuit_model_id].resize(size_t(delay_type) + 1); + delay_out_port_names_[circuit_model_id].resize(size_t(delay_type) + 1); + delay_values_[circuit_model_id].resize(size_t(delay_type) + 1); + } + delay_types_[circuit_model_id][size_t(delay_type)] = delay_type; + return; +} + +void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type, + const std::string& in_port_names) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Validate delay_type */ + VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + delay_in_port_names_[circuit_model_id][size_t(delay_type)] = in_port_names; + return; +} + +void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type, + const std::string& out_port_names) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Validate delay_type */ + VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + delay_out_port_names_[circuit_model_id][size_t(delay_type)] = out_port_names; + return; +} + +void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type, + const std::string& delay_values) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Validate delay_type */ + VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + delay_values_[circuit_model_id][size_t(delay_type)] = delay_values; + return; +} + +/* Buffer/Inverter-related parameters */ /************************************************************************ * Internal Mutators @@ -656,6 +712,12 @@ bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_i return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); } +bool CircuitLibrary::valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return ( size_t(delay_type) < delay_types_[circuit_model_id].size() ) && ( delay_type == delay_types_[circuit_model_id][size_t(delay_type)] ); +} + /* Invalidators */ /* Empty fast lookup for circuit_models*/ void CircuitLibrary::invalidate_circuit_model_lookup() const { diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index b9918fbeb..a918ff369 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -309,6 +309,18 @@ class CircuitLibrary { void set_port_sram_orgz(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz); + /* Delay information */ + void add_delay_info(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type); + void set_delay_in_port_names(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type, + const std::string& in_port_names); + void set_delay_out_port_names(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type, + const std::string& out_port_names); + void set_delay_values(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type, + const std::string& delay_values); public: /* Internal mutators: link circuit_models */ void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); @@ -318,6 +330,7 @@ class CircuitLibrary { /* Validators */ bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; /* Invalidators */ void invalidate_circuit_model_lookup() const; void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index 7711285a2..d16c2de5d 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -12,7 +12,8 @@ enum e_spice_tech_lib_type { enum spice_model_delay_type { SPICE_MODEL_DELAY_RISE, - SPICE_MODEL_DELAY_FALL + SPICE_MODEL_DELAY_FALL, + NUM_CIRCUIT_MODEL_DELAY_TYPES }; /*Struct for a SPICE model of a module*/ From ad8c33e1bafc276359c1fd64054dfc7545b018cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 8 Aug 2019 11:33:11 -0600 Subject: [PATCH 029/482] complete the mutators --- libs/libvtrutil/src/vtr_geometry.h | 3 + libs/libvtrutil/src/vtr_geometry.tpp | 10 + .../fpga_spice_include/circuit_library.cpp | 286 +++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 64 +++- 4 files changed, 348 insertions(+), 15 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index e19dff1c0..ce9cfe59f 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -60,6 +60,9 @@ class Point { friend bool operator== <>(Point lhs, Point rhs); friend bool operator!= <>(Point lhs, Point rhs); friend bool operator< <>(Point lhs, Point rhs); + public: //Mutators + void set_x(T x_val); + void set_y(T y_val); private: T x_; T y_; diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index b06f29189..76b1ad457 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -42,6 +42,16 @@ namespace vtr { return std::make_tuple(lhs.x(), lhs.y()) < std::make_tuple(rhs.x(), rhs.y()); } + template + void Point::set_x(T x_val) { + x_ = x_val; + } + + template + void Point::set_y(T y_val) { + y_ = y_val; + } + /* * Rect */ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 74270df51..c56a956de 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -54,6 +54,27 @@ CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); } +/************************************************************************ + * Public Accessors : Basic data query + ***********************************************************************/ +enum e_spice_model_type CircuitLibrary::circuit_model_type(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return circuit_model_types_[circuit_model_id]; +} + +enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_types_[circuit_model_id][circuit_port_id]; +} + +enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return design_tech_types_[circuit_model_id]; +} /************************************************************************ * Public Accessors : Methods to find circuit model @@ -163,22 +184,19 @@ CircuitModelId CircuitLibrary::add_circuit_model() { buffer_types_.push_back(NUM_CIRCUIT_MODEL_BUF_TYPES); buffer_location_maps_.emplace_back(); buffer_sizes_.push_back(-1); - buffer_is_tapered_.push_back(false); buffer_num_levels_.push_back(-1); buffer_f_per_stage_.push_back(-1); /* Pass-gate-related parameters */ pass_gate_logic_types_.push_back(NUM_CIRCUIT_MODEL_PASS_GATE_TYPES); - pass_gate_logic_nmos_sizes_.push_back(-1); - pass_gate_logic_pmos_sizes_.push_back(-1); + pass_gate_logic_sizes_.emplace_back(); /* Multiplexer-related parameters */ mux_structure_.push_back(NUM_CIRCUIT_MODEL_STRUCTURE_TYPES); mux_num_levels_.push_back(-1); - mux_add_const_input_.push_back(false); mux_const_input_values_.push_back(-1); mux_use_local_encoder_.push_back(false); - mux_advanced_rram_design_.push_back(false); + mux_use_advanced_rram_design_.push_back(false); /* LUT-related parameters */ lut_is_fracturable_.push_back(false); @@ -543,7 +561,7 @@ void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& circuit_model /* validate the circuit_port_id */ VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); port_lut_frac_level_[circuit_model_id][circuit_port_id] = lut_frac_level; return; } @@ -555,7 +573,7 @@ void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& circuit_mode /* validate the circuit_port_id */ VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); port_lut_output_masks_[circuit_model_id][circuit_port_id] = lut_output_masks; return; } @@ -567,7 +585,7 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, /* validate the circuit_port_id */ VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Make sure this is a SRAM port */ - VTR_ASSERT_SAFE(SPICE_MODEL_PORT_SRAM == port_types_[circuit_model_id][circuit_port_id]); + VTR_ASSERT_SAFE(SPICE_MODEL_PORT_SRAM == port_type(circuit_model_id, circuit_port_id)); port_sram_orgz_[circuit_model_id][circuit_port_id] = sram_orgz; return; } @@ -617,8 +635,8 @@ void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& circuit_mode } void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, - const enum spice_model_delay_type& delay_type, - const std::string& delay_values) { + const enum spice_model_delay_type& delay_type, + const std::string& delay_values) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); /* Validate delay_type */ @@ -628,6 +646,254 @@ void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, } /* Buffer/Inverter-related parameters */ +void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_buffer_type& buffer_type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + buffer_types_[circuit_model_id] = buffer_type; + return; +} + +void CircuitLibrary::set_buffer_location_map(const CircuitModelId& circuit_model_id, + const std::string& location_map) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + buffer_location_maps_[circuit_model_id] = location_map; + return; +} + +void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id, + const size_t& buffer_size) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + buffer_sizes_[circuit_model_id] = buffer_size; + return; +} + +void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& circuit_model_id, + const size_t& num_levels) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + buffer_num_levels_[circuit_model_id] = num_levels; + return; +} + +void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, + const size_t& f_per_stage) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + buffer_f_per_stage_[circuit_model_id] = f_per_stage; + return; +} + +/* Pass-gate-related parameters */ +void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); + pass_gate_logic_types_[circuit_model_id] = pass_gate_logic_type; + return; +} + +void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, + const size_t& nmos_size) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); + pass_gate_logic_sizes_[circuit_model_id].set_x(nmos_size); + return; +} + +void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, + const size_t& pmos_size) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be BUFFER or INVERTER */ + VTR_ASSERT_SAFE(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); + pass_gate_logic_sizes_[circuit_model_id].set_y(pmos_size); + return; +} + +/* Multiplexer-related parameters */ +void CircuitLibrary::set_mux_structure(const CircuitModelId& circuit_model_id, + const enum e_spice_model_structure& mux_structure) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX */ + VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + mux_structure_[circuit_model_id] = mux_structure; + return; +} + +void CircuitLibrary::set_mux_num_levels(const CircuitModelId& circuit_model_id, + const size_t& num_levels) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX */ + VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + mux_num_levels_[circuit_model_id] = num_levels; + return; +} + +void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& circuit_model_id, + const size_t& const_input_value) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX */ + VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + mux_const_input_values_[circuit_model_id] = const_input_value; + return; +} + +void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, + const bool& use_local_encoder) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX */ + VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + mux_use_local_encoder_[circuit_model_id] = use_local_encoder; + return; +} + +void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, + const bool& use_advanced_rram_design) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX */ + VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + mux_use_advanced_rram_design_[circuit_model_id] = use_advanced_rram_design; + return; +} + +/* LUT-related parameters */ +void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_id, + const bool& is_fracturable) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be LUT */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); + lut_is_fracturable_[circuit_model_id] = is_fracturable; + return; +} + +/* RRAM-related design technology information */ +void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id, + const float& rlrs) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the design_tech of this circuit_model should be RRAM */ + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + rram_res_[circuit_model_id].set_x(rlrs); + return; +} + +void CircuitLibrary::set_rram_rhrs(const CircuitModelId& circuit_model_id, + const float& rhrs) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the design_tech of this circuit_model should be RRAM */ + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + rram_res_[circuit_model_id].set_y(rhrs); + return; +} + +void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, + const float& wprog_set_nmos) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the design_tech of this circuit_model should be RRAM */ + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + wprog_set_[circuit_model_id].set_x(wprog_set_nmos); + return; +} + +void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, + const float& wprog_set_pmos) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the design_tech of this circuit_model should be RRAM */ + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + wprog_set_[circuit_model_id].set_y(wprog_set_pmos); + return; +} + +void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, + const float& wprog_reset_nmos) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the design_tech of this circuit_model should be RRAM */ + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + wprog_reset_[circuit_model_id].set_x(wprog_reset_nmos); + return; +} + +void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, + const float& wprog_reset_pmos) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the design_tech of this circuit_model should be RRAM */ + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + wprog_reset_[circuit_model_id].set_y(wprog_reset_pmos); + return; +} + +/* Wire parameters */ +void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, + const enum e_wire_model_type& wire_type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ + VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + wire_types_[circuit_model_id] = wire_type; + return; +} + +void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, + const float& r_val) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ + VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + wire_rc_[circuit_model_id].set_x(r_val); + return; +} + +void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, + const float& c_val) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ + VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + wire_rc_[circuit_model_id].set_y(c_val); + return; +} + +void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, + const size_t& num_level) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ + VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + wire_num_levels_[circuit_model_id] = num_level; + return; +} /************************************************************************ * Internal Mutators diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index a918ff369..b175622a5 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -218,6 +218,9 @@ class CircuitLibrary { public: /* Constructors */ public: /* Accessors: aggregates */ circuit_model_range circuit_models() const; + enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; + enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + enum e_spice_model_design_tech design_tech_type(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query */ public: /* Public Accessors: Methods to find circuit model */ CircuitModelId get_circuit_model_id_by_name(const std::string& name) const ; @@ -321,6 +324,60 @@ class CircuitLibrary { void set_delay_values(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type, const std::string& delay_values); + /* Buffer/Inverter-related parameters */ + void set_buffer_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_buffer_type& buffer_type); + void set_buffer_location_map(const CircuitModelId& circuit_model_id, + const std::string& location_map); + void set_buffer_size(const CircuitModelId& circuit_model_id, + const size_t& buffer_size); + void set_buffer_num_levels(const CircuitModelId& circuit_model_id, + const size_t& num_levels); + void set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, + const size_t& f_per_stage); + /* Pass-gate-related parameters */ + void set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type); + void set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, + const size_t& nmos_size); + void set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, + const size_t& pmos_size); + /* Multiplexer-related parameters */ + void set_mux_structure(const CircuitModelId& circuit_model_id, + const enum e_spice_model_structure& mux_structure); + void set_mux_num_levels(const CircuitModelId& circuit_model_id, + const size_t& num_levels); + void set_mux_const_input_value(const CircuitModelId& circuit_model_id, + const size_t& const_input_value); + void set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, + const bool& use_local_encoder); + void set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, + const bool& use_advanced_rram_design); + /* LUT-related parameters */ + void set_lut_is_fracturable(const CircuitModelId& circuit_model_id, + const bool& is_fracturable); + /* RRAM-related design technology information */ + void set_rram_rlrs(const CircuitModelId& circuit_model_id, + const float& rlrs); + void set_rram_rhrs(const CircuitModelId& circuit_model_id, + const float& rhrs); + void set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, + const float& wprog_set_nmos); + void set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, + const float& wprog_set_pmos); + void set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, + const float& wprog_reset_nmos); + void set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, + const float& wprog_reset_pmos); + /* Wire parameters */ + void set_wire_type(const CircuitModelId& circuit_model_id, + const enum e_wire_model_type& wire_type); + void set_wire_r(const CircuitModelId& circuit_model_id, + const float& r_val); + void set_wire_c(const CircuitModelId& circuit_model_id, + const float& c_val); + void set_wire_num_levels(const CircuitModelId& circuit_model_id, + const size_t& num_level); public: /* Internal mutators: link circuit_models */ void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); @@ -413,22 +470,19 @@ class CircuitLibrary { vtr::vector buffer_types_; vtr::vector buffer_location_maps_; vtr::vector buffer_sizes_; - vtr::vector buffer_is_tapered_; vtr::vector buffer_num_levels_; vtr::vector buffer_f_per_stage_; /* Pass-gate-related parameters */ vtr::vector pass_gate_logic_types_; - vtr::vector pass_gate_logic_nmos_sizes_; - vtr::vector pass_gate_logic_pmos_sizes_; + vtr::vector> pass_gate_logic_sizes_; /* x=> nmos_size; y => pmos_size */ /* Multiplexer-related parameters */ vtr::vector mux_structure_; vtr::vector mux_num_levels_; - vtr::vector mux_add_const_input_; vtr::vector mux_const_input_values_; vtr::vector mux_use_local_encoder_; - vtr::vector mux_advanced_rram_design_; + vtr::vector mux_use_advanced_rram_design_; /* LUT-related parameters */ vtr::vector lut_is_fracturable_; From e19485bbb7ed257c2e99c07096fc525aec0d1d92 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 8 Aug 2019 14:16:29 -0600 Subject: [PATCH 030/482] add more accessors and more to be added when plug into framework --- .../fpga_spice_include/circuit_library.cpp | 182 +++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 32 ++- 2 files changed, 201 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index c56a956de..ff78158fe 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -55,14 +55,105 @@ CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { } /************************************************************************ - * Public Accessors : Basic data query + * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ +/* Access the type of a circuit model */ enum e_spice_model_type CircuitLibrary::circuit_model_type(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); return circuit_model_types_[circuit_model_id]; } +/* Access the name of a circuit model */ +std::string CircuitLibrary::circuit_model_name(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return circuit_model_names_[circuit_model_id]; +} + +/* Access the prefix of a circuit model */ +std::string CircuitLibrary::circuit_model_prefix(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return circuit_model_prefix_[circuit_model_id]; +} + +/* Access the path + file of user-defined verilog netlist of a circuit model */ +std::string CircuitLibrary::circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return circuit_model_verilog_netlists_[circuit_model_id]; +} + +/* Access the path + file of user-defined spice netlist of a circuit model */ +std::string CircuitLibrary::circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return circuit_model_spice_netlists_[circuit_model_id]; +} + +/* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */ +bool CircuitLibrary::circuit_model_is_default(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return circuit_model_is_default_[circuit_model_id]; +} + +/* Access the dump_structural_verilog flag of a circuit model */ +bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return dump_structural_verilog_[circuit_model_id]; +} + +/* Access the dump_explicit_port_map flag of a circuit model */ +bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return dump_explicit_port_map_[circuit_model_id]; +} + +/* Access the design technology type of a circuit model */ +enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return design_tech_types_[circuit_model_id]; +} + +/* Access the is_power_gated flag of a circuit model */ +bool CircuitLibrary::is_power_gated(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return is_power_gated_[circuit_model_id]; +} + +/* Return a flag showing if inputs are buffered for a circuit model */ +bool CircuitLibrary::is_input_buffered(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return buffer_existence_[circuit_model_id][INPUT]; +} + +/* Return a flag showing if outputs are buffered for a circuit model */ +bool CircuitLibrary::is_output_buffered(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return buffer_existence_[circuit_model_id][OUTPUT]; +} + +/* Return a flag showing if intermediate stages of a LUT are buffered for a circuit model */ +bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate the circuit model type is LUT */ + VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); + return buffer_existence_[circuit_model_id][LUT_INTER_BUFFER]; +} + +/************************************************************************ + * Public Accessors : Basic data query on Circuit Porst + ***********************************************************************/ +/* Access the type of a port of a circuit model */ enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ @@ -70,12 +161,87 @@ enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& cir return port_types_[circuit_model_id][circuit_port_id]; } -enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - return design_tech_types_[circuit_model_id]; +/* Access the type of a port of a circuit model */ +size_t CircuitLibrary::port_size(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_sizes_[circuit_model_id][circuit_port_id]; } +/* Access the prefix of a port of a circuit model */ +std::string CircuitLibrary::port_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_prefix_[circuit_model_id][circuit_port_id]; +} + +/* Access the lib_name of a port of a circuit model */ +std::string CircuitLibrary::port_lib_name(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_lib_names_[circuit_model_id][circuit_port_id]; +} + +/* Access the inv_prefix of a port of a circuit model */ +std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_inv_prefix_[circuit_model_id][circuit_port_id]; +} + +/* Return a flag if the port is used in mode-selection purpuse of a circuit model */ +bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_is_mode_select_[circuit_model_id][circuit_port_id]; +} + +/* Return a flag if the port is a global one of a circuit model */ +bool CircuitLibrary::port_is_global(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_is_global_[circuit_model_id][circuit_port_id]; +} + +/* Return a flag if the port does a reset functionality in a circuit model */ +bool CircuitLibrary::port_is_reset(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_is_reset_[circuit_model_id][circuit_port_id]; +} + +/* Return a flag if the port does a set functionality in a circuit model */ +bool CircuitLibrary::port_is_set(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_is_set_[circuit_model_id][circuit_port_id]; +} + +/* Return a flag if the port enables a configuration in a circuit model */ +bool CircuitLibrary::port_is_config_enable(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_is_config_enable_[circuit_model_id][circuit_port_id]; +} + +/* Return a flag if the port is used during programming a FPGA in a circuit model */ +bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_is_prog_[circuit_model_id][circuit_port_id]; +} + + /************************************************************************ * Public Accessors : Methods to find circuit model ***********************************************************************/ @@ -131,7 +297,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() { /* Design technology information */ design_tech_types_.push_back(NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES); - power_gated_.push_back(false); + is_power_gated_.push_back(false); /* Buffer existence */ buffer_existence_.emplace_back(); @@ -294,10 +460,10 @@ void CircuitLibrary::set_circuit_model_design_tech_type(const CircuitModelId& ci } /* Set the power-gated flag of a Circuit Model */ -void CircuitLibrary::set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated) { +void CircuitLibrary::set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - power_gated_[circuit_model_id] = power_gated; + is_power_gated_[circuit_model_id] = is_power_gated; return; } diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index b175622a5..b129ab089 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -103,7 +103,7 @@ typedef vtr::StrongId CircuitEdgeId; * * ------ Design technology information ----- * 1. design_tech_types_: the design technology [cmos|rram] for each circuit model - * 2. power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND) + * 2. is_power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND) * * ------ Buffer existence ----- * Use vectors to simplify the defition of buffer existence: @@ -217,11 +217,33 @@ class CircuitLibrary { }; public: /* Constructors */ public: /* Accessors: aggregates */ + public: /* Public Accessors: Basic data query on Circuit Models*/ circuit_model_range circuit_models() const; enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + std::string circuit_model_name(const CircuitModelId& circuit_model_id) const; + std::string circuit_model_prefix(const CircuitModelId& circuit_model_id) const; + std::string circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const; + std::string circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const; + bool circuit_model_is_default(const CircuitModelId& circuit_model_id) const; + bool dump_structural_verilog(const CircuitModelId& circuit_model_id) const; + bool dump_explicit_port_map(const CircuitModelId& circuit_model_id) const; enum e_spice_model_design_tech design_tech_type(const CircuitModelId& circuit_model_id) const; - public: /* Public Accessors: Basic data query */ + bool is_power_gated(const CircuitModelId& circuit_model_id) const; + bool is_input_buffered(const CircuitModelId& circuit_model_id) const; + bool is_output_buffered(const CircuitModelId& circuit_model_id) const; + bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; + public: /* Public Accessors: Basic data query on Circuit Ports*/ + enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + std::string port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + std::string port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_set(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Methods to find circuit model */ CircuitModelId get_circuit_model_id_by_name(const std::string& name) const ; CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const; @@ -239,7 +261,7 @@ class CircuitLibrary { void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); /* Design technology information */ void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); - void set_circuit_model_power_gated(const CircuitModelId& circuit_model_id, const bool& power_gated); + void set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated); /* Buffer existence */ void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); @@ -416,7 +438,7 @@ class CircuitLibrary { /* Design technology information */ vtr::vector design_tech_types_; - vtr::vector power_gated_; + vtr::vector is_power_gated_; /* Buffer existence */ vtr::vector> buffer_existence_; From 0b46adb5efaf13367eb0cd42adfa2d8d60f65328 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 8 Aug 2019 15:17:43 -0600 Subject: [PATCH 031/482] Correction to the explicit Verilog for FPGAs above 2x2 --- .../verilog/verilog_compact_netlist.c | 11 ++++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 38 +++++++++++++++++-- .../SRC/fpga_x2p/verilog/verilog_routing.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 8 ++++ .../SRC/fpga_x2p/verilog/verilog_tcl_utils.c | 4 ++ .../verilog/verilog_top_netlist_utils.c | 4 ++ 6 files changed, 59 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4c0ec145f..c38ba3b3a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -789,14 +789,15 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); + DeviceCoordinator unique_chan_coordinator = unique_mirror.get_side_block_coordinator(side_manager.get_side()); fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + gen_verilog_routing_channel_one_pin_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack), + unique_chan_coordinator.get_x(), unique_chan_coordinator.get_y(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack))); } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), @@ -815,6 +816,8 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } @@ -964,6 +967,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 14d200038..30ac68c03 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -313,6 +313,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping) { int height; @@ -360,7 +361,7 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(unique_x, unique_y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -565,6 +566,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, + 0, 0, /* No explicit mapping*/ FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: @@ -667,6 +669,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, + 0, /*Used in more recent version*/ + 0, /*Used in more recent version*/ FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: @@ -767,12 +771,16 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Find grid_x and grid_y */ grid_x = drive_rr_nodes[inode]->xlow; grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print a grid pin */ fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ + FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1029,7 +1037,9 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, false); + grid_x, grid_y, + 0,0,/*No explicit mapping */ + FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1803,6 +1813,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, } /* Dump OPINs of adjacent CLBs */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -1810,6 +1821,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ if (FALSE == dump_port_type) { fprintf(fp, ",\n"); @@ -2078,7 +2091,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ + 0,0, /*No explicit mapping */ + TRUE, false); /* Dump the direction of the port ! */ } } @@ -2315,6 +2329,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ + puts("CHECK4"); + const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -2322,6 +2338,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2524,6 +2542,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2772,6 +2792,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -2849,6 +2870,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3006,6 +3028,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3253,6 +3276,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,/*No explicit mapping*/ + 0,/*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3582,6 +3607,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, + 0,/*No explicit mapping */ + 0,/*No explicit mapping */ TRUE, false); } @@ -3785,6 +3812,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert((1 == side_cnt)||(2 == side_cnt)); side_cnt = 0; + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print the ports of grids*/ /* only check ipin_rr_nodes of cur_cb_info */ for (side = 0; side < cur_cb_info->num_sides; side++) { @@ -3802,6 +3830,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ TRUE, is_explicit_mapping); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index b126300e7..24b805a6b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -14,6 +14,7 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index b70163422..4311c341f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -638,6 +638,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -723,6 +725,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -1769,6 +1773,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } @@ -1827,6 +1833,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 256f281a9..c3df4ed95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -187,6 +187,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } @@ -231,6 +233,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index f3cc2c5b9..8e52d6f5a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -686,6 +686,8 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } @@ -833,6 +835,8 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, + 0, /*Used in a more recent version*/ + 0, /*Used in a more recent version*/ FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } From 158c67075e8c47aa592f37c2e945fb67eca86927 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 8 Aug 2019 17:25:27 -0600 Subject: [PATCH 032/482] built a conversion from spice_models to circuit_library and plug in --- .../fpga_spice_include/circuit_library.cpp | 77 ++++-- .../SRC/fpga_spice_include/circuit_library.h | 41 ++- .../SRC/fpga_spice_include/circuit_types.h | 144 ++++++++++ .../SRC/fpga_spice_include/spice_types.h | 86 +----- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 260 +++++++++++++++++- 5 files changed, 480 insertions(+), 128 deletions(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index ff78158fe..6e067ce3e 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -193,6 +193,15 @@ std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_ return port_inv_prefix_[circuit_model_id][circuit_port_id]; } +/* Return the default value of a port of a circuit model */ +size_t CircuitLibrary::port_default_value(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return port_default_values_[circuit_model_id][circuit_port_id]; +} + + /* Return a flag if the port is used in mode-selection purpuse of a circuit model */ bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { @@ -303,6 +312,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() { buffer_existence_.emplace_back(); buffer_circuit_model_names_.emplace_back(); buffer_circuit_model_ids_.emplace_back(); + buffer_location_maps_.emplace_back(); /* Pass-gate-related parameters */ pass_gate_logic_circuit_model_names_.emplace_back(); @@ -314,6 +324,8 @@ CircuitModelId CircuitLibrary::add_circuit_model() { port_sizes_.emplace_back(); port_prefix_.emplace_back(); port_lib_names_.emplace_back(); + port_inv_prefix_.emplace_back(); + port_default_values_.emplace_back(); port_is_mode_select_.emplace_back(); port_is_global_.emplace_back(); port_is_reset_.emplace_back(); @@ -348,7 +360,6 @@ CircuitModelId CircuitLibrary::add_circuit_model() { /* Buffer/Inverter-related parameters */ buffer_types_.push_back(NUM_CIRCUIT_MODEL_BUF_TYPES); - buffer_location_maps_.emplace_back(); buffer_sizes_.push_back(-1); buffer_num_levels_.push_back(-1); buffer_f_per_stage_.push_back(-1); @@ -367,6 +378,9 @@ CircuitModelId CircuitLibrary::add_circuit_model() { /* LUT-related parameters */ lut_is_fracturable_.push_back(false); + /* Gate-related parameters */ + gate_types_.push_back(NUM_SPICE_MODEL_GATE_TYPES); + /* RRAM-related design technology information */ rram_res_.emplace_back(); wprog_set_.emplace_back(); @@ -519,6 +533,15 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitMode return; } +void CircuitLibrary::set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, + const std::string& location_map) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + buffer_location_maps_[circuit_model_id][LUT_INTER_BUFFER] = location_map; + return; +} + + /* Set pass-gate logic information of a circuit model */ void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) { /* validate the circuit_model_id */ @@ -542,6 +565,7 @@ CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circu port_prefix_[circuit_model_id].emplace_back(); port_lib_names_[circuit_model_id].emplace_back(); port_inv_prefix_[circuit_model_id].emplace_back(); + port_default_values_[circuit_model_id].push_back(-1); port_is_mode_select_[circuit_model_id].push_back(false); port_is_global_[circuit_model_id].push_back(false); port_is_reset_[circuit_model_id].push_back(false); @@ -561,9 +585,9 @@ CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circu } /* Set the type for a port of a circuit model */ -void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id, - const CircuitPortId& circuit_port_id, - const enum e_spice_model_port_type& port_type) { +void CircuitLibrary::set_port_type(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_spice_model_port_type& port_type) { /* validate the circuit_port_id */ VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_types_[circuit_model_id][circuit_port_id] = port_type; @@ -571,9 +595,9 @@ void CircuitLibrary::set_port_types(const CircuitModelId& circuit_model_id, } /* Set the size for a port of a circuit model */ -void CircuitLibrary::set_port_sizes(const CircuitModelId& circuit_model_id, - const CircuitPortId& circuit_port_id, - const size_t& port_size) { +void CircuitLibrary::set_port_size(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& port_size) { /* validate the circuit_port_id */ VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_sizes_[circuit_model_id][circuit_port_id] = port_size; @@ -610,6 +634,16 @@ void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& circuit_model_id, return; } +/* Set the default value for a port of a circuit model */ +void CircuitLibrary::set_port_default_value(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& default_value) { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + port_default_values_[circuit_model_id][circuit_port_id] = default_value; + return; +} + /* Set the is_mode_select for a port of a circuit model */ void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, @@ -822,18 +856,8 @@ void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id, return; } -void CircuitLibrary::set_buffer_location_map(const CircuitModelId& circuit_model_id, - const std::string& location_map) { - /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_location_maps_[circuit_model_id] = location_map; - return; -} - void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id, - const size_t& buffer_size) { + const float& buffer_size) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ @@ -874,7 +898,7 @@ void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_mode } void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, - const size_t& nmos_size) { + const float& nmos_size) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ @@ -884,7 +908,7 @@ void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit } void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, - const size_t& pmos_size) { + const float& pmos_size) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ @@ -955,6 +979,18 @@ void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_ return; } +/* Gate-related parameters */ +void CircuitLibrary::set_gate_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_gate_type& gate_type) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be GATE */ + VTR_ASSERT_SAFE(SPICE_MODEL_GATE == circuit_model_type(circuit_model_id)); + gate_types_[circuit_model_id] = gate_type; + return; +} + + /* RRAM-related design technology information */ void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id, const float& rlrs) { @@ -1079,6 +1115,7 @@ void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_mode buffer_existence_[circuit_model_id].resize(size_t(buffer_type) + 1); buffer_circuit_model_names_[circuit_model_id].resize(size_t(buffer_type) + 1); buffer_circuit_model_ids_[circuit_model_id].resize(size_t(buffer_type) + 1); + buffer_location_maps_[circuit_model_id].resize(size_t(buffer_type) + 1); } /* Now we are in the range, assign values */ buffer_existence_[circuit_model_id][size_t(buffer_type)] = existence; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index b129ab089..04eb75fd5 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -55,7 +55,7 @@ #include "vtr_vector.h" #include "vtr_range.h" -#include "spice_types.h" +#include "circuit_types.h" /************************************************************************ * Create strong id for Circuit Models/Ports to avoid illegal type casting @@ -238,6 +238,7 @@ class CircuitLibrary { std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + size_t port_default_value(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -273,16 +274,18 @@ class CircuitLibrary { const bool& existence, const std::string& circuit_model_name); void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name); + void set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, + const std::string& location_map); /* Pass-gate-related parameters */ void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name); /* Port information */ CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id); - void set_port_types(const CircuitModelId& circuit_model_id, - const CircuitPortId& circuit_port_id, - const enum e_spice_model_port_type& port_type); - void set_port_sizes(const CircuitModelId& circuit_model_id, - const CircuitPortId& circuit_port_id, - const size_t& port_size); + void set_port_type(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const enum e_spice_model_port_type& port_type); + void set_port_size(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& port_size); void set_port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix); @@ -292,6 +295,9 @@ class CircuitLibrary { void set_port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const std::string& inv_prefix); + void set_port_default_value(const CircuitModelId& circuit_model_id, + const CircuitPortId& circuit_port_id, + const size_t& default_val); void set_port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const bool& is_mode_select); @@ -349,10 +355,8 @@ class CircuitLibrary { /* Buffer/Inverter-related parameters */ void set_buffer_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_buffer_type& buffer_type); - void set_buffer_location_map(const CircuitModelId& circuit_model_id, - const std::string& location_map); void set_buffer_size(const CircuitModelId& circuit_model_id, - const size_t& buffer_size); + const float& buffer_size); void set_buffer_num_levels(const CircuitModelId& circuit_model_id, const size_t& num_levels); void set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, @@ -361,9 +365,9 @@ class CircuitLibrary { void set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type); void set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, - const size_t& nmos_size); + const float& nmos_size); void set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, - const size_t& pmos_size); + const float& pmos_size); /* Multiplexer-related parameters */ void set_mux_structure(const CircuitModelId& circuit_model_id, const enum e_spice_model_structure& mux_structure); @@ -378,6 +382,9 @@ class CircuitLibrary { /* LUT-related parameters */ void set_lut_is_fracturable(const CircuitModelId& circuit_model_id, const bool& is_fracturable); + /* Gate-related parameters */ + void set_gate_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_gate_type& gate_type); /* RRAM-related design technology information */ void set_rram_rlrs(const CircuitModelId& circuit_model_id, const float& rlrs); @@ -444,6 +451,7 @@ class CircuitLibrary { vtr::vector> buffer_existence_; vtr::vector> buffer_circuit_model_names_; vtr::vector> buffer_circuit_model_ids_; + vtr::vector> buffer_location_maps_; /* Pass-gate-related parameters */ vtr::vector pass_gate_logic_circuit_model_names_; @@ -456,6 +464,7 @@ class CircuitLibrary { vtr::vector> port_prefix_; vtr::vector> port_lib_names_; vtr::vector> port_inv_prefix_; + vtr::vector> port_default_values_; vtr::vector> port_is_mode_select_; vtr::vector> port_is_global_; vtr::vector> port_is_reset_; @@ -490,14 +499,13 @@ class CircuitLibrary { /* Buffer/Inverter-related parameters */ vtr::vector buffer_types_; - vtr::vector buffer_location_maps_; - vtr::vector buffer_sizes_; + vtr::vector buffer_sizes_; vtr::vector buffer_num_levels_; vtr::vector buffer_f_per_stage_; /* Pass-gate-related parameters */ vtr::vector pass_gate_logic_types_; - vtr::vector> pass_gate_logic_sizes_; /* x=> nmos_size; y => pmos_size */ + vtr::vector> pass_gate_logic_sizes_; /* x=> nmos_size; y => pmos_size */ /* Multiplexer-related parameters */ vtr::vector mux_structure_; @@ -509,6 +517,9 @@ class CircuitLibrary { /* LUT-related parameters */ vtr::vector lut_is_fracturable_; + /* Gate-related parameters */ + vtr::vector gate_types_; + /* RRAM-related design technology information */ vtr::vector> rram_res_; /* x => R_LRS, y => R_HRS */ vtr::vector> wprog_set_; /* x => wprog_set_nmos, y=> wprog_set_pmos */ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h new file mode 100644 index 000000000..c13e91934 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h @@ -0,0 +1,144 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: circuit_types.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/08 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef CIRCUIT_TYPES_H +#define CIRCUIT_TYPES_H + +/************************************************************************ + * This file includes basic enumeration types for circuit models + ***********************************************************************/ +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ + +enum spice_model_delay_type { + SPICE_MODEL_DELAY_RISE, + SPICE_MODEL_DELAY_FALL, + NUM_CIRCUIT_MODEL_DELAY_TYPES +}; + +/*Struct for a SPICE model of a module*/ +enum e_spice_model_type { + SPICE_MODEL_CHAN_WIRE, + SPICE_MODEL_WIRE, + SPICE_MODEL_MUX, + SPICE_MODEL_LUT, + SPICE_MODEL_FF, + SPICE_MODEL_SRAM, + SPICE_MODEL_HARDLOGIC, + SPICE_MODEL_SCFF, + SPICE_MODEL_IOPAD, + SPICE_MODEL_INVBUF, + SPICE_MODEL_PASSGATE, + SPICE_MODEL_GATE, + NUM_CIRCUIT_MODEL_TYPES +}; + +enum e_spice_model_design_tech { + SPICE_MODEL_DESIGN_CMOS, + SPICE_MODEL_DESIGN_RRAM, + NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES +}; + +enum e_spice_model_structure { + SPICE_MODEL_STRUCTURE_TREE, + SPICE_MODEL_STRUCTURE_ONELEVEL, + SPICE_MODEL_STRUCTURE_MULTILEVEL, + SPICE_MODEL_STRUCTURE_CROSSBAR, + NUM_CIRCUIT_MODEL_STRUCTURE_TYPES +}; + +enum e_spice_model_buffer_type { + SPICE_MODEL_BUF_INV, + SPICE_MODEL_BUF_BUF, + NUM_CIRCUIT_MODEL_BUF_TYPES +}; + +enum e_spice_model_pass_gate_logic_type { + SPICE_MODEL_PASS_GATE_TRANSMISSION, + SPICE_MODEL_PASS_GATE_TRANSISTOR, + NUM_CIRCUIT_MODEL_PASS_GATE_TYPES +}; + +enum e_spice_model_gate_type { + SPICE_MODEL_GATE_AND, + SPICE_MODEL_GATE_OR, + SPICE_MODEL_GATE_MUX2, + NUM_SPICE_MODEL_GATE_TYPES +}; + +enum e_wire_model_type { + WIRE_MODEL_PIE, + WIRE_MODEL_T, + NUM_WIRE_MODEL_TYPES, +}; + +enum e_spice_model_port_type { + SPICE_MODEL_PORT_INPUT, + SPICE_MODEL_PORT_OUTPUT, + SPICE_MODEL_PORT_INOUT, + SPICE_MODEL_PORT_CLOCK, + SPICE_MODEL_PORT_SRAM, + SPICE_MODEL_PORT_BL, + SPICE_MODEL_PORT_BLB, + SPICE_MODEL_PORT_WL, + SPICE_MODEL_PORT_WLB, + NUM_CIRCUIT_MODEL_PORT_TYPES +}; + +/* For SRAM */ +enum e_sram_orgz { + SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ + SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ + SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ + SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */ + NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES +}; + + +#endif + +/************************************************************************ + * End of file : circuit_types.h + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index d16c2de5d..1c333eb70 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -3,6 +3,7 @@ #include "util.h" #include "linkedlist.h" +#include "circuit_library.h" /* Xifan TANG: Spice support*/ enum e_spice_tech_lib_type { @@ -10,61 +11,6 @@ enum e_spice_tech_lib_type { SPICE_LIB_ACADEMIA }; -enum spice_model_delay_type { - SPICE_MODEL_DELAY_RISE, - SPICE_MODEL_DELAY_FALL, - NUM_CIRCUIT_MODEL_DELAY_TYPES -}; - -/*Struct for a SPICE model of a module*/ -enum e_spice_model_type { - SPICE_MODEL_CHAN_WIRE, - SPICE_MODEL_WIRE, - SPICE_MODEL_MUX, - SPICE_MODEL_LUT, - SPICE_MODEL_FF, - SPICE_MODEL_SRAM, - SPICE_MODEL_HARDLOGIC, - SPICE_MODEL_SCFF, - SPICE_MODEL_IOPAD, - SPICE_MODEL_INVBUF, - SPICE_MODEL_PASSGATE, - SPICE_MODEL_GATE, - NUM_CIRCUIT_MODEL_TYPES -}; - -enum e_spice_model_design_tech { - SPICE_MODEL_DESIGN_CMOS, - SPICE_MODEL_DESIGN_RRAM, - NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES -}; - -enum e_spice_model_structure { - SPICE_MODEL_STRUCTURE_TREE, - SPICE_MODEL_STRUCTURE_ONELEVEL, - SPICE_MODEL_STRUCTURE_MULTILEVEL, - SPICE_MODEL_STRUCTURE_CROSSBAR, - NUM_CIRCUIT_MODEL_STRUCTURE_TYPES -}; - -enum e_spice_model_buffer_type { - SPICE_MODEL_BUF_INV, - SPICE_MODEL_BUF_BUF, - NUM_CIRCUIT_MODEL_BUF_TYPES -}; - -enum e_spice_model_pass_gate_logic_type { - SPICE_MODEL_PASS_GATE_TRANSMISSION, - SPICE_MODEL_PASS_GATE_TRANSISTOR, - NUM_CIRCUIT_MODEL_PASS_GATE_TYPES -}; - -enum e_spice_model_gate_type { - SPICE_MODEL_GATE_AND, - SPICE_MODEL_GATE_OR, - SPICE_MODEL_GATE_MUX2 -}; - /* Transistor-level basic informations*/ enum e_spice_trans_type { SPICE_TRANS_NMOS, @@ -73,25 +19,6 @@ enum e_spice_trans_type { SPICE_TRANS_IO_PMOS }; -enum e_wire_model_type { - WIRE_MODEL_PIE, - WIRE_MODEL_T, - NUM_WIRE_MODEL_TYPES, -}; - -enum e_spice_model_port_type { - SPICE_MODEL_PORT_INPUT, - SPICE_MODEL_PORT_OUTPUT, - SPICE_MODEL_PORT_INOUT, - SPICE_MODEL_PORT_CLOCK, - SPICE_MODEL_PORT_SRAM, - SPICE_MODEL_PORT_BL, - SPICE_MODEL_PORT_BLB, - SPICE_MODEL_PORT_WL, - SPICE_MODEL_PORT_WLB, - NUM_CIRCUIT_MODEL_PORT_TYPES -}; - /* For process corner */ enum e_process_corner { BEST_CORNER, @@ -99,15 +26,6 @@ enum e_process_corner { WORST_CORNER }; -/* For SRAM */ -enum e_sram_orgz { - SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ - SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ - SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ - SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */ - NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES -}; - enum e_spice_accuracy_type { SPICE_FRAC, SPICE_ABS }; @@ -450,6 +368,8 @@ struct s_spice { t_spice_tech_lib tech_lib; int num_spice_model; t_spice_model* spice_models; + /* Circuit library, object to replace the legacy spice_models */ + CircuitLibrary circuit_lib; }; /* Information needed to build a Multiplexer architecture*/ diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 89c3995a8..5c5d38d3c 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -10,6 +10,8 @@ #include "read_xml_spice_util.h" #include "read_xml_spice.h" +#include "circuit_library.h" + /*********** Subroutines Declaration (only called in this source file) **********/ static void ProcessSpiceMeasParams(ezxml_t Parent, t_spice_meas_params* meas_params); @@ -768,6 +770,8 @@ static void ProcessSpiceModelPort(ezxml_t Node, ||(SPICE_MODEL_PORT_WLB == port->type)) { port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_circuit_model_name", FALSE)); ezxml_set_attr(Node, "inv_circuit_model_name", NULL); + } else { + port->inv_spice_model_name = NULL; } /* Add a feature to enable/disable the configuration encoders for multiplexers */ @@ -914,6 +918,13 @@ static void ProcessSpiceModel(ezxml_t Parent, /* Check the design technology settings*/ Node = ezxml_child(Parent, "design_technology"); + /* Initialize */ + spice_model->design_tech_info.buffer_info = NULL; + spice_model->design_tech_info.pass_gate_info = NULL; + spice_model->design_tech_info.rram_info = NULL; + spice_model->design_tech_info.mux_info = NULL; + spice_model->design_tech_info.lut_info = NULL; + spice_model->design_tech_info.gate_info = NULL; if (Node) { /* Specify if this spice_model is power gated or not*/ spice_model->design_tech_info.power_gated = GetBooleanProperty(Node,"power_gated", FALSE, FALSE); @@ -941,7 +952,7 @@ static void ProcessSpiceModel(ezxml_t Parent, } else if (0 == strcmp(FindProperty(Node,"type",TRUE),"rram")) { spice_model->design_tech = SPICE_MODEL_DESIGN_RRAM; /* Malloc RRAM info */ - spice_model->design_tech_info.rram_info = (t_spice_model_rram*)my_malloc(sizeof(t_spice_model_rram)); + spice_model->design_tech_info.rram_info = (t_spice_model_rram*)my_calloc(1, sizeof(t_spice_model_rram)); /* Fill information */ ProcessSpiceModelRRAM(Node, spice_model->design_tech_info.rram_info); } else { @@ -955,7 +966,7 @@ static void ProcessSpiceModel(ezxml_t Parent, spice_model->design_tech_info.mux_info = NULL; if (SPICE_MODEL_MUX == spice_model->type) { /* Malloc */ - spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_malloc(sizeof(t_spice_model_mux)); + spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_calloc(1, sizeof(t_spice_model_mux)); /* Fill information */ ProcessSpiceModelMUX(Node, spice_model, spice_model->design_tech_info.mux_info); } @@ -964,11 +975,11 @@ static void ProcessSpiceModel(ezxml_t Parent, spice_model->design_tech_info.lut_info = NULL; if (SPICE_MODEL_LUT == spice_model->type) { /* Malloc */ - spice_model->design_tech_info.lut_info = (t_spice_model_lut*)my_malloc(sizeof(t_spice_model_lut)); + spice_model->design_tech_info.lut_info = (t_spice_model_lut*)my_calloc(1, sizeof(t_spice_model_lut)); /* Fill information */ ProcessSpiceModelLUT(Node, spice_model->design_tech_info.lut_info); /* Malloc */ - spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_malloc(sizeof(t_spice_model_mux)); + spice_model->design_tech_info.mux_info = (t_spice_model_mux*)my_calloc(1, sizeof(t_spice_model_mux)); /* Fill information */ /* Default: tree, no const_inputs */ spice_model->design_tech_info.mux_info->structure = SPICE_MODEL_STRUCTURE_TREE; @@ -1041,7 +1052,7 @@ static void ProcessSpiceModel(ezxml_t Parent, spice_model->input_buffer = NULL; if (Node) { /*Alloc*/ - spice_model->input_buffer = (t_spice_model_buffer*)my_malloc(sizeof(t_spice_model_buffer)); + spice_model->input_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); ProcessSpiceModelBuffer(Node,spice_model->input_buffer); FreeNode(Node); } else if (SPICE_MODEL_INVBUF != spice_model->type) { @@ -1053,7 +1064,7 @@ static void ProcessSpiceModel(ezxml_t Parent, Node = ezxml_child(Parent, "output_buffer"); spice_model->output_buffer = NULL; if (Node) { - spice_model->output_buffer = (t_spice_model_buffer*)my_malloc(sizeof(t_spice_model_buffer)); + spice_model->output_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); ProcessSpiceModelBuffer(Node,spice_model->output_buffer); FreeNode(Node); } else if (SPICE_MODEL_INVBUF != spice_model->type) { @@ -1066,7 +1077,7 @@ static void ProcessSpiceModel(ezxml_t Parent, Node = ezxml_child(Parent, "pass_gate_logic"); spice_model->pass_gate_logic = NULL; if (Node) { - spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_malloc(sizeof(t_spice_model_pass_gate_logic)); + spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_calloc(1, sizeof(t_spice_model_pass_gate_logic)); /* Find spice_model_name */ spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", TRUE)); ezxml_set_attr(Node, "circuit_model_name", NULL); @@ -1082,7 +1093,7 @@ static void ProcessSpiceModel(ezxml_t Parent, /* Find All the ports*/ spice_model->num_port = CountChildren(Parent, "port", 1); /*Alloc*/ - spice_model->ports = (t_spice_model_port*)my_malloc(spice_model->num_port*sizeof(t_spice_model_port)); + spice_model->ports = (t_spice_model_port*)my_calloc(spice_model->num_port, sizeof(t_spice_model_port)); /* Assign each found spice model*/ for (iport = 0; iport < spice_model->num_port; iport++) { Cur = FindFirstElement(Parent, "port", TRUE); @@ -1091,8 +1102,9 @@ static void ProcessSpiceModel(ezxml_t Parent, } /* Read in wire parameters */ + spice_model->wire_param = NULL; if ((SPICE_MODEL_CHAN_WIRE == spice_model->type)||(SPICE_MODEL_WIRE == spice_model->type)) { - spice_model->wire_param = (t_spice_model_wire_param*)my_malloc(sizeof(t_spice_model_wire_param)); + spice_model->wire_param = (t_spice_model_wire_param*)my_calloc(1, sizeof(t_spice_model_wire_param)); Node = ezxml_child(Parent, "wire_param"); if (Node) { ProcessSpiceModelWireParam(Node,spice_model->wire_param); @@ -1107,7 +1119,7 @@ static void ProcessSpiceModel(ezxml_t Parent, /* Find delay info */ spice_model->num_delay_info = CountChildren(Parent, "delay_matrix", 0); /*Alloc*/ - spice_model->delay_info = (t_spice_model_delay_info*) my_malloc(spice_model->num_delay_info * sizeof(t_spice_model_delay_info)); + spice_model->delay_info = (t_spice_model_delay_info*) my_calloc(spice_model->num_delay_info, sizeof(t_spice_model_delay_info)); /* Assign each found spice model*/ for (i = 0; i < spice_model->num_delay_info; i++) { Cur = FindFirstElement(Parent, "delay_matrix", TRUE); @@ -1508,6 +1520,232 @@ static void ProcessSpiceTechLibTransistors(ezxml_t Parent, return; } +/* Build a circuit library based on the spice_models + * This function does a quick conversion, so that we can proceed to update the downstream codes + * TODO: The circuit library should be incrementally built during XML parsing + * when the downstream is updated, the legacy spice_models will be removed + */ +static +CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_models) { + CircuitLibrary circuit_lib; + + /* Go spice_model by spice_model */ + for (int imodel = 0; imodel < num_spice_model; ++imodel) { + /* Add a spice model to the circuit_lib */ + CircuitModelId model_id = circuit_lib.add_circuit_model(); + /* Fill fundamental attributes */ + /* Basic information*/ + circuit_lib.set_circuit_model_type(model_id, spice_models[imodel].type); + + std::string name(spice_models[imodel].name); + circuit_lib.set_circuit_model_name(model_id, name); + + std::string prefix(spice_models[imodel].prefix); + circuit_lib.set_circuit_model_prefix(model_id, prefix); + + if (NULL != spice_models[imodel].verilog_netlist) { + std::string verilog_netlist(spice_models[imodel].verilog_netlist); + circuit_lib.set_circuit_model_verilog_netlist(model_id, verilog_netlist); + } + + if (NULL != spice_models[imodel].model_netlist) { + std::string spice_netlist(spice_models[imodel].model_netlist); + circuit_lib.set_circuit_model_spice_netlist(model_id, spice_netlist); + } + + circuit_lib.set_circuit_model_is_default(model_id, 0 != spice_models[imodel].is_default); + + /* Verilog generatioin options */ + circuit_lib.set_circuit_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog); + + circuit_lib.set_circuit_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map); + + /* Design technology information */ + circuit_lib.set_circuit_model_design_tech_type(model_id, spice_models[imodel].design_tech); + + circuit_lib.set_circuit_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated); + + /* Buffer linking information */ + if (NULL != spice_models[imodel].input_buffer) { + std::string model_name; + if (NULL != spice_models[imodel].input_buffer->spice_model_name) { + model_name = spice_models[imodel].input_buffer->spice_model_name; + } + circuit_lib.set_circuit_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name); + } + if (NULL != spice_models[imodel].output_buffer) { + std::string model_name; + if (NULL != spice_models[imodel].output_buffer->spice_model_name) { + model_name = spice_models[imodel].output_buffer->spice_model_name; + } + circuit_lib.set_circuit_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name); + } + if (NULL != spice_models[imodel].lut_input_buffer) { + std::string model_name; + if (NULL != spice_models[imodel].lut_input_buffer->spice_model_name) { + model_name = spice_models[imodel].lut_input_buffer->spice_model_name; + } + circuit_lib.set_circuit_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name); + } + if (NULL != spice_models[imodel].lut_input_inverter) { + std::string model_name; + if (NULL != spice_models[imodel].lut_input_inverter->spice_model_name) { + model_name = spice_models[imodel].lut_input_inverter->spice_model_name; + } + circuit_lib.set_circuit_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); + } + if (NULL != spice_models[imodel].lut_intermediate_buffer) { + std::string model_name; + if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) { + model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name; + } + circuit_lib.set_circuit_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name); + + std::string model_location_map; + if (NULL != spice_models[imodel].lut_intermediate_buffer->location_map) { + model_location_map = spice_models[imodel].lut_intermediate_buffer->location_map; + } + circuit_lib.set_circuit_model_lut_intermediate_buffer_location_map(model_id, model_location_map); + } + + /* Pass-gate-logic linking information */ + if (NULL != spice_models[imodel].pass_gate_logic) { + std::string model_name(spice_models[imodel].pass_gate_logic->spice_model_name); + circuit_lib.set_circuit_model_pass_gate_logic(model_id, model_name); + } + + /* Buffer information */ + if (NULL != spice_models[imodel].design_tech_info.buffer_info) { + circuit_lib.set_buffer_type(model_id, spice_models[imodel].design_tech_info.buffer_info->type); + circuit_lib.set_buffer_size(model_id, spice_models[imodel].design_tech_info.buffer_info->size); + if (TRUE == spice_models[imodel].design_tech_info.buffer_info->tapered_buf) { + circuit_lib.set_buffer_num_levels(model_id, spice_models[imodel].design_tech_info.buffer_info->tap_buf_level); + circuit_lib.set_buffer_f_per_stage(model_id, spice_models[imodel].design_tech_info.buffer_info->f_per_stage); + } + } + + /* Pass-gate information */ + if (NULL != spice_models[imodel].design_tech_info.pass_gate_info) { + circuit_lib.set_pass_gate_logic_type(model_id, spice_models[imodel].design_tech_info.pass_gate_info->type); + circuit_lib.set_pass_gate_logic_nmos_size(model_id, spice_models[imodel].design_tech_info.pass_gate_info->nmos_size); + circuit_lib.set_pass_gate_logic_pmos_size(model_id, spice_models[imodel].design_tech_info.pass_gate_info->pmos_size); + } + + /* Multiplexer information */ + if (NULL != spice_models[imodel].design_tech_info.mux_info) { + circuit_lib.set_mux_structure(model_id, spice_models[imodel].design_tech_info.mux_info->structure); + circuit_lib.set_mux_num_levels(model_id, spice_models[imodel].design_tech_info.mux_info->mux_num_level); + if (TRUE == spice_models[imodel].design_tech_info.mux_info->add_const_input) { + circuit_lib.set_mux_const_input_value(model_id, spice_models[imodel].design_tech_info.mux_info->const_input_val); + } + circuit_lib.set_mux_use_local_encoder(model_id, TRUE == spice_models[imodel].design_tech_info.mux_info->local_encoder); + circuit_lib.set_mux_use_advanced_rram_design(model_id, TRUE == spice_models[imodel].design_tech_info.mux_info->advanced_rram_design); + } + + /* LUT information */ + if (NULL != spice_models[imodel].design_tech_info.lut_info) { + circuit_lib.set_lut_is_fracturable(model_id, TRUE == spice_models[imodel].design_tech_info.lut_info->frac_lut); + } + + /* Gate information */ + if (NULL != spice_models[imodel].design_tech_info.gate_info) { + circuit_lib.set_gate_type(model_id, spice_models[imodel].design_tech_info.gate_info->type); + } + + /* RRAM information */ + if (NULL != spice_models[imodel].design_tech_info.rram_info) { + circuit_lib.set_rram_rlrs(model_id, spice_models[imodel].design_tech_info.rram_info->ron); + circuit_lib.set_rram_rhrs(model_id, spice_models[imodel].design_tech_info.rram_info->roff); + circuit_lib.set_rram_wprog_set_nmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_set_nmos); + circuit_lib.set_rram_wprog_set_pmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_set_pmos); + circuit_lib.set_rram_wprog_reset_nmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_reset_nmos); + circuit_lib.set_rram_wprog_reset_pmos(model_id, spice_models[imodel].design_tech_info.rram_info->wprog_reset_pmos); + } + + /* Delay information */ + for (int idelay = 0; idelay < spice_models[imodel].num_delay_info; ++idelay) { + circuit_lib.add_delay_info(model_id, spice_models[imodel].delay_info[idelay].type); + + std::string in_port_names(spice_models[imodel].delay_info[idelay].in_port_name); + circuit_lib.set_delay_in_port_names(model_id, spice_models[imodel].delay_info[idelay].type, in_port_names); + + std::string out_port_names(spice_models[imodel].delay_info[idelay].out_port_name); + circuit_lib.set_delay_out_port_names(model_id, spice_models[imodel].delay_info[idelay].type, out_port_names); + + std::string delay_values(spice_models[imodel].delay_info[idelay].value); + circuit_lib.set_delay_values(model_id, spice_models[imodel].delay_info[idelay].type, delay_values); + } + + /* Wire parameters */ + if (NULL != spice_models[imodel].wire_param) { + circuit_lib.set_wire_type(model_id, spice_models[imodel].wire_param->type); + circuit_lib.set_wire_r(model_id, spice_models[imodel].wire_param->res_val); + circuit_lib.set_wire_c(model_id, spice_models[imodel].wire_param->cap_val); + circuit_lib.set_wire_num_levels(model_id, spice_models[imodel].wire_param->level); + } + + /* Ports */ + for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) { + CircuitPortId port_id = circuit_lib.add_circuit_model_port(model_id); + /* Fill fundamental attributes */ + circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type); + + circuit_lib.set_port_size(model_id, port_id, spice_models[imodel].ports[iport].size); + + std::string port_prefix(spice_models[imodel].ports[iport].prefix); + circuit_lib.set_port_prefix(model_id, port_id, port_prefix); + + std::string port_lib_name(spice_models[imodel].ports[iport].lib_name); + circuit_lib.set_port_lib_name(model_id, port_id, port_lib_name); + + if (NULL != spice_models[imodel].ports[iport].inv_prefix) { + std::string port_inv_prefix(spice_models[imodel].ports[iport].inv_prefix); + circuit_lib.set_port_inv_prefix(model_id, port_id, port_inv_prefix); + } + + circuit_lib.set_port_default_value(model_id, port_id, spice_models[imodel].ports[iport].default_val); + + circuit_lib.set_port_is_mode_select(model_id, port_id, TRUE == spice_models[imodel].ports[iport].mode_select); + circuit_lib.set_port_is_global(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_global); + circuit_lib.set_port_is_reset(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_reset); + circuit_lib.set_port_is_set(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_set); + circuit_lib.set_port_is_config_enable(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_config_enable); + circuit_lib.set_port_is_prog(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_prog); + + if (NULL != spice_models[imodel].ports[iport].spice_model_name) { + std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name); + circuit_lib.set_port_circuit_model_name(model_id, port_id, port_model_name); + } + + if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) { + std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name); + circuit_lib.set_port_inv_circuit_model_name(model_id, port_id, port_inv_model_name); + } + + if (NULL != spice_models[imodel].ports[iport].tri_state_map) { + std::string port_tri_state_map(spice_models[imodel].ports[iport].tri_state_map); + circuit_lib.set_port_tri_state_map(model_id, port_id, port_tri_state_map); + } + + if (SPICE_MODEL_LUT == spice_models[imodel].type) { + circuit_lib.set_port_lut_frac_level(model_id, port_id, spice_models[imodel].ports[iport].lut_frac_level); + + std::vector port_lut_output_mask; + for (int ipin = 0; ipin < spice_models[imodel].ports[iport].size; ++ipin) { + port_lut_output_mask.push_back(spice_models[imodel].ports[iport].lut_output_mask[ipin]); + } + circuit_lib.set_port_lut_output_mask(model_id, port_id, port_lut_output_mask); + } + + if (SPICE_MODEL_PORT_SRAM == spice_models[imodel].ports[iport].type) { + circuit_lib.set_port_sram_orgz(model_id, port_id, spice_models[imodel].ports[iport].organization); + } + } + } + + return circuit_lib; +} + /* Process the SPICE Settings*/ void ProcessSpiceSettings(ezxml_t Parent, t_spice* spice) { @@ -1541,6 +1779,8 @@ void ProcessSpiceSettings(ezxml_t Parent, assert(imodel == spice->num_spice_model); FreeNode(Node); } + /* Build the CircuitLibrary here from spice_models */ + spice->circuit_lib = build_circuit_library(spice->num_spice_model, spice->spice_models); /* Check codes*/ check_tech_lib(spice->tech_lib, spice->num_spice_model, spice->spice_models); From 0cc439f76c09c5e729f936d767319354a6b5f2b1 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 8 Aug 2019 18:08:39 -0600 Subject: [PATCH 033/482] Working lattice benchmark unclean commit --- .gitignore | 4 +- Dockerfile | 26 +++--- fpga_flow/.gitignore | 1 + .../k6_N10_rram_memory_bank_SC_winbond90.xml | 69 +++++---------- .../benchmarks/List/lattice_benchmark.txt | 6 +- fpga_flow/configs/lattice_benchmark.conf | 7 +- fpga_flow/configs/lattice_benchmark.txt | 6 ++ fpga_flow/run_benchmark.sh | 88 +++++++++++++++---- fpga_flow/scripts/fpga_flow.pl | 59 +++++++------ fpga_flow/vpr_fpga_spice_conf/sample.conf | 55 ++++++------ run_local.bat | 2 +- 11 files changed, 182 insertions(+), 141 deletions(-) create mode 100644 fpga_flow/.gitignore create mode 100644 fpga_flow/configs/lattice_benchmark.txt diff --git a/.gitignore b/.gitignore index 5651b1ed0..7e355cf96 100644 --- a/.gitignore +++ b/.gitignore @@ -35,4 +35,6 @@ vpr7_x2p/pcre/pcredemo # Some local temporary files .vscode -*_local.bat \ No newline at end of file +*_local.bat +fpga_flow/csv_rpts +tmp/ \ No newline at end of file diff --git a/Dockerfile b/Dockerfile index c573dbbee..7f25b6c01 100755 --- a/Dockerfile +++ b/Dockerfile @@ -1,10 +1,16 @@ -FROM ubuntu:16.04 - -RUN apt-get update -qq -y -RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev - -RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default - -RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA -RUN cd OpenFPGA && make - +FROM ubuntu:16.04 + +RUN apt-get update -qq -y +RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev + +RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default + +RUN mkdir -p /release /dev + +RUN cd release && git clone --single-branch --branch documentation https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA + +RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -CMAKE_BUILD_TYPE=debug && make + +RUN rm -rf /var/lib/apt/lists/* + +WORKDIR /release/OpenFPGA \ No newline at end of file diff --git a/fpga_flow/.gitignore b/fpga_flow/.gitignore new file mode 100644 index 000000000..1a06816d8 --- /dev/null +++ b/fpga_flow/.gitignore @@ -0,0 +1 @@ +results diff --git a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml index bfd21a6d8..f0c7e5752 100644 --- a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +++ b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml @@ -15,7 +15,7 @@ - + @@ -33,7 +33,7 @@ - + @@ -142,7 +142,7 @@ - + @@ -155,7 +155,7 @@ - + @@ -168,7 +168,7 @@ - + @@ -191,7 +191,7 @@ - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + @@ -225,7 +225,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -252,28 +252,8 @@ - - - - @@ -334,14 +314,6 @@ 1 - - @@ -457,12 +429,12 @@ - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 @@ -483,9 +455,8 @@ - - - + + @@ -508,8 +479,8 @@ 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback to get the part that should be marked on the crossbar. --> - - + + diff --git a/fpga_flow/benchmarks/List/lattice_benchmark.txt b/fpga_flow/benchmarks/List/lattice_benchmark.txt index 912818af7..1a5dc6995 100644 --- a/fpga_flow/benchmarks/List/lattice_benchmark.txt +++ b/fpga_flow/benchmarks/List/lattice_benchmark.txt @@ -1,2 +1,6 @@ # Circuit Names, fixed routing channel width, -PID/*.v, 120 \ No newline at end of file +# PID/*.v, 120 +up_counter/*.v, 30 +# MultiBitAdder/*.v, 30 +# i2c_master_top/*.v, 40 +# asynch_fifo/*.v, 30 \ No newline at end of file diff --git a/fpga_flow/configs/lattice_benchmark.conf b/fpga_flow/configs/lattice_benchmark.conf index 7d270f6e3..c74d47581 100644 --- a/fpga_flow/configs/lattice_benchmark.conf +++ b/fpga_flow/configs/lattice_benchmark.conf @@ -1,8 +1,9 @@ # Standard Configuration Example [dir_path] script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example +# yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc @@ -12,7 +13,7 @@ mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results +rpt_dir = /var/tmp/Openfpga/results ace_path = OPENFPGAPATHKEYWORD/ace2/ace [flow_conf] diff --git a/fpga_flow/configs/lattice_benchmark.txt b/fpga_flow/configs/lattice_benchmark.txt new file mode 100644 index 000000000..1a5dc6995 --- /dev/null +++ b/fpga_flow/configs/lattice_benchmark.txt @@ -0,0 +1,6 @@ +# Circuit Names, fixed routing channel width, +# PID/*.v, 120 +up_counter/*.v, 30 +# MultiBitAdder/*.v, 30 +# i2c_master_top/*.v, 40 +# asynch_fifo/*.v, 30 \ No newline at end of file diff --git a/fpga_flow/run_benchmark.sh b/fpga_flow/run_benchmark.sh index c039011b5..41e5ab3f8 100644 --- a/fpga_flow/run_benchmark.sh +++ b/fpga_flow/run_benchmark.sh @@ -4,7 +4,24 @@ set -e # Make sure a clear start default_task='lattice_benchmark' pwd_path="$PWD" -task_name=${1:-$default_task} # run task defined in argument else run default task + +# ========================= Read command argument ========================= +usage() { echo "Usage: $0 [-b ] [-s] run spice only [-p] run vpr only " 1>&2; exit 1; } + +while getopts ":b:vpr:spice:" o; do + case "${o}" in + b) + bench=${OPTARG};; + v) + vpr=1;; + s) + spice=1;; + esac +done +# ========================================================================== + +task_name=${bench:-$default_task} # run task defined in argument else run default task +echo "Running task ${task_name}" config_file="$PWD/configs/${task_name}.conf" bench_txt="$PWD/benchmarks/List/${task_name}.txt" rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv" @@ -16,22 +33,45 @@ config_file_final=$(echo ${config_file/.conf/_final.conf}) # List of argument passed to FPGA flow vpr_config_flags=( - '-N 10' - '-K 6' - '-ace_d 0.5' - '-multi_thread 1' - '-vpr_fpga_x2p_rename_illegal_port' - '-vpr_fpga_verilog' - '-vpr_fpga_bitstream_generator' - '-vpr_fpga_verilog_print_autocheck_top_testbench' - '-vpr_fpga_verilog_include_timing' - '-vpr_fpga_verilog_include_signal_init' - '-vpr_fpga_verilog_formal_verification_top_netlist' - '-fix_route_chan_width' - '-vpr_fpga_verilog_include_icarus_simulator' - '-power' + "-conf ${config_file_final}" + "-benchmark ${bench_txt}" + "-rpt ${rpt_file}" + "-vpr_fpga_verilog_dir ${verilog_path}" + "-N 10" + "-K 6" + "-remove_designs" + "-ace_d 0.5" + "-multi_thread 1" + # "-route_chan_width 10" + "-vpr_fpga_x2p_rename_illegal_port" + "-vpr_fpga_verilog" + "-vpr_fpga_bitstream_generator" + "-vpr_fpga_verilog_print_autocheck_top_testbench" + "-vpr_fpga_verilog_include_timing" + "-vpr_fpga_verilog_include_signal_init" + "-vpr_fpga_verilog_formal_verification_top_netlist" + "-fix_route_chan_width" + # "-vpr_fpga_verilog_include_icarus_simulator" + "-power" + "-vpr_fpga_spice spice_taskfile" + "-vpr_fpga_spice_simulator_path /uusoc/facility/cad_tools/Synopsys/lnis_tools/hspice/P-2019.06/hspice/bin/" + # "-vpr_fpga_spice_print_top_tb" + "-vpr_fpga_spice_print_component_tb", + # "-vpr_fpga_spice_print_grid_tb" +) + +spice_config_flags=( + "-conf /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/vpr_fpga_spice_conf/sample.conf" + "-task /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/scripts/spice_taskfile_yosys_vpr.txt" + "-rpt ${rpt_file/.csv/_spice_result.csv}" + "-multi_thread 10" + # "-parse_grid_tb" + "-parse_pb_mux_tb" + "-parse_cb_mux_tb" + "-parse_sb_mux_tb" + "-parse_lut_tb" + # "-parse_hardlogic_tb" ) -# vpr_config_flags+=("$@") # Append provided arguments #=============== Argument Sanity Check ===================== #Check if script running in correct (OpenFPGA/fpga_flow) folder @@ -63,9 +103,19 @@ sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_f #==================Clean result, change directory and execute =============== cd ${pwd_path}/scripts -# perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -vpr_fpga_verilog_dir $verilog_path $(echo "${vpr_config_flags[@]}") +if [[ -n "$vpr" ]]; then + # Create echo and execute VPR command + command="perl fpga_flow.pl $(echo ${vpr_config_flags[@]})" + echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n" + eval ${command} +fi -perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power +if [[ -n "$spice" ]]; then + # Create echo and SPICE Execution + command="perl run_fpga_spice.pl $(echo ${spice_config_flags[@]})" + echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n" + eval ${command} +fi echo "Netlists successfully generated and simulated" -exit 0 +exit 0 \ No newline at end of file diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index d94d03482..db66be359 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1,4 +1,4 @@ -#!usr/bin/perl -w +#!/usr/bin/perl -w # use the strict mode use strict; # Use the Shell enviornment @@ -1182,6 +1182,7 @@ sub run_odin2($ $ $) { } sub run_pro_blif_3arg($ $ $) { + # Adopt blif format my ($abc_blif_out_bak, $abc_blif_out, $initial_blif) = @_; my ($pro_blif_path) = ($conf_ptr->{dir_path}->{script_base}->{val}); @@ -1301,7 +1302,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) { my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - + my ($power_opts); if ("on" eq $opt_ptr->{power}) { $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; @@ -1460,7 +1461,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) # foreach my $file (0..$#files){ # print "$files[$file]\t"; # } - 3 print "\n"; + # print "\n"; #} chdir $cwd; } @@ -1765,7 +1766,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { print "INFO: try route_chan_width($min_chan_width) success!\n"; last; #Jump out } elsif ($max_route_width_retry < $min_chan_width) { - # I set a threshold of 1000 as it is the limit of VPR + # I set a threshold of 1000 as it is the limit of VPR die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $min_chan_width!\n"; } else { print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; @@ -1791,7 +1792,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { print "INFO: try route_chan_width($fix_chan_width) success!\n"; last; #Jump out } elsif ($max_route_width_retry < $fix_chan_width) { - # I set a threshold of 1000 as it is the limit of VPR + # I set a threshold of 1000 as it is the limit of VPR die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $fix_chan_width!\n"; } else { print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; @@ -2994,11 +2995,11 @@ sub gen_csv_rpt_vtr_flow($ $) my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - # adapt to matlab format if the option is enabled + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3029,7 +3030,7 @@ sub gen_csv_rpt_vtr_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.v$//g; + $tmp =~ s/\.v$//g; print $CSVFH "$tmp"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3078,12 +3079,12 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) my ($tmp,$ikw,$tmpkw); my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled + + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3117,9 +3118,9 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) my @tokens = split('/', $tmp); $tmp = $tokens[0]; - # For matlab script, we use {} for string + # For matlab script, we use {} for string if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "{'$tmp'}"; + print $CSVFH "{'$tmp'}"; } else { print $CSVFH "$tmp"; } @@ -3171,12 +3172,12 @@ sub gen_csv_rpt_standard_flow($ $) my ($tmp,$ikw,$tmpkw); my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled + + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3207,7 +3208,7 @@ sub gen_csv_rpt_standard_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3222,7 +3223,7 @@ sub gen_csv_rpt_standard_flow($ $) @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } if ("on" eq $opt_ptr->{power}) { @@ -3258,11 +3259,11 @@ sub gen_csv_rpt_mpack2_flow($ $) my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - # adapt to matlab format if the option is enabled + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3298,7 +3299,7 @@ sub gen_csv_rpt_mpack2_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; @@ -3353,11 +3354,11 @@ sub gen_csv_rpt_mpack1_flow($ $) my @keywords; my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val}); - # adapt to matlab format if the option is enabled + # adapt to matlab format if the option is enabled if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name + # Print the data name print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented + # We will set the stats line to be commented print $CSVFH "%"; } @@ -3383,7 +3384,7 @@ sub gen_csv_rpt_mpack1_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; #foreach $tmpkw(@keywords) { print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}"; diff --git a/fpga_flow/vpr_fpga_spice_conf/sample.conf b/fpga_flow/vpr_fpga_spice_conf/sample.conf index 92d477f60..e43b53e66 100644 --- a/fpga_flow/vpr_fpga_spice_conf/sample.conf +++ b/fpga_flow/vpr_fpga_spice_conf/sample.conf @@ -12,11 +12,11 @@ hardlogic_tb_dir_name = hardlogic_tb cb_tb_dir_name = cb_tb sb_tb_dir_name = sb_tb # Prefix -top_tb_prefix = +top_tb_prefix = pb_mux_tb_prefix = _grid cb_mux_tb_prefix = _cb sb_mux_tb_prefix = _sb -lut_tb_prefix = _grid +lut_tb_prefix = _grid hardlogic_tb_prefix = _grid grid_tb_prefix = _grid cb_tb_prefix = _cb @@ -34,35 +34,34 @@ sb_tb_postfix = _sb_testbench.sp [task_conf] auto_check = on -num_pb_mux_tb = -num_cb_mux_tb = -num_sb_mux_tb = -num_lut_mux_tb = -num_hardlogic_tb = -num_grid_mux_tb = -num_top_tb = -num_cb_tb = -num_sb_tb = +num_pb_mux_tb = +num_cb_mux_tb = +num_sb_mux_tb = +num_lut_mux_tb = +num_hardlogic_tb = +num_grid_mux_tb = +num_top_tb = +num_cb_tb = +num_sb_tb = [csv_tags] #top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_io|leakage_power_local_interc|total_leakage_power_lut5|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs -top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_local_interc|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs +top_tb_leakage_power_tags = leakage_power_sram_local_routing | leakage_power_sram_luts | leakage_power_sram_cbs | leakage_power_sram_sbs | leakage_power_local_interc | total_leakage_power_lut6 | total_leakage_power_dff | leakage_power_cbs | leakage_power_sbs #top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_io|energy_per_cycle_local_routing|total_energy_per_cycle_lut5|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs -top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs #|crit_path_delay -pb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_pb_mux -cb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_cb_mux -sb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_sb_mux -pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_pb_mux -cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_cb_mux -sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_sb_mux -lut_tb_leakage_power_tags = leakage_power_sram_luts|total_leakage_power_lut6 -lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts|total_energy_per_cycle_lut6 +top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing | energy_per_cycle_sram_luts | energy_per_cycle_sram_cbs | energy_per_cycle_sram_sbs | energy_per_cycle_local_routing | total_energy_per_cycle_lut6 | total_energy_per_cycle_dff | energy_per_cycle_cbs | energy_per_cycle_sbs #|crit_path_delay +pb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_pb_mux +cb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_cb_mux +sb_mux_tb_leakage_power_tags = total_leakage_srams | total_leakage_power_sb_mux +pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_pb_mux +cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_cb_mux +sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams | total_energy_per_cycle_sb_mux +lut_tb_leakage_power_tags = leakage_power_sram_luts | total_leakage_power_lut6 +lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts | total_energy_per_cycle_lut6 hardlogic_tb_leakage_power_tags = total_leakage_power_dff hardlogic_tb_dynamic_power_tags = total_energy_per_cycle_dff -grid_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_local_routing|total_leakage_power_lut6|total_leakage_power_dff -grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing|total_energy_per_cycle_sram_luts|total_energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff -cb_tb_leakage_power_tags = leakage_power_cb|leakage_power_sram_cb -cb_tb_dynamic_power_tags = energy_per_cycle_cb|energy_per_cycle_sram_cb -sb_tb_leakage_power_tags = leakage_power_sb|leakage_power_sram_sb -sb_tb_dynamic_power_tags = energy_per_cycle_sb|energy_per_cycle_sram_sb - +grid_tb_leakage_power_tags = leakage_power_sram_local_routing | leakage_power_sram_luts | leakage_power_local_routing | total_leakage_power_lut6 | total_leakage_power_dff +grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing | total_energy_per_cycle_sram_luts | total_energy_per_cycle_local_routing | total_energy_per_cycle_lut6 | total_energy_per_cycle_dff +cb_tb_leakage_power_tags = leakage_power_cb | leakage_power_sram_cb +cb_tb_dynamic_power_tags = energy_per_cycle_cb | energy_per_cycle_sram_cb +sb_tb_leakage_power_tags = leakage_power_sb | leakage_power_sram_sb +sb_tb_dynamic_power_tags = energy_per_cycle_sb | energy_per_cycle_sram_sb diff --git a/run_local.bat b/run_local.bat index 578f750ce..79c20324a 100755 --- a/run_local.bat +++ b/run_local.bat @@ -1,2 +1,2 @@ -docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh +docker run -it --rm -v "%cd%":/localfile/OpenFPGA -w="/localfile/OpenFPGA" goreganesh/open_fpga bash pause From c8d04c4f0018cbf85c76f531ba4d63044d69c4cc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 8 Aug 2019 21:20:28 -0600 Subject: [PATCH 034/482] plug in fast look-up builder --- .../fpga_spice_include/circuit_library.cpp | 134 +++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 22 ++- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 6 + 3 files changed, 151 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 6e067ce3e..b552ebd2b 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -54,6 +54,10 @@ CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); } +CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& circuit_model_id) const { + return vtr::make_range(port_ids_[circuit_model_id].begin(), port_ids_[circuit_model_id].end()); +} + /************************************************************************ * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ @@ -153,6 +157,13 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ /************************************************************************ * Public Accessors : Basic data query on Circuit Porst ***********************************************************************/ +/* Access the type of a port of a circuit model */ +size_t CircuitLibrary::num_ports(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return port_ids_[circuit_model_id].size(); +} + /* Access the type of a port of a circuit model */ enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { @@ -255,7 +266,7 @@ bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, * Public Accessors : Methods to find circuit model ***********************************************************************/ /* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::get_circuit_model_id_by_name(const std::string& name) const { +CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { CircuitModelId ret = CIRCUIT_MODEL_OPEN_ID; size_t num_found = 0; for (circuit_model_string_iterator it = circuit_model_names_.begin(); @@ -276,7 +287,7 @@ CircuitModelId CircuitLibrary::get_circuit_model_id_by_name(const std::string& n } /* Get the CircuitModelId of a default circuit model with a given type */ -CircuitModelId CircuitLibrary::get_default_circuit_model_id(const enum e_spice_model_type& type) const { +CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_type& type) const { /* Default circuit model id is the first element by type in the fast look-up */ return circuit_model_lookup_[size_t(type)].front(); } @@ -406,6 +417,8 @@ void CircuitLibrary::set_circuit_model_type(const CircuitModelId& circuit_model_ /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); circuit_model_types_[circuit_model_id] = type; + /* Build the fast look-up for circuit models */ + build_circuit_model_lookup(); return; } @@ -591,6 +604,8 @@ void CircuitLibrary::set_port_type(const CircuitModelId& circuit_model_id, /* validate the circuit_port_id */ VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_types_[circuit_model_id][circuit_port_id] = port_type; + /* Build the fast look-up for circuit model ports */ + build_circuit_model_port_lookup(circuit_model_id); return; } @@ -1098,7 +1113,7 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, } /************************************************************************ - * Internal Mutators + * Internal Mutators: builders and linkers ***********************************************************************/ /* Set the information for a buffer * For a buffer type, we check if it is in the range of vector @@ -1124,21 +1139,112 @@ void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_mode return; } +/* Link the circuit_model_id for each port of a circuit model. + * We search the inv_circuit_model_name in the CircuitLibrary and + * configure the port inv_circuit_model_id + */ +void CircuitLibrary::link_port_circuit_model(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Walk through each ports, get the port id and find the circuit model id by name */ + for (auto& port_id : ports(circuit_model_id)) { + /* Bypass empty name */ + if (true == port_circuit_model_names_[circuit_model_id][port_id].empty()) { + continue; + } + port_circuit_model_ids_[circuit_model_id][port_id] = circuit_model(port_circuit_model_names_[circuit_model_id][port_id]); + } + return; +} + /* Link the inv_circuit_model_id for each port of a circuit model. * We search the inv_circuit_model_name in the CircuitLibrary and * configure the port inv_circuit_model_id */ -void CircuitLibrary::set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { +void CircuitLibrary::link_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* TODO: complete this function when port mutators are finished */ + /* Walk through each ports, get the port id and find the circuit model id by name */ + for (auto& port_id : ports(circuit_model_id)) { + /* Bypass empty name */ + if (true == port_inv_circuit_model_names_[circuit_model_id][port_id].empty()) { + continue; + } + port_inv_circuit_model_ids_[circuit_model_id][port_id] = circuit_model(port_inv_circuit_model_names_[circuit_model_id][port_id]); + } return; } +/* Link all the circuit model ids for each port of a circuit model */ +void CircuitLibrary::link_port_circuit_models(const CircuitModelId& circuit_model_id) { + link_port_circuit_model(circuit_model_id); + link_port_inv_circuit_model(circuit_model_id); + return; +} + +/* Link the buffer_circuit_model + * We search the buffer_circuit_model_name in the CircuitLibrary and + * configure the buffer_circuit_model_id + */ +void CircuitLibrary::link_buffer_circuit_model(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Get the circuit model id by name, skip those with empty names*/ + for (size_t buffer_id = 0; buffer_id < buffer_circuit_model_names_[circuit_model_id].size(); ++buffer_id) { + if (true == buffer_circuit_model_names_[circuit_model_id][buffer_id].empty()) { + return; + } + buffer_circuit_model_ids_[circuit_model_id][buffer_id] = circuit_model(buffer_circuit_model_names_[circuit_model_id][buffer_id]); + } + return; +} + +/* Link the buffer_circuit_model + * We search the buffer_circuit_model_name in the CircuitLibrary and + * configure the buffer_circuit_model_id + */ +void CircuitLibrary::link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Get the circuit model id by name, skip those with empty names*/ + if (true == pass_gate_logic_circuit_model_names_[circuit_model_id].empty()) { + return; + } + pass_gate_logic_circuit_model_ids_[circuit_model_id] = circuit_model(pass_gate_logic_circuit_model_names_[circuit_model_id]); + return; +} + +/* Build the links for attributes of each circuit_model by searching the circuit_model_names */ +void CircuitLibrary::build_circuit_model_links() { + /* Walk through each circuit model, build links one by one */ + for (auto& circuit_model_id : circuit_models()) { + /* Build links for buffers, pass-gates circuit_model */ + link_buffer_circuit_model(circuit_model_id); + link_pass_gate_logic_circuit_model(circuit_model_id); + /* Build links for ports */ + link_port_circuit_models(circuit_model_id); + } + return; +} + +/* Build the timing graph for a circuit models*/ +void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { + return; +} + +/* Build the timing graph for a circuit models*/ +void CircuitLibrary::build_timing_graphs() { + /* Walk through each circuit model, build timing graph one by one */ + for (auto& circuit_model_id : circuit_models()) { + build_circuit_model_timing_graph(circuit_model_id); + } + return; +} /************************************************************************ * Internal mutators: build fast look-ups ***********************************************************************/ +/* Build fast look-up for circuit models */ void CircuitLibrary::build_circuit_model_lookup() { /* invalidate fast look-up */ invalidate_circuit_model_lookup(); @@ -1150,6 +1256,10 @@ void CircuitLibrary::build_circuit_model_lookup() { } /* Make the default circuit_model to be the first element for each type */ for (auto& type : circuit_model_lookup_) { + /* Skip zero-length parts of look-up */ + if (true == type.empty()) { + continue; + } /* if the first element is already a default model, we skip this */ if (true == circuit_model_is_default_[type[0]]) { continue; @@ -1167,6 +1277,20 @@ void CircuitLibrary::build_circuit_model_lookup() { return; } +/* Build fast look-up for circuit model ports */ +void CircuitLibrary::build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) { + /* invalidate fast look-up */ + invalidate_circuit_model_port_lookup(circuit_model_id); + /* Classify circuit models by type */ + circuit_model_port_lookup_[size_t(circuit_model_id)].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + /* Walk through circuit_models and categorize */ + for (auto& port_id : port_ids_[circuit_model_id]) { + circuit_model_port_lookup_[size_t(circuit_model_id)][port_type(circuit_model_id, port_id)].push_back(port_id); + } + return; +} + + /************************************************************************ * Internal invalidators/validators ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 04eb75fd5..612e99ff1 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -233,6 +233,8 @@ class CircuitLibrary { bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ + circuit_port_range ports(const CircuitModelId& circuit_model_id) const; + size_t num_ports(const CircuitModelId& circuit_model_id) const; enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -246,8 +248,8 @@ class CircuitLibrary { bool port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Methods to find circuit model */ - CircuitModelId get_circuit_model_id_by_name(const std::string& name) const ; - CircuitModelId get_default_circuit_model_id(const enum e_spice_model_type& type) const; + CircuitModelId circuit_model(const std::string& name) const; + CircuitModelId default_circuit_model(const enum e_spice_model_type& type) const; public: /* Public Mutators */ CircuitModelId add_circuit_model(); /* Fundamental information */ @@ -407,11 +409,19 @@ class CircuitLibrary { const float& c_val); void set_wire_num_levels(const CircuitModelId& circuit_model_id, const size_t& num_level); - public: /* Internal mutators: link circuit_models */ + public: /* Public Mutators: builders */ void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_port_inv_circuit_model(const CircuitModelId& circuit_model_id); + void link_port_circuit_model(const CircuitModelId& circuit_model_id); + void link_port_inv_circuit_model(const CircuitModelId& circuit_model_id); + void link_port_circuit_models(const CircuitModelId& circuit_model_id); + void link_buffer_circuit_model(const CircuitModelId& circuit_model_id); + void link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id); + void build_circuit_model_links(); + void build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); + void build_timing_graphs(); public: /* Internal mutators: build fast look-ups */ void build_circuit_model_lookup(); + void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); private: /* Internal invalidators/validators */ /* Validators */ bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; @@ -482,8 +492,8 @@ class CircuitLibrary { /* Timing graphs */ vtr::vector> edge_ids_; - vtr::vector>> port_in_edge_ids_; - vtr::vector>> port_out_edge_ids_; + vtr::vector>> port_in_edge_ids_; + vtr::vector>> port_out_edge_ids_; vtr::vector> edge_src_ports_; vtr::vector> edge_src_pin_ids_; vtr::vector> edge_sink_ports_; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 5c5d38d3c..ba7cb7cec 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1743,6 +1743,12 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m } } + /* Build circuit_model links */ + circuit_lib.build_circuit_model_links(); + + /* Build timing graph */ + circuit_lib.build_timing_graphs(); + return circuit_lib; } From b82369dd967be11a4a4226d9545a3f0db891904b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 9 Aug 2019 00:17:06 -0600 Subject: [PATCH 035/482] Added first draft of fpga_task script --- openfpga_flow/.gitignore | 1 + .../k6_N10_rram_memory_bank_SC_winbond90.xml | 524 ++ .../benchmarks/MCNC_Verilog/alu4/alu4.v | 802 ++ .../benchmarks/MCNC_Verilog/apex2/apex2.v | 1036 +++ .../benchmarks/MCNC_Verilog/apex4/apex4.v | 792 ++ .../benchmarks/MCNC_Verilog/bigkey/bigkey.v | 2197 +++++ .../benchmarks/MCNC_Verilog/clma/clma.v | 4776 ++++++++++ .../benchmarks/MCNC_Verilog/des/des.v | 1822 ++++ .../benchmarks/MCNC_Verilog/diffeq/diffeq.v | 1523 ++++ .../benchmarks/MCNC_Verilog/dsip/dsip.v | 1917 ++++ .../MCNC_Verilog/elliptic/elliptic.v | 5343 ++++++++++++ .../benchmarks/MCNC_Verilog/ex1010/ex1010.v | 930 ++ .../benchmarks/MCNC_Verilog/ex5p/ex5p.v | 588 ++ .../benchmarks/MCNC_Verilog/frisc/frisc.v | 4994 +++++++++++ .../benchmarks/MCNC_Verilog/misex3/misex3.v | 805 ++ .../benchmarks/MCNC_Verilog/pdc/pdc.v | 2558 ++++++ .../benchmarks/MCNC_Verilog/s298/s298.v | 69 + .../benchmarks/MCNC_Verilog/s38417/s38417.v | 6731 +++++++++++++++ .../benchmarks/MCNC_Verilog/s38584/s38584.v | 7675 +++++++++++++++++ .../benchmarks/MCNC_Verilog/seq/seq.v | 1127 +++ .../benchmarks/MCNC_Verilog/spla/spla.v | 2462 ++++++ .../benchmarks/MCNC_Verilog/tseng/tseng.v | 1648 ++++ openfpga_flow/docs/KeyExampleTasks.txt | 26 + openfpga_flow/misc/fpga_flow_script.conf | 31 + openfpga_flow/misc/fpga_flow_template.sh | 38 + .../misc/openfpga_benchmark_list.txt | 6 + openfpga_flow/scripts/run_fpga_task.conf | 9 + openfpga_flow/scripts/run_fpga_task.py | 219 + .../basic_flow/config/golden_results.txt | 2 + .../tasks/basic_flow/config/task.conf | 54 + openfpga_flow/tasks/basic_flow/latest | 5 + .../winbond90nm_power_properties.xml | 7493 ++++++++++++++++ 32 files changed, 58203 insertions(+) create mode 100644 openfpga_flow/.gitignore create mode 100644 openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/apex2/apex2.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/apex4/apex4.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/bigkey/bigkey.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/clma/clma.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/des/des.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/diffeq/diffeq.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/dsip/dsip.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/ex1010/ex1010.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/ex5p/ex5p.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/frisc/frisc.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/misex3/misex3.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/pdc/pdc.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/s38584/s38584.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/seq/seq.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/spla/spla.v create mode 100644 openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v create mode 100644 openfpga_flow/docs/KeyExampleTasks.txt create mode 100644 openfpga_flow/misc/fpga_flow_script.conf create mode 100644 openfpga_flow/misc/fpga_flow_template.sh create mode 100644 openfpga_flow/misc/openfpga_benchmark_list.txt create mode 100644 openfpga_flow/scripts/run_fpga_task.conf create mode 100644 openfpga_flow/scripts/run_fpga_task.py create mode 100644 openfpga_flow/tasks/basic_flow/config/golden_results.txt create mode 100644 openfpga_flow/tasks/basic_flow/config/task.conf create mode 100644 openfpga_flow/tasks/basic_flow/latest create mode 100644 openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml diff --git a/openfpga_flow/.gitignore b/openfpga_flow/.gitignore new file mode 100644 index 000000000..d920b27b0 --- /dev/null +++ b/openfpga_flow/.gitignore @@ -0,0 +1 @@ +local_test_folder/ \ No newline at end of file diff --git a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml new file mode 100644 index 000000000..f0c7e5752 --- /dev/null +++ b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml @@ -0,0 +1,524 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v b/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v new file mode 100644 index 000000000..e5cd63a4e --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v @@ -0,0 +1,802 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 10:08:03 2019 + +module alu4 ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, + i_11_, i_12_, i_13_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, + i_10_, i_11_, i_12_, i_13_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_; + wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, + n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, + n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, + n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, + n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, + n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, + n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, + n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, + n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, + n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, + n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, + n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, + n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, + n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, + n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, + n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, + n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, + n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, + n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, + n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, + n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, + n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, + n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, + n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, + n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, + n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, + n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, + n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, + n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, + n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, + n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, + n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, + n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, + n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, + n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, + n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, + n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, + n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, + n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, + n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, + n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, + n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, + n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, + n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, + n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, + n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, + n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, + n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, + n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, + n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, + n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, + n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, + n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, + n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, + n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, + n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, + n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, + n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, + n748, n749, n750, n751; + assign o_0_ = ~n42; + assign o_1_ = ~n509; + assign o_2_ = ~n502; + assign o_3_ = ~n488; + assign o_4_ = ~n41; + assign o_5_ = ~n659 | ~n662 | n40 | ~n658 | n38 | n39 | n36 | n37; + assign o_6_ = ~n35; + assign o_7_ = ~n636 | ~n637 | n34 | ~n576 | n32 | n33 | n30 | n31; + assign n30 = ~i_9_ & (~n163 | n165 | n168); + assign n31 = i_9_ & n65 & n419; + assign n32 = ~i_5_ & (~n625 | (~n238 & n250)); + assign n33 = i_9_ & (n66 | ~n621 | ~n622); + assign n34 = n244 | n246 | n240 | n242 | ~n630 | ~n632 | n248 | n249; + assign n35 = n278 & n279 & (~i_2_ | n277); + assign n36 = i_11_ & (~n650 | (~n266 & n360)); + assign n37 = i_2_ & n361 & n272; + assign n38 = ~n71 & ~n532; + assign n39 = ~n562 & (~n648 | (~i_13_ & ~n532)); + assign n40 = ~i_4_ & (~n647 | (~n59 & ~n281)); + assign n41 = n473 & n472 & n471 & n470 & n469 & ~n465 & ~n459 & ~n461; + assign n42 = ~n46 & n510 & (~i_0_ | n511); + assign n43 = ~i_1_ | ~i_3_; + assign n44 = ~i_5_ | n43; + assign n45 = ~i_8_ & i_10_; + assign n46 = i_3_ & (n45 | ~n435); + assign n47 = ~n67 & (~i_6_ | ~i_10_); + assign n48 = (n521 | n52) & (n56 | n120); + assign n49 = i_1_ | n445; + assign n50 = i_11_ | n116; + assign n51 = n48 & (n49 | n50); + assign n52 = i_12_ | n116; + assign n53 = i_0_ | n225; + assign n54 = (i_11_ | n53) & (n49 | n52); + assign n55 = ~i_6_ | i_7_; + assign n56 = i_0_ | n212; + assign n57 = ~i_2_ | i_0_ | i_1_; + assign n58 = (i_6_ | n57) & (n55 | n56); + assign n59 = ~i_3_ | n225; + assign n60 = ~i_3_ | n445; + assign n61 = (~i_6_ | n60) & (~i_5_ | n59); + assign n62 = i_0_ | n63; + assign n63 = i_3_ | i_2_; + assign n64 = n62 & (~i_5_ | n63); + assign n65 = ~i_12_ & i_13_; + assign n66 = n65 & (~n613 | (i_8_ & ~n379)); + assign n67 = i_6_ & n519; + assign n68 = ~n158 & (~n615 | (n67 & ~n400)); + assign n69 = (i_7_ | n200) & (i_6_ | n62); + assign n70 = n69 & (i_8_ | n56); + assign n71 = ~i_12_ | n116; + assign n72 = (~i_1_ | n71) & (~i_6_ | ~n348); + assign n73 = ~i_1_ & i_6_; + assign n74 = (~i_0_ | n73) & (~i_1_ | i_5_); + assign n75 = ~n304 & ~i_9_ & ~n77; + assign n76 = i_3_ & (n75 | (~n71 & ~n98)); + assign n77 = ~i_11_ | n116; + assign n78 = i_8_ | i_6_; + assign n79 = n77 | n78 | ~i_2_ | i_9_; + assign n80 = ~i_0_ | n63; + assign n81 = ~i_0_ | n195; + assign n82 = (i_7_ | n81) & (i_6_ | n80); + assign n83 = i_0_ & (n76 | ~n79 | ~n627); + assign n84 = i_3_ | ~i_11_ | n56 | ~n348; + assign n85 = n116 | n400 | ~i_3_ | i_9_; + assign n86 = n178 | ~i_5_ | n72; + assign n87 = n516 | n177 | ~n338; + assign n88 = i_9_ | n74 | n522 | n77; + assign n89 = n88 & n87 & n86 & n85 & ~n83 & n84; + assign n90 = (n99 | n157) & (n134 | n521); + assign n91 = ~i_6_ | n522; + assign n92 = n90 & (n91 | n49); + assign n93 = (~n102 | n521) & (~n67 | n157); + assign n94 = (n518 | n49) & (n520 | n400); + assign n95 = n93 & n94; + assign n96 = (~n103 | n134) & (n53 | n107); + assign n97 = n96 & (n57 | n91); + assign n98 = ~i_6_ | n272; + assign n99 = i_8_ | ~i_6_ | ~i_7_; + assign n100 = n98 & n97 & (n99 | n56); + assign n101 = i_5_ & n365; + assign n102 = ~i_6_ & n519; + assign n103 = ~i_2_ & ~i_0_ & i_1_; + assign n104 = n101 & (~n607 | (n102 & n103)); + assign n105 = i_11_ | ~n166; + assign n106 = i_10_ | n304; + assign n107 = i_6_ | n522; + assign n108 = (n107 | n50) & (n105 | n106); + assign n109 = i_12_ | n113; + assign n110 = i_11_ | n113; + assign n111 = (~n67 | n109) & (n99 | n110); + assign n112 = i_11_ | i_12_; + assign n113 = i_9_ | i_13_; + assign n114 = i_3_ | i_10_ | n112 | n113; + assign n115 = i_5_ | n312; + assign n116 = i_10_ | i_13_; + assign n117 = (~i_10_ | n115) & (n116 | ~n164); + assign n118 = i_13_ & (~n600 | (~n547 & ~n548)); + assign n119 = i_5_ | n515; + assign n120 = i_12_ | ~n338; + assign n121 = (n119 | n120) & (~n164 | ~n239); + assign n122 = n65 & (~n599 | (~i_3_ & ~i_11_)); + assign n123 = n555 | n518 | n554; + assign n124 = n553 | n134 | n552; + assign n125 = n522 | n198 | ~n247; + assign n126 = ~n348 | ~n67 | ~n101; + assign n127 = n449 | n107 | ~n338; + assign n128 = n524 | n99 | ~n319; + assign n129 = (n544 | n546) & (n121 | n520); + assign n130 = n129 & n128 & n127 & n126 & n125 & n124 & ~n122 & n123; + assign n131 = (n107 | ~n419) & (n91 | ~n402); + assign n132 = (n171 | n151) & (n150 | n551); + assign n133 = n597 & n598 & (n545 | n550); + assign n134 = ~i_7_ | n78; + assign n135 = ~n101 | ~n239; + assign n136 = n132 & n133 & (n134 | n135); + assign n137 = i_4_ | ~i_0_ | ~i_1_; + assign n138 = i_4_ | n445; + assign n139 = (~i_6_ | n138) & (~i_7_ | n137); + assign n140 = ~n524 & ~n220 & i_2_ & ~i_8_; + assign n141 = n546 | n549; + assign n142 = n162 | n107 | n158; + assign n143 = n555 | ~n102 | n554; + assign n144 = n553 | n91 | n552; + assign n145 = (n194 | n151) & (n198 | n551); + assign n146 = (n134 | n543) & (n547 | n550); + assign n147 = n146 & n145 & n144 & n143 & n141 & n142; + assign n148 = (n171 | n551) & (n99 | n543); + assign n149 = n595 & n596 & (n545 | n549); + assign n150 = ~i_5_ | n201; + assign n151 = ~n65 | ~n264; + assign n152 = n148 & n149 & (n150 | n151); + assign n153 = (n99 | ~n402) & (n91 | ~n419); + assign n154 = (n544 | n547) & (n172 | n198); + assign n155 = n593 & n594 & (n542 | n546); + assign n156 = n154 & n155 & (n91 | n135); + assign n157 = ~i_0_ | n212; + assign n158 = ~i_5_ | n312; + assign n159 = n158 | n157 | n134; + assign n160 = n115 | n99 | ~n103; + assign n161 = i_2_ | n312; + assign n162 = ~i_10_ | ~n319; + assign n163 = n161 | n162 | ~i_5_ | n91; + assign n164 = ~i_5_ & i_3_ & i_4_; + assign n165 = n164 & ~n77 & i_1_ & ~i_7_; + assign n166 = ~i_12_ & ~i_13_; + assign n167 = i_10_ & i_11_; + assign n168 = n166 & n167 & (~n159 | ~n160); + assign n169 = (n542 | n545) & (n541 | n150); + assign n170 = (n107 | n135) & (~n446 | n544); + assign n171 = i_3_ | n539; + assign n172 = ~n65 | ~n437; + assign n173 = n169 & n170 & (n171 | n172); + assign n174 = (~n446 | n542) & (n171 | n541); + assign n175 = (n544 | n545) & (n91 | n543); + assign n176 = n174 & n175 & (n172 | n150); + assign n177 = i_10_ | n522; + assign n178 = ~i_8_ | n272; + assign n179 = n177 & n178; + assign n180 = (~n460 | n591) & (n179 | ~n463); + assign n181 = n592 & (n533 | n56); + assign n182 = n106 & n98; + assign n183 = n180 & n181 & (n182 | ~n385); + assign n184 = (~n340 | n535) & (n106 | n449); + assign n185 = i_8_ | n534; + assign n186 = ~i_4_ | n212; + assign n187 = n184 & (n185 | n186); + assign n188 = (~n536 | n537) & (n335 | n538); + assign n189 = (n186 | n474) & (n98 | ~n101); + assign n190 = ~i_5_ | n272; + assign n191 = n188 & n189 & (n190 | ~n340); + assign n192 = (n518 | n521) & (n520 | n157); + assign n193 = n192 & (n49 | ~n102); + assign n194 = i_3_ | n214; + assign n195 = i_1_ | i_3_; + assign n196 = n194 & (~i_5_ | n195); + assign n197 = ~i_6_ | i_0_ | i_3_; + assign n198 = i_3_ | n516; + assign n199 = n198 & (i_5_ | n195); + assign n200 = i_0_ | n195; + assign n201 = i_3_ | i_6_; + assign n202 = n200 & n199 & (i_0_ | n201); + assign n203 = ~i_6_ | ~i_0_ | ~i_3_; + assign n204 = i_1_ & ~i_6_; + assign n205 = (i_2_ | ~i_6_) & (~i_7_ | n204); + assign n206 = n517 | i_6_ | n749; + assign n207 = n517 | i_1_ | i_7_; + assign n208 = i_11_ | n435; + assign n209 = n206 & n207 & (n205 | n208); + assign n210 = i_5_ | n63; + assign n211 = i_2_ | n516; + assign n212 = i_1_ | i_2_; + assign n213 = n211 & (i_5_ | n212); + assign n214 = ~i_5_ | ~i_6_; + assign n215 = (~i_5_ | n212) & (i_2_ | n214); + assign n216 = (~i_5_ | n225) & (~i_2_ | n214); + assign n217 = ~i_6_ | n445; + assign n218 = n216 & n217; + assign n219 = ~i_7_ | ~i_1_ | ~i_5_; + assign n220 = ~i_1_ & ~i_6_; + assign n221 = n219 & (~i_0_ | ~i_7_ | n220); + assign n222 = i_10_ & ~n435 & (~n218 | ~n221); + assign n223 = ~i_2_ | n516; + assign n224 = i_6_ | n445; + assign n225 = ~i_1_ | ~i_2_; + assign n226 = n223 & n224 & (i_5_ | n225); + assign n227 = n226 & (i_7_ | n74); + assign n228 = (~i_0_ | i_6_) & (~i_1_ | i_5_); + assign n229 = (i_6_ | n138) & (i_7_ | n137); + assign n230 = n73 | n119 | ~i_2_ | ~i_8_; + assign n231 = n230 & (n229 | ~n475); + assign n232 = (n53 | ~n67) & (~n103 | n518); + assign n233 = n232 & (n57 | ~n102); + assign n234 = ~i_4_ | n225; + assign n235 = ~i_4_ | n557; + assign n236 = (i_6_ | n235) & (i_8_ | n234); + assign n237 = i_4_ & (~n623 | (~i_1_ & ~n177)); + assign n238 = ~n237 & (i_6_ | i_10_ | ~n536); + assign n239 = ~i_9_ & n338; + assign n240 = n239 & n164 & ~n233; + assign n241 = n406 & ~i_10_ & ~i_13_; + assign n242 = ~n119 & (~n580 | (~n92 & n241)); + assign n243 = ~i_3_ & ~i_8_; + assign n244 = ~n525 & (n140 | (~n139 & n243)); + assign n245 = n383 & ~i_9_ & ~i_13_; + assign n246 = ~n524 & (~n582 | (~n193 & n245)); + assign n247 = ~i_11_ & i_13_; + assign n248 = n247 & (~n584 | (~n223 & ~n528)); + assign n249 = n65 & (~n586 | ~n588 | ~n590); + assign n250 = n338 & i_12_; + assign n251 = n250 & (~n183 | ~n187 | ~n191); + assign n252 = ~n71 & (~n609 | ~n610 | ~n611); + assign n253 = ~n247 & (i_4_ | ~i_8_ | ~n406); + assign n254 = (~i_3_ | n208) & (~n338 | n533); + assign n255 = n253 & n254 & (n120 | ~n475); + assign n256 = ~i_7_ | i_10_; + assign n257 = i_4_ | ~n383; + assign n258 = (~i_7_ | n257) & (n256 | ~n318); + assign n259 = i_7_ & n45; + assign n260 = (i_8_ | n258) & (~n259 | n559); + assign n261 = n260 & ~n731 & (i_7_ | n255); + assign n262 = ~i_7_ | ~i_9_; + assign n263 = n262 & (i_7_ | ~i_10_); + assign n264 = i_10_ & ~i_7_ & i_8_; + assign n265 = i_12_ & (n264 | ~n548); + assign n266 = ~i_10_ | n522; + assign n267 = i_8_ | n262; + assign n268 = ~n265 & (~i_11_ | (n266 & n267)); + assign n269 = (n110 | ~n243) & (n109 | ~n475); + assign n270 = ~i_4_ | n116; + assign n271 = n270 & (~i_8_ | n52); + assign n272 = ~i_7_ | i_9_; + assign n273 = ~i_4_ | n272; + assign n274 = (i_7_ | n271) & (i_13_ | n273); + assign n275 = n282 & (i_4_ | n268); + assign n276 = n556 & n638 & (i_3_ | n274); + assign n277 = n275 & n276 & (~i_13_ | n263); + assign n278 = ~n750 & (n548 | n559); + assign n279 = n644 & n645 & (i_2_ | n261); + assign n280 = ~i_6_ | ~i_9_; + assign n281 = n280 & (i_6_ | ~i_10_); + assign n282 = n332 | n116; + assign n283 = (n523 & (~i_7_ | n733)) | (i_7_ & n733); + assign n284 = i_2_ | i_13_; + assign n285 = n282 & (n283 | n284); + assign n286 = i_10_ | i_7_; + assign n287 = i_11_ | n286; + assign n288 = i_11_ | i_13_; + assign n289 = (~n166 | n287) & (n177 | n288); + assign n290 = i_8_ | n272; + assign n291 = (n288 | n290) & (~n166 | n178); + assign n292 = (n289 & (~i_6_ | n291)) | (i_6_ & n291); + assign n293 = (n523 & (~i_8_ | n733)) | (i_8_ & n733); + assign n294 = n292 & (i_13_ | n293); + assign n295 = (~i_7_ & n566) | (n565 & (i_7_ | n566)); + assign n296 = i_7_ | n435; + assign n297 = n295 & (~i_6_ | ~i_11_ | n296); + assign n298 = n287 & (i_12_ | n256); + assign n299 = ~i_2_ & ~n751 & (i_6_ | ~n298); + assign n300 = ~n299 & (~i_4_ | ~n578); + assign n301 = n591 | i_2_ | ~i_4_; + assign n302 = n300 & n301 & (n182 | ~n365); + assign n303 = ~i_7_ | n280; + assign n304 = i_6_ | i_7_; + assign n305 = n303 & (~i_10_ | (~i_9_ & n304)); + assign n306 = (i_6_ & ~n540) | (~n266 & (~i_6_ | ~n540)); + assign n307 = ~i_4_ & (~n577 | (i_11_ & n306)); + assign n308 = (n294 & (~i_3_ | n297)) | (i_3_ & n297); + assign n309 = (~i_13_ & n302) | (n281 & (i_13_ | n302)); + assign n310 = ~n307 & n656 & (~i_2_ | n305); + assign n311 = n310 & n309 & n308 & n285; + assign n312 = ~i_3_ | i_4_; + assign n313 = (n312 | ~n406) & (n284 | ~n383); + assign n314 = (~i_4_ | ~n338) & (i_3_ | n120); + assign n315 = ~n247 & (~i_3_ | ~n406 | n548); + assign n316 = (~i_2_ | n530) & (~i_7_ | n313); + assign n317 = n315 & n316 & (n314 | n178); + assign n318 = i_4_ & n348; + assign n319 = ~i_11_ & n348; + assign n320 = ~n177 & (n318 | (~i_3_ & n319)); + assign n321 = ~n402 | ~i_2_ | i_7_; + assign n322 = ~n319 | n563; + assign n323 = ~n383 | ~i_3_ | n266; + assign n324 = n257 | ~i_2_ | i_8_; + assign n325 = ~n65 & (i_7_ | n312 | ~n383); + assign n326 = n325 & n324 & n323 & n322 & ~n320 & n321; + assign n327 = i_11_ | ~n496 | n558 | ~n563; + assign n328 = (n317 & (~i_6_ | n326)) | (i_6_ & n326); + assign n329 = n327 & n328 & (n91 | n257); + assign n330 = ~i_11_ | n514; + assign n331 = ~n166 | ~n475; + assign n332 = ~i_4_ | i_9_; + assign n333 = (n332 | n77) & (n330 | n331); + assign n334 = ~n517 & i_3_ & i_12_; + assign n335 = i_1_ | n63; + assign n336 = ~i_11_ | ~n166; + assign n337 = (n335 | n336) & (n186 | ~n239); + assign n338 = i_11_ & ~i_13_; + assign n339 = i_4_ & (~n652 | (~n335 & n338)); + assign n340 = ~i_1_ & n365; + assign n341 = i_7_ & (n334 | (n340 & n239)); + assign n342 = n734 & (~i_8_ | n337); + assign n343 = (n208 | n561) & (n404 | n356); + assign n344 = (n517 | n557) & (~n45 | n59); + assign n345 = n344 & n343 & n342 & ~n341 & n333 & ~n339; + assign n346 = ~i_2_ | i_12_; + assign n347 = (~i_8_ | n59) & (n346 | ~n391); + assign n348 = i_12_ & ~i_13_; + assign n349 = n348 & (~n654 | (i_4_ & ~n335)); + assign n350 = n655 & (i_8_ | ~n402 | n561); + assign n351 = ~n349 & n350 & (~i_9_ | n347); + assign n352 = ~i_8_ | i_9_; + assign n353 = (~n263 | ~n340) & (n186 | n352); + assign n354 = i_10_ | n78; + assign n355 = ~i_6_ | n352; + assign n356 = ~i_1_ | n312; + assign n357 = (n303 | n356) & (~n259 | ~n360); + assign n358 = ~n573 & (~i_4_ | i_13_ | ~n496); + assign n359 = ~n512 & (i_6_ | i_11_); + assign n360 = i_3_ & n204; + assign n361 = ~i_6_ & n419; + assign n362 = ~i_9_ | ~i_11_; + assign n363 = ~i_12_ | n362; + assign n364 = ~i_4_ | n113; + assign n365 = ~i_3_ & i_4_; + assign n366 = ~i_9_ | ~i_12_; + assign n367 = n364 & (n365 | n366); + assign n368 = (~i_9_ & n572) | (~i_13_ & (i_9_ | n572)); + assign n369 = i_3_ | n111; + assign n370 = ~n166 | i_2_ | n98; + assign n371 = (~i_1_ | n280) & (n363 | ~n391); + assign n372 = (~n67 | n367) & (i_4_ | n363); + assign n373 = ~n737 & n372 & n371 & n370 & n368 & n369; + assign n374 = ~i_4_ & (~n564 | (~n107 & n167)); + assign n375 = ~n736 & (~i_10_ | (~i_13_ & ~n204)); + assign n376 = ~n374 & n687 & (n107 | n270); + assign n377 = n375 & n376 & (i_3_ | n108); + assign n378 = i_7_ | n516; + assign n379 = ~i_7_ | n214; + assign n380 = (n113 | n379) & (n378 | n116); + assign n381 = ~i_2_ & (~n686 | (~n270 & ~n440)); + assign n382 = ~n53 & i_3_ & ~i_8_; + assign n383 = i_11_ & ~i_12_; + assign n384 = n383 & i_10_ & ~i_0_ & i_2_; + assign n385 = ~i_0_ & n365; + assign n386 = ~i_6_ & (n384 | (~n71 & n385)); + assign n387 = (n56 | ~n319) & (n53 | ~n402); + assign n388 = i_0_ | n43; + assign n389 = ~n386 & n387 & (n257 | n388); + assign n390 = (~i_7_ | n81) & (~i_6_ | n80); + assign n391 = i_8_ & i_3_; + assign n392 = ~n400 & (i_7_ | n391); + assign n393 = (i_3_ & n553) | (~n241 & (~i_3_ | n553)); + assign n394 = n257 & n393 & (~i_4_ | n71); + assign n395 = ~i_12_ | n572; + assign n396 = ~n65 & (i_2_ | n106 | ~n319); + assign n397 = n395 & n396 & (n394 | n107); + assign n398 = ~i_7_ | n362; + assign n399 = (i_2_ | n355) & (n204 | n178); + assign n400 = ~i_1_ | n445; + assign n401 = (~i_8_ | n400) & (~i_6_ | n60); + assign n402 = i_10_ & ~i_12_; + assign n403 = n402 & (n382 | (~i_0_ & n204)); + assign n404 = i_7_ | ~n167; + assign n405 = n167 & (~n718 | (~i_8_ & ~n400)); + assign n406 = ~i_11_ & i_12_; + assign n407 = n406 & (~n674 | (i_8_ & ~n53)); + assign n408 = ~i_0_ | n43; + assign n409 = ~n405 & ~n407 & (n404 | n408); + assign n410 = ~n247 & (~i_1_ | i_11_ | n280); + assign n411 = n672 & (~n67 | (~n423 & n673)); + assign n412 = n410 & n411 & (~n73 | n336); + assign n413 = ~n385 | ~i_6_ | ~n239; + assign n414 = ~n166 | ~i_11_ | n56; + assign n415 = n413 & n414 & (n200 | ~n423); + assign n416 = n238 & (~i_4_ | i_6_ | n177); + assign n417 = ~i_7_ & n419; + assign n418 = n417 & i_2_ & i_12_; + assign n419 = i_10_ & ~i_11_; + assign n420 = n116 | ~i_4_ | i_8_; + assign n421 = n420 & (n50 | ~n243); + assign n422 = ~n53 & (~n530 | (i_3_ & ~n208)); + assign n423 = i_4_ & n239; + assign n424 = i_6_ & (n418 | (~n62 & n423)); + assign n425 = (n517 | n59) & (i_4_ | n409); + assign n426 = (~i_7_ | n415) & (i_0_ | n412); + assign n427 = (n82 | n271) & (~n338 | n416); + assign n428 = (~i_1_ | ~n361) & (~n423 | n671); + assign n429 = (n157 | n421) & (n400 | ~n670); + assign n430 = ~n422 & (n56 | n120 | ~n475); + assign n431 = n430 & n429 & n428 & n427 & n426 & n425 & n333 & ~n424; + assign n432 = n183 & (~i_4_ | i_10_ | n70); + assign n433 = i_7_ | i_9_ | i_11_; + assign n434 = n191 & (n215 | n433); + assign n435 = ~i_8_ | ~i_9_; + assign n436 = i_5_ & ~n558 & (~n540 | ~n568); + assign n437 = i_10_ & n519; + assign n438 = ~i_4_ & ~n539 & (n437 | ~n568); + assign n439 = ~i_8_ | n214; + assign n440 = i_8_ | n516; + assign n441 = (n366 | n439) & (~n167 | n440); + assign n442 = ~i_12_ & (~n158 | n417 | ~n530); + assign n443 = n435 | ~i_3_ | n112; + assign n444 = ~n442 & n443 & (i_11_ | n115); + assign n445 = ~i_0_ | ~i_2_; + assign n446 = ~i_6_ & i_3_ & i_5_; + assign n447 = n383 & (~n684 | (~i_7_ & n446)); + assign n448 = n406 & (~n685 | (i_7_ & ~n545)); + assign n449 = i_5_ | ~n365; + assign n450 = (~n338 | n449) & (~n101 | ~n348); + assign n451 = i_5_ | n522; + assign n452 = (n80 | n440) & (n81 | n451); + assign n453 = ~i_5_ | ~n519; + assign n454 = (n453 | n81) & (n439 | n80); + assign n455 = n137 & n408; + assign n456 = ~i_0_ | n312; + assign n457 = (n379 | n456) & (n455 | n453); + assign n458 = ~i_5_ & i_0_ & i_3_; + assign n459 = n167 & (~n663 | (~n107 & n458)); + assign n460 = i_4_ & ~i_0_ & ~i_2_; + assign n461 = ~n569 & (~n664 | (n239 & n460)); + assign n462 = ~i_5_ & n519; + assign n463 = i_4_ & ~i_0_ & ~i_1_; + assign n464 = n462 & (~n665 | (n239 & n463)); + assign n465 = ~n570 & (~n666 | (~n71 & n463)); + assign n466 = ~n571 & (~n667 | (~n71 & n460)); + assign n467 = n406 & (n438 | (n259 & ~n545)); + assign n468 = n383 & (n436 | (~n296 & n446)); + assign n469 = (n450 | n56) & (n441 | n60); + assign n470 = ~n464 & (~i_9_ | n158 | n400); + assign n471 = n702 & n701 & (n452 | n50); + assign n472 = n699 & n698 & (n457 | n366); + assign n473 = ~n740 & ~n739 & n709 & n707 & n706 & n705 & n703 & n704; + assign n474 = ~i_5_ | n352; + assign n475 = ~i_3_ & i_8_; + assign n476 = ~n56 & (i_7_ | n475); + assign n477 = (i_1_ | n537) & (n589 | n178); + assign n478 = ~n476 & n715 & (n335 | n474); + assign n479 = n477 & n478 & (i_0_ | ~i_5_); + assign n480 = ~n56 & (~i_7_ | n243); + assign n481 = n300 & (i_1_ | n359); + assign n482 = n746 & (i_5_ | n416); + assign n483 = n187 & (i_3_ | n293); + assign n484 = (n56 | ~n365) & (i_12_ | n479); + assign n485 = (n213 | n298) & (n215 | n574); + assign n486 = n716 & (i_1_ | n359 | n534); + assign n487 = n717 & (i_11_ | (n714 & n711)); + assign n488 = n487 & n486 & n485 & n484 & n483 & n482 & n432 & n434; + assign n489 = ~i_7_ | n366; + assign n490 = ~i_10_ | ~i_12_; + assign n491 = n489 & ~n496 & (i_7_ | n490); + assign n492 = (n747 & (~i_5_ | n748)) | (i_5_ & n748); + assign n493 = n492 & (~i_0_ | n281); + assign n494 = i_8_ | ~i_11_; + assign n495 = ~n496 & n494 & ~i_3_ & n263; + assign n496 = i_8_ & i_12_; + assign n497 = n496 & (~n221 | ~n379); + assign n498 = (n218 | n491) & (~i_1_ | n493); + assign n499 = n726 & (~i_12_ | (n61 & n723)); + assign n500 = n725 & (~i_11_ | (n719 & n722)); + assign n501 = n724 & (n494 | (n227 & n378)); + assign n502 = n501 & n500 & n498 & n499; + assign n503 = i_12_ | ~n475; + assign n504 = ~n46 & n503 & (i_11_ | ~n243); + assign n505 = (~n243 | ~n338) & (n113 | ~n391); + assign n506 = (~n243 | ~n247) & (~n65 | ~n475); + assign n507 = (n504 & (~i_4_ | n505)) | (i_4_ & n505); + assign n508 = n727 & n728 & (~i_13_ | ~n46); + assign n509 = n508 & n506 & n507; + assign n510 = (~i_1_ | n281) & (~i_2_ | n263); + assign n511 = (~i_5_ & ~i_10_) | (~i_9_ & (i_5_ | ~i_10_)); + assign n512 = i_6_ & ~i_12_; + assign n513 = i_9_ & (n392 | (n512 & i_1_)); + assign n514 = i_9_ | i_10_; + assign n515 = i_3_ | i_4_; + assign n516 = i_5_ | i_6_; + assign n517 = i_8_ | ~n419; + assign n518 = ~i_8_ | n55; + assign n519 = i_8_ & i_7_; + assign n520 = ~i_8_ | n304; + assign n521 = i_2_ | ~i_0_ | ~i_1_; + assign n522 = i_8_ | i_7_; + assign n523 = i_11_ | n514; + assign n524 = ~i_5_ | n515; + assign n525 = ~n348 | n523; + assign n526 = ~i_9_ | ~i_10_; + assign n527 = i_7_ | n526; + assign n528 = ~i_3_ | n526; + assign n529 = ~i_7_ | n526; + assign n530 = i_11_ | n262; + assign n531 = ~i_5_ | ~i_3_ | ~i_4_; + assign n532 = ~i_6_ | n332; + assign n533 = ~i_8_ | n332; + assign n534 = i_5_ | i_10_; + assign n535 = i_7_ | n534; + assign n536 = ~i_2_ & n365; + assign n537 = i_9_ | n214; + assign n538 = ~i_5_ | n332; + assign n539 = i_5_ | ~i_6_; + assign n540 = ~i_9_ | n522; + assign n541 = ~n247 | n540; + assign n542 = ~n65 | ~n259; + assign n543 = ~n239 | n449; + assign n544 = ~n247 | n296; + assign n545 = ~i_3_ | n539; + assign n546 = ~i_3_ | n516; + assign n547 = ~i_3_ | n214; + assign n548 = ~i_7_ | n435; + assign n549 = ~n247 | n548; + assign n550 = ~n65 | n266; + assign n551 = ~n247 | n267; + assign n552 = i_13_ | n115; + assign n553 = ~i_11_ | ~n402; + assign n554 = i_13_ | n158; + assign n555 = ~i_9_ | ~n406; + assign n556 = n114 & n528; + assign n557 = ~i_2_ | ~i_3_; + assign n558 = i_4_ | i_6_; + assign n559 = ~i_3_ | i_12_; + assign n560 = i_4_ | n225; + assign n561 = i_1_ | n557; + assign n562 = ~i_1_ | n63; + assign n563 = i_7_ | i_2_; + assign n564 = ~i_11_ | n490; + assign n565 = ~i_9_ | n490; + assign n566 = ~i_9_ | ~n167; + assign n567 = ~i_8_ | n286; + assign n568 = i_0_ | n557; + assign n569 = ~i_8_ | n539; + assign n570 = ~i_5_ | n522; + assign n571 = ~i_5_ | n78; + assign n572 = ~n220 | n288; + assign n573 = n243 & n319; + assign n574 = i_12_ | n272; + assign n575 = (~i_5_ & n419) | (n402 & (i_5_ | n419)); + assign n576 = (~i_4_ & n729) | (n89 & (i_4_ | n729)); + assign n577 = (~i_6_ & n564) | (n363 & (i_6_ | n564)); + assign n578 = (i_6_ & ~n178) | (~n177 & (~i_6_ | ~n178)); + assign n579 = i_10_ | i_13_ | ~n383 | n520; + assign n580 = n579 & (n233 | ~n245); + assign n581 = i_9_ | i_13_ | n99 | ~n406; + assign n582 = n581 & (n97 | ~n241); + assign n583 = n527 | ~i_3_ | n228; + assign n584 = n583 & (i_8_ | n227 | n526); + assign n585 = (n213 | n517) & (n210 | ~n361); + assign n586 = ~n222 & n585 & (n208 | n215); + assign n587 = n547 & n408 & n44 & n203; + assign n588 = (n587 | n529) & (i_0_ | n209); + assign n589 = n196 & n200 & n197; + assign n590 = (n530 | n589) & (n202 | ~n417); + assign n591 = n355 & n354; + assign n592 = (n273 | n200) & (n62 | n532); + assign n593 = n541 | n194; + assign n594 = n113 | n153 | n158; + assign n595 = ~n402 | n107 | n158; + assign n596 = ~n446 | n550; + assign n597 = ~n446 | n549; + assign n598 = n113 | n131 | n158; + assign n599 = (~n259 | n547) & (n194 | ~n519); + assign n600 = n528 & (n546 | n266); + assign n601 = n531 | ~n67 | n113; + assign n602 = n601 & (n117 | n107); + assign n603 = (n99 | n135) & (n198 | n151); + assign n604 = n602 & n603 & (n194 | n551); + assign n605 = (n108 | n119) & (n111 | n524); + assign n606 = ~n118 & n605 & (i_4_ | n556); + assign n607 = (n518 | n57) & (n53 | n520); + assign n608 = (n95 | n449) & (n92 | ~n164); + assign n609 = ~n104 & n608 & (n100 | n531); + assign n610 = (n537 | n235) & (n474 | n234); + assign n611 = (n273 | n408) & (n538 | n59); + assign n612 = n64 | ~i_6_ | i_11_; + assign n613 = n612 & (~i_10_ | n61); + assign n614 = i_10_ | ~n103 | ~n319 | n520; + assign n615 = n614 & (n58 | n162); + assign n616 = i_10_ | n157 | ~n319 | n518; + assign n617 = n616 & (n47 | n57 | n120); + assign n618 = n617 & (n520 | n521 | n50); + assign n619 = (n54 | ~n67) & (n51 | ~n102); + assign n620 = n161 | n534 | ~n102 | n120; + assign n621 = n620 & (i_4_ | n59 | ~n575); + assign n622 = ~n68 & (n115 | (n618 & n619)); + assign n623 = (i_2_ | n354) & (i_10_ | n335); + assign n624 = i_11_ | n266 | n59 | n558; + assign n625 = n624 & (i_9_ | n236 | n77); + assign n626 = n355 | ~i_2_ | n71; + assign n627 = n626 & (n220 | n71 | n178); + assign n628 = n332 | i_10_ | ~n250; + assign n629 = n628 & (~n166 | n231 | n330); + assign n630 = n629 & (~i_13_ | n378 | n517); + assign n631 = n531 | n193 | ~n239; + assign n632 = ~n251 & n631 & (~n103 | n176); + assign n633 = (n156 | n521) & (n173 | n157); + assign n634 = n633 & (n152 | n53); + assign n635 = (n136 | n49) & (n147 | n57); + assign n636 = n635 & n634 & (n130 | n56); + assign n637 = ~n252 & (n400 | (n604 & n606)); + assign n638 = n730 & (~i_7_ | n269); + assign n639 = ~n435 | ~i_4_ | n77; + assign n640 = n639 & (i_8_ | i_13_ | n235); + assign n641 = (i_11_ | n161) & (~n338 | ~n536); + assign n642 = n235 | ~i_8_ | i_13_; + assign n643 = n642 & (~n348 | (n533 & ~n536)); + assign n644 = n312 | ~i_2_ | n263; + assign n645 = ~n732 & (i_7_ | (n640 & n641)); + assign n646 = ~n563 | ~n361 | ~n496; + assign n647 = n646 & (n359 | n561); + assign n648 = (n288 | n354) & (~n166 | n355); + assign n649 = ~i_8_ | i_3_ | i_6_ | n749 | i_10_ | ~n166; + assign n650 = n649 & (~n348 | n353); + assign n651 = i_10_ | i_13_ | n749 | n494; + assign n652 = n651 & (n116 | n562); + assign n653 = i_10_ | i_8_; + assign n654 = (n286 | ~n340) & (n186 | n653); + assign n655 = n335 | i_8_ | ~n319; + assign n656 = n365 | n548 | ~i_6_ | ~i_12_; + assign n657 = ~i_3_ | ~i_9_ | ~n383 | n518; + assign n658 = n657 & (n281 | ~n496 | n560); + assign n659 = (n358 | n98) & (n346 | n303); + assign n660 = (n345 & (~i_6_ | n351)) | (i_6_ & n351); + assign n661 = (~i_1_ & n329) | (n311 & (i_1_ | n329)); + assign n662 = n660 & n661 & (~i_12_ | n357); + assign n663 = (n378 | n456) & (n455 | n451); + assign n664 = (n555 | n568) & (n62 | ~n245); + assign n665 = (n388 | n555) & (n200 | ~n245); + assign n666 = (n388 | n553) & (n200 | ~n241); + assign n667 = (n553 | n568) & (n62 | ~n241); + assign n668 = (n288 | n535) & (~n166 | n190); + assign n669 = (n116 | n449) & (~n101 | n113); + assign n670 = i_10_ & (~i_7_ | (i_3_ & ~i_8_)); + assign n671 = ~i_8_ | n56; + assign n672 = n741 & (~i_2_ | n303 | ~n406); + assign n673 = (i_3_ & n555) | (~n245 & (~i_3_ | n555)); + assign n674 = (~i_7_ | n388) & (i_0_ | ~n67); + assign n675 = ~n383 | i_8_ | n53; + assign n676 = n675 & (n401 | n366); + assign n677 = n157 | ~i_8_ | n113; + assign n678 = n677 & (~n348 | n399); + assign n679 = n346 | i_6_ | n398; + assign n680 = n679 & (n390 | n364); + assign n681 = (~n243 | n525) & (n157 | n269); + assign n682 = n680 & n681 & (n56 | ~n573); + assign n683 = (i_7_ | n389) & (i_0_ | n397); + assign n684 = (~i_2_ | n571) & (~i_1_ | n570); + assign n685 = (~i_2_ | n569) & (~i_1_ | ~n462); + assign n686 = (n364 | n439) & (n105 | n537); + assign n687 = n288 | i_2_ | n106; + assign n688 = (n451 | n270) & (n364 | n453); + assign n689 = n211 | i_10_ | n105; + assign n690 = n689 & (~i_9_ | n536 | n564); + assign n691 = ~n381 & n690 & (~n365 | n380); + assign n692 = i_3_ | i_13_ | n293; + assign n693 = n735 & (~i_6_ | ~i_12_ | n529); + assign n694 = n285 & n692 & (~i_3_ | n693); + assign n695 = (~i_5_ & n377) | (n373 & (i_5_ | n377)); + assign n696 = n695 & ~n738 & (~i_1_ | n526); + assign n697 = n564 | i_8_ | ~n458; + assign n698 = n697 & (n213 | n256 | n336); + assign n699 = n400 | ~i_10_ | n115; + assign n700 = n567 | n199 | n120; + assign n701 = n700 & (n454 | n109); + assign n702 = ~n319 | n196 | n290; + assign n703 = ~n466 & (n157 | (n668 & n669)); + assign n704 = (n444 | n53) & (n217 | n565); + assign n705 = ~n467 & ~n468 & (n138 | n441); + assign n706 = (~n348 | n434) & (~n250 | n432); + assign n707 = (n538 | n71) & (n566 | n224); + assign n708 = n445 | i_5_ | n512 | n404; + assign n709 = n708 & ~n745 & (i_5_ | n431); + assign n710 = (n589 | n290) & (n202 | n177); + assign n711 = ~n480 & n710 & (n62 | n354); + assign n712 = (n185 | n335) & (n210 | n354); + assign n713 = ~n220 | ~i_5_ | i_9_; + assign n714 = n713 & n712 & (i_0_ | i_5_); + assign n715 = (n202 | n567) & (n64 | n355); + assign n716 = i_10_ | n332; + assign n717 = (i_2_ | n283) & (i_0_ | n481); + assign n718 = i_6_ | n60; + assign n719 = ~i_12_ & n718 & (i_5_ | n59); + assign n720 = n228 | ~i_3_ | i_7_; + assign n721 = n720 & (i_7_ | n408); + assign n722 = n721 & (n546 | (~i_2_ & i_7_)); + assign n723 = (~i_7_ | n587) & (~i_2_ | n547); + assign n724 = ~n497 & (n226 | (n398 & n404)); + assign n725 = ~i_0_ | n511; + assign n726 = n495 | n400; + assign n727 = ~n435 | ~i_3_ | n270; + assign n728 = ~n365 | ~i_8_ | ~n348; + assign n729 = ~i_5_ | n59 | ~n512 | n548; + assign n730 = ~n243 | i_7_ | n50; + assign n731 = i_7_ & (n573 | n65); + assign n732 = i_7_ & (~n643 | (~i_12_ & ~n161)); + assign n733 = i_12_ | n514; + assign n734 = n560 | i_8_ | ~n167; + assign n735 = n527 | i_6_ | ~i_11_; + assign n736 = ~i_10_ & (~n572 | (n73 & n166)); + assign n737 = i_2_ & i_12_ & (~n303 | ~n398); + assign n738 = ~i_1_ & (~n688 | (n166 & ~n537)); + assign n739 = ~i_0_ & ~i_4_ & (n447 | n448); + assign n740 = i_0_ & (~n691 | ~n694 | ~n696); + assign n741 = i_2_ | n98 | n120; + assign n742 = i_4_ & (~n678 | (~n70 & ~n71)); + assign n743 = ~i_4_ & (~n676 | (~n408 & ~n489)); + assign n744 = ~n682 | n403 | n513 | n743 | ~n683 | n742; + assign n745 = i_5_ & n744; + assign n746 = n399 | ~i_4_ | ~i_5_; + assign n747 = (i_6_ & n362) | (~n167 & (~i_6_ | n362)); + assign n748 = (~i_6_ & n490) | (n366 & (i_6_ | n490)); + assign n749 = i_2_ & i_7_; + assign n750 = n417 & n533 & i_3_; + assign n751 = i_6_ & n574 & n433; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/apex2/apex2.v b/openfpga_flow/benchmarks/MCNC_Verilog/apex2/apex2.v new file mode 100644 index 000000000..357e6f846 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/apex2/apex2.v @@ -0,0 +1,1036 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 09:54:52 2019 + +module apex2 ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, + i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, i_20_, + i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, + i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, + o_0_, o_1_, o_2_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, + i_10_, i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, + i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, + i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_; + output o_0_, o_1_, o_2_; + wire n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, + n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, + n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, + n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, + n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, + n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, + n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, + n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, + n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, + n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, + n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, + n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, + n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, + n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, + n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, + n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, + n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, + n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, + n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, + n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, + n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, + n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, + n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, + n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, + n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, + n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, + n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, + n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, + n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, + n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, + n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, + n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, + n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, + n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, + n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, + n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, + n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, + n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, + n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, + n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, + n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, + n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, + n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, + n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, + n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, + n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, + n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, + n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, + n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, + n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, + n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, + n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, + n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, + n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, + n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, + n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, + n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, + n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, + n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, + n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, + n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, + n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, + n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, + n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, + n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, + n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, + n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, + n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, + n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, + n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, + n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, + n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, + n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, + n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, + n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, + n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, + n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, + n977, n978, n979, n980, n981, n982, n983; + assign o_0_ = ~n965 | ~n966 | n49 | ~n964 | n47 | n48 | n45 | n46; + assign o_1_ = ~n603; + assign o_2_ = ~n350; + assign n45 = ~n798 & n686 & n229 & ~n379; + assign n46 = ~n684 & n528 & i_35_ & n526; + assign n47 = ~n693 & ~n805 & (~i_13_ | ~i_14_); + assign n48 = ~n524 & (~n939 | (~n205 & ~n473)); + assign n49 = n804 | ~n968 | n734 | n736 | n732 | n733 | ~n208 | n731; + assign n50 = ~i_27_ & ~n161; + assign n51 = ~i_30_ & n300; + assign n52 = i_36_ & (~n938 | (n50 & n51)); + assign n53 = ~i_12_ & ~i_13_; + assign n54 = ~i_7_ & (n53 | ~n803); + assign n55 = ~i_11_ & ~i_19_; + assign n56 = ~i_24_ & (~n80 | (n55 & ~n81)); + assign n57 = i_19_ & ~i_13_ & i_18_; + assign n58 = ~i_13_ & i_18_; + assign n59 = ~i_22_ & (n57 | (i_11_ & n58)); + assign n60 = ~i_24_ & (~n86 | (n55 & ~n87)); + assign n61 = i_17_ & i_12_; + assign n62 = i_14_ & i_13_; + assign n63 = i_22_ & (n61 | n62); + assign n64 = ~i_10_ & ~i_24_; + assign n65 = ~n90 & (n64 | (i_13_ & ~i_24_)); + assign n66 = ~i_24_ & (n61 | n62); + assign n67 = n610 | i_1_ | n746; + assign n68 = ~i_18_ | ~n237; + assign n69 = i_6_ | n113; + assign n70 = (n68 | n69) & (n67 | ~n237); + assign n71 = i_11_ & ~i_13_; + assign n72 = n71 & (~n773 | (i_18_ & ~n149)); + assign n73 = i_9_ & n71; + assign n74 = n73 & (~n67 | (i_18_ & ~n69)); + assign n75 = ~n635 | ~n280 | ~n324; + assign n76 = ~n324 | n747; + assign n77 = n75 & (n76 | ~n128); + assign n78 = ~n280 | n106 | n140; + assign n79 = n78 & (~n128 | ~n259 | ~n328); + assign n80 = n764 | i_9_ | i_18_; + assign n81 = n313 | n100; + assign n82 = n80 & (~n55 | n81); + assign n83 = n113 | i_6_ | n744; + assign n84 = n316 | n745; + assign n85 = n83 & (~i_9_ | n84); + assign n86 = i_18_ | n759; + assign n87 = n313 | n98; + assign n88 = n86 & (~n55 | n87); + assign n89 = i_10_ & ~i_13_; + assign n90 = i_9_ | n760; + assign n91 = (i_32_ | n88) & (n89 | n90); + assign n92 = n754 | ~i_9_ | n745; + assign n93 = ~i_11_ | i_12_; + assign n94 = ~i_11_ | n744; + assign n95 = (n67 | n94) & (n92 | n93); + assign n96 = (~n73 | n84) & (~n71 | n83); + assign n97 = (~i_18_ | n96) & (i_13_ | n95); + assign n98 = i_7_ | n763; + assign n99 = i_32_ | ~i_38_; + assign n100 = i_8_ | n763; + assign n101 = (n98 | n99) & (n100 | ~n262); + assign n102 = ~n278 | n98 | n107; + assign n103 = ~n328 | n100 | n116; + assign n104 = i_25_ | n743; + assign n105 = n102 & n103 & (n101 | n104); + assign n106 = i_32_ | ~n324; + assign n107 = i_32_ | n743; + assign n108 = (n104 | n106) & (n107 | ~n328); + assign n109 = n757 | n419; + assign n110 = n313 | n765; + assign n111 = (i_19_ | n110) & (i_18_ | n109); + assign n112 = n316 | n468; + assign n113 = i_12_ | n313; + assign n114 = i_6_ | ~n214; + assign n115 = (n113 | n114) & (i_8_ | n112); + assign n116 = i_31_ | n743; + assign n117 = i_35_ | n749; + assign n118 = n117 | n116 | n111; + assign n119 = ~n262 | i_32_ | n111; + assign n120 = n119 & (i_2_ | ~n259 | ~n324); + assign n121 = ~n104 | ~n971; + assign n122 = i_38_ & (~n118 | (~n115 & n121)); + assign n123 = n867 & (~n635 | n774); + assign n124 = (~i_38_ | n91) & (n82 | ~n262); + assign n125 = n866 & (i_10_ | n85 | ~n324); + assign n126 = n123 & (i_28_ | (n124 & n125)); + assign n127 = ~i_24_ & (~n869 | ~n871 | ~n873); + assign n128 = ~i_28_ & ~n161; + assign n129 = n128 & (~n876 | ~n878 | ~n880); + assign n130 = ~n271 | i_30_ | n160; + assign n131 = (n190 | ~n269) & (n104 | n768); + assign n132 = ~i_38_ | n762; + assign n133 = n130 & n131 & (~n51 | n132); + assign n134 = i_28_ | n175; + assign n135 = i_22_ | ~n257; + assign n136 = n143 | ~n324; + assign n137 = (n135 | n136) & (n134 | ~n269); + assign n138 = n135 | n143; + assign n139 = n175 | ~n328; + assign n140 = i_28_ | i_31_ | i_30_; + assign n141 = (n139 | n140) & (n138 | ~n262); + assign n142 = n104 | i_30_ | ~i_38_; + assign n143 = i_30_ | n743; + assign n144 = n142 & (n143 | ~n278); + assign n145 = (~n64 | n83) & (n84 | ~n272); + assign n146 = ~i_18_ | ~n257; + assign n147 = i_13_ | ~n257; + assign n148 = (n95 | n147) & (n96 | n146); + assign n149 = n742 | n316; + assign n150 = i_10_ | i_6_ | ~i_9_; + assign n151 = (n113 | n150) & (i_10_ | n149); + assign n152 = ~n262 | i_8_ | i_30_; + assign n153 = n119 & (n89 | n101 | n313); + assign n154 = n152 & n153 & (n151 | n106); + assign n155 = ~n65 & (i_32_ | ~n60); + assign n156 = n155 & (i_30_ | ~n336); + assign n157 = (n156 | ~n278) & (~n56 | n282); + assign n158 = n865 & (n76 | ~n272); + assign n159 = n157 & n158 & (n154 | ~n257); + assign n160 = ~i_34_ | ~n324; + assign n161 = i_24_ | i_26_; + assign n162 = (n161 | ~n328) & (n160 | ~n257); + assign n163 = n98 | n161 | ~n278 | ~n310; + assign n164 = n162 | n167; + assign n165 = i_31_ | i_33_ | n160 | ~n267; + assign n166 = n163 & (n100 | (n164 & n165)); + assign n167 = i_31_ | ~n300; + assign n168 = (n116 | n135) & (n167 | ~n280); + assign n169 = (n160 | ~n265) & (~n128 | ~n328); + assign n170 = n750 | n160 | ~n267; + assign n171 = (i_31_ | n199) & (n168 | n106); + assign n172 = i_29_ | n541; + assign n173 = n170 & n171 & (n169 | n172); + assign n174 = n135 | n143 | i_32_ | ~i_38_; + assign n175 = i_22_ | n161; + assign n176 = n174 & (n175 | ~n278 | ~n635); + assign n177 = n176 | n761; + assign n178 = i_3_ | i_8_ | ~i_10_ | n141; + assign n179 = i_3_ | n744; + assign n180 = n177 & n178 & (n137 | n179); + assign n181 = (i_29_ | ~n128) & (i_28_ | n175); + assign n182 = i_2_ | n744; + assign n183 = i_24_ | ~i_12_ | i_22_; + assign n184 = i_10_ | n744; + assign n185 = (n183 | n184) & (n182 | ~n342); + assign n186 = i_26_ | ~i_38_ | ~n51 | n117; + assign n187 = i_29_ | ~n219; + assign n188 = n186 & (i_28_ | n187 | n132); + assign n189 = ~n654 | ~i_38_ | ~n51; + assign n190 = i_26_ | ~n300; + assign n191 = i_30_ | n106; + assign n192 = n189 & (n190 | n191); + assign n193 = ~i_19_ | i_24_; + assign n194 = ~i_19_ | ~n257; + assign n195 = (n192 | n194) & (n188 | n193); + assign n196 = (n107 | n135) & (~n265 | n509); + assign n197 = (~n128 | n224) & (~n267 | n318); + assign n198 = n196 & n197 & (~n280 | ~n310); + assign n199 = n139 | i_32_ | i_28_; + assign n200 = n199 & (n198 | ~n324); + assign n201 = ~i_31_ | ~n235; + assign n202 = n201 & (~n235 | (~i_30_ & ~i_32_)); + assign n203 = i_23_ | ~n739; + assign n204 = i_27_ | n740; + assign n205 = ~i_14_ | n580; + assign n206 = (n204 | n205) & (n203 | ~n307); + assign n207 = n684 | n738 | ~i_20_ | ~n537; + assign n208 = n207 & (n206 | ~n235 | ~n531); + assign n209 = i_22_ | ~n237; + assign n210 = ~n59 & (i_3_ | n209); + assign n211 = (i_8_ | n141) & (i_7_ | n176); + assign n212 = (n79 | n210) & (n211 | n68); + assign n213 = ~i_22_ & ~n193; + assign n214 = ~i_7_ & ~i_8_; + assign n215 = n214 & ~n144 & n213; + assign n216 = i_12_ & n58; + assign n217 = n216 & (n215 | (i_11_ & ~n211)); + assign n218 = ~i_34_ | n769; + assign n219 = ~i_30_ & ~i_32_; + assign n220 = n218 & (i_28_ | ~i_34_ | n219); + assign n221 = (~i_22_ | n220) & (n219 | ~n303); + assign n222 = i_29_ | n572; + assign n223 = n221 & (i_28_ | n222); + assign n224 = i_29_ | n749; + assign n225 = (i_28_ | n224) & (i_25_ | ~n310); + assign n226 = i_31_ | n752; + assign n227 = (i_8_ | n226) & (n111 | n172); + assign n228 = i_33_ & n235; + assign n229 = i_33_ & i_34_; + assign n230 = i_14_ & (n228 | (~i_24_ & n229)); + assign n231 = n785 & n112; + assign n232 = i_2_ | ~n214; + assign n233 = (i_30_ | n232) & (i_32_ | n231); + assign n234 = i_22_ & (n230 | (~n202 & n203)); + assign n235 = ~i_34_ & i_35_; + assign n236 = ~n259 & (~n853 | (n63 & n235)); + assign n237 = ~i_13_ & i_19_; + assign n238 = ~n179 & (n71 | n237); + assign n239 = ~i_24_ & (n238 | (n58 & ~n94)); + assign n240 = i_13_ | n744; + assign n241 = ~n239 & (~i_18_ | n193 | n240); + assign n242 = n68 & (~i_18_ | ~n71); + assign n243 = (n94 | ~n216) & (n182 | n242); + assign n244 = ~i_12_ | n744; + assign n245 = n243 & (n68 | n244); + assign n246 = i_12_ & n71; + assign n247 = n246 & i_18_ & ~i_22_; + assign n248 = ~n761 & n213 & ~i_13_ & ~i_8_ & i_12_; + assign n249 = (n106 | n138) & (n139 | ~n635); + assign n250 = (n77 | n210) & (i_7_ | n176); + assign n251 = ~i_10_ & ~n249 & (~i_2_ | i_12_); + assign n252 = ~i_3_ & i_11_; + assign n253 = ~i_22_ & i_12_ & ~i_13_; + assign n254 = n252 & (~n847 | (~n77 & n253)); + assign n255 = (~n55 | n90) & (i_8_ | n86); + assign n256 = ~n225 & ~n89 & ~i_24_ & ~n87; + assign n257 = ~i_24_ & ~i_25_; + assign n258 = n257 & n51 & ~i_7_ & ~i_32_; + assign n259 = ~i_31_ & n219; + assign n260 = (~i_22_ | ~i_23_) & (~n63 | n259); + assign n261 = (~i_38_ | n155) & (~n56 | ~n262); + assign n262 = ~i_31_ & n324; + assign n263 = ~n823 & ~i_29_ & n262; + assign n264 = i_8_ | ~n51 | ~n257 | ~n262; + assign n265 = ~i_28_ & n257; + assign n266 = n265 & (n263 | (~n184 & ~n768)); + assign n267 = ~i_24_ & n300; + assign n268 = ~n823 & ~i_31_ & n328; + assign n269 = ~i_30_ & n328; + assign n270 = n267 & (n268 | (~n184 & n269)); + assign n271 = ~i_25_ & n300; + assign n272 = n64 & i_9_; + assign n273 = n271 & (~n261 | (~n191 & n272)); + assign n274 = i_29_ | n769; + assign n275 = ~n66 | n274; + assign n276 = i_38_ & (n256 | n258 | ~n842); + assign n277 = (n104 | n261) & (n142 | ~n336); + assign n278 = ~i_33_ & i_38_; + assign n279 = n278 & ~i_7_ & ~n161; + assign n280 = ~i_25_ & ~n161; + assign n281 = ~i_32_ & (n279 | (n262 & n280)); + assign n282 = i_33_ | ~n262; + assign n283 = ~n281 & (i_8_ | n161 | n282); + assign n284 = ~i_25_ & (~n770 | (n51 & n214)); + assign n285 = ~n89 & (~n90 | (~i_32_ & ~n87)); + assign n286 = n829 & (~n310 | (~n280 & ~n299)); + assign n287 = n830 & (~n267 | n318); + assign n288 = i_32_ | ~n235; + assign n289 = n286 & n287 & (~n271 | n288); + assign n290 = ~n190 & (~n115 | (~i_7_ & n219)); + assign n291 = n565 | n87 | ~n300; + assign n292 = i_29_ | i_34_ | i_33_; + assign n293 = n291 & (i_28_ | n90 | n292); + assign n294 = (n117 | ~n128) & (~n265 | ~n654); + assign n295 = i_33_ | n755; + assign n296 = i_24_ | i_28_; + assign n297 = i_33_ | ~n300; + assign n298 = (n161 | n297) & (n295 | n296); + assign n299 = ~i_33_ & n235; + assign n300 = ~i_28_ & ~i_29_; + assign n301 = ~n115 & (~n298 | (n299 & n300)); + assign n302 = ~n255 & (~n827 | (n280 & n300)); + assign n303 = n300 & i_34_; + assign n304 = n257 & (~n828 | (~n115 & n303)); + assign n305 = n235 & (n284 | ~n832 | ~n834); + assign n306 = ~i_27_ & n300; + assign n307 = n53 & i_14_; + assign n308 = ~i_16_ & n655; + assign n309 = n308 & n306 & n307; + assign n310 = ~i_32_ & n300; + assign n311 = n310 & ~n151 & ~n161; + assign n312 = (~n56 | n167) & (~n259 | ~n267); + assign n313 = i_5_ | n741; + assign n314 = i_12_ | i_6_; + assign n315 = i_5_ | i_6_; + assign n316 = i_1_ | n741; + assign n317 = (n315 | n316) & (n313 | n314); + assign n318 = ~i_34_ | n749; + assign n319 = (~n272 | n318) & (n184 | ~n280); + assign n320 = (i_29_ | n145) & (n187 | ~n272); + assign n321 = ~i_24_ & ~n317 & (~n814 | ~n815); + assign n322 = n213 & (~n104 | ~n971); + assign n323 = (~n816 | ~n817) & (~n819 | ~n820); + assign n324 = ~i_35_ & i_38_; + assign n325 = n324 & (~n821 | ~n822 | ~n825); + assign n326 = ~n181 & (n268 | (~n255 & n278)); + assign n327 = ~n180 & (n246 | (i_12_ & n237)); + assign n328 = ~i_33_ & n324; + assign n329 = n328 & (n311 | (~n143 & ~n185)); + assign n330 = n306 & ~n473; + assign n331 = n229 & (n309 | (~n205 & n330)); + assign n332 = n228 & n300 & n259; + assign n333 = i_14_ & (n332 | (n128 & i_33_)); + assign n334 = i_9_ & (~n848 | ~n850 | ~n852); + assign n335 = i_10_ & (n247 | (n252 & n253)); + assign n336 = ~i_24_ & n214; + assign n337 = ~n144 & (n248 | (n335 & n336)); + assign n338 = ~i_28_ & (n234 | n236 | ~n975); + assign n339 = i_10_ & (~n857 | (i_12_ & ~n212)); + assign n340 = n73 & (~n859 | (~n137 & ~n771)); + assign n341 = n203 & (~n860 | (n128 & ~n219)); + assign n342 = ~i_22_ & n64; + assign n343 = ~n313 & (~n864 | (~n105 & n342)); + assign n344 = ~n325 & (~i_27_ | n175 | ~n421); + assign n345 = n887 & (n77 | n209 | n748); + assign n346 = n886 & (~n66 | n219 | ~n303); + assign n347 = ~n333 & n890 & (~n51 | n283); + assign n348 = ~n329 & n888 & (n132 | n312); + assign n349 = n897 & n896 & n895 & n893 & n892 & n891 & ~n339 & ~n340; + assign n350 = n349 & n348 & n347 & n346 & n345 & n344 & ~n326 & ~n327; + assign n351 = ~i_34_ | ~i_37_; + assign n352 = i_29_ | n510; + assign n353 = ~i_37_ | ~n235; + assign n354 = (n351 | n352) & (~n306 | n353); + assign n355 = n523 | i_29_ | ~n427; + assign n356 = ~i_34_ | ~n427; + assign n357 = n355 & (~n306 | n356); + assign n358 = ~n654 | ~i_37_ | ~n306; + assign n359 = n358 & (i_32_ | n355); + assign n360 = n793 | n313 | n361; + assign n361 = i_17_ | n581; + assign n362 = i_10_ | n763; + assign n363 = n360 & (n313 | n361 | n362); + assign n364 = n413 | n397 | n788 | n362; + assign n365 = n488 | ~i_37_ | n468; + assign n366 = n863 | ~n427 | n788; + assign n367 = n364 & (n361 | (n365 & n366)); + assign n368 = n788 | ~n391 | n766; + assign n369 = n778 | i_7_ | i_0_; + assign n370 = n368 & (i_12_ | n369); + assign n371 = ~i_23_ & ~n161; + assign n372 = n371 & (~n921 | (~n370 & ~n493)); + assign n373 = n463 | n500 | n782; + assign n374 = i_11_ | n581; + assign n375 = n590 | n98 | n788; + assign n376 = ~n372 & n373 & (n374 | n375); + assign n377 = i_14_ | ~n427; + assign n378 = (~i_21_ | ~n546) & (~n51 | n377); + assign n379 = n737 & n361; + assign n380 = n379 & (i_33_ | ~n544); + assign n381 = n87 | n604; + assign n382 = i_10_ | n581; + assign n383 = n381 & (n87 | n382); + assign n384 = n380 | n450 | ~i_31_ | ~n51; + assign n385 = n384 & (~n330 | n383); + assign n386 = n523 | n800 | ~i_29_ | n367; + assign n387 = n796 | i_29_ | n690 | n444; + assign n388 = (~i_37_ | n376) & (n351 | n385); + assign n389 = n923 & (i_31_ | n378 | n540); + assign n390 = n389 & n388 & n386 & n387; + assign n391 = ~i_27_ & n421; + assign n392 = n655 & i_22_; + assign n393 = n391 & n392 & (~n379 | ~n784); + assign n394 = ~i_33_ | n541; + assign n395 = ~i_25_ | ~n655; + assign n396 = ~n393 & (~n51 | n394 | n395); + assign n397 = i_33_ | ~n427; + assign n398 = n377 & (i_13_ | n397); + assign n399 = n382 & n604; + assign n400 = i_10_ | n580; + assign n401 = (n397 | n400) & (n399 | ~n427); + assign n402 = ~n365 & (~n485 | (~i_33_ & ~n474)); + assign n403 = i_20_ | ~n776; + assign n404 = i_20_ | n740; + assign n405 = (i_16_ | n404) & (i_12_ | n403); + assign n406 = n900 & (n764 | n500 | n786); + assign n407 = i_19_ | n740; + assign n408 = n406 & (n81 | n407 | n374); + assign n409 = n786 | n764 | n501; + assign n410 = i_11_ | n580; + assign n411 = n409 & (n81 | n407 | n410); + assign n412 = n399 & (i_33_ | n400); + assign n413 = i_17_ | n580; + assign n414 = (n397 | n413) & (n361 | ~n427); + assign n415 = n918 & (i_19_ | n765 | n417); + assign n416 = n415 & (n398 | n314 | n403); + assign n417 = n414 | i_23_ | i_20_; + assign n418 = ~i_3_ | n780; + assign n419 = i_9_ | n315; + assign n420 = n419 | i_18_ | n417 | n418; + assign n421 = ~i_28_ & i_29_; + assign n422 = ~n404 & n421 & (n402 | ~n917); + assign n423 = n438 | i_13_ | n787; + assign n424 = n423 | ~n310 | n397; + assign n425 = ~i_32_ & n421; + assign n426 = n425 & (~n420 | (~n416 & ~n788)); + assign n427 = ~i_35_ & i_37_; + assign n428 = n427 & (~n919 | (n310 & ~n556)); + assign n429 = n898 & (n758 | n501 | n786); + assign n430 = n429 & (n87 | n407 | n410); + assign n431 = i_18_ | ~n655; + assign n432 = i_19_ | ~n655; + assign n433 = (n110 | n432) & (n109 | n431); + assign n434 = ~i_37_ | n749; + assign n435 = i_30_ | ~i_31_ | n434 | ~n544; + assign n436 = n362 | n313 | n413; + assign n437 = n436 | ~i_37_ | n117; + assign n438 = i_16_ | n740; + assign n439 = i_13_ | ~n214; + assign n440 = i_23_ | n580; + assign n441 = i_12_ | ~n214; + assign n442 = (n440 | n441) & (n438 | n439); + assign n443 = n397 | n472 | ~i_34_ | ~n308; + assign n444 = i_34_ | n566; + assign n445 = n443 & (i_33_ | n442 | n444); + assign n446 = n371 & (~n435 | ~n437 | ~n913); + assign n447 = n915 & (n430 | n565 | n566); + assign n448 = ~n446 & n447 & (i_30_ | n445); + assign n449 = ~n659 | n690; + assign n450 = i_27_ | ~n655; + assign n451 = n449 & (~n303 | n450); + assign n452 = n462 | i_8_ | n759; + assign n453 = i_11_ | n783; + assign n454 = n452 & (n90 | n453); + assign n455 = i_7_ | i_28_ | n226 | n288; + assign n456 = n495 | i_9_ | n89 | ~n537 | n789; + assign n457 = n455 & n456 & (n451 | n454); + assign n458 = (i_10_ | n90) & (i_30_ | ~n214); + assign n459 = n438 | n354 | n458; + assign n460 = n912 & (~n427 | n751 | n767); + assign n461 = n459 & n460 & (~i_37_ | n457); + assign n462 = i_18_ | n779; + assign n463 = n468 | n418; + assign n464 = n463 | n462 | i_8_; + assign n465 = ~i_9_ & (~n464 | (~n453 & ~n789)); + assign n466 = n465 & (~i_14_ | (~i_13_ & ~i_33_)); + assign n467 = ~n789 & (~n737 | (~i_33_ & ~n784)); + assign n468 = i_7_ | n315; + assign n469 = n434 | n413 | n468; + assign n470 = ~n488 & (~n469 | (~n414 & ~n745)); + assign n471 = ~n470 & (~i_37_ | (~n466 & ~n467)); + assign n472 = i_8_ | ~n53; + assign n473 = i_17_ | ~n655; + assign n474 = i_8_ | n580; + assign n475 = (n473 | n474) & (~n308 | n472); + assign n476 = i_33_ | n752; + assign n477 = n623 & n972; + assign n478 = (n477 | n224) & (n475 | n476); + assign n479 = ~n543 | n737; + assign n480 = n969 & (~i_29_ | n471 | n800); + assign n481 = n479 & n480 & (~n427 | n478); + assign n482 = n394 | n799 | ~i_25_ | i_28_; + assign n483 = n482 & (~n330 | n397 | n474); + assign n484 = i_8_ | n803; + assign n485 = i_8_ | n581; + assign n486 = (~n308 | n484) & (n473 | n485); + assign n487 = i_33_ | i_9_ | i_10_ | n789; + assign n488 = i_1_ | n780; + assign n489 = n487 & (n315 | n117 | n488); + assign n490 = n434 | n369 | ~n371; + assign n491 = n490 & (~i_37_ | n489 | ~n537); + assign n492 = i_20_ | n580; + assign n493 = i_20_ | n581; + assign n494 = (~n427 | n493) & (n397 | n492); + assign n495 = i_20_ | n779; + assign n496 = (n398 | n495) & (i_12_ | n494); + assign n497 = n299 & ~i_7_ & i_37_; + assign n498 = n300 & (n497 | (i_25_ & n228)); + assign n499 = ~n498 & (~n235 | ~n421 | ~n738); + assign n500 = i_9_ | n581; + assign n501 = i_9_ | n580; + assign n502 = (n397 | n501) & (~n427 | n500); + assign n503 = (n356 | n423) & (n430 | n351); + assign n504 = n760 | n784; + assign n505 = n783 | i_11_ | n90; + assign n506 = n504 & (i_13_ | (n505 & n452)); + assign n507 = n84 | n413; + assign n508 = (n356 | n507) & (n506 | n351); + assign n509 = i_32_ | n755; + assign n510 = i_24_ | n777; + assign n511 = (n509 | n510) & (n288 | ~n306); + assign n512 = n907 & (n758 | n500 | n786); + assign n513 = n512 & (n87 | n407 | n374); + assign n514 = ~n310 | n450; + assign n515 = n81 | n400; + assign n516 = (n436 | n514) & (~n330 | n515); + assign n517 = n204 | ~n310; + assign n518 = (n318 | ~n330) & (~n299 | n517); + assign n519 = (n511 | n513) & (n516 | n762); + assign n520 = n908 & n909 & (n518 | n802); + assign n521 = n760 | n737; + assign n522 = n519 & n520 & (n451 | n521); + assign n523 = i_26_ | n777; + assign n524 = (~n229 | ~n306) & (~i_33_ | n523); + assign n525 = ~n664 & i_25_ & i_20_ & ~i_23_; + assign n526 = ~i_34_ & n421; + assign n527 = ~i_27_ & n697; + assign n528 = i_22_ & n797; + assign n529 = i_35_ & n526 & (n527 | n528); + assign n530 = i_25_ & n797; + assign n531 = n300 & i_33_; + assign n532 = n235 & (n525 | (n530 & n531)); + assign n533 = n906 & (~i_34_ | ~n391 | ~n686); + assign n534 = ~n532 & n533 & (n395 | n524); + assign n535 = ~n413 & i_34_ & n391; + assign n536 = ~i_20_ & ~i_21_; + assign n537 = n371 & n391; + assign n538 = ~n737 | ~n784; + assign n539 = n538 & n537 & n536 & i_2_; + assign n540 = i_34_ | n161; + assign n541 = i_31_ | i_32_; + assign n542 = ~i_22_ | n540 | n541 | ~n546; + assign n543 = i_29_ & n392; + assign n544 = ~n413 | ~n784; + assign n545 = ~n523 & n543 & (~n361 | n544); + assign n546 = ~i_30_ & n421; + assign n547 = n392 & (n535 | (n546 & ~n751)); + assign n548 = n112 | n413; + assign n549 = n112 | n474; + assign n550 = (n514 | n548) & (~n330 | n549); + assign n551 = n905 & (n442 | n476 | n510); + assign n552 = (~n330 | n794) & (n514 | n796); + assign n553 = n551 & n552 & (i_33_ | n550); + assign n554 = ~n655 | i_28_ | n318; + assign n555 = n973 & n411; + assign n556 = n438 | i_14_ | n787; + assign n557 = (n509 | n556) & (n555 | n295); + assign n558 = ~n226 & (~n554 | (n128 & ~n565)); + assign n559 = n795 | ~n303 | n450; + assign n560 = ~n558 & n559 & (n510 | n557); + assign n561 = (n297 | n549) & (~n310 | n383); + assign n562 = n794 | ~n300 | n444; + assign n563 = n562 & (n561 | n353); + assign n564 = n379 | ~i_37_ | n288; + assign n565 = i_34_ | n749; + assign n566 = ~i_35_ | ~i_37_; + assign n567 = n564 & (~n544 | n565 | n566); + assign n568 = n492 | n370 | ~n371; + assign n569 = n463 | n501 | n782; + assign n570 = n568 & n569 & (n410 | n375); + assign n571 = i_27_ | n769; + assign n572 = ~i_31_ | ~i_34_; + assign n573 = (~n235 | n571) & (n510 | n572); + assign n574 = (~n306 | n572) & (~i_31_ | n523); + assign n575 = n274 | n204 | ~n235; + assign n576 = n740 | ~i_20_ | n573; + assign n577 = n575 & n576 & (n574 | n473); + assign n578 = n308 & ~n574; + assign n579 = (n578 | ~n902) & (n53 | ~n803); + assign n580 = i_16_ | i_13_; + assign n581 = i_16_ | i_14_; + assign n582 = ~n579 & (n577 | (n580 & n581)); + assign n583 = i_34_ | i_24_ | n143 | n394; + assign n584 = n583 & (i_28_ | ~n228 | ~n259); + assign n585 = ~n51 | n540; + assign n586 = (~i_20_ | n584) & (n394 | n585); + assign n587 = (n363 | n514) & (n408 | n352); + assign n588 = (n397 | n410) & (n374 | ~n427); + assign n589 = n753 | n494 | ~n537; + assign n590 = i_19_ | n781; + assign n591 = n589 & (n588 | n100 | n590); + assign n592 = ~n308 | i_14_ | n69; + assign n593 = n592 & (n433 | n361); + assign n594 = ~i_30_ & (~n911 | (i_34_ & ~n483)); + assign n595 = n502 | n745 | n782 | n418; + assign n596 = i_0_ | i_8_ | n496 | n709; + assign n597 = n924 & (n503 | n224 | n510); + assign n598 = n926 & n927 & (n473 | ~n899); + assign n599 = (~i_25_ | n586) & (n356 | n587); + assign n600 = (n591 | n788) & (n359 | n593); + assign n601 = n928 & (n690 | (n904 & n929)); + assign n602 = n936 & n935 & n933 & n932 & n931 & n930 & ~n594 & ~n804; + assign n603 = n602 & n601 & n600 & n599 & n598 & n597 & n595 & n596; + assign n604 = ~i_13_ | n581; + assign n605 = (i_12_ | n604) & (~i_13_ | n361); + assign n606 = n413 & n361; + assign n607 = (i_10_ | n413) & (~i_13_ | n361); + assign n608 = i_5_ | ~i_3_ | i_4_; + assign n609 = n608 | n462 | i_6_; + assign n610 = i_4_ | n315; + assign n611 = ~i_2_ & (i_8_ | n610 | ~n735); + assign n612 = ~n610 & i_36_ & ~i_7_ & ~i_32_; + assign n613 = ~n607 & (~n611 | n612); + assign n614 = ~i_13_ & (~n609 | (~n453 & ~n610)); + assign n615 = ~i_32_ & n735; + assign n616 = ~i_9_ & (n613 | (n614 & n615)); + assign n617 = n957 & (~n259 | ~n735 | n958); + assign n618 = i_31_ | n610 | ~n615 | n958; + assign n619 = n617 & (~i_29_ | (~n616 & n618)); + assign n620 = n974 & n515; + assign n621 = n794 & n549; + assign n622 = (~i_36_ | n621) & (n620 | ~n735); + assign n623 = n433 | n413; + assign n624 = (~n615 | n623) & (n473 | n622); + assign n625 = n485 & n474; + assign n626 = n472 & n484; + assign n627 = (n473 | n625) & (~n308 | n626); + assign n628 = n972 & n592; + assign n629 = (n627 | n226) & (n628 | n172); + assign n630 = n425 & ~n610; + assign n631 = i_9_ | n610; + assign n632 = n400 & n604; + assign n633 = n631 | n632 | ~n214 | ~n421; + assign n634 = ~i_21_ & n776; + assign n635 = ~i_28_ & n219; + assign n636 = n54 & n634 & (n630 | n635); + assign n637 = ~n809 & (~n633 | (~i_28_ & ~n621)); + assign n638 = n310 & (~n898 | ~n907); + assign n639 = n410 | n631 | i_19_ | ~n214; + assign n640 = n114 | i_18_ | n608 | n501; + assign n641 = ~n306 | ~n371; + assign n642 = i_21_ | ~n655; + assign n643 = n641 & (n523 | n642); + assign n644 = ~n648 & (~n449 | ~n643); + assign n645 = n371 & (~n504 | ~n521); + assign n646 = n330 & (~n621 | (~i_32_ & ~n978)); + assign n647 = n352 | n651 | n438; + assign n648 = n796 & n548; + assign n649 = ~n646 & n647 & (n514 | n648); + assign n650 = n978 | n204 | ~n310; + assign n651 = n790 & n801; + assign n652 = n650 & (~n306 | n438 | n651); + assign n653 = (i_7_ | ~n259) & (n204 | n621); + assign n654 = ~i_35_ & ~i_32_ & i_34_; + assign n655 = ~i_23_ & ~i_24_; + assign n656 = n655 & ~n226 & n654; + assign n657 = ~n511 & (~n430 | ~n907); + assign n658 = ~n451 & (~n506 | ~n521); + assign n659 = ~i_29_ & n235; + assign n660 = ~i_28_ & (n656 | (~n653 & n659)); + assign n661 = n306 & (n645 | (~n623 & n654)); + assign n662 = ~i_32_ & (n644 | (~i_7_ & ~n812)); + assign n663 = n50 & (n636 | n637 | n638); + assign n664 = ~i_33_ | n777; + assign n665 = (~n235 | n664) & (~n229 | n510); + assign n666 = n973 & n900; + assign n667 = n411 & (i_31_ | n666); + assign n668 = n951 & (n678 | n172 | n510); + assign n669 = (~n330 | n620) & (n514 | n947); + assign n670 = n668 & n669 & (n667 | n352); + assign n671 = n140 & (i_31_ | ~n421 | n610); + assign n672 = ~i_8_ & ~n812; + assign n673 = ~n751 & n306 & ~n628; + assign n674 = ~i_31_ & (n672 | (~n643 & ~n980)); + assign n675 = n50 & (~n950 | (n300 & ~n411)); + assign n676 = ~n371 | i_31_ | n62 | n777 | n787; + assign n677 = n676 & (~n537 | n631 | ~n813); + assign n678 = n423 & n556; + assign n679 = n678 | ~n50 | n167; + assign n680 = ~n226 & ~i_34_ & n128; + assign n681 = ~i_14_ & ~i_25_; + assign n682 = i_28_ | i_30_ | n394 | n681; + assign n683 = ~n421 | i_24_ | ~n259; + assign n684 = n379 & ~n544; + assign n685 = n683 & (~i_29_ | n510 | n684); + assign n686 = n655 & i_21_; + assign n687 = n686 & (~n682 | (~n571 & ~n807)); + assign n688 = (n222 | n510) & (~n50 | n769); + assign n689 = n688 & (n201 | ~n306); + assign n690 = i_23_ | n777; + assign n691 = (n450 | n218) & (n690 | n201); + assign n692 = n779 | ~i_21_ | n691; + assign n693 = n692 & (n689 | n438); + assign n694 = i_11_ | n806; + assign n695 = ~i_3_ | n806; + assign n696 = (i_18_ | n695) & (i_19_ | n694); + assign n697 = i_21_ & ~i_23_; + assign n698 = n697 & i_25_ & ~n664; + assign n699 = i_22_ & n259 & n421; + assign n700 = ~n379 & (n698 | (n530 & n531)); + assign n701 = n608 | i_18_ | n98; + assign n702 = n701 & (i_7_ | ~n55 | n631); + assign n703 = i_9_ | ~i_2_ | ~i_3_; + assign n704 = n703 & (n100 | n608 | ~n735); + assign n705 = ~n611 & ~i_9_ & n55; + assign n706 = n421 & (n705 | (~i_18_ & ~n704)); + assign n707 = ~n706 & (~i_36_ | ~n425 | n702); + assign n708 = ~n981 & (i_31_ | n288 | ~n546); + assign n709 = ~n371 | n778; + assign n710 = n709 & (~n537 | n610); + assign n711 = n523 | n187 | n473; + assign n712 = n711 & (~n51 | n204 | n288); + assign n713 = ~n219 | ~i_34_ | ~i_36_; + assign n714 = (~n330 | n713) & (~i_36_ | n712); + assign n715 = ~n615 | i_2_ | n140; + assign n716 = ~n983 & (~n52 | ~n214 | n438); + assign n717 = (i_7_ | n714) & (n809 | ~n940); + assign n718 = n970 & (~i_21_ | n691 | n729); + assign n719 = n716 & (i_16_ | (n717 & n718)); + assign n720 = (n431 | n695) & (n432 | n694); + assign n721 = ~n697 | n573 | n696; + assign n722 = n721 & (n574 | n720); + assign n723 = (i_17_ | n205) & (i_16_ | ~n307); + assign n724 = n394 | n585; + assign n725 = ~n332 & n724 & (~i_21_ | n584); + assign n726 = i_31_ | i_30_ | n627 | n808; + assign n727 = n726 & (~n54 | ~n308 | n713); + assign n728 = (~n371 | n571) & (~i_31_ | n449); + assign n729 = i_12_ | n805; + assign n730 = (n689 | n729) & (~n52 | n441); + assign n731 = ~i_21_ & (~n982 | (i_20_ & ~n708)); + assign n732 = n235 & (n699 | n700 | ~n943); + assign n733 = i_34_ & (~n396 | n687 | ~n946); + assign n734 = n615 & (~n679 | n680 | ~n948); + assign n735 = ~i_35_ & i_36_; + assign n736 = n735 & (n673 | n674 | n675); + assign n737 = i_12_ | n581; + assign n738 = i_21_ | i_22_; + assign n739 = ~i_16_ & ~i_27_; + assign n740 = i_23_ | i_17_; + assign n741 = i_2_ | i_4_; + assign n742 = ~i_9_ | n315; + assign n743 = i_28_ | i_26_; + assign n744 = i_8_ | ~i_9_; + assign n745 = i_8_ | n315; + assign n746 = i_2_ | i_3_; + assign n747 = i_33_ | ~n219; + assign n748 = ~i_9_ | n746; + assign n749 = i_33_ | i_32_; + assign n750 = i_31_ | n749; + assign n751 = ~i_34_ | n541; + assign n752 = i_30_ | i_29_; + assign n753 = i_8_ | n314; + assign n754 = i_4_ | n746; + assign n755 = i_29_ | ~i_34_; + assign n756 = ~i_9_ | ~n58; + assign n757 = ~i_3_ | n741; + assign n758 = n757 | n468; + assign n759 = i_9_ | n758; + assign n760 = n313 | n114; + assign n761 = ~i_10_ | i_3_ | i_7_; + assign n762 = i_35_ | i_33_ | ~i_34_; + assign n763 = i_9_ | i_6_; + assign n764 = n745 | n757; + assign n765 = i_11_ | n763; + assign n766 = i_7_ | n314; + assign n767 = ~n51 | ~n655; + assign n768 = ~n324 | n752; + assign n769 = i_28_ | ~i_31_; + assign n770 = n187 | i_7_ | i_28_; + assign n771 = i_8_ | n746; + assign n772 = i_22_ | ~n421 | n684 | ~n697; + assign n773 = n754 | i_12_ | n742; + assign n774 = ~i_38_ | i_2_ | i_7_; + assign n775 = n61 | n62; + assign n776 = ~i_16_ & ~i_23_; + assign n777 = i_27_ | i_28_; + assign n778 = i_30_ | n777; + assign n779 = i_16_ | i_17_; + assign n780 = i_0_ | i_4_; + assign n781 = ~n537 | i_17_ | i_20_; + assign n782 = i_18_ | n781; + assign n783 = i_19_ | n779; + assign n784 = i_12_ | n580; + assign n785 = n313 | n766; + assign n786 = i_18_ | n740; + assign n787 = n315 | n316; + assign n788 = i_5_ | n780; + assign n789 = n114 | n788; + assign n790 = n90 | ~i_13_ | i_14_; + assign n791 = n313 | n753; + assign n792 = i_23_ | n581; + assign n793 = ~i_13_ | n763; + assign n794 = n112 | n485; + assign n795 = n84 | n361; + assign n796 = n112 | n361; + assign n797 = ~i_23_ & ~i_27_; + assign n798 = ~i_25_ | n777; + assign n799 = ~i_20_ | ~n655; + assign n800 = i_20_ | ~n655; + assign n801 = n90 | i_13_ | i_10_; + assign n802 = n87 | n400; + assign n803 = i_14_ | i_12_; + assign n804 = n545 | n547 | n539 | ~n542; + assign n805 = ~i_7_ | i_9_; + assign n806 = ~i_7_ | ~i_10_; + assign n807 = n605 | n806; + assign n808 = ~i_34_ | ~n735; + assign n809 = i_21_ | n740; + assign n810 = i_23_ | ~i_20_ | i_21_; + assign n811 = i_21_ | n779; + assign n812 = i_2_ | n62 | n709 | n811; + assign n813 = (i_13_ & ~i_14_) | (~i_10_ & (~i_13_ | ~i_14_)); + assign n814 = (n104 | n172) & (n167 | n318); + assign n815 = (~n271 | n751) & (n190 | n750); + assign n816 = (~n53 | n92) & (n67 | n240); + assign n817 = (n84 | n756) & (~n58 | n83); + assign n818 = n297 | ~i_19_ | n161; + assign n819 = n818 & (i_28_ | n295 | n193); + assign n820 = ~n322 & (n194 | (n190 & ~n303)); + assign n821 = ~n321 & (~n128 | n184 | n476); + assign n822 = (~n51 | n319) & (n104 | n320); + assign n823 = n791 & n84; + assign n824 = (n148 | ~n303) & (n168 | n823); + assign n825 = ~n323 & n824 & (n97 | n298); + assign n826 = n659 & (~n115 | n285); + assign n827 = (~n265 | n755) & (n135 | n743); + assign n828 = ~n290 & (n111 | n167 | ~n654); + assign n829 = n107 | n135; + assign n830 = (~n128 | n224) & (~n265 | n509); + assign n831 = n476 | i_28_ | ~n214; + assign n832 = n831 & (i_7_ | ~n300 | n747); + assign n833 = ~n271 & n297; + assign n834 = (n88 | n225) & (n833 | n255); + assign n835 = n111 | n161 | n167 | n117; + assign n836 = n835 & (i_25_ | i_28_ | ~n826); + assign n837 = n836 & (~i_35_ | n89 | n293); + assign n838 = ~n301 & n837 & (n226 | n294); + assign n839 = ~n302 & ~n304 & (n138 | n232); + assign n840 = ~n305 & n839 & (n231 | n289); + assign n841 = ~n336 | i_30_ | ~n271; + assign n842 = n841 & (~n65 | n297); + assign n843 = (~n60 | ~n310) & (i_24_ | n770); + assign n844 = (n255 | ~n267) & (~n51 | ~n336); + assign n845 = ~n276 & (~n278 | (n843 & n844)); + assign n846 = i_13_ | i_24_; + assign n847 = (n192 | n147) & (n188 | n846); + assign n848 = ~n251 & (n137 | ~n237 | n771); + assign n849 = n77 | i_2_ | ~n59; + assign n850 = n849 & (i_13_ | i_3_ | n195); + assign n851 = ~n214 | n144 | n183; + assign n852 = ~n254 & n851 & (~i_12_ | n250); + assign n853 = (i_26_ | ~n66) & (~n659 | ~n775); + assign n854 = n160 | n151 | n225; + assign n855 = n854 & (i_28_ | n227 | n132); + assign n856 = (n223 | n739) & (~i_23_ | ~n303); + assign n857 = ~n217 & (n79 | ~n252 | ~n253); + assign n858 = n188 | ~i_18_ | i_24_; + assign n859 = n858 & (n192 | n146); + assign n860 = (n202 | ~n300) & (n161 | n769); + assign n861 = ~n72 & ~n74 & (~i_9_ | n70); + assign n862 = (n68 | n149) & (~n237 | n773); + assign n863 = n793 & n362; + assign n864 = (n89 | n166) & (n863 | n173); + assign n865 = (n148 | ~n324) & (n145 | ~n328); + assign n866 = n106 | i_31_ | n875; + assign n867 = i_2_ | i_8_ | n140 | ~n324; + assign n868 = n536 | ~i_34_ | ~n421; + assign n869 = n868 & (n97 | ~n121 | ~n324); + assign n870 = n150 | n108 | n113; + assign n871 = n870 & (~i_13_ | n105 | n313); + assign n872 = n136 | i_2_ | n750; + assign n873 = ~n122 & n872 & (n104 | n120); + assign n874 = i_2_ | i_8_ | i_31_ | ~n269; + assign n875 = n787 & n69; + assign n876 = n874 & (~n324 | n750 | n875); + assign n877 = ~n328 | i_10_ | n85; + assign n878 = n877 & (~i_29_ | (~n775 & n776)); + assign n879 = (n82 | n282) & (n747 | n774); + assign n880 = n879 & (n91 | ~n278); + assign n881 = n536 | ~n235 | ~n421; + assign n882 = n881 & (~n71 | n77 | n748); + assign n883 = n882 & (~i_9_ | ~i_12_ | n79); + assign n884 = ~n127 & ~n129 & (n126 | ~n280); + assign n885 = ~n342 | n108 | n149; + assign n886 = n885 & (n145 | n833 | n160); + assign n887 = n142 | i_35_ | n185; + assign n888 = ~n331 & (~i_38_ | (n838 & n840)); + assign n889 = n976 & n945 & n845 & n275 & ~n273 & ~n270 & n264 & ~n266; + assign n890 = (~i_34_ | n889) & (i_29_ | n277); + assign n891 = ~n334 & ~n337 & (~n50 | n772); + assign n892 = (n133 | n241) & (n137 | n245); + assign n893 = ~n338 & (i_24_ | (n855 & n856)); + assign n894 = ~n341 & (n200 | (n861 & n862)); + assign n895 = ~n343 & n894 & (n195 | n756); + assign n896 = (n141 | n244) & (n159 | n190); + assign n897 = n208 & (i_22_ | (n884 & n883)); + assign n898 = n785 | n440; + assign n899 = ~n357 & (~n974 | (~n81 & ~n382)); + assign n900 = n791 | n792; + assign n901 = n274 | n203 | ~n235; + assign n902 = n901 & (~i_20_ | n573 | ~n776); + assign n903 = n752 | ~i_31_ | n567; + assign n904 = n903 & (n506 | n292 | n566); + assign n905 = n767 | i_7_ | n750; + assign n906 = ~n529 & (~n229 | n798 | n799); + assign n907 = n785 | n792; + assign n908 = n295 | n438 | n510 | n801; + assign n909 = ~n214 | i_0_ | i_30_ | n800 | n380 | n523; + assign n910 = n441 | n354 | n792; + assign n911 = n910 & (n357 | n486); + assign n912 = ~n259 | i_7_ | i_23_ | ~n267 | n351; + assign n913 = (~n427 | n795) & (n397 | n507); + assign n914 = n438 | n801 | ~i_37_ | ~n299; + assign n915 = n914 & (n318 | ~n427 | n477); + assign n916 = n62 | ~i_2_ | i_16_; + assign n917 = n916 & (n401 | n100 | n788); + assign n918 = n404 | n412 | ~i_37_ | n98; + assign n919 = (n297 | n555) & (~n300 | n408); + assign n920 = i_30_ | ~i_31_ | ~n306 | n379; + assign n921 = n920 & (i_14_ | n495 | n369); + assign n922 = n488 | n315 | n377 | n495 | ~n537; + assign n923 = n922 & (n363 | ~n427 | n641); + assign n924 = n450 | n508 | n297; + assign n925 = n751 | ~n546 | ~n686; + assign n926 = n925 & (n354 | n438 | n790); + assign n927 = n495 | i_13_ | n491; + assign n928 = (n434 | n570) & (~i_7_ | n582); + assign n929 = n548 | n224 | n353; + assign n930 = (n204 | n563) & (~n427 | n560); + assign n931 = (n684 | n534) & (n553 | n351); + assign n932 = (~i_37_ | n522) & (~n259 | n499); + assign n933 = (i_14_ | n461) & (n481 | n523); + assign n934 = n977 & n772 & ~n428 & ~n426 & ~n422 & n424; + assign n935 = (~n50 | n934) & (~n306 | n448); + assign n936 = (~i_34_ | n396) & (i_32_ | n390); + assign n937 = n752 | ~i_34_ | n510; + assign n938 = n937 & (i_30_ | ~n235 | ~n306); + assign n939 = (n379 | n395) & (~n307 | ~n308); + assign n940 = n50 & (~n715 | (i_0_ & n421)); + assign n941 = n274 | ~n544 | n696 | ~n797; + assign n942 = n941 & (~n527 | n769 | n807); + assign n943 = n942 & (~n391 | n684 | n810); + assign n944 = n807 | n274 | n450; + assign n945 = n767 | ~i_14_ | n394; + assign n946 = n944 & n945 & (n685 | n810); + assign n947 = n360 & n436; + assign n948 = (n947 | n641) & (n677 | n811); + assign n949 = n671 | n626 | ~n634; + assign n950 = n949 & (n666 | n167); + assign n951 = n450 | n980 | n167; + assign n952 = n537 & (~n639 | ~n640); + assign n953 = n203 | n288 | ~n51 | ~n54; + assign n954 = n953 & (i_17_ | i_21_ | ~n952); + assign n955 = n954 & (i_7_ | n751 | n767); + assign n956 = (~n235 | n652) & (~i_34_ | n649); + assign n957 = n232 | n606 | i_30_ | ~i_36_; + assign n958 = n737 & n784; + assign n959 = ~i_36_ | ~n54 | n187 | ~n308; + assign n960 = n479 & n959 & (n629 | ~n735); + assign n961 = (n619 | n642) & (i_29_ | n624); + assign n962 = n723 | n665 | ~n697; + assign n963 = n962 & (n730 | (n440 & n792)); + assign n964 = n963 & (n728 | n807); + assign n965 = (n681 | n725) & (~n306 | n727); + assign n966 = (~n544 | n722) & (n62 | n719); + assign n967 = (~i_36_ | ~n979) & (n670 | n808); + assign n968 = n967 & (n523 | (n961 & n960)); + assign n969 = n515 | i_29_ | n473 | n397; + assign n970 = n441 | n710 | i_21_ | ~i_36_; + assign n971 = i_33_ | n743; + assign n972 = ~n308 | i_13_ | n69; + assign n973 = n440 | n791; + assign n974 = n81 | n604; + assign n975 = ~n278 | n175 | n233; + assign n976 = n260 | i_24_ | i_28_; + assign n977 = i_0_ | n398 | n405 | ~n635; + assign n978 = n381 & n802; + assign n979 = n660 | n661 | n657 | n658 | ~n955 | ~n956 | n662 | n663; + assign n980 = n507 & n795; + assign n981 = n526 & ~n161 & n259; + assign n982 = n413 | n707 | i_23_ | ~n50; + assign n983 = n634 & n421 & n50 & i_0_ & ~i_12_; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/apex4/apex4.v b/openfpga_flow/benchmarks/MCNC_Verilog/apex4/apex4.v new file mode 100644 index 000000000..df98f3d1d --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/apex4/apex4.v @@ -0,0 +1,792 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:25:42 2019 + +module apex4 ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_; + wire n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, + n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, + n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, + n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, + n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, + n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, + n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, + n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, + n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, + n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, + n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, + n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, + n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, + n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, + n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, + n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, + n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, + n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, + n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, + n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, + n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, + n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, + n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, + n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, + n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, + n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, + n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, + n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, + n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, + n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, + n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, + n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, + n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, + n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, + n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, + n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, + n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, + n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, + n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, + n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, + n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, + n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, + n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, + n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, + n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, + n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, + n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, + n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, + n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, + n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, + n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, + n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, + n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, + n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, + n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, + n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, + n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749; + assign o_0_ = 1'b0; + assign o_1_ = ~n134; + assign o_2_ = ~n492; + assign o_3_ = ~n129; + assign o_4_ = ~n128; + assign o_5_ = ~n119; + assign o_6_ = ~n110; + assign o_7_ = ~n101; + assign o_8_ = ~n313; + assign o_9_ = ~n100; + assign o_10_ = ~n526; + assign o_11_ = ~n91; + assign o_12_ = ~n87; + assign o_13_ = ~n80; + assign o_14_ = ~n72; + assign o_15_ = ~n64; + assign o_16_ = ~n63; + assign o_17_ = ~n61; + assign o_18_ = ~n53; + assign n47 = n440 | n512; + assign n48 = n539 | n454; + assign n49 = n425 | n540; + assign n50 = n305 | n557; + assign n51 = n643 & n644 & n409 & n616 & n645 & n646 & n642 & n647; + assign n52 = n65 & (n515 | n514); + assign n53 = n47 & n48 & n49 & n50 & n51 & n52; + assign n54 = n641 & n501 & n624 & n620 & n586; + assign n55 = n314 | n591; + assign n56 = n528 | n208; + assign n57 = n425 | n558; + assign n58 = n236 | n576; + assign n59 = n545 | ~i_6_ | n531; + assign n60 = n49 & n742; + assign n61 = n48 & n54 & n55 & n56 & n57 & n58 & n59 & n60; + assign n62 = n651 & n652 & n653 & n654 & n650 & n259 & n604 & n655; + assign n63 = n54 & n62 & n50 & n47; + assign n64 = n51 & n62 & n58 & n56; + assign n65 = n190 | n543 | n514; + assign n66 = n229 | n548; + assign n67 = n443 | ~i_0_ | n419; + assign n68 = n190 | n562; + assign n69 = n656 & n247 & n657 & n621 & n658 & n599 & n659; + assign n70 = n437 & n456 & n513 & n660 & n661 & n516 & n662 & n663; + assign n71 = n504 & n505 & n506 & n507 & n508 & n509 & n510 & n511; + assign n72 = n65 & n66 & n67 & n68 & n69 & n70 & n71; + assign n73 = n664 & n597 & n556 & n264 & n358 & n391 & n434 & ~n522; + assign n74 = n360 & n517 & n399 & n518 & n519 & n520 & n521; + assign n75 = n515 | n245; + assign n76 = n440 | n558; + assign n77 = ~i_0_ | n190 | n250 | n252; + assign n78 = n430 | n419; + assign n79 = ~n332 | n345; + assign n80 = n73 & n74 & n75 & n70 & n76 & n77 & n78 & n79; + assign n81 = n634 & n596 & n350 & n468 & n130 & n665 & n666 & n667; + assign n82 = n440 | n144; + assign n83 = i_3_ | n373 | n419; + assign n84 = n190 | n575; + assign n85 = n342 | n559; + assign n86 = n182 | n575; + assign n87 = n74 & n81 & n82 & n69 & n83 & n84 & n85 & n86; + assign n88 = n560 | n575; + assign n89 = ~i_3_ | i_5_ | n440 | ~n461; + assign n90 = n345 | ~i_0_ | n250; + assign n91 = n88 & n89 & n59 & n90 & n71 & n73 & n81; + assign n92 = n570 & n193 & n202 & n199 & n588 & n589; + assign n93 = n178 & n184 & n183 & n185 & n186 & n187 & n188 & n189; + assign n94 = n141 & n155 & n160 & n164 & n172 & n122 & n173 & n174; + assign n95 = n221 & n222 & (n223 | n224); + assign n96 = n213 & n214 & n215 & n216 & n217 & n218 & n219 & n220; + assign n97 = n210 & n206 & n583 & n212 & n584 & n585 & n586 & n587; + assign n98 = n582 & n580 & ~n255 & n123 & n238 & n249 & ~n254; + assign n99 = n660 & n685 & n615 & n686 & n687 & n325 & n253 & n684; + assign n100 = n92 & n93 & n94 & n95 & n96 & n97 & n98 & n99; + assign n101 = n102 & n348 & n349 & n347 & n350 & n351 & n352 & n353; + assign n102 = n325 & n326 & n152 & n327 & n328 & n329 & n330 & n331; + assign n103 = n371 & (i_5_ | n372); + assign n104 = n369 & (n190 | n223 | n370); + assign n105 = n630 & n366 & n368 & n149 & n216 & n631; + assign n106 = n151 & n358 & n359 & n360 & n361 & n362 & n363 & n364; + assign n107 = n580 & n379 & n210 & n267 & n285 & ~n377; + assign n108 = n90 & n417 & n712 & n148 & n568 & n713; + assign n109 = n646 & n66 & n75 & n86 & n374 & ~n376; + assign n110 = n102 & n103 & n104 & n105 & n106 & n107 & n108 & n109; + assign n111 = n414 & (n415 | n416); + assign n112 = n281 & n413 & (n224 | ~n332); + assign n113 = n407 & n79 & n408 & n409 & n49 & n410 & n411 & n412; + assign n114 = n399 & n400 & n401 & n402 & n403 & n404 & n405 & n406; + assign n115 = n391 & n392 & n393 & n394 & n395 & n396 & n397 & n398; + assign n116 = n349 & n424 & n420 & n431 & n94 & n307; + assign n117 = n638 & n656 & n713 & n694 & n57 & n651; + assign n118 = n427 & n428 & n429 & n614 & n86 & n696; + assign n119 = n111 & n112 & n113 & n114 & n115 & n116 & n117 & n118; + assign n120 = n262 & n266 & n267 & n268 & n269 & n270 & n271 & n272; + assign n121 = n315 & n202 & n613 & n614; + assign n122 = n168 & n169 & (n170 | n171); + assign n123 = n88 & n231 & (n232 | n233); + assign n124 = n240 | n415 | i_0_ | ~i_2_; + assign n125 = n443 | n190 | n444; + assign n126 = n500 & n719 & n720; + assign n127 = n435 & n457 & n442 & n437 & n386 & n111 & n348 & n106; + assign n128 = n120 & n121 & n122 & n123 & n124 & n125 & n126 & n127; + assign n129 = n447 & n456 & n455 & n457 & n115 & n347 & n458 & n459; + assign n130 = n382 & n496 & (n145 | n335); + assign n131 = n640 & n494 & n495 & n505 & n504 & n619; + assign n132 = n661 & n657 & n497; + assign n133 = n603 & n48 & n68 & n720 & n279 & n187 & n602 & n741; + assign n134 = ~n499 & n97 & n112 & n130 & n131 & n132 & n133 & ~n498; + assign n135 = n339 | n542; + assign n136 = n440 | n416; + assign n137 = n166 | n541; + assign n138 = n236 | n538; + assign n139 = (n440 | n237) & (n305 | n224); + assign n140 = n679 & (n301 | n226 | n515); + assign n141 = n135 & n136 & n137 & n138 & n139 & n140; + assign n142 = n301 | n354 | n474; + assign n143 = n166 | n341; + assign n144 = n430 | n158; + assign n145 = i_6_ | i_7_; + assign n146 = n142 & n143 & (n144 | n145); + assign n147 = n422 | n467; + assign n148 = n170 | n544; + assign n149 = n342 | n367; + assign n150 = n440 | n436; + assign n151 = n166 | n365; + assign n152 = ~i_6_ | ~i_8_ | n453; + assign n153 = n422 | n546; + assign n154 = n146 & (n440 | n232 | n430); + assign n155 = n147 & n148 & n149 & n150 & n151 & n152 & n153 & n154; + assign n156 = n425 | n448; + assign n157 = n229 | n252 | n226; + assign n158 = i_5_ | n533; + assign n159 = n182 | ~n332; + assign n160 = n156 & n157 & (n158 | n159); + assign n161 = n529 | n548; + assign n162 = n425 | n546; + assign n163 = (n440 | n534) & (n423 | n454); + assign n164 = n161 & n162 & n163; + assign n165 = n182 | n430; + assign n166 = i_5_ | n240; + assign n167 = n165 | n166; + assign n168 = n240 | n223 | n208; + assign n169 = n342 | n337; + assign n170 = ~i_5_ | n533; + assign n171 = n425 | n430; + assign n172 = n553 & n554 & n167 & n286 & n555 & n556; + assign n173 = n683 & n477 & (n425 | n195); + assign n174 = n633 & n482 & n637 & n609 & n681 & n682 & n621 & n680; + assign n175 = n454 | n463; + assign n176 = n236 | n209; + assign n177 = (n166 | n559) & (n158 | n341); + assign n178 = n175 & n176 & n177; + assign n179 = n560 | n441; + assign n180 = n531 | n224; + assign n181 = n166 | n305; + assign n182 = ~i_6_ | n529; + assign n183 = n179 & n180 & (n181 | n182); + assign n184 = n295 & n294 & n563; + assign n185 = n166 | n367; + assign n186 = n529 | n531 | n472; + assign n187 = n225 | n301 | ~n332; + assign n188 = n678 & (~i_8_ | n562); + assign n189 = n675 & n676 & n269 & n76 & n362 & n624 & n677 & n50; + assign n190 = i_7_ | i_8_; + assign n191 = ~i_6_ | n543; + assign n192 = ~i_0_ | ~n469; + assign n193 = n85 & (n190 | n191 | n192); + assign n194 = i_6_ | ~i_7_; + assign n195 = n166 | n223; + assign n196 = n194 | n195; + assign n197 = n416 | n454; + assign n198 = n232 | n223; + assign n199 = n197 & (n198 | n145); + assign n200 = n166 | n566; + assign n201 = n339 | n274; + assign n202 = n200 & n201 & (n182 | n144); + assign n203 = n166 | n337; + assign n204 = n425 | n209; + assign n205 = (n158 | n233) & (n198 | n454); + assign n206 = n203 & n204 & n205; + assign n207 = n145 | n170 | ~n461; + assign n208 = ~i_6_ | n229; + assign n209 = n241 | n545; + assign n210 = n207 & (n208 | n209); + assign n211 = n223 | n339; + assign n212 = n211 | n208; + assign n213 = n440 | n209; + assign n214 = n158 | n274; + assign n215 = n236 | n572; + assign n216 = n182 | n572; + assign n217 = n415 | n211; + assign n218 = n301 | n191 | n488; + assign n219 = n182 | n211; + assign n220 = (n166 | n573) & (n532 | n145); + assign n221 = n531 | n229 | n545; + assign n222 = n59 & (n232 | ~n332 | n574); + assign n223 = ~i_2_ | n321; + assign n224 = n425 | n339; + assign n225 = i_6_ | n487; + assign n226 = ~i_1_ | n443; + assign n227 = n226 | ~i_7_ | n225; + assign n228 = i_0_ | n191 | ~n469; + assign n229 = ~i_7_ | ~i_8_; + assign n230 = n228 | n229; + assign n231 = n422 | n195; + assign n232 = ~i_5_ | n240; + assign n233 = n182 | ~n461; + assign n234 = n190 | n515 | n488; + assign n235 = n342 | n372; + assign n236 = i_6_ | n529; + assign n237 = n531 | n158; + assign n238 = n234 & n235 & (n236 | n237); + assign n239 = n321 | n577; + assign n240 = ~i_3_ | i_4_; + assign n241 = ~i_2_ | n373; + assign n242 = ~i_6_ | i_8_; + assign n243 = n239 & (n240 | n241 | n242); + assign n244 = i_6_ | n323; + assign n245 = n190 | ~n461; + assign n246 = n244 | n245; + assign n247 = n339 | n573; + assign n248 = i_3_ | i_4_ | i_6_; + assign n249 = n247 & (n229 | n248 | ~n332); + assign n250 = i_2_ | ~i_3_; + assign n251 = n250 | ~i_0_ | n225; + assign n252 = i_6_ | ~i_4_ | i_5_; + assign n253 = ~i_1_ | ~i_7_ | n250 | n252; + assign n254 = i_8_ & (~n251 | (~n430 & ~n472)); + assign n255 = ~i_5_ & (~n591 | (~n422 & ~n561)); + assign n256 = n425 | n436; + assign n257 = n378 | ~n461; + assign n258 = n170 | n367; + assign n259 = n208 | n558; + assign n260 = n327 & (n166 | n229 | ~n461); + assign n261 = n301 | n144; + assign n262 = n256 & n257 & n258 & n259 & n260 & n261; + assign n263 = n415 | n538; + assign n264 = n181 | n208; + assign n265 = n578 & (n301 | n241 | n444); + assign n266 = n78 & n263 & n264 & n265; + assign n267 = n592 & n593; + assign n268 = n238 & n700 & (n537 | n191); + assign n269 = n339 | n440 | ~n461; + assign n270 = n342 | n365; + assign n271 = n232 | n241 | n242; + assign n272 = n669 & n699 & n656 & n410; + assign n273 = ~n415 & (~n237 | (~n305 & ~n533)); + assign n274 = n208 | ~n332; + assign n275 = n274 | n170; + assign n276 = n444 | n565; + assign n277 = n365 | ~i_4_ | i_5_; + assign n278 = n276 & n277 & (n225 | n245); + assign n279 = n232 | n372; + assign n280 = n529 | n571; + assign n281 = n342 | n159; + assign n282 = n182 | n539; + assign n283 = n691 & (n527 | n544); + assign n284 = n689 & n466 & n690 & n658 & n452 & n648 & n138 & n402; + assign n285 = n279 & n280 & n281 & n282 & n183 & n146 & n283 & n284; + assign n286 = n545 | n274; + assign n287 = n158 | n542; + assign n288 = n532 | n425; + assign n289 = n425 | n453; + assign n290 = n170 | n302 | n430; + assign n291 = n182 | n423; + assign n292 = (n532 | n454) & (n528 | n145); + assign n293 = n286 & n136 & n287 & n288 & n289 & n290 & n291 & n292; + assign n294 = n208 | n546; + assign n295 = n440 | n493; + assign n296 = n236 | n564; + assign n297 = n158 | n591; + assign n298 = n688 & (n158 | n236 | ~n332); + assign n299 = n305 | n229 | n354; + assign n300 = n294 & n295 & n296 & n297 & n298 & n299; + assign n301 = ~i_7_ | i_8_; + assign n302 = i_6_ | ~i_8_; + assign n303 = n531 | n339; + assign n304 = (n301 | n228) & (n302 | n303); + assign n305 = i_2_ | n321; + assign n306 = i_3_ | i_5_; + assign n307 = n239 & (n305 | n236 | n306); + assign n308 = n602 & n603 & n604 & n519; + assign n309 = n702 & (~i_1_ | n182 | n342); + assign n310 = n351 & n285 & n120 & n300 & n304 & n293; + assign n311 = n673 & n84 & n640 & n675 & n701 & n67; + assign n312 = n76 & n404 & n219 & n636 & n649 & n79; + assign n313 = n308 & n95 & n307 & n309 & n160 & n310 & n311 & n312; + assign n314 = i_3_ | n487; + assign n315 = n159 | n314; + assign n316 = n165 | n232; + assign n317 = n440 | n423; + assign n318 = n190 | n248 | ~n332; + assign n319 = (n236 | n536) & (n415 | n575); + assign n320 = n317 & n318 & n319; + assign n321 = i_0_ | ~i_1_; + assign n322 = n191 | n301 | n321 | i_3_; + assign n323 = i_3_ | ~i_5_; + assign n324 = n208 | n223 | n323; + assign n325 = n537 | n252; + assign n326 = n415 | n467; + assign n327 = n342 | n573; + assign n328 = n706 & (i_0_ | n443 | n419); + assign n329 = i_3_ | n566; + assign n330 = n320 & n478 & n300 & n172 & n121 & n612 & n617; + assign n331 = n705 & n218 & n403 & n257 & n150 & n187 & n583 & n704; + assign n332 = ~i_2_ & ~n426; + assign n333 = ~n170 & (~n233 | (~n301 & n332)); + assign n334 = ~n430 & (~n224 | (~n314 & ~n529)); + assign n335 = n342 | n241; + assign n336 = n335 | n190; + assign n337 = ~n332 | n422; + assign n338 = n337 | n232; + assign n339 = i_5_ | n527; + assign n340 = n242 | n339 | ~n461; + assign n341 = n415 | ~n461; + assign n342 = ~i_5_ | n527; + assign n343 = n341 | n342; + assign n344 = n681 & n563 & n703; + assign n345 = n229 | n444; + assign n346 = i_1_ | ~n469; + assign n347 = n243 & n344 & (n345 | n346); + assign n348 = n621 & n622 & n623 & n624 & n496 & n625 & n626 & n627; + assign n349 = n340 & n343 & n58 & n620; + assign n350 = n618 & n405 & n619; + assign n351 = n605 & n178 & n606 & n607 & n278 & n596 & n601 & n608; + assign n352 = n582 & n193 & n266; + assign n353 = n399 & n258 & n695 & n708 & n506 & n186 & n654 & n707; + assign n354 = ~i_6_ | n487; + assign n355 = n301 | n354 | ~n461; + assign n356 = ~i_4_ | ~i_5_; + assign n357 = n356 | n165; + assign n358 = n182 | n448; + assign n359 = n241 | n224; + assign n360 = n232 | n182 | n241; + assign n361 = n166 | n159; + assign n362 = n170 | n341; + assign n363 = n47 & n501 & n147; + assign n364 = n408 & n396 & n676 & n197 & n710 & n388 & n711 & n709; + assign n365 = n430 | n208; + assign n366 = n365 | n232; + assign n367 = ~n332 | n425; + assign n368 = n367 | n158; + assign n369 = n531 | n208 | n547; + assign n370 = i_6_ | n547; + assign n371 = n534 | n449; + assign n372 = n425 | ~n461; + assign n373 = ~i_0_ | ~i_1_; + assign n374 = n373 | n301 | n339; + assign n375 = (i_1_ & (~i_5_ | ~n426)) | (i_5_ & ~n426); + assign n376 = ~n454 & ~i_4_ & n375; + assign n377 = ~n195 & (~n425 | ~n449); + assign n378 = n232 | n236; + assign n379 = ~n332 | n378; + assign n380 = n241 | n557; + assign n381 = n423 | n208; + assign n382 = n166 | n590; + assign n383 = n232 | n542; + assign n384 = (n170 | n541) & (n422 | n453); + assign n385 = n716 & (~i_1_ | i_2_ | n577); + assign n386 = n380 & n381 & n382 & n383 & n384 & n385; + assign n387 = n422 | n549; + assign n388 = n355 & n357 & n628 & n629; + assign n389 = n529 | n515; + assign n390 = n387 & n388 & (n389 | n346); + assign n391 = n236 | n549; + assign n392 = n170 | n590; + assign n393 = n415 | n441; + assign n394 = n182 | n564; + assign n395 = n425 | n538; + assign n396 = n208 | n441; + assign n397 = n425 | n441; + assign n398 = n390 & n320 & n386 & n308 & n278 & n718; + assign n399 = n166 | n430 | n454; + assign n400 = n170 | n159; + assign n401 = n314 | n559; + assign n402 = n425 | n564; + assign n403 = n144 | n454; + assign n404 = n314 | n274; + assign n405 = n538 | n208; + assign n406 = n326 & n607 & n282 & n697 & n714 & n715; + assign n407 = n474 | n438; + assign n408 = n314 | n449 | ~n461; + assign n409 = n449 | n564; + assign n410 = n182 | n467; + assign n411 = n708 & n625 & (n537 | n248); + assign n412 = n613 & n698 & n710; + assign n413 = n594 & n693 & n90; + assign n414 = n301 | n430 | n252; + assign n415 = i_6_ | n301; + assign n416 = n305 | n170; + assign n417 = n415 | n453; + assign n418 = n425 | n576; + assign n419 = n225 | n229; + assign n420 = n417 & n418 & (n192 | n419); + assign n421 = n574 | ~n332 | n545; + assign n422 = ~i_6_ | n301; + assign n423 = n166 | n241; + assign n424 = n421 & (n422 | n423); + assign n425 = ~i_6_ | n190; + assign n426 = ~i_0_ | i_1_; + assign n427 = n425 | n240 | n426; + assign n428 = n354 | i_7_ | n192; + assign n429 = n229 | n241 | n244; + assign n430 = i_2_ | n373; + assign n431 = n224 | n430; + assign n432 = ~n454 & ((~n223 & ~n306) | ~n534); + assign n433 = n372 | n158; + assign n434 = n415 | n546; + assign n435 = n434 & (n229 | ~n332 | n370); + assign n436 = n223 | n545; + assign n437 = n401 & (n236 | n436); + assign n438 = n229 | n515; + assign n439 = ~i_0_ | ~i_2_; + assign n440 = i_6_ | n190; + assign n441 = n223 | n170; + assign n442 = (n438 | n439) & (n440 | n441); + assign n443 = ~i_2_ | i_3_; + assign n444 = i_6_ | n356; + assign n445 = n208 | n493; + assign n446 = (n422 | n575) & (n529 | n441); + assign n447 = n445 & n361 & n446; + assign n448 = n430 | n545; + assign n449 = ~i_6_ | ~i_7_; + assign n450 = n448 | n449; + assign n451 = n232 | n367; + assign n452 = n305 | n422 | n533; + assign n453 = n342 | n223; + assign n454 = i_6_ | n229; + assign n455 = n451 & n452 & (n453 | n454); + assign n456 = n636 & n450 & n622 & n579; + assign n457 = n635 & n634 & n633 & n632 & n553 & n552 & ~n432 & n433; + assign n458 = n601 & n249 & n617; + assign n459 = n294 & n297 & n701 & n721 & n206 & n199 & n722 & n155; + assign n460 = ~n252 & ~n529; + assign n461 = i_2_ & ~n426; + assign n462 = n461 & ((~n194 & ~n314) | n460); + assign n463 = n305 | n339; + assign n464 = n463 | n415; + assign n465 = n182 | n534; + assign n466 = n314 | n365; + assign n467 = n241 | n158; + assign n468 = n465 & n466 & (n236 | n467); + assign n469 = i_3_ & i_2_; + assign n470 = n469 & ((~n229 & ~n252) | ~n389); + assign n471 = ~n470 & (i_2_ | n306 | n440); + assign n472 = ~i_6_ | n527; + assign n473 = (n229 | n472) & (i_7_ | n370); + assign n474 = i_3_ | n426; + assign n475 = (n321 | n158) & (i_4_ | n474); + assign n476 = n639 & n638 & n637 & n464 & n148 & ~n462; + assign n477 = n550 & n551 & n552; + assign n478 = n291 & n322 & n324; + assign n479 = n732 & n734 & (~i_1_ | n471); + assign n480 = n554 & n701 & n731 & n730 & n396 & n161 & n688 & n727; + assign n481 = n468 & n420 & n476 & n96 & n477 & n478 & n479 & n480; + assign n482 = n440 | n540; + assign n483 = n482 & (n198 | n415); + assign n484 = n302 | n158; + assign n485 = n166 | n236; + assign n486 = n484 & n485 & (~i_5_ | n440); + assign n487 = i_4_ | ~i_5_; + assign n488 = i_3_ | ~i_0_ | i_2_; + assign n489 = (n487 | n488) & (n373 | n170); + assign n490 = n262 & n92 & n612 & n738 & n739 & n737; + assign n491 = n621 & n649 & n644 & n643 & n289 & n162 & n393 & n736; + assign n492 = n483 & n447 & n481 & n114 & n103 & n442 & n490 & n491; + assign n493 = n241 | n314; + assign n494 = n493 | n422; + assign n495 = n209 | n182; + assign n496 = n425 | n493; + assign n497 = n356 | n182 | n346; + assign n498 = ~n170 & ~n449 & (~n430 | n461); + assign n499 = n332 & (~n378 | ~n485 | ~n740); + assign n500 = n545 | n145 | ~n332; + assign n501 = n531 | n557; + assign n502 = (n342 | n171) & (n449 | n335); + assign n503 = n500 & n501 & n502; + assign n504 = n166 | n274; + assign n505 = n158 | n566; + assign n506 = n422 | n576; + assign n507 = n719 & (n190 | n354 | n561); + assign n508 = n430 | n345; + assign n509 = n476 & n455 & n503 & n293 & n570 & n424; + assign n510 = n611 & n383 & n203 & n213 & n682 & n361; + assign n511 = n317 & n176 & n175 & n643 & n641 & n318; + assign n512 = n166 | n531; + assign n513 = n270 & (n425 | n512); + assign n514 = i_3_ | n530; + assign n515 = i_6_ | n543; + assign n516 = n514 | n515; + assign n517 = n145 | n575; + assign n518 = n166 | n233; + assign n519 = n170 | n566; + assign n520 = n669 & n387 & n217 & n693 & n200; + assign n521 = n404 & n692 & n359 & n744 & n650 & n642 & n483 & n105; + assign n522 = ~n232 & (~n544 | ~n591); + assign n523 = n390 & n104 & n113 & n93 & n141 & n304; + assign n524 = n745 & n746 & n747 & n77 & n381 & n605; + assign n525 = n689 & n271 & n705 & n360 & n47 & n618; + assign n526 = n481 & n435 & n131 & n513 & n503 & n523 & n524 & n525; + assign n527 = i_3_ | ~i_4_; + assign n528 = n305 | n342; + assign n529 = i_7_ | ~i_8_; + assign n530 = i_1_ | i_0_; + assign n531 = ~i_2_ | n530; + assign n532 = n342 | n531; + assign n533 = ~i_3_ | ~i_4_; + assign n534 = n170 | n241; + assign n535 = i_0_ | n443 | n225; + assign n536 = n339 | n430; + assign n537 = n223 | n229; + assign n538 = n531 | n170; + assign n539 = n305 | n158; + assign n540 = n305 | n314; + assign n541 = n422 | n430; + assign n542 = n208 | ~n461; + assign n543 = i_4_ | i_5_; + assign n544 = n415 | n430; + assign n545 = i_4_ | n306; + assign n546 = n305 | n545; + assign n547 = ~i_3_ | ~i_5_; + assign n548 = n430 | n370; + assign n549 = n223 | n158; + assign n550 = n232 | n341; + assign n551 = n170 | n372; + assign n552 = n208 | n540; + assign n553 = n182 | n549; + assign n554 = n208 | n463; + assign n555 = n540 | n454; + assign n556 = n425 | n467; + assign n557 = n422 | n339; + assign n558 = n531 | n314; + assign n559 = ~n332 | n454; + assign n560 = ~i_6_ | i_7_; + assign n561 = i_1_ | n443; + assign n562 = n426 | ~i_3_ | n252; + assign n563 = n236 | n211; + assign n564 = n305 | n232; + assign n565 = n529 | n474; + assign n566 = n422 | ~n461; + assign n567 = n236 | n463; + assign n568 = n536 | n560; + assign n569 = n339 | n341; + assign n570 = n567 & n196 & n568 & n569; + assign n571 = n223 | n314; + assign n572 = n241 | n339; + assign n573 = ~n332 | n415; + assign n574 = i_6_ | i_8_; + assign n575 = ~n461 | n545; + assign n576 = n232 | n531; + assign n577 = i_3_ | n190 | n444; + assign n578 = n49 & n394 & n421 & n387 & n445; + assign n579 = n440 | n564; + assign n580 = n246 & n578 & n243 & n410 & n579 & n418; + assign n581 = ~n461 | n485; + assign n582 = n227 & n230 & n451 & n581; + assign n583 = n422 | n441; + assign n584 = n422 | n571; + assign n585 = n182 | n546; + assign n586 = n425 | n416; + assign n587 = n182 | n436; + assign n588 = n672 & n673 & n606 & n674; + assign n589 = n668 & n626 & n669 & n670 & n671 & n287 & n645 & n296; + assign n590 = ~n332 | n440; + assign n591 = n182 | n531; + assign n592 = n407 & n135 & n692 & n392 & n137 & n693 & n694 & n55; + assign n593 = n695 & n696 & n685 & n687 & n585 & n697 & n698 & n681; + assign n594 = n339 | n559; + assign n595 = n181 | n425; + assign n596 = n418 & n393 & n594 & n595 & n550; + assign n597 = ~n332 | n557; + assign n598 = n425 | n144; + assign n599 = n440 | n571; + assign n600 = n314 | n541; + assign n601 = n600 & n599 & n598 & n597 & n518 & ~n273 & n275; + assign n602 = n182 | n493; + assign n603 = n232 | n274; + assign n604 = n422 | n558; + assign n605 = n170 | n236 | ~n461; + assign n606 = n430 | n485; + assign n607 = n208 | n416; + assign n608 = n551 & n686 & n639 & n637 & n671 & n569 & n57 & n653; + assign n609 = n339 | n159; + assign n610 = n422 | n237; + assign n611 = n237 | n454; + assign n612 = n609 & n395 & n316 & n610 & n611 & n391; + assign n613 = n236 | n416; + assign n614 = n539 | n242; + assign n615 = n181 | n302; + assign n616 = n454 | n564; + assign n617 = n615 & n256 & n269 & n234 & n214 & n270 & n50 & n616; + assign n618 = n529 | n535; + assign n619 = n223 | n557; + assign n620 = n532 | n208; + assign n621 = n422 | n538; + assign n622 = n182 | n571; + assign n623 = n181 | n440; + assign n624 = n182 | n463; + assign n625 = n182 | n195; + assign n626 = n565 | n191; + assign n627 = n397 & n338 & n336 & ~n334 & n82 & ~n333; + assign n628 = n425 | n571; + assign n629 = n342 | n274; + assign n630 = n236 | n342 | ~n461; + assign n631 = n534 | n415; + assign n632 = n232 | n171; + assign n633 = n236 | n539; + assign n634 = n342 | n233; + assign n635 = n672 & (n252 | ~n332 | n529); + assign n636 = n546 | n454; + assign n637 = n232 | n159; + assign n638 = n182 | n416; + assign n639 = n430 | n557; + assign n640 = n422 | n540; + assign n641 = i_2_ | n530; + assign n642 = n402 & n623 & n641 & n394; + assign n643 = n425 | n237; + assign n644 = n237 | n208; + assign n645 = n415 | n564; + assign n646 = n415 | n576; + assign n647 = n138 & n263 & n694 & n610 & n501 & n677 & n297; + assign n648 = n440 | n576; + assign n649 = n440 | n303; + assign n650 = n59 & n57 & n648 & n649 & n587; + assign n651 = n339 | n591; + assign n652 = i_5_ | n236 | n514; + assign n653 = n528 | n422; + assign n654 = n303 | n194; + assign n655 = n742 & n55 & n180; + assign n656 = n181 | n454; + assign n657 = n236 | n448; + assign n658 = n198 | n182; + assign n659 = n214 & n235 & n671 & n58 & n652 & n137; + assign n660 = n528 | n425; + assign n661 = n440 | n572; + assign n662 = n725 & n632 & n581 & n231 & n400 & n699 & n584; + assign n663 = n147 & n143 & n644 & n410 & n296 & n201 & n362 & n743; + assign n664 = n651 & n445 & n628; + assign n665 = n670 & n713 & n668 & n633 & n598 & n600; + assign n666 = n180 & n257 & n151 & n49 & n694 & n742; + assign n667 = n403 & n219 & n555 & n392 & n371 & n629; + assign n668 = n415 | n448; + assign n669 = n208 | n549; + assign n670 = n454 | n441; + assign n671 = n440 | n467; + assign n672 = n440 | n195; + assign n673 = n422 | n209; + assign n674 = n236 | n453; + assign n675 = n198 | n425; + assign n676 = n236 | n493; + assign n677 = n440 | n538; + assign n678 = n301 | n561 | n444; + assign n679 = n208 | n303; + assign n680 = n263 & n610 & n56; + assign n681 = n208 | n467; + assign n682 = n539 | n449; + assign n683 = ~n461 | ~i_3_ | n454; + assign n684 = n658 & n288 & n623 & n653 & n631 & n630 & n595; + assign n685 = n301 | n423; + assign n686 = n301 | n535; + assign n687 = n536 | n229; + assign n688 = n208 | n575; + assign n689 = n422 | n531 | n356; + assign n690 = n241 | n378; + assign n691 = n301 | n241 | n472; + assign n692 = n538 | n454; + assign n693 = n314 | n544; + assign n694 = n440 | n539; + assign n695 = n190 | n548; + assign n696 = n192 | n389; + assign n697 = n208 | n448; + assign n698 = n236 | n335; + assign n699 = n342 | n590; + assign n700 = n153 & (n440 | n223 | n306); + assign n701 = n440 | n549; + assign n702 = n305 | ~i_7_ | n244; + assign n703 = n527 | n182 | n373; + assign n704 = n638 & n235 & n136 & n677 & n669 & n567 & n217; + assign n705 = n540 | n574; + assign n706 = n425 | n241 | n547; + assign n707 = n164 & (n321 | n415 | n543); + assign n708 = n181 | n301; + assign n709 = n674 & (~i_7_ | n223 | n248); + assign n710 = n342 | n541; + assign n711 = n158 | n337; + assign n712 = ~i_3_ | i_5_ | n305 | n415; + assign n713 = n422 | n198; + assign n714 = n712 & (n354 | ~n461 | n529); + assign n715 = n171 | n323; + assign n716 = i_7_ | n244 | ~n461; + assign n717 = n301 | n225 | n226; + assign n718 = n717 & (n419 | n346); + assign n719 = n182 | n453; + assign n720 = n529 | n225 | n488; + assign n721 = n679 & (n226 | n438); + assign n722 = (n449 | n195) & (n223 | n224); + assign n723 = (n527 | n194) & (n301 | n232); + assign n724 = (n529 | n444) & (n190 | n166); + assign n725 = n339 | n233; + assign n726 = n549 | n194; + assign n727 = n517 & n149 & n725 & n726; + assign n728 = i_8_ | n252 | n488; + assign n729 = n728 & (n240 | n373 | n415); + assign n730 = n729 & (i_3_ | n454 | ~n461); + assign n731 = n533 | n236 | ~n332; + assign n732 = (n475 | n425) & (n473 | n241); + assign n733 = (n194 | n512) & (n529 | n540); + assign n734 = n733 & (n430 | (n724 & n723)); + assign n735 = ~i_0_ | ~i_2_ | ~i_7_ | n342; + assign n736 = n280 & n89 & n735 & n380 & n169 & n83; + assign n737 = (~n332 | n486) & (n232 | n591); + assign n738 = n489 | n190; + assign n739 = n373 | n208 | n547; + assign n740 = (n533 | n415) & (n422 | n232); + assign n741 = n383 & n295 & n675; + assign n742 = i_4_ | i_6_ | n514; + assign n743 = n215 & n204 & n690 & n162 & n726 & n258; + assign n744 = n184 & (n534 | n236); + assign n745 = ~i_2_ | ~i_5_ | n748 | n749; + assign n746 = i_3_ | n430 | n574; + assign n747 = n487 | n565; + assign n748 = i_1_ & (i_4_ | n229); + assign n749 = ~i_1_ & (~i_4_ | n208); +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/bigkey/bigkey.v b/openfpga_flow/benchmarks/MCNC_Verilog/bigkey/bigkey.v new file mode 100644 index 000000000..e6cf05c69 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/bigkey/bigkey.v @@ -0,0 +1,2197 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 09:55:28 2019 + +module bigkey ( clock, + Pstart_0_, Pkey_255_, Pkey_254_, Pkey_253_, Pkey_252_, Pkey_251_, + Pkey_250_, Pkey_249_, Pkey_248_, Pkey_247_, Pkey_246_, Pkey_245_, + Pkey_244_, Pkey_243_, Pkey_242_, Pkey_241_, Pkey_240_, Pkey_239_, + Pkey_238_, Pkey_237_, Pkey_236_, Pkey_235_, Pkey_234_, Pkey_233_, + Pkey_232_, Pkey_231_, Pkey_230_, Pkey_229_, Pkey_228_, Pkey_227_, + Pkey_226_, Pkey_225_, Pkey_224_, Pkey_223_, Pkey_222_, Pkey_221_, + Pkey_220_, Pkey_219_, Pkey_218_, Pkey_217_, Pkey_216_, Pkey_215_, + Pkey_214_, Pkey_213_, Pkey_212_, Pkey_211_, Pkey_210_, Pkey_209_, + Pkey_208_, Pkey_207_, Pkey_206_, Pkey_205_, Pkey_204_, Pkey_203_, + Pkey_202_, Pkey_201_, Pkey_200_, Pkey_199_, Pkey_198_, Pkey_197_, + Pkey_196_, Pkey_195_, Pkey_194_, Pkey_193_, Pkey_192_, Pkey_191_, + Pkey_190_, Pkey_189_, Pkey_188_, Pkey_187_, Pkey_186_, Pkey_185_, + Pkey_184_, Pkey_183_, Pkey_182_, Pkey_181_, Pkey_180_, Pkey_179_, + Pkey_178_, Pkey_177_, Pkey_176_, Pkey_175_, Pkey_174_, Pkey_173_, + Pkey_172_, Pkey_171_, Pkey_170_, Pkey_169_, Pkey_168_, Pkey_167_, + Pkey_166_, Pkey_165_, Pkey_164_, Pkey_163_, Pkey_162_, Pkey_161_, + Pkey_160_, Pkey_159_, Pkey_158_, Pkey_157_, Pkey_156_, Pkey_155_, + Pkey_154_, Pkey_153_, Pkey_152_, Pkey_151_, Pkey_150_, Pkey_149_, + Pkey_148_, Pkey_147_, Pkey_146_, Pkey_145_, Pkey_144_, Pkey_143_, + Pkey_142_, Pkey_141_, Pkey_140_, Pkey_139_, Pkey_138_, Pkey_137_, + Pkey_136_, Pkey_135_, Pkey_134_, Pkey_133_, Pkey_132_, Pkey_131_, + Pkey_130_, Pkey_129_, Pkey_128_, Pkey_127_, Pkey_126_, Pkey_125_, + Pkey_124_, Pkey_123_, Pkey_122_, Pkey_121_, Pkey_120_, Pkey_119_, + Pkey_118_, Pkey_117_, Pkey_116_, Pkey_115_, Pkey_114_, Pkey_113_, + Pkey_112_, Pkey_111_, Pkey_110_, Pkey_109_, Pkey_108_, Pkey_107_, + Pkey_106_, Pkey_105_, Pkey_104_, Pkey_103_, Pkey_102_, Pkey_101_, + Pkey_100_, Pkey_99_, Pkey_98_, Pkey_97_, Pkey_96_, Pkey_95_, Pkey_94_, + Pkey_93_, Pkey_92_, Pkey_91_, Pkey_90_, Pkey_89_, Pkey_88_, Pkey_87_, + Pkey_86_, Pkey_85_, Pkey_84_, Pkey_83_, Pkey_82_, Pkey_81_, Pkey_80_, + Pkey_79_, Pkey_78_, Pkey_77_, Pkey_76_, Pkey_75_, Pkey_74_, Pkey_73_, + Pkey_72_, Pkey_71_, Pkey_70_, Pkey_69_, Pkey_68_, Pkey_67_, Pkey_66_, + Pkey_65_, Pkey_64_, Pkey_63_, Pkey_62_, Pkey_61_, Pkey_60_, Pkey_59_, + Pkey_58_, Pkey_57_, Pkey_56_, Pkey_55_, Pkey_54_, Pkey_53_, Pkey_52_, + Pkey_51_, Pkey_50_, Pkey_49_, Pkey_48_, Pkey_47_, Pkey_46_, Pkey_45_, + Pkey_44_, Pkey_43_, Pkey_42_, Pkey_41_, Pkey_40_, Pkey_39_, Pkey_38_, + Pkey_37_, Pkey_36_, Pkey_35_, Pkey_34_, Pkey_33_, Pkey_32_, Pkey_31_, + Pkey_30_, Pkey_29_, Pkey_28_, Pkey_27_, Pkey_26_, Pkey_25_, Pkey_24_, + Pkey_23_, Pkey_22_, Pkey_21_, Pkey_20_, Pkey_19_, Pkey_18_, Pkey_17_, + Pkey_16_, Pkey_15_, Pkey_14_, Pkey_13_, Pkey_12_, Pkey_11_, Pkey_10_, + Pkey_9_, Pkey_8_, Pkey_7_, Pkey_6_, Pkey_5_, Pkey_4_, Pkey_3_, Pkey_2_, + Pkey_1_, Pkey_0_, Pencrypt_0_, Pcount_3_, Pcount_2_, Pcount_1_, + Pcount_0_, + Pnew_count_3_, Pnew_count_2_, Pnew_count_1_, Pnew_count_0_, + Pdata_ready_0_, PKSi_191_, PKSi_190_, PKSi_189_, PKSi_188_, PKSi_187_, + PKSi_186_, PKSi_185_, PKSi_184_, PKSi_183_, PKSi_182_, PKSi_181_, + PKSi_180_, PKSi_179_, PKSi_178_, PKSi_177_, PKSi_176_, PKSi_175_, + PKSi_174_, PKSi_173_, PKSi_172_, PKSi_171_, PKSi_170_, PKSi_169_, + PKSi_168_, PKSi_167_, PKSi_166_, PKSi_165_, PKSi_164_, PKSi_163_, + PKSi_162_, PKSi_161_, PKSi_160_, PKSi_159_, PKSi_158_, PKSi_157_, + PKSi_156_, PKSi_155_, PKSi_154_, PKSi_153_, PKSi_152_, PKSi_151_, + PKSi_150_, PKSi_149_, PKSi_148_, PKSi_147_, PKSi_146_, PKSi_145_, + PKSi_144_, PKSi_143_, PKSi_142_, PKSi_141_, PKSi_140_, PKSi_139_, + PKSi_138_, PKSi_137_, PKSi_136_, PKSi_135_, PKSi_134_, PKSi_133_, + PKSi_132_, PKSi_131_, PKSi_130_, PKSi_129_, PKSi_128_, PKSi_127_, + PKSi_126_, PKSi_125_, PKSi_124_, PKSi_123_, PKSi_122_, PKSi_121_, + PKSi_120_, PKSi_119_, PKSi_118_, PKSi_117_, PKSi_116_, PKSi_115_, + PKSi_114_, PKSi_113_, PKSi_112_, PKSi_111_, PKSi_110_, PKSi_109_, + PKSi_108_, PKSi_107_, PKSi_106_, PKSi_105_, PKSi_104_, PKSi_103_, + PKSi_102_, PKSi_101_, PKSi_100_, PKSi_99_, PKSi_98_, PKSi_97_, + PKSi_96_, PKSi_95_, PKSi_94_, PKSi_93_, PKSi_92_, PKSi_91_, PKSi_90_, + PKSi_89_, PKSi_88_, PKSi_87_, PKSi_86_, PKSi_85_, PKSi_84_, PKSi_83_, + PKSi_82_, PKSi_81_, PKSi_80_, PKSi_79_, PKSi_78_, PKSi_77_, PKSi_76_, + PKSi_75_, PKSi_74_, PKSi_73_, PKSi_72_, PKSi_71_, PKSi_70_, PKSi_69_, + PKSi_68_, PKSi_67_, PKSi_66_, PKSi_65_, PKSi_64_, PKSi_63_, PKSi_62_, + PKSi_61_, PKSi_60_, PKSi_59_, PKSi_58_, PKSi_57_, PKSi_56_, PKSi_55_, + PKSi_54_, PKSi_53_, PKSi_52_, PKSi_51_, PKSi_50_, PKSi_49_, PKSi_48_, + PKSi_47_, PKSi_46_, PKSi_45_, PKSi_44_, PKSi_43_, PKSi_42_, PKSi_41_, + PKSi_40_, PKSi_39_, PKSi_38_, PKSi_37_, PKSi_36_, PKSi_35_, PKSi_34_, + PKSi_33_, PKSi_32_, PKSi_31_, PKSi_30_, PKSi_29_, PKSi_28_, PKSi_27_, + PKSi_26_, PKSi_25_, PKSi_24_, PKSi_23_, PKSi_22_, PKSi_21_, PKSi_20_, + PKSi_19_, PKSi_18_, PKSi_17_, PKSi_16_, PKSi_15_, PKSi_14_, PKSi_13_, + PKSi_12_, PKSi_11_, PKSi_10_, PKSi_9_, PKSi_8_, PKSi_7_, PKSi_6_, + PKSi_5_, PKSi_4_, PKSi_3_, PKSi_2_, PKSi_1_, PKSi_0_ ); + input Pstart_0_, Pkey_255_, Pkey_254_, Pkey_253_, Pkey_252_, + Pkey_251_, Pkey_250_, Pkey_249_, Pkey_248_, Pkey_247_, Pkey_246_, + Pkey_245_, Pkey_244_, Pkey_243_, Pkey_242_, Pkey_241_, Pkey_240_, + Pkey_239_, Pkey_238_, Pkey_237_, Pkey_236_, Pkey_235_, Pkey_234_, + Pkey_233_, Pkey_232_, Pkey_231_, Pkey_230_, Pkey_229_, Pkey_228_, + Pkey_227_, Pkey_226_, Pkey_225_, Pkey_224_, Pkey_223_, Pkey_222_, + Pkey_221_, Pkey_220_, Pkey_219_, Pkey_218_, Pkey_217_, Pkey_216_, + Pkey_215_, Pkey_214_, Pkey_213_, Pkey_212_, Pkey_211_, Pkey_210_, + Pkey_209_, Pkey_208_, Pkey_207_, Pkey_206_, Pkey_205_, Pkey_204_, + Pkey_203_, Pkey_202_, Pkey_201_, Pkey_200_, Pkey_199_, Pkey_198_, + Pkey_197_, Pkey_196_, Pkey_195_, Pkey_194_, Pkey_193_, Pkey_192_, + Pkey_191_, Pkey_190_, Pkey_189_, Pkey_188_, Pkey_187_, Pkey_186_, + Pkey_185_, Pkey_184_, Pkey_183_, Pkey_182_, Pkey_181_, Pkey_180_, + Pkey_179_, Pkey_178_, Pkey_177_, Pkey_176_, Pkey_175_, Pkey_174_, + Pkey_173_, Pkey_172_, Pkey_171_, Pkey_170_, Pkey_169_, Pkey_168_, + Pkey_167_, Pkey_166_, Pkey_165_, Pkey_164_, Pkey_163_, Pkey_162_, + Pkey_161_, Pkey_160_, Pkey_159_, Pkey_158_, Pkey_157_, Pkey_156_, + Pkey_155_, Pkey_154_, Pkey_153_, Pkey_152_, Pkey_151_, Pkey_150_, + Pkey_149_, Pkey_148_, Pkey_147_, Pkey_146_, Pkey_145_, Pkey_144_, + Pkey_143_, Pkey_142_, Pkey_141_, Pkey_140_, Pkey_139_, Pkey_138_, + Pkey_137_, Pkey_136_, Pkey_135_, Pkey_134_, Pkey_133_, Pkey_132_, + Pkey_131_, Pkey_130_, Pkey_129_, Pkey_128_, Pkey_127_, Pkey_126_, + Pkey_125_, Pkey_124_, Pkey_123_, Pkey_122_, Pkey_121_, Pkey_120_, + Pkey_119_, Pkey_118_, Pkey_117_, Pkey_116_, Pkey_115_, Pkey_114_, + Pkey_113_, Pkey_112_, Pkey_111_, Pkey_110_, Pkey_109_, Pkey_108_, + Pkey_107_, Pkey_106_, Pkey_105_, Pkey_104_, Pkey_103_, Pkey_102_, + Pkey_101_, Pkey_100_, Pkey_99_, Pkey_98_, Pkey_97_, Pkey_96_, Pkey_95_, + Pkey_94_, Pkey_93_, Pkey_92_, Pkey_91_, Pkey_90_, Pkey_89_, Pkey_88_, + Pkey_87_, Pkey_86_, Pkey_85_, Pkey_84_, Pkey_83_, Pkey_82_, Pkey_81_, + Pkey_80_, Pkey_79_, Pkey_78_, Pkey_77_, Pkey_76_, Pkey_75_, Pkey_74_, + Pkey_73_, Pkey_72_, Pkey_71_, Pkey_70_, Pkey_69_, Pkey_68_, Pkey_67_, + Pkey_66_, Pkey_65_, Pkey_64_, Pkey_63_, Pkey_62_, Pkey_61_, Pkey_60_, + Pkey_59_, Pkey_58_, Pkey_57_, Pkey_56_, Pkey_55_, Pkey_54_, Pkey_53_, + Pkey_52_, Pkey_51_, Pkey_50_, Pkey_49_, Pkey_48_, Pkey_47_, Pkey_46_, + Pkey_45_, Pkey_44_, Pkey_43_, Pkey_42_, Pkey_41_, Pkey_40_, Pkey_39_, + Pkey_38_, Pkey_37_, Pkey_36_, Pkey_35_, Pkey_34_, Pkey_33_, Pkey_32_, + Pkey_31_, Pkey_30_, Pkey_29_, Pkey_28_, Pkey_27_, Pkey_26_, Pkey_25_, + Pkey_24_, Pkey_23_, Pkey_22_, Pkey_21_, Pkey_20_, Pkey_19_, Pkey_18_, + Pkey_17_, Pkey_16_, Pkey_15_, Pkey_14_, Pkey_13_, Pkey_12_, Pkey_11_, + Pkey_10_, Pkey_9_, Pkey_8_, Pkey_7_, Pkey_6_, Pkey_5_, Pkey_4_, + Pkey_3_, Pkey_2_, Pkey_1_, Pkey_0_, Pencrypt_0_, Pcount_3_, Pcount_2_, + Pcount_1_, Pcount_0_, clock; + output Pnew_count_3_, Pnew_count_2_, Pnew_count_1_, Pnew_count_0_, + Pdata_ready_0_, PKSi_191_, PKSi_190_, PKSi_189_, PKSi_188_, PKSi_187_, + PKSi_186_, PKSi_185_, PKSi_184_, PKSi_183_, PKSi_182_, PKSi_181_, + PKSi_180_, PKSi_179_, PKSi_178_, PKSi_177_, PKSi_176_, PKSi_175_, + PKSi_174_, PKSi_173_, PKSi_172_, PKSi_171_, PKSi_170_, PKSi_169_, + PKSi_168_, PKSi_167_, PKSi_166_, PKSi_165_, PKSi_164_, PKSi_163_, + PKSi_162_, PKSi_161_, PKSi_160_, PKSi_159_, PKSi_158_, PKSi_157_, + PKSi_156_, PKSi_155_, PKSi_154_, PKSi_153_, PKSi_152_, PKSi_151_, + PKSi_150_, PKSi_149_, PKSi_148_, PKSi_147_, PKSi_146_, PKSi_145_, + PKSi_144_, PKSi_143_, PKSi_142_, PKSi_141_, PKSi_140_, PKSi_139_, + PKSi_138_, PKSi_137_, PKSi_136_, PKSi_135_, PKSi_134_, PKSi_133_, + PKSi_132_, PKSi_131_, PKSi_130_, PKSi_129_, PKSi_128_, PKSi_127_, + PKSi_126_, PKSi_125_, PKSi_124_, PKSi_123_, PKSi_122_, PKSi_121_, + PKSi_120_, PKSi_119_, PKSi_118_, PKSi_117_, PKSi_116_, PKSi_115_, + PKSi_114_, PKSi_113_, PKSi_112_, PKSi_111_, PKSi_110_, PKSi_109_, + PKSi_108_, PKSi_107_, PKSi_106_, PKSi_105_, PKSi_104_, PKSi_103_, + PKSi_102_, PKSi_101_, PKSi_100_, PKSi_99_, PKSi_98_, PKSi_97_, + PKSi_96_, PKSi_95_, PKSi_94_, PKSi_93_, PKSi_92_, PKSi_91_, PKSi_90_, + PKSi_89_, PKSi_88_, PKSi_87_, PKSi_86_, PKSi_85_, PKSi_84_, PKSi_83_, + PKSi_82_, PKSi_81_, PKSi_80_, PKSi_79_, PKSi_78_, PKSi_77_, PKSi_76_, + PKSi_75_, PKSi_74_, PKSi_73_, PKSi_72_, PKSi_71_, PKSi_70_, PKSi_69_, + PKSi_68_, PKSi_67_, PKSi_66_, PKSi_65_, PKSi_64_, PKSi_63_, PKSi_62_, + PKSi_61_, PKSi_60_, PKSi_59_, PKSi_58_, PKSi_57_, PKSi_56_, PKSi_55_, + PKSi_54_, PKSi_53_, PKSi_52_, PKSi_51_, PKSi_50_, PKSi_49_, PKSi_48_, + PKSi_47_, PKSi_46_, PKSi_45_, PKSi_44_, PKSi_43_, PKSi_42_, PKSi_41_, + PKSi_40_, PKSi_39_, PKSi_38_, PKSi_37_, PKSi_36_, PKSi_35_, PKSi_34_, + PKSi_33_, PKSi_32_, PKSi_31_, PKSi_30_, PKSi_29_, PKSi_28_, PKSi_27_, + PKSi_26_, PKSi_25_, PKSi_24_, PKSi_23_, PKSi_22_, PKSi_21_, PKSi_20_, + PKSi_19_, PKSi_18_, PKSi_17_, PKSi_16_, PKSi_15_, PKSi_14_, PKSi_13_, + PKSi_12_, PKSi_11_, PKSi_10_, PKSi_9_, PKSi_8_, PKSi_7_, PKSi_6_, + PKSi_5_, PKSi_4_, PKSi_3_, PKSi_2_, PKSi_1_, PKSi_0_; + reg PKSi_79_, PKSi_92_, \[333] , N_N2737, PKSi_75_, PKSi_84_, N_N2741, + PKSi_82_, PKSi_93_, PKSi_85_, N_N2746, PKSi_73_, N_N2749, PKSi_80_, + PKSi_72_, PKSi_94_, PKSi_86_, PKSi_74_, PKSi_83_, N_N2757, PKSi_89_, + PKSi_91_, PKSi_81_, PKSi_77_, PKSi_87_, PKSi_78_, PKSi_95_, PKSi_76_, + PKSi_55_, PKSi_68_, PKSi_64_, N_N2770, PKSi_51_, PKSi_60_, N_N2774, + PKSi_58_, PKSi_69_, PKSi_61_, N_N2779, PKSi_49_, PKSi_66_, PKSi_56_, + PKSi_48_, PKSi_70_, PKSi_62_, PKSi_50_, PKSi_59_, N_N2789, PKSi_65_, + PKSi_67_, PKSi_57_, PKSi_53_, PKSi_63_, PKSi_54_, PKSi_71_, PKSi_52_, + PKSi_31_, PKSi_44_, PKSi_40_, N_N2802, PKSi_27_, PKSi_36_, N_N2806, + PKSi_34_, PKSi_45_, PKSi_37_, N_N2811, PKSi_25_, PKSi_42_, PKSi_32_, + PKSi_24_, PKSi_46_, PKSi_38_, PKSi_26_, PKSi_35_, N_N2821, PKSi_41_, + PKSi_43_, PKSi_33_, PKSi_29_, PKSi_39_, PKSi_30_, PKSi_47_, PKSi_28_, + PKSi_7_, PKSi_20_, PKSi_16_, N_N2834, PKSi_3_, PKSi_12_, N_N2838, + PKSi_10_, PKSi_21_, PKSi_13_, N_N2843, PKSi_1_, PKSi_18_, PKSi_8_, + PKSi_0_, PKSi_22_, PKSi_14_, PKSi_2_, PKSi_11_, N_N2853, PKSi_17_, + PKSi_19_, PKSi_9_, PKSi_5_, PKSi_15_, PKSi_6_, PKSi_23_, PKSi_4_, + PKSi_183_, PKSi_173_, N_N2865, PKSi_185_, PKSi_169_, PKSi_176_, + PKSi_188_, \[253] , PKSi_179_, PKSi_172_, PKSi_186_, PKSi_177_, + PKSi_180_, N_N2877, N_N2879, N_N2881, PKSi_175_, PKSi_182_, N_N2885, + PKSi_171_, PKSi_189_, N_N2889, PKSi_184_, PKSi_178_, \[234] , + PKSi_170_, PKSi_174_, PKSi_190_, PKSi_159_, PKSi_149_, N_N2899, + PKSi_161_, PKSi_145_, PKSi_152_, PKSi_164_, PKSi_157_, PKSi_155_, + PKSi_148_, PKSi_162_, N_N2909, PKSi_156_, PKSi_153_, PKSi_163_, + PKSi_144_, PKSi_151_, PKSi_158_, N_N2917, PKSi_147_, PKSi_165_, + N_N2921, PKSi_160_, PKSi_154_, PKSi_167_, PKSi_146_, PKSi_150_, + PKSi_166_, PKSi_135_, PKSi_125_, N_N2931, PKSi_137_, PKSi_121_, + PKSi_128_, PKSi_140_, PKSi_133_, PKSi_131_, PKSi_124_, PKSi_138_, + PKSi_129_, PKSi_132_, N_N2943, N_N2945, PKSi_120_, PKSi_127_, + PKSi_134_, N_N2950, PKSi_123_, PKSi_141_, N_N2954, PKSi_136_, + PKSi_130_, \[282] , PKSi_122_, PKSi_126_, PKSi_142_, PKSi_111_, + PKSi_101_, N_N2964, PKSi_113_, PKSi_97_, PKSi_104_, PKSi_116_, + PKSi_109_, PKSi_107_, PKSi_100_, PKSi_114_, PKSi_105_, PKSi_108_, + N_N2976, PKSi_115_, PKSi_96_, PKSi_103_, PKSi_110_, N_N2982, PKSi_99_, + PKSi_117_, N_N2986, PKSi_112_, PKSi_106_, PKSi_119_, PKSi_98_, + PKSi_102_, PKSi_118_; + wire n1137, n1138, n1139_1, n1140, n1141, n1142, n1143_1, n1144, n1145, + n1146, n1148, n1150, n1152, n1154, n1156, n1158, n1160, n1162, n1164, + n1166, n1168, n1170, n1172_1, n1174, n1176_1, n1178, n1180_1, n1182, + n1184, n1186, n1188, n1190, n1192, n1194, n1196, n1198, n1200, n1202_1, + n1204, n1206_1, n1208, n1210_1, n1212, n1214_1, n1216, n1218_1, n1220, + n1222_1, n1224, n1226_1, n1228, n1230_1, n1232, n1234_1, n1236, n1238, + n1240, n1242, n1244, n1246, n1248, n1250, n1252, n1254, n1256, n1258, + n1260, n1262, n1264, n1266, n1268, n1270, n1272, n1274, n1276, n1278, + n1280, n1282, n1284, n1286, n1288_1, n1290, n1292, n1294, n1296, n1298, + n1300, n1302, n1304, n1306, n1308, n1310, n1312, n1314, n1316, n1318, + n1320, n1322, n1324, n1326, n1328, n1330, n1332, n1334, n1336, n1338, + n1340, n1342, n1344, n1346, n1348, n1350, n1352, n1354, n1356, n1358, + n1360, n1362, n1364, n1366, n1368, n1370, n1372, n1374, n1376, n1378, + n1380, n1382, n1384, n1386, n1388, n1390, n1392, n1394, n1396, n1398, + n1400, n1402, n1404, n1406, n1408, n1410, n1412, n1414, n1416, n1418, + n1420, n1422, n1424, n1426, n1428, n1430, n1432, n1434, n1436, n1438, + n1440, n1442, n1444, n1446, n1448, n1450, n1452, n1454, n1456, n1458, + n1460, n1462, n1464, n1466, n1468, n1470, n1472, n1474, n1476, n1478, + n1480, n1482, n1484, n1486, n1488, n1490, n1492, n1494, n1496, n1498, + n1500, n1502, n1504, n1506, n1508, n1510, n1512, n1514, n1516, n1518, + n1520, n1522, n1524, n1526, n1528, n1530, n1532, n1534, n1536, n1538, + n1540, n1542, n1544, n1546, n1548, n1550, n1552, n1554, n1556, n1558, + n1560, n1562, n1564, n1566, n1568, n1570, n1572, n1574, n1576, n1578, + n1580, n1582, n1584, n1586, n1588, n1590, n1592, n1594, n1595, n1596, + n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, + n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, + n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, + n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, + n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, + n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, + n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, + n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, + n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, + n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, + n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, + n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, + n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, + n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, + n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745_1, n1746, + n1747, n1748, n1749_1, n1750, n1751, n1752, n1753, n1754, n1755, n1756, + n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, + n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, + n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, + n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, + n1797, n1798, n1799_1, n1800, n1801, n1802, n1803_1, n1804, n1805, + n1806, n1807_1, n1808, n1809, n1810, n1811_1, n1812, n1813, n1814, + n1815_1, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, + n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833_1, n1834, + n1835, n1836, n1837_1, n1838, n1839, n1840, n1841_1, n1842, n1843, + n1844, n1845_1, n1846, n1847, n1848, n1849_1, n1850, n1851, n1852, + n1853_1, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, + n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, + n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, + n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, + n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, + n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, + n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, + n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, + n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, + n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, + n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, + n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, + n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, + n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, + n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, + n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, + n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, + n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, + n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, + n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, + n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, + n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, + n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, + n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, + n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, + n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, + n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, + n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, + n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, + n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, + n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, + n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, + n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, + n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, + n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, + n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, + n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, + n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, + n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, + n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, + n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, + n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, + n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, + n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, + n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, + n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, + n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, + n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, + n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, + n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, + n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, + n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, + n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, + n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, + n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, + n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, + n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, + n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, + n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, + n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, + n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, + n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, + n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, + n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, + n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, + n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, + n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, + n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, + n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, + n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, + n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, + n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, + n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, + n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, + n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, + n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, + n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, + n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, + n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, + n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, + n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, + n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, + n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, + n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, + n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, + n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, + n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, + n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, + n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n921, + n925_1, n929_1, n934_1, n939_1, n943, n947, n952_1, n956_1, n960_1, + n964_1, n969, n973, n978_1, n982_1, n986_1, n990_1, n994_1, n998_1, + n1002_1, n1007, n1011, n1015, n1019, n1023, n1027, n1031, n1035, n1039, + n1043, n1047, n1051, n1056_1, n1060_1, n1064_1, n1069, n1073, n1077, + n1081, n1086_1, n1090_1, n1094_1, n1098_1, n1102_1, n1106_1, n1110_1, + n1114_1, n1118_1, n1123, n1127, n1131, n1135, n1139, n1143, n1147, + n1151, n1155, n1159, n1163, n1167_1, n1172, n1176, n1180, n1185, n1189, + n1193, n1197, n1202, n1206, n1210, n1214, n1218, n1222, n1226, n1230, + n1234, n1239, n1243, n1247, n1251, n1255, n1259, n1263, n1267, n1271, + n1275, n1279, n1283, n1288, n1292_1, n1296_1, n1301_1, n1305_1, + n1309_1, n1313_1, n1318_1, n1322_1, n1326_1, n1330_1, n1334_1, n1338_1, + n1342_1, n1346_1, n1350_1, n1355_1, n1359_1, n1363_1, n1367_1, n1371_1, + n1375_1, n1379_1, n1383_1, n1387_1, n1391_1, n1395_1, n1400_1, n1404_1, + n1408_1, n1412_1, n1416_1, n1421_1, n1425_1, n1429_1, n1433_1, n1437_1, + n1441_1, n1446_1, n1451_1, n1456_1, n1460_1, n1464_1, n1469_1, n1473_1, + n1477_1, n1482_1, n1486_1, n1490_1, n1495_1, n1499_1, n1503_1, n1507_1, + n1511_1, n1515, n1520_1, n1524_1, n1528_1, n1532_1, n1536_1, n1540_1, + n1544_1, n1548_1, n1552_1, n1557_1, n1561_1, n1565_1, n1569_1, n1573_1, + n1577_1, n1581_1, n1586_1, n1590_1, n1594_1, n1599_1, n1603_1, n1607_1, + n1611_1, n1615_1, n1619_1, n1623_1, n1627_1, n1631_1, n1636_1, n1640_1, + n1644_1, n1648_1, n1652_1, n1656_1, n1660_1, n1664_1, n1668_1, n1672_1, + n1676_1, n1681_1, n1686_1, n1690_1, n1694_1, n1698_1, n1703_1, n1707_1, + n1711_1, n1716_1, n1720_1, n1724_1, n1729_1, n1733_1, n1737_1, n1741_1, + n1745, n1749, n1754_1, n1758_1, n1762_1, n1766_1, n1770_1, n1774_1, + n1778_1, n1782_1, n1786_1, n1790_1, n1794_1, n1799, n1803, n1807, + n1811, n1815, n1820_1, n1824_1, n1828_1, n1833, n1837, n1841, n1845, + n1849, n1853; + assign Pnew_count_3_ = ~n1142; + assign Pnew_count_2_ = ~n1143_1; + assign Pnew_count_1_ = ~n1144; + assign Pnew_count_0_ = ~n1145; + assign Pdata_ready_0_ = ~n1141; + assign n1137 = ~Pstart_0_ | Pencrypt_0_; + assign n1138 = ~Pstart_0_ | ~Pencrypt_0_; + assign n1139_1 = n1597 | Pstart_0_ | Pencrypt_0_; + assign n1140 = n1597 & ~Pstart_0_ & ~Pencrypt_0_; + assign n1141 = n2049 & (Pstart_0_ | n2050); + assign n1142 = n1137 & (Pstart_0_ | n2058); + assign n1143_1 = ~n2053 & (Pencrypt_0_ | n1595) & n2054; + assign n1144 = n1137 & n2051 & (~Pcount_0_ | n2052); + assign n1145 = n1137 & (Pstart_0_ | Pcount_0_); + assign n1146 = n1823 & (~Pkey_62_ | n1138) & n1824; + assign n1387_1 = ~n1146; + assign n1148 = n1821 & (~Pkey_195_ | n1138) & n1822; + assign n1391_1 = ~n1148; + assign n1150 = n1819 & (~Pkey_203_ | n1138) & n1820; + assign n1395_1 = ~n1150; + assign n1152 = n1817 & (~Pkey_211_ | n1138) & n1818; + assign n1400_1 = ~n1152; + assign n1154 = n1815_1 & (~Pkey_219_ | n1138) & n1816; + assign n1404_1 = ~n1154; + assign n1156 = n1813 & (~Pkey_196_ | n1138) & n1814; + assign n1408_1 = ~n1156; + assign n1158 = n1811_1 & (~Pkey_204_ | n1138) & n1812; + assign n1412_1 = ~n1158; + assign n1160 = n1809 & (~Pkey_212_ | n1138) & n1810; + assign n1416_1 = ~n1160; + assign n1162 = n1807_1 & (~Pkey_220_ | n1138) & n1808; + assign n1421_1 = ~n1162; + assign n1164 = n1805 & (~Pkey_228_ | n1138) & n1806; + assign n1425_1 = ~n1164; + assign n1166 = n1803_1 & (~Pkey_172_ | n1138) & n1804; + assign n1429_1 = ~n1166; + assign n1168 = n1801 & (~Pkey_244_ | n1138) & n1802; + assign n1433_1 = ~n1168; + assign n1170 = n1799_1 & (~Pkey_252_ | n1138) & n1800; + assign n1437_1 = ~n1170; + assign n1172_1 = n1797 & (~Pkey_197_ | n1138) & n1798; + assign n1441_1 = ~n1172_1; + assign n1174 = n1795 & (~Pkey_205_ | n1138) & n1796; + assign n1446_1 = ~n1174; + assign n1176_1 = n1793 & (~Pkey_213_ | n1138) & n1794; + assign n1451_1 = ~n1176_1; + assign n1178 = n1791 & (~Pkey_221_ | n1138) & n1792; + assign n1456_1 = ~n1178; + assign n1180_1 = n1789 & (~Pkey_229_ | n1138) & n1790; + assign n1460_1 = ~n1180_1; + assign n1182 = n1787 & (~Pkey_237_ | n1138) & n1788; + assign n1464_1 = ~n1182; + assign n1184 = n1785 & (~Pkey_245_ | n1138) & n1786; + assign n1469_1 = ~n1184; + assign n1186 = n1783 & (~Pkey_253_ | n1138) & n1784; + assign n1473_1 = ~n1186; + assign n1188 = n1781 & (~Pkey_198_ | n1138) & n1782; + assign n1477_1 = ~n1188; + assign n1190 = n1779 & (~Pkey_206_ | n1138) & n1780; + assign n1482_1 = ~n1190; + assign n1192 = n1777 & (~Pkey_214_ | n1138) & n1778; + assign n1486_1 = ~n1192; + assign n1194 = n1775 & (~Pkey_222_ | n1138) & n1776; + assign n1490_1 = ~n1194; + assign n1196 = n1773 & (~Pkey_230_ | n1138) & n1774; + assign n1495_1 = ~n1196; + assign n1198 = n1771 & (~Pkey_238_ | n1138) & n1772; + assign n1499_1 = ~n1198; + assign n1200 = n1769 & (~Pkey_246_ | n1138) & n1770; + assign n1503_1 = ~n1200; + assign n1202_1 = n1767 & (~Pkey_254_ | n1138) & n1768; + assign n1507_1 = ~n1202_1; + assign n1204 = n1765 & (~Pkey_131_ | n1138) & n1766; + assign n1511_1 = ~n1204; + assign n1206_1 = n1763 & (~Pkey_139_ | n1138) & n1764; + assign n1515 = ~n1206_1; + assign n1208 = n1761 & (~Pkey_147_ | n1138) & n1762; + assign n1520_1 = ~n1208; + assign n1210_1 = n1759 & (~Pkey_155_ | n1138) & n1760; + assign n1524_1 = ~n1210_1; + assign n1212 = n1757 & (~Pkey_132_ | n1138) & n1758; + assign n1528_1 = ~n1212; + assign n1214_1 = n1755 & (~Pkey_140_ | n1138) & n1756; + assign n1532_1 = ~n1214_1; + assign n1216 = n1753 & (~Pkey_148_ | n1138) & n1754; + assign n1536_1 = ~n1216; + assign n1218_1 = n1751 & (~Pkey_156_ | n1138) & n1752; + assign n1540_1 = ~n1218_1; + assign n1220 = n1749_1 & (~Pkey_164_ | n1138) & n1750; + assign n1544_1 = ~n1220; + assign n1222_1 = n1747 & (~Pkey_172_ | n1138) & n1748; + assign n1548_1 = ~n1222_1; + assign n1224 = n1745_1 & (~Pkey_180_ | n1138) & n1746; + assign n1552_1 = ~n1224; + assign n1226_1 = n1743 & (~Pkey_188_ | n1138) & n1744; + assign n1557_1 = ~n1226_1; + assign n1228 = n1741 & (~Pkey_133_ | n1138) & n1742; + assign n1561_1 = ~n1228; + assign n1230_1 = n1739 & (~Pkey_141_ | n1138) & n1740; + assign n1565_1 = ~n1230_1; + assign n1232 = n1737 & (~Pkey_149_ | n1138) & n1738; + assign n1569_1 = ~n1232; + assign n1234_1 = n1735 & (~Pkey_157_ | n1138) & n1736; + assign n1573_1 = ~n1234_1; + assign n1236 = n1733 & (~Pkey_165_ | n1138) & n1734; + assign n1577_1 = ~n1236; + assign n1238 = n1731 & (~Pkey_173_ | n1138) & n1732; + assign n1581_1 = ~n1238; + assign n1240 = n1729 & (~Pkey_181_ | n1138) & n1730; + assign n1586_1 = ~n1240; + assign n1242 = n1727 & (~Pkey_189_ | n1138) & n1728; + assign n1590_1 = ~n1242; + assign n1244 = n1725 & (~Pkey_134_ | n1138) & n1726; + assign n1594_1 = ~n1244; + assign n1246 = n1723 & (~Pkey_142_ | n1138) & n1724; + assign n1599_1 = ~n1246; + assign n1248 = n1721 & (~Pkey_150_ | n1138) & n1722; + assign n1603_1 = ~n1248; + assign n1250 = n1719 & (~Pkey_158_ | n1138) & n1720; + assign n1607_1 = ~n1250; + assign n1252 = n1717 & (~Pkey_166_ | n1138) & n1718; + assign n1611_1 = ~n1252; + assign n1254 = n1715 & (~Pkey_174_ | n1138) & n1716; + assign n1615_1 = ~n1254; + assign n1256 = n1713 & (~Pkey_182_ | n1138) & n1714; + assign n1619_1 = ~n1256; + assign n1258 = n1711 & (~Pkey_190_ | n1138) & n1712; + assign n1623_1 = ~n1258; + assign n1260 = n1709 & (~Pkey_67_ | n1138) & n1710; + assign n1627_1 = ~n1260; + assign n1262 = n1707 & (~Pkey_75_ | n1138) & n1708; + assign n1631_1 = ~n1262; + assign n1264 = n1705 & (~Pkey_83_ | n1138) & n1706; + assign n1636_1 = ~n1264; + assign n1266 = n1703 & (~Pkey_91_ | n1138) & n1704; + assign n1640_1 = ~n1266; + assign n1268 = n1701 & (~Pkey_68_ | n1138) & n1702; + assign n1644_1 = ~n1268; + assign n1270 = n1699 & (~Pkey_76_ | n1138) & n1700; + assign n1648_1 = ~n1270; + assign n1272 = n1697 & (~Pkey_84_ | n1138) & n1698; + assign n1652_1 = ~n1272; + assign n1274 = n1695 & (~Pkey_92_ | n1138) & n1696; + assign n1656_1 = ~n1274; + assign n1276 = n1693 & (~Pkey_100_ | n1138) & n1694; + assign n1660_1 = ~n1276; + assign n1278 = n1691 & (~Pkey_44_ | n1138) & n1692; + assign n1664_1 = ~n1278; + assign n1280 = n1689 & (~Pkey_116_ | n1138) & n1690; + assign n1668_1 = ~n1280; + assign n1282 = n1687 & (~Pkey_124_ | n1138) & n1688; + assign n1672_1 = ~n1282; + assign n1284 = n1685 & (~Pkey_69_ | n1138) & n1686; + assign n1676_1 = ~n1284; + assign n1286 = n1683 & (~Pkey_77_ | n1138) & n1684; + assign n1681_1 = ~n1286; + assign n1288_1 = n1681 & (~Pkey_85_ | n1138) & n1682; + assign n1686_1 = ~n1288_1; + assign n1290 = n1679 & (~Pkey_93_ | n1138) & n1680; + assign n1690_1 = ~n1290; + assign n1292 = n1677 & (~Pkey_101_ | n1138) & n1678; + assign n1694_1 = ~n1292; + assign n1294 = n1675 & (~Pkey_109_ | n1138) & n1676; + assign n1698_1 = ~n1294; + assign n1296 = n1673 & (~Pkey_117_ | n1138) & n1674; + assign n1703_1 = ~n1296; + assign n1298 = n1671 & (~Pkey_125_ | n1138) & n1672; + assign n1707_1 = ~n1298; + assign n1300 = n1669 & (~Pkey_70_ | n1138) & n1670; + assign n1711_1 = ~n1300; + assign n1302 = n1667 & (~Pkey_78_ | n1138) & n1668; + assign n1716_1 = ~n1302; + assign n1304 = n1665 & (~Pkey_86_ | n1138) & n1666; + assign n1720_1 = ~n1304; + assign n1306 = n1663 & (~Pkey_94_ | n1138) & n1664; + assign n1724_1 = ~n1306; + assign n1308 = n1661 & (~Pkey_102_ | n1138) & n1662; + assign n1729_1 = ~n1308; + assign n1310 = n1659 & (~Pkey_110_ | n1138) & n1660; + assign n1733_1 = ~n1310; + assign n1312 = n1657 & (~Pkey_118_ | n1138) & n1658; + assign n1737_1 = ~n1312; + assign n1314 = n1655 & (~Pkey_126_ | n1138) & n1656; + assign n1741_1 = ~n1314; + assign n1316 = n1653 & (~Pkey_3_ | n1138) & n1654; + assign n1745 = ~n1316; + assign n1318 = n1651 & (~Pkey_11_ | n1138) & n1652; + assign n1749 = ~n1318; + assign n1320 = n1649 & (~Pkey_19_ | n1138) & n1650; + assign n1754_1 = ~n1320; + assign n1322 = n1647 & (~Pkey_27_ | n1138) & n1648; + assign n1758_1 = ~n1322; + assign n1324 = n1645 & (~Pkey_4_ | n1138) & n1646; + assign n1762_1 = ~n1324; + assign n1326 = n1643 & (~Pkey_12_ | n1138) & n1644; + assign n1766_1 = ~n1326; + assign n1328 = n1641 & (~Pkey_20_ | n1138) & n1642; + assign n1770_1 = ~n1328; + assign n1330 = n1639 & (~Pkey_28_ | n1138) & n1640; + assign n1774_1 = ~n1330; + assign n1332 = n1637 & (~Pkey_36_ | n1138) & n1638; + assign n1778_1 = ~n1332; + assign n1334 = n1635 & (~Pkey_44_ | n1138) & n1636; + assign n1782_1 = ~n1334; + assign n1336 = n1633 & (~Pkey_52_ | n1138) & n1634; + assign n1786_1 = ~n1336; + assign n1338 = n1631 & (~Pkey_60_ | n1138) & n1632; + assign n1790_1 = ~n1338; + assign n1340 = n1629 & (~Pkey_5_ | n1138) & n1630; + assign n1794_1 = ~n1340; + assign n1342 = n1627 & (~Pkey_13_ | n1138) & n1628; + assign n1799 = ~n1342; + assign n1344 = n1625 & (~Pkey_21_ | n1138) & n1626; + assign n1803 = ~n1344; + assign n1346 = n1623 & (~Pkey_29_ | n1138) & n1624; + assign n1807 = ~n1346; + assign n1348 = n1621 & (~Pkey_37_ | n1138) & n1622; + assign n1811 = ~n1348; + assign n1350 = n1619 & (~Pkey_45_ | n1138) & n1620; + assign n1815 = ~n1350; + assign n1352 = n1617 & (~Pkey_53_ | n1138) & n1618; + assign n1820_1 = ~n1352; + assign n1354 = n1615 & (~Pkey_61_ | n1138) & n1616; + assign n1824_1 = ~n1354; + assign n1356 = n1613 & (~Pkey_6_ | n1138) & n1614; + assign n1828_1 = ~n1356; + assign n1358 = n1611 & (~Pkey_14_ | n1138) & n1612; + assign n1833 = ~n1358; + assign n1360 = n1609 & (~Pkey_22_ | n1138) & n1610; + assign n1837 = ~n1360; + assign n1362 = n1607 & (~Pkey_30_ | n1138) & n1608; + assign n1841 = ~n1362; + assign n1364 = n1605 & (~Pkey_38_ | n1138) & n1606; + assign n1845 = ~n1364; + assign n1366 = n1603 & (~Pkey_46_ | n1138) & n1604; + assign n1849 = ~n1366; + assign n1368 = n1601 & (~Pkey_54_ | n1138) & n1602; + assign n1853 = ~n1368; + assign n1370 = n2047 & (~Pkey_56_ | n1138) & n2048; + assign n921 = ~n1370; + assign n1372 = n2045 & (~Pkey_227_ | n1138) & n2046; + assign n925_1 = ~n1372; + assign n1374 = n2043 & (~Pkey_235_ | n1138) & n2044; + assign n929_1 = ~n1374; + assign n1376 = n2041 & (~Pkey_243_ | n1138) & n2042; + assign n934_1 = ~n1376; + assign n1378 = n2039 & (~Pkey_251_ | n1138) & n2040; + assign n939_1 = ~n1378; + assign n1380 = n2037 & (~Pkey_194_ | n1138) & n2038; + assign n943 = ~n1380; + assign n1382 = n2035 & (~Pkey_202_ | n1138) & n2036; + assign n947 = ~n1382; + assign n1384 = n2033 & (~Pkey_210_ | n1138) & n2034; + assign n952_1 = ~n1384; + assign n1386 = n2031 & (~Pkey_218_ | n1138) & n2032; + assign n956_1 = ~n1386; + assign n1388 = n2029 & (~Pkey_226_ | n1138) & n2030; + assign n960_1 = ~n1388; + assign n1390 = n2027 & (~Pkey_234_ | n1138) & n2028; + assign n964_1 = ~n1390; + assign n1392 = n2025 & (~Pkey_242_ | n1138) & n2026; + assign n969 = ~n1392; + assign n1394 = n2023 & (~Pkey_250_ | n1138) & n2024; + assign n973 = ~n1394; + assign n1396 = n2021 & (~Pkey_193_ | n1138) & n2022; + assign n978_1 = ~n1396; + assign n1398 = n2019 & (~Pkey_201_ | n1138) & n2020; + assign n982_1 = ~n1398; + assign n1400 = n2017 & (~Pkey_209_ | n1138) & n2018; + assign n986_1 = ~n1400; + assign n1402 = n2015 & (~Pkey_217_ | n1138) & n2016; + assign n990_1 = ~n1402; + assign n1404 = n2013 & (~Pkey_225_ | n1138) & n2014; + assign n994_1 = ~n1404; + assign n1406 = n2011 & (~Pkey_233_ | n1138) & n2012; + assign n998_1 = ~n1406; + assign n1408 = n2009 & (~Pkey_241_ | n1138) & n2010; + assign n1002_1 = ~n1408; + assign n1410 = n2007 & (~Pkey_249_ | n1138) & n2008; + assign n1007 = ~n1410; + assign n1412 = n2005 & (~Pkey_192_ | n1138) & n2006; + assign n1011 = ~n1412; + assign n1414 = n2003 & (~Pkey_200_ | n1138) & n2004; + assign n1015 = ~n1414; + assign n1416 = n2001 & (~Pkey_208_ | n1138) & n2002; + assign n1019 = ~n1416; + assign n1418 = n1999 & (~Pkey_216_ | n1138) & n2000; + assign n1023 = ~n1418; + assign n1420 = n1997 & (~Pkey_224_ | n1138) & n1998; + assign n1027 = ~n1420; + assign n1422 = n1995 & (~Pkey_232_ | n1138) & n1996; + assign n1031 = ~n1422; + assign n1424 = n1993 & (~Pkey_240_ | n1138) & n1994; + assign n1035 = ~n1424; + assign n1426 = n1991 & (~Pkey_248_ | n1138) & n1992; + assign n1039 = ~n1426; + assign n1428 = n1989 & (~Pkey_163_ | n1138) & n1990; + assign n1043 = ~n1428; + assign n1430 = n1987 & (~Pkey_171_ | n1138) & n1988; + assign n1047 = ~n1430; + assign n1432 = n1985 & (~Pkey_179_ | n1138) & n1986; + assign n1051 = ~n1432; + assign n1434 = n1983 & (~Pkey_187_ | n1138) & n1984; + assign n1056_1 = ~n1434; + assign n1436 = n1981 & (~Pkey_130_ | n1138) & n1982; + assign n1060_1 = ~n1436; + assign n1438 = n1979 & (~Pkey_138_ | n1138) & n1980; + assign n1064_1 = ~n1438; + assign n1440 = n1977 & (~Pkey_146_ | n1138) & n1978; + assign n1069 = ~n1440; + assign n1442 = n1975 & (~Pkey_154_ | n1138) & n1976; + assign n1073 = ~n1442; + assign n1444 = n1973 & (~Pkey_162_ | n1138) & n1974; + assign n1077 = ~n1444; + assign n1446 = n1971 & (~Pkey_170_ | n1138) & n1972; + assign n1081 = ~n1446; + assign n1448 = n1969 & (~Pkey_178_ | n1138) & n1970; + assign n1086_1 = ~n1448; + assign n1450 = n1967 & (~Pkey_186_ | n1138) & n1968; + assign n1090_1 = ~n1450; + assign n1452 = n1965 & (~Pkey_129_ | n1138) & n1966; + assign n1094_1 = ~n1452; + assign n1454 = n1963 & (~Pkey_137_ | n1138) & n1964; + assign n1098_1 = ~n1454; + assign n1456 = n1961 & (~Pkey_145_ | n1138) & n1962; + assign n1102_1 = ~n1456; + assign n1458 = n1959 & (~Pkey_153_ | n1138) & n1960; + assign n1106_1 = ~n1458; + assign n1460 = n1957 & (~Pkey_161_ | n1138) & n1958; + assign n1110_1 = ~n1460; + assign n1462 = n1955 & (~Pkey_169_ | n1138) & n1956; + assign n1114_1 = ~n1462; + assign n1464 = n1953 & (~Pkey_177_ | n1138) & n1954; + assign n1118_1 = ~n1464; + assign n1466 = n1951 & (~Pkey_185_ | n1138) & n1952; + assign n1123 = ~n1466; + assign n1468 = n1949 & (~Pkey_128_ | n1138) & n1950; + assign n1127 = ~n1468; + assign n1470 = n1947 & (~Pkey_136_ | n1138) & n1948; + assign n1131 = ~n1470; + assign n1472 = n1945 & (~Pkey_144_ | n1138) & n1946; + assign n1135 = ~n1472; + assign n1474 = n1943 & (~Pkey_152_ | n1138) & n1944; + assign n1139 = ~n1474; + assign n1476 = n1941 & (~Pkey_160_ | n1138) & n1942; + assign n1143 = ~n1476; + assign n1478 = n1939 & (~Pkey_168_ | n1138) & n1940; + assign n1147 = ~n1478; + assign n1480 = n1937 & (~Pkey_176_ | n1138) & n1938; + assign n1151 = ~n1480; + assign n1482 = n1935 & (~Pkey_184_ | n1138) & n1936; + assign n1155 = ~n1482; + assign n1484 = n1933 & (~Pkey_99_ | n1138) & n1934; + assign n1159 = ~n1484; + assign n1486 = n1931 & (~Pkey_107_ | n1138) & n1932; + assign n1163 = ~n1486; + assign n1488 = n1929 & (~Pkey_115_ | n1138) & n1930; + assign n1167_1 = ~n1488; + assign n1490 = n1927 & (~Pkey_123_ | n1138) & n1928; + assign n1172 = ~n1490; + assign n1492 = n1925 & (~Pkey_66_ | n1138) & n1926; + assign n1176 = ~n1492; + assign n1494 = n1923 & (~Pkey_74_ | n1138) & n1924; + assign n1180 = ~n1494; + assign n1496 = n1921 & (~Pkey_82_ | n1138) & n1922; + assign n1185 = ~n1496; + assign n1498 = n1919 & (~Pkey_90_ | n1138) & n1920; + assign n1189 = ~n1498; + assign n1500 = n1917 & (~Pkey_98_ | n1138) & n1918; + assign n1193 = ~n1500; + assign n1502 = n1915 & (~Pkey_106_ | n1138) & n1916; + assign n1197 = ~n1502; + assign n1504 = n1913 & (~Pkey_114_ | n1138) & n1914; + assign n1202 = ~n1504; + assign n1506 = n1911 & (~Pkey_122_ | n1138) & n1912; + assign n1206 = ~n1506; + assign n1508 = n1909 & (~Pkey_65_ | n1138) & n1910; + assign n1210 = ~n1508; + assign n1510 = n1907 & (~Pkey_73_ | n1138) & n1908; + assign n1214 = ~n1510; + assign n1512 = n1905 & (~Pkey_81_ | n1138) & n1906; + assign n1218 = ~n1512; + assign n1514 = n1903 & (~Pkey_89_ | n1138) & n1904; + assign n1222 = ~n1514; + assign n1516 = n1901 & (~Pkey_97_ | n1138) & n1902; + assign n1226 = ~n1516; + assign n1518 = n1899 & (~Pkey_105_ | n1138) & n1900; + assign n1230 = ~n1518; + assign n1520 = n1897 & (~Pkey_113_ | n1138) & n1898; + assign n1234 = ~n1520; + assign n1522 = n1895 & (~Pkey_121_ | n1138) & n1896; + assign n1239 = ~n1522; + assign n1524 = n1893 & (~Pkey_64_ | n1138) & n1894; + assign n1243 = ~n1524; + assign n1526 = n1891 & (~Pkey_72_ | n1138) & n1892; + assign n1247 = ~n1526; + assign n1528 = n1889 & (~Pkey_80_ | n1138) & n1890; + assign n1251 = ~n1528; + assign n1530 = n1887 & (~Pkey_88_ | n1138) & n1888; + assign n1255 = ~n1530; + assign n1532 = n1885 & (~Pkey_96_ | n1138) & n1886; + assign n1259 = ~n1532; + assign n1534 = n1883 & (~Pkey_104_ | n1138) & n1884; + assign n1263 = ~n1534; + assign n1536 = n1881 & (~Pkey_112_ | n1138) & n1882; + assign n1267 = ~n1536; + assign n1538 = n1879 & (~Pkey_120_ | n1138) & n1880; + assign n1271 = ~n1538; + assign n1540 = n1877 & (~Pkey_35_ | n1138) & n1878; + assign n1275 = ~n1540; + assign n1542 = n1875 & (~Pkey_43_ | n1138) & n1876; + assign n1279 = ~n1542; + assign n1544 = n1873 & (~Pkey_51_ | n1138) & n1874; + assign n1283 = ~n1544; + assign n1546 = n1871 & (~Pkey_59_ | n1138) & n1872; + assign n1288 = ~n1546; + assign n1548 = n1869 & (~Pkey_2_ | n1138) & n1870; + assign n1292_1 = ~n1548; + assign n1550 = n1867 & (~Pkey_10_ | n1138) & n1868; + assign n1296_1 = ~n1550; + assign n1552 = n1865 & (~Pkey_18_ | n1138) & n1866; + assign n1301_1 = ~n1552; + assign n1554 = n1863 & (~Pkey_26_ | n1138) & n1864; + assign n1305_1 = ~n1554; + assign n1556 = n1861 & (~Pkey_34_ | n1138) & n1862; + assign n1309_1 = ~n1556; + assign n1558 = n1859 & (~Pkey_42_ | n1138) & n1860; + assign n1313_1 = ~n1558; + assign n1560 = n1857 & (~Pkey_50_ | n1138) & n1858; + assign n1318_1 = ~n1560; + assign n1562 = n1855 & (~Pkey_58_ | n1138) & n1856; + assign n1322_1 = ~n1562; + assign n1564 = n1853_1 & (~Pkey_1_ | n1138) & n1854; + assign n1326_1 = ~n1564; + assign n1566 = n1851 & (~Pkey_9_ | n1138) & n1852; + assign n1330_1 = ~n1566; + assign n1568 = n1849_1 & (~Pkey_17_ | n1138) & n1850; + assign n1334_1 = ~n1568; + assign n1570 = n1847 & (~Pkey_25_ | n1138) & n1848; + assign n1338_1 = ~n1570; + assign n1572 = n1845_1 & (~Pkey_33_ | n1138) & n1846; + assign n1342_1 = ~n1572; + assign n1574 = n1843 & (~Pkey_41_ | n1138) & n1844; + assign n1346_1 = ~n1574; + assign n1576 = n1841_1 & (~Pkey_49_ | n1138) & n1842; + assign n1350_1 = ~n1576; + assign n1578 = n1839 & (~Pkey_57_ | n1138) & n1840; + assign n1355_1 = ~n1578; + assign n1580 = n1837_1 & (~Pkey_0_ | n1138) & n1838; + assign n1359_1 = ~n1580; + assign n1582 = n1835 & (~Pkey_8_ | n1138) & n1836; + assign n1363_1 = ~n1582; + assign n1584 = n1833_1 & (~Pkey_16_ | n1138) & n1834; + assign n1367_1 = ~n1584; + assign n1586 = n1831 & (~Pkey_24_ | n1138) & n1832; + assign n1371_1 = ~n1586; + assign n1588 = n1829 & (~Pkey_32_ | n1138) & n1830; + assign n1375_1 = ~n1588; + assign n1590 = n1827 & (~Pkey_40_ | n1138) & n1828; + assign n1379_1 = ~n1590; + assign n1592 = n1825 & (~Pkey_48_ | n1138) & n1826; + assign n1383_1 = ~n1592; + assign n1594 = Pcount_3_ | Pcount_1_ | Pcount_2_; + assign n1595 = Pcount_0_ | Pcount_1_ | Pcount_2_; + assign n1596 = ~Pcount_2_ | ~Pcount_1_ | ~Pcount_0_; + assign n1597 = n1594 & n1595 & (~Pcount_3_ | n1596); + assign n1598 = ~Pcount_3_ | ~Pcount_2_ | ~Pcount_1_ | Pcount_0_; + assign n1599 = Pcount_3_ | n1596; + assign n1600 = n1598 & n1599 & (Pcount_3_ | n1595); + assign n1601 = n2179 & (~PKSi_118_ | ~PKSi_4_ | n2172); + assign n1602 = (~Pkey_62_ | n1137) & n2180; + assign n1603 = n2181 & (~PKSi_102_ | ~PKSi_23_ | n2172); + assign n1604 = (~Pkey_54_ | n1137) & n2182; + assign n1605 = n2183 & (~PKSi_98_ | ~PKSi_6_ | n2172); + assign n1606 = (~Pkey_46_ | n1137) & n2184; + assign n1607 = n2185 & (~PKSi_119_ | ~PKSi_15_ | n2172); + assign n1608 = (~Pkey_38_ | n1137) & n2186; + assign n1609 = n2187 & (~PKSi_106_ | ~PKSi_5_ | n2172); + assign n1610 = (~Pkey_30_ | n1137) & n2188; + assign n1611 = n2189 & (~PKSi_112_ | ~PKSi_9_ | n2172); + assign n1612 = (~Pkey_22_ | n1137) & n2190; + assign n1613 = n2191 & (~PKSi_19_ | ~N_N2986 | n2172); + assign n1614 = (~Pkey_14_ | n1137) & n2192; + assign n1615 = n2193 & (~PKSi_117_ | ~PKSi_17_ | n2172); + assign n1616 = (~Pkey_6_ | n1137) & n2194; + assign n1617 = n2195 & (~PKSi_99_ | n2172 | ~N_N2853); + assign n1618 = (~Pkey_61_ | n1137) & n2196; + assign n1619 = n2197 & (~PKSi_11_ | ~N_N2982 | n2172); + assign n1620 = (~Pkey_53_ | n1137) & n2198; + assign n1621 = n2199 & (~PKSi_110_ | ~PKSi_2_ | n2172); + assign n1622 = (~Pkey_45_ | n1137) & n2200; + assign n1623 = n2201 & (~PKSi_103_ | ~PKSi_14_ | n2172); + assign n1624 = (~Pkey_37_ | n1137) & n2202; + assign n1625 = n2203 & (~PKSi_96_ | ~PKSi_22_ | n2172); + assign n1626 = (~Pkey_29_ | n1137) & n2204; + assign n1627 = n2205 & (~PKSi_115_ | ~PKSi_0_ | n2172); + assign n1628 = (~Pkey_21_ | n1137) & n2206; + assign n1629 = n2207 & (~PKSi_8_ | ~N_N2976 | n2172); + assign n1630 = (~Pkey_13_ | n1137) & n2208; + assign n1631 = n2209 & (~PKSi_108_ | ~PKSi_18_ | n2172); + assign n1632 = (~Pkey_5_ | n1137) & n2210; + assign n1633 = n2211 & (~PKSi_105_ | ~PKSi_1_ | n2172); + assign n1634 = (~Pkey_60_ | n1137) & n2212; + assign n1635 = n2213 & (~PKSi_114_ | n2172 | ~N_N2843); + assign n1636 = (~Pkey_52_ | n1137) & n2214; + assign n1637 = n2215 & (~PKSi_100_ | ~PKSi_13_ | n2172); + assign n1638 = (~Pkey_44_ | n1137) & n2216; + assign n1639 = n2217 & (~PKSi_107_ | ~PKSi_21_ | n2172); + assign n1640 = (~Pkey_36_ | n1137) & n2218; + assign n1641 = n2219 & (~PKSi_109_ | ~PKSi_10_ | n2172); + assign n1642 = (~Pkey_28_ | n1137) & n2220; + assign n1643 = n2221 & (~PKSi_116_ | n2172 | ~N_N2838); + assign n1644 = (~Pkey_20_ | n1137) & n2222; + assign n1645 = n2223 & (~PKSi_104_ | ~PKSi_12_ | n2172); + assign n1646 = (~Pkey_12_ | n1137) & n2224; + assign n1647 = n2225 & (~PKSi_97_ | ~PKSi_3_ | n2172); + assign n1648 = (~Pkey_4_ | n1137) & n2226; + assign n1649 = n2227 & (~PKSi_113_ | n2172 | ~N_N2834); + assign n1650 = (~Pkey_27_ | n1137) & n2228; + assign n1651 = n2229 & (~PKSi_16_ | ~N_N2964 | n2172); + assign n1652 = (~Pkey_19_ | n1137) & n2230; + assign n1653 = n2231 & (~PKSi_101_ | ~PKSi_20_ | n2172); + assign n1654 = (~Pkey_11_ | n1137) & n2232; + assign n1655 = n2233 & (~PKSi_111_ | ~PKSi_7_ | n2172); + assign n1656 = (~Pkey_3_ | n1137) & n2234; + assign n1657 = n2235 & (~PKSi_142_ | ~PKSi_28_ | n2172); + assign n1658 = (~Pkey_126_ | n1137) & n2236; + assign n1659 = n2237 & (~PKSi_126_ | ~PKSi_47_ | n2172); + assign n1660 = (~Pkey_118_ | n1137) & n2238; + assign n1661 = n2239 & (~PKSi_122_ | ~PKSi_30_ | n2172); + assign n1662 = (~Pkey_110_ | n1137) & n2240; + assign n1663 = n2241 & (~\[282] | ~PKSi_39_ | n2172); + assign n1664 = (~Pkey_102_ | n1137) & n2242; + assign n1665 = n2243 & (~PKSi_130_ | ~PKSi_29_ | n2172); + assign n1666 = (~Pkey_94_ | n1137) & n2244; + assign n1667 = n2245 & (~PKSi_136_ | ~PKSi_33_ | n2172); + assign n1668 = (~Pkey_86_ | n1137) & n2246; + assign n1669 = n2247 & (~PKSi_43_ | ~N_N2954 | n2172); + assign n1670 = (~Pkey_78_ | n1137) & n2248; + assign n1671 = n2249 & (~PKSi_141_ | ~PKSi_41_ | n2172); + assign n1672 = (~Pkey_70_ | n1137) & n2250; + assign n1673 = n2251 & (~PKSi_123_ | n2172 | ~N_N2821); + assign n1674 = (~Pkey_125_ | n1137) & n2252; + assign n1675 = n2253 & (~PKSi_35_ | ~N_N2950 | n2172); + assign n1676 = (~Pkey_117_ | n1137) & n2254; + assign n1677 = n2255 & (~PKSi_134_ | ~PKSi_26_ | n2172); + assign n1678 = (~Pkey_109_ | n1137) & n2256; + assign n1679 = n2257 & (~PKSi_127_ | ~PKSi_38_ | n2172); + assign n1680 = (~Pkey_101_ | n1137) & n2258; + assign n1681 = n2259 & (~PKSi_120_ | ~PKSi_46_ | n2172); + assign n1682 = (~Pkey_93_ | n1137) & n2260; + assign n1683 = n2261 & (~PKSi_24_ | ~N_N2945 | n2172); + assign n1684 = (~Pkey_85_ | n1137) & n2262; + assign n1685 = n2263 & (~PKSi_32_ | ~N_N2943 | n2172); + assign n1686 = (~Pkey_77_ | n1137) & n2264; + assign n1687 = n2265 & (~PKSi_132_ | ~PKSi_42_ | n2172); + assign n1688 = (~Pkey_69_ | n1137) & n2266; + assign n1689 = n2267 & (~PKSi_129_ | ~PKSi_25_ | n2172); + assign n1690 = (~Pkey_124_ | n1137) & n2268; + assign n1691 = n2269 & (~PKSi_138_ | n2172 | ~N_N2811); + assign n1692 = (~Pkey_116_ | n1137) & n2270; + assign n1693 = n2271 & (~PKSi_124_ | ~PKSi_37_ | n2172); + assign n1694 = (~Pkey_44_ | n1137) & n2272; + assign n1695 = n2273 & (~PKSi_131_ | ~PKSi_45_ | n2172); + assign n1696 = (~Pkey_100_ | n1137) & n2274; + assign n1697 = n2275 & (~PKSi_133_ | ~PKSi_34_ | n2172); + assign n1698 = (~Pkey_92_ | n1137) & n2276; + assign n1699 = n2277 & (~PKSi_140_ | n2172 | ~N_N2806); + assign n1700 = (~Pkey_84_ | n1137) & n2278; + assign n1701 = n2279 & (~PKSi_128_ | ~PKSi_36_ | n2172); + assign n1702 = (~Pkey_76_ | n1137) & n2280; + assign n1703 = n2281 & (~PKSi_121_ | ~PKSi_27_ | n2172); + assign n1704 = (~Pkey_68_ | n1137) & n2282; + assign n1705 = n2283 & (~PKSi_137_ | n2172 | ~N_N2802); + assign n1706 = (~Pkey_91_ | n1137) & n2284; + assign n1707 = n2285 & (~PKSi_40_ | ~N_N2931 | n2172); + assign n1708 = (~Pkey_83_ | n1137) & n2286; + assign n1709 = n2287 & (~PKSi_125_ | ~PKSi_44_ | n2172); + assign n1710 = (~Pkey_75_ | n1137) & n2288; + assign n1711 = n2289 & (~PKSi_135_ | ~PKSi_31_ | n2172); + assign n1712 = (~Pkey_67_ | n1137) & n2290; + assign n1713 = n2291 & (~PKSi_166_ | ~PKSi_52_ | n2172); + assign n1714 = (~Pkey_190_ | n1137) & n2292; + assign n1715 = n2293 & (~PKSi_150_ | ~PKSi_71_ | n2172); + assign n1716 = (~Pkey_182_ | n1137) & n2294; + assign n1717 = n2295 & (~PKSi_146_ | ~PKSi_54_ | n2172); + assign n1718 = (~Pkey_174_ | n1137) & n2296; + assign n1719 = n2297 & (~PKSi_167_ | ~PKSi_63_ | n2172); + assign n1720 = (~Pkey_166_ | n1137) & n2298; + assign n1721 = n2299 & (~PKSi_154_ | ~PKSi_53_ | n2172); + assign n1722 = (~Pkey_158_ | n1137) & n2300; + assign n1723 = n2301 & (~PKSi_160_ | ~PKSi_57_ | n2172); + assign n1724 = (~Pkey_150_ | n1137) & n2302; + assign n1725 = n2303 & (~PKSi_67_ | ~N_N2921 | n2172); + assign n1726 = (~Pkey_142_ | n1137) & n2304; + assign n1727 = n2305 & (~PKSi_165_ | ~PKSi_65_ | n2172); + assign n1728 = (~Pkey_134_ | n1137) & n2306; + assign n1729 = n2307 & (~PKSi_147_ | n2172 | ~N_N2789); + assign n1730 = (~Pkey_189_ | n1137) & n2308; + assign n1731 = n2309 & (~PKSi_59_ | ~N_N2917 | n2172); + assign n1732 = (~Pkey_181_ | n1137) & n2310; + assign n1733 = n2311 & (~PKSi_158_ | ~PKSi_50_ | n2172); + assign n1734 = (~Pkey_173_ | n1137) & n2312; + assign n1735 = n2313 & (~PKSi_151_ | ~PKSi_62_ | n2172); + assign n1736 = (~Pkey_165_ | n1137) & n2314; + assign n1737 = n2315 & (~PKSi_144_ | ~PKSi_70_ | n2172); + assign n1738 = (~Pkey_157_ | n1137) & n2316; + assign n1739 = n2317 & (~PKSi_163_ | ~PKSi_48_ | n2172); + assign n1740 = (~Pkey_149_ | n1137) & n2318; + assign n1741 = n2319 & (~PKSi_153_ | ~PKSi_56_ | n2172); + assign n1742 = (~Pkey_141_ | n1137) & n2320; + assign n1743 = n2321 & (~PKSi_156_ | ~PKSi_66_ | n2172); + assign n1744 = (~Pkey_133_ | n1137) & n2322; + assign n1745_1 = n2323 & (~PKSi_49_ | ~N_N2909 | n2172); + assign n1746 = (~Pkey_188_ | n1137) & n2324; + assign n1747 = n2325 & (~PKSi_162_ | n2172 | ~N_N2779); + assign n1748 = (~Pkey_180_ | n1137) & n2326; + assign n1749_1 = n2327 & (~PKSi_148_ | ~PKSi_61_ | n2172); + assign n1750 = (~Pkey_172_ | n1137) & n2328; + assign n1751 = n2329 & (~PKSi_155_ | ~PKSi_69_ | n2172); + assign n1752 = (~Pkey_164_ | n1137) & n2330; + assign n1753 = n2331 & (~PKSi_157_ | ~PKSi_58_ | n2172); + assign n1754 = (~Pkey_156_ | n1137) & n2332; + assign n1755 = n2333 & (~PKSi_164_ | n2172 | ~N_N2774); + assign n1756 = (~Pkey_148_ | n1137) & n2334; + assign n1757 = n2335 & (~PKSi_152_ | ~PKSi_60_ | n2172); + assign n1758 = (~Pkey_140_ | n1137) & n2336; + assign n1759 = n2337 & (~PKSi_145_ | ~PKSi_51_ | n2172); + assign n1760 = (~Pkey_132_ | n1137) & n2338; + assign n1761 = n2339 & (~PKSi_161_ | n2172 | ~N_N2770); + assign n1762 = (~Pkey_155_ | n1137) & n2340; + assign n1763 = n2341 & (~PKSi_64_ | ~N_N2899 | n2172); + assign n1764 = (~Pkey_147_ | n1137) & n2342; + assign n1765 = n2343 & (~PKSi_149_ | ~PKSi_68_ | n2172); + assign n1766 = (~Pkey_139_ | n1137) & n2344; + assign n1767 = n2345 & (~PKSi_159_ | ~PKSi_55_ | n2172); + assign n1768 = (~Pkey_131_ | n1137) & n2346; + assign n1769 = n2347 & (~PKSi_190_ | ~PKSi_76_ | n2172); + assign n1770 = (~Pkey_254_ | n1137) & n2348; + assign n1771 = n2349 & (~PKSi_174_ | ~PKSi_95_ | n2172); + assign n1772 = (~Pkey_246_ | n1137) & n2350; + assign n1773 = n2351 & (~PKSi_170_ | ~PKSi_78_ | n2172); + assign n1774 = (~Pkey_238_ | n1137) & n2352; + assign n1775 = n2353 & (~\[234] | ~PKSi_87_ | n2172); + assign n1776 = (~Pkey_230_ | n1137) & n2354; + assign n1777 = n2355 & (~PKSi_178_ | ~PKSi_77_ | n2172); + assign n1778 = (~Pkey_222_ | n1137) & n2356; + assign n1779 = n2357 & (~PKSi_184_ | ~PKSi_81_ | n2172); + assign n1780 = (~Pkey_214_ | n1137) & n2358; + assign n1781 = n2359 & (~PKSi_91_ | ~N_N2889 | n2172); + assign n1782 = (~Pkey_206_ | n1137) & n2360; + assign n1783 = n2361 & (~PKSi_189_ | ~PKSi_89_ | n2172); + assign n1784 = (~Pkey_198_ | n1137) & n2362; + assign n1785 = n2363 & (~PKSi_171_ | n2172 | ~N_N2757); + assign n1786 = (~Pkey_253_ | n1137) & n2364; + assign n1787 = n2365 & (~PKSi_83_ | ~N_N2885 | n2172); + assign n1788 = (~Pkey_245_ | n1137) & n2366; + assign n1789 = n2367 & (~PKSi_182_ | ~PKSi_74_ | n2172); + assign n1790 = (~Pkey_237_ | n1137) & n2368; + assign n1791 = n2369 & (~PKSi_175_ | ~PKSi_86_ | n2172); + assign n1792 = (~Pkey_229_ | n1137) & n2370; + assign n1793 = n2371 & (~PKSi_94_ | ~N_N2881 | n2172); + assign n1794 = (~Pkey_221_ | n1137) & n2372; + assign n1795 = n2373 & (~PKSi_72_ | ~N_N2879 | n2172); + assign n1796 = (~Pkey_213_ | n1137) & n2374; + assign n1797 = n2375 & (~PKSi_80_ | ~N_N2877 | n2172); + assign n1798 = (~Pkey_205_ | n1137) & n2376; + assign n1799_1 = n2377 & (~PKSi_180_ | n2172 | ~N_N2749); + assign n1800 = (~Pkey_197_ | n1137) & n2378; + assign n1801 = n2379 & (~PKSi_177_ | ~PKSi_73_ | n2172); + assign n1802 = (~Pkey_252_ | n1137) & n2380; + assign n1803_1 = n2381 & (~PKSi_186_ | n2172 | ~N_N2746); + assign n1804 = (~Pkey_244_ | n1137) & n2382; + assign n1805 = n2383 & (~PKSi_172_ | ~PKSi_85_ | n2172); + assign n1806 = (~Pkey_172_ | n1137) & n2384; + assign n1807_1 = n2385 & (~PKSi_179_ | ~PKSi_93_ | n2172); + assign n1808 = (~Pkey_228_ | n1137) & n2386; + assign n1809 = n2387 & (~\[253] | ~PKSi_82_ | n2172); + assign n1810 = (~Pkey_220_ | n1137) & n2388; + assign n1811_1 = n2389 & (~PKSi_188_ | n2172 | ~N_N2741); + assign n1812 = (~Pkey_212_ | n1137) & n2390; + assign n1813 = n2391 & (~PKSi_176_ | ~PKSi_84_ | n2172); + assign n1814 = (~Pkey_204_ | n1137) & n2392; + assign n1815_1 = n2393 & (~PKSi_169_ | ~PKSi_75_ | n2172); + assign n1816 = (~Pkey_196_ | n1137) & n2394; + assign n1817 = n2395 & (~PKSi_185_ | n2172 | ~N_N2737); + assign n1818 = (~Pkey_219_ | n1137) & n2396; + assign n1819 = n2397 & (~\[333] | ~N_N2865 | n2172); + assign n1820 = (~Pkey_211_ | n1137) & n2398; + assign n1821 = n2399 & (~PKSi_173_ | ~PKSi_92_ | n2172); + assign n1822 = (~Pkey_203_ | n1137) & n2400; + assign n1823 = n2401 & (~PKSi_183_ | ~PKSi_79_ | n2172); + assign n1824 = (~Pkey_195_ | n1137) & n2402; + assign n1825 = (n2059 | n2176) & (~n2175 | n2403); + assign n1826 = (~Pkey_56_ | n1137) & n2404; + assign n1827 = (n2060 | n2176) & (~n2175 | n2405); + assign n1828 = (~Pkey_48_ | n1137) & n2406; + assign n1829 = (n2061 | n2176) & (~n2175 | n2407); + assign n1830 = (~Pkey_40_ | n1137) & n2408; + assign n1831 = (n2062 | n2176) & (~n2175 | n2409); + assign n1832 = (~Pkey_32_ | n1137) & n2410; + assign n1833_1 = (n2063 | n2176) & (~n2175 | n2411); + assign n1834 = (~Pkey_24_ | n1137) & n2412; + assign n1835 = (n2064 | n2176) & (~n2175 | n2413); + assign n1836 = (~Pkey_16_ | n1137) & n2414; + assign n1837_1 = (n2065 | n2176) & (~n2175 | n2415); + assign n1838 = (~Pkey_8_ | n1137) & n2416; + assign n1839 = (n2066 | n2176) & (~n2175 | n2417); + assign n1840 = (~Pkey_0_ | n1137) & n2418; + assign n1841_1 = (n2067 | n2176) & (~n2175 | n2419); + assign n1842 = (~Pkey_57_ | n1137) & n2420; + assign n1843 = (n2068 | n2176) & (~n2175 | n2421); + assign n1844 = (~Pkey_49_ | n1137) & n2422; + assign n1845_1 = (n2069 | n2176) & (~n2175 | n2423); + assign n1846 = (~Pkey_41_ | n1137) & n2424; + assign n1847 = (n2070 | n2176) & (~n2175 | n2425); + assign n1848 = (~Pkey_33_ | n1137) & n2426; + assign n1849_1 = (n2071 | n2176) & (~n2175 | n2427); + assign n1850 = (~Pkey_25_ | n1137) & n2428; + assign n1851 = (n2072 | n2176) & (~n2175 | n2429); + assign n1852 = (~Pkey_17_ | n1137) & n2430; + assign n1853_1 = (n2073 | n2176) & (~n2175 | n2431); + assign n1854 = (~Pkey_9_ | n1137) & n2432; + assign n1855 = (n2074 | n2176) & (~n2175 | n2433); + assign n1856 = (~Pkey_1_ | n1137) & n2434; + assign n1857 = (n2075 | n2176) & (~n2175 | n2435); + assign n1858 = (~Pkey_58_ | n1137) & n2436; + assign n1859 = (n2076 | n2176) & (~n2175 | n2437); + assign n1860 = (~Pkey_50_ | n1137) & n2438; + assign n1861 = (n2077 | n2176) & (~n2175 | n2439); + assign n1862 = (~Pkey_42_ | n1137) & n2440; + assign n1863 = (n2078 | n2176) & (~n2175 | n2441); + assign n1864 = (~Pkey_34_ | n1137) & n2442; + assign n1865 = (n2079 | n2176) & (~n2175 | n2443); + assign n1866 = (~Pkey_26_ | n1137) & n2444; + assign n1867 = (n2080 | n2176) & (~n2175 | n2445); + assign n1868 = (~Pkey_18_ | n1137) & n2446; + assign n1869 = (n2081 | n2176) & (~n2175 | n2447); + assign n1870 = (~Pkey_10_ | n1137) & n2448; + assign n1871 = (n2082 | n2176) & (~n2175 | n2449); + assign n1872 = (~Pkey_2_ | n1137) & n2450; + assign n1873 = (n2083 | n2176) & (~n2175 | n2451); + assign n1874 = (~Pkey_59_ | n1137) & n2452; + assign n1875 = (n2084 | n2176) & (~n2175 | n2453); + assign n1876 = (~Pkey_51_ | n1137) & n2454; + assign n1877 = (n2085 | n2176) & (~n2175 | n2455); + assign n1878 = (~Pkey_43_ | n1137) & n2456; + assign n1879 = (n2086 | n2176) & (~n2175 | n2457); + assign n1880 = (~Pkey_35_ | n1137) & n2458; + assign n1881 = (n2087 | n2176) & (~n2175 | n2459); + assign n1882 = (~Pkey_120_ | n1137) & n2460; + assign n1883 = (n2088 | n2176) & (~n2175 | n2461); + assign n1884 = (~Pkey_112_ | n1137) & n2462; + assign n1885 = (n2089 | n2176) & (~n2175 | n2463); + assign n1886 = (~Pkey_104_ | n1137) & n2464; + assign n1887 = (n2090 | n2176) & (~n2175 | n2465); + assign n1888 = (~Pkey_96_ | n1137) & n2466; + assign n1889 = (n2091 | n2176) & (~n2175 | n2467); + assign n1890 = (~Pkey_88_ | n1137) & n2468; + assign n1891 = (n2092 | n2176) & (~n2175 | n2469); + assign n1892 = (~Pkey_80_ | n1137) & n2470; + assign n1893 = (n2093 | n2176) & (~n2175 | n2471); + assign n1894 = (~Pkey_72_ | n1137) & n2472; + assign n1895 = (n2094 | n2176) & (~n2175 | n2473); + assign n1896 = (~Pkey_64_ | n1137) & n2474; + assign n1897 = (n2095 | n2176) & (~n2175 | n2475); + assign n1898 = (~Pkey_121_ | n1137) & n2476; + assign n1899 = (n2096 | n2176) & (~n2175 | n2477); + assign n1900 = (~Pkey_113_ | n1137) & n2478; + assign n1901 = (n2097 | n2176) & (~n2175 | n2479); + assign n1902 = (~Pkey_105_ | n1137) & n2480; + assign n1903 = (n2098 | n2176) & (~n2175 | n2481); + assign n1904 = (~Pkey_97_ | n1137) & n2482; + assign n1905 = (n2099 | n2176) & (~n2175 | n2483); + assign n1906 = (~Pkey_89_ | n1137) & n2484; + assign n1907 = (n2100 | n2176) & (~n2175 | n2485); + assign n1908 = (~Pkey_81_ | n1137) & n2486; + assign n1909 = (n2101 | n2176) & (~n2175 | n2487); + assign n1910 = (~Pkey_73_ | n1137) & n2488; + assign n1911 = (n2102 | n2176) & (~n2175 | n2489); + assign n1912 = (~Pkey_65_ | n1137) & n2490; + assign n1913 = (n2103 | n2176) & (~n2175 | n2491); + assign n1914 = (~Pkey_122_ | n1137) & n2492; + assign n1915 = (n2104 | n2176) & (~n2175 | n2493); + assign n1916 = (~Pkey_114_ | n1137) & n2494; + assign n1917 = (n2105 | n2176) & (~n2175 | n2495); + assign n1918 = (~Pkey_106_ | n1137) & n2496; + assign n1919 = (n2106 | n2176) & (~n2175 | n2497); + assign n1920 = (~Pkey_98_ | n1137) & n2498; + assign n1921 = (n2107 | n2176) & (~n2175 | n2499); + assign n1922 = (~Pkey_90_ | n1137) & n2500; + assign n1923 = (n2108 | n2176) & (~n2175 | n2501); + assign n1924 = (~Pkey_82_ | n1137) & n2502; + assign n1925 = (n2109 | n2176) & (~n2175 | n2503); + assign n1926 = (~Pkey_74_ | n1137) & n2504; + assign n1927 = (n2110 | n2176) & (~n2175 | n2505); + assign n1928 = (~Pkey_66_ | n1137) & n2506; + assign n1929 = (n2111 | n2176) & (~n2175 | n2507); + assign n1930 = (~Pkey_123_ | n1137) & n2508; + assign n1931 = (n2112 | n2176) & (~n2175 | n2509); + assign n1932 = (~Pkey_115_ | n1137) & n2510; + assign n1933 = (n2113 | n2176) & (~n2175 | n2511); + assign n1934 = (~Pkey_107_ | n1137) & n2512; + assign n1935 = (n2114 | n2176) & (~n2175 | n2513); + assign n1936 = (~Pkey_99_ | n1137) & n2514; + assign n1937 = (n2115 | n2176) & (~n2175 | n2515); + assign n1938 = (~Pkey_184_ | n1137) & n2516; + assign n1939 = (n2116 | n2176) & (~n2175 | n2517); + assign n1940 = (~Pkey_176_ | n1137) & n2518; + assign n1941 = (n2117 | n2176) & (~n2175 | n2519); + assign n1942 = (~Pkey_168_ | n1137) & n2520; + assign n1943 = (n2118 | n2176) & (~n2175 | n2521); + assign n1944 = (~Pkey_160_ | n1137) & n2522; + assign n1945 = (n2119 | n2176) & (~n2175 | n2523); + assign n1946 = (~Pkey_152_ | n1137) & n2524; + assign n1947 = (n2120 | n2176) & (~n2175 | n2525); + assign n1948 = (~Pkey_144_ | n1137) & n2526; + assign n1949 = (n2121 | n2176) & (~n2175 | n2527); + assign n1950 = (~Pkey_136_ | n1137) & n2528; + assign n1951 = (n2122 | n2176) & (~n2175 | n2529); + assign n1952 = (~Pkey_128_ | n1137) & n2530; + assign n1953 = (n2123 | n2176) & (~n2175 | n2531); + assign n1954 = (~Pkey_185_ | n1137) & n2532; + assign n1955 = (n2124 | n2176) & (~n2175 | n2533); + assign n1956 = (~Pkey_177_ | n1137) & n2534; + assign n1957 = (n2125 | n2176) & (~n2175 | n2535); + assign n1958 = (~Pkey_169_ | n1137) & n2536; + assign n1959 = (n2126 | n2176) & (~n2175 | n2537); + assign n1960 = (~Pkey_161_ | n1137) & n2538; + assign n1961 = (n2127 | n2176) & (~n2175 | n2539); + assign n1962 = (~Pkey_153_ | n1137) & n2540; + assign n1963 = (n2128 | n2176) & (~n2175 | n2541); + assign n1964 = (~Pkey_145_ | n1137) & n2542; + assign n1965 = (n2129 | n2176) & (~n2175 | n2543); + assign n1966 = (~Pkey_137_ | n1137) & n2544; + assign n1967 = (n2130 | n2176) & (~n2175 | n2545); + assign n1968 = (~Pkey_129_ | n1137) & n2546; + assign n1969 = (n2131 | n2176) & (~n2175 | n2547); + assign n1970 = (~Pkey_186_ | n1137) & n2548; + assign n1971 = (n2132 | n2176) & (~n2175 | n2549); + assign n1972 = (~Pkey_178_ | n1137) & n2550; + assign n1973 = (n2133 | n2176) & (~n2175 | n2551); + assign n1974 = (~Pkey_170_ | n1137) & n2552; + assign n1975 = (n2134 | n2176) & (~n2175 | n2553); + assign n1976 = (~Pkey_162_ | n1137) & n2554; + assign n1977 = (n2135 | n2176) & (~n2175 | n2555); + assign n1978 = (~Pkey_154_ | n1137) & n2556; + assign n1979 = (n2136 | n2176) & (~n2175 | n2557); + assign n1980 = (~Pkey_146_ | n1137) & n2558; + assign n1981 = (n2137 | n2176) & (~n2175 | n2559); + assign n1982 = (~Pkey_138_ | n1137) & n2560; + assign n1983 = (n2138 | n2176) & (~n2175 | n2561); + assign n1984 = (~Pkey_130_ | n1137) & n2562; + assign n1985 = (n2139 | n2176) & (~n2175 | n2563); + assign n1986 = (~Pkey_187_ | n1137) & n2564; + assign n1987 = (n2140 | n2176) & (~n2175 | n2565); + assign n1988 = (~Pkey_179_ | n1137) & n2566; + assign n1989 = (n2141 | n2176) & (~n2175 | n2567); + assign n1990 = (~Pkey_171_ | n1137) & n2568; + assign n1991 = (n2142 | n2176) & (~n2175 | n2569); + assign n1992 = (~Pkey_163_ | n1137) & n2570; + assign n1993 = (n2143 | n2176) & (~n2175 | n2571); + assign n1994 = (~Pkey_248_ | n1137) & n2572; + assign n1995 = (n2144 | n2176) & (~n2175 | n2573); + assign n1996 = (~Pkey_240_ | n1137) & n2574; + assign n1997 = (n2145 | n2176) & (~n2175 | n2575); + assign n1998 = (~Pkey_232_ | n1137) & n2576; + assign n1999 = (n2146 | n2176) & (~n2175 | n2577); + assign n2000 = (~Pkey_224_ | n1137) & n2578; + assign n2001 = (n2147 | n2176) & (~n2175 | n2579); + assign n2002 = (~Pkey_216_ | n1137) & n2580; + assign n2003 = (n2148 | n2176) & (~n2175 | n2581); + assign n2004 = (~Pkey_208_ | n1137) & n2582; + assign n2005 = (n2149 | n2176) & (~n2175 | n2583); + assign n2006 = (~Pkey_200_ | n1137) & n2584; + assign n2007 = (n2150 | n2176) & (~n2175 | n2585); + assign n2008 = (~Pkey_192_ | n1137) & n2586; + assign n2009 = (n2151 | n2176) & (~n2175 | n2587); + assign n2010 = (~Pkey_249_ | n1137) & n2588; + assign n2011 = (n2152 | n2176) & (~n2175 | n2589); + assign n2012 = (~Pkey_241_ | n1137) & n2590; + assign n2013 = (n2153 | n2176) & (~n2175 | n2591); + assign n2014 = (~Pkey_233_ | n1137) & n2592; + assign n2015 = (n2154 | n2176) & (~n2175 | n2593); + assign n2016 = (~Pkey_225_ | n1137) & n2594; + assign n2017 = (n2155 | n2176) & (~n2175 | n2595); + assign n2018 = (~Pkey_217_ | n1137) & n2596; + assign n2019 = (n2156 | n2176) & (~n2175 | n2597); + assign n2020 = (~Pkey_209_ | n1137) & n2598; + assign n2021 = (n2157 | n2176) & (~n2175 | n2599); + assign n2022 = (~Pkey_201_ | n1137) & n2600; + assign n2023 = (n2158 | n2176) & (~n2175 | n2601); + assign n2024 = (~Pkey_193_ | n1137) & n2602; + assign n2025 = (n2159 | n2176) & (~n2175 | n2603); + assign n2026 = (~Pkey_250_ | n1137) & n2604; + assign n2027 = (n2160 | n2176) & (~n2175 | n2605); + assign n2028 = (~Pkey_242_ | n1137) & n2606; + assign n2029 = (n2161 | n2176) & (~n2175 | n2607); + assign n2030 = (~Pkey_234_ | n1137) & n2608; + assign n2031 = (n2162 | n2176) & (~n2175 | n2609); + assign n2032 = (~Pkey_226_ | n1137) & n2610; + assign n2033 = (n2163 | n2176) & (~n2175 | n2611); + assign n2034 = (~Pkey_218_ | n1137) & n2612; + assign n2035 = (n2164 | n2176) & (~n2175 | n2613); + assign n2036 = (~Pkey_210_ | n1137) & n2614; + assign n2037 = (n2165 | n2176) & (~n2175 | n2615); + assign n2038 = (~Pkey_202_ | n1137) & n2616; + assign n2039 = (n2166 | n2176) & (~n2175 | n2617); + assign n2040 = (~Pkey_194_ | n1137) & n2618; + assign n2041 = (n2167 | n2176) & (~n2175 | n2619); + assign n2042 = (~Pkey_251_ | n1137) & n2620; + assign n2043 = (n2168 | n2176) & (~n2175 | n2621); + assign n2044 = (~Pkey_243_ | n1137) & n2622; + assign n2045 = (n2169 | n2176) & (~n2175 | n2623); + assign n2046 = (~Pkey_235_ | n1137) & n2624; + assign n2047 = (n2170 | n2176) & (~n2175 | n2625); + assign n2048 = (~Pkey_227_ | n1137) & n2626; + assign n2049 = ~Pcount_3_ | n1596 | n2177; + assign n2050 = n1595 | Pcount_3_ | Pencrypt_0_; + assign n2051 = (n2739 & (~Pcount_1_ | n2740)) | (Pcount_1_ & n2740); + assign n2052 = Pencrypt_0_ | ~Pcount_1_; + assign n2053 = Pcount_2_ & (~n2052 | ~n2740); + assign n2054 = n1137 & (Pstart_0_ | ~Pcount_0_ | ~n2178); + assign n2055 = ~Pcount_2_ & ~Pcount_0_; + assign n2056 = (~Pencrypt_0_ | n1599) & n2050; + assign n2057 = (~n1596 & (Pencrypt_0_ | n2055)) | (~Pencrypt_0_ & n2055); + assign n2058 = n2056 & (~Pcount_3_ | (n2052 & n2057)); + assign n2059 = ~PKSi_118_ ^ PKSi_4_; + assign n2060 = ~PKSi_102_ ^ PKSi_23_; + assign n2061 = ~PKSi_98_ ^ PKSi_6_; + assign n2062 = ~PKSi_119_ ^ PKSi_15_; + assign n2063 = ~PKSi_106_ ^ PKSi_5_; + assign n2064 = ~PKSi_112_ ^ PKSi_9_; + assign n2065 = ~PKSi_19_ ^ N_N2986; + assign n2066 = ~PKSi_117_ ^ PKSi_17_; + assign n2067 = ~PKSi_99_ ^ N_N2853; + assign n2068 = ~PKSi_11_ ^ N_N2982; + assign n2069 = ~PKSi_110_ ^ PKSi_2_; + assign n2070 = ~PKSi_103_ ^ PKSi_14_; + assign n2071 = ~PKSi_96_ ^ PKSi_22_; + assign n2072 = ~PKSi_115_ ^ PKSi_0_; + assign n2073 = ~PKSi_8_ ^ N_N2976; + assign n2074 = ~PKSi_108_ ^ PKSi_18_; + assign n2075 = ~PKSi_105_ ^ PKSi_1_; + assign n2076 = ~PKSi_114_ ^ N_N2843; + assign n2077 = ~PKSi_100_ ^ PKSi_13_; + assign n2078 = ~PKSi_107_ ^ PKSi_21_; + assign n2079 = ~PKSi_109_ ^ PKSi_10_; + assign n2080 = ~PKSi_116_ ^ N_N2838; + assign n2081 = ~PKSi_104_ ^ PKSi_12_; + assign n2082 = ~PKSi_97_ ^ PKSi_3_; + assign n2083 = ~PKSi_113_ ^ N_N2834; + assign n2084 = ~PKSi_16_ ^ N_N2964; + assign n2085 = ~PKSi_101_ ^ PKSi_20_; + assign n2086 = ~PKSi_111_ ^ PKSi_7_; + assign n2087 = ~PKSi_142_ ^ PKSi_28_; + assign n2088 = ~PKSi_126_ ^ PKSi_47_; + assign n2089 = ~PKSi_122_ ^ PKSi_30_; + assign n2090 = ~\[282] ^ PKSi_39_; + assign n2091 = ~PKSi_130_ ^ PKSi_29_; + assign n2092 = ~PKSi_136_ ^ PKSi_33_; + assign n2093 = ~PKSi_43_ ^ N_N2954; + assign n2094 = ~PKSi_141_ ^ PKSi_41_; + assign n2095 = ~PKSi_123_ ^ N_N2821; + assign n2096 = ~PKSi_35_ ^ N_N2950; + assign n2097 = ~PKSi_134_ ^ PKSi_26_; + assign n2098 = ~PKSi_127_ ^ PKSi_38_; + assign n2099 = ~PKSi_120_ ^ PKSi_46_; + assign n2100 = ~PKSi_24_ ^ N_N2945; + assign n2101 = ~PKSi_32_ ^ N_N2943; + assign n2102 = ~PKSi_132_ ^ PKSi_42_; + assign n2103 = ~PKSi_129_ ^ PKSi_25_; + assign n2104 = ~PKSi_138_ ^ N_N2811; + assign n2105 = ~PKSi_124_ ^ PKSi_37_; + assign n2106 = ~PKSi_131_ ^ PKSi_45_; + assign n2107 = ~PKSi_133_ ^ PKSi_34_; + assign n2108 = ~PKSi_140_ ^ N_N2806; + assign n2109 = ~PKSi_128_ ^ PKSi_36_; + assign n2110 = ~PKSi_121_ ^ PKSi_27_; + assign n2111 = ~PKSi_137_ ^ N_N2802; + assign n2112 = ~PKSi_40_ ^ N_N2931; + assign n2113 = ~PKSi_125_ ^ PKSi_44_; + assign n2114 = ~PKSi_135_ ^ PKSi_31_; + assign n2115 = ~PKSi_166_ ^ PKSi_52_; + assign n2116 = ~PKSi_150_ ^ PKSi_71_; + assign n2117 = ~PKSi_146_ ^ PKSi_54_; + assign n2118 = ~PKSi_167_ ^ PKSi_63_; + assign n2119 = ~PKSi_154_ ^ PKSi_53_; + assign n2120 = ~PKSi_160_ ^ PKSi_57_; + assign n2121 = ~PKSi_67_ ^ N_N2921; + assign n2122 = ~PKSi_165_ ^ PKSi_65_; + assign n2123 = ~PKSi_147_ ^ N_N2789; + assign n2124 = ~PKSi_59_ ^ N_N2917; + assign n2125 = ~PKSi_158_ ^ PKSi_50_; + assign n2126 = ~PKSi_151_ ^ PKSi_62_; + assign n2127 = ~PKSi_144_ ^ PKSi_70_; + assign n2128 = ~PKSi_163_ ^ PKSi_48_; + assign n2129 = ~PKSi_153_ ^ PKSi_56_; + assign n2130 = ~PKSi_156_ ^ PKSi_66_; + assign n2131 = ~PKSi_49_ ^ N_N2909; + assign n2132 = ~PKSi_162_ ^ N_N2779; + assign n2133 = ~PKSi_148_ ^ PKSi_61_; + assign n2134 = ~PKSi_155_ ^ PKSi_69_; + assign n2135 = ~PKSi_157_ ^ PKSi_58_; + assign n2136 = ~PKSi_164_ ^ N_N2774; + assign n2137 = ~PKSi_152_ ^ PKSi_60_; + assign n2138 = ~PKSi_145_ ^ PKSi_51_; + assign n2139 = ~PKSi_161_ ^ N_N2770; + assign n2140 = ~PKSi_64_ ^ N_N2899; + assign n2141 = ~PKSi_149_ ^ PKSi_68_; + assign n2142 = ~PKSi_159_ ^ PKSi_55_; + assign n2143 = ~PKSi_190_ ^ PKSi_76_; + assign n2144 = ~PKSi_174_ ^ PKSi_95_; + assign n2145 = ~PKSi_170_ ^ PKSi_78_; + assign n2146 = ~\[234] ^ PKSi_87_; + assign n2147 = ~PKSi_178_ ^ PKSi_77_; + assign n2148 = ~PKSi_184_ ^ PKSi_81_; + assign n2149 = ~PKSi_91_ ^ N_N2889; + assign n2150 = ~PKSi_189_ ^ PKSi_89_; + assign n2151 = ~PKSi_171_ ^ N_N2757; + assign n2152 = ~PKSi_83_ ^ N_N2885; + assign n2153 = ~PKSi_182_ ^ PKSi_74_; + assign n2154 = ~PKSi_175_ ^ PKSi_86_; + assign n2155 = ~PKSi_94_ ^ N_N2881; + assign n2156 = ~PKSi_72_ ^ N_N2879; + assign n2157 = ~PKSi_80_ ^ N_N2877; + assign n2158 = ~PKSi_180_ ^ N_N2749; + assign n2159 = ~PKSi_177_ ^ PKSi_73_; + assign n2160 = ~PKSi_186_ ^ N_N2746; + assign n2161 = ~PKSi_172_ ^ PKSi_85_; + assign n2162 = ~PKSi_179_ ^ PKSi_93_; + assign n2163 = ~\[253] ^ PKSi_82_; + assign n2164 = ~PKSi_188_ ^ N_N2741; + assign n2165 = ~PKSi_176_ ^ PKSi_84_; + assign n2166 = ~PKSi_169_ ^ PKSi_75_; + assign n2167 = ~PKSi_185_ ^ N_N2737; + assign n2168 = ~\[333] ^ N_N2865; + assign n2169 = ~PKSi_173_ ^ PKSi_92_; + assign n2170 = ~PKSi_183_ ^ PKSi_79_; + assign n2171 = Pencrypt_0_ & ~n1600; + assign n2172 = Pstart_0_ | n2171; + assign n2173 = Pstart_0_ | ~n2171; + assign n2174 = ~Pencrypt_0_ | ~n1600; + assign n2175 = ~Pstart_0_ & n2174; + assign n2176 = Pstart_0_ | n2174; + assign n2177 = Pstart_0_ | ~Pencrypt_0_; + assign n2178 = n2741 & ((Pencrypt_0_ & ~Pcount_2_) | ~Pcount_1_); + assign n2179 = n2059 | n2173; + assign n2180 = (~n1140 & ~n2627) | (n1139_1 & (~n1140 | n2627)); + assign n2181 = n2060 | n2173; + assign n2182 = (~n1140 & ~n2628) | (n1139_1 & (~n1140 | n2628)); + assign n2183 = n2061 | n2173; + assign n2184 = (~n1140 & ~n2629) | (n1139_1 & (~n1140 | n2629)); + assign n2185 = n2062 | n2173; + assign n2186 = (~n1140 & ~n2630) | (n1139_1 & (~n1140 | n2630)); + assign n2187 = n2063 | n2173; + assign n2188 = (~n1140 & ~n2631) | (n1139_1 & (~n1140 | n2631)); + assign n2189 = n2064 | n2173; + assign n2190 = (~n1140 & ~n2632) | (n1139_1 & (~n1140 | n2632)); + assign n2191 = n2065 | n2173; + assign n2192 = (~n1140 & ~n2633) | (n1139_1 & (~n1140 | n2633)); + assign n2193 = n2066 | n2173; + assign n2194 = (~n1140 & ~n2634) | (n1139_1 & (~n1140 | n2634)); + assign n2195 = n2067 | n2173; + assign n2196 = (~n1140 & ~n2635) | (n1139_1 & (~n1140 | n2635)); + assign n2197 = n2068 | n2173; + assign n2198 = (~n1140 & ~n2636) | (n1139_1 & (~n1140 | n2636)); + assign n2199 = n2069 | n2173; + assign n2200 = (~n1140 & ~n2637) | (n1139_1 & (~n1140 | n2637)); + assign n2201 = n2070 | n2173; + assign n2202 = (~n1140 & ~n2638) | (n1139_1 & (~n1140 | n2638)); + assign n2203 = n2071 | n2173; + assign n2204 = (~n1140 & ~n2639) | (n1139_1 & (~n1140 | n2639)); + assign n2205 = n2072 | n2173; + assign n2206 = (~n1140 & ~n2640) | (n1139_1 & (~n1140 | n2640)); + assign n2207 = n2073 | n2173; + assign n2208 = (~n1140 & ~n2641) | (n1139_1 & (~n1140 | n2641)); + assign n2209 = n2074 | n2173; + assign n2210 = (~n1140 & ~n2642) | (n1139_1 & (~n1140 | n2642)); + assign n2211 = n2075 | n2173; + assign n2212 = (~n1140 & ~n2643) | (n1139_1 & (~n1140 | n2643)); + assign n2213 = n2076 | n2173; + assign n2214 = (~n1140 & ~n2644) | (n1139_1 & (~n1140 | n2644)); + assign n2215 = n2077 | n2173; + assign n2216 = (~n1140 & ~n2645) | (n1139_1 & (~n1140 | n2645)); + assign n2217 = n2078 | n2173; + assign n2218 = (~n1140 & ~n2646) | (n1139_1 & (~n1140 | n2646)); + assign n2219 = n2079 | n2173; + assign n2220 = (~n1140 & ~n2647) | (n1139_1 & (~n1140 | n2647)); + assign n2221 = n2080 | n2173; + assign n2222 = (~n1140 & ~n2648) | (n1139_1 & (~n1140 | n2648)); + assign n2223 = n2081 | n2173; + assign n2224 = (~n1140 & ~n2649) | (n1139_1 & (~n1140 | n2649)); + assign n2225 = n2082 | n2173; + assign n2226 = (~n1140 & ~n2650) | (n1139_1 & (~n1140 | n2650)); + assign n2227 = n2083 | n2173; + assign n2228 = (~n1140 & ~n2651) | (n1139_1 & (~n1140 | n2651)); + assign n2229 = n2084 | n2173; + assign n2230 = (~n1140 & ~n2652) | (n1139_1 & (~n1140 | n2652)); + assign n2231 = n2085 | n2173; + assign n2232 = (~n1140 & ~n2653) | (n1139_1 & (~n1140 | n2653)); + assign n2233 = n2086 | n2173; + assign n2234 = (~n1140 & ~n2654) | (n1139_1 & (~n1140 | n2654)); + assign n2235 = n2087 | n2173; + assign n2236 = (~n1140 & ~n2655) | (n1139_1 & (~n1140 | n2655)); + assign n2237 = n2088 | n2173; + assign n2238 = (~n1140 & ~n2656) | (n1139_1 & (~n1140 | n2656)); + assign n2239 = n2089 | n2173; + assign n2240 = (~n1140 & ~n2657) | (n1139_1 & (~n1140 | n2657)); + assign n2241 = n2090 | n2173; + assign n2242 = (~n1140 & ~n2658) | (n1139_1 & (~n1140 | n2658)); + assign n2243 = n2091 | n2173; + assign n2244 = (~n1140 & ~n2659) | (n1139_1 & (~n1140 | n2659)); + assign n2245 = n2092 | n2173; + assign n2246 = (~n1140 & ~n2660) | (n1139_1 & (~n1140 | n2660)); + assign n2247 = n2093 | n2173; + assign n2248 = (~n1140 & ~n2661) | (n1139_1 & (~n1140 | n2661)); + assign n2249 = n2094 | n2173; + assign n2250 = (~n1140 & ~n2662) | (n1139_1 & (~n1140 | n2662)); + assign n2251 = n2095 | n2173; + assign n2252 = (~n1140 & ~n2663) | (n1139_1 & (~n1140 | n2663)); + assign n2253 = n2096 | n2173; + assign n2254 = (~n1140 & ~n2664) | (n1139_1 & (~n1140 | n2664)); + assign n2255 = n2097 | n2173; + assign n2256 = (~n1140 & ~n2665) | (n1139_1 & (~n1140 | n2665)); + assign n2257 = n2098 | n2173; + assign n2258 = (~n1140 & ~n2666) | (n1139_1 & (~n1140 | n2666)); + assign n2259 = n2099 | n2173; + assign n2260 = (~n1140 & ~n2667) | (n1139_1 & (~n1140 | n2667)); + assign n2261 = n2100 | n2173; + assign n2262 = (~n1140 & ~n2668) | (n1139_1 & (~n1140 | n2668)); + assign n2263 = n2101 | n2173; + assign n2264 = (~n1140 & ~n2669) | (n1139_1 & (~n1140 | n2669)); + assign n2265 = n2102 | n2173; + assign n2266 = (~n1140 & ~n2670) | (n1139_1 & (~n1140 | n2670)); + assign n2267 = n2103 | n2173; + assign n2268 = (~n1140 & ~n2671) | (n1139_1 & (~n1140 | n2671)); + assign n2269 = n2104 | n2173; + assign n2270 = (~n1140 & ~n2672) | (n1139_1 & (~n1140 | n2672)); + assign n2271 = n2105 | n2173; + assign n2272 = (~n1140 & ~n2673) | (n1139_1 & (~n1140 | n2673)); + assign n2273 = n2106 | n2173; + assign n2274 = (~n1140 & ~n2674) | (n1139_1 & (~n1140 | n2674)); + assign n2275 = n2107 | n2173; + assign n2276 = (~n1140 & ~n2675) | (n1139_1 & (~n1140 | n2675)); + assign n2277 = n2108 | n2173; + assign n2278 = (~n1140 & ~n2676) | (n1139_1 & (~n1140 | n2676)); + assign n2279 = n2109 | n2173; + assign n2280 = (~n1140 & ~n2677) | (n1139_1 & (~n1140 | n2677)); + assign n2281 = n2110 | n2173; + assign n2282 = (~n1140 & ~n2678) | (n1139_1 & (~n1140 | n2678)); + assign n2283 = n2111 | n2173; + assign n2284 = (~n1140 & ~n2679) | (n1139_1 & (~n1140 | n2679)); + assign n2285 = n2112 | n2173; + assign n2286 = (~n1140 & ~n2680) | (n1139_1 & (~n1140 | n2680)); + assign n2287 = n2113 | n2173; + assign n2288 = (~n1140 & ~n2681) | (n1139_1 & (~n1140 | n2681)); + assign n2289 = n2114 | n2173; + assign n2290 = (~n1140 & ~n2682) | (n1139_1 & (~n1140 | n2682)); + assign n2291 = n2115 | n2173; + assign n2292 = (~n1140 & ~n2683) | (n1139_1 & (~n1140 | n2683)); + assign n2293 = n2116 | n2173; + assign n2294 = (~n1140 & ~n2684) | (n1139_1 & (~n1140 | n2684)); + assign n2295 = n2117 | n2173; + assign n2296 = (~n1140 & ~n2685) | (n1139_1 & (~n1140 | n2685)); + assign n2297 = n2118 | n2173; + assign n2298 = (~n1140 & ~n2686) | (n1139_1 & (~n1140 | n2686)); + assign n2299 = n2119 | n2173; + assign n2300 = (~n1140 & ~n2687) | (n1139_1 & (~n1140 | n2687)); + assign n2301 = n2120 | n2173; + assign n2302 = (~n1140 & ~n2688) | (n1139_1 & (~n1140 | n2688)); + assign n2303 = n2121 | n2173; + assign n2304 = (~n1140 & ~n2689) | (n1139_1 & (~n1140 | n2689)); + assign n2305 = n2122 | n2173; + assign n2306 = (~n1140 & ~n2690) | (n1139_1 & (~n1140 | n2690)); + assign n2307 = n2123 | n2173; + assign n2308 = (~n1140 & ~n2691) | (n1139_1 & (~n1140 | n2691)); + assign n2309 = n2124 | n2173; + assign n2310 = (~n1140 & ~n2692) | (n1139_1 & (~n1140 | n2692)); + assign n2311 = n2125 | n2173; + assign n2312 = (~n1140 & ~n2693) | (n1139_1 & (~n1140 | n2693)); + assign n2313 = n2126 | n2173; + assign n2314 = (~n1140 & ~n2694) | (n1139_1 & (~n1140 | n2694)); + assign n2315 = n2127 | n2173; + assign n2316 = (~n1140 & ~n2695) | (n1139_1 & (~n1140 | n2695)); + assign n2317 = n2128 | n2173; + assign n2318 = (~n1140 & ~n2696) | (n1139_1 & (~n1140 | n2696)); + assign n2319 = n2129 | n2173; + assign n2320 = (~n1140 & ~n2697) | (n1139_1 & (~n1140 | n2697)); + assign n2321 = n2130 | n2173; + assign n2322 = (~n1140 & ~n2698) | (n1139_1 & (~n1140 | n2698)); + assign n2323 = n2131 | n2173; + assign n2324 = (~n1140 & ~n2699) | (n1139_1 & (~n1140 | n2699)); + assign n2325 = n2132 | n2173; + assign n2326 = (~n1140 & ~n2700) | (n1139_1 & (~n1140 | n2700)); + assign n2327 = n2133 | n2173; + assign n2328 = (~n1140 & ~n2701) | (n1139_1 & (~n1140 | n2701)); + assign n2329 = n2134 | n2173; + assign n2330 = (~n1140 & ~n2702) | (n1139_1 & (~n1140 | n2702)); + assign n2331 = n2135 | n2173; + assign n2332 = (~n1140 & ~n2703) | (n1139_1 & (~n1140 | n2703)); + assign n2333 = n2136 | n2173; + assign n2334 = (~n1140 & ~n2704) | (n1139_1 & (~n1140 | n2704)); + assign n2335 = n2137 | n2173; + assign n2336 = (~n1140 & ~n2705) | (n1139_1 & (~n1140 | n2705)); + assign n2337 = n2138 | n2173; + assign n2338 = (~n1140 & ~n2706) | (n1139_1 & (~n1140 | n2706)); + assign n2339 = n2139 | n2173; + assign n2340 = (~n1140 & ~n2707) | (n1139_1 & (~n1140 | n2707)); + assign n2341 = n2140 | n2173; + assign n2342 = (~n1140 & ~n2708) | (n1139_1 & (~n1140 | n2708)); + assign n2343 = n2141 | n2173; + assign n2344 = (~n1140 & ~n2709) | (n1139_1 & (~n1140 | n2709)); + assign n2345 = n2142 | n2173; + assign n2346 = (~n1140 & ~n2710) | (n1139_1 & (~n1140 | n2710)); + assign n2347 = n2143 | n2173; + assign n2348 = (~n1140 & ~n2711) | (n1139_1 & (~n1140 | n2711)); + assign n2349 = n2144 | n2173; + assign n2350 = (~n1140 & ~n2712) | (n1139_1 & (~n1140 | n2712)); + assign n2351 = n2145 | n2173; + assign n2352 = (~n1140 & ~n2713) | (n1139_1 & (~n1140 | n2713)); + assign n2353 = n2146 | n2173; + assign n2354 = (~n1140 & ~n2714) | (n1139_1 & (~n1140 | n2714)); + assign n2355 = n2147 | n2173; + assign n2356 = (~n1140 & ~n2715) | (n1139_1 & (~n1140 | n2715)); + assign n2357 = n2148 | n2173; + assign n2358 = (~n1140 & ~n2716) | (n1139_1 & (~n1140 | n2716)); + assign n2359 = n2149 | n2173; + assign n2360 = (~n1140 & ~n2717) | (n1139_1 & (~n1140 | n2717)); + assign n2361 = n2150 | n2173; + assign n2362 = (~n1140 & ~n2718) | (n1139_1 & (~n1140 | n2718)); + assign n2363 = n2151 | n2173; + assign n2364 = (~n1140 & ~n2719) | (n1139_1 & (~n1140 | n2719)); + assign n2365 = n2152 | n2173; + assign n2366 = (~n1140 & ~n2720) | (n1139_1 & (~n1140 | n2720)); + assign n2367 = n2153 | n2173; + assign n2368 = (~n1140 & ~n2721) | (n1139_1 & (~n1140 | n2721)); + assign n2369 = n2154 | n2173; + assign n2370 = (~n1140 & ~n2722) | (n1139_1 & (~n1140 | n2722)); + assign n2371 = n2155 | n2173; + assign n2372 = (~n1140 & ~n2723) | (n1139_1 & (~n1140 | n2723)); + assign n2373 = n2156 | n2173; + assign n2374 = (~n1140 & ~n2724) | (n1139_1 & (~n1140 | n2724)); + assign n2375 = n2157 | n2173; + assign n2376 = (~n1140 & ~n2725) | (n1139_1 & (~n1140 | n2725)); + assign n2377 = n2158 | n2173; + assign n2378 = (~n1140 & ~n2726) | (n1139_1 & (~n1140 | n2726)); + assign n2379 = n2159 | n2173; + assign n2380 = (~n1140 & ~n2727) | (n1139_1 & (~n1140 | n2727)); + assign n2381 = n2160 | n2173; + assign n2382 = (~n1140 & ~n2728) | (n1139_1 & (~n1140 | n2728)); + assign n2383 = n2161 | n2173; + assign n2384 = (~n1140 & ~n2729) | (n1139_1 & (~n1140 | n2729)); + assign n2385 = n2162 | n2173; + assign n2386 = (~n1140 & ~n2730) | (n1139_1 & (~n1140 | n2730)); + assign n2387 = n2163 | n2173; + assign n2388 = (~n1140 & ~n2731) | (n1139_1 & (~n1140 | n2731)); + assign n2389 = n2164 | n2173; + assign n2390 = (~n1140 & ~n2732) | (n1139_1 & (~n1140 | n2732)); + assign n2391 = n2165 | n2173; + assign n2392 = (~n1140 & ~n2733) | (n1139_1 & (~n1140 | n2733)); + assign n2393 = n2166 | n2173; + assign n2394 = (~n1140 & ~n2734) | (n1139_1 & (~n1140 | n2734)); + assign n2395 = n2167 | n2173; + assign n2396 = (~n1140 & ~n2735) | (n1139_1 & (~n1140 | n2735)); + assign n2397 = n2168 | n2173; + assign n2398 = (~n1140 & ~n2736) | (n1139_1 & (~n1140 | n2736)); + assign n2399 = n2169 | n2173; + assign n2400 = (~n1140 & ~n2737) | (n1139_1 & (~n1140 | n2737)); + assign n2401 = n2170 | n2173; + assign n2402 = (~n1140 & ~n2738) | (n1139_1 & (~n1140 | n2738)); + assign n2403 = ~PKSi_118_ | ~PKSi_4_; + assign n2404 = (~n1140 & n2627) | (n1139_1 & (~n1140 | ~n2627)); + assign n2405 = ~PKSi_102_ | ~PKSi_23_; + assign n2406 = (~n1140 & n2628) | (n1139_1 & (~n1140 | ~n2628)); + assign n2407 = ~PKSi_98_ | ~PKSi_6_; + assign n2408 = (~n1140 & n2629) | (n1139_1 & (~n1140 | ~n2629)); + assign n2409 = ~PKSi_119_ | ~PKSi_15_; + assign n2410 = (~n1140 & n2630) | (n1139_1 & (~n1140 | ~n2630)); + assign n2411 = ~PKSi_106_ | ~PKSi_5_; + assign n2412 = (~n1140 & n2631) | (n1139_1 & (~n1140 | ~n2631)); + assign n2413 = ~PKSi_112_ | ~PKSi_9_; + assign n2414 = (~n1140 & n2632) | (n1139_1 & (~n1140 | ~n2632)); + assign n2415 = ~PKSi_19_ | ~N_N2986; + assign n2416 = (~n1140 & n2633) | (n1139_1 & (~n1140 | ~n2633)); + assign n2417 = ~PKSi_117_ | ~PKSi_17_; + assign n2418 = (~n1140 & n2634) | (n1139_1 & (~n1140 | ~n2634)); + assign n2419 = ~PKSi_99_ | ~N_N2853; + assign n2420 = (~n1140 & n2635) | (n1139_1 & (~n1140 | ~n2635)); + assign n2421 = ~PKSi_11_ | ~N_N2982; + assign n2422 = (~n1140 & n2636) | (n1139_1 & (~n1140 | ~n2636)); + assign n2423 = ~PKSi_110_ | ~PKSi_2_; + assign n2424 = (~n1140 & n2637) | (n1139_1 & (~n1140 | ~n2637)); + assign n2425 = ~PKSi_103_ | ~PKSi_14_; + assign n2426 = (~n1140 & n2638) | (n1139_1 & (~n1140 | ~n2638)); + assign n2427 = ~PKSi_96_ | ~PKSi_22_; + assign n2428 = (~n1140 & n2639) | (n1139_1 & (~n1140 | ~n2639)); + assign n2429 = ~PKSi_115_ | ~PKSi_0_; + assign n2430 = (~n1140 & n2640) | (n1139_1 & (~n1140 | ~n2640)); + assign n2431 = ~PKSi_8_ | ~N_N2976; + assign n2432 = (~n1140 & n2641) | (n1139_1 & (~n1140 | ~n2641)); + assign n2433 = ~PKSi_108_ | ~PKSi_18_; + assign n2434 = (~n1140 & n2642) | (n1139_1 & (~n1140 | ~n2642)); + assign n2435 = ~PKSi_105_ | ~PKSi_1_; + assign n2436 = (~n1140 & n2643) | (n1139_1 & (~n1140 | ~n2643)); + assign n2437 = ~PKSi_114_ | ~N_N2843; + assign n2438 = (~n1140 & n2644) | (n1139_1 & (~n1140 | ~n2644)); + assign n2439 = ~PKSi_100_ | ~PKSi_13_; + assign n2440 = (~n1140 & n2645) | (n1139_1 & (~n1140 | ~n2645)); + assign n2441 = ~PKSi_107_ | ~PKSi_21_; + assign n2442 = (~n1140 & n2646) | (n1139_1 & (~n1140 | ~n2646)); + assign n2443 = ~PKSi_109_ | ~PKSi_10_; + assign n2444 = (~n1140 & n2647) | (n1139_1 & (~n1140 | ~n2647)); + assign n2445 = ~PKSi_116_ | ~N_N2838; + assign n2446 = (~n1140 & n2648) | (n1139_1 & (~n1140 | ~n2648)); + assign n2447 = ~PKSi_104_ | ~PKSi_12_; + assign n2448 = (~n1140 & n2649) | (n1139_1 & (~n1140 | ~n2649)); + assign n2449 = ~PKSi_97_ | ~PKSi_3_; + assign n2450 = (~n1140 & n2650) | (n1139_1 & (~n1140 | ~n2650)); + assign n2451 = ~PKSi_113_ | ~N_N2834; + assign n2452 = (~n1140 & n2651) | (n1139_1 & (~n1140 | ~n2651)); + assign n2453 = ~PKSi_16_ | ~N_N2964; + assign n2454 = (~n1140 & n2652) | (n1139_1 & (~n1140 | ~n2652)); + assign n2455 = ~PKSi_101_ | ~PKSi_20_; + assign n2456 = (~n1140 & n2653) | (n1139_1 & (~n1140 | ~n2653)); + assign n2457 = ~PKSi_111_ | ~PKSi_7_; + assign n2458 = (~n1140 & n2654) | (n1139_1 & (~n1140 | ~n2654)); + assign n2459 = ~PKSi_142_ | ~PKSi_28_; + assign n2460 = (~n1140 & n2655) | (n1139_1 & (~n1140 | ~n2655)); + assign n2461 = ~PKSi_126_ | ~PKSi_47_; + assign n2462 = (~n1140 & n2656) | (n1139_1 & (~n1140 | ~n2656)); + assign n2463 = ~PKSi_122_ | ~PKSi_30_; + assign n2464 = (~n1140 & n2657) | (n1139_1 & (~n1140 | ~n2657)); + assign n2465 = ~\[282] | ~PKSi_39_; + assign n2466 = (~n1140 & n2658) | (n1139_1 & (~n1140 | ~n2658)); + assign n2467 = ~PKSi_130_ | ~PKSi_29_; + assign n2468 = (~n1140 & n2659) | (n1139_1 & (~n1140 | ~n2659)); + assign n2469 = ~PKSi_136_ | ~PKSi_33_; + assign n2470 = (~n1140 & n2660) | (n1139_1 & (~n1140 | ~n2660)); + assign n2471 = ~PKSi_43_ | ~N_N2954; + assign n2472 = (~n1140 & n2661) | (n1139_1 & (~n1140 | ~n2661)); + assign n2473 = ~PKSi_141_ | ~PKSi_41_; + assign n2474 = (~n1140 & n2662) | (n1139_1 & (~n1140 | ~n2662)); + assign n2475 = ~PKSi_123_ | ~N_N2821; + assign n2476 = (~n1140 & n2663) | (n1139_1 & (~n1140 | ~n2663)); + assign n2477 = ~PKSi_35_ | ~N_N2950; + assign n2478 = (~n1140 & n2664) | (n1139_1 & (~n1140 | ~n2664)); + assign n2479 = ~PKSi_134_ | ~PKSi_26_; + assign n2480 = (~n1140 & n2665) | (n1139_1 & (~n1140 | ~n2665)); + assign n2481 = ~PKSi_127_ | ~PKSi_38_; + assign n2482 = (~n1140 & n2666) | (n1139_1 & (~n1140 | ~n2666)); + assign n2483 = ~PKSi_120_ | ~PKSi_46_; + assign n2484 = (~n1140 & n2667) | (n1139_1 & (~n1140 | ~n2667)); + assign n2485 = ~PKSi_24_ | ~N_N2945; + assign n2486 = (~n1140 & n2668) | (n1139_1 & (~n1140 | ~n2668)); + assign n2487 = ~PKSi_32_ | ~N_N2943; + assign n2488 = (~n1140 & n2669) | (n1139_1 & (~n1140 | ~n2669)); + assign n2489 = ~PKSi_132_ | ~PKSi_42_; + assign n2490 = (~n1140 & n2670) | (n1139_1 & (~n1140 | ~n2670)); + assign n2491 = ~PKSi_129_ | ~PKSi_25_; + assign n2492 = (~n1140 & n2671) | (n1139_1 & (~n1140 | ~n2671)); + assign n2493 = ~PKSi_138_ | ~N_N2811; + assign n2494 = (~n1140 & n2672) | (n1139_1 & (~n1140 | ~n2672)); + assign n2495 = ~PKSi_124_ | ~PKSi_37_; + assign n2496 = (~n1140 & n2673) | (n1139_1 & (~n1140 | ~n2673)); + assign n2497 = ~PKSi_131_ | ~PKSi_45_; + assign n2498 = (~n1140 & n2674) | (n1139_1 & (~n1140 | ~n2674)); + assign n2499 = ~PKSi_133_ | ~PKSi_34_; + assign n2500 = (~n1140 & n2675) | (n1139_1 & (~n1140 | ~n2675)); + assign n2501 = ~PKSi_140_ | ~N_N2806; + assign n2502 = (~n1140 & n2676) | (n1139_1 & (~n1140 | ~n2676)); + assign n2503 = ~PKSi_128_ | ~PKSi_36_; + assign n2504 = (~n1140 & n2677) | (n1139_1 & (~n1140 | ~n2677)); + assign n2505 = ~PKSi_121_ | ~PKSi_27_; + assign n2506 = (~n1140 & n2678) | (n1139_1 & (~n1140 | ~n2678)); + assign n2507 = ~PKSi_137_ | ~N_N2802; + assign n2508 = (~n1140 & n2679) | (n1139_1 & (~n1140 | ~n2679)); + assign n2509 = ~PKSi_40_ | ~N_N2931; + assign n2510 = (~n1140 & n2680) | (n1139_1 & (~n1140 | ~n2680)); + assign n2511 = ~PKSi_125_ | ~PKSi_44_; + assign n2512 = (~n1140 & n2681) | (n1139_1 & (~n1140 | ~n2681)); + assign n2513 = ~PKSi_135_ | ~PKSi_31_; + assign n2514 = (~n1140 & n2682) | (n1139_1 & (~n1140 | ~n2682)); + assign n2515 = ~PKSi_166_ | ~PKSi_52_; + assign n2516 = (~n1140 & n2683) | (n1139_1 & (~n1140 | ~n2683)); + assign n2517 = ~PKSi_150_ | ~PKSi_71_; + assign n2518 = (~n1140 & n2684) | (n1139_1 & (~n1140 | ~n2684)); + assign n2519 = ~PKSi_146_ | ~PKSi_54_; + assign n2520 = (~n1140 & n2685) | (n1139_1 & (~n1140 | ~n2685)); + assign n2521 = ~PKSi_167_ | ~PKSi_63_; + assign n2522 = (~n1140 & n2686) | (n1139_1 & (~n1140 | ~n2686)); + assign n2523 = ~PKSi_154_ | ~PKSi_53_; + assign n2524 = (~n1140 & n2687) | (n1139_1 & (~n1140 | ~n2687)); + assign n2525 = ~PKSi_160_ | ~PKSi_57_; + assign n2526 = (~n1140 & n2688) | (n1139_1 & (~n1140 | ~n2688)); + assign n2527 = ~PKSi_67_ | ~N_N2921; + assign n2528 = (~n1140 & n2689) | (n1139_1 & (~n1140 | ~n2689)); + assign n2529 = ~PKSi_165_ | ~PKSi_65_; + assign n2530 = (~n1140 & n2690) | (n1139_1 & (~n1140 | ~n2690)); + assign n2531 = ~PKSi_147_ | ~N_N2789; + assign n2532 = (~n1140 & n2691) | (n1139_1 & (~n1140 | ~n2691)); + assign n2533 = ~PKSi_59_ | ~N_N2917; + assign n2534 = (~n1140 & n2692) | (n1139_1 & (~n1140 | ~n2692)); + assign n2535 = ~PKSi_158_ | ~PKSi_50_; + assign n2536 = (~n1140 & n2693) | (n1139_1 & (~n1140 | ~n2693)); + assign n2537 = ~PKSi_151_ | ~PKSi_62_; + assign n2538 = (~n1140 & n2694) | (n1139_1 & (~n1140 | ~n2694)); + assign n2539 = ~PKSi_144_ | ~PKSi_70_; + assign n2540 = (~n1140 & n2695) | (n1139_1 & (~n1140 | ~n2695)); + assign n2541 = ~PKSi_163_ | ~PKSi_48_; + assign n2542 = (~n1140 & n2696) | (n1139_1 & (~n1140 | ~n2696)); + assign n2543 = ~PKSi_153_ | ~PKSi_56_; + assign n2544 = (~n1140 & n2697) | (n1139_1 & (~n1140 | ~n2697)); + assign n2545 = ~PKSi_156_ | ~PKSi_66_; + assign n2546 = (~n1140 & n2698) | (n1139_1 & (~n1140 | ~n2698)); + assign n2547 = ~PKSi_49_ | ~N_N2909; + assign n2548 = (~n1140 & n2699) | (n1139_1 & (~n1140 | ~n2699)); + assign n2549 = ~PKSi_162_ | ~N_N2779; + assign n2550 = (~n1140 & n2700) | (n1139_1 & (~n1140 | ~n2700)); + assign n2551 = ~PKSi_148_ | ~PKSi_61_; + assign n2552 = (~n1140 & n2701) | (n1139_1 & (~n1140 | ~n2701)); + assign n2553 = ~PKSi_155_ | ~PKSi_69_; + assign n2554 = (~n1140 & n2702) | (n1139_1 & (~n1140 | ~n2702)); + assign n2555 = ~PKSi_157_ | ~PKSi_58_; + assign n2556 = (~n1140 & n2703) | (n1139_1 & (~n1140 | ~n2703)); + assign n2557 = ~PKSi_164_ | ~N_N2774; + assign n2558 = (~n1140 & n2704) | (n1139_1 & (~n1140 | ~n2704)); + assign n2559 = ~PKSi_152_ | ~PKSi_60_; + assign n2560 = (~n1140 & n2705) | (n1139_1 & (~n1140 | ~n2705)); + assign n2561 = ~PKSi_145_ | ~PKSi_51_; + assign n2562 = (~n1140 & n2706) | (n1139_1 & (~n1140 | ~n2706)); + assign n2563 = ~PKSi_161_ | ~N_N2770; + assign n2564 = (~n1140 & n2707) | (n1139_1 & (~n1140 | ~n2707)); + assign n2565 = ~PKSi_64_ | ~N_N2899; + assign n2566 = (~n1140 & n2708) | (n1139_1 & (~n1140 | ~n2708)); + assign n2567 = ~PKSi_149_ | ~PKSi_68_; + assign n2568 = (~n1140 & n2709) | (n1139_1 & (~n1140 | ~n2709)); + assign n2569 = ~PKSi_159_ | ~PKSi_55_; + assign n2570 = (~n1140 & n2710) | (n1139_1 & (~n1140 | ~n2710)); + assign n2571 = ~PKSi_190_ | ~PKSi_76_; + assign n2572 = (~n1140 & n2711) | (n1139_1 & (~n1140 | ~n2711)); + assign n2573 = ~PKSi_174_ | ~PKSi_95_; + assign n2574 = (~n1140 & n2712) | (n1139_1 & (~n1140 | ~n2712)); + assign n2575 = ~PKSi_170_ | ~PKSi_78_; + assign n2576 = (~n1140 & n2713) | (n1139_1 & (~n1140 | ~n2713)); + assign n2577 = ~\[234] | ~PKSi_87_; + assign n2578 = (~n1140 & n2714) | (n1139_1 & (~n1140 | ~n2714)); + assign n2579 = ~PKSi_178_ | ~PKSi_77_; + assign n2580 = (~n1140 & n2715) | (n1139_1 & (~n1140 | ~n2715)); + assign n2581 = ~PKSi_184_ | ~PKSi_81_; + assign n2582 = (~n1140 & n2716) | (n1139_1 & (~n1140 | ~n2716)); + assign n2583 = ~PKSi_91_ | ~N_N2889; + assign n2584 = (~n1140 & n2717) | (n1139_1 & (~n1140 | ~n2717)); + assign n2585 = ~PKSi_189_ | ~PKSi_89_; + assign n2586 = (~n1140 & n2718) | (n1139_1 & (~n1140 | ~n2718)); + assign n2587 = ~PKSi_171_ | ~N_N2757; + assign n2588 = (~n1140 & n2719) | (n1139_1 & (~n1140 | ~n2719)); + assign n2589 = ~PKSi_83_ | ~N_N2885; + assign n2590 = (~n1140 & n2720) | (n1139_1 & (~n1140 | ~n2720)); + assign n2591 = ~PKSi_182_ | ~PKSi_74_; + assign n2592 = (~n1140 & n2721) | (n1139_1 & (~n1140 | ~n2721)); + assign n2593 = ~PKSi_175_ | ~PKSi_86_; + assign n2594 = (~n1140 & n2722) | (n1139_1 & (~n1140 | ~n2722)); + assign n2595 = ~PKSi_94_ | ~N_N2881; + assign n2596 = (~n1140 & n2723) | (n1139_1 & (~n1140 | ~n2723)); + assign n2597 = ~PKSi_72_ | ~N_N2879; + assign n2598 = (~n1140 & n2724) | (n1139_1 & (~n1140 | ~n2724)); + assign n2599 = ~PKSi_80_ | ~N_N2877; + assign n2600 = (~n1140 & n2725) | (n1139_1 & (~n1140 | ~n2725)); + assign n2601 = ~PKSi_180_ | ~N_N2749; + assign n2602 = (~n1140 & n2726) | (n1139_1 & (~n1140 | ~n2726)); + assign n2603 = ~PKSi_177_ | ~PKSi_73_; + assign n2604 = (~n1140 & n2727) | (n1139_1 & (~n1140 | ~n2727)); + assign n2605 = ~PKSi_186_ | ~N_N2746; + assign n2606 = (~n1140 & n2728) | (n1139_1 & (~n1140 | ~n2728)); + assign n2607 = ~PKSi_172_ | ~PKSi_85_; + assign n2608 = (~n1140 & n2729) | (n1139_1 & (~n1140 | ~n2729)); + assign n2609 = ~PKSi_179_ | ~PKSi_93_; + assign n2610 = (~n1140 & n2730) | (n1139_1 & (~n1140 | ~n2730)); + assign n2611 = ~\[253] | ~PKSi_82_; + assign n2612 = (~n1140 & n2731) | (n1139_1 & (~n1140 | ~n2731)); + assign n2613 = ~PKSi_188_ | ~N_N2741; + assign n2614 = (~n1140 & n2732) | (n1139_1 & (~n1140 | ~n2732)); + assign n2615 = ~PKSi_176_ | ~PKSi_84_; + assign n2616 = (~n1140 & n2733) | (n1139_1 & (~n1140 | ~n2733)); + assign n2617 = ~PKSi_169_ | ~PKSi_75_; + assign n2618 = (~n1140 & n2734) | (n1139_1 & (~n1140 | ~n2734)); + assign n2619 = ~PKSi_185_ | ~N_N2737; + assign n2620 = (~n1140 & n2735) | (n1139_1 & (~n1140 | ~n2735)); + assign n2621 = ~\[333] | ~N_N2865; + assign n2622 = (~n1140 & n2736) | (n1139_1 & (~n1140 | ~n2736)); + assign n2623 = ~PKSi_173_ | ~PKSi_92_; + assign n2624 = (~n1140 & n2737) | (n1139_1 & (~n1140 | ~n2737)); + assign n2625 = ~PKSi_183_ | ~PKSi_79_; + assign n2626 = (~n1140 & n2738) | (n1139_1 & (~n1140 | ~n2738)); + assign n2627 = PKSi_4_ | PKSi_118_; + assign n2628 = PKSi_23_ | PKSi_102_; + assign n2629 = PKSi_6_ | PKSi_98_; + assign n2630 = PKSi_15_ | PKSi_119_; + assign n2631 = PKSi_5_ | PKSi_106_; + assign n2632 = PKSi_9_ | PKSi_112_; + assign n2633 = PKSi_19_ | N_N2986; + assign n2634 = PKSi_17_ | PKSi_117_; + assign n2635 = N_N2853 | PKSi_99_; + assign n2636 = PKSi_11_ | N_N2982; + assign n2637 = PKSi_2_ | PKSi_110_; + assign n2638 = PKSi_14_ | PKSi_103_; + assign n2639 = PKSi_22_ | PKSi_96_; + assign n2640 = PKSi_0_ | PKSi_115_; + assign n2641 = PKSi_8_ | N_N2976; + assign n2642 = PKSi_18_ | PKSi_108_; + assign n2643 = PKSi_1_ | PKSi_105_; + assign n2644 = N_N2843 | PKSi_114_; + assign n2645 = PKSi_13_ | PKSi_100_; + assign n2646 = PKSi_21_ | PKSi_107_; + assign n2647 = PKSi_10_ | PKSi_109_; + assign n2648 = N_N2838 | PKSi_116_; + assign n2649 = PKSi_12_ | PKSi_104_; + assign n2650 = PKSi_3_ | PKSi_97_; + assign n2651 = N_N2834 | PKSi_113_; + assign n2652 = PKSi_16_ | N_N2964; + assign n2653 = PKSi_20_ | PKSi_101_; + assign n2654 = PKSi_7_ | PKSi_111_; + assign n2655 = PKSi_28_ | PKSi_142_; + assign n2656 = PKSi_47_ | PKSi_126_; + assign n2657 = PKSi_30_ | PKSi_122_; + assign n2658 = PKSi_39_ | \[282] ; + assign n2659 = PKSi_29_ | PKSi_130_; + assign n2660 = PKSi_33_ | PKSi_136_; + assign n2661 = PKSi_43_ | N_N2954; + assign n2662 = PKSi_41_ | PKSi_141_; + assign n2663 = N_N2821 | PKSi_123_; + assign n2664 = PKSi_35_ | N_N2950; + assign n2665 = PKSi_26_ | PKSi_134_; + assign n2666 = PKSi_38_ | PKSi_127_; + assign n2667 = PKSi_46_ | PKSi_120_; + assign n2668 = PKSi_24_ | N_N2945; + assign n2669 = PKSi_32_ | N_N2943; + assign n2670 = PKSi_42_ | PKSi_132_; + assign n2671 = PKSi_25_ | PKSi_129_; + assign n2672 = N_N2811 | PKSi_138_; + assign n2673 = PKSi_37_ | PKSi_124_; + assign n2674 = PKSi_45_ | PKSi_131_; + assign n2675 = PKSi_34_ | PKSi_133_; + assign n2676 = N_N2806 | PKSi_140_; + assign n2677 = PKSi_36_ | PKSi_128_; + assign n2678 = PKSi_27_ | PKSi_121_; + assign n2679 = N_N2802 | PKSi_137_; + assign n2680 = PKSi_40_ | N_N2931; + assign n2681 = PKSi_44_ | PKSi_125_; + assign n2682 = PKSi_31_ | PKSi_135_; + assign n2683 = PKSi_52_ | PKSi_166_; + assign n2684 = PKSi_71_ | PKSi_150_; + assign n2685 = PKSi_54_ | PKSi_146_; + assign n2686 = PKSi_63_ | PKSi_167_; + assign n2687 = PKSi_53_ | PKSi_154_; + assign n2688 = PKSi_57_ | PKSi_160_; + assign n2689 = PKSi_67_ | N_N2921; + assign n2690 = PKSi_65_ | PKSi_165_; + assign n2691 = N_N2789 | PKSi_147_; + assign n2692 = PKSi_59_ | N_N2917; + assign n2693 = PKSi_50_ | PKSi_158_; + assign n2694 = PKSi_62_ | PKSi_151_; + assign n2695 = PKSi_70_ | PKSi_144_; + assign n2696 = PKSi_48_ | PKSi_163_; + assign n2697 = PKSi_56_ | PKSi_153_; + assign n2698 = PKSi_66_ | PKSi_156_; + assign n2699 = PKSi_49_ | N_N2909; + assign n2700 = N_N2779 | PKSi_162_; + assign n2701 = PKSi_61_ | PKSi_148_; + assign n2702 = PKSi_69_ | PKSi_155_; + assign n2703 = PKSi_58_ | PKSi_157_; + assign n2704 = N_N2774 | PKSi_164_; + assign n2705 = PKSi_60_ | PKSi_152_; + assign n2706 = PKSi_51_ | PKSi_145_; + assign n2707 = N_N2770 | PKSi_161_; + assign n2708 = PKSi_64_ | N_N2899; + assign n2709 = PKSi_68_ | PKSi_149_; + assign n2710 = PKSi_55_ | PKSi_159_; + assign n2711 = PKSi_76_ | PKSi_190_; + assign n2712 = PKSi_95_ | PKSi_174_; + assign n2713 = PKSi_78_ | PKSi_170_; + assign n2714 = PKSi_87_ | \[234] ; + assign n2715 = PKSi_77_ | PKSi_178_; + assign n2716 = PKSi_81_ | PKSi_184_; + assign n2717 = PKSi_91_ | N_N2889; + assign n2718 = PKSi_89_ | PKSi_189_; + assign n2719 = N_N2757 | PKSi_171_; + assign n2720 = PKSi_83_ | N_N2885; + assign n2721 = PKSi_74_ | PKSi_182_; + assign n2722 = PKSi_86_ | PKSi_175_; + assign n2723 = PKSi_94_ | N_N2881; + assign n2724 = PKSi_72_ | N_N2879; + assign n2725 = PKSi_80_ | N_N2877; + assign n2726 = N_N2749 | PKSi_180_; + assign n2727 = PKSi_73_ | PKSi_177_; + assign n2728 = N_N2746 | PKSi_186_; + assign n2729 = PKSi_85_ | PKSi_172_; + assign n2730 = PKSi_93_ | PKSi_179_; + assign n2731 = PKSi_82_ | \[253] ; + assign n2732 = N_N2741 | PKSi_188_; + assign n2733 = PKSi_84_ | PKSi_176_; + assign n2734 = PKSi_75_ | PKSi_169_; + assign n2735 = N_N2737 | PKSi_185_; + assign n2736 = \[333] | N_N2865; + assign n2737 = PKSi_92_ | PKSi_173_; + assign n2738 = PKSi_79_ | PKSi_183_; + assign n2739 = (Pcount_0_ & n2177) | (Pencrypt_0_ & (~Pcount_0_ | n2177)); + assign n2740 = Pcount_0_ | n2177; + assign n2741 = Pcount_1_ | Pcount_2_; + assign PKSi_191_ = \[234] ; + assign PKSi_187_ = \[234] ; + assign PKSi_181_ = \[253] ; + assign PKSi_168_ = \[253] ; + assign PKSi_143_ = \[282] ; + assign PKSi_139_ = \[282] ; + assign PKSi_90_ = \[333] ; + assign PKSi_88_ = \[333] ; + always @ (posedge clock) begin + PKSi_79_ <= n921; + PKSi_92_ <= n925_1; + \[333] <= n929_1; + N_N2737 <= n934_1; + PKSi_75_ <= n939_1; + PKSi_84_ <= n943; + N_N2741 <= n947; + PKSi_82_ <= n952_1; + PKSi_93_ <= n956_1; + PKSi_85_ <= n960_1; + N_N2746 <= n964_1; + PKSi_73_ <= n969; + N_N2749 <= n973; + PKSi_80_ <= n978_1; + PKSi_72_ <= n982_1; + PKSi_94_ <= n986_1; + PKSi_86_ <= n990_1; + PKSi_74_ <= n994_1; + PKSi_83_ <= n998_1; + N_N2757 <= n1002_1; + PKSi_89_ <= n1007; + PKSi_91_ <= n1011; + PKSi_81_ <= n1015; + PKSi_77_ <= n1019; + PKSi_87_ <= n1023; + PKSi_78_ <= n1027; + PKSi_95_ <= n1031; + PKSi_76_ <= n1035; + PKSi_55_ <= n1039; + PKSi_68_ <= n1043; + PKSi_64_ <= n1047; + N_N2770 <= n1051; + PKSi_51_ <= n1056_1; + PKSi_60_ <= n1060_1; + N_N2774 <= n1064_1; + PKSi_58_ <= n1069; + PKSi_69_ <= n1073; + PKSi_61_ <= n1077; + N_N2779 <= n1081; + PKSi_49_ <= n1086_1; + PKSi_66_ <= n1090_1; + PKSi_56_ <= n1094_1; + PKSi_48_ <= n1098_1; + PKSi_70_ <= n1102_1; + PKSi_62_ <= n1106_1; + PKSi_50_ <= n1110_1; + PKSi_59_ <= n1114_1; + N_N2789 <= n1118_1; + PKSi_65_ <= n1123; + PKSi_67_ <= n1127; + PKSi_57_ <= n1131; + PKSi_53_ <= n1135; + PKSi_63_ <= n1139; + PKSi_54_ <= n1143; + PKSi_71_ <= n1147; + PKSi_52_ <= n1151; + PKSi_31_ <= n1155; + PKSi_44_ <= n1159; + PKSi_40_ <= n1163; + N_N2802 <= n1167_1; + PKSi_27_ <= n1172; + PKSi_36_ <= n1176; + N_N2806 <= n1180; + PKSi_34_ <= n1185; + PKSi_45_ <= n1189; + PKSi_37_ <= n1193; + N_N2811 <= n1197; + PKSi_25_ <= n1202; + PKSi_42_ <= n1206; + PKSi_32_ <= n1210; + PKSi_24_ <= n1214; + PKSi_46_ <= n1218; + PKSi_38_ <= n1222; + PKSi_26_ <= n1226; + PKSi_35_ <= n1230; + N_N2821 <= n1234; + PKSi_41_ <= n1239; + PKSi_43_ <= n1243; + PKSi_33_ <= n1247; + PKSi_29_ <= n1251; + PKSi_39_ <= n1255; + PKSi_30_ <= n1259; + PKSi_47_ <= n1263; + PKSi_28_ <= n1267; + PKSi_7_ <= n1271; + PKSi_20_ <= n1275; + PKSi_16_ <= n1279; + N_N2834 <= n1283; + PKSi_3_ <= n1288; + PKSi_12_ <= n1292_1; + N_N2838 <= n1296_1; + PKSi_10_ <= n1301_1; + PKSi_21_ <= n1305_1; + PKSi_13_ <= n1309_1; + N_N2843 <= n1313_1; + PKSi_1_ <= n1318_1; + PKSi_18_ <= n1322_1; + PKSi_8_ <= n1326_1; + PKSi_0_ <= n1330_1; + PKSi_22_ <= n1334_1; + PKSi_14_ <= n1338_1; + PKSi_2_ <= n1342_1; + PKSi_11_ <= n1346_1; + N_N2853 <= n1350_1; + PKSi_17_ <= n1355_1; + PKSi_19_ <= n1359_1; + PKSi_9_ <= n1363_1; + PKSi_5_ <= n1367_1; + PKSi_15_ <= n1371_1; + PKSi_6_ <= n1375_1; + PKSi_23_ <= n1379_1; + PKSi_4_ <= n1383_1; + PKSi_183_ <= n1387_1; + PKSi_173_ <= n1391_1; + N_N2865 <= n1395_1; + PKSi_185_ <= n1400_1; + PKSi_169_ <= n1404_1; + PKSi_176_ <= n1408_1; + PKSi_188_ <= n1412_1; + \[253] <= n1416_1; + PKSi_179_ <= n1421_1; + PKSi_172_ <= n1425_1; + PKSi_186_ <= n1429_1; + PKSi_177_ <= n1433_1; + PKSi_180_ <= n1437_1; + N_N2877 <= n1441_1; + N_N2879 <= n1446_1; + N_N2881 <= n1451_1; + PKSi_175_ <= n1456_1; + PKSi_182_ <= n1460_1; + N_N2885 <= n1464_1; + PKSi_171_ <= n1469_1; + PKSi_189_ <= n1473_1; + N_N2889 <= n1477_1; + PKSi_184_ <= n1482_1; + PKSi_178_ <= n1486_1; + \[234] <= n1490_1; + PKSi_170_ <= n1495_1; + PKSi_174_ <= n1499_1; + PKSi_190_ <= n1503_1; + PKSi_159_ <= n1507_1; + PKSi_149_ <= n1511_1; + N_N2899 <= n1515; + PKSi_161_ <= n1520_1; + PKSi_145_ <= n1524_1; + PKSi_152_ <= n1528_1; + PKSi_164_ <= n1532_1; + PKSi_157_ <= n1536_1; + PKSi_155_ <= n1540_1; + PKSi_148_ <= n1544_1; + PKSi_162_ <= n1548_1; + N_N2909 <= n1552_1; + PKSi_156_ <= n1557_1; + PKSi_153_ <= n1561_1; + PKSi_163_ <= n1565_1; + PKSi_144_ <= n1569_1; + PKSi_151_ <= n1573_1; + PKSi_158_ <= n1577_1; + N_N2917 <= n1581_1; + PKSi_147_ <= n1586_1; + PKSi_165_ <= n1590_1; + N_N2921 <= n1594_1; + PKSi_160_ <= n1599_1; + PKSi_154_ <= n1603_1; + PKSi_167_ <= n1607_1; + PKSi_146_ <= n1611_1; + PKSi_150_ <= n1615_1; + PKSi_166_ <= n1619_1; + PKSi_135_ <= n1623_1; + PKSi_125_ <= n1627_1; + N_N2931 <= n1631_1; + PKSi_137_ <= n1636_1; + PKSi_121_ <= n1640_1; + PKSi_128_ <= n1644_1; + PKSi_140_ <= n1648_1; + PKSi_133_ <= n1652_1; + PKSi_131_ <= n1656_1; + PKSi_124_ <= n1660_1; + PKSi_138_ <= n1664_1; + PKSi_129_ <= n1668_1; + PKSi_132_ <= n1672_1; + N_N2943 <= n1676_1; + N_N2945 <= n1681_1; + PKSi_120_ <= n1686_1; + PKSi_127_ <= n1690_1; + PKSi_134_ <= n1694_1; + N_N2950 <= n1698_1; + PKSi_123_ <= n1703_1; + PKSi_141_ <= n1707_1; + N_N2954 <= n1711_1; + PKSi_136_ <= n1716_1; + PKSi_130_ <= n1720_1; + \[282] <= n1724_1; + PKSi_122_ <= n1729_1; + PKSi_126_ <= n1733_1; + PKSi_142_ <= n1737_1; + PKSi_111_ <= n1741_1; + PKSi_101_ <= n1745; + N_N2964 <= n1749; + PKSi_113_ <= n1754_1; + PKSi_97_ <= n1758_1; + PKSi_104_ <= n1762_1; + PKSi_116_ <= n1766_1; + PKSi_109_ <= n1770_1; + PKSi_107_ <= n1774_1; + PKSi_100_ <= n1778_1; + PKSi_114_ <= n1782_1; + PKSi_105_ <= n1786_1; + PKSi_108_ <= n1790_1; + N_N2976 <= n1794_1; + PKSi_115_ <= n1799; + PKSi_96_ <= n1803; + PKSi_103_ <= n1807; + PKSi_110_ <= n1811; + N_N2982 <= n1815; + PKSi_99_ <= n1820_1; + PKSi_117_ <= n1824_1; + N_N2986 <= n1828_1; + PKSi_112_ <= n1833; + PKSi_106_ <= n1837; + PKSi_119_ <= n1841; + PKSi_98_ <= n1845; + PKSi_102_ <= n1849; + PKSi_118_ <= n1853; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/clma/clma.v b/openfpga_flow/benchmarks/MCNC_Verilog/clma/clma.v new file mode 100644 index 000000000..c73b12461 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/clma/clma.v @@ -0,0 +1,4776 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 09:55:52 2019 + +module clma ( clock, + Pi416, Pi415, Pi414, Pi413, Pi412, Pi411, Pi410, Pi409, Pi408, Pi407, + Pi406, Pi405, Pi404, Pi403, Pi402, Pi401, Pi400, Pi399, Pi398, Pi397, + Pi396, Pi395, Pi394, Pi393, Pi392, Pi391, Pi390, Pi389, Pi388, Pi387, + Pi386, Pi385, Pi384, Pi383, Pi382, Pi381, Pi380, Pi379, Pi378, Pi377, + Pi376, Pi375, Pi374, Pi373, Pi372, Pi371, Pi370, Pi369, Pi368, Pi367, + Pi366, Pi365, Pi364, Pi363, Pi362, Pi361, Pi360, Pi359, Pi358, Pi357, + Pi356, Pi355, Pi354, Pi353, Pi352, Pi351, Pi350, Pi349, Pi348, Pi347, + Pi346, Pi345, Pi344, Pi343, Pi342, Pi341, Pi340, Pi339, Pi338, Pi337, + Pi336, Pi335, Pi334, Pi333, Pi332, Pi331, Pi330, Pi329, Pi328, Pi327, + Pi326, Pi325, Pi324, Pi323, Pi322, Pi321, Pi320, Pi319, Pi318, Pi317, + Pi316, Pi315, Pi314, Pi313, Pi312, Pi311, Pi310, Pi309, Pi308, Pi307, + Pi306, Pi305, Pi304, Pi303, Pi302, Pi301, Pi300, Pi299, Pi298, Pi297, + Pi296, Pi295, Pi294, Pi293, Pi292, Pi291, Pi290, Pi289, Pi288, Pi287, + Pi286, Pi285, Pi284, Pi283, Pi282, Pi281, Pi280, Pi279, Pi278, Pi277, + Pi276, Pi275, Pi274, Pi273, Pi272, Pi271, Pi270, Pi269, Pi268, Pi267, + Pi266, Pi265, Pi264, Pi263, Pi262, Pi261, Pi260, Pi259, Pi258, Pi257, + Pi256, Pi255, Pi254, Pi253, Pi252, Pi251, Pi250, Pi249, Pi248, Pi247, + Pi246, Pi245, Pi244, Pi243, Pi242, Pi241, Pi240, Pi239, Pi238, Pi237, + Pi236, Pi235, Pi234, Pi233, Pi232, Pi231, Pi230, Pi229, Pi228, Pi227, + Pi226, Pi225, Pi224, Pi223, Pi222, Pi221, Pi220, Pi219, Pi218, Pi217, + Pi216, Pi215, Pi214, Pi213, Pi212, Pi211, Pi210, Pi209, Pi208, Pi207, + Pi206, Pi205, Pi204, Pi203, Pi202, Pi201, Pi200, Pi199, Pi198, Pi197, + Pi196, Pi195, Pi194, Pi193, Pi192, Pi191, Pi190, Pi189, Pi188, Pi187, + Pi186, Pi185, Pi184, Pi183, Pi182, Pi181, Pi180, Pi179, Pi178, Pi177, + Pi176, Pi175, Pi174, Pi173, Pi172, Pi171, Pi170, Pi169, Pi168, Pi167, + Pi166, Pi165, Pi164, Pi163, Pi162, Pi161, Pi160, Pi159, Pi158, Pi157, + Pi156, Pi155, Pi154, Pi153, Pi152, Pi151, Pi150, Pi149, Pi148, Pi147, + Pi146, Pi145, Pi144, Pi143, Pi142, Pi141, Pi140, Pi139, Pi138, Pi137, + Pi136, Pi135, Pi134, Pi133, Pi132, Pi131, Pi130, Pi129, Pi128, Pi127, + Pi126, Pi125, Pi124, Pi123, Pi122, Pi121, Pi120, Pi119, Pi118, Pi117, + Pi116, Pi115, Pi114, Pi113, Pi112, Pi111, Pi110, Pi109, Pi108, Pi107, + Pi106, Pi105, Pi104, Pi103, Pi102, Pi101, Pi100, Pi99, Pi98, Pi97, + Pi96, Pi95, Pi94, Pi93, Pi92, Pi91, Pi90, Pi89, Pi88, Pi87, Pi86, Pi85, + Pi84, Pi83, Pi82, Pi81, Pi80, Pi79, Pi78, Pi77, Pi76, Pi75, Pi74, Pi73, + Pi72, Pi71, Pi70, Pi69, Pi68, Pi67, Pi66, Pi65, Pi64, Pi63, Pi62, Pi61, + Pi60, Pi59, Pi58, Pi57, Pi56, Pi55, Pi54, Pi53, Pi52, Pi51, Pi50, Pi49, + Pi28, Pi27, Pi26, Pi25, Pi24, Pi23, Pi22, Pi21, Pi20, Pi19, Pi18, Pi17, + Pi16, Pi15, + P__cmxir_1, P__cmxir_0, P__cmxig_1, P__cmxig_0, P__cmxcl_1, P__cmxcl_0, + P__cmx1ad_35, P__cmx1ad_34, P__cmx1ad_33, P__cmx1ad_32, P__cmx1ad_31, + P__cmx1ad_30, P__cmx1ad_29, P__cmx1ad_28, P__cmx1ad_27, P__cmx1ad_26, + P__cmx1ad_25, P__cmx1ad_24, P__cmx1ad_23, P__cmx1ad_22, P__cmx1ad_21, + P__cmx1ad_20, P__cmx1ad_19, P__cmx1ad_18, P__cmx1ad_17, P__cmx1ad_16, + P__cmx1ad_15, P__cmx1ad_14, P__cmx1ad_13, P__cmx1ad_12, P__cmx1ad_11, + P__cmx1ad_10, P__cmx1ad_9, P__cmx1ad_8, P__cmx1ad_7, P__cmx1ad_6, + P__cmx1ad_5, P__cmx1ad_4, P__cmx1ad_3, P__cmx1ad_2, P__cmx1ad_1, + P__cmx1ad_0, P__cmx0ad_35, P__cmx0ad_34, P__cmx0ad_33, P__cmx0ad_32, + P__cmx0ad_31, P__cmx0ad_30, P__cmx0ad_29, P__cmx0ad_28, P__cmx0ad_27, + P__cmx0ad_26, P__cmx0ad_25, P__cmx0ad_24, P__cmx0ad_23, P__cmx0ad_22, + P__cmx0ad_21, P__cmx0ad_20, P__cmx0ad_19, P__cmx0ad_18, P__cmx0ad_17, + P__cmx0ad_16, P__cmx0ad_15, P__cmx0ad_14, P__cmx0ad_13, P__cmx0ad_12, + P__cmx0ad_11, P__cmx0ad_10, P__cmx0ad_9, P__cmx0ad_8, P__cmx0ad_7, + P__cmx0ad_6, P__cmx0ad_5, P__cmx0ad_4, P__cmx0ad_3, P__cmx0ad_2, + P__cmx0ad_1, P__cmx0ad_0, P__cmnxcp_1, P__cmnxcp_0, P__cmndst1p0, + P__cmndst0p0 ); + input Pi416, Pi415, Pi414, Pi413, Pi412, Pi411, Pi410, Pi409, Pi408, + Pi407, Pi406, Pi405, Pi404, Pi403, Pi402, Pi401, Pi400, Pi399, Pi398, + Pi397, Pi396, Pi395, Pi394, Pi393, Pi392, Pi391, Pi390, Pi389, Pi388, + Pi387, Pi386, Pi385, Pi384, Pi383, Pi382, Pi381, Pi380, Pi379, Pi378, + Pi377, Pi376, Pi375, Pi374, Pi373, Pi372, Pi371, Pi370, Pi369, Pi368, + Pi367, Pi366, Pi365, Pi364, Pi363, Pi362, Pi361, Pi360, Pi359, Pi358, + Pi357, Pi356, Pi355, Pi354, Pi353, Pi352, Pi351, Pi350, Pi349, Pi348, + Pi347, Pi346, Pi345, Pi344, Pi343, Pi342, Pi341, Pi340, Pi339, Pi338, + Pi337, Pi336, Pi335, Pi334, Pi333, Pi332, Pi331, Pi330, Pi329, Pi328, + Pi327, Pi326, Pi325, Pi324, Pi323, Pi322, Pi321, Pi320, Pi319, Pi318, + Pi317, Pi316, Pi315, Pi314, Pi313, Pi312, Pi311, Pi310, Pi309, Pi308, + Pi307, Pi306, Pi305, Pi304, Pi303, Pi302, Pi301, Pi300, Pi299, Pi298, + Pi297, Pi296, Pi295, Pi294, Pi293, Pi292, Pi291, Pi290, Pi289, Pi288, + Pi287, Pi286, Pi285, Pi284, Pi283, Pi282, Pi281, Pi280, Pi279, Pi278, + Pi277, Pi276, Pi275, Pi274, Pi273, Pi272, Pi271, Pi270, Pi269, Pi268, + Pi267, Pi266, Pi265, Pi264, Pi263, Pi262, Pi261, Pi260, Pi259, Pi258, + Pi257, Pi256, Pi255, Pi254, Pi253, Pi252, Pi251, Pi250, Pi249, Pi248, + Pi247, Pi246, Pi245, Pi244, Pi243, Pi242, Pi241, Pi240, Pi239, Pi238, + Pi237, Pi236, Pi235, Pi234, Pi233, Pi232, Pi231, Pi230, Pi229, Pi228, + Pi227, Pi226, Pi225, Pi224, Pi223, Pi222, Pi221, Pi220, Pi219, Pi218, + Pi217, Pi216, Pi215, Pi214, Pi213, Pi212, Pi211, Pi210, Pi209, Pi208, + Pi207, Pi206, Pi205, Pi204, Pi203, Pi202, Pi201, Pi200, Pi199, Pi198, + Pi197, Pi196, Pi195, Pi194, Pi193, Pi192, Pi191, Pi190, Pi189, Pi188, + Pi187, Pi186, Pi185, Pi184, Pi183, Pi182, Pi181, Pi180, Pi179, Pi178, + Pi177, Pi176, Pi175, Pi174, Pi173, Pi172, Pi171, Pi170, Pi169, Pi168, + Pi167, Pi166, Pi165, Pi164, Pi163, Pi162, Pi161, Pi160, Pi159, Pi158, + Pi157, Pi156, Pi155, Pi154, Pi153, Pi152, Pi151, Pi150, Pi149, Pi148, + Pi147, Pi146, Pi145, Pi144, Pi143, Pi142, Pi141, Pi140, Pi139, Pi138, + Pi137, Pi136, Pi135, Pi134, Pi133, Pi132, Pi131, Pi130, Pi129, Pi128, + Pi127, Pi126, Pi125, Pi124, Pi123, Pi122, Pi121, Pi120, Pi119, Pi118, + Pi117, Pi116, Pi115, Pi114, Pi113, Pi112, Pi111, Pi110, Pi109, Pi108, + Pi107, Pi106, Pi105, Pi104, Pi103, Pi102, Pi101, Pi100, Pi99, Pi98, + Pi97, Pi96, Pi95, Pi94, Pi93, Pi92, Pi91, Pi90, Pi89, Pi88, Pi87, Pi86, + Pi85, Pi84, Pi83, Pi82, Pi81, Pi80, Pi79, Pi78, Pi77, Pi76, Pi75, Pi74, + Pi73, Pi72, Pi71, Pi70, Pi69, Pi68, Pi67, Pi66, Pi65, Pi64, Pi63, Pi62, + Pi61, Pi60, Pi59, Pi58, Pi57, Pi56, Pi55, Pi54, Pi53, Pi52, Pi51, Pi50, + Pi49, Pi28, Pi27, Pi26, Pi25, Pi24, Pi23, Pi22, Pi21, Pi20, Pi19, Pi18, + Pi17, Pi16, Pi15, clock; + output P__cmxir_1, P__cmxir_0, P__cmxig_1, P__cmxig_0, P__cmxcl_1, + P__cmxcl_0, P__cmx1ad_35, P__cmx1ad_34, P__cmx1ad_33, P__cmx1ad_32, + P__cmx1ad_31, P__cmx1ad_30, P__cmx1ad_29, P__cmx1ad_28, P__cmx1ad_27, + P__cmx1ad_26, P__cmx1ad_25, P__cmx1ad_24, P__cmx1ad_23, P__cmx1ad_22, + P__cmx1ad_21, P__cmx1ad_20, P__cmx1ad_19, P__cmx1ad_18, P__cmx1ad_17, + P__cmx1ad_16, P__cmx1ad_15, P__cmx1ad_14, P__cmx1ad_13, P__cmx1ad_12, + P__cmx1ad_11, P__cmx1ad_10, P__cmx1ad_9, P__cmx1ad_8, P__cmx1ad_7, + P__cmx1ad_6, P__cmx1ad_5, P__cmx1ad_4, P__cmx1ad_3, P__cmx1ad_2, + P__cmx1ad_1, P__cmx1ad_0, P__cmx0ad_35, P__cmx0ad_34, P__cmx0ad_33, + P__cmx0ad_32, P__cmx0ad_31, P__cmx0ad_30, P__cmx0ad_29, P__cmx0ad_28, + P__cmx0ad_27, P__cmx0ad_26, P__cmx0ad_25, P__cmx0ad_24, P__cmx0ad_23, + P__cmx0ad_22, P__cmx0ad_21, P__cmx0ad_20, P__cmx0ad_19, P__cmx0ad_18, + P__cmx0ad_17, P__cmx0ad_16, P__cmx0ad_15, P__cmx0ad_14, P__cmx0ad_13, + P__cmx0ad_12, P__cmx0ad_11, P__cmx0ad_10, P__cmx0ad_9, P__cmx0ad_8, + P__cmx0ad_7, P__cmx0ad_6, P__cmx0ad_5, P__cmx0ad_4, P__cmx0ad_3, + P__cmx0ad_2, P__cmx0ad_1, P__cmx0ad_0, P__cmnxcp_1, P__cmnxcp_0, + P__cmndst1p0, P__cmndst0p0; + reg Ni48, Ni47, Ni46, Ni45, Ni44, Ni43, Ni42, Ni41, Ni40, Ni39, Ni38, + Ni37, Ni36, Ni35, Ni34, Ni33, Ni32, Ni31, Ni30, n18, Ni14, Ni13, Ni12, + Ni11, Ni10, Ni9, Ni8, Ni7, Ni6, Ni5, Ni4, Ni3, Ni2; + wire n646, n648, n649, n651, n653, n654, n655, n656, n658, n660, n662, + n663, n664, n665, n666, n668, n670, n672, n674, n675, n676, n677, n678, + n679, n681, n683, n684, n686, n688, n689, n690, n691, n692, n693, n694, + n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, + n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, + n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, + n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, + n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, + n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, + n767, n768, n770, n772, n773, n774, n776, n778, n780, n781, n783, n784, + n785, n786, n787, n788, n789, n790, n792, n793, n794, n795, n796, n797, + n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, + n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, + n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, + n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, + n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, + n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, + n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, + n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, + n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, + n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, + n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, + n930, n931, n932, n933, n934, n935, n936_1, n937, n938, n939, n940, + n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, + n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, + n965, n966, n967, n968, n969, n970, n971_1, n972, n973, n974, n975, + n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986_1, + n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, + n999, n1000, n1001_1, n1002, n1003, n1004, n1005, n1006, n1007, n1008, + n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, + n1019, n1020, n1021_1, n1022, n1023, n1024, n1025, n1026, n1027, n1028, + n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036_1, n1037, n1038, + n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, + n1049, n1050, n1051_1, n1052, n1053, n1054, n1055, n1056, n1057, n1058, + n1059, n1060, n1061_1, n1062, n1063, n1064, n1065, n1066, n1067, n1068, + n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076_1, n1077, n1078, + n1079, n1080, n1081_1, n1082, n1083, n1084, n1085_1, n1086, n1087, + n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, + n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, + n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, + n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, + n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, + n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, + n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, + n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, + n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, + n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, + n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, + n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, + n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, + n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, + n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, + n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, + n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, + n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, + n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, + n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, + n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, + n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, + n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, + n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, + n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, + n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, + n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, + n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, + n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, + n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, + n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, + n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, + n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, + n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, + n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, + n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, + n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, + n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, + n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, + n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, + n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, + n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, + n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, + n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, + n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, + n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, + n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, + n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, + n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, + n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, + n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, + n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, + n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, + n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, + n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, + n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, + n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, + n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, + n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, + n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, + n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, + n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, + n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, + n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, + n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, + n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, + n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, + n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, + n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, + n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, + n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, + n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, + n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, + n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, + n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, + n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, + n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, + n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, + n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, + n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, + n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, + n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, + n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, + n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, + n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, + n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, + n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, + n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, + n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, + n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, + n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, + n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, + n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, + n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, + n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, + n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, + n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, + n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, + n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, + n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, + n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, + n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, + n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, + n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, + n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, + n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, + n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, + n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, + n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, + n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, + n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, + n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, + n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, + n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, + n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, + n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, + n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, + n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, + n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, + n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, + n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, + n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, + n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, + n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, + n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, + n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, + n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, + n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, + n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, + n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, + n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, + n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, + n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, + n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, + n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, + n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, + n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, + n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, + n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, + n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, + n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, + n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, + n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, + n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, + n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, + n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, + n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, + n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, + n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, + n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, + n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, + n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, + n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, + n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, + n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, + n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, + n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, + n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, + n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, + n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, + n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, + n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, + n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, + n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, + n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, + n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, + n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, + n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, + n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, + n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, + n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, + n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, + n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, + n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, + n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, + n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, + n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, + n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, + n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, + n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, + n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, + n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, + n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, + n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, + n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, + n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, + n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, + n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, + n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, + n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, + n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, + n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, + n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, + n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, + n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, + n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, + n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, + n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, + n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, + n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, + n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, + n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, + n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, + n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, + n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, + n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, + n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, + n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, + n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, + n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, + n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, + n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, + n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, + n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, + n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, + n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, + n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, + n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, + n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, + n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, + n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, + n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, + n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, + n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, + n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, + n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, + n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, + n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, + n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, + n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, + n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, + n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, + n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, + n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, + n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, + n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, + n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, + n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, + n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, + n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, + n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, + n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, + n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, + n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, + n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, + n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, + n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, + n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, + n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, + n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, + n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, + n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, + n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, + n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, + n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, + n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, + n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, + n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, + n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, + n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, + n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, + n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, + n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, + n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, + n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, + n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, + n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, + n3758, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, + n3769, n3770, n3771, n3772, n3773, n3775, n3777, n3779, n3780, n3781, + n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, + n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, + n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, + n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, + n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, + n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, + n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, + n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, + n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, + n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, + n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, + n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, + n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, + n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, + n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, + n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, + n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, + n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, + n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, + n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, + n3983, n3984, n3985, n3986, n3987, n3989, n3990, n3991, n3992, n3993, + n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, + n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, + n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, + n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, + n4034, n4035, n4037, n4038, n4039, n4040, n4042, n4044, n4045, n4046, + n4048, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, + n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, + n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, + n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, + n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, + n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, + n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, + n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, + n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, + n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, + n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, + n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, + n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, + n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, + n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, + n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, + n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, + n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, + n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, + n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, + n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, + n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, + n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, + n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, + n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, + n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, + n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, + n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, + n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, + n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, + n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, + n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, + n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, + n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, + n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, + n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, + n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, + n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, + n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, + n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, + n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, + n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, + n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, + n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, + n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, + n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, + n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, + n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, + n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, + n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, + n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, + n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, + n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, + n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, + n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, + n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, + n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, + n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, + n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, + n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, + n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, + n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, + n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, + n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, + n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, + n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, + n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, + n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, + n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, + n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, + n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, + n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, + n4769, n4770, n4771, n4772, n4773, n4774, n4775, n931_1, n936, n941_1, + n946_1, n951_1, n956_1, n961_1, n966_1, n971, n976_1, n981_1, n986, + n991_1, n996_1, n1001, n1006_1, n1011_1, n1016_1, n1021, n1026_1, + n1031_1, n1036, n1041_1, n1046_1, n1051, n1056_1, n1061, n1066_1, + n1071_1, n1076, n1081, n1085, n1090_1; + assign P__cmxir_1 = n785 & ~n3327 & ~n3707; + assign P__cmxir_0 = ~n773 & ~n3659; + assign P__cmxig_1 = ~n785; + assign P__cmxig_0 = ~n3950; + assign P__cmxcl_1 = ~n3707; + assign P__cmxcl_0 = ~n3707; + assign P__cmx1ad_35 = 1'b0; + assign P__cmx1ad_34 = 1'b0; + assign P__cmx1ad_33 = 1'b0; + assign P__cmx1ad_32 = 1'b0; + assign P__cmx1ad_31 = Pi255 & ~n3985; + assign P__cmx1ad_30 = Pi254 & ~n3985; + assign P__cmx1ad_29 = Pi253 & ~n3985; + assign P__cmx1ad_28 = Pi252 & ~n3985; + assign P__cmx1ad_27 = Pi251 & ~n3985; + assign P__cmx1ad_26 = Pi250 & ~n3985; + assign P__cmx1ad_25 = Pi249 & ~n3985; + assign P__cmx1ad_24 = Pi248 & ~n3985; + assign P__cmx1ad_23 = Pi247 & ~n3985; + assign P__cmx1ad_22 = Pi246 & ~n3985; + assign P__cmx1ad_21 = Pi245 & ~n3985; + assign P__cmx1ad_20 = Pi244 & ~n3985; + assign P__cmx1ad_19 = Pi243 & ~n3985; + assign P__cmx1ad_18 = Pi242 & ~n3985; + assign P__cmx1ad_17 = Pi241 & ~n3985; + assign P__cmx1ad_16 = Pi240 & ~n3985; + assign P__cmx1ad_15 = ~n3985 & Pi27 & Pi26; + assign P__cmx1ad_14 = ~n4051; + assign P__cmx1ad_13 = n789 & ~n3985; + assign P__cmx1ad_12 = ~n4760; + assign P__cmx1ad_11 = 1'b0; + assign P__cmx1ad_10 = 1'b0; + assign P__cmx1ad_9 = ~n3985; + assign P__cmx1ad_8 = 1'b0; + assign P__cmx1ad_7 = Pi239 & ~n3985; + assign P__cmx1ad_6 = Pi238 & ~n3985; + assign P__cmx1ad_5 = Pi237 & ~n3985; + assign P__cmx1ad_4 = Pi236 & ~n3985; + assign P__cmx1ad_3 = Pi235 & ~n3985; + assign P__cmx1ad_2 = Pi234 & ~n3985; + assign P__cmx1ad_1 = Pi233 & ~n3985; + assign P__cmx1ad_0 = Pi232 & ~n3985; + assign P__cmx0ad_35 = 1'b0; + assign P__cmx0ad_34 = 1'b0; + assign P__cmx0ad_33 = 1'b0; + assign P__cmx0ad_32 = 1'b0; + assign P__cmx0ad_31 = Pi72 & ~n3986; + assign P__cmx0ad_30 = Pi71 & ~n3986; + assign P__cmx0ad_29 = Pi70 & ~n3986; + assign P__cmx0ad_28 = Pi69 & ~n3986; + assign P__cmx0ad_27 = Pi68 & ~n3986; + assign P__cmx0ad_26 = Pi67 & ~n3986; + assign P__cmx0ad_25 = Pi66 & ~n3986; + assign P__cmx0ad_24 = Pi65 & ~n3986; + assign P__cmx0ad_23 = Pi64 & ~n3986; + assign P__cmx0ad_22 = Pi63 & ~n3986; + assign P__cmx0ad_21 = Pi62 & ~n3986; + assign P__cmx0ad_20 = Pi61 & ~n3986; + assign P__cmx0ad_19 = Pi60 & ~n3986; + assign P__cmx0ad_18 = Pi59 & ~n3986; + assign P__cmx0ad_17 = Pi58 & ~n3986; + assign P__cmx0ad_16 = Pi57 & ~n3986; + assign P__cmx0ad_15 = ~n3986 & Pi24 & Pi23; + assign P__cmx0ad_14 = ~n4052; + assign P__cmx0ad_13 = n788 & ~n3986; + assign P__cmx0ad_12 = ~n4762; + assign P__cmx0ad_11 = 1'b0; + assign P__cmx0ad_10 = 1'b0; + assign P__cmx0ad_9 = ~n3986; + assign P__cmx0ad_8 = 1'b0; + assign P__cmx0ad_7 = Pi56 & ~n3986; + assign P__cmx0ad_6 = Pi55 & ~n3986; + assign P__cmx0ad_5 = Pi54 & ~n3986; + assign P__cmx0ad_4 = Pi53 & ~n3986; + assign P__cmx0ad_3 = Pi52 & ~n3986; + assign P__cmx0ad_2 = Pi51 & ~n3986; + assign P__cmx0ad_1 = Pi50 & ~n3986; + assign P__cmx0ad_0 = Pi49 & ~n3986; + assign P__cmnxcp_1 = ~n787; + assign P__cmnxcp_0 = ~n786; + assign P__cmndst1p0 = n784 & ~n3754; + assign P__cmndst0p0 = n783 & ~n3984; + assign n646 = ~n3662 & (~Ni48 | (~Pi22 & n3663)); + assign n931_1 = ~n646; + assign n648 = ~n904 & n3185 & (Pi20 | n3186); + assign n649 = Ni46 & (Pi21 | (~Ni32 & ~n2416)); + assign n941_1 = n648 | n649; + assign n651 = ~n3829 & (~Ni44 | ~n3751); + assign n951_1 = ~n651; + assign n653 = Ni44 ^ ~Ni39; + assign n654 = n653 & Ni38; + assign n655 = n653 & Ni32 & (Ni37 | n654); + assign n656 = n3190 & (n2398 | ~Ni41); + assign n966_1 = ~n656; + assign n658 = n3188 & (n2398 | ~Ni40); + assign n971 = ~n658; + assign n660 = n2391 & (n665 | ~Ni39); + assign n976_1 = ~n660; + assign n662 = ~n3183 & (~n1241 | ~n2389) & ~n3864; + assign n663 = ~n1322 & ~n3183 & (n808 | ~n995); + assign n664 = Pi15 & ~n741 & ~n3984; + assign n665 = ~Ni32 & n2406; + assign n666 = ~n3984 & ~n3183 & n3184; + assign n981_1 = ~n4774 | n665 | n666 | n664 | n662 | n663; + assign n668 = ~n2404 & (~Ni36 | n2398) & n2405; + assign n991_1 = ~n668; + assign n670 = ~n2396 & n2397 & (~Ni35 | n2398); + assign n996_1 = ~n670; + assign n672 = ~n2388 & ~n3806 & (~Ni34 | ~n3707); + assign n1001 = ~n672; + assign n674 = ~Ni42 & (~Ni44 | ~n738); + assign n675 = ~Ni42 & (Ni44 | ~n738); + assign n676 = ~Ni47 & ~Ni45; + assign n677 = ~Ni42 | Ni43; + assign n678 = n676 & n677; + assign n679 = n3658 & (n3659 | (~n3657 & n3660)); + assign n1006_1 = ~n679; + assign n681 = ~n3181 & n3182 & (~n2073 | ~n4431); + assign n1011_1 = ~n681; + assign n683 = n2078 & (~n678 | ~n814) & ~n3707; + assign n684 = ~n3707 & n2254 & ~Ni32 & ~Ni30; + assign n1016_1 = Ni31 | n683 | n684; + assign n686 = n2076 & n2077 & (~Ni30 | ~n3707); + assign n1021 = ~n686; + assign n688 = n1393 & n1394 & (n689 | n1395); + assign n689 = n4769 & n713; + assign n690 = ~n814 | ~Ni36; + assign n691 = n688 & ~n1539 & (n689 | n690); + assign n692 = n1393 & n1394 & (n693 | n1398); + assign n693 = n4770 & n713; + assign n694 = n692 & ~n1539 & (n690 | n693); + assign n695 = n985 & (n697 | ~Ni38); + assign n696 = ~n1539 & (n744 | ~Ni35); + assign n697 = n713 & (n689 | ~Ni40); + assign n698 = Ni37 | ~Ni36; + assign n699 = n695 & n696 & (n697 | n698); + assign n700 = n985 & (n702 | ~Ni38); + assign n701 = ~n1539 & (n746 | ~Ni35); + assign n702 = n713 & (n693 | ~Ni40); + assign n703 = n700 & n701 & (n702 | n698); + assign n704 = n985 & (n706 | ~Ni38); + assign n705 = ~n1539 & (Ni35 | n748); + assign n706 = n713 & (Ni40 | n689); + assign n707 = n704 & n705 & (n706 | n698); + assign n708 = n985 & (n710 | ~Ni38); + assign n709 = ~n1539 & (Ni35 | n750); + assign n710 = n713 & (Ni40 | n693); + assign n711 = n708 & n709 & (n710 | n698); + assign n712 = n985 & (n713 | ~Ni38); + assign n713 = n738 & (n1351 | ~Ni41); + assign n714 = n712 & ~n1539 & (n698 | n713); + assign n715 = n1393 & n1394 & (n716 | n1395); + assign n716 = n738 & n4769; + assign n717 = n715 & ~n1539 & (n690 | n716); + assign n718 = n1393 & n1394 & (n719 | n1398); + assign n719 = n738 & n4770; + assign n720 = n718 & ~n1539 & (n690 | n719); + assign n721 = n985 & (n723 | ~Ni38); + assign n722 = (~Ni35 | n754) & ~n1539; + assign n723 = n738 & (n716 | ~Ni40); + assign n724 = n721 & n722 & (n723 | n698); + assign n725 = n985 & (n727 | ~Ni38); + assign n726 = (~Ni35 | n756) & ~n1539; + assign n727 = n738 & (n719 | ~Ni40); + assign n728 = n725 & n726 & (n727 | n698); + assign n729 = n985 & (n731 | ~Ni38); + assign n730 = ~n1539 & (Ni35 | n758); + assign n731 = n738 & (Ni40 | n716); + assign n732 = n729 & n730 & (n731 | n698); + assign n733 = n985 & (n735 | ~Ni38); + assign n734 = ~n1539 & (Ni35 | n760); + assign n735 = n738 & (Ni40 | n719); + assign n736 = n733 & n734 & (n735 | n698); + assign n737 = n985 & (n738 | ~Ni38); + assign n738 = n676 & ~Ni43; + assign n739 = n737 & ~n1539 & (n698 | n738); + assign n740 = n985 & ~n1539; + assign n741 = ~Ni36 | ~Ni38; + assign n742 = n688 & n740 & (n689 | n741); + assign n743 = n692 & n740 & (n693 | n741); + assign n744 = n697 | n817; + assign n745 = n695 & ~n1539 & (n744 | ~Ni35); + assign n746 = n702 | n853; + assign n747 = n700 & ~n1539 & (n746 | ~Ni35); + assign n748 = n706 | n817; + assign n749 = n704 & ~n1539 & (Ni35 | n748); + assign n750 = n710 | n853; + assign n751 = n708 & ~n1539 & (Ni35 | n750); + assign n752 = n740 & n715 & (n716 | n741); + assign n753 = n740 & n718 & (n719 | n741); + assign n754 = n723 | n817; + assign n755 = n721 & ~n1539 & (~Ni35 | n754); + assign n756 = n727 | n853; + assign n757 = n725 & ~n1539 & (~Ni35 | n756); + assign n758 = n731 | n817; + assign n759 = n729 & ~n1539 & (Ni35 | n758); + assign n760 = n735 | n853; + assign n761 = n733 & ~n1539 & (Ni35 | n760); + assign n762 = Ni47 | n923; + assign n763 = (~Ni44 | n762) & ~Ni41; + assign n764 = Ni45 | n923; + assign n765 = (~Ni44 | n764) & ~Ni41; + assign n766 = ~Ni41 & (Ni44 | n762); + assign n767 = ~Ni41 & (Ni44 | n764); + assign n768 = ~n3731 & (~Ni14 | (n3711 & ~Ni2)); + assign n1031_1 = ~n768; + assign n770 = n3726 & (~Ni13 | (~n3707 & ~n3727)); + assign n1036 = ~n770; + assign n772 = ~Pi25 | Ni10; + assign n773 = n772 & ~Ni9 & (~Ni10 | ~n3950); + assign n774 = n3718 & (~Ni9 | (~n3707 & ~n3957)); + assign n1056_1 = ~n774; + assign n776 = (n2403 | n3707) & (~Ni8 | n3715); + assign n1061 = ~n776; + assign n778 = n3713 & (Ni6 | n3712) & ~n4756; + assign n1071_1 = ~n778; + assign n780 = Ni6 & ~n3843 & (~n3668 | ~n3982); + assign n781 = n3709 & n3710 & (n2418 | n3708); + assign n1076 = ~n781; + assign n783 = ~Ni37 & Ni38; + assign n784 = ~Ni32 | ~Ni30; + assign n785 = ~n18 | ~Ni33; + assign n786 = n3770 & n3771 & (n3769 | n3707); + assign n787 = ~n3763 & (n3707 | n3762) & n3764; + assign n788 = Pi23 | Pi24; + assign n789 = Pi26 | Pi27; + assign n790 = n3751 & (~n784 | (n3752 & n3753)); + assign n956_1 = ~n790; + assign n792 = Ni34 & (Ni30 | Ni32 | Ni31); + assign n793 = ~Pi21 | ~n2643; + assign n794 = Ni30 & n793 & (n788 | ~n1463); + assign n795 = Pi24 | ~Pi23; + assign n796 = Ni30 & n793 & (n795 | ~n1463); + assign n797 = ~n3795 | n3956 | n3973; + assign n798 = ~n1919 & (n797 | ~n4771); + assign n799 = ~n2254 & (n797 | ~n3539 | ~n4771); + assign n800 = n3956 | n3751; + assign n801 = ~Ni32 | ~Ni31; + assign n802 = n800 & n801; + assign n803 = n3811 & n2430; + assign n804 = ~n2420 & (n803 | ~Ni33); + assign n805 = ~n2420 & (n803 | Ni33); + assign n806 = (~n655 | Ni31) & ~n784; + assign n807 = n3283 & (~Pi20 | ~n3977); + assign n808 = ~Ni35 & ~Ni30; + assign n809 = n797 | ~n4771; + assign n810 = Pi22 & (n809 | ~n3539); + assign n811 = n2419 & (Ni45 | n2420); + assign n812 = n801 & ~n3829; + assign n813 = n811 & n812; + assign n814 = ~Ni37 | Ni38; + assign n815 = n881 & (Ni40 | n1048); + assign n816 = n814 & (~Ni37 | n815); + assign n817 = ~n3194 | n3852; + assign n818 = n678 & (n815 | n817); + assign n819 = n678 & n816 & (~n783 | n815); + assign n820 = (n815 | n698) & (n819 | n2434); + assign n821 = n816 & n820 & (Ni35 | n818); + assign n822 = ~Ni37 & (Ni36 | (n676 & ~n3194)); + assign n823 = n1082 | n1083; + assign n824 = ~Ni36 & n822; + assign n825 = Ni35 | n2438; + assign n826 = n823 & (n824 | n825); + assign n827 = n883 & (Ni40 | n1051_1); + assign n828 = n814 & (~Ni37 | n827); + assign n829 = n3849 | n3854; + assign n830 = n829 & n828 & (n827 | n817); + assign n831 = Ni38 | n3849; + assign n832 = n828 & (~n783 | n827) & n831; + assign n833 = (n827 | n1052) & (n828 | n886); + assign n834 = (n832 | n3856) & (n830 | n992); + assign n835 = n833 & n834; + assign n836 = n889 & (Ni40 | n1055); + assign n837 = n814 & (~Ni37 | n836); + assign n838 = n3874 | n3854; + assign n839 = n838 & n837 & (n836 | n817); + assign n840 = Ni38 | n3874; + assign n841 = n837 & (~n783 | n836) & n840; + assign n842 = (n839 | n995) & (n837 | n891); + assign n843 = (n841 | n3851) & (n836 | n1056); + assign n844 = n842 & n843; + assign n845 = n835 & n844; + assign n846 = (n845 | n3850) & (n821 | n896); + assign n847 = Ni32 | n1355; + assign n848 = n826 & n846 & (n815 | n847); + assign n849 = n18 | ~n1539; + assign n850 = n849 & n848 & (n18 | n821); + assign n851 = n881 & (Ni40 | n1064); + assign n852 = n814 & (~Ni37 | n851); + assign n853 = ~n3195 | n3852; + assign n854 = n678 & (n851 | n853); + assign n855 = n678 & n852 & (~n783 | n851); + assign n856 = (n851 | n698) & (n855 | n2434); + assign n857 = n852 & n856 & (Ni35 | n854); + assign n858 = ~Ni37 & (Ni36 | (n676 & ~n3195)); + assign n859 = ~Ni36 & n858; + assign n860 = n823 & (n859 | n825); + assign n861 = n883 & (Ni40 | n1067); + assign n862 = n814 & (~Ni37 | n861); + assign n863 = n3849 | n3855; + assign n864 = n863 & n862 & (n861 | n853); + assign n865 = n831 & n862 & (~n783 | n861); + assign n866 = (n861 | n1052) & (n862 | n886); + assign n867 = (n865 | n3856) & (n864 | n992); + assign n868 = n866 & n867; + assign n869 = n889 & (Ni40 | n1070); + assign n870 = n814 & (~Ni37 | n869); + assign n871 = n3874 | n3855; + assign n872 = n871 & n870 & (n869 | n853); + assign n873 = n840 & n870 & (~n783 | n869); + assign n874 = (n872 | n995) & (n870 | n891); + assign n875 = (n873 | n3851) & (n869 | n1056); + assign n876 = n874 & n875; + assign n877 = n868 & n876; + assign n878 = (n877 | n3850) & (n857 | n896); + assign n879 = n860 & n878 & (n851 | n847); + assign n880 = n849 & n879 & (n18 | n857); + assign n881 = n916 & ~Ni41; + assign n882 = n678 & n814 & (n881 | ~Ni38); + assign n883 = ~n762 & ~Ni41; + assign n884 = n814 & n831 & (n883 | ~Ni38); + assign n885 = n883 & n814; + assign n886 = Ni32 | ~Ni36; + assign n887 = Ni32 | Ni36; + assign n888 = (n885 | n886) & (n884 | n887); + assign n889 = ~n764 & ~Ni41; + assign n890 = n814 & n840 & (n889 | ~Ni38); + assign n891 = ~Ni32 | ~Ni36; + assign n892 = (n889 | n891) & (~Ni32 | n890); + assign n893 = ~n3850 & (~n888 | ~n892); + assign n894 = (n881 | n847) & (n1082 | n2438); + assign n895 = (~Ni36 | n881) & n882; + assign n896 = ~n18 | n2420; + assign n897 = ~n893 & n894 & (n895 | n896); + assign n898 = n849 & n897 & (n18 | n895); + assign n899 = Pi22 | ~Ni30; + assign n900 = n899 & (Pi22 | ~n801); + assign n901 = n900 & (Pi22 | n18); + assign n902 = Pi21 | ~Ni30; + assign n903 = n902 & (Ni31 | Pi21); + assign n904 = n2421 & n903; + assign n905 = n904 & (Pi21 | n18); + assign n906 = Pi21 & ~Pi20; + assign n907 = ~n844 & n906; + assign n908 = Pi20 & Pi21; + assign n909 = ~Pi22 & (n907 | (~n876 & n908)); + assign n910 = n901 & (Pi22 | n892); + assign n911 = n905 & n910 & (Pi21 | n888); + assign n912 = (n911 & (Pi19 | ~n3863)) | (~Pi19 & ~n3863); + assign n913 = (n898 | n1702) & (n850 | n1408); + assign n914 = Pi19 | n3859; + assign n915 = n912 & n913 & (n880 | n914); + assign n916 = n738 & ~Ni42; + assign n917 = n916 & (Ni40 | n1134); + assign n918 = n814 & (~Ni37 | n917); + assign n919 = n678 & (n917 | n817); + assign n920 = n678 & n918 & (~n783 | n917); + assign n921 = (n917 | n698) & (n920 | n2434); + assign n922 = n918 & n921 & (Ni35 | n919); + assign n923 = Ni43 | Ni42; + assign n924 = ~n762 & (n1137 | Ni40); + assign n925 = n814 & (~Ni37 | n924); + assign n926 = n829 & n925 & (n924 | n817); + assign n927 = n831 & n925 & (~n783 | n924); + assign n928 = (n924 | n1052) & (n925 | n886); + assign n929 = (n927 | n3856) & (n926 | n992); + assign n930 = n928 & n929; + assign n931 = ~n764 & (n1140 | Ni40); + assign n932 = n814 & (~Ni37 | n931); + assign n933 = n838 & n932 & (n931 | n817); + assign n934 = n840 & n932 & (~n783 | n931); + assign n935 = (n933 | n995) & (n932 | n891); + assign n936_1 = (n934 | n3851) & (n931 | n1056); + assign n937 = n935 & n936_1; + assign n938 = n930 & n937; + assign n939 = (n938 | n3850) & (n922 | n896); + assign n940 = n826 & n939 & (n917 | n847); + assign n941 = n849 & n940 & (n18 | n922); + assign n942 = n916 & (Ni40 | n1148); + assign n943 = n814 & (~Ni37 | n942); + assign n944 = n678 & (n942 | n853); + assign n945 = n678 & n943 & (~n783 | n942); + assign n946 = (n942 | n698) & (n945 | n2434); + assign n947 = n943 & n946 & (Ni35 | n944); + assign n948 = ~n762 & (n1151 | Ni40); + assign n949 = n814 & (~Ni37 | n948); + assign n950 = n863 & n949 & (n948 | n853); + assign n951 = n831 & n949 & (~n783 | n948); + assign n952 = (n948 | n1052) & (n949 | n886); + assign n953 = (n951 | n3856) & (n950 | n992); + assign n954 = n952 & n953; + assign n955 = ~n764 & (n1154 | Ni40); + assign n956 = n814 & (~Ni37 | n955); + assign n957 = n871 & n956 & (n955 | n853); + assign n958 = n840 & n956 & (~n783 | n955); + assign n959 = (n957 | n995) & (n956 | n891); + assign n960 = (n958 | n3851) & (n955 | n1056); + assign n961 = n959 & n960; + assign n962 = n954 & n961; + assign n963 = (n962 | n3850) & (n947 | n896); + assign n964 = n860 & n963 & (n942 | n847); + assign n965 = n849 & n964 & (n18 | n947); + assign n966 = n678 & n814 & (n916 | ~Ni38); + assign n967 = n814 & n831 & (~n762 | ~Ni38); + assign n968 = ~n762 & n814; + assign n969 = (n968 | n886) & (n967 | n887); + assign n970 = n814 & n840 & (~n764 | ~Ni38); + assign n971_1 = (~Ni32 | n970) & (~n764 | n891); + assign n972 = ~n3850 & (~n969 | ~n971_1); + assign n973 = (n916 | n847) & (n1082 | n2438); + assign n974 = (~Ni36 | n916) & n966; + assign n975 = ~n972 & n973 & (n896 | n974); + assign n976 = n849 & n975 & (n18 | n974); + assign n977 = n906 & ~n937; + assign n978 = ~Pi22 & (n977 | (n908 & ~n961)); + assign n979 = n901 & (Pi22 | n971_1); + assign n980 = n905 & n979 & (Pi21 | n969); + assign n981 = (n980 & (Pi19 | ~n3880)) | (~Pi19 & ~n3880); + assign n982 = (n976 | n1702) & (n941 | n1408); + assign n983 = n981 & n982 & (n965 | n914); + assign n984 = n819 & (Ni35 | n818); + assign n985 = Ni38 | n676; + assign n986_1 = ~Ni37 & ~Ni38; + assign n987 = n985 & n986_1; + assign n988 = n987 | n1083; + assign n989 = n987 & n822; + assign n990 = n988 & (n989 | n825); + assign n991 = Ni32 | ~n2530; + assign n992 = Ni32 | Ni35; + assign n993 = (n832 | n991) & (n830 | n992); + assign n994 = n1241 & n891; + assign n995 = ~Ni32 | Ni35; + assign n996 = (n841 | n994) & (n839 | n995); + assign n997 = n993 & n996; + assign n998 = (n997 | n3850) & (n984 | n896); + assign n999 = n990 & n998 & (n815 | n847); + assign n1000 = n849 & n999 & (n18 | n984); + assign n1001_1 = n855 & (Ni35 | n854); + assign n1002 = n987 & n858; + assign n1003 = n988 & (n1002 | n825); + assign n1004 = (n865 | n991) & (n864 | n992); + assign n1005 = (n873 | n994) & (n872 | n995); + assign n1006 = n1004 & n1005; + assign n1007 = (n1006 | n3850) & (n1001_1 | n896); + assign n1008 = n1003 & n1007 & (n851 | n847); + assign n1009 = n849 & n1008 & (n18 | n1001_1); + assign n1010 = n4071 & (n890 | n3663); + assign n1011 = (n881 | n847) & (n987 | n2438); + assign n1012 = n1010 & n1011 & (n882 | n896); + assign n1013 = n849 & n1012 & (n18 | n882); + assign n1014 = n906 & ~n996; + assign n1015 = ~Pi22 & (n1014 | (n908 & ~n1005)); + assign n1016 = n901 & (Pi22 | n890); + assign n1017 = n905 & n1016 & (Pi21 | n884); + assign n1018 = (n1017 & (Pi19 | ~n3873)) | (~Pi19 & ~n3873); + assign n1019 = (n1013 | n1702) & (n1000 | n1408); + assign n1020 = n1018 & n1019 & (n1009 | n914); + assign n1021_1 = n920 & (Ni35 | n919); + assign n1022 = (n927 | n991) & (n926 | n992); + assign n1023 = (n934 | n994) & (n933 | n995); + assign n1024 = n1022 & n1023; + assign n1025 = (n1024 | n3850) & (n1021_1 | n896); + assign n1026 = n990 & n1025 & (n917 | n847); + assign n1027 = n849 & n1026 & (n18 | n1021_1); + assign n1028 = n945 & (Ni35 | n944); + assign n1029 = (n951 | n991) & (n950 | n992); + assign n1030 = (n958 | n994) & (n957 | n995); + assign n1031 = n1029 & n1030; + assign n1032 = (n1031 | n3850) & (n1028 | n896); + assign n1033 = n1003 & n1032 & (n942 | n847); + assign n1034 = n849 & n1033 & (n18 | n1028); + assign n1035 = n4072 & (n970 | n3663); + assign n1036_1 = (n916 | n847) & (n987 | n2438); + assign n1037 = n1035 & n1036_1 & (n966 | n896); + assign n1038 = n849 & n1037 & (n18 | n966); + assign n1039 = n906 & ~n1023; + assign n1040 = ~Pi22 & (n1039 | (n908 & ~n1030)); + assign n1041 = n901 & (Pi22 | n970); + assign n1042 = n905 & n1041 & (Pi21 | n967); + assign n1043 = (n1042 & (Pi19 | ~n3887)) | (~Pi19 & ~n3887); + assign n1044 = (n1038 | n1702) & (n1027 | n1408); + assign n1045 = n1043 & n1044 & (n1034 | n914); + assign n1046 = n1048 | (~Ni37 & n817); + assign n1047 = n1046 & n814 & n678; + assign n1048 = ~n674 & ~n2426; + assign n1049 = n1047 & (n1048 | n698); + assign n1050 = ~Ni32 & (~n814 | ~n829 | ~n4056); + assign n1051_1 = ~n763 & ~Ni41; + assign n1052 = Ni32 | n698; + assign n1053 = ~n1050 & (n1051_1 | n1052); + assign n1054 = Ni32 & (~n814 | ~n838 | ~n4055); + assign n1055 = ~n765 & ~Ni41; + assign n1056 = Ni37 | n891; + assign n1057 = ~n1054 & (n1055 | n1056); + assign n1058 = ~n3850 & (~n1053 | ~n1057); + assign n1059 = (n1048 | n847) & (n824 | n2438); + assign n1060 = ~n1058 & (n896 | n1049) & n1059; + assign n1061_1 = n849 & n1060 & (n18 | n1049); + assign n1062 = n1064 | (~Ni37 & n853); + assign n1063 = n1062 & n814 & n678; + assign n1064 = ~n675 & ~n2426; + assign n1065 = n1063 & (n1064 | n698); + assign n1066 = ~Ni32 & (~n814 | ~n863 | ~n4058); + assign n1067 = ~n766 & ~Ni41; + assign n1068 = ~n1066 & (n1052 | n1067); + assign n1069 = Ni32 & (~n814 | ~n871 | ~n4057); + assign n1070 = ~n767 & ~Ni41; + assign n1071 = ~n1069 & (n1056 | n1070); + assign n1072 = ~n3850 & (~n1068 | ~n1071); + assign n1073 = (n1064 | n847) & (n859 | n2438); + assign n1074 = ~n1072 & (n896 | n1065) & n1073; + assign n1075 = n849 & n1074 & (n18 | n1065); + assign n1076_1 = n881 & (n1048 | ~Ni40); + assign n1077 = n814 & (~Ni37 | n1076_1); + assign n1078 = n678 & n1077 & (~n783 | n1076_1); + assign n1079 = n678 & (n1076_1 | n817); + assign n1080 = (n1076_1 | n698) & (n1078 | n2530); + assign n1081_1 = n1077 & n1080 & (~Ni35 | n1079); + assign n1082 = ~Ni36 & n987; + assign n1083 = ~Ni35 | n2438; + assign n1084 = (n1082 | n825) & (n824 | n1083); + assign n1085_1 = n883 & (n1051_1 | ~Ni40); + assign n1086 = n814 & (~Ni37 | n1085_1); + assign n1087 = n831 & n1086 & (~n783 | n1085_1); + assign n1088 = n829 & n1086 & (n1085_1 | n817); + assign n1089 = (n1085_1 | n1052) & (n1086 | n886); + assign n1090 = (n1087 | n3869) & (n1088 | n1238); + assign n1091 = n1089 & n1090; + assign n1092 = n889 & (n1055 | ~Ni40); + assign n1093 = n814 & (~Ni37 | n1092); + assign n1094 = n840 & n1093 & (~n783 | n1092); + assign n1095 = n838 & n1093 & (n1092 | n817); + assign n1096 = (n1095 | n1241) & (n1093 | n891); + assign n1097 = (n1094 | n3868) & (n1092 | n1056); + assign n1098 = n1096 & n1097; + assign n1099 = n1091 & n1098; + assign n1100 = (n1099 | n3850) & (n1081_1 | n896); + assign n1101 = n1084 & n1100 & (n1076_1 | n847); + assign n1102 = n849 & n1101 & (n18 | n1081_1); + assign n1103 = n881 & (n1064 | ~Ni40); + assign n1104 = n814 & (~Ni37 | n1103); + assign n1105 = n678 & n1104 & (~n783 | n1103); + assign n1106 = n678 & (n1103 | n853); + assign n1107 = (n1103 | n698) & (n1105 | n2530); + assign n1108 = n1104 & n1107 & (~Ni35 | n1106); + assign n1109 = (n1082 | n825) & (n859 | n1083); + assign n1110 = n883 & (n1067 | ~Ni40); + assign n1111 = n814 & (~Ni37 | n1110); + assign n1112 = n831 & n1111 & (~n783 | n1110); + assign n1113 = n863 & n1111 & (n1110 | n853); + assign n1114 = (n1110 | n1052) & (n1111 | n886); + assign n1115 = (n1112 | n3869) & (n1113 | n1238); + assign n1116 = n1114 & n1115; + assign n1117 = n889 & (n1070 | ~Ni40); + assign n1118 = n814 & (~Ni37 | n1117); + assign n1119 = n840 & n1118 & (~n783 | n1117); + assign n1120 = n871 & n1118 & (n1117 | n853); + assign n1121 = (n1120 | n1241) & (n1118 | n891); + assign n1122 = (n1119 | n3868) & (n1117 | n1056); + assign n1123 = n1121 & n1122; + assign n1124 = n1116 & n1123; + assign n1125 = (n1124 | n3850) & (n1108 | n896); + assign n1126 = n1109 & n1125 & (n1103 | n847); + assign n1127 = n849 & n1126 & (n18 | n1108); + assign n1128 = n906 & ~n1098; + assign n1129 = ~Pi22 & (n1128 | (n908 & ~n1123)); + assign n1130 = n906 & ~n1057; + assign n1131 = ~Pi22 & (n1130 | (n908 & ~n1071)); + assign n1132 = n1134 | (~Ni37 & n817); + assign n1133 = n1132 & n814 & n678; + assign n1134 = n4769 & n916; + assign n1135 = n1133 & (n1134 | n698); + assign n1136 = ~Ni32 & (~n814 | ~n829 | ~n4062); + assign n1137 = ~n762 & ~n763; + assign n1138 = ~n1136 & (n1052 | n1137); + assign n1139 = Ni32 & (~n814 | ~n838 | ~n4061); + assign n1140 = ~n764 & ~n765; + assign n1141 = ~n1139 & (n1056 | n1140); + assign n1142 = ~n3850 & (~n1138 | ~n1141); + assign n1143 = (n1134 | n847) & (n824 | n2438); + assign n1144 = ~n1142 & (n896 | n1135) & n1143; + assign n1145 = n849 & n1144 & (n18 | n1135); + assign n1146 = n1148 | (~Ni37 & n853); + assign n1147 = n1146 & n814 & n678; + assign n1148 = n4770 & n916; + assign n1149 = n1147 & (n1148 | n698); + assign n1150 = ~Ni32 & (~n814 | ~n863 | ~n4064); + assign n1151 = ~n762 & ~n766; + assign n1152 = ~n1150 & (n1052 | n1151); + assign n1153 = Ni32 & (~n814 | ~n871 | ~n4063); + assign n1154 = ~n764 & ~n767; + assign n1155 = ~n1153 & (n1056 | n1154); + assign n1156 = ~n3850 & (~n1152 | ~n1155); + assign n1157 = (n1148 | n847) & (n859 | n2438); + assign n1158 = ~n1156 & (n896 | n1149) & n1157; + assign n1159 = n849 & n1158 & (n18 | n1149); + assign n1160 = n916 & (n1134 | ~Ni40); + assign n1161 = n814 & (~Ni37 | n1160); + assign n1162 = n678 & n1161 & (~n783 | n1160); + assign n1163 = n678 & (n1160 | n817); + assign n1164 = (n1160 | n698) & (n1162 | n2530); + assign n1165 = n1161 & n1164 & (~Ni35 | n1163); + assign n1166 = ~n762 & (n1137 | ~Ni40); + assign n1167 = n814 & (~Ni37 | n1166); + assign n1168 = n831 & n1167 & (~n783 | n1166); + assign n1169 = n829 & n1167 & (n1166 | n817); + assign n1170 = (n1166 | n1052) & (n1167 | n886); + assign n1171 = (n1168 | n3869) & (n1169 | n1238); + assign n1172 = n1170 & n1171; + assign n1173 = ~n764 & (n1140 | ~Ni40); + assign n1174 = n814 & (~Ni37 | n1173); + assign n1175 = n840 & n1174 & (~n783 | n1173); + assign n1176 = n838 & n1174 & (n1173 | n817); + assign n1177 = (n1176 | n1241) & (n1174 | n891); + assign n1178 = (n1175 | n3868) & (n1173 | n1056); + assign n1179 = n1177 & n1178; + assign n1180 = n1172 & n1179; + assign n1181 = (n1180 | n3850) & (n1165 | n896); + assign n1182 = n1084 & n1181 & (n1160 | n847); + assign n1183 = n849 & n1182 & (n18 | n1165); + assign n1184 = n916 & (n1148 | ~Ni40); + assign n1185 = n814 & (~Ni37 | n1184); + assign n1186 = n678 & n1185 & (~n783 | n1184); + assign n1187 = n678 & (n1184 | n853); + assign n1188 = (n1184 | n698) & (n1186 | n2530); + assign n1189 = n1185 & n1188 & (~Ni35 | n1187); + assign n1190 = ~n762 & (n1151 | ~Ni40); + assign n1191 = n814 & (~Ni37 | n1190); + assign n1192 = n831 & n1191 & (~n783 | n1190); + assign n1193 = n863 & n1191 & (n1190 | n853); + assign n1194 = (n1190 | n1052) & (n1191 | n886); + assign n1195 = (n1192 | n3869) & (n1193 | n1238); + assign n1196 = n1194 & n1195; + assign n1197 = ~n764 & (n1154 | ~Ni40); + assign n1198 = n814 & (~Ni37 | n1197); + assign n1199 = n840 & n1198 & (~n783 | n1197); + assign n1200 = n871 & n1198 & (n1197 | n853); + assign n1201 = (n1200 | n1241) & (n1198 | n891); + assign n1202 = (n1199 | n3868) & (n1197 | n1056); + assign n1203 = n1201 & n1202; + assign n1204 = n1196 & n1203; + assign n1205 = (n1204 | n3850) & (n1189 | n896); + assign n1206 = n1109 & n1205 & (n1184 | n847); + assign n1207 = n849 & n1206 & (n18 | n1189); + assign n1208 = n906 & ~n1179; + assign n1209 = ~Pi22 & (n1208 | (n908 & ~n1203)); + assign n1210 = n906 & ~n1141; + assign n1211 = ~Pi22 & (n1210 | (n908 & ~n1155)); + assign n1212 = (n914 | n1159) & (Pi19 | ~n3883); + assign n1213 = (n1183 | n3893) & (n1207 | n2109); + assign n1214 = n1145 | n1408; + assign n1215 = ~n3789 & n1214 & n1212 & n1213; + assign n1216 = n698 | ~Ni38; + assign n1217 = n1047 & (n1048 | n1216); + assign n1218 = n831 | n1052; + assign n1219 = Ni32 | n1216; + assign n1220 = ~n1050 & n1218 & (n1051_1 | n1219); + assign n1221 = n891 | n840; + assign n1222 = ~n783 | n891; + assign n1223 = ~n1054 & n1221 & (n1055 | n1222); + assign n1224 = ~n3850 & (~n1220 | ~n1223); + assign n1225 = (n1048 | n847) & (n989 | n2438); + assign n1226 = ~n1224 & (n896 | n1217) & n1225; + assign n1227 = n849 & n1226 & (n18 | n1217); + assign n1228 = n1063 & (n1064 | n1216); + assign n1229 = ~n1066 & n1218 & (n1067 | n1219); + assign n1230 = ~n1069 & n1221 & (n1070 | n1222); + assign n1231 = ~n3850 & (~n1229 | ~n1230); + assign n1232 = (n1064 | n847) & (n1002 | n2438); + assign n1233 = ~n1231 & (n896 | n1228) & n1232; + assign n1234 = n849 & n1233 & (n18 | n1228); + assign n1235 = n1078 & (~Ni35 | n1079); + assign n1236 = (n987 | n825) & (n989 | n1083); + assign n1237 = Ni32 | ~n2434; + assign n1238 = Ni32 | ~Ni35; + assign n1239 = (n1087 | n1237) & (n1088 | n1238); + assign n1240 = n995 & n891; + assign n1241 = ~Ni32 | ~Ni35; + assign n1242 = (n1094 | n1240) & (n1095 | n1241); + assign n1243 = n1239 & n1242; + assign n1244 = (n1243 | n3850) & (n1235 | n896); + assign n1245 = n1236 & n1244 & (n1076_1 | n847); + assign n1246 = n849 & n1245 & (n18 | n1235); + assign n1247 = n1105 & (~Ni35 | n1106); + assign n1248 = (n987 | n825) & (n1002 | n1083); + assign n1249 = (n1112 | n1237) & (n1113 | n1238); + assign n1250 = (n1119 | n1240) & (n1120 | n1241); + assign n1251 = n1249 & n1250; + assign n1252 = (n1251 | n3850) & (n1247 | n896); + assign n1253 = n1248 & n1252 & (n1103 | n847); + assign n1254 = n849 & n1253 & (n18 | n1247); + assign n1255 = n906 & ~n1242; + assign n1256 = ~Pi22 & (n1255 | (n908 & ~n1250)); + assign n1257 = n906 & ~n1223; + assign n1258 = ~Pi22 & (n1257 | (n908 & ~n1230)); + assign n1259 = n1133 & (n1134 | n1216); + assign n1260 = ~n1136 & n1218 & (n1137 | n1219); + assign n1261 = ~n1139 & n1221 & (n1140 | n1222); + assign n1262 = ~n3850 & (~n1260 | ~n1261); + assign n1263 = (n1134 | n847) & (n989 | n2438); + assign n1264 = ~n1262 & (n896 | n1259) & n1263; + assign n1265 = n849 & n1264 & (n18 | n1259); + assign n1266 = n1147 & (n1148 | n1216); + assign n1267 = ~n1150 & n1218 & (n1151 | n1219); + assign n1268 = ~n1153 & n1221 & (n1154 | n1222); + assign n1269 = ~n3850 & (~n1267 | ~n1268); + assign n1270 = (n1148 | n847) & (n1002 | n2438); + assign n1271 = ~n1269 & (n896 | n1266) & n1270; + assign n1272 = n849 & n1271 & (n18 | n1266); + assign n1273 = n1162 & (~Ni35 | n1163); + assign n1274 = (n1168 | n1237) & (n1169 | n1238); + assign n1275 = (n1175 | n1240) & (n1176 | n1241); + assign n1276 = n1274 & n1275; + assign n1277 = (n1276 | n3850) & (n1273 | n896); + assign n1278 = n1236 & n1277 & (n1160 | n847); + assign n1279 = n849 & n1278 & (n18 | n1273); + assign n1280 = n1186 & (~Ni35 | n1187); + assign n1281 = (n1192 | n1237) & (n1193 | n1238); + assign n1282 = (n1199 | n1240) & (n1200 | n1241); + assign n1283 = n1281 & n1282; + assign n1284 = (n1283 | n3850) & (n1280 | n896); + assign n1285 = n1248 & n1284 & (n1184 | n847); + assign n1286 = n849 & n1285 & (n18 | n1280); + assign n1287 = n906 & ~n1275; + assign n1288 = ~Pi22 & (n1287 | (n908 & ~n1282)); + assign n1289 = n906 & ~n1261; + assign n1290 = ~Pi22 & (n1289 | (n908 & ~n1268)); + assign n1291 = (n914 | n1272) & (Pi19 | ~n3890); + assign n1292 = (n1279 | n3893) & (n1286 | n2109); + assign n1293 = n1265 | n1408; + assign n1294 = ~n3792 & n1293 & n1291 & n1292; + assign n1295 = ~n901 | n1129 | n3783 | n3784; + assign n1296 = ~n3870 & (n1295 | ~n4084 | ~n4085); + assign n1297 = ~n901 | n1256 | n3785 | n3786; + assign n1298 = ~n3877 & (n1297 | ~n4087 | ~n4088); + assign n1299 = ~n901 | n1258 | n3875 | n3876; + assign n1300 = ~n2272 & (n1299 | ~n4075); + assign n1301 = n18 & (n3737 | (~n3792 & n4078)); + assign n1302 = n4082 & (n3743 | (~n3890 & n4077)); + assign n1303 = n4081 & (n3740 | (~n3887 & n4074)); + assign n1304 = n4079 & (n1012 | n1495); + assign n1305 = n1304 & n1303 & n1301 & n1302; + assign n1306 = ~n901 | n1131 | n3865 | n3866; + assign n1307 = ~n2272 & (n1306 | ~n4059); + assign n1308 = n18 & (n3737 | (~n3789 & n4066)); + assign n1309 = n4070 & (n3743 | (~n3883 & n4065)); + assign n1310 = n4069 & (n3740 | (~n3880 & n4054)); + assign n1311 = n4067 & (n897 | n1495); + assign n1312 = n1311 & n1310 & n1308 & n1309; + assign n1313 = n4103 & (n1183 | n2372); + assign n1314 = ~Pi25 | n3859; + assign n1315 = n1313 & ~n3789 & (n1207 | n1314); + assign n1316 = n4102 & (n1145 | n2372); + assign n1317 = n1316 & (n1159 | n1314) & ~n3883; + assign n1318 = n4101 & (n941 | n2372); + assign n1319 = n1318 & (n965 | n1314) & ~n3880; + assign n1320 = (n1319 | n3864) & (n1317 | n3867); + assign n1321 = n4096 & n4104 & (n975 | n3848); + assign n1322 = ~Pi19 | Pi17; + assign n1323 = n1320 & n1321 & (n1315 | n1322); + assign n1324 = n4094 & (n1102 | n2372); + assign n1325 = ~n1295 & n1324 & (n1127 | n1314); + assign n1326 = n4093 & (n1061_1 | n2372); + assign n1327 = ~n1306 & n1326 & (n1075 | n1314); + assign n1328 = n4092 & (n850 | n2372); + assign n1329 = n1328 & (n880 | n1314) & ~n3863; + assign n1330 = (n1329 | n3864) & (n1327 | n3867); + assign n1331 = n4096 & n4095 & (n897 | n3848); + assign n1332 = n1330 & n1331 & (n1325 | n1322); + assign n1333 = n4107 & (n1279 | n2372); + assign n1334 = n1333 & (n1286 | n1314) & ~n3792; + assign n1335 = n4106 & (n1265 | n2372); + assign n1336 = n1335 & (n1272 | n1314) & ~n3890; + assign n1337 = n4105 & (n1027 | n2372); + assign n1338 = n1337 & (n1034 | n1314) & ~n3887; + assign n1339 = (n1338 | n3864) & (n1336 | n3867); + assign n1340 = n4096 & n4108 & (n1037 | n3848); + assign n1341 = n1339 & n1340 & (n1334 | n1322); + assign n1342 = n4099 & (n1246 | n2372); + assign n1343 = ~n1297 & n1342 & (n1254 | n1314); + assign n1344 = n4098 & (n1227 | n2372); + assign n1345 = ~n1299 & n1344 & (n1234 | n1314); + assign n1346 = n4097 & (n1000 | n2372); + assign n1347 = n1346 & (n1009 | n1314) & ~n3873; + assign n1348 = (n1347 | n3864) & (n1345 | n3867); + assign n1349 = n4096 & n4100 & (n1012 | n3848); + assign n1350 = n1348 & n1349 & (n1343 | n1322); + assign n1351 = n738 & Ni42; + assign n1352 = n985 & (~n814 | n1351); + assign n1353 = ~Ni31 | ~Ni30; + assign n1354 = (~Ni30 | Ni33) & n1353; + assign n1355 = ~n18 | ~Ni30; + assign n1356 = ~n707 & ~Ni30; + assign n1357 = n1355 & (n18 | n1356); + assign n1358 = ~n711 & ~Ni30; + assign n1359 = n1355 & (n18 | n1358); + assign n1360 = ~n714 & ~Ni30; + assign n1361 = n1355 & (n18 | n1360); + assign n1362 = n899 & n902; + assign n1363 = (n1534 | n1702) & (n4135 | n1408); + assign n1364 = n1520 & n1359; + assign n1365 = n1362 & n1363 & (n1364 | n914); + assign n1366 = ~n732 & ~Ni30; + assign n1367 = n1355 & (n18 | n1366); + assign n1368 = ~n736 & ~Ni30; + assign n1369 = n1355 & (n18 | n1368); + assign n1370 = ~n739 & ~Ni30; + assign n1371 = n1355 & (n18 | n1370); + assign n1372 = (n1535 | n1702) & (n4136 | n1408); + assign n1373 = n1532 & n1369; + assign n1374 = n1362 & n1372 & (n1373 | n914); + assign n1375 = ~n749 & ~Ni30; + assign n1376 = n1355 & (n18 | n1375); + assign n1377 = ~n751 & ~Ni30; + assign n1378 = n1355 & (n18 | n1377); + assign n1379 = ~Ni30 & n1465; + assign n1380 = n1355 & (n18 | n1379); + assign n1381 = (n1494 | n1702) & (n4149 | n1408); + assign n1382 = n1480 & n1378; + assign n1383 = n1362 & n1381 & (n1382 | n914); + assign n1384 = ~n759 & ~Ni30; + assign n1385 = n1355 & (n18 | n1384); + assign n1386 = ~n761 & ~Ni30; + assign n1387 = n1355 & (n18 | n1386); + assign n1388 = ~Ni30 & n1468; + assign n1389 = n1355 & (n18 | n1388); + assign n1390 = (n1496 | n1702) & (n4150 | n1408); + assign n1391 = n1492 & n1387; + assign n1392 = n1362 & n1390 & (n1391 | n914); + assign n1393 = ~Ni37 | n985; + assign n1394 = n676 | n3853; + assign n1395 = n3959 & n3183; + assign n1396 = ~n691 & ~Ni30; + assign n1397 = n1355 & (n18 | n1396); + assign n1398 = n3961 & n3183; + assign n1399 = ~n694 & ~Ni30; + assign n1400 = n1355 & (n18 | n1399); + assign n1401 = ~n699 & ~Ni30; + assign n1402 = n1355 & (n18 | n1401); + assign n1403 = ~n703 & ~Ni30; + assign n1404 = n1355 & (n18 | n1403); + assign n1405 = (n4140 | n3893) & (n4141 | n2109); + assign n1406 = n1362 & (n4138 | n914); + assign n1407 = n1514 & n1397; + assign n1408 = Pi19 | n3857; + assign n1409 = n1405 & n1406 & (n1407 | n1408); + assign n1410 = ~n717 & ~Ni30; + assign n1411 = n1355 & (n18 | n1410); + assign n1412 = ~n720 & ~Ni30; + assign n1413 = n1355 & (n18 | n1412); + assign n1414 = ~n724 & ~Ni30; + assign n1415 = n1355 & (n18 | n1414); + assign n1416 = ~n728 & ~Ni30; + assign n1417 = n1355 & (n18 | n1416); + assign n1418 = (n4145 | n3893) & (n4146 | n2109); + assign n1419 = n1362 & (n4143 | n914); + assign n1420 = n1526 & n1411; + assign n1421 = n1418 & n1419 & (n1420 | n1408); + assign n1422 = ~n742 & ~Ni30; + assign n1423 = n1355 & (n18 | n1422); + assign n1424 = ~n743 & ~Ni30; + assign n1425 = n1355 & (n18 | n1424); + assign n1426 = ~n745 & ~Ni30; + assign n1427 = n1355 & (n18 | n1426); + assign n1428 = ~n747 & ~Ni30; + assign n1429 = n1355 & (n18 | n1428); + assign n1430 = (n4154 | n3893) & (n4155 | n2109); + assign n1431 = n1362 & (n4152 | n914); + assign n1432 = n1474 & n1423; + assign n1433 = n1430 & n1431 & (n1432 | n1408); + assign n1434 = ~n752 & ~Ni30; + assign n1435 = n1355 & (n18 | n1434); + assign n1436 = ~n753 & ~Ni30; + assign n1437 = n1355 & (n18 | n1436); + assign n1438 = ~n755 & ~Ni30; + assign n1439 = n1355 & (n18 | n1438); + assign n1440 = ~n757 & ~Ni30; + assign n1441 = n1355 & (n18 | n1440); + assign n1442 = (n4159 | n3893) & (n4160 | n2109); + assign n1443 = n1362 & (n4157 | n914); + assign n1444 = n1486 & n1435; + assign n1445 = n1442 & n1443 & (n1444 | n1408); + assign n1446 = Ni12 | n2750; + assign n1447 = n1461 & n1362; + assign n1448 = Ni12 | ~n2750; + assign n1449 = (n1447 | n1448) & (n1446 | ~n3991); + assign n1450 = ~n3696 & (~n1552 | (~n1986 & ~n2254)); + assign n1451 = ~n1450 & (n2632 | (~n3918 & n4300)); + assign n1452 = ~Ni12 | ~Ni13; + assign n1453 = n1449 & n1451 & (n1447 | n1452); + assign n1454 = n1354 & (~Ni30 | ~n3761); + assign n1455 = n1454 | (Pi22 & Pi21); + assign n1456 = n1455 | n3677; + assign n1457 = (n1541 | n1610) & (n1447 | ~n3898); + assign n1458 = n1456 & n1457 & (Ni11 | n1453); + assign n1459 = n4772 | n2254; + assign n1460 = (Pi24 | n1362) & (~n793 | n1463); + assign n1461 = n1918 | n2254; + assign n1462 = n1459 & n1460 & (Pi24 | n1461); + assign n1463 = n1353 & n3795; + assign n1464 = n4766 | n1465; + assign n1465 = ~n712 | n1539; + assign n1466 = n1463 & n1464 & (n18 | n1465); + assign n1467 = n4766 | n1468; + assign n1468 = ~n737 | n1539; + assign n1469 = n1463 & n1467 & (n18 | n1468); + assign n1470 = ~n745 | n4766; + assign n1471 = n1463 & n1470 & (n18 | ~n745); + assign n1472 = ~n747 | n4766; + assign n1473 = n1463 & n1472 & (n18 | ~n747); + assign n1474 = ~n742 | n4766; + assign n1475 = n1463 & n1474 & (n18 | ~n742); + assign n1476 = ~n743 | n4766; + assign n1477 = n1463 & n1476 & (n18 | ~n743); + assign n1478 = ~n749 | n4766; + assign n1479 = n1463 & n1478 & (n18 | ~n749); + assign n1480 = ~n751 | n4766; + assign n1481 = n1463 & n1480 & (n18 | ~n751); + assign n1482 = ~n755 | n4766; + assign n1483 = n1463 & n1482 & (n18 | ~n755); + assign n1484 = ~n757 | n4766; + assign n1485 = n1463 & n1484 & (n18 | ~n757); + assign n1486 = ~n752 | n4766; + assign n1487 = n1463 & n1486 & (n18 | ~n752); + assign n1488 = ~n753 | n4766; + assign n1489 = n1463 & n1488 & (n18 | ~n753); + assign n1490 = ~n759 | n4766; + assign n1491 = n1463 & n1490 & (n18 | ~n759); + assign n1492 = ~n761 | n4766; + assign n1493 = n1463 & n1492 & (n18 | ~n761); + assign n1494 = n1464 & n1380; + assign n1495 = Pi16 | n3848; + assign n1496 = n1467 & n1389; + assign n1497 = ~Pi16 | n3848; + assign n1498 = (n1494 | n1495) & (n1496 | n1497); + assign n1499 = ~n3894 & (~n4277 | ~n4278); + assign n1500 = ~n2272 & (~n4281 | ~n4282); + assign n1501 = n1460 & (n3737 | (n4288 & n4287)); + assign n1502 = n4290 & (n3743 | (n4286 & n4285)); + assign n1503 = ~n1499 & (n3740 | (n4279 & n4280)); + assign n1504 = n4289 & (Pi24 | n1498); + assign n1505 = n1504 & n1503 & n1501 & n1502; + assign n1506 = ~n714 | n4766; + assign n1507 = n1463 & n1506 & (n18 | ~n714); + assign n1508 = ~n739 | n4766; + assign n1509 = n1463 & n1508 & (n18 | ~n739); + assign n1510 = ~n699 | n4766; + assign n1511 = n1463 & n1510 & (n18 | ~n699); + assign n1512 = ~n703 | n4766; + assign n1513 = n1463 & n1512 & (n18 | ~n703); + assign n1514 = ~n691 | n4766; + assign n1515 = n1463 & n1514 & (n18 | ~n691); + assign n1516 = ~n694 | n4766; + assign n1517 = n1463 & n1516 & (n18 | ~n694); + assign n1518 = ~n707 | n4766; + assign n1519 = n1463 & n1518 & (n18 | ~n707); + assign n1520 = ~n711 | n4766; + assign n1521 = n1463 & n1520 & (n18 | ~n711); + assign n1522 = ~n724 | n4766; + assign n1523 = n1463 & n1522 & (n18 | ~n724); + assign n1524 = ~n728 | n4766; + assign n1525 = n1463 & n1524 & (n18 | ~n728); + assign n1526 = ~n717 | n4766; + assign n1527 = n1463 & n1526 & (n18 | ~n717); + assign n1528 = ~n720 | n4766; + assign n1529 = n1463 & n1528 & (n18 | ~n720); + assign n1530 = ~n732 | n4766; + assign n1531 = n1463 & n1530 & (n18 | ~n732); + assign n1532 = ~n736 | n4766; + assign n1533 = n1463 & n1532 & (n18 | ~n736); + assign n1534 = n1506 & n1361; + assign n1535 = n1508 & n1371; + assign n1536 = (n1534 | n1495) & (n1535 | n1497); + assign n1537 = ~n3894 & (~n4259 | ~n4260); + assign n1538 = ~n2272 & (~n4263 | ~n4264); + assign n1539 = Ni32 | n2420; + assign n1540 = ~n1352 | n1539; + assign n1541 = n3794 & (Pi26 | n1918); + assign n1542 = ~Ni11 | ~Ni12; + assign n1543 = Ni12 | Ni11; + assign n1544 = n1542 & ~Ni13 & (Ni14 | n1543); + assign n1545 = Ni11 & ~Ni12; + assign n1546 = ~n1462 & n1545 & (~n1541 | ~Ni14); + assign n1547 = ~n3928 & ~n4674 & (Ni14 | ~n3993); + assign n1548 = ~n3944 & (~n4273 | ~n4275 | ~n4276); + assign n1549 = ~n794 & n1459 & (~n788 | n1461); + assign n1550 = Pi21 | n3801; + assign n1551 = Pi22 | n3801; + assign n1552 = n1550 & n1551; + assign n1553 = ~Ni13 & (Ni14 | Ni12); + assign n1554 = ~n794 & (n1523 | n3935); + assign n1555 = (n4145 | n3936) & (n4146 | n2707); + assign n1556 = n3859 | n788; + assign n1557 = n1554 & n1555 & (n1525 | n1556); + assign n1558 = ~n794 & (n1527 | n3935); + assign n1559 = (n1420 | n3936) & (n4143 | n2707); + assign n1560 = n1558 & n1559 & (n1529 | n1556); + assign n1561 = ~n794 & (n1531 | n3935); + assign n1562 = (n4136 | n3936) & (n1373 | n2707); + assign n1563 = n1561 & n1562 & (n1533 | n1556); + assign n1564 = (n1563 | n3864) & (n1560 | n3867); + assign n1565 = n4254 & n4252 & (n1535 | n3934); + assign n1566 = n1564 & n1565 & (n1557 | n1322); + assign n1567 = ~n794 & (n1511 | n3935); + assign n1568 = (n4140 | n3936) & (n4141 | n2707); + assign n1569 = n1567 & n1568 & (n1513 | n1556); + assign n1570 = ~n794 & (n1515 | n3935); + assign n1571 = (n1407 | n3936) & (n4138 | n2707); + assign n1572 = n1570 & n1571 & (n1517 | n1556); + assign n1573 = ~n794 & (n1519 | n3935); + assign n1574 = (n4135 | n3936) & (n1364 | n2707); + assign n1575 = n1573 & n1574 & (n1521 | n1556); + assign n1576 = (n1575 | n3864) & (n1572 | n3867); + assign n1577 = n4251 & n4252 & (n1534 | n3934); + assign n1578 = n1576 & n1577 & (n1569 | n1322); + assign n1579 = ~n794 & (n1483 | n3935); + assign n1580 = (n4159 | n3936) & (n4160 | n2707); + assign n1581 = n1579 & n1580 & (n1485 | n1556); + assign n1582 = ~n794 & (n1487 | n3935); + assign n1583 = (n1444 | n3936) & (n4157 | n2707); + assign n1584 = n1582 & n1583 & (n1489 | n1556); + assign n1585 = ~n794 & (n1491 | n3935); + assign n1586 = (n4150 | n3936) & (n1391 | n2707); + assign n1587 = n1585 & n1586 & (n1493 | n1556); + assign n1588 = (n1587 | n3864) & (n1584 | n3867); + assign n1589 = n4255 & n4252 & (n1496 | n3934); + assign n1590 = n1588 & n1589 & (n1581 | n1322); + assign n1591 = ~n794 & (n1471 | n3935); + assign n1592 = (n4154 | n3936) & (n4155 | n2707); + assign n1593 = n1591 & n1592 & (n1473 | n1556); + assign n1594 = ~n794 & (n1475 | n3935); + assign n1595 = (n1432 | n3936) & (n4152 | n2707); + assign n1596 = n1594 & n1595 & (n1477 | n1556); + assign n1597 = ~n794 & (n1479 | n3935); + assign n1598 = (n4149 | n3936) & (n1382 | n2707); + assign n1599 = n1597 & n1598 & (n1481 | n1556); + assign n1600 = (n1599 | n3864) & (n1596 | n3867); + assign n1601 = n4253 & n4252 & (n1494 | n3934); + assign n1602 = n1600 & n1601 & (n1593 | n1322); + assign n1603 = ~Ni14 & ~n3796 & (n788 | ~n3797); + assign n1604 = ~n1986 & n788 & Ni14 & ~n2254; + assign n1605 = Ni12 & (n1603 | n1604 | ~n4250); + assign n1606 = ~n1605 & (n1446 | (n4256 & n4257)); + assign n1607 = n1606 & (n1549 | n1553); + assign n1608 = ~n1454 & ~n3677 & (n788 | ~n1463); + assign n1609 = (Ni11 | n1607) & (n1549 | ~n3898); + assign n1610 = n2254 | n3677; + assign n1611 = ~n1608 & n1609 & (n1540 | n1610); + assign n1612 = ~n796 & n1459 & (~n795 | n1461); + assign n1613 = ~n796 & (n1523 | n3947); + assign n1614 = (n4145 | n3948) & (n4146 | n2757); + assign n1615 = n3859 | n795; + assign n1616 = n1613 & n1614 & (n1525 | n1615); + assign n1617 = ~n796 & (n1527 | n3947); + assign n1618 = (n1420 | n3948) & (n4143 | n2757); + assign n1619 = n1617 & n1618 & (n1529 | n1615); + assign n1620 = ~n796 & (n1531 | n3947); + assign n1621 = (n4136 | n3948) & (n1373 | n2757); + assign n1622 = n1620 & n1621 & (n1533 | n1615); + assign n1623 = (n1622 | n3864) & (n1619 | n3867); + assign n1624 = n4296 & n4294 & (n1535 | n3946); + assign n1625 = n1623 & n1624 & (n1616 | n1322); + assign n1626 = ~n796 & (n1511 | n3947); + assign n1627 = (n4140 | n3948) & (n4141 | n2757); + assign n1628 = n1626 & n1627 & (n1513 | n1615); + assign n1629 = ~n796 & (n1515 | n3947); + assign n1630 = (n1407 | n3948) & (n4138 | n2757); + assign n1631 = n1629 & n1630 & (n1517 | n1615); + assign n1632 = ~n796 & (n1519 | n3947); + assign n1633 = (n4135 | n3948) & (n1364 | n2757); + assign n1634 = n1632 & n1633 & (n1521 | n1615); + assign n1635 = (n1634 | n3864) & (n1631 | n3867); + assign n1636 = n4293 & n4294 & (n1534 | n3946); + assign n1637 = n1635 & n1636 & (n1628 | n1322); + assign n1638 = ~n796 & (n1483 | n3947); + assign n1639 = (n4159 | n3948) & (n4160 | n2757); + assign n1640 = n1638 & n1639 & (n1485 | n1615); + assign n1641 = ~n796 & (n1487 | n3947); + assign n1642 = (n1444 | n3948) & (n4157 | n2757); + assign n1643 = n1641 & n1642 & (n1489 | n1615); + assign n1644 = ~n796 & (n1491 | n3947); + assign n1645 = (n4150 | n3948) & (n1391 | n2757); + assign n1646 = n1644 & n1645 & (n1493 | n1615); + assign n1647 = (n1646 | n3864) & (n1643 | n3867); + assign n1648 = n4297 & n4294 & (n1496 | n3946); + assign n1649 = n1647 & n1648 & (n1640 | n1322); + assign n1650 = ~n796 & (n1471 | n3947); + assign n1651 = (n4154 | n3948) & (n4155 | n2757); + assign n1652 = n1650 & n1651 & (n1473 | n1615); + assign n1653 = ~n796 & (n1475 | n3947); + assign n1654 = (n1432 | n3948) & (n4152 | n2757); + assign n1655 = n1653 & n1654 & (n1477 | n1615); + assign n1656 = ~n796 & (n1479 | n3947); + assign n1657 = (n4149 | n3948) & (n1382 | n2757); + assign n1658 = n1656 & n1657 & (n1481 | n1615); + assign n1659 = (n1658 | n3864) & (n1655 | n3867); + assign n1660 = n4295 & n4294 & (n1494 | n3946); + assign n1661 = n1659 & n1660 & (n1652 | n1322); + assign n1662 = ~Ni14 & ~n3796 & (n795 | ~n3797); + assign n1663 = ~n1986 & n795 & Ni14 & ~n2254; + assign n1664 = Ni12 & (n1662 | n1663 | ~n4292); + assign n1665 = ~n1664 & (n1446 | (n4298 & n4299)); + assign n1666 = n1665 & (n1553 | n1612); + assign n1667 = ~n1454 & ~n3677 & (n795 | ~n1463); + assign n1668 = (Ni11 | n1666) & (n1612 | ~n3898); + assign n1669 = ~n1667 & (n1540 | n1610) & n1668; + assign n1670 = ~Ni9 & (~Ni8 | ~Ni7); + assign n1671 = n1670 & (Ni10 | ~Ni7); + assign n1672 = (n4129 | n1702) & (n1783 | n1408); + assign n1673 = n1778 & n1359; + assign n1674 = n1362 & n1672 & (n1673 | n914); + assign n1675 = (n4131 | n1702) & (n1748 | n1408); + assign n1676 = n1743 & n1369; + assign n1677 = n1362 & n1675 & (n1676 | n914); + assign n1678 = (n4130 | n1702) & (n1853 | n1408); + assign n1679 = n1848 & n1378; + assign n1680 = n1362 & n1678 & (n1679 | n914); + assign n1681 = (n4132 | n1702) & (n1818 | n1408); + assign n1682 = n1813 & n1387; + assign n1683 = n1362 & n1681 & (n1682 | n914); + assign n1684 = (n1764 | n3893) & (n4119 | n2109); + assign n1685 = n1362 & (n4120 | n914); + assign n1686 = n1766 & n1397; + assign n1687 = n1684 & n1685 & (n1686 | n1408); + assign n1688 = (n1728 | n3893) & (n4123 | n2109); + assign n1689 = n1362 & (n4124 | n914); + assign n1690 = n1731 & n1411; + assign n1691 = n1688 & n1689 & (n1690 | n1408); + assign n1692 = (n1834 | n3893) & (n4121 | n2109); + assign n1693 = n1362 & (n4122 | n914); + assign n1694 = n1836 & n1423; + assign n1695 = n1692 & n1693 & (n1694 | n1408); + assign n1696 = (n1799 | n3893) & (n4125 | n2109); + assign n1697 = n1362 & (n4126 | n914); + assign n1698 = n1801 & n1435; + assign n1699 = n1696 & n1697 & (n1698 | n1408); + assign n1700 = (Pi20 & n1368) | (n1366 & (~Pi20 | n1368)); + assign n1701 = Pi19 | n2254; + assign n1702 = ~Pi19 | n2254; + assign n1703 = (n1700 | n1701) & (n1370 | n1702); + assign n1704 = (Pi20 & n1377) | (n1375 & (~Pi20 | n1377)); + assign n1705 = (n1704 | n1701) & (n1379 | n1702); + assign n1706 = (Pi20 & n1386) | (n1384 & (~Pi20 | n1386)); + assign n1707 = (n1706 | n1701) & (n1388 | n1702); + assign n1708 = (Pi20 & n1412) | (n1410 & (~Pi20 | n1412)); + assign n1709 = (Pi20 & n1416) | (n1414 & (~Pi20 | n1416)); + assign n1710 = (n1708 | n1701) & (n1709 | n1702); + assign n1711 = (Pi20 & n1424) | (n1422 & (~Pi20 | n1424)); + assign n1712 = (Pi20 & n1428) | (n1426 & (~Pi20 | n1428)); + assign n1713 = (n1711 | n1701) & (n1712 | n1702); + assign n1714 = (Pi20 & n1436) | (n1434 & (~Pi20 | n1436)); + assign n1715 = (Pi20 & n1440) | (n1438 & (~Pi20 | n1440)); + assign n1716 = (n1714 | n1701) & (n1715 | n1702); + assign n1717 = n1446 | n4684 | n4685; + assign n1718 = ~n4683 & (Pi17 | (n4127 & n4128)); + assign n1719 = n1717 & (n1718 | n1448); + assign n1720 = ~n724 | n4767; + assign n1721 = ~n724 & n1354; + assign n1722 = n1354 & n1720 & (n18 | n1721); + assign n1723 = ~n728 | n4767; + assign n1724 = ~n728 & n1354; + assign n1725 = n1354 & n1723 & (n18 | n1724); + assign n1726 = (n1722 | n3915) & (n1725 | n3916); + assign n1727 = ~n3918 & (n3917 | n4123); + assign n1728 = n1720 & n1415; + assign n1729 = ~n789 | n3857; + assign n1730 = n1726 & n1727 & (n1728 | n1729); + assign n1731 = ~n717 | n4767; + assign n1732 = ~n717 & n1354; + assign n1733 = n1354 & n1731 & (n18 | n1732); + assign n1734 = ~n720 | n4767; + assign n1735 = ~n720 & n1354; + assign n1736 = n1354 & n1734 & (n18 | n1735); + assign n1737 = (n1733 | n3915) & (n1736 | n3916); + assign n1738 = ~n3918 & (n3917 | n4124); + assign n1739 = n1737 & n1738 & (n1690 | n1729); + assign n1740 = ~n732 | n4767; + assign n1741 = ~n732 & n1354; + assign n1742 = n1354 & n1740 & (n18 | n1741); + assign n1743 = ~n736 | n4767; + assign n1744 = ~n736 & n1354; + assign n1745 = n1354 & n1743 & (n18 | n1744); + assign n1746 = (n1742 | n3915) & (n1745 | n3916); + assign n1747 = ~n3918 & (n1676 | n3917); + assign n1748 = n1740 & n1367; + assign n1749 = n1746 & n1747 & (n1748 | n1729); + assign n1750 = ~n739 | n4767; + assign n1751 = ~n739 & n1354; + assign n1752 = n1354 & n1750 & (n18 | n1751); + assign n1753 = (n1749 | n3864) & (n1739 | n3867); + assign n1754 = n4244 & n4242 & (n4131 | n3914); + assign n1755 = n1753 & n1754 & (n1730 | n1322); + assign n1756 = ~n699 | n4767; + assign n1757 = ~n699 & n1354; + assign n1758 = n1354 & n1756 & (n18 | n1757); + assign n1759 = ~n703 | n4767; + assign n1760 = ~n703 & n1354; + assign n1761 = n1354 & n1759 & (n18 | n1760); + assign n1762 = (n1758 | n3915) & (n1761 | n3916); + assign n1763 = ~n3918 & (n3917 | n4119); + assign n1764 = n1756 & n1402; + assign n1765 = n1762 & n1763 & (n1764 | n1729); + assign n1766 = ~n691 | n4767; + assign n1767 = ~n691 & n1354; + assign n1768 = n1354 & n1766 & (n18 | n1767); + assign n1769 = ~n694 | n4767; + assign n1770 = ~n694 & n1354; + assign n1771 = n1354 & n1769 & (n18 | n1770); + assign n1772 = (n1768 | n3915) & (n1771 | n3916); + assign n1773 = ~n3918 & (n3917 | n4120); + assign n1774 = n1772 & n1773 & (n1686 | n1729); + assign n1775 = ~n707 | n4767; + assign n1776 = ~n707 & n1354; + assign n1777 = n1354 & n1775 & (n18 | n1776); + assign n1778 = ~n711 | n4767; + assign n1779 = ~n711 & n1354; + assign n1780 = n1354 & n1778 & (n18 | n1779); + assign n1781 = (n1777 | n3915) & (n1780 | n3916); + assign n1782 = ~n3918 & (n1673 | n3917); + assign n1783 = n1775 & n1357; + assign n1784 = n1781 & n1782 & (n1783 | n1729); + assign n1785 = ~n714 | n4767; + assign n1786 = ~n714 & n1354; + assign n1787 = n1354 & n1785 & (n18 | n1786); + assign n1788 = (n1784 | n3864) & (n1774 | n3867); + assign n1789 = n4241 & n4242 & (n4129 | n3914); + assign n1790 = n1788 & n1789 & (n1765 | n1322); + assign n1791 = ~n755 | n4767; + assign n1792 = ~n755 & n1354; + assign n1793 = n1354 & n1791 & (n18 | n1792); + assign n1794 = ~n757 | n4767; + assign n1795 = ~n757 & n1354; + assign n1796 = n1354 & n1794 & (n18 | n1795); + assign n1797 = (n1793 | n3915) & (n1796 | n3916); + assign n1798 = ~n3918 & (n3917 | n4125); + assign n1799 = n1791 & n1439; + assign n1800 = n1797 & n1798 & (n1799 | n1729); + assign n1801 = ~n752 | n4767; + assign n1802 = ~n752 & n1354; + assign n1803 = n1354 & n1801 & (n18 | n1802); + assign n1804 = ~n753 | n4767; + assign n1805 = ~n753 & n1354; + assign n1806 = n1354 & n1804 & (n18 | n1805); + assign n1807 = (n1803 | n3915) & (n1806 | n3916); + assign n1808 = ~n3918 & (n3917 | n4126); + assign n1809 = n1807 & n1808 & (n1698 | n1729); + assign n1810 = ~n759 | n4767; + assign n1811 = ~n759 & n1354; + assign n1812 = n1354 & n1810 & (n18 | n1811); + assign n1813 = ~n761 | n4767; + assign n1814 = ~n761 & n1354; + assign n1815 = n1354 & n1813 & (n18 | n1814); + assign n1816 = (n1812 | n3915) & (n1815 | n3916); + assign n1817 = ~n3918 & (n1682 | n3917); + assign n1818 = n1810 & n1385; + assign n1819 = n1816 & n1817 & (n1818 | n1729); + assign n1820 = n4767 | n1468; + assign n1821 = n1468 & n1354; + assign n1822 = n1354 & n1820 & (n18 | n1821); + assign n1823 = (n1819 | n3864) & (n1809 | n3867); + assign n1824 = n4245 & n4242 & (n4132 | n3914); + assign n1825 = n1823 & n1824 & (n1800 | n1322); + assign n1826 = ~n745 | n4767; + assign n1827 = ~n745 & n1354; + assign n1828 = n1354 & n1826 & (n18 | n1827); + assign n1829 = ~n747 | n4767; + assign n1830 = ~n747 & n1354; + assign n1831 = n1354 & n1829 & (n18 | n1830); + assign n1832 = (n1828 | n3915) & (n1831 | n3916); + assign n1833 = ~n3918 & (n3917 | n4121); + assign n1834 = n1826 & n1427; + assign n1835 = n1832 & n1833 & (n1834 | n1729); + assign n1836 = ~n742 | n4767; + assign n1837 = ~n742 & n1354; + assign n1838 = n1354 & n1836 & (n18 | n1837); + assign n1839 = ~n743 | n4767; + assign n1840 = ~n743 & n1354; + assign n1841 = n1354 & n1839 & (n18 | n1840); + assign n1842 = (n1838 | n3915) & (n1841 | n3916); + assign n1843 = ~n3918 & (n3917 | n4122); + assign n1844 = n1842 & n1843 & (n1694 | n1729); + assign n1845 = ~n749 | n4767; + assign n1846 = ~n749 & n1354; + assign n1847 = n1354 & n1845 & (n18 | n1846); + assign n1848 = ~n751 | n4767; + assign n1849 = ~n751 & n1354; + assign n1850 = n1354 & n1848 & (n18 | n1849); + assign n1851 = (n1847 | n3915) & (n1850 | n3916); + assign n1852 = ~n3918 & (n1679 | n3917); + assign n1853 = n1845 & n1376; + assign n1854 = n1851 & n1852 & (n1853 | n1729); + assign n1855 = n4767 | n1465; + assign n1856 = n1465 & n1354; + assign n1857 = n1354 & n1855 & (n18 | n1856); + assign n1858 = (n1854 | n3864) & (n1844 | n3867); + assign n1859 = n4243 & n4242 & (n4130 | n3914); + assign n1860 = n1858 & n1859 & (n1835 | n1322); + assign n1861 = ~n2272 & (~n4226 | ~n4227); + assign n1862 = ~n2272 & (~n4207 | ~n4208); + assign n1863 = n3696 | n4680 | n4682; + assign n1864 = n1719 & (n2632 | (n4247 & n4246)); + assign n1865 = n1863 & n1864 & (n1718 | n1452); + assign n1866 = (n1722 | n3901) & (n1725 | n3902); + assign n1867 = n1455 & (n4123 | n3903); + assign n1868 = ~n3761 | n3857; + assign n1869 = n1866 & n1867 & (n1728 | n1868); + assign n1870 = (n1733 | n3901) & (n1736 | n3902); + assign n1871 = n1455 & (n4124 | n3903); + assign n1872 = n1870 & n1871 & (n1690 | n1868); + assign n1873 = (n1742 | n3901) & (n1745 | n3902); + assign n1874 = n1455 & (n1676 | n3903); + assign n1875 = n1873 & n1874 & (n1748 | n1868); + assign n1876 = (n1875 | n3864) & (n1872 | n3867); + assign n1877 = n4201 & n4199 & (n4131 | n3900); + assign n1878 = n1876 & n1877 & (n1869 | n1322); + assign n1879 = (n1758 | n3901) & (n1761 | n3902); + assign n1880 = n1455 & (n4119 | n3903); + assign n1881 = n1879 & n1880 & (n1764 | n1868); + assign n1882 = (n1768 | n3901) & (n1771 | n3902); + assign n1883 = n1455 & (n4120 | n3903); + assign n1884 = n1882 & n1883 & (n1686 | n1868); + assign n1885 = (n1777 | n3901) & (n1780 | n3902); + assign n1886 = n1455 & (n1673 | n3903); + assign n1887 = n1885 & n1886 & (n1783 | n1868); + assign n1888 = (n1887 | n3864) & (n1884 | n3867); + assign n1889 = n4198 & n4199 & (n4129 | n3900); + assign n1890 = n1888 & n1889 & (n1881 | n1322); + assign n1891 = (n1793 | n3901) & (n1796 | n3902); + assign n1892 = n1455 & (n4125 | n3903); + assign n1893 = n1891 & n1892 & (n1799 | n1868); + assign n1894 = (n1803 | n3901) & (n1806 | n3902); + assign n1895 = n1455 & (n4126 | n3903); + assign n1896 = n1894 & n1895 & (n1698 | n1868); + assign n1897 = (n1812 | n3901) & (n1815 | n3902); + assign n1898 = n1455 & (n1682 | n3903); + assign n1899 = n1897 & n1898 & (n1818 | n1868); + assign n1900 = (n1899 | n3864) & (n1896 | n3867); + assign n1901 = n4202 & n4199 & (n4132 | n3900); + assign n1902 = n1900 & n1901 & (n1893 | n1322); + assign n1903 = (n1828 | n3901) & (n1831 | n3902); + assign n1904 = n1455 & (n4121 | n3903); + assign n1905 = n1903 & n1904 & (n1834 | n1868); + assign n1906 = (n1838 | n3901) & (n1841 | n3902); + assign n1907 = n1455 & (n4122 | n3903); + assign n1908 = n1906 & n1907 & (n1694 | n1868); + assign n1909 = (n1847 | n3901) & (n1850 | n3902); + assign n1910 = n1455 & (n1679 | n3903); + assign n1911 = n1909 & n1910 & (n1853 | n1868); + assign n1912 = (n1911 | n3864) & (n1908 | n3867); + assign n1913 = n4200 & n4199 & (n4130 | n3900); + assign n1914 = n1912 & n1913 & (n1905 | n1322); + assign n1915 = (n1878 | n3884) & (n1902 | n3891); + assign n1916 = (n1890 | n3870) & (n1914 | n3877); + assign n1917 = n1915 & n1916; + assign n1918 = ~Ni30 & n1540; + assign n1919 = Pi25 | n2254; + assign n1920 = n1362 & (n1918 | n1919); + assign n1921 = n1920 & (n1929 | (n4118 & n4116)); + assign n1922 = n1379 & (~Pi16 | n1388); + assign n1923 = ~Pi25 | n3848; + assign n1924 = n1921 & (n1922 | n1923); + assign n1925 = n1920 & (n1929 | (n4114 & n4112)); + assign n1926 = n1360 & (~Pi16 | n1370); + assign n1927 = n1925 & (n1926 | n1923); + assign n1928 = (n4149 | n3858) & (n1382 | n3860); + assign n1929 = ~Pi25 | n2254; + assign n1930 = n1928 & (n1704 | n1929); + assign n1931 = ~n3740 & ((~n1706 & ~n1929) | ~n4151); + assign n1932 = ~n2272 & ((~n1711 & ~n1929) | ~n4153); + assign n1933 = ~n3895 & ((~n1712 & ~n1929) | ~n4156); + assign n1934 = ~n3743 & ((~n1714 & ~n1929) | ~n4158); + assign n1935 = ~n3737 & ((~n1715 & ~n1929) | ~n4161); + assign n1936 = (n4135 | n3858) & (n1364 | n3860); + assign n1937 = (Pi20 & n1358) | (n1356 & (~Pi20 | n1358)); + assign n1938 = n1936 & (n1937 | n1929); + assign n1939 = ~n3740 & ((~n1700 & ~n1929) | ~n4137); + assign n1940 = ~n2272 & ((~n1929 & ~n1961) | ~n4139); + assign n1941 = ~n3895 & ((~n1929 & ~n1958) | ~n4142); + assign n1942 = ~n3743 & ((~n1708 & ~n1929) | ~n4144); + assign n1943 = ~n3737 & ((~n1709 & ~n1929) | ~n4147); + assign n1944 = (~Pi15 & n1927) | (n1924 & (Pi15 | n1927)); + assign n1945 = (n1448 | n1944) & (n1446 | ~n3990); + assign n1946 = n1455 & (n1541 | n1919); + assign n1947 = (n1721 | n3931) & (n1724 | n3932); + assign n1948 = n1929 | ~n3761; + assign n1949 = n1946 & n1947 & (n1709 | n1948); + assign n1950 = (n1732 | n3931) & (n1735 | n3932); + assign n1951 = n1946 & n1950 & (n1708 | n1948); + assign n1952 = (n1741 | n3931) & (n1744 | n3932); + assign n1953 = n1946 & n1952 & (n1700 | n1948); + assign n1954 = (n1953 | n3864) & (n1951 | n3867); + assign n1955 = n4190 & n4188 & (n1370 | n3930); + assign n1956 = n1954 & n1955 & (n1949 | n1322); + assign n1957 = (n1757 | n3931) & (n1760 | n3932); + assign n1958 = (Pi20 & n1403) | (n1401 & (~Pi20 | n1403)); + assign n1959 = n1946 & n1957 & (n1958 | n1948); + assign n1960 = (n1767 | n3931) & (n1770 | n3932); + assign n1961 = (Pi20 & n1399) | (n1396 & (~Pi20 | n1399)); + assign n1962 = n1946 & n1960 & (n1961 | n1948); + assign n1963 = (n1776 | n3931) & (n1779 | n3932); + assign n1964 = n1946 & n1963 & (n1937 | n1948); + assign n1965 = (n1964 | n3864) & (n1962 | n3867); + assign n1966 = n4187 & n4188 & (n1360 | n3930); + assign n1967 = n1965 & n1966 & (n1959 | n1322); + assign n1968 = (n1792 | n3931) & (n1795 | n3932); + assign n1969 = n1946 & n1968 & (n1715 | n1948); + assign n1970 = (n1802 | n3931) & (n1805 | n3932); + assign n1971 = n1946 & n1970 & (n1714 | n1948); + assign n1972 = (n1811 | n3931) & (n1814 | n3932); + assign n1973 = n1946 & n1972 & (n1706 | n1948); + assign n1974 = (n1973 | n3864) & (n1971 | n3867); + assign n1975 = n4191 & n4188 & (n1388 | n3930); + assign n1976 = n1974 & n1975 & (n1969 | n1322); + assign n1977 = (n1827 | n3931) & (n1830 | n3932); + assign n1978 = n1946 & n1977 & (n1712 | n1948); + assign n1979 = (n1837 | n3931) & (n1840 | n3932); + assign n1980 = n1946 & n1979 & (n1711 | n1948); + assign n1981 = (n1846 | n3931) & (n1849 | n3932); + assign n1982 = n1946 & n1981 & (n1704 | n1948); + assign n1983 = (n1982 | n3864) & (n1980 | n3867); + assign n1984 = n4189 & n4188 & (n1379 | n3930); + assign n1985 = n1983 & n1984 & (n1978 | n1322); + assign n1986 = n3793 & (Pi27 | n1918); + assign n1987 = n1552 & (n1986 | n1919); + assign n1988 = (n1709 | n3922) & (n1721 | n3923); + assign n1989 = ~Pi27 | n1314; + assign n1990 = n1987 & n1988 & (n1724 | n1989); + assign n1991 = (n1708 | n3922) & (n1732 | n3923); + assign n1992 = n1987 & n1991 & (n1735 | n1989); + assign n1993 = (n1700 | n3922) & (n1741 | n3923); + assign n1994 = n1987 & n1993 & (n1744 | n1989); + assign n1995 = (n1994 | n3864) & (n1992 | n3867); + assign n1996 = n4183 & n4181 & (n1751 | n3921); + assign n1997 = n1995 & n1996 & (n1990 | n1322); + assign n1998 = (n1958 | n3922) & (n1757 | n3923); + assign n1999 = n1987 & n1998 & (n1760 | n1989); + assign n2000 = (n1961 | n3922) & (n1767 | n3923); + assign n2001 = n1987 & n2000 & (n1770 | n1989); + assign n2002 = (n1937 | n3922) & (n1776 | n3923); + assign n2003 = n1987 & n2002 & (n1779 | n1989); + assign n2004 = (n2003 | n3864) & (n2001 | n3867); + assign n2005 = n4180 & n4181 & (n1786 | n3921); + assign n2006 = n2004 & n2005 & (n1999 | n1322); + assign n2007 = (n1715 | n3922) & (n1792 | n3923); + assign n2008 = n1987 & n2007 & (n1795 | n1989); + assign n2009 = (n1714 | n3922) & (n1802 | n3923); + assign n2010 = n1987 & n2009 & (n1805 | n1989); + assign n2011 = (n1706 | n3922) & (n1811 | n3923); + assign n2012 = n1987 & n2011 & (n1814 | n1989); + assign n2013 = (n2012 | n3864) & (n2010 | n3867); + assign n2014 = n4184 & n4181 & (n1821 | n3921); + assign n2015 = n2013 & n2014 & (n2008 | n1322); + assign n2016 = (n1712 | n3922) & (n1827 | n3923); + assign n2017 = n1987 & n2016 & (n1830 | n1989); + assign n2018 = (n1711 | n3922) & (n1837 | n3923); + assign n2019 = n1987 & n2018 & (n1840 | n1989); + assign n2020 = (n1704 | n3922) & (n1846 | n3923); + assign n2021 = n1987 & n2020 & (n1849 | n1989); + assign n2022 = (n2021 | n3864) & (n2019 | n3867); + assign n2023 = n4182 & n4181 & (n1856 | n3921); + assign n2024 = n2022 & n2023 & (n2017 | n1322); + assign n2025 = (~Pi26 | n1918) & n3794; + assign n2026 = ~n3918 & (n1919 | n2025); + assign n2027 = (n1721 | n3926) & (n1724 | n3927); + assign n2028 = ~n789 | n1929; + assign n2029 = n2026 & n2027 & (n1709 | n2028); + assign n2030 = (n1732 | n3926) & (n1735 | n3927); + assign n2031 = n2026 & n2030 & (n1708 | n2028); + assign n2032 = (n1741 | n3926) & (n1744 | n3927); + assign n2033 = n2026 & n2032 & (n1700 | n2028); + assign n2034 = (n2033 | n3864) & (n2031 | n3867); + assign n2035 = n4176 & n4174 & (n1370 | n3925); + assign n2036 = n2034 & n2035 & (n2029 | n1322); + assign n2037 = (n1757 | n3926) & (n1760 | n3927); + assign n2038 = n2026 & n2037 & (n1958 | n2028); + assign n2039 = (n1767 | n3926) & (n1770 | n3927); + assign n2040 = n2026 & n2039 & (n1961 | n2028); + assign n2041 = (n1776 | n3926) & (n1779 | n3927); + assign n2042 = n2026 & n2041 & (n1937 | n2028); + assign n2043 = (n2042 | n3864) & (n2040 | n3867); + assign n2044 = n4173 & n4174 & (n1360 | n3925); + assign n2045 = n2043 & n2044 & (n2038 | n1322); + assign n2046 = (n1792 | n3926) & (n1795 | n3927); + assign n2047 = n2026 & n2046 & (n1715 | n2028); + assign n2048 = (n1802 | n3926) & (n1805 | n3927); + assign n2049 = n2026 & n2048 & (n1714 | n2028); + assign n2050 = (n1811 | n3926) & (n1814 | n3927); + assign n2051 = n2026 & n2050 & (n1706 | n2028); + assign n2052 = (n2051 | n3864) & (n2049 | n3867); + assign n2053 = n4177 & n4174 & (n1388 | n3925); + assign n2054 = n2052 & n2053 & (n2047 | n1322); + assign n2055 = (n1827 | n3926) & (n1830 | n3927); + assign n2056 = n2026 & n2055 & (n1712 | n2028); + assign n2057 = (n1837 | n3926) & (n1840 | n3927); + assign n2058 = n2026 & n2057 & (n1711 | n2028); + assign n2059 = (n1846 | n3926) & (n1849 | n3927); + assign n2060 = n2026 & n2059 & (n1704 | n2028); + assign n2061 = (n2060 | n3864) & (n2058 | n3867); + assign n2062 = n4175 & n4174 & (n1379 | n3925); + assign n2063 = n2061 & n2062 & (n2056 | n1322); + assign n2064 = (n1611 | n3937) & (n3805 | ~n3992); + assign n2065 = (n1669 | n3766) & (n1458 | n1671); + assign n2066 = ~Ni10 | n3768; + assign n2067 = n2064 & n2065 & (n2066 | ~n4773); + assign n2068 = (n1449 | Ni11) & (n1447 | ~n1543); + assign n2069 = (n1945 | n3897) & (~n1543 | ~n3989); + assign n2070 = Ni11 | ~Ni10; + assign n2071 = n2069 & (n1719 | n2070); + assign n2072 = Ni7 & n2398; + assign n2073 = n2398 & ~Ni7; + assign n2074 = Ni9 | Ni8; + assign n2075 = ~n2068 & (n2072 | (n2073 & n2074)); + assign n2076 = ~n3896 | n2067 | n3707; + assign n2077 = ~n2075 & (n2071 | ~n2073 | n2074); + assign n2078 = ~Ni32 & ~Ni30; + assign n2079 = ~n18 | n1539; + assign n2080 = ~Ni34 | ~Ni33; + assign n2081 = ~n792 & (n2079 | n2080); + assign n2082 = (~Ni34 | n821) & n2081; + assign n2083 = (~Ni34 | n857) & n2081; + assign n2084 = (~Ni34 | n895) & n2081; + assign n2085 = ~Ni34 | ~n793; + assign n2086 = (n2082 | n1408) & (n2083 | n914); + assign n2087 = n2085 & n2086 & (n2084 | n1702); + assign n2088 = (~Ni34 | n922) & n2081; + assign n2089 = (~Ni34 | n947) & n2081; + assign n2090 = (~Ni34 | n974) & n2081; + assign n2091 = (n2088 | n1408) & (n2089 | n914); + assign n2092 = n2085 & n2091 & (n2090 | n1702); + assign n2093 = (~Ni34 | n984) & n2081; + assign n2094 = (~Ni34 | n1001_1) & n2081; + assign n2095 = (~Ni34 | n882) & n2081; + assign n2096 = (n2093 | n1408) & (n2094 | n914); + assign n2097 = n2085 & n2096 & (n2095 | n1702); + assign n2098 = (~Ni34 | n1021_1) & n2081; + assign n2099 = (~Ni34 | n1028) & n2081; + assign n2100 = (~Ni34 | n966) & n2081; + assign n2101 = (n2098 | n1408) & (n2099 | n914); + assign n2102 = n2085 & n2101 & (n2100 | n1702); + assign n2103 = (~Ni34 | n1049) & n2081; + assign n2104 = (~Ni34 | n1065) & n2081; + assign n2105 = (~Ni34 | n1081_1) & n2081; + assign n2106 = (~Ni34 | n1108) & n2081; + assign n2107 = n2085 & (n2105 | n3893); + assign n2108 = (n2103 | n1408) & (n2104 | n914); + assign n2109 = ~Pi19 | n3859; + assign n2110 = n2107 & n2108 & (n2106 | n2109); + assign n2111 = (~Ni34 | n1135) & n2081; + assign n2112 = (~Ni34 | n1149) & n2081; + assign n2113 = (~Ni34 | n1165) & n2081; + assign n2114 = (~Ni34 | n1189) & n2081; + assign n2115 = n2085 & (n2113 | n3893); + assign n2116 = (n2111 | n1408) & (n2112 | n914); + assign n2117 = n2115 & n2116 & (n2114 | n2109); + assign n2118 = (~Ni34 | n1217) & n2081; + assign n2119 = (~Ni34 | n1228) & n2081; + assign n2120 = (~Ni34 | n1235) & n2081; + assign n2121 = (~Ni34 | n1247) & n2081; + assign n2122 = n2085 & (n2120 | n3893); + assign n2123 = (n2118 | n1408) & (n2119 | n914); + assign n2124 = n2122 & n2123 & (n2121 | n2109); + assign n2125 = (~Ni34 | n1259) & n2081; + assign n2126 = (~Ni34 | n1266) & n2081; + assign n2127 = (~Ni34 | n1273) & n2081; + assign n2128 = (~Ni34 | n1280) & n2081; + assign n2129 = n2085 & (n2127 | n3893); + assign n2130 = (n2125 | n1408) & (n2126 | n914); + assign n2131 = n2129 & n2130 & (n2128 | n2109); + assign n2132 = n2080 & (~Ni33 | ~n821); + assign n2133 = (n2132 | n3949) & (~n821 | n3951); + assign n2134 = (n821 & n4691) | (n4690 & (~n821 | n4691)); + assign n2135 = n2082 & n2133 & (~Pi25 | n2134); + assign n2136 = n2080 & (~Ni33 | ~n857); + assign n2137 = (n2136 | n3949) & (~n857 | n3951); + assign n2138 = (n857 & n4691) | (n4690 & (~n857 | n4691)); + assign n2139 = n2083 & n2137 & (~Pi25 | n2138); + assign n2140 = n2080 & (~Ni33 | ~n895); + assign n2141 = (n2140 | n3949) & (~n895 | n3951); + assign n2142 = (n895 & n4691) | (n4690 & (~n895 | n4691)); + assign n2143 = n2084 & n2141 & (~Pi25 | n2142); + assign n2144 = (n2135 | n1408) & (n2139 | n914); + assign n2145 = n2085 & n2144 & (n2143 | n1702); + assign n2146 = n2080 & (~Ni33 | ~n922); + assign n2147 = (n2146 | n3949) & (~n922 | n3951); + assign n2148 = (n922 & n4691) | (n4690 & (~n922 | n4691)); + assign n2149 = n2088 & n2147 & (~Pi25 | n2148); + assign n2150 = n2080 & (~Ni33 | ~n947); + assign n2151 = (n2150 | n3949) & (~n947 | n3951); + assign n2152 = (n947 & n4691) | (n4690 & (~n947 | n4691)); + assign n2153 = n2089 & n2151 & (~Pi25 | n2152); + assign n2154 = n2080 & (~Ni33 | ~n974); + assign n2155 = (n2154 | n3949) & (~n974 | n3951); + assign n2156 = (n974 & n4691) | (n4690 & (~n974 | n4691)); + assign n2157 = n2090 & n2155 & (~Pi25 | n2156); + assign n2158 = (n2149 | n1408) & (n2153 | n914); + assign n2159 = n2085 & n2158 & (n2157 | n1702); + assign n2160 = n2080 & (~Ni33 | ~n984); + assign n2161 = (n2160 | n3949) & (~n984 | n3951); + assign n2162 = (n984 & n4691) | (n4690 & (~n984 | n4691)); + assign n2163 = n2093 & n2161 & (~Pi25 | n2162); + assign n2164 = n2080 & (~Ni33 | ~n1001_1); + assign n2165 = (n2164 | n3949) & (~n1001_1 | n3951); + assign n2166 = (n1001_1 & n4691) | (n4690 & (~n1001_1 | n4691)); + assign n2167 = n2094 & n2165 & (~Pi25 | n2166); + assign n2168 = n2080 & (~Ni33 | ~n882); + assign n2169 = (n2168 | n3949) & (~n882 | n3951); + assign n2170 = (n882 & n4691) | (n4690 & (~n882 | n4691)); + assign n2171 = n2095 & n2169 & (~Pi25 | n2170); + assign n2172 = (n2163 | n1408) & (n2167 | n914); + assign n2173 = n2085 & n2172 & (n2171 | n1702); + assign n2174 = n2080 & (~Ni33 | ~n1021_1); + assign n2175 = (n2174 | n3949) & (~n1021_1 | n3951); + assign n2176 = (n1021_1 & n4691) | (n4690 & (~n1021_1 | n4691)); + assign n2177 = n2098 & n2175 & (~Pi25 | n2176); + assign n2178 = n2080 & (~Ni33 | ~n1028); + assign n2179 = (n2178 | n3949) & (~n1028 | n3951); + assign n2180 = (n1028 & n4691) | (n4690 & (~n1028 | n4691)); + assign n2181 = n2099 & n2179 & (~Pi25 | n2180); + assign n2182 = n2080 & (~Ni33 | ~n966); + assign n2183 = (n2182 | n3949) & (~n966 | n3951); + assign n2184 = (n966 & n4691) | (n4690 & (~n966 | n4691)); + assign n2185 = n2100 & n2183 & (~Pi25 | n2184); + assign n2186 = (n2177 | n1408) & (n2181 | n914); + assign n2187 = n2085 & n2186 & (n2185 | n1702); + assign n2188 = n2080 & (~Ni33 | ~n1049); + assign n2189 = (n2188 | n3949) & (~n1049 | n3951); + assign n2190 = (n1049 & n4691) | (n4690 & (~n1049 | n4691)); + assign n2191 = n2103 & n2189 & (~Pi25 | n2190); + assign n2192 = n2080 & (~Ni33 | ~n1065); + assign n2193 = (n2192 | n3949) & (~n1065 | n3951); + assign n2194 = (n1065 & n4691) | (n4690 & (~n1065 | n4691)); + assign n2195 = n2104 & n2193 & (~Pi25 | n2194); + assign n2196 = n2080 & (~Ni33 | ~n1081_1); + assign n2197 = n2080 & (~Ni33 | ~n1108); + assign n2198 = (n2197 | n3949) & (~n1108 | n3951); + assign n2199 = (n1108 & n4691) | (n4690 & (~n1108 | n4691)); + assign n2200 = n2106 & n2198 & (~Pi25 | n2199); + assign n2201 = n2085 & (n3893 | (n4309 & n4308)); + assign n2202 = (n2191 | n1408) & (n2195 | n914); + assign n2203 = n2201 & n2202 & (n2200 | n2109); + assign n2204 = n2080 & (~Ni33 | ~n1135); + assign n2205 = (n2204 | n3949) & (~n1135 | n3951); + assign n2206 = (n1135 & n4691) | (n4690 & (~n1135 | n4691)); + assign n2207 = n2111 & n2205 & (~Pi25 | n2206); + assign n2208 = n2080 & (~Ni33 | ~n1149); + assign n2209 = (n2208 | n3949) & (~n1149 | n3951); + assign n2210 = (n1149 & n4691) | (n4690 & (~n1149 | n4691)); + assign n2211 = n2112 & n2209 & (~Pi25 | n2210); + assign n2212 = n2080 & (~Ni33 | ~n1165); + assign n2213 = n2080 & (~Ni33 | ~n1189); + assign n2214 = (n2213 | n3949) & (~n1189 | n3951); + assign n2215 = (n1189 & n4691) | (n4690 & (~n1189 | n4691)); + assign n2216 = n2114 & n2214 & (~Pi25 | n2215); + assign n2217 = n2085 & (n3893 | (n4313 & n4312)); + assign n2218 = (n2207 | n1408) & (n2211 | n914); + assign n2219 = n2217 & n2218 & (n2216 | n2109); + assign n2220 = n2080 & (~Ni33 | ~n1217); + assign n2221 = (n2220 | n3949) & (~n1217 | n3951); + assign n2222 = (n1217 & n4691) | (n4690 & (~n1217 | n4691)); + assign n2223 = n2118 & n2221 & (~Pi25 | n2222); + assign n2224 = n2080 & (~Ni33 | ~n1228); + assign n2225 = (n2224 | n3949) & (~n1228 | n3951); + assign n2226 = (n1228 & n4691) | (n4690 & (~n1228 | n4691)); + assign n2227 = n2119 & n2225 & (~Pi25 | n2226); + assign n2228 = n2080 & (~Ni33 | ~n1235); + assign n2229 = n2080 & (~Ni33 | ~n1247); + assign n2230 = (n2229 | n3949) & (~n1247 | n3951); + assign n2231 = (n1247 & n4691) | (n4690 & (~n1247 | n4691)); + assign n2232 = n2121 & n2230 & (~Pi25 | n2231); + assign n2233 = n2085 & (n3893 | (n4311 & n4310)); + assign n2234 = (n2223 | n1408) & (n2227 | n914); + assign n2235 = n2233 & n2234 & (n2232 | n2109); + assign n2236 = n2080 & (~Ni33 | ~n1259); + assign n2237 = (n2236 | n3949) & (~n1259 | n3951); + assign n2238 = (n1259 & n4691) | (n4690 & (~n1259 | n4691)); + assign n2239 = n2125 & n2237 & (~Pi25 | n2238); + assign n2240 = n2080 & (~Ni33 | ~n1266); + assign n2241 = (n2240 | n3949) & (~n1266 | n3951); + assign n2242 = (n1266 & n4691) | (n4690 & (~n1266 | n4691)); + assign n2243 = n2126 & n2241 & (~Pi25 | n2242); + assign n2244 = n2080 & (~Ni33 | ~n1273); + assign n2245 = n2080 & (~Ni33 | ~n1280); + assign n2246 = (n2245 | n3949) & (~n1280 | n3951); + assign n2247 = (n1280 & n4691) | (n4690 & (~n1280 | n4691)); + assign n2248 = n2128 & n2246 & (~Pi25 | n2247); + assign n2249 = n2085 & (n3893 | (n4315 & n4314)); + assign n2250 = (n2239 | n1408) & (n2243 | n914); + assign n2251 = n2249 & n2250 & (n2248 | n2109); + assign n2252 = ~n792 & n2085; + assign n2253 = (n882 | n3954) & (n2168 | n3952); + assign n2254 = ~Pi22 | ~Pi21; + assign n2255 = n2252 & n2253 & (n2170 | n2254); + assign n2256 = (n966 | n3954) & (n2182 | n3952); + assign n2257 = n2252 & n2256 & (n2184 | n2254); + assign n2258 = (n1228 | n3954) & (n2224 | n3952); + assign n2259 = n2252 & n2258 & (n2226 | n2254); + assign n2260 = (n1247 | n3954) & (n2229 | n3952); + assign n2261 = n2252 & n2260 & (n2231 | n2254); + assign n2262 = (n1001_1 | n3954) & (n2164 | n3952); + assign n2263 = n2252 & n2262 & (n2166 | n2254); + assign n2264 = (n1266 | n3954) & (n2240 | n3952); + assign n2265 = n2252 & n2264 & (n2242 | n2254); + assign n2266 = (n1280 | n3954) & (n2245 | n3952); + assign n2267 = n2252 & n2266 & (n2247 | n2254); + assign n2268 = (n1028 | n3954) & (n2178 | n3952); + assign n2269 = n2252 & n2268 & (n2180 | n2254); + assign n2270 = (n2263 | n3894) & (n2269 | n3740); + assign n2271 = n4370 & (n2267 | n3737); + assign n2272 = Pi16 | n3867; + assign n2273 = n2270 & n2271 & (n2259 | n2272); + assign n2274 = (n1217 | n3954) & (n2220 | n3952); + assign n2275 = n2252 & n2274 & (n2222 | n2254); + assign n2276 = (n1235 | n3954) & (n2228 | n3952); + assign n2277 = (n1235 & n4691) | (n4690 & (~n1235 | n4691)); + assign n2278 = n2252 & n2276 & (n2277 | n2254); + assign n2279 = (n984 | n3954) & (n2160 | n3952); + assign n2280 = n2252 & n2279 & (n2162 | n2254); + assign n2281 = (n1259 | n3954) & (n2236 | n3952); + assign n2282 = n2252 & n2281 & (n2238 | n2254); + assign n2283 = (n1273 | n3954) & (n2244 | n3952); + assign n2284 = (n1273 & n4691) | (n4690 & (~n1273 | n4691)); + assign n2285 = n2252 & n2283 & (n2284 | n2254); + assign n2286 = (n1021_1 | n3954) & (n2174 | n3952); + assign n2287 = n2252 & n2286 & (n2176 | n2254); + assign n2288 = (n2280 | n3894) & (n2287 | n3740); + assign n2289 = n4369 & (n2285 | n3737); + assign n2290 = n2288 & n2289 & (n2275 | n2272); + assign n2291 = (n895 | n3954) & (n2140 | n3952); + assign n2292 = n2252 & n2291 & (n2142 | n2254); + assign n2293 = (n974 | n3954) & (n2154 | n3952); + assign n2294 = n2252 & n2293 & (n2156 | n2254); + assign n2295 = (n1065 | n3954) & (n2192 | n3952); + assign n2296 = n2252 & n2295 & (n2194 | n2254); + assign n2297 = (n1108 | n3954) & (n2197 | n3952); + assign n2298 = n2252 & n2297 & (n2199 | n2254); + assign n2299 = (n857 | n3954) & (n2136 | n3952); + assign n2300 = n2252 & n2299 & (n2138 | n2254); + assign n2301 = (n1149 | n3954) & (n2208 | n3952); + assign n2302 = n2252 & n2301 & (n2210 | n2254); + assign n2303 = (n1189 | n3954) & (n2213 | n3952); + assign n2304 = n2252 & n2303 & (n2215 | n2254); + assign n2305 = (n947 | n3954) & (n2150 | n3952); + assign n2306 = n2252 & n2305 & (n2152 | n2254); + assign n2307 = (n2300 | n3894) & (n2306 | n3740); + assign n2308 = n4367 & (n2304 | n3737); + assign n2309 = n2307 & n2308 & (n2296 | n2272); + assign n2310 = (n1049 | n3954) & (n2188 | n3952); + assign n2311 = n2252 & n2310 & (n2190 | n2254); + assign n2312 = (n1081_1 | n3954) & (n2196 | n3952); + assign n2313 = (n1081_1 & n4691) | (n4690 & (~n1081_1 | n4691)); + assign n2314 = n2252 & n2312 & (n2313 | n2254); + assign n2315 = (n821 | n3954) & (n2132 | n3952); + assign n2316 = n2252 & n2315 & (n2134 | n2254); + assign n2317 = (n1135 | n3954) & (n2204 | n3952); + assign n2318 = n2252 & n2317 & (n2206 | n2254); + assign n2319 = (n1165 | n3954) & (n2212 | n3952); + assign n2320 = (n1165 & n4691) | (n4690 & (~n1165 | n4691)); + assign n2321 = n2252 & n2319 & (n2320 | n2254); + assign n2322 = (n922 | n3954) & (n2146 | n3952); + assign n2323 = n2252 & n2322 & (n2148 | n2254); + assign n2324 = (n2316 | n3894) & (n2323 | n3740); + assign n2325 = n4366 & (n2321 | n3737); + assign n2326 = n2324 & n2325 & (n2311 | n2272); + assign n2327 = ~Ni34 & (~n882 | n1539); + assign n2328 = ~Ni34 & (~n966 | n1539); + assign n2329 = ~Ni34 & (~n1228 | n1539); + assign n2330 = ~Ni34 & (~n1247 | n1539); + assign n2331 = ~Ni34 & (~n1001_1 | n1539); + assign n2332 = ~Ni34 & (~n1266 | n1539); + assign n2333 = ~Ni34 & (~n1280 | n1539); + assign n2334 = ~Ni34 & (~n1028 | n1539); + assign n2335 = ~n3894 & (~n3955 | ~n4355); + assign n2336 = ~n3743 & (~n3955 | ~n4359); + assign n2337 = ~Ni34 & (~n1217 | n1539); + assign n2338 = ~Ni34 & (~n1235 | n1539); + assign n2339 = ~Ni34 & (~n984 | n1539); + assign n2340 = ~Ni34 & (~n1259 | n1539); + assign n2341 = ~Ni34 & (~n1273 | n1539); + assign n2342 = ~Ni34 & (~n1021_1 | n1539); + assign n2343 = ~n3894 & (~n3955 | ~n4345); + assign n2344 = ~n3743 & (~n3955 | ~n4349); + assign n2345 = n3184 & Pi16; + assign n2346 = n2345 & (~n3955 | ~n4344); + assign n2347 = ~Ni34 & (~n895 | n1539); + assign n2348 = ~Ni34 & (~n974 | n1539); + assign n2349 = ~Ni34 & (~n1065 | n1539); + assign n2350 = ~Ni34 & (~n1108 | n1539); + assign n2351 = ~Ni34 & (~n857 | n1539); + assign n2352 = ~Ni34 & (~n1149 | n1539); + assign n2353 = ~Ni34 & (~n1189 | n1539); + assign n2354 = ~Ni34 & (~n947 | n1539); + assign n2355 = ~n3894 & (~n3955 | ~n4332); + assign n2356 = ~n3743 & (~n3955 | ~n4336); + assign n2357 = ~Ni34 & (~n1049 | n1539); + assign n2358 = ~Ni34 & (~n1081_1 | n1539); + assign n2359 = ~Ni34 & (~n821 | n1539); + assign n2360 = ~Ni34 & (~n1135 | n1539); + assign n2361 = ~Ni34 & (~n1165 | n1539); + assign n2362 = ~Ni34 & (~n922 | n1539); + assign n2363 = ~n3894 & (~n3955 | ~n4322); + assign n2364 = ~n3743 & (~n3955 | ~n4326); + assign n2365 = n2345 & (~n3955 | ~n4321); + assign n2366 = n4371 & (n3944 | (n4368 & n4372)); + assign n2367 = ~Pi15 | n3327; + assign n2368 = (n2255 | ~n3772) & (n2257 | ~n2345); + assign n2369 = (~Pi20 & n2290) | (n2273 & (Pi20 | n2290)); + assign n2370 = n2366 & (n2367 | (n2368 & n2369)); + assign n2371 = (~Ni34 | n1919) & n2085; + assign n2372 = ~Pi25 | n3857; + assign n2373 = (n2338 | n2372) & (n2330 | n1314); + assign n2374 = (n2337 | n2372) & (n2329 | n1314); + assign n2375 = (n2339 | n2372) & (n2331 | n1314); + assign n2376 = (n2341 | n2372) & (n2333 | n1314); + assign n2377 = (n2340 | n2372) & (n2332 | n1314); + assign n2378 = (n2342 | n2372) & (n2334 | n1314); + assign n2379 = ~n1923 & ~n2328 & (Pi16 | ~n2327); + assign n2380 = (n2358 | n2372) & (n2350 | n1314); + assign n2381 = (n2357 | n2372) & (n2349 | n1314); + assign n2382 = (n2359 | n2372) & (n2351 | n1314); + assign n2383 = (n2361 | n2372) & (n2353 | n1314); + assign n2384 = (n2360 | n2372) & (n2352 | n1314); + assign n2385 = (n2362 | n2372) & (n2354 | n1314); + assign n2386 = ~n1923 & ~n2348 & (Pi16 | ~n2347); + assign n2387 = ~n4689 & (~Pi15 | ~n4305 | ~n4307); + assign n2388 = ~n3659 & (~n3994 | (n2387 & ~n3892)); + assign n2389 = ~Ni35 | Ni30; + assign n2390 = n1241 & n2389 & (~Ni35 | n1353); + assign n2391 = Ni32 | n3958; + assign n2392 = n2390 & (~Pi26 | n2391); + assign n2393 = n1543 | n3727; + assign n2394 = Ni35 & (n2393 | ~n3807); + assign n2395 = ~n2072 & (~n2073 | ~n2403); + assign n2396 = ~n2395 & (n2394 | (~n2392 & ~n2393)); + assign n2397 = ~n2073 | n2403 | n4702 | n4703; + assign n2398 = ~n3707 & ~n3896; + assign n2399 = ~Ni31 | ~Ni36; + assign n2400 = n891 & n2399 & (Ni30 | ~Ni36); + assign n2401 = (~Pi27 | n2391) & n2400; + assign n2402 = ~n4706 & (Ni36 | ~n2393); + assign n2403 = Ni8 | n3957; + assign n2404 = n2402 & (n2072 | (n2073 & n2403)); + assign n2405 = ~n2073 | n2403 | n4704 | n4705; + assign n2406 = ~Ni31 & Ni30; + assign n2407 = ~n4708 & ~Ni32 & n2406; + assign n2408 = ~Ni30 & (~n814 | (Ni37 & ~n4708)); + assign n2409 = ~Pi20 | n3961 | n3962; + assign n2410 = Pi20 | n3959 | n3962; + assign n2411 = Pi20 | n3959 | n3960; + assign n2412 = ~Pi20 | n3960 | n3961; + assign n2413 = n2412 & n2411 & n2409 & n2410; + assign n2414 = n1216 | (n784 & Ni30); + assign n2415 = ~n784 & ((Ni37 & n654) | ~n814); + assign n2416 = ~Ni31 | Ni30; + assign n2417 = Ni45 & (Ni32 | n2416); + assign n2418 = ~Ni6 | Ni5; + assign n2419 = ~Ni32 | Ni30; + assign n2420 = Ni30 | Ni31; + assign n2421 = Pi21 | ~Ni32; + assign n2422 = Pi22 | n3812; + assign n2423 = n2421 & (~Pi21 | n2422); + assign n2424 = n2419 & (~n803 | n2420); + assign n2425 = ~Ni45 & (Ni47 | ~Ni43); + assign n2426 = Ni41 | Ni42; + assign n2427 = n2425 & (Ni47 | n2426 | ~n3331); + assign n2428 = n2425 & n2451; + assign n2429 = n2518 | Ni40; + assign n2430 = ~Ni37 | Ni47 | Ni38; + assign n2431 = n3811 | n3854; + assign n2432 = n2431 & n2430 & n2428 & n2429; + assign n2433 = Ni38 | n3811; + assign n2434 = ~Ni35 | Ni36; + assign n2435 = n2432 & (n2433 | n2434); + assign n2436 = n2419 & (~n804 | ~n2435); + assign n2437 = n2419 & (n2420 | ~n2435); + assign n2438 = ~n18 | n784; + assign n2439 = n784 & n2437; + assign n2440 = n2438 & (n18 | n2439); + assign n2441 = ~Ni44 & ~Ni43; + assign n2442 = n2425 & (Ni47 | n2441 | n2426); + assign n2443 = n2523 | Ni40; + assign n2444 = n3811 | n3855; + assign n2445 = n2444 & n2430 & n2428 & n2443; + assign n2446 = n2445 & (n2433 | n2434); + assign n2447 = n2419 & (~n804 | ~n2446); + assign n2448 = n2419 & (n2420 | ~n2446); + assign n2449 = n784 & n2448; + assign n2450 = n2438 & (n18 | n2449); + assign n2451 = ~Ni41 | n3811; + assign n2452 = n2428 & n2433 & n2430; + assign n2453 = n2428 & n2430 & (Ni36 | n2452); + assign n2454 = n2419 & (~n804 | ~n2453); + assign n2455 = n2419 & (n2420 | ~n2453); + assign n2456 = n784 & n2455; + assign n2457 = n2438 & (n18 | n2456); + assign n2458 = (n2689 | n1702) & (n4404 | n1408); + assign n2459 = n2447 & n2450; + assign n2460 = n2423 & n2458 & (n2459 | n914); + assign n2461 = n2427 | Ni40; + assign n2462 = n2431 & n2430 & n2425 & n2461; + assign n2463 = n2462 & (n2433 | n2434); + assign n2464 = n2419 & (~n804 | ~n2463); + assign n2465 = n2419 & (n2420 | ~n2463); + assign n2466 = n784 & n2465; + assign n2467 = n2438 & (n18 | n2466); + assign n2468 = n2442 | Ni40; + assign n2469 = n2444 & n2430 & n2425 & n2468; + assign n2470 = n2469 & (n2433 | n2434); + assign n2471 = n2419 & (~n804 | ~n2470); + assign n2472 = n2419 & (n2420 | ~n2470); + assign n2473 = n784 & n2472; + assign n2474 = n2438 & (n18 | n2473); + assign n2475 = n2425 & n2433 & n2430; + assign n2476 = n2425 & n2430 & (Ni36 | n2475); + assign n2477 = n2419 & (~n804 | ~n2476); + assign n2478 = n2419 & (n2420 | ~n2476); + assign n2479 = n784 & n2478; + assign n2480 = n2438 & (n18 | n2479); + assign n2481 = (n2690 | n1702) & (n4405 | n1408); + assign n2482 = n2471 & n2474; + assign n2483 = n2423 & n2481 & (n2482 | n914); + assign n2484 = n2432 & (n2433 | ~n2530); + assign n2485 = n2419 & (~n804 | ~n2484); + assign n2486 = n2419 & (n2420 | ~n2484); + assign n2487 = n784 & n2486; + assign n2488 = n2438 & (n18 | n2487); + assign n2489 = n2445 & (n2433 | ~n2530); + assign n2490 = n2419 & (~n804 | ~n2489); + assign n2491 = n2419 & (n2420 | ~n2489); + assign n2492 = n784 & n2491; + assign n2493 = n2438 & (n18 | n2492); + assign n2494 = n2419 & (~n804 | ~n2452); + assign n2495 = n2419 & (n2420 | ~n2452); + assign n2496 = n784 & n2495; + assign n2497 = n2438 & (n18 | n2496); + assign n2498 = (n2666 | n1702) & (n4414 | n1408); + assign n2499 = n2490 & n2493; + assign n2500 = n2423 & n2498 & (n2499 | n914); + assign n2501 = n2462 & (n2433 | ~n2530); + assign n2502 = n2419 & (~n804 | ~n2501); + assign n2503 = n2419 & (n2420 | ~n2501); + assign n2504 = n784 & n2503; + assign n2505 = n2438 & (n18 | n2504); + assign n2506 = n2469 & (n2433 | ~n2530); + assign n2507 = n2419 & (~n804 | ~n2506); + assign n2508 = n2419 & (n2420 | ~n2506); + assign n2509 = n784 & n2508; + assign n2510 = n2438 & (n18 | n2509); + assign n2511 = n2419 & (~n804 | ~n2475); + assign n2512 = n2419 & (n2420 | ~n2475); + assign n2513 = n784 & n2512; + assign n2514 = n2438 & (n18 | n2513); + assign n2515 = (n2667 | n1702) & (n4415 | n1408); + assign n2516 = n2507 & n2510; + assign n2517 = n2423 & n2515 & (n2516 | n914); + assign n2518 = n2451 & n2427; + assign n2519 = n2419 & (~n804 | ~n3963); + assign n2520 = n2419 & (n2420 | ~n3963); + assign n2521 = n784 & n2520; + assign n2522 = n2438 & (n18 | n2521); + assign n2523 = n2451 & n2442; + assign n2524 = n2419 & (~n804 | ~n3964); + assign n2525 = n2419 & (n2420 | ~n3964); + assign n2526 = n784 & n2525; + assign n2527 = n2438 & (n18 | n2526); + assign n2528 = n2518 | ~Ni40; + assign n2529 = n2431 & n2430 & n2428 & n2528; + assign n2530 = Ni35 | Ni36; + assign n2531 = n2529 & (n2433 | n2530); + assign n2532 = n2419 & (~n804 | ~n2531); + assign n2533 = n2419 & (n2420 | ~n2531); + assign n2534 = n784 & n2533; + assign n2535 = n2438 & (n18 | n2534); + assign n2536 = n2523 | ~Ni40; + assign n2537 = n2444 & n2430 & n2428 & n2536; + assign n2538 = n2537 & (n2433 | n2530); + assign n2539 = n2419 & (~n804 | ~n2538); + assign n2540 = n2419 & (n2420 | ~n2538); + assign n2541 = n784 & n2540; + assign n2542 = n2438 & (n18 | n2541); + assign n2543 = (n4408 | n3893) & (n2718 | n2109); + assign n2544 = n2423 & (n2721 | n914); + assign n2545 = n2519 & n2522; + assign n2546 = n2543 & n2544 & (n2545 | n1408); + assign n2547 = n2419 & (~n804 | ~n3965); + assign n2548 = n2419 & (n2420 | ~n3965); + assign n2549 = n784 & n2548; + assign n2550 = n2438 & (n18 | n2549); + assign n2551 = n2419 & (~n804 | ~n3966); + assign n2552 = n2419 & (n2420 | ~n3966); + assign n2553 = n784 & n2552; + assign n2554 = n2438 & (n18 | n2553); + assign n2555 = n2427 | ~Ni40; + assign n2556 = n2431 & n2430 & n2425 & n2555; + assign n2557 = n2556 & (n2433 | n2530); + assign n2558 = n2419 & (~n804 | ~n2557); + assign n2559 = n2419 & (n2420 | ~n2557); + assign n2560 = n784 & n2559; + assign n2561 = n2438 & (n18 | n2560); + assign n2562 = n2442 | ~Ni40; + assign n2563 = n2444 & n2430 & n2425 & n2562; + assign n2564 = n2563 & (n2433 | n2530); + assign n2565 = n2419 & (~n804 | ~n2564); + assign n2566 = n2419 & (n2420 | ~n2564); + assign n2567 = n784 & n2566; + assign n2568 = n2438 & (n18 | n2567); + assign n2569 = (n4411 | n3893) & (n2706 | n2109); + assign n2570 = n2423 & (n2710 | n914); + assign n2571 = n2547 & n2550; + assign n2572 = n2569 & n2570 & (n2571 | n1408); + assign n2573 = ~n3963 | ~n4768; + assign n2574 = n2419 & (~n804 | n2573); + assign n2575 = n2419 & (n2420 | n2573); + assign n2576 = n784 & n2575; + assign n2577 = n2438 & (n18 | n2576); + assign n2578 = ~n3964 | ~n4768; + assign n2579 = n2419 & (~n804 | n2578); + assign n2580 = n2419 & (n2420 | n2578); + assign n2581 = n784 & n2580; + assign n2582 = n2438 & (n18 | n2581); + assign n2583 = n2529 & (n2433 | ~n2434); + assign n2584 = n2419 & (~n804 | ~n2583); + assign n2585 = n2419 & (n2420 | ~n2583); + assign n2586 = n784 & n2585; + assign n2587 = n2438 & (n18 | n2586); + assign n2588 = n2537 & (n2433 | ~n2434); + assign n2589 = n2419 & (~n804 | ~n2588); + assign n2590 = n2419 & (n2420 | ~n2588); + assign n2591 = n784 & n2590; + assign n2592 = n2438 & (n18 | n2591); + assign n2593 = (n4418 | n3893) & (n2740 | n2109); + assign n2594 = n2423 & (n2743 | n914); + assign n2595 = n2574 & n2577; + assign n2596 = n2593 & n2594 & (n2595 | n1408); + assign n2597 = ~n3965 | ~n4768; + assign n2598 = n2419 & (~n804 | n2597); + assign n2599 = n2419 & (n2420 | n2597); + assign n2600 = n784 & n2599; + assign n2601 = n2438 & (n18 | n2600); + assign n2602 = ~n3966 | ~n4768; + assign n2603 = n2419 & (~n804 | n2602); + assign n2604 = n2419 & (n2420 | n2602); + assign n2605 = n784 & n2604; + assign n2606 = n2438 & (n18 | n2605); + assign n2607 = n2556 & (n2433 | ~n2434); + assign n2608 = n2419 & (~n804 | ~n2607); + assign n2609 = n2419 & (n2420 | ~n2607); + assign n2610 = n784 & n2609; + assign n2611 = n2438 & (n18 | n2610); + assign n2612 = n2563 & (n2433 | ~n2434); + assign n2613 = n2419 & (~n804 | ~n2612); + assign n2614 = n2419 & (n2420 | ~n2612); + assign n2615 = n784 & n2614; + assign n2616 = n2438 & (n18 | n2615); + assign n2617 = (n4421 | n3893) & (n2729 | n2109); + assign n2618 = n2423 & (n2732 | n914); + assign n2619 = n2598 & n2601; + assign n2620 = n2617 & n2618 & (n2619 | n1408); + assign n2621 = n2641 & n2423; + assign n2622 = (n1448 | n2621) & (n1446 | ~n3998); + assign n2623 = n802 & (~Pi27 | ~Ni32) & n2419; + assign n2624 = n4709 & (Pi22 | ~Pi21 | n3821); + assign n2625 = (~Pi26 | n3037) & n3817; + assign n2626 = n2624 & (n2625 | n2254); + assign n2627 = n802 & n2419 & (Pi27 | ~Ni32); + assign n2628 = (n2627 & (~Pi21 | ~n3999)) | (Pi21 & ~n3999); + assign n2629 = n3813 & (Pi27 | n3037); + assign n2630 = n2628 & (n2629 | n2254); + assign n2631 = (n2621 | n1452) & (n2630 | n3696); + assign n2632 = ~Ni12 | n3912; + assign n2633 = n2622 & n2631 & (n2626 | n2632); + assign n2634 = ~n4711 & (Pi22 | ~Pi21 | n3826); + assign n2635 = n3817 & (Pi26 | n3037); + assign n2636 = n2634 & (n2635 | n2254); + assign n2637 = Pi21 & ~n2422 & (~Pi24 | ~n813); + assign n2638 = Pi21 | n3822; + assign n2639 = ~n2637 & (Pi24 | n2421) & n2638; + assign n2640 = n3825 | n2254; + assign n2641 = n3037 | n2254; + assign n2642 = n2640 & n2639 & (Pi24 | n2641); + assign n2643 = Pi22 | ~Pi21; + assign n2644 = n2640 & n2638 & (n813 | n2643); + assign n2645 = n3823 | n2643; + assign n2646 = n2649 & (~Pi27 | n3822); + assign n2647 = n3824 & (~Pi27 | n3825); + assign n2648 = n2645 & n2646 & (n2647 | n2254); + assign n2649 = n2419 & n801; + assign n2650 = (n2750 | ~n4005) & (n3912 | ~n4006); + assign n2651 = n2650 & (n2642 | ~Ni13); + assign n2652 = n812 & n2494 & (n18 | n2495); + assign n2653 = n812 & n2511 & (n18 | n2512); + assign n2654 = n812 & n2584 & (n18 | n2585); + assign n2655 = n812 & n2589 & (n18 | n2590); + assign n2656 = n812 & n2574 & (n18 | n2575); + assign n2657 = n812 & n2579 & (n18 | n2580); + assign n2658 = n812 & n2485 & (n18 | n2486); + assign n2659 = n812 & n2490 & (n18 | n2491); + assign n2660 = n812 & n2608 & (n18 | n2609); + assign n2661 = n812 & n2613 & (n18 | n2614); + assign n2662 = n812 & n2598 & (n18 | n2599); + assign n2663 = n812 & n2603 & (n18 | n2604); + assign n2664 = n812 & n2502 & (n18 | n2503); + assign n2665 = n812 & n2507 & (n18 | n2508); + assign n2666 = n2494 & n2497; + assign n2667 = n2511 & n2514; + assign n2668 = (n2666 | n1495) & (n2667 | n1497); + assign n2669 = ~n3740 & (~n4553 | ~n4554); + assign n2670 = ~n2272 & (~n4555 | ~n4556); + assign n2671 = n2639 & (n3737 | (n4562 & n4561)); + assign n2672 = n4565 & (n3743 | (n4560 & n4559)); + assign n2673 = n4563 & n4564 & (Pi24 | n2668); + assign n2674 = n2673 & n2671 & n2672; + assign n2675 = n812 & n2454 & (n18 | n2455); + assign n2676 = n812 & n2477 & (n18 | n2478); + assign n2677 = n812 & n2532 & (n18 | n2533); + assign n2678 = n812 & n2539 & (n18 | n2540); + assign n2679 = n812 & n2519 & (n18 | n2520); + assign n2680 = n812 & n2524 & (n18 | n2525); + assign n2681 = n812 & n2436 & (n18 | n2437); + assign n2682 = n812 & n2447 & (n18 | n2448); + assign n2683 = n812 & n2558 & (n18 | n2559); + assign n2684 = n812 & n2565 & (n18 | n2566); + assign n2685 = n812 & n2547 & (n18 | n2548); + assign n2686 = n812 & n2551 & (n18 | n2552); + assign n2687 = n812 & n2464 & (n18 | n2465); + assign n2688 = n812 & n2471 & (n18 | n2472); + assign n2689 = n2454 & n2457; + assign n2690 = n2477 & n2480; + assign n2691 = (n2689 | n1495) & (n2690 | n1497); + assign n2692 = ~n3740 & (~n4535 | ~n4536); + assign n2693 = ~n2272 & (~n4537 | ~n4538); + assign n2694 = ~n3944 & (~n4547 | ~n4549 | ~n4550); + assign n2695 = ~n2694 & (n2642 | (n1448 & n1542)); + assign n2696 = (n2651 | n3919) & (n3677 | ~n4007); + assign n2697 = n2695 & n2696 & (n2674 | n2367); + assign n2698 = Pi21 & ~n2422 & (n788 | ~n813); + assign n2699 = n2638 & (~n788 | n2421) & ~n2698; + assign n2700 = n2640 & n2699 & (~n788 | n2641); + assign n2701 = ~n2643 & (~n4508 | (Pi24 & ~n3821)); + assign n2702 = ~n2254 & (~n4509 | (Pi24 & ~n2625)); + assign n2703 = ~Pi21 & (~n4510 | (Pi24 & ~n3818)); + assign n2704 = n1542 & (n1543 | ~n2750); + assign n2705 = n4523 & (n4411 | n3936); + assign n2706 = n2565 & n2568; + assign n2707 = ~n788 | n3859; + assign n2708 = n2699 & n2705 & (n2706 | n2707); + assign n2709 = n4522 & (n2571 | n3936); + assign n2710 = n2551 & n2554; + assign n2711 = n2699 & n2709 & (n2710 | n2707); + assign n2712 = n4521 & (n4405 | n3936); + assign n2713 = n2699 & n2712 & (n2482 | n2707); + assign n2714 = (n2713 | n3864) & (n2711 | n3867); + assign n2715 = n4524 & (n2690 | n3934); + assign n2716 = n2714 & n2715 & (n2708 | n1322); + assign n2717 = n4514 & (n4408 | n3936); + assign n2718 = n2539 & n2542; + assign n2719 = n2699 & n2717 & (n2718 | n2707); + assign n2720 = n4513 & (n2545 | n3936); + assign n2721 = n2524 & n2527; + assign n2722 = n2699 & n2720 & (n2721 | n2707); + assign n2723 = n4512 & (n4404 | n3936); + assign n2724 = n2699 & n2723 & (n2459 | n2707); + assign n2725 = (n2724 | n3864) & (n2722 | n3867); + assign n2726 = n4516 & (n2689 | n3934); + assign n2727 = n2725 & n2726 & (n2719 | n1322); + assign n2728 = n4527 & (n4421 | n3936); + assign n2729 = n2613 & n2616; + assign n2730 = n2699 & n2728 & (n2729 | n2707); + assign n2731 = n4526 & (n2619 | n3936); + assign n2732 = n2603 & n2606; + assign n2733 = n2699 & n2731 & (n2732 | n2707); + assign n2734 = n4525 & (n4415 | n3936); + assign n2735 = n2699 & n2734 & (n2516 | n2707); + assign n2736 = (n2735 | n3864) & (n2733 | n3867); + assign n2737 = n4528 & n4515 & (n2667 | n3934); + assign n2738 = n2736 & n2737 & (n2730 | n1322); + assign n2739 = n4519 & (n4418 | n3936); + assign n2740 = n2589 & n2592; + assign n2741 = n2699 & n2739 & (n2740 | n2707); + assign n2742 = n4518 & (n2595 | n3936); + assign n2743 = n2579 & n2582; + assign n2744 = n2699 & n2742 & (n2743 | n2707); + assign n2745 = n4517 & (n4414 | n3936); + assign n2746 = n2699 & n2745 & (n2499 | n2707); + assign n2747 = (n2746 | n3864) & (n2744 | n3867); + assign n2748 = n4520 & (n2666 | n3934); + assign n2749 = n2747 & n2748 & (n2741 | n1322); + assign n2750 = ~Ni14 | Ni13; + assign n2751 = n1545 & ~n2700 & (~n2636 | n2750); + assign n2752 = ~n3919 & (~n4511 | (~n2700 & Ni13)); + assign n2753 = Pi21 & ~n2422 & (n795 | ~n813); + assign n2754 = n2638 & (~n795 | n2421) & ~n2753; + assign n2755 = n2640 & n2754 & (~n795 | n2641); + assign n2756 = n4578 & (n4411 | n3948); + assign n2757 = ~n795 | n3859; + assign n2758 = n2754 & n2756 & (n2706 | n2757); + assign n2759 = n4577 & (n2571 | n3948); + assign n2760 = n2754 & n2759 & (n2710 | n2757); + assign n2761 = n4576 & (n4405 | n3948); + assign n2762 = n2754 & n2761 & (n2482 | n2757); + assign n2763 = (n2762 | n3864) & (n2760 | n3867); + assign n2764 = n4579 & (n2690 | n3946); + assign n2765 = n2763 & n2764 & (n2758 | n1322); + assign n2766 = n4569 & (n4408 | n3948); + assign n2767 = n2754 & n2766 & (n2718 | n2757); + assign n2768 = n4568 & (n2545 | n3948); + assign n2769 = n2754 & n2768 & (n2721 | n2757); + assign n2770 = n4567 & (n4404 | n3948); + assign n2771 = n2754 & n2770 & (n2459 | n2757); + assign n2772 = (n2771 | n3864) & (n2769 | n3867); + assign n2773 = n4571 & (n2689 | n3946); + assign n2774 = n2772 & n2773 & (n2767 | n1322); + assign n2775 = n4582 & (n4421 | n3948); + assign n2776 = n2754 & n2775 & (n2729 | n2757); + assign n2777 = n4581 & (n2619 | n3948); + assign n2778 = n2754 & n2777 & (n2732 | n2757); + assign n2779 = n4580 & (n4415 | n3948); + assign n2780 = n2754 & n2779 & (n2516 | n2757); + assign n2781 = (n2780 | n3864) & (n2778 | n3867); + assign n2782 = n4583 & n4570 & (n2667 | n3946); + assign n2783 = n2781 & n2782 & (n2776 | n1322); + assign n2784 = n4574 & (n4418 | n3948); + assign n2785 = n2754 & n2784 & (n2740 | n2757); + assign n2786 = n4573 & (n2595 | n3948); + assign n2787 = n2754 & n2786 & (n2743 | n2757); + assign n2788 = n4572 & (n4414 | n3948); + assign n2789 = n2754 & n2788 & (n2499 | n2757); + assign n2790 = (n2789 | n3864) & (n2787 | n3867); + assign n2791 = n4575 & (n2666 | n3946); + assign n2792 = n2790 & n2791 & (n2785 | n1322); + assign n2793 = n1545 & ~n2755 & (~n2636 | n2750); + assign n2794 = ~n3919 & ((Ni13 & ~n2755) | ~n4566); + assign n2795 = n2419 & (~n805 | ~n2435); + assign n2796 = n2419 & (~n805 | ~n2446); + assign n2797 = n2419 & (~n805 | ~n2453); + assign n2798 = (n4398 | n1702) & (n2918 | n1408); + assign n2799 = n2796 & n2450; + assign n2800 = n2423 & n2798 & (n2799 | n914); + assign n2801 = n2419 & (~n805 | ~n2463); + assign n2802 = n2419 & (~n805 | ~n2470); + assign n2803 = n2419 & (~n805 | ~n2476); + assign n2804 = (n4400 | n1702) & (n2890 | n1408); + assign n2805 = n2802 & n2474; + assign n2806 = n2423 & n2804 & (n2805 | n914); + assign n2807 = n2419 & (~n805 | ~n2484); + assign n2808 = n2419 & (~n805 | ~n2489); + assign n2809 = n2419 & (~n805 | ~n2452); + assign n2810 = (n4399 | n1702) & (n2974 | n1408); + assign n2811 = n2808 & n2493; + assign n2812 = n2423 & n2810 & (n2811 | n914); + assign n2813 = n2419 & (~n805 | ~n2501); + assign n2814 = n2419 & (~n805 | ~n2506); + assign n2815 = n2419 & (~n805 | ~n2475); + assign n2816 = (n4401 | n1702) & (n2946 | n1408); + assign n2817 = n2814 & n2510; + assign n2818 = n2423 & n2816 & (n2817 | n914); + assign n2819 = n2419 & (~n805 | ~n3963); + assign n2820 = n2419 & (~n805 | ~n3964); + assign n2821 = n2419 & (~n805 | ~n2531); + assign n2822 = n2419 & (~n805 | ~n2538); + assign n2823 = (n2903 | n3893) & (n4388 | n2109); + assign n2824 = n2423 & (n4389 | n914); + assign n2825 = n2819 & n2522; + assign n2826 = n2823 & n2824 & (n2825 | n1408); + assign n2827 = n2419 & (~n805 | ~n3965); + assign n2828 = n2419 & (~n805 | ~n3966); + assign n2829 = n2419 & (~n805 | ~n2557); + assign n2830 = n2419 & (~n805 | ~n2564); + assign n2831 = (n2875 | n3893) & (n4392 | n2109); + assign n2832 = n2423 & (n4393 | n914); + assign n2833 = n2827 & n2550; + assign n2834 = n2831 & n2832 & (n2833 | n1408); + assign n2835 = n2419 & (~n805 | n2573); + assign n2836 = n2419 & (~n805 | n2578); + assign n2837 = n2419 & (~n805 | ~n2583); + assign n2838 = n2419 & (~n805 | ~n2588); + assign n2839 = (n2959 | n3893) & (n4390 | n2109); + assign n2840 = n2423 & (n4391 | n914); + assign n2841 = n2835 & n2577; + assign n2842 = n2839 & n2840 & (n2841 | n1408); + assign n2843 = n2419 & (~n805 | n2597); + assign n2844 = n2419 & (~n805 | n2602); + assign n2845 = n2419 & (~n805 | ~n2607); + assign n2846 = n2419 & (~n805 | ~n2612); + assign n2847 = (n2931 | n3893) & (n4394 | n2109); + assign n2848 = n2423 & (n4395 | n914); + assign n2849 = n2843 & n2601; + assign n2850 = n2847 & n2848 & (n2849 | n1408); + assign n2851 = (Pi20 & n2449) | (n2439 & (~Pi20 | n2449)); + assign n2852 = (n2851 | n1701) & (n2456 | n1702); + assign n2853 = (Pi20 & n2473) | (n2466 & (~Pi20 | n2473)); + assign n2854 = (n2853 | n1701) & (n2479 | n1702); + assign n2855 = (Pi20 & n2509) | (n2504 & (~Pi20 | n2509)); + assign n2856 = (n2855 | n1701) & (n2513 | n1702); + assign n2857 = (Pi20 & n2526) | (n2521 & (~Pi20 | n2526)); + assign n2858 = (Pi20 & n2541) | (n2534 & (~Pi20 | n2541)); + assign n2859 = (n2857 | n1701) & (n2858 | n1702); + assign n2860 = (Pi20 & n2553) | (n2549 & (~Pi20 | n2553)); + assign n2861 = (Pi20 & n2567) | (n2560 & (~Pi20 | n2567)); + assign n2862 = (n2860 | n1701) & (n2861 | n1702); + assign n2863 = (Pi20 & n2605) | (n2600 & (~Pi20 | n2605)); + assign n2864 = (Pi20 & n2615) | (n2610 & (~Pi20 | n2615)); + assign n2865 = (n2863 | n1701) & (n2864 | n1702); + assign n2866 = n1446 | n4721 | n4722; + assign n2867 = ~n4720 & (Pi17 | (n4396 & n4397)); + assign n2868 = n2866 & (n2867 | n1448); + assign n2869 = n802 & n2559; + assign n2870 = n802 & n2829 & (n18 | n2869); + assign n2871 = n802 & n2566; + assign n2872 = n802 & n2830 & (n18 | n2871); + assign n2873 = (n2870 | n3915) & (n2872 | n3916); + assign n2874 = n2624 & (n4392 | n3917); + assign n2875 = n2829 & n2561; + assign n2876 = n2873 & n2874 & (n2875 | n1729); + assign n2877 = n802 & n2548; + assign n2878 = n802 & n2827 & (n18 | n2877); + assign n2879 = n802 & n2552; + assign n2880 = n802 & n2828 & (n18 | n2879); + assign n2881 = (n2878 | n3915) & (n2880 | n3916); + assign n2882 = n2624 & (n4393 | n3917); + assign n2883 = n2881 & n2882 & (n2833 | n1729); + assign n2884 = n802 & n2465; + assign n2885 = n802 & n2801 & (n18 | n2884); + assign n2886 = n802 & n2472; + assign n2887 = n802 & n2802 & (n18 | n2886); + assign n2888 = (n2885 | n3915) & (n2887 | n3916); + assign n2889 = n2624 & (n2805 | n3917); + assign n2890 = n2801 & n2467; + assign n2891 = n2888 & n2889 & (n2890 | n1729); + assign n2892 = n802 & n2478; + assign n2893 = n802 & n2803 & (n18 | n2892); + assign n2894 = (n2891 | n3864) & (n2883 | n3867); + assign n2895 = n4503 & n4501 & (n4400 | n3914); + assign n2896 = n2894 & n2895 & (n2876 | n1322); + assign n2897 = n802 & n2533; + assign n2898 = n802 & n2821 & (n18 | n2897); + assign n2899 = n802 & n2540; + assign n2900 = n802 & n2822 & (n18 | n2899); + assign n2901 = (n2898 | n3915) & (n2900 | n3916); + assign n2902 = n2624 & (n4388 | n3917); + assign n2903 = n2821 & n2535; + assign n2904 = n2901 & n2902 & (n2903 | n1729); + assign n2905 = n802 & n2520; + assign n2906 = n802 & n2819 & (n18 | n2905); + assign n2907 = n802 & n2525; + assign n2908 = n802 & n2820 & (n18 | n2907); + assign n2909 = (n2906 | n3915) & (n2908 | n3916); + assign n2910 = n2624 & (n4389 | n3917); + assign n2911 = n2909 & n2910 & (n2825 | n1729); + assign n2912 = n802 & n2437; + assign n2913 = n802 & n2795 & (n18 | n2912); + assign n2914 = n802 & n2448; + assign n2915 = n802 & n2796 & (n18 | n2914); + assign n2916 = (n2913 | n3915) & (n2915 | n3916); + assign n2917 = n2624 & (n2799 | n3917); + assign n2918 = n2795 & n2440; + assign n2919 = n2916 & n2917 & (n2918 | n1729); + assign n2920 = n802 & n2455; + assign n2921 = n802 & n2797 & (n18 | n2920); + assign n2922 = (n2919 | n3864) & (n2911 | n3867); + assign n2923 = n4500 & n4501 & (n4398 | n3914); + assign n2924 = n2922 & n2923 & (n2904 | n1322); + assign n2925 = n802 & n2609; + assign n2926 = n802 & n2845 & (n18 | n2925); + assign n2927 = n802 & n2614; + assign n2928 = n802 & n2846 & (n18 | n2927); + assign n2929 = (n2926 | n3915) & (n2928 | n3916); + assign n2930 = n2624 & (n4394 | n3917); + assign n2931 = n2845 & n2611; + assign n2932 = n2929 & n2930 & (n2931 | n1729); + assign n2933 = n802 & n2599; + assign n2934 = n802 & n2843 & (n18 | n2933); + assign n2935 = n802 & n2604; + assign n2936 = n802 & n2844 & (n18 | n2935); + assign n2937 = (n2934 | n3915) & (n2936 | n3916); + assign n2938 = n2624 & (n4395 | n3917); + assign n2939 = n2937 & n2938 & (n2849 | n1729); + assign n2940 = n802 & n2503; + assign n2941 = n802 & n2813 & (n18 | n2940); + assign n2942 = n802 & n2508; + assign n2943 = n802 & n2814 & (n18 | n2942); + assign n2944 = (n2941 | n3915) & (n2943 | n3916); + assign n2945 = n2624 & (n2817 | n3917); + assign n2946 = n2813 & n2505; + assign n2947 = n2944 & n2945 & (n2946 | n1729); + assign n2948 = n802 & n2512; + assign n2949 = n802 & n2815 & (n18 | n2948); + assign n2950 = (n2947 | n3864) & (n2939 | n3867); + assign n2951 = n4504 & n4501 & (n4401 | n3914); + assign n2952 = n2950 & n2951 & (n2932 | n1322); + assign n2953 = n802 & n2585; + assign n2954 = n802 & n2837 & (n18 | n2953); + assign n2955 = n802 & n2590; + assign n2956 = n802 & n2838 & (n18 | n2955); + assign n2957 = (n2954 | n3915) & (n2956 | n3916); + assign n2958 = n2624 & (n4390 | n3917); + assign n2959 = n2837 & n2587; + assign n2960 = n2957 & n2958 & (n2959 | n1729); + assign n2961 = n802 & n2575; + assign n2962 = n802 & n2835 & (n18 | n2961); + assign n2963 = n802 & n2580; + assign n2964 = n802 & n2836 & (n18 | n2963); + assign n2965 = (n2962 | n3915) & (n2964 | n3916); + assign n2966 = n2624 & (n4391 | n3917); + assign n2967 = n2965 & n2966 & (n2841 | n1729); + assign n2968 = n802 & n2486; + assign n2969 = n802 & n2807 & (n18 | n2968); + assign n2970 = n802 & n2491; + assign n2971 = n802 & n2808 & (n18 | n2970); + assign n2972 = (n2969 | n3915) & (n2971 | n3916); + assign n2973 = n2624 & (n2811 | n3917); + assign n2974 = n2807 & n2488; + assign n2975 = n2972 & n2973 & (n2974 | n1729); + assign n2976 = n802 & n2495; + assign n2977 = n802 & n2809 & (n18 | n2976); + assign n2978 = (n2975 | n3864) & (n2967 | n3867); + assign n2979 = n4502 & n4501 & (n4399 | n3914); + assign n2980 = n2978 & n2979 & (n2960 | n1322); + assign n2981 = ~n2272 & (~n4485 | ~n4486); + assign n2982 = ~n2272 & (~n4466 | ~n4467); + assign n2983 = n3696 | n4717 | n4719; + assign n2984 = n2868 & (n2632 | (n4506 & n4505)); + assign n2985 = n2983 & n2984 & (n2867 | n1452); + assign n2986 = (n2870 | n3901) & (n2872 | n3902); + assign n2987 = n2634 & (n4392 | n3903); + assign n2988 = n2986 & n2987 & (n2875 | n1868); + assign n2989 = (n2878 | n3901) & (n2880 | n3902); + assign n2990 = n2634 & (n4393 | n3903); + assign n2991 = n2989 & n2990 & (n2833 | n1868); + assign n2992 = (n2885 | n3901) & (n2887 | n3902); + assign n2993 = n2634 & (n2805 | n3903); + assign n2994 = n2992 & n2993 & (n2890 | n1868); + assign n2995 = (n2994 | n3864) & (n2991 | n3867); + assign n2996 = n4460 & n4458 & (n4400 | n3900); + assign n2997 = n2995 & n2996 & (n2988 | n1322); + assign n2998 = (n2898 | n3901) & (n2900 | n3902); + assign n2999 = n2634 & (n4388 | n3903); + assign n3000 = n2998 & n2999 & (n2903 | n1868); + assign n3001 = (n2906 | n3901) & (n2908 | n3902); + assign n3002 = n2634 & (n4389 | n3903); + assign n3003 = n3001 & n3002 & (n2825 | n1868); + assign n3004 = (n2913 | n3901) & (n2915 | n3902); + assign n3005 = n2634 & (n2799 | n3903); + assign n3006 = n3004 & n3005 & (n2918 | n1868); + assign n3007 = (n3006 | n3864) & (n3003 | n3867); + assign n3008 = n4457 & n4458 & (n4398 | n3900); + assign n3009 = n3007 & n3008 & (n3000 | n1322); + assign n3010 = (n2926 | n3901) & (n2928 | n3902); + assign n3011 = n2634 & (n4394 | n3903); + assign n3012 = n3010 & n3011 & (n2931 | n1868); + assign n3013 = (n2934 | n3901) & (n2936 | n3902); + assign n3014 = n2634 & (n4395 | n3903); + assign n3015 = n3013 & n3014 & (n2849 | n1868); + assign n3016 = (n2941 | n3901) & (n2943 | n3902); + assign n3017 = n2634 & (n2817 | n3903); + assign n3018 = n3016 & n3017 & (n2946 | n1868); + assign n3019 = (n3018 | n3864) & (n3015 | n3867); + assign n3020 = n4461 & n4458 & (n4401 | n3900); + assign n3021 = n3019 & n3020 & (n3012 | n1322); + assign n3022 = (n2954 | n3901) & (n2956 | n3902); + assign n3023 = n2634 & (n4390 | n3903); + assign n3024 = n3022 & n3023 & (n2959 | n1868); + assign n3025 = (n2962 | n3901) & (n2964 | n3902); + assign n3026 = n2634 & (n4391 | n3903); + assign n3027 = n3025 & n3026 & (n2841 | n1868); + assign n3028 = (n2969 | n3901) & (n2971 | n3902); + assign n3029 = n2634 & (n2811 | n3903); + assign n3030 = n3028 & n3029 & (n2974 | n1868); + assign n3031 = (n3030 | n3864) & (n3027 | n3867); + assign n3032 = n4459 & n4458 & (n4399 | n3900); + assign n3033 = n3031 & n3032 & (n3024 | n1322); + assign n3034 = (n2997 | n3884) & (n3021 | n3891); + assign n3035 = (n3009 | n3870) & (n3033 | n3877); + assign n3036 = n3034 & n3035; + assign n3037 = n784 & n2424; + assign n3038 = n2423 & (n3037 | n1919); + assign n3039 = n3038 & (n1929 | (n4387 & n4385)); + assign n3040 = n2496 & (~Pi16 | n2513); + assign n3041 = n3039 & (n3040 | n1923); + assign n3042 = n3038 & (n1929 | (n4383 & n4381)); + assign n3043 = n2456 & (~Pi16 | n2479); + assign n3044 = n3042 & (n3043 | n1923); + assign n3045 = (n4414 | n3858) & (n2499 | n3860); + assign n3046 = (Pi20 & n2492) | (n2487 & (~Pi20 | n2492)); + assign n3047 = n3045 & (n3046 | n1929); + assign n3048 = ~n3740 & ((~n1929 & ~n2855) | ~n4416); + assign n3049 = ~n2272 & (~n4417 | (~n1929 & ~n3094)); + assign n3050 = ~n3895 & ((~n1929 & ~n3091) | ~n4419); + assign n3051 = ~n3743 & ((~n1929 & ~n2863) | ~n4420); + assign n3052 = ~n3737 & ((~n1929 & ~n2864) | ~n4422); + assign n3053 = (n4404 | n3858) & (n2459 | n3860); + assign n3054 = n3053 & (n2851 | n1929); + assign n3055 = ~n3740 & ((~n1929 & ~n2853) | ~n4406); + assign n3056 = ~n2272 & (~n4407 | (~n1929 & ~n2857)); + assign n3057 = ~n3895 & ((~n1929 & ~n2858) | ~n4409); + assign n3058 = ~n3743 & ((~n1929 & ~n2860) | ~n4410); + assign n3059 = ~n3737 & ((~n1929 & ~n2861) | ~n4412); + assign n3060 = (~Pi15 & n3044) | (n3041 & (Pi15 | n3044)); + assign n3061 = (n1448 | n3060) & (n1446 | ~n3997); + assign n3062 = n2634 & (n2635 | n1919); + assign n3063 = (n2869 | n3931) & (n2871 | n3932); + assign n3064 = n3062 & n3063 & (n2861 | n1948); + assign n3065 = (n2877 | n3931) & (n2879 | n3932); + assign n3066 = n3062 & n3065 & (n2860 | n1948); + assign n3067 = (n2884 | n3931) & (n2886 | n3932); + assign n3068 = n3062 & n3067 & (n2853 | n1948); + assign n3069 = (n3068 | n3864) & (n3066 | n3867); + assign n3070 = n4453 & n4451 & (n2479 | n3930); + assign n3071 = n3069 & n3070 & (n3064 | n1322); + assign n3072 = (n2897 | n3931) & (n2899 | n3932); + assign n3073 = n3062 & n3072 & (n2858 | n1948); + assign n3074 = (n2905 | n3931) & (n2907 | n3932); + assign n3075 = n3062 & n3074 & (n2857 | n1948); + assign n3076 = (n2912 | n3931) & (n2914 | n3932); + assign n3077 = n3062 & n3076 & (n2851 | n1948); + assign n3078 = (n3077 | n3864) & (n3075 | n3867); + assign n3079 = n4450 & n4451 & (n2456 | n3930); + assign n3080 = n3078 & n3079 & (n3073 | n1322); + assign n3081 = (n2925 | n3931) & (n2927 | n3932); + assign n3082 = n3062 & n3081 & (n2864 | n1948); + assign n3083 = (n2933 | n3931) & (n2935 | n3932); + assign n3084 = n3062 & n3083 & (n2863 | n1948); + assign n3085 = (n2940 | n3931) & (n2942 | n3932); + assign n3086 = n3062 & n3085 & (n2855 | n1948); + assign n3087 = (n3086 | n3864) & (n3084 | n3867); + assign n3088 = n4454 & n4451 & (n2513 | n3930); + assign n3089 = n3087 & n3088 & (n3082 | n1322); + assign n3090 = (n2953 | n3931) & (n2955 | n3932); + assign n3091 = (Pi20 & n2591) | (n2586 & (~Pi20 | n2591)); + assign n3092 = n3062 & n3090 & (n3091 | n1948); + assign n3093 = (n2961 | n3931) & (n2963 | n3932); + assign n3094 = (Pi20 & n2581) | (n2576 & (~Pi20 | n2581)); + assign n3095 = n3062 & n3093 & (n3094 | n1948); + assign n3096 = (n2968 | n3931) & (n2970 | n3932); + assign n3097 = n3062 & n3096 & (n3046 | n1948); + assign n3098 = (n3097 | n3864) & (n3095 | n3867); + assign n3099 = n4452 & n4451 & (n2496 | n3930); + assign n3100 = n3098 & n3099 & (n3092 | n1322); + assign n3101 = n2628 & (n2629 | n1919); + assign n3102 = (n2861 | n3922) & (n2869 | n3923); + assign n3103 = n3101 & n3102 & (n2871 | n1989); + assign n3104 = (n2860 | n3922) & (n2877 | n3923); + assign n3105 = n3101 & n3104 & (n2879 | n1989); + assign n3106 = (n2853 | n3922) & (n2884 | n3923); + assign n3107 = n3101 & n3106 & (n2886 | n1989); + assign n3108 = (n3107 | n3864) & (n3105 | n3867); + assign n3109 = n4446 & n4444 & (n2892 | n3921); + assign n3110 = n3108 & n3109 & (n3103 | n1322); + assign n3111 = (n2858 | n3922) & (n2897 | n3923); + assign n3112 = n3101 & n3111 & (n2899 | n1989); + assign n3113 = (n2857 | n3922) & (n2905 | n3923); + assign n3114 = n3101 & n3113 & (n2907 | n1989); + assign n3115 = (n2851 | n3922) & (n2912 | n3923); + assign n3116 = n3101 & n3115 & (n2914 | n1989); + assign n3117 = (n3116 | n3864) & (n3114 | n3867); + assign n3118 = n4443 & n4444 & (n2920 | n3921); + assign n3119 = n3117 & n3118 & (n3112 | n1322); + assign n3120 = (n2864 | n3922) & (n2925 | n3923); + assign n3121 = n3101 & n3120 & (n2927 | n1989); + assign n3122 = (n2863 | n3922) & (n2933 | n3923); + assign n3123 = n3101 & n3122 & (n2935 | n1989); + assign n3124 = (n2855 | n3922) & (n2940 | n3923); + assign n3125 = n3101 & n3124 & (n2942 | n1989); + assign n3126 = (n3125 | n3864) & (n3123 | n3867); + assign n3127 = n4447 & n4444 & (n2948 | n3921); + assign n3128 = n3126 & n3127 & (n3121 | n1322); + assign n3129 = (n3091 | n3922) & (n2953 | n3923); + assign n3130 = n3101 & n3129 & (n2955 | n1989); + assign n3131 = (n3094 | n3922) & (n2961 | n3923); + assign n3132 = n3101 & n3131 & (n2963 | n1989); + assign n3133 = (n3046 | n3922) & (n2968 | n3923); + assign n3134 = n3101 & n3133 & (n2970 | n1989); + assign n3135 = (n3134 | n3864) & (n3132 | n3867); + assign n3136 = n4445 & n4444 & (n2976 | n3921); + assign n3137 = n3135 & n3136 & (n3130 | n1322); + assign n3138 = n2624 & (n2625 | n1919); + assign n3139 = (n2869 | n3926) & (n2871 | n3927); + assign n3140 = n3138 & n3139 & (n2861 | n2028); + assign n3141 = (n2877 | n3926) & (n2879 | n3927); + assign n3142 = n3138 & n3141 & (n2860 | n2028); + assign n3143 = (n2884 | n3926) & (n2886 | n3927); + assign n3144 = n3138 & n3143 & (n2853 | n2028); + assign n3145 = (n3144 | n3864) & (n3142 | n3867); + assign n3146 = n4439 & n4437 & (n2479 | n3925); + assign n3147 = n3145 & n3146 & (n3140 | n1322); + assign n3148 = (n2897 | n3926) & (n2899 | n3927); + assign n3149 = n3138 & n3148 & (n2858 | n2028); + assign n3150 = (n2905 | n3926) & (n2907 | n3927); + assign n3151 = n3138 & n3150 & (n2857 | n2028); + assign n3152 = (n2912 | n3926) & (n2914 | n3927); + assign n3153 = n3138 & n3152 & (n2851 | n2028); + assign n3154 = (n3153 | n3864) & (n3151 | n3867); + assign n3155 = n4436 & n4437 & (n2456 | n3925); + assign n3156 = n3154 & n3155 & (n3149 | n1322); + assign n3157 = (n2925 | n3926) & (n2927 | n3927); + assign n3158 = n3138 & n3157 & (n2864 | n2028); + assign n3159 = (n2933 | n3926) & (n2935 | n3927); + assign n3160 = n3138 & n3159 & (n2863 | n2028); + assign n3161 = (n2940 | n3926) & (n2942 | n3927); + assign n3162 = n3138 & n3161 & (n2855 | n2028); + assign n3163 = (n3162 | n3864) & (n3160 | n3867); + assign n3164 = n4440 & n4437 & (n2513 | n3925); + assign n3165 = n3163 & n3164 & (n3158 | n1322); + assign n3166 = (n2953 | n3926) & (n2955 | n3927); + assign n3167 = n3138 & n3166 & (n3091 | n2028); + assign n3168 = (n2961 | n3926) & (n2963 | n3927); + assign n3169 = n3138 & n3168 & (n3094 | n2028); + assign n3170 = (n2968 | n3926) & (n2970 | n3927); + assign n3171 = n3138 & n3170 & (n3046 | n2028); + assign n3172 = (n3171 | n3864) & (n3169 | n3867); + assign n3173 = n4438 & n4437 & (n2496 | n3925); + assign n3174 = n3172 & n3173 & (n3167 | n1322); + assign n3175 = ~n3677 & (~n4455 | ~n4456); + assign n3176 = ~n3805 & ~n4723 & (Ni10 | ~n4002); + assign n3177 = ~n3937 & (n2751 | n2752 | ~n4532); + assign n3178 = ~n3766 & (n2793 | n2794 | ~n4587); + assign n3179 = ~n1671 & (~n4588 | (~Ni11 & ~n2633)); + assign n3180 = (Ni11 | n2622) & (~n1543 | n2621); + assign n3181 = ~n3180 & (n2072 | (n2073 & n2074)); + assign n3182 = (~n3707 & ~n4010) | (~Ni32 & (n3707 | ~n4010)); + assign n3183 = Ni36 | ~Ni38; + assign n3184 = Pi19 & Pi17; + assign n3185 = ~Ni45 | n3186; + assign n3186 = Ni45 & Ni46; + assign n3187 = ~Ni40 | (Ni30 & n1353); + assign n3188 = (~n2073 | ~n4014) & (~n2072 | n4013); + assign n3189 = ~Ni41 | (Ni30 & n1353); + assign n3190 = (~n2073 | ~n4018) & (~n2072 | n4017); + assign n3191 = ~n3186 & (Ni45 | ~n3661); + assign n3192 = ~Ni47 | ~Ni48; + assign n3193 = ~n3186 & (Ni45 | n3192); + assign n3194 = Ni38 | ~Ni39; + assign n3195 = Ni39 | Ni38; + assign n3196 = (n3191 | n3194) & (n3193 | n3195); + assign n3197 = ~Ni37 | n3196; + assign n3198 = n3193 & (n3203 | ~Ni42); + assign n3199 = n3197 & (~n814 | n3198); + assign n3200 = n3333 & (Ni42 | n3191); + assign n3201 = n3197 & (~n814 | n3200); + assign n3202 = ~n797 & (n1539 | n3193); + assign n3203 = n3193 & (n3191 | n3331); + assign n3204 = n3198 & (Ni41 | n3203); + assign n3205 = n3203 & (n3191 | n923); + assign n3206 = n3198 & (Ni41 | n3205); + assign n3207 = n3200 | n3854; + assign n3208 = n3211 | (n817 & n3968); + assign n3209 = n3208 & n3207 & n3197; + assign n3210 = Ni37 | n3976; + assign n3211 = n3204 & (n3206 | ~Ni40); + assign n3212 = n3210 & (~n783 | n3211); + assign n3213 = n3209 & (~n2530 | n3212); + assign n3214 = ~n2426 & ~n3191 & (n2441 | ~n3193); + assign n3215 = Ni41 | ~Ni42; + assign n3216 = ~n3214 & (n3203 | n3215); + assign n3217 = n3200 | n3855; + assign n3218 = n3220 | (n853 & n3968); + assign n3219 = n3218 & n3217 & n3197; + assign n3220 = n3247 & (n3206 | ~Ni40); + assign n3221 = n3210 & (~n783 | n3220); + assign n3222 = n3219 & (~n2530 | n3221); + assign n3223 = Pi20 | Pi19; + assign n3224 = ~Pi20 | Pi19; + assign n3225 = (n3213 | n3223) & (n3222 | n3224); + assign n3226 = n3197 & n3210 & (n3206 | ~Ni38); + assign n3227 = Pi21 & Pi19; + assign n3228 = Pi22 & ~n3550; + assign n3229 = n3227 & (n810 | (~n3226 & n3228)); + assign n3230 = n3232 | (n817 & n3968); + assign n3231 = n3230 & n3207 & n3197; + assign n3232 = n3276 & (n3205 | ~Ni40); + assign n3233 = n3210 & (~n783 | n3232); + assign n3234 = n3231 & (~n2530 | n3233); + assign n3235 = (~Ni41 | n3205) & n3216; + assign n3236 = n3238 | (n853 & n3968); + assign n3237 = n3236 & n3217 & n3197; + assign n3238 = n3235 & (n3205 | ~Ni40); + assign n3239 = n3210 & (~n783 | n3238); + assign n3240 = n3237 & (~n2530 | n3239); + assign n3241 = (n3234 | n3223) & (n3240 | n3224); + assign n3242 = n3197 & n3210 & (n3205 | ~Ni38); + assign n3243 = n3227 & (n810 | (n3228 & ~n3242)); + assign n3244 = n3247 | (n853 & n3968); + assign n3245 = n3244 & n3217 & n3197; + assign n3246 = n698 | n3976; + assign n3247 = n3198 & n3216; + assign n3248 = n3246 & n3245 & (n1216 | n3247); + assign n3249 = n3247 & (Ni40 | n3206); + assign n3250 = n3210 & (~n783 | n3249); + assign n3251 = n3249 | (n853 & n3968); + assign n3252 = n3251 & n3217 & n3197; + assign n3253 = (~n2434 | n3250) & n3252; + assign n3254 = n3235 | (n853 & n3968); + assign n3255 = n3254 & n3217 & n3197; + assign n3256 = n3246 & n3255 & (n1216 | n3235); + assign n3257 = n3235 & (Ni40 | n3205); + assign n3258 = n3210 & (~n783 | n3257); + assign n3259 = n3257 | (n853 & n3968); + assign n3260 = n3259 & n3217 & n3197; + assign n3261 = (~n2434 | n3258) & n3260; + assign n3262 = ~n799 & ~n3977; + assign n3263 = (n3256 | n3743) & (n3261 | n3737); + assign n3264 = (n3248 | n2272) & (n3253 | n3895); + assign n3265 = n3262 & (~n3288 | (n3263 & n3264)); + assign n3266 = n3204 | (n817 & n3968); + assign n3267 = n3266 & n3207 & n3197; + assign n3268 = n3246 & n3267 & (n1216 | n3204); + assign n3269 = n3204 & (Ni40 | n3206); + assign n3270 = n3210 & (~n783 | n3269); + assign n3271 = n3269 | (n817 & n3968); + assign n3272 = n3271 & n3207 & n3197; + assign n3273 = (~n2434 | n3270) & n3272; + assign n3274 = n3276 | (n817 & n3968); + assign n3275 = n3274 & n3207 & n3197; + assign n3276 = n3203 & (~Ni41 | n3205); + assign n3277 = n3246 & n3275 & (n1216 | n3276); + assign n3278 = n3276 & (Ni40 | n3205); + assign n3279 = n3210 & (~n783 | n3278); + assign n3280 = n3278 | (n817 & n3968); + assign n3281 = n3280 & n3207 & n3197; + assign n3282 = (~n2434 | n3279) & n3281; + assign n3283 = ~n4732 & (Pi22 | ~Pi21 | n3202); + assign n3284 = ~n799 & n3283; + assign n3285 = (n3277 | n3743) & (n3282 | n3737); + assign n3286 = (n3268 | n2272) & (n3273 | n3895); + assign n3287 = n3284 & (~n3288 | (n3285 & n3286)); + assign n3288 = ~n2254 & ~n3550; + assign n3289 = ~n3978 & (n3229 | (~n3225 & n3288)); + assign n3290 = ~n3979 & (n3243 | (~n3241 & n3288)); + assign n3291 = (n3211 | n698) & (n3212 | n2434); + assign n3292 = n3291 & n3209; + assign n3293 = (n3220 | n698) & (n3221 | n2434); + assign n3294 = n3293 & n3219; + assign n3295 = (n3292 | n3223) & (n3294 | n3224); + assign n3296 = n3197 & (n3206 | n690); + assign n3297 = n3296 & (Ni36 | n3226); + assign n3298 = ~n3297 & n3227 & n3228; + assign n3299 = (n3232 | n698) & (n3233 | n2434); + assign n3300 = n3299 & n3231; + assign n3301 = (n3238 | n698) & (n3239 | n2434); + assign n3302 = n3301 & n3237; + assign n3303 = (n3300 | n3223) & (n3302 | n3224); + assign n3304 = n3197 & (n3205 | n690); + assign n3305 = n3304 & (Ni36 | n3242); + assign n3306 = n3227 & (n810 | (n3228 & ~n3305)); + assign n3307 = n3245 & (n3247 | n698); + assign n3308 = (n3249 | n698) & (n3250 | n2530); + assign n3309 = n3308 & n3252; + assign n3310 = n3255 & (n3235 | n698); + assign n3311 = (n3257 | n698) & (n3258 | n2530); + assign n3312 = n3311 & n3260; + assign n3313 = (n3310 | n3743) & (n3312 | n3737); + assign n3314 = (n3307 | n2272) & (n3309 | n3895); + assign n3315 = n3262 & (~n3288 | (n3313 & n3314)); + assign n3316 = n3267 & (n3204 | n698); + assign n3317 = (n3269 | n698) & (n3270 | n2530); + assign n3318 = n3317 & n3272; + assign n3319 = n3275 & (n3276 | n698); + assign n3320 = (n3278 | n698) & (n3279 | n2530); + assign n3321 = n3320 & n3281; + assign n3322 = (n3319 | n3743) & (n3321 | n3737); + assign n3323 = (n3316 | n2272) & (n3318 | n3895); + assign n3324 = n3284 & (~n3288 | (n3322 & n3323)); + assign n3325 = ~n3978 & ((n3288 & ~n3295) | n3298); + assign n3326 = ~n3979 & ((n3288 & ~n3303) | n3306); + assign n3327 = Ni11 | n1446; + assign n3328 = n3327 & (~n807 | (~n2254 & ~n3471)); + assign n3329 = ~n3944 & (n3325 | n3326 | ~n4030); + assign n3330 = ~n2367 & (n3289 | n3290 | ~n4031); + assign n3331 = ~Ni44 | Ni43; + assign n3332 = ~n2426 & ~n3191 & (~n3193 | n3331); + assign n3333 = n3193 & (n2441 | n3191); + assign n3334 = ~n3332 & (n3215 | n3333); + assign n3335 = n3193 & (n3191 | n3754); + assign n3336 = n3335 & (n3333 | ~Ni42); + assign n3337 = n3353 & (Ni40 | n3395); + assign n3338 = n3337 | n817; + assign n3339 = Ni37 | n3974; + assign n3340 = n3337 | (~n783 & n3968); + assign n3341 = n3340 & n3339 & n3197; + assign n3342 = n3337 | n698; + assign n3343 = n3341 & n3342 & (Ni35 | n3338); + assign n3344 = ~n797 & n3480; + assign n3345 = (~Ni33 | n3343) & n3344; + assign n3346 = n3353 & (Ni40 | n3401); + assign n3347 = n3346 | n853; + assign n3348 = n3346 | (~n783 & n3968); + assign n3349 = n3348 & n3339 & n3197; + assign n3350 = n3346 | n698; + assign n3351 = n3349 & n3350 & (Ni35 | n3347); + assign n3352 = n3344 & (~Ni33 | n3351); + assign n3353 = n3336 & n3836; + assign n3354 = n3197 & n3339 & (n3353 | ~Ni38); + assign n3355 = n3354 & (n3353 | n690); + assign n3356 = n3344 & (~Ni33 | n3355); + assign n3357 = (n3345 | n1408) & (n3352 | n914); + assign n3358 = n807 & n3357 & (n3356 | n1702); + assign n3359 = n3336 & (Ni40 | n3423); + assign n3360 = n3359 | n817; + assign n3361 = n3359 | (~n783 & n3968); + assign n3362 = n3361 & n3339 & n3197; + assign n3363 = n3359 | n698; + assign n3364 = n3362 & n3363 & (Ni35 | n3360); + assign n3365 = n3344 & (~Ni33 | n3364); + assign n3366 = n3336 & (Ni40 | n3428); + assign n3367 = n3366 | n853; + assign n3368 = n3366 | (~n783 & n3968); + assign n3369 = n3368 & n3339 & n3197; + assign n3370 = n3366 | n698; + assign n3371 = n3369 & n3370 & (Ni35 | n3367); + assign n3372 = n3344 & (~Ni33 | n3371); + assign n3373 = n3197 & n3339 & (n3336 | ~Ni38); + assign n3374 = n3373 & (n3336 | n690); + assign n3375 = n3344 & (~Ni33 | n3374); + assign n3376 = (n3365 | n1408) & (n3372 | n914); + assign n3377 = n807 & n3376 & (n3375 | n1702); + assign n3378 = n3341 & (Ni35 | n3338); + assign n3379 = n3344 & (~Ni33 | n3378); + assign n3380 = n3349 & (Ni35 | n3347); + assign n3381 = n3344 & (~Ni33 | n3380); + assign n3382 = n3344 & (~Ni33 | n3354); + assign n3383 = (n3379 | n1408) & (n3381 | n914); + assign n3384 = n807 & n3383 & (n3382 | n1702); + assign n3385 = n3362 & (Ni35 | n3360); + assign n3386 = n3344 & (~Ni33 | n3385); + assign n3387 = n3369 & (Ni35 | n3367); + assign n3388 = n3344 & (~Ni33 | n3387); + assign n3389 = n3344 & (~Ni33 | n3373); + assign n3390 = (n3386 | n1408) & (n3388 | n914); + assign n3391 = n807 & n3390 & (n3389 | n1702); + assign n3392 = n3198 | n3854; + assign n3393 = n3395 | (n817 & n3968); + assign n3394 = n3393 & n3392 & n3197; + assign n3395 = n3836 & n3334; + assign n3396 = n3394 & (n3395 | n698); + assign n3397 = n3344 & (~Ni33 | n3396); + assign n3398 = n3198 | n3855; + assign n3399 = n3401 | (n853 & n3968); + assign n3400 = n3399 & n3398 & n3197; + assign n3401 = n3333 & n3836; + assign n3402 = n3400 & (n3401 | n698); + assign n3403 = n3344 & (~Ni33 | n3402); + assign n3404 = n3406 | (~n783 & n3968); + assign n3405 = n3404 & n3339 & n3197; + assign n3406 = n3353 & (n3395 | ~Ni40); + assign n3407 = n3406 | n817; + assign n3408 = n3406 | n698; + assign n3409 = n3405 & n3408 & (~Ni35 | n3407); + assign n3410 = n3344 & (~Ni33 | n3409); + assign n3411 = n3413 | (~n783 & n3968); + assign n3412 = n3411 & n3339 & n3197; + assign n3413 = n3353 & (n3401 | ~Ni40); + assign n3414 = n3413 | n853; + assign n3415 = n3413 | n698; + assign n3416 = n3412 & n3415 & (~Ni35 | n3414); + assign n3417 = n3344 & (~Ni33 | n3416); + assign n3418 = n807 & (n3410 | n3893); + assign n3419 = (n3397 | n1408) & (n3403 | n914); + assign n3420 = n3418 & n3419 & (n3417 | n2109); + assign n3421 = n3423 | (n817 & n3968); + assign n3422 = n3421 & n3392 & n3197; + assign n3423 = n3336 & n3334; + assign n3424 = n3422 & (n3423 | n698); + assign n3425 = n3344 & (~Ni33 | n3424); + assign n3426 = n3428 | (n853 & n3968); + assign n3427 = n3426 & n3398 & n3197; + assign n3428 = n3336 & (Ni41 | n3333); + assign n3429 = n3427 & (n3428 | n698); + assign n3430 = n3344 & (~Ni33 | n3429); + assign n3431 = n3433 | (~n783 & n3968); + assign n3432 = n3431 & n3339 & n3197; + assign n3433 = n3336 & (n3423 | ~Ni40); + assign n3434 = n3433 | n817; + assign n3435 = n3433 | n698; + assign n3436 = n3432 & n3435 & (~Ni35 | n3434); + assign n3437 = n3344 & (~Ni33 | n3436); + assign n3438 = n3440 | (~n783 & n3968); + assign n3439 = n3438 & n3339 & n3197; + assign n3440 = n3336 & (n3428 | ~Ni40); + assign n3441 = n3440 | n853; + assign n3442 = n3440 | n698; + assign n3443 = n3439 & n3442 & (~Ni35 | n3441); + assign n3444 = n3344 & (~Ni33 | n3443); + assign n3445 = n807 & (n3437 | n3893); + assign n3446 = (n3425 | n1408) & (n3430 | n914); + assign n3447 = n3445 & n3446 & (n3444 | n2109); + assign n3448 = n698 | n3974; + assign n3449 = n3448 & n3394 & (n1216 | n3395); + assign n3450 = n3344 & (~Ni33 | n3449); + assign n3451 = n3448 & n3400 & (n1216 | n3401); + assign n3452 = n3344 & (~Ni33 | n3451); + assign n3453 = n3405 & (~Ni35 | n3407); + assign n3454 = n3344 & (~Ni33 | n3453); + assign n3455 = n3412 & (~Ni35 | n3414); + assign n3456 = n3344 & (~Ni33 | n3455); + assign n3457 = n807 & (n3454 | n3893); + assign n3458 = (n3450 | n1408) & (n3452 | n914); + assign n3459 = n3457 & n3458 & (n3456 | n2109); + assign n3460 = n3448 & n3422 & (n1216 | n3423); + assign n3461 = n3344 & (~Ni33 | n3460); + assign n3462 = n3448 & n3427 & (n1216 | n3428); + assign n3463 = n3344 & (~Ni33 | n3462); + assign n3464 = n3432 & (~Ni35 | n3434); + assign n3465 = n3344 & (~Ni33 | n3464); + assign n3466 = n3439 & (~Ni35 | n3441); + assign n3467 = n3344 & (~Ni33 | n3466); + assign n3468 = n807 & (n3465 | n3893); + assign n3469 = (n3461 | n1408) & (n3463 | n914); + assign n3470 = n3468 & n3469 & (n3467 | n2109); + assign n3471 = ~n809 & n3480; + assign n3472 = n807 & (n3471 | n1919); + assign n3473 = (~n2345 | n3389) & (n3382 | ~n3772); + assign n3474 = ~n2272 & (~n3472 | ~n4604); + assign n3475 = ~n3743 & (~n3472 | ~n4606); + assign n3476 = (~n2345 | n3375) & (n3356 | ~n3772); + assign n3477 = ~n3740 & (~n3472 | ~n4593); + assign n3478 = ~n2272 & (~n3472 | ~n4594); + assign n3479 = ~n3743 & (~n3472 | ~n4596); + assign n3480 = n1539 | Ni33 | n3199; + assign n3481 = ~Ni34 | n3201; + assign n3482 = ~n797 & n3480 & (~Ni33 | n3481); + assign n3483 = Ni34 | ~Ni33; + assign n3484 = n3482 & (n3343 | n3483); + assign n3485 = n3482 & (n3351 | n3483); + assign n3486 = n3482 & (n3355 | n3483); + assign n3487 = (n3484 | n1408) & (n3485 | n914); + assign n3488 = n807 & n3487 & (n3486 | n1702); + assign n3489 = n3482 & (n3364 | n3483); + assign n3490 = n3482 & (n3371 | n3483); + assign n3491 = n3482 & (n3374 | n3483); + assign n3492 = (n3489 | n1408) & (n3490 | n914); + assign n3493 = n807 & n3492 & (n3491 | n1702); + assign n3494 = n3482 & (n3378 | n3483); + assign n3495 = n3482 & (n3380 | n3483); + assign n3496 = n3482 & (n3354 | n3483); + assign n3497 = (n3494 | n1408) & (n3495 | n914); + assign n3498 = n807 & n3497 & (n3496 | n1702); + assign n3499 = n3482 & (n3385 | n3483); + assign n3500 = n3482 & (n3387 | n3483); + assign n3501 = n3482 & (n3373 | n3483); + assign n3502 = (n3499 | n1408) & (n3500 | n914); + assign n3503 = n807 & n3502 & (n3501 | n1702); + assign n3504 = n3482 & (n3396 | n3483); + assign n3505 = n3482 & (n3402 | n3483); + assign n3506 = n3482 & (n3409 | n3483); + assign n3507 = n3482 & (n3416 | n3483); + assign n3508 = n807 & (n3506 | n3893); + assign n3509 = (n3504 | n1408) & (n3505 | n914); + assign n3510 = n3508 & n3509 & (n3507 | n2109); + assign n3511 = n3482 & (n3424 | n3483); + assign n3512 = n3482 & (n3429 | n3483); + assign n3513 = n3482 & (n3436 | n3483); + assign n3514 = n3482 & (n3443 | n3483); + assign n3515 = n807 & (n3513 | n3893); + assign n3516 = (n3511 | n1408) & (n3512 | n914); + assign n3517 = n3515 & n3516 & (n3514 | n2109); + assign n3518 = n3482 & (n3449 | n3483); + assign n3519 = n3482 & (n3451 | n3483); + assign n3520 = n3482 & (n3453 | n3483); + assign n3521 = n3482 & (n3455 | n3483); + assign n3522 = n807 & (n3520 | n3893); + assign n3523 = (n3518 | n1408) & (n3519 | n914); + assign n3524 = n3522 & n3523 & (n3521 | n2109); + assign n3525 = n3482 & (n3460 | n3483); + assign n3526 = n3482 & (n3462 | n3483); + assign n3527 = n3482 & (n3464 | n3483); + assign n3528 = n3482 & (n3466 | n3483); + assign n3529 = n807 & (n3527 | n3893); + assign n3530 = (n3525 | n1408) & (n3526 | n914); + assign n3531 = n3529 & n3530 & (n3528 | n2109); + assign n3532 = (~n2345 | n3501) & (n3496 | ~n3772); + assign n3533 = ~n2272 & (~n3472 | ~n4625); + assign n3534 = ~n3743 & (~n3472 | ~n4627); + assign n3535 = (~n2345 | n3491) & (n3486 | ~n3772); + assign n3536 = ~n3740 & (~n3472 | ~n4614); + assign n3537 = ~n2272 & (~n3472 | ~n4615); + assign n3538 = ~n3743 & (~n3472 | ~n4617); + assign n3539 = n3975 | Ni34 | n3199; + assign n3540 = ~n797 & n3539 & (~Ni33 | n3481); + assign n3541 = n3292 | n3550; + assign n3542 = n3541 & n3540 & (n3343 | n3483); + assign n3543 = n3294 | n3550; + assign n3544 = n3543 & n3540 & (n3351 | n3483); + assign n3545 = (n3297 | n3550) & (n3355 | n3483); + assign n3546 = n3545 & n3540; + assign n3547 = (n3542 | n1408) & (n3544 | n914); + assign n3548 = n807 & n3547 & (n3546 | n1702); + assign n3549 = n3364 | n3483; + assign n3550 = n1539 | n3953; + assign n3551 = n3549 & n3540 & (n3300 | n3550); + assign n3552 = n3371 | n3483; + assign n3553 = n3552 & n3540 & (n3302 | n3550); + assign n3554 = (n3305 | n3550) & (n3374 | n3483); + assign n3555 = n3554 & n3540; + assign n3556 = (n3551 | n1408) & (n3553 | n914); + assign n3557 = n807 & n3556 & (n3555 | n1702); + assign n3558 = n3213 | n3550; + assign n3559 = n3558 & n3540 & (n3378 | n3483); + assign n3560 = n3222 | n3550; + assign n3561 = n3560 & n3540 & (n3380 | n3483); + assign n3562 = (n3226 | n3550) & (n3354 | n3483); + assign n3563 = n3562 & n3540; + assign n3564 = (n3559 | n1408) & (n3561 | n914); + assign n3565 = n807 & n3564 & (n3563 | n1702); + assign n3566 = n3385 | n3483; + assign n3567 = n3566 & n3540 & (n3234 | n3550); + assign n3568 = n3387 | n3483; + assign n3569 = n3568 & n3540 & (n3240 | n3550); + assign n3570 = (n3242 | n3550) & (n3373 | n3483); + assign n3571 = n3570 & n3540; + assign n3572 = (n3567 | n1408) & (n3569 | n914); + assign n3573 = n807 & n3572 & (n3571 | n1702); + assign n3574 = n3316 | n3550; + assign n3575 = n3574 & n3540 & (n3396 | n3483); + assign n3576 = n3307 | n3550; + assign n3577 = n3576 & n3540 & (n3402 | n3483); + assign n3578 = n3318 | n3550; + assign n3579 = n3578 & n3540 & (n3409 | n3483); + assign n3580 = n3309 | n3550; + assign n3581 = n3580 & n3540 & (n3416 | n3483); + assign n3582 = n807 & (n3579 | n3893); + assign n3583 = (n3575 | n1408) & (n3577 | n914); + assign n3584 = n3582 & n3583 & (n3581 | n2109); + assign n3585 = n3424 | n3483; + assign n3586 = n3585 & n3540 & (n3319 | n3550); + assign n3587 = n3429 | n3483; + assign n3588 = n3587 & n3540 & (n3310 | n3550); + assign n3589 = n3436 | n3483; + assign n3590 = n3589 & n3540 & (n3321 | n3550); + assign n3591 = n3443 | n3483; + assign n3592 = n3591 & n3540 & (n3312 | n3550); + assign n3593 = n807 & (n3590 | n3893); + assign n3594 = (n3586 | n1408) & (n3588 | n914); + assign n3595 = n3593 & n3594 & (n3592 | n2109); + assign n3596 = n3268 | n3550; + assign n3597 = n3596 & n3540 & (n3449 | n3483); + assign n3598 = n3248 | n3550; + assign n3599 = n3598 & n3540 & (n3451 | n3483); + assign n3600 = n3273 | n3550; + assign n3601 = n3600 & n3540 & (n3453 | n3483); + assign n3602 = n3253 | n3550; + assign n3603 = n3602 & n3540 & (n3455 | n3483); + assign n3604 = n807 & (n3601 | n3893); + assign n3605 = (n3597 | n1408) & (n3599 | n914); + assign n3606 = n3604 & n3605 & (n3603 | n2109); + assign n3607 = n3460 | n3483; + assign n3608 = n3607 & n3540 & (n3277 | n3550); + assign n3609 = n3462 | n3483; + assign n3610 = n3609 & n3540 & (n3256 | n3550); + assign n3611 = n3464 | n3483; + assign n3612 = n3611 & n3540 & (n3282 | n3550); + assign n3613 = n3466 | n3483; + assign n3614 = n3613 & n3540 & (n3261 | n3550); + assign n3615 = n807 & (n3612 | n3893); + assign n3616 = (n3608 | n1408) & (n3610 | n914); + assign n3617 = n3615 & n3616 & (n3614 | n2109); + assign n3618 = n2254 | n3624; + assign n3619 = n3561 & ~n3635 & (n3222 | n3618); + assign n3620 = n3213 | n3618; + assign n3621 = ~n798 & n3283; + assign n3622 = n3620 & n3621 & (n3559 | n1929); + assign n3623 = Pi25 | ~n809; + assign n3624 = Pi25 | n3975; + assign n3625 = n3623 & n3563 & (n3226 | n3624); + assign n3626 = (n3622 | n3223) & (n3619 | n3224); + assign n3627 = ~Pi22 | ~n3227; + assign n3628 = n807 & n3626 & (n3625 | n3627); + assign n3629 = n3623 & n3571 & (n3242 | n3624); + assign n3630 = ~n3223 & (~n3621 | ~n4646); + assign n3631 = ~n3630 & (n3224 | (~n3635 & n4647)); + assign n3632 = n807 & n3631 & (n3629 | n3627); + assign n3633 = n3599 & ~n3635 & (n3248 | n3618); + assign n3634 = n3603 & ~n3635 & (n3253 | n3618); + assign n3635 = n798 | n3977; + assign n3636 = ~n3743 & (n3635 | ~n4654); + assign n3637 = ~n3737 & (n3635 | ~n4655); + assign n3638 = ~n2272 & (~n3621 | ~n4648); + assign n3639 = ~n3743 & (~n3621 | ~n4650); + assign n3640 = n3544 & ~n3635 & (n3294 | n3618); + assign n3641 = n3292 | n3618; + assign n3642 = n3641 & n3621 & (n3542 | n1929); + assign n3643 = n3623 & n3546 & (n3297 | n3624); + assign n3644 = (n3642 | n3223) & (n3640 | n3224); + assign n3645 = n807 & n3644 & (n3643 | n3627); + assign n3646 = n3623 & n3555 & (n3305 | n3624); + assign n3647 = ~n3223 & (~n3621 | ~n4634); + assign n3648 = ~n3647 & (n3224 | (~n3635 & n4635)); + assign n3649 = n807 & n3648 & (n3646 | n3627); + assign n3650 = n3577 & ~n3635 & (n3307 | n3618); + assign n3651 = n3581 & ~n3635 & (n3309 | n3618); + assign n3652 = ~n3743 & (n3635 | ~n4642); + assign n3653 = ~n3737 & (n3635 | ~n4643); + assign n3654 = ~n2272 & (~n3621 | ~n4636); + assign n3655 = ~n3743 & (~n3621 | ~n4638); + assign n3656 = ~n4739 & (~Pi17 | ~n4660 | ~n4661); + assign n3657 = ~n3327 & ~n4740 & (~Ni10 | n3656); + assign n3658 = (~n3707 & ~n4032) | (~Ni33 & (n3707 | ~n4032)); + assign n3659 = n3707 | n3805; + assign n3660 = n4662 & (~n4029 | (~n1543 & ~Ni13)); + assign n3661 = ~Ni47 | ~n3192; + assign n3662 = ~n900 & n3661 & (Pi20 | ~n3192); + assign n3663 = Ni30 | n801; + assign n3664 = Ni47 & (n801 | Ni30); + assign n3665 = n1353 & Ni30; + assign n3666 = n1463 & Ni30; + assign n3667 = Ni12 | ~n3727; + assign n3668 = n3665 & (n3666 | n3667); + assign n3669 = n1354 & Ni30; + assign n3670 = n1553 & n1542 & n1543; + assign n3671 = n4750 & (Ni12 | n3679); + assign n3672 = ~Pi26 & n3981; + assign n3673 = n3670 & n3671 & (Ni14 | n3672); + assign n3674 = (n3841 | n3696) & (n3838 | n2632); + assign n3675 = ~n3842 & (n3670 | (Pi24 & n3666)); + assign n3676 = n3695 & (Pi26 | n3666); + assign n3677 = n1446 | ~Ni11; + assign n3678 = n3674 & n3675 & (n3676 | n3677); + assign n3679 = Pi26 & n3981; + assign n3680 = (n3672 | n2632) & (n3679 | n3677); + assign n3681 = ~n3696 & ~n4775 & (n788 | ~n3841); + assign n3682 = n3840 & (~Pi23 | (n3670 & n3680)); + assign n3683 = ~Pi24 & n3666; + assign n3684 = ~n3681 & n3682 & (n3670 | n3683); + assign n3685 = ~n3696 & ~n4775 & (n795 | ~n3841); + assign n3686 = n3840 & (Pi23 | (n3670 & n3680)); + assign n3687 = ~n3685 & (n3670 | n3683) & n3686; + assign n3688 = Ni7 | Ni8; + assign n3689 = n3688 & n1670 & (Ni8 | Ni10); + assign n3690 = (n3687 | n3766) & (n3673 | n3689); + assign n3691 = (n3684 | n3937) & (n3678 | n2066); + assign n3692 = n3690 & n3691; + assign n3693 = ~n3692 & (~Ni6 | ~Ni5); + assign n3694 = n2632 | Pi26 | n3841; + assign n3695 = n3665 & (~Pi27 | n3666); + assign n3696 = ~Ni12 | n2750; + assign n3697 = n3694 & n3668 & (n3695 | n3696); + assign n3698 = n3665 & (~Pi26 | n3677 | n3841); + assign n3699 = n4663 & n4664 & (n3669 | n3982); + assign n3700 = n3698 & n3699 & (Ni11 | n3697); + assign n3701 = (Ni32 | n2399) & (n801 | ~Ni41); + assign n3702 = ~Ni5 & (~Ni31 | ~Ni6 | ~n3980); + assign n3703 = ~n3707 & (n780 | (~Ni6 & ~n3692)); + assign n3704 = Ni4 | n3711; + assign n3705 = ~n3703 & ~Ni2 & (Ni31 | n3704); + assign n3706 = n3701 & Ni30; + assign n3707 = Ni2 | Ni3; + assign n3708 = (n1353 | n3704) & (~n3700 | n3707); + assign n3709 = n3702 | n3711 | ~Ni4 | ~n4752; + assign n3710 = (~Ni5 | n3705) & (n3706 | n3983); + assign n3711 = Ni2 | ~Ni3; + assign n3712 = (~n3700 | n3707) & (n3711 | ~n4665); + assign n3713 = (~n780 | n3707) & (n3980 | n3983); + assign n3714 = ~Ni9 & ~Ni7; + assign n3715 = ~n3707 & (~n3957 | (n3714 & ~n3767)); + assign n3716 = (~n795 | ~Ni7) & (n3688 | n3950); + assign n3717 = n3716 & (Pi24 | ~Ni8); + assign n3718 = ~Ni10 | n3707 | n3717 | ~n3957; + assign n3719 = (~n788 | Ni10) & ~Ni9; + assign n3720 = (n773 | n3688) & (~Ni8 | n3719); + assign n3721 = (Ni10 | ~Ni7) & (n3720 | ~n3957); + assign n3722 = (~n789 & ~Ni14) | (Pi27 & (~n789 | Ni14)); + assign n3723 = n3722 & ~Ni11 & ~Ni13; + assign n3724 = (n785 | n1543) & (~Ni11 | ~n3761); + assign n3725 = n3724 & (Pi27 | ~Ni12); + assign n3726 = ~Ni14 | n3707 | n3725 | ~n3727; + assign n3727 = ~Ni14 | ~Ni13; + assign n3728 = n789 & ~Ni14 & Ni12; + assign n3729 = ~n1543 & n785 & Ni14; + assign n3730 = n3727 & (n3728 | n3729 | Ni13); + assign n3731 = ~n3707 & ((Ni11 & ~Ni14) | n3730); + assign n3732 = ~Ni42 | ~Ni43; + assign n3733 = Ni44 | ~Ni43; + assign n3734 = n3732 & (n2426 | n3733); + assign n3735 = ~Ni41 | ~Ni43; + assign n3736 = (n3740 | ~Ni43) & (n3844 | n3894); + assign n3737 = ~Pi16 | n1322; + assign n3738 = n3734 & n3736 & (n3735 | n3737); + assign n3739 = (n3737 | ~Ni43) & (n3844 | n3895); + assign n3740 = ~Pi16 | n3864; + assign n3741 = n3734 & n3739 & (n3735 | n3740); + assign n3742 = (n3738 & (n3741 | Ni40)) | (n3741 & ~Ni40); + assign n3743 = ~Pi16 | n3867; + assign n3744 = n3742 & (n3735 | n3743); + assign n3745 = ~Ni44 | ~Ni43; + assign n3746 = n3732 & (n2426 | n3745); + assign n3747 = n3746 & n3736 & (n3735 | n3737); + assign n3748 = n3746 & n3739 & (n3735 | n3740); + assign n3749 = (n3747 & (n3748 | Ni40)) | (n3748 & ~Ni40); + assign n3750 = n3749 & (n3735 | n3743); + assign n3751 = Ni31 | n784; + assign n3752 = (~n2345 | ~Ni43) & (~n3772 | n3844); + assign n3753 = (~Pi20 & n3750) | (n3744 & (Pi20 | n3750)); + assign n3754 = Ni42 | ~Ni43; + assign n3755 = n2426 | ~Ni40; + assign n3756 = n3733 | n3755; + assign n3757 = n3756 | (Ni30 & ~n3984); + assign n3758 = (n801 | Ni41) & (~Ni31 | n887); + assign n1090_1 = ~n3711; + assign n3760 = Ni4 & ~n3711 & ~n2418 & ~n3701; + assign n3761 = Pi27 | ~Pi26; + assign n3762 = (~Ni12 | ~n3723) & (n3677 | n3761); + assign n3763 = ~n3795 & (n3760 | (~n3758 & ~n3983)); + assign n3764 = Ni30 | n2418 | n3704 | ~n3973; + assign n3765 = n887 & (~Ni32 | Ni41); + assign n3766 = ~Ni10 | n2074 | ~Ni7; + assign n3767 = (~Pi24 & (n788 | Ni10)) | (n788 & ~Ni10); + assign n3768 = ~Ni8 | Ni9 | Ni7; + assign n3769 = (n795 | n3766) & (n3767 | n3768); + assign n3770 = n2418 | n3711 | n4764 | n4765; + assign n3771 = n1353 | n3983 | Ni33 | n3765; + assign n3772 = ~Pi16 & n3184; + assign n3773 = ~n3472 & (n2345 | n3772); + assign n986 = n2407 | n2408 | n2415 | ~n4379; + assign n3775 = ~n2417 & (Pi21 | n801) & n3810; + assign n946_1 = ~n3775; + assign n3777 = n900 & n3837 & (~Ni47 | ~n3711); + assign n936 = ~n3777; + assign n3779 = n3845 & ((n655 & Ni30) | ~n4050); + assign n3780 = ~n3754 & Ni41 & ~Pi16 & ~n806; + assign n3781 = n3846 & ~n4758 & (Pi20 | ~n3757); + assign n961_1 = n3781 | n3779 | n3780; + assign n3783 = Pi20 & (~n905 | (~Pi21 & ~n1116)); + assign n3784 = ~Pi20 & (~n905 | (~Pi21 & ~n1091)); + assign n3785 = Pi20 & (~n905 | (~Pi21 & ~n1249)); + assign n3786 = ~Pi20 & (~n905 | (~Pi21 & ~n1239)); + assign n3787 = Pi20 & (~n905 | (~Pi21 & ~n1196)); + assign n3788 = ~Pi20 & (~n905 | (~Pi21 & ~n1172)); + assign n3789 = ~n901 | n1209 | n3787 | n3788; + assign n3790 = Pi20 & (~n905 | (~Pi21 & ~n1281)); + assign n3791 = ~Pi20 & (~n905 | (~Pi21 & ~n1274)); + assign n3792 = ~n901 | n1288 | n3790 | n3791; + assign n3793 = n1540 & n1354; + assign n3794 = (~Pi27 | n1918) & n3793; + assign n3795 = ~Ni30 | ~Ni33; + assign n3796 = n1354 & (~n789 | ~Ni30); + assign n3797 = n1353 & (~n789 | n1463); + assign n3798 = ~Pi21 & ~n3796; + assign n3799 = ~Pi22 & ~n3796; + assign n3800 = ~Pi24 & (n3798 | n3799 | ~n4300); + assign n3801 = n1354 & (Pi27 | ~Ni30); + assign n3802 = n1353 & (Pi27 | n1463); + assign n3803 = Ni14 & ~n3801 & (Pi24 | ~n3802); + assign n3804 = ~n3803 & (n1540 | n2254); + assign n3805 = Ni7 | n2074; + assign n3806 = Ni34 & n3805 & (n3327 | ~n3995); + assign n3807 = ~n665 | Ni33; + assign n3808 = n2390 & (~Pi26 | ~n665) & n3807; + assign n3809 = n2400 & (~Pi27 | ~n665) & n3807; + assign n3810 = n903 & (~Ni45 | (~n2418 & ~n3704)); + assign n3811 = n2425 & (Ni42 | Ni47); + assign n3812 = n784 & n811; + assign n3813 = n802 & n2424; + assign n3814 = (n3824 | n2254) & (Pi27 | n3822); + assign n3815 = n801 & n811; + assign n3816 = n2649 & n3814 & (n3815 | n2643); + assign n3817 = (~Pi27 | n3037) & n3813; + assign n3818 = n2623 & (~Pi26 | ~Ni32); + assign n3819 = n802 & n811; + assign n3820 = (~Pi27 | n3812) & n3819; + assign n3821 = (~Pi26 | n3812) & n3820; + assign n3822 = n2419 & n812; + assign n3823 = (~Pi27 | n813) & n3815; + assign n3824 = n801 & n2424; + assign n3825 = n2424 & n812; + assign n3826 = n3820 & (Pi26 | n3812); + assign n3827 = n3969 & n3187; + assign n3828 = n800 & n3827 & (~Pi26 | n3751); + assign n3829 = n2406 & n3956; + assign n3830 = ~n3828 & (Pi23 | ~n3827 | n3829); + assign n3831 = n3972 & n3189; + assign n3832 = n800 & n3831 & (~Pi27 | n3751); + assign n3833 = ~n3832 & (Pi24 | n3829 | ~n3831); + assign n3834 = ~Pi22 & (n797 | (~n1539 & ~n3191)); + assign n3835 = ~Pi21 & (n797 | (~n1539 & n3185)); + assign n3836 = n3200 | ~Ni41; + assign n3837 = ~n3664 & (~Ni47 | (~n2418 & ~Ni4)); + assign n3838 = (~Pi26 | n3666) & n3695; + assign n3839 = (n3838 | n2632) & (n3676 | n3677); + assign n3840 = (~Pi24 | n3680) & n3839; + assign n3841 = n3665 & (Pi27 | n3666); + assign n3842 = ~Pi24 & (~n3680 | (~n3696 & ~n4775)); + assign n3843 = n3669 & (Ni11 | n3667); + assign n3844 = Ni41 | ~Ni43; + assign n3845 = ~n806 & (Ni30 | ~n986_1 | n3732); + assign n3846 = Pi18 & ~Pi17; + assign n3847 = n18 | n2254; + assign n3848 = n2254 | ~n3184; + assign n3849 = n677 & ~Ni47; + assign n3850 = ~n18 | n2416; + assign n3851 = Ni36 | n1241; + assign n3852 = Ni37 | Ni36; + assign n3853 = Ni38 | n3852; + assign n3854 = n3853 | ~Ni39; + assign n3855 = Ni39 | n3853; + assign n3856 = Ni32 | n2434; + assign n3857 = Pi20 | n2254; + assign n3858 = Pi25 | n3857; + assign n3859 = ~Pi20 | n2254; + assign n3860 = Pi25 | n3859; + assign n3861 = Pi20 & (~n905 | (~Pi21 & ~n868)); + assign n3862 = ~Pi20 & (~n905 | (~Pi21 & ~n835)); + assign n3863 = ~n901 | n909 | n3861 | n3862; + assign n3864 = Pi19 | ~Pi17; + assign n3865 = Pi20 & (~n905 | (~Pi21 & ~n1068)); + assign n3866 = ~Pi20 & (~n905 | (~Pi21 & ~n1053)); + assign n3867 = Pi17 | Pi19; + assign n3868 = ~Ni32 | n2530; + assign n3869 = Ni32 | n2530; + assign n3870 = Pi16 | Pi15; + assign n3871 = Pi20 & (~n905 | (~Pi21 & ~n1004)); + assign n3872 = ~Pi20 & (~n905 | (~Pi21 & ~n993)); + assign n3873 = ~n901 | n1015 | n3871 | n3872; + assign n3874 = n677 & ~Ni45; + assign n3875 = Pi20 & (~n905 | (~Pi21 & ~n1229)); + assign n3876 = ~Pi20 & (~n905 | (~Pi21 & ~n1220)); + assign n3877 = Pi16 | ~Pi15; + assign n3878 = Pi20 & (~n905 | (~Pi21 & ~n954)); + assign n3879 = ~Pi20 & (~n905 | (~Pi21 & ~n930)); + assign n3880 = ~n901 | n978 | n3878 | n3879; + assign n3881 = Pi20 & (~n905 | (~Pi21 & ~n1152)); + assign n3882 = ~Pi20 & (~n905 | (~Pi21 & ~n1138)); + assign n3883 = ~n901 | n1211 | n3881 | n3882; + assign n3884 = ~Pi16 | Pi15; + assign n3885 = Pi20 & (~n905 | (~Pi21 & ~n1029)); + assign n3886 = ~Pi20 & (~n905 | (~Pi21 & ~n1022)); + assign n3887 = ~n901 | n1040 | n3885 | n3886; + assign n3888 = Pi20 & (~n905 | (~Pi21 & ~n1267)); + assign n3889 = ~Pi20 & (~n905 | (~Pi21 & ~n1260)); + assign n3890 = ~n901 | n1290 | n3888 | n3889; + assign n3891 = ~Pi16 | ~Pi15; + assign n3892 = Ni10 | ~n3327; + assign n3893 = ~Pi19 | n3857; + assign n3894 = Pi16 | n3864; + assign n3895 = Pi16 | n1322; + assign n3896 = Ni6 | Ni4 | Ni5; + assign n3897 = Ni11 | Ni10; + assign n3898 = n1446 & Ni11; + assign n3899 = n3848 | n3761; + assign n3900 = ~n3761 | n3848; + assign n3901 = n3857 | n3761; + assign n3902 = n3859 | n3761; + assign n3903 = ~n3761 | n3859; + assign n3904 = Pi27 | n1495; + assign n3905 = Pi27 | n1497; + assign n3906 = ~Pi27 | n1495; + assign n3907 = ~Pi27 | n1497; + assign n3908 = Pi27 | n3857; + assign n3909 = Pi27 | n3859; + assign n3910 = ~Pi27 | n3857; + assign n3911 = ~Pi27 | n3859; + assign n3912 = Ni13 | Ni14; + assign n3913 = n3848 | n789; + assign n3914 = ~n789 | n3848; + assign n3915 = n3857 | n789; + assign n3916 = n3859 | n789; + assign n3917 = ~n789 | n3859; + assign n3918 = n3799 | n3798; + assign n3919 = Ni11 | ~Ni12; + assign n3920 = Pi27 | n1923; + assign n3921 = ~Pi27 | n1923; + assign n3922 = Pi27 | n1929; + assign n3923 = ~Pi27 | n2372; + assign n3924 = n1923 | n789; + assign n3925 = ~n789 | n1923; + assign n3926 = n2372 | n789; + assign n3927 = n1314 | n789; + assign n3928 = Ni13 | n3919; + assign n3929 = n1923 | n3761; + assign n3930 = n1923 | ~n3761; + assign n3931 = n2372 | n3761; + assign n3932 = n1314 | n3761; + assign n3933 = n3848 | n788; + assign n3934 = ~n788 | n3848; + assign n3935 = n3857 | n788; + assign n3936 = ~n788 | n3857; + assign n3937 = Ni10 | n3768; + assign n3938 = ~Pi24 | n1495; + assign n3939 = ~Pi24 | n1497; + assign n3940 = Pi24 | n3857; + assign n3941 = Pi24 | n3859; + assign n3942 = ~Pi24 | n3857; + assign n3943 = ~Pi24 | n3859; + assign n3944 = Pi15 | n3327; + assign n3945 = n3848 | n795; + assign n3946 = ~n795 | n3848; + assign n3947 = n3857 | n795; + assign n3948 = ~n795 | n3857; + assign n3949 = ~Pi25 | n2079; + assign n3950 = ~n18 | Ni33; + assign n3951 = ~Pi25 | Ni34 | n1539 | n3950; + assign n3952 = n2254 | n2079; + assign n3953 = ~Ni34 | Ni33; + assign n3954 = n3952 | n3953; + assign n3955 = n3954 & ~n792 & n2085; + assign n3956 = Ni32 & Ni33; + assign n3957 = ~Ni10 | ~Ni9; + assign n3958 = Ni31 | n3795; + assign n3959 = Ni39 | n3852; + assign n3960 = n1241 | ~Ni38; + assign n3961 = n3852 | ~Ni39; + assign n3962 = n2389 | ~Ni38; + assign n3963 = n2518 & n2430 & n2431; + assign n3964 = n2523 & n2430 & n2444; + assign n3965 = n2427 & n2430 & n2431; + assign n3966 = n2442 & n2430 & n2444; + assign n3967 = ~Pi26 | Pi24; + assign n3968 = ~Ni37 | ~Ni38; + assign n3969 = Ni32 | ~Ni40; + assign n3970 = Ni33 | n3751; + assign n3971 = ~Ni33 | n3751; + assign n3972 = Ni32 | ~Ni41; + assign n3973 = Ni31 & Ni33; + assign n3974 = Ni38 | n3198; + assign n3975 = Ni33 | n1539; + assign n3976 = Ni38 | n3200; + assign n3977 = n3834 | n3835; + assign n3978 = ~Pi17 | Pi16; + assign n3979 = ~Pi17 | ~Pi16; + assign n3980 = ~Ni30 | n3701; + assign n3981 = ~Pi27 & n3669; + assign n3982 = n3688 | ~n3957; + assign n3983 = n3704 | Ni6 | ~Ni5; + assign n3984 = ~Ni32 & Ni30; + assign n3985 = n3707 | n2393; + assign n3986 = n2403 | Ni7 | n3707; + assign n3987 = ~n4673 & (~n18 | ~n3707); + assign n1026_1 = ~n3987; + assign n3989 = (~Ni10 & ~n1944) | (~n1718 & (Ni10 | ~n1944)); + assign n3990 = (Pi15 & n4678) | (n4677 & (~Pi15 | n4678)); + assign n3991 = ~n4687 & (~Pi17 | ~n4171 | ~n4172); + assign n3992 = ~n4686 & (Ni10 | ~n4195 | ~n4197); + assign n3993 = n3797 & (n1540 | n2254) & ~n3800; + assign n3994 = (~Ni10 | n2370) & n4700; + assign n3995 = ~n4701 & (~Pi17 | (n4375 & n4376)); + assign n3996 = (~Ni10 & ~n3060) | (~n2867 & (Ni10 | ~n3060)); + assign n3997 = (Pi15 & n4715) | (n4714 & (~Pi15 | n4715)); + assign n3998 = ~n4725 & (~Pi17 | ~n4434 | ~n4435); + assign n3999 = ~Pi22 & ~n3812 & (~Pi27 | ~n3819); + assign n4000 = ~n4713 & (~Ni14 | ~n4448 | ~n4449); + assign n4001 = (n4196 | n3060) & (Ni11 | n3061); + assign n4002 = ~n3175 & n4001 & (n3928 | ~n4000); + assign n4003 = (~Pi23 & n4724) | (~n2626 & (Pi23 | n4724)); + assign n4004 = (~n788 & ~n3816) | (~n2630 & (n788 | ~n3816)); + assign n4005 = (Pi24 & ~n3816) | (~n2630 & (~Pi24 | ~n3816)); + assign n4006 = (Pi24 & n4710) | (~n2626 & (~Pi24 | n4710)); + assign n4007 = (Pi24 & n4712) | (~n2636 & (~Pi24 | n4712)); + assign n4008 = (Pi23 & n4724) | (~n2626 & (~Pi23 | n4724)); + assign n4009 = (~n795 & ~n3816) | (~n2630 & (n795 | ~n3816)); + assign n4010 = n3896 & (n3178 | n3179 | ~n4589); + assign n4011 = n3969 & (~Pi23 | n3970); + assign n4012 = n3187 & n4011 & (~Ni40 | n3971); + assign n4013 = n4728 & (n2393 | (n4590 & n3827)); + assign n4014 = (~n2403 & n4729) | (~n4013 & (n2403 | n4729)); + assign n4015 = (~Pi24 | n3970) & n3972; + assign n4016 = n3189 & n4015 & (~Ni41 | n3971); + assign n4017 = n4730 & (n2393 | (n4591 & n3831)); + assign n4018 = (~n2403 & n4731) | (~n4017 & (n2403 | n4731)); + assign n4019 = ~n3773 & (n3737 | (n3472 & n4607)); + assign n4020 = ~n3475 & (n3895 | (n3472 & n4605)); + assign n4021 = ~n3474 & (n3740 | (n3472 & n4603)); + assign n4022 = n4608 & (n3894 | (n4602 & n3472)); + assign n4023 = n4022 & n4021 & n4019 & n4020; + assign n4024 = ~n3773 & (n3737 | (n3472 & n4628)); + assign n4025 = ~n3534 & (n3895 | (n3472 & n4626)); + assign n4026 = ~n3533 & (n3740 | (n3472 & n4624)); + assign n4027 = n4629 & (n3894 | (n4623 & n3472)); + assign n4028 = n4027 & n4026 & n4024 & n4025; + assign n4029 = ~n4749 & (~Ni10 | (~n4747 & ~n4748)); + assign n4030 = (~Pi20 & n3324) | (n3315 & (Pi20 | n3324)); + assign n4031 = (~Pi20 & n3287) | (n3265 & (Pi20 | n3287)); + assign n4032 = n3805 & (n3328 | n3329 | n3330); + assign n4033 = ~Ni4 | n780 | n3693; + assign n4034 = n4033 & ~n4751 & (Ni5 | ~n3692); + assign n4035 = ~n4755 & (~Ni4 | ~Ni2); + assign n1081 = ~n4035; + assign n4037 = n3957 | ~Ni8 | ~Ni7; + assign n4038 = n3688 & (n795 | ~Ni10 | n2074); + assign n4039 = n4037 & n4038 & (Ni7 | ~n3957); + assign n4040 = (~n3707 & ~n4039) | (~Ni7 & (n3707 | ~n4039)); + assign n1066_1 = ~n4040; + assign n4042 = (~Ni10 & (n3707 | n3721)) | (~n3707 & n3721); + assign n1051 = ~n4042; + assign n4044 = (Ni11 & (n1542 | n3727)) | (n1542 & ~n3727); + assign n4045 = n1543 & n4044 & (n1446 | n3761); + assign n4046 = (~n3707 & ~n4045) | (~Ni11 & (n3707 | ~n4045)); + assign n1046_1 = ~n4046; + assign n4048 = ~n4757 & (Ni12 | n3707 | n3727); + assign n1041_1 = ~n4048; + assign n4050 = ~n4759 & (~n3733 | ~Ni42 | ~Ni39); + assign n4051 = (~Pi26 | n4760) & n4761; + assign n4052 = (~Pi23 | n4762) & n4763; + assign n4053 = (n848 | n3857) & (n879 | n3859); + assign n4054 = (n940 | n3857) & (n964 | n3859); + assign n4055 = n1055 | (~Ni37 & n817); + assign n4056 = n1051_1 | (~Ni37 & n817); + assign n4057 = n1070 | (~Ni37 & n853); + assign n4058 = n1067 | (~Ni37 & n853); + assign n4059 = (n1060 | n3857) & (n1074 | n3859); + assign n4060 = (n1101 | n3857) & (n1126 | n3859); + assign n4061 = n1140 | (~Ni37 & n817); + assign n4062 = n1137 | (~Ni37 & n817); + assign n4063 = n1154 | (~Ni37 & n853); + assign n4064 = n1151 | (~Ni37 & n853); + assign n4065 = (n1144 | n3857) & (n1158 | n3859); + assign n4066 = (n1182 | n3857) & (n1206 | n3859); + assign n4067 = (n911 | ~n3772) & (n980 | ~n2345); + assign n4068 = n975 | n1497; + assign n4069 = n4068 & (n3894 | (~n3863 & n4053)); + assign n4070 = ~n1307 & (n3895 | (~n1295 & n4060)); + assign n4071 = n3850 | Ni32 | n884; + assign n4072 = n3850 | Ni32 | n967; + assign n4073 = (n999 | n3857) & (n1008 | n3859); + assign n4074 = (n1026 | n3857) & (n1033 | n3859); + assign n4075 = (n1226 | n3857) & (n1233 | n3859); + assign n4076 = (n1245 | n3857) & (n1253 | n3859); + assign n4077 = (n1264 | n3857) & (n1271 | n3859); + assign n4078 = (n1278 | n3857) & (n1285 | n3859); + assign n4079 = (n1017 | ~n3772) & (n1042 | ~n2345); + assign n4080 = n1037 | n1497; + assign n4081 = n4080 & (n3894 | (~n3873 & n4073)); + assign n4082 = ~n1300 & (n3895 | (~n1297 & n4076)); + assign n4083 = (n1102 | n3893) & (n1127 | n2109); + assign n4084 = n4083 & (n1061_1 | n1408); + assign n4085 = (n914 | n1075) & (Pi19 | ~n1306); + assign n4086 = (n1246 | n3893) & (n1254 | n2109); + assign n4087 = n4086 & (n1227 | n1408); + assign n4088 = (n914 | n1234) & (Pi19 | ~n1299); + assign n4089 = (n1215 | n3884) & (n1294 | n3891); + assign n4090 = (n915 | n3870) & (n1020 | n3877); + assign n4091 = (n983 | n3884) & (n1045 | n3891); + assign n4092 = (n848 | n3858) & (n879 | n3860); + assign n4093 = (n1060 | n3858) & (n1074 | n3860); + assign n4094 = (n1101 | n3858) & (n1126 | n3860); + assign n4095 = (n898 | n1923) & (n911 | ~n3184); + assign n4096 = Pi25 | n3847; + assign n4097 = (n999 | n3858) & (n1008 | n3860); + assign n4098 = (n1226 | n3858) & (n1233 | n3860); + assign n4099 = (n1245 | n3858) & (n1253 | n3860); + assign n4100 = (n1013 | n1923) & (n1017 | ~n3184); + assign n4101 = (n940 | n3858) & (n964 | n3860); + assign n4102 = (n1144 | n3858) & (n1158 | n3860); + assign n4103 = (n1182 | n3858) & (n1206 | n3860); + assign n4104 = (n976 | n1923) & (n980 | ~n3184); + assign n4105 = (n1026 | n3858) & (n1033 | n3860); + assign n4106 = (n1264 | n3858) & (n1271 | n3860); + assign n4107 = (n1278 | n3858) & (n1285 | n3860); + assign n4108 = (n1038 | n1923) & (n1042 | ~n3184); + assign n4109 = (n1332 | n3870) & (n1350 | n3877); + assign n4110 = (n1323 | n3884) & (n1341 | n3891); + assign n4111 = (n1937 | n3894) & (n1700 | n3740); + assign n4112 = n4111 & (n1961 | n2272); + assign n4113 = (n1958 | n3895) & (n1708 | n3743); + assign n4114 = n4113 & (n1709 | n3737); + assign n4115 = (n1704 | n3894) & (n1706 | n3740); + assign n4116 = n4115 & (n1711 | n2272); + assign n4117 = (n1712 | n3895) & (n1714 | n3743); + assign n4118 = n4117 & (n1715 | n3737); + assign n4119 = n1759 & n1404; + assign n4120 = n1769 & n1400; + assign n4121 = n1829 & n1429; + assign n4122 = n1839 & n1425; + assign n4123 = n1723 & n1417; + assign n4124 = n1734 & n1413; + assign n4125 = n1794 & n1441; + assign n4126 = n1804 & n1437; + assign n4127 = (n1687 | n3870) & (n1695 | n3877); + assign n4128 = (n1691 | n3884) & (n1699 | n3891); + assign n4129 = n1785 & n1361; + assign n4130 = n1855 & n1380; + assign n4131 = n1750 & n1371; + assign n4132 = n1820 & n1389; + assign n4133 = (n1674 | n3870) & (n1680 | n3877); + assign n4134 = (n1677 | n3884) & (n1683 | n3891); + assign n4135 = n1518 & n1357; + assign n4136 = n1530 & n1367; + assign n4137 = (n4136 | n3858) & (n1373 | n3860); + assign n4138 = n1516 & n1400; + assign n4139 = (n1407 | n3858) & (n4138 | n3860); + assign n4140 = n1510 & n1402; + assign n4141 = n1512 & n1404; + assign n4142 = (n4140 | n3858) & (n4141 | n3860); + assign n4143 = n1528 & n1413; + assign n4144 = (n1420 | n3858) & (n4143 | n3860); + assign n4145 = n1522 & n1415; + assign n4146 = n1524 & n1417; + assign n4147 = (n4145 | n3858) & (n4146 | n3860); + assign n4148 = (n1926 | n1923) & (n1938 | n3894); + assign n4149 = n1478 & n1376; + assign n4150 = n1490 & n1385; + assign n4151 = (n4150 | n3858) & (n1391 | n3860); + assign n4152 = n1476 & n1425; + assign n4153 = (n1432 | n3858) & (n4152 | n3860); + assign n4154 = n1470 & n1427; + assign n4155 = n1472 & n1429; + assign n4156 = (n4154 | n3858) & (n4155 | n3860); + assign n4157 = n1488 & n1437; + assign n4158 = (n1444 | n3858) & (n4157 | n3860); + assign n4159 = n1482 & n1439; + assign n4160 = n1484 & n1441; + assign n4161 = (n4159 | n3858) & (n4160 | n3860); + assign n4162 = (n1922 | n1923) & (n1930 | n3894); + assign n4163 = (n1961 | n1701) & (n1958 | n1702); + assign n4164 = n4163 & (n1713 | n3877); + assign n4165 = (n1710 | n3884) & (n1716 | n3891); + assign n4166 = (n1937 | n1701) & (n1360 | n1702); + assign n4167 = n4166 & (n1705 | n3877); + assign n4168 = (n1703 | n3884) & (n1707 | n3891); + assign n4169 = (n1409 | n3870) & (n1433 | n3877); + assign n4170 = (n1421 | n3884) & (n1445 | n3891); + assign n4171 = (n1365 | n3870) & (n1383 | n3877); + assign n4172 = (n1374 | n3884) & (n1392 | n3891); + assign n4173 = n1786 | n3924; + assign n4174 = n2026 | ~n3184; + assign n4175 = n1856 | n3924; + assign n4176 = n1751 | n3924; + assign n4177 = n1821 | n3924; + assign n4178 = (n2045 | n3870) & (n2063 | n3877); + assign n4179 = (n2036 | n3884) & (n2054 | n3891); + assign n4180 = n1360 | n3920; + assign n4181 = n1987 | ~n3184; + assign n4182 = n1379 | n3920; + assign n4183 = n1370 | n3920; + assign n4184 = n1388 | n3920; + assign n4185 = (n2006 | n3870) & (n2024 | n3877); + assign n4186 = (n1997 | n3884) & (n2015 | n3891); + assign n4187 = n1786 | n3929; + assign n4188 = n1946 | ~n3184; + assign n4189 = n1856 | n3929; + assign n4190 = n1751 | n3929; + assign n4191 = n1821 | n3929; + assign n4192 = (n1967 | n3870) & (n1985 | n3877); + assign n4193 = (n1956 | n3884) & (n1976 | n3891); + assign n4194 = n3928 | n4675 | n4676; + assign n4195 = n4194 & (n3677 | (n4193 & n4192)); + assign n4196 = n1452 & ~n3898; + assign n4197 = (n4196 | n1944) & (Ni11 | n1945); + assign n4198 = n1787 | n3899; + assign n4199 = n1455 | ~n3184; + assign n4200 = n1857 | n3899; + assign n4201 = n1752 | n3899; + assign n4202 = n1822 | n3899; + assign n4203 = (n1783 | n3908) & (n1673 | n3909); + assign n4204 = (n1777 | n3910) & (n1780 | n3911); + assign n4205 = (n1748 | n3908) & (n1676 | n3909); + assign n4206 = (n1742 | n3910) & (n1745 | n3911); + assign n4207 = (n1686 | n3908) & (n4120 | n3909); + assign n4208 = (n1768 | n3910) & (n1771 | n3911); + assign n4209 = (n1764 | n3908) & (n4119 | n3909); + assign n4210 = (n1758 | n3910) & (n1761 | n3911); + assign n4211 = (n1690 | n3908) & (n4124 | n3909); + assign n4212 = (n1733 | n3910) & (n1736 | n3911); + assign n4213 = (n1728 | n3908) & (n4123 | n3909); + assign n4214 = (n1722 | n3910) & (n1725 | n3911); + assign n4215 = (n4129 | n3904) & (n4131 | n3905); + assign n4216 = n1752 | n3907; + assign n4217 = n4216 & (n3894 | (n4204 & n4203)); + assign n4218 = n4217 & (n3740 | (n4206 & n4205)); + assign n4219 = ~n1862 & (n3895 | (n4209 & n4210)); + assign n4220 = n4219 & (n3743 | (n4212 & n4211)); + assign n4221 = n1552 & (n3737 | (n4214 & n4213)); + assign n4222 = (n1853 | n3908) & (n1679 | n3909); + assign n4223 = (n1847 | n3910) & (n1850 | n3911); + assign n4224 = (n1818 | n3908) & (n1682 | n3909); + assign n4225 = (n1812 | n3910) & (n1815 | n3911); + assign n4226 = (n1694 | n3908) & (n4122 | n3909); + assign n4227 = (n1838 | n3910) & (n1841 | n3911); + assign n4228 = (n1834 | n3908) & (n4121 | n3909); + assign n4229 = (n1828 | n3910) & (n1831 | n3911); + assign n4230 = (n1698 | n3908) & (n4126 | n3909); + assign n4231 = (n1803 | n3910) & (n1806 | n3911); + assign n4232 = (n1799 | n3908) & (n4125 | n3909); + assign n4233 = (n1793 | n3910) & (n1796 | n3911); + assign n4234 = (n4130 | n3904) & (n4132 | n3905); + assign n4235 = n1822 | n3907; + assign n4236 = n4235 & (n3894 | (n4223 & n4222)); + assign n4237 = n4236 & (n3740 | (n4225 & n4224)); + assign n4238 = ~n1861 & (n3895 | (n4228 & n4229)); + assign n4239 = n4238 & (n3743 | (n4231 & n4230)); + assign n4240 = n1552 & (n3737 | (n4233 & n4232)); + assign n4241 = n1787 | n3913; + assign n4242 = ~n3184 | ~n3918; + assign n4243 = n1857 | n3913; + assign n4244 = n1752 | n3913; + assign n4245 = n1822 | n3913; + assign n4246 = (n1790 | n3870) & (n1860 | n3877); + assign n4247 = (n1755 | n3884) & (n1825 | n3891); + assign n4248 = (n1917 | n3677) & (n1718 | ~n3898); + assign n4249 = (~Ni14 & n4300) | (n1552 & (Ni14 | n4300)); + assign n4250 = n3804 & (~Pi23 | n4249); + assign n4251 = n1507 | n3933; + assign n4252 = ~n794 | ~n3184; + assign n4253 = n1466 | n3933; + assign n4254 = n1509 | n3933; + assign n4255 = n1469 | n3933; + assign n4256 = (n1578 | n3870) & (n1602 | n3877); + assign n4257 = (n1566 | n3884) & (n1590 | n3891); + assign n4258 = (n1540 | n2254) & (Pi24 | n3801); + assign n4259 = (n4135 | n3940) & (n1364 | n3941); + assign n4260 = (n1519 | n3942) & (n1521 | n3943); + assign n4261 = (n4136 | n3940) & (n1373 | n3941); + assign n4262 = (n1531 | n3942) & (n1533 | n3943); + assign n4263 = (n1407 | n3940) & (n4138 | n3941); + assign n4264 = (n1515 | n3942) & (n1517 | n3943); + assign n4265 = (n4140 | n3940) & (n4141 | n3941); + assign n4266 = (n1511 | n3942) & (n1513 | n3943); + assign n4267 = (n1420 | n3940) & (n4143 | n3941); + assign n4268 = (n1527 | n3942) & (n1529 | n3943); + assign n4269 = (n4145 | n3940) & (n4146 | n3941); + assign n4270 = (n1523 | n3942) & (n1525 | n3943); + assign n4271 = (n1507 | n3938) & (n1509 | n3939); + assign n4272 = ~n1537 & (n3740 | (n4261 & n4262)); + assign n4273 = n4271 & n4272 & (Pi24 | n1536); + assign n4274 = ~n1538 & (n3895 | (n4265 & n4266)); + assign n4275 = n4274 & (n3743 | (n4268 & n4267)); + assign n4276 = n1460 & (n3737 | (n4270 & n4269)); + assign n4277 = (n4149 | n3940) & (n1382 | n3941); + assign n4278 = (n1479 | n3942) & (n1481 | n3943); + assign n4279 = (n4150 | n3940) & (n1391 | n3941); + assign n4280 = (n1491 | n3942) & (n1493 | n3943); + assign n4281 = (n1432 | n3940) & (n4152 | n3941); + assign n4282 = (n1475 | n3942) & (n1477 | n3943); + assign n4283 = (n4154 | n3940) & (n4155 | n3941); + assign n4284 = (n1471 | n3942) & (n1473 | n3943); + assign n4285 = (n1444 | n3940) & (n4157 | n3941); + assign n4286 = (n1487 | n3942) & (n1489 | n3943); + assign n4287 = (n4159 | n3940) & (n4160 | n3941); + assign n4288 = (n1483 | n3942) & (n1485 | n3943); + assign n4289 = (n1466 | n3938) & (n1469 | n3939); + assign n4290 = ~n1500 & (n3895 | (n4283 & n4284)); + assign n4291 = (n1505 | n2367) & (n1462 | n1544); + assign n4292 = n3804 & (Pi23 | n4249); + assign n4293 = n1507 | n3945; + assign n4294 = ~n796 | ~n3184; + assign n4295 = n1466 | n3945; + assign n4296 = n1509 | n3945; + assign n4297 = n1469 | n3945; + assign n4298 = (n1637 | n3870) & (n1661 | n3877); + assign n4299 = (n1625 | n3884) & (n1649 | n3891); + assign n4300 = n2025 | n2254; + assign n4301 = ~n2386 & (n2382 | n3894); + assign n4302 = (n2385 | n3740) & (n2381 | n2272); + assign n4303 = (n2380 | n3895) & (n2384 | n3743); + assign n4304 = (n2378 | n3740) & (n2374 | n2272); + assign n4305 = ~n2379 & n4304 & (n2375 | n3894); + assign n4306 = (n2373 | n3895) & (n2377 | n3743); + assign n4307 = n2371 & n4306 & (n2376 | n3737); + assign n4308 = (n2196 | n3949) & (~n1081_1 | n3951); + assign n4309 = n2105 & (~Pi25 | n2313); + assign n4310 = (n2228 | n3949) & (~n1235 | n3951); + assign n4311 = n2120 & (~Pi25 | n2277); + assign n4312 = (n2212 | n3949) & (~n1165 | n3951); + assign n4313 = n2113 & (~Pi25 | n2320); + assign n4314 = (n2244 | n3949) & (~n1273 | n3951); + assign n4315 = n2127 & (~Pi25 | n2284); + assign n4316 = (n2203 | n3870) & (n2235 | n3877); + assign n4317 = (n2219 | n3884) & (n2251 | n3891); + assign n4318 = (n2145 | n3870) & (n2173 | n3877); + assign n4319 = (n2159 | n3884) & (n2187 | n3891); + assign n4320 = (n2347 | n3847) & (n2140 | n3952); + assign n4321 = (n2348 | n3847) & (n2154 | n3952); + assign n4322 = (n2359 | n3847) & (n2132 | n3952); + assign n4323 = (n2362 | n3847) & (n2146 | n3952); + assign n4324 = (n2357 | n3847) & (n2188 | n3952); + assign n4325 = (n2358 | n3847) & (n2196 | n3952); + assign n4326 = (n2360 | n3847) & (n2204 | n3952); + assign n4327 = (n2361 | n3847) & (n2212 | n3952); + assign n4328 = ~n2363 & (n3740 | (n3955 & n4323)); + assign n4329 = n4328 & (n2272 | (n4324 & n3955)); + assign n4330 = ~n2364 & (n3895 | (n3955 & n4325)); + assign n4331 = n4330 & (n3737 | (n4327 & n3955)); + assign n4332 = (n2351 | n3847) & (n2136 | n3952); + assign n4333 = (n2354 | n3847) & (n2150 | n3952); + assign n4334 = (n2349 | n3847) & (n2192 | n3952); + assign n4335 = (n2350 | n3847) & (n2197 | n3952); + assign n4336 = (n2352 | n3847) & (n2208 | n3952); + assign n4337 = (n2353 | n3847) & (n2213 | n3952); + assign n4338 = ~n2355 & (n3740 | (n3955 & n4333)); + assign n4339 = n4338 & (n2272 | (n4334 & n3955)); + assign n4340 = ~n2356 & (n3895 | (n3955 & n4335)); + assign n4341 = n4340 & (n3737 | (n4337 & n3955)); + assign n4342 = ~n2365 & (~n3772 | (n3955 & n4320)); + assign n4343 = (n2327 | n3847) & (n2168 | n3952); + assign n4344 = (n2328 | n3847) & (n2182 | n3952); + assign n4345 = (n2339 | n3847) & (n2160 | n3952); + assign n4346 = (n2342 | n3847) & (n2174 | n3952); + assign n4347 = (n2337 | n3847) & (n2220 | n3952); + assign n4348 = (n2338 | n3847) & (n2228 | n3952); + assign n4349 = (n2340 | n3847) & (n2236 | n3952); + assign n4350 = (n2341 | n3847) & (n2244 | n3952); + assign n4351 = ~n2343 & (n3740 | (n3955 & n4346)); + assign n4352 = n4351 & (n2272 | (n4347 & n3955)); + assign n4353 = ~n2344 & (n3895 | (n3955 & n4348)); + assign n4354 = n4353 & (n3737 | (n4350 & n3955)); + assign n4355 = (n2331 | n3847) & (n2164 | n3952); + assign n4356 = (n2334 | n3847) & (n2178 | n3952); + assign n4357 = (n2329 | n3847) & (n2224 | n3952); + assign n4358 = (n2330 | n3847) & (n2229 | n3952); + assign n4359 = (n2332 | n3847) & (n2240 | n3952); + assign n4360 = (n2333 | n3847) & (n2245 | n3952); + assign n4361 = ~n2335 & (n3740 | (n3955 & n4356)); + assign n4362 = n4361 & (n2272 | (n4357 & n3955)); + assign n4363 = ~n2336 & (n3895 | (n3955 & n4358)); + assign n4364 = n4363 & (n3737 | (n4360 & n3955)); + assign n4365 = ~n2346 & (~n3772 | (n3955 & n4343)); + assign n4366 = (n2314 | n3895) & (n2318 | n3743); + assign n4367 = (n2298 | n3895) & (n2302 | n3743); + assign n4368 = (n2292 | ~n3772) & (n2294 | ~n2345); + assign n4369 = (n2278 | n3895) & (n2282 | n3743); + assign n4370 = (n2261 | n3895) & (n2265 | n3743); + assign n4371 = ~n3327 | n4698 | n4699; + assign n4372 = (~Pi20 & n2326) | (n2309 & (Pi20 | n2326)); + assign n4373 = (n2110 | n3870) & (n2124 | n3877); + assign n4374 = (n2117 | n3884) & (n2131 | n3891); + assign n4375 = (n2087 | n3870) & (n2097 | n3877); + assign n4376 = (n2092 | n3884) & (n2102 | n3891); + assign n4377 = (n1238 | n3958) & (~Pi23 | n3807); + assign n4378 = (n886 | n3958) & (~Pi24 | n3807); + assign n4379 = (Pi15 | n2414) & (n2413 | ~n3846); + assign n4380 = (n2851 | n3894) & (n2853 | n3740); + assign n4381 = n4380 & (n2857 | n2272); + assign n4382 = (n2858 | n3895) & (n2860 | n3743); + assign n4383 = n4382 & (n2861 | n3737); + assign n4384 = (n3046 | n3894) & (n2855 | n3740); + assign n4385 = n4384 & (n3094 | n2272); + assign n4386 = (n3091 | n3895) & (n2863 | n3743); + assign n4387 = n4386 & (n2864 | n3737); + assign n4388 = n2822 & n2542; + assign n4389 = n2820 & n2527; + assign n4390 = n2838 & n2592; + assign n4391 = n2836 & n2582; + assign n4392 = n2830 & n2568; + assign n4393 = n2828 & n2554; + assign n4394 = n2846 & n2616; + assign n4395 = n2844 & n2606; + assign n4396 = (n2826 | n3870) & (n2842 | n3877); + assign n4397 = (n2834 | n3884) & (n2850 | n3891); + assign n4398 = n2797 & n2457; + assign n4399 = n2809 & n2497; + assign n4400 = n2803 & n2480; + assign n4401 = n2815 & n2514; + assign n4402 = (n2800 | n3870) & (n2812 | n3877); + assign n4403 = (n2806 | n3884) & (n2818 | n3891); + assign n4404 = n2436 & n2440; + assign n4405 = n2464 & n2467; + assign n4406 = (n4405 | n3858) & (n2482 | n3860); + assign n4407 = (n2545 | n3858) & (n2721 | n3860); + assign n4408 = n2532 & n2535; + assign n4409 = (n4408 | n3858) & (n2718 | n3860); + assign n4410 = (n2571 | n3858) & (n2710 | n3860); + assign n4411 = n2558 & n2561; + assign n4412 = (n4411 | n3858) & (n2706 | n3860); + assign n4413 = (n3043 | n1923) & (n3054 | n3894); + assign n4414 = n2485 & n2488; + assign n4415 = n2502 & n2505; + assign n4416 = (n4415 | n3858) & (n2516 | n3860); + assign n4417 = (n2595 | n3858) & (n2743 | n3860); + assign n4418 = n2584 & n2587; + assign n4419 = (n4418 | n3858) & (n2740 | n3860); + assign n4420 = (n2619 | n3858) & (n2732 | n3860); + assign n4421 = n2608 & n2611; + assign n4422 = (n4421 | n3858) & (n2729 | n3860); + assign n4423 = (n3040 | n1923) & (n3047 | n3894); + assign n4424 = (n3094 | n1701) & (n3091 | n1702); + assign n4425 = n4424 & (n2859 | n3870); + assign n4426 = (n2862 | n3884) & (n2865 | n3891); + assign n4427 = (n3046 | n1701) & (n2496 | n1702); + assign n4428 = n4427 & (n2852 | n3870); + assign n4429 = (n2854 | n3884) & (n2856 | n3891); + assign n4430 = (n3061 | n3897) & (~n1543 | ~n3996); + assign n4431 = ~n2074 & (~n4430 | (~n2070 & ~n2868)); + assign n4432 = (n2546 | n3870) & (n2596 | n3877); + assign n4433 = (n2572 | n3884) & (n2620 | n3891); + assign n4434 = (n2460 | n3870) & (n2500 | n3877); + assign n4435 = (n2483 | n3884) & (n2517 | n3891); + assign n4436 = n2920 | n3924; + assign n4437 = n3138 | ~n3184; + assign n4438 = n2976 | n3924; + assign n4439 = n2892 | n3924; + assign n4440 = n2948 | n3924; + assign n4441 = (n3156 | n3870) & (n3174 | n3877); + assign n4442 = (n3147 | n3884) & (n3165 | n3891); + assign n4443 = n2456 | n3920; + assign n4444 = n3101 | ~n3184; + assign n4445 = n2496 | n3920; + assign n4446 = n2479 | n3920; + assign n4447 = n2513 | n3920; + assign n4448 = (n3119 | n3870) & (n3137 | n3877); + assign n4449 = (n3110 | n3884) & (n3128 | n3891); + assign n4450 = n2920 | n3929; + assign n4451 = n3062 | ~n3184; + assign n4452 = n2976 | n3929; + assign n4453 = n2892 | n3929; + assign n4454 = n2948 | n3929; + assign n4455 = (n3080 | n3870) & (n3100 | n3877); + assign n4456 = (n3071 | n3884) & (n3089 | n3891); + assign n4457 = n2921 | n3899; + assign n4458 = n2634 | ~n3184; + assign n4459 = n2977 | n3899; + assign n4460 = n2893 | n3899; + assign n4461 = n2949 | n3899; + assign n4462 = (n2918 | n3908) & (n2799 | n3909); + assign n4463 = (n2913 | n3910) & (n2915 | n3911); + assign n4464 = (n2890 | n3908) & (n2805 | n3909); + assign n4465 = (n2885 | n3910) & (n2887 | n3911); + assign n4466 = (n2825 | n3908) & (n4389 | n3909); + assign n4467 = (n2906 | n3910) & (n2908 | n3911); + assign n4468 = (n2903 | n3908) & (n4388 | n3909); + assign n4469 = (n2898 | n3910) & (n2900 | n3911); + assign n4470 = (n2833 | n3908) & (n4393 | n3909); + assign n4471 = (n2878 | n3910) & (n2880 | n3911); + assign n4472 = (n2875 | n3908) & (n4392 | n3909); + assign n4473 = (n2870 | n3910) & (n2872 | n3911); + assign n4474 = (n4398 | n3904) & (n4400 | n3905); + assign n4475 = n2893 | n3907; + assign n4476 = n4475 & (n3894 | (n4463 & n4462)); + assign n4477 = n4476 & (n3740 | (n4465 & n4464)); + assign n4478 = ~n2982 & (n3895 | (n4468 & n4469)); + assign n4479 = n4478 & (n3743 | (n4471 & n4470)); + assign n4480 = n2628 & (n3737 | (n4473 & n4472)); + assign n4481 = (n2974 | n3908) & (n2811 | n3909); + assign n4482 = (n2969 | n3910) & (n2971 | n3911); + assign n4483 = (n2946 | n3908) & (n2817 | n3909); + assign n4484 = (n2941 | n3910) & (n2943 | n3911); + assign n4485 = (n2841 | n3908) & (n4391 | n3909); + assign n4486 = (n2962 | n3910) & (n2964 | n3911); + assign n4487 = (n2959 | n3908) & (n4390 | n3909); + assign n4488 = (n2954 | n3910) & (n2956 | n3911); + assign n4489 = (n2849 | n3908) & (n4395 | n3909); + assign n4490 = (n2934 | n3910) & (n2936 | n3911); + assign n4491 = (n2931 | n3908) & (n4394 | n3909); + assign n4492 = (n2926 | n3910) & (n2928 | n3911); + assign n4493 = (n4399 | n3904) & (n4401 | n3905); + assign n4494 = n2949 | n3907; + assign n4495 = n4494 & (n3894 | (n4482 & n4481)); + assign n4496 = n4495 & (n3740 | (n4484 & n4483)); + assign n4497 = ~n2981 & (n3895 | (n4487 & n4488)); + assign n4498 = n4497 & (n3743 | (n4490 & n4489)); + assign n4499 = n2628 & (n3737 | (n4492 & n4491)); + assign n4500 = n2921 | n3913; + assign n4501 = n2624 | ~n3184; + assign n4502 = n2977 | n3913; + assign n4503 = n2893 | n3913; + assign n4504 = n2949 | n3913; + assign n4505 = (n2924 | n3870) & (n2980 | n3877); + assign n4506 = (n2896 | n3884) & (n2952 | n3891); + assign n4507 = (n3036 | n3677) & (n2867 | ~n3898); + assign n4508 = n3823 & (n813 | n3967); + assign n4509 = n2647 & (n3825 | n3967); + assign n4510 = n2646 & (n3822 | n3967); + assign n4511 = (n2750 | ~n4004) & (n3912 | ~n4003); + assign n4512 = (n2681 | n3935) & (n2682 | n1556); + assign n4513 = (n2679 | n3935) & (n2680 | n1556); + assign n4514 = (n2677 | n3935) & (n2678 | n1556); + assign n4515 = n2699 | ~n3184; + assign n4516 = n4515 & (n2675 | n3933); + assign n4517 = (n2658 | n3935) & (n2659 | n1556); + assign n4518 = (n2656 | n3935) & (n2657 | n1556); + assign n4519 = (n2654 | n3935) & (n2655 | n1556); + assign n4520 = n4515 & (n2652 | n3933); + assign n4521 = (n2687 | n3935) & (n2688 | n1556); + assign n4522 = (n2685 | n3935) & (n2686 | n1556); + assign n4523 = (n2683 | n3935) & (n2684 | n1556); + assign n4524 = n4515 & (n2676 | n3933); + assign n4525 = (n2664 | n3935) & (n2665 | n1556); + assign n4526 = (n2662 | n3935) & (n2663 | n1556); + assign n4527 = (n2660 | n3935) & (n2661 | n1556); + assign n4528 = n2653 | n3933; + assign n4529 = (n2727 | n3870) & (n2749 | n3877); + assign n4530 = (n2716 | n3884) & (n2738 | n3891); + assign n4531 = n2700 | n2704; + assign n4532 = n4531 & (n3327 | (n4530 & n4529)); + assign n4533 = (n4404 | n3940) & (n2459 | n3941); + assign n4534 = (n2681 | n3942) & (n2682 | n3943); + assign n4535 = (n4405 | n3940) & (n2482 | n3941); + assign n4536 = (n2687 | n3942) & (n2688 | n3943); + assign n4537 = (n2545 | n3940) & (n2721 | n3941); + assign n4538 = (n2679 | n3942) & (n2680 | n3943); + assign n4539 = (n4408 | n3940) & (n2718 | n3941); + assign n4540 = (n2677 | n3942) & (n2678 | n3943); + assign n4541 = (n2571 | n3940) & (n2710 | n3941); + assign n4542 = (n2685 | n3942) & (n2686 | n3943); + assign n4543 = (n4411 | n3940) & (n2706 | n3941); + assign n4544 = (n2683 | n3942) & (n2684 | n3943); + assign n4545 = (n2675 | n3938) & (n2676 | n3939); + assign n4546 = ~n2692 & (n3894 | (n4533 & n4534)); + assign n4547 = n4545 & n4546 & (Pi24 | n2691); + assign n4548 = ~n2693 & (n3895 | (n4539 & n4540)); + assign n4549 = n4548 & (n3743 | (n4542 & n4541)); + assign n4550 = n2639 & (n3737 | (n4544 & n4543)); + assign n4551 = (n4414 | n3940) & (n2499 | n3941); + assign n4552 = (n2658 | n3942) & (n2659 | n3943); + assign n4553 = (n4415 | n3940) & (n2516 | n3941); + assign n4554 = (n2664 | n3942) & (n2665 | n3943); + assign n4555 = (n2595 | n3940) & (n2743 | n3941); + assign n4556 = (n2656 | n3942) & (n2657 | n3943); + assign n4557 = (n4418 | n3940) & (n2740 | n3941); + assign n4558 = (n2654 | n3942) & (n2655 | n3943); + assign n4559 = (n2619 | n3940) & (n2732 | n3941); + assign n4560 = (n2662 | n3942) & (n2663 | n3943); + assign n4561 = (n4421 | n3940) & (n2729 | n3941); + assign n4562 = (n2660 | n3942) & (n2661 | n3943); + assign n4563 = (n2652 | n3938) & (n2653 | n3939); + assign n4564 = ~n2669 & (n3894 | (n4551 & n4552)); + assign n4565 = ~n2670 & (n3895 | (n4557 & n4558)); + assign n4566 = (n2750 | ~n4009) & (n3912 | ~n4008); + assign n4567 = (n2681 | n3947) & (n2682 | n1615); + assign n4568 = (n2679 | n3947) & (n2680 | n1615); + assign n4569 = (n2677 | n3947) & (n2678 | n1615); + assign n4570 = n2754 | ~n3184; + assign n4571 = n4570 & (n2675 | n3945); + assign n4572 = (n2658 | n3947) & (n2659 | n1615); + assign n4573 = (n2656 | n3947) & (n2657 | n1615); + assign n4574 = (n2654 | n3947) & (n2655 | n1615); + assign n4575 = n4570 & (n2652 | n3945); + assign n4576 = (n2687 | n3947) & (n2688 | n1615); + assign n4577 = (n2685 | n3947) & (n2686 | n1615); + assign n4578 = (n2683 | n3947) & (n2684 | n1615); + assign n4579 = n4570 & (n2676 | n3945); + assign n4580 = (n2664 | n3947) & (n2665 | n1615); + assign n4581 = (n2662 | n3947) & (n2663 | n1615); + assign n4582 = (n2660 | n3947) & (n2661 | n1615); + assign n4583 = n2653 | n3945; + assign n4584 = (n2774 | n3870) & (n2792 | n3877); + assign n4585 = (n2765 | n3884) & (n2783 | n3891); + assign n4586 = n2704 | n2755; + assign n4587 = n4586 & (n3327 | (n4585 & n4584)); + assign n4588 = (n2636 | n3677) & (n2621 | ~n3898); + assign n4589 = ~n3176 & (n2066 | n2697) & ~n3177; + assign n4590 = (~Pi26 | n3971) & (~Ni40 | n3970); + assign n4591 = (~Pi27 | n3971) & (~Ni41 | n3970); + assign n4592 = (n3345 | n2372) & (n3352 | n1314); + assign n4593 = (n3365 | n2372) & (n3372 | n1314); + assign n4594 = (n3397 | n2372) & (n3403 | n1314); + assign n4595 = (n3410 | n2372) & (n3417 | n1314); + assign n4596 = (n3425 | n2372) & (n3430 | n1314); + assign n4597 = (n3437 | n2372) & (n3444 | n1314); + assign n4598 = n3476 | n1929; + assign n4599 = n4598 & (n3894 | (n4592 & n3472)); + assign n4600 = ~n3479 & (n3895 | (n3472 & n4595)); + assign n4601 = ~n3773 & (n3737 | (n3472 & n4597)); + assign n4602 = (n3379 | n2372) & (n3381 | n1314); + assign n4603 = (n3386 | n2372) & (n3388 | n1314); + assign n4604 = (n3450 | n2372) & (n3452 | n1314); + assign n4605 = (n3454 | n2372) & (n3456 | n1314); + assign n4606 = (n3461 | n2372) & (n3463 | n1314); + assign n4607 = (n3465 | n2372) & (n3467 | n1314); + assign n4608 = n3473 | n1929; + assign n4609 = (n3420 | n3870) & (n3459 | n3877); + assign n4610 = (n3447 | n3884) & (n3470 | n3891); + assign n4611 = (n3358 | n3870) & (n3384 | n3877); + assign n4612 = (n3377 | n3884) & (n3391 | n3891); + assign n4613 = (n3484 | n2372) & (n3485 | n1314); + assign n4614 = (n3489 | n2372) & (n3490 | n1314); + assign n4615 = (n3504 | n2372) & (n3505 | n1314); + assign n4616 = (n3506 | n2372) & (n3507 | n1314); + assign n4617 = (n3511 | n2372) & (n3512 | n1314); + assign n4618 = (n3513 | n2372) & (n3514 | n1314); + assign n4619 = n3535 | n1929; + assign n4620 = n4619 & (n3894 | (n4613 & n3472)); + assign n4621 = ~n3538 & (n3895 | (n3472 & n4616)); + assign n4622 = ~n3773 & (n3737 | (n3472 & n4618)); + assign n4623 = (n3494 | n2372) & (n3495 | n1314); + assign n4624 = (n3499 | n2372) & (n3500 | n1314); + assign n4625 = (n3518 | n2372) & (n3519 | n1314); + assign n4626 = (n3520 | n2372) & (n3521 | n1314); + assign n4627 = (n3525 | n2372) & (n3526 | n1314); + assign n4628 = (n3527 | n2372) & (n3528 | n1314); + assign n4629 = n3532 | n1929; + assign n4630 = (n3510 | n3870) & (n3524 | n3877); + assign n4631 = (n3517 | n3884) & (n3531 | n3891); + assign n4632 = (n3488 | n3870) & (n3498 | n3877); + assign n4633 = (n3493 | n3884) & (n3503 | n3891); + assign n4634 = (n3300 | n3618) & (n3551 | n1929); + assign n4635 = (n3302 | n3618) & (n3553 | n1929); + assign n4636 = (n3316 | n3618) & (n3575 | n1929); + assign n4637 = (n3318 | n3618) & (n3579 | n1929); + assign n4638 = (n3319 | n3618) & (n3586 | n1929); + assign n4639 = (n3321 | n3618) & (n3590 | n1929); + assign n4640 = ~n3654 & (n3895 | (n3621 & n4637)); + assign n4641 = ~n3655 & (n3737 | (n3621 & n4639)); + assign n4642 = (n3310 | n3618) & (n3588 | n1929); + assign n4643 = (n3312 | n3618) & (n3592 | n1929); + assign n4644 = (n3650 | n2272) & (n3651 | n3895); + assign n4645 = (n3645 | n3978) & (n3649 | n3979); + assign n4646 = (n3234 | n3618) & (n3567 | n1929); + assign n4647 = (n3240 | n3618) & (n3569 | n1929); + assign n4648 = (n3268 | n3618) & (n3597 | n1929); + assign n4649 = (n3273 | n3618) & (n3601 | n1929); + assign n4650 = (n3277 | n3618) & (n3608 | n1929); + assign n4651 = (n3282 | n3618) & (n3612 | n1929); + assign n4652 = ~n3638 & (n3895 | (n3621 & n4649)); + assign n4653 = ~n3639 & (n3737 | (n3621 & n4651)); + assign n4654 = (n3256 | n3618) & (n3610 | n1929); + assign n4655 = (n3261 | n3618) & (n3614 | n1929); + assign n4656 = (n3633 | n2272) & (n3634 | n3895); + assign n4657 = (n3628 | n3978) & (n3632 | n3979); + assign n4658 = (n3584 | n3870) & (n3606 | n3877); + assign n4659 = (n3595 | n3884) & (n3617 | n3891); + assign n4660 = (n3548 | n3870) & (n3565 | n3877); + assign n4661 = (n3557 | n3884) & (n3573 | n3891); + assign n4662 = n3912 | n1543 | n4744 | n4745; + assign n4663 = n2074 | n3669 | n795 | ~Ni10; + assign n4664 = n3768 | n3669 | n3767; + assign n4665 = Ni31 & (~Ni30 | ~Ni5 | Ni4); + assign n4666 = (~Pi15 & n1312) | (n1305 & (Pi15 | n1312)); + assign n4667 = ~Pi17 & (n1296 | n1298 | ~n4089); + assign n4668 = ~n4667 & (~Pi17 | (n4090 & n4091)); + assign n4669 = (~n3327 & n4668) | (n4666 & (n3327 | n4668)); + assign n4670 = n4110 & ~n3892 & n4109; + assign n4671 = ~n2074 & (n4670 | (n3892 & n4668)); + assign n4672 = ~Ni7 & (n4671 | (n2074 & n4669)); + assign n4673 = ~n3707 & (n4672 | (Ni7 & n4669)); + assign n4674 = Ni14 & n4258 & n3802; + assign n4675 = n4179 & ~Ni14 & n4178; + assign n4676 = Ni14 & n4186 & n4185; + assign n4677 = n1943 | ~n4148 | n1941 | n1942 | ~n1362 | ~n1536 | n1939 | n1940; + assign n4678 = n1935 | ~n4162 | n1933 | n1934 | ~n1362 | ~n1498 | n1931 | n1932; + assign n4679 = n1787 | n3906; + assign n4680 = n4679 & n4221 & n4220 & n4218 & ~Pi15 & n4215; + assign n4681 = n1857 | n3906; + assign n4682 = Pi15 & n4239 & n4240 & n4237 & n4234 & n4681; + assign n4683 = Pi17 & (~n4133 | ~n4134); + assign n4684 = n4165 & n4164 & ~Pi17 & n1362; + assign n4685 = Pi17 & n4167 & n4168 & n1362; + assign n4686 = n4248 & Ni10 & (Ni11 | n1865); + assign n4687 = n4170 & ~Pi17 & n4169; + assign n4688 = n2383 | n3737; + assign n4689 = n4688 & n4303 & n4302 & n4301 & ~Pi15 & n2371; + assign n4690 = n18 | ~Ni34; + assign n4691 = n1539 | Ni34 | n18; + assign n4692 = n4317 & ~Pi17 & n4316; + assign n4693 = Pi17 & n4319 & n4318; + assign n4694 = Pi20 & (~n4339 | ~n4341); + assign n4695 = ~n4694 & (Pi20 | (n4329 & n4331)); + assign n4696 = Pi20 & (~n4362 | ~n4364); + assign n4697 = ~n4696 & (Pi20 | (n4352 & n4354)); + assign n4698 = n4695 & ~Pi15 & n4342; + assign n4699 = Pi15 & n4365 & n4697; + assign n4700 = n4692 | n4693 | n3327 | Ni10; + assign n4701 = ~Pi17 & (~n4373 | ~n4374); + assign n4702 = n2393 & n4377 & n2390; + assign n4703 = ~n2393 & (n3808 | (~Pi23 & n2392)); + assign n4704 = n2393 & n4378 & n2400; + assign n4705 = ~n2393 & (n3809 | (~Pi24 & n2401)); + assign n4706 = ~n2393 & (Ni33 | n886) & n2401; + assign n4707 = ~Ni44 & ~Ni39 & (~n3733 | Ni42); + assign n4708 = ~n4707 & (~Ni44 | ~n923 | ~Ni39); + assign n4709 = Pi21 | n3818; + assign n4710 = (~Pi26 & ~n2648) | (~n2644 & (Pi26 | ~n2648)); + assign n4711 = ~Pi21 & (~n2623 | (~Pi26 & Ni32)); + assign n4712 = (Pi26 & ~n2648) | (~n2644 & (~Pi26 | ~n2648)); + assign n4713 = n4442 & ~Ni14 & n4441; + assign n4714 = n3059 | ~n4413 | n3057 | n3058 | ~n2423 | ~n2691 | n3055 | n3056; + assign n4715 = n3052 | ~n4423 | n3050 | n3051 | ~n2423 | ~n2668 | n3048 | n3049; + assign n4716 = n2921 | n3906; + assign n4717 = n4716 & n4480 & n4479 & n4477 & ~Pi15 & n4474; + assign n4718 = n2977 | n3906; + assign n4719 = Pi15 & n4498 & n4499 & n4496 & n4493 & n4718; + assign n4720 = Pi17 & (~n4402 | ~n4403); + assign n4721 = n4426 & n4425 & ~Pi17 & n2423; + assign n4722 = Pi17 & n4428 & n4429 & n2423; + assign n4723 = n4507 & Ni10 & (Ni11 | n2985); + assign n4724 = n2703 | n2701 | n2702; + assign n4725 = n4433 & ~Pi17 & n4432; + assign n4726 = ~Pi20 & n3968 & (n3183 | ~Ni39); + assign n4727 = n3968 & Pi20 & (Ni39 | n3183); + assign n4728 = ~n2393 | ~Ni40; + assign n4729 = (n3830 & (~n2393 | ~n4012)) | (n2393 & ~n4012); + assign n4730 = ~n2393 | ~Ni41; + assign n4731 = (n3833 & (~n2393 | ~n4016)) | (n2393 & ~n4016); + assign n4732 = ~Pi21 & (n797 | (~n1539 & n3186)); + assign n4733 = Pi20 & (n3652 | n3653 | ~n4644); + assign n4734 = ~n4733 & (Pi20 | (n4640 & n4641)); + assign n4735 = Pi20 & (n3636 | n3637 | ~n4656); + assign n4736 = ~n4735 & (Pi20 | (n4652 & n4653)); + assign n4737 = n4734 & ~Pi15 & n4645; + assign n4738 = Pi15 & n4657 & n4736; + assign n4739 = n4659 & ~Pi17 & n4658; + assign n4740 = ~Ni10 & (n4737 | n4738); + assign n4741 = n4601 & n4600 & n4599 & ~n3478 & ~Pi15 & ~n3477; + assign n4742 = n4610 & ~Pi17 & n4609; + assign n4743 = Pi17 & n4612 & n4611; + assign n4744 = ~Ni10 & (n4741 | (Pi15 & n4023)); + assign n4745 = Ni10 & (n4742 | n4743); + assign n4746 = n4622 & n4621 & n4620 & ~n3537 & ~Pi15 & ~n3536; + assign n4747 = n4631 & ~Pi17 & n4630; + assign n4748 = Pi17 & n4633 & n4632; + assign n4749 = ~Ni10 & (n4746 | (Pi15 & n4028)); + assign n4750 = n4775 | ~Ni14 | ~Ni12; + assign n4751 = ~Ni4 & (~Ni6 | ~Ni5 | ~n3700); + assign n4752 = ~Ni5 | ~Ni31 | ~Ni6; + assign n4753 = n4752 & Ni4 & (n2418 | n3980); + assign n4754 = Ni3 & (n4753 | (~Ni4 & ~n4752)); + assign n4755 = ~Ni2 & (n4754 | (~Ni3 & n4034)); + assign n4756 = Ni6 & (Ni2 | (~Ni31 & Ni3)); + assign n4757 = Ni12 & (n3707 | (~n3723 & n3727)); + assign n4758 = Pi20 & (n806 | n3745 | n3755); + assign n4759 = Ni42 & (~Ni44 | n3732) & ~Ni39; + assign n4760 = Pi27 | n3985; + assign n4761 = ~Pi27 | Pi26 | n3985; + assign n4762 = Pi24 | n3986; + assign n4763 = ~Pi24 | Pi23 | n3986; + assign n4764 = ~Ni4 & (n2416 | n3973); + assign n4765 = Ni4 & (Ni33 | n3980); + assign n4766 = Ni33 & ~n1352; + assign n4767 = ~Ni33 & ~n1352; + assign n4768 = n698 | n2433; + assign n4769 = ~n674 | Ni41; + assign n4770 = ~n675 | Ni41; + assign n4771 = ~Ni33 | n3201; + assign n4772 = n1540 & n1463; + assign n4773 = n1546 | n1547 | n1548 | ~n4291; + assign n4774 = n3984 | n4726 | n4727; + assign n4775 = n3669 & Pi27; + assign n1085 = P__cmxcl_0; + always @ (posedge clock) begin + Ni48 <= n931_1; + Ni47 <= n936; + Ni46 <= n941_1; + Ni45 <= n946_1; + Ni44 <= n951_1; + Ni43 <= n956_1; + Ni42 <= n961_1; + Ni41 <= n966_1; + Ni40 <= n971; + Ni39 <= n976_1; + Ni38 <= n981_1; + Ni37 <= n986; + Ni36 <= n991_1; + Ni35 <= n996_1; + Ni34 <= n1001; + Ni33 <= n1006_1; + Ni32 <= n1011_1; + Ni31 <= n1016_1; + Ni30 <= n1021; + n18 <= n1026_1; + Ni14 <= n1031_1; + Ni13 <= n1036; + Ni12 <= n1041_1; + Ni11 <= n1046_1; + Ni10 <= n1051; + Ni9 <= n1056_1; + Ni8 <= n1061; + Ni7 <= n1066_1; + Ni6 <= n1071_1; + Ni5 <= n1076; + Ni4 <= n1081; + Ni3 <= n1085; + Ni2 <= n1090_1; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/des/des.v b/openfpga_flow/benchmarks/MCNC_Verilog/des/des.v new file mode 100644 index 000000000..e4f2fab16 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/des/des.v @@ -0,0 +1,1822 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 09:56:12 2019 + +module des ( + Preset_0_, Poutreg_63_, Poutreg_62_, Poutreg_61_, Poutreg_60_, + Poutreg_59_, Poutreg_58_, Poutreg_57_, Poutreg_56_, Poutreg_55_, + Poutreg_54_, Poutreg_53_, Poutreg_52_, Poutreg_51_, Poutreg_50_, + Poutreg_49_, Poutreg_48_, Poutreg_47_, Poutreg_46_, Poutreg_45_, + Poutreg_44_, Poutreg_43_, Poutreg_42_, Poutreg_41_, Poutreg_40_, + Poutreg_39_, Poutreg_38_, Poutreg_37_, Poutreg_36_, Poutreg_35_, + Poutreg_34_, Poutreg_33_, Poutreg_32_, Poutreg_31_, Poutreg_30_, + Poutreg_29_, Poutreg_28_, Poutreg_27_, Poutreg_26_, Poutreg_25_, + Poutreg_24_, Poutreg_23_, Poutreg_22_, Poutreg_21_, Poutreg_20_, + Poutreg_19_, Poutreg_18_, Poutreg_17_, Poutreg_16_, Poutreg_15_, + Poutreg_14_, Poutreg_13_, Poutreg_12_, Poutreg_11_, Poutreg_10_, + Poutreg_9_, Poutreg_8_, Poutreg_7_, Poutreg_6_, Poutreg_5_, Poutreg_4_, + Poutreg_3_, Poutreg_2_, Poutreg_1_, Poutreg_0_, Pload_key_0_, + Pinreg_55_, Pinreg_54_, Pinreg_53_, Pinreg_52_, Pinreg_51_, Pinreg_50_, + Pinreg_49_, Pinreg_48_, Pinreg_47_, Pinreg_46_, Pinreg_45_, Pinreg_44_, + Pinreg_43_, Pinreg_42_, Pinreg_41_, Pinreg_40_, Pinreg_39_, Pinreg_38_, + Pinreg_37_, Pinreg_36_, Pinreg_35_, Pinreg_34_, Pinreg_33_, Pinreg_32_, + Pinreg_31_, Pinreg_30_, Pinreg_29_, Pinreg_28_, Pinreg_27_, Pinreg_26_, + Pinreg_25_, Pinreg_24_, Pinreg_23_, Pinreg_22_, Pinreg_21_, Pinreg_20_, + Pinreg_19_, Pinreg_18_, Pinreg_17_, Pinreg_16_, Pinreg_15_, Pinreg_14_, + Pinreg_13_, Pinreg_12_, Pinreg_11_, Pinreg_10_, Pinreg_9_, Pinreg_8_, + Pinreg_7_, Pinreg_6_, Pinreg_5_, Pinreg_4_, Pinreg_3_, Pinreg_2_, + Pinreg_1_, Pinreg_0_, Pencrypt_mode_0_, Pencrypt_0_, Pdata_in_7_, + Pdata_in_6_, Pdata_in_5_, Pdata_in_4_, Pdata_in_3_, Pdata_in_2_, + Pdata_in_1_, Pdata_in_0_, Pdata_63_, Pdata_62_, Pdata_61_, Pdata_60_, + Pdata_59_, Pdata_58_, Pdata_57_, Pdata_56_, Pdata_55_, Pdata_54_, + Pdata_53_, Pdata_52_, Pdata_51_, Pdata_50_, Pdata_49_, Pdata_48_, + Pdata_47_, Pdata_46_, Pdata_45_, Pdata_44_, Pdata_43_, Pdata_42_, + Pdata_41_, Pdata_40_, Pdata_39_, Pdata_38_, Pdata_37_, Pdata_36_, + Pdata_35_, Pdata_34_, Pdata_33_, Pdata_32_, Pdata_31_, Pdata_30_, + Pdata_29_, Pdata_28_, Pdata_27_, Pdata_26_, Pdata_25_, Pdata_24_, + Pdata_23_, Pdata_22_, Pdata_21_, Pdata_20_, Pdata_19_, Pdata_18_, + Pdata_17_, Pdata_16_, Pdata_15_, Pdata_14_, Pdata_13_, Pdata_12_, + Pdata_11_, Pdata_10_, Pdata_9_, Pdata_8_, Pdata_7_, Pdata_6_, Pdata_5_, + Pdata_4_, Pdata_3_, Pdata_2_, Pdata_1_, Pdata_0_, Pcount_3_, Pcount_2_, + Pcount_1_, Pcount_0_, PD_27_, PD_26_, PD_25_, PD_24_, PD_23_, PD_22_, + PD_21_, PD_20_, PD_19_, PD_18_, PD_17_, PD_16_, PD_15_, PD_14_, PD_13_, + PD_12_, PD_11_, PD_10_, PD_9_, PD_8_, PD_7_, PD_6_, PD_5_, PD_4_, + PD_3_, PD_2_, PD_1_, PD_0_, PC_27_, PC_26_, PC_25_, PC_24_, PC_23_, + PC_22_, PC_21_, PC_20_, PC_19_, PC_18_, PC_17_, PC_16_, PC_15_, PC_14_, + PC_13_, PC_12_, PC_11_, PC_10_, PC_9_, PC_8_, PC_7_, PC_6_, PC_5_, + PC_4_, PC_3_, PC_2_, PC_1_, PC_0_, + Poutreg_new_63_, Poutreg_new_62_, Poutreg_new_61_, Poutreg_new_60_, + Poutreg_new_59_, Poutreg_new_58_, Poutreg_new_57_, Poutreg_new_56_, + Poutreg_new_55_, Poutreg_new_54_, Poutreg_new_53_, Poutreg_new_52_, + Poutreg_new_51_, Poutreg_new_50_, Poutreg_new_49_, Poutreg_new_48_, + Poutreg_new_47_, Poutreg_new_46_, Poutreg_new_45_, Poutreg_new_44_, + Poutreg_new_43_, Poutreg_new_42_, Poutreg_new_41_, Poutreg_new_40_, + Poutreg_new_39_, Poutreg_new_38_, Poutreg_new_37_, Poutreg_new_36_, + Poutreg_new_35_, Poutreg_new_34_, Poutreg_new_33_, Poutreg_new_32_, + Poutreg_new_31_, Poutreg_new_30_, Poutreg_new_29_, Poutreg_new_28_, + Poutreg_new_27_, Poutreg_new_26_, Poutreg_new_25_, Poutreg_new_24_, + Poutreg_new_23_, Poutreg_new_22_, Poutreg_new_21_, Poutreg_new_20_, + Poutreg_new_19_, Poutreg_new_18_, Poutreg_new_17_, Poutreg_new_16_, + Poutreg_new_15_, Poutreg_new_14_, Poutreg_new_13_, Poutreg_new_12_, + Poutreg_new_11_, Poutreg_new_10_, Poutreg_new_9_, Poutreg_new_8_, + Poutreg_new_7_, Poutreg_new_6_, Poutreg_new_5_, Poutreg_new_4_, + Poutreg_new_3_, Poutreg_new_2_, Poutreg_new_1_, Poutreg_new_0_, + Pinreg_new_55_, Pinreg_new_54_, Pinreg_new_53_, Pinreg_new_52_, + Pinreg_new_51_, Pinreg_new_50_, Pinreg_new_49_, Pinreg_new_48_, + Pinreg_new_47_, Pinreg_new_46_, Pinreg_new_45_, Pinreg_new_44_, + Pinreg_new_43_, Pinreg_new_42_, Pinreg_new_41_, Pinreg_new_40_, + Pinreg_new_39_, Pinreg_new_38_, Pinreg_new_37_, Pinreg_new_36_, + Pinreg_new_35_, Pinreg_new_34_, Pinreg_new_33_, Pinreg_new_32_, + Pinreg_new_31_, Pinreg_new_30_, Pinreg_new_29_, Pinreg_new_28_, + Pinreg_new_27_, Pinreg_new_26_, Pinreg_new_25_, Pinreg_new_24_, + Pinreg_new_23_, Pinreg_new_22_, Pinreg_new_21_, Pinreg_new_20_, + Pinreg_new_19_, Pinreg_new_18_, Pinreg_new_17_, Pinreg_new_16_, + Pinreg_new_15_, Pinreg_new_14_, Pinreg_new_13_, Pinreg_new_12_, + Pinreg_new_11_, Pinreg_new_10_, Pinreg_new_9_, Pinreg_new_8_, + Pinreg_new_7_, Pinreg_new_6_, Pinreg_new_5_, Pinreg_new_4_, + Pinreg_new_3_, Pinreg_new_2_, Pinreg_new_1_, Pinreg_new_0_, + Pencrypt_mode_new_0_, Pdata_new_63_, Pdata_new_62_, Pdata_new_61_, + Pdata_new_60_, Pdata_new_59_, Pdata_new_58_, Pdata_new_57_, + Pdata_new_56_, Pdata_new_55_, Pdata_new_54_, Pdata_new_53_, + Pdata_new_52_, Pdata_new_51_, Pdata_new_50_, Pdata_new_49_, + Pdata_new_48_, Pdata_new_47_, Pdata_new_46_, Pdata_new_45_, + Pdata_new_44_, Pdata_new_43_, Pdata_new_42_, Pdata_new_41_, + Pdata_new_40_, Pdata_new_39_, Pdata_new_38_, Pdata_new_37_, + Pdata_new_36_, Pdata_new_35_, Pdata_new_34_, Pdata_new_33_, + Pdata_new_32_, Pdata_new_31_, Pdata_new_30_, Pdata_new_29_, + Pdata_new_28_, Pdata_new_27_, Pdata_new_26_, Pdata_new_25_, + Pdata_new_24_, Pdata_new_23_, Pdata_new_22_, Pdata_new_21_, + Pdata_new_20_, Pdata_new_19_, Pdata_new_18_, Pdata_new_17_, + Pdata_new_16_, Pdata_new_15_, Pdata_new_14_, Pdata_new_13_, + Pdata_new_12_, Pdata_new_11_, Pdata_new_10_, Pdata_new_9_, + Pdata_new_8_, Pdata_new_7_, Pdata_new_6_, Pdata_new_5_, Pdata_new_4_, + Pdata_new_3_, Pdata_new_2_, Pdata_new_1_, Pdata_new_0_, Pcount_new_3_, + Pcount_new_2_, Pcount_new_1_, Pcount_new_0_, PD_new_27_, PD_new_26_, + PD_new_25_, PD_new_24_, PD_new_23_, PD_new_22_, PD_new_21_, PD_new_20_, + PD_new_19_, PD_new_18_, PD_new_17_, PD_new_16_, PD_new_15_, PD_new_14_, + PD_new_13_, PD_new_12_, PD_new_11_, PD_new_10_, PD_new_9_, PD_new_8_, + PD_new_7_, PD_new_6_, PD_new_5_, PD_new_4_, PD_new_3_, PD_new_2_, + PD_new_1_, PD_new_0_, PC_new_27_, PC_new_26_, PC_new_25_, PC_new_24_, + PC_new_23_, PC_new_22_, PC_new_21_, PC_new_20_, PC_new_19_, PC_new_18_, + PC_new_17_, PC_new_16_, PC_new_15_, PC_new_14_, PC_new_13_, PC_new_12_, + PC_new_11_, PC_new_10_, PC_new_9_, PC_new_8_, PC_new_7_, PC_new_6_, + PC_new_5_, PC_new_4_, PC_new_3_, PC_new_2_, PC_new_1_, PC_new_0_ ); + input Preset_0_, Poutreg_63_, Poutreg_62_, Poutreg_61_, Poutreg_60_, + Poutreg_59_, Poutreg_58_, Poutreg_57_, Poutreg_56_, Poutreg_55_, + Poutreg_54_, Poutreg_53_, Poutreg_52_, Poutreg_51_, Poutreg_50_, + Poutreg_49_, Poutreg_48_, Poutreg_47_, Poutreg_46_, Poutreg_45_, + Poutreg_44_, Poutreg_43_, Poutreg_42_, Poutreg_41_, Poutreg_40_, + Poutreg_39_, Poutreg_38_, Poutreg_37_, Poutreg_36_, Poutreg_35_, + Poutreg_34_, Poutreg_33_, Poutreg_32_, Poutreg_31_, Poutreg_30_, + Poutreg_29_, Poutreg_28_, Poutreg_27_, Poutreg_26_, Poutreg_25_, + Poutreg_24_, Poutreg_23_, Poutreg_22_, Poutreg_21_, Poutreg_20_, + Poutreg_19_, Poutreg_18_, Poutreg_17_, Poutreg_16_, Poutreg_15_, + Poutreg_14_, Poutreg_13_, Poutreg_12_, Poutreg_11_, Poutreg_10_, + Poutreg_9_, Poutreg_8_, Poutreg_7_, Poutreg_6_, Poutreg_5_, Poutreg_4_, + Poutreg_3_, Poutreg_2_, Poutreg_1_, Poutreg_0_, Pload_key_0_, + Pinreg_55_, Pinreg_54_, Pinreg_53_, Pinreg_52_, Pinreg_51_, Pinreg_50_, + Pinreg_49_, Pinreg_48_, Pinreg_47_, Pinreg_46_, Pinreg_45_, Pinreg_44_, + Pinreg_43_, Pinreg_42_, Pinreg_41_, Pinreg_40_, Pinreg_39_, Pinreg_38_, + Pinreg_37_, Pinreg_36_, Pinreg_35_, Pinreg_34_, Pinreg_33_, Pinreg_32_, + Pinreg_31_, Pinreg_30_, Pinreg_29_, Pinreg_28_, Pinreg_27_, Pinreg_26_, + Pinreg_25_, Pinreg_24_, Pinreg_23_, Pinreg_22_, Pinreg_21_, Pinreg_20_, + Pinreg_19_, Pinreg_18_, Pinreg_17_, Pinreg_16_, Pinreg_15_, Pinreg_14_, + Pinreg_13_, Pinreg_12_, Pinreg_11_, Pinreg_10_, Pinreg_9_, Pinreg_8_, + Pinreg_7_, Pinreg_6_, Pinreg_5_, Pinreg_4_, Pinreg_3_, Pinreg_2_, + Pinreg_1_, Pinreg_0_, Pencrypt_mode_0_, Pencrypt_0_, Pdata_in_7_, + Pdata_in_6_, Pdata_in_5_, Pdata_in_4_, Pdata_in_3_, Pdata_in_2_, + Pdata_in_1_, Pdata_in_0_, Pdata_63_, Pdata_62_, Pdata_61_, Pdata_60_, + Pdata_59_, Pdata_58_, Pdata_57_, Pdata_56_, Pdata_55_, Pdata_54_, + Pdata_53_, Pdata_52_, Pdata_51_, Pdata_50_, Pdata_49_, Pdata_48_, + Pdata_47_, Pdata_46_, Pdata_45_, Pdata_44_, Pdata_43_, Pdata_42_, + Pdata_41_, Pdata_40_, Pdata_39_, Pdata_38_, Pdata_37_, Pdata_36_, + Pdata_35_, Pdata_34_, Pdata_33_, Pdata_32_, Pdata_31_, Pdata_30_, + Pdata_29_, Pdata_28_, Pdata_27_, Pdata_26_, Pdata_25_, Pdata_24_, + Pdata_23_, Pdata_22_, Pdata_21_, Pdata_20_, Pdata_19_, Pdata_18_, + Pdata_17_, Pdata_16_, Pdata_15_, Pdata_14_, Pdata_13_, Pdata_12_, + Pdata_11_, Pdata_10_, Pdata_9_, Pdata_8_, Pdata_7_, Pdata_6_, Pdata_5_, + Pdata_4_, Pdata_3_, Pdata_2_, Pdata_1_, Pdata_0_, Pcount_3_, Pcount_2_, + Pcount_1_, Pcount_0_, PD_27_, PD_26_, PD_25_, PD_24_, PD_23_, PD_22_, + PD_21_, PD_20_, PD_19_, PD_18_, PD_17_, PD_16_, PD_15_, PD_14_, PD_13_, + PD_12_, PD_11_, PD_10_, PD_9_, PD_8_, PD_7_, PD_6_, PD_5_, PD_4_, + PD_3_, PD_2_, PD_1_, PD_0_, PC_27_, PC_26_, PC_25_, PC_24_, PC_23_, + PC_22_, PC_21_, PC_20_, PC_19_, PC_18_, PC_17_, PC_16_, PC_15_, PC_14_, + PC_13_, PC_12_, PC_11_, PC_10_, PC_9_, PC_8_, PC_7_, PC_6_, PC_5_, + PC_4_, PC_3_, PC_2_, PC_1_, PC_0_; + output Poutreg_new_63_, Poutreg_new_62_, Poutreg_new_61_, Poutreg_new_60_, + Poutreg_new_59_, Poutreg_new_58_, Poutreg_new_57_, Poutreg_new_56_, + Poutreg_new_55_, Poutreg_new_54_, Poutreg_new_53_, Poutreg_new_52_, + Poutreg_new_51_, Poutreg_new_50_, Poutreg_new_49_, Poutreg_new_48_, + Poutreg_new_47_, Poutreg_new_46_, Poutreg_new_45_, Poutreg_new_44_, + Poutreg_new_43_, Poutreg_new_42_, Poutreg_new_41_, Poutreg_new_40_, + Poutreg_new_39_, Poutreg_new_38_, Poutreg_new_37_, Poutreg_new_36_, + Poutreg_new_35_, Poutreg_new_34_, Poutreg_new_33_, Poutreg_new_32_, + Poutreg_new_31_, Poutreg_new_30_, Poutreg_new_29_, Poutreg_new_28_, + Poutreg_new_27_, Poutreg_new_26_, Poutreg_new_25_, Poutreg_new_24_, + Poutreg_new_23_, Poutreg_new_22_, Poutreg_new_21_, Poutreg_new_20_, + Poutreg_new_19_, Poutreg_new_18_, Poutreg_new_17_, Poutreg_new_16_, + Poutreg_new_15_, Poutreg_new_14_, Poutreg_new_13_, Poutreg_new_12_, + Poutreg_new_11_, Poutreg_new_10_, Poutreg_new_9_, Poutreg_new_8_, + Poutreg_new_7_, Poutreg_new_6_, Poutreg_new_5_, Poutreg_new_4_, + Poutreg_new_3_, Poutreg_new_2_, Poutreg_new_1_, Poutreg_new_0_, + Pinreg_new_55_, Pinreg_new_54_, Pinreg_new_53_, Pinreg_new_52_, + Pinreg_new_51_, Pinreg_new_50_, Pinreg_new_49_, Pinreg_new_48_, + Pinreg_new_47_, Pinreg_new_46_, Pinreg_new_45_, Pinreg_new_44_, + Pinreg_new_43_, Pinreg_new_42_, Pinreg_new_41_, Pinreg_new_40_, + Pinreg_new_39_, Pinreg_new_38_, Pinreg_new_37_, Pinreg_new_36_, + Pinreg_new_35_, Pinreg_new_34_, Pinreg_new_33_, Pinreg_new_32_, + Pinreg_new_31_, Pinreg_new_30_, Pinreg_new_29_, Pinreg_new_28_, + Pinreg_new_27_, Pinreg_new_26_, Pinreg_new_25_, Pinreg_new_24_, + Pinreg_new_23_, Pinreg_new_22_, Pinreg_new_21_, Pinreg_new_20_, + Pinreg_new_19_, Pinreg_new_18_, Pinreg_new_17_, Pinreg_new_16_, + Pinreg_new_15_, Pinreg_new_14_, Pinreg_new_13_, Pinreg_new_12_, + Pinreg_new_11_, Pinreg_new_10_, Pinreg_new_9_, Pinreg_new_8_, + Pinreg_new_7_, Pinreg_new_6_, Pinreg_new_5_, Pinreg_new_4_, + Pinreg_new_3_, Pinreg_new_2_, Pinreg_new_1_, Pinreg_new_0_, + Pencrypt_mode_new_0_, Pdata_new_63_, Pdata_new_62_, Pdata_new_61_, + Pdata_new_60_, Pdata_new_59_, Pdata_new_58_, Pdata_new_57_, + Pdata_new_56_, Pdata_new_55_, Pdata_new_54_, Pdata_new_53_, + Pdata_new_52_, Pdata_new_51_, Pdata_new_50_, Pdata_new_49_, + Pdata_new_48_, Pdata_new_47_, Pdata_new_46_, Pdata_new_45_, + Pdata_new_44_, Pdata_new_43_, Pdata_new_42_, Pdata_new_41_, + Pdata_new_40_, Pdata_new_39_, Pdata_new_38_, Pdata_new_37_, + Pdata_new_36_, Pdata_new_35_, Pdata_new_34_, Pdata_new_33_, + Pdata_new_32_, Pdata_new_31_, Pdata_new_30_, Pdata_new_29_, + Pdata_new_28_, Pdata_new_27_, Pdata_new_26_, Pdata_new_25_, + Pdata_new_24_, Pdata_new_23_, Pdata_new_22_, Pdata_new_21_, + Pdata_new_20_, Pdata_new_19_, Pdata_new_18_, Pdata_new_17_, + Pdata_new_16_, Pdata_new_15_, Pdata_new_14_, Pdata_new_13_, + Pdata_new_12_, Pdata_new_11_, Pdata_new_10_, Pdata_new_9_, + Pdata_new_8_, Pdata_new_7_, Pdata_new_6_, Pdata_new_5_, Pdata_new_4_, + Pdata_new_3_, Pdata_new_2_, Pdata_new_1_, Pdata_new_0_, Pcount_new_3_, + Pcount_new_2_, Pcount_new_1_, Pcount_new_0_, PD_new_27_, PD_new_26_, + PD_new_25_, PD_new_24_, PD_new_23_, PD_new_22_, PD_new_21_, PD_new_20_, + PD_new_19_, PD_new_18_, PD_new_17_, PD_new_16_, PD_new_15_, PD_new_14_, + PD_new_13_, PD_new_12_, PD_new_11_, PD_new_10_, PD_new_9_, PD_new_8_, + PD_new_7_, PD_new_6_, PD_new_5_, PD_new_4_, PD_new_3_, PD_new_2_, + PD_new_1_, PD_new_0_, PC_new_27_, PC_new_26_, PC_new_25_, PC_new_24_, + PC_new_23_, PC_new_22_, PC_new_21_, PC_new_20_, PC_new_19_, PC_new_18_, + PC_new_17_, PC_new_16_, PC_new_15_, PC_new_14_, PC_new_13_, PC_new_12_, + PC_new_11_, PC_new_10_, PC_new_9_, PC_new_8_, PC_new_7_, PC_new_6_, + PC_new_5_, PC_new_4_, PC_new_3_, PC_new_2_, PC_new_1_, PC_new_0_; + wire n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, + n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, + n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, + n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, + n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, + n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, + n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, + n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, + n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, + n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, + n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, + n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, + n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, + n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, + n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, + n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, + n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, + n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, + n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, + n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, + n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, + n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, + n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, + n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, + n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, + n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, + n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, + n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, + n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, + n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, + n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, + n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, + n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, + n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, + n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, + n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, + n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, + n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, + n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, + n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, + n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, + n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, + n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, + n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, + n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, + n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, + n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, + n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, + n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, + n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, + n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, + n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, + n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, + n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, + n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, + n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, + n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, + n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, + n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, + n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, + n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, + n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, + n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, + n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, + n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, + n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, + n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, + n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, + n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, + n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, + n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, + n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, + n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, + n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, + n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, + n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, + n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, + n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, + n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, + n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, + n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, + n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, + n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, + n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, + n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, + n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, + n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, + n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, + n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, + n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, + n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, + n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, + n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, + n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, + n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, + n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, + n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, + n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, + n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, + n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, + n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, + n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, + n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, + n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, + n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, + n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, + n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, + n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, + n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, + n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, + n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, + n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, + n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, + n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, + n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, + n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, + n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, + n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, + n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, + n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, + n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, + n1997, n1998; + assign Poutreg_new_63_ = ~n747; + assign Poutreg_new_62_ = ~n849; + assign Poutreg_new_61_ = ~n748; + assign Poutreg_new_60_ = ~n845; + assign Poutreg_new_59_ = ~n749; + assign Poutreg_new_58_ = ~n841; + assign Poutreg_new_57_ = ~n750; + assign Poutreg_new_56_ = ~n836; + assign Poutreg_new_55_ = ~n751; + assign Poutreg_new_54_ = ~n868; + assign Poutreg_new_53_ = ~n752; + assign Poutreg_new_52_ = ~n838; + assign Poutreg_new_51_ = ~n753; + assign Poutreg_new_50_ = ~n867; + assign Poutreg_new_49_ = ~n754; + assign Poutreg_new_48_ = ~n866; + assign Poutreg_new_47_ = ~n755; + assign Poutreg_new_46_ = ~n865; + assign Poutreg_new_45_ = ~n756; + assign Poutreg_new_44_ = ~n864; + assign Poutreg_new_43_ = ~n757; + assign Poutreg_new_42_ = ~n863; + assign Poutreg_new_41_ = ~n758; + assign Poutreg_new_40_ = ~n862; + assign Poutreg_new_39_ = ~n759; + assign Poutreg_new_38_ = ~n861; + assign Poutreg_new_37_ = ~n760; + assign Poutreg_new_36_ = ~n860; + assign Poutreg_new_35_ = ~n761; + assign Poutreg_new_34_ = ~n859; + assign Poutreg_new_33_ = ~n762; + assign Poutreg_new_32_ = ~n858; + assign Poutreg_new_31_ = ~n763; + assign Poutreg_new_30_ = ~n857; + assign Poutreg_new_29_ = ~n764; + assign Poutreg_new_28_ = ~n856; + assign Poutreg_new_27_ = ~n765; + assign Poutreg_new_26_ = ~n855; + assign Poutreg_new_25_ = ~n766; + assign Poutreg_new_24_ = ~n854; + assign Poutreg_new_23_ = ~n767; + assign Poutreg_new_22_ = ~n853; + assign Poutreg_new_21_ = ~n768; + assign Poutreg_new_20_ = ~n852; + assign Poutreg_new_19_ = ~n769; + assign Poutreg_new_18_ = ~n851; + assign Poutreg_new_17_ = ~n770; + assign Poutreg_new_16_ = ~n850; + assign Poutreg_new_15_ = ~n771; + assign Poutreg_new_14_ = ~n848; + assign Poutreg_new_13_ = ~n772; + assign Poutreg_new_12_ = ~n847; + assign Poutreg_new_11_ = ~n773; + assign Poutreg_new_10_ = ~n846; + assign Poutreg_new_9_ = ~n774; + assign Poutreg_new_8_ = ~n844; + assign Poutreg_new_7_ = ~n775; + assign Poutreg_new_6_ = ~n843; + assign Poutreg_new_5_ = ~n776; + assign Poutreg_new_4_ = ~n842; + assign Poutreg_new_3_ = ~n777; + assign Poutreg_new_2_ = ~n840; + assign Poutreg_new_1_ = ~n778; + assign Poutreg_new_0_ = ~n839; + assign Pinreg_new_55_ = ~n780; + assign Pinreg_new_54_ = ~n781; + assign Pinreg_new_53_ = ~n782; + assign Pinreg_new_52_ = ~n783; + assign Pinreg_new_51_ = ~n784; + assign Pinreg_new_50_ = ~n785; + assign Pinreg_new_49_ = ~n786; + assign Pinreg_new_48_ = ~n787; + assign Pinreg_new_47_ = ~n788; + assign Pinreg_new_46_ = ~n789; + assign Pinreg_new_45_ = ~n790; + assign Pinreg_new_44_ = ~n791; + assign Pinreg_new_43_ = ~n792; + assign Pinreg_new_42_ = ~n793; + assign Pinreg_new_41_ = ~n794; + assign Pinreg_new_40_ = ~n795; + assign Pinreg_new_39_ = ~n796; + assign Pinreg_new_38_ = ~n797; + assign Pinreg_new_37_ = ~n798; + assign Pinreg_new_36_ = ~n799; + assign Pinreg_new_35_ = ~n800; + assign Pinreg_new_34_ = ~n801; + assign Pinreg_new_33_ = ~n802; + assign Pinreg_new_32_ = ~n803; + assign Pinreg_new_31_ = ~n804; + assign Pinreg_new_30_ = ~n805; + assign Pinreg_new_29_ = ~n806; + assign Pinreg_new_28_ = ~n807; + assign Pinreg_new_27_ = ~n808; + assign Pinreg_new_26_ = ~n809; + assign Pinreg_new_25_ = ~n810; + assign Pinreg_new_24_ = ~n811; + assign Pinreg_new_23_ = ~n812; + assign Pinreg_new_22_ = ~n813; + assign Pinreg_new_21_ = ~n814; + assign Pinreg_new_20_ = ~n815; + assign Pinreg_new_19_ = ~n816; + assign Pinreg_new_18_ = ~n817; + assign Pinreg_new_17_ = ~n818; + assign Pinreg_new_16_ = ~n819; + assign Pinreg_new_15_ = ~n820; + assign Pinreg_new_14_ = ~n821; + assign Pinreg_new_13_ = ~n822; + assign Pinreg_new_12_ = ~n823; + assign Pinreg_new_11_ = ~n824; + assign Pinreg_new_10_ = ~n825; + assign Pinreg_new_9_ = ~n826; + assign Pinreg_new_8_ = ~n827; + assign Pinreg_new_7_ = ~n828; + assign Pinreg_new_6_ = ~n829; + assign Pinreg_new_5_ = ~n830; + assign Pinreg_new_4_ = ~n831; + assign Pinreg_new_3_ = ~n832; + assign Pinreg_new_2_ = ~n833; + assign Pinreg_new_1_ = ~n834; + assign Pinreg_new_0_ = ~n835; + assign Pencrypt_mode_new_0_ = ~n1799; + assign Pdata_new_63_ = ~n1732; + assign Pdata_new_62_ = ~n1733; + assign Pdata_new_61_ = ~n1734; + assign Pdata_new_60_ = ~n1735; + assign Pdata_new_59_ = ~n1736; + assign Pdata_new_58_ = ~n1737; + assign Pdata_new_57_ = ~n1738; + assign Pdata_new_56_ = ~n1739; + assign Pdata_new_55_ = ~n1740; + assign Pdata_new_54_ = ~n1741; + assign Pdata_new_53_ = ~n1742; + assign Pdata_new_52_ = ~n1743; + assign Pdata_new_51_ = ~n1744; + assign Pdata_new_50_ = ~n1745; + assign Pdata_new_49_ = ~n1746; + assign Pdata_new_48_ = ~n1747; + assign Pdata_new_47_ = ~n1748; + assign Pdata_new_46_ = ~n1749; + assign Pdata_new_45_ = ~n1750; + assign Pdata_new_44_ = ~n1751; + assign Pdata_new_43_ = ~n1752; + assign Pdata_new_42_ = ~n1753; + assign Pdata_new_41_ = ~n1754; + assign Pdata_new_40_ = ~n1755; + assign Pdata_new_39_ = ~n1756; + assign Pdata_new_38_ = ~n1757; + assign Pdata_new_37_ = ~n1758; + assign Pdata_new_36_ = ~n1759; + assign Pdata_new_35_ = ~n1760; + assign Pdata_new_34_ = ~n1761; + assign Pdata_new_33_ = ~n1762; + assign Pdata_new_32_ = ~n1763; + assign Pdata_new_31_ = ~n1764; + assign Pdata_new_30_ = ~n1765; + assign Pdata_new_29_ = ~n1766; + assign Pdata_new_28_ = ~n1767; + assign Pdata_new_27_ = ~n1768; + assign Pdata_new_26_ = ~n1769; + assign Pdata_new_25_ = ~n1770; + assign Pdata_new_24_ = ~n1771; + assign Pdata_new_23_ = ~n1772; + assign Pdata_new_22_ = ~n1773; + assign Pdata_new_21_ = ~n1774; + assign Pdata_new_20_ = ~n1775; + assign Pdata_new_19_ = ~n1776; + assign Pdata_new_18_ = ~n1777; + assign Pdata_new_17_ = ~n1778; + assign Pdata_new_16_ = ~n1779; + assign Pdata_new_15_ = ~n1780; + assign Pdata_new_14_ = ~n1781; + assign Pdata_new_13_ = ~n1782; + assign Pdata_new_12_ = ~n1783; + assign Pdata_new_11_ = ~n1784; + assign Pdata_new_10_ = ~n1785; + assign Pdata_new_9_ = ~n1786; + assign Pdata_new_8_ = ~n1787; + assign Pdata_new_7_ = ~n1788; + assign Pdata_new_6_ = ~n1789; + assign Pdata_new_5_ = ~n1790; + assign Pdata_new_4_ = ~n1791; + assign Pdata_new_3_ = ~n1792; + assign Pdata_new_2_ = ~n1793; + assign Pdata_new_1_ = ~n1794; + assign Pdata_new_0_ = ~n1795; + assign Pcount_new_3_ = ~n779; + assign Pcount_new_2_ = ~n1796; + assign Pcount_new_1_ = ~n1797; + assign Pcount_new_0_ = ~n1403; + assign PD_new_27_ = ~n1524; + assign PD_new_26_ = ~n1528; + assign PD_new_25_ = ~n1532; + assign PD_new_24_ = ~n1536; + assign PD_new_23_ = ~n1540; + assign PD_new_22_ = ~n1544; + assign PD_new_21_ = ~n1548; + assign PD_new_20_ = ~n1552; + assign PD_new_19_ = ~n1556; + assign PD_new_18_ = ~n1560; + assign PD_new_17_ = ~n1564; + assign PD_new_16_ = ~n1568; + assign PD_new_15_ = ~n1572; + assign PD_new_14_ = ~n1576; + assign PD_new_13_ = ~n1580; + assign PD_new_12_ = ~n1584; + assign PD_new_11_ = ~n1588; + assign PD_new_10_ = ~n1592; + assign PD_new_9_ = ~n1596; + assign PD_new_8_ = ~n1600; + assign PD_new_7_ = ~n1604; + assign PD_new_6_ = ~n1608; + assign PD_new_5_ = ~n1612; + assign PD_new_4_ = ~n1616; + assign PD_new_3_ = ~n1620; + assign PD_new_2_ = ~n1624; + assign PD_new_1_ = ~n1628; + assign PD_new_0_ = ~n1632; + assign PC_new_27_ = ~n1412; + assign PC_new_26_ = ~n1416; + assign PC_new_25_ = ~n1420; + assign PC_new_24_ = ~n1424; + assign PC_new_23_ = ~n1428; + assign PC_new_22_ = ~n1432; + assign PC_new_21_ = ~n1436; + assign PC_new_20_ = ~n1440; + assign PC_new_19_ = ~n1444; + assign PC_new_18_ = ~n1448; + assign PC_new_17_ = ~n1452; + assign PC_new_16_ = ~n1456; + assign PC_new_15_ = ~n1460; + assign PC_new_14_ = ~n1464; + assign PC_new_13_ = ~n1468; + assign PC_new_12_ = ~n1472; + assign PC_new_11_ = ~n1476; + assign PC_new_10_ = ~n1480; + assign PC_new_9_ = ~n1484; + assign PC_new_8_ = ~n1488; + assign PC_new_7_ = ~n1492; + assign PC_new_6_ = ~n1496; + assign PC_new_5_ = ~n1500; + assign PC_new_4_ = ~n1504; + assign PC_new_3_ = ~n1508; + assign PC_new_2_ = ~n1512; + assign PC_new_1_ = ~n1516; + assign PC_new_0_ = ~n1520; + assign n746 = ~Pcount_3_ | n1648; + assign n747 = (~Poutreg_63_ | Pcount_0_) & (n746 | n899); + assign n748 = (~Poutreg_61_ | Pcount_0_) & (n746 | n931); + assign n749 = (~Poutreg_59_ | Pcount_0_) & (n746 | n948); + assign n750 = (~Poutreg_57_ | Pcount_0_) & (n746 | n976); + assign n751 = (~Poutreg_55_ | Pcount_0_) & n986; + assign n752 = (~Poutreg_53_ | Pcount_0_) & n1024; + assign n753 = (~Poutreg_51_ | Pcount_0_) & n1037; + assign n754 = (~Poutreg_49_ | Pcount_0_) & n1059; + assign n755 = (~Poutreg_47_ | Pcount_0_) & n1099; + assign n756 = (~Poutreg_45_ | Pcount_0_) & n1126; + assign n757 = (~Poutreg_43_ | Pcount_0_) & n1135; + assign n758 = (~Poutreg_41_ | Pcount_0_) & n1144; + assign n759 = (~Poutreg_39_ | Pcount_0_) & n1157; + assign n760 = (~Poutreg_37_ | Pcount_0_) & n1167; + assign n761 = (~Poutreg_35_ | Pcount_0_) & n1197; + assign n762 = (~Poutreg_33_ | Pcount_0_) & n1203; + assign n763 = (~Poutreg_31_ | Pcount_0_) & n1216; + assign n764 = (~Poutreg_29_ | Pcount_0_) & n1233; + assign n765 = (~Poutreg_27_ | Pcount_0_) & n1242; + assign n766 = (~Poutreg_25_ | Pcount_0_) & n1248; + assign n767 = (~Poutreg_23_ | Pcount_0_) & n1290; + assign n768 = (~Poutreg_21_ | Pcount_0_) & n1305; + assign n769 = (~Poutreg_19_ | Pcount_0_) & n1313; + assign n770 = (~Poutreg_17_ | Pcount_0_) & n1329; + assign n771 = (~Poutreg_15_ | Pcount_0_) & n1336; + assign n772 = (~Poutreg_13_ | Pcount_0_) & n1345; + assign n773 = (~Poutreg_11_ | Pcount_0_) & n1354; + assign n774 = (~Poutreg_9_ | Pcount_0_) & n1363; + assign n775 = (~Poutreg_7_ | Pcount_0_) & n1374; + assign n776 = (~Poutreg_5_ | Pcount_0_) & n1379; + assign n777 = (~Poutreg_3_ | Pcount_0_) & n1392; + assign n778 = (~Poutreg_1_ | Pcount_0_) & n1401; + assign n779 = (n1404 | n1407) & (~Pcount_3_ | n1406); + assign n780 = (~Pinreg_55_ | Pcount_0_) & (~Pinreg_47_ | n869); + assign n781 = (~Pinreg_54_ | Pcount_0_) & (~Pinreg_46_ | n869); + assign n782 = (~Pinreg_53_ | Pcount_0_) & (~Pinreg_45_ | n869); + assign n783 = (~Pinreg_52_ | Pcount_0_) & (~Pinreg_44_ | n869); + assign n784 = (~Pinreg_51_ | Pcount_0_) & (~Pinreg_43_ | n869); + assign n785 = (~Pinreg_50_ | Pcount_0_) & (~Pinreg_42_ | n869); + assign n786 = (~Pinreg_49_ | Pcount_0_) & (~Pinreg_41_ | n869); + assign n787 = (~Pinreg_48_ | Pcount_0_) & (~Pinreg_40_ | n869); + assign n788 = (~Pinreg_47_ | Pcount_0_) & (~Pinreg_39_ | n869); + assign n789 = (~Pinreg_46_ | Pcount_0_) & (~Pinreg_38_ | n869); + assign n790 = (~Pinreg_45_ | Pcount_0_) & (~Pinreg_37_ | n869); + assign n791 = (~Pinreg_44_ | Pcount_0_) & (~Pinreg_36_ | n869); + assign n792 = (~Pinreg_43_ | Pcount_0_) & (~Pinreg_35_ | n869); + assign n793 = (~Pinreg_42_ | Pcount_0_) & (~Pinreg_34_ | n869); + assign n794 = (~Pinreg_41_ | Pcount_0_) & (~Pinreg_33_ | n869); + assign n795 = (~Pinreg_40_ | Pcount_0_) & (~Pinreg_32_ | n869); + assign n796 = (~Pinreg_39_ | Pcount_0_) & (~Pinreg_31_ | n869); + assign n797 = (~Pinreg_38_ | Pcount_0_) & (~Pinreg_30_ | n869); + assign n798 = (~Pinreg_37_ | Pcount_0_) & (~Pinreg_29_ | n869); + assign n799 = (~Pinreg_36_ | Pcount_0_) & (~Pinreg_28_ | n869); + assign n800 = (~Pinreg_35_ | Pcount_0_) & (~Pinreg_27_ | n869); + assign n801 = (~Pinreg_34_ | Pcount_0_) & (~Pinreg_26_ | n869); + assign n802 = (~Pinreg_33_ | Pcount_0_) & (~Pinreg_25_ | n869); + assign n803 = (~Pinreg_32_ | Pcount_0_) & (~Pinreg_24_ | n869); + assign n804 = (~Pinreg_31_ | Pcount_0_) & (~Pinreg_23_ | n869); + assign n805 = (~Pinreg_30_ | Pcount_0_) & (~Pinreg_22_ | n869); + assign n806 = (~Pinreg_29_ | Pcount_0_) & (~Pinreg_21_ | n869); + assign n807 = (~Pinreg_28_ | Pcount_0_) & (~Pinreg_20_ | n869); + assign n808 = (~Pinreg_27_ | Pcount_0_) & (~Pinreg_19_ | n869); + assign n809 = (~Pinreg_26_ | Pcount_0_) & (~Pinreg_18_ | n869); + assign n810 = (~Pinreg_25_ | Pcount_0_) & (~Pinreg_17_ | n869); + assign n811 = (~Pinreg_24_ | Pcount_0_) & (~Pinreg_16_ | n869); + assign n812 = (~Pinreg_23_ | Pcount_0_) & (~Pinreg_15_ | n869); + assign n813 = (~Pinreg_22_ | Pcount_0_) & (~Pinreg_14_ | n869); + assign n814 = (~Pinreg_21_ | Pcount_0_) & (~Pinreg_13_ | n869); + assign n815 = (~Pinreg_20_ | Pcount_0_) & (~Pinreg_12_ | n869); + assign n816 = (~Pinreg_19_ | Pcount_0_) & (~Pinreg_11_ | n869); + assign n817 = (~Pinreg_18_ | Pcount_0_) & (~Pinreg_10_ | n869); + assign n818 = (~Pinreg_17_ | Pcount_0_) & (~Pinreg_9_ | n869); + assign n819 = (~Pinreg_16_ | Pcount_0_) & (~Pinreg_8_ | n869); + assign n820 = (~Pinreg_15_ | Pcount_0_) & (~Pinreg_7_ | n869); + assign n821 = (~Pinreg_14_ | Pcount_0_) & (~Pinreg_6_ | n869); + assign n822 = (~Pinreg_13_ | Pcount_0_) & (~Pinreg_5_ | n869); + assign n823 = (~Pinreg_12_ | Pcount_0_) & (~Pinreg_4_ | n869); + assign n824 = (~Pinreg_11_ | Pcount_0_) & (~Pinreg_3_ | n869); + assign n825 = (~Pinreg_10_ | Pcount_0_) & (~Pinreg_2_ | n869); + assign n826 = (~Pinreg_9_ | Pcount_0_) & (~Pinreg_1_ | n869); + assign n827 = (~Pinreg_8_ | Pcount_0_) & (~Pinreg_0_ | n869); + assign n828 = (~Pinreg_7_ | Pcount_0_) & (~Pdata_in_7_ | n869); + assign n829 = (~Pinreg_6_ | Pcount_0_) & (~Pdata_in_6_ | n869); + assign n830 = (~Pinreg_5_ | Pcount_0_) & (~Pdata_in_5_ | n869); + assign n831 = (~Pinreg_4_ | Pcount_0_) & (~Pdata_in_4_ | n869); + assign n832 = (~Pinreg_3_ | Pcount_0_) & (~Pdata_in_3_ | n869); + assign n833 = (~Pinreg_2_ | Pcount_0_) & (~Pdata_in_2_ | n869); + assign n834 = (~Pinreg_1_ | Pcount_0_) & (~Pdata_in_1_ | n869); + assign n835 = (~Pinreg_0_ | Pcount_0_) & (~Pdata_in_0_ | n869); + assign n836 = (~Poutreg_56_ | Pcount_0_) & (~Pdata_32_ | n746); + assign n837 = Pload_key_0_ & ~n746; + assign n838 = (~Pdata_49_ | n746) & n1025; + assign n839 = (~Pdata_39_ | n746) & n1402; + assign n840 = (~Pdata_47_ | n746) & n1393; + assign n841 = (~Poutreg_58_ | Pcount_0_) & (~Pdata_40_ | n746); + assign n842 = (~Pdata_55_ | n746) & n1380; + assign n843 = (~Pdata_63_ | n746) & n1375; + assign n844 = (~Pdata_38_ | n746) & n1364; + assign n845 = (~Poutreg_60_ | Pcount_0_) & (~Pdata_48_ | n746); + assign n846 = (~Pdata_46_ | n746) & n1355; + assign n847 = (~Pdata_54_ | n746) & n1346; + assign n848 = (~Pdata_62_ | n746) & n1337; + assign n849 = (~Poutreg_62_ | Pcount_0_) & (~Pdata_56_ | n746); + assign n850 = (~Pdata_37_ | n746) & n1330; + assign n851 = (~Pdata_45_ | n746) & n1314; + assign n852 = (~Pdata_53_ | n746) & n1306; + assign n853 = (~Pdata_61_ | n746) & n1291; + assign n854 = (~Pdata_36_ | n746) & n1249; + assign n855 = (~Pdata_44_ | n746) & n1243; + assign n856 = (~Pdata_52_ | n746) & n1234; + assign n857 = (~Pdata_60_ | n746) & n1217; + assign n858 = (~Pdata_35_ | n746) & n1204; + assign n859 = (~Pdata_43_ | n746) & n1198; + assign n860 = (~Pdata_51_ | n746) & n1168; + assign n861 = (~Pdata_59_ | n746) & n1158; + assign n862 = (~Pdata_34_ | n746) & n1145; + assign n863 = (~Pdata_42_ | n746) & n1136; + assign n864 = (~Pdata_50_ | n746) & n1127; + assign n865 = (~Pdata_58_ | n746) & n1100; + assign n866 = (~Pdata_33_ | n746) & n1060; + assign n867 = (~Pdata_41_ | n746) & n1038; + assign n868 = (~Pdata_57_ | n746) & n987; + assign n869 = ~Pcount_0_ | ~n746; + assign n870 = (~n893 | ~n1140) & (~n892 | ~n896); + assign n871 = (~n878 | ~n892) & (~n1140 | ~n1649); + assign n872 = ~Pdata_49_ ^ ~PD_2_; + assign n873 = (n871 | ~n1394) & (n870 | n872); + assign n874 = n1800 & (~n1651 | (~n877 & n885)); + assign n875 = n873 & n874 & (~n1394 | ~n1652); + assign n876 = n1398 & ~n1633; + assign n877 = n1394 & n1650; + assign n878 = ~n887 & n1634; + assign n879 = n876 & (n877 | (n878 & ~n890)); + assign n880 = ~n1651 | n890 | ~n1649; + assign n881 = n1633 | n1653; + assign n882 = ~n879 & n880 & (n881 | ~n1395); + assign n883 = ~n1652 | n872 | n1397; + assign n884 = (n1311 | ~n1650) & (~n878 | n1654); + assign n885 = ~n872 | ~n896; + assign n886 = n883 & n884 & (n885 | ~n1140); + assign n887 = ~Pdata_50_ ^ ~PD_8_; + assign n888 = ~n1397 ^ ~n1634; + assign n889 = ~n1651 | n887 | n888; + assign n890 = ~n872 | n1397; + assign n891 = n890 | ~n1651; + assign n892 = n1398 & n1633; + assign n893 = ~n1397 & n1650; + assign n894 = n1650 | n1649; + assign n895 = n892 & (n893 | (n872 & n894)); + assign n896 = n1395 & ~n1397; + assign n897 = n1140 | n876; + assign n898 = ~n872 & (~n889 | (n896 & n897)); + assign n899 = ~Pdata_24_ ^ ~n1978; + assign n900 = n914 & ~n920; + assign n901 = ~n1338 & ~n912 & ~n916; + assign n902 = n900 & ~n1926 & (n901 | ~n906); + assign n903 = ~n902 & (~n912 | ~n918 | ~n1721); + assign n904 = (~n934 | n938) & (~n1338 | ~n1720); + assign n905 = n903 & n904 & (~n926 | ~n1656); + assign n906 = ~Pdata_36_ ^ ~PC_4_; + assign n907 = (~n926 | ~n1338) & (n906 | ~n1657); + assign n908 = n1655 | ~n914 | ~n932; + assign n909 = ~n934 | ~n1656; + assign n910 = n908 & n909 & (n907 | ~n935); + assign n911 = n906 | ~n912; + assign n912 = ~Pdata_35_ ^ ~PC_0_; + assign n913 = n911 & (~n906 | n912); + assign n914 = ~Pdata_63_ ^ ~PC_13_; + assign n915 = ~n900 & (n914 | ~n920); + assign n916 = ~Pdata_32_ ^ ~PC_16_; + assign n917 = ~n906 & n916; + assign n918 = ~n916 & ~n920; + assign n919 = ~n906 & n918 & (~n912 | ~n914); + assign n920 = ~Pdata_34_ ^ ~PC_23_; + assign n921 = ~n912 & n916; + assign n922 = ~n914 & n920 & (n917 | n921); + assign n923 = (~n920 | ~n921) & (n913 | ~n918); + assign n924 = n1338 & n934; + assign n925 = n924 & ~n912 & n918; + assign n926 = ~n906 & ~n914; + assign n927 = n901 & ~n920 & n926; + assign n928 = ~n914 | n923 | ~n1338; + assign n929 = (~n926 | n1659) & (~n932 | ~n1658); + assign n930 = n929 & n928 & n905 & n910 & ~n1662 & ~n1924; + assign n931 = ~n930 ^ ~Pdata_16_; + assign n932 = n912 & n906; + assign n933 = n932 & n900 & n916; + assign n934 = n906 & ~n914; + assign n935 = n920 & n916 & n912; + assign n936 = ~n1338 & (n933 | (n934 & n935)); + assign n937 = n1655 | n911 | ~n914; + assign n938 = n912 | n1655; + assign n939 = ~n936 & n937 & (~n926 | n938); + assign n940 = (n906 | ~n921) & (n913 | n916); + assign n941 = n916 | ~n900 | ~n906; + assign n942 = ~n926 | n1655; + assign n943 = (n906 & (~n920 | ~n924)) | (n920 & ~n924); + assign n944 = n941 & n942 & (~n916 | n943); + assign n945 = n1803 & (~n920 | n940 | ~n1657); + assign n946 = n905 & n1341 & (~n906 | n1659); + assign n947 = n945 & (~n912 | n944) & n946; + assign n948 = ~n947 ^ ~Pdata_8_; + assign n949 = n980 | n1635; + assign n950 = ~n956 | n1030; + assign n951 = n957 | ~n980; + assign n952 = (n949 | n950) & (n951 | ~n1163); + assign n953 = (n983 | n1663) & (n952 | n958); + assign n954 = n949 | n981; + assign n955 = n953 & (n954 | ~n1161); + assign n956 = ~Pdata_43_ ^ ~PC_15_; + assign n957 = n956 | ~n1159; + assign n958 = ~Pdata_48_ ^ ~PC_1_; + assign n959 = (n956 | ~n961) & (n957 | n958); + assign n960 = n956 & ~n958 & n1159; + assign n961 = n958 & ~n1159; + assign n962 = ~n1664 & (n960 | (n956 & n961)); + assign n963 = n955 & ~n962 & (n954 | n959); + assign n964 = (~n960 | n1663) & (~n961 | n1667); + assign n965 = n1805 & (n958 | ~n1635 | n1666); + assign n966 = n964 & n965; + assign n967 = n1804 & (n949 | ~n981 | n983); + assign n968 = n1159 | n958; + assign n969 = n967 & (n968 | ~n1724); + assign n970 = ~n956 ^ ~n1635; + assign n971 = n1030 | n958; + assign n972 = n981 | ~n1635; + assign n973 = (n970 | n971) & (n972 | ~n1161); + assign n974 = ~n956 | n968; + assign n975 = n974 & n950 & (n957 | n958); + assign n976 = ~Pdata_0_ ^ ~n1979; + assign n977 = (~n958 | n1669) & (n968 | n1667); + assign n978 = n1809 & (~n960 | ~n981 | n1665); + assign n979 = n977 & n978; + assign n980 = ~Pdata_46_ ^ ~PC_19_; + assign n981 = ~Pdata_44_ ^ ~PC_6_; + assign n982 = n980 & (~n973 | (n981 & ~n983)); + assign n983 = n957 | ~n958; + assign n984 = n954 | n983; + assign n985 = n956 & (~n1808 | (~n1159 & ~n1663)); + assign n986 = (n746 | n1810) & (~Poutreg_63_ | n869); + assign n987 = (~Poutreg_62_ | n869) & (~Poutreg_54_ | Pcount_0_); + assign n988 = (n1017 | n1236) & (~n996 | ~n997); + assign n989 = ~n1017 | n1149; + assign n990 = n988 & (n989 | ~n1039); + assign n991 = ~n993 | ~n1146; + assign n992 = ~n1039 | n989 | n991; + assign n993 = ~Pdata_36_ ^ ~PC_27_; + assign n994 = n1004 | ~n1146; + assign n995 = ~n997 | n993 | n994; + assign n996 = ~n1054 & ~n1636; + assign n997 = n1017 & n1149; + assign n998 = n996 & (~n1022 | (n997 & ~n1670)); + assign n999 = ~n998 & n992 & n995; + assign n1000 = n1813 & (~n1050 | ~n1146 | n1671); + assign n1001 = n1670 | n1017; + assign n1002 = n1004 | ~n1149; + assign n1003 = n999 & n1000 & (n1001 | n1002); + assign n1004 = ~n1054 | n1636; + assign n1005 = n993 | ~n1146; + assign n1006 = (n1005 | ~n1050) & (n1004 | ~n1049); + assign n1007 = ~n993 | n1018 | n1056; + assign n1008 = n1001 | n1236; + assign n1009 = n1007 & n1008 & (n1006 | ~n1051); + assign n1010 = (n1042 | ~n1049) & (n1004 | n1053); + assign n1011 = n1811 & (~n993 | n1013 | n1056); + assign n1012 = n1010 & n1011; + assign n1013 = ~n996 | ~n1149; + assign n1014 = n1012 & n1009 & (n1001 | n1013); + assign n1015 = n1636 | n989 | ~n1146; + assign n1016 = (~n997 | ~n1054) & (~n996 | ~n1051); + assign n1017 = ~Pdata_37_ ^ ~PC_14_; + assign n1018 = ~n1050 | ~n1149; + assign n1019 = n1015 & n1016 & (n1017 | n1018); + assign n1020 = n1814 & (n990 | n1005); + assign n1021 = n1003 & n1014 & (~n993 | n1019); + assign n1022 = n1149 | n1001; + assign n1023 = n1020 & n1021 & (n1004 | n1022); + assign n1024 = (n746 | n1815) & (~Poutreg_61_ | n869); + assign n1025 = (~Poutreg_60_ | n869) & (~Poutreg_52_ | Pcount_0_); + assign n1026 = ~n981 | ~n1159 | n970 | n980; + assign n1027 = (n957 | n972) & (n950 | n1665); + assign n1028 = n1026 & n1027 & (n951 | n981); + assign n1029 = ~n1163 | n957 | n980; + assign n1030 = ~n981 | n1159; + assign n1031 = n1029 & (n970 | ~n980 | n1030); + assign n1032 = (n958 & n1031) | (n1028 & (~n958 | n1031)); + assign n1033 = n969 & n966; + assign n1034 = (n954 | ~n956) & (n951 | n972); + assign n1035 = n1165 & (~n1161 | n1665); + assign n1036 = n1035 & n955 & n1033 & n1032 & n979 & n1034; + assign n1037 = (n746 | n1816) & (~Poutreg_59_ | n869); + assign n1038 = (~Poutreg_58_ | n869) & (~Poutreg_50_ | Pcount_0_); + assign n1039 = n1054 & n1636; + assign n1040 = n1039 & (~n1022 | (n997 & ~n1670)); + assign n1041 = ~n1051 | n993 | n994; + assign n1042 = ~n1017 | n1018; + assign n1043 = ~n1040 & n1041 & (n991 | n1042); + assign n1044 = n1004 & ~n1050; + assign n1045 = n989 | n991 | n1044; + assign n1046 = n1236 & ~n996 & n1146; + assign n1047 = n1002 & ~n1146; + assign n1048 = n1046 | n1047 | n993 | ~n1017; + assign n1049 = n993 & ~n1146; + assign n1050 = ~n1054 & n1636; + assign n1051 = ~n1017 & ~n1149; + assign n1052 = n1049 & (~n990 | (n1050 & n1051)); + assign n1053 = n1146 | n1671; + assign n1054 = ~Pdata_39_ ^ ~PC_20_; + assign n1055 = n1053 | n1054; + assign n1056 = n1017 | ~n1146; + assign n1057 = n1018 & ~n1637; + assign n1058 = n1056 | n1057; + assign n1059 = (n746 | n1817) & (~Poutreg_57_ | n869); + assign n1060 = (~Poutreg_56_ | n869) & (~Poutreg_48_ | Pcount_0_); + assign n1061 = ~Pdata_63_ ^ ~PD_0_; + assign n1062 = ~Pdata_61_ ^ ~PD_21_; + assign n1063 = ~n1087 | ~n1672; + assign n1064 = n1063 | n1061 | n1062; + assign n1065 = n1078 | n1076 | n1673; + assign n1066 = n1078 | n1061 | ~n1062; + assign n1067 = n1065 & ~n1929 & (n1063 | n1066); + assign n1068 = n1930 & (n1078 | n1083 | ~n1352); + assign n1069 = (~n1349 | n1676) & (n1073 | n1818); + assign n1070 = n1069 & n1068 & n1067; + assign n1071 = ~n1062 | n1087 | n1222; + assign n1072 = n1061 | ~n1078; + assign n1073 = n1062 | n1083; + assign n1074 = n1078 | ~n1222; + assign n1075 = (n1073 | n1074) & (n1071 | n1072); + assign n1076 = ~Pdata_59_ ^ ~PD_17_; + assign n1077 = ~n1078 | ~n1222; + assign n1078 = ~Pdata_32_ ^ ~PD_3_; + assign n1079 = (n1076 | n1077) & (n1078 | ~n1351); + assign n1080 = ~n1061 | n1074 | ~n1076 | ~n1349; + assign n1081 = n1674 | n1220; + assign n1082 = n1080 & n1081 & (n1079 | n1073); + assign n1083 = n1061 | n1087; + assign n1084 = n1077 | n1076 | n1083; + assign n1085 = ~n1076 | n1077 | ~n1675; + assign n1086 = ~n1672 | n1073 | n1078; + assign n1087 = ~Pdata_60_ ^ ~PD_13_; + assign n1088 = n1062 & (~n1084 | (n1087 & ~n1676)); + assign n1089 = ~n1349 | n1061 | n1076; + assign n1090 = (~n1061 | n1063) & n1089; + assign n1091 = ~n1352 | n1061 | ~n1087; + assign n1092 = n1066 | ~n1351; + assign n1093 = ~n1061 | n1062 | n1063; + assign n1094 = n1819 & (~n1078 | (n1090 & ~n1950)); + assign n1095 = (n1062 & n1680) | (n1676 & (~n1062 | n1680)); + assign n1096 = (n1075 | ~n1076) & (n1066 | ~n1087); + assign n1097 = n1678 & n1082; + assign n1098 = n1070 & n1094 & n1093 & n1091 & n1092 & n1095 & n1096 & n1097; + assign n1099 = (n746 | n1820) & (~Poutreg_55_ | n869); + assign n1100 = (~Poutreg_54_ | n869) & (~Poutreg_46_ | Pcount_0_); + assign n1101 = ~n1102 | n1120; + assign n1102 = ~Pdata_55_ ^ ~PD_4_; + assign n1103 = n1101 & (n1102 | ~n1120); + assign n1104 = ~n1638 & ~n1639; + assign n1105 = ~n1102 & n1682; + assign n1106 = n1104 & (n1105 | ~n1822); + assign n1107 = ~n1932 & (~n1105 | ~n1132 | ~n1201); + assign n1108 = n1823 & n1824 & (n1130 | n1117); + assign n1109 = n1201 | n1207; + assign n1110 = n1107 & n1108 & (n1109 | ~n1683); + assign n1111 = n1821 & (n1130 | (~n1105 & n1822)); + assign n1112 = n1102 | n1119; + assign n1113 = n1111 & (n1112 | n1109); + assign n1114 = ~n1201 | n1207 | ~n1683; + assign n1115 = (n1109 | n1685) & (n1130 | n1684); + assign n1116 = n1201 | n1211; + assign n1117 = n1133 | n1101; + assign n1118 = n1114 & n1115 & (n1116 | n1117); + assign n1119 = ~n1120 | n1133; + assign n1120 = ~Pdata_51_ ^ ~PD_1_; + assign n1121 = n1119 & (n1120 | ~n1133); + assign n1122 = n1118 & n1113; + assign n1123 = n1931 & (~n1201 | (n1825 & n1826)); + assign n1124 = n1828 & (n1211 | n1685); + assign n1125 = n1124 & n1123 & n1110 & n1122; + assign n1126 = (n746 | n1829) & (~Poutreg_53_ | n869); + assign n1127 = (~Poutreg_52_ | n869) & (~Poutreg_44_ | Pcount_0_); + assign n1128 = n1830 & (n1109 | (n1822 & n1684)); + assign n1129 = n1133 | ~n1681; + assign n1130 = ~n1201 | n1211; + assign n1131 = n1128 & (n1129 | n1130); + assign n1132 = ~n1638 & n1639; + assign n1133 = ~Pdata_54_ ^ ~PD_16_; + assign n1134 = n1132 & (~n1684 | (~n1103 & n1133)); + assign n1135 = (n746 | n1834) & (~Poutreg_51_ | n869); + assign n1136 = (~Poutreg_50_ | n869) & (~Poutreg_42_ | Pcount_0_); + assign n1137 = ~n1649 | n890 | ~n1140; + assign n1138 = (~n878 | n881) & (~n1650 | n1654); + assign n1139 = n1137 & (~n876 | n885) & n1138; + assign n1140 = ~n1398 & n1633; + assign n1141 = n878 & n1140 & n890; + assign n1142 = n1649 & n892; + assign n1143 = n1142 & ~n1397; + assign n1144 = (~Poutreg_49_ | n869) & (n746 | ~n1996); + assign n1145 = (~Poutreg_48_ | n869) & (~Poutreg_40_ | Pcount_0_); + assign n1146 = ~Pdata_35_ ^ ~PC_2_; + assign n1147 = ~n1017 | ~n1039; + assign n1148 = n994 & (n1146 | (~n996 & n1147)); + assign n1149 = ~Pdata_40_ ^ ~PC_9_; + assign n1150 = (n989 | n1146) & (n1149 | n1056); + assign n1151 = (n1148 | ~n1149) & (n1054 | n1150); + assign n1152 = (~n1039 | n1056) & n1151; + assign n1153 = n1001 | n1018; + assign n1154 = (n1146 | n1687) & (~n993 | n1152); + assign n1155 = n1835 & (n994 | n1671); + assign n1156 = n1155 & n1153 & n1009 & n1043 & n1003 & n1154; + assign n1157 = (n746 | n1836) & (~Poutreg_47_ | n869); + assign n1158 = (~Poutreg_46_ | n869) & (~Poutreg_38_ | Pcount_0_); + assign n1159 = ~Pdata_47_ ^ ~PC_12_; + assign n1160 = n980 & (~n950 | (~n981 & n1159)); + assign n1161 = n1159 & n956 & n958; + assign n1162 = n981 & (~n951 | (~n980 & n1161)); + assign n1163 = n981 & n1635; + assign n1164 = n960 & (~n954 | (n980 & n1163)); + assign n1165 = ~n961 | n1663; + assign n1166 = n1165 | n956; + assign n1167 = (n746 | n1837) & (~Poutreg_45_ | n869); + assign n1168 = (~Poutreg_44_ | n869) & (~Poutreg_36_ | Pcount_0_); + assign n1169 = (~n1292 | ~n1726) & (n1177 | ~n1358); + assign n1170 = n1367 | ~n1642; + assign n1171 = n1169 & (n1170 | ~n1303); + assign n1172 = ~n1190 & n1641; + assign n1173 = ~n1299 & ~n1642; + assign n1174 = ~n1292 & ~n1300; + assign n1175 = n1172 & (~n1170 | (n1173 & n1174)); + assign n1176 = n1689 | ~n1296 | ~n1303; + assign n1177 = n1689 | ~n1690; + assign n1178 = ~n1175 & n1176 & (n1177 | ~n1295); + assign n1179 = n1292 | ~n1300; + assign n1180 = (~n1172 | ~n1174) & (n1179 | ~n1358); + assign n1181 = ~n1292 | n1641 | ~n1691; + assign n1182 = n1177 | ~n1303; + assign n1183 = n1181 & n1182 & (n1180 | ~n1298); + assign n1184 = (~n1296 | ~n1358) & (~n1295 | ~n1690); + assign n1185 = ~n1690 | ~n1172 | ~n1302; + assign n1186 = ~n1173 | n1692; + assign n1187 = n1185 & n1186 & (n1184 | ~n1298); + assign n1188 = ~n1302 | ~n1358; + assign n1189 = n1694 | ~n1298 | ~n1300; + assign n1190 = ~Pdata_57_ ^ ~PD_10_; + assign n1191 = n1188 & n1189 & (n1190 | ~n1361); + assign n1192 = n1942 & (n1694 | n1695); + assign n1193 = n1178 & n1171; + assign n1194 = (n1191 | ~n1292) & (~n1299 | n1692); + assign n1195 = (n1370 | ~n1641) & (~n1295 | n1693); + assign n1196 = n1195 & n1187 & n1183 & n1192 & n1193 & n1194; + assign n1197 = (n746 | n1838) & (~Poutreg_43_ | n869); + assign n1198 = (~Poutreg_42_ | n869) & (~Poutreg_34_ | Pcount_0_); + assign n1199 = (~n1681 | ~n1696) & (n1103 | ~n1640); + assign n1200 = ~n1102 | ~n1120; + assign n1201 = ~Pdata_53_ ^ ~PD_22_; + assign n1202 = n1200 & ~n1681 & (n1102 | n1201); + assign n1203 = (n746 | n1840) & (~Poutreg_41_ | n869); + assign n1204 = (~Poutreg_40_ | n869) & (~Poutreg_32_ | Pcount_0_); + assign n1205 = n1639 | n1685; + assign n1206 = n1841 & n1842 & (n1211 | ~n1683); + assign n1207 = ~n1638 | ~n1639; + assign n1208 = n1205 & n1206 & (n1112 | n1207); + assign n1209 = ~n1132 | n1102 | n1121; + assign n1210 = (~n1681 | n1686) & (n1638 | ~n1683); + assign n1211 = ~n1638 | n1639; + assign n1212 = n1209 & n1210 & (n1103 | n1211); + assign n1213 = (~n1201 & n1212) | (n1208 & (n1201 | n1212)); + assign n1214 = n1118 & (n1129 | n1109); + assign n1215 = n1110 & n1214 & n1213 & n1131; + assign n1216 = (n746 | n1843) & (~Poutreg_39_ | n869); + assign n1217 = (~Poutreg_38_ | n869) & (~Poutreg_30_ | Pcount_0_); + assign n1218 = n1066 | n1076 | n1087 | ~n1222; + assign n1219 = n1946 & (n1078 | ~n1672 | ~n1675); + assign n1220 = ~n1078 | ~n1352; + assign n1221 = n1218 & n1219 & (n1220 | ~n1677); + assign n1222 = ~Pdata_62_ ^ ~PD_7_; + assign n1223 = n1074 & (~n1078 | n1222); + assign n1224 = n1073 | ~n1351; + assign n1225 = n1061 | ~n1087 | ~n1222 | n1643; + assign n1226 = n1224 & (~n1062 | n1063) & n1225; + assign n1227 = n1643 | n1223 | n1674; + assign n1228 = ~n1677 | n1222 | ~n1643; + assign n1229 = (n1078 & n1226) | (n1091 & (~n1078 | n1226)); + assign n1230 = n1061 | n1679; + assign n1231 = (~n1087 | n1092) & (n1074 | n1089); + assign n1232 = n1067 & n1221 & n1229 & n1227 & n1228 & n1097 & n1230 & n1231; + assign n1233 = (n746 | n1844) & (~Poutreg_37_ | n869); + assign n1234 = (~Poutreg_36_ | n869) & (~Poutreg_28_ | Pcount_0_); + assign n1235 = n1149 | n1044 | ~n1146; + assign n1236 = ~n1039 | ~n1149; + assign n1237 = n1235 & (~n996 | n1146) & n1236; + assign n1238 = n1949 & (~n1017 | n1057 | n1146); + assign n1239 = ~n993 | n1017 | n1237; + assign n1240 = (n1022 | ~n1050) & (~n1670 | n1687); + assign n1241 = n1240 & n1012 & n1238 & n1043 & n1003 & n1239; + assign n1242 = (n746 | n1845) & (~Poutreg_35_ | n869); + assign n1243 = (~Poutreg_34_ | n869) & (~Poutreg_26_ | Pcount_0_); + assign n1244 = n1846 & (~n1078 | n1093) & ~n1951; + assign n1245 = (n1222 | n1089) & (n1062 | n1680); + assign n1246 = n1225 & n1679 & (n1083 | n1220); + assign n1247 = n1246 & n1244 & n1221 & n1070 & n1082 & n1245; + assign n1248 = (n746 | n1847) & (~Poutreg_33_ | n869); + assign n1249 = (~Poutreg_32_ | n869) & (~Poutreg_24_ | Pcount_0_); + assign n1250 = n1276 | n1382; + assign n1251 = ~n1281 | ~n1285; + assign n1252 = (~n1258 | ~n1259) & (n1250 | n1251); + assign n1253 = n1697 | n1251 | ~n1276; + assign n1254 = n1276 | n1265 | n1384; + assign n1255 = n1253 & n1254 & (n1252 | ~n1317); + assign n1256 = n1644 & n1271; + assign n1257 = n1258 & ~n1276 & n1382; + assign n1258 = ~n1281 & n1285; + assign n1259 = n1276 & ~n1382; + assign n1260 = n1256 & (n1257 | (n1258 & n1259)); + assign n1261 = n1268 | n1251 | ~n1259; + assign n1262 = ~n1325 | ~n1382; + assign n1263 = n1281 | n1268; + assign n1264 = ~n1260 & n1261 & (n1262 | n1263); + assign n1265 = ~n1271 | n1644; + assign n1266 = ~n1276 | ~n1382; + assign n1267 = ~n1258 | n1265 | n1266; + assign n1268 = n1271 | ~n1644; + assign n1269 = ~n1376 | n1268 | ~n1325; + assign n1270 = ~n1256 | n1250 | n1251; + assign n1271 = ~Pdata_44_ ^ ~PC_7_; + assign n1272 = n1644 | ~n1315 | ~n1382; + assign n1273 = ~n1281 | n1271 | n1272; + assign n1274 = n1384 | n1268 | ~n1276; + assign n1275 = n1952 & (n1265 | n1262 | n1281); + assign n1276 = ~Pdata_39_ ^ ~PC_22_; + assign n1277 = ~n1382 | n1263 | ~n1285; + assign n1278 = n1274 & n1275 & (n1276 | n1277); + assign n1279 = (~n1258 & n1276) | (n1251 & (~n1258 | ~n1276)); + assign n1280 = n1279 & (~n1281 | ~n1315); + assign n1281 = ~Pdata_41_ ^ ~PC_11_; + assign n1282 = ~n1376 & (n1281 | ~n1382); + assign n1283 = ~n1317 | n1384; + assign n1284 = n1283 & (~n1256 | n1282 | ~n1285); + assign n1285 = ~Pdata_40_ ^ ~PC_18_; + assign n1286 = (~n1258 | n1276) & (~n1281 | n1285); + assign n1287 = (n1325 & ~n1644) | (~n1280 & (n1325 | n1644)); + assign n1288 = ~n1382 & ~n1271 & n1287; + assign n1289 = n1272 | n1281; + assign n1290 = (n746 | n1849) & (~Poutreg_31_ | n869); + assign n1291 = (~Poutreg_30_ | n869) & (~Poutreg_22_ | Pcount_0_); + assign n1292 = ~Pdata_59_ ^ ~PD_5_; + assign n1293 = ~n1691 | n1292 | ~n1641; + assign n1294 = ~n1690 | ~n1172 | ~n1173; + assign n1295 = ~n1190 & ~n1641; + assign n1296 = n1292 & ~n1300; + assign n1297 = n1295 & (~n1170 | (n1173 & n1296)); + assign n1298 = n1299 & ~n1642; + assign n1299 = ~Pdata_56_ ^ ~PD_20_; + assign n1300 = ~Pdata_55_ ^ ~PD_15_; + assign n1301 = ~n1190 & (n1298 | (n1299 & n1300)); + assign n1302 = n1299 & n1642; + assign n1303 = n1190 & ~n1641; + assign n1304 = n1302 & n1303; + assign n1305 = (n746 | n1852) & (~Poutreg_29_ | n869); + assign n1306 = (~Poutreg_28_ | n869) & (~Poutreg_20_ | Pcount_0_); + assign n1307 = ~n1308 & (~n878 | ~n1397); + assign n1308 = n887 & n888; + assign n1309 = n1308 & n876; + assign n1310 = ~n1398 & (~n1728 | (n896 & ~n1633)); + assign n1311 = ~n1633 | n1653; + assign n1312 = n1311 | ~n1649; + assign n1313 = (n746 | n1854) & (~Poutreg_27_ | n869); + assign n1314 = (~Poutreg_26_ | n869) & (~Poutreg_18_ | Pcount_0_); + assign n1315 = n1276 & ~n1285; + assign n1316 = ~n1281 & ~n1382; + assign n1317 = ~n1271 & ~n1644; + assign n1318 = n1315 & n1316 & (n1317 | n1256); + assign n1319 = n1697 | n1281 | ~n1325; + assign n1320 = ~n1318 & n1319 & (~n1257 | ~n1317); + assign n1321 = ~n1317 | n1251 | ~n1259; + assign n1322 = ~n1315 | n1268 | n1282; + assign n1323 = n1266 & n1250; + assign n1324 = ~n1258 | n1323 | ~n1705; + assign n1325 = ~n1276 & ~n1285; + assign n1326 = ~n1382 & ~n1263 & n1325; + assign n1327 = n1644 & ~n1276 & ~n1384; + assign n1328 = n1327 & n1271; + assign n1329 = (~Poutreg_25_ | n869) & (n746 | ~n1997); + assign n1330 = (~Poutreg_24_ | n869) & (~Poutreg_16_ | Pcount_0_); + assign n1331 = ~n914 | n1646; + assign n1332 = ~n924 & n1331 & (n906 | ~n915); + assign n1333 = ~n906 | n938; + assign n1334 = (~n921 | n1332) & (~n1338 | ~n1658); + assign n1335 = ~n1990 & n1333 & n939 & n905 & n910 & n1334; + assign n1336 = (n746 | n1856) & (~Poutreg_23_ | n869); + assign n1337 = (~Poutreg_22_ | n869) & (~Poutreg_14_ | Pcount_0_); + assign n1338 = ~Pdata_33_ ^ ~PC_10_; + assign n1339 = n921 & (n914 | n1338); + assign n1340 = (n906 & ~n1729) | (n938 & (~n906 | ~n1729)); + assign n1341 = n939 & ~n1662; + assign n1342 = n1961 | n1962 | n920 | ~n1338; + assign n1343 = n903 & (~n914 | n1659); + assign n1344 = ~n1963 & n1342 & n1341 & n910 & n1340 & n1343; + assign n1345 = (n746 | n1857) & (~Poutreg_21_ | n869); + assign n1346 = (~Poutreg_20_ | n869) & (~Poutreg_12_ | Pcount_0_); + assign n1347 = ~n1061 | n1076 | ~n1222; + assign n1348 = n1347 & (n1061 | ~n1076); + assign n1349 = ~n1062 & n1087; + assign n1350 = n1349 & ~n1061 & n1222; + assign n1351 = ~n1076 & ~n1222; + assign n1352 = n1076 & n1062 & n1222; + assign n1353 = ~n1674 & (n1351 | n1352); + assign n1354 = (n746 | n1860) & (~Poutreg_19_ | n869); + assign n1355 = (~Poutreg_18_ | n869) & (~Poutreg_10_ | Pcount_0_); + assign n1356 = n1302 & n1296 & n1303; + assign n1357 = n1172 & ~n1174 & n1298; + assign n1358 = n1641 & n1190; + assign n1359 = (~n1642 & n1702) | (n1174 & (n1642 | n1702)); + assign n1360 = n1359 & ~n1299 & n1358; + assign n1361 = n1298 & ~n1300 & ~n1641; + assign n1362 = ~n1292 & (n1361 | ~n1370); + assign n1363 = (~Poutreg_17_ | n869) & (n746 | ~n1998); + assign n1364 = (~Poutreg_16_ | n869) & (~Poutreg_8_ | Pcount_0_); + assign n1365 = n1702 | ~n1299 | ~n1694; + assign n1366 = n1692 | n1299; + assign n1367 = n1299 | n1179; + assign n1368 = n1365 & n1366 & (~n1358 | n1367); + assign n1369 = n1966 & (n1190 | ~n1300 | n1689); + assign n1370 = ~n1299 | n1688; + assign n1371 = ~n1361 & (~n1641 | (n1369 & n1370)); + assign n1372 = ~n1298 | n1179 | n1190; + assign n1373 = n1303 & (~n1693 | ~n1695); + assign n1374 = (n746 | n1863) & (~Poutreg_15_ | n869); + assign n1375 = (~Poutreg_14_ | n869) & (~Poutreg_6_ | Pcount_0_); + assign n1376 = n1281 & ~n1382; + assign n1377 = ~n1285 & n1376; + assign n1378 = n1263 | n1323; + assign n1379 = (n746 | n1864) & (~Poutreg_13_ | n869); + assign n1380 = (~Poutreg_12_ | n869) & (~Poutreg_4_ | Pcount_0_); + assign n1381 = n1317 | ~n1382; + assign n1382 = ~Pdata_43_ ^ ~PC_25_; + assign n1383 = ~n1285 & n1381 & (~n1263 | n1382); + assign n1384 = n1251 | ~n1382; + assign n1385 = n1277 & ~n1383 & (~n1271 | n1384); + assign n1386 = n1698 & n1321 & n1278 & n1320; + assign n1387 = (n1276 & n1385) | (n1283 & (~n1276 | n1385)); + assign n1388 = n1705 | n1262 | ~n1281; + assign n1389 = ~n1644 | n1250 | ~n1258; + assign n1390 = (n1280 | n1697) & (n1382 | n1706); + assign n1391 = n1390 & n1388 & n1387 & n1386 & n1264 & n1389; + assign n1392 = (n746 | n1865) & (~Poutreg_11_ | n869); + assign n1393 = (~Poutreg_10_ | n869) & (~Poutreg_2_ | Pcount_0_); + assign n1394 = ~n872 & n1397; + assign n1395 = n887 & ~n1634; + assign n1396 = n897 & n1394 & (n1395 | n878); + assign n1397 = ~Pdata_47_ ^ ~PD_12_; + assign n1398 = ~Pdata_52_ ^ ~PD_26_; + assign n1399 = ~n1972 | n1397 | n1398; + assign n1400 = n881 | ~n894; + assign n1401 = (n746 | n1866) & (~Poutreg_9_ | n869); + assign n1402 = (~Poutreg_8_ | n869) & (~Poutreg_0_ | Pcount_0_); + assign n1403 = Pcount_0_ | n1404; + assign n1404 = n837 | Preset_0_; + assign n1405 = n1403 & (Pcount_1_ | n1404); + assign n1406 = n1405 & (Pcount_2_ | n1404); + assign n1407 = Pcount_3_ | n1648; + assign n1408 = n746 & n1407 & (Pcount_0_ | ~n1798); + assign n1409 = (~PC_26_ | n1712) & (~PC_0_ | n1713); + assign n1410 = (~PC_25_ | n1709) & (~PC_1_ | n1711); + assign n1411 = (~PC_27_ | n1718) & n1867; + assign n1412 = n1411 & n1409 & n1410; + assign n1413 = (~PC_27_ | n1713) & (~PC_25_ | n1712); + assign n1414 = (~PC_24_ | n1709) & (~PC_0_ | n1711); + assign n1415 = (~PC_26_ | n1718) & n1868; + assign n1416 = n1415 & n1413 & n1414; + assign n1417 = (~PC_26_ | n1713) & (~PC_24_ | n1712); + assign n1418 = (~PC_27_ | n1711) & (~PC_23_ | n1709); + assign n1419 = (~PC_25_ | n1718) & n1869; + assign n1420 = n1419 & n1417 & n1418; + assign n1421 = (~PC_25_ | n1713) & (~PC_23_ | n1712); + assign n1422 = (~PC_26_ | n1711) & (~PC_22_ | n1709); + assign n1423 = (~PC_24_ | n1718) & n1870; + assign n1424 = n1423 & n1421 & n1422; + assign n1425 = (~PC_24_ | n1713) & (~PC_22_ | n1712); + assign n1426 = (~PC_25_ | n1711) & (~PC_21_ | n1709); + assign n1427 = (~PC_23_ | n1718) & n1871; + assign n1428 = n1427 & n1425 & n1426; + assign n1429 = (~PC_23_ | n1713) & (~PC_21_ | n1712); + assign n1430 = (~PC_24_ | n1711) & (~PC_20_ | n1709); + assign n1431 = (~PC_22_ | n1718) & n1872; + assign n1432 = n1431 & n1429 & n1430; + assign n1433 = (~PC_22_ | n1713) & (~PC_20_ | n1712); + assign n1434 = (~PC_23_ | n1711) & (~PC_19_ | n1709); + assign n1435 = (~PC_21_ | n1718) & n1873; + assign n1436 = n1435 & n1433 & n1434; + assign n1437 = (~PC_21_ | n1713) & (~PC_19_ | n1712); + assign n1438 = (~PC_22_ | n1711) & (~PC_18_ | n1709); + assign n1439 = (~PC_20_ | n1718) & n1874; + assign n1440 = n1439 & n1437 & n1438; + assign n1441 = (~PC_20_ | n1713) & (~PC_18_ | n1712); + assign n1442 = (~PC_21_ | n1711) & (~PC_17_ | n1709); + assign n1443 = (~PC_19_ | n1718) & n1875; + assign n1444 = n1443 & n1441 & n1442; + assign n1445 = (~PC_19_ | n1713) & (~PC_17_ | n1712); + assign n1446 = (~PC_20_ | n1711) & (~PC_16_ | n1709); + assign n1447 = (~PC_18_ | n1718) & n1876; + assign n1448 = n1447 & n1445 & n1446; + assign n1449 = (~PC_18_ | n1713) & (~PC_16_ | n1712); + assign n1450 = (~PC_19_ | n1711) & (~PC_15_ | n1709); + assign n1451 = (~PC_17_ | n1718) & n1877; + assign n1452 = n1451 & n1449 & n1450; + assign n1453 = (~PC_17_ | n1713) & (~PC_15_ | n1712); + assign n1454 = (~PC_18_ | n1711) & (~PC_14_ | n1709); + assign n1455 = (~PC_16_ | n1718) & n1878; + assign n1456 = n1455 & n1453 & n1454; + assign n1457 = (~PC_16_ | n1713) & (~PC_14_ | n1712); + assign n1458 = (~PC_17_ | n1711) & (~PC_13_ | n1709); + assign n1459 = (~PC_15_ | n1718) & n1879; + assign n1460 = n1459 & n1457 & n1458; + assign n1461 = (~PC_15_ | n1713) & (~PC_13_ | n1712); + assign n1462 = (~PC_16_ | n1711) & (~PC_12_ | n1709); + assign n1463 = (~PC_14_ | n1718) & n1880; + assign n1464 = n1463 & n1461 & n1462; + assign n1465 = (~PC_14_ | n1713) & (~PC_12_ | n1712); + assign n1466 = (~PC_15_ | n1711) & (~PC_11_ | n1709); + assign n1467 = (~PC_13_ | n1718) & n1881; + assign n1468 = n1467 & n1465 & n1466; + assign n1469 = (~PC_13_ | n1713) & (~PC_11_ | n1712); + assign n1470 = (~PC_14_ | n1711) & (~PC_10_ | n1709); + assign n1471 = (~PC_12_ | n1718) & n1882; + assign n1472 = n1471 & n1469 & n1470; + assign n1473 = (~PC_12_ | n1713) & (~PC_10_ | n1712); + assign n1474 = (~PC_13_ | n1711) & (~PC_9_ | n1709); + assign n1475 = (~PC_11_ | n1718) & n1883; + assign n1476 = n1475 & n1473 & n1474; + assign n1477 = (~PC_11_ | n1713) & (~PC_9_ | n1712); + assign n1478 = (~PC_12_ | n1711) & (~PC_8_ | n1709); + assign n1479 = (~PC_10_ | n1718) & n1884; + assign n1480 = n1479 & n1477 & n1478; + assign n1481 = (~PC_10_ | n1713) & (~PC_8_ | n1712); + assign n1482 = (~PC_11_ | n1711) & (~PC_7_ | n1709); + assign n1483 = (~PC_9_ | n1718) & n1885; + assign n1484 = n1483 & n1481 & n1482; + assign n1485 = (~PC_9_ | n1713) & (~PC_7_ | n1712); + assign n1486 = (~PC_10_ | n1711) & (~PC_6_ | n1709); + assign n1487 = (~PC_8_ | n1718) & n1886; + assign n1488 = n1487 & n1485 & n1486; + assign n1489 = (~PC_8_ | n1713) & (~PC_6_ | n1712); + assign n1490 = (~PC_9_ | n1711) & (~PC_5_ | n1709); + assign n1491 = (~PC_7_ | n1718) & n1887; + assign n1492 = n1491 & n1489 & n1490; + assign n1493 = (~PC_7_ | n1713) & (~PC_5_ | n1712); + assign n1494 = (~PC_8_ | n1711) & (~PC_4_ | n1709); + assign n1495 = (~PC_6_ | n1718) & n1888; + assign n1496 = n1495 & n1493 & n1494; + assign n1497 = (~PC_6_ | n1713) & (~PC_4_ | n1712); + assign n1498 = (~PC_7_ | n1711) & (~PC_3_ | n1709); + assign n1499 = (~PC_5_ | n1718) & n1889; + assign n1500 = n1499 & n1497 & n1498; + assign n1501 = (~PC_5_ | n1713) & (~PC_3_ | n1712); + assign n1502 = (~PC_6_ | n1711) & (~PC_2_ | n1709); + assign n1503 = (~PC_4_ | n1718) & n1890; + assign n1504 = n1503 & n1501 & n1502; + assign n1505 = (~PC_4_ | n1713) & (~PC_2_ | n1712); + assign n1506 = (~PC_5_ | n1711) & (~PC_1_ | n1709); + assign n1507 = (~PC_3_ | n1718) & n1891; + assign n1508 = n1507 & n1505 & n1506; + assign n1509 = (~PC_3_ | n1713) & (~PC_1_ | n1712); + assign n1510 = (~PC_4_ | n1711) & (~PC_0_ | n1709); + assign n1511 = (~PC_2_ | n1718) & n1892; + assign n1512 = n1511 & n1509 & n1510; + assign n1513 = (~PC_2_ | n1713) & (~PC_0_ | n1712); + assign n1514 = (~PC_27_ | n1709) & (~PC_3_ | n1711); + assign n1515 = (~PC_1_ | n1718) & n1893; + assign n1516 = n1515 & n1513 & n1514; + assign n1517 = (~PC_27_ | n1712) & (~PC_1_ | n1713); + assign n1518 = (~PC_26_ | n1709) & (~PC_2_ | n1711); + assign n1519 = (~PC_0_ | n1718) & n1894; + assign n1520 = n1519 & n1517 & n1518; + assign n1521 = (~PD_26_ | n1712) & (~PD_0_ | n1713); + assign n1522 = (~PD_25_ | n1709) & (~PD_1_ | n1711); + assign n1523 = (~PD_27_ | n1718) & n1895; + assign n1524 = n1523 & n1521 & n1522; + assign n1525 = (~PD_27_ | n1713) & (~PD_25_ | n1712); + assign n1526 = (~PD_24_ | n1709) & (~PD_0_ | n1711); + assign n1527 = (~PD_26_ | n1718) & n1896; + assign n1528 = n1527 & n1525 & n1526; + assign n1529 = (~PD_26_ | n1713) & (~PD_24_ | n1712); + assign n1530 = (~PD_27_ | n1711) & (~PD_23_ | n1709); + assign n1531 = (~PD_25_ | n1718) & n1897; + assign n1532 = n1531 & n1529 & n1530; + assign n1533 = (~PD_25_ | n1713) & (~PD_23_ | n1712); + assign n1534 = (~PD_26_ | n1711) & (~PD_22_ | n1709); + assign n1535 = (~PD_24_ | n1718) & n1898; + assign n1536 = n1535 & n1533 & n1534; + assign n1537 = (~PD_24_ | n1713) & (~PD_22_ | n1712); + assign n1538 = (~PD_25_ | n1711) & (~PD_21_ | n1709); + assign n1539 = (~PD_23_ | n1718) & n1899; + assign n1540 = n1539 & n1537 & n1538; + assign n1541 = (~PD_23_ | n1713) & (~PD_21_ | n1712); + assign n1542 = (~PD_24_ | n1711) & (~PD_20_ | n1709); + assign n1543 = (~PD_22_ | n1718) & n1900; + assign n1544 = n1543 & n1541 & n1542; + assign n1545 = (~PD_22_ | n1713) & (~PD_20_ | n1712); + assign n1546 = (~PD_23_ | n1711) & (~PD_19_ | n1709); + assign n1547 = (~PD_21_ | n1718) & n1901; + assign n1548 = n1547 & n1545 & n1546; + assign n1549 = (~PD_21_ | n1713) & (~PD_19_ | n1712); + assign n1550 = (~PD_22_ | n1711) & (~PD_18_ | n1709); + assign n1551 = (~PD_20_ | n1718) & n1902; + assign n1552 = n1551 & n1549 & n1550; + assign n1553 = (~PD_20_ | n1713) & (~PD_18_ | n1712); + assign n1554 = (~PD_21_ | n1711) & (~PD_17_ | n1709); + assign n1555 = (~PD_19_ | n1718) & n1903; + assign n1556 = n1555 & n1553 & n1554; + assign n1557 = (~PD_19_ | n1713) & (~PD_17_ | n1712); + assign n1558 = (~PD_20_ | n1711) & (~PD_16_ | n1709); + assign n1559 = (~PD_18_ | n1718) & n1904; + assign n1560 = n1559 & n1557 & n1558; + assign n1561 = (~PD_18_ | n1713) & (~PD_16_ | n1712); + assign n1562 = (~PD_19_ | n1711) & (~PD_15_ | n1709); + assign n1563 = (~PD_17_ | n1718) & n1905; + assign n1564 = n1563 & n1561 & n1562; + assign n1565 = (~PD_17_ | n1713) & (~PD_15_ | n1712); + assign n1566 = (~PD_18_ | n1711) & (~PD_14_ | n1709); + assign n1567 = (~PD_16_ | n1718) & n1906; + assign n1568 = n1567 & n1565 & n1566; + assign n1569 = (~PD_16_ | n1713) & (~PD_14_ | n1712); + assign n1570 = (~PD_17_ | n1711) & (~PD_13_ | n1709); + assign n1571 = (~PD_15_ | n1718) & n1907; + assign n1572 = n1571 & n1569 & n1570; + assign n1573 = (~PD_15_ | n1713) & (~PD_13_ | n1712); + assign n1574 = (~PD_16_ | n1711) & (~PD_12_ | n1709); + assign n1575 = (~PD_14_ | n1718) & n1908; + assign n1576 = n1575 & n1573 & n1574; + assign n1577 = (~PD_14_ | n1713) & (~PD_12_ | n1712); + assign n1578 = (~PD_15_ | n1711) & (~PD_11_ | n1709); + assign n1579 = (~PD_13_ | n1718) & n1909; + assign n1580 = n1579 & n1577 & n1578; + assign n1581 = (~PD_13_ | n1713) & (~PD_11_ | n1712); + assign n1582 = (~PD_14_ | n1711) & (~PD_10_ | n1709); + assign n1583 = (~PD_12_ | n1718) & n1910; + assign n1584 = n1583 & n1581 & n1582; + assign n1585 = (~PD_12_ | n1713) & (~PD_10_ | n1712); + assign n1586 = (~PD_13_ | n1711) & (~PD_9_ | n1709); + assign n1587 = (~PD_11_ | n1718) & n1911; + assign n1588 = n1587 & n1585 & n1586; + assign n1589 = (~PD_11_ | n1713) & (~PD_9_ | n1712); + assign n1590 = (~PD_12_ | n1711) & (~PD_8_ | n1709); + assign n1591 = (~PD_10_ | n1718) & n1912; + assign n1592 = n1591 & n1589 & n1590; + assign n1593 = (~PD_10_ | n1713) & (~PD_8_ | n1712); + assign n1594 = (~PD_11_ | n1711) & (~PD_7_ | n1709); + assign n1595 = (~PD_9_ | n1718) & n1913; + assign n1596 = n1595 & n1593 & n1594; + assign n1597 = (~PD_9_ | n1713) & (~PD_7_ | n1712); + assign n1598 = (~PD_10_ | n1711) & (~PD_6_ | n1709); + assign n1599 = (~PD_8_ | n1718) & n1914; + assign n1600 = n1599 & n1597 & n1598; + assign n1601 = (~PD_8_ | n1713) & (~PD_6_ | n1712); + assign n1602 = (~PD_9_ | n1711) & (~PD_5_ | n1709); + assign n1603 = (~PD_7_ | n1718) & n1915; + assign n1604 = n1603 & n1601 & n1602; + assign n1605 = (~PD_7_ | n1713) & (~PD_5_ | n1712); + assign n1606 = (~PD_8_ | n1711) & (~PD_4_ | n1709); + assign n1607 = (~PD_6_ | n1718) & n1916; + assign n1608 = n1607 & n1605 & n1606; + assign n1609 = (~PD_6_ | n1713) & (~PD_4_ | n1712); + assign n1610 = (~PD_7_ | n1711) & (~PD_3_ | n1709); + assign n1611 = (~PD_5_ | n1718) & n1917; + assign n1612 = n1611 & n1609 & n1610; + assign n1613 = (~PD_5_ | n1713) & (~PD_3_ | n1712); + assign n1614 = (~PD_6_ | n1711) & (~PD_2_ | n1709); + assign n1615 = (~PD_4_ | n1718) & n1918; + assign n1616 = n1615 & n1613 & n1614; + assign n1617 = (~PD_4_ | n1713) & (~PD_2_ | n1712); + assign n1618 = (~PD_5_ | n1711) & (~PD_1_ | n1709); + assign n1619 = (~PD_3_ | n1718) & n1919; + assign n1620 = n1619 & n1617 & n1618; + assign n1621 = (~PD_3_ | n1713) & (~PD_1_ | n1712); + assign n1622 = (~PD_4_ | n1711) & (~PD_0_ | n1709); + assign n1623 = (~PD_2_ | n1718) & n1920; + assign n1624 = n1623 & n1621 & n1622; + assign n1625 = (~PD_2_ | n1713) & (~PD_0_ | n1712); + assign n1626 = (~PD_27_ | n1709) & (~PD_3_ | n1711); + assign n1627 = (~PD_1_ | n1718) & n1921; + assign n1628 = n1627 & n1625 & n1626; + assign n1629 = (~PD_27_ | n1712) & (~PD_1_ | n1713); + assign n1630 = (~PD_26_ | n1709) & (~PD_2_ | n1711); + assign n1631 = (~PD_0_ | n1718) & n1922; + assign n1632 = n1631 & n1629 & n1630; + assign n1633 = ~Pdata_48_ ^ ~PD_23_; + assign n1634 = ~Pdata_51_ ^ ~PD_18_; + assign n1635 = ~Pdata_45_ ^ ~PC_26_; + assign n1636 = ~Pdata_38_ ^ ~PC_5_; + assign n1637 = n993 & (~n1002 | (n1039 & ~n1149)); + assign n1638 = ~Pdata_52_ ^ ~PD_11_; + assign n1639 = ~Pdata_56_ ^ ~PD_19_; + assign n1640 = ~n1639 ^ ~n1133; + assign n1641 = ~Pdata_60_ ^ ~PD_24_; + assign n1642 = ~Pdata_58_ ^ ~PD_27_; + assign n1643 = ~n1062 ^ n1076; + assign n1644 = ~Pdata_42_ ^ ~PC_3_; + assign n1645 = ~n1649 & (~n887 | ~n1633); + assign n1646 = ~n906 ^ n1338; + assign n1647 = ~Pencrypt_mode_0_ ^ Pencrypt_0_; + assign n1648 = ~Pcount_0_ | ~Pcount_2_ | ~Pcount_1_; + assign n1649 = ~n887 & ~n1634; + assign n1650 = n887 & n1634; + assign n1651 = ~n1398 & ~n1633; + assign n1652 = n1649 & n876; + assign n1653 = n1398 | ~n872 | ~n1397; + assign n1654 = ~n1397 | ~n872 | ~n876; + assign n1655 = ~n1338 | n916 | ~n920; + assign n1656 = n920 & n901; + assign n1657 = n914 & ~n1338; + assign n1658 = ~n920 & ~n914 & n916; + assign n1659 = ~n1338 | n920 | ~n921; + assign n1660 = n1656 & ~n906 & n914; + assign n1661 = n906 & n1657 & n935; + assign n1662 = n1660 | n1661 | n925 | n927; + assign n1663 = n980 | n972; + assign n1664 = n972 | ~n980; + assign n1665 = ~n980 | n1635; + assign n1666 = n956 | n1030 | n980; + assign n1667 = n1665 | n956 | n981; + assign n1668 = n1664 | n956 | n958; + assign n1669 = n956 | ~n980 | n1030 | ~n1635; + assign n1670 = n993 | n1146; + assign n1671 = n989 | n993; + assign n1672 = n1076 & ~n1222; + assign n1673 = ~n1061 | n1071; + assign n1674 = ~n1061 | n1087; + assign n1675 = ~n1062 & ~n1674; + assign n1676 = n1078 | n1347; + assign n1677 = n1061 & n1087; + assign n1678 = ~n1088 & n1085 & n1086; + assign n1679 = n1078 | n1071 | ~n1076; + assign n1680 = ~n1078 | n1087 | n1347; + assign n1681 = ~n1102 & ~n1120; + assign n1682 = n1120 & n1133; + assign n1683 = n1102 & n1682; + assign n1684 = ~n1102 | n1119; + assign n1685 = ~n1133 | ~n1681; + assign n1686 = ~n1104 | n1133; + assign n1687 = n989 | ~n996; + assign n1688 = ~n1642 | n1190 | n1300; + assign n1689 = n1299 | ~n1642; + assign n1690 = n1300 & n1292; + assign n1691 = ~n1299 & ~n1688; + assign n1692 = ~n1174 | ~n1303; + assign n1693 = n1179 | ~n1302; + assign n1694 = ~n1172 & ~n1303; + assign n1695 = n1367 | n1642; + assign n1696 = n1639 & n1133; + assign n1697 = n1382 | n1265; + assign n1698 = n1269 & n1267 & n1270 & n1273; + assign n1699 = n1255 & n1698 & n1264; + assign n1700 = n1303 & ~n1642 & n1690; + assign n1701 = n1190 | n1695; + assign n1702 = ~n1174 & ~n1690; + assign n1703 = ~n1297 & n1294 & n1187 & n1293; + assign n1704 = n886 & n1139; + assign n1705 = n1317 | n1256; + assign n1706 = ~n1705 | ~n1281 | ~n1325; + assign n1707 = n1404 | ~n1717; + assign n1708 = Pencrypt_mode_0_ | n1707; + assign n1709 = ~n1408 | n1708; + assign n1710 = ~Pencrypt_mode_0_ | n1707; + assign n1711 = ~n1408 | n1710; + assign n1712 = n1408 | n1708; + assign n1713 = n1408 | n1710; + assign n1714 = Preset_0_ | ~n837; + assign n1715 = Pencrypt_0_ | n1714; + assign n1716 = ~Pencrypt_0_ | n1714; + assign n1717 = n1647 | n746; + assign n1718 = n1404 | n1717; + assign n1719 = n1923 & (~n900 | n913 | ~n916); + assign n1720 = ~n1925 & (~n906 | (n914 & n935)); + assign n1721 = (n934 & ~n1338) | (n926 & (n934 | n1338)); + assign n1722 = n956 & (n961 | (~n958 & n981)); + assign n1723 = (~n980 & ~n1722) | (n975 & (n980 | ~n1722)); + assign n1724 = (~n954 & (~n956 | ~n1664)) | (n956 & ~n1664); + assign n1725 = ~n1936 & (n887 | ~n892 | n1397); + assign n1726 = (n1641 & n1691) | (~n1370 & (~n1641 | n1691)); + assign n1727 = n1943 & (n1199 | ~n1201); + assign n1728 = (n1397 & n1645) | (~n878 & (~n1397 | n1645)); + assign n1729 = n920 & (n1339 | (n1657 & n912)); + assign n1730 = n892 & (n896 | (~n887 & n888)); + assign n1731 = n1650 & (n892 | (~n1397 & n1398)); + assign n1732 = (n746 & n1863) | (~Pdata_in_6_ & (~n746 | n1863)); + assign n1733 = (n746 & n1856) | (~Pinreg_6_ & (~n746 | n1856)); + assign n1734 = (n746 & n1849) | (~Pinreg_14_ & (~n746 | n1849)); + assign n1735 = (n746 & n1843) | (~Pinreg_22_ & (~n746 | n1843)); + assign n1736 = (n746 & n1836) | (~Pinreg_30_ & (~n746 | n1836)); + assign n1737 = (n746 & n1820) | (~Pinreg_38_ & (~n746 | n1820)); + assign n1738 = (n746 & n1810) | (~Pinreg_46_ & (~n746 | n1810)); + assign n1739 = (n746 & n899) | (~Pinreg_54_ & (~n746 | n899)); + assign n1740 = (n746 & n1864) | (~Pdata_in_4_ & (~n746 | n1864)); + assign n1741 = (n746 & n1857) | (~Pinreg_4_ & (~n746 | n1857)); + assign n1742 = (n746 & n1852) | (~Pinreg_12_ & (~n746 | n1852)); + assign n1743 = (n746 & n1844) | (~Pinreg_20_ & (~n746 | n1844)); + assign n1744 = (n746 & n1837) | (~Pinreg_28_ & (~n746 | n1837)); + assign n1745 = (n746 & n1829) | (~Pinreg_36_ & (~n746 | n1829)); + assign n1746 = (n746 & n1815) | (~Pinreg_44_ & (~n746 | n1815)); + assign n1747 = (n746 & n931) | (~Pinreg_52_ & (~n746 | n931)); + assign n1748 = (n746 & n1865) | (~Pdata_in_2_ & (~n746 | n1865)); + assign n1749 = (n746 & n1860) | (~Pinreg_2_ & (~n746 | n1860)); + assign n1750 = (n746 & n1854) | (~Pinreg_10_ & (~n746 | n1854)); + assign n1751 = (n746 & n1845) | (~Pinreg_18_ & (~n746 | n1845)); + assign n1752 = (n746 & n1838) | (~Pinreg_26_ & (~n746 | n1838)); + assign n1753 = (n746 & n1834) | (~Pinreg_34_ & (~n746 | n1834)); + assign n1754 = (n746 & n1816) | (~Pinreg_42_ & (~n746 | n1816)); + assign n1755 = (n746 & n948) | (~Pinreg_50_ & (~n746 | n948)); + assign n1756 = (n746 & n1866) | (~Pdata_in_0_ & (~n746 | n1866)); + assign n1757 = (~Pinreg_0_ & (~n746 | ~n1998)) | (n746 & ~n1998); + assign n1758 = (~Pinreg_8_ & (~n746 | ~n1997)) | (n746 & ~n1997); + assign n1759 = (n746 & n1847) | (~Pinreg_16_ & (~n746 | n1847)); + assign n1760 = (n746 & n1840) | (~Pinreg_24_ & (~n746 | n1840)); + assign n1761 = (~Pinreg_32_ & (~n746 | ~n1996)) | (n746 & ~n1996); + assign n1762 = (n746 & n1817) | (~Pinreg_40_ & (~n746 | n1817)); + assign n1763 = (n746 & n976) | (~Pinreg_48_ & (~n746 | n976)); + assign n1764 = (~Pdata_63_ & n746) | (~Pdata_in_7_ & (~Pdata_63_ | ~n746)); + assign n1765 = (~Pdata_62_ & n746) | (~Pinreg_7_ & (~Pdata_62_ | ~n746)); + assign n1766 = (~Pdata_61_ & n746) | (~Pinreg_15_ & (~Pdata_61_ | ~n746)); + assign n1767 = (~Pdata_60_ & n746) | (~Pinreg_23_ & (~Pdata_60_ | ~n746)); + assign n1768 = (~Pdata_59_ & n746) | (~Pinreg_31_ & (~Pdata_59_ | ~n746)); + assign n1769 = (~Pdata_58_ & n746) | (~Pinreg_39_ & (~Pdata_58_ | ~n746)); + assign n1770 = (~Pdata_57_ & n746) | (~Pinreg_47_ & (~Pdata_57_ | ~n746)); + assign n1771 = (~Pdata_56_ & n746) | (~Pinreg_55_ & (~Pdata_56_ | ~n746)); + assign n1772 = (~Pdata_55_ & n746) | (~Pdata_in_5_ & (~Pdata_55_ | ~n746)); + assign n1773 = (~Pdata_54_ & n746) | (~Pinreg_5_ & (~Pdata_54_ | ~n746)); + assign n1774 = (~Pdata_53_ & n746) | (~Pinreg_13_ & (~Pdata_53_ | ~n746)); + assign n1775 = (~Pdata_52_ & n746) | (~Pinreg_21_ & (~Pdata_52_ | ~n746)); + assign n1776 = (~Pdata_51_ & n746) | (~Pinreg_29_ & (~Pdata_51_ | ~n746)); + assign n1777 = (~Pdata_50_ & n746) | (~Pinreg_37_ & (~Pdata_50_ | ~n746)); + assign n1778 = (~Pdata_49_ & n746) | (~Pinreg_45_ & (~Pdata_49_ | ~n746)); + assign n1779 = (~Pdata_48_ & n746) | (~Pinreg_53_ & (~Pdata_48_ | ~n746)); + assign n1780 = (~Pdata_47_ & n746) | (~Pdata_in_3_ & (~Pdata_47_ | ~n746)); + assign n1781 = (~Pdata_46_ & n746) | (~Pinreg_3_ & (~Pdata_46_ | ~n746)); + assign n1782 = (~Pdata_45_ & n746) | (~Pinreg_11_ & (~Pdata_45_ | ~n746)); + assign n1783 = (~Pdata_44_ & n746) | (~Pinreg_19_ & (~Pdata_44_ | ~n746)); + assign n1784 = (~Pdata_43_ & n746) | (~Pinreg_27_ & (~Pdata_43_ | ~n746)); + assign n1785 = (~Pdata_42_ & n746) | (~Pinreg_35_ & (~Pdata_42_ | ~n746)); + assign n1786 = (~Pdata_41_ & n746) | (~Pinreg_43_ & (~Pdata_41_ | ~n746)); + assign n1787 = (~Pdata_40_ & n746) | (~Pinreg_51_ & (~Pdata_40_ | ~n746)); + assign n1788 = (~Pdata_39_ & n746) | (~Pdata_in_1_ & (~Pdata_39_ | ~n746)); + assign n1789 = (~Pdata_38_ & n746) | (~Pinreg_1_ & (~Pdata_38_ | ~n746)); + assign n1790 = (~Pdata_37_ & n746) | (~Pinreg_9_ & (~Pdata_37_ | ~n746)); + assign n1791 = (~Pdata_36_ & n746) | (~Pinreg_17_ & (~Pdata_36_ | ~n746)); + assign n1792 = (~Pdata_35_ & n746) | (~Pinreg_25_ & (~Pdata_35_ | ~n746)); + assign n1793 = (~Pdata_34_ & n746) | (~Pinreg_33_ & (~Pdata_34_ | ~n746)); + assign n1794 = (~Pdata_33_ & n746) | (~Pinreg_41_ & (~Pdata_33_ | ~n746)); + assign n1795 = (~Pdata_32_ & n746) | (~Pinreg_49_ & (~Pdata_32_ | ~n746)); + assign n1796 = (~Pcount_2_ | n1405) & n1974; + assign n1797 = (~Pcount_1_ | n1403) & n1975; + assign n1798 = ~n1976 & (~Pcount_1_ | (Pcount_3_ & Pcount_2_)); + assign n1799 = (~Pencrypt_0_ & ~n746) | (~Pencrypt_mode_0_ & (~Pencrypt_0_ | n746)); + assign n1800 = n872 | ~n876 | ~n878 | n1397; + assign n1801 = (~n1395 | n1654) & (n887 | n1311); + assign n1802 = (~n1142 | ~n1397) & (~n1649 | n1653); + assign n1803 = ~n916 | n1338 | n913 | n914; + assign n1804 = ~n1163 | n980 | ~n1161; + assign n1805 = n1665 | ~n981 | ~n1161; + assign n1806 = (n973 | n980) & (n1159 | n1668); + assign n1807 = n968 | n1635 | n981; + assign n1808 = n1807 & (~n958 | n980 | n1030); + assign n1809 = ~n1163 | ~n980 | ~n1161; + assign n1810 = ~Pdata_25_ ^ ~n1980; + assign n1811 = ~n1051 | n1005 | ~n1039; + assign n1812 = ~n1051 | ~n1039 | ~n1049; + assign n1813 = n1812 & (n1013 | n993 | n1056); + assign n1814 = n1146 | n989 | ~n1050; + assign n1815 = ~n1023 ^ ~Pdata_17_; + assign n1816 = ~n1036 ^ ~Pdata_9_; + assign n1817 = ~Pdata_1_ ^ ~n1981; + assign n1818 = ~n1076 | n1077; + assign n1819 = ~n1061 | n1679; + assign n1820 = ~n1098 ^ ~Pdata_26_; + assign n1821 = n1207 | n1117 | ~n1201; + assign n1822 = n1101 | ~n1133; + assign n1823 = n1116 | n1112; + assign n1824 = ~n1201 | n1129 | ~n1132; + assign n1825 = (~n1638 | n1685) & (n1112 | n1211); + assign n1826 = (n1121 | ~n1132) & (~n1681 | n1686); + assign n1827 = ~n1640 | n1200 | n1638; + assign n1828 = n1827 & (n1109 | (~n1105 & n1117)); + assign n1829 = ~n1125 ^ ~Pdata_18_; + assign n1830 = n1686 | n1200 | n1201; + assign n1831 = n1207 | n1121 | n1102; + assign n1832 = n1831 & (n1103 | n1686); + assign n1833 = (n1211 | ~n1683) & (n1205 | n1638); + assign n1834 = ~Pdata_10_ ^ ~n1982; + assign n1835 = (~n1039 | n1053) & (n1005 | n1042); + assign n1836 = ~n1156 ^ ~Pdata_27_; + assign n1837 = ~Pdata_19_ ^ ~n1984; + assign n1838 = ~n1196 ^ ~Pdata_11_; + assign n1839 = (n1202 | n1686) & (n1116 | ~n1683); + assign n1840 = ~Pdata_3_ ^ ~n1985; + assign n1841 = n1682 | ~n1102 | ~n1132; + assign n1842 = ~n1133 | n1102 | ~n1104; + assign n1843 = ~n1215 ^ ~Pdata_28_; + assign n1844 = ~n1232 ^ ~Pdata_20_; + assign n1845 = ~n1241 ^ ~Pdata_12_; + assign n1846 = (n1076 & n1673) | (n1075 & (~n1076 | n1673)); + assign n1847 = ~n1247 ^ ~Pdata_4_; + assign n1848 = (~n1276 | n1284) & (n1286 | n1697); + assign n1849 = ~Pdata_29_ ^ ~n1986; + assign n1850 = n1694 | ~n1296 | ~n1298; + assign n1851 = n1850 & (n1299 | ~n1700); + assign n1852 = ~Pdata_21_ ^ ~n1987; + assign n1853 = (~n892 | n1307) & (n1397 | ~n1652); + assign n1854 = ~Pdata_13_ ^ ~n1988; + assign n1855 = (n1271 | n1262) & (n1265 | n1266); + assign n1856 = ~n1335 ^ ~Pdata_30_; + assign n1857 = ~n1344 ^ ~Pdata_22_; + assign n1858 = n1673 & (~n1062 | ~n1087 | n1348); + assign n1859 = (n1071 | n1076) & (n1089 | ~n1222); + assign n1860 = ~Pdata_14_ ^ ~n1991; + assign n1861 = (n1641 | n1701) & (~n1190 | n1693); + assign n1862 = (~n1292 | n1371) & (n1368 | ~n1642); + assign n1863 = ~Pdata_31_ ^ ~n1993; + assign n1864 = ~Pdata_23_ ^ ~n1994; + assign n1865 = ~n1391 ^ ~Pdata_15_; + assign n1866 = ~Pdata_7_ ^ ~n1995; + assign n1867 = (~Pinreg_48_ | n1716) & (~Pinreg_27_ | n1715); + assign n1868 = (~Pinreg_35_ | n1715) & (~Pinreg_27_ | n1716); + assign n1869 = (~Pinreg_43_ | n1715) & (~Pinreg_35_ | n1716); + assign n1870 = (~Pinreg_51_ | n1715) & (~Pinreg_43_ | n1716); + assign n1871 = (~Pinreg_51_ | n1716) & (~Pdata_in_2_ | n1715); + assign n1872 = (~Pinreg_2_ | n1715) & (~Pdata_in_2_ | n1716); + assign n1873 = (~Pinreg_10_ | n1715) & (~Pinreg_2_ | n1716); + assign n1874 = (~Pinreg_18_ | n1715) & (~Pinreg_10_ | n1716); + assign n1875 = (~Pinreg_26_ | n1715) & (~Pinreg_18_ | n1716); + assign n1876 = (~Pinreg_34_ | n1715) & (~Pinreg_26_ | n1716); + assign n1877 = (~Pinreg_42_ | n1715) & (~Pinreg_34_ | n1716); + assign n1878 = (~Pinreg_50_ | n1715) & (~Pinreg_42_ | n1716); + assign n1879 = (~Pinreg_50_ | n1716) & (~Pdata_in_1_ | n1715); + assign n1880 = (~Pinreg_1_ | n1715) & (~Pdata_in_1_ | n1716); + assign n1881 = (~Pinreg_9_ | n1715) & (~Pinreg_1_ | n1716); + assign n1882 = (~Pinreg_17_ | n1715) & (~Pinreg_9_ | n1716); + assign n1883 = (~Pinreg_25_ | n1715) & (~Pinreg_17_ | n1716); + assign n1884 = (~Pinreg_33_ | n1715) & (~Pinreg_25_ | n1716); + assign n1885 = (~Pinreg_41_ | n1715) & (~Pinreg_33_ | n1716); + assign n1886 = (~Pinreg_49_ | n1715) & (~Pinreg_41_ | n1716); + assign n1887 = (~Pinreg_49_ | n1716) & (~Pdata_in_0_ | n1715); + assign n1888 = (~Pinreg_0_ | n1715) & (~Pdata_in_0_ | n1716); + assign n1889 = (~Pinreg_8_ | n1715) & (~Pinreg_0_ | n1716); + assign n1890 = (~Pinreg_16_ | n1715) & (~Pinreg_8_ | n1716); + assign n1891 = (~Pinreg_24_ | n1715) & (~Pinreg_16_ | n1716); + assign n1892 = (~Pinreg_32_ | n1715) & (~Pinreg_24_ | n1716); + assign n1893 = (~Pinreg_40_ | n1715) & (~Pinreg_32_ | n1716); + assign n1894 = (~Pinreg_48_ | n1715) & (~Pinreg_40_ | n1716); + assign n1895 = (~Pinreg_54_ | n1716) & (~Pdata_in_3_ | n1715); + assign n1896 = (~Pinreg_3_ | n1715) & (~Pdata_in_3_ | n1716); + assign n1897 = (~Pinreg_11_ | n1715) & (~Pinreg_3_ | n1716); + assign n1898 = (~Pinreg_19_ | n1715) & (~Pinreg_11_ | n1716); + assign n1899 = (~Pinreg_19_ | n1716) & (~Pdata_in_4_ | n1715); + assign n1900 = (~Pinreg_4_ | n1715) & (~Pdata_in_4_ | n1716); + assign n1901 = (~Pinreg_12_ | n1715) & (~Pinreg_4_ | n1716); + assign n1902 = (~Pinreg_20_ | n1715) & (~Pinreg_12_ | n1716); + assign n1903 = (~Pinreg_28_ | n1715) & (~Pinreg_20_ | n1716); + assign n1904 = (~Pinreg_36_ | n1715) & (~Pinreg_28_ | n1716); + assign n1905 = (~Pinreg_44_ | n1715) & (~Pinreg_36_ | n1716); + assign n1906 = (~Pinreg_52_ | n1715) & (~Pinreg_44_ | n1716); + assign n1907 = (~Pinreg_52_ | n1716) & (~Pdata_in_5_ | n1715); + assign n1908 = (~Pinreg_5_ | n1715) & (~Pdata_in_5_ | n1716); + assign n1909 = (~Pinreg_13_ | n1715) & (~Pinreg_5_ | n1716); + assign n1910 = (~Pinreg_21_ | n1715) & (~Pinreg_13_ | n1716); + assign n1911 = (~Pinreg_29_ | n1715) & (~Pinreg_21_ | n1716); + assign n1912 = (~Pinreg_37_ | n1715) & (~Pinreg_29_ | n1716); + assign n1913 = (~Pinreg_45_ | n1715) & (~Pinreg_37_ | n1716); + assign n1914 = (~Pinreg_53_ | n1715) & (~Pinreg_45_ | n1716); + assign n1915 = (~Pinreg_53_ | n1716) & (~Pdata_in_6_ | n1715); + assign n1916 = (~Pinreg_6_ | n1715) & (~Pdata_in_6_ | n1716); + assign n1917 = (~Pinreg_14_ | n1715) & (~Pinreg_6_ | n1716); + assign n1918 = (~Pinreg_22_ | n1715) & (~Pinreg_14_ | n1716); + assign n1919 = (~Pinreg_30_ | n1715) & (~Pinreg_22_ | n1716); + assign n1920 = (~Pinreg_38_ | n1715) & (~Pinreg_30_ | n1716); + assign n1921 = (~Pinreg_46_ | n1715) & (~Pinreg_38_ | n1716); + assign n1922 = (~Pinreg_54_ | n1715) & (~Pinreg_46_ | n1716); + assign n1923 = ~n932 | n915 | n916; + assign n1924 = ~n1338 & (n919 | n922 | ~n1719); + assign n1925 = ~n906 & (~n900 | n912 | n916); + assign n1926 = ~n906 & (~n921 | n1338); + assign n1927 = ~n1635 & (~n1723 | (~n951 & ~n981)); + assign n1928 = n958 & n1635 & (~n951 | ~n1666); + assign n1929 = n1078 & (~n1064 | (n1351 & n1675)); + assign n1930 = ~n1062 | ~n1078 | ~n1351 | ~n1677; + assign n1931 = n1201 | n1103 | n1686; + assign n1932 = ~n1201 & (n1106 | (~n1117 & n1132)); + assign n1933 = n1201 & (~n1832 | (~n1638 & n1683)); + assign n1934 = ~n1201 & (n1134 | (n1640 & n1681)); + assign n1935 = (n1308 & ~n1633) | (n896 & (n1308 | n1633)); + assign n1936 = n1397 & (n1652 | (n892 & n887)); + assign n1937 = n872 & (~n1725 | (n893 & n897)); + assign n1938 = n1935 & ~n872 & ~n1398; + assign n1939 = n1160 | ~n1666; + assign n1940 = ~n1635 & (n1162 | (n958 & n1939)); + assign n1941 = ~n1635 | n975 | n980; + assign n1942 = n1702 | ~n1173 | ~n1694; + assign n1943 = n1696 | n1201 | ~n1681; + assign n1944 = ~n1638 & (~n1727 | (n1639 & n1683)); + assign n1945 = ~n1638 | ~n1696 | n1103 | ~n1201; + assign n1946 = ~n1078 | n1347 | ~n1349; + assign n1947 = n993 & ~n1039; + assign n1948 = ~n993 & (n1017 | n1044); + assign n1949 = n1947 | n1948 | ~n1146 | ~n1149; + assign n1950 = n1351 & n1349; + assign n1951 = ~n1078 & (n1950 | (n1352 & n1677)); + assign n1952 = ~n1256 | ~n1281 | ~n1315 | ~n1382; + assign n1953 = ~n1702 & (n1304 | (n1298 & n1358)); + assign n1954 = ~n1702 | ~n1358 | ~n1642; + assign n1955 = ~n1292 & ~n1641 & (n1301 | n1691); + assign n1956 = ~n1641 | n1701; + assign n1957 = n872 & (~n1853 | (n893 & n1651)); + assign n1958 = ~n872 & (n1142 | n1309 | n1310); + assign n1959 = n1281 & (~n1855 | (n1325 & ~n1697)); + assign n1960 = ~n1281 & (~n1977 | (n1315 & ~n1697)); + assign n1961 = n914 & n911; + assign n1962 = ~n914 & (~n913 | n916); + assign n1963 = ~n1338 & (n1658 | (n921 & n926)); + assign n1964 = n1078 & (~n1858 | (~n1073 & n1672)); + assign n1965 = ~n1078 & (~n1090 | n1350 | n1353); + assign n1966 = ~n1190 | n1299 | n1300; + assign n1967 = n1265 | n1276 | n1282 | ~n1285; + assign n1968 = n1276 & n1705 & (n1377 | ~n1384); + assign n1969 = ~n1271 | n1272; + assign n1970 = ~n1271 & (n1327 | (n1316 & n1325)); + assign n1971 = (n872 & n1650) | (n1649 & (~n872 | n1650)); + assign n1972 = (n1633 & n1971) | (n878 & (~n1633 | n1971)); + assign n1973 = (~n872 & ~n1731) | (~n1730 & (n872 | ~n1731)); + assign n1974 = Pcount_2_ | ~Pcount_1_ | ~Pcount_0_ | n1404; + assign n1975 = n1404 | Pcount_1_ | ~Pcount_0_; + assign n1976 = ~Pcount_1_ & (Pcount_3_ | Pcount_2_); + assign n1977 = ~n1256 | n1262; + assign n1978 = n1802 & n891 & n886 & n875 & n882 & ~n895 & ~n898 & n1801; + assign n1979 = ~n1928 & ~n1927 & n1806 & n963 & n1033; + assign n1980 = n1668 & n1029 & ~n985 & n984 & ~n982 & n979 & n963 & n966; + assign n1981 = n1058 & n1055 & ~n1052 & n1045 & n1043 & n999 & n1014 & n1048; + assign n1982 = n1833 & n1131 & n1110 & n1113 & ~n1933 & ~n1934; + assign n1983 = ~n875 | n877 | ~n882 | ~n1139 | n1937 | n1938 | n1141 | n1143; + assign n1984 = n1941 & ~n1940 & n1669 & n1166 & ~n1164 & n979 & n963 & n969; + assign n1985 = n1839 & n1131 & n1107 & n1122 & ~n1944 & n1945; + assign n1986 = n1848 & n1706 & n1699 & n1278 & ~n1288 & n1289; + assign n1987 = n1956 & ~n1955 & n1851 & n1703 & n1171 & n1183 & ~n1953 & n1954; + assign n1988 = n1704 & n1312 & n873 & n882 & ~n1957 & ~n1958; + assign n1989 = n1959 | n1960 | n1328 | ~n1386 | ~n1255 | ~n1322 | ~n1324 | n1326; + assign n1990 = n1646 & n912 & ~n915 & ~n916; + assign n1991 = n1859 & n1678 & n1070 & n1221 & ~n1964 & ~n1965; + assign n1992 = n1362 | n1700 | ~n1703 | ~n1861 | ~n1193 | n1356 | n1357 | n1360; + assign n1993 = n1862 & n1703 & ~n1373 & n1372 & n1178 & n1183; + assign n1994 = n1977 & ~n1970 & n1967 & n1699 & n1320 & n1378 & ~n1968 & n1969; + assign n1995 = n1973 & n1704 & n1400 & n875 & ~n1396 & n1399; + assign n1996 = ~Pdata_2_ ^ ~n1983; + assign n1997 = ~Pdata_5_ ^ ~n1989; + assign n1998 = ~Pdata_6_ ^ ~n1992; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/diffeq/diffeq.v b/openfpga_flow/benchmarks/MCNC_Verilog/diffeq/diffeq.v new file mode 100644 index 000000000..419c09c79 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/diffeq/diffeq.v @@ -0,0 +1,1523 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 09:56:39 2019 + +module diffeq ( clock, + PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_, Pdxport_3_3_, + Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_, Pdxport_8_8_, + Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_, Paport_0_0_, Paport_1_1_, + Paport_2_2_, Paport_3_3_, Paport_4_4_, Paport_5_5_, Paport_6_6_, + Paport_7_7_, Paport_8_8_, Paport_9_9_, Paport_10_10_, Paport_11_11_, + Preset_0_0_, Pready_0_0_, + PDN, Pnext_0_0_, Pover_0_0_ ); + input clock, PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_, + Pdxport_3_3_, Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_, + Pdxport_8_8_, Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_, + Paport_0_0_, Paport_1_1_, Paport_2_2_, Paport_3_3_, Paport_4_4_, + Paport_5_5_, Paport_6_6_, Paport_7_7_, Paport_8_8_, Paport_9_9_, + Paport_10_10_, Paport_11_11_, Preset_0_0_, Pready_0_0_; + output PDN, Pnext_0_0_, Pover_0_0_; + reg N_N4054, N_N3745, N_N4119, N_N3826, N_N3818, N_N3345, N_N3924, + N_N3815, N_N3691, N_N3157, N_N3872, N_N3788, N_N3375, N_N3143, N_N4197, + N_N3843, N_N3426, N_N4118, N_N3580, N_N3175, N_N3071, N_N3808, N_N3923, + N_N3250, N_N4221, N_N3069, N_N3464, N_N3535, N_N3871, N_N3248, N_N4180, + N_N3311, N_N3442, N_N3981, N_N3842, N_N3105, N_N4133, N_N4117, N_N3420, + N_N3761, N_N3062, N_N4071, N_N4227, N_N3807, N_N4145, N_N3922, N_N3516, + N_N3489, N_N4030, N_N3540, N_N3513, N_N4083, N_N3841, N_N4018, N_N3971, + N_N4232, N_N4246, N_N3806, N_N3992, N_N4086, N_N4230, N_N4212, + Pnext_0_0_, N_N3626, N_N3965, N_N3890, NDN3_11, NDN5_10, N_N3786, + N_N4171, NDN5_16, N_N3799, N_N3844, N_N3196, N_N4126, N_N3681, N_N3679, + N_N3340, N_N4116, N_N3810, N_N3235, N_N3283, N_N3716, N_N3701, N_N3921, + N_N3625, N_N3751, N_N3736, N_N3870, N_N4024, N_N3876, N_N3840, N_N4021, + N_N3932, NLC1_2, N_N3805, N_N3700, N_N3735, NLak3_2, NLak3_9, N_N3906, + N_N3388, N_N4057, N_N3011, N_N3346, N_N3677, N_N4165, N_N4080, N_N3373, + N_N3709, N_N4206, N_N3324, N_N3575, N_N4159, NAK5_2, N_N3916, N_N3743, + N_N4242, N_N3312, N_N3733, N_N3774, N_N4214, N_N3294, N_N3796, N_N3574, + N_N3791, N_N3480, N_N4243, N_N3940, N_N3509, N_N4015, N_N2989, N_N3919, + N_N3578, N_N3529, N_N4222, N_N3910, N_N3868, N_N3947, N_N4181, N_N3793, + N_N3822, N_N3813, N_N4114, N_N4134, N_N3866, N_N4218, N_N3939, N_N3776, + N_N3387, N_N4194, N_N3821, N_N3882, N_N4167, N_N3800, N_N4237, N_N3417, + N_N3918, N_N4158, N_N3630, N_N3344, N_N4072, N_N3274, N_N3473, N_N4205, + N_N4111, N_N3680, N_N3838, N_N3262, N_N4099, N_N3607, N_N3323, N_N3612, + N_N4079, PDN, N_N3457, N_N3445, N_N3794, N_N3663, N_N3715, N_N4039, + N_N3280, N_N4239, N_N3988, N_N3433, N_N4075, N_N3468, N_N4045, N_N3482, + N_N3832, N_N3304, N_N3750, N_N3634, N_N3293, N_N3659, N_N4252, N_N3912, + N_N3862, N_N3221, N_N3875, N_N3949, N_N3908, N_N3711, N_N3931, N_N3469, + N_N3436, N_N3974, N_N3905, N_N3741, N_N3369, N_N3164, N_N3500, N_N3996, + N_N3356, N_N4093, Pover_0_0_, N_N4224, N_N4027, NDN1_4, N_N3384, + N_N4036, N_N3968, N_N4183, NGFDN_3, N_N4090, N_N4004, N_N3205, N_N4136, + N_N3303, N_N3533, N_N3336, N_N3961, N_N3331, N_N3203, N_N4236, N_N3884, + N_N3367, N_N4140, NDN2_2, N_N4106, N_N3100, N_N4193, N_N3470, N_N3424, + N_N3959, N_N3393, N_N4042, N_N3188, N_N4095, N_N3957, N_N3517, N_N4047, + N_N3081, N_N3541, N_N4177, NDN3_3, N_N4176, N_N3585, NDN3_8, N_N4209, + N_N3824, N_N4208, N_N4120, N_N3708, N_N4220, N_N3999, N_N4223, N_N3179, + N_N4179, N_N3475, N_N4132, N_N4182, N_N3797, N_N3214, N_N4070, N_N4135, + NLD3_9, NDN5_2, NDN5_3, N_N3778, NDN5_4, N_N3212, NDN5_5, NDN5_6, + NDN5_7, NDN5_8, N_N4073, NDN5_9, NEN5_9, N_N3684, N_N4056, N_N3713, + N_N3829, N_N4060, NSr3_2, NSr5_2, NSr5_3, N_N3462, N_N3460, NSr5_4, + NSr3_9, NSr5_5, NSr5_7, NSr5_8, N_N3998; + wire n946, n947, n949, n951, n953, n955, n957, n959, n961, n963, n965, + n967, n969, n971, n973, n975, n977, n979, n981, n983, n985, n987, n989, + n991, n993, n995, n997, n999, n1001, n1003, n1005, n1007, n1009, + n1011_1, n1013, n1015, n1017, n1019, n1021_1, n1023, n1025, n1027, + n1030, n1032, n1034, n1036_1, n1038, n1040, n1042, n1044, n1046_1, + n1048, n1050, n1052, n1054, n1056_1, n1058, n1060, n1062, n1065, n1067, + n1069, n1071_1, n1073, n1076_1, n1078, n1081, n1083, n1085, n1087, + n1089, n1091, n1093, n1095, n1097, n1099, n1101_1, n1104, n1106_1, + n1107, n1110, n1112, n1114, n1116, n1118, n1120, n1122, n1124, n1126_1, + n1128, n1130, n1132, n1134, n1136_1, n1138, n1140_1, n1142, n1145_1, + n1147, n1149, n1151, n1153, n1155_1, n1157, n1159, n1161, n1163, + n1165_1, n1167, n1169, n1171, n1173, n1176, n1178, n1180, n1182, n1184, + n1186, n1189, n1192, n1194, n1196, n1198, n1200, n1202, n1204, n1206, + n1211, n1213, n1215_1, n1217, n1220_1, n1223, n1225_1, n1227, n1229, + n1231, n1233, n1235, n1237, n1239, n1241, n1244, n1248, n1250, n1252, + n1254, n1256, n1258, n1260_1, n1262, n1264, n1266, n1268, n1270_1, + n1272, n1274, n1276, n1278, n1280_1, n1282, n1284, n1286, n1288, n1291, + n1293, n1295, n1297, n1299, n1301, n1303, n1305_1, n1307, n1309, n1311, + n1313, n1315_1, n1317, n1319, n1321, n1323, n1325_1, n1330_1, n1332, + n1334, n1336, n1338, n1340_1, n1342, n1344, n1346, n1348, n1350_1, + n1352, n1355_1, n1357, n1359, n1361, n1363, n1365_1, n1367, n1369, + n1371, n1373, n1375_1, n1377, n1380_1, n1382, n1384, n1387, n1389, + n1391, n1393, n1395_1, n1397, n1399, n1401, n1404, n1407, n1409, n1411, + n1413, n1416, n1418, n1420_1, n1422, n1424, n1426, n1428, n1430_1, + n1432, n1434, n1437, n1439, n1441, n1443, n1445_1, n1447, n1449, n1451, + n1453, n1455_1, n1457, n1459, n1461, n1463, n1465_1, n1469, n1471, + n1473, n1475_1, n1479, n1481, n1483, n1485_1, n1487, n1489, n1491, + n1493, n1495_1, n1497, n1499, n1501, n1503, n1505_1, n1507, n1509, + n1510_1, n1511, n1512, n1513, n1514, n1515_1, n1516, n1517, n1518, + n1519, n1520_1, n1521, n1522, n1523, n1524, n1525_1, n1526, n1527, + n1528, n1529, n1530_1, n1531, n1532, n1533, n1534, n1535_1, n1536, + n1537, n1538, n1539, n1540_1, n1541, n1542, n1543, n1544, n1545_1, + n1546, n1547, n1548, n1549, n1550_1, n1551, n1552, n1553, n1554, + n1555_1, n1556, n1557, n1558, n1559, n1560_1, n1561, n1562, n1564, + n1565_1, n1566, n1567, n1568, n1569, n1570_1, n1571, n1572, n1573, + n1574, n1575_1, n1576, n1577, n1578, n1579, n1580_1, n1581, n1582, + n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, + n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, + n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, + n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, + n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, + n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, + n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, + n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, + n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, + n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, + n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, + n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, + n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, + n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, + n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, + n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, + n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, + n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, + n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, + n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, + n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, + n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, + n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, + n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, + n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, + n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, + n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, + n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, + n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, + n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, + n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, + n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, + n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, + n1913, n1914, n1915, n1916, n1918, n1920, n1923, n1924, n1925, n1926, + n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, + n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, + n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, + n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, + n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1975, n1976, n1979, + n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, + n1990, n1991, n1992, n1993, n63_1, n68_1, n73_1, n78_1, n83_1, n88, + n93_1, n98_1, n103, n108_1, n113_1, n118_1, n123_1, n128, n133, n138_1, + n143_1, n148_1, n153_1, n158_1, n163_1, n168_1, n173_1, n178_1, n183_1, + n188_1, n193_1, n198_1, n203_1, n208_1, n213_1, n218_1, n223_1, n228_1, + n233, n238, n243_1, n248_1, n253_1, n258_1, n263_1, n268, n273, n278_1, + n283, n288_1, n293, n298, n303_1, n308_1, n313_1, n318_1, n323_1, + n328_1, n333_1, n338_1, n343_1, n348_1, n353_1, n358_1, n363_1, n368, + n373, n377, n382_1, n387_1, n392_1, n397_1, n402_1, n407, n412_1, + n417_1, n422_1, n427, n432_1, n437_1, n442, n447, n452_1, n457, n462, + n467, n472, n477, n482, n487_1, n492, n497, n502_1, n507, n512, n517_1, + n522_1, n527, n532, n537_1, n542_1, n547, n552, n557_1, n562, n567_1, + n572, n577_1, n582, n587, n592, n597_1, n602_1, n607_1, n612, n617, + n622, n627, n632, n637_1, n642_1, n647, n652, n657, n662_1, n667, n672, + n677, n682_1, n687_1, n692, n697, n702_1, n707, n712_1, n717, n722_1, + n727_1, n732, n737, n742_1, n747, n752_1, n757, n762, n767_1, n772, + n777, n782, n787, n792, n797, n802_1, n807_1, n812_1, n817, n822_1, + n827_1, n832_1, n837, n842_1, n847_1, n852_1, n857_1, n862, n867_1, + n872_1, n877, n882_1, n887_1, n892_1, n897_1, n902, n907, n912, n917, + n922, n927_1, n932_1, n936, n941, n946_1, n951_1, n956_1, n961_1, + n966_1, n971_1, n976, n981_1, n986, n991_1, n996, n1001_1, n1006_1, + n1011, n1016_1, n1021, n1026, n1031_1, n1036, n1041_1, n1046, n1051_1, + n1056, n1061_1, n1066_1, n1071, n1076, n1081_1, n1086_1, n1091_1, + n1096, n1101, n1106, n1111, n1116_1, n1121, n1126, n1131, n1136, n1140, + n1145, n1150, n1155, n1160, n1165, n1170, n1175, n1180_1, n1185_1, + n1190, n1195_1, n1200_1, n1205_1, n1210_1, n1215, n1220, n1225, + n1230_1, n1235_1, n1240, n1245_1, n1250_1, n1255, n1260, n1265, n1270, + n1275_1, n1280, n1285_1, n1290_1, n1295_1, n1300, n1305, n1310, n1315, + n1320, n1325, n1330, n1335, n1340, n1345, n1350, n1355, n1360, n1365, + n1370, n1375, n1380, n1385, n1390, n1395, n1400, n1405, n1410, n1415, + n1420, n1425, n1430, n1435, n1440, n1445, n1450, n1455, n1460, n1465, + n1470, n1475, n1480, n1485, n1490, n1495, n1500, n1505, n1510, n1515, + n1520, n1525, n1530, n1535, n1540, n1545, n1550, n1555, n1560, n1565, + n1570, n1575, n1580; + assign n946 = ~PRESET & n1558; + assign n947 = N_N3460 & ~n1556 & n1557; + assign n1385 = n946 & (n947 | N_N3999); + assign n949 = (n1585 | ~N_N4239) & (PRESET | n1584); + assign n971_1 = ~n949; + assign n951 = n1586 | ~N_N4232; + assign n338_1 = ~n951; + assign n953 = n1586 | ~N_N4230; + assign n363_1 = ~n953; + assign n955 = n1586 | ~N_N4218; + assign n792 = ~n955; + assign n957 = ~PRESET & n1961; + assign n737 = N_N4222 & n957; + assign n959 = (n1644 | ~n1934) & (~n1962 | ~N_N4167); + assign n827_1 = ~n959; + assign n961 = (n1585 | ~N_N4140) & (PRESET | n1646); + assign n1245_1 = ~n961; + assign n963 = (n1648 | ~n1934) & (n1647 | ~N_N4114); + assign n777 = ~n963; + assign n965 = (n1653 | n1654) & (n1652 | ~N_N4111); + assign n887_1 = ~n965; + assign n967 = n1586 | ~N_N4106; + assign n1255 = ~n967; + assign n969 = (n1585 | ~N_N4099) & (PRESET | n1656); + assign n907 = ~n969; + assign n971 = (n1585 | ~N_N4095) & (PRESET | n1658); + assign n1300 = ~n971; + assign n973 = n1586 | ~N_N4090; + assign n1180_1 = ~n973; + assign n975 = (n1585 | ~N_N4086) & (PRESET | n1660); + assign n358_1 = ~n975; + assign n977 = (n1662 | n1663) & (n1661 | ~N_N4075); + assign n986 = ~n977; + assign n979 = (n1586 | ~N_N4056) & (~Paport_5_5_ | n1587); + assign n1510 = ~n979; + assign n981 = (n1586 | ~N_N4054) & (~Paport_7_7_ | n1587); + assign n63_1 = ~n981; + assign n983 = (n1665 | n1666) & (n1664 | ~N_N4047); + assign n1315 = ~n983; + assign n985 = (n1664 | ~N_N4045) & (n1663 | n1665); + assign n996 = ~n985; + assign n987 = (n1668 | n1669) & (n1667 | ~N_N4042); + assign n1290_1 = ~n987; + assign n989 = (n1668 | n1670) & (n1667 | ~N_N4039); + assign n961_1 = ~n989; + assign n991 = (n1648 | n1709) & (n1647 | ~N_N4079); + assign n927_1 = ~n991; + assign n993 = (n1711 | n1712) & (n1710 | ~N_N4030); + assign n303_1 = ~n993; + assign n995 = (n1713 | ~N_N4236) & (n1670 | n1714); + assign n1230_1 = ~n995; + assign n997 = (n1662 | n1715) & (n1661 | ~N_N4024); + assign n507 = ~n997; + assign n999 = (n1662 | n1716) & (n1661 | ~N_N4021); + assign n522_1 = ~n999; + assign n1001 = (n1586 | ~N_N4057) & (~Pdxport_2_2_ | n1587); + assign n572 = ~n1001; + assign n1003 = (n1738 | n1739) & (n1737 | ~N_N3988); + assign n976 = ~n1003; + assign n1005 = (n1654 | n1740) & (n1652 | ~N_N3981); + assign n228_1 = ~n1005; + assign n1007 = (n1665 | n1741) & (n1664 | ~N_N4116); + assign n452_1 = ~n1007; + assign n1009 = (n1668 | n1741) & (n1667 | ~N_N3968); + assign n1165 = ~n1009; + assign n1011_1 = (n1586 | ~N_N4179) & (~Pdxport_5_5_ | n1587); + assign n1400 = ~n1011_1; + assign n1013 = (n1662 | n1741) & (n1661 | ~N_N3959); + assign n1280 = ~n1013; + assign n1015 = (n1662 | n1742) & (n1661 | ~N_N3957); + assign n1305 = ~n1015; + assign n1017 = (n1644 | n1743) & (~n1962 | ~N_N3947); + assign n752_1 = ~n1017; + assign n1019 = (n1586 | ~N_N4220) & (~Pdxport_3_3_ | n1587); + assign n1380 = ~n1019; + assign n1021_1 = (n1586 | ~N_N3916) & (~Paport_0_0_ | n1587); + assign n637_1 = ~n1021_1; + assign n1023 = (n1586 | ~N_N4243) & (~Paport_6_6_ | n1587); + assign n697 = ~n1023; + assign n1025 = (n1586 | ~N_N4015) & (~Paport_8_8_ | n1587); + assign n712_1 = ~n1025; + assign n1027 = (n1714 | n1744) & (n1713 | ~N_N3910); + assign n742_1 = ~n1027; + assign n1096 = N_N3905 & n957; + assign n1030 = (n1586 | ~N_N4120) & (~Pdxport_1_1_ | n1587); + assign n1370 = ~n1030; + assign n1032 = (n1808 | ~N_N4197) & (n1806 | n1807); + assign n133 = ~n1032; + assign n1034 = (n1644 | n1809) & (~n1962 | ~N_N3829); + assign n1520 = ~n1034; + assign n1036_1 = (n1644 | n1810) & (~n1962 | ~N_N3826); + assign n78_1 = ~n1036_1; + assign n1038 = (n1662 | n1669) & (n1661 | ~N_N3824); + assign n1360 = ~n1038; + assign n1040 = (n1586 | ~N_N3818) & (~Paport_9_9_ | n1587); + assign n83_1 = ~n1040; + assign n1042 = (n1644 | n1811) & (~n1962 | ~N_N3815); + assign n98_1 = ~n1042; + assign n1044 = n1586 | ~N_N3876; + assign n512 = ~n1044; + assign n1046_1 = (n1585 | ~N_N3971) & (PRESET | n1813); + assign n333_1 = ~n1046_1; + assign n1048 = (n1668 | n1715) & (n1667 | ~N_N3799); + assign n417_1 = ~n1048; + assign n1050 = (n1644 | n1814) & (~n1962 | ~N_N3796); + assign n677 = ~n1050; + assign n1052 = (n1644 | n1815) & (~n1962 | ~N_N3788); + assign n118_1 = ~n1052; + assign n1054 = n1586 | ~N_N3786; + assign n402_1 = ~n1054; + assign n1056_1 = (n1665 | n1712) & (n1664 | ~N_N3870); + assign n502_1 = ~n1056_1; + assign n1058 = ~PRESET & ~NGFDN_3; + assign n1350 = n1058 & (NDN3_8 | NDN3_3); + assign n1060 = n1816 & (PRESET | ~N_N3745); + assign n68_1 = ~n1060; + assign n1062 = n1586 | ~N_N3741; + assign n1101 = ~n1062; + assign n1460 = ~PRESET & ~NSr5_4; + assign n1065 = (n1808 | ~N_N3992) & (n1807 | n1817); + assign n353_1 = ~n1065; + assign n1067 = (n1713 | ~N_N4193) & (n1663 | n1714); + assign n1265 = ~n1067; + assign n1069 = (n1808 | ~N_N4018) & (n1807 | n1818); + assign n328_1 = ~n1069; + assign n1071_1 = (n1648 | n1819) & (n1647 | ~N_N3713); + assign n1515 = ~n1071_1; + assign n1073 = (n1711 | n1716) & (n1710 | ~N_N3711); + assign n1071 = ~n1073; + assign n1375 = N_N3708 & n957; + assign n1076_1 = (n1586 | ~N_N3882) & (~Paport_10_10_ | n1587); + assign n822_1 = ~n1076_1; + assign n1078 = (n1714 | n1715) & (n1713 | ~N_N3793); + assign n762 = ~n1078; + assign n103 = N_N3691 & n957; + assign n1081 = (n1644 | n1820) & (~n1962 | ~N_N3684); + assign n1505 = ~n1081; + assign n1083 = (n1585 | ~N_N4252) & (PRESET | n1822); + assign n1036 = ~n1083; + assign n1085 = (n1585 | ~N_N3843) & (PRESET | n1824); + assign n138_1 = ~n1085; + assign n1087 = (n1648 | n1825) & (n1647 | ~N_N3743); + assign n642_1 = ~n1087; + assign n1089 = (n1648 | n1826) & (n1647 | ~N_N3774); + assign n662_1 = ~n1089; + assign n1091 = (n1737 | ~N_N3663) & (n1670 | n1738); + assign n951_1 = ~n1091; + assign n1093 = (n1711 | n1741) & (n1710 | ~N_N4117); + assign n248_1 = ~n1093; + assign n1095 = (n1665 | n1670) & (n1664 | ~N_N3659); + assign n1031_1 = ~n1095; + assign n1097 = (n1648 | n1827) & (n1647 | ~N_N3791); + assign n687_1 = ~n1097; + assign n1099 = (n1711 | n1742) & (n1710 | ~N_N3922); + assign n288_1 = ~n1099; + assign n1101_1 = (n1654 | n1828) & (n1652 | ~N_N3761); + assign n258_1 = ~n1101_1; + assign n632 = ~PRESET & ~n1558; + assign n1104 = n1586 | ~N_N3634; + assign n1021 = ~n1104; + assign n1106_1 = (n1735 | n1736) & (N_N3336 | ~N_N4205); + assign n1107 = NLD3_9 & (n1106_1 | (N_N3336 & ~N_N4205)); + assign n532 = ~PRESET & ~PDN; + assign n932_1 = n532 & (NGFDN_3 | ~n1169); + assign n1110 = (n1829 | ~NEN5_9) & (NLD3_9 | n1830); + assign n1500 = ~n1110; + assign n1112 = (n1648 | n1831) & (n1647 | ~N_N3709); + assign n607_1 = ~n1112; + assign n1114 = (n1737 | ~N_N4071) & (n1669 | n1738); + assign n268 = ~n1114; + assign n1116 = (n1714 | n1716) & (n1713 | ~N_N3776); + assign n802_1 = ~n1116; + assign n1118 = (n1662 | n1670) & (n1661 | ~N_N3612); + assign n922 = ~n1118; + assign n1120 = (n1808 | ~N_N3949) & (n1807 | n1832); + assign n1061_1 = ~n1120; + assign n1122 = (n1836 | ~N_N4212) & (PRESET | n1835); + assign n368 = ~n1122; + assign n1124 = (n1836 | ~N_N4171) & (PRESET | n1838); + assign n407 = ~n1124; + assign n1126_1 = (n1586 | ~N_N3733) & (~Paport_2_2_ | n1587); + assign n657 = ~n1126_1; + assign n1128 = (n1585 | ~N_N3918) & (PRESET | n1840); + assign n847_1 = ~n1128; + assign n1130 = (n1585 | ~N_N3939) & (PRESET | n1842); + assign n797 = ~n1130; + assign n1132 = (n1585 | ~N_N4224) & (PRESET | n1844); + assign n1140 = ~n1132; + assign n1134 = (n1662 | n1845) & (n1661 | ~N_N3585); + assign n1345 = ~n1134; + assign n1136_1 = n1586 | ~N_N3580; + assign n153_1 = ~n1136_1; + assign n1138 = n1846 & (n1847 | ~N_N3751); + assign n387_1 = ~n1138; + assign n1140_1 = (n1654 | n1831) & (n1652 | ~N_N3794); + assign n946_1 = ~n1140_1; + assign n1142 = (n1662 | n1744) & (n1661 | ~N_N3625); + assign n487_1 = ~n1142; + assign n1335 = n1058 & (NDN3_3 | ~NSr3_2); + assign n1145_1 = (n1665 | n1742) & (n1664 | ~N_N3921); + assign n482 = ~n1145_1; + assign n1147 = (n1586 | ~N_N3574) & (~Paport_4_4_ | n1587); + assign n682_1 = ~n1147; + assign n1149 = (n1586 | ~N_N4205) & (~Paport_11_11_ | n1587); + assign n882_1 = ~n1149; + assign n1151 = (n1585 | ~N_N4118) & (PRESET | n1849); + assign n148_1 = ~n1151; + assign n1153 = (n1585 | ~N_N4209) & (PRESET | n1851); + assign n1355 = ~n1153; + assign n1155_1 = (n1585 | ~N_N3500) & (PRESET | n1853); + assign n1116_1 = ~n1155_1; + assign n1157 = (n1654 | n1854) & (n1652 | ~N_N3489); + assign n298 = ~n1157; + assign n1159 = (n1654 | n1819) & (n1652 | ~N_N3513); + assign n313_1 = ~n1159; + assign n1161 = (n1738 | n1742) & (n1737 | ~N_N4221); + assign n183_1 = ~n1161; + assign n1163 = (n1586 | ~N_N4206) & (~Pdxport_6_6_ | n1587); + assign n612 = ~n1163; + assign n1165_1 = (n1667 | ~N_N3482) & (n1663 | n1668); + assign n1001_1 = ~n1165_1; + assign n1167 = n1855 & (n1847 | ~N_N4080); + assign n1340 = ~n1167; + assign n1169 = ~Preset_0_0_ | PDN | NLC1_2; + assign n1250_1 = ~PRESET & n1169 & NDN2_2; + assign n1171 = (n1648 | n1740) & (n1647 | ~N_N3475); + assign n1405 = ~n1171; + assign n1173 = (n1737 | ~N_N3473) & (n1663 | n1738); + assign n877 = ~n1173; + assign n557_1 = ~PRESET & n1107; + assign n1176 = ~n1440 & (n1829 | ~NEN5_9); + assign n1495 = ~n1176; + assign n1178 = (n1667 | ~N_N3736) & (n1666 | n1668); + assign n497 = ~n1178; + assign n1180 = (n1654 | n1856) & (n1652 | ~N_N3535); + assign n198_1 = ~n1180; + assign n1182 = (n1808 | ~N_N3912) & (n1807 | n1857); + assign n1041_1 = ~n1182; + assign n1184 = (n1648 | n1862) & (n1647 | ~N_N4158); + assign n852_1 = ~n1184; + assign n1186 = (n1711 | n1739) & (n1710 | ~N_N3436); + assign n1086_1 = ~n1186; + assign n897_1 = ~PRESET & (n947 | N_N3838); + assign n1189 = (n1711 | n1845) & (n1710 | ~N_N3841); + assign n323_1 = ~n1189; + assign n143_1 = N_N3426 & n957; + assign n1192 = (n1665 | n1716) & (n1664 | ~N_N3424); + assign n1275_1 = ~n1192; + assign n1194 = n1586 | ~N_N3417; + assign n842_1 = ~n1194; + assign n1196 = (n1585 | ~N_N3842) & (PRESET | n1864); + assign n233 = ~n1196; + assign n1198 = (n1585 | ~N_N3924) & (PRESET | n1866); + assign n93_1 = ~n1198; + assign n1200 = (n1585 | ~N_N4119) & (PRESET | n1868); + assign n73_1 = ~n1200; + assign n1202 = n1586 | ~N_N3517; + assign n1310 = ~n1202; + assign n1204 = n1586 | ~N_N3681; + assign n437_1 = ~n1204; + assign n1206 = n1586 | ~N_N3716; + assign n472 = ~n1206; + assign n757 = N_N4181 & n957; + assign n727_1 = N_N3578 & n946; + assign n123_1 = N_N3375 & n957; + assign n1211 = n1586 | ~N_N3373; + assign n602_1 = ~n1211; + assign n1213 = (n1665 | n1715) & (n1664 | ~N_N3367); + assign n1240 = ~n1213; + assign n1215_1 = n1586 | ~N_N3533; + assign n1205_1 = ~n1215_1; + assign n1217 = (n1585 | ~N_N3808) & (PRESET | n1870); + assign n168_1 = ~n1217; + assign n1470 = ~PRESET & ~NSr5_5; + assign n1220_1 = (n1836 | ~N_N3340) & (PRESET | n1873); + assign n447 = ~n1220_1; + assign n1490 = N_N4073 & n957; + assign n1223 = (~N_N3336 | n1652) & (n1654 | n1862); + assign n1210_1 = ~n1223; + assign n1225_1 = (n1737 | ~N_N4180) & (n1712 | n1738); + assign n213_1 = ~n1225_1; + assign n1227 = ~PRESET & (n1955 | (~n1229 & N_N4214)); + assign n667 = n1227 & N_N3462; + assign n1229 = n1581 & ~N_N4060 & n1577 & n1579 & ~n1803 & n1872 & n1907 & n1956; + assign n622 = ~PRESET & n1229; + assign n1231 = (n1654 | n1827) & (n1652 | ~N_N3908); + assign n1066_1 = ~n1231; + assign n1233 = (n1654 | n1709) & (n1652 | ~N_N3884); + assign n1235_1 = ~n1233; + assign n1235 = (n1737 | ~N_N3323) & (n1716 | n1738); + assign n917 = ~n1235; + assign n1237 = n1586 | ~N_N3393; + assign n1285_1 = ~n1237; + assign n1239 = n1874 & (n1847 | ~N_N3932); + assign n457 = ~n1239; + assign n1241 = n1875 & (n1847 | ~N_N3876); + assign n422_1 = ~n1241; + assign n1390 = N_N4223 & n957; + assign n1244 = (n1713 | ~N_N3311) & (n1669 | n1714); + assign n218_1 = ~n1244; + assign n1150 = NDN1_4 & n532; + assign n392_1 = NDN3_11 & n1058; + assign n1248 = (n1586 | ~N_N3778) & (~Paport_3_3_ | n1587); + assign n1455 = ~n1248; + assign n1250 = n1876 & (n1577 | n1807); + assign n432_1 = ~n1250; + assign n1252 = n1877 & (n1573 | n1807); + assign n343_1 = ~n1252; + assign n1254 = (n1644 | n1878) & (~n1962 | ~N_N3274); + assign n872_1 = ~n1254; + assign n1256 = (n1644 | n1879) & (~n1962 | ~N_N3480); + assign n692 = ~n1256; + assign n1258 = (n1585 | ~N_N3940) & (PRESET | n1881); + assign n702_1 = ~n1258; + assign n1260_1 = (n1662 | n1739) & (n1661 | ~N_N3700); + assign n542_1 = ~n1260_1; + assign n1262 = n1586 | ~N_N3250; + assign n178_1 = ~n1262; + assign n1264 = n1586 | ~N_N3248; + assign n208_1 = ~n1264; + assign n1266 = (n1648 | n1743) & (n1647 | ~N_N3931); + assign n1076 = ~n1266; + assign n1268 = (n1644 | n1882) & (~n1962 | ~N_N3509); + assign n707 = ~n1268; + assign n1270_1 = (n1644 | n1883) & (~n1962 | ~N_N3529); + assign n732 = ~n1270_1; + assign n1272 = (n1829 | ~NDN5_10) & (NLD3_9 | n1884); + assign n397_1 = ~n1272; + assign n1274 = (n1585 | ~N_N3923) & (PRESET | n1886); + assign n173_1 = ~n1274; + assign n1276 = (n1808 | ~N_N4145) & (n1807 | n1887); + assign n283 = ~n1276; + assign n1278 = (n1648 | n1820) & (n1647 | ~N_N3464); + assign n193_1 = ~n1278; + assign n1280_1 = (n1648 | n1809) & (n1647 | ~N_N3442); + assign n223_1 = ~n1280_1; + assign n1282 = (n1648 | n1828) & (n1647 | ~N_N3214); + assign n1425 = ~n1282; + assign n1284 = (n1648 | n1854) & (n1647 | ~N_N3212); + assign n1465 = ~n1284; + assign n1286 = (n1711 | n1744) & (n1710 | ~N_N3304); + assign n1011 = ~n1286; + assign n1288 = (n1711 | n1715) & (n1710 | ~N_N3221); + assign n1051_1 = ~n1288; + assign n867_1 = N_N4072 & n957; + assign n1291 = (n1668 | n1742) & (n1667 | ~N_N3205); + assign n1190 = ~n1291; + assign n1293 = (n1668 | n1712) & (n1667 | ~N_N3203); + assign n1225 = ~n1293; + assign n1295 = n1888 & (n1847 | ~N_N3634); + assign n832_1 = ~n1295; + assign n1297 = (n1808 | ~N_N3996) & (n1807 | n1889); + assign n1121 = ~n1297; + assign n1299 = (n1586 | ~N_N4132) & (~Pdxport_7_7_ | n1587); + assign n1410 = ~n1299; + assign n1301 = (n1586 | ~N_N4070) & (~Pdxport_9_9_ | n1587); + assign n1430 = ~n1301; + assign n1303 = (n1586 | ~N_N4237) & (~Pdxport_11_11_ | n1587); + assign n837 = ~n1303; + assign n1305_1 = n1890 & (n1847 | ~N_N3517); + assign n1195_1 = ~n1305_1; + assign n1307 = n1891 & (n1847 | ~N_N3393); + assign n1170 = ~n1307; + assign n1309 = n1586 | ~N_N3932; + assign n527 = ~n1309; + assign n1311 = (n1648 | n1856) & (n1647 | ~N_N3179); + assign n1395 = ~n1311; + assign n1313 = (n1737 | ~N_N3293) & (n1666 | n1738); + assign n1026 = ~n1313; + assign n1315_1 = (n1738 | n1741) & (n1737 | ~N_N3175); + assign n158_1 = ~n1315_1; + assign n1317 = (n1710 | ~N_N3806) & (n1669 | n1711); + assign n348_1 = ~n1317; + assign n1319 = (n1710 | ~N_N3433) & (n1670 | n1711); + assign n981_1 = ~n1319; + assign n1321 = (n1836 | ~N_N3369) & (PRESET | n1893); + assign n1106 = ~n1321; + assign n1323 = (n1586 | ~N_N3797) & (~Paport_1_1_ | n1587); + assign n1420 = ~n1323; + assign n1325_1 = (n1668 | n1744) & (n1667 | ~N_N3626); + assign n377 = ~n1325_1; + assign n1445 = ~PRESET & ~NSr5_2; + assign n782 = N_N4134 & n957; + assign n941 = N_N3445 & n957; + assign n1330_1 = n1894 & (n1847 | ~N_N3280); + assign n772 = ~n1330_1; + assign n1332 = n1586 | ~N_N3196; + assign n427 = ~n1332; + assign n1334 = (n1836 | ~N_N4093) & (PRESET | n1896); + assign n1131 = ~n1334; + assign n1336 = (n1586 | ~N_N4165) & (~Pdxport_4_4_ | n1587); + assign n592 = ~n1336; + assign n1338 = (n1738 | n1744) & (n1737 | ~N_N3387); + assign n807_1 = ~n1338; + assign n1340_1 = (n1710 | ~N_N3164) & (n1666 | n1711); + assign n1111 = ~n1340_1; + assign n1342 = (n1714 | n1742) & (n1713 | ~N_N3143); + assign n128 = ~n1342; + assign n1344 = (n1665 | n1845) & (n1664 | ~N_N3840); + assign n517_1 = ~n1344; + assign n1346 = (n1665 | n1669) & (n1664 | ~N_N3805); + assign n537_1 = ~n1346; + assign n1348 = n1897 & (n1847 | ~N_N4159); + assign n1365 = ~n1348; + assign n1350_1 = n1898 & (n1847 | ~N_N3235); + assign n278_1 = ~n1350_1; + assign n1352 = (n1585 | ~N_N3872) & (PRESET | n1900); + assign n113_1 = ~n1352; + assign n617 = N_N3324 & n957; + assign n1355_1 = (n1654 | n1826) & (n1652 | ~N_N3862); + assign n1046 = ~n1355_1; + assign n1357 = n1586 | ~N_N3751; + assign n492 = ~n1357; + assign n1359 = (n1648 | n1883) & (n1647 | ~N_N3875); + assign n1056 = ~n1359; + assign n1361 = (n1808 | ~N_N3965) & (n1807 | n1901); + assign n382_1 = ~n1361; + assign n1363 = n1586 | ~N_N3105; + assign n238 = ~n1363; + assign n1365_1 = (n1737 | ~N_N3344) & (n1715 | n1738); + assign n862 = ~n1365_1; + assign n1367 = (n1710 | ~N_N3457) & (n1663 | n1711); + assign n936 = ~n1367; + assign n1369 = (n1665 | n1744) & (n1664 | ~N_N3303); + assign n1200_1 = ~n1369; + assign n1371 = n1902 & (n1579 | n1807); + assign n1160 = ~n1371; + assign n1373 = n1903 & (n1581 | n1807); + assign n1185_1 = ~n1373; + assign n1375_1 = (n1585 | ~N_N4177) & (PRESET | n1905); + assign n1330 = ~n1375_1; + assign n1377 = (n1654 | n1825) & (n1652 | ~N_N3832); + assign n1006_1 = ~n1377; + assign n88 = N_N3345 & n957; + assign n1380_1 = (n1665 | n1739) & (n1664 | ~N_N3188); + assign n1295_1 = ~n1380_1; + assign n1382 = (n1713 | ~N_N3071) & (n1712 | n1714); + assign n163_1 = ~n1382; + assign n1384 = (n1714 | n1845) & (n1713 | ~N_N3069); + assign n188_1 = ~n1384; + assign n412_1 = NDN5_16 & ~n1829; + assign n1387 = n1586 | ~N_N4159; + assign n627 = ~n1387; + assign n1389 = n1586 | ~N_N3331; + assign n1220 = ~n1389; + assign n1391 = (n1836 | ~N_N3283) & (PRESET | n1908); + assign n467 = ~n1391; + assign n1393 = (n1586 | ~N_N4242) & (~Pdxport_8_8_ | n1587); + assign n647 = ~n1393; + assign n1395_1 = (n1586 | ~N_N4194) & (~Pdxport_10_10_ | n1587); + assign n812_1 = ~n1395_1; + assign n1397 = (n1648 | n1815) & (n1647 | ~N_N3540); + assign n308_1 = ~n1397; + assign n1399 = (n1668 | n1716) & (n1667 | ~N_N3679); + assign n442 = ~n1399; + assign n1401 = (n1668 | n1739) & (n1667 | ~N_N3701); + assign n477 = ~n1401; + assign n1450 = ~PRESET & ~NSr5_3; + assign n1404 = (n1648 | n1882) & (n1647 | ~N_N3750); + assign n1016_1 = ~n1404; + assign n991_1 = N_N3468 & n957; + assign n1407 = n1816 & (PRESET | ~N_N3346); + assign n582 = ~n1407; + assign n1409 = n1909 & (n1847 | ~N_N3822); + assign n1270 = ~n1409; + assign n1411 = (n1668 | n1845) & (n1667 | ~N_N3100); + assign n1260 = ~n1411; + assign n1413 = (n1808 | ~N_N3974) & (n1807 | n1910); + assign n1091_1 = ~n1413; + assign n1475 = (NDN5_6 | ~n1514) & ~n1829; + assign n1416 = (n1662 | n1666) & (n1661 | ~N_N3735); + assign n547 = ~n1416; + assign n1418 = (n1648 | n1878) & (n1647 | ~N_N3821); + assign n817 = ~n1418; + assign n1420_1 = n1586 | ~N_N4080; + assign n597_1 = ~n1420_1; + assign n1422 = n1586 | ~N_N3062; + assign n263_1 = ~n1422; + assign n1424 = (n1648 | n1814) & (n1647 | ~N_N3680); + assign n892_1 = ~n1424; + assign n1426 = (n1648 | n1879) & (n1647 | ~N_N3715); + assign n956_1 = ~n1426; + assign n1428 = n1586 | ~N_N3822; + assign n767_1 = ~n1428; + assign n1430_1 = (n1586 | ~N_N3906) & (~Pdxport_0_0_ | n1587); + assign n562 = ~n1430_1; + assign n1432 = (n1648 | n1653) & (n1647 | ~N_N3677); + assign n587 = ~n1432; + assign n1434 = (n1738 | n1845) & (n1737 | ~N_N4133); + assign n243_1 = ~n1434; + assign n1081_1 = N_N3469 & n957; + assign n1437 = (n1648 | n1811) & (n1647 | ~N_N3516); + assign n293 = ~n1437; + assign n1439 = n1816 & (PRESET | ~N_N2989); + assign n717 = ~n1439; + assign n1441 = Pready_0_0_ & ~PDN & n1959 & ~NLak3_2; + assign n552 = ~PRESET & NSr3_2 & n1441; + assign n1443 = n1586 | ~N_N3262; + assign n902 = ~n1443; + assign n1445_1 = n1586 | ~N_N3280; + assign n966_1 = ~n1445_1; + assign n1447 = (n1808 | ~N_N4027) & (n1807 | n1911); + assign n1145 = ~n1447; + assign n1449 = n1586 | ~N_N3356; + assign n1126 = ~n1449; + assign n1451 = n1586 | ~N_N3384; + assign n1155 = ~n1451; + assign n1453 = (n1662 | n1712) & (n1661 | ~N_N3081); + assign n1320 = ~n1453; + assign n1455_1 = (n1714 | n1739) & (n1713 | ~N_N3630); + assign n857_1 = ~n1455_1; + assign n1457 = (n1713 | ~N_N3607) & (n1666 | n1714); + assign n912 = ~n1457; + assign n1459 = n1586 | ~N_N3235; + assign n462 = ~n1459; + assign n1461 = (n1648 | n1810) & (n1647 | ~N_N3420); + assign n253_1 = ~n1461; + assign n1463 = (n1714 | n1741) & (n1713 | ~N_N3157); + assign n108_1 = ~n1463; + assign n1465_1 = n1586 | ~N_N3011; + assign n577_1 = ~n1465_1; + assign n652 = N_N3312 & n957; + assign n672 = N_N3294 & n957; + assign n1469 = n1912 & (n1567 | n1807); + assign n1215 = ~n1469; + assign n1471 = (n1808 | ~N_N4083) & (n1807 | n1913); + assign n318_1 = ~n1471; + assign n1473 = n1586 | ~N_N3541; + assign n1325 = ~n1473; + assign n1475_1 = n1586 | ~N_N3866; + assign n787 = ~n1475_1; + assign n1415 = N_N4182 & n957; + assign n1435 = N_N4135 & n957; + assign n1479 = n1914 & (n1847 | ~N_N3262); + assign n747 = ~n1479; + assign n1481 = n1915 & (n1847 | ~N_N3417); + assign n722_1 = ~n1481; + assign n1483 = n1816 & (PRESET | ~N_N3388); + assign n567_1 = ~n1483; + assign n1485_1 = n1916 & (n1847 | ~N_N3786); + assign n203_1 = ~n1485_1; + assign n1487 = n532 & (~NSr3_2 | n1441); + assign n1530 = ~n1487; + assign n1489 = ~n1829 & ((~n1514 & NAK5_2) | ~NSr5_2); + assign n1535 = ~n1489; + assign n1491 = ~n1829 & (~NSr5_3 | (NAK5_2 & ~NSr5_2)); + assign n1540 = ~n1491; + assign n1493 = n946 & (~N_N3462 | n1229); + assign n1545 = ~n1493; + assign n1495_1 = n946 & ~n1556 & (~N_N3462 | n1229); + assign n1550 = ~n1495_1; + assign n1497 = ~n1829 & (~NSr5_4 | (NAK5_2 & ~NSr5_3)); + assign n1555 = ~n1497; + assign n1499 = n532 & (~NSr3_9 | (NDN3_8 & n1107)); + assign n1560 = ~n1499; + assign n1501 = ~n1829 & ((~NSr5_4 & NAK5_2) | ~NSr5_5); + assign n1565 = ~n1501; + assign n1503 = ~n1829 & (~NSr5_7 | (NAK5_2 & ~NSr5_5)); + assign n1570 = ~n1503; + assign n1505_1 = ~n1829 & (~NSr5_8 | (NAK5_2 & ~NSr5_7)); + assign n1575 = ~n1505_1; + assign n1507 = ~PRESET & ~n1993 & (n1833 | ~N_N3998); + assign n1580 = ~n1507; + assign n1509 = ~n1958 & n1959; + assign n1510_1 = ~NLD3_9 & n1583 & n1958; + assign n1511 = ~PRESET & (n1509 | n1510_1); + assign n1512 = n1559 & ~n1802; + assign n1513 = ~PRESET & (n1512 | ~n1970); + assign n1514 = NLak3_9 | ~NDN3_8 | ~NSr3_9; + assign n1515_1 = (n1514 | ~NSr5_2) & (NSr5_4 | ~NSr5_5); + assign n1516 = (n1528 | ~N_N3303) & (n1515_1 | ~N_N3906); + assign n1517 = (n1542 | ~N_N3940) & (n1538 | ~N_N3939); + assign n1518 = ~NSr5_7 | NSr5_5; + assign n1519 = n1516 & n1517 & (n1518 | ~N_N3304); + assign n1520_1 = (n1528 | ~N_N3188) & (n1515_1 | ~N_N4206); + assign n1521 = (n1542 | ~N_N3813) & (n1538 | ~N_N4239); + assign n1522 = n1520_1 & n1521 & (n1518 | ~N_N3436); + assign n1523 = (n1528 | ~N_N3424) & (n1515_1 | ~N_N4165); + assign n1524 = (n1542 | ~N_N3868) & (n1538 | ~N_N4099); + assign n1525_1 = n1523 & n1524 & (n1518 | ~N_N3711); + assign n1526 = (n1518 | ~N_N3221) & (n1515_1 | ~N_N4057); + assign n1527 = (n1542 | ~N_N3919) & (n1538 | ~N_N3918); + assign n1528 = NSr5_7 | ~NSr5_8; + assign n1529 = n1526 & n1527 & (n1528 | ~N_N3367); + assign n1530_1 = (n1528 | ~N_N4116) & (n1515_1 | ~N_N4120); + assign n1531 = (n1542 | ~N_N4119) & (n1538 | ~N_N4118); + assign n1532 = n1530_1 & n1531 & (n1518 | ~N_N4117); + assign n1533 = (n1528 | ~N_N3921) & (n1515_1 | ~N_N4220); + assign n1534 = (n1542 | ~N_N3924) & (n1538 | ~N_N3923); + assign n1535_1 = n1533 & n1534 & (n1518 | ~N_N3922); + assign n1536 = (n1528 | ~N_N3870) & (n1515_1 | ~N_N4179); + assign n1537 = (n1542 | ~N_N3872) & (n1518 | ~N_N4030); + assign n1538 = ~NSr5_4 | NSr5_3; + assign n1539 = n1536 & n1537 & (n1538 | ~N_N3871); + assign n1540_1 = (n1518 | ~N_N3164) & (n1515_1 | ~N_N4242); + assign n1541 = (n1538 | ~N_N4252) & (n1528 | ~N_N4047); + assign n1542 = ~NSr5_3 | NSr5_2; + assign n1543 = n1540_1 & n1541 & (n1542 | ~N_N3800); + assign n1544 = (n1528 | ~N_N3805) & (n1515_1 | ~N_N4070); + assign n1545_1 = (n1542 | ~N_N3808) & (n1538 | ~N_N3807); + assign n1546 = n1544 & n1545_1 & (n1518 | ~N_N3806); + assign n1547 = (n1528 | ~N_N3840) & (n1515_1 | ~N_N4132); + assign n1548 = (n1542 | ~N_N3843) & (n1538 | ~N_N3842); + assign n1549 = n1547 & n1548 & (n1518 | ~N_N3841); + assign n1550_1 = (n1518 | ~N_N3433) & (n1515_1 | ~N_N4237); + assign n1551 = (n1542 | ~N_N4209) & (n1538 | ~N_N4208); + assign n1552 = n1550_1 & n1551 & (n1528 | ~N_N3659); + assign n1553 = (n1518 | ~N_N3457) & (n1515_1 | ~N_N4194); + assign n1554 = (n1542 | ~N_N4177) & (n1538 | ~N_N4176); + assign n1555_1 = n1553 & n1554 & (n1528 | ~N_N4045); + assign n1556 = n1515_1 & n1528 & n1518 & n1542 & n1538; + assign n1557 = (~N_N3999 | N_N3838) & ~n1992; + assign n1558 = N_N3460 & (n1556 | n1557); + assign n1559 = N_N3578 | n1558; + assign n1560_1 = ~n1955 & (n1557 | n1559); + assign n1561 = (~n1513 & (~N_N4060 | n1807)) | (N_N4060 & n1807); + assign n1562 = PRESET | n1560_1; + assign n1525 = n1561 & (n1519 | n1562); + assign n1564 = N_N3369 | n1572; + assign n1565_1 = n1564 & (~n1572 | ~N_N3369); + assign n1566 = ~N_N4060 | N_N3961; + assign n1567 = n1566 & (N_N4060 | ~N_N3961); + assign n1568 = N_N4093 | n1570_1; + assign n1569 = n1568 & (~n1570_1 | ~N_N4093); + assign n1570_1 = N_N4212 | n1578; + assign n1571 = n1570_1 & (~n1578 | ~N_N4212); + assign n1572 = N_N4246 | n1568; + assign n1573 = n1572 & (~n1568 | ~N_N4246); + assign n1574 = N_N4171 | n1580_1; + assign n1575_1 = n1574 & (~n1580_1 | ~N_N4171); + assign n1576 = N_N4126 | n1566; + assign n1577 = n1576 & (~n1566 | ~N_N4126); + assign n1578 = N_N4036 | n1574; + assign n1579 = n1578 & (~n1574 | ~N_N4036); + assign n1580_1 = N_N4004 | n1576; + assign n1581 = n1580_1 & (~n1576 | ~N_N4004); + assign n1582 = (~n1509 | ~N_N4239) & (~NLD3_9 | ~N_N3774); + assign n1583 = NDN3_8 | ~NDN3_3; + assign n1584 = n1582 & (n1583 | ~N_N4090); + assign n1585 = PRESET | ~n1510_1; + assign n1586 = n1960 | PRESET; + assign n1587 = PRESET | ~n1960; + assign n1588 = NDN5_9 | ~NEN5_9; + assign n1589 = NDN5_10 | NSr5_7; + assign n1590 = (n1589 | ~N_N4039) & (n1588 | ~N_N3612); + assign n1591 = (n1589 | ~N_N3482) & (n1588 | ~N_N4075); + assign n1592 = (n1589 | ~N_N3736) & (n1588 | ~N_N3735); + assign n1593 = (n1589 | ~N_N3701) & (n1588 | ~N_N3700); + assign n1594 = (n1589 | ~N_N3679) & (n1588 | ~N_N4021); + assign n1595 = (n1589 | ~N_N3626) & (n1588 | ~N_N3625); + assign n1596 = (n1589 | ~N_N3799) & (n1588 | ~N_N4024); + assign n1597 = (n1589 | ~N_N3968) & (n1588 | ~N_N3959); + assign n1598 = (n1589 | ~N_N3205) & (n1588 | ~N_N3957); + assign n1599 = (n1589 | ~N_N3203) & (n1588 | ~N_N3081); + assign n1600 = (n1589 | ~N_N3100) & (n1588 | ~N_N3585); + assign n1601 = (n1589 | ~N_N4042) & (n1588 | ~N_N3824); + assign n1602 = (n1589 | ~N_N3470) & (n1588 | ~N_N3274); + assign n1603 = (n1589 | ~N_N3810) & (n1588 | ~N_N3947); + assign n1604 = n1627 & n1599 & n1593; + assign n1605 = n1604 & n1600; + assign n1606 = (n1589 | ~N_N4224) & (n1588 | ~N_N3829); + assign n1607 = (n1589 | ~N_N3971) & (n1588 | ~N_N3796); + assign n1608 = (n1589 | ~N_N3500) & (n1588 | ~N_N3684); + assign n1609 = ~n1595 & ~n1607 & (~n1608 | ~n1610); + assign n1610 = n1595 ^ ~n1597; + assign n1611 = ~n1609 & (n1608 | n1610); + assign n1612 = n1595 & n1597; + assign n1613 = (n1589 | ~N_N4086) & (n1588 | ~N_N3480); + assign n1614 = n1613 & ~n1924; + assign n1615 = (n1613 | ~n1924) & (n1611 | n1614); + assign n1616 = n1606 & n1615; + assign n1617 = (n1616 | ~n1925) & (n1606 | n1615); + assign n1618 = (n1589 | ~N_N3890) & (n1588 | ~N_N3509); + assign n1619 = n1595 & n1597 & n1596; + assign n1620 = n1619 & n1598; + assign n1621 = n1618 & ~n1926; + assign n1622 = (n1618 | ~n1926) & (n1617 | n1621); + assign n1623 = (n1589 | ~N_N4183) & (n1588 | ~N_N3826); + assign n1624 = n1623 & ~n1927; + assign n1625 = (n1623 | ~n1927) & (n1622 | n1624); + assign n1626 = (n1589 | ~N_N3844) & (n1588 | ~N_N3529); + assign n1627 = n1619 & n1598 & n1594; + assign n1628 = n1627 & n1599; + assign n1629 = n1626 & ~n1928; + assign n1630 = (n1626 | ~n1928) & (n1625 | n1629); + assign n1631 = (n1589 | ~N_N4136) & (n1588 | ~N_N3815); + assign n1632 = n1631 & ~n1929; + assign n1633 = (n1631 | ~n1929) & (n1630 | n1632); + assign n1634 = n1592 ^ ~n1605; + assign n1635 = n1633 & n1634; + assign n1636 = (n1603 | n1635) & (n1633 | n1634); + assign n1637 = (n1589 | ~N_N4140) & (n1588 | ~N_N3788); + assign n1638 = n1636 & n1637; + assign n1639 = (n1638 | ~n1931) & (n1636 | n1637); + assign n1640 = n1602 & n1639; + assign n1641 = n1591 ^ ~n1963; + assign n1642 = (n1640 | n1641) & (n1602 | n1639); + assign n1643 = (n1589 | ~N_N4095) & (n1588 | ~N_N4167); + assign n1644 = PRESET | n1589; + assign n1645 = (~n1509 | ~N_N4140) & (~NLD3_9 | ~N_N3540); + assign n1646 = n1645 & (n1583 | ~N_N3541); + assign n1647 = PRESET | ~n1588; + assign n1648 = PRESET | n1588; + assign n1649 = NDN5_6 | n1514; + assign n1650 = (n1649 | ~N_N3906) & (n1588 | ~N_N3910); + assign n1651 = (n1649 | ~N_N3940) & (n1588 | ~N_N3939); + assign n1652 = PRESET | ~n1649; + assign n1653 = n1650 ^ ~n1651; + assign n1654 = PRESET | n1649; + assign n1655 = (n1583 | ~N_N3384) & (~n1509 | ~N_N4099); + assign n1656 = n1655 & (~NLD3_9 | ~N_N3743); + assign n1657 = (n1583 | ~N_N3866) & (~n1509 | ~N_N4095); + assign n1658 = n1657 & (~NLD3_9 | ~N_N4114); + assign n1659 = (~n1509 | ~N_N4086) & (~NLD3_9 | ~N_N3715); + assign n1660 = n1659 & (n1583 | ~N_N3716); + assign n1661 = PRESET | ~n1964; + assign n1662 = PRESET | n1964; + assign n1663 = ~n1557 | ~N_N4197; + assign n1664 = PRESET | ~n1965; + assign n1665 = PRESET | n1965; + assign n1666 = ~n1557 | ~N_N4145; + assign n1667 = PRESET | ~n1966; + assign n1668 = PRESET | n1966; + assign n1669 = ~n1557 | ~N_N3912; + assign n1670 = ~n1557 | ~N_N4227; + assign n1671 = (n1649 | ~N_N4194) & (n1588 | ~N_N4193); + assign n1672 = (n1649 | ~N_N4177) & (n1588 | ~N_N4176); + assign n1673 = (n1649 | ~N_N3800) & (n1588 | ~N_N4252); + assign n1674 = (n1649 | ~N_N4242) & (n1588 | ~N_N3607); + assign n1675 = (n1649 | ~N_N4220) & (n1588 | ~N_N3143); + assign n1676 = (n1649 | ~N_N3924) & (n1588 | ~N_N3923); + assign n1677 = (n1649 | ~N_N3919) & (n1588 | ~N_N3918); + assign n1678 = (n1649 | ~N_N4057) & (n1588 | ~N_N3793); + assign n1679 = (n1649 | ~N_N4119) & (n1588 | ~N_N4118); + assign n1680 = (n1649 | ~N_N4120) & (n1588 | ~N_N3157); + assign n1681 = ~n1650 & ~n1651 & (~n1679 | ~n1680); + assign n1682 = ~n1681 & (n1679 | n1680); + assign n1683 = n1678 & n1682; + assign n1684 = (n1677 | n1683) & (n1678 | n1682); + assign n1685 = n1676 & n1684; + assign n1686 = (n1675 | n1685) & (n1676 | n1684); + assign n1687 = (n1649 | ~N_N3868) & (n1588 | ~N_N4099); + assign n1688 = (n1649 | ~N_N4165) & (n1588 | ~N_N3776); + assign n1689 = n1687 & n1688; + assign n1690 = (n1686 | n1689) & (n1687 | n1688); + assign n1691 = (n1649 | ~N_N3872) & (n1588 | ~N_N3871); + assign n1692 = (n1649 | ~N_N4179) & (n1588 | ~N_N3071); + assign n1693 = n1691 & n1692; + assign n1694 = (n1690 | n1693) & (n1691 | n1692); + assign n1695 = (n1649 | ~N_N3813) & (n1588 | ~N_N4239); + assign n1696 = (n1649 | ~N_N4206) & (n1588 | ~N_N3630); + assign n1697 = n1695 & n1696; + assign n1698 = (n1694 | n1697) & (n1695 | n1696); + assign n1699 = (n1649 | ~N_N3843) & (n1588 | ~N_N3842); + assign n1700 = (n1649 | ~N_N4132) & (n1588 | ~N_N3069); + assign n1701 = n1699 & n1700; + assign n1702 = (n1698 | n1701) & (n1699 | n1700); + assign n1703 = n1674 & n1702; + assign n1704 = (n1673 | n1703) & (n1674 | n1702); + assign n1705 = (n1649 | ~N_N3808) & (n1588 | ~N_N3807); + assign n1706 = (n1649 | ~N_N4070) & (n1588 | ~N_N3311); + assign n1707 = n1705 & n1706; + assign n1708 = (n1704 | n1707) & (n1705 | n1706); + assign n1709 = n1708 ^ n1981; + assign n1710 = PRESET | ~n1967; + assign n1711 = PRESET | n1967; + assign n1712 = ~n1557 | ~N_N3974; + assign n1713 = PRESET | ~n1968; + assign n1714 = PRESET | n1968; + assign n1715 = ~n1557 | ~N_N3992; + assign n1716 = ~n1557 | ~N_N4018; + assign n1717 = N_N3916 & ~N_N4111 & (N_N3797 | ~N_N3535); + assign n1718 = ~n1717 & (~N_N3797 | N_N3535); + assign n1719 = n1718 & ~N_N3733; + assign n1720 = (n1719 | N_N3794) & (n1718 | ~N_N3733); + assign n1721 = n1720 & ~N_N3778; + assign n1722 = (n1721 | N_N3981) & (n1720 | ~N_N3778); + assign n1723 = ~n1722 & N_N3574; + assign n1724 = (~n1722 | N_N3574) & (n1723 | ~N_N3832); + assign n1725 = n1724 & ~N_N3761; + assign n1726 = (n1725 | N_N4056) & (n1724 | ~N_N3761); + assign n1727 = ~n1726 & N_N3862; + assign n1728 = (~n1726 | N_N3862) & (n1727 | ~N_N4243); + assign n1729 = n1728 & N_N3489; + assign n1730 = (n1729 | ~N_N4054) & (n1728 | N_N3489); + assign n1731 = ~n1730 & ~N_N3908; + assign n1732 = (n1731 | N_N4015) & (~n1730 | ~N_N3908); + assign n1733 = n1732 & ~N_N3513; + assign n1734 = (n1733 | N_N3818) & (n1732 | ~N_N3513); + assign n1735 = N_N3884 & (~n1734 | ~N_N3882); + assign n1736 = ~n1734 & ~N_N3882; + assign n1737 = PRESET | ~n1969; + assign n1738 = PRESET | n1969; + assign n1739 = ~n1557 | ~N_N4083; + assign n1740 = n1684 ^ n1982; + assign n1741 = ~n1557 | ~N_N4027; + assign n1742 = ~n1557 | ~N_N3996; + assign n1743 = n1634 ^ n1935; + assign n1744 = ~n1557 | ~N_N3965; + assign n1745 = (n1515_1 | ~N_N4095) & (~N_N3445 | n1538); + assign n1746 = (n1528 | ~N_N4237) & (~N_N3905 | n1542); + assign n1747 = n1745 & n1746 & (n1518 | ~N_N3663); + assign n1748 = (n1515_1 | ~N_N3470) & (~N_N3468 | n1538); + assign n1749 = (n1528 | ~N_N4194) & (n1518 | ~N_N3473); + assign n1750 = n1748 & (~N_N3469 | n1542) & n1749; + assign n1751 = (n1528 | ~N_N4070) & (n1515_1 | ~N_N4140); + assign n1752 = (~N_N4072 | n1538) & (~N_N4073 | n1542); + assign n1753 = n1751 & n1752 & (n1518 | ~N_N4071); + assign n1754 = (n1518 | ~N_N3293) & (n1515_1 | ~N_N3810); + assign n1755 = (n1528 | ~N_N4242) & (~N_N3426 | n1538); + assign n1756 = n1754 & (~N_N3294 | n1542) & n1755; + assign n1757 = (n1528 | ~N_N4132) & (n1515_1 | ~N_N4136); + assign n1758 = (~N_N4134 | n1538) & (~N_N4135 | n1542); + assign n1759 = n1757 & n1758 & (n1518 | ~N_N4133); + assign n1760 = (n1515_1 | ~N_N3844) & (~N_N3312 | n1542); + assign n1761 = (n1528 | ~N_N4206) & (n1518 | ~N_N3988); + assign n1762 = n1760 & (~N_N3375 | n1538) & n1761; + assign n1763 = (n1528 | ~N_N4179) & (n1515_1 | ~N_N4183); + assign n1764 = (~N_N4181 | n1538) & (~N_N4182 | n1542); + assign n1765 = n1763 & n1764 & (n1518 | ~N_N4180); + assign n1766 = (n1518 | ~N_N3323) & (n1515_1 | ~N_N3890); + assign n1767 = (n1528 | ~N_N4165) & (~N_N3691 | n1538); + assign n1768 = n1766 & (~N_N3324 | n1542) & n1767; + assign n1769 = (n1528 | ~N_N4220) & (n1515_1 | ~N_N4224); + assign n1770 = (~N_N4222 | n1538) & (~N_N4223 | n1542); + assign n1771 = n1769 & n1770 & (n1518 | ~N_N4221); + assign n1772 = (n1518 | ~N_N3344) & (n1515_1 | ~N_N4086); + assign n1773 = (n1542 | ~N_N3346) & (n1528 | ~N_N4057); + assign n1774 = n1772 & (~N_N3345 | n1538) & n1773; + assign n1775 = (n1538 | ~N_N2989) & (n1515_1 | ~N_N3500); + assign n1776 = (n1528 | ~N_N4120) & (~N_N3708 | n1542); + assign n1777 = n1775 & n1776 & (n1518 | ~N_N3175); + assign n1778 = (n1518 | ~N_N3387) & (n1515_1 | ~N_N3971); + assign n1779 = (n1538 | ~N_N3745) & (n1528 | ~N_N3906); + assign n1780 = n1778 & n1779 & (n1542 | ~N_N3388); + assign n1781 = n1780 | ~N_N3965; + assign n1782 = n1777 & n1781; + assign n1783 = (n1782 | ~N_N4027) & (n1777 | n1781); + assign n1784 = n1783 & ~N_N3992; + assign n1785 = (n1783 | ~N_N3992) & (n1774 | n1784); + assign n1786 = n1785 & ~N_N3996; + assign n1787 = (n1785 | ~N_N3996) & (n1771 | n1786); + assign n1788 = n1787 & ~N_N4018; + assign n1789 = (n1787 | ~N_N4018) & (n1768 | n1788); + assign n1790 = n1789 & ~N_N3974; + assign n1791 = (n1789 | ~N_N3974) & (n1765 | n1790); + assign n1792 = n1791 & ~N_N4083; + assign n1793 = (n1791 | ~N_N4083) & (n1762 | n1792); + assign n1794 = n1793 & ~N_N3949; + assign n1795 = (n1793 | ~N_N3949) & (n1759 | n1794); + assign n1796 = n1795 & ~N_N4145; + assign n1797 = (n1795 | ~N_N4145) & (n1756 | n1796); + assign n1798 = n1797 & ~N_N3912; + assign n1799 = (n1797 | ~N_N3912) & (n1753 | n1798); + assign n1800 = n1799 & ~N_N4197; + assign n1801 = (n1799 | ~N_N4197) & (n1750 | n1800); + assign n1802 = ~n1803 | n1955; + assign n1803 = ~N_N3462 | N_N3575 | ~N_N4214; + assign n1804 = n1801 ^ n1747; + assign n1805 = n1802 & (n1803 | n1804); + assign n1806 = n1799 ^ n1936; + assign n1807 = PRESET | n1803; + assign n1808 = PRESET | n1802; + assign n1809 = n1925 ^ ~n1937; + assign n1810 = n1927 ^ ~n1938; + assign n1811 = n1929 ^ ~n1939; + assign n1812 = (~n1509 | ~N_N3971) & (~NLD3_9 | ~N_N3680); + assign n1813 = n1812 & (n1583 | ~N_N3681); + assign n1814 = n1595 ^ ~n1607; + assign n1815 = n1931 ^ ~n1940; + assign n1816 = PRESET | n1961; + assign n1817 = n1783 ^ n1941; + assign n1818 = n1787 ^ n1942; + assign n1819 = n1706 ^ n1983; + assign n1820 = n1610 ^ n1984; + assign n1821 = (n1583 | ~N_N3533) & (~n1509 | ~N_N4252); + assign n1822 = n1821 & (~NLD3_9 | ~N_N3791); + assign n1823 = (n1583 | ~N_N3105) & (~n1509 | ~N_N3843); + assign n1824 = n1823 & (~NLD3_9 | ~N_N3489); + assign n1825 = n1688 ^ n1985; + assign n1826 = n1696 ^ n1986; + assign n1827 = n1702 ^ n1987; + assign n1828 = n1692 ^ n1988; + assign n1829 = PRESET | NLD3_9; + assign n1830 = NSr5_8 | PRESET; + assign n1831 = n1682 ^ n1989; + assign n1832 = n1793 ^ n1943; + assign n1833 = ~PDN & ~NLC1_2; + assign n1834 = (n1522 | n1560_1) & (~N_N4212 | n1970); + assign n1835 = n1834 & (n1571 | n1803); + assign n1836 = PRESET | ~n1512; + assign n1837 = (n1525_1 | n1560_1) & (~N_N4171 | n1970); + assign n1838 = n1837 & (n1575_1 | n1803); + assign n1839 = (n1583 | ~N_N3356) & (~n1509 | ~N_N3918); + assign n1840 = n1839 & (~NLD3_9 | ~N_N3709); + assign n1841 = (~n1509 | ~N_N3939) & (~NLD3_9 | ~N_N3677); + assign n1842 = n1841 & (n1583 | ~N_N3741); + assign n1843 = (~n1509 | ~N_N4224) & (~NLD3_9 | ~N_N3442); + assign n1844 = n1843 & (n1583 | ~N_N4106); + assign n1845 = ~n1557 | ~N_N3949; + assign n1846 = (n1971 | ~N_N3750) & (~n1511 | ~N_N3890); + assign n1847 = PRESET | n1583; + assign n1848 = (~n1509 | ~N_N4118) & (~NLD3_9 | ~N_N3179); + assign n1849 = n1848 & (n1583 | ~N_N4232); + assign n1850 = (~NLD3_9 | ~N_N3336) & (~n1509 | ~N_N4209); + assign n1851 = n1850 & (n1583 | ~N_N3373); + assign n1852 = (n1583 | ~N_N3331) & (~n1509 | ~N_N3500); + assign n1853 = n1852 & (~NLD3_9 | ~N_N3464); + assign n1854 = n1700 ^ n1990; + assign n1855 = (~n1511 | ~N_N4176) & (~N_N4079 | n1971); + assign n1856 = n1944 ^ n1945; + assign n1857 = n1797 ^ n1946; + assign n1858 = (n1649 | ~N_N4237) & (n1588 | ~N_N4236); + assign n1859 = (n1649 | ~N_N4209) & (n1588 | ~N_N4208); + assign n1860 = n1708 & n1672; + assign n1861 = (n1671 | n1860) & (n1672 | n1708); + assign n1862 = n1861 ^ n1991; + assign n1863 = (n1583 | ~N_N3196) & (~n1509 | ~N_N3842); + assign n1864 = n1863 & (~NLD3_9 | ~N_N3212); + assign n1865 = (n1583 | ~N_N3250) & (~n1509 | ~N_N3924); + assign n1866 = n1865 & (~NLD3_9 | ~N_N3981); + assign n1867 = (~NLD3_9 | ~N_N3535) & (~n1509 | ~N_N4119); + assign n1868 = n1867 & (n1583 | ~N_N3580); + assign n1869 = (n1583 | ~N_N3062) & (~n1509 | ~N_N3808); + assign n1870 = n1869 & (~NLD3_9 | ~N_N3513); + assign n1871 = (n1552 | n1560_1) & (~N_N3340 | n1970); + assign n1872 = N_N3340 ^ n1923; + assign n1873 = n1871 & (n1872 | n1803); + assign n1874 = (~n1511 | ~N_N3810) & (~N_N3931 | n1971); + assign n1875 = (~n1511 | ~N_N3844) & (~N_N3875 | n1971); + assign n1876 = (n1529 | n1562) & (~n1513 | ~N_N4126); + assign n1877 = (n1543 | n1562) & (~n1513 | ~N_N4246); + assign n1878 = n1641 ^ n1947; + assign n1879 = n1924 ^ ~n1948; + assign n1880 = (~n1509 | ~N_N3940) & (~NLD3_9 | ~N_N4111); + assign n1881 = n1880 & (n1583 | ~N_N4218); + assign n1882 = n1926 ^ ~n1949; + assign n1883 = n1928 ^ ~n1950; + assign n1884 = NSr5_7 | PRESET; + assign n1885 = (~n1509 | ~N_N3923) & (~NLD3_9 | ~N_N3475); + assign n1886 = n1885 & (n1583 | ~N_N4230); + assign n1887 = n1795 ^ n1951; + assign n1888 = (~n1511 | ~N_N3800) & (~N_N3908 | n1971); + assign n1889 = n1785 ^ n1952; + assign n1890 = (n1971 | ~N_N3516) & (~n1511 | ~N_N4136); + assign n1891 = (n1971 | ~N_N3420) & (~n1511 | ~N_N4183); + assign n1892 = (n1546 | n1560_1) & (~N_N3369 | n1970); + assign n1893 = n1892 & (n1565_1 | n1803); + assign n1894 = (~N_N3862 | n1971) & (~n1511 | ~N_N3813); + assign n1895 = (n1549 | n1560_1) & (~N_N4093 | n1970); + assign n1896 = n1895 & (n1569 | n1803); + assign n1897 = (~n1511 | ~N_N4208) & (~N_N4158 | n1971); + assign n1898 = (~n1511 | ~N_N3807) & (~N_N3713 | n1971); + assign n1899 = (n1583 | ~N_N3248) & (~n1509 | ~N_N3872); + assign n1900 = n1899 & (~NLD3_9 | ~N_N3761); + assign n1901 = N_N3965 ^ n1780; + assign n1902 = (n1539 | n1562) & (~n1513 | ~N_N4036); + assign n1903 = (n1535_1 | n1562) & (~n1513 | ~N_N4004); + assign n1904 = (n1583 | ~N_N3011) & (~n1509 | ~N_N4177); + assign n1905 = n1904 & (~NLD3_9 | ~N_N3884); + assign n1906 = (n1555_1 | n1560_1) & (~N_N3283 | n1970); + assign n1907 = N_N3283 ^ n1564; + assign n1908 = n1906 & (n1907 | n1803); + assign n1909 = (~n1511 | ~N_N3470) & (~N_N3821 | n1971); + assign n1910 = n1789 ^ n1953; + assign n1911 = n1777 ^ n1972; + assign n1912 = (n1532 | n1562) & (~n1513 | ~N_N3961); + assign n1913 = n1791 ^ n1954; + assign n1914 = (~n1511 | ~N_N3868) & (~N_N3832 | n1971); + assign n1915 = (~N_N3794 | n1971) & (~n1511 | ~N_N3919); + assign n1916 = (~n1511 | ~N_N3871) & (~N_N3214 | n1971); + assign n1175 = n1058 & ~NSr3_9; + assign n1918 = ~PRESET & Pover_0_0_ & (~NGFDN_3 | NDN3_11); + assign n1136 = n1175 | n1918; + assign n1920 = ~PRESET & Pnext_0_0_ & (~NLD3_9 | NDN5_16); + assign n1440 = ~PRESET & n1957; + assign n373 = n1920 | n1440; + assign n1923 = N_N3283 | n1564; + assign n1924 = n1612 ^ n1596; + assign n1925 = n1619 ^ n1598; + assign n1926 = n1620 ^ n1594; + assign n1927 = n1627 ^ n1599; + assign n1928 = n1628 ^ n1593; + assign n1929 = n1604 ^ n1600; + assign n1930 = n1604 & n1600 & n1592; + assign n1931 = n1930 ^ n1601; + assign n1932 = n1642 ^ n1643; + assign n1933 = n1590 ^ n1979; + assign n1934 = n1932 ^ n1933; + assign n1935 = n1633 ^ n1603; + assign n1936 = n1750 ^ ~N_N4197; + assign n1937 = n1615 ^ n1606; + assign n1938 = n1622 ^ n1623; + assign n1939 = n1630 ^ n1631; + assign n1940 = n1636 ^ n1637; + assign n1941 = n1774 ^ ~N_N3992; + assign n1942 = n1768 ^ ~N_N4018; + assign n1943 = n1759 ^ ~N_N3949; + assign n1944 = n1679 ^ n1680; + assign n1945 = n1651 | n1650; + assign n1946 = n1753 ^ ~N_N3912; + assign n1947 = n1639 ^ n1602; + assign n1948 = n1611 ^ n1613; + assign n1949 = n1617 ^ n1618; + assign n1950 = n1625 ^ n1626; + assign n1951 = n1756 ^ ~N_N4145; + assign n1952 = n1771 ^ ~N_N3996; + assign n1953 = n1765 ^ ~N_N3974; + assign n1954 = n1762 ^ ~N_N4083; + assign n1955 = n947 & ~N_N4214; + assign n1956 = n1571 & n1573 & n1575_1 & n1565_1 & n1569 & n1567; + assign n1957 = ~NLD3_9 & NDN5_9; + assign n1958 = ~PDN | NDN1_4; + assign n1959 = (~Preset_0_0_ & (~NLC1_2 | N_N3998)) | (NLC1_2 & N_N3998); + assign n1960 = ~NDN3_3 & ~NSr3_2; + assign n1961 = NDN2_2 | n1169; + assign n1962 = ~PRESET & n1589; + assign n1963 = n1601 & n1930; + assign n1964 = NSr5_8 | NDN5_8; + assign n1965 = NSr5_4 | NDN5_4; + assign n1966 = NSr5_7 | NDN5_7; + assign n1967 = NSr5_3 | NDN5_3; + assign n1968 = NSr5_5 | NDN5_5; + assign n1969 = NSr5_2 | NDN5_2; + assign n1970 = ~n1557 | n1559; + assign n1971 = PRESET | ~NLD3_9; + assign n1972 = n1781 ^ ~N_N4027; + assign n1973 = n1976 & (PRESET | n1805 | ~N_N4227); + assign n273 = ~n1973; + assign n1975 = n1532 & n1535_1 & n1539 & n1522 & n1529 & n1525_1; + assign n1976 = ~n1804 | n1807 | N_N4227; + assign n1480 = ~n1884; + assign n1485 = ~n1830; + assign n1979 = n1963 & n1591; + assign n1980 = n1595 | n1607; + assign n1981 = n1671 ^ n1672; + assign n1982 = n1675 ^ n1676; + assign n1983 = n1704 ^ n1705; + assign n1984 = n1608 ^ n1980; + assign n1985 = n1686 ^ n1687; + assign n1986 = n1694 ^ n1695; + assign n1987 = n1673 ^ n1674; + assign n1988 = n1690 ^ n1691; + assign n1989 = n1677 ^ n1678; + assign n1990 = n1698 ^ n1699; + assign n1991 = n1858 ^ n1859; + assign n1992 = n1975 & n1555_1 & n1552 & n1546 & ~N_N3999 & n1519 & n1543 & n1549; + assign n1993 = ~Preset_0_0_ & n1833; + always @ (posedge clock) begin + N_N4054 <= n63_1; + N_N3745 <= n68_1; + N_N4119 <= n73_1; + N_N3826 <= n78_1; + N_N3818 <= n83_1; + N_N3345 <= n88; + N_N3924 <= n93_1; + N_N3815 <= n98_1; + N_N3691 <= n103; + N_N3157 <= n108_1; + N_N3872 <= n113_1; + N_N3788 <= n118_1; + N_N3375 <= n123_1; + N_N3143 <= n128; + N_N4197 <= n133; + N_N3843 <= n138_1; + N_N3426 <= n143_1; + N_N4118 <= n148_1; + N_N3580 <= n153_1; + N_N3175 <= n158_1; + N_N3071 <= n163_1; + N_N3808 <= n168_1; + N_N3923 <= n173_1; + N_N3250 <= n178_1; + N_N4221 <= n183_1; + N_N3069 <= n188_1; + N_N3464 <= n193_1; + N_N3535 <= n198_1; + N_N3871 <= n203_1; + N_N3248 <= n208_1; + N_N4180 <= n213_1; + N_N3311 <= n218_1; + N_N3442 <= n223_1; + N_N3981 <= n228_1; + N_N3842 <= n233; + N_N3105 <= n238; + N_N4133 <= n243_1; + N_N4117 <= n248_1; + N_N3420 <= n253_1; + N_N3761 <= n258_1; + N_N3062 <= n263_1; + N_N4071 <= n268; + N_N4227 <= n273; + N_N3807 <= n278_1; + N_N4145 <= n283; + N_N3922 <= n288_1; + N_N3516 <= n293; + N_N3489 <= n298; + N_N4030 <= n303_1; + N_N3540 <= n308_1; + N_N3513 <= n313_1; + N_N4083 <= n318_1; + N_N3841 <= n323_1; + N_N4018 <= n328_1; + N_N3971 <= n333_1; + N_N4232 <= n338_1; + N_N4246 <= n343_1; + N_N3806 <= n348_1; + N_N3992 <= n353_1; + N_N4086 <= n358_1; + N_N4230 <= n363_1; + N_N4212 <= n368; + Pnext_0_0_ <= n373; + N_N3626 <= n377; + N_N3965 <= n382_1; + N_N3890 <= n387_1; + NDN3_11 <= n392_1; + NDN5_10 <= n397_1; + N_N3786 <= n402_1; + N_N4171 <= n407; + NDN5_16 <= n412_1; + N_N3799 <= n417_1; + N_N3844 <= n422_1; + N_N3196 <= n427; + N_N4126 <= n432_1; + N_N3681 <= n437_1; + N_N3679 <= n442; + N_N3340 <= n447; + N_N4116 <= n452_1; + N_N3810 <= n457; + N_N3235 <= n462; + N_N3283 <= n467; + N_N3716 <= n472; + N_N3701 <= n477; + N_N3921 <= n482; + N_N3625 <= n487_1; + N_N3751 <= n492; + N_N3736 <= n497; + N_N3870 <= n502_1; + N_N4024 <= n507; + N_N3876 <= n512; + N_N3840 <= n517_1; + N_N4021 <= n522_1; + N_N3932 <= n527; + NLC1_2 <= n532; + N_N3805 <= n537_1; + N_N3700 <= n542_1; + N_N3735 <= n547; + NLak3_2 <= n552; + NLak3_9 <= n557_1; + N_N3906 <= n562; + N_N3388 <= n567_1; + N_N4057 <= n572; + N_N3011 <= n577_1; + N_N3346 <= n582; + N_N3677 <= n587; + N_N4165 <= n592; + N_N4080 <= n597_1; + N_N3373 <= n602_1; + N_N3709 <= n607_1; + N_N4206 <= n612; + N_N3324 <= n617; + N_N3575 <= n622; + N_N4159 <= n627; + NAK5_2 <= n632; + N_N3916 <= n637_1; + N_N3743 <= n642_1; + N_N4242 <= n647; + N_N3312 <= n652; + N_N3733 <= n657; + N_N3774 <= n662_1; + N_N4214 <= n667; + N_N3294 <= n672; + N_N3796 <= n677; + N_N3574 <= n682_1; + N_N3791 <= n687_1; + N_N3480 <= n692; + N_N4243 <= n697; + N_N3940 <= n702_1; + N_N3509 <= n707; + N_N4015 <= n712_1; + N_N2989 <= n717; + N_N3919 <= n722_1; + N_N3578 <= n727_1; + N_N3529 <= n732; + N_N4222 <= n737; + N_N3910 <= n742_1; + N_N3868 <= n747; + N_N3947 <= n752_1; + N_N4181 <= n757; + N_N3793 <= n762; + N_N3822 <= n767_1; + N_N3813 <= n772; + N_N4114 <= n777; + N_N4134 <= n782; + N_N3866 <= n787; + N_N4218 <= n792; + N_N3939 <= n797; + N_N3776 <= n802_1; + N_N3387 <= n807_1; + N_N4194 <= n812_1; + N_N3821 <= n817; + N_N3882 <= n822_1; + N_N4167 <= n827_1; + N_N3800 <= n832_1; + N_N4237 <= n837; + N_N3417 <= n842_1; + N_N3918 <= n847_1; + N_N4158 <= n852_1; + N_N3630 <= n857_1; + N_N3344 <= n862; + N_N4072 <= n867_1; + N_N3274 <= n872_1; + N_N3473 <= n877; + N_N4205 <= n882_1; + N_N4111 <= n887_1; + N_N3680 <= n892_1; + N_N3838 <= n897_1; + N_N3262 <= n902; + N_N4099 <= n907; + N_N3607 <= n912; + N_N3323 <= n917; + N_N3612 <= n922; + N_N4079 <= n927_1; + PDN <= n932_1; + N_N3457 <= n936; + N_N3445 <= n941; + N_N3794 <= n946_1; + N_N3663 <= n951_1; + N_N3715 <= n956_1; + N_N4039 <= n961_1; + N_N3280 <= n966_1; + N_N4239 <= n971_1; + N_N3988 <= n976; + N_N3433 <= n981_1; + N_N4075 <= n986; + N_N3468 <= n991_1; + N_N4045 <= n996; + N_N3482 <= n1001_1; + N_N3832 <= n1006_1; + N_N3304 <= n1011; + N_N3750 <= n1016_1; + N_N3634 <= n1021; + N_N3293 <= n1026; + N_N3659 <= n1031_1; + N_N4252 <= n1036; + N_N3912 <= n1041_1; + N_N3862 <= n1046; + N_N3221 <= n1051_1; + N_N3875 <= n1056; + N_N3949 <= n1061_1; + N_N3908 <= n1066_1; + N_N3711 <= n1071; + N_N3931 <= n1076; + N_N3469 <= n1081_1; + N_N3436 <= n1086_1; + N_N3974 <= n1091_1; + N_N3905 <= n1096; + N_N3741 <= n1101; + N_N3369 <= n1106; + N_N3164 <= n1111; + N_N3500 <= n1116_1; + N_N3996 <= n1121; + N_N3356 <= n1126; + N_N4093 <= n1131; + Pover_0_0_ <= n1136; + N_N4224 <= n1140; + N_N4027 <= n1145; + NDN1_4 <= n1150; + N_N3384 <= n1155; + N_N4036 <= n1160; + N_N3968 <= n1165; + N_N4183 <= n1170; + NGFDN_3 <= n1175; + N_N4090 <= n1180_1; + N_N4004 <= n1185_1; + N_N3205 <= n1190; + N_N4136 <= n1195_1; + N_N3303 <= n1200_1; + N_N3533 <= n1205_1; + N_N3336 <= n1210_1; + N_N3961 <= n1215; + N_N3331 <= n1220; + N_N3203 <= n1225; + N_N4236 <= n1230_1; + N_N3884 <= n1235_1; + N_N3367 <= n1240; + N_N4140 <= n1245_1; + NDN2_2 <= n1250_1; + N_N4106 <= n1255; + N_N3100 <= n1260; + N_N4193 <= n1265; + N_N3470 <= n1270; + N_N3424 <= n1275_1; + N_N3959 <= n1280; + N_N3393 <= n1285_1; + N_N4042 <= n1290_1; + N_N3188 <= n1295_1; + N_N4095 <= n1300; + N_N3957 <= n1305; + N_N3517 <= n1310; + N_N4047 <= n1315; + N_N3081 <= n1320; + N_N3541 <= n1325; + N_N4177 <= n1330; + NDN3_3 <= n1335; + N_N4176 <= n1340; + N_N3585 <= n1345; + NDN3_8 <= n1350; + N_N4209 <= n1355; + N_N3824 <= n1360; + N_N4208 <= n1365; + N_N4120 <= n1370; + N_N3708 <= n1375; + N_N4220 <= n1380; + N_N3999 <= n1385; + N_N4223 <= n1390; + N_N3179 <= n1395; + N_N4179 <= n1400; + N_N3475 <= n1405; + N_N4132 <= n1410; + N_N4182 <= n1415; + N_N3797 <= n1420; + N_N3214 <= n1425; + N_N4070 <= n1430; + N_N4135 <= n1435; + NLD3_9 <= n1440; + NDN5_2 <= n1445; + NDN5_3 <= n1450; + N_N3778 <= n1455; + NDN5_4 <= n1460; + N_N3212 <= n1465; + NDN5_5 <= n1470; + NDN5_6 <= n1475; + NDN5_7 <= n1480; + NDN5_8 <= n1485; + N_N4073 <= n1490; + NDN5_9 <= n1495; + NEN5_9 <= n1500; + N_N3684 <= n1505; + N_N4056 <= n1510; + N_N3713 <= n1515; + N_N3829 <= n1520; + N_N4060 <= n1525; + NSr3_2 <= n1530; + NSr5_2 <= n1535; + NSr5_3 <= n1540; + N_N3462 <= n1545; + N_N3460 <= n1550; + NSr5_4 <= n1555; + NSr3_9 <= n1560; + NSr5_5 <= n1565; + NSr5_7 <= n1570; + NSr5_8 <= n1575; + N_N3998 <= n1580; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/dsip/dsip.v b/openfpga_flow/benchmarks/MCNC_Verilog/dsip/dsip.v new file mode 100644 index 000000000..a8275d9c1 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/dsip/dsip.v @@ -0,0 +1,1917 @@ +// Benchmark "top" written by ABC on Tue Mar 5 10:01:57 2019 + +module dsip ( clock, + pcount_3_, pkey_5_, pkey_131_, pkey_144_, pkey_157_, pkey_230_, + pkey_243_, pcount_2_, pkey_4_, pkey_132_, pkey_158_, pkey_169_, + pkey_242_, pcount_1_, pkey_146_, pkey_168_, pkey_245_, pcount_0_, + pkey_6_, pkey_130_, pkey_145_, pkey_244_, pkey_9_, pkey_16_, pkey_27_, + pkey_38_, pkey_49_, pkey_122_, pkey_148_, pkey_153_, pkey_166_, + pkey_221_, pkey_252_, pkey_8_, pkey_17_, pkey_26_, pkey_48_, pkey_110_, + pkey_121_, pkey_147_, pkey_154_, pkey_165_, pkey_220_, pkey_246_, + pkey_253_, pkey_18_, pkey_29_, pkey_36_, pkey_120_, pkey_155_, + pkey_164_, pkey_210_, pkey_249_, pkey_254_, pkey_19_, pkey_28_, + pkey_37_, pkey_46_, pkey_112_, pkey_149_, pkey_156_, pkey_163_, + pkey_211_, pkey_248_, pkey_56_, pkey_67_, pkey_78_, pkey_89_, + pkey_113_, pkey_126_, pkey_139_, pkey_162_, pkey_212_, pkey_225_, + pkey_238_, pkey_57_, pkey_66_, pkey_88_, pkey_114_, pkey_125_, + pkey_150_, pkey_161_, pkey_213_, pkey_224_, pkey_58_, pkey_69_, + pkey_76_, pkey_115_, pkey_124_, pkey_137_, pkey_160_, pkey_214_, + pkey_250_, pkey_59_, pkey_68_, pkey_77_, pkey_86_, pkey_116_, + pkey_123_, pkey_138_, pkey_152_, pkey_222_, pkey_237_, pkey_251_, + pkey_1_, pkey_96_, pkey_117_, pkey_140_, pkey_216_, pkey_229_, + pkey_234_, pkey_0_, pkey_97_, pkey_118_, pkey_129_, pkey_136_, + pkey_217_, pkey_228_, pkey_235_, pkey_3_, pkey_98_, pkey_128_, + pkey_133_, pkey_142_, pkey_218_, pkey_227_, pkey_232_, pkey_241_, + pkey_2_, pkey_99_, pkey_134_, pkey_141_, pkey_219_, pkey_226_, + pkey_233_, pkey_240_, pkey_70_, pkey_81_, pkey_92_, pkey_180_, + pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, + pkey_50_, pkey_61_, pkey_94_, pkey_182_, pkey_195_, pkey_209_, + pstart_0_, pkey_51_, pkey_60_, pkey_109_, pkey_181_, pkey_196_, + pkey_208_, pkey_52_, pkey_74_, pkey_85_, pkey_104_, pkey_171_, + pkey_197_, pkey_203_, pencrypt_0_, pkey_53_, pkey_62_, pkey_75_, + pkey_84_, pkey_172_, pkey_198_, pkey_202_, pkey_54_, pkey_65_, + pkey_72_, pkey_83_, pkey_90_, pkey_106_, pkey_205_, pkey_64_, pkey_73_, + pkey_82_, pkey_91_, pkey_105_, pkey_170_, pkey_204_, pkey_12_, + pkey_34_, pkey_45_, pkey_100_, pkey_188_, pkey_13_, pkey_22_, pkey_35_, + pkey_44_, pkey_176_, pkey_187_, pkey_14_, pkey_25_, pkey_32_, pkey_43_, + pkey_102_, pkey_173_, pkey_201_, pkey_24_, pkey_33_, pkey_42_, + pkey_101_, pkey_174_, pkey_189_, pkey_200_, pkey_30_, pkey_41_, + pkey_179_, pkey_184_, pkey_40_, pkey_190_, pkey_10_, pkey_21_, + pkey_177_, pkey_186_, pkey_11_, pkey_20_, pkey_178_, pkey_185_, + pkey_192_, + pksi_50_, pksi_61_, pksi_72_, pksi_83_, pksi_94_, pksi_102_, pksi_115_, + pksi_128_, pdata_ready_0_, pksi_51_, pksi_60_, pksi_73_, pksi_82_, + pksi_95_, pksi_101_, pksi_116_, pksi_127_, pksi_52_, pksi_63_, + pksi_70_, pksi_81_, pksi_96_, pksi_100_, pksi_113_, pksi_53_, pksi_62_, + pksi_71_, pksi_80_, pksi_97_, pksi_114_, pksi_129_, pksi_54_, pksi_65_, + pksi_76_, pksi_87_, pksi_90_, pksi_119_, pksi_124_, pksi_191_, + pksi_55_, pksi_64_, pksi_77_, pksi_86_, pksi_91_, pksi_123_, pksi_56_, + pksi_67_, pksi_74_, pksi_85_, pksi_92_, pksi_117_, pksi_126_, pksi_57_, + pksi_66_, pksi_75_, pksi_84_, pksi_93_, pksi_118_, pksi_125_, + pksi_190_, pksi_14_, pksi_25_, pksi_36_, pksi_47_, pksi_120_, pksi_15_, + pksi_24_, pksi_37_, pksi_46_, pksi_109_, pnew_count_3_, pksi_16_, + pksi_27_, pksi_34_, pksi_45_, pksi_108_, pksi_122_, pksi_17_, pksi_26_, + pksi_35_, pksi_44_, pksi_107_, pksi_121_, pksi_10_, pksi_21_, pksi_32_, + pksi_43_, pksi_106_, pksi_111_, pnew_count_0_, pksi_11_, pksi_20_, + pksi_33_, pksi_42_, pksi_105_, pksi_112_, pksi_12_, pksi_23_, pksi_30_, + pksi_41_, pksi_104_, pnew_count_2_, pksi_13_, pksi_22_, pksi_31_, + pksi_40_, pksi_103_, pksi_110_, pnew_count_1_, pksi_3_, pksi_151_, + pksi_164_, pksi_177_, pksi_2_, pksi_152_, pksi_163_, pksi_178_, + pksi_189_, pksi_1_, pksi_166_, pksi_179_, pksi_188_, pksi_0_, + pksi_150_, pksi_165_, pksi_187_, pksi_18_, pksi_29_, pksi_142_, + pksi_168_, pksi_173_, pksi_186_, pksi_19_, pksi_28_, pksi_130_, + pksi_141_, pksi_167_, pksi_174_, pksi_185_, pksi_38_, pksi_49_, + pksi_131_, pksi_140_, pksi_175_, pksi_184_, pksi_39_, pksi_48_, + pksi_132_, pksi_169_, pksi_176_, pksi_183_, pksi_58_, pksi_69_, + pksi_133_, pksi_146_, pksi_159_, pksi_182_, pksi_59_, pksi_68_, + pksi_134_, pksi_145_, pksi_170_, pksi_181_, pksi_9_, pksi_78_, + pksi_89_, pksi_135_, pksi_144_, pksi_157_, pksi_171_, pksi_180_, + pksi_8_, pksi_79_, pksi_88_, pksi_136_, pksi_143_, pksi_158_, + pksi_172_, pksi_7_, pksi_98_, pksi_137_, pksi_155_, pksi_160_, pksi_6_, + pksi_99_, pksi_138_, pksi_149_, pksi_156_, pksi_5_, pksi_139_, + pksi_148_, pksi_153_, pksi_162_, pksi_4_, pksi_147_, pksi_154_, + pksi_161_ ); + input pcount_3_, pkey_5_, pkey_131_, pkey_144_, pkey_157_, pkey_230_, + pkey_243_, pcount_2_, pkey_4_, pkey_132_, pkey_158_, pkey_169_, + pkey_242_, pcount_1_, pkey_146_, pkey_168_, pkey_245_, pcount_0_, + pkey_6_, pkey_130_, pkey_145_, pkey_244_, pkey_9_, pkey_16_, pkey_27_, + pkey_38_, pkey_49_, pkey_122_, pkey_148_, pkey_153_, pkey_166_, + pkey_221_, pkey_252_, pkey_8_, pkey_17_, pkey_26_, pkey_48_, pkey_110_, + pkey_121_, pkey_147_, pkey_154_, pkey_165_, pkey_220_, pkey_246_, + pkey_253_, pkey_18_, pkey_29_, pkey_36_, pkey_120_, pkey_155_, + pkey_164_, pkey_210_, pkey_249_, pkey_254_, pkey_19_, pkey_28_, + pkey_37_, pkey_46_, pkey_112_, pkey_149_, pkey_156_, pkey_163_, + pkey_211_, pkey_248_, pkey_56_, pkey_67_, pkey_78_, pkey_89_, + pkey_113_, pkey_126_, pkey_139_, pkey_162_, pkey_212_, pkey_225_, + pkey_238_, pkey_57_, pkey_66_, pkey_88_, pkey_114_, pkey_125_, + pkey_150_, pkey_161_, pkey_213_, pkey_224_, pkey_58_, pkey_69_, + pkey_76_, pkey_115_, pkey_124_, pkey_137_, pkey_160_, pkey_214_, + pkey_250_, pkey_59_, pkey_68_, pkey_77_, pkey_86_, pkey_116_, + pkey_123_, pkey_138_, pkey_152_, pkey_222_, pkey_237_, pkey_251_, + pkey_1_, pkey_96_, pkey_117_, pkey_140_, pkey_216_, pkey_229_, + pkey_234_, pkey_0_, pkey_97_, pkey_118_, pkey_129_, pkey_136_, + pkey_217_, pkey_228_, pkey_235_, pkey_3_, pkey_98_, pkey_128_, + pkey_133_, pkey_142_, pkey_218_, pkey_227_, pkey_232_, pkey_241_, + pkey_2_, pkey_99_, pkey_134_, pkey_141_, pkey_219_, pkey_226_, + pkey_233_, pkey_240_, pkey_70_, pkey_81_, pkey_92_, pkey_180_, + pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, clock, + pkey_50_, pkey_61_, pkey_94_, pkey_182_, pkey_195_, pkey_209_, + pstart_0_, pkey_51_, pkey_60_, pkey_109_, pkey_181_, pkey_196_, + pkey_208_, pkey_52_, pkey_74_, pkey_85_, pkey_104_, pkey_171_, + pkey_197_, pkey_203_, pencrypt_0_, pkey_53_, pkey_62_, pkey_75_, + pkey_84_, pkey_172_, pkey_198_, pkey_202_, pkey_54_, pkey_65_, + pkey_72_, pkey_83_, pkey_90_, pkey_106_, pkey_205_, pkey_64_, pkey_73_, + pkey_82_, pkey_91_, pkey_105_, pkey_170_, pkey_204_, pkey_12_, + pkey_34_, pkey_45_, pkey_100_, pkey_188_, pkey_13_, pkey_22_, pkey_35_, + pkey_44_, pkey_176_, pkey_187_, pkey_14_, pkey_25_, pkey_32_, pkey_43_, + pkey_102_, pkey_173_, pkey_201_, pkey_24_, pkey_33_, pkey_42_, + pkey_101_, pkey_174_, pkey_189_, pkey_200_, pkey_30_, pkey_41_, + pkey_179_, pkey_184_, pkey_40_, pkey_190_, pkey_10_, pkey_21_, + pkey_177_, pkey_186_, pkey_11_, pkey_20_, pkey_178_, pkey_185_, + pkey_192_; + output pksi_50_, pksi_61_, pksi_72_, pksi_83_, pksi_94_, pksi_102_, + pksi_115_, pksi_128_, pdata_ready_0_, pksi_51_, pksi_60_, pksi_73_, + pksi_82_, pksi_95_, pksi_101_, pksi_116_, pksi_127_, pksi_52_, + pksi_63_, pksi_70_, pksi_81_, pksi_96_, pksi_100_, pksi_113_, pksi_53_, + pksi_62_, pksi_71_, pksi_80_, pksi_97_, pksi_114_, pksi_129_, pksi_54_, + pksi_65_, pksi_76_, pksi_87_, pksi_90_, pksi_119_, pksi_124_, + pksi_191_, pksi_55_, pksi_64_, pksi_77_, pksi_86_, pksi_91_, pksi_123_, + pksi_56_, pksi_67_, pksi_74_, pksi_85_, pksi_92_, pksi_117_, pksi_126_, + pksi_57_, pksi_66_, pksi_75_, pksi_84_, pksi_93_, pksi_118_, pksi_125_, + pksi_190_, pksi_14_, pksi_25_, pksi_36_, pksi_47_, pksi_120_, pksi_15_, + pksi_24_, pksi_37_, pksi_46_, pksi_109_, pnew_count_3_, pksi_16_, + pksi_27_, pksi_34_, pksi_45_, pksi_108_, pksi_122_, pksi_17_, pksi_26_, + pksi_35_, pksi_44_, pksi_107_, pksi_121_, pksi_10_, pksi_21_, pksi_32_, + pksi_43_, pksi_106_, pksi_111_, pnew_count_0_, pksi_11_, pksi_20_, + pksi_33_, pksi_42_, pksi_105_, pksi_112_, pksi_12_, pksi_23_, pksi_30_, + pksi_41_, pksi_104_, pnew_count_2_, pksi_13_, pksi_22_, pksi_31_, + pksi_40_, pksi_103_, pksi_110_, pnew_count_1_, pksi_3_, pksi_151_, + pksi_164_, pksi_177_, pksi_2_, pksi_152_, pksi_163_, pksi_178_, + pksi_189_, pksi_1_, pksi_166_, pksi_179_, pksi_188_, pksi_0_, + pksi_150_, pksi_165_, pksi_187_, pksi_18_, pksi_29_, pksi_142_, + pksi_168_, pksi_173_, pksi_186_, pksi_19_, pksi_28_, pksi_130_, + pksi_141_, pksi_167_, pksi_174_, pksi_185_, pksi_38_, pksi_49_, + pksi_131_, pksi_140_, pksi_175_, pksi_184_, pksi_39_, pksi_48_, + pksi_132_, pksi_169_, pksi_176_, pksi_183_, pksi_58_, pksi_69_, + pksi_133_, pksi_146_, pksi_159_, pksi_182_, pksi_59_, pksi_68_, + pksi_134_, pksi_145_, pksi_170_, pksi_181_, pksi_9_, pksi_78_, + pksi_89_, pksi_135_, pksi_144_, pksi_157_, pksi_171_, pksi_180_, + pksi_8_, pksi_79_, pksi_88_, pksi_136_, pksi_143_, pksi_158_, + pksi_172_, pksi_7_, pksi_98_, pksi_137_, pksi_155_, pksi_160_, pksi_6_, + pksi_99_, pksi_138_, pksi_149_, pksi_156_, pksi_5_, pksi_139_, + pksi_148_, pksi_153_, pksi_162_, pksi_4_, pksi_147_, pksi_154_, + pksi_161_; + reg pksi_17_, pksi_185_, n_n2410, pksi_170_, pksi_155_, pksi_147_, + pksi_109_, n_n2513, pksi_19_, n_n2396, n_n2412, n_n121, pksi_148_, + n_n2448, pksi_107_, pksi_110_, pksi_9_, pksi_176_, pksi_180_, + pksi_178_, pksi_135_, pksi_129_, pksi_100_, pksi_117_, pksi_118_, + pksi_5_, pksi_169_, n_n2408, pksi_184_, pksi_125_, pksi_138_, + pksi_114_, pksi_99_, pksi_85_, pksi_14_, pksi_4_, pksi_186_, n_n2420, + pksi_141_, pksi_113_, pksi_115_, pksi_98_, pksi_2_, pksi_23_, + pksi_177_, pksi_189_, n_n2485, n_n2495, pksi_97_, pksi_102_, pksi_11_, + pksi_173_, pksi_179_, pksi_171_, pksi_104_, pksi_103_, n_n2384, + pksi_183_, pksi_172_, n_n2416, pksi_116_, pksi_96_, pksi_119_, + pksi_84_, pksi_159_, n_n2440, pksi_160_, pksi_128_, pksi_127_, + pksi_142_, n_n2272, pksi_149_, pksi_162_, pksi_154_, pksi_121_, + pksi_134_, pksi_126_, pksi_82_, n_n2430, pksi_153_, pksi_165_, + pksi_137_, n_n2481, pksi_101_, pksi_93_, pksi_161_, pksi_156_, n_n2452, + n_n2462, pksi_123_, pksi_111_, pksi_92_, pksi_15_, n_n109, pksi_145_, + pksi_144_, pksi_150_, pksi_124_, pksi_132_, pksi_130_, pksi_105_, + pksi_112_, n_n10, pksi_6_, pksi_188_, pksi_152_, pksi_163_, pksi_166_, + pksi_131_, n_n2474, pksi_136_, pksi_108_, n_n2517, n_n2268, pksi_175_, + pksi_190_, pksi_164_, pksi_158_, pksi_167_, pksi_133_, n_n2476, + pksi_122_, n_n2507, pksi_75_, pksi_182_, pksi_174_, pksi_157_, + pksi_151_, pksi_146_, pksi_140_, pksi_120_, n_n168, pksi_106_, + pksi_57_, pksi_36_, pksi_38_, pksi_28_, n_n2374, pksi_53_, pksi_27_, + pksi_26_, pksi_47_, pksi_1_, pksi_63_, pksi_34_, pksi_24_, pksi_30_, + pksi_18_, pksi_79_, pksi_54_, n_n2337, pksi_46_, pksi_39_, pksi_8_, + n_n2277, pksi_91_, pksi_51_, pksi_70_, pksi_0_, pksi_73_, pksi_89_, + pksi_60_, pksi_48_, pksi_22_, n_n2280, pksi_77_, pksi_64_, pksi_56_, + pksi_80_, pksi_81_, n_n2301, pksi_66_, pksi_72_, pksi_78_, pksi_69_, + n_n2320, pksi_40_, pksi_32_, pksi_94_, pksi_87_, pksi_61_, pksi_59_, + n_n2333, pksi_42_, pksi_86_, pksi_76_, n_n2305, pksi_50_, pksi_33_, + pksi_12_, pksi_74_, pksi_95_, pksi_58_, pksi_62_, pksi_29_, pksi_3_, + pksi_83_, pksi_68_, pksi_71_, pksi_37_, pksi_41_, n_n2365, n_n2369, + n_n2288, pksi_55_, pksi_52_, pksi_45_, pksi_43_, pksi_16_, pksi_10_, + n_n2310, pksi_67_, pksi_31_, pksi_25_, pksi_35_, pksi_20_, pksi_21_, + pksi_49_, pksi_65_, pksi_44_, n_n2342, n_n2352, pksi_7_, pksi_13_; + wire n1327_1, n1328, n1329, n1330, n1331, n1332_1, n1341, n1342, n1343, + n1344_1, n1345, n1346, n1347, n1348_1, n1349, n1350, n1351, n1352_1, + n1353, n1354, n1355, n1356_1, n1357, n1358, n1359, n1360, n1361_1, + n1362, n1363, n1364, n1365_1, n1366, n1367, n1368, n1369, n1370_1, + n1371, n1372, n1373, n1374_1, n1375, n1376, n1377, n1378_1, n1379, + n1380, n1381, n1382_1, n1383, n1384, n1385, n1386_1, n1387, n1388, + n1389, n1390_1, n1391, n1392, n1393, n1394_1, n1395, n1396, n1397, + n1398_1, n1399, n1400, n1401, n1402_1, n1403, n1404, n1405, n1406, + n1407_1, n1408, n1409, n1410, n1411_1, n1412, n1413, n1414, n1415_1, + n1416, n1417, n1418, n1419_1, n1420, n1421, n1422, n1423_1, n1424, + n1425, n1426, n1427_1, n1428, n1429, n1430, n1431, n1432_1, n1433, + n1434, n1435, n1436_1, n1437, n1438, n1439, n1440_1, n1441, n1442, + n1443, n1444_1, n1445, n1446, n1447, n1448_1, n1449, n1450, n1451, + n1452_1, n1453, n1454, n1455, n1456_1, n1457, n1458, n1459, n1460_1, + n1461, n1462, n1463, n1464_1, n1465, n1466, n1467, n1468_1, n1469, + n1470, n1471, n1472_1, n1473, n1474, n1475, n1476_1, n1477, n1478, + n1479, n1480_1, n1481, n1482, n1483, n1484, n1485_1, n1486, n1487, + n1488, n1489_1, n1490, n1491, n1492, n1493_1, n1494, n1495, n1496, + n1497_1, n1498, n1499, n1500, n1501, n1502_1, n1503, n1504, n1505, + n1506_1, n1507, n1508, n1509, n1510_1, n1511, n1512, n1513, n1514_1, + n1515, n1516, n1517, n1518_1, n1519, n1520, n1521, n1522_1, n1523, + n1524, n1525, n1526_1, n1527, n1528, n1529, n1530_1, n1531, n1532, + n1533, n1534_1, n1535, n1536, n1537, n1538_1, n1539, n1540, n1541, + n1542, n1543_1, n1544, n1545, n1546, n1547_1, n1548, n1549, n1550, + n1551_1, n1552, n1553, n1554, n1555_1, n1556, n1557, n1558, n1559_1, + n1560, n1561, n1562, n1563_1, n1564, n1565, n1566, n1567, n1568_1, + n1569, n1570, n1571, n1572_1, n1573, n1574, n1575, n1576_1, n1577, + n1578, n1579, n1580_1, n1581, n1582, n1583, n1584_1, n1585, n1586, + n1587, n1588, n1589_1, n1590, n1591, n1592, n1593_1, n1594, n1595, + n1596, n1597_1, n1598, n1599, n1600, n1601_1, n1602, n1603, n1604, + n1605_1, n1606, n1607, n1608, n1609_1, n1610, n1611, n1612, n1613_1, + n1614, n1615, n1616, n1617, n1618_1, n1619, n1620, n1621, n1622_1, + n1623, n1624, n1625, n1626_1, n1627, n1628, n1629, n1630_1, n1631, + n1632, n1633, n1634, n1635_1, n1636, n1637, n1638, n1639_1, n1640, + n1641, n1642, n1643_1, n1644, n1645, n1646, n1647_1, n1648, n1649, + n1650, n1651_1, n1652, n1653, n1654, n1655_1, n1656, n1657, n1658, + n1659_1, n1660, n1661, n1662, n1663_1, n1664, n1665, n1666, n1667_1, + n1668, n1669, n1670, n1671_1, n1672, n1673, n1674, n1675_1, n1676, + n1677, n1678, n1679_1, n1680, n1681, n1682, n1683_1, n1684, n1685, + n1686, n1687_1, n1688, n1689, n1690, n1691_1, n1692, n1693, n1694, + n1695, n1696_1, n1697, n1698, n1699, n1700, n1701_1, n1702, n1703, + n1704, n1705, n1706_1, n1707, n1708, n1709, n1710_1, n1711, n1712, + n1713, n1714_1, n1715, n1716, n1717, n1718_1, n1719, n1720, n1721, + n1722_1, n1723, n1724, n1725, n1726_1, n1727, n1728, n1729, n1730_1, + n1731, n1732, n1733, n1734, n1735_1, n1736, n1737, n1738, n1739_1, + n1740, n1741, n1742, n1743_1, n1744, n1745, n1746, n1747_1, n1748, + n1749, n1750, n1751_1, n1752, n1753, n1754, n1755_1, n1756, n1757, + n1758, n1759_1, n1760, n1761, n1762, n1763_1, n1764, n1765, n1766, + n1767_1, n1768, n1769, n1770, n1771_1, n1772, n1773, n1774, n1775, + n1776_1, n1777, n1778, n1779, n1780, n1781_1, n1782, n1783, n1784, + n1785_1, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, + n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, + n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, + n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, + n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, + n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, + n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, + n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, + n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, + n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, + n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, + n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, + n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, + n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, + n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, + n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, + n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, + n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, + n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, + n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, + n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, + n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, + n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, + n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, + n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, + n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, + n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, + n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, + n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, + n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, + n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, + n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, + n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, + n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, + n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, + n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, + n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, + n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, + n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, + n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, + n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, + n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, + n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, + n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, + n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, + n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, + n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, + n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, + n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, + n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, + n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, + n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, + n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, + n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, + n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, + n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, + n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, + n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, + n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, + n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, + n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, + n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, + n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, + n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, + n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, + n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, + n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, + n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, + n2465, n2466, n2467, n853, n857, n861, n866, n870, n874, n878, n882, + n887, n891, n896, n901, n906, n910, n915, n919, n923, n927, n931, n935, + n939, n943, n947, n951, n955, n959, n963, n967, n972, n976, n980, n984, + n988, n992, n996, n1000, n1004, n1008, n1013, n1017, n1021, n1025, + n1029, n1033, n1037, n1041, n1045, n1050, n1055, n1059, n1063, n1067, + n1071, n1075, n1079, n1083, n1087, n1092, n1096, n1100, n1105, n1109, + n1113, n1117, n1121, n1125, n1130, n1134, n1138, n1142, n1146, n1151, + n1155, n1159, n1163, n1167, n1171, n1175, n1179, n1184, n1188, n1192, + n1196, n1201, n1205, n1209, n1213, n1217, n1222, n1227, n1231, n1235, + n1239, n1243, n1248, n1252, n1256, n1260, n1264, n1268, n1272, n1276, + n1280, n1285, n1289, n1293, n1297, n1301, n1305, n1309, n1314, n1318, + n1322, n1327, n1332, n1336, n1340, n1344, n1348, n1352, n1356, n1361, + n1365, n1370, n1374, n1378, n1382, n1386, n1390, n1394, n1398, n1402, + n1407, n1411, n1415, n1419, n1423, n1427, n1432, n1436, n1440, n1444, + n1448, n1452, n1456, n1460, n1464, n1468, n1472, n1476, n1480, n1485, + n1489, n1493, n1497, n1502, n1506, n1510, n1514, n1518, n1522, n1526, + n1530, n1534, n1538, n1543, n1547, n1551, n1555, n1559, n1563, n1568, + n1572, n1576, n1580, n1584, n1589, n1593, n1597, n1601, n1605, n1609, + n1613, n1618, n1622, n1626, n1630, n1635, n1639, n1643, n1647, n1651, + n1655, n1659, n1663, n1667, n1671, n1675, n1679, n1683, n1687, n1691, + n1696, n1701, n1706, n1710, n1714, n1718, n1722, n1726, n1730, n1735, + n1739, n1743, n1747, n1751, n1755, n1759, n1763, n1767, n1771, n1776, + n1781, n1785; + assign pdata_ready_0_ = (n1327_1 & n2465) | (n1328 & n1329); + assign pnew_count_3_ = n1343 | n1342 | (pstart_0_ & ~pencrypt_0_); + assign pnew_count_0_ = pstart_0_ ? ~pencrypt_0_ : ~pcount_0_; + assign pnew_count_2_ = n2467 | (pcount_2_ & ~n1331); + assign pnew_count_1_ = (pcount_1_ & (pcount_0_ ? ~pencrypt_0_ : (~pstart_0_ & pencrypt_0_))) | (~pcount_1_ & (pcount_0_ ? (~pstart_0_ & pencrypt_0_) : ~pencrypt_0_)) | (pstart_0_ & ~pencrypt_0_); + assign n853 = n2014 | n2015 | n2016 | n2018; + assign n857 = n2011 | n2012 | n2013 | n2020; + assign n861 = n2008 | n2009 | n2010 | n2022; + assign n866 = n2005 | n2006 | n2007 | n2024; + assign n870 = n2002 | n2003 | n2004 | n2026; + assign n874 = n1999 | n2000 | n2001 | n2028; + assign n878 = n1996 | n1997 | n1998 | n2030; + assign n882 = n1993 | n1994 | n1995 | n2032; + assign n887 = n1990 | n1991 | n1992 | n2034; + assign n891 = n1987 | n1988 | n1989 | n2036; + assign n896 = n1984 | n1985 | n1986 | n2038; + assign n901 = n1981 | n1982 | n1983 | n2040; + assign n906 = n1978 | n1979 | n1980 | n2042; + assign n910 = n1975 | n1976 | n1977 | n2044; + assign n915 = n1972 | n1973 | n1974 | n2046; + assign n919 = n1969 | n1970 | n1971 | n2048; + assign n923 = n1966 | n1967 | n1968 | n2050; + assign n927 = n1963 | n1964 | n1965 | n2052; + assign n931 = n1960 | n1961 | n1962 | n2054; + assign n935 = n1957 | n1958 | n1959 | n2056; + assign n939 = n1954 | n1955 | n1956 | n2058; + assign n943 = n1951 | n1952 | n1953 | n2060; + assign n947 = n1948 | n1949 | n1950 | n2062; + assign n951 = n1945 | n1946 | n1947 | n2064; + assign n955 = n1942 | n1943 | n1944 | n2066; + assign n959 = n1939 | n1940 | n1941 | n2068; + assign n963 = n1936 | n1937 | n1938 | n2070; + assign n967 = n1933 | n1934 | n1935 | n2072; + assign n972 = n1930 | n1931 | n1932 | n2074; + assign n976 = n1927 | n1928 | n1929 | n2076; + assign n980 = n1924 | n1925 | n1926 | n2078; + assign n984 = n1921 | n1922 | n1923 | n2080; + assign n988 = n1918 | n1919 | n1920 | n2082; + assign n992 = n1915 | n1916 | n1917 | n2084; + assign n996 = n1912 | n1913 | n1914 | n2086; + assign n1000 = n1909 | n1910 | n1911 | n2088; + assign n1004 = n1906 | n1907 | n1908 | n2090; + assign n1008 = n1903 | n1904 | n1905 | n2092; + assign n1013 = n1900 | n1901 | n1902 | n2094; + assign n1017 = n1897 | n1898 | n1899 | n2096; + assign n1021 = n1894 | n1895 | n1896 | n2098; + assign n1025 = n1891 | n1892 | n1893 | n2100; + assign n1029 = n1888 | n1889 | n1890 | n2102; + assign n1033 = n1885 | n1886 | n1887 | n2104; + assign n1037 = n1882 | n1883 | n1884 | n2106; + assign n1041 = n1879 | n1880 | n1881 | n2108; + assign n1045 = n1876 | n1877 | n1878 | n2110; + assign n1050 = n1873 | n1874 | n1875 | n2112; + assign n1055 = n1870 | n1871 | n1872 | n2114; + assign n1059 = n1867 | n1868 | n1869 | n2116; + assign n1063 = n1864 | n1865 | n1866 | n2118; + assign n1067 = n1861 | n1862 | n1863 | n2120; + assign n1071 = n1858 | n1859 | n1860 | n2122; + assign n1075 = n1855 | n1856 | n1857 | n2124; + assign n1079 = n1852 | n1853 | n1854 | n2126; + assign n1083 = n1849 | n1850 | n1851 | n2128; + assign n1087 = n1846 | n1847 | n1848 | n2130; + assign n1092 = n1843 | n1844 | n1845 | n2132; + assign n1096 = n1840 | n1841 | n1842 | n2134; + assign n1100 = n1837 | n1838 | n1839 | n2136; + assign n1105 = n1834 | n1835 | n1836 | n2138; + assign n1109 = n1831 | n1832 | n1833 | n2140; + assign n1113 = n1828 | n1829 | n1830 | n2142; + assign n1117 = n1825 | n1826 | n1827 | n2144; + assign n1121 = n1822 | n1823 | n1824 | n2146; + assign n1125 = n1819 | n1820 | n1821 | n2148; + assign n1130 = n1816 | n1817 | n1818 | n2150; + assign n1134 = n1813 | n1814 | n1815 | n2152; + assign n1138 = n1810 | n1811 | n1812 | n2154; + assign n1142 = n1807 | n1808 | n1809 | n2156; + assign n1146 = n1804 | n1805 | n1806 | n2158; + assign n1151 = n1801 | n1802 | n1803 | n2160; + assign n1155 = n1798 | n1799 | n1800 | n2162; + assign n1159 = n1795 | n1796 | n1797 | n2164; + assign n1163 = n1792 | n1793 | n1794 | n2166; + assign n1167 = n1789 | n1790 | n1791 | n2168; + assign n1171 = n1786 | n1787 | n1788 | n2170; + assign n1175 = n1783 | n1784 | n1785_1 | n2172; + assign n1179 = n1780 | n1781_1 | n1782 | n2174; + assign n1184 = n1777 | n1778 | n1779 | n2176; + assign n1188 = n1774 | n1775 | n1776_1 | n2178; + assign n1192 = n1771_1 | n1772 | n1773 | n2180; + assign n1196 = n1768 | n1769 | n1770 | n2182; + assign n1201 = n1765 | n1766 | n1767_1 | n2184; + assign n1205 = n1762 | n1763_1 | n1764 | n2186; + assign n1209 = n1759_1 | n1760 | n1761 | n2188; + assign n1213 = n1756 | n1757 | n1758 | n2190; + assign n1217 = n1753 | n1754 | n1755_1 | n2192; + assign n1222 = n1750 | n1751_1 | n1752 | n2194; + assign n1227 = n1747_1 | n1748 | n1749 | n2196; + assign n1231 = n1744 | n1745 | n1746 | n2198; + assign n1235 = n1741 | n1742 | n1743_1 | n2200; + assign n1239 = n1738 | n1739_1 | n1740 | n2202; + assign n1243 = n1735_1 | n1736 | n1737 | n2204; + assign n1248 = n1732 | n1733 | n1734 | n2206; + assign n1252 = n1729 | n1730_1 | n1731 | n2208; + assign n1256 = n1726_1 | n1727 | n1728 | n2210; + assign n1260 = n1723 | n1724 | n1725 | n2212; + assign n1264 = n1720 | n1721 | n1722_1 | n2214; + assign n1268 = n1717 | n1718_1 | n1719 | n2216; + assign n1272 = n1714_1 | n1715 | n1716 | n2218; + assign n1276 = n1711 | n1712 | n1713 | n2220; + assign n1280 = n1708 | n1709 | n1710_1 | n2222; + assign n1285 = n1705 | n1706_1 | n1707 | n2224; + assign n1289 = n1702 | n1703 | n1704 | n2226; + assign n1293 = n1699 | n1700 | n1701_1 | n2228; + assign n1297 = n1696_1 | n1697 | n1698 | n2230; + assign n1301 = n1693 | n1694 | n1695 | n2232; + assign n1305 = n1690 | n1691_1 | n1692 | n2234; + assign n1309 = n1687_1 | n1688 | n1689 | n2236; + assign n1314 = n1684 | n1685 | n1686 | n2238; + assign n1318 = n1681 | n1682 | n1683_1 | n2240; + assign n1322 = n1678 | n1679_1 | n1680 | n2242; + assign n1327 = n1675_1 | n1676 | n1677 | n2244; + assign n1332 = n1672 | n1673 | n1674 | n2246; + assign n1336 = n1669 | n1670 | n1671_1 | n2248; + assign n1340 = n1666 | n1667_1 | n1668 | n2250; + assign n1344 = n1663_1 | n1664 | n1665 | n2252; + assign n1348 = n1660 | n1661 | n1662 | n2254; + assign n1352 = n1657 | n1658 | n1659_1 | n2256; + assign n1356 = n1654 | n1655_1 | n1656 | n2258; + assign n1361 = n1651_1 | n1652 | n1653 | n2260; + assign n1365 = n1648 | n1649 | n1650 | n2262; + assign n1370 = n1645 | n1646 | n1647_1 | n2264; + assign n1374 = n1642 | n1643_1 | n1644 | n2266; + assign n1378 = n1639_1 | n1640 | n1641 | n2268; + assign n1382 = n1636 | n1637 | n1638 | n2270; + assign n1386 = n1633 | n1634 | n1635_1 | n2272; + assign n1390 = n1630_1 | n1631 | n1632 | n2274; + assign n1394 = n1627 | n1628 | n1629 | n2276; + assign n1398 = n1624 | n1625 | n1626_1 | n2278; + assign n1402 = n1621 | n1622_1 | n1623 | n2280; + assign n1407 = n1618_1 | n1619 | n1620 | n2282; + assign n1411 = n1615 | n1616 | n1617 | n2284; + assign n1415 = n1612 | n1613_1 | n1614 | n2286; + assign n1419 = n1609_1 | n1610 | n1611 | n2288; + assign n1423 = n1606 | n1607 | n1608 | n2290; + assign n1427 = n1603 | n1604 | n1605_1 | n2292; + assign n1432 = n1600 | n1601_1 | n1602 | n2294; + assign n1436 = n1597_1 | n1598 | n1599 | n2296; + assign n1440 = n1594 | n1595 | n1596 | n2298; + assign n1444 = n1591 | n1592 | n1593_1 | n2300; + assign n1448 = n1588 | n1589_1 | n1590 | n2302; + assign n1452 = n1585 | n1586 | n1587 | n2304; + assign n1456 = n1582 | n1583 | n1584_1 | n2306; + assign n1460 = n1579 | n1580_1 | n1581 | n2308; + assign n1464 = n1576_1 | n1577 | n1578 | n2310; + assign n1468 = n1573 | n1574 | n1575 | n2312; + assign n1472 = n1570 | n1571 | n1572_1 | n2314; + assign n1476 = n1567 | n1568_1 | n1569 | n2316; + assign n1480 = n1564 | n1565 | n1566 | n2318; + assign n1485 = n1561 | n1562 | n1563_1 | n2320; + assign n1489 = n1558 | n1559_1 | n1560 | n2322; + assign n1493 = n1555_1 | n1556 | n1557 | n2324; + assign n1497 = n1552 | n1553 | n1554 | n2326; + assign n1502 = n1549 | n1550 | n1551_1 | n2328; + assign n1506 = n1546 | n1547_1 | n1548 | n2330; + assign n1510 = n1543_1 | n1544 | n1545 | n2332; + assign n1514 = n1540 | n1541 | n1542 | n2334; + assign n1518 = n1537 | n1538_1 | n1539 | n2336; + assign n1522 = n1534_1 | n1535 | n1536 | n2338; + assign n1526 = n1531 | n1532 | n1533 | n2340; + assign n1530 = n1528 | n1529 | n1530_1 | n2342; + assign n1534 = n1525 | n1526_1 | n1527 | n2344; + assign n1538 = n1522_1 | n1523 | n1524 | n2346; + assign n1543 = n1519 | n1520 | n1521 | n2348; + assign n1547 = n1516 | n1517 | n1518_1 | n2350; + assign n1551 = n1513 | n1514_1 | n1515 | n2352; + assign n1555 = n1510_1 | n1511 | n1512 | n2354; + assign n1559 = n1507 | n1508 | n1509 | n2356; + assign n1563 = n1504 | n1505 | n1506_1 | n2358; + assign n1568 = n1501 | n1502_1 | n1503 | n2360; + assign n1572 = n1498 | n1499 | n1500 | n2362; + assign n1576 = n1495 | n1496 | n1497_1 | n2364; + assign n1580 = n1492 | n1493_1 | n1494 | n2366; + assign n1584 = n1489_1 | n1490 | n1491 | n2368; + assign n1589 = n1486 | n1487 | n1488 | n2370; + assign n1593 = n1483 | n1484 | n1485_1 | n2372; + assign n1597 = n1480_1 | n1481 | n1482 | n2374; + assign n1601 = n1477 | n1478 | n1479 | n2376; + assign n1605 = n1474 | n1475 | n1476_1 | n2378; + assign n1609 = n1471 | n1472_1 | n1473 | n2380; + assign n1613 = n1468_1 | n1469 | n1470 | n2382; + assign n1618 = n1465 | n1466 | n1467 | n2384; + assign n1622 = n1462 | n1463 | n1464_1 | n2386; + assign n1626 = n1459 | n1460_1 | n1461 | n2388; + assign n1630 = n1456_1 | n1457 | n1458 | n2390; + assign n1635 = n1453 | n1454 | n1455 | n2392; + assign n1639 = n1450 | n1451 | n1452_1 | n2394; + assign n1643 = n1447 | n1448_1 | n1449 | n2396; + assign n1647 = n1444_1 | n1445 | n1446 | n2398; + assign n1651 = n1441 | n1442 | n1443 | n2400; + assign n1655 = n1438 | n1439 | n1440_1 | n2402; + assign n1659 = n1435 | n1436_1 | n1437 | n2404; + assign n1663 = n1432_1 | n1433 | n1434 | n2406; + assign n1667 = n1429 | n1430 | n1431 | n2408; + assign n1671 = n1426 | n1427_1 | n1428 | n2410; + assign n1675 = n1423_1 | n1424 | n1425 | n2412; + assign n1679 = n1420 | n1421 | n1422 | n2414; + assign n1683 = n1417 | n1418 | n1419_1 | n2416; + assign n1687 = n1414 | n1415_1 | n1416 | n2418; + assign n1691 = n1411_1 | n1412 | n1413 | n2420; + assign n1696 = n1408 | n1409 | n1410 | n2422; + assign n1701 = n1405 | n1406 | n1407_1 | n2424; + assign n1706 = n1402_1 | n1403 | n1404 | n2426; + assign n1710 = n1399 | n1400 | n1401 | n2428; + assign n1714 = n1396 | n1397 | n1398_1 | n2430; + assign n1718 = n1393 | n1394_1 | n1395 | n2432; + assign n1722 = n1390_1 | n1391 | n1392 | n2434; + assign n1726 = n1387 | n1388 | n1389 | n2436; + assign n1730 = n1384 | n1385 | n1386_1 | n2438; + assign n1735 = n1381 | n1382_1 | n1383 | n2440; + assign n1739 = n1378_1 | n1379 | n1380 | n2442; + assign n1743 = n1375 | n1376 | n1377 | n2444; + assign n1747 = n1372 | n1373 | n1374_1 | n2446; + assign n1751 = n1369 | n1370_1 | n1371 | n2448; + assign n1755 = n1366 | n1367 | n1368 | n2450; + assign n1759 = n1363 | n1364 | n1365_1 | n2452; + assign n1763 = n1360 | n1361_1 | n1362 | n2454; + assign n1767 = n1357 | n1358 | n1359 | n2456; + assign n1771 = n1354 | n1355 | n1356_1 | n2458; + assign n1776 = n1351 | n1352_1 | n1353 | n2460; + assign n1781 = n1348_1 | n1349 | n1350 | n2462; + assign n1785 = n1345 | n1346 | n1347 | n2464; + assign n1327_1 = (~pcount_3_ & (pcount_2_ ? (pcount_1_ & pcount_0_) : (~pcount_1_ & ~pcount_0_))) | (pcount_1_ & ~pcount_0_ & pcount_3_ & pcount_2_); + assign n1328 = (~pcount_2_ & ~pcount_1_ & (~pcount_3_ | ~pcount_0_)) | (pcount_1_ & pcount_0_ & pcount_3_ & pcount_2_); + assign n1329 = pencrypt_0_ & ~pstart_0_ & pcount_1_ & pcount_0_; + assign n1330 = ~pstart_0_ | pencrypt_0_; + assign n1331 = (pencrypt_0_ & (pstart_0_ | (pcount_1_ & pcount_0_))) | (~pcount_1_ & ~pcount_0_ & ~pencrypt_0_); + assign n1332_1 = ~pstart_0_ & pencrypt_0_; + assign pksi_90_ = n_n10; + assign pksi_191_ = n_n121; + assign pksi_187_ = n_n121; + assign pksi_168_ = n_n109; + assign pksi_181_ = n_n109; + assign pksi_88_ = n_n10; + assign pksi_143_ = n_n168; + assign pksi_139_ = n_n168; + assign n1341 = ~pencrypt_0_ & ~pcount_0_ & ~pcount_2_ & ~pcount_1_; + assign n1342 = ~pcount_3_ & (n1344_1 | (pcount_2_ & n1329)); + assign n1343 = pcount_3_ & (~n1331 | n2466); + assign n1344_1 = ~pencrypt_0_ & ~pcount_0_ & ~pcount_2_ & ~pcount_1_; + assign n1345 = n1328 & n_n2374 & ~pstart_0_ & ~pencrypt_0_; + assign n1346 = ~n1328 & pksi_1_ & ~pstart_0_ & ~pencrypt_0_; + assign n1347 = ~n1327_1 & pksi_10_ & ~pstart_0_ & pencrypt_0_; + assign n1348_1 = ~n1328 & pksi_16_ & ~pstart_0_ & ~pencrypt_0_; + assign n1349 = n1328 & pksi_20_ & ~pstart_0_ & ~pencrypt_0_; + assign n1350 = ~n1327_1 & pksi_47_ & ~pstart_0_ & pencrypt_0_; + assign n1351 = ~n1328 & pksi_43_ & ~pstart_0_ & ~pencrypt_0_; + assign n1352_1 = n1328 & pksi_41_ & ~pstart_0_ & ~pencrypt_0_; + assign n1353 = ~n1327_1 & pksi_26_ & ~pstart_0_ & pencrypt_0_; + assign n1354 = ~n1328 & pksi_42_ & ~pstart_0_ & ~pencrypt_0_; + assign n1355 = n1328 & pksi_25_ & ~pstart_0_ & ~pencrypt_0_; + assign n1356_1 = ~n1327_1 & pksi_45_ & ~pstart_0_ & pencrypt_0_; + assign n1357 = ~n1328 & n_n2333 & ~pstart_0_ & ~pencrypt_0_; + assign n1358 = n1328 & pksi_40_ & ~pstart_0_ & ~pencrypt_0_; + assign n1359 = ~n1327_1 & pksi_52_ & ~pstart_0_ & pencrypt_0_; + assign n1360 = ~n1328 & pksi_57_ & ~pstart_0_ & ~pencrypt_0_; + assign n1361_1 = n1328 & pksi_67_ & ~pstart_0_ & ~pencrypt_0_; + assign n1362 = ~n1327_1 & pksi_59_ & ~pstart_0_ & pencrypt_0_; + assign n1363 = ~n1328 & pksi_56_ & ~pstart_0_ & ~pencrypt_0_; + assign n1364 = n1328 & pksi_66_ & ~pstart_0_ & ~pencrypt_0_; + assign n1365_1 = ~n1327_1 & pksi_61_ & ~pstart_0_ & pencrypt_0_; + assign n1366 = ~n1328 & n_n2374 & ~pstart_0_ & ~pencrypt_0_; + assign n1367 = n1327_1 & pksi_10_ & ~pstart_0_ & pencrypt_0_; + assign n1368 = n1328 & pksi_13_ & ~pstart_0_ & ~pencrypt_0_; + assign n1369 = ~n1328 & n_n2365 & ~pstart_0_ & ~pencrypt_0_; + assign n1370_1 = n1328 & pksi_16_ & ~pstart_0_ & ~pencrypt_0_; + assign n1371 = ~n1327_1 & pksi_28_ & ~pstart_0_ & pencrypt_0_; + assign n1372 = n1328 & n_n2352 & ~pstart_0_ & ~pencrypt_0_; + assign n1373 = ~n1328 & pksi_41_ & ~pstart_0_ & ~pencrypt_0_; + assign n1374_1 = ~n1327_1 & pksi_38_ & ~pstart_0_ & pencrypt_0_; + assign n1375 = ~n1328 & pksi_32_ & ~pstart_0_ & ~pencrypt_0_; + assign n1376 = n1328 & pksi_42_ & ~pstart_0_ & ~pencrypt_0_; + assign n1377 = ~n1327_1 & pksi_37_ & ~pstart_0_ & pencrypt_0_; + assign n1378_1 = ~n1328 & pksi_40_ & ~pstart_0_ & ~pencrypt_0_; + assign n1379 = n1328 & pksi_44_ & ~pstart_0_ & ~pencrypt_0_; + assign n1380 = ~n1327_1 & pksi_71_ & ~pstart_0_ & pencrypt_0_; + assign n1381 = ~n1328 & pksi_53_ & ~pstart_0_ & ~pencrypt_0_; + assign n1382_1 = n1327_1 & pksi_65_ & ~pstart_0_ & pencrypt_0_; + assign n1383 = n1328 & pksi_57_ & ~pstart_0_ & ~pencrypt_0_; + assign n1384 = ~n1328 & pksi_66_ & ~pstart_0_ & ~pencrypt_0_; + assign n1385 = n1328 & pksi_49_ & ~pstart_0_ & ~pencrypt_0_; + assign n1386_1 = ~n1327_1 & pksi_69_ & ~pstart_0_ & pencrypt_0_; + assign n1387 = ~n1328 & pksi_13_ & ~pstart_0_ & ~pencrypt_0_; + assign n1388 = n1328 & pksi_21_ & ~pstart_0_ & ~pencrypt_0_; + assign n1389 = ~n1327_1 & pksi_12_ & ~pstart_0_ & pencrypt_0_; + assign n1390_1 = n1328 & n_n2365 & ~pstart_0_ & ~pencrypt_0_; + assign n1391 = ~n1328 & pksi_3_ & ~pstart_0_ & ~pencrypt_0_; + assign n1392 = ~n1327_1 & pksi_7_ & ~pstart_0_ & pencrypt_0_; + assign n1393 = ~n1328 & pksi_29_ & ~pstart_0_ & ~pencrypt_0_; + assign n1394_1 = n1327_1 & pksi_41_ & ~pstart_0_ & pencrypt_0_; + assign n1395 = n1328 & pksi_33_ & ~pstart_0_ & ~pencrypt_0_; + assign n1396 = ~n1328 & n_n2342 & ~pstart_0_ & ~pencrypt_0_; + assign n1397 = n1327_1 & pksi_34_ & ~pstart_0_ & pencrypt_0_; + assign n1398_1 = n1328 & pksi_37_ & ~pstart_0_ & ~pencrypt_0_; + assign n1399 = ~n1328 & pksi_44_ & ~pstart_0_ & ~pencrypt_0_; + assign n1400 = n1328 & pksi_31_ & ~pstart_0_ & ~pencrypt_0_; + assign n1401 = ~n1327_1 & pksi_54_ & ~pstart_0_ & pencrypt_0_; + assign n1402_1 = ~n1328 & pksi_64_ & ~pstart_0_ & ~pencrypt_0_; + assign n1403 = n1328 & pksi_68_ & ~pstart_0_ & ~pencrypt_0_; + assign n1404 = ~n1327_1 & pksi_95_ & ~pstart_0_ & pencrypt_0_; + assign n1405 = ~n1328 & pksi_91_ & ~pstart_0_ & ~pencrypt_0_; + assign n1406 = n1328 & pksi_89_ & ~pstart_0_ & ~pencrypt_0_; + assign n1407_1 = ~n1327_1 & pksi_74_ & ~pstart_0_ & pencrypt_0_; + assign n1408 = ~n1328 & pksi_21_ & ~pstart_0_ & ~pencrypt_0_; + assign n1409 = n1328 & pksi_10_ & ~pstart_0_ & ~pencrypt_0_; + assign n1410 = ~n1327_1 & pksi_3_ & ~pstart_0_ & pencrypt_0_; + assign n1411_1 = ~n1328 & pksi_12_ & ~pstart_0_ & ~pencrypt_0_; + assign n1412 = n1328 & pksi_3_ & ~pstart_0_ & ~pencrypt_0_; + assign n1413 = ~n1327_1 & pksi_20_ & ~pstart_0_ & pencrypt_0_; + assign n1414 = ~n1328 & pksi_33_ & ~pstart_0_ & ~pencrypt_0_; + assign n1415_1 = n1328 & pksi_43_ & ~pstart_0_ & ~pencrypt_0_; + assign n1416 = ~n1327_1 & pksi_35_ & ~pstart_0_ & pencrypt_0_; + assign n1417 = n1328 & n_n2342 & ~pstart_0_ & ~pencrypt_0_; + assign n1418 = ~n1328 & pksi_25_ & ~pstart_0_ & ~pencrypt_0_; + assign n1419_1 = ~n1327_1 & pksi_34_ & ~pstart_0_ & pencrypt_0_; + assign n1420 = ~n1328 & pksi_31_ & ~pstart_0_ & ~pencrypt_0_; + assign n1421 = n1328 & pksi_52_ & ~pstart_0_ & ~pencrypt_0_; + assign n1422 = ~n1327_1 & pksi_63_ & ~pstart_0_ & pencrypt_0_; + assign n1423_1 = ~n1328 & n_n2301 & ~pstart_0_ & ~pencrypt_0_; + assign n1424 = n1328 & pksi_64_ & ~pstart_0_ & ~pencrypt_0_; + assign n1425 = ~n1327_1 & pksi_76_ & ~pstart_0_ & pencrypt_0_; + assign n1426 = ~n1328 & pksi_89_ & ~pstart_0_ & ~pencrypt_0_; + assign n1427_1 = n1328 & n_n2288 & ~pstart_0_ & ~pencrypt_0_; + assign n1428 = ~n1327_1 & pksi_86_ & ~pstart_0_ & pencrypt_0_; + assign n1429 = ~n1328 & n_n2369 & ~pstart_0_ & ~pencrypt_0_; + assign n1430 = n1328 & pksi_12_ & ~pstart_0_ & ~pencrypt_0_; + assign n1431 = ~n1327_1 & pksi_16_ & ~pstart_0_ & pencrypt_0_; + assign n1432_1 = ~n1328 & pksi_30_ & ~pstart_0_ & ~pencrypt_0_; + assign n1433 = n1328 & pksi_39_ & ~pstart_0_ & ~pencrypt_0_; + assign n1434 = ~n1327_1 & pksi_43_ & ~pstart_0_ & pencrypt_0_; + assign n1435 = ~n1328 & pksi_59_ & ~pstart_0_ & ~pencrypt_0_; + assign n1436_1 = n1328 & pksi_50_ & ~pstart_0_ & ~pencrypt_0_; + assign n1437 = ~n1327_1 & pksi_48_ & ~pstart_0_ & pencrypt_0_; + assign n1438 = ~n1328 & pksi_61_ & ~pstart_0_ & ~pencrypt_0_; + assign n1439 = n1328 & pksi_69_ & ~pstart_0_ & ~pencrypt_0_; + assign n1440_1 = ~n1327_1 & pksi_60_ & ~pstart_0_ & pencrypt_0_; + assign n1441 = ~n1328 & pksi_55_ & ~pstart_0_ & ~pencrypt_0_; + assign n1442 = n1328 & pksi_76_ & ~pstart_0_ & ~pencrypt_0_; + assign n1443 = ~n1327_1 & pksi_87_ & ~pstart_0_ & pencrypt_0_; + assign n1444_1 = ~n1328 & n_n2288 & ~pstart_0_ & ~pencrypt_0_; + assign n1445 = n1328 & pksi_83_ & ~pstart_0_ & ~pencrypt_0_; + assign n1446 = ~n1327_1 & pksi_94_ & ~pstart_0_ & pencrypt_0_; + assign n1447 = n1328 & n_n2369 & ~pstart_0_ & ~pencrypt_0_; + assign n1448_1 = ~n1328 & pksi_10_ & ~pstart_0_ & ~pencrypt_0_; + assign n1449 = n1327_1 & pksi_3_ & ~pstart_0_ & pencrypt_0_; + assign n1450 = ~n1328 & pksi_39_ & ~pstart_0_ & ~pencrypt_0_; + assign n1451 = n1328 & pksi_29_ & ~pstart_0_ & ~pencrypt_0_; + assign n1452_1 = ~n1327_1 & pksi_41_ & ~pstart_0_ & pencrypt_0_; + assign n1453 = ~n1328 & n_n2320 & ~pstart_0_ & ~pencrypt_0_; + assign n1454 = n1328 & pksi_59_ & ~pstart_0_ & ~pencrypt_0_; + assign n1455 = ~n1327_1 & pksi_70_ & ~pstart_0_ & pencrypt_0_; + assign n1456_1 = ~n1328 & pksi_69_ & ~pstart_0_ & ~pencrypt_0_; + assign n1457 = n1328 & pksi_58_ & ~pstart_0_ & ~pencrypt_0_; + assign n1458 = ~n1327_1 & pksi_51_ & ~pstart_0_ & pencrypt_0_; + assign n1459 = ~n1328 & pksi_68_ & ~pstart_0_ & ~pencrypt_0_; + assign n1460_1 = n1328 & pksi_55_ & ~pstart_0_ & ~pencrypt_0_; + assign n1461 = ~n1327_1 & pksi_78_ & ~pstart_0_ & pencrypt_0_; + assign n1462 = ~n1328 & pksi_83_ & ~pstart_0_ & ~pencrypt_0_; + assign n1463 = n1328 & pksi_74_ & ~pstart_0_ & ~pencrypt_0_; + assign n1464_1 = ~n1327_1 & pksi_72_ & ~pstart_0_ & pencrypt_0_; + assign n1465 = ~n1328 & pksi_24_ & ~pstart_0_ & ~pencrypt_0_; + assign n1466 = n1327_1 & pksi_25_ & ~pstart_0_ & pencrypt_0_; + assign n1467 = n1328 & pksi_32_ & ~pstart_0_ & ~pencrypt_0_; + assign n1468_1 = ~n1328 & pksi_36_ & ~pstart_0_ & ~pencrypt_0_; + assign n1469 = n1328 & pksi_27_ & ~pstart_0_ & ~pencrypt_0_; + assign n1470 = ~n1327_1 & pksi_44_ & ~pstart_0_ & pencrypt_0_; + assign n1471 = n1328 & n_n2320 & ~pstart_0_ & ~pencrypt_0_; + assign n1472_1 = ~n1328 & pksi_65_ & ~pstart_0_ & ~pencrypt_0_; + assign n1473 = ~n1327_1 & pksi_62_ & ~pstart_0_ & pencrypt_0_; + assign n1474 = ~n1328 & pksi_49_ & ~pstart_0_ & ~pencrypt_0_; + assign n1475 = n1328 & n_n2310 & ~pstart_0_ & ~pencrypt_0_; + assign n1476_1 = ~n1327_1 & pksi_58_ & ~pstart_0_ & pencrypt_0_; + assign n1477 = ~n1328 & pksi_95_ & ~pstart_0_ & ~pencrypt_0_; + assign n1478 = n1328 & pksi_78_ & ~pstart_0_ & ~pencrypt_0_; + assign n1479 = ~n1327_1 & pksi_81_ & ~pstart_0_ & pencrypt_0_; + assign n1480_1 = ~n1328 & pksi_74_ & ~pstart_0_ & ~pencrypt_0_; + assign n1481 = n1328 & pksi_86_ & ~pstart_0_ & ~pencrypt_0_; + assign n1482 = ~n1327_1 & pksi_80_ & ~pstart_0_ & pencrypt_0_; + assign n1483 = ~n1328 & pksi_46_ & ~pstart_0_ & ~pencrypt_0_; + assign n1484 = n1328 & pksi_24_ & ~pstart_0_ & ~pencrypt_0_; + assign n1485_1 = ~n1327_1 & pksi_25_ & ~pstart_0_ & pencrypt_0_; + assign n1486 = n1328 & n_n2333 & ~pstart_0_ & ~pencrypt_0_; + assign n1487 = ~n1328 & pksi_27_ & ~pstart_0_ & ~pencrypt_0_; + assign n1488 = ~n1327_1 & pksi_31_ & ~pstart_0_ & pencrypt_0_; + assign n1489_1 = ~n1328 & pksi_67_ & ~pstart_0_ & ~pencrypt_0_; + assign n1490 = n1328 & pksi_65_ & ~pstart_0_ & ~pencrypt_0_; + assign n1491 = ~n1327_1 & pksi_50_ & ~pstart_0_ & pencrypt_0_; + assign n1492 = ~n1328 & n_n2310 & ~pstart_0_ & ~pencrypt_0_; + assign n1493_1 = ~n1327_1 & n_n2305 & ~pstart_0_ & pencrypt_0_; + assign n1494 = n1328 & pksi_61_ & ~pstart_0_ & ~pencrypt_0_; + assign n1495 = ~n1328 & pksi_76_ & ~pstart_0_ & ~pencrypt_0_; + assign n1496 = n1328 & pksi_95_ & ~pstart_0_ & ~pencrypt_0_; + assign n1497_1 = ~n1327_1 & pksi_77_ & ~pstart_0_ & pencrypt_0_; + assign n1498 = ~n1328 & pksi_86_ & ~pstart_0_ & ~pencrypt_0_; + assign n1499 = ~n1327_1 & n_n2280 & ~pstart_0_ & pencrypt_0_; + assign n1500 = n1328 & pksi_94_ & ~pstart_0_ & ~pencrypt_0_; + assign n1501 = ~n1328 & pksi_48_ & ~pstart_0_ & ~pencrypt_0_; + assign n1502_1 = n1328 & pksi_56_ & ~pstart_0_ & ~pencrypt_0_; + assign n1503 = ~n1327_1 & n_n2310 & ~pstart_0_ & pencrypt_0_; + assign n1504 = ~n1328 & pksi_60_ & ~pstart_0_ & ~pencrypt_0_; + assign n1505 = n1328 & pksi_51_ & ~pstart_0_ & ~pencrypt_0_; + assign n1506_1 = ~n1327_1 & pksi_68_ & ~pstart_0_ & pencrypt_0_; + assign n1507 = ~n1328 & pksi_87_ & ~pstart_0_ & ~pencrypt_0_; + assign n1508 = n1328 & pksi_77_ & ~pstart_0_ & ~pencrypt_0_; + assign n1509 = ~n1327_1 & pksi_89_ & ~pstart_0_ & pencrypt_0_; + assign n1510_1 = ~n1328 & pksi_94_ & ~pstart_0_ & ~pencrypt_0_; + assign n1511 = n1328 & pksi_72_ & ~pstart_0_ & ~pencrypt_0_; + assign n1512 = ~n1327_1 & pksi_73_ & ~pstart_0_ & pencrypt_0_; + assign n1513 = ~n1328 & pksi_70_ & ~pstart_0_ & ~pencrypt_0_; + assign n1514_1 = n1328 & pksi_48_ & ~pstart_0_ & ~pencrypt_0_; + assign n1515 = ~n1327_1 & pksi_49_ & ~pstart_0_ & pencrypt_0_; + assign n1516 = ~n1328 & pksi_51_ & ~pstart_0_ & ~pencrypt_0_; + assign n1517 = n1328 & n_n2301 & ~pstart_0_ & ~pencrypt_0_; + assign n1518_1 = ~n1327_1 & pksi_55_ & ~pstart_0_ & pencrypt_0_; + assign n1519 = ~n1328 & pksi_78_ & ~pstart_0_ & ~pencrypt_0_; + assign n1520 = n1328 & pksi_87_ & ~pstart_0_ & ~pencrypt_0_; + assign n1521 = ~n1327_1 & pksi_91_ & ~pstart_0_ & pencrypt_0_; + assign n1522_1 = ~n1328 & pksi_72_ & ~pstart_0_ & ~pencrypt_0_; + assign n1523 = n1327_1 & pksi_73_ & ~pstart_0_ & pencrypt_0_; + assign n1524 = n1328 & pksi_80_ & ~pstart_0_ & ~pencrypt_0_; + assign n1525 = ~n1328 & pksi_2_ & ~pstart_0_ & ~pencrypt_0_; + assign n1526_1 = n1328 & pksi_14_ & ~pstart_0_ & ~pencrypt_0_; + assign n1527 = ~n1327_1 & pksi_8_ & ~pstart_0_ & pencrypt_0_; + assign n1528 = ~n1328 & pksi_62_ & ~pstart_0_ & ~pencrypt_0_; + assign n1529 = n1328 & pksi_70_ & ~pstart_0_ & ~pencrypt_0_; + assign n1530_1 = ~n1327_1 & pksi_66_ & ~pstart_0_ & pencrypt_0_; + assign n1531 = ~n1328 & pksi_58_ & ~pstart_0_ & ~pencrypt_0_; + assign n1532 = n1328 & n_n2305 & ~pstart_0_ & ~pencrypt_0_; + assign n1533 = ~n1327_1 & n_n2301 & ~pstart_0_ & pencrypt_0_; + assign n1534_1 = ~n1328 & pksi_81_ & ~pstart_0_ & ~pencrypt_0_; + assign n1535 = n1328 & pksi_91_ & ~pstart_0_ & ~pencrypt_0_; + assign n1536 = ~n1327_1 & pksi_83_ & ~pstart_0_ & pencrypt_0_; + assign n1537 = ~n1328 & pksi_80_ & ~pstart_0_ & ~pencrypt_0_; + assign n1538_1 = n1328 & n_n2280 & ~pstart_0_ & ~pencrypt_0_; + assign n1539 = ~n1327_1 & pksi_85_ & ~pstart_0_ & pencrypt_0_; + assign n1540 = ~n1328 & pksi_14_ & ~pstart_0_ & ~pencrypt_0_; + assign n1541 = n1328 & pksi_22_ & ~pstart_0_ & ~pencrypt_0_; + assign n1542 = ~n1327_1 & pksi_18_ & ~pstart_0_ & pencrypt_0_; + assign n1543_1 = ~n1328 & pksi_50_ & ~pstart_0_ & ~pencrypt_0_; + assign n1544 = n1328 & pksi_62_ & ~pstart_0_ & ~pencrypt_0_; + assign n1545 = ~n1327_1 & pksi_56_ & ~pstart_0_ & pencrypt_0_; + assign n1546 = ~n1328 & n_n2305 & ~pstart_0_ & ~pencrypt_0_; + assign n1547_1 = n1328 & pksi_60_ & ~pstart_0_ & ~pencrypt_0_; + assign n1548 = ~n1327_1 & pksi_64_ & ~pstart_0_ & pencrypt_0_; + assign n1549 = ~n1328 & pksi_77_ & ~pstart_0_ & ~pencrypt_0_; + assign n1550 = n1328 & pksi_81_ & ~pstart_0_ & ~pencrypt_0_; + assign n1551_1 = ~n1327_1 & n_n2288 & ~pstart_0_ & pencrypt_0_; + assign n1552 = ~n1328 & n_n2280 & ~pstart_0_ & ~pencrypt_0_; + assign n1553 = n1328 & pksi_73_ & ~pstart_0_ & ~pencrypt_0_; + assign n1554 = ~n1327_1 & pksi_93_ & ~pstart_0_ & pencrypt_0_; + assign n1555_1 = ~n1328 & pksi_22_ & ~pstart_0_ & ~pencrypt_0_; + assign n1556 = n1328 & pksi_0_ & ~pstart_0_ & ~pencrypt_0_; + assign n1557 = ~n1327_1 & pksi_1_ & ~pstart_0_ & pencrypt_0_; + assign n1558 = ~n1328 & pksi_47_ & ~pstart_0_ & ~pencrypt_0_; + assign n1559_1 = n1328 & pksi_30_ & ~pstart_0_ & ~pencrypt_0_; + assign n1560 = ~n1327_1 & pksi_33_ & ~pstart_0_ & pencrypt_0_; + assign n1561 = ~n1328 & pksi_26_ & ~pstart_0_ & ~pencrypt_0_; + assign n1562 = n1328 & pksi_38_ & ~pstart_0_ & ~pencrypt_0_; + assign n1563_1 = ~n1327_1 & pksi_32_ & ~pstart_0_ & pencrypt_0_; + assign n1564 = ~n1328 & pksi_45_ & ~pstart_0_ & ~pencrypt_0_; + assign n1565 = n1328 & pksi_34_ & ~pstart_0_ & ~pencrypt_0_; + assign n1566 = ~n1327_1 & pksi_27_ & ~pstart_0_ & pencrypt_0_; + assign n1567 = ~n1328 & pksi_52_ & ~pstart_0_ & ~pencrypt_0_; + assign n1568_1 = n1328 & pksi_71_ & ~pstart_0_ & ~pencrypt_0_; + assign n1569 = ~n1327_1 & pksi_53_ & ~pstart_0_ & pencrypt_0_; + assign n1570 = ~n1328 & n_n10 & ~pstart_0_ & ~pencrypt_0_; + assign n1571 = n1328 & pksi_92_ & ~pstart_0_ & ~pencrypt_0_; + assign n1572_1 = ~n1327_1 & pksi_23_ & ~pstart_0_ & pencrypt_0_; + assign n1573 = ~n1328 & pksi_0_ & ~pstart_0_ & ~pencrypt_0_; + assign n1574 = n1327_1 & pksi_1_ & ~pstart_0_ & pencrypt_0_; + assign n1575 = n1328 & pksi_8_ & ~pstart_0_ & ~pencrypt_0_; + assign n1576_1 = ~n1328 & pksi_28_ & ~pstart_0_ & ~pencrypt_0_; + assign n1577 = n1328 & pksi_47_ & ~pstart_0_ & ~pencrypt_0_; + assign n1578 = ~n1327_1 & pksi_29_ & ~pstart_0_ & pencrypt_0_; + assign n1579 = ~n1328 & pksi_38_ & ~pstart_0_ & ~pencrypt_0_; + assign n1580_1 = n1328 & pksi_46_ & ~pstart_0_ & ~pencrypt_0_; + assign n1581 = ~n1327_1 & pksi_42_ & ~pstart_0_ & pencrypt_0_; + assign n1582 = ~n1328 & pksi_37_ & ~pstart_0_ & ~pencrypt_0_; + assign n1583 = n1328 & pksi_45_ & ~pstart_0_ & ~pencrypt_0_; + assign n1584_1 = ~n1327_1 & pksi_36_ & ~pstart_0_ & pencrypt_0_; + assign n1585 = ~n1328 & pksi_71_ & ~pstart_0_ & ~pencrypt_0_; + assign n1586 = n1328 & pksi_54_ & ~pstart_0_ & ~pencrypt_0_; + assign n1587 = ~n1327_1 & pksi_57_ & ~pstart_0_ & pencrypt_0_; + assign n1588 = ~n1328 & pksi_8_ & ~pstart_0_ & ~pencrypt_0_; + assign n1589_1 = n1328 & pksi_18_ & ~pstart_0_ & ~pencrypt_0_; + assign n1590 = ~n1327_1 & pksi_13_ & ~pstart_0_ & pencrypt_0_; + assign n1591 = ~n1328 & pksi_7_ & ~pstart_0_ & ~pencrypt_0_; + assign n1592 = n1328 & pksi_28_ & ~pstart_0_ & ~pencrypt_0_; + assign n1593_1 = ~n1327_1 & pksi_39_ & ~pstart_0_ & pencrypt_0_; + assign n1594 = ~n1328 & n_n2352 & ~pstart_0_ & ~pencrypt_0_; + assign n1595 = n1328 & pksi_35_ & ~pstart_0_ & ~pencrypt_0_; + assign n1596 = ~n1327_1 & pksi_46_ & ~pstart_0_ & pencrypt_0_; + assign n1597_1 = ~n1328 & n_n2337 & ~pstart_0_ & ~pencrypt_0_; + assign n1598 = n1328 & pksi_36_ & ~pstart_0_ & ~pencrypt_0_; + assign n1599 = ~n1327_1 & pksi_40_ & ~pstart_0_ & pencrypt_0_; + assign n1600 = ~n1328 & pksi_54_ & ~pstart_0_ & ~pencrypt_0_; + assign n1601_1 = n1328 & pksi_63_ & ~pstart_0_ & ~pencrypt_0_; + assign n1602 = ~n1327_1 & pksi_67_ & ~pstart_0_ & pencrypt_0_; + assign n1603 = ~n1328 & pksi_18_ & ~pstart_0_ & ~pencrypt_0_; + assign n1604 = n1328 & pksi_1_ & ~pstart_0_ & ~pencrypt_0_; + assign n1605_1 = ~n1327_1 & pksi_21_ & ~pstart_0_ & pencrypt_0_; + assign n1606 = ~n1328 & pksi_20_ & ~pstart_0_ & ~pencrypt_0_; + assign n1607 = n1328 & pksi_7_ & ~pstart_0_ & ~pencrypt_0_; + assign n1608 = ~n1327_1 & pksi_30_ & ~pstart_0_ & pencrypt_0_; + assign n1609_1 = ~n1328 & pksi_35_ & ~pstart_0_ & ~pencrypt_0_; + assign n1610 = n1328 & pksi_26_ & ~pstart_0_ & ~pencrypt_0_; + assign n1611 = ~n1327_1 & pksi_24_ & ~pstart_0_ & pencrypt_0_; + assign n1612 = n1328 & n_n2337 & ~pstart_0_ & ~pencrypt_0_; + assign n1613_1 = ~n1328 & pksi_34_ & ~pstart_0_ & ~pencrypt_0_; + assign n1614 = n1327_1 & pksi_27_ & ~pstart_0_ & pencrypt_0_; + assign n1615 = ~n1328 & pksi_63_ & ~pstart_0_ & ~pencrypt_0_; + assign n1616 = n1328 & pksi_53_ & ~pstart_0_ & ~pencrypt_0_; + assign n1617 = ~n1327_1 & pksi_65_ & ~pstart_0_ & pencrypt_0_; + assign n1618_1 = ~n1328 & pksi_98_ & ~pstart_0_ & ~pencrypt_0_; + assign n1619 = n1327_1 & pksi_112_ & ~pstart_0_ & pencrypt_0_; + assign n1620 = n1328 & pksi_119_ & ~pstart_0_ & ~pencrypt_0_; + assign n1621 = ~n1328 & pksi_126_ & ~pstart_0_ & ~pencrypt_0_; + assign n1622_1 = n1328 & pksi_122_ & ~pstart_0_ & ~pencrypt_0_; + assign n1623 = ~n1327_1 & pksi_136_ & ~pstart_0_ & pencrypt_0_; + assign n1624 = ~n1328 & pksi_134_ & ~pstart_0_ & ~pencrypt_0_; + assign n1625 = n1327_1 & n_n2476 & ~pstart_0_ & pencrypt_0_; + assign n1626_1 = n1328 & pksi_127_ & ~pstart_0_ & ~pencrypt_0_; + assign n1627 = ~n1328 & pksi_131_ & ~pstart_0_ & ~pencrypt_0_; + assign n1628 = n1328 & pksi_133_ & ~pstart_0_ & ~pencrypt_0_; + assign n1629 = ~n1327_1 & pksi_121_ & ~pstart_0_ & pencrypt_0_; + assign n1630_1 = ~n1328 & pksi_166_ & ~pstart_0_ & ~pencrypt_0_; + assign n1631 = n1328 & pksi_150_ & ~pstart_0_ & ~pencrypt_0_; + assign n1632 = ~n1327_1 & pksi_154_ & ~pstart_0_ & pencrypt_0_; + assign n1633 = ~n1328 & n_n2448 & ~pstart_0_ & ~pencrypt_0_; + assign n1634 = n1328 & pksi_158_ & ~pstart_0_ & ~pencrypt_0_; + assign n1635_1 = ~n1327_1 & pksi_163_ & ~pstart_0_ & pencrypt_0_; + assign n1636 = ~n1328 & pksi_148_ & ~pstart_0_ & ~pencrypt_0_; + assign n1637 = n1328 & pksi_155_ & ~pstart_0_ & ~pencrypt_0_; + assign n1638 = ~n1327_1 & pksi_152_ & ~pstart_0_ & pencrypt_0_; + assign n1639_1 = ~n1328 & pksi_159_ & ~pstart_0_ & ~pencrypt_0_; + assign n1640 = n1328 & pksi_190_ & ~pstart_0_ & ~pencrypt_0_; + assign n1641 = ~n1327_1 & n_n121 & ~pstart_0_ & pencrypt_0_; + assign n1642 = ~n1328 & pksi_171_ & ~pstart_0_ & ~pencrypt_0_; + assign n1643_1 = n1328 & n_n2416 & ~pstart_0_ & ~pencrypt_0_; + assign n1644 = ~n1327_1 & n_n2412 & ~pstart_0_ & pencrypt_0_; + assign n1645 = ~n1328 & n_n2272 & ~pstart_0_ & ~pencrypt_0_; + assign n1646 = n1328 & pksi_84_ & ~pstart_0_ & ~pencrypt_0_; + assign n1647_1 = ~n1327_1 & n_n10 & ~pstart_0_ & pencrypt_0_; + assign n1648 = ~n1328 & pksi_96_ & ~pstart_0_ & ~pencrypt_0_; + assign n1649 = n1328 & pksi_115_ & ~pstart_0_ & ~pencrypt_0_; + assign n1650 = ~n1327_1 & pksi_105_ & ~pstart_0_ & pencrypt_0_; + assign n1651_1 = ~n1328 & pksi_142_ & ~pstart_0_ & ~pencrypt_0_; + assign n1652 = n1328 & pksi_126_ & ~pstart_0_ & ~pencrypt_0_; + assign n1653 = ~n1327_1 & pksi_130_ & ~pstart_0_ & pencrypt_0_; + assign n1654 = ~n1328 & pksi_127_ & ~pstart_0_ & ~pencrypt_0_; + assign n1655_1 = n1328 & pksi_120_ & ~pstart_0_ & ~pencrypt_0_; + assign n1656 = ~n1327_1 & pksi_132_ & ~pstart_0_ & pencrypt_0_; + assign n1657 = ~n1328 & pksi_124_ & ~pstart_0_ & ~pencrypt_0_; + assign n1658 = n1328 & pksi_131_ & ~pstart_0_ & ~pencrypt_0_; + assign n1659_1 = ~n1327_1 & pksi_128_ & ~pstart_0_ & pencrypt_0_; + assign n1660 = ~n1328 & pksi_150_ & ~pstart_0_ & ~pencrypt_0_; + assign n1661 = n1328 & pksi_146_ & ~pstart_0_ & ~pencrypt_0_; + assign n1662 = ~n1327_1 & pksi_160_ & ~pstart_0_ & pencrypt_0_; + assign n1663_1 = ~n1328 & pksi_147_ & ~pstart_0_ & ~pencrypt_0_; + assign n1664 = n1328 & n_n2448 & ~pstart_0_ & ~pencrypt_0_; + assign n1665 = ~n1327_1 & pksi_144_ & ~pstart_0_ & pencrypt_0_; + assign n1666 = ~n1328 & pksi_155_ & ~pstart_0_ & ~pencrypt_0_; + assign n1667_1 = n1328 & pksi_157_ & ~pstart_0_ & ~pencrypt_0_; + assign n1668 = ~n1327_1 & pksi_145_ & ~pstart_0_ & pencrypt_0_; + assign n1669 = ~n1328 & pksi_149_ & ~pstart_0_ & ~pencrypt_0_; + assign n1670 = n1328 & pksi_159_ & ~pstart_0_ & ~pencrypt_0_; + assign n1671_1 = ~n1327_1 & pksi_170_ & ~pstart_0_ & pencrypt_0_; + assign n1672 = ~n1328 & n_n2416 & ~pstart_0_ & ~pencrypt_0_; + assign n1673 = n1328 & pksi_182_ & ~pstart_0_ & ~pencrypt_0_; + assign n1674 = ~n1327_1 & n_n2410 & ~pstart_0_ & pencrypt_0_; + assign n1675_1 = ~n1328 & pksi_84_ & ~pstart_0_ & ~pencrypt_0_; + assign n1676 = n1328 & pksi_75_ & ~pstart_0_ & ~pencrypt_0_; + assign n1677 = ~n1327_1 & pksi_92_ & ~pstart_0_ & pencrypt_0_; + assign n1678 = ~n1328 & pksi_106_ & ~pstart_0_ & ~pencrypt_0_; + assign n1679_1 = n1328 & pksi_112_ & ~pstart_0_ & ~pencrypt_0_; + assign n1680 = ~n1327_1 & pksi_99_ & ~pstart_0_ & pencrypt_0_; + assign n1681 = ~n1328 & pksi_115_ & ~pstart_0_ & ~pencrypt_0_; + assign n1682 = n1328 & n_n2507 & ~pstart_0_ & ~pencrypt_0_; + assign n1683_1 = ~n1327_1 & pksi_114_ & ~pstart_0_ & pencrypt_0_; + assign n1684 = ~n1328 & n_n168 & ~pstart_0_ & ~pencrypt_0_; + assign n1685 = n1328 & pksi_130_ & ~pstart_0_ & ~pencrypt_0_; + assign n1686 = ~n1327_1 & pksi_141_ & ~pstart_0_ & pencrypt_0_; + assign n1687_1 = ~n1328 & pksi_120_ & ~pstart_0_ & ~pencrypt_0_; + assign n1688 = n1328 & n_n2476 & ~pstart_0_ & ~pencrypt_0_; + assign n1689 = ~n1327_1 & pksi_129_ & ~pstart_0_ & pencrypt_0_; + assign n1690 = ~n1328 & pksi_138_ & ~pstart_0_ & ~pencrypt_0_; + assign n1691_1 = n1328 & pksi_124_ & ~pstart_0_ & ~pencrypt_0_; + assign n1692 = ~n1327_1 & pksi_140_ & ~pstart_0_ & pencrypt_0_; + assign n1693 = ~n1328 & pksi_125_ & ~pstart_0_ & ~pencrypt_0_; + assign n1694 = n1328 & pksi_135_ & ~pstart_0_ & ~pencrypt_0_; + assign n1695 = ~n1327_1 & pksi_146_ & ~pstart_0_ & pencrypt_0_; + assign n1696_1 = ~n1328 & pksi_151_ & ~pstart_0_ & ~pencrypt_0_; + assign n1697 = n1328 & pksi_144_ & ~pstart_0_ & ~pencrypt_0_; + assign n1698 = ~n1327_1 & pksi_156_ & ~pstart_0_ & pencrypt_0_; + assign n1699 = ~n1328 & pksi_157_ & ~pstart_0_ & ~pencrypt_0_; + assign n1700 = n1328 & pksi_164_ & ~pstart_0_ & ~pencrypt_0_; + assign n1701_1 = ~n1327_1 & pksi_161_ & ~pstart_0_ & pencrypt_0_; + assign n1702 = ~n1328 & pksi_179_ & ~pstart_0_ & ~pencrypt_0_; + assign n1703 = n1328 & n_n109 & ~pstart_0_ & ~pencrypt_0_; + assign n1704 = ~n1327_1 & pksi_169_ & ~pstart_0_ & pencrypt_0_; + assign n1705 = ~n1328 & pksi_4_ & ~pstart_0_ & ~pencrypt_0_; + assign n1706_1 = n1328 & pksi_23_ & ~pstart_0_ & ~pencrypt_0_; + assign n1707 = ~n1327_1 & pksi_5_ & ~pstart_0_ & pencrypt_0_; + assign n1708 = n1328 & n_n2268 & ~pstart_0_ & ~pencrypt_0_; + assign n1709 = ~n1328 & pksi_75_ & ~pstart_0_ & ~pencrypt_0_; + assign n1710_1 = ~n1327_1 & pksi_79_ & ~pstart_0_ & pencrypt_0_; + assign n1711 = ~n1328 & pksi_119_ & ~pstart_0_ & ~pencrypt_0_; + assign n1712 = n1328 & pksi_106_ & ~pstart_0_ & ~pencrypt_0_; + assign n1713 = ~n1327_1 & pksi_117_ & ~pstart_0_ & pencrypt_0_; + assign n1714_1 = ~n1328 & n_n2507 & ~pstart_0_ & ~pencrypt_0_; + assign n1715 = n1328 & pksi_108_ & ~pstart_0_ & ~pencrypt_0_; + assign n1716 = ~n1327_1 & pksi_100_ & ~pstart_0_ & pencrypt_0_; + assign n1717 = ~n1328 & pksi_122_ & ~pstart_0_ & ~pencrypt_0_; + assign n1718_1 = ~n1327_1 & n_n2485 & ~pstart_0_ & pencrypt_0_; + assign n1719 = n1328 & n_n168 & ~pstart_0_ & ~pencrypt_0_; + assign n1720 = n1328 & n_n2474 & ~pstart_0_ & ~pencrypt_0_; + assign n1721 = ~n1328 & n_n2476 & ~pstart_0_ & ~pencrypt_0_; + assign n1722_1 = ~n1327_1 & pksi_138_ & ~pstart_0_ & pencrypt_0_; + assign n1723 = ~n1328 & pksi_129_ & ~pstart_0_ & ~pencrypt_0_; + assign n1724 = n1328 & pksi_138_ & ~pstart_0_ & ~pencrypt_0_; + assign n1725 = ~n1327_1 & pksi_133_ & ~pstart_0_ & pencrypt_0_; + assign n1726_1 = ~n1328 & pksi_135_ & ~pstart_0_ & ~pencrypt_0_; + assign n1727 = n1328 & pksi_166_ & ~pstart_0_ & ~pencrypt_0_; + assign n1728 = ~n1327_1 & pksi_167_ & ~pstart_0_ & pencrypt_0_; + assign n1729 = ~n1328 & pksi_158_ & ~pstart_0_ & ~pencrypt_0_; + assign n1730_1 = n1328 & pksi_151_ & ~pstart_0_ & ~pencrypt_0_; + assign n1731 = ~n1327_1 & pksi_153_ & ~pstart_0_ & pencrypt_0_; + assign n1732 = ~n1328 & pksi_164_ & ~pstart_0_ & ~pencrypt_0_; + assign n1733 = n1327_1 & pksi_161_ & ~pstart_0_ & pencrypt_0_; + assign n1734 = n1328 & pksi_152_ & ~pstart_0_ & ~pencrypt_0_; + assign n1735_1 = ~n1328 & pksi_172_ & ~pstart_0_ & ~pencrypt_0_; + assign n1736 = n1328 & pksi_179_ & ~pstart_0_ & ~pencrypt_0_; + assign n1737 = ~n1327_1 & pksi_176_ & ~pstart_0_ & pencrypt_0_; + assign n1738 = ~n1328 & pksi_23_ & ~pstart_0_ & ~pencrypt_0_; + assign n1739_1 = n1328 & pksi_6_ & ~pstart_0_ & ~pencrypt_0_; + assign n1740 = ~n1327_1 & pksi_9_ & ~pstart_0_ & pencrypt_0_; + assign n1741 = ~n1328 & n_n2268 & ~pstart_0_ & ~pencrypt_0_; + assign n1742 = n1328 & n_n10 & ~pstart_0_ & ~pencrypt_0_; + assign n1743_1 = ~n1327_1 & pksi_4_ & ~pstart_0_ & pencrypt_0_; + assign n1744 = ~n1328 & n_n2495 & ~pstart_0_ & ~pencrypt_0_; + assign n1745 = n1328 & pksi_101_ & ~pstart_0_ & ~pencrypt_0_; + assign n1746 = ~n1327_1 & pksi_126_ & ~pstart_0_ & pencrypt_0_; + assign n1747_1 = ~n1328 & n_n2485 & ~pstart_0_ & ~pencrypt_0_; + assign n1748 = n1328 & pksi_141_ & ~pstart_0_ & ~pencrypt_0_; + assign n1749 = ~n1327_1 & pksi_134_ & ~pstart_0_ & pencrypt_0_; + assign n1750 = ~n1328 & pksi_121_ & ~pstart_0_ & ~pencrypt_0_; + assign n1751_1 = n1328 & pksi_137_ & ~pstart_0_ & ~pencrypt_0_; + assign n1752 = ~n1327_1 & pksi_135_ & ~pstart_0_ & pencrypt_0_; + assign n1753 = ~n1328 & pksi_154_ & ~pstart_0_ & ~pencrypt_0_; + assign n1754 = n1328 & pksi_160_ & ~pstart_0_ & ~pencrypt_0_; + assign n1755_1 = ~n1327_1 & pksi_147_ & ~pstart_0_ & pencrypt_0_; + assign n1756 = ~n1328 & pksi_163_ & ~pstart_0_ & ~pencrypt_0_; + assign n1757 = n1328 & pksi_153_ & ~pstart_0_ & ~pencrypt_0_; + assign n1758 = ~n1327_1 & pksi_162_ & ~pstart_0_ & pencrypt_0_; + assign n1759_1 = ~n1328 & pksi_152_ & ~pstart_0_ & ~pencrypt_0_; + assign n1760 = n1328 & pksi_145_ & ~pstart_0_ & ~pencrypt_0_; + assign n1761 = ~n1327_1 & pksi_149_ & ~pstart_0_ & pencrypt_0_; + assign n1762 = ~n1328 & n_n2277 & ~pstart_0_ & ~pencrypt_0_; + assign n1763_1 = ~n1327_1 & n_n2272 & ~pstart_0_ & pencrypt_0_; + assign n1764 = n1328 & pksi_85_ & ~pstart_0_ & ~pencrypt_0_; + assign n1765 = ~n1328 & pksi_113_ & ~pstart_0_ & ~pencrypt_0_; + assign n1766 = n1328 & n_n2495 & ~pstart_0_ & ~pencrypt_0_; + assign n1767_1 = ~n1327_1 & pksi_142_ & ~pstart_0_ & pencrypt_0_; + assign n1768 = ~n1328 & pksi_141_ & ~pstart_0_ & ~pencrypt_0_; + assign n1769 = n1328 & pksi_123_ & ~pstart_0_ & ~pencrypt_0_; + assign n1770 = ~n1327_1 & pksi_127_ & ~pstart_0_ & pencrypt_0_; + assign n1771_1 = ~n1328 & pksi_128_ & ~pstart_0_ & ~pencrypt_0_; + assign n1772 = n1328 & pksi_121_ & ~pstart_0_ & ~pencrypt_0_; + assign n1773 = ~n1327_1 & pksi_125_ & ~pstart_0_ & pencrypt_0_; + assign n1774 = n1328 & n_n2452 & ~pstart_0_ & ~pencrypt_0_; + assign n1775 = ~n1328 & pksi_160_ & ~pstart_0_ & ~pencrypt_0_; + assign n1776_1 = ~n1327_1 & n_n2448 & ~pstart_0_ & pencrypt_0_; + assign n1777 = ~n1328 & pksi_144_ & ~pstart_0_ & ~pencrypt_0_; + assign n1778 = ~n1327_1 & n_n2440 & ~pstart_0_ & pencrypt_0_; + assign n1779 = n1328 & pksi_163_ & ~pstart_0_ & ~pencrypt_0_; + assign n1780 = ~n1328 & pksi_145_ & ~pstart_0_ & ~pencrypt_0_; + assign n1781_1 = n1328 & pksi_161_ & ~pstart_0_ & ~pencrypt_0_; + assign n1782 = ~n1327_1 & pksi_159_ & ~pstart_0_ & pencrypt_0_; + assign n1783 = ~n1328 & pksi_85_ & ~pstart_0_ & ~pencrypt_0_; + assign n1784 = n1328 & pksi_93_ & ~pstart_0_ & ~pencrypt_0_; + assign n1785_1 = ~n1327_1 & pksi_84_ & ~pstart_0_ & pencrypt_0_; + assign n1786 = ~n1328 & pksi_111_ & ~pstart_0_ & ~pencrypt_0_; + assign n1787 = n1328 & pksi_142_ & ~pstart_0_ & ~pencrypt_0_; + assign n1788 = ~n1327_1 & n_n168 & ~pstart_0_ & pencrypt_0_; + assign n1789 = ~n1328 & pksi_123_ & ~pstart_0_ & ~pencrypt_0_; + assign n1790 = n1328 & n_n2481 & ~pstart_0_ & ~pencrypt_0_; + assign n1791 = ~n1327_1 & pksi_120_ & ~pstart_0_ & pencrypt_0_; + assign n1792 = ~n1328 & pksi_140_ & ~pstart_0_ & ~pencrypt_0_; + assign n1793 = n1327_1 & pksi_137_ & ~pstart_0_ & pencrypt_0_; + assign n1794 = n1328 & pksi_128_ & ~pstart_0_ & ~pencrypt_0_; + assign n1795 = ~n1328 & pksi_146_ & ~pstart_0_ & ~pencrypt_0_; + assign n1796 = n1327_1 & pksi_160_ & ~pstart_0_ & pencrypt_0_; + assign n1797 = n1328 & pksi_167_ & ~pstart_0_ & ~pencrypt_0_; + assign n1798 = ~n1328 & pksi_156_ & ~pstart_0_ & ~pencrypt_0_; + assign n1799 = n1328 & n_n2440 & ~pstart_0_ & ~pencrypt_0_; + assign n1800 = ~n1327_1 & pksi_155_ & ~pstart_0_ & pencrypt_0_; + assign n1801 = ~n1328 & pksi_161_ & ~pstart_0_ & ~pencrypt_0_; + assign n1802 = n1328 & n_n2430 & ~pstart_0_ & ~pencrypt_0_; + assign n1803 = ~n1327_1 & pksi_190_ & ~pstart_0_ & pencrypt_0_; + assign n1804 = ~n1328 & pksi_93_ & ~pstart_0_ & ~pencrypt_0_; + assign n1805 = n1328 & pksi_82_ & ~pstart_0_ & ~pencrypt_0_; + assign n1806 = ~n1327_1 & pksi_75_ & ~pstart_0_ & pencrypt_0_; + assign n1807 = ~n1328 & pksi_101_ & ~pstart_0_ & ~pencrypt_0_; + assign n1808 = n1328 & pksi_111_ & ~pstart_0_ & ~pencrypt_0_; + assign n1809 = ~n1327_1 & pksi_122_ & ~pstart_0_ & pencrypt_0_; + assign n1810 = ~n1328 & n_n2481 & ~pstart_0_ & ~pencrypt_0_; + assign n1811 = n1327_1 & pksi_120_ & ~pstart_0_ & pencrypt_0_; + assign n1812 = n1328 & pksi_134_ & ~pstart_0_ & ~pencrypt_0_; + assign n1813 = ~n1328 & pksi_133_ & ~pstart_0_ & ~pencrypt_0_; + assign n1814 = n1328 & pksi_140_ & ~pstart_0_ & ~pencrypt_0_; + assign n1815 = ~n1327_1 & pksi_137_ & ~pstart_0_ & pencrypt_0_; + assign n1816 = ~n1328 & pksi_167_ & ~pstart_0_ & ~pencrypt_0_; + assign n1817 = n1328 & pksi_154_ & ~pstart_0_ & ~pencrypt_0_; + assign n1818 = ~n1327_1 & pksi_165_ & ~pstart_0_ & pencrypt_0_; + assign n1819 = ~n1328 & pksi_153_ & ~pstart_0_ & ~pencrypt_0_; + assign n1820 = n1328 & pksi_156_ & ~pstart_0_ & ~pencrypt_0_; + assign n1821 = ~n1327_1 & pksi_148_ & ~pstart_0_ & pencrypt_0_; + assign n1822 = ~n1328 & n_n2430 & ~pstart_0_ & ~pencrypt_0_; + assign n1823 = n1328 & pksi_149_ & ~pstart_0_ & ~pencrypt_0_; + assign n1824 = ~n1327_1 & pksi_174_ & ~pstart_0_ & pencrypt_0_; + assign n1825 = ~n1328 & pksi_82_ & ~pstart_0_ & ~pencrypt_0_; + assign n1826 = n1327_1 & pksi_75_ & ~pstart_0_ & pencrypt_0_; + assign n1827 = n1328 & n_n2272 & ~pstart_0_ & ~pencrypt_0_; + assign n1828 = ~n1328 & pksi_102_ & ~pstart_0_ & ~pencrypt_0_; + assign n1829 = n1328 & pksi_98_ & ~pstart_0_ & ~pencrypt_0_; + assign n1830 = ~n1327_1 & pksi_112_ & ~pstart_0_ & pencrypt_0_; + assign n1831 = ~n1328 & pksi_110_ & ~pstart_0_ & ~pencrypt_0_; + assign n1832 = n1327_1 & pksi_115_ & ~pstart_0_ & pencrypt_0_; + assign n1833 = n1328 & pksi_103_ & ~pstart_0_ & ~pencrypt_0_; + assign n1834 = ~n1328 & pksi_107_ & ~pstart_0_ & ~pencrypt_0_; + assign n1835 = n1328 & pksi_109_ & ~pstart_0_ & ~pencrypt_0_; + assign n1836 = ~n1327_1 & pksi_97_ & ~pstart_0_ & pencrypt_0_; + assign n1837 = ~n1328 & pksi_189_ & ~pstart_0_ & ~pencrypt_0_; + assign n1838 = n1328 & pksi_171_ & ~pstart_0_ & ~pencrypt_0_; + assign n1839 = ~n1327_1 & pksi_175_ & ~pstart_0_ & pencrypt_0_; + assign n1840 = ~n1328 & pksi_177_ & ~pstart_0_ & ~pencrypt_0_; + assign n1841 = n1328 & pksi_186_ & ~pstart_0_ & ~pencrypt_0_; + assign n1842 = ~n1327_1 & n_n109 & ~pstart_0_ & pencrypt_0_; + assign n1843 = ~n1328 & n_n2396 & ~pstart_0_ & ~pencrypt_0_; + assign n1844 = n1328 & pksi_173_ & ~pstart_0_ & ~pencrypt_0_; + assign n1845 = ~n1327_1 & pksi_102_ & ~pstart_0_ & pencrypt_0_; + assign n1846 = ~n1328 & pksi_19_ & ~pstart_0_ & ~pencrypt_0_; + assign n1847 = n1328 & pksi_17_ & ~pstart_0_ & ~pencrypt_0_; + assign n1848 = ~n1327_1 & pksi_2_ & ~pstart_0_ & pencrypt_0_; + assign n1849 = ~n1328 & n_n2513 & ~pstart_0_ & ~pencrypt_0_; + assign n1850 = n1328 & pksi_110_ & ~pstart_0_ & ~pencrypt_0_; + assign n1851 = ~n1327_1 & pksi_115_ & ~pstart_0_ & pencrypt_0_; + assign n1852 = ~n1328 & pksi_109_ & ~pstart_0_ & ~pencrypt_0_; + assign n1853 = n1328 & pksi_116_ & ~pstart_0_ & ~pencrypt_0_; + assign n1854 = ~n1327_1 & pksi_113_ & ~pstart_0_ & pencrypt_0_; + assign n1855 = ~n1328 & n_n2420 & ~pstart_0_ & ~pencrypt_0_; + assign n1856 = n1328 & pksi_189_ & ~pstart_0_ & ~pencrypt_0_; + assign n1857 = ~n1327_1 & pksi_182_ & ~pstart_0_ & pencrypt_0_; + assign n1858 = ~n1328 & pksi_186_ & ~pstart_0_ & ~pencrypt_0_; + assign n1859 = n1328 & pksi_172_ & ~pstart_0_ & ~pencrypt_0_; + assign n1860 = ~n1327_1 & pksi_188_ & ~pstart_0_ & pencrypt_0_; + assign n1861 = ~n1328 & pksi_185_ & ~pstart_0_ & ~pencrypt_0_; + assign n1862 = n1328 & n_n2396 & ~pstart_0_ & ~pencrypt_0_; + assign n1863 = ~n1327_1 & pksi_118_ & ~pstart_0_ & pencrypt_0_; + assign n1864 = ~n1328 & pksi_17_ & ~pstart_0_ & ~pencrypt_0_; + assign n1865 = n1328 & n_n2384 & ~pstart_0_ & ~pencrypt_0_; + assign n1866 = ~n1327_1 & pksi_14_ & ~pstart_0_ & pencrypt_0_; + assign n1867 = ~n1328 & pksi_183_ & ~pstart_0_ & ~pencrypt_0_; + assign n1868 = n1328 & pksi_118_ & ~pstart_0_ & ~pencrypt_0_; + assign n1869 = ~n1327_1 & pksi_119_ & ~pstart_0_ & pencrypt_0_; + assign n1870 = ~n1328 & pksi_116_ & ~pstart_0_ & ~pencrypt_0_; + assign n1871 = ~n1327_1 & n_n2495 & ~pstart_0_ & pencrypt_0_; + assign n1872 = n1328 & pksi_104_ & ~pstart_0_ & ~pencrypt_0_; + assign n1873 = ~n1328 & pksi_97_ & ~pstart_0_ & ~pencrypt_0_; + assign n1874 = n1328 & pksi_113_ & ~pstart_0_ & ~pencrypt_0_; + assign n1875 = ~n1327_1 & pksi_111_ & ~pstart_0_ & pencrypt_0_; + assign n1876 = ~n1328 & pksi_130_ & ~pstart_0_ & ~pencrypt_0_; + assign n1877 = n1328 & pksi_136_ & ~pstart_0_ & ~pencrypt_0_; + assign n1878 = ~n1327_1 & pksi_123_ & ~pstart_0_ & pencrypt_0_; + assign n1879 = ~n1328 & pksi_184_ & ~pstart_0_ & ~pencrypt_0_; + assign n1880 = ~n1327_1 & n_n2416 & ~pstart_0_ & pencrypt_0_; + assign n1881 = n1328 & n_n2420 & ~pstart_0_ & ~pencrypt_0_; + assign n1882 = ~n1328 & n_n2408 & ~pstart_0_ & ~pencrypt_0_; + assign n1883 = n1328 & pksi_180_ & ~pstart_0_ & ~pencrypt_0_; + assign n1884 = ~n1327_1 & pksi_172_ & ~pstart_0_ & pencrypt_0_; + assign n1885 = ~n1328 & pksi_79_ & ~pstart_0_ & ~pencrypt_0_; + assign n1886 = n1328 & pksi_4_ & ~pstart_0_ & ~pencrypt_0_; + assign n1887 = ~n1327_1 & pksi_15_ & ~pstart_0_ & pencrypt_0_; + assign n1888 = ~n1328 & n_n2384 & ~pstart_0_ & ~pencrypt_0_; + assign n1889 = n1328 & pksi_11_ & ~pstart_0_ & ~pencrypt_0_; + assign n1890 = ~n1327_1 & pksi_22_ & ~pstart_0_ & pencrypt_0_; + assign n1891 = ~n1328 & pksi_118_ & ~pstart_0_ & ~pencrypt_0_; + assign n1892 = n1328 & pksi_102_ & ~pstart_0_ & ~pencrypt_0_; + assign n1893 = ~n1327_1 & pksi_106_ & ~pstart_0_ & pencrypt_0_; + assign n1894 = ~n1328 & pksi_103_ & ~pstart_0_ & ~pencrypt_0_; + assign n1895 = n1328 & pksi_96_ & ~pstart_0_ & ~pencrypt_0_; + assign n1896 = ~n1327_1 & pksi_108_ & ~pstart_0_ & pencrypt_0_; + assign n1897 = ~n1328 & pksi_104_ & ~pstart_0_ & ~pencrypt_0_; + assign n1898 = n1328 & pksi_97_ & ~pstart_0_ & ~pencrypt_0_; + assign n1899 = ~n1327_1 & pksi_101_ & ~pstart_0_ & pencrypt_0_; + assign n1900 = ~n1328 & pksi_136_ & ~pstart_0_ & ~pencrypt_0_; + assign n1901 = n1327_1 & pksi_123_ & ~pstart_0_ & pencrypt_0_; + assign n1902 = n1328 & n_n2485 & ~pstart_0_ & ~pencrypt_0_; + assign n1903 = ~n1328 & pksi_178_ & ~pstart_0_ & ~pencrypt_0_; + assign n1904 = n1328 & pksi_184_ & ~pstart_0_ & ~pencrypt_0_; + assign n1905 = ~n1327_1 & pksi_171_ & ~pstart_0_ & pencrypt_0_; + assign n1906 = ~n1328 & pksi_180_ & ~pstart_0_ & ~pencrypt_0_; + assign n1907 = n1328 & pksi_177_ & ~pstart_0_ & ~pencrypt_0_; + assign n1908 = ~n1327_1 & pksi_179_ & ~pstart_0_ & pencrypt_0_; + assign n1909 = ~n1328 & pksi_92_ & ~pstart_0_ & ~pencrypt_0_; + assign n1910 = n1328 & pksi_79_ & ~pstart_0_ & ~pencrypt_0_; + assign n1911 = ~n1327_1 & pksi_6_ & ~pstart_0_ & pencrypt_0_; + assign n1912 = ~n1328 & pksi_11_ & ~pstart_0_ & ~pencrypt_0_; + assign n1913 = n1328 & pksi_2_ & ~pstart_0_ & ~pencrypt_0_; + assign n1914 = ~n1327_1 & pksi_0_ & ~pstart_0_ & pencrypt_0_; + assign n1915 = n1328 & n_n2277 & ~pstart_0_ & ~pencrypt_0_; + assign n1916 = ~n1328 & pksi_73_ & ~pstart_0_ & ~pencrypt_0_; + assign n1917 = ~n1327_1 & pksi_82_ & ~pstart_0_ & pencrypt_0_; + assign n1918 = ~n1328 & n_n2517 & ~pstart_0_ & ~pencrypt_0_; + assign n1919 = n1328 & pksi_117_ & ~pstart_0_ & ~pencrypt_0_; + assign n1920 = ~n1327_1 & pksi_110_ & ~pstart_0_ & pencrypt_0_; + assign n1921 = ~n1328 & pksi_108_ & ~pstart_0_ & ~pencrypt_0_; + assign n1922 = n1328 & pksi_105_ & ~pstart_0_ & ~pencrypt_0_; + assign n1923 = ~n1327_1 & pksi_107_ & ~pstart_0_ & pencrypt_0_; + assign n1924 = ~n1328 & pksi_132_ & ~pstart_0_ & ~pencrypt_0_; + assign n1925 = n1328 & pksi_129_ & ~pstart_0_ & ~pencrypt_0_; + assign n1926 = ~n1327_1 & pksi_131_ & ~pstart_0_ & pencrypt_0_; + assign n1927 = n1328 & n_n2462 & ~pstart_0_ & ~pencrypt_0_; + assign n1928 = ~n1328 & pksi_137_ & ~pstart_0_ & ~pencrypt_0_; + assign n1929 = ~n1327_1 & pksi_166_ & ~pstart_0_ & pencrypt_0_; + assign n1930 = ~n1328 & n_n121 & ~pstart_0_ & ~pencrypt_0_; + assign n1931 = n1328 & pksi_178_ & ~pstart_0_ & ~pencrypt_0_; + assign n1932 = ~n1327_1 & pksi_189_ & ~pstart_0_ & pencrypt_0_; + assign n1933 = ~n1328 & n_n2412 & ~pstart_0_ & ~pencrypt_0_; + assign n1934 = n1328 & n_n2410 & ~pstart_0_ & ~pencrypt_0_; + assign n1935 = ~n1327_1 & pksi_177_ & ~pstart_0_ & pencrypt_0_; + assign n1936 = ~n1328 & pksi_188_ & ~pstart_0_ & ~pencrypt_0_; + assign n1937 = n1328 & pksi_176_ & ~pstart_0_ & ~pencrypt_0_; + assign n1938 = ~n1327_1 & n_n2396 & ~pstart_0_ & pencrypt_0_; + assign n1939 = ~n1328 & pksi_6_ & ~pstart_0_ & ~pencrypt_0_; + assign n1940 = n1328 & pksi_15_ & ~pstart_0_ & ~pencrypt_0_; + assign n1941 = ~n1327_1 & pksi_19_ & ~pstart_0_ & pencrypt_0_; + assign n1942 = ~n1328 & pksi_173_ & ~pstart_0_ & ~pencrypt_0_; + assign n1943 = n1328 & pksi_183_ & ~pstart_0_ & ~pencrypt_0_; + assign n1944 = ~n1327_1 & pksi_98_ & ~pstart_0_ & pencrypt_0_; + assign n1945 = ~n1328 & pksi_112_ & ~pstart_0_ & ~pencrypt_0_; + assign n1946 = n1328 & n_n2517 & ~pstart_0_ & ~pencrypt_0_; + assign n1947 = ~n1327_1 & n_n2513 & ~pstart_0_ & pencrypt_0_; + assign n1948 = ~n1328 & pksi_105_ & ~pstart_0_ & ~pencrypt_0_; + assign n1949 = n1328 & pksi_114_ & ~pstart_0_ & ~pencrypt_0_; + assign n1950 = ~n1327_1 & pksi_109_ & ~pstart_0_ & pencrypt_0_; + assign n1951 = ~n1328 & n_n2474 & ~pstart_0_ & ~pencrypt_0_; + assign n1952 = n1328 & pksi_132_ & ~pstart_0_ & ~pencrypt_0_; + assign n1953 = ~n1327_1 & pksi_124_ & ~pstart_0_ & pencrypt_0_; + assign n1954 = ~n1328 & n_n2462 & ~pstart_0_ & ~pencrypt_0_; + assign n1955 = n1328 & pksi_125_ & ~pstart_0_ & ~pencrypt_0_; + assign n1956 = ~n1327_1 & pksi_150_ & ~pstart_0_ & pencrypt_0_; + assign n1957 = ~n1328 & pksi_170_ & ~pstart_0_ & ~pencrypt_0_; + assign n1958 = ~n1327_1 & n_n2420 & ~pstart_0_ & pencrypt_0_; + assign n1959 = n1328 & n_n121 & ~pstart_0_ & ~pencrypt_0_; + assign n1960 = ~n1328 & n_n2410 & ~pstart_0_ & ~pencrypt_0_; + assign n1961 = n1328 & n_n2408 & ~pstart_0_ & ~pencrypt_0_; + assign n1962 = ~n1327_1 & pksi_186_ & ~pstart_0_ & pencrypt_0_; + assign n1963 = ~n1328 & n_n109 & ~pstart_0_ & ~pencrypt_0_; + assign n1964 = n1328 & pksi_188_ & ~pstart_0_ & ~pencrypt_0_; + assign n1965 = ~n1327_1 & pksi_185_ & ~pstart_0_ & pencrypt_0_; + assign n1966 = ~n1328 & pksi_15_ & ~pstart_0_ & ~pencrypt_0_; + assign n1967 = n1328 & pksi_5_ & ~pstart_0_ & ~pencrypt_0_; + assign n1968 = ~n1327_1 & pksi_17_ & ~pstart_0_ & pencrypt_0_; + assign n1969 = ~n1328 & pksi_99_ & ~pstart_0_ & ~pencrypt_0_; + assign n1970 = n1328 & n_n2513 & ~pstart_0_ & ~pencrypt_0_; + assign n1971 = ~n1327_1 & pksi_96_ & ~pstart_0_ & pencrypt_0_; + assign n1972 = ~n1328 & pksi_114_ & ~pstart_0_ & ~pencrypt_0_; + assign n1973 = n1328 & pksi_100_ & ~pstart_0_ & ~pencrypt_0_; + assign n1974 = ~n1327_1 & pksi_116_ & ~pstart_0_ & pencrypt_0_; + assign n1975 = ~n1328 & pksi_165_ & ~pstart_0_ & ~pencrypt_0_; + assign n1976 = n1328 & pksi_147_ & ~pstart_0_ & ~pencrypt_0_; + assign n1977 = ~n1327_1 & pksi_151_ & ~pstart_0_ & pencrypt_0_; + assign n1978 = ~n1328 & n_n2440 & ~pstart_0_ & ~pencrypt_0_; + assign n1979 = n1328 & pksi_162_ & ~pstart_0_ & ~pencrypt_0_; + assign n1980 = ~n1327_1 & pksi_157_ & ~pstart_0_ & pencrypt_0_; + assign n1981 = ~n1328 & pksi_174_ & ~pstart_0_ & ~pencrypt_0_; + assign n1982 = n1328 & pksi_170_ & ~pstart_0_ & ~pencrypt_0_; + assign n1983 = ~n1327_1 & pksi_184_ & ~pstart_0_ & pencrypt_0_; + assign n1984 = ~n1328 & pksi_182_ & ~pstart_0_ & ~pencrypt_0_; + assign n1985 = ~n1327_1 & n_n2408 & ~pstart_0_ & pencrypt_0_; + assign n1986 = n1328 & pksi_175_ & ~pstart_0_ & ~pencrypt_0_; + assign n1987 = ~n1328 & pksi_169_ & ~pstart_0_ & ~pencrypt_0_; + assign n1988 = n1328 & pksi_185_ & ~pstart_0_ & ~pencrypt_0_; + assign n1989 = ~n1327_1 & pksi_183_ & ~pstart_0_ & pencrypt_0_; + assign n1990 = ~n1328 & pksi_5_ & ~pstart_0_ & ~pencrypt_0_; + assign n1991 = ~n1327_1 & n_n2384 & ~pstart_0_ & pencrypt_0_; + assign n1992 = n1328 & pksi_9_ & ~pstart_0_ & ~pencrypt_0_; + assign n1993 = ~n1328 & pksi_117_ & ~pstart_0_ & ~pencrypt_0_; + assign n1994 = n1328 & pksi_99_ & ~pstart_0_ & ~pencrypt_0_; + assign n1995 = ~n1327_1 & pksi_103_ & ~pstart_0_ & pencrypt_0_; + assign n1996 = ~n1328 & pksi_100_ & ~pstart_0_ & ~pencrypt_0_; + assign n1997 = n1328 & pksi_107_ & ~pstart_0_ & ~pencrypt_0_; + assign n1998 = ~n1327_1 & pksi_104_ & ~pstart_0_ & pencrypt_0_; + assign n1999 = ~n1328 & n_n2452 & ~pstart_0_ & ~pencrypt_0_; + assign n2000 = n1328 & pksi_165_ & ~pstart_0_ & ~pencrypt_0_; + assign n2001 = ~n1327_1 & pksi_158_ & ~pstart_0_ & pencrypt_0_; + assign n2002 = ~n1328 & pksi_162_ & ~pstart_0_ & ~pencrypt_0_; + assign n2003 = n1328 & pksi_148_ & ~pstart_0_ & ~pencrypt_0_; + assign n2004 = ~n1327_1 & pksi_164_ & ~pstart_0_ & pencrypt_0_; + assign n2005 = ~n1328 & pksi_190_ & ~pstart_0_ & ~pencrypt_0_; + assign n2006 = n1328 & pksi_174_ & ~pstart_0_ & ~pencrypt_0_; + assign n2007 = ~n1327_1 & pksi_178_ & ~pstart_0_ & pencrypt_0_; + assign n2008 = ~n1328 & pksi_175_ & ~pstart_0_ & ~pencrypt_0_; + assign n2009 = n1328 & n_n2412 & ~pstart_0_ & ~pencrypt_0_; + assign n2010 = ~n1327_1 & pksi_180_ & ~pstart_0_ & pencrypt_0_; + assign n2011 = ~n1328 & pksi_176_ & ~pstart_0_ & ~pencrypt_0_; + assign n2012 = n1328 & pksi_169_ & ~pstart_0_ & ~pencrypt_0_; + assign n2013 = ~n1327_1 & pksi_173_ & ~pstart_0_ & pencrypt_0_; + assign n2014 = ~n1328 & pksi_9_ & ~pstart_0_ & ~pencrypt_0_; + assign n2015 = n1328 & pksi_19_ & ~pstart_0_ & ~pencrypt_0_; + assign n2016 = ~n1327_1 & pksi_11_ & ~pstart_0_ & pencrypt_0_; + assign n2017 = pstart_0_ & (pencrypt_0_ ? pkey_57_ : pkey_0_); + assign n2018 = n2017 | (n_n2384 & n1327_1 & n1332_1); + assign n2019 = pstart_0_ & (pencrypt_0_ ? pkey_211_ : pkey_219_); + assign n2020 = n2019 | (n_n2396 & n1327_1 & n1332_1); + assign n2021 = pstart_0_ & (pencrypt_0_ ? pkey_205_ : pkey_213_); + assign n2022 = n2021 | (n_n2408 & n1327_1 & n1332_1); + assign n2023 = pstart_0_ & (pencrypt_0_ ? pkey_230_ : pkey_238_); + assign n2024 = n2023 | (n_n121 & n1327_1 & n1332_1); + assign n2025 = pstart_0_ & (pencrypt_0_ ? pkey_156_ : pkey_164_); + assign n2026 = n2025 | (pksi_157_ & n1327_1 & n1332_1); + assign n2027 = pstart_0_ & (pencrypt_0_ ? pkey_181_ : pkey_189_); + assign n2028 = n2027 | (n_n2448 & n1327_1 & n1332_1); + assign n2029 = pstart_0_ & (pencrypt_0_ ? pkey_20_ : pkey_28_); + assign n2030 = n2029 | (pksi_116_ & n1327_1 & n1332_1); + assign n2031 = pstart_0_ & (pencrypt_0_ ? pkey_45_ : pkey_53_); + assign n2032 = n2031 | (pksi_110_ & n1327_1 & n1332_1); + assign n2033 = pstart_0_ & (pencrypt_0_ ? pkey_0_ : pkey_8_); + assign n2034 = n2033 | (pksi_17_ & n1327_1 & n1332_1); + assign n2035 = pstart_0_ & (pencrypt_0_ ? pkey_203_ : pkey_211_); + assign n2036 = n2035 | (pksi_173_ & n1327_1 & n1332_1); + assign n2037 = pstart_0_ & (pencrypt_0_ ? pkey_213_ : pkey_221_); + assign n2038 = n2037 | (n_n2410 & n1327_1 & n1332_1); + assign n2039 = pstart_0_ & (pencrypt_0_ ? pkey_222_ : pkey_230_); + assign n2040 = n2039 | (pksi_178_ & n1327_1 & n1332_1); + assign n2041 = pstart_0_ & (pencrypt_0_ ? pkey_164_ : pkey_172_); + assign n2042 = n2041 | (pksi_155_ & n1327_1 & n1332_1); + assign n2043 = pstart_0_ & (pencrypt_0_ ? pkey_173_ : pkey_181_); + assign n2044 = n2043 | (pksi_158_ & n1327_1 & n1332_1); + assign n2045 = pstart_0_ & (pencrypt_0_ ? pkey_28_ : pkey_36_); + assign n2046 = n2045 | (pksi_109_ & n1327_1 & n1332_1); + assign n2047 = pstart_0_ & (pencrypt_0_ ? pkey_37_ : pkey_45_); + assign n2048 = n2047 | (pksi_103_ & n1327_1 & n1332_1); + assign n2049 = pstart_0_ & (pencrypt_0_ ? pkey_8_ : pkey_16_); + assign n2050 = n2049 | (pksi_19_ & n1327_1 & n1332_1); + assign n2051 = pstart_0_ & (pencrypt_0_ ? pkey_196_ : pkey_204_); + assign n2052 = n2051 | (pksi_169_ & n1327_1 & n1332_1); + assign n2053 = pstart_0_ & (pencrypt_0_ ? pkey_252_ : pkey_197_); + assign n2054 = n2053 | (pksi_177_ & n1327_1 & n1332_1); + assign n2055 = pstart_0_ & (pencrypt_0_ ? pkey_214_ : pkey_222_); + assign n2056 = n2055 | (pksi_184_ & n1327_1 & n1332_1); + assign n2057 = pstart_0_ & (pencrypt_0_ ? pkey_190_ : pkey_67_); + assign n2058 = n2057 | (pksi_166_ & n1327_1 & n1332_1); + assign n2059 = pstart_0_ & (pencrypt_0_ ? pkey_116_ : pkey_124_); + assign n2060 = n2059 | (pksi_138_ & n1327_1 & n1332_1); + assign n2061 = pstart_0_ & (pencrypt_0_ ? pkey_36_ : pkey_44_); + assign n2062 = n2061 | (pksi_107_ & n1327_1 & n1332_1); + assign n2063 = pstart_0_ & (pencrypt_0_ ? pkey_61_ : pkey_6_); + assign n2064 = n2063 | (pksi_99_ & n1327_1 & n1332_1); + assign n2065 = pstart_0_ & (pencrypt_0_ ? pkey_54_ : pkey_62_); + assign n2066 = n2065 | (pksi_102_ & n1327_1 & n1332_1); + assign n2067 = pstart_0_ & (pencrypt_0_ ? pkey_16_ : pkey_24_); + assign n2068 = n2067 | (pksi_9_ & n1327_1 & n1332_1); + assign n2069 = pstart_0_ & (pencrypt_0_ ? pkey_219_ : pkey_196_); + assign n2070 = n2069 | (pksi_185_ & n1327_1 & n1332_1); + assign n2071 = pstart_0_ & (pencrypt_0_ ? pkey_197_ : pkey_205_); + assign n2072 = n2071 | (pksi_180_ & n1327_1 & n1332_1); + assign n2073 = pstart_0_ & (pencrypt_0_ ? pkey_206_ : pkey_214_); + assign n2074 = n2073 | (n_n2420 & n1327_1 & n1332_1); + assign n2075 = pstart_0_ & (pencrypt_0_ ? pkey_67_ : pkey_75_); + assign n2076 = n2075 | (pksi_135_ & n1327_1 & n1332_1); + assign n2077 = pstart_0_ & (pencrypt_0_ ? pkey_44_ : pkey_116_); + assign n2078 = n2077 | (pksi_124_ & n1327_1 & n1332_1); + assign n2079 = pstart_0_ & (pencrypt_0_ ? pkey_44_ : pkey_52_); + assign n2080 = n2079 | (pksi_100_ & n1327_1 & n1332_1); + assign n2081 = pstart_0_ & (pencrypt_0_ ? pkey_53_ : pkey_61_); + assign n2082 = n2081 | (n_n2513 & n1327_1 & n1332_1); + assign n2083 = pstart_0_ & (pencrypt_0_ ? pkey_226_ : pkey_234_); + assign n2084 = n2083 | (pksi_93_ & n1327_1 & n1332_1); + assign n2085 = pstart_0_ & (pencrypt_0_ ? pkey_25_ : pkey_33_); + assign n2086 = n2085 | (pksi_22_ & n1327_1 & n1332_1); + assign n2087 = pstart_0_ & (pencrypt_0_ ? pkey_48_ : pkey_56_); + assign n2088 = n2087 | (pksi_23_ & n1327_1 & n1332_1); + assign n2089 = pstart_0_ & (pencrypt_0_ ? pkey_172_ : pkey_244_); + assign n2090 = n2089 | (pksi_172_ & n1327_1 & n1332_1); + assign n2091 = pstart_0_ & (pencrypt_0_ ? pkey_198_ : pkey_206_); + assign n2092 = n2091 | (pksi_189_ & n1327_1 & n1332_1); + assign n2093 = pstart_0_ & (pencrypt_0_ ? pkey_125_ : pkey_70_); + assign n2094 = n2093 | (n_n2481 & ~n1327_1 & n1332_1); + assign n2095 = pstart_0_ & (pencrypt_0_ ? pkey_19_ : pkey_27_); + assign n2096 = n2095 | (n_n2495 & n1327_1 & n1332_1); + assign n2097 = pstart_0_ & (pencrypt_0_ ? pkey_13_ : pkey_21_); + assign n2098 = n2097 | (n_n2507 & n1327_1 & n1332_1); + assign n2099 = pstart_0_ & (pencrypt_0_ ? pkey_38_ : pkey_46_); + assign n2100 = n2099 | (pksi_119_ & n1327_1 & n1332_1); + assign n2101 = pstart_0_ & (pencrypt_0_ ? pkey_33_ : pkey_41_); + assign n2102 = n2101 | (pksi_14_ & n1327_1 & n1332_1); + assign n2103 = pstart_0_ & (pencrypt_0_ ? pkey_40_ : pkey_48_); + assign n2104 = n2103 | (pksi_6_ & n1327_1 & n1332_1); + assign n2105 = pstart_0_ & (pencrypt_0_ ? pkey_244_ : pkey_252_); + assign n2106 = n2105 | (pksi_186_ & n1327_1 & n1332_1); + assign n2107 = pstart_0_ & (pencrypt_0_ ? pkey_253_ : pkey_198_); + assign n2108 = n2107 | (pksi_171_ & n1327_1 & n1332_1); + assign n2109 = pstart_0_ & (pencrypt_0_ ? pkey_70_ : pkey_78_); + assign n2110 = n2109 | (pksi_141_ & n1327_1 & n1332_1); + assign n2111 = pstart_0_ & (pencrypt_0_ ? pkey_11_ : pkey_19_); + assign n2112 = n2111 | (pksi_101_ & n1327_1 & n1332_1); + assign n2113 = pstart_0_ & (pencrypt_0_ ? pkey_27_ : pkey_4_); + assign n2114 = n2113 | (pksi_113_ & n1327_1 & n1332_1); + assign n2115 = pstart_0_ & (pencrypt_0_ ? pkey_46_ : pkey_54_); + assign n2116 = n2115 | (pksi_98_ & n1327_1 & n1332_1); + assign n2117 = pstart_0_ & (pencrypt_0_ ? pkey_41_ : pkey_49_); + assign n2118 = n2117 | (pksi_2_ & n1327_1 & n1332_1); + assign n2119 = pstart_0_ & (pencrypt_0_ ? pkey_195_ : pkey_203_); + assign n2120 = n2119 | (pksi_183_ & n1327_1 & n1332_1); + assign n2121 = pstart_0_ & (pencrypt_0_ ? pkey_220_ : pkey_228_); + assign n2122 = n2121 | (n_n109 & n1327_1 & n1332_1); + assign n2123 = pstart_0_ & (pencrypt_0_ ? pkey_245_ : pkey_253_); + assign n2124 = n2123 | (n_n2416 & n1327_1 & n1332_1); + assign n2125 = pstart_0_ & (pencrypt_0_ ? pkey_4_ : pkey_12_); + assign n2126 = n2125 | (pksi_97_ & n1327_1 & n1332_1); + assign n2127 = pstart_0_ & (pencrypt_0_ ? pkey_29_ : pkey_37_); + assign n2128 = n2127 | (pksi_96_ & n1327_1 & n1332_1); + assign n2129 = pstart_0_ & (pencrypt_0_ ? pkey_49_ : pkey_57_); + assign n2130 = n2129 | (pksi_11_ & n1327_1 & n1332_1); + assign n2131 = pstart_0_ & (pencrypt_0_ ? pkey_62_ : pkey_195_); + assign n2132 = n2131 | (pksi_118_ & n1327_1 & n1332_1); + assign n2133 = pstart_0_ & (pencrypt_0_ ? pkey_228_ : pkey_172_); + assign n2134 = n2133 | (pksi_179_ & n1327_1 & n1332_1); + assign n2135 = pstart_0_ & (pencrypt_0_ ? pkey_237_ : pkey_245_); + assign n2136 = n2135 | (pksi_182_ & n1327_1 & n1332_1); + assign n2137 = pstart_0_ & (pencrypt_0_ ? pkey_12_ : pkey_20_); + assign n2138 = n2137 | (pksi_104_ & n1327_1 & n1332_1); + assign n2139 = pstart_0_ & (pencrypt_0_ ? pkey_21_ : pkey_29_); + assign n2140 = n2139 | (n_n2507 & ~n1327_1 & n1332_1); + assign n2141 = pstart_0_ & (pencrypt_0_ ? pkey_30_ : pkey_38_); + assign n2142 = n2141 | (pksi_106_ & n1327_1 & n1332_1); + assign n2143 = pstart_0_ & (pencrypt_0_ ? pkey_194_ : pkey_202_); + assign n2144 = n2143 | (n_n2268 & ~n1327_1 & n1332_1); + assign n2145 = pstart_0_ & (pencrypt_0_ ? pkey_254_ : pkey_131_); + assign n2146 = n2145 | (pksi_190_ & n1327_1 & n1332_1); + assign n2147 = pstart_0_ & (pencrypt_0_ ? pkey_180_ : pkey_188_); + assign n2148 = n2147 | (pksi_162_ & n1327_1 & n1332_1); + assign n2149 = pstart_0_ & (pencrypt_0_ ? pkey_142_ : pkey_150_); + assign n2150 = n2149 | (n_n2452 & n1327_1 & n1332_1); + assign n2151 = pstart_0_ & (pencrypt_0_ ? pkey_68_ : pkey_76_); + assign n2152 = n2151 | (pksi_121_ & n1327_1 & n1332_1); + assign n2153 = pstart_0_ & (pencrypt_0_ ? pkey_93_ : pkey_101_); + assign n2154 = n2153 | (n_n2476 & ~n1327_1 & n1332_1); + assign n2155 = pstart_0_ & (pencrypt_0_ ? pkey_118_ : pkey_126_); + assign n2156 = n2155 | (pksi_126_ & n1327_1 & n1332_1); + assign n2157 = pstart_0_ & (pencrypt_0_ ? pkey_202_ : pkey_210_); + assign n2158 = n2157 | (pksi_84_ & n1327_1 & n1332_1); + assign n2159 = pstart_0_ & (pencrypt_0_ ? pkey_131_ : pkey_139_); + assign n2160 = n2159 | (pksi_159_ & n1327_1 & n1332_1); + assign n2161 = pstart_0_ & (pencrypt_0_ ? pkey_172_ : pkey_180_); + assign n2162 = n2161 | (pksi_148_ & n1327_1 & n1332_1); + assign n2163 = pstart_0_ & (pencrypt_0_ ? pkey_150_ : pkey_158_); + assign n2164 = n2163 | (n_n2452 & ~n1327_1 & n1332_1); + assign n2165 = pstart_0_ & (pencrypt_0_ ? pkey_91_ : pkey_68_); + assign n2166 = n2165 | (n_n2462 & ~n1327_1 & n1332_1); + assign n2167 = pstart_0_ & (pencrypt_0_ ? pkey_101_ : pkey_109_); + assign n2168 = n2167 | (pksi_127_ & n1327_1 & n1332_1); + assign n2169 = pstart_0_ & (pencrypt_0_ ? pkey_110_ : pkey_118_); + assign n2170 = n2169 | (pksi_122_ & n1327_1 & n1332_1); + assign n2171 = pstart_0_ & (pencrypt_0_ ? pkey_210_ : pkey_218_); + assign n2172 = n2171 | (n_n2272 & n1327_1 & n1332_1); + assign n2173 = pstart_0_ & (pencrypt_0_ ? pkey_139_ : pkey_147_); + assign n2174 = n2173 | (pksi_149_ & n1327_1 & n1332_1); + assign n2175 = pstart_0_ & (pencrypt_0_ ? pkey_133_ : pkey_141_); + assign n2176 = n2175 | (pksi_156_ & n1327_1 & n1332_1); + assign n2177 = pstart_0_ & (pencrypt_0_ ? pkey_189_ : pkey_134_); + assign n2178 = n2177 | (pksi_147_ & n1327_1 & n1332_1); + assign n2179 = pstart_0_ & (pencrypt_0_ ? pkey_83_ : pkey_91_); + assign n2180 = n2179 | (n_n2462 & n1327_1 & n1332_1); + assign n2181 = pstart_0_ & (pencrypt_0_ ? pkey_109_ : pkey_117_); + assign n2182 = n2181 | (pksi_134_ & n1327_1 & n1332_1); + assign n2183 = pstart_0_ & (pencrypt_0_ ? pkey_3_ : pkey_11_); + assign n2184 = n2183 | (pksi_111_ & n1327_1 & n1332_1); + assign n2185 = pstart_0_ & (pencrypt_0_ ? pkey_218_ : pkey_226_); + assign n2186 = n2185 | (pksi_82_ & n1327_1 & n1332_1); + assign n2187 = pstart_0_ & (pencrypt_0_ ? pkey_147_ : pkey_155_); + assign n2188 = n2187 | (n_n2430 & n1327_1 & n1332_1); + assign n2189 = pstart_0_ & (pencrypt_0_ ? pkey_188_ : pkey_133_); + assign n2190 = n2189 | (n_n2440 & n1327_1 & n1332_1); + assign n2191 = pstart_0_ & (pencrypt_0_ ? pkey_134_ : pkey_142_); + assign n2192 = n2191 | (pksi_165_ & n1327_1 & n1332_1); + assign n2193 = pstart_0_ & (pencrypt_0_ ? pkey_75_ : pkey_83_); + assign n2194 = n2193 | (pksi_125_ & n1327_1 & n1332_1); + assign n2195 = pstart_0_ & (pencrypt_0_ ? pkey_117_ : pkey_125_); + assign n2196 = n2195 | (n_n2481 & n1327_1 & n1332_1); + assign n2197 = pstart_0_ & (pencrypt_0_ ? pkey_126_ : pkey_3_); + assign n2198 = n2197 | (pksi_142_ & n1327_1 & n1332_1); + assign n2199 = pstart_0_ & (pencrypt_0_ ? pkey_227_ : pkey_235_); + assign n2200 = n2199 | (pksi_79_ & n1327_1 & n1332_1); + assign n2201 = pstart_0_ & (pencrypt_0_ ? pkey_24_ : pkey_32_); + assign n2202 = n2201 | (pksi_5_ & n1327_1 & n1332_1); + assign n2203 = pstart_0_ & (pencrypt_0_ ? pkey_212_ : pkey_220_); + assign n2204 = n2203 | (pksi_188_ & n1327_1 & n1332_1); + assign n2205 = pstart_0_ & (pencrypt_0_ ? pkey_155_ : pkey_132_); + assign n2206 = n2205 | (n_n2430 & ~n1327_1 & n1332_1); + assign n2207 = pstart_0_ & (pencrypt_0_ ? pkey_149_ : pkey_157_); + assign n2208 = n2207 | (pksi_163_ & n1327_1 & n1332_1); + assign n2209 = pstart_0_ & (pencrypt_0_ ? pkey_174_ : pkey_182_); + assign n2210 = n2209 | (pksi_146_ & n1327_1 & n1332_1); + assign n2211 = pstart_0_ & (pencrypt_0_ ? pkey_100_ : pkey_44_); + assign n2212 = n2211 | (pksi_131_ & n1327_1 & n1332_1); + assign n2213 = pstart_0_ & (pencrypt_0_ ? pkey_124_ : pkey_69_); + assign n2214 = n2213 | (pksi_129_ & n1327_1 & n1332_1); + assign n2215 = pstart_0_ & (pencrypt_0_ ? pkey_86_ : pkey_94_); + assign n2216 = n2215 | (pksi_136_ & n1327_1 & n1332_1); + assign n2217 = pstart_0_ & (pencrypt_0_ ? pkey_52_ : pkey_60_); + assign n2218 = n2217 | (pksi_114_ & n1327_1 & n1332_1); + assign n2219 = pstart_0_ & (pencrypt_0_ ? pkey_14_ : pkey_22_); + assign n2220 = n2219 | (n_n2517 & n1327_1 & n1332_1); + assign n2221 = pstart_0_ & (pencrypt_0_ ? pkey_235_ : pkey_243_); + assign n2222 = n2221 | (pksi_92_ & n1327_1 & n1332_1); + assign n2223 = pstart_0_ & (pencrypt_0_ ? pkey_32_ : pkey_40_); + assign n2224 = n2223 | (pksi_15_ & n1327_1 & n1332_1); + assign n2225 = pstart_0_ & (pencrypt_0_ ? pkey_204_ : pkey_212_); + assign n2226 = n2225 | (pksi_176_ & n1327_1 & n1332_1); + assign n2227 = pstart_0_ & (pencrypt_0_ ? pkey_132_ : pkey_140_); + assign n2228 = n2227 | (pksi_145_ & n1327_1 & n1332_1); + assign n2229 = pstart_0_ & (pencrypt_0_ ? pkey_141_ : pkey_149_); + assign n2230 = n2229 | (pksi_153_ & n1327_1 & n1332_1); + assign n2231 = pstart_0_ & (pencrypt_0_ ? pkey_182_ : pkey_190_); + assign n2232 = n2231 | (pksi_150_ & n1327_1 & n1332_1); + assign n2233 = pstart_0_ & (pencrypt_0_ ? pkey_92_ : pkey_100_); + assign n2234 = n2233 | (pksi_133_ & n1327_1 & n1332_1); + assign n2235 = pstart_0_ & (pencrypt_0_ ? pkey_69_ : pkey_77_); + assign n2236 = n2235 | (pksi_132_ & n1327_1 & n1332_1); + assign n2237 = pstart_0_ & (pencrypt_0_ ? pkey_78_ : pkey_86_); + assign n2238 = n2237 | (n_n2485 & n1327_1 & n1332_1); + assign n2239 = pstart_0_ & (pencrypt_0_ ? pkey_60_ : pkey_5_); + assign n2240 = n2239 | (pksi_105_ & n1327_1 & n1332_1); + assign n2241 = pstart_0_ & (pencrypt_0_ ? pkey_6_ : pkey_14_); + assign n2242 = n2241 | (pksi_117_ & n1327_1 & n1332_1); + assign n2243 = pstart_0_ & (pencrypt_0_ ? pkey_243_ : pkey_251_); + assign n2244 = n2243 | (n_n10 & n1327_1 & n1332_1); + assign n2245 = pstart_0_ & (pencrypt_0_ ? pkey_221_ : pkey_229_); + assign n2246 = n2245 | (n_n2412 & n1327_1 & n1332_1); + assign n2247 = pstart_0_ & (pencrypt_0_ ? pkey_246_ : pkey_254_); + assign n2248 = n2247 | (pksi_174_ & n1327_1 & n1332_1); + assign n2249 = pstart_0_ & (pencrypt_0_ ? pkey_140_ : pkey_148_); + assign n2250 = n2249 | (pksi_152_ & n1327_1 & n1332_1); + assign n2251 = pstart_0_ & (pencrypt_0_ ? pkey_165_ : pkey_173_); + assign n2252 = n2251 | (pksi_151_ & n1327_1 & n1332_1); + assign n2253 = pstart_0_ & (pencrypt_0_ ? pkey_158_ : pkey_166_); + assign n2254 = n2253 | (pksi_154_ & n1327_1 & n1332_1); + assign n2255 = pstart_0_ & (pencrypt_0_ ? pkey_84_ : pkey_92_); + assign n2256 = n2255 | (pksi_140_ & n1327_1 & n1332_1); + assign n2257 = pstart_0_ & (pencrypt_0_ ? pkey_77_ : pkey_85_); + assign n2258 = n2257 | (n_n2474 & n1327_1 & n1332_1); + assign n2259 = pstart_0_ & (pencrypt_0_ ? pkey_102_ : pkey_110_); + assign n2260 = n2259 | (n_n168 & n1327_1 & n1332_1); + assign n2261 = pstart_0_ & (pencrypt_0_ ? pkey_5_ : pkey_13_); + assign n2262 = n2261 | (pksi_108_ & n1327_1 & n1332_1); + assign n2263 = pstart_0_ & (pencrypt_0_ ? pkey_251_ : pkey_194_); + assign n2264 = n2263 | (n_n2268 & n1327_1 & n1332_1); + assign n2265 = pstart_0_ & (pencrypt_0_ ? pkey_229_ : pkey_237_); + assign n2266 = n2265 | (pksi_175_ & n1327_1 & n1332_1); + assign n2267 = pstart_0_ & (pencrypt_0_ ? pkey_238_ : pkey_246_); + assign n2268 = n2267 | (pksi_170_ & n1327_1 & n1332_1); + assign n2269 = pstart_0_ & (pencrypt_0_ ? pkey_148_ : pkey_156_); + assign n2270 = n2269 | (pksi_164_ & n1327_1 & n1332_1); + assign n2271 = pstart_0_ & (pencrypt_0_ ? pkey_157_ : pkey_165_); + assign n2272 = n2271 | (pksi_144_ & n1327_1 & n1332_1); + assign n2273 = pstart_0_ & (pencrypt_0_ ? pkey_166_ : pkey_174_); + assign n2274 = n2273 | (pksi_167_ & n1327_1 & n1332_1); + assign n2275 = pstart_0_ & (pencrypt_0_ ? pkey_76_ : pkey_84_); + assign n2276 = n2275 | (pksi_128_ & n1327_1 & n1332_1); + assign n2277 = pstart_0_ & (pencrypt_0_ ? pkey_85_ : pkey_93_); + assign n2278 = n2277 | (n_n2474 & ~n1327_1 & n1332_1); + assign n2279 = pstart_0_ & (pencrypt_0_ ? pkey_94_ : pkey_102_); + assign n2280 = n2279 | (pksi_130_ & n1327_1 & n1332_1); + assign n2281 = pstart_0_ & (pencrypt_0_ ? pkey_22_ : pkey_30_); + assign n2282 = n2281 | (n_n2517 & ~n1327_1 & n1332_1); + assign n2283 = pstart_0_ & (pencrypt_0_ ? pkey_136_ : pkey_144_); + assign n2284 = n2283 | (pksi_67_ & n1327_1 & n1332_1); + assign n2285 = pstart_0_ & (pencrypt_0_ ? pkey_66_ : pkey_74_); + assign n2286 = n2285 | (n_n2333 & ~n1327_1 & n1332_1); + assign n2287 = pstart_0_ & (pencrypt_0_ ? pkey_89_ : pkey_97_); + assign n2288 = n2287 | (pksi_46_ & n1327_1 & n1332_1); + assign n2289 = pstart_0_ & (pencrypt_0_ ? pkey_112_ : pkey_120_); + assign n2290 = n2289 | (pksi_47_ & n1327_1 & n1332_1); + assign n2291 = pstart_0_ & (pencrypt_0_ ? pkey_42_ : pkey_50_); + assign n2292 = n2291 | (pksi_13_ & n1327_1 & n1332_1); + assign n2293 = pstart_0_ & (pencrypt_0_ ? pkey_144_ : pkey_152_); + assign n2294 = n2293 | (pksi_57_ & n1327_1 & n1332_1); + assign n2295 = pstart_0_ & (pencrypt_0_ ? pkey_123_ : pkey_66_); + assign n2296 = n2295 | (n_n2333 & n1327_1 & n1332_1); + assign n2297 = pstart_0_ & (pencrypt_0_ ? pkey_97_ : pkey_105_); + assign n2298 = n2297 | (pksi_38_ & n1327_1 & n1332_1); + assign n2299 = pstart_0_ & (pencrypt_0_ ? pkey_104_ : pkey_112_); + assign n2300 = n2299 | (pksi_30_ & n1327_1 & n1332_1); + assign n2301 = pstart_0_ & (pencrypt_0_ ? pkey_50_ : pkey_58_); + assign n2302 = n2301 | (n_n2374 & n1327_1 & n1332_1); + assign n2303 = pstart_0_ & (pencrypt_0_ ? pkey_152_ : pkey_160_); + assign n2304 = n2303 | (pksi_53_ & n1327_1 & n1332_1); + assign n2305 = pstart_0_ & (pencrypt_0_ ? pkey_82_ : pkey_90_); + assign n2306 = n2305 | (n_n2337 & n1327_1 & n1332_1); + assign n2307 = pstart_0_ & (pencrypt_0_ ? pkey_73_ : pkey_81_); + assign n2308 = n2307 | (pksi_32_ & n1327_1 & n1332_1); + assign n2309 = pstart_0_ & (pencrypt_0_ ? pkey_96_ : pkey_104_); + assign n2310 = n2309 | (pksi_39_ & n1327_1 & n1332_1); + assign n2311 = pstart_0_ & (pencrypt_0_ ? pkey_58_ : pkey_1_); + assign n2312 = n2311 | (n_n2374 & ~n1327_1 & n1332_1); + assign n2313 = pstart_0_ & (pencrypt_0_ ? pkey_56_ : pkey_227_); + assign n2314 = n2313 | (pksi_4_ & n1327_1 & n1332_1); + assign n2315 = pstart_0_ & (pencrypt_0_ ? pkey_160_ : pkey_168_); + assign n2316 = n2315 | (pksi_63_ & n1327_1 & n1332_1); + assign n2317 = pstart_0_ & (pencrypt_0_ ? pkey_74_ : pkey_82_); + assign n2318 = n2317 | (pksi_36_ & n1327_1 & n1332_1); + assign n2319 = pstart_0_ & (pencrypt_0_ ? pkey_81_ : pkey_89_); + assign n2320 = n2319 | (pksi_24_ & n1327_1 & n1332_1); + assign n2321 = pstart_0_ & (pencrypt_0_ ? pkey_88_ : pkey_96_); + assign n2322 = n2321 | (pksi_29_ & n1327_1 & n1332_1); + assign n2323 = pstart_0_ & (pencrypt_0_ ? pkey_1_ : pkey_9_); + assign n2324 = n2323 | (pksi_18_ & n1327_1 & n1332_1); + assign n2325 = pstart_0_ & (pencrypt_0_ ? pkey_234_ : pkey_242_); + assign n2326 = n2325 | (pksi_85_ & n1327_1 & n1332_1); + assign n2327 = pstart_0_ & (pencrypt_0_ ? pkey_192_ : pkey_200_); + assign n2328 = n2327 | (pksi_89_ & n1327_1 & n1332_1); + assign n2329 = pstart_0_ & (pencrypt_0_ ? pkey_187_ : pkey_130_); + assign n2330 = n2329 | (n_n2301 & n1327_1 & n1332_1); + assign n2331 = pstart_0_ & (pencrypt_0_ ? pkey_145_ : pkey_153_); + assign n2332 = n2331 | (pksi_48_ & n1327_1 & n1332_1); + assign n2333 = pstart_0_ & (pencrypt_0_ ? pkey_9_ : pkey_17_); + assign n2334 = n2333 | (pksi_8_ & n1327_1 & n1332_1); + assign n2335 = pstart_0_ & (pencrypt_0_ ? pkey_242_ : pkey_250_); + assign n2336 = n2335 | (n_n2277 & n1327_1 & n1332_1); + assign n2337 = pstart_0_ & (pencrypt_0_ ? pkey_249_ : pkey_192_); + assign n2338 = n2337 | (n_n2288 & n1327_1 & n1332_1); + assign n2339 = pstart_0_ & (pencrypt_0_ ? pkey_130_ : pkey_138_); + assign n2340 = n2339 | (pksi_51_ & n1327_1 & n1332_1); + assign n2341 = pstart_0_ & (pencrypt_0_ ? pkey_137_ : pkey_145_); + assign n2342 = n2341 | (pksi_56_ & n1327_1 & n1332_1); + assign n2343 = pstart_0_ & (pencrypt_0_ ? pkey_17_ : pkey_25_); + assign n2344 = n2343 | (pksi_0_ & n1327_1 & n1332_1); + assign n2345 = pstart_0_ & (pencrypt_0_ ? pkey_250_ : pkey_193_); + assign n2346 = n2345 | (n_n2277 & ~n1327_1 & n1332_1); + assign n2347 = pstart_0_ & (pencrypt_0_ ? pkey_208_ : pkey_216_); + assign n2348 = n2347 | (pksi_81_ & n1327_1 & n1332_1); + assign n2349 = pstart_0_ & (pencrypt_0_ ? pkey_171_ : pkey_179_); + assign n2350 = n2349 | (pksi_68_ & n1327_1 & n1332_1); + assign n2351 = pstart_0_ & (pencrypt_0_ ? pkey_129_ : pkey_137_); + assign n2352 = n2351 | (pksi_66_ & n1327_1 & n1332_1); + assign n2353 = pstart_0_ & (pencrypt_0_ ? pkey_193_ : pkey_201_); + assign n2354 = n2353 | (n_n2280 & n1327_1 & n1332_1); + assign n2355 = pstart_0_ & (pencrypt_0_ ? pkey_200_ : pkey_208_); + assign n2356 = n2355 | (pksi_91_ & n1327_1 & n1332_1); + assign n2357 = pstart_0_ & (pencrypt_0_ ? pkey_179_ : pkey_187_); + assign n2358 = n2357 | (pksi_64_ & n1327_1 & n1332_1); + assign n2359 = pstart_0_ & (pencrypt_0_ ? pkey_186_ : pkey_129_); + assign n2360 = n2359 | (pksi_49_ & n1327_1 & n1332_1); + assign n2361 = pstart_0_ & (pencrypt_0_ ? pkey_201_ : pkey_209_); + assign n2362 = n2361 | (pksi_80_ & n1327_1 & n1332_1); + assign n2363 = pstart_0_ & (pencrypt_0_ ? pkey_224_ : pkey_232_); + assign n2364 = n2363 | (pksi_87_ & n1327_1 & n1332_1); + assign n2365 = pstart_0_ & (pencrypt_0_ ? pkey_154_ : pkey_162_); + assign n2366 = n2365 | (pksi_58_ & n1327_1 & n1332_1); + assign n2367 = pstart_0_ & (pencrypt_0_ ? pkey_177_ : pkey_185_); + assign n2368 = n2367 | (pksi_59_ & n1327_1 & n1332_1); + assign n2369 = pstart_0_ & (pencrypt_0_ ? pkey_107_ : pkey_115_); + assign n2370 = n2369 | (pksi_44_ & n1327_1 & n1332_1); + assign n2371 = pstart_0_ & (pencrypt_0_ ? pkey_65_ : pkey_73_); + assign n2372 = n2371 | (pksi_42_ & n1327_1 & n1332_1); + assign n2373 = pstart_0_ & (pencrypt_0_ ? pkey_209_ : pkey_217_); + assign n2374 = n2373 | (pksi_72_ & n1327_1 & n1332_1); + assign n2375 = pstart_0_ & (pencrypt_0_ ? pkey_216_ : pkey_224_); + assign n2376 = n2375 | (pksi_77_ & n1327_1 & n1332_1); + assign n2377 = pstart_0_ & (pencrypt_0_ ? pkey_162_ : pkey_170_); + assign n2378 = n2377 | (pksi_69_ & n1327_1 & n1332_1); + assign n2379 = pstart_0_ & (pencrypt_0_ ? pkey_169_ : pkey_177_); + assign n2380 = n2379 | (pksi_50_ & n1327_1 & n1332_1); + assign n2381 = pstart_0_ & (pencrypt_0_ ? pkey_115_ : pkey_123_); + assign n2382 = n2381 | (pksi_40_ & n1327_1 & n1332_1); + assign n2383 = pstart_0_ & (pencrypt_0_ ? pkey_122_ : pkey_65_); + assign n2384 = n2383 | (n_n2342 & ~n1327_1 & n1332_1); + assign n2385 = pstart_0_ & (pencrypt_0_ ? pkey_217_ : pkey_225_); + assign n2386 = n2385 | (pksi_94_ & n1327_1 & n1332_1); + assign n2387 = pstart_0_ & (pencrypt_0_ ? pkey_240_ : pkey_248_); + assign n2388 = n2387 | (pksi_95_ & n1327_1 & n1332_1); + assign n2389 = pstart_0_ & (pencrypt_0_ ? pkey_138_ : pkey_146_); + assign n2390 = n2389 | (pksi_60_ & n1327_1 & n1332_1); + assign n2391 = pstart_0_ & (pencrypt_0_ ? pkey_161_ : pkey_169_); + assign n2392 = n2391 | (pksi_62_ & n1327_1 & n1332_1); + assign n2393 = pstart_0_ & (pencrypt_0_ ? pkey_72_ : pkey_80_); + assign n2394 = n2393 | (pksi_43_ & n1327_1 & n1332_1); + assign n2395 = pstart_0_ & (pencrypt_0_ ? pkey_2_ : pkey_10_); + assign n2396 = n2395 | (n_n2365 & ~n1327_1 & n1332_1); + assign n2397 = pstart_0_ & (pencrypt_0_ ? pkey_225_ : pkey_233_); + assign n2398 = n2397 | (pksi_86_ & n1327_1 & n1332_1); + assign n2399 = pstart_0_ & (pencrypt_0_ ? pkey_232_ : pkey_240_); + assign n2400 = n2399 | (pksi_78_ & n1327_1 & n1332_1); + assign n2401 = pstart_0_ & (pencrypt_0_ ? pkey_146_ : pkey_154_); + assign n2402 = n2401 | (n_n2305 & n1327_1 & n1332_1); + assign n2403 = pstart_0_ & (pencrypt_0_ ? pkey_153_ : pkey_161_); + assign n2404 = n2403 | (pksi_70_ & n1327_1 & n1332_1); + assign n2405 = pstart_0_ & (pencrypt_0_ ? pkey_80_ : pkey_88_); + assign n2406 = n2405 | (pksi_33_ & n1327_1 & n1332_1); + assign n2407 = pstart_0_ & (pencrypt_0_ ? pkey_59_ : pkey_2_); + assign n2408 = n2407 | (n_n2365 & n1327_1 & n1332_1); + assign n2409 = pstart_0_ & (pencrypt_0_ ? pkey_233_ : pkey_241_); + assign n2410 = n2409 | (pksi_74_ & n1327_1 & n1332_1); + assign n2411 = pstart_0_ & (pencrypt_0_ ? pkey_163_ : pkey_171_); + assign n2412 = n2411 | (pksi_55_ & n1327_1 & n1332_1); + assign n2413 = pstart_0_ & (pencrypt_0_ ? pkey_168_ : pkey_176_); + assign n2414 = n2413 | (pksi_54_ & n1327_1 & n1332_1); + assign n2415 = pstart_0_ & (pencrypt_0_ ? pkey_98_ : pkey_106_); + assign n2416 = n2415 | (pksi_45_ & n1327_1 & n1332_1); + assign n2417 = pstart_0_ & (pencrypt_0_ ? pkey_121_ : pkey_64_); + assign n2418 = n2417 | (n_n2352 & n1327_1 & n1332_1); + assign n2419 = pstart_0_ & (pencrypt_0_ ? pkey_51_ : pkey_59_); + assign n2420 = n2419 | (pksi_16_ & n1327_1 & n1332_1); + assign n2421 = pstart_0_ & (pencrypt_0_ ? pkey_10_ : pkey_18_); + assign n2422 = n2421 | (pksi_12_ & n1327_1 & n1332_1); + assign n2423 = pstart_0_ & (pencrypt_0_ ? pkey_241_ : pkey_249_); + assign n2424 = n2423 | (pksi_83_ & n1327_1 & n1332_1); + assign n2425 = pstart_0_ & (pencrypt_0_ ? pkey_248_ : pkey_163_); + assign n2426 = n2425 | (pksi_76_ & n1327_1 & n1332_1); + assign n2427 = pstart_0_ & (pencrypt_0_ ? pkey_176_ : pkey_184_); + assign n2428 = n2427 | (pksi_71_ & n1327_1 & n1332_1); + assign n2429 = pstart_0_ & (pencrypt_0_ ? pkey_90_ : pkey_98_); + assign n2430 = n2429 | (n_n2337 & ~n1327_1 & n1332_1); + assign n2431 = pstart_0_ & (pencrypt_0_ ? pkey_64_ : pkey_72_); + assign n2432 = n2431 | (n_n2352 & ~n1327_1 & n1332_1); + assign n2433 = pstart_0_ & (pencrypt_0_ ? pkey_43_ : pkey_51_); + assign n2434 = n2433 | (pksi_20_ & n1327_1 & n1332_1); + assign n2435 = pstart_0_ & (pencrypt_0_ ? pkey_18_ : pkey_26_); + assign n2436 = n2435 | (n_n2369 & n1327_1 & n1332_1); + assign n2437 = pstart_0_ & (pencrypt_0_ ? pkey_170_ : pkey_178_); + assign n2438 = n2437 | (pksi_61_ & n1327_1 & n1332_1); + assign n2439 = pstart_0_ & (pencrypt_0_ ? pkey_128_ : pkey_136_); + assign n2440 = n2439 | (n_n2320 & ~n1327_1 & n1332_1); + assign n2441 = pstart_0_ & (pencrypt_0_ ? pkey_184_ : pkey_99_); + assign n2442 = n2441 | (pksi_52_ & n1327_1 & n1332_1); + assign n2443 = pstart_0_ & (pencrypt_0_ ? pkey_114_ : pkey_122_); + assign n2444 = n2443 | (n_n2342 & n1327_1 & n1332_1); + assign n2445 = pstart_0_ & (pencrypt_0_ ? pkey_105_ : pkey_113_); + assign n2446 = n2445 | (pksi_26_ & n1327_1 & n1332_1); + assign n2447 = pstart_0_ & (pencrypt_0_ ? pkey_35_ : pkey_43_); + assign n2448 = n2447 | (pksi_7_ & n1327_1 & n1332_1); + assign n2449 = pstart_0_ & (pencrypt_0_ ? pkey_26_ : pkey_34_); + assign n2450 = n2449 | (n_n2369 & ~n1327_1 & n1332_1); + assign n2451 = pstart_0_ & (pencrypt_0_ ? pkey_178_ : pkey_186_); + assign n2452 = n2451 | (n_n2310 & n1327_1 & n1332_1); + assign n2453 = pstart_0_ & (pencrypt_0_ ? pkey_185_ : pkey_128_); + assign n2454 = n2453 | (n_n2320 & n1327_1 & n1332_1); + assign n2455 = pstart_0_ & (pencrypt_0_ ? pkey_99_ : pkey_107_); + assign n2456 = n2455 | (pksi_31_ & n1327_1 & n1332_1); + assign n2457 = pstart_0_ & (pencrypt_0_ ? pkey_106_ : pkey_114_); + assign n2458 = n2457 | (pksi_37_ & n1327_1 & n1332_1); + assign n2459 = pstart_0_ & (pencrypt_0_ ? pkey_113_ : pkey_121_); + assign n2460 = n2459 | (pksi_35_ & n1327_1 & n1332_1); + assign n2461 = pstart_0_ & (pencrypt_0_ ? pkey_120_ : pkey_35_); + assign n2462 = n2461 | (pksi_28_ & n1327_1 & n1332_1); + assign n2463 = pstart_0_ & (pencrypt_0_ ? pkey_34_ : pkey_42_); + assign n2464 = n2463 | (pksi_21_ & n1327_1 & n1332_1); + assign n2465 = ~pencrypt_0_ & ~pstart_0_ & ~pcount_1_ & ~pcount_0_; + assign n2466 = pcount_2_ ? ~pencrypt_0_ : (~pstart_0_ & pencrypt_0_); + assign n2467 = n1341 | ~n1330 | (~pcount_2_ & n1329); + always @ (posedge clock) begin + pksi_17_ <= n853; + pksi_185_ <= n857; + n_n2410 <= n861; + pksi_170_ <= n866; + pksi_155_ <= n870; + pksi_147_ <= n874; + pksi_109_ <= n878; + n_n2513 <= n882; + pksi_19_ <= n887; + n_n2396 <= n891; + n_n2412 <= n896; + n_n121 <= n901; + pksi_148_ <= n906; + n_n2448 <= n910; + pksi_107_ <= n915; + pksi_110_ <= n919; + pksi_9_ <= n923; + pksi_176_ <= n927; + pksi_180_ <= n931; + pksi_178_ <= n935; + pksi_135_ <= n939; + pksi_129_ <= n943; + pksi_100_ <= n947; + pksi_117_ <= n951; + pksi_118_ <= n955; + pksi_5_ <= n959; + pksi_169_ <= n963; + n_n2408 <= n967; + pksi_184_ <= n972; + pksi_125_ <= n976; + pksi_138_ <= n980; + pksi_114_ <= n984; + pksi_99_ <= n988; + pksi_85_ <= n992; + pksi_14_ <= n996; + pksi_4_ <= n1000; + pksi_186_ <= n1004; + n_n2420 <= n1008; + pksi_141_ <= n1013; + pksi_113_ <= n1017; + pksi_115_ <= n1021; + pksi_98_ <= n1025; + pksi_2_ <= n1029; + pksi_23_ <= n1033; + pksi_177_ <= n1037; + pksi_189_ <= n1041; + n_n2485 <= n1045; + n_n2495 <= n1050; + pksi_97_ <= n1055; + pksi_102_ <= n1059; + pksi_11_ <= n1063; + pksi_173_ <= n1067; + pksi_179_ <= n1071; + pksi_171_ <= n1075; + pksi_104_ <= n1079; + pksi_103_ <= n1083; + n_n2384 <= n1087; + pksi_183_ <= n1092; + pksi_172_ <= n1096; + n_n2416 <= n1100; + pksi_116_ <= n1105; + pksi_96_ <= n1109; + pksi_119_ <= n1113; + pksi_84_ <= n1117; + pksi_159_ <= n1121; + n_n2440 <= n1125; + pksi_160_ <= n1130; + pksi_128_ <= n1134; + pksi_127_ <= n1138; + pksi_142_ <= n1142; + n_n2272 <= n1146; + pksi_149_ <= n1151; + pksi_162_ <= n1155; + pksi_154_ <= n1159; + pksi_121_ <= n1163; + pksi_134_ <= n1167; + pksi_126_ <= n1171; + pksi_82_ <= n1175; + n_n2430 <= n1179; + pksi_153_ <= n1184; + pksi_165_ <= n1188; + pksi_137_ <= n1192; + n_n2481 <= n1196; + pksi_101_ <= n1201; + pksi_93_ <= n1205; + pksi_161_ <= n1209; + pksi_156_ <= n1213; + n_n2452 <= n1217; + n_n2462 <= n1222; + pksi_123_ <= n1227; + pksi_111_ <= n1231; + pksi_92_ <= n1235; + pksi_15_ <= n1239; + n_n109 <= n1243; + pksi_145_ <= n1248; + pksi_144_ <= n1252; + pksi_150_ <= n1256; + pksi_124_ <= n1260; + pksi_132_ <= n1264; + pksi_130_ <= n1268; + pksi_105_ <= n1272; + pksi_112_ <= n1276; + n_n10 <= n1280; + pksi_6_ <= n1285; + pksi_188_ <= n1289; + pksi_152_ <= n1293; + pksi_163_ <= n1297; + pksi_166_ <= n1301; + pksi_131_ <= n1305; + n_n2474 <= n1309; + pksi_136_ <= n1314; + pksi_108_ <= n1318; + n_n2517 <= n1322; + n_n2268 <= n1327; + pksi_175_ <= n1332; + pksi_190_ <= n1336; + pksi_164_ <= n1340; + pksi_158_ <= n1344; + pksi_167_ <= n1348; + pksi_133_ <= n1352; + n_n2476 <= n1356; + pksi_122_ <= n1361; + n_n2507 <= n1365; + pksi_75_ <= n1370; + pksi_182_ <= n1374; + pksi_174_ <= n1378; + pksi_157_ <= n1382; + pksi_151_ <= n1386; + pksi_146_ <= n1390; + pksi_140_ <= n1394; + pksi_120_ <= n1398; + n_n168 <= n1402; + pksi_106_ <= n1407; + pksi_57_ <= n1411; + pksi_36_ <= n1415; + pksi_38_ <= n1419; + pksi_28_ <= n1423; + n_n2374 <= n1427; + pksi_53_ <= n1432; + pksi_27_ <= n1436; + pksi_26_ <= n1440; + pksi_47_ <= n1444; + pksi_1_ <= n1448; + pksi_63_ <= n1452; + pksi_34_ <= n1456; + pksi_24_ <= n1460; + pksi_30_ <= n1464; + pksi_18_ <= n1468; + pksi_79_ <= n1472; + pksi_54_ <= n1476; + n_n2337 <= n1480; + pksi_46_ <= n1485; + pksi_39_ <= n1489; + pksi_8_ <= n1493; + n_n2277 <= n1497; + pksi_91_ <= n1502; + pksi_51_ <= n1506; + pksi_70_ <= n1510; + pksi_0_ <= n1514; + pksi_73_ <= n1518; + pksi_89_ <= n1522; + pksi_60_ <= n1526; + pksi_48_ <= n1530; + pksi_22_ <= n1534; + n_n2280 <= n1538; + pksi_77_ <= n1543; + pksi_64_ <= n1547; + pksi_56_ <= n1551; + pksi_80_ <= n1555; + pksi_81_ <= n1559; + n_n2301 <= n1563; + pksi_66_ <= n1568; + pksi_72_ <= n1572; + pksi_78_ <= n1576; + pksi_69_ <= n1580; + n_n2320 <= n1584; + pksi_40_ <= n1589; + pksi_32_ <= n1593; + pksi_94_ <= n1597; + pksi_87_ <= n1601; + pksi_61_ <= n1605; + pksi_59_ <= n1609; + n_n2333 <= n1613; + pksi_42_ <= n1618; + pksi_86_ <= n1622; + pksi_76_ <= n1626; + n_n2305 <= n1630; + pksi_50_ <= n1635; + pksi_33_ <= n1639; + pksi_12_ <= n1643; + pksi_74_ <= n1647; + pksi_95_ <= n1651; + pksi_58_ <= n1655; + pksi_62_ <= n1659; + pksi_29_ <= n1663; + pksi_3_ <= n1667; + pksi_83_ <= n1671; + pksi_68_ <= n1675; + pksi_71_ <= n1679; + pksi_37_ <= n1683; + pksi_41_ <= n1687; + n_n2365 <= n1691; + n_n2369 <= n1696; + n_n2288 <= n1701; + pksi_55_ <= n1706; + pksi_52_ <= n1710; + pksi_45_ <= n1714; + pksi_43_ <= n1718; + pksi_16_ <= n1722; + pksi_10_ <= n1726; + n_n2310 <= n1730; + pksi_67_ <= n1735; + pksi_31_ <= n1739; + pksi_25_ <= n1743; + pksi_35_ <= n1747; + pksi_20_ <= n1751; + pksi_21_ <= n1755; + pksi_49_ <= n1759; + pksi_65_ <= n1763; + pksi_44_ <= n1767; + n_n2342 <= n1771; + n_n2352 <= n1776; + pksi_7_ <= n1781; + pksi_13_ <= n1785; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v b/openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v new file mode 100644 index 000000000..34435cafd --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v @@ -0,0 +1,5343 @@ +// Benchmark "top" written by ABC on Thu Feb 21 17:22:32 2019 + +module elliptic ( clock, + tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_, + tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_, + tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_, + tin_psv39_9_9_, tin_psv39_1_1_, tin_psv13_6_6_, tin_psv2_6_6_, + pinp_0_0_, tin_psv38_3_3_, tin_psv33_6_6_, tin_psv26_13_13_, + tin_psv26_12_12_, tin_psv26_7_7_, tin_psv2_7_7_, pinp_1_1_, + preset_0_0_, tin_psv18_3_3_, tin_psv39_2_2_, tin_psv33_12_12_, + tin_psv33_11_11_, tin_psv33_10_10_, tin_psv13_7_7_, tin_psv2_10_10_, + tin_psv38_4_4_, tin_psv39_10_10_, tin_psv33_7_7_, tin_psv26_15_15_, + tin_psv26_14_14_, tin_psv26_8_8_, tin_psv26_0_0_, tin_psv13_12_12_, + tin_psv13_11_11_, tin_psv18_4_4_, tin_psv39_3_3_, tin_psv13_8_8_, + tin_psv13_0_0_, pinp_15_15_, pinp_12_12_, tin_psv38_5_5_, + tin_psv33_8_8_, tin_psv33_0_0_, tin_psv26_9_9_, tin_psv26_1_1_, + tin_psv13_10_10_, tin_psv18_5_5_, tin_psv39_4_4_, tin_psv13_9_9_, + tin_psv13_1_1_, tin_psv2_15_15_, tin_psv2_11_11_, tin_psv2_0_0_, + tin_psv38_14_14_, tin_psv38_12_12_, tin_psv38_10_10_, tin_psv38_6_6_, + tin_psv18_15_15_, tin_psv18_13_13_, tin_psv18_11_11_, tin_psv33_9_9_, + tin_psv33_1_1_, tin_psv26_2_2_, tin_psv2_1_1_, pclk, tin_psv38_15_15_, + tin_psv38_11_11_, tin_psv18_12_12_, tin_psv18_6_6_, tin_psv39_5_5_, + tin_psv13_2_2_, pinp_14_14_, pinp_11_11_, pinp_8_8_, tin_psv38_7_7_, + tin_psv39_12_12_, tin_psv39_11_11_, tin_psv33_2_2_, tin_psv26_3_3_, + tin_psv13_14_14_, tin_psv13_13_13_, pinp_9_9_, tin_psv18_10_10_, + tin_psv18_7_7_, tin_psv39_6_6_, tin_psv33_15_15_, tin_psv33_14_14_, + tin_psv33_13_13_, tin_psv13_3_3_, tin_psv2_14_14_, tin_psv2_12_12_, + tin_psv2_4_4_, pinp_6_6_, tin_psv38_8_8_, tin_psv38_0_0_, + tin_psv39_14_14_, tin_psv39_13_13_, tin_psv33_3_3_, tin_psv26_11_11_, + tin_psv26_10_10_, tin_psv26_4_4_, tin_psv13_15_15_, tin_psv2_5_5_, + pinp_7_7_, tin_psv18_8_8_, tin_psv18_0_0_, tin_psv39_7_7_, + tin_psv13_4_4_, tin_psv2_2_2_, pinp_13_13_, pinp_10_10_, pinp_4_4_, + tin_psv38_9_9_, tin_psv38_1_1_, preset, tin_psv39_15_15_, + tin_psv33_4_4_, tin_psv26_5_5_, tin_psv2_3_3_, pinp_5_5_, + tin_psv38_13_13_, tin_psv18_14_14_, tin_psv18_9_9_, tin_psv18_1_1_, + psv39_8_8_, psv39_0_0_, psv13_5_5_, psv2_13_13_, psv2_8_8_, psv38_2_2_, + psv33_5_5_, psv26_6_6_, psv2_9_9_, psv18_2_2_, psv39_9_9_, psv39_1_1_, + psv13_6_6_, psv2_6_6_, psv38_3_3_, psv33_6_6_, psv26_13_13_, + psv26_12_12_, psv26_7_7_, psv2_7_7_, psv18_3_3_, psv39_2_2_, + psv33_12_12_, psv33_11_11_, psv33_10_10_, psv13_7_7_, psv2_10_10_, + psv38_4_4_, psv39_10_10_, psv33_7_7_, psv26_15_15_, psv26_14_14_, + psv26_8_8_, psv26_0_0_, psv13_12_12_, psv13_11_11_, psv18_4_4_, + psv39_3_3_, psv13_8_8_, psv13_0_0_, psv38_5_5_, psv33_8_8_, psv33_0_0_, + psv26_9_9_, psv26_1_1_, psv13_10_10_, psv18_5_5_, psv39_4_4_, + psv13_9_9_, psv13_1_1_, psv2_15_15_, psv2_11_11_, psv2_0_0_, + psv38_14_14_, psv38_12_12_, psv38_10_10_, psv38_6_6_, psv18_15_15_, + psv18_13_13_, psv18_11_11_, psv33_9_9_, psv33_1_1_, psv26_2_2_, + psv2_1_1_, psv38_15_15_, psv38_11_11_, psv18_12_12_, psv18_6_6_, + psv39_5_5_, psv13_2_2_, pover_0_0_, psv38_7_7_, psv39_12_12_, + psv39_11_11_, psv33_2_2_, psv26_3_3_, psv13_14_14_, psv13_13_13_, + psv18_10_10_, psv18_7_7_, psv39_6_6_, psv33_15_15_, psv33_14_14_, + psv33_13_13_, psv13_3_3_, psv2_14_14_, psv2_12_12_, psv2_4_4_, + psv38_8_8_, psv38_0_0_, pdn, psv39_14_14_, psv39_13_13_, psv33_3_3_, + psv26_11_11_, psv26_10_10_, psv26_4_4_, psv13_15_15_, psv2_5_5_, + psv18_8_8_, psv18_0_0_, psv39_7_7_, psv13_4_4_, psv2_2_2_, psv38_9_9_, + psv38_1_1_, psv39_15_15_, psv33_4_4_, psv26_5_5_, psv2_3_3_, + psv38_13_13_, psv18_14_14_, psv18_9_9_, psv18_1_1_ ); + input clock, tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_, + tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_, + tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_, + tin_psv39_9_9_, tin_psv39_1_1_, tin_psv13_6_6_, tin_psv2_6_6_, + pinp_0_0_, tin_psv38_3_3_, tin_psv33_6_6_, tin_psv26_13_13_, + tin_psv26_12_12_, tin_psv26_7_7_, tin_psv2_7_7_, pinp_1_1_, + preset_0_0_, tin_psv18_3_3_, tin_psv39_2_2_, tin_psv33_12_12_, + tin_psv33_11_11_, tin_psv33_10_10_, tin_psv13_7_7_, tin_psv2_10_10_, + tin_psv38_4_4_, tin_psv39_10_10_, tin_psv33_7_7_, tin_psv26_15_15_, + tin_psv26_14_14_, tin_psv26_8_8_, tin_psv26_0_0_, tin_psv13_12_12_, + tin_psv13_11_11_, tin_psv18_4_4_, tin_psv39_3_3_, tin_psv13_8_8_, + tin_psv13_0_0_, pinp_15_15_, pinp_12_12_, tin_psv38_5_5_, + tin_psv33_8_8_, tin_psv33_0_0_, tin_psv26_9_9_, tin_psv26_1_1_, + tin_psv13_10_10_, tin_psv18_5_5_, tin_psv39_4_4_, tin_psv13_9_9_, + tin_psv13_1_1_, tin_psv2_15_15_, tin_psv2_11_11_, tin_psv2_0_0_, + tin_psv38_14_14_, tin_psv38_12_12_, tin_psv38_10_10_, tin_psv38_6_6_, + tin_psv18_15_15_, tin_psv18_13_13_, tin_psv18_11_11_, tin_psv33_9_9_, + tin_psv33_1_1_, tin_psv26_2_2_, tin_psv2_1_1_, pclk, tin_psv38_15_15_, + tin_psv38_11_11_, tin_psv18_12_12_, tin_psv18_6_6_, tin_psv39_5_5_, + tin_psv13_2_2_, pinp_14_14_, pinp_11_11_, pinp_8_8_, tin_psv38_7_7_, + tin_psv39_12_12_, tin_psv39_11_11_, tin_psv33_2_2_, tin_psv26_3_3_, + tin_psv13_14_14_, tin_psv13_13_13_, pinp_9_9_, tin_psv18_10_10_, + tin_psv18_7_7_, tin_psv39_6_6_, tin_psv33_15_15_, tin_psv33_14_14_, + tin_psv33_13_13_, tin_psv13_3_3_, tin_psv2_14_14_, tin_psv2_12_12_, + tin_psv2_4_4_, pinp_6_6_, tin_psv38_8_8_, tin_psv38_0_0_, + tin_psv39_14_14_, tin_psv39_13_13_, tin_psv33_3_3_, tin_psv26_11_11_, + tin_psv26_10_10_, tin_psv26_4_4_, tin_psv13_15_15_, tin_psv2_5_5_, + pinp_7_7_, tin_psv18_8_8_, tin_psv18_0_0_, tin_psv39_7_7_, + tin_psv13_4_4_, tin_psv2_2_2_, pinp_13_13_, pinp_10_10_, pinp_4_4_, + tin_psv38_9_9_, tin_psv38_1_1_, preset, tin_psv39_15_15_, + tin_psv33_4_4_, tin_psv26_5_5_, tin_psv2_3_3_, pinp_5_5_, + tin_psv38_13_13_, tin_psv18_14_14_, tin_psv18_9_9_, tin_psv18_1_1_; + output psv39_8_8_, psv39_0_0_, psv13_5_5_, psv2_13_13_, psv2_8_8_, + psv38_2_2_, psv33_5_5_, psv26_6_6_, psv2_9_9_, psv18_2_2_, psv39_9_9_, + psv39_1_1_, psv13_6_6_, psv2_6_6_, psv38_3_3_, psv33_6_6_, + psv26_13_13_, psv26_12_12_, psv26_7_7_, psv2_7_7_, psv18_3_3_, + psv39_2_2_, psv33_12_12_, psv33_11_11_, psv33_10_10_, psv13_7_7_, + psv2_10_10_, psv38_4_4_, psv39_10_10_, psv33_7_7_, psv26_15_15_, + psv26_14_14_, psv26_8_8_, psv26_0_0_, psv13_12_12_, psv13_11_11_, + psv18_4_4_, psv39_3_3_, psv13_8_8_, psv13_0_0_, psv38_5_5_, psv33_8_8_, + psv33_0_0_, psv26_9_9_, psv26_1_1_, psv13_10_10_, psv18_5_5_, + psv39_4_4_, psv13_9_9_, psv13_1_1_, psv2_15_15_, psv2_11_11_, + psv2_0_0_, psv38_14_14_, psv38_12_12_, psv38_10_10_, psv38_6_6_, + psv18_15_15_, psv18_13_13_, psv18_11_11_, psv33_9_9_, psv33_1_1_, + psv26_2_2_, psv2_1_1_, psv38_15_15_, psv38_11_11_, psv18_12_12_, + psv18_6_6_, psv39_5_5_, psv13_2_2_, pover_0_0_, psv38_7_7_, + psv39_12_12_, psv39_11_11_, psv33_2_2_, psv26_3_3_, psv13_14_14_, + psv13_13_13_, psv18_10_10_, psv18_7_7_, psv39_6_6_, psv33_15_15_, + psv33_14_14_, psv33_13_13_, psv13_3_3_, psv2_14_14_, psv2_12_12_, + psv2_4_4_, psv38_8_8_, psv38_0_0_, pdn, psv39_14_14_, psv39_13_13_, + psv33_3_3_, psv26_11_11_, psv26_10_10_, psv26_4_4_, psv13_15_15_, + psv2_5_5_, psv18_8_8_, psv18_0_0_, psv39_7_7_, psv13_4_4_, psv2_2_2_, + psv38_9_9_, psv38_1_1_, psv39_15_15_, psv33_4_4_, psv26_5_5_, + psv2_3_3_, psv38_13_13_, psv18_14_14_, psv18_9_9_, psv18_1_1_; + reg n_n9280, n_n9172, n_n9260, n_n7726, n_n8270, n_n8196, n_n9150, + n_n9267, n_n7779, n_n9503, n_n8150, n_n9401, n_n7341, n_n9180, n_n8592, + n_n8871, n_n7252, n_n7271, n_n6991, n_n8557, n_n7707, n_n7552, ndn3_23, + n_n9548, n_n9467, n_n8002, n_n6950, n_n8930, n_n7244, n_n7819, n_n8883, + n_n7709, n_n9580, n_n9130, n_n9486, n_n9235, n_n7522, n_n7373, n_n9085, + n_n9638, n_n7452, n_n8775, n_n7654, n_n8410, n_n8208, n_n8377, n_n7558, + n_n7599, n_n8225, n_n8202, n_n7670, n_n7888, n_n7889, n_n8597, n_n8152, + n_n8394, n_n7812, n_n7816, n_n9141, n_n7332, n_n8758, n_n7765, n_n7877, + n_n7814, n_n9008, n_n7581, n_n7376, n_n7970, pover_0_0_, n_n8599, + n_n8227, n_n9442, n_n9485, n_n7148, n_n9311, n_n9273, ndn3_9, n_n8613, + n_n8533, n_n8699, n_n8609, n_n8308, n_n8655, n_n8981, n_n7583, n_n9198, + n_n9602, n_n8786, n_n9598, n_n7738, n_n8573, n_n9473, n_n9000, n_n8001, + n_n9554, n_n8508, n_n9635, n_n7190, n_n8702, n_n9106, n_n7409, n_n9437, + n_n9052, n_n8647, n_n9265, n_n7179, ndn3_13, ndn3_17, ndn3_25, ndn3_29, + n_n9539, n_n7953, n_n8488, nen3_22, n_n9438, n_n8132, n_n8661, n_n7759, + n_n8333, n_n9399, n_n7798, n_n9434, n_n7910, n_n9528, n_n7850, n_n8251, + n_n7937, n_n8482, n_n9290, n_n8007, n_n7556, n_n9064, n_n9398, n_n9412, + n_n9361, n_n9304, n_n7651, n_n7712, n_n7735, n_n7934, n_n7811, n_n8053, + n_n9015, n_n8066, n_n9518, n_n8091, n_n9257, n_n8175, n_n8491, n_n8114, + n_n7951, n_n8913, n_n8035, n_n8631, n_n8243, n_n7857, ngfdn_3, n_n7791, + n_n9175, n_n9588, n_n9049, n_n9483, n_n9410, n_n7691, n_n7740, n_n7602, + n_n7783, n_n7948, n_n7054, n_n9343, n_n9400, nsr1_2, n_n9127, n_n8531, + n_n9335, n_n7324, n_n9611, n_n8112, n_n9406, n_n9618, n_n9613, n_n9242, + n_n7384, n_n8884, n_n7462, n_n7908, n_n8765, n_n7909, n_n7898, n_n9135, + n_n8862, n_n8037, ndn3_18, ndn3_22, n_n8974, n_n7286, n_n9223, n_n7306, + n_n9169, n_n9125, nen3_39, n_n8278, n_n9557, n_n7758, n_n9391, n_n8110, + n_n9597, n_n8568, n_n7428, n_n7931, n_n7742, n_n7236, n_n8219, n_n9568, + n_n9200, n_n8545, n_n7823, n_n8005, n_n8736, n_n9339, n_n8499, n_n8086, + n_n7803, n_n7640, n_n9098, n_n7160, n_n7713, n_n9566, n_n7955, n_n8414, + n_n8006, n_n9560, n_n8742, n_n7174, n_n8882, n_n7546, n_n8282, n_n8998, + n_n7656, n_n9465, n_n9601, n_n8875, n_n7954, n_n8959, n_n8957, n_n8247, + n_n8258, n_n7641, n_n8843, n_n9321, n_n7702, nsr3_23, n_n8199, n_n7983, + n_n7217, n_n7821, n_n9489, n_n8348, n_n9408, n_n8445, n_n9501, n_n7831, + n_n7757, n_n9174, n_n9432, n_n8678, n_n8024, n_n7806, n_n8996, n_n7918, + n_n8260, n_n9341, n_n9189, n_n9096, ndn3_30, n_n7775, n_n7693, nen3_16, + n_n7643, n_n8941, n_n8042, n_n8681, n_n8659, n_n9110, n_n9573, n_n8951, + n_n9589, n_n9387, n_n8279, n_n7790, n_n8406, n_n8582, n_n7911, n_n7474, + n_n8466, n_n6984, n_n7760, n_n7847, n_n9559, n_n7362, n_n9300, n_n9550, + n_n9492, n_n8777, n_n7764, n_n7826, n_n7777, n_n7824, n_n8173, n_n7498, + n_n9148, n_n8753, n_n8772, n_n8049, n_n9362, ndn1_4, n_n9561, n_n9004, + n_n8203, n_n8153, n_n9263, n_n8369, n_n9331, n_n7454, ndn3_7, n_n7527, + n_n9036, n_n7875, n_n8697, n_n9497, n_n7291, nsr3_13, nsr3_38, n_n8240, + n_n7703, n_n9282, n_n8237, n_n8935, n_n9244, n_n8648, n_n8235, n_n8611, + n_n9045, n_n9334, n_n8572, n_n9491, n_n9134, n_n9555, n_n9336, n_n7050, + n_n9346, n_n7140, n_n7681, n_n6948, n_n8549, ndn3_19, ndn3_28, n_n7102, + n_n8093, n_n9041, n_n8381, n_n8810, nen3_36, n_n9047, n_n9333, n_n7736, + n_n7820, n_n8986, n_n8891, n_n8000, n_n7968, n_n8750, n_n9558, n_n9368, + n_n8519, n_n6956, n_n8298, n_n9397, n_n7017, n_n8638, n_n9552, n_n8964, + n_n8016, n_n7603, n_n7696, n_n8589, n_n9337, n_n9132, n_n8652, n_n8707, + n_n9407, n_n9044, n_n8808, nsr3_30, n_n8274, n_n8615, n_n8238, n_n7854, + n_n8649, n_n8236, n_n8269, n_n9592, n_n8022, n_n8744, n_n8529, n_n7967, + n_n9487, n_n8685, n_n9531, n_n9510, n_n7771, n_n8480, n_n8543, n_n7789, + ndn3_11, ndn3_15, ndn3_21, n_n7584, n_n8354, n_n6952, n_n8864, n_n7930, + n_n7962, n_n7929, n_n9316, n_n9102, n_n7308, n_n7657, n_n9264, n_n8760, + n_n6912, n_n7887, n_n8911, n_n7952, n_n8704, n_n7876, n_n9596, n_n8430, + n_n9019, n_n7699, n_n7375, n_n7936, n_n8340, n_n8809, n_n6961, n_n9429, + n_n7743, n_n8980, n_n7582, n_n8968, n_n9371, n_n8741, n_n9502, n_n9373, + n_n9248, n_n7822, n_n9054, n_n8273, n_n6937, n_n9342, n_n9325, n_n9609, + n_n9623, n_n9470, n_n7570, n_n9310, n_n9366, n_n7181, n_n8739, n_n8939, + n_n7256, n_n8983, n_n7487, n_n9268, n_n8906, n_n7988, n_n9181, n_n8725, + n_n8626, ndn3_27, n_n8210, n_n7415, n_n8900, nen3_19, n_n8762, n_n8512, + n_n8095, n_n8982, n_n7387, n_n9494, n_n7689, n_n7835, n_n9157, n_n8552, + n_n7381, n_n9446, n_n8633, n_n7684, n_n7310, n_n8402, n_n9315, n_n7950, + n_n8504, n_n8456, n_n7514, n_n7315, n_n9476, n_n8276, n_n8833, n_n7923, + n_n9395, n_n9512, n_n9319, nsr3_35, n_n7154, n_n9495, n_n9137, n_n8854, + n_n9183, n_n9323, n_n9349, n_n7896, n_n8073, n_n8970, n_n9314, n_n8486, + n_n7246, n_n7866, n_n9599, n_n7635, n_n8984, n_n7360, n_n8794, n_n9108, + n_n9286, ndn3_12, ndn3_16, n_n7708, n_n7807, n_n7650, n_n7947, n_n9500, + n_n7734, n_n8464, n_n7659, n_n7630, n_n7756, n_n8691, n_n9176, n_n9327, + n_n7995, n_n7395, n_n7878, n_n7507, n_n7959, n_n7825, n_n8009, n_n8281, + n_n7685, n_n8106, n_n7687, n_n7766, n_n7880, n_n8961, n_n8014, n_n9278, + n_n9087, n_n9182, n_n7852, n_n9324, nak3_13, n_n9416, nsr3_14, n_n8603, + n_n7026, n_n8856, n_n8272, n_n9312, n_n7985, n_n8312, n_n7231, n_n9396, + n_n8801, n_n8683, ndn3_39, n_n8245, n_n9458, n_n9302, n_n7392, n_n6963, + n_n7808, n_n7225, n_n7817, n_n8201, n_n7793, n_n8177, n_n8389, n_n9440, + n_n7683, n_n7761, n_n7667, n_n7980, n_n7509, n_n7813, n_n8396, n_n9535, + n_n7209, n_n7003, n_n7695, n_n7624, n_n8791, n_n7374, n_n7429, n_n7944, + n_n9266, n_n8100, n_n6988, n_n6986, n_n8933, n_n7117, n_n9043, n_n8241, + n_n9219, n_n8198, n_n8081, n_n8575, n_n8710, n_n7622, n_n7966, n_n7885, + n_n7033, ndn3_34, n_n9186, ndn3_50, n_n7879, n_n7019, n_n9171, n_n7261, + n_n8223, n_n8989, n_n7993, n_n7845, n_n8253, n_n8889, n_n7809, n_n8918, + n_n8515, n_n7933, n_n8075, n_n7338, n_n8104, n_n8171, n_n9059, n_n9023, + n_n7692, n_n9441, n_n6920, n_n8831, n_n8441, n_n9576, n_n9252, n_n9363, + ndn3_4, n_n9247, n_n7561, n_n8923, n_n7978, n_n8978, n_n9499, n_n8713, + n_n8944, n_n8239, n_n7652, n_n9042, n_n8530, n_n9271, n_n9318, n_n7706, + n_n7964, n_n8222, n_n8898, n_n7976, n_n7649, n_n7604, n_n7961, n_n7424, + n_n7476, n_n9259, n_n9309, n_n9161, n_n8436, n_n9121, n_n8061, n_n8004, + n_n9360, n_n9205, n_n8392, n_n9034, n_n8375, n_n8328, n_n9298, n_n7598, + n_n8506, pdn, n_n7737, n_n7420, n_n9291, n_n7946, n_n8584, n_n9308, + n_n9403, n_n7284, n_n9270, n_n7390, n_n9351, n_n6968, n_n8668, n_n9605, + n_n7013, n_n9626, n_n8200, n_n9028, n_n8803, n_n9570, n_n8366, n_n9050, + n_n8650, n_n8574, n_n7276, n_n9212, n_n8384, ndn3_35, n_n8449, ndn3_46, + n_n7554, n_n8743, n_n8277, n_n9359, n_n8425, n_n9104, n_n9221, n_n9448, + n_n9537, n_n8003, n_n7467, n_n8233, n_n7932, n_n8064, n_n9162, n_n7971, + n_n8055, n_n7711, n_n8256, n_n7925, n_n7762, n_n7668, n_n7914, n_n7873, + n_n7849, n_n9421, n_n7626, n_n7848, n_n8263, n_n9100, n_n9393, n_n9591, + n_n7588, n_n9123, n_n9159, n_n9128, n_n8045, n_n7728, n_n8929, n_n7739, + n_n9355, n_n9394, n_n8470, n_n8571, n_n8796, ndn3_36, n_n7990, n_n8781, + n_n8817, n_n9160, n_n9092, n_n8513, n_n8213, n_n8581, n_n9284, n_n7837, + n_n8224, n_n9203, n_n7655, n_n8946, n_n7052, n_n9615, n_n8473, n_n7741, + n_n9460, n_n7912, n_n7606, n_n9021, n_n7781, n_n7810, n_n7108, n_n7697, + n_n7642, n_n9595, n_n7694, n_n8221, n_n7600, n_n7935, n_n9230, n_n7701, + n_n7510, n_n7627, n_n8502, n_n8516, n_n7913, n_n9320, n_n7411, n_n9129, + n_n9053, n_n7069, n_n8617, n_n7242, n_n8230, n_n9294, n_n8249, n_n8972, + n_n7074, n_n7493, n_n8290, n_n8821, n_n7769, n_n7491, n_n9600, n_n9317, + n_n8047, n_n9629, n_n9126, n_n9508, n_n9155, n_n8528, ndn3_37, ndn3_42, + n_n9358, n_n8185, nen3_28, n_n8839, n_n7903, n_n9139, n_n9075, n_n9439, + n_n9353, n_n7665, n_n8798, n_n7146, n_n7890, n_n7176, n_n8477, n_n8514, + n_n8636, n_n7183, n_n8657, n_n9493, n_n7969, n_n9255, n_n8535, n_n8619, + n_n8909, n_n7744, n_n9119, n_n7827, n_n8916, n_n8729, n_n9011, n_n8779, + n_n6980, n_n7715, n_n9067, n_n9164, n_n7402, n_n8938, n_n9046, n_n8789, + n_n9390, n_n7768, n_n9136, n_n8670, n_n8644, n_n9178, n_n8188, n_n7083, + n_n9344, n_n7366, n_n8361, n_n9228, n_n9402, n_n8510, n_n8881, n_n9404, + n_n9424, n_n9031, nsr3_37, n_n8197, n_n8468, n_n7121, n_n7511, ndn3_44, + n_n9322, n_n7682, n_n9603, nlc1_2, n_n8408, n_n8577, n_n7079, n_n8828, + n_n9340, n_n8586, n_n7901, n_n8628, n_n8869, n_n7710, n_n8993, n_n9586, + n_n8852, n_n8583, n_n8011, n_n7717, n_n8326, n_n9163, n_n8344, n_n8296, + n_n8116, n_n8267, n_n7686, n_n9061, n_n9338, n_n7688, n_n9081, n_n6910, + n_n8727, n_n7674, n_n7330, n_n8966, n_n7843, n_n8847, n_n9376, n_n7553, + n_n9292, n_n7464, n_n8146, n_n8439, n_n9498, n_n8118, n_n9452, n_n9239, + n_n9237, n_n9488, ndn3_2, n_n9522, n_n9313, n_n7435, n_n8665, n_n9593, + n_n8303, n_n7022, n_n9173, n_n9261, n_n7150, n_n9455, n_n8371, nsr3_20, + n_n8271, n_n9542, n_n7444, ndn3_40, n_n7130, n_n9347, n_n8102, n_n9225, + n_n8462, n_n8088, n_n9026, n_n9289, n_n7661, n_n8108, n_n8921, n_n7859, + n_n7732, n_n7956, n_n9520, n_n7666, n_n7678, n_n7846, n_n8280, n_n8841, + n_n7336, n_n8226, n_n8151, n_n7644, n_n8770, n_n8423, n_n7763, n_n9525, + n_n8033, n_n7881, n_n7815, n_n9232, n_n7792, n_n9563, n_n8672, n_n7346, + n_n7949, n_n8756, n_n8641, n_n8192, n_n8058, n_n8561, n_n9306, n_n9165, + n_n8850, n_n9210, ndn2_2, n_n7342, n_n8051, n_n7136, n_n9348, n_n9006, + n_n7653, n_n7905, n_n9166, n_n7065, n_n9490, n_n7024, n_n7586, n_n8416, + n_n8937, n_n8141, n_n7853, n_n8121, n_n9604, n_n9496, n_n8195, n_n9516, + n_n9077, n_n9436, n_n9051, n_n7664, n_n8419, n_n7874, n_n9133, n_n9392, + n_n7770, ndn3_32, n_n7601, n_n8206, n_n7927, n_n9606, n_n7111, n_n9269, + ndn3_38, n_n7886, n_n9179, n_n9357, n_n9594, n_n7628, n_n8454, ndn3_20, + n_n9505, nen3_34, n_n9632, n_n7076, n_n9262, n_n9048, n_n9578, n_n8135, + ndn3_26, n_n7500, n_n6974, n_n8605, n_n9296, n_n7156, n_n7920, n_n8895, + n_n8991, n_n8139, n_n9275, n_n7203, n_n9590, n_n7344, n_n6976, n_n7629, + ndn3_14, n_n7862, n_n9013, n_n7288, n_n8078, n_n7334, n_n7704, n_n7788, + n_n8526, n_n9556, n_n9345, n_n8447, n_n7485, n_n8570, n_n7453, n_n7928, + n_n8646, n_n9405, n_n8948, n_n9131, n_n8216, n_n9177, n_n7844, n_n8811, + n_n9145, n_n8428, n_n8858, n_n8580; + wire n4845, n4846, n4847, n4848, n4849_1, n4850, n4851, n4852, n4853, + n4854_1, n4855, n4856, n4857, n4858, n4859_1, n4860, n4861, n4862, + n4863, n4864_1, n4865, n4866, n4867, n4868, n4869_1, n4870, n4871, + n4872, n4873, n4874_1, n4875, n4876, n4877, n4878, n4879_1, n4880, + n4881, n4882, n4883, n4884_1, n4885, n4886, n4887, n4888, n4889_1, + n4890, n4891, n4892, n4893, n4894_1, n4895, n4896, n4897, n4898, + n4899_1, n4900, n4901, n4902, n4903, n4904_1, n4905, n4906, n4907, + n4908, n4909_1, n4910, n4911, n4912, n4913, n4914_1, n4915, n4916, + n4917, n4918, n4919_1, n4920, n4921, n4922, n4923, n4924_1, n4925, + n4926, n4927, n4928, n4929_1, n4930, n4931, n4932, n4933, n4934_1, + n4935, n4936, n4937, n4938, n4939_1, n4940, n4941, n4942, n4943, + n4944_1, n4945, n4946, n4947, n4948, n4949_1, n4950, n4951, n4952, + n4953, n4954_1, n4955, n4956, n4957, n4958, n4959_1, n4960, n4961, + n4962, n4963, n4964_1, n4965, n4966, n4967, n4968, n4969_1, n4970, + n4971, n4972, n4973, n4974_1, n4975, n4976, n4977, n4978, n4979_1, + n4980, n4981, n4982, n4983, n4984_1, n4985, n4986, n4987, n4988, + n4989_1, n4990, n4991, n4992, n4993, n4994_1, n4995, n4996, n4997, + n4998, n4999_1, n5000, n5001, n5002, n5003, n5004_1, n5005, n5006, + n5007, n5008, n5009_1, n5010, n5011, n5012, n5013, n5014_1, n5015, + n5016, n5017, n5018, n5019_1, n5020, n5021, n5022, n5023, n5024_1, + n5025, n5026, n5027, n5028, n5029_1, n5030, n5031, n5032, n5033, + n5034_1, n5035, n5036, n5037, n5038, n5039_1, n5040, n5041, n5042, + n5043, n5044_1, n5045, n5046, n5047, n5048, n5049_1, n5050, n5051, + n5052, n5053, n5054_1, n5055, n5056, n5057, n5058, n5059_1, n5060, + n5061, n5062, n5063, n5064_1, n5065, n5066, n5067, n5068, n5069_1, + n5070, n5071, n5072, n5073, n5074_1, n5075, n5076, n5077, n5078, + n5079_1, n5080, n5081, n5082, n5083, n5084_1, n5085, n5086, n5087, + n5088, n5089_1, n5090, n5091, n5092, n5093, n5094_1, n5095, n5096, + n5097, n5098, n5099_1, n5100, n5101, n5102, n5103, n5104_1, n5105, + n5106, n5107, n5108, n5109_1, n5110, n5111, n5112, n5113, n5114_1, + n5115, n5116, n5117, n5118, n5119_1, n5120, n5121, n5122, n5123, + n5124_1, n5125, n5126, n5127, n5128, n5129_1, n5130, n5131, n5132, + n5133, n5134_1, n5135, n5136, n5137, n5138, n5139_1, n5140, n5141, + n5142, n5143, n5144_1, n5145, n5146, n5147, n5148, n5149_1, n5150, + n5151, n5152, n5153, n5154_1, n5155, n5156, n5157, n5158, n5159_1, + n5160, n5161, n5162, n5163, n5164_1, n5165, n5166, n5167, n5168, + n5169_1, n5170, n5171, n5172, n5173, n5174_1, n5175, n5176, n5177, + n5178, n5179_1, n5180, n5181, n5182, n5183, n5184_1, n5185, n5186, + n5187, n5188, n5189_1, n5190, n5191, n5192, n5193, n5194_1, n5195, + n5196, n5197, n5198, n5199_1, n5200, n5201, n5202, n5203, n5204_1, + n5205, n5206, n5207, n5208, n5209_1, n5210, n5211, n5212, n5213, + n5214_1, n5215, n5216, n5217, n5218, n5219_1, n5220, n5221, n5222, + n5223, n5224_1, n5225, n5226, n5227, n5228, n5229_1, n5230, n5231, + n5232, n5233, n5234_1, n5235, n5236, n5237, n5238, n5239_1, n5240, + n5241, n5242, n5243, n5244_1, n5245, n5246, n5247, n5248, n5249_1, + n5250, n5251, n5252, n5253, n5254_1, n5255, n5256, n5257, n5258, + n5259_1, n5260, n5261, n5262, n5263, n5264_1, n5265, n5266, n5267, + n5268, n5269_1, n5270, n5271, n5272, n5273, n5274_1, n5275, n5276, + n5277, n5278, n5279_1, n5280, n5281, n5282, n5283, n5284_1, n5285, + n5286, n5287, n5288, n5289_1, n5290, n5291, n5292, n5293, n5294_1, + n5295, n5296, n5297, n5298, n5299_1, n5300, n5301, n5302, n5303, + n5304_1, n5305, n5306, n5307, n5308, n5309_1, n5310, n5311, n5312, + n5313, n5314_1, n5315, n5316, n5317, n5318, n5319_1, n5320, n5321, + n5322, n5323, n5324_1, n5325, n5326, n5327, n5328, n5329_1, n5330, + n5331, n5332, n5333, n5334_1, n5335, n5336, n5337, n5338, n5339_1, + n5340, n5341, n5342, n5343, n5344_1, n5345, n5346, n5347, n5348, + n5349_1, n5350, n5351, n5352, n5353, n5354_1, n5355, n5356, n5357, + n5358, n5359_1, n5360, n5361, n5362, n5363, n5364_1, n5365, n5366, + n5367, n5368, n5369_1, n5370, n5371, n5372, n5373, n5374_1, n5375, + n5376, n5377, n5378, n5379_1, n5380, n5381, n5382, n5383, n5384_1, + n5385, n5386, n5387, n5388, n5389_1, n5390, n5391, n5392, n5393, + n5394_1, n5395, n5396, n5397, n5398, n5399_1, n5400, n5401, n5402, + n5403, n5404_1, n5405, n5406, n5407, n5408, n5409_1, n5410, n5411, + n5412, n5413, n5414_1, n5415, n5416, n5417, n5418, n5419_1, n5420, + n5421, n5422, n5423, n5424_1, n5425, n5426, n5427, n5428, n5429_1, + n5430, n5431, n5432, n5433, n5434_1, n5435, n5436, n5437, n5438, + n5439_1, n5440, n5441, n5442, n5443, n5444_1, n5445, n5446, n5447, + n5448, n5449_1, n5450, n5451, n5452, n5453, n5454_1, n5455, n5456, + n5457, n5458, n5459_1, n5460, n5461, n5462, n5463, n5464_1, n5465, + n5466, n5467, n5468, n5469_1, n5470, n5471, n5472, n5473, n5474_1, + n5475, n5476, n5477, n5478, n5479_1, n5480, n5481, n5482, n5483, + n5484_1, n5485, n5486, n5487, n5488, n5489_1, n5490, n5491, n5492, + n5493, n5494_1, n5495, n5496, n5497, n5498, n5499_1, n5500, n5501, + n5502, n5503, n5504_1, n5505, n5506, n5507, n5508, n5509_1, n5510, + n5511, n5512, n5513, n5514_1, n5515, n5516, n5517, n5518, n5519_1, + n5520, n5521, n5522, n5523, n5524_1, n5525, n5526, n5527, n5528, + n5529_1, n5530, n5531, n5532, n5533, n5534_1, n5535, n5536, n5537, + n5538, n5539_1, n5540, n5541, n5542, n5543, n5544_1, n5545, n5546, + n5547, n5548, n5549_1, n5550, n5551, n5552, n5553, n5554_1, n5555, + n5556, n5557, n5558, n5559_1, n5560, n5561, n5562, n5563, n5564_1, + n5565, n5566, n5567, n5568, n5569_1, n5570, n5571, n5572, n5573, + n5574_1, n5575, n5576, n5577, n5578, n5579_1, n5580, n5581, n5582, + n5583, n5584_1, n5585, n5586, n5587, n5588, n5589_1, n5590, n5591, + n5592, n5593, n5594_1, n5595, n5596, n5597, n5598, n5599_1, n5600, + n5601, n5602, n5603, n5604_1, n5605, n5606, n5607, n5608, n5609_1, + n5610, n5611, n5612, n5613, n5614_1, n5615, n5616, n5617, n5618, + n5619_1, n5620, n5621, n5622, n5623, n5624_1, n5625, n5626, n5627, + n5628, n5629_1, n5630, n5631, n5632, n5633, n5634_1, n5635, n5636, + n5637, n5638, n5639_1, n5640, n5641, n5642, n5643, n5644_1, n5645, + n5646, n5647, n5648, n5649_1, n5650, n5651, n5652, n5653, n5654_1, + n5655, n5656, n5657, n5658, n5659_1, n5660, n5661, n5662, n5663, + n5664_1, n5665, n5666, n5667, n5668, n5669_1, n5670, n5671, n5672, + n5673, n5674_1, n5675, n5676, n5677, n5678, n5679_1, n5680, n5681, + n5682, n5683, n5684_1, n5685, n5686, n5687, n5688, n5689_1, n5690, + n5691, n5692, n5693, n5694_1, n5695, n5696, n5697, n5698, n5699_1, + n5700, n5701, n5702, n5703, n5704_1, n5705, n5706, n5707, n5708, + n5709_1, n5710, n5711, n5712, n5713, n5714_1, n5715, n5716, n5717, + n5718, n5719_1, n5720, n5721, n5722, n5723, n5724_1, n5725, n5726, + n5727, n5728, n5729_1, n5730, n5731, n5732, n5733, n5734_1, n5735, + n5736, n5737, n5738, n5739_1, n5740, n5741, n5742, n5743, n5744_1, + n5745, n5746, n5747, n5748, n5749_1, n5750, n5751, n5752, n5753, + n5754_1, n5755, n5756, n5757, n5758, n5759_1, n5760, n5761, n5762, + n5763, n5764_1, n5765, n5766, n5767, n5768, n5769_1, n5770, n5771, + n5772, n5773, n5774_1, n5775, n5776, n5777, n5778, n5779_1, n5780, + n5781, n5782, n5783, n5784_1, n5785, n5786, n5787, n5788, n5789_1, + n5790, n5791, n5792, n5793, n5794_1, n5795, n5796, n5797, n5798, + n5799_1, n5800, n5801, n5802, n5803, n5804_1, n5805, n5806, n5807, + n5808, n5809_1, n5810, n5811, n5812, n5813, n5814_1, n5815, n5816, + n5817, n5818, n5819_1, n5820, n5821, n5822, n5823, n5824_1, n5825, + n5826, n5827, n5828, n5829_1, n5830, n5831, n5832, n5833, n5834_1, + n5835, n5836, n5837, n5838, n5839_1, n5840, n5841, n5842, n5843, + n5844_1, n5845, n5846, n5847, n5848, n5849_1, n5850, n5851, n5852, + n5853, n5854_1, n5855, n5856, n5857, n5858, n5859_1, n5860, n5861, + n5862, n5863, n5864_1, n5865, n5866, n5867, n5868, n5869_1, n5870, + n5871, n5872, n5873, n5874_1, n5875, n5876, n5877, n5878, n5879_1, + n5880, n5881, n5882, n5883, n5884_1, n5885, n5886, n5887, n5888, + n5889_1, n5890, n5891, n5892, n5893, n5894_1, n5895, n5896, n5897, + n5898, n5899_1, n5900, n5901, n5902, n5903, n5904_1, n5905, n5906, + n5907, n5908, n5909_1, n5910, n5911, n5912, n5913, n5914_1, n5915, + n5916, n5917, n5918, n5919_1, n5920, n5921, n5922, n5923, n5924_1, + n5925, n5926, n5927, n5928, n5929_1, n5930, n5931, n5932, n5933, + n5934_1, n5935, n5936, n5937, n5938, n5939_1, n5940, n5941, n5942, + n5943, n5944_1, n5945, n5946, n5947, n5948, n5949_1, n5950, n5951, + n5952, n5953, n5954_1, n5955, n5956, n5957, n5958, n5959_1, n5960, + n5961, n5962, n5963, n5964_1, n5965, n5966, n5967, n5968, n5969_1, + n5970, n5971, n5972, n5973, n5974_1, n5975, n5976, n5977, n5978, + n5979_1, n5980, n5981, n5982, n5983, n5984_1, n5985, n5986, n5987, + n5988, n5989_1, n5990, n5991, n5992, n5993, n5994_1, n5995, n5996, + n5997, n5998, n5999_1, n6000, n6001, n6002, n6003, n6004_1, n6005, + n6006, n6007, n6008, n6009_1, n6010, n6011, n6012, n6013, n6014_1, + n6015, n6016, n6017, n6018, n6019_1, n6020, n6021, n6022, n6023, + n6024_1, n6025, n6026, n6027, n6028, n6029_1, n6030, n6031, n6032, + n6033, n6034_1, n6035, n6036, n6037, n6038, n6039_1, n6040, n6041, + n6042, n6043, n6044_1, n6045, n6046, n6047, n6048, n6049_1, n6050, + n6051, n6052, n6053, n6054_1, n6055, n6056, n6057, n6058, n6059_1, + n6060, n6061, n6062, n6063, n6064_1, n6065, n6066, n6067, n6068, + n6069_1, n6070, n6071, n6072, n6073, n6074_1, n6075, n6076, n6077, + n6078, n6079_1, n6080, n6081, n6082, n6083, n6084_1, n6085, n6086, + n6087, n6088, n6089_1, n6090, n6091, n6092, n6093, n6094_1, n6095, + n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, + n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, + n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, + n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, + n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, + n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, + n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, + n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, + n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, + n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, + n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, + n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, + n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, + n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, + n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, + n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, + n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, + n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, + n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, + n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, + n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, + n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, + n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, + n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, + n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, + n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, + n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, + n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, + n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, + n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, + n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, + n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, + n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, + n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, + n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, + n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, + n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465, + n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475, + n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485, + n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495, + n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505, + n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515, + n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525, + n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535, + n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545, + n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555, + n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565, + n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575, + n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585, + n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595, + n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605, + n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615, + n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625, + n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635, + n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645, + n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655, + n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665, + n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675, + n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685, + n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, + n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, + n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, + n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, + n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, + n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, + n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, + n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, + n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, + n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, + n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, + n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, + n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, + n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, + n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, + n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, + n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, + n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, + n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, + n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, + n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, + n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, + n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, + n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, + n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, + n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, + n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, + n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, + n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, + n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, + n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, + n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, + n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, + n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, + n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, + n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, + n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, + n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065, + n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075, + n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085, + n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095, + n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105, + n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115, + n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125, + n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135, + n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145, + n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155, + n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165, + n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175, + n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185, + n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195, + n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205, + n7206, n7207, n7208, n7209, n7210, n7211, n7212, n491, n496, n501, + n506, n511, n516, n521, n526, n531, n536, n541, n546, n551, n556, n561, + n566, n571, n576, n581, n586, n591, n596, n601, n606, n611, n616, n621, + n626, n631, n636, n641, n646, n651, n656, n661, n666, n671, n676, n681, + n686, n691, n696, n701, n706, n711, n716, n721, n726, n731, n736, n741, + n746, n751, n756, n761, n766, n771, n776, n781, n786, n791, n796, n801, + n806, n811, n816, n821, n826, n831, n835, n840, n845, n850, n855, n860, + n865, n870, n875, n880, n885, n890, n895, n900, n905, n910, n915, n920, + n925, n930, n935, n940, n945, n950, n955, n960, n965, n970, n975, n980, + n985, n990, n995, n1000, n1005, n1010, n1015, n1020, n1025, n1030, + n1035, n1040, n1045, n1050, n1055, n1060, n1065, n1070, n1075, n1080, + n1085, n1090, n1095, n1100, n1105, n1110, n1115, n1120, n1125, n1130, + n1135, n1140, n1145, n1150, n1155, n1160, n1165, n1170, n1175, n1180, + n1185, n1190, n1195, n1200, n1205, n1210, n1215, n1220, n1225, n1230, + n1235, n1240, n1245, n1250, n1255, n1260, n1265, n1270, n1275, n1280, + n1285, n1290, n1295, n1300, n1305, n1310, n1315, n1320, n1325, n1330, + n1335, n1340, n1345, n1350, n1355, n1360, n1365, n1370, n1375, n1380, + n1385, n1390, n1395, n1400, n1405, n1410, n1415, n1420, n1425, n1430, + n1435, n1440, n1445, n1450, n1455, n1460, n1465, n1470, n1475, n1480, + n1485, n1490, n1495, n1500, n1505, n1510, n1515, n1520, n1525, n1530, + n1535, n1540, n1545, n1550, n1555, n1560, n1565, n1570, n1575, n1580, + n1585, n1590, n1595, n1600, n1605, n1610, n1615, n1620, n1625, n1630, + n1635, n1640, n1645, n1650, n1655, n1660, n1665, n1670, n1675, n1680, + n1685, n1690, n1695, n1700, n1705, n1710, n1715, n1720, n1725, n1730, + n1735, n1740, n1745, n1750, n1755, n1760, n1765, n1770, n1775, n1780, + n1785, n1790, n1795, n1800, n1805, n1810, n1815, n1820, n1825, n1830, + n1835, n1840, n1845, n1850, n1855, n1860, n1865, n1870, n1875, n1880, + n1885, n1890, n1895, n1900, n1905, n1910, n1915, n1920, n1925, n1930, + n1935, n1940, n1945, n1950, n1955, n1960, n1965, n1970, n1975, n1980, + n1985, n1990, n1995, n2000, n2005, n2010, n2015, n2020, n2025, n2030, + n2035, n2040, n2045, n2050, n2055, n2060, n2065, n2070, n2075, n2080, + n2085, n2090, n2095, n2100, n2105, n2110, n2115, n2120, n2125, n2130, + n2135, n2140, n2145, n2150, n2155, n2160, n2165, n2170, n2175, n2180, + n2185, n2190, n2195, n2200, n2205, n2210, n2215, n2220, n2225, n2230, + n2235, n2240, n2245, n2250, n2255, n2260, n2265, n2270, n2275, n2280, + n2285, n2290, n2295, n2300, n2305, n2310, n2315, n2320, n2325, n2330, + n2335, n2340, n2345, n2350, n2355, n2360, n2365, n2370, n2375, n2380, + n2385, n2390, n2395, n2400, n2405, n2410, n2415, n2420, n2425, n2430, + n2435, n2440, n2445, n2450, n2455, n2460, n2465, n2470, n2475, n2480, + n2485, n2490, n2495, n2500, n2505, n2510, n2515, n2520, n2525, n2530, + n2535, n2540, n2545, n2550, n2555, n2560, n2565, n2570, n2575, n2580, + n2585, n2590, n2595, n2600, n2605, n2610, n2615, n2620, n2625, n2630, + n2635, n2640, n2645, n2650, n2655, n2660, n2665, n2670, n2675, n2680, + n2685, n2690, n2695, n2700, n2705, n2710, n2715, n2720, n2725, n2730, + n2735, n2740, n2745, n2750, n2755, n2760, n2765, n2770, n2775, n2780, + n2785, n2790, n2795, n2800, n2805, n2810, n2815, n2820, n2825, n2830, + n2835, n2840, n2845, n2850, n2855, n2860, n2865, n2870, n2875, n2880, + n2885, n2890, n2895, n2900, n2905, n2910, n2915, n2920, n2925, n2930, + n2935, n2940, n2945, n2950, n2955, n2960, n2965, n2970, n2975, n2980, + n2985, n2990, n2995, n3000, n3005, n3010, n3015, n3020, n3025, n3030, + n3035, n3040, n3045, n3050, n3055, n3060, n3065, n3070, n3075, n3080, + n3085, n3090, n3095, n3100, n3105, n3110, n3115, n3120, n3125, n3130, + n3135, n3140, n3145, n3150, n3155, n3160, n3165, n3170, n3175, n3180, + n3185, n3190, n3195, n3200, n3205, n3210, n3215, n3220, n3225, n3230, + n3235, n3240, n3245, n3250, n3255, n3260, n3265, n3270, n3275, n3280, + n3285, n3290, n3295, n3300, n3305, n3310, n3315, n3320, n3325, n3330, + n3335, n3340, n3345, n3350, n3355, n3360, n3365, n3370, n3375, n3380, + n3385, n3390, n3395, n3400, n3405, n3410, n3415, n3420, n3425, n3430, + n3435, n3440, n3445, n3450, n3455, n3460, n3465, n3470, n3475, n3480, + n3485, n3490, n3495, n3500, n3505, n3510, n3515, n3520, n3525, n3530, + n3535, n3540, n3545, n3550, n3555, n3560, n3565, n3570, n3575, n3580, + n3585, n3590, n3595, n3600, n3605, n3610, n3615, n3620, n3625, n3630, + n3635, n3640, n3645, n3650, n3655, n3660, n3665, n3670, n3675, n3680, + n3685, n3690, n3695, n3700, n3705, n3710, n3715, n3720, n3725, n3730, + n3735, n3740, n3745, n3750, n3755, n3760, n3765, n3770, n3775, n3780, + n3785, n3790, n3795, n3800, n3805, n3810, n3815, n3820, n3825, n3830, + n3835, n3840, n3845, n3850, n3855, n3860, n3865, n3870, n3875, n3880, + n3885, n3890, n3895, n3900, n3905, n3910, n3915, n3920, n3925, n3930, + n3935, n3940, n3945, n3950, n3955, n3960, n3965, n3970, n3975, n3980, + n3985, n3990, n3995, n4000, n4005, n4009, n4014, n4019, n4024, n4029, + n4034, n4039, n4044, n4049, n4054, n4059, n4064, n4069, n4074, n4079, + n4084, n4089, n4094, n4099, n4104, n4109, n4114, n4119, n4124, n4129, + n4134, n4139, n4144, n4149, n4154, n4159, n4164, n4169, n4174, n4179, + n4184, n4189, n4194, n4199, n4204, n4209, n4214, n4219, n4224, n4229, + n4234, n4239, n4244, n4249, n4254, n4259, n4264, n4269, n4274, n4279, + n4284, n4289, n4294, n4299, n4304, n4309, n4314, n4319, n4324, n4329, + n4334, n4339, n4344, n4349, n4354, n4359, n4364, n4369, n4374, n4379, + n4384, n4389, n4394, n4399, n4404, n4409, n4414, n4419, n4424, n4429, + n4434, n4439, n4444, n4449, n4454, n4459, n4464, n4469, n4474, n4479, + n4484, n4489, n4494, n4499, n4504, n4509, n4514, n4519, n4524, n4529, + n4534, n4539, n4544, n4549, n4554, n4559, n4564, n4569, n4574, n4579, + n4584, n4589, n4594, n4599, n4604, n4609, n4614, n4619, n4624, n4629, + n4634, n4639, n4644, n4649, n4654, n4659, n4664, n4669, n4674, n4679, + n4684, n4689, n4694, n4699, n4704, n4709, n4714, n4719, n4724, n4729, + n4734, n4739, n4744, n4749, n4754, n4759, n4764, n4769, n4774, n4779, + n4784, n4789, n4794, n4799, n4804, n4809, n4814, n4819, n4824, n4829, + n4834, n4839, n4844, n4849, n4854, n4859, n4864, n4869, n4874, n4879, + n4884, n4889, n4894, n4899, n4904, n4909, n4914, n4919, n4924, n4929, + n4934, n4939, n4944, n4949, n4954, n4959, n4964, n4969, n4974, n4979, + n4984, n4989, n4994, n4999, n5004, n5009, n5014, n5019, n5024, n5029, + n5034, n5039, n5044, n5049, n5054, n5059, n5064, n5069, n5074, n5079, + n5084, n5089, n5094, n5099, n5104, n5109, n5114, n5119, n5124, n5129, + n5134, n5139, n5144, n5149, n5154, n5159, n5164, n5169, n5174, n5179, + n5184, n5189, n5194, n5199, n5204, n5209, n5214, n5219, n5224, n5229, + n5234, n5239, n5244, n5249, n5254, n5259, n5264, n5269, n5274, n5279, + n5284, n5289, n5294, n5299, n5304, n5309, n5314, n5319, n5324, n5329, + n5334, n5339, n5344, n5349, n5354, n5359, n5364, n5369, n5374, n5379, + n5384, n5389, n5394, n5399, n5404, n5409, n5414, n5419, n5424, n5429, + n5434, n5439, n5444, n5449, n5454, n5459, n5464, n5469, n5474, n5479, + n5484, n5489, n5494, n5499, n5504, n5509, n5514, n5519, n5524, n5529, + n5534, n5539, n5544, n5549, n5554, n5559, n5564, n5569, n5574, n5579, + n5584, n5589, n5594, n5599, n5604, n5609, n5614, n5619, n5624, n5629, + n5634, n5639, n5644, n5649, n5654, n5659, n5664, n5669, n5674, n5679, + n5684, n5689, n5694, n5699, n5704, n5709, n5714, n5719, n5724, n5729, + n5734, n5739, n5744, n5749, n5754, n5759, n5764, n5769, n5774, n5779, + n5784, n5789, n5794, n5799, n5804, n5809, n5814, n5819, n5824, n5829, + n5834, n5839, n5844, n5849, n5854, n5859, n5864, n5869, n5874, n5879, + n5884, n5889, n5894, n5899, n5904, n5909, n5914, n5919, n5924, n5929, + n5934, n5939, n5944, n5949, n5954, n5959, n5964, n5969, n5974, n5979, + n5984, n5989, n5994, n5999, n6004, n6009, n6014, n6019, n6024, n6029, + n6034, n6039, n6044, n6049, n6054, n6059, n6064, n6069, n6074, n6079, + n6084, n6089, n6094; + assign psv39_8_8_ = n_n7154 ? n_n9366 : tin_psv39_8_8_; + assign psv39_0_0_ = n_n6986 ? n_n9424 : tin_psv39_0_0_; + assign psv13_5_5_ = n_n7561 ? n_n9004 : tin_psv13_5_5_; + assign psv2_13_13_ = n_n8245 ? n_n9169 : tin_psv2_13_13_; + assign psv2_8_8_ = n_n8121 ? n_n8303 : tin_psv2_8_8_; + assign psv38_2_2_ = n_n7146 ? n_n6910 : tin_psv38_2_2_; + assign psv33_5_5_ = n_n7050 ? n_n9148 : tin_psv33_5_5_; + assign psv26_6_6_ = n_n7622 ? n_n6980 : tin_psv26_6_6_; + assign psv2_9_9_ = n_n8918 ? n_n7522 : tin_psv2_9_9_; + assign psv18_2_2_ = n_n7905 ? n_n8801 : tin_psv18_2_2_; + assign psv39_9_9_ = n_n7717 ? n_n7332 : tin_psv39_9_9_; + assign psv39_1_1_ = n_n8946 ? n_n8430 : tin_psv39_1_1_; + assign psv13_6_6_ = n_n8568 ? n_n7179 : tin_psv13_6_6_; + assign psv2_6_6_ = n_n7150 ? n_n7022 : tin_psv2_6_6_; + assign psv38_3_3_ = n_n7491 ? n_n7203 : tin_psv38_3_3_; + assign psv33_6_6_ = n_n8243 ? n_n7344 : tin_psv33_6_6_; + assign psv26_13_13_ = n_n7381 ? n_n7500 : tin_psv26_13_13_; + assign psv26_12_12_ = n_n7798 ? n_n8488 : tin_psv26_12_12_; + assign psv26_7_7_ = n_n7362 ? n_n8702 : tin_psv26_7_7_; + assign psv2_7_7_ = n_n8392 ? n_n8061 : tin_psv2_7_7_; + assign psv18_3_3_ = n_n7079 ? n_n7498 : tin_psv18_3_3_; + assign psv39_2_2_ = n_n7978 ? n_n7726 : tin_psv39_2_2_; + assign psv33_12_12_ = n_n7493 ? n_n8369 : tin_psv33_12_12_; + assign psv33_11_11_ = n_n8665 ? n_n7923 : tin_psv33_11_11_; + assign psv33_10_10_ = n_n9123 ? n_n9483 : tin_psv33_10_10_; + assign psv13_7_7_ = n_n9228 ? n_n7546 : tin_psv13_7_7_; + assign psv2_10_10_ = n_n7244 ? n_n8681 : tin_psv2_10_10_; + assign psv38_4_4_ = n_n7052 ? n_n7674 : tin_psv38_4_4_; + assign psv39_10_10_ = n_n7330 ? n_n8644 : tin_psv39_10_10_; + assign psv33_7_7_ = n_n7140 ? n_n7843 : tin_psv33_7_7_; + assign psv26_15_15_ = n_n8389 ? n_n9026 : tin_psv26_15_15_; + assign psv26_14_14_ = n_n9200 ? n_n7392 : tin_psv26_14_14_; + assign psv26_8_8_ = n_n6937 ? n_n7581 : tin_psv26_8_8_; + assign psv26_0_0_ = n_n7246 ? n_n7017 : tin_psv26_0_0_; + assign psv13_12_12_ = n_n8055 ? n_n8895 : tin_psv13_12_12_; + assign psv13_11_11_ = n_n7336 ? n_n9548 : tin_psv13_11_11_; + assign psv18_4_4_ = n_n9006 ? n_n9432 : tin_psv18_4_4_; + assign psv39_3_3_ = n_n7507 ? n_n7108 : tin_psv39_3_3_; + assign psv13_8_8_ = n_n7261 ? n_n7271 : tin_psv13_8_8_; + assign psv13_0_0_ = n_n7176 ? n_n7775 : tin_psv13_0_0_; + assign psv38_5_5_ = n_n8655 ? n_n7256 : tin_psv38_5_5_; + assign psv33_8_8_ = n_n9306 ? n_n7288 : tin_psv33_8_8_; + assign psv33_0_0_ = n_n8672 ? n_n8486 : tin_psv33_0_0_; + assign psv26_9_9_ = n_n7310 ? n_n7360 : tin_psv26_9_9_; + assign psv26_1_1_ = n_n7699 ? n_n7231 : tin_psv26_1_1_; + assign psv13_10_10_ = n_n6956 ? n_n7976 : tin_psv13_10_10_; + assign psv18_5_5_ = n_n7903 ? n_n7715 : tin_psv18_5_5_; + assign psv39_4_4_ = n_n7117 ? n_n7121 : tin_psv39_4_4_; + assign psv13_9_9_ = n_n7944 ? n_n9376 : tin_psv13_9_9_; + assign psv13_1_1_ = n_n7013 ? n_n8589 : tin_psv13_1_1_; + assign psv2_15_15_ = n_n6948 ? n_n8102 : tin_psv2_15_15_; + assign psv2_11_11_ = n_n6952 ? n_n6963 : tin_psv2_11_11_; + assign psv2_0_0_ = n_n7024 ? n_n8371 : tin_psv2_0_0_; + assign psv38_14_14_ = n_n8454 ? n_n7174 : tin_psv38_14_14_; + assign psv38_12_12_ = n_n8605 ? n_n7402 : tin_psv38_12_12_; + assign psv38_10_10_ = n_n7181 ? n_n7284 : tin_psv38_10_10_; + assign psv38_6_6_ = n_n7556 ? n_n7514 : tin_psv38_6_6_; + assign psv18_15_15_ = n_n7019 ? n_n7074 : tin_psv18_15_15_; + assign psv18_13_13_ = n_n7415 ? n_n7148 : tin_psv18_13_13_; + assign psv18_11_11_ = n_n8195 ? n_n8439 : tin_psv18_11_11_; + assign psv33_9_9_ = n_n8725 ? n_n9278 : tin_psv33_9_9_; + assign psv33_1_1_ = n_n7635 ? n_n8091 : tin_psv33_1_1_; + assign psv26_2_2_ = n_n7276 ? n_n7777 : tin_psv26_2_2_; + assign psv2_1_1_ = n_n7467 ? n_n7678 : tin_psv2_1_1_; + assign psv38_15_15_ = n_n8216 ? n_n8340 : tin_psv38_15_15_; + assign psv38_11_11_ = n_n7033 ? n_n7857 : tin_psv38_11_11_; + assign psv18_12_12_ = n_n8817 ? n_n9465 : tin_psv18_12_12_; + assign psv18_6_6_ = n_n8230 ? n_n7156 : tin_psv18_6_6_; + assign psv39_5_5_ = n_n8633 ? n_n8777 : tin_psv39_5_5_; + assign psv13_2_2_ = n_n8251 ? n_n7130 : tin_psv13_2_2_; + assign psv38_7_7_ = n_n8713 ? n_n8592 : tin_psv38_7_7_; + assign psv39_12_12_ = n_n9476 ? n_n8100 : tin_psv39_12_12_; + assign psv39_11_11_ = n_n7315 ? n_n7390 : tin_psv39_11_11_; + assign psv33_2_2_ = n_n7209 ? n_n7111 : tin_psv33_2_2_; + assign psv26_3_3_ = n_n7338 ? n_n8384 : tin_psv26_3_3_; + assign psv13_14_14_ = n_n7959 ? n_n7252 : tin_psv13_14_14_; + assign psv13_13_13_ = n_n8704 ? n_n6991 : tin_psv13_13_13_; + assign psv18_10_10_ = n_n8974 ? n_n8146 : tin_psv18_10_10_; + assign psv18_7_7_ = n_n7659 ? n_n8049 : tin_psv18_7_7_; + assign psv39_6_6_ = n_n8047 ? n_n8073 : tin_psv39_6_6_; + assign psv33_15_15_ = n_n7026 ? n_n8263 : tin_psv33_15_15_; + assign psv33_14_14_ = n_n6988 ? n_n9429 : tin_psv33_14_14_; + assign psv33_13_13_ = n_n8290 ? n_n7069 : tin_psv33_13_13_; + assign psv13_3_3_ = n_n7586 ? n_n8850 : tin_psv13_3_3_; + assign psv2_14_14_ = n_n8683 ? n_n7102 : tin_psv2_14_14_; + assign psv2_12_12_ = n_n7286 ? n_n8132 : tin_psv2_12_12_; + assign psv2_4_4_ = n_n7291 ? n_n8045 : tin_psv2_4_4_; + assign psv38_8_8_ = n_n6984 ? n_n9421 : tin_psv38_8_8_; + assign psv38_0_0_ = n_n8921 ? n_n8916 : tin_psv38_0_0_; + assign psv39_14_14_ = n_n8441 ? n_n9371 : tin_psv39_14_14_; + assign psv39_13_13_ = n_n8831 ? n_n7366 : tin_psv39_13_13_; + assign psv33_3_3_ = n_n7409 ? n_n7420 : tin_psv33_3_3_; + assign psv26_11_11_ = n_n7308 ? n_n8185 : tin_psv26_11_11_; + assign psv26_10_10_ = n_n9580 ? n_n8781 : tin_psv26_10_10_; + assign psv26_4_4_ = n_n8112 ? n_n8175 : tin_psv26_4_4_; + assign psv13_15_15_ = n_n8406 ? n_n9145 : tin_psv13_15_15_; + assign psv2_5_5_ = n_n9446 ? n_n7395 : tin_psv2_5_5_; + assign psv18_8_8_ = n_n7242 ? n_n8678 : tin_psv18_8_8_; + assign psv18_0_0_ = n_n7065 ? n_n7190 : tin_psv18_0_0_; + assign psv39_7_7_ = n_n7183 ? n_n7160 : tin_psv39_7_7_; + assign psv13_4_4_ = n_n9085 ? n_n9096 : tin_psv13_4_4_; + assign psv2_2_2_ = n_n8510 ? n_n7054 : tin_psv2_2_2_; + assign psv38_9_9_ = n_n8944 ? n_n8428 : tin_psv38_9_9_; + assign psv38_1_1_ = n_n9373 ? n_n7964 : tin_psv38_1_1_; + assign psv39_15_15_ = n_n7411 ? n_n8361 : tin_psv39_15_15_; + assign psv33_4_4_ = n_n7003 ? n_n7462 : tin_psv33_4_4_; + assign psv26_5_5_ = n_n8423 ? n_n7076 : tin_psv26_5_5_; + assign psv2_3_3_ = n_n6912 ? n_n8750 : tin_psv2_3_3_; + assign psv38_13_13_ = n_n9531 ? n_n6920 : tin_psv38_13_13_; + assign psv18_14_14_ = n_n8762 ? n_n7435 : tin_psv18_14_14_; + assign psv18_9_9_ = n_n6950 ? n_n6961 : tin_psv18_9_9_; + assign psv18_1_1_ = n_n7387 ? n_n9535 : tin_psv18_1_1_; + assign n491 = ~n4956 & ~preset & n_n9280; + assign n496 = n6728 | (n_n9434 & n4845 & n4967); + assign n501 = n6727 | (n_n9537 & n4845 & n4967); + assign n506 = n6725 | n6726; + assign n511 = ~n4956 & ~preset & n_n8270; + assign n516 = ~n4956 & ~preset & n_n8196; + assign n521 = ~n4956 & ~preset & n_n9150; + assign n526 = n6479 | n6480; + assign n531 = n6356 | (n1270 & n4848); + assign n536 = n6354 | n6355; + assign n541 = n6320 | n6321; + assign n546 = n6319 | (ndn3_11 & ~ndn3_12 & n4850); + assign n551 = ~preset & (n4851 ? n4930 : n_n7341); + assign n556 = ~preset & (n4852 ? n4868 : n_n9180); + assign n561 = n6317 | n6318; + assign n566 = n6316 | (nen3_39 & ~ndn3_39 & n4855); + assign n571 = n6314 | n6315; + assign n576 = n6312 | n6313; + assign n581 = n6310 | n6311; + assign n586 = n6197 | (n4858 & n7122) | (~n4858 & n7121); + assign n591 = n6196 | (n_n8354 & n4845 & n4967); + assign n596 = ~preset & (n4859_1 ? n4903 : n_n7552); + assign n601 = ~preset & ~nsr3_23; + assign n606 = n6194 | n6195; + assign n611 = n6192 | n6193; + assign n616 = n6190 | n6191; + assign n621 = ~preset & (n_n6950 | (ndn3_42 & ~ndn3_44)); + assign n626 = ~n4862 & (n_n8930 | (n4967 & n7089)); + assign n631 = ~preset & (n_n7244 | (~ndn3_42 & ndn3_40)); + assign n636 = n6189 | (n_n9512 & n4864_1 & n4967); + assign n641 = ~preset & (n4865 ? n4868 : n_n8883); + assign n646 = n6187 | n6188; + assign n651 = ~preset & (n_n9580 | (nen3_22 & ~ndn3_22)); + assign n656 = n6186 | (n_n9353 & n4867 & n4967); + assign n661 = n6185 | (n4863 & n4868); + assign n666 = n6184 | (n4853 & (n4969_1 ^ n4970)); + assign n671 = n6182 | n6183; + assign n676 = ~preset & (n4869_1 ? n4903 : n_n7373); + assign n681 = ~preset & (n_n9085 | (~ngfdn_3 & ndn3_46)); + assign n686 = n6178 | n6179 | n6180 | n6181; + assign n691 = n6177 | (~ndn3_29 & ndn3_28 & n4873); + assign n696 = n6145 | n6146; + assign n701 = ~preset & (n4875 ? n4930 : n_n7654); + assign n706 = ~preset & (n4876 ? n4887 : n_n8410); + assign n711 = n6082 | (ndn3_17 & ~ndn3_18 & n4878); + assign n716 = n6081 | (~ndn3_7 & ndn3_4 & n4873); + assign n721 = n6079_1 | n6080; + assign n726 = n6078 | (n_n9512 & n4845 & n4967); + assign n731 = n6077 | (~ndn3_19 & nen3_19 & n4855); + assign n736 = ~preset & (n4865 ? n4848 : n_n8202); + assign n741 = ~preset & (n4880 ? n4930 : n_n7670); + assign n746 = n6075 | n6076; + assign n751 = n6073 | n6074_1; + assign n756 = n6071 | n6072; + assign n761 = n6069_1 | n6070; + assign n766 = n6068 | (n_n8449 & n4883 & n4967); + assign n771 = n6067 | (n_n8419 & n4883 & n4967); + assign n776 = n6065 | n6066; + assign n781 = ~preset & (n4849_1 ? n4903 : n_n9141); + assign n786 = n6063 | n6064_1; + assign n791 = n6061 | n6062; + assign n796 = n6059_1 | n6060; + assign n801 = n6058 | (ndn3_11 & ~ndn3_12 & n4873); + assign n806 = n6056 | n6057; + assign n811 = n6054_1 | n6055; + assign n816 = n6052 | n6053; + assign n821 = ~preset & (n4854_1 ? n4903 : n_n7376); + assign n826 = n6051 | (ndn3_9 & ~ndn3_11 & n4878); + assign n831 = (n4005 & n4884_1) | (~preset & pover_0_0_ & ~n4884_1); + assign n835 = ~preset & (n4877 ? n4887 : n_n8599); + assign n840 = n6050 | (ndn3_11 & ~ndn3_12 & n4855); + assign n845 = ~n4956 & ~preset & n_n9442; + assign n850 = ~preset & (n4860 ? n4868 : n_n9485); + assign n855 = n6048 | n6049_1; + assign n860 = n6047 | (n_n9284 & n4864_1 & n4967); + assign n865 = n6046 | (ndn3_19 & ~ndn3_21 & n4873); + assign n870 = ~preset & ~ngfdn_3 & (ndn3_9 | ndn3_7); + assign n875 = ~n4956 & ~preset & n_n8613; + assign n880 = n6045 | (n_n8707 & n4867 & n4967); + assign n885 = n6044_1 | (n_n9512 & n4886 & n4967); + assign n890 = n6042 | n6043; + assign n895 = n6041 | (n4853 & n4887); + assign n900 = ~preset & (n_n8655 | (~ndn3_46 & ndn3_44)); + assign n905 = n6040 | (~ndn3_29 & ndn3_28 & n4888); + assign n910 = ~n4956 & ~preset & n_n7583; + assign n915 = n7174 | (n_n9248 & (~n_n9247 | ~n4902)); + assign n920 = n6038 | n6039_1; + assign n925 = n6037 | (~ndn3_7 & ndn3_4 & n4888); + assign n930 = n6035 | n6036; + assign n935 = ~preset & (n4889_1 ? n4903 : n_n7738); + assign n940 = ~n4956 & ~preset & n_n8573; + assign n945 = ~preset & (n4880 ? n4868 : n_n9473); + assign n950 = n6034_1 | (~ndn3_25 & ndn3_22 & n4873); + assign n955 = n6033 | (n_n8557 & n4890 & n4967); + assign n960 = ~n4956 & ~preset & n_n9554; + assign n965 = ~n4956 & ~preset & n_n8508; + assign n970 = n6031 | n6032; + assign n975 = n6029_1 | n6030; + assign n980 = n6027 | n6028; + assign n985 = n6025 | n6026; + assign n990 = ~preset & (n_n7409 | (ngfdn_3 & ~ndn3_50)); + assign n995 = ~n4956 & ~preset & n_n9437; + assign n1000 = n6023 | n6024_1; + assign n1005 = ~n4956 & ~preset & n_n8647; + assign n1010 = n6021 | n6022; + assign n1015 = n6019_1 | n6020; + assign n1020 = ~preset & ~nsr3_13; + assign n1025 = ~preset & ~ngfdn_3 & (ndn3_17 | ndn3_16); + assign n1030 = ~preset & ~ngfdn_3 & (ndn3_25 | ndn3_22); + assign n1035 = ~preset & ~ngfdn_3 & (ndn3_29 | ndn3_28); + assign n1040 = ~n4956 & ~preset & n_n9539; + assign n1045 = n6018 | (n_n8821 & n4883 & n4967); + assign n1050 = n6016 | n6017; + assign n1055 = ~preset & ~ngfdn_3 & (nen3_22 | ~nsr3_23); + assign n1060 = ~n4956 & ~preset & n_n9438; + assign n1065 = n6014_1 | n6015; + assign n1070 = n6013 | (n_n9416 & n4891 & n4967); + assign n1075 = n6011 | n6012; + assign n1080 = n6009_1 | n6010; + assign n1085 = n6008 | (n_n9353 & n4886 & n4967); + assign n1090 = ~preset & (n_n7798 | (nen3_22 & ~ndn3_22)); + assign n1095 = n6004_1 | n6005 | n6006 | n6007; + assign n1100 = ~preset & (n4859_1 ? n4904_1 : n_n7910); + assign n1105 = ~preset & (n4881 ? n4903 : n_n9528); + assign n1110 = n6002 | n6003; + assign n1115 = ~preset & (n_n8251 | (~ngfdn_3 & ndn3_46)); + assign n1120 = n6000 | n6001; + assign n1125 = n5998 | n5999_1; + assign n1130 = ~n4956 & ~preset & n_n9290; + assign n1135 = n5996 | n5997; + assign n1140 = ~preset & (n_n7556 | (~ndn3_46 & ndn3_44)); + assign n1145 = n5995 | (n_n8449 & n4886 & n4967); + assign n1150 = n5993 | n5994_1; + assign n1155 = n5992 | (ndn3_19 & ~ndn3_21 & n4855); + assign n1160 = ~n4956 & ~preset & n_n9361; + assign n1165 = ~preset & (n4885 ? n4848 : n_n9304); + assign n1170 = n5991 | (n_n8652 & n4896 & n4967); + assign n1175 = ~preset & (n4877 ? n4848 : n_n7712); + assign n1180 = n5990 | (n_n8707 & n4896 & n4967); + assign n1185 = n5989_1 | (n_n8549 & n4883 & n4967); + assign n1190 = n5988 | (~nsr3_13 & ~ndn3_15 & n4855); + assign n1195 = n5986 | n5987; + assign n1200 = ~preset & (n4849_1 ? n4930 : n_n9015); + assign n1205 = n5985 | (n_n8354 & n4891 & n4967); + assign n1210 = ~preset & (n4880 ? n4887 : n_n9518); + assign n1215 = n5983 | n5984_1; + assign n1220 = n5982 | (n_n9448 & n4883 & n4967); + assign n1225 = n5980 | n5981; + assign n1230 = n5978 | n5979_1; + assign n1235 = n5976 | n5977; + assign n1240 = ~preset & (n4849_1 ? n4887 : n_n7951); + assign n1245 = n5974_1 | n5973 | (n_n8913 & n4898); + assign n1250 = ~preset & (n4877 ? n4903 : n_n8035); + assign n1255 = n5972 | n5971 | (n_n8631 & n4898); + assign n1260 = ~preset & (n_n8243 | (ngfdn_3 & ~ndn3_50)); + assign n1265 = n5969_1 | n5970; + assign n1270 = ndn3_46 & ~preset & ~ngfdn_3; + assign n1275 = n5968 | (ndn3_9 & ~ndn3_11 & n4855); + assign n1280 = ~preset & (n4859_1 ? n4868 : n_n9175); + assign n1285 = n5966 | n5967; + assign n1290 = n5965 | (n_n9284 & n4891 & n4967); + assign n1295 = n5963 | n5964_1; + assign n1300 = ~n4956 & ~preset & n_n9410; + assign n1305 = n5962 | (n4861 & n4887); + assign n1310 = n5961 | (n_n8707 & n4886 & n4967); + assign n1315 = n5960 | (n_n9512 & n4867 & n4967); + assign n1320 = n5958 | n5959_1; + assign n1325 = n5957 | (n4863 & n4887); + assign n1330 = n5955 | n5956; + assign n1335 = n5954_1 | (~nsr3_13 & ~ndn3_15 & n4888); + assign n1340 = n5953 | (nen3_16 & ~ndn3_16 & n4850); + assign n1345 = n5952 | preset | pdn; + assign n1350 = n5951 | (n_n9353 & n4845 & n4967); + assign n1355 = ~n4956 & ~preset & n_n8531; + assign n1360 = n5950 | (n_n9638 & n4845 & n4967); + assign n1365 = n5949_1 | (n1270 & (n4985 ^ n4986)); + assign n1370 = n5948 | (nen3_39 & ~ndn3_39 & n4878); + assign n1375 = ~preset & (n_n8112 | (nen3_22 & ~ndn3_22)); + assign n1380 = n5946 | n5947; + assign n1385 = ~preset & (n4889_1 ? n4887 : n_n9618); + assign n1390 = n5944_1 | n5945; + assign n1395 = ~n4956 & ~preset & n_n9242; + assign n1400 = n5943 | (n4848 & n4853); + assign n1405 = ~preset & (n4882 ? n4868 : n_n8884); + assign n1410 = n5941 | n5942; + assign n1415 = n5940 | (n_n8549 & n4845 & n4967); + assign n1420 = n5939_1 | (n4853 & (n4976 ^ n4977)); + assign n1425 = ~preset & (n4876 ? n4904_1 : n_n7909); + assign n1430 = n5938 | (n4861 & (n4976 ^ n4977)); + assign n1435 = n5937 | (~ndn3_4 & ndn3_2 & n4850); + assign n1440 = ~preset & (n4860 ? n4930 : n_n8862); + assign n1445 = ~n4956 & ~preset & n_n8037; + assign n1450 = ~preset & ~ngfdn_3 & (ndn3_17 | ndn3_18); + assign n1455 = ~preset & ~ngfdn_3 & (nen3_22 | ndn3_22); + assign n1460 = ~preset & (n_n8974 | (ndn3_42 & ~ndn3_44)); + assign n1465 = ~preset & (n_n7286 | (~ndn3_42 & ndn3_40)); + assign n1470 = n5935 | n5936; + assign n1475 = ~preset & n4902; + assign n1480 = n5933 | n5934_1; + assign n1485 = n5931 | n5932; + assign n1490 = ~preset & ~ngfdn_3 & (nen3_39 | ~nsr3_38); + assign n1495 = n5929_1 | n5930; + assign n1500 = ~n4956 & ~preset & n_n9557; + assign n1505 = n5928 | (n_n8354 & n4896 & n4967); + assign n1510 = n5926 | n5927; + assign n1515 = n5924_1 | n5925; + assign n1520 = n5923 | (n_n9537 & n4886 & n4967); + assign n1525 = ~preset & (n_n8568 | (~ngfdn_3 & ndn3_46)); + assign n1530 = n5921 | n5922; + assign n1535 = ~preset & (n4889_1 ? n4904_1 : n_n7931); + assign n1540 = ~preset & (n4879_1 ? n4903 : n_n7742); + assign n1545 = n5920 | (ndn3_19 & ~ndn3_21 & n4878); + assign n1550 = n5919_1 | (n_n8549 & n4886 & n4967); + assign n1555 = ~preset & (n4874_1 ? n4904_1 : n_n9568); + assign n1560 = ~preset & (n_n9200 | (nen3_22 & ~ndn3_22)); + assign n1565 = n5917 | n5918; + assign n1570 = n5915 | n5916; + assign n1575 = n5914_1 | (nen3_16 & ~ndn3_16 & n4878); + assign n1580 = n5912 | n5913; + assign n1585 = n5910 | n5911; + assign n1590 = ~preset & (n4880 ? n4903 : n_n8499); + assign n1595 = n5908 | n5909_1; + assign n1600 = n5906 | n5907; + assign n1605 = n5905 | (ndn3_29 & ~ndn3_32 & n4873); + assign n1610 = n5903 | n5904_1; + assign n1615 = n5901 | n5902; + assign n1620 = ~preset & (n4852 ? n4848 : n_n7713); + assign n1625 = ~preset & (n4852 ? n4930 : n_n9566); + assign n1630 = n5899_1 | n5900; + assign n1635 = n5897 | n5898; + assign n1640 = n5896 | (~ndn3_7 & ndn3_4 & n4878); + assign n1645 = ~n4956 & ~preset & n_n9560; + assign n1650 = n5894_1 | n5895; + assign n1655 = n5892 | n5893; + assign n1660 = ~preset & (n4851 ? n4868 : n_n8882); + assign n1665 = n5890 | n5891; + assign n1670 = n5888 | n5889_1; + assign n1675 = n5887 | (ndn3_25 & ~ndn3_26 & n4888); + assign n1680 = n5885 | n5886; + assign n1685 = n5883 | n5884_1; + assign n1690 = n5882 | (n_n9537 & n4883 & n4967); + assign n1695 = ~n4956 & ~preset & n_n8875; + assign n1700 = n5880 | n5881; + assign n1705 = n5878 | n5879_1; + assign n1710 = n5877 | (n4846 & n4887); + assign n1715 = n5876 | (n4863 & n4903); + assign n1720 = n5875 | (n4853 & (n4971 ^ n4972)); + assign n1725 = n5874_1 | (n_n9416 & n4867 & n4967); + assign n1730 = n5873 | (n_n8821 & n4886 & n4967); + assign n1735 = n5871 | n5872; + assign n1740 = ~n4956 & ~preset & n_n7702; + assign n1745 = n7177 | (nsr3_23 & ~ndn3_19); + assign n1750 = ~n4956 & ~preset & n_n8199; + assign n1755 = ~n4956 & ~preset & n_n7983; + assign n1760 = n5870 | (n1270 & n4904_1); + assign n1765 = n5868 | n5869_1; + assign n1770 = n5867 | (n_n9434 & n4896 & n4967); + assign n1775 = ~n4956 & ~preset & n_n8348; + assign n1780 = n5865 | n5866; + assign n1785 = n5864_1 | (n_n8549 & n4890 & n4967); + assign n1790 = n5862 | n5863; + assign n1795 = n5861 | (n_n9638 & n4896 & n4967); + assign n1800 = n5860 | (n4848 & n4863); + assign n1805 = n5858 | n5859_1; + assign n1810 = n5856 | n5857; + assign n1815 = n5854_1 | n5855; + assign n1820 = n5853 | (n4863 & (n4976 ^ n4977)); + assign n1825 = n5852 | (n_n8419 & n4890 & n4967); + assign n1830 = n5851 | (n4846 & (n4976 ^ n4977)); + assign n1835 = n5850 | (n_n8354 & n4890 & n4967); + assign n1840 = n5849_1 | (n_n8652 & n4883 & n4967); + assign n1845 = n5848 | (ndn3_17 & ~ndn3_18 & n4888); + assign n1850 = n5847 | (n_n8707 & n4883 & n4967); + assign n1855 = n5845 | n5846; + assign n1860 = ~preset & ~nsr3_30; + assign n1865 = n5843 | n5844_1; + assign n1870 = ~preset & (n4859_1 ? n4887 : n_n7693); + assign n1875 = ~preset & ~ngfdn_3 & (nen3_16 | ~nsr3_14); + assign n1880 = n5841 | n5842; + assign n1885 = n5840 | (~ndn3_29 & ndn3_28 & n4878); + assign n1890 = n5839_1 | (n_n9512 & n4891 & n4967); + assign n1895 = n5837 | n5838; + assign n1900 = n5836 | (n_n8821 & n4891 & n4967); + assign n1905 = ~preset & (n4880 ? n4848 : n_n9110); + assign n1910 = n5834_1 | n5835; + assign n1915 = n5833 | (n4853 & n4868); + assign n1920 = n5832 | (n4863 & (n4969_1 ^ n4970)); + assign n1925 = n5830 | n5831; + assign n1930 = n5828 | n5829_1; + assign n1935 = n5827 | (~ndn3_27 & ndn3_26 & n4855); + assign n1940 = ~preset & (n_n8406 | (~ngfdn_3 & ndn3_46)); + assign n1945 = n5826 | (~ndn3_19 & nen3_19 & n4878); + assign n1950 = n5825 | (n_n8549 & n4867 & n4967); + assign n1955 = ~preset & (n4869_1 ? n4887 : n_n7474); + assign n1960 = n5824_1 | (n1270 & (n4954_1 ^ n4955)); + assign n1965 = ~preset & (n_n6984 | (~ndn3_46 & ndn3_44)); + assign n1970 = n5823 | (n4848 & n4866); + assign n1975 = n5821 | n5822; + assign n1980 = ~n4956 & ~preset & n_n9559; + assign n1985 = ~preset & (n_n7362 | (nen3_22 & ~ndn3_22)); + assign n1990 = n5819_1 | n5820; + assign n1995 = ~n4956 & ~preset & n_n9550; + assign n2000 = ~preset & (n4889_1 ? n4868 : n_n9492); + assign n2005 = n5817 | n5818; + assign n2010 = ~preset & (n4879_1 ? n4848 : n_n7764); + assign n2015 = n5815 | n5816; + assign n2020 = n5813 | n5814_1; + assign n2025 = n5811 | n5812; + assign n2030 = ~n4956 & ~preset & n_n8173; + assign n2035 = n5809_1 | n5810; + assign n2040 = n5807 | n5808; + assign n2045 = ~preset & (n4882 ? n4887 : n_n8753); + assign n2050 = ~preset & (n4852 ? n4904_1 : n_n8772); + assign n2055 = n5805 | n5806; + assign n2060 = ~n4956 & ~preset & n_n9362; + assign n2065 = ndn1_4 & ~preset & ~pdn; + assign n2070 = ~n4956 & ~preset & n_n9561; + assign n2075 = n5803 | n5804_1; + assign n2080 = ~preset & (n4849_1 ? n4848 : n_n8203); + assign n2085 = n5801 | n5802; + assign n2090 = n5799_1 | n5800; + assign n2095 = n5797 | n5798; + assign n2100 = ~n4956 & ~preset & n_n9331; + assign n2105 = n5796 | (~ndn3_19 & nen3_19 & n4873); + assign n2110 = ~preset & ~ngfdn_3 & (ndn3_7 | ndn3_4); + assign n2115 = n5795 | (n4853 & n4903); + assign n2120 = n5794_1 | (n4863 & (n4971 ^ n4972)); + assign n2125 = n5793 | (n_n9416 & n4886 & n4967); + assign n2130 = n5792 | (n_n8821 & n4867 & n4967); + assign n2135 = ~preset & (n4881 ? n4868 : n_n9497); + assign n2140 = ~preset & (n_n7291 | (~ndn3_42 & ndn3_40)); + assign n2145 = n7178 | (nsr3_13 & ~ndn3_12); + assign n2150 = n7179 | (nsr3_38 & ~nen3_36); + assign n2155 = ~n4956 & ~preset & n_n8240; + assign n2160 = ~n4956 & ~preset & n_n7703; + assign n2165 = n5791 | (n1270 & n4887); + assign n2170 = ~n4956 & ~preset & n_n8237; + assign n2175 = ~n4956 & ~preset & n_n8935; + assign n2180 = ~n4956 & ~preset & n_n9244; + assign n2185 = ~n4956 & ~preset & n_n8648; + assign n2190 = ~n4956 & ~preset & n_n8235; + assign n2195 = ~preset & (n4854_1 ? n4904_1 : n_n8611); + assign n2200 = n5789_1 | n5790; + assign n2205 = n5788 | (ndn3_29 & ~ndn3_32 & n4888); + assign n2210 = ~n4956 & ~preset & n_n8572; + assign n2215 = n5786 | n5787; + assign n2220 = n5785 | (~ndn3_9 & ndn3_7 & n4850); + assign n2225 = ~n4956 & ~preset & n_n9555; + assign n2230 = n5783 | n5784_1; + assign n2235 = ~preset & (n_n7050 | (ngfdn_3 & ~ndn3_50)); + assign n2240 = n5782 | (~ndn3_9 & ndn3_7 & n4888); + assign n2245 = ~preset & (n_n7140 | (ngfdn_3 & ~ndn3_50)); + assign n2250 = n5781 | (n_n9448 & n4890 & n4967); + assign n2255 = ~preset & (n_n6948 | (~ndn3_42 & ndn3_40)); + assign n2260 = n5777 | n5778 | n5779_1 | n5780; + assign n2265 = ~preset & ~ngfdn_3 & (ndn3_19 | nen3_19); + assign n2270 = ~preset & ~ngfdn_3 & (ndn3_28 | nen3_28); + assign n2275 = n5775 | n5776; + assign n2280 = n5773 | n5774_1; + assign n2285 = n5772 | (n4861 & (n4954_1 ^ n4955)); + assign n2290 = n5771 | (n_n8707 & n4891 & n4967); + assign n2295 = n5770 | (~ndn3_19 & nen3_19 & n4850); + assign n2300 = ~preset & ~ngfdn_3 & (nen3_36 | ~nsr3_37); + assign n2305 = n5769_1 | (n_n9284 & n4867 & n4967); + assign n2310 = n5767 | n5768; + assign n2315 = ~preset & (n4892 ? n4903 : n_n7736); + assign n2320 = n5765 | n5766; + assign n2325 = n5763 | n5764_1; + assign n2330 = ~preset & (n4892 ? n4887 : n_n8891); + assign n2335 = n5761 | n5762; + assign n2340 = n5760 | (n_n8557 & n4867 & n4967); + assign n2345 = n5758 | n5759_1; + assign n2350 = ~n4956 & ~preset & n_n9558; + assign n2355 = n5757 | (n4866 & (n4954_1 ^ n4955)); + assign n2360 = n5756 | (~nsr3_13 & ~ndn3_15 & n4878); + assign n2365 = ~preset & (n_n6956 | (~ngfdn_3 & ndn3_46)); + assign n2370 = ~preset & (n4847 ? n4903 : n_n8298); + assign n2375 = n5755 | (~ndn3_25 & ndn3_22 & n4850); + assign n2380 = n5753 | n5754_1; + assign n2385 = n5751 | n5752; + assign n2390 = ~n4956 & ~preset & n_n9552; + assign n2395 = n5750 | n5749_1 | (n_n8964 & n4898); + assign n2400 = ~n4956 & ~preset & n_n8016; + assign n2405 = n5747 | n5748; + assign n2410 = ~preset & (n4874_1 ? n4887 : n_n7696); + assign n2415 = n5745 | n5746; + assign n2420 = n5744_1 | (~ndn3_27 & ndn3_26 & n4888); + assign n2425 = n5743 | (n_n9353 & n4891 & n4967); + assign n2430 = n7181 | (~preset & n_n8652 & ~n5001); + assign n2435 = n7184 | (~preset & n_n8707 & ~n5001); + assign n2440 = n5741 | n5742; + assign n2445 = n5739_1 | n5740; + assign n2450 = n5738 | (~ndn3_29 & ndn3_28 & n4850); + assign n2455 = n7185 | (nsr3_30 & ~nak3_13); + assign n2460 = ~n4956 & ~preset & n_n8274; + assign n2465 = ~n4956 & ~preset & n_n8615; + assign n2470 = ~n4956 & ~preset & n_n8238; + assign n2475 = ~n4956 & ~preset & n_n7854; + assign n2480 = ~n4956 & ~preset & n_n8649; + assign n2485 = ~n4956 & ~preset & n_n8236; + assign n2490 = ~n4956 & ~preset & n_n8269; + assign n2495 = n5737 | (n_n9537 & n4896 & n4967); + assign n2500 = n5735 | n5736; + assign n2505 = n5733 | n5734_1; + assign n2510 = ~n4956 & ~preset & n_n8529; + assign n2515 = n5732 | (nen3_36 & ~ndn3_36 & n4878); + assign n2520 = n5731 | (n_n9434 & n4890 & n4967); + assign n2525 = ~n4956 & ~preset & n_n8685; + assign n2530 = ~preset & (n_n9531 | (~ndn3_46 & ndn3_44)); + assign n2535 = ~n4956 & ~preset & n_n9510; + assign n2540 = ~n4956 & ~preset & n_n7771; + assign n2545 = n5730 | (n_n8449 & n4845 & n4967); + assign n2550 = n5728 | n5729_1; + assign n2555 = n5727 | (nen3_36 & ~ndn3_36 & n4855); + assign n2560 = ~preset & ~ngfdn_3 & (ndn3_9 | ndn3_11); + assign n2565 = ~preset & ~ngfdn_3 & (~nsr3_13 | ndn3_15); + assign n2570 = ~preset & ~ngfdn_3 & (ndn3_19 | ndn3_21); + assign n2575 = ~n4956 & ~preset & n_n7584; + assign n2580 = n5723 | n5724_1 | n5725 | n5726; + assign n2585 = ~preset & (n_n6952 | (~ndn3_42 & ndn3_40)); + assign n2590 = n5722 | (ndn3_29 & ~ndn3_32 & n4878); + assign n2595 = n5720 | n5721; + assign n2600 = n5718 | n5719_1; + assign n2605 = n5717 | (n_n8549 & n4896 & n4967); + assign n2610 = n5716 | (n_n9284 & n4886 & n4967); + assign n2615 = n5714_1 | n5715; + assign n2620 = ~preset & (n_n7308 | (nen3_22 & ~ndn3_22)); + assign n2625 = n5712 | n5713; + assign n2630 = n5711 | (n_n9537 & n4867 & n4967); + assign n2635 = n5709_1 | n5710; + assign n2640 = ~preset & (n_n6912 | (~ndn3_42 & ndn3_40)); + assign n2645 = n5707 | n5708; + assign n2650 = n5706 | n5705 | (n_n8911 & n4898); + assign n2655 = ~preset & (n4881 ? n4887 : n_n7952); + assign n2660 = ~preset & (n_n8704 | (~ngfdn_3 & ndn3_46)); + assign n2665 = n5704_1 | (nen3_16 & ~ndn3_16 & n4873); + assign n2670 = n5703 | (n4866 & (n4969_1 ^ n4970)); + assign n2675 = n5701 | n5702; + assign n2680 = ~preset & (n4882 ? n4848 : n_n9019); + assign n2685 = ~preset & (n_n7699 | (nen3_22 & ~ndn3_22)); + assign n2690 = ~preset & (n4882 ? n4903 : n_n7375); + assign n2695 = n5699_1 | n5700; + assign n2700 = n5697 | n5698; + assign n2705 = n5696 | (ndn3_25 & ~ndn3_26 & n4850); + assign n2710 = n5694_1 | n5695; + assign n2715 = n5692 | n5693; + assign n2720 = n5690 | n5691; + assign n2725 = n5689_1 | (~ndn3_34 & nen3_34 & n4888); + assign n2730 = ~n4956 & ~preset & n_n7582; + assign n2735 = ~n4956 & ~preset & n_n8968; + assign n2740 = n5687 | n5688; + assign n2745 = n5685 | n5686; + assign n2750 = n5683 | n5684_1; + assign n2755 = ~preset & (n_n9373 | (~ndn3_46 & ndn3_44)); + assign n2760 = n4862 | (n_n9248 & (~n_n9247 | ~n4902)); + assign n2765 = n5682 | (n4866 & (n4971 ^ n4972)); + assign n2770 = n5680 | n5681; + assign n2775 = ~n4956 & ~preset & n_n8273; + assign n2780 = ~preset & (n_n6937 | (nen3_22 & ~ndn3_22)); + assign n2785 = n5679_1 | (nen3_16 & ~ndn3_16 & n4888); + assign n2790 = n5677 | n5678; + assign n2795 = n5676 | (n4846 & n4904_1); + assign n2800 = n5675 | (n4863 & (n4985 ^ n4986)); + assign n2805 = n5673 | n5674_1; + assign n2810 = n5671 | n5672; + assign n2815 = n5670 | (n_n9284 & n4890 & n4967); + assign n2820 = n5668 | n5669_1; + assign n2825 = ~preset & (n_n7181 | (~ndn3_46 & ndn3_44)); + assign n2830 = n5666 | n5667; + assign n2835 = n5664_1 | n5665; + assign n2840 = n5662 | n5663; + assign n2845 = n5661 | (~ndn3_17 & ndn3_16 & n4888); + assign n2850 = ~preset & (n4851 ? n4903 : n_n7487); + assign n2855 = n5659_1 | n5660; + assign n2860 = n5657 | n5658; + assign n2865 = n5656 | (n_n8449 & n4864_1 & n4967); + assign n2870 = ~preset & (n4874_1 ? n4868 : n_n9181); + assign n2875 = ~preset & (n_n8725 | (ngfdn_3 & ~ndn3_50)); + assign n2880 = n5654_1 | n5655; + assign n2885 = ~preset & ~ngfdn_3 & (ndn3_27 | ndn3_26); + assign n2890 = n5653 | (n_n8652 & n4891 & n4967); + assign n2895 = ~preset & (n_n7415 | (ndn3_42 & ~ndn3_44)); + assign n2900 = n5652 | (n_n8557 & n4896 & n4967); + assign n2905 = ~preset & ~ngfdn_3 & (nen3_19 | ~nsr3_20); + assign n2910 = ~preset & (n_n8762 | (ndn3_42 & ~ndn3_44)); + assign n2915 = ~preset & (n4880 ? n4904_1 : n_n8512); + assign n2920 = n5651 | (n_n8821 & n4864_1 & n4967); + assign n2925 = n5650 | (~ndn3_19 & nen3_19 & n4888); + assign n2930 = ~preset & (n_n7387 | (ndn3_42 & ~ndn3_44)); + assign n2935 = n5649_1 | (n_n9434 & n4886 & n4967); + assign n2940 = n5647 | n5648; + assign n2945 = n5645 | n5646; + assign n2950 = ~preset & (n4892 ? n4848 : n_n9157); + assign n2955 = n5644_1 | (nen3_36 & ~ndn3_36 & n4873); + assign n2960 = ~preset & (n_n7381 | (nen3_22 & ~ndn3_22)); + assign n2965 = ~preset & (n_n9446 | (~ndn3_42 & ndn3_40)); + assign n2970 = ~preset & (n_n8633 | (ndn3_39 & ~ndn3_40)); + assign n2975 = n5643 | (n4866 & (n4976 ^ n4977)); + assign n2980 = ~preset & (n_n7310 | (nen3_22 & ~ndn3_22)); + assign n2985 = n5642 | (ndn3_17 & ~ndn3_18 & n4855); + assign n2990 = n5640 | n5641; + assign n2995 = n5639_1 | (n_n8821 & n4896 & n4967); + assign n3000 = n5637 | n5638; + assign n3005 = n5635 | n5636; + assign n3010 = n5633 | n5634_1; + assign n3015 = ~preset & (n_n7315 | (ndn3_39 & ~ndn3_40)); + assign n3020 = ~preset & (n_n9476 | (ndn3_39 & ~ndn3_40)); + assign n3025 = n5631 | n5632; + assign n3030 = n5630 | (n_n9638 & n4883 & n4967); + assign n3035 = n5628 | n5629_1; + assign n3040 = n5627 | (~ndn3_28 & nen3_28 & n4850); + assign n3045 = n7190 | (~n4894_1 & (n7188 | n7189)); + assign n3050 = n5624_1 | n5625; + assign n3055 = n7191 | (~ndn3_29 & nsr3_35); + assign n3060 = ~preset & (n_n7154 | (ndn3_39 & ~ndn3_40)); + assign n3065 = ~preset & (n4875 ? n4868 : n_n9495); + assign n3070 = n5622 | n5623; + assign n3075 = n5621 | (n4866 & n4887); + assign n3080 = n5619_1 | n5620; + assign n3085 = n5617 | n5618; + assign n3090 = n5615 | n5616; + assign n3095 = n5614_1 | (n4853 & (n4985 ^ n4986)); + assign n3100 = n5612 | n5613; + assign n3105 = ~n4956 & ~preset & n_n8970; + assign n3110 = n5610 | n5611; + assign n3115 = n5608 | n5609_1; + assign n3120 = ~preset & (n_n7246 | (nen3_22 & ~ndn3_22)); + assign n3125 = n5606 | n5607; + assign n3130 = n5604_1 | n5605; + assign n3135 = ~preset & (n_n7635 | (ngfdn_3 & ~ndn3_50)); + assign n3140 = n5603 | (ndn3_11 & ~ndn3_12 & n4888); + assign n3145 = n5601 | n5602; + assign n3150 = n5600 | (nen3_39 & ~ndn3_39 & n4850); + assign n3155 = ~preset & (n4860 ? n4904_1 : n_n9108); + assign n3160 = ~preset & (n4851 ? n4887 : n_n9286); + assign n3165 = ~preset & ~ngfdn_3 & (ndn3_11 | ndn3_12); + assign n3170 = ~preset & ~ngfdn_3 & (nen3_16 | ndn3_16); + assign n3175 = ~preset & (n4876 ? n4848 : n_n7708); + assign n3180 = n5599_1 | (n_n8419 & n4864_1 & n4967); + assign n3185 = n5598 | (n_n8652 & n4864_1 & n4967); + assign n3190 = ~preset & (n4860 ? n4887 : n_n7947); + assign n3195 = n5596 | n5597; + assign n3200 = n5595 | (n_n8707 & n4864_1 & n4967); + assign n3205 = n5594_1 | (ndn3_19 & ~ndn3_21 & n4850); + assign n3210 = ~preset & (n_n7659 | (ndn3_42 & ~ndn3_44)); + assign n3215 = ~n4956 & ~preset & n_n7630; + assign n3220 = n5593 | (ndn3_19 & ~ndn3_21 & n4888); + assign n3225 = ~n4956 & ~preset & n_n8691; + assign n3230 = n5592 | (n_n9434 & n4867 & n4967); + assign n3235 = n5591 | (~ndn3_28 & nen3_28 & n4873); + assign n3240 = ~preset & (n4876 ? n4930 : n_n7995); + assign n3245 = n5589_1 | n5590; + assign n3250 = n5588 | (~nsr3_13 & ~ndn3_15 & n4873); + assign n3255 = ~preset & (n_n7507 | (ndn3_39 & ~ndn3_40)); + assign n3260 = ~preset & (n_n7959 | (~ngfdn_3 & ndn3_46)); + assign n3265 = n5586 | n5587; + assign n3270 = n5584_1 | n5585; + assign n3275 = n5582 | n5583; + assign n3280 = n5581 | (n_n9448 & n4886 & n4967); + assign n3285 = ~preset & (n4881 ? n4904_1 : n_n8106); + assign n3290 = n5579_1 | n5580; + assign n3295 = n5577 | n5578; + assign n3300 = n5575 | n5576; + assign n3305 = n5574_1 | (~ndn3_9 & ndn3_7 & n4873); + assign n3310 = n5573 | (~ndn3_9 & ndn3_7 & n4878); + assign n3315 = n5571 | n5572; + assign n3320 = ~preset & (n4885 ? n4930 : n_n9087); + assign n3325 = n5569_1 | n5570; + assign n3330 = ~n4956 & ~preset & n_n7852; + assign n3335 = n5567 | n5568; + assign n3340 = ~preset & (~n_n9198 | (~n4967 & n4974_1)); + assign n3345 = n5563 | n5564_1 | n5565 | n5566; + assign n3350 = n7193 | preset | (nsr3_13 & nsr3_14); + assign n3355 = n7197 | n5561 | n5562; + assign n3360 = ~preset & (n_n7026 | (ngfdn_3 & ~ndn3_50)); + assign n3365 = n5559_1 | n5560; + assign n3370 = ~n4956 & ~preset & n_n8272; + assign n3375 = n5558 | (n_n9284 & n4896 & n4967); + assign n3380 = ~n4956 & ~preset & n_n7985; + assign n3385 = ~n4956 & ~preset & n_n8312; + assign n3390 = n5556 | n5557; + assign n3395 = n5554_1 | n5555; + assign n3400 = n5552 | n5553; + assign n3405 = ~preset & (n_n8683 | (~ndn3_42 & ndn3_40)); + assign n3410 = ~preset & ~ngfdn_3 & (nen3_39 | ndn3_39); + assign n3415 = ~preset & (n_n8245 | (~ndn3_42 & ndn3_40)); + assign n3420 = n5551 | (~ndn3_34 & nen3_34 & n4873); + assign n3425 = n5549_1 | n5550; + assign n3430 = n5547 | n5548; + assign n3435 = n5545 | n5546; + assign n3440 = n5544_1 | (n_n8419 & n4896 & n4967); + assign n3445 = n5543 | (n_n9638 & n4886 & n4967); + assign n3450 = n5541 | n5542; + assign n3455 = ~preset & (n4869_1 ? n4848 : n_n8201); + assign n3460 = n5540 | (~ndn3_4 & ndn3_2 & n4855); + assign n3465 = n5538 | n5539_1; + assign n3470 = ~preset & (n_n8389 | (nen3_22 & ~ndn3_22)); + assign n3475 = ~n4956 & ~preset & n_n9440; + assign n3480 = n5536 | n5537; + assign n3485 = n5535 | (n_n8354 & n4886 & n4967); + assign n3490 = n5534_1 | (n_n9448 & n4867 & n4967); + assign n3495 = n5533 | (n_n9416 & n4896 & n4967); + assign n3500 = n5531 | n5532; + assign n3505 = n5530 | (~ndn3_7 & ndn3_4 & n4855); + assign n3510 = n5529_1 | (n_n8354 & n4883 & n4967); + assign n3515 = n5527 | n5528; + assign n3520 = ~preset & (n_n7209 | (ngfdn_3 & ~ndn3_50)); + assign n3525 = ~preset & (n_n7003 | (ngfdn_3 & ~ndn3_50)); + assign n3530 = ~preset & (n4852 ? n4887 : n_n7695); + assign n3535 = n5526 | (nen3_39 & ~ndn3_39 & n4873); + assign n3540 = n5524_1 | n5525; + assign n3545 = ~preset & (n4865 ? n4903 : n_n7374); + assign n3550 = n5522 | n5523; + assign n3555 = ~preset & (n_n7944 | (~ngfdn_3 & ndn3_46)); + assign n3560 = n5521 | (n_n9537 & n4891 & n4967); + assign n3565 = n5519_1 | n5520; + assign n3570 = ~preset & (n_n6988 | (ngfdn_3 & ~ndn3_50)); + assign n3575 = ~preset & (n_n6986 | (ndn3_39 & ~ndn3_40)); + assign n3580 = n5518 | n5517 | (n_n8933 & n4898); + assign n3585 = ~preset & (n_n7117 | (ndn3_39 & ~ndn3_40)); + assign n3590 = n5516 | (n_n9284 & n4845 & n4967); + assign n3595 = ~n4956 & ~preset & n_n8241; + assign n3600 = n5515 | (n1270 & (n4971 ^ n4972)); + assign n3605 = ~n4956 & ~preset & n_n8198; + assign n3610 = n5513 | n5514_1; + assign n3615 = ~n4956 & ~preset & n_n8575; + assign n3620 = ~n4956 & ~preset & n_n8710; + assign n3625 = ~preset & (n_n7622 | (nen3_22 & ~ndn3_22)); + assign n3630 = n5512 | (n_n8557 & n4845 & n4967); + assign n3635 = n5511 | (n_n8449 & n4890 & n4967); + assign n3640 = ~preset & (n_n7033 | (~ndn3_46 & ndn3_44)); + assign n3645 = ~preset & ~ngfdn_3 & (ndn3_34 | nen3_34); + assign n3650 = n5510 | (n_n9512 & n4883 & n4967); + assign n3655 = ndn3_50 & ~preset & ~ngfdn_3; + assign n3660 = n5509_1 | (n_n9416 & n4883 & n4967); + assign n3665 = ~preset & (n_n7019 | (ndn3_42 & ~ndn3_44)); + assign n3670 = n5508 | (n4861 & n4868); + assign n3675 = ~preset & (n_n7261 | (~ngfdn_3 & ndn3_46)); + assign n3680 = n5507 | (ndn3_29 & ~ndn3_32 & n4855); + assign n3685 = n5505 | n5506; + assign n3690 = ~preset & (n4876 ? n4903 : n_n7993); + assign n3695 = n5503 | n5504_1; + assign n3700 = n5501 | n5502; + assign n3705 = n5499_1 | n5500; + assign n3710 = n5497 | n5498; + assign n3715 = ~preset & (n_n8918 | (~ndn3_42 & ndn3_40)); + assign n3720 = ~preset & (n4882 ? n4904_1 : n_n8515); + assign n3725 = ~preset & (n4875 ? n4904_1 : n_n7933); + assign n3730 = ~preset & (n4847 ? n4930 : n_n8075); + assign n3735 = ~preset & (n_n7338 | (nen3_22 & ~ndn3_22)); + assign n3740 = ~preset & (n4882 ? n4930 : n_n8104); + assign n3745 = ~n4956 & ~preset & n_n8171; + assign n3750 = n5496 | (n_n8707 & n4890 & n4967); + assign n3755 = n5494_1 | n5495; + assign n3760 = n5492 | n5493; + assign n3765 = ~n4956 & ~preset & n_n9441; + assign n3770 = n5490 | n5491; + assign n3775 = ~preset & (n_n8831 | (ndn3_39 & ~ndn3_40)); + assign n3780 = ~preset & (n_n8441 | (ndn3_39 & ~ndn3_40)); + assign n3785 = n5489_1 | (n4846 & n4903); + assign n3790 = n5487 | n5488; + assign n3795 = ~n4956 & ~preset & n_n9363; + assign n3800 = ~preset & ~ngfdn_3 & (ndn3_4 | ndn3_2); + assign n3805 = n5485 | n5486; + assign n3810 = ~preset & (n_n7561 | (~ngfdn_3 & ndn3_46)); + assign n3815 = n5484_1 | n5483 | (n_n8923 & n4898); + assign n3820 = ~preset & (n_n7978 | (ndn3_39 & ~ndn3_40)); + assign n3825 = n5482 | n5481 | (n_n8978 & n4898); + assign n3830 = ~preset & (n4879_1 ? n4868 : n_n9499); + assign n3835 = ~preset & (n_n8713 | (~ndn3_46 & ndn3_44)); + assign n3840 = ~preset & (n_n8944 | (~ndn3_46 & ndn3_44)); + assign n3845 = ~n4956 & ~preset & n_n8239; + assign n3850 = ~preset & (n4889_1 ? n4930 : n_n7652); + assign n3855 = n5479_1 | n5480; + assign n3860 = ~n4956 & ~preset & n_n8530; + assign n3865 = n5477 | n5478; + assign n3870 = n5475 | n5476; + assign n3875 = n5474_1 | (n4848 & n4861); + assign n3880 = n5472 | n5473; + assign n3885 = n5471 | (~ndn3_34 & nen3_34 & n4855); + assign n3890 = n5469_1 | n5470; + assign n3895 = n5467 | n5468; + assign n3900 = n5466 | (~ndn3_27 & ndn3_26 & n4873); + assign n3905 = n5464_1 | n5465; + assign n3910 = ~n4956 & ~preset & n_n7961; + assign n3915 = n5462 | n5463; + assign n3920 = n5460 | n5461; + assign n3925 = n5459_1 | (n4861 & (n4969_1 ^ n4970)); + assign n3930 = n5458 | (n4863 & (n4954_1 ^ n4955)); + assign n3935 = ~preset & (n_n9161 | n4956); + assign n3940 = n5456 | n5457; + assign n3945 = n5454_1 | n5455; + assign n3950 = n5452 | n5453; + assign n3955 = n5450 | n5451; + assign n3960 = ~n4956 & ~preset & n_n9360; + assign n3965 = n5449_1 | (ndn3_25 & ~ndn3_26 & n4855); + assign n3970 = ~preset & (n_n8392 | (~ndn3_42 & ndn3_40)); + assign n3975 = n5448 | n5447 | (n_n9034 & n4898); + assign n3980 = ~preset & (n4879_1 ? n4887 : n_n8375); + assign n3985 = n5446 | (n_n9416 & n4845 & n4967); + assign n3990 = ~n4956 & ~preset & n_n9298; + assign n3995 = n5444_1 | n5445; + assign n4000 = n5442 | n5443; + assign n4005 = ~nsr1_2 & ~preset & ~pdn; + assign n4009 = n5440 | n5441; + assign n4014 = n5438 | n5439_1; + assign n4019 = ~n4956 & ~preset & n_n9291; + assign n4024 = n5436 | n5437; + assign n4029 = n5435 | (ndn3_11 & ~ndn3_12 & n4878); + assign n4034 = n5433 | n5434_1; + assign n4039 = n5432 | (n_n9353 & n4883 & n4967); + assign n4044 = n5430 | n5431; + assign n4049 = n5428 | n5429_1; + assign n4054 = n5426 | n5427; + assign n4059 = ~preset & (n4885 ? n4887 : n_n9351); + assign n4064 = n5425 | (n_n9638 & n4864_1 & n4967); + assign n4069 = n_n8668 & ~n4862; + assign n4074 = n5423 | n5424_1; + assign n4079 = ~preset & (n_n7013 | (~ngfdn_3 & ndn3_46)); + assign n4084 = n5422 | (n1270 & n4930); + assign n4089 = ~n4956 & ~preset & n_n8200; + assign n4094 = n5421 | (n1270 & n4903); + assign n4099 = ~n4956 & ~preset & n_n8803; + assign n4104 = n5419_1 | n5420; + assign n4109 = ~n4956 & ~preset & n_n8366; + assign n4114 = n5417 | n5418; + assign n4119 = ~n4956 & ~preset & n_n8650; + assign n4124 = ~n4956 & ~preset & n_n8574; + assign n4129 = ~preset & (n_n7276 | (nen3_22 & ~ndn3_22)); + assign n4134 = n5415 | n5416; + assign n4139 = n5413 | n5414_1; + assign n4144 = ~preset & ~nsr3_35; + assign n4149 = n5409_1 | n5410 | n5411 | n5412; + assign n4154 = ~preset & ~ngfdn_3 & (ndn3_46 | ndn3_44); + assign n4159 = n5407 | n5408; + assign n4164 = n5405 | n5406; + assign n4169 = n5403 | n5404_1; + assign n4174 = ~n4956 & ~preset & n_n9359; + assign n4179 = ~preset & (n4892 ? n4904_1 : n_n8425); + assign n4184 = n5402 | (n4846 & (n4969_1 ^ n4970)); + assign n4189 = n5401 | (n4853 & (n4954_1 ^ n4955)); + assign n4194 = n5397 | n5398 | n5399_1 | n5400; + assign n4199 = n5393 | n5394_1 | n5395 | n5396; + assign n4204 = n5392 | (~ndn3_25 & ndn3_22 & n4878); + assign n4209 = ~preset & (n_n7467 | (~ndn3_42 & ndn3_40)); + assign n4214 = n5390 | n5391; + assign n4219 = n5389_1 | (n4866 & n4904_1); + assign n4224 = n5388 | (n_n8557 & n4886 & n4967); + assign n4229 = ~preset & (n_n9162 | n4956); + assign n4234 = n5387 | (~ndn3_4 & ndn3_2 & n4878); + assign n4239 = ~preset & (n_n8055 | (~ngfdn_3 & ndn3_46)); + assign n4244 = n5386 | (n_n8354 & n4867 & n4967); + assign n4249 = n5385 | (n1270 & (n4969_1 ^ n4970)); + assign n4254 = n5384_1 | (n_n9512 & n4896 & n4967); + assign n4259 = ~preset & (n4875 ? n4848 : n_n7762); + assign n4264 = n5382 | n5383; + assign n4269 = n5380 | n5381; + assign n4274 = n5379_1 | (n_n9416 & n4890 & n4967); + assign n4279 = n5377 | n5378; + assign n4284 = n5375 | n5376; + assign n4289 = n5373 | n5374_1; + assign n4294 = n5371 | n5372; + assign n4299 = n5369_1 | n5370; + assign n4304 = ~preset & (n4885 ? n4903 : n_n9100); + assign n4309 = n5368 | (n_n9353 & n4864_1 & n4967); + assign n4314 = n5367 | (n_n9537 & n4864_1 & n4967); + assign n4319 = ~preset & (n4865 ? n4887 : n_n7588); + assign n4324 = ~preset & (n_n9123 | (ngfdn_3 & ~ndn3_50)); + assign n4329 = n5366 | (~ndn3_28 & nen3_28 & n4888); + assign n4334 = n5365 | (nen3_36 & ~ndn3_36 & n4850); + assign n4339 = n5363 | n5364_1; + assign n4344 = n5362 | (n4866 & n4930); + assign n4349 = n5360 | n5361; + assign n4354 = n5359_1 | (n4866 & n4903); + assign n4359 = n5357 | n5358; + assign n4364 = n5356 | (n_n9353 & n4896 & n4967); + assign n4369 = n5355 | (n4861 & (n4985 ^ n4986)); + assign n4374 = ~n4956 & ~preset & n_n8571; + assign n4379 = ~n4956 & ~preset & n_n8796; + assign n4384 = ~preset & ~ngfdn_3 & (nen3_36 | ndn3_36); + assign n4389 = n5354_1 | (n_n8354 & n4864_1 & n4967); + assign n4394 = n5352 | n5353; + assign n4399 = ~preset & (n_n8817 | (ndn3_42 & ~ndn3_44)); + assign n4404 = ~preset & (n_n9160 | n4956); + assign n4409 = n5351 | (n_n8449 & n4896 & n4967); + assign n4414 = ~preset & (n4869_1 ? n4904_1 : n_n8513); + assign n4419 = n5349_1 | n5350; + assign n4424 = n5348 | (ndn3_25 & ~ndn3_26 & n4878); + assign n4429 = n7206 | (~preset & n_n9284 & ~n5001); + assign n4434 = n5346 | n5347; + assign n4439 = n5345 | (~ndn3_29 & ndn3_28 & n4855); + assign n4444 = ~preset & (n4851 ? n4904_1 : n_n9203); + assign n4449 = ~preset & (n4879_1 ? n4930 : n_n7655); + assign n4454 = ~preset & (n_n8946 | (ndn3_39 & ~ndn3_40)); + assign n4459 = ~preset & (n_n7052 | (~ndn3_46 & ndn3_44)); + assign n4464 = ~preset & (n4851 ? n4848 : n_n9615); + assign n4469 = n5344_1 | (~ndn3_25 & ndn3_22 & n4855); + assign n4474 = ~preset & (n4875 ? n4903 : n_n7741); + assign n4479 = n5342 | n5343; + assign n4484 = ~preset & (n4877 ? n4904_1 : n_n7912); + assign n4489 = n5341 | (n1270 & n4868); + assign n4494 = ~preset & (n4875 ? n4887 : n_n9021); + assign n4499 = n5339_1 | n5340; + assign n4504 = n5338 | (nen3_16 & ~ndn3_16 & n4855); + assign n4509 = n5336 | n5337; + assign n4514 = n5334_1 | n5335; + assign n4519 = n5333 | (ndn3_9 & ~ndn3_11 & n4873); + assign n4524 = n5331 | n5332; + assign n4529 = ~preset & (n4847 ? n4887 : n_n7694); + assign n4534 = n5330 | (n_n9448 & n4891 & n4967); + assign n4539 = n5328 | n5329_1; + assign n4544 = ~preset & (n4879_1 ? n4904_1 : n_n7935); + assign n4549 = n5326 | n5327; + assign n4554 = ~n4956 & ~preset & n_n7701; + assign n4559 = ~preset & (n4877 ? n4930 : n_n7510); + assign n4564 = ~n4956 & ~preset & n_n7627; + assign n4569 = n5324_1 | n5325; + assign n4574 = ~preset & (n4849_1 ? n4904_1 : n_n8516); + assign n4579 = ~preset & (n4847 ? n4904_1 : n_n7913); + assign n4584 = n5323 | (n_n9284 & n4883 & n4967); + assign n4589 = ~preset & (n_n7411 | (ndn3_39 & ~ndn3_40)); + assign n4594 = n5322 | (~ndn3_27 & ndn3_26 & n4850); + assign n4599 = n5320 | n5321; + assign n4604 = n5318 | n5319_1; + assign n4609 = n5316 | n5317; + assign n4614 = ~preset & (n_n7242 | (ndn3_42 & ~ndn3_44)); + assign n4619 = ~preset & (n_n8230 | (ndn3_42 & ~ndn3_44)); + assign n4624 = ~n4956 & ~preset & n_n9294; + assign n4629 = n5315 | (n4863 & n4930); + assign n4634 = ~n4956 & ~preset & n_n8972; + assign n4639 = n5313 | n5314_1; + assign n4644 = ~preset & (n_n7493 | (ngfdn_3 & ~ndn3_50)); + assign n4649 = ~preset & (n_n8290 | (ngfdn_3 & ~ndn3_50)); + assign n4654 = n5309_1 | n5310 | n5311 | n5312; + assign n4659 = ~n4956 & ~preset & n_n7769; + assign n4664 = ~preset & (n_n7491 | (~ndn3_46 & ndn3_44)); + assign n4669 = n5307 | n5308; + assign n4674 = n5305 | n5306; + assign n4679 = ~preset & (n_n8047 | (ndn3_39 & ~ndn3_40)); + assign n4684 = n5303 | n5304_1; + assign n4689 = n5302 | (ndn3_29 & ~ndn3_32 & n4850); + assign n4694 = n5300 | n5301; + assign n4699 = n5299_1 | (n4846 & n4848); + assign n4704 = ~n4956 & ~preset & n_n8528; + assign n4709 = ~preset & ~nsr3_37; + assign n4714 = ~preset & ~ngfdn_3 & (ndn3_42 | ndn3_40); + assign n4719 = ~n4956 & ~preset & n_n9358; + assign n4724 = n5297 | n5298; + assign n4729 = ~preset & ~ngfdn_3 & (~nsr3_30 | nen3_28); + assign n4734 = n5296 | (~ndn3_28 & nen3_28 & n4878); + assign n4739 = ~preset & (n_n7903 | (ndn3_42 & ~ndn3_44)); + assign n4744 = n5294_1 | n5295; + assign n4749 = ~preset & (n4892 ? n4930 : n_n9075); + assign n4754 = ~n4956 & ~preset & n_n9439; + assign n4759 = n7209 | n5292 | n5293; + assign n4764 = n5290 | n5291; + assign n4769 = n5289_1 | n5288 | (n_n8798 & n4898); + assign n4774 = ~preset & (n_n7146 | (~ndn3_46 & ndn3_44)); + assign n4779 = n5286 | n5287; + assign n4784 = ~preset & (n_n7176 | (~ngfdn_3 & ndn3_46)); + assign n4789 = n5285 | (n_n8652 & n4845 & n4967); + assign n4794 = ~preset & (n4865 ? n4904_1 : n_n8514); + assign n4799 = n5284_1 | (n_n8707 & n4845 & n4967); + assign n4804 = ~preset & (n_n7183 | (ndn3_39 & ~ndn3_40)); + assign n4809 = n5283 | (n_n8419 & n4886 & n4967); + assign n4814 = n5282 | (n4866 & n4868); + assign n4819 = n5281 | (n_n8557 & n4891 & n4967); + assign n4824 = n5279_1 | n5280; + assign n4829 = n5278 | (n_n8549 & n4891 & n4967); + assign n4834 = n5276 | n5277; + assign n4839 = n5275 | (n_n8449 & n4891 & n4967); + assign n4844 = n5273 | n5274_1; + assign n4849 = n5271 | n5272; + assign n4854 = n5269_1 | n5270; + assign n4859 = n5267 | n5268; + assign n4864 = n5265 | n5266; + assign n4869 = n5264_1 | n5263 | (n_n9011 & n4898); + assign n4874 = n5261 | n5262; + assign n4879 = n5259_1 | n5260; + assign n4884 = n5257 | n5258; + assign n4889 = n5255 | n5256; + assign n4894 = ~preset & (n_n9164 | n4956); + assign n4899 = n5253 | n5254_1; + assign n4904 = n5251 | n5252; + assign n4909 = n5249_1 | n5250; + assign n4914 = n5248 | (~ndn3_4 & ndn3_2 & n4873); + assign n4919 = n5247 | (~ndn3_34 & nen3_34 & n4850); + assign n4924 = ~n4956 & ~preset & n_n7768; + assign n4929 = n5245 | n5246; + assign n4934 = n5244_1 | (n4861 & n4930); + assign n4939 = n5242 | n5243; + assign n4944 = n5241 | (n_n9434 & n4891 & n4967); + assign n4949 = n5239_1 | n5240; + assign n4954 = n5238 | (n4853 & n4930); + assign n4959 = n5237 | (n_n9638 & n4891 & n4967); + assign n4964 = n5235 | n5236; + assign n4969 = n5233 | n5234_1; + assign n4974 = ~preset & (n_n9228 | (~ngfdn_3 & ndn3_46)); + assign n4979 = n5232 | (~nsr3_13 & ~ndn3_15 & n4850); + assign n4984 = ~preset & (n_n8510 | (~ndn3_42 & ndn3_40)); + assign n4989 = ~preset & (n4869_1 ? n4868 : n_n8881); + assign n4994 = n5231 | (~ndn3_7 & ndn3_4 & n4850); + assign n4999 = n5229_1 | n5230; + assign n5004 = n5228 | n5227 | (n_n9031 & n4898); + assign n5009 = n7210 | (~nak3_13 & nsr3_37); + assign n5014 = ~n4956 & ~preset & n_n8197; + assign n5019 = n5225 | n5226; + assign n5024 = n5223 | n5224_1; + assign n5029 = n5221 | n5222; + assign n5034 = ~preset & ~ngfdn_3 & (ndn3_42 | ndn3_44); + assign n5039 = n5219_1 | n5220; + assign n5044 = n5218 | (n_n9448 & n4864_1 & n4967); + assign n5049 = n5216 | n5217; + assign n5054 = ~preset & ~pdn & (nsr1_2 | nlc1_2); + assign n5059 = n5214_1 | n5215; + assign n5064 = ~n4956 & ~preset & n_n8577; + assign n5069 = ~preset & (n_n7079 | (ndn3_42 & ~ndn3_44)); + assign n5074 = ~preset & (n4869_1 ? n4930 : n_n8828); + assign n5079 = n5213 | (n_n9638 & n4867 & n4967); + assign n5084 = n5211 | n5212; + assign n5089 = ~preset & (n4874_1 ? n4848 : n_n7901); + assign n5094 = n5209_1 | n5210; + assign n5099 = n5208 | n5207 | (n_n8869 & n4898); + assign n5104 = ~preset & (n4859_1 ? n4848 : n_n7710); + assign n5109 = n5206 | n5205 | (n_n8993 & n4898); + assign n5114 = ~preset & (n4885 ? n4904_1 : n_n9586); + assign n5119 = ~preset & (n4889_1 ? n4848 : n_n8852); + assign n5124 = n5204_1 | (~ndn3_17 & ndn3_16 & n4878); + assign n5129 = n5202 | n5203; + assign n5134 = ~preset & (n_n7717 | (ndn3_39 & ~ndn3_40)); + assign n5139 = n5201 | (n_n8821 & n4845 & n4967); + assign n5144 = ~preset & (n_n9163 | n4956); + assign n5149 = n5200 | (n_n8557 & n4883 & n4967); + assign n5154 = n5198 | n5199_1; + assign n5159 = n5196 | n5197; + assign n5164 = n5194_1 | n5195; + assign n5169 = n5192 | n5193; + assign n5174 = n5191 | (n_n8652 & n4890 & n4967); + assign n5179 = n5190 | (~ndn3_25 & ndn3_22 & n4888); + assign n5184 = n5188 | n5189_1; + assign n5189 = n5187 | (n_n9512 & n4890 & n4967); + assign n5194 = n5185 | n5186; + assign n5199 = n5184_1 | (~ndn3_17 & ndn3_16 & n4873); + assign n5204 = n5182 | n5183; + assign n5209 = ~preset & (n_n7330 | (ndn3_39 & ~ndn3_40)); + assign n5214 = n5180 | n5181; + assign n5219 = n5178 | n5179_1; + assign n5224 = n5177 | n5176 | (n_n8847 & n4898); + assign n5229 = n5174_1 | n5175; + assign n5234 = ~preset & (n4874_1 ? n4903 : n_n7553); + assign n5239 = ~n4956 & ~preset & n_n9292; + assign n5244 = ~preset & (n4854_1 ? n4887 : n_n7464); + assign n5249 = n5172 | n5173; + assign n5254 = n5170 | n5171; + assign n5259 = n5169_1 | (n_n9434 & n4883 & n4967); + assign n5264 = ~n4956 & ~preset & n_n8118; + assign n5269 = n5168 | (n4846 & n4930); + assign n5274 = n5167 | (n4861 & n4903); + assign n5279 = n5166 | (n4861 & (n4971 ^ n4972)); + assign n5284 = n5165 | (n_n9434 & n4864_1 & n4967); + assign n5289 = ~preset & ~ngfdn_3 & (ndn3_2 | n4949_1); + assign n5294 = n5164_1 | (n_n8652 & n4867 & n4967); + assign n5299 = n5162 | n5163; + assign n5304 = n5160 | n5161; + assign n5309 = ~preset & (n_n8665 | (ngfdn_3 & ~ndn3_50)); + assign n5314 = n5158 | n5159_1; + assign n5319 = n5156 | n5157; + assign n5324 = n5154_1 | n5155; + assign n5329 = ~preset & (n4876 ? n4868 : n_n9173); + assign n5334 = n5152 | n5153; + assign n5339 = ~preset & (n_n7150 | (~ndn3_42 & ndn3_40)); + assign n5344 = n5151 | (nen3_36 & ~ndn3_36 & n4888); + assign n5349 = n5149_1 | n5150; + assign n5354 = n7211 | (~ndn3_17 & nsr3_20); + assign n5359 = ~n4956 & ~preset & n_n8271; + assign n5364 = n5147 | n5148; + assign n5369 = n5146 | (n4853 & n4904_1); + assign n5374 = ~preset & ~ngfdn_3 & (ndn3_39 | ndn3_40); + assign n5379 = n5144_1 | n5145; + assign n5384 = n5143 | (~ndn3_4 & ndn3_2 & n4888); + assign n5389 = n5141 | n5142; + assign n5394 = n5139_1 | n5140; + assign n5399 = ~preset & (n4885 ? n4868 : n_n8462); + assign n5404 = n5137 | n5138; + assign n5409 = n5135 | n5136; + assign n5414 = ~n4956 & ~preset & n_n9289; + assign n5419 = ~preset & (n4881 ? n4930 : n_n7661); + assign n5424 = n5133 | n5134_1; + assign n5429 = ~preset & (n_n8921 | (~ndn3_46 & ndn3_44)); + assign n5434 = n5132 | (~ndn3_28 & nen3_28 & n4855); + assign n5439 = n5131 | (n_n9448 & n4896 & n4967); + assign n5444 = n5129_1 | n5130; + assign n5449 = n5128 | (n4866 & (n4985 ^ n4986)); + assign n5454 = n5126 | n5127; + assign n5459 = n5124_1 | n5125; + assign n5464 = n5123 | (n_n8449 & n4867 & n4967); + assign n5469 = n5121 | n5122; + assign n5474 = n5120 | (n_n8419 & n4867 & n4967); + assign n5479 = ~preset & (n_n7336 | (~ngfdn_3 & ndn3_46)); + assign n5484 = n5119_1 | (~ndn3_17 & ndn3_16 & n4855); + assign n5489 = n5117 | n5118; + assign n5494 = n5115 | n5116; + assign n5499 = n5113 | n5114_1; + assign n5504 = ~preset & (n_n8423 | (nen3_22 & ~ndn3_22)); + assign n5509 = ~preset & (n4881 ? n4848 : n_n7763); + assign n5514 = n5112 | (n_n8419 & n4891 & n4967); + assign n5519 = n5110 | n5111; + assign n5524 = n5108 | n5109_1; + assign n5529 = n5106 | n5107; + assign n5534 = n5104_1 | n5105; + assign n5539 = n5103 | (~ndn3_9 & ndn3_7 & n4855); + assign n5544 = ~preset & (n4852 ? n4903 : n_n9563); + assign n5549 = ~preset & (n_n8672 | (ngfdn_3 & ~ndn3_50)); + assign n5554 = ~preset & (n4854_1 ? n4930 : n_n7346); + assign n5559 = n5102 | (n_n8821 & n4890 & n4967); + assign n5564 = ~n4956 & ~preset & n_n8756; + assign n5569 = ~preset & (n4874_1 ? n4930 : n_n8641); + assign n5574 = n5100 | n5101; + assign n5579 = n5099_1 | (ndn3_17 & ~ndn3_18 & n4873); + assign n5584 = n5098 | n5097 | (n_n8561 & n4898); + assign n5589 = ~preset & (n_n9306 | (ngfdn_3 & ~ndn3_50)); + assign n5594 = ~preset & (n_n9165 | n4956); + assign n5599 = n5095 | n5096; + assign n5604 = ~preset & (n4847 ? n4848 : n_n9210); + assign n5609 = ~n4901 & ~preset & ndn2_2; + assign n5614 = ~preset & (n4865 ? n4930 : n_n7342); + assign n5619 = n5093 | n5094_1; + assign n5624 = n5092 | (n4846 & (n4971 ^ n4972)); + assign n5629 = n5090 | n5091; + assign n5634 = ~preset & (n_n9006 | (ndn3_42 & ~ndn3_44)); + assign n5639 = n5089_1 | (n_n8652 & n4886 & n4967); + assign n5644 = ~preset & (n_n7905 | (ndn3_42 & ~ndn3_44)); + assign n5649 = ~preset & (n_n9166 | n4956); + assign n5654 = ~preset & (n_n7065 | (ndn3_42 & ~ndn3_44)); + assign n5659 = ~preset & (n4892 ? n4868 : n_n9490); + assign n5664 = ~preset & (n_n7024 | (~ndn3_42 & ndn3_40)); + assign n5669 = ~preset & (n_n7586 | (~ngfdn_3 & ndn3_46)); + assign n5674 = n5087 | n5088; + assign n5679 = n5085 | n5086; + assign n5684 = ~n4956 & ~preset & n_n8141; + assign n5689 = ~n4956 & ~preset & n_n7853; + assign n5694 = ~preset & (n_n8121 | (~ndn3_42 & ndn3_40)); + assign n5699 = n5083 | n5084_1; + assign n5704 = ~preset & (n4849_1 ? n4868 : n_n9496); + assign n5709 = ~preset & (n_n8195 | (ndn3_42 & ~ndn3_44)); + assign n5714 = ~preset & (n4860 ? n4848 : n_n9516); + assign n5719 = n5082 | (~ndn3_27 & ndn3_26 & n4878); + assign n5724 = ~n4956 & ~preset & n_n9436; + assign n5729 = n5080 | n5081; + assign n5734 = n5078 | n5079_1; + assign n5739 = n5074_1 | n5075 | n5076 | n5077; + assign n5744 = n5073 | (n_n9416 & n4864_1 & n4967); + assign n5749 = n5072 | (ndn3_9 & ~ndn3_11 & n4850); + assign n5754 = n5071 | (n_n9353 & n4890 & n4967); + assign n5759 = ~n4956 & ~preset & n_n7770; + assign n5764 = ~preset & ~ngfdn_3 & (ndn3_29 | ndn3_32); + assign n5769 = n5069_1 | n5070; + assign n5774 = n5068 | (n4846 & n4868); + assign n5779 = n5067 | (n4863 & n4904_1); + assign n5784 = n5065 | n5066; + assign n5789 = n5063 | n5064_1; + assign n5794 = n5061 | n5062; + assign n5799 = ~preset & ~nsr3_38; + assign n5804 = n5059_1 | n5060; + assign n5809 = ~preset & (n4847 ? n4868 : n_n9179); + assign n5814 = ~n4956 & ~preset & n_n9357; + assign n5819 = n5057 | n5058; + assign n5824 = ~n4956 & ~preset & n_n7628; + assign n5829 = ~preset & (n_n8454 | (~ndn3_46 & ndn3_44)); + assign n5834 = ~preset & ~nsr3_20; + assign n5839 = n5056 | (n_n9448 & n4845 & n4967); + assign n5844 = ~preset & ~ngfdn_3 & (~nsr3_35 | nen3_34); + assign n5849 = n5055 | (n4861 & n4904_1); + assign n5854 = n5053 | n5054_1; + assign n5859 = n5051 | n5052; + assign n5864 = n5049_1 | n5050; + assign n5869 = ~preset & (n_n9578 | n4956); + assign n5874 = ~preset & (n4860 ? n4903 : n_n8135); + assign n5879 = ~preset & ~ngfdn_3 & (ndn3_25 | ndn3_26); + assign n5884 = n5047 | n5048; + assign n5889 = n5046 | (n4846 & (n4985 ^ n4986)); + assign n5894 = ~preset & (n_n8605 | (~ndn3_46 & ndn3_44)); + assign n5899 = ~n4956 & ~preset & n_n9296; + assign n5904 = n5044_1 | n5045; + assign n5909 = n5043 | (n_n9638 & n4890 & n4967); + assign n5914 = n5041 | n5042; + assign n5919 = n5040 | (nen3_39 & ~ndn3_39 & n4888); + assign n5924 = n5038 | n5039_1; + assign n5929 = ~n4956 & ~preset & n_n9275; + assign n5934 = n5036 | n5037; + assign n5939 = n5035 | (n_n9537 & n4890 & n4967); + assign n5944 = n5033 | n5034_1; + assign n5949 = n5031 | n5032; + assign n5954 = ~n4956 & ~preset & n_n7629; + assign n5959 = ~preset & ~nsr3_14; + assign n5964 = n5030 | (n4846 & (n4954_1 ^ n4955)); + assign n5969 = ~n4956 & ~preset & n_n9013; + assign n5974 = n5028 | n5029_1; + assign n5979 = n5027 | (n_n8557 & n4864_1 & n4967); + assign n5984 = ~preset & (n4854_1 ? n4848 : n_n7334); + assign n5989 = ~n4956 & ~preset & n_n7704; + assign n5994 = n5026 | (n_n8419 & n4845 & n4967); + assign n5999 = ~preset & (n4859_1 ? n4930 : n_n8526); + assign n6004 = ~n4956 & ~preset & n_n9556; + assign n6009 = n5025 | (ndn3_9 & ~ndn3_11 & n4888); + assign n6014 = ~n4956 & ~preset & n_n8447; + assign n6019 = n5023 | n5024_1; + assign n6024 = ~n4956 & ~preset & n_n8570; + assign n6029 = n5022 | (ndn3_25 & ~ndn3_26 & n4873); + assign n6034 = n5021 | (n_n8549 & n4864_1 & n4967); + assign n6039 = ~n4956 & ~preset & n_n8646; + assign n6044 = n5019_1 | n5020; + assign n6049 = n5018 | (n1270 & (n4976 ^ n4977)); + assign n6054 = n5017 | (ndn3_17 & ~ndn3_18 & n4850); + assign n6059 = ~preset & (n_n8216 | (~ndn3_46 & ndn3_44)); + assign n6064 = ~preset & (n4877 ? n4868 : n_n9177); + assign n6069 = n5015 | n5016; + assign n6074 = n5014_1 | (~ndn3_17 & ndn3_16 & n4850); + assign n6079 = n5012 | n5013; + assign n6084 = n5010 | n5011; + assign n6089 = ~preset & (n4854_1 ? n4868 : n_n8858); + assign n6094 = n5009_1 | (~ndn3_34 & nen3_34 & n4878); + assign n4845 = ~nsr3_37 & ~preset & ~ndn3_37; + assign n4846 = ~ndn3_40 & ~preset & ndn3_39; + assign n4847 = ndn3_9 & ~ndn3_11; + assign n4848 = n5002 ? ((~n4988 & ~n4989_1) | (~n4976 & (~n4989_1 | (~n4988 & n4989_1)))) : ((n4988 & n4989_1) | (n4976 & (n4988 ^ n4989_1))); + assign n4849_1 = ndn3_11 & ~ndn3_12; + assign n4850 = ~preset & (n4996 ^ (n6545 | n6546)); + assign n4851 = ndn3_25 & ~ndn3_26; + assign n4852 = ~ndn3_9 & ndn3_7; + assign n4853 = ndn3_44 & ~preset & ~ndn3_46; + assign n4854_1 = nen3_39 & ~ndn3_39; + assign n4855 = ~preset & (n4980 ^ (n6352 | n6353)); + assign n4856 = n_n9247 & n_n9248 & ~preset & ~n_n7306; + assign n4857 = n4856 & n5001; + assign n4858 = n4998 ? ((n4905 & n4906) | (n_n8549 & (n4905 | n4906))) : ((~n4905 & ~n4906) | (~n_n8549 & (~n4905 | ~n4906))); + assign n4859_1 = ~ndn3_27 & ndn3_26; + assign n4860 = ~ndn3_34 & nen3_34; + assign n4861 = ~ndn3_44 & ~preset & ndn3_42; + assign n4862 = ~n_n9198 | preset | (~n4967 & n4974_1); + assign n4863 = ndn3_40 & ~preset & ~ndn3_42; + assign n4864_1 = ~ndn3_35 & ~preset & ~nsr3_35; + assign n4865 = ~ndn3_19 & nen3_19; + assign n4866 = ~ndn3_22 & ~preset & nen3_22; + assign n4867 = ~nsr3_23 & ~preset & ~ndn3_23; + assign n4868 = n4965 ? ((~n4978 & ~n4979_1) | (~n4972 & (~n4979_1 | (~n4978 & n4979_1)))) : ((n4978 & n4979_1) | (n4972 & (~n4978 ^ ~n4979_1))); + assign n4869_1 = ~ndn3_29 & ndn3_28; + assign n4870 = n6282 | n6283 | n6284 | n7095; + assign n4871 = (n_n8821 & n4934_1) | ((n_n8821 | n4934_1) & (n7112 | n7113)); + assign n4872 = (n_n9638 & n4871) | ((n_n9638 | n4871) & (n7094 | n7095)); + assign n4873 = ~preset & (n5004_1 ^ (n6527 | n6528)); + assign n4874_1 = ~ndn3_4 & ndn3_2; + assign n4875 = nen3_16 & ~ndn3_16; + assign n4876 = nen3_36 & ~ndn3_36; + assign n4877 = ndn3_17 & ~ndn3_18; + assign n4878 = ~preset & (n4997 ^ (n6083 | n6084_1)); + assign n4879_1 = ~ndn3_7 & ndn3_4; + assign n4880 = ndn3_29 & ~ndn3_32; + assign n4881 = ~nsr3_13 & ~ndn3_15; + assign n4882 = ~ndn3_17 & ndn3_16; + assign n4883 = ~nsr3_13 & ~preset & ~ndn3_13; + assign n4884_1 = pdn ? ~ndn1_4 : ~nsr1_2; + assign n4885 = ndn3_19 & ~ndn3_21; + assign n4886 = ~ndn3_20 & ~preset & ~nsr3_20; + assign n4887 = n4966 ? ((~n5007 & ~n5008) | (~n4969_1 & (~n5008 | (~n5007 & n5008)))) : ((n5007 & n5008) | (n4969_1 & (~n5007 ^ ~n5008))); + assign n4888 = ~preset & (n4987 ^ (n6433 | n6434)); + assign n4889_1 = ~ndn3_25 & ndn3_22; + assign n4890 = ~ndn3_38 & ~preset & ~nsr3_38; + assign n4891 = ~ndn3_14 & ~preset & ~nsr3_14; + assign n4892 = ~ndn3_28 & nen3_28; + assign n4893 = n6261 | n6262 | n6263 | n7097; + assign n4894_1 = (n_n9512 & n4919_1) | ((n_n9512 | n4919_1) & (n7098 | n7099)); + assign n4895 = (n_n9434 & n4894_1) | ((n_n9434 | n4894_1) & (n7096 | n7097)); + assign n4896 = ~nsr3_30 & ~preset & ~ndn3_30; + assign n4897 = n6857 | n6858; + assign n4898 = ~preset & (n4975 ? n4967 : ~n5001); + assign n4899_1 = ~n_n8631 ^ (n_n8561 | n4999_1); + assign n4900 = n6859 | n6860; + assign n4901 = ~nlc1_2 & preset_0_0_ & nsr1_2; + assign n4902 = n7173 & n7172 & ~n4907 & ~n4940; + assign n4903 = n4973 ? ((~n4981 & ~n4982) | (~n4955 & (~n4982 | (~n4981 & n4982)))) : ((n4981 & n4982) | (n4955 & (~n4981 ^ ~n4982))); + assign n4904_1 = n4952 ? ((~n4994_1 & ~n4995) | (~n4986 & (~n4995 | (~n4994_1 & n4995)))) : ((n4994_1 & n4995) | (n4986 & (~n4994_1 ^ ~n4995))); + assign n4905 = n6303 | n6304 | n6305 | n7091; + assign n4906 = (n_n8449 & n4932) | ((n_n8449 | n4932) & (n7092 | n7093)); + assign n4907 = (~n_n8913 & ~n_n8964 & ~n4968) | (n_n8964 & (n_n8913 | n4968)); + assign n4908 = n6861 | n6862; + assign n4909_1 = n_n8652 & (n7100 | n7101); + assign n4910 = n6233 | n6234 | n6235 | n7101; + assign n4911 = (n_n9284 & n4909_1) | ((n_n9284 | n4909_1) & (n7102 | n7103)); + assign n4912 = (n_n8707 & n4911) | ((n_n8707 | n4911) & (n7104 | n7105)); + assign n4913 = n6226 | n6227 | n6228 | n7105; + assign n4914_1 = (n_n8354 & n4915) | ((n_n8354 | n4915) & (n7116 | n7117)); + assign n4915 = (n_n9448 & n4872) | ((n_n9448 | n4872) & (n7114 | n7115)); + assign n4916 = n6212 | n6213 | n6214 | n7117; + assign n4917 = n6863 | n6864; + assign n4918 = n6254 | n6255 | n6256 | n7099; + assign n4919_1 = (n_n9353 & n4912) | ((n_n9353 | n4912) & (n7106 | n7107)); + assign n4920 = (n_n9353 & (n4912 | n4938)) | n4918 | (n4912 & n4938); + assign n4921 = n6268 | n6269 | n6270 | n7109; + assign n4922 = (n_n9416 & n4895) | ((n_n9416 | n4895) & (n7108 | n7109)); + assign n4923 = n6867 | n6868; + assign n4924_1 = (n_n8923 & (~n_n8603 | n_n8798)) | (n_n8603 & ~n_n8923 & ~n_n8798); + assign n4925 = n6869 | n6870; + assign n4926 = n6871 | n6872; + assign n4927 = (~n_n8911 & ~n_n8933 & ~n_n8978 & ~n5000) | (n_n8978 & (n_n8911 | n_n8933 | n5000)); + assign n4928 = (~n_n9034 & ~n_n9031 & ~n_n8993 & ~n5005) | (n_n9034 & (n_n9031 | n_n8993 | n5005)); + assign n4929_1 = n6873 | n6874; + assign n4930 = (~n6992 & ~n6993 & (n6999 | n7000)) | (~n6999 & ~n7000 & (n6992 | n6993)); + assign n4931 = n6296 | n6297 | n6298 | n7093; + assign n4932 = (n_n8419 & n4914_1) | ((n_n8419 | n4914_1) & (n7118 | n7119)); + assign n4933 = n6289 | n6290 | n6291 | n7115; + assign n4934_1 = (n_n9537 & n4922) | ((n_n9537 | n4922) & (n7110 | n7111)); + assign n4935 = n6275 | n6276 | n6277 | n7111; + assign n4936 = n6240 | n6241 | n6242 | n7103; + assign n4937 = n6219 | n6220 | n6221 | n7113; + assign n4938 = n6247 | n6248 | n6249 | n7107; + assign n4939_1 = n6875 | n6876; + assign n4940 = (~n_n8913 & ~n_n8964 & ~n_n9011 & ~n4968) | (n_n9011 & (n_n8913 | n_n8964 | n4968)); + assign n4941 = n6877 | n6878; + assign n4942 = n6879 | n6880; + assign n4943 = ~n_n9031 ^ (n_n8993 | n5005); + assign n4944_1 = n6881 | n6882; + assign n4945 = (n_n8869 & (~n_n8603 | n_n8923 | n_n8798)) | (n_n8603 & ~n_n8923 & ~n_n8798 & ~n_n8869); + assign n4946 = n6883 | n6884; + assign n4947 = (~n_n8631 & ~n_n8847 & ~n_n8561 & ~n4999_1) | (n_n8847 & (n_n8631 | n_n8561 | n4999_1)); + assign n4948 = n6885 | n6886; + assign n4949_1 = nsr1_2 & (nlc1_2 ? n_n7476 : ~preset_0_0_); + assign n4950 = n6887 | n6888; + assign n4951 = n6205 | n6206 | n6207 | n7119; + assign n4952 = (~n7157 & ~n7158 & (n7164 | n7165)) | (~n7164 & ~n7165 & (n7157 | n7158)); + assign n4953 = n_n9247 & ~n_n7306 & n_n9248; + assign n4954_1 = (~n6978 & ~n6979 & (n6985 | n6986)) | (~n6985 & ~n6986 & (n6978 | n6979)); + assign n4955 = (n6992 | n6993) & (n6999 | n7000); + assign n4956 = ~ndn2_2 & ~nlc1_2 & preset_0_0_ & nsr1_2; + assign n4957 = nsr3_13 ? ndn3_12 : nsr3_14; + assign n4958 = (nen3_36 & ~ndn3_36) | (~ndn3_4 & ndn3_2); + assign n4959_1 = (~ndn3_29 & ndn3_28) | (nen3_39 & ~ndn3_39); + assign n4960 = (ndn3_42 & ~ndn3_44) | (~ndn3_34 & nen3_34); + assign n4961 = (~ndn3_19 & nen3_19) | (~ndn3_28 & nen3_28); + assign n4962 = (ndn3_39 & ~ndn3_40) | (ndn3_25 & ~ndn3_26); + assign n4963 = (~ndn3_42 & ndn3_40) | (ndn3_29 & ~ndn3_32); + assign n4964_1 = (~ndn3_17 & ndn3_16) | (~ndn3_27 & ndn3_26); + assign n4965 = (~n6922 & ~n6923 & (n6929 | n6930)) | (~n6929 & ~n6930 & (n6922 | n6923)); + assign n4966 = (~n7048 & ~n7049 & (n7055 | n7056)) | (~n7055 & ~n7056 & (n7048 | n7049)); + assign n4967 = n_n8930 ? n_n8929 : (n6897 | n6898); + assign n4968 = n_n8631 | n_n8847 | n_n8561 | n4999_1; + assign n4969_1 = (n4992 & n4993) | ((n6527 | n6528) & (~n4992 ^ ~n4993)); + assign n4970 = (~n7006 & ~n7007 & (n7013 | n7014)) | (~n7013 & ~n7014 & (n7006 | n7007)); + assign n4971 = (~n6936 & ~n6937 & (n6943 | n6944)) | (~n6943 & ~n6944 & (n6936 | n6937)); + assign n4972 = (n4990 & n4991) | ((n6545 | n6546) & (~n4990 ^ ~n4991)); + assign n4973 = (~n6964 & ~n6965 & (n6971 | n6972)) | (~n6971 & ~n6972 & (n6964 | n6965)); + assign n4974_1 = n4957 | n7086 | n7087 | n7088; + assign n4975 = ~n_n8668 & (~n_n9198 | (~n4967 & n4974_1)); + assign n4976 = (n4983 & n4984_1) | ((n6433 | n6434) & (~n4983 ^ ~n4984_1)); + assign n4977 = (~n7020 & ~n7021 & (n7027 | n7028)) | (~n7027 & ~n7028 & (n7020 | n7021)); + assign n4978 = n6665 | n6666 | n6935 | n6937; + assign n4979_1 = n6651 | n6652 | n6942 | n6944; + assign n4980 = (~n7076 & ~n7077 & (n7083 | n7084)) | (~n7083 & ~n7084 & (n7076 | n7077)); + assign n4981 = n6593 | n6594 | n6977 | n6979; + assign n4982 = n6607 | n6608 | n6984 | n6986; + assign n4983 = n6465 | n6466 | n7033 | n7035; + assign n4984_1 = n6417 | n6418 | n7040 | n7042; + assign n4985 = (~n7129 & ~n7130 & (n7136 | n7137)) | (~n7136 & ~n7137 & (n7129 | n7130)); + assign n4986 = (n5003 & n5006) | ((n6352 | n6353) & (~n5003 ^ ~n5006)); + assign n4987 = (~n7034 & ~n7035 & (n7041 | n7042)) | (~n7041 & ~n7042 & (n7034 | n7035)); + assign n4988 = n6387 | n6388 | n7019 | n7021; + assign n4989_1 = n6401 | n6402 | n7026 | n7028; + assign n4990 = n6637 | n6638 | n6949 | n6951; + assign n4991 = n6529 | n6530 | n6956 | n6958; + assign n4992 = n6711 | n6712 | n6905 | n6907; + assign n4993 = n6511 | n6512 | n6914 | n6916; + assign n4994_1 = n6163 | n6164 | n7128 | n7130; + assign n4995 = n6147 | n6148 | n7135 | n7137; + assign n4996 = (~n6950 & ~n6951 & (n6957 | n6958)) | (~n6957 & ~n6958 & (n6950 | n6951)); + assign n4997 = (~n7143 & ~n7144 & (n7150 | n7151)) | (~n7150 & ~n7151 & (n7143 | n7144)); + assign n4998 = n6198 | n6199 | n6200 | n7120; + assign n4999_1 = n_n9034 | n_n9031 | n_n8993 | n5005; + assign n5000 = ~n_n8603 | n_n8923 | n_n8798 | n_n8869; + assign n5001 = n_n9247 ? n7085 : (n4967 & n7089); + assign n5002 = (~n7062 & ~n7063 & (n7069 | n7070)) | (~n7069 & ~n7070 & (n7062 | n7063)); + assign n5003 = n6322 | n6323 | n7075 | n7077; + assign n5004_1 = (~n6906 & ~n6907 & (n6915 | n6916)) | (~n6915 & ~n6916 & (n6906 | n6907)); + assign n5005 = n_n8911 | n_n8933 | n_n8978 | n5000; + assign n5006 = n6338 | n6339 | n7082 | n7084; + assign n5007 = n6497 | n6498 | n7005 | n7007; + assign n5008 = n6481 | n6482 | n7012 | n7014; + assign n5009_1 = ~preset & n_n8580 & (ndn3_34 | ~nen3_34); + assign n5010 = ~preset & n_n8428 & (ndn3_46 | ~ndn3_44); + assign n5011 = ~ndn3_46 & ~preset & n_n9333 & ndn3_44; + assign n5012 = ~preset & n_n9145 & (ngfdn_3 | ~ndn3_46); + assign n5013 = n_n9629 & ndn3_46 & ~preset & ~ngfdn_3; + assign n5014_1 = ~preset & n_n8811 & (ndn3_17 | ~ndn3_16); + assign n5015 = ~preset & n_n7844 & (~nen3_36 | ndn3_36); + assign n5016 = ~preset & n4876 & (~n4985 ^ ~n4986); + assign n5017 = ~preset & n_n9131 & (~ndn3_17 | ndn3_18); + assign n5018 = ~preset & n_n8948 & (ngfdn_3 | ~ndn3_46); + assign n5019_1 = ~ndn3_2 & ~preset & psv26_3_3_ & n4949_1; + assign n5020 = ~preset & n_n9405 & (ndn3_2 | ~n4949_1); + assign n5021 = ~preset & n_n7928 & (nsr3_35 | ndn3_35); + assign n5022 = ~preset & n_n7453 & (~ndn3_25 | ndn3_26); + assign n5023 = ~preset & n_n7485 & (~ndn3_25 | ndn3_26); + assign n5024_1 = ~preset & n4851 & (~n4971 ^ ~n4972); + assign n5025 = ~preset & n_n9345 & (~ndn3_9 | ndn3_11); + assign n5026 = ~preset & n_n7788 & (ndn3_37 | nsr3_37); + assign n5027 = ~preset & n_n8078 & (nsr3_35 | ndn3_35); + assign n5028 = ~preset & n_n7288 & (~ngfdn_3 | ndn3_50); + assign n5029_1 = ~ndn3_50 & n_n9282 & ~preset & ngfdn_3; + assign n5030 = ~preset & n_n7862 & (~ndn3_39 | ndn3_40); + assign n5031 = ~ndn3_2 & ~preset & psv18_9_9_ & n4949_1; + assign n5032 = ~preset & n_n6976 & (ndn3_2 | ~n4949_1); + assign n5033 = ~preset & n_n7344 & (~ngfdn_3 | ndn3_50); + assign n5034_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9570; + assign n5035 = ~preset & n_n9590 & (nsr3_38 | ndn3_38); + assign n5036 = ~preset & n_n7203 & (ndn3_46 | ~ndn3_44); + assign n5037 = ~ndn3_46 & ~preset & n_n9125 & ndn3_44; + assign n5038 = ~ndn3_2 & ~preset & psv38_14_14_ & n4949_1; + assign n5039_1 = ~preset & n_n8139 & (ndn3_2 | ~n4949_1); + assign n5040 = ~preset & n_n8991 & (~nen3_39 | ndn3_39); + assign n5041 = ~preset & n_n8895 & (ngfdn_3 | ~ndn3_46); + assign n5042 = ndn3_46 & n_n7570 & ~preset & ~ngfdn_3; + assign n5043 = ~preset & n_n7920 & (nsr3_38 | ndn3_38); + assign n5044_1 = ~preset & n_n7156 & (~ndn3_42 | ndn3_44); + assign n5045 = ~ndn3_44 & ndn3_42 & ~preset & n_n8609; + assign n5046 = ~preset & n_n6974 & (~ndn3_39 | ndn3_40); + assign n5047 = ~preset & n_n7500 & (~nen3_22 | ndn3_22); + assign n5048 = ~ndn3_22 & ~preset & nen3_22 & n_n9460; + assign n5049_1 = ~preset & n_n9048 & (~ndn3_17 | ndn3_18); + assign n5050 = ~preset & n4877 & (~n4954_1 ^ ~n4955); + assign n5051 = ~ndn3_2 & ~preset & psv38_7_7_ & n4949_1; + assign n5052 = ~preset & n_n9262 & (ndn3_2 | ~n4949_1); + assign n5053 = ~preset & n_n7076 & (~nen3_22 | ndn3_22); + assign n5054_1 = ~ndn3_22 & ~preset & nen3_22 & n_n8462; + assign n5055 = ~preset & n_n9632 & (~ndn3_42 | ndn3_44); + assign n5056 = ~preset & n_n9505 & (ndn3_37 | nsr3_37); + assign n5057 = ~ndn3_2 & ~preset & psv18_7_7_ & n4949_1; + assign n5058 = ~preset & n_n9594 & (ndn3_2 | ~n4949_1); + assign n5059_1 = ~ndn3_2 & ~preset & psv18_13_13_ & n4949_1; + assign n5060 = ~preset & n_n7886 & (ndn3_2 | ~n4949_1); + assign n5061 = ~preset & n_n9269 & (ndn3_4 | ~ndn3_2); + assign n5062 = ~preset & n4874_1 & (~n4969_1 ^ ~n4970); + assign n5063 = ~preset & n_n7111 & (~ngfdn_3 | ndn3_50); + assign n5064_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9028; + assign n5065 = ~ndn3_2 & ~preset & psv2_7_7_ & n4949_1; + assign n5066 = ~preset & n_n9606 & (ndn3_2 | ~n4949_1); + assign n5067 = ~preset & n_n7927 & (ndn3_42 | ~ndn3_40); + assign n5068 = ~preset & n_n8206 & (~ndn3_39 | ndn3_40); + assign n5069_1 = ~preset & n_n7601 & (ndn3_27 | ~ndn3_26); + assign n5070 = ~preset & n4859_1 & (~n4971 ^ ~n4972); + assign n5071 = ~preset & n_n9392 & (nsr3_38 | ndn3_38); + assign n5072 = ~preset & n_n9133 & (~ndn3_9 | ndn3_11); + assign n5073 = ~preset & n_n7874 & (nsr3_35 | ndn3_35); + assign n5074_1 = n7212 & ((n4915 & n4916) | (n_n8354 & (n4915 | n4916))); + assign n5075 = ~n_n8419 & n4857 & (~n4914_1 ^ ~n4951); + assign n5076 = ~n4951 & ~n4914_1 & n_n8419 & n4856; + assign n5077 = ~n5001 & ~preset & n_n8419; + assign n5078 = ~preset & n_n7664 & (~nen3_36 | ndn3_36); + assign n5079_1 = ~preset & n4876 & (~n4976 ^ ~n4977); + assign n5080 = ~preset & n_n9051 & (ndn3_9 | ~ndn3_7); + assign n5081 = ~preset & n4852 & (~n4954_1 ^ ~n4955); + assign n5082 = ~preset & n_n9077 & (ndn3_27 | ~ndn3_26); + assign n5083 = ~ndn3_2 & ~preset & psv13_7_7_ & n4949_1; + assign n5084_1 = ~preset & n_n9604 & (ndn3_2 | ~n4949_1); + assign n5085 = ~preset & n_n8937 & (ndn3_29 | ~ndn3_28); + assign n5086 = ~preset & n4869_1 & (~n4969_1 ^ ~n4970); + assign n5087 = ~ndn3_2 & ~preset & psv39_9_9_ & n4949_1; + assign n5088 = ~preset & n_n8416 & (ndn3_2 | ~n4949_1); + assign n5089_1 = ~preset & n_n7653 & (nsr3_20 | ndn3_20); + assign n5090 = ~ndn3_2 & ~preset & psv33_9_9_ & n4949_1; + assign n5091 = ~preset & n_n9348 & (ndn3_2 | ~n4949_1); + assign n5092 = ~preset & n_n7136 & (~ndn3_39 | ndn3_40); + assign n5093 = ~ndn3_2 & ~preset & psv26_6_6_ & n4949_1; + assign n5094_1 = ~preset & n_n8051 & (ndn3_2 | ~n4949_1); + assign n5095 = ~preset & n_n8850 & (ngfdn_3 | ~ndn3_46); + assign n5096 = ndn3_46 & n_n9573 & ~preset & ~ngfdn_3; + assign n5097 = n4950 & (n5975 | (n4975 & n7176)); + assign n5098 = n4856 & (n_n8561 ^ ~n4999_1); + assign n5099_1 = ~preset & n_n8058 & (~ndn3_17 | ndn3_18); + assign n5100 = ~ndn3_2 & ~preset & psv26_15_15_ & n4949_1; + assign n5101 = ~preset & n_n8192 & (ndn3_2 | ~n4949_1); + assign n5102 = ~preset & n_n7949 & (nsr3_38 | ndn3_38); + assign n5103 = ~preset & n_n7792 & (ndn3_9 | ~ndn3_7); + assign n5104_1 = ~ndn3_2 & ~preset & psv18_4_4_ & n4949_1; + assign n5105 = ~preset & n_n9232 & (ndn3_2 | ~n4949_1); + assign n5106 = ~ndn3_2 & ~preset & psv13_12_12_ & n4949_1; + assign n5107 = ~preset & n_n7815 & (ndn3_2 | ~n4949_1); + assign n5108 = ~ndn3_2 & ~preset & psv2_6_6_ & n4949_1; + assign n5109_1 = ~preset & n_n7881 & (ndn3_2 | ~n4949_1); + assign n5110 = ~ndn3_2 & ~preset & psv18_0_0_ & n4949_1; + assign n5111 = ~preset & n_n8033 & (ndn3_2 | ~n4949_1); + assign n5112 = ~preset & n_n9525 & (nsr3_14 | ndn3_14); + assign n5113 = ~ndn3_2 & ~preset & psv2_0_0_ & n4949_1; + assign n5114_1 = ~preset & n_n8770 & (ndn3_2 | ~n4949_1); + assign n5115 = n4949_1 & ~ndn3_2 & pinp_6_6_ & ~preset; + assign n5116 = ~preset & n_n7644 & (ndn3_2 | ~n4949_1); + assign n5117 = ~preset & n_n8151 & (ndn3_19 | ~nen3_19); + assign n5118 = ~preset & n4865 & (~n4976 ^ ~n4977); + assign n5119_1 = ~preset & n_n8226 & (ndn3_17 | ~ndn3_16); + assign n5120 = ~preset & n_n8841 & (ndn3_23 | nsr3_23); + assign n5121 = ~preset & n_n8280 & (ndn3_19 | ~nen3_19); + assign n5122 = ~preset & n4865 & (~n4985 ^ ~n4986); + assign n5123 = ~preset & n_n7846 & (ndn3_23 | nsr3_23); + assign n5124_1 = ~preset & n_n7678 & (ndn3_42 | ~ndn3_40); + assign n5125 = n_n7862 & ndn3_40 & ~preset & ~ndn3_42; + assign n5126 = ~preset & n_n7666 & (ndn3_27 | ~ndn3_26); + assign n5127 = ~preset & n4859_1 & (~n4976 ^ ~n4977); + assign n5128 = ~preset & n_n9520 & (~nen3_22 | ndn3_22); + assign n5129_1 = ~ndn3_2 & ~preset & psv39_8_8_ & n4949_1; + assign n5130 = ~preset & n_n7956 & (ndn3_2 | ~n4949_1); + assign n5131 = ~preset & n_n7732 & (ndn3_30 | nsr3_30); + assign n5132 = ~preset & n_n7859 & (ndn3_28 | ~nen3_28); + assign n5133 = n4949_1 & ~ndn3_2 & pinp_12_12_ & ~preset; + assign n5134_1 = ~preset & n_n8108 & (ndn3_2 | ~n4949_1); + assign n5135 = ~preset & n_n9026 & (~nen3_22 | ndn3_22); + assign n5136 = ~ndn3_22 & ~preset & nen3_22 & n_n7236; + assign n5137 = ~ndn3_2 & ~preset & psv38_12_12_ & n4949_1; + assign n5138 = ~preset & n_n8088 & (ndn3_2 | ~n4949_1); + assign n5139_1 = ~ndn3_2 & ~preset & psv38_13_13_ & n4949_1; + assign n5140 = ~preset & n_n9225 & (ndn3_2 | ~n4949_1); + assign n5141 = ~preset & n_n8102 & (ndn3_42 | ~ndn3_40); + assign n5142 = ndn3_40 & n_n9542 & ~preset & ~ndn3_42; + assign n5143 = ~preset & n_n9347 & (ndn3_4 | ~ndn3_2); + assign n5144_1 = ~preset & n_n7130 & (ngfdn_3 | ~ndn3_46); + assign n5145 = ndn3_46 & n_n7527 & ~preset & ~ngfdn_3; + assign n5146 = ~preset & n_n7444 & (ndn3_46 | ~ndn3_44); + assign n5147 = ~preset & n_n9542 & (~ndn3_39 | ndn3_40); + assign n5148 = n4846 & (n4997 ^ (n6083 | n6084_1)); + assign n5149_1 = ~preset & n_n8371 & (ndn3_42 | ~ndn3_40); + assign n5150 = ndn3_40 & n_n9452 & ~preset & ~ndn3_42; + assign n5151 = ~preset & n_n9455 & (~nen3_36 | ndn3_36); + assign n5152 = ~preset & n_n9261 & (~nen3_36 | ndn3_36); + assign n5153 = ~preset & n4876 & (~n4969_1 ^ ~n4970); + assign n5154_1 = ~preset & n_n7022 & (ndn3_42 | ~ndn3_40); + assign n5155 = ~ndn3_42 & ~preset & n_n8959 & ndn3_40; + assign n5156 = ~preset & n_n8303 & (ndn3_42 | ~ndn3_40); + assign n5157 = ~ndn3_42 & ~preset & n_n8957 & ndn3_40; + assign n5158 = ~preset & n_n9593 & (ndn3_28 | ~nen3_28); + assign n5159_1 = ~preset & n4892 & (~n4969_1 ^ ~n4970); + assign n5160 = ~preset & n_n7435 & (~ndn3_42 | ndn3_44); + assign n5161 = ~ndn3_44 & ~preset & ndn3_42 & n_n7927; + assign n5162 = ~preset & n_n9313 & (ndn3_28 | ~nen3_28); + assign n5163 = ~preset & n4892 & (~n4954_1 ^ ~n4955); + assign n5164_1 = ~preset & n_n9522 & (ndn3_23 | nsr3_23); + assign n5165 = ~preset & n_n9488 & (nsr3_35 | ndn3_35); + assign n5166 = ~preset & n_n9237 & (~ndn3_42 | ndn3_44); + assign n5167 = ~preset & n_n9239 & (~ndn3_42 | ndn3_44); + assign n5168 = ~preset & n_n9452 & (~ndn3_39 | ndn3_40); + assign n5169_1 = ~preset & n_n9498 & (ndn3_13 | nsr3_13); + assign n5170 = ~preset & n_n8439 & (~ndn3_42 | ndn3_44); + assign n5171 = ~ndn3_44 & ndn3_42 & ~preset & n_n7757; + assign n5172 = ~preset & n_n8146 & (~ndn3_42 | ndn3_44); + assign n5173 = ~ndn3_44 & ndn3_42 & ~preset & n_n8024; + assign n5174_1 = ~preset & n_n9376 & (ngfdn_3 | ~ndn3_46); + assign n5175 = ndn3_46 & n_n8436 & ~preset & ~ngfdn_3; + assign n5176 = n4948 & (n5975 | (n4975 & n7176)); + assign n5177 = n4856 & n4947; + assign n5178 = ~preset & n_n7843 & (~ngfdn_3 | ndn3_50); + assign n5179_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n8256; + assign n5180 = ~ndn3_2 & ~preset & psv18_8_8_ & n4949_1; + assign n5181 = ~preset & n_n8966 & (ndn3_2 | ~n4949_1); + assign n5182 = ~preset & n_n7674 & (ndn3_46 | ~ndn3_44); + assign n5183 = n_n9237 & ndn3_44 & ~preset & ~ndn3_46; + assign n5184_1 = ~preset & n_n8727 & (ndn3_17 | ~ndn3_16); + assign n5185 = ~preset & n_n6910 & (ndn3_46 | ~ndn3_44); + assign n5186 = n_n9239 & ndn3_44 & ~preset & ~ndn3_46; + assign n5187 = ~preset & n_n9081 & (nsr3_38 | ndn3_38); + assign n5188 = ~ndn3_2 & ~preset & psv26_10_10_ & n4949_1; + assign n5189_1 = ~preset & n_n7688 & (ndn3_2 | ~n4949_1); + assign n5190 = ~preset & n_n9338 & (ndn3_25 | ~ndn3_22); + assign n5191 = ~preset & n_n9061 & (nsr3_38 | ndn3_38); + assign n5192 = ~preset & n_n7686 & (~nen3_16 | ndn3_16); + assign n5193 = ~preset & n4875 & (~n4976 ^ ~n4977); + assign n5194_1 = ~ndn3_2 & ~preset & psv33_12_12_ & n4949_1; + assign n5195 = ~preset & n_n8267 & (ndn3_2 | ~n4949_1); + assign n5196 = ~ndn3_2 & ~preset & psv39_10_10_ & n4949_1; + assign n5197 = ~preset & n_n8116 & (ndn3_2 | ~n4949_1); + assign n5198 = ~preset & n_n8296 & (~ndn3_9 | ndn3_11); + assign n5199_1 = ~preset & n4847 & (~n4971 ^ ~n4972); + assign n5200 = ~preset & n_n8344 & (ndn3_13 | nsr3_13); + assign n5201 = ~preset & n_n8326 & (ndn3_37 | nsr3_37); + assign n5202 = n4949_1 & ~ndn3_2 & pinp_0_0_ & ~preset; + assign n5203 = ~preset & n_n8011 & (ndn3_2 | ~n4949_1); + assign n5204_1 = ~preset & n_n8583 & (ndn3_17 | ~ndn3_16); + assign n5205 = n4946 & (n5975 | (n4975 & n7176)); + assign n5206 = n4856 & (n_n8993 ^ ~n5005); + assign n5207 = n4944_1 & (n5975 | (n4975 & n7176)); + assign n5208 = n4856 & n4945; + assign n5209_1 = ~preset & n_n8628 & (~ndn3_29 | ndn3_32); + assign n5210 = ~preset & n4880 & (~n4976 ^ ~n4977); + assign n5211 = ~ndn3_2 & ~preset & psv18_10_10_ & n4949_1; + assign n5212 = ~preset & n_n8586 & (ndn3_2 | ~n4949_1); + assign n5213 = ~preset & n_n9340 & (ndn3_23 | nsr3_23); + assign n5214_1 = ~ndn3_2 & ~preset & psv18_12_12_ & n4949_1; + assign n5215 = ~preset & n_n8408 & (ndn3_2 | ~n4949_1); + assign n5216 = ~ndn3_2 & ~preset & psv26_7_7_ & n4949_1; + assign n5217 = ~preset & n_n9603 & (ndn3_2 | ~n4949_1); + assign n5218 = ~preset & n_n7682 & (nsr3_35 | ndn3_35); + assign n5219_1 = ~ndn3_2 & ~preset & psv26_1_1_ & n4949_1; + assign n5220 = ~preset & n_n9322 & (ndn3_2 | ~n4949_1); + assign n5221 = ~ndn3_2 & ~preset & psv33_0_0_ & n4949_1; + assign n5222 = ~preset & n_n7511 & (ndn3_2 | ~n4949_1); + assign n5223 = ~preset & n_n7121 & (~ndn3_39 | ndn3_40); + assign n5224_1 = ~ndn3_40 & n_n7626 & ~preset & ndn3_39; + assign n5225 = ~preset & n_n8468 & (~ndn3_42 | ndn3_44); + assign n5226 = n4861 & (n4997 ^ (n6083 | n6084_1)); + assign n5227 = n4942 & (n5975 | (n4975 & n7176)); + assign n5228 = n4856 & (~n_n9031 ^ (n_n8993 | n5005)); + assign n5229_1 = ~preset & n_n9424 & (~ndn3_39 | ndn3_40); + assign n5230 = ~ndn3_40 & ~preset & ndn3_39 & n_n7346; + assign n5231 = ~preset & n_n9404 & (ndn3_7 | ~ndn3_4); + assign n5232 = ~preset & n_n9402 & (nsr3_13 | ndn3_15); + assign n5233 = ~preset & n_n8361 & (~ndn3_39 | ndn3_40); + assign n5234_1 = ~ndn3_40 & ndn3_39 & ~preset & n_n9611; + assign n5235 = ~preset & n_n7366 & (~ndn3_39 | ndn3_40); + assign n5236 = ~ndn3_40 & ndn3_39 & ~preset & n_n9613; + assign n5237 = ~preset & n_n9344 & (nsr3_14 | ndn3_14); + assign n5238 = ~preset & n_n7083 & (ndn3_46 | ~ndn3_44); + assign n5239_1 = ~preset & n_n8188 & (~ndn3_42 | ndn3_44); + assign n5240 = n4861 & (n5004_1 ^ (n6527 | n6528)); + assign n5241 = ~preset & n_n9178 & (nsr3_14 | ndn3_14); + assign n5242 = ~preset & n_n8644 & (~ndn3_39 | ndn3_40); + assign n5243 = ~ndn3_40 & ndn3_39 & ~preset & n_n8543; + assign n5244_1 = ~preset & n_n8670 & (~ndn3_42 | ndn3_44); + assign n5245 = ~ndn3_2 & ~preset & psv33_3_3_ & n4949_1; + assign n5246 = ~preset & n_n9136 & (ndn3_2 | ~n4949_1); + assign n5247 = ~preset & n_n9390 & (ndn3_34 | ~nen3_34); + assign n5248 = ~preset & n_n8789 & (ndn3_4 | ~ndn3_2); + assign n5249_1 = ~preset & n_n9046 & (ndn3_27 | ~ndn3_26); + assign n5250 = ~preset & n4859_1 & (~n4954_1 ^ ~n4955); + assign n5251 = ~preset & n_n8938 & (~ndn3_25 | ndn3_26); + assign n5252 = ~preset & n4851 & (~n4969_1 ^ ~n4970); + assign n5253 = ~preset & n_n7402 & (ndn3_46 | ~ndn3_44); + assign n5254_1 = ~ndn3_46 & ~preset & n_n9635 & ndn3_44; + assign n5255 = ~ndn3_2 & ~preset & psv26_13_13_ & n4949_1; + assign n5256 = ~preset & n_n9067 & (ndn3_2 | ~n4949_1); + assign n5257 = ~preset & n_n7715 & (~ndn3_42 | ndn3_44); + assign n5258 = ~ndn3_44 & ndn3_42 & ~preset & n_n9486; + assign n5259_1 = ~preset & n_n6980 & (~nen3_22 | ndn3_22); + assign n5260 = ~ndn3_22 & nen3_22 & ~preset & n_n9273; + assign n5261 = ~ndn3_2 & ~preset & psv38_6_6_ & n4949_1; + assign n5262 = ~preset & n_n8779 & (ndn3_2 | ~n4949_1); + assign n5263 = n4941 & (n5975 | (n4975 & n7176)); + assign n5264_1 = n4856 & n4940; + assign n5265 = ~preset & n_n8729 & (ndn3_17 | ~ndn3_16); + assign n5266 = ~preset & n4882 & (~n4971 ^ ~n4972); + assign n5267 = ~preset & n_n8916 & (ndn3_46 | ~ndn3_44); + assign n5268 = ndn3_44 & n_n8670 & ~preset & ~ndn3_46; + assign n5269_1 = ~ndn3_2 & ~preset & psv2_4_4_ & n4949_1; + assign n5270 = ~preset & n_n7827 & (ndn3_2 | ~n4949_1); + assign n5271 = ~ndn3_2 & ~preset & psv13_10_10_ & n4949_1; + assign n5272 = ~preset & n_n9119 & (ndn3_2 | ~n4949_1); + assign n5273 = ~ndn3_2 & ~preset & psv2_2_2_ & n4949_1; + assign n5274_1 = ~preset & n_n7744 & (ndn3_2 | ~n4949_1); + assign n5275 = ~preset & n_n8909 & (nsr3_14 | ndn3_14); + assign n5276 = ~ndn3_2 & ~preset & psv13_0_0_ & n4949_1; + assign n5277 = ~preset & n_n8619 & (ndn3_2 | ~n4949_1); + assign n5278 = ~preset & n_n8535 & (nsr3_14 | ndn3_14); + assign n5279_1 = ~preset & n_n9255 & (~ndn3_19 | ndn3_21); + assign n5280 = ~preset & n4885 & (~n4976 ^ ~n4977); + assign n5281 = ~preset & n_n7969 & (nsr3_14 | ndn3_14); + assign n5282 = ~preset & n_n9493 & (~nen3_22 | ndn3_22); + assign n5283 = ~preset & n_n8657 & (nsr3_20 | ndn3_20); + assign n5284_1 = ~preset & n_n8636 & (ndn3_37 | nsr3_37); + assign n5285 = ~preset & n_n8477 & (ndn3_37 | nsr3_37); + assign n5286 = ~ndn3_2 & ~preset & psv2_13_13_ & n4949_1; + assign n5287 = ~preset & n_n7890 & (ndn3_2 | ~n4949_1); + assign n5288 = n4939_1 & (n5975 | (n4975 & n7176)); + assign n5289_1 = n4856 & (~n_n8603 ^ ~n_n8798); + assign n5290 = ~ndn3_2 & ~preset & psv38_10_10_ & n4949_1; + assign n5291 = ~preset & n_n7665 & (ndn3_2 | ~n4949_1); + assign n5292 = n7208 & n4856 & n5001; + assign n5293 = ~n5001 & ~preset & n_n9353; + assign n5294_1 = ~preset & n_n9139 & (ndn3_19 | ~nen3_19); + assign n5295 = ~preset & n4865 & (~n4969_1 ^ ~n4970); + assign n5296 = ~preset & n_n8839 & (ndn3_28 | ~nen3_28); + assign n5297 = ~preset & n_n8185 & (~nen3_22 | ndn3_22); + assign n5298 = ~ndn3_22 & n_n9304 & ~preset & nen3_22; + assign n5299_1 = ~preset & n_n9155 & (~ndn3_39 | ndn3_40); + assign n5300 = ~preset & n_n9508 & (ngfdn_3 | ~ndn3_46); + assign n5301 = n1270 & (n4980 ^ (n6352 | n6353)); + assign n5302 = ~preset & n_n9126 & (~ndn3_29 | ndn3_32); + assign n5303 = ~preset & n_n9629 & (ndn3_46 | ~ndn3_44); + assign n5304_1 = n4853 & (n4997 ^ (n6083 | n6084_1)); + assign n5305 = ~preset & n_n9317 & (~nen3_16 | ndn3_16); + assign n5306 = ~preset & n4875 & (~n4954_1 ^ ~n4955); + assign n5307 = ~preset & n_n9600 & (nsr3_13 | ndn3_15); + assign n5308 = ~preset & n4881 & (~n4969_1 ^ ~n4970); + assign n5309_1 = n7207 & ((n4922 & n4935) | (n_n9537 & (n4922 | n4935))); + assign n5310 = ~n_n8821 & n4857 & (~n4934_1 ^ ~n4937); + assign n5311 = ~n4937 & ~n4934_1 & n_n8821 & n4856; + assign n5312 = ~n5001 & ~preset & n_n8821; + assign n5313 = ~preset & n_n7074 & (~ndn3_42 | ndn3_44); + assign n5314_1 = ~ndn3_44 & ndn3_42 & ~preset & n_n9355; + assign n5315 = ~preset & n_n8249 & (ndn3_42 | ~ndn3_40); + assign n5316 = ~ndn3_2 & ~preset & psv26_4_4_ & n4949_1; + assign n5317 = ~preset & n_n8617 & (ndn3_2 | ~n4949_1); + assign n5318 = ~preset & n_n7069 & (~ngfdn_3 | ndn3_50); + assign n5319_1 = ~ndn3_50 & n_n7324 & ~preset & ngfdn_3; + assign n5320 = ~ndn3_2 & ~preset & psv33_1_1_ & n4949_1; + assign n5321 = ~preset & n_n9053 & (ndn3_2 | ~n4949_1); + assign n5322 = ~preset & n_n9129 & (ndn3_27 | ~ndn3_26); + assign n5323 = ~preset & n_n9320 & (ndn3_13 | nsr3_13); + assign n5324_1 = ~ndn3_2 & ~preset & psv13_15_15_ & n4949_1; + assign n5325 = ~preset & n_n8502 & (ndn3_2 | ~n4949_1); + assign n5326 = ~ndn3_2 & ~preset & psv18_6_6_ & n4949_1; + assign n5327 = ~preset & n_n9230 & (ndn3_2 | ~n4949_1); + assign n5328 = ~ndn3_2 & ~preset & psv38_4_4_ & n4949_1; + assign n5329_1 = ~preset & n_n7600 & (ndn3_2 | ~n4949_1); + assign n5330 = ~preset & n_n8221 & (nsr3_14 | ndn3_14); + assign n5331 = ~preset & n_n9595 & (ndn3_25 | ~ndn3_22); + assign n5332 = ~preset & n4889_1 & (~n4969_1 ^ ~n4970); + assign n5333 = ~preset & n_n7642 & (~ndn3_9 | ndn3_11); + assign n5334_1 = n4949_1 & ~ndn3_2 & pinp_8_8_ & ~preset; + assign n5335 = ~preset & n_n7697 & (ndn3_2 | ~n4949_1); + assign n5336 = ~preset & n_n7108 & (~ndn3_39 | ndn3_40); + assign n5337 = ~ndn3_40 & ndn3_39 & ~preset & n_n8794; + assign n5338 = ~preset & n_n7810 & (~nen3_16 | ndn3_16); + assign n5339_1 = ~preset & n_n7781 & (ngfdn_3 | ~ndn3_46); + assign n5340 = n1270 & (n4987 ^ (n6433 | n6434)); + assign n5341 = ~preset & n_n7606 & (ngfdn_3 | ~ndn3_46); + assign n5342 = ~preset & n_n9460 & (~ndn3_19 | ndn3_21); + assign n5343 = ~preset & n4885 & (~n4985 ^ ~n4986); + assign n5344_1 = ~preset & n_n8473 & (ndn3_25 | ~ndn3_22); + assign n5345 = ~preset & n_n8224 & (ndn3_29 | ~ndn3_28); + assign n5346 = ~ndn3_2 & ~preset & psv39_2_2_ & n4949_1; + assign n5347 = ~preset & n_n7837 & (ndn3_2 | ~n4949_1); + assign n5348 = ~preset & n_n8581 & (~ndn3_25 | ndn3_26); + assign n5349_1 = ~preset & n_n8213 & (~ndn3_19 | ndn3_21); + assign n5350 = ~preset & n4885 & (~n4969_1 ^ ~n4970); + assign n5351 = ~preset & n_n9092 & (ndn3_30 | nsr3_30); + assign n5352 = ~preset & n_n8781 & (~nen3_22 | ndn3_22); + assign n5353 = ~ndn3_22 & ~preset & nen3_22 & n_n9255; + assign n5354_1 = ~preset & n_n7990 & (nsr3_35 | ndn3_35); + assign n5355 = ~preset & n_n8470 & (~ndn3_42 | ndn3_44); + assign n5356 = ~preset & n_n9394 & (ndn3_30 | nsr3_30); + assign n5357 = ~preset & n_n9355 & (ndn3_42 | ~ndn3_40); + assign n5358 = n4863 & (n4997 ^ (n6083 | n6084_1)); + assign n5359_1 = ~preset & n_n7739 & (~nen3_22 | ndn3_22); + assign n5360 = n7202 & (n_n8930 | ~n4967 | ~n7089); + assign n5361 = n7203 & n7089 & ~n_n8930 & n4967; + assign n5362 = ~preset & n_n7728 & (~nen3_22 | ndn3_22); + assign n5363 = ~preset & n_n8045 & (ndn3_42 | ~ndn3_40); + assign n5364_1 = n_n7136 & ndn3_40 & ~preset & ~ndn3_42; + assign n5365 = ~preset & n_n9128 & (~nen3_36 | ndn3_36); + assign n5366 = ~preset & n_n9159 & (ndn3_28 | ~nen3_28); + assign n5367 = ~preset & n_n9591 & (nsr3_35 | ndn3_35); + assign n5368 = ~preset & n_n9393 & (nsr3_35 | ndn3_35); + assign n5369_1 = ~preset & n_n8263 & (~ngfdn_3 | ndn3_50); + assign n5370 = ~ndn3_50 & n_n8081 & ~preset & ngfdn_3; + assign n5371 = ~preset & n_n7848 & (~ndn3_9 | ndn3_11); + assign n5372 = ~preset & n4847 & (~n4985 ^ ~n4986); + assign n5373 = ~preset & n_n7626 & (~nen3_39 | ndn3_39); + assign n5374_1 = ~preset & n4854_1 & (~n4971 ^ ~n4972); + assign n5375 = ~preset & n_n9421 & (ndn3_46 | ~ndn3_44); + assign n5376 = ~ndn3_46 & ~preset & n_n7691 & ndn3_44; + assign n5377 = ~preset & n_n7849 & (ndn3_9 | ~ndn3_7); + assign n5378 = ~preset & n4852 & (~n4985 ^ ~n4986); + assign n5379_1 = ~preset & n_n7873 & (nsr3_38 | ndn3_38); + assign n5380 = ~ndn3_2 & ~preset & psv33_14_14_ & n4949_1; + assign n5381 = ~preset & n_n7914 & (ndn3_2 | ~n4949_1); + assign n5382 = ~preset & n_n7668 & (ndn3_9 | ~ndn3_7); + assign n5383 = ~preset & n4852 & (~n4976 ^ ~n4977); + assign n5384_1 = ~preset & n_n7925 & (ndn3_30 | nsr3_30); + assign n5385 = ~preset & n_n8256 & (ngfdn_3 | ~ndn3_46); + assign n5386 = ~preset & n_n7711 & (ndn3_23 | nsr3_23); + assign n5387 = ~preset & n_n7971 & (ndn3_4 | ~ndn3_2); + assign n5388 = ~preset & n_n8064 & (nsr3_20 | ndn3_20); + assign n5389_1 = ~preset & n_n7932 & (~nen3_22 | ndn3_22); + assign n5390 = ~preset & n_n8233 & (nsr3_13 | ndn3_15); + assign n5391 = ~preset & n4881 & (~n4971 ^ ~n4972); + assign n5392 = ~preset & n_n8003 & (ndn3_25 | ~ndn3_22); + assign n5393 = n7201 & ((n4895 & n4921) | (n_n9416 & (n4895 | n4921))); + assign n5394_1 = ~n_n9537 & n4857 & (~n4922 ^ ~n4935); + assign n5395 = ~n4935 & ~n4922 & n_n9537 & n4856; + assign n5396 = ~n5001 & ~preset & n_n9537; + assign n5397 = n7200 & ((n4870 & n4871) | (n_n9638 & (n4870 | n4871))); + assign n5398 = ~n_n9448 & n4857 & (~n4872 ^ ~n4933); + assign n5399_1 = ~n4933 & ~n4872 & n_n9448 & n4856; + assign n5400 = ~n5001 & ~preset & n_n9448; + assign n5401 = ~preset & n_n9221 & (ndn3_46 | ~ndn3_44); + assign n5402 = ~preset & n_n9104 & (~ndn3_39 | ndn3_40); + assign n5403 = ~preset & n_n8277 & (~ndn3_29 | ndn3_32); + assign n5404_1 = ~preset & n4880 & (~n4985 ^ ~n4986); + assign n5405 = ~preset & n_n8743 & (ndn3_19 | ~nen3_19); + assign n5406 = ~preset & n4865 & (~n4954_1 ^ ~n4955); + assign n5407 = ~ndn3_2 & ~preset & psv33_2_2_ & n4949_1; + assign n5408 = ~preset & n_n7554 & (ndn3_2 | ~n4949_1); + assign n5409_1 = n7199 & ((n4914_1 & n4951) | (n_n8419 & (n4914_1 | n4951))); + assign n5410 = ~n_n8449 & n4857 & (~n4931 ^ ~n4932); + assign n5411 = ~n4932 & ~n4931 & n_n8449 & n4856; + assign n5412 = ~n5001 & ~preset & n_n8449; + assign n5413 = ~preset & n_n8384 & (~nen3_22 | ndn3_22); + assign n5414_1 = ~ndn3_22 & ~preset & nen3_22 & n_n8464; + assign n5415 = ~ndn3_2 & ~preset & psv38_3_3_ & n4949_1; + assign n5416 = ~preset & n_n9212 & (ndn3_2 | ~n4949_1); + assign n5417 = ~preset & n_n9050 & (~ndn3_9 | ndn3_11); + assign n5418 = ~preset & n4847 & (~n4954_1 ^ ~n4955); + assign n5419_1 = ~preset & n_n9570 & (ngfdn_3 | ~ndn3_46); + assign n5420 = n1270 & (n5004_1 ^ (n6527 | n6528)); + assign n5421 = ~preset & n_n9028 & (ngfdn_3 | ~ndn3_46); + assign n5422 = ~preset & n_n9626 & (ngfdn_3 | ~ndn3_46); + assign n5423 = ~ndn3_2 & ~preset & psv39_7_7_ & n4949_1; + assign n5424_1 = ~preset & n_n9605 & (ndn3_2 | ~n4949_1); + assign n5425 = ~preset & n_n6968 & (nsr3_35 | ndn3_35); + assign n5426 = ~preset & n_n7390 & (~ndn3_39 | ndn3_40); + assign n5427 = ~ndn3_40 & ~preset & ndn3_39 & n_n7334; + assign n5428 = ~ndn3_2 & ~preset & psv33_7_7_ & n4949_1; + assign n5429_1 = ~preset & n_n9270 & (ndn3_2 | ~n4949_1); + assign n5430 = ~preset & n_n7284 & (ndn3_46 | ~ndn3_44); + assign n5431 = ~ndn3_46 & ~preset & n_n7898 & ndn3_44; + assign n5432 = ~preset & n_n9403 & (ndn3_13 | nsr3_13); + assign n5433 = ~preset & n_n9308 & (ndn3_34 | ~nen3_34); + assign n5434_1 = ~preset & n4860 & (~n4954_1 ^ ~n4955); + assign n5435 = ~preset & n_n8584 & (~ndn3_11 | ndn3_12); + assign n5436 = ~ndn3_2 & ~preset & psv26_14_14_ & n4949_1; + assign n5437 = ~preset & n_n7946 & (ndn3_2 | ~n4949_1); + assign n5438 = ~preset & n_n7420 & (~ngfdn_3 | ndn3_50); + assign n5439_1 = ~ndn3_50 & ngfdn_3 & ~preset & n_n7558; + assign n5440 = ~ndn3_2 & ~preset & psv18_2_2_ & n4949_1; + assign n5441 = ~preset & n_n7737 & (ndn3_2 | ~n4949_1); + assign n5442 = ~ndn3_2 & ~preset & psv39_11_11_ & n4949_1; + assign n5443 = ~preset & n_n8506 & (ndn3_2 | ~n4949_1); + assign n5444_1 = ~preset & n_n7598 & (~ndn3_29 | ndn3_32); + assign n5445 = ~preset & n4880 & (~n4971 ^ ~n4972); + assign n5446 = ~preset & n_n8328 & (ndn3_37 | nsr3_37); + assign n5447 = n4929_1 & (n5975 | (n4975 & n7176)); + assign n5448 = n4856 & n4928; + assign n5449_1 = ~preset & n_n9205 & (~ndn3_25 | ndn3_26); + assign n5450 = ~preset & n_n8004 & (~nen3_22 | ndn3_22); + assign n5451 = n4866 & (n4997 ^ (n6083 | n6084_1)); + assign n5452 = ~preset & n_n8061 & (ndn3_42 | ~ndn3_40); + assign n5453 = ~ndn3_42 & ~preset & n_n9104 & ndn3_40; + assign n5454_1 = ~ndn3_2 & ~preset & psv39_6_6_ & n4949_1; + assign n5455 = ~preset & n_n9121 & (ndn3_2 | ~n4949_1); + assign n5456 = ~preset & n_n8436 & (ndn3_46 | ~ndn3_44); + assign n5457 = n4853 & (n4987 ^ (n6433 | n6434)); + assign n5458 = ~preset & n_n9309 & (ndn3_42 | ~ndn3_40); + assign n5459_1 = ~preset & n_n9259 & (~ndn3_42 | ndn3_44); + assign n5460 = ~preset & n_n7476 & (~nsr1_2 | nlc1_2); + assign n5461 = ~nlc1_2 & nsr1_2 & ~preset_0_0_ & ~preset; + assign n5462 = ~ndn3_2 & ~preset & psv26_9_9_ & n4949_1; + assign n5463 = ~preset & n_n7424 & (ndn3_2 | ~n4949_1); + assign n5464_1 = ~ndn3_2 & ~preset & psv33_4_4_ & n4949_1; + assign n5465 = ~preset & n_n7604 & (ndn3_2 | ~n4949_1); + assign n5466 = ~preset & n_n7649 & (ndn3_27 | ~ndn3_26); + assign n5467 = ~preset & n_n7976 & (ngfdn_3 | ~ndn3_46); + assign n5468 = ndn3_46 & n_n8765 & ~preset & ~ngfdn_3; + assign n5469_1 = ~preset & n_n8898 & (ndn3_34 | ~nen3_34); + assign n5470 = ~preset & n4860 & (~n4971 ^ ~n4972); + assign n5471 = ~preset & n_n8222 & (ndn3_34 | ~nen3_34); + assign n5472 = ~preset & n_n7964 & (ndn3_46 | ~ndn3_44); + assign n5473 = ~ndn3_46 & ~preset & n_n9041 & ndn3_44; + assign n5474_1 = ~preset & n_n7706 & (~ndn3_42 | ndn3_44); + assign n5475 = ~preset & n_n9318 & (~ndn3_11 | ndn3_12); + assign n5476 = ~preset & n4849_1 & (~n4954_1 ^ ~n4955); + assign n5477 = n4949_1 & ~ndn3_2 & pinp_7_7_ & ~preset; + assign n5478 = ~preset & n_n9271 & (ndn3_2 | ~n4949_1); + assign n5479_1 = ~preset & n_n9042 & (~ndn3_29 | ndn3_32); + assign n5480 = ~preset & n4880 & (~n4954_1 ^ ~n4955); + assign n5481 = n4926 & (n5975 | (n4975 & n7176)); + assign n5482 = n4856 & n4927; + assign n5483 = n4925 & (n5975 | (n4975 & n7176)); + assign n5484_1 = n4856 & ((n_n8923 & (~n_n8603 | n_n8798)) | (n_n8603 & ~n_n8923 & ~n_n8798)); + assign n5485 = n_n9248 & (~n_n9247 | ~n4902) & n7198; + assign n5486 = ~n4902 & n_n9247 & ~preset & n_n9248; + assign n5487 = ~preset & n_n9252 & (~ndn3_19 | ndn3_21); + assign n5488 = ~preset & n4885 & (~n4971 ^ ~n4972); + assign n5489_1 = ~preset & n_n9576 & (~ndn3_39 | ndn3_40); + assign n5490 = ~preset & n_n6920 & (ndn3_46 | ~ndn3_44); + assign n5491 = ndn3_44 & n_n8470 & ~preset & ~ndn3_46; + assign n5492 = ~ndn3_2 & ~preset & psv38_8_8_ & n4949_1; + assign n5493 = ~preset & n_n7692 & (ndn3_2 | ~n4949_1); + assign n5494_1 = ~ndn3_2 & ~preset & psv2_8_8_ & n4949_1; + assign n5495 = ~preset & n_n9023 & (ndn3_2 | ~n4949_1); + assign n5496 = ~preset & n_n9059 & (nsr3_38 | ndn3_38); + assign n5497 = ~preset & n_n7809 & (~nen3_22 | ndn3_22); + assign n5498 = n4866 & (n4980 ^ (n6352 | n6353)); + assign n5499_1 = ~preset & n_n8889 & (ndn3_28 | ~nen3_28); + assign n5500 = ~preset & n4892 & (~n4976 ^ ~n4977); + assign n5501 = ~preset & n_n8253 & (~nen3_36 | ndn3_36); + assign n5502 = ~preset & n4876 & (~n4971 ^ ~n4972); + assign n5503 = ~preset & n_n7845 & (ndn3_27 | ~ndn3_26); + assign n5504_1 = ~preset & n4859_1 & (~n4985 ^ ~n4986); + assign n5505 = ~preset & n_n8989 & (ndn3_42 | ~ndn3_40); + assign n5506 = n4863 & (n4987 ^ (n6433 | n6434)); + assign n5507 = ~preset & n_n8223 & (~ndn3_29 | ndn3_32); + assign n5508 = ~preset & n_n9171 & (~ndn3_42 | ndn3_44); + assign n5509_1 = ~preset & n_n7879 & (ndn3_13 | nsr3_13); + assign n5510 = ~preset & n_n9186 & (ndn3_13 | nsr3_13); + assign n5511 = ~preset & n_n7885 & (nsr3_38 | ndn3_38); + assign n5512 = ~preset & n_n7966 & (ndn3_37 | nsr3_37); + assign n5513 = ~preset & n_n8081 & (ngfdn_3 | ~ndn3_46); + assign n5514_1 = n1270 & (n4997 ^ (n6083 | n6084_1)); + assign n5515 = ~preset & n_n9219 & (ngfdn_3 | ~ndn3_46); + assign n5516 = ~preset & n_n9043 & (ndn3_37 | nsr3_37); + assign n5517 = n4923 & (n5975 | (n4975 & n7176)); + assign n5518 = n4856 & (n_n8933 ^ ~n5000); + assign n5519_1 = ~preset & n_n8100 & (~ndn3_39 | ndn3_40); + assign n5520 = ~ndn3_40 & ndn3_39 & ~preset & n_n8871; + assign n5521 = ~preset & n_n9266 & (nsr3_14 | ndn3_14); + assign n5522 = ~preset & n_n7429 & (ndn3_19 | ~nen3_19); + assign n5523 = ~preset & n4865 & (~n4971 ^ ~n4972); + assign n5524_1 = ~preset & n_n8791 & (ndn3_4 | ~ndn3_2); + assign n5525 = ~preset & n4874_1 & (~n4971 ^ ~n4972); + assign n5526 = ~preset & n_n7624 & (~nen3_39 | ndn3_39); + assign n5527 = ~preset & n_n9535 & (~ndn3_42 | ndn3_44); + assign n5528 = ~ndn3_44 & ndn3_42 & ~preset & n_n9309; + assign n5529_1 = ~preset & n_n8396 & (ndn3_13 | nsr3_13); + assign n5530 = ~preset & n_n7813 & (ndn3_7 | ~ndn3_4); + assign n5531 = ~ndn3_2 & ~preset & psv38_0_0_ & n4949_1; + assign n5532 = ~preset & n_n7509 & (ndn3_2 | ~n4949_1); + assign n5533 = ~preset & n_n7980 & (ndn3_30 | nsr3_30); + assign n5534_1 = ~preset & n_n7667 & (ndn3_23 | nsr3_23); + assign n5535 = ~preset & n_n7761 & (nsr3_20 | ndn3_20); + assign n5536 = ~preset & n_n7683 & (ndn3_25 | ~ndn3_22); + assign n5537 = ~preset & n4889_1 & (~n4976 ^ ~n4977); + assign n5538 = ~preset & n_n8177 & (ndn3_29 | ~ndn3_28); + assign n5539_1 = ~preset & n4869_1 & (~n4976 ^ ~n4977); + assign n5540 = ~preset & n_n7793 & (ndn3_4 | ~ndn3_2); + assign n5541 = ~ndn3_2 & ~preset & psv2_12_12_ & n4949_1; + assign n5542 = ~preset & n_n7817 & (ndn3_2 | ~n4949_1); + assign n5543 = ~preset & n_n7225 & (nsr3_20 | ndn3_20); + assign n5544_1 = ~preset & n_n7808 & (ndn3_30 | nsr3_30); + assign n5545 = ~preset & n_n6963 & (ndn3_42 | ~ndn3_40); + assign n5546 = ~ndn3_42 & ~preset & n_n9155 & ndn3_40; + assign n5547 = ~preset & n_n7392 & (~nen3_22 | ndn3_22); + assign n5548 = ~ndn3_22 & ~preset & nen3_22 & n_n9586; + assign n5549_1 = ~ndn3_2 & ~preset & psv33_8_8_ & n4949_1; + assign n5550 = ~preset & n_n9302 & (ndn3_2 | ~n4949_1); + assign n5551 = ~preset & n_n9458 & (ndn3_34 | ~nen3_34); + assign n5552 = ~preset & n_n8801 & (~ndn3_42 | ndn3_44); + assign n5553 = ~ndn3_44 & ndn3_42 & ~preset & n_n8247; + assign n5554_1 = ~ndn3_2 & ~preset & psv18_3_3_ & n4949_1; + assign n5555 = ~preset & n_n9396 & (ndn3_2 | ~n4949_1); + assign n5556 = ~preset & n_n7231 & (~nen3_22 | ndn3_22); + assign n5557 = ~ndn3_22 & ~preset & nen3_22 & n_n8093; + assign n5558 = ~preset & n_n9312 & (ndn3_30 | nsr3_30); + assign n5559_1 = ~preset & n_n8856 & (~nen3_22 | ndn3_22); + assign n5560 = n4866 & (n5004_1 ^ (n6527 | n6528)); + assign n5561 = ~n5975 & n7196 & (~n4975 | ~n7176); + assign n5562 = ~n6866 & ~n6865 & n_n8603 & ~n4856; + assign n5563 = n7192 & ((n4893 & n4894_1) | (n_n9434 & (n4893 | n4894_1))); + assign n5564_1 = ~n_n9416 & n4857 & (~n4895 ^ ~n4921); + assign n5565 = ~n4921 & ~n4895 & n_n9416 & n4856; + assign n5566 = ~n5001 & ~preset & n_n9416; + assign n5567 = ~ndn3_2 & ~preset & psv39_1_1_ & n4949_1; + assign n5568 = ~preset & n_n9324 & (ndn3_2 | ~n4949_1); + assign n5569_1 = ~ndn3_2 & ~preset & psv33_5_5_ & n4949_1; + assign n5570 = ~preset & n_n9182 & (ndn3_2 | ~n4949_1); + assign n5571 = ~preset & n_n9278 & (~ngfdn_3 | ndn3_50); + assign n5572 = ~ndn3_50 & ~preset & ngfdn_3 & n_n7781; + assign n5573 = ~preset & n_n8014 & (ndn3_9 | ~ndn3_7); + assign n5574_1 = ~preset & n_n8961 & (ndn3_9 | ~ndn3_7); + assign n5575 = ~ndn3_2 & ~preset & psv13_6_6_ & n4949_1; + assign n5576 = ~preset & n_n7880 & (ndn3_2 | ~n4949_1); + assign n5577 = ~ndn3_2 & ~preset & psv13_11_11_ & n4949_1; + assign n5578 = ~preset & n_n7766 & (ndn3_2 | ~n4949_1); + assign n5579_1 = ~preset & n_n7687 & (nsr3_13 | ndn3_15); + assign n5580 = ~preset & n4881 & (~n4976 ^ ~n4977); + assign n5581 = ~preset & n_n7685 & (nsr3_20 | ndn3_20); + assign n5582 = ~preset & n_n8281 & (ndn3_17 | ~ndn3_16); + assign n5583 = ~preset & n4882 & (~n4985 ^ ~n4986); + assign n5584_1 = n4949_1 & ~ndn3_2 & pinp_2_2_ & ~preset; + assign n5585 = ~preset & n_n8009 & (ndn3_2 | ~n4949_1); + assign n5586 = ~preset & n_n7825 & (ndn3_7 | ~ndn3_4); + assign n5587 = ~preset & n4879_1 & (~n4971 ^ ~n4972); + assign n5588 = ~preset & n_n7878 & (nsr3_13 | ndn3_15); + assign n5589_1 = ~preset & n_n7395 & (ndn3_42 | ~ndn3_40); + assign n5590 = n_n8206 & ndn3_40 & ~preset & ~ndn3_42; + assign n5591 = ~preset & n_n9327 & (ndn3_28 | ~nen3_28); + assign n5592 = ~preset & n_n9176 & (ndn3_23 | nsr3_23); + assign n5593 = ~preset & n_n7756 & (~ndn3_19 | ndn3_21); + assign n5594_1 = ~preset & n_n8464 & (~ndn3_19 | ndn3_21); + assign n5595 = ~preset & n_n7734 & (nsr3_35 | ndn3_35); + assign n5596 = ~ndn3_2 & ~preset & psv26_5_5_ & n4949_1; + assign n5597 = ~preset & n_n9500 & (ndn3_2 | ~n4949_1); + assign n5598 = ~preset & n_n7650 & (nsr3_35 | ndn3_35); + assign n5599_1 = ~preset & n_n7807 & (nsr3_35 | ndn3_35); + assign n5600 = ~preset & n_n8794 & (~nen3_39 | ndn3_39); + assign n5601 = ~preset & n_n7360 & (~nen3_22 | ndn3_22); + assign n5602 = ~ndn3_22 & ~preset & nen3_22 & n_n7756; + assign n5603 = ~preset & n_n8984 & (~ndn3_11 | ndn3_12); + assign n5604_1 = ~preset & n_n9599 & (~ndn3_11 | ndn3_12); + assign n5605 = ~preset & n4849_1 & (~n4969_1 ^ ~n4970); + assign n5606 = ~ndn3_2 & ~preset & psv13_9_9_ & n4949_1; + assign n5607 = ~preset & n_n7866 & (ndn3_2 | ~n4949_1); + assign n5608 = ~preset & n_n8486 & (~ngfdn_3 | ndn3_50); + assign n5609_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9626; + assign n5610 = ~ndn3_2 & ~preset & psv18_1_1_ & n4949_1; + assign n5611 = ~preset & n_n9314 & (ndn3_2 | ~n4949_1); + assign n5612 = ~preset & n_n8073 & (~ndn3_39 | ndn3_40); + assign n5613 = ~ndn3_40 & n_n7624 & ~preset & ndn3_39; + assign n5614_1 = ~preset & n_n7896 & (ndn3_46 | ~ndn3_44); + assign n5615 = n4949_1 & ~ndn3_2 & pinp_9_9_ & ~preset; + assign n5616 = ~preset & n_n9349 & (ndn3_2 | ~n4949_1); + assign n5617 = ~ndn3_2 & ~preset & psv13_1_1_ & n4949_1; + assign n5618 = ~preset & n_n9323 & (ndn3_2 | ~n4949_1); + assign n5619_1 = ~ndn3_2 & ~preset & pinp_5_5_ & n4949_1; + assign n5620 = ~preset & n_n9183 & (ndn3_2 | ~n4949_1); + assign n5621 = ~preset & n_n8854 & (~nen3_22 | ndn3_22); + assign n5622 = n4949_1 & ~ndn3_2 & pinp_3_3_ & ~preset; + assign n5623 = ~preset & n_n9137 & (ndn3_2 | ~n4949_1); + assign n5624_1 = ~preset & n_n9319 & (nsr3_13 | ndn3_15); + assign n5625 = ~preset & n4881 & (~n4954_1 ^ ~n4955); + assign n5626 = n7187 & ((n4912 & n4938) | (n_n9353 & (n4912 | n4938))); + assign n5627 = ~preset & n_n9395 & (ndn3_28 | ~nen3_28); + assign n5628 = ~preset & n_n7923 & (~ngfdn_3 | ndn3_50); + assign n5629_1 = ~ndn3_50 & ngfdn_3 & ~preset & n_n7779; + assign n5630 = ~preset & n_n8833 & (ndn3_13 | nsr3_13); + assign n5631 = ~preset & n_n8276 & (~ndn3_9 | ndn3_11); + assign n5632 = ~preset & n4847 & (~n4976 ^ ~n4977); + assign n5633 = ~preset & n_n7514 & (ndn3_46 | ~ndn3_44); + assign n5634_1 = ndn3_44 & n_n8188 & ~preset & ~ndn3_46; + assign n5635 = ~ndn3_2 & ~preset & psv33_15_15_ & n4949_1; + assign n5636 = ~preset & n_n8456 & (ndn3_2 | ~n4949_1); + assign n5637 = ~ndn3_2 & ~preset & psv39_13_13_ & n4949_1; + assign n5638 = ~preset & n_n8504 & (ndn3_2 | ~n4949_1); + assign n5639_1 = ~preset & n_n7950 & (ndn3_30 | nsr3_30); + assign n5640 = ~preset & n_n9315 & (ndn3_25 | ~ndn3_22); + assign n5641 = ~preset & n4889_1 & (~n4954_1 ^ ~n4955); + assign n5642 = ~preset & n_n8402 & (~ndn3_17 | ndn3_18); + assign n5643 = ~preset & n_n7684 & (~nen3_22 | ndn3_22); + assign n5644_1 = ~preset & n_n8552 & (~nen3_36 | ndn3_36); + assign n5645 = ~ndn3_2 & ~preset & psv39_4_4_ & n4949_1; + assign n5646 = ~preset & n_n7835 & (ndn3_2 | ~n4949_1); + assign n5647 = ~ndn3_2 & ~preset & psv2_10_10_ & n4949_1; + assign n5648 = ~preset & n_n7689 & (ndn3_2 | ~n4949_1); + assign n5649_1 = ~preset & n_n9494 & (nsr3_20 | ndn3_20); + assign n5650 = ~preset & n_n8982 & (ndn3_19 | ~nen3_19); + assign n5651 = ~preset & n_n8095 & (nsr3_35 | ndn3_35); + assign n5652 = ~preset & n_n8900 & (ndn3_30 | nsr3_30); + assign n5653 = ~preset & n_n8210 & (nsr3_14 | ndn3_14); + assign n5654_1 = ~preset & n_n8626 & (ndn3_34 | ~nen3_34); + assign n5655 = ~preset & n4860 & (~n4985 ^ ~n4986); + assign n5656 = ~preset & n_n7988 & (nsr3_35 | ndn3_35); + assign n5657 = ~preset & n_n8906 & (~nen3_39 | ndn3_39); + assign n5658 = ~preset & n4854_1 & (~n4969_1 ^ ~n4970); + assign n5659_1 = ~preset & n_n9268 & (ndn3_9 | ~ndn3_7); + assign n5660 = ~preset & n4852 & (~n4969_1 ^ ~n4970); + assign n5661 = ~preset & n_n8983 & (ndn3_17 | ~ndn3_16); + assign n5662 = ~preset & n_n7256 & (ndn3_46 | ~ndn3_44); + assign n5663 = ~ndn3_46 & ~preset & n_n9171 & ndn3_44; + assign n5664_1 = ~preset & n_n8939 & (ndn3_17 | ~ndn3_16); + assign n5665 = ~preset & n4882 & (~n4969_1 ^ ~n4970); + assign n5666 = ~ndn3_2 & ~preset & psv2_9_9_ & n4949_1; + assign n5667 = ~preset & n_n8739 & (ndn3_2 | ~n4949_1); + assign n5668 = ~preset & n_n9366 & (~ndn3_39 | ndn3_40); + assign n5669_1 = ~ndn3_40 & n_n7464 & ~preset & ndn3_39; + assign n5670 = ~preset & n_n9310 & (nsr3_38 | ndn3_38); + assign n5671 = ~preset & n_n7570 & (ndn3_46 | ~ndn3_44); + assign n5672 = n4853 & (n4980 ^ (n6352 | n6353)); + assign n5673 = ~preset & n_n9470 & (~ndn3_29 | ndn3_32); + assign n5674_1 = ~preset & n4880 & (~n4969_1 ^ ~n4970); + assign n5675 = ~preset & n_n9623 & (ndn3_42 | ~ndn3_40); + assign n5676 = ~preset & n_n9609 & (~ndn3_39 | ndn3_40); + assign n5677 = ~ndn3_2 & ~preset & psv2_1_1_ & n4949_1; + assign n5678 = ~preset & n_n9325 & (ndn3_2 | ~n4949_1); + assign n5679_1 = ~preset & n_n9342 & (~nen3_16 | ndn3_16); + assign n5680 = n4949_1 & ~ndn3_2 & pinp_1_1_ & ~preset; + assign n5681 = ~preset & n_n9054 & (ndn3_2 | ~n4949_1); + assign n5682 = ~preset & n_n7822 & (~nen3_22 | ndn3_22); + assign n5683 = ~ndn3_2 & ~preset & psv39_5_5_ & n4949_1; + assign n5684_1 = ~preset & n_n9502 & (ndn3_2 | ~n4949_1); + assign n5685 = ~preset & n_n8741 & (ndn3_29 | ~ndn3_28); + assign n5686 = ~preset & n4869_1 & (~n4954_1 ^ ~n4955); + assign n5687 = ~preset & n_n9371 & (~ndn3_39 | ndn3_40); + assign n5688 = ~ndn3_40 & ndn3_39 & ~preset & n_n8611; + assign n5689_1 = ~preset & n_n8980 & (ndn3_34 | ~nen3_34); + assign n5690 = ~ndn3_2 & ~preset & psv26_2_2_ & n4949_1; + assign n5691 = ~preset & n_n7743 & (ndn3_2 | ~n4949_1); + assign n5692 = ~preset & n_n9429 & (~ngfdn_3 | ndn3_50); + assign n5693 = ~ndn3_50 & n_n7217 & ~preset & ngfdn_3; + assign n5694_1 = ~preset & n_n6961 & (~ndn3_42 | ndn3_44); + assign n5695 = ~ndn3_44 & ndn3_42 & ~preset & n_n8989; + assign n5696 = ~preset & n_n8809 & (~ndn3_25 | ndn3_26); + assign n5697 = ~preset & n_n8340 & (ndn3_46 | ~ndn3_44); + assign n5698 = ndn3_44 & n_n8468 & ~preset & ~ndn3_46; + assign n5699_1 = ~ndn3_2 & ~preset & psv39_14_14_ & n4949_1; + assign n5700 = ~preset & n_n7936 & (ndn3_2 | ~n4949_1); + assign n5701 = ~preset & n_n8430 & (~ndn3_39 | ndn3_40); + assign n5702 = ~ndn3_40 & ndn3_39 & ~preset & n_n9106; + assign n5703 = ~preset & n_n9596 & (~nen3_22 | ndn3_22); + assign n5704_1 = ~preset & n_n7876 & (~nen3_16 | ndn3_16); + assign n5705 = n4917 & (n5975 | (n4975 & n7176)); + assign n5706 = n4856 & (~n_n8911 ^ (n_n8933 | n5000)); + assign n5707 = ~preset & n_n7887 & (ndn3_25 | ~ndn3_22); + assign n5708 = ~preset & n4889_1 & (~n4985 ^ ~n4986); + assign n5709_1 = ~preset & n_n8760 & (ndn3_4 | ~ndn3_2); + assign n5710 = ~preset & n4874_1 & (~n4976 ^ ~n4977); + assign n5711 = ~preset & n_n9264 & (ndn3_23 | nsr3_23); + assign n5712 = ~ndn3_2 & ~preset & psv39_0_0_ & n4949_1; + assign n5713 = ~preset & n_n7657 & (ndn3_2 | ~n4949_1); + assign n5714_1 = ~preset & n_n9102 & (~ndn3_39 | ndn3_40); + assign n5715 = n4846 & (n4987 ^ (n6433 | n6434)); + assign n5716 = ~preset & n_n9316 & (nsr3_20 | ndn3_20); + assign n5717 = ~preset & n_n7929 & (ndn3_30 | nsr3_30); + assign n5718 = ~preset & n_n7962 & (~ndn3_39 | ndn3_40); + assign n5719_1 = n4846 & (n4996 ^ (n6545 | n6546)); + assign n5720 = ~ndn3_2 & ~preset & psv18_14_14_ & n4949_1; + assign n5721 = ~preset & n_n7930 & (ndn3_2 | ~n4949_1); + assign n5722 = ~preset & n_n8864 & (~ndn3_29 | ndn3_32); + assign n5723 = n7186 & ((n4872 & n4933) | (n_n9448 & (n4872 | n4933))); + assign n5724_1 = ~n_n8354 & n4857 & (~n4915 ^ ~n4916); + assign n5725 = ~n4916 & ~n4915 & n_n8354 & n4856; + assign n5726 = ~n5001 & ~preset & n_n8354; + assign n5727 = ~preset & n_n7789 & (~nen3_36 | ndn3_36); + assign n5728 = ~preset & n_n8543 & (~nen3_39 | ndn3_39); + assign n5729_1 = ~preset & n4854_1 & (~n4976 ^ ~n4977); + assign n5730 = ~preset & n_n8480 & (ndn3_37 | nsr3_37); + assign n5731 = ~preset & n_n9487 & (nsr3_38 | ndn3_38); + assign n5732 = ~preset & n_n7967 & (~nen3_36 | ndn3_36); + assign n5733 = ~preset & n_n8744 & (ndn3_17 | ~ndn3_16); + assign n5734_1 = ~preset & n4882 & (~n4954_1 ^ ~n4955); + assign n5735 = ~preset & n_n8022 & (ndn3_42 | ~ndn3_40); + assign n5736 = n4863 & (n4980 ^ (n6352 | n6353)); + assign n5737 = ~preset & n_n9592 & (ndn3_30 | nsr3_30); + assign n5738 = ~preset & n_n8808 & (ndn3_29 | ~ndn3_28); + assign n5739_1 = ~preset & n_n9044 & (~nen3_36 | ndn3_36); + assign n5740 = ~preset & n4876 & (~n4954_1 ^ ~n4955); + assign n5741 = ~ndn3_2 & ~preset & psv39_3_3_ & n4949_1; + assign n5742 = ~preset & n_n9407 & (ndn3_2 | ~n4949_1); + assign n5743 = ~preset & n_n9132 & (nsr3_14 | ndn3_14); + assign n5744_1 = ~preset & n_n9337 & (ndn3_27 | ~ndn3_26); + assign n5745 = ~preset & n_n8589 & (ngfdn_3 | ~ndn3_46); + assign n5746 = n_n9221 & ndn3_46 & ~preset & ~ngfdn_3; + assign n5747 = ~preset & n_n7603 & (~ndn3_17 | ndn3_18); + assign n5748 = ~preset & n4877 & (~n4971 ^ ~n4972); + assign n5749_1 = n4908 & (n5975 | (n4975 & n7176)); + assign n5750 = n4856 & ((~n_n8913 & ~n_n8964 & ~n4968) | (n_n8964 & (n_n8913 | n4968))); + assign n5751 = ~ndn3_2 & ~preset & psv38_2_2_ & n4949_1; + assign n5752 = ~preset & n_n8638 & (ndn3_2 | ~n4949_1); + assign n5753 = ~preset & n_n7017 & (~nen3_22 | ndn3_22); + assign n5754_1 = ~ndn3_22 & ~preset & nen3_22 & n_n9087; + assign n5755 = ~preset & n_n9397 & (ndn3_25 | ~ndn3_22); + assign n5756 = ~preset & n_n8519 & (nsr3_13 | ndn3_15); + assign n5757 = ~preset & n_n9368 & (~nen3_22 | ndn3_22); + assign n5758 = ~preset & n_n8750 & (ndn3_42 | ~ndn3_40); + assign n5759_1 = ~ndn3_42 & ~preset & n_n7962 & ndn3_40; + assign n5760 = ~preset & n_n7968 & (ndn3_23 | nsr3_23); + assign n5761 = n4949_1 & ~ndn3_2 & pinp_14_14_ & ~preset; + assign n5762 = ~preset & n_n8000 & (ndn3_2 | ~n4949_1); + assign n5763 = n4949_1 & ~ndn3_2 & pinp_11_11_ & ~preset; + assign n5764_1 = ~preset & n_n8986 & (ndn3_2 | ~n4949_1); + assign n5765 = ~preset & n_n7820 & (ndn3_28 | ~nen3_28); + assign n5766 = ~preset & n4892 & (~n4971 ^ ~n4972); + assign n5767 = ~preset & n_n9333 & (~ndn3_42 | ndn3_44); + assign n5768 = n4861 & (n4987 ^ (n6433 | n6434)); + assign n5769_1 = ~preset & n_n9047 & (ndn3_23 | nsr3_23); + assign n5770 = ~preset & n_n8810 & (ndn3_19 | ~nen3_19); + assign n5771 = ~preset & n_n8381 & (nsr3_14 | ndn3_14); + assign n5772 = ~preset & n_n9041 & (~ndn3_42 | ndn3_44); + assign n5773 = ~preset & n_n8093 & (~ndn3_19 | ndn3_21); + assign n5774_1 = ~preset & n4885 & (~n4954_1 ^ ~n4955); + assign n5775 = ~preset & n_n7102 & (ndn3_42 | ~ndn3_40); + assign n5776 = ~ndn3_42 & ~preset & n_n9609 & ndn3_40; + assign n5777 = n7180 & ((n4931 & n4932) | (n_n8449 & (n4931 | n4932))); + assign n5778 = ~n_n8549 & n4857 & (~n4905 ^ ~n4906); + assign n5779_1 = ~n4906 & ~n4905 & n_n8549 & n4856; + assign n5780 = ~n5001 & ~preset & n_n8549; + assign n5781 = ~preset & n_n7681 & (nsr3_38 | ndn3_38); + assign n5782 = ~preset & n_n9346 & (ndn3_9 | ~ndn3_7); + assign n5783 = ~ndn3_2 & ~preset & psv38_9_9_ & n4949_1; + assign n5784_1 = ~preset & n_n9336 & (ndn3_2 | ~n4949_1); + assign n5785 = ~preset & n_n9134 & (ndn3_9 | ~ndn3_7); + assign n5786 = ~ndn3_2 & ~preset & psv18_5_5_ & n4949_1; + assign n5787 = ~preset & n_n9491 & (ndn3_2 | ~n4949_1); + assign n5788 = ~preset & n_n9334 & (~ndn3_29 | ndn3_32); + assign n5789_1 = ~ndn3_2 & ~preset & psv38_1_1_ & n4949_1; + assign n5790 = ~preset & n_n9045 & (ndn3_2 | ~n4949_1); + assign n5791 = ~preset & n_n9282 & (ngfdn_3 | ~ndn3_46); + assign n5792 = ~preset & n_n8697 & (ndn3_23 | nsr3_23); + assign n5793 = ~preset & n_n7875 & (nsr3_20 | ndn3_20); + assign n5794_1 = ~preset & n_n9036 & (ndn3_42 | ~ndn3_40); + assign n5795 = ~preset & n_n7527 & (ndn3_46 | ~ndn3_44); + assign n5796 = ~preset & n_n7454 & (ndn3_19 | ~nen3_19); + assign n5797 = ~preset & n_n8369 & (~ngfdn_3 | ndn3_50); + assign n5798 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9508; + assign n5799_1 = ~preset & n_n9263 & (ndn3_27 | ~ndn3_26); + assign n5800 = ~preset & n4859_1 & (~n4969_1 ^ ~n4970); + assign n5801 = ~preset & n_n8153 & (~ndn3_11 | ndn3_12); + assign n5802 = ~preset & n4849_1 & (~n4976 ^ ~n4977); + assign n5803 = ~preset & n_n9004 & (ngfdn_3 | ~ndn3_46); + assign n5804_1 = ndn3_46 & n_n8951 & ~preset & ~ngfdn_3; + assign n5805 = ~preset & n_n8049 & (~ndn3_42 | ndn3_44); + assign n5806 = ~ndn3_44 & ndn3_42 & ~preset & n_n9589; + assign n5807 = ~preset & n_n9148 & (~ngfdn_3 | ndn3_50); + assign n5808 = ~ndn3_50 & ~preset & ngfdn_3 & n_n7606; + assign n5809_1 = ~preset & n_n7498 & (~ndn3_42 | ndn3_44); + assign n5810 = ~ndn3_44 & ndn3_42 & ~preset & n_n9391; + assign n5811 = ~preset & n_n7824 & (~ndn3_11 | ndn3_12); + assign n5812 = ~preset & n4849_1 & (~n4971 ^ ~n4972); + assign n5813 = ~preset & n_n7777 & (~nen3_22 | ndn3_22); + assign n5814_1 = ~ndn3_22 & ~preset & nen3_22 & n_n9100; + assign n5815 = ~ndn3_2 & ~preset & psv13_4_4_ & n4949_1; + assign n5816 = ~preset & n_n7826 & (ndn3_2 | ~n4949_1); + assign n5817 = ~preset & n_n8777 & (~ndn3_39 | ndn3_40); + assign n5818 = ~ndn3_40 & ~preset & ndn3_39 & n_n8858; + assign n5819_1 = ~ndn3_2 & ~preset & psv33_10_10_ & n4949_1; + assign n5820 = ~preset & n_n9300 & (ndn3_2 | ~n4949_1); + assign n5821 = ~preset & n_n7847 & (~ndn3_17 | ndn3_18); + assign n5822 = ~preset & n4877 & (~n4985 ^ ~n4986); + assign n5823 = ~preset & n_n7760 & (~nen3_22 | ndn3_22); + assign n5824_1 = ~preset & n_n8466 & (ngfdn_3 | ~ndn3_46); + assign n5825 = ~preset & n_n7911 & (ndn3_23 | nsr3_23); + assign n5826 = ~preset & n_n8582 & (ndn3_19 | ~nen3_19); + assign n5827 = ~preset & n_n7790 & (ndn3_27 | ~ndn3_26); + assign n5828 = ~preset & n_n8279 & (~ndn3_25 | ndn3_26); + assign n5829_1 = ~preset & n4851 & (~n4985 ^ ~n4986); + assign n5830 = ~ndn3_2 & ~preset & psv2_11_11_ & n4949_1; + assign n5831 = ~preset & n_n9387 & (ndn3_2 | ~n4949_1); + assign n5832 = ~preset & n_n9589 & (ndn3_42 | ~ndn3_40); + assign n5833 = ~preset & n_n8951 & (ndn3_46 | ~ndn3_44); + assign n5834_1 = ~preset & n_n9573 & (ndn3_46 | ~ndn3_44); + assign n5835 = n4853 & (n4996 ^ (n6545 | n6546)); + assign n5836 = ~preset & n_n8659 & (nsr3_14 | ndn3_14); + assign n5837 = ~preset & n_n8681 & (ndn3_42 | ~ndn3_40); + assign n5838 = ~ndn3_42 & ~preset & n_n8996 & ndn3_40; + assign n5839_1 = ~preset & n_n8042 & (nsr3_14 | ndn3_14); + assign n5840 = ~preset & n_n8941 & (ndn3_29 | ~ndn3_28); + assign n5841 = ~ndn3_2 & ~preset & psv33_6_6_ & n4949_1; + assign n5842 = ~preset & n_n7643 & (ndn3_2 | ~n4949_1); + assign n5843 = ~preset & n_n7775 & (ngfdn_3 | ~ndn3_46); + assign n5844_1 = n_n7083 & ndn3_46 & ~preset & ~ngfdn_3; + assign n5845 = ~preset & n_n9096 & (ngfdn_3 | ~ndn3_46); + assign n5846 = ndn3_46 & n_n8258 & ~preset & ~ngfdn_3; + assign n5847 = ~preset & n_n9189 & (ndn3_13 | nsr3_13); + assign n5848 = ~preset & n_n9341 & (~ndn3_17 | ndn3_18); + assign n5849_1 = ~preset & n_n8260 & (ndn3_13 | nsr3_13); + assign n5850 = ~preset & n_n7918 & (nsr3_38 | ndn3_38); + assign n5851 = ~preset & n_n8996 & (~ndn3_39 | ndn3_40); + assign n5852 = ~preset & n_n7806 & (nsr3_38 | ndn3_38); + assign n5853 = ~preset & n_n8024 & (ndn3_42 | ~ndn3_40); + assign n5854_1 = ~preset & n_n8678 & (~ndn3_42 | ndn3_44); + assign n5855 = ~ndn3_44 & ndn3_42 & ~preset & n_n7948; + assign n5856 = ~preset & n_n9432 & (~ndn3_42 | ndn3_44); + assign n5857 = ~ndn3_44 & ndn3_42 & ~preset & n_n9036; + assign n5858 = ~ndn3_2 & ~preset & psv38_5_5_ & n4949_1; + assign n5859_1 = ~preset & n_n9174 & (ndn3_2 | ~n4949_1); + assign n5860 = ~preset & n_n7757 & (ndn3_42 | ~ndn3_40); + assign n5861 = ~preset & n_n7831 & (ndn3_30 | nsr3_30); + assign n5862 = ~ndn3_2 & ~preset & psv13_5_5_ & n4949_1; + assign n5863 = ~preset & n_n9501 & (ndn3_2 | ~n4949_1); + assign n5864_1 = ~preset & n_n8445 & (nsr3_38 | ndn3_38); + assign n5865 = ~ndn3_2 & ~preset & psv2_3_3_ & n4949_1; + assign n5866 = ~preset & n_n9408 & (ndn3_2 | ~n4949_1); + assign n5867 = ~preset & n_n9489 & (ndn3_30 | nsr3_30); + assign n5868 = ~preset & n_n7821 & (ndn3_25 | ~ndn3_22); + assign n5869_1 = ~preset & n4889_1 & (~n4971 ^ ~n4972); + assign n5870 = ~preset & n_n7217 & (ngfdn_3 | ~ndn3_46); + assign n5871 = ~preset & n_n9321 & (ndn3_7 | ~ndn3_4); + assign n5872 = ~preset & n4879_1 & (~n4954_1 ^ ~n4955); + assign n5873 = ~preset & n_n8843 & (nsr3_20 | ndn3_20); + assign n5874_1 = ~preset & n_n7641 & (ndn3_23 | nsr3_23); + assign n5875 = ~preset & n_n8258 & (ndn3_46 | ~ndn3_44); + assign n5876 = ~preset & n_n8247 & (ndn3_42 | ~ndn3_40); + assign n5877 = ~preset & n_n8957 & (~ndn3_39 | ndn3_40); + assign n5878 = ~preset & n_n8959 & (~ndn3_39 | ndn3_40); + assign n5879_1 = n4846 & (n5004_1 ^ (n6527 | n6528)); + assign n5880 = ~ndn3_2 & ~preset & psv26_8_8_ & n4949_1; + assign n5881 = ~preset & n_n7954 & (ndn3_2 | ~n4949_1); + assign n5882 = ~preset & n_n9601 & (ndn3_13 | nsr3_13); + assign n5883 = ~preset & n_n9465 & (~ndn3_42 | ndn3_44); + assign n5884_1 = ~ndn3_44 & ndn3_42 & ~preset & n_n8022; + assign n5885 = ~ndn3_2 & ~preset & psv26_0_0_ & n4949_1; + assign n5886 = ~preset & n_n7656 & (ndn3_2 | ~n4949_1); + assign n5887 = ~preset & n_n8998 & (~ndn3_25 | ndn3_26); + assign n5888 = ~preset & n_n8282 & (~ndn3_11 | ndn3_12); + assign n5889_1 = ~preset & n4849_1 & (~n4985 ^ ~n4986); + assign n5890 = ~preset & n_n7546 & (ngfdn_3 | ~ndn3_46); + assign n5891 = ~ngfdn_3 & ~preset & n_n9235 & ndn3_46; + assign n5892 = ~preset & n_n7174 & (ndn3_46 | ~ndn3_44); + assign n5893 = n_n9632 & ndn3_44 & ~preset & ~ndn3_46; + assign n5894_1 = ~preset & n_n8742 & (~ndn3_25 | ndn3_26); + assign n5895 = ~preset & n4851 & (~n4954_1 ^ ~n4955); + assign n5896 = ~preset & n_n8006 & (ndn3_7 | ~ndn3_4); + assign n5897 = ~ndn3_2 & ~preset & psv13_13_13_ & n4949_1; + assign n5898 = ~preset & n_n8414 & (ndn3_2 | ~n4949_1); + assign n5899_1 = ~ndn3_2 & ~preset & psv13_8_8_ & n4949_1; + assign n5900 = ~preset & n_n7955 & (ndn3_2 | ~n4949_1); + assign n5901 = ~preset & n_n7160 & (~ndn3_39 | ndn3_40); + assign n5902 = ~ndn3_40 & ndn3_39 & ~preset & n_n8906; + assign n5903 = ~ndn3_2 & ~preset & psv33_13_13_ & n4949_1; + assign n5904_1 = ~preset & n_n9098 & (ndn3_2 | ~n4949_1); + assign n5905 = ~preset & n_n7640 & (~ndn3_29 | ndn3_32); + assign n5906 = ~preset & n_n7803 & (ndn3_7 | ~ndn3_4); + assign n5907 = ~preset & n4879_1 & (~n4976 ^ ~n4977); + assign n5908 = ~ndn3_2 & ~preset & psv33_11_11_ & n4949_1; + assign n5909_1 = ~preset & n_n8086 & (ndn3_2 | ~n4949_1); + assign n5910 = ~preset & n_n9339 & (~nen3_22 | ndn3_22); + assign n5911 = n4866 & (n4987 ^ (n6433 | n6434)); + assign n5912 = n4949_1 & ~ndn3_2 & pinp_4_4_ & ~preset; + assign n5913 = ~preset & n_n8736 & (ndn3_2 | ~n4949_1); + assign n5914_1 = ~preset & n_n8005 & (~nen3_16 | ndn3_16); + assign n5915 = ~preset & n_n7823 & (~nen3_16 | ndn3_16); + assign n5916 = ~preset & n4875 & (~n4971 ^ ~n4972); + assign n5917 = ~preset & n_n8545 & (~ndn3_25 | ndn3_26); + assign n5918 = ~preset & n4851 & (~n4976 ^ ~n4977); + assign n5919_1 = ~preset & n_n8219 & (nsr3_20 | ndn3_20); + assign n5920 = ~preset & n_n7236 & (~ndn3_19 | ndn3_21); + assign n5921 = ~preset & n_n7428 & (ndn3_29 | ~ndn3_28); + assign n5922 = ~preset & n4869_1 & (~n4971 ^ ~n4972); + assign n5923 = ~preset & n_n9597 & (nsr3_20 | ndn3_20); + assign n5924_1 = n4949_1 & ~ndn3_2 & pinp_10_10_ & ~preset; + assign n5925 = ~preset & n_n8110 & (ndn3_2 | ~n4949_1); + assign n5926 = ~preset & n_n9391 & (ndn3_42 | ~ndn3_40); + assign n5927 = n4863 & (n4996 ^ (n6545 | n6546)); + assign n5928 = ~preset & n_n7758 & (ndn3_30 | nsr3_30); + assign n5929_1 = ~preset & n_n8278 & (ndn3_29 | ~ndn3_28); + assign n5930 = ~preset & n4869_1 & (~n4985 ^ ~n4986); + assign n5931 = ~preset & n_n9125 & (~ndn3_42 | ndn3_44); + assign n5932 = n4861 & (n4996 ^ (n6545 | n6546)); + assign n5933 = ~preset & n_n9169 & (ndn3_42 | ~ndn3_40); + assign n5934_1 = n_n6974 & ndn3_40 & ~preset & ~ndn3_42; + assign n5935 = ~ndn3_2 & ~preset & psv38_15_15_ & n4949_1; + assign n5936 = ~preset & n_n9223 & (ndn3_2 | ~n4949_1); + assign n5937 = ~preset & n_n9135 & (ndn3_4 | ~ndn3_2); + assign n5938 = ~preset & n_n7898 & (~ndn3_42 | ndn3_44); + assign n5939_1 = ~preset & n_n8765 & (ndn3_46 | ~ndn3_44); + assign n5940 = ~preset & n_n7908 & (ndn3_37 | nsr3_37); + assign n5941 = ~preset & n_n7462 & (~ngfdn_3 | ndn3_50); + assign n5942 = ~ndn3_50 & n_n9219 & ~preset & ngfdn_3; + assign n5943 = ~preset & n_n7384 & (ndn3_46 | ~ndn3_44); + assign n5944_1 = ~preset & n_n9613 & (~nen3_39 | ndn3_39); + assign n5945 = ~preset & n4854_1 & (~n4985 ^ ~n4986); + assign n5946 = ~ndn3_2 & ~preset & psv13_3_3_ & n4949_1; + assign n5947 = ~preset & n_n9406 & (ndn3_2 | ~n4949_1); + assign n5948 = ~preset & n_n9611 & (~nen3_39 | ndn3_39); + assign n5949_1 = ~preset & n_n7324 & (ngfdn_3 | ~ndn3_46); + assign n5950 = ~preset & n_n9335 & (ndn3_37 | nsr3_37); + assign n5951 = ~preset & n_n9127 & (ndn3_37 | nsr3_37); + assign n5952 = ~ngfdn_3 & nsr1_2 & (~preset_0_0_ | nlc1_2); + assign n5953 = ~preset & n_n9400 & (~nen3_16 | ndn3_16); + assign n5954_1 = ~preset & n_n9343 & (nsr3_13 | ndn3_15); + assign n5955 = ~preset & n_n7054 & (ndn3_42 | ~ndn3_40); + assign n5956 = ~ndn3_42 & ~preset & n_n9576 & ndn3_40; + assign n5957 = ~preset & n_n7948 & (ndn3_42 | ~ndn3_40); + assign n5958 = ~preset & n_n7783 & (ndn3_46 | ~ndn3_44); + assign n5959_1 = n4853 & (n5004_1 ^ (n6527 | n6528)); + assign n5960 = ~preset & n_n7602 & (ndn3_23 | nsr3_23); + assign n5961 = ~preset & n_n7740 & (nsr3_20 | ndn3_20); + assign n5962 = ~preset & n_n7691 & (~ndn3_42 | ndn3_44); + assign n5963 = ~preset & n_n9483 & (~ngfdn_3 | ndn3_50); + assign n5964_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n8948; + assign n5965 = ~preset & n_n9049 & (nsr3_14 | ndn3_14); + assign n5966 = ~preset & n_n9588 & (ndn3_34 | ~nen3_34); + assign n5967 = ~preset & n4860 & (~n4969_1 ^ ~n4970); + assign n5968 = ~preset & n_n7791 & (~ndn3_9 | ndn3_11); + assign n5969_1 = ~preset & n_n7857 & (ndn3_46 | ~ndn3_44); + assign n5970 = ~ndn3_46 & ~preset & n_n7706 & ndn3_44; + assign n5971 = n4900 & (n5975 | (n4975 & n7176)); + assign n5972 = n4856 & (~n_n8631 ^ (n_n8561 | n4999_1)); + assign n5973 = n4897 & (n5975 | (n4975 & n7176)); + assign n5974_1 = n4856 & (n_n8913 ^ ~n4968); + assign n5975 = n7089 & n4967 & ~preset & ~n_n9247; + assign n5976 = ~ndn3_2 & ~preset & psv13_14_14_ & n4949_1; + assign n5977 = ~preset & n_n8114 & (ndn3_2 | ~n4949_1); + assign n5978 = ~ndn3_2 & ~preset & psv39_15_15_ & n4949_1; + assign n5979_1 = ~preset & n_n8491 & (ndn3_2 | ~n4949_1); + assign n5980 = ~preset & n_n8175 & (~nen3_22 | ndn3_22); + assign n5981 = ~ndn3_22 & ~preset & nen3_22 & n_n9252; + assign n5982 = ~preset & n_n9257 & (ndn3_13 | nsr3_13); + assign n5983 = ~preset & n_n8091 & (~ngfdn_3 | ndn3_50); + assign n5984_1 = ~ndn3_50 & n_n8466 & ~preset & ngfdn_3; + assign n5985 = ~preset & n_n8066 & (nsr3_14 | ndn3_14); + assign n5986 = ~ndn3_2 & ~preset & psv13_2_2_ & n4949_1; + assign n5987 = ~preset & n_n8053 & (ndn3_2 | ~n4949_1); + assign n5988 = ~preset & n_n7811 & (nsr3_13 | ndn3_15); + assign n5989_1 = ~preset & n_n7934 & (ndn3_13 | nsr3_13); + assign n5990 = ~preset & n_n7735 & (ndn3_30 | nsr3_30); + assign n5991 = ~preset & n_n7651 & (ndn3_30 | nsr3_30); + assign n5992 = ~preset & n_n9412 & (~ndn3_19 | ndn3_21); + assign n5993 = ~preset & n_n9398 & (~nen3_22 | ndn3_22); + assign n5994_1 = n4866 & (n4996 ^ (n6545 | n6546)); + assign n5995 = ~preset & n_n9064 & (nsr3_20 | ndn3_20); + assign n5996 = ~ndn3_2 & ~preset & psv2_15_15_ & n4949_1; + assign n5997 = ~preset & n_n8007 & (ndn3_2 | ~n4949_1); + assign n5998 = n4949_1 & ~ndn3_2 & pinp_15_15_ & ~preset; + assign n5999_1 = ~preset & n_n8482 & (ndn3_2 | ~n4949_1); + assign n6000 = ~ndn3_2 & ~preset & psv2_14_14_ & n4949_1; + assign n6001 = ~preset & n_n7937 & (ndn3_2 | ~n4949_1); + assign n6002 = n4949_1 & ~ndn3_2 & pinp_13_13_ & ~preset; + assign n6003 = ~preset & n_n7850 & (ndn3_2 | ~n4949_1); + assign n6004_1 = n7175 & ((n4918 & n4919_1) | (n_n9512 & (n4918 | n4919_1))); + assign n6005 = ~n_n9434 & n4857 & (~n4893 ^ ~n4894_1); + assign n6006 = ~n4894_1 & ~n4893 & n_n9434 & n4856; + assign n6007 = ~n5001 & ~preset & n_n9434; + assign n6008 = ~preset & n_n9399 & (nsr3_20 | ndn3_20); + assign n6009_1 = ~preset & n_n8333 & (ndn3_28 | ~nen3_28); + assign n6010 = ~preset & n4892 & (~n4985 ^ ~n4986); + assign n6011 = ~ndn3_2 & ~preset & psv18_11_11_ & n4949_1; + assign n6012 = ~preset & n_n7759 & (ndn3_2 | ~n4949_1); + assign n6013 = ~preset & n_n8661 & (nsr3_14 | ndn3_14); + assign n6014_1 = ~preset & n_n8132 & (ndn3_42 | ~ndn3_40); + assign n6015 = ~ndn3_42 & ~preset & n_n8150 & ndn3_40; + assign n6016 = ~preset & n_n8488 & (~nen3_22 | ndn3_22); + assign n6017 = ~ndn3_22 & n_n9412 & ~preset & nen3_22; + assign n6018 = ~preset & n_n7953 & (ndn3_13 | nsr3_13); + assign n6019_1 = ~preset & n_n7179 & (ngfdn_3 | ~ndn3_46); + assign n6020 = ndn3_46 & n_n7783 & ~preset & ~ngfdn_3; + assign n6021 = ~preset & n_n9265 & (~ndn3_17 | ndn3_18); + assign n6022 = ~preset & n4877 & (~n4969_1 ^ ~n4970); + assign n6023 = ~preset & n_n9052 & (ndn3_4 | ~ndn3_2); + assign n6024_1 = ~preset & n4874_1 & (~n4954_1 ^ ~n4955); + assign n6025 = ~preset & n_n9106 & (~nen3_39 | ndn3_39); + assign n6026 = ~preset & n4854_1 & (~n4954_1 ^ ~n4955); + assign n6027 = ~preset & n_n8702 & (~nen3_22 | ndn3_22); + assign n6028 = ~ndn3_22 & ~preset & nen3_22 & n_n8213; + assign n6029_1 = ~preset & n_n7190 & (~ndn3_42 | ndn3_44); + assign n6030 = ~ndn3_44 & ndn3_42 & ~preset & n_n8249; + assign n6031 = ~preset & n_n9635 & (~ndn3_42 | ndn3_44); + assign n6032 = n4861 & (n4980 ^ (n6352 | n6353)); + assign n6033 = ~preset & n_n8001 & (nsr3_38 | ndn3_38); + assign n6034_1 = ~preset & n_n9000 & (ndn3_25 | ~ndn3_22); + assign n6035 = ~preset & n_n9598 & (~nen3_16 | ndn3_16); + assign n6036 = ~preset & n4875 & (~n4969_1 ^ ~n4970); + assign n6037 = ~preset & n_n8786 & (ndn3_7 | ~ndn3_4); + assign n6038 = ~preset & n_n9602 & (ndn3_7 | ~ndn3_4); + assign n6039_1 = ~preset & n4879_1 & (~n4969_1 ^ ~n4970); + assign n6040 = ~preset & n_n8981 & (ndn3_29 | ~ndn3_28); + assign n6041 = ~preset & n_n8308 & (ndn3_46 | ~ndn3_44); + assign n6042 = ~preset & n_n8609 & (ndn3_42 | ~ndn3_40); + assign n6043 = n4863 & (n5004_1 ^ (n6527 | n6528)); + assign n6044_1 = ~preset & n_n8699 & (nsr3_20 | ndn3_20); + assign n6045 = ~preset & n_n8533 & (ndn3_23 | nsr3_23); + assign n6046 = ~preset & n_n9273 & (~ndn3_19 | ndn3_21); + assign n6047 = ~preset & n_n9311 & (nsr3_35 | ndn3_35); + assign n6048 = ~preset & n_n7148 & (~ndn3_42 | ndn3_44); + assign n6049_1 = ~ndn3_44 & ndn3_42 & ~preset & n_n9623; + assign n6050 = ~preset & n_n8227 & (~ndn3_11 | ndn3_12); + assign n6051 = ~preset & n_n7970 & (~ndn3_9 | ndn3_11); + assign n6052 = ~preset & n_n7581 & (~nen3_22 | ndn3_22); + assign n6053 = ~ndn3_22 & ~preset & nen3_22 & n_n9351; + assign n6054_1 = ~preset & n_n9008 & (ndn3_9 | ~ndn3_7); + assign n6055 = ~preset & n4852 & (~n4971 ^ ~n4972); + assign n6056 = ~ndn3_2 & ~preset & psv26_12_12_ & n4949_1; + assign n6057 = ~preset & n_n7814 & (ndn3_2 | ~n4949_1); + assign n6058 = ~preset & n_n7877 & (~ndn3_11 | ndn3_12); + assign n6059_1 = ~ndn3_2 & ~preset & psv26_11_11_ & n4949_1; + assign n6060 = ~preset & n_n7765 & (ndn3_2 | ~n4949_1); + assign n6061 = ~preset & n_n8758 & (ndn3_7 | ~ndn3_4); + assign n6062 = ~preset & n4879_1 & (~n4985 ^ ~n4986); + assign n6063 = ~preset & n_n7332 & (~ndn3_39 | ndn3_40); + assign n6064_1 = ~ndn3_40 & ~preset & ndn3_39 & n_n8991; + assign n6065 = ~ndn3_2 & ~preset & psv39_12_12_ & n4949_1; + assign n6066 = ~preset & n_n7816 & (ndn3_2 | ~n4949_1); + assign n6067 = ~preset & n_n7812 & (ndn3_13 | nsr3_13); + assign n6068 = ~preset & n_n8394 & (ndn3_13 | nsr3_13); + assign n6069_1 = ~preset & n_n8152 & (ndn3_17 | ~ndn3_16); + assign n6070 = ~preset & n4882 & (~n4976 ^ ~n4977); + assign n6071 = ~preset & n_n8597 & (~ndn3_17 | ndn3_18); + assign n6072 = ~preset & n4877 & (~n4976 ^ ~n4977); + assign n6073 = ~preset & n_n7889 & (nsr3_13 | ndn3_15); + assign n6074_1 = ~preset & n4881 & (~n4985 ^ ~n4986); + assign n6075 = ~preset & n_n7888 & (~nen3_16 | ndn3_16); + assign n6076 = ~preset & n4875 & (~n4985 ^ ~n4986); + assign n6077 = ~preset & n_n8225 & (ndn3_19 | ~nen3_19); + assign n6078 = ~preset & n_n7599 & (ndn3_37 | nsr3_37); + assign n6079_1 = ~preset & n_n7558 & (ngfdn_3 | ~ndn3_46); + assign n6080 = n1270 & (n4996 ^ (n6545 | n6546)); + assign n6081 = ~preset & n_n8377 & (ndn3_7 | ~ndn3_4); + assign n6082 = ~preset & n_n8208 & (~ndn3_17 | ndn3_18); + assign n6083 = n4952 & ((n4994_1 & n4995) | (n4986 & (~n4994_1 ^ ~n4995))); + assign n6084_1 = (n7157 | n7158) & (n7164 | n7165); + assign n6085 = n_n9568 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6086 = n_n8772 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6087 = n_n7914 & ~ndn3_7 & ndn3_4; + assign n6088 = n_n7913 & ndn3_11 & ~ndn3_12; + assign n6089_1 = ndn3_40 & n_n7908 & ~ndn3_42; + assign n6090 = ndn3_26 & ~ndn3_27 & n_n7932; + assign n6091 = n_n9632 & ~ngfdn_3 & ndn3_46; + assign n6092 = n_n8535 & nen3_16 & ~ndn3_16; + assign n6093 = ~ndn3_32 & ndn3_29 & n_n7910; + assign n6094_1 = ~ndn3_40 & n_n7909 & ndn3_39; + assign n6095 = n_n7912 & ndn3_19 & ~ndn3_21; + assign n6096 = n_n7911 & ~ndn3_25 & ndn3_22; + assign n6097 = ndn3_44 & n_n8512 & ~ndn3_46; + assign n6098 = n_n8106 & ndn3_17 & ~ndn3_18; + assign n6099 = n_n7935 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6100 = n_n7936 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6101 = ndn3_2 & n_n7937 & ~ndn3_4; + assign n6102 = n_n7928 & nen3_39 & ~ndn3_39; + assign n6103 = ndn3_7 & ~ndn3_9 & n_n8114; + assign n6104 = ndn3_46 & ~ngfdn_3 & n_n9108; + assign n6105 = n_n7946 & ndn3_9 & ~ndn3_11; + assign n6106 = n_n7933 & ndn3_19 & ~ndn3_21; + assign n6107 = nen3_28 & n_n7931 & ~ndn3_28; + assign n6108 = n_n7927 & ~ndn3_46 & ndn3_44; + assign n6109 = ~ndn3_44 & n_n8445 & ndn3_42; + assign n6110 = nen3_34 & ~ndn3_34 & n_n8425; + assign n6111 = ~ndn3_36 & nen3_36 & n_n7929; + assign n6112 = n_n8516 & ndn3_17 & ~ndn3_18; + assign n6113 = n_n8219 & nen3_22 & ~ndn3_22; + assign n6114 = ~ndn3_15 & n_n7934 & ~nsr3_13; + assign n6115 = n_n7971 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6116 = n_n8014 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6117 = ndn3_4 & ~ndn3_7 & n_n8456; + assign n6118 = ~ndn3_12 & n_n7970 & ndn3_11; + assign n6119 = ndn3_40 & n_n7966 & ~ndn3_42; + assign n6120 = ndn3_26 & ~ndn3_27 & n_n8004; + assign n6121 = n_n8468 & ~ngfdn_3 & ndn3_46; + assign n6122 = n_n7969 & nen3_16 & ~ndn3_16; + assign n6123 = ~ndn3_32 & ndn3_29 & n_n9077; + assign n6124 = ~ndn3_40 & n_n7967 & ndn3_39; + assign n6125 = ~ndn3_21 & n_n8208 & ndn3_19; + assign n6126 = n_n7968 & ~ndn3_25 & ndn3_22; + assign n6127 = ndn3_44 & n_n8864 & ~ndn3_46; + assign n6128 = n_n8519 & ndn3_17 & ~ndn3_18; + assign n6129 = n_n8006 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6130 = n_n8491 & (n6909 | (~ndn3_25 & ndn3_22)); + assign n6131 = ndn3_2 & n_n8007 & ~ndn3_4; + assign n6132 = n_n8078 & nen3_39 & ~ndn3_39; + assign n6133 = n_n8502 & ~ndn3_9 & ndn3_7; + assign n6134 = n_n8580 & ~ngfdn_3 & ndn3_46; + assign n6135 = n_n8192 & ndn3_9 & ~ndn3_11; + assign n6136 = ~ndn3_21 & n_n8005 & ndn3_19; + assign n6137 = nen3_28 & ~ndn3_28 & n_n8003; + assign n6138 = ndn3_44 & ~ndn3_46 & n_n9355; + assign n6139 = ~ndn3_44 & n_n8001 & ndn3_42; + assign n6140 = nen3_34 & ~ndn3_34 & n_n8839; + assign n6141 = ~ndn3_36 & nen3_36 & n_n8900; + assign n6142 = n_n8584 & ndn3_17 & ~ndn3_18; + assign n6143 = n_n8064 & nen3_22 & ~ndn3_22; + assign n6144 = n_n8344 & ~nsr3_13 & ~ndn3_15; + assign n6145 = ~preset & n_n8775 & (ndn3_4 | ~ndn3_2); + assign n6146 = ~preset & n4874_1 & (~n4985 ^ ~n4986); + assign n6147 = n_n8758 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6148 = n_n8504 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6149 = ndn3_2 & ~ndn3_4 & n_n7890; + assign n6150 = ~ndn3_39 & nen3_39 & n_n7988; + assign n6151 = ndn3_7 & ~ndn3_9 & n_n8414; + assign n6152 = ndn3_46 & ~ngfdn_3 & n_n8626; + assign n6153 = n_n9067 & ndn3_9 & ~ndn3_11; + assign n6154 = ~ndn3_21 & n_n7888 & ndn3_19; + assign n6155 = nen3_28 & ~ndn3_28 & n_n7887; + assign n6156 = ndn3_44 & n_n9623 & ~ndn3_46; + assign n6157 = ~ndn3_44 & n_n7885 & ndn3_42; + assign n6158 = nen3_34 & n_n8333 & ~ndn3_34; + assign n6159 = n_n9092 & nen3_36 & ~ndn3_36; + assign n6160 = n_n8282 & ndn3_17 & ~ndn3_18; + assign n6161 = ~ndn3_22 & nen3_22 & n_n9064; + assign n6162 = ~ndn3_15 & n_n8394 & ~nsr3_13; + assign n6163 = n_n8775 & (n6899 | (nen3_22 & ~ndn3_22)); + assign n6164 = n_n7849 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6165 = ndn3_4 & n_n9098 & ~ndn3_7; + assign n6166 = n_n7848 & ndn3_11 & ~ndn3_12; + assign n6167 = ndn3_40 & n_n8480 & ~ndn3_42; + assign n6168 = ndn3_26 & ~ndn3_27 & n_n9520; + assign n6169 = n_n8470 & ~ngfdn_3 & ndn3_46; + assign n6170 = n_n8909 & nen3_16 & ~ndn3_16; + assign n6171 = ~ndn3_32 & ndn3_29 & n_n7845; + assign n6172 = n_n7844 & ndn3_39 & ~ndn3_40; + assign n6173 = ~ndn3_21 & n_n7847 & ndn3_19; + assign n6174 = n_n7846 & ~ndn3_25 & ndn3_22; + assign n6175 = ndn3_44 & ~ndn3_46 & n_n8277; + assign n6176 = ~ndn3_18 & n_n7889 & ndn3_17; + assign n6177 = ~preset & n_n7452 & (ndn3_29 | ~ndn3_28); + assign n6178 = n7123 & ((n4934_1 & n4937) | (n_n8821 & (n4934_1 | n4937))); + assign n6179 = ~n_n9638 & n4857 & (~n4870 ^ ~n4871); + assign n6180 = ~n4871 & ~n4870 & n_n9638 & n4856; + assign n6181 = ~n5001 & ~preset & n_n9638; + assign n6182 = ~preset & n_n7522 & (ndn3_42 | ~ndn3_40); + assign n6183 = ~ndn3_42 & ~preset & n_n9102 & ndn3_40; + assign n6184 = ~preset & n_n9235 & (ndn3_46 | ~ndn3_44); + assign n6185 = ~preset & n_n9486 & (ndn3_42 | ~ndn3_40); + assign n6186 = ~preset & n_n9130 & (ndn3_23 | nsr3_23); + assign n6187 = ~ndn3_2 & ~preset & psv38_11_11_ & n4949_1; + assign n6188 = ~preset & n_n7709 & (ndn3_2 | ~n4949_1); + assign n6189 = ~preset & n_n7819 & (nsr3_35 | ndn3_35); + assign n6190 = ~ndn3_2 & ~preset & psv18_15_15_ & n4949_1; + assign n6191 = ~preset & n_n8002 & (ndn3_2 | ~n4949_1); + assign n6192 = ~preset & n_n9467 & (ndn3_34 | ~nen3_34); + assign n6193 = ~preset & n4860 & (~n4976 ^ ~n4977); + assign n6194 = ~preset & n_n9548 & (ngfdn_3 | ~ndn3_46); + assign n6195 = ndn3_46 & n_n7384 & ~preset & ~ngfdn_3; + assign n6196 = ~preset & n_n7707 & (ndn3_37 | nsr3_37); + assign n6197 = ~n5001 & ~preset & n_n8557; + assign n6198 = n_n8584 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6199 = nsr3_20 & ndn3_17 & n_n8583; + assign n6200 = nsr3_35 & ndn3_29 & n_n8941; + assign n6201 = nen3_34 & n_n8864 & nsr3_37; + assign n6202 = ndn3_26 & nsr3_30 & n_n8581; + assign n6203 = n_n8580 & nsr3_38 & nen3_36; + assign n6204 = ndn3_19 & nsr3_23 & n_n8582; + assign n6205 = n_n8227 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6206 = n_n8226 & ndn3_17 & nsr3_20; + assign n6207 = n_n8224 & ndn3_29 & nsr3_35; + assign n6208 = nen3_34 & n_n8223 & nsr3_37; + assign n6209 = ndn3_26 & nsr3_30 & n_n9205; + assign n6210 = n_n8222 & nsr3_38 & nen3_36; + assign n6211 = ndn3_19 & n_n8225 & nsr3_23; + assign n6212 = n_n8203 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6213 = nsr3_20 & ndn3_17 & n_n9019; + assign n6214 = n_n8201 & ndn3_29 & nsr3_35; + assign n6215 = nen3_34 & n_n9110 & nsr3_37; + assign n6216 = ndn3_26 & nsr3_30 & n_n9615; + assign n6217 = n_n9516 & nsr3_38 & nen3_36; + assign n6218 = ndn3_19 & n_n8202 & nsr3_23; + assign n6219 = n_n7951 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6220 = nsr3_20 & ndn3_17 & n_n8753; + assign n6221 = nsr3_35 & ndn3_29 & n_n7474; + assign n6222 = nen3_34 & n_n9518 & nsr3_37; + assign n6223 = ndn3_26 & nsr3_30 & n_n9286; + assign n6224 = n_n7947 & nsr3_38 & nen3_36; + assign n6225 = n_n7588 & nsr3_23 & ndn3_19; + assign n6226 = n_n9141 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6227 = nsr3_20 & ndn3_17 & n_n7375; + assign n6228 = nsr3_35 & n_n7373 & ndn3_29; + assign n6229 = nen3_34 & n_n8499 & nsr3_37; + assign n6230 = ndn3_26 & nsr3_30 & n_n7487; + assign n6231 = n_n8135 & nsr3_38 & nen3_36; + assign n6232 = n_n7374 & nsr3_23 & ndn3_19; + assign n6233 = n_n9015 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6234 = nsr3_20 & ndn3_17 & n_n8104; + assign n6235 = n_n8828 & ndn3_29 & nsr3_35; + assign n6236 = nen3_34 & n_n7670 & nsr3_37; + assign n6237 = ndn3_26 & n_n7341 & nsr3_30; + assign n6238 = nen3_36 & n_n8862 & nsr3_38; + assign n6239 = n_n7342 & nsr3_23 & ndn3_19; + assign n6240 = n_n9318 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6241 = nsr3_20 & ndn3_17 & n_n8744; + assign n6242 = nsr3_35 & ndn3_29 & n_n8741; + assign n6243 = nen3_34 & n_n9042 & nsr3_37; + assign n6244 = ndn3_26 & n_n8742 & nsr3_30; + assign n6245 = n_n9308 & nsr3_38 & nen3_36; + assign n6246 = n_n8743 & nsr3_23 & ndn3_19; + assign n6247 = n_n9401 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6248 = n_n8811 & ndn3_17 & nsr3_20; + assign n6249 = nsr3_35 & ndn3_29 & n_n8808; + assign n6250 = nen3_34 & n_n9126 & nsr3_37; + assign n6251 = ndn3_26 & nsr3_30 & n_n8809; + assign n6252 = n_n9390 & nsr3_38 & nen3_36; + assign n6253 = n_n8810 & nsr3_23 & ndn3_19; + assign n6254 = n_n7824 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6255 = nsr3_20 & ndn3_17 & n_n8729; + assign n6256 = nsr3_35 & ndn3_29 & n_n7428; + assign n6257 = nen3_34 & n_n7598 & nsr3_37; + assign n6258 = n_n7485 & nsr3_30 & ndn3_26; + assign n6259 = n_n8898 & nsr3_38 & nen3_36; + assign n6260 = n_n7429 & nsr3_23 & ndn3_19; + assign n6261 = n_n9496 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6262 = nsr3_20 & ndn3_17 & n_n8884; + assign n6263 = n_n8881 & ndn3_29 & nsr3_35; + assign n6264 = nen3_34 & n_n9473 & nsr3_37; + assign n6265 = ndn3_26 & n_n8882 & nsr3_30; + assign n6266 = nen3_36 & n_n9485 & nsr3_38; + assign n6267 = ndn3_19 & n_n8883 & nsr3_23; + assign n6268 = n_n7877 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6269 = nsr3_20 & ndn3_17 & n_n8727; + assign n6270 = nsr3_35 & n_n7452 & ndn3_29; + assign n6271 = nen3_34 & n_n7640 & nsr3_37; + assign n6272 = n_n7453 & nsr3_30 & ndn3_26; + assign n6273 = n_n9458 & nsr3_38 & nen3_36; + assign n6274 = ndn3_19 & nsr3_23 & n_n7454; + assign n6275 = n_n9599 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6276 = nsr3_20 & ndn3_17 & n_n8939; + assign n6277 = n_n8937 & ndn3_29 & nsr3_35; + assign n6278 = nen3_34 & n_n9470 & nsr3_37; + assign n6279 = ndn3_26 & nsr3_30 & n_n8938; + assign n6280 = nen3_36 & n_n9588 & nsr3_38; + assign n6281 = n_n9139 & nsr3_23 & ndn3_19; + assign n6282 = n_n8984 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6283 = nsr3_20 & ndn3_17 & n_n8983; + assign n6284 = nsr3_35 & n_n8981 & ndn3_29; + assign n6285 = nen3_34 & n_n9334 & nsr3_37; + assign n6286 = ndn3_26 & n_n8998 & nsr3_30; + assign n6287 = n_n8980 & nsr3_38 & nen3_36; + assign n6288 = n_n8982 & nsr3_23 & ndn3_19; + assign n6289 = n_n8153 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6290 = nsr3_20 & n_n8152 & ndn3_17; + assign n6291 = n_n8177 & ndn3_29 & nsr3_35; + assign n6292 = nen3_34 & nsr3_37 & n_n8628; + assign n6293 = ndn3_26 & n_n8545 & nsr3_30; + assign n6294 = nen3_36 & n_n9467 & nsr3_38; + assign n6295 = n_n8151 & nsr3_23 & ndn3_19; + assign n6296 = n_n8282 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6297 = nsr3_20 & ndn3_17 & n_n8281; + assign n6298 = nsr3_35 & ndn3_29 & n_n8278; + assign n6299 = nen3_34 & n_n8277 & nsr3_37; + assign n6300 = ndn3_26 & n_n8279 & nsr3_30; + assign n6301 = n_n8626 & nsr3_38 & nen3_36; + assign n6302 = n_n8280 & nsr3_23 & ndn3_19; + assign n6303 = n_n8516 & (nsr3_13 ? ndn3_12 : nsr3_14); + assign n6304 = nsr3_20 & ndn3_17 & n_n8515; + assign n6305 = n_n8513 & ndn3_29 & nsr3_35; + assign n6306 = nen3_34 & n_n8512 & nsr3_37; + assign n6307 = ndn3_26 & nsr3_30 & n_n9203; + assign n6308 = n_n9108 & nsr3_38 & nen3_36; + assign n6309 = n_n8514 & nsr3_23 & ndn3_19; + assign n6310 = ~preset & n_n6991 & (ngfdn_3 | ~ndn3_46); + assign n6311 = ndn3_46 & n_n7896 & ~preset & ~ngfdn_3; + assign n6312 = ~preset & n_n7271 & (ngfdn_3 | ~ndn3_46); + assign n6313 = ~ngfdn_3 & ~preset & n_n8308 & ndn3_46; + assign n6314 = ~preset & n_n7252 & (ngfdn_3 | ~ndn3_46); + assign n6315 = n_n7444 & ndn3_46 & ~preset & ~ngfdn_3; + assign n6316 = ~preset & n_n8871 & (~nen3_39 | ndn3_39); + assign n6317 = ~preset & n_n8592 & (ndn3_46 | ~ndn3_44); + assign n6318 = ~ndn3_46 & ~preset & n_n9259 & ndn3_44; + assign n6319 = ~preset & n_n9401 & (~ndn3_11 | ndn3_12); + assign n6320 = ~preset & n_n8150 & (~ndn3_39 | ndn3_40); + assign n6321 = n4846 & (n4980 ^ (n6352 | n6353)); + assign n6322 = n_n7813 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6323 = n_n7816 & (n6909 | (~ndn3_25 & ndn3_22)); + assign n6324 = ndn3_2 & n_n7817 & ~ndn3_4; + assign n6325 = ~ndn3_39 & nen3_39 & n_n7807; + assign n6326 = n_n7815 & ~ndn3_9 & ndn3_7; + assign n6327 = ndn3_46 & ~ngfdn_3 & n_n8222; + assign n6328 = ~ndn3_11 & n_n7814 & ndn3_9; + assign n6329 = n_n7810 & ndn3_19 & ~ndn3_21; + assign n6330 = nen3_28 & ~ndn3_28 & n_n8473; + assign n6331 = ndn3_44 & n_n8022 & ~ndn3_46; + assign n6332 = ~ndn3_44 & n_n7806 & ndn3_42; + assign n6333 = nen3_34 & ~ndn3_34 & n_n7859; + assign n6334 = ~ndn3_36 & nen3_36 & n_n7808; + assign n6335 = ~ndn3_18 & n_n8227 & ndn3_17; + assign n6336 = n_n8657 & nen3_22 & ~ndn3_22; + assign n6337 = ~ndn3_15 & n_n7812 & ~nsr3_13; + assign n6338 = n_n7793 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6339 = n_n7792 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6340 = n_n8267 & ~ndn3_7 & ndn3_4; + assign n6341 = ~ndn3_12 & n_n7791 & ndn3_11; + assign n6342 = n_n7788 & ~ndn3_42 & ndn3_40; + assign n6343 = ndn3_26 & ~ndn3_27 & n_n7809; + assign n6344 = ndn3_46 & n_n9635 & ~ngfdn_3; + assign n6345 = n_n9525 & nen3_16 & ~ndn3_16; + assign n6346 = ~ndn3_32 & ndn3_29 & n_n7790; + assign n6347 = ~ndn3_40 & n_n7789 & ndn3_39; + assign n6348 = n_n8402 & ndn3_19 & ~ndn3_21; + assign n6349 = n_n8841 & ~ndn3_25 & ndn3_22; + assign n6350 = ndn3_44 & n_n8223 & ~ndn3_46; + assign n6351 = ~ndn3_18 & ndn3_17 & n_n7811; + assign n6352 = (n7062 | n7063) & (n7069 | n7070); + assign n6353 = n5002 & ((n4988 & n4989_1) | (n4976 & (n4988 ^ n4989_1))); + assign n6354 = ~ndn3_2 & ~preset & psv2_5_5_ & n4949_1; + assign n6355 = ~preset & n_n9503 & (ndn3_2 | ~n4949_1); + assign n6356 = ~preset & n_n7779 & (ngfdn_3 | ~ndn3_46); + assign n6357 = n_n7764 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6358 = n_n8506 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6359 = ndn3_2 & n_n9387 & ~ndn3_4; + assign n6360 = n_n7990 & nen3_39 & ~ndn3_39; + assign n6361 = n_n7766 & ~ndn3_9 & ndn3_7; + assign n6362 = n_n9516 & ~ngfdn_3 & ndn3_46; + assign n6363 = ~ndn3_11 & n_n7765 & ndn3_9; + assign n6364 = n_n7762 & ndn3_19 & ~ndn3_21; + assign n6365 = n_n8852 & ~ndn3_28 & nen3_28; + assign n6366 = ndn3_44 & n_n7757 & ~ndn3_46; + assign n6367 = ~ndn3_44 & n_n7918 & ndn3_42; + assign n6368 = nen3_34 & n_n9157 & ~ndn3_34; + assign n6369 = ~ndn3_36 & n_n7758 & nen3_36; + assign n6370 = n_n8203 & ndn3_17 & ~ndn3_18; + assign n6371 = n_n7761 & nen3_22 & ~ndn3_22; + assign n6372 = n_n8396 & ~nsr3_13 & ~ndn3_15; + assign n6373 = n_n7901 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6374 = n_n7713 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6375 = ndn3_4 & n_n8086 & ~ndn3_7; + assign n6376 = n_n9210 & ndn3_11 & ~ndn3_12; + assign n6377 = ndn3_40 & n_n7707 & ~ndn3_42; + assign n6378 = ndn3_26 & n_n7760 & ~ndn3_27; + assign n6379 = ndn3_46 & ~ngfdn_3 & n_n7706; + assign n6380 = ~ndn3_16 & n_n8066 & nen3_16; + assign n6381 = ~ndn3_32 & ndn3_29 & n_n7710; + assign n6382 = ~ndn3_40 & n_n7708 & ndn3_39; + assign n6383 = ~ndn3_21 & n_n7712 & ndn3_19; + assign n6384 = n_n7711 & ~ndn3_25 & ndn3_22; + assign n6385 = ndn3_44 & n_n9110 & ~ndn3_46; + assign n6386 = n_n7763 & ndn3_17 & ~ndn3_18; + assign n6387 = n_n8760 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6388 = n_n7668 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6389 = ndn3_4 & n_n9300 & ~ndn3_7; + assign n6390 = ~ndn3_12 & ndn3_11 & n_n8276; + assign n6391 = n_n9505 & ~ndn3_42 & ndn3_40; + assign n6392 = ndn3_26 & ~ndn3_27 & n_n7684; + assign n6393 = ndn3_46 & ~ngfdn_3 & n_n7898; + assign n6394 = n_n8221 & nen3_16 & ~ndn3_16; + assign n6395 = ~ndn3_32 & ndn3_29 & n_n7666; + assign n6396 = n_n7664 & ndn3_39 & ~ndn3_40; + assign n6397 = ~ndn3_21 & n_n8597 & ndn3_19; + assign n6398 = n_n7667 & ~ndn3_25 & ndn3_22; + assign n6399 = n_n8628 & ~ndn3_46 & ndn3_44; + assign n6400 = n_n7687 & ndn3_17 & ~ndn3_18; + assign n6401 = n_n7803 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6402 = n_n8116 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6403 = ndn3_2 & n_n7689 & ~ndn3_4; + assign n6404 = n_n7682 & nen3_39 & ~ndn3_39; + assign n6405 = n_n9119 & ~ndn3_9 & ndn3_7; + assign n6406 = ndn3_46 & n_n9467 & ~ngfdn_3; + assign n6407 = n_n7688 & ndn3_9 & ~ndn3_11; + assign n6408 = n_n7686 & ndn3_19 & ~ndn3_21; + assign n6409 = nen3_28 & ~ndn3_28 & n_n7683; + assign n6410 = ndn3_44 & n_n8024 & ~ndn3_46; + assign n6411 = ~ndn3_44 & n_n7681 & ndn3_42; + assign n6412 = nen3_34 & ~ndn3_34 & n_n8889; + assign n6413 = n_n7732 & nen3_36 & ~ndn3_36; + assign n6414 = n_n8153 & ndn3_17 & ~ndn3_18; + assign n6415 = n_n7685 & nen3_22 & ~ndn3_22; + assign n6416 = ~ndn3_15 & n_n9257 & ~nsr3_13; + assign n6417 = n_n8786 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6418 = n_n8416 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6419 = ndn3_2 & n_n8739 & ~ndn3_4; + assign n6420 = n_n6968 & nen3_39 & ~ndn3_39; + assign n6421 = n_n7866 & ~ndn3_9 & ndn3_7; + assign n6422 = ndn3_46 & ~ngfdn_3 & n_n8980; + assign n6423 = n_n7424 & ndn3_9 & ~ndn3_11; + assign n6424 = n_n9342 & ndn3_19 & ~ndn3_21; + assign n6425 = n_n9338 & ~ndn3_28 & nen3_28; + assign n6426 = ndn3_44 & n_n8989 & ~ndn3_46; + assign n6427 = n_n7920 & ndn3_42 & ~ndn3_44; + assign n6428 = nen3_34 & ~ndn3_34 & n_n9159; + assign n6429 = ~ndn3_36 & n_n7831 & nen3_36; + assign n6430 = n_n8984 & ndn3_17 & ~ndn3_18; + assign n6431 = n_n7225 & nen3_22 & ~ndn3_22; + assign n6432 = n_n8833 & ~nsr3_13 & ~ndn3_15; + assign n6433 = (n7048 | n7049) & (n7055 | n7056); + assign n6434 = n4966 & ((n5007 & n5008) | (n4969_1 & (~n5007 ^ ~n5008))); + assign n6435 = n_n8375 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6436 = n_n7956 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6437 = ndn3_2 & n_n9023 & ~ndn3_4; + assign n6438 = ~ndn3_39 & nen3_39 & n_n8095; + assign n6439 = ndn3_7 & ~ndn3_9 & n_n7955; + assign n6440 = ndn3_46 & ~ngfdn_3 & n_n7947; + assign n6441 = ~ndn3_11 & ndn3_9 & n_n7954; + assign n6442 = n_n9021 & ndn3_19 & ~ndn3_21; + assign n6443 = nen3_28 & n_n9618 & ~ndn3_28; + assign n6444 = ndn3_44 & n_n7948 & ~ndn3_46; + assign n6445 = n_n7949 & ndn3_42 & ~ndn3_44; + assign n6446 = nen3_34 & n_n8891 & ~ndn3_34; + assign n6447 = ~ndn3_36 & nen3_36 & n_n7950; + assign n6448 = ~ndn3_18 & ndn3_17 & n_n7951; + assign n6449 = n_n8843 & nen3_22 & ~ndn3_22; + assign n6450 = ~ndn3_15 & n_n7953 & ~nsr3_13; + assign n6451 = n_n7696 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6452 = n_n7695 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6453 = ndn3_4 & ~ndn3_7 & n_n9302; + assign n6454 = n_n7694 & ndn3_11 & ~ndn3_12; + assign n6455 = ndn3_40 & ~ndn3_42 & n_n8326; + assign n6456 = ndn3_26 & ~ndn3_27 & n_n8854; + assign n6457 = ndn3_46 & ~ngfdn_3 & n_n7691; + assign n6458 = ~ndn3_16 & nen3_16 & n_n8659; + assign n6459 = ~ndn3_32 & ndn3_29 & n_n7693; + assign n6460 = ~ndn3_40 & n_n8410 & ndn3_39; + assign n6461 = ~ndn3_21 & n_n8599 & ndn3_19; + assign n6462 = n_n8697 & ~ndn3_25 & ndn3_22; + assign n6463 = ndn3_44 & n_n9518 & ~ndn3_46; + assign n6464 = n_n7952 & ndn3_17 & ~ndn3_18; + assign n6465 = n_n9347 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6466 = n_n9346 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6467 = n_n9348 & ~ndn3_7 & ndn3_4; + assign n6468 = n_n9345 & ndn3_11 & ~ndn3_12; + assign n6469 = ndn3_40 & n_n9335 & ~ndn3_42; + assign n6470 = ndn3_26 & n_n9339 & ~ndn3_27; + assign n6471 = ndn3_46 & ~ngfdn_3 & n_n9333; + assign n6472 = n_n9344 & nen3_16 & ~ndn3_16; + assign n6473 = ~ndn3_32 & ndn3_29 & n_n9337; + assign n6474 = ~ndn3_40 & ndn3_39 & n_n9455; + assign n6475 = ~ndn3_21 & n_n9341 & ndn3_19; + assign n6476 = n_n9340 & ~ndn3_25 & ndn3_22; + assign n6477 = ndn3_44 & n_n9334 & ~ndn3_46; + assign n6478 = ~ndn3_18 & ndn3_17 & n_n9343; + assign n6479 = ~preset & n_n9267 & (~ndn3_9 | ndn3_11); + assign n6480 = ~preset & n4847 & (~n4969_1 ^ ~n4970); + assign n6481 = n_n9602 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6482 = n_n9605 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6483 = n_n9606 & ~ndn3_4 & ndn3_2; + assign n6484 = n_n9591 & nen3_39 & ~ndn3_39; + assign n6485 = n_n9604 & ~ndn3_9 & ndn3_7; + assign n6486 = ndn3_46 & ~ngfdn_3 & n_n9588; + assign n6487 = n_n9603 & ndn3_9 & ~ndn3_11; + assign n6488 = ~ndn3_21 & n_n9598 & ndn3_19; + assign n6489 = nen3_28 & ~ndn3_28 & n_n9595; + assign n6490 = ndn3_44 & n_n9589 & ~ndn3_46; + assign n6491 = n_n9590 & ndn3_42 & ~ndn3_44; + assign n6492 = nen3_34 & ~ndn3_34 & n_n9593; + assign n6493 = ~ndn3_36 & nen3_36 & n_n9592; + assign n6494 = n_n9599 & ndn3_17 & ~ndn3_18; + assign n6495 = n_n9597 & nen3_22 & ~ndn3_22; + assign n6496 = ~ndn3_15 & n_n9601 & ~nsr3_13; + assign n6497 = n_n9269 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6498 = n_n9268 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6499 = n_n9270 & ~ndn3_7 & ndn3_4; + assign n6500 = ~ndn3_12 & n_n9267 & ndn3_11; + assign n6501 = ndn3_40 & n_n9260 & ~ndn3_42; + assign n6502 = ndn3_26 & n_n9596 & ~ndn3_27; + assign n6503 = ndn3_46 & ~ngfdn_3 & n_n9259; + assign n6504 = n_n9266 & nen3_16 & ~ndn3_16; + assign n6505 = ~ndn3_32 & ndn3_29 & n_n9263; + assign n6506 = ~ndn3_40 & ndn3_39 & n_n9261; + assign n6507 = ~ndn3_21 & n_n9265 & ndn3_19; + assign n6508 = n_n9264 & ~ndn3_25 & ndn3_22; + assign n6509 = ndn3_44 & n_n9470 & ~ndn3_46; + assign n6510 = n_n9600 & ndn3_17 & ~ndn3_18; + assign n6511 = n_n8377 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6512 = n_n9121 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6513 = n_n7881 & ~ndn3_4 & ndn3_2; + assign n6514 = n_n7874 & nen3_39 & ~ndn3_39; + assign n6515 = n_n7880 & ~ndn3_9 & ndn3_7; + assign n6516 = ndn3_46 & ~ngfdn_3 & n_n9458; + assign n6517 = n_n8051 & ndn3_9 & ~ndn3_11; + assign n6518 = n_n7876 & ndn3_19 & ~ndn3_21; + assign n6519 = nen3_28 & n_n9000 & ~ndn3_28; + assign n6520 = ndn3_44 & n_n8609 & ~ndn3_46; + assign n6521 = ~ndn3_44 & n_n7873 & ndn3_42; + assign n6522 = nen3_34 & n_n9327 & ~ndn3_34; + assign n6523 = ~ndn3_36 & nen3_36 & n_n7980; + assign n6524 = ~ndn3_18 & n_n7877 & ndn3_17; + assign n6525 = n_n7875 & nen3_22 & ~ndn3_22; + assign n6526 = n_n7879 & ~nsr3_13 & ~ndn3_15; + assign n6527 = n4965 & ((n4978 & n4979_1) | (n4972 & (~n4978 ^ ~n4979_1))); + assign n6528 = (n6922 | n6923) & (n6929 | n6930); + assign n6529 = n_n9404 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6530 = n_n9407 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6531 = ndn3_2 & n_n9408 & ~ndn3_4; + assign n6532 = n_n9393 & nen3_39 & ~ndn3_39; + assign n6533 = ndn3_7 & ~ndn3_9 & n_n9406; + assign n6534 = n_n9390 & ~ngfdn_3 & ndn3_46; + assign n6535 = n_n9405 & ndn3_9 & ~ndn3_11; + assign n6536 = ~ndn3_21 & n_n9400 & ndn3_19; + assign n6537 = nen3_28 & ~ndn3_28 & n_n9397; + assign n6538 = ndn3_44 & n_n9391 & ~ndn3_46; + assign n6539 = n_n9392 & ndn3_42 & ~ndn3_44; + assign n6540 = nen3_34 & n_n9395 & ~ndn3_34; + assign n6541 = ~ndn3_36 & nen3_36 & n_n9394; + assign n6542 = ~ndn3_18 & n_n9401 & ndn3_17; + assign n6543 = ~ndn3_22 & nen3_22 & n_n9399; + assign n6544 = n_n9403 & ~nsr3_13 & ~ndn3_15; + assign n6545 = (n6964 | n6965) & (n6971 | n6972); + assign n6546 = n4973 & ((n4981 & n4982) | (n4955 & (~n4981 ^ ~n4982))); + assign n6547 = n_n7742 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6548 = n_n7837 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6549 = ndn3_2 & ~ndn3_4 & n_n7744; + assign n6550 = ~ndn3_39 & nen3_39 & n_n7734; + assign n6551 = ndn3_7 & ~ndn3_9 & n_n8053; + assign n6552 = n_n8135 & ~ngfdn_3 & ndn3_46; + assign n6553 = n_n7743 & ndn3_9 & ~ndn3_11; + assign n6554 = n_n7741 & ndn3_19 & ~ndn3_21; + assign n6555 = nen3_28 & n_n7738 & ~ndn3_28; + assign n6556 = ndn3_44 & n_n8247 & ~ndn3_46; + assign n6557 = ~ndn3_44 & n_n9059 & ndn3_42; + assign n6558 = nen3_34 & n_n7736 & ~ndn3_34; + assign n6559 = ~ndn3_36 & n_n7735 & nen3_36; + assign n6560 = ~ndn3_18 & n_n9141 & ndn3_17; + assign n6561 = ~ndn3_22 & nen3_22 & n_n7740; + assign n6562 = ~ndn3_15 & n_n9189 & ~nsr3_13; + assign n6563 = n_n7655 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6564 = n_n7657 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6565 = n_n8770 & ~ndn3_4 & ndn3_2; + assign n6566 = ~ndn3_39 & nen3_39 & n_n7650; + assign n6567 = n_n8619 & ~ndn3_9 & ndn3_7; + assign n6568 = ndn3_46 & ~ngfdn_3 & n_n8862; + assign n6569 = ~ndn3_11 & ndn3_9 & n_n7656; + assign n6570 = ~ndn3_21 & n_n7654 & ndn3_19; + assign n6571 = nen3_28 & ~ndn3_28 & n_n7652; + assign n6572 = ndn3_44 & ~ndn3_46 & n_n8249; + assign n6573 = n_n9061 & ndn3_42 & ~ndn3_44; + assign n6574 = nen3_34 & ~ndn3_34 & n_n9075; + assign n6575 = ~ndn3_36 & n_n7651 & nen3_36; + assign n6576 = ~ndn3_18 & ndn3_17 & n_n9015; + assign n6577 = n_n7653 & nen3_22 & ~ndn3_22; + assign n6578 = ~ndn3_15 & n_n8260 & ~nsr3_13; + assign n6579 = n_n8641 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6580 = n_n9566 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6581 = n_n7511 & ~ndn3_7 & ndn3_4; + assign n6582 = n_n8075 & ndn3_11 & ~ndn3_12; + assign n6583 = ndn3_40 & ~ndn3_42 & n_n8477; + assign n6584 = ndn3_26 & ~ndn3_27 & n_n7728; + assign n6585 = n_n8670 & ~ngfdn_3 & ndn3_46; + assign n6586 = ~ndn3_16 & nen3_16 & n_n8210; + assign n6587 = n_n8526 & ndn3_29 & ~ndn3_32; + assign n6588 = ~ndn3_40 & n_n7995 & ndn3_39; + assign n6589 = n_n7510 & ndn3_19 & ~ndn3_21; + assign n6590 = n_n9522 & ~ndn3_25 & ndn3_22; + assign n6591 = ndn3_44 & n_n7670 & ~ndn3_46; + assign n6592 = n_n7661 & ndn3_17 & ~ndn3_18; + assign n6593 = n_n9052 & (n6899 | (nen3_22 & ~ndn3_22)); + assign n6594 = n_n9051 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6595 = n_n9053 & ~ndn3_7 & ndn3_4; + assign n6596 = n_n9050 & ndn3_11 & ~ndn3_12; + assign n6597 = ndn3_40 & n_n9043 & ~ndn3_42; + assign n6598 = ndn3_26 & n_n9368 & ~ndn3_27; + assign n6599 = ndn3_46 & ~ngfdn_3 & n_n9041; + assign n6600 = ~ndn3_16 & n_n9049 & nen3_16; + assign n6601 = ~ndn3_32 & ndn3_29 & n_n9046; + assign n6602 = ~ndn3_40 & n_n9044 & ndn3_39; + assign n6603 = n_n9048 & ndn3_19 & ~ndn3_21; + assign n6604 = n_n9047 & ~ndn3_25 & ndn3_22; + assign n6605 = ndn3_44 & n_n9042 & ~ndn3_46; + assign n6606 = n_n9319 & ndn3_17 & ~ndn3_18; + assign n6607 = n_n9321 & (n6908 | (nen3_16 & ~ndn3_16)); + assign n6608 = n_n9324 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6609 = ndn3_2 & n_n9325 & ~ndn3_4; + assign n6610 = ~ndn3_39 & n_n9311 & nen3_39; + assign n6611 = n_n9323 & ~ndn3_9 & ndn3_7; + assign n6612 = ndn3_46 & ~ngfdn_3 & n_n9308; + assign n6613 = n_n9322 & ndn3_9 & ~ndn3_11; + assign n6614 = n_n9317 & ndn3_19 & ~ndn3_21; + assign n6615 = nen3_28 & ~ndn3_28 & n_n9315; + assign n6616 = ndn3_44 & n_n9309 & ~ndn3_46; + assign n6617 = ~ndn3_44 & n_n9310 & ndn3_42; + assign n6618 = nen3_34 & ~ndn3_34 & n_n9313; + assign n6619 = ~ndn3_36 & nen3_36 & n_n9312; + assign n6620 = n_n9318 & ndn3_17 & ~ndn3_18; + assign n6621 = n_n9316 & nen3_22 & ~ndn3_22; + assign n6622 = n_n9320 & ~nsr3_13 & ~ndn3_15; + assign n6623 = n_n7553 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6624 = n_n9563 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6625 = n_n7554 & ~ndn3_7 & ndn3_4; + assign n6626 = ~ndn3_12 & n_n8298 & ndn3_11; + assign n6627 = ndn3_40 & ~ndn3_42 & n_n8636; + assign n6628 = ndn3_26 & ~ndn3_27 & n_n7739; + assign n6629 = n_n9239 & ~ngfdn_3 & ndn3_46; + assign n6630 = ~ndn3_16 & nen3_16 & n_n8381; + assign n6631 = ~ndn3_32 & n_n7552 & ndn3_29; + assign n6632 = ~ndn3_40 & ndn3_39 & n_n7993; + assign n6633 = ~ndn3_21 & n_n8035 & ndn3_19; + assign n6634 = ndn3_22 & n_n8533 & ~ndn3_25; + assign n6635 = ndn3_44 & n_n8499 & ~ndn3_46; + assign n6636 = ~ndn3_18 & ndn3_17 & n_n9528; + assign n6637 = n_n9135 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6638 = n_n9134 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6639 = n_n9136 & ~ndn3_7 & ndn3_4; + assign n6640 = n_n9133 & ndn3_11 & ~ndn3_12; + assign n6641 = ndn3_40 & n_n9127 & ~ndn3_42; + assign n6642 = ndn3_26 & n_n9398 & ~ndn3_27; + assign n6643 = ndn3_46 & ~ngfdn_3 & n_n9125; + assign n6644 = ~ndn3_16 & nen3_16 & n_n9132; + assign n6645 = ~ndn3_32 & ndn3_29 & n_n9129; + assign n6646 = ~ndn3_40 & ndn3_39 & n_n9128; + assign n6647 = n_n9131 & ndn3_19 & ~ndn3_21; + assign n6648 = ndn3_22 & n_n9130 & ~ndn3_25; + assign n6649 = ndn3_44 & ~ndn3_46 & n_n9126; + assign n6650 = n_n9402 & ndn3_17 & ~ndn3_18; + assign n6651 = n_n8791 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6652 = n_n9008 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6653 = n_n7604 & ~ndn3_7 & ndn3_4; + assign n6654 = n_n8296 & ndn3_11 & ~ndn3_12; + assign n6655 = ndn3_40 & n_n7599 & ~ndn3_42; + assign n6656 = ndn3_26 & n_n7822 & ~ndn3_27; + assign n6657 = n_n9237 & ~ngfdn_3 & ndn3_46; + assign n6658 = ~ndn3_16 & nen3_16 & n_n8042; + assign n6659 = n_n7601 & ndn3_29 & ~ndn3_32; + assign n6660 = ~ndn3_40 & ndn3_39 & n_n8253; + assign n6661 = ~ndn3_21 & ndn3_19 & n_n7603; + assign n6662 = ndn3_22 & ~ndn3_25 & n_n7602; + assign n6663 = ndn3_44 & n_n7598 & ~ndn3_46; + assign n6664 = n_n8233 & ndn3_17 & ~ndn3_18; + assign n6665 = n_n7825 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6666 = n_n7835 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6667 = ndn3_2 & ~ndn3_4 & n_n7827; + assign n6668 = ~ndn3_39 & n_n7819 & nen3_39; + assign n6669 = ndn3_7 & ~ndn3_9 & n_n7826; + assign n6670 = ndn3_46 & ~ngfdn_3 & n_n8898; + assign n6671 = n_n8617 & ndn3_9 & ~ndn3_11; + assign n6672 = ~ndn3_21 & n_n7823 & ndn3_19; + assign n6673 = nen3_28 & n_n7821 & ~ndn3_28; + assign n6674 = ndn3_44 & n_n9036 & ~ndn3_46; + assign n6675 = n_n9081 & ndn3_42 & ~ndn3_44; + assign n6676 = nen3_34 & n_n7820 & ~ndn3_34; + assign n6677 = ~ndn3_36 & nen3_36 & n_n7925; + assign n6678 = n_n7824 & ndn3_17 & ~ndn3_18; + assign n6679 = ~ndn3_22 & n_n8699 & nen3_22; + assign n6680 = n_n9186 & ~nsr3_13 & ~ndn3_15; + assign n6681 = n_n9499 & ((nen3_16 & ~ndn3_16) | n6908); + assign n6682 = n_n9502 & ((~ndn3_25 & ndn3_22) | n6909); + assign n6683 = ndn3_2 & n_n9503 & ~ndn3_4; + assign n6684 = n_n9488 & nen3_39 & ~ndn3_39; + assign n6685 = ndn3_7 & ~ndn3_9 & n_n9501; + assign n6686 = ndn3_46 & n_n9485 & ~ngfdn_3; + assign n6687 = n_n9500 & ndn3_9 & ~ndn3_11; + assign n6688 = n_n9495 & ndn3_19 & ~ndn3_21; + assign n6689 = nen3_28 & n_n9492 & ~ndn3_28; + assign n6690 = ndn3_44 & n_n9486 & ~ndn3_46; + assign n6691 = ~ndn3_44 & n_n9487 & ndn3_42; + assign n6692 = nen3_34 & ~ndn3_34 & n_n9490; + assign n6693 = ~ndn3_36 & n_n9489 & nen3_36; + assign n6694 = n_n9496 & ndn3_17 & ~ndn3_18; + assign n6695 = n_n9494 & nen3_22 & ~ndn3_22; + assign n6696 = n_n9498 & ~nsr3_13 & ~ndn3_15; + assign n6697 = n_n9181 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6698 = n_n9180 & (n6900 | (~ndn3_17 & ndn3_16)); + assign n6699 = ndn3_4 & ~ndn3_7 & n_n9182; + assign n6700 = n_n9179 & ndn3_11 & ~ndn3_12; + assign n6701 = ndn3_40 & n_n9172 & ~ndn3_42; + assign n6702 = ndn3_26 & ~ndn3_27 & n_n9493; + assign n6703 = ndn3_46 & ~ngfdn_3 & n_n9171; + assign n6704 = n_n9178 & nen3_16 & ~ndn3_16; + assign n6705 = ~ndn3_32 & ndn3_29 & n_n9175; + assign n6706 = ~ndn3_40 & ndn3_39 & n_n9173; + assign n6707 = n_n9177 & ndn3_19 & ~ndn3_21; + assign n6708 = n_n9176 & ~ndn3_25 & ndn3_22; + assign n6709 = ndn3_44 & n_n9473 & ~ndn3_46; + assign n6710 = n_n9497 & ndn3_17 & ~ndn3_18; + assign n6711 = n_n8789 & ((nen3_22 & ~ndn3_22) | n6899); + assign n6712 = n_n8961 & ((~ndn3_17 & ndn3_16) | n6900); + assign n6713 = ndn3_4 & n_n7643 & ~ndn3_7; + assign n6714 = n_n7642 & ndn3_11 & ~ndn3_12; + assign n6715 = ndn3_40 & n_n8328 & ~ndn3_42; + assign n6716 = ndn3_26 & ~ndn3_27 & n_n8856; + assign n6717 = n_n8188 & ~ngfdn_3 & ndn3_46; + assign n6718 = ~ndn3_16 & n_n8661 & nen3_16; + assign n6719 = ~ndn3_32 & ndn3_29 & n_n7649; + assign n6720 = ~ndn3_40 & n_n8552 & ndn3_39; + assign n6721 = n_n8058 & ndn3_19 & ~ndn3_21; + assign n6722 = n_n7641 & ~ndn3_25 & ndn3_22; + assign n6723 = ndn3_44 & n_n7640 & ~ndn3_46; + assign n6724 = n_n7878 & ndn3_17 & ~ndn3_18; + assign n6725 = ~preset & n_n7726 & (~ndn3_39 | ndn3_40); + assign n6726 = ~ndn3_40 & ndn3_39 & ~preset & n_n7376; + assign n6727 = ~preset & n_n9260 & (ndn3_37 | nsr3_37); + assign n6728 = ~preset & n_n9172 & (ndn3_37 | nsr3_37); + assign n6729 = nsr3_14 & ~nsr3_13 & n_n8649; + assign n6730 = nsr3_20 & ndn3_17 & n_n8648; + assign n6731 = n_n8650 & nsr3_13 & ndn3_12; + assign n6732 = n_n8796 & ndn3_29 & nsr3_35; + assign n6733 = nen3_34 & n_n8647 & nsr3_37; + assign n6734 = ndn3_26 & n_n9242 & nsr3_30; + assign n6735 = n_n8646 & nsr3_38 & nen3_36; + assign n6736 = n_n9013 & nsr3_23 & ndn3_19; + assign n6737 = n_n7629 & ~nsr3_13 & nsr3_14; + assign n6738 = n_n7628 & ndn3_17 & nsr3_20; + assign n6739 = n_n7630 & nsr3_13 & ndn3_12; + assign n6740 = nsr3_35 & n_n8613 & ndn3_29; + assign n6741 = nen3_34 & n_n8875 & nsr3_37; + assign n6742 = ndn3_26 & nsr3_30 & n_n8141; + assign n6743 = n_n7627 & nsr3_38 & nen3_36; + assign n6744 = ndn3_19 & nsr3_23 & n_n7983; + assign n6745 = n_n9165 & ~nsr3_13 & nsr3_14; + assign n6746 = nsr3_20 & ndn3_17 & n_n9164; + assign n6747 = n_n9166 & nsr3_13 & ndn3_12; + assign n6748 = n_n9161 & ndn3_29 & nsr3_35; + assign n6749 = nen3_34 & n_n9160 & nsr3_37; + assign n6750 = ndn3_26 & nsr3_30 & n_n9162; + assign n6751 = n_n9578 & nsr3_38 & nen3_36; + assign n6752 = n_n9163 & nsr3_23 & ndn3_19; + assign n6753 = nsr3_14 & ~nsr3_13 & n_n8240; + assign n6754 = nsr3_20 & ndn3_17 & n_n8239; + assign n6755 = n_n8241 & nsr3_13 & ndn3_12; + assign n6756 = n_n8312 & ndn3_29 & nsr3_35; + assign n6757 = nen3_34 & n_n8236 & nsr3_37; + assign n6758 = ndn3_26 & n_n8237 & nsr3_30; + assign n6759 = nen3_36 & nsr3_38 & n_n8235; + assign n6760 = n_n8238 & nsr3_23 & ndn3_19; + assign n6761 = n_n8574 & ~nsr3_13 & nsr3_14; + assign n6762 = nsr3_20 & n_n8573 & ndn3_17; + assign n6763 = n_n8575 & nsr3_13 & ndn3_12; + assign n6764 = nsr3_35 & ndn3_29 & n_n8572; + assign n6765 = nen3_34 & n_n8571 & nsr3_37; + assign n6766 = ndn3_26 & nsr3_30 & n_n8970; + assign n6767 = n_n8570 & nsr3_38 & nen3_36; + assign n6768 = ndn3_19 & n_n9150 & nsr3_23; + assign n6769 = nsr3_14 & n_n9362 & ~nsr3_13; + assign n6770 = nsr3_20 & ndn3_17 & n_n9552; + assign n6771 = n_n9363 & nsr3_13 & ndn3_12; + assign n6772 = n_n9359 & ndn3_29 & nsr3_35; + assign n6773 = nen3_34 & n_n9358 & nsr3_37; + assign n6774 = ndn3_26 & nsr3_30 & n_n9360; + assign n6775 = n_n9357 & nsr3_38 & nen3_36; + assign n6776 = ndn3_19 & n_n9361 & nsr3_23; + assign n6777 = n_n9292 & ~nsr3_13 & nsr3_14; + assign n6778 = nsr3_20 & ndn3_17 & n_n9291; + assign n6779 = ndn3_12 & n_n9410 & nsr3_13; + assign n6780 = n_n9289 & ndn3_29 & nsr3_35; + assign n6781 = nen3_34 & n_n9539 & nsr3_37; + assign n6782 = ndn3_26 & n_n9290 & nsr3_30; + assign n6783 = n_n9296 & nsr3_38 & nen3_36; + assign n6784 = n_n9298 & nsr3_23 & ndn3_19; + assign n6785 = nsr3_14 & ~nsr3_13 & n_n8273; + assign n6786 = nsr3_20 & ndn3_17 & n_n8272; + assign n6787 = ndn3_12 & nsr3_13 & n_n8274; + assign n6788 = nsr3_35 & ndn3_29 & n_n8348; + assign n6789 = nen3_34 & n_n8269 & nsr3_37; + assign n6790 = ndn3_26 & n_n8270 & nsr3_30; + assign n6791 = nen3_36 & n_n8508 & nsr3_38; + assign n6792 = n_n8271 & nsr3_23 & ndn3_19; + assign n6793 = nsr3_14 & n_n9560 & ~nsr3_13; + assign n6794 = nsr3_20 & ndn3_17 & n_n9559; + assign n6795 = ndn3_12 & n_n9561 & nsr3_13; + assign n6796 = n_n9556 & ndn3_29 & nsr3_35; + assign n6797 = nen3_34 & n_n9555 & nsr3_37; + assign n6798 = ndn3_26 & n_n9557 & nsr3_30; + assign n6799 = nen3_36 & n_n9554 & nsr3_38; + assign n6800 = n_n9558 & nsr3_23 & ndn3_19; + assign n6801 = nsr3_14 & ~nsr3_13 & n_n9510; + assign n6802 = nsr3_20 & ndn3_17 & n_n7854; + assign n6803 = ndn3_12 & n_n8037 & nsr3_13; + assign n6804 = n_n7852 & ndn3_29 & nsr3_35; + assign n6805 = nen3_34 & nsr3_37 & n_n8756; + assign n6806 = ndn3_26 & nsr3_30 & n_n8972; + assign n6807 = n_n8171 & nsr3_38 & nen3_36; + assign n6808 = n_n7853 & nsr3_23 & ndn3_19; + assign n6809 = nsr3_14 & ~nsr3_13 & n_n7771; + assign n6810 = n_n7770 & ndn3_17 & nsr3_20; + assign n6811 = n_n7961 & nsr3_13 & ndn3_12; + assign n6812 = nsr3_35 & ndn3_29 & n_n9331; + assign n6813 = nen3_34 & n_n7768 & nsr3_37; + assign n6814 = ndn3_26 & nsr3_30 & n_n7769; + assign n6815 = nen3_36 & n_n8173 & nsr3_38; + assign n6816 = n_n8803 & nsr3_23 & ndn3_19; + assign n6817 = nsr3_14 & n_n8199 & ~nsr3_13; + assign n6818 = nsr3_20 & n_n9280 & ndn3_17; + assign n6819 = n_n8200 & nsr3_13 & ndn3_12; + assign n6820 = n_n8197 & ndn3_29 & nsr3_35; + assign n6821 = nen3_34 & n_n8710 & nsr3_37; + assign n6822 = ndn3_26 & nsr3_30 & n_n8366; + assign n6823 = nen3_36 & n_n8196 & nsr3_38; + assign n6824 = n_n8198 & nsr3_23 & ndn3_19; + assign n6825 = n_n9441 & ~nsr3_13 & nsr3_14; + assign n6826 = nsr3_20 & ndn3_17 & n_n9550; + assign n6827 = ndn3_12 & n_n9442 & nsr3_13; + assign n6828 = nsr3_35 & ndn3_29 & n_n9438; + assign n6829 = nen3_34 & n_n9437 & nsr3_37; + assign n6830 = ndn3_26 & nsr3_30 & n_n9439; + assign n6831 = n_n9436 & nsr3_38 & nen3_36; + assign n6832 = n_n9440 & nsr3_23 & ndn3_19; + assign n6833 = nsr3_14 & ~nsr3_13 & n_n7584; + assign n6834 = n_n8447 & ndn3_17 & nsr3_20; + assign n6835 = n_n8691 & nsr3_13 & ndn3_12; + assign n6836 = nsr3_35 & ndn3_29 & n_n8968; + assign n6837 = nen3_34 & n_n7582 & nsr3_37; + assign n6838 = ndn3_26 & n_n7583 & nsr3_30; + assign n6839 = n_n8016 & nsr3_38 & nen3_36; + assign n6840 = n_n7985 & nsr3_23 & ndn3_19; + assign n6841 = n_n7704 & ~nsr3_13 & nsr3_14; + assign n6842 = nsr3_20 & ndn3_17 & n_n8685; + assign n6843 = n_n8577 & nsr3_13 & ndn3_12; + assign n6844 = n_n9294 & ndn3_29 & nsr3_35; + assign n6845 = nen3_34 & nsr3_37 & n_n8118; + assign n6846 = ndn3_26 & n_n7702 & nsr3_30; + assign n6847 = n_n7701 & nsr3_38 & nen3_36; + assign n6848 = ndn3_19 & nsr3_23 & n_n7703; + assign n6849 = nsr3_14 & n_n8531 & ~nsr3_13; + assign n6850 = nsr3_20 & ndn3_17 & n_n8530; + assign n6851 = ndn3_12 & nsr3_13 & n_n8615; + assign n6852 = n_n9275 & ndn3_29 & nsr3_35; + assign n6853 = nen3_34 & n_n8529 & nsr3_37; + assign n6854 = ndn3_26 & n_n9244 & nsr3_30; + assign n6855 = n_n8528 & nsr3_38 & nen3_36; + assign n6856 = ndn3_19 & nsr3_23 & n_n8935; + assign n6857 = n6849 | n6850 | n6851 | n6852; + assign n6858 = n6853 | n6854 | n6855 | n6856; + assign n6859 = n6753 | n6754 | n6755 | n6756; + assign n6860 = n6757 | n6758 | n6759 | n6760; + assign n6861 = n6761 | n6762 | n6763 | n6764; + assign n6862 = n6765 | n6766 | n6767 | n6768; + assign n6863 = n6769 | n6770 | n6771 | n6772; + assign n6864 = n6773 | n6774 | n6775 | n6776; + assign n6865 = n6833 | n6834 | n6835 | n6836; + assign n6866 = n6837 | n6838 | n6839 | n6840; + assign n6867 = n6841 | n6842 | n6843 | n6844; + assign n6868 = n6845 | n6846 | n6847 | n6848; + assign n6869 = n6737 | n6738 | n6739 | n6740; + assign n6870 = n6741 | n6742 | n6743 | n6744; + assign n6871 = n6809 | n6810 | n6811 | n6812; + assign n6872 = n6813 | n6814 | n6815 | n6816; + assign n6873 = n6793 | n6794 | n6795 | n6796; + assign n6874 = n6797 | n6798 | n6799 | n6800; + assign n6875 = n6745 | n6746 | n6747 | n6748; + assign n6876 = n6749 | n6750 | n6751 | n6752; + assign n6877 = n6729 | n6730 | n6731 | n6732; + assign n6878 = n6733 | n6734 | n6735 | n6736; + assign n6879 = n6801 | n6802 | n6803 | n6804; + assign n6880 = n6805 | n6806 | n6807 | n6808; + assign n6881 = n6777 | n6778 | n6779 | n6780; + assign n6882 = n6781 | n6782 | n6783 | n6784; + assign n6883 = n6825 | n6826 | n6827 | n6828; + assign n6884 = n6829 | n6830 | n6831 | n6832; + assign n6885 = n6785 | n6786 | n6787 | n6788; + assign n6886 = n6789 | n6790 | n6791 | n6792; + assign n6887 = n6817 | n6818 | n6819 | n6820; + assign n6888 = n6821 | n6822 | n6823 | n6824; + assign n6889 = n6857 | n6858 | n6859 | n6860; + assign n6890 = n6861 | n6862 | n6863 | n6864; + assign n6891 = n6865 | n6866 | n6867 | n6868; + assign n6892 = n6869 | n6870 | n6871 | n6872; + assign n6893 = n6873 | n6874 | n6875 | n6876; + assign n6894 = n6877 | n6878 | n6879 | n6880; + assign n6895 = n6881 | n6882 | n6883 | n6884; + assign n6896 = n6885 | n6886 | n6887 | n6888; + assign n6897 = n6889 | n6890 | n6891 | n6892; + assign n6898 = n6893 | n6894 | n6895 | n6896; + assign n6899 = (~ndn3_9 & ndn3_7) | (ndn3_25 & ~ndn3_26); + assign n6900 = (ndn3_9 & ~ndn3_11) | (~nsr3_13 & ~ndn3_15); + assign n6901 = (n_n8779 & n4960) | (n_n7876 & n4961); + assign n6902 = (n_n7644 & n4958) | (n_n9000 & n4959_1); + assign n6903 = n6713 | n6714 | n6715 | n6716; + assign n6904 = n6717 | n6718 | n6719 | n6720; + assign n6905 = n6721 | n6722 | n6723 | n6724; + assign n6906 = n6905 | n6711 | n6712; + assign n6907 = n6901 | n6902 | n6903 | n6904; + assign n6908 = (~ndn3_19 & nen3_19) | (ndn3_11 & ~ndn3_12); + assign n6909 = (~ndn3_29 & ndn3_28) | (~ndn3_7 & ndn3_4); + assign n6910 = (n_n9230 & n4963) | (n_n7878 & n4964_1); + assign n6911 = n6514 | n6513 | (n_n8856 & n4962); + assign n6912 = n6515 | n6516 | n6517 | n6518; + assign n6913 = n6519 | n6520 | n6521 | n6522; + assign n6914 = n6523 | n6524 | n6525 | n6526; + assign n6915 = n6914 | n6511 | n6512; + assign n6916 = n6910 | n6911 | n6912 | n6913; + assign n6917 = (n_n9491 & n4963) | (n_n9497 & n4964_1); + assign n6918 = n6684 | n6683 | (n_n9493 & n4962); + assign n6919 = n6685 | n6686 | n6687 | n6688; + assign n6920 = n6689 | n6690 | n6691 | n6692; + assign n6921 = n6693 | n6694 | n6695 | n6696; + assign n6922 = n6921 | n6681 | n6682; + assign n6923 = n6917 | n6918 | n6919 | n6920; + assign n6924 = (n_n9495 & n4961) | (n_n9174 & n4960); + assign n6925 = (n_n9183 & n4958) | (n_n9492 & n4959_1); + assign n6926 = n6699 | n6700 | n6701 | n6702; + assign n6927 = n6703 | n6704 | n6705 | n6706; + assign n6928 = n6707 | n6708 | n6709 | n6710; + assign n6929 = n6928 | n6697 | n6698; + assign n6930 = n6924 | n6925 | n6926 | n6927; + assign n6931 = (n_n9232 & n4963) | (n_n8233 & n4964_1); + assign n6932 = n6668 | n6667 | (n_n7822 & n4962); + assign n6933 = n6669 | n6670 | n6671 | n6672; + assign n6934 = n6673 | n6674 | n6675 | n6676; + assign n6935 = n6677 | n6678 | n6679 | n6680; + assign n6936 = n6935 | n6665 | n6666; + assign n6937 = n6931 | n6932 | n6933 | n6934; + assign n6938 = (n_n7600 & n4960) | (n_n7823 & n4961); + assign n6939 = (n_n7821 & n4959_1) | (n_n8736 & n4958); + assign n6940 = n6653 | n6654 | n6655 | n6656; + assign n6941 = n6657 | n6658 | n6659 | n6660; + assign n6942 = n6661 | n6662 | n6663 | n6664; + assign n6943 = n6942 | n6651 | n6652; + assign n6944 = n6938 | n6939 | n6940 | n6941; + assign n6945 = (n_n9212 & n4960) | (n_n9400 & n4961); + assign n6946 = (n_n9137 & n4958) | (n_n9397 & n4959_1); + assign n6947 = n6639 | n6640 | n6641 | n6642; + assign n6948 = n6643 | n6644 | n6645 | n6646; + assign n6949 = n6647 | n6648 | n6649 | n6650; + assign n6950 = n6949 | n6637 | n6638; + assign n6951 = n6945 | n6946 | n6947 | n6948; + assign n6952 = (n_n9402 & n4964_1) | (n_n9396 & n4963); + assign n6953 = n6532 | n6531 | (n_n9398 & n4962); + assign n6954 = n6533 | n6534 | n6535 | n6536; + assign n6955 = n6537 | n6538 | n6539 | n6540; + assign n6956 = n6541 | n6542 | n6543 | n6544; + assign n6957 = n6956 | n6529 | n6530; + assign n6958 = n6952 | n6953 | n6954 | n6955; + assign n6959 = (n_n7741 & n4961) | (n_n8638 & n4960); + assign n6960 = (n_n8009 & n4958) | (n_n7738 & n4959_1); + assign n6961 = n6625 | n6626 | n6627 | n6628; + assign n6962 = n6629 | n6630 | n6631 | n6632; + assign n6963 = n6633 | n6634 | n6635 | n6636; + assign n6964 = n6963 | n6623 | n6624; + assign n6965 = n6959 | n6960 | n6961 | n6962; + assign n6966 = (n_n7737 & n4963) | (n_n9528 & n4964_1); + assign n6967 = n6550 | n6549 | (n_n7739 & n4962); + assign n6968 = n6551 | n6552 | n6553 | n6554; + assign n6969 = n6555 | n6556 | n6557 | n6558; + assign n6970 = n6559 | n6560 | n6561 | n6562; + assign n6971 = n6970 | n6547 | n6548; + assign n6972 = n6966 | n6967 | n6968 | n6969; + assign n6973 = (n_n9317 & n4961) | (n_n9045 & n4960); + assign n6974 = (n_n9315 & n4959_1) | (n_n9054 & n4958); + assign n6975 = n6595 | n6596 | n6597 | n6598; + assign n6976 = n6599 | n6600 | n6601 | n6602; + assign n6977 = n6603 | n6604 | n6605 | n6606; + assign n6978 = n6977 | n6593 | n6594; + assign n6979 = n6973 | n6974 | n6975 | n6976; + assign n6980 = (n_n9314 & n4963) | (n_n9319 & n4964_1); + assign n6981 = n6610 | n6609 | (n_n9368 & n4962); + assign n6982 = n6611 | n6612 | n6613 | n6614; + assign n6983 = n6615 | n6616 | n6617 | n6618; + assign n6984 = n6619 | n6620 | n6621 | n6622; + assign n6985 = n6984 | n6607 | n6608; + assign n6986 = n6980 | n6981 | n6982 | n6983; + assign n6987 = (n_n7509 & n4960) | (n_n7654 & n4961); + assign n6988 = (n_n8011 & n4958) | (n_n7652 & n4959_1); + assign n6989 = n6581 | n6582 | n6583 | n6584; + assign n6990 = n6585 | n6586 | n6587 | n6588; + assign n6991 = n6589 | n6590 | n6591 | n6592; + assign n6992 = n6991 | n6579 | n6580; + assign n6993 = n6987 | n6988 | n6989 | n6990; + assign n6994 = (n_n8033 & n4963) | (n_n7661 & n4964_1); + assign n6995 = n6566 | n6565 | (n_n7728 & n4962); + assign n6996 = n6567 | n6568 | n6569 | n6570; + assign n6997 = n6571 | n6572 | n6573 | n6574; + assign n6998 = n6575 | n6576 | n6577 | n6578; + assign n6999 = n6998 | n6563 | n6564; + assign n7000 = n6994 | n6995 | n6996 | n6997; + assign n7001 = (n_n9262 & n4960) | (n_n9598 & n4961); + assign n7002 = (n_n9595 & n4959_1) | (n_n9271 & n4958); + assign n7003 = n6499 | n6500 | n6501 | n6502; + assign n7004 = n6503 | n6504 | n6505 | n6506; + assign n7005 = n6507 | n6508 | n6509 | n6510; + assign n7006 = n7005 | n6497 | n6498; + assign n7007 = n7001 | n7002 | n7003 | n7004; + assign n7008 = (n_n9594 & n4963) | (n_n9600 & n4964_1); + assign n7009 = n6484 | n6483 | (n_n9596 & n4962); + assign n7010 = n6485 | n6486 | n6487 | n6488; + assign n7011 = n6489 | n6490 | n6491 | n6492; + assign n7012 = n6493 | n6494 | n6495 | n6496; + assign n7013 = n7012 | n6481 | n6482; + assign n7014 = n7008 | n7009 | n7010 | n7011; + assign n7015 = (n_n7686 & n4961) | (n_n7665 & n4960); + assign n7016 = (n_n7683 & n4959_1) | (n_n8110 & n4958); + assign n7017 = n6389 | n6390 | n6391 | n6392; + assign n7018 = n6393 | n6394 | n6395 | n6396; + assign n7019 = n6397 | n6398 | n6399 | n6400; + assign n7020 = n7019 | n6387 | n6388; + assign n7021 = n7015 | n7016 | n7017 | n7018; + assign n7022 = (n_n8586 & n4963) | (n_n7687 & n4964_1); + assign n7023 = n6404 | n6403 | (n_n7684 & n4962); + assign n7024 = n6405 | n6406 | n6407 | n6408; + assign n7025 = n6409 | n6410 | n6411 | n6412; + assign n7026 = n6413 | n6414 | n6415 | n6416; + assign n7027 = n7026 | n6401 | n6402; + assign n7028 = n7022 | n7023 | n7024 | n7025; + assign n7029 = (n_n9342 & n4961) | (n_n9336 & n4960); + assign n7030 = (n_n9338 & n4959_1) | (n_n9349 & n4958); + assign n7031 = n6467 | n6468 | n6469 | n6470; + assign n7032 = n6471 | n6472 | n6473 | n6474; + assign n7033 = n6475 | n6476 | n6477 | n6478; + assign n7034 = n7033 | n6465 | n6466; + assign n7035 = n7029 | n7030 | n7031 | n7032; + assign n7036 = (n_n6976 & n4963) | (n_n9343 & n4964_1); + assign n7037 = n6420 | n6419 | (n_n9339 & n4962); + assign n7038 = n6421 | n6422 | n6423 | n6424; + assign n7039 = n6425 | n6426 | n6427 | n6428; + assign n7040 = n6429 | n6430 | n6431 | n6432; + assign n7041 = n7040 | n6417 | n6418; + assign n7042 = n7036 | n7037 | n7038 | n7039; + assign n7043 = (n_n9021 & n4961) | (n_n7692 & n4960); + assign n7044 = (n_n7697 & n4958) | (n_n9618 & n4959_1); + assign n7045 = n6453 | n6454 | n6455 | n6456; + assign n7046 = n6457 | n6458 | n6459 | n6460; + assign n7047 = n6461 | n6462 | n6463 | n6464; + assign n7048 = n7047 | n6451 | n6452; + assign n7049 = n7043 | n7044 | n7045 | n7046; + assign n7050 = (n_n8966 & n4963) | (n_n7952 & n4964_1); + assign n7051 = n6438 | n6437 | (n_n8854 & n4962); + assign n7052 = n6439 | n6440 | n6441 | n6442; + assign n7053 = n6443 | n6444 | n6445 | n6446; + assign n7054 = n6447 | n6448 | n6449 | n6450; + assign n7055 = n7054 | n6435 | n6436; + assign n7056 = n7050 | n7051 | n7052 | n7053; + assign n7057 = (n_n7762 & n4961) | (n_n7709 & n4960); + assign n7058 = (n_n8852 & n4959_1) | (n_n8986 & n4958); + assign n7059 = n6375 | n6376 | n6377 | n6378; + assign n7060 = n6379 | n6380 | n6381 | n6382; + assign n7061 = n6383 | n6384 | n6385 | n6386; + assign n7062 = n7061 | n6373 | n6374; + assign n7063 = n7057 | n7058 | n7059 | n7060; + assign n7064 = (n_n7763 & n4964_1) | (n_n7759 & n4963); + assign n7065 = n6360 | n6359 | (n_n7760 & n4962); + assign n7066 = n6361 | n6362 | n6363 | n6364; + assign n7067 = n6365 | n6366 | n6367 | n6368; + assign n7068 = n6369 | n6370 | n6371 | n6372; + assign n7069 = n7068 | n6357 | n6358; + assign n7070 = n7064 | n7065 | n7066 | n7067; + assign n7071 = (n_n8408 & n4963) | (n_n7811 & n4964_1); + assign n7072 = n6325 | n6324 | (n_n7809 & n4962); + assign n7073 = n6326 | n6327 | n6328 | n6329; + assign n7074 = n6330 | n6331 | n6332 | n6333; + assign n7075 = n6334 | n6335 | n6336 | n6337; + assign n7076 = n7075 | n6322 | n6323; + assign n7077 = n7071 | n7072 | n7073 | n7074; + assign n7078 = (n_n8088 & n4960) | (n_n7810 & n4961); + assign n7079 = (n_n8108 & n4958) | (n_n8473 & n4959_1); + assign n7080 = n6340 | n6341 | n6342 | n6343; + assign n7081 = n6344 | n6345 | n6346 | n6347; + assign n7082 = n6348 | n6349 | n6350 | n6351; + assign n7083 = n7082 | n6338 | n6339; + assign n7084 = n7078 | n7079 | n7080 | n7081; + assign n7085 = n_n9248 & ~n_n7306; + assign n7086 = (nsr3_38 & nen3_36) | (nsr3_23 & ndn3_19); + assign n7087 = (nsr3_37 & nen3_34) | (nsr3_30 & ndn3_26); + assign n7088 = (ndn3_29 & nsr3_35) | (ndn3_17 & nsr3_20); + assign n7089 = n4974_1 & n_n9198; + assign n7090 = n6305 | n6303 | n6304; + assign n7091 = n6306 | n6307 | n6308 | n6309; + assign n7092 = n6298 | n6296 | n6297; + assign n7093 = n6299 | n6300 | n6301 | n6302; + assign n7094 = n6284 | n6282 | n6283; + assign n7095 = n6285 | n6286 | n6287 | n6288; + assign n7096 = n6263 | n6261 | n6262; + assign n7097 = n6264 | n6265 | n6266 | n6267; + assign n7098 = n6256 | n6254 | n6255; + assign n7099 = n6257 | n6258 | n6259 | n6260; + assign n7100 = n6235 | n6233 | n6234; + assign n7101 = n6236 | n6237 | n6238 | n6239; + assign n7102 = n6242 | n6240 | n6241; + assign n7103 = n6243 | n6244 | n6245 | n6246; + assign n7104 = n6228 | n6226 | n6227; + assign n7105 = n6229 | n6230 | n6231 | n6232; + assign n7106 = n6249 | n6247 | n6248; + assign n7107 = n6250 | n6251 | n6252 | n6253; + assign n7108 = n6270 | n6268 | n6269; + assign n7109 = n6271 | n6272 | n6273 | n6274; + assign n7110 = n6277 | n6275 | n6276; + assign n7111 = n6278 | n6279 | n6280 | n6281; + assign n7112 = n6221 | n6219 | n6220; + assign n7113 = n6222 | n6223 | n6224 | n6225; + assign n7114 = n6291 | n6289 | n6290; + assign n7115 = n6292 | n6293 | n6294 | n6295; + assign n7116 = n6214 | n6212 | n6213; + assign n7117 = n6215 | n6216 | n6217 | n6218; + assign n7118 = n6207 | n6205 | n6206; + assign n7119 = n6208 | n6209 | n6210 | n6211; + assign n7120 = n6201 | n6202 | n6203 | n6204; + assign n7121 = n5001 & ~n_n8557 & n4856; + assign n7122 = n4856 & n_n8557; + assign n7123 = n_n9638 & n4856 & (n7094 | n7095); + assign n7124 = (n_n9225 & n4960) | (n_n7888 & n4961); + assign n7125 = (n_n7887 & n4959_1) | (n_n7850 & n4958); + assign n7126 = n6165 | n6166 | n6167 | n6168; + assign n7127 = n6169 | n6170 | n6171 | n6172; + assign n7128 = n6173 | n6174 | n6175 | n6176; + assign n7129 = n7128 | n6163 | n6164; + assign n7130 = n7124 | n7125 | n7126 | n7127; + assign n7131 = (n_n7886 & n4963) | (n_n7889 & n4964_1); + assign n7132 = n6150 | n6149 | (n_n9520 & n4962); + assign n7133 = n6151 | n6152 | n6153 | n6154; + assign n7134 = n6155 | n6156 | n6157 | n6158; + assign n7135 = n6159 | n6160 | n6161 | n6162; + assign n7136 = n7135 | n6147 | n6148; + assign n7137 = n7131 | n7132 | n7133 | n7134; + assign n7138 = (n_n8519 & n4964_1) | (n_n8002 & n4963); + assign n7139 = n6132 | n6131 | (n_n8004 & n4962); + assign n7140 = n6133 | n6134 | n6135 | n6136; + assign n7141 = n6137 | n6138 | n6139 | n6140; + assign n7142 = n6141 | n6142 | n6143 | n6144; + assign n7143 = n7142 | n6129 | n6130; + assign n7144 = n7138 | n7139 | n7140 | n7141; + assign n7145 = (n_n8005 & n4961) | (n_n9223 & n4960); + assign n7146 = (n_n8003 & n4959_1) | (n_n8482 & n4958); + assign n7147 = n6117 | n6118 | n6119 | n6120; + assign n7148 = n6121 | n6122 | n6123 | n6124; + assign n7149 = n6125 | n6126 | n6127 | n6128; + assign n7150 = n7149 | n6115 | n6116; + assign n7151 = n7145 | n7146 | n7147 | n7148; + assign n7152 = (n_n8139 & n4960) | (n_n7933 & n4961); + assign n7153 = (n_n8000 & n4958) | (n_n7931 & n4959_1); + assign n7154 = n6087 | n6088 | n6089_1 | n6090; + assign n7155 = n6091 | n6092 | n6093 | n6094_1; + assign n7156 = n6095 | n6096 | n6097 | n6098; + assign n7157 = n7156 | n6085 | n6086; + assign n7158 = n7152 | n7153 | n7154 | n7155; + assign n7159 = (n_n8106 & n4964_1) | (n_n7930 & n4963); + assign n7160 = n6102 | n6101 | (n_n7932 & n4962); + assign n7161 = n6103 | n6104 | n6105 | n6106; + assign n7162 = n6107 | n6108 | n6109 | n6110; + assign n7163 = n6111 | n6112 | n6113 | n6114; + assign n7164 = n7163 | n6099 | n6100; + assign n7165 = n7159 | n7160 | n7161 | n7162; + assign n7166 = ~n_n8869 & ~n_n8603 & ~n_n8798; + assign n7167 = ~n4924_1 & n4953 & (n_n8933 ^ n5000); + assign n7168 = n7166 & (n_n8911 ^ (n_n8933 | n5000)); + assign n7169 = ~n4927 & n7167; + assign n7170 = ~n4928 & n7168 & (~n_n8993 ^ ~n5005); + assign n7171 = ~n4943 & n7169 & (~n_n8561 ^ ~n4999_1); + assign n7172 = ~n4947 & n7171; + assign n7173 = ~n4899_1 & n7170 & (~n_n8913 ^ ~n4968); + assign n7174 = preset | ~n_n9198 | ~n4967 | ~n4974_1; + assign n7175 = n_n9434 & n4856 & (n7096 | n7097); + assign n7176 = ~n4967 & ~preset; + assign n7177 = pdn | preset | (nsr3_23 & ~nak3_13); + assign n7178 = pdn | preset | (nsr3_13 & ~nak3_13); + assign n7179 = pdn | preset | (nsr3_38 & ~nak3_13); + assign n7180 = n_n8549 & n4856 & (n7090 | n7091); + assign n7181 = n4856 & (n_n8652 ? ~n4910 : (n4910 & n5001)); + assign n7182 = ~n_n8707 & (n4911 ^ (n7104 | n7105)); + assign n7183 = n_n8707 & n4856 & (~n4911 ^ n4913); + assign n7184 = n7183 | (n4856 & n5001 & n7182); + assign n7185 = pdn | preset | (nsr3_30 & ~ndn3_26); + assign n7186 = n_n8354 & n4856 & (n7116 | n7117); + assign n7187 = n_n9512 & n4856 & (n7098 | n7099); + assign n7188 = n5001 & n4856 & n4920; + assign n7189 = n4856 & n_n9512; + assign n7190 = n5626 | (~preset & n_n9512 & ~n5001); + assign n7191 = pdn | preset | (nsr3_35 & ~nak3_13); + assign n7192 = n_n9416 & n4856 & (n7108 | n7109); + assign n7193 = pdn | (~nak3_13 & (preset | nsr3_14)); + assign n7194 = ~n_n8603 & ~n5975 & (~n4975 | ~n7176); + assign n7195 = ~n6866 & ~n_n8603 & ~n6865; + assign n7196 = ~n4856 & n_n8603; + assign n7197 = ~n4898 & (n7194 | n7195); + assign n7198 = n4974_1 & n4967 & ~preset & n_n9198; + assign n7199 = n_n8449 & n4856 & (n7092 | n7093); + assign n7200 = n_n9448 & n4856 & (n7114 | n7115); + assign n7201 = n_n9537 & n4856 & (n7110 | n7111); + assign n7202 = n_n8929 & ~preset; + assign n7203 = ~preset & (n6897 | n6898); + assign n7204 = ~n_n9284 & (n4909_1 ^ (n7102 | n7103)); + assign n7205 = n_n9284 & n4856 & (~n4909_1 ^ n4936); + assign n7206 = n7205 | (n4856 & n5001 & n7204); + assign n7207 = n_n8821 & n4856 & (n7112 | n7113); + assign n7208 = ~n_n9353 & (n4912 ^ (n7106 | n7107)); + assign n7209 = n_n9353 & n4856 & (~n4912 ^ n4938); + assign n7210 = pdn | preset | (nsr3_37 & ~nen3_34); + assign n7211 = pdn | preset | (~nak3_13 & nsr3_20); + assign n7212 = n_n8419 & n4856 & (n7118 | n7119); + always @ (posedge clock) begin + n_n9280 <= n491; + n_n9172 <= n496; + n_n9260 <= n501; + n_n7726 <= n506; + n_n8270 <= n511; + n_n8196 <= n516; + n_n9150 <= n521; + n_n9267 <= n526; + n_n7779 <= n531; + n_n9503 <= n536; + n_n8150 <= n541; + n_n9401 <= n546; + n_n7341 <= n551; + n_n9180 <= n556; + n_n8592 <= n561; + n_n8871 <= n566; + n_n7252 <= n571; + n_n7271 <= n576; + n_n6991 <= n581; + n_n8557 <= n586; + n_n7707 <= n591; + n_n7552 <= n596; + ndn3_23 <= n601; + n_n9548 <= n606; + n_n9467 <= n611; + n_n8002 <= n616; + n_n6950 <= n621; + n_n8930 <= n626; + n_n7244 <= n631; + n_n7819 <= n636; + n_n8883 <= n641; + n_n7709 <= n646; + n_n9580 <= n651; + n_n9130 <= n656; + n_n9486 <= n661; + n_n9235 <= n666; + n_n7522 <= n671; + n_n7373 <= n676; + n_n9085 <= n681; + n_n9638 <= n686; + n_n7452 <= n691; + n_n8775 <= n696; + n_n7654 <= n701; + n_n8410 <= n706; + n_n8208 <= n711; + n_n8377 <= n716; + n_n7558 <= n721; + n_n7599 <= n726; + n_n8225 <= n731; + n_n8202 <= n736; + n_n7670 <= n741; + n_n7888 <= n746; + n_n7889 <= n751; + n_n8597 <= n756; + n_n8152 <= n761; + n_n8394 <= n766; + n_n7812 <= n771; + n_n7816 <= n776; + n_n9141 <= n781; + n_n7332 <= n786; + n_n8758 <= n791; + n_n7765 <= n796; + n_n7877 <= n801; + n_n7814 <= n806; + n_n9008 <= n811; + n_n7581 <= n816; + n_n7376 <= n821; + n_n7970 <= n826; + pover_0_0_ <= n831; + n_n8599 <= n835; + n_n8227 <= n840; + n_n9442 <= n845; + n_n9485 <= n850; + n_n7148 <= n855; + n_n9311 <= n860; + n_n9273 <= n865; + ndn3_9 <= n870; + n_n8613 <= n875; + n_n8533 <= n880; + n_n8699 <= n885; + n_n8609 <= n890; + n_n8308 <= n895; + n_n8655 <= n900; + n_n8981 <= n905; + n_n7583 <= n910; + n_n9198 <= n915; + n_n9602 <= n920; + n_n8786 <= n925; + n_n9598 <= n930; + n_n7738 <= n935; + n_n8573 <= n940; + n_n9473 <= n945; + n_n9000 <= n950; + n_n8001 <= n955; + n_n9554 <= n960; + n_n8508 <= n965; + n_n9635 <= n970; + n_n7190 <= n975; + n_n8702 <= n980; + n_n9106 <= n985; + n_n7409 <= n990; + n_n9437 <= n995; + n_n9052 <= n1000; + n_n8647 <= n1005; + n_n9265 <= n1010; + n_n7179 <= n1015; + ndn3_13 <= n1020; + ndn3_17 <= n1025; + ndn3_25 <= n1030; + ndn3_29 <= n1035; + n_n9539 <= n1040; + n_n7953 <= n1045; + n_n8488 <= n1050; + nen3_22 <= n1055; + n_n9438 <= n1060; + n_n8132 <= n1065; + n_n8661 <= n1070; + n_n7759 <= n1075; + n_n8333 <= n1080; + n_n9399 <= n1085; + n_n7798 <= n1090; + n_n9434 <= n1095; + n_n7910 <= n1100; + n_n9528 <= n1105; + n_n7850 <= n1110; + n_n8251 <= n1115; + n_n7937 <= n1120; + n_n8482 <= n1125; + n_n9290 <= n1130; + n_n8007 <= n1135; + n_n7556 <= n1140; + n_n9064 <= n1145; + n_n9398 <= n1150; + n_n9412 <= n1155; + n_n9361 <= n1160; + n_n9304 <= n1165; + n_n7651 <= n1170; + n_n7712 <= n1175; + n_n7735 <= n1180; + n_n7934 <= n1185; + n_n7811 <= n1190; + n_n8053 <= n1195; + n_n9015 <= n1200; + n_n8066 <= n1205; + n_n9518 <= n1210; + n_n8091 <= n1215; + n_n9257 <= n1220; + n_n8175 <= n1225; + n_n8491 <= n1230; + n_n8114 <= n1235; + n_n7951 <= n1240; + n_n8913 <= n1245; + n_n8035 <= n1250; + n_n8631 <= n1255; + n_n8243 <= n1260; + n_n7857 <= n1265; + ngfdn_3 <= n1270; + n_n7791 <= n1275; + n_n9175 <= n1280; + n_n9588 <= n1285; + n_n9049 <= n1290; + n_n9483 <= n1295; + n_n9410 <= n1300; + n_n7691 <= n1305; + n_n7740 <= n1310; + n_n7602 <= n1315; + n_n7783 <= n1320; + n_n7948 <= n1325; + n_n7054 <= n1330; + n_n9343 <= n1335; + n_n9400 <= n1340; + nsr1_2 <= n1345; + n_n9127 <= n1350; + n_n8531 <= n1355; + n_n9335 <= n1360; + n_n7324 <= n1365; + n_n9611 <= n1370; + n_n8112 <= n1375; + n_n9406 <= n1380; + n_n9618 <= n1385; + n_n9613 <= n1390; + n_n9242 <= n1395; + n_n7384 <= n1400; + n_n8884 <= n1405; + n_n7462 <= n1410; + n_n7908 <= n1415; + n_n8765 <= n1420; + n_n7909 <= n1425; + n_n7898 <= n1430; + n_n9135 <= n1435; + n_n8862 <= n1440; + n_n8037 <= n1445; + ndn3_18 <= n1450; + ndn3_22 <= n1455; + n_n8974 <= n1460; + n_n7286 <= n1465; + n_n9223 <= n1470; + n_n7306 <= n1475; + n_n9169 <= n1480; + n_n9125 <= n1485; + nen3_39 <= n1490; + n_n8278 <= n1495; + n_n9557 <= n1500; + n_n7758 <= n1505; + n_n9391 <= n1510; + n_n8110 <= n1515; + n_n9597 <= n1520; + n_n8568 <= n1525; + n_n7428 <= n1530; + n_n7931 <= n1535; + n_n7742 <= n1540; + n_n7236 <= n1545; + n_n8219 <= n1550; + n_n9568 <= n1555; + n_n9200 <= n1560; + n_n8545 <= n1565; + n_n7823 <= n1570; + n_n8005 <= n1575; + n_n8736 <= n1580; + n_n9339 <= n1585; + n_n8499 <= n1590; + n_n8086 <= n1595; + n_n7803 <= n1600; + n_n7640 <= n1605; + n_n9098 <= n1610; + n_n7160 <= n1615; + n_n7713 <= n1620; + n_n9566 <= n1625; + n_n7955 <= n1630; + n_n8414 <= n1635; + n_n8006 <= n1640; + n_n9560 <= n1645; + n_n8742 <= n1650; + n_n7174 <= n1655; + n_n8882 <= n1660; + n_n7546 <= n1665; + n_n8282 <= n1670; + n_n8998 <= n1675; + n_n7656 <= n1680; + n_n9465 <= n1685; + n_n9601 <= n1690; + n_n8875 <= n1695; + n_n7954 <= n1700; + n_n8959 <= n1705; + n_n8957 <= n1710; + n_n8247 <= n1715; + n_n8258 <= n1720; + n_n7641 <= n1725; + n_n8843 <= n1730; + n_n9321 <= n1735; + n_n7702 <= n1740; + nsr3_23 <= n1745; + n_n8199 <= n1750; + n_n7983 <= n1755; + n_n7217 <= n1760; + n_n7821 <= n1765; + n_n9489 <= n1770; + n_n8348 <= n1775; + n_n9408 <= n1780; + n_n8445 <= n1785; + n_n9501 <= n1790; + n_n7831 <= n1795; + n_n7757 <= n1800; + n_n9174 <= n1805; + n_n9432 <= n1810; + n_n8678 <= n1815; + n_n8024 <= n1820; + n_n7806 <= n1825; + n_n8996 <= n1830; + n_n7918 <= n1835; + n_n8260 <= n1840; + n_n9341 <= n1845; + n_n9189 <= n1850; + n_n9096 <= n1855; + ndn3_30 <= n1860; + n_n7775 <= n1865; + n_n7693 <= n1870; + nen3_16 <= n1875; + n_n7643 <= n1880; + n_n8941 <= n1885; + n_n8042 <= n1890; + n_n8681 <= n1895; + n_n8659 <= n1900; + n_n9110 <= n1905; + n_n9573 <= n1910; + n_n8951 <= n1915; + n_n9589 <= n1920; + n_n9387 <= n1925; + n_n8279 <= n1930; + n_n7790 <= n1935; + n_n8406 <= n1940; + n_n8582 <= n1945; + n_n7911 <= n1950; + n_n7474 <= n1955; + n_n8466 <= n1960; + n_n6984 <= n1965; + n_n7760 <= n1970; + n_n7847 <= n1975; + n_n9559 <= n1980; + n_n7362 <= n1985; + n_n9300 <= n1990; + n_n9550 <= n1995; + n_n9492 <= n2000; + n_n8777 <= n2005; + n_n7764 <= n2010; + n_n7826 <= n2015; + n_n7777 <= n2020; + n_n7824 <= n2025; + n_n8173 <= n2030; + n_n7498 <= n2035; + n_n9148 <= n2040; + n_n8753 <= n2045; + n_n8772 <= n2050; + n_n8049 <= n2055; + n_n9362 <= n2060; + ndn1_4 <= n2065; + n_n9561 <= n2070; + n_n9004 <= n2075; + n_n8203 <= n2080; + n_n8153 <= n2085; + n_n9263 <= n2090; + n_n8369 <= n2095; + n_n9331 <= n2100; + n_n7454 <= n2105; + ndn3_7 <= n2110; + n_n7527 <= n2115; + n_n9036 <= n2120; + n_n7875 <= n2125; + n_n8697 <= n2130; + n_n9497 <= n2135; + n_n7291 <= n2140; + nsr3_13 <= n2145; + nsr3_38 <= n2150; + n_n8240 <= n2155; + n_n7703 <= n2160; + n_n9282 <= n2165; + n_n8237 <= n2170; + n_n8935 <= n2175; + n_n9244 <= n2180; + n_n8648 <= n2185; + n_n8235 <= n2190; + n_n8611 <= n2195; + n_n9045 <= n2200; + n_n9334 <= n2205; + n_n8572 <= n2210; + n_n9491 <= n2215; + n_n9134 <= n2220; + n_n9555 <= n2225; + n_n9336 <= n2230; + n_n7050 <= n2235; + n_n9346 <= n2240; + n_n7140 <= n2245; + n_n7681 <= n2250; + n_n6948 <= n2255; + n_n8549 <= n2260; + ndn3_19 <= n2265; + ndn3_28 <= n2270; + n_n7102 <= n2275; + n_n8093 <= n2280; + n_n9041 <= n2285; + n_n8381 <= n2290; + n_n8810 <= n2295; + nen3_36 <= n2300; + n_n9047 <= n2305; + n_n9333 <= n2310; + n_n7736 <= n2315; + n_n7820 <= n2320; + n_n8986 <= n2325; + n_n8891 <= n2330; + n_n8000 <= n2335; + n_n7968 <= n2340; + n_n8750 <= n2345; + n_n9558 <= n2350; + n_n9368 <= n2355; + n_n8519 <= n2360; + n_n6956 <= n2365; + n_n8298 <= n2370; + n_n9397 <= n2375; + n_n7017 <= n2380; + n_n8638 <= n2385; + n_n9552 <= n2390; + n_n8964 <= n2395; + n_n8016 <= n2400; + n_n7603 <= n2405; + n_n7696 <= n2410; + n_n8589 <= n2415; + n_n9337 <= n2420; + n_n9132 <= n2425; + n_n8652 <= n2430; + n_n8707 <= n2435; + n_n9407 <= n2440; + n_n9044 <= n2445; + n_n8808 <= n2450; + nsr3_30 <= n2455; + n_n8274 <= n2460; + n_n8615 <= n2465; + n_n8238 <= n2470; + n_n7854 <= n2475; + n_n8649 <= n2480; + n_n8236 <= n2485; + n_n8269 <= n2490; + n_n9592 <= n2495; + n_n8022 <= n2500; + n_n8744 <= n2505; + n_n8529 <= n2510; + n_n7967 <= n2515; + n_n9487 <= n2520; + n_n8685 <= n2525; + n_n9531 <= n2530; + n_n9510 <= n2535; + n_n7771 <= n2540; + n_n8480 <= n2545; + n_n8543 <= n2550; + n_n7789 <= n2555; + ndn3_11 <= n2560; + ndn3_15 <= n2565; + ndn3_21 <= n2570; + n_n7584 <= n2575; + n_n8354 <= n2580; + n_n6952 <= n2585; + n_n8864 <= n2590; + n_n7930 <= n2595; + n_n7962 <= n2600; + n_n7929 <= n2605; + n_n9316 <= n2610; + n_n9102 <= n2615; + n_n7308 <= n2620; + n_n7657 <= n2625; + n_n9264 <= n2630; + n_n8760 <= n2635; + n_n6912 <= n2640; + n_n7887 <= n2645; + n_n8911 <= n2650; + n_n7952 <= n2655; + n_n8704 <= n2660; + n_n7876 <= n2665; + n_n9596 <= n2670; + n_n8430 <= n2675; + n_n9019 <= n2680; + n_n7699 <= n2685; + n_n7375 <= n2690; + n_n7936 <= n2695; + n_n8340 <= n2700; + n_n8809 <= n2705; + n_n6961 <= n2710; + n_n9429 <= n2715; + n_n7743 <= n2720; + n_n8980 <= n2725; + n_n7582 <= n2730; + n_n8968 <= n2735; + n_n9371 <= n2740; + n_n8741 <= n2745; + n_n9502 <= n2750; + n_n9373 <= n2755; + n_n9248 <= n2760; + n_n7822 <= n2765; + n_n9054 <= n2770; + n_n8273 <= n2775; + n_n6937 <= n2780; + n_n9342 <= n2785; + n_n9325 <= n2790; + n_n9609 <= n2795; + n_n9623 <= n2800; + n_n9470 <= n2805; + n_n7570 <= n2810; + n_n9310 <= n2815; + n_n9366 <= n2820; + n_n7181 <= n2825; + n_n8739 <= n2830; + n_n8939 <= n2835; + n_n7256 <= n2840; + n_n8983 <= n2845; + n_n7487 <= n2850; + n_n9268 <= n2855; + n_n8906 <= n2860; + n_n7988 <= n2865; + n_n9181 <= n2870; + n_n8725 <= n2875; + n_n8626 <= n2880; + ndn3_27 <= n2885; + n_n8210 <= n2890; + n_n7415 <= n2895; + n_n8900 <= n2900; + nen3_19 <= n2905; + n_n8762 <= n2910; + n_n8512 <= n2915; + n_n8095 <= n2920; + n_n8982 <= n2925; + n_n7387 <= n2930; + n_n9494 <= n2935; + n_n7689 <= n2940; + n_n7835 <= n2945; + n_n9157 <= n2950; + n_n8552 <= n2955; + n_n7381 <= n2960; + n_n9446 <= n2965; + n_n8633 <= n2970; + n_n7684 <= n2975; + n_n7310 <= n2980; + n_n8402 <= n2985; + n_n9315 <= n2990; + n_n7950 <= n2995; + n_n8504 <= n3000; + n_n8456 <= n3005; + n_n7514 <= n3010; + n_n7315 <= n3015; + n_n9476 <= n3020; + n_n8276 <= n3025; + n_n8833 <= n3030; + n_n7923 <= n3035; + n_n9395 <= n3040; + n_n9512 <= n3045; + n_n9319 <= n3050; + nsr3_35 <= n3055; + n_n7154 <= n3060; + n_n9495 <= n3065; + n_n9137 <= n3070; + n_n8854 <= n3075; + n_n9183 <= n3080; + n_n9323 <= n3085; + n_n9349 <= n3090; + n_n7896 <= n3095; + n_n8073 <= n3100; + n_n8970 <= n3105; + n_n9314 <= n3110; + n_n8486 <= n3115; + n_n7246 <= n3120; + n_n7866 <= n3125; + n_n9599 <= n3130; + n_n7635 <= n3135; + n_n8984 <= n3140; + n_n7360 <= n3145; + n_n8794 <= n3150; + n_n9108 <= n3155; + n_n9286 <= n3160; + ndn3_12 <= n3165; + ndn3_16 <= n3170; + n_n7708 <= n3175; + n_n7807 <= n3180; + n_n7650 <= n3185; + n_n7947 <= n3190; + n_n9500 <= n3195; + n_n7734 <= n3200; + n_n8464 <= n3205; + n_n7659 <= n3210; + n_n7630 <= n3215; + n_n7756 <= n3220; + n_n8691 <= n3225; + n_n9176 <= n3230; + n_n9327 <= n3235; + n_n7995 <= n3240; + n_n7395 <= n3245; + n_n7878 <= n3250; + n_n7507 <= n3255; + n_n7959 <= n3260; + n_n7825 <= n3265; + n_n8009 <= n3270; + n_n8281 <= n3275; + n_n7685 <= n3280; + n_n8106 <= n3285; + n_n7687 <= n3290; + n_n7766 <= n3295; + n_n7880 <= n3300; + n_n8961 <= n3305; + n_n8014 <= n3310; + n_n9278 <= n3315; + n_n9087 <= n3320; + n_n9182 <= n3325; + n_n7852 <= n3330; + n_n9324 <= n3335; + nak3_13 <= n3340; + n_n9416 <= n3345; + nsr3_14 <= n3350; + n_n8603 <= n3355; + n_n7026 <= n3360; + n_n8856 <= n3365; + n_n8272 <= n3370; + n_n9312 <= n3375; + n_n7985 <= n3380; + n_n8312 <= n3385; + n_n7231 <= n3390; + n_n9396 <= n3395; + n_n8801 <= n3400; + n_n8683 <= n3405; + ndn3_39 <= n3410; + n_n8245 <= n3415; + n_n9458 <= n3420; + n_n9302 <= n3425; + n_n7392 <= n3430; + n_n6963 <= n3435; + n_n7808 <= n3440; + n_n7225 <= n3445; + n_n7817 <= n3450; + n_n8201 <= n3455; + n_n7793 <= n3460; + n_n8177 <= n3465; + n_n8389 <= n3470; + n_n9440 <= n3475; + n_n7683 <= n3480; + n_n7761 <= n3485; + n_n7667 <= n3490; + n_n7980 <= n3495; + n_n7509 <= n3500; + n_n7813 <= n3505; + n_n8396 <= n3510; + n_n9535 <= n3515; + n_n7209 <= n3520; + n_n7003 <= n3525; + n_n7695 <= n3530; + n_n7624 <= n3535; + n_n8791 <= n3540; + n_n7374 <= n3545; + n_n7429 <= n3550; + n_n7944 <= n3555; + n_n9266 <= n3560; + n_n8100 <= n3565; + n_n6988 <= n3570; + n_n6986 <= n3575; + n_n8933 <= n3580; + n_n7117 <= n3585; + n_n9043 <= n3590; + n_n8241 <= n3595; + n_n9219 <= n3600; + n_n8198 <= n3605; + n_n8081 <= n3610; + n_n8575 <= n3615; + n_n8710 <= n3620; + n_n7622 <= n3625; + n_n7966 <= n3630; + n_n7885 <= n3635; + n_n7033 <= n3640; + ndn3_34 <= n3645; + n_n9186 <= n3650; + ndn3_50 <= n3655; + n_n7879 <= n3660; + n_n7019 <= n3665; + n_n9171 <= n3670; + n_n7261 <= n3675; + n_n8223 <= n3680; + n_n8989 <= n3685; + n_n7993 <= n3690; + n_n7845 <= n3695; + n_n8253 <= n3700; + n_n8889 <= n3705; + n_n7809 <= n3710; + n_n8918 <= n3715; + n_n8515 <= n3720; + n_n7933 <= n3725; + n_n8075 <= n3730; + n_n7338 <= n3735; + n_n8104 <= n3740; + n_n8171 <= n3745; + n_n9059 <= n3750; + n_n9023 <= n3755; + n_n7692 <= n3760; + n_n9441 <= n3765; + n_n6920 <= n3770; + n_n8831 <= n3775; + n_n8441 <= n3780; + n_n9576 <= n3785; + n_n9252 <= n3790; + n_n9363 <= n3795; + ndn3_4 <= n3800; + n_n9247 <= n3805; + n_n7561 <= n3810; + n_n8923 <= n3815; + n_n7978 <= n3820; + n_n8978 <= n3825; + n_n9499 <= n3830; + n_n8713 <= n3835; + n_n8944 <= n3840; + n_n8239 <= n3845; + n_n7652 <= n3850; + n_n9042 <= n3855; + n_n8530 <= n3860; + n_n9271 <= n3865; + n_n9318 <= n3870; + n_n7706 <= n3875; + n_n7964 <= n3880; + n_n8222 <= n3885; + n_n8898 <= n3890; + n_n7976 <= n3895; + n_n7649 <= n3900; + n_n7604 <= n3905; + n_n7961 <= n3910; + n_n7424 <= n3915; + n_n7476 <= n3920; + n_n9259 <= n3925; + n_n9309 <= n3930; + n_n9161 <= n3935; + n_n8436 <= n3940; + n_n9121 <= n3945; + n_n8061 <= n3950; + n_n8004 <= n3955; + n_n9360 <= n3960; + n_n9205 <= n3965; + n_n8392 <= n3970; + n_n9034 <= n3975; + n_n8375 <= n3980; + n_n8328 <= n3985; + n_n9298 <= n3990; + n_n7598 <= n3995; + n_n8506 <= n4000; + pdn <= n4005; + n_n7737 <= n4009; + n_n7420 <= n4014; + n_n9291 <= n4019; + n_n7946 <= n4024; + n_n8584 <= n4029; + n_n9308 <= n4034; + n_n9403 <= n4039; + n_n7284 <= n4044; + n_n9270 <= n4049; + n_n7390 <= n4054; + n_n9351 <= n4059; + n_n6968 <= n4064; + n_n8668 <= n4069; + n_n9605 <= n4074; + n_n7013 <= n4079; + n_n9626 <= n4084; + n_n8200 <= n4089; + n_n9028 <= n4094; + n_n8803 <= n4099; + n_n9570 <= n4104; + n_n8366 <= n4109; + n_n9050 <= n4114; + n_n8650 <= n4119; + n_n8574 <= n4124; + n_n7276 <= n4129; + n_n9212 <= n4134; + n_n8384 <= n4139; + ndn3_35 <= n4144; + n_n8449 <= n4149; + ndn3_46 <= n4154; + n_n7554 <= n4159; + n_n8743 <= n4164; + n_n8277 <= n4169; + n_n9359 <= n4174; + n_n8425 <= n4179; + n_n9104 <= n4184; + n_n9221 <= n4189; + n_n9448 <= n4194; + n_n9537 <= n4199; + n_n8003 <= n4204; + n_n7467 <= n4209; + n_n8233 <= n4214; + n_n7932 <= n4219; + n_n8064 <= n4224; + n_n9162 <= n4229; + n_n7971 <= n4234; + n_n8055 <= n4239; + n_n7711 <= n4244; + n_n8256 <= n4249; + n_n7925 <= n4254; + n_n7762 <= n4259; + n_n7668 <= n4264; + n_n7914 <= n4269; + n_n7873 <= n4274; + n_n7849 <= n4279; + n_n9421 <= n4284; + n_n7626 <= n4289; + n_n7848 <= n4294; + n_n8263 <= n4299; + n_n9100 <= n4304; + n_n9393 <= n4309; + n_n9591 <= n4314; + n_n7588 <= n4319; + n_n9123 <= n4324; + n_n9159 <= n4329; + n_n9128 <= n4334; + n_n8045 <= n4339; + n_n7728 <= n4344; + n_n8929 <= n4349; + n_n7739 <= n4354; + n_n9355 <= n4359; + n_n9394 <= n4364; + n_n8470 <= n4369; + n_n8571 <= n4374; + n_n8796 <= n4379; + ndn3_36 <= n4384; + n_n7990 <= n4389; + n_n8781 <= n4394; + n_n8817 <= n4399; + n_n9160 <= n4404; + n_n9092 <= n4409; + n_n8513 <= n4414; + n_n8213 <= n4419; + n_n8581 <= n4424; + n_n9284 <= n4429; + n_n7837 <= n4434; + n_n8224 <= n4439; + n_n9203 <= n4444; + n_n7655 <= n4449; + n_n8946 <= n4454; + n_n7052 <= n4459; + n_n9615 <= n4464; + n_n8473 <= n4469; + n_n7741 <= n4474; + n_n9460 <= n4479; + n_n7912 <= n4484; + n_n7606 <= n4489; + n_n9021 <= n4494; + n_n7781 <= n4499; + n_n7810 <= n4504; + n_n7108 <= n4509; + n_n7697 <= n4514; + n_n7642 <= n4519; + n_n9595 <= n4524; + n_n7694 <= n4529; + n_n8221 <= n4534; + n_n7600 <= n4539; + n_n7935 <= n4544; + n_n9230 <= n4549; + n_n7701 <= n4554; + n_n7510 <= n4559; + n_n7627 <= n4564; + n_n8502 <= n4569; + n_n8516 <= n4574; + n_n7913 <= n4579; + n_n9320 <= n4584; + n_n7411 <= n4589; + n_n9129 <= n4594; + n_n9053 <= n4599; + n_n7069 <= n4604; + n_n8617 <= n4609; + n_n7242 <= n4614; + n_n8230 <= n4619; + n_n9294 <= n4624; + n_n8249 <= n4629; + n_n8972 <= n4634; + n_n7074 <= n4639; + n_n7493 <= n4644; + n_n8290 <= n4649; + n_n8821 <= n4654; + n_n7769 <= n4659; + n_n7491 <= n4664; + n_n9600 <= n4669; + n_n9317 <= n4674; + n_n8047 <= n4679; + n_n9629 <= n4684; + n_n9126 <= n4689; + n_n9508 <= n4694; + n_n9155 <= n4699; + n_n8528 <= n4704; + ndn3_37 <= n4709; + ndn3_42 <= n4714; + n_n9358 <= n4719; + n_n8185 <= n4724; + nen3_28 <= n4729; + n_n8839 <= n4734; + n_n7903 <= n4739; + n_n9139 <= n4744; + n_n9075 <= n4749; + n_n9439 <= n4754; + n_n9353 <= n4759; + n_n7665 <= n4764; + n_n8798 <= n4769; + n_n7146 <= n4774; + n_n7890 <= n4779; + n_n7176 <= n4784; + n_n8477 <= n4789; + n_n8514 <= n4794; + n_n8636 <= n4799; + n_n7183 <= n4804; + n_n8657 <= n4809; + n_n9493 <= n4814; + n_n7969 <= n4819; + n_n9255 <= n4824; + n_n8535 <= n4829; + n_n8619 <= n4834; + n_n8909 <= n4839; + n_n7744 <= n4844; + n_n9119 <= n4849; + n_n7827 <= n4854; + n_n8916 <= n4859; + n_n8729 <= n4864; + n_n9011 <= n4869; + n_n8779 <= n4874; + n_n6980 <= n4879; + n_n7715 <= n4884; + n_n9067 <= n4889; + n_n9164 <= n4894; + n_n7402 <= n4899; + n_n8938 <= n4904; + n_n9046 <= n4909; + n_n8789 <= n4914; + n_n9390 <= n4919; + n_n7768 <= n4924; + n_n9136 <= n4929; + n_n8670 <= n4934; + n_n8644 <= n4939; + n_n9178 <= n4944; + n_n8188 <= n4949; + n_n7083 <= n4954; + n_n9344 <= n4959; + n_n7366 <= n4964; + n_n8361 <= n4969; + n_n9228 <= n4974; + n_n9402 <= n4979; + n_n8510 <= n4984; + n_n8881 <= n4989; + n_n9404 <= n4994; + n_n9424 <= n4999; + n_n9031 <= n5004; + nsr3_37 <= n5009; + n_n8197 <= n5014; + n_n8468 <= n5019; + n_n7121 <= n5024; + n_n7511 <= n5029; + ndn3_44 <= n5034; + n_n9322 <= n5039; + n_n7682 <= n5044; + n_n9603 <= n5049; + nlc1_2 <= n5054; + n_n8408 <= n5059; + n_n8577 <= n5064; + n_n7079 <= n5069; + n_n8828 <= n5074; + n_n9340 <= n5079; + n_n8586 <= n5084; + n_n7901 <= n5089; + n_n8628 <= n5094; + n_n8869 <= n5099; + n_n7710 <= n5104; + n_n8993 <= n5109; + n_n9586 <= n5114; + n_n8852 <= n5119; + n_n8583 <= n5124; + n_n8011 <= n5129; + n_n7717 <= n5134; + n_n8326 <= n5139; + n_n9163 <= n5144; + n_n8344 <= n5149; + n_n8296 <= n5154; + n_n8116 <= n5159; + n_n8267 <= n5164; + n_n7686 <= n5169; + n_n9061 <= n5174; + n_n9338 <= n5179; + n_n7688 <= n5184; + n_n9081 <= n5189; + n_n6910 <= n5194; + n_n8727 <= n5199; + n_n7674 <= n5204; + n_n7330 <= n5209; + n_n8966 <= n5214; + n_n7843 <= n5219; + n_n8847 <= n5224; + n_n9376 <= n5229; + n_n7553 <= n5234; + n_n9292 <= n5239; + n_n7464 <= n5244; + n_n8146 <= n5249; + n_n8439 <= n5254; + n_n9498 <= n5259; + n_n8118 <= n5264; + n_n9452 <= n5269; + n_n9239 <= n5274; + n_n9237 <= n5279; + n_n9488 <= n5284; + ndn3_2 <= n5289; + n_n9522 <= n5294; + n_n9313 <= n5299; + n_n7435 <= n5304; + n_n8665 <= n5309; + n_n9593 <= n5314; + n_n8303 <= n5319; + n_n7022 <= n5324; + n_n9173 <= n5329; + n_n9261 <= n5334; + n_n7150 <= n5339; + n_n9455 <= n5344; + n_n8371 <= n5349; + nsr3_20 <= n5354; + n_n8271 <= n5359; + n_n9542 <= n5364; + n_n7444 <= n5369; + ndn3_40 <= n5374; + n_n7130 <= n5379; + n_n9347 <= n5384; + n_n8102 <= n5389; + n_n9225 <= n5394; + n_n8462 <= n5399; + n_n8088 <= n5404; + n_n9026 <= n5409; + n_n9289 <= n5414; + n_n7661 <= n5419; + n_n8108 <= n5424; + n_n8921 <= n5429; + n_n7859 <= n5434; + n_n7732 <= n5439; + n_n7956 <= n5444; + n_n9520 <= n5449; + n_n7666 <= n5454; + n_n7678 <= n5459; + n_n7846 <= n5464; + n_n8280 <= n5469; + n_n8841 <= n5474; + n_n7336 <= n5479; + n_n8226 <= n5484; + n_n8151 <= n5489; + n_n7644 <= n5494; + n_n8770 <= n5499; + n_n8423 <= n5504; + n_n7763 <= n5509; + n_n9525 <= n5514; + n_n8033 <= n5519; + n_n7881 <= n5524; + n_n7815 <= n5529; + n_n9232 <= n5534; + n_n7792 <= n5539; + n_n9563 <= n5544; + n_n8672 <= n5549; + n_n7346 <= n5554; + n_n7949 <= n5559; + n_n8756 <= n5564; + n_n8641 <= n5569; + n_n8192 <= n5574; + n_n8058 <= n5579; + n_n8561 <= n5584; + n_n9306 <= n5589; + n_n9165 <= n5594; + n_n8850 <= n5599; + n_n9210 <= n5604; + ndn2_2 <= n5609; + n_n7342 <= n5614; + n_n8051 <= n5619; + n_n7136 <= n5624; + n_n9348 <= n5629; + n_n9006 <= n5634; + n_n7653 <= n5639; + n_n7905 <= n5644; + n_n9166 <= n5649; + n_n7065 <= n5654; + n_n9490 <= n5659; + n_n7024 <= n5664; + n_n7586 <= n5669; + n_n8416 <= n5674; + n_n8937 <= n5679; + n_n8141 <= n5684; + n_n7853 <= n5689; + n_n8121 <= n5694; + n_n9604 <= n5699; + n_n9496 <= n5704; + n_n8195 <= n5709; + n_n9516 <= n5714; + n_n9077 <= n5719; + n_n9436 <= n5724; + n_n9051 <= n5729; + n_n7664 <= n5734; + n_n8419 <= n5739; + n_n7874 <= n5744; + n_n9133 <= n5749; + n_n9392 <= n5754; + n_n7770 <= n5759; + ndn3_32 <= n5764; + n_n7601 <= n5769; + n_n8206 <= n5774; + n_n7927 <= n5779; + n_n9606 <= n5784; + n_n7111 <= n5789; + n_n9269 <= n5794; + ndn3_38 <= n5799; + n_n7886 <= n5804; + n_n9179 <= n5809; + n_n9357 <= n5814; + n_n9594 <= n5819; + n_n7628 <= n5824; + n_n8454 <= n5829; + ndn3_20 <= n5834; + n_n9505 <= n5839; + nen3_34 <= n5844; + n_n9632 <= n5849; + n_n7076 <= n5854; + n_n9262 <= n5859; + n_n9048 <= n5864; + n_n9578 <= n5869; + n_n8135 <= n5874; + ndn3_26 <= n5879; + n_n7500 <= n5884; + n_n6974 <= n5889; + n_n8605 <= n5894; + n_n9296 <= n5899; + n_n7156 <= n5904; + n_n7920 <= n5909; + n_n8895 <= n5914; + n_n8991 <= n5919; + n_n8139 <= n5924; + n_n9275 <= n5929; + n_n7203 <= n5934; + n_n9590 <= n5939; + n_n7344 <= n5944; + n_n6976 <= n5949; + n_n7629 <= n5954; + ndn3_14 <= n5959; + n_n7862 <= n5964; + n_n9013 <= n5969; + n_n7288 <= n5974; + n_n8078 <= n5979; + n_n7334 <= n5984; + n_n7704 <= n5989; + n_n7788 <= n5994; + n_n8526 <= n5999; + n_n9556 <= n6004; + n_n9345 <= n6009; + n_n8447 <= n6014; + n_n7485 <= n6019; + n_n8570 <= n6024; + n_n7453 <= n6029; + n_n7928 <= n6034; + n_n8646 <= n6039; + n_n9405 <= n6044; + n_n8948 <= n6049; + n_n9131 <= n6054; + n_n8216 <= n6059; + n_n9177 <= n6064; + n_n7844 <= n6069; + n_n8811 <= n6074; + n_n9145 <= n6079; + n_n8428 <= n6084; + n_n8858 <= n6089; + n_n8580 <= n6094; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/ex1010/ex1010.v b/openfpga_flow/benchmarks/MCNC_Verilog/ex1010/ex1010.v new file mode 100644 index 000000000..47c44a6c9 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/ex1010/ex1010.v @@ -0,0 +1,930 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:22 2019 + +module ex1010 ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_; + wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, + n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, + n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, + n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, + n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, + n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, + n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, + n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, + n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, + n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, + n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, + n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, + n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, + n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, + n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, + n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, + n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, + n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, + n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, + n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, + n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, + n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, + n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, + n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, + n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, + n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, + n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, + n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, + n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, + n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, + n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, + n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, + n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, + n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, + n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, + n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, + n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, + n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, + n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, + n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, + n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, + n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, + n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, + n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, + n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, + n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, + n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, + n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, + n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, + n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, + n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, + n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, + n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, + n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, + n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, + n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, + n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, + n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, + n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, + n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, + n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, + n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, + n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, + n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, + n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, + n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, + n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, + n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, + n868, n869; + assign o_0_ = ~n418; + assign o_1_ = ~n31; + assign o_2_ = ~n403; + assign o_3_ = ~n378; + assign o_4_ = ~n349; + assign o_5_ = ~n30; + assign o_6_ = ~n270; + assign o_7_ = ~n216; + assign o_8_ = ~n170; + assign o_9_ = ~n109; + assign n30 = n155 & n50 & n301 & n302 & n303 & n304 & n305 & n306; + assign n31 = n97 & n404 & n151 & n405 & n406 & n407 & n408 & n409; + assign n32 = (n436 | n458) & (n219 | n479); + assign n33 = ~i_9_ | n429; + assign n34 = n423 | n446; + assign n35 = n32 & (n33 | n34); + assign n36 = (n222 | n481) & (n43 | n480); + assign n37 = ~i_9_ | n419; + assign n38 = n423 | n457; + assign n39 = n36 & (n37 | n38); + assign n40 = i_9_ | n440; + assign n41 = n420 | n441; + assign n42 = n419 | n450; + assign n43 = i_9_ | n421; + assign n44 = (n42 | n43) & (n40 | n41); + assign n45 = n219 | n103; + assign n46 = n439 | n290; + assign n47 = n565 & n320 & n566; + assign n48 = n563 & n564 & (n272 | n476); + assign n49 = n561 & n562 & n125 & n556 & n560 & n557; + assign n50 = n45 & n46 & n44 & n35 & n39 & n47 & n48 & n49; + assign n51 = n40 | n456; + assign n52 = n436 | n203; + assign n53 = ~i_9_ | n427; + assign n54 = n426 | n446; + assign n55 = n51 & n52 & (n53 | n54); + assign n56 = n37 | n262; + assign n57 = n272 | n487; + assign n58 = n319 & (n219 | n488); + assign n59 = n555 & n55 & (n91 | n489); + assign n60 = n53 | n92; + assign n61 = n219 | n485; + assign n62 = n33 | n486; + assign n63 = n388 & n554 & (n53 | n483); + assign n64 = n56 & n57 & n58 & n59 & n60 & n61 & n62 & n63; + assign n65 = n552 & (n37 | n490); + assign n66 = n436 | n491; + assign n67 = (n33 | n469) & (n96 | n43); + assign n68 = n219 | n339; + assign n69 = (n37 | n478) & (n439 | n494); + assign n70 = n553 & n328 & (n309 | n481); + assign n71 = n65 & n66 & n67 & n68 & n69 & n70; + assign n72 = n91 | n496; + assign n73 = n100 | n41; + assign n74 = (n309 | n463) & (n222 | n495); + assign n75 = (n222 | n463) & (n43 | n255); + assign n76 = (n422 | n462) & (n43 | n223); + assign n77 = n72 & n73 & n74 & n75 & n76; + assign n78 = n219 | n498; + assign n79 = n436 | n480; + assign n80 = (n436 | n447) & (n222 | n497); + assign n81 = (n86 | n475) & (n258 | n499); + assign n82 = (n309 | n480) & (n40 | n493); + assign n83 = n78 & n79 & n80 & n81 & n82; + assign n84 = (n443 | n86) & (n462 | n502); + assign n85 = n225 & n551 & (n258 | n500); + assign n86 = i_9_ | n460; + assign n87 = n433 | n466; + assign n88 = n84 & n85 & (n86 | n87); + assign n89 = (n222 | n203) & (n33 | n150); + assign n90 = n549 & n550 & (n219 | n199); + assign n91 = ~i_9_ | n466; + assign n92 = n435 | n442; + assign n93 = n89 & n90 & (n91 | n92); + assign n94 = n462 | n507; + assign n95 = n548 & n124 & (n100 | n506); + assign n96 = n441 | n442; + assign n97 = n94 & n95 & (n96 | n86); + assign n98 = (n219 | n92) & (n53 | n469); + assign n99 = n431 | n432; + assign n100 = i_9_ | n457; + assign n101 = n98 & (n99 | n100); + assign n102 = (n100 | n508) & (n33 | n489); + assign n103 = n423 | n460; + assign n104 = n102 & (n37 | n103); + assign n105 = (n86 | n465) & (n464 | n219); + assign n106 = n64 & n71 & n50 & n83 & n88 & n77; + assign n107 = n589 & n593 & n592 & n586 & n585 & n588; + assign n108 = n580 & n584 & n583 & n579 & n577 & n575; + assign n109 = n97 & n101 & n93 & n105 & n104 & n106 & n107 & n108; + assign n110 = n623 & (n100 | n514); + assign n111 = n37 | n507; + assign n112 = n86 | (n468 & n492); + assign n113 = n622 & (n462 | n498); + assign n114 = n620 & n621 & (n43 | n310); + assign n115 = n619 & n285 & n561 & n209 & n56 & n618 & n299 & n616; + assign n116 = n110 & n111 & n112 & n113 & n114 & n115; + assign n117 = (n37 | n471) & (n33 | n520); + assign n118 = n53 | n34; + assign n119 = (n91 | n523) & (n462 | n488); + assign n120 = n609 & n608 & (n100 | n475); + assign n121 = n312 & n613 & (n309 | n458); + assign n122 = n611 & n610 & (n447 | n43); + assign n123 = n117 & n118 & n119 & n120 & n121 & n122; + assign n124 = n462 | n505; + assign n125 = n43 | n468; + assign n126 = n73 & (n222 | n518); + assign n127 = (n86 | n525) & (n272 | n465); + assign n128 = n606 & (n309 | n524); + assign n129 = n603 & (n462 | n526); + assign n130 = n601 & n602 & (n439 | n498); + assign n131 = n605 & n604 & (n37 | n461); + assign n132 = n124 & n125 & n126 & n127 & n128 & n129 & n130 & n131; + assign n133 = (n272 | n495) & (n91 | n103); + assign n134 = n454 | n100; + assign n135 = n600 & (n309 | n484); + assign n136 = n462 | n477; + assign n137 = n598 & n599 & (n219 | n500); + assign n138 = n596 & n597 & (n222 | n42); + assign n139 = n133 & n134 & n135 & n136 & n137 & n138; + assign n140 = (n91 | n511) & (n272 | n528); + assign n141 = n594 & n595 & (n91 | n34); + assign n142 = n420 | n432; + assign n143 = n140 & n141 & (n86 | n142); + assign n144 = (n272 | n529) & (n258 | n503); + assign n145 = n86 | n530; + assign n146 = (n53 | n103) & (n424 | n462); + assign n147 = n144 & n145 & n146 & n61; + assign n148 = (n309 | n531) & (n436 | n456); + assign n149 = (n86 | n532) & (n100 | n472); + assign n150 = n421 | n442; + assign n151 = n148 & n149 & (n91 | n150); + assign n152 = (n40 & n436) | n533; + assign n153 = n380 & (n53 | n496); + assign n154 = n423 | n435; + assign n155 = n152 & n153 & (n91 | n154); + assign n156 = (n100 | n531) & (n91 | n534); + assign n157 = n426 | n466; + assign n158 = n156 & (n86 | n157); + assign n159 = (n33 | n505) & (n91 | n38); + assign n160 = n433 | n460; + assign n161 = n159 & (n33 | n160); + assign n162 = (n436 | n513) & (n33 | n92); + assign n163 = (n53 | n509) & (n222 | n512); + assign n164 = (n222 | n513) & (n37 | n467); + assign n165 = (n258 | n467) & (n43 | n501); + assign n166 = n626 & n625 & (n309 | n42); + assign n167 = n633 & n634 & n631 & n630 & n629 & n387 & n628 & n627; + assign n168 = n139 & n143 & n147 & n151 & n123 & n132 & n116 & n644; + assign n169 = n640 & n641 & n639 & n638 & n637 & n642 & n636 & n635; + assign n170 = n162 & n163 & n164 & n165 & n166 & n167 & n168 & n169; + assign n171 = (n37 | n92) & (n43 | n484); + assign n172 = n648 & n649 & (n458 | n86); + assign n173 = n647 & (n100 | n294); + assign n174 = n645 & n646 & (n219 | n540); + assign n175 = n171 & n172 & n173 & n174; + assign n176 = n33 | n477; + assign n177 = n272 | n255; + assign n178 = (n91 | n538) & (n452 | n43); + assign n179 = n91 | n504; + assign n180 = (n100 | n492) & (n258 | n504); + assign n181 = n559 & (n53 | n290); + assign n182 = n176 & n177 & n178 & n179 & n180 & n181; + assign n183 = n428 | n100; + assign n184 = n219 | n34; + assign n185 = (n436 | n472) & (n43 | n474); + assign n186 = n40 | n542; + assign n187 = (n91 | n339) & (n445 | n219); + assign n188 = (n40 | n525) & (n219 | n505); + assign n189 = n183 & n184 & n185 & n186 & n187 & n188; + assign n190 = n436 | n525; + assign n191 = n86 | n512; + assign n192 = (n86 | n480) & (n436 | n544); + assign n193 = n53 | n486; + assign n194 = n309 | n543; + assign n195 = (n258 | n251) & (n222 | n294); + assign n196 = n190 & n191 & n192 & n193 & n194 & n195; + assign n197 = (n96 | n100) & (n272 | n532); + assign n198 = n350 & n351 & (n40 | n513); + assign n199 = n450 | n457; + assign n200 = n197 & n198 & (n53 | n199); + assign n201 = (n462 | n496) & (n37 | n522); + assign n202 = (n309 | n517) & (n439 | n539); + assign n203 = n423 | n432; + assign n204 = n201 & n202 & (n86 | n203); + assign n205 = (n222 | n142) & (n272 | n521); + assign n206 = (n439 | n496) & (n33 | n470); + assign n207 = n205 & n206; + assign n208 = (n86 | n519) & (n100 | n537); + assign n209 = n53 | n150; + assign n210 = n674 & n673 & (n272 | n514); + assign n211 = n566 & n563 & n234 & n605 & n672 & n671; + assign n212 = n64 & n139 & (n461 | n91); + assign n213 = n676 & n675 & (n53 | n539); + assign n214 = n196 & n200 & n204 & n207 & n182 & n189 & n175; + assign n215 = n670 & n227 & n668 & n667 & n663 & n662 & n666 & n661; + assign n216 = n208 & n209 & n210 & n211 & n212 & n213 & n214 & n215; + assign n217 = n258 | n92; + assign n218 = (n309 | n542) & (n40 | n518); + assign n219 = ~i_9_ | n451; + assign n220 = n217 & n218 & (n219 | n38); + assign n221 = (n86 | n513) & (n462 | n545); + assign n222 = i_9_ | n425; + assign n223 = n442 | n466; + assign n224 = n221 & (n222 | n223); + assign n225 = n272 | n501; + assign n226 = n438 | n439; + assign n227 = n456 | n100; + assign n228 = n45 & n72 & (n43 | n525); + assign n229 = n686 & n685 & (n309 | n294); + assign n230 = n276 & n652 & n684 & n277; + assign n231 = n224 & n158 & n220 & n44 & n404 & n693 & n692 & n690; + assign n232 = n225 & n226 & n227 & n176 & n228 & n229 & n230 & n231; + assign n233 = n434 | n33; + assign n234 = n462 | n478; + assign n235 = n674 & (n40 | n536); + assign n236 = (n258 | n527) & (n222 | n510); + assign n237 = n33 | n523; + assign n238 = (n40 | n519) & (n37 | n259); + assign n239 = n439 | (n339 & n516); + assign n240 = n682 & n683 & (n100 | n541); + assign n241 = n233 & n234 & n235 & n236 & n237 & n238 & n239 & n240; + assign n242 = (n53 | n534) & (n462 | n54); + assign n243 = n96 | n272; + assign n244 = n681 & (n86 | n501); + assign n245 = n43 | n491; + assign n246 = n46 & n615 & (n91 | n479); + assign n247 = n679 & n680 & (n436 | n508); + assign n248 = n242 & n243 & n244 & n245 & n246 & n247; + assign n249 = n392 & (n40 | n492); + assign n250 = n678 & n677 & (n33 | n546); + assign n251 = n442 | n446; + assign n252 = n249 & n250 & (n53 | n251); + assign n253 = n272 | n536; + assign n254 = (n258 | n540) & (n86 | n515); + assign n255 = n431 | n441; + assign n256 = n253 & n254 & (n40 | n255); + assign n257 = (n91 | n520) & (n456 | n43); + assign n258 = ~i_9_ | n441; + assign n259 = n420 | n440; + assign n260 = n257 & (n258 | n259); + assign n261 = (n222 | n468) & (n258 | n339); + assign n262 = n420 | n449; + assign n263 = n261 & (n53 | n262); + assign n264 = (n37 | n290) & (n454 | n86); + assign n265 = (n219 | n511) & (n33 | n494); + assign n266 = n710 & n709 & (n309 | n506); + assign n267 = n713 & n712 & (n33 | n479); + assign n268 = n252 & n256 & n260 & n263 & n241 & n248 & n232 & n717; + assign n269 = n700 & n177 & n699 & n698 & n695 & n694 & n697 & n708; + assign n270 = n264 & n265 & n266 & n267 & n268 & n269; + assign n271 = (n100 | n535) & (n439 | n251); + assign n272 = i_9_ | n449; + assign n273 = n271 & (n272 | n42); + assign n274 = n91 | n546; + assign n275 = n439 | n546; + assign n276 = n436 | n476; + assign n277 = n219 | n150; + assign n278 = n253 & n719 & (n309 | n528); + assign n279 = n714 & (n91 | n526); + assign n280 = n321 & (n37 | n438); + assign n281 = n721 & n720 & (n86 | n41); + assign n282 = n274 & n275 & n276 & n277 & n278 & n279 & n280 & n281; + assign n283 = n219 | n478; + assign n284 = n428 | n436; + assign n285 = n100 | n521; + assign n286 = n665 & (n455 | n219); + assign n287 = n161 & n283 & n263 & n284 & n285 & n286; + assign n288 = (n40 | n497) & (n37 | n539); + assign n289 = n718 & (n219 | n486); + assign n290 = n453 | n460; + assign n291 = n288 & n289 & (n290 | n91); + assign n292 = n43 | (n476 & n506); + assign n293 = n686 & (n53 | n473); + assign n294 = n423 | n466; + assign n295 = n292 & n293 & (n272 | n294); + assign n296 = n219 | n469; + assign n297 = n100 | n533; + assign n298 = (n272 | n543) & (n462 | n486); + assign n299 = n455 | n53; + assign n300 = n296 & n297 & n298 & n299; + assign n301 = (n436 | n529) & (n219 | n547); + assign n302 = n749 & n748 & (n91 | n516); + assign n303 = n282 & n287 & n291 & n295 & n300 & n252 & n224 & n196; + assign n304 = n747 & n746 & n745 & n744 & n743 & n742 & n741 & n740; + assign n305 = n738 & n739 & n730 & n732 & n731 & n737 & n736 & n735; + assign n306 = n729 & n728 & n727 & n726 & n725 & n724 & n723 & n722; + assign n307 = n678 & (n219 | n490); + assign n308 = (n219 | n507) & (n459 | n462); + assign n309 = i_9_ | n446; + assign n310 = n419 | n433; + assign n311 = n307 & n308 & (n309 | n310); + assign n312 = n53 | n503; + assign n313 = n710 & n632 & (n309 | n501); + assign n314 = n753 & n590 & n190 & n78 & n79 & n51; + assign n315 = n469 | n91; + assign n316 = n669 & n649 & (n37 | n477); + assign n317 = n751 & n752 & (n439 | n92); + assign n318 = n311 & n312 & n313 & n314 & n315 & n234 & n316 & n317; + assign n319 = n447 | n100; + assign n320 = n219 | n477; + assign n321 = n219 | n154; + assign n322 = (n439 | n461) & (n100 | n530); + assign n323 = n222 | n472; + assign n324 = n654 & (n91 | n259); + assign n325 = (n222 | n537) & (n37 | n482); + assign n326 = n750 & n738 & (n272 | n484); + assign n327 = n319 & n320 & n321 & n322 & n323 & n324 & n325 & n326; + assign n328 = n436 | n492; + assign n329 = n53 | n489; + assign n330 = n452 | n100; + assign n331 = (n465 | n43) & (n272 | n512); + assign n332 = (n439 | n538) & (n37 | n527); + assign n333 = n462 | n538; + assign n334 = (n462 | n520) & (n424 | n219); + assign n335 = n258 | n490; + assign n336 = n328 & n329 & n330 & n331 & n332 & n333 & n334 & n335; + assign n337 = n53 | n520; + assign n338 = n43 | n203; + assign n339 = n420 | n425; + assign n340 = n337 & n338 & (n53 | n339); + assign n341 = n759 & n758 & (n462 | n527); + assign n342 = n602 & n757 & (n258 | n479); + assign n343 = n614 & n756 & (n43 | n497); + assign n344 = n755 & n754 & (n43 | n294); + assign n345 = n599 & n274 & n761 & n763 & n762 & n765 & n764 & n766; + assign n346 = n773 & n621 & n772 & n771; + assign n347 = n769 & n770 & n552 & n562 & n768 & n767; + assign n348 = n340 & n300 & n248 & n220 & n327 & n336 & n318 & n777; + assign n349 = n341 & n342 & n343 & n344 & n345 & n346 & n347 & n348; + assign n350 = n99 | n272; + assign n351 = n462 | n103; + assign n352 = n340 & (n459 | n219); + assign n353 = (n436 | n468) & (n33 | n467); + assign n354 = n94 & n582 & (n43 | n541); + assign n355 = n315 & n782 & (n258 | n511); + assign n356 = n739 & n780 & (n222 | n491); + assign n357 = n297 & n350 & n351 & n352 & n353 & n354 & n355 & n356; + assign n358 = (n436 | n532) & (n91 | n470); + assign n359 = n40 | n528; + assign n360 = (n43 | n515) & (n424 | n53); + assign n361 = n222 | n536; + assign n362 = n779 & n676 & (n100 | n142); + assign n363 = n778 & n760 & (n91 | n477); + assign n364 = n358 & n359 & n360 & n361 & n362 & n363; + assign n365 = (n222 | n524) & (n436 | n537); + assign n366 = n100 | n532; + assign n367 = (n91 | n498) & (n40 | n541); + assign n368 = (n33 | n154) & (n222 | n541); + assign n369 = n53 | n502; + assign n370 = n569 & (n436 | n157); + assign n371 = n365 & n366 & n367 & n368 & n369 & n370; + assign n372 = n801 & n800 & (n455 | n462); + assign n373 = n798 & n797 & (n272 | n530); + assign n374 = n364 & n371 & n357 & n804 & n88 & n55 & n116 & n803; + assign n375 = n795 & n794 & (n290 | n219); + assign n376 = n792 & n791 & (n100 | n493); + assign n377 = n788 & n789 & n787 & n786 & n785 & n217 & n784 & n783; + assign n378 = n372 & n373 & n374 & n375 & n376 & n377; + assign n379 = n462 | (n444 & n534); + assign n380 = n258 | n507; + assign n381 = n808 & (n53 | n471); + assign n382 = n809 & n810 & (n100 | n501); + assign n383 = n806 & n807 & (n53 | n461); + assign n384 = n759 & n805 & (n40 | n484); + assign n385 = n379 & n380 & n381 & n382 & n383 & n384; + assign n386 = n86 | n514; + assign n387 = n219 | n496; + assign n388 = n91 | n482; + assign n389 = n101 & (n272 | n519); + assign n390 = n40 | n514; + assign n391 = n37 | n154; + assign n392 = n430 | n100; + assign n393 = n596 & n597 & (n439 | n520); + assign n394 = n386 & n387 & n388 & n389 & n390 & n391 & n392 & n393; + assign n395 = (n222 | n447) & (n37 | n339); + assign n396 = n43 | (n454 & n510); + assign n397 = n811 & (n37 | n434); + assign n398 = n813 & (n462 | n546); + assign n399 = n812 & (n53 | n498); + assign n400 = n817 & n818 & (n439 | n103); + assign n401 = n816 & n815 & (n272 | n508); + assign n402 = n182 & n143 & n260 & n827 & n93 & n828 & n826 & n822; + assign n403 = n395 & n396 & n397 & n398 & n399 & n400 & n401 & n402; + assign n404 = n33 | n534; + assign n405 = (n37 | n502) & (n86 | n524); + assign n406 = (n100 | n518) & (n222 | n454); + assign n407 = n318 & n287 & n256 & n200 & n394 & n364 & n273; + assign n408 = n111 & n606 & n808 & n849 & n848 & n847 & n846 & n845; + assign n409 = n843 & n564 & n842 & n840 & n832 & n831 & n830 & n836; + assign n410 = (n86 | n533) & (n439 | n199); + assign n411 = n438 | n91; + assign n412 = n858 & n555 & (n43 | n533); + assign n413 = n721 & n857 & (n100 | n517); + assign n414 = n781 & n856 & (n462 | n499); + assign n415 = n855 & n854 & (n309 | n468); + assign n416 = n852 & n851 & (n33 | n444); + assign n417 = n132 & n83 & n175 & n868 & n867 & n869 & n866 & n862; + assign n418 = n410 & n411 & n412 & n413 & n414 & n415 & n416 & n417; + assign n419 = i_8_ | i_6_ | ~i_7_; + assign n420 = ~i_5_ | ~i_3_ | i_4_; + assign n421 = ~i_0_ | ~i_1_ | ~i_2_; + assign n422 = n420 | n421; + assign n423 = i_5_ | i_3_ | ~i_4_; + assign n424 = n421 | n423; + assign n425 = ~i_0_ | ~i_1_ | i_2_; + assign n426 = ~i_3_ | ~i_4_ | i_5_; + assign n427 = ~i_6_ | ~i_7_ | i_8_; + assign n428 = n426 | n427; + assign n429 = ~i_6_ | ~i_7_ | ~i_8_; + assign n430 = n420 | n429; + assign n431 = ~i_5_ | i_3_ | i_4_; + assign n432 = i_8_ | i_6_ | i_7_; + assign n433 = i_5_ | i_3_ | i_4_; + assign n434 = n425 | n433; + assign n435 = ~i_2_ | ~i_0_ | i_1_; + assign n436 = i_9_ | n435; + assign n437 = i_8_ | ~i_6_ | i_7_; + assign n438 = n433 | n435; + assign n439 = ~i_9_ | n437; + assign n440 = i_2_ | ~i_0_ | i_1_; + assign n441 = ~i_8_ | ~i_6_ | i_7_; + assign n442 = ~i_3_ | ~i_4_ | ~i_5_; + assign n443 = n419 | n442; + assign n444 = n431 | n440; + assign n445 = n433 | n440; + assign n446 = ~i_2_ | i_0_ | ~i_1_; + assign n447 = n419 | n420; + assign n448 = n431 | n437; + assign n449 = i_2_ | i_0_ | ~i_1_; + assign n450 = i_5_ | ~i_3_ | i_4_; + assign n451 = ~i_8_ | i_6_ | ~i_7_; + assign n452 = n450 | n451; + assign n453 = ~i_5_ | i_3_ | ~i_4_; + assign n454 = n429 | n453; + assign n455 = n423 | n449; + assign n456 = n423 | n441; + assign n457 = ~i_2_ | i_0_ | i_1_; + assign n458 = n429 | n431; + assign n459 = n433 | n457; + assign n460 = i_2_ | i_0_ | i_1_; + assign n461 = n450 | n460; + assign n462 = ~i_9_ | n432; + assign n463 = n423 | n429; + assign n464 = n431 | n460; + assign n465 = n427 | n433; + assign n466 = ~i_8_ | i_6_ | i_7_; + assign n467 = n421 | n450; + assign n468 = n423 | n437; + assign n469 = n421 | n431; + assign n470 = n425 | n426; + assign n471 = n425 | n453; + assign n472 = n433 | n441; + assign n473 = n426 | n440; + assign n474 = n453 | n466; + assign n475 = n423 | n451; + assign n476 = n432 | n450; + assign n477 = n426 | n457; + assign n478 = n420 | n460; + assign n479 = n420 | n435; + assign n480 = n432 | n453; + assign n481 = n426 | n429; + assign n482 = n421 | n426; + assign n483 = n421 | n453; + assign n484 = n427 | n453; + assign n485 = n425 | n431; + assign n486 = n431 | n446; + assign n487 = n420 | n427; + assign n488 = n431 | n449; + assign n489 = n453 | n457; + assign n490 = n425 | n450; + assign n491 = n420 | n466; + assign n492 = n429 | n450; + assign n493 = n441 | n453; + assign n494 = n442 | n449; + assign n495 = n429 | n433; + assign n496 = n426 | n460; + assign n497 = n431 | n466; + assign n498 = n431 | n435; + assign n499 = n449 | n453; + assign n500 = n440 | n450; + assign n501 = n442 | n451; + assign n502 = n431 | n457; + assign n503 = n423 | n440; + assign n504 = n426 | n449; + assign n505 = n435 | n453; + assign n506 = n420 | n437; + assign n507 = n442 | n460; + assign n508 = n419 | n423; + assign n509 = n423 | n425; + assign n510 = n437 | n453; + assign n511 = n420 | n457; + assign n512 = n441 | n450; + assign n513 = n419 | n426; + assign n514 = n432 | n433; + assign n515 = n433 | n451; + assign n516 = n435 | n450; + assign n517 = n426 | n451; + assign n518 = n433 | n437; + assign n519 = n451 | n453; + assign n520 = n421 | n433; + assign n521 = n437 | n442; + assign n522 = n426 | n435; + assign n523 = n442 | n457; + assign n524 = n429 | n442; + assign n525 = n427 | n442; + assign n526 = n420 | n446; + assign n527 = n440 | n442; + assign n528 = n431 | n451; + assign n529 = n426 | n441; + assign n530 = n420 | n451; + assign n531 = n437 | n450; + assign n532 = n427 | n431; + assign n533 = n427 | n450; + assign n534 = n433 | n446; + assign n535 = n419 | n453; + assign n536 = n432 | n442; + assign n537 = n423 | n427; + assign n538 = n446 | n453; + assign n539 = n449 | n450; + assign n540 = n433 | n449; + assign n541 = n426 | n432; + assign n542 = n419 | n431; + assign n543 = n426 | n437; + assign n544 = n450 | n466; + assign n545 = n446 | n450; + assign n546 = n440 | n453; + assign n547 = n425 | n442; + assign n548 = n462 | n259; + assign n549 = n439 | n504; + assign n550 = n91 | n503; + assign n551 = (n222 | n493) & (n424 | n33); + assign n552 = n53 | n479; + assign n553 = n436 | n493; + assign n554 = (n222 | n484) & (n33 | n339); + assign n555 = n456 | n86; + assign n556 = n315 & n338 & (n462 | n470); + assign n557 = n323 & n411 & (n33 | n471); + assign n558 = n40 | n157; + assign n559 = n91 | n473; + assign n560 = n558 & n559 & (n309 | n474); + assign n561 = n53 | n467; + assign n562 = n157 | n43; + assign n563 = n309 | n475; + assign n564 = n272 | n203; + assign n565 = n428 | n86; + assign n566 = n33 | n478; + assign n567 = (n219 | n467) & (n422 | n37); + assign n568 = (n37 | n424) & (n91 | n483); + assign n569 = n222 | n430; + assign n570 = n569 & (n428 | n222); + assign n571 = (n222 | n99) & (n258 | n485); + assign n572 = (n436 | n510) & (n434 | n439); + assign n573 = n99 | n436; + assign n574 = n33 | n509; + assign n575 = n572 & n573 & n571 & n233 & n570 & n574 & n568 & n567; + assign n576 = n96 | n40; + assign n577 = n576 & n226 & (n40 | n443); + assign n578 = (n33 | n445) & (n37 | n444); + assign n579 = n578 & (n439 | n54); + assign n580 = n309 | (n447 & n448); + assign n581 = n272 | n454; + assign n582 = n272 | n452; + assign n583 = n581 & n582 & (n272 | n493); + assign n584 = n443 | n272; + assign n585 = (n33 & n258) | n455; + assign n586 = (n33 | n511) & (n272 | n456); + assign n587 = n100 | n42; + assign n588 = n587 & n330 & (n100 | n203); + assign n589 = (n459 | n53) & (n100 | n458); + assign n590 = n463 | n86; + assign n591 = n290 | n462; + assign n592 = n590 & n591 & (n448 | n86); + assign n593 = n258 | n461; + assign n594 = n40 | n476; + assign n595 = n91 | n527; + assign n596 = n458 | n43; + assign n597 = n439 | n505; + assign n598 = n40 | n524; + assign n599 = n40 | n465; + assign n600 = n91 | n262; + assign n601 = n258 | n498; + assign n602 = n436 | n223; + assign n603 = n40 | n521; + assign n604 = (n258 | n477) & (n309 | n510); + assign n605 = n439 | n38; + assign n606 = n430 | n436; + assign n607 = n100 | n481; + assign n608 = n607 & (n100 | n484); + assign n609 = n100 | n463; + assign n610 = n549 & n584 & (n43 | n521); + assign n611 = n422 | n258; + assign n612 = n222 | n456; + assign n613 = n612 & (n439 | n485); + assign n614 = n219 | n520; + assign n615 = n436 | n518; + assign n616 = n614 & n615 & (n219 | n470); + assign n617 = n40 | n508; + assign n618 = n617 & (n219 | n503); + assign n619 = n86 | n472; + assign n620 = n222 | n443; + assign n621 = n462 | n339; + assign n622 = (n436 | n42) & (n439 | n522); + assign n623 = n219 | n259; + assign n624 = n40 | (n491 & n529); + assign n625 = n391 & n624 & (n436 | n514); + assign n626 = (n40 | n458) & (n33 | n500); + assign n627 = (n272 | n497) & (n258 | n262); + assign n628 = (n33 | n38) & (n272 | n87); + assign n629 = (n33 | n502) & (n100 | n468); + assign n630 = (n33 | n461) & (n91 | n478); + assign n631 = (n219 | n482) & (n86 | n294); + assign n632 = n462 | n467; + assign n633 = n632 & (n43 | n495); + assign n634 = n222 | n501; + assign n635 = (n436 | n443) & (n222 | n515); + assign n636 = (n37 | n479) & (n462 | n92); + assign n637 = (n40 | n517) & (n37 | n516); + assign n638 = n309 | (n491 & n497); + assign n639 = (n272 | n518) & (n37 | n499); + assign n640 = (n100 | n519) & (n219 | n489); + assign n641 = n100 | n87; + assign n642 = n91 | n251; + assign n643 = (n258 | n464) & (n86 | n535); + assign n644 = n158 & n161 & n155 & n71 & n35 & n643; + assign n645 = n436 | n454; + assign n646 = n43 | n87; + assign n647 = n272 | n310; + assign n648 = n86 | n541; + assign n649 = n439 | n502; + assign n650 = n43 | (n493 & n513); + assign n651 = (n258 | n520) & (n43 | n475); + assign n652 = n53 | n470; + assign n653 = n652 & (n439 | n470); + assign n654 = n222 | n532; + assign n655 = n654 & (n91 | n509); + assign n656 = (n434 | n91) & (n222 | n528); + assign n657 = (n436 | n536) & (n222 | n87); + assign n658 = n436 | n484; + assign n659 = n658 & (n462 | n516); + assign n660 = n462 | n154; + assign n661 = n659 & n660 & n657 & n656 & n655 & n653 & n651 & n650; + assign n662 = (n40 | n42) & (n436 | n465); + assign n663 = n40 | (n510 & n537); + assign n664 = (n37 | n445) & (n40 | n448); + assign n665 = n258 | n54; + assign n666 = n665 & n664 & (n309 | n536); + assign n667 = (n272 | n517) & (n37 | n34); + assign n668 = (n100 | n529) & (n53 | n523); + assign n669 = n462 | n199; + assign n670 = n669 & (n100 | n513); + assign n671 = (n37 | n503) & (n33 | n527); + assign n672 = (n219 | n538) & (n444 | n91); + assign n673 = (n272 | n524) & (n258 | n34); + assign n674 = n272 | n463; + assign n675 = (n219 | n526) & (n309 | n157); + assign n676 = n439 | n507; + assign n677 = (n439 | n479) & (n258 | n150); + assign n678 = n309 | n537; + assign n679 = n436 | n531; + assign n680 = n430 | n43; + assign n681 = n309 | n530; + assign n682 = n272 | n492; + assign n683 = n309 | n508; + assign n684 = n219 | n483; + assign n685 = (n33 | n545) & (n439 | n473); + assign n686 = n33 | n488; + assign n687 = n43 | n528; + assign n688 = n687 & (n33 | n490); + assign n689 = n53 | n494; + assign n690 = n689 & n688 & (n53 | n527); + assign n691 = n462 | n540; + assign n692 = n691 & n623 & (n272 | n535); + assign n693 = (n219 | n509) & (n37 | n523); + assign n694 = (n462 | n509) & (n43 | n518); + assign n695 = (n40 | n487) & (n53 | n505); + assign n696 = (n444 | n53) & (n40 | n544); + assign n697 = n390 & n696 & (n428 | n309); + assign n698 = (n37 | n538) & (n258 | n545); + assign n699 = n179 & (n91 | n494); + assign n700 = (n439 | n262) & (n272 | n41); + assign n701 = (n91 | n199) & (n258 | n523); + assign n702 = (n258 | n38) & (n100 | n476); + assign n703 = n619 & (n86 | n518); + assign n704 = (n222 | n448) & (n43 | n142); + assign n705 = (n436 | n530) & (n462 | n522); + assign n706 = (n436 | n515) & (n219 | n516); + assign n707 = n706 & (n436 | n310); + assign n708 = n550 & n60 & n703 & n702 & n701 & n705 & n704 & n707; + assign n709 = (n309 | n512) & (n53 | n545); + assign n710 = n40 | n515; + assign n711 = n351 & (n99 | n86); + assign n712 = n620 & n711 & (n43 | n543); + assign n713 = (n272 | n472) & (n91 | n54); + assign n714 = n309 | n535; + assign n715 = n714 & (n430 | n40); + assign n716 = (n219 | n494) & (n33 | n540); + assign n717 = n207 & n123 & n104 & n39 & n716 & n715; + assign n718 = (n40 | n506) & (n258 | n470); + assign n719 = (n272 | n542) & (n53 | n499); + assign n720 = (n436 | n517) & (n43 | n544); + assign n721 = n53 | n477; + assign n722 = (n53 | n482) & (n439 | n150); + assign n723 = (n439 | n483) & (n422 | n219); + assign n724 = (n43 | n508) & (n424 | n258); + assign n725 = (n33 & n258) | n547; + assign n726 = n222 | (n487 & n543); + assign n727 = (n33 | n516) & (n439 | n490); + assign n728 = n598 & (n436 | n528); + assign n729 = n595 & (n462 | n500); + assign n730 = (n40 | n535) & (n37 | n546); + assign n731 = n186 & (n309 | n142); + assign n732 = n309 | (n255 & n519); + assign n733 = (n430 | n272) & (n309 | n514); + assign n734 = n100 | n524; + assign n735 = n734 & n733 & (n272 | n475); + assign n736 = (n258 | n489) & (n100 | n536); + assign n737 = (n258 | n103) & (n462 | n38); + assign n738 = n444 | n219; + assign n739 = n462 | n503; + assign n740 = n386 & (n258 | n160); + assign n741 = (n422 | n33) & (n43 | n524); + assign n742 = (n222 | n521) & (n448 | n43); + assign n743 = n436 | (n495 & n512); + assign n744 = n681 & (n37 | n494); + assign n745 = (n219 | n523) & (n272 | n541); + assign n746 = (n37 | n496) & (n258 | n199); + assign n747 = n612 & (n434 | n258); + assign n748 = (n219 | n502) & (n272 | n537); + assign n749 = n219 | n522; + assign n750 = n219 | n262; + assign n751 = (n222 | n506) & (n43 | n472); + assign n752 = n595 & n194 & (n436 | n448); + assign n753 = n462 | n471; + assign n754 = (n258 | n483) & (n43 | n531); + assign n755 = n424 | n91; + assign n756 = n222 | (n529 & n530); + assign n757 = (n434 | n219) & (n222 | n542); + assign n758 = (n37 | n498) & (n436 | n294); + assign n759 = n258 | n546; + assign n760 = n40 | n472; + assign n761 = n760 & (n445 | n258); + assign n762 = (n309 | n525) & (n439 | n445); + assign n763 = (n309 | n493) & (n462 | n251); + assign n764 = n118 & (n219 | n534); + assign n765 = n272 | (n157 & n506); + assign n766 = n600 & n607 & (n33 | n539); + assign n767 = (n86 | n536) & (n37 | n511); + assign n768 = (n219 | n160) & (n86 | n517); + assign n769 = n222 | n519; + assign n770 = n222 | n525; + assign n771 = n40 | (n468 & n543); + assign n772 = (n91 | n486) & (n33 | n526); + assign n773 = n100 | (n495 & n544); + assign n774 = (n436 | n542) & (n222 | n517); + assign n775 = (n439 | n34) & (n40 | n463); + assign n776 = n258 | n534; + assign n777 = n189 & n147 & n77 & n776 & n775 & n774; + assign n778 = n309 | n476; + assign n779 = n436 | n519; + assign n780 = n680 & n652 & (n33 | n483); + assign n781 = n439 | n499; + assign n782 = n781 & n734 & (n37 | n486); + assign n783 = (n422 | n53) & (n43 | n517); + assign n784 = (n222 | n452) & (n258 | n469); + assign n785 = (n222 | n535) & (n462 | n490); + assign n786 = (n436 | n475) & (n91 | n522); + assign n787 = (n438 | n219) & (n33 | n498); + assign n788 = (n219 | n546) & (n37 | n500); + assign n789 = n445 | n91; + assign n790 = (n447 | n272) & (n37 | n504); + assign n791 = n184 & n790 & (n40 | n87); + assign n792 = (n53 & n258) | n488; + assign n793 = (n100 | n310) & (n91 | n502); + assign n794 = n793 & (n86 | n223); + assign n795 = n86 | (n491 & n529); + assign n796 = n558 & (n86 | n537); + assign n797 = n769 & n796 & (n43 | n542); + assign n798 = n753 & (n258 | n516); + assign n799 = (n258 | n526) & (n100 | n512); + assign n800 = n691 & n799 & (n272 | n531); + assign n801 = (n272 | n491) & (n33 | n504); + assign n802 = (n86 | n310) & (n37 | n199); + assign n803 = n44 & n802 & (n439 | n477); + assign n804 = n241 & n204 & n282; + assign n805 = n658 & n755 & (n91 | n500); + assign n806 = (n459 | n91) & (n53 | n504); + assign n807 = n57 & (n219 | n471); + assign n808 = n422 | n439; + assign n809 = n749 & (n222 | n465); + assign n810 = (n428 | n43) & (n462 | n150); + assign n811 = (n37 | n485) & (n222 | n533); + assign n812 = n436 | (n463 & n524); + assign n813 = n40 | (n142 & n530); + assign n814 = (n445 | n462) & (n444 | n258); + assign n815 = n814 & (n443 | n309); + assign n816 = (n272 | n481) & (n309 | n529); + assign n817 = (n258 | n478) & (n53 | n511); + assign n818 = n68 & n62 & (n439 | n160); + assign n819 = (n467 | n91) & (n462 | n482); + assign n820 = n687 & n819 & (n439 | n509); + assign n821 = (n33 | n473) & (n53 | n516); + assign n822 = n821 & n820 & (n40 | n531); + assign n823 = n91 | n499; + assign n824 = n823 & n689 & (n53 | n540); + assign n825 = (n436 | n543) & (n86 | n495); + assign n826 = n825 & n824 & (n258 | n505); + assign n827 = (n42 | n86) & (n428 | n272); + assign n828 = n394 & n357 & n385 & n311 & n295 & n336; + assign n829 = (n43 | n514) & (n462 | n483); + assign n830 = n684 & n829 & (n443 | n43); + assign n831 = (n91 | n490) & (n222 | n41); + assign n832 = (n436 | n501) & (n462 | n485); + assign n833 = (n436 | n41) & (n33 | n522); + assign n834 = n645 & n833 & (n438 | n258); + assign n835 = n603 & (n40 | n474); + assign n836 = n835 & n834 & (n309 | n521); + assign n837 = (n219 | n499) & (n272 | n142); + assign n838 = n683 & n837 & (n462 | n262); + assign n839 = (n272 | n458) & (n455 | n91); + assign n840 = n839 & n838 & (n439 | n488); + assign n841 = n647 & (n100 | n223); + assign n842 = n609 & n841 & (n439 | n511); + assign n843 = n33 | (n459 & n464); + assign n844 = (n436 | n506) & (n53 | n490); + assign n845 = n565 & n844 & (n43 | n41); + assign n846 = (n219 | n251) & (n91 | n505); + assign n847 = n37 | (n54 & n251); + assign n848 = (n439 | n540) & (n430 | n309); + assign n849 = n611 & (n462 | n464); + assign n850 = (n436 | n535) & (n43 | n487); + assign n851 = n275 & n850 & (n40 | n452); + assign n852 = n617 & (n40 | n475); + assign n853 = (n96 | n309) & (n40 | n310); + assign n854 = n853 & (n309 | n492); + assign n855 = (n258 | n538) & (n309 | n544); + assign n856 = (n219 | n504) & (n462 | n494); + assign n857 = n37 | n455; + assign n858 = n43 | n536; + assign n859 = (n37 & n53) | n547; + assign n860 = n779 & n859 & (n222 | n508); + assign n861 = n53 | (n154 & n259); + assign n862 = n861 & n860 & (n40 | n512); + assign n863 = (n53 | n538) & (n439 | n500); + assign n864 = n863 & (n100 | n543); + assign n865 = (n462 | n489) & (n100 | n510); + assign n866 = n865 & n864 & (n448 | n100); + assign n867 = (n436 | n481) & (n462 | n34); + assign n868 = (n436 | n474) & (n258 | n494); + assign n869 = n385 & n371 & n273 & n291 & n232 & n327; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/ex5p/ex5p.v b/openfpga_flow/benchmarks/MCNC_Verilog/ex5p/ex5p.v new file mode 100644 index 000000000..098a862f5 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/ex5p/ex5p.v @@ -0,0 +1,588 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:57 2019 + +module ex5p ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, + o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_, + o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_, + o_61_, o_62_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, + o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_, + o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_, + o_61_, o_62_; + wire n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, + n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, + n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, + n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, + n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, + n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, + n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, + n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, + n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, + n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, + n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, + n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, + n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, + n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, + n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, + n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, + n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, + n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, + n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, + n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, + n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, + n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, + n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, + n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, + n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, + n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, + n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, + n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, + n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, + n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, + n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, + n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, + n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, + n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, + n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, + n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, + n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, + n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, + n589, n590, n591, n592, n593, n594, n595, n596, n597; + assign o_0_ = ~n365; + assign o_1_ = ~n361; + assign o_2_ = ~n403; + assign o_3_ = ~n370; + assign o_4_ = ~n450; + assign o_5_ = ~n357; + assign o_6_ = ~n136; + assign o_7_ = ~n180; + assign o_8_ = ~n452; + assign o_9_ = ~n491; + assign o_10_ = ~n139; + assign o_11_ = ~n179; + assign o_12_ = ~n385; + assign o_13_ = ~n471; + assign o_14_ = ~n507; + assign o_15_ = ~n138; + assign o_16_ = ~n407; + assign o_17_ = ~n354; + assign o_18_ = ~n421; + assign o_19_ = ~n420; + assign o_20_ = ~n142; + assign o_21_ = ~n145; + assign o_22_ = ~n148; + assign o_23_ = ~n352; + assign o_24_ = ~n504; + assign o_25_ = ~n200; + assign o_26_ = ~n151; + assign o_27_ = ~n260; + assign o_28_ = ~n556; + assign o_29_ = ~n506; + assign o_30_ = ~n150; + assign o_31_ = ~n347; + assign o_32_ = ~n344; + assign o_33_ = ~n340; + assign o_34_ = ~n336; + assign o_35_ = ~n332; + assign o_36_ = ~n328; + assign o_37_ = ~n321; + assign o_38_ = ~n314; + assign o_39_ = ~n308; + assign o_40_ = ~n303; + assign o_41_ = ~n296; + assign o_42_ = ~n291; + assign o_43_ = ~n284; + assign o_44_ = ~n276; + assign o_45_ = ~n274; + assign o_46_ = ~n268; + assign o_47_ = ~n264; + assign o_48_ = ~n259; + assign o_49_ = ~n257; + assign o_50_ = ~n252; + assign o_51_ = ~n245; + assign o_52_ = ~n238; + assign o_53_ = ~n232; + assign o_54_ = ~n226; + assign o_55_ = ~n220; + assign o_56_ = ~n214; + assign o_57_ = ~n205; + assign o_58_ = ~n197; + assign o_59_ = ~n189; + assign o_60_ = ~n182; + assign o_61_ = ~n173; + assign o_62_ = ~n164; + assign n134 = n155 | n439; + assign n135 = n155 | n441; + assign n136 = n134 & n135; + assign n137 = n436 | n339; + assign n138 = n445 | n339; + assign n139 = n137 & n138; + assign n140 = n462 | n152; + assign n141 = n463 | n152; + assign n142 = n140 & n141; + assign n143 = n439 | n152; + assign n144 = n441 | n152; + assign n145 = n143 & n144; + assign n146 = n434 | n152; + assign n147 = n446 | n152; + assign n148 = n146 & n147; + assign n149 = n434 | n373; + assign n150 = n434 | n369; + assign n151 = n149 & n150; + assign n152 = i_2_ | ~i_0_ | i_1_; + assign n153 = n152 | ~n381; + assign n154 = ~i_3_ | ~i_4_ | ~i_5_; + assign n155 = i_0_ | i_1_ | ~i_2_; + assign n156 = n154 | n155; + assign n157 = i_0_ | i_1_ | i_2_; + assign n158 = n157 | ~n366; + assign n159 = n373 & n338; + assign n160 = n514 & n505 & n363; + assign n161 = n515 & n339 & n269 & n195 & n496; + assign n162 = n179 & n458 & n408 & n461 & n374; + assign n163 = n150 & n516 & n517 & n176 & n454; + assign n164 = n159 & n160 & n161 & n162 & n163; + assign n165 = n398 & n533 & n535; + assign n166 = n523 & n524; + assign n167 = n412 & n503; + assign n168 = n504 & n363; + assign n169 = n450 & n556; + assign n170 = n372 & n555 & n180; + assign n171 = n254 & n243 & n400; + assign n172 = n518 & n192 & n554; + assign n173 = n165 & n166 & n167 & n168 & n169 & n170 & n171 & n172; + assign n174 = n208 & n309 & n563 & n421 & n254 & n518; + assign n175 = n410 & n560 & n192 & n165 & n457 & n461 & n150 & n516; + assign n176 = n452 & n451; + assign n177 = n362 & n552 & n454; + assign n178 = n369 | n462; + assign n179 = n436 | n409; + assign n180 = n436 | n270; + assign n181 = n369 | n463; + assign n182 = n174 & n175 & n176 & n177 & n178 & n179 & n180 & n181; + assign n183 = n411 & (n157 | ~n382) & n412; + assign n184 = n548 & n298; + assign n185 = n418 & (n239 | n409); + assign n186 = n569 & n570 & n310 & n345 & n169 & n334 & n255 & n163; + assign n187 = n265 & n573 & n170 & n203; + assign n188 = n594 & n493 & n487 & n483 & n408 & n397 & ~n383 & n387; + assign n189 = n183 & n184 & n185 & n186 & n187 & n188; + assign n190 = n576 & n575 & n532 & n451 & n414 & n140 & n297 & ~n367; + assign n191 = n493 & ~n383 & n492; + assign n192 = n405 & n550 & n404 & n145 & n551 & n549; + assign n193 = n563 & n272; + assign n194 = n421 & n485 & n487; + assign n195 = n478 & n481 & n475 & n477; + assign n196 = n351 & n158 & (n154 | n157); + assign n197 = n190 & n191 & n192 & n193 & n194 & n195 & n138 & n196; + assign n198 = n470 & n468; + assign n199 = n150 & n536; + assign n200 = n270 | n443; + assign n201 = n261 & n471 & n394; + assign n202 = n228 & n414 & (n339 | ~n382); + assign n203 = n179 & n572; + assign n204 = n221 & n215 & n422 & n185 & n423 & n300; + assign n205 = n198 & n199 & n200 & n201 & n166 & n202 & n203 & n204; + assign n206 = n578 & n579 & n554 & n169; + assign n207 = n310 & n577; + assign n208 = n496 & n562; + assign n209 = n580 & ~n395 & n491; + assign n210 = n149 & n378 & n370 & n419 & n306; + assign n211 = n501 & n563; + assign n212 = n180 & n518; + assign n213 = n228 & n171 & n467 & n196 & n594 & n376 & n534 & n471; + assign n214 = n206 & n207 & n208 & n209 & n210 & n211 & n212 & n213; + assign n215 = n563 & n183; + assign n216 = n537 & ~n367 & n451; + assign n217 = n534 & n275 & n139 & n142; + assign n218 = n570 & n571 & n184 & n581 & n337 & n582; + assign n219 = n156 & n171 & n427 & n200; + assign n220 = n215 & n216 & n180 & n166 & n217 & n218 & n219; + assign n221 = n396 & n180 & n159; + assign n222 = n474 & n247; + assign n223 = n519 & n348 & n494; + assign n224 = n472 & n470; + assign n225 = n572 & n575 & n478 & n538 & n158 & n458 & n534 & n468; + assign n226 = n209 & n219 & n193 & n221 & n222 & n223 & n224 & n225; + assign n227 = n449 & n452; + assign n228 = n525 & n526; + assign n229 = n146 & n527 & n528 & n529 & n530; + assign n230 = n391 & n392 & (n393 | n339); + assign n231 = n476 & n583 & n537 & n137 & n141 & n534; + assign n232 = n174 & n218 & n227 & n228 & n229 & n230 & n231; + assign n233 = n351 & n215; + assign n234 = n254 & n494 & n559 & n509 & n262 & n292 & n426; + assign n235 = n387 & n491; + assign n236 = n384 & n385 & (n373 | n386); + assign n237 = n510 & n548; + assign n238 = n233 & n234 & n224 & n235 & n236 & n186 & n162 & n237; + assign n239 = ~n381 & ~n382; + assign n240 = n155 | n239; + assign n241 = n255 & n240 & n389 & n387 & n584 & n491; + assign n242 = n488 & n489; + assign n243 = n421 & n482; + assign n244 = n254 & n494 & n453; + assign n245 = n175 & n212 & n227 & n233 & n241 & n242 & n243 & n244; + assign n246 = n560 & n203; + assign n247 = n408 & ((~n381 & ~n382) | n409); + assign n248 = n200 & n483 & n486; + assign n249 = n540 & n539; + assign n250 = n524 & n192 & n412 & n501 & n168 & n288 & n293; + assign n251 = n535 & n543 & n546 & n477 & n380 & n533; + assign n252 = n246 & n247 & n248 & n249 & n250 & n251; + assign n253 = n288 & n248 & n342 & n586 & n266; + assign n254 = n155 | n446; + assign n255 = n155 | n443; + assign n256 = n350 & n158 & n351 & n520; + assign n257 = n193 & n235 & n253 & n254 & n255 & n256; + assign n258 = n254 & n241 & n135 & n134; + assign n259 = n258 & n253 & n242 & n160; + assign n260 = n443 | n339; + assign n261 = n434 | n339; + assign n262 = n429 & n281 & n248; + assign n263 = n417 & n224 & (n393 | n270); + assign n264 = n260 & n190 & n139 & n261 & n262 & n250 & n263; + assign n265 = n421 & n156 & n468 & n200; + assign n266 = n210 & n585 & n345 & n207; + assign n267 = n196 & n496 & n160 & n396 & n180 & n515; + assign n268 = n265 & n191 & n206 & n263 & n266 & n267; + assign n269 = n493 & n492 & n194 & n196 & ~n383; + assign n270 = i_2_ | i_0_ | ~i_1_; + assign n271 = n260 & n261; + assign n272 = n500 & n330 & n420 & n411 & n497 & n498; + assign n273 = n577 & n206 & n210; + assign n274 = n269 & n168 & n270 & n271 & n272 & n217 & n273; + assign n275 = n530 & n568 & n146 & n529; + assign n276 = n211 & n273 & n161 & n275; + assign n277 = n567 & n530 & n482 & ~n415 & n137 & n228 & ~n395; + assign n278 = n196 & n330 & n451 & n431 & n254 & n491 & n588 & n589; + assign n279 = n484 & n363 & n486 & n502; + assign n280 = n180 & (n270 | n355); + assign n281 = n476 & n583 & n468 & n396; + assign n282 = n298 & n417 & n222; + assign n283 = n511 & n405 & n499 & n508 & n374 & n377 & n179 & n595; + assign n284 = n277 & n278 & n249 & n279 & n280 & n281 & n282 & n283; + assign n285 = n477 & n394 & n471 & n378; + assign n286 = n413 & n423 & n590 & n138 & n144 & n228; + assign n287 = n179 & n553; + assign n288 = n422 & n243; + assign n289 = n419 & n420 & n579; + assign n290 = n549 & n406 & n410 & n563 & n569 & n411 & n380 & n596; + assign n291 = n285 & n286 & n248 & n278 & n287 & n288 & n289 & n290; + assign n292 = n288 & n404 & (n152 | ~n366); + assign n293 = n326 & n426 & n258; + assign n294 = n585 & n586 & n345 & n248; + assign n295 = n547 & n405 & n560 & n542 & n543 & n546; + assign n296 = n292 & n293 & n294 & n193 & n207 & n223 & n295; + assign n297 = n458 & n246 & n247; + assign n298 = n402 & n547; + assign n299 = n356 & n550 & n564; + assign n300 = n254 & n400 & n543; + assign n301 = n405 & n318 & n473 & n536 & n476 & n469 & n474 & n409; + assign n302 = n482 & n411 & n153 & n339 & n380 & n330 & n523; + assign n303 = n275 & n297 & n298 & n299 & n300 & n279 & n301 & n302; + assign n304 = n573 & n185 & n581 & n587 & n315 & n167 & n203 & n591; + assign n305 = n153 & n531; + assign n306 = n356 & n564 & n184; + assign n307 = n470 & n142 & n145 & n194 & n261 & ~n382; + assign n308 = n277 & n285 & n304 & n305 & n306 & n258 & n307; + assign n309 = n196 & n492 & n561; + assign n310 = n142 & n275 & ~n415; + assign n311 = n149 & n298 & n419; + assign n312 = n147 & n370 & n508; + assign n313 = n327 & n503 & n363; + assign n314 = n309 & n310 & n206 & n294 & n311 & n312 & n208 & n313; + assign n315 = n575 & n576 & n457 & n454; + assign n316 = n448 & n513 & n459; + assign n317 = n447 & n512 & n136 & n145 & n526 & n495 & n460; + assign n318 = n525 & n478 & n481; + assign n319 = n405 & n562 & n578 & n230 & n532 & n371; + assign n320 = n541 & n556 & n147 & n449 & n510 & n551 & n565 & n597; + assign n321 = n315 & n316 & n317 & n211 & n234 & n318 & n319 & n320; + assign n322 = n477 & n550 & n342 & n318 & n311 & n471 & n470 & n592; + assign n323 = n146 & n590; + assign n324 = n561 & n548 & n531 & n491 & ~n382 & n387; + assign n325 = n356 & n507; + assign n326 = n242 & n256; + assign n327 = n482 & n254; + assign n328 = n322 & n323 & n193 & n324 & n325 & n326 & n327 & n194; + assign n329 = n325 & n353 & (n152 | ~n381); + assign n330 = n515 & n495; + assign n331 = n531 & n486 & n485; + assign n332 = n243 & n293 & n322 & n323 & n329 & n330 & n211 & n331; + assign n333 = n143 & (n152 | ~n382); + assign n334 = n416 & (n270 | ~n366) & n417; + assign n335 = n518 & n398 & n243 & n180 & n254 & n508; + assign n336 = n286 & n304 & n324 & n298 & n333 & n334 & n335; + assign n337 = n572 & n578 & n287; + assign n338 = n152 & n511 & n312 & n402 & n512 & n513; + assign n339 = ~i_2_ | i_0_ | ~i_1_; + assign n340 = n216 & n301 & n211 & n337 & n338 & n208 & n339 & n269; + assign n341 = n550 & n311 & n329; + assign n342 = n206 & n223; + assign n343 = n180 & n482; + assign n344 = n279 & n341 & n258 & n342 & n326 & n272 & n165 & n343; + assign n345 = n202 & n413 & n567; + assign n346 = n523 & n505 & n229 & n305 & n330 & n363 & ~n415; + assign n347 = n345 & n206 & n171 & n334 & n224 & n262 & n341 & n346; + assign n348 = n157 | n370; + assign n349 = n519 & n520; + assign n350 = n154 | n157; + assign n351 = n445 | n157; + assign n352 = n348 & n349 & n350 & n351; + assign n353 = n152 | ~n366; + assign n354 = n153 & n353; + assign n355 = n435 | n442; + assign n356 = n442 | n444; + assign n357 = n355 & n356; + assign n358 = n157 | n462; + assign n359 = n488 & n515 & n178 & n552 & n316 & n396 & n486 & n593; + assign n360 = (~n366 & ~n381) | n438; + assign n361 = n143 & n358 & n134 & n140 & n359 & n360; + assign n362 = n409 | n463; + assign n363 = n358 & n506; + assign n364 = n468 & n483 & n489 & n142 & n509 & n465; + assign n365 = n181 & n362 & n363 & n317 & n359 & n364; + assign n366 = i_3_ & i_4_ & ~i_5_; + assign n367 = ~n369 & (~n154 | n366); + assign n368 = n369 | (n356 & n378); + assign n369 = ~i_0_ | ~i_1_ | ~i_2_; + assign n370 = n438 | n444; + assign n371 = n368 & (n369 | n370); + assign n372 = n445 | n373; + assign n373 = ~i_2_ | ~i_0_ | i_1_; + assign n374 = n372 & ((n154 & ~n366) | n373); + assign n375 = n339 | n239; + assign n376 = n464 & n465; + assign n377 = n376 & (n270 | n154); + assign n378 = n440 | n444; + assign n379 = n270 | (n356 & n378); + assign n380 = n180 & (n270 | ~n381); + assign n381 = ~i_5_ & ~i_3_ & i_4_; + assign n382 = i_5_ & ~i_3_ & i_4_; + assign n383 = ~n155 & (n381 | n382); + assign n384 = n373 | n355; + assign n385 = n436 | n373; + assign n386 = n435 | n440; + assign n387 = n155 | n436; + assign n388 = n387 & (n155 | ~n381); + assign n389 = n155 | (n355 & n386); + assign n390 = ~n157 & (~n154 | n366); + assign n391 = n378 | n339; + assign n392 = n140 & n138 & n566; + assign n393 = n154 & ~n366; + assign n394 = n260 & n376 & (n393 | n270); + assign n395 = ~n339 & (n381 | n382); + assign n396 = n270 | n439; + assign n397 = n396 & (n270 | ~n382); + assign n398 = n198 & n397 & (n270 | ~n381); + assign n399 = n155 | ~n382; + assign n400 = n136 & (n239 | n155); + assign n401 = n369 | (n355 & n386); + assign n402 = n443 | n373; + assign n403 = n435 | n438; + assign n404 = n149 & n402 & (n373 | n403); + assign n405 = n236 & (n239 | n373); + assign n406 = n372 & (n393 | n373); + assign n407 = n409 | n445; + assign n408 = n459 & n460; + assign n409 = ~i_0_ | ~i_1_ | i_2_; + assign n410 = n407 & n408 & (n393 | n409); + assign n411 = n436 | n157; + assign n412 = n157 | ~n381; + assign n413 = n137 & (n339 | ~n381); + assign n414 = n391 & n565 & n534; + assign n415 = ~n339 & (~n154 | n366); + assign n416 = n271 & n377; + assign n417 = n471 & n379; + assign n418 = n407 & n455 & n456; + assign n419 = n385 & (n373 | ~n381); + assign n420 = n412 & (n157 | ~n382); + assign n421 = n155 | ~n366; + assign n422 = n421 & (n155 | n154); + assign n423 = n339 | (n239 & n393); + assign n424 = n373 | n393; + assign n425 = n155 | (n356 & n378); + assign n426 = n425 & (n155 | n370); + assign n427 = n434 | n270; + assign n428 = n270 | (n386 & n403); + assign n429 = n280 & n427 & n428; + assign n430 = n409 | (n434 & n443); + assign n431 = n386 & n355 & n430; + assign n432 = i_3_ | i_4_ | i_5_; + assign n433 = ~i_6_ | ~i_7_; + assign n434 = n432 | n433; + assign n435 = i_3_ | i_4_ | ~i_5_; + assign n436 = n433 | n435; + assign n437 = i_5_ | ~i_3_ | i_4_; + assign n438 = i_6_ | i_7_; + assign n439 = n437 | n438; + assign n440 = i_6_ | ~i_7_; + assign n441 = n437 | n440; + assign n442 = ~i_6_ | i_7_; + assign n443 = n432 | n442; + assign n444 = ~i_5_ | ~i_3_ | i_4_; + assign n445 = n433 | n444; + assign n446 = n433 | n437; + assign n447 = n369 | n441; + assign n448 = n369 | n439; + assign n449 = n369 | n446; + assign n450 = n437 | n442; + assign n451 = n447 & n448 & n449 & n450; + assign n452 = n436 | n369; + assign n453 = n369 | n445; + assign n454 = ~n367 & n453; + assign n455 = n409 | n356; + assign n456 = n409 | n378; + assign n457 = n409 | n446; + assign n458 = n457 & n418; + assign n459 = n439 | n409; + assign n460 = n441 | n409; + assign n461 = n403 & n431; + assign n462 = n432 | n438; + assign n463 = n432 | n440; + assign n464 = n339 | n462; + assign n465 = n339 | n463; + assign n466 = n403 | n339; + assign n467 = n466 & n271; + assign n468 = n270 | n441; + assign n469 = n468 & n396; + assign n470 = n270 | n446; + assign n471 = n270 | n445; + assign n472 = n270 | n370; + assign n473 = n470 & n379 & n471 & n472; + assign n474 = n270 | ~n366; + assign n475 = n474 & n473; + assign n476 = n270 | ~n382; + assign n477 = n476 & n469; + assign n478 = n377 & n467; + assign n479 = n386 | n339; + assign n480 = n355 | n339; + assign n481 = n479 & n375 & n137 & n480; + assign n482 = n155 | n445; + assign n483 = n270 | n463; + assign n484 = n427 & n200 & n483; + assign n485 = n484 & n380; + assign n486 = n270 | n462; + assign n487 = n486 & n156; + assign n488 = n155 | n462; + assign n489 = n155 | n463; + assign n490 = n255 & n242; + assign n491 = n434 | n155; + assign n492 = n387 & n491 & n490; + assign n493 = n136 & n327; + assign n494 = n446 | n157; + assign n495 = n441 | n157; + assign n496 = n494 & n495; + assign n497 = n355 | n157; + assign n498 = n386 | n157; + assign n499 = n411 & n497 & n498; + assign n500 = n403 | n157; + assign n501 = n500 & n499; + assign n502 = n434 | n157; + assign n503 = n502 & n501; + assign n504 = n443 | n157; + assign n505 = n412 & n504 & n503; + assign n506 = n157 | n463; + assign n507 = n445 | n152; + assign n508 = n378 & n325; + assign n509 = n441 | n373; + assign n510 = n439 | n373; + assign n511 = n509 & n510; + assign n512 = n373 | n463; + assign n513 = n373 | n462; + assign n514 = n157 | ~n382; + assign n515 = n439 | n157; + assign n516 = n369 | n443; + assign n517 = n393 | n409; + assign n518 = n486 & n156 & n484; + assign n519 = n378 | n157; + assign n520 = n356 | n157; + assign n521 = n584 & n491 & n255; + assign n522 = n521 & n489 & n488 & n349 & n351 & n388 & n389 & ~n390; + assign n523 = n494 & n522; + assign n524 = n514 & n330; + assign n525 = n439 | n339; + assign n526 = n441 | n339; + assign n527 = n355 | n152; + assign n528 = n386 | n152; + assign n529 = n403 | n152; + assign n530 = n443 | n152; + assign n531 = n436 | n152; + assign n532 = n141 & n229 & n305; + assign n533 = n137 & n201 & ~n395; + assign n534 = n446 | n339; + assign n535 = n230 & n532 & n534 & n228; + assign n536 = n516 & n181 & n178; + assign n537 = n239 | n369; + assign n538 = n537 & n451 & n454 & n401 & n371; + assign n539 = n407 & n455; + assign n540 = ~n366 | n409; + assign n541 = n409 | n370; + assign n542 = n540 & n408 & n539 & n456 & n541 & n457; + assign n543 = n452 & n538; + assign n544 = n369 | n403; + assign n545 = n154 | n409; + assign n546 = n544 & n545 & n199; + assign n547 = n513 & n512; + assign n548 = n154 | n152; + assign n549 = n325 & n547 & n353 & n548; + assign n550 = n147 & n378 & n370; + assign n551 = n152 | ~n382; + assign n552 = n409 | n462; + assign n553 = n239 | n409; + assign n554 = n543 & n546 & n461 & n542 & n552 & n553 & n179 & n362; + assign n555 = n373 | ~n382; + assign n556 = n446 | n373; + assign n557 = n356 | n373; + assign n558 = n378 | n373; + assign n559 = n373 | n370; + assign n560 = n511 & n169 & n406 & n557 & n558 & n559; + assign n561 = n136 & ~n383; + assign n562 = n515 & n514 & n412; + assign n563 = n502 & n168; + assign n564 = n507 & n353; + assign n565 = n339 | n370; + assign n566 = n356 | n339; + assign n567 = n138 & n566; + assign n568 = n531 & n527 & n528; + assign n569 = n153 & n333; + assign n570 = n144 & n299; + assign n571 = n149 & n419; + assign n572 = n362 & n552 & n461; + assign n573 = n326 & n571 & n524 & n168; + assign n574 = n452 & n537 & n401; + assign n575 = n517 & n199; + assign n576 = n544 & n574; + assign n577 = n153 & n333 & n144 & n147; + assign n578 = n558 & n424 & n372 & n557; + assign n579 = n509 & n510 & n555; + assign n580 = n350 & n490; + assign n581 = n169 & n579; + assign n582 = n473 & n536 & n569 & n150 & n458 & n271; + assign n583 = n270 | ~n381; + assign n584 = n155 | n403; + assign n585 = n466 & n416 & n480 & n479; + assign n586 = n429 & n281 & n263; + assign n587 = n534 & n494; + assign n588 = n457 & n261 & n470; + assign n589 = n580 & n587 & n568 & n574 & n536 & n177 & n388 & n400; + assign n590 = n142 & n530; + assign n591 = n451 & n408 & n374; + assign n592 = n145 & n339 & n474; + assign n593 = n510 & n525 & n464; + assign n594 = n239 | n270; + assign n595 = n545 & n260; + assign n596 = n151 & n402 & n427; + assign n597 = n418 & n475 & n522 & n534 & n348 & n399; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/frisc/frisc.v b/openfpga_flow/benchmarks/MCNC_Verilog/frisc/frisc.v new file mode 100644 index 000000000..ea0d1ca1f --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/frisc/frisc.v @@ -0,0 +1,4994 @@ +// Benchmark "top" written by ABC on Mon Feb 4 17:32:32 2019 + +module frisc ( + tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_, + tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk, + pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_, + tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_, + tin_pdata_5_5_, preset, tin_pdata_13_13_, + ppeakb_7_7_, ppeakp_12_12_, ppeakp_0_0_, ppeaka_7_7_, ppeaki_15_15_, + ppeaki_11_11_, ppeaki_3_3_, paddress_3_3_, pdata_8_8_, pdata_0_0_, + ppeakb_14_14_, ppeakb_10_10_, ppeakb_8_8_, ppeakp_1_1_, ppeaka_14_14_, + ppeaka_10_10_, ppeaka_8_8_, ppeaki_4_4_, paddress_15_15_, + paddress_11_11_, paddress_2_2_, ppeakb_9_9_, ppeakp_2_2_, ppeaka_9_9_, + ppeaks_12_12_, ppeaks_0_0_, ppeaki_5_5_, paddress_5_5_, pdata_7_7_, + ppeakb_15_15_, ppeakp_3_3_, pwr_0_0_, ppeaks_1_1_, ppeaki_6_6_, + paddress_4_4_, piack_0_0_, ppeakp_13_13_, ppeakp_4_4_, ppeaka_15_15_, + ppeaka_11_11_, ppeaks_2_2_, ppeaki_7_7_, paddress_10_10_, + paddress_7_7_, pdata_2_2_, ppeakp_5_5_, ppeaks_13_13_, ppeaks_3_3_, + ppeaki_14_14_, ppeaki_10_10_, ppeaki_8_8_, paddress_6_6_, ppeakp_6_6_, + ppeaks_4_4_, ppeaki_9_9_, paddress_9_9_, pdata_9_9_, pdata_1_1_, + ppeakb_11_11_, ppeakp_7_7_, ppeaks_5_5_, paddress_13_13_, + paddress_8_8_, ppeakp_14_14_, ppeakp_10_10_, ppeakp_8_8_, ppeaks_6_6_, + ppeaki_13_13_, pdata_4_4_, ppeakb_0_0_, ppeakp_9_9_, ppeaka_0_0_, + ppeaks_7_7_, ppeakb_1_1_, ppeaka_1_1_, ppeaks_10_10_, ppeaks_8_8_, + pdata_10_10_, pdata_3_3_, ppeakb_12_12_, ppeakb_2_2_, ppeaka_12_12_, + ppeaka_2_2_, ppeaks_15_15_, ppeaks_9_9_, ppeakb_3_3_, ppeakp_15_15_, + ppeakp_11_11_, ppeaka_13_13_, ppeaka_3_3_, paddress_14_14_, + paddress_12_12_, pdata_6_6_, ppeakb_13_13_, ppeakb_4_4_, pdn, + ppeaka_4_4_, ppeaki_0_0_, prd_0_0_, pdata_15_15_, pdata_11_11_, + ppeakb_5_5_, ppeaka_5_5_, ppeaks_14_14_, ppeaki_1_1_, paddress_1_1_, + pdata_14_14_, pdata_12_12_, pdata_5_5_, ppeakb_6_6_, ppeaka_6_6_, + ppeaks_11_11_, ppeaki_12_12_, ppeaki_2_2_, paddress_0_0_, pdata_13_13_ ); + input tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_, + tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk, + pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_, + tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_, + tin_pdata_5_5_, preset, tin_pdata_13_13_; + output ppeakb_7_7_, ppeakp_12_12_, ppeakp_0_0_, ppeaka_7_7_, ppeaki_15_15_, + ppeaki_11_11_, ppeaki_3_3_, paddress_3_3_, pdata_8_8_, pdata_0_0_, + ppeakb_14_14_, ppeakb_10_10_, ppeakb_8_8_, ppeakp_1_1_, ppeaka_14_14_, + ppeaka_10_10_, ppeaka_8_8_, ppeaki_4_4_, paddress_15_15_, + paddress_11_11_, paddress_2_2_, ppeakb_9_9_, ppeakp_2_2_, ppeaka_9_9_, + ppeaks_12_12_, ppeaks_0_0_, ppeaki_5_5_, paddress_5_5_, pdata_7_7_, + ppeakb_15_15_, ppeakp_3_3_, pwr_0_0_, ppeaks_1_1_, ppeaki_6_6_, + paddress_4_4_, piack_0_0_, ppeakp_13_13_, ppeakp_4_4_, ppeaka_15_15_, + ppeaka_11_11_, ppeaks_2_2_, ppeaki_7_7_, paddress_10_10_, + paddress_7_7_, pdata_2_2_, ppeakp_5_5_, ppeaks_13_13_, ppeaks_3_3_, + ppeaki_14_14_, ppeaki_10_10_, ppeaki_8_8_, paddress_6_6_, ppeakp_6_6_, + ppeaks_4_4_, ppeaki_9_9_, paddress_9_9_, pdata_9_9_, pdata_1_1_, + ppeakb_11_11_, ppeakp_7_7_, ppeaks_5_5_, paddress_13_13_, + paddress_8_8_, ppeakp_14_14_, ppeakp_10_10_, ppeakp_8_8_, ppeaks_6_6_, + ppeaki_13_13_, pdata_4_4_, ppeakb_0_0_, ppeakp_9_9_, ppeaka_0_0_, + ppeaks_7_7_, ppeakb_1_1_, ppeaka_1_1_, ppeaks_10_10_, ppeaks_8_8_, + pdata_10_10_, pdata_3_3_, ppeakb_12_12_, ppeakb_2_2_, ppeaka_12_12_, + ppeaka_2_2_, ppeaks_15_15_, ppeaks_9_9_, ppeakb_3_3_, ppeakp_15_15_, + ppeakp_11_11_, ppeaka_13_13_, ppeaka_3_3_, paddress_14_14_, + paddress_12_12_, pdata_6_6_, ppeakb_13_13_, ppeakb_4_4_, pdn, + ppeaka_4_4_, ppeaki_0_0_, prd_0_0_, pdata_15_15_, pdata_11_11_, + ppeakb_5_5_, ppeaka_5_5_, ppeaks_14_14_, ppeaki_1_1_, paddress_1_1_, + pdata_14_14_, pdata_12_12_, pdata_5_5_, ppeakb_6_6_, ppeaka_6_6_, + ppeaks_11_11_, ppeaki_12_12_, ppeaki_2_2_, paddress_0_0_, pdata_13_13_; + reg ndout, ppeakb_12_12_, ppeakb_1_1_, ppeaka_6_6_, \[4295] , \[4310] , + ppeaks_5_5_, ppeakp_10_10_, \[4355] , \[4370] , \[4385] , \[4400] , + \[4415] , \[4430] , \[4445] , \[4460] , \[4475] , \[4490] , \[4505] , + \[4520] , \[4535] , \[4550] , \[4565] , \[4580] , \[4595] , \[4610] , + \[4625] , \[4640] , \[4655] , \[4670] , \[4700] , \[4715] , \[4730] , + \[4745] , \[4760] , \[4775] , \[4790] , \[4805] , \[4820] , \[4835] , + \[4850] , \[4865] , \[4880] , \[4895] , \[4910] , \[4925] , \[4940] , + \[4955] , \[4970] , ppeakb_0_0_, ppeaka_7_7_, \[5015] , \[5030] , + ppeaks_4_4_, ppeakp_11_11_, \[5075] , \[5090] , \[5105] , \[5120] , + \[5135] , \[5150] , \[5165] , \[5180] , \[5195] , \[5210] , \[5225] , + \[5240] , \[5255] , \[5270] , \[5285] , \[5300] , \[5315] , \[5330] , + \[5345] , \[5360] , \[5375] , \[5390] , \[5405] , \[5420] , \[5435] , + \[5450] , \[5465] , \[5480] , \[5495] , \[5510] , \[5525] , \[5540] , + \[5555] , \[5570] , \[5600] , \[5615] , \[5630] , \[5645] , \[5660] , + \[5675] , ppeakb_10_10_, ppeaka_8_8_, \[5720] , ppeaks_14_14_, + ppeaks_7_7_, ppeakp_12_12_, \[5780] , \[5795] , \[5810] , \[5825] , + \[5840] , \[5855] , \[5870] , \[5885] , \[5900] , \[5915] , \[5930] , + \[5945] , \[5960] , \[5975] , \[5990] , \[6005] , \[6020] , \[6035] , + \[6050] , \[6065] , \[6080] , \[6095] , \[6110] , \[6125] , \[6140] , + \[6155] , \[6170] , \[6185] , \[6200] , \[6215] , \[6230] , \[6245] , + \[6260] , \[6275] , \[6290] , \[6305] , \[6320] , \[6335] , \[6350] , + \[6365] , ppeakb_11_11_, ppeakb_2_2_, \[6410] , ppeaks_15_15_, + ppeaks_6_6_, ppeakp_13_13_, \[6470] , \[6485] , \[6500] , \[6515] , + \[6530] , \[6545] , \[6560] , \[6575] , \[6590] , \[6605] , \[6620] , + \[6635] , \[6650] , \[6665] , \[6680] , \[6695] , \[6710] , \[6725] , + \[6740] , \[6755] , \[6770] , \[6785] , \[6815] , \[6830] , \[6845] , + \[6860] , \[6875] , \[6890] , \[6905] , \[6920] , \[6935] , \[6950] , + \[6965] , \[6980] , \[6995] , \[7010] , \[7025] , \[7055] , + ppeaks_12_12_, ppeaks_1_1_, ppeakp_3_3_, \[7115] , \[7130] , \[7145] , + \[7160] , \[7175] , \[7190] , \[7205] , \[7220] , \[7235] , \[7250] , + \[7265] , \[7280] , \[7295] , \[7310] , \[7325] , \[7340] , \[7355] , + \[7370] , \[7385] , \[7400] , \[7415] , \[7430] , \[7445] , \[7460] , + \[7475] , \[7490] , \[7505] , \[7520] , \[7535] , \[7550] , \[7565] , + \[7580] , \[7595] , \[7625] , \[7640] , \[7655] , \[7670] , \[7685] , + ppeaks_13_13_, ppeakp_7_7_, ppeakp_2_2_, \[7745] , \[7760] , \[7775] , + \[7790] , \[7805] , \[7820] , \[7835] , \[7850] , \[7865] , \[7880] , + \[7895] , \[7910] , \[7925] , \[7940] , \[7955] , \[7970] , \[8000] , + \[8015] , \[8030] , \[8045] , \[8060] , \[8075] , \[8090] , \[8105] , + \[8120] , \[8135] , \[8150] , \[8165] , \[8180] , \[8195] , \[8210] , + \[8225] , \[8240] , \[8255] , \[8285] , \[8300] , \[8315] , \[8330] , + ppeaks_3_3_, ppeakp_8_8_, ppeakp_1_1_, \[8390] , \[8405] , \[8420] , + \[8435] , \[8450] , \[8465] , \[8480] , \[8495] , \[8510] , \[8525] , + \[8540] , \[8555] , \[8570] , \[8585] , \[8600] , \[8615] , \[8630] , + \[8645] , \[8660] , \[8675] , \[8690] , \[8705] , \[8720] , \[8735] , + \[8750] , \[8765] , \[8780] , \[8810] , \[8825] , \[8840] , \[8855] , + \[8870] , \[8885] , \[8900] , \[8915] , \[8930] , \[8945] , \[8960] , + \[8975] , ppeaks_11_11_, ppeaks_2_2_, ppeakp_9_9_, ppeakp_0_0_, + \[9050] , \[9065] , \[9080] , \[9095] , \[9110] , \[9125] , \[9140] , + \[9155] , \[9170] , \[9185] , \[9200] , \[9215] , \[9230] , \[9245] , + \[9260] , \[9275] , \[9290] , \[9305] , \[9320] , \[9335] , \[9350] , + \[9365] , \[9380] , \[9395] , \[9410] , \[9440] , \[9455] , \[9470] , + \[9485] , \[9500] , \[9515] , \[9530] , \[9545] , \[9560] , \[9575] , + \[9590] , \[9605] , \[9620] , \[9635] , \[9650] , \[9665] , \[9680] , + ppeaki_6_6_, \[9710] , \[9725] , \[9740] , \[9770] , \[9785] , + \[9800] , \[9815] , \[9830] , \[9845] , \[9860] , \[9875] , \[9890] , + \[9905] , \[9920] , \[9935] , \[9950] , \[9980] , \[9995] , \[10010] , + \[10025] , \[10040] , \[10055] , \[10070] , \[10085] , \[10100] , + \[10115] , \[10130] , \[10145] , \[10175] , \[10190] , \[10205] , + \[10220] , ppeaki_15_15_, ppeaki_4_4_, \[10265] , \[10280] , \[10310] , + \[10325] , \[10340] , \[10355] , \[10370] , \[10400] , \[10415] , + \[10430] , \[10445] , \[10460] , \[10475] , \[10490] , \[10505] , + ppeaki_14_14_, ppeaki_5_5_, \[10550] , \[10565] , \[10580] , \[10595] , + \[10610] , \[10625] , \[10655] , \[10670] , \[10685] , \[10700] , + \[10715] , \[10730] , \[10745] , \[10760] , \[10775] , \[10790] , + \[10805] , \[10820] , \[10850] , \[10865] , \[10880] , \[10895] , + \[10925] , \[10940] , \[10955] , \[10970] , \[10985] , \[11015] , + \[11030] , \[11045] , \[11060] , \[11075] , \[11090] , \[11120] , + \[11135] , \[11150] , \[11165] , \[11180] , \[11195] , \[11210] , + \[11225] , \[11240] , \[11255] , \[11270] , \[11285] , \[11300] , + \[11315] , \[11330] , \[11345] , \[11375] , \[11390] , \[11405] , + \[11420] , \[11435] , \[11450] , \[11465] , \[11480] , \[11495] , + \[11510] , \[11525] , \[11540] , \[11555] , \[11570] , \[11585] , + \[11600] , \[11615] , \[11630] , \[11645] , \[11660] , \[11675] , + \[11690] , \[11705] , \[11720] , \[11735] , \[11750] , \[11765] , + \[11780] , \[11795] , \[11810] , ppeaki_9_9_, ppeakb_14_14_, \[11885] , + \[11900] , \[11915] , \[11930] , ppeaki_8_8_, ppeakb_15_15_, \[12005] , + \[12020] , \[12035] , \[12050] , \[12065] , \[12080] , ppeaki_7_7_, + \[12125] , \[12140] , \[12155] , \[12170] , \[12185] , \[12200] , + ppeakb_13_13_, \[12245] , \[12260] , \[12275] , ppeaki_13_13_, + ppeaki_2_2_, \[12335] , \[12350] , \[12365] , \[12380] , \[12395] , + \[12410] , \[12425] , \[12440] , \[12455] , \[12470] , \[12485] , + ppeaki_12_12_, ppeaki_3_3_, \[12545] , \[12560] , \[12575] , \[12590] , + \[12605] , \[12620] , \[12635] , \[12650] , \[12665] , \[12680] , + \[12695] , ppeaki_11_11_, ppeaki_0_0_, \[12770] , \[12800] , \[12815] , + \[12830] , \[12845] , \[12860] , \[12875] , \[12890] , \[12905] , + \[12920] , \[12935] , ppeaki_10_10_, ppeaki_1_1_, \[13010] , \[13025] , + \[13040] , \[13055] , \[13070] , \[13085] , \[13100] , \[13115] , + \[13130] , \[13160] , \[13175] , ppeakb_4_4_, ppeaka_9_9_, \[13220] , + \[13235] , \[13250] , \[13265] , \[13280] , \[13295] , \[13310] , + \[13325] , \[13340] , \[13355] , \[13370] , \[13385] , \[13400] , + \[13415] , \[13430] , \[13445] , \[13460] , \[13475] , \[13490] , + \[13505] , ppeakb_5_5_, \[13550] , ppeakp_6_6_, \[13580] , \[13595] , + \[13610] , \[13625] , \[13640] , \[13655] , \[13670] , \[13685] , + \[13700] , \[13715] , \[13730] , \[13745] , \[13775] , \[13790] , + \[13805] , \[13820] , \[13835] , \[13850] , \[13865] , \[13880] , + \[13895] , ppeaka_11_11_, ppeaka_0_0_, ppeakp_5_5_, \[13955] , + \[13970] , \[13985] , \[14000] , \[14015] , \[14030] , \[14045] , + \[14060] , \[14075] , \[14090] , \[14105] , \[14120] , \[14135] , + \[14150] , \[14165] , \[14180] , \[14210] , \[14225] , \[14240] , + \[14255] , \[14270] , \[14285] , ppeakb_3_3_, ppeaka_10_10_, + ppeaka_1_1_, ppeakp_4_4_, \[14360] , \[14375] , \[14390] , \[14405] , + \[14420] , \[14435] , \[14450] , \[14465] , \[14480] , \[14495] , + \[14510] , \[14525] , \[14540] , \[14555] , \[14570] , \[14585] , + \[14600] , \[14615] , \[14630] , \[14660] , \[14675] , \[14690] , + \[14705] , ppeakb_8_8_, ppeaka_13_13_, ppeaka_2_2_, \[14765] , + ppeaks_9_9_, ppeakp_14_14_, \[14810] , \[14825] , \[14840] , \[14855] , + \[14870] , \[14885] , \[14900] , \[14915] , \[14930] , \[14960] , + \[14975] , \[14990] , \[15005] , \[15020] , \[15035] , \[15050] , + \[15065] , \[15080] , ppeakb_9_9_, ppeaka_12_12_, ppeaka_3_3_, + \[15140] , ppeaks_8_8_, ppeakp_15_15_, \[15185] , \[15200] , \[15215] , + \[15230] , \[15245] , \[15260] , \[15275] , \[15290] , \[15305] , + \[15320] , \[15335] , \[15350] , \[15365] , \[15380] , \[15395] , + \[15410] , \[15425] , \[15440] , ppeakb_6_6_, ppeaka_15_15_, + ppeaka_4_4_, \[15500] , \[15515] , ppeaks_0_0_, \[15545] , \[15560] , + \[15575] , \[15590] , \[15605] , \[15620] , \[15635] , \[15650] , + \[15665] , \[15680] , \[15695] , \[15710] , \[15725] , \[15755] , + \[15770] , \[15785] , ppeakb_7_7_, ppeaka_14_14_, ppeaka_5_5_, + \[15845] , \[15860] , ppeaks_10_10_, \[15890] , \[15905] , \[15920] , + \[15935] , \[15950] , \[15965] , \[15980] , \[15995] , \[16010] , + \[16025] , \[16040] , \[16055] , \[16070] , \[16085] , \[16100] , + paddress_8_8_, \[16907] , \[16920] , \[16933] , paddress_9_9_, + \[16959] , \[16972] , \[16985] , \[16998] , \[17011] , \[17024] , + \[17037] , \[17050] , \[17063] , \[17076] , \[17089] , \[17102] , + \[17115] , \[17128] , \[17141] , \[17154] , \[17167] , \[17180] , + \[17193] , \[17206] , \[17219] , \[17232] , \[17245] , \[17258] , + \[17271] , \[17284] , \[17297] , \[17310] , \[17323] , \[17336] , + \[17349] , \[17362] , \[17375] , \[17388] , paddress_11_11_, \[17414] , + \[17427] , \[17453] , paddress_10_10_, \[17479] , \[17492] , \[17505] , + \[17518] , \[17531] , \[17544] , paddress_13_13_, \[17570] , \[17583] , + \[17596] , \[17609] , paddress_12_12_, \[17635] , \[17648] , \[17661] , + \[17674] , paddress_15_15_, \[17700] , \[17713] , paddress_14_14_, + \[17739] , \[17752] , \[17765] , \[17778] , \[17791] , \[17804] , + \[17817] , pwr_0_0_, \[17843] , \[17856] , \[17869] , \[17882] , + prd_0_0_, \[17908] , \[17921] , \[17934] , \[17947] , \[17960] , + \[17973] , \[17986] , \[17999] , \[18012] , \[18025] , \[18038] , pdn, + \[18064] , \[18077] , \[18090] , \[18103] , \[18116] , \[18129] , + \[18142] , \[18155] , \[18168] , \[18181] , \[18194] , \[18207] , + \[18220] , \[18233] , \[18246] , paddress_0_0_, piack_0_0_, \[18285] , + \[18298] , \[18311] , paddress_1_1_, \[18337] , \[18350] , \[18363] , + \[18376] , \[18389] , paddress_2_2_, \[18415] , \[18428] , \[18441] , + paddress_3_3_, \[18467] , \[18480] , \[18493] , \[18506] , + paddress_4_4_, paddress_5_5_, \[18545] , paddress_6_6_, \[18571] , + \[18584] , \[18597] , \[18610] , paddress_7_7_, \[18636] ; + wire n3696_1, n3697, n3698, n3699, n3700, n3701_1, n3702, n3703, n3704, + n3705, n3706_1, n3707, n3708, n3709, n3710, n3711_1, n3712, n3713, + n3714, n3715, n3716_1, n3717, n3718, n3719, n3720, n3721_1, n3722, + n3723, n3724, n3725, n3726_1, n3727, n3728, n3729, n3730, n3731_1, + n3732, n3733, n3734, n3735, n3736_1, n3737, n3738, n3739, n3740, + n3741_1, n3742, n3743, n3744, n3745, n3746_1, n3747, n3748, n3749, + n3750_1, n3751, n3752, n3753, n3754_1, n3755, n3756, n3757, n3758_1, + n3759, n3760, n3761, n3762, n3763_1, n3764, n3765, n3766, n3767, + n3768_1, n3769, n3770, n3771, n3772_1, n3773, n3774, n3775, n3776, + n3777_1, n3778, n3779, n3780, n3781, n3782_1, n3783, n3784, n3785, + n3786, n3787_1, n3788, n3789, n3790, n3791, n3792_1, n3793, n3794, + n3795, n3796, n3797_1, n3798, n3799, n3800, n3801, n3802_1, n3803, + n3804, n3805, n3806, n3807_1, n3808, n3809, n3810, n3811, n3812_1, + n3813, n3814, n3815, n3816, n3817_1, n3818, n3819, n3820, n3821, + n3822_1, n3823, n3824, n3825, n3826, n3827_1, n3828, n3829, n3830, + n3831, n3832_1, n3833, n3834, n3835, n3836, n3837_1, n3838, n3839, + n3840, n3841, n3842_1, n3843, n3844, n3845, n3846, n3847_1, n3848, + n3849, n3850, n3851, n3852_1, n3853, n3854, n3855, n3856_1, n3857, + n3858, n3859, n3860_1, n3861, n3862, n3863, n3864_1, n3865, n3866, + n3867, n3868, n3869_1, n3870, n3871, n3872, n3873, n3874_1, n3875, + n3876, n3877, n3878_1, n3879, n3880, n3881, n3882, n3883_1, n3884, + n3885, n3886, n3887, n3888_1, n3889, n3890, n3891, n3892, n3893_1, + n3894, n3895, n3896, n3897, n3898_1, n3899, n3900, n3901, n3902, + n3903_1, n3904, n3905, n3906, n3907, n3908_1, n3909, n3910, n3911, + n3912, n3913_1, n3914, n3915, n3916, n3917, n3918_1, n3919, n3920, + n3921, n3922, n3923_1, n3924, n3925, n3926, n3927, n3928_1, n3929, + n3930, n3931, n3932, n3933_1, n3934, n3935, n3936, n3937, n3938_1, + n3939, n3940, n3941, n3942, n3943_1, n3944, n3945, n3946, n3947, + n3948_1, n3949, n3950, n3951, n3952, n3953_1, n3954, n3955, n3956, + n3957_1, n3958, n3959, n3960, n3961, n3962_1, n3963, n3964, n3965, + n3966, n3967_1, n3968, n3969, n3970, n3971, n3972_1, n3973, n3974, + n3975, n3976_1, n3977, n3978, n3979, n3980, n3981_1, n3982, n3983, + n3984, n3985, n3986_1, n3987, n3988, n3989, n3990, n3991_1, n3992, + n3993, n3994, n3995, n3996_1, n3997, n3998, n3999, n4000, n4001_1, + n4002, n4003, n4004, n4005, n4006_1, n4007, n4008, n4009, n4010, + n4011_1, n4012, n4013, n4014, n4015, n4016_1, n4017, n4018, n4019, + n4020, n4021_1, n4022, n4023, n4024, n4025, n4026_1, n4027, n4028, + n4029, n4030, n4031_1, n4032, n4033, n4034, n4035, n4036_1, n4037, + n4038, n4039, n4040, n4041_1, n4042, n4043, n4044, n4045, n4046_1, + n4047, n4048, n4049, n4050, n4051_1, n4052, n4053, n4054, n4055, + n4056_1, n4057, n4058, n4059, n4060, n4061_1, n4062, n4063, n4064, + n4065, n4066_1, n4067, n4068, n4069, n4070, n4071_1, n4072, n4073, + n4074, n4075, n4076_1, n4077, n4078, n4079, n4080, n4081_1, n4082, + n4083, n4084, n4085, n4086_1, n4087, n4088, n4089, n4090, n4091_1, + n4092, n4093, n4094, n4095, n4096_1, n4097, n4098, n4099, n4100, + n4101_1, n4102, n4103, n4104, n4105, n4106_1, n4107, n4108, n4109, + n4110, n4111_1, n4112, n4113, n4114, n4115, n4116_1, n4117, n4118, + n4119, n4120, n4121_1, n4122, n4123, n4124, n4125, n4126_1, n4127, + n4128, n4129, n4130, n4131_1, n4132, n4133, n4134, n4135, n4136_1, + n4137, n4138, n4139, n4140, n4141_1, n4142, n4143, n4144, n4145, + n4146_1, n4147, n4148, n4149, n4150_1, n4151, n4152, n4153, n4154, + n4155_1, n4156, n4157, n4158, n4159, n4160_1, n4161, n4162, n4163, + n4164, n4165_1, n4166, n4167, n4168, n4169_1, n4170, n4171, n4172, + n4173, n4174_1, n4175, n4176, n4177, n4178, n4179_1, n4180, n4181, + n4182, n4183, n4184_1, n4185, n4186, n4187, n4188, n4189_1, n4190, + n4191, n4192, n4193, n4194_1, n4195, n4196, n4197, n4198, n4199_1, + n4200, n4201, n4202, n4203_1, n4204, n4205, n4206, n4207, n4208_1, + n4209, n4210, n4211, n4212, n4213_1, n4214, n4215, n4216, n4217, + n4218_1, n4219, n4220, n4221, n4222, n4223_1, n4224, n4225, n4226, + n4227_1, n4228, n4229, n4230, n4231, n4232_1, n4233, n4234, n4235, + n4236, n4237_1, n4238, n4239, n4240, n4241, n4242_1, n4243, n4244, + n4245, n4246, n4247_1, n4248, n4249, n4250, n4251_1, n4252, n4253, + n4254, n4255, n4256_1, n4257, n4258, n4259, n4260, n4261_1, n4262, + n4263, n4264, n4265_1, n4266, n4267, n4268, n4269, n4270_1, n4271, + n4272, n4273, n4274, n4275_1, n4276, n4277, n4278, n4279, n4280_1, + n4281, n4282, n4283, n4284, n4285_1, n4286, n4287, n4288, n4289, + n4290_1, n4291, n4292, n4293, n4294, n4295_1, n4296, n4297, n4298, + n4299, n4300_1, n4301, n4302, n4303, n4304_1, n4305, n4306, n4307, + n4308, n4309_1, n4310, n4311, n4312, n4313, n4314_1, n4315, n4316, + n4317, n4318, n4319_1, n4320, n4321, n4322, n4323, n4324_1, n4325, + n4326, n4327, n4328_1, n4329, n4330, n4331, n4332, n4333_1, n4334, + n4335, n4336, n4337, n4338_1, n4339, n4340, n4341, n4342, n4343_1, + n4344, n4345, n4346, n4347, n4348_1, n4349, n4350, n4351, n4352, + n4353_1, n4354, n4355, n4356, n4357, n4358_1, n4359, n4360, n4361, + n4362, n4363_1, n4364, n4365, n4366, n4367, n4368_1, n4369, n4370, + n4371, n4372, n4373_1, n4374, n4375, n4376, n4377, n4378_1, n4379, + n4380, n4381, n4382, n4383_1, n4384, n4385, n4386, n4387_1, n4388, + n4389, n4390, n4391, n4392_1, n4393, n4394, n4395, n4396, n4397_1, + n4398, n4399, n4400, n4401, n4402_1, n4403, n4404, n4405, n4406, + n4407_1, n4408, n4409, n4410, n4411, n4412_1, n4413, n4414, n4415, + n4416, n4417_1, n4418, n4419, n4420, n4421, n4422_1, n4423, n4424, + n4425, n4426, n4427_1, n4428, n4429, n4430, n4431, n4432_1, n4433, + n4434, n4435, n4436, n4437_1, n4438, n4439, n4440, n4441, n4442_1, + n4443, n4444, n4445, n4446, n4447_1, n4448, n4449, n4450, n4451, + n4452_1, n4453, n4454, n4455, n4456, n4457_1, n4458, n4459, n4460, + n4461, n4462_1, n4463, n4464, n4465, n4466_1, n4467, n4468, n4469, + n4470_1, n4471, n4472, n4473, n4474, n4475_1, n4476, n4477, n4478, + n4479, n4480_1, n4481, n4482, n4483, n4484, n4485_1, n4486, n4487, + n4488, n4489_1, n4490, n4491, n4492, n4493, n4494_1, n4495, n4496, + n4497, n4498, n4499_1, n4500, n4501, n4502, n4503, n4504_1, n4505, + n4506, n4507, n4508, n4509_1, n4510, n4511, n4512, n4513, n4514_1, + n4515, n4516, n4517, n4518_1, n4519, n4520, n4521, n4522, n4523_1, + n4524, n4525, n4526, n4527, n4528_1, n4529, n4530, n4531, n4532, + n4533_1, n4534, n4535, n4536, n4537_1, n4538, n4539, n4540, n4541, + n4542_1, n4543, n4544, n4545, n4546, n4547_1, n4548, n4549, n4550, + n4551, n4552_1, n4553, n4554, n4555, n4556, n4557_1, n4558, n4559, + n4560, n4561_1, n4562, n4563, n4564, n4565_1, n4566, n4567, n4568, + n4569, n4570_1, n4571, n4572, n4573, n4574_1, n4575, n4576, n4577, + n4578, n4579_1, n4580, n4581, n4582, n4583, n4584_1, n4585, n4586, + n4587, n4588, n4589_1, n4590, n4591, n4592, n4593, n4594_1, n4595, + n4596, n4597, n4598_1, n4599, n4600, n4601, n4602, n4603, n4604, n4605, + n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, + n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, + n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, + n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, + n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, + n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, + n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, + n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, + n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, + n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, + n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, + n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, + n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, + n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, + n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, + n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, + n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, + n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, + n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, + n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, + n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, + n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, + n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, + n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, + n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, + n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, + n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, + n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, + n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, + n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, + n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, + n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, + n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, + n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, + n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, + n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, + n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, + n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, + n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, + n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, + n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, + n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, + n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, + n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, + n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, + n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, + n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, + n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, + n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, + n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, + n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, + n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, + n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, + n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, + n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, + n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, + n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, + n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, + n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, + n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, + n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, + n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, + n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, + n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, + n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, + n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, + n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, + n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, + n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, + n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, + n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, + n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, + n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335, + n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345, + n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, + n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365, + n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375, + n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385, + n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, + n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405, + n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415, + n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425, + n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, + n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445, + n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455, + n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465, + n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, + n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485, + n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495, + n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505, + n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, + n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525, + n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, + n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, + n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, + n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, + n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, + n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, + n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, + n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605, + n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615, + n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625, + n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, + n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645, + n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655, + n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665, + n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675, + n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685, + n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695, + n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705, + n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715, + n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725, + n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735, + n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745, + n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, + n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, + n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, + n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, + n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, + n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, + n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, + n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, + n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, + n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, + n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, + n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, + n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, + n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, + n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, + n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, + n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, + n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, + n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, + n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, + n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, + n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, + n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, + n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, + n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, + n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, + n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015, + n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, + n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, + n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, + n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, + n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, + n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, + n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, + n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, + n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, + n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, + n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, + n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, + n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, + n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, + n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, + n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, + n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, + n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, + n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, + n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, + n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, + n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, + n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, + n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, + n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, + n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, + n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, + n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, + n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, + n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, + n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, + n6326, n6327, n6328, n6329, n6330, n6331, n6332, n273, n278, n282, + n286, n290, n295, n300, n304, n308, n313, n318, n323, n328, n333, n338, + n343, n348, n353, n358, n363, n368, n373, n378, n383, n388, n393, n398, + n403, n408, n413, n418, n423, n428, n433, n438, n443, n448, n453, n458, + n463, n468, n473, n478, n483, n488, n493, n498, n503, n508, n513, n517, + n521, n526, n531, n535, n539, n544, n549, n554, n559, n564, n569, n574, + n579, n584, n589, n594, n599, n604, n609, n614, n619, n624, n629, n634, + n639, n644, n649, n654, n659, n664, n669, n674, n679, n684, n689, n694, + n699, n704, n709, n714, n719, n724, n729, n734, n739, n743, n747, n752, + n756, n760, n764, n769, n774, n779, n784, n789, n794, n799, n804, n809, + n814, n819, n824, n829, n834, n839, n844, n849, n854, n859, n864, n869, + n874, n879, n884, n889, n894, n899, n904, n909, n914, n919, n924, n929, + n934, n939, n944, n949, n954, n959, n964, n968, n972, n977, n981, n985, + n989, n994, n999, n1004, n1009, n1014, n1019, n1024, n1029, n1034, + n1039, n1044, n1049, n1054, n1059, n1064, n1069, n1074, n1079, n1084, + n1089, n1094, n1099, n1104, n1109, n1114, n1119, n1124, n1129, n1134, + n1139, n1144, n1149, n1154, n1159, n1164, n1169, n1174, n1179, n1183, + n1187, n1191, n1196, n1201, n1206, n1211, n1216, n1221, n1226, n1231, + n1236, n1241, n1246, n1251, n1256, n1261, n1266, n1271, n1276, n1281, + n1286, n1291, n1296, n1301, n1306, n1311, n1316, n1321, n1326, n1331, + n1336, n1341, n1346, n1351, n1356, n1361, n1366, n1371, n1376, n1381, + n1385, n1389, n1393, n1398, n1403, n1408, n1413, n1418, n1423, n1428, + n1433, n1438, n1443, n1448, n1453, n1458, n1463, n1468, n1473, n1478, + n1483, n1488, n1493, n1498, n1503, n1508, n1513, n1518, n1523, n1528, + n1533, n1538, n1543, n1548, n1553, n1558, n1563, n1568, n1573, n1578, + n1583, n1587, n1591, n1595, n1600, n1605, n1610, n1615, n1620, n1625, + n1630, n1635, n1640, n1645, n1650, n1655, n1660, n1665, n1670, n1675, + n1680, n1685, n1690, n1695, n1700, n1705, n1710, n1715, n1720, n1725, + n1730, n1735, n1740, n1745, n1750, n1755, n1760, n1765, n1770, n1775, + n1780, n1785, n1790, n1794, n1798, n1802, n1806, n1811, n1816, n1821, + n1826, n1831, n1836, n1841, n1846, n1851, n1856, n1861, n1866, n1871, + n1876, n1881, n1886, n1891, n1896, n1901, n1906, n1911, n1916, n1921, + n1926, n1931, n1936, n1941, n1946, n1951, n1956, n1961, n1966, n1971, + n1976, n1981, n1986, n1991, n1996, n2001, n2006, n2011, n2016, n2020, + n2025, n2030, n2035, n2040, n2045, n2050, n2055, n2060, n2065, n2070, + n2075, n2080, n2085, n2090, n2095, n2100, n2105, n2110, n2115, n2120, + n2125, n2130, n2135, n2140, n2145, n2150, n2155, n2160, n2165, n2170, + n2175, n2180, n2184, n2188, n2193, n2198, n2203, n2208, n2213, n2218, + n2223, n2228, n2233, n2238, n2243, n2248, n2253, n2258, n2263, n2267, + n2271, n2276, n2281, n2286, n2291, n2296, n2301, n2306, n2311, n2316, + n2321, n2326, n2331, n2336, n2341, n2346, n2351, n2356, n2361, n2366, + n2371, n2376, n2381, n2386, n2391, n2396, n2401, n2406, n2411, n2416, + n2421, n2426, n2431, n2436, n2441, n2446, n2451, n2456, n2461, n2466, + n2471, n2476, n2481, n2486, n2491, n2496, n2501, n2506, n2511, n2516, + n2521, n2526, n2531, n2536, n2541, n2546, n2551, n2556, n2561, n2566, + n2571, n2576, n2581, n2586, n2591, n2596, n2601, n2606, n2611, n2616, + n2621, n2626, n2631, n2636, n2641, n2646, n2651, n2656, n2661, n2666, + n2670, n2674, n2679, n2684, n2689, n2694, n2698, n2702, n2707, n2712, + n2717, n2722, n2727, n2732, n2736, n2741, n2746, n2751, n2756, n2761, + n2766, n2770, n2775, n2780, n2785, n2789, n2793, n2798, n2803, n2808, + n2813, n2818, n2823, n2828, n2833, n2838, n2843, n2848, n2852, n2856, + n2861, n2866, n2871, n2876, n2881, n2886, n2891, n2896, n2901, n2906, + n2911, n2915, n2919, n2924, n2929, n2934, n2939, n2944, n2949, n2954, + n2959, n2964, n2969, n2974, n2978, n2982, n2987, n2992, n2997, n3002, + n3007, n3012, n3017, n3022, n3027, n3032, n3037, n3041, n3045, n3050, + n3055, n3060, n3065, n3070, n3075, n3080, n3085, n3090, n3095, n3100, + n3105, n3110, n3115, n3120, n3125, n3130, n3135, n3140, n3145, n3149, + n3154, n3158, n3163, n3168, n3173, n3178, n3183, n3188, n3193, n3198, + n3203, n3208, n3213, n3218, n3223, n3228, n3233, n3238, n3243, n3248, + n3253, n3258, n3263, n3267, n3271, n3275, n3280, n3285, n3290, n3295, + n3300, n3305, n3310, n3315, n3320, n3325, n3330, n3335, n3340, n3345, + n3350, n3355, n3360, n3365, n3370, n3375, n3380, n3385, n3389, n3393, + n3397, n3401, n3406, n3411, n3416, n3421, n3426, n3431, n3436, n3441, + n3446, n3451, n3456, n3461, n3466, n3471, n3476, n3481, n3486, n3491, + n3496, n3501, n3506, n3511, n3516, n3520, n3524, n3528, n3533, n3537, + n3541, n3546, n3551, n3556, n3561, n3566, n3571, n3576, n3581, n3586, + n3591, n3596, n3601, n3606, n3611, n3616, n3621, n3626, n3631, n3635, + n3639, n3643, n3648, n3652, n3656, n3661, n3666, n3671, n3676, n3681, + n3686, n3691, n3696, n3701, n3706, n3711, n3716, n3721, n3726, n3731, + n3736, n3741, n3746, n3750, n3754, n3758, n3763, n3768, n3772, n3777, + n3782, n3787, n3792, n3797, n3802, n3807, n3812, n3817, n3822, n3827, + n3832, n3837, n3842, n3847, n3852, n3856, n3860, n3864, n3869, n3874, + n3878, n3883, n3888, n3893, n3898, n3903, n3908, n3913, n3918, n3923, + n3928, n3933, n3938, n3943, n3948, n3953, n3957, n3962, n3967, n3972, + n3976, n3981, n3986, n3991, n3996, n4001, n4006, n4011, n4016, n4021, + n4026, n4031, n4036, n4041, n4046, n4051, n4056, n4061, n4066, n4071, + n4076, n4081, n4086, n4091, n4096, n4101, n4106, n4111, n4116, n4121, + n4126, n4131, n4136, n4141, n4146, n4150, n4155, n4160, n4165, n4169, + n4174, n4179, n4184, n4189, n4194, n4199, n4203, n4208, n4213, n4218, + n4223, n4227, n4232, n4237, n4242, n4247, n4251, n4256, n4261, n4265, + n4270, n4275, n4280, n4285, n4290, n4295, n4300, n4304, n4309, n4314, + n4319, n4324, n4328, n4333, n4338, n4343, n4348, n4353, n4358, n4363, + n4368, n4373, n4378, n4383, n4387, n4392, n4397, n4402, n4407, n4412, + n4417, n4422, n4427, n4432, n4437, n4442, n4447, n4452, n4457, n4462, + n4466, n4470, n4475, n4480, n4485, n4489, n4494, n4499, n4504, n4509, + n4514, n4518, n4523, n4528, n4533, n4537, n4542, n4547, n4552, n4557, + n4561, n4565, n4570, n4574, n4579, n4584, n4589, n4594, n4598; + assign pdata_8_8_ = \[17882] ? \[16959] : tin_pdata_8_8_; + assign pdata_0_0_ = \[17479] ? \[18337] : tin_pdata_0_0_; + assign pdata_7_7_ = \[17869] ? \[16907] : tin_pdata_7_7_; + assign pdata_2_2_ = \[18181] ? \[17323] : tin_pdata_2_2_; + assign pdata_9_9_ = \[18571] ? \[17765] : tin_pdata_9_9_; + assign pdata_1_1_ = \[18116] ? \[17258] : tin_pdata_1_1_; + assign pdata_4_4_ = \[18038] ? \[17193] : tin_pdata_4_4_; + assign pdata_10_10_ = \[17011] ? \[17921] : tin_pdata_10_10_; + assign pdata_3_3_ = \[17960] ? \[17128] : tin_pdata_3_3_; + assign pdata_6_6_ = \[17934] ? \[17063] : tin_pdata_6_6_; + assign pdata_15_15_ = \[17947] ? \[17076] : tin_pdata_15_15_; + assign pdata_11_11_ = \[17336] ? \[18194] : tin_pdata_11_11_; + assign pdata_14_14_ = \[18584] ? \[17778] : tin_pdata_14_14_; + assign pdata_12_12_ = \[17141] ? \[17973] : tin_pdata_12_12_; + assign pdata_5_5_ = \[17908] ? \[16998] : tin_pdata_5_5_; + assign pdata_13_13_ = \[18350] ? \[17492] : tin_pdata_13_13_; + assign n273 = n5632 | (pdata_2_2_ & n3696_1); + assign n278 = n5690 | n5687 | n5688; + assign n282 = n5694 | n5691 | n5692; + assign n286 = n5700 | n5698 | n5699; + assign n290 = n5703 | n5596 | n5597; + assign n295 = n5704 | n5593 | n5594; + assign n300 = n5715 | n5713 | n5714; + assign n304 = n5573 | n5575 | n5576 | n5727; + assign n308 = n5572 | (pdata_0_0_ & n3703); + assign n313 = n5571 | (pdata_11_11_ & n3703); + assign n318 = ~preset & (n3792_1 ? pdata_6_6_ : \[4385] ); + assign n323 = n5570 | (pdata_1_1_ & n3705); + assign n328 = n5569 | (pdata_12_12_ & n3705); + assign n333 = ~preset & (n3817_1 ? pdata_7_7_ : \[4430] ); + assign n338 = ~preset & (n3817_1 ? pdata_2_2_ : \[4445] ); + assign n343 = ~preset & (n3817_1 ? pdata_13_13_ : \[4460] ); + assign n348 = n5568 | (pdata_8_8_ & n3708); + assign n353 = n5567 | (pdata_3_3_ & n4504); + assign n358 = n5566 | (pdata_14_14_ & n4504); + assign n363 = n5564 | n5565; + assign n368 = n5562 | n5563; + assign n373 = n5560 | n5561; + assign n378 = ~preset & (n3813 ? pdata_5_5_ : \[4565] ); + assign n383 = ~preset & (n3813 ? pdata_0_0_ : \[4580] ); + assign n388 = ~preset & (n3813 ? pdata_11_11_ : \[4595] ); + assign n393 = n5559 | (pdata_6_6_ & n3711_1); + assign n398 = (n4160 & n3712) | (\[4625] & n3713); + assign n403 = (n4160 & n3714) | (\[4640] & n3713); + assign n408 = n5481 | n5482; + assign n413 = n5480 | (\[4670] & n3707); + assign n418 = n5478 | n5479; + assign n423 = n5477 | (\[4715] & n3717); + assign n428 = (\[4730] & n3717) | (n3718 & n3719); + assign n433 = n5461 | (n4547 & n3720); + assign n438 = n5460 | (\[4760] & n3710); + assign n443 = n5459 | (\[4775] & n3710); + assign n448 = n5457 | n5458; + assign n453 = (n3712 & n3723) | (\[4805] & n3722); + assign n458 = (n3714 & n3723) | (\[4820] & n3722); + assign n463 = ~preset & (n3825 ? n3724 : \[4835] ); + assign n468 = n5378 | (n3726_1 & n3727); + assign n473 = (n3728 & n3730) | (\[4865] & n3729); + assign n478 = n5342 | (n3730 & (~n3930 ^ n3931)); + assign n483 = n5341 | (n3731_1 & n3732); + assign n488 = (n3733 & n3735) | (\[4910] & n3734); + assign n493 = (\[4925] & n3722) | (n3723 & n3736_1); + assign n498 = (\[4940] & n3722) | (n3723 & n3737); + assign n503 = (n3724 & n3739) | (\[4955] & n3738); + assign n508 = n5340 | (pdata_1_1_ & n3696_1); + assign n513 = n5862 | n5859 | n5860; + assign n517 = n5868 | n5866 | n5867; + assign n521 = n5869 | n5319 | n5320; + assign n526 = n5870 | n5316 | n5317; + assign n531 = n5876 | n5874 | n5875; + assign n535 = n5298 | n5300 | n5301 | n5878; + assign n539 = n5297 | (pdata_1_1_ & n3703); + assign n544 = n5296 | (pdata_10_10_ & n3703); + assign n549 = n5295 | (pdata_2_2_ & n3705); + assign n554 = n5294 | (pdata_11_11_ & n3705); + assign n559 = ~preset & (n3817_1 ? pdata_8_8_ : \[5135] ); + assign n564 = ~preset & (n3817_1 ? pdata_1_1_ : \[5150] ); + assign n569 = ~preset & (n3817_1 ? pdata_14_14_ : \[5165] ); + assign n574 = n5293 | (pdata_7_7_ & n3708); + assign n579 = n5292 | (pdata_4_4_ & n4504); + assign n584 = n5291 | (pdata_13_13_ & n4504); + assign n589 = n5289 | n5290; + assign n594 = n5287 | n5288; + assign n599 = n5285 | n5286; + assign n604 = ~preset & (n3813 ? pdata_4_4_ : \[5270] ); + assign n609 = ~preset & (n3813 ? pdata_1_1_ : \[5285] ); + assign n614 = ~preset & (n3813 ? pdata_10_10_ : \[5300] ); + assign n619 = n5284 | (pdata_7_7_ & n3711_1); + assign n624 = n5283 | (n4160 & (n3893_1 ^ n3894)); + assign n629 = n5282 | (\[5345] & n3713); + assign n634 = n5281 | (n3714 & n3715); + assign n639 = n5280 | (\[5375] & n3707); + assign n644 = n5279 | (n3716_1 & (n3893_1 ^ n3894)); + assign n649 = n5278 | (n3716_1 & n3720); + assign n654 = n5277 | (\[5420] & n3717); + assign n659 = (\[5435] & n3717) | (n3718 & n3740); + assign n664 = n5275 | n5276; + assign n669 = n5274 | (n4106 & n3720); + assign n674 = (n3709 & n3740) | (\[5480] & n3710); + assign n679 = n5273 | (n3721_1 & n3741_1); + assign n684 = n5272 | (\[5510] & n3722); + assign n689 = n5271 | (\[5525] & n3722); + assign n694 = ~preset & (n3825 ? n3742 : \[5540] ); + assign n699 = n5270 | (n3727 & n3743); + assign n704 = (\[5570] & n3729) | (n3730 & n3733); + assign n709 = n5269 | (n3732 & n3744); + assign n714 = (n3728 & n3735) | (\[5615] & n3734); + assign n719 = n5268 | (n4081 & n3744); + assign n724 = (\[5645] & n3722) | (n3723 & n3745); + assign n729 = (\[5660] & n3738) | (n3739 & n3746_1); + assign n734 = n5267 | (pdata_0_0_ & n3696_1); + assign n739 = n5882 | n5879 | n5880; + assign n743 = n5888 | n5886 | n5887; + assign n747 = n5889 | n5246 | n5247; + assign n752 = n5895 | n5893 | n5894; + assign n756 = n5901 | n5899 | n5900; + assign n760 = n5214 | n5216 | n5217 | n5903; + assign n764 = n5213 | (pdata_2_2_ & n3703); + assign n769 = ~preset & (n3792_1 ? pdata_4_4_ : \[5795] ); + assign n774 = ~preset & (n3792_1 ? pdata_8_8_ : \[5810] ); + assign n779 = ~preset & (n3817_1 ? pdata_9_9_ : \[5825] ); + assign n784 = ~preset & (n3817_1 ? pdata_4_4_ : \[5840] ); + assign n789 = ~preset & (n3817_1 ? pdata_11_11_ : \[5855] ); + assign n794 = n5212 | (pdata_6_6_ & n3708); + assign n799 = n5211 | (pdata_5_5_ & n4504); + assign n804 = n5209 | n5210; + assign n809 = n5207 | n5208; + assign n814 = n5205 | n5206; + assign n819 = n5203 | n5204; + assign n824 = ~preset & (n3813 ? pdata_7_7_ : \[5960] ); + assign n829 = ~preset & (n3813 ? pdata_14_14_ : \[5975] ); + assign n834 = ~preset & (n3813 ? pdata_9_9_ : \[5990] ); + assign n839 = n5202 | (pdata_8_8_ & n3711_1); + assign n844 = (n4160 & n3747) | (\[6020] & n3713); + assign n849 = n5201 | (\[6035] & n3713); + assign n854 = n5199 | n5200; + assign n859 = n5198 | (\[6065] & n3707); + assign n864 = (n3706_1 & n3740) | (\[6080] & n3707); + assign n869 = n5196 | n5197; + assign n874 = (\[6110] & n3717) | (n3718 & n3741_1); + assign n879 = n5195 | (n4547 & (n3893_1 ^ n3894)); + assign n884 = n5193 | n5194; + assign n889 = n5191 | n5192; + assign n894 = n5190 | (\[6170] & n3710); + assign n899 = n5188 | n5189; + assign n904 = (\[6200] & n3722) | (n3723 & n3747); + assign n909 = (\[6215] & n3722) | (n3723 & n3740); + assign n914 = ~preset & (n3825 ? n3728 : \[6230] ); + assign n919 = n5187 | (n3742 & n3748); + assign n924 = n5186 | (n3727 & n3736_1); + assign n929 = n5185 | (n3732 & n3749); + assign n934 = n5184 | (n3732 & n3743); + assign n939 = (\[6305] & n3734) | (n3735 & n3736_1); + assign n944 = n5183 | (n3750_1 & (~n3930 ^ n3931)); + assign n949 = (\[6335] & n3722) | (n3723 & n3752); + assign n954 = (\[6350] & n3738) | (n3739 & n3744); + assign n959 = n5182 | (n3739 & (~n3930 ^ n3931)); + assign n964 = n5907 | n5904 | n5905; + assign n968 = n5911 | n5908 | n5909; + assign n972 = n5912 | n5159 | n5160; + assign n977 = n5918 | n5916 | n5917; + assign n981 = n5924 | n5922 | n5923; + assign n985 = n5127 | n5129 | n5130 | n5926; + assign n989 = n5126 | (pdata_12_12_ & n3703); + assign n994 = ~preset & (n3792_1 ? pdata_5_5_ : \[6485] ); + assign n999 = ~preset & (n3792_1 ? pdata_7_7_ : \[6500] ); + assign n1004 = ~preset & (n3817_1 ? pdata_10_10_ : \[6515] ); + assign n1009 = ~preset & (n3817_1 ? pdata_3_3_ : \[6530] ); + assign n1014 = ~preset & (n3817_1 ? pdata_12_12_ : \[6545] ); + assign n1019 = n5125 | (pdata_5_5_ & n3708); + assign n1024 = n5124 | (pdata_6_6_ & n4504); + assign n1029 = n5123 | (pdata_15_15_ & n4504); + assign n1034 = n5121 | n5122; + assign n1039 = n5119 | n5120; + assign n1044 = ~preset & (n3813 ? pdata_6_6_ : \[6635] ); + assign n1049 = ~preset & (n3813 ? pdata_15_15_ : \[6650] ); + assign n1054 = ~preset & (n3813 ? pdata_8_8_ : \[6665] ); + assign n1059 = n5118 | (pdata_9_9_ & n3711_1); + assign n1064 = n5117 | (\[6695] & n3713); + assign n1069 = n5116 | (\[6710] & n3713); + assign n1074 = n5115 | (n3715 & n3740); + assign n1079 = (n3706_1 & n3741_1) | (\[6740] & n3707); + assign n1084 = (n3706_1 & n3719) | (\[6755] & n3707); + assign n1089 = n5113 | n5114; + assign n1094 = n5112 | (\[6785] & n3717); + assign n1099 = n5110 | n5111; + assign n1104 = n5108 | n5109; + assign n1109 = (n3709 & n3747) | (\[6845] & n3710); + assign n1114 = (n3709 & n3714) | (\[6860] & n3710); + assign n1119 = n5107 | (\[6875] & n3722); + assign n1124 = n5106 | (\[6890] & n3722); + assign n1129 = ~preset & (n3825 ? n3746_1 : \[6905] ); + assign n1134 = n5105 | (n3744 & n3748); + assign n1139 = n5104 | (n3727 & n3749); + assign n1144 = n5103 | (n3732 & n3736_1); + assign n1149 = n5102 | (n3726_1 & n3732); + assign n1154 = (\[6980] & n3734) | (n3735 & n3753); + assign n1159 = (n3746_1 & n3750_1) | (\[6995] & n3751); + assign n1164 = n5101 | (n3723 & (~n3930 ^ n3931)); + assign n1169 = (\[7025] & n3738) | (n3739 & n3742); + assign n1174 = n5927 | n5098 | n5099; + assign n1179 = n5933 | n5931 | n5932; + assign n1183 = n5939 | n5937 | n5938; + assign n1187 = n5066 | n5068 | n5069 | n5941; + assign n1191 = n5065 | (pdata_7_7_ & n3703); + assign n1196 = ~preset & (n3792_1 ? pdata_2_2_ : \[7130] ); + assign n1201 = ~preset & (n3817_1 ? pdata_11_11_ : \[7145] ); + assign n1206 = ~preset & (n3817_1 ? pdata_6_6_ : \[7160] ); + assign n1211 = n5064 | (pdata_1_1_ & n3708); + assign n1216 = n5063 | (pdata_12_12_ & n3708); + assign n1221 = n5062 | (pdata_15_15_ & n3708); + assign n1226 = n5061 | (pdata_10_10_ & n4504); + assign n1231 = n5059 | n5060; + assign n1236 = n5057 | n5058; + assign n1241 = ~preset & (n3813 ? pdata_9_9_ : \[7265] ); + assign n1246 = ~preset & (n3813 ? pdata_4_4_ : \[7280] ); + assign n1251 = ~preset & (n3813 ? pdata_15_15_ : \[7295] ); + assign n1256 = n5056 | (pdata_2_2_ & n3711_1); + assign n1261 = n5055 | (pdata_13_13_ & n3711_1); + assign n1266 = n5054 | (\[7340] & n3713); + assign n1271 = n5053 | (n3715 & n3719); + assign n1276 = (n3706_1 & n3720) | (\[7370] & n3707); + assign n1281 = n5052 | (n3716_1 & n3747); + assign n1286 = n5051 | (n3716_1 & n3740); + assign n1291 = n5050 | (n3718 & (n3893_1 ^ n3894)); + assign n1296 = n5049 | (\[7430] & n3717); + assign n1301 = n5047 | n5048; + assign n1306 = n5046 | (n4106 & n3714); + assign n1311 = (n3709 & n3741_1) | (\[7475] & n3710); + assign n1316 = n5045 | (n3721_1 & (n3893_1 ^ n3894)); + assign n1321 = n5043 | n5044; + assign n1326 = n5042 | (\[7520] & n3722); + assign n1331 = ~preset & (n3825 ? n3753 : \[7535] ); + assign n1336 = n5041 | (n3731_1 & n3748); + assign n1341 = n5040 | (n3727 & n3733); + assign n1346 = n5039 | (n3727 & n3752); + assign n1351 = (\[7595] & n3729) | (n3730 & n3744); + assign n1356 = (n3724 & n3750_1) | (\[7625] & n3751); + assign n1361 = n5038 | (n4081 & n3749); + assign n1366 = n5037 | (n4081 & n3743); + assign n1371 = (\[7670] & n3722) | (n3723 & n3746_1); + assign n1376 = n5942 | n5034 | n5035; + assign n1381 = n5948 | n5946 | n5947; + assign n1385 = n5016 | n5018 | n5019 | n5950; + assign n1389 = n5012 | n5014 | n5015 | n5952; + assign n1393 = n5011 | (pdata_6_6_ & n3703); + assign n1398 = ~preset & (n3792_1 ? pdata_3_3_ : \[7760] ); + assign n1403 = ~preset & (n3817_1 ? pdata_12_12_ : \[7775] ); + assign n1408 = ~preset & (n3817_1 ? pdata_5_5_ : \[7790] ); + assign n1413 = n5010 | (pdata_2_2_ & n3708); + assign n1418 = n5009 | (pdata_11_11_ & n3708); + assign n1423 = n5008 | (pdata_0_0_ & n4504); + assign n1428 = n5007 | (pdata_9_9_ & n4504); + assign n1433 = n5005 | n5006; + assign n1438 = n5003 | n5004; + assign n1443 = ~preset & (n3813 ? pdata_8_8_ : \[7895] ); + assign n1448 = ~preset & (n3813 ? pdata_5_5_ : \[7910] ); + assign n1453 = ~preset & (n3813 ? pdata_14_14_ : \[7925] ); + assign n1458 = n5002 | (pdata_3_3_ & n3711_1); + assign n1463 = n5001 | (pdata_12_12_ & n3711_1); + assign n1468 = (n4160 & n3720) | (\[7970] & n3713); + assign n1473 = n5000 | (\[8000] & n3707); + assign n1478 = n4998 | n4999; + assign n1483 = n4996 | n4997; + assign n1488 = (n3712 & n3718) | (\[8045] & n3717); + assign n1493 = n4995 | (\[8060] & n3717); + assign n1498 = n4994 | (n4547 & n3741_1); + assign n1503 = n4992 | n4993; + assign n1508 = n4991 | (\[8105] & n3710); + assign n1513 = n4990 | (n3712 & n3721_1); + assign n1518 = n4988 | n4989; + assign n1523 = n4987 | (n3719 & n3721_1); + assign n1528 = ~preset & (n3825 ? n3733 : \[8165] ); + assign n1533 = n4986 | (n3726_1 & n3748); + assign n1538 = n4985 | (n3727 & n3753); + assign n1543 = n4984 | (n3727 & (~n3930 ^ n3931)); + assign n1548 = (\[8225] & n3729) | (n3730 & n3742); + assign n1553 = (\[8240] & n3734) | (n3735 & n3749); + assign n1558 = (n3742 & n3750_1) | (\[8255] & n3751); + assign n1563 = n4983 | (n4081 & n3737); + assign n1568 = (\[8300] & n3722) | (n3723 & n3728); + assign n1573 = (\[8315] & n3738) | (n3739 & n3752); + assign n1578 = n5953 | n4980 | n4981; + assign n1583 = n5959 | n5957 | n5958; + assign n1587 = n4962 | n4964 | n4965 | n5961; + assign n1591 = n4958 | n4960 | n4961 | n5963; + assign n1595 = n4957 | (pdata_9_9_ & n3703); + assign n1600 = ~preset & (n3792_1 ? pdata_0_0_ : \[8405] ); + assign n1605 = ~preset & (n3817_1 ? pdata_13_13_ : \[8420] ); + assign n1610 = ~preset & (n3817_1 ? pdata_8_8_ : \[8435] ); + assign n1615 = ~preset & (n3817_1 ? pdata_15_15_ : \[8450] ); + assign n1620 = n4956 | (pdata_10_10_ & n3708); + assign n1625 = n4955 | (pdata_1_1_ & n4504); + assign n1630 = n4954 | (pdata_12_12_ & n4504); + assign n1635 = n4952 | n4953; + assign n1640 = ~preset & (n3813 ? pdata_0_0_ : \[8525] ); + assign n1645 = ~preset & (n3813 ? pdata_11_11_ : \[8540] ); + assign n1650 = ~preset & (n3813 ? pdata_2_2_ : \[8555] ); + assign n1655 = ~preset & (n3813 ? pdata_13_13_ : \[8570] ); + assign n1660 = n4951 | (pdata_4_4_ & n3711_1); + assign n1665 = n4950 | (pdata_15_15_ & n3711_1); + assign n1670 = (n4160 & n3741_1) | (\[8615] & n3713); + assign n1675 = n4949 | (n3706_1 & (n3893_1 ^ n3894)); + assign n1680 = n4948 | (\[8645] & n3707); + assign n1685 = n4947 | (n3712 & n3716_1); + assign n1690 = n4946 | (n3714 & n3716_1); + assign n1695 = n4945 | (\[8690] & n3717); + assign n1700 = n4944 | (\[8705] & n3717); + assign n1705 = n4943 | (n4547 & n3747); + assign n1710 = n4942 | (n4106 & n3740); + assign n1715 = n4941 | (\[8750] & n3710); + assign n1720 = (n3709 & n3719) | (\[8765] & n3710); + assign n1725 = n4940 | (n3720 & n3721_1); + assign n1730 = n4939 | (\[8810] & n3722); + assign n1735 = n4938 | (n3743 & n3748); + assign n1740 = n4937 | (n3727 & n3746_1); + assign n1745 = n4936 | (n3727 & n3737); + assign n1750 = (n3724 & n3730) | (\[8870] & n3729); + assign n1755 = (\[8885] & n3729) | (n3730 & n3745); + assign n1760 = n4935 | (n3732 & n3742); + assign n1765 = (n3744 & n3750_1) | (\[8915] & n3751); + assign n1770 = n4934 | (n4081 & n3753); + assign n1775 = n4933 | (n4081 & n3731_1); + assign n1780 = (\[8960] & n3722) | (n3723 & n3733); + assign n1785 = (n3728 & n3739) | (\[8975] & n3738); + assign n1790 = n5969 | n5967 | n5968; + assign n1794 = n5975 | n5973 | n5974; + assign n1798 = n4901 | n4903 | n4904 | n5977; + assign n1802 = n4897 | n4899 | n4900 | n5979; + assign n1806 = n4896 | (pdata_8_8_ & n3703); + assign n1811 = ~preset & (n3792_1 ? pdata_1_1_ : \[9065] ); + assign n1816 = ~preset & (n3817_1 ? pdata_14_14_ : \[9080] ); + assign n1821 = ~preset & (n3817_1 ? pdata_7_7_ : \[9095] ); + assign n1826 = n4895 | (pdata_0_0_ & n3708); + assign n1831 = n4894 | (pdata_9_9_ & n3708); + assign n1836 = n4893 | (pdata_2_2_ & n4504); + assign n1841 = n4892 | (pdata_11_11_ & n4504); + assign n1846 = n4890 | n4891; + assign n1851 = ~preset & (n3813 ? pdata_1_1_ : \[9185] ); + assign n1856 = ~preset & (n3813 ? pdata_10_10_ : \[9200] ); + assign n1861 = ~preset & (n3813 ? pdata_3_3_ : \[9215] ); + assign n1866 = ~preset & (n3813 ? pdata_12_12_ : \[9230] ); + assign n1871 = n4889 | (pdata_5_5_ & n3711_1); + assign n1876 = n4888 | (pdata_14_14_ & n3711_1); + assign n1881 = n4887 | (\[9275] & n3713); + assign n1886 = (n3706_1 & n3712) | (\[9290] & n3707); + assign n1891 = n4886 | (\[9305] & n3707); + assign n1896 = n4884 | n4885; + assign n1901 = n4882 | n4883; + assign n1906 = (\[9350] & n3717) | (n3718 & n3747); + assign n1911 = (n3714 & n3718) | (\[9365] & n3717); + assign n1916 = n4880 | n4881; + assign n1921 = n4879 | (n4106 & n3719); + assign n1926 = n4878 | (\[9410] & n3710); + assign n1931 = n4876 | n4877; + assign n1936 = n4875 | (n3723 & (n3893_1 ^ n3894)); + assign n1941 = (n3720 & n3723) | (\[9470] & n3722); + assign n1946 = ~preset & (n3825 ? n3736_1 : \[9485] ); + assign n1951 = n4874 | (n3737 & n3748); + assign n1956 = n4873 | (n3727 & n3728); + assign n1961 = n4872 | (n3727 & n3745); + assign n1966 = (\[9545] & n3729) | (n3730 & n3746_1); + assign n1971 = (\[9560] & n3729) | (n3730 & n3752); + assign n1976 = n4871 | (n3724 & n3732); + assign n1981 = (n3731_1 & n3750_1) | (\[9590] & n3751); + assign n1986 = n4870 | (n4081 & n3736_1); + assign n1991 = n4869 | (n4081 & n3726_1); + assign n1996 = (\[9635] & n3722) | (n3723 & n3753); + assign n2001 = (\[9650] & n3722) | (n3723 & n3743); + assign n2006 = n4868 | (pdata_1_1_ & n3754_1); + assign n2011 = n4867 | (pdata_12_12_ & n3754_1); + assign n2016 = n4865 | (n3755 & n3756) | n4866; + assign n2020 = ~preset & (n3813 ? pdata_2_2_ : \[9710] ); + assign n2025 = n4864 | (\[9725] & n3707); + assign n2030 = n4863 | (\[9740] & n3707); + assign n2035 = n4862 | (\[9770] & n3710); + assign n2040 = n4860 | n4861; + assign n2045 = n4859 | (n3745 & n3748); + assign n2050 = n4858 | (n3727 & n3742); + assign n2055 = (\[9830] & n3729) | (n3730 & n3736_1); + assign n2060 = (\[9845] & n3729) | (n3730 & n3737); + assign n2065 = (n3726_1 & n3750_1) | (\[9860] & n3751); + assign n2070 = n4857 | (n4081 & n3728); + assign n2075 = n4856 | (n4081 & (~n3930 ^ n3931)); + assign n2080 = (\[9905] & n3722) | (n3723 & n3731_1); + assign n2085 = (n3733 & n3739) | (\[9920] & n3738); + assign n2090 = n4855 | (pdata_0_0_ & n3754_1); + assign n2095 = n4854 | (pdata_6_6_ & n3757); + assign n2100 = ~preset & (n3813 ? pdata_12_12_ : \[9980] ); + assign n2105 = (n3706_1 & n3747) | (\[9995] & n3707); + assign n2110 = (n3706_1 & n3714) | (\[10010] & n3707); + assign n2115 = n4853 | (n3709 & (n3893_1 ^ n3894)); + assign n2120 = (n3709 & n3720) | (\[10040] & n3710); + assign n2125 = n4852 | (n3721_1 & n3740); + assign n2130 = n4851 | (n3748 & n3752); + assign n2135 = n4850 | (n3724 & n3727); + assign n2140 = (\[10100] & n3729) | (n3730 & n3753); + assign n2145 = (\[10115] & n3729) | (n3730 & n3743); + assign n2150 = (n3743 & n3750_1) | (\[10130] & n3751); + assign n2155 = n4849 | (n4081 & n3733); + assign n2160 = (\[10175] & n3722) | (n3723 & n3744); + assign n2165 = (\[10190] & n3738) | (n3739 & n3745); + assign n2170 = n4848 | (pdata_10_10_ & n3754_1); + assign n2175 = n4847 | (pdata_5_5_ & n3757); + assign n2180 = n4846 | (\[12200] & (n5627 | n5628)); + assign n2184 = n4844 | (n3756 & n3758_1) | n4845; + assign n2188 = ~preset & (n3813 ? pdata_6_6_ : \[10265] ); + assign n2193 = n4842 | n4843; + assign n2198 = (n3709 & n3712) | (\[10310] & n3710); + assign n2203 = n4840 | n4841; + assign n2208 = n4838 | n4839; + assign n2213 = n4837 | (n3748 & (~n3930 ^ n3931)); + assign n2218 = n4836 | (n3727 & n3731_1); + assign n2223 = (n3726_1 & n3730) | (\[10400] & n3729); + assign n2228 = (n3737 & n3750_1) | (\[10415] & n3751); + assign n2233 = n4835 | (n4081 & n3724); + assign n2238 = n4834 | (n4081 & n3745); + assign n2243 = (\[10460] & n3722) | (n3723 & n3742); + assign n2248 = n4833 | (pdata_2_2_ & n3754_1); + assign n2253 = n4832 | (pdata_11_11_ & n3754_1); + assign n2258 = n4831 | (pdata_4_4_ & n3757); + assign n2263 = n4830 | (\[12080] & (n5627 | n5628)); + assign n2267 = n4828 | (n3756 & n3759) | n4829; + assign n2271 = n4827 | (pdata_0_0_ & n3711_1); + assign n2276 = n4826 | (n3716_1 & n3741_1); + assign n2281 = n4825 | (n3716_1 & n3719); + assign n2286 = n4824 | (\[10595] & n3710); + assign n2291 = n4823 | (n3721_1 & n3747); + assign n2296 = n4822 | (n3714 & n3721_1); + assign n2301 = n4821 | (n3727 & n3744); + assign n2306 = (\[10670] & n3729) | (n3730 & n3749); + assign n2311 = (\[10685] & n3729) | (n3730 & n3731_1); + assign n2316 = (n3745 & n3750_1) | (\[10700] & n3751); + assign n2321 = n4820 | (n4081 & n3746_1); + assign n2326 = n4819 | (n4081 & n3752); + assign n2331 = (\[10745] & n3722) | (n3723 & n3724); + assign n2336 = n4818 | (pdata_13_13_ & n3696_1); + assign n2341 = n4817 | (pdata_8_8_ & n3754_1); + assign n2346 = n4816 | (pdata_3_3_ & n3757); + assign n2351 = n4815 | (pdata_1_1_ & n3760); + assign n2356 = n4814 | (pdata_12_12_ & n3760); + assign n2361 = n4813 | (pdata_10_10_ & n3711_1); + assign n2366 = n4812 | (\[10865] & n3717); + assign n2371 = n4810 | n4811; + assign n2376 = n4809 | (\[10895] & n3722); + assign n2381 = ~preset & (n3825 ? n3726_1 : \[10925] ); + assign n2386 = n4808 | (n3732 & n3753); + assign n2391 = n4807 | (n3732 & n3745); + assign n2396 = (\[10970] & n3734) | (n3735 & n3742); + assign n2401 = (n3750_1 & n3752) | (\[10985] & n3751); + assign n2406 = (n3726_1 & n3739) | (\[11015] & n3738); + assign n2411 = n4806 | (pdata_12_12_ & n3696_1); + assign n2416 = n4805 | (pdata_9_9_ & n3754_1); + assign n2421 = n4804 | (pdata_2_2_ & n3757); + assign n2426 = n4803 | (pdata_7_7_ & n3757); + assign n2431 = n4802 | (pdata_13_13_ & n3760); + assign n2436 = n4801 | (\[11120] & n3713); + assign n2441 = (\[11135] & n3717) | (n3718 & n3720); + assign n2446 = n4800 | (n4547 & n3712); + assign n2451 = (\[11165] & n3722) | (n3723 & n3741_1); + assign n2456 = (n3719 & n3723) | (\[11180] & n3722); + assign n2461 = n4799 | (n3732 & n3733); + assign n2466 = n4798 | (n3732 & n3737); + assign n2471 = (\[11225] & n3734) | (n3735 & n3744); + assign n2476 = n4797 | (n4081 & n3742); + assign n2481 = (\[11255] & n3738) | (n3739 & n3749); + assign n2486 = (n3731_1 & n3739) | (\[11270] & n3738); + assign n2491 = n4796 | (pdata_15_15_ & n3696_1); + assign n2496 = n4795 | (pdata_6_6_ & n3754_1); + assign n2501 = n4794 | (pdata_1_1_ & n3757); + assign n2506 = n4793 | (pdata_8_8_ & n3757); + assign n2511 = n4792 | (pdata_3_3_ & n3760); + assign n2516 = (n4160 & n3740) | (\[11375] & n3713); + assign n2521 = n4790 | n4791; + assign n2526 = n4789 | (\[11405] & n3722); + assign n2531 = ~preset & (n3825 ? n3744 : \[11420] ); + assign n2536 = n4788 | (n3728 & n3732); + assign n2541 = n4787 | (n3732 & (~n3930 ^ n3931)); + assign n2546 = (\[11465] & n3734) | (n3735 & n3746_1); + assign n2551 = (\[11480] & n3722) | (n3723 & n3749); + assign n2556 = (n3736_1 & n3739) | (\[11495] & n3738); + assign n2561 = (n3737 & n3739) | (\[11510] & n3738); + assign n2566 = n4786 | (pdata_14_14_ & n3696_1); + assign n2571 = n4785 | (pdata_7_7_ & n3754_1); + assign n2576 = n4784 | (pdata_0_0_ & n3757); + assign n2581 = n4783 | (pdata_9_9_ & n3757); + assign n2586 = n4782 | (pdata_2_2_ & n3760); + assign n2591 = n4781 | (pdata_11_11_ & n3760); + assign n2596 = n4780 | (n4547 & n3714); + assign n2601 = ~preset & (n3825 ? n3749 : \[11630] ); + assign n2606 = ~preset & (n3825 ? n3731_1 : \[11645] ); + assign n2611 = n4779 | (n3732 & n3746_1); + assign n2616 = n4778 | (n3732 & n3752); + assign n2621 = (n3724 & n3735) | (\[11690] & n3734); + assign n2626 = (\[11705] & n3722) | (n3723 & n3726_1); + assign n2631 = (\[11720] & n3738) | (n3739 & n3753); + assign n2636 = (\[11735] & n3738) | (n3739 & n3743); + assign n2641 = n4777 | (pdata_9_9_ & n3696_1); + assign n2646 = n4776 | (pdata_4_4_ & n3754_1); + assign n2651 = n4775 | (pdata_15_15_ & n3754_1); + assign n2656 = n4774 | (pdata_10_10_ & n3757); + assign n2661 = n4773 | (pdata_5_5_ & n3760); + assign n2666 = n4771 | (n3756 & n3761) | n4772; + assign n2670 = n5983 | n5980 | n5981; + assign n2674 = n4760 | (pdata_5_5_ & n3754_1); + assign n2679 = n4759 | (pdata_14_14_ & n3754_1); + assign n2684 = n4758 | (pdata_11_11_ & n3757); + assign n2689 = n4757 | (pdata_4_4_ & n3760); + assign n2694 = n4755 | (n3756 & n3762) | n4756; + assign n2698 = n4753 | n5985 | n5986 | n5987; + assign n2702 = (n3736_1 & n3764) | (\[12005] & n3763_1); + assign n2707 = n4743 | (pdata_11_11_ & n3696_1); + assign n2712 = n4742 | (pdata_13_13_ & n3754_1); + assign n2717 = n4741 | (pdata_12_12_ & n3757); + assign n2722 = n4740 | (pdata_7_7_ & n3760); + assign n2727 = n4739 | (pdata_14_14_ & n3760); + assign n2732 = n4737 | (n3756 & n3765) | n4738; + assign n2736 = (n3743 & n3764) | (\[12125] & n3763_1); + assign n2741 = n4736 | (pdata_10_10_ & n3696_1); + assign n2746 = n4735 | (pdata_3_3_ & n3754_1); + assign n2751 = n4734 | (pdata_13_13_ & n3757); + assign n2756 = n4733 | (pdata_6_6_ & n3760); + assign n2761 = n4732 | (pdata_15_15_ & n3760); + assign n2766 = n4730 | n5989 | n5990 | n5991; + assign n2770 = (n3728 & n3750_1) | (\[12245] & n3751); + assign n2775 = n4720 | (pdata_14_14_ & n3757); + assign n2780 = n4719 | (pdata_9_9_ & n3760); + assign n2785 = n4718 | (\[11090] & (n5627 | n5628)); + assign n2789 = n4716 | (n3756 & n3766) | n4717; + assign n2793 = n4715 | (\[12335] & n3704); + assign n2798 = n4713 | n4714; + assign n2803 = n4712 | (n3962 & n3719); + assign n2808 = n4711 | (n3736_1 & n3767); + assign n2813 = n4710 | (n3737 & n3767); + assign n2818 = n4709 | (n3724 & n3748); + assign n2823 = n4708 | (n3735 & (~n3930 ^ n3931)); + assign n2828 = (n3731_1 & n3764) | (\[12440] & n3763_1); + assign n2833 = (n3733 & n3750_1) | (\[12455] & n3751); + assign n2838 = n4707 | (pdata_15_15_ & n3757); + assign n2843 = n4706 | (pdata_8_8_ & n3760); + assign n2848 = n4705 | (\[10820] & (n5627 | n5628)); + assign n2852 = n4703 | (n3756 & n3768_1) | n4704; + assign n2856 = n4701 | n4702; + assign n2861 = (n4427 & n3741_1) | (\[12560] & n3704); + assign n2866 = n4700 | (n3962 & n3747); + assign n2871 = n4698 | n4699; + assign n2876 = n4697 | (n3749 & n3767); + assign n2881 = n4696 | (n3745 & n3767); + assign n2886 = n4695 | (n3746_1 & n3748); + assign n2891 = (\[12650] & n3734) | (n3735 & n3752); + assign n2896 = (n3726_1 & n3764) | (\[12665] & n3763_1); + assign n2901 = (n3750_1 & n3753) | (\[12680] & n3751); + assign n2906 = n4694 | (pdata_0_0_ & n3760); + assign n2911 = n4692 | (n3756 & n3769) | n4693; + assign n2915 = n4690 | (n3756 & n3770) | n4691; + assign n2919 = n4688 | n4689; + assign n2924 = n4686 | n4687; + assign n2929 = n4684 | n4685; + assign n2934 = n4682 | n4683; + assign n2939 = n4681 | (n3733 & n3767); + assign n2944 = n4680 | (n3726_1 & n3767); + assign n2949 = n4679 | (n3728 & n3748); + assign n2954 = (n3749 & n3764) | (\[12890] & n3763_1); + assign n2959 = (n3742 & n3764) | (\[12905] & n3763_1); + assign n2964 = (n3736_1 & n3750_1) | (\[12920] & n3751); + assign n2969 = n4678 | (pdata_10_10_ & n3760); + assign n2974 = n4676 | (n3756 & n3771) | n4677; + assign n2978 = n4674 | (n3756 & n3772_1) | n4675; + assign n2982 = n4672 | n4673; + assign n2987 = n4671 | (n3715 & (n3893_1 ^ n3894)); + assign n2992 = n4670 | (n3715 & n3720); + assign n2997 = n4668 | n4669; + assign n3002 = n4667 | (n3962 & n3740); + assign n3007 = n4666 | (n4106 & n3741_1); + assign n3012 = n4665 | (n3753 & n3767); + assign n3017 = n4664 | (n3743 & n3767); + assign n3022 = n4663 | (n3733 & n3748); + assign n3027 = (n3744 & n3764) | (\[13160] & n3763_1); + assign n3032 = (n3749 & n3750_1) | (\[13175] & n3751); + assign n3037 = n5995 | n5992 | n5993; + assign n3041 = n6001 | n5999 | n6000; + assign n3045 = n4644 | (pdata_3_3_ & n3703); + assign n3050 = n4643 | (pdata_14_14_ & n3703); + assign n3055 = ~preset & (n3792_1 ? pdata_14_14_ : \[13250] ); + assign n3060 = n4642 | (pdata_9_9_ & n3705); + assign n3065 = ~preset & (n3817_1 ? pdata_4_4_ : \[13280] ); + assign n3070 = n4640 | n4641; + assign n3075 = n4638 | n4639; + assign n3080 = n4636 | n4637; + assign n3085 = n4634 | n4635; + assign n3090 = (n4427 & n3747) | (\[13355] & n3704); + assign n3095 = (n4427 & n3740) | (\[13370] & n3704); + assign n3100 = n4632 | n4633; + assign n3105 = n4631 | (n3962 & (n3893_1 ^ n3894)); + assign n3110 = n4629 | n4630; + assign n3115 = n4627 | n4628; + assign n3120 = ~preset & (n3825 ? n3752 : \[13445] ); + assign n3125 = n4626 | (n3744 & n3767); + assign n3130 = n4625 | (n3748 & n3753); + assign n3135 = (\[13490] & n3734) | (n3735 & n3743); + assign n3140 = (n3746_1 & n3764) | (\[13505] & n3763_1); + assign n3145 = n6005 | n6002 | n6003; + assign n3149 = n6006 | n4612 | n4613; + assign n3154 = n4608 | n4610 | n4611 | n6008; + assign n3158 = n4607 | (pdata_15_15_ & n3703); + assign n3163 = ~preset & (n3792_1 ? pdata_13_13_ : \[13595] ); + assign n3168 = n4606 | (pdata_10_10_ & n3705); + assign n3173 = ~preset & (n3817_1 ? pdata_3_3_ : \[13625] ); + assign n3178 = n4604 | n4605; + assign n3183 = n4602 | n4603; + assign n3188 = n4600 | n4601; + assign n3193 = n4598_1 | n4599; + assign n3198 = n4597 | (\[13700] & n3713); + assign n3203 = n4596 | (\[13715] & n3704); + assign n3208 = (n4427 & n3719) | (\[13730] & n3704); + assign n3213 = n4594_1 | n4595; + assign n3218 = n4593 | (n3962 & n3714); + assign n3223 = n4591 | n4592; + assign n3228 = ~preset & (n3825 ? n3745 : \[13805] ); + assign n3233 = n4590 | (n3731_1 & n3767); + assign n3238 = n4589_1 | (n3736_1 & n3748); + assign n3243 = (n3726_1 & n3735) | (\[13850] & n3734); + assign n3248 = (n3724 & n3764) | (\[13865] & n3763_1); + assign n3253 = n4588 | (n3764 & (~n3930 ^ n3931)); + assign n3258 = n4587 | (pdata_8_8_ & n3696_1); + assign n3263 = n6014 | n6012 | n6013; + assign n3267 = n6018 | n4577 | n6016; + assign n3271 = n4560 | n4562 | n4563 | n6020; + assign n3275 = n4559 | (pdata_5_5_ & n3703); + assign n3280 = n4558 | (pdata_0_0_ & n3705); + assign n3285 = n4557_1 | (pdata_7_7_ & n3705); + assign n3290 = ~preset & (n3817_1 ? pdata_2_2_ : \[14000] ); + assign n3295 = n4556 | (pdata_13_13_ & n3708); + assign n3300 = n4555 | (pdata_8_8_ & n4504); + assign n3305 = n4553 | n4554; + assign n3310 = n4551 | n4552_1; + assign n3315 = n4549 | n4550; + assign n3320 = n4548 | (pdata_11_11_ & n3711_1); + assign n3325 = n4547_1 | (\[14105] & n3704); + assign n3330 = (n4427 & n3714) | (\[14120] & n3704); + assign n3335 = n4546 | (n3715 & n3741_1); + assign n3340 = n4544 | n4545; + assign n3345 = n4543 | (n3962 & n3720); + assign n3350 = n4542_1 | (n4106 & n3747); + assign n3355 = n4541 | (n3724 & n3767); + assign n3360 = n4540 | (n3748 & n3749); + assign n3365 = (\[14240] & n3734) | (n3735 & n3745); + assign n3370 = (n3733 & n3764) | (\[14255] & n3763_1); + assign n3375 = (n3752 & n3764) | (\[14270] & n3763_1); + assign n3380 = n4539 | (pdata_7_7_ & n3696_1); + assign n3385 = n4537_1 | n6022 | n6023 | n6024; + assign n3389 = n6028 | n4527 | n6026; + assign n3393 = n6032 | n4513 | n6030; + assign n3397 = n4496 | n4498 | n4499_1 | n6034; + assign n3401 = n4495 | (pdata_4_4_ & n3703); + assign n3406 = n4494_1 | (pdata_13_13_ & n3703); + assign n3411 = ~preset & (n3792_1 ? pdata_15_15_ : \[14390] ); + assign n3416 = n4493 | (pdata_8_8_ & n3705); + assign n3421 = ~preset & (n3817_1 ? pdata_1_1_ : \[14420] ); + assign n3426 = n4492 | (pdata_14_14_ & n3708); + assign n3431 = n4491 | (pdata_7_7_ & n4504); + assign n3436 = n4489_1 | n4490; + assign n3441 = n4487 | n4488; + assign n3446 = n4485_1 | n4486; + assign n3451 = n4484 | (pdata_1_1_ & n3711_1); + assign n3456 = n4483 | (\[14525] & n3704); + assign n3461 = n4482 | (\[14540] & n3704); + assign n3466 = n4480_1 | n4481; + assign n3471 = n4479 | (n3962 & n3712); + assign n3476 = n4477 | n4478; + assign n3481 = n4475_1 | n4476; + assign n3486 = n4474 | (n3725 & (~n3930 ^ n3931)); + assign n3491 = n4473 | (n3742 & n3767); + assign n3496 = (\[14660] & n3734) | (n3735 & n3737); + assign n3501 = (n3728 & n3764) | (\[14675] & n3763_1); + assign n3506 = (n3745 & n3764) | (\[14690] & n3763_1); + assign n3511 = n4472 | (pdata_6_6_ & n3696_1); + assign n3516 = n4470_1 | n6036 | n6037 | n6038; + assign n3520 = n6044 | n6042 | n6043; + assign n3524 = n6048 | n4451 | n6046; + assign n3528 = n6049 | n4435 | n4436; + assign n3533 = n6055 | n6053 | n6054; + assign n3537 = n4417_1 | n4419 | n4420 | n6057; + assign n3541 = ~preset & (n3792_1 ? pdata_10_10_ : \[14810] ); + assign n3546 = n4416 | (pdata_5_5_ & n3705); + assign n3551 = ~preset & (n3817_1 ? pdata_0_0_ : \[14840] ); + assign n3556 = ~preset & (n3817_1 ? pdata_9_9_ : \[14855] ); + assign n3561 = n4415 | (pdata_4_4_ & n3708); + assign n3566 = n4413 | n4414; + assign n3571 = n4411 | n4412_1; + assign n3576 = n4409 | n4410; + assign n3581 = ~preset & (n3813 ? pdata_7_7_ : \[14930] ); + assign n3586 = n4408 | (\[14960] & n3704); + assign n3591 = n4406 | n4407_1; + assign n3596 = n4404 | n4405; + assign n3601 = n4402_1 | n4403; + assign n3606 = n4401 | (n4106 & n3712); + assign n3611 = n4400 | (n3728 & n3767); + assign n3616 = n4399 | (n3767 & (~n3930 ^ n3931)); + assign n3621 = (n3737 & n3764) | (\[15065] & n3763_1); + assign n3626 = n4398 | (pdata_5_5_ & n3696_1); + assign n3631 = n4396 | n6059 | n6060 | n6061; + assign n3635 = n6067 | n6065 | n6066; + assign n3639 = n6071 | n4378_1 | n6069; + assign n3643 = n6072 | n4362 | n4363_1; + assign n3648 = n6078 | n6076 | n6077; + assign n3652 = n4344 | n4346 | n4347 | n6080; + assign n3656 = ~preset & (n3792_1 ? pdata_9_9_ : \[15185] ); + assign n3661 = n4343_1 | (pdata_6_6_ & n3705); + assign n3666 = n4342 | (pdata_15_15_ & n3705); + assign n3671 = ~preset & (n3817_1 ? pdata_10_10_ : \[15230] ); + assign n3676 = n4341 | (pdata_3_3_ & n3708); + assign n3681 = n4339 | n4340; + assign n3686 = n4337 | n4338_1; + assign n3691 = n4335 | n4336; + assign n3696 = ~preset & (n3813 ? pdata_13_13_ : \[15305] ); + assign n3701 = (n4160 & n3719) | (\[15320] & n3713); + assign n3706 = n4334 | (\[15335] & n3704); + assign n3711 = n4333_1 | (n3715 & n3747); + assign n3716 = n4331 | n4332; + assign n3721 = n4330 | (n4106 & (n3893_1 ^ n3894)); + assign n3726 = n4329 | (n3746_1 & n3767); + assign n3731 = n4328_1 | (n3752 & n3767); + assign n3736 = (n3753 & n3764) | (\[15425] & n3763_1); + assign n3741 = n4327 | (pdata_4_4_ & n3696_1); + assign n3746 = n4325 | n6082 | n6083 | n6084; + assign n3750 = n4315 | n6085 | n6086 | n6087; + assign n3754 = n6091 | n4302 | n6089; + assign n3758 = n6092 | n4286 | n4287; + assign n3763 = n6093 | n4283 | n4284; + assign n3768 = n6099 | n6097 | n6098; + assign n3772 = ~preset & (n3792_1 ? pdata_12_12_ : \[15545] ); + assign n3777 = n4268 | (pdata_3_3_ & n3705); + assign n3782 = n4267 | (pdata_14_14_ & n3705); + assign n3787 = ~preset & (n3817_1 ? pdata_5_5_ : \[15590] ); + assign n3792 = ~preset & (n3817_1 ? pdata_0_0_ : \[15605] ); + assign n3797 = n4265_1 | n4266; + assign n3802 = n4263 | n4264; + assign n3807 = n4261_1 | n4262; + assign n3812 = ~preset & (n3813 ? pdata_3_3_ : \[15665] ); + assign n3817 = (n4427 & n3712) | (\[15680] & n3704); + assign n3822 = n4260 | (\[15695] & n3704); + assign n3827 = n4258 | n4259; + assign n3832 = n4257 | (n4547 & n3719); + assign n3837 = ~preset & (n3825 ? n3737 : \[15755] ); + assign n3842 = (n3731_1 & n3735) | (\[15770] & n3734); + assign n3847 = n4256_1 | (pdata_3_3_ & n3696_1); + assign n3852 = n6103 | n6100 | n6101; + assign n3856 = n6109 | n6107 | n6108; + assign n3860 = n6113 | n4237_1 | n6111; + assign n3864 = n6114 | n4221 | n4222; + assign n3869 = n6115 | n4218_1 | n4219; + assign n3874 = n6121 | n6119 | n6120; + assign n3878 = ~preset & (n3792_1 ? pdata_11_11_ : \[15890] ); + assign n3883 = n4203_1 | (pdata_4_4_ & n3705); + assign n3888 = n4202 | (pdata_13_13_ & n3705); + assign n3893 = ~preset & (n3817_1 ? pdata_6_6_ : \[15935] ); + assign n3898 = ~preset & (n3817_1 ? pdata_15_15_ : \[15950] ); + assign n3903 = n4200 | n4201; + assign n3908 = n4198 | n4199_1; + assign n3913 = n4196 | n4197; + assign n3918 = n4194_1 | n4195; + assign n3923 = n4193 | (n4427 & (n3893_1 ^ n3894)); + assign n3928 = (n4427 & n3720) | (\[16040] & n3704); + assign n3933 = n4192 | (n3712 & n3715); + assign n3938 = n4191 | (n4547 & n3740); + assign n3943 = n4190 | (n3962 & n3741_1); + assign n3948 = ~preset & (n3825 ? n3743 : \[16100] ); + assign n3953 = n6140 | n6141; + assign n3957 = n4175 | n6142; + assign n3962 = n3876 & n3798 & ~preset & ~\[16920] ; + assign n3967 = n4141 | (n3798 & n3803 & n6143); + assign n3972 = n6149 | n6150; + assign n3976 = n4163 | n6151; + assign n3981 = \[16972] & ~preset & ~\[16920] ; + assign n3986 = ~\[18389] & ~preset & \[16985] ; + assign n3991 = n4161 | n6152; + assign n3996 = ~preset & (\[17011] | n3858 | n3859); + assign n4001 = ~preset & ~pdn; + assign n4006 = ~preset & ~\[17102] & (\[17037] | \[18025] ); + assign n4011 = \[17115] & ~preset & ~\[17050] ; + assign n4016 = n4159 | n6153; + assign n4021 = n4157 | n6154; + assign n4026 = \[17089] & ~preset & ~pdn; + assign n4031 = ~\[17102] & ~preset & \[17037] ; + assign n4036 = n4011 | (n3798 & n3826 & n6155); + assign n4041 = n4155_1 | n6156; + assign n4046 = ~preset & (\[17141] | n3858 | n3859); + assign n4051 = \[17154] & ~preset & ~\[17102] ; + assign n4056 = n3819 & n3798 & ~preset & ~\[17167] ; + assign n4061 = n4081 | (n3798 & n3827_1 & n6157); + assign n4066 = n4153 | n6158; + assign n4071 = n4096 | (n3798 & n3808 & n6159); + assign n4076 = \[17219] & ~preset & ~\[17050] ; + assign n4081 = ~\[17232] & ~preset & \[17180] ; + assign n4086 = ~preset & \[17245] & (~n3798 | ~n3811); + assign n4091 = n4151 | n6160; + assign n4096 = ~\[17271] & ~preset & \[17206] ; + assign n4101 = n4504 | (n3798 & n3802_1 & n6161); + assign n4106 = n3812_1 & n3798 & ~preset & ~\[17297] ; + assign n4111 = ~\[17388] & ~preset & \[17310] ; + assign n4116 = n4149 | n6162; + assign n4121 = ~preset & (\[17336] | n3858 | n3859); + assign n4126 = \[17349] & ~preset & ~\[17271] ; + assign n4131 = \[17362] & ~preset & ~\[17167] ; + assign n4136 = \[17375] & ~preset & ~\[17297] ; + assign n4141 = ~\[17388] & ~preset & \[16933] ; + assign n4146 = n6168 | n6169; + assign n4150 = \[17843] & ~preset & ~\[17414] ; + assign n4155 = ~preset & ~\[17700] & (\[17427] | \[17518] ); + assign n4160 = n5734 & n5729 & ~preset & n3798; + assign n4165 = n6175 | n6176; + assign n4169 = ~preset & (\[17479] | n3858 | n3859); + assign n4174 = n4127 | n6177; + assign n4179 = \[17505] & ~preset & ~\[17414] ; + assign n4184 = ~preset & ~\[17700] & (\[17518] | \[17817] ); + assign n4189 = n4126_1 | (\[17531] & n3784); + assign n4194 = ~preset & (n3877 ? ppeaki_7_7_ : \[17544] ); + assign n4199 = n6183 | n6184; + assign n4203 = ~preset & ~n3786 & (\[17570] | n3785); + assign n4208 = ~preset & ~\[17700] & (\[17583] | \[17648] ); + assign n4213 = n4114 | (~n3786 & n6195); + assign n4218 = ~preset & (n3877 ? ppeaki_6_6_ : \[17609] ); + assign n4223 = n6201 | n6202; + assign n4227 = ~preset & ~n3786 & (\[17570] | \[17635] ); + assign n4232 = ~preset & ~\[17700] & (\[17427] | \[17648] ); + assign n4237 = n6191 & n6188 & ~preset & n6187; + assign n4242 = ~preset & (n3877 ? ppeaki_5_5_ : \[17674] ); + assign n4247 = n6208 | n6209; + assign n4251 = \[18142] & ~preset & ~\[17700] ; + assign n4256 = ~preset & (n3877 ? ppeaki_4_4_ : \[17713] ); + assign n4261 = n6215 | n6216; + assign n4265 = \[17739] & ~preset & ~\[17700] ; + assign n4270 = n3784 & (\[17752] | (n3798 & n5729)); + assign n4275 = n4082 | n6217; + assign n4280 = n4080 | n6218; + assign n4285 = ~preset & ~\[17414] & (\[17791] | n3788); + assign n4290 = n3786 & ~preset & ~pdn; + assign n4295 = n4079 | (~preset & ~\[17700] & \[17817] ); + assign n4300 = n6229 | n6227 | n6228; + assign n4304 = ~preset & ~\[17414] & (\[17843] | (\[17791] & ~\[17843] )); + assign n4309 = ~preset & (\[17856] | n3790); + assign n4314 = ~preset & (\[17869] | n3858 | n3859); + assign n4319 = ~preset & (\[17882] | n3858 | n3859); + assign n4324 = n6254 | n6251 | n6252; + assign n4328 = ~preset & (\[17908] | n3858 | n3859); + assign n4333 = n4077 | n6255; + assign n4338 = ~preset & (\[17934] | n3858 | n3859); + assign n4343 = ~preset & (\[17947] | n3858 | n3859); + assign n4348 = ~preset & (\[17960] | n3858 | n3859); + assign n4353 = n4075 | n6256; + assign n4358 = ~preset & ~n3786 & (\[17635] | \[17986] ); + assign n4363 = ~preset & ~\[17700] & (\[17999] | \[18077] ); + assign n4368 = n4073 | n4074; + assign n4373 = n3779 & (\[18025] | (n3798 & n3806)); + assign n4378 = ~preset & (\[18038] | n3858 | n3859); + assign n4383 = ~preset & ~pdn & (\[17414] | n3786); + assign n4387 = n4072 | (~preset & ~pdn & \[18064] ); + assign n4392 = ~preset & ~\[17700] & (\[17583] | \[18077] ); + assign n4397 = n4070 | n4071_1; + assign n4402 = ~\[18168] & ~preset & \[18103] ; + assign n4407 = ~preset & (\[18116] | n3858 | n3859); + assign n4412 = n4068 | n4069; + assign n4417 = ~preset & ~\[17700] & (\[18142] | \[18220] ); + assign n4422 = n4066_1 | n4067; + assign n4427 = n5730 & n5729 & ~preset & n3798; + assign n4432 = ~preset & (\[18181] | n3858 | n3859); + assign n4437 = n4064 | n6258; + assign n4442 = ~preset & ~pdn & (\[18207] | n3790); + assign n4447 = ~preset & ~\[17700] & (\[17999] | \[18220] ); + assign n4452 = n4062 | n4063; + assign n4457 = \[18246] & ~preset & ~\[17453] ; + assign n4462 = n6264 | n6265; + assign n4466 = n4050 | n4251 | n4049; + assign n4470 = n4048 | (n3798 & n3800 & n6266); + assign n4475 = ~\[18376] & ~preset & \[18298] ; + assign n4480 = ~preset & ~\[18389] & (\[18311] | \[18506] ); + assign n4485 = n6272 | n6273; + assign n4489 = n4035 | n6274; + assign n4494 = ~preset & (\[18350] | n3858 | n3859); + assign n4499 = ~preset & ~\[18415] & (\[18363] | (\[18285] & ~\[18363] )); + assign n4504 = ~\[18376] & ~preset & \[17284] ; + assign n4509 = ~\[18389] & ~preset & \[18311] ; + assign n4514 = n6280 | n6281; + assign n4518 = ~\[18415] & ~preset & \[18363] ; + assign n4523 = ~\[18493] & ~preset & \[18428] ; + assign n4528 = \[18441] & ~preset & ~\[17232] ; + assign n4533 = n6287 | n6288; + assign n4537 = n4013 | n4014; + assign n4542 = \[18480] & ~preset & ~\[18415] ; + assign n4547 = n3821 & n3798 & ~preset & ~\[18493] ; + assign n4552 = n3778 & (\[18506] | (n3798 & n3801)); + assign n4557 = n6295 | n6296; + assign n4561 = n6302 | n6303; + assign n4565 = ~preset & ((\[18545] & (pdn | n3874_1)) | (~pdn & n3874_1)); + assign n4570 = n6309 | n6310; + assign n4574 = ~preset & (\[18571] | n3858 | n3859); + assign n4579 = ~preset & (\[18584] | n3858 | n3859); + assign n4584 = n3982 | (~preset & ~pdn & \[18597] ); + assign n4589 = n6316 | (\[18610] & n3784) | n6317; + assign n4594 = n6323 | n6324; + assign n4598 = n6332 | n3970 | n6331; + assign n3696_1 = ~\[17843] & ~preset & \[17791] ; + assign n3697 = n3857 & n3815 & n3756 & n3796; + assign n3698 = n3857 & n3814 & n3756 & n3796; + assign n3699 = n3857 & (n3702 | (n3756 & n3828)); + assign n3700 = n3857 & n3843 & n3756 & n3796; + assign n3701_1 = n3962_1 & n3756 & n3857; + assign n3702 = n3804 & (n5628 | (~n3955 & n3963)); + assign n3703 = ~\[18246] & ~preset & \[17453] ; + assign n3704 = ~preset & (~n3798 | ~n5729 | ~n5730); + assign n3705 = ~\[17154] & ~preset & \[17102] ; + assign n3706_1 = n3800 & n3798 & ~preset & ~\[18285] ; + assign n3707 = ~preset & (\[18285] | ~n3798 | ~n3800); + assign n3708 = ~\[17362] & ~preset & \[17167] ; + assign n3709 = n3801 & n3798 & ~preset & ~\[18506] ; + assign n3710 = ~preset & (\[18506] | ~n3798 | ~n3801); + assign n3711_1 = \[17388] & ~preset & ~\[17310] ; + assign n3712 = ((~n3891 ^ n3945) & (~n3893_1 | (n3893_1 & n3894))) | (n3893_1 & ~n3894 & (n3891 ^ n3945)); + assign n3713 = ~preset & (~n3798 | ~n5729 | ~n5734); + assign n3714 = ((n5483 | n5484) & (~n3880 ^ n3902)) | (~n5483 & ~n5484 & (~n3880 ^ ~n3902)); + assign n3715 = \[18168] & ~preset & ~\[18103] ; + assign n3716_1 = ~\[18363] & ~preset & \[18285] ; + assign n3717 = ~preset & (\[17284] | ~n3798 | ~n3802_1); + assign n3718 = n3802_1 & n3798 & ~preset & ~\[17284] ; + assign n3719 = n3916 ? ((n3914 & n3915) | (n3892 & (n3914 ^ n3915))) : (n3892 ? (~n3914 & ~n3915) : (~n3914 | (n3914 & ~n3915))); + assign n3720 = ((n5485 | n5486) & (~n3896 ^ n3917)) | (~n5485 & ~n5486 & (~n3896 ^ ~n3917)); + assign n3721_1 = \[18506] & ~preset & ~\[18311] ; + assign n3722 = ~preset & (\[16933] | ~n3798 | ~n3803); + assign n3723 = n3803 & n3798 & ~preset & ~\[16933] ; + assign n3724 = (ppeaka_6_6_ & n3810 & (n3861 ^ ~n3924)) | ((~ppeaka_6_6_ | ~n3810) & (~n3861 ^ ~n3924)); + assign n3725 = ~preset & n3825; + assign n3726_1 = (ppeaka_10_10_ & n3810 & (n3866 ^ ~n3926)) | ((~ppeaka_10_10_ | ~n3810) & (~n3866 ^ ~n3926)); + assign n3727 = ~\[17986] & ~preset & \[17635] ; + assign n3728 = (ppeaka_4_4_ & n3810 & (n3872 ^ ~n3929)) | ((~ppeaka_4_4_ | ~n3810) & (~n3872 ^ ~n3929)); + assign n3729 = ~preset & (\[18025] | ~n3798 | ~n3806); + assign n3730 = n3806 & n3798 & ~preset & ~\[18025] ; + assign n3731_1 = (ppeaka_9_9_ & n3810 & (n3864_1 ^ ~n3932)) | ((~ppeaka_9_9_ | ~n3810) & (~n3864_1 ^ ~n3932)); + assign n3732 = \[18025] & ~preset & ~\[17037] ; + assign n3733 = (ppeaka_3_3_ & n3810 & (n3850 ^ ~n3933_1)) | ((~ppeaka_3_3_ | ~n3810) & (~n3850 ^ ~n3933_1)); + assign n3734 = ~preset & (\[17206] | ~n3798 | ~n3808); + assign n3735 = n3808 & n3798 & ~preset & ~\[17206] ; + assign n3736_1 = ((n3870 ^ n3934) & (n3780 | ~n3944)) | (~n3780 & n3944 & (~n3870 ^ n3934)); + assign n3737 = (ppeaka_12_12_ & n3810 & (n3860_1 ^ ~n3935)) | ((~ppeaka_12_12_ | ~n3810) & (~n3860_1 ^ ~n3935)); + assign n3738 = ~preset & (\[17245] | ~n3798 | ~n3811); + assign n3739 = n3811 & n3798 & ~preset & ~\[17245] ; + assign n3740 = n3937 ? ((n3903_1 & n3920) | (n3885 & (n3903_1 | n3920))) : ((~n3903_1 & ~n3920) | (~n3885 & (~n3903_1 | ~n3920))); + assign n3741_1 = ((n5487 | n5488) & (~n3898_1 ^ n3938_1)) | (~n5487 & ~n5488 & (~n3898_1 ^ ~n3938_1)); + assign n3742 = (ppeaka_7_7_ & n3810 & (n3873 ^ ~n3925)) | ((~ppeaka_7_7_ | ~n3810) & (~n3873 ^ ~n3925)); + assign n3743 = (ppeaka_11_11_ & n3810 & (n3869_1 ^ ~n3927)) | ((~ppeaka_11_11_ | ~n3810) & (~n3869_1 ^ ~n3927)); + assign n3744 = (ppeaka_8_8_ & n3810 & (n3865 ^ ~n3939)) | ((~ppeaka_8_8_ | ~n3810) & (~n3865 ^ ~n3939)); + assign n3745 = (ppeaka_13_13_ & n3810 & (n3863 ^ ~n3936)) | ((~ppeaka_13_13_ | ~n3810) & (~n3863 ^ ~n3936)); + assign n3746_1 = (ppeaka_5_5_ & n3810 & (n3871 ^ ~n3928_1)) | ((~ppeaka_5_5_ | ~n3810) & (~n3871 ^ ~n3928_1)); + assign n3747 = ((n5493 | n5761) & (~n3884 ^ n3919)) | (~n5493 & ~n5761 & (~n3884 ^ ~n3919)); + assign n3748 = \[18077] & ~preset & ~\[17999] ; + assign n3749 = (~n5814 & ((~n3848 & n5811) | (~ppeaks_0_0_ & (n3848 | n5811)))) | (~n3848 & ~n5811 & n5814); + assign n3750_1 = n3827_1 & n3798 & ~preset & ~\[17180] ; + assign n3751 = ~preset & (\[17180] | ~n3798 | ~n3827_1); + assign n3752 = (ppeaka_14_14_ & n3810 & (n3867 ^ ~n3940)) | ((~ppeaka_14_14_ | ~n3810) & (~n3867 ^ ~n3940)); + assign n3753 = (ppeaka_2_2_ & n3810 & (n3849 ^ ~n3943_1)) | ((~ppeaka_2_2_ | ~n3810) & (~n3849 ^ ~n3943_1)); + assign n3754_1 = ~\[17505] & ~preset & \[17414] ; + assign n3755 = (ppeaki_10_10_ & n3883_1) | (ppeaki_14_14_ & n3796); + assign n3756 = ~preset & (\[18636] | (~n3798 & n5672)); + assign n3757 = \[18220] & ~preset & ~\[18142] ; + assign n3758_1 = (ppeaki_12_12_ & n3796) | (ppeaki_8_8_ & n3883_1); + assign n3759 = (ppeaki_13_13_ & n3796) | (ppeaki_9_9_ & n3883_1); + assign n3760 = ~\[17635] & ~preset & \[17570] ; + assign n3761 = ppeaki_13_13_ & n3883_1; + assign n3762 = ppeaki_12_12_ & n3883_1; + assign n3763_1 = ~preset & (\[17115] | ~n3798 | ~n3826); + assign n3764 = n3826 & n3798 & ~preset & ~\[17115] ; + assign n3765 = (ppeaki_11_11_ & n3883_1) | (ppeaki_15_15_ & n3796); + assign n3766 = (ppeaki_10_10_ & n3796) | (ppeaki_6_6_ & n3883_1); + assign n3767 = ~\[17648] & ~preset & \[17427] ; + assign n3768_1 = (ppeaki_7_7_ & n3883_1) | (ppeaki_11_11_ & n3796); + assign n3769 = ppeaki_15_15_ & n3883_1; + assign n3770 = (ppeaki_8_8_ & n3796) | (ppeaki_4_4_ & n3883_1); + assign n3771 = ppeaki_14_14_ & n3883_1; + assign n3772_1 = (ppeaki_9_9_ & n3796) | (ppeaki_5_5_ & n3883_1); + assign n3773 = ~preset & n3824 & (n6130 | n6131); + assign n3774 = ~preset & n3813 & (n6130 | n6131); + assign n3775 = ~preset & n3818 & (n6130 | n6131); + assign n3776 = ~preset & n3807_1 & (n6130 | n6131); + assign n3777_1 = ~preset & n3820 & (n6130 | n6131); + assign n3778 = ~preset & ~\[18389] ; + assign n3779 = ~preset & ~\[17102] ; + assign n3780 = \[17180] & ~\[17232] ; + assign n3781 = \[17206] & ~\[17271] ; + assign n3782_1 = ~preset & ~\[17700] ; + assign n3783 = \[18636] | (~n3798 & n5672); + assign n3784 = ~preset & ~\[18636] & (n3798 | ~n5672); + assign n3785 = \[18467] | (n3795 & ~n3804); + assign n3786 = n6193 | (n6190 & n6191 & n6192); + assign n3787_1 = n3798 & ~n3797_1 & ~\[18610] & n3796; + assign n3788 = ~pdn & (\[17024] ? \[18545] : preset_0_0_); + assign n3789 = (~\[17518] & \[17817] ) | (~\[17037] & \[18025] ); + assign n3790 = ~n5631 & (~n5677 | ~n5678) & n5679; + assign n3791 = n4160 | n4427 | n6133 | n6134; + assign n3792_1 = n5729 & n3814 & ~\[18168] & n3798; + assign n3793 = \[17999] & ~\[18220] ; + assign n3794 = \[18363] & ~\[18415] ; + assign n3795 = ~pdn & ((\[17024] & ~\[18545] ) | (~preset_0_0_ & (~\[17024] | ~\[18545] ))); + assign n3796 = ~n3881 & n3875 & ~n3829 & ~n3862; + assign n3797_1 = n5659 | n5660 | n5661 | n5662; + assign n3798 = n5671 | (~n3797_1 & (n5664 | n5668)); + assign n3799 = pdn & ~\[17089] ; + assign n3800 = ~n3881 & ~n3875 & n3829 & ~n3862; + assign n3801 = ~n3881 & n3875 & n3829 & n3862; + assign n3802_1 = n3881 & n3875 & n3829 & ~n3862; + assign n3803 = n3881 & ~n3875 & n3829 & n3862; + assign n3804 = \[18064] ? \[18129] : pirq_0_0_; + assign n3805 = \[17635] & ~\[17986] ; + assign n3806 = ~n3875 & ~n3829 & ~n3862 & n3881; + assign n3807_1 = ~\[17037] & \[18025] ; + assign n3808 = n3881 & n3875 & ~n3829 & ~n3862; + assign n3809 = n3808 & ~\[17206] & n3798; + assign n3810 = n3803 & ~\[16933] & n3798; + assign n3811 = n3881 & n3875 & n3829 & n3862; + assign n3812_1 = n3881 & ~n3875 & ~n3829 & n3862; + assign n3813 = n3801 & ~\[18506] & n3798; + assign n3814 = (n5680 & n5681) | (n3852_1 & n5682); + assign n3815 = (n5683 & n5684) | (n3852_1 & n5685); + assign n3816 = ~\[17570] & (\[18467] | (n3795 & ~n3804)); + assign n3817_1 = n3800 & ~\[18285] & n3798; + assign n3818 = ~\[17583] & \[17648] ; + assign n3819 = n3881 & ~n3875 & n3829 & ~n3862; + assign n3820 = n3802_1 & ~\[17284] & n3798; + assign n3821 = ~n3881 & ~n3875 & ~n3829 & n3862; + assign n3822_1 = n3826 & ~\[17115] & n3798; + assign n3823 = n3827_1 & ~\[17180] & n3798; + assign n3824 = ~\[17518] & \[17817] ; + assign n3825 = n3804 & n3795 & ~\[17817] & ~\[18467] ; + assign n3826 = ~n3881 & n3875 & n3829 & ~n3862; + assign n3827_1 = n3881 & n3875 & ~n3829 & n3862; + assign n3828 = ~n3881 & ~n3875 & n3829 & n3862; + assign n3829 = \[17531] ? \[18012] : ppeaki_2_2_; + assign n3830 = (n3845 & n5633) | (n3844 & n5634); + assign n3831 = (n3845 & n3847_1) | (n5635 & n5636); + assign n3832_1 = (n3852_1 & n5637) | (n3851 & n5638); + assign n3833 = (n3853 & n5640) | (n3847_1 & n5639); + assign n3834 = (n3846 & n5641) | (n3845 & n3854); + assign n3835 = (n3855 & n5642) | (n3851 & n5643); + assign n3836 = (n3853 & n5645) | (n3847_1 & n5644); + assign n3837_1 = (n3847_1 & n3855) | (n5646 & n5647); + assign n3838 = (n3854 & n5648) | (n3853 & n5649); + assign n3839 = (n3852_1 & n5650) | (n3851 & n5651); + assign n3840 = (n3854 & n5652) | (n3853 & n5653); + assign n3841 = (n3851 & n5655) | (n3845 & n5654); + assign n3842_1 = (n3854 & n3855) | (n3846 & n5656); + assign n3843 = (n3855 & n5657) | (n3844 & n5658); + assign n3844 = ~\[17609] & \[17674] ; + assign n3845 = ppeaki_4_4_ & ppeaki_5_5_; + assign n3846 = \[17544] & \[17752] ; + assign n3847_1 = ~\[17752] & ppeaki_6_6_ & ppeaki_7_7_; + assign n3848 = n3809 | n3822_1 | n3823 | n5791; + assign n3849 = n5806 | (ppeaks_2_2_ & n3848); + assign n3850 = n5803 | (ppeaks_3_3_ & n3848); + assign n3851 = \[17752] & ~\[17544] & \[17609] ; + assign n3852_1 = ~\[17752] & ~ppeaki_5_5_ & ~ppeaki_7_7_; + assign n3853 = \[17752] & \[17544] & ~\[17674] ; + assign n3854 = ~\[17752] & ~ppeaki_6_6_ & ppeaki_7_7_; + assign n3855 = ~ppeaki_4_4_ & ppeaki_5_5_; + assign n3856_1 = (pdn & ~\[17089] ) | (~\[17596] & n3790); + assign n3857 = n3856_1 | \[18636] | (~n3798 & n5672); + assign n3858 = n3818 | (~\[17284] & n3798 & n3802_1); + assign n3859 = n3789 | n3809 | n3822_1 | n3823; + assign n3860_1 = n5851 | (ppeaks_12_12_ & n3848); + assign n3861 = n5794 | (ppeaks_6_6_ & n3848); + assign n3862 = \[17531] ? \[18090] : ppeaki_3_3_; + assign n3863 = n5848 | (ppeaks_13_13_ & n3848); + assign n3864_1 = n5829 | (ppeaks_9_9_ & n3848); + assign n3865 = n5832 | (ppeaks_8_8_ & n3848); + assign n3866 = n5826 | (ppeaks_10_10_ & n3848); + assign n3867 = n5845 | (ppeaks_14_14_ & n3848); + assign n3868 = n5842 | (ppeaks_15_15_ & n3848); + assign n3869_1 = n5854 | (ppeaks_11_11_ & n3848); + assign n3870 = n5817 | (ppeaks_1_1_ & n3848); + assign n3871 = n5797 | (ppeaks_5_5_ & n3848); + assign n3872 = n5800 | (ppeaks_4_4_ & n3848); + assign n3873 = n5835 | (ppeaks_7_7_ & n3848); + assign n3874_1 = \[17024] ? \[18545] : preset_0_0_; + assign n3875 = \[17531] ? \[18155] : ppeaki_0_0_; + assign n3876 = ~n3881 & n3875 & ~n3829 & n3862; + assign n3877 = n5728 & n3798 & ~\[17752] & ~n3797_1; + assign n3878_1 = n5736 | n5735 | (~\[18103] & \[18168] ); + assign n3879 = (\[17037] & ~\[17102] ) | (\[17284] & ~\[18376] ); + assign n3880 = n5745 | (ppeaks_12_12_ & (n3878_1 | n5737)); + assign n3881 = \[17531] ? \[18233] : ppeaki_1_1_; + assign n3882 = n5786 | (ppeaks_15_15_ & (n3878_1 | n5737)); + assign n3883_1 = n3829 | (~n3829 & n3862) | (~n3829 & ~n3862 & n3881); + assign n3884 = n5759 | (ppeaks_3_3_ & (n3878_1 | n5737)); + assign n3885 = n5780 | (ppeaks_13_13_ & (n3878_1 | n5737)); + assign n3886 = n5772 | (ppeaks_8_8_ & (n3878_1 | n5737)); + assign n3887 = n5763 | (ppeaks_4_4_ & (n3878_1 | n5737)); + assign n3888_1 = n5757 | (ppeaks_2_2_ & (n3878_1 | n5737)); + assign n3889 = n5765 | (ppeaks_5_5_ & (n3878_1 | n5737)); + assign n3890 = n5770 | (ppeaks_7_7_ & (n3878_1 | n5737)); + assign n3891 = n5743 | (ppeaks_1_1_ & (n3878_1 | n5737)); + assign n3892 = n5782 | (ppeaks_14_14_ & (n3878_1 | n5737)); + assign n3893_1 = n3810 | n3820 | n3878_1 | n5739; + assign n3894 = n5741 | (ppeaks_0_0_ & (n3878_1 | n5737)); + assign n3895 = n5778 | (ppeaks_11_11_ & (n3878_1 | n5737)); + assign n3896 = n5774 | (ppeaks_9_9_ & (n3878_1 | n5737)); + assign n3897 = n5776 | (ppeaks_10_10_ & (n3878_1 | n5737)); + assign n3898_1 = n5767 | (ppeaks_6_6_ & (n3878_1 | n5737)); + assign n3899 = n5716 | n5717 | n5718 | n5719; + assign n3900 = (~n3878_1 & ~n3945 & ~n5737 & ~n5739) | (n3945 & (n3878_1 | n5737 | n5739)); + assign n3901 = (n3893_1 & ((n3894 & n3945) | (n3891 & (n3894 | n3945)))) | (n3891 & ~n3893_1 & ~n3945); + assign n3902 = n5755 | (~ppeaka_12_12_ & ~n5532 & ~n5533); + assign n3903_1 = (n3880 & n3902) | ((n3880 | n3902) & (n5483 | n5484)); + assign n3904 = n5535 | n5534 | (~ppeaka_11_11_ & ~n3952); + assign n3905 = (n3910 & n3911) | (n3897 & (n3910 | n3911)); + assign n3906 = n3895 | n5534 | n5535 | n5536; + assign n3907 = n5749 | (n3948_1 & ~n5541 & ~n5542); + assign n3908_1 = (n3912 & n3913_1) | (n3887 & (n3912 | n3913_1)); + assign n3909 = n5749 | n3889 | n5539; + assign n3910 = ~n3952 ^ (~n5537 & (n3941 | ~n5751)); + assign n3911 = (n3896 & n3917) | ((n3896 | n3917) & (n5485 | n5486)); + assign n3912 = ~n3947 ^ ((n3792_1 | n3900) & ~n5541); + assign n3913_1 = (n3884 & n3919) | ((n3884 | n3919) & (n5493 | n5761)); + assign n3914 = n5468 | n5784; + assign n3915 = (n3903_1 & n3920) | (n3885 & (n3903_1 | n3920)); + assign n3916 = (~n3882 & ~n5462 & ~n5463 & ~n5790) | (n3882 & (n5462 | n5463 | n5790)); + assign n3917 = n5519 | n5518 | (~n3792_1 & ~n3949); + assign n3918_1 = n5544 | n5543 | (~ppeaka_2_2_ & ~n3945); + assign n3919 = (n3901 & n3918_1) | (n3888_1 & (n3901 | n3918_1)); + assign n3920 = n3950 ^ (n5532 | n5533); + assign n3921 = ~n3949 ^ ~n3953_1; + assign n3922 = (n3898_1 & n3938_1) | ((n3898_1 | n3938_1) & (n5487 | n5488)); + assign n3923_1 = (n3890 & n3922) | ((n3890 | n3922) & (~n3949 ^ ~n3953_1)); + assign n3924 = (n3928_1 & n5822) | (n3871 & (n3928_1 | n5822)); + assign n3925 = (n3924 & n5823) | (n3861 & (n3924 | n5823)); + assign n3926 = (n3932 & n5838) | (n3864_1 & (n3932 | n5838)); + assign n3927 = (n3926 & n5839) | (n3866 & (n3926 | n5839)); + assign n3928_1 = (n3929 & n5821) | (n3872 & (n3929 | n5821)); + assign n3929 = (n3933_1 & n5820) | (n3850 & (n3933_1 | n5820)); + assign n3930 = n3868 ? ((~n3940 & ~n5858) | (~n3867 & (~n3940 | ~n5858))) : ((n3940 & n5858) | (n3867 & (n3940 | n5858))); + assign n3931 = ~ppeaka_15_15_ | \[16933] | ~n3798 | ~n3803; + assign n3932 = (n3939 & n5837) | (n3865 & (n3939 | n5837)); + assign n3933_1 = (n3943_1 & n5819) | (n3849 & (n3943_1 | n5819)); + assign n3934 = (~ppeaks_0_0_ & ~n5814) | (~n3848 & (~n5811 | ~n5814)); + assign n3935 = (n3927 & n5855) | (n3869_1 & (n3927 | n5855)); + assign n3936 = (n3935 & n5856) | (n3860_1 & (n3935 | n5856)); + assign n3937 = ~n3892 ^ (n5468 | n5784); + assign n3938_1 = ~n3949 & (~ppeaka_6_6_ | ~n3792_1 | n5768); + assign n3939 = (n3925 & n5836) | (n3873 & (n3925 | n5836)); + assign n3940 = (n3936 & n5857) | (n3863 & (n3936 | n5857)); + assign n3941 = (~ppeaka_8_8_ & (~n3949 | (ppeaka_7_7_ & n3792_1))) | (~n3792_1 & ~n3949) | (n3792_1 & n3949 & ~ppeaka_7_7_ & ppeaka_8_8_); + assign n3942 = n3886 | n3941; + assign n3943_1 = (n3944 & n5818 & ~n3780 & n3870) | ((n3780 | ~n3944) & (n3870 | (~n3870 & n5818))); + assign n3944 = ~ppeaka_1_1_ | \[16933] | ~n3798 | ~n3803; + assign n3945 = ~ppeaka_1_1_ | ~n3798 | ~n5729 | ~n5730; + assign n3946 = ~ppeaka_2_2_ | ~n3798 | ~n5729 | ~n5730; + assign n3947 = ~ppeaka_4_4_ | ~n3798 | ~n5729 | ~n5730; + assign n3948_1 = ~ppeaka_5_5_ | ~n3798 | ~n5729 | ~n5730; + assign n3949 = n5538 | (~n5539 & ~n5749 & n5750); + assign n3950 = ~ppeaka_13_13_ | ~n3798 | ~n5729 | ~n5730; + assign n3951 = n5537 | (~ppeaka_8_8_ & ~ppeaka_9_9_ & ~n3941); + assign n3952 = ~ppeaka_10_10_ | ~n3798 | ~n5729 | ~n5730; + assign n3953_1 = ~ppeaka_7_7_ | ~n3798 | ~n5729 | ~n5730; + assign n3954 = ~ppeaka_11_11_ | ~n3798 | ~n5729 | ~n5730; + assign n3955 = n3874_1 | (~n5631 & (~n5677 | ~n5678)); + assign n3956 = n3829 & n3881 & (~n3862 ^ n3875); + assign n3957_1 = n3875 & (n3829 ? (~n3862 & ~n3881) : (n3862 & n3881)); + assign n3958 = n3881 & (n3829 ? (~n3862 & n3875) : (n3862 & ~n3875)); + assign n3959 = n3829 & (n3862 ? (n3875 ^ ~n3881) : (~n3875 & n3881)); + assign n3960 = n3959 | (n3796 & n3843); + assign n3961 = ~n3829 & ~n3862 & n3881; + assign n3962_1 = (~n3829 & n3862 & ~n3875) | (n3875 & (n3829 ? (~n3862 & n3881) : (n3862 & ~n3881))); + assign n3963 = ~\[17089] & ~preset & pdn; + assign n3964 = (n3829 & ~n3875 & (~n3862 ^ n3881)) | (~n3829 & ~n3862 & n3875 & ~n3881); + assign n3965 = ~preset & n3816 & (n6130 | n6131); + assign n3966 = (~n3829 & n3881 & (~n3862 | (n3862 & n3875))) | (n3829 & ~n3862 & n3875 & ~n3881); + assign n3967_1 = (n3829 & ~n3862 & n3881) | (~n3829 & n3862 & ~n3881) | (n3862 & (n3829 ? (n3875 ^ ~n3881) : (~n3875 & n3881))); + assign n3968 = n5629 | (~preset & (~n3857 | n5630)); + assign n3969 = n3798 & ~preset & \[16920] ; + assign n3970 = n3798 & (n3981_1 | n6316 | n6317); + assign n3971 = \[8255] & n4081 & (n6130 | n6131); + assign n3972_1 = \[6065] & n4518 & (n6130 | n6131); + assign n3973 = \[9410] & n4509 & (n6130 | n6131); + assign n3974 = \[10970] & n4096 & (n6130 | n6131); + assign n3975 = ppeaks_7_7_ & n3791 & (n6130 | n6131); + assign n3976_1 = ~n6131 & ~n6130 & ~preset & paddress_7_7_; + assign n3977 = \[12905] & n4011 & (n6130 | n6131); + assign n3978 = n3965 & \[11075] & n3804; + assign n3979 = ppeaka_7_7_ & (n4187 | n4188); + assign n3980 = ppeakp_7_7_ & (n4189_1 | (~n3804 & n3965)); + assign n3981_1 = \[18610] & n3784; + assign n3982 = n6311 & n6191 & ~preset & n6190; + assign n3983 = \[7625] & n4081 & (n6130 | n6131); + assign n3984 = \[6740] & n4518 & (n6130 | n6131); + assign n3985 = \[7475] & n4509 & (n6130 | n6131); + assign n3986_1 = \[11690] & n4096 & (n6130 | n6131); + assign n3987 = ppeaks_6_6_ & n3791 & (n6130 | n6131); + assign n3988 = ~n6131 & ~n6130 & ~preset & paddress_6_6_; + assign n3989 = \[13865] & n4011 & (n6130 | n6131); + assign n3990 = n3965 & \[9950] & n3804; + assign n3991_1 = ppeaka_6_6_ & (n4187 | n4188); + assign n3992 = ppeakp_6_6_ & (n4189_1 | (~n3804 & n3965)); + assign n3993 = \[6995] & n4081 & (n6130 | n6131); + assign n3994 = \[4670] & n4518 & (n6130 | n6131); + assign n3995 = \[8105] & n4509 & (n6130 | n6131); + assign n3996_1 = \[11465] & n4096 & (n6130 | n6131); + assign n3997 = ppeaks_5_5_ & n3791 & (n6130 | n6131); + assign n3998 = ~n6131 & ~n6130 & ~preset & paddress_5_5_; + assign n3999 = \[13505] & n4011 & (n6130 | n6131); + assign n4000 = n3965 & \[10220] & n3804; + assign n4001_1 = ppeaka_5_5_ & (n4187 | n4188); + assign n4002 = ppeakp_5_5_ & (n4189_1 | (~n3804 & n3965)); + assign n4003 = \[12245] & n4081 & (n6130 | n6131); + assign n4004 = \[5375] & n4518 & (n6130 | n6131); + assign n4005 = \[6170] & n4509 & (n6130 | n6131); + assign n4006_1 = \[5615] & n4096 & (n6130 | n6131); + assign n4007 = ppeaks_4_4_ & n3791 & (n6130 | n6131); + assign n4008 = ~n6131 & ~n6130 & ~preset & paddress_4_4_; + assign n4009 = \[14675] & n4011 & (n6130 | n6131); + assign n4010 = n3965 & \[10505] & n3804; + assign n4011_1 = ppeaka_4_4_ & (n4187 | n4188); + assign n4012 = ppeakp_4_4_ & (n4189_1 | (~n3804 & n3965)); + assign n4013 = n6289 & n3804 & ~\[18467] & n3795; + assign n4014 = n4001 & (\[18467] | (n3795 & ~n3804)); + assign n4015 = \[12455] & n4081 & (n6130 | n6131); + assign n4016_1 = \[9995] & n4518 & (n6130 | n6131); + assign n4017 = \[6845] & n4509 & (n6130 | n6131); + assign n4018 = \[4910] & n4096 & (n6130 | n6131); + assign n4019 = ppeaks_3_3_ & n3791 & (n6130 | n6131); + assign n4020 = ~n6131 & ~n6130 & ~preset & paddress_3_3_; + assign n4021_1 = \[14255] & n4011 & (n6130 | n6131); + assign n4022 = n3965 & \[10790] & n3804; + assign n4023 = ppeaka_3_3_ & (n4187 | n4188); + assign n4024 = ppeakp_3_3_ & (n4189_1 | (~n3804 & n3965)); + assign n4025 = \[12680] & n4081 & (n6130 | n6131); + assign n4026_1 = \[9725] & n4518 & (n6130 | n6131); + assign n4027 = \[4760] & n4509 & (n6130 | n6131); + assign n4028 = \[6980] & n4096 & (n6130 | n6131); + assign n4029 = ppeaks_2_2_ & n3791 & (n6130 | n6131); + assign n4030 = ~n6131 & ~n6130 & ~preset & paddress_2_2_; + assign n4031_1 = \[15425] & n4011 & (n6130 | n6131); + assign n4032 = n3965 & \[11060] & n3804; + assign n4033 = ppeaka_2_2_ & (n4187 | n4188); + assign n4034 = ppeakp_2_2_ & (n4189_1 | (~n3804 & n3965)); + assign n4035 = ~n3859 & ~n3858 & ~preset & \[18337] ; + assign n4036_1 = n3858 & ~preset & ppeaka_0_0_; + assign n4037 = \[12920] & n4081 & (n6130 | n6131); + assign n4038 = \[9290] & n4518 & (n6130 | n6131); + assign n4039 = \[10310] & n4509 & (n6130 | n6131); + assign n4040 = \[6305] & n4096 & (n6130 | n6131); + assign n4041_1 = ppeaks_1_1_ & n3791 & (n6130 | n6131); + assign n4042 = ~n6131 & ~n6130 & ~preset & paddress_1_1_; + assign n4043 = \[12005] & n4011 & (n6130 | n6131); + assign n4044 = n3965 & \[11315] & n3804; + assign n4045 = ppeaka_1_1_ & (n4187 | n4188); + assign n4046_1 = ppeakp_1_1_ & (n4189_1 | (~n3804 & n3965)); + assign n4047 = ~preset & n3793 & (n6130 | n6131); + assign n4048 = ~\[18415] & ~preset & \[18285] ; + assign n4049 = \[17739] & ~preset & piack_0_0_; + assign n4050 = ~\[17700] & ~preset & piack_0_0_; + assign n4051_1 = \[13175] & n4081 & (n6130 | n6131); + assign n4052 = \[8630] & n4518 & (n6130 | n6131); + assign n4053 = \[10025] & n4509 & (n6130 | n6131); + assign n4054 = \[8240] & n4096 & (n6130 | n6131); + assign n4055 = ppeaks_0_0_ & n3791 & (n6130 | n6131); + assign n4056_1 = ~n6131 & ~n6130 & ~preset & paddress_0_0_; + assign n4057 = \[12890] & n4011 & (n6130 | n6131); + assign n4058 = n3965 & \[11555] & n3804; + assign n4059 = ppeaka_0_0_ & (n4187 | n4188); + assign n4060 = ppeakp_0_0_ & (n4189_1 | (~n3804 & n3965)); + assign n4061_1 = n4150 & (n6130 | n6131); + assign n4062 = ~preset & \[18233] & (\[17531] | ~n3798); + assign n4063 = n3798 & ~\[17531] & ~preset & ppeaki_1_1_; + assign n4064 = ~n3859 & ~n3858 & ~preset & \[18194] ; + assign n4065 = n3858 & ~preset & ppeaka_11_11_; + assign n4066_1 = ~preset & \[18155] & (\[17531] | ~n3798); + assign n4067 = n3798 & ~\[17531] & ~preset & ppeaki_0_0_; + assign n4068 = n6257 & (\[18467] | ~n3795 | (n3795 & ~n3804)); + assign n4069 = n3804 & n3795 & ~preset & ~\[18467] ; + assign n4070 = ~preset & \[18090] & (\[17531] | ~n3798); + assign n4071_1 = n3798 & ~\[17531] & ~preset & ppeaki_3_3_; + assign n4072 = n3804 & n3795 & n4001 & ~\[18467] ; + assign n4073 = ~preset & \[18012] & (\[17531] | ~n3798); + assign n4074 = n3798 & ~\[17531] & ~preset & ppeaki_2_2_; + assign n4075 = ~n3859 & ~n3858 & ~preset & \[17973] ; + assign n4076_1 = n3858 & ~preset & ppeaka_12_12_; + assign n4077 = ~n3859 & ~n3858 & ~preset & \[17921] ; + assign n4078 = n3858 & ~preset & ppeaka_10_10_; + assign n4079 = n3804 & n3795 & ~\[18467] & n3782_1; + assign n4080 = ~n3859 & ~n3858 & ~preset & \[17778] ; + assign n4081_1 = n3858 & ~preset & ppeaka_14_14_; + assign n4082 = ~n3859 & ~n3858 & ~preset & \[17765] ; + assign n4083 = n3858 & ~preset & ppeaka_9_9_; + assign n4084 = \[10985] & n4081 & (n6130 | n6131); + assign n4085 = \[6080] & n4518 & (n6130 | n6131); + assign n4086_1 = \[5480] & n4509 & (n6130 | n6131); + assign n4087 = \[12650] & n4096 & (n6130 | n6131); + assign n4088 = ppeaks_14_14_ & n3791 & (n6130 | n6131); + assign n4089 = ~n6131 & ~n6130 & ~preset & paddress_14_14_; + assign n4090 = \[14270] & n4011 & (n6130 | n6131); + assign n4091_1 = n3965 & \[12260] & n3804; + assign n4092 = ppeaka_14_14_ & (n4187 | n4188); + assign n4093 = ppeakp_14_14_ & (n4189_1 | (~n3804 & n3965)); + assign n4094 = \[6320] & n4081 & (n6130 | n6131); + assign n4095 = \[6755] & n4518 & (n6130 | n6131); + assign n4096_1 = \[8765] & n4509 & (n6130 | n6131); + assign n4097 = \[12425] & n4096 & (n6130 | n6131); + assign n4098 = ppeaks_15_15_ & n3791 & (n6130 | n6131); + assign n4099 = ~n6131 & ~n6130 & ~preset & paddress_15_15_; + assign n4100 = \[13880] & n4011 & (n6130 | n6131); + assign n4101_1 = n3965 & \[12470] & n3804; + assign n4102 = ppeaka_15_15_ & (n4187 | n4188); + assign n4103 = ppeakp_15_15_ & (n4189_1 | (~n3804 & n3965)); + assign n4104 = \[10415] & n4081 & (n6130 | n6131); + assign n4105 = \[10010] & n4518 & (n6130 | n6131); + assign n4106_1 = \[6860] & n4509 & (n6130 | n6131); + assign n4107 = \[14660] & n4096 & (n6130 | n6131); + assign n4108 = ppeaks_12_12_ & n3791 & (n6130 | n6131); + assign n4109 = ~n6131 & ~n6130 & ~preset & paddress_12_12_; + assign n4110 = \[15065] & n4011 & (n6130 | n6131); + assign n4111_1 = n3965 & \[12050] & n3804; + assign n4112 = ppeaka_12_12_ & (n4187 | n4188); + assign n4113 = ppeakp_12_12_ & (n4189_1 | (~n3804 & n3965)); + assign n4114 = n6194 & (~n6187 | ~n6188 | ~n6191); + assign n4115 = \[17986] & (n5631 | (n5677 & n5678)); + assign n4116_1 = \[10700] & n4081 & (n6130 | n6131); + assign n4117 = \[9740] & n4518 & (n6130 | n6131); + assign n4118 = \[4775] & n4509 & (n6130 | n6131); + assign n4119 = \[14240] & n4096 & (n6130 | n6131); + assign n4120 = ppeaks_13_13_ & n3791 & (n6130 | n6131); + assign n4121_1 = ~n6131 & ~n6130 & ~preset & paddress_13_13_; + assign n4122 = \[14690] & n4011 & (n6130 | n6131); + assign n4123 = n3965 & \[12170] & n3804; + assign n4124 = ppeaka_13_13_ & (n4187 | n4188); + assign n4125 = ppeakp_13_13_ & (n4189_1 | (~n3804 & n3965)); + assign n4126_1 = n3798 & ~preset & ~\[18636] ; + assign n4127 = ~n3859 & ~n3858 & ~preset & \[17492] ; + assign n4128 = n3858 & ~preset & ppeaka_13_13_; + assign n4129 = \[9860] & n4081 & (n6130 | n6131); + assign n4130 = \[9305] & n4518 & (n6130 | n6131); + assign n4131_1 = \[9770] & n4509 & (n6130 | n6131); + assign n4132 = \[13850] & n4096 & (n6130 | n6131); + assign n4133 = ppeaks_10_10_ & n3791 & (n6130 | n6131); + assign n4134 = ~n6131 & ~n6130 & ~preset & paddress_10_10_; + assign n4135 = \[12665] & n4011 & (n6130 | n6131); + assign n4136_1 = n3965 & \[11795] & n3804; + assign n4137 = ppeaka_10_10_ & (n4187 | n4188); + assign n4138 = ppeakp_10_10_ & (n4189_1 | (~n3804 & n3965)); + assign n4139 = \[10130] & n4081 & (n6130 | n6131); + assign n4140 = \[8645] & n4518 & (n6130 | n6131); + assign n4141_1 = \[10595] & n4509 & (n6130 | n6131); + assign n4142 = \[13490] & n4096 & (n6130 | n6131); + assign n4143 = ppeaks_11_11_ & n3791 & (n6130 | n6131); + assign n4144 = ~n6131 & ~n6130 & ~preset & paddress_11_11_; + assign n4145 = \[12125] & n4011 & (n6130 | n6131); + assign n4146_1 = n3965 & \[11915] & n3804; + assign n4147 = ppeaka_11_11_ & (n4187 | n4188); + assign n4148 = ppeakp_11_11_ & (n4189_1 | (~n3804 & n3965)); + assign n4149 = ~n3859 & ~n3858 & ~preset & \[17323] ; + assign n4150_1 = n3858 & ~preset & ppeaka_2_2_; + assign n4151 = ~n3859 & ~n3858 & ~preset & \[17258] ; + assign n4152 = n3858 & ~preset & ppeaka_1_1_; + assign n4153 = ~n3859 & ~n3858 & ~preset & \[17193] ; + assign n4154 = n3858 & ~preset & ppeaka_4_4_; + assign n4155_1 = ~n3859 & ~n3858 & ~preset & \[17128] ; + assign n4156 = n3858 & ~preset & ppeaka_3_3_; + assign n4157 = ~n3859 & ~n3858 & ~preset & \[17076] ; + assign n4158 = n3858 & ~preset & ppeaka_15_15_; + assign n4159 = ~n3859 & ~n3858 & ~preset & \[17063] ; + assign n4160_1 = n3858 & ~preset & ppeaka_6_6_; + assign n4161 = ~n3859 & ~n3858 & ~preset & \[16998] ; + assign n4162 = n3858 & ~preset & ppeaka_5_5_; + assign n4163 = ~n3859 & ~n3858 & ~preset & \[16959] ; + assign n4164 = n3858 & ~preset & ppeaka_8_8_; + assign n4165_1 = \[9590] & n4081 & (n6130 | n6131); + assign n4166 = \[7370] & n4518 & (n6130 | n6131); + assign n4167 = \[10040] & n4509 & (n6130 | n6131); + assign n4168 = \[15770] & n4096 & (n6130 | n6131); + assign n4169_1 = ppeaks_9_9_ & n3791 & (n6130 | n6131); + assign n4170 = ~n6131 & ~n6130 & ~preset & paddress_9_9_; + assign n4171 = \[12440] & n4011 & (n6130 | n6131); + assign n4172 = n3965 & \[11570] & n3804; + assign n4173 = ppeaka_9_9_ & (n4187 | n4188); + assign n4174_1 = ppeakp_9_9_ & (n4189_1 | (~n3804 & n3965)); + assign n4175 = ~n3859 & ~n3858 & ~preset & \[16907] ; + assign n4176 = n3858 & ~preset & ppeaka_7_7_; + assign n4177 = \[8915] & n4081 & (n6130 | n6131); + assign n4178 = \[8000] & n4518 & (n6130 | n6131); + assign n4179_1 = \[8750] & n4509 & (n6130 | n6131); + assign n4180 = \[11225] & n4096 & (n6130 | n6131); + assign n4181 = ppeaks_8_8_ & n3791 & (n6130 | n6131); + assign n4182 = ~n6131 & ~n6130 & ~preset & paddress_8_8_; + assign n4183 = \[13160] & n4011 & (n6130 | n6131); + assign n4184_1 = n3965 & \[11330] & n3804; + assign n4185 = ppeaka_8_8_ & (n4187 | n4188); + assign n4186 = ppeakp_8_8_ & (n4189_1 | (~n3804 & n3965)); + assign n4187 = ~preset & n3817_1 & (n6130 | n6131); + assign n4188 = n4056 & (n6130 | n6131); + assign n4189_1 = n4031 & (n6130 | n6131); + assign n4190 = ~preset & \[16085] & (~n3798 | ~n5732); + assign n4191 = ~preset & \[16070] & (~n3798 | ~n5731); + assign n4192 = ~preset & \[16055] & (\[18103] | ~\[18168] ); + assign n4193 = \[16025] & n3704; + assign n4194_1 = ~preset & \[16010] & (~n3798 | ~n5733); + assign n4195 = n5733 & n3798 & ~preset & pdata_9_9_; + assign n4196 = ~preset & \[15995] & (~n3798 | ~n5733); + assign n4197 = n5733 & n3798 & ~preset & pdata_0_0_; + assign n4198 = ~preset & \[15980] & (~n3798 | ~n5732); + assign n4199_1 = n5732 & n3798 & ~preset & pdata_7_7_; + assign n4200 = ~preset & \[15965] & (~n3798 | ~n5731); + assign n4201 = n5731 & n3798 & ~preset & pdata_14_14_; + assign n4202 = ~preset & \[15920] & (~\[17102] | \[17154] ); + assign n4203_1 = ~preset & \[15905] & (~\[17102] | \[17154] ); + assign n4204 = n3857 & n3827_1 & \[9860] & n3756; + assign n4205 = n3963 & n3874_1 & \[10205] & n3857; + assign n4206 = n3857 & n3826 & \[12665] & n3756; + assign n4207 = n3857 & n3808 & \[13850] & n3756; + assign n4208_1 = n3857 & n3806 & \[10400] & n3756; + assign n4209 = n3857 & n3812_1 & \[6155] & n3756; + assign n4210 = n3857 & n3801 & \[8135] & n3756; + assign n4211 = n3876 & n3857 & \[14585] & n3756; + assign n4212 = n3857 & n3821 & \[5450] & n3756; + assign n4213_1 = n3857 & n3802_1 & \[8060] & n3756; + assign n4214 = n3857 & n3803 & \[8810] & n3756; + assign n4215 = n3857 & \[12860] & n3702; + assign n4216 = n3857 & n3800 & \[4700] & n3756; + assign n4217 = ppeaks_10_10_ & (n5708 | n5709); + assign n4218_1 = n3801 & \[15665] & n3756; + assign n4219 = \[15860] & (n3968 | n5701 | n5702); + assign n4220 = \[13130] & n3804 & (n5627 | n5628); + assign n4221 = n3801 & \[9980] & n3756; + assign n4222 = \[15845] & (n3968 | n5701 | n5702); + assign n4223_1 = \[9500] & n3804 & (n5627 | n5628); + assign n4224 = n3843 & n3796 & ppeaka_6_6_ & n3756; + assign n4225 = n3957_1 & \[8330] & n3756; + assign n4226 = n3811 & \[5660] & n3756; + assign n4227_1 = n3962_1 & ppeakb_5_5_ & n3756; + assign n4228 = n3819 & \[6560] & n3756; + assign n4229 = n3808 & \[11465] & n3756; + assign n4230 = n3800 & \[15590] & n3756; + assign n4231 = n3814 & n3796 & \[14105] & n3756; + assign n4232_1 = n3803 & \[7670] & n3756; + assign n4233 = n3815 & n3796 & ~ppeaka_5_5_ & n3756; + assign n4234 = n3815 & n3796 & ~ppeakb_5_5_ & n3756; + assign n4235 = ppeakp_5_5_ & (n3702 | (n3756 & n3828)); + assign n4236 = n3806 & \[14825] & n3756; + assign n4237_1 = ppeaka_5_5_ & ((n3756 & n3801) | n3968); + assign n4238 = n3857 & n3811 & \[8315] & n3756; + assign n4239 = n3857 & n3819 & \[14435] & n3756; + assign n4240 = n3957_1 & n3857 & \[15140] & n3756; + assign n4241 = n3857 & n3808 & \[12650] & n3756; + assign n4242_1 = n3857 & n3806 & \[15575] & n3756; + assign n4243 = n3857 & n3803 & \[6335] & n3756; + assign n4244 = n3857 & n3800 & \[9080] & n3756; + assign n4245 = ppeaka_14_14_ & ((n3756 & n3801) | n3968); + assign n4246 = n3966 & n3857 & ppeaka_7_7_ & n3756; + assign n4247_1 = n3857 & n3812_1 & \[13340] & n3756; + assign n4248 = n3857 & n3801 & \[14930] & n3756; + assign n4249 = n3876 & n3857 & \[15980] & n3756; + assign n4250 = n3857 & n3821 & \[5915] & n3756; + assign n4251_1 = n3857 & n3802_1 & \[14450] & n3756; + assign n4252 = n3857 & n3803 & \[5315] & n3756; + assign n4253 = n3857 & \[7055] & n3702; + assign n4254 = n3857 & n3800 & \[9095] & n3756; + assign n4255 = ppeakb_7_7_ & ((n3756 & n3960) | n3968); + assign n4256_1 = ~preset & \[15785] & (~\[17791] | \[17843] ); + assign n4257 = ~preset & \[15725] & (~n3798 | ~n5731); + assign n4258 = ~preset & \[15710] & (\[18103] | ~\[18168] ); + assign n4259 = n3715 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4260 = n4427 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4261_1 = ~preset & \[15650] & (~n3798 | ~n5733); + assign n4262 = n5733 & n3798 & ~preset & pdata_1_1_; + assign n4263 = ~preset & \[15635] & (~n3798 | ~n5732); + assign n4264 = n5732 & n3798 & ~preset & pdata_6_6_; + assign n4265_1 = ~preset & \[15620] & (~n3798 | ~n5731); + assign n4266 = n5731 & n3798 & ~preset & pdata_15_15_; + assign n4267 = ~preset & \[15575] & (~\[17102] | \[17154] ); + assign n4268 = ~preset & \[15560] & (~\[17102] | \[17154] ); + assign n4269 = n3857 & n3827_1 & \[13175] & n3756; + assign n4270_1 = n3963 & n3874_1 & \[9935] & n3857; + assign n4271 = n3857 & n3826 & \[12890] & n3756; + assign n4272 = n3857 & n3808 & \[8240] & n3756; + assign n4273 = n3857 & n3806 & \[10670] & n3756; + assign n4274 = n3857 & n3812_1 & \[15380] & n3756; + assign n4275_1 = n3857 & n3801 & \[7490] & n3756; + assign n4276 = n3876 & n3857 & \[13400] & n3756; + assign n4277 = n3857 & n3821 & \[6125] & n3756; + assign n4278 = n3857 & n3802_1 & \[7415] & n3756; + assign n4279 = n3857 & n3803 & \[9455] & n3756; + assign n4280_1 = n3857 & \[12605] & n3702; + assign n4281 = n3857 & n3800 & \[5390] & n3756; + assign n4282 = ppeaks_0_0_ & (n5708 | n5709); + assign n4283 = n3801 & \[9710] & n3756; + assign n4284 = \[15515] & (n3968 | n5701 | n5702); + assign n4285_1 = \[13475] & n3804 & (n5627 | n5628); + assign n4286 = n3801 & \[15305] & n3756; + assign n4287 = \[15500] & (n3968 | n5701 | n5702); + assign n4288 = \[9800] & n3804 & (n5627 | n5628); + assign n4289 = n3843 & n3796 & ppeaka_5_5_ & n3756; + assign n4290_1 = n3957_1 & \[14765] & n3756; + assign n4291 = n3811 & \[8975] & n3756; + assign n4292 = n3962_1 & ppeakb_4_4_ & n3756; + assign n4293 = n3819 & \[14870] & n3756; + assign n4294 = n3808 & \[5615] & n3756; + assign n4295_1 = n3800 & \[13280] & n3756; + assign n4296 = n3814 & n3796 & \[14525] & n3756; + assign n4297 = n3803 & \[8300] & n3756; + assign n4298 = n3815 & n3796 & ~ppeaka_4_4_ & n3756; + assign n4299 = n3815 & n3796 & ~ppeakb_4_4_ & n3756; + assign n4300_1 = ppeakp_4_4_ & (n3702 | (n3756 & n3828)); + assign n4301 = n3806 & \[15905] & n3756; + assign n4302 = ppeaka_4_4_ & ((n3756 & n3801) | n3968); + assign n4303 = n3957_1 & \[13550] & n3756; + assign n4304_1 = n3811 & \[6365] & n3756; + assign n4305 = n3962_1 & ppeakb_15_15_ & n3756; + assign n4306 = n3819 & \[7205] & n3756; + assign n4307 = n3808 & \[12425] & n3756; + assign n4308 = n3800 & \[15950] & n3756; + assign n4309_1 = n3814 & n3796 & \[13730] & n3756; + assign n4310 = n3803 & \[7010] & n3756; + assign n4311 = n3815 & n3796 & ~ppeaka_15_15_ & n3756; + assign n4312 = n3815 & n3796 & ~ppeakb_15_15_ & n3756; + assign n4313 = ppeakp_15_15_ & (n3702 | (n3756 & n3828)); + assign n4314_1 = n3806 & \[15215] & n3756; + assign n4315 = ppeaka_15_15_ & ((n3756 & n3801) | n3968); + assign n4316 = n3966 & ppeaka_6_6_ & n3756; + assign n4317 = n3821 & \[7865] & n3756; + assign n4318 = n3802_1 & \[6575] & n3756; + assign n4319_1 = n3876 & \[15635] & n3756; + assign n4320 = n3800 & \[7160] & n3756; + assign n4321 = n3814 & n3796 & \[4385] & n3756; + assign n4322 = n3803 & \[4610] & n3756; + assign n4323 = n3815 & n3796 & \[7745] & n3756; + assign n4324_1 = n3801 & \[10265] & n3756; + assign n4325 = ppeakb_6_6_ & ((n3756 & n3960) | n3968); + assign n4326 = \[7685] & n3804 & (n5627 | n5628); + assign n4327 = ~preset & \[15440] & (~\[17791] | \[17843] ); + assign n4328_1 = ~preset & \[15410] & (~\[17427] | \[17648] ); + assign n4329 = ~preset & \[15395] & (~\[17427] | \[17648] ); + assign n4330 = ~preset & \[15380] & (~n3798 | ~n5733); + assign n4331 = ~preset & \[15365] & (~n3798 | ~n5732); + assign n4332 = n3962 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4333_1 = ~preset & \[15350] & (\[18103] | ~\[18168] ); + assign n4334 = n4427 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n4335 = ~preset & \[15290] & (~n3798 | ~n5733); + assign n4336 = n5733 & n3798 & ~preset & pdata_2_2_; + assign n4337 = ~preset & \[15275] & (~n3798 | ~n5732); + assign n4338_1 = n5732 & n3798 & ~preset & pdata_9_9_; + assign n4339 = ~preset & \[15260] & (~n3798 | ~n5731); + assign n4340 = n5731 & n3798 & ~preset & pdata_12_12_; + assign n4341 = ~preset & \[15245] & (~\[17167] | \[17362] ); + assign n4342 = ~preset & \[15215] & (~\[17102] | \[17154] ); + assign n4343_1 = ~preset & \[15200] & (~\[17102] | \[17154] ); + assign n4344 = ppeaka_15_15_ & (n5577 | n5720); + assign n4345 = n3963 & \[11285] & n3874_1; + assign n4346 = ppeakp_15_15_ & (n5722 | n5723 | n5725); + assign n4347 = n3801 & ppeakb_15_15_ & n3756; + assign n4348_1 = n3857 & n3827_1 & \[8915] & n3756; + assign n4349 = n3963 & n3874_1 & \[10775] & n3857; + assign n4350 = n3857 & n3826 & \[13160] & n3756; + assign n4351 = n3857 & n3808 & \[11225] & n3756; + assign n4352 = n3857 & n3806 & \[7595] & n3756; + assign n4353_1 = n3857 & n3812_1 & \[12590] & n3756; + assign n4354 = n3857 & n3801 & \[9440] & n3756; + assign n4355 = n3876 & n3857 & \[15365] & n3756; + assign n4356 = n3857 & n3821 & \[6815] & n3756; + assign n4357 = n3857 & n3802_1 & \[10865] & n3756; + assign n4358_1 = n3857 & n3803 & \[7520] & n3756; + assign n4359 = n3857 & \[13460] & n3702; + assign n4360 = n3857 & n3800 & \[6095] & n3756; + assign n4361 = ppeaks_8_8_ & (n5708 | n5709); + assign n4362 = n3801 & \[5975] & n3756; + assign n4363_1 = \[15140] & (n3968 | n5701 | n5702); + assign n4364 = \[10070] & n3804 & (n5627 | n5628); + assign n4365 = n3843 & n3796 & ppeaka_4_4_ & n3756; + assign n4366 = n3957_1 & \[15860] & n3756; + assign n4367 = n3811 & \[9920] & n3756; + assign n4368_1 = n3962_1 & ppeakb_3_3_ & n3756; + assign n4369 = n3819 & \[15245] & n3756; + assign n4370 = n3808 & \[4910] & n3756; + assign n4371 = n3800 & \[13625] & n3756; + assign n4372 = n3814 & n3796 & \[13355] & n3756; + assign n4373_1 = n3803 & \[8960] & n3756; + assign n4374 = n3815 & n3796 & ~ppeaka_3_3_ & n3756; + assign n4375 = n3815 & n3796 & ~ppeakb_3_3_ & n3756; + assign n4376 = ppeakp_3_3_ & (n3702 | (n3756 & n3828)); + assign n4377 = n3806 & \[15560] & n3756; + assign n4378_1 = ppeaka_3_3_ & ((n3756 & n3801) | n3968); + assign n4379 = n3857 & n3811 & \[11510] & n3756; + assign n4380 = n3857 & n3819 & \[7190] & n3756; + assign n4381 = n3957_1 & n3857 & \[15845] & n3756; + assign n4382 = n3857 & n3808 & \[14660] & n3756; + assign n4383_1 = n3857 & n3806 & \[4415] & n3756; + assign n4384 = n3857 & n3803 & \[4940] & n3756; + assign n4385 = n3857 & n3800 & \[7775] & n3756; + assign n4386 = ppeaka_12_12_ & ((n3756 & n3801) | n3968); + assign n4387_1 = n3966 & ppeaka_9_9_ & n3756; + assign n4388 = n3821 & \[4520] & n3756; + assign n4389 = n3802_1 & \[7850] & n3756; + assign n4390 = n3876 & \[15275] & n3756; + assign n4391 = n3800 & \[14855] & n3756; + assign n4392_1 = n3814 & n3796 & \[15185] & n3756; + assign n4393 = n3803 & \[6680] & n3756; + assign n4394 = n3815 & n3796 & \[8390] & n3756; + assign n4395 = n3801 & \[5990] & n3756; + assign n4396 = ppeakb_9_9_ & ((n3756 & n3960) | n3968); + assign n4397_1 = \[5720] & n3804 & (n5627 | n5628); + assign n4398 = ~preset & \[15080] & (~\[17791] | \[17843] ); + assign n4399 = ~preset & \[15050] & (~\[17427] | \[17648] ); + assign n4400 = ~preset & \[15035] & (~\[17427] | \[17648] ); + assign n4401 = ~preset & \[15020] & (~n3798 | ~n5733); + assign n4402_1 = ~preset & \[15005] & (~n3798 | ~n5732); + assign n4403 = n3962 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4404 = ~preset & \[14990] & (~n3798 | ~n5731); + assign n4405 = n4547 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4406 = ~preset & \[14975] & (\[18103] | ~\[18168] ); + assign n4407_1 = n3715 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4408 = n4427 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4409 = ~preset & \[14915] & (~n3798 | ~n5733); + assign n4410 = n5733 & n3798 & ~preset & pdata_3_3_; + assign n4411 = ~preset & \[14900] & (~n3798 | ~n5732); + assign n4412_1 = n5732 & n3798 & ~preset & pdata_8_8_; + assign n4413 = ~preset & \[14885] & (~n3798 | ~n5731); + assign n4414 = n5731 & n3798 & ~preset & pdata_13_13_; + assign n4415 = ~preset & \[14870] & (~\[17167] | \[17362] ); + assign n4416 = ~preset & \[14825] & (~\[17102] | \[17154] ); + assign n4417_1 = ppeaka_14_14_ & (n5577 | n5720); + assign n4418 = n3963 & \[11525] & n3874_1; + assign n4419 = ppeakp_14_14_ & (n5722 | n5723 | n5725); + assign n4420 = n3801 & ppeakb_14_14_ & n3756; + assign n4421 = n3857 & n3827_1 & \[9590] & n3756; + assign n4422_1 = n3963 & n3874_1 & \[11045] & n3857; + assign n4423 = n3857 & n3826 & \[12440] & n3756; + assign n4424 = n3857 & n3808 & \[15770] & n3756; + assign n4425 = n3857 & n3806 & \[10685] & n3756; + assign n4426 = n3857 & n3812_1 & \[5465] & n3756; + assign n4427_1 = n3857 & n3801 & \[8780] & n3756; + assign n4428 = n3876 & n3857 & \[14165] & n3756; + assign n4429 = n3857 & n3821 & \[4745] & n3756; + assign n4430 = n3857 & n3802_1 & \[11135] & n3756; + assign n4431 = n3857 & n3803 & \[9470] & n3756; + assign n4432_1 = n3857 & \[13820] & n3702; + assign n4433 = n3857 & n3800 & \[5405] & n3756; + assign n4434 = ppeaks_9_9_ & (n5708 | n5709); + assign n4435 = n3801 & \[5270] & n3756; + assign n4436 = \[14765] & (n3968 | n5701 | n5702); + assign n4437_1 = \[12875] & n3804 & (n5627 | n5628); + assign n4438 = n3843 & n3796 & ppeaka_3_3_ & n3756; + assign n4439 = n3957_1 & \[15515] & n3756; + assign n4440 = n3811 & \[11720] & n3756; + assign n4441 = n3962_1 & ppeakb_2_2_ & n3756; + assign n4442_1 = n3819 & \[7805] & n3756; + assign n4443 = n3808 & \[6980] & n3756; + assign n4444 = n3800 & \[14000] & n3756; + assign n4445 = n3814 & n3796 & \[13715] & n3756; + assign n4446 = n3803 & \[9635] & n3756; + assign n4447_1 = n3815 & n3796 & ~ppeaka_2_2_ & n3756; + assign n4448 = n3815 & n3796 & ~ppeakb_2_2_ & n3756; + assign n4449 = ppeakp_2_2_ & (n3702 | (n3756 & n3828)); + assign n4450 = n3806 & \[5105] & n3756; + assign n4451 = ppeaka_2_2_ & ((n3756 & n3801) | n3968); + assign n4452_1 = n3857 & n3811 & \[10190] & n3756; + assign n4453 = n3962_1 & n3857 & ppeakb_13_13_ & n3756; + assign n4454 = n3857 & n3819 & \[14015] & n3756; + assign n4455 = n3957_1 & n3857 & \[15500] & n3756; + assign n4456 = n3857 & n3808 & \[14240] & n3756; + assign n4457_1 = n3857 & n3806 & \[15920] & n3756; + assign n4458 = n3857 & n3803 & \[5645] & n3756; + assign n4459 = n3857 & n3800 & \[8420] & n3756; + assign n4460 = ppeaka_13_13_ & ((n3756 & n3801) | n3968); + assign n4461 = n3966 & ppeaka_8_8_ & n3756; + assign n4462_1 = n3821 & \[6605] & n3756; + assign n4463 = n3802_1 & \[14030] & n3756; + assign n4464 = n3876 & \[14900] & n3756; + assign n4465 = n3800 & \[8435] & n3756; + assign n4466_1 = n3814 & n3796 & \[5810] & n3756; + assign n4467 = n3803 & \[6005] & n3756; + assign n4468 = n3815 & n3796 & \[9050] & n3756; + assign n4469 = n3801 & \[6665] & n3756; + assign n4470_1 = ppeakb_8_8_ & ((n3756 & n3960) | n3968); + assign n4471 = \[6410] & n3804 & (n5627 | n5628); + assign n4472 = ~preset & \[14705] & (~\[17791] | \[17843] ); + assign n4473 = ~preset & \[14630] & (~\[17427] | \[17648] ); + assign n4474 = ~n3825 & ~preset & \[14615] ; + assign n4475_1 = ~preset & \[14600] & (~n3798 | ~n5733); + assign n4476 = n4106 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4477 = ~preset & \[14585] & (~n3798 | ~n5732); + assign n4478 = n3962 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4479 = ~preset & \[14570] & (~n3798 | ~n5732); + assign n4480_1 = ~preset & \[14555] & (\[18103] | ~\[18168] ); + assign n4481 = n3715 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4482 = n4427 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4483 = n4427 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4484 = ~preset & \[14510] & (\[17310] | ~\[17388] ); + assign n4485_1 = ~preset & \[14495] & (~n3798 | ~n5733); + assign n4486 = n5733 & n3798 & ~preset & pdata_4_4_; + assign n4487 = ~preset & \[14480] & (~n3798 | ~n5732); + assign n4488 = n5732 & n3798 & ~preset & pdata_11_11_; + assign n4489_1 = ~preset & \[14465] & (~n3798 | ~n5732); + assign n4490 = n5732 & n3798 & ~preset & pdata_2_2_; + assign n4491 = ~preset & \[14450] & (~\[17284] | \[18376] ); + assign n4492 = ~preset & \[14435] & (~\[17167] | \[17362] ); + assign n4493 = ~preset & \[14405] & (~\[17102] | \[17154] ); + assign n4494_1 = ~preset & \[14375] & (~\[17453] | \[18246] ); + assign n4495 = ~preset & \[14360] & (~\[17453] | \[18246] ); + assign n4496 = ppeaka_4_4_ & (n5577 | n5720); + assign n4497 = n3963 & \[15440] & n3874_1; + assign n4498 = ppeakp_4_4_ & (n5722 | n5723 | n5725); + assign n4499_1 = n3801 & ppeakb_4_4_ & n3756; + assign n4500 = n3843 & n3796 & ppeaka_2_2_ & n3756; + assign n4501 = n3957_1 & \[5030] & n3756; + assign n4502 = n3811 & \[11495] & n3756; + assign n4503 = n3962_1 & ppeakb_1_1_ & n3756; + assign n4504_1 = n3819 & \[7175] & n3756; + assign n4505 = n3808 & \[6305] & n3756; + assign n4506 = n3800 & \[14420] & n3756; + assign n4507 = n3814 & n3796 & \[15680] & n3756; + assign n4508 = n3803 & \[4925] & n3756; + assign n4509_1 = n3815 & n3796 & ~ppeaka_1_1_ & n3756; + assign n4510 = n3815 & n3796 & ~ppeakb_1_1_ & n3756; + assign n4511 = ppeakp_1_1_ & (n3702 | (n3756 & n3828)); + assign n4512 = n3806 & \[4400] & n3756; + assign n4513 = ppeaka_1_1_ & ((n3756 & n3801) | n3968); + assign n4514_1 = n3843 & n3796 & ppeaka_11_11_ & n3756; + assign n4515 = n3957_1 & \[5015] & n3756; + assign n4516 = n3811 & \[11015] & n3756; + assign n4517 = n3962_1 & ppeakb_10_10_ & n3756; + assign n4518_1 = n3819 & \[8465] & n3756; + assign n4519 = n3808 & \[13850] & n3756; + assign n4520 = n3800 & \[6515] & n3756; + assign n4521 = n3814 & n3796 & \[14960] & n3756; + assign n4522 = n3803 & \[11705] & n3756; + assign n4523_1 = n3815 & n3796 & ~ppeaka_10_10_ & n3756; + assign n4524 = n3815 & n3796 & ~ppeakb_10_10_ & n3756; + assign n4525 = ppeakp_10_10_ & (n3702 | (n3756 & n3828)); + assign n4526 = n3806 & \[13610] & n3756; + assign n4527 = ppeaka_10_10_ & ((n3756 & n3801) | n3968); + assign n4528_1 = n3966 & ppeaka_3_3_ & n3756; + assign n4529 = n3821 & \[8510] & n3756; + assign n4530 = n3802_1 & \[4490] & n3756; + assign n4531 = n3876 & \[14045] & n3756; + assign n4532 = n3800 & \[6530] & n3756; + assign n4533_1 = n3814 & n3796 & \[7760] & n3756; + assign n4534 = n3803 & \[7940] & n3756; + assign n4535 = n3815 & n3796 & \[13220] & n3756; + assign n4536 = n3801 & \[9215] & n3756; + assign n4537_1 = ppeakb_3_3_ & ((n3756 & n3960) | n3968); + assign n4538 = \[15860] & n3804 & (n5627 | n5628); + assign n4539 = ~preset & \[14285] & (~\[17791] | \[17843] ); + assign n4540 = ~preset & \[14225] & (\[17999] | ~\[18077] ); + assign n4541 = ~preset & \[14210] & (~\[17427] | \[17648] ); + assign n4542_1 = ~preset & \[14180] & (~n3798 | ~n5733); + assign n4543 = ~preset & \[14165] & (~n3798 | ~n5732); + assign n4544 = ~preset & \[14150] & (~n3798 | ~n5732); + assign n4545 = n3962 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4546 = ~preset & \[14135] & (\[18103] | ~\[18168] ); + assign n4547_1 = n4427 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4548 = ~preset & \[14090] & (\[17310] | ~\[17388] ); + assign n4549 = ~preset & \[14075] & (~n3798 | ~n5733); + assign n4550 = n5733 & n3798 & ~preset & pdata_5_5_; + assign n4551 = ~preset & \[14060] & (~n3798 | ~n5732); + assign n4552_1 = n5732 & n3798 & ~preset & pdata_10_10_; + assign n4553 = ~preset & \[14045] & (~n3798 | ~n5732); + assign n4554 = n5732 & n3798 & ~preset & pdata_3_3_; + assign n4555 = ~preset & \[14030] & (~\[17284] | \[18376] ); + assign n4556 = ~preset & \[14015] & (~\[17167] | \[17362] ); + assign n4557_1 = ~preset & \[13985] & (~\[17102] | \[17154] ); + assign n4558 = ~preset & \[13970] & (~\[17102] | \[17154] ); + assign n4559 = ~preset & \[13955] & (~\[17453] | \[18246] ); + assign n4560 = ppeaka_5_5_ & (n5577 | n5720); + assign n4561_1 = n3963 & \[15080] & n3874_1; + assign n4562 = ppeakp_5_5_ & (n5722 | n5723 | n5725); + assign n4563 = n3801 & ppeakb_5_5_ & n3756; + assign n4564 = n3843 & n3796 & ppeaka_1_1_ & n3756; + assign n4565_1 = n3957_1 & \[4310] & n3756; + assign n4566 = n3811 & \[11255] & n3756; + assign n4567 = n3962_1 & ppeakb_0_0_ & n3756; + assign n4568 = n3819 & \[9110] & n3756; + assign n4569 = n3808 & \[8240] & n3756; + assign n4570_1 = n3800 & \[14840] & n3756; + assign n4571 = n3814 & n3796 & \[16025] & n3756; + assign n4572 = n3803 & \[11480] & n3756; + assign n4573 = n3815 & n3796 & ~ppeaka_0_0_ & n3756; + assign n4574_1 = n3815 & n3796 & ~ppeakb_0_0_ & n3756; + assign n4575 = ppeakp_0_0_ & (n3702 | (n3756 & n3828)); + assign n4576 = n3806 & \[13970] & n3756; + assign n4577 = ppeaka_0_0_ & ((n3756 & n3801) | n3968); + assign n4578 = n3857 & n3811 & \[11735] & n3756; + assign n4579_1 = n3962_1 & n3857 & ppeakb_11_11_ & n3756; + assign n4580 = n3857 & n3819 & \[7820] & n3756; + assign n4581 = n3957_1 & n3857 & \[4295] & n3756; + assign n4582 = n3857 & n3808 & \[13490] & n3756; + assign n4583 = n3857 & n3806 & \[5120] & n3756; + assign n4584_1 = n3857 & n3803 & \[9650] & n3756; + assign n4585 = n3857 & n3800 & \[7145] & n3756; + assign n4586 = ppeaka_11_11_ & ((n3756 & n3801) | n3968); + assign n4587 = ~preset & \[13895] & (~\[17791] | \[17843] ); + assign n4588 = \[13880] & n3763_1; + assign n4589_1 = ~preset & \[13835] & (\[17999] | ~\[18077] ); + assign n4590 = ~preset & \[13820] & (~\[17427] | \[17648] ); + assign n4591 = ~preset & \[13790] & (~n3798 | ~n5733); + assign n4592 = n4106 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4593 = ~preset & \[13775] & (~n3798 | ~n5732); + assign n4594_1 = ~preset & \[13745] & (\[18103] | ~\[18168] ); + assign n4595 = n3715 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4596 = n4427 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4597 = n4160 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4598_1 = ~preset & \[13685] & (~n3798 | ~n5733); + assign n4599 = n5733 & n3798 & ~preset & pdata_6_6_; + assign n4600 = ~preset & \[13670] & (~n3798 | ~n5732); + assign n4601 = n5732 & n3798 & ~preset & pdata_13_13_; + assign n4602 = ~preset & \[13655] & (~n3798 | ~n5732); + assign n4603 = n5732 & n3798 & ~preset & pdata_0_0_; + assign n4604 = ~preset & \[13640] & (~n3798 | ~n5731); + assign n4605 = n5731 & n3798 & ~preset & pdata_2_2_; + assign n4606 = ~preset & \[13610] & (~\[17102] | \[17154] ); + assign n4607 = ~preset & \[13580] & (~\[17453] | \[18246] ); + assign n4608 = ppeaka_6_6_ & (n5577 | n5720); + assign n4609 = n3963 & \[14705] & n3874_1; + assign n4610 = ppeakp_6_6_ & (n5722 | n5723 | n5725); + assign n4611 = n3801 & ppeakb_6_6_ & n3756; + assign n4612 = n3801 & \[6650] & n3756; + assign n4613 = \[13550] & (n3968 | n5701 | n5702); + assign n4614 = \[10355] & n3804 & (n5627 | n5628); + assign n4615 = n3966 & n3857 & ppeaka_5_5_ & n3756; + assign n4616 = n3857 & n3812_1 & \[14075] & n3756; + assign n4617 = n3857 & n3801 & \[7910] & n3756; + assign n4618 = n3876 & n3857 & \[5240] & n3756; + assign n4619 = n3857 & n3821 & \[7235] & n3756; + assign n4620 = n3857 & n3802_1 & \[5885] & n3756; + assign n4621 = n3857 & n3803 & \[9245] & n3756; + assign n4622 = n3857 & \[8330] & n3702; + assign n4623 = n3857 & n3800 & \[7790] & n3756; + assign n4624 = ppeakb_5_5_ & ((n3756 & n3960) | n3968); + assign n4625 = ~preset & \[13475] & (\[17999] | ~\[18077] ); + assign n4626 = ~preset & \[13460] & (~\[17427] | \[17648] ); + assign n4627 = ~preset & \[13430] & (~n3798 | ~n5733); + assign n4628 = n4106 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4629 = ~preset & \[13415] & (~n3798 | ~n5732); + assign n4630 = n3962 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n4631 = ~preset & \[13400] & (~n3798 | ~n5732); + assign n4632 = ~preset & \[13385] & (\[18103] | ~\[18168] ); + assign n4633 = n3715 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4634 = ~preset & \[13340] & (~n3798 | ~n5733); + assign n4635 = n5733 & n3798 & ~preset & pdata_7_7_; + assign n4636 = ~preset & \[13325] & (~n3798 | ~n5732); + assign n4637 = n5732 & n3798 & ~preset & pdata_12_12_; + assign n4638 = ~preset & \[13310] & (~n3798 | ~n5732); + assign n4639 = n5732 & n3798 & ~preset & pdata_1_1_; + assign n4640 = ~preset & \[13295] & (~n3798 | ~n5731); + assign n4641 = n5731 & n3798 & ~preset & pdata_1_1_; + assign n4642 = ~preset & \[13265] & (~\[17102] | \[17154] ); + assign n4643 = ~preset & \[13235] & (~\[17453] | \[18246] ); + assign n4644 = ~preset & \[13220] & (~\[17453] | \[18246] ); + assign n4645 = n3857 & n3811 & \[11270] & n3756; + assign n4646 = n3857 & n3819 & \[9125] & n3756; + assign n4647 = n3957_1 & n3857 & \[5720] & n3756; + assign n4648 = n3857 & n3808 & \[15770] & n3756; + assign n4649 = n3857 & n3806 & \[13265] & n3756; + assign n4650 = n3857 & n3803 & \[9905] & n3756; + assign n4651 = n3857 & n3800 & \[5825] & n3756; + assign n4652 = ppeaka_9_9_ & ((n3756 & n3801) | n3968); + assign n4653 = n3966 & n3857 & ppeaka_4_4_ & n3756; + assign n4654 = n3857 & n3812_1 & \[14495] & n3756; + assign n4655 = n3857 & n3801 & \[7280] & n3756; + assign n4656 = n3876 & n3857 & \[12545] & n3756; + assign n4657 = n3857 & n3821 & \[9170] & n3756; + assign n4658 = n3857 & n3802_1 & \[5195] & n3756; + assign n4659 = n3857 & n3803 & \[8585] & n3756; + assign n4660 = n3857 & \[14765] & n3702; + assign n4661 = n3857 & n3800 & \[5840] & n3756; + assign n4662 = ppeakb_4_4_ & ((n3756 & n3960) | n3968); + assign n4663 = ~preset & \[13130] & (\[17999] | ~\[18077] ); + assign n4664 = ~preset & \[13115] & (~\[17427] | \[17648] ); + assign n4665 = ~preset & \[13100] & (~\[17427] | \[17648] ); + assign n4666 = ~preset & \[13085] & (~n3798 | ~n5733); + assign n4667 = ~preset & \[13070] & (~n3798 | ~n5732); + assign n4668 = ~preset & \[13055] & (~n3798 | ~n5732); + assign n4669 = n3962 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4670 = ~preset & \[13040] & (\[18103] | ~\[18168] ); + assign n4671 = ~preset & \[13025] & (\[18103] | ~\[18168] ); + assign n4672 = ~preset & \[13010] & (~n3798 | ~n5733); + assign n4673 = n5733 & n3798 & ~preset & pdata_8_8_; + assign n4674 = ~preset & ppeaki_1_1_ & (~n3857 | n5630); + assign n4675 = \[10805] & (n5628 | (~n3955 & n3963)); + assign n4676 = ~preset & ppeaki_10_10_ & (~n3857 | n5630); + assign n4677 = \[12935] & (n5628 | (~n3955 & n3963)); + assign n4678 = ~preset & \[12935] & (~\[17570] | \[17635] ); + assign n4679 = ~preset & \[12875] & (\[17999] | ~\[18077] ); + assign n4680 = ~preset & \[12860] & (~\[17427] | \[17648] ); + assign n4681 = ~preset & \[12845] & (~\[17427] | \[17648] ); + assign n4682 = ~preset & \[12830] & (~n3798 | ~n5733); + assign n4683 = n4106 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4684 = ~preset & \[12815] & (~n3798 | ~n5732); + assign n4685 = n3962 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4686 = ~preset & \[12800] & (\[18103] | ~\[18168] ); + assign n4687 = n3715 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4688 = ~preset & \[12770] & (~n3798 | ~n5732); + assign n4689 = n5732 & n3798 & ~preset & pdata_14_14_; + assign n4690 = ~preset & ppeaki_0_0_ & (~n3857 | n5630); + assign n4691 = \[12695] & (n5628 | (~n3955 & n3963)); + assign n4692 = ~preset & ppeaki_11_11_ & (~n3857 | n5630); + assign n4693 = \[11600] & (n5628 | (~n3955 & n3963)); + assign n4694 = ~preset & \[12695] & (~\[17570] | \[17635] ); + assign n4695 = ~preset & \[12635] & (\[17999] | ~\[18077] ); + assign n4696 = ~preset & \[12620] & (~\[17427] | \[17648] ); + assign n4697 = ~preset & \[12605] & (~\[17427] | \[17648] ); + assign n4698 = ~preset & \[12590] & (~n3798 | ~n5733); + assign n4699 = n4106 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4700 = ~preset & \[12575] & (~n3798 | ~n5732); + assign n4701 = ~preset & \[12545] & (~n3798 | ~n5732); + assign n4702 = n5732 & n3798 & ~preset & pdata_4_4_; + assign n4703 = ~preset & ppeaki_3_3_ & (~n3857 | n5630); + assign n4704 = \[11345] & (n5628 | (~n3955 & n3963)); + assign n4705 = ~preset & ppeaki_12_12_ & (~n3857 | n5630); + assign n4706 = ~preset & \[12485] & (~\[17570] | \[17635] ); + assign n4707 = ~preset & \[12470] & (\[18142] | ~\[18220] ); + assign n4708 = \[12425] & n3734; + assign n4709 = ~preset & \[12410] & (\[17999] | ~\[18077] ); + assign n4710 = ~preset & \[12395] & (~\[17427] | \[17648] ); + assign n4711 = ~preset & \[12380] & (~\[17427] | \[17648] ); + assign n4712 = ~preset & \[12365] & (~n3798 | ~n5732); + assign n4713 = ~preset & \[12350] & (~n3798 | ~n5732); + assign n4714 = n3962 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4715 = n4427 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4716 = ~preset & ppeaki_2_2_ & (~n3857 | n5630); + assign n4717 = \[11585] & (n5628 | (~n3955 & n3963)); + assign n4718 = ~preset & ppeaki_13_13_ & (~n3857 | n5630); + assign n4719 = ~preset & \[12275] & (~\[17570] | \[17635] ); + assign n4720 = ~preset & \[12260] & (\[18142] | ~\[18220] ); + assign n4721 = n3966 & ppeaka_13_13_ & n3756; + assign n4722 = n3821 & \[14885] & n3756; + assign n4723 = n3802_1 & \[5210] & n3756; + assign n4724 = n3876 & \[13670] & n3756; + assign n4725 = n3800 & \[4460] & n3756; + assign n4726 = n3814 & n3796 & \[13595] & n3756; + assign n4727 = n3803 & \[7325] & n3756; + assign n4728 = n3815 & n3796 & \[14375] & n3756; + assign n4729 = n3801 & \[8570] & n3756; + assign n4730 = ppeakb_13_13_ & ((n3756 & n3960) | n3968); + assign n4731 = \[15500] & n3804 & (n5627 | n5628); + assign n4732 = ~preset & \[12200] & (~\[17570] | \[17635] ); + assign n4733 = ~preset & \[12185] & (~\[17570] | \[17635] ); + assign n4734 = ~preset & \[12170] & (\[18142] | ~\[18220] ); + assign n4735 = ~preset & \[12155] & (~\[17414] | \[17505] ); + assign n4736 = ~preset & \[12140] & (~\[17791] | \[17843] ); + assign n4737 = ~preset & ppeaki_7_7_ & (~n3857 | n5630); + assign n4738 = \[12065] & (n5628 | (~n3955 & n3963)); + assign n4739 = ~preset & \[12080] & (~\[17570] | \[17635] ); + assign n4740 = ~preset & \[12065] & (~\[17570] | \[17635] ); + assign n4741 = ~preset & \[12050] & (\[18142] | ~\[18220] ); + assign n4742 = ~preset & \[12035] & (~\[17414] | \[17505] ); + assign n4743 = ~preset & \[12020] & (~\[17791] | \[17843] ); + assign n4744 = n3966 & ppeaka_15_15_ & n3756; + assign n4745 = n3821 & \[15620] & n3756; + assign n4746 = n3802_1 & \[6590] & n3756; + assign n4747 = n3876 & \[4535] & n3756; + assign n4748 = n3800 & \[8450] & n3756; + assign n4749 = n3814 & n3796 & \[14390] & n3756; + assign n4750 = n3803 & \[8600] & n3756; + assign n4751 = n3815 & n3796 & \[13580] & n3756; + assign n4752 = n3801 & \[7295] & n3756; + assign n4753 = ppeakb_15_15_ & ((n3756 & n3960) | n3968); + assign n4754 = \[13550] & n3804 & (n5627 | n5628); + assign n4755 = ~preset & ppeaki_8_8_ & (~n3857 | n5630); + assign n4756 = \[12485] & (n5628 | (~n3955 & n3963)); + assign n4757 = ~preset & \[11930] & (~\[17570] | \[17635] ); + assign n4758 = ~preset & \[11915] & (\[18142] | ~\[18220] ); + assign n4759 = ~preset & \[11900] & (~\[17414] | \[17505] ); + assign n4760 = ~preset & \[11885] & (~\[17414] | \[17505] ); + assign n4761 = n3966 & n3857 & ppeaka_14_14_ & n3756; + assign n4762 = n3857 & n3812_1 & \[7250] & n3756; + assign n4763 = n3857 & n3801 & \[7925] & n3756; + assign n4764 = n3876 & n3857 & \[12770] & n3756; + assign n4765 = n3857 & n3821 & \[15965] & n3756; + assign n4766 = n3857 & n3802_1 & \[4505] & n3756; + assign n4767 = n3857 & n3803 & \[9260] & n3756; + assign n4768 = n3857 & \[15140] & n3702; + assign n4769 = n3857 & n3800 & \[5165] & n3756; + assign n4770 = ppeakb_14_14_ & ((n3756 & n3960) | n3968); + assign n4771 = ~preset & ppeaki_9_9_ & (~n3857 | n5630); + assign n4772 = \[12275] & (n5628 | (~n3955 & n3963)); + assign n4773 = ~preset & \[11810] & (~\[17570] | \[17635] ); + assign n4774 = ~preset & \[11795] & (\[18142] | ~\[18220] ); + assign n4775 = ~preset & \[11780] & (~\[17414] | \[17505] ); + assign n4776 = ~preset & \[11765] & (~\[17414] | \[17505] ); + assign n4777 = ~preset & \[11750] & (~\[17791] | \[17843] ); + assign n4778 = ~preset & \[11675] & (\[17037] | ~\[18025] ); + assign n4779 = ~preset & \[11660] & (\[17037] | ~\[18025] ); + assign n4780 = ~preset & \[11615] & (~n3798 | ~n5731); + assign n4781 = ~preset & \[11600] & (~\[17570] | \[17635] ); + assign n4782 = ~preset & \[11585] & (~\[17570] | \[17635] ); + assign n4783 = ~preset & \[11570] & (\[18142] | ~\[18220] ); + assign n4784 = ~preset & \[11555] & (\[18142] | ~\[18220] ); + assign n4785 = ~preset & \[11540] & (~\[17414] | \[17505] ); + assign n4786 = ~preset & \[11525] & (~\[17791] | \[17843] ); + assign n4787 = ~preset & \[11450] & (\[17037] | ~\[18025] ); + assign n4788 = ~preset & \[11435] & (\[17037] | ~\[18025] ); + assign n4789 = n3723 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4790 = ~preset & \[11390] & (~n3798 | ~n5731); + assign n4791 = n4547 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n4792 = ~preset & \[11345] & (~\[17570] | \[17635] ); + assign n4793 = ~preset & \[11330] & (\[18142] | ~\[18220] ); + assign n4794 = ~preset & \[11315] & (\[18142] | ~\[18220] ); + assign n4795 = ~preset & \[11300] & (~\[17414] | \[17505] ); + assign n4796 = ~preset & \[11285] & (~\[17791] | \[17843] ); + assign n4797 = ~preset & \[11240] & (~\[17180] | \[17232] ); + assign n4798 = ~preset & \[11210] & (\[17037] | ~\[18025] ); + assign n4799 = ~preset & \[11195] & (\[17037] | ~\[18025] ); + assign n4800 = ~preset & \[11150] & (~n3798 | ~n5731); + assign n4801 = n4160 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4802 = ~preset & \[11090] & (~\[17570] | \[17635] ); + assign n4803 = ~preset & \[11075] & (\[18142] | ~\[18220] ); + assign n4804 = ~preset & \[11060] & (\[18142] | ~\[18220] ); + assign n4805 = ~preset & \[11045] & (~\[17414] | \[17505] ); + assign n4806 = ~preset & \[11030] & (~\[17791] | \[17843] ); + assign n4807 = ~preset & \[10955] & (\[17037] | ~\[18025] ); + assign n4808 = ~preset & \[10940] & (\[17037] | ~\[18025] ); + assign n4809 = n3723 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4810 = ~preset & \[10880] & (~n3798 | ~n5731); + assign n4811 = n4547 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4812 = n3718 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4813 = ~preset & \[10850] & (\[17310] | ~\[17388] ); + assign n4814 = ~preset & \[10820] & (~\[17570] | \[17635] ); + assign n4815 = ~preset & \[10805] & (~\[17570] | \[17635] ); + assign n4816 = ~preset & \[10790] & (\[18142] | ~\[18220] ); + assign n4817 = ~preset & \[10775] & (~\[17414] | \[17505] ); + assign n4818 = ~preset & \[10760] & (~\[17791] | \[17843] ); + assign n4819 = ~preset & \[10730] & (~\[17180] | \[17232] ); + assign n4820 = ~preset & \[10715] & (~\[17180] | \[17232] ); + assign n4821 = ~preset & \[10655] & (~\[17635] | \[17986] ); + assign n4822 = ~preset & \[10625] & (\[18311] | ~\[18506] ); + assign n4823 = ~preset & \[10610] & (\[18311] | ~\[18506] ); + assign n4824 = n3709 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n4825 = ~preset & \[10580] & (~\[18285] | \[18363] ); + assign n4826 = ~preset & \[10565] & (~\[18285] | \[18363] ); + assign n4827 = ~preset & \[10550] & (\[17310] | ~\[17388] ); + assign n4828 = ~preset & ppeaki_5_5_ & (~n3857 | n5630); + assign n4829 = \[11810] & (n5628 | (~n3955 & n3963)); + assign n4830 = ~preset & ppeaki_14_14_ & (~n3857 | n5630); + assign n4831 = ~preset & \[10505] & (\[18142] | ~\[18220] ); + assign n4832 = ~preset & \[10490] & (~\[17414] | \[17505] ); + assign n4833 = ~preset & \[10475] & (~\[17414] | \[17505] ); + assign n4834 = ~preset & \[10445] & (~\[17180] | \[17232] ); + assign n4835 = ~preset & \[10430] & (~\[17180] | \[17232] ); + assign n4836 = ~preset & \[10370] & (~\[17635] | \[17986] ); + assign n4837 = ~preset & \[10355] & (\[17999] | ~\[18077] ); + assign n4838 = n3721_1 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4839 = ~preset & \[10340] & (\[18311] | ~\[18506] ); + assign n4840 = n3721_1 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4841 = ~preset & \[10325] & (\[18311] | ~\[18506] ); + assign n4842 = ~preset & \[10280] & (~\[18285] | \[18363] ); + assign n4843 = n3716_1 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4844 = ~preset & ppeaki_4_4_ & (~n3857 | n5630); + assign n4845 = \[11930] & (n5628 | (~n3955 & n3963)); + assign n4846 = ~preset & ppeaki_15_15_ & (~n3857 | n5630); + assign n4847 = ~preset & \[10220] & (\[18142] | ~\[18220] ); + assign n4848 = ~preset & \[10205] & (~\[17414] | \[17505] ); + assign n4849 = ~preset & \[10145] & (~\[17180] | \[17232] ); + assign n4850 = ~preset & \[10085] & (~\[17635] | \[17986] ); + assign n4851 = ~preset & \[10070] & (\[17999] | ~\[18077] ); + assign n4852 = ~preset & \[10055] & (\[18311] | ~\[18506] ); + assign n4853 = \[10025] & n3710; + assign n4854 = ~preset & \[9950] & (\[18142] | ~\[18220] ); + assign n4855 = ~preset & \[9935] & (~\[17414] | \[17505] ); + assign n4856 = ~preset & \[9890] & (~\[17180] | \[17232] ); + assign n4857 = ~preset & \[9875] & (~\[17180] | \[17232] ); + assign n4858 = ~preset & \[9815] & (~\[17635] | \[17986] ); + assign n4859 = ~preset & \[9800] & (\[17999] | ~\[18077] ); + assign n4860 = n3721_1 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4861 = ~preset & \[9785] & (\[18311] | ~\[18506] ); + assign n4862 = n3709 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4863 = n3706_1 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4864 = n3706_1 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4865 = ~preset & ppeaki_6_6_ & (~n3857 | n5630); + assign n4866 = \[12185] & (n5628 | (~n3955 & n3963)); + assign n4867 = ~preset & \[9680] & (~\[17414] | \[17505] ); + assign n4868 = ~preset & \[9665] & (~\[17414] | \[17505] ); + assign n4869 = ~preset & \[9620] & (~\[17180] | \[17232] ); + assign n4870 = ~preset & \[9605] & (~\[17180] | \[17232] ); + assign n4871 = ~preset & \[9575] & (\[17037] | ~\[18025] ); + assign n4872 = ~preset & \[9530] & (~\[17635] | \[17986] ); + assign n4873 = ~preset & \[9515] & (~\[17635] | \[17986] ); + assign n4874 = ~preset & \[9500] & (\[17999] | ~\[18077] ); + assign n4875 = \[9455] & n3722; + assign n4876 = n3721_1 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4877 = ~preset & \[9440] & (\[18311] | ~\[18506] ); + assign n4878 = n3709 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4879 = ~preset & \[9395] & (~n3798 | ~n5733); + assign n4880 = ~preset & \[9380] & (~n3798 | ~n5731); + assign n4881 = n4547 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n4882 = ~preset & \[9335] & (~\[18285] | \[18363] ); + assign n4883 = n3716_1 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n4884 = ~preset & \[9320] & (~\[18285] | \[18363] ); + assign n4885 = n3716_1 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4886 = n3706_1 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4887 = n4160 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n4888 = ~preset & \[9260] & (\[17310] | ~\[17388] ); + assign n4889 = ~preset & \[9245] & (\[17310] | ~\[17388] ); + assign n4890 = ~preset & \[9170] & (~n3798 | ~n5731); + assign n4891 = n5731 & n3798 & ~preset & pdata_4_4_; + assign n4892 = ~preset & \[9155] & (~\[17284] | \[18376] ); + assign n4893 = ~preset & \[9140] & (~\[17284] | \[18376] ); + assign n4894 = ~preset & \[9125] & (~\[17167] | \[17362] ); + assign n4895 = ~preset & \[9110] & (~\[17167] | \[17362] ); + assign n4896 = ~preset & \[9050] & (~\[17453] | \[18246] ); + assign n4897 = ppeaka_0_0_ & (n5577 | n5720); + assign n4898 = n3963 & \[5675] & n3874_1; + assign n4899 = ppeakp_0_0_ & (n5722 | n5723 | n5725); + assign n4900 = n3801 & ppeakb_0_0_ & n3756; + assign n4901 = ppeaka_9_9_ & (n5577 | n5720); + assign n4902 = n3963 & \[11750] & n3874_1; + assign n4903 = ppeakp_9_9_ & (n5722 | n5723 | n5725); + assign n4904 = n3801 & ppeakb_9_9_ & n3756; + assign n4905 = n3857 & n3827_1 & \[12680] & n3756; + assign n4906 = n3963 & n3874_1 & \[10475] & n3857; + assign n4907 = n3857 & n3826 & \[15425] & n3756; + assign n4908 = n3857 & n3808 & \[6980] & n3756; + assign n4909 = n3857 & n3806 & \[10100] & n3756; + assign n4910 = n3857 & n3812_1 & \[14600] & n3756; + assign n4911 = n3857 & n3801 & \[10325] & n3756; + assign n4912 = n3876 & n3857 & \[14150] & n3756; + assign n4913 = n3857 & n3821 & \[10880] & n3756; + assign n4914 = n3857 & n3802_1 & \[8690] & n3756; + assign n4915 = n3857 & n3803 & \[5510] & n3756; + assign n4916 = n3857 & \[13100] & n3702; + assign n4917 = n3857 & n3800 & \[9320] & n3756; + assign n4918 = ppeaks_2_2_ & (n5708 | n5709); + assign n4919 = n3857 & n3827_1 & \[10130] & n3756; + assign n4920 = n3963 & n3874_1 & \[10490] & n3857; + assign n4921 = n3857 & n3826 & \[12125] & n3756; + assign n4922 = n3857 & n3808 & \[13490] & n3756; + assign n4923 = n3857 & n3806 & \[10115] & n3756; + assign n4924 = n3857 & n3812_1 & \[6830] & n3756; + assign n4925 = n3857 & n3801 & \[7505] & n3756; + assign n4926 = n3876 & n3857 & \[13415] & n3756; + assign n4927 = n3857 & n3821 & \[11390] & n3756; + assign n4928 = n3857 & n3802_1 & \[7430] & n3756; + assign n4929 = n3857 & n3803 & \[5525] & n3756; + assign n4930 = n3857 & \[13115] & n3702; + assign n4931 = n3857 & n3800 & \[9335] & n3756; + assign n4932 = ppeaks_11_11_ & (n5708 | n5709); + assign n4933 = ~preset & \[8945] & (~\[17180] | \[17232] ); + assign n4934 = ~preset & \[8930] & (~\[17180] | \[17232] ); + assign n4935 = ~preset & \[8900] & (\[17037] | ~\[18025] ); + assign n4936 = ~preset & \[8855] & (~\[17635] | \[17986] ); + assign n4937 = ~preset & \[8840] & (~\[17635] | \[17986] ); + assign n4938 = ~preset & \[8825] & (\[17999] | ~\[18077] ); + assign n4939 = n3723 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4940 = ~preset & \[8780] & (\[18311] | ~\[18506] ); + assign n4941 = n3709 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n4942 = ~preset & \[8735] & (~n3798 | ~n5733); + assign n4943 = ~preset & \[8720] & (~n3798 | ~n5731); + assign n4944 = n3718 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4945 = n3718 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n4946 = ~preset & \[8675] & (~\[18285] | \[18363] ); + assign n4947 = ~preset & \[8660] & (~\[18285] | \[18363] ); + assign n4948 = n3706_1 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n4949 = \[8630] & n3707; + assign n4950 = ~preset & \[8600] & (\[17310] | ~\[17388] ); + assign n4951 = ~preset & \[8585] & (\[17310] | ~\[17388] ); + assign n4952 = ~preset & \[8510] & (~n3798 | ~n5731); + assign n4953 = n5731 & n3798 & ~preset & pdata_3_3_; + assign n4954 = ~preset & \[8495] & (~\[17284] | \[18376] ); + assign n4955 = ~preset & \[8480] & (~\[17284] | \[18376] ); + assign n4956 = ~preset & \[8465] & (~\[17167] | \[17362] ); + assign n4957 = ~preset & \[8390] & (~\[17453] | \[18246] ); + assign n4958 = ppeaka_1_1_ & (n5577 | n5720); + assign n4959 = n3963 & \[4970] & n3874_1; + assign n4960 = ppeakp_1_1_ & (n5722 | n5723 | n5725); + assign n4961 = n3801 & ppeakb_1_1_ & n3756; + assign n4962 = ppeaka_8_8_ & (n5577 | n5720); + assign n4963 = n3963 & \[13895] & n3874_1; + assign n4964 = ppeakp_8_8_ & (n5722 | n5723 | n5725); + assign n4965 = n3801 & ppeakb_8_8_ & n3756; + assign n4966 = n3857 & n3827_1 & \[12455] & n3756; + assign n4967 = n3963 & n3874_1 & \[12155] & n3857; + assign n4968 = n3857 & n3826 & \[14255] & n3756; + assign n4969 = n3857 & n3808 & \[4910] & n3756; + assign n4970 = n3857 & n3806 & \[5570] & n3756; + assign n4971 = n3857 & n3812_1 & \[14180] & n3756; + assign n4972 = n3857 & n3801 & \[10610] & n3756; + assign n4973 = n3876 & n3857 & \[12575] & n3756; + assign n4974 = n3857 & n3821 & \[8720] & n3756; + assign n4975 = n3857 & n3802_1 & \[9350] & n3756; + assign n4976 = n3857 & n3803 & \[6200] & n3756; + assign n4977 = n3857 & \[12845] & n3702; + assign n4978 = n3857 & n3800 & \[7385] & n3756; + assign n4979 = ppeaks_3_3_ & (n5708 | n5709); + assign n4980 = n3801 & \[4565] & n3756; + assign n4981 = \[8330] & (n3968 | n5701 | n5702); + assign n4982 = \[12635] & n3804 & (n5627 | n5628); + assign n4983 = ~preset & \[8285] & (~\[17180] | \[17232] ); + assign n4984 = ~preset & \[8210] & (~\[17635] | \[17986] ); + assign n4985 = ~preset & \[8195] & (~\[17635] | \[17986] ); + assign n4986 = ~preset & \[8180] & (\[17999] | ~\[18077] ); + assign n4987 = ~preset & \[8150] & (\[18311] | ~\[18506] ); + assign n4988 = n3721_1 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4989 = ~preset & \[8135] & (\[18311] | ~\[18506] ); + assign n4990 = ~preset & \[8120] & (\[18311] | ~\[18506] ); + assign n4991 = n3709 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n4992 = ~preset & \[8090] & (~n3798 | ~n5733); + assign n4993 = n4106 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4994 = ~preset & \[8075] & (~n3798 | ~n5731); + assign n4995 = n3718 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n4996 = ~preset & \[8030] & (~\[18285] | \[18363] ); + assign n4997 = n3716_1 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n4998 = ~preset & \[8015] & (~\[18285] | \[18363] ); + assign n4999 = n3716_1 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n5000 = n3706_1 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n5001 = ~preset & \[7955] & (\[17310] | ~\[17388] ); + assign n5002 = ~preset & \[7940] & (\[17310] | ~\[17388] ); + assign n5003 = ~preset & \[7880] & (~n3798 | ~n5733); + assign n5004 = n5733 & n3798 & ~preset & pdata_15_15_; + assign n5005 = ~preset & \[7865] & (~n3798 | ~n5731); + assign n5006 = n5731 & n3798 & ~preset & pdata_6_6_; + assign n5007 = ~preset & \[7850] & (~\[17284] | \[18376] ); + assign n5008 = ~preset & \[7835] & (~\[17284] | \[18376] ); + assign n5009 = ~preset & \[7820] & (~\[17167] | \[17362] ); + assign n5010 = ~preset & \[7805] & (~\[17167] | \[17362] ); + assign n5011 = ~preset & \[7745] & (~\[17453] | \[18246] ); + assign n5012 = ppeaka_2_2_ & (n5577 | n5720); + assign n5013 = n3963 & ndout & n3874_1; + assign n5014 = ppeakp_2_2_ & (n5722 | n5723 | n5725); + assign n5015 = n3801 & ppeakb_2_2_ & n3756; + assign n5016 = ppeaka_7_7_ & (n5577 | n5720); + assign n5017 = n3963 & \[14285] & n3874_1; + assign n5018 = ppeakp_7_7_ & (n5722 | n5723 | n5725); + assign n5019 = n3801 & ppeakb_7_7_ & n3756; + assign n5020 = n3857 & n3827_1 & \[10700] & n3756; + assign n5021 = n3963 & n3874_1 & \[12035] & n3857; + assign n5022 = n3857 & n3826 & \[14690] & n3756; + assign n5023 = n3857 & n3808 & \[14240] & n3756; + assign n5024 = n3857 & n3806 & \[8885] & n3756; + assign n5025 = n3857 & n3812_1 & \[8090] & n3756; + assign n5026 = n3857 & n3801 & \[10340] & n3756; + assign n5027 = n3876 & n3857 & \[12815] & n3756; + assign n5028 = n3857 & n3821 & \[14990] & n3756; + assign n5029 = n3857 & n3802_1 & \[8705] & n3756; + assign n5030 = n3857 & n3803 & \[6890] & n3756; + assign n5031 = n3857 & \[12620] & n3702; + assign n5032 = n3857 & n3800 & \[8030] & n3756; + assign n5033 = ppeaks_13_13_ & (n5708 | n5709); + assign n5034 = n3801 & \[6635] & n3756; + assign n5035 = \[7685] & (n3968 | n5701 | n5702); + assign n5036 = \[12410] & n3804 & (n5627 | n5628); + assign n5037 = ~preset & \[7655] & (~\[17180] | \[17232] ); + assign n5038 = ~preset & \[7640] & (~\[17180] | \[17232] ); + assign n5039 = ~preset & \[7580] & (~\[17635] | \[17986] ); + assign n5040 = ~preset & \[7565] & (~\[17635] | \[17986] ); + assign n5041 = ~preset & \[7550] & (\[17999] | ~\[18077] ); + assign n5042 = n3723 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n5043 = n3721_1 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n5044 = ~preset & \[7505] & (\[18311] | ~\[18506] ); + assign n5045 = ~preset & \[7490] & (\[18311] | ~\[18506] ); + assign n5046 = ~preset & \[7460] & (~n3798 | ~n5733); + assign n5047 = ~preset & \[7445] & (~n3798 | ~n5731); + assign n5048 = n4547 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n5049 = n3718 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n5050 = \[7415] & n3717; + assign n5051 = ~preset & \[7400] & (~\[18285] | \[18363] ); + assign n5052 = ~preset & \[7385] & (~\[18285] | \[18363] ); + assign n5053 = ~preset & \[7355] & (\[18103] | ~\[18168] ); + assign n5054 = n4160 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n5055 = ~preset & \[7325] & (\[17310] | ~\[17388] ); + assign n5056 = ~preset & \[7310] & (\[17310] | ~\[17388] ); + assign n5057 = ~preset & \[7250] & (~n3798 | ~n5733); + assign n5058 = n5733 & n3798 & ~preset & pdata_14_14_; + assign n5059 = ~preset & \[7235] & (~n3798 | ~n5731); + assign n5060 = n5731 & n3798 & ~preset & pdata_5_5_; + assign n5061 = ~preset & \[7220] & (~\[17284] | \[18376] ); + assign n5062 = ~preset & \[7205] & (~\[17167] | \[17362] ); + assign n5063 = ~preset & \[7190] & (~\[17167] | \[17362] ); + assign n5064 = ~preset & \[7175] & (~\[17167] | \[17362] ); + assign n5065 = ~preset & \[7115] & (~\[17453] | \[18246] ); + assign n5066 = ppeaka_3_3_ & (n5577 | n5720); + assign n5067 = n3963 & \[15785] & n3874_1; + assign n5068 = ppeakp_3_3_ & (n5722 | n5723 | n5725); + assign n5069 = n3801 & ppeakb_3_3_ & n3756; + assign n5070 = n3857 & n3827_1 & \[12920] & n3756; + assign n5071 = n3963 & n3874_1 & \[9665] & n3857; + assign n5072 = n3857 & n3826 & \[12005] & n3756; + assign n5073 = n3857 & n3808 & \[6305] & n3756; + assign n5074 = n3857 & n3806 & \[9830] & n3756; + assign n5075 = n3857 & n3812_1 & \[15020] & n3756; + assign n5076 = n3857 & n3801 & \[8120] & n3756; + assign n5077 = n3876 & n3857 & \[14570] & n3756; + assign n5078 = n3857 & n3821 & \[11150] & n3756; + assign n5079 = n3857 & n3802_1 & \[8045] & n3756; + assign n5080 = n3857 & n3803 & \[4805] & n3756; + assign n5081 = n3857 & \[12380] & n3702; + assign n5082 = n3857 & n3800 & \[8660] & n3756; + assign n5083 = ppeaks_1_1_ & (n5708 | n5709); + assign n5084 = n3857 & n3827_1 & \[10415] & n3756; + assign n5085 = n3963 & n3874_1 & \[9680] & n3857; + assign n5086 = n3857 & n3826 & \[15065] & n3756; + assign n5087 = n3857 & n3808 & \[14660] & n3756; + assign n5088 = n3857 & n3806 & \[9845] & n3756; + assign n5089 = n3857 & n3812_1 & \[7460] & n3756; + assign n5090 = n3857 & n3801 & \[10625] & n3756; + assign n5091 = n3876 & n3857 & \[13775] & n3756; + assign n5092 = n3857 & n3821 & \[11615] & n3756; + assign n5093 = n3857 & n3802_1 & \[9365] & n3756; + assign n5094 = n3857 & n3803 & \[4820] & n3756; + assign n5095 = n3857 & \[12395] & n3702; + assign n5096 = n3857 & n3800 & \[8675] & n3756; + assign n5097 = ppeaks_12_12_ & (n5708 | n5709); + assign n5098 = n3801 & \[5960] & n3756; + assign n5099 = \[7055] & (n3968 | n5701 | n5702); + assign n5100 = \[6245] & n3804 & (n5627 | n5628); + assign n5101 = \[7010] & n3722; + assign n5102 = ~preset & \[6965] & (\[17037] | ~\[18025] ); + assign n5103 = ~preset & \[6950] & (\[17037] | ~\[18025] ); + assign n5104 = ~preset & \[6935] & (~\[17635] | \[17986] ); + assign n5105 = ~preset & \[6920] & (\[17999] | ~\[18077] ); + assign n5106 = n3723 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n5107 = n3723 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n5108 = ~preset & \[6830] & (~n3798 | ~n5733); + assign n5109 = n4106 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n5110 = ~preset & \[6815] & (~n3798 | ~n5731); + assign n5111 = n4547 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n5112 = n3718 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n5113 = ~preset & \[6770] & (~\[18285] | \[18363] ); + assign n5114 = n3716_1 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n5115 = ~preset & \[6725] & (\[18103] | ~\[18168] ); + assign n5116 = n4160 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n5117 = n4160 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n5118 = ~preset & \[6680] & (\[17310] | ~\[17388] ); + assign n5119 = ~preset & \[6620] & (~n3798 | ~n5733); + assign n5120 = n5733 & n3798 & ~preset & pdata_13_13_; + assign n5121 = ~preset & \[6605] & (~n3798 | ~n5731); + assign n5122 = n5731 & n3798 & ~preset & pdata_8_8_; + assign n5123 = ~preset & \[6590] & (~\[17284] | \[18376] ); + assign n5124 = ~preset & \[6575] & (~\[17284] | \[18376] ); + assign n5125 = ~preset & \[6560] & (~\[17167] | \[17362] ); + assign n5126 = ~preset & \[6470] & (~\[17453] | \[18246] ); + assign n5127 = ppeaka_13_13_ & (n5577 | n5720); + assign n5128 = n3963 & \[10760] & n3874_1; + assign n5129 = ppeakp_13_13_ & (n5722 | n5723 | n5725); + assign n5130 = n3801 & ppeakb_13_13_ & n3756; + assign n5131 = n3857 & n3827_1 & \[7625] & n3756; + assign n5132 = n3963 & n3874_1 & \[11300] & n3857; + assign n5133 = n3857 & n3826 & \[13865] & n3756; + assign n5134 = n3857 & n3808 & \[11690] & n3756; + assign n5135 = n3857 & n3806 & \[8870] & n3756; + assign n5136 = n3857 & n3812_1 & \[13085] & n3756; + assign n5137 = n3857 & n3801 & \[5495] & n3756; + assign n5138 = n3876 & n3857 & \[16085] & n3756; + assign n5139 = n3857 & n3821 & \[8075] & n3756; + assign n5140 = n3857 & n3802_1 & \[6110] & n3756; + assign n5141 = n3857 & n3803 & \[11165] & n3756; + assign n5142 = n3857 & \[14210] & n3702; + assign n5143 = n3857 & n3800 & \[10565] & n3756; + assign n5144 = ppeaks_6_6_ & (n5708 | n5709); + assign n5145 = n3857 & n3827_1 & \[6320] & n3756; + assign n5146 = n3963 & n3874_1 & \[11780] & n3857; + assign n5147 = n3857 & n3826 & \[13880] & n3756; + assign n5148 = n3857 & n3808 & \[12425] & n3756; + assign n5149 = n3857 & n3806 & \[4880] & n3756; + assign n5150 = n3857 & n3812_1 & \[9395] & n3756; + assign n5151 = n3857 & n3801 & \[8150] & n3756; + assign n5152 = n3876 & n3857 & \[12365] & n3756; + assign n5153 = n3857 & n3821 & \[15725] & n3756; + assign n5154 = n3857 & n3802_1 & \[4730] & n3756; + assign n5155 = n3857 & n3803 & \[11180] & n3756; + assign n5156 = n3857 & \[15050] & n3702; + assign n5157 = n3857 & n3800 & \[10580] & n3756; + assign n5158 = ppeaks_15_15_ & (n5708 | n5709); + assign n5159 = n3801 & \[7895] & n3756; + assign n5160 = \[6410] & (n3968 | n5701 | n5702); + assign n5161 = \[6920] & n3804 & (n5627 | n5628); + assign n5162 = n3966 & n3857 & ppeaka_2_2_ & n3756; + assign n5163 = n3857 & n3812_1 & \[15290] & n3756; + assign n5164 = n3857 & n3801 & \[8555] & n3756; + assign n5165 = n3876 & n3857 & \[14465] & n3756; + assign n5166 = n3857 & n3821 & \[13640] & n3756; + assign n5167 = n3857 & n3802_1 & \[9140] & n3756; + assign n5168 = n3857 & n3803 & \[7310] & n3756; + assign n5169 = n3857 & \[15515] & n3702; + assign n5170 = n3857 & n3800 & \[4445] & n3756; + assign n5171 = ppeakb_2_2_ & ((n3756 & n3960) | n3968); + assign n5172 = n3966 & n3857 & ppeaka_11_11_ & n3756; + assign n5173 = n3857 & n3812_1 & \[5255] & n3756; + assign n5174 = n3857 & n3801 & \[4595] & n3756; + assign n5175 = n3876 & n3857 & \[14480] & n3756; + assign n5176 = n3857 & n3821 & \[5930] & n3756; + assign n5177 = n3857 & n3802_1 & \[9155] & n3756; + assign n5178 = n3857 & n3803 & \[14090] & n3756; + assign n5179 = n3857 & \[4295] & n3702; + assign n5180 = n3857 & n3800 & \[5855] & n3756; + assign n5181 = ppeakb_11_11_ & ((n3756 & n3960) | n3968); + assign n5182 = \[6365] & n3738; + assign n5183 = \[6320] & n3751; + assign n5184 = ~preset & \[6290] & (\[17037] | ~\[18025] ); + assign n5185 = ~preset & \[6275] & (\[17037] | ~\[18025] ); + assign n5186 = ~preset & \[6260] & (~\[17635] | \[17986] ); + assign n5187 = ~preset & \[6245] & (\[17999] | ~\[18077] ); + assign n5188 = n3721_1 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n5189 = ~preset & \[6185] & (\[18311] | ~\[18506] ); + assign n5190 = n3709 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n5191 = ~preset & \[6155] & (~n3798 | ~n5733); + assign n5192 = n4106 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n5193 = ~preset & \[6140] & (~n3798 | ~n5731); + assign n5194 = n4547 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n5195 = ~preset & \[6125] & (~n3798 | ~n5731); + assign n5196 = ~preset & \[6095] & (~\[18285] | \[18363] ); + assign n5197 = n3716_1 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); + assign n5198 = n3706_1 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n5199 = ~preset & \[6050] & (\[18103] | ~\[18168] ); + assign n5200 = n3715 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n5201 = n4160 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n5202 = ~preset & \[6005] & (\[17310] | ~\[17388] ); + assign n5203 = ~preset & \[5945] & (~n3798 | ~n5733); + assign n5204 = n5733 & n3798 & ~preset & pdata_12_12_; + assign n5205 = ~preset & \[5930] & (~n3798 | ~n5731); + assign n5206 = n5731 & n3798 & ~preset & pdata_11_11_; + assign n5207 = ~preset & \[5915] & (~n3798 | ~n5731); + assign n5208 = n5731 & n3798 & ~preset & pdata_7_7_; + assign n5209 = ~preset & \[5900] & (~n3798 | ~n5731); + assign n5210 = n5731 & n3798 & ~preset & pdata_0_0_; + assign n5211 = ~preset & \[5885] & (~\[17284] | \[18376] ); + assign n5212 = ~preset & \[5870] & (~\[17167] | \[17362] ); + assign n5213 = ~preset & \[5780] & (~\[17453] | \[18246] ); + assign n5214 = ppeaka_12_12_ & (n5577 | n5720); + assign n5215 = n3963 & \[11030] & n3874_1; + assign n5216 = ppeakp_12_12_ & (n5722 | n5723 | n5725); + assign n5217 = n3801 & ppeakb_12_12_ & n3756; + assign n5218 = n3857 & n3827_1 & \[8255] & n3756; + assign n5219 = n3963 & n3874_1 & \[11540] & n3857; + assign n5220 = n3857 & n3826 & \[12905] & n3756; + assign n5221 = n3857 & n3808 & \[10970] & n3756; + assign n5222 = n3857 & n3806 & \[8225] & n3756; + assign n5223 = n3857 & n3812_1 & \[12830] & n3756; + assign n5224 = n3857 & n3801 & \[4790] & n3756; + assign n5225 = n3876 & n3857 & \[15005] & n3756; + assign n5226 = n3857 & n3821 & \[6140] & n3756; + assign n5227 = n3857 & n3802_1 & \[6785] & n3756; + assign n5228 = n3857 & n3803 & \[11405] & n3756; + assign n5229 = n3857 & \[14630] & n3702; + assign n5230 = n3857 & n3800 & \[6770] & n3756; + assign n5231 = ppeaks_7_7_ & (n5708 | n5709); + assign n5232 = n3857 & n3827_1 & \[10985] & n3756; + assign n5233 = n3963 & n3874_1 & \[11900] & n3857; + assign n5234 = n3857 & n3826 & \[14270] & n3756; + assign n5235 = n3857 & n3808 & \[12650] & n3756; + assign n5236 = n3857 & n3806 & \[9560] & n3756; + assign n5237 = n3857 & n3812_1 & \[8735] & n3756; + assign n5238 = n3857 & n3801 & \[10055] & n3756; + assign n5239 = n3876 & n3857 & \[13070] & n3756; + assign n5240 = n3857 & n3821 & \[16070] & n3756; + assign n5241 = n3857 & n3802_1 & \[5435] & n3756; + assign n5242 = n3857 & n3803 & \[6215] & n3756; + assign n5243 = n3857 & \[15410] & n3702; + assign n5244 = n3857 & n3800 & \[7400] & n3756; + assign n5245 = ppeaks_14_14_ & (n5708 | n5709); + assign n5246 = n3801 & \[7265] & n3756; + assign n5247 = \[5720] & (n3968 | n5701 | n5702); + assign n5248 = \[7550] & n3804 & (n5627 | n5628); + assign n5249 = n3857 & n3811 & \[6350] & n3756; + assign n5250 = n3857 & n3819 & \[4475] & n3756; + assign n5251 = n3957_1 & n3857 & \[6410] & n3756; + assign n5252 = n3857 & n3808 & \[11225] & n3756; + assign n5253 = n3857 & n3806 & \[14405] & n3756; + assign n5254 = n3857 & n3803 & \[10175] & n3756; + assign n5255 = n3857 & n3800 & \[5135] & n3756; + assign n5256 = ppeaka_8_8_ & ((n3756 & n3801) | n3968); + assign n5257 = n3966 & n3857 & ppeaka_10_10_ & n3756; + assign n5258 = n3857 & n3812_1 & \[4550] & n3756; + assign n5259 = n3857 & n3801 & \[5300] & n3756; + assign n5260 = n3876 & n3857 & \[14060] & n3756; + assign n5261 = n3857 & n3821 & \[5225] & n3756; + assign n5262 = n3857 & n3802_1 & \[7220] & n3756; + assign n5263 = n3857 & n3803 & \[10850] & n3756; + assign n5264 = n3857 & \[5015] & n3702; + assign n5265 = n3857 & n3800 & \[15230] & n3756; + assign n5266 = ppeakb_10_10_ & ((n3756 & n3960) | n3968); + assign n5267 = ~preset & \[5675] & (~\[17791] | \[17843] ); + assign n5268 = ~preset & \[5630] & (~\[17180] | \[17232] ); + assign n5269 = ~preset & \[5600] & (\[17037] | ~\[18025] ); + assign n5270 = ~preset & \[5555] & (~\[17635] | \[17986] ); + assign n5271 = n3723 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n5272 = n3723 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n5273 = ~preset & \[5495] & (\[18311] | ~\[18506] ); + assign n5274 = ~preset & \[5465] & (~n3798 | ~n5733); + assign n5275 = ~preset & \[5450] & (~n3798 | ~n5731); + assign n5276 = n4547 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n5277 = n3718 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n5278 = ~preset & \[5405] & (~\[18285] | \[18363] ); + assign n5279 = ~preset & \[5390] & (~\[18285] | \[18363] ); + assign n5280 = n3706_1 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n5281 = ~preset & \[5360] & (\[18103] | ~\[18168] ); + assign n5282 = n4160 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n5283 = \[5330] & n3713; + assign n5284 = ~preset & \[5315] & (\[17310] | ~\[17388] ); + assign n5285 = ~preset & \[5255] & (~n3798 | ~n5733); + assign n5286 = n5733 & n3798 & ~preset & pdata_11_11_; + assign n5287 = ~preset & \[5240] & (~n3798 | ~n5732); + assign n5288 = n5732 & n3798 & ~preset & pdata_5_5_; + assign n5289 = ~preset & \[5225] & (~n3798 | ~n5731); + assign n5290 = n5731 & n3798 & ~preset & pdata_10_10_; + assign n5291 = ~preset & \[5210] & (~\[17284] | \[18376] ); + assign n5292 = ~preset & \[5195] & (~\[17284] | \[18376] ); + assign n5293 = ~preset & \[5180] & (~\[17167] | \[17362] ); + assign n5294 = ~preset & \[5120] & (~\[17102] | \[17154] ); + assign n5295 = ~preset & \[5105] & (~\[17102] | \[17154] ); + assign n5296 = ~preset & \[5090] & (~\[17453] | \[18246] ); + assign n5297 = ~preset & \[5075] & (~\[17453] | \[18246] ); + assign n5298 = ppeaka_11_11_ & (n5577 | n5720); + assign n5299 = n3963 & \[12020] & n3874_1; + assign n5300 = ppeakp_11_11_ & (n5722 | n5723 | n5725); + assign n5301 = n3801 & ppeakb_11_11_ & n3756; + assign n5302 = n3857 & n3827_1 & \[12245] & n3756; + assign n5303 = n3963 & n3874_1 & \[11765] & n3857; + assign n5304 = n3857 & n3826 & \[14675] & n3756; + assign n5305 = n3857 & n3808 & \[5615] & n3756; + assign n5306 = n3857 & n3806 & \[4865] & n3756; + assign n5307 = n3857 & n3812_1 & \[13790] & n3756; + assign n5308 = n3857 & n3801 & \[9785] & n3756; + assign n5309 = n3876 & n3857 & \[12350] & n3756; + assign n5310 = n3857 & n3821 & \[9380] & n3756; + assign n5311 = n3857 & n3802_1 & \[4715] & n3756; + assign n5312 = n3857 & n3803 & \[6875] & n3756; + assign n5313 = n3857 & \[15035] & n3702; + assign n5314 = n3857 & n3800 & \[8015] & n3756; + assign n5315 = ppeaks_4_4_ & (n5708 | n5709); + assign n5316 = n3801 & \[9185] & n3756; + assign n5317 = \[5030] & (n3968 | n5701 | n5702); + assign n5318 = \[13835] & n3804 & (n5627 | n5628); + assign n5319 = n3801 & \[9200] & n3756; + assign n5320 = \[5015] & (n3968 | n5701 | n5702); + assign n5321 = \[8180] & n3804 & (n5627 | n5628); + assign n5322 = n3857 & n3811 & \[7025] & n3756; + assign n5323 = n3857 & n3819 & \[5180] & n3756; + assign n5324 = n3957_1 & n3857 & \[7055] & n3756; + assign n5325 = n3857 & n3808 & \[10970] & n3756; + assign n5326 = n3857 & n3806 & \[13985] & n3756; + assign n5327 = n3857 & n3803 & \[10460] & n3756; + assign n5328 = n3857 & n3800 & \[4430] & n3756; + assign n5329 = ppeaka_7_7_ & ((n3756 & n3801) | n3968); + assign n5330 = n3966 & n3857 & ppeaka_0_0_ & n3756; + assign n5331 = n3857 & n3812_1 & \[15995] & n3756; + assign n5332 = n3857 & n3801 & \[4580] & n3756; + assign n5333 = n3876 & n3857 & \[13655] & n3756; + assign n5334 = n3857 & n3821 & \[5900] & n3756; + assign n5335 = n3857 & n3802_1 & \[7835] & n3756; + assign n5336 = n3857 & n3803 & \[10550] & n3756; + assign n5337 = n3857 & \[4310] & n3702; + assign n5338 = n3857 & n3800 & \[15605] & n3756; + assign n5339 = ppeakb_0_0_ & ((n3756 & n3960) | n3968); + assign n5340 = ~preset & \[4970] & (~\[17791] | \[17843] ); + assign n5341 = ~preset & \[4895] & (\[17037] | ~\[18025] ); + assign n5342 = \[4880] & n3729; + assign n5343 = n3804 & ~\[17986] & \[11915] & \[17635] ; + assign n5344 = ppeakp_11_11_ & (n3807_1 | (~n3804 & n3805)); + assign n5345 = ~\[17648] & \[16100] & \[17427] ; + assign n5346 = ~\[17232] & \[10130] & \[17180] ; + assign n5347 = n3811 & n3798 & ppeaka_11_11_ & ~\[17245] ; + assign n5348 = \[18077] & \[13115] & ~\[17999] ; + assign n5349 = n3803 & n3798 & ppeakb_11_11_ & ~\[16933] ; + assign n5350 = n3804 & ~\[17986] & \[12050] & \[17635] ; + assign n5351 = ppeakp_12_12_ & (n3807_1 | (~n3804 & n3805)); + assign n5352 = ~\[17648] & \[15755] & \[17427] ; + assign n5353 = ~\[17232] & \[10415] & \[17180] ; + assign n5354 = n3811 & n3798 & ppeaka_12_12_ & ~\[17245] ; + assign n5355 = \[18077] & \[12395] & ~\[17999] ; + assign n5356 = n3803 & n3798 & ppeakb_12_12_ & ~\[16933] ; + assign n5357 = n3804 & ~\[17986] & \[12170] & \[17635] ; + assign n5358 = ppeakp_13_13_ & (n3807_1 | (~n3804 & n3805)); + assign n5359 = ~\[17648] & \[13805] & \[17427] ; + assign n5360 = ~\[17232] & \[10700] & \[17180] ; + assign n5361 = n3811 & n3798 & ppeaka_13_13_ & ~\[17245] ; + assign n5362 = \[18077] & \[12620] & ~\[17999] ; + assign n5363 = n3803 & n3798 & ppeakb_13_13_ & ~\[16933] ; + assign n5364 = n3804 & ~\[17986] & \[12260] & \[17635] ; + assign n5365 = ppeakp_14_14_ & (n3807_1 | (~n3804 & n3805)); + assign n5366 = ~\[17648] & \[13445] & \[17427] ; + assign n5367 = ~\[17232] & \[10985] & \[17180] ; + assign n5368 = n3811 & n3798 & ppeaka_14_14_ & ~\[17245] ; + assign n5369 = \[18077] & \[15410] & ~\[17999] ; + assign n5370 = n3803 & n3798 & ppeakb_14_14_ & ~\[16933] ; + assign n5371 = n3804 & ~\[17986] & \[12470] & \[17635] ; + assign n5372 = ppeakp_15_15_ & (n3807_1 | (~n3804 & n3805)); + assign n5373 = ~\[17648] & \[14615] & \[17427] ; + assign n5374 = ~\[17232] & \[6320] & \[17180] ; + assign n5375 = n3811 & n3798 & ppeaka_15_15_ & ~\[17245] ; + assign n5376 = \[18077] & \[15050] & ~\[17999] ; + assign n5377 = n3803 & n3798 & ppeakb_15_15_ & ~\[16933] ; + assign n5378 = ~preset & \[4850] & (~\[17635] | \[17986] ); + assign n5379 = n3804 & ~\[17986] & \[11075] & \[17635] ; + assign n5380 = ppeakp_7_7_ & (n3807_1 | (~n3804 & n3805)); + assign n5381 = ~\[17648] & \[5540] & \[17427] ; + assign n5382 = ~\[17232] & \[8255] & \[17180] ; + assign n5383 = n3811 & n3798 & ppeaka_7_7_ & ~\[17245] ; + assign n5384 = \[18077] & \[14630] & ~\[17999] ; + assign n5385 = n3803 & n3798 & ppeakb_7_7_ & ~\[16933] ; + assign n5386 = n3804 & ~\[17986] & \[11330] & \[17635] ; + assign n5387 = ppeakp_8_8_ & (n3807_1 | (~n3804 & n3805)); + assign n5388 = ~\[17648] & \[11420] & \[17427] ; + assign n5389 = ~\[17232] & \[8915] & \[17180] ; + assign n5390 = n3811 & n3798 & ppeaka_8_8_ & ~\[17245] ; + assign n5391 = \[18077] & \[13460] & ~\[17999] ; + assign n5392 = n3803 & n3798 & ppeakb_8_8_ & ~\[16933] ; + assign n5393 = n3804 & ~\[17986] & \[11570] & \[17635] ; + assign n5394 = ppeakp_9_9_ & (n3807_1 | (~n3804 & n3805)); + assign n5395 = ~\[17648] & \[11645] & \[17427] ; + assign n5396 = ~\[17232] & \[9590] & \[17180] ; + assign n5397 = n3811 & n3798 & ppeaka_9_9_ & ~\[17245] ; + assign n5398 = \[18077] & \[13820] & ~\[17999] ; + assign n5399 = n3803 & n3798 & ppeakb_9_9_ & ~\[16933] ; + assign n5400 = n3804 & ~\[17986] & \[11795] & \[17635] ; + assign n5401 = ppeakp_10_10_ & (n3807_1 | (~n3804 & n3805)); + assign n5402 = ~\[17648] & \[10925] & \[17427] ; + assign n5403 = ~\[17232] & \[9860] & \[17180] ; + assign n5404 = n3811 & n3798 & ppeaka_10_10_ & ~\[17245] ; + assign n5405 = \[18077] & \[12860] & ~\[17999] ; + assign n5406 = n3803 & n3798 & ppeakb_10_10_ & ~\[16933] ; + assign n5407 = n3803 & n3798 & ppeaka_0_0_ & ~\[16933] ; + assign n5408 = n3804 & ~\[17986] & \[11555] & \[17635] ; + assign n5409 = ppeakp_0_0_ & (n3807_1 | (~n3804 & n3805)); + assign n5410 = ~\[17648] & \[11630] & \[17427] ; + assign n5411 = ~\[17232] & \[13175] & \[17180] ; + assign n5412 = n3811 & n3798 & ppeaka_0_0_ & ~\[17245] ; + assign n5413 = \[18077] & \[12605] & ~\[17999] ; + assign n5414 = n3803 & n3798 & ppeakb_0_0_ & ~\[16933] ; + assign n5415 = n3804 & ~\[17986] & \[11315] & \[17635] ; + assign n5416 = ppeakp_1_1_ & (n3807_1 | (~n3804 & n3805)); + assign n5417 = ~\[17648] & \[9485] & \[17427] ; + assign n5418 = ~\[17232] & \[12920] & \[17180] ; + assign n5419 = n3811 & n3798 & ppeaka_1_1_ & ~\[17245] ; + assign n5420 = \[18077] & \[12380] & ~\[17999] ; + assign n5421 = n3803 & n3798 & ppeakb_1_1_ & ~\[16933] ; + assign n5422 = n3804 & ~\[17986] & \[11060] & \[17635] ; + assign n5423 = ppeakp_2_2_ & (n3807_1 | (~n3804 & n3805)); + assign n5424 = ~\[17648] & \[7535] & \[17427] ; + assign n5425 = ~\[17232] & \[12680] & \[17180] ; + assign n5426 = n3811 & n3798 & ppeaka_2_2_ & ~\[17245] ; + assign n5427 = \[18077] & \[13100] & ~\[17999] ; + assign n5428 = n3803 & n3798 & ppeakb_2_2_ & ~\[16933] ; + assign n5429 = n3804 & ~\[17986] & \[10790] & \[17635] ; + assign n5430 = ppeakp_3_3_ & (n3807_1 | (~n3804 & n3805)); + assign n5431 = ~\[17648] & \[8165] & \[17427] ; + assign n5432 = ~\[17232] & \[12455] & \[17180] ; + assign n5433 = n3811 & n3798 & ppeaka_3_3_ & ~\[17245] ; + assign n5434 = \[18077] & \[12845] & ~\[17999] ; + assign n5435 = n3803 & n3798 & ppeakb_3_3_ & ~\[16933] ; + assign n5436 = n3804 & ~\[17986] & \[10505] & \[17635] ; + assign n5437 = ppeakp_4_4_ & (n3807_1 | (~n3804 & n3805)); + assign n5438 = ~\[17648] & \[6230] & \[17427] ; + assign n5439 = ~\[17232] & \[12245] & \[17180] ; + assign n5440 = n3811 & n3798 & ppeaka_4_4_ & ~\[17245] ; + assign n5441 = \[18077] & \[15035] & ~\[17999] ; + assign n5442 = n3803 & n3798 & ppeakb_4_4_ & ~\[16933] ; + assign n5443 = n3804 & ~\[17986] & \[10220] & \[17635] ; + assign n5444 = ppeakp_5_5_ & (n3807_1 | (~n3804 & n3805)); + assign n5445 = ~\[17648] & \[6905] & \[17427] ; + assign n5446 = ~\[17232] & \[6995] & \[17180] ; + assign n5447 = n3811 & n3798 & ppeaka_5_5_ & ~\[17245] ; + assign n5448 = \[18077] & \[15395] & ~\[17999] ; + assign n5449 = n3803 & n3798 & ppeakb_5_5_ & ~\[16933] ; + assign n5450 = n3804 & ~\[17986] & \[9950] & \[17635] ; + assign n5451 = ppeakp_6_6_ & (n3807_1 | (~n3804 & n3805)); + assign n5452 = ~\[17648] & \[4835] & \[17427] ; + assign n5453 = ~\[17232] & \[7625] & \[17180] ; + assign n5454 = n3811 & n3798 & ppeaka_6_6_ & ~\[17245] ; + assign n5455 = \[18077] & \[14210] & ~\[17999] ; + assign n5456 = n3803 & n3798 & ppeakb_6_6_ & ~\[16933] ; + assign n5457 = n3721_1 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); + assign n5458 = ~preset & \[4790] & (\[18311] | ~\[18506] ); + assign n5459 = n3709 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); + assign n5460 = n3709 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); + assign n5461 = ~preset & \[4745] & (~n3798 | ~n5731); + assign n5462 = n5788 & ~n5468 & ~n5784; + assign n5463 = ~ppeaka_15_15_ & (~n3950 | (~n5532 & ~n5533)); + assign n5464 = ~\[18363] & \[6755] & \[18285] ; + assign n5465 = n3800 & n3798 & ppeaka_15_15_ & ~\[18285] ; + assign n5466 = n5730 & n5729 & ppeakb_15_15_ & n3798; + assign n5467 = n3801 & n3798 & \[13550] & ~\[18506] ; + assign n5468 = ~ppeaka_14_14_ & (~n3950 | (~n5532 & ~n5533)); + assign n5469 = ~\[18363] & \[9740] & \[18285] ; + assign n5470 = n3800 & n3798 & ppeaka_13_13_ & ~\[18285] ; + assign n5471 = n5730 & n5729 & ppeakb_13_13_ & n3798; + assign n5472 = n3801 & n3798 & \[15500] & ~\[18506] ; + assign n5473 = ~\[18363] & \[6080] & \[18285] ; + assign n5474 = n3800 & n3798 & ppeaka_14_14_ & ~\[18285] ; + assign n5475 = n5730 & n5729 & ppeakb_14_14_ & n3798; + assign n5476 = n3801 & n3798 & \[15140] & ~\[18506] ; + assign n5477 = n3718 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); + assign n5478 = ~preset & \[4700] & (~\[18285] | \[18363] ); + assign n5479 = n3716_1 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); + assign n5480 = n3706_1 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); + assign n5481 = ~preset & \[4655] & (\[18103] | ~\[18168] ); + assign n5482 = n3715 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); + assign n5483 = n3906 & ((n3910 & n3911) | (n3897 & (n3910 | n3911))); + assign n5484 = n3895 & (n5534 | n5535 | n5536); + assign n5485 = n3942 & ((n3921 & n3922) | (n3890 & (n3921 | n3922))); + assign n5486 = n3886 & n3941; + assign n5487 = n3909 & ((n3912 & n3913_1) | (n3887 & (n3912 | n3913_1))); + assign n5488 = n3889 & (n5539 | n5749); + assign n5489 = ~\[18363] & \[9725] & \[18285] ; + assign n5490 = n3800 & n3798 & ppeaka_2_2_ & ~\[18285] ; + assign n5491 = n5730 & n5729 & ppeakb_2_2_ & n3798; + assign n5492 = n3801 & n3798 & \[15515] & ~\[18506] ; + assign n5493 = ~ppeaka_3_3_ & ~n5541 & (n3792_1 | n3900); + assign n5494 = ~\[18363] & \[9995] & \[18285] ; + assign n5495 = n3800 & n3798 & ppeaka_3_3_ & ~\[18285] ; + assign n5496 = n5730 & n5729 & ppeakb_3_3_ & n3798; + assign n5497 = n3801 & n3798 & \[15860] & ~\[18506] ; + assign n5498 = ~\[18363] & \[5375] & \[18285] ; + assign n5499 = n3800 & n3798 & ppeaka_4_4_ & ~\[18285] ; + assign n5500 = n5730 & n5729 & ppeakb_4_4_ & n3798; + assign n5501 = n3801 & n3798 & \[14765] & ~\[18506] ; + assign n5502 = ~\[18363] & \[4670] & \[18285] ; + assign n5503 = n3800 & n3798 & ppeaka_5_5_ & ~\[18285] ; + assign n5504 = n5730 & n5729 & ppeakb_5_5_ & n3798; + assign n5505 = n3801 & n3798 & \[8330] & ~\[18506] ; + assign n5506 = ~\[18363] & \[6740] & \[18285] ; + assign n5507 = n3800 & n3798 & ppeaka_6_6_ & ~\[18285] ; + assign n5508 = n5730 & n5729 & ppeakb_6_6_ & n3798; + assign n5509 = n3801 & n3798 & \[7685] & ~\[18506] ; + assign n5510 = ~\[18363] & \[6065] & \[18285] ; + assign n5511 = n3800 & n3798 & ppeaka_7_7_ & ~\[18285] ; + assign n5512 = n5730 & n5729 & ppeakb_7_7_ & n3798; + assign n5513 = n3801 & n3798 & \[7055] & ~\[18506] ; + assign n5514 = ~\[18363] & \[8000] & \[18285] ; + assign n5515 = n3800 & n3798 & ppeaka_8_8_ & ~\[18285] ; + assign n5516 = n5730 & n5729 & ppeakb_8_8_ & n3798; + assign n5517 = n3801 & n3798 & \[6410] & ~\[18506] ; + assign n5518 = ~n5537 & ~n3941 & ~ppeaka_8_8_ & ppeaka_9_9_; + assign n5519 = ~ppeaka_9_9_ & ~n5537 & (ppeaka_8_8_ | n3941); + assign n5520 = ~\[18363] & \[7370] & \[18285] ; + assign n5521 = n3800 & n3798 & ppeaka_9_9_ & ~\[18285] ; + assign n5522 = n5730 & n5729 & ppeakb_9_9_ & n3798; + assign n5523 = n3801 & n3798 & \[5720] & ~\[18506] ; + assign n5524 = ~\[18363] & \[9305] & \[18285] ; + assign n5525 = n3800 & n3798 & ppeaka_10_10_ & ~\[18285] ; + assign n5526 = n5730 & n5729 & ppeakb_10_10_ & n3798; + assign n5527 = n3801 & n3798 & \[5015] & ~\[18506] ; + assign n5528 = ~\[18363] & \[8645] & \[18285] ; + assign n5529 = n3800 & n3798 & ppeaka_11_11_ & ~\[18285] ; + assign n5530 = n5730 & n5729 & ppeakb_11_11_ & n3798; + assign n5531 = n3801 & n3798 & \[4295] & ~\[18506] ; + assign n5532 = ~n5536 & ~n5534 & ~n5535 & n5753; + assign n5533 = ~n3792_1 & (n3949 | (~n3941 & n5751)); + assign n5534 = n5752 & (n5537 | (~n3941 & n5751)); + assign n5535 = n3954 & ~n5537 & (n3941 | ~n5751); + assign n5536 = ~ppeaka_11_11_ & ~n3952; + assign n5537 = n3949 & (~n3798 | ~n5729 | ~n5730); + assign n5538 = ~n3792_1 & (~n3900 | n5541); + assign n5539 = n3948_1 & (n3792_1 | n3900) & ~n5541; + assign n5540 = ~ppeaka_5_5_ & ~n3947; + assign n5541 = ~n5545 & ~n5543 & ~n5544 & n5747; + assign n5542 = ~n3900 & (~n3798 | ~n5729 | ~n5730); + assign n5543 = ~n5739 & ~n3878_1 & ~n5737 & n5746; + assign n5544 = n3946 & (n3878_1 | n5737 | n5739); + assign n5545 = ~ppeaka_2_2_ & ~n3945; + assign n5546 = ~\[18363] & \[10010] & \[18285] ; + assign n5547 = n3800 & n3798 & ppeaka_12_12_ & ~\[18285] ; + assign n5548 = n5730 & n5729 & ppeakb_12_12_ & n3798; + assign n5549 = n3801 & n3798 & \[15845] & ~\[18506] ; + assign n5550 = n5730 & n5729 & ppeaka_0_0_ & n3798; + assign n5551 = ~\[18363] & \[8630] & \[18285] ; + assign n5552 = n3800 & n3798 & ppeaka_0_0_ & ~\[18285] ; + assign n5553 = n5730 & n5729 & ppeakb_0_0_ & n3798; + assign n5554 = n3801 & n3798 & \[4310] & ~\[18506] ; + assign n5555 = ~\[18363] & \[9290] & \[18285] ; + assign n5556 = n3800 & n3798 & ppeaka_1_1_ & ~\[18285] ; + assign n5557 = n5730 & n5729 & ppeakb_1_1_ & n3798; + assign n5558 = n3801 & n3798 & \[5030] & ~\[18506] ; + assign n5559 = ~preset & \[4610] & (\[17310] | ~\[17388] ); + assign n5560 = ~preset & \[4550] & (~n3798 | ~n5733); + assign n5561 = n5733 & n3798 & ~preset & pdata_10_10_; + assign n5562 = ~preset & \[4535] & (~n3798 | ~n5732); + assign n5563 = n5732 & n3798 & ~preset & pdata_15_15_; + assign n5564 = ~preset & \[4520] & (~n3798 | ~n5731); + assign n5565 = n5731 & n3798 & ~preset & pdata_9_9_; + assign n5566 = ~preset & \[4505] & (~\[17284] | \[18376] ); + assign n5567 = ~preset & \[4490] & (~\[17284] | \[18376] ); + assign n5568 = ~preset & \[4475] & (~\[17167] | \[17362] ); + assign n5569 = ~preset & \[4415] & (~\[17102] | \[17154] ); + assign n5570 = ~preset & \[4400] & (~\[17102] | \[17154] ); + assign n5571 = ~preset & \[4370] & (~\[17453] | \[18246] ); + assign n5572 = ~preset & \[4355] & (~\[17453] | \[18246] ); + assign n5573 = ppeaka_10_10_ & (n5577 | n5720); + assign n5574 = n3963 & \[12140] & n3874_1; + assign n5575 = ppeakp_10_10_ & (n5722 | n5723 | n5725); + assign n5576 = n3801 & ppeakb_10_10_ & n3756; + assign n5577 = n3899 & n3756 & n3876; + assign n5578 = ~n3899 & n3756 & n3876; + assign n5579 = n3857 & n3827_1 & \[6995] & n3756; + assign n5580 = n3963 & n3874_1 & \[11885] & n3857; + assign n5581 = n3857 & n3826 & \[13505] & n3756; + assign n5582 = n3857 & n3808 & \[11465] & n3756; + assign n5583 = n3857 & n3806 & \[9545] & n3756; + assign n5584 = n3857 & n3812_1 & \[13430] & n3756; + assign n5585 = n3857 & n3801 & \[6185] & n3756; + assign n5586 = n3876 & n3857 & \[13055] & n3756; + assign n5587 = n3857 & n3821 & \[7445] & n3756; + assign n5588 = n3857 & n3802_1 & \[5420] & n3756; + assign n5589 = n3857 & n3803 & \[10895] & n3756; + assign n5590 = n3857 & \[15395] & n3702; + assign n5591 = n3857 & n3800 & \[10280] & n3756; + assign n5592 = ppeaks_5_5_ & (n5708 | n5709); + assign n5593 = n3801 & \[8525] & n3756; + assign n5594 = \[4310] & (n3968 | n5701 | n5702); + assign n5595 = \[14225] & n3804 & (n5627 | n5628); + assign n5596 = n3801 & \[8540] & n3756; + assign n5597 = \[4295] & (n3968 | n5701 | n5702); + assign n5598 = \[8825] & n3804 & (n5627 | n5628); + assign n5599 = n3857 & n3811 & \[4955] & n3756; + assign n5600 = n3857 & n3819 & \[5870] & n3756; + assign n5601 = n3957_1 & n3857 & \[7685] & n3756; + assign n5602 = n3857 & n3808 & \[11690] & n3756; + assign n5603 = n3857 & n3806 & \[15200] & n3756; + assign n5604 = n3857 & n3803 & \[10745] & n3756; + assign n5605 = n3857 & n3800 & \[15935] & n3756; + assign n5606 = ppeaka_6_6_ & ((n3756 & n3801) | n3968); + assign n5607 = n3966 & n3857 & ppeaka_1_1_ & n3756; + assign n5608 = n3857 & n3812_1 & \[15650] & n3756; + assign n5609 = n3857 & n3801 & \[5285] & n3756; + assign n5610 = n3876 & n3857 & \[13310] & n3756; + assign n5611 = n3857 & n3821 & \[13295] & n3756; + assign n5612 = n3857 & n3802_1 & \[8480] & n3756; + assign n5613 = n3857 & n3803 & \[14510] & n3756; + assign n5614 = n3857 & \[5030] & n3702; + assign n5615 = n3857 & n3800 & \[5150] & n3756; + assign n5616 = ppeakb_1_1_ & ((n3756 & n3960) | n3968); + assign n5617 = n3966 & n3857 & ppeaka_12_12_ & n3756; + assign n5618 = n3857 & n3812_1 & \[5945] & n3756; + assign n5619 = n3857 & n3801 & \[9230] & n3756; + assign n5620 = n3876 & n3857 & \[13325] & n3756; + assign n5621 = n3857 & n3821 & \[15260] & n3756; + assign n5622 = n3857 & n3802_1 & \[8495] & n3756; + assign n5623 = n3857 & n3803 & \[7955] & n3756; + assign n5624 = n3857 & \[15845] & n3702; + assign n5625 = n3857 & n3800 & \[6545] & n3756; + assign n5626 = ppeakb_12_12_ & ((n3756 & n3960) | n3968); + assign n5627 = ~n3955 & ~\[17089] & ~preset & pdn; + assign n5628 = n3790 & ~preset & ~\[17596] ; + assign n5629 = n5686 & (n3799 | (~\[17596] & n3790)); + assign n5630 = n3955 & pdn & ~\[17089] ; + assign n5631 = ~\[17856] & \[18207] ; + assign n5632 = ~preset & ndout & (~\[17791] | \[17843] ); + assign n5633 = ~\[17752] & ~ppeaki_6_6_ & ~ppeaki_7_7_; + assign n5634 = \[17752] & ~\[17544] & \[17713] ; + assign n5635 = \[17674] & \[17609] ; + assign n5636 = \[17752] & \[17544] & \[17713] ; + assign n5637 = ppeaki_6_6_ & ~ppeaki_4_4_; + assign n5638 = ~\[17713] & ~\[17674] ; + assign n5639 = ~ppeaki_5_5_ & ppeaki_4_4_; + assign n5640 = \[17713] & \[17609] ; + assign n5641 = \[17713] & ~\[17609] & \[17674] ; + assign n5642 = ~\[17752] & ppeaki_6_6_ & ~ppeaki_7_7_; + assign n5643 = ~\[17713] & \[17674] ; + assign n5644 = ~ppeaki_5_5_ & ~ppeaki_4_4_; + assign n5645 = ~\[17713] & \[17609] ; + assign n5646 = \[17674] & \[17609] ; + assign n5647 = \[17752] & \[17544] & ~\[17713] ; + assign n5648 = ~ppeaki_5_5_ & ~ppeaki_4_4_; + assign n5649 = ~\[17713] & ~\[17609] ; + assign n5650 = ppeaki_6_6_ & ppeaki_4_4_; + assign n5651 = \[17713] & ~\[17674] ; + assign n5652 = ~ppeaki_5_5_ & ppeaki_4_4_; + assign n5653 = \[17713] & ~\[17609] ; + assign n5654 = ~\[17752] & ppeaki_6_6_ & ~ppeaki_7_7_; + assign n5655 = \[17713] & \[17674] ; + assign n5656 = ~\[17713] & ~\[17609] & \[17674] ; + assign n5657 = ~\[17752] & ~ppeaki_6_6_ & ~ppeaki_7_7_; + assign n5658 = \[17752] & ~\[17544] & ~\[17713] ; + assign n5659 = n3843 | n3842_1; + assign n5660 = n3830 | n3831 | n3832_1 | n3833; + assign n5661 = n3834 | n3835 | n3836 | n3837_1; + assign n5662 = n3838 | n3839 | n3840 | n3841; + assign n5663 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; + assign n5664 = ~n3828 & n5663 & (n3875 | n3881); + assign n5665 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; + assign n5666 = n5665 & (n3875 | n3881); + assign n5667 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; + assign n5668 = ~n3828 & n5667 & (n3829 | n3862); + assign n5669 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; + assign n5670 = n5669 & (n3829 | n3862); + assign n5671 = ~n3796 & ~n3828 & (n5666 | n5670); + assign n5672 = ~\[18597] & \[17596] & ~\[17661] ; + assign n5673 = ~\[18207] & ~\[10805] & ~\[10820] ; + assign n5674 = ~\[11585] & ~\[11090] & ~\[11345] & ~\[11600] ; + assign n5675 = ~\[12065] & ~\[11810] & ~\[11930] & ~\[12080] ; + assign n5676 = ~\[12275] & ~\[12185] & ~\[12200] & ~\[12485] ; + assign n5677 = n5675 & n5674; + assign n5678 = n5676 & n5673 & ~\[12695] & ~\[12935] ; + assign n5679 = \[17986] & ~\[17804] ; + assign n5680 = ~\[17674] & ~\[17609] ; + assign n5681 = \[17752] & ~\[17544] & \[17713] ; + assign n5682 = ~ppeaki_6_6_ & ppeaki_4_4_; + assign n5683 = ~\[17674] & ~\[17609] ; + assign n5684 = \[17752] & ~\[17544] & ~\[17713] ; + assign n5685 = ~ppeaki_6_6_ & ~ppeaki_4_4_; + assign n5686 = ~preset & ((\[18064] & ~\[18129] ) | (~pirq_0_0_ & (~\[18064] | ~\[18129] ))); + assign n5687 = n5625 | (\[15545] & n3698); + assign n5688 = n5617 | (\[6470] & n3697) | n5624; + assign n5689 = n5618 | n5619 | n5620 | n5621; + assign n5690 = n5622 | n5623 | n5626 | n5689; + assign n5691 = n5615 | (\[9065] & n3698); + assign n5692 = n5607 | (\[5075] & n3697) | n5614; + assign n5693 = n5608 | n5609 | n5610 | n5611; + assign n5694 = n5612 | n5613 | n5616 | n5693; + assign n5695 = n5605 | n5604; + assign n5696 = (ppeakp_6_6_ & n3699) | (ppeaka_7_7_ & n3700); + assign n5697 = (\[12560] & n3698) | (~ppeaka_6_6_ & n3697); + assign n5698 = n5599 | (ppeakb_6_6_ & n3701_1) | (~ppeakb_6_6_ & n3697); + assign n5699 = n5600 | n5601 | n5602 | n5603; + assign n5700 = n5606 | n5695 | n5696 | n5697; + assign n5701 = n3756 & (n3964 | n3967_1); + assign n5702 = n3756 & (n3826 | n3961); + assign n5703 = n5598 | (\[7655] & n3756 & n3827_1); + assign n5704 = n5595 | (\[7640] & n3756 & n3827_1); + assign n5705 = ~n3874_1 & ~\[17089] & ~preset & pdn; + assign n5706 = ~n5631 & (~n5677 | ~n5678) & n5705; + assign n5707 = ~n3804 & (n5628 | (~n3955 & n3963)); + assign n5708 = n3857 & (n5706 | n5707); + assign n5709 = ~preset & (n3783 ? n3960 : ~n3856_1); + assign n5710 = n5589 | n5588; + assign n5711 = n5591 | n5580 | n5590; + assign n5712 = (\[14555] & n3698) | (\[13700] & n3697); + assign n5713 = n5579 | n5581 | n5582 | n5583; + assign n5714 = n5584 | n5585 | n5586 | n5587; + assign n5715 = n5592 | n5710 | n5711 | n5712; + assign n5716 = ppeakb_7_7_ | ppeakb_14_14_ | ppeakb_10_10_ | ppeakb_8_8_; + assign n5717 = ppeakb_9_9_ | ppeakb_15_15_ | ppeakb_11_11_ | ppeakb_0_0_; + assign n5718 = ppeakb_1_1_ | ppeakb_12_12_ | ppeakb_2_2_ | ppeakb_3_3_; + assign n5719 = ppeakb_13_13_ | ppeakb_4_4_ | ppeakb_5_5_ | ppeakb_6_6_; + assign n5720 = n3756 & (n3821 | n3828); + assign n5721 = n3963 & (\[17024] ? ~\[18545] : ~preset_0_0_); + assign n5722 = (n3756 & n3808) | (n3955 & n5721); + assign n5723 = n3756 & (n3957_1 | n3964); + assign n5724 = n3756 & (n3956 | n3958); + assign n5725 = n5724 | n5578 | (~preset & ~n3857); + assign n5726 = n5574 | (\[4850] & (n5627 | n5628)); + assign n5727 = n5726 | (\[6965] & n3756 & n3806); + assign n5728 = n3796 & ~\[18610] ; + assign n5729 = ~n3797_1 & ~\[18610] & n3796; + assign n5730 = n3814 & ~\[18168] ; + assign n5731 = n3821 & ~\[18493] ; + assign n5732 = n3876 & ~\[16920] ; + assign n5733 = n3812_1 & ~\[17297] ; + assign n5734 = n3815 & ~\[17453] ; + assign n5735 = n3798 & (n5733 | (~\[16920] & n3876)); + assign n5736 = n3798 & (n5731 | (n5729 & n5734)); + assign n5737 = n3810 | (~\[17284] & n3798 & n3802_1); + assign n5738 = (\[18285] & ~\[18363] ) | (~\[18311] & \[18506] ); + assign n5739 = n3813 | n3817_1 | n5550 | n5738; + assign n5740 = n5551 | (\[10025] & ~\[18311] & \[18506] ); + assign n5741 = n5552 | n5553 | n5554 | n5740; + assign n5742 = n5555 | (\[10310] & ~\[18311] & \[18506] ); + assign n5743 = n5556 | n5557 | n5558 | n5742; + assign n5744 = n5546 | (\[6860] & ~\[18311] & \[18506] ); + assign n5745 = n5547 | n5548 | n5549 | n5744; + assign n5746 = ~n3946 & ~ppeaka_1_1_; + assign n5747 = ~ppeaka_3_3_ & ~ppeaka_2_2_; + assign n5748 = ~n3948_1 & ~ppeaka_4_4_; + assign n5749 = n5540 | (n5748 & (n5541 | n5542)); + assign n5750 = ~ppeaka_6_6_ & ~ppeaka_5_5_; + assign n5751 = ~ppeaka_9_9_ & ~ppeaka_8_8_; + assign n5752 = ~n3954 & ~ppeaka_10_10_; + assign n5753 = ~ppeaka_12_12_ & ~ppeaka_11_11_; + assign n5754 = ~ppeaka_11_11_ & n3951 & (~ppeaka_10_10_ | ~n3792_1); + assign n5755 = (~n3951 & (~n3792_1 | (~n5532 & n5754))) | (n3792_1 & ~n5532 & n5754); + assign n5756 = n5489 | (\[4760] & ~\[18311] & \[18506] ); + assign n5757 = n5490 | n5491 | n5492 | n5756; + assign n5758 = n5494 | (\[6845] & ~\[18311] & \[18506] ); + assign n5759 = n5495 | n5496 | n5497 | n5758; + assign n5760 = ~ppeaka_2_2_ & ~n3893_1 & (~ppeaka_1_1_ | ~n3792_1); + assign n5761 = ~n5541 & ((n3792_1 & n5760) | (n3900 & (~n3792_1 | n5760))); + assign n5762 = n5498 | (\[6170] & ~\[18311] & \[18506] ); + assign n5763 = n5499 | n5500 | n5501 | n5762; + assign n5764 = n5502 | (\[8105] & ~\[18311] & \[18506] ); + assign n5765 = n5503 | n5504 | n5505 | n5764; + assign n5766 = n5506 | (\[7475] & ~\[18311] & \[18506] ); + assign n5767 = n5507 | n5508 | n5509 | n5766; + assign n5768 = ~n5749 & ~ppeaka_5_5_ & ~n5539; + assign n5769 = n5510 | (\[9410] & ~\[18311] & \[18506] ); + assign n5770 = n5511 | n5512 | n5513 | n5769; + assign n5771 = n5514 | (\[8750] & ~\[18311] & \[18506] ); + assign n5772 = n5515 | n5516 | n5517 | n5771; + assign n5773 = n5520 | (\[10040] & ~\[18311] & \[18506] ); + assign n5774 = n5521 | n5522 | n5523 | n5773; + assign n5775 = n5524 | (\[9770] & ~\[18311] & \[18506] ); + assign n5776 = n5525 | n5526 | n5527 | n5775; + assign n5777 = n5528 | (\[10595] & ~\[18311] & \[18506] ); + assign n5778 = n5529 | n5530 | n5531 | n5777; + assign n5779 = n5469 | (\[4775] & ~\[18311] & \[18506] ); + assign n5780 = n5470 | n5471 | n5472 | n5779; + assign n5781 = n5473 | (\[5480] & ~\[18311] & \[18506] ); + assign n5782 = n5474 | n5475 | n5476 | n5781; + assign n5783 = ~ppeaka_13_13_ & ppeaka_14_14_; + assign n5784 = n3792_1 ? (n5532 & n5783) : (~n3951 & ~n5532); + assign n5785 = n5464 | (\[8765] & ~\[18311] & \[18506] ); + assign n5786 = n5465 | n5466 | n5467 | n5785; + assign n5787 = ppeaka_15_15_ & ~ppeaka_14_14_; + assign n5788 = n5787 & n5730 & n3798 & n5729; + assign n5789 = ~ppeaka_15_15_ & ppeaka_14_14_; + assign n5790 = n3792_1 ? n5789 : (~n3951 & ~n5532); + assign n5791 = n3825 | (~\[18025] & n3798 & n3806); + assign n5792 = n5455 | n5452 | n5453; + assign n5793 = n5792 | n5450 | n5451; + assign n5794 = n5793 | n5454 | n5456; + assign n5795 = n5448 | n5445 | n5446; + assign n5796 = n5795 | n5443 | n5444; + assign n5797 = n5796 | n5447 | n5449; + assign n5798 = n5441 | n5438 | n5439; + assign n5799 = n5798 | n5436 | n5437; + assign n5800 = n5799 | n5440 | n5442; + assign n5801 = n5434 | n5431 | n5432; + assign n5802 = n5801 | n5429 | n5430; + assign n5803 = n5802 | n5433 | n5435; + assign n5804 = n5427 | n5424 | n5425; + assign n5805 = n5804 | n5422 | n5423; + assign n5806 = n5805 | n5426 | n5428; + assign n5807 = (\[17635] & ~\[17986] ) | (~\[17037] & \[18025] ); + assign n5808 = (\[17427] & ~\[17648] ) | (~\[17999] & \[18077] ); + assign n5809 = n5808 | n5807; + assign n5810 = n5809 | (~\[17245] & n3798 & n3811); + assign n5811 = n5810 | n5407; + assign n5812 = n5413 | n5410 | n5411; + assign n5813 = n5812 | n5408 | n5409; + assign n5814 = n5813 | n5412 | n5414; + assign n5815 = n5420 | n5417 | n5418; + assign n5816 = n5815 | n5415 | n5416; + assign n5817 = n5816 | n5419 | n5421; + assign n5818 = (n5811 & n5814) | (n3848 & (ppeaks_0_0_ | n5814)); + assign n5819 = n3803 & n3798 & ppeaka_2_2_ & ~\[16933] ; + assign n5820 = n3803 & n3798 & ppeaka_3_3_ & ~\[16933] ; + assign n5821 = n3803 & n3798 & ppeaka_4_4_ & ~\[16933] ; + assign n5822 = n3803 & n3798 & ppeaka_5_5_ & ~\[16933] ; + assign n5823 = n3803 & n3798 & ppeaka_6_6_ & ~\[16933] ; + assign n5824 = n5405 | n5402 | n5403; + assign n5825 = n5824 | n5400 | n5401; + assign n5826 = n5825 | n5404 | n5406; + assign n5827 = n5398 | n5395 | n5396; + assign n5828 = n5827 | n5393 | n5394; + assign n5829 = n5828 | n5397 | n5399; + assign n5830 = n5391 | n5388 | n5389; + assign n5831 = n5830 | n5386 | n5387; + assign n5832 = n5831 | n5390 | n5392; + assign n5833 = n5384 | n5381 | n5382; + assign n5834 = n5833 | n5379 | n5380; + assign n5835 = n5834 | n5383 | n5385; + assign n5836 = n3803 & n3798 & ppeaka_7_7_ & ~\[16933] ; + assign n5837 = n3803 & n3798 & ppeaka_8_8_ & ~\[16933] ; + assign n5838 = n3803 & n3798 & ppeaka_9_9_ & ~\[16933] ; + assign n5839 = n3803 & n3798 & ppeaka_10_10_ & ~\[16933] ; + assign n5840 = n5376 | n5373 | n5374; + assign n5841 = n5840 | n5371 | n5372; + assign n5842 = n5841 | n5375 | n5377; + assign n5843 = n5369 | n5366 | n5367; + assign n5844 = n5843 | n5364 | n5365; + assign n5845 = n5844 | n5368 | n5370; + assign n5846 = n5362 | n5359 | n5360; + assign n5847 = n5846 | n5357 | n5358; + assign n5848 = n5847 | n5361 | n5363; + assign n5849 = n5355 | n5352 | n5353; + assign n5850 = n5849 | n5350 | n5351; + assign n5851 = n5850 | n5354 | n5356; + assign n5852 = n5348 | n5345 | n5346; + assign n5853 = n5852 | n5343 | n5344; + assign n5854 = n5853 | n5347 | n5349; + assign n5855 = n3803 & n3798 & ppeaka_11_11_ & ~\[16933] ; + assign n5856 = n3803 & n3798 & ppeaka_12_12_ & ~\[16933] ; + assign n5857 = n3803 & n3798 & ppeaka_13_13_ & ~\[16933] ; + assign n5858 = n3803 & n3798 & ppeaka_14_14_ & ~\[16933] ; + assign n5859 = n5338 | (\[8405] & n3698); + assign n5860 = n5330 | (\[4355] & n3697) | n5337; + assign n5861 = n5331 | n5332 | n5333 | n5334; + assign n5862 = n5335 | n5336 | n5339 | n5861; + assign n5863 = n5328 | n5327; + assign n5864 = (ppeakp_7_7_ & n3699) | (ppeaka_8_8_ & n3700); + assign n5865 = (\[12335] & n3698) | (~ppeaka_7_7_ & n3697); + assign n5866 = n5322 | (ppeakb_7_7_ & n3701_1) | (~ppeakb_7_7_ & n3697); + assign n5867 = n5323 | n5324 | n5325 | n5326; + assign n5868 = n5329 | n5863 | n5864 | n5865; + assign n5869 = n5321 | (\[9620] & n3756 & n3827_1); + assign n5870 = n5318 | (\[9605] & n3756 & n3827_1); + assign n5871 = n5312 | n5311; + assign n5872 = n5314 | n5303 | n5313; + assign n5873 = (\[14975] & n3698) | (\[11120] & n3697); + assign n5874 = n5302 | n5304 | n5305 | n5306; + assign n5875 = n5307 | n5308 | n5309 | n5310; + assign n5876 = n5315 | n5871 | n5872 | n5873; + assign n5877 = n5299 | (\[5555] & (n5627 | n5628)); + assign n5878 = n5877 | (\[6290] & n3756 & n3806); + assign n5879 = n5265 | (\[14810] & n3698); + assign n5880 = n5257 | (\[5090] & n3697) | n5264; + assign n5881 = n5258 | n5259 | n5260 | n5261; + assign n5882 = n5262 | n5263 | n5266 | n5881; + assign n5883 = n5255 | n5254; + assign n5884 = (ppeakp_8_8_ & n3699) | (ppeaka_9_9_ & n3700); + assign n5885 = (\[15695] & n3698) | (~ppeaka_8_8_ & n3697); + assign n5886 = n5249 | (ppeakb_8_8_ & n3701_1) | (~ppeakb_8_8_ & n3697); + assign n5887 = n5250 | n5251 | n5252 | n5253; + assign n5888 = n5256 | n5883 | n5884 | n5885; + assign n5889 = n5248 | (\[8945] & n3756 & n3827_1); + assign n5890 = n5242 | n5241; + assign n5891 = n5244 | n5233 | n5243; + assign n5892 = (\[11375] & n3697) | (\[6725] & n3698); + assign n5893 = n5232 | n5234 | n5235 | n5236; + assign n5894 = n5237 | n5238 | n5239 | n5240; + assign n5895 = n5245 | n5890 | n5891 | n5892; + assign n5896 = n5228 | n5227; + assign n5897 = n5230 | n5219 | n5229; + assign n5898 = (\[13745] & n3698) | (\[9275] & n3697); + assign n5899 = n5218 | n5220 | n5221 | n5222; + assign n5900 = n5223 | n5224 | n5225 | n5226; + assign n5901 = n5231 | n5896 | n5897 | n5898; + assign n5902 = n5215 | (\[8855] & (n5627 | n5628)); + assign n5903 = n5902 | (\[11210] & n3756 & n3806); + assign n5904 = n5180 | (\[15890] & n3698); + assign n5905 = n5172 | (\[4370] & n3697) | n5179; + assign n5906 = n5173 | n5174 | n5175 | n5176; + assign n5907 = n5177 | n5178 | n5181 | n5906; + assign n5908 = n5170 | (\[7130] & n3698); + assign n5909 = n5162 | (\[5780] & n3697) | n5169; + assign n5910 = n5163 | n5164 | n5165 | n5166; + assign n5911 = n5167 | n5168 | n5171 | n5910; + assign n5912 = n5161 | (\[5630] & n3756 & n3827_1); + assign n5913 = n5155 | n5154; + assign n5914 = n5157 | n5146 | n5156; + assign n5915 = (\[15320] & n3697) | (\[7355] & n3698); + assign n5916 = n5145 | n5147 | n5148 | n5149; + assign n5917 = n5150 | n5151 | n5152 | n5153; + assign n5918 = n5158 | n5913 | n5914 | n5915; + assign n5919 = n5141 | n5140; + assign n5920 = n5143 | n5132 | n5142; + assign n5921 = (\[14135] & n3698) | (\[8615] & n3697); + assign n5922 = n5131 | n5133 | n5134 | n5135; + assign n5923 = n5136 | n5137 | n5138 | n5139; + assign n5924 = n5144 | n5919 | n5920 | n5921; + assign n5925 = n5128 | (\[9530] & (n5627 | n5628)); + assign n5926 = n5925 | (\[10955] & n3756 & n3806); + assign n5927 = n5100 | (\[11240] & n3756 & n3827_1); + assign n5928 = n5094 | n5093; + assign n5929 = n5096 | n5085 | n5095; + assign n5930 = (\[5360] & n3698) | (\[4640] & n3697); + assign n5931 = n5084 | n5086 | n5087 | n5088; + assign n5932 = n5089 | n5090 | n5091 | n5092; + assign n5933 = n5097 | n5928 | n5929 | n5930; + assign n5934 = n5080 | n5079; + assign n5935 = n5082 | n5071 | n5081; + assign n5936 = (\[16055] & n3698) | (\[4625] & n3697); + assign n5937 = n5070 | n5072 | n5073 | n5074; + assign n5938 = n5075 | n5076 | n5077 | n5078; + assign n5939 = n5083 | n5934 | n5935 | n5936; + assign n5940 = n5067 | (\[7565] & (n5627 | n5628)); + assign n5941 = n5940 | (\[11195] & n3756 & n3806); + assign n5942 = n5036 | (\[10430] & n3756 & n3827_1); + assign n5943 = n5030 | n5029; + assign n5944 = n5032 | n5021 | n5031; + assign n5945 = (\[6050] & n3698) | (\[5345] & n3697); + assign n5946 = n5020 | n5022 | n5023 | n5024; + assign n5947 = n5025 | n5026 | n5027 | n5028; + assign n5948 = n5033 | n5943 | n5944 | n5945; + assign n5949 = n5017 | (\[9815] & (n5627 | n5628)); + assign n5950 = n5949 | (\[8900] & n3756 & n3806); + assign n5951 = n5013 | (\[8195] & (n5627 | n5628)); + assign n5952 = n5951 | (\[10940] & n3756 & n3806); + assign n5953 = n4982 | (\[10715] & n3756 & n3827_1); + assign n5954 = n4976 | n4975; + assign n5955 = n4978 | n4967 | n4977; + assign n5956 = (\[15350] & n3698) | (\[6020] & n3697); + assign n5957 = n4966 | n4968 | n4969 | n4970; + assign n5958 = n4971 | n4972 | n4973 | n4974; + assign n5959 = n4979 | n5954 | n5955 | n5956; + assign n5960 = n4963 | (\[10655] & (n5627 | n5628)); + assign n5961 = n5960 | (\[5600] & n3756 & n3806); + assign n5962 = n4959 | (\[6260] & (n5627 | n5628)); + assign n5963 = n5962 | (\[6950] & n3756 & n3806); + assign n5964 = n4929 | n4928; + assign n5965 = n4931 | n4920 | n4930; + assign n5966 = (\[6710] & n3697) | (\[4655] & n3698); + assign n5967 = n4919 | n4921 | n4922 | n4923; + assign n5968 = n4924 | n4925 | n4926 | n4927; + assign n5969 = n4932 | n5964 | n5965 | n5966; + assign n5970 = n4915 | n4914; + assign n5971 = n4917 | n4906 | n4916; + assign n5972 = (\[15710] & n3698) | (\[6695] & n3697); + assign n5973 = n4905 | n4907 | n4908 | n4909; + assign n5974 = n4910 | n4911 | n4912 | n4913; + assign n5975 = n4918 | n5970 | n5971 | n5972; + assign n5976 = n4902 | (\[10370] & (n5627 | n5628)); + assign n5977 = n5976 | (\[4895] & n3756 & n3806); + assign n5978 = n4898 | (\[6935] & (n5627 | n5628)); + assign n5979 = n5978 | (\[6275] & n3756 & n3806); + assign n5980 = n4769 | (\[13250] & n3698); + assign n5981 = n4761 | (\[13235] & n3697) | n4768; + assign n5982 = n4762 | n4763 | n4764 | n4765; + assign n5983 = n4766 | n4767 | n4770 | n5982; + assign n5984 = n4754 | (\[7880] & n3756 & n3812_1); + assign n5985 = n5984 | n4751; + assign n5986 = n4744 | n4745 | n4746 | n4747; + assign n5987 = n4748 | n4749 | n4750 | n4752; + assign n5988 = n4731 | (\[6620] & n3756 & n3812_1); + assign n5989 = n5988 | n4728; + assign n5990 = n4721 | n4722 | n4723 | n4724; + assign n5991 = n4725 | n4726 | n4727 | n4729; + assign n5992 = n4661 | (\[5795] & n3698); + assign n5993 = n4653 | (\[14360] & n3697) | n4660; + assign n5994 = n4654 | n4655 | n4656 | n4657; + assign n5995 = n4658 | n4659 | n4662 | n5994; + assign n5996 = n4651 | n4650; + assign n5997 = (ppeakp_9_9_ & n3699) | (ppeaka_10_10_ & n3700); + assign n5998 = (\[16040] & n3698) | (~ppeaka_9_9_ & n3697); + assign n5999 = n4645 | (ppeakb_9_9_ & n3701_1) | (~ppeakb_9_9_ & n3697); + assign n6000 = n4646 | n4647 | n4648 | n4649; + assign n6001 = n4652 | n5996 | n5997 | n5998; + assign n6002 = n4623 | (\[6485] & n3698); + assign n6003 = n4615 | (\[13955] & n3697) | n4622; + assign n6004 = n4616 | n4617 | n4618 | n4619; + assign n6005 = n4620 | n4621 | n4624 | n6004; + assign n6006 = n4614 | (\[9890] & n3756 & n3827_1); + assign n6007 = n4609 | (\[10085] & (n5627 | n5628)); + assign n6008 = n6007 | (\[9575] & n3756 & n3806); + assign n6009 = n4585 | n4584_1; + assign n6010 = (ppeakp_11_11_ & n3699) | (ppeaka_12_12_ & n3700); + assign n6011 = (\[15335] & n3698) | (~ppeakb_11_11_ & n3697); + assign n6012 = n4579_1 | n4578 | (~ppeaka_11_11_ & n3697); + assign n6013 = n4580 | n4581 | n4582 | n4583; + assign n6014 = n4586 | n6009 | n6010 | n6011; + assign n6015 = n4575 | n4565_1 | n4566; + assign n6016 = n4567 | n4568 | n4569 | n4570_1; + assign n6017 = n4564 | n4571 | n4572 | n4576; + assign n6018 = n4573 | n4574_1 | n6015 | n6017; + assign n6019 = n4561_1 | (\[8840] & (n5627 | n5628)); + assign n6020 = n6019 | (\[11660] & n3756 & n3806); + assign n6021 = n4538 | (\[14915] & n3756 & n3812_1); + assign n6022 = n6021 | n4535; + assign n6023 = n4528_1 | n4529 | n4530 | n4531; + assign n6024 = n4532 | n4533_1 | n4534 | n4536; + assign n6025 = n4525 | n4515 | n4516; + assign n6026 = n4517 | n4518_1 | n4519 | n4520; + assign n6027 = n4514_1 | n4521 | n4522 | n4526; + assign n6028 = n4523_1 | n4524 | n6025 | n6027; + assign n6029 = n4511 | n4501 | n4502; + assign n6030 = n4503 | n4504_1 | n4505 | n4506; + assign n6031 = n4500 | n4507 | n4508 | n4512; + assign n6032 = n4509_1 | n4510 | n6029 | n6031; + assign n6033 = n4497 | (\[9515] & (n5627 | n5628)); + assign n6034 = n6033 | (\[11435] & n3756 & n3806); + assign n6035 = n4471 | (\[13010] & n3756 & n3812_1); + assign n6036 = n6035 | n4468; + assign n6037 = n4461 | n4462_1 | n4463 | n4464; + assign n6038 = n4465 | n4466_1 | n4467 | n4469; + assign n6039 = n4459 | n4458; + assign n6040 = (ppeakp_13_13_ & n3699) | (ppeaka_14_14_ & n3700); + assign n6041 = (\[14540] & n3698) | (~ppeakb_13_13_ & n3697); + assign n6042 = n4453 | n4452_1 | (~ppeaka_13_13_ & n3697); + assign n6043 = n4454 | n4455 | n4456 | n4457_1; + assign n6044 = n4460 | n6039 | n6040 | n6041; + assign n6045 = n4449 | n4439 | n4440; + assign n6046 = n4441 | n4442_1 | n4443 | n4444; + assign n6047 = n4438 | n4445 | n4446 | n4450; + assign n6048 = n4447_1 | n4448 | n6045 | n6047; + assign n6049 = n4437_1 | (\[9875] & n3756 & n3827_1); + assign n6050 = n4431 | n4430; + assign n6051 = n4433 | n4422_1 | n4432_1; + assign n6052 = (\[13040] & n3698) | (\[7970] & n3697); + assign n6053 = n4421 | n4423 | n4424 | n4425; + assign n6054 = n4426 | n4427_1 | n4428 | n4429; + assign n6055 = n4434 | n6050 | n6051 | n6052; + assign n6056 = n4418 | (\[7580] & (n5627 | n5628)); + assign n6057 = n6056 | (\[11675] & n3756 & n3806); + assign n6058 = n4397_1 | (\[16010] & n3756 & n3812_1); + assign n6059 = n6058 | n4394; + assign n6060 = n4387_1 | n4388 | n4389 | n4390; + assign n6061 = n4391 | n4392_1 | n4393 | n4395; + assign n6062 = n4385 | n4384; + assign n6063 = (ppeaka_13_13_ & n3700) | (ppeakp_12_12_ & n3699); + assign n6064 = (\[14120] & n3698) | (~ppeaka_12_12_ & n3697); + assign n6065 = n4379 | (ppeakb_12_12_ & n3701_1) | (~ppeakb_12_12_ & n3697); + assign n6066 = n4380 | n4381 | n4382 | n4383_1; + assign n6067 = n4386 | n6062 | n6063 | n6064; + assign n6068 = n4376 | n4366 | n4367; + assign n6069 = n4368_1 | n4369 | n4370 | n4371; + assign n6070 = n4365 | n4372 | n4373_1 | n4377; + assign n6071 = n4374 | n4375 | n6068 | n6070; + assign n6072 = n4364 | (\[10730] & n3756 & n3827_1); + assign n6073 = n4358_1 | n4357; + assign n6074 = n4360 | n4349 | n4359; + assign n6075 = (\[13385] & n3698) | (\[7340] & n3697); + assign n6076 = n4348_1 | n4350 | n4351 | n4352; + assign n6077 = n4353_1 | n4354 | n4355 | n4356; + assign n6078 = n4361 | n6073 | n6074 | n6075; + assign n6079 = n4345 | (\[8210] & (n5627 | n5628)); + assign n6080 = n6079 | (\[11450] & n3756 & n3806); + assign n6081 = n4326 | (\[13685] & n3756 & n3812_1); + assign n6082 = n6081 | n4323; + assign n6083 = n4316 | n4317 | n4318 | n4319_1; + assign n6084 = n4320 | n4321 | n4322 | n4324_1; + assign n6085 = n4303 | n4304_1 | n4305 | n4306; + assign n6086 = n4307 | n4308 | n4310 | n4314_1; + assign n6087 = n4309_1 | n4311 | n4312 | n4313; + assign n6088 = n4300_1 | n4290_1 | n4291; + assign n6089 = n4292 | n4293 | n4294 | n4295_1; + assign n6090 = n4289 | n4296 | n4297 | n4301; + assign n6091 = n4298 | n4299 | n6088 | n6090; + assign n6092 = n4288 | (\[10445] & n3756 & n3827_1); + assign n6093 = n4285_1 | (\[8930] & n3756 & n3827_1); + assign n6094 = n4279 | n4278; + assign n6095 = n4281 | n4270_1 | n4280_1; + assign n6096 = (\[13025] & n3698) | (\[5330] & n3697); + assign n6097 = n4269 | n4271 | n4272 | n4273; + assign n6098 = n4274 | n4275_1 | n4276 | n4277; + assign n6099 = n4282 | n6094 | n6095 | n6096; + assign n6100 = n4254 | (\[6500] & n3698); + assign n6101 = n4246 | (\[7115] & n3697) | n4253; + assign n6102 = n4247_1 | n4248 | n4249 | n4250; + assign n6103 = n4251_1 | n4252 | n4255 | n6102; + assign n6104 = n4244 | n4243; + assign n6105 = (ppeakp_14_14_ & n3699) | (ppeaka_15_15_ & n3700); + assign n6106 = (\[13370] & n3698) | (~ppeaka_14_14_ & n3697); + assign n6107 = n4238 | (ppeakb_14_14_ & n3701_1) | (~ppeakb_14_14_ & n3697); + assign n6108 = n4239 | n4240 | n4241 | n4242_1; + assign n6109 = n4245 | n6104 | n6105 | n6106; + assign n6110 = n4235 | n4225 | n4226; + assign n6111 = n4227_1 | n4228 | n4229 | n4230; + assign n6112 = n4224 | n4231 | n4232_1 | n4236; + assign n6113 = n4233 | n4234 | n6110 | n6112; + assign n6114 = n4223_1 | (\[8285] & n3756 & n3827_1); + assign n6115 = n4220 | (\[10145] & n3756 & n3827_1); + assign n6116 = n4214 | n4213_1; + assign n6117 = n4216 | n4205 | n4215; + assign n6118 = (\[12800] & n3698) | (\[6035] & n3697); + assign n6119 = n4204 | n4206 | n4207 | n4208_1; + assign n6120 = n4209 | n4210 | n4211 | n4212; + assign n6121 = n4217 | n6116 | n6117 | n6118; + assign n6122 = (\[17999] & ~\[18220] ) | (~\[17791] & n3788); + assign n6123 = (\[17180] & ~\[17232] ) | (~\[17050] & \[17115] ); + assign n6124 = (\[17206] & ~\[17271] ) | (\[16933] & ~\[17388] ); + assign n6125 = (\[18311] & ~\[18389] ) | (~\[17414] & \[17843] ); + assign n6126 = n6125 | n6124; + assign n6127 = n3789 | n3794 | n3879 | n6123; + assign n6128 = n3816 | n6122 | n6126 | n6127; + assign n6129 = n6128 | (~\[17167] & n3798 & n3819); + assign n6130 = n3858 | n3813 | n3817_1; + assign n6131 = n3792_1 | n5735 | n5736 | n6129; + assign n6132 = n4141 | (~preset & \[17284] & ~\[18376] ); + assign n6133 = n6132 | (~preset & n3798 & n5732); + assign n6134 = ~preset & n3798 & (n5731 | n5733); + assign n6135 = n4182 | n4181; + assign n6136 = n4183 | (ppeakb_8_8_ & n3777_1); + assign n6137 = (\[13460] & n3775) | (\[7595] & n3776); + assign n6138 = (\[11420] & n3773) | (\[6410] & n3774); + assign n6139 = n4177 | n4178 | n4179_1 | n4180; + assign n6140 = n4184_1 | n4185 | n6135 | n6136; + assign n6141 = n4186 | n6137 | n6138 | n6139; + assign n6142 = n4176 | (~preset & ppeakb_7_7_ & n3859); + assign n6143 = ~\[17388] & ~preset; + assign n6144 = n4170 | n4169_1; + assign n6145 = n4171 | (ppeakb_9_9_ & n3777_1); + assign n6146 = (\[13820] & n3775) | (\[10685] & n3776); + assign n6147 = (\[11645] & n3773) | (\[5720] & n3774); + assign n6148 = n4165_1 | n4166 | n4167 | n4168; + assign n6149 = n4172 | n4173 | n6144 | n6145; + assign n6150 = n4174_1 | n6146 | n6147 | n6148; + assign n6151 = n4164 | (~preset & ppeakb_8_8_ & n3859); + assign n6152 = n4162 | (~preset & ppeakb_5_5_ & n3859); + assign n6153 = n4160_1 | (~preset & ppeakb_6_6_ & n3859); + assign n6154 = n4158 | (~preset & ppeakb_15_15_ & n3859); + assign n6155 = ~\[17050] & ~preset; + assign n6156 = n4156 | (~preset & ppeakb_3_3_ & n3859); + assign n6157 = ~\[17232] & ~preset; + assign n6158 = n4154 | (~preset & ppeakb_4_4_ & n3859); + assign n6159 = ~\[17271] & ~preset; + assign n6160 = n4152 | (~preset & ppeakb_1_1_ & n3859); + assign n6161 = ~\[18376] & ~preset; + assign n6162 = n4150_1 | (~preset & ppeakb_2_2_ & n3859); + assign n6163 = n4144 | n4143; + assign n6164 = n4145 | (ppeakb_11_11_ & n3777_1); + assign n6165 = (\[13115] & n3775) | (\[10115] & n3776); + assign n6166 = (\[16100] & n3773) | (\[4295] & n3774); + assign n6167 = n4139 | n4140 | n4141_1 | n4142; + assign n6168 = n4146_1 | n4147 | n6163 | n6164; + assign n6169 = n4148 | n6165 | n6166 | n6167; + assign n6170 = n4134 | n4133; + assign n6171 = n4135 | (ppeakb_10_10_ & n3777_1); + assign n6172 = (\[12860] & n3775) | (\[10400] & n3776); + assign n6173 = (\[10925] & n3773) | (\[5015] & n3774); + assign n6174 = n4129 | n4130 | n4131_1 | n4132; + assign n6175 = n4136_1 | n4137 | n6170 | n6171; + assign n6176 = n4138 | n6172 | n6173 | n6174; + assign n6177 = n4128 | (~preset & ppeakb_13_13_ & n3859); + assign n6178 = n4121_1 | n4120; + assign n6179 = n4122 | (ppeakb_13_13_ & n3777_1); + assign n6180 = (\[12620] & n3775) | (\[8885] & n3776); + assign n6181 = (\[15500] & n3774) | (\[13805] & n3773); + assign n6182 = n4116_1 | n4117 | n4118 | n4119; + assign n6183 = n4123 | n4124 | n6178 | n6179; + assign n6184 = n4125 | n6180 | n6181 | n6182; + assign n6185 = ~n3883_1 | (~ppeaki_13_13_ & ~ppeaki_12_12_); + assign n6186 = ~n3883_1 | (~ppeaki_15_15_ & ~ppeaki_14_14_); + assign n6187 = n6185 & (~n3883_1 | (~ppeaki_15_15_ & ~ppeaki_14_14_)); + assign n6188 = ~n3759 & ~n3755 & ~n3758_1 & ~n3765; + assign n6189 = ~n3770 & ~n3766 & ~n3768_1 & ~n3772_1; + assign n6190 = n6188 & n6185 & n6186; + assign n6191 = n6189 & (\[18636] | (~n3798 & n5672)); + assign n6192 = \[17986] & \[17596] ; + assign n6193 = n4115 | \[17804] | (\[17986] & \[18597] ); + assign n6194 = ~\[18597] & ~preset & \[17596] ; + assign n6195 = n3790 & ~preset & ~\[17596] ; + assign n6196 = n4109 | n4108; + assign n6197 = n4110 | (ppeakb_12_12_ & n3777_1); + assign n6198 = (\[12395] & n3775) | (\[9845] & n3776); + assign n6199 = (\[15845] & n3774) | (\[15755] & n3773); + assign n6200 = n4104 | n4105 | n4106_1 | n4107; + assign n6201 = n4111_1 | n4112 | n6196 | n6197; + assign n6202 = n4113 | n6198 | n6199 | n6200; + assign n6203 = n4099 | n4098; + assign n6204 = n4100 | (ppeakb_15_15_ & n3777_1); + assign n6205 = (\[15050] & n3775) | (\[4880] & n3776); + assign n6206 = (\[14615] & n3773) | (\[13550] & n3774); + assign n6207 = n4094 | n4095 | n4096_1 | n4097; + assign n6208 = n4101_1 | n4102 | n6203 | n6204; + assign n6209 = n4103 | n6205 | n6206 | n6207; + assign n6210 = n4089 | n4088; + assign n6211 = n4090 | (ppeakb_14_14_ & n3777_1); + assign n6212 = (\[15410] & n3775) | (\[9560] & n3776); + assign n6213 = (\[15140] & n3774) | (\[13445] & n3773); + assign n6214 = n4084 | n4085 | n4086_1 | n4087; + assign n6215 = n4091_1 | n4092 | n6210 | n6211; + assign n6216 = n4093 | n6212 | n6213 | n6214; + assign n6217 = n4083 | (~preset & ppeakb_9_9_ & n3859); + assign n6218 = n4081_1 | (~preset & ppeakb_14_14_ & n3859); + assign n6219 = (\[17180] & ~\[17232] ) | (~\[17050] & \[17115] ); + assign n6220 = (\[17206] & ~\[17271] ) | (\[17232] & ~\[18441] ); + assign n6221 = (\[17583] & ~\[18077] ) | (~\[17427] & \[17518] ); + assign n6222 = (\[17050] & ~\[17219] ) | (\[17271] & ~\[17349] ); + assign n6223 = n3789 | n3879 | n6219 | n6220; + assign n6224 = n6223 | n6221 | n6222; + assign n6225 = n3789 & ~preset; + assign n6226 = pwr_0_0_ & ~preset; + assign n6227 = (~n3858 & ~n6224 & n6226) | (n6225 & (n3858 | n6224)); + assign n6228 = ~preset & (n3858 | (n3781 & n6224)); + assign n6229 = (n4011 | n4081) & (n3858 | n6224); + assign n6230 = (\[16933] & ~\[17388] ) | (~\[17414] & \[17843] ); + assign n6231 = (\[18311] & ~\[18389] ) | (\[18363] & ~\[18415] ); + assign n6232 = (\[17791] & ~\[17843] ) | (\[17453] & ~\[18246] ); + assign n6233 = (\[17102] & ~\[17154] ) | (\[17167] & ~\[17362] ); + assign n6234 = (\[17414] & ~\[17505] ) | (~\[17310] & \[17388] ); + assign n6235 = (~\[18142] & \[18220] ) | (~\[18311] & \[18506] ); + assign n6236 = (\[17570] & ~\[17635] ) | (\[18285] & ~\[18363] ); + assign n6237 = (\[18415] & ~\[18480] ) | (~\[18428] & \[18493] ); + assign n6238 = (~\[18298] & \[18376] ) | (~\[16985] & \[18389] ); + assign n6239 = (\[16920] & ~\[16972] ) | (\[17297] & ~\[17375] ); + assign n6240 = n6239 | n3879 | n6230; + assign n6241 = n6231 | n6232 | n6233 | n6234; + assign n6242 = n6235 | n6236 | n6237 | n6238; + assign n6243 = n6242 | n6240 | n6241; + assign n6244 = n6243 | n3816 | n6122; + assign n6245 = n6244 | (~\[17167] & n3798 & n3819); + assign n6246 = n3792_1 | n3813 | n3817_1 | n6245; + assign n6247 = ~preset & (n3816 | n6122); + assign n6248 = prd_0_0_ & ~preset; + assign n6249 = (~n3878_1 & ~n6246 & n6248) | (n6247 & (n3878_1 | n6246)); + assign n6250 = (n3706_1 | n3709) & (n3878_1 | n6246); + assign n6251 = (n4518 | n3791) & (n3878_1 | n6246); + assign n6252 = (n4150 | n4509) & (n3878_1 | n6246); + assign n6253 = (n4031 | n4056) & (n3878_1 | n6246); + assign n6254 = n6253 | n6249 | n6250; + assign n6255 = n4078 | (~preset & ppeakb_10_10_ & n3859); + assign n6256 = n4076_1 | (~preset & ppeakb_12_12_ & n3859); + assign n6257 = \[18129] & ~preset; + assign n6258 = n4065 | (~preset & ppeakb_11_11_ & n3859); + assign n6259 = n4057 | n4056_1; + assign n6260 = (\[10670] & n3776) | (ppeakb_0_0_ & n3777_1); + assign n6261 = (\[12605] & n3775) | (\[4310] & n3774); + assign n6262 = n4051_1 | (\[11630] & n3773) | n4061_1; + assign n6263 = n4052 | n4053 | n4054 | n4055; + assign n6264 = n4058 | n4059 | n6259 | n6260; + assign n6265 = n4060 | n6261 | n6262 | n6263; + assign n6266 = ~\[18415] & ~preset; + assign n6267 = n4047 | n4043; + assign n6268 = (\[9830] & n3776) | (ppeakb_1_1_ & n3777_1); + assign n6269 = (\[12380] & n3775) | (\[5030] & n3774); + assign n6270 = n4037 | (\[9485] & n3773) | n4038; + assign n6271 = n4039 | n4040 | n4041_1 | n4042; + assign n6272 = n4044 | n4045 | n6267 | n6268; + assign n6273 = n4046_1 | n6269 | n6270 | n6271; + assign n6274 = n4036_1 | (~preset & ppeakb_0_0_ & n3859); + assign n6275 = n4030 | n4029; + assign n6276 = n4031_1 | (ppeakb_2_2_ & n3777_1); + assign n6277 = (\[13100] & n3775) | (\[10100] & n3776); + assign n6278 = (\[15515] & n3774) | (\[7535] & n3773); + assign n6279 = n4025 | n4026_1 | n4027 | n4028; + assign n6280 = n4032 | n4033 | n6275 | n6276; + assign n6281 = n4034 | n6277 | n6278 | n6279; + assign n6282 = n4020 | n4019; + assign n6283 = n4021_1 | (ppeakb_3_3_ & n3777_1); + assign n6284 = (\[12845] & n3775) | (\[5570] & n3776); + assign n6285 = (\[15860] & n3774) | (\[8165] & n3773); + assign n6286 = n4015 | n4016_1 | n4017 | n4018; + assign n6287 = n4022 | n4023 | n6282 | n6283; + assign n6288 = n4024 | n6284 | n6285 | n6286; + assign n6289 = \[17700] & ~preset & ~pdn; + assign n6290 = n4008 | n4007; + assign n6291 = n4009 | (ppeakb_4_4_ & n3777_1); + assign n6292 = (\[15035] & n3775) | (\[4865] & n3776); + assign n6293 = (\[14765] & n3774) | (\[6230] & n3773); + assign n6294 = n4003 | n4004 | n4005 | n4006_1; + assign n6295 = n4010 | n4011_1 | n6290 | n6291; + assign n6296 = n4012 | n6292 | n6293 | n6294; + assign n6297 = n3998 | n3997; + assign n6298 = n3999 | (ppeakb_5_5_ & n3777_1); + assign n6299 = (\[15395] & n3775) | (\[9545] & n3776); + assign n6300 = (\[8330] & n3774) | (\[6905] & n3773); + assign n6301 = n3993 | n3994 | n3995 | n3996_1; + assign n6302 = n4000 | n4001_1 | n6297 | n6298; + assign n6303 = n4002 | n6299 | n6300 | n6301; + assign n6304 = n3988 | n3987; + assign n6305 = n3989 | (ppeakb_6_6_ & n3777_1); + assign n6306 = (\[14210] & n3775) | (\[8870] & n3776); + assign n6307 = (\[7685] & n3774) | (\[4835] & n3773); + assign n6308 = n3983 | n3984 | n3985 | n3986_1; + assign n6309 = n3990 | n3991_1 | n6304 | n6305; + assign n6310 = n3992 | n6306 | n6307 | n6308; + assign n6311 = \[17596] & ~preset & ~pdn; + assign n6312 = n3798 & ~preset & n3796; + assign n6313 = n3798 & n3797_1 & ~preset & n3796; + assign n6314 = n3798 & n3796 & ~preset & \[18168] ; + assign n6315 = n3798 & n3796 & ~preset & \[17453] ; + assign n6316 = ~n3783 & (n6313 | n6314); + assign n6317 = ~n3783 & (n6315 | (~n3787_1 & n6312)); + assign n6318 = n3976_1 | n3975; + assign n6319 = n3977 | (ppeakb_7_7_ & n3777_1); + assign n6320 = (\[14630] & n3775) | (\[8225] & n3776); + assign n6321 = (\[7055] & n3774) | (\[5540] & n3773); + assign n6322 = n3971 | n3972_1 | n3973 | n3974; + assign n6323 = n3978 | n3979 | n6318 | n6319; + assign n6324 = n3980 | n6320 | n6321 | n6322; + assign n6325 = ~preset & n3798 & (\[18493] | n3811); + assign n6326 = ~preset & n3798 & (\[18389] | \[18415] ); + assign n6327 = ~preset & n3798 & (\[17388] | \[18376] ); + assign n6328 = ~preset & n3798 & (\[17271] | \[17297] ); + assign n6329 = ~preset & n3798 & (\[17167] | \[17232] ); + assign n6330 = ~preset & n3798 & (\[17050] | \[17102] ); + assign n6331 = n6330 | n3969 | n6325; + assign n6332 = n6326 | n6327 | n6328 | n6329; + always @ (posedge pclk) begin + ndout <= n273; + ppeakb_12_12_ <= n278; + ppeakb_1_1_ <= n282; + ppeaka_6_6_ <= n286; + \[4295] <= n290; + \[4310] <= n295; + ppeaks_5_5_ <= n300; + ppeakp_10_10_ <= n304; + \[4355] <= n308; + \[4370] <= n313; + \[4385] <= n318; + \[4400] <= n323; + \[4415] <= n328; + \[4430] <= n333; + \[4445] <= n338; + \[4460] <= n343; + \[4475] <= n348; + \[4490] <= n353; + \[4505] <= n358; + \[4520] <= n363; + \[4535] <= n368; + \[4550] <= n373; + \[4565] <= n378; + \[4580] <= n383; + \[4595] <= n388; + \[4610] <= n393; + \[4625] <= n398; + \[4640] <= n403; + \[4655] <= n408; + \[4670] <= n413; + \[4700] <= n418; + \[4715] <= n423; + \[4730] <= n428; + \[4745] <= n433; + \[4760] <= n438; + \[4775] <= n443; + \[4790] <= n448; + \[4805] <= n453; + \[4820] <= n458; + \[4835] <= n463; + \[4850] <= n468; + \[4865] <= n473; + \[4880] <= n478; + \[4895] <= n483; + \[4910] <= n488; + \[4925] <= n493; + \[4940] <= n498; + \[4955] <= n503; + \[4970] <= n508; + ppeakb_0_0_ <= n513; + ppeaka_7_7_ <= n517; + \[5015] <= n521; + \[5030] <= n526; + ppeaks_4_4_ <= n531; + ppeakp_11_11_ <= n535; + \[5075] <= n539; + \[5090] <= n544; + \[5105] <= n549; + \[5120] <= n554; + \[5135] <= n559; + \[5150] <= n564; + \[5165] <= n569; + \[5180] <= n574; + \[5195] <= n579; + \[5210] <= n584; + \[5225] <= n589; + \[5240] <= n594; + \[5255] <= n599; + \[5270] <= n604; + \[5285] <= n609; + \[5300] <= n614; + \[5315] <= n619; + \[5330] <= n624; + \[5345] <= n629; + \[5360] <= n634; + \[5375] <= n639; + \[5390] <= n644; + \[5405] <= n649; + \[5420] <= n654; + \[5435] <= n659; + \[5450] <= n664; + \[5465] <= n669; + \[5480] <= n674; + \[5495] <= n679; + \[5510] <= n684; + \[5525] <= n689; + \[5540] <= n694; + \[5555] <= n699; + \[5570] <= n704; + \[5600] <= n709; + \[5615] <= n714; + \[5630] <= n719; + \[5645] <= n724; + \[5660] <= n729; + \[5675] <= n734; + ppeakb_10_10_ <= n739; + ppeaka_8_8_ <= n743; + \[5720] <= n747; + ppeaks_14_14_ <= n752; + ppeaks_7_7_ <= n756; + ppeakp_12_12_ <= n760; + \[5780] <= n764; + \[5795] <= n769; + \[5810] <= n774; + \[5825] <= n779; + \[5840] <= n784; + \[5855] <= n789; + \[5870] <= n794; + \[5885] <= n799; + \[5900] <= n804; + \[5915] <= n809; + \[5930] <= n814; + \[5945] <= n819; + \[5960] <= n824; + \[5975] <= n829; + \[5990] <= n834; + \[6005] <= n839; + \[6020] <= n844; + \[6035] <= n849; + \[6050] <= n854; + \[6065] <= n859; + \[6080] <= n864; + \[6095] <= n869; + \[6110] <= n874; + \[6125] <= n879; + \[6140] <= n884; + \[6155] <= n889; + \[6170] <= n894; + \[6185] <= n899; + \[6200] <= n904; + \[6215] <= n909; + \[6230] <= n914; + \[6245] <= n919; + \[6260] <= n924; + \[6275] <= n929; + \[6290] <= n934; + \[6305] <= n939; + \[6320] <= n944; + \[6335] <= n949; + \[6350] <= n954; + \[6365] <= n959; + ppeakb_11_11_ <= n964; + ppeakb_2_2_ <= n968; + \[6410] <= n972; + ppeaks_15_15_ <= n977; + ppeaks_6_6_ <= n981; + ppeakp_13_13_ <= n985; + \[6470] <= n989; + \[6485] <= n994; + \[6500] <= n999; + \[6515] <= n1004; + \[6530] <= n1009; + \[6545] <= n1014; + \[6560] <= n1019; + \[6575] <= n1024; + \[6590] <= n1029; + \[6605] <= n1034; + \[6620] <= n1039; + \[6635] <= n1044; + \[6650] <= n1049; + \[6665] <= n1054; + \[6680] <= n1059; + \[6695] <= n1064; + \[6710] <= n1069; + \[6725] <= n1074; + \[6740] <= n1079; + \[6755] <= n1084; + \[6770] <= n1089; + \[6785] <= n1094; + \[6815] <= n1099; + \[6830] <= n1104; + \[6845] <= n1109; + \[6860] <= n1114; + \[6875] <= n1119; + \[6890] <= n1124; + \[6905] <= n1129; + \[6920] <= n1134; + \[6935] <= n1139; + \[6950] <= n1144; + \[6965] <= n1149; + \[6980] <= n1154; + \[6995] <= n1159; + \[7010] <= n1164; + \[7025] <= n1169; + \[7055] <= n1174; + ppeaks_12_12_ <= n1179; + ppeaks_1_1_ <= n1183; + ppeakp_3_3_ <= n1187; + \[7115] <= n1191; + \[7130] <= n1196; + \[7145] <= n1201; + \[7160] <= n1206; + \[7175] <= n1211; + \[7190] <= n1216; + \[7205] <= n1221; + \[7220] <= n1226; + \[7235] <= n1231; + \[7250] <= n1236; + \[7265] <= n1241; + \[7280] <= n1246; + \[7295] <= n1251; + \[7310] <= n1256; + \[7325] <= n1261; + \[7340] <= n1266; + \[7355] <= n1271; + \[7370] <= n1276; + \[7385] <= n1281; + \[7400] <= n1286; + \[7415] <= n1291; + \[7430] <= n1296; + \[7445] <= n1301; + \[7460] <= n1306; + \[7475] <= n1311; + \[7490] <= n1316; + \[7505] <= n1321; + \[7520] <= n1326; + \[7535] <= n1331; + \[7550] <= n1336; + \[7565] <= n1341; + \[7580] <= n1346; + \[7595] <= n1351; + \[7625] <= n1356; + \[7640] <= n1361; + \[7655] <= n1366; + \[7670] <= n1371; + \[7685] <= n1376; + ppeaks_13_13_ <= n1381; + ppeakp_7_7_ <= n1385; + ppeakp_2_2_ <= n1389; + \[7745] <= n1393; + \[7760] <= n1398; + \[7775] <= n1403; + \[7790] <= n1408; + \[7805] <= n1413; + \[7820] <= n1418; + \[7835] <= n1423; + \[7850] <= n1428; + \[7865] <= n1433; + \[7880] <= n1438; + \[7895] <= n1443; + \[7910] <= n1448; + \[7925] <= n1453; + \[7940] <= n1458; + \[7955] <= n1463; + \[7970] <= n1468; + \[8000] <= n1473; + \[8015] <= n1478; + \[8030] <= n1483; + \[8045] <= n1488; + \[8060] <= n1493; + \[8075] <= n1498; + \[8090] <= n1503; + \[8105] <= n1508; + \[8120] <= n1513; + \[8135] <= n1518; + \[8150] <= n1523; + \[8165] <= n1528; + \[8180] <= n1533; + \[8195] <= n1538; + \[8210] <= n1543; + \[8225] <= n1548; + \[8240] <= n1553; + \[8255] <= n1558; + \[8285] <= n1563; + \[8300] <= n1568; + \[8315] <= n1573; + \[8330] <= n1578; + ppeaks_3_3_ <= n1583; + ppeakp_8_8_ <= n1587; + ppeakp_1_1_ <= n1591; + \[8390] <= n1595; + \[8405] <= n1600; + \[8420] <= n1605; + \[8435] <= n1610; + \[8450] <= n1615; + \[8465] <= n1620; + \[8480] <= n1625; + \[8495] <= n1630; + \[8510] <= n1635; + \[8525] <= n1640; + \[8540] <= n1645; + \[8555] <= n1650; + \[8570] <= n1655; + \[8585] <= n1660; + \[8600] <= n1665; + \[8615] <= n1670; + \[8630] <= n1675; + \[8645] <= n1680; + \[8660] <= n1685; + \[8675] <= n1690; + \[8690] <= n1695; + \[8705] <= n1700; + \[8720] <= n1705; + \[8735] <= n1710; + \[8750] <= n1715; + \[8765] <= n1720; + \[8780] <= n1725; + \[8810] <= n1730; + \[8825] <= n1735; + \[8840] <= n1740; + \[8855] <= n1745; + \[8870] <= n1750; + \[8885] <= n1755; + \[8900] <= n1760; + \[8915] <= n1765; + \[8930] <= n1770; + \[8945] <= n1775; + \[8960] <= n1780; + \[8975] <= n1785; + ppeaks_11_11_ <= n1790; + ppeaks_2_2_ <= n1794; + ppeakp_9_9_ <= n1798; + ppeakp_0_0_ <= n1802; + \[9050] <= n1806; + \[9065] <= n1811; + \[9080] <= n1816; + \[9095] <= n1821; + \[9110] <= n1826; + \[9125] <= n1831; + \[9140] <= n1836; + \[9155] <= n1841; + \[9170] <= n1846; + \[9185] <= n1851; + \[9200] <= n1856; + \[9215] <= n1861; + \[9230] <= n1866; + \[9245] <= n1871; + \[9260] <= n1876; + \[9275] <= n1881; + \[9290] <= n1886; + \[9305] <= n1891; + \[9320] <= n1896; + \[9335] <= n1901; + \[9350] <= n1906; + \[9365] <= n1911; + \[9380] <= n1916; + \[9395] <= n1921; + \[9410] <= n1926; + \[9440] <= n1931; + \[9455] <= n1936; + \[9470] <= n1941; + \[9485] <= n1946; + \[9500] <= n1951; + \[9515] <= n1956; + \[9530] <= n1961; + \[9545] <= n1966; + \[9560] <= n1971; + \[9575] <= n1976; + \[9590] <= n1981; + \[9605] <= n1986; + \[9620] <= n1991; + \[9635] <= n1996; + \[9650] <= n2001; + \[9665] <= n2006; + \[9680] <= n2011; + ppeaki_6_6_ <= n2016; + \[9710] <= n2020; + \[9725] <= n2025; + \[9740] <= n2030; + \[9770] <= n2035; + \[9785] <= n2040; + \[9800] <= n2045; + \[9815] <= n2050; + \[9830] <= n2055; + \[9845] <= n2060; + \[9860] <= n2065; + \[9875] <= n2070; + \[9890] <= n2075; + \[9905] <= n2080; + \[9920] <= n2085; + \[9935] <= n2090; + \[9950] <= n2095; + \[9980] <= n2100; + \[9995] <= n2105; + \[10010] <= n2110; + \[10025] <= n2115; + \[10040] <= n2120; + \[10055] <= n2125; + \[10070] <= n2130; + \[10085] <= n2135; + \[10100] <= n2140; + \[10115] <= n2145; + \[10130] <= n2150; + \[10145] <= n2155; + \[10175] <= n2160; + \[10190] <= n2165; + \[10205] <= n2170; + \[10220] <= n2175; + ppeaki_15_15_ <= n2180; + ppeaki_4_4_ <= n2184; + \[10265] <= n2188; + \[10280] <= n2193; + \[10310] <= n2198; + \[10325] <= n2203; + \[10340] <= n2208; + \[10355] <= n2213; + \[10370] <= n2218; + \[10400] <= n2223; + \[10415] <= n2228; + \[10430] <= n2233; + \[10445] <= n2238; + \[10460] <= n2243; + \[10475] <= n2248; + \[10490] <= n2253; + \[10505] <= n2258; + ppeaki_14_14_ <= n2263; + ppeaki_5_5_ <= n2267; + \[10550] <= n2271; + \[10565] <= n2276; + \[10580] <= n2281; + \[10595] <= n2286; + \[10610] <= n2291; + \[10625] <= n2296; + \[10655] <= n2301; + \[10670] <= n2306; + \[10685] <= n2311; + \[10700] <= n2316; + \[10715] <= n2321; + \[10730] <= n2326; + \[10745] <= n2331; + \[10760] <= n2336; + \[10775] <= n2341; + \[10790] <= n2346; + \[10805] <= n2351; + \[10820] <= n2356; + \[10850] <= n2361; + \[10865] <= n2366; + \[10880] <= n2371; + \[10895] <= n2376; + \[10925] <= n2381; + \[10940] <= n2386; + \[10955] <= n2391; + \[10970] <= n2396; + \[10985] <= n2401; + \[11015] <= n2406; + \[11030] <= n2411; + \[11045] <= n2416; + \[11060] <= n2421; + \[11075] <= n2426; + \[11090] <= n2431; + \[11120] <= n2436; + \[11135] <= n2441; + \[11150] <= n2446; + \[11165] <= n2451; + \[11180] <= n2456; + \[11195] <= n2461; + \[11210] <= n2466; + \[11225] <= n2471; + \[11240] <= n2476; + \[11255] <= n2481; + \[11270] <= n2486; + \[11285] <= n2491; + \[11300] <= n2496; + \[11315] <= n2501; + \[11330] <= n2506; + \[11345] <= n2511; + \[11375] <= n2516; + \[11390] <= n2521; + \[11405] <= n2526; + \[11420] <= n2531; + \[11435] <= n2536; + \[11450] <= n2541; + \[11465] <= n2546; + \[11480] <= n2551; + \[11495] <= n2556; + \[11510] <= n2561; + \[11525] <= n2566; + \[11540] <= n2571; + \[11555] <= n2576; + \[11570] <= n2581; + \[11585] <= n2586; + \[11600] <= n2591; + \[11615] <= n2596; + \[11630] <= n2601; + \[11645] <= n2606; + \[11660] <= n2611; + \[11675] <= n2616; + \[11690] <= n2621; + \[11705] <= n2626; + \[11720] <= n2631; + \[11735] <= n2636; + \[11750] <= n2641; + \[11765] <= n2646; + \[11780] <= n2651; + \[11795] <= n2656; + \[11810] <= n2661; + ppeaki_9_9_ <= n2666; + ppeakb_14_14_ <= n2670; + \[11885] <= n2674; + \[11900] <= n2679; + \[11915] <= n2684; + \[11930] <= n2689; + ppeaki_8_8_ <= n2694; + ppeakb_15_15_ <= n2698; + \[12005] <= n2702; + \[12020] <= n2707; + \[12035] <= n2712; + \[12050] <= n2717; + \[12065] <= n2722; + \[12080] <= n2727; + ppeaki_7_7_ <= n2732; + \[12125] <= n2736; + \[12140] <= n2741; + \[12155] <= n2746; + \[12170] <= n2751; + \[12185] <= n2756; + \[12200] <= n2761; + ppeakb_13_13_ <= n2766; + \[12245] <= n2770; + \[12260] <= n2775; + \[12275] <= n2780; + ppeaki_13_13_ <= n2785; + ppeaki_2_2_ <= n2789; + \[12335] <= n2793; + \[12350] <= n2798; + \[12365] <= n2803; + \[12380] <= n2808; + \[12395] <= n2813; + \[12410] <= n2818; + \[12425] <= n2823; + \[12440] <= n2828; + \[12455] <= n2833; + \[12470] <= n2838; + \[12485] <= n2843; + ppeaki_12_12_ <= n2848; + ppeaki_3_3_ <= n2852; + \[12545] <= n2856; + \[12560] <= n2861; + \[12575] <= n2866; + \[12590] <= n2871; + \[12605] <= n2876; + \[12620] <= n2881; + \[12635] <= n2886; + \[12650] <= n2891; + \[12665] <= n2896; + \[12680] <= n2901; + \[12695] <= n2906; + ppeaki_11_11_ <= n2911; + ppeaki_0_0_ <= n2915; + \[12770] <= n2919; + \[12800] <= n2924; + \[12815] <= n2929; + \[12830] <= n2934; + \[12845] <= n2939; + \[12860] <= n2944; + \[12875] <= n2949; + \[12890] <= n2954; + \[12905] <= n2959; + \[12920] <= n2964; + \[12935] <= n2969; + ppeaki_10_10_ <= n2974; + ppeaki_1_1_ <= n2978; + \[13010] <= n2982; + \[13025] <= n2987; + \[13040] <= n2992; + \[13055] <= n2997; + \[13070] <= n3002; + \[13085] <= n3007; + \[13100] <= n3012; + \[13115] <= n3017; + \[13130] <= n3022; + \[13160] <= n3027; + \[13175] <= n3032; + ppeakb_4_4_ <= n3037; + ppeaka_9_9_ <= n3041; + \[13220] <= n3045; + \[13235] <= n3050; + \[13250] <= n3055; + \[13265] <= n3060; + \[13280] <= n3065; + \[13295] <= n3070; + \[13310] <= n3075; + \[13325] <= n3080; + \[13340] <= n3085; + \[13355] <= n3090; + \[13370] <= n3095; + \[13385] <= n3100; + \[13400] <= n3105; + \[13415] <= n3110; + \[13430] <= n3115; + \[13445] <= n3120; + \[13460] <= n3125; + \[13475] <= n3130; + \[13490] <= n3135; + \[13505] <= n3140; + ppeakb_5_5_ <= n3145; + \[13550] <= n3149; + ppeakp_6_6_ <= n3154; + \[13580] <= n3158; + \[13595] <= n3163; + \[13610] <= n3168; + \[13625] <= n3173; + \[13640] <= n3178; + \[13655] <= n3183; + \[13670] <= n3188; + \[13685] <= n3193; + \[13700] <= n3198; + \[13715] <= n3203; + \[13730] <= n3208; + \[13745] <= n3213; + \[13775] <= n3218; + \[13790] <= n3223; + \[13805] <= n3228; + \[13820] <= n3233; + \[13835] <= n3238; + \[13850] <= n3243; + \[13865] <= n3248; + \[13880] <= n3253; + \[13895] <= n3258; + ppeaka_11_11_ <= n3263; + ppeaka_0_0_ <= n3267; + ppeakp_5_5_ <= n3271; + \[13955] <= n3275; + \[13970] <= n3280; + \[13985] <= n3285; + \[14000] <= n3290; + \[14015] <= n3295; + \[14030] <= n3300; + \[14045] <= n3305; + \[14060] <= n3310; + \[14075] <= n3315; + \[14090] <= n3320; + \[14105] <= n3325; + \[14120] <= n3330; + \[14135] <= n3335; + \[14150] <= n3340; + \[14165] <= n3345; + \[14180] <= n3350; + \[14210] <= n3355; + \[14225] <= n3360; + \[14240] <= n3365; + \[14255] <= n3370; + \[14270] <= n3375; + \[14285] <= n3380; + ppeakb_3_3_ <= n3385; + ppeaka_10_10_ <= n3389; + ppeaka_1_1_ <= n3393; + ppeakp_4_4_ <= n3397; + \[14360] <= n3401; + \[14375] <= n3406; + \[14390] <= n3411; + \[14405] <= n3416; + \[14420] <= n3421; + \[14435] <= n3426; + \[14450] <= n3431; + \[14465] <= n3436; + \[14480] <= n3441; + \[14495] <= n3446; + \[14510] <= n3451; + \[14525] <= n3456; + \[14540] <= n3461; + \[14555] <= n3466; + \[14570] <= n3471; + \[14585] <= n3476; + \[14600] <= n3481; + \[14615] <= n3486; + \[14630] <= n3491; + \[14660] <= n3496; + \[14675] <= n3501; + \[14690] <= n3506; + \[14705] <= n3511; + ppeakb_8_8_ <= n3516; + ppeaka_13_13_ <= n3520; + ppeaka_2_2_ <= n3524; + \[14765] <= n3528; + ppeaks_9_9_ <= n3533; + ppeakp_14_14_ <= n3537; + \[14810] <= n3541; + \[14825] <= n3546; + \[14840] <= n3551; + \[14855] <= n3556; + \[14870] <= n3561; + \[14885] <= n3566; + \[14900] <= n3571; + \[14915] <= n3576; + \[14930] <= n3581; + \[14960] <= n3586; + \[14975] <= n3591; + \[14990] <= n3596; + \[15005] <= n3601; + \[15020] <= n3606; + \[15035] <= n3611; + \[15050] <= n3616; + \[15065] <= n3621; + \[15080] <= n3626; + ppeakb_9_9_ <= n3631; + ppeaka_12_12_ <= n3635; + ppeaka_3_3_ <= n3639; + \[15140] <= n3643; + ppeaks_8_8_ <= n3648; + ppeakp_15_15_ <= n3652; + \[15185] <= n3656; + \[15200] <= n3661; + \[15215] <= n3666; + \[15230] <= n3671; + \[15245] <= n3676; + \[15260] <= n3681; + \[15275] <= n3686; + \[15290] <= n3691; + \[15305] <= n3696; + \[15320] <= n3701; + \[15335] <= n3706; + \[15350] <= n3711; + \[15365] <= n3716; + \[15380] <= n3721; + \[15395] <= n3726; + \[15410] <= n3731; + \[15425] <= n3736; + \[15440] <= n3741; + ppeakb_6_6_ <= n3746; + ppeaka_15_15_ <= n3750; + ppeaka_4_4_ <= n3754; + \[15500] <= n3758; + \[15515] <= n3763; + ppeaks_0_0_ <= n3768; + \[15545] <= n3772; + \[15560] <= n3777; + \[15575] <= n3782; + \[15590] <= n3787; + \[15605] <= n3792; + \[15620] <= n3797; + \[15635] <= n3802; + \[15650] <= n3807; + \[15665] <= n3812; + \[15680] <= n3817; + \[15695] <= n3822; + \[15710] <= n3827; + \[15725] <= n3832; + \[15755] <= n3837; + \[15770] <= n3842; + \[15785] <= n3847; + ppeakb_7_7_ <= n3852; + ppeaka_14_14_ <= n3856; + ppeaka_5_5_ <= n3860; + \[15845] <= n3864; + \[15860] <= n3869; + ppeaks_10_10_ <= n3874; + \[15890] <= n3878; + \[15905] <= n3883; + \[15920] <= n3888; + \[15935] <= n3893; + \[15950] <= n3898; + \[15965] <= n3903; + \[15980] <= n3908; + \[15995] <= n3913; + \[16010] <= n3918; + \[16025] <= n3923; + \[16040] <= n3928; + \[16055] <= n3933; + \[16070] <= n3938; + \[16085] <= n3943; + \[16100] <= n3948; + paddress_8_8_ <= n3953; + \[16907] <= n3957; + \[16920] <= n3962; + \[16933] <= n3967; + paddress_9_9_ <= n3972; + \[16959] <= n3976; + \[16972] <= n3981; + \[16985] <= n3986; + \[16998] <= n3991; + \[17011] <= n3996; + \[17024] <= n4001; + \[17037] <= n4006; + \[17050] <= n4011; + \[17063] <= n4016; + \[17076] <= n4021; + \[17089] <= n4026; + \[17102] <= n4031; + \[17115] <= n4036; + \[17128] <= n4041; + \[17141] <= n4046; + \[17154] <= n4051; + \[17167] <= n4056; + \[17180] <= n4061; + \[17193] <= n4066; + \[17206] <= n4071; + \[17219] <= n4076; + \[17232] <= n4081; + \[17245] <= n4086; + \[17258] <= n4091; + \[17271] <= n4096; + \[17284] <= n4101; + \[17297] <= n4106; + \[17310] <= n4111; + \[17323] <= n4116; + \[17336] <= n4121; + \[17349] <= n4126; + \[17362] <= n4131; + \[17375] <= n4136; + \[17388] <= n4141; + paddress_11_11_ <= n4146; + \[17414] <= n4150; + \[17427] <= n4155; + \[17453] <= n4160; + paddress_10_10_ <= n4165; + \[17479] <= n4169; + \[17492] <= n4174; + \[17505] <= n4179; + \[17518] <= n4184; + \[17531] <= n4189; + \[17544] <= n4194; + paddress_13_13_ <= n4199; + \[17570] <= n4203; + \[17583] <= n4208; + \[17596] <= n4213; + \[17609] <= n4218; + paddress_12_12_ <= n4223; + \[17635] <= n4227; + \[17648] <= n4232; + \[17661] <= n4237; + \[17674] <= n4242; + paddress_15_15_ <= n4247; + \[17700] <= n4251; + \[17713] <= n4256; + paddress_14_14_ <= n4261; + \[17739] <= n4265; + \[17752] <= n4270; + \[17765] <= n4275; + \[17778] <= n4280; + \[17791] <= n4285; + \[17804] <= n4290; + \[17817] <= n4295; + pwr_0_0_ <= n4300; + \[17843] <= n4304; + \[17856] <= n4309; + \[17869] <= n4314; + \[17882] <= n4319; + prd_0_0_ <= n4324; + \[17908] <= n4328; + \[17921] <= n4333; + \[17934] <= n4338; + \[17947] <= n4343; + \[17960] <= n4348; + \[17973] <= n4353; + \[17986] <= n4358; + \[17999] <= n4363; + \[18012] <= n4368; + \[18025] <= n4373; + \[18038] <= n4378; + pdn <= n4383; + \[18064] <= n4387; + \[18077] <= n4392; + \[18090] <= n4397; + \[18103] <= n4402; + \[18116] <= n4407; + \[18129] <= n4412; + \[18142] <= n4417; + \[18155] <= n4422; + \[18168] <= n4427; + \[18181] <= n4432; + \[18194] <= n4437; + \[18207] <= n4442; + \[18220] <= n4447; + \[18233] <= n4452; + \[18246] <= n4457; + paddress_0_0_ <= n4462; + piack_0_0_ <= n4466; + \[18285] <= n4470; + \[18298] <= n4475; + \[18311] <= n4480; + paddress_1_1_ <= n4485; + \[18337] <= n4489; + \[18350] <= n4494; + \[18363] <= n4499; + \[18376] <= n4504; + \[18389] <= n4509; + paddress_2_2_ <= n4514; + \[18415] <= n4518; + \[18428] <= n4523; + \[18441] <= n4528; + paddress_3_3_ <= n4533; + \[18467] <= n4537; + \[18480] <= n4542; + \[18493] <= n4547; + \[18506] <= n4552; + paddress_4_4_ <= n4557; + paddress_5_5_ <= n4561; + \[18545] <= n4565; + paddress_6_6_ <= n4570; + \[18571] <= n4574; + \[18584] <= n4579; + \[18597] <= n4584; + \[18610] <= n4589; + paddress_7_7_ <= n4594; + \[18636] <= n4598; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/misex3/misex3.v b/openfpga_flow/benchmarks/MCNC_Verilog/misex3/misex3.v new file mode 100644 index 000000000..95f1ee6e6 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/misex3/misex3.v @@ -0,0 +1,805 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:32:57 2019 + +module misex3 ( + a, b, c, d, e, f, g, h, i, j, k, l, m, n, + r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2 ); + input a, b, c, d, e, f, g, h, i, j, k, l, m, n; + output r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2; + wire n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, + n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, + n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, + n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, + n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, + n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, + n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, + n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, + n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, + n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, + n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, + n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, + n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, + n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, + n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, + n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, + n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, + n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, + n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, + n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, + n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, + n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, + n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, + n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, + n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, + n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, + n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, + n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, + n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, + n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, + n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, + n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, + n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, + n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, + n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, + n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, + n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, + n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, + n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, + n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, + n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, + n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, + n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, + n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, + n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, + n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, + n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, + n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, + n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, + n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, + n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, + n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, + n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, + n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, + n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, + n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, + n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, + n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, + n758, n759, n760, n761, n762; + assign r2 = ~n293; + assign s2 = ~n74; + assign t2 = ~n217; + assign u2 = ~n148; + assign n2 = ~n68; + assign o2 = ~n62; + assign p2 = ~n388; + assign q2 = ~n349; + assign h2 = ~n56; + assign i2 = ~n569; + assign j2 = ~n55; + assign k2 = ~n50; + assign m2 = ~n456; + assign l2 = ~n757 | ~n759 | n46 | ~n747 | n44 | n45 | n42 | n43; + assign n42 = f & (~n680 | ~n739 | ~n740); + assign n43 = ~f & (n475 | n476 | ~n735); + assign n44 = ~n & (~n722 | ~n724 | ~n728); + assign n45 = n & (~n518 | ~n730 | ~n731); + assign n46 = n548 | ~n744 | n544 | n547 | n542 | ~n543 | ~n540 | n541; + assign n47 = n675 | n676 | n372 | i | l; + assign n48 = n438 | n549 | n189; + assign n49 = n434 & n662 & n661 & n51 & n437 & n439; + assign n50 = n49 & n47 & n48; + assign n51 = n657 & n573 & n656 & n431 & n425 & n428; + assign n52 = n443 & n442 & n440 & n441; + assign n53 = n675 | n189 | n438; + assign n54 = n179 | n480 | n550 | n551; + assign n55 = n54 & n53 & n51 & n52; + assign n56 = n579 & n578 & n577 & n576 & n575 & n574 & n572 & n573; + assign n57 = (n95 | n408) & (n409 | n88); + assign n58 = n96 | n121; + assign n59 = n648 & ~n404 & n361 & n402; + assign n60 = n83 | n317; + assign n61 = (n362 | n300) & (n363 | n426); + assign n62 = ~n416 & ~n415 & ~n414 & n61 & n60 & n59 & n57 & n58; + assign n63 = j | n243 | n119 | n591; + assign n64 = (n177 | n362) & (n684 | n409); + assign n65 = ~n297 & (n95 | n253 | n298); + assign n66 = n620 & n619 & n572 & n618 & n617 & n69 & n574 & n211; + assign n67 = ~n422 & (n591 | (n710 & n711)); + assign n68 = ~n420 & ~n419 & n67 & n66 & n65 & n64 & n59 & n63; + assign n69 = n92 | n407 | n91; + assign n70 = n595 | n92; + assign n71 = n264 | ~d | n248; + assign n72 = n701 & (n236 | n79); + assign n73 = n232 & (n152 | n632); + assign n74 = ~n267 & ~n266 & ~n265 & n73 & n72 & n71 & n69 & n70; + assign n75 = ~h | ~k; + assign n76 = n75 | l; + assign n77 = n623 | ~n658; + assign n78 = ~n167 & (n77 | ~n586); + assign n79 = ~c | n459; + assign n80 = e | n521; + assign n81 = n612 & n302; + assign n82 = n81 & n79 & n80; + assign n83 = ~k | n199; + assign n84 = m | j | ~l; + assign n85 = n83 & (~n | n84); + assign n86 = n684 | n83; + assign n87 = (n192 | n605) & (n206 | n604); + assign n88 = ~g | n603; + assign n89 = n86 & n87 & (n85 | n88); + assign n90 = (n110 | n156) & (n113 | n275); + assign n91 = ~i | n538; + assign n92 = ~a | n521; + assign n93 = n90 & (n91 | n92); + assign n94 = ~g | n600; + assign n95 = n285 & n397; + assign n96 = ~k | n167; + assign n97 = n96 | n94 | n95; + assign n98 = n601 | n199; + assign n99 = ~i | n368; + assign n100 = n98 & (~n | n99); + assign n101 = ~h | n538; + assign n102 = ~n | n129; + assign n103 = h | n538; + assign n104 = (n100 | n103) & (n101 | n102); + assign n105 = ~g | n249; + assign n106 = h | n197; + assign n107 = (n100 | n106) & (n102 | n105); + assign n108 = ~k | n179; + assign n109 = n108 & (n | n84); + assign n110 = n608 & n287 & n607; + assign n111 = (n101 | n92) & (n110 | n105); + assign n112 = n135 | n119; + assign n113 = n218 & n295; + assign n114 = ~g | n393; + assign n115 = n112 & n111 & (n113 | n114); + assign n116 = (n110 | n164) & (n113 | n189); + assign n117 = e | n609; + assign n118 = n116 & (n92 | n117); + assign n119 = ~a | n271; + assign n120 = ~e | n609; + assign n121 = n118 & (n119 | n120); + assign n122 = (n110 | n106) & (n113 | n202); + assign n123 = n122 & (n92 | n103); + assign n124 = n153 | n399; + assign n125 = ~n610 | ~g | n237; + assign n126 = j | n154; + assign n127 = ~i | n609; + assign n128 = n124 & n125 & (n126 | n127); + assign n129 = n401 & n512 & n527 & n760; + assign n130 = (n106 | n99) & (n129 | n105); + assign n131 = n519 | ~i | n121; + assign n132 = (n123 | n588) & (n95 | n128); + assign n133 = ~e | n271; + assign n134 = n131 & n132 & (n130 | n133); + assign n135 = ~h | n243; + assign n136 = h | n243; + assign n137 = (n100 | n136) & (n135 | n102); + assign n138 = ~n137 & (~n625 | (b & ~n479)); + assign n139 = ~n89 & (~n325 | ~n606); + assign n140 = ~n167 & (~n683 | (~n121 & ~n601)); + assign n141 = ~n95 & (~n687 | (~n96 & ~n127)); + assign n142 = n133 | n601 | n179 | n106; + assign n143 = n590 | n591; + assign n144 = n136 | n587 | n588; + assign n145 = ~n139 & ~n140 & (n | n134); + assign n146 = (n93 | n591) & (n104 | n616); + assign n147 = n688 & (n107 | n269); + assign n148 = n147 & n146 & n145 & n144 & n143 & n142 & n66 & ~n138; + assign n149 = n689 | n108; + assign n150 = (n372 | n193) & (n613 | n624); + assign n151 = ~f | n603; + assign n152 = n149 & n150 & (n109 | n151); + assign n153 = ~m | n611; + assign n154 = ~l | ~m; + assign n155 = n153 & (i | n154); + assign n156 = ~i | n197; + assign n157 = j | n197; + assign n158 = n156 & n157; + assign n159 = (n155 | n105) & (n158 | n589); + assign n160 = n690 & (n164 | n126); + assign n161 = n644 & n647; + assign n162 = i | n197; + assign n163 = n159 & n160 & (n161 | n162); + assign n164 = g | n249; + assign n165 = (n164 | n96) & (n | n163); + assign n166 = n75 | ~m | n; + assign n167 = ~m | n; + assign n168 = ~l | ~h | j; + assign n169 = n166 & (n167 | n168); + assign n170 = ~f | n243; + assign n171 = ~e | n196; + assign n172 = (n169 | n171) & (~n78 | n170); + assign n173 = n196 | d | n169; + assign n174 = d | n197; + assign n175 = n173 & (~n78 | n174); + assign n176 = j | n75; + assign n177 = n176 & (i | n75); + assign n178 = n299 & n300 & n76 & n177; + assign n179 = m | n; + assign n180 = j | n603; + assign n181 = ~l | n179; + assign n182 = (n180 | n181) & (n178 | n179); + assign n183 = ~e | n615; + assign n184 = ~n | n183; + assign n185 = (n99 | n184) & (n98 | n183); + assign n186 = ~n184 & ~n761 & (~n114 | ~n189); + assign n187 = ~n186 & (n185 | (n202 & n676)); + assign n188 = n183 | n391; + assign n189 = g | n393; + assign n190 = n187 & (n188 | (n114 & n189)); + assign n191 = (n206 | n624) & (n689 | n83); + assign n192 = k | n199; + assign n193 = ~j | n249; + assign n194 = n191 & (n192 | n193); + assign n195 = n194 & (n85 | n151); + assign n196 = ~f | g; + assign n197 = ~f | ~g; + assign n198 = (n169 | n196) & (~n78 | n197); + assign n199 = m | ~n; + assign n200 = ~l | n199; + assign n201 = (n180 | n200) & (n178 | n199); + assign n202 = h | n570; + assign n203 = (n100 | n202) & (n102 | n114); + assign n204 = n203 & (n201 | (n170 & n171)); + assign n205 = n691 & n692 & (n85 | n314); + assign n206 = l | n199; + assign n207 = ~k | n393; + assign n208 = n89 & n205 & (n206 | n207); + assign n209 = ~n152 & (~n133 | ~n430); + assign n210 = n595 | n599; + assign n211 = n595 | n353; + assign n212 = n693 & (~e | n195 | n324); + assign n213 = ~n209 & (n285 | (n165 & n595)); + assign n214 = n208 | n315; + assign n215 = (n172 | n119) & (n175 | n287); + assign n216 = n694 & (n182 | n302); + assign n217 = n216 & n190 & n215 & n214 & n213 & n212 & n210 & n211; + assign n218 = ~a | n560; + assign n219 = n167 | n218; + assign n220 = (n168 | n219) & (n218 | n166); + assign n221 = ~n658 | ~n586 | n623; + assign n222 = ~f & ~n538; + assign n223 = ~n219 & n221 & (n222 | ~n261); + assign n224 = e | n488; + assign n225 = e | n196; + assign n226 = ~n223 & (n220 | (n224 & n225)); + assign n227 = n393 | ~j | n372; + assign n228 = (n613 | n207) & (n109 | n314); + assign n229 = n640 & n643; + assign n230 = n227 & n228 & (n229 | n108); + assign n231 = ~e | n626; + assign n232 = n190 & n226 & (n230 | n231); + assign n233 = ~n83 & (~n252 | ~n639); + assign n234 = (n192 | n322) & (n256 | n206); + assign n235 = g | n603; + assign n236 = ~n233 & n234 & (n85 | n235); + assign n237 = k | n154; + assign n238 = (i | n161) & (~j | n237); + assign n239 = ~n591 & (~n91 | (~j & ~n538)); + assign n240 = ~n239 & (n | (n699 & n700)); + assign n241 = n165 & n240 & (n96 | n117); + assign n242 = ~i | n243; + assign n243 = ~e | ~g; + assign n244 = n242 & (j | n243); + assign n245 = n96 | n120; + assign n246 = n697 & (n120 | n126); + assign n247 = n696 & n695 & (n244 | n589); + assign n248 = n245 & (n | (n246 & n247)); + assign n249 = ~f | ~h; + assign n250 = n249 | n102 | e; + assign n251 = n629 & n88; + assign n252 = j | n609; + assign n253 = i | n602; + assign n254 = ~g | n360; + assign n255 = n254 & n253 & n251 & n252; + assign n256 = g | n75; + assign n257 = n698 & (n376 | (n628 & n649)); + assign n258 = (n94 | n96) & (n629 | n630); + assign n259 = ~l | n167; + assign n260 = n257 & n258 & (n255 | n259); + assign n261 = ~f | n538; + assign n262 = (n169 | n225) & (~n78 | n261); + assign n263 = ~n260 & (~n655 | (d & ~n524)); + assign n264 = a | ~b; + assign n265 = ~n201 & (~n325 | (~n261 & ~n616)); + assign n266 = ~n352 & (~n262 | n263); + assign n267 = ~n526 & (~n250 | (~n100 & ~n631)); + assign n268 = n344 & (n83 | n633); + assign n269 = ~b | n598; + assign n270 = n268 & (n194 | n269); + assign n271 = ~c | d; + assign n272 = n79 & (~f | n271); + assign n273 = (n100 | n634) & (n164 | n102); + assign n274 = n273 & n107; + assign n275 = ~i | n570; + assign n276 = j | n570; + assign n277 = n275 & n276; + assign n278 = (n155 | n114) & (n277 | n589); + assign n279 = n749 & (n189 | n126); + assign n280 = i | n570; + assign n281 = n278 & n279 & (n161 | n280); + assign n282 = (n96 | n189) & (n | n281); + assign n283 = n286 | g | n169; + assign n284 = n283 & (d | ~n78 | n243); + assign n285 = ~e | n264; + assign n286 = d | ~e; + assign n287 = c | ~a | ~b; + assign n288 = n285 & (n286 | n287); + assign n289 = (n236 | n635) & (n104 | n616); + assign n290 = (n260 | n288) & (n284 | ~n545); + assign n291 = n107 | n315; + assign n292 = (n182 | n272) & (n274 | n625); + assign n293 = n292 & n291 & n290 & n289 & n270 & n232; + assign n294 = n123 & (n119 | n136); + assign n295 = n596 & n594; + assign n296 = n112 & n111 & (n295 | n114); + assign n297 = ~n636 & (~n355 | (~n167 & ~n296)); + assign n298 = n | n126; + assign n299 = ~h | n360; + assign n300 = ~k | n603; + assign n301 = n180 & n300 & n299 & n176; + assign n302 = ~c | n524; + assign n303 = n302 & (~c | n196); + assign n304 = (n113 | n646) & (~j | n645); + assign n305 = ~j | n197; + assign n306 = n304 & (n110 | n305); + assign n307 = n121 & (n95 | n94); + assign n308 = ~n95 & ~n644 & (~n88 | ~n660); + assign n309 = ~n308 & (n329 | n339 | n435); + assign n310 = (n118 | n126) & (n306 | n237); + assign n311 = ~l | n519; + assign n312 = n309 & n310 & (n307 | n311); + assign n313 = n183 & n390; + assign n314 = f | n603; + assign n315 = ~b | n286; + assign n316 = (n314 | n315) & (n313 | n235); + assign n317 = n633 & n316; + assign n318 = (n80 & (~n | n371)) | (n & n371); + assign n319 = (n88 | n318) & (~n | n317); + assign n320 = n393 | ~j | n315; + assign n321 = n269 | n193; + assign n322 = ~j | n609; + assign n323 = n320 & n321 & (n313 | n322); + assign n324 = b | ~c; + assign n325 = ~f | n324; + assign n326 = (n315 | n643) & (n313 | n252); + assign n327 = j | n249; + assign n328 = n326 & (n269 | n327); + assign n329 = ~h | n621; + assign n330 = n328 & (n325 | n329); + assign n331 = (n316 | n84) & (n330 | n435); + assign n332 = m | k | ~l; + assign n333 = n331 & (n323 | n332); + assign n334 = (n315 | n640) & (n313 | n639); + assign n335 = i | n249; + assign n336 = n334 & (n269 | n335); + assign n337 = ~n199 & (~n336 | (~n253 & ~n371)); + assign n338 = ~n337 & (n80 | n179 | n253); + assign n339 = n303 & n637; + assign n340 = (n339 | n181) & (n325 | n200); + assign n341 = ~n318 & (~n704 | (~n332 & ~n605)); + assign n342 = n243 | n490 | ~j | n119; + assign n343 = n298 | n119 | n120; + assign n344 = n633 | ~n | n84; + assign n345 = n705 & (n301 | n340); + assign n346 = n65 & (n319 | n435); + assign n347 = (n312 & (~n | n333)) | (n & n333); + assign n348 = (n682 | n641) & (n338 | n433); + assign n349 = n348 & n347 & n346 & n345 & n344 & n343 & ~n341 & n342; + assign n350 = (n113 | n280) & (i | n645); + assign n351 = n350 & (n110 | n162); + assign n352 = ~a | n324; + assign n353 = ~b | n597; + assign n354 = n353 & n287 & n352; + assign n355 = n114 | n219; + assign n356 = (n599 | n105) & (n295 | n114); + assign n357 = n112 & (n92 | (n105 & n101)); + assign n358 = n355 & (n167 | (n356 & n357)); + assign n359 = n707 & (n285 | n630 | n605); + assign n360 = ~j | k; + assign n361 = n359 & (n358 | n360); + assign n362 = (n339 | n179) & (n325 | n199); + assign n363 = (n339 | n108) & (n325 | n83); + assign n364 = ~n88 & (~n706 | (~n167 & ~n433)); + assign n365 = ~n364 & (n629 | (n259 & n630)); + assign n366 = n365 & (n96 | n322); + assign n367 = n519 | n | n121; + assign n368 = ~k | m; + assign n369 = (n253 | n318) & (~n | n336); + assign n370 = n367 & (n368 | (n369 & n319)); + assign n371 = n395 & n315 & n606; + assign n372 = k | n179; + assign n373 = (n372 | n80) & (n371 | n192); + assign n374 = ~i | k | ~l | n167; + assign n375 = ~k | ~n610; + assign n376 = l | n167; + assign n377 = n374 & (n375 | (n376 & n259)); + assign n378 = ~j | n603; + assign n379 = n378 & n329; + assign n380 = n644 | n587 | n627; + assign n381 = n647 | n587 | n627; + assign n382 = n351 | n | n161; + assign n383 = (n294 | n377) & (n363 | n379); + assign n384 = n373 | n605; + assign n385 = (n95 | n366) & (~j | n370); + assign n386 = n362 | n299; + assign n387 = n361 & (n323 | n192); + assign n388 = n387 & n386 & n385 & n384 & n383 & n382 & n380 & n381; + assign n389 = ~n372 & (~n303 | ~n637); + assign n390 = n635 & n638; + assign n391 = ~n | n401; + assign n392 = n188 & (n390 | n391); + assign n393 = f | ~h; + assign n394 = (n393 | n315) & (n249 | n269); + assign n395 = n616 & n625; + assign n396 = e | n324; + assign n397 = ~b | n524; + assign n398 = n397 & n396 & n395 & n315; + assign n399 = ~i | n602; + assign n400 = (n398 | n399) & (~i | n394); + assign n401 = m | n360; + assign n402 = n399 | n | n80 | n401; + assign n403 = h & n610; + assign n404 = n403 & (n389 | (~n192 & ~n325)); + assign n405 = n253 | n641; + assign n406 = (n256 | n167) & (n376 | n176); + assign n407 = n | n592; + assign n408 = n405 & n406 & (n407 | n399); + assign n409 = (n108 | n80) & (n371 | n83); + assign n410 = i & ~n394; + assign n411 = n & (n410 | (~n127 & ~n313)); + assign n412 = j | i; + assign n413 = n412 | ~k | n259; + assign n414 = ~n115 & (~n413 | (n77 & ~n167)); + assign n415 = ~n527 & (n411 | (~n318 & ~n399)); + assign n416 = ~n591 & (~n709 | (~n110 & ~n327)); + assign n417 = ~n433 & (~n351 | (~n119 & ~n627)); + assign n418 = ~n311 & ~n & ~n251; + assign n419 = ~n95 & (n418 | (~n376 & ~n649)); + assign n420 = ~n83 & (~n328 | ~n336); + assign n421 = i & k; + assign n422 = ~n167 & (n417 | (~n294 & n421)); + assign n423 = n654 | ~f | n598; + assign n424 = j | k; + assign n425 = n259 | n399 | n423 | n424; + assign n426 = ~h | n600; + assign n427 = n651 | ~n | n557; + assign n428 = n427 | n426 | n332; + assign n429 = n650 | n114 | n181; + assign n430 = ~e | n521; + assign n431 = n429 | n430; + assign n432 = ~n545 | n655; + assign n433 = ~l | ~j | ~k; + assign n434 = n399 | n167 | n432 | n433; + assign n435 = ~l | n368; + assign n436 = n170 | n526; + assign n437 = n436 | ~n403 | n435; + assign n438 = n181 | n375; + assign n439 = n438 | n231 | n105; + assign n440 = n652 | n202 | n632; + assign n441 = ~n653 | n435 | n445; + assign n442 = n181 | n202 | n430 | ~n473; + assign n443 = n712 & (n332 | n427 | n378); + assign n444 = n106 | n613 | n231 | n658; + assign n445 = h | n621; + assign n446 = m | k | l; + assign n447 = n444 & (n436 | n445 | n446); + assign n448 = n551 | n | n446; + assign n449 = n448 & (n179 | n127 | n433); + assign n450 = k | n189 | n181 | n632; + assign n451 = n332 | n651 | ~h | n224; + assign n452 = n450 & n451; + assign n453 = n641 | n654 | n660 | n477; + assign n454 = n105 | n181 | n549 | n650; + assign n455 = (n449 | n480) & (n452 | n412); + assign n456 = n455 & n454 & n453 & n49 & n52 & n447; + assign n457 = i | n179; + assign n458 = (~k | n457) & (n179 | ~n412); + assign n459 = e | ~f; + assign n460 = a | n526; + assign n461 = j & ~n630 & (n459 | n460); + assign n462 = ~n758 & (~h | n438 | ~n479); + assign n463 = f | ~c | e; + assign n464 = ~n461 & n462 & (n458 | n463); + assign n465 = b | n199; + assign n466 = n200 & n83 & n465 & n298; + assign n467 = (b | n200) & (c | n181); + assign n468 = ~n167 & (~n737 | (~b & ~n479)); + assign n469 = h | j | n199; + assign n470 = (j | n83) & (~i | n663); + assign n471 = ~j | n199; + assign n472 = n469 & n470 & (~h | n471); + assign n473 = ~k & n610; + assign n474 = n473 & b & ~n199; + assign n475 = ~h & (n474 | (~i & ~n206)); + assign n476 = ~n673 & (~n521 | (~e & n324)); + assign n477 = f | n659; + assign n478 = n477 & (f | a | e); + assign n479 = c | d; + assign n480 = f | n479; + assign n481 = n669 | c | e; + assign n482 = b | e | ~n | n669; + assign n483 = n375 | ~n615 | ~h | n259; + assign n484 = (d | n734) & (n457 | n480); + assign n485 = n199 | n675; + assign n486 = ~n762 & n485 & n484 & n483 & n481 & n482; + assign n487 = c & ~n655; + assign n488 = f | g; + assign n489 = b | n488; + assign n490 = n | n237; + assign n491 = (j | n490) & (n199 | ~n626); + assign n492 = ~n199 & (~n741 | (~j & ~n525)); + assign n493 = n742 & (n670 | n671); + assign n494 = ~n492 & ~n756 & (i | n491); + assign n495 = n493 & n494 & (n457 | n271); + assign n496 = c | n488; + assign n497 = n664 & n463; + assign n498 = (n106 | n231) & (~j | n497); + assign n499 = (n716 | n167) & (n498 | n179); + assign n500 = n496 | n372; + assign n501 = (n527 | n671) & (n719 | n613); + assign n502 = n718 & (n436 | (n206 & n192)); + assign n503 = n502 & n501 & n499 & n500; + assign n504 = ~j & ~n372 & (~n271 | ~n302); + assign n505 = (b | n199) & (c | n179); + assign n506 = ~b | ~e | ~n | n666; + assign n507 = e | n505 | n650; + assign n508 = (n525 | n471) & (n457 | n479); + assign n509 = n478 | n167; + assign n510 = ~n626 | j | n192; + assign n511 = n510 & n509 & n508 & n507 & ~n504 & n506; + assign n512 = i | n368; + assign n513 = m | n603; + assign n514 = i | m; + assign n515 = n512 & n513 & (~l | n514); + assign n516 = n253 & n127; + assign n517 = (n426 | n446) & (n516 | n666); + assign n518 = n517 & (n401 | n151); + assign n519 = ~k | ~m; + assign n520 = n519 & (j | ~m); + assign n521 = c | ~d; + assign n522 = n81 & (g | n521); + assign n523 = ~n311 & n403 & (~n174 | ~n261); + assign n524 = ~e | f; + assign n525 = b | n524; + assign n526 = ~d | n615; + assign n527 = j | n368; + assign n528 = n99 & n527; + assign n529 = n717 & (h | n524 | n636); + assign n530 = (n521 | n525) & (~j | n716); + assign n531 = (i | n432) & (n254 | n665); + assign n532 = n634 & n550 & (n135 | n650); + assign n533 = n532 & n531 & n529 & n530; + assign n534 = ~c & ~n524; + assign n535 = (~n180 | ~n628) & (~n463 | n534); + assign n536 = ~j & (~n660 | (~n156 & ~n231)); + assign n537 = n396 & (a | c | e); + assign n538 = e | ~g; + assign n539 = ~n162 & (~n108 | ~n181); + assign n540 = n375 | n259 | n114; + assign n541 = ~n489 & (~n206 | ~n663); + assign n542 = ~n613 & (~n497 | (~c & ~n660)); + assign n543 = n438 | n101; + assign n544 = ~n231 & (n539 | (~n156 & ~n613)); + assign n545 = a & ~n615; + assign n546 = n545 & ~n655 & (~n630 | ~n672); + assign n547 = ~n457 & (~n631 | (~n105 & ~n231)); + assign n548 = ~n179 & (n535 | n536 | ~n715); + assign n549 = ~e | n479; + assign n550 = l | n424; + assign n551 = i | g | h; + assign n552 = n112 | n155 | n; + assign n553 = n119 | n245; + assign n554 = f | n167; + assign n555 = (n168 | n554) & (f | n166); + assign n556 = n555 | ~e | g; + assign n557 = f | n243; + assign n558 = n556 & (~n78 | n557); + assign n559 = ~n99 & ~g & n; + assign n560 = ~b | ~d; + assign n561 = (n203 | n560) & (n526 | ~n748); + assign n562 = (n175 | n287) & (n282 | n594); + assign n563 = n236 | n638; + assign n564 = (n352 | n558) & (~e | n561); + assign n565 = n608 | n172; + assign n566 = n677 & n553 & n552 & n342 & n143 & n63; + assign n567 = n226 & n270 & (n89 | n625); + assign n568 = n750 & n752 & n656 & n661 & n441 & n657 & n440 & n662; + assign n569 = n568 & n567 & n447 & n566 & n565 & n564 & n562 & n563; + assign n570 = f | ~g; + assign n571 = (g | n555) & (~n78 | n570); + assign n572 = n595 | n352; + assign n573 = n652 | n106 | n549; + assign n574 = n593 | n596; + assign n575 = n626 | ~a | n262; + assign n576 = n571 | ~d | ~n545; + assign n577 = n753 & (n654 | (n175 & n248)); + assign n578 = n282 | n596; + assign n579 = n566 & (n165 | n352); + assign n580 = l | ~n421; + assign n581 = ~l | ~h | i; + assign n582 = (~l & n622) | (n603 & (l | n622)); + assign n583 = ~h | n611; + assign n584 = ~l | n360; + assign n585 = ~l | n621; + assign n586 = n585 & n584 & n583 & n582 & n580 & n581; + assign n587 = n | n119; + assign n588 = ~i | n154; + assign n589 = l | n519; + assign n590 = n119 | n242; + assign n591 = n | n589; + assign n592 = j | n519; + assign n593 = n407 | n275; + assign n594 = ~a | n286; + assign n595 = n156 | n407; + assign n596 = ~e | ~a | ~c; + assign n597 = d | a; + assign n598 = ~d | e; + assign n599 = ~a | n598; + assign n600 = ~i | j; + assign n601 = ~l | n600; + assign n602 = ~g | ~h; + assign n603 = h | ~i; + assign n604 = ~g | n75; + assign n605 = ~j | n602; + assign n606 = n396 & n397; + assign n607 = n599 & n353; + assign n608 = n92 & n352; + assign n609 = g | ~h; + assign n610 = i & j; + assign n611 = ~j | l; + assign n612 = ~f | n521; + assign n613 = l | n179; + assign n614 = ~g | ~n421; + assign n615 = ~b | ~c; + assign n616 = d | n615; + assign n617 = n590 | n407; + assign n618 = n593 | n594; + assign n619 = n97 & n70 & n210; + assign n620 = (n595 | n287) & (n593 | n218); + assign n621 = i | ~j; + assign n622 = j | ~k; + assign n623 = k & ~n600; + assign n624 = ~k | n249; + assign n625 = ~b | n521; + assign n626 = ~c | ~d; + assign n627 = i | n243; + assign n628 = n614 & n605; + assign n629 = ~g | n621; + assign n630 = k | n167; + assign n631 = h | n459; + assign n632 = e | n626; + assign n633 = n269 | n151; + assign n634 = h | n196; + assign n635 = ~b | n459; + assign n636 = ~l | n412; + assign n637 = n612 & n272; + assign n638 = ~f | n560; + assign n639 = i | n609; + assign n640 = i | n393; + assign n641 = n622 | ~l | n167; + assign n642 = j | n602; + assign n643 = j | n393; + assign n644 = ~j | n154; + assign n645 = n538 | n92; + assign n646 = ~j | n570; + assign n647 = ~m | n360; + assign n648 = (n392 | n127) & (n400 | n391); + assign n649 = ~g | n622; + assign n650 = k | n600; + assign n651 = b | n626; + assign n652 = n621 | ~k | n181; + assign n653 = n222 & ~n526; + assign n654 = a | n615; + assign n655 = ~f | ~d | ~e; + assign n656 = ~n653 | n332 | n426; + assign n657 = n632 | n429; + assign n658 = k | n621; + assign n659 = d | e; + assign n660 = i | ~g | h; + assign n661 = n445 | n435 | n427; + assign n662 = n430 | n202 | n652; + assign n663 = n83 & n471; + assign n664 = ~g | n479; + assign n665 = a | n598; + assign n666 = m | n424; + assign n667 = ~h | n514; + assign n668 = k | n514; + assign n669 = h | n514; + assign n670 = m | n600; + assign n671 = n | n479; + assign n672 = h | n167; + assign n673 = g | n199; + assign n674 = h & ~n650; + assign n675 = e | n479; + assign n676 = h | n488; + assign n677 = n343 & n144 & n454 & n617 & n381 & n380; + assign n678 = (e & ~n119) | (~n92 & (~e | ~n119)); + assign n679 = (n479 & n674) | (~g & (~n479 | n674)); + assign n680 = n755 & (i | n466 | h); + assign n681 = ~n610 | l | n115; + assign n682 = n590 & n93; + assign n683 = n681 & (n682 | n584); + assign n684 = n642 & n253; + assign n685 = (n684 | n108) & (n109 | n88); + assign n686 = (n605 | n372) & (n604 | n613); + assign n687 = (n614 | n376) & (n88 | n259); + assign n688 = ~n141 & (n82 | (n685 & n686)); + assign n689 = n335 & n327; + assign n690 = (n588 | n106) & (n237 | n305); + assign n691 = n229 | n83; + assign n692 = n393 | ~j | n192; + assign n693 = ~a | b | ~d | n198; + assign n694 = (n607 | n165) & (n204 | n625); + assign n695 = (n161 | n627) & (n155 | n135); + assign n696 = n243 | ~j | n237; + assign n697 = (n588 | n136) & (n242 | n592); + assign n698 = n256 | n167; + assign n699 = (n155 | n101) & (n238 | n538); + assign n700 = (n588 | n103) & (n117 | n126); + assign n701 = (n182 | n612) & (n241 | n92); + assign n702 = ~n294 & (~n585 | (l & n610)); + assign n703 = ~n95 & (~n252 | ~n254 | ~n256); + assign n704 = (n84 | n88) & (n642 | n435); + assign n705 = (n167 | ~n702) & (n259 | ~n703); + assign n706 = n490 & (n96 | n611); + assign n707 = n354 | n360 | n167 | n105; + assign n708 = ~h | j; + assign n709 = (n113 | n643) & (~n678 | n708); + assign n710 = (n95 | n88) & (j | n645); + assign n711 = (n110 | n157) & (n113 | n276); + assign n712 = n167 | n127 | n584 | n423; + assign n713 = (d | n525) & (j | n436); + assign n714 = (b | c) & (n127 | n433); + assign n715 = (n253 | n463) & (n103 | ~n473); + assign n716 = n676 & n478; + assign n717 = a | b; + assign n718 = n433 | n487 | ~h | n199; + assign n719 = n496 & ~n534; + assign n720 = n478 & n665 & n432; + assign n721 = ~n523 & (g | n520 | n720); + assign n722 = n721 & (n670 | (n496 & n480)); + assign n723 = (n522 | n669) & (n164 | n666); + assign n724 = n723 & (n668 | (n202 & n664)); + assign n725 = n231 | n156 | n401; + assign n726 = n592 | n432; + assign n727 = n725 & n726 & (n719 | n667); + assign n728 = n518 & n727 & (n496 | n515); + assign n729 = (n436 | n667) & (n525 | n528); + assign n730 = n729 & (n515 | n436); + assign n731 = (n669 | n397) & (n525 | n668); + assign n732 = n526 | e | n472; + assign n733 = n672 | ~n597 | n636; + assign n734 = n754 & (~h | n438); + assign n735 = n732 & n733 & (~c | n734); + assign n736 = n | a | ~g; + assign n737 = (i | n665) & (~n545 | n659); + assign n738 = ~n468 & (n311 | ~n403 | n736); + assign n739 = n738 & (n665 | (n672 & n96)); + assign n740 = (n549 | n673) & (n179 | ~n679); + assign n741 = n489 & (e | n254); + assign n742 = ~n629 | k | n206; + assign n743 = ~n546 & (n537 | n554); + assign n744 = n743 & (n199 | (n714 & n713)); + assign n745 = (n720 | n376) & (n533 | n167); + assign n746 = (n192 | n327) & (~i | n503); + assign n747 = n745 & n746 & (n591 | n445); + assign n748 = ~h & (n559 | (~n601 & ~n673)); + assign n749 = (n588 | n202) & (n237 | n646); + assign n750 = n53 & n47 & n618; + assign n751 = n526 | n102 | n120; + assign n752 = n751 & (n651 | (n104 & n195)); + assign n753 = n449 | n480; + assign n754 = ~n473 | h | n179; + assign n755 = n467 | ~h | n375; + assign n756 = i & ~k & (~n376 | ~n613); + assign n757 = (n495 & (~h | n511)) | (h & n511); + assign n758 = ~h & (~n96 | (c & ~n457)); + assign n759 = (n464 & (~g | n486)) | (g & n486); + assign n760 = l | n368; + assign n761 = n760 & n512 & n527; + assign n762 = n674 & ~n167 & n460; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/pdc/pdc.v b/openfpga_flow/benchmarks/MCNC_Verilog/pdc/pdc.v new file mode 100644 index 000000000..f1adc4cfa --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/pdc/pdc.v @@ -0,0 +1,2558 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:33:19 2019 + +module pdc ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, + i_11_, i_12_, i_13_, i_14_, i_15_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, + i_10_, i_11_, i_12_, i_13_, i_14_, i_15_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_; + wire n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, + n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, + n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, + n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, + n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, + n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, + n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, + n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, + n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, + n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, + n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, + n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, + n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, + n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, + n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, + n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, + n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, + n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, + n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, + n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, + n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, + n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, + n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, + n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, + n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, + n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, + n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, + n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, + n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, + n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, + n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, + n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, + n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, + n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, + n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, + n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, + n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, + n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, + n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, + n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, + n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, + n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, + n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, + n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, + n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, + n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, + n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, + n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, + n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, + n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, + n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, + n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, + n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, + n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, + n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, + n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, + n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, + n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, + n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, + n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, + n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, + n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, + n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, + n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, + n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, + n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, + n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, + n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, + n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, + n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, + n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, + n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, + n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, + n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, + n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, + n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, + n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, + n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, + n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, + n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, + n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, + n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, + n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, + n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, + n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, + n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, + n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, + n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, + n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, + n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, + n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, + n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, + n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, + n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, + n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, + n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, + n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, + n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, + n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, + n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, + n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, + n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, + n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, + n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, + n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, + n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, + n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, + n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, + n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, + n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, + n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, + n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, + n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, + n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, + n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, + n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, + n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, + n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, + n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, + n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, + n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, + n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, + n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, + n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, + n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, + n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, + n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, + n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, + n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, + n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, + n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, + n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, + n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, + n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, + n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, + n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, + n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, + n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, + n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, + n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, + n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, + n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, + n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, + n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, + n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, + n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, + n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, + n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, + n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, + n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, + n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, + n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, + n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, + n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, + n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, + n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, + n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, + n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, + n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, + n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, + n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, + n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, + n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, + n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, + n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, + n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, + n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, + n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, + n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, + n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, + n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, + n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, + n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, + n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, + n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, + n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, + n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, + n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, + n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, + n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, + n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, + n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, + n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, + n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, + n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, + n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, + n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, + n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, + n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, + n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, + n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, + n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, + n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, + n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, + n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, + n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, + n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, + n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, + n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, + n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, + n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, + n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, + n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, + n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, + n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, + n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, + n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, + n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, + n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, + n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, + n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, + n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, + n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, + n2376, n2377, n2378, n2379, n2380, n2381; + assign o_0_ = ~n126 & (n124 | n161); + assign o_1_ = ~n126 & (n160 | ~n1042 | ~n1612); + assign o_2_ = ~n126 & (n158 | n159 | ~n714); + assign o_3_ = ~n126 & (~n2261 | ~n2266); + assign o_4_ = ~n126 & (~n2241 | ~n2250 | ~n2252); + assign o_5_ = ~n2380; + assign o_6_ = ~n157; + assign o_7_ = ~n126 & (n156 | ~n1365 | ~n1370); + assign o_8_ = ~n2379; + assign o_9_ = ~n126 & (n155 | ~n1984 | ~n1986); + assign o_10_ = ~n154; + assign o_11_ = ~n995; + assign o_12_ = ~n1187; + assign o_13_ = ~n1174; + assign o_14_ = ~n1353; + assign o_15_ = ~n152; + assign o_16_ = ~n126 & (~n2359 | ~n2361 | ~n2363); + assign o_17_ = ~n126 & (~n2347 | ~n2349 | ~n2351); + assign o_18_ = ~n126 & (~n2332 | ~n2334 | ~n2336); + assign o_19_ = ~n126 & (~n2318 | ~n2319 | ~n2320); + assign o_20_ = ~n126 & (~n2302 | ~n2304); + assign o_21_ = ~n151; + assign o_22_ = ~n927 | ~n1431 | n148 | n149; + assign o_23_ = ~n147; + assign o_24_ = ~n145; + assign o_25_ = ~n144; + assign o_26_ = ~n142; + assign o_27_ = n136 & ~n126 & n135; + assign o_28_ = ~n2378; + assign o_29_ = ~n126 & (~n866 | ~n2284 | ~n2285); + assign o_30_ = ~n134; + assign o_31_ = n132 | n130 | n131; + assign o_32_ = ~n129; + assign o_33_ = ~n2377; + assign o_34_ = ~n126 & (~n2280 | ~n2282); + assign o_35_ = ~n126 & (~n1622 | ~n1625 | ~n2278); + assign o_36_ = ~n128; + assign o_37_ = ~n126 & (n123 | n124 | n125); + assign o_38_ = n121 & ~n1251; + assign o_39_ = n121 & n122; + assign n96 = n1239 & n1264; + assign n97 = n1239 & n177; + assign n98 = n1228 & n1239; + assign n99 = ~n361 | ~n1373; + assign n100 = n98 & (n99 | ~n617); + assign n101 = n96 & (~n564 | ~n926); + assign n102 = ~n617 | ~n1176; + assign n103 = n96 & (n102 | ~n361); + assign n104 = n1252 & n1256; + assign n105 = ~n597 | ~n1377; + assign n106 = n104 & (n105 | ~n500); + assign n107 = n1256 & n1264; + assign n108 = n107 & (~n336 | ~n1334); + assign n109 = ~n305 | ~n653; + assign n110 = n107 & (n109 | ~n685); + assign n111 = n107 & (~n426 | ~n1378); + assign n112 = n107 & (~n777 | ~n1795); + assign n113 = ~n1214 & n1256; + assign n114 = n113 & (~n1330 | ~n1418); + assign n115 = n113 & (~n774 | ~n1795); + assign n116 = n1228 & n1231; + assign n117 = n116 & (~n653 | ~n1378); + assign n118 = n113 & (~n266 | ~n1175); + assign n119 = ~n226 | ~n845; + assign n120 = n116 & (n119 | ~n472); + assign n121 = n172 & (n173 | n174); + assign n122 = i_6_ & ~i_7_; + assign n123 = n178 & n1228; + assign n124 = ~n1365 | ~n1370 | n159 | ~n714; + assign n125 = n2267 | n1647 | n717; + assign n126 = ~n1988 | ~n1989 | n184 | n185 | ~n157 | n175 | n180 | n182; + assign n127 = ~n2277 & n1618 & n1617 & n923 & n748 & n817; + assign n128 = n126 | n127; + assign n129 = n895 & n896 & (~n136 | ~n1237); + assign n130 = ~n481 & (n897 | n898); + assign n131 = n899 & (n900 | n901); + assign n132 = n1646 | n1647; + assign n133 = n1990 & n1648 & n1365 & n904 & n895 & n863 & ~n159 & n460; + assign n134 = n126 | n133; + assign n135 = ~i_2_ & i_0_ & i_1_; + assign n136 = i_6_ & i_7_; + assign n137 = n907 | n777; + assign n138 = n916 & n917 & (n918 | n911); + assign n139 = n1654 & n1653 & n1652 & n1651 & ~n915 & n1650; + assign n140 = n1658 & n1657 & n1656 & n1655 & ~n913 & n914; + assign n141 = n1661 & n1660 & n1659 & n912 & ~n171 & n909; + assign n142 = n141 & n140 & n139 & n137 & n138; + assign n143 = n2288 & n919 & n1617 & n815 & n740 & n1457 & n747 & n746; + assign n144 = n126 | n143; + assign n145 = n923 & (~n161 | n924); + assign n146 = n748 & n817 & n727 & n889 & n1622 & n862; + assign n147 = n126 | n146; + assign n148 = n929 & (~n984 | ~n1141); + assign n149 = n928 & (~n677 | ~n1663); + assign n150 = n978 & n977 & n976 & n938 & n975 & n974 & n972 & n973; + assign n151 = n126 | n150; + assign n152 = n187 & (~i_0_ | i_1_ | i_2_); + assign n153 = n1859 & n927 & n1644 & n769 & n1537 & n1617 & n1618; + assign n154 = n126 | n153; + assign n155 = ~n1973 | ~n1977 | ~n358 | n1972 | n347 | n350 | n352 | n355; + assign n156 = n1213 & ~n1214; + assign n157 = (~i_3_ | n186) & (n187 | n188); + assign n158 = n1213 & n176; + assign n159 = n1215 & ~n1353; + assign n160 = ~n481 & ~n1235; + assign n161 = n158 | n156; + assign n162 = n98 & (~n362 | ~n495); + assign n163 = n1239 & n1252; + assign n164 = n163 & (~n216 | ~n316); + assign n165 = ~n1233 & n1253; + assign n166 = n165 & (~n654 | ~n1012); + assign n167 = n176 & n1231; + assign n168 = n167 & (~n1176 | ~n1373); + assign n169 = n107 & (~n329 | ~n1416); + assign n170 = n167 & (~n709 | ~n1335); + assign n171 = ~n907 & (~n879 | ~n979); + assign n172 = ~i_2_ & ~i_0_ & i_1_; + assign n173 = i_3_ & i_5_ & i_4_; + assign n174 = ~i_5_ & i_3_ & i_4_; + assign n175 = ~n2381 & (n156 | n158); + assign n176 = n122 & i_8_; + assign n177 = i_8_ & n136; + assign n178 = n172 & n1215; + assign n179 = n172 & n1216; + assign n180 = (n176 | n177) & (n178 | n179); + assign n181 = n1228 & n179; + assign n182 = (~n1227 | ~n1987) & (n123 | n181); + assign n183 = n1216 | ~n1229 | i_3_ | ~n1212; + assign n184 = n135 & n183; + assign n185 = ~n1235 & (~n1227 | (i_12_ & ~n943)); + assign n186 = i_0_ | i_1_ | i_2_; + assign n187 = i_0_ | ~i_2_; + assign n188 = i_1_ | ~i_3_; + assign n189 = ~n98 | n316; + assign n190 = n1240 | n1245; + assign n191 = n1240 | n1243; + assign n192 = n189 & (~n98 | (n190 & n191)); + assign n193 = ~n98 | n317; + assign n194 = ~n98 | n287; + assign n195 = n1245 | n1260; + assign n196 = n193 & n194 & (~n98 | n195); + assign n197 = ~n98 | n979; + assign n198 = n264 & n1207; + assign n199 = n197 & (~n98 | n198); + assign n200 = ~n98 | n1105; + assign n201 = n329 & n444; + assign n202 = n200 & (~n98 | n201); + assign n203 = ~n98 | n1262; + assign n204 = n1238 | n1245; + assign n205 = n203 & (~n98 | n204); + assign n206 = n1198 | n1263; + assign n207 = n205 & (~n98 | n206); + assign n208 = ~n98 | n527; + assign n209 = n330 & n442; + assign n210 = n208 & (~n98 | n209); + assign n211 = ~n97 | n284; + assign n212 = n313 & n226; + assign n213 = n211 & (~n97 | n212); + assign n214 = ~n97 | n191; + assign n215 = n214 & (~n97 | n190); + assign n216 = n1198 | n1206; + assign n217 = n215 & (~n97 | n216); + assign n218 = ~n97 | n287; + assign n219 = n195 & n356; + assign n220 = n218 & (~n97 | n219); + assign n221 = ~n97 | n1105; + assign n222 = n221 & (~n97 | n201); + assign n223 = ~n97 | n527; + assign n224 = n223 & (~n97 | n209); + assign n225 = ~n167 | n444; + assign n226 = n1198 | n1201; + assign n227 = n1217 | n1220; + assign n228 = n225 & (~n167 | (n226 & n227)); + assign n229 = n113 & (~n331 | ~n334); + assign n230 = n107 & (~n474 | ~n1207); + assign n231 = ~n96 | n216; + assign n232 = ~n96 | n251; + assign n233 = ~n96 | n316; + assign n234 = ~n96 | n1157; + assign n235 = ~n96 | n1248; + assign n236 = n834 & n1475 & n1928 & n1546 & n860 & n827; + assign n237 = n1930 & n1932 & n1681 & n933 & n934 & n1715 & n955 & n1931; + assign n238 = n1941 & n1943 & n1944 & n1948 & n1947 & n1838 & n1945 & n1946; + assign n239 = n238 & n237 & n236 & n235 & n234 & n233 & n231 & n232; + assign n240 = ~n96 | n1247; + assign n241 = ~n96 | n204; + assign n242 = ~n96 | n195; + assign n243 = ~n278 | n617; + assign n244 = ~n96 | n264; + assign n245 = n1927 & (~n278 | (n204 & n306)); + assign n246 = ~n268 | n2036; + assign n247 = (~n107 | n195) & (n263 | n907); + assign n248 = n247 & n246 & n245 & n244 & n243 & n242 & n240 & n241; + assign n249 = ~n167 | n316; + assign n250 = ~n96 | n317; + assign n251 = n1220 | n1238; + assign n252 = n249 & n250 & (~n107 | n251); + assign n253 = n278 | n107; + assign n254 = ~n755 & (n97 | n253); + assign n255 = ~n96 | n331; + assign n256 = ~n113 | n1250; + assign n257 = (~n107 | n1295) & (~n633 | n1866); + assign n258 = (~n96 | n190) & (~n97 | n749); + assign n259 = (~n167 | ~n268) & (n924 | n1968); + assign n260 = n252 & n248 & n239 & n1282 & n1286 & n1054 & n217 & n220; + assign n261 = n1962 & n1964 & n1967 & n1966 & n1965 & n1800 & n1842 & n1818; + assign n262 = n261 & n260 & n259 & n258 & n257 & n256 & ~n254 & n255; + assign n263 = n195 & n305; + assign n264 = n1219 | n1245; + assign n265 = ~i_15_ | n1218; + assign n266 = n1197 | n1204; + assign n267 = n266 & n265 & n263 & n264; + assign n268 = ~n190 | ~n617; + assign n269 = ~n327 & (~n263 | n268); + assign n270 = ~n167 | n604; + assign n271 = ~n167 | n204; + assign n272 = n1923 & (n1924 | n313); + assign n273 = (~n107 | n597) & (~n167 | n330); + assign n274 = n1926 & (~n348 | n604); + assign n275 = n1712 & n1502 & n1706 & n1750 & n1674 & n1680; + assign n276 = n1594 & n1860 & n1548 & n1602 & n1568 & n1573; + assign n277 = n276 & n275 & n274 & n273 & n272 & n271 & ~n269 & n270; + assign n278 = ~n1214 & n1253; + assign n279 = n278 & (~n284 | ~n287); + assign n280 = n191 | ~n353; + assign n281 = n116 & (~n287 | ~n979); + assign n282 = n1105 & n309; + assign n283 = ~n104 | n282; + assign n284 = n1217 | n1243; + assign n285 = ~n104 & ~n116; + assign n286 = n284 | n285; + assign n287 = n1243 | n1260; + assign n288 = n1204 | n1238; + assign n289 = n191 & n536 & n926; + assign n290 = n289 & n287 & n288; + assign n291 = ~n571 & n1292; + assign n292 = ~n381 & n1291; + assign n293 = n292 & n291 & ~n113 & ~n163; + assign n294 = n113 | n571; + assign n295 = n165 | n107; + assign n296 = ~n674 & (n167 | n294 | n295); + assign n297 = n1300 & n1299 & n1298 & n1297 & n1296 & n286 & ~n281 & n283; + assign n298 = n563 & n561 & n497; + assign n299 = (~n107 | n508) & (~n278 | n288); + assign n300 = (n292 | n879) & (~n96 | n926); + assign n301 = (n290 | ~n404) & (~n253 | n1293); + assign n302 = n1910 & n1909 & n1400 & n1398 & n1396 & n559 & ~n296 & n483; + assign n303 = n302 & n301 & n300 & n299 & n297 & n298; + assign n304 = n610 & n604; + assign n305 = n1204 | n1265; + assign n306 = n1204 | n1263; + assign n307 = n266 & n306 & n304 & n305; + assign n308 = n1207 & n226; + assign n309 = n1241 | n1243; + assign n310 = n206 & n284 & n308 & n309; + assign n311 = ~n98 | n227; + assign n312 = ~n98 | n284; + assign n313 = n1217 | n1245; + assign n314 = n311 & n312 & (~n98 | n313); + assign n315 = n314 & (~n98 | n226); + assign n316 = n1220 | n1240; + assign n317 = n1220 | n1260; + assign n318 = n317 & n316 & n216; + assign n319 = n316 & n474; + assign n320 = ~n165 | n319; + assign n321 = n571 | n104; + assign n322 = n321 & (~n227 | ~n822 | ~n1157); + assign n323 = ~n165 & ~n571; + assign n324 = n317 | n323; + assign n325 = n1308 & n1307 & n1306 & n1305 & n1304 & n1303 & n1301 & n1302; + assign n326 = n487 & n494 & (n318 | ~n404); + assign n327 = ~n294 & n1290; + assign n328 = n325 & n326 & (n327 | n251); + assign n329 = n1245 | n1249; + assign n330 = n1245 | n1255; + assign n331 = n1198 | n1255; + assign n332 = n331 & n329 & n330; + assign n333 = n1250 & n334; + assign n334 = n1198 | n1217; + assign n335 = (n291 | n333) & (~n98 | n334); + assign n336 = n1247 & n1248; + assign n337 = n336 & n316 & n204; + assign n338 = n343 | n354; + assign n339 = n338 & (~n755 | ~n924); + assign n340 = n165 | ~n291; + assign n341 = n340 & (~n921 | ~n1262); + assign n342 = n294 & (~n287 | ~n474); + assign n343 = n404 | n163; + assign n344 = ~n327 | n348; + assign n345 = ~n774 & (n343 | n344); + assign n346 = n404 | n165; + assign n347 = ~n1250 & (n96 | n346); + assign n348 = n98 | n97; + assign n349 = n113 | ~n291; + assign n350 = ~n265 & (n348 | n349); + assign n351 = n359 | n381 | n344; + assign n352 = ~n597 & (n278 | n351); + assign n353 = n1231 & n177; + assign n354 = n98 | ~n327; + assign n355 = ~n216 & (n353 | n354); + assign n356 = n1198 | n1265; + assign n357 = ~n98 & n1309; + assign n358 = n356 | n357; + assign n359 = n163 | n96; + assign n360 = n359 & (~n265 | ~n604 | ~n1311); + assign n361 = n1206 | n1221; + assign n362 = n1197 | n1245; + assign n363 = n361 & n362; + assign n364 = ~n97 | n495; + assign n365 = ~n97 | n566; + assign n366 = ~n96 | n447; + assign n367 = ~n96 | n426; + assign n368 = ~n96 | n688; + assign n369 = n1604 & n1701 & n2075 & n2076; + assign n370 = n2081 & n947 & n1719 & n2080 & n2079 & n998 & n2077 & n2078; + assign n371 = n2085 & n2086 & n1089 & n1846 & n1016 & n1007 & n1864 & n2087; + assign n372 = n371 & n370 & n369 & n368 & n367 & n366 & n364 & n365; + assign n373 = (~n116 | n1138) & (~n404 | n447); + assign n374 = n2109 & (n361 | ~n381); + assign n375 = n2108 & (~n165 | (n426 & n1331)); + assign n376 = n1131 & n1132 & n1078 & n2107; + assign n377 = n2103 & n2106 & n916 & n1810 & n1785 & n1822 & n2104 & n2105; + assign n378 = n2097 & n1709 & n2101 & n2100 & n2099 & n1697 & n2098 & n1687; + assign n379 = n2091 & n1484 & n2094 & n1525 & n2093 & n1574 & n2092 & n1565; + assign n380 = n379 & n378 & n377 & n376 & n375 & n374 & n373 & n372; + assign n381 = n404 | n167; + assign n382 = n163 | n107; + assign n383 = ~n845 & (n381 | n382); + assign n384 = ~n167 | n1331; + assign n385 = ~n167 | n688; + assign n386 = ~n278 | n1331; + assign n387 = ~n96 | n845; + assign n388 = n2110 & (~n107 | (n426 & n688)); + assign n389 = (~n163 | n361) & (~n167 | n426); + assign n390 = n2111 & (~n348 | n1331); + assign n391 = n390 & n380 & n389 & n388 & n387 & n386 & n384 & n385; + assign n392 = i_15_ | n1332; + assign n393 = n1243 | n1257; + assign n394 = n392 & n393; + assign n395 = ~n104 | n441; + assign n396 = ~n104 | n393; + assign n397 = (n394 | n911) & (~n253 | n1336); + assign n398 = n1340 & n2071 & (~n116 | n441); + assign n399 = n2069 & n1000 & n1805 & n1746 & n1747 & n2070; + assign n400 = n2061 & n2065 & n1776 & n1786 & n1819 & n2066 & n1752 & n1830; + assign n401 = n2049 & n2051 & n2054 & n2053 & n1694 & n2052 & n1710 & n1685; + assign n402 = n2043 & n2037 & n770 & n2045 & n2044 & n733 & n1510 & n722; + assign n403 = n402 & n401 & n400 & n399 & n398 & n397 & n395 & n396; + assign n404 = n1231 & ~n1232; + assign n405 = n404 & (~n430 | ~n529 | ~n709); + assign n406 = ~n167 | n1334; + assign n407 = ~n278 | n393; + assign n408 = ~n96 | n441; + assign n409 = n2073 & (~n278 | n429); + assign n410 = (~n107 | n1334) & (~n167 | n471); + assign n411 = n2074 & (~n348 | n393); + assign n412 = n411 & n410 & n409 & n408 & n407 & n406 & n403 & ~n405; + assign n413 = ~n107 | n1224; + assign n414 = ~n113 | n1152; + assign n415 = ~n113 | n1151; + assign n416 = ~n107 | n1341; + assign n417 = n990 & (n2036 | n1145); + assign n418 = n1345 & n1344 & n1342 & n1343; + assign n419 = n958 & n2035 & n1439 & n2034 & n2033 & n2032 & n2030 & n2031; + assign n420 = n2028 & n2029 & n1419 & n1725 & n1471 & n1499 & n1729 & n782; + assign n421 = n420 & n419 & n418 & n417 & n416 & n415 & n413 & n414; + assign n422 = ~n96 | n1330; + assign n423 = n1335 & n1330; + assign n424 = n421 & n422 & (~n107 | n423); + assign n425 = ~n97 | n471; + assign n426 = n1245 | n1265; + assign n427 = n425 & (~n97 | n426); + assign n428 = n427 & (~n97 | n356); + assign n429 = n709 & n473; + assign n430 = n1221 | n1240; + assign n431 = n429 & n430; + assign n432 = ~n107 | n471; + assign n433 = ~n107 | n1337; + assign n434 = ~n107 | n472; + assign n435 = (~n107 | n431) & (n907 | n908); + assign n436 = ~n278 | n441; + assign n437 = n2002 & n2001 & n2000 & n1999 & n1998 & n1997 & n989; + assign n438 = n1993 & n1996 & n1995 & n1714 & n1600 & n1605 & n1994 & n1554; + assign n439 = n438 & n437 & n436 & n435 & n434 & n433 & ~n170 & n432; + assign n440 = n1220 | n1246; + assign n441 = i_15_ | n1225; + assign n442 = n1198 | n1258; + assign n443 = n1224 & n1082; + assign n444 = n1198 | n1257; + assign n445 = n444 & n443 & n442 & n206 & n441 & n356 & n308 & n440; + assign n446 = ~n98 | n473; + assign n447 = n1245 | n1263; + assign n448 = n446 & (~n98 | n447); + assign n449 = (n119 | ~n206) & (n97 | n98); + assign n450 = ~n216 | ~n564; + assign n451 = ~n327 & (n450 | ~n1347); + assign n452 = ~n361 & (n96 | n354); + assign n453 = n163 | ~n292; + assign n454 = ~n1224 & (n104 | n453); + assign n455 = ~n291 & (~n316 | ~n685 | ~n1348); + assign n456 = ~n1145 & (~n327 | n359 | n381); + assign n457 = ~n1152 & (~n292 | n340 | n359); + assign n458 = n1230 | n1251; + assign n459 = n1230 | n1233; + assign n460 = n458 & (n459 | ~n819); + assign n461 = n1990 & n1624 & n1620; + assign n462 = n444 & n508; + assign n463 = n460 & n461 & (n462 | n459); + assign n464 = n442 & n469; + assign n465 = ~n450 & n464; + assign n466 = (~n97 | n465) & (~n98 | n464); + assign n467 = n393 & n1331; + assign n468 = n426 & n845; + assign n469 = n707 & n656; + assign n470 = n709 & n362; + assign n471 = n1243 | n1265; + assign n472 = n1201 | n1243; + assign n473 = n1243 | n1263; + assign n474 = n1219 | n1220; + assign n475 = n474 & n473 & n472 & n471 & n470 & n469 & n467 & n468; + assign n476 = ~n362 & (n278 | n381); + assign n477 = n1363 & n1362 & n1361 & n1360 & n766 & n239 & n439 & n428; + assign n478 = n2117 & n1359 & n328 & n252; + assign n479 = n2115 & n2113 & n1041 & n2114 & n2112 & n839 & n1385 & n869; + assign n480 = n479 & n478 & n477 & n466 & n463 & n391 & n412 & n424; + assign n481 = i_10_ | i_9_; + assign n482 = n481 | ~n897; + assign n483 = ~n98 | n508; + assign n484 = n483 & (~n98 | n467); + assign n485 = ~n96 | n227; + assign n486 = n485 & (~n99 | ~n163); + assign n487 = ~n163 | n227; + assign n488 = ~n96 | n1372; + assign n489 = n1221 | n1246; + assign n490 = n487 & n488 & (~n96 | n489); + assign n491 = ~n163 | n1372; + assign n492 = n250 & n491 & (~n163 | n489); + assign n493 = ~n96 | n1125; + assign n494 = ~n163 | n474; + assign n495 = ~i_15_ | n1223; + assign n496 = n493 & n494 & (~n96 | n495); + assign n497 = ~n98 | n1293; + assign n498 = n497 & (~n98 | n469); + assign n499 = n1258 | n1371; + assign n500 = n1221 | n1258; + assign n501 = n499 & n500; + assign n502 = (n501 | ~n571) & (~n113 | n251); + assign n503 = ~n96 | n288; + assign n504 = n1238 | n1376; + assign n505 = n422 & n503 & (~n96 | n504); + assign n506 = n879 | n675; + assign n507 = ~n107 | n499; + assign n508 = n1204 | n1249; + assign n509 = n1233 | ~n1239; + assign n510 = n506 & n507 & (n508 | n509); + assign n511 = ~n163 | n1375; + assign n512 = ~n163 | n530; + assign n513 = ~n98 | n1374; + assign n514 = ~n98 | n951; + assign n515 = n2185 & (~n929 | n984); + assign n516 = n875 | n509; + assign n517 = n516 & n515 & n514 & n513 & n511 & n512; + assign n518 = n682 & n504; + assign n519 = n1377 & n653; + assign n520 = n979 & n1262; + assign n521 = n1240 | n1371; + assign n522 = n1238 | n1371; + assign n523 = n1249 | n1376; + assign n524 = n523 & n522 & n521 & n520 & n518 & n519; + assign n525 = n430 & n926 & n1176; + assign n526 = n1217 | n1376; + assign n527 = n1243 | n1255; + assign n528 = n1241 | n1376; + assign n529 = n1221 | n1241; + assign n530 = n1241 | n1371; + assign n531 = n530 & n529 & n528 & n527 & n526 & n284 & n282 & n525; + assign n532 = n107 & (~n1175 | ~n1381 | ~n2184); + assign n533 = n528 & n1380; + assign n534 = ~n532 & (~n104 | (n525 & n533)); + assign n535 = ~n278 | n529; + assign n536 = n1204 | n1241; + assign n537 = n535 & (~n278 | n536); + assign n538 = ~n278 | n528; + assign n539 = ~n453 & n1349; + assign n540 = n1260 | n1371; + assign n541 = n538 & n537 & (n539 | n540); + assign n542 = n107 & (~n523 | ~n530 | ~n1382); + assign n543 = (~n98 | n592) & (n567 | ~n929); + assign n544 = (~n96 | n682) & (~n404 | n522); + assign n545 = n2203 & n2204 & (~n346 | n1375); + assign n546 = n944 & n765 & n541 & n534 & n517 & n510 & n1387 & n505; + assign n547 = n2198 & n2199 & n2200 & n2201 & n2197 & n2195 & n2202 & n1283; + assign n548 = n2191 & n2187 & n2188 & n200 & n2192 & n197 & n221 & n218; + assign n549 = n548 & n547 & n546 & n545 & n543 & n544; + assign n550 = n1395 & n1394 & n1393 & n1392 & n1391 & n1090 & n1389 & n1390; + assign n551 = n1321 & n1320 & n1319 & n1318 & n1317 & n280 & ~n171 & ~n279; + assign n552 = n2183 & (n1196 | ~n1388); + assign n553 = (~n113 | n1374) & (n521 | n2036); + assign n554 = n1843 & n2182 & (~n107 | n520); + assign n555 = n2178 & n2181 & n1761 & n1061 & n1836 & n2180 & n1095 & n2179; + assign n556 = n2172 & n1652 & n1659 & n2174 & n959 & n1682 & n2173 & n1728; + assign n557 = n2171 & n1428 & n1453 & n1479 & n1468 & n1464 & n1534 & n1448; + assign n558 = n557 & n556 & n555 & n554 & n553 & n552 & n550 & n551; + assign n559 = ~n97 | n508; + assign n560 = n559 & (~n97 | n467); + assign n561 = ~n97 | n1293; + assign n562 = n561 & (~n97 | n469); + assign n563 = ~n97 | n926; + assign n564 = n1337 & n1333; + assign n565 = n563 & (~n97 | n564); + assign n566 = ~i_15_ | n1332; + assign n567 = n1257 | n1371; + assign n568 = n566 & n567; + assign n569 = (n568 | ~n571) & (~n113 | n474); + assign n570 = ~n879 & (n116 | n165 | n381); + assign n571 = ~n1233 & n1256; + assign n572 = ~n1028 & (n346 | n571); + assign n573 = (~n116 | n984) & (~n165 | n528); + assign n574 = n1403 & n848 & n851 & n1402; + assign n575 = (~n321 | n592) & (~n404 | n504); + assign n576 = (n323 | n1125) & (~n253 | n1377); + assign n577 = n2138 & n2137 & n2136 & n1743 & n1130 & ~n572 & n1079; + assign n578 = n2134 & n1650 & n1852 & n1654 & n2135 & n1809 & n1824 & n1751; + assign n579 = n2128 & n1741 & n1119 & n1733 & n2129 & n1688 & n1707 & n1708; + assign n580 = n2121 & n2124 & n1542 & n1527 & n725 & n723 & n2122 & n2123; + assign n581 = n580 & n579 & n578 & n577 & n576 & n575 & n573 & n574; + assign n582 = ~n291 & (~n729 | ~n1405); + assign n583 = n381 & (~n316 | ~n1377 | ~n1406); + assign n584 = (n287 | ~n294) & (~n348 | n442); + assign n585 = n2211 & (~n404 | n1756); + assign n586 = n2208 & n2209 & (~n113 | n2210); + assign n587 = n2206 & n2207 & n1071 & n1531 & n1691 & n1834 & n1792 & n1816; + assign n588 = n2214 & n486 & n484 & n502 & n498 & n549 & n558 & n1414; + assign n589 = n2213 & n581 & n1411 & n477 & n421 & n403; + assign n590 = n589 & n588 & n587 & n586 & n584 & n585; + assign n591 = ~n98 | n685; + assign n592 = n1265 | n1371; + assign n593 = n591 & (~n98 | n592); + assign n594 = n593 & (~n98 | n305); + assign n595 = ~n96 | n1377; + assign n596 = ~n96 | n500; + assign n597 = n1204 | n1258; + assign n598 = n595 & n596 & (~n96 | n597); + assign n599 = ~n163 | n1377; + assign n600 = ~n163 | n500; + assign n601 = n599 & n600 & (~n163 | n597); + assign n602 = ~n96 | n523; + assign n603 = ~n96 | n566; + assign n604 = n1204 | n1257; + assign n605 = n602 & n603 & (~n96 | n604); + assign n606 = ~n163 | n523; + assign n607 = ~n163 | n566; + assign n608 = n606 & n607 & (~n163 | n604); + assign n609 = ~n167 | n528; + assign n610 = n1204 | n1246; + assign n611 = n609 & (~n167 | n610); + assign n612 = (~n167 | n1377) & (~n571 | n1141); + assign n613 = n2227 & (~n343 | n652); + assign n614 = n613 & n612 & n581; + assign n615 = ~n97 | n361; + assign n616 = ~n97 | n1373; + assign n617 = n1204 | n1206; + assign n618 = n615 & n616 & (~n97 | n617); + assign n619 = ~n97 | n685; + assign n620 = ~n97 | n592; + assign n621 = n619 & n620 & (~n97 | n305); + assign n622 = ~n96 | n526; + assign n623 = ~n96 | n1138; + assign n624 = n622 & n623 & (~n96 | n265); + assign n625 = ~n96 | n653; + assign n626 = n625 & (~n96 | n305); + assign n627 = ~n113 | n777; + assign n628 = n137 & n1461 & n1452; + assign n629 = n489 & n1415; + assign n630 = n627 & n628 & (~n107 | n629); + assign n631 = n798 & n654 & n752; + assign n632 = n631 & n264 & n204; + assign n633 = n96 | n107; + assign n634 = ~n738 & (n633 | ~n907); + assign n635 = ~n96 | n2372; + assign n636 = ~n96 | n629; + assign n637 = ~n278 | n654; + assign n638 = n1209 | ~n1388; + assign n639 = ~n278 | n777; + assign n640 = n2220 & n2219 & n2217 & n2218; + assign n641 = n2216 & n2215 & n1519 & n1513 & n1497 & n1478 & ~n103 & n1467; + assign n642 = n2225 & n2226 & n630 & n1420 & n1422 & n624 & n618 & n621; + assign n643 = n642 & n641 & n640 & n639 & n638 & n637 & n635 & n636; + assign n644 = ~n98 | n1138; + assign n645 = ~n98 | n984; + assign n646 = n644 & n645 & (~n98 | n265); + assign n647 = ~n404 | n500; + assign n648 = n647 & (~n105 | ~n404); + assign n649 = n500 & n566; + assign n650 = ~n571 | n649; + assign n651 = n1258 | n1376; + assign n652 = n1176 & n1373; + assign n653 = n1260 | n1376; + assign n654 = n1257 | n1376; + assign n655 = n361 & n654 & n653 & n652 & n518 & n651; + assign n656 = n1245 | n1258; + assign n657 = n1415 & ~n1114 & n1331; + assign n658 = n526 & n265; + assign n659 = n658 & n657 & n656 & ~n105 & n362; + assign n660 = n313 & n656 & n447 & n468 & n195 & n190; + assign n661 = ~n98 | n684; + assign n662 = ~n98 | n1028; + assign n663 = n661 & n662 & (~n98 | n306); + assign n664 = n597 & n610 & n306 & n265; + assign n665 = ~n97 | n684; + assign n666 = ~n97 | n1028; + assign n667 = ~n97 | n984; + assign n668 = n2027 & (~n97 | n664); + assign n669 = n1427 & n1428; + assign n670 = n1426 & n1425 & n1423 & n1424; + assign n671 = ~n98 | n597; + assign n672 = n671 & n670 & n669 & n663 & n668 & n667 & n665 & n666; + assign n673 = n288 | n675; + assign n674 = n1204 | n1260; + assign n675 = n1214 | ~n1239; + assign n676 = n673 & (n674 | n675); + assign n677 = n592 & n1028; + assign n678 = n507 & n676 & (n677 | ~n928); + assign n679 = ~n738 & (n344 | n453); + assign n680 = ~n359 & n911; + assign n681 = n680 & ~n346 & ~n98 & n291; + assign n682 = n1219 | n1376; + assign n683 = n488 & n493 & (~n167 | n682); + assign n684 = n1221 | n1263; + assign n685 = n1221 | n1265; + assign n686 = n684 & n685; + assign n687 = n329 & n204 & n1247; + assign n688 = n1245 | n1246; + assign n689 = n330 & n688 & n687 & n264; + assign n690 = n359 & (~n190 | ~n1429); + assign n691 = n165 & (~n523 | ~n1377); + assign n692 = n107 & (~n500 | ~n1247); + assign n693 = ~n292 & (~n362 | ~n752 | ~n1382); + assign n694 = (~n96 | n521) & (~n253 | n910); + assign n695 = n2253 & (~n278 | n1378); + assign n696 = n425 & n1005 & (~n113 | n1086); + assign n697 = n696 & n695 & n439 & n694 & n683 & n558; + assign n698 = n227 | n1234; + assign n699 = n822 | n1234; + assign n700 = n474 | n1234; + assign n701 = n879 | n1234; + assign n702 = n875 | n1234; + assign n703 = n1207 | n1234; + assign n704 = n226 | n1234; + assign n705 = n1645 & (n462 | n1234); + assign n706 = n705 & n704 & n703 & n702 & n701 & n700 & n698 & n699; + assign n707 = n1243 | n1258; + assign n708 = n441 & n393 & n473 & n707 & n536; + assign n709 = n1197 | n1243; + assign n710 = n472 & n709; + assign n711 = n227 | n713; + assign n712 = ~n136 | ~n1213; + assign n713 = ~n1213 | n1232; + assign n714 = n711 & n712 & (n713 | ~n716); + assign n715 = n178 & ~n1232; + assign n716 = n819 | ~n481 | ~n757; + assign n717 = n715 & (~n227 | n716); + assign n718 = ~n98 | n1341; + assign n719 = n2192 & n1276 & n1344; + assign n720 = n755 & n793; + assign n721 = n718 & n719 & (~n98 | n720); + assign n722 = ~n98 | n392; + assign n723 = ~n98 | n523; + assign n724 = ~n98 | n566; + assign n725 = ~n98 | n567; + assign n726 = n202 & (~n98 | n604); + assign n727 = n484 & n726 & n725 & n724 & n722 & n723; + assign n728 = ~n98 | n536; + assign n729 = n1334 & n688; + assign n730 = n728 & (~n98 | n729); + assign n731 = ~n97 | n879; + assign n732 = n731 & (~n97 | n470); + assign n733 = ~n97 | n1335; + assign n734 = ~n97 | n682; + assign n735 = n733 & n734 & (~n97 | n266); + assign n736 = ~n98 | n266; + assign n737 = ~n98 | n334; + assign n738 = n1265 | n1376; + assign n739 = n1198 | n1260; + assign n740 = (~n98 | n739) & (~n348 | n738); + assign n741 = ~n97 | n530; + assign n742 = ~n98 | n1797; + assign n743 = ~n97 | n440; + assign n744 = n740 & (~n97 | n774); + assign n745 = n1457 & n732; + assign n746 = n1466 & n1465 & n1464 & n1462 & n1463; + assign n747 = n737 & n1461 & n1460 & n1459 & n1458 & n1434 & n513; + assign n748 = n747 & n746 & n745 & n730 & n744 & n743 & n741 & n742; + assign n749 = n1198 | n1219; + assign n750 = ~n348 | n749; + assign n751 = n750 & n1435 & n1471 & n1470 & n1469 & n1467 & n1468; + assign n752 = n1197 | n1376; + assign n753 = n751 & (~n98 | n752); + assign n754 = ~n98 | n651; + assign n755 = n1198 | n1238; + assign n756 = n514 & n754 & (~n97 | n755); + assign n757 = n1446 & n822 & n462; + assign n758 = n757 | ~n1473; + assign n759 = n1151 & n1250; + assign n760 = (~n96 | n759) & (~n163 | n752); + assign n761 = n309 & n1247; + assign n762 = n1262 & n204; + assign n763 = n330 & n313 & n761 & n762; + assign n764 = n1477 & n1476 & n1474 & n1475; + assign n765 = n1383 & n208 & n872 & n869 & n223 & n870; + assign n766 = n1352 & n1351 & ~n449 & n1350; + assign n767 = n1340 & n314 & n298; + assign n768 = n2271 & n205 & n215 & n1928 & n834 & n1955 & n1626 & n852; + assign n769 = n768 & n767 & n766 & n466 & n765 & n574 & n764 & n672; + assign n770 = ~n97 | n392; + assign n771 = ~n97 | n523; + assign n772 = n770 & n771 & (~n97 | n604); + assign n773 = n98 & (~n610 | ~n777); + assign n774 = n1198 | n1241; + assign n775 = ~n98 | n774; + assign n776 = ~n96 | n530; + assign n777 = n1246 | n1376; + assign n778 = n776 & (~n96 | (n440 & n777)); + assign n779 = ~n163 | n440; + assign n780 = n779 & (~n163 | n777); + assign n781 = ~n359 | n739; + assign n782 = ~n96 | n1097; + assign n783 = ~n96 | n540; + assign n784 = (~n96 | n738) & (~n163 | n1097); + assign n785 = n780 & n784 & n783 & n782 & n781 & n512; + assign n786 = ~n163 | n1155; + assign n787 = ~n163 | n951; + assign n788 = n786 & n787 & (~n163 | n651); + assign n789 = n1417 & n924; + assign n790 = ~n98 | n789; + assign n791 = ~n96 | n1341; + assign n792 = ~n96 | n522; + assign n793 = n1263 | n1376; + assign n794 = n791 & n792 & (~n96 | n793); + assign n795 = n163 & (~n1224 | ~n1506); + assign n796 = n163 & (~n654 | ~n749 | ~n1507); + assign n797 = ~n96 | n749; + assign n798 = n1201 | n1376; + assign n799 = n798 & n738 & n540 & n313 & ~n102 & n191; + assign n800 = n359 & (~n190 | ~n1166); + assign n801 = n1505 & n255 & n1073; + assign n802 = n1532 & n1537 & n1526 & n1521 & n1518; + assign n803 = n2270 & n1951 & n1516 & n1436 & n1278 & n1195 & ~n103 & ~n164; + assign n804 = n2269 & n244 & n1915 & n1275 & n1959 & n1345 & n1313 & n1273; + assign n805 = n2268 & n2154 & n2089 & n2038 & n1991 & n1891 & ~n101 & n231; + assign n806 = n805 & n804 & n803 & n802 & n788 & n785 & n778 & n801; + assign n807 = n1553 & n1552 & n1551 & n1550 & n1549 & n1547 & n1548; + assign n808 = n1546 & n1545 & n366 & n232 & n241 & n1544; + assign n809 = n505 & (~n96 | n1867); + assign n810 = n1543 & n1542 & n1541 & n1540 & n1539 & n1538 & n1329 & n601; + assign n811 = n810 & n809 & n807 & n808; + assign n812 = n96 & (~n682 | ~n1415); + assign n813 = n163 & (~n305 | ~n774 | ~n1415); + assign n814 = n266 | ~n359; + assign n815 = n1611 & n1610 & n1609 & n1596 & n806 & n1588 & n1578 & n836; + assign n816 = i_7_ | i_6_; + assign n817 = n815 & (n816 | ~n1608); + assign n818 = n179 & ~n1232; + assign n819 = ~n879 | ~n1207; + assign n820 = n818 & (~n227 | ~n757 | n819); + assign n821 = n227 | ~n1619; + assign n822 = n1220 | n1249; + assign n823 = n822 | ~n1628; + assign n824 = n474 | ~n897; + assign n825 = n902 & ~n1473; + assign n826 = n700 & n824 & (n825 | n474); + assign n827 = ~n97 | n317; + assign n828 = n220 & (~n98 | n263); + assign n829 = n1563 & n1562 & n1560 & n1561; + assign n830 = n1559 & n1558 & n1557 & n621; + assign n831 = n427 & n593 & n830 & n829 & n828 & n827 & n193 & n194; + assign n832 = ~n97 | n536; + assign n833 = n832 & (~n97 | n729); + assign n834 = ~n97 | n1157; + assign n835 = ~n97 | n1797; + assign n836 = n1582 & n1581 & n1580 & n368 & n240 & n235 & n1579 & n234; + assign n837 = n1578 & n2228 & (~n163 | n774); + assign n838 = n837 & n836 & n833 & n835 & n636 & n491 & n488 & n834; + assign n839 = ~n97 | n529; + assign n840 = ~n97 | n528; + assign n841 = n839 & n840 & (~n97 | n610); + assign n842 = ~n96 | n1375; + assign n843 = n842 & (~n96 | n759); + assign n844 = n97 & (~n265 | ~n845); + assign n845 = n1201 | n1245; + assign n846 = ~n98 | n845; + assign n847 = ~n97 | n1336; + assign n848 = ~n97 | n1377; + assign n849 = n847 & n848 & (~n97 | n597); + assign n850 = ~n98 | n1336; + assign n851 = ~n98 | n1377; + assign n852 = ~n98 | n1261; + assign n853 = n210 & (~n98 | n597); + assign n854 = n562 & n498 & n670 & n849 & n853 & n852 & n850 & n851; + assign n855 = n1453 & n1451 & n1452; + assign n856 = n756 & n1472 & n1312; + assign n857 = n721 & n1450 & (~n98 | n752); + assign n858 = ~n97 | n2369; + assign n859 = n508 | ~n897; + assign n860 = ~n97 | n474; + assign n861 = n1858 & n1616 & (n888 | n508); + assign n862 = n861 & n860 & n859 & n858 & n857 & n856 & n751 & n855; + assign n863 = ~n136 | n1441; + assign n864 = ~n136 | n1364; + assign n865 = (~n136 | ~n159) & (n459 | n875); + assign n866 = n865 & n863 & n864; + assign n867 = ~n122 | n1364; + assign n868 = n867 & (~n122 | ~n159); + assign n869 = ~n97 | n1330; + assign n870 = ~n97 | n504; + assign n871 = n869 & n870 & (~n97 | n306); + assign n872 = ~n97 | n288; + assign n873 = n473 & n447; + assign n874 = n872 & (~n97 | n873); + assign n875 = i_15_ | n1218; + assign n876 = n875 | n825; + assign n877 = n163 & (~n266 | ~n305 | ~n752); + assign n878 = ~n481 & (n818 | ~n1234); + assign n879 = n1204 | n1219; + assign n880 = n459 & n902; + assign n881 = n879 | n880; + assign n882 = ~n159 | n1251; + assign n883 = n1251 | n1364; + assign n884 = n882 & n883 & (n226 | n459); + assign n885 = n816 | n1364; + assign n886 = n885 & (~n159 | n816); + assign n887 = n444 | ~n897; + assign n888 = n1235 & ~n1628; + assign n889 = n887 & (n888 | n444); + assign n890 = n1355 & n1442 & n2118; + assign n891 = n704 & n890 & (n825 | n226); + assign n892 = n703 & n1356 & n1444 & n1367 & n1613; + assign n893 = (n880 | n1207) & (n1235 | n481); + assign n894 = n893 & n891 & n889 & n884 & n892 & n886; + assign n895 = n1645 & n712 & n1368; + assign n896 = n458 & (~n1608 | (~n136 & n816)); + assign n897 = n1213 & ~n1233; + assign n898 = ~n713 | n715; + assign n899 = n2267 | n2276; + assign n900 = i_9_ & ~i_10_; + assign n901 = ~i_9_ & i_10_; + assign n902 = n713 & ~n1619; + assign n903 = ~n819 | n902; + assign n904 = n826 & n903 & n1641 & n892; + assign n905 = n868 & n2287 & (~n899 | ~n901); + assign n906 = n905 & n904 & ~n132 & n886; + assign n907 = ~n176 | ~n1239; + assign n908 = n709 & n1335; + assign n909 = n907 | n908; + assign n910 = n1219 | n1371; + assign n911 = n1232 | ~n1239; + assign n912 = n910 | n911; + assign n913 = ~n907 & (~n263 | ~n738); + assign n914 = n738 | n911; + assign n915 = ~n911 & (~n393 | ~n1102); + assign n916 = n911 | n688; + assign n917 = n2135 & n2104 & n2133; + assign n918 = n777 & n1649; + assign n919 = n741 & n743 & (~n97 | n774); + assign n920 = ~n98 | n761; + assign n921 = n264 & n979; + assign n922 = ~n97 | n921; + assign n923 = n1615 & n1614 & n1613 & n758; + assign n924 = n1198 | n1240; + assign n925 = n2289 & (n509 | (n1662 & n875)); + assign n926 = n1204 | n1240; + assign n927 = n676 & n925 & (n926 | n675); + assign n928 = n177 & n1256; + assign n929 = n1228 & n1256; + assign n930 = n165 | n278; + assign n931 = n930 & (~n685 | ~n1378); + assign n932 = ~n278 | n979; + assign n933 = ~n278 | n1207; + assign n934 = ~n278 | n474; + assign n935 = n2143 & (~n165 | n474); + assign n936 = n1196 | ~n1388; + assign n937 = n2100 & n2157 & n2075 & n1996 & n1877 & n2052; + assign n938 = n937 & n936 & n935 & n934 & n932 & n933; + assign n939 = n656 & n1665; + assign n940 = ~n165 | n939; + assign n941 = ~i_11_ | ~n900; + assign n942 = n941 | ~n1379; + assign n943 = i_11_ | n1202; + assign n944 = n943 | ~n1379; + assign n945 = ~n278 | n984; + assign n946 = ~n278 | n982; + assign n947 = ~n278 | n845; + assign n948 = n1995 & (~n278 | (n284 & n983)); + assign n949 = n948 & n947 & n945 & n946; + assign n950 = ~n278 | n939; + assign n951 = n1255 | n1371; + assign n952 = n1162 & n1028 & n1330; + assign n953 = n651 & n1029; + assign n954 = n953 & n952 & n684 & n288 & n951; + assign n955 = n251 | ~n278; + assign n956 = ~n278 | n1262; + assign n957 = ~n165 | n499; + assign n958 = ~n278 | n1341; + assign n959 = ~n278 | n522; + assign n960 = n1670 & (~n165 | n954); + assign n961 = n2291 & (~n278 | (n204 & n793)); + assign n962 = n2290 & n638 & n1949 & n1994 & n1931 & n1874 & n2050 & n2098; + assign n963 = n962 & n961 & n960 & n959 & n958 & n957 & n955 & n956; + assign n964 = n313 & n334; + assign n965 = n682 & n653 & n263 & n1676; + assign n966 = n739 & n789 & n964 & n965; + assign n967 = n1125 & ~n450 & n979; + assign n968 = n1335 & n1247 & n1373 & n1678 & n331 & n1102; + assign n969 = n774 & n777; + assign n970 = n329 & n317 & n495; + assign n971 = n970 & n793 & n798 & n969 & n968 & n967 & n657 & n525; + assign n972 = n1697 & n1696 & n1695 & n1694 & n1693 & n1692 & n1691 & n942; + assign n973 = n944 & n1690 & n1689 & n1688 & n1687 & n1685 & n1686; + assign n974 = n1705 & n1704 & n1703 & n1702 & n1701 & n1700 & n1698 & n1699; + assign n975 = n1713 & n1712 & n1711 & n1710 & n1709 & n1708 & n1706 & n1707; + assign n976 = n1721 & n1002 & n1730 & n1726; + assign n977 = n2298 & n2296 & n1936 & n1914 & n1684 & n963 & ~n166 & n949; + assign n978 = n2294 & n2295 & n1999 & n1913 & n2079 & n1998 & n1927 & n1937; + assign n979 = n1219 | n1243; + assign n980 = ~n116 | n979; + assign n981 = ~n116 | n287; + assign n982 = n798 & n1374 & n1224; + assign n983 = n1666 & n875 & n441; + assign n984 = n1201 | n1371; + assign n985 = n984 & n284 & n982 & n983; + assign n986 = ~n116 | n227; + assign n987 = ~n120 & n986 & (~n116 | n985); + assign n988 = ~n353 | n926; + assign n989 = ~n353 | n430; + assign n990 = ~n353 | ~n450; + assign n991 = n2162 & n2077 & n2161; + assign n992 = n1742 & n1741 & n1740 & n1739 & n1738 & n1737 & n1736 & n980; + assign n993 = n1735 & n1734 & n1733 & n1732 & ~n117 & n981; + assign n994 = (~n116 | n1144) & (~n353 | n1677); + assign n995 = n987 & n994 & n993 & n992 & n991 & n990 & n988 & n989; + assign n996 = ~n167 | n567; + assign n997 = ~n167 | n1157; + assign n998 = ~n167 | n566; + assign n999 = ~n167 | n508; + assign n1000 = ~n167 | n529; + assign n1001 = n1744 & n270 & n1743; + assign n1002 = n1722 & n537; + assign n1003 = n384 & n1440 & (~n167 | n982); + assign n1004 = n1003 & n1002 & n1001 & n1000 & n999 & n998 & n996 & n997; + assign n1005 = ~n167 | n393; + assign n1006 = ~n167 | n1139; + assign n1007 = ~n167 | n1138; + assign n1008 = ~n167 | n984; + assign n1009 = (~n381 | n658) & (~n404 | n982); + assign n1010 = n1969 & n1997 & n1919 & n2059 & n1878 & n1901 & n1117 & n1879; + assign n1011 = n1010 & n1004 & n1009 & n1008 & n1007 & n1005 & n1006; + assign n1012 = n1250 & n1104; + assign n1013 = ~n404 | n1012; + assign n1014 = ~n167 | n474; + assign n1015 = ~n167 | n979; + assign n1016 = ~n167 | n495; + assign n1017 = ~n170 & (~n381 | n2297); + assign n1018 = ~n404 | n654; + assign n1019 = n1899 & n2062 & n1884 & n1939 & n2165 & n1882; + assign n1020 = n1019 & n1018 & n1017 & n1016 & n1014 & n1015; + assign n1021 = ~n167 | n442; + assign n1022 = n1021 & (~n167 | (n330 & n527)); + assign n1023 = ~n167 | n707; + assign n1024 = n2096 & n1905 & n2058; + assign n1025 = n1023 & n1024 & (~n105 | ~n167); + assign n1026 = n684 & n1418; + assign n1027 = n288 & n873; + assign n1028 = n1263 | n1371; + assign n1029 = n1341 & n522; + assign n1030 = n1029 & n1028 & n204 & n1027 & n1026 & n720; + assign n1031 = n1748 & n1747 & n1745 & n1746; + assign n1032 = n1754 & n1753 & n1752 & n1751 & n1749 & n1750; + assign n1033 = n1956 & n1965 & (~n404 | n1030); + assign n1034 = n1279 & n1342 & n2132; + assign n1035 = n2299 & n1881 & n1933 & n1906 & n1880 & n2060; + assign n1036 = n1035 & n1034 & n1033 & n1022 & n1032 & n1031 & n1025 & n648; + assign n1037 = n381 & (~n964 | ~n1678); + assign n1038 = ~n774 | ~n329 | ~n604; + assign n1039 = n404 & (~n918 | n1038 | ~n1756); + assign n1040 = ~n176 | n1230; + assign n1041 = n1214 | n1230; + assign n1042 = n1040 & n1041; + assign n1043 = ~n105 & n1336; + assign n1044 = ~n571 | n1043; + assign n1045 = n107 & (~n500 | ~n1665); + assign n1046 = n331 & n951 & n1155; + assign n1047 = ~n104 | n1046; + assign n1048 = ~n113 | n1080; + assign n1049 = ~n278 | n610; + assign n1050 = n778 & (~n107 | n2307); + assign n1051 = n1050 & n1049 & n1048 & n919 & ~n115 & n538; + assign n1052 = n346 & (~n1247 | ~n1415); + assign n1053 = n1490 & n1489 & n1488 & n1487 & n1486 & n1485 & ~n773 & n1484; + assign n1054 = n1289 & n1287 & n1288; + assign n1055 = (~n404 | n2307) & (~n571 | n1795); + assign n1056 = n2309 & (~n104 | (n529 & n1136)); + assign n1057 = n1804 & n1051 & n1802 & n838 & n138 & n1783 & n972; + assign n1058 = n2308 & n2231 & n2167 & n2083 & n1722 & n1679 & n997 & ~n1052; + assign n1059 = n1058 & n1057 & n1056 & n1055 & n1054 & n630 & n1053 & n730; + assign n1060 = n104 & (~n447 | ~n1026 | ~n1381); + assign n1061 = ~n107 | n522; + assign n1062 = (~n104 | n953) & (n720 | n1292); + assign n1063 = n1062 & n416 & n1061; + assign n1064 = n104 & (~n1336 | ~n1664); + assign n1065 = n113 & (~n331 | ~n755); + assign n1066 = n571 & (~n651 | ~n755 | ~n951); + assign n1067 = n571 & (~n206 | ~n952 | ~n1026); + assign n1068 = n107 & (~n206 | ~n1027 | ~n1330); + assign n1069 = ~n113 | n1043; + assign n1070 = ~n107 | n1026; + assign n1071 = ~n113 | n2374; + assign n1072 = n1854 & n255 & (n1292 | n1162); + assign n1073 = n1499 & n1497 & n1498; + assign n1074 = ~n1067 & ~n1068 & (~n165 | n793); + assign n1075 = n2306 & n1063 & n1169 & n1823 & n1180 & n1812; + assign n1076 = n1075 & n1074 & n756 & n1073 & n1072 & n1071 & n1069 & n1070; + assign n1077 = n738 & n739; + assign n1078 = n489 | ~n571; + assign n1079 = ~n571 | n1372; + assign n1080 = n529 & n1415; + assign n1081 = n1078 & n1079 & (~n571 | n1080); + assign n1082 = n1221 | n1260; + assign n1083 = n1082 & n287 & ~n109 & n219; + assign n1084 = n471 & n674 & n426; + assign n1085 = n263 & n653 & n356; + assign n1086 = n287 & n1082; + assign n1087 = n685 & n592; + assign n1088 = n1087 & n1086 & n1085 & n1084 & n317; + assign n1089 = ~n113 | n685; + assign n1090 = ~n113 | n592; + assign n1091 = ~n113 | n317; + assign n1092 = (~n113 | n1083) & (~n571 | n1088); + assign n1093 = n1957 & n2145 & n1280 & n2030 & n2180 & n2142; + assign n1094 = n1093 & n1081 & n1092 & n1091 & n1089 & n1090; + assign n1095 = ~n113 | n951; + assign n1096 = n1095 & (~n113 | n651); + assign n1097 = n1220 | n1265; + assign n1098 = n739 & n1097 & n195; + assign n1099 = ~n653 & (n381 | n930); + assign n1100 = ~n107 | n470; + assign n1101 = n1887 & n2068 & n2102; + assign n1102 = n392 & n508; + assign n1103 = ~n169 & n1101 & (~n107 | n1102); + assign n1104 = n1151 & n1375; + assign n1105 = n1243 | n1249; + assign n1106 = n1105 & n1104 & n329 & n822 & n654; + assign n1107 = ~n104 | n1331; + assign n1108 = ~n104 | n444; + assign n1109 = (~n104 | n1106) & (~n107 | n654); + assign n1110 = n2136 & n1946 & n2230 & n2223 & n2311 & n1916 & n2166; + assign n1111 = n1110 & n1103 & n1109 & n1108 & n396 & n1107; + assign n1112 = n1105 & n201; + assign n1113 = ~n1114 & n1112 & n467 & n1102; + assign n1114 = ~n523 | ~n604; + assign n1115 = n571 & (~n392 | ~n822 | n1114); + assign n1116 = n329 & ~n1114; + assign n1117 = ~n167 | n1105; + assign n1118 = ~n167 | n329; + assign n1119 = ~n278 | n523; + assign n1120 = (~n346 | n1116) & (n1102 | n1290); + assign n1121 = ~n166 & ((~n107 & ~n571) | n1104); + assign n1122 = n1616 & n1430 & n2156 & n2081 & n1681 & n996 & n1680 & n998; + assign n1123 = n2323 & n1111 & n1779 & n1181 & n139 & n1675 & n1001 & n973; + assign n1124 = n1123 & n1122 & n1121 & n1120 & n1119 & n1118 & n225 & n1117; + assign n1125 = n1197 | n1371; + assign n1126 = n1125 & n1028; + assign n1127 = n116 | n253; + assign n1128 = (~n749 | ~n752) & (~n327 | n1127); + assign n1129 = ~n682 & (n321 | n930); + assign n1130 = ~n104 | n526; + assign n1131 = ~n104 | n1138; + assign n1132 = ~n104 | n845; + assign n1133 = n1823 & (~n104 | (n875 & n1224)); + assign n1134 = n507 & n2168 & n2224 & n2144 & n1922 & n2137 & n1889 & n2067; + assign n1135 = n1134 & n1133 & n1132 & n434 & n413 & n1131 & n395 & n1130; + assign n1136 = n1797 & n1157 & n1796; + assign n1137 = ~n571 | n1136; + assign n1138 = ~i_15_ | n1225; + assign n1139 = n472 & n875 & n845; + assign n1140 = n1139 & n1138 & n984; + assign n1141 = n499 & n567; + assign n1142 = n226 & n526 & n1141 & n441; + assign n1143 = n525 & ~n450 & n191 & ~n268; + assign n1144 = n879 & n1147; + assign n1145 = n1206 | n1220; + assign n1146 = n361 & n1145 & n1144 & n658; + assign n1147 = n313 & n1152 & n752 & n1731 & n263 & n1676; + assign n1148 = n1147 & n658 & n685; + assign n1149 = n1866 & n1224 & n1166 & n738 & ~n99 & n631; + assign n1150 = n953 & n474 & n251 & n1149 & n1085 & n720; + assign n1151 = n1220 | n1257; + assign n1152 = n1197 | n1220; + assign n1153 = n447 & n1152 & n1151 & n333 & n316 & n313; + assign n1154 = n426 & n738; + assign n1155 = n1220 | n1258; + assign n1156 = n284 & n265 & n227; + assign n1157 = n1220 | n1241; + assign n1158 = n1248 & n1334 & n951; + assign n1159 = n1158 & n1157 & n1156 & n1155 & n969 & n968 & n309 & ~n450; + assign n1160 = n334 & n749; + assign n1161 = n752 & n1507; + assign n1162 = n251 & n762; + assign n1163 = n1250 & n1374 & n610 & n688 & n489 & n313; + assign n1164 = n1163 & n1162 & n1161 & n1160 & n798 & n979; + assign n1165 = n1868 & n1867 & n1104 & n430 & n319 & ~n268 & n198 & n206; + assign n1166 = n789 & n521 & n1145; + assign n1167 = n1166 & n1165 & n873 & n195 & n361; + assign n1168 = n1833 & n1832 & n1831 & n1830 & n1829 & n1828 & ~n110 & n1827; + assign n1169 = n1826 & n1825 & ~n1060 & n1824; + assign n1170 = n1853 & n1852 & n1851 & n1850 & n1849 & n1848 & n1847 & n1100; + assign n1171 = n1063 & n1808 & n1802; + assign n1172 = n534 & n1790 & (~n104 | n1159); + assign n1173 = n2364 & n2365 & n2169 & n1267 & n1266 & n433 & n2087 & n1921; + assign n1174 = n1173 & n1172 & n1171 & n1170 & n1135 & n1111 & n1168 & n1169; + assign n1175 = n1335 & n682; + assign n1176 = n1240 | n1376; + assign n1177 = n227 & n1250 & n540; + assign n1178 = n1507 & n952 & n967 & n969 & n1795 & n1165 & n1870 & n1869; + assign n1179 = n1178 & n1177 & n926 & n504 & n1176 & n191 & n1175 & n1097; + assign n1180 = n1818 & n1817 & n1816 & n1815 & n1814 & ~n114 & n1813; + assign n1181 = n1839 & n1838 & n1837 & n1836 & n1835 & n1834 & n1096 & ~n1115; + assign n1182 = n1865 & n1855 & n1137 & n1864 & n1863 & n1390; + assign n1183 = n1846 & n1845 & n1844 & n1843 & n1842 & ~n118 & n414; + assign n1184 = n1812 & n1794 & n569; + assign n1185 = n2367 & (~n571 | n1179); + assign n1186 = n2366 & n1958 & n1942 & n1409 & ~n115 & n1268; + assign n1187 = n1186 & n1185 & n1184 & n1183 & n1182 & n1181 & n1094 & n1180; + assign n1188 = ~n96 | n755; + assign n1189 = ~n163 | n1341; + assign n1190 = ~n163 | n522; + assign n1191 = ~n163 | n288; + assign n1192 = n1512 & n1511 & n1510 & n598 & n1508 & n1509; + assign n1193 = ~n163 | (n306 & n720); + assign n1194 = n2149 & n1860 & n1912 & n1954 & n2123 & n2088 & n2041 & n2122; + assign n1195 = n1194 & n1193 & n794 & n1192 & n1191 & n1190 & n1188 & n1189; + assign n1196 = i_11_ | ~n901; + assign n1197 = ~i_15_ | n1196; + assign n1198 = i_12_ | i_14_ | i_13_; + assign n1199 = i_12_ | ~i_13_; + assign n1200 = i_11_ | ~n900; + assign n1201 = ~i_15_ | n1200; + assign n1202 = ~i_9_ | ~i_10_; + assign n1203 = n1202 & n941; + assign n1204 = ~i_14_ | i_12_ | i_13_; + assign n1205 = i_11_ | n481; + assign n1206 = ~i_15_ | n1205; + assign n1207 = n1197 | n1198; + assign n1208 = ~i_12_ | n1196; + assign n1209 = ~i_11_ | ~n901; + assign n1210 = ~i_12_ | n1200; + assign n1211 = n1199 & n1204 & n1210 & n1209 & n226 & n1208 & n1207 & n1203; + assign n1212 = i_3_ | i_5_ | i_4_; + assign n1213 = n172 & ~n1212; + assign n1214 = ~i_8_ | n816; + assign n1215 = i_5_ & ~i_3_ & ~i_4_; + assign n1216 = i_5_ & ~i_3_ & i_4_; + assign n1217 = i_15_ | n1200; + assign n1218 = n1200 | n1204; + assign n1219 = i_15_ | n1196; + assign n1220 = i_14_ | n1199; + assign n1221 = ~i_14_ | n1199; + assign n1222 = n481 & n1202; + assign n1223 = n1196 | n1221; + assign n1224 = n1201 | n1220; + assign n1225 = n1200 | n1221; + assign n1226 = n266 & n1209 & n941 & n1208 & n265 & n1210; + assign n1227 = n1226 & n1225 & n1224 & n1223 & n749 & n1152; + assign n1228 = ~i_8_ & n136; + assign n1229 = i_5_ | i_3_ | ~i_4_; + assign n1230 = ~n172 | n1229; + assign n1231 = ~n186 & ~n1212; + assign n1232 = i_8_ | ~n122; + assign n1233 = i_8_ | n816; + assign n1234 = n1230 | n1232; + assign n1235 = n1234 & n459; + assign n1236 = ~i_5_ & i_3_ & ~i_4_; + assign n1237 = n172 & n174; + assign n1238 = i_15_ | n1209; + assign n1239 = ~n186 & n1216; + assign n1240 = i_15_ | n1205; + assign n1241 = i_15_ | n941; + assign n1242 = ~i_12_ | i_13_; + assign n1243 = i_14_ | n1242; + assign n1244 = ~i_12_ | ~i_13_; + assign n1245 = i_14_ | n1244; + assign n1246 = ~i_15_ | n941; + assign n1247 = n1241 | n1245; + assign n1248 = n1198 | n1246; + assign n1249 = i_15_ | n943; + assign n1250 = n1198 | n1249; + assign n1251 = i_6_ | ~i_7_; + assign n1252 = ~i_8_ & ~n1251; + assign n1253 = ~n186 & n1215; + assign n1254 = ~i_11_ | n1202; + assign n1255 = i_15_ | n1254; + assign n1256 = ~n186 & ~n1229; + assign n1257 = ~i_15_ | n943; + assign n1258 = ~i_15_ | n1254; + assign n1259 = ~i_11_ | n481; + assign n1260 = i_15_ | n1259; + assign n1261 = n1220 | n1255; + assign n1262 = n1238 | n1243; + assign n1263 = ~i_15_ | n1209; + assign n1264 = i_8_ & ~n1251; + assign n1265 = ~i_15_ | n1259; + assign n1266 = ~n107 | n226; + assign n1267 = ~n107 | n227; + assign n1268 = ~n113 | n227; + assign n1269 = n1957 & n1815 & n1826 & n1956; + assign n1270 = n1955 & n1476 & n1954 & n1953 & n1952 & n1951 & n1949 & n1950; + assign n1271 = n1270 & n1269 & n1268 & n1267 & n1266 & n228; + assign n1272 = ~n96 | n1207; + assign n1273 = ~n96 | n474; + assign n1274 = n1273 & ~n230 & n1272; + assign n1275 = ~n96 | n334; + assign n1276 = ~n97 | n331; + assign n1277 = ~n97 | n334; + assign n1278 = ~n96 | n313; + assign n1279 = ~n167 | n331; + assign n1280 = ~n113 | n1797; + assign n1281 = n1958 & n1271 & n1118 & ~n229 & n222 & n224; + assign n1282 = n1281 & n1280 & n1279 & n1278 & n1277 & n1276 & n485 & n1275; + assign n1283 = ~n167 | n309; + assign n1284 = ~n167 | n1247; + assign n1285 = ~n167 | n1248; + assign n1286 = n1285 & n1283 & n1284; + assign n1287 = ~n278 | n309; + assign n1288 = ~n278 | n1248; + assign n1289 = ~n278 | n1247; + assign n1290 = ~n104 & ~n165; + assign n1291 = ~n116 & ~n278; + assign n1292 = ~n104 & ~n107; + assign n1293 = n1204 | n1255; + assign n1294 = n1293 & n508; + assign n1295 = n288 & n879; + assign n1296 = n1908 & (n911 | n508); + assign n1297 = n1828 & n1907 & n1788 & n1651 & n1753 & n1748; + assign n1298 = n1904 & n1749 & n1906 & n1905 & n1692 & n1717 & n1671 & n1689; + assign n1299 = n1892 & n731 & n1893 & n728 & n1626 & n1477 & n1482 & n1560; + assign n1300 = n1896 & n1599 & n1898 & n1564 & n1589 & n1897 & n1577 & n1570; + assign n1301 = n1789 & n1820 & n1829 & n1831 & n1888 & n1793 & n1806 & n1887; + assign n1302 = n1889 & n1851 & n1850 & n1108 & n324 & ~n322 & ~n164 & n320; + assign n1303 = n1737 & n1735 & n1021 & n986 & n1881 & n1880 & n1878 & n1879; + assign n1304 = n1886 & n1885 & n1884 & n1883 & n1773 & n1882 & n1777 & n1784; + assign n1305 = n1504 & n1501 & n1669 & n1875 & n1703 & n1874 & n1872 & n1873; + assign n1306 = n1693 & n1695 & n1686 & n1877 & n1711 & n1690 & n1876 & n1673; + assign n1307 = n852 & n1474 & n1871 & n1487 & n1509 & n1451 & n1547 & n1552; + assign n1308 = n1529 & n1539 & n1590 & n1593 & n1571 & n1572 & n1567 & n1601; + assign n1309 = ~n116 & ~n294; + assign n1310 = n617 & n306 & n305; + assign n1311 = n266 & n1310; + assign n1312 = ~n98 | n331; + assign n1313 = ~n163 | n331; + assign n1314 = ~n571 | n2375; + assign n1315 = n1890 & (~n165 | n331); + assign n1316 = n1315 & n1314 & n1312 & n1313; + assign n1317 = ~n107 | n191; + assign n1318 = n1922 & n1117 & n1920 & n1921; + assign n1319 = n1919 & n988 & n1769 & n1918 & n1917 & n1015 & n1825 & n1916; + assign n1320 = n1912 & n1557 & n1911 & n1544 & n1579 & n1582 & n1585 & n1587; + assign n1321 = n1603 & n1635 & n1555 & n1915 & n932 & n956 & n1913 & n1914; + assign n1322 = ~n404 | n442; + assign n1323 = n330 | ~n404; + assign n1324 = ~n404 | n527; + assign n1325 = n1324 & n1322 & n1323; + assign n1326 = ~n163 | n330; + assign n1327 = ~n163 | n527; + assign n1328 = ~n163 | n1261; + assign n1329 = n1328 & n1326 & n1327; + assign n1330 = n1221 | n1238; + assign n1331 = n1245 | n1257; + assign n1332 = n1221 | n943; + assign n1333 = n1206 | n1245; + assign n1334 = n1243 | n1246; + assign n1335 = i_15_ | n1223; + assign n1336 = n1221 | n1255; + assign n1337 = n1206 | n1243; + assign n1338 = ~n97 | n441; + assign n1339 = ~n98 | n1330; + assign n1340 = n1339 & n847 & n850 & n1338; + assign n1341 = n1220 | n1263; + assign n1342 = ~n167 | n1155; + assign n1343 = ~n113 | n1155; + assign n1344 = ~n97 | n1155; + assign n1345 = ~n96 | n1224; + assign n1346 = n1248 & n729; + assign n1347 = n423 & n1336 & n392; + assign n1348 = n684 & n1151; + assign n1349 = ~n165 & ~n321; + assign n1350 = ~n97 | n472; + assign n1351 = ~n98 | n472; + assign n1352 = n448 & (~n97 | (n873 & n1346)); + assign n1353 = ~i_0_ | i_1_; + assign n1354 = n1229 | n1353; + assign n1355 = n1251 | n1354; + assign n1356 = n816 | n1354; + assign n1357 = ~n136 | n1354; + assign n1358 = ~n122 | n1354; + assign n1359 = n1358 & n1357 & n1355 & n1356; + assign n1360 = n1271 & n2026 & (~n107 | n495); + assign n1361 = n2024 & n2023 & n2022 & n2021 & ~n456 & ~n457; + assign n1362 = n2018 & n2016 & n2020 & n1288 & n1791 & n2019 & n1732 & n1322; + assign n1363 = n2013 & n2005 & n2006 & n1536 & n1857 & n1472 & n619 & n718; + assign n1364 = n1212 | n1353; + assign n1365 = n883 & n864 & n867 & n885; + assign n1366 = n879 | ~n897; + assign n1367 = ~n897 | n1207; + assign n1368 = ~n1213 | n1251; + assign n1369 = n887 & n859 & n1621 & n2118 & n1623 & n1631; + assign n1370 = n1369 & n482 & n1368 & n1367 & n824 & n1366; + assign n1371 = ~i_14_ | n1242; + assign n1372 = n1246 | n1371; + assign n1373 = n1206 | n1371; + assign n1374 = n1217 | n1371; + assign n1375 = n1249 | n1371; + assign n1376 = ~i_14_ | n1244; + assign n1377 = n1255 | n1376; + assign n1378 = n1082 & n674; + assign n1379 = n1252 & n1253; + assign n1380 = n529 & n536; + assign n1381 = n1330 & n288; + assign n1382 = n526 & n653; + assign n1383 = n840 & n211 & n839 & n832; + assign n1384 = ~n98 | n1176; + assign n1385 = ~n98 | n430; + assign n1386 = ~n98 | n926; + assign n1387 = n1386 & n1384 & n1385; + assign n1388 = n1253 & n1264; + assign n1389 = ~n107 | n1176; + assign n1390 = ~n113 | n984; + assign n1391 = ~n168 & n1845 & (~n278 | n518); + assign n1392 = n2170 & n1661 & n1660 & n2169 & n2168 & n1008; + assign n1393 = n1798 & n2165 & n1762 & n1658 & n1827 & n1656; + assign n1394 = n1765 & n2167 & n1813 & n1848 & n1807 & n2166; + assign n1395 = n2155 & n2159 & n996 & n2164 & n2163 & n2162 & n2160 & n2161; + assign n1396 = ~n167 | n536; + assign n1397 = n406 & n1396 & n385; + assign n1398 = ~n96 | n875; + assign n1399 = n387 & n408 & n1398; + assign n1400 = ~n278 | n508; + assign n1401 = n407 & n1400 & n386; + assign n1402 = ~n97 | n526; + assign n1403 = ~n98 | n504; + assign n1404 = n447 & n649; + assign n1405 = n1374 & n1375; + assign n1406 = n521 & n910 & n653 & n191; + assign n1407 = n523 & n592 & n984 & n1125 & n528; + assign n1408 = n685 & n688 & n1138 & n566 & n495; + assign n1409 = ~n571 | n2376; + assign n1410 = n2139 & (n474 | ~n571); + assign n1411 = n1410 & n1409 & n1401 & n1005 & n999 & ~n570 & n384 & n569; + assign n1412 = n1397 & n2147 & (~n278 | n875); + assign n1413 = n2141 & n2145 & n1817 & n2144 & n1844 & n2143 & n2142 & n1767; + assign n1414 = n1413 & n1412 & n565 & n1399 & n562 & n560; + assign n1415 = n610 & n528; + assign n1416 = n566 & ~n1114; + assign n1417 = n1206 | n1376; + assign n1418 = n504 & n306; + assign n1419 = ~n278 | n489; + assign n1420 = n538 & n1419 & n1049; + assign n1421 = ~n96 | n685; + assign n1422 = n1421 & n626; + assign n1423 = ~n98 | n499; + assign n1424 = ~n98 | n500; + assign n1425 = ~n97 | n499; + assign n1426 = ~n97 | n500; + assign n1427 = ~n97 | n489; + assign n1428 = ~n97 | n1372; + assign n1429 = n793 & n752; + assign n1430 = n1293 | n509; + assign n1431 = ~n929 | n1372; + assign n1432 = (n509 | n536) & (n499 | ~n929); + assign n1433 = n1432 & n1431 & n1430 & n678 & ~n679; + assign n1434 = ~n98 | n798; + assign n1435 = ~n98 | n654; + assign n1436 = ~n163 | n1666; + assign n1437 = (~n343 | n654) & (n327 | n798); + assign n1438 = n1437 & n646 & n648 & n650 & n1436 & n1435 & n754 & n1434; + assign n1439 = ~n167 | n489; + assign n1440 = n1439 & n611; + assign n1441 = ~n1216 | n1353; + assign n1442 = n1251 | n1441; + assign n1443 = ~n122 | n1441; + assign n1444 = n816 | n1441; + assign n1445 = n1444 & n1442 & n1443; + assign n1446 = n474 & n226 & n875; + assign n1447 = ~n97 | n793; + assign n1448 = ~n97 | n522; + assign n1449 = ~n97 | n1341; + assign n1450 = n1449 & n1447 & n1448; + assign n1451 = ~n98 | n822; + assign n1452 = ~n97 | n651; + assign n1453 = ~n97 | n951; + assign n1454 = n1450 & n721; + assign n1455 = n855 & n860 & n727 & n1454; + assign n1456 = n2120 & n1953 & n2045 & n2119 & n2044 & n1893 & n1871 & n2148; + assign n1457 = n1456 & n736 & n735 & n560 & n364 & n222 & ~n162 & n199; + assign n1458 = ~n97 | n1145; + assign n1459 = ~n97 | n924; + assign n1460 = ~n98 | n1224; + assign n1461 = ~n97 | n777; + assign n1462 = ~n98 | n540; + assign n1463 = ~n98 | n1097; + assign n1464 = ~n97 | n540; + assign n1465 = ~n97 | n1097; + assign n1466 = ~n97 | n739; + assign n1467 = ~n97 | n752; + assign n1468 = ~n97 | n910; + assign n1469 = ~n98 | n910; + assign n1470 = ~n98 | n1152; + assign n1471 = ~n97 | n1152; + assign n1472 = ~n98 | n1155; + assign n1473 = n179 & ~n1233; + assign n1474 = ~n98 | n251; + assign n1475 = ~n97 | n251; + assign n1476 = ~n97 | n1261; + assign n1477 = ~n98 | n288; + assign n1478 = ~n97 | n654; + assign n1479 = ~n97 | n1375; + assign n1480 = ~n98 | n526; + assign n1481 = ~n98 | n441; + assign n1482 = ~n98 | n875; + assign n1483 = n1482 & n1481 & n1480 & n775 & n1478 & n1479; + assign n1484 = ~n98 | n489; + assign n1485 = ~n98 | n440; + assign n1486 = ~n98 | n1372; + assign n1487 = ~n98 | n1157; + assign n1488 = ~n98 | n530; + assign n1489 = ~n98 | n528; + assign n1490 = ~n98 | n529; + assign n1491 = ~n97 | n1151; + assign n1492 = ~n97 | n1250; + assign n1493 = ~n97 | n567; + assign n1494 = ~n98 | n1151; + assign n1495 = ~n98 | n1250; + assign n1496 = n772 & n1495 & n1494 & n365 & n1493 & n1491 & n1492; + assign n1497 = ~n96 | n651; + assign n1498 = ~n96 | n951; + assign n1499 = ~n96 | n1155; + assign n1500 = ~n163 | n393; + assign n1501 = ~n163 | n444; + assign n1502 = ~n163 | n329; + assign n1503 = ~n163 | n1105; + assign n1504 = ~n163 | n822; + assign n1505 = n1504 & n1503 & n1502 & n1500 & n1501; + assign n1506 = n334 & n1374; + assign n1507 = n1152 & n910; + assign n1508 = ~n96 | n707; + assign n1509 = ~n96 | n442; + assign n1510 = ~n96 | n1336; + assign n1511 = ~n96 | n1293; + assign n1512 = ~n96 | n656; + assign n1513 = ~n96 | n654; + assign n1514 = ~n163 | n1151; + assign n1515 = ~n163 | n1250; + assign n1516 = n1515 & n1513 & n1514; + assign n1517 = ~n96 | n1161; + assign n1518 = n1517 & n797 & n511 & ~n796; + assign n1519 = ~n96 | n798; + assign n1520 = ~n96 | n1374; + assign n1521 = n1520 & ~n795 & n1519; + assign n1522 = ~n163 | n567; + assign n1523 = ~n163 | n392; + assign n1524 = ~n163 | n508; + assign n1525 = ~n163 | n1331; + assign n1526 = n608 & n1525 & n1524 & n1522 & n1523; + assign n1527 = ~n163 | n984; + assign n1528 = ~n163 | n472; + assign n1529 = ~n163 | n226; + assign n1530 = ~n163 | n284; + assign n1531 = ~n163 | n2371; + assign n1532 = n1531 & n1530 & n1529 & n1527 & n1528; + assign n1533 = ~n97 | n1417; + assign n1534 = ~n97 | n521; + assign n1535 = ~n98 | n521; + assign n1536 = ~n98 | n1145; + assign n1537 = n1536 & n1535 & n1277 & n790 & n1533 & n1534; + assign n1538 = ~n163 | n707; + assign n1539 = ~n163 | n442; + assign n1540 = ~n163 | n1293; + assign n1541 = ~n163 | n656; + assign n1542 = ~n163 | n499; + assign n1543 = ~n163 | n1336; + assign n1544 = ~n96 | n1262; + assign n1545 = ~n96 | n473; + assign n1546 = ~n96 | n206; + assign n1547 = ~n163 | n206; + assign n1548 = ~n163 | n204; + assign n1549 = ~n163 | n447; + assign n1550 = ~n163 | n473; + assign n1551 = ~n163 | n1262; + assign n1552 = ~n163 | n251; + assign n1553 = ~n96 | n1028; + assign n1554 = ~n96 | n472; + assign n1555 = ~n96 | n284; + assign n1556 = n1399 & n1554 & n1555; + assign n1557 = ~n97 | n674; + assign n1558 = ~n97 | n653; + assign n1559 = ~n97 | n1082; + assign n1560 = ~n98 | n674; + assign n1561 = ~n98 | n2368; + assign n1562 = ~n98 | n653; + assign n1563 = ~n98 | n1082; + assign n1564 = ~n96 | n508; + assign n1565 = ~n96 | n1331; + assign n1566 = ~n96 | n393; + assign n1567 = ~n96 | n444; + assign n1568 = ~n96 | n329; + assign n1569 = n1568 & n1567 & n1566 & n1564 & n1565; + assign n1570 = ~n163 | n309; + assign n1571 = ~n163 | n1157; + assign n1572 = ~n163 | n1248; + assign n1573 = ~n163 | n1247; + assign n1574 = ~n163 | n688; + assign n1575 = ~n163 | n1334; + assign n1576 = ~n163 | n529; + assign n1577 = ~n163 | n536; + assign n1578 = n1577 & n1576 & n1575 & n1574 & n1573 & n1572 & n1570 & n1571; + assign n1579 = ~n96 | n309; + assign n1580 = ~n96 | n1334; + assign n1581 = ~n96 | n529; + assign n1582 = ~n96 | n536; + assign n1583 = ~n96 | n471; + assign n1584 = ~n96 | n1082; + assign n1585 = ~n96 | n674; + assign n1586 = ~n96 | n356; + assign n1587 = ~n96 | n287; + assign n1588 = n1587 & n242 & n1586 & n1585 & n1584 & n367 & n1583; + assign n1589 = ~n163 | n287; + assign n1590 = ~n163 | n317; + assign n1591 = ~n96 | n592; + assign n1592 = ~n163 | n471; + assign n1593 = ~n163 | n356; + assign n1594 = ~n163 | n195; + assign n1595 = n2127 & n2090 & n2124 & n2093 & n2042 & n1897; + assign n1596 = n1595 & n1594 & n1593 & n1592 & n1591 & n1589 & n1590; + assign n1597 = n2150 & n2004 & n1992 & n1387 & ~n100 & n192; + assign n1598 = n1597 & n1496 & n1053 & n1483 & n618 & n646; + assign n1599 = ~n163 | n979; + assign n1600 = ~n96 | n1335; + assign n1601 = ~n163 | n1207; + assign n1602 = ~n163 | n264; + assign n1603 = ~n96 | n879; + assign n1604 = ~n96 | n362; + assign n1605 = ~n96 | n709; + assign n1606 = n2046 & n2094 & n1898 & n2092 & n2126 & n2125 & n2047; + assign n1607 = n1606 & n1605 & n1604 & n1603 & n1602 & n1601 & n1599 & n1600; + assign n1608 = n172 & n173; + assign n1609 = n1607 & n1598 & n769 & n760; + assign n1610 = n2275 & n605 & n1556 & n594 & n830 & n811 & n829 & n1569; + assign n1611 = n2274 & n2272 & n1629 & n1634 & n1633 & n1635 & n842 & n2152; + assign n1612 = n706 & n1445 & n463 & n863 & n1359; + assign n1613 = n1207 | ~n1473; + assign n1614 = n227 | ~n1473; + assign n1615 = n879 | ~n1473; + assign n1616 = ~n98 | n1375; + assign n1617 = n753 & n1616 & n856; + assign n1618 = n858 & n1455; + assign n1619 = n715 | n123 | n818 | n181; + assign n1620 = n822 | n459; + assign n1621 = n822 | ~n897; + assign n1622 = n699 & n1621 & n1620 & n823; + assign n1623 = n227 | ~n897; + assign n1624 = n227 | n459; + assign n1625 = n1624 & n1614 & n1623 & n821 & n711 & n698; + assign n1626 = ~n97 | n875; + assign n1627 = n1626 & n1402 & n1350 & n1338 & n213 & ~n844; + assign n1628 = n898 | n1473 | n818; + assign n1629 = ~n96 | n392; + assign n1630 = n1569 & n1629 & n605; + assign n1631 = n875 | ~n897; + assign n1632 = n1357 & n1631 & n702 & n876; + assign n1633 = ~n96 | n822; + assign n1634 = ~n96 | n567; + assign n1635 = ~n96 | n1105; + assign n1636 = n1635 & n1634 & n1633 & n1630; + assign n1637 = n493 & n494 & n635 & n1607; + assign n1638 = n1422 & n250 & n1588 & n1596; + assign n1639 = n666 & n1339 & n1403 & n224 & n665 & n1961; + assign n1640 = n1639 & n663 & n448 & n207 & n871 & n764 & n874; + assign n1641 = n701 & n1358 & n1615 & n1366 & n1443; + assign n1642 = n2027 & n667 & n2152 & n1351 & n846 & n487 & n315 & n624; + assign n1643 = n1642 & n841 & n843 & n1627 & n727 & n669 & n810 & n1556; + assign n1644 = n831 & n1598 & n748; + assign n1645 = ~n136 | n1230; + assign n1646 = n1237 & ~n481 & ~n1214; + assign n1647 = n1236 & ~n1214 & n172 & ~n481; + assign n1648 = n891 & n1625 & n1632; + assign n1649 = n1247 & n610; + assign n1650 = n911 | n523; + assign n1651 = n1105 | n911; + assign n1652 = n907 | n1375; + assign n1653 = n911 | n1375; + assign n1654 = n911 | n567; + assign n1655 = n907 | n426; + assign n1656 = n907 | n592; + assign n1657 = n907 | n685; + assign n1658 = n907 | n653; + assign n1659 = n907 | n910; + assign n1660 = n907 | n1125; + assign n1661 = n907 | n682; + assign n1662 = n508 & n536; + assign n1663 = n1373 & n1125; + assign n1664 = n330 & n1293; + assign n1665 = n1664 & n1043; + assign n1666 = n1138 & n658; + assign n1667 = ~n278 | n527; + assign n1668 = ~n278 | n707; + assign n1669 = ~n278 | n442; + assign n1670 = n1669 & n1668 & n1667 & n950; + assign n1671 = ~n278 | n1105; + assign n1672 = ~n278 | n392; + assign n1673 = ~n278 | n444; + assign n1674 = ~n278 | n329; + assign n1675 = n1401 & n1674 & n1673 & n1671 & n1672; + assign n1676 = n1097 & n738 & n264 & n540 & n266; + assign n1677 = n1166 & n316 & n191 & ~n268; + assign n1678 = n965 & n1677 & n739 & n879 & n361; + assign n1679 = ~n278 | n1334; + assign n1680 = ~n278 | n604; + assign n1681 = ~n278 | n822; + assign n1682 = ~n278 | n530; + assign n1683 = n2081 & n1932 & n2156; + assign n1684 = n1683 & n1682 & n1681 & n1675 & n1054 & n1119 & n1679 & n1680; + assign n1685 = ~n165 | n393; + assign n1686 = ~n165 | n444; + assign n1687 = ~n165 | n566; + assign n1688 = ~n165 | n567; + assign n1689 = ~n165 | n1105; + assign n1690 = ~n165 | n822; + assign n1691 = ~n165 | n1796; + assign n1692 = ~n165 | n309; + assign n1693 = ~n165 | n1157; + assign n1694 = ~n165 | n529; + assign n1695 = ~n165 | n1248; + assign n1696 = ~n165 | n1372; + assign n1697 = ~n165 | n489; + assign n1698 = ~n165 | n1155; + assign n1699 = n1254 | ~n1379; + assign n1700 = ~n278 | n499; + assign n1701 = ~n278 | n500; + assign n1702 = ~n165 | n707; + assign n1703 = ~n165 | n442; + assign n1704 = ~n165 | n527; + assign n1705 = n2174 & n2220 & n1872 & n940 & n2029 & n1963; + assign n1706 = ~n165 | n265; + assign n1707 = ~n165 | n526; + assign n1708 = ~n165 | n984; + assign n1709 = ~n165 | n1138; + assign n1710 = ~n165 | n472; + assign n1711 = ~n165 | n226; + assign n1712 = ~n165 | n313; + assign n1713 = n2010 & n2194 & n2101 & n1875 & n1895 & n2054 & n1894; + assign n1714 = ~n278 | n471; + assign n1715 = ~n278 | n356; + assign n1716 = n2292 & (n1259 | ~n1388); + assign n1717 = ~n165 | n287; + assign n1718 = ~n278 | n592; + assign n1719 = ~n278 | n426; + assign n1720 = n2129 & n1929 & n2053 & n1873; + assign n1721 = n1720 & n1719 & n1718 & n1717 & n1716 & n1715 & ~n931 & n1714; + assign n1722 = ~n278 | n688; + assign n1723 = ~n278 | n774; + assign n1724 = ~n278 | n1372; + assign n1725 = ~n278 | n440; + assign n1726 = n1725 & n1724 & n1723 & n639; + assign n1727 = ~n278 | n1250; + assign n1728 = ~n278 | n1375; + assign n1729 = ~n278 | n1151; + assign n1730 = n1729 & n1728 & n1727 & n637; + assign n1731 = n739 & n1160; + assign n1732 = ~n116 | n2368; + assign n1733 = ~n116 | n592; + assign n1734 = ~n116 | n685; + assign n1735 = ~n116 | n317; + assign n1736 = ~n116 | n2373; + assign n1737 = ~n116 | n474; + assign n1738 = ~n116 | n910; + assign n1739 = ~n116 | n682; + assign n1740 = ~n116 | n1335; + assign n1741 = ~n116 | n1125; + assign n1742 = ~n116 | n495; + assign n1743 = ~n167 | n523; + assign n1744 = ~n167 | n392; + assign n1745 = ~n404 | n656; + assign n1746 = ~n404 | n707; + assign n1747 = ~n404 | n1336; + assign n1748 = ~n404 | n1293; + assign n1749 = ~n167 | n1262; + assign n1750 = ~n167 | n306; + assign n1751 = ~n167 | n504; + assign n1752 = ~n167 | n1330; + assign n1753 = ~n167 | n288; + assign n1754 = n2070 & n2106 & n1888 & n271; + assign n1755 = n317 & n1373 & n287; + assign n1756 = n1755 & n1408 & n1407 & n1380 & n1139 & n525 & ~n450 & n470; + assign n1757 = ~n404 | n951; + assign n1758 = ~n404 | n651; + assign n1759 = ~n167 | n500; + assign n1760 = ~n167 | n651; + assign n1761 = ~n167 | n951; + assign n1762 = ~n167 | n499; + assign n1763 = n2015 & n1970; + assign n1764 = n1763 & n1762 & n1761 & n1760 & n1759 & n1758 & n1757 & n1325; + assign n1765 = ~n167 | n592; + assign n1766 = ~n167 | n685; + assign n1767 = ~n167 | n1084; + assign n1768 = ~n167 | n356; + assign n1769 = ~n167 | n287; + assign n1770 = ~n167 | n317; + assign n1771 = n2095 & n1902 & n2056 & n2002 & n2055 & n1885; + assign n1772 = n1771 & n1770 & n1769 & n1768 & n1767 & n1765 & n1766; + assign n1773 = ~n404 | n444; + assign n1774 = ~n404 | n1105; + assign n1775 = ~n404 | n1331; + assign n1776 = n393 | ~n404; + assign n1777 = ~n404 | n822; + assign n1778 = n2219 & n1934 & n1966 & n2033 & n2130 & n2181 & n2064 & n1900; + assign n1779 = n1778 & n1730 & n1013 & n1777 & n1776 & n1775 & n1773 & n1774; + assign n1780 = ~n404 | n489; + assign n1781 = n2020 & n1883 & n2202; + assign n1782 = n2300 & n1967 & n2034 & n1903 & n1886 & n2063 & n2217 & n2131; + assign n1783 = n1782 & n1781 & n1780 & n1000 & n1397 & n1286 & n611 & n1726; + assign n1784 = ~n107 | n442; + assign n1785 = ~n107 | n656; + assign n1786 = ~n107 | n707; + assign n1787 = n1786 & n1785 & ~n1045 & n1784; + assign n1788 = ~n104 | n527; + assign n1789 = ~n104 | n1261; + assign n1790 = n1787 & n1788 & n1789; + assign n1791 = ~n571 | n1155; + assign n1792 = ~n571 | n2374; + assign n1793 = ~n571 | n1261; + assign n1794 = n1793 & n1792 & n1791 & n1044; + assign n1795 = n440 & n530; + assign n1796 = n536 & n729; + assign n1797 = n309 & n336; + assign n1798 = ~n107 | n1372; + assign n1799 = ~n104 | n1372; + assign n1800 = ~n107 | n774; + assign n1801 = n2019 & n2196 & n1920 & n1945; + assign n1802 = n1801 & n1800 & n1799 & n1798 & ~n108 & ~n112; + assign n1803 = n1047 & n1876 & n1472 & n854 & n1316 & n788; + assign n1804 = n1803 & n1794 & n1790 & n1764 & n974 & n1031; + assign n1805 = ~n104 | n473; + assign n1806 = ~n104 | n206; + assign n1807 = ~n107 | n1028; + assign n1808 = n1807 & n1805 & n1806; + assign n1809 = ~n113 | n499; + assign n1810 = ~n113 | n500; + assign n1811 = n1343 & (~n294 | (n793 & n1029)); + assign n1812 = n1811 & n1810 & n1809 & ~n1066 & n502 & ~n1065; + assign n1813 = ~n113 | n1028; + assign n1814 = ~n113 | n684; + assign n1815 = ~n113 | n1261; + assign n1816 = ~n571 | n1027; + assign n1817 = ~n113 | n1027; + assign n1818 = ~n113 | n2370; + assign n1819 = ~n104 | n707; + assign n1820 = ~n104 | n442; + assign n1821 = ~n104 | n499; + assign n1822 = ~n104 | n656; + assign n1823 = n1822 & n1821 & n1820 & n1819 & ~n106 & ~n1064; + assign n1824 = ~n104 | n1028; + assign n1825 = ~n107 | n527; + assign n1826 = ~n107 | n1261; + assign n1827 = ~n107 | n592; + assign n1828 = ~n104 | n287; + assign n1829 = ~n104 | n317; + assign n1830 = ~n104 | n471; + assign n1831 = ~n104 | n356; + assign n1832 = n2105 & n2066 & n1907; + assign n1833 = n2305 & n2179 & n2031 & n1947 & n1940 & n1917 & ~n111 & n432; + assign n1834 = ~n571 | n2210; + assign n1835 = ~n571 | n1112; + assign n1836 = ~n113 | n1375; + assign n1837 = n415 & n256; + assign n1838 = ~n113 | n822; + assign n1839 = ~n113 | n1113; + assign n1840 = n495 & n1125; + assign n1841 = n291 & ~n930; + assign n1842 = ~n113 | n2369; + assign n1843 = ~n113 | n910; + assign n1844 = ~n113 | n2376; + assign n1845 = ~n113 | n1125; + assign n1846 = ~n113 | n495; + assign n1847 = ~n104 | n362; + assign n1848 = ~n107 | n1125; + assign n1849 = ~n104 | n495; + assign n1850 = ~n104 | n1207; + assign n1851 = ~n104 | n474; + assign n1852 = ~n104 | n1125; + assign n1853 = ~n104 | n709; + assign n1854 = ~n113 | n2375; + assign n1855 = n1854 & n1069 & n1071; + assign n1856 = ~n97 | n1374; + assign n1857 = ~n97 | n1224; + assign n1858 = ~n97 | n798; + assign n1859 = n1858 & n1856 & n1857; + assign n1860 = ~n96 | n330; + assign n1861 = n1025 & n1684 & n1022 & n1859; + assign n1862 = n1861 & n1670 & n1192 & n1810 & n1860 & n1809; + assign n1863 = ~n571 | n1139; + assign n1864 = ~n113 | n1138; + assign n1865 = n2337 & n2082 & n2170 & n2107 & n2146 & n2138; + assign n1866 = n739 & n749; + assign n1867 = n684 & n306; + assign n1868 = n266 & n495; + assign n1869 = n441 & n658; + assign n1870 = n284 & n212; + assign n1871 = ~n98 | n474; + assign n1872 = ~n165 | n1261; + assign n1873 = ~n165 | n356; + assign n1874 = ~n165 | n206; + assign n1875 = ~n165 | n227; + assign n1876 = ~n404 | n1261; + assign n1877 = ~n165 | n1207; + assign n1878 = n226 | ~n404; + assign n1879 = n227 | ~n404; + assign n1880 = n206 | ~n404; + assign n1881 = n251 | ~n404; + assign n1882 = ~n404 | n474; + assign n1883 = ~n404 | n1157; + assign n1884 = ~n404 | n1207; + assign n1885 = n356 | ~n404; + assign n1886 = ~n404 | n1248; + assign n1887 = ~n107 | n444; + assign n1888 = ~n167 | n206; + assign n1889 = ~n104 | n226; + assign n1890 = n331 | ~n571; + assign n1891 = ~n163 | n926; + assign n1892 = n1551 & n1191 & n1511 & n1530 & n1540 & n1891; + assign n1893 = ~n98 | n879; + assign n1894 = ~n165 | n875; + assign n1895 = ~n165 | n284; + assign n1896 = n1895 & n1503 & n1524 & n1894 & n1667 & n1704; + assign n1897 = ~n163 | n674; + assign n1898 = ~n163 | n879; + assign n1899 = ~n404 | n979; + assign n1900 = ~n404 | n508; + assign n1901 = n284 | ~n404; + assign n1902 = ~n404 | n674; + assign n1903 = n309 | ~n404; + assign n1904 = n1903 & n1902 & n1901 & n1774 & n1899 & n1900; + assign n1905 = ~n167 | n1293; + assign n1906 = ~n404 | n1262; + assign n1907 = ~n104 | n674; + assign n1908 = (~n163 | n191) & (~n167 | n527); + assign n1909 = n999 & (n327 | (n1295 & n1294)); + assign n1910 = n293 | n875; + assign n1911 = ~n96 | n191; + assign n1912 = ~n96 | n527; + assign n1913 = ~n278 | n926; + assign n1914 = n191 | ~n278; + assign n1915 = ~n96 | n979; + assign n1916 = ~n107 | n1105; + assign n1917 = ~n107 | n287; + assign n1918 = ~n167 | n926; + assign n1919 = ~n167 | n284; + assign n1920 = ~n107 | n309; + assign n1921 = ~n107 | n926; + assign n1922 = ~n107 | n284; + assign n1923 = (n1649 | n911) & (n292 | n267); + assign n1924 = n291 & ~n453; + assign n1925 = n327 & ~n404; + assign n1926 = (n306 | n1925) & (n266 | ~n344); + assign n1927 = n190 | ~n278; + assign n1928 = ~n97 | n316; + assign n1929 = ~n278 | n317; + assign n1930 = n1929 & n1633 & n1586; + assign n1931 = n206 | ~n278; + assign n1932 = ~n278 | n1157; + assign n1933 = ~n167 | n251; + assign n1934 = ~n167 | n822; + assign n1935 = ~n167 | n216; + assign n1936 = ~n278 | n316; + assign n1937 = n216 | ~n278; + assign n1938 = n997 & n1937 & n1936 & n1935 & n1933 & n1934; + assign n1939 = ~n167 | n1207; + assign n1940 = ~n107 | n317; + assign n1941 = n1938 & n1014 & n1940 & n1939 & n1770 & n1768; + assign n1942 = ~n113 | n316; + assign n1943 = n1091 & n1942 & (n316 | ~n353); + assign n1944 = n1274 & (~n107 | n206); + assign n1945 = ~n107 | n1157; + assign n1946 = ~n107 | n822; + assign n1947 = ~n107 | n356; + assign n1948 = ~n107 | n216; + assign n1949 = ~n278 | n1261; + assign n1950 = n226 | ~n278; + assign n1951 = ~n96 | n226; + assign n1952 = n227 | ~n278; + assign n1953 = ~n97 | n822; + assign n1954 = ~n96 | n1261; + assign n1955 = ~n97 | n227; + assign n1956 = ~n167 | n1261; + assign n1957 = ~n113 | n1157; + assign n1958 = ~n113 | n1870; + assign n1959 = ~n96 | n774; + assign n1960 = n1959 & n1188; + assign n1961 = ~n97 | n2370; + assign n1962 = n1960 & n1961 & n835 & n1492 & n503 & n1466 & n1459 & n858; + assign n1963 = ~n278 | n331; + assign n1964 = n1963 & n1723 & n1727; + assign n1965 = ~n167 | n755; + assign n1966 = ~n167 | n1250; + assign n1967 = ~n167 | n774; + assign n1968 = ~n353 & ~n253 & ~n96 & ~n167; + assign n1969 = ~n165 | n334; + assign n1970 = n331 | ~n404; + assign n1971 = n1386 & n872 & n742 & n832 & n1515 & n1495 & n1969 & n1970; + assign n1972 = n339 | n341 | n342 | n345 | ~n1854 | ~n1971 | ~n1049 | ~n1835; + assign n1973 = (n291 | n337) & (~n354 | n1866); + assign n1974 = (n332 | n1292) & (~n453 | n1731); + assign n1975 = ~n360 & n1974 & (~n116 | n308); + assign n1976 = (n310 | ~n571) & (~n107 | n307); + assign n1977 = n1975 & n1976 & (~n348 | n1310); + assign n1978 = (n1291 | n674) & (n1925 | n604); + assign n1979 = (n289 | n327) & (~n351 | n610); + assign n1980 = (~n113 | n1112) & (~n346 | n687); + assign n1981 = n1980 & (~n268 | ~n404); + assign n1982 = (~n253 | n536) & (n330 | ~n930); + assign n1983 = (~n163 | n190) & (~n167 | n191); + assign n1984 = n1981 & n1978 & n1979 & n1982 & n1983 & n315 & n328 & n335; + assign n1985 = n192 & n196 & n199 & n207 & n210 & n1329 & n202; + assign n1986 = n1985 & n213 & n1325 & n262 & n303 & n1316 & n551 & n277; + assign n1987 = n334 & n1222; + assign n1988 = (n481 | n1042) & (~n116 | n1203); + assign n1989 = (n1042 | n1211) & (~n899 | n1222); + assign n1990 = n1446 | n459; + assign n1991 = ~n96 | n430; + assign n1992 = ~n97 | n430; + assign n1993 = n1992 & n1559 & n1545 & n1991 & n1581 & n1580 & n1583 & n1584; + assign n1994 = ~n278 | n1330; + assign n1995 = ~n278 | n472; + assign n1996 = ~n278 | n1335; + assign n1997 = ~n167 | n441; + assign n1998 = ~n278 | n1337; + assign n1999 = ~n278 | n430; + assign n2000 = ~n167 | n1337; + assign n2001 = ~n167 | n430; + assign n2002 = ~n167 | n1082; + assign n2003 = n591 & n644 & n311; + assign n2004 = ~n98 | ~n450; + assign n2005 = n2003 & n193 & n1561 & n615 & n189 & n2004 & n661 & n1424; + assign n2006 = n743 & n1460 & n1463 & n1485; + assign n2007 = n607 & n603 & n1189 & n791; + assign n2008 = n2007 & n1421 & n1328 & n600 & n1470 & n596; + assign n2009 = n1494 & n786 & n779; + assign n2010 = ~n165 | n1224; + assign n2011 = ~n98 | n1346; + assign n2012 = ~n97 | n2373; + assign n2013 = n2008 & n2009 & n1514 & n623 & n2012 & n2011 & n1698 & n2010; + assign n2014 = ~n165 | n440; + assign n2015 = ~n404 | n1155; + assign n2016 = n535 & n2014 & n2015; + assign n2017 = ~n120 & (n1292 | (n489 & n1155)); + assign n2018 = n2017 & n1736 & n1285 & n647 & ~n455 & ~n454 & ~n451 & ~n452; + assign n2019 = ~n104 | n440; + assign n2020 = ~n404 | n440; + assign n2021 = (n440 | ~n633) & (n1341 | n1925); + assign n2022 = (~n349 | n1248) & (~n382 | n1138); + assign n2023 = (~n294 | n445) & (n539 | n1097); + assign n2024 = ~n96 | n1348; + assign n2025 = (~n346 | n1151) & (~n348 | n444); + assign n2026 = n2025 & (~n98 | n1207); + assign n2027 = ~n97 | n1138; + assign n2028 = n1426 & n665 & n2027 & n1427 & n1449 & n1458 & n1491 & n1465; + assign n2029 = ~n278 | n1155; + assign n2030 = ~n113 | n1097; + assign n2031 = ~n107 | n1097; + assign n2032 = ~n167 | n1341; + assign n2033 = ~n167 | n1151; + assign n2034 = ~n167 | n440; + assign n2035 = ~n278 | n1145; + assign n2036 = ~n107 & ~n353; + assign n2037 = n1490 & n1563 & n1481; + assign n2038 = ~n163 | n1337; + assign n2039 = ~n163 | n430; + assign n2040 = n2038 & n2039; + assign n2041 = ~n163 | n1330; + assign n2042 = ~n163 | n1082; + assign n2043 = n2040 & n1528 & n2042 & n1543 & n1538 & n1550 & n2041 & n1508; + assign n2044 = ~n98 | n709; + assign n2045 = ~n98 | n1335; + assign n2046 = ~n163 | n709; + assign n2047 = ~n163 | n1335; + assign n2048 = n2047 & n2046 & n1500 & n1523; + assign n2049 = n2048 & n1629 & n1566 & n1575 & n1576 & n1592; + assign n2050 = ~n165 | n473; + assign n2051 = n1702 & n2050 & n1668; + assign n2052 = ~n165 | n709; + assign n2053 = ~n165 | n471; + assign n2054 = ~n165 | n441; + assign n2055 = ~n404 | n471; + assign n2056 = ~n404 | n1082; + assign n2057 = n2055 & n2056; + assign n2058 = ~n167 | n1336; + assign n2059 = ~n404 | n441; + assign n2060 = ~n404 | n1330; + assign n2061 = n2057 & n2060 & n2059 & n2058 & n1023 & n1740 & n1672 & n1679; + assign n2062 = ~n404 | n1335; + assign n2063 = ~n404 | n1334; + assign n2064 = n392 | ~n404; + assign n2065 = n2064 & n2062 & n2063; + assign n2066 = ~n104 | n1082; + assign n2067 = ~n104 | n472; + assign n2068 = ~n107 | n393; + assign n2069 = n2068 & n1853 & n2067 & n1744; + assign n2070 = ~n167 | n473; + assign n2071 = (~n107 | n392) & (~n404 | n473); + assign n2072 = ~n96 & ~n404; + assign n2073 = (~n295 | n1082) & (n1337 | n2072); + assign n2074 = (~n381 | n472) & (~n382 | n441); + assign n2075 = ~n278 | n495; + assign n2076 = ~n278 | n684; + assign n2077 = ~n353 | n361; + assign n2078 = ~n167 | n684; + assign n2079 = ~n278 | n1333; + assign n2080 = ~n278 | n361; + assign n2081 = ~n278 | n566; + assign n2082 = ~n113 | n566; + assign n2083 = ~n113 | n489; + assign n2084 = ~n167 | n1333; + assign n2085 = n2084 & n1657 & n1655 & n1814 & n2083 & n1759 & n2082 & n1766; + assign n2086 = (~n107 | n363) & (~n278 | n1138); + assign n2087 = ~n107 | n1333; + assign n2088 = ~n163 | n684; + assign n2089 = ~n163 | n1333; + assign n2090 = ~n163 | n685; + assign n2091 = n2090 & n1541 & n2089 & n724 & n1512 & n1549 & n2088; + assign n2092 = ~n163 | n495; + assign n2093 = ~n163 | n426; + assign n2094 = ~n163 | n362; + assign n2095 = ~n404 | n426; + assign n2096 = ~n167 | n656; + assign n2097 = n1742 & n1722 & n1734 & n1775 & n2095 & n2096; + assign n2098 = ~n165 | n447; + assign n2099 = ~n165 | n500; + assign n2100 = ~n165 | n362; + assign n2101 = ~n165 | n845; + assign n2102 = ~n107 | n1331; + assign n2103 = n2102 & n1745 & n1780 & n1107 & n1847 & n1849; + assign n2104 = n911 | n489; + assign n2105 = ~n104 | n426; + assign n2106 = ~n167 | n447; + assign n2107 = ~n571 | n1138; + assign n2108 = ~n162 & (~n930 | (n656 & n685)); + assign n2109 = (n323 | n495) & (~n346 | n684); + assign n2110 = ~n383 & (n447 | (~n113 & ~n278)); + assign n2111 = (~n404 | n1408) & (n1333 | n2072); + assign n2112 = n485 & n1005 & (~n294 | n475); + assign n2113 = ~n476 & (n327 | (n430 & n729)); + assign n2114 = (~n349 | n529) & (n291 | n1404); + assign n2115 = n1291 | n1082; + assign n2116 = (~n96 | n495) & (~n359 | n489); + assign n2117 = n2116 & (n481 | n459); + assign n2118 = n226 | ~n897; + assign n2119 = ~n98 | n682; + assign n2120 = ~n98 | n1125; + assign n2121 = n734 & n2120 & n2119 & n1480 & n1562 & n771 & n1489; + assign n2122 = ~n163 | n504; + assign n2123 = ~n163 | n1028; + assign n2124 = ~n163 | n592; + assign n2125 = ~n163 | n682; + assign n2126 = ~n163 | n1125; + assign n2127 = ~n163 | n653; + assign n2128 = n957 & n1486 & n1696 & n2127 & n2126 & n1522 & n2125; + assign n2129 = ~n165 | n592; + assign n2130 = ~n404 | n567; + assign n2131 = ~n404 | n1372; + assign n2132 = ~n404 | n499; + assign n2133 = n911 | n1372; + assign n2134 = n2133 & n1821 & n1799 & n1739 & n2132 & n2130 & n2131; + assign n2135 = n911 | n528; + assign n2136 = ~n104 | n567; + assign n2137 = ~n104 | n984; + assign n2138 = ~n571 | n984; + assign n2139 = (~n381 | n682) & (n910 | n1841); + assign n2140 = ~n278 | n1027; + assign n2141 = n2140 & ~n101 & ~n111; + assign n2142 = ~n113 | n1084; + assign n2143 = ~n278 | n2376; + assign n2144 = ~n107 | n2371; + assign n2145 = ~n113 | n1796; + assign n2146 = ~n113 | n1139; + assign n2147 = n1006 & n2146 & (~n167 | n362); + assign n2148 = ~n97 | n1125; + assign n2149 = ~n96 | n499; + assign n2150 = ~n97 | n1176; + assign n2151 = n1493 & n1558 & n2150 & n1553 & n2148 & n2149; + assign n2152 = ~n96 | n984; + assign n2153 = ~n278 | n1028; + assign n2154 = ~n96 | n1373; + assign n2155 = n2151 & n1634 & n1591 & n2154 & n2153 & n2152 & n1700; + assign n2156 = ~n278 | n567; + assign n2157 = ~n278 | n1125; + assign n2158 = ~n278 | n1373; + assign n2159 = n2158 & n2157 & n1724 & n1718 & n2156 & n945; + assign n2160 = ~n167 | n1028; + assign n2161 = ~n353 | n1373; + assign n2162 = ~n353 | n1176; + assign n2163 = ~n278 | n1176; + assign n2164 = ~n167 | n1372; + assign n2165 = ~n167 | n1125; + assign n2166 = ~n107 | n567; + assign n2167 = ~n113 | n1372; + assign n2168 = ~n107 | n984; + assign n2169 = ~n107 | n1373; + assign n2170 = ~n113 | n567; + assign n2171 = n667 & n666 & n1425; + assign n2172 = n783 & n1520 & n1498; + assign n2173 = n1205 | ~n1388; + assign n2174 = ~n278 | n951; + assign n2175 = ~n167 | n530; + assign n2176 = ~n278 | n521; + assign n2177 = ~n167 | n522; + assign n2178 = n2177 & n2175 & n2176; + assign n2179 = ~n107 | n540; + assign n2180 = ~n113 | n540; + assign n2181 = ~n167 | n1375; + assign n2182 = ~n928 | n1663; + assign n2183 = (~n278 | n653) & (n675 | n926); + assign n2184 = n533 & n879 & n504; + assign n2185 = n1200 | ~n1379; + assign n2186 = n620 & n194; + assign n2187 = n2186 & n645 & n312 & n616 & n214 & n1423 & n203 & n662; + assign n2188 = n1856 & n1535 & n1462 & n741; + assign n2189 = n1616 & n1469 & n1488; + assign n2190 = n1190 & n792 & n787 & n776 & n842 & n622 & n1287 & n1653; + assign n2191 = n2190 & n2189 & n595 & n599 & n1327 & n625 & n606 & n602; + assign n2192 = ~n98 | n522; + assign n2193 = ~n165 | n530; + assign n2194 = ~n165 | n1374; + assign n2195 = n1738 & n2193 & n2194; + assign n2196 = ~n104 | n530; + assign n2197 = n2196 & n1324 & ~n117 & n609; + assign n2198 = n1757 & (~n354 | (n191 & n1373)); + assign n2199 = ~n542 & (~n453 | (n526 & n1374)); + assign n2200 = (~n97 | n520) & (n680 | n910); + assign n2201 = (n327 | n524) & (~n294 | n531); + assign n2202 = ~n404 | n530; + assign n2203 = (~n165 | n525) & (~n340 | n951); + assign n2204 = (n309 | ~n348) & (~n359 | n528); + assign n2205 = n1863 & (~n930 | (n1293 & n1378)); + assign n2206 = n2205 & (~n359 | (n521 & n1176)); + assign n2207 = ~n582 & (n1292 | (n1294 & n1404)); + assign n2208 = ~n583 & (~n571 | (n536 & n1084)); + assign n2209 = (n285 | n875) & (~n104 | n1295); + assign n2210 = n508 & n467; + assign n2211 = (n288 | ~n346) & (n251 | ~n340); + assign n2212 = (~n97 | n216) & (~n165 | n508); + assign n2213 = n297 & n2212 & n380 & n325; + assign n2214 = n490 & n492 & n496; + assign n2215 = n1533 & n1447; + assign n2216 = ~n96 | n1026; + assign n2217 = ~n167 | n777; + assign n2218 = ~n167 | n793; + assign n2219 = ~n167 | n654; + assign n2220 = ~n278 | n651; + assign n2221 = (~n107 | n632) & (n1417 | n1968); + assign n2222 = ~n107 | n2372; + assign n2223 = ~n107 | n651; + assign n2224 = ~n107 | n1666; + assign n2225 = n2224 & n2223 & n2222 & n2221 & n1760 & n1070 & ~n110 & ~n634; + assign n2226 = (n1259 | ~n1388) & (~n253 | n793); + assign n2227 = n491 & (~n404 | (n682 & n1407)); + assign n2228 = ~n163 | n629; + assign n2229 = n2228 & n1699 & n1384 & n1326 & n1278 & n870 & ~n100 & n840; + assign n2230 = ~n104 | n1416; + assign n2231 = ~n104 | n629; + assign n2232 = n2231 & n2230 & n1758 & n1323 & n1289 & n1284 & ~n106 & n1118; + assign n2233 = (~n321 | n686) & (~n344 | n689); + assign n2234 = ~n690 & (~n404 | (n687 & n793)); + assign n2235 = ~n691 & (~n163 | (n651 & n1311)); + assign n2236 = ~n692 & (n597 | (~n167 & ~n930)); + assign n2237 = ~n693 & (n468 | n1309) & n2236; + assign n2238 = ~n344 & ~n353; + assign n2239 = (n304 | ~n346) & (n1333 | n2238); + assign n2240 = n2237 & n2239 & (~n354 | n1429); + assign n2241 = n2240 & n2235 & n2234 & n2233 & n2232 & n2229 & ~n169 & n1858; + assign n2242 = (n681 | n777) & (~n338 | n1417); + assign n2243 = (~n294 | n659) & (~n348 | n660); + assign n2244 = (~n268 | ~n381) & (n327 | n655); + assign n2245 = (~n253 | n330) & (~n453 | n798); + assign n2246 = (~n113 | n313) & (n291 | n447); + assign n2247 = (~n97 | n362) & (~n98 | n610); + assign n2248 = (~n104 | n265) & (n738 | n911); + assign n2249 = n248 & (n941 | ~n1379); + assign n2250 = n2242 & n2243 & n2244 & n2245 & n2246 & n2247 & n2249 & n2248; + assign n2251 = n391 & n277 & n683 & n550 & n672 & n1433 & n1438 & n643; + assign n2252 = n2251 & n594 & n598 & n601 & n1440 & n614 & n608 & n605; + assign n2253 = (~n107 | n1405) & (~n167 | n1406); + assign n2254 = (~n404 | n519) & (n710 | n1309); + assign n2255 = n2254 & (n357 | n471); + assign n2256 = ~n321 & ~n346; + assign n2257 = (n2256 | n910) & (n2238 | n1337); + assign n2258 = (~n294 | n708) & (~n571 | n1086); + assign n2259 = (~n97 | n429) & (~n321 | n1405); + assign n2260 = n2259 & (n327 | n1347); + assign n2261 = n2260 & n2257 & n2258 & n2255 & n863 & n446 & n1351 & n1350; + assign n2262 = (~n344 | n1334) & (~n348 | n707); + assign n2263 = n1040 & n2262 & (~n343 | n521); + assign n2264 = (~n96 | n1176) & (~n165 | n536); + assign n2265 = n2264 & n2263 & (n481 | n1234); + assign n2266 = n2265 & n697 & n1445 & n706 & n303 & n412 & n614 & n549; + assign n2267 = n1236 & n172 & ~n1233; + assign n2268 = n2039 & n1857 & n1856; + assign n2269 = n1272 & n233 & n1911; + assign n2270 = n486 & ~n800 & (~n163 | n799); + assign n2271 = (~n97 | n763) & (~n98 | n330); + assign n2272 = n1421 & n218 & n827; + assign n2273 = n196 & (~n97 | n195); + assign n2274 = n2273 & n814 & ~n813 & ~n812 & n496 & n492 & n428 & n490; + assign n2275 = n626 & n624; + assign n2276 = ~n1233 & n1237; + assign n2277 = ~n1612 | n181 | n820 | n2276 | n1646 | ~n1858; + assign n2278 = n826 & (n459 | (n481 & n474)); + assign n2279 = n565 & n217 & n881 & n806 & n808 & n807; + assign n2280 = n2279 & n2216 & n1955 & n1928 & ~n878 & ~n877 & n422 & n503; + assign n2281 = n854 & n862 & n866 & n1644 & n1643 & n838; + assign n2282 = n2281 & n1641 & n868 & n1640 & n1636 & n1632 & n1637 & n1638; + assign n2283 = n1251 & ~n122 & ~n136; + assign n2284 = (~n899 | ~n900) & (~n1608 | n2283); + assign n2285 = n1648 & ~n132 & n884; + assign n2286 = ~n1237 | n2283; + assign n2287 = n2286 & (n459 | (n474 & ~n819)); + assign n2288 = n731 & n728 & n2012 & n2011 & n920 & n1858 & n922 & n1455; + assign n2289 = n506 & n1430; + assign n2290 = n2099 & n2076 & n2153; + assign n2291 = n2140 & (~n930 | (n755 & n1418)); + assign n2292 = (~n165 | n426) & (~n278 | n287); + assign n2293 = n2185 & n2173 & n1952; + assign n2294 = n2293 & n2158 & n1969 & n2193 & n2014 & n2035 & n2176 & n1950; + assign n2295 = n2163 & n243 & n2080; + assign n2296 = (~n165 | n971) & (~n278 | n966); + assign n2297 = n749 & n1161; + assign n2298 = n1420 & (~n930 | n2297); + assign n2299 = n1876 & n2160 & n2078 & n2032 & n2177 & n2218; + assign n2300 = n2175 & n2164 & n1439; + assign n2301 = n2084 & n2001 & n1918; + assign n2302 = n2301 & n2000 & n1935 & n1118 & ~n1039 & ~n1037 & ~n168 & n995; + assign n2303 = n150 & n228 & (~n167 | n362); + assign n2304 = n2303 & n1764 & n1036 & n1783 & n1011 & n1779 & n1020 & n1772; + assign n2305 = (~n104 | n1087) & (~n107 | n1077); + assign n2306 = n1640 & n1195 & n811 & n1808 & n1036 & n963; + assign n2307 = n688 & n1380; + assign n2308 = n742 & n1453 & n1959 & n1419 & n1932 & n1682 & n2014 & n2193; + assign n2309 = n2256 | n969; + assign n2310 = ~n1099 & (~n404 | (n287 & n1087)); + assign n2311 = ~n107 | n1046; + assign n2312 = n2310 & n2311 & n2223; + assign n2313 = (n292 | n1098) & (n1349 | n1097); + assign n2314 = (~n104 | ~n109) & (~n354 | n739); + assign n2315 = (~n165 | n263) & (~n571 | n1136); + assign n2316 = (n317 | ~n346) & (n305 | ~n453); + assign n2317 = (~n98 | n774) & (n195 | n1292); + assign n2318 = n2312 & n2313 & n2314 & n2315 & n2316 & n2317 & n669 & n541; + assign n2319 = n1454 & n1433 & n785 & n746 & n841 & n831 & n1638 & n140; + assign n2320 = n993 & n1721 & n1096 & n1772 & n1168 & n1094 & n1076 & n1059; + assign n2321 = (~n294 | n654) & (~n929 | n1141); + assign n2322 = (~n165 | n1331) & (~n404 | n566); + assign n2323 = n2321 & n2322 & n1496 & n1516 & n1636 & n1526; + assign n2324 = n244 & n1478 & n1479 & n673 & n842 & n1915; + assign n2325 = ~n1128 & (~n340 | (n921 & n1335)); + assign n2326 = ~n1129 & (~n571 | (n1207 & n1840)); + assign n2327 = n2326 & (n1152 | (~n116 & n1841)); + assign n2328 = (~n346 | n1840) & (~n928 | n1126); + assign n2329 = (n362 | ~n381) & (n266 | n539); + assign n2330 = (n291 | n1250) & (n292 | n264); + assign n2331 = n2329 & n2330 & (n1292 | n879); + assign n2332 = n2331 & n2327 & n2328 & n2324 & n2325 & n2082 & n2170 & n2222; + assign n2333 = n510 & n1274 & (~n404 | n709); + assign n2334 = n2333 & n1411 & n745 & n760 & n1618 & n1518 & n1505 & n753; + assign n2335 = n938 & n1637 & n141; + assign n2336 = n2335 & n1020 & n992 & n1170 & n1183 & n1124 & n1804 & n1076; + assign n2337 = ~n113 | n1869; + assign n2338 = n2149 & n1451 & n1460 & n957 & n2099 & n1912; + assign n2339 = n1431 & (~n571 | n1142); + assign n2340 = (~n404 | n1140) & (n313 | n1924); + assign n2341 = (~n321 | n1156) & (n651 | n1349); + assign n2342 = n2341 & (~n349 | n1374); + assign n2343 = n2340 & n2342 & (n1662 | n509); + assign n2344 = (~n382 | n798) & (n323 | n951); + assign n2345 = n2344 & (~n294 | n1224); + assign n2346 = n1282 & (n292 | n334); + assign n2347 = n2343 & n2345 & n2346 & n2338 & n2339 & n1825 & n2145 & n2132; + assign n2348 = n517 & n418 & n335 & n1483 & n560 & n1438; + assign n2349 = n2348 & n1643 & n801 & n1532 & n780 & n1521; + assign n2350 = n987 & n949 & n975; + assign n2351 = n2350 & n1081 & n1011 & n1135 & n1182 & n1862 & n1059 & n1124; + assign n2352 = n2311 & n1517 & n946 & ~n114 & ~n108 & ~n112; + assign n2353 = ~n113 | n1143; + assign n2354 = n2353 & n2352 & n2337 & n1839 & ~n118 & n506; + assign n2355 = (~n97 | n1154) & (~n107 | n1153); + assign n2356 = n2355 & (~n113 | n1150); + assign n2357 = (~n167 | n1146) & (~n278 | n1148); + assign n2358 = n2357 & (~n96 | n1145); + assign n2359 = n2354 & n2356 & n2358 & n1414 & n678 & n424 & n372 & n262; + assign n2360 = n735 & n697 & n643 & n794 & n732 & n772; + assign n2361 = n2360 & n849 & n841 & n843 & n833 & n1627; + assign n2362 = n1630 & n874 & n871; + assign n2363 = n2362 & n1032 & n1004 & n1862 & n1855 & n1103 & n1787 & n1051; + assign n2364 = n1389 & n1317 & n1948; + assign n2365 = (~n107 | n1167) & (n1164 | n1292); + assign n2366 = n2083 & n1314 & n2167 & n627 & n1890 & n1048; + assign n2367 = n2353 & (~n294 | (n1149 & n1506)); + assign n2368 = n471 & n426 & n356; + assign n2369 = n1207 & n921; + assign n2370 = n206 & n762; + assign n2371 = n845 & n875 & n441; + assign n2372 = n682 & n266 & n495; + assign n2373 = n1207 & n470; + assign n2374 = n1293 & n469; + assign n2375 = n527 & n209; + assign n2376 = n879 & n470; + assign n2377 = n894 | n126; + assign n2378 = n906 | n126; + assign n2379 = n480 | n126; + assign n2380 = n590 | n126; + assign n2381 = n1259 & n1211 & ~i_12_ & n216; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v b/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v new file mode 100644 index 000000000..172950b5e --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v @@ -0,0 +1,69 @@ +// Benchmark "s298.bench" written by ABC on Tue Mar 5 10:03:54 2019 + +module s298 ( clock, + G0, G1, G2, + G117, G132, G66, G118, G133, G67 ); + input G0, G1, G2, clock; + output G117, G132, G66, G118, G133, G67; + reg G10, G11, G12, G13, G14, G15, G16, G17, G18, G19, G20, G21, G22, G23; + wire n57, n59, n64, n66, n21_1, n26_1, n31_1, n36_1, n41_1, n46_1, n51_1, + n56_1, n61_1, n66_2, n71_1, n76_1, n81_1, n86_1; + assign n21_1 = ~G0 & ~G10; + assign n26_1 = ~G0 & (G10 ? (~G11 & (G12 | ~G13)) : G11); + assign n31_1 = ~G0 & ((G12 & (~G10 | ~G11)) | (G10 & G11 & ~G12)); + assign n36_1 = ~G0 & ((G11 & ((~G12 & G13) | (G10 & G12 & ~G13))) | (G13 & (~G10 | (~G11 & G12)))); + assign n41_1 = ~G0 & (G14 ^ (G23 | (G10 & G13 & n57))); + assign n57 = ~G11 & ~G12; + assign n46_1 = ~G0 & ~n59; + assign n59 = (G11 & (~G15 | (~G12 & G13 & ~G14 & ~G22))) | (~G15 & (G12 | ~G13 | G14 | ~G22)); + assign n51_1 = n59 & ((G13 & (~G14 | G16)) | (G12 & G14 & G16)); + assign n56_1 = n59 & ((~G13 & (G11 ? ~G12 : ~G14)) | (G14 & G17 & (G12 | G13))); + assign n61_1 = n59 & ((G14 & G18 & (G12 | G13)) | (~G13 & (~G14 | (G11 & ~G12)))); + assign n66_2 = n59 ? n64 : ~G10; + assign n64 = (G13 & (~G14 | G19)) | (G14 & ((~G11 & ~G12 & ~G13) | (G12 & G19))); + assign n71_1 = n59 ? (n66 & (G20 | (~G12 & ~G13))) : ~G10; + assign n66 = G14 & (~G11 | G12 | G13); + assign n76_1 = n59 & ((G12 & ((G11 & ~G13 & ~G14) | (G14 & G21))) | (G13 & G14 & G21)); + assign n81_1 = ~G0 & (G2 ^ G22); + assign n86_1 = ~G0 & (G1 ^ G23); + assign G117 = G18; + assign G132 = G20; + assign G66 = G16; + assign G118 = G19; + assign G133 = G21; + assign G67 = G17; + always @ (posedge clock) begin + G10 <= n21_1; + G11 <= n26_1; + G12 <= n31_1; + G13 <= n36_1; + G14 <= n41_1; + G15 <= n46_1; + G16 <= n51_1; + G17 <= n56_1; + G18 <= n61_1; + G19 <= n66_2; + G20 <= n71_1; + G21 <= n76_1; + G22 <= n81_1; + G23 <= n86_1; + end + initial begin + G10 <= 1'b0; + G11 <= 1'b0; + G12 <= 1'b0; + G13 <= 1'b0; + G14 <= 1'b0; + G15 <= 1'b0; + G16 <= 1'b0; + G17 <= 1'b0; + G18 <= 1'b0; + G19 <= 1'b0; + G20 <= 1'b0; + G21 <= 1'b0; + G22 <= 1'b0; + G23 <= 1'b0; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v b/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v new file mode 100644 index 000000000..3dc99f65b --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v @@ -0,0 +1,6731 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 10:04:28 2019 + +module s38417 ( clock, + Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227, Pg3226, + Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218, Pg3217, + Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249, Pg563, + Pg51, + Pg27380, Pg26149, Pg26135, Pg26104, Pg25489, Pg25442, Pg25435, Pg25420, + Pg24734, Pg16496, Pg16437, Pg16399, Pg16355, Pg16297, Pg8275, Pg8274, + Pg8273, Pg8272, Pg8271, Pg8270, Pg8269, Pg8268, Pg8267, Pg8266, Pg8265, + Pg8264, Pg8263, Pg8262, Pg8261, Pg8260, Pg8259, Pg8258, Pg8251, Pg8249, + Pg8175, Pg8167, Pg8106, Pg8096, Pg8087, Pg8082, Pg8030, Pg8023, Pg8021, + Pg8012, Pg8007, Pg7961, Pg7956, Pg7909, Pg7519, Pg7487, Pg7425, Pg7390, + Pg7357, Pg7334, Pg7302, Pg7264, Pg7229, Pg7194, Pg7161, Pg7084, Pg7052, + Pg7014, Pg6979, Pg6944, Pg6911, Pg6895, Pg6837, Pg6782, Pg6750, Pg6712, + Pg6677, Pg6642, Pg6573, Pg6518, Pg6485, Pg6447, Pg6442, Pg6368, Pg6313, + Pg6231, Pg6225, Pg5796, Pg5747, Pg5738, Pg5695, Pg5686, Pg5657, Pg5648, + Pg5637, Pg5629, Pg5612, Pg5595, Pg5555, Pg5549, Pg5511, Pg5472, Pg5437, + Pg5388, Pg4590, Pg4450, Pg4323, Pg4321, Pg4200, Pg4090, Pg4088, Pg3993 ); + input Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227, + Pg3226, Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218, + Pg3217, Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249, + Pg563, Pg51, clock; + output Pg27380, Pg26149, Pg26135, Pg26104, Pg25489, Pg25442, Pg25435, + Pg25420, Pg24734, Pg16496, Pg16437, Pg16399, Pg16355, Pg16297, Pg8275, + Pg8274, Pg8273, Pg8272, Pg8271, Pg8270, Pg8269, Pg8268, Pg8267, Pg8266, + Pg8265, Pg8264, Pg8263, Pg8262, Pg8261, Pg8260, Pg8259, Pg8258, Pg8251, + Pg8249, Pg8175, Pg8167, Pg8106, Pg8096, Pg8087, Pg8082, Pg8030, Pg8023, + Pg8021, Pg8012, Pg8007, Pg7961, Pg7956, Pg7909, Pg7519, Pg7487, Pg7425, + Pg7390, Pg7357, Pg7334, Pg7302, Pg7264, Pg7229, Pg7194, Pg7161, Pg7084, + Pg7052, Pg7014, Pg6979, Pg6944, Pg6911, Pg6895, Pg6837, Pg6782, Pg6750, + Pg6712, Pg6677, Pg6642, Pg6573, Pg6518, Pg6485, Pg6447, Pg6442, Pg6368, + Pg6313, Pg6231, Pg6225, Pg5796, Pg5747, Pg5738, Pg5695, Pg5686, Pg5657, + Pg5648, Pg5637, Pg5629, Pg5612, Pg5595, Pg5555, Pg5549, Pg5511, Pg5472, + Pg5437, Pg5388, Pg4590, Pg4450, Pg4323, Pg4321, Pg4200, Pg4090, Pg4088, + Pg3993; + reg Pg8021, Ng2817, Ng2933, Ng13457, Ng2883, Ng2888, Ng2896, Ng2892, + Ng2903, Ng2900, Ng2908, Ng2912, Ng2917, Ng2924, Ng2920, Ng2984, Ng2985, + Ng2929, Ng2879, Ng2934, Ng2935, Ng2938, Ng2941, Ng2944, Ng2947, Ng2953, + Ng2956, Ng2959, Ng2962, Ng2963, Ng2966, Ng2969, Ng2972, Ng2975, Ng2978, + Ng2981, Ng2874, Ng1506, Ng1501, Ng1496, Ng1491, Ng1486, Ng1481, Ng1476, + Ng1471, Ng13439, Pg8251, Ng813, Pg4090, Ng809, Pg4323, Ng805, Pg4590, + Ng801, Pg6225, Ng797, Pg6442, Ng793, Pg6895, Ng789, Pg7334, Ng785, + Pg7519, Ng13423, Pg8249, Ng125, Pg4088, Ng121, Pg4321, Ng117, Pg8023, + Ng113, Pg8175, Ng109, Pg3993, Ng105, Pg4200, Ng101, Pg4450, Ng97, + Pg8096, Ng13407, Ng2200, Ng2195, Ng2190, Ng2185, Ng2180, Ng2175, + Ng2170, Ng2165, Ng13455, Ng3210, Ng3211, Ng3084, Ng3085, Ng3086, + Ng3087, Ng3091, Ng3092, Ng3093, Ng3094, Ng3095, Ng3096, Ng3097, Ng3098, + Ng3099, Ng3100, Ng3101, Ng3102, Ng3103, Ng3104, Ng3105, Ng3106, Ng3107, + Ng3108, Ng3155, Ng3158, Ng3161, Ng3164, Ng3167, Ng3170, Ng3173, Ng3176, + Ng3179, Ng3182, Ng3185, Ng3088, Ng3191, Ng3128, Ng3126, Ng3125, Ng3123, + Ng3120, Ng3110, Ng3139, Ng3135, Ng3147, Ng185, Ng130, Ng131, Ng129, + Ng133, Ng134, Ng132, Ng142, Ng143, Ng141, Ng145, Ng146, Ng144, Ng148, + Ng149, Ng147, Ng151, Ng152, Ng150, Ng154, Ng155, Ng153, Ng157, Ng158, + Ng156, Ng160, Ng161, Ng159, Ng163, Ng164, Ng162, Ng169, Ng170, Ng168, + Ng172, Ng173, Ng171, Ng175, Ng176, Ng174, Ng178, Ng179, Ng177, Ng186, + Ng189, Ng192, Ng231, Ng234, Ng237, Ng195, Ng198, Ng201, Ng240, Ng243, + Ng246, Ng204, Ng207, Ng210, Ng249, Ng252, Ng255, Ng213, Ng216, Ng219, + Ng258, Ng261, Ng264, Ng222, Ng225, Ng228, Ng267, Ng270, Ng273, Ng92, + Ng88, Ng83, Ng79, Ng74, Ng70, Ng65, Ng61, Ng56, Ng52, Ng11497, Ng11498, + Ng11499, Ng11500, Ng11501, Ng11502, Ng11503, Ng11504, Ng11505, Ng11506, + Ng11507, Ng11508, Ng408, Ng411, Ng414, Ng417, Ng420, Ng423, Ng427, + Ng428, Ng426, Ng429, Ng432, Ng435, Ng438, Ng441, Ng444, Ng448, Ng449, + Ng447, Ng312, Ng313, Ng314, Ng315, Ng316, Ng317, Ng318, Ng319, Ng320, + Ng322, Ng323, Ng321, Ng403, Ng404, Ng402, Ng450, Ng451, Ng452, Ng453, + Ng454, Ng279, Ng280, Ng281, Ng282, Ng283, Ng284, Ng285, Ng286, Ng287, + Ng288, Ng289, Ng290, Ng291, Ng299, Ng305, Ng298, Ng342, Ng349, Ng350, + Ng351, Ng352, Ng353, Ng357, Ng364, Ng365, Ng366, Ng367, Ng368, Ng372, + Ng379, Ng380, Ng381, Ng382, Ng383, Ng387, Ng394, Ng395, Ng396, Ng397, + Ng324, Ng554, Ng557, Ng510, Ng513, Ng523, Ng524, Ng564, Ng569, Ng570, + Ng571, Ng572, Ng573, Ng574, Ng565, Ng566, Ng567, Ng568, Ng489, Ng486, + Ng487, Ng488, Ng11512, Ng11515, Ng11516, Ng477, Ng478, Ng479, Ng480, + Ng484, Ng464, Ng11517, Ng11513, Ng11514, Ng528, Ng535, Ng542, Ng543, + Ng544, Ng548, Ng549, Ng8284, Ng558, Ng559, Ng576, Ng577, Ng575, Ng579, + Ng580, Ng578, Ng582, Ng583, Ng581, Ng585, Ng586, Ng584, Ng587, Ng590, + Ng593, Ng596, Ng599, Ng602, Ng614, Ng617, Ng620, Ng605, Ng608, Ng611, + Ng490, Ng493, Ng496, Ng506, Ng507, Pg16297, Ng525, Ng529, Ng530, Ng531, + Ng532, Ng533, Ng534, Ng536, Ng537, Ng538, Ng541, Ng630, Ng659, Ng640, + Ng633, Ng653, Ng646, Ng660, Ng672, Ng666, Ng679, Ng686, Ng692, Ng699, + Ng700, Ng698, Ng702, Ng703, Ng701, Ng705, Ng706, Ng704, Ng708, Ng709, + Ng707, Ng711, Ng712, Ng710, Ng714, Ng715, Ng713, Ng717, Ng718, Ng716, + Ng720, Ng721, Ng719, Ng723, Ng724, Ng722, Ng726, Ng727, Ng725, Ng729, + Ng730, Ng728, Ng732, Ng733, Ng731, Ng735, Ng736, Ng734, Ng738, Ng739, + Ng737, \[1612] , \[1594] , Ng853, Ng818, Ng819, Ng817, Ng821, Ng822, + Ng820, Ng830, Ng831, Ng829, Ng833, Ng834, Ng832, Ng836, Ng837, Ng835, + Ng839, Ng840, Ng838, Ng842, Ng843, Ng841, Ng845, Ng846, Ng844, Ng848, + Ng849, Ng847, Ng851, Ng852, Ng850, Ng857, Ng858, Ng856, Ng860, Ng861, + Ng859, Ng863, Ng864, Ng862, Ng866, Ng867, Ng865, Ng873, Ng876, Ng879, + Ng918, Ng921, Ng924, Ng882, Ng885, Ng888, Ng927, Ng930, Ng933, Ng891, + Ng894, Ng897, Ng936, Ng939, Ng942, Ng900, Ng903, Ng906, Ng945, Ng948, + Ng951, Ng909, Ng912, Ng915, Ng954, Ng957, Ng960, Ng780, Ng776, Ng771, + Ng767, Ng762, Ng758, Ng753, Ng749, Ng744, Ng740, Ng11524, Ng11525, + Ng11526, Ng11527, Ng11528, Ng11529, Ng11530, Ng11531, Ng11532, Ng11533, + Ng11534, Ng11535, Ng1095, Ng1098, Ng1101, Ng1104, Ng1107, Ng1110, + Ng1114, Ng1115, Ng1113, Ng1116, Ng1119, Ng1122, Ng1125, Ng1128, Ng1131, + Ng1135, Ng1136, Ng1134, Ng999, Ng1000, Ng1001, Ng1002, Ng1003, Ng1004, + Ng1005, Ng1006, Ng1007, Ng1009, Ng1010, Ng1008, Ng1090, Ng1091, Ng1089, + Ng1137, Ng1138, Ng1139, Ng1140, Ng1141, Ng966, Ng967, Ng968, Ng969, + Ng970, Ng971, Ng972, Ng973, Ng974, Ng975, Ng976, Ng977, Ng978, Ng986, + Ng992, Ng985, Ng1029, Ng1036, Ng1037, Ng1038, Ng1039, Ng1040, Ng1044, + Ng1051, Ng1052, Ng1053, Ng1054, Ng1055, Ng1059, Ng1066, Ng1067, Ng1068, + Ng1069, Ng1070, Ng1074, Ng1081, Ng1082, Ng1083, Ng1084, Ng1011, Ng1240, + Ng1243, Ng1196, Ng1199, Ng1209, Ng1210, Ng1250, Ng1255, Ng1256, Ng1257, + Ng1258, Ng1259, Ng1260, Ng1251, Ng1252, Ng1253, Ng1254, Ng1176, Ng1173, + Ng1174, Ng1175, Ng11539, Ng11542, Ng11543, Ng1164, Ng1165, Ng1166, + Ng1167, Ng1171, Ng1151, Ng11544, Ng11540, Ng11541, Ng1214, Ng1221, + Ng1228, Ng1229, Ng1230, Ng1234, Ng1235, Ng8293, Ng1244, Ng1245, Ng1262, + Ng1263, Ng1261, Ng1265, Ng1266, Ng1264, Ng1268, Ng1269, Ng1267, Ng1271, + Ng1272, Ng1270, Ng1273, Ng1276, Ng1279, Ng1282, Ng1285, Ng1288, Ng1300, + Ng1303, Ng1306, Ng1291, Ng1294, Ng1297, Ng1177, Ng1180, Ng1183, Ng1192, + Ng1193, Pg16355, Ng1211, Ng1215, Ng1216, Ng1217, Ng1218, Ng1219, + Ng1220, Ng1222, Ng1223, Ng1224, Ng1227, \[1605] , \[1603] , Ng1315, + Ng1316, Ng1345, Ng1326, Ng1319, Ng1339, Ng1332, Ng1346, Ng1358, Ng1352, + Ng1365, Ng1372, Ng1378, Ng1385, Ng1386, Ng1384, Ng1388, Ng1389, Ng1387, + Ng1391, Ng1392, Ng1390, Ng1394, Ng1395, Ng1393, Ng1397, Ng1398, Ng1396, + Ng1400, Ng1401, Ng1399, Ng1403, Ng1404, Ng1402, Ng1406, Ng1407, Ng1405, + Ng1409, Ng1410, Ng1408, Ng1412, Ng1413, Ng1411, Ng1415, Ng1416, Ng1414, + Ng1418, Ng1419, Ng1417, Ng1421, Ng1422, Ng1420, Ng1424, Ng1425, Ng1423, + Ng1512, Ng1513, Ng1511, Ng1515, Ng1516, Ng1514, Ng1524, Ng1525, Ng1523, + Ng1527, Ng1528, Ng1526, Ng1530, Ng1531, Ng1529, Ng1533, Ng1534, Ng1532, + Ng1536, Ng1537, Ng1535, Ng1539, Ng1540, Ng1538, Ng1542, Ng1543, Ng1541, + Ng1545, Ng1546, Ng1544, Ng1551, Ng1552, Ng1550, Ng1554, Ng1555, Ng1553, + Ng1557, Ng1558, Ng1556, Ng1560, Ng1561, Ng1559, Ng1567, Ng1570, Ng1573, + Ng1612, Ng1615, Ng1618, Ng1576, Ng1579, Ng1582, Ng1621, Ng1624, Ng1627, + Ng1585, Ng1588, Ng1591, Ng1630, Ng1633, Ng1636, Ng1594, Ng1597, Ng1600, + Ng1639, Ng1642, Ng1645, Ng1603, Ng1606, Ng1609, Ng1648, Ng1651, Ng1654, + Ng1466, Ng1462, Ng1457, Ng1453, Ng1448, Ng1444, Ng1439, Ng1435, Ng1430, + Ng1426, Ng11551, Ng11552, Ng11553, Ng11554, Ng11555, Ng11556, Ng11557, + Ng11558, Ng11559, Ng11560, Ng11561, Ng11562, Ng1789, Ng1792, Ng1795, + Ng1798, Ng1801, Ng1804, Ng1808, Ng1809, Ng1807, Ng1810, Ng1813, Ng1816, + Ng1819, Ng1822, Ng1825, Ng1829, Ng1830, Ng1828, Ng1693, Ng1694, Ng1695, + Ng1696, Ng1697, Ng1698, Ng1699, Ng1700, Ng1701, Ng1703, Ng1704, Ng1702, + Ng1784, Ng1785, Ng1783, Ng1831, Ng1832, Ng1833, Ng1834, Ng1835, Ng1660, + Ng1661, Ng1662, Ng1663, Ng1664, Ng1665, Ng1666, Ng1667, Ng1668, Ng1669, + Ng1670, Ng1671, Ng1672, Ng1680, Ng1686, Ng1679, Ng1723, Ng1730, Ng1731, + Ng1732, Ng1733, Ng1734, Ng1738, Ng1745, Ng1746, Ng1747, Ng1748, Ng1749, + Ng1753, Ng1760, Ng1761, Ng1762, Ng1763, Ng1764, Ng1768, Ng1775, Ng1776, + Ng1777, Ng1778, Ng1705, Ng1934, Ng1937, Ng1890, Ng1893, Ng1903, Ng1904, + Ng1944, Ng1949, Ng1950, Ng1951, Ng1952, Ng1953, Ng1954, Ng1945, Ng1946, + Ng1947, Ng1948, Ng1870, Ng1867, Ng1868, Ng1869, Ng11566, Ng11569, + Ng11570, Ng1858, Ng1859, Ng1860, Ng1861, Ng1865, Ng1845, Ng11571, + Ng11567, Ng11568, Ng1908, Ng1915, Ng1922, Ng1923, Ng1924, Ng1928, + Ng1929, Ng8302, Ng1938, Ng1939, Ng1956, Ng1957, Ng1955, Ng1959, Ng1960, + Ng1958, Ng1962, Ng1963, Ng1961, Ng1965, Ng1966, Ng1964, Ng1967, Ng1970, + Ng1973, Ng1976, Ng1979, Ng1982, Ng1994, Ng1997, Ng2000, Ng1985, Ng1988, + Ng1991, Ng1871, Ng1874, Ng1877, Ng1886, Ng1887, Pg16399, Ng1905, + Ng1909, Ng1910, Ng1911, Ng1912, Ng1913, Ng1914, Ng1916, Ng1917, Ng1918, + Ng1921, Ng2010, Ng2039, Ng2020, Ng2013, Ng2033, Ng2026, Ng2040, Ng2052, + Ng2046, Ng2059, Ng2066, Ng2072, Ng2079, Ng2080, Ng2078, Ng2082, Ng2083, + Ng2081, Ng2085, Ng2086, Ng2084, Ng2088, Ng2089, Ng2087, Ng2091, Ng2092, + Ng2090, Ng2094, Ng2095, Ng2093, Ng2097, Ng2098, Ng2096, Ng2100, Ng2101, + Ng2099, Ng2103, Ng2104, Ng2102, Ng2106, Ng2107, Ng2105, Ng2109, Ng2110, + Ng2108, Ng2112, Ng2113, Ng2111, Ng2115, Ng2116, Ng2114, Ng2118, Ng2119, + Ng2117, Ng2206, Ng2207, Ng2205, Ng2209, Ng2210, Ng2208, Ng2218, Ng2219, + Ng2217, Ng2221, Ng2222, Ng2220, Ng2224, Ng2225, Ng2223, Ng2227, Ng2228, + Ng2226, Ng2230, Ng2231, Ng2229, Ng2233, Ng2234, Ng2232, Ng2236, Ng2237, + Ng2235, Ng2239, Ng2240, Ng2238, Ng2245, Ng2246, Ng2244, Ng2248, Ng2249, + Ng2247, Ng2251, Ng2252, Ng2250, Ng2254, Ng2255, Ng2253, Ng2261, Ng2264, + Ng2267, Ng2306, Ng2309, Ng2312, Ng2270, Ng2273, Ng2276, Ng2315, Ng2318, + Ng2321, Ng2279, Ng2282, Ng2285, Ng2324, Ng2327, Ng2330, Ng2288, Ng2291, + Ng2294, Ng2333, Ng2336, Ng2339, Ng2297, Ng2300, Ng2303, Ng2342, Ng2345, + Ng2348, Ng2160, Ng2156, Ng2151, Ng2147, Ng2142, Ng2138, Ng2133, Ng2129, + Ng2124, Ng2120, Ng2256, \[1609] , Ng2257, Ng11578, Ng11579, Ng11580, + Ng11581, Ng11582, Ng11583, Ng11584, Ng11585, Ng11586, Ng11587, Ng11588, + Ng11589, Ng2483, Ng2486, Ng2489, Ng2492, Ng2495, Ng2498, Ng2502, + Ng2503, Ng2501, Ng2504, Ng2507, Ng2510, Ng2513, Ng2516, Ng2519, Ng2523, + Ng2524, Ng2522, Ng2387, Ng2388, Ng2389, Ng2390, Ng2391, Ng2392, Ng2393, + Ng2394, Ng2395, Ng2397, Ng2398, Ng2396, Ng2478, Ng2479, Ng2477, Ng2525, + Ng2526, Ng2527, Ng2528, Ng2529, Ng2354, Ng2355, Ng2356, Ng2357, Ng2358, + Ng2359, Ng2360, Ng2361, Ng2362, Ng2363, Ng2364, Ng2365, Ng2366, Ng2374, + Ng2380, Ng2373, Ng2417, Ng2424, Ng2425, Ng2426, Ng2427, Ng2428, Ng2432, + Ng2439, Ng2440, Ng2441, Ng2442, Ng2443, Ng2447, Ng2454, Ng2455, Ng2456, + Ng2457, Ng2458, Ng2462, Ng2469, Ng2470, Ng2471, Ng2472, Ng2399, Ng2628, + Ng2631, Ng2584, Ng2587, Ng2597, Ng2598, Ng2638, Ng2643, Ng2644, Ng2645, + Ng2646, Ng2647, Ng2648, Ng2639, Ng2640, Ng2641, Ng2642, Ng2564, Ng2561, + Ng2562, Ng2563, Ng11593, Ng11596, Ng11597, Ng2552, Ng2553, Ng2554, + Ng2555, Ng2559, Ng2539, Ng11598, Ng11594, Ng11595, Ng2602, Ng2609, + Ng2616, Ng2617, Ng2618, Ng2622, Ng2623, Ng8311, Ng2632, Ng2633, Ng2650, + Ng2651, Ng2649, Ng2653, Ng2654, Ng2652, Ng2656, Ng2657, Ng2655, Ng2659, + Ng2660, Ng2658, Ng2661, Ng2664, Ng2667, Ng2670, Ng2673, Ng2676, Ng2688, + Ng2691, Ng2694, Ng2679, Ng2682, Ng2685, Ng2565, Ng2568, Ng2571, Ng2580, + Ng2581, Pg16437, Ng2599, Ng2603, Ng2604, Ng2605, Ng2606, Ng2607, + Ng2608, Ng2610, Ng2611, Ng2612, Ng2615, Ng2704, Ng2733, Ng2714, Ng2707, + Ng2727, Ng2720, Ng2734, Ng2746, Ng2740, Ng2753, Ng2760, Ng2766, Ng2773, + Ng2774, Ng2772, Ng2776, Ng2777, Ng2775, Ng2779, Ng2780, Ng2778, Ng2782, + Ng2783, Ng2781, Ng2785, Ng2786, Ng2784, Ng2788, Ng2789, Ng2787, Ng2791, + Ng2792, Ng2790, Ng2794, Ng2795, Ng2793, Ng2797, Ng2798, Ng2796, Ng2800, + Ng2801, Ng2799, Ng2803, Ng2804, Ng2802, Ng2806, Ng2807, Ng2805, Ng2809, + Ng2810, Ng2808, Ng2812, Ng2813, Ng2811, Ng3054, Ng3079, Ng13475, + Ng3043, Ng3044, Ng3045, Ng3046, Ng3047, Ng3048, Ng3049, Ng3050, Ng3051, + Ng3052, Ng3053, Ng3055, Ng3056, Ng3057, Ng3058, Ng3059, Ng3060, Ng3061, + Ng3062, Ng3063, Ng3064, Ng3065, Ng3066, Ng3067, Ng3068, Ng3069, Ng3070, + Ng3071, Ng3072, Ng3073, Ng3074, Ng3075, Ng3076, Ng3077, Ng3078, Ng2997, + Ng2993, Ng2998, Ng3006, Ng3002, Ng3013, Ng3010, Ng3024, Ng3018, Ng3028, + Ng3036, Ng3032, Pg5388, Ng2986, Ng2987, Pg8275, Pg8274, Pg8273, Pg8272, + Pg8268, Pg8269, Pg8270, Pg8271, Ng3083, Pg8267, Ng2992, Pg8266, Pg8265, + Pg8264, Pg8262, Pg8263, Pg8260, Pg8261, Pg8259, Ng2990, Ng2991, Pg8258; + wire n4530, n4531_1, n4532, n4533, n4534, n4535, n4536_1, n4537, n4538, + n4539, n4540, n4541_1, n4542, n4543, n4544, n4545, n4546_1, n4547, + n4548, n4549, n4550_1, n4551, n4552, n4553, n4554, n4555_1, n4556, + n4557, n4558, n4559_1, n4560, n4561, n4562, n4563, n4564_1, n4565, + n4566, n4567, n4568_1, n4569, n4570, n4571, n4572, n4573_1, n4574, + n4575, n4576, n4577_1, n4578, n4579, n4580, n4581, n4582_1, n4583, + n4584, n4585, n4586_1, n4588, n4590, n4591_1, n4592, n4593, n4594, + n4596, n4598, n4600_1, n4601, n4602, n4603, n4604_1, n4606, n4608, + n4610, n4612, n4613_1, n4614, n4615, n4616, n4618, n4620, n4622, n4624, + n4625, n4626_1, n4628, n4630, n4632, n4633, n4634, n4636_1, n4638, + n4639, n4640_1, n4642, n4643, n4644, n4646, n4647, n4648_1, n4649, + n4650, n4651, n4652_1, n4653, n4654, n4655, n4656_1, n4657, n4658, + n4659, n4660_1, n4661, n4662, n4663, n4664_1, n4665, n4666, n4667, + n4668_1, n4669, n4670, n4671, n4672_1, n4673, n4674, n4675, n4676_1, + n4677, n4678, n4679, n4680_1, n4681, n4682, n4683, n4684_1, n4685, + n4686, n4687, n4688_1, n4689, n4690, n4691, n4692_1, n4693, n4694, + n4695, n4696_1, n4697, n4698, n4699, n4700_1, n4701, n4702, n4703, + n4704_1, n4705, n4706, n4707, n4708_1, n4709, n4710, n4711, n4712_1, + n4713, n4714, n4715, n4716_1, n4717, n4718, n4719, n4720_1, n4721, + n4722, n4723, n4724_1, n4725, n4726, n4727, n4728_1, n4729, n4730, + n4731, n4732_1, n4733, n4734, n4735, n4736, n4737_1, n4738, n4739, + n4740, n4741, n4742_1, n4743, n4744, n4745, n4746, n4747_1, n4748, + n4749, n4750, n4751, n4752_1, n4753, n4754, n4755, n4756_1, n4757, + n4758, n4759, n4760_1, n4761, n4762, n4763, n4764, n4765_1, n4766, + n4767, n4768, n4769_1, n4770, n4771, n4772, n4773, n4774_1, n4775, + n4776, n4777, n4778_1, n4779, n4780, n4781, n4782, n4783_1, n4784, + n4785, n4786, n4787_1, n4788, n4789, n4790, n4791, n4792_1, n4793, + n4794, n4795, n4796_1, n4797, n4798, n4799, n4800, n4801_1, n4802, + n4803, n4804, n4805_1, n4806, n4807, n4808, n4809, n4810_1, n4811, + n4812, n4813, n4814_1, n4815, n4816, n4817, n4818, n4819_1, n4820, + n4821, n4822, n4823, n4824_1, n4825, n4826, n4827, n4828, n4829_1, + n4830, n4831, n4832, n4833, n4834_1, n4835, n4836, n4837, n4838_1, + n4839, n4840, n4841, n4842_1, n4843, n4844, n4845, n4846_1, n4847, + n4848, n4849, n4850, n4851_1, n4852, n4853, n4854, n4855, n4856_1, + n4857, n4858, n4859, n4860, n4861_1, n4862, n4863, n4864, n4865, + n4866_1, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, + n4876_1, n4877, n4878, n4879, n4880_1, n4881, n4882, n4883, n4884_1, + n4885, n4886, n4887, n4888_1, n4889, n4890, n4891, n4892_1, n4893, + n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901_1, n4902, n4903, + n4904, n4905, n4906, n4907, n4908, n4909, n4910_1, n4911, n4912, n4913, + n4914, n4915_1, n4916, n4917, n4918, n4919_1, n4920, n4921, n4922, + n4923, n4924_1, n4925, n4926, n4927, n4928_1, n4929, n4930, n4931, + n4932, n4933_1, n4934, n4935, n4936, n4937, n4938_1, n4939, n4940, + n4941, n4942, n4943_1, n4944, n4945, n4946, n4947, n4948_1, n4949, + n4950, n4951, n4952, n4953_1, n4954, n4955, n4956, n4957, n4958_1, + n4959, n4960, n4961, n4962, n4963_1, n4964, n4965, n4966, n4967, + n4968_1, n4969, n4970, n4971, n4972, n4973_1, n4974, n4975, n4976, + n4977, n4978_1, n4979, n4980, n4981, n4982, n4983_1, n4984, n4985, + n4986, n4987, n4988_1, n4989, n4990, n4991, n4992, n4993_1, n4994, + n4995, n4996, n4997, n4998_1, n4999, n5000, n5001, n5002, n5003_1, + n5004, n5005, n5006, n5007, n5008_1, n5009, n5010, n5011, n5012, + n5013_1, n5014, n5015, n5016, n5017, n5018_1, n5019, n5020, n5021, + n5022, n5023_1, n5024, n5025, n5026, n5027, n5028_1, n5029, n5030, + n5031, n5032, n5033_1, n5034, n5035, n5036, n5037, n5038_1, n5039, + n5040, n5041, n5042, n5043_1, n5044, n5045, n5046, n5047, n5049, n5050, + n5051, n5052, n5053_1, n5054, n5055, n5056, n5057, n5058_1, n5059, + n5060, n5061, n5062, n5063_1, n5064, n5065, n5066, n5067_1, n5068, + n5069, n5070, n5071, n5072_1, n5073, n5074, n5075, n5076, n5077_1, + n5078, n5079, n5080_1, n5081, n5082, n5083, n5084, n5087, n5089, n5091, + n5093, n5097, n5099, n5101, n5103, n5105_1, n5106, n5108, n5109, n5111, + n5112, n5114, n5115_1, n5117, n5118, n5122, n5124, n5126, n5127, n5128, + n5129, n5131, n5132, n5133, n5135_1, n5136, n5137, n5138, n5139, + n5140_1, n5142, n5144, n5145_1, n5147, n5149, n5151, n5153, n5154, + n5156, n5158, n5160_1, n5161, n5163, n5164, n5165_1, n5166, n5168, + n5170_1, n5171, n5173, n5174, n5175_1, n5176, n5178, n5180_1, n5181, + n5183, n5184, n5185_1, n5186, n5188, n5190_1, n5191, n5192, n5193, + n5196, n5198, n5200_1, n5202, n5204, n5206, n5208, n5210_1, n5213, + n5215_1, n5217, n5219, n5221, n5223, n5225_1, n5227, n5229, n5230_1, + n5232, n5234, n5236, n5239, n5241, n5243, n5245_1, n5247, n5249, n5251, + n5253, n5255_1, n5257, n5259, n5261, n5263, n5265_1, n5267, n5269, + n5271, n5273, n5275_1, n5277, n5279, n5281, n5284, n5286, n5289, n5291, + n5293, n5295_1, n5297, n5299, n5301, n5303, n5305_1, n5307, n5309, + n5311, n5312, n5313, n5314, n5315_1, n5316, n5317, n5318, n5319, + n5320_1, n5321, n5322, n5323, n5325_1, n5327, n5329, n5331, n5333, + n5335_1, n5337, n5339, n5340_1, n5342, n5344, n5345_1, n5347, n5349, + n5351, n5352, n5354, n5356, n5358, n5359, n5361, n5363, n5365_1, n5367, + n5369, n5371, n5373, n5375_1, n5377, n5379, n5381, n5383, n5385_1, + n5387, n5389, n5391, n5392, n5394, n5396, n5397, n5399, n5401, n5403, + n5404, n5406, n5408, n5410_1, n5411, n5413, n5415_1, n5417, n5419, + n5421, n5423, n5425_1, n5427, n5429, n5431, n5433, n5435_1, n5436, + n5437, n5438, n5439, n5440_1, n5441, n5442, n5443, n5444, n5445_1, + n5446, n5447, n5448, n5449, n5450_1, n5451, n5452, n5453, n5454, + n5455_1, n5456, n5457, n5458, n5459, n5460_1, n5461, n5462, n5463, + n5464, n5465_1, n5466, n5467, n5468, n5469, n5470_1, n5471, n5472, + n5473, n5474, n5475_1, n5476, n5477, n5478, n5479, n5480_1, n5481, + n5482, n5483, n5484, n5485_1, n5486, n5487, n5488, n5489, n5490_1, + n5491, n5492, n5493, n5494, n5495_1, n5496, n5497, n5498, n5499, + n5500_1, n5501, n5502, n5503, n5504, n5505_1, n5506, n5507, n5508, + n5509, n5510_1, n5511, n5512, n5513, n5514, n5515_1, n5516, n5517, + n5518, n5519, n5520_1, n5521, n5522, n5523, n5524, n5525_1, n5526, + n5527, n5528, n5529, n5530_1, n5531, n5532, n5533, n5534, n5535_1, + n5536, n5537, n5538, n5539, n5540_1, n5541, n5542, n5543, n5544, + n5545_1, n5546, n5547, n5548, n5549, n5550_1, n5551, n5552, n5553, + n5554, n5555_1, n5556, n5557, n5558, n5559, n5560_1, n5561, n5562, + n5563, n5564, n5565_1, n5566, n5567, n5568, n5569, n5570_1, n5571, + n5572, n5573, n5574, n5575_1, n5576, n5577, n5578, n5579, n5580_1, + n5581, n5582, n5583, n5584, n5585_1, n5586, n5587, n5588, n5589, + n5590_1, n5591, n5592, n5593, n5594, n5595_1, n5596, n5597, n5598, + n5599, n5600_1, n5601, n5602, n5603, n5604, n5605_1, n5606, n5607, + n5608, n5609, n5610_1, n5611, n5612, n5613, n5614, n5615_1, n5616, + n5617, n5618, n5619, n5620_1, n5621, n5622, n5623, n5624, n5625_1, + n5626, n5627, n5628, n5629, n5630_1, n5631, n5632, n5633, n5634, + n5635_1, n5636, n5637, n5638, n5639, n5640_1, n5641, n5642, n5643, + n5644, n5645_1, n5646, n5647, n5648, n5649, n5650_1, n5651, n5652, + n5653, n5654, n5655_1, n5656, n5657, n5658, n5659, n5660_1, n5661, + n5662, n5663, n5664, n5665_1, n5666, n5667, n5668, n5669, n5670_1, + n5671, n5672, n5677, n5679, n5681, n5683, n5685_1, n5687, n5689, n5691, + n5693, n5695_1, n5697, n5699, n5701, n5703, n5705_1, n5707, n5709, + n5711, n5713, n5715_1, n5717, n5719, n5721, n5723, n5725_1, n5727, + n5729, n5731, n5733, n5735_1, n5737, n5739, n5741, n5743, n5745_1, + n5747, n5817, n5818, n5819_1, n5820, n5821, n5822, n5823_1, n5824, + n5825, n5826, n5827, n5828_1, n5829, n5830, n5831, n5832, n5833_1, + n5834, n5835, n5836, n5837, n5838_1, n5839, n5840, n5841, n5842, + n5843_1, n5844, n5845, n5846, n5847, n5848_1, n5849, n5850, n5851, + n5852, n5853_1, n5854, n5855, n5856, n5857, n5858_1, n5859, n5860, + n5861, n5862, n5863_1, n5864, n5865, n5866, n5867, n5868_1, n5869, + n5870, n5871, n5872, n5873_1, n5874, n5875, n5876, n5877, n5878_1, + n5879, n5880, n5881, n5882, n5883_1, n5884, n5885, n5886, n5887, + n5888_1, n5889, n5890, n5891, n5892, n5893_1, n5894, n5895, n5896, + n5897, n5898_1, n5899, n5900, n5901, n5902, n5903_1, n5904, n5905, + n5906, n5907, n5908_1, n5909, n5910, n5911, n5912, n5913_1, n5914, + n5915, n5916, n5917, n5918_1, n5919, n5920, n5921, n5922, n5923_1, + n5924, n5925, n5926, n5927, n5928_1, n5929, n5930, n5931, n5932, + n5933_1, n5934, n5935, n5936, n5937, n5938_1, n5939, n5940, n5941, + n5942, n5943_1, n5944, n5945, n5946, n5947, n5948_1, n5949, n5950, + n5951, n5952, n5953_1, n5954, n5955, n5956, n5957, n5958_1, n5959, + n5960, n5961, n5962, n5963_1, n5964, n5965, n5966, n5967, n5968_1, + n5969, n5970, n5971, n5972, n5973_1, n5974, n5975, n5976, n5977, + n5978_1, n5979, n5980, n5981, n5982, n5983_1, n5984, n5985, n5986, + n5987, n5988_1, n5989, n5990, n5991, n5992, n5993_1, n5994, n5995, + n5996, n5997, n5998_1, n5999, n6000, n6001, n6002, n6003_1, n6004, + n6005, n6006, n6007, n6008_1, n6009, n6010, n6011, n6012, n6013_1, + n6014, n6015, n6016, n6017, n6018_1, n6019, n6020, n6021, n6022, + n6023_1, n6024, n6025, n6026, n6027, n6028_1, n6029, n6030, n6031, + n6032, n6033_1, n6034, n6035, n6036, n6037, n6038_1, n6039, n6040, + n6041, n6042, n6043_1, n6044, n6045, n6046, n6047, n6048_1, n6049, + n6050, n6051, n6052, n6053_1, n6054, n6055, n6056, n6057_1, n6058, + n6059, n6060, n6061, n6062_1, n6063, n6064, n6065, n6066_1, n6067, + n6068, n6069, n6070, n6071_1, n6072, n6073, n6074, n6075_1, n6076, + n6077, n6078, n6079, n6080_1, n6081, n6082, n6083, n6084_1, n6085, + n6086, n6087, n6088, n6089_1, n6090, n6091, n6092, n6093_1, n6094, + n6095, n6096, n6097, n6098_1, n6099, n6100, n6101, n6102_1, n6103, + n6104, n6105, n6106, n6107_1, n6108, n6109, n6110, n6111_1, n6112, + n6113, n6114, n6115, n6116_1, n6117, n6118, n6119, n6120_1, n6121, + n6122, n6123, n6124_1, n6125, n6126, n6127, n6128_1, n6129, n6130, + n6131, n6132, n6133_1, n6134, n6135, n6136, n6137, n6138_1, n6139, + n6140, n6141, n6142, n6143_1, n6144, n6145, n6146, n6147_1, n6148, + n6149, n6150, n6151_1, n6152, n6153, n6154, n6155_1, n6156, n6157, + n6158, n6159_1, n6160, n6161, n6162, n6163_1, n6164, n6165, n6166, + n6167_1, n6168, n6169, n6170, n6171_1, n6172, n6173, n6174, n6175_1, + n6176, n6177, n6178, n6179_1, n6180, n6181, n6182, n6183_1, n6184, + n6185, n6186, n6187_1, n6188, n6189, n6190, n6191_1, n6192, n6193, + n6194, n6195_1, n6196, n6197, n6198, n6199_1, n6200, n6201, n6202, + n6203_1, n6204, n6205, n6206, n6207_1, n6208, n6209, n6210, n6211_1, + n6212, n6213, n6214, n6215_1, n6216, n6217, n6218, n6219_1, n6221, + n6222, n6223_1, n6225, n6226, n6227_1, n6229, n6230, n6231_1, n6233, + n6234, n6235_1, n6236, n6237, n6238, n6239_1, n6240, n6241, n6242, + n6243, n6244_1, n6245, n6246, n6247, n6248, n6249_1, n6250, n6251, + n6252, n6253, n6254_1, n6255, n6256, n6257, n6258, n6259_1, n6260, + n6261, n6262, n6263_1, n6264, n6265, n6266, n6267_1, n6268, n6269, + n6270, n6271, n6272_1, n6273, n6274, n6275, n6276_1, n6277, n6278, + n6279, n6280, n6281_1, n6282, n6283, n6285_1, n6286, n6287, n6288, + n6289, n6290_1, n6291, n6292, n6293, n6294_1, n6295, n6296, n6297, + n6298, n6299_1, n6300, n6301, n6302, n6303_1, n6304, n6305, n6306, + n6307, n6308_1, n6309, n6310, n6311, n6312_1, n6313, n6314, n6315, + n6316, n6317_1, n6318, n6319, n6320, n6321_1, n6322, n6323, n6324, + n6325, n6326_1, n6327, n6328, n6329, n6330, n6331_1, n6332, n6333, + n6334, n6335, n6336_1, n6337, n6338, n6339, n6340, n6341_1, n6342, + n6343, n6344, n6345_1, n6346, n6347, n6348, n6349_1, n6350, n6351, + n6352, n6353_1, n6354, n6355, n6356, n6357, n6358_1, n6359, n6360, + n6361, n6362, n6363_1, n6364, n6365, n6366, n6367, n6368_1, n6369, + n6370, n6371, n6372, n6373_1, n6374, n6375, n6376, n6377, n6378_1, + n6379, n6380, n6381, n6382, n6383_1, n6384, n6385, n6386, n6387_1, + n6388, n6389, n6390, n6391_1, n6392, n6393, n6394, n6395_1, n6396, + n6397, n6398, n6399_1, n6400, n6401, n6402, n6403_1, n6404, n6405, + n6406, n6407, n6408_1, n6409, n6410, n6411, n6412_1, n6413, n6414, + n6415, n6416, n6417_1, n6418, n6419, n6420, n6421, n6422_1, n6423, + n6424, n6425, n6426_1, n6427, n6428, n6429, n6430, n6431_1, n6432, + n6433, n6434, n6435_1, n6436, n6437, n6438, n6439, n6440_1, n6441, + n6442, n6443, n6444, n6445_1, n6446, n6447, n6448, n6449, n6450_1, + n6451, n6452, n6453, n6454, n6455_1, n6456, n6457, n6458, n6459, + n6460_1, n6461, n6462, n6463, n6464, n6465_1, n6466, n6467, n6468, + n6469, n6470_1, n6471, n6472, n6473, n6474, n6476, n6478, n6479, + n6480_1, n6481, n6482, n6483, n6484, n6485_1, n6486, n6487, n6488, + n6489, n6490_1, n6491, n6492, n6493, n6494, n6495_1, n6496, n6497, + n6498, n6499, n6500_1, n6501, n6502, n6503, n6504, n6505_1, n6506, + n6507, n6508, n6509, n6510_1, n6511, n6512, n6513, n6514, n6515_1, + n6516, n6517, n6518, n6520_1, n6521, n6522, n6523, n6524, n6526, n6527, + n6528, n6529, n6530_1, n6531, n6532, n6533, n6534, n6535_1, n6536, + n6537, n6538, n6539, n6540_1, n6541, n6542, n6543, n6544, n6545_1, + n6546, n6547, n6548, n6549, n6550_1, n6551, n6552, n6553, n6554, + n6555_1, n6556, n6557, n6558, n6559, n6560_1, n6561, n6562, n6563, + n6564, n6565_1, n6566, n6567, n6568, n6569, n6570_1, n6571, n6572, + n6573, n6574_1, n6575, n6576, n6577, n6578, n6579_1, n6580, n6581, + n6582, n6583, n6584_1, n6585, n6586, n6587_1, n6588, n6589, n6591, + n6595, n6597_1, n6599, n6600, n6601, n6602_1, n6603, n6604, n6605, + n6606, n6607_1, n6608, n6610, n6612_1, n6614, n6615, n6616, n6617_1, + n6618, n6619, n6621, n6623, n6625, n6626, n6627_1, n6629, n6631, n6633, + n6635, n6637_1, n6639, n6641, n6643, n6645, n6647_1, n6649, n6651, + n6653, n6655, n6657_1, n6659, n6661, n6663, n6664, n6665, n6667_1, + n6669, n6671, n6673, n6675, n6677_1, n6679, n6681, n6683, n6685, + n6687_1, n6689, n6691, n6693, n6695, n6697_1, n6699, n6701, n6702_1, + n6703, n6705, n6707_1, n6709, n6711, n6713, n6715, n6717_1, n6719, + n6721, n6723, n6725, n6727_1, n6729, n6731, n6733, n6735, n6737_1, + n6739, n6740, n6741, n6743, n6745, n6747_1, n6749, n6751, n6753, n6755, + n6757_1, n6759, n6761, n6763, n6765, n6767_1, n6769, n6771, n6773, + n6775, n6777_1, n6779, n6781, n6783, n6785, n6787_1, n6789, n6791, + n6793, n6795, n6796, n6798, n6800, n6802_1, n6804, n6806, n6808, n6809, + n6811, n6813, n6815, n6816, n6818, n6820, n6822_1, n6823, n6825, + n6827_1, n6829, n6830, n6832_1, n6834, n6836, n6838, n6840, n6842_1, + n6843, n6845, n6847_1, n6849, n6850, n6852_1, n6854, n6856, n6857_1, + n6859, n6861, n6863, n6864, n6866, n6868, n6870, n6872_1, n6874, n6876, + n6877_1, n6879, n6881, n6883, n6884, n6886, n6888, n6890, n6891, n6893, + n6895, n6897_1, n6898, n6900, n6902_1, n6904, n6906, n6908, n6910, + n6911, n6913, n6915, n6917_1, n6918, n6920, n6922_1, n6924, n6925, + n6927, n6929, n6932, n6934, n6936_1, n6938, n6940, n6942, n6944, + n6946_1, n6948, n6949, n6950, n6951_1, n6952, n6953, n6955, n6957, + n6959, n6961_1, n6963, n6965, n6967, n6969, n6971_1, n6973, n6975, + n6977, n6978, n6979, n6980, n6981_1, n6982, n6983, n6985, n6987, n6989, + n6991_1, n6993, n6995, n6997, n6999, n7001_1, n7003, n7005, n7007, + n7009, n7011_1, n7013, n7015, n7017, n7019, n7021_1, n7023, n7025, + n7027, n7029, n7031_1, n7033, n7035, n7037, n7039, n7041_1, n7043, + n7045, n7047, n7049, n7051_1, n7053, n7055, n7057, n7059, n7061_1, + n7062, n7063, n7065, n7067, n7069, n7070, n7071_1, n7073, n7075, n7077, + n7078, n7079, n7081_1, n7083, n7085, n7086_1, n7087, n7089, n7091_1, + n7093, n7094, n7095, n7097, n7099, n7101_1, n7102, n7103, n7105, n7107, + n7109, n7110, n7111_1, n7113, n7115, n7117, n7118, n7119, n7121_1, + n7123, n7125, n7127, n7129, n7131_1, n7132, n7134, n7136_1, n7138, + n7139, n7141_1, n7143, n7145, n7147, n7149, n7151_1, n7153, n7155, + n7157, n7158, n7160_1, n7162, n7164, n7165, n7167_1, n7169, n7171, + n7173, n7175, n7177, n7179, n7181, n7183, n7184_1, n7186, n7188_1, + n7190, n7191, n7193, n7195, n7197, n7199, n7201, n7203, n7205, n7207, + n7209_1, n7210, n7212, n7214, n7216, n7217, n7219, n7221, n7223, n7225, + n7227, n7229, n7231, n7233, n7235, n7236, n7238_1, n7240, n7242_1, + n7243, n7245, n7247, n7249, n7251, n7253, n7255_1, n7257, n7259, n7261, + n7262, n7264, n7266, n7268, n7269, n7271, n7273, n7275, n7277, n7279, + n7281, n7283, n7285, n7287, n7288, n7290, n7292, n7294, n7295, n7297, + n7299, n7301, n7303, n7305, n7307, n7309, n7311, n7313, n7314, n7316, + n7318, n7320, n7321, n7323, n7325, n7327, n7329, n7331, n7333, n7335, + n7337, n7339, n7341, n7343, n7345, n7347, n7349, n7351, n7353, n7355, + n7357, n7359, n7361, n7363, n7365, n7367, n7369, n7371, n7373, n7375, + n7377, n7379, n7381, n7383, n7385, n7387, n7389, n7391, n7393, n7395, + n7397, n7399, n7401, n7403, n7405, n7407, n7409, n7411, n7413, n7415, + n7417, n7419, n7421, n7423, n7425, n7427, n7429, n7431, n7433, n7435, + n7437, n7439, n7441, n7443, n7445, n7447, n7449, n7451, n7453, n7455, + n7457, n7459, n7461, n7463, n7465, n7467, n7469, n7471, n7473, n7475, + n7477, n7479, n7481, n7483, n7485, n7487, n7489, n7491, n7493, n7495, + n7497, n7499, n7501, n7503, n7505, n7507, n7509, n7511, n7513, n7515, + n7517, n7519, n7521, n7523, n7525, n7527, n7529, n7531, n7533, n7535, + n7537, n7539, n7541, n7543, n7545, n7547, n7549, n7551, n7553, n7555, + n7557, n7559, n7561, n7563, n7565, n7567, n7569, n7571, n7573, n7575, + n7577, n7579, n7581, n7583, n7585, n7587, n7589, n7591, n7593, n7595, + n7597, n7599, n7601, n7603, n7605, n7607, n7609, n7611, n7613, n7615, + n7617, n7619, n7621, n7622, n7624, n7626, n7628, n7630, n7632, n7634, + n7636, n7638, n7640, n7642, n7644, n7646, n7648, n7650, n7652, n7654, + n7656, n7658, n7660, n7662, n7664, n7666, n7668, n7670, n7672, n7674, + n7676, n7678, n7680, n7682, n7684, n7686, n7688, n7690, n7692, n7694, + n7696, n7698, n7700, n7702, n7704, n7706, n7708, n7710, n7712, n7714, + n7716, n7718, n7720, n7722, n7724, n7726, n7728, n7730, n7732, n7734, + n7736, n7738, n7740, n7742, n7744, n7746, n7748, n7750, n7752, n7754, + n7756, n7758, n7760, n7762, n7764, n7766, n7768, n7770, n7772, n7774, + n7776, n7778, n7780, n7782, n7784, n7786, n7788, n7790, n7792, n7794, + n7796, n7798, n7800, n7802, n7804, n7806, n7808, n7810, n7812, n7814, + n7816, n7818, n7820, n7822, n7824, n7826, n7828, n7830, n7832, n7834, + n7836, n7838, n7840, n7842, n7844, n7846, n7848, n7850, n7852, n7854, + n7856, n7858, n7860, n7862, n7864, n7866, n7868, n7870, n7872, n7874, + n7876, n7878, n7880, n7882, n7884, n7886, n7888, n7890, n7892, n7894, + n7896, n7898, n7900, n7902, n7904, n7906, n7908, n7910, n7912, n7914, + n7916, n7918, n7920, n7922, n7924, n7926, n7928, n7930, n7932, n7934, + n7936, n7938, n7940, n7942, n7944, n7946, n7948, n7950, n7952, n7954, + n7956, n7958, n7960, n7962, n7964, n7966, n7968, n7970, n7972, n7974, + n7976, n7978, n7980, n7982, n7984, n7986, n7988, n7990, n7992, n7994, + n7996, n7998, n8000, n8002, n8004, n8006, n8008, n8010, n8012, n8014, + n8016, n8018, n8020, n8022, n8024, n8026, n8028, n8030, n8032, n8034, + n8036, n8038, n8040, n8042, n8044, n8046, n8048, n8050, n8052, n8054, + n8056, n8058, n8060, n8062, n8064, n8066, n8068, n8070, n8072, n8074, + n8076, n8078, n8080, n8082, n8084, n8086, n8088, n8090, n8092, n8094, + n8096, n8098, n8100, n8102, n8104, n8106, n8108, n8110, n8112, n8114, + n8116, n8118, n8120, n8122, n8124, n8126, n8128, n8130, n8132, n8134, + n8136, n8138, n8140, n8142, n8144, n8146, n8148, n8150, n8152, n8154, + n8156, n8158, n8160, n8162, n8164, n8166, n8168, n8170, n8172, n8174, + n8176, n8178, n8180, n8182, n8184, n8186, n8188, n8190, n8192, n8194, + n8196, n8198, n8200, n8202, n8204, n8206, n8208, n8210, n8212, n8214, + n8216, n8218, n8220, n8222, n8224, n8226, n8228, n8230, n8232, n8234, + n8236, n8238, n8240, n8242, n8244, n8246, n8248, n8250, n8252, n8254, + n8256, n8258, n8260, n8262, n8264, n8266, n8268, n8270, n8272, n8274, + n8276, n8278, n8280, n8282, n8284, n8286, n8288, n8290, n8292, n8294, + n8296, n8298, n8300, n8302, n8304, n8306, n8308, n8310, n8312, n8314, + n8316, n8318, n8320, n8322, n8324, n8326, n8328, n8330, n8332, n8334, + n8336, n8338, n8340, n8342, n8344, n8346, n8348, n8350, n8352, n8354, + n8356, n8358, n8360, n8362, n8364, n8366, n8368, n8370, n8372, n8374, + n8376, n8378, n8380, n8382, n8384, n8386, n8388, n8390, n8392, n8394, + n8396, n8398, n8400, n8402, n8404, n8406, n8408, n8410, n8412, n8414, + n8416, n8418, n8420, n8422, n8424, n8426, n8428, n8430, n8432, n8434, + n8436, n8438, n8440, n8442, n8444, n8446, n8448, n8450, n8451, n8452, + n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461, n8462, + n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471, n8472, + n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481, n8482, + n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491, n8492, + n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501, n8502, + n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511, n8512, + n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521, n8522, + n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8530, n8531, n8532, + n8533, n8534, n8535, n8536, n8537, n8538, n8539, n8540, n8541, n8542, + n8543, n8544, n8545, n8546, n8547, n8548, n8549, n8550, n8551, n8552, + n8553, n8554, n8555, n8556, n8557, n8558, n8559, n8560, n8561, n8562, + n8563, n8564, n8565, n8566, n8567, n8568, n8569, n8570, n8571, n8572, + n8573, n8574, n8575, n8576, n8577, n8578, n8579, n8580, n8581, n8582, + n8583, n8584, n8585, n8586, n8587, n8588, n8589, n8590, n8591, n8592, + n8593, n8594, n8595, n8596, n8597, n8598, n8599, n8600, n8601, n8603, + n8605, n8606, n8607, n8608, n8609, n8610, n8611, n8612, n8613, n8614, + n8615, n8616, n8617, n8618, n8619, n8620, n8621, n8622, n8623, n8624, + n8625, n8626, n8627, n8628, n8629, n8630, n8631, n8632, n8633, n8634, + n8635, n8636, n8637, n8638, n8639, n8640, n8641, n8642, n8643, n8644, + n8645, n8646, n8647, n8648, n8649, n8650, n8651, n8652, n8653, n8654, + n8655, n8656, n8657, n8658, n8659, n8660, n8661, n8662, n8663, n8664, + n8665, n8666, n8667, n8668, n8669, n8670, n8671, n8672, n8673, n8674, + n8675, n8676, n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, + n8685, n8686, n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, + n8695, n8696, n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, + n8705, n8706, n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, + n8715, n8716, n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, + n8725, n8726, n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, + n8735, n8736, n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, + n8745, n8746, n8747, n8748, n8749, n8750, n8752, n8753, n8754, n8755, + n8756, n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765, + n8766, n8767, n270_1, n274_1, n279_1, n284_1, n289_1, n294_1, n299_1, + n304_1, n309_1, n314_1, n319_1, n324_1, n329, n334_1, n339, n344, + n349_1, n353_1, n358_1, n362_1, n366_1, n370_1, n374_1, n378_1, n382_1, + n386, n390_1, n394, n398_1, n402_1, n406, n410_1, n414_1, n418_1, + n422_1, n426_1, n430_1, n435_1, n440_1, n445_1, n450_1, n455_1, n460_1, + n465, n470_1, n475_1, n480_1, n483_1, n488_1, n491_1, n496_1, n499_1, + n504_1, n507, n512_1, n515_1, n520_1, n523_1, n528_1, n531_1, n536_1, + n539_1, n544_1, n547_1, n552_1, n555_1, n560_1, n563_1, n568_1, n571_1, + n576_1, n579, n584_1, n587_1, n592_1, n595_1, n600_1, n603_1, n608_1, + n611_1, n616, n619_1, n624_1, n629_1, n634_1, n639_1, n644_1, n649_1, + n654_1, n659_1, n664_1, n669_1, n674, n679_1, n684_1, n689_1, n694, + n699_1, n704_1, n709_1, n714_1, n719_1, n724_1, n729, n734_1, n739_1, + n744_1, n749_1, n754_1, n759_1, n764_1, n769_1, n774, n779, n784_1, + n789_1, n794_1, n799_1, n804_1, n809_1, n814_1, n819_1, n824_1, n829_1, + n834_1, n839_1, n844_1, n848_1, n853_1, n858_1, n863_1, n868_1, n872_1, + n876_1, n880_1, n884_1, n888_1, n893_1, n898_1, n903_1, n908_1, n913_1, + n918_1, n923_1, n928, n933_1, n938_1, n943_1, n948_1, n953_1, n958, + n963_1, n968_1, n973_1, n978_1, n983_1, n988_1, n993_1, n998, n1003, + n1008_1, n1013_1, n1018, n1023_1, n1028_1, n1033, n1038_1, n1043_1, + n1048, n1053, n1058_1, n1063, n1068_1, n1073_1, n1078_1, n1083_1, + n1088_1, n1093_1, n1098_1, n1103_1, n1108, n1113_1, n1118_1, n1123_1, + n1128_1, n1133_1, n1138_1, n1143_1, n1148_1, n1153_1, n1158_1, n1163_1, + n1168_1, n1173_1, n1178, n1183_1, n1188_1, n1193_1, n1198_1, n1203_1, + n1208_1, n1213_1, n1218_1, n1223_1, n1228_1, n1233_1, n1238_1, n1243_1, + n1248_1, n1253_1, n1258_1, n1263_1, n1268, n1273_1, n1278, n1283_1, + n1288, n1293_1, n1298, n1303, n1308_1, n1313, n1318, n1323_1, n1328_1, + n1333_1, n1338_1, n1343_1, n1348, n1353, n1358_1, n1363_1, n1368, + n1373_1, n1378_1, n1383, n1388, n1393, n1398_1, n1403, n1408_1, n1413, + n1418_1, n1423_1, n1428_1, n1433_1, n1438_1, n1443_1, n1448_1, n1453, + n1458_1, n1463_1, n1468_1, n1473_1, n1478_1, n1483_1, n1488_1, n1493, + n1498, n1503, n1508, n1513_1, n1518_1, n1523_1, n1528, n1533_1, + n1537_1, n1542_1, n1546_1, n1551_1, n1555_1, n1560_1, n1564, n1569_1, + n1573, n1578, n1582_1, n1587, n1591, n1596, n1600_1, n1604_1, n1608, + n1613, n1618_1, n1623_1, n1627_1, n1631, n1635, n1639_1, n1643, + n1647_1, n1651, n1655, n1659_1, n1663_1, n1667, n1671_1, n1675_1, + n1679_1, n1683_1, n1687_1, n1691_1, n1695, n1699_1, n1703, n1707, + n1711_1, n1715, n1719, n1724_1, n1729_1, n1734_1, n1739_1, n1743, + n1747, n1752_1, n1756, n1761_1, n1765, n1770_1, n1774_1, n1779_1, + n1783_1, n1788, n1792_1, n1797_1, n1801_1, n1806_1, n1811_1, n1816_1, + n1821_1, n1825_1, n1829, n1833, n1838, n1843_1, n1848, n1853_1, + n1858_1, n1863, n1867_1, n1871_1, n1875_1, n1879_1, n1883_1, n1888, + n1892, n1897_1, n1902_1, n1906_1, n1911_1, n1915_1, n1920_1, n1925, + n1930_1, n1935_1, n1940_1, n1945_1, n1950, n1955, n1960_1, n1965, + n1970_1, n1975, n1980, n1985, n1990_1, n1995_1, n2000_1, n2005_1, + n2010, n2015_1, n2020_1, n2025_1, n2030, n2035_1, n2040, n2045_1, + n2050_1, n2054_1, n2059_1, n2064_1, n2067, n2072_1, n2077_1, n2082, + n2087_1, n2092_1, n2097_1, n2102_1, n2107_1, n2112, n2117_1, n2122_1, + n2127_1, n2132, n2137, n2142_1, n2147_1, n2152_1, n2157_1, n2162_1, + n2167_1, n2172_1, n2177, n2182_1, n2187_1, n2192_1, n2197, n2202, + n2207_1, n2212_1, n2217_1, n2222, n2227_1, n2232, n2237_1, n2242, + n2247_1, n2252, n2257_1, n2262, n2267, n2272, n2277, n2282, n2287, + n2292, n2297_1, n2302, n2307, n2312, n2317, n2322, n2327_1, n2332_1, + n2337, n2342, n2347, n2352, n2357, n2362_1, n2367_1, n2372, n2377, + n2382, n2387, n2391, n2395_1, n2399, n2404, n2409, n2414, n2419, + n2424_1, n2429_1, n2434, n2439, n2444_1, n2449, n2454, n2459, n2464, + n2469, n2474, n2479, n2484, n2489_1, n2494, n2499_1, n2504_1, n2509, + n2514_1, n2519_1, n2524_1, n2529, n2534_1, n2539, n2544, n2549, n2554, + n2559, n2564, n2569, n2574, n2579, n2584_1, n2589, n2594, n2599_1, + n2604, n2609, n2614, n2619_1, n2624, n2629, n2634, n2639, n2644, n2649, + n2654, n2659, n2664, n2669, n2674, n2679, n2684, n2689, n2694_1, + n2699_1, n2704_1, n2709, n2714_1, n2719, n2724_1, n2729_1, n2734_1, + n2739_1, n2744_1, n2749_1, n2754_1, n2759_1, n2764_1, n2769_1, n2774_1, + n2779_1, n2784_1, n2789_1, n2794_1, n2799_1, n2804_1, n2809_1, n2814_1, + n2819_1, n2824_1, n2829_1, n2834_1, n2839_1, n2844_1, n2849_1, n2854_1, + n2859_1, n2864_1, n2869_1, n2874_1, n2879_1, n2884_1, n2889, n2894, + n2899, n2904, n2909_1, n2914_1, n2919_1, n2924_1, n2929_1, n2934_1, + n2939_1, n2944_1, n2949_1, n2954_1, n2959_1, n2964_1, n2969_1, n2974_1, + n2979_1, n2984_1, n2989_1, n2994_1, n2999, n3004_1, n3009_1, n3014, + n3019_1, n3024_1, n3029_1, n3034_1, n3039_1, n3043_1, n3048_1, n3052_1, + n3057_1, n3061_1, n3066_1, n3070, n3075, n3079_1, n3084_1, n3088_1, + n3093_1, n3097_1, n3102, n3106_1, n3110_1, n3114_1, n3119_1, n3124_1, + n3129_1, n3133_1, n3137_1, n3141_1, n3145_1, n3149_1, n3153_1, n3157_1, + n3161_1, n3165_1, n3169_1, n3173_1, n3177_1, n3181_1, n3185_1, n3189_1, + n3193_1, n3197_1, n3201_1, n3205_1, n3209_1, n3213_1, n3217_1, n3221_1, + n3225_1, n3230_1, n3235_1, n3240_1, n3245_1, n3249_1, n3253_1, n3258_1, + n3262_1, n3267_1, n3271_1, n3276_1, n3280_1, n3285_1, n3289_1, n3294_1, + n3298_1, n3303_1, n3307_1, n3312_1, n3317_1, n3322_1, n3327_1, n3331_1, + n3335_1, n3339_1, n3344_1, n3349_1, n3354_1, n3359_1, n3364_1, n3369_1, + n3373_1, n3377_1, n3381_1, n3385_1, n3389_1, n3394_1, n3398_1, n3403_1, + n3408_1, n3412_1, n3417_1, n3421_1, n3426_1, n3431_1, n3436_1, n3441_1, + n3446_1, n3451_1, n3456_1, n3461_1, n3466_1, n3471_1, n3476_1, n3481_1, + n3486_1, n3491_1, n3496_1, n3501_1, n3506_1, n3511_1, n3516_1, n3521_1, + n3526_1, n3531_1, n3536_1, n3541_1, n3546_1, n3551_1, n3556_1, n3560_1, + n3565_1, n3570_1, n3573_1, n3578_1, n3583_1, n3588_1, n3593_1, n3598_1, + n3603_1, n3608_1, n3613_1, n3618_1, n3623_1, n3628_1, n3632_1, n3636_1, + n3641_1, n3646_1, n3651_1, n3656_1, n3661_1, n3666_1, n3671_1, n3676_1, + n3681_1, n3686_1, n3691_1, n3696_1, n3701_1, n3706_1, n3711_1, n3716_1, + n3721_1, n3726_1, n3731_1, n3736_1, n3741_1, n3746_1, n3751_1, n3756_1, + n3761, n3766_1, n3771, n3776_1, n3781_1, n3786, n3791, n3796_1, n3801, + n3806, n3811_1, n3816, n3821, n3826_1, n3831_1, n3836_1, n3841_1, + n3846_1, n3851_1, n3856_1, n3861_1, n3866, n3871_1, n3876_1, n3881_1, + n3886_1, n3891, n3896, n3901, n3906, n3911, n3916_1, n3921, n3926_1, + n3931, n3936, n3941_1, n3946, n3951, n3956, n3961_1, n3966, n3971, + n3976, n3981, n3986, n3991, n3996_1, n4001_1, n4006_1, n4011_1, + n4016_1, n4021, n4026, n4031_1, n4036, n4041_1, n4046, n4051, n4056, + n4061, n4066_1, n4071_1, n4076, n4081_1, n4086_1, n4091, n4096_1, + n4101, n4106, n4111_1, n4116_1, n4121, n4126, n4131, n4136_1, n4141, + n4146, n4151, n4156, n4161, n4166, n4171, n4176, n4181_1, n4186, + n4191_1, n4196, n4201, n4206, n4211, n4216, n4221, n4226, n4231, + n4236_1, n4241_1, n4246, n4251, n4256, n4261_1, n4266, n4271, n4276, + n4281_1, n4286, n4291_1, n4296, n4301, n4306_1, n4311_1, n4316, n4321, + n4326, n4331_1, n4336_1, n4341_1, n4346, n4351, n4356, n4361, n4366, + n4371, n4376, n4381, n4386, n4391, n4396, n4401, n4406, n4411, n4416, + n4421, n4426, n4431, n4436, n4441, n4446_1, n4451_1, n4456_1, n4461, + n4466, n4471, n4476, n4481, n4486, n4491, n4496, n4501, n4506_1, n4511, + n4516, n4521, n4526, n4531, n4536, n4541, n4546, n4550, n4555, n4559, + n4564, n4568, n4573, n4577, n4582, n4586, n4591, n4595, n4600, n4604, + n4609, n4613, n4617, n4621, n4626, n4631, n4636, n4640, n4644_1, n4648, + n4652, n4656, n4660, n4664, n4668, n4672, n4676, n4680, n4684, n4688, + n4692, n4696, n4700, n4704, n4708, n4712, n4716, n4720, n4724, n4728, + n4732, n4737, n4742, n4747, n4752, n4756, n4760, n4765, n4769, n4774, + n4778, n4783, n4787, n4792, n4796, n4801, n4805, n4810, n4814, n4819, + n4824, n4829, n4834, n4838, n4842, n4846, n4851, n4856, n4861, n4866, + n4871_1, n4876, n4880, n4884, n4888, n4892, n4896_1, n4901, n4905_1, + n4910, n4915, n4919, n4924, n4928, n4933, n4938, n4943, n4948, n4953, + n4958, n4963, n4968, n4973, n4978, n4983, n4988, n4993, n4998, n5003, + n5008, n5013, n5018, n5023, n5028, n5033, n5038, n5043, n5048, n5053, + n5058, n5063, n5067, n5072, n5077, n5080, n5085, n5090, n5095, n5100, + n5105, n5110, n5115, n5120, n5125, n5130, n5135, n5140, n5145, n5150, + n5155, n5160, n5165, n5170, n5175, n5180, n5185, n5190, n5195, n5200, + n5205, n5210, n5215, n5220, n5225, n5230, n5235, n5240, n5245, n5250, + n5255, n5260, n5265, n5270, n5275, n5280, n5285, n5290, n5295, n5300, + n5305, n5310, n5315, n5320, n5325, n5330, n5335, n5340, n5345, n5350, + n5355, n5360, n5365, n5370, n5375, n5380, n5385, n5390, n5395, n5400, + n5405, n5410, n5415, n5420, n5425, n5430, n5435, n5440, n5445, n5450, + n5455, n5460, n5465, n5470, n5475, n5480, n5485, n5490, n5495, n5500, + n5505, n5510, n5515, n5520, n5525, n5530, n5535, n5540, n5545, n5550, + n5555, n5560, n5565, n5570, n5575, n5580, n5585, n5590, n5595, n5600, + n5605, n5610, n5615, n5620, n5625, n5630, n5635, n5640, n5645, n5650, + n5655, n5660, n5665, n5670, n5675, n5680, n5685, n5690, n5695, n5700, + n5705, n5710, n5715, n5720, n5725, n5730, n5735, n5740, n5745, n5750, + n5755, n5760, n5765, n5770, n5775, n5780, n5785, n5790, n5795, n5800, + n5805, n5810, n5815, n5819, n5823, n5828, n5833, n5838, n5843, n5848, + n5853, n5858, n5863, n5868, n5873, n5878, n5883, n5888, n5893, n5898, + n5903, n5908, n5913, n5918, n5923, n5928, n5933, n5938, n5943, n5948, + n5953, n5958, n5963, n5968, n5973, n5978, n5983, n5988, n5993, n5998, + n6003, n6008, n6013, n6018, n6023, n6028, n6033, n6038, n6043, n6048, + n6053, n6057, n6062, n6066, n6071, n6075, n6080, n6084, n6089, n6093, + n6098, n6102, n6107, n6111, n6116, n6120, n6124, n6128, n6133, n6138, + n6143, n6147, n6151, n6155, n6159, n6163, n6167, n6171, n6175, n6179, + n6183, n6187, n6191, n6195, n6199, n6203, n6207, n6211, n6215, n6219, + n6223, n6227, n6231, n6235, n6239, n6244, n6249, n6254, n6259, n6263, + n6267, n6272, n6276, n6281, n6285, n6290, n6294, n6299, n6303, n6308, + n6312, n6317, n6321, n6326, n6331, n6336, n6341, n6345, n6349, n6353, + n6358, n6363, n6368, n6373, n6378, n6383, n6387, n6391, n6395, n6399, + n6403, n6408, n6412, n6417, n6422, n6426, n6431, n6435, n6440, n6445, + n6450, n6455, n6460, n6465, n6470, n6475, n6480, n6485, n6490, n6495, + n6500, n6505, n6510, n6515, n6520, n6525, n6530, n6535, n6540, n6545, + n6550, n6555, n6560, n6565, n6570, n6574, n6579, n6584, n6587, n6592, + n6597, n6602, n6607, n6612, n6617, n6622, n6627, n6632, n6637, n6642, + n6647, n6652, n6657, n6662, n6667, n6672, n6677, n6682, n6687, n6692, + n6697, n6702, n6707, n6712, n6717, n6722, n6727, n6732, n6737, n6742, + n6747, n6752, n6757, n6762, n6767, n6772, n6777, n6782, n6787, n6792, + n6797, n6802, n6807, n6812, n6817, n6822, n6827, n6832, n6837, n6842, + n6847, n6852, n6857, n6862, n6867, n6872, n6877, n6882, n6887, n6892, + n6897, n6902, n6907, n6912, n6917, n6922, n6926, n6931, n6936, n6941, + n6946, n6951, n6956, n6961, n6966, n6971, n6976, n6981, n6986, n6991, + n6996, n7001, n7006, n7011, n7016, n7021, n7026, n7031, n7036, n7041, + n7046, n7051, n7056, n7061, n7066, n7071, n7076, n7081, n7086, n7091, + n7096, n7101, n7106, n7111, n7116, n7121, n7126, n7131, n7136, n7141, + n7146, n7151, n7156, n7160, n7163, n7167, n7172, n7176, n7180, n7184, + n7188, n7192, n7196, n7200, n7204, n7209, n7213, n7218, n7222, n7226, + n7230, n7234, n7238, n7242, n7246, n7250, n7255, n7260; + assign Pg27380 = ~n893_1; + assign Pg26149 = ~n6140; + assign Pg26135 = ~n853_1; + assign Pg26104 = ~n6148; + assign Pg25489 = ~n7621; + assign n858_1 = ~Pg3233 | Pg3230; + assign Pg25435 = ~n863_1; + assign Pg24734 = ~n868_1; + assign Pg16496 = ~n4652_1; + assign n4530 = ~Pg8269 ^ ~Pg8268; + assign n4531_1 = ~Pg8271 ^ ~Pg8270; + assign n4532 = ~n4530 ^ ~n4531_1; + assign n4533 = ~Pg8262 ^ ~Pg8264; + assign n4534 = ~Pg8265 ^ ~Pg8266; + assign n4535 = ~n4533 ^ ~n4534; + assign n4536_1 = ~Pg8259 ^ ~Pg8261; + assign n4537 = ~Pg8260 ^ ~Pg8263; + assign n4538 = ~n4536_1 ^ ~n4537; + assign n4539 = ~Pg8272 ^ ~Pg8273; + assign n4540 = ~Pg8275 ^ ~Pg8274; + assign n4541_1 = ~n4539 ^ ~n4540; + assign n4542 = (~Ng1315 | ~Ng324) & (~\[1605] | ~Ng394); + assign n4543 = n4542 & (~\[1603] | ~Ng396); + assign n4544 = (~Ng1315 | ~Ng383) & (~\[1605] | ~Ng379); + assign n4545 = n4544 & (~\[1603] | ~Ng381); + assign n4546_1 = (~Ng1315 | ~Ng1011) & (~\[1605] | ~Ng1081); + assign n4547 = n4546_1 & (~\[1603] | ~Ng1083); + assign n4548 = (~Ng1315 | ~Ng368) & (~\[1605] | ~Ng364); + assign n4549 = n4548 & (~\[1603] | ~Ng366); + assign n4550_1 = (~Ng1315 | ~Ng1070) & (~\[1605] | ~Ng1066); + assign n4551 = n4550_1 & (~\[1603] | ~Ng1068); + assign n4552 = (~Ng1315 | ~Ng1705) & (~\[1605] | ~Ng1775); + assign n4553 = n4552 & (~\[1603] | ~Ng1777); + assign n4554 = (~Ng1315 | ~Ng353) & (~\[1605] | ~Ng349); + assign n4555_1 = n4554 & (~\[1603] | ~Ng351); + assign n4556 = (~Ng1315 | ~Ng1055) & (~\[1605] | ~Ng1051); + assign n4557 = n4556 & (~\[1603] | ~Ng1053); + assign n4558 = (~Ng1315 | ~Ng1764) & (~\[1605] | ~Ng1760); + assign n4559_1 = n4558 & (~\[1603] | ~Ng1762); + assign n4560 = (~Ng1315 | ~Ng2399) & (~\[1605] | ~Ng2469); + assign n4561 = n4560 & (~\[1603] | ~Ng2471); + assign n4562 = (~Ng1315 | ~Ng1040) & (~\[1605] | ~Ng1036); + assign n4563 = n4562 & (~\[1603] | ~Ng1038); + assign n4564_1 = (~Ng1315 | ~Ng1749) & (~\[1605] | ~Ng1745); + assign n4565 = n4564_1 & (~\[1603] | ~Ng1747); + assign n4566 = (~Ng1315 | ~Ng2458) & (~\[1605] | ~Ng2454); + assign n4567 = n4566 & (~\[1603] | ~Ng2456); + assign n4568_1 = (~Ng1315 | ~Ng1734) & (~\[1605] | ~Ng1730); + assign n4569 = n4568_1 & (~\[1603] | ~Ng1732); + assign n4570 = (~Ng1315 | ~Ng2443) & (~\[1605] | ~Ng2439); + assign n4571 = n4570 & (~\[1603] | ~Ng2441); + assign n4572 = (~Ng1315 | ~Ng2428) & (~\[1605] | ~Ng2424); + assign n4573_1 = n4572 & (~\[1603] | ~Ng2426); + assign n4574 = (~Ng1315 | ~Ng496) & (~\[1605] | ~Ng490); + assign n4575 = n4574 & (~\[1603] | ~Ng493); + assign n4576 = (~Ng1315 | ~Ng1183) & (~\[1605] | ~Ng1177); + assign n4577_1 = n4576 & (~\[1603] | ~Ng1180); + assign n4578 = (~Ng1315 | ~Ng1877) & (~\[1605] | ~Ng1871); + assign n4579 = n4578 & (~\[1603] | ~Ng1874); + assign n4580 = (~Ng1315 | ~Ng2571) & (~\[1605] | ~Ng2565); + assign n4581 = n4580 & (~\[1603] | ~Ng2568); + assign n4582_1 = (~Ng853 | Ng447) & (~\[1612] | Ng448); + assign n4583 = n4582_1 & (~\[1594] | Ng449); + assign n4584 = (~Ng853 | Ng402) & (~\[1612] | Ng403); + assign n4585 = n4584 & (~\[1594] | Ng404); + assign n4586_1 = (~\[1605] | Ng479) & (~\[1603] | Ng477); + assign n1888 = n4586_1 & (~Ng1315 | Ng478); + assign n4588 = (~\[1605] | Ng464) & (~\[1603] | Ng480); + assign n1902_1 = n4588 & (~Ng1315 | Ng484); + assign n4590 = (~Ng853 | Ng1134) & (~\[1612] | Ng1135); + assign n4591_1 = n4590 & (~\[1594] | Ng1136); + assign n4592 = (~Ng853 | Ng1089) & (~\[1612] | Ng1090); + assign n4593 = n4592 & (~\[1594] | Ng1091); + assign n4594 = (~\[1605] | Ng1166) & (~\[1603] | Ng1164); + assign n3394_1 = n4594 & (~Ng1315 | Ng1165); + assign n4596 = (~\[1605] | Ng488) & (~\[1603] | Ng486); + assign n1911_1 = n4596 & (~Ng1315 | Ng487); + assign n4598 = (~\[1605] | Ng1151) & (~\[1603] | Ng1167); + assign n3408_1 = n4598 & (~Ng1315 | Ng1171); + assign n4600_1 = (~Ng853 | Ng1828) & (~\[1612] | Ng1829); + assign n4601 = n4600_1 & (~\[1594] | Ng1830); + assign n4602 = (~Ng853 | Ng1783) & (~\[1612] | Ng1784); + assign n4603 = n4602 & (~\[1594] | Ng1785); + assign n4604_1 = (~\[1605] | Ng1860) & (~\[1603] | Ng1858); + assign n4901 = n4604_1 & (~Ng1315 | Ng1859); + assign n4606 = (~Ng1315 | ~Ng573) & (~\[1605] | ~Ng569); + assign n1739_1 = n4606 & (~\[1603] | ~Ng571); + assign n4608 = (~\[1605] | Ng1175) & (~\[1603] | Ng1173); + assign n3417_1 = n4608 & (~Ng1315 | Ng1174); + assign n4610 = (~\[1605] | Ng1845) & (~\[1603] | Ng1861); + assign n4915 = n4610 & (~Ng1315 | Ng1865); + assign n4612 = (~Ng853 | Ng2522) & (~\[1612] | Ng2523); + assign n4613_1 = n4612 & (~\[1594] | Ng2524); + assign n4614 = (~Ng853 | Ng2477) & (~\[1612] | Ng2478); + assign n4615 = n4614 & (~\[1594] | Ng2479); + assign n4616 = (~\[1605] | Ng2554) & (~\[1603] | Ng2552); + assign n6408 = n4616 & (~Ng1315 | Ng2553); + assign n4618 = (~Ng1315 | ~Ng1259) & (~\[1605] | ~Ng1255); + assign n3245_1 = n4618 & (~\[1603] | ~Ng1257); + assign n4620 = (~\[1605] | Ng1869) & (~\[1603] | Ng1867); + assign n4924 = n4620 & (~Ng1315 | Ng1868); + assign n4622 = (~\[1605] | Ng2539) & (~\[1603] | Ng2555); + assign n6422 = n4622 & (~Ng1315 | Ng2559); + assign n4624 = (~Ng853 | Ng321) & (~\[1612] | Ng322); + assign n4625 = n4624 & (~\[1594] | Ng323); + assign n4626_1 = (~Ng1315 | ~Ng1953) & (~\[1605] | ~Ng1949); + assign n4752 = n4626_1 & (~\[1603] | ~Ng1951); + assign n4628 = (~\[1605] | Ng2563) & (~\[1603] | Ng2561); + assign n6431 = n4628 & (~Ng1315 | Ng2562); + assign n4630 = (~Ng1315 | ~Ng489) & (~\[1605] | ~Ng565); + assign n1875_1 = n4630 & (~\[1603] | ~Ng567); + assign n4632 = (~Ng853 | Ng1008) & (~\[1612] | Ng1009); + assign n4633 = n4632 & (~\[1594] | Ng1010); + assign n4634 = (~Ng1315 | ~Ng2647) & (~\[1605] | ~Ng2643); + assign n6259 = n4634 & (~\[1603] | ~Ng2645); + assign n4636_1 = (~Ng1315 | ~Ng1176) & (~\[1605] | ~Ng1251); + assign n3381_1 = n4636_1 & (~\[1603] | ~Ng1253); + assign n4638 = (~Ng853 | Ng1702) & (~\[1612] | Ng1703); + assign n4639 = n4638 & (~\[1594] | Ng1704); + assign n4640_1 = (~Ng1315 | ~Ng1870) & (~\[1605] | ~Ng1945); + assign n4888 = n4640_1 & (~\[1603] | ~Ng1947); + assign n4642 = (~Ng853 | Ng2396) & (~\[1612] | Ng2397); + assign n4643 = n4642 & (~\[1594] | Ng2398); + assign n4644 = (~Ng1315 | ~Ng2564) & (~\[1605] | ~Ng2639); + assign n6395 = n4644 & (~\[1603] | ~Ng2641); + assign n4646 = (~Ng853 | Ng141) & (~\[1594] | Ng143); + assign n4647 = n4646 & (~\[1612] | Ng142); + assign n4648_1 = (~Ng853 | Ng144) & (~\[1594] | Ng146); + assign n4649 = n4648_1 & (~\[1612] | Ng145); + assign n4650 = (~Ng853 | Ng829) & (~\[1594] | Ng831); + assign n4651 = n4650 & (~\[1612] | Ng830); + assign n4652_1 = Ng2987 & (~Pg5388 | Ng2986); + assign n4653 = (~Ng853 | Ng147) & (~\[1594] | Ng149); + assign n4654 = n4653 & (~\[1612] | Ng148); + assign n4655 = (~Ng853 | Ng832) & (~\[1594] | Ng834); + assign n4656_1 = n4655 & (~\[1612] | Ng833); + assign n4657 = (~Ng853 | Ng1523) & (~\[1594] | Ng1525); + assign n4658 = n4657 & (~\[1612] | Ng1524); + assign n4659 = (~Ng853 | Ng150) & (~\[1594] | Ng152); + assign n4660_1 = n4659 & (~\[1612] | Ng151); + assign n4661 = (~\[1594] | ~Ng216) & (~Ng853 | ~Ng219); + assign n4662 = n4661 & (~\[1612] | ~Ng213); + assign n4663 = (~Ng853 | Ng835) & (~\[1594] | Ng837); + assign n4664_1 = n4663 & (~\[1612] | Ng836); + assign n4665 = (~Ng853 | Ng1526) & (~\[1594] | Ng1528); + assign n4666 = n4665 & (~\[1612] | Ng1527); + assign n4667 = (~Ng853 | Ng2217) & (~\[1594] | Ng2219); + assign n4668_1 = n4667 & (~\[1612] | Ng2218); + assign n4669 = (~Ng853 | Ng153) & (~\[1612] | Ng154); + assign n4670 = n4669 & (~\[1594] | Ng155); + assign n4671 = (~\[1612] | ~Ng222) & (~\[1594] | ~Ng225); + assign n4672_1 = n4671 & (~Ng853 | ~Ng228); + assign n4673 = (~Ng853 | Ng838) & (~\[1612] | Ng839); + assign n4674 = n4673 & (~\[1594] | Ng840); + assign n4675 = (~\[1612] | ~Ng900) & (~\[1594] | ~Ng903); + assign n4676_1 = n4675 & (~Ng853 | ~Ng906); + assign n4677 = (~Ng853 | Ng1529) & (~\[1612] | Ng1530); + assign n4678 = n4677 & (~\[1594] | Ng1531); + assign n4679 = (~Ng853 | Ng2220) & (~\[1612] | Ng2221); + assign n4680_1 = n4679 & (~\[1594] | Ng2222); + assign n4681 = (~Ng853 | Ng156) & (~\[1612] | Ng157); + assign n4682 = n4681 & (~\[1594] | Ng158); + assign n4683 = (~Ng853 | ~Ng237) & (~\[1612] | ~Ng231); + assign n4684_1 = n4683 & (~\[1594] | ~Ng234); + assign n4685 = (~Ng1315 | Ng698) & (~\[1605] | Ng699); + assign n4686 = n4685 & (~\[1603] | Ng700); + assign n4687 = (~Ng1315 | Ng725) & (~\[1605] | Ng726); + assign n4688_1 = n4687 & (~\[1603] | Ng727); + assign n4689 = (~Ng853 | Ng841) & (~\[1612] | Ng842); + assign n4690 = n4689 & (~\[1594] | Ng843); + assign n4691 = (~Ng853 | ~Ng915) & (~\[1612] | ~Ng909); + assign n4692_1 = n4691 & (~\[1594] | ~Ng912); + assign n4693 = (~Ng853 | Ng1532) & (~\[1612] | Ng1533); + assign n4694 = n4693 & (~\[1594] | Ng1534); + assign n4695 = (~Ng853 | ~Ng1600) & (~\[1612] | ~Ng1594); + assign n4696_1 = n4695 & (~\[1594] | ~Ng1597); + assign n4697 = (~Ng853 | Ng2223) & (~\[1612] | Ng2224); + assign n4698 = n4697 & (~\[1594] | Ng2225); + assign n4699 = (~Ng853 | Ng159) & (~\[1612] | Ng160); + assign n4700_1 = n4699 & (~\[1594] | Ng161); + assign n4701 = (~Ng853 | ~Ng246) & (~\[1612] | ~Ng240); + assign n4702 = n4701 & (~\[1594] | ~Ng243); + assign n4703 = (~Ng1315 | Ng701) & (~\[1605] | Ng702); + assign n4704_1 = n4703 & (~\[1603] | Ng703); + assign n4705 = (~Ng853 | Ng844) & (~\[1612] | Ng845); + assign n4706 = n4705 & (~\[1594] | Ng846); + assign n4707 = (~Ng853 | ~Ng924) & (~\[1612] | ~Ng918); + assign n4708_1 = n4707 & (~\[1594] | ~Ng921); + assign n4709 = (~Ng1315 | Ng1384) & (~\[1605] | Ng1385); + assign n4710 = n4709 & (~\[1603] | Ng1386); + assign n4711 = (~Ng1315 | Ng1411) & (~\[1605] | Ng1412); + assign n4712_1 = n4711 & (~\[1603] | Ng1413); + assign n4713 = (~Ng853 | Ng1535) & (~\[1612] | Ng1536); + assign n4714 = n4713 & (~\[1594] | Ng1537); + assign n4715 = (~Ng853 | ~Ng1609) & (~\[1612] | ~Ng1603); + assign n4716_1 = n4715 & (~\[1594] | ~Ng1606); + assign n4717 = (~Ng853 | Ng2226) & (~\[1612] | Ng2227); + assign n4718 = n4717 & (~\[1594] | Ng2228); + assign n4719 = (~Ng853 | ~Ng2294) & (~\[1612] | ~Ng2288); + assign n4720_1 = n4719 & (~\[1594] | ~Ng2291); + assign n4721 = (~Ng853 | Ng129) & (~\[1612] | Ng130); + assign n4722 = n4721 & (~\[1594] | Ng131); + assign n4723 = (~Ng853 | Ng162) & (~\[1612] | Ng163); + assign n4724_1 = n4723 & (~\[1594] | Ng164); + assign n4725 = (~Ng853 | ~Ng255) & (~\[1612] | ~Ng249); + assign n4726 = n4725 & (~\[1594] | ~Ng252); + assign n4727 = (~Ng1315 | Ng704) & (~\[1605] | Ng705); + assign n4728_1 = n4727 & (~\[1603] | Ng706); + assign n4729 = (~Ng853 | Ng847) & (~\[1612] | Ng848); + assign n4730 = n4729 & (~\[1594] | Ng849); + assign n4731 = (~Ng853 | ~Ng933) & (~\[1612] | ~Ng927); + assign n4732_1 = n4731 & (~\[1594] | ~Ng930); + assign n4733 = (~Ng1315 | Ng1387) & (~\[1605] | Ng1388); + assign n4734 = n4733 & (~\[1603] | Ng1389); + assign n4735 = (~Ng853 | Ng1538) & (~\[1612] | Ng1539); + assign n4736 = n4735 & (~\[1594] | Ng1540); + assign n4737_1 = (~Ng853 | ~Ng1618) & (~\[1612] | ~Ng1612); + assign n4738 = n4737_1 & (~\[1594] | ~Ng1615); + assign n4739 = (~Ng1315 | Ng2078) & (~\[1605] | Ng2079); + assign n4740 = n4739 & (~\[1603] | Ng2080); + assign n4741 = (~Ng1315 | Ng2105) & (~\[1605] | Ng2106); + assign n4742_1 = n4741 & (~\[1603] | Ng2107); + assign n4743 = (~Ng853 | Ng2229) & (~\[1612] | Ng2230); + assign n4744 = n4743 & (~\[1594] | Ng2231); + assign n4745 = (~Ng853 | ~Ng2303) & (~\[1612] | ~Ng2297); + assign n4746 = n4745 & (~\[1594] | ~Ng2300); + assign n4747_1 = (~Ng853 | Ng132) & (~\[1612] | Ng133); + assign n4748 = n4747_1 & (~\[1594] | Ng134); + assign n4749 = (~Ng853 | ~Ng264) & (~\[1612] | ~Ng258); + assign n4750 = n4749 & (~\[1594] | ~Ng261); + assign n4751 = (~Ng853 | Ng11499) & (~\[1612] | Ng11497); + assign n4752_1 = n4751 & (~\[1594] | Ng11498); + assign n4753 = (~Ng853 | ~Ng435) & (~\[1612] | ~Ng429); + assign n4754 = n4753 & (~\[1594] | ~Ng432); + assign n4755 = (~Ng1315 | Ng707) & (~\[1605] | Ng708); + assign n4756_1 = n4755 & (~\[1603] | Ng709); + assign n4757 = (~Ng853 | Ng817) & (~\[1612] | Ng818); + assign n4758 = n4757 & (~\[1594] | Ng819); + assign n4759 = (~Ng853 | Ng850) & (~\[1612] | Ng851); + assign n4760_1 = n4759 & (~\[1594] | Ng852); + assign n4761 = (~Ng853 | ~Ng942) & (~\[1612] | ~Ng936); + assign n4762 = n4761 & (~\[1594] | ~Ng939); + assign n4763 = (~Ng1315 | Ng1390) & (~\[1605] | Ng1391); + assign n4764 = n4763 & (~\[1603] | Ng1392); + assign n4765_1 = (~Ng853 | Ng1541) & (~\[1612] | Ng1542); + assign n4766 = n4765_1 & (~\[1594] | Ng1543); + assign n4767 = (~Ng853 | ~Ng1627) & (~\[1612] | ~Ng1621); + assign n4768 = n4767 & (~\[1594] | ~Ng1624); + assign n4769_1 = (~Ng1315 | Ng2081) & (~\[1605] | Ng2082); + assign n4770 = n4769_1 & (~\[1603] | Ng2083); + assign n4771 = (~Ng853 | Ng2232) & (~\[1612] | Ng2233); + assign n4772 = n4771 & (~\[1594] | Ng2234); + assign n4773 = (~Ng853 | ~Ng2312) & (~\[1612] | ~Ng2306); + assign n4774_1 = n4773 & (~\[1594] | ~Ng2309); + assign n4775 = (~Ng1315 | Ng2772) & (~\[1605] | Ng2773); + assign n4776 = n4775 & (~\[1603] | Ng2774); + assign n4777 = (~Ng1315 | Ng2799) & (~\[1605] | Ng2800); + assign n4778_1 = n4777 & (~\[1603] | Ng2801); + assign n4779 = (~Ng853 | ~Ng192) & (~\[1612] | ~Ng186); + assign n4780 = n4779 & (~\[1594] | ~Ng189); + assign n4781 = (~Ng853 | ~Ng273) & (~\[1612] | ~Ng267); + assign n4782 = n4781 & (~\[1594] | ~Ng270); + assign n4783_1 = (~Ng853 | Ng11502) & (~\[1612] | Ng11500); + assign n4784 = n4783_1 & (~\[1594] | Ng11501); + assign n4785 = (~Ng853 | ~Ng444) & (~\[1612] | ~Ng438); + assign n4786 = n4785 & (~\[1594] | ~Ng441); + assign n4787_1 = (~Ng1315 | Ng710) & (~\[1605] | Ng711); + assign n4788 = n4787_1 & (~\[1603] | Ng712); + assign n4789 = (~Ng853 | Ng820) & (~\[1612] | Ng821); + assign n4790 = n4789 & (~\[1594] | Ng822); + assign n4791 = (~Ng853 | ~Ng951) & (~\[1612] | ~Ng945); + assign n4792_1 = n4791 & (~\[1594] | ~Ng948); + assign n4793 = (~Ng853 | Ng11526) & (~\[1612] | Ng11524); + assign n4794 = n4793 & (~\[1594] | Ng11525); + assign n4795 = (~Ng853 | ~Ng1122) & (~\[1612] | ~Ng1116); + assign n4796_1 = n4795 & (~\[1594] | ~Ng1119); + assign n4797 = (~Ng1315 | Ng1393) & (~\[1605] | Ng1394); + assign n4798 = n4797 & (~\[1603] | Ng1395); + assign n4799 = (~Ng853 | Ng1511) & (~\[1612] | Ng1512); + assign n4800 = n4799 & (~\[1594] | Ng1513); + assign n4801_1 = (~Ng853 | Ng1544) & (~\[1612] | Ng1545); + assign n4802 = n4801_1 & (~\[1594] | Ng1546); + assign n4803 = (~Ng853 | ~Ng1636) & (~\[1612] | ~Ng1630); + assign n4804 = n4803 & (~\[1594] | ~Ng1633); + assign n4805_1 = (~Ng1315 | Ng2084) & (~\[1605] | Ng2085); + assign n4806 = n4805_1 & (~\[1603] | Ng2086); + assign n4807 = (~Ng853 | Ng2235) & (~\[1612] | Ng2236); + assign n4808 = n4807 & (~\[1594] | Ng2237); + assign n4809 = (~Ng853 | ~Ng2321) & (~\[1612] | ~Ng2315); + assign n4810_1 = n4809 & (~\[1594] | ~Ng2318); + assign n4811 = (~Ng1315 | Ng2775) & (~\[1605] | Ng2776); + assign n4812 = n4811 & (~\[1603] | Ng2777); + assign n4813 = (~Ng853 | ~Ng201) & (~\[1612] | ~Ng195); + assign n4814_1 = n4813 & (~\[1594] | ~Ng198); + assign n4815 = (~Ng853 | Ng11505) & (~\[1612] | Ng11503); + assign n4816 = n4815 & (~\[1594] | Ng11504); + assign n4817 = (~Ng1315 | Ng713) & (~\[1605] | Ng714); + assign n4818 = n4817 & (~\[1603] | Ng715); + assign n4819_1 = (~Ng1315 | Ng731) & (~\[1605] | Ng732); + assign n4820 = n4819_1 & (~\[1603] | Ng733); + assign n4821 = (~Ng853 | ~Ng879) & (~\[1612] | ~Ng873); + assign n4822 = n4821 & (~\[1594] | ~Ng876); + assign n4823 = (~Ng853 | ~Ng960) & (~\[1612] | ~Ng954); + assign n4824_1 = n4823 & (~\[1594] | ~Ng957); + assign n4825 = (~Ng853 | Ng11529) & (~\[1612] | Ng11527); + assign n4826 = n4825 & (~\[1594] | Ng11528); + assign n4827 = (~Ng853 | ~Ng1131) & (~\[1612] | ~Ng1125); + assign n4828 = n4827 & (~\[1594] | ~Ng1128); + assign n4829_1 = (~Ng1315 | Ng1396) & (~\[1605] | Ng1397); + assign n4830 = n4829_1 & (~\[1603] | Ng1398); + assign n4831 = (~Ng853 | Ng1514) & (~\[1612] | Ng1515); + assign n4832 = n4831 & (~\[1594] | Ng1516); + assign n4833 = (~Ng853 | ~Ng1645) & (~\[1612] | ~Ng1639); + assign n4834_1 = n4833 & (~\[1594] | ~Ng1642); + assign n4835 = (~Ng853 | Ng11553) & (~\[1612] | Ng11551); + assign n4836 = n4835 & (~\[1594] | Ng11552); + assign n4837 = (~Ng853 | ~Ng1816) & (~\[1612] | ~Ng1810); + assign n4838_1 = n4837 & (~\[1594] | ~Ng1813); + assign n4839 = (~Ng1315 | Ng2087) & (~\[1605] | Ng2088); + assign n4840 = n4839 & (~\[1603] | Ng2089); + assign n4841 = (~Ng853 | Ng2205) & (~\[1612] | Ng2206); + assign n4842_1 = n4841 & (~\[1594] | Ng2207); + assign n4843 = (~Ng853 | Ng2238) & (~\[1612] | Ng2239); + assign n4844 = n4843 & (~\[1594] | Ng2240); + assign n4845 = (~Ng853 | ~Ng2330) & (~\[1612] | ~Ng2324); + assign n4846_1 = n4845 & (~\[1594] | ~Ng2327); + assign n4847 = (~Ng1315 | Ng2778) & (~\[1605] | Ng2779); + assign n4848 = n4847 & (~\[1603] | Ng2780); + assign n4849 = (~Ng853 | ~Ng210) & (~\[1612] | ~Ng204); + assign n4850 = n4849 & (~\[1594] | ~Ng207); + assign n4851_1 = (~Ng853 | Ng11508) & (~\[1612] | Ng11506); + assign n4852 = n4851_1 & (~\[1594] | Ng11507); + assign n4853 = (~Ng1315 | Ng716) & (~\[1605] | Ng717); + assign n4854 = n4853 & (~\[1603] | Ng718); + assign n4855 = (~Ng853 | ~Ng888) & (~\[1612] | ~Ng882); + assign n4856_1 = n4855 & (~\[1594] | ~Ng885); + assign n4857 = (~Ng853 | Ng11532) & (~\[1612] | Ng11530); + assign n4858 = n4857 & (~\[1594] | Ng11531); + assign n4859 = (~Ng1315 | Ng1399) & (~\[1605] | Ng1400); + assign n4860 = n4859 & (~\[1603] | Ng1401); + assign n4861_1 = (~Ng1315 | Ng1417) & (~\[1605] | Ng1418); + assign n4862 = n4861_1 & (~\[1603] | Ng1419); + assign n4863 = (~Ng853 | ~Ng1573) & (~\[1612] | ~Ng1567); + assign n4864 = n4863 & (~\[1594] | ~Ng1570); + assign n4865 = (~Ng853 | ~Ng1654) & (~\[1612] | ~Ng1648); + assign n4866_1 = n4865 & (~\[1594] | ~Ng1651); + assign n4867 = (~Ng853 | Ng11556) & (~\[1612] | Ng11554); + assign n4868 = n4867 & (~\[1594] | Ng11555); + assign n4869 = (~Ng853 | ~Ng1825) & (~\[1612] | ~Ng1819); + assign n4870 = n4869 & (~\[1594] | ~Ng1822); + assign n4871 = (~Ng1315 | Ng2090) & (~\[1605] | Ng2091); + assign n4872 = n4871 & (~\[1603] | Ng2092); + assign n4873 = (~Ng853 | Ng2208) & (~\[1612] | Ng2209); + assign n4874 = n4873 & (~\[1594] | Ng2210); + assign n4875 = (~Ng853 | ~Ng2339) & (~\[1612] | ~Ng2333); + assign n4876_1 = n4875 & (~\[1594] | ~Ng2336); + assign n4877 = (~Ng853 | Ng11580) & (~\[1612] | Ng11578); + assign n4878 = n4877 & (~\[1594] | Ng11579); + assign n4879 = (~Ng853 | ~Ng2510) & (~\[1612] | ~Ng2504); + assign n4880_1 = n4879 & (~\[1594] | ~Ng2507); + assign n4881 = (~Ng1315 | Ng2781) & (~\[1605] | Ng2782); + assign n4882 = n4881 & (~\[1603] | Ng2783); + assign n4883 = (~Ng853 | Ng168) & (~\[1594] | Ng170); + assign n4884_1 = n4883 & (~\[1612] | Ng169); + assign n4885 = (~Ng1315 | Ng719) & (~\[1605] | Ng720); + assign n4886 = n4885 & (~\[1603] | Ng721); + assign n4887 = (~Ng853 | ~Ng897) & (~\[1612] | ~Ng891); + assign n4888_1 = n4887 & (~\[1594] | ~Ng894); + assign n4889 = (~Ng853 | Ng11535) & (~\[1612] | Ng11533); + assign n4890 = n4889 & (~\[1594] | Ng11534); + assign n4891 = (~Ng1315 | Ng1402) & (~\[1605] | Ng1403); + assign n4892_1 = n4891 & (~\[1603] | Ng1404); + assign n4893 = (~Ng853 | ~Ng1582) & (~\[1612] | ~Ng1576); + assign n4894 = n4893 & (~\[1594] | ~Ng1579); + assign n4895 = (~Ng853 | Ng11559) & (~\[1612] | Ng11557); + assign n4896 = n4895 & (~\[1594] | Ng11558); + assign n4897 = (~Ng1315 | Ng2093) & (~\[1605] | Ng2094); + assign n4898 = n4897 & (~\[1603] | Ng2095); + assign n4899 = (~Ng1315 | Ng2111) & (~\[1605] | Ng2112); + assign n4900 = n4899 & (~\[1603] | Ng2113); + assign n4901_1 = (~Ng853 | ~Ng2267) & (~\[1612] | ~Ng2261); + assign n4902 = n4901_1 & (~\[1594] | ~Ng2264); + assign n4903 = (~Ng853 | ~Ng2348) & (~\[1612] | ~Ng2342); + assign n4904 = n4903 & (~\[1594] | ~Ng2345); + assign n4905 = (~Ng853 | Ng11583) & (~\[1612] | Ng11581); + assign n4906 = n4905 & (~\[1594] | Ng11582); + assign n4907 = (~Ng853 | ~Ng2519) & (~\[1612] | ~Ng2513); + assign n4908 = n4907 & (~\[1594] | ~Ng2516); + assign n4909 = (~Ng1315 | Ng2784) & (~\[1605] | Ng2785); + assign n4910_1 = n4909 & (~\[1603] | Ng2786); + assign n4911 = (~Ng1315 | Ng722) & (~\[1605] | Ng723); + assign n4912 = n4911 & (~\[1603] | Ng724); + assign n4913 = (~Ng853 | Ng856) & (~\[1594] | Ng858); + assign n4914 = n4913 & (~\[1612] | Ng857); + assign n4915_1 = (~Ng1315 | Ng1405) & (~\[1605] | Ng1406); + assign n4916 = n4915_1 & (~\[1603] | Ng1407); + assign n4917 = (~Ng853 | ~Ng1591) & (~\[1612] | ~Ng1585); + assign n4918 = n4917 & (~\[1594] | ~Ng1588); + assign n4919_1 = (~Ng853 | Ng11562) & (~\[1612] | Ng11560); + assign n4920 = n4919_1 & (~\[1594] | Ng11561); + assign n4921 = (~Ng1315 | Ng2096) & (~\[1605] | Ng2097); + assign n4922 = n4921 & (~\[1603] | Ng2098); + assign n4923 = (~Ng853 | ~Ng2276) & (~\[1612] | ~Ng2270); + assign n4924_1 = n4923 & (~\[1594] | ~Ng2273); + assign n4925 = (~Ng853 | Ng11586) & (~\[1612] | Ng11584); + assign n4926 = n4925 & (~\[1594] | Ng11585); + assign n4927 = (~Ng1315 | Ng2787) & (~\[1605] | Ng2788); + assign n4928_1 = n4927 & (~\[1603] | Ng2789); + assign n4929 = (~Ng1315 | Ng2805) & (~\[1605] | Ng2806); + assign n4930 = n4929 & (~\[1603] | Ng2807); + assign n4931 = (~Ng1315 | Ng1408) & (~\[1605] | Ng1409); + assign n4932 = n4931 & (~\[1603] | Ng1410); + assign n4933_1 = (~Ng853 | Ng1550) & (~\[1612] | Ng1551); + assign n4934 = n4933_1 & (~\[1594] | Ng1552); + assign n4935 = (~Ng1315 | Ng2099) & (~\[1605] | Ng2100); + assign n4936 = n4935 & (~\[1603] | Ng2101); + assign n4937 = (~Ng853 | ~Ng2285) & (~\[1612] | ~Ng2279); + assign n4938_1 = n4937 & (~\[1594] | ~Ng2282); + assign n4939 = (~Ng853 | Ng11589) & (~\[1612] | Ng11587); + assign n4940 = n4939 & (~\[1594] | Ng11588); + assign n4941 = (~Ng1315 | Ng2790) & (~\[1605] | Ng2791); + assign n4942 = n4941 & (~\[1603] | Ng2792); + assign n4943_1 = (~Ng1315 | Ng2102) & (~\[1605] | Ng2103); + assign n4944 = n4943_1 & (~\[1603] | Ng2104); + assign n4945 = (~Ng853 | Ng2244) & (~\[1612] | Ng2245); + assign n4946 = n4945 & (~\[1594] | Ng2246); + assign n4947 = (~Ng1315 | Ng2793) & (~\[1605] | Ng2794); + assign n4948_1 = n4947 & (~\[1603] | Ng2795); + assign n4949 = (~Ng853 | Ng314) & (~\[1612] | Ng312); + assign n4950 = n4949 & (~\[1594] | Ng313); + assign n4951 = (~Ng1315 | Ng2796) & (~\[1605] | Ng2797); + assign n4952 = n4951 & (~\[1603] | Ng2798); + assign n4953_1 = (~Ng853 | Ng317) & (~\[1612] | Ng315); + assign n4954 = n4953_1 & (~\[1594] | Ng316); + assign n4955 = (~Ng853 | Ng1001) & (~\[1612] | Ng999); + assign n4956 = n4955 & (~\[1594] | Ng1000); + assign n4957 = (~Ng853 | Ng320) & (~\[1612] | Ng318); + assign n4958_1 = n4957 & (~\[1594] | Ng319); + assign n4959 = (~Ng853 | Ng1004) & (~\[1612] | Ng1002); + assign n4960 = n4959 & (~\[1594] | Ng1003); + assign n4961 = (~Ng853 | Ng1695) & (~\[1612] | Ng1693); + assign n4962 = n4961 & (~\[1594] | Ng1694); + assign n4963_1 = (~Ng1315 | ~Ng620) & (~\[1605] | ~Ng614); + assign n4964 = n4963_1 & (~\[1603] | ~Ng617); + assign n4965 = (~Ng853 | Ng1007) & (~\[1612] | Ng1005); + assign n4966 = n4965 & (~\[1594] | Ng1006); + assign n4967 = (~Ng853 | Ng1698) & (~\[1612] | Ng1696); + assign n4968_1 = n4967 & (~\[1594] | Ng1697); + assign n4969 = (~Ng853 | Ng2389) & (~\[1612] | Ng2387); + assign n4970 = n4969 & (~\[1594] | Ng2388); + assign n4971 = (~Ng1315 | ~Ng1306) & (~\[1605] | ~Ng1300); + assign n4972 = n4971 & (~\[1603] | ~Ng1303); + assign n4973_1 = (~Ng853 | Ng1701) & (~\[1612] | Ng1699); + assign n4974 = n4973_1 & (~\[1594] | Ng1700); + assign n4975 = (~Ng853 | Ng2392) & (~\[1612] | Ng2390); + assign n4976 = n4975 & (~\[1594] | Ng2391); + assign n4977 = (~Ng1315 | ~Ng2000) & (~\[1605] | ~Ng1994); + assign n4978_1 = n4977 & (~\[1603] | ~Ng1997); + assign n4979 = (~Ng853 | Ng2395) & (~\[1612] | Ng2393); + assign n4980 = n4979 & (~\[1594] | Ng2394); + assign n4981 = (~Ng1315 | ~Ng2694) & (~\[1605] | ~Ng2688); + assign n4982 = n4981 & (~\[1603] | ~Ng2691); + assign n4983_1 = (~Ng1315 | Ng575) & (~\[1605] | Ng576); + assign n4984 = n4983_1 & (~\[1603] | Ng577); + assign n4985 = (~Ng1315 | Ng578) & (~\[1605] | Ng579); + assign n4986 = n4985 & (~\[1603] | Ng580); + assign n4987 = (~Ng1315 | Ng1261) & (~\[1605] | Ng1262); + assign n4988_1 = n4987 & (~\[1603] | Ng1263); + assign n4989 = (~Ng853 | ~Ng414) & (~\[1612] | ~Ng408); + assign n4990 = n4989 & (~\[1594] | ~Ng411); + assign n4991 = (~Ng1315 | Ng581) & (~\[1605] | Ng582); + assign n4992 = n4991 & (~\[1603] | Ng583); + assign n4993_1 = (~Ng1315 | Ng1264) & (~\[1605] | Ng1265); + assign n4994 = n4993_1 & (~\[1603] | Ng1266); + assign n4995 = (~Ng1315 | Ng1955) & (~\[1605] | Ng1956); + assign n4996 = n4995 & (~\[1603] | Ng1957); + assign n4997 = (~Ng853 | ~Ng423) & (~\[1612] | ~Ng417); + assign n4998_1 = n4997 & (~\[1594] | ~Ng420); + assign n4999 = (~Ng1315 | Ng584) & (~\[1605] | Ng585); + assign n5000 = n4999 & (~\[1603] | Ng586); + assign n5001 = (~Ng853 | ~Ng1101) & (~\[1612] | ~Ng1095); + assign n5002 = n5001 & (~\[1594] | ~Ng1098); + assign n5003_1 = (~Ng1315 | Ng1267) & (~\[1605] | Ng1268); + assign n5004 = n5003_1 & (~\[1603] | Ng1269); + assign n5005 = (~Ng1315 | Ng1958) & (~\[1605] | Ng1959); + assign n5006 = n5005 & (~\[1603] | Ng1960); + assign n5007 = (~Ng1315 | Ng2649) & (~\[1605] | Ng2650); + assign n5008_1 = n5007 & (~\[1603] | Ng2651); + assign n5009 = (~Ng853 | ~Ng1110) & (~\[1612] | ~Ng1104); + assign n5010 = n5009 & (~\[1594] | ~Ng1107); + assign n5011 = (~Ng1315 | Ng1270) & (~\[1605] | Ng1271); + assign n5012 = n5011 & (~\[1603] | Ng1272); + assign n5013_1 = (~Ng853 | ~Ng1795) & (~\[1612] | ~Ng1789); + assign n5014 = n5013_1 & (~\[1594] | ~Ng1792); + assign n5015 = (~Ng1315 | Ng1961) & (~\[1605] | Ng1962); + assign n5016 = n5015 & (~\[1603] | Ng1963); + assign n5017 = (~Ng1315 | Ng2652) & (~\[1605] | Ng2653); + assign n5018_1 = n5017 & (~\[1603] | Ng2654); + assign n5019 = (~Ng853 | Ng171) & (~\[1594] | Ng173); + assign n5020 = n5019 & (~\[1612] | Ng172); + assign n5021 = (~Ng853 | ~Ng1804) & (~\[1612] | ~Ng1798); + assign n5022 = n5021 & (~\[1594] | ~Ng1801); + assign n5023_1 = (~Ng1315 | Ng1964) & (~\[1605] | Ng1965); + assign n5024 = n5023_1 & (~\[1603] | Ng1966); + assign n5025 = (~Ng853 | ~Ng2489) & (~\[1612] | ~Ng2483); + assign n5026 = n5025 & (~\[1594] | ~Ng2486); + assign n5027 = (~Ng1315 | Ng2655) & (~\[1605] | Ng2656); + assign n5028_1 = n5027 & (~\[1603] | Ng2657); + assign n5029 = (~Ng853 | Ng174) & (~\[1612] | Ng175); + assign n5030 = n5029 & (~\[1594] | Ng176); + assign n5031 = (~Ng853 | Ng859) & (~\[1612] | Ng860); + assign n5032 = n5031 & (~\[1594] | Ng861); + assign n5033_1 = (~Ng853 | ~Ng2498) & (~\[1612] | ~Ng2492); + assign n5034 = n5033_1 & (~\[1594] | ~Ng2495); + assign n5035 = (~Ng1315 | Ng2658) & (~\[1605] | Ng2659); + assign n5036 = n5035 & (~\[1603] | Ng2660); + assign n5037 = (~Ng853 | Ng862) & (~\[1612] | Ng863); + assign n5038_1 = n5037 & (~\[1594] | Ng864); + assign n5039 = (~Ng853 | Ng1553) & (~\[1612] | Ng1554); + assign n5040 = n5039 & (~\[1594] | Ng1555); + assign n5041 = (~Ng853 | Ng1556) & (~\[1612] | Ng1557); + assign n5042 = n5041 & (~\[1594] | Ng1558); + assign n5043_1 = (~Ng853 | Ng2247) & (~\[1612] | Ng2248); + assign n5044 = n5043_1 & (~\[1594] | Ng2249); + assign n5045 = (~Ng853 | Ng2250) & (~\[1612] | Ng2251); + assign n5046 = n5045 & (~\[1594] | Ng2252); + assign n5047 = Ng2879 & (~Pg8021 | Ng2929); + assign n358_1 = ~n5047; + assign n5049 = (~Ng853 | Ng426) & (~\[1612] | Ng427); + assign n5050 = n5049 & (~\[1594] | Ng428); + assign n5051 = (~Ng853 | Ng1113) & (~\[1612] | Ng1114); + assign n5052 = n5051 & (~\[1594] | Ng1115); + assign n5053_1 = (~Ng1315 | ~Ng611) & (~\[1605] | ~Ng605); + assign n5054 = n5053_1 & (~\[1603] | ~Ng608); + assign n5055 = (~Ng853 | Ng1807) & (~\[1612] | Ng1808); + assign n5056 = n5055 & (~\[1594] | Ng1809); + assign n5057 = (~Ng1315 | ~Ng1297) & (~\[1605] | ~Ng1291); + assign n5058_1 = n5057 & (~\[1603] | ~Ng1294); + assign n5059 = (~Ng853 | Ng2501) & (~\[1612] | Ng2502); + assign n5060 = n5059 & (~\[1594] | Ng2503); + assign n5061 = (~Ng1315 | ~Ng1991) & (~\[1605] | ~Ng1985); + assign n5062 = n5061 & (~\[1603] | ~Ng1988); + assign n5063_1 = (~Ng1315 | ~Ng2685) & (~\[1605] | ~Ng2679); + assign n5064 = n5063_1 & (~\[1603] | ~Ng2682); + assign n5065 = ~Ng557 & (Ng525 | Ng510); + assign n5066 = ~Ng510 & (Ng525 | Ng557); + assign n5067_1 = ~Ng1243 & (Ng1211 | Ng1196); + assign n5068 = ~Ng1196 & (Ng1211 | Ng1243); + assign n5069 = ~Ng1937 & (Ng1905 | Ng1890); + assign n5070 = ~Ng1890 & (Ng1905 | Ng1937); + assign n5071 = ~Ng2631 & (Ng2599 | Ng2584); + assign n5072_1 = ~Ng2584 & (Ng2599 | Ng2631); + assign n5073 = n1739_1 | ~Ng185 | ~Ng524; + assign n5074 = (~Ng1315 | ~Ng593) & (~\[1605] | ~Ng587); + assign n5075 = n5073 & n5074 & (~\[1603] | ~Ng590); + assign n5076 = n3245_1 | ~Ng185 | ~Ng1210; + assign n5077_1 = (~Ng1315 | ~Ng1279) & (~\[1605] | ~Ng1273); + assign n5078 = n5076 & n5077_1 & (~\[1603] | ~Ng1276); + assign n5079 = n4752 | ~Ng185 | ~Ng1904; + assign n5080_1 = (~Ng1315 | ~Ng1973) & (~\[1605] | ~Ng1967); + assign n5081 = n5079 & n5080_1 & (~\[1603] | ~Ng1970); + assign n5082 = n6259 | ~Ng185 | ~Ng2598; + assign n5083 = (~Ng1315 | ~Ng2667) & (~\[1605] | ~Ng2661); + assign n5084 = n5082 & n5083 & (~\[1603] | ~Ng2664); + assign n274_1 = ~Pg51 & Ng13457; + assign n279_1 = ~Pg51 & Ng2817; + assign n5087 = n6275 & (~Ng659 | n6276_1); + assign n2127_1 = ~n5087; + assign n5089 = n6275 & (~Ng1345 | n6276_1); + assign n3646_1 = ~n5089; + assign n5091 = n6275 & (~Ng2039 | n6276_1); + assign n5140 = ~n5091; + assign n5093 = n6275 & (~Ng2733 | n6276_1); + assign n6647 = ~n5093; + assign n284_1 = Pg51 | Ng2933; + assign n6922 = Ng3079 | Pg3234; + assign n5097 = n6270 & (n6271 | ~Ng554); + assign n1724_1 = ~n5097; + assign n5099 = n6270 & (n6271 | ~Ng1240); + assign n3230_1 = ~n5099; + assign n5101 = n6270 & (n6271 | ~Ng1934); + assign n4737 = ~n5101; + assign n5103 = n6270 & (n6271 | ~Ng2628); + assign n6244 = ~n5103; + assign n5105_1 = n6274 ^ ~Ng640; + assign n5106 = ~\[1603] | ~Ng630; + assign n2132 = n5105_1 & n5106; + assign n5108 = n6273 ^ ~Ng1326; + assign n5109 = ~\[1603] | ~Ng1316; + assign n3651_1 = n5108 & n5109; + assign n5111 = n6272_1 ^ ~Ng2020; + assign n5112 = ~\[1603] | ~Ng2010; + assign n5145 = n5111 & n5112; + assign n5114 = n6269 ^ ~Ng2714; + assign n5115_1 = ~\[1603] | ~Ng2704; + assign n6652 = n5114 & n5115_1; + assign n5117 = n6258 | Pg8021; + assign n5118 = ~Ng2883 ^ ~Ng13457; + assign n289_1 = n5117 | n5118; + assign n6912 = ~Pg3234 & Ng13475; + assign n6917 = ~Pg3234 & Ng3054; + assign n5122 = ~n6266 ^ ~Ng633; + assign n2137 = n5122 & n5106; + assign n5124 = ~n6264 ^ ~Ng1319; + assign n3656_1 = n5124 & n5109; + assign n5126 = ~n4950 | n4954 | n4958_1; + assign n5127 = Ng2896 | Ng2900 | Ng2908 | Ng2892 | Ng2903; + assign n5128 = n5126 & (n5127 | ~n6231_1); + assign n5129 = ~n6262 ^ ~Ng2013; + assign n5150 = n5129 & n5112; + assign n5131 = ~n4956 | n4960 | n4966; + assign n5132 = n5131 & (n5127 | ~n6227_1); + assign n5133 = ~n6260 ^ ~Ng2707; + assign n6657 = n5133 & n5115_1; + assign n5135_1 = ~n4962 | n4968_1 | n4974; + assign n5136 = n5135_1 & (n5127 | ~n6223_1); + assign n5137 = ~n4970 | n4976 | n4980; + assign n5138 = n5137 & (n5127 | ~n6219_1); + assign n5139 = n5117 & (Pg8021 | n6237); + assign n5140_1 = ~n6258 ^ ~Ng2912; + assign n324_1 = n5139 | n5140_1; + assign n5142 = n6192 & (~n8750 | (~n4575 & ~n5054)); + assign n2059_1 = ~n5142; + assign n5144 = n6234 & (Pg3234 | n6233); + assign n5145_1 = ~n6256 ^ ~Ng3018; + assign n7141 = n5144 | n5145_1; + assign n5147 = n6187_1 & (~n8750 | (~n4577_1 & ~n5058_1)); + assign n3565_1 = ~n5147; + assign n5149 = n6182 & (~n8750 | (~n4579 & ~n5062)); + assign n5072 = ~n5149; + assign n5151 = ~Ng2888 ^ ~n6268; + assign n294_1 = ~n5117 & n5151; + assign n5153 = ~\[1605] | ~Ng630; + assign n5154 = \[1605] & n6579_1; + assign n2377 = n5153 & (Ng738 | n5154); + assign n5156 = n6177 & (~n8750 | (~n4581 & ~n5064)); + assign n6579 = ~n5156; + assign n5158 = \[1603] & n6579_1; + assign n2382 = n5106 & (Ng739 | n5158); + assign n5160_1 = ~\[1605] | ~Ng1316; + assign n5161 = \[1605] & n6578; + assign n3896 = n5160_1 & (Ng1424 | n5161); + assign n5163 = n8547 & n8548 & (~\[1605] | Ng729); + assign n5164 = n4820 & n5163 & (~\[1603] | Ng730); + assign n5165_1 = ~Ng1315 | ~Ng630; + assign n5166 = Ng1315 & n6579_1; + assign n2387 = n5165_1 & (Ng737 | n5166); + assign n5168 = \[1603] & n6578; + assign n3901 = n5109 & (Ng1425 | n5168); + assign n5170_1 = ~\[1605] | ~Ng2010; + assign n5171 = \[1605] & n6577; + assign n5390 = n5170_1 & (Ng2118 | n5171); + assign n5173 = n8544 & n8545 & (~\[1605] | Ng1415); + assign n5174 = n4862 & n5173 & (~\[1603] | Ng1416); + assign n5175_1 = ~Ng1315 | ~Ng1316; + assign n5176 = Ng1315 & n6578; + assign n3906 = n5175_1 & (Ng1423 | n5176); + assign n5178 = \[1603] & n6577; + assign n5395 = n5112 & (Ng2119 | n5178); + assign n5180_1 = ~\[1605] | ~Ng2704; + assign n5181 = \[1605] & n6575; + assign n6897 = n5180_1 & (Ng2812 | n5181); + assign n5183 = n8541 & n8542 & (~\[1605] | Ng2109); + assign n5184 = n4900 & n5183 & (~\[1603] | Ng2110); + assign n5185_1 = ~Ng1315 | ~Ng2010; + assign n5186 = Ng1315 & n6577; + assign n5400 = n5185_1 & (Ng2117 | n5186); + assign n5188 = \[1603] & n6575; + assign n6902 = n5115_1 & (Ng2813 | n5188); + assign n5190_1 = n8538 & n8539 & (~\[1605] | Ng2803); + assign n5191 = n4930 & n5190_1 & (~\[1603] | Ng2804); + assign n5192 = ~Ng1315 | ~Ng2704; + assign n5193 = Ng1315 & n6575; + assign n6907 = n5192 & (Ng2811 | n5193); + assign n868_1 = ~n858_1 & (n5978_1 | Ng3123); + assign n5196 = ~Ng653 ^ ~n6267_1; + assign n2142_1 = n5196 & n5106; + assign n5198 = ~Ng1339 ^ ~n6265; + assign n3661_1 = n5198 & n5109; + assign n5200_1 = ~n6572 ^ ~Ng3006; + assign n7116 = n5200_1 & ~n6234; + assign n5202 = ~Ng2033 ^ ~n6263_1; + assign n5155 = n5202 & n5112; + assign n5204 = ~Ng2727 ^ ~n6261; + assign n6662 = n5204 & n5115_1; + assign n5206 = ~Ng2917 ^ ~n6259_1; + assign n329 = ~n5139 & n5206; + assign n5208 = ~n6254_1 ^ ~Ng2896; + assign n299_1 = ~n5117 & n5208; + assign n5210_1 = ~Ng3028 ^ ~n6257; + assign n7146 = ~n5144 & n5210_1; + assign n863_1 = ~n858_1 & (n5978_1 | Ng3125); + assign n5213 = ~n6250 ^ ~Ng646; + assign n2147_1 = n5213 & n5106; + assign n5215_1 = ~n6247 ^ ~Ng1332; + assign n3666_1 = n5215_1 & n5109; + assign n5217 = ~n6244_1 ^ ~Ng2026; + assign n5160 = n5217 & n5112; + assign n5219 = ~n6240 ^ ~Ng2720; + assign n6667 = n5219 & n5115_1; + assign n5221 = n6253 ^ ~Ng3002; + assign n7121 = n5221 & ~n6234; + assign n5223 = ~n6235_1 ^ ~Ng3036; + assign n7151 = ~n5144 & n5223; + assign n5225_1 = ~Ng2892 ^ ~n6255; + assign n304_1 = ~n5117 & n5225_1; + assign n5227 = ~n6238 ^ ~Ng2924; + assign n334_1 = ~n5139 & n5227; + assign n5229 = n6252 ^ ~Ng88; + assign n5230_1 = n6521 | n5127; + assign n1263_1 = n5229 & n5230_1; + assign n5232 = n6249_1 ^ ~Ng776; + assign n2769_1 = n5232 & n5230_1; + assign n5234 = n6246 ^ ~Ng1462; + assign n4276 = n5234 & n5230_1; + assign n5236 = n6243 ^ ~Ng2156; + assign n5770 = n5236 & n5230_1; + assign n853_1 = n6039 & n6038_1 & n6037 & n6035 & n6036 & n6040 & n6041 & n6042; + assign n5239 = ~Ng660 ^ ~n6251; + assign n2152_1 = n5239 & n5106; + assign n5241 = ~Ng1346 ^ ~n6248; + assign n3671_1 = n5241 & n5109; + assign n5243 = Ng3013 ^ ~n6573; + assign n7126 = n5243 & ~n6234; + assign n5245_1 = ~Ng2040 ^ ~n6245; + assign n5165 = n5245_1 & n5112; + assign n5247 = ~Ng2734 ^ ~n6241; + assign n6672 = n5247 & n5115_1; + assign n5249 = ~Ng2920 ^ ~n6239_1; + assign n339 = ~n5139 & n5249; + assign n5251 = ~n6574_1 ^ ~Ng2903; + assign n309_1 = ~n5117 & n5251; + assign n5253 = ~Ng3032 ^ ~n6236; + assign n7156 = ~n5144 & n5253; + assign n5255_1 = ~n6215_1 ^ ~Ng83; + assign n1268 = n5255_1 & n5230_1; + assign n5257 = ~n6211_1 ^ ~Ng771; + assign n2774_1 = n5257 & n5230_1; + assign n5259 = ~n6207_1 ^ ~Ng1457; + assign n4281_1 = n5259 & n5230_1; + assign n5261 = ~n6203_1 ^ ~Ng2151; + assign n5775 = n5261 & n5230_1; + assign n5263 = ~n6213 ^ ~Ng672; + assign n2157_1 = n5263 & n5106; + assign n5265_1 = ~n6209 ^ ~Ng1358; + assign n3676_1 = n5265_1 & n5109; + assign n5267 = ~n6205 ^ ~Ng2052; + assign n5170 = n5267 & n5112; + assign n5269 = ~n6201 ^ ~Ng2746; + assign n6677 = n5269 & n5115_1; + assign n5271 = n6197 ^ ~Ng3010; + assign n7131 = n5271 & ~n6234; + assign n5273 = ~Ng2900 ^ ~n6199_1; + assign n314_1 = ~n5117 & n5273; + assign n5275_1 = ~Ng79 ^ ~n6216; + assign n1273_1 = n5275_1 & n5230_1; + assign n5277 = ~Ng767 ^ ~n6212; + assign n2779_1 = n5277 & n5230_1; + assign n5279 = ~Ng1453 ^ ~n6208; + assign n4286 = n5279 & n5230_1; + assign n5281 = ~Ng2147 ^ ~n6204; + assign n5780 = n5281 & n5230_1; + assign n893_1 = ~n858_1 & n5977 & (Ng185 | n5978_1); + assign n5284 = ~Ng666 ^ ~n6214; + assign n2162_1 = n5284 & n5106; + assign n5286 = ~Ng1352 ^ ~n6210; + assign n3681_1 = n5286 & n5109; + assign n7136 = ~n6234 & ~n6584_1; + assign n5289 = ~Ng2046 ^ ~n6206; + assign n5175 = n5289 & n5112; + assign n5291 = ~Ng2740 ^ ~n6202; + assign n6682 = n5291 & n5115_1; + assign n5293 = ~Ng2908 ^ ~n6200; + assign n319_1 = ~n5117 & n5293; + assign n5295_1 = ~n6175_1 ^ ~Ng74; + assign n1278 = n5295_1 & n5230_1; + assign n5297 = ~n6168 ^ ~Ng762; + assign n2784_1 = n5297 & n5230_1; + assign n5299 = ~n6161 ^ ~Ng1448; + assign n4291_1 = n5299 & n5230_1; + assign n5301 = ~n6154 ^ ~Ng2142; + assign n5785 = n5301 & n5230_1; + assign n5303 = ~n6564 ^ ~Ng679; + assign n2167_1 = n5303 & n5106; + assign n5305_1 = ~n6560_1 ^ ~Ng1365; + assign n3686_1 = n5305_1 & n5109; + assign n5307 = ~n6556 ^ ~Ng2059; + assign n5180 = n5307 & n5112; + assign n5309 = ~n6550_1 ^ ~Ng2753; + assign n6687 = n5309 & n5115_1; + assign n5311 = n5918_1 & n5916 & n5917; + assign n5312 = n4672_1 ^ ~n5947; + assign n5313 = n5311 & n5312; + assign n5314 = n5898_1 & n5896 & n5897; + assign n5315_1 = n4692_1 ^ ~n5940; + assign n5316 = n5314 & n5315_1; + assign n5317 = n5878_1 & n5876 & n5877; + assign n5318 = n4716_1 ^ ~n5933_1; + assign n5319 = n5317 & n5318; + assign n5320_1 = n5858_1 & n5856 & n5857; + assign n5321 = n4746 ^ ~n5926; + assign n5322 = n5320_1 & n5321; + assign n5323 = ~Ng70 ^ ~n6176; + assign n1283_1 = n5323 & n5230_1; + assign n5325_1 = ~Ng758 ^ ~n6169; + assign n2789_1 = n5325_1 & n5230_1; + assign n5327 = ~Ng1444 ^ ~n6162; + assign n4296 = n5327 & n5230_1; + assign n5329 = ~Ng2138 ^ ~n6155_1; + assign n5790 = n5329 & n5230_1; + assign n5331 = ~Ng686 ^ ~n6109; + assign n2172_1 = n5331 & n5106; + assign n5333 = ~Ng1372 ^ ~n6087; + assign n3691_1 = n5333 & n5109; + assign n5335_1 = ~Ng2066 ^ ~n6065; + assign n5185 = n5335_1 & n5112; + assign n5337 = ~Ng2760 ^ ~n6043_1; + assign n6692 = n5337 & n5115_1; + assign n5339 = n6571 | ~n4583 | ~Ng2257; + assign n5340_1 = \[1612] & ~n6174; + assign n1443_1 = (~\[1612] | n5339) & (n5340_1 | Ng448); + assign n5342 = \[1594] & ~n6174; + assign n1448_1 = (~\[1594] | n5339) & (Ng449 | n5342); + assign n5344 = n6570_1 | ~n4591_1 | ~Ng2257; + assign n5345_1 = \[1612] & ~n6167_1; + assign n2949_1 = (~\[1612] | n5344) & (n5345_1 | Ng1135); + assign n5347 = Ng853 & ~n6174; + assign n1453 = (~Ng853 | n5339) & (n5347 | Ng447); + assign n5349 = \[1594] & ~n6167_1; + assign n2954_1 = (~\[1594] | n5344) & (Ng1136 | n5349); + assign n5351 = n6569 | ~n4601 | ~Ng2257; + assign n5352 = \[1612] & ~n6160; + assign n4456_1 = (~\[1612] | n5351) & (n5352 | Ng1829); + assign n5354 = Ng853 & ~n6167_1; + assign n2959_1 = (~Ng853 | n5344) & (n5354 | Ng1134); + assign n5356 = \[1594] & ~n6160; + assign n4461 = (~\[1594] | n5351) & (Ng1830 | n5356); + assign n5358 = n6568 | ~n4613_1 | ~Ng2257; + assign n5359 = \[1612] & ~n6153; + assign n5963 = (~\[1612] | n5358) & (n5359 | Ng2523); + assign n5361 = Ng853 & ~n6160; + assign n4466 = (~Ng853 | n5351) & (n5361 | Ng1828); + assign n5363 = \[1594] & ~n6153; + assign n5968 = (~\[1594] | n5358) & (Ng2524 | n5363); + assign n5365_1 = Ng853 & ~n6153; + assign n5973 = (~Ng853 | n5358) & (n5365_1 | Ng2522); + assign n5367 = ~n6033_1 ^ ~Ng65; + assign n1288 = n5367 & n5230_1; + assign n5369 = ~n6029 ^ ~Ng753; + assign n2794_1 = n5369 & n5230_1; + assign n5371 = ~n6025 ^ ~Ng1439; + assign n4301 = n5371 & n5230_1; + assign n5373 = ~n6021 ^ ~Ng2133; + assign n5795 = n5373 & n5230_1; + assign n5375_1 = ~Ng692 ^ ~n6110; + assign n2177 = n5375_1 & n5106; + assign n5377 = ~Ng1378 ^ ~n6088; + assign n3696_1 = n5377 & n5109; + assign n5379 = ~Ng2072 ^ ~n6066_1; + assign n5190 = n5379 & n5112; + assign n5381 = ~Ng2766 ^ ~n6044; + assign n6697 = n5381 & n5115_1; + assign n5383 = ~Ng61 ^ ~n6034; + assign n1293_1 = n5383 & n5230_1; + assign n5385_1 = ~Ng749 ^ ~n6030; + assign n2799_1 = n5385_1 & n5230_1; + assign n5387 = ~Ng1435 ^ ~n6026; + assign n4306_1 = n5387 & n5230_1; + assign n5389 = ~Ng2129 ^ ~n6022; + assign n5800 = n5389 & n5230_1; + assign n5391 = ~\[1612] | n6530_1; + assign n5392 = n4990 & ~n5663 & Ng2257; + assign n1398_1 = n5391 & (Ng427 | (\[1612] & n5392)); + assign n5394 = ~\[1594] | n6530_1; + assign n1403 = n5394 & (Ng428 | (\[1594] & n5392)); + assign n5396 = ~\[1612] | n6529; + assign n5397 = n5002 & ~n5666 & Ng2257; + assign n2904 = n5396 & (Ng1114 | (\[1612] & n5397)); + assign n5399 = ~Ng853 | n6530_1; + assign n1408_1 = n5399 & (Ng426 | (Ng853 & n5392)); + assign n5401 = ~\[1594] | n6529; + assign n2909_1 = n5401 & (Ng1115 | (\[1594] & n5397)); + assign n5403 = ~\[1612] | n6528; + assign n5404 = n5014 & ~n5669 & Ng2257; + assign n4411 = n5403 & (Ng1808 | (\[1612] & n5404)); + assign n5406 = ~Ng853 | n6529; + assign n2914_1 = n5406 & (Ng1113 | (Ng853 & n5397)); + assign n5408 = ~\[1594] | n6528; + assign n4416 = n5408 & (Ng1809 | (\[1594] & n5404)); + assign n5410_1 = ~\[1612] | n6527; + assign n5411 = n5026 & ~n5672 & Ng2257; + assign n5918 = n5410_1 & (Ng2502 | (\[1612] & n5411)); + assign n5413 = ~Ng853 | n6528; + assign n4421 = n5413 & (Ng1807 | (Ng853 & n5404)); + assign n5415_1 = ~\[1594] | n6527; + assign n5923 = n5415_1 & (Ng2503 | (\[1594] & n5411)); + assign n5417 = ~Ng853 | n6527; + assign n5928 = n5417 & (Ng2501 | (Ng853 & n5411)); + assign n5419 = ~n5971 ^ ~Ng56; + assign n1298 = n5419 & n5230_1; + assign n5421 = ~n5968_1 ^ ~Ng744; + assign n2804_1 = n5421 & n5230_1; + assign n5423 = ~n5965 ^ ~Ng1430; + assign n4311_1 = n5423 & n5230_1; + assign n5425_1 = ~n5962 ^ ~Ng2124; + assign n5805 = n5425_1 & n5230_1; + assign n5427 = ~Ng52 ^ ~n5972; + assign n1303 = n5427 & n5230_1; + assign n5429 = ~Ng740 ^ ~n5969; + assign n2809_1 = n5429 & n5230_1; + assign n5431 = ~Ng1426 ^ ~n5966; + assign n4316 = n5431 & n5230_1; + assign n5433 = ~Ng2120 ^ ~n5963_1; + assign n5810 = n5433 & n5230_1; + assign n5435_1 = n5542 | n5920; + assign n5436 = n4585 | n6013_1; + assign n5437 = n5435_1 & n5436 & (~n4958_1 | ~n5542); + assign n5438 = n5544 | n5900; + assign n5439 = n4593 | n6005; + assign n5440_1 = n5438 & n5439 & (~n4966 | ~n5544); + assign n5441 = n5546 | n5880; + assign n5442 = n4603 | n5997; + assign n5443 = n5441 & n5442 & (~n4974 | ~n5546); + assign n5444 = n5548 | n5860; + assign n5445_1 = n4615 | n5989; + assign n5446 = n5444 & n5445_1 & (~n4980 | ~n5548); + assign n5447 = n4672_1 ^ ~n5311; + assign n5448 = ~n5030 & ~n5923_1; + assign n5449 = (n5448 | ~n5828_1) & (n5447 | ~n5925); + assign n5450_1 = ~n4684_1 ^ ~n6379; + assign n5451 = Ng101 & ~n5923_1; + assign n5452 = (n5451 | ~n5828_1) & (n5450_1 | ~n5925); + assign n5453 = n4692_1 ^ ~n5314; + assign n5454 = ~n5038_1 & ~n5903_1; + assign n5455_1 = (n5454 | ~n5829) & (n5453 | ~n5905); + assign n5456 = ~n4702 ^ ~n6378_1; + assign n5457 = Ng109 & ~n5923_1; + assign n5458 = (n5457 | ~n5828_1) & (n5456 | ~n5925); + assign n5459 = ~n4708_1 ^ ~n6355; + assign n5460_1 = Ng789 & ~n5903_1; + assign n5461 = (n5460_1 | ~n5829) & (n5459 | ~n5905); + assign n5462 = n4716_1 ^ ~n5317; + assign n5463 = ~n5042 & ~n5883_1; + assign n5464 = (n5463 | ~n5830) & (n5462 | ~n5885); + assign n5465_1 = ~n4732_1 ^ ~n6354; + assign n5466 = Ng797 & ~n5903_1; + assign n5467 = (n5466 | ~n5829) & (n5465_1 | ~n5905); + assign n5468 = ~n4738 ^ ~n6331_1; + assign n5469 = Ng1476 & ~n5883_1; + assign n5470_1 = (n5469 | ~n5830) & (n5468 | ~n5885); + assign n5471 = n4746 ^ ~n5320_1; + assign n5472 = ~n5046 & ~n5863_1; + assign n5473 = (n5472 | ~n5831) & (n5471 | ~n5865); + assign n5474 = ~n4768 ^ ~n6330; + assign n5475_1 = Ng1486 & ~n5883_1; + assign n5476 = (n5475_1 | ~n5830) & (n5474 | ~n5885); + assign n5477 = ~n4774_1 ^ ~n6307; + assign n5478 = Ng2170 & ~n5863_1; + assign n5479 = (n5478 | ~n5831) & (n5477 | ~n5865); + assign n5480_1 = n4782 ^ ~n5313; + assign n5481 = ~n5020 & ~n5923_1; + assign n5482 = (n5481 | ~n5828_1) & (n5480_1 | ~n5925); + assign n5483 = ~n4810_1 ^ ~n6306; + assign n5484 = Ng2180 & ~n5863_1; + assign n5485_1 = (n5484 | ~n5831) & (n5483 | ~n5865); + assign n5486 = ~n4814_1 ^ ~n6380; + assign n5487 = Ng105 & ~n5923_1; + assign n5488 = (n5487 | ~n5828_1) & (n5486 | ~n5925); + assign n5489 = n4824_1 ^ ~n5316; + assign n5490_1 = ~n5032 & ~n5903_1; + assign n5491 = (n5490_1 | ~n5829) & (n5489 | ~n5905); + assign n5492 = ~n4856_1 ^ ~n6356; + assign n5493 = Ng793 & ~n5903_1; + assign n5494 = (n5493 | ~n5829) & (n5492 | ~n5905); + assign n5495_1 = n4866_1 ^ ~n5319; + assign n5496 = ~n5040 & ~n5883_1; + assign n5497 = (n5496 | ~n5830) & (n5495_1 | ~n5885); + assign n5498 = ~n4894 ^ ~n6332; + assign n5499 = Ng1481 & ~n5883_1; + assign n5500_1 = (n5499 | ~n5830) & (n5498 | ~n5885); + assign n5501 = n4904 ^ ~n5322; + assign n5502 = ~n5044 & ~n5863_1; + assign n5503 = (n5502 | ~n5831) & (n5501 | ~n5865); + assign n5504 = ~n4924_1 ^ ~n6308_1; + assign n5505_1 = Ng2175 & ~n5863_1; + assign n5506 = (n5505_1 | ~n5831) & (n5504 | ~n5865); + assign n5507 = ~n4854 | n4964; + assign n5508 = ~n4964 & ~n5981; + assign n5509 = n5507 & ~n5826 & (n4854 | n5508); + assign n5510_1 = n5981 & n5054; + assign n5511 = ~n5826 & (n5510_1 | ~n6981_1); + assign n5512 = n5981 & n4964; + assign n5513 = ~n5826 & (n5512 | ~n6982); + assign n5514 = ~n4818 | n5054; + assign n5515_1 = n5514 & ~n5826 & (n4818 | ~n8450); + assign n5516 = ~n5826 & (n5510_1 | ~n6980); + assign n5517 = ~n4686 | n4964; + assign n5518 = n5517 & ~n5826 & (n4686 | n5508); + assign n5519 = ~n4788 | n4964; + assign n5520_1 = n5519 & ~n5826 & (n4788 | n5508); + assign n5521 = ~n4886 | n5054; + assign n5522 = n5521 & ~n5826 & (n4886 | ~n8450); + assign n5523 = Pg563 | n5979 | Ng559 | ~n6600; + assign n5524 = ~n6016 & (n5523 | (Ng8284 & ~n5825)); + assign n5525_1 = ~n4916 | n5058_1; + assign n5526 = n5525_1 & ~n5823_1 & (n4916 | ~n8451); + assign n5527 = ~n4892_1 | n4972; + assign n5528 = ~n4972 & ~n5955; + assign n5529 = n5527 & ~n5823_1 & (n4892_1 | n5528); + assign n5530_1 = n5955 & n5058_1; + assign n5531 = ~n5823_1 & (n5530_1 | ~n6951_1); + assign n5532 = n5955 & n4972; + assign n5533 = ~n5823_1 & (n5532 | ~n6952); + assign n5534 = ~n4860 | n5058_1; + assign n5535_1 = n5534 & ~n5823_1 & (n4860 | ~n8451); + assign n5536 = ~n5823_1 & (n5530_1 | ~n6950); + assign n5537 = ~n4710 | n4972; + assign n5538 = n5537 & ~n5823_1 & (n4710 | n5528); + assign n5539 = ~n4830 | n4972; + assign n5540_1 = n5539 & ~n5823_1 & (n4830 | n5528); + assign n5541 = (~n5911 & (n4958_1 | n6514)) | (~n4958_1 & n6514); + assign n5542 = ~n4950 & ~n8584 & (n4954 | n5541); + assign n5543 = (~n5891 & (n4966 | n6504)) | (~n4966 & n6504); + assign n5544 = ~n4956 & ~n8583 & (n4960 | n5543); + assign n5545_1 = (~n5871 & (n4974 | n6494)) | (~n4974 & n6494); + assign n5546 = ~n4962 & ~n8582 & (n4968_1 | n5545_1); + assign n5547 = (~n5851 & (n4980 | n6484)) | (~n4980 & n6484); + assign n5548 = ~n4970 & ~n8581 & (n4976 | n5547); + assign n5549 = ~n6601 | Pg1249 | Ng1245; + assign n5550_1 = ~n5958_1 & (n5549 | (Ng8293 & ~n5822)); + assign n5551 = ~n5914 & (~n4958_1 | n5908_1 | ~n6514); + assign n5552 = ~n4950 & ~n8577 & (n4954 | n5551); + assign n5553 = ~n5894 & (~n4966 | n5888_1 | ~n6504); + assign n5554 = ~n4956 & ~n8572 & (n4960 | n5553); + assign n5555_1 = ~n5874 & (~n4974 | n5868_1 | ~n6494); + assign n5556 = ~n4962 & ~n8567 & (n4968_1 | n5555_1); + assign n5557 = ~n5854 & (~n4980 | n5848_1 | ~n6484); + assign n5558 = ~n4970 & ~n8562 & (n4976 | n5557); + assign n5559 = (~n4872 & n8452) | (n4978_1 & (n4872 | n8452)); + assign n5560_1 = n5559 & ~n5820; + assign n5561 = (~n4936 & ~n8453) | (n5062 & (n4936 | ~n8453)); + assign n5562 = n5561 & ~n5820; + assign n5563 = (~n4922 & n8452) | (n4978_1 & (n4922 | n8452)); + assign n5564 = n5563 & ~n5820; + assign n5565_1 = n5062 & ~n5840; + assign n5566 = ~n5820 & (n5565_1 | ~n6617_1); + assign n5567 = n4978_1 & ~n5840; + assign n5568 = ~n5820 & (n5567 | ~n6618); + assign n5569 = (~n4898 & ~n8453) | (n5062 & (n4898 | ~n8453)); + assign n5570_1 = n5569 & ~n5820; + assign n5571 = ~n5820 & (n5565_1 | ~n6616); + assign n5572 = (~n4740 & n8452) | (n4978_1 & (n4740 | n8452)); + assign n5573 = n5572 & ~n5820; + assign n5574 = ~n6602_1 | Pg1943 | Ng1939; + assign n5575_1 = ~n5843_1 & (n5574 | (Ng8302 & ~n5819_1)); + assign n5576 = n5591 | ~Ng8311; + assign n5577 = n5576 | ~n8554; + assign n5578 = (~n4910_1 & n8454) | (n4982 & (n4910_1 | n8454)); + assign n5579 = ~n5576 & n5578; + assign n5580_1 = (~n4948_1 & ~n8455) | (n5064 & (n4948_1 | ~n8455)); + assign n5581 = ~n5576 & n5580_1; + assign n5582 = (~n4942 & n8454) | (n4982 & (n4942 | n8454)); + assign n5583 = ~n5576 & n5582; + assign n5584 = n5064 & ~n5833_1; + assign n5585_1 = ~n5576 & (n5584 | ~n6606); + assign n5586 = n4982 & ~n5833_1; + assign n5587 = ~n5576 & (n5586 | ~n6607_1); + assign n5588 = (~n4928_1 & ~n8455) | (n5064 & (n4928_1 | ~n8455)); + assign n5589 = ~n5576 & n5588; + assign n5590_1 = ~n5576 & (n5584 | ~n6605); + assign n5591 = ~n6603 | Pg2637 | Ng2633; + assign n5592 = ~n5836 & (n5591 | (Ng8311 & ~n5817)); + assign n5593 = Ng2874 ^ ~Ng2981; + assign n5594 = Ng2978 ^ ~Ng2975; + assign n5595_1 = ~Ng2874 ^ ~Ng2981; + assign n5596 = ~Ng2978 ^ ~Ng2975; + assign n5597 = (n5593 | n5594) & (n5595_1 | n5596); + assign n5598 = Ng2972 ^ ~Ng2969; + assign n5599 = Ng2966 ^ ~Ng2963; + assign n5600_1 = ~Ng2972 ^ ~Ng2969; + assign n5601 = ~Ng2966 ^ ~Ng2963; + assign n5602 = (n5598 | n5599) & (n5600_1 | n5601); + assign n5603 = Ng2959 ^ ~Ng2956; + assign n5604 = Ng2953 ^ ~Ng2947; + assign n5605_1 = ~Ng2959 ^ ~Ng2956; + assign n5606 = ~Ng2953 ^ ~Ng2947; + assign n5607 = (n5603 | n5604) & (n5605_1 | n5606); + assign n5608 = Ng2944 ^ ~Ng2941; + assign n5609 = Ng2938 ^ ~Ng2935; + assign n5610_1 = ~Ng2944 ^ ~Ng2941; + assign n5611 = ~Ng2938 ^ ~Ng2935; + assign n5612 = (n5608 | n5609) & (n5610_1 | n5611); + assign n5613 = ~n5826 & (n5512 | ~n6978); + assign n5614 = ~n5826 & (n5510_1 | ~n6979); + assign n5615_1 = n5509 ^ ~n5522; + assign n5616 = n5515_1 ^ ~n5520_1; + assign n5617 = ~n5509 ^ ~n5522; + assign n5618 = ~n5515_1 ^ ~n5520_1; + assign n5619 = (n5615_1 | n5616) & (n5617 | n5618); + assign n5620_1 = n5516 ^ ~n5518; + assign n5621 = n5511 ^ ~n5513; + assign n5622 = ~n5516 ^ ~n5518; + assign n5623 = ~n5511 ^ ~n5513; + assign n5624 = (n5620_1 | n5621) & (n5622 | n5623); + assign n5625_1 = ~n5823_1 & (n5532 | ~n6948); + assign n5626 = ~n5823_1 & (n5530_1 | ~n6949); + assign n5627 = n5535_1 ^ ~n5540_1; + assign n5628 = n5526 ^ ~n5529; + assign n5629 = ~n5535_1 ^ ~n5540_1; + assign n5630_1 = ~n5526 ^ ~n5529; + assign n5631 = (n5627 | n5628) & (n5629 | n5630_1); + assign n5632 = n5536 ^ ~n5538; + assign n5633 = n5531 ^ ~n5533; + assign n5634 = ~n5536 ^ ~n5538; + assign n5635_1 = ~n5531 ^ ~n5533; + assign n5636 = (n5632 | n5633) & (n5634 | n5635_1); + assign n5637 = ~n5820 & (n5567 | ~n6614); + assign n5638 = ~n5820 & (n5565_1 | ~n6615); + assign n5639 = n5560_1 ^ ~n5570_1; + assign n5640_1 = n5562 ^ ~n5564; + assign n5641 = ~n5560_1 ^ ~n5570_1; + assign n5642 = ~n5562 ^ ~n5564; + assign n5643 = (n5639 | n5640_1) & (n5641 | n5642); + assign n5644 = n5571 ^ ~n5573; + assign n5645_1 = n5566 ^ ~n5568; + assign n5646 = ~n5571 ^ ~n5573; + assign n5647 = ~n5566 ^ ~n5568; + assign n5648 = (n5644 | n5645_1) & (n5646 | n5647); + assign n5649 = ~n5576 & (n5586 | ~n6599); + assign n5650_1 = ~n5576 & (n5584 | ~n6604); + assign n5651 = n5579 ^ ~n5589; + assign n5652 = n5581 ^ ~n5583; + assign n5653 = ~n5579 ^ ~n5589; + assign n5654 = ~n5581 ^ ~n5583; + assign n5655_1 = (n5651 | n5652) & (n5653 | n5654); + assign n5656 = ~n5590_1 ^ ~n5577; + assign n5657 = n5585_1 ^ ~n5587; + assign n5658 = n5577 ^ ~n5590_1; + assign n5659 = ~n5585_1 ^ ~n5587; + assign n5660_1 = (n5656 | n5657) & (n5658 | n5659); + assign n5661 = n6515_1 | ~n4998_1 | ~n5662; + assign n5662 = n6170 & ~n5020 & ~n5030; + assign n5663 = n5661 & (n5662 | n4998_1); + assign n5664 = n6505_1 | ~n5010 | ~n5665_1; + assign n5665_1 = n6163_1 & ~n5032 & ~n5038_1; + assign n5666 = n5664 & (n5665_1 | n5010); + assign n5667 = n6495_1 | ~n5022 | ~n5668; + assign n5668 = n6156 & ~n5040 & ~n5042; + assign n5669 = n5667 & (n5668 | n5022); + assign n5670_1 = n6485_1 | ~n5034 | ~n5671; + assign n5671 = n6149 & ~n5044 & ~n5046; + assign n5672 = n5670_1 & (n5671 | n5034); + assign n6133 = ~n5034; + assign n4626 = ~n5022; + assign n3119_1 = ~n5010; + assign n1613 = ~n4998_1; + assign n5677 = n5834 & (~Ng2584 | n5835); + assign n7101 = ~n5677; + assign n5679 = (~n5071 | ~n8458) & (n5649 | n5836); + assign n7096 = ~n5679; + assign n5681 = (~n5071 | ~n8459) & (n5650_1 | n5836); + assign n7091 = ~n5681; + assign n5683 = n5837 & (~n5071 | ~n8460); + assign n7086 = ~n5683; + assign n5685_1 = n5837 & (~n5071 | ~n8461); + assign n7081 = ~n5685_1; + assign n5687 = ~n5818 & (~n5071 | ~n8462); + assign n7076 = ~n5687; + assign n5689 = ~n5592 & (~n5071 | ~n8463); + assign n7071 = ~n5689; + assign n5691 = ~n5592 & (~n5071 | ~n8464); + assign n7066 = ~n5691; + assign n5693 = ~n5818 & (~n5071 | ~n8465); + assign n7061 = ~n5693; + assign n5695_1 = n5841 & (~Ng1890 | n5842); + assign n7056 = ~n5695_1; + assign n5697 = (~n5069 | ~n8468) & (n5637 | n5843_1); + assign n7051 = ~n5697; + assign n5699 = (~n5069 | ~n8469) & (n5638 | n5843_1); + assign n7046 = ~n5699; + assign n5701 = n5844 & (~n5069 | ~n8470); + assign n7041 = ~n5701; + assign n5703 = n5844 & (~n5069 | ~n8471); + assign n7036 = ~n5703; + assign n5705_1 = ~n5821 & (~n5069 | ~n8472); + assign n7031 = ~n5705_1; + assign n5707 = ~n5575_1 & (~n5069 | ~n8473); + assign n7026 = ~n5707; + assign n5709 = ~n5575_1 & (~n5069 | ~n8474); + assign n7021 = ~n5709; + assign n5711 = ~n5821 & (~n5069 | ~n8475); + assign n7016 = ~n5711; + assign n5713 = n5956 & (~Ng1196 | n5957); + assign n7011 = ~n5713; + assign n5715_1 = (~n5067_1 | ~n8502) & (n5625_1 | n5958_1); + assign n7006 = ~n5715_1; + assign n5717 = (~n5067_1 | ~n8503) & (n5626 | n5958_1); + assign n7001 = ~n5717; + assign n5719 = n5959 & (~n5067_1 | ~n8504); + assign n6996 = ~n5719; + assign n5721 = n5959 & (~n5067_1 | ~n8505); + assign n6991 = ~n5721; + assign n5723 = ~n5824 & (~n5067_1 | ~n8506); + assign n6986 = ~n5723; + assign n5725_1 = ~n5550_1 & (~n5067_1 | ~n8507); + assign n6981 = ~n5725_1; + assign n5727 = ~n5550_1 & (~n5067_1 | ~n8508); + assign n6976 = ~n5727; + assign n5729 = ~n5824 & (~n5067_1 | ~n8509); + assign n6971 = ~n5729; + assign n5731 = n5982 & (~Ng510 | n5983_1); + assign n6966 = ~n5731; + assign n5733 = (~n5065 | ~n8512) & (n5613 | n6016); + assign n6961 = ~n5733; + assign n5735_1 = (~n5065 | ~n8513) & (n5614 | n6016); + assign n6956 = ~n5735_1; + assign n5737 = n6017 & (~n5065 | ~n8514); + assign n6951 = ~n5737; + assign n5739 = n6017 & (~n5065 | ~n8515); + assign n6946 = ~n5739; + assign n5741 = ~n5827 & (~n5065 | ~n8516); + assign n6941 = ~n5741; + assign n5743 = ~n5524 & (~n5065 | ~n8517); + assign n6936 = ~n5743; + assign n5745_1 = ~n5524 & (~n5065 | ~n8518); + assign n6931 = ~n5745_1; + assign n5747 = ~n5827 & (~n5065 | ~n8519); + assign n6926 = ~n5747; + assign n6637 = ~Ng2366; + assign n6627 = ~Ng2364; + assign n6622 = ~Ng2362; + assign n6617 = ~Ng2360; + assign n6612 = ~Ng2358; + assign n6607 = ~Ng2356; + assign n6602 = ~Ng2354; + assign n6597 = ~Ng2528; + assign n6592 = ~Ng2526; + assign n6116 = ~Ng2165; + assign n6107 = ~Ng2170; + assign n6098 = ~Ng2175; + assign n6089 = ~Ng2180; + assign n6080 = ~Ng2185; + assign n6071 = ~Ng2190; + assign n6062 = ~Ng2195; + assign n6053 = ~Ng2200; + assign n5130 = ~Ng1672; + assign n5120 = ~Ng1670; + assign n5115 = ~Ng1668; + assign n5110 = ~Ng1666; + assign n5105 = ~Ng1664; + assign n5100 = ~Ng1662; + assign n5095 = ~Ng1660; + assign n5090 = ~Ng1834; + assign n5085 = ~Ng1832; + assign n4609 = ~Ng1471; + assign n4600 = ~Ng1476; + assign n4591 = ~Ng1481; + assign n4582 = ~Ng1486; + assign n4573 = ~Ng1491; + assign n4564 = ~Ng1496; + assign n4555 = ~Ng1501; + assign n4546 = ~Ng1506; + assign n3623_1 = ~Ng978; + assign n3613_1 = ~Ng976; + assign n3608_1 = ~Ng974; + assign n3603_1 = ~Ng972; + assign n3598_1 = ~Ng970; + assign n3593_1 = ~Ng968; + assign n3588_1 = ~Ng966; + assign n3583_1 = ~Ng1140; + assign n3578_1 = ~Ng1138; + assign n3102 = ~Ng785; + assign n3093_1 = ~Ng789; + assign n3084_1 = ~Ng793; + assign n3075 = ~Ng797; + assign n3066_1 = ~Ng801; + assign n3057_1 = ~Ng805; + assign n3048_1 = ~Ng809; + assign n3039_1 = ~Ng813; + assign n2117_1 = ~Ng291; + assign n2107_1 = ~Ng289; + assign n2102_1 = ~Ng287; + assign n2097_1 = ~Ng285; + assign n2092_1 = ~Ng283; + assign n2087_1 = ~Ng281; + assign n2082 = ~Ng279; + assign n2077_1 = ~Ng453; + assign n2072_1 = ~Ng451; + assign n1596 = ~Ng97; + assign n1587 = ~Ng101; + assign n1578 = ~Ng105; + assign n1569_1 = ~Ng109; + assign n1560_1 = ~Ng113; + assign n1551_1 = ~Ng117; + assign n1542_1 = ~Ng121; + assign n1533_1 = ~Ng125; + assign n5817 = n5833_1 & n5838_1 & (~\[1605] | Ng2809); + assign n5818 = ~n5836 & (n5576 | n5817); + assign n5819_1 = n5840 & n5845 & (~\[1605] | Ng2115); + assign n5820 = n5574 | ~Ng8302; + assign n5821 = ~n5843_1 & (n5819_1 | n5820); + assign n5822 = ~n5955 & n5960 & (~\[1605] | Ng1421); + assign n5823_1 = n5549 | ~Ng8293; + assign n5824 = ~n5958_1 & (n5822 | n5823_1); + assign n5825 = ~n5981 & n6018_1 & (~\[1605] | Ng735); + assign n5826 = n5523 | ~Ng8284; + assign n5827 = ~n6016 & (n5825 | n5826); + assign n5828_1 = ~n5925 & (~n5923_1 | ~n5947); + assign n5829 = ~n5905 & (~n5903_1 | ~n5940); + assign n5830 = ~n5885 & (~n5883_1 | ~n5933_1); + assign n5831 = ~n5865 & (~n5863_1 | ~n5926); + assign n5832 = n4952 | n4930 | n4882 | n4812 | n4778_1 | n4848; + assign n5833_1 = ~n4928_1 | ~n4776 | ~n4910_1 | ~n8457 | ~n4942 | n5832; + assign n5834 = (~Ng2631 | n8556) & n8557; + assign n5835 = n5655_1 ^ ~n5660_1; + assign n5836 = n5071 | ~n5072_1; + assign n5837 = ~n5591 | n5836; + assign n5838_1 = (~Ng1315 | Ng2808) & (~\[1603] | Ng2810); + assign n5839 = n4944 | n4900 | n4840 | n4770 | n4742_1 | n4806; + assign n5840 = ~n4898 | ~n4740 | ~n4872 | ~n8467 | ~n4922 | n5839; + assign n5841 = (~Ng1937 | n8559) & n8560; + assign n5842 = n5643 ^ ~n5648; + assign n5843_1 = n5069 | ~n5070; + assign n5844 = ~n5574 | n5843_1; + assign n5845 = (~Ng1315 | Ng2114) & (~\[1603] | Ng2116); + assign n5846 = (n6297 | ~n6298) & (n6299_1 | n6300); + assign n5847 = n4846_1 ^ ~Ng2190; + assign n5848_1 = ~n5849 & (~n8481 | (n5846 & n5847)); + assign n5849 = n4946 | ~Ng2257; + assign n5850 = n6300 | n6482 | ~n6298 | n6299_1 | n5847 | n5853_1 | n6296 | n6297; + assign n5851 = ~n6485_1 & (n5849 | n5850); + assign n5852 = (n6293 | n6294_1) & (n6295 | n6296); + assign n5853_1 = ~n4746 ^ ~n5046; + assign n5854 = ~n5849 & (~n8478 | (n5852 & n5853_1)); + assign n5855 = n6301 & ~n6308_1 & ~n6488; + assign n5856 = n5855 & (n4846_1 | ~n5926); + assign n5857 = n4720_1 ^ ~n5926; + assign n5858_1 = (n4876_1 & n5926) | (~n4846_1 & (~n4876_1 | n5926)); + assign n5859 = ~n5989 & ~n6483; + assign n5860 = ~n4970 & n4980; + assign n5861 = n5860 & n4976 & n5859; + assign n5862 = ~n4643 & (n5861 | (~n5989 & ~n5990)); + assign n5863_1 = n5445_1 & ~n5862 & (n4970 | ~n6485_1); + assign n5864 = n6219_1 & n5926; + assign n5865 = n5863_1 & (n5864 | ~n6626); + assign n5866 = (n6321_1 | ~n6322) & (n6323 | n6324); + assign n5867 = n4804 ^ ~Ng1496; + assign n5868_1 = ~n5869 & (~n8487 | (n5866 & n5867)); + assign n5869 = n4934 | ~Ng2257; + assign n5870 = n6324 | n6492 | ~n6322 | n6323 | n5867 | n5873_1 | n6320 | n6321_1; + assign n5871 = ~n6495_1 & (n5869 | n5870); + assign n5872 = (n6317_1 | n6318) & (n6319 | n6320); + assign n5873_1 = ~n4716_1 ^ ~n5042; + assign n5874 = ~n5869 & (~n8484 | (n5872 & n5873_1)); + assign n5875 = n6325 & ~n6332 & ~n6498; + assign n5876 = n5875 & (n4804 | ~n5933_1); + assign n5877 = n4696_1 ^ ~n5933_1; + assign n5878_1 = (n4834_1 & n5933_1) | (~n4804 & (~n4834_1 | n5933_1)); + assign n5879 = ~n5997 & ~n6493; + assign n5880 = ~n4962 & n4974; + assign n5881 = n5880 & n4968_1 & n5879; + assign n5882 = ~n4639 & (n5881 | (~n5997 & ~n5998_1)); + assign n5883_1 = n5442 & ~n5882 & (n4962 | ~n6495_1); + assign n5884 = n6223_1 & n5933_1; + assign n5885 = n5883_1 & (n5884 | ~n6664); + assign n5886 = (n6345_1 | ~n6346) & (n6347 | n6348); + assign n5887 = n4762 ^ ~Ng805; + assign n5888_1 = ~n5889 & (~n8493 | (n5886 & n5887)); + assign n5889 = n4914 | ~Ng2257; + assign n5890 = n6348 | n6502 | ~n6346 | n6347 | n5887 | n5893_1 | n6344 | n6345_1; + assign n5891 = ~n6505_1 & (n5889 | n5890); + assign n5892 = (n6341_1 | n6342) & (n6343 | n6344); + assign n5893_1 = ~n4692_1 ^ ~n5038_1; + assign n5894 = ~n5889 & (~n8490 | (n5892 & n5893_1)); + assign n5895 = n6349_1 & ~n6356 & ~n6508; + assign n5896 = n5895 & (n4762 | ~n5940); + assign n5897 = n4676_1 ^ ~n5940; + assign n5898_1 = (n4792_1 & n5940) | (~n4762 & (~n4792_1 | n5940)); + assign n5899 = ~n6005 & ~n6503; + assign n5900 = ~n4956 & n4966; + assign n5901 = n5900 & n4960 & n5899; + assign n5902 = ~n4633 & (n5901 | (~n6005 & ~n6006)); + assign n5903_1 = n5439 & ~n5902 & (n4956 | ~n6505_1); + assign n5904 = n6227_1 & n5940; + assign n5905 = n5903_1 & (n5904 | ~n6702_1); + assign n5906 = (n6369 | ~n6370) & (n6371 | n6372); + assign n5907 = n4726 ^ ~Ng117; + assign n5908_1 = ~n5909 & (~n8499 | (n5906 & n5907)); + assign n5909 = n4884_1 | ~Ng2257; + assign n5910 = n6372 | n6512 | ~n6370 | n6371 | n5907 | n5913_1 | n6368_1 | n6369; + assign n5911 = ~n6515_1 & (n5909 | n5910); + assign n5912 = (n6365 | n6366) & (n6367 | n6368_1); + assign n5913_1 = ~n4672_1 ^ ~n5030; + assign n5914 = ~n5909 & (~n8496 | (n5912 & n5913_1)); + assign n5915 = n6373_1 & ~n6380 & ~n6518; + assign n5916 = n5915 & (n4726 | ~n5947); + assign n5917 = n4662 ^ ~n5947; + assign n5918_1 = (n4750 & n5947) | (~n4726 & (~n4750 | n5947)); + assign n5919 = ~n6013_1 & ~n6513; + assign n5920 = ~n4950 & n4958_1; + assign n5921 = n5920 & n4954 & n5919; + assign n5922 = ~n4625 & (n5921 | (~n6013_1 & ~n6014)); + assign n5923_1 = n5436 & ~n5922 & (n4950 | ~n6515_1); + assign n5924 = n6231_1 & n5947; + assign n5925 = n5923_1 & (n5924 | ~n6740); + assign n5926 = ~n4970 | n4976 | ~n4980; + assign n5927 = n5856 & (~n4846_1 | n5926); + assign n5928_1 = n5927 & n5857; + assign n5929 = Ng2200 & ~n5863_1; + assign n5930 = Ng2195 & ~n5863_1; + assign n5931 = Ng2185 & ~n5863_1; + assign n5932 = Ng2165 & ~n5863_1; + assign n5933_1 = ~n4962 | n4968_1 | ~n4974; + assign n5934 = n5876 & (~n4804 | n5933_1); + assign n5935 = n5934 & n5877; + assign n5936 = Ng1506 & ~n5883_1; + assign n5937 = Ng1501 & ~n5883_1; + assign n5938_1 = Ng1491 & ~n5883_1; + assign n5939 = Ng1471 & ~n5883_1; + assign n5940 = ~n4956 | n4960 | ~n4966; + assign n5941 = n5896 & (~n4762 | n5940); + assign n5942 = n5941 & n5897; + assign n5943_1 = Ng813 & ~n5903_1; + assign n5944 = Ng809 & ~n5903_1; + assign n5945 = Ng801 & ~n5903_1; + assign n5946 = Ng785 & ~n5903_1; + assign n5947 = ~n4950 | n4954 | ~n4958_1; + assign n5948_1 = n5916 & (~n4726 | n5947); + assign n5949 = n5948_1 & n5917; + assign n5950 = Ng125 & ~n5923_1; + assign n5951 = Ng121 & ~n5923_1; + assign n5952 = Ng113 & ~n5923_1; + assign n5953_1 = Ng97 & ~n5923_1; + assign n5954 = n4916 & (~n8500 | (\[1603] & ~Ng1425)); + assign n5955 = n5954 & n4892_1 & n4860 & n4710 & n4830 & ~n8501; + assign n5956 = (~Ng1243 | n8612) & n8613; + assign n5957 = n5631 ^ ~n5636; + assign n5958_1 = n5067_1 | ~n5068; + assign n5959 = ~n5549 | n5958_1; + assign n5960 = (~Ng1315 | Ng1420) & (~\[1603] | Ng1422); + assign n5961 = n5926 & (n4970 | ~n5990 | ~n6483); + assign n5962 = n6021 & Ng2133 & Ng2129; + assign n5963_1 = n5962 & Ng2124; + assign n5964 = n5933_1 & (n4962 | ~n5998_1 | ~n6493); + assign n5965 = n6025 & Ng1439 & Ng1435; + assign n5966 = n5965 & Ng1430; + assign n5967 = n5940 & (n4956 | ~n6006 | ~n6503); + assign n5968_1 = n6029 & Ng753 & Ng749; + assign n5969 = n5968_1 & Ng744; + assign n5970 = n5947 & (n4950 | ~n6014 | ~n6513); + assign n5971 = n6033_1 & Ng65 & Ng61; + assign n5972 = n5971 & Ng56; + assign n5973_1 = n6522 | n5975; + assign n5974 = ~Ng3135 | n6524; + assign n5975 = ~Ng3147 | n6131; + assign n5976 = n5973_1 & (n5974 | n5975); + assign n5977 = n6531 & (Ng3120 | ~Ng3135 | ~n6977); + assign n5978_1 = n5974 | Ng3147 | n6131; + assign n5979 = \[1605] & ~Ng8284; + assign n5980 = n4886 & (~n8510 | (\[1603] & ~Ng739)); + assign n5981 = n5980 & n4854 & n4818 & n4686 & n4788 & ~n8511; + assign n5982 = (~Ng557 | n8619) & n8620; + assign n5983_1 = n5619 ^ ~n5624; + assign n5984 = ~n5034 | ~n5671 | ~Ng2257 | ~n6485_1; + assign n5985 = n5034 & (n5060 | ~n5671); + assign n5986 = ~n5034 & (n5060 | n5671); + assign n5987 = n5026 | ~Ng2257; + assign n5988_1 = n5984 & (n5985 | n5986 | n5987); + assign n5989 = n5849 | n6291 | n6292 | n6479 | n6480_1 | n6481; + assign n5990 = n4970 | ~n4976 | n4980; + assign n5991 = (~n5859 | ~n5860) & (n5989 | n5990); + assign n5992 = ~n5022 | ~n5668 | ~Ng2257 | ~n6495_1; + assign n5993_1 = n5022 & (n5056 | ~n5668); + assign n5994 = ~n5022 & (n5056 | n5668); + assign n5995 = n5014 | ~Ng2257; + assign n5996 = n5992 & (n5993_1 | n5994 | n5995); + assign n5997 = n5869 | n6315 | n6316 | n6489 | n6490_1 | n6491; + assign n5998_1 = n4962 | ~n4968_1 | n4974; + assign n5999 = (~n5879 | ~n5880) & (n5997 | n5998_1); + assign n6000 = ~n5010 | ~n5665_1 | ~Ng2257 | ~n6505_1; + assign n6001 = n5010 & (n5052 | ~n5665_1); + assign n6002 = ~n5010 & (n5052 | n5665_1); + assign n6003_1 = n5002 | ~Ng2257; + assign n6004 = n6000 & (n6001 | n6002 | n6003_1); + assign n6005 = n5889 | n6339 | n6340 | n6499 | n6500_1 | n6501; + assign n6006 = n4956 | ~n4960 | n4966; + assign n6007 = (~n5899 | ~n5900) & (n6005 | n6006); + assign n6008_1 = ~n4998_1 | ~n5662 | ~Ng2257 | ~n6515_1; + assign n6009 = n4998_1 & (n5050 | ~n5662); + assign n6010 = ~n4998_1 & (n5050 | n5662); + assign n6011 = n4990 | ~Ng2257; + assign n6012 = n6008_1 & (n6009 | n6010 | n6011); + assign n6013_1 = n5909 | n6363_1 | n6364 | n6509 | n6510_1 | n6511; + assign n6014 = n4950 | ~n4954 | n4958_1; + assign n6015 = (~n5919 | ~n5920) & (n6013_1 | n6014); + assign n6016 = n5065 | ~n5066; + assign n6017 = ~n5523 | n6016; + assign n6018_1 = (~Ng1315 | Ng734) & (~\[1603] | Ng736); + assign n6019 = n5034 | ~n5060 | n5671; + assign n6020 = ~n5987 & (~n5060 | n5670_1) & n6019; + assign n6021 = n6154 & Ng2142 & Ng2138; + assign n6022 = n6021 & Ng2133; + assign n6023_1 = n5022 | ~n5056 | n5668; + assign n6024 = ~n5995 & (~n5056 | n5667) & n6023_1; + assign n6025 = n6161 & Ng1448 & Ng1444; + assign n6026 = n6025 & Ng1439; + assign n6027 = n5010 | ~n5052 | n5665_1; + assign n6028_1 = ~n6003_1 & (~n5052 | n5664) & n6027; + assign n6029 = n6168 & Ng762 & Ng758; + assign n6030 = n6029 & Ng753; + assign n6031 = n4998_1 | ~n5050 | n5662; + assign n6032 = ~n6011 & (~n5050 | n5661) & n6031; + assign n6033_1 = n6175_1 & Ng74 & Ng70; + assign n6034 = n6033_1 & Ng65; + assign n6035 = ~n858_1 & n5976; + assign n6036 = (~Ng3105 | n6549) & (n5978_1 | Ng3128); + assign n6037 = (~Ng3103 | n6547) & (~Ng3104 | n6548); + assign n6038_1 = (n6545_1 | ~Ng3101) & (n6546 | ~Ng3102); + assign n6039 = (n6542 | ~Ng3099) & (n6543 | ~Ng3100); + assign n6040 = (n6540_1 | ~Ng3097) & (n6541 | ~Ng3098); + assign n6041 = (~Ng3107 | n6536) & (~Ng3108 | n6538); + assign n6042 = (~Ng3106 | n6535_1) & (n6531 | ~n8756); + assign n6043_1 = Ng2753 & n6550_1; + assign n6044 = Ng2760 & n6043_1; + assign n6045 = (~n4573_1 | ~n5028_1) & (n4567 | ~n5008_1); + assign n6046 = n5008_1 & (~n8522 | (n4571 & ~n5028_1)); + assign n6047 = n4573_1 & (~n8521 | (n4567 & ~n5018_1)); + assign n6048_1 = n5028_1 & n5018_1; + assign n6049 = ~n5008_1 & (n6047 | (n4561 & n6048_1)); + assign n6050 = ~n4573_1 & (n6046 | (~n5036 & ~n6057_1)); + assign n6051 = ~n5028_1 | n4561 | n4571; + assign n6052 = n6051 & (~n4567 | (n4571 & ~n5028_1)); + assign n6053_1 = n5028_1 & (n4573_1 | ~n5036); + assign n6054 = n4567 & (~n5036 | (~n4571 & n6048_1)); + assign n6055 = ~n6054 & (n4561 | n5008_1 | n5036); + assign n6056 = (~n5018_1 & (n4573_1 | n5028_1)) | (~n4573_1 & n5028_1); + assign n6057_1 = n4567 | n4571; + assign n6058 = (~n4561 | n6053_1) & (n6056 | n6057_1); + assign n6059 = n4573_1 | n5018_1 | n6052; + assign n6060 = (~n5008_1 & ~n7061_1) | (n6058 & (n5008_1 | ~n7061_1)); + assign n6061 = n6059 & (~n4573_1 | n6055) & n6060; + assign n6062_1 = n6395 | ~Ng185 | ~Ng2616; + assign n6063 = (~\[1603] | ~Ng2673) & (~\[1605] | ~Ng2670); + assign n6064 = n6062_1 & n6063 & (~Ng1315 | ~Ng2676); + assign n6065 = Ng2059 & n6556; + assign n6066_1 = Ng2066 & n6065; + assign n6067 = (~n4569 | ~n5016) & (n4559_1 | ~n4996); + assign n6068 = n4996 & (~n8525 | (n4565 & ~n5016)); + assign n6069 = n4569 & (~n8524 | (n4559_1 & ~n5006)); + assign n6070 = n5016 & n5006; + assign n6071_1 = ~n4996 & (n6069 | (n4553 & n6070)); + assign n6072 = ~n4569 & (n6068 | (~n5024 & ~n6079)); + assign n6073 = ~n5016 | n4553 | n4565; + assign n6074 = n6073 & (~n4559_1 | (n4565 & ~n5016)); + assign n6075_1 = n5016 & (n4569 | ~n5024); + assign n6076 = n4559_1 & (~n5024 | (~n4565 & n6070)); + assign n6077 = ~n6076 & (n4553 | n4996 | n5024); + assign n6078 = (~n5006 & (n4569 | n5016)) | (~n4569 & n5016); + assign n6079 = n4559_1 | n4565; + assign n6080_1 = (~n4553 | n6075_1) & (n6078 | n6079); + assign n6081 = n4569 | n5006 | n6074; + assign n6082 = (~n4996 & ~n7077) | (n6080_1 & (n4996 | ~n7077)); + assign n6083 = n6081 & (~n4569 | n6077) & n6082; + assign n6084_1 = n4888 | ~Ng185 | ~Ng1922; + assign n6085 = (~\[1603] | ~Ng1979) & (~\[1605] | ~Ng1976); + assign n6086 = n6084_1 & n6085 & (~Ng1315 | ~Ng1982); + assign n6087 = Ng1365 & n6560_1; + assign n6088 = Ng1372 & n6087; + assign n6089_1 = (~n4563 | ~n5004) & (n4551 | ~n4988_1); + assign n6090 = n4988_1 & (~n8528 | (n4557 & ~n5004)); + assign n6091 = n4563 & (~n8527 | (n4551 & ~n4994)); + assign n6092 = n5004 & n4994; + assign n6093_1 = ~n4988_1 & (n6091 | (n4547 & n6092)); + assign n6094 = ~n4563 & (n6090 | (~n5012 & ~n6101)); + assign n6095 = ~n5004 | n4547 | n4557; + assign n6096 = n6095 & (~n4551 | (n4557 & ~n5004)); + assign n6097 = n5004 & (n4563 | ~n5012); + assign n6098_1 = n4551 & (~n5012 | (~n4557 & n6092)); + assign n6099 = ~n6098_1 & (n4547 | n4988_1 | n5012); + assign n6100 = (~n4994 & (n4563 | n5004)) | (~n4563 & n5004); + assign n6101 = n4551 | n4557; + assign n6102_1 = (~n4547 | n6097) & (n6100 | n6101); + assign n6103 = n4563 | n4994 | n6096; + assign n6104 = (~n4988_1 & ~n7093) | (n6102_1 & (n4988_1 | ~n7093)); + assign n6105 = n6103 & (~n4563 | n6099) & n6104; + assign n6106 = n3381_1 | ~Ng185 | ~Ng1228; + assign n6107_1 = (~\[1603] | ~Ng1285) & (~\[1605] | ~Ng1282); + assign n6108 = n6106 & n6107_1 & (~Ng1315 | ~Ng1288); + assign n6109 = Ng679 & n6564; + assign n6110 = Ng686 & n6109; + assign n6111_1 = (~n4555_1 | ~n4992) & (n4545 | ~n4984); + assign n6112 = n4984 & (~n8531 | (n4549 & ~n4992)); + assign n6113 = n4555_1 & (~n8530 | (n4545 & ~n4986)); + assign n6114 = n4992 & n4986; + assign n6115 = ~n4984 & (n6113 | (n4543 & n6114)); + assign n6116_1 = ~n4555_1 & (n6112 | (~n5000 & ~n6123)); + assign n6117 = ~n4992 | n4543 | n4549; + assign n6118 = n6117 & (~n4545 | (n4549 & ~n4992)); + assign n6119 = n4992 & (n4555_1 | ~n5000); + assign n6120_1 = n4545 & (~n5000 | (~n4549 & n6114)); + assign n6121 = ~n6120_1 & (n4543 | n4984 | n5000); + assign n6122 = (~n4986 & (n4555_1 | n4992)) | (~n4555_1 & n4992); + assign n6123 = n4545 | n4549; + assign n6124_1 = (~n4543 | n6119) & (n6122 | n6123); + assign n6125 = n4555_1 | n4986 | n6118; + assign n6126 = (~n4984 & ~n7109) | (n6124_1 & (n4984 | ~n7109)); + assign n6127 = n6125 & (~n4555_1 | n6121) & n6126; + assign n6128_1 = n1875_1 | ~Ng185 | ~Ng542; + assign n6129 = (~\[1603] | ~Ng599) & (~\[1605] | ~Ng596); + assign n6130 = n6128_1 & n6129 & (~Ng1315 | ~Ng602); + assign n6131 = Ng3126 | Ng3191 | Ng3126 | Ng3110; + assign n6132 = n5973_1 & n5978_1; + assign n6133_1 = (n6542 | ~Ng3161) & (n6540_1 | ~Ng3155); + assign n6134 = (n6543 | ~Ng3164) & (n6541 | ~Ng3158); + assign n6135 = (n6545_1 | ~Ng3167) & (n6546 | ~Ng3170); + assign n6136 = (n6548 | ~Ng3176) & (n6549 | ~Ng3179); + assign n6137 = n6547 | ~Ng3173; + assign n6138_1 = (n6536 | ~Ng3185) & (n6535_1 | ~Ng3182); + assign n6139 = (n6132 | ~Ng3135) & (n6538 | ~Ng3088); + assign n6140 = n6139 & n6138_1 & n6137 & n6136 & n6135 & ~n858_1 & n6133_1 & n6134; + assign n6141 = (n6536 | ~Ng3095) & (n6538 | ~Ng3096); + assign n6142 = (n6549 | ~Ng3093) & (n6535_1 | ~Ng3094); + assign n6143_1 = (n6547 | ~Ng3091) & (n6548 | ~Ng3092); + assign n6144 = (n6545_1 | ~Ng3086) & (n6546 | ~Ng3087); + assign n6145 = (n6542 | ~Ng3084) & (n6543 | ~Ng3085); + assign n6146 = (n6540_1 | ~Ng3210) & (n6541 | ~Ng3211); + assign n6147_1 = n8532 & (~Ng3120 | (n5976 & n5978_1)); + assign n6148 = n6147_1 & n6146 & n6145 & n6144 & n6143_1 & ~n858_1 & n6141 & n6142; + assign n6149 = Ng2175 & Ng2190 & Ng2185 & Ng2195 & Ng2200 & Ng2180 & Ng2165 & Ng2170; + assign n6150 = n6149 & (~n8533 | (\[1594] & ~Ng2255)); + assign n6151_1 = n4880_1 & (~n4908 | ~n6150); + assign n6152 = ~n4880_1 & (n4908 | n6150); + assign n6153 = ~Ng2257 | n6151_1 | n6152; + assign n6154 = n6203_1 & Ng2151 & Ng2147; + assign n6155_1 = n6154 & Ng2142; + assign n6156 = Ng1481 & Ng1496 & Ng1491 & Ng1501 & Ng1506 & Ng1486 & Ng1471 & Ng1476; + assign n6157 = n6156 & (~n8534 | (\[1594] & ~Ng1561)); + assign n6158 = n4838_1 & (~n4870 | ~n6157); + assign n6159_1 = ~n4838_1 & (n4870 | n6157); + assign n6160 = ~Ng2257 | n6158 | n6159_1; + assign n6161 = n6207_1 & Ng1457 & Ng1453; + assign n6162 = n6161 & Ng1448; + assign n6163_1 = Ng793 & Ng805 & Ng801 & Ng809 & Ng813 & Ng797 & Ng785 & Ng789; + assign n6164 = n6163_1 & (~n8535 | (\[1594] & ~Ng867)); + assign n6165 = n4796_1 & (~n4828 | ~n6164); + assign n6166 = ~n4796_1 & (n4828 | n6164); + assign n6167_1 = ~Ng2257 | n6165 | n6166; + assign n6168 = n6211_1 & Ng771 & Ng767; + assign n6169 = n6168 & Ng762; + assign n6170 = Ng105 & Ng117 & Ng113 & Ng121 & Ng125 & Ng109 & Ng97 & Ng101; + assign n6171_1 = n6170 & (~n8536 | (\[1594] & ~Ng179)); + assign n6172 = n4754 & (~n4786 | ~n6171_1); + assign n6173 = ~n4754 & (n4786 | n6171_1); + assign n6174 = ~Ng2257 | n6172 | n6173; + assign n6175_1 = n6215_1 & Ng83 & Ng79; + assign n6176 = n6175_1 & Ng74; + assign n6177 = ~n4581 | n4982 | ~Ng2584; + assign n6178 = ~n5028_1 | Pg3229 | n5018_1; + assign n6179_1 = n6178 & (~Pg3229 | n5036) & ~n8670; + assign n6180 = ~n4926 | Pg3229 | n4906; + assign n6181 = n6180 & (~Pg3229 | n4940) & ~n8675; + assign n6182 = ~n4579 | n4978_1 | ~Ng1890; + assign n6183_1 = ~n5016 | Pg3229 | n5006; + assign n6184 = n6183_1 & (~Pg3229 | n5024) & ~n8681; + assign n6185 = ~n4896 | Pg3229 | n4868; + assign n6186 = n6185 & (~Pg3229 | n4920) & ~n8686; + assign n6187_1 = ~n4577_1 | n4972 | ~Ng1196; + assign n6188 = ~n5004 | Pg3229 | n4994; + assign n6189 = n6188 & (~Pg3229 | n5012) & ~n8692; + assign n6190 = ~n4858 | Pg3229 | n4826; + assign n6191_1 = n6190 & (~Pg3229 | n4890) & ~n8697; + assign n6192 = ~n4575 | n4964 | ~Ng510; + assign n6193 = ~n4992 | Pg3229 | n4986; + assign n6194 = n6193 & (~Pg3229 | n5000) & ~n8703; + assign n6195_1 = ~n4816 | Pg3229 | n4784; + assign n6196 = n6195_1 & (~Pg3229 | n4852) & ~n8708; + assign n6197 = ~Ng3013 | n6573; + assign n6198 = n6197 | ~Ng3010; + assign n6199_1 = Ng2903 & n6574_1; + assign n6200 = Ng2900 & n6199_1; + assign n6201 = n6240 & Ng2734 & Ng2720; + assign n6202 = n6201 & Ng2746; + assign n6203_1 = ~n6242 & Ng2160 & Ng2156; + assign n6204 = n6203_1 & Ng2151; + assign n6205 = n6244_1 & Ng2040 & Ng2026; + assign n6206 = n6205 & Ng2052; + assign n6207_1 = ~n6242 & Ng1466 & Ng1462; + assign n6208 = n6207_1 & Ng1457; + assign n6209 = n6247 & Ng1346 & Ng1332; + assign n6210 = n6209 & Ng1358; + assign n6211_1 = ~n6242 & Ng780 & Ng776; + assign n6212 = n6211_1 & Ng771; + assign n6213 = n6250 & Ng660 & Ng646; + assign n6214 = n6213 & Ng672; + assign n6215_1 = ~n6242 & Ng92 & Ng88; + assign n6216 = n6215_1 & Ng83; + assign n6217 = n6395_1 | ~n5127 | ~n5137 | n6396 | n6397 | n6398; + assign n6218 = n6404 | n6402 | n6403_1 | n6399_1 | n6400 | n6401; + assign n6219_1 = ~n4980 | ~n4970 | ~n4976; + assign n6143 = (n6217 | n6218) & (n6219_1 | ~n6487); + assign n6221 = n6405 | ~n5127 | ~n5135_1 | n6406 | n6407 | n6408_1; + assign n6222 = n6414 | n6412_1 | n6413 | n6409 | n6410 | n6411; + assign n6223_1 = ~n4974 | ~n4962 | ~n4968_1; + assign n4636 = (n6221 | n6222) & (n6223_1 | ~n6497); + assign n6225 = n6415 | ~n5127 | ~n5131 | n6416 | n6417_1 | n6418; + assign n6226 = n6424 | n6422_1 | n6423 | n6419 | n6420 | n6421; + assign n6227_1 = ~n4966 | ~n4956 | ~n4960; + assign n3129_1 = (n6225 | n6226) & (n6227_1 | ~n6507); + assign n6229 = n6425 | ~n5126 | ~n5127 | n6426_1 | n6427 | n6428; + assign n6230 = n6434 | n6432 | n6433 | n6429 | n6430 | n6431_1; + assign n6231_1 = ~n4958_1 | ~n4950 | ~n4954; + assign n1623_1 = (n6229 | n6230) & (n6231_1 | ~n6517); + assign n6233 = ~Ng3028 & ~Ng3036 & Ng3032 & Ng3018; + assign n6234 = n6256 | Pg3234; + assign n6235_1 = n6256 & Ng3028 & Ng3018; + assign n6236 = n6235_1 & Ng3036; + assign n6237 = ~Ng2917 & ~Ng2924 & Ng2912 & Ng2920; + assign n6238 = n6258 & Ng2912 & Ng2917; + assign n6239_1 = n6238 & Ng2924; + assign n6240 = n6260 & Ng2727 & Ng2707; + assign n6241 = n6240 & Ng2720; + assign n6242 = ~Ng853 | ~n5127; + assign n6243 = n6242 | ~Ng2160; + assign n6244_1 = n6262 & Ng2033 & Ng2013; + assign n6245 = n6244_1 & Ng2026; + assign n6246 = n6242 | ~Ng1466; + assign n6247 = n6264 & Ng1339 & Ng1319; + assign n6248 = n6247 & Ng1332; + assign n6249_1 = n6242 | ~Ng780; + assign n6250 = n6266 & Ng653 & Ng633; + assign n6251 = n6250 & Ng646; + assign n6252 = n6242 | ~Ng92; + assign n6253 = ~n6572 | ~Ng3006; + assign n6254_1 = Ng2883 & Ng13457 & Ng2888; + assign n6255 = n6254_1 & Ng2896; + assign n6256 = n6551 & Ng13475; + assign n6257 = n6256 & Ng3018; + assign n6258 = Ng2888 & Ng2908 & Ng2903 & Ng2892 & ~Ng2883 & Ng13457 & ~Ng2900 & ~Ng2896; + assign n6259_1 = n6258 & Ng2912; + assign n6260 = Ng1315 & ~Ng2733 & Ng2714; + assign n6261 = n6260 & Ng2707; + assign n6262 = Ng1315 & ~Ng2039 & Ng2020; + assign n6263_1 = n6262 & Ng2013; + assign n6264 = Ng1315 & ~Ng1345 & Ng1326; + assign n6265 = n6264 & Ng1319; + assign n6266 = Ng1315 & ~Ng659 & Ng640; + assign n6267_1 = n6266 & Ng633; + assign n6268 = Ng2883 & Ng13457; + assign n6269 = ~Ng1315 | Ng2733; + assign n6270 = ~Ng1315 | n6271; + assign n6271 = Ng1315 & n6555_1; + assign n6272_1 = ~Ng1315 | Ng2039; + assign n6273 = ~Ng1315 | Ng1345; + assign n6274 = ~Ng1315 | Ng659; + assign n6275 = ~Ng1315 | n6276_1; + assign n6276_1 = n8750 & Ng1315; + assign n6277 = ~n5848_1 & n5851 & (n4643 | ~n5859); + assign n6278 = ~n5868_1 & n5871 & (n4639 | ~n5879); + assign n6279 = ~n5888_1 & n5891 & (n4633 | ~n5899); + assign n6280 = ~n5908_1 & n5911 & (n4625 | ~n5919); + assign n6281_1 = ~Ng185 | ~Ng3139; + assign n6282 = n6281_1 & ~n6523 & (Ng3139 | ~n8756); + assign n6283 = ~Pg3234 & (n6234 | ~n6394); + assign n7111 = ~n6283; + assign n6285_1 = n4744 ^ ~Ng2195; + assign n6286 = n4874 ^ ~Ng2170; + assign n6287 = n4680_1 ^ ~Ng2180; + assign n6288 = n4668_1 ^ ~Ng2175; + assign n6289 = n4772 ^ ~Ng2200; + assign n6290_1 = n4718 ^ ~Ng2190; + assign n6291 = n4698 ^ ~Ng2185; + assign n6292 = n4842_1 ^ ~Ng2165; + assign n6293 = n4924_1 ^ ~Ng2175; + assign n6294_1 = n4902 ^ ~Ng2165; + assign n6295 = n4720_1 ^ ~Ng2195; + assign n6296 = n4938_1 ^ ~Ng2185; + assign n6297 = n4810_1 ^ ~Ng2180; + assign n6298 = n4904 ^ ~n5044; + assign n6299_1 = n4876_1 ^ ~Ng2200; + assign n6300 = n4774_1 ^ ~Ng2170; + assign n6301 = n4938_1 ^ ~n5926; + assign n6302 = ~n4902 ^ ~n5926; + assign n6303_1 = ~n4774_1 ^ ~n5926; + assign n6304 = ~n4924_1 ^ ~n5926; + assign n6305 = ~n4810_1 ^ ~n5926; + assign n6306 = n6304 | n6308_1; + assign n6307 = n5864 | n6302; + assign n6308_1 = n6303_1 | n6307; + assign n6309 = n4658 ^ ~Ng1481; + assign n6310 = n4666 ^ ~Ng1486; + assign n6311 = n4800 ^ ~Ng1471; + assign n6312_1 = n4678 ^ ~Ng1491; + assign n6313 = n4832 ^ ~Ng1476; + assign n6314 = n4694 ^ ~Ng1496; + assign n6315 = n4736 ^ ~Ng1506; + assign n6316 = n4714 ^ ~Ng1501; + assign n6317_1 = n4894 ^ ~Ng1481; + assign n6318 = n4864 ^ ~Ng1471; + assign n6319 = n4696_1 ^ ~Ng1501; + assign n6320 = n4918 ^ ~Ng1491; + assign n6321_1 = n4768 ^ ~Ng1486; + assign n6322 = n4866_1 ^ ~n5040; + assign n6323 = n4834_1 ^ ~Ng1506; + assign n6324 = n4738 ^ ~Ng1476; + assign n6325 = n4918 ^ ~n5933_1; + assign n6326_1 = ~n4864 ^ ~n5933_1; + assign n6327 = ~n4738 ^ ~n5933_1; + assign n6328 = ~n4894 ^ ~n5933_1; + assign n6329 = ~n4768 ^ ~n5933_1; + assign n6330 = n6328 | n6332; + assign n6331_1 = n5884 | n6326_1; + assign n6332 = n6327 | n6331_1; + assign n6333 = n4651 ^ ~Ng793; + assign n6334 = n4790 ^ ~Ng789; + assign n6335 = n4706 ^ ~Ng813; + assign n6336_1 = n4656_1 ^ ~Ng797; + assign n6337 = n4690 ^ ~Ng809; + assign n6338 = n4674 ^ ~Ng805; + assign n6339 = n4664_1 ^ ~Ng801; + assign n6340 = n4758 ^ ~Ng785; + assign n6341_1 = n4856_1 ^ ~Ng793; + assign n6342 = n4822 ^ ~Ng785; + assign n6343 = n4676_1 ^ ~Ng809; + assign n6344 = n4888_1 ^ ~Ng801; + assign n6345_1 = n4732_1 ^ ~Ng797; + assign n6346 = n4824_1 ^ ~n5032; + assign n6347 = n4792_1 ^ ~Ng813; + assign n6348 = n4708_1 ^ ~Ng789; + assign n6349_1 = n4888_1 ^ ~n5940; + assign n6350 = ~n4822 ^ ~n5940; + assign n6351 = ~n4708_1 ^ ~n5940; + assign n6352 = ~n4856_1 ^ ~n5940; + assign n6353_1 = ~n4732_1 ^ ~n5940; + assign n6354 = n6352 | n6356; + assign n6355 = n5904 | n6350; + assign n6356 = n6351 | n6355; + assign n6357 = n4647 ^ ~Ng105; + assign n6358_1 = n4748 ^ ~Ng101; + assign n6359 = n4682 ^ ~Ng125; + assign n6360 = n4649 ^ ~Ng109; + assign n6361 = n4670 ^ ~Ng121; + assign n6362 = n4660_1 ^ ~Ng117; + assign n6363_1 = n4654 ^ ~Ng113; + assign n6364 = n4722 ^ ~Ng97; + assign n6365 = n4814_1 ^ ~Ng105; + assign n6366 = n4780 ^ ~Ng97; + assign n6367 = n4662 ^ ~Ng121; + assign n6368_1 = n4850 ^ ~Ng113; + assign n6369 = n4702 ^ ~Ng109; + assign n6370 = n4782 ^ ~n5020; + assign n6371 = n4750 ^ ~Ng125; + assign n6372 = n4684_1 ^ ~Ng101; + assign n6373_1 = n4850 ^ ~n5947; + assign n6374 = ~n4780 ^ ~n5947; + assign n6375 = ~n4684_1 ^ ~n5947; + assign n6376 = ~n4814_1 ^ ~n5947; + assign n6377 = ~n4702 ^ ~n5947; + assign n6378_1 = n6376 | n6380; + assign n6379 = n5924 | n6374; + assign n6380 = n6375 | n6379; + assign n6381 = ~n4846_1 ^ ~n5855; + assign n6382 = (~Ng2190 | n5863_1) & (~n5865 | n6381); + assign n6383_1 = ~n4804 ^ ~n5875; + assign n6384 = (~Ng1496 | n5883_1) & (~n5885 | n6383_1); + assign n6385 = ~n4762 ^ ~n5895; + assign n6386 = (~Ng805 | n5903_1) & (~n5905 | n6385); + assign n6387_1 = ~n4726 ^ ~n5915; + assign n6388 = (~Ng117 | n5923_1) & (~n5925 | n6387_1); + assign n6389 = Pg3229 ^ ~n4878; + assign n6390 = Pg3229 ^ ~n4836; + assign n6391_1 = Pg3229 ^ ~n4794; + assign n6392 = Pg3229 ^ ~n4752_1; + assign n6393 = Ng13475 & Ng2993; + assign n6394 = ~n6393 ^ ~Ng2998; + assign n6395_1 = n4904 ^ ~Ng2120; + assign n6396 = n4876_1 ^ ~Ng2129; + assign n6397 = n4746 ^ ~Ng2124; + assign n6398 = n4720_1 ^ ~Ng2133; + assign n6399_1 = n4924_1 ^ ~Ng2151; + assign n6400 = n4938_1 ^ ~Ng2142; + assign n6401 = n4846_1 ^ ~Ng2138; + assign n6402 = n4902 ^ ~Ng2160; + assign n6403_1 = n4810_1 ^ ~Ng2147; + assign n6404 = n4774_1 ^ ~Ng2156; + assign n6405 = n4866_1 ^ ~Ng1426; + assign n6406 = n4834_1 ^ ~Ng1435; + assign n6407 = n4716_1 ^ ~Ng1430; + assign n6408_1 = n4696_1 ^ ~Ng1439; + assign n6409 = n4894 ^ ~Ng1457; + assign n6410 = n4918 ^ ~Ng1448; + assign n6411 = n4804 ^ ~Ng1444; + assign n6412_1 = n4864 ^ ~Ng1466; + assign n6413 = n4768 ^ ~Ng1453; + assign n6414 = n4738 ^ ~Ng1462; + assign n6415 = n4824_1 ^ ~Ng740; + assign n6416 = n4792_1 ^ ~Ng749; + assign n6417_1 = n4692_1 ^ ~Ng744; + assign n6418 = n4676_1 ^ ~Ng753; + assign n6419 = n4856_1 ^ ~Ng771; + assign n6420 = n4888_1 ^ ~Ng762; + assign n6421 = n4762 ^ ~Ng758; + assign n6422_1 = n4822 ^ ~Ng780; + assign n6423 = n4732_1 ^ ~Ng767; + assign n6424 = n4708_1 ^ ~Ng776; + assign n6425 = n4782 ^ ~Ng52; + assign n6426_1 = n4750 ^ ~Ng61; + assign n6427 = n4672_1 ^ ~Ng56; + assign n6428 = n4662 ^ ~Ng65; + assign n6429 = n4814_1 ^ ~Ng83; + assign n6430 = n4850 ^ ~Ng74; + assign n6431_1 = n4726 ^ ~Ng70; + assign n6432 = n4780 ^ ~Ng92; + assign n6433 = n4702 ^ ~Ng79; + assign n6434 = n4684_1 ^ ~Ng88; + assign n6435_1 = n4952 ^ ~Ng2760; + assign n6436 = n4942 ^ ~Ng2740; + assign n6437 = n4948_1 ^ ~Ng2753; + assign n6438 = n4778_1 ^ ~Ng2766; + assign n6439 = n4812 ^ ~Ng2707; + assign n6440_1 = n4910_1 ^ ~Ng2734; + assign n6441 = n4848 ^ ~Ng2727; + assign n6442 = n4882 ^ ~Ng2720; + assign n6443 = n4928_1 ^ ~Ng2746; + assign n6444 = n4776 ^ ~Ng2714; + assign n6445_1 = n4944 ^ ~Ng2066; + assign n6446 = n4922 ^ ~Ng2046; + assign n6447 = n4936 ^ ~Ng2059; + assign n6448 = n4742_1 ^ ~Ng2072; + assign n6449 = n4770 ^ ~Ng2013; + assign n6450_1 = n4872 ^ ~Ng2040; + assign n6451 = n4806 ^ ~Ng2033; + assign n6452 = n4840 ^ ~Ng2026; + assign n6453 = n4898 ^ ~Ng2052; + assign n6454 = n4740 ^ ~Ng2020; + assign n6455_1 = n4932 ^ ~Ng1372; + assign n6456 = n4892_1 ^ ~Ng1352; + assign n6457 = n4916 ^ ~Ng1365; + assign n6458 = n4712_1 ^ ~Ng1378; + assign n6459 = n4734 ^ ~Ng1319; + assign n6460_1 = n4830 ^ ~Ng1346; + assign n6461 = n4764 ^ ~Ng1339; + assign n6462 = n4798 ^ ~Ng1332; + assign n6463 = n4860 ^ ~Ng1358; + assign n6464 = n4710 ^ ~Ng1326; + assign n6465_1 = n4912 ^ ~Ng686; + assign n6466 = n4854 ^ ~Ng666; + assign n6467 = n4886 ^ ~Ng679; + assign n6468 = n4688_1 ^ ~Ng692; + assign n6469 = n4704_1 ^ ~Ng633; + assign n6470_1 = n4788 ^ ~Ng660; + assign n6471 = n4728_1 ^ ~Ng653; + assign n6472 = n4756_1 ^ ~Ng646; + assign n6473 = n4818 ^ ~Ng672; + assign n6474 = n4686 ^ ~Ng640; + assign n6417 = ~n6603; + assign n6476 = ~n5072_1 | n5591; + assign n4910 = ~n6602_1; + assign n6478 = ~n5070 | n5574; + assign n6479 = ~n4808 ^ ~n5046; + assign n6480_1 = ~n4844 ^ ~n5044; + assign n6481 = n6290_1 | n6288 | n6289 | n6285_1 | n6286 | n6287; + assign n6482 = n6295 | n6293 | n6294_1; + assign n6483 = n5848_1 | n5854; + assign n6484 = ~n5849 & n5850; + assign n6485_1 = Ng2257 & n4946; + assign n6486 = n4938_1 & n4720_1 & n4902 & n4846_1 & n4876_1; + assign n6487 = n4904 & n4810_1 & n6486 & n4746 & n4924_1 & n4774_1; + assign n6488 = n6304 | n6305; + assign n6489 = ~n4766 ^ ~n5042; + assign n6490_1 = ~n4802 ^ ~n5040; + assign n6491 = n6314 | n6312_1 | n6313 | n6309 | n6310 | n6311; + assign n6492 = n6319 | n6317_1 | n6318; + assign n6493 = n5868_1 | n5874; + assign n6494 = ~n5869 & n5870; + assign n6495_1 = Ng2257 & n4934; + assign n6496 = n4918 & n4696_1 & n4864 & n4804 & n4834_1; + assign n6497 = n4866_1 & n4768 & n6496 & n4716_1 & n4894 & n4738; + assign n6498 = n6328 | n6329; + assign n6499 = ~n4730 ^ ~n5038_1; + assign n6500_1 = ~n4760_1 ^ ~n5032; + assign n6501 = n6338 | n6336_1 | n6337 | n6333 | n6334 | n6335; + assign n6502 = n6343 | n6341_1 | n6342; + assign n6503 = n5888_1 | n5894; + assign n6504 = ~n5889 & n5890; + assign n6505_1 = Ng2257 & n4914; + assign n6506 = n4888_1 & n4676_1 & n4822 & n4762 & n4792_1; + assign n6507 = n4824_1 & n4732_1 & n6506 & n4692_1 & n4856_1 & n4708_1; + assign n6508 = n6352 | n6353_1; + assign n6509 = ~n4700_1 ^ ~n5030; + assign n6510_1 = ~n4724_1 ^ ~n5020; + assign n6511 = n6362 | n6360 | n6361 | n6357 | n6358_1 | n6359; + assign n6512 = n6367 | n6365 | n6366; + assign n6513 = n5908_1 | n5914; + assign n6514 = ~n5909 & n5910; + assign n6515_1 = Ng2257 & n4884_1; + assign n6516 = n4850 & n4662 & n4780 & n4726 & n4750; + assign n6517 = n4782 & n4702 & n6516 & n4672_1 & n4814_1 & n4684_1; + assign n6518 = n6376 | n6377; + assign n3403_1 = ~n6601; + assign n6520_1 = ~n5068 | n5549; + assign n6521 = ~Ng853 | ~Ng2257; + assign n6522 = Ng3139 | Ng3120; + assign n6523 = Ng3126 | Ng3191 | Ng3126 | ~Ng3110; + assign n6524 = Ng3139 | ~Ng3120; + assign n1897_1 = ~n6600; + assign n6526 = ~n5066 | n5523; + assign n6527 = ~n5060 | n5672 | n5987; + assign n6528 = ~n5056 | n5669 | n5995; + assign n6529 = ~n5052 | n5666 | n6003_1; + assign n6530_1 = ~n5050 | n5663 | n6011; + assign n6531 = n6522 | n6131 | Ng3135 | Ng3147; + assign n6532 = Ng3147 | n6523; + assign n6533 = ~Ng3139 | Ng3120; + assign n6534 = ~Ng3135 | n6532; + assign n6535_1 = n6533 | n6534; + assign n6536 = n5974 | n6532; + assign n6537 = ~Ng3139 | ~Ng3120; + assign n6538 = n6534 | n6537; + assign n6539 = Ng3135 | n6532; + assign n6540_1 = n6522 | n6539; + assign n6541 = n6533 | n6539; + assign n6542 = n6524 | n6539; + assign n6543 = n6537 | n6539; + assign n6544 = ~Ng3147 | n6523 | Ng3135; + assign n6545_1 = n6522 | n6544; + assign n6546 = n6533 | n6544; + assign n6547 = n6524 | n6544; + assign n6548 = n6537 | n6544; + assign n6549 = n6522 | n6534; + assign n6550_1 = n6201 & Ng2740 & Ng2746; + assign n6551 = ~Ng3010 & ~Ng3006 & ~Ng2993 & Ng3002 & Ng3013 & Ng2998 & Ng3024; + assign n6552 = ~n5018_1 | ~n5036; + assign n6553 = n4571 & ~n5018_1 & ~n6045; + assign n6554 = n6050 | n6553 | n6049; + assign n6555_1 = Ng3028 & n6551 & ~Ng3032 & Ng3018 & ~Ng3036; + assign n6556 = n6205 & Ng2046 & Ng2052; + assign n6557 = ~n5006 | ~n5024; + assign n6558 = n4565 & ~n5006 & ~n6067; + assign n6559 = n6072 | n6558 | n6071_1; + assign n6560_1 = n6209 & Ng1352 & Ng1358; + assign n6561 = ~n4994 | ~n5012; + assign n6562 = n4557 & ~n4994 & ~n6089_1; + assign n6563 = n6094 | n6562 | n6093_1; + assign n6564 = n6213 & Ng666 & Ng672; + assign n6565_1 = ~n4986 | ~n5000; + assign n6566 = n4549 & ~n4986 & ~n6111_1; + assign n6567 = n6116_1 | n6566 | n6115; + assign n6568 = n8661 & (n4880_1 | ~n4908 | ~n6150); + assign n6569 = n8662 & (n4838_1 | ~n4870 | ~n6157); + assign n6570_1 = n8663 & (n4796_1 | ~n4828 | ~n6164); + assign n6571 = n8664 & (n4754 | ~n4786 | ~n6171_1); + assign n6572 = Ng2998 & n6393; + assign n6573 = ~Ng3006 | ~Ng3002 | ~n6572; + assign n6574_1 = n6254_1 & Ng2892 & Ng2896; + assign n6575 = Ng2599 & ~Ng2733 & Ng2612; + assign n6576 = n5127 | Ng2912 | Ng2920 | ~Ng2924 | Ng2917 | ~Ng2883 | Ng2888; + assign n6577 = Ng1905 & ~Ng2039 & Ng1918; + assign n6578 = Ng1211 & ~Ng1345 & Ng1224; + assign n6579_1 = Ng525 & ~Ng659 & Ng538; + assign n6580 = ~n4902 ^ ~n5864; + assign n6581 = ~n4864 ^ ~n5884; + assign n6582 = ~n4822 ^ ~n5904; + assign n6583 = ~n4780 ^ ~n5924; + assign n6584_1 = ~Ng3024 ^ ~n6198; + assign n6585 = ~n4880_1 ^ ~n6150; + assign n6586 = ~n4838_1 ^ ~n6157; + assign n6587_1 = ~n4796_1 ^ ~n6164; + assign n6588 = ~n4754 ^ ~n6171_1; + assign n6589 = ~n4532 ^ ~n4541_1; + assign n7213 = ~Ng3083 ^ ~n6589; + assign n6591 = ~n4535 ^ ~n4538; + assign n7255 = ~Ng2990 ^ ~n6591; + assign n7209 = n6589 ^ ~n8762; + assign n7260 = n6591 ^ ~n8762; + assign n6595 = ~n5607 ^ ~n5612; + assign n344 = ~Ng2934 ^ ~n6595; + assign n6597_1 = ~n5597 ^ ~n5602; + assign n349_1 = ~Ng2962 ^ ~n6597_1; + assign n6599 = (~n4952 & ~n8454) | (~n4982 & (n4952 | ~n8454)); + assign n6600 = n8550 & (~Ng8284 | ~Ng544); + assign n6601 = (n8551 & (~Ng8293 | ~Ng1230)) | (Ng8293 & ~Ng1230); + assign n6602_1 = (n8552 & (~Ng8302 | ~Ng1924)) | (Ng8302 & ~Ng1924); + assign n6603 = (n8553 & (~Ng8311 | ~Ng2618)) | (Ng8311 & ~Ng2618); + assign n6604 = (~n5064 & (n4778_1 | n8455)) | (~n4778_1 & n8455); + assign n6605 = (~n5064 & (n4812 | n8455)) | (~n4812 & n8455); + assign n6606 = (~n5064 & (n4882 | n8455)) | (~n4882 & n8455); + assign n6607_1 = (~n4848 & ~n8454) | (~n4982 & (n4848 | ~n8454)); + assign n6608 = (Ng1315 & n6603) | (~Ng3108 & (~Ng1315 | n6603)); + assign n784_1 = ~n6608; + assign n6610 = (\[1603] & n6603) | (~Ng3107 & (~\[1603] | n6603)); + assign n779 = ~n6610; + assign n6612_1 = (\[1605] & n6603) | (~Ng3106 & (~\[1605] | n6603)); + assign n774 = ~n6612_1; + assign n6614 = (~n4944 & ~n8452) | (~n4978_1 & (n4944 | ~n8452)); + assign n6615 = (~n5062 & (n4742_1 | n8453)) | (~n4742_1 & n8453); + assign n6616 = (~n5062 & (n4770 | n8453)) | (~n4770 & n8453); + assign n6617_1 = (~n5062 & (n4840 | n8453)) | (~n4840 & n8453); + assign n6618 = (~n4806 & ~n8452) | (~n4978_1 & (n4806 | ~n8452)); + assign n6619 = (Ng853 & n8565) | (~Ng2392 & (~Ng853 | n8565)); + assign n6003 = ~n6619; + assign n6621 = (\[1594] & n8565) | (~Ng2391 & (~\[1594] | n8565)); + assign n5998 = ~n6621; + assign n6623 = (\[1612] & n8565) | (~Ng2390 & (~\[1612] | n8565)); + assign n5993 = ~n6623; + assign n6625 = n6486 & ~n4924_1 & ~n4904 & ~n4810_1 & ~n4746 & ~n4774_1; + assign n6626 = (~n5926 & n6625) | (n6487 & (n5926 | n6625)); + assign n6627_1 = (~Ng853 & ~Ng2348) | (~n5503 & (Ng853 | ~Ng2348)); + assign n5760 = ~n6627_1; + assign n6629 = (~\[1594] & ~Ng2345) | (~n5503 & (\[1594] | ~Ng2345)); + assign n5755 = ~n6629; + assign n6631 = (~\[1612] & ~Ng2342) | (~n5503 & (\[1612] | ~Ng2342)); + assign n5750 = ~n6631; + assign n6633 = (~Ng853 & ~Ng2321) | (~n5485_1 & (Ng853 | ~Ng2321)); + assign n5670 = ~n6633; + assign n6635 = (~\[1594] & ~Ng2318) | (~n5485_1 & (\[1594] | ~Ng2318)); + assign n5665 = ~n6635; + assign n6637_1 = (~\[1612] & ~Ng2315) | (~n5485_1 & (\[1612] | ~Ng2315)); + assign n5660 = ~n6637_1; + assign n6639 = (~Ng853 & ~Ng2312) | (~n5479 & (Ng853 | ~Ng2312)); + assign n5640 = ~n6639; + assign n6641 = (~\[1594] & ~Ng2309) | (~n5479 & (\[1594] | ~Ng2309)); + assign n5635 = ~n6641; + assign n6643 = (~\[1612] & ~Ng2306) | (~n5479 & (\[1612] | ~Ng2306)); + assign n5630 = ~n6643; + assign n6645 = (~Ng853 & ~Ng2303) | (~n5473 & (Ng853 | ~Ng2303)); + assign n5745 = ~n6645; + assign n6647_1 = (~\[1594] & ~Ng2300) | (~n5473 & (\[1594] | ~Ng2300)); + assign n5740 = ~n6647_1; + assign n6649 = (~\[1612] & ~Ng2297) | (~n5473 & (\[1612] | ~Ng2297)); + assign n5735 = ~n6649; + assign n6651 = (~Ng853 & ~Ng2276) | (~n5506 & (Ng853 | ~Ng2276)); + assign n5655 = ~n6651; + assign n6653 = (~\[1594] & ~Ng2273) | (~n5506 & (\[1594] | ~Ng2273)); + assign n5650 = ~n6653; + assign n6655 = (~\[1612] & ~Ng2270) | (~n5506 & (\[1612] | ~Ng2270)); + assign n5645 = ~n6655; + assign n6657_1 = (Ng853 & n8570) | (~Ng1698 & (~Ng853 | n8570)); + assign n4496 = ~n6657_1; + assign n6659 = (\[1594] & n8570) | (~Ng1697 & (~\[1594] | n8570)); + assign n4491 = ~n6659; + assign n6661 = (\[1612] & n8570) | (~Ng1696 & (~\[1612] | n8570)); + assign n4486 = ~n6661; + assign n6663 = n6496 & ~n4894 & ~n4866_1 & ~n4768 & ~n4716_1 & ~n4738; + assign n6664 = (~n5933_1 & n6663) | (n6497 & (n5933_1 | n6663)); + assign n6665 = (~Ng853 & ~Ng1654) | (~n5497 & (Ng853 | ~Ng1654)); + assign n4266 = ~n6665; + assign n6667_1 = (~\[1594] & ~Ng1651) | (~n5497 & (\[1594] | ~Ng1651)); + assign n4261_1 = ~n6667_1; + assign n6669 = (~\[1612] & ~Ng1648) | (~n5497 & (\[1612] | ~Ng1648)); + assign n4256 = ~n6669; + assign n6671 = (~Ng853 & ~Ng1627) | (~n5476 & (Ng853 | ~Ng1627)); + assign n4176 = ~n6671; + assign n6673 = (~\[1594] & ~Ng1624) | (~n5476 & (\[1594] | ~Ng1624)); + assign n4171 = ~n6673; + assign n6675 = (~\[1612] & ~Ng1621) | (~n5476 & (\[1612] | ~Ng1621)); + assign n4166 = ~n6675; + assign n6677_1 = (~Ng853 & ~Ng1618) | (~n5470_1 & (Ng853 | ~Ng1618)); + assign n4146 = ~n6677_1; + assign n6679 = (~\[1594] & ~Ng1615) | (~n5470_1 & (\[1594] | ~Ng1615)); + assign n4141 = ~n6679; + assign n6681 = (~\[1612] & ~Ng1612) | (~n5470_1 & (\[1612] | ~Ng1612)); + assign n4136_1 = ~n6681; + assign n6683 = (~Ng853 & ~Ng1609) | (~n5464 & (Ng853 | ~Ng1609)); + assign n4251 = ~n6683; + assign n6685 = (~\[1594] & ~Ng1606) | (~n5464 & (\[1594] | ~Ng1606)); + assign n4246 = ~n6685; + assign n6687_1 = (~\[1612] & ~Ng1603) | (~n5464 & (\[1612] | ~Ng1603)); + assign n4241_1 = ~n6687_1; + assign n6689 = (~Ng853 & ~Ng1582) | (~n5500_1 & (Ng853 | ~Ng1582)); + assign n4161 = ~n6689; + assign n6691 = (~\[1594] & ~Ng1579) | (~n5500_1 & (\[1594] | ~Ng1579)); + assign n4156 = ~n6691; + assign n6693 = (~\[1612] & ~Ng1576) | (~n5500_1 & (\[1612] | ~Ng1576)); + assign n4151 = ~n6693; + assign n6695 = (Ng853 & n8575) | (~Ng1004 & (~Ng853 | n8575)); + assign n2989_1 = ~n6695; + assign n6697_1 = (\[1594] & n8575) | (~Ng1003 & (~\[1594] | n8575)); + assign n2984_1 = ~n6697_1; + assign n6699 = (\[1612] & n8575) | (~Ng1002 & (~\[1612] | n8575)); + assign n2979_1 = ~n6699; + assign n6701 = n6506 & ~n4856_1 & ~n4824_1 & ~n4732_1 & ~n4692_1 & ~n4708_1; + assign n6702_1 = (~n5940 & n6701) | (n6507 & (n5940 | n6701)); + assign n6703 = (~Ng853 & ~Ng960) | (~n5491 & (Ng853 | ~Ng960)); + assign n2759_1 = ~n6703; + assign n6705 = (~\[1594] & ~Ng957) | (~n5491 & (\[1594] | ~Ng957)); + assign n2754_1 = ~n6705; + assign n6707_1 = (~\[1612] & ~Ng954) | (~n5491 & (\[1612] | ~Ng954)); + assign n2749_1 = ~n6707_1; + assign n6709 = (~Ng853 & ~Ng933) | (~n5467 & (Ng853 | ~Ng933)); + assign n2669 = ~n6709; + assign n6711 = (~\[1594] & ~Ng930) | (~n5467 & (\[1594] | ~Ng930)); + assign n2664 = ~n6711; + assign n6713 = (~\[1612] & ~Ng927) | (~n5467 & (\[1612] | ~Ng927)); + assign n2659 = ~n6713; + assign n6715 = (~Ng853 & ~Ng924) | (~n5461 & (Ng853 | ~Ng924)); + assign n2639 = ~n6715; + assign n6717_1 = (~\[1594] & ~Ng921) | (~n5461 & (\[1594] | ~Ng921)); + assign n2634 = ~n6717_1; + assign n6719 = (~\[1612] & ~Ng918) | (~n5461 & (\[1612] | ~Ng918)); + assign n2629 = ~n6719; + assign n6721 = (~Ng853 & ~Ng915) | (~n5455_1 & (Ng853 | ~Ng915)); + assign n2744_1 = ~n6721; + assign n6723 = (~\[1594] & ~Ng912) | (~n5455_1 & (\[1594] | ~Ng912)); + assign n2739_1 = ~n6723; + assign n6725 = (~\[1612] & ~Ng909) | (~n5455_1 & (\[1612] | ~Ng909)); + assign n2734_1 = ~n6725; + assign n6727_1 = (~Ng853 & ~Ng888) | (~n5494 & (Ng853 | ~Ng888)); + assign n2654 = ~n6727_1; + assign n6729 = (~\[1594] & ~Ng885) | (~n5494 & (\[1594] | ~Ng885)); + assign n2649 = ~n6729; + assign n6731 = (~\[1612] & ~Ng882) | (~n5494 & (\[1612] | ~Ng882)); + assign n2644 = ~n6731; + assign n6733 = (Ng853 & n8580) | (~Ng317 & (~Ng853 | n8580)); + assign n1483_1 = ~n6733; + assign n6735 = (\[1594] & n8580) | (~Ng316 & (~\[1594] | n8580)); + assign n1478_1 = ~n6735; + assign n6737_1 = (\[1612] & n8580) | (~Ng315 & (~\[1612] | n8580)); + assign n1473_1 = ~n6737_1; + assign n6739 = n6516 & ~n4814_1 & ~n4782 & ~n4702 & ~n4672_1 & ~n4684_1; + assign n6740 = (~n5947 & n6739) | (n6517 & (n5947 | n6739)); + assign n6741 = (~Ng853 & ~Ng273) | (~n5482 & (Ng853 | ~Ng273)); + assign n1253_1 = ~n6741; + assign n6743 = (~\[1594] & ~Ng270) | (~n5482 & (\[1594] | ~Ng270)); + assign n1248_1 = ~n6743; + assign n6745 = (~\[1612] & ~Ng267) | (~n5482 & (\[1612] | ~Ng267)); + assign n1243_1 = ~n6745; + assign n6747_1 = (~Ng853 & ~Ng246) | (~n5458 & (Ng853 | ~Ng246)); + assign n1163_1 = ~n6747_1; + assign n6749 = (~\[1594] & ~Ng243) | (~n5458 & (\[1594] | ~Ng243)); + assign n1158_1 = ~n6749; + assign n6751 = (~\[1612] & ~Ng240) | (~n5458 & (\[1612] | ~Ng240)); + assign n1153_1 = ~n6751; + assign n6753 = (~Ng853 & ~Ng237) | (~n5452 & (Ng853 | ~Ng237)); + assign n1133_1 = ~n6753; + assign n6755 = (~\[1594] & ~Ng234) | (~n5452 & (\[1594] | ~Ng234)); + assign n1128_1 = ~n6755; + assign n6757_1 = (~\[1612] & ~Ng231) | (~n5452 & (\[1612] | ~Ng231)); + assign n1123_1 = ~n6757_1; + assign n6759 = (~Ng853 & ~Ng228) | (~n5449 & (Ng853 | ~Ng228)); + assign n1238_1 = ~n6759; + assign n6761 = (~\[1594] & ~Ng225) | (~n5449 & (\[1594] | ~Ng225)); + assign n1233_1 = ~n6761; + assign n6763 = (~\[1612] & ~Ng222) | (~n5449 & (\[1612] | ~Ng222)); + assign n1228_1 = ~n6763; + assign n6765 = (~Ng853 & ~Ng201) | (~n5488 & (Ng853 | ~Ng201)); + assign n1148_1 = ~n6765; + assign n6767_1 = (~\[1594] & ~Ng198) | (~n5488 & (\[1594] | ~Ng198)); + assign n1143_1 = ~n6767_1; + assign n6769 = (~\[1612] & ~Ng195) | (~n5488 & (\[1612] | ~Ng195)); + assign n1138_1 = ~n6769; + assign n6771 = (~Ng853 & ~Ng2395) | (~n5446 & (Ng853 | ~Ng2395)); + assign n6018 = ~n6771; + assign n6773 = (\[1594] & ~n5446) | (~Ng2394 & (~\[1594] | ~n5446)); + assign n6013 = ~n6773; + assign n6775 = (~\[1612] & ~Ng2393) | (~n5446 & (\[1612] | ~Ng2393)); + assign n6008 = ~n6775; + assign n6777_1 = (~Ng853 & ~Ng1701) | (~n5443 & (Ng853 | ~Ng1701)); + assign n4511 = ~n6777_1; + assign n6779 = (\[1594] & ~n5443) | (~Ng1700 & (~\[1594] | ~n5443)); + assign n4506_1 = ~n6779; + assign n6781 = (~\[1612] & ~Ng1699) | (~n5443 & (\[1612] | ~Ng1699)); + assign n4501 = ~n6781; + assign n6783 = (~Ng853 & ~Ng1007) | (~n5440_1 & (Ng853 | ~Ng1007)); + assign n3004_1 = ~n6783; + assign n6785 = (\[1594] & ~n5440_1) | (~Ng1006 & (~\[1594] | ~n5440_1)); + assign n2999 = ~n6785; + assign n6787_1 = (~\[1612] & ~Ng1005) | (~n5440_1 & (\[1612] | ~Ng1005)); + assign n2994_1 = ~n6787_1; + assign n6789 = (~Ng853 & ~Ng320) | (~n5437 & (Ng853 | ~Ng320)); + assign n1498 = ~n6789; + assign n6791 = (\[1594] & ~n5437) | (~Ng319 & (~\[1594] | ~n5437)); + assign n1493 = ~n6791; + assign n6793 = (~\[1612] & ~Ng318) | (~n5437 & (\[1612] | ~Ng318)); + assign n1488_1 = ~n6793; + assign n6795 = (n5865 & n8585) | (n5929 & (~n5865 | n8585)); + assign n6796 = (Ng853 & ~n6795) | (~Ng2339 & (~Ng853 | ~n6795)); + assign n5730 = ~n6796; + assign n6798 = (\[1594] & ~n6795) | (~Ng2336 & (~\[1594] | ~n6795)); + assign n5725 = ~n6798; + assign n6800 = (\[1612] & ~n6795) | (~Ng2333 & (~\[1612] | ~n6795)); + assign n5720 = ~n6800; + assign n6802_1 = (~Ng853 & ~Ng2330) | (n6382 & (Ng853 | ~Ng2330)); + assign n5700 = ~n6802_1; + assign n6804 = (~\[1594] & ~Ng2327) | (n6382 & (\[1594] | ~Ng2327)); + assign n5695 = ~n6804; + assign n6806 = (~\[1612] & ~Ng2324) | (n6382 & (\[1612] | ~Ng2324)); + assign n5690 = ~n6806; + assign n6808 = (n5865 & n8586) | (n5930 & (~n5865 | n8586)); + assign n6809 = (Ng853 & ~n6808) | (~Ng2294 & (~Ng853 | ~n6808)); + assign n5715 = ~n6809; + assign n6811 = (\[1594] & ~n6808) | (~Ng2291 & (~\[1594] | ~n6808)); + assign n5710 = ~n6811; + assign n6813 = (\[1612] & ~n6808) | (~Ng2288 & (~\[1612] | ~n6808)); + assign n5705 = ~n6813; + assign n6815 = (n5865 & n8588) | (n5931 & (~n5865 | n8588)); + assign n6816 = (Ng853 & ~n6815) | (~Ng2285 & (~Ng853 | ~n6815)); + assign n5685 = ~n6816; + assign n6818 = (\[1594] & ~n6815) | (~Ng2282 & (~\[1594] | ~n6815)); + assign n5680 = ~n6818; + assign n6820 = (\[1612] & ~n6815) | (~Ng2279 & (~\[1612] | ~n6815)); + assign n5675 = ~n6820; + assign n6822_1 = (n5865 & n6580) | (n5932 & (~n5865 | n6580)); + assign n6823 = (Ng853 & ~n6822_1) | (~Ng2267 & (~Ng853 | ~n6822_1)); + assign n5625 = ~n6823; + assign n6825 = (\[1594] & ~n6822_1) | (~Ng2264 & (~\[1594] | ~n6822_1)); + assign n5620 = ~n6825; + assign n6827_1 = (\[1612] & ~n6822_1) | (~Ng2261 & (~\[1612] | ~n6822_1)); + assign n5615 = ~n6827_1; + assign n6829 = (n5885 & n8589) | (n5936 & (~n5885 | n8589)); + assign n6830 = (Ng853 & ~n6829) | (~Ng1645 & (~Ng853 | ~n6829)); + assign n4236_1 = ~n6830; + assign n6832_1 = (\[1594] & ~n6829) | (~Ng1642 & (~\[1594] | ~n6829)); + assign n4231 = ~n6832_1; + assign n6834 = (\[1612] & ~n6829) | (~Ng1639 & (~\[1612] | ~n6829)); + assign n4226 = ~n6834; + assign n6836 = (~Ng853 & ~Ng1636) | (n6384 & (Ng853 | ~Ng1636)); + assign n4206 = ~n6836; + assign n6838 = (~\[1594] & ~Ng1633) | (n6384 & (\[1594] | ~Ng1633)); + assign n4201 = ~n6838; + assign n6840 = (~\[1612] & ~Ng1630) | (n6384 & (\[1612] | ~Ng1630)); + assign n4196 = ~n6840; + assign n6842_1 = (n5885 & n8590) | (n5937 & (~n5885 | n8590)); + assign n6843 = (Ng853 & ~n6842_1) | (~Ng1600 & (~Ng853 | ~n6842_1)); + assign n4221 = ~n6843; + assign n6845 = (\[1594] & ~n6842_1) | (~Ng1597 & (~\[1594] | ~n6842_1)); + assign n4216 = ~n6845; + assign n6847_1 = (\[1612] & ~n6842_1) | (~Ng1594 & (~\[1612] | ~n6842_1)); + assign n4211 = ~n6847_1; + assign n6849 = (n5885 & n8592) | (n5938_1 & (~n5885 | n8592)); + assign n6850 = (Ng853 & ~n6849) | (~Ng1591 & (~Ng853 | ~n6849)); + assign n4191_1 = ~n6850; + assign n6852_1 = (\[1594] & ~n6849) | (~Ng1588 & (~\[1594] | ~n6849)); + assign n4186 = ~n6852_1; + assign n6854 = (\[1612] & ~n6849) | (~Ng1585 & (~\[1612] | ~n6849)); + assign n4181_1 = ~n6854; + assign n6856 = (n5885 & n6581) | (n5939 & (~n5885 | n6581)); + assign n6857_1 = (Ng853 & ~n6856) | (~Ng1573 & (~Ng853 | ~n6856)); + assign n4131 = ~n6857_1; + assign n6859 = (\[1594] & ~n6856) | (~Ng1570 & (~\[1594] | ~n6856)); + assign n4126 = ~n6859; + assign n6861 = (\[1612] & ~n6856) | (~Ng1567 & (~\[1612] | ~n6856)); + assign n4121 = ~n6861; + assign n6863 = (n5905 & n8593) | (n5943_1 & (~n5905 | n8593)); + assign n6864 = (Ng853 & ~n6863) | (~Ng951 & (~Ng853 | ~n6863)); + assign n2729_1 = ~n6864; + assign n6866 = (\[1594] & ~n6863) | (~Ng948 & (~\[1594] | ~n6863)); + assign n2724_1 = ~n6866; + assign n6868 = (\[1612] & ~n6863) | (~Ng945 & (~\[1612] | ~n6863)); + assign n2719 = ~n6868; + assign n6870 = (~Ng853 & ~Ng942) | (n6386 & (Ng853 | ~Ng942)); + assign n2699_1 = ~n6870; + assign n6872_1 = (~\[1594] & ~Ng939) | (n6386 & (\[1594] | ~Ng939)); + assign n2694_1 = ~n6872_1; + assign n6874 = (~\[1612] & ~Ng936) | (n6386 & (\[1612] | ~Ng936)); + assign n2689 = ~n6874; + assign n6876 = (n5905 & n8594) | (n5944 & (~n5905 | n8594)); + assign n6877_1 = (Ng853 & ~n6876) | (~Ng906 & (~Ng853 | ~n6876)); + assign n2714_1 = ~n6877_1; + assign n6879 = (\[1594] & ~n6876) | (~Ng903 & (~\[1594] | ~n6876)); + assign n2709 = ~n6879; + assign n6881 = (\[1612] & ~n6876) | (~Ng900 & (~\[1612] | ~n6876)); + assign n2704_1 = ~n6881; + assign n6883 = (n5905 & n8596) | (n5945 & (~n5905 | n8596)); + assign n6884 = (Ng853 & ~n6883) | (~Ng897 & (~Ng853 | ~n6883)); + assign n2684 = ~n6884; + assign n6886 = (\[1594] & ~n6883) | (~Ng894 & (~\[1594] | ~n6883)); + assign n2679 = ~n6886; + assign n6888 = (\[1612] & ~n6883) | (~Ng891 & (~\[1612] | ~n6883)); + assign n2674 = ~n6888; + assign n6890 = (n5905 & n6582) | (n5946 & (~n5905 | n6582)); + assign n6891 = (Ng853 & ~n6890) | (~Ng879 & (~Ng853 | ~n6890)); + assign n2624 = ~n6891; + assign n6893 = (\[1594] & ~n6890) | (~Ng876 & (~\[1594] | ~n6890)); + assign n2619_1 = ~n6893; + assign n6895 = (\[1612] & ~n6890) | (~Ng873 & (~\[1612] | ~n6890)); + assign n2614 = ~n6895; + assign n6897_1 = (n5925 & n8597) | (n5950 & (~n5925 | n8597)); + assign n6898 = (Ng853 & ~n6897_1) | (~Ng264 & (~Ng853 | ~n6897_1)); + assign n1223_1 = ~n6898; + assign n6900 = (\[1594] & ~n6897_1) | (~Ng261 & (~\[1594] | ~n6897_1)); + assign n1218_1 = ~n6900; + assign n6902_1 = (\[1612] & ~n6897_1) | (~Ng258 & (~\[1612] | ~n6897_1)); + assign n1213_1 = ~n6902_1; + assign n6904 = (~Ng853 & ~Ng255) | (n6388 & (Ng853 | ~Ng255)); + assign n1193_1 = ~n6904; + assign n6906 = (~\[1594] & ~Ng252) | (n6388 & (\[1594] | ~Ng252)); + assign n1188_1 = ~n6906; + assign n6908 = (~\[1612] & ~Ng249) | (n6388 & (\[1612] | ~Ng249)); + assign n1183_1 = ~n6908; + assign n6910 = (n5925 & n8598) | (n5951 & (~n5925 | n8598)); + assign n6911 = (Ng853 & ~n6910) | (~Ng219 & (~Ng853 | ~n6910)); + assign n1208_1 = ~n6911; + assign n6913 = (\[1594] & ~n6910) | (~Ng216 & (~\[1594] | ~n6910)); + assign n1203_1 = ~n6913; + assign n6915 = (\[1612] & ~n6910) | (~Ng213 & (~\[1612] | ~n6910)); + assign n1198_1 = ~n6915; + assign n6917_1 = (n5925 & n8600) | (n5952 & (~n5925 | n8600)); + assign n6918 = (Ng853 & ~n6917_1) | (~Ng210 & (~Ng853 | ~n6917_1)); + assign n1178 = ~n6918; + assign n6920 = (\[1594] & ~n6917_1) | (~Ng207 & (~\[1594] | ~n6917_1)); + assign n1173_1 = ~n6920; + assign n6922_1 = (\[1612] & ~n6917_1) | (~Ng204 & (~\[1612] | ~n6917_1)); + assign n1168_1 = ~n6922_1; + assign n6924 = (n5925 & n6583) | (n5953_1 & (~n5925 | n6583)); + assign n6925 = (Ng853 & ~n6924) | (~Ng192 & (~Ng853 | ~n6924)); + assign n1118_1 = ~n6925; + assign n6927 = (\[1594] & ~n6924) | (~Ng189 & (~\[1594] | ~n6924)); + assign n1113_1 = ~n6927; + assign n6929 = (\[1612] & ~n6924) | (~Ng186 & (~\[1612] | ~n6924)); + assign n1108 = ~n6929; + assign n5077 = (Ng1886 & Ng1887) | (n8605 & (~Ng1886 | Ng1887)); + assign n6932 = (Ng2580 & ~Ng2581) | (n8606 & (~Ng2580 | ~Ng2581)); + assign n6584 = ~n6932; + assign n6934 = n8607 & (\[1594] | ~Ng305 | ~Ng299); + assign n1618_1 = ~n6934; + assign n6936_1 = (~Ng986 & Ng985) | (n8608 & (Ng986 | Ng985)); + assign n3124_1 = ~n6936_1; + assign n6938 = (~Ng1680 & Ng1679) | (n8609 & (Ng1680 | Ng1679)); + assign n4631 = ~n6938; + assign n6940 = (~Ng2374 & Ng2373) | (n8610 & (Ng2374 | Ng2373)); + assign n6138 = ~n6940; + assign n6942 = (Ng1315 & n6602_1) | (~Ng3105 & (~Ng1315 | n6602_1)); + assign n769_1 = ~n6942; + assign n6944 = (\[1603] & n6602_1) | (~Ng3104 & (~\[1603] | n6602_1)); + assign n764_1 = ~n6944; + assign n6946_1 = (\[1605] & n6602_1) | (~Ng3103 & (~\[1605] | n6602_1)); + assign n759_1 = ~n6946_1; + assign n6948 = (~n4932 & ~n5528) | (~n4972 & (n4932 | ~n5528)); + assign n6949 = (~n5058_1 & (n4712_1 | n8451)) | (~n4712_1 & n8451); + assign n6950 = (~n5058_1 & (n4734 | n8451)) | (~n4734 & n8451); + assign n6951_1 = (~n5058_1 & (n4798 | n8451)) | (~n4798 & n8451); + assign n6952 = (~n4764 & ~n5528) | (~n4972 & (n4764 | ~n5528)); + assign n6953 = (Ng853 & n8614) | (~Ng2389 & (~Ng853 | n8614)); + assign n5988 = ~n6953; + assign n6955 = (\[1594] & n8614) | (~Ng2388 & (~\[1594] | n8614)); + assign n5983 = ~n6955; + assign n6957 = (\[1612] & n8614) | (~Ng2387 & (~\[1612] | n8614)); + assign n5978 = ~n6957; + assign n6959 = (Ng853 & n8615) | (~Ng1695 & (~Ng853 | n8615)); + assign n4481 = ~n6959; + assign n6961_1 = (\[1594] & n8615) | (~Ng1694 & (~\[1594] | n8615)); + assign n4476 = ~n6961_1; + assign n6963 = (\[1612] & n8615) | (~Ng1693 & (~\[1612] | n8615)); + assign n4471 = ~n6963; + assign n6965 = (Ng853 & n8616) | (~Ng1001 & (~Ng853 | n8616)); + assign n2974_1 = ~n6965; + assign n6967 = (\[1594] & n8616) | (~Ng1000 & (~\[1594] | n8616)); + assign n2969_1 = ~n6967; + assign n6969 = (\[1612] & n8616) | (~Ng999 & (~\[1612] | n8616)); + assign n2964_1 = ~n6969; + assign n6971_1 = (Ng853 & n8617) | (~Ng314 & (~Ng853 | n8617)); + assign n1468_1 = ~n6971_1; + assign n6973 = (\[1594] & n8617) | (~Ng313 & (~\[1594] | n8617)); + assign n1463_1 = ~n6973; + assign n6975 = (\[1612] & n8617) | (~Ng312 & (~\[1612] | n8617)); + assign n1458_1 = ~n6975; + assign n6977 = (Ng3147 & n6282) | (~n6131 & (~Ng3147 | n6282)); + assign n6978 = (~n4912 & ~n5508) | (~n4964 & (n4912 | ~n5508)); + assign n6979 = (~n5054 & (n4688_1 | n8450)) | (~n4688_1 & n8450); + assign n6980 = (~n5054 & (n4704_1 | n8450)) | (~n4704_1 & n8450); + assign n6981_1 = (~n5054 & (n4756_1 | n8450)) | (~n4756_1 & n8450); + assign n6982 = (~n4728_1 & ~n5508) | (~n4964 & (n4728_1 | ~n5508)); + assign n6983 = (Ng853 & n8621) | (~Ng2498 & (~Ng853 | n8621)); + assign n5913 = ~n6983; + assign n6985 = (\[1594] & n8621) | (~Ng2495 & (~\[1594] | n8621)); + assign n5908 = ~n6985; + assign n6987 = (\[1612] & n8621) | (~Ng2492 & (~\[1612] | n8621)); + assign n5903 = ~n6987; + assign n6989 = (~Ng2396 & ~n8623) | (~n5991 & (~Ng2396 | n8623)); + assign n6033 = ~n6989; + assign n6991_1 = (~n5991 & n8624) | (~Ng2398 & (~n5991 | ~n8624)); + assign n6028 = ~n6991_1; + assign n6993 = (~Ng2397 & ~n8625) | (~n5991 & (~Ng2397 | n8625)); + assign n6023 = ~n6993; + assign n6995 = (Ng853 & n8626) | (~Ng1804 & (~Ng853 | n8626)); + assign n4406 = ~n6995; + assign n6997 = (\[1594] & n8626) | (~Ng1801 & (~\[1594] | n8626)); + assign n4401 = ~n6997; + assign n6999 = (\[1612] & n8626) | (~Ng1798 & (~\[1612] | n8626)); + assign n4396 = ~n6999; + assign n7001_1 = (~Ng1702 & ~n8628) | (~n5999 & (~Ng1702 | n8628)); + assign n4526 = ~n7001_1; + assign n7003 = (~n5999 & n8629) | (~Ng1704 & (~n5999 | ~n8629)); + assign n4521 = ~n7003; + assign n7005 = (~Ng1703 & ~n8630) | (~n5999 & (~Ng1703 | n8630)); + assign n4516 = ~n7005; + assign n7007 = (Ng853 & n8631) | (~Ng1110 & (~Ng853 | n8631)); + assign n2899 = ~n7007; + assign n7009 = (\[1594] & n8631) | (~Ng1107 & (~\[1594] | n8631)); + assign n2894 = ~n7009; + assign n7011_1 = (\[1612] & n8631) | (~Ng1104 & (~\[1612] | n8631)); + assign n2889 = ~n7011_1; + assign n7013 = (~Ng1008 & ~n8633) | (~n6007 & (~Ng1008 | n8633)); + assign n3019_1 = ~n7013; + assign n7015 = (~n6007 & n8634) | (~Ng1010 & (~n6007 | ~n8634)); + assign n3014 = ~n7015; + assign n7017 = (~Ng1009 & ~n8635) | (~n6007 & (~Ng1009 | n8635)); + assign n3009_1 = ~n7017; + assign n7019 = (Ng853 & n8636) | (~Ng423 & (~Ng853 | n8636)); + assign n1393 = ~n7019; + assign n7021_1 = (\[1594] & n8636) | (~Ng420 & (~\[1594] | n8636)); + assign n1388 = ~n7021_1; + assign n7023 = (\[1612] & n8636) | (~Ng417 & (~\[1612] | n8636)); + assign n1383 = ~n7023; + assign n7025 = (~Ng321 & ~n8638) | (~n6015 & (~Ng321 | n8638)); + assign n1513_1 = ~n7025; + assign n7027 = (~n6015 & n8639) | (~Ng323 & (~n6015 | ~n8639)); + assign n1508 = ~n7027; + assign n7029 = (~Ng322 & ~n8640) | (~n6015 & (~Ng322 | n8640)); + assign n1503 = ~n7029; + assign n7031_1 = (Ng853 & n8642) | (~Ng2489 & (~Ng853 | n8642)); + assign n5898 = ~n7031_1; + assign n7033 = (\[1594] & n8642) | (~Ng2486 & (~\[1594] | n8642)); + assign n5893 = ~n7033; + assign n7035 = (\[1612] & n8642) | (~Ng2483 & (~\[1612] | n8642)); + assign n5888 = ~n7035; + assign n7037 = (Ng853 & n8644) | (~Ng1795 & (~Ng853 | n8644)); + assign n4391 = ~n7037; + assign n7039 = (\[1594] & n8644) | (~Ng1792 & (~\[1594] | n8644)); + assign n4386 = ~n7039; + assign n7041_1 = (\[1612] & n8644) | (~Ng1789 & (~\[1612] | n8644)); + assign n4381 = ~n7041_1; + assign n7043 = (Ng853 & n8646) | (~Ng1101 & (~Ng853 | n8646)); + assign n2884_1 = ~n7043; + assign n7045 = (\[1594] & n8646) | (~Ng1098 & (~\[1594] | n8646)); + assign n2879_1 = ~n7045; + assign n7047 = (\[1612] & n8646) | (~Ng1095 & (~\[1612] | n8646)); + assign n2874_1 = ~n7047; + assign n7049 = (Ng853 & n8648) | (~Ng414 & (~Ng853 | n8648)); + assign n1378_1 = ~n7049; + assign n7051_1 = (\[1594] & n8648) | (~Ng411 & (~\[1594] | n8648)); + assign n1373_1 = ~n7051_1; + assign n7053 = (\[1612] & n8648) | (~Ng408 & (~\[1612] | n8648)); + assign n1368 = ~n7053; + assign n7055 = (Ng1315 & n6601) | (~Ng3102 & (~Ng1315 | n6601)); + assign n754_1 = ~n7055; + assign n7057 = (\[1603] & n6601) | (~Ng3101 & (~\[1603] | n6601)); + assign n749_1 = ~n7057; + assign n7059 = (\[1605] & n6601) | (~Ng3100 & (~\[1605] | n6601)); + assign n744_1 = ~n7059; + assign n7061_1 = n4571 & (~n6056 | (~n4567 & ~n6053_1)); + assign n7062 = (~n6061 & n6064) | (n5084 & (~n6061 | ~n6064)); + assign n7063 = (Ng1315 & n8650) | (~Ng2694 & (~Ng1315 | n8650)); + assign n6540 = ~n7063; + assign n7065 = (\[1603] & n8650) | (~Ng2691 & (~\[1603] | n8650)); + assign n6535 = ~n7065; + assign n7067 = (\[1605] & n8650) | (~Ng2688 & (~\[1605] | n8650)); + assign n6530 = ~n7067; + assign n7069 = n5084 | n6064; + assign n7070 = n6061 & n7069 & (~n5084 | n6554); + assign n7071_1 = (Ng1315 & n8651) | (~Ng2685 & (~Ng1315 | n8651)); + assign n6555 = ~n7071_1; + assign n7073 = (\[1603] & n8651) | (~Ng2682 & (~\[1603] | n8651)); + assign n6550 = ~n7073; + assign n7075 = (\[1605] & n8651) | (~Ng2679 & (~\[1605] | n8651)); + assign n6545 = ~n7075; + assign n7077 = n4565 & (~n6078 | (~n4559_1 & ~n6075_1)); + assign n7078 = (~n6083 & n6086) | (n5081 & (~n6083 | ~n6086)); + assign n7079 = (Ng1315 & n8653) | (~Ng2000 & (~Ng1315 | n8653)); + assign n5033 = ~n7079; + assign n7081_1 = (\[1603] & n8653) | (~Ng1997 & (~\[1603] | n8653)); + assign n5028 = ~n7081_1; + assign n7083 = (\[1605] & n8653) | (~Ng1994 & (~\[1605] | n8653)); + assign n5023 = ~n7083; + assign n7085 = n5081 | n6086; + assign n7086_1 = n6083 & n7085 & (~n5081 | n6559); + assign n7087 = (Ng1315 & n8654) | (~Ng1991 & (~Ng1315 | n8654)); + assign n5048 = ~n7087; + assign n7089 = (\[1603] & n8654) | (~Ng1988 & (~\[1603] | n8654)); + assign n5043 = ~n7089; + assign n7091_1 = (\[1605] & n8654) | (~Ng1985 & (~\[1605] | n8654)); + assign n5038 = ~n7091_1; + assign n7093 = n4557 & (~n6100 | (~n4551 & ~n6097)); + assign n7094 = (~n6105 & n6108) | (n5078 & (~n6105 | ~n6108)); + assign n7095 = (Ng1315 & n8656) | (~Ng1306 & (~Ng1315 | n8656)); + assign n3526_1 = ~n7095; + assign n7097 = (\[1603] & n8656) | (~Ng1303 & (~\[1603] | n8656)); + assign n3521_1 = ~n7097; + assign n7099 = (\[1605] & n8656) | (~Ng1300 & (~\[1605] | n8656)); + assign n3516_1 = ~n7099; + assign n7101_1 = n5078 | n6108; + assign n7102 = n6105 & n7101_1 & (~n5078 | n6563); + assign n7103 = (Ng1315 & n8657) | (~Ng1297 & (~Ng1315 | n8657)); + assign n3541_1 = ~n7103; + assign n7105 = (\[1603] & n8657) | (~Ng1294 & (~\[1603] | n8657)); + assign n3536_1 = ~n7105; + assign n7107 = (\[1605] & n8657) | (~Ng1291 & (~\[1605] | n8657)); + assign n3531_1 = ~n7107; + assign n7109 = n4549 & (~n6122 | (~n4545 & ~n6119)); + assign n7110 = (~n6127 & n6130) | (n5075 & (~n6127 | ~n6130)); + assign n7111_1 = (Ng1315 & n8659) | (~Ng620 & (~Ng1315 | n8659)); + assign n2020_1 = ~n7111_1; + assign n7113 = (\[1603] & n8659) | (~Ng617 & (~\[1603] | n8659)); + assign n2015_1 = ~n7113; + assign n7115 = (\[1605] & n8659) | (~Ng614 & (~\[1605] | n8659)); + assign n2010 = ~n7115; + assign n7117 = n5075 | n6130; + assign n7118 = n6127 & n7117 & (~n5075 | n6567); + assign n7119 = (Ng1315 & n8660) | (~Ng611 & (~Ng1315 | n8660)); + assign n2035_1 = ~n7119; + assign n7121_1 = (\[1603] & n8660) | (~Ng608 & (~\[1603] | n8660)); + assign n2030 = ~n7121_1; + assign n7123 = (\[1605] & n8660) | (~Ng605 & (~\[1605] | n8660)); + assign n2025_1 = ~n7123; + assign n7125 = (~n8665 & n8666) | (~Ng2658 & (n8665 | n8666)); + assign n6495 = ~n7125; + assign n7127 = (n8666 & ~n8667) | (~Ng2660 & (n8666 | n8667)); + assign n6490 = ~n7127; + assign n7129 = (n8666 & ~n8668) | (~Ng2659 & (n8666 | n8668)); + assign n6485 = ~n7129; + assign n7131_1 = (n6552 & ~n8669) | (n5018_1 & (n6552 | n8669)); + assign n7132 = (~Ng2655 & n8665) | (~n7131_1 & (~Ng2655 | ~n8665)); + assign n6480 = ~n7132; + assign n7134 = (~n7131_1 & ~n8667) | (~Ng2657 & (~n7131_1 | n8667)); + assign n6475 = ~n7134; + assign n7136_1 = (~Ng2656 & n8668) | (~n7131_1 & (~Ng2656 | ~n8668)); + assign n6470 = ~n7136_1; + assign n7138 = (~n5028_1 & n8669) | (n5018_1 & (n5028_1 | n8669)); + assign n7139 = (~Ng2652 & n8665) | (~n7138 & (~Ng2652 | ~n8665)); + assign n6465 = ~n7139; + assign n7141_1 = (~n7138 & ~n8667) | (~Ng2654 & (~n7138 | n8667)); + assign n6460 = ~n7141_1; + assign n7143 = (~Ng2653 & n8668) | (~n7138 & (~Ng2653 | ~n8668)); + assign n6455 = ~n7143; + assign n7145 = (~Ng2649 & n8665) | (~n6179_1 & (~Ng2649 | ~n8665)); + assign n6450 = ~n7145; + assign n7147 = (~n6179_1 & ~n8667) | (~Ng2651 & (~n6179_1 | n8667)); + assign n6445 = ~n7147; + assign n7149 = (~Ng2650 & n8668) | (~n6179_1 & (~Ng2650 | ~n8668)); + assign n6440 = ~n7149; + assign n7151_1 = (n8671 & n8672) | (~Ng11589 & (~n8671 | n8672)); + assign n5883 = ~n7151_1; + assign n7153 = (n8672 & n8673) | (~Ng11588 & (n8672 | ~n8673)); + assign n5878 = ~n7153; + assign n7155 = (n8672 & n8674) | (~Ng11587 & (n8672 | ~n8674)); + assign n5873 = ~n7155; + assign n7157 = (n4906 | ~n6389) & ~n8764; + assign n7158 = (~Ng11586 & ~n8671) | (~n7157 & (~Ng11586 | n8671)); + assign n5868 = ~n7158; + assign n7160_1 = (~n7157 & n8673) | (~Ng11585 & (~n7157 | ~n8673)); + assign n5863 = ~n7160_1; + assign n7162 = (~Ng11584 & ~n8674) | (~n7157 & (~Ng11584 | n8674)); + assign n5858 = ~n7162; + assign n7164 = (~n4926 & n6389) | (n4906 & (n4926 | n6389)); + assign n7165 = (~Ng11583 & ~n8671) | (~n7164 & (~Ng11583 | n8671)); + assign n5853 = ~n7165; + assign n7167_1 = (~n7164 & n8673) | (~Ng11582 & (~n7164 | ~n8673)); + assign n5848 = ~n7167_1; + assign n7169 = (~Ng11581 & ~n8674) | (~n7164 & (~Ng11581 | n8674)); + assign n5843 = ~n7169; + assign n7171 = (~Ng11580 & ~n8671) | (~n6181 & (~Ng11580 | n8671)); + assign n5838 = ~n7171; + assign n7173 = (~n6181 & n8673) | (~Ng11579 & (~n6181 | ~n8673)); + assign n5833 = ~n7173; + assign n7175 = (~Ng11578 & ~n8674) | (~n6181 & (~Ng11578 | n8674)); + assign n5828 = ~n7175; + assign n7177 = (~n8676 & n8677) | (~Ng1964 & (n8676 | n8677)); + assign n4988 = ~n7177; + assign n7179 = (n8677 & ~n8678) | (~Ng1966 & (n8677 | n8678)); + assign n4983 = ~n7179; + assign n7181 = (n8677 & ~n8679) | (~Ng1965 & (n8677 | n8679)); + assign n4978 = ~n7181; + assign n7183 = (n6557 & ~n8680) | (n5006 & (n6557 | n8680)); + assign n7184_1 = (~Ng1961 & n8676) | (~n7183 & (~Ng1961 | ~n8676)); + assign n4973 = ~n7184_1; + assign n7186 = (~n7183 & ~n8678) | (~Ng1963 & (~n7183 | n8678)); + assign n4968 = ~n7186; + assign n7188_1 = (~Ng1962 & n8679) | (~n7183 & (~Ng1962 | ~n8679)); + assign n4963 = ~n7188_1; + assign n7190 = (~n5016 & n8680) | (n5006 & (n5016 | n8680)); + assign n7191 = (~Ng1958 & n8676) | (~n7190 & (~Ng1958 | ~n8676)); + assign n4958 = ~n7191; + assign n7193 = (~n7190 & ~n8678) | (~Ng1960 & (~n7190 | n8678)); + assign n4953 = ~n7193; + assign n7195 = (~Ng1959 & n8679) | (~n7190 & (~Ng1959 | ~n8679)); + assign n4948 = ~n7195; + assign n7197 = (~Ng1955 & n8676) | (~n6184 & (~Ng1955 | ~n8676)); + assign n4943 = ~n7197; + assign n7199 = (~n6184 & ~n8678) | (~Ng1957 & (~n6184 | n8678)); + assign n4938 = ~n7199; + assign n7201 = (~Ng1956 & n8679) | (~n6184 & (~Ng1956 | ~n8679)); + assign n4933 = ~n7201; + assign n7203 = (n8682 & n8683) | (~Ng11562 & (~n8682 | n8683)); + assign n4376 = ~n7203; + assign n7205 = (n8683 & n8684) | (~Ng11561 & (n8683 | ~n8684)); + assign n4371 = ~n7205; + assign n7207 = (n8683 & n8685) | (~Ng11560 & (n8683 | ~n8685)); + assign n4366 = ~n7207; + assign n7209_1 = (n4868 | ~n6390) & ~n8765; + assign n7210 = (~Ng11559 & ~n8682) | (~n7209_1 & (~Ng11559 | n8682)); + assign n4361 = ~n7210; + assign n7212 = (~n7209_1 & n8684) | (~Ng11558 & (~n7209_1 | ~n8684)); + assign n4356 = ~n7212; + assign n7214 = (~Ng11557 & ~n8685) | (~n7209_1 & (~Ng11557 | n8685)); + assign n4351 = ~n7214; + assign n7216 = (~n4896 & n6390) | (n4868 & (n4896 | n6390)); + assign n7217 = (~Ng11556 & ~n8682) | (~n7216 & (~Ng11556 | n8682)); + assign n4346 = ~n7217; + assign n7219 = (~n7216 & n8684) | (~Ng11555 & (~n7216 | ~n8684)); + assign n4341_1 = ~n7219; + assign n7221 = (~Ng11554 & ~n8685) | (~n7216 & (~Ng11554 | n8685)); + assign n4336_1 = ~n7221; + assign n7223 = (~Ng11553 & ~n8682) | (~n6186 & (~Ng11553 | n8682)); + assign n4331_1 = ~n7223; + assign n7225 = (~n6186 & n8684) | (~Ng11552 & (~n6186 | ~n8684)); + assign n4326 = ~n7225; + assign n7227 = (~Ng11551 & ~n8685) | (~n6186 & (~Ng11551 | n8685)); + assign n4321 = ~n7227; + assign n7229 = (~n8687 & n8688) | (~Ng1270 & (n8687 | n8688)); + assign n3481_1 = ~n7229; + assign n7231 = (n8688 & ~n8689) | (~Ng1272 & (n8688 | n8689)); + assign n3476_1 = ~n7231; + assign n7233 = (n8688 & ~n8690) | (~Ng1271 & (n8688 | n8690)); + assign n3471_1 = ~n7233; + assign n7235 = (n6561 & ~n8691) | (n4994 & (n6561 | n8691)); + assign n7236 = (~Ng1267 & n8687) | (~n7235 & (~Ng1267 | ~n8687)); + assign n3466_1 = ~n7236; + assign n7238_1 = (~n7235 & ~n8689) | (~Ng1269 & (~n7235 | n8689)); + assign n3461_1 = ~n7238_1; + assign n7240 = (~Ng1268 & n8690) | (~n7235 & (~Ng1268 | ~n8690)); + assign n3456_1 = ~n7240; + assign n7242_1 = (~n5004 & n8691) | (n4994 & (n5004 | n8691)); + assign n7243 = (~Ng1264 & n8687) | (~n7242_1 & (~Ng1264 | ~n8687)); + assign n3451_1 = ~n7243; + assign n7245 = (~n7242_1 & ~n8689) | (~Ng1266 & (~n7242_1 | n8689)); + assign n3446_1 = ~n7245; + assign n7247 = (~Ng1265 & n8690) | (~n7242_1 & (~Ng1265 | ~n8690)); + assign n3441_1 = ~n7247; + assign n7249 = (~Ng1261 & n8687) | (~n6189 & (~Ng1261 | ~n8687)); + assign n3436_1 = ~n7249; + assign n7251 = (~n6189 & ~n8689) | (~Ng1263 & (~n6189 | n8689)); + assign n3431_1 = ~n7251; + assign n7253 = (~Ng1262 & n8690) | (~n6189 & (~Ng1262 | ~n8690)); + assign n3426_1 = ~n7253; + assign n7255_1 = (n8693 & n8694) | (~Ng11535 & (~n8693 | n8694)); + assign n2869_1 = ~n7255_1; + assign n7257 = (n8694 & n8695) | (~Ng11534 & (n8694 | ~n8695)); + assign n2864_1 = ~n7257; + assign n7259 = (n8694 & n8696) | (~Ng11533 & (n8694 | ~n8696)); + assign n2859_1 = ~n7259; + assign n7261 = (n4826 | ~n6391_1) & ~n8766; + assign n7262 = (~Ng11532 & ~n8693) | (~n7261 & (~Ng11532 | n8693)); + assign n2854_1 = ~n7262; + assign n7264 = (~n7261 & n8695) | (~Ng11531 & (~n7261 | ~n8695)); + assign n2849_1 = ~n7264; + assign n7266 = (~Ng11530 & ~n8696) | (~n7261 & (~Ng11530 | n8696)); + assign n2844_1 = ~n7266; + assign n7268 = (~n4858 & n6391_1) | (n4826 & (n4858 | n6391_1)); + assign n7269 = (~Ng11529 & ~n8693) | (~n7268 & (~Ng11529 | n8693)); + assign n2839_1 = ~n7269; + assign n7271 = (~n7268 & n8695) | (~Ng11528 & (~n7268 | ~n8695)); + assign n2834_1 = ~n7271; + assign n7273 = (~Ng11527 & ~n8696) | (~n7268 & (~Ng11527 | n8696)); + assign n2829_1 = ~n7273; + assign n7275 = (~Ng11526 & ~n8693) | (~n6191_1 & (~Ng11526 | n8693)); + assign n2824_1 = ~n7275; + assign n7277 = (~n6191_1 & n8695) | (~Ng11525 & (~n6191_1 | ~n8695)); + assign n2819_1 = ~n7277; + assign n7279 = (~Ng11524 & ~n8696) | (~n6191_1 & (~Ng11524 | n8696)); + assign n2814_1 = ~n7279; + assign n7281 = (~n8698 & n8699) | (~Ng584 & (n8698 | n8699)); + assign n1975 = ~n7281; + assign n7283 = (n8699 & ~n8700) | (~Ng586 & (n8699 | n8700)); + assign n1970_1 = ~n7283; + assign n7285 = (n8699 & ~n8701) | (~Ng585 & (n8699 | n8701)); + assign n1965 = ~n7285; + assign n7287 = (n6565_1 & ~n8702) | (n4986 & (n6565_1 | n8702)); + assign n7288 = (~Ng581 & n8698) | (~n7287 & (~Ng581 | ~n8698)); + assign n1960_1 = ~n7288; + assign n7290 = (~n7287 & ~n8700) | (~Ng583 & (~n7287 | n8700)); + assign n1955 = ~n7290; + assign n7292 = (~Ng582 & n8701) | (~n7287 & (~Ng582 | ~n8701)); + assign n1950 = ~n7292; + assign n7294 = (~n4992 & n8702) | (n4986 & (n4992 | n8702)); + assign n7295 = (~Ng578 & n8698) | (~n7294 & (~Ng578 | ~n8698)); + assign n1945_1 = ~n7295; + assign n7297 = (~n7294 & ~n8700) | (~Ng580 & (~n7294 | n8700)); + assign n1940_1 = ~n7297; + assign n7299 = (~Ng579 & n8701) | (~n7294 & (~Ng579 | ~n8701)); + assign n1935_1 = ~n7299; + assign n7301 = (~Ng575 & n8698) | (~n6194 & (~Ng575 | ~n8698)); + assign n1930_1 = ~n7301; + assign n7303 = (~n6194 & ~n8700) | (~Ng577 & (~n6194 | n8700)); + assign n1925 = ~n7303; + assign n7305 = (~Ng576 & n8701) | (~n6194 & (~Ng576 | ~n8701)); + assign n1920_1 = ~n7305; + assign n7307 = (n8704 & n8705) | (~Ng11508 & (~n8704 | n8705)); + assign n1363_1 = ~n7307; + assign n7309 = (n8705 & n8706) | (~Ng11507 & (n8705 | ~n8706)); + assign n1358_1 = ~n7309; + assign n7311 = (n8705 & n8707) | (~Ng11506 & (n8705 | ~n8707)); + assign n1353 = ~n7311; + assign n7313 = (n4784 | ~n6392) & ~n8767; + assign n7314 = (~Ng11505 & ~n8704) | (~n7313 & (~Ng11505 | n8704)); + assign n1348 = ~n7314; + assign n7316 = (~n7313 & n8706) | (~Ng11504 & (~n7313 | ~n8706)); + assign n1343_1 = ~n7316; + assign n7318 = (~Ng11503 & ~n8707) | (~n7313 & (~Ng11503 | n8707)); + assign n1338_1 = ~n7318; + assign n7320 = (~n4816 & n6392) | (n4784 & (n4816 | n6392)); + assign n7321 = (~Ng11502 & ~n8704) | (~n7320 & (~Ng11502 | n8704)); + assign n1333_1 = ~n7321; + assign n7323 = (~n7320 & n8706) | (~Ng11501 & (~n7320 | ~n8706)); + assign n1328_1 = ~n7323; + assign n7325 = (~Ng11500 & ~n8707) | (~n7320 & (~Ng11500 | n8707)); + assign n1323_1 = ~n7325; + assign n7327 = (~Ng11499 & ~n8704) | (~n6196 & (~Ng11499 | n8704)); + assign n1318 = ~n7327; + assign n7329 = (~n6196 & n8706) | (~Ng11498 & (~n6196 | ~n8706)); + assign n1313 = ~n7329; + assign n7331 = (~Ng11497 & ~n8707) | (~n6196 & (~Ng11497 | n8707)); + assign n1308_1 = ~n7331; + assign n7333 = (Ng853 & n8709) | (~Ng2519 & (~Ng853 | n8709)); + assign n5958 = ~n7333; + assign n7335 = (\[1594] & n8709) | (~Ng2516 & (~\[1594] | n8709)); + assign n5953 = ~n7335; + assign n7337 = (\[1612] & n8709) | (~Ng2513 & (~\[1612] | n8709)); + assign n5948 = ~n7337; + assign n7339 = (Ng853 & n8710) | (~Ng2510 & (~Ng853 | n8710)); + assign n5943 = ~n7339; + assign n7341 = (\[1594] & n8710) | (~Ng2507 & (~\[1594] | n8710)); + assign n5938 = ~n7341; + assign n7343 = (\[1612] & n8710) | (~Ng2504 & (~\[1612] | n8710)); + assign n5933 = ~n7343; + assign n7345 = (Ng853 & n8711) | (~Ng1825 & (~Ng853 | n8711)); + assign n4451_1 = ~n7345; + assign n7347 = (\[1594] & n8711) | (~Ng1822 & (~\[1594] | n8711)); + assign n4446_1 = ~n7347; + assign n7349 = (\[1612] & n8711) | (~Ng1819 & (~\[1612] | n8711)); + assign n4441 = ~n7349; + assign n7351 = (Ng853 & n8712) | (~Ng1816 & (~Ng853 | n8712)); + assign n4436 = ~n7351; + assign n7353 = (\[1594] & n8712) | (~Ng1813 & (~\[1594] | n8712)); + assign n4431 = ~n7353; + assign n7355 = (\[1612] & n8712) | (~Ng1810 & (~\[1612] | n8712)); + assign n4426 = ~n7355; + assign n7357 = (Ng853 & n8713) | (~Ng1131 & (~Ng853 | n8713)); + assign n2944_1 = ~n7357; + assign n7359 = (\[1594] & n8713) | (~Ng1128 & (~\[1594] | n8713)); + assign n2939_1 = ~n7359; + assign n7361 = (\[1612] & n8713) | (~Ng1125 & (~\[1612] | n8713)); + assign n2934_1 = ~n7361; + assign n7363 = (Ng853 & n8714) | (~Ng1122 & (~Ng853 | n8714)); + assign n2929_1 = ~n7363; + assign n7365 = (\[1594] & n8714) | (~Ng1119 & (~\[1594] | n8714)); + assign n2924_1 = ~n7365; + assign n7367 = (\[1612] & n8714) | (~Ng1116 & (~\[1612] | n8714)); + assign n2919_1 = ~n7367; + assign n7369 = (Ng853 & n8715) | (~Ng444 & (~Ng853 | n8715)); + assign n1438_1 = ~n7369; + assign n7371 = (\[1594] & n8715) | (~Ng441 & (~\[1594] | n8715)); + assign n1433_1 = ~n7371; + assign n7373 = (\[1612] & n8715) | (~Ng438 & (~\[1612] | n8715)); + assign n1428_1 = ~n7373; + assign n7375 = (Ng853 & n8716) | (~Ng435 & (~Ng853 | n8716)); + assign n1423_1 = ~n7375; + assign n7377 = (\[1594] & n8716) | (~Ng432 & (~\[1594] | n8716)); + assign n1418_1 = ~n7377; + assign n7379 = (\[1612] & n8716) | (~Ng429 & (~\[1612] | n8716)); + assign n1413 = ~n7379; + assign n7381 = (Ng1315 & n8717) | (~Ng2571 & (~Ng1315 | n8717)); + assign n6570 = ~n7381; + assign n7383 = (\[1603] & n8717) | (~Ng2568 & (~\[1603] | n8717)); + assign n6565 = ~n7383; + assign n7385 = (\[1605] & n8717) | (~Ng2565 & (~\[1605] | n8717)); + assign n6560 = ~n7385; + assign n7387 = (~n8718 & n8719) | (~Ng2477 & (n8718 | n8719)); + assign n6048 = ~n7387; + assign n7389 = (n8719 & ~n8720) | (~Ng2479 & (n8719 | n8720)); + assign n6043 = ~n7389; + assign n7391 = (n8719 & ~n8721) | (~Ng2478 & (n8719 | n8721)); + assign n6038 = ~n7391; + assign n7393 = (Ng1315 & n8722) | (~Ng1877 & (~Ng1315 | n8722)); + assign n5063 = ~n7393; + assign n7395 = (\[1603] & n8722) | (~Ng1874 & (~\[1603] | n8722)); + assign n5058 = ~n7395; + assign n7397 = (\[1605] & n8722) | (~Ng1871 & (~\[1605] | n8722)); + assign n5053 = ~n7397; + assign n7399 = (~n8718 & n8723) | (~Ng1783 & (n8718 | n8723)); + assign n4541 = ~n7399; + assign n7401 = (~n8720 & n8723) | (~Ng1785 & (n8720 | n8723)); + assign n4536 = ~n7401; + assign n7403 = (~n8721 & n8723) | (~Ng1784 & (n8721 | n8723)); + assign n4531 = ~n7403; + assign n7405 = (Ng1315 & n8724) | (~Ng1183 & (~Ng1315 | n8724)); + assign n3556_1 = ~n7405; + assign n7407 = (\[1603] & n8724) | (~Ng1180 & (~\[1603] | n8724)); + assign n3551_1 = ~n7407; + assign n7409 = (\[1605] & n8724) | (~Ng1177 & (~\[1605] | n8724)); + assign n3546_1 = ~n7409; + assign n7411 = (~n8718 & n8725) | (~Ng1089 & (n8718 | n8725)); + assign n3034_1 = ~n7411; + assign n7413 = (~n8720 & n8725) | (~Ng1091 & (n8720 | n8725)); + assign n3029_1 = ~n7413; + assign n7415 = (~n8721 & n8725) | (~Ng1090 & (n8721 | n8725)); + assign n3024_1 = ~n7415; + assign n7417 = (Ng1315 & n8726) | (~Ng496 & (~Ng1315 | n8726)); + assign n2050_1 = ~n7417; + assign n7419 = (\[1603] & n8726) | (~Ng493 & (~\[1603] | n8726)); + assign n2045_1 = ~n7419; + assign n7421 = (\[1605] & n8726) | (~Ng490 & (~\[1605] | n8726)); + assign n2040 = ~n7421; + assign n7423 = (~n8718 & n8727) | (~Ng402 & (n8718 | n8727)); + assign n1528 = ~n7423; + assign n7425 = (~n8720 & n8727) | (~Ng404 & (n8720 | n8727)); + assign n1523_1 = ~n7425; + assign n7427 = (~n8721 & n8727) | (~Ng403 & (n8721 | n8727)); + assign n1518_1 = ~n7427; + assign n7429 = (Ng1315 & n6600) | (~Ng3099 & (~Ng1315 | n6600)); + assign n739_1 = ~n7429; + assign n7431 = (\[1603] & n6600) | (~Ng3098 & (~\[1603] | n6600)); + assign n734_1 = ~n7431; + assign n7433 = (\[1605] & n6600) | (~Ng3097 & (~\[1605] | n6600)); + assign n729 = ~n7433; + assign n7435 = (~n6234 & n8728) | (Pg3234 & (n6234 | n8728)); + assign n7106 = ~n7435; + assign n7437 = (~n5193 & ~Ng2808) | (~n5191 & (n5193 | ~Ng2808)); + assign n6892 = ~n7437; + assign n7439 = (~n5188 & ~Ng2810) | (~n5191 & (n5188 | ~Ng2810)); + assign n6887 = ~n7439; + assign n7441 = (~n5181 & ~Ng2809) | (~n5191 & (n5181 | ~Ng2809)); + assign n6882 = ~n7441; + assign n7443 = (~Ng2253 & n8729) | (n6149 & (~Ng2253 | ~n8729)); + assign n5610 = ~n7443; + assign n7445 = (n8730 & ~Ng2255) | (n6149 & (~n8730 | ~Ng2255)); + assign n5605 = ~n7445; + assign n7447 = (~Ng2254 & n8731) | (n6149 & (~Ng2254 | ~n8731)); + assign n5600 = ~n7447; + assign n7449 = (~Ng2250 & n8729) | (Ng2165 & (~Ng2250 | ~n8729)); + assign n5595 = ~n7449; + assign n7451 = (Ng2165 & ~n8730) | (~Ng2252 & (Ng2165 | n8730)); + assign n5590 = ~n7451; + assign n7453 = (~Ng2251 & n8731) | (Ng2165 & (~Ng2251 | ~n8731)); + assign n5585 = ~n7453; + assign n7455 = (~Ng2247 & n8729) | (Ng2170 & (~Ng2247 | ~n8729)); + assign n5580 = ~n7455; + assign n7457 = (Ng2170 & ~n8730) | (~Ng2249 & (Ng2170 | n8730)); + assign n5575 = ~n7457; + assign n7459 = (~Ng2248 & n8731) | (Ng2170 & (~Ng2248 | ~n8731)); + assign n5570 = ~n7459; + assign n7461 = (~n8729 & n8732) | (~Ng2244 & (n8729 | n8732)); + assign n5565 = ~n7461; + assign n7463 = (~n8730 & n8732) | (~Ng2246 & (n8730 | n8732)); + assign n5560 = ~n7463; + assign n7465 = (~n8731 & n8732) | (~Ng2245 & (n8731 | n8732)); + assign n5555 = ~n7465; + assign n7467 = (~n5186 & ~Ng2114) | (~n5184 & (n5186 | ~Ng2114)); + assign n5385 = ~n7467; + assign n7469 = (~n5178 & ~Ng2116) | (~n5184 & (n5178 | ~Ng2116)); + assign n5380 = ~n7469; + assign n7471 = (~n5171 & ~Ng2115) | (~n5184 & (n5171 | ~Ng2115)); + assign n5375 = ~n7471; + assign n7473 = (~Ng1559 & n8729) | (n6156 & (~Ng1559 | ~n8729)); + assign n4116_1 = ~n7473; + assign n7475 = (n8730 & ~Ng1561) | (n6156 & (~n8730 | ~Ng1561)); + assign n4111_1 = ~n7475; + assign n7477 = (~Ng1560 & n8731) | (n6156 & (~Ng1560 | ~n8731)); + assign n4106 = ~n7477; + assign n7479 = (~Ng1556 & n8729) | (Ng1471 & (~Ng1556 | ~n8729)); + assign n4101 = ~n7479; + assign n7481 = (Ng1471 & ~n8730) | (~Ng1558 & (Ng1471 | n8730)); + assign n4096_1 = ~n7481; + assign n7483 = (~Ng1557 & n8731) | (Ng1471 & (~Ng1557 | ~n8731)); + assign n4091 = ~n7483; + assign n7485 = (~Ng1553 & n8729) | (Ng1476 & (~Ng1553 | ~n8729)); + assign n4086_1 = ~n7485; + assign n7487 = (Ng1476 & ~n8730) | (~Ng1555 & (Ng1476 | n8730)); + assign n4081_1 = ~n7487; + assign n7489 = (~Ng1554 & n8731) | (Ng1476 & (~Ng1554 | ~n8731)); + assign n4076 = ~n7489; + assign n7491 = (~n8729 & n8733) | (~Ng1550 & (n8729 | n8733)); + assign n4071_1 = ~n7491; + assign n7493 = (~n8730 & n8733) | (~Ng1552 & (n8730 | n8733)); + assign n4066_1 = ~n7493; + assign n7495 = (~n8731 & n8733) | (~Ng1551 & (n8731 | n8733)); + assign n4061 = ~n7495; + assign n7497 = (~n5176 & ~Ng1420) | (~n5174 & (n5176 | ~Ng1420)); + assign n3891 = ~n7497; + assign n7499 = (~n5168 & ~Ng1422) | (~n5174 & (n5168 | ~Ng1422)); + assign n3886_1 = ~n7499; + assign n7501 = (~n5161 & ~Ng1421) | (~n5174 & (n5161 | ~Ng1421)); + assign n3881_1 = ~n7501; + assign n7503 = (~Ng865 & n8729) | (n6163_1 & (~Ng865 | ~n8729)); + assign n2609 = ~n7503; + assign n7505 = (n8730 & ~Ng867) | (n6163_1 & (~n8730 | ~Ng867)); + assign n2604 = ~n7505; + assign n7507 = (~Ng866 & n8731) | (n6163_1 & (~Ng866 | ~n8731)); + assign n2599_1 = ~n7507; + assign n7509 = (~Ng862 & n8729) | (Ng785 & (~Ng862 | ~n8729)); + assign n2594 = ~n7509; + assign n7511 = (Ng785 & ~n8730) | (~Ng864 & (Ng785 | n8730)); + assign n2589 = ~n7511; + assign n7513 = (~Ng863 & n8731) | (Ng785 & (~Ng863 | ~n8731)); + assign n2584_1 = ~n7513; + assign n7515 = (~Ng859 & n8729) | (Ng789 & (~Ng859 | ~n8729)); + assign n2579 = ~n7515; + assign n7517 = (Ng789 & ~n8730) | (~Ng861 & (Ng789 | n8730)); + assign n2574 = ~n7517; + assign n7519 = (~Ng860 & n8731) | (Ng789 & (~Ng860 | ~n8731)); + assign n2569 = ~n7519; + assign n7521 = (~n8729 & n8734) | (~Ng856 & (n8729 | n8734)); + assign n2564 = ~n7521; + assign n7523 = (~n8730 & n8734) | (~Ng858 & (n8730 | n8734)); + assign n2559 = ~n7523; + assign n7525 = (~n8731 & n8734) | (~Ng857 & (n8731 | n8734)); + assign n2554 = ~n7525; + assign n7527 = (~n5166 & ~Ng734) | (~n5164 & (n5166 | ~Ng734)); + assign n2372 = ~n7527; + assign n7529 = (~n5158 & ~Ng736) | (~n5164 & (n5158 | ~Ng736)); + assign n2367_1 = ~n7529; + assign n7531 = (~n5154 & ~Ng735) | (~n5164 & (n5154 | ~Ng735)); + assign n2362_1 = ~n7531; + assign n7533 = (~Ng177 & n8729) | (n6170 & (~Ng177 | ~n8729)); + assign n1103_1 = ~n7533; + assign n7535 = (n8730 & ~Ng179) | (n6170 & (~n8730 | ~Ng179)); + assign n1098_1 = ~n7535; + assign n7537 = (~Ng178 & n8731) | (n6170 & (~Ng178 | ~n8731)); + assign n1093_1 = ~n7537; + assign n7539 = (~Ng174 & n8729) | (Ng97 & (~Ng174 | ~n8729)); + assign n1088_1 = ~n7539; + assign n7541 = (Ng97 & ~n8730) | (~Ng176 & (Ng97 | n8730)); + assign n1083_1 = ~n7541; + assign n7543 = (~Ng175 & n8731) | (Ng97 & (~Ng175 | ~n8731)); + assign n1078_1 = ~n7543; + assign n7545 = (~Ng171 & n8729) | (Ng101 & (~Ng171 | ~n8729)); + assign n1073_1 = ~n7545; + assign n7547 = (~Ng173 & n8730) | (Ng101 & (~Ng173 | ~n8730)); + assign n1068_1 = ~n7547; + assign n7549 = (Ng101 & ~n8731) | (~Ng172 & (Ng101 | n8731)); + assign n1063 = ~n7549; + assign n7551 = (~n8729 & n8735) | (~Ng168 & (n8729 | n8735)); + assign n1058_1 = ~n7551; + assign n7553 = (~n8730 & n8735) | (~Ng170 & (n8730 | n8735)); + assign n1053 = ~n7553; + assign n7555 = (~n8731 & n8735) | (~Ng169 & (n8731 | n8735)); + assign n1048 = ~n7555; + assign n7557 = (Ng1315 & n8736) | (~Ng2676 & (~Ng1315 | n8736)); + assign n6525 = ~n7557; + assign n7559 = (\[1603] & n8736) | (~Ng2673 & (~\[1603] | n8736)); + assign n6520 = ~n7559; + assign n7561 = (\[1605] & n8736) | (~Ng2670 & (~\[1605] | n8736)); + assign n6515 = ~n7561; + assign n7563 = (Ng1315 & n8737) | (~Ng2667 & (~Ng1315 | n8737)); + assign n6510 = ~n7563; + assign n7565 = (\[1603] & n8737) | (~Ng2664 & (~\[1603] | n8737)); + assign n6505 = ~n7565; + assign n7567 = (\[1605] & n8737) | (~Ng2661 & (~\[1605] | n8737)); + assign n6500 = ~n7567; + assign n7569 = (~Pg3229 & ~Ng2380) | (Ng2366 & (Pg3229 | ~Ng2380)); + assign n6632 = ~n7569; + assign n7571 = (Ng2160 & ~n8738) | (n6242 & (~Ng2160 | ~n8738)); + assign n5765 = ~n7571; + assign n7573 = (Ng1315 & n8739) | (~Ng1982 & (~Ng1315 | n8739)); + assign n5018 = ~n7573; + assign n7575 = (\[1603] & n8739) | (~Ng1979 & (~\[1603] | n8739)); + assign n5013 = ~n7575; + assign n7577 = (\[1605] & n8739) | (~Ng1976 & (~\[1605] | n8739)); + assign n5008 = ~n7577; + assign n7579 = (Ng1315 & n8740) | (~Ng1973 & (~Ng1315 | n8740)); + assign n5003 = ~n7579; + assign n7581 = (\[1603] & n8740) | (~Ng1970 & (~\[1603] | n8740)); + assign n4998 = ~n7581; + assign n7583 = (\[1605] & n8740) | (~Ng1967 & (~\[1605] | n8740)); + assign n4993 = ~n7583; + assign n7585 = (~Pg3229 & ~Ng1686) | (Ng1672 & (Pg3229 | ~Ng1686)); + assign n5125 = ~n7585; + assign n7587 = (Ng1466 & ~n8738) | (n6242 & (~Ng1466 | ~n8738)); + assign n4271 = ~n7587; + assign n7589 = (Ng1315 & n8741) | (~Ng1288 & (~Ng1315 | n8741)); + assign n3511_1 = ~n7589; + assign n7591 = (\[1603] & n8741) | (~Ng1285 & (~\[1603] | n8741)); + assign n3506_1 = ~n7591; + assign n7593 = (\[1605] & n8741) | (~Ng1282 & (~\[1605] | n8741)); + assign n3501_1 = ~n7593; + assign n7595 = (Ng1315 & n8742) | (~Ng1279 & (~Ng1315 | n8742)); + assign n3496_1 = ~n7595; + assign n7597 = (\[1603] & n8742) | (~Ng1276 & (~\[1603] | n8742)); + assign n3491_1 = ~n7597; + assign n7599 = (\[1605] & n8742) | (~Ng1273 & (~\[1605] | n8742)); + assign n3486_1 = ~n7599; + assign n7601 = (~Pg3229 & ~Ng992) | (Ng978 & (Pg3229 | ~Ng992)); + assign n3618_1 = ~n7601; + assign n7603 = (Ng780 & ~n8738) | (n6242 & (~Ng780 | ~n8738)); + assign n2764_1 = ~n7603; + assign n7605 = (Ng1315 & n8743) | (~Ng602 & (~Ng1315 | n8743)); + assign n2005_1 = ~n7605; + assign n7607 = (\[1603] & n8743) | (~Ng599 & (~\[1603] | n8743)); + assign n2000_1 = ~n7607; + assign n7609 = (\[1605] & n8743) | (~Ng596 & (~\[1605] | n8743)); + assign n1995_1 = ~n7609; + assign n7611 = (Ng1315 & n8744) | (~Ng593 & (~Ng1315 | n8744)); + assign n1990_1 = ~n7611; + assign n7613 = (\[1603] & n8744) | (~Ng590 & (~\[1603] | n8744)); + assign n1985 = ~n7613; + assign n7615 = (\[1605] & n8744) | (~Ng587 & (~\[1605] | n8744)); + assign n1980 = ~n7615; + assign n7617 = (~Pg3229 & ~Ng305) | (Ng291 & (Pg3229 | ~Ng305)); + assign n2112 = ~n7617; + assign n7619 = (Ng92 & ~n8738) | (n6242 & (~Ng92 | ~n8738)); + assign n1258_1 = ~n7619; + assign n7621 = ~n8746 & (~Ng3147 | n6537 | ~Ng3097); + assign n7622 = (~\[1612] & ~Ng11593) | (n5137 & (\[1612] | ~Ng11593)); + assign n6341 = ~n7622; + assign n7624 = (~Ng853 & ~Ng2554) | (n5990 & (Ng853 | ~Ng2554)); + assign n6363 = ~n7624; + assign n7626 = (\[1594] & n5990) | (~Ng2553 & (~\[1594] | n5990)); + assign n6358 = ~n7626; + assign n7628 = (~\[1612] & ~Ng2552) | (n5990 & (\[1612] | ~Ng2552)); + assign n6353 = ~n7628; + assign n7630 = (~Ng853 & ~Ng11595) | (n6219_1 & (Ng853 | ~Ng11595)); + assign n6391 = ~n7630; + assign n7632 = (~\[1594] & ~Ng11594) | (n6219_1 & (\[1594] | ~Ng11594)); + assign n6387 = ~n7632; + assign n7634 = (~\[1612] & ~Ng11598) | (n6219_1 & (\[1612] | ~Ng11598)); + assign n6383 = ~n7634; + assign n7636 = (~Ng853 & ~Ng11597) | (n5137 & (Ng853 | ~Ng11597)); + assign n6349 = ~n7636; + assign n7638 = (~\[1594] & ~Ng11596) | (n5137 & (\[1594] | ~Ng11596)); + assign n6345 = ~n7638; + assign n7640 = (~\[1612] & ~Ng11566) | (n5135_1 & (\[1612] | ~Ng11566)); + assign n4834 = ~n7640; + assign n7642 = (~Ng853 & ~Ng1860) | (n5998_1 & (Ng853 | ~Ng1860)); + assign n4856 = ~n7642; + assign n7644 = (\[1594] & n5998_1) | (~Ng1859 & (~\[1594] | n5998_1)); + assign n4851 = ~n7644; + assign n7646 = (~\[1612] & ~Ng1858) | (n5998_1 & (\[1612] | ~Ng1858)); + assign n4846 = ~n7646; + assign n7648 = (~Ng853 & ~Ng11568) | (n6223_1 & (Ng853 | ~Ng11568)); + assign n4884 = ~n7648; + assign n7650 = (~\[1594] & ~Ng11567) | (n6223_1 & (\[1594] | ~Ng11567)); + assign n4880 = ~n7650; + assign n7652 = (~\[1612] & ~Ng11571) | (n6223_1 & (\[1612] | ~Ng11571)); + assign n4876 = ~n7652; + assign n7654 = (~Ng853 & ~Ng11570) | (n5135_1 & (Ng853 | ~Ng11570)); + assign n4842 = ~n7654; + assign n7656 = (~\[1594] & ~Ng11569) | (n5135_1 & (\[1594] | ~Ng11569)); + assign n4838 = ~n7656; + assign n7658 = (~\[1612] & ~Ng11539) | (n5131 & (\[1612] | ~Ng11539)); + assign n3327_1 = ~n7658; + assign n7660 = (~Ng853 & ~Ng1166) | (n6006 & (Ng853 | ~Ng1166)); + assign n3349_1 = ~n7660; + assign n7662 = (\[1594] & n6006) | (~Ng1165 & (~\[1594] | n6006)); + assign n3344_1 = ~n7662; + assign n7664 = (~\[1612] & ~Ng1164) | (n6006 & (\[1612] | ~Ng1164)); + assign n3339_1 = ~n7664; + assign n7666 = (~Ng853 & ~Ng11541) | (n6227_1 & (Ng853 | ~Ng11541)); + assign n3377_1 = ~n7666; + assign n7668 = (~\[1594] & ~Ng11540) | (n6227_1 & (\[1594] | ~Ng11540)); + assign n3373_1 = ~n7668; + assign n7670 = (~\[1612] & ~Ng11544) | (n6227_1 & (\[1612] | ~Ng11544)); + assign n3369_1 = ~n7670; + assign n7672 = (~Ng853 & ~Ng11543) | (n5131 & (Ng853 | ~Ng11543)); + assign n3335_1 = ~n7672; + assign n7674 = (~\[1594] & ~Ng11542) | (n5131 & (\[1594] | ~Ng11542)); + assign n3331_1 = ~n7674; + assign n7676 = (~\[1612] & ~Ng11512) | (n5126 & (\[1612] | ~Ng11512)); + assign n1821_1 = ~n7676; + assign n7678 = (~Ng853 & ~Ng479) | (n6014 & (Ng853 | ~Ng479)); + assign n1843_1 = ~n7678; + assign n7680 = (\[1594] & n6014) | (~Ng478 & (~\[1594] | n6014)); + assign n1838 = ~n7680; + assign n7682 = (~\[1612] & ~Ng477) | (n6014 & (\[1612] | ~Ng477)); + assign n1833 = ~n7682; + assign n7684 = (~Ng853 & ~Ng11514) | (n6231_1 & (Ng853 | ~Ng11514)); + assign n1871_1 = ~n7684; + assign n7686 = (~\[1594] & ~Ng11513) | (n6231_1 & (\[1594] | ~Ng11513)); + assign n1867_1 = ~n7686; + assign n7688 = (~\[1612] & ~Ng11517) | (n6231_1 & (\[1612] | ~Ng11517)); + assign n1863 = ~n7688; + assign n7690 = (~Ng853 & ~Ng11516) | (n5126 & (Ng853 | ~Ng11516)); + assign n1829 = ~n7690; + assign n7692 = (~\[1594] & ~Ng11515) | (n5126 & (\[1594] | ~Ng11515)); + assign n1825_1 = ~n7692; + assign n7694 = (~Ng853 & ~Ng2563) | (n4908 & (Ng853 | ~Ng2563)); + assign n6336 = ~n7694; + assign n7696 = (\[1594] & n4908) | (~Ng2562 & (~\[1594] | n4908)); + assign n6331 = ~n7696; + assign n7698 = (~\[1612] & ~Ng2561) | (n4908 & (\[1612] | ~Ng2561)); + assign n6326 = ~n7698; + assign n7700 = (~Ng853 & ~Ng2539) | (~n5034 & (Ng853 | ~Ng2539)); + assign n6378 = ~n7700; + assign n7702 = (\[1594] & ~n5034) | (~Ng2559 & (~\[1594] | ~n5034)); + assign n6373 = ~n7702; + assign n7704 = (~\[1612] & ~Ng2555) | (~n5034 & (\[1612] | ~Ng2555)); + assign n6368 = ~n7704; + assign n7706 = (n6521 & ~Ng2238) | (~n5044 & (~n6521 | ~Ng2238)); + assign n5550 = ~n7706; + assign n7708 = (~n5044 & ~n8747) | (~Ng2240 & (~n5044 | n8747)); + assign n5545 = ~n7708; + assign n7710 = (~Ng2239 & n8748) | (~n5044 & (~Ng2239 | ~n8748)); + assign n5540 = ~n7710; + assign n7712 = (n6521 & ~Ng2235) | (~n5046 & (~n6521 | ~Ng2235)); + assign n5535 = ~n7712; + assign n7714 = (~n5046 & ~n8747) | (~Ng2237 & (~n5046 | n8747)); + assign n5530 = ~n7714; + assign n7716 = (~Ng2236 & n8748) | (~n5046 & (~Ng2236 | ~n8748)); + assign n5525 = ~n7716; + assign n7718 = (n6521 & ~Ng2232) | (Ng2200 & (~n6521 | ~Ng2232)); + assign n5520 = ~n7718; + assign n7720 = (Ng2200 & ~n8747) | (~Ng2234 & (Ng2200 | n8747)); + assign n5515 = ~n7720; + assign n7722 = (~Ng2233 & n8748) | (Ng2200 & (~Ng2233 | ~n8748)); + assign n5510 = ~n7722; + assign n7724 = (n6521 & ~Ng2229) | (Ng2195 & (~n6521 | ~Ng2229)); + assign n5505 = ~n7724; + assign n7726 = (Ng2195 & ~n8747) | (~Ng2231 & (Ng2195 | n8747)); + assign n5500 = ~n7726; + assign n7728 = (~Ng2230 & n8748) | (Ng2195 & (~Ng2230 | ~n8748)); + assign n5495 = ~n7728; + assign n7730 = (n6521 & ~Ng2226) | (Ng2190 & (~n6521 | ~Ng2226)); + assign n5490 = ~n7730; + assign n7732 = (Ng2190 & ~n8747) | (~Ng2228 & (Ng2190 | n8747)); + assign n5485 = ~n7732; + assign n7734 = (~Ng2227 & n8748) | (Ng2190 & (~Ng2227 | ~n8748)); + assign n5480 = ~n7734; + assign n7736 = (n6521 & ~Ng2223) | (Ng2185 & (~n6521 | ~Ng2223)); + assign n5475 = ~n7736; + assign n7738 = (Ng2185 & ~n8747) | (~Ng2225 & (Ng2185 | n8747)); + assign n5470 = ~n7738; + assign n7740 = (~Ng2224 & n8748) | (Ng2185 & (~Ng2224 | ~n8748)); + assign n5465 = ~n7740; + assign n7742 = (n6521 & ~Ng2220) | (Ng2180 & (~n6521 | ~Ng2220)); + assign n5460 = ~n7742; + assign n7744 = (Ng2180 & ~n8747) | (~Ng2222 & (Ng2180 | n8747)); + assign n5455 = ~n7744; + assign n7746 = (~Ng2221 & n8748) | (Ng2180 & (~Ng2221 | ~n8748)); + assign n5450 = ~n7746; + assign n7748 = (n6521 & ~Ng2217) | (Ng2175 & (~n6521 | ~Ng2217)); + assign n5445 = ~n7748; + assign n7750 = (~Ng2219 & n8747) | (Ng2175 & (~Ng2219 | ~n8747)); + assign n5440 = ~n7750; + assign n7752 = (Ng2175 & ~n8748) | (~Ng2218 & (Ng2175 | n8748)); + assign n5435 = ~n7752; + assign n7754 = (n6521 & ~Ng2208) | (Ng2170 & (~n6521 | ~Ng2208)); + assign n5430 = ~n7754; + assign n7756 = (Ng2170 & ~n8747) | (~Ng2210 & (Ng2170 | n8747)); + assign n5425 = ~n7756; + assign n7758 = (~Ng2209 & n8748) | (Ng2170 & (~Ng2209 | ~n8748)); + assign n5420 = ~n7758; + assign n7760 = (n6521 & ~Ng2205) | (Ng2165 & (~n6521 | ~Ng2205)); + assign n5415 = ~n7760; + assign n7762 = (Ng2165 & ~n8747) | (~Ng2207 & (Ng2165 | n8747)); + assign n5410 = ~n7762; + assign n7764 = (~Ng2206 & n8748) | (Ng2165 & (~Ng2206 | ~n8748)); + assign n5405 = ~n7764; + assign n7766 = (~Ng853 & ~Ng1869) | (n4870 & (Ng853 | ~Ng1869)); + assign n4829 = ~n7766; + assign n7768 = (\[1594] & n4870) | (~Ng1868 & (~\[1594] | n4870)); + assign n4824 = ~n7768; + assign n7770 = (~\[1612] & ~Ng1867) | (n4870 & (\[1612] | ~Ng1867)); + assign n4819 = ~n7770; + assign n7772 = (~Ng853 & ~Ng1845) | (~n5022 & (Ng853 | ~Ng1845)); + assign n4871_1 = ~n7772; + assign n7774 = (\[1594] & ~n5022) | (~Ng1865 & (~\[1594] | ~n5022)); + assign n4866 = ~n7774; + assign n7776 = (~\[1612] & ~Ng1861) | (~n5022 & (\[1612] | ~Ng1861)); + assign n4861 = ~n7776; + assign n7778 = (n6521 & ~Ng1544) | (~n5040 & (~n6521 | ~Ng1544)); + assign n4056 = ~n7778; + assign n7780 = (~n5040 & ~n8747) | (~Ng1546 & (~n5040 | n8747)); + assign n4051 = ~n7780; + assign n7782 = (~Ng1545 & n8748) | (~n5040 & (~Ng1545 | ~n8748)); + assign n4046 = ~n7782; + assign n7784 = (n6521 & ~Ng1541) | (~n5042 & (~n6521 | ~Ng1541)); + assign n4041_1 = ~n7784; + assign n7786 = (~n5042 & ~n8747) | (~Ng1543 & (~n5042 | n8747)); + assign n4036 = ~n7786; + assign n7788 = (~Ng1542 & n8748) | (~n5042 & (~Ng1542 | ~n8748)); + assign n4031_1 = ~n7788; + assign n7790 = (n6521 & ~Ng1538) | (Ng1506 & (~n6521 | ~Ng1538)); + assign n4026 = ~n7790; + assign n7792 = (Ng1506 & ~n8747) | (~Ng1540 & (Ng1506 | n8747)); + assign n4021 = ~n7792; + assign n7794 = (~Ng1539 & n8748) | (Ng1506 & (~Ng1539 | ~n8748)); + assign n4016_1 = ~n7794; + assign n7796 = (n6521 & ~Ng1535) | (Ng1501 & (~n6521 | ~Ng1535)); + assign n4011_1 = ~n7796; + assign n7798 = (Ng1501 & ~n8747) | (~Ng1537 & (Ng1501 | n8747)); + assign n4006_1 = ~n7798; + assign n7800 = (~Ng1536 & n8748) | (Ng1501 & (~Ng1536 | ~n8748)); + assign n4001_1 = ~n7800; + assign n7802 = (n6521 & ~Ng1532) | (Ng1496 & (~n6521 | ~Ng1532)); + assign n3996_1 = ~n7802; + assign n7804 = (Ng1496 & ~n8747) | (~Ng1534 & (Ng1496 | n8747)); + assign n3991 = ~n7804; + assign n7806 = (~Ng1533 & n8748) | (Ng1496 & (~Ng1533 | ~n8748)); + assign n3986 = ~n7806; + assign n7808 = (n6521 & ~Ng1529) | (Ng1491 & (~n6521 | ~Ng1529)); + assign n3981 = ~n7808; + assign n7810 = (Ng1491 & ~n8747) | (~Ng1531 & (Ng1491 | n8747)); + assign n3976 = ~n7810; + assign n7812 = (~Ng1530 & n8748) | (Ng1491 & (~Ng1530 | ~n8748)); + assign n3971 = ~n7812; + assign n7814 = (n6521 & ~Ng1526) | (Ng1486 & (~n6521 | ~Ng1526)); + assign n3966 = ~n7814; + assign n7816 = (~Ng1528 & n8747) | (Ng1486 & (~Ng1528 | ~n8747)); + assign n3961_1 = ~n7816; + assign n7818 = (Ng1486 & ~n8748) | (~Ng1527 & (Ng1486 | n8748)); + assign n3956 = ~n7818; + assign n7820 = (n6521 & ~Ng1523) | (Ng1481 & (~n6521 | ~Ng1523)); + assign n3951 = ~n7820; + assign n7822 = (~Ng1525 & n8747) | (Ng1481 & (~Ng1525 | ~n8747)); + assign n3946 = ~n7822; + assign n7824 = (Ng1481 & ~n8748) | (~Ng1524 & (Ng1481 | n8748)); + assign n3941_1 = ~n7824; + assign n7826 = (n6521 & ~Ng1514) | (Ng1476 & (~n6521 | ~Ng1514)); + assign n3936 = ~n7826; + assign n7828 = (Ng1476 & ~n8747) | (~Ng1516 & (Ng1476 | n8747)); + assign n3931 = ~n7828; + assign n7830 = (~Ng1515 & n8748) | (Ng1476 & (~Ng1515 | ~n8748)); + assign n3926_1 = ~n7830; + assign n7832 = (n6521 & ~Ng1511) | (Ng1471 & (~n6521 | ~Ng1511)); + assign n3921 = ~n7832; + assign n7834 = (Ng1471 & ~n8747) | (~Ng1513 & (Ng1471 | n8747)); + assign n3916_1 = ~n7834; + assign n7836 = (~Ng1512 & n8748) | (Ng1471 & (~Ng1512 | ~n8748)); + assign n3911 = ~n7836; + assign n7838 = (~Ng853 & ~Ng1175) | (n4828 & (Ng853 | ~Ng1175)); + assign n3322_1 = ~n7838; + assign n7840 = (\[1594] & n4828) | (~Ng1174 & (~\[1594] | n4828)); + assign n3317_1 = ~n7840; + assign n7842 = (~\[1612] & ~Ng1173) | (n4828 & (\[1612] | ~Ng1173)); + assign n3312_1 = ~n7842; + assign n7844 = (~Ng853 & ~Ng1151) | (~n5010 & (Ng853 | ~Ng1151)); + assign n3364_1 = ~n7844; + assign n7846 = (\[1594] & ~n5010) | (~Ng1171 & (~\[1594] | ~n5010)); + assign n3359_1 = ~n7846; + assign n7848 = (~\[1612] & ~Ng1167) | (~n5010 & (\[1612] | ~Ng1167)); + assign n3354_1 = ~n7848; + assign n7850 = (n6521 & ~Ng850) | (~n5032 & (~n6521 | ~Ng850)); + assign n2549 = ~n7850; + assign n7852 = (~n5032 & ~n8747) | (~Ng852 & (~n5032 | n8747)); + assign n2544 = ~n7852; + assign n7854 = (~Ng851 & n8748) | (~n5032 & (~Ng851 | ~n8748)); + assign n2539 = ~n7854; + assign n7856 = (n6521 & ~Ng847) | (~n5038_1 & (~n6521 | ~Ng847)); + assign n2534_1 = ~n7856; + assign n7858 = (~n5038_1 & ~n8747) | (~Ng849 & (~n5038_1 | n8747)); + assign n2529 = ~n7858; + assign n7860 = (~Ng848 & n8748) | (~n5038_1 & (~Ng848 | ~n8748)); + assign n2524_1 = ~n7860; + assign n7862 = (n6521 & ~Ng844) | (Ng813 & (~n6521 | ~Ng844)); + assign n2519_1 = ~n7862; + assign n7864 = (Ng813 & ~n8747) | (~Ng846 & (Ng813 | n8747)); + assign n2514_1 = ~n7864; + assign n7866 = (~Ng845 & n8748) | (Ng813 & (~Ng845 | ~n8748)); + assign n2509 = ~n7866; + assign n7868 = (n6521 & ~Ng841) | (Ng809 & (~n6521 | ~Ng841)); + assign n2504_1 = ~n7868; + assign n7870 = (Ng809 & ~n8747) | (~Ng843 & (Ng809 | n8747)); + assign n2499_1 = ~n7870; + assign n7872 = (~Ng842 & n8748) | (Ng809 & (~Ng842 | ~n8748)); + assign n2494 = ~n7872; + assign n7874 = (n6521 & ~Ng838) | (Ng805 & (~n6521 | ~Ng838)); + assign n2489_1 = ~n7874; + assign n7876 = (Ng805 & ~n8747) | (~Ng840 & (Ng805 | n8747)); + assign n2484 = ~n7876; + assign n7878 = (~Ng839 & n8748) | (Ng805 & (~Ng839 | ~n8748)); + assign n2479 = ~n7878; + assign n7880 = (n6521 & ~Ng835) | (Ng801 & (~n6521 | ~Ng835)); + assign n2474 = ~n7880; + assign n7882 = (~Ng837 & n8747) | (Ng801 & (~Ng837 | ~n8747)); + assign n2469 = ~n7882; + assign n7884 = (Ng801 & ~n8748) | (~Ng836 & (Ng801 | n8748)); + assign n2464 = ~n7884; + assign n7886 = (n6521 & ~Ng832) | (Ng797 & (~n6521 | ~Ng832)); + assign n2459 = ~n7886; + assign n7888 = (~Ng834 & n8747) | (Ng797 & (~Ng834 | ~n8747)); + assign n2454 = ~n7888; + assign n7890 = (Ng797 & ~n8748) | (~Ng833 & (Ng797 | n8748)); + assign n2449 = ~n7890; + assign n7892 = (n6521 & ~Ng829) | (Ng793 & (~n6521 | ~Ng829)); + assign n2444_1 = ~n7892; + assign n7894 = (~Ng831 & n8747) | (Ng793 & (~Ng831 | ~n8747)); + assign n2439 = ~n7894; + assign n7896 = (Ng793 & ~n8748) | (~Ng830 & (Ng793 | n8748)); + assign n2434 = ~n7896; + assign n7898 = (n6521 & ~Ng820) | (Ng789 & (~n6521 | ~Ng820)); + assign n2429_1 = ~n7898; + assign n7900 = (Ng789 & ~n8747) | (~Ng822 & (Ng789 | n8747)); + assign n2424_1 = ~n7900; + assign n7902 = (~Ng821 & n8748) | (Ng789 & (~Ng821 | ~n8748)); + assign n2419 = ~n7902; + assign n7904 = (n6521 & ~Ng817) | (Ng785 & (~n6521 | ~Ng817)); + assign n2414 = ~n7904; + assign n7906 = (Ng785 & ~n8747) | (~Ng819 & (Ng785 | n8747)); + assign n2409 = ~n7906; + assign n7908 = (~Ng818 & n8748) | (Ng785 & (~Ng818 | ~n8748)); + assign n2404 = ~n7908; + assign n7910 = (~Ng853 & ~Ng488) | (n4786 & (Ng853 | ~Ng488)); + assign n1816_1 = ~n7910; + assign n7912 = (\[1594] & n4786) | (~Ng487 & (~\[1594] | n4786)); + assign n1811_1 = ~n7912; + assign n7914 = (~\[1612] & ~Ng486) | (n4786 & (\[1612] | ~Ng486)); + assign n1806_1 = ~n7914; + assign n7916 = (~Ng853 & ~Ng464) | (~n4998_1 & (Ng853 | ~Ng464)); + assign n1858_1 = ~n7916; + assign n7918 = (\[1594] & ~n4998_1) | (~Ng484 & (~\[1594] | ~n4998_1)); + assign n1853_1 = ~n7918; + assign n7920 = (~\[1612] & ~Ng480) | (~n4998_1 & (\[1612] | ~Ng480)); + assign n1848 = ~n7920; + assign n7922 = (n6521 & ~Ng162) | (~n5020 & (~n6521 | ~Ng162)); + assign n1043_1 = ~n7922; + assign n7924 = (~n5020 & ~n8747) | (~Ng164 & (~n5020 | n8747)); + assign n1038_1 = ~n7924; + assign n7926 = (~Ng163 & n8748) | (~n5020 & (~Ng163 | ~n8748)); + assign n1033 = ~n7926; + assign n7928 = (n6521 & ~Ng159) | (~n5030 & (~n6521 | ~Ng159)); + assign n1028_1 = ~n7928; + assign n7930 = (~n5030 & ~n8747) | (~Ng161 & (~n5030 | n8747)); + assign n1023_1 = ~n7930; + assign n7932 = (~Ng160 & n8748) | (~n5030 & (~Ng160 | ~n8748)); + assign n1018 = ~n7932; + assign n7934 = (n6521 & ~Ng156) | (Ng125 & (~n6521 | ~Ng156)); + assign n1013_1 = ~n7934; + assign n7936 = (Ng125 & ~n8747) | (~Ng158 & (Ng125 | n8747)); + assign n1008_1 = ~n7936; + assign n7938 = (~Ng157 & n8748) | (Ng125 & (~Ng157 | ~n8748)); + assign n1003 = ~n7938; + assign n7940 = (n6521 & ~Ng153) | (Ng121 & (~n6521 | ~Ng153)); + assign n998 = ~n7940; + assign n7942 = (Ng121 & ~n8747) | (~Ng155 & (Ng121 | n8747)); + assign n993_1 = ~n7942; + assign n7944 = (~Ng154 & n8748) | (Ng121 & (~Ng154 | ~n8748)); + assign n988_1 = ~n7944; + assign n7946 = (n6521 & ~Ng150) | (Ng117 & (~n6521 | ~Ng150)); + assign n983_1 = ~n7946; + assign n7948 = (~Ng152 & n8747) | (Ng117 & (~Ng152 | ~n8747)); + assign n978_1 = ~n7948; + assign n7950 = (Ng117 & ~n8748) | (~Ng151 & (Ng117 | n8748)); + assign n973_1 = ~n7950; + assign n7952 = (n6521 & ~Ng147) | (Ng113 & (~n6521 | ~Ng147)); + assign n968_1 = ~n7952; + assign n7954 = (~Ng149 & n8747) | (Ng113 & (~Ng149 | ~n8747)); + assign n963_1 = ~n7954; + assign n7956 = (Ng113 & ~n8748) | (~Ng148 & (Ng113 | n8748)); + assign n958 = ~n7956; + assign n7958 = (n6521 & ~Ng144) | (Ng109 & (~n6521 | ~Ng144)); + assign n953_1 = ~n7958; + assign n7960 = (~Ng146 & n8747) | (Ng109 & (~Ng146 | ~n8747)); + assign n948_1 = ~n7960; + assign n7962 = (Ng109 & ~n8748) | (~Ng145 & (Ng109 | n8748)); + assign n943_1 = ~n7962; + assign n7964 = (n6521 & ~Ng141) | (Ng105 & (~n6521 | ~Ng141)); + assign n938_1 = ~n7964; + assign n7966 = (~Ng143 & n8747) | (Ng105 & (~Ng143 | ~n8747)); + assign n933_1 = ~n7966; + assign n7968 = (Ng105 & ~n8748) | (~Ng142 & (Ng105 | n8748)); + assign n928 = ~n7968; + assign n7970 = (n6521 & ~Ng132) | (Ng101 & (~n6521 | ~Ng132)); + assign n923_1 = ~n7970; + assign n7972 = (Ng101 & ~n8747) | (~Ng134 & (Ng101 | n8747)); + assign n918_1 = ~n7972; + assign n7974 = (~Ng133 & n8748) | (Ng101 & (~Ng133 | ~n8748)); + assign n913_1 = ~n7974; + assign n7976 = (n6521 & ~Ng129) | (Ng97 & (~n6521 | ~Ng129)); + assign n908_1 = ~n7976; + assign n7978 = (Ng97 & ~n8747) | (~Ng131 & (Ng97 | n8747)); + assign n903_1 = ~n7978; + assign n7980 = (~Ng130 & n8748) | (Ng97 & (~Ng130 | ~n8748)); + assign n898_1 = ~n7980; + assign n7982 = (~Ng2879 & n8749) | (~Pg8096 & (Ng2879 | n8749)); + assign n616 = ~n7982; + assign n7984 = (Ng2879 & ~n8763) | (~Ng13455 & (~Ng2879 | ~n8763)); + assign n664_1 = ~n7984; + assign n7986 = (~Ng2879 & ~Ng13439) | (n8749 & (Ng2879 | ~Ng13439)); + assign n475_1 = ~n7986; + assign n7988 = (~Ng2879 & ~n8763) | (~Pg7519 & (Ng2879 | ~n8763)); + assign n544_1 = ~n7988; + assign n7990 = (n5192 & ~Ng2805) | (~n5064 & (~n5192 | ~Ng2805)); + assign n6877 = ~n7990; + assign n7992 = (~n5064 & ~n5115_1) | (~Ng2807 & (~n5064 | n5115_1)); + assign n6872 = ~n7992; + assign n7994 = (n5180_1 & ~Ng2806) | (~n5064 & (~n5180_1 | ~Ng2806)); + assign n6867 = ~n7994; + assign n7996 = (n5192 & ~Ng2802) | (~n4982 & (~n5192 | ~Ng2802)); + assign n6862 = ~n7996; + assign n7998 = (n5115_1 & ~Ng2804) | (~n4982 & (~n5115_1 | ~Ng2804)); + assign n6857 = ~n7998; + assign n8000 = (n5180_1 & ~Ng2803) | (~n4982 & (~n5180_1 | ~Ng2803)); + assign n6852 = ~n8000; + assign n8002 = (~n5193 & ~Ng2799) | (Ng2766 & (n5193 | ~Ng2799)); + assign n6847 = ~n8002; + assign n8004 = (n5188 & Ng2766) | (~Ng2801 & (~n5188 | Ng2766)); + assign n6842 = ~n8004; + assign n8006 = (~n5181 & ~Ng2800) | (Ng2766 & (n5181 | ~Ng2800)); + assign n6837 = ~n8006; + assign n8008 = (~n5193 & ~Ng2796) | (Ng2760 & (n5193 | ~Ng2796)); + assign n6832 = ~n8008; + assign n8010 = (n5188 & Ng2760) | (~Ng2798 & (~n5188 | Ng2760)); + assign n6827 = ~n8010; + assign n8012 = (~n5181 & ~Ng2797) | (Ng2760 & (n5181 | ~Ng2797)); + assign n6822 = ~n8012; + assign n8014 = (~n5193 & ~Ng2793) | (Ng2753 & (n5193 | ~Ng2793)); + assign n6817 = ~n8014; + assign n8016 = (n5188 & Ng2753) | (~Ng2795 & (~n5188 | Ng2753)); + assign n6812 = ~n8016; + assign n8018 = (~n5181 & ~Ng2794) | (Ng2753 & (n5181 | ~Ng2794)); + assign n6807 = ~n8018; + assign n8020 = (~n5193 & ~Ng2790) | (Ng2740 & (n5193 | ~Ng2790)); + assign n6802 = ~n8020; + assign n8022 = (n5188 & Ng2740) | (~Ng2792 & (~n5188 | Ng2740)); + assign n6797 = ~n8022; + assign n8024 = (~n5181 & ~Ng2791) | (Ng2740 & (n5181 | ~Ng2791)); + assign n6792 = ~n8024; + assign n8026 = (~n5193 & ~Ng2787) | (Ng2746 & (n5193 | ~Ng2787)); + assign n6787 = ~n8026; + assign n8028 = (n5188 & Ng2746) | (~Ng2789 & (~n5188 | Ng2746)); + assign n6782 = ~n8028; + assign n8030 = (~n5181 & ~Ng2788) | (Ng2746 & (n5181 | ~Ng2788)); + assign n6777 = ~n8030; + assign n8032 = (~n5193 & ~Ng2784) | (Ng2734 & (n5193 | ~Ng2784)); + assign n6772 = ~n8032; + assign n8034 = (n5188 & Ng2734) | (~Ng2786 & (~n5188 | Ng2734)); + assign n6767 = ~n8034; + assign n8036 = (~n5181 & ~Ng2785) | (Ng2734 & (n5181 | ~Ng2785)); + assign n6762 = ~n8036; + assign n8038 = (~n5193 & ~Ng2781) | (Ng2720 & (n5193 | ~Ng2781)); + assign n6757 = ~n8038; + assign n8040 = (n5188 & Ng2720) | (~Ng2783 & (~n5188 | Ng2720)); + assign n6752 = ~n8040; + assign n8042 = (~n5181 & ~Ng2782) | (Ng2720 & (n5181 | ~Ng2782)); + assign n6747 = ~n8042; + assign n8044 = (~n5193 & ~Ng2778) | (Ng2727 & (n5193 | ~Ng2778)); + assign n6742 = ~n8044; + assign n8046 = (n5188 & Ng2727) | (~Ng2780 & (~n5188 | Ng2727)); + assign n6737 = ~n8046; + assign n8048 = (~n5181 & ~Ng2779) | (Ng2727 & (n5181 | ~Ng2779)); + assign n6732 = ~n8048; + assign n8050 = (~n5193 & ~Ng2775) | (Ng2707 & (n5193 | ~Ng2775)); + assign n6727 = ~n8050; + assign n8052 = (n5188 & Ng2707) | (~Ng2777 & (~n5188 | Ng2707)); + assign n6722 = ~n8052; + assign n8054 = (~n5181 & ~Ng2776) | (Ng2707 & (n5181 | ~Ng2776)); + assign n6717 = ~n8054; + assign n8056 = (~n5193 & ~Ng2772) | (Ng2714 & (n5193 | ~Ng2772)); + assign n6712 = ~n8056; + assign n8058 = (n5188 & Ng2714) | (~Ng2774 & (~n5188 | Ng2714)); + assign n6707 = ~n8058; + assign n8060 = (~n5181 & ~Ng2773) | (Ng2714 & (n5181 | ~Ng2773)); + assign n6702 = ~n8060; + assign n8062 = (n5185_1 & ~Ng2111) | (~n5062 & (~n5185_1 | ~Ng2111)); + assign n5370 = ~n8062; + assign n8064 = (~n5062 & ~n5112) | (~Ng2113 & (~n5062 | n5112)); + assign n5365 = ~n8064; + assign n8066 = (n5170_1 & ~Ng2112) | (~n5062 & (~n5170_1 | ~Ng2112)); + assign n5360 = ~n8066; + assign n8068 = (n5185_1 & ~Ng2108) | (~n4978_1 & (~n5185_1 | ~Ng2108)); + assign n5355 = ~n8068; + assign n8070 = (n5112 & ~Ng2110) | (~n4978_1 & (~n5112 | ~Ng2110)); + assign n5350 = ~n8070; + assign n8072 = (n5170_1 & ~Ng2109) | (~n4978_1 & (~n5170_1 | ~Ng2109)); + assign n5345 = ~n8072; + assign n8074 = (~n5186 & ~Ng2105) | (Ng2072 & (n5186 | ~Ng2105)); + assign n5340 = ~n8074; + assign n8076 = (n5178 & Ng2072) | (~Ng2107 & (~n5178 | Ng2072)); + assign n5335 = ~n8076; + assign n8078 = (~n5171 & ~Ng2106) | (Ng2072 & (n5171 | ~Ng2106)); + assign n5330 = ~n8078; + assign n8080 = (~n5186 & ~Ng2102) | (Ng2066 & (n5186 | ~Ng2102)); + assign n5325 = ~n8080; + assign n8082 = (n5178 & Ng2066) | (~Ng2104 & (~n5178 | Ng2066)); + assign n5320 = ~n8082; + assign n8084 = (~n5171 & ~Ng2103) | (Ng2066 & (n5171 | ~Ng2103)); + assign n5315 = ~n8084; + assign n8086 = (~n5186 & ~Ng2099) | (Ng2059 & (n5186 | ~Ng2099)); + assign n5310 = ~n8086; + assign n8088 = (n5178 & Ng2059) | (~Ng2101 & (~n5178 | Ng2059)); + assign n5305 = ~n8088; + assign n8090 = (~n5171 & ~Ng2100) | (Ng2059 & (n5171 | ~Ng2100)); + assign n5300 = ~n8090; + assign n8092 = (~n5186 & ~Ng2096) | (Ng2046 & (n5186 | ~Ng2096)); + assign n5295 = ~n8092; + assign n8094 = (n5178 & Ng2046) | (~Ng2098 & (~n5178 | Ng2046)); + assign n5290 = ~n8094; + assign n8096 = (~n5171 & ~Ng2097) | (Ng2046 & (n5171 | ~Ng2097)); + assign n5285 = ~n8096; + assign n8098 = (~n5186 & ~Ng2093) | (Ng2052 & (n5186 | ~Ng2093)); + assign n5280 = ~n8098; + assign n8100 = (n5178 & Ng2052) | (~Ng2095 & (~n5178 | Ng2052)); + assign n5275 = ~n8100; + assign n8102 = (~n5171 & ~Ng2094) | (Ng2052 & (n5171 | ~Ng2094)); + assign n5270 = ~n8102; + assign n8104 = (~n5186 & ~Ng2090) | (Ng2040 & (n5186 | ~Ng2090)); + assign n5265 = ~n8104; + assign n8106 = (n5178 & Ng2040) | (~Ng2092 & (~n5178 | Ng2040)); + assign n5260 = ~n8106; + assign n8108 = (~n5171 & ~Ng2091) | (Ng2040 & (n5171 | ~Ng2091)); + assign n5255 = ~n8108; + assign n8110 = (~n5186 & ~Ng2087) | (Ng2026 & (n5186 | ~Ng2087)); + assign n5250 = ~n8110; + assign n8112 = (n5178 & Ng2026) | (~Ng2089 & (~n5178 | Ng2026)); + assign n5245 = ~n8112; + assign n8114 = (~n5171 & ~Ng2088) | (Ng2026 & (n5171 | ~Ng2088)); + assign n5240 = ~n8114; + assign n8116 = (~n5186 & ~Ng2084) | (Ng2033 & (n5186 | ~Ng2084)); + assign n5235 = ~n8116; + assign n8118 = (n5178 & Ng2033) | (~Ng2086 & (~n5178 | Ng2033)); + assign n5230 = ~n8118; + assign n8120 = (~n5171 & ~Ng2085) | (Ng2033 & (n5171 | ~Ng2085)); + assign n5225 = ~n8120; + assign n8122 = (~n5186 & ~Ng2081) | (Ng2013 & (n5186 | ~Ng2081)); + assign n5220 = ~n8122; + assign n8124 = (n5178 & Ng2013) | (~Ng2083 & (~n5178 | Ng2013)); + assign n5215 = ~n8124; + assign n8126 = (~n5171 & ~Ng2082) | (Ng2013 & (n5171 | ~Ng2082)); + assign n5210 = ~n8126; + assign n8128 = (~n5186 & ~Ng2078) | (Ng2020 & (n5186 | ~Ng2078)); + assign n5205 = ~n8128; + assign n8130 = (n5178 & Ng2020) | (~Ng2080 & (~n5178 | Ng2020)); + assign n5200 = ~n8130; + assign n8132 = (~n5171 & ~Ng2079) | (Ng2020 & (n5171 | ~Ng2079)); + assign n5195 = ~n8132; + assign n8134 = (n5175_1 & ~Ng1417) | (~n5058_1 & (~n5175_1 | ~Ng1417)); + assign n3876_1 = ~n8134; + assign n8136 = (~n5058_1 & ~n5109) | (~Ng1419 & (~n5058_1 | n5109)); + assign n3871_1 = ~n8136; + assign n8138 = (n5160_1 & ~Ng1418) | (~n5058_1 & (~n5160_1 | ~Ng1418)); + assign n3866 = ~n8138; + assign n8140 = (n5175_1 & ~Ng1414) | (~n4972 & (~n5175_1 | ~Ng1414)); + assign n3861_1 = ~n8140; + assign n8142 = (n5109 & ~Ng1416) | (~n4972 & (~n5109 | ~Ng1416)); + assign n3856_1 = ~n8142; + assign n8144 = (n5160_1 & ~Ng1415) | (~n4972 & (~n5160_1 | ~Ng1415)); + assign n3851_1 = ~n8144; + assign n8146 = (~n5176 & ~Ng1411) | (Ng1378 & (n5176 | ~Ng1411)); + assign n3846_1 = ~n8146; + assign n8148 = (n5168 & Ng1378) | (~Ng1413 & (~n5168 | Ng1378)); + assign n3841_1 = ~n8148; + assign n8150 = (~n5161 & ~Ng1412) | (Ng1378 & (n5161 | ~Ng1412)); + assign n3836_1 = ~n8150; + assign n8152 = (~n5176 & ~Ng1408) | (Ng1372 & (n5176 | ~Ng1408)); + assign n3831_1 = ~n8152; + assign n8154 = (n5168 & Ng1372) | (~Ng1410 & (~n5168 | Ng1372)); + assign n3826_1 = ~n8154; + assign n8156 = (~n5161 & ~Ng1409) | (Ng1372 & (n5161 | ~Ng1409)); + assign n3821 = ~n8156; + assign n8158 = (~n5176 & ~Ng1405) | (Ng1365 & (n5176 | ~Ng1405)); + assign n3816 = ~n8158; + assign n8160 = (n5168 & Ng1365) | (~Ng1407 & (~n5168 | Ng1365)); + assign n3811_1 = ~n8160; + assign n8162 = (~n5161 & ~Ng1406) | (Ng1365 & (n5161 | ~Ng1406)); + assign n3806 = ~n8162; + assign n8164 = (~n5176 & ~Ng1402) | (Ng1352 & (n5176 | ~Ng1402)); + assign n3801 = ~n8164; + assign n8166 = (n5168 & Ng1352) | (~Ng1404 & (~n5168 | Ng1352)); + assign n3796_1 = ~n8166; + assign n8168 = (~n5161 & ~Ng1403) | (Ng1352 & (n5161 | ~Ng1403)); + assign n3791 = ~n8168; + assign n8170 = (~n5176 & ~Ng1399) | (Ng1358 & (n5176 | ~Ng1399)); + assign n3786 = ~n8170; + assign n8172 = (n5168 & Ng1358) | (~Ng1401 & (~n5168 | Ng1358)); + assign n3781_1 = ~n8172; + assign n8174 = (~n5161 & ~Ng1400) | (Ng1358 & (n5161 | ~Ng1400)); + assign n3776_1 = ~n8174; + assign n8176 = (~n5176 & ~Ng1396) | (Ng1346 & (n5176 | ~Ng1396)); + assign n3771 = ~n8176; + assign n8178 = (n5168 & Ng1346) | (~Ng1398 & (~n5168 | Ng1346)); + assign n3766_1 = ~n8178; + assign n8180 = (~n5161 & ~Ng1397) | (Ng1346 & (n5161 | ~Ng1397)); + assign n3761 = ~n8180; + assign n8182 = (~n5176 & ~Ng1393) | (Ng1332 & (n5176 | ~Ng1393)); + assign n3756_1 = ~n8182; + assign n8184 = (n5168 & Ng1332) | (~Ng1395 & (~n5168 | Ng1332)); + assign n3751_1 = ~n8184; + assign n8186 = (~n5161 & ~Ng1394) | (Ng1332 & (n5161 | ~Ng1394)); + assign n3746_1 = ~n8186; + assign n8188 = (~n5176 & ~Ng1390) | (Ng1339 & (n5176 | ~Ng1390)); + assign n3741_1 = ~n8188; + assign n8190 = (n5168 & Ng1339) | (~Ng1392 & (~n5168 | Ng1339)); + assign n3736_1 = ~n8190; + assign n8192 = (~n5161 & ~Ng1391) | (Ng1339 & (n5161 | ~Ng1391)); + assign n3731_1 = ~n8192; + assign n8194 = (~n5176 & ~Ng1387) | (Ng1319 & (n5176 | ~Ng1387)); + assign n3726_1 = ~n8194; + assign n8196 = (n5168 & Ng1319) | (~Ng1389 & (~n5168 | Ng1319)); + assign n3721_1 = ~n8196; + assign n8198 = (~n5161 & ~Ng1388) | (Ng1319 & (n5161 | ~Ng1388)); + assign n3716_1 = ~n8198; + assign n8200 = (~n5176 & ~Ng1384) | (Ng1326 & (n5176 | ~Ng1384)); + assign n3711_1 = ~n8200; + assign n8202 = (n5168 & Ng1326) | (~Ng1386 & (~n5168 | Ng1326)); + assign n3706_1 = ~n8202; + assign n8204 = (~n5161 & ~Ng1385) | (Ng1326 & (n5161 | ~Ng1385)); + assign n3701_1 = ~n8204; + assign n8206 = (n5165_1 & ~Ng731) | (~n5054 & (~n5165_1 | ~Ng731)); + assign n2357 = ~n8206; + assign n8208 = (~n5054 & ~n5106) | (~Ng733 & (~n5054 | n5106)); + assign n2352 = ~n8208; + assign n8210 = (n5153 & ~Ng732) | (~n5054 & (~n5153 | ~Ng732)); + assign n2347 = ~n8210; + assign n8212 = (n5165_1 & ~Ng728) | (~n4964 & (~n5165_1 | ~Ng728)); + assign n2342 = ~n8212; + assign n8214 = (n5106 & ~Ng730) | (~n4964 & (~n5106 | ~Ng730)); + assign n2337 = ~n8214; + assign n8216 = (n5153 & ~Ng729) | (~n4964 & (~n5153 | ~Ng729)); + assign n2332_1 = ~n8216; + assign n8218 = (~n5166 & ~Ng725) | (Ng692 & (n5166 | ~Ng725)); + assign n2327_1 = ~n8218; + assign n8220 = (n5158 & Ng692) | (~Ng727 & (~n5158 | Ng692)); + assign n2322 = ~n8220; + assign n8222 = (~n5154 & ~Ng726) | (Ng692 & (n5154 | ~Ng726)); + assign n2317 = ~n8222; + assign n8224 = (~n5166 & ~Ng722) | (Ng686 & (n5166 | ~Ng722)); + assign n2312 = ~n8224; + assign n8226 = (n5158 & Ng686) | (~Ng724 & (~n5158 | Ng686)); + assign n2307 = ~n8226; + assign n8228 = (~n5154 & ~Ng723) | (Ng686 & (n5154 | ~Ng723)); + assign n2302 = ~n8228; + assign n8230 = (~n5166 & ~Ng719) | (Ng679 & (n5166 | ~Ng719)); + assign n2297_1 = ~n8230; + assign n8232 = (n5158 & Ng679) | (~Ng721 & (~n5158 | Ng679)); + assign n2292 = ~n8232; + assign n8234 = (~n5154 & ~Ng720) | (Ng679 & (n5154 | ~Ng720)); + assign n2287 = ~n8234; + assign n8236 = (~n5166 & ~Ng716) | (Ng666 & (n5166 | ~Ng716)); + assign n2282 = ~n8236; + assign n8238 = (n5158 & Ng666) | (~Ng718 & (~n5158 | Ng666)); + assign n2277 = ~n8238; + assign n8240 = (~n5154 & ~Ng717) | (Ng666 & (n5154 | ~Ng717)); + assign n2272 = ~n8240; + assign n8242 = (~n5166 & ~Ng713) | (Ng672 & (n5166 | ~Ng713)); + assign n2267 = ~n8242; + assign n8244 = (n5158 & Ng672) | (~Ng715 & (~n5158 | Ng672)); + assign n2262 = ~n8244; + assign n8246 = (~n5154 & ~Ng714) | (Ng672 & (n5154 | ~Ng714)); + assign n2257_1 = ~n8246; + assign n8248 = (~n5166 & ~Ng710) | (Ng660 & (n5166 | ~Ng710)); + assign n2252 = ~n8248; + assign n8250 = (n5158 & Ng660) | (~Ng712 & (~n5158 | Ng660)); + assign n2247_1 = ~n8250; + assign n8252 = (~n5154 & ~Ng711) | (Ng660 & (n5154 | ~Ng711)); + assign n2242 = ~n8252; + assign n8254 = (~n5166 & ~Ng707) | (Ng646 & (n5166 | ~Ng707)); + assign n2237_1 = ~n8254; + assign n8256 = (n5158 & Ng646) | (~Ng709 & (~n5158 | Ng646)); + assign n2232 = ~n8256; + assign n8258 = (~n5154 & ~Ng708) | (Ng646 & (n5154 | ~Ng708)); + assign n2227_1 = ~n8258; + assign n8260 = (~n5166 & ~Ng704) | (Ng653 & (n5166 | ~Ng704)); + assign n2222 = ~n8260; + assign n8262 = (n5158 & Ng653) | (~Ng706 & (~n5158 | Ng653)); + assign n2217_1 = ~n8262; + assign n8264 = (~n5154 & ~Ng705) | (Ng653 & (n5154 | ~Ng705)); + assign n2212_1 = ~n8264; + assign n8266 = (~n5166 & ~Ng701) | (Ng633 & (n5166 | ~Ng701)); + assign n2207_1 = ~n8266; + assign n8268 = (n5158 & Ng633) | (~Ng703 & (~n5158 | Ng633)); + assign n2202 = ~n8268; + assign n8270 = (~n5154 & ~Ng702) | (Ng633 & (n5154 | ~Ng702)); + assign n2197 = ~n8270; + assign n8272 = (~n5166 & ~Ng698) | (Ng640 & (n5166 | ~Ng698)); + assign n2192_1 = ~n8272; + assign n8274 = (n5158 & Ng640) | (~Ng700 & (~n5158 | Ng640)); + assign n2187_1 = ~n8274; + assign n8276 = (~n5154 & ~Ng699) | (Ng640 & (n5154 | ~Ng699)); + assign n2182_1 = ~n8276; + assign n8278 = (~Ng2879 & ~Ng2975) | (~Pg4590 & (Ng2879 | ~Ng2975)); + assign n504_1 = ~n8278; + assign n8280 = (~Ng2879 & ~Ng2978) | (~Pg4323 & (Ng2879 | ~Ng2978)); + assign n496_1 = ~n8280; + assign n8282 = (~Ng2879 & ~Ng2981) | (~Pg4090 & (Ng2879 | ~Ng2981)); + assign n488_1 = ~n8282; + assign n8284 = (~Ng2879 & ~Ng2874) | (~Pg8251 & (Ng2879 | ~Ng2874)); + assign n480_1 = ~n8284; + assign n8286 = (~Ng2879 & ~Ng2935) | (~Pg4450 & (Ng2879 | ~Ng2935)); + assign n608_1 = ~n8286; + assign n8288 = (~Ng2879 & ~Ng2938) | (~Pg4200 & (Ng2879 | ~Ng2938)); + assign n600_1 = ~n8288; + assign n8290 = (~Ng2879 & ~Ng2941) | (~Pg3993 & (Ng2879 | ~Ng2941)); + assign n592_1 = ~n8290; + assign n8292 = (~Ng2879 & ~Ng2944) | (~Pg8175 & (Ng2879 | ~Ng2944)); + assign n584_1 = ~n8292; + assign n8294 = (~Ng2879 & ~Ng2947) | (~Pg8023 & (Ng2879 | ~Ng2947)); + assign n576_1 = ~n8294; + assign n8296 = (~Ng2879 & ~Ng2953) | (~Pg4321 & (Ng2879 | ~Ng2953)); + assign n568_1 = ~n8296; + assign n8298 = (~Ng2879 & ~Ng2956) | (~Pg4088 & (Ng2879 | ~Ng2956)); + assign n560_1 = ~n8298; + assign n8300 = (~Ng2879 & ~Ng2959) | (~Pg8249 & (Ng2879 | ~Ng2959)); + assign n552_1 = ~n8300; + assign n8302 = (~Ng2879 & ~Ng2963) | (~Pg7334 & (Ng2879 | ~Ng2963)); + assign n536_1 = ~n8302; + assign n8304 = (~Ng2879 & ~Ng2966) | (~Pg6895 & (Ng2879 | ~Ng2966)); + assign n528_1 = ~n8304; + assign n8306 = (~Ng2879 & ~Ng2969) | (~Pg6442 & (Ng2879 | ~Ng2969)); + assign n520_1 = ~n8306; + assign n8308 = (~Ng2879 & ~Ng2972) | (~Pg6225 & (Ng2879 | ~Ng2972)); + assign n512_1 = ~n8308; + assign n8310 = (~Ng1315 & ~Ng3084) | (~Ng559 & (Ng1315 | ~Ng3084)); + assign n679_1 = ~n8310; + assign n8312 = (~\[1603] & ~Ng3211) | (~Ng559 & (\[1603] | ~Ng3211)); + assign n674 = ~n8312; + assign n8314 = (~\[1605] & ~Ng3210) | (~Ng559 & (\[1605] | ~Ng3210)); + assign n669_1 = ~n8314; + assign n8316 = (~Ng1315 & ~Ng3088) | (~Ng8311 & (Ng1315 | ~Ng3088)); + assign n844_1 = ~n8316; + assign n8318 = (~\[1603] & ~Ng3185) | (~Ng8311 & (\[1603] | ~Ng3185)); + assign n839_1 = ~n8318; + assign n8320 = (~\[1605] & ~Ng3182) | (~Ng8311 & (\[1605] | ~Ng3182)); + assign n834_1 = ~n8320; + assign n8322 = (~Ng1315 & ~Ng3179) | (~Ng8302 & (Ng1315 | ~Ng3179)); + assign n829_1 = ~n8322; + assign n8324 = (~\[1603] & ~Ng3176) | (~Ng8302 & (\[1603] | ~Ng3176)); + assign n824_1 = ~n8324; + assign n8326 = (~\[1605] & ~Ng3173) | (~Ng8302 & (\[1605] | ~Ng3173)); + assign n819_1 = ~n8326; + assign n8328 = (~Ng1315 & ~Ng3170) | (~Ng8293 & (Ng1315 | ~Ng3170)); + assign n814_1 = ~n8328; + assign n8330 = (~\[1603] & ~Ng3167) | (~Ng8293 & (\[1603] | ~Ng3167)); + assign n809_1 = ~n8330; + assign n8332 = (~\[1605] & ~Ng3164) | (~Ng8293 & (\[1605] | ~Ng3164)); + assign n804_1 = ~n8332; + assign n8334 = (~Ng1315 & ~Ng3161) | (~Ng8284 & (Ng1315 | ~Ng3161)); + assign n799_1 = ~n8334; + assign n8336 = (~\[1603] & ~Ng3158) | (~Ng8284 & (\[1603] | ~Ng3158)); + assign n794_1 = ~n8336; + assign n8338 = (~\[1605] & ~Ng3155) | (~Ng8284 & (\[1605] | ~Ng3155)); + assign n789_1 = ~n8338; + assign n8340 = (~Ng1315 & ~Ng3096) | (~Ng2633 & (Ng1315 | ~Ng3096)); + assign n724_1 = ~n8340; + assign n8342 = (~\[1603] & ~Ng3095) | (~Ng2633 & (\[1603] | ~Ng3095)); + assign n719_1 = ~n8342; + assign n8344 = (~\[1605] & ~Ng3094) | (~Ng2633 & (\[1605] | ~Ng3094)); + assign n714_1 = ~n8344; + assign n8346 = (~Ng1315 & ~Ng3093) | (~Ng1939 & (Ng1315 | ~Ng3093)); + assign n709_1 = ~n8346; + assign n8348 = (~\[1603] & ~Ng3092) | (~Ng1939 & (\[1603] | ~Ng3092)); + assign n704_1 = ~n8348; + assign n8350 = (~\[1605] & ~Ng3091) | (~Ng1939 & (\[1605] | ~Ng3091)); + assign n699_1 = ~n8350; + assign n8352 = (~Ng1315 & ~Ng3087) | (~Ng1245 & (Ng1315 | ~Ng3087)); + assign n694 = ~n8352; + assign n8354 = (~\[1603] & ~Ng3086) | (~Ng1245 & (\[1603] | ~Ng3086)); + assign n689_1 = ~n8354; + assign n8356 = (~\[1605] & ~Ng3085) | (~Ng1245 & (\[1605] | ~Ng3085)); + assign n684_1 = ~n8356; + assign n8358 = (Ng2987 & ~Ng3074) | (~Ng3056 & (~Ng2987 | ~Ng3074)); + assign n7230 = ~n8358; + assign n8360 = (Ng2987 & ~Ng3073) | (~Ng3055 & (~Ng2987 | ~Ng3073)); + assign n7226 = ~n8360; + assign n8362 = (Ng2987 & ~Ng3072) | (~Ng3053 & (~Ng2987 | ~Ng3072)); + assign n7222 = ~n8362; + assign n8364 = (Ng2987 & ~Ng3071) | (~Ng3052 & (~Ng2987 | ~Ng3071)); + assign n7218 = ~n8364; + assign n8366 = (Ng2987 & ~Ng3070) | (~Ng3051 & (~Ng2987 | ~Ng3070)); + assign n7204 = ~n8366; + assign n8368 = (Ng2987 & ~Ng3069) | (~Ng3050 & (~Ng2987 | ~Ng3069)); + assign n7200 = ~n8368; + assign n8370 = (Ng2987 & ~Ng3068) | (~Ng3049 & (~Ng2987 | ~Ng3068)); + assign n7196 = ~n8370; + assign n8372 = (Ng2987 & ~Ng3067) | (~Ng3048 & (~Ng2987 | ~Ng3067)); + assign n7192 = ~n8372; + assign n8374 = (Ng2987 & ~Ng3066) | (~Ng3047 & (~Ng2987 | ~Ng3066)); + assign n7188 = ~n8374; + assign n8376 = (Ng2987 & ~Ng3065) | (~Ng3046 & (~Ng2987 | ~Ng3065)); + assign n7184 = ~n8376; + assign n8378 = (Ng2987 & ~Ng3064) | (~Ng3045 & (~Ng2987 | ~Ng3064)); + assign n7180 = ~n8378; + assign n8380 = (Ng2987 & ~Ng3063) | (~Ng3044 & (~Ng2987 | ~Ng3063)); + assign n7176 = ~n8380; + assign n8382 = (Ng2987 & ~Ng3062) | (~Ng3043 & (~Ng2987 | ~Ng3062)); + assign n7172 = ~n8382; + assign n8384 = (Ng2987 & ~Ng2997) | (~Ng3061 & (~Ng2987 | ~Ng2997)); + assign n7250 = ~n8384; + assign n8386 = (Ng2987 & ~Ng3078) | (~Ng3060 & (~Ng2987 | ~Ng3078)); + assign n7246 = ~n8386; + assign n8388 = (Ng2987 & ~Ng3077) | (~Ng3059 & (~Ng2987 | ~Ng3077)); + assign n7242 = ~n8388; + assign n8390 = (Ng2987 & ~Ng3076) | (~Ng3058 & (~Ng2987 | ~Ng3076)); + assign n7238 = ~n8390; + assign n8392 = (Ng2987 & ~Ng3075) | (~Ng3057 & (~Ng2987 | ~Ng3075)); + assign n7234 = ~n8392; + assign n8394 = (Ng2879 & ~Ng2874) | (~Ng2200 & (~Ng2879 | ~Ng2874)); + assign n624_1 = ~n8394; + assign n8396 = (Ng2879 & ~Ng2978) | (~Ng2190 & (~Ng2879 | ~Ng2978)); + assign n634_1 = ~n8396; + assign n8398 = (Ng2879 & ~Ng2981) | (~Ng2195 & (~Ng2879 | ~Ng2981)); + assign n629_1 = ~n8398; + assign n8400 = (Ng2879 & ~Ng2975) | (~Ng2185 & (~Ng2879 | ~Ng2975)); + assign n639_1 = ~n8400; + assign n8402 = (Ng2879 & ~Ng2972) | (~Ng2180 & (~Ng2879 | ~Ng2972)); + assign n644_1 = ~n8402; + assign n8404 = (Ng2879 & ~Ng2969) | (~Ng2175 & (~Ng2879 | ~Ng2969)); + assign n649_1 = ~n8404; + assign n8406 = (Ng2879 & ~Ng2966) | (~Ng2170 & (~Ng2879 | ~Ng2966)); + assign n654_1 = ~n8406; + assign n8408 = (Ng2879 & ~Ng2963) | (~Ng2165 & (~Ng2879 | ~Ng2963)); + assign n659_1 = ~n8408; + assign n8410 = (Ng2879 & ~Ng2935) | (~Ng1471 & (~Ng2879 | ~Ng2935)); + assign n470_1 = ~n8410; + assign n8412 = (Ng2879 & ~Ng2938) | (~Ng1476 & (~Ng2879 | ~Ng2938)); + assign n465 = ~n8412; + assign n8414 = (Ng2879 & ~Ng2941) | (~Ng1481 & (~Ng2879 | ~Ng2941)); + assign n460_1 = ~n8414; + assign n8416 = (Ng2879 & ~Ng2944) | (~Ng1486 & (~Ng2879 | ~Ng2944)); + assign n455_1 = ~n8416; + assign n8418 = (Ng2879 & ~Ng2947) | (~Ng1491 & (~Ng2879 | ~Ng2947)); + assign n450_1 = ~n8418; + assign n8420 = (Ng2879 & ~Ng2953) | (~Ng1496 & (~Ng2879 | ~Ng2953)); + assign n445_1 = ~n8420; + assign n8422 = (Ng2879 & ~Ng2956) | (~Ng1501 & (~Ng2879 | ~Ng2956)); + assign n440_1 = ~n8422; + assign n8424 = (Ng2879 & ~Ng2959) | (~Ng1506 & (~Ng2879 | ~Ng2959)); + assign n435_1 = ~n8424; + assign n8426 = (~Ng1315 & ~Ng2704) | (~Ng2584 & (Ng1315 | ~Ng2704)); + assign n6642 = ~n8426; + assign n8428 = (Ng1315 & ~Ng2631) | (~Ng2584 & (~Ng1315 | ~Ng2631)); + assign n6254 = ~n8428; + assign n8430 = (Ng1315 & Ng2628) | (~Ng2631 & (~Ng1315 | Ng2628)); + assign n6249 = ~n8430; + assign n8432 = (~Ng1315 & ~Ng2010) | (~Ng1890 & (Ng1315 | ~Ng2010)); + assign n5135 = ~n8432; + assign n8434 = (Ng1315 & ~Ng1937) | (~Ng1890 & (~Ng1315 | ~Ng1937)); + assign n4747 = ~n8434; + assign n8436 = (Ng1315 & Ng1934) | (~Ng1937 & (~Ng1315 | Ng1934)); + assign n4742 = ~n8436; + assign n8438 = (~Ng1315 & ~Ng1316) | (~Ng1196 & (Ng1315 | ~Ng1316)); + assign n3641_1 = ~n8438; + assign n8440 = (Ng1315 & ~Ng1243) | (~Ng1196 & (~Ng1315 | ~Ng1243)); + assign n3240_1 = ~n8440; + assign n8442 = (Ng1315 & Ng1240) | (~Ng1243 & (~Ng1315 | Ng1240)); + assign n3235_1 = ~n8442; + assign n8444 = (~Ng1315 & ~Ng630) | (~Ng510 & (Ng1315 | ~Ng630)); + assign n2122_1 = ~n8444; + assign n8446 = (Ng1315 & ~Ng557) | (~Ng510 & (~Ng1315 | ~Ng557)); + assign n1734_1 = ~n8446; + assign n8448 = (Ng1315 & Ng554) | (~Ng557 & (~Ng1315 | Ng554)); + assign n1729_1 = ~n8448; + assign n8450 = n5054 | n5981; + assign n8451 = n5058_1 | n5955; + assign n8452 = ~n4978_1 & n5840; + assign n8453 = n5062 | ~n5840; + assign n8454 = ~n4982 & n5833_1; + assign n8455 = n5064 | ~n5833_1; + assign n8456 = (~Ng1315 | Ng2811) & (~\[1605] | Ng2812); + assign n8457 = n4948_1 & (~n8456 | (\[1603] & ~Ng2813)); + assign n8458 = (Ng2611 | n6476) & (n5072_1 | n5577); + assign n8459 = (n5072_1 | ~n5590_1) & (n6476 | Ng2610); + assign n8460 = (n5072_1 | ~n5587) & (n6476 | Ng2608); + assign n8461 = (n5072_1 | ~n5585_1) & (n6476 | Ng2607); + assign n8462 = (n5072_1 | ~n5579) & (n6476 | Ng2606); + assign n8463 = (n5072_1 | ~n5589) & (n6476 | Ng2605); + assign n8464 = (n5072_1 | ~n5583) & (n6476 | Ng2604); + assign n8465 = (n5072_1 | ~n5581) & (n6476 | Ng2603); + assign n8466 = (~Ng1315 | Ng2117) & (~\[1605] | Ng2118); + assign n8467 = n4936 & (~n8466 | (\[1603] & ~Ng2119)); + assign n8468 = (n5070 | ~n5573) & (n6478 | Ng1917); + assign n8469 = (n5070 | ~n5571) & (n6478 | Ng1916); + assign n8470 = (n5070 | ~n5568) & (n6478 | Ng1914); + assign n8471 = (n5070 | ~n5566) & (n6478 | Ng1913); + assign n8472 = (n5070 | ~n5560_1) & (n6478 | Ng1912); + assign n8473 = (n5070 | ~n5570_1) & (n6478 | Ng1911); + assign n8474 = (n5070 | ~n5564) & (n6478 | Ng1910); + assign n8475 = (n5070 | ~n5562) & (n6478 | Ng1909); + assign n8476 = (n6293 | n5853_1) & (n6294_1 | n6295); + assign n8477 = (n6295 | n5853_1) & (n6293 | n6296); + assign n8478 = (~n6296 | ~n8476) & (~n6294_1 | ~n8477); + assign n8479 = (n5847 | n6297) & (~n6298 | n6299_1); + assign n8480 = (n5847 | n6299_1) & (n6297 | n6300); + assign n8481 = (~n6300 | ~n8479) & (n6298 | ~n8480); + assign n8482 = (n6317_1 | n5873_1) & (n6318 | n6319); + assign n8483 = (n6319 | n5873_1) & (n6317_1 | n6320); + assign n8484 = (~n6320 | ~n8482) & (~n6318 | ~n8483); + assign n8485 = (n5867 | n6321_1) & (~n6322 | n6323); + assign n8486 = (n5867 | n6323) & (n6321_1 | n6324); + assign n8487 = (~n6324 | ~n8485) & (n6322 | ~n8486); + assign n8488 = (n6341_1 | n5893_1) & (n6342 | n6343); + assign n8489 = (n6343 | n5893_1) & (n6341_1 | n6344); + assign n8490 = (~n6344 | ~n8488) & (~n6342 | ~n8489); + assign n8491 = (n5887 | n6345_1) & (~n6346 | n6347); + assign n8492 = (n5887 | n6347) & (n6345_1 | n6348); + assign n8493 = (~n6348 | ~n8491) & (n6346 | ~n8492); + assign n8494 = (n6365 | n5913_1) & (n6366 | n6367); + assign n8495 = (n6367 | n5913_1) & (n6365 | n6368_1); + assign n8496 = (~n6368_1 | ~n8494) & (~n6366 | ~n8495); + assign n8497 = (n5907 | n6369) & (~n6370 | n6371); + assign n8498 = (n5907 | n6371) & (n6369 | n6372); + assign n8499 = (~n6372 | ~n8497) & (n6370 | ~n8498); + assign n8500 = (~Ng1315 | Ng1423) & (~\[1605] | Ng1424); + assign n8501 = n4932 | n4862 | n4798 | n4734 | n4712_1 | n4764; + assign n8502 = (n5068 | ~n5538) & (n6520_1 | Ng1223); + assign n8503 = (n5068 | ~n5536) & (n6520_1 | Ng1222); + assign n8504 = (n5068 | ~n5533) & (n6520_1 | Ng1220); + assign n8505 = (n5068 | ~n5531) & (n6520_1 | Ng1219); + assign n8506 = (n5068 | ~n5540_1) & (n6520_1 | Ng1218); + assign n8507 = (n5068 | ~n5535_1) & (n6520_1 | Ng1217); + assign n8508 = (n5068 | ~n5529) & (n6520_1 | Ng1216); + assign n8509 = (n5068 | ~n5526) & (n6520_1 | Ng1215); + assign n8510 = (~Ng1315 | Ng737) & (~\[1605] | Ng738); + assign n8511 = n4912 | n4820 | n4756_1 | n4704_1 | n4688_1 | n4728_1; + assign n8512 = (n5066 | ~n5518) & (n6526 | Ng537); + assign n8513 = (n5066 | ~n5516) & (n6526 | Ng536); + assign n8514 = (n5066 | ~n5513) & (n6526 | Ng534); + assign n8515 = (n5066 | ~n5511) & (n6526 | Ng533); + assign n8516 = (n5066 | ~n5520_1) & (n6526 | Ng532); + assign n8517 = (n5066 | ~n5515_1) & (n6526 | Ng531); + assign n8518 = (n5066 | ~n5509) & (n6526 | Ng530); + assign n8519 = (n5066 | ~n5522) & (n6526 | Ng529); + assign n8520 = n5028_1 | n4561 | n4571; + assign n8521 = n8520 & (n6552 | n6057_1); + assign n8522 = (~n5018_1 | n6051) & (~n4567 | n6552); + assign n8523 = n5016 | n4553 | n4565; + assign n8524 = n8523 & (n6557 | n6079); + assign n8525 = (~n5006 | n6073) & (~n4559_1 | n6557); + assign n8526 = n5004 | n4547 | n4557; + assign n8527 = n8526 & (n6561 | n6101); + assign n8528 = (~n4994 | n6095) & (~n4551 | n6561); + assign n8529 = n4992 | n4543 | n4549; + assign n8530 = n8529 & (n6565_1 | n6123); + assign n8531 = (~n4986 | n6117) & (~n4545 | n6565_1); + assign n8532 = n6531 | ~n8745; + assign n8533 = (~Ng853 | Ng2253) & (~\[1612] | Ng2254); + assign n8534 = (~Ng853 | Ng1559) & (~\[1612] | Ng1560); + assign n8535 = (~Ng853 | Ng865) & (~\[1612] | Ng866); + assign n8536 = (~Ng853 | Ng177) & (~\[1612] | Ng178); + assign n8537 = n6437 | n6435_1 | n6436; + assign n8538 = n6440_1 | n6441 | n6442 | n6443 | n6439 | n8537 | n6444 | n6438; + assign n8539 = ~Ng1315 | Ng2802; + assign n8540 = n6447 | n6445_1 | n6446; + assign n8541 = n6450_1 | n6451 | n6452 | n6453 | n6449 | n8540 | n6454 | n6448; + assign n8542 = ~Ng1315 | Ng2108; + assign n8543 = n6457 | n6455_1 | n6456; + assign n8544 = n6460_1 | n6461 | n6462 | n6463 | n6459 | n8543 | n6464 | n6458; + assign n8545 = ~Ng1315 | Ng1414; + assign n8546 = n6467 | n6465_1 | n6466; + assign n8547 = n6470_1 | n6471 | n6472 | n6473 | n6469 | n8546 | n6474 | n6468; + assign n8548 = ~Ng1315 | Ng728; + assign n8549 = n6522 & (Ng3139 | ~n8756); + assign n8550 = ~Ng548 | \[1605] | Ng8284; + assign n8551 = (~\[1605] & ~Ng1234) | (n6600 & (\[1605] | ~Ng1234)); + assign n8552 = (~\[1605] & ~Ng1928) | (n6601 & (\[1605] | ~Ng1928)); + assign n8553 = (~\[1605] & ~Ng2622) | (n6602_1 & (\[1605] | ~Ng2622)); + assign n8554 = (~n4776 & n8454) | (n4982 & (n4776 | n8454)); + assign n8555 = (~Pg3229 & Ng2615) | (Ng2612 & (Pg3229 | Ng2615)); + assign n8556 = n5649 ^ ~n5650_1; + assign n8557 = ~n8555 | Ng2631 | n6476; + assign n8558 = (~Pg3229 & Ng1921) | (Ng1918 & (Pg3229 | Ng1921)); + assign n8559 = n5637 ^ ~n5638; + assign n8560 = ~n8558 | Ng1937 | n6478; + assign n8561 = ~n4980 & (n6485_1 | (~n4643 & ~n5989)); + assign n8562 = n4976 & (n8561 | (n4980 & ~n6277)); + assign n8563 = ~n4976 & (n4970 | n5558); + assign n8564 = n4976 & ~n5558 & (~n4970 | n4980); + assign n8565 = ~n5445_1 | n8563 | n8564; + assign n8566 = ~n4974 & (n6495_1 | (~n4639 & ~n5997)); + assign n8567 = n4968_1 & (n8566 | (n4974 & ~n6278)); + assign n8568 = ~n4968_1 & (n4962 | n5556); + assign n8569 = n4968_1 & ~n5556 & (~n4962 | n4974); + assign n8570 = ~n5442 | n8568 | n8569; + assign n8571 = ~n4966 & (n6505_1 | (~n4633 & ~n6005)); + assign n8572 = n4960 & (n8571 | (n4966 & ~n6279)); + assign n8573 = ~n4960 & (n4956 | n5554); + assign n8574 = n4960 & ~n5554 & (~n4956 | n4966); + assign n8575 = ~n5439 | n8573 | n8574; + assign n8576 = ~n4958_1 & (n6515_1 | (~n4625 & ~n6013_1)); + assign n8577 = n4954 & (n8576 | (n4958_1 & ~n6280)); + assign n8578 = ~n4954 & (n4950 | n5552); + assign n8579 = n4954 & ~n5552 & (~n4950 | n4958_1); + assign n8580 = ~n5436 | n8578 | n8579; + assign n8581 = n4976 & (~n4980 | ~Ng2257 | n6483); + assign n8582 = n4968_1 & (~n4974 | ~Ng2257 | n6493); + assign n8583 = n4960 & (~n4966 | ~Ng2257 | n6503); + assign n8584 = n4954 & (~n4958_1 | ~Ng2257 | n6513); + assign n8585 = n4876_1 ^ ~n5928_1; + assign n8586 = n4720_1 ^ ~n5927; + assign n8587 = n4938_1 | n6488 | n6308_1; + assign n8588 = n8587 & (~n4938_1 | (~n6308_1 & ~n6488)); + assign n8589 = n4834_1 ^ ~n5935; + assign n8590 = n4696_1 ^ ~n5934; + assign n8591 = n4918 | n6498 | n6332; + assign n8592 = n8591 & (~n4918 | (~n6332 & ~n6498)); + assign n8593 = n4792_1 ^ ~n5942; + assign n8594 = n4676_1 ^ ~n5941; + assign n8595 = n4888_1 | n6508 | n6356; + assign n8596 = n8595 & (~n4888_1 | (~n6356 & ~n6508)); + assign n8597 = n4750 ^ ~n5949; + assign n8598 = n4662 ^ ~n5948_1; + assign n8599 = n4850 | n6518 | n6380; + assign n8600 = n8599 & (~n4850 | (~n6380 & ~n6518)); + assign n8601 = Ng506 | \[1603] | Pg16297; + assign n2064_1 = n8601 & (~Ng506 | Ng507); + assign n8603 = (\[1603] & n2064_1) | (Pg16355 & (~\[1603] | n2064_1)); + assign n3570_1 = (Ng1192 & Ng1193) | (n8603 & (~Ng1192 | Ng1193)); + assign n8605 = (\[1603] & n3570_1) | (Pg16399 & (~\[1603] | n3570_1)); + assign n8606 = (\[1603] & ~n5077) | (~Pg16437 & (~\[1603] | ~n5077)); + assign n8607 = Ng298 | Ng299; + assign n8608 = (~\[1594] & ~Ng992) | (n6934 & (\[1594] | ~Ng992)); + assign n8609 = (~\[1594] & ~Ng1686) | (n6936_1 & (\[1594] | ~Ng1686)); + assign n8610 = (~\[1594] & ~Ng2380) | (n6938 & (\[1594] | ~Ng2380)); + assign n8611 = (~Pg3229 & Ng1227) | (Ng1224 & (Pg3229 | Ng1227)); + assign n8612 = n5625_1 ^ ~n5626; + assign n8613 = ~n8611 | Ng1243 | n6520_1; + assign n8614 = ~n5445_1 | n5961; + assign n8615 = ~n5442 | n5964; + assign n8616 = ~n5439 | n5967; + assign n8617 = ~n5436 | n5970; + assign n8618 = (~Pg3229 & Ng541) | (Ng538 & (Pg3229 | Ng541)); + assign n8619 = n5613 ^ ~n5614; + assign n8620 = ~n8618 | Ng557 | n6526; + assign n8621 = n5034 ^ ~n5988_1; + assign n8622 = (n5990 & n6484) | (Ng2257 & (~n5990 | n6484)); + assign n8623 = Ng853 & n8622; + assign n8624 = \[1594] & n8622; + assign n8625 = \[1612] & n8622; + assign n8626 = n5022 ^ ~n5996; + assign n8627 = (n5998_1 & n6494) | (Ng2257 & (~n5998_1 | n6494)); + assign n8628 = Ng853 & n8627; + assign n8629 = \[1594] & n8627; + assign n8630 = \[1612] & n8627; + assign n8631 = n5010 ^ ~n6004; + assign n8632 = (n6006 & n6504) | (Ng2257 & (~n6006 | n6504)); + assign n8633 = Ng853 & n8632; + assign n8634 = \[1594] & n8632; + assign n8635 = \[1612] & n8632; + assign n8636 = n4998_1 ^ ~n6012; + assign n8637 = (n6014 & n6514) | (Ng2257 & (~n6014 | n6514)); + assign n8638 = Ng853 & n8637; + assign n8639 = \[1594] & n8637; + assign n8640 = \[1612] & n8637; + assign n8641 = n6020 | n5411; + assign n8642 = ~n5026 ^ ~n8641; + assign n8643 = n6024 | n5404; + assign n8644 = ~n5014 ^ ~n8643; + assign n8645 = n6028_1 | n5397; + assign n8646 = ~n5002 ^ ~n8645; + assign n8647 = n6032 | n5392; + assign n8648 = ~n4990 ^ ~n8647; + assign n8649 = n6555_1 | n4982; + assign n8650 = n8649 & (n6554 | ~n6555_1 | ~n7062); + assign n8651 = (n6555_1 & ~n7070) | (n5064 & (~n6555_1 | ~n7070)); + assign n8652 = n6555_1 | n4978_1; + assign n8653 = n8652 & (~n6555_1 | n6559 | ~n7078); + assign n8654 = (n6555_1 & ~n7086_1) | (n5062 & (~n6555_1 | ~n7086_1)); + assign n8655 = n6555_1 | n4972; + assign n8656 = n8655 & (~n6555_1 | n6563 | ~n7094); + assign n8657 = (n6555_1 & ~n7102) | (n5058_1 & (~n6555_1 | ~n7102)); + assign n8658 = n6555_1 | n4964; + assign n8659 = n8658 & (~n6555_1 | n6567 | ~n7110); + assign n8660 = (n6555_1 & ~n7118) | (n5054 & (~n6555_1 | ~n7118)); + assign n8661 = ~n4880_1 | n4908 | n6150; + assign n8662 = ~n4838_1 | n4870 | n6157; + assign n8663 = ~n4796_1 | n4828 | n6164; + assign n8664 = ~n4754 | n4786 | n6171_1; + assign n8665 = ~Ng1315 | n5156; + assign n8666 = n6048_1 & n8669; + assign n8667 = ~\[1603] | n5156; + assign n8668 = ~\[1605] | n5156; + assign n8669 = Pg3229 ^ ~n5008_1; + assign n8670 = ~n5008_1 & n5036 & (n5018_1 | ~n5028_1); + assign n8671 = Ng853 & n5138; + assign n8672 = n4906 & n4926 & n6389; + assign n8673 = \[1594] & n5138; + assign n8674 = \[1612] & n5138; + assign n8675 = ~n4878 & n4940 & (n4906 | ~n4926); + assign n8676 = ~Ng1315 | n5149; + assign n8677 = n6070 & n8680; + assign n8678 = ~\[1603] | n5149; + assign n8679 = ~\[1605] | n5149; + assign n8680 = Pg3229 ^ ~n4996; + assign n8681 = ~n4996 & n5024 & (n5006 | ~n5016); + assign n8682 = Ng853 & n5136; + assign n8683 = n4868 & n4896 & n6390; + assign n8684 = \[1594] & n5136; + assign n8685 = \[1612] & n5136; + assign n8686 = ~n4836 & n4920 & (n4868 | ~n4896); + assign n8687 = ~Ng1315 | n5147; + assign n8688 = n6092 & n8691; + assign n8689 = ~\[1603] | n5147; + assign n8690 = ~\[1605] | n5147; + assign n8691 = Pg3229 ^ ~n4988_1; + assign n8692 = ~n4988_1 & n5012 & (n4994 | ~n5004); + assign n8693 = Ng853 & n5132; + assign n8694 = n4826 & n4858 & n6391_1; + assign n8695 = \[1594] & n5132; + assign n8696 = \[1612] & n5132; + assign n8697 = ~n4794 & n4890 & (n4826 | ~n4858); + assign n8698 = ~Ng1315 | n5142; + assign n8699 = n6114 & n8702; + assign n8700 = ~\[1603] | n5142; + assign n8701 = ~\[1605] | n5142; + assign n8702 = Pg3229 ^ ~n4984; + assign n8703 = ~n4984 & n5000 & (n4986 | ~n4992); + assign n8704 = Ng853 & n5128; + assign n8705 = n4784 & n4816 & n6392; + assign n8706 = \[1594] & n5128; + assign n8707 = \[1612] & n5128; + assign n8708 = ~n4752_1 & n4852 & (n4784 | ~n4816); + assign n8709 = n4908 ^ ~n8755; + assign n8710 = n4880_1 ^ ~n8757; + assign n8711 = n4870 ^ ~n8754; + assign n8712 = n4838_1 ^ ~n8758; + assign n8713 = n4828 ^ ~n8753; + assign n8714 = n4796_1 ^ ~n8759; + assign n8715 = n4786 ^ ~n8752; + assign n8716 = n4754 ^ ~n8760; + assign n8717 = ~Ng2584 | ~n4581 | ~n4982; + assign n8718 = ~Ng853 | ~Ng2257; + assign n8719 = n4615 & ~n5989; + assign n8720 = ~\[1594] | ~Ng2257; + assign n8721 = ~\[1612] | ~Ng2257; + assign n8722 = ~Ng1890 | ~n4579 | ~n4978_1; + assign n8723 = n4603 & ~n5997; + assign n8724 = ~Ng1196 | ~n4577_1 | ~n4972; + assign n8725 = n4593 & ~n6005; + assign n8726 = ~Ng510 | ~n4575 | ~n4964; + assign n8727 = n4585 & ~n6013_1; + assign n8728 = Ng13475 ^ ~Ng2993; + assign n8729 = ~Ng853 | n6576; + assign n8730 = ~\[1594] | n6576; + assign n8731 = ~\[1612] | n6576; + assign n8732 = ~Ng2185 | Ng2190 | Ng2195 | ~Ng2200; + assign n8733 = ~Ng1491 | Ng1496 | Ng1501 | ~Ng1506; + assign n8734 = ~Ng801 | Ng805 | Ng809 | ~Ng813; + assign n8735 = ~Ng113 | Ng117 | Ng121 | ~Ng125; + assign n8736 = n6555_1 | n6064; + assign n8737 = n6555_1 | n5084; + assign n8738 = n6242 & n5230_1; + assign n8739 = n6555_1 | n6086; + assign n8740 = n6555_1 | n5081; + assign n8741 = n6555_1 | n6108; + assign n8742 = n6555_1 | n5078; + assign n8743 = n6555_1 | n6130; + assign n8744 = n6555_1 | n5075; + assign n8745 = Ng2985 | Ng2984; + assign n8746 = ~Ng3147 & (~n8549 | (~Ng3120 & n8745)); + assign n8747 = ~\[1594] | ~Ng2257; + assign n8748 = ~\[1612] | ~Ng2257; + assign n8749 = n6595 ^ ~n8761; + assign n8750 = Ng3006 | Ng3010 | Ng3024 | Ng3002 | Ng3013; + assign n5815 = ~n6576; + assign n8752 = n4583 | ~Ng2257 | n6571; + assign n8753 = n4591_1 | ~Ng2257 | n6570_1; + assign n8754 = n4601 | ~Ng2257 | n6569; + assign n8755 = n4613_1 | ~Ng2257 | n6568; + assign n8756 = Ng2991 | Ng2992; + assign n8757 = ~Ng2257 | n6585; + assign n8758 = ~Ng2257 | n6586; + assign n8759 = ~Ng2257 | n6587_1; + assign n8760 = ~Ng2257 | n6588; + assign n8761 = Pg3231 | ~Ng3139; + assign n8762 = Pg3231 | ~Ng3120; + assign n8763 = ~n6597_1 ^ ~n8761; + assign n8764 = ~n6389 & n4906 & n4940; + assign n8765 = ~n6390 & n4868 & n4920; + assign n8766 = ~n6391_1 & n4826 & n4890; + assign n8767 = ~n6392 & n4784 & n4852; + assign Pg25442 = n858_1; + assign Pg25420 = n858_1; + assign Pg8167 = \[1594] ; + assign Pg8106 = \[1605] ; + assign Pg8087 = \[1612] ; + assign Pg8082 = \[1594] ; + assign Pg8030 = \[1603] ; + assign Pg8012 = \[1612] ; + assign Pg8007 = \[1594] ; + assign Pg7961 = \[1612] ; + assign Pg7956 = \[1594] ; + assign Pg7909 = \[1612] ; + assign Pg7487 = \[1603] ; + assign Pg7425 = \[1605] ; + assign Pg7390 = \[1603] ; + assign Pg7357 = \[1603] ; + assign Pg7302 = \[1605] ; + assign Pg7264 = \[1594] ; + assign Pg7229 = \[1605] ; + assign Pg7194 = \[1603] ; + assign Pg7161 = \[1603] ; + assign Pg7084 = \[1594] ; + assign Pg7052 = \[1605] ; + assign Pg7014 = \[1594] ; + assign Pg6979 = \[1605] ; + assign Pg6944 = \[1603] ; + assign Pg6911 = \[1603] ; + assign Pg6837 = \[1612] ; + assign Pg6782 = \[1594] ; + assign Pg6750 = \[1605] ; + assign Pg6712 = \[1594] ; + assign Pg6677 = \[1605] ; + assign Pg6642 = \[1603] ; + assign Pg6573 = \[1612] ; + assign Pg6518 = \[1594] ; + assign Pg6485 = \[1605] ; + assign Pg6447 = \[1594] ; + assign Pg6368 = \[1612] ; + assign Pg6313 = \[1594] ; + assign Pg6231 = \[1612] ; + assign Pg5796 = \[1603] ; + assign Pg5747 = \[1605] ; + assign Pg5738 = \[1603] ; + assign Pg5695 = \[1605] ; + assign Pg5686 = \[1603] ; + assign Pg5657 = \[1605] ; + assign Pg5648 = \[1603] ; + assign Pg5637 = \[1609] ; + assign Pg5629 = \[1605] ; + assign Pg5612 = \[1609] ; + assign Pg5595 = \[1609] ; + assign Pg5555 = \[1612] ; + assign Pg5549 = \[1609] ; + assign Pg5511 = \[1612] ; + assign Pg5472 = \[1612] ; + assign Pg5437 = \[1612] ; + assign n270_1 = Pg51; + assign n353_1 = Pg8021; + assign n362_1 = Pg3212; + assign n366_1 = Pg3228; + assign n370_1 = Pg3227; + assign n374_1 = Pg3226; + assign n378_1 = Pg3225; + assign n382_1 = Pg3224; + assign n386 = Pg3223; + assign n390_1 = Pg3222; + assign n394 = Pg3221; + assign n398_1 = Pg3232; + assign n402_1 = Pg3220; + assign n406 = Pg3219; + assign n410_1 = Pg3218; + assign n414_1 = Pg3217; + assign n418_1 = Pg3216; + assign n422_1 = Pg3215; + assign n426_1 = Pg3214; + assign n430_1 = Pg3213; + assign n483_1 = Pg8251; + assign n491_1 = Pg4090; + assign n499_1 = Pg4323; + assign n507 = Pg4590; + assign n515_1 = Pg6225; + assign n523_1 = Pg6442; + assign n531_1 = Pg6895; + assign n539_1 = Pg7334; + assign n547_1 = Pg7519; + assign n555_1 = Pg8249; + assign n563_1 = Pg4088; + assign n571_1 = Pg4321; + assign n579 = Pg8023; + assign n587_1 = Pg8175; + assign n595_1 = Pg3993; + assign n603_1 = Pg4200; + assign n611_1 = Pg4450; + assign n619_1 = Pg8096; + assign n848_1 = Pg24734; + assign n872_1 = Pg26104; + assign n876_1 = Pg25435; + assign n880_1 = Pg27380; + assign n884_1 = Pg26149; + assign n888_1 = Pg26135; + assign n1537_1 = Ng450; + assign n1546_1 = Ng452; + assign n1555_1 = Ng454; + assign n1564 = Ng280; + assign n1573 = Ng282; + assign n1582_1 = Ng284; + assign n1591 = Ng286; + assign n1600_1 = Ng288; + assign n1604_1 = Ng13407; + assign n1608 = Ng290; + assign n1627_1 = Ng11497; + assign n1631 = Ng342; + assign n1635 = Ng11498; + assign n1639_1 = Ng350; + assign n1643 = Ng11499; + assign n1647_1 = Ng352; + assign n1651 = Ng11500; + assign n1655 = Ng357; + assign n1659_1 = Ng11501; + assign n1663_1 = Ng365; + assign n1667 = Ng11502; + assign n1671_1 = Ng367; + assign n1675_1 = Ng11503; + assign n1679_1 = Ng372; + assign n1683_1 = Ng11504; + assign n1687_1 = Ng380; + assign n1691_1 = Ng11505; + assign n1695 = Ng382; + assign n1699_1 = Ng11506; + assign n1703 = Ng387; + assign n1707 = Ng11507; + assign n1711_1 = Ng395; + assign n1715 = Ng11508; + assign n1719 = Ng397; + assign n1743 = Ng513; + assign n1747 = Ng523; + assign n1752_1 = Ng11512; + assign n1756 = Ng564; + assign n1761_1 = Ng11515; + assign n1765 = Ng570; + assign n1770_1 = Ng11516; + assign n1774_1 = Ng572; + assign n1779_1 = Ng11517; + assign n1783_1 = Ng574; + assign n1788 = Ng11513; + assign n1792_1 = Ng566; + assign n1797_1 = Ng11514; + assign n1801_1 = Ng568; + assign n1879_1 = Ng528; + assign n1883_1 = Ng535; + assign n1892 = Ng543; + assign n1906_1 = Ng549; + assign n1915_1 = Ng558; + assign n2054_1 = Ng8284; + assign n2067 = Pg16297; + assign n2391 = Ng13457; + assign n2395_1 = \[1612] ; + assign n2399 = \[1594] ; + assign n3043_1 = Ng1137; + assign n3052_1 = Ng1139; + assign n3061_1 = Ng1141; + assign n3070 = Ng967; + assign n3079_1 = Ng969; + assign n3088_1 = Ng971; + assign n3097_1 = Ng973; + assign n3106_1 = Ng975; + assign n3110_1 = Ng13423; + assign n3114_1 = Ng977; + assign n3133_1 = Ng11524; + assign n3137_1 = Ng1029; + assign n3141_1 = Ng11525; + assign n3145_1 = Ng1037; + assign n3149_1 = Ng11526; + assign n3153_1 = Ng1039; + assign n3157_1 = Ng11527; + assign n3161_1 = Ng1044; + assign n3165_1 = Ng11528; + assign n3169_1 = Ng1052; + assign n3173_1 = Ng11529; + assign n3177_1 = Ng1054; + assign n3181_1 = Ng11530; + assign n3185_1 = Ng1059; + assign n3189_1 = Ng11531; + assign n3193_1 = Ng1067; + assign n3197_1 = Ng11532; + assign n3201_1 = Ng1069; + assign n3205_1 = Ng11533; + assign n3209_1 = Ng1074; + assign n3213_1 = Ng11534; + assign n3217_1 = Ng1082; + assign n3221_1 = Ng11535; + assign n3225_1 = Ng1084; + assign n3249_1 = Ng1199; + assign n3253_1 = Ng1209; + assign n3258_1 = Ng11539; + assign n3262_1 = Ng1250; + assign n3267_1 = Ng11542; + assign n3271_1 = Ng1256; + assign n3276_1 = Ng11543; + assign n3280_1 = Ng1258; + assign n3285_1 = Ng11544; + assign n3289_1 = Ng1260; + assign n3294_1 = Ng11540; + assign n3298_1 = Ng1252; + assign n3303_1 = Ng11541; + assign n3307_1 = Ng1254; + assign n3385_1 = Ng1214; + assign n3389_1 = Ng1221; + assign n3398_1 = Ng1229; + assign n3412_1 = Ng1235; + assign n3421_1 = Ng1244; + assign n3560_1 = Ng8293; + assign n3573_1 = Pg16355; + assign n3628_1 = Ng13475; + assign n3632_1 = \[1605] ; + assign n3636_1 = \[1603] ; + assign n4550 = Ng1831; + assign n4559 = Ng1833; + assign n4568 = Ng1835; + assign n4577 = Ng1661; + assign n4586 = Ng1663; + assign n4595 = Ng1665; + assign n4604 = Ng1667; + assign n4613 = Ng1669; + assign n4617 = Ng13439; + assign n4621 = Ng1671; + assign n4640 = Ng11551; + assign n4644_1 = Ng1723; + assign n4648 = Ng11552; + assign n4652 = Ng1731; + assign n4656 = Ng11553; + assign n4660 = Ng1733; + assign n4664 = Ng11554; + assign n4668 = Ng1738; + assign n4672 = Ng11555; + assign n4676 = Ng1746; + assign n4680 = Ng11556; + assign n4684 = Ng1748; + assign n4688 = Ng11557; + assign n4692 = Ng1753; + assign n4696 = Ng11558; + assign n4700 = Ng1761; + assign n4704 = Ng11559; + assign n4708 = Ng1763; + assign n4712 = Ng11560; + assign n4716 = Ng1768; + assign n4720 = Ng11561; + assign n4724 = Ng1776; + assign n4728 = Ng11562; + assign n4732 = Ng1778; + assign n4756 = Ng1893; + assign n4760 = Ng1903; + assign n4765 = Ng11566; + assign n4769 = Ng1944; + assign n4774 = Ng11569; + assign n4778 = Ng1950; + assign n4783 = Ng11570; + assign n4787 = Ng1952; + assign n4792 = Ng11571; + assign n4796 = Ng1954; + assign n4801 = Ng11567; + assign n4805 = Ng1946; + assign n4810 = Ng11568; + assign n4814 = Ng1948; + assign n4892 = Ng1908; + assign n4896_1 = Ng1915; + assign n4905_1 = Ng1923; + assign n4919 = Ng1929; + assign n4928 = Ng1938; + assign n5067 = Ng8302; + assign n5080 = Pg16399; + assign n5819 = Ng2256; + assign n5823 = \[1609] ; + assign n6057 = Ng2525; + assign n6066 = Ng2527; + assign n6075 = Ng2529; + assign n6084 = Ng2355; + assign n6093 = Ng2357; + assign n6102 = Ng2359; + assign n6111 = Ng2361; + assign n6120 = Ng2363; + assign n6124 = Ng13455; + assign n6128 = Ng2365; + assign n6147 = Ng11578; + assign n6151 = Ng2417; + assign n6155 = Ng11579; + assign n6159 = Ng2425; + assign n6163 = Ng11580; + assign n6167 = Ng2427; + assign n6171 = Ng11581; + assign n6175 = Ng2432; + assign n6179 = Ng11582; + assign n6183 = Ng2440; + assign n6187 = Ng11583; + assign n6191 = Ng2442; + assign n6195 = Ng11584; + assign n6199 = Ng2447; + assign n6203 = Ng11585; + assign n6207 = Ng2455; + assign n6211 = Ng11586; + assign n6215 = Ng2457; + assign n6219 = Ng11587; + assign n6223 = Ng2462; + assign n6227 = Ng11588; + assign n6231 = Ng2470; + assign n6235 = Ng11589; + assign n6239 = Ng2472; + assign n6263 = Ng2587; + assign n6267 = Ng2597; + assign n6272 = Ng11593; + assign n6276 = Ng2638; + assign n6281 = Ng11596; + assign n6285 = Ng2644; + assign n6290 = Ng11597; + assign n6294 = Ng2646; + assign n6299 = Ng11598; + assign n6303 = Ng2648; + assign n6308 = Ng11594; + assign n6312 = Ng2640; + assign n6317 = Ng11595; + assign n6321 = Ng2642; + assign n6399 = Ng2602; + assign n6403 = Ng2609; + assign n6412 = Ng2617; + assign n6426 = Ng2623; + assign n6435 = Ng2632; + assign n6574 = Ng8311; + assign n6587 = Pg16437; + assign n7160 = Pg3234; + assign n7163 = Pg5388; + assign n7167 = Pg16496; + always @ (posedge clock) begin + Pg8021 <= n270_1; + Ng2817 <= n274_1; + Ng2933 <= n279_1; + Ng13457 <= n284_1; + Ng2883 <= n289_1; + Ng2888 <= n294_1; + Ng2896 <= n299_1; + Ng2892 <= n304_1; + Ng2903 <= n309_1; + Ng2900 <= n314_1; + Ng2908 <= n319_1; + Ng2912 <= n324_1; + Ng2917 <= n329; + Ng2924 <= n334_1; + Ng2920 <= n339; + Ng2984 <= n344; + Ng2985 <= n349_1; + Ng2929 <= n353_1; + Ng2879 <= n358_1; + Ng2934 <= n362_1; + Ng2935 <= n366_1; + Ng2938 <= n370_1; + Ng2941 <= n374_1; + Ng2944 <= n378_1; + Ng2947 <= n382_1; + Ng2953 <= n386; + Ng2956 <= n390_1; + Ng2959 <= n394; + Ng2962 <= n398_1; + Ng2963 <= n402_1; + Ng2966 <= n406; + Ng2969 <= n410_1; + Ng2972 <= n414_1; + Ng2975 <= n418_1; + Ng2978 <= n422_1; + Ng2981 <= n426_1; + Ng2874 <= n430_1; + Ng1506 <= n435_1; + Ng1501 <= n440_1; + Ng1496 <= n445_1; + Ng1491 <= n450_1; + Ng1486 <= n455_1; + Ng1481 <= n460_1; + Ng1476 <= n465; + Ng1471 <= n470_1; + Ng13439 <= n475_1; + Pg8251 <= n480_1; + Ng813 <= n483_1; + Pg4090 <= n488_1; + Ng809 <= n491_1; + Pg4323 <= n496_1; + Ng805 <= n499_1; + Pg4590 <= n504_1; + Ng801 <= n507; + Pg6225 <= n512_1; + Ng797 <= n515_1; + Pg6442 <= n520_1; + Ng793 <= n523_1; + Pg6895 <= n528_1; + Ng789 <= n531_1; + Pg7334 <= n536_1; + Ng785 <= n539_1; + Pg7519 <= n544_1; + Ng13423 <= n547_1; + Pg8249 <= n552_1; + Ng125 <= n555_1; + Pg4088 <= n560_1; + Ng121 <= n563_1; + Pg4321 <= n568_1; + Ng117 <= n571_1; + Pg8023 <= n576_1; + Ng113 <= n579; + Pg8175 <= n584_1; + Ng109 <= n587_1; + Pg3993 <= n592_1; + Ng105 <= n595_1; + Pg4200 <= n600_1; + Ng101 <= n603_1; + Pg4450 <= n608_1; + Ng97 <= n611_1; + Pg8096 <= n616; + Ng13407 <= n619_1; + Ng2200 <= n624_1; + Ng2195 <= n629_1; + Ng2190 <= n634_1; + Ng2185 <= n639_1; + Ng2180 <= n644_1; + Ng2175 <= n649_1; + Ng2170 <= n654_1; + Ng2165 <= n659_1; + Ng13455 <= n664_1; + Ng3210 <= n669_1; + Ng3211 <= n674; + Ng3084 <= n679_1; + Ng3085 <= n684_1; + Ng3086 <= n689_1; + Ng3087 <= n694; + Ng3091 <= n699_1; + Ng3092 <= n704_1; + Ng3093 <= n709_1; + Ng3094 <= n714_1; + Ng3095 <= n719_1; + Ng3096 <= n724_1; + Ng3097 <= n729; + Ng3098 <= n734_1; + Ng3099 <= n739_1; + Ng3100 <= n744_1; + Ng3101 <= n749_1; + Ng3102 <= n754_1; + Ng3103 <= n759_1; + Ng3104 <= n764_1; + Ng3105 <= n769_1; + Ng3106 <= n774; + Ng3107 <= n779; + Ng3108 <= n784_1; + Ng3155 <= n789_1; + Ng3158 <= n794_1; + Ng3161 <= n799_1; + Ng3164 <= n804_1; + Ng3167 <= n809_1; + Ng3170 <= n814_1; + Ng3173 <= n819_1; + Ng3176 <= n824_1; + Ng3179 <= n829_1; + Ng3182 <= n834_1; + Ng3185 <= n839_1; + Ng3088 <= n844_1; + Ng3191 <= n848_1; + Ng3128 <= n853_1; + Ng3126 <= n858_1; + Ng3125 <= n863_1; + Ng3123 <= n868_1; + Ng3120 <= n872_1; + Ng3110 <= n876_1; + Ng3139 <= n880_1; + Ng3135 <= n884_1; + Ng3147 <= n888_1; + Ng185 <= n893_1; + Ng130 <= n898_1; + Ng131 <= n903_1; + Ng129 <= n908_1; + Ng133 <= n913_1; + Ng134 <= n918_1; + Ng132 <= n923_1; + Ng142 <= n928; + Ng143 <= n933_1; + Ng141 <= n938_1; + Ng145 <= n943_1; + Ng146 <= n948_1; + Ng144 <= n953_1; + Ng148 <= n958; + Ng149 <= n963_1; + Ng147 <= n968_1; + Ng151 <= n973_1; + Ng152 <= n978_1; + Ng150 <= n983_1; + Ng154 <= n988_1; + Ng155 <= n993_1; + Ng153 <= n998; + Ng157 <= n1003; + Ng158 <= n1008_1; + Ng156 <= n1013_1; + Ng160 <= n1018; + Ng161 <= n1023_1; + Ng159 <= n1028_1; + Ng163 <= n1033; + Ng164 <= n1038_1; + Ng162 <= n1043_1; + Ng169 <= n1048; + Ng170 <= n1053; + Ng168 <= n1058_1; + Ng172 <= n1063; + Ng173 <= n1068_1; + Ng171 <= n1073_1; + Ng175 <= n1078_1; + Ng176 <= n1083_1; + Ng174 <= n1088_1; + Ng178 <= n1093_1; + Ng179 <= n1098_1; + Ng177 <= n1103_1; + Ng186 <= n1108; + Ng189 <= n1113_1; + Ng192 <= n1118_1; + Ng231 <= n1123_1; + Ng234 <= n1128_1; + Ng237 <= n1133_1; + Ng195 <= n1138_1; + Ng198 <= n1143_1; + Ng201 <= n1148_1; + Ng240 <= n1153_1; + Ng243 <= n1158_1; + Ng246 <= n1163_1; + Ng204 <= n1168_1; + Ng207 <= n1173_1; + Ng210 <= n1178; + Ng249 <= n1183_1; + Ng252 <= n1188_1; + Ng255 <= n1193_1; + Ng213 <= n1198_1; + Ng216 <= n1203_1; + Ng219 <= n1208_1; + Ng258 <= n1213_1; + Ng261 <= n1218_1; + Ng264 <= n1223_1; + Ng222 <= n1228_1; + Ng225 <= n1233_1; + Ng228 <= n1238_1; + Ng267 <= n1243_1; + Ng270 <= n1248_1; + Ng273 <= n1253_1; + Ng92 <= n1258_1; + Ng88 <= n1263_1; + Ng83 <= n1268; + Ng79 <= n1273_1; + Ng74 <= n1278; + Ng70 <= n1283_1; + Ng65 <= n1288; + Ng61 <= n1293_1; + Ng56 <= n1298; + Ng52 <= n1303; + Ng11497 <= n1308_1; + Ng11498 <= n1313; + Ng11499 <= n1318; + Ng11500 <= n1323_1; + Ng11501 <= n1328_1; + Ng11502 <= n1333_1; + Ng11503 <= n1338_1; + Ng11504 <= n1343_1; + Ng11505 <= n1348; + Ng11506 <= n1353; + Ng11507 <= n1358_1; + Ng11508 <= n1363_1; + Ng408 <= n1368; + Ng411 <= n1373_1; + Ng414 <= n1378_1; + Ng417 <= n1383; + Ng420 <= n1388; + Ng423 <= n1393; + Ng427 <= n1398_1; + Ng428 <= n1403; + Ng426 <= n1408_1; + Ng429 <= n1413; + Ng432 <= n1418_1; + Ng435 <= n1423_1; + Ng438 <= n1428_1; + Ng441 <= n1433_1; + Ng444 <= n1438_1; + Ng448 <= n1443_1; + Ng449 <= n1448_1; + Ng447 <= n1453; + Ng312 <= n1458_1; + Ng313 <= n1463_1; + Ng314 <= n1468_1; + Ng315 <= n1473_1; + Ng316 <= n1478_1; + Ng317 <= n1483_1; + Ng318 <= n1488_1; + Ng319 <= n1493; + Ng320 <= n1498; + Ng322 <= n1503; + Ng323 <= n1508; + Ng321 <= n1513_1; + Ng403 <= n1518_1; + Ng404 <= n1523_1; + Ng402 <= n1528; + Ng450 <= n1533_1; + Ng451 <= n1537_1; + Ng452 <= n1542_1; + Ng453 <= n1546_1; + Ng454 <= n1551_1; + Ng279 <= n1555_1; + Ng280 <= n1560_1; + Ng281 <= n1564; + Ng282 <= n1569_1; + Ng283 <= n1573; + Ng284 <= n1578; + Ng285 <= n1582_1; + Ng286 <= n1587; + Ng287 <= n1591; + Ng288 <= n1596; + Ng289 <= n1600_1; + Ng290 <= n1604_1; + Ng291 <= n1608; + Ng299 <= n1613; + Ng305 <= n1618_1; + Ng298 <= n1623_1; + Ng342 <= n1627_1; + Ng349 <= n1631; + Ng350 <= n1635; + Ng351 <= n1639_1; + Ng352 <= n1643; + Ng353 <= n1647_1; + Ng357 <= n1651; + Ng364 <= n1655; + Ng365 <= n1659_1; + Ng366 <= n1663_1; + Ng367 <= n1667; + Ng368 <= n1671_1; + Ng372 <= n1675_1; + Ng379 <= n1679_1; + Ng380 <= n1683_1; + Ng381 <= n1687_1; + Ng382 <= n1691_1; + Ng383 <= n1695; + Ng387 <= n1699_1; + Ng394 <= n1703; + Ng395 <= n1707; + Ng396 <= n1711_1; + Ng397 <= n1715; + Ng324 <= n1719; + Ng554 <= n1724_1; + Ng557 <= n1729_1; + Ng510 <= n1734_1; + Ng513 <= n1739_1; + Ng523 <= n1743; + Ng524 <= n1747; + Ng564 <= n1752_1; + Ng569 <= n1756; + Ng570 <= n1761_1; + Ng571 <= n1765; + Ng572 <= n1770_1; + Ng573 <= n1774_1; + Ng574 <= n1779_1; + Ng565 <= n1783_1; + Ng566 <= n1788; + Ng567 <= n1792_1; + Ng568 <= n1797_1; + Ng489 <= n1801_1; + Ng486 <= n1806_1; + Ng487 <= n1811_1; + Ng488 <= n1816_1; + Ng11512 <= n1821_1; + Ng11515 <= n1825_1; + Ng11516 <= n1829; + Ng477 <= n1833; + Ng478 <= n1838; + Ng479 <= n1843_1; + Ng480 <= n1848; + Ng484 <= n1853_1; + Ng464 <= n1858_1; + Ng11517 <= n1863; + Ng11513 <= n1867_1; + Ng11514 <= n1871_1; + Ng528 <= n1875_1; + Ng535 <= n1879_1; + Ng542 <= n1883_1; + Ng543 <= n1888; + Ng544 <= n1892; + Ng548 <= n1897_1; + Ng549 <= n1902_1; + Ng8284 <= n1906_1; + Ng558 <= n1911_1; + Ng559 <= n1915_1; + Ng576 <= n1920_1; + Ng577 <= n1925; + Ng575 <= n1930_1; + Ng579 <= n1935_1; + Ng580 <= n1940_1; + Ng578 <= n1945_1; + Ng582 <= n1950; + Ng583 <= n1955; + Ng581 <= n1960_1; + Ng585 <= n1965; + Ng586 <= n1970_1; + Ng584 <= n1975; + Ng587 <= n1980; + Ng590 <= n1985; + Ng593 <= n1990_1; + Ng596 <= n1995_1; + Ng599 <= n2000_1; + Ng602 <= n2005_1; + Ng614 <= n2010; + Ng617 <= n2015_1; + Ng620 <= n2020_1; + Ng605 <= n2025_1; + Ng608 <= n2030; + Ng611 <= n2035_1; + Ng490 <= n2040; + Ng493 <= n2045_1; + Ng496 <= n2050_1; + Ng506 <= n2054_1; + Ng507 <= n2059_1; + Pg16297 <= n2064_1; + Ng525 <= n2067; + Ng529 <= n2072_1; + Ng530 <= n2077_1; + Ng531 <= n2082; + Ng532 <= n2087_1; + Ng533 <= n2092_1; + Ng534 <= n2097_1; + Ng536 <= n2102_1; + Ng537 <= n2107_1; + Ng538 <= n2112; + Ng541 <= n2117_1; + Ng630 <= n2122_1; + Ng659 <= n2127_1; + Ng640 <= n2132; + Ng633 <= n2137; + Ng653 <= n2142_1; + Ng646 <= n2147_1; + Ng660 <= n2152_1; + Ng672 <= n2157_1; + Ng666 <= n2162_1; + Ng679 <= n2167_1; + Ng686 <= n2172_1; + Ng692 <= n2177; + Ng699 <= n2182_1; + Ng700 <= n2187_1; + Ng698 <= n2192_1; + Ng702 <= n2197; + Ng703 <= n2202; + Ng701 <= n2207_1; + Ng705 <= n2212_1; + Ng706 <= n2217_1; + Ng704 <= n2222; + Ng708 <= n2227_1; + Ng709 <= n2232; + Ng707 <= n2237_1; + Ng711 <= n2242; + Ng712 <= n2247_1; + Ng710 <= n2252; + Ng714 <= n2257_1; + Ng715 <= n2262; + Ng713 <= n2267; + Ng717 <= n2272; + Ng718 <= n2277; + Ng716 <= n2282; + Ng720 <= n2287; + Ng721 <= n2292; + Ng719 <= n2297_1; + Ng723 <= n2302; + Ng724 <= n2307; + Ng722 <= n2312; + Ng726 <= n2317; + Ng727 <= n2322; + Ng725 <= n2327_1; + Ng729 <= n2332_1; + Ng730 <= n2337; + Ng728 <= n2342; + Ng732 <= n2347; + Ng733 <= n2352; + Ng731 <= n2357; + Ng735 <= n2362_1; + Ng736 <= n2367_1; + Ng734 <= n2372; + Ng738 <= n2377; + Ng739 <= n2382; + Ng737 <= n2387; + \[1612] <= n2391; + \[1594] <= n2395_1; + Ng853 <= n2399; + Ng818 <= n2404; + Ng819 <= n2409; + Ng817 <= n2414; + Ng821 <= n2419; + Ng822 <= n2424_1; + Ng820 <= n2429_1; + Ng830 <= n2434; + Ng831 <= n2439; + Ng829 <= n2444_1; + Ng833 <= n2449; + Ng834 <= n2454; + Ng832 <= n2459; + Ng836 <= n2464; + Ng837 <= n2469; + Ng835 <= n2474; + Ng839 <= n2479; + Ng840 <= n2484; + Ng838 <= n2489_1; + Ng842 <= n2494; + Ng843 <= n2499_1; + Ng841 <= n2504_1; + Ng845 <= n2509; + Ng846 <= n2514_1; + Ng844 <= n2519_1; + Ng848 <= n2524_1; + Ng849 <= n2529; + Ng847 <= n2534_1; + Ng851 <= n2539; + Ng852 <= n2544; + Ng850 <= n2549; + Ng857 <= n2554; + Ng858 <= n2559; + Ng856 <= n2564; + Ng860 <= n2569; + Ng861 <= n2574; + Ng859 <= n2579; + Ng863 <= n2584_1; + Ng864 <= n2589; + Ng862 <= n2594; + Ng866 <= n2599_1; + Ng867 <= n2604; + Ng865 <= n2609; + Ng873 <= n2614; + Ng876 <= n2619_1; + Ng879 <= n2624; + Ng918 <= n2629; + Ng921 <= n2634; + Ng924 <= n2639; + Ng882 <= n2644; + Ng885 <= n2649; + Ng888 <= n2654; + Ng927 <= n2659; + Ng930 <= n2664; + Ng933 <= n2669; + Ng891 <= n2674; + Ng894 <= n2679; + Ng897 <= n2684; + Ng936 <= n2689; + Ng939 <= n2694_1; + Ng942 <= n2699_1; + Ng900 <= n2704_1; + Ng903 <= n2709; + Ng906 <= n2714_1; + Ng945 <= n2719; + Ng948 <= n2724_1; + Ng951 <= n2729_1; + Ng909 <= n2734_1; + Ng912 <= n2739_1; + Ng915 <= n2744_1; + Ng954 <= n2749_1; + Ng957 <= n2754_1; + Ng960 <= n2759_1; + Ng780 <= n2764_1; + Ng776 <= n2769_1; + Ng771 <= n2774_1; + Ng767 <= n2779_1; + Ng762 <= n2784_1; + Ng758 <= n2789_1; + Ng753 <= n2794_1; + Ng749 <= n2799_1; + Ng744 <= n2804_1; + Ng740 <= n2809_1; + Ng11524 <= n2814_1; + Ng11525 <= n2819_1; + Ng11526 <= n2824_1; + Ng11527 <= n2829_1; + Ng11528 <= n2834_1; + Ng11529 <= n2839_1; + Ng11530 <= n2844_1; + Ng11531 <= n2849_1; + Ng11532 <= n2854_1; + Ng11533 <= n2859_1; + Ng11534 <= n2864_1; + Ng11535 <= n2869_1; + Ng1095 <= n2874_1; + Ng1098 <= n2879_1; + Ng1101 <= n2884_1; + Ng1104 <= n2889; + Ng1107 <= n2894; + Ng1110 <= n2899; + Ng1114 <= n2904; + Ng1115 <= n2909_1; + Ng1113 <= n2914_1; + Ng1116 <= n2919_1; + Ng1119 <= n2924_1; + Ng1122 <= n2929_1; + Ng1125 <= n2934_1; + Ng1128 <= n2939_1; + Ng1131 <= n2944_1; + Ng1135 <= n2949_1; + Ng1136 <= n2954_1; + Ng1134 <= n2959_1; + Ng999 <= n2964_1; + Ng1000 <= n2969_1; + Ng1001 <= n2974_1; + Ng1002 <= n2979_1; + Ng1003 <= n2984_1; + Ng1004 <= n2989_1; + Ng1005 <= n2994_1; + Ng1006 <= n2999; + Ng1007 <= n3004_1; + Ng1009 <= n3009_1; + Ng1010 <= n3014; + Ng1008 <= n3019_1; + Ng1090 <= n3024_1; + Ng1091 <= n3029_1; + Ng1089 <= n3034_1; + Ng1137 <= n3039_1; + Ng1138 <= n3043_1; + Ng1139 <= n3048_1; + Ng1140 <= n3052_1; + Ng1141 <= n3057_1; + Ng966 <= n3061_1; + Ng967 <= n3066_1; + Ng968 <= n3070; + Ng969 <= n3075; + Ng970 <= n3079_1; + Ng971 <= n3084_1; + Ng972 <= n3088_1; + Ng973 <= n3093_1; + Ng974 <= n3097_1; + Ng975 <= n3102; + Ng976 <= n3106_1; + Ng977 <= n3110_1; + Ng978 <= n3114_1; + Ng986 <= n3119_1; + Ng992 <= n3124_1; + Ng985 <= n3129_1; + Ng1029 <= n3133_1; + Ng1036 <= n3137_1; + Ng1037 <= n3141_1; + Ng1038 <= n3145_1; + Ng1039 <= n3149_1; + Ng1040 <= n3153_1; + Ng1044 <= n3157_1; + Ng1051 <= n3161_1; + Ng1052 <= n3165_1; + Ng1053 <= n3169_1; + Ng1054 <= n3173_1; + Ng1055 <= n3177_1; + Ng1059 <= n3181_1; + Ng1066 <= n3185_1; + Ng1067 <= n3189_1; + Ng1068 <= n3193_1; + Ng1069 <= n3197_1; + Ng1070 <= n3201_1; + Ng1074 <= n3205_1; + Ng1081 <= n3209_1; + Ng1082 <= n3213_1; + Ng1083 <= n3217_1; + Ng1084 <= n3221_1; + Ng1011 <= n3225_1; + Ng1240 <= n3230_1; + Ng1243 <= n3235_1; + Ng1196 <= n3240_1; + Ng1199 <= n3245_1; + Ng1209 <= n3249_1; + Ng1210 <= n3253_1; + Ng1250 <= n3258_1; + Ng1255 <= n3262_1; + Ng1256 <= n3267_1; + Ng1257 <= n3271_1; + Ng1258 <= n3276_1; + Ng1259 <= n3280_1; + Ng1260 <= n3285_1; + Ng1251 <= n3289_1; + Ng1252 <= n3294_1; + Ng1253 <= n3298_1; + Ng1254 <= n3303_1; + Ng1176 <= n3307_1; + Ng1173 <= n3312_1; + Ng1174 <= n3317_1; + Ng1175 <= n3322_1; + Ng11539 <= n3327_1; + Ng11542 <= n3331_1; + Ng11543 <= n3335_1; + Ng1164 <= n3339_1; + Ng1165 <= n3344_1; + Ng1166 <= n3349_1; + Ng1167 <= n3354_1; + Ng1171 <= n3359_1; + Ng1151 <= n3364_1; + Ng11544 <= n3369_1; + Ng11540 <= n3373_1; + Ng11541 <= n3377_1; + Ng1214 <= n3381_1; + Ng1221 <= n3385_1; + Ng1228 <= n3389_1; + Ng1229 <= n3394_1; + Ng1230 <= n3398_1; + Ng1234 <= n3403_1; + Ng1235 <= n3408_1; + Ng8293 <= n3412_1; + Ng1244 <= n3417_1; + Ng1245 <= n3421_1; + Ng1262 <= n3426_1; + Ng1263 <= n3431_1; + Ng1261 <= n3436_1; + Ng1265 <= n3441_1; + Ng1266 <= n3446_1; + Ng1264 <= n3451_1; + Ng1268 <= n3456_1; + Ng1269 <= n3461_1; + Ng1267 <= n3466_1; + Ng1271 <= n3471_1; + Ng1272 <= n3476_1; + Ng1270 <= n3481_1; + Ng1273 <= n3486_1; + Ng1276 <= n3491_1; + Ng1279 <= n3496_1; + Ng1282 <= n3501_1; + Ng1285 <= n3506_1; + Ng1288 <= n3511_1; + Ng1300 <= n3516_1; + Ng1303 <= n3521_1; + Ng1306 <= n3526_1; + Ng1291 <= n3531_1; + Ng1294 <= n3536_1; + Ng1297 <= n3541_1; + Ng1177 <= n3546_1; + Ng1180 <= n3551_1; + Ng1183 <= n3556_1; + Ng1192 <= n3560_1; + Ng1193 <= n3565_1; + Pg16355 <= n3570_1; + Ng1211 <= n3573_1; + Ng1215 <= n3578_1; + Ng1216 <= n3583_1; + Ng1217 <= n3588_1; + Ng1218 <= n3593_1; + Ng1219 <= n3598_1; + Ng1220 <= n3603_1; + Ng1222 <= n3608_1; + Ng1223 <= n3613_1; + Ng1224 <= n3618_1; + Ng1227 <= n3623_1; + \[1605] <= n3628_1; + \[1603] <= n3632_1; + Ng1315 <= n3636_1; + Ng1316 <= n3641_1; + Ng1345 <= n3646_1; + Ng1326 <= n3651_1; + Ng1319 <= n3656_1; + Ng1339 <= n3661_1; + Ng1332 <= n3666_1; + Ng1346 <= n3671_1; + Ng1358 <= n3676_1; + Ng1352 <= n3681_1; + Ng1365 <= n3686_1; + Ng1372 <= n3691_1; + Ng1378 <= n3696_1; + Ng1385 <= n3701_1; + Ng1386 <= n3706_1; + Ng1384 <= n3711_1; + Ng1388 <= n3716_1; + Ng1389 <= n3721_1; + Ng1387 <= n3726_1; + Ng1391 <= n3731_1; + Ng1392 <= n3736_1; + Ng1390 <= n3741_1; + Ng1394 <= n3746_1; + Ng1395 <= n3751_1; + Ng1393 <= n3756_1; + Ng1397 <= n3761; + Ng1398 <= n3766_1; + Ng1396 <= n3771; + Ng1400 <= n3776_1; + Ng1401 <= n3781_1; + Ng1399 <= n3786; + Ng1403 <= n3791; + Ng1404 <= n3796_1; + Ng1402 <= n3801; + Ng1406 <= n3806; + Ng1407 <= n3811_1; + Ng1405 <= n3816; + Ng1409 <= n3821; + Ng1410 <= n3826_1; + Ng1408 <= n3831_1; + Ng1412 <= n3836_1; + Ng1413 <= n3841_1; + Ng1411 <= n3846_1; + Ng1415 <= n3851_1; + Ng1416 <= n3856_1; + Ng1414 <= n3861_1; + Ng1418 <= n3866; + Ng1419 <= n3871_1; + Ng1417 <= n3876_1; + Ng1421 <= n3881_1; + Ng1422 <= n3886_1; + Ng1420 <= n3891; + Ng1424 <= n3896; + Ng1425 <= n3901; + Ng1423 <= n3906; + Ng1512 <= n3911; + Ng1513 <= n3916_1; + Ng1511 <= n3921; + Ng1515 <= n3926_1; + Ng1516 <= n3931; + Ng1514 <= n3936; + Ng1524 <= n3941_1; + Ng1525 <= n3946; + Ng1523 <= n3951; + Ng1527 <= n3956; + Ng1528 <= n3961_1; + Ng1526 <= n3966; + Ng1530 <= n3971; + Ng1531 <= n3976; + Ng1529 <= n3981; + Ng1533 <= n3986; + Ng1534 <= n3991; + Ng1532 <= n3996_1; + Ng1536 <= n4001_1; + Ng1537 <= n4006_1; + Ng1535 <= n4011_1; + Ng1539 <= n4016_1; + Ng1540 <= n4021; + Ng1538 <= n4026; + Ng1542 <= n4031_1; + Ng1543 <= n4036; + Ng1541 <= n4041_1; + Ng1545 <= n4046; + Ng1546 <= n4051; + Ng1544 <= n4056; + Ng1551 <= n4061; + Ng1552 <= n4066_1; + Ng1550 <= n4071_1; + Ng1554 <= n4076; + Ng1555 <= n4081_1; + Ng1553 <= n4086_1; + Ng1557 <= n4091; + Ng1558 <= n4096_1; + Ng1556 <= n4101; + Ng1560 <= n4106; + Ng1561 <= n4111_1; + Ng1559 <= n4116_1; + Ng1567 <= n4121; + Ng1570 <= n4126; + Ng1573 <= n4131; + Ng1612 <= n4136_1; + Ng1615 <= n4141; + Ng1618 <= n4146; + Ng1576 <= n4151; + Ng1579 <= n4156; + Ng1582 <= n4161; + Ng1621 <= n4166; + Ng1624 <= n4171; + Ng1627 <= n4176; + Ng1585 <= n4181_1; + Ng1588 <= n4186; + Ng1591 <= n4191_1; + Ng1630 <= n4196; + Ng1633 <= n4201; + Ng1636 <= n4206; + Ng1594 <= n4211; + Ng1597 <= n4216; + Ng1600 <= n4221; + Ng1639 <= n4226; + Ng1642 <= n4231; + Ng1645 <= n4236_1; + Ng1603 <= n4241_1; + Ng1606 <= n4246; + Ng1609 <= n4251; + Ng1648 <= n4256; + Ng1651 <= n4261_1; + Ng1654 <= n4266; + Ng1466 <= n4271; + Ng1462 <= n4276; + Ng1457 <= n4281_1; + Ng1453 <= n4286; + Ng1448 <= n4291_1; + Ng1444 <= n4296; + Ng1439 <= n4301; + Ng1435 <= n4306_1; + Ng1430 <= n4311_1; + Ng1426 <= n4316; + Ng11551 <= n4321; + Ng11552 <= n4326; + Ng11553 <= n4331_1; + Ng11554 <= n4336_1; + Ng11555 <= n4341_1; + Ng11556 <= n4346; + Ng11557 <= n4351; + Ng11558 <= n4356; + Ng11559 <= n4361; + Ng11560 <= n4366; + Ng11561 <= n4371; + Ng11562 <= n4376; + Ng1789 <= n4381; + Ng1792 <= n4386; + Ng1795 <= n4391; + Ng1798 <= n4396; + Ng1801 <= n4401; + Ng1804 <= n4406; + Ng1808 <= n4411; + Ng1809 <= n4416; + Ng1807 <= n4421; + Ng1810 <= n4426; + Ng1813 <= n4431; + Ng1816 <= n4436; + Ng1819 <= n4441; + Ng1822 <= n4446_1; + Ng1825 <= n4451_1; + Ng1829 <= n4456_1; + Ng1830 <= n4461; + Ng1828 <= n4466; + Ng1693 <= n4471; + Ng1694 <= n4476; + Ng1695 <= n4481; + Ng1696 <= n4486; + Ng1697 <= n4491; + Ng1698 <= n4496; + Ng1699 <= n4501; + Ng1700 <= n4506_1; + Ng1701 <= n4511; + Ng1703 <= n4516; + Ng1704 <= n4521; + Ng1702 <= n4526; + Ng1784 <= n4531; + Ng1785 <= n4536; + Ng1783 <= n4541; + Ng1831 <= n4546; + Ng1832 <= n4550; + Ng1833 <= n4555; + Ng1834 <= n4559; + Ng1835 <= n4564; + Ng1660 <= n4568; + Ng1661 <= n4573; + Ng1662 <= n4577; + Ng1663 <= n4582; + Ng1664 <= n4586; + Ng1665 <= n4591; + Ng1666 <= n4595; + Ng1667 <= n4600; + Ng1668 <= n4604; + Ng1669 <= n4609; + Ng1670 <= n4613; + Ng1671 <= n4617; + Ng1672 <= n4621; + Ng1680 <= n4626; + Ng1686 <= n4631; + Ng1679 <= n4636; + Ng1723 <= n4640; + Ng1730 <= n4644_1; + Ng1731 <= n4648; + Ng1732 <= n4652; + Ng1733 <= n4656; + Ng1734 <= n4660; + Ng1738 <= n4664; + Ng1745 <= n4668; + Ng1746 <= n4672; + Ng1747 <= n4676; + Ng1748 <= n4680; + Ng1749 <= n4684; + Ng1753 <= n4688; + Ng1760 <= n4692; + Ng1761 <= n4696; + Ng1762 <= n4700; + Ng1763 <= n4704; + Ng1764 <= n4708; + Ng1768 <= n4712; + Ng1775 <= n4716; + Ng1776 <= n4720; + Ng1777 <= n4724; + Ng1778 <= n4728; + Ng1705 <= n4732; + Ng1934 <= n4737; + Ng1937 <= n4742; + Ng1890 <= n4747; + Ng1893 <= n4752; + Ng1903 <= n4756; + Ng1904 <= n4760; + Ng1944 <= n4765; + Ng1949 <= n4769; + Ng1950 <= n4774; + Ng1951 <= n4778; + Ng1952 <= n4783; + Ng1953 <= n4787; + Ng1954 <= n4792; + Ng1945 <= n4796; + Ng1946 <= n4801; + Ng1947 <= n4805; + Ng1948 <= n4810; + Ng1870 <= n4814; + Ng1867 <= n4819; + Ng1868 <= n4824; + Ng1869 <= n4829; + Ng11566 <= n4834; + Ng11569 <= n4838; + Ng11570 <= n4842; + Ng1858 <= n4846; + Ng1859 <= n4851; + Ng1860 <= n4856; + Ng1861 <= n4861; + Ng1865 <= n4866; + Ng1845 <= n4871_1; + Ng11571 <= n4876; + Ng11567 <= n4880; + Ng11568 <= n4884; + Ng1908 <= n4888; + Ng1915 <= n4892; + Ng1922 <= n4896_1; + Ng1923 <= n4901; + Ng1924 <= n4905_1; + Ng1928 <= n4910; + Ng1929 <= n4915; + Ng8302 <= n4919; + Ng1938 <= n4924; + Ng1939 <= n4928; + Ng1956 <= n4933; + Ng1957 <= n4938; + Ng1955 <= n4943; + Ng1959 <= n4948; + Ng1960 <= n4953; + Ng1958 <= n4958; + Ng1962 <= n4963; + Ng1963 <= n4968; + Ng1961 <= n4973; + Ng1965 <= n4978; + Ng1966 <= n4983; + Ng1964 <= n4988; + Ng1967 <= n4993; + Ng1970 <= n4998; + Ng1973 <= n5003; + Ng1976 <= n5008; + Ng1979 <= n5013; + Ng1982 <= n5018; + Ng1994 <= n5023; + Ng1997 <= n5028; + Ng2000 <= n5033; + Ng1985 <= n5038; + Ng1988 <= n5043; + Ng1991 <= n5048; + Ng1871 <= n5053; + Ng1874 <= n5058; + Ng1877 <= n5063; + Ng1886 <= n5067; + Ng1887 <= n5072; + Pg16399 <= n5077; + Ng1905 <= n5080; + Ng1909 <= n5085; + Ng1910 <= n5090; + Ng1911 <= n5095; + Ng1912 <= n5100; + Ng1913 <= n5105; + Ng1914 <= n5110; + Ng1916 <= n5115; + Ng1917 <= n5120; + Ng1918 <= n5125; + Ng1921 <= n5130; + Ng2010 <= n5135; + Ng2039 <= n5140; + Ng2020 <= n5145; + Ng2013 <= n5150; + Ng2033 <= n5155; + Ng2026 <= n5160; + Ng2040 <= n5165; + Ng2052 <= n5170; + Ng2046 <= n5175; + Ng2059 <= n5180; + Ng2066 <= n5185; + Ng2072 <= n5190; + Ng2079 <= n5195; + Ng2080 <= n5200; + Ng2078 <= n5205; + Ng2082 <= n5210; + Ng2083 <= n5215; + Ng2081 <= n5220; + Ng2085 <= n5225; + Ng2086 <= n5230; + Ng2084 <= n5235; + Ng2088 <= n5240; + Ng2089 <= n5245; + Ng2087 <= n5250; + Ng2091 <= n5255; + Ng2092 <= n5260; + Ng2090 <= n5265; + Ng2094 <= n5270; + Ng2095 <= n5275; + Ng2093 <= n5280; + Ng2097 <= n5285; + Ng2098 <= n5290; + Ng2096 <= n5295; + Ng2100 <= n5300; + Ng2101 <= n5305; + Ng2099 <= n5310; + Ng2103 <= n5315; + Ng2104 <= n5320; + Ng2102 <= n5325; + Ng2106 <= n5330; + Ng2107 <= n5335; + Ng2105 <= n5340; + Ng2109 <= n5345; + Ng2110 <= n5350; + Ng2108 <= n5355; + Ng2112 <= n5360; + Ng2113 <= n5365; + Ng2111 <= n5370; + Ng2115 <= n5375; + Ng2116 <= n5380; + Ng2114 <= n5385; + Ng2118 <= n5390; + Ng2119 <= n5395; + Ng2117 <= n5400; + Ng2206 <= n5405; + Ng2207 <= n5410; + Ng2205 <= n5415; + Ng2209 <= n5420; + Ng2210 <= n5425; + Ng2208 <= n5430; + Ng2218 <= n5435; + Ng2219 <= n5440; + Ng2217 <= n5445; + Ng2221 <= n5450; + Ng2222 <= n5455; + Ng2220 <= n5460; + Ng2224 <= n5465; + Ng2225 <= n5470; + Ng2223 <= n5475; + Ng2227 <= n5480; + Ng2228 <= n5485; + Ng2226 <= n5490; + Ng2230 <= n5495; + Ng2231 <= n5500; + Ng2229 <= n5505; + Ng2233 <= n5510; + Ng2234 <= n5515; + Ng2232 <= n5520; + Ng2236 <= n5525; + Ng2237 <= n5530; + Ng2235 <= n5535; + Ng2239 <= n5540; + Ng2240 <= n5545; + Ng2238 <= n5550; + Ng2245 <= n5555; + Ng2246 <= n5560; + Ng2244 <= n5565; + Ng2248 <= n5570; + Ng2249 <= n5575; + Ng2247 <= n5580; + Ng2251 <= n5585; + Ng2252 <= n5590; + Ng2250 <= n5595; + Ng2254 <= n5600; + Ng2255 <= n5605; + Ng2253 <= n5610; + Ng2261 <= n5615; + Ng2264 <= n5620; + Ng2267 <= n5625; + Ng2306 <= n5630; + Ng2309 <= n5635; + Ng2312 <= n5640; + Ng2270 <= n5645; + Ng2273 <= n5650; + Ng2276 <= n5655; + Ng2315 <= n5660; + Ng2318 <= n5665; + Ng2321 <= n5670; + Ng2279 <= n5675; + Ng2282 <= n5680; + Ng2285 <= n5685; + Ng2324 <= n5690; + Ng2327 <= n5695; + Ng2330 <= n5700; + Ng2288 <= n5705; + Ng2291 <= n5710; + Ng2294 <= n5715; + Ng2333 <= n5720; + Ng2336 <= n5725; + Ng2339 <= n5730; + Ng2297 <= n5735; + Ng2300 <= n5740; + Ng2303 <= n5745; + Ng2342 <= n5750; + Ng2345 <= n5755; + Ng2348 <= n5760; + Ng2160 <= n5765; + Ng2156 <= n5770; + Ng2151 <= n5775; + Ng2147 <= n5780; + Ng2142 <= n5785; + Ng2138 <= n5790; + Ng2133 <= n5795; + Ng2129 <= n5800; + Ng2124 <= n5805; + Ng2120 <= n5810; + Ng2256 <= n5815; + \[1609] <= n5819; + Ng2257 <= n5823; + Ng11578 <= n5828; + Ng11579 <= n5833; + Ng11580 <= n5838; + Ng11581 <= n5843; + Ng11582 <= n5848; + Ng11583 <= n5853; + Ng11584 <= n5858; + Ng11585 <= n5863; + Ng11586 <= n5868; + Ng11587 <= n5873; + Ng11588 <= n5878; + Ng11589 <= n5883; + Ng2483 <= n5888; + Ng2486 <= n5893; + Ng2489 <= n5898; + Ng2492 <= n5903; + Ng2495 <= n5908; + Ng2498 <= n5913; + Ng2502 <= n5918; + Ng2503 <= n5923; + Ng2501 <= n5928; + Ng2504 <= n5933; + Ng2507 <= n5938; + Ng2510 <= n5943; + Ng2513 <= n5948; + Ng2516 <= n5953; + Ng2519 <= n5958; + Ng2523 <= n5963; + Ng2524 <= n5968; + Ng2522 <= n5973; + Ng2387 <= n5978; + Ng2388 <= n5983; + Ng2389 <= n5988; + Ng2390 <= n5993; + Ng2391 <= n5998; + Ng2392 <= n6003; + Ng2393 <= n6008; + Ng2394 <= n6013; + Ng2395 <= n6018; + Ng2397 <= n6023; + Ng2398 <= n6028; + Ng2396 <= n6033; + Ng2478 <= n6038; + Ng2479 <= n6043; + Ng2477 <= n6048; + Ng2525 <= n6053; + Ng2526 <= n6057; + Ng2527 <= n6062; + Ng2528 <= n6066; + Ng2529 <= n6071; + Ng2354 <= n6075; + Ng2355 <= n6080; + Ng2356 <= n6084; + Ng2357 <= n6089; + Ng2358 <= n6093; + Ng2359 <= n6098; + Ng2360 <= n6102; + Ng2361 <= n6107; + Ng2362 <= n6111; + Ng2363 <= n6116; + Ng2364 <= n6120; + Ng2365 <= n6124; + Ng2366 <= n6128; + Ng2374 <= n6133; + Ng2380 <= n6138; + Ng2373 <= n6143; + Ng2417 <= n6147; + Ng2424 <= n6151; + Ng2425 <= n6155; + Ng2426 <= n6159; + Ng2427 <= n6163; + Ng2428 <= n6167; + Ng2432 <= n6171; + Ng2439 <= n6175; + Ng2440 <= n6179; + Ng2441 <= n6183; + Ng2442 <= n6187; + Ng2443 <= n6191; + Ng2447 <= n6195; + Ng2454 <= n6199; + Ng2455 <= n6203; + Ng2456 <= n6207; + Ng2457 <= n6211; + Ng2458 <= n6215; + Ng2462 <= n6219; + Ng2469 <= n6223; + Ng2470 <= n6227; + Ng2471 <= n6231; + Ng2472 <= n6235; + Ng2399 <= n6239; + Ng2628 <= n6244; + Ng2631 <= n6249; + Ng2584 <= n6254; + Ng2587 <= n6259; + Ng2597 <= n6263; + Ng2598 <= n6267; + Ng2638 <= n6272; + Ng2643 <= n6276; + Ng2644 <= n6281; + Ng2645 <= n6285; + Ng2646 <= n6290; + Ng2647 <= n6294; + Ng2648 <= n6299; + Ng2639 <= n6303; + Ng2640 <= n6308; + Ng2641 <= n6312; + Ng2642 <= n6317; + Ng2564 <= n6321; + Ng2561 <= n6326; + Ng2562 <= n6331; + Ng2563 <= n6336; + Ng11593 <= n6341; + Ng11596 <= n6345; + Ng11597 <= n6349; + Ng2552 <= n6353; + Ng2553 <= n6358; + Ng2554 <= n6363; + Ng2555 <= n6368; + Ng2559 <= n6373; + Ng2539 <= n6378; + Ng11598 <= n6383; + Ng11594 <= n6387; + Ng11595 <= n6391; + Ng2602 <= n6395; + Ng2609 <= n6399; + Ng2616 <= n6403; + Ng2617 <= n6408; + Ng2618 <= n6412; + Ng2622 <= n6417; + Ng2623 <= n6422; + Ng8311 <= n6426; + Ng2632 <= n6431; + Ng2633 <= n6435; + Ng2650 <= n6440; + Ng2651 <= n6445; + Ng2649 <= n6450; + Ng2653 <= n6455; + Ng2654 <= n6460; + Ng2652 <= n6465; + Ng2656 <= n6470; + Ng2657 <= n6475; + Ng2655 <= n6480; + Ng2659 <= n6485; + Ng2660 <= n6490; + Ng2658 <= n6495; + Ng2661 <= n6500; + Ng2664 <= n6505; + Ng2667 <= n6510; + Ng2670 <= n6515; + Ng2673 <= n6520; + Ng2676 <= n6525; + Ng2688 <= n6530; + Ng2691 <= n6535; + Ng2694 <= n6540; + Ng2679 <= n6545; + Ng2682 <= n6550; + Ng2685 <= n6555; + Ng2565 <= n6560; + Ng2568 <= n6565; + Ng2571 <= n6570; + Ng2580 <= n6574; + Ng2581 <= n6579; + Pg16437 <= n6584; + Ng2599 <= n6587; + Ng2603 <= n6592; + Ng2604 <= n6597; + Ng2605 <= n6602; + Ng2606 <= n6607; + Ng2607 <= n6612; + Ng2608 <= n6617; + Ng2610 <= n6622; + Ng2611 <= n6627; + Ng2612 <= n6632; + Ng2615 <= n6637; + Ng2704 <= n6642; + Ng2733 <= n6647; + Ng2714 <= n6652; + Ng2707 <= n6657; + Ng2727 <= n6662; + Ng2720 <= n6667; + Ng2734 <= n6672; + Ng2746 <= n6677; + Ng2740 <= n6682; + Ng2753 <= n6687; + Ng2760 <= n6692; + Ng2766 <= n6697; + Ng2773 <= n6702; + Ng2774 <= n6707; + Ng2772 <= n6712; + Ng2776 <= n6717; + Ng2777 <= n6722; + Ng2775 <= n6727; + Ng2779 <= n6732; + Ng2780 <= n6737; + Ng2778 <= n6742; + Ng2782 <= n6747; + Ng2783 <= n6752; + Ng2781 <= n6757; + Ng2785 <= n6762; + Ng2786 <= n6767; + Ng2784 <= n6772; + Ng2788 <= n6777; + Ng2789 <= n6782; + Ng2787 <= n6787; + Ng2791 <= n6792; + Ng2792 <= n6797; + Ng2790 <= n6802; + Ng2794 <= n6807; + Ng2795 <= n6812; + Ng2793 <= n6817; + Ng2797 <= n6822; + Ng2798 <= n6827; + Ng2796 <= n6832; + Ng2800 <= n6837; + Ng2801 <= n6842; + Ng2799 <= n6847; + Ng2803 <= n6852; + Ng2804 <= n6857; + Ng2802 <= n6862; + Ng2806 <= n6867; + Ng2807 <= n6872; + Ng2805 <= n6877; + Ng2809 <= n6882; + Ng2810 <= n6887; + Ng2808 <= n6892; + Ng2812 <= n6897; + Ng2813 <= n6902; + Ng2811 <= n6907; + Ng3054 <= n6912; + Ng3079 <= n6917; + Ng13475 <= n6922; + Ng3043 <= n6926; + Ng3044 <= n6931; + Ng3045 <= n6936; + Ng3046 <= n6941; + Ng3047 <= n6946; + Ng3048 <= n6951; + Ng3049 <= n6956; + Ng3050 <= n6961; + Ng3051 <= n6966; + Ng3052 <= n6971; + Ng3053 <= n6976; + Ng3055 <= n6981; + Ng3056 <= n6986; + Ng3057 <= n6991; + Ng3058 <= n6996; + Ng3059 <= n7001; + Ng3060 <= n7006; + Ng3061 <= n7011; + Ng3062 <= n7016; + Ng3063 <= n7021; + Ng3064 <= n7026; + Ng3065 <= n7031; + Ng3066 <= n7036; + Ng3067 <= n7041; + Ng3068 <= n7046; + Ng3069 <= n7051; + Ng3070 <= n7056; + Ng3071 <= n7061; + Ng3072 <= n7066; + Ng3073 <= n7071; + Ng3074 <= n7076; + Ng3075 <= n7081; + Ng3076 <= n7086; + Ng3077 <= n7091; + Ng3078 <= n7096; + Ng2997 <= n7101; + Ng2993 <= n7106; + Ng2998 <= n7111; + Ng3006 <= n7116; + Ng3002 <= n7121; + Ng3013 <= n7126; + Ng3010 <= n7131; + Ng3024 <= n7136; + Ng3018 <= n7141; + Ng3028 <= n7146; + Ng3036 <= n7151; + Ng3032 <= n7156; + Pg5388 <= n7160; + Ng2986 <= n7163; + Ng2987 <= n7167; + Pg8275 <= n7172; + Pg8274 <= n7176; + Pg8273 <= n7180; + Pg8272 <= n7184; + Pg8268 <= n7188; + Pg8269 <= n7192; + Pg8270 <= n7196; + Pg8271 <= n7200; + Ng3083 <= n7204; + Pg8267 <= n7209; + Ng2992 <= n7213; + Pg8266 <= n7218; + Pg8265 <= n7222; + Pg8264 <= n7226; + Pg8262 <= n7230; + Pg8263 <= n7234; + Pg8260 <= n7238; + Pg8261 <= n7242; + Pg8259 <= n7246; + Ng2990 <= n7250; + Ng2991 <= n7255; + Pg8258 <= n7260; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/s38584/s38584.v b/openfpga_flow/benchmarks/MCNC_Verilog/s38584/s38584.v new file mode 100644 index 000000000..075e52556 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/s38584/s38584.v @@ -0,0 +1,7675 @@ +// Benchmark "TOP" written by ABC on Tue Mar 5 10:05:28 2019 + +module s38584 ( clock, + Pg6753, Pg6752, Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746, Pg6745, + Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116, Pg115, + Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72, Pg64, + Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, + Pg34972, Pg34956, Pg34927, Pg34925, Pg34923, Pg34921, Pg34919, Pg34917, + Pg34915, Pg34913, Pg34839, Pg34788, Pg34597, Pg34437, Pg34436, Pg34435, + Pg34425, Pg34383, Pg34240, Pg34239, Pg34238, Pg34237, Pg34236, Pg34235, + Pg34234, Pg34233, Pg34232, Pg34221, Pg34201, Pg33959, Pg33950, Pg33949, + Pg33948, Pg33947, Pg33946, Pg33945, Pg33935, Pg33894, Pg33874, Pg33659, + Pg33636, Pg33533, Pg33435, Pg33079, Pg32975, Pg32454, Pg32429, Pg32185, + Pg31863, Pg31862, Pg31861, Pg31860, Pg31793, Pg31665, Pg31656, Pg31521, + Pg30332, Pg30331, Pg30330, Pg30329, Pg30327, Pg29221, Pg29220, Pg29219, + Pg29218, Pg29217, Pg29216, Pg29215, Pg29214, Pg29213, Pg29212, Pg29211, + Pg29210, Pg28753, Pg28042, Pg28041, Pg28030, Pg27831, Pg26877, Pg26876, + Pg26875, Pg26801, Pg25590, Pg25589, Pg25588, Pg25587, Pg25586, Pg25585, + Pg25584, Pg25583, Pg25582, Pg25259, Pg25219, Pg25167, Pg25114, Pg24185, + Pg24184, Pg24183, Pg24182, Pg24181, Pg24180, Pg24179, Pg24178, Pg24177, + Pg24176, Pg24175, Pg24174, Pg24173, Pg24172, Pg24171, Pg24170, Pg24169, + Pg24168, Pg24167, Pg24166, Pg24165, Pg24164, Pg24163, Pg24162, Pg24161, + Pg24151, Pg23759, Pg23683, Pg23652, Pg23612, Pg23190, Pg23002, Pg21727, + Pg21698, Pg21292, Pg21270, Pg21245, Pg21176, Pg20901, Pg20899, Pg20763, + Pg20654, Pg20652, Pg20557, Pg20049, Pg19357, Pg19334, Pg18881, Pg18101, + Pg18100, Pg18099, Pg18098, Pg18097, Pg18096, Pg18095, Pg18094, Pg18092, + Pg17871, Pg17845, Pg17819, Pg17813, Pg17787, Pg17778, Pg17764, Pg17760, + Pg17743, Pg17739, Pg17722, Pg17715, Pg17711, Pg17688, Pg17685, Pg17678, + Pg17674, Pg17649, Pg17646, Pg17639, Pg17607, Pg17604, Pg17580, Pg17577, + Pg17519, Pg17423, Pg17404, Pg17400, Pg17320, Pg17316, Pg17291, Pg16955, + Pg16924, Pg16874, Pg16775, Pg16748, Pg16744, Pg16722, Pg16718, Pg16693, + Pg16686, Pg16659, Pg16656, Pg16627, Pg16624, Pg16603, Pg14828, Pg14779, + Pg14749, Pg14738, Pg14705, Pg14694, Pg14673, Pg14662, Pg14635, Pg14597, + Pg14518, Pg14451, Pg14421, Pg14217, Pg14201, Pg14189, Pg14167, Pg14147, + Pg14125, Pg14096, Pg13966, Pg13926, Pg13906, Pg13895, Pg13881, Pg13865, + Pg13272, Pg13259, Pg13099, Pg13085, Pg13068, Pg13049, Pg13039, Pg12923, + Pg12919, Pg12833, Pg12832, Pg12470, Pg12422, Pg12368, Pg12350, Pg12300, + Pg12238, Pg12184, Pg11770, Pg11678, Pg11447, Pg11418, Pg11388, Pg11349, + Pg10527, Pg10500, Pg10306, Pg10122, Pg9817, Pg9743, Pg9741, Pg9682, + Pg9680, Pg9617, Pg9615, Pg9555, Pg9553, Pg9497, Pg9251, Pg9048, Pg9019, + Pg8920, Pg8919, Pg8918, Pg8917, Pg8916, Pg8915, Pg8870, Pg8839, Pg8789, + Pg8788, Pg8787, Pg8786, Pg8785, Pg8784, Pg8783, Pg8719, Pg8475, Pg8416, + Pg8403, Pg8398, Pg8358, Pg8353, Pg8344, Pg8342, Pg8291, Pg8283, Pg8279, + Pg8277, Pg8235, Pg8215, Pg8178, Pg8132, Pg7946, Pg7916, Pg7540, Pg7260, + Pg7257, Pg7245, Pg7243 ); + input Pg6753, Pg6752, Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746, + Pg6745, Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116, + Pg115, Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72, + Pg64, Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, clock; + output Pg34972, Pg34956, Pg34927, Pg34925, Pg34923, Pg34921, Pg34919, + Pg34917, Pg34915, Pg34913, Pg34839, Pg34788, Pg34597, Pg34437, Pg34436, + Pg34435, Pg34425, Pg34383, Pg34240, Pg34239, Pg34238, Pg34237, Pg34236, + Pg34235, Pg34234, Pg34233, Pg34232, Pg34221, Pg34201, Pg33959, Pg33950, + Pg33949, Pg33948, Pg33947, Pg33946, Pg33945, Pg33935, Pg33894, Pg33874, + Pg33659, Pg33636, Pg33533, Pg33435, Pg33079, Pg32975, Pg32454, Pg32429, + Pg32185, Pg31863, Pg31862, Pg31861, Pg31860, Pg31793, Pg31665, Pg31656, + Pg31521, Pg30332, Pg30331, Pg30330, Pg30329, Pg30327, Pg29221, Pg29220, + Pg29219, Pg29218, Pg29217, Pg29216, Pg29215, Pg29214, Pg29213, Pg29212, + Pg29211, Pg29210, Pg28753, Pg28042, Pg28041, Pg28030, Pg27831, Pg26877, + Pg26876, Pg26875, Pg26801, Pg25590, Pg25589, Pg25588, Pg25587, Pg25586, + Pg25585, Pg25584, Pg25583, Pg25582, Pg25259, Pg25219, Pg25167, Pg25114, + Pg24185, Pg24184, Pg24183, Pg24182, Pg24181, Pg24180, Pg24179, Pg24178, + Pg24177, Pg24176, Pg24175, Pg24174, Pg24173, Pg24172, Pg24171, Pg24170, + Pg24169, Pg24168, Pg24167, Pg24166, Pg24165, Pg24164, Pg24163, Pg24162, + Pg24161, Pg24151, Pg23759, Pg23683, Pg23652, Pg23612, Pg23190, Pg23002, + Pg21727, Pg21698, Pg21292, Pg21270, Pg21245, Pg21176, Pg20901, Pg20899, + Pg20763, Pg20654, Pg20652, Pg20557, Pg20049, Pg19357, Pg19334, Pg18881, + Pg18101, Pg18100, Pg18099, Pg18098, Pg18097, Pg18096, Pg18095, Pg18094, + Pg18092, Pg17871, Pg17845, Pg17819, Pg17813, Pg17787, Pg17778, Pg17764, + Pg17760, Pg17743, Pg17739, Pg17722, Pg17715, Pg17711, Pg17688, Pg17685, + Pg17678, Pg17674, Pg17649, Pg17646, Pg17639, Pg17607, Pg17604, Pg17580, + Pg17577, Pg17519, Pg17423, Pg17404, Pg17400, Pg17320, Pg17316, Pg17291, + Pg16955, Pg16924, Pg16874, Pg16775, Pg16748, Pg16744, Pg16722, Pg16718, + Pg16693, Pg16686, Pg16659, Pg16656, Pg16627, Pg16624, Pg16603, Pg14828, + Pg14779, Pg14749, Pg14738, Pg14705, Pg14694, Pg14673, Pg14662, Pg14635, + Pg14597, Pg14518, Pg14451, Pg14421, Pg14217, Pg14201, Pg14189, Pg14167, + Pg14147, Pg14125, Pg14096, Pg13966, Pg13926, Pg13906, Pg13895, Pg13881, + Pg13865, Pg13272, Pg13259, Pg13099, Pg13085, Pg13068, Pg13049, Pg13039, + Pg12923, Pg12919, Pg12833, Pg12832, Pg12470, Pg12422, Pg12368, Pg12350, + Pg12300, Pg12238, Pg12184, Pg11770, Pg11678, Pg11447, Pg11418, Pg11388, + Pg11349, Pg10527, Pg10500, Pg10306, Pg10122, Pg9817, Pg9743, Pg9741, + Pg9682, Pg9680, Pg9617, Pg9615, Pg9555, Pg9553, Pg9497, Pg9251, Pg9048, + Pg9019, Pg8920, Pg8919, Pg8918, Pg8917, Pg8916, Pg8915, Pg8870, Pg8839, + Pg8789, Pg8788, Pg8787, Pg8786, Pg8785, Pg8784, Pg8783, Pg8719, Pg8475, + Pg8416, Pg8403, Pg8398, Pg8358, Pg8353, Pg8344, Pg8342, Pg8291, Pg8283, + Pg8279, Pg8277, Pg8235, Pg8215, Pg8178, Pg8132, Pg7946, Pg7916, Pg7540, + Pg7260, Pg7257, Pg7245, Pg7243; + reg Ng5057, Ng2771, Ng1882, Ng2299, Ng4040, Ng2547, Ng559, Ng3243, Ng452, + Ng3542, Ng5232, Ng5813, Ng2907, Ng1744, Ng5909, Ng1802, Ng3554, Ng6219, + Ng807, Ng6031, Ng847, Ng976, Ng4172, Ng4372, Ng3512, Ng749, Ng3490, + Pg12350, Ng4235, Ng1600, Ng1714, Pg14451, Ng3155, Ng2236, Ng4555, + Ng3698, Ng1736, Ng1968, Ng4621, Ng5607, Ng2657, Pg12300, Ng490, Ng311, + Ng772, Ng5587, Ng6177, Ng6377, Ng3167, Ng5615, Ng4567, Ng3457, Ng6287, + Pg7946, Ng2563, Ng4776, Ng4593, Ng6199, Ng2295, Ng1384, Ng1339, Ng5180, + Ng2844, Ng1024, Ng5591, Ng3598, Ng4264, Ng767, Ng5853, Pg13865, Ng2089, + Ng4933, Ng4521, Ng5507, Pg16656, Ng6291, Ng294, Ng5559, Pg9617, Pg9741, + Ng3813, Ng562, Ng608, Ng1205, Ng3909, Ng6259, Ng5905, Ng921, Ng2955, + Ng203, Ng1099, Ng4878, Ng5204, Pg17604, Ng3606, Ng1926, Ng6215, Ng3586, + Ng291, Ng4674, Ng3570, Pg9048, Pg17607, Ng1862, Ng676, Ng843, Ng4332, + Ng4153, Pg17711, Ng6336, Ng622, Ng3506, Ng4558, Pg17685, Ng3111, + \[4430] , Ng26936, Ng939, Ng278, Ng4492, Ng4864, Ng1036, \[4427] , + Ng1178, Ng3239, Ng718, Ng6195, Ng1135, Ng6395, \[4415] , Ng554, Ng496, + Ng3853, Ng5134, Pg17404, Pg8344, Ng2485, Ng925, Ng48, Ng5555, Pg14096, + Ng1798, Ng4076, Ng2941, Ng3905, Ng763, Ng6255, Ng4375, Ng4871, Ng4722, + Ng590, Pg13099, Ng1632, Pg12238, Ng3100, Ng1495, Ng1437, Ng6154, + Ng1579, Ng5567, Ng1752, Ng1917, Ng744, Ng4737, \[4661] , Ng6267, + Pg16659, Ng1442, Ng5965, Ng4477, Pg10500, Ng4643, Ng5264, Pg14779, + Ng2610, Ng5160, Ng5933, Ng1454, Ng753, Ng1296, Ng3151, Ng2980, Ng6727, + Ng3530, Ng4104, Ng1532, Pg9251, Ng2177, Ng52, Ng4754, Ng1189, Ng2287, + Ng4273, Ng1389, Ng1706, Ng5835, Ng1171, Ng4269, Ng2399, Ng4983, Ng5611, + Pg16627, Ng4572, Ng3143, Ng2898, Ng3343, Ng3235, Ng4543, Ng3566, + Ng4534, Ng4961, Ng4927, Ng2259, Ng2819, Pg7257, Ng5802, Ng2852, Ng417, + Ng681, Ng437, Ng351, Ng5901, Ng2886, Ng3494, Ng5511, Ng3518, Ng1604, + Ng5092, Ng4831, Ng4382, Ng6386, Ng479, Ng3965, Ng4749, Ng2008, Ng736, + Ng3933, Ng222, Ng3050, Ng1052, Pg17580, Ng2122, Ng2465, Ng5889, Ng4495, + Pg8719, Ng4653, Ng3179, Ng1728, Ng2433, Ng3835, Ng6187, Ng4917, Ng1070, + Ng822, Pg17715, Ng914, Ng5339, Ng4164, Ng969, Ng2807, Ng4054, Ng6191, + Ng5077, Ng5523, Ng3680, Ng6637, Ng174, Ng1682, Ng355, Ng1087, Ng1105, + Ng2342, Ng6307, Ng3802, Ng6159, Ng2255, Ng2815, Ng911, Ng43, Pg16775, + Ng1748, Ng5551, Ng3558, Ng5499, Ng2960, Ng3901, Ng4888, Ng6251, + Pg17649, Ng1373, Pg8215, Ng157, Ng2783, Ng4281, Ng3574, Ng2112, Ng1283, + Ng433, Ng4297, Pg14738, Pg13272, Ng758, Ng4639, Ng6537, Ng5543, Pg8475, + Ng5961, Ng6243, Ng632, Pg12919, Ng3889, Ng3476, Ng1664, Ng1246, Ng6629, + Ng246, Ng4049, Pg7260, Ng2932, Ng4575, Ng4098, Ng4498, Ng528, Ng16, + Ng3139, \[4432] , Ng4584, Ng142, Pg17639, Ng5831, Ng239, Ng1216, + Ng2848, Ng5022, Pg16955, Ng1030, Pg13881, Ng3231, Pg9817, Ng1430, + Ng4452, Ng2241, Ng1564, Pg9680, Ng6148, Ng6649, Ng110, Pg14147, Ng225, + Ng4486, Ng4504, Ng5873, Ng5037, Ng2319, Ng5495, Pg11770, Ng5208, + Ng5579, Ng5869, Ng1589, Ng5752, Ng6279, Ng5917, Ng2975, Ng6167, + Pg13966, Ng2599, Ng1448, Pg14125, Ng2370, Ng5164, Ng1333, Ng153, + Ng6549, Ng4087, Ng4801, Ng2984, Ng3961, Ng962, Ng101, Pg8918, Ng6625, + Ng51, Ng1018, Pg17320, Ng4045, Ng1467, Ng2461, Ng2756, Ng5990, Ng1256, + Ng5029, Ng6519, Ng1816, Ng4369, Ng4578, Ng4459, Ng3831, Ng2514, Ng3288, + Ng2403, Ng2145, Ng1700, Ng513, Ng2841, Ng5297, Ng2763, Ng4793, Ng952, + Ng1263, Ng1950, Ng5138, Ng2307, Ng5109, Pg8398, Ng4664, Ng2223, Ng5808, + Ng6645, Ng2016, Ng3873, Pg13926, Ng2315, Ng2811, Ng5957, Ng2047, + Ng3869, Pg17760, Ng5575, Ng46, Ng3752, Ng3917, Pg8783, Ng1585, Ng4388, + Ng6275, Ng6311, Pg8916, Ng1041, Ng2595, Ng2537, \[4426] , Ng4430, + Ng4564, Ng4826, Ng6239, Ng232, Ng5268, Ng6545, Ng2417, Ng1772, Ng5052, + Pg9615, Ng1890, Ng2629, Ng572, Ng2130, Ng4108, Ng4308, Ng475, Ng990, + Ng45, Pg12184, Ng3990, Ng5881, Ng1992, Ng3171, Ng812, Ng832, Ng5897, + Ng4571, Pg13895, Ng4455, Ng2902, Ng333, Ng168, Ng2823, Ng3684, Ng3639, + Pg14597, Ng3338, Ng5406, Ng269, Ng401, Ng6040, Ng441, Pg9553, Ng3808, + Ng10384, Ng3957, Ng4093, Ng1760, Pg12422, Ng160, Ng2279, Ng3498, Ng586, + Pg14201, Ng2619, Ng1183, Ng1608, Pg8785, Pg17577, Ng1779, Ng2652, + Ng2193, Ng2393, Ng661, Ng4950, Ng5535, Ng2834, Ng1361, Ng6235, Ng1146, + Ng2625, Ng150, Ng1696, Ng6555, Pg14189, Ng3881, Ng6621, Ng3470, Ng3897, + Ng518, Ng538, Ng2606, Ng1472, Ng542, Ng5188, Ng5689, Pg13259, Ng405, + Ng5216, Ng6494, Ng4669, Ng996, Ng4531, Ng2860, Ng4743, Ng6593, Pg8291, + Ng4411, Ng1413, Ng26960, Pg13039, Ng6641, Ng1936, Ng55, Ng504, Ng2587, + Ng4480, Ng2311, Ng3602, Ng5571, Ng3578, Pg9555, Ng5827, Ng3582, Ng6271, + Ng4688, Ng2380, Ng5196, Ng3227, Ng2020, Pg14518, Pg17316, Ng6541, + Ng3203, Ng1668, Ng4760, Ng262, Ng1840, Ng5467, Ng460, Ng6209, \[4436] , + Pg14662, Ng655, Ng3502, Ng2204, Ng5256, Ng4608, Ng794, Pg13906, Ng4423, + Ng3689, Ng5685, Ng703, Ng862, Ng3247, Ng2040, Ng4146, Ng4633, Pg7916, + Ng4732, Pg9497, Ng5817, Ng2351, Ng2648, Ng6736, Ng4944, Ng4072, Pg7540, + Ng4443, Ng3466, Ng4116, Ng5041, Ng4434, Ng3827, Ng6500, Pg17813, + Ng3133, Ng3333, Ng979, Ng4681, Ng298, Ng2667, Pg8789, Ng1894, Ng2988, + Ng3538, Ng301, Ng341, Ng827, Pg17291, Ng2555, Ng5011, Ng199, Ng6523, + Ng1526, Ng4601, Ng854, Ng1484, Ng4922, Ng5080, Ng5863, Ng4581, Ng2518, + Ng2567, Ng568, Ng3263, Ng6613, Ng6044, Ng6444, Ng2965, Ng5857, Ng1616, + Ng890, Pg17646, Ng3562, Pg10122, Ng1404, Ng3817, Ng93, Ng4501, Ng287, + Ng2724, Ng4704, Ng22, Ng2878, Ng5220, Ng617, Pg12368, Ng316, Ng1277, + Ng6513, Ng336, Ng2882, Ng933, Ng1906, Ng305, Ng8, Ng2799, Pg14167, + Pg17787, Ng4912, Ng4157, Ng2541, Ng2153, Ng550, Ng255, Ng1945, Ng5240, + Ng1478, Ng3863, Ng1959, Ng3480, Ng6653, Pg17764, Ng2864, Ng4894, + Pg17678, Ng3857, Pg16693, Ng499, Ng1002, Ng776, Ng1236, Ng4646, Ng2476, + Ng1657, Ng2375, Ng63, Pg17739, Ng358, Ng896, Ng283, Ng3161, Ng2384, + Pg14828, Ng4616, Ng4561, Ng2024, Ng3451, Ng2795, Ng613, Ng4527, Ng1844, + Ng5937, Ng4546, Ng2523, Pg11349, Ng2643, Ng1489, Pg8358, Ng2551, + Ng5156, \[4421] , Pg8279, Pg8839, Ng1955, Ng6049, Ng2273, Pg14749, + Ng4771, Ng6098, Ng3147, Ng3347, Ng2269, Ng191, Ng2712, Ng626, Ng2729, + Ng5357, Ng4991, Pg17819, Ng4709, Ng2927, Ng4340, Ng5929, Ng4907, + Pg16874, Ng4035, Ng2946, Ng918, Ng4082, Pg9743, Ng2036, Ng577, Ng1620, + Ng2831, Ng667, Ng930, Ng3937, Ng817, Ng1249, Ng837, Pg16924, Ng599, + Ng5475, Ng739, Ng5949, Ng6682, Ng904, Ng2873, Ng1854, Ng5084, Ng5603, + Pg8870, Ng2495, Ng2437, Ng2102, Ng2208, Ng2579, Ng4064, Ng4899, Ng2719, + Ng4785, Ng5583, Ng781, Ng6173, Pg17743, Ng2917, Ng686, Ng1252, Ng671, + Ng2265, Ng6283, Pg14705, Pg17519, Pg8784, Ng5527, Ng4489, Ng1974, + Ng1270, Ng4966, Ng6227, Ng3929, Ng5503, Ng4242, Ng5925, Ng1124, Ng4955, + Ng5224, Ng2012, Ng6203, Ng5120, Pg17674, Ng2389, Ng4438, Ng2429, + Ng2787, Ng1287, Ng2675, \[4507] , Ng4836, Ng1199, Pg19357, Ng5547, + Ng2138, Pg16744, Ng2338, Pg8919, Ng6247, Ng2791, Ng3949, Ng1291, + Ng5945, Ng5244, Ng2759, Ng6741, Ng785, Ng1259, Ng3484, Ng209, Ng6609, + Ng5517, Ng2449, Ng2575, Ng65, Ng2715, Ng936, Ng2098, Ng4462, Ng604, + Ng6589, Ng1886, Pg17845, Pg17871, Ng429, Ng1870, Ng4249, Ng1825, + Ng1008, Ng4392, Ng3546, Ng5236, Ng1768, Ng4854, Ng3925, Ng6509, Ng732, + Ng2504, Ng1322, Ng4520, Pg8917, Ng2185, Ng37, Ng4031, Ng2070, \[4658] , + Ng4176, Pg11418, Ng4405, Ng872, Ng6181, Ng6381, Ng4765, Ng5563, Ng1395, + Ng1913, Ng2331, Ng6263, Ng50, Ng3945, Ng347, Ng4473, Ng1266, Ng5489, + Ng714, Ng2748, Ng5471, Ng4540, Ng6723, Ng6605, Ng2445, Ng2173, Pg9019, + Ng2491, Ng4849, Ng2169, Ng2283, Ng6585, \[4428] , Ng2407, Ng2868, + Ng2767, Ng1783, Pg16718, Ng1312, Ng5212, Ng4245, Ng645, Ng4291, + \[4435] , Ng182, Ng1129, Ng2227, Pg8788, Ng2246, Ng1830, Ng3590, Ng392, + Ng1592, Ng6505, Ng1221, Ng5921, \[4431] , Ng146, Ng218, Ng1932, Ng1624, + Ng5062, Ng5462, Ng2689, Ng6573, Ng1677, Ng2028, Ng2671, Pg10527, + Pg7243, Ng1848, \[4434] , Ng5485, Ng2741, Pg11678, Ng2638, Ng4122, + Ng4322, Ng5941, Ng2108, Pg13068, Ng25, Ng1644, Ng595, Ng2217, Ng1319, + Ng2066, Ng1152, Ng5252, Ng2165, Ng2571, Ng5176, Pg14673, Ng1211, + Ng2827, Pg14217, Ng4859, Ng424, Ng1274, Pg17423, Ng85, Ng2803, Ng1821, + Ng2509, Ng5073, Ng1280, \[4651] , Pg13085, Ng6633, Ng5124, Pg17400, + Ng6303, Ng5069, Ng2994, Ng650, Ng1636, Ng3921, Ng2093, Ng6732, Ng1306, + Ng1061, Ng3462, Ng2181, Ng956, Ng1756, Ng5849, Ng4112, Ng2685, Ng2197, + Ng2421, Ng1046, Ng482, Ng4401, Ng1514, Ng329, Ng6565, Ng2950, Ng1345, + Ng6533, Pg14421, Ng4727, Pg12470, Ng1536, Ng3941, Ng370, Ng5694, + Ng1858, Ng446, Ng3219, Ng1811, Ng6601, Ng2441, Ng1874, Ng4349, Ng6581, + Ng6597, Ng3610, Ng2890, Ng1978, Ng1612, Ng112, Ng2856, Ng1982, Pg17722, + Ng5228, Ng4119, Ng6390, Ng1542, Ng4258, Ng4818, Ng5033, Ng4717, Ng1554, + Ng3849, Pg17778, Ng3199, Ng5845, Ng4975, Ng790, Ng5913, Ng1902, Ng6163, + Ng4125, Ng4821, Ng4939, Pg19334, Ng3207, Ng4483, Ng3259, Ng5142, + Ng5248, Ng2126, Ng3694, Ng5481, Ng1964, Ng5097, Ng3215, Pg16748, Ng111, + Ng4427, Ng2779, Pg8786, Pg7245, Ng1720, Ng1367, Ng5112, Ng4145, Ng2161, + Ng376, Ng2361, Pg11447, Ng582, Ng2051, Ng1193, Ng2327, Ng907, Ng947, + Ng1834, Ng3594, Ng2999, Ng2303, Pg17688, Ng699, Ng723, Ng5703, Ng546, + Ng2472, Ng5953, Pg8277, Ng1740, Ng3550, Ng3845, Ng2116, Pg14635, + Ng3195, Ng3913, Pg10306, Ng1687, Ng2681, Ng2533, Ng324, Ng2697, Ng4417, + Ng6561, Ng1141, Pg12923, Ng2413, Ng1710, Ng6527, Ng3255, Ng1691, + Ng2936, Ng5644, Ng5152, Ng5352, Pg8915, Ng2775, Ng2922, Ng1111, Ng5893, + Pg16603, Ng6617, Ng2060, Ng4512, Ng5599, Ng3401, Ng4366, Pg16722, + \[4433] , Ng3129, Ng3329, Ng5170, Ng26959, Ng5821, Ng6299, Pg8416, + Ng2079, Ng4698, Ng3703, Ng1559, Ng943, Ng411, Pg9682, Ng3953, Ng2704, + Ng6035, Ng1300, Ng4057, Ng5200, Ng4843, Ng5046, Ng2250, Ng26885, + Ng4549, Ng2453, Ng5841, Pg14694, Ng2912, Ng2357, Pg8920, Ng164, Ng4253, + Ng5016, Ng3119, Ng1351, Ng1648, Ng6972, Ng5115, Ng3352, Ng6657, Ng4552, + Ng3893, Ng3211, Pg13049, Pg16624, Ng5595, Ng3614, Ng2894, Ng3125, + Pg16686, Ng3821, Ng4141, Ng6974, Ng5272, Ng2735, Ng728, Ng6295, Ng2661, + Ng1988, Ng5128, Ng1548, Ng3106, Ng4659, Ng4358, Ng1792, Ng2084, Ng3187, + Ng4311, Ng2583, Ng3003, Ng1094, Ng3841, Ng4284, Ng3191, Ng4239, Ng4180, + Ng691, Ng534, Ng385, Ng2004, Ng2527, Ng5456, Ng4420, Ng5148, Ng4507, + Ng5348, Ng3223, Ng2970, Ng5698, Ng5260, Ng1521, Ng3522, Ng3115, Ng3251, + Pg12832, Ng4628, Ng1996, Pg8342, Ng4515, Pg8787, Ng4300, Ng1724, + Ng1379, Pg11388, Ng1878, Ng5619, Ng71, \[4437] ; + wire n4124_1, n4133, n4135, n4136, n4151_1, n4162, n4205, n4206_1, n4207, + n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216_1, n4217, + n4218, n4219, n4220, n4221, n4223, n4225, n4227, n4229, n4231, n4233, + n4235, n4237, n4239, n4241, n4243, n4245, n4247, n4249_1, n4251, n4252, + n4254_1, n4256, n4258, n4260, n4262, n4265, n4267, n4269, n4271, n4273, + n4275, n4277, n4279, n4281, n4283, n4285, n4287, n4289, n4291, n4293, + n4295, n4297, n4299, n4301, n4303, n4305, n4307, n4309, n4311, n4313, + n4315, n4317, n4319, n4321, n4323, n4325, n4327, n4329, n4331, n4333, + n4335, n4337, n4339, n4341, n4343, n4345, n4347, n4349, n4351, n4353, + n4355, n4357, n4359, n4361, n4363, n4365, n4367, n4369_1, n4371, n4373, + n4375, n4377, n4379, n4382, n4384, n4385, n4388, n4390, n4392, n4394, + n4396, n4398, n4400, n4402, n4404, n4406, n4408, n4410, n4412, n4414, + n4416, n4418, n4420, n4423, n4425, n4427, n4429, n4431, n4433, n4435, + n4437_1, n4439, n4441, n4443, n4445, n4448, n4450, n4452_1, n4454, + n4456_1, n4458, n4460_1, n4462, n4464, n4466, n4468, n4470_1, n4472, + n4474, n4475_1, n4477, n4479, n4481, n4483, n4485_1, n4487, n4489_1, + n4491, n4493, n4495_1, n4497, n4499_1, n4501, n4503, n4505, n4507, + n4509, n4512, n4514_1, n4516, n4518, n4520, n4521, n4522, n4524_1, + n4526, n4528, n4530, n4532, n4534_1, n4536, n4538, n4541, n4543, n4545, + n4547, n4549_1, n4551, n4553, n4555, n4557, n4558, n4560, n4562, n4564, + n4567, n4569, n4571, n4573, n4575, n4577, n4579, n4581, n4583, n4585, + n4587, n4589, n4591, n4593, n4595, n4597, n4599, n4601, n4603, n4605, + n4607_1, n4609, n4611, n4613, n4615, n4617_1, n4619, n4621, n4623, + n4625, n4627_1, n4629, n4631_1, n4633, n4635, n4637, n4639, n4641, + n4643, n4645, n4647, n4649, n4651, n4653, n4655, n4657, n4659, n4661, + n4663, n4665, n4667, n4669, n4671, n4673, n4675, n4677, n4679, n4681, + n4683, n4685, n4687_1, n4689, n4692, n4695, n4697, n4699, n4701, n4703, + n4705, n4707, n4709, n4711, n4713, n4715, n4717, n4719, n4722, n4724, + n4726, n4728, n4730, n4732, n4734, n4736, n4738, n4740, n4742, n4744, + n4746_1, n4748, n4750, n4752, n4754, n4756_1, n4758, n4760, n4762, + n4764, n4766_1, n4768, n4770, n4772, n4774, n4776, n4778, n4780, + n4782_1, n4784, n4786, n4788, n4790, n4792, n4794, n4796, n4798, n4800, + n4802_1, n4804, n4806, n4808, n4810, n4812_1, n4814, n4816, n4818, + n4820, n4822_1, n4824, n4826, n4828, n4830, n4832, n4834, n4836, n4838, + n4840, n4842, n4844, n4846, n4848, n4850, n4852, n4854, n4856, n4858, + n4860, n4862, n4864, n4866, n4868, n4870, n4872, n4874, n4876, n4878, + n4880, n4882_1, n4884, n4886, n4887, n4889, n4891, n4893, n4895, n4898, + n4900, n4902, n4904_1, n4906, n4908, n4909, n4911, n4913, n4915, n4917, + n4919, n4921, n4923, n4925, n4927, n4929, n4931, n4933, n4935, n4937, + n4939_1, n4941, n4943, n4945, n4947, n4949, n4951, n4953, n4955, n4958, + n4960, n4962, n4964, n4966, n4968, n4970, n4972, n4974, n4976, n4978_1, + n4980, n4982, n4984, n4986, n4988, n4990, n4992_1, n4994, n4996, n4998, + n5000, n5002_1, n5004, n5006, n5008, n5010, n5012, n5014, n5016_1, + n5018, n5020, n5022, n5025, n5027, n5029, n5031, n5034, n5036_1, n5038, + n5040, n5042, n5044, n5046, n5048, n5049, n5050, n5052, n5054, n5057, + n5059, n5061, n5063, n5065, n5067, n5069_1, n5072, n5074, n5076, n5078, + n5080, n5082, n5084, n5086, n5088, n5090, n5091, n5093, n5095, n5097, + n5099, n5102, n5104, n5106, n5108, n5110, n5112, n5114, n5116_1, n5118, + n5120, n5122, n5124, n5126_1, n5128, n5131_1, n5132, n5134, n5136, + n5139, n5141_1, n5143, n5145, n5147, n5149, n5151, n5153, n5155, n5157, + n5159, n5161, n5163, n5165, n5167, n5169, n5170, n5172, n5174, n5176, + n5178, n5180, n5182, n5184, n5186, n5188, n5190, n5192, n5194, n5196, + n5198, n5200, n5202, n5204, n5206, n5208, n5210, n5212, n5214, n5216, + n5218, n5220, n5222, n5224, n5226, n5228, n5230, n5232, n5234, n5236, + n5238, n5240, n5242, n5244, n5246, n5248, n5250, n5252, n5254, n5256, + n5258, n5260, n5262, n5264, n5266, n5268, n5270, n5272, n5274, n5276, + n5278, n5280, n5283, n5285, n5287, n5289, n5291, n5293, n5296, n5298_1, + n5300, n5302, n5304, n5306, n5308, n5310, n5312, n5314, n5316, n5318_1, + n5320, n5322_1, n5324, n5326, n5328, n5330, n5332, n5334, n5336, n5338, + n5340, n5342, n5344, n5346, n5348, n5350, n5352, n5354, n5356, n5358, + n5360, n5362, n5365, n5367, n5370, n5372, n5374, n5376, n5378, n5380, + n5382, n5384, n5386, n5388, n5390, n5392, n5394, n5396, n5398, n5400, + n5402, n5404, n5406, n5408, n5410, n5412, n5414, n5416_1, n5418, n5420, + n5422, n5424, n5425, n5427, n5429, n5431, n5433, n5435, n5437, n5439, + n5441, n5443, n5445, n5447, n5449, n5451, n5453, n5455, n5457, n5459, + n5461_1, n5463, n5465, n5467, n5469, n5471, n5473, n5475, n5477, n5479, + n5481, n5483, n5485, n5487, n5489, n5491, n5493, n5495, n5497, n5499, + n5501, n5503, n5505, n5507, n5509, n5511, n5513, n5515, n5517, n5519, + n5521, n5523, n5525, n5527, n5529, n5531, n5533, n5535, n5537, n5539, + n5541, n5543, n5545, n5547, n5549, n5551, n5553, n5555, n5557, n5559, + n5560, n5562, n5564, n5566, n5568, n5570, n5572, n5574, n5576, n5578, + n5580, n5582, n5584, n5586, n5588, n5590, n5592, n5594, n5596, n5598_1, + n5600, n5602, n5604, n5606, n5608, n5610, n5612, n5614, n5616, n5618, + n5620, n5622, n5624, n5626, n5628_1, n5630, n5632, n5634, n5636, + n5638_1, n5640, n5642, n5644, n5646, n5648, n5650, n5652, n5654, n5656, + n5658, n5660, n5662_1, n5664, n5666, n5668, n5669, n5671_1, n5673, + n5675, n5677, n5679, n5681, n5683, n5685, n5687, n5689, n5691, n5693, + n5695_1, n5697, n5699, n5701, n5703, n5705, n5707, n5709, n5711, n5713, + n5715, n5717, n5719, n5721, n5723, n5725, n5727, n5729, n5730, n5731, + n5733, n5735, n5737, n5739, n5741, n5743, n5745, n5747, n5749, n5751, + n5753_1, n5755, n5757, n5759, n5761, n5763_1, n5765, n5767, n5769, + n5771, n5773, n5775, n5777, n5779, n5781, n5783, n5785, n5787, n5789, + n5791_1, n5793, n5795, n5797, n5799, n5801_1, n5803, n5805, n5807, + n5809, n5811_1, n5813, n5815, n5817, n5819, n5821, n5823, n5825, n5827, + n5829, n5831, n5833, n5835, n5837, n5839, n5841, n5843, n5845, n5847, + n5849, n5851, n5853, n5855, n5857, n5859_1, n5861, n5863, n5865, n5866, + n5867, n5868, n5869_1, n5871, n5872, n5873, n5874_1, n5875, n5876, + n5877, n5878, n5880, n5881, n5882, n5883, n5884_1, n5885, n5886, n5887, + n5888, n5889, n5892, n5894, n5895, n5897, n5898_1, n5899, n5901, n5902, + n5903, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5914, + n5915, n5916, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, + n5926, n5927, n5929, n5930, n5931, n5933, n5934, n5935, n5936, n5938, + n5939, n5940, n5941, n5942, n5944, n5945, n5947, n5948, n5949, n5950, + n5951, n5952, n5953, n5954, n5956_1, n5957, n5958, n5959, n5960, n5961, + n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, + n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, + n5982, n5983, n5984, n5985, n5988, n5989, n5990_1, n5991, n5992, n5993, + n5994, n5995, n5996, n5997, n5998_1, n5999, n6000, n6001, n6002, n6003, + n6004, n6005, n6006, n6007, n6008_1, n6009, n6010, n6011, n6012_1, + n6013, n6014, n6015, n6016, n6017_1, n6018, n6019, n6020, n6021, n6022, + n6023, n6024, n6025, n6026, n6027_1, n6028, n6029, n6030, n6031, n6032, + n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042_1, + n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, + n6053, n6054, n6055, n6056_1, n6057, n6058, n6059, n6060, n6061_1, + n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, + n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081_1, + n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091_1, + n6092, n6093, n6094, n6095, n6096_1, n6097, n6098, n6099, n6100, n6101, + n6102, n6103, n6104_1, n6105, n6106, n6107, n6108, n6109, n6110, n6111, + n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, + n6122, n6123, n6124, n6125, n6126, n6127_1, n6128, n6129, n6130, n6131, + n6132, n6133, n6134, n6135, n6136, n6137_1, n6138, n6139, n6140, n6141, + n6142_1, n6143, n6144, n6145, n6146, n6147_1, n6148, n6149, n6150, + n6151, n6152_1, n6153, n6154, n6155, n6156_1, n6157, n6158, n6159, + n6160_1, n6161, n6162, n6163, n6164, n6165_1, n6166, n6167, n6168, + n6169_1, n6170, n6171, n6172, n6173, n6174, n6175, n6176, n6177, n6178, + n6179_1, n6180, n6181, n6182, n6183_1, n6184, n6185, n6186, n6187, + n6188, n6189, n6190, n6191, n6192_1, n6193, n6194, n6195, n6196_1, + n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206_1, + n6207, n6208, n6209, n6210, n6211_1, n6212, n6213, n6214, n6215, + n6216_1, n6217, n6218, n6219, n6220, n6221_1, n6222, n6223, n6224, + n6225, n6226_1, n6227, n6228, n6229, n6230_1, n6231, n6232, n6233, + n6234, n6235_1, n6236, n6237, n6238, n6239, n6240_1, n6241, n6242, + n6243, n6244, n6245_1, n6246, n6247, n6248, n6249, n6250_1, n6251, + n6252, n6253, n6254, n6255_1, n6256, n6257, n6258, n6259, n6260_1, + n6261, n6262, n6263, n6264, n6265_1, n6266, n6267, n6268, n6269, + n6270_1, n6271, n6272, n6273, n6274, n6275_1, n6276, n6277, n6278, + n6279_1, n6280, n6281, n6282, n6283, n6284_1, n6285, n6286, n6287, + n6288, n6289_1, n6290, n6291, n6292, n6293_1, n6294, n6295, n6296, + n6297_1, n6298, n6299, n6300, n6301, n6302_1, n6303, n6304, n6305, + n6306, n6307, n6308, n6309, n6310_1, n6311, n6312, n6313, n6314, + n6315_1, n6316, n6317, n6318, n6319, n6320_1, n6321, n6322, n6323, + n6324, n6325, n6326, n6327, n6328, n6329, n6330_1, n6331, n6332, n6333, + n6334, n6335_1, n6336, n6337, n6338, n6339, n6340_1, n6341, n6342, + n6343, n6344, n6345, n6346, n6347, n6348, n6349_1, n6350, n6351, n6352, + n6353, n6354_1, n6355, n6356, n6357, n6358, n6359_1, n6360, n6361, + n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369_1, n6370, n6371, + n6372, n6373_1, n6374, n6375, n6376_1, n6377, n6378, n6379, n6380_1, + n6381, n6382, n6383, n6384, n6385_1, n6386, n6387, n6388, n6389, + n6390_1, n6391, n6392, n6393, n6394, n6395_1, n6396, n6397, n6398, + n6399_1, n6400, n6401, n6402, n6403_1, n6404, n6405, n6406, n6407, + n6408, n6409, n6410, n6411, n6412, n6413_1, n6414, n6415, n6416, + n6417_1, n6418, n6419, n6420, n6421, n6422_1, n6423, n6424, n6425, + n6426, n6427_1, n6428, n6429, n6430, n6431, n6432_1, n6433, n6434, + n6435, n6436, n6437_1, n6438, n6439, n6440, n6441, n6442_1, n6443, + n6444, n6445, n6446, n6447_1, n6448, n6449, n6450, n6451, n6452_1, + n6453, n6454, n6455, n6456, n6457_1, n6458, n6459, n6460, n6461, + n6462_1, n6463, n6464, n6465, n6466, n6467_1, n6468, n6469, n6470, + n6471, n6472_1, n6473, n6474, n6475, n6476, n6477_1, n6478, n6479, + n6480, n6481, n6482_1, n6483, n6484, n6485, n6486, n6487_1, n6488, + n6489, n6490, n6491, n6492_1, n6493, n6494, n6495, n6496, n6497_1, + n6498, n6499, n6500, n6501, n6502_1, n6503, n6504, n6505, n6506, + n6507_1, n6508, n6509, n6510, n6511, n6512_1, n6513, n6514, n6515, + n6516, n6517_1, n6518, n6519, n6520, n6521, n6522_1, n6523, n6524, + n6525, n6526_1, n6527, n6528, n6529, n6530, n6531_1, n6532, n6533, + n6534, n6535, n6536_1, n6537, n6538, n6539, n6540, n6541_1, n6542, + n6543, n6544, n6545, n6546_1, n6547, n6548, n6549, n6550, n6551_1, + n6552, n6553, n6554, n6555_1, n6556, n6557, n6558, n6559, n6560_1, + n6561, n6562, n6563, n6564, n6565_1, n6566, n6567, n6568, n6569, + n6570_1, n6571, n6572, n6573, n6574, n6575_1, n6576, n6577, n6578, + n6579, n6580_1, n6581, n6582, n6583, n6584, n6585_1, n6586, n6587, + n6588, n6589, n6590_1, n6591, n6592, n6593, n6594, n6595_1, n6596, + n6597, n6598, n6599, n6600_1, n6601, n6602, n6603, n6604, n6605_1, + n6606, n6607, n6608, n6609, n6610_1, n6611, n6612, n6613, n6614, + n6615_1, n6616, n6617, n6618, n6619, n6620_1, n6621, n6622, n6623, + n6624_1, n6625, n6626, n6627, n6628, n6629_1, n6630, n6631, n6632, + n6633, n6634_1, n6635, n6636, n6637, n6638_1, n6639, n6640, n6641, + n6642_1, n6643, n6644, n6645, n6646_1, n6647, n6648, n6649, n6650, + n6651_1, n6652, n6653, n6654, n6655, n6656_1, n6657, n6658, n6659, + n6660, n6661_1, n6662, n6663, n6664, n6665_1, n6666, n6667, n6668, + n6669, n6670_1, n6671, n6672, n6673, n6674, n6675_1, n6676, n6677, + n6678, n6679, n6680_1, n6681, n6682, n6683, n6684, n6685, n6686, n6687, + n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, n6696, n6697, + n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, n6706, n6707, + n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, n6716, n6717, + n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726, n6727, + n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736, n6737, + n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, n6746, n6747, + n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756, n6757, + n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766, n6767, + n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776, n6777, + n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786, n6787, + n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796, n6797, + n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806, n6807, + n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816, n6817, + n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826, n6827, + n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836, n6837, + n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846, n6847, + n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856, n6857, + n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866, n6867, + n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876, n6877, + n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886, n6887, + n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896, n6897, + n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906, n6907, + n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916, n6917, + n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926, n6927, + n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936, n6937, + n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946, n6947, + n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956, n6957, + n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966, n6967, + n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976, n6977, + n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986, n6987, + n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996, n6997, + n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006, n7007, + n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016, n7017, + n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, n7026, n7027, + n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036, n7037, + n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046, n7047, + n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056, n7057, + n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065, n7066, n7067, + n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076, n7077, + n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085, n7086, n7087, + n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095, n7096, n7097, + n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105, n7106, n7107, + n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115, n7116, n7117, + n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125, n7126, n7127, + n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135, n7136, n7137, + n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145, n7146, n7147, + n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155, n7156, n7157, + n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165, n7166, n7167, + n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175, n7176, n7177, + n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185, n7186, n7187, + n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195, n7196, n7197, + n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205, n7206, n7207, + n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215, n7216, n7217, + n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225, n7226, n7227, + n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235, n7236, n7237, + n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245, n7246, n7247, + n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255, n7256, n7257, + n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265, n7266, n7267, + n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275, n7276, n7277, + n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285, n7286, n7287, + n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295, n7296, n7297, + n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305, n7306, n7307, + n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315, n7316, n7317, + n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325, n7326, n7327, + n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336, n7337, + n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346, n7347, + n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356, n7357, + n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366, n7367, + n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376, n7377, + n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386, n7387, + n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396, n7397, + n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406, n7407, + n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416, n7417, + n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426, n7427, + n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436, n7437, + n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446, n7447, + n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456, n7457, + n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466, n7467, + n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476, n7477, + n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486, n7487, + n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496, n7497, + n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506, n7507, + n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516, n7517, + n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526, n7527, + n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536, n7537, + n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546, n7547, + n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556, n7557, + n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566, n7567, + n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576, n7577, + n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586, n7587, + n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596, n7597, + n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606, n7607, + n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616, n7617, + n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626, n7627, + n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636, n7637, + n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646, n7647, + n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656, n7657, + n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666, n7667, + n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676, n7677, + n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686, n7687, + n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696, n7697, + n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706, n7707, + n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716, n7717, + n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726, n7727, + n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736, n7737, + n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746, n7747, + n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756, n7757, + n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766, n7767, + n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776, n7777, + n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786, n7787, + n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796, n7797, + n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806, n7807, + n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816, n7817, + n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826, n7827, + n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836, n7837, + n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846, n7847, + n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856, n7857, + n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866, n7867, + n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876, n7877, + n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886, n7887, + n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896, n7897, + n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906, n7907, + n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916, n7917, + n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926, n7927, + n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936, n7937, + n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946, n7947, + n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956, n7957, + n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966, n7967, + n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976, n7977, + n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986, n7987, + n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996, n7997, + n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006, n8007, + n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016, n8017, + n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026, n8027, + n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036, n8037, + n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046, n8047, + n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056, n8057, + n8058, n8059, n8061, n8062, n8063, n8064, n8065, n8066, n8067, n8068, + n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076, n8077, n8078, + n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086, n8087, n8088, + n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096, n8097, n8098, + n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106, n8107, n8108, + n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116, n8117, n8118, + n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126, n8127, n8128, + n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136, n8137, n8138, + n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146, n8147, n8148, + n8149, n8150, n8151, n8153, n8154, n8155, n8156, n8157, n8158, n8159, + n8160, n8161, n8162, n8163, n8164, n8165, n8166, n8167, n8168, n8169, + n8170, n8171, n8172, n8173, n8174, n8175, n8176, n8177, n8178, n8179, + n8180, n8181, n8182, n8183, n8184, n8185, n8186, n8187, n8188, n8189, + n8190, n8191, n8192, n8193, n8194, n8195, n8196, n8197, n8198, n8199, + n8200, n8201, n8202, n8203, n8204, n8205, n8206, n8207, n8208, n8209, + n8210, n8211, n8212, n8213, n8214, n8215, n8216, n8217, n8218, n8219, + n8220, n8221, n8222, n8223, n8224, n8225, n8226, n8227, n8228, n8229, + n8230, n8231, n8232, n8233, n8234, n8235, n8236, n8237, n8238, n8239, + n8240, n8241, n8242, n8243, n8244, n8245, n8246, n8247, n8248, n8249, + n8250, n8251, n8252, n8253, n8254, n8255, n8256, n8257, n8258, n8259, + n8260, n8261, n8262, n8263, n8264, n8265, n8266, n8267, n8268, n8269, + n8270, n8271, n8272, n8273, n8274, n8275, n8276, n8277, n8278, n8279, + n8280, n8281, n8282, n8283, n8284, n8285, n8286, n8287, n8288, n8289, + n8290, n8291, n8292, n8293, n8294, n8295, n8296, n8297, n8298, n8299, + n8300, n8301, n8302, n8303, n8304, n8305, n8306, n8307, n8308, n8309, + n8310, n8311, n8312, n8313, n8314, n8315, n8316, n8317, n8318, n8319, + n8320, n8321, n8322, n8323, n8324, n8325, n8326, n8327, n8328, n8329, + n8330, n8331, n8332, n8333, n8334, n8335, n8336, n8337, n8338, n8339, + n8340, n8341, n8342, n8343, n8344, n8346, n8347, n8348, n8350, n8351, + n8352, n8353, n8354, n8355, n8356, n8357, n8358, n8359, n8360, n8361, + n8362, n8363, n8364, n8365, n8366, n8367, n8368, n8369, n8370, n8371, + n8372, n8373, n8374, n8375, n8376, n8377, n8378, n8379, n8380, n8381, + n8382, n8383, n8384, n8385, n8386, n8387, n8388, n8389, n8390, n8391, + n8392, n8393, n8394, n8395, n8396, n8397, n8398, n8399, n8400, n8401, + n8402, n8403, n8404, n8405, n8406, n8407, n8408, n8409, n8410, n8411, + n8412, n8413, n8414, n8415, n8416, n8417, n8418, n8419, n8420, n8421, + n8422, n8423, n8424, n8425, n8426, n8427, n8428, n8429, n8430, n8431, + n8432, n8433, n8434, n8435, n8436, n8437, n8438, n8439, n8440, n8441, + n8442, n8443, n8444, n8445, n8446, n8447, n8448, n8449, n8450, n8451, + n8452, n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461, + n8462, n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471, + n8472, n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481, + n8482, n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491, + n8492, n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501, + n8502, n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511, + n8512, n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521, + n8522, n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8533, n8534, + n8535, n8540, n8541, n8542, n8543, n8544, n8546, n8548, n8550, n8552, + n8554, n8556, n8558, n8560, n8562, n8563, n8565, n8566, n8568, n8569, + n8571, n8572, n8574, n8576, n8577, n8579, n8580, n8582, n8584, n8586, + n8587, n8589, n8590, n8592, n8593, n8595, n8596, n8598, n8599, n8601, + n8602, n8604, n8605, n8607, n8608, n8610, n8614, n8616, n8618, n8620, + n8622, n8624, n8626, n8628, n8630, n8632, n8634, n8636, n8637, n8639, + n8641, n8642, n8644, n8645, n8647, n8648, n8649, n8650, n8651, n8652, + n8653, n8654, n8655, n8656, n8657, n8658, n8659, n8660, n8661, n8662, + n8663, n8664, n8665, n8667, n8668, n8669, n8670, n8671, n8673, n8674, + n8676, n8678, n8680, n8681, n8683, n8685, n8686, n8688, n8690, n8691, + n8693, n8695, n8696, n8698, n8700, n8701, n8703, n8705, n8706, n8708, + n8710, n8711, n8713, n8715, n8716, n8718, n8720, n8722, n8723, n8724, + n8726, n8728, n8730, n8732, n8734, n8736, n8738, n8740, n8742, n8744, + n8745, n8747, n8748, n8750, n8752, n8754, n8756, n8758, n8760, n8761, + n8762, n8764, n8766, n8768, n8770, n8771, n8772, n8774, n8776, n8778, + n8779, n8780, n8782, n8784, n8786, n8788, n8790, n8792, n8794, n8796, + n8798, n8800, n8802, n8804, n8806, n8808, n8810, n8812, n8814, n8816, + n8818, n8820, n8822, n8824, n8826, n8828, n8830, n8832, n8834, n8836, + n8838, n8839, n8841, n8842, n8844, n8845, n8847, n8849, n8851, n8853, + n8855, n8857, n8859, n8861, n8863, n8864, n8866, n8867, n8869, n8871, + n8873, n8874, n8876, n8877, n8879, n8881, n8883, n8884, n8886, n8887, + n8889, n8891, n8893, n8894, n8896, n8897, n8899, n8901, n8903, n8904, + n8906, n8907, n8909, n8910, n8912, n8914, n8915, n8917, n8919, n8920, + n8922, n8923, n8925, n8927, n8929, n8930, n8932, n8933, n8935, n8937, + n8939, n8940, n8942, n8943, n8945, n8947, n8949, n8950, n8952, n8954, + n8956, n8957, n8959, n8961, n8962, n8964, n8966, n8968, n8970, n8972, + n8974, n8976, n8978, n8980, n8982, n8984, n8986, n8988, n8990, n8992, + n8994, n8996, n8998, n9000, n9002, n9004, n9006, n9008, n9010, n9012, + n9014, n9016, n9018, n9020, n9022, n9024, n9026, n9028, n9030, n9032, + n9034, n9036, n9038, n9040, n9042, n9044, n9046, n9048, n9050, n9052, + n9054, n9056, n9058, n9060, n9062, n9064, n9066, n9068, n9070, n9071, + n9072, n9073, n9074, n9075, n9076, n9077, n9078, n9079, n9080, n9081, + n9082, n9083, n9084, n9085, n9086, n9087, n9088, n9089, n9090, n9091, + n9092, n9093, n9094, n9095, n9096, n9097, n9098, n9099, n9100, n9101, + n9102, n9103, n9104, n9105, n9106, n9107, n9108, n9109, n9110, n9111, + n9112, n9113, n9114, n9115, n9116, n9117, n9118, n9119, n9120, n9121, + n9122, n9123, n9124, n9125, n9126, n9127, n9128, n9129, n9130, n9131, + n9132, n9133, n9134, n9135, n9136, n9137, n9138, n9139, n9140, n9141, + n9142, n9143, n9144, n9145, n9146, n9147, n9148, n9149, n9150, n9151, + n9152, n9153, n9154, n9155, n9156, n9157, n9158, n9159, n9160, n9161, + n9162, n9163, n9164, n9165, n9166, n9167, n9168, n9169, n9170, n9171, + n9172, n9173, n9174, n9175, n9176, n9177, n9178, n9179, n9180, n9181, + n9182, n9183, n9184, n9185, n9186, n9187, n9188, n9189, n9190, n9191, + n9192, n9193, n9194, n9195, n9196, n9197, n9198, n9199, n9200, n9201, + n9202, n9203, n9204, n9205, n9206, n9207, n9208, n9209, n9210, n9211, + n9212, n9213, n9214, n9215, n9216, n9217, n9218, n9219, n9220, n9221, + n9222, n9223, n9224, n9225, n9226, n9227, n9228, n9229, n9230, n9231, + n9232, n9233, n9234, n9235, n9236, n9237, n9238, n9239, n9240, n9241, + n9242, n9243, n9244, n9245, n9246, n9247, n9248, n9249, n9250, n9251, + n9252, n9253, n9254, n9255, n9256, n9257, n9258, n9259, n9260, n9261, + n9262, n9263, n9264, n9265, n9266, n9267, n9268, n9269, n9270, n9271, + n9272, n9273, n9274, n9275, n9276, n9277, n9278, n9279, n9280, n9281, + n9282, n9283, n9284, n9285, n9286, n9287, n9288, n9289, n9290, n9291, + n9292, n9293, n9294, n9295, n9296, n9297, n9298, n9299, n9300, n9301, + n9302, n9303, n9304, n9305, n9306, n9307, n9308, n9309, n9310, n9311, + n9312, n9313, n9314, n9315, n9316, n9317, n9318, n9319, n9320, n9321, + n9322, n9323, n9324, n9325, n9326, n9327, n9328, n9329, n9330, n9331, + n9332, n9333, n9334, n9335, n9336, n9337, n9338, n9339, n9340, n9341, + n9342, n9343, n9344, n9345, n9346, n9347, n9348, n9349, n9350, n9351, + n9352, n9353, n9354, n9355, n9356, n9357, n9358, n9359, n9360, n9361, + n9362, n9363, n9364, n9365, n9366, n9367, n9368, n9369, n9370, n9371, + n9372, n9373, n9374, n9375, n9376, n9377, n9378, n9379, n9380, n9381, + n9382, n9383, n9384, n9385, n9386, n9387, n9388, n9389, n9390, n9391, + n9392, n9393, n9394, n9395, n9396, n9397, n9398, n9399, n9400, n9401, + n9402, n9417, n9418, n9419, n9420, n9421, n9422, n9423, n9424, n9425, + n9426, n9427, n9428, n9429, n9430, n9431, n9432, n9433, n9434, n9435, + n9436, n9437, n9438, n9439, n9440, n9441, n9442, n9443, n9444, n9445, + n9446, n9447, n9448, n9449, n9450, n9451, n9452, n9453, n9454, n9455, + n9456, n9457, n9458, n9459, n9460, n9461, n9462, n9463, n9464, n9465, + n9466, n9467, n9468, n9469, n9470, n9471, n9472, n9473, n9474, n687, + n692_1, n697_1, n702_1, n707_1, n712, n716, n721_1, n726_1, n731_1, + n736_1, n741_1, n746_1, n751_1, n756_1, n761_1, n766_1, n771_1, n776_1, + n780_1, n785_1, n790_1, n795_1, n800_1, n805_1, n810_1, n815_1, n820_1, + n823_1, n828_1, n833_1, n837_1, n841_1, n846_1, n851_1, n856_1, n861_1, + n866_1, n871_1, n876_1, n881_1, n886_1, n890_1, n895_1, n900_1, n905_1, + n910_1, n914_1, n919_1, n924_1, n929, n934_1, n939_1, n944_1, n948_1, + n953_1, n958_1, n963_1, n968_1, n973_1, n978_1, n983_1, n988_1, n993_1, + n998_1, n1003_1, n1008_1, n1013_1, n1018_1, n1022_1, n1026_1, n1031_1, + n1036_1, n1041_1, n1045_1, n1049_1, n1054_1, n1059_1, n1064_1, n1068_1, + n1072_1, n1077_1, n1082, n1087_1, n1092_1, n1097_1, n1102, n1107_1, + n1112_1, n1117, n1122_1, n1127, n1132_1, n1136_1, n1140_1, n1145_1, + n1150_1, n1155_1, n1160_1, n1165_1, n1170_1, n1174, n1177, n1181, + n1186, n1191_1, n1196_1, n1201_1, n1205_1, n1209_1, n1214, n1219_1, + n1224_1, n1228_1, n1232_1, n1237_1, n1242_1, n1247, n1252, n1257_1, + n1262, n1267_1, n1272_1, n1277_1, n1282_1, n1287_1, n1292_1, n1297_1, + n1302, n1307_1, n1312_1, n1317_1, n1322_1, n1327_1, n1331_1, n1335_1, + n1339_1, n1344, n1349_1, n1354_1, n1358_1, n1362_1, n1367, n1372_1, + n1377_1, n1382_1, n1387_1, n1392_1, n1397_1, n1402_1, n1407_1, n1411_1, + n1415_1, n1420, n1423, n1428_1, n1433_1, n1438_1, n1442, n1447, + n1452_1, n1457, n1462_1, n1467, n1472_1, n1477, n1481, n1485_1, n1490, + n1495_1, n1500, n1504, n1509, n1513, n1517, n1522_1, n1527, n1532_1, + n1537_1, n1542_1, n1547_1, n1552_1, n1557_1, n1562_1, n1567, n1572_1, + n1577_1, n1581, n1586, n1591_1, n1596_1, n1601_1, n1606_1, n1611_1, + n1616, n1621_1, n1626_1, n1631_1, n1636_1, n1641_1, n1646_1, n1650, + n1654, n1659, n1664_1, n1669_1, n1674, n1679_1, n1684_1, n1689_1, + n1694_1, n1699_1, n1704_1, n1709_1, n1714, n1717_1, n1722_1, n1727_1, + n1732_1, n1737_1, n1742_1, n1747_1, n1752, n1757_1, n1762_1, n1767_1, + n1772, n1777, n1782_1, n1787_1, n1792, n1797, n1802, n1807_1, n1812_1, + n1816_1, n1821_1, n1826_1, n1831_1, n1836_1, n1840, n1844_1, n1849_1, + n1854, n1859_1, n1864_1, n1868, n1873_1, n1878_1, n1883_1, n1888_1, + n1893_1, n1898_1, n1903_1, n1908_1, n1912_1, n1916_1, n1920_1, n1925_1, + n1930_1, n1935_1, n1940_1, n1945_1, n1950_1, n1955, n1959, n1964, + n1969_1, n1974_1, n1979_1, n1983_1, n1988, n1993_1, n1998_1, n2002_1, + n2007_1, n2012_1, n2017_1, n2022_1, n2027_1, n2031, n2035, n2040, + n2045, n2050, n2055_1, n2060, n2065_1, n2070, n2074, n2078_1, n2083, + n2087, n2092, n2096_1, n2101_1, n2106_1, n2111, n2116, n2120_1, n2124, + n2127_1, n2131_1, n2136, n2141_1, n2146, n2150, n2154, n2159_1, + n2164_1, n2169_1, n2173_1, n2178, n2183_1, n2188_1, n2193, n2198, + n2203_1, n2208_1, n2212, n2217_1, n2222, n2227, n2232_1, n2237_1, + n2242_1, n2247, n2252, n2257, n2261_1, n2265, n2270_1, n2275, n2280_1, + n2285_1, n2289_1, n2293_1, n2297_1, n2301_1, n2306, n2309_1, n2313, + n2318_1, n2323_1, n2328_1, n2331_1, n2336_1, n2341_1, n2345_1, n2349_1, + n2354_1, n2359_1, n2364_1, n2369_1, n2374_1, n2379_1, n2384_1, n2388_1, + n2393_1, n2398_1, n2403_1, n2408_1, n2413, n2418, n2423, n2428_1, + n2432, n2436_1, n2441_1, n2445, n2449_1, n2454_1, n2458, n2463_1, + n2468_1, n2473_1, n2478_1, n2483, n2488_1, n2493, n2498_1, n2502, + n2506, n2511_1, n2516, n2521_1, n2525, n2530, n2535_1, n2540, n2545_1, + n2550_1, n2555_1, n2560_1, n2565_1, n2570, n2575, n2580_1, n2585_1, + n2590_1, n2595_1, n2600_1, n2605_1, n2610_1, n2615_1, n2619_1, n2624_1, + n2629_1, n2634_1, n2639_1, n2644_1, n2649_1, n2654, n2659_1, n2663, + n2668_1, n2672_1, n2677_1, n2682_1, n2687_1, n2692_1, n2697, n2701_1, + n2705_1, n2710_1, n2715_1, n2720_1, n2725_1, n2729_1, n2733_1, n2738_1, + n2743, n2748_1, n2752_1, n2755_1, n2760_1, n2765_1, n2770, n2774_1, + n2778_1, n2783_1, n2788_1, n2793_1, n2798_1, n2803_1, n2808_1, n2813_1, + n2818_1, n2823_1, n2828, n2833_1, n2838_1, n2843_1, n2848_1, n2852_1, + n2857_1, n2862_1, n2867_1, n2872_1, n2876_1, n2881_1, n2885_1, n2890_1, + n2895_1, n2899_1, n2904_1, n2909_1, n2914_1, n2919_1, n2924_1, n2929_1, + n2934_1, n2937_1, n2941_1, n2946_1, n2951_1, n2956_1, n2961_1, n2966_1, + n2971_1, n2975_1, n2979_1, n2984_1, n2989_1, n2994_1, n2999_1, n3004_1, + n3009_1, n3013_1, n3018_1, n3023_1, n3028_1, n3033_1, n3038_1, n3042_1, + n3047, n3052, n3057, n3061, n3065_1, n3070, n3075, n3079, n3082, + n3086_1, n3091, n3096_1, n3101_1, n3106, n3111, n3116_1, n3121, n3126, + n3131_1, n3136, n3141_1, n3146, n3151_1, n3156_1, n3161, n3165, + n3170_1, n3175_1, n3180_1, n3185_1, n3190, n3195, n3200, n3205, + n3210_1, n3215, n3219_1, n3223_1, n3228, n3232_1, n3237, n3242_1, + n3247_1, n3252, n3257_1, n3262_1, n3267, n3270, n3275_1, n3279_1, + n3282_1, n3286_1, n3291_1, n3296_1, n3301, n3306_1, n3311, n3316_1, + n3321, n3326_1, n3331_1, n3336, n3340_1, n3345, n3350_1, n3355_1, + n3360, n3365_1, n3370_1, n3375, n3379, n3382_1, n3386_1, n3391_1, + n3396_1, n3401_1, n3406_1, n3411, n3416, n3421_1, n3426_1, n3431_1, + n3435_1, n3439, n3444_1, n3449, n3454, n3459_1, n3464_1, n3468_1, + n3471, n3476_1, n3480_1, n3485_1, n3490, n3495_1, n3500_1, n3505, + n3510_1, n3515, n3519_1, n3524, n3528_1, n3533, n3538, n3543, n3548, + n3553, n3558, n3561, n3566_1, n3571_1, n3576, n3581_1, n3586_1, + n3591_1, n3595, n3599, n3604, n3608_1, n3613_1, n3618_1, n3623, n3627, + n3631, n3636_1, n3641, n3646_1, n3651_1, n3656_1, n3661, n3665_1, + n3670_1, n3675, n3680_1, n3685_1, n3690_1, n3695, n3700, n3705, + n3710_1, n3715_1, n3720_1, n3725, n3730, n3735, n3740, n3745, n3750_1, + n3755_1, n3760, n3765_1, n3770_1, n3775, n3779, n3783_1, n3788_1, + n3792, n3797_1, n3802_1, n3807_1, n3812_1, n3817_1, n3822_1, n3827_1, + n3832_1, n3837_1, n3842_1, n3847_1, n3851_1, n3856, n3861_1, n3866_1, + n3871_1, n3876_1, n3881_1, n3886, n3891_1, n3896, n3900_1, n3903_1, + n3907_1, n3912, n3917, n3922, n3927, n3932, n3937_1, n3942_1, n3947, + n3952_1, n3957_1, n3962, n3967_1, n3971_1, n3975, n3980_1, n3984_1, + n3988, n3992, n3996_1, n4001, n4006, n4010_1, n4015, n4020, n4025_1, + n4030, n4035_1, n4039_1, n4042, n4047_1, n4052_1, n4057, n4062, n4066, + n4070_1, n4075, n4080, n4084, n4089_1, n4094_1, n4099, n4104, n4109, + n4114_1, n4119, n4124, n4128, n4133_1, n4138_1, n4142_1, n4147, n4151, + n4156_1, n4160_1, n4164, n4169_1, n4174, n4178_1, n4182_1, n4187, + n4192_1, n4197, n4202_1, n4206, n4211_1, n4216, n4221_1, n4226_1, + n4231_1, n4235_1, n4239_1, n4244, n4249, n4254, n4259_1, n4263_1, + n4267_1, n4272_1, n4277_1, n4282, n4287_1, n4291_1, n4296_1, n4301_1, + n4306, n4311_1, n4316_1, n4321_1, n4326_1, n4331_1, n4336_1, n4340_1, + n4344_1, n4349_1, n4354_1, n4359_1, n4364_1, n4369, n4374_1, n4379_1, + n4384_1, n4389_1, n4393_1, n4397_1, n4402_1, n4407_1, n4412_1, n4417_1, + n4422, n4427_1, n4432_1, n4437, n4442_1, n4447, n4452, n4456, n4460, + n4465_1, n4470, n4475, n4480, n4485, n4489, n4492_1, n4495, n4499, + n4504, n4509_1, n4514, n4519, n4524, n4529, n4534, n4539, n4544_1, + n4549, n4554, n4559_1, n4564_1, n4569_1, n4574, n4578, n4582_1, + n4587_1, n4592, n4597_1, n4602, n4607, n4612, n4617, n4622, n4627, + n4631, n4636, n4640_1, n4644, n4648, n4652_1, n4657_1, n4662, n4667_1, + n4672_1, n4677_1, n4682, n4687, n4692_1, n4697_1, n4702_1, n4707_1, + n4712_1, n4717_1, n4722_1, n4727_1, n4731_1, n4736_1, n4741_1, n4746, + n4751_1, n4756, n4761_1, n4766, n4770_1, n4773_1, n4777_1, n4782, + n4787_1, n4792_1, n4797, n4802, n4807_1, n4812, n4817, n4822, n4827, + n4832_1, n4837_1, n4842_1, n4846_1, n4851_1, n4855_1, n4859_1, n4864_1, + n4868_1, n4873_1, n4877, n4882, n4887_1, n4890, n4894_1, n4899, n4904, + n4909_1, n4914_1, n4919_1, n4924_1, n4929_1, n4934_1, n4939, n4944, + n4948_1, n4953_1, n4958_1, n4963_1, n4968_1, n4973, n4978, n4983_1, + n4987, n4992, n4997, n5002, n5007, n5011_1, n5016, n5021, n5026, + n5031_1, n5036, n5041, n5046_1, n5051_1, n5056_1, n5060, n5064, n5069, + n5074_1, n5079_1, n5083_1, n5088_1, n5093_1, n5098, n5103, n5107, + n5111, n5116, n5121, n5126, n5131, n5136_1, n5141, n5146, n5151_1, + n5156, n5160_1, n5165_1, n5170_1, n5175_1, n5180_1, n5185_1, n5190_1, + n5195_1, n5200_1, n5205_1, n5210_1, n5214_1, n5218_1, n5223_1, n5228_1, + n5233_1, n5237_1, n5241_1, n5246_1, n5251, n5256_1, n5261, n5265_1, + n5269_1, n5273, n5278_1, n5283_1, n5288_1, n5293_1, n5298, n5303_1, + n5308_1, n5313_1, n5318, n5322, n5326_1, n5331_1, n5335_1, n5339_1, + n5344_1, n5349, n5353_1, n5356_1, n5361_1, n5366_1, n5371_1, n5376_1, + n5381_1, n5385_1, n5389_1, n5393_1, n5398_1, n5402_1, n5406_1, n5411_1, + n5416, n5421_1, n5426_1, n5431_1, n5436, n5441_1, n5446_1, n5451_1, + n5456_1, n5461, n5466_1, n5471_1, n5476_1, n5481_1, n5486_1, n5491_1, + n5496_1, n5501_1, n5506_1, n5511_1, n5516_1, n5521_1, n5526_1, n5531_1, + n5536_1, n5541_1, n5545_1, n5549_1, n5554_1, n5558_1, n5563_1, n5568_1, + n5573_1, n5578_1, n5583_1, n5588_1, n5593_1, n5598, n5603_1, n5608_1, + n5613_1, n5618_1, n5623_1, n5628, n5633, n5638, n5643_1, n5648_1, + n5653, n5658_1, n5662, n5666_1, n5671, n5676_1, n5681_1, n5686, n5690, + n5695, n5700_1, n5705_1, n5710_1, n5714, n5718, n5723_1, n5728, + n5733_1, n5738_1, n5743_1, n5748, n5753, n5758_1, n5763, n5768, n5772, + n5776, n5781_1, n5786, n5791, n5796, n5801, n5806, n5811, n5816_1, + n5821_1, n5825_1, n5828_1, n5833_1, n5838_1, n5842_1, n5846, n5850_1, + n5855_1, n5859, n5864, n5869, n5874, n5879_1, n5884, n5888_1, n5893_1, + n5898, n5903_1, n5908_1, n5913_1, n5918_1, n5923_1, n5928_1, n5933_1, + n5937, n5941_1, n5946_1, n5951_1, n5956, n5961_1, n5966_1, n5971_1, + n5975_1, n5980_1, n5985_1, n5990, n5994_1, n5998, n6003_1, n6008, + n6012, n6017, n6022_1, n6027, n6032_1, n6037_1, n6042, n6047_1, + n6052_1, n6056, n6061, n6066_1, n6071_1, n6076_1, n6081, n6086_1, + n6091, n6096, n6100_1, n6104, n6109_1, n6114_1, n6119_1, n6123_1, + n6127, n6132_1, n6137, n6142, n6147, n6152, n6156, n6160, n6165, n6169, + n6174_1, n6179, n6183, n6188_1, n6192, n6196, n6201_1, n6206, n6211, + n6216, n6221, n6226, n6230, n6235, n6240, n6245, n6250, n6255, n6260, + n6265, n6270, n6275, n6279, n6284, n6289, n6293, n6297, n6302, n6306_1, + n6310, n6315, n6320, n6325_1, n6330, n6335, n6340, n6344_1, n6349, + n6354, n6359, n6364_1, n6369, n6373, n6376, n6380, n6385, n6390, n6395, + n6399, n6403, n6408_1, n6413, n6417, n6422, n6427, n6432, n6437, n6442, + n6447, n6452, n6457, n6462, n6467, n6472, n6477, n6482, n6487, n6492, + n6497, n6502, n6507, n6512, n6517, n6522, n6526, n6531, n6536, n6541, + n6546, n6551, n6555, n6560, n6565, n6570, n6575, n6580, n6585, n6590, + n6595, n6600, n6605, n6610, n6615, n6620, n6624, n6629, n6634, n6638, + n6642, n6646, n6651, n6656, n6661, n6665, n6670, n6675, n6680; + assign Pg34972 = ~n8177 | ~Ng22; + assign n4124_1 = Ng4369 & (Ng4366 | n6090); + assign Pg34927 = ~n5895 | ~Ng22; + assign Pg34925 = ~n5912 | ~Ng22; + assign Pg34923 = ~n4252 | ~Ng22; + assign Pg34921 = ~n5892 | ~Ng22; + assign Pg34919 = ~n5869_1 | ~Ng22; + assign Pg34917 = ~n5669 | ~Ng22; + assign Pg34915 = ~n5903 | ~Ng22; + assign Pg34913 = ~n4909 | ~Ng22; + assign n4133 = Ng890 & (Ng528 | n5931 | ~Ng479); + assign Pg34597 = 1'b0; + assign n4135 = ~Pg113 | ~Ng2868; + assign n4136 = ~Pg113 | ~Ng2873; + assign Pg34435 = ~n9417; + assign Pg34425 = ~n5945 | ~n6265_1; + assign Pg34383 = ~n6264 | n5901 | ~n5930; + assign Pg34240 = 1'b0; + assign Pg34239 = 1'b0; + assign Pg34238 = 1'b0; + assign Pg34237 = 1'b0; + assign Pg34236 = 1'b0; + assign Pg34235 = 1'b0; + assign Pg34234 = 1'b0; + assign Pg34233 = 1'b0; + assign Pg34232 = 1'b0; + assign Pg34221 = ~n5929 | ~n6265_1; + assign Pg34201 = ~n6264 | n5938 | ~n6122; + assign n4151_1 = Ng4646 & (n5875 | n5915); + assign Pg33950 = 1'b0; + assign Pg33949 = 1'b0; + assign Pg33948 = 1'b0; + assign Pg33947 = 1'b0; + assign Pg33946 = 1'b0; + assign Pg33945 = 1'b0; + assign Pg33935 = ~n5936; + assign Pg33874 = ~Ng4507 | \[4507] | n5924; + assign Pg33659 = ~n9418 | n5947 | ~n6264; + assign Pg33636 = ~n5950; + assign n4162 = Pg17291 & (~Ng1171 | n5914); + assign Pg33435 = (n9185 & (~Ng2729 | n9186)) | (Ng2729 & n9186); + assign Pg33079 = (n9183 & (~Ng2729 | n9184)) | (Ng2729 & n9184); + assign Pg32975 = ~n7527; + assign Pg32454 = 1'b0; + assign Pg32429 = 1'b0; + assign Pg32185 = n6847 & n6844 & n6845 & n6846; + assign Pg31863 = ~n8207; + assign Pg31862 = ~n8080; + assign Pg31860 = ~n8192; + assign Pg31793 = ~n4220; + assign Pg31521 = ~n9417; + assign Pg30331 = ~Ng2831; + assign Pg30330 = ~Ng2834; + assign Pg30329 = ~\[4426] ; + assign Pg30327 = ~Ng37; + assign Pg28042 = n4218 | n4219; + assign Pg28041 = n4217 | ~n8478; + assign Pg28030 = n4215 | n4216_1; + assign Pg26877 = ~n4214; + assign Pg26876 = ~n4211; + assign Pg26875 = ~n4208; + assign Pg26801 = ~n7527; + assign Pg25590 = 1'b0; + assign Pg25589 = 1'b0; + assign Pg25588 = 1'b0; + assign Pg25587 = 1'b0; + assign Pg25586 = 1'b0; + assign Pg25585 = 1'b0; + assign Pg25584 = 1'b0; + assign Pg25583 = 1'b0; + assign Pg25582 = 1'b0; + assign Pg25259 = ~n8080; + assign Pg25167 = ~n8207; + assign Pg25114 = ~n8192; + assign Pg24151 = 1'b0; + assign Pg23759 = ~Ng2831; + assign Pg23652 = ~Ng2834; + assign Pg23612 = ~\[4426] ; + assign Pg23190 = ~Ng25 & ~Ng22; + assign Pg23002 = ~Ng37; + assign Pg21727 = ~Pg35 & Ng3003; + assign Pg12833 = ~Pg5; + assign n4205 = ~Pg35 | n8382; + assign n4206_1 = Ng1830 | Ng2098 | Ng1696 | Ng1964; + assign n4207 = n6127_1 & Pg35; + assign n4208 = n4206_1 & n4207; + assign n4209 = Ng1710 | Ng1858 | Ng1844 | Ng2126 | Ng1724 | Ng2112 | Ng1992 | Ng1978; + assign n4210 = n5989 & Pg35; + assign n4211 = n4209 & n4210; + assign n4212 = Ng1913 | Ng2047 | Ng1932 | Ng1798 | Ng1664 | Ng1779 | Ng1644 | Ng2066; + assign n4213 = n5988 & Pg35; + assign n4214 = n4212 & n4213; + assign n4215 = n7837 & ~n8125 & (~n5906 | ~n8212); + assign n4216_1 = ~n5906 & (~n5902 | ~n5905) & n7838; + assign n4217 = ~Pg35 | n6128; + assign n4218 = ~Pg35 | Ng962; + assign n4219 = ~Pg35 | Ng1306; + assign n4220 = n6888 & (n6889 | n6890 | ~n9117); + assign n4221 = n6702 & n6703 & (Pg35 | ~Ng5052); + assign n687 = ~n4221; + assign n4223 = n6247 & (n6241 | n6246 | n6238); + assign n692_1 = ~n4223; + assign n4225 = n6439 & n6440 & (~n6006 | n6441); + assign n697_1 = ~n4225; + assign n4227 = n6374 & (Pg35 | ~Ng2380); + assign n702_1 = ~n4227; + assign n4229 = n7300 & n7301 & (n4205 | n7302); + assign n721_1 = ~n4229; + assign n4231 = n7273 & n7274 & (n4205 | n7275); + assign n731_1 = ~n4231; + assign n4233 = n7141 & n7142 & (n4205 | n7143); + assign n736_1 = ~n4233; + assign n4235 = n6172 & (Pg35 | ~Ng2984); + assign n746_1 = ~n4235; + assign n4237 = n6460 & n6461 & (~n5998_1 | n6462_1); + assign n751_1 = ~n4237; + assign n4239 = n7041 & n7042 & (n4205 | n7043); + assign n756_1 = ~n4239; + assign n4241 = (n6452_1 | ~Ng1802) & (n6616 | ~Ng1772); + assign n761_1 = ~n4241; + assign n4243 = n7229 & n7230 & (n4205 | n6723); + assign n766_1 = ~n4243; + assign n4245 = (~Ng6215 | n6667) & (~Ng6219 | n6668); + assign n771_1 = ~n4245; + assign n4247 = n6098 & n6099 & (Ng807 | n6093); + assign n776_1 = ~n4247; + assign n4249_1 = Ng1061 ^ n8020; + assign n790_1 = n4249_1 | ~n9152; + assign n4251 = Ng4172 | Ng4153; + assign n4252 = n6024 & n6021 & n6022 & n6023; + assign n795_1 = n4251 & Pg35; + assign n4254_1 = (n6726 | n6732) & (Pg35 | ~Ng3506); + assign n805_1 = ~n4254_1; + assign n4256 = n6874 & n6875 & (Ng749 | n6876); + assign n810_1 = ~n4256; + assign n4258 = (~Pg17739 & (~Pg14738 | Pg12350)) | (Pg14738 & Pg12350); + assign n820_1 = n4258 & ~Pg13068 & ~Pg17607 & Pg35 & ~Pg17646; + assign n4260 = n6483 & n6484 & (~n6010 | n6485); + assign n828_1 = ~n4260; + assign n4262 = n6623 & n6624_1 & (~n8312 | ~Ng1714); + assign n833_1 = ~n4262; + assign n841_1 = ~n6738 & ~Ng3155; + assign n4265 = n7692 & n7693 & (~Ng2165 | ~n8424); + assign n846_1 = ~n4265; + assign n4267 = ~Ng3689 | n8508; + assign n856_1 = Ng3694 & (~Pg35 | n4267); + assign n4269 = n6463 & n6464 & (~n5998_1 | n6465); + assign n861_1 = ~n4269; + assign n4271 = n7364 & (Pg35 | ~Ng1964); + assign n866_1 = ~n4271; + assign n4273 = (~Ng4621 | n6202) & (n6201 | ~Ng4639); + assign n871_1 = ~n4273; + assign n4275 = n7067 & n7068 & (n4205 | n7069); + assign n876_1 = ~n4275; + assign n4277 = n7340 & ~n9252 & (Pg35 | ~Ng2652); + assign n881_1 = ~n4277; + assign n4279 = (~Pg17711 & (~Pg14694 | Pg12300)) | (Pg14694 & Pg12300); + assign n886_1 = n4279 & ~Pg13049 & ~Pg17580 & Pg35 & ~Pg17604; + assign n4281 = n7755 & n7756 & (Ng490 | ~n8470); + assign n890_1 = ~n4281; + assign n4283 = n6293_1 & n6294 & (Ng772 | n6295); + assign n900_1 = ~n4283; + assign n4285 = n7081 & n7082 & (n4205 | n7083); + assign n905_1 = ~n4285; + assign n4287 = n7437 & ~n9281 & (~Ng6177 | n7438); + assign n910_1 = ~n4287; + assign n4289 = (n6738 | n6739) & (Pg35 | ~Ng3161); + assign n919_1 = ~n4289; + assign n4291 = n7061 & n7062 & (n4205 | n7063); + assign n924_1 = ~n4291; + assign n4293 = ~n5990_1 & n6706 & (~n6860 | ~Ng4543); + assign n929 = ~n4293; + assign n4295 = n7625 & (Ng3457 | n7626) & ~n9308; + assign n934_1 = ~n4295; + assign n4297 = n6969 & ~n9452 & (n4205 | n6970); + assign n939_1 = ~n4297; + assign n4299 = n6352 & n6353 & (~n6000 | n6354_1); + assign n948_1 = ~n4299; + assign n4301 = n6326 & (n6327 | n6328 | ~Ng4801); + assign n953_1 = ~n4301; + assign n4303 = n6221_1 & n6222 & (Pg35 | ~Ng4584); + assign n958_1 = ~n4303; + assign n4305 = ~Pg35 | ~Ng6199; + assign n963_1 = ~n4305; + assign n4307 = n6388 & n6389 & (~n6012_1 | n6390_1); + assign n968_1 = ~n4307; + assign n4309 = n7962 & n7963 & (Pg35 | ~Ng1379); + assign n973_1 = ~n4309; + assign n4311 = n8005 & (Pg35 | ~Ng1579); + assign n978_1 = ~n4311; + assign n4313 = (~Ng5176 | n6696) & (~Ng5180 | n6697); + assign n983_1 = ~n4313; + assign n4315 = n6179_1 & (Pg35 | ~Ng2890); + assign n988_1 = ~n4315; + assign n4317 = n6870 & n6871 & (Pg35 | ~Ng1018); + assign n993_1 = ~n4317; + assign n4319 = n7078 & n7079 & (n4205 | n7080); + assign n998_1 = ~n4319; + assign n4321 = n7242 & n7243 & (n4205 | n7244); + assign n1003_1 = ~n4321; + assign n4323 = (n8033 | ~Ng4258) & (n7997 | ~Ng4264); + assign n1008_1 = ~n4323; + assign n4325 = n6486 & n6487_1 & (Ng767 | n6488); + assign n1013_1 = ~n4325; + assign n4327 = ~Pg35 | ~Ng5853; + assign n1018_1 = ~n4327; + assign n4329 = n6277 & n6278 & (n6279_1 | n6276); + assign n1031_1 = ~n4329; + assign n4331 = ~Pg35 | ~Ng5507; + assign n1041_1 = ~n4331; + assign n4333 = n6966 & n6967 & (n4205 | n6968); + assign n1049_1 = ~n4333; + assign n4335 = n6650 & n6651_1 & (Pg35 | ~Ng291); + assign n1054_1 = ~n4335; + assign n4337 = n7057 & ~n9458 & (n4205 | n6682); + assign n1059_1 = ~n4337; + assign n4339 = ~n7985 & (Pg35 | ~Ng559); + assign n1077_1 = ~n4339; + assign n4341 = n6258 & (Ng608 | n6259) & ~n9441; + assign n1082 = ~n4341; + assign n4343 = n7213 & n7214 & (n4205 | n7215); + assign n1092_1 = ~n4343; + assign n4345 = n6946 & n6947 & (n4205 | n6948); + assign n1097_1 = ~n4345; + assign n4347 = n7003 & ~n9455 & (n4205 | n6673); + assign n1102 = ~n4347; + assign n4349 = (~Ng921 | n7975) & (n7974 | ~Ng904); + assign n1107_1 = ~n4349; + assign n4351 = ~Pg35 | ~n8251; + assign n1127 = Ng4871 & n4351; + assign n4353 = n7114 & n7115 & (n4205 | n7116); + assign n1132_1 = ~n4353; + assign n4355 = n7237 & n7238 & (n4205 | n7239); + assign n1140_1 = ~n4355; + assign n4357 = n6799 & n6800 & (n6795 | ~Ng1926); + assign n1145_1 = ~n4357; + assign n4359 = (n6668 | n6669) & (Pg35 | ~Ng6209); + assign n1150_1 = ~n4359; + assign n4361 = n7250 & n7251 & (n4205 | n7252); + assign n1155_1 = ~n4361; + assign n4363 = n6840 & n6841 & (Pg35 | ~Ng287); + assign n1160_1 = ~n4363; + assign n4365 = ~Pg35 | ~n8253; + assign n1165_1 = Ng4646 & n4365; + assign n4367 = n7261 & n7262 & (n4205 | n7263); + assign n1170_1 = ~n4367; + assign n4369_1 = n6609 & (n6433 | ~Ng1862); + assign n1181 = ~n4369_1; + assign n4371 = n7748 & n7749 & (Pg35 | ~Ng671); + assign n1186 = ~n4371; + assign n4373 = Ng843 ^ n8022; + assign n1191_1 = Ng837 & (~Pg35 | n4373); + assign n4375 = n6215 & (n6216_1 | ~Ng4322 | ~n8236); + assign n1196_1 = ~n4375; + assign n4377 = (Pg35 | ~Ng6395) & (n6503 | ~n9421); + assign n1209_1 = ~n4377; + assign n4379 = n6132 & n6133 & (Ng622 | n6134); + assign n1214 = ~n4379; + assign n1219_1 = ~n6728 & ~Ng3506; + assign n4382 = n7333 & (Pg35 | ~Ng2834); + assign n1237_1 = ~n4382; + assign n4384 = Ng255 | Ng269 | Ng262 | ~Ng246 | ~Ng239 | ~Ng232 | ~Ng225; + assign n4385 = Ng255 & Ng262 & Ng269 & ~Ng225 & ~Ng232 & ~Ng246 & ~Ng239; + assign n1252 = n4384 & Pg35 & (Ng278 | n4385); + assign n1262 = Ng4836 & n4351; + assign n4388 = (~Ng1036 | ~n9116) & (n6642_1 | ~Ng1030); + assign n1267_1 = ~n4388; + assign n4390 = n7554 & n7763 & (Pg35 | ~Ng5272); + assign n1272_1 = ~n4390; + assign n4392 = n7303 & ~n9469 & (n4205 | n7304); + assign n1282_1 = ~n4392; + assign n4394 = n7434 & (n4205 | (Ng6195 & n7435)); + assign n1292_1 = ~n4394; + assign n4396 = n7883 & n7884 & (Ng1135 | ~n8486); + assign n1297_1 = ~n4396; + assign n4398 = n6504 & n6505 & (n6506 | ~Ng6395); + assign n1302 = ~n4398; + assign n4400 = n6092 & (n6093 | ~Ng807); + assign n1312_1 = ~n4400; + assign n4402 = ~Pg35 | ~Ng3853; + assign n1322_1 = ~n4402; + assign n4404 = n6759 & n6760 & (n6755 | ~Ng2485); + assign n1339_1 = ~n4404; + assign n4406 = n6832 & n6833 & (Ng925 | n6834); + assign n1344 = ~n4406; + assign n4408 = n7099 & n7100 & (n4205 | n7101); + assign n1354_1 = ~n4408; + assign n4410 = n6807 & n6808 & (~Ng1798 | n6806); + assign n1362_1 = ~n4410; + assign n4412 = n6521 & n7806 & (Ng4076 | n7807); + assign n1367 = ~n4412; + assign n4414 = n7175 & n7176 & (n4205 | n6713); + assign n1377_1 = ~n4414; + assign n4416 = n6645 & n6646_1 & (Ng763 | n6647); + assign n1382_1 = ~n4416; + assign n4418 = n6987 & n6988 & (n4205 | n6989); + assign n1387_1 = ~n4418; + assign n4420 = n7852 & (Pg35 | ~Ng4427); + assign n1392_1 = ~n4420; + assign n1397_1 = Ng4864 & n4351; + assign n4423 = n6157 & (Pg35 | ~Ng4717); + assign n1402_1 = ~n4423; + assign n4425 = n6838 & (Ng590 | n6839) & ~n9448; + assign n1407_1 = ~n4425; + assign n4427 = ~n7376 & ~n9274 & (Pg35 | ~Ng1612); + assign n1415_1 = ~n4427; + assign n4429 = (~Pg17674 & (~Pg14662 | Pg12238)) | (Pg14662 & Pg12238); + assign n1420 = n4429 & ~Pg13039 & ~Pg17519 & Pg35 & ~Pg17577; + assign n4431 = n7463 & (Ng6154 | n7464) & ~n9284; + assign n1438_1 = ~n4431; + assign n4433 = n7054 & n7055 & (n4205 | n7056); + assign n1447 = ~n4433; + assign n4435 = n6455 & n6456 & (~n5998_1 | ~n8308); + assign n1452_1 = ~n4435; + assign n4437_1 = n7395 & n7396 & (Ng744 | n7397); + assign n1462_1 = ~n4437_1; + assign n4439 = n6156_1 & (Pg35 | ~Ng4722); + assign n1467 = ~n4439; + assign n4441 = n6981 & n6982 & (n4205 | n6983); + assign n1477 = ~n4441; + assign n4443 = n6999 & (Pg35 | ~Ng5961); + assign n1490 = ~n4443; + assign n4445 = n8018 & n8019 & (~Pg17400 | n8014); + assign n1500 = ~n4445; + assign n1504 = Ng4633 & (~Pg35 | (~Ng4639 & ~n6208)); + assign n4448 = n7120 & n7121 & (n4205 | n7122); + assign n1509 = ~n4448; + assign n4450 = ~Pg35 | ~Ng5160; + assign n1522_1 = ~n4450; + assign n4452_1 = n7026 & n7027 & (n4205 | n7028); + assign n1527 = ~n4452_1; + assign n4454 = n6140 & n6141; + assign n1542_1 = ~n4454; + assign n4456_1 = ~Pg35 | ~Ng3151; + assign n1547_1 = ~n4456_1; + assign n4458 = (Pg35 | ~Ng3522) & (n6725 | n6726); + assign n1562_1 = ~n4458; + assign n4460_1 = n6521 & n6522_1 & (Ng4104 | n6523); + assign n1567 = ~n4460_1; + assign n4462 = n9378 ^ Pg9251; + assign n1577_1 = n4462 & Pg35; + assign n4464 = n6399_1 & n6400 & (~n6008_1 | ~n8287); + assign n1581 = ~n4464; + assign n4466 = n6576 & (n6377 | ~Ng2287); + assign n1601_1 = ~n4466; + assign n4468 = (~Ng4269 | n8000) & (n7999 | ~Ng4273); + assign n1606_1 = ~n4468; + assign n4470_1 = n7880 & ~n9437 & (Pg35 | ~Ng1384); + assign n1611_1 = ~n4470_1; + assign n4472 = n7467 & (Pg35 | ~Ng5831); + assign n1621_1 = ~n4472; + assign n4474 = n5959 & (~Ng1193 | (~Ng1171 & Ng1183)); + assign n4475_1 = Pg7916 ^ Ng1171; + assign n1626_1 = Pg35 & (n4474 | n4475_1); + assign n4477 = (~Ng4264 | n8032) & (n7998 | ~Ng4269); + assign n1631_1 = ~n4477; + assign n4479 = (n6311 | n6312) & (Pg35 | ~Ng4818); + assign n1641_1 = ~n4479; + assign n4481 = n7064 & n7065 & (n4205 | n7066); + assign n1646_1 = ~n4481; + assign n4483 = Ng4864 | Ng4878 | Ng4836 | Ng4871; + assign n1654 = Pg35 & ~n9298 & (n4483 | ~n8760); + assign n4485_1 = n7954 & (Pg35 | ~Ng3139); + assign n1659 = ~n4485_1; + assign n4487 = n7305 & ~n9470 & (n4205 | n7306); + assign n1674 = ~n4487; + assign n4489_1 = ~n5990_1 & ~n5993 & (~n6860 | ~Ng4540); + assign n1679_1 = ~n4489_1; + assign n4491 = n7264 & n7265 & (n4205 | n7266); + assign n1684_1 = ~n4491; + assign n4493 = n7767 & (~Pg35 | n7766 | n7768); + assign n1694_1 = ~n4493; + assign n4495_1 = n6152_1 & (Pg35 | ~Ng4912); + assign n1699_1 = ~n4495_1; + assign n4497 = n7354 & (Pg35 | ~Ng2255); + assign n1704_1 = ~n4497; + assign n4499_1 = n6227 & (n6228 | n6226_1 | n6229); + assign n1709_1 = ~n4499_1; + assign n4501 = n7858 & (~Ng4375 | (Pg35 & ~Ng4382)); + assign n1714 = ~n4501; + assign n4503 = n6178 & (Pg35 | ~Ng2844); + assign n1722_1 = ~n4503; + assign n4505 = (n7758 | ~Ng417) & (n8027 | ~Ng446); + assign n1727_1 = ~n4505; + assign n4507 = n7044 & n7045 & (n4205 | n7046); + assign n1747_1 = ~n4507; + assign n4509 = n7951 & (Pg35 | ~Ng3490); + assign n1757_1 = ~n4509; + assign n1762_1 = ~n6687 & ~Ng5511; + assign n4512 = (n6728 | n6729) & (Pg35 | ~Ng3512); + assign n1767_1 = ~n4512; + assign n4514_1 = n6467_1 & (Pg35 | ~Ng1687); + assign n1772 = ~n4514_1; + assign n4516 = n7495 & n7761 & (Pg35 | ~Ng5965); + assign n1782_1 = ~n4516; + assign n4518 = n7855 & n7856 & n7857; + assign n1787_1 = ~n4518; + assign n4520 = Ng518 & Ng203 & ~Ng513; + assign n4521 = Ng182 & (Ng168 | Ng174); + assign n4522 = Ng168 & Ng174; + assign n1797 = Pg35 & n4520 & (n4521 | n4522); + assign n4524_1 = n7171 & (Pg35 | ~Ng3961); + assign n1802 = ~n4524_1; + assign n4526 = (n7790 | ~n9147) & (n7791 | ~Ng4749); + assign n1807_1 = ~n4526; + assign n4528 = n6411 & (Pg35 | ~Ng2089); + assign n1812_1 = ~n4528; + assign n4530 = n7198 & n7199 & (n4205 | n7200); + assign n1821_1 = ~n4530; + assign n4532 = Ng1052 ^ n7888; + assign n1836_1 = Pg35 & n4532 & ~Ng979; + assign n4534_1 = n6562 & n6563 & (n6359_1 | ~Ng2465); + assign n1849_1 = ~n4534_1; + assign n4536 = n7050 & n7051 & (n4205 | n7052); + assign n1854 = ~n4536; + assign n4538 = ~n5990_1 & n6708 & (~n6860 | ~Ng4480); + assign n1859_1 = ~n4538; + assign n1864_1 = ~Ng358 & Pg35 & ~Pg8719; + assign n4541 = (Pg35 | ~Ng3171) & (n6735 | n6736); + assign n1873_1 = ~n4541; + assign n4543 = n6620_1 & (n6452_1 | ~Ng1728); + assign n1878_1 = ~n4543; + assign n4545 = n6356 & (Pg35 | ~Ng2514); + assign n1883_1 = ~n4545; + assign n4547 = n7569 & (Pg35 | ~Ng3831); + assign n1888_1 = ~n4547; + assign n4549_1 = ~Pg35 | ~Ng4917; + assign n1898_1 = ~n4549_1; + assign n4551 = (Pg35 | ~Ng1199) & (n4474 | ~n8747); + assign n1903_1 = ~n4551; + assign n4553 = (n7903 | n7904) & (Pg35 | ~Ng832); + assign n1908_1 = ~n4553; + assign n4555 = n7392 & n7393 & (Ng914 | n7394); + assign n1916_1 = ~n4555; + assign n4557 = n6638_1 & ~n9361 & (Ng1008 | n7385); + assign n4558 = ~n6638_1 | n8083; + assign n1930_1 = Pg35 & (n4557 | (Ng969 & n4558)); + assign n4560 = n6231 & (n6228 | n6230_1 | n6232); + assign n1935_1 = ~n4560; + assign n4562 = n6527 & n6528 & (n6529 | ~Ng4054); + assign n1940_1 = ~n4562; + assign n4564 = n7922 & (Pg35 | ~Ng6187); + assign n1945_1 = ~n4564; + assign n1950_1 = Ng5073 & (~Pg35 | Ng5069); + assign n4567 = (n6687 | n6688) & (Pg35 | ~Ng5517); + assign n1955 = ~n4567; + assign n4569 = n6910 & n6911 & (n4205 | n6912); + assign n1964 = ~n4569; + assign n4571 = n6469 & (n6470 | ~Ng1682); + assign n1974_1 = ~n4571; + assign n4573 = n7887 & ~n9473 & (Ng1105 | ~n8488); + assign n1988 = ~n4573; + assign n4575 = n6954 & n6955 & (n4205 | n6956); + assign n1998_1 = ~n4575; + assign n4577 = n7355 & ~n9261 & (Pg35 | ~Ng2250); + assign n2012_1 = ~n4577; + assign n4579 = n6234 & (n6228 | n6233 | n6235_1); + assign n2017_1 = ~n4579; + assign n4581 = n7736 & n7737 & (Ng911 | ~n8341); + assign n2022_1 = ~n4581; + assign n4583 = n6457_1 & n6458 & (~n5998_1 | n6459); + assign n2035 = ~n4583; + assign n4585 = n7058 & n7059 & (n4205 | n7060); + assign n2040 = ~n4585; + assign n4587 = n7267 & n7268 & (n4205 | n7269); + assign n2045 = ~n4587; + assign n4589 = n7928 & (Pg35 | ~Ng5495); + assign n2050 = ~n4589; + assign n4591 = n6167 & (Pg35 | ~Ng2950); + assign n2055_1 = ~n4591; + assign n4593 = n7216 & n7217 & (n4205 | n7218); + assign n2060 = ~n4593; + assign n4595 = n6949 & n6950 & (n4205 | n6663); + assign n2070 = ~n4595; + assign n4597 = n6825 & n6826 & (Pg35 | ~Ng1367); + assign n2078_1 = ~n4597; + assign n4599 = n6493 & n6494 & (Pg35 | ~Ng153); + assign n2087 = ~n4599; + assign n4601 = n6245_1 & (n6241 | n6244 | n6235_1); + assign n2092 = ~n4601; + assign n4603 = n7258 & n7259 & (n4205 | n7260); + assign n2101_1 = ~n4603; + assign n4605 = n6592 & (Pg35 | ~Ng2108); + assign n2106_1 = ~n4605; + assign n4607_1 = n8029 & (Pg35 | ~Ng437); + assign n2116 = ~n4607_1; + assign n4609 = n6835 & n6836 & (Ng758 | n6837); + assign n2131_1 = ~n4609; + assign n4611 = n7919 & (Pg35 | ~Ng6533); + assign n2141_1 = ~n4611; + assign n4613 = n7105 & n7106 & (n4205 | n7107); + assign n2146 = ~n4613; + assign n4615 = n7007 & ~n9456 & (n4205 | n7008); + assign n2154 = ~n4615; + assign n4617_1 = n6951 & n6952 & (n4205 | n6953); + assign n2159_1 = ~n4617_1; + assign n4619 = n6100 & n6101 & (Ng632 | n6102); + assign n2164_1 = ~n4619; + assign n4621 = n7222 & n7223 & (n4205 | n7224); + assign n2173_1 = ~n4621; + assign n4623 = n6817 & n6818 & (~Ng1664 | n6816); + assign n2183_1 = ~n4623; + assign n4625 = n8014 & (Pg35 | ~\[4421] ); + assign n2188_1 = ~n4625; + assign n4627_1 = n6915 & n6916 & (n4205 | n6917); + assign n2193 = ~n4627_1; + assign n4629 = n7896 & (Pg35 | ~Ng269); + assign n2198 = ~n4629; + assign n4631_1 = ~Ng4040 | n8507; + assign n2203_1 = Ng4045 & (~Pg35 | n4631_1); + assign n4633 = n7847 & (~Ng4438 | (Pg35 & ~Ng4382)); + assign n2208_1 = ~n4633; + assign n4635 = ~n6680 & (Pg35 | ~\[4437] ); + assign n2217_1 = ~n4635; + assign n4637 = Ng4681 | Ng4688 | Ng4674 | Ng4646; + assign n6680 = Pg35 & ~n9300 & (n4637 | ~n8761); + assign n4639 = n6521 & n6862 & (~Pg35 | n6863); + assign n2222 = ~n4639; + assign n4641 = ~n5990_1 & n6710 & (~n6860 | ~Ng4495); + assign n2227 = ~n4641; + assign n4643 = (n6220 | n6223) & (Pg35 | ~Ng4332); + assign n2252 = ~n4643; + assign n4645 = n6298 & n6299 & (Pg35 | ~Ng298); + assign n2257 = ~n4645; + assign n4647 = n7468 & ~n9285 & (~Ng5831 | n7469); + assign n2265 = ~n4647; + assign n4649 = n7898 & (Pg35 | ~Ng262); + assign n2270_1 = ~n4649; + assign n4651 = n6830 & n6831 & (Pg35 | ~Ng1024); + assign n2293_1 = ~n4651; + assign n4653 = n7307 & n7308 & (n4205 | n7309); + assign n2301_1 = ~n4653; + assign n4655 = n6394 & (n6395_1 | ~Ng2241); + assign n2318_1 = ~n4655; + assign n4657 = n8003 & n8004 & (Ng1564 | ~n8495); + assign n2323_1 = ~n4657; + assign n4659 = n6901 & n6902 & (n4205 | n6903); + assign n2336_1 = ~n4659; + assign n4661 = n7902 & (Pg35 | ~Ng872); + assign n2349_1 = ~n4661; + assign n4663 = ~n5991 & n6710 & (~n6860 | ~Ng4501); + assign n2359_1 = ~n4663; + assign n4665 = (~Ng5869 | n6676) & (~Ng5873 | n6677); + assign n2364_1 = ~n4665; + assign n4667 = n6857 & (n6855 | ~Ng5037 | ~n8723); + assign n2369_1 = ~n4667; + assign n4669 = n6773 & n6769 & n6774; + assign n2374_1 = ~n4669; + assign n4671 = n7153 & n7154 & (n4205 | n7155); + assign n2388_1 = ~n4671; + assign n4673 = n7087 & n7088 & (n4205 | n7089); + assign n2393_1 = ~n4673; + assign n4675 = (n6677 | n6678) & (Pg35 | ~Ng5863); + assign n2398_1 = ~n4675; + assign n4677 = n8005 & (Pg35 | ~Ng1585); + assign n2403_1 = ~n4677; + assign n4679 = n6973 & n6974 & (n4205 | n6975); + assign n2413 = ~n4679; + assign n4681 = n7038 & n7039 & (n4205 | n7040); + assign n2418 = ~n4681; + assign n4683 = n7923 & n7924 & (~n8386 | ~Ng6167); + assign n2428_1 = ~n4683; + assign n4685 = n6551_1 & n6552 & (n6340_1 | ~Ng2599); + assign n2436_1 = ~n4685; + assign n4687_1 = n7876 & ~n9472 & (Ng1448 | ~n8483); + assign n2441_1 = ~n4687_1; + assign n4689 = n7683 & n7684 & (~Ng2299 | ~n8421); + assign n2449_1 = ~n4689; + assign n2454_1 = ~n6697 & ~Ng5164; + assign n4692 = n6652 & n6653 & (Pg35 | ~Ng150); + assign n2463_1 = ~n4692; + assign n2468_1 = ~n6658 & ~Ng6549; + assign n4695 = (n7565 | n7566) & (Pg35 | ~Ng4076); + assign n2473_1 = ~n4695; + assign n4697 = n6329 & n6330_1 & (Pg35 | ~Ng4793); + assign n2478_1 = ~n4697; + assign n4699 = n7180 & n7181 & (n4205 | n7182); + assign n2488_1 = ~n4699; + assign n4701 = n6918 & n6919 & (n4205 | n6920); + assign n2506 = ~n4701; + assign n4703 = n7390 & n7391 & (Pg35 | ~Ng1002); + assign n2516 = ~n4703; + assign n4705 = Pg35 & ((~n5425 & ~n5965) | ~n8510); + assign n2521_1 = n4705 & ~Pg17320 & ~Pg17423 & ~Pg17404; + assign n4707 = n7346 & ~n9256 & (Pg35 | ~Ng2441); + assign n2535_1 = ~n4707; + assign n4709 = n6333 & n6743 & (~Pg35 | n6744); + assign n2540 = ~n4709; + assign n4711 = (Pg35 | ~Ng6049) & (n6509 | ~n9423); + assign n2545_1 = ~n4711; + assign n4713 = n7732 & n7733 & (Ng1256 | ~n8335); + assign n2550_1 = ~n4713; + assign n4715 = n6852 & n6853 & (n6851 | ~Ng5016); + assign n2555_1 = ~n4715; + assign n4717 = n6451 & (n6452_1 | ~Ng1816); + assign n2565_1 = ~n4717; + assign n4719 = ~n1654 & (Pg35 | ~Ng4572); + assign n2575 = ~n4719; + assign n2580_1 = Pg35 & (~Ng4462 | ~n6290 | ~Ng10384); + assign n4722 = n7570 & ~n9301 & (~Ng3831 | n7571); + assign n2585_1 = ~n4722; + assign n4724 = (Pg35 | ~Ng3352) & (n6538 | ~n9425); + assign n2595_1 = ~n4724; + assign n4726 = n6570_1 & (Pg35 | ~Ng2399); + assign n2600_1 = ~n4726; + assign n4728 = n6182 & (Pg35 | ~Ng2138); + assign n2605_1 = ~n4728; + assign n4730 = n7374 & (Pg35 | ~Ng1696); + assign n2610_1 = ~n4730; + assign n4732 = (n7983 | ~Ng513) & (n7987 | ~Ng504); + assign n2615_1 = ~n4732; + assign n4734 = (Pg35 | ~Ng5357) & (n6517_1 | ~n9422); + assign n2624_1 = ~n4734; + assign n4736 = n6333 & n6334 & (Ng2763 | n6335_1); + assign n2629_1 = ~n4736; + assign n4738 = (n6322 | n6323) & (Pg35 | ~Ng4818); + assign n2634_1 = ~n4738; + assign n4740 = n6144 & n6145; + assign n2639_1 = ~n4740; + assign n4742 = n6868 & n6869 & (Ng1263 | ~n8336); + assign n2644_1 = ~n4742; + assign n4744 = n6432_1 & (n6433 | ~Ng1950); + assign n2649_1 = ~n4744; + assign n4746_1 = n7529 & ~n9293 & (~Ng5138 | n7530); + assign n2654 = ~n4746_1; + assign n4748 = n6382 & n6383 & (~n6012_1 | n6384); + assign n2659_1 = ~n4748; + assign n4750 = (n6197 | n6198) & (Pg35 | ~Ng4659); + assign n2672_1 = ~n4750; + assign n4752 = n6777 & n6778 & (~Ng2223 | n6776); + assign n2677_1 = ~n4752; + assign n4754 = n7494 & (Ng5808 | n7495) & ~n9288; + assign n2682_1 = ~n4754; + assign n4756_1 = n6904 & n6905 & (n4205 | n6906); + assign n2687_1 = ~n4756_1; + assign n4758 = n6420 & n6421 & (~n6004 | n6422_1); + assign n2692_1 = ~n4758; + assign n4760 = (~Ng3869 | n6717) & (~Ng3873 | n6718); + assign n2697 = ~n4760; + assign n4762 = n6378 & ~n9444 & (~n6012_1 | n6379); + assign n2705_1 = ~n4762; + assign n4764 = n7864 & (Pg35 | ~Ng2799); + assign n2710_1 = ~n4764; + assign n4766_1 = n7009 & n7010 & (n4205 | n7011); + assign n2715_1 = ~n4766_1; + assign n4768 = n6589 & ~n9432 & (~Ng2047 | n6588); + assign n2720_1 = ~n4768; + assign n4770 = (n6718 | n6719) & (Pg35 | ~Ng3863); + assign n2725_1 = ~n4770; + assign n4772 = n7090 & n7091 & (n4205 | n7092); + assign n2733_1 = ~n4772; + assign n4774 = n7210 & n7211 & (n4205 | n7212); + assign n2748_1 = ~n4774; + assign n4776 = (~Pg35 | ~Ng4411) & (n7854 | ~Ng4401); + assign n2760_1 = ~n4776; + assign n4778 = n6976 & ~n9454 & (n4205 | n6977); + assign n2765_1 = ~n4778; + assign n4780 = n6945 & (Pg35 | ~Ng6307); + assign n2770 = ~n4780; + assign n4782_1 = n7970 & n7971 & (Pg35 | ~Ng1036); + assign n2778_1 = ~n4782_1; + assign n4784 = n7341 & ~n9253 & (Pg35 | ~Ng2575); + assign n2783_1 = ~n4784; + assign n4786 = n6559 & (Pg35 | ~Ng2533); + assign n2788_1 = ~n4786; + assign n4788 = (~Pg35 | ~Ng4443) & (n7845 | ~Ng4434); + assign n2798_1 = ~n4788; + assign n4790 = n7464 & n7760 & (Pg35 | ~Ng6311); + assign n2808_1 = ~n4790; + assign n4792 = n6993 & n6994 & (n4205 | n6995); + assign n2813_1 = ~n4792; + assign n4794 = n7900 & (Pg35 | ~Ng255); + assign n2818_1 = ~n4794; + assign n4796 = n7117 & n7118 & (n4205 | n7119); + assign n2823_1 = ~n4796; + assign n4798 = ~Pg35 | ~Ng6545; + assign n2828 = ~n4798; + assign n4800 = n7347 & ~n9257 & (~Ng2417 | n7348); + assign n2833_1 = ~n4800; + assign n4802_1 = n6617 & n6618 & (n6452_1 | ~Ng1772); + assign n2838_1 = ~n4802_1; + assign n4804 = n6849 & ~n9233 & (Pg35 | ~Ng5046); + assign n2843_1 = ~n4804; + assign n4806 = n6434 & n6435 & (~n6006 | n6436); + assign n2852_1 = ~n4806; + assign n4808 = (n6340_1 | ~Ng2629) & (n6550 | ~Ng2599); + assign n2857_1 = ~n4808; + assign n4810 = n7829 & n7830 & (Ng572 | n7831); + assign n2862_1 = ~n4810; + assign n4812_1 = ~Pg35 | ~Ng2130; + assign n2867_1 = ~n4812_1; + assign n4814 = n6521 & n6711 & (Ng4108 | n6712); + assign n2872_1 = ~n4814; + assign n4816 = n8028 & (Pg35 | ~Ng424); + assign n2881_1 = ~n4816; + assign n4818 = ~n3847_1 & (Pg35 | ~Ng753); + assign n2895_1 = ~n4818; + assign n4820 = (Pg35 | ~Ng4054) & (n6526_1 | ~n9419); + assign n2899_1 = ~n4820; + assign n4822_1 = (Pg35 | ~Ng5873) & (n6674 | n6675_1); + assign n2904_1 = ~n4822_1; + assign n4824 = n7362 & ~n9266 & (~Ng1992 | n7363); + assign n2909_1 = ~n4824; + assign n4826 = (~Ng3167 | n6737) & (~Ng3171 | n6738); + assign n2914_1 = ~n4826; + assign n4828 = (Pg35 | ~Ng843) & (~Ng837 | ~n8838); + assign n2919_1 = ~n4828; + assign n4830 = (~n7739 | ~n9149) & (n7977 | ~Ng817); + assign n2924_1 = ~n4830; + assign n4832 = n7004 & n7005 & (n4205 | n7006); + assign n2929_1 = ~n4832; + assign n4834 = n7916 & (n7915 | (n7917 & ~Ng26885)); + assign n2951_1 = ~n4834; + assign n4836 = n7863 & (Pg35 | ~Ng2811); + assign n2961_1 = ~n4836; + assign n4838 = n7626 & n7809 & (Pg35 | ~Ng3614); + assign n2966_1 = ~n4838; + assign n4840 = (Pg35 | ~Ng3703) & (n6532 | ~n9424); + assign n2971_1 = ~n4840; + assign n4842 = n7897 & (Pg35 | ~Ng239); + assign n2989_1 = ~n4842; + assign n4844 = n7596 & (Ng3808 | n7597) & ~n9304; + assign n3013_1 = ~n4844; + assign n4846 = Ng10384 & Ng4473; + assign n3018_1 = Ng4462 | ~n6290 | ~Pg35 | n4846; + assign n4848 = n7183 & n7184 & (n4205 | n7185); + assign n3023_1 = ~n4848; + assign n4850 = n7169 & n7170 & (Pg35 | ~Ng4087); + assign n3028_1 = ~n4850; + assign n4852 = n6813 & n6809 & n6814; + assign n3033_1 = ~n4852; + assign n4854 = (~Pg17760 & (~Pg14779 | Pg12422)) | (Pg14779 & Pg12422); + assign n3038_1 = n4854 & ~Pg13085 & ~Pg17649 & Pg35 & ~Pg17685; + assign n4856 = n6301 & n6302_1 & (Pg35 | ~Ng157); + assign n3042_1 = ~n4856; + assign n4858 = n7598 & (n4205 | (Ng3498 & n7599)); + assign n3052 = ~n4858; + assign n4860 = n7752 & n7753 & (Ng586 | n7754); + assign n3057 = ~n4860; + assign n4862 = n6749 & n6750 & (n6745 | ~Ng2619); + assign n3065_1 = ~n4862; + assign n4864 = n7388 & (Ng1183 | n7389); + assign n3070 = ~n4864; + assign n4866 = n6480 & n6481 & (~n6010 | n6482_1); + assign n3075 = ~n4866; + assign n4868 = n6611 & ~n9434 & (~Ng1779 | n6610_1); + assign n3086_1 = ~n4868; + assign n4870 = ~n7660 & (~Pg35 | n7658 | ~Ng2652); + assign n3091 = ~n4870; + assign n4872 = n7356 & ~n9262 & (Pg35 | ~Ng2173); + assign n3096_1 = ~n4872; + assign n4874 = n7349 & (Pg35 | ~Ng2389); + assign n3101_1 = ~n4874; + assign n4876 = n7772 & (~Pg35 | n7771 | n7773); + assign n3111 = ~n4876; + assign n4878 = (Pg35 | ~Ng5527) & (n6684 | n6685); + assign n3116_1 = ~n4878; + assign n4880 = n7333 & (Pg35 | ~Ng2803); + assign n3121 = ~n4880; + assign n4882_1 = n7380 & n7381 & (Pg35 | ~Ng1345); + assign n3126 = ~n4882_1; + assign n4884 = n6996 & n6997 & (n4205 | n6998); + assign n3131_1 = ~n4884; + assign n4886 = Ng1146 & (~n4887 | ~Ng1152); + assign n4887 = ~Ng1183 & Pg13259 & ~Ng1171; + assign n3136 = Pg35 & (n4886 | (n4887 & ~Ng1099)); + assign n4889 = n6747 & n6748 & (~Ng2625 | n6746); + assign n3141_1 = ~n4889; + assign n4891 = n6842 & n6843 & (Pg35 | ~Ng164); + assign n3146 = ~n4891; + assign n4893 = n7375 & ~n9273 & (Pg35 | ~Ng1691); + assign n3151_1 = ~n4893; + assign n4895 = (n6656_1 | n6662) & (Pg35 | ~Ng6549); + assign n3156_1 = ~n4895; + assign n3161 = \[4431] & Pg35; + assign n4898 = (Pg35 | ~Ng3873) & (n6715 | n6716); + assign n3165 = ~n4898; + assign n4900 = n6921 & n6922 & (n4205 | n6923); + assign n3170_1 = ~n4900; + assign n4902 = n7952 & n7953 & (~n8405 | ~Ng3470); + assign n3175_1 = ~n4902; + assign n4904_1 = n7177 & n7178 & (n4205 | n7179); + assign n3180_1 = ~n4904_1; + assign n4906 = (n7983 | ~Ng518) & (n7987 | ~Ng513); + assign n3185_1 = ~n4906; + assign n4908 = Ng538 | Ng209; + assign n4909 = n6068 & n6065 & n6066 & n6067; + assign n3190 = n4908 & Pg35; + assign n4911 = n6545 & ~n9428 & (~Ng2606 | n6544); + assign n3195 = ~n4911; + assign n4913 = n7874 & n7875 & (Ng1472 | ~n8482); + assign n3200 = ~n4913; + assign n4915 = (n7743 | n8026) & (Pg35 | ~Ng546); + assign n3205 = ~n4915; + assign n4917 = (Pg35 | ~Ng5180) & (n6694 | n6695); + assign n3210_1 = ~n4917; + assign n4919 = n7150 & n7151 & (n4205 | n7152); + assign n3228 = ~n4919; + assign n4921 = n6195 & (n6196_1 | ~Ng4664 | ~n8230); + assign n3237 = ~n4921; + assign n4923 = n8014 & (Pg35 | ~Ng1236); + assign n3242_1 = ~n4923; + assign n4925 = (Pg35 | ~\[4507] ) & (n7994 | n7995); + assign n3247_1 = ~n4925; + assign n4927 = n6177 & (Pg35 | ~Ng2852); + assign n3252 = ~n4927; + assign n4929 = n6285 & n6286 & (n6287 | n6284_1); + assign n3257_1 = ~n4929; + assign n4931 = n6936 & n6937 & (n4205 | n6938); + assign n3262_1 = ~n4931; + assign n4933 = (Pg35 | ~Ng1542) & (n5559 | ~n8744); + assign n3275_1 = ~n4933; + assign n4935 = n6907 & n6908 & (n4205 | n6909); + assign n3286_1 = ~n4935; + assign n4937 = (n6433 | ~Ng1936) & (n6605_1 | ~Ng1906); + assign n3291_1 = ~n4937; + assign n4939_1 = n7988 & (n7986 | n7755); + assign n3301 = ~n4939_1; + assign n4941 = n6753 & n6749 & n6754; + assign n3306_1 = ~n4941; + assign n4943 = n6710 & n6861 & (Pg35 | ~Ng4477); + assign n3311 = ~n4943; + assign n4945 = n6380_1 & n6381 & (~n6012_1 | ~n8279); + assign n3316_1 = ~n4945; + assign n4947 = n7240 & ~n9466 & (n4205 | n7241); + assign n3321 = ~n4947; + assign n4949 = n7093 & n7094 & (n4205 | n7095); + assign n3326_1 = ~n4949; + assign n4951 = n7256 & ~n9468 & (n4205 | n7257); + assign n3331_1 = ~n4951; + assign n4953 = n7253 & n7254 & (n4205 | n7255); + assign n3345 = ~n4953; + assign n4955 = n6978 & n6979 & (n4205 | n6980); + assign n3350_1 = ~n4955; + assign n3355_1 = Ng4681 & n4365; + assign n4958 = n7159 & n7160 & (n4205 | n7161); + assign n3365_1 = ~n4958; + assign n4960 = n7310 & ~n9471 & (n4205 | n7311); + assign n3370_1 = ~n4960; + assign n4962 = n6418 & n6419 & (~n6004 | ~n8295); + assign n3375 = ~n4962; + assign n4964 = n7403 & (n4205 | (Ng6541 & n7404)); + assign n3386_1 = ~n4964; + assign n4966 = n7283 & n7284 & (n4205 | n6733); + assign n3391_1 = ~n4966; + assign n4968 = n6626 & (Pg35 | ~Ng1636); + assign n3396_1 = ~n4968; + assign n4970 = n7788 & (~Pg35 | n7787 | n7789); + assign n3401_1 = ~n4970; + assign n4972 = n7899 & (Pg35 | ~Ng232); + assign n3406_1 = ~n4972; + assign n4974 = n7989 & (Pg35 | ~Ng168); + assign n3421_1 = ~n4974; + assign n4976 = (n6666 | n6672) & (Pg35 | ~Ng6203); + assign n3426_1 = ~n4976; + assign n4978_1 = (n7910 | n7911) & (Pg35 | ~Ng355); + assign n3431_1 = ~n4978_1; + assign n4980 = ~Pg35 | ~Ng3502; + assign n3444_1 = ~n4980; + assign n4982 = n6578 & ~n9431 & (~Ng2204 | n6577); + assign n3449 = ~n4982; + assign n4984 = n7125 & n7126 & (n4205 | n7127); + assign n3454 = ~n4984; + assign n4986 = n6217 & n6218 & (Pg35 | ~Ng4601); + assign n3459_1 = ~n4986; + assign n4988 = n6112 & n6113 & (Ng794 | n6114); + assign n3464_1 = ~n4988; + assign n4990 = n8025 & (~Ng703 | n8024); + assign n3485_1 = ~n4990; + assign n4992_1 = n7297 & n7298 & (n4205 | n7299); + assign n3495_1 = ~n4992_1; + assign n4994 = n6595_1 & n6596 & (n6414 | ~Ng2040); + assign n3500_1 = ~n4994; + assign n4996 = n6164 & (Pg35 | ~Ng4176); + assign n3505 = ~n4996; + assign n4998 = (~Ng4633 | n6207) & (~Ng4628 | n6209); + assign n3510_1 = ~n4998; + assign n5000 = n6159 & (Pg35 | ~Ng4727); + assign n3519_1 = ~n5000; + assign n5002_1 = n7470 & ~n9286 & (~n6884 | ~n8444); + assign n3528_1 = ~n5002_1; + assign n5004 = n6769 & n6770 & (n6765 | ~Ng2351); + assign n3533 = ~n5004; + assign n5006 = ~Ng6727 | ~n8502; + assign n3543 = Ng6732 & (~Pg35 | n5006); + assign n5008 = (n6521 | n7943) & (Pg35 | ~Ng4125); + assign n3553 = ~n5008; + assign n5010 = n7603 & ~n9306 & (~n8105 | ~n8453); + assign n3566_1 = ~n5010; + assign n5012 = n7804 & n7805 & (n7801 | ~n8473); + assign n3571_1 = ~n5012; + assign n5014 = n6856 & (n6855 | ~Ng5041 | ~n8379); + assign n3576 = ~n5014; + assign n5016_1 = ~Ng4452 & (n7844 | n7846 | ~Ng4430); + assign n3581_1 = ~n5016_1; + assign n5018 = n7432 & (Ng6500 | n7433) & ~n9280; + assign n3591_1 = ~n5018; + assign n5020 = n7629 & (Pg35 | ~Ng3129); + assign n3599 = ~n5020; + assign n5022 = n7810 & (Pg35 | ~Ng3263); + assign n3604 = ~n5022; + assign n3613_1 = Ng4674 & n4365; + assign n5025 = n6491 & n6492_1 & (Pg35 | ~Ng294); + assign n3618_1 = ~n5025; + assign n5027 = n6803 & n6799 & n6804; + assign n3631 = ~n5027; + assign n5029 = n6165_1 & (Pg35 | ~Ng2994); + assign n3636_1 = ~n5029; + assign n5031 = n7276 & n7277 & (n4205 | n7278); + assign n3641 = ~n5031; + assign n3646_1 = Ng160 & (~Pg35 | ~n9218); + assign n5034 = n7823 & n7824 & (Pg35 | ~Ng822); + assign n3656_1 = ~n5034; + assign n5036_1 = ~Ng1008 & ~Ng969 & ~n4558; + assign n3661 = Pg35 & ~n9151 & (n5036_1 | ~n8511); + assign n5038 = n6554 & (n6340_1 | ~Ng2555); + assign n3665_1 = ~n5038; + assign n5040 = n7433 & n7759 & (Pg35 | ~Ng6657); + assign n3670_1 = ~n5040; + assign n5042 = n7406 & ~n9277 & (~Ng6523 | n7407); + assign n3680_1 = ~n5042; + assign n5044 = n7378 & (Ng1526 | n7379); + assign n3685_1 = ~n5044; + assign n5046 = (n6219 | n6220) & (Pg35 | ~Ng4593); + assign n3690_1 = ~n5046; + assign n5048 = ~n5049 | Ng854; + assign n5049 = ~Pg8719 | Ng385 | ~Ng376 | ~Ng370; + assign n5050 = n6250_1 | ~n9329; + assign n3695 = n5048 & Pg35 & (n5049 | n5050); + assign n5052 = n7730 & (n7731 | ~Ng1484); + assign n3700 = ~n5052; + assign n5054 = n6155 & (Pg35 | ~Ng4917); + assign n3705 = ~n5054; + assign n3710_1 = Ng5077 & (~Pg35 | ~n8914); + assign n5057 = (n6675_1 | n6681) & (Pg35 | ~Ng5857); + assign n3715_1 = ~n5057; + assign n5059 = ~n7669 & (~Pg35 | n7667 | ~Ng2518); + assign n3725 = ~n5059; + assign n5061 = n6337 & (Pg35 | ~Ng2648); + assign n3730 = ~n5061; + assign n5063 = n7907 & n7908 & (Ng568 | n7909); + assign n3735 = ~n5063; + assign n5065 = n7279 & (Pg35 | ~Ng3259); + assign n3740 = ~n5065; + assign n5067 = n6927 & n6928 & (n4205 | n6929); + assign n3745 = ~n5067; + assign n5069_1 = ~Ng6035 | ~n8504; + assign n3750_1 = Ng6040 & (~Pg35 | n5069_1); + assign n3765_1 = ~n6677 & ~Ng5857; + assign n5072 = n6474 & n6475 & (~n6010 | n6476); + assign n3770_1 = ~n5072; + assign n5074 = n7226 & n7227 & (n4205 | n7228); + assign n3783_1 = ~n5074; + assign n5076 = n7572 & ~n9302 & (~n6889 | ~n8451); + assign n3797_1 = ~n5076; + assign n5078 = ~n5991 & n6708 & (~n6860 | ~Ng4498); + assign n3807_1 = ~n5078; + assign n5080 = n7870 & n7871 & (Pg35 | ~Ng2719); + assign n3817_1 = ~n5080; + assign n5082 = n7795 & (~Pg35 | n7794 | n7796); + assign n3822_1 = ~n5082; + assign n5084 = n7109 & n7110 & (n4205 | n7111); + assign n3837_1 = ~n5084; + assign n5086 = n6149 & n6150 & (Ng617 | n6151); + assign n3842_1 = ~n5086; + assign n5088 = n7915 & (Pg35 | ~Ng324); + assign n3851_1 = ~n5088; + assign n5090 = Ng1270 & ~n6829; + assign n5091 = ~n5965 | ~Ng1536; + assign n3856 = Ng1274 & (~Pg35 | (n5090 & n5091)); + assign n5093 = n7920 & n7921 & (~n8381 | ~Ng6513); + assign n3861_1 = ~n5093; + assign n5095 = n7913 & n7914 & (n7915 | ~Ng305); + assign n3866_1 = ~n5095; + assign n5097 = Ng925 & ~n6834; + assign n3876_1 = Ng930 & (~Pg35 | (n5097 & ~n6128)); + assign n5099 = n6606 & n6607 & (n6433 | ~Ng1906); + assign n3881_1 = ~n5099; + assign n3886 = Pg6745 & Pg35; + assign n5102 = n7865 & (Pg35 | ~\[4428] ); + assign n3896 = ~n5102; + assign n5104 = n6153 & (Pg35 | ~Ng4907); + assign n3907_1 = ~n5104; + assign n5106 = n6163 & (Pg35 | ~Ng4146); + assign n3912 = ~n5106; + assign n5108 = n6557 & n6558 & (~n8269 | ~Ng2541); + assign n3917 = ~n5108; + assign n5110 = n6587 & (n6395_1 | ~Ng2153); + assign n3922 = ~n5110; + assign n5112 = n7901 & (Pg35 | ~Ng225); + assign n3932 = ~n5112; + assign n5114 = n7710 & n7711 & (~Ng1874 | ~n8431); + assign n3937_1 = ~n5114; + assign n5116_1 = n7135 & n7136 & (n4205 | n7137); + assign n3942_1 = ~n5116_1; + assign n5118 = n7872 & n7873 & (Ng1478 | ~n8481); + assign n3947 = ~n5118; + assign n5120 = (n6716 | n6722) & (Pg35 | ~Ng3857); + assign n3952_1 = ~n5120; + assign n5122 = ~n7705 & (~Pg35 | n7704 | ~Ng1959); + assign n3957_1 = ~n5122; + assign n5124 = n7601 & ~n9305 & (~Ng3480 | n7602); + assign n3962 = ~n5124; + assign n5126_1 = n6899 & ~n9450 & (n4205 | n6900); + assign n3967_1 = ~n5126_1; + assign n5128 = n7779 & (~Pg35 | n6125 | n7778); + assign n3980_1 = ~n5128; + assign n3988 = ~n6718 & ~Ng3857; + assign n5131_1 = Ng499 & (n7986 | ~Ng513); + assign n5132 = ~n7986 & (~Ng518 | ~n8468); + assign n3996_1 = Pg35 & (n5131_1 | n5132); + assign n5134 = n7818 & (~n6638_1 | Ng1002 | n7819); + assign n4001 = ~n5134; + assign n5136 = n6255_1 & n6256 & (Ng776 | n6257); + assign n4006 = ~n5136; + assign n4015 = ~n6198 & ~Ng4674 & ~Ng4646 & ~Ng4681; + assign n5139 = n6819 & n6820 & (n6815 | ~Ng1657); + assign n4025_1 = ~n5139; + assign n5141_1 = n6376_1 & (n6377 | ~Ng2375); + assign n4030 = ~n5141_1; + assign n5143 = (Pg35 | ~Ng278) & (Ng283 | n7834); + assign n4052_1 = ~n5143; + assign n5145 = (n6736 | n6742) & (Pg35 | ~Ng3155); + assign n4057 = ~n5145; + assign n5147 = ~n7678 & (~Pg35 | n7677 | ~Ng2384); + assign n4062 = ~n5147; + assign n5149 = n6213 & (~n6212 | n6214 | ~Ng4608); + assign n4070_1 = ~n5149; + assign n5151 = n6415 & n6416 & (~n6004 | n6417_1); + assign n4080 = ~n5151; + assign n5153 = n7866 & (Pg35 | ~Ng2791); + assign n4089_1 = ~n5153; + assign n5155 = n6187 & n6188 & (Ng613 | n6189); + assign n4094_1 = ~n5155; + assign n5157 = n6614 & (Pg35 | ~Ng1840); + assign n4104 = ~n5157; + assign n5159 = n7023 & n7024 & (n4205 | n7025); + assign n4109 = ~n5159; + assign n5161 = ~n5991 & ~n5993 & (~n6860 | ~Ng4567); + assign n4114_1 = ~n5161; + assign n5163 = n7345 & ~n9255 & (Pg35 | ~Ng2518); + assign n4119 = ~n5163; + assign n5165 = (~Pg16718 & (~Pg13895 | Pg11349)) | (Pg13895 & Pg11349); + assign n4124 = n5165 & ~Pg14421 & ~Pg16603 & Pg35 & ~Pg16624; + assign n5167 = n6339 & (n6340_1 | ~Ng2643); + assign n4128 = ~n5167; + assign n5169 = Ng1489 & (~n5170 | ~Ng1495); + assign n5170 = ~Ng1514 & Pg13272 & ~Ng1526; + assign n4133_1 = Pg35 & (n5169 | (n5170 & ~Ng1442)); + assign n5172 = n7342 & ~n9254 & (~Ng2551 | n7343); + assign n4142_1 = ~n5172; + assign n5174 = n7526 & (n4205 | (Ng5156 & n7527)); + assign n4147 = ~n5174; + assign n5176 = n6510 & n6511 & (n6512_1 | ~Ng6049); + assign n4169_1 = ~n5176; + assign n5178 = n6579 & n6580_1 & (~n8283 | ~Ng2273); + assign n4174 = ~n5178; + assign n5180 = n7783 & (~Pg35 | n7782 | n7784); + assign n4182_1 = ~n5180; + assign n5182 = n7627 & (n4205 | (Ng3147 & n7628)); + assign n4192_1 = ~n5182; + assign n5184 = ~Ng3338 | n8509; + assign n4197 = Ng3343 & (~Pg35 | n5184); + assign n5186 = n6581 & (Pg35 | ~Ng2265); + assign n4202_1 = ~n5186; + assign n5188 = n6115 & n6116 & (Ng626 | n6117); + assign n4216 = ~n5188; + assign n5190 = n6333 & n7811 & (~Pg35 | n7812); + assign n4221_1 = ~n5190; + assign n5192 = n6518 & n6519 & (n6520 | ~Ng5357); + assign n4226_1 = ~n5192; + assign n5194 = n6318 & n6319 & (Pg35 | ~Ng4983); + assign n4231_1 = ~n5194; + assign n5196 = n6325 & (Pg35 | ~Ng4785); + assign n4239_1 = ~n5196; + assign n5198 = n7029 & n7030 & (n4205 | n7031); + assign n4254 = ~n5198; + assign n5200 = n6154 & (Pg35 | ~Ng4922); + assign n4259_1 = ~n5200; + assign n5202 = n7597 & n7808 & (Pg35 | ~Ng3965); + assign n4267_1 = ~n5202; + assign n5204 = n6872 & n6873 & (Ng918 | ~n8342); + assign n4277_1 = ~n5204; + assign n5206 = n6521 & n7860 & (~Pg35 | n7861); + assign n4282 = ~n5206; + assign n5208 = n7361 & ~n9265 & (Pg35 | ~Ng2016); + assign n4291_1 = ~n5208; + assign n5210 = n7398 & n7399 & (Ng577 | n7400); + assign n4296_1 = ~n5210; + assign n5212 = n6471 & n6472_1 & (~n6010 | n6473); + assign n4301_1 = ~n5212; + assign n5214 = n7334 & (Pg35 | ~Ng2771); + assign n4306 = ~n5214; + assign n5216 = n6643 & n6644 & (Ng930 | ~n5097); + assign n4316_1 = ~n5216; + assign n5218 = n7195 & n7196 & (n4205 | n7197); + assign n4321_1 = ~n5218; + assign n5220 = (Pg35 | ~Ng812) & (~n7739 | ~n8961); + assign n4326_1 = ~n5220; + assign n5222 = ~n8023 & (~Ng837 | (n7758 & ~n8021)); + assign n4336_1 = ~n5222; + assign n5224 = n6489 & (Ng599 | n6490) & ~n9446; + assign n4344_1 = ~n5224; + assign n5226 = n7929 & n7930 & (~n8394 | ~Ng5475); + assign n4349_1 = ~n5226; + assign n5228 = (n7742 | n7743) & (Pg35 | ~Ng736); + assign n4354_1 = ~n5228; + assign n5230 = n7015 & n7016 & (n4205 | n7017); + assign n4359_1 = ~n5230; + assign n5232 = (Pg35 | ~Ng6741) & (n6497_1 | ~n9420); + assign n4364_1 = ~n5232; + assign n5234 = n6174 & (Pg35 | ~Ng2868); + assign n4374_1 = ~n5234; + assign n5236 = n7940 & ~n9350 & (n7941 | ~Ng5080); + assign n4384_1 = ~n5236; + assign n5238 = n7070 & n7071 & (n4205 | n7072); + assign n4389_1 = ~n5238; + assign n5240 = (n6359_1 | ~Ng2495) & (n6561 | ~Ng2465); + assign n4397_1 = ~n5240; + assign n5242 = n6367 & n6368 & (~n6002 | n6369_1); + assign n4402_1 = ~n5242; + assign n5244 = n7359 & (Pg35 | ~Ng2098); + assign n4407_1 = ~n5244; + assign n5246 = n6344 & n6345 & (~n6000 | ~n8265); + assign n4417_1 = ~n5246; + assign n5248 = n6314 & (Pg35 | ~Ng4975); + assign n4427_1 = ~n5248; + assign n5250 = n6331 & n6332 & (n6323 | ~Ng4785); + assign n4437 = ~n5250; + assign n5252 = n7084 & n7085 & (n4205 | n7086); + assign n4442_1 = ~n5252; + assign n5254 = n6184 & n6185 & (Ng781 | n6186); + assign n4447 = ~n5254; + assign n5256 = n7981 & n7982 & (n7983 | ~Ng686); + assign n4465_1 = ~n5256; + assign n5258 = n7815 & n7816 & (Ng1252 | n7817); + assign n4470 = ~n5258; + assign n5260 = (n7750 | n7751) & (Pg35 | ~Ng667); + assign n4475 = ~n5260; + assign n5262 = n6971 & ~n9453 & (n4205 | n6972); + assign n4485 = ~n5262; + assign n5264 = (~Ng5523 | n6686) & (~Ng5527 | n6687); + assign n4499 = ~n5264; + assign n5266 = n6827 & n6828 & (Ng1270 | n6829); + assign n4514 = ~n5266; + assign n5268 = n6315_1 & (n6316 | n6317 | ~Ng4991); + assign n4519 = ~n5268; + assign n5270 = (Pg35 | ~Ng6219) & (n6665_1 | n6666); + assign n4524 = ~n5270; + assign n5272 = n7201 & n7202 & (n4205 | n7203); + assign n4529 = ~n5272; + assign n5274 = n7496 & (n4205 | (Ng5503 & n7497)); + assign n4534 = ~n5274; + assign n5276 = n7032 & n7033 & (n4205 | n7034); + assign n4544_1 = ~n5276; + assign n5278 = n7147 & n7148 & (n4205 | n7149); + assign n4559_1 = ~n5278; + assign n5280 = n6423 & n6424 & (~n6004 | n6425); + assign n4564_1 = ~n5280; + assign n4569_1 = ~n6668 & ~Ng6203; + assign n5283 = n7350 & ~n9258 & (Pg35 | ~Ng2384); + assign n4582_1 = ~n5283; + assign n5285 = n6370 & n6371 & (~n6002 | n6372); + assign n4592 = ~n5285; + assign n5287 = n6240_1 & (n6241 | n6239 | n6229); + assign n4597_1 = ~n5287; + assign n5289 = n6138 & n6139; + assign n4602 = ~n5289; + assign n5291 = n6546_1 & n6547 & (~n8262 | ~Ng2675); + assign n4607 = ~n5291; + assign n5293 = n7996 & (Pg35 | ~Ng4358); + assign n4612 = ~n5293; + assign n4617 = ~n6193 & ~Ng4864 & ~Ng4871 & ~Ng4836; + assign n5296 = n7102 & n7103 & (n4205 | n7104); + assign n4631 = ~n5296; + assign n5298_1 = n6183_1 & (Pg35 | ~Ng2130); + assign n4636 = ~n5298_1; + assign n5300 = n6567 & ~n9430 & (~Ng2338 | n6566); + assign n4644 = ~n5300; + assign n5302 = n6990 & n6991 & (n4205 | n6992); + assign n4652_1 = ~n5302; + assign n5304 = n7867 & (Pg35 | ~Ng2779); + assign n4657_1 = ~n5304; + assign n5306 = n7188 & n7189 & (n4205 | n7190); + assign n4662 = ~n5306; + assign n5308 = n7018 & n7019 & (n4205 | n7020); + assign n4672_1 = ~n5308; + assign n5310 = n7132 & n7133 & (n4205 | n7134); + assign n4677_1 = ~n5310; + assign n5312 = n6333 & n6541_1 & (Ng2759 | n6542); + assign n4682 = ~n5312; + assign n5314 = n6498 & n6499 & (n6500 | ~Ng6741); + assign n4687 = ~n5314; + assign n5316 = n6146 & n6147_1 & (Ng785 | n6148); + assign n4692_1 = ~n5316; + assign n5318_1 = n7382 & n7383 & (Ng1259 | n7384); + assign n4697_1 = ~n5318_1; + assign n5320 = n7600 & (Pg35 | ~Ng3480); + assign n4702_1 = ~n5320; + assign n5322_1 = n6930 & n6931 & (n4205 | n6932); + assign n4712_1 = ~n5322_1; + assign n5324 = (n6685 | n6691) & (Pg35 | ~Ng5511); + assign n4717_1 = ~n5324; + assign n5326 = n6360 & ~n9443 & (~n6002 | n6361); + assign n4722_1 = ~n5326; + assign n5328 = n6346 & n6347 & (~n6000 | n6348); + assign n4727_1 = ~n5328; + assign n5330 = n7892 & n7893 & (Pg35 | ~Ng921); + assign n4741_1 = ~n5330; + assign n5332 = n7360 & ~n9264 & (Pg35 | ~Ng2093); + assign n4746 = ~n5332; + assign n5334 = (~Pg35 | n6290) & (~Ng4473 | n6292); + assign n4751_1 = ~n5334; + assign n5336 = n6296 & (Ng604 | n6297_1) & ~n9442; + assign n4756 = ~n5336; + assign n5338 = n6896 & n6897 & (n4205 | n6898); + assign n4761_1 = ~n5338; + assign n5340 = n6437_1 & n6438 & (~n6006 | ~n8302); + assign n4766 = ~n5340; + assign n5342 = n6445 & n6446 & (~n6006 | n6447_1); + assign n4782 = ~n5342; + assign n5344 = n6161 & (Pg35 | ~Ng4253); + assign n4787_1 = ~n5344; + assign n5346 = ~n7714 & (~Pg35 | n7712 | ~Ng1825); + assign n4792_1 = ~n5346; + assign n5348 = ~n7973 & (~Ng969 | (Pg35 & n4558)); + assign n4797 = ~n5348; + assign n5350 = n7843 & (Pg35 | ~Ng4417); + assign n4802 = ~n5350; + assign n5352 = n7231 & n7232 & (n4205 | n7233); + assign n4807_1 = ~n5352; + assign n5354 = n7138 & n7139 & (n4205 | n7140); + assign n4812 = ~n5354; + assign n5356 = n7371 & ~n9271 & (Pg35 | ~Ng1748); + assign n4817 = ~n5356; + assign n5358 = (n6192_1 | n6193) & (Pg35 | ~Ng4849); + assign n4822 = ~n5358; + assign n5360 = n7204 & n7205 & (n4205 | n7206); + assign n4827 = ~n5360; + assign n5362 = n7408 & ~n9278 & (~n8213 | ~n8440); + assign n4832_1 = ~n5362; + assign n4837_1 = Pg35 & ~n8535; + assign n5365 = n7674 & n7675 & (~Ng2433 | ~n8418); + assign n4842_1 = ~n5365; + assign n5367 = n6783 & n6779 & n6784; + assign n4859_1 = ~n5367; + assign n4864_1 = ~n6175; + assign n5370 = (n6414 | ~Ng2070) & (n6594 | ~Ng2040); + assign n4873_1 = ~n5370; + assign n5372 = (~Pg16775 & (~Pg13966 | Pg11418)) | (Pg13966 & Pg11418); + assign n4887_1 = n5372 & ~Pg14518 & ~Pg16659 & Pg35 & ~Pg16693; + assign n5374 = n7436 & (Pg35 | ~Ng6177); + assign n4899 = ~n5374; + assign n5376 = n7096 & n7097 & (n4205 | n7098); + assign n4914_1 = ~n5376; + assign n5378 = Ng1395 ^ n7877; + assign n4919_1 = Pg35 & n5378 & ~Ng1322; + assign n5380 = n6600_1 & ~n9433 & (~Ng1913 | n6599); + assign n4924_1 = ~n5380; + assign n5382 = n6573 & n6574 & (n6377 | ~Ng2331); + assign n4929_1 = ~n5382; + assign n5384 = n6984 & n6985 & (n4205 | n6986); + assign n4934_1 = ~n5384; + assign n5386 = n7191 & ~n9464 & (n4205 | n7192); + assign n4944 = ~n5386; + assign n5388 = (~Ng1266 | n7967) & (n7966 | ~Ng1249); + assign n4958_1 = ~n5388; + assign n5390 = n7498 & (Pg35 | ~Ng5485); + assign n4963_1 = ~n5390; + assign n5392 = n7746 & n7747 & (Pg35 | ~Ng676); + assign n4968_1 = ~n5392; + assign n5394 = n6864 & n6865 & (Pg35 | ~Ng2741); + assign n4973 = ~n5394; + assign n5396 = n7501 & ~n9290 & (~n8100 | ~n8446); + assign n4978 = ~n5396; + assign n5398 = n6706 & n6861 & (Pg35 | ~Ng4423); + assign n4983_1 = ~n5398; + assign n5400 = n6892 & n6893 & (n4205 | n6894); + assign n4992 = ~n5400; + assign n5402 = n6362 & n6363 & (~n6002 | ~n8272); + assign n4997 = ~n5402; + assign n5404 = n6401 & n6402 & (~n6008_1 | n6403_1); + assign n5002 = ~n5404; + assign n5406 = n6757 & n6758 & (~Ng2491 | n6756); + assign n5011_1 = ~n5406; + assign n5408 = n6194 & ~n9439 & (Pg35 | ~Ng4843); + assign n5016 = ~n5408; + assign n5410 = n6404 & n6405 & (~n6008_1 | n6406); + assign n5021 = ~n5410; + assign n5412 = n7352 & ~n9260 & (~Ng2283 | n7353); + assign n5026 = ~n5412; + assign n5414 = n6939 & n6940 & (n4205 | n6941); + assign n5031_1 = ~n5414; + assign n5416_1 = n7334 & (Pg35 | ~Ng2831); + assign n5036 = ~n5416_1; + assign n5418 = n6568 & n6569 & (~n8276 | ~Ng2407); + assign n5041 = ~n5418; + assign n5420 = n6173 & (Pg35 | ~Ng2988); + assign n5046_1 = ~n5420; + assign n5422 = n7869 & (Pg35 | ~Ng2763); + assign n5051_1 = ~n5422; + assign n5424 = n6631 & ~n9356 & (n5964 | Ng1351); + assign n5425 = ~n6631 | n8082; + assign n5064 = Pg35 & (n5424 | (Ng1312 & n5425)); + assign n5427 = n7112 & n7113 & (n4205 | n6692); + assign n5069 = ~n5427; + assign n5429 = n6160_1 & (Pg35 | ~Ng4249); + assign n5074_1 = ~n5429; + assign n5431 = (n7826 | ~Ng446) & (~Ng645 | ~n8475); + assign n5079_1 = ~n5431; + assign n5433 = n7906 & ~n8132 & (Pg35 | ~Ng728); + assign n5088_1 = ~n5433; + assign n5435 = n7990 & (Pg35 | ~Ng405); + assign n5093_1 = ~n5435; + assign n5437 = n7885 & n7886 & (Ng1129 | ~n8487); + assign n5098 = ~n5437; + assign n5439 = (n6395_1 | ~Ng2227) & (n6583 | ~Ng2197); + assign n5103 = ~n5439; + assign n5441 = n7370 & ~n9270 & (Pg35 | ~Ng1825); + assign n5116 = ~n5441; + assign n5443 = n7248 & ~n9467 & (n4205 | n7249); + assign n5121 = ~n5443; + assign n5445 = n8030 & n8031 & (Pg35 | ~Ng401); + assign n5126 = ~n5445; + assign n5447 = n6630 & (n6470 | ~Ng1592); + assign n5131 = ~n5447; + assign n5449 = n8012 & n8013 & (Ng1221 | ~n8497); + assign n5141 = ~n5449; + assign n5451 = n7035 & n7036 & (n4205 | n7037); + assign n5146 = ~n5451; + assign n5453 = (n7401 | n7402) & (Pg35 | ~Ng142); + assign n5156 = ~n5453; + assign n5455 = n6797 & n6798 & (~Ng1932 | n6796); + assign n5165_1 = ~n5455; + assign n5457 = n6823 & n6819 & n6824; + assign n5170_1 = ~n5457; + assign n5459 = n7525 & ~n9292 & (Pg35 | ~Ng5467); + assign n5180_1 = ~n5459; + assign n5461_1 = ~Pg35 | ~Ng2689; + assign n5185_1 = ~n5461_1; + assign n5463 = (Pg35 | ~Ng6565) & (n6655 | n6656_1); + assign n5190_1 = ~n5463; + assign n5465 = n7728 & n7729 & (~Ng1604 | ~n8437); + assign n5195_1 = ~n5465; + assign n5467 = n6793 & n6794 & (Pg35 | ~Ng2036); + assign n5200_1 = ~n5467; + assign n5469 = n6548 & (Pg35 | ~Ng2667); + assign n5205_1 = ~n5469; + assign n5471 = n8009 & n8010 & (~Pg17423 | n8005); + assign n5210_1 = ~n5471; + assign n5473 = n7856 & n7859 & (Pg35 | ~Ng4411); + assign n5214_1 = ~n5473; + assign n5475 = n6612 & n6613 & (~n8305 | ~Ng1848); + assign n5218_1 = ~n5475; + assign n5477 = n7935 & ~n9474 & (\[4434] | n7936); + assign n5223_1 = ~n5477; + assign n5479 = n7499 & ~n9289 & (~Ng5485 | n7500); + assign n5228_1 = ~n5479; + assign n5481 = (n7335 | n7336) & (Pg35 | ~Ng2735); + assign n5233_1 = ~n5481; + assign n5483 = n7665 & n7666 & (~Ng2567 | ~n8414); + assign n5241_1 = ~n5483; + assign n5485 = n7798 & n7799 & (n7800 | n7801); + assign n5246_1 = ~n5485; + assign n5487 = n6224 & n6225 & (Pg35 | ~Ng4311); + assign n5251 = ~n5487; + assign n5489 = n7021 & ~n9457 & (n4205 | n7022); + assign n5256_1 = ~n5489; + assign n5491 = n6622 & ~n9435 & (~Ng1644 | n6621); + assign n5273 = ~n5491; + assign n5493 = n6648 & (Ng595 | n6649) & ~n9447; + assign n5278_1 = ~n5493; + assign n5495 = n6779 & n6780 & (n6775 | ~Ng2217); + assign n5283_1 = ~n5495; + assign n5497 = Ng1404 ^ n8011; + assign n5288_1 = n5497 | ~n9150; + assign n5499 = n6787 & n6788 & (~Ng2066 | n6786); + assign n5293_1 = ~n5499; + assign n5501 = n7128 & ~n9461 & (n4205 | n7129); + assign n5303_1 = ~n5501; + assign n5503 = n6392 & (Pg35 | ~Ng2246); + assign n5308_1 = ~n5503; + assign n5505 = n6349_1 & n6350 & (~n6000 | n6351); + assign n5313_1 = ~n5505; + assign n5507 = (n6697 | n6698) & (Pg35 | ~Ng5170); + assign n5318 = ~n5507; + assign n5509 = n7862 & (Pg35 | ~Ng2823); + assign n5331_1 = ~n5509; + assign n5511 = n6190 & (n6191 | ~Ng4854 | ~n8228); + assign n5339_1 = ~n5511; + assign n5513 = n6636 & n6637 & (Ng1274 | ~n5090); + assign n5349 = ~n5513; + assign n5515 = n6237 & (n6228 | n6236 | n6238); + assign n5361_1 = ~n5515; + assign n5517 = n6358 & (n6359_1 | ~Ng2509); + assign n5371_1 = ~n5517; + assign n5519 = n7881 & n7882 & (Pg35 | ~Ng1266); + assign n5381_1 = ~n5519; + assign n5521 = n6913 & ~n9451 & (n4205 | n6914); + assign n5393_1 = ~n5521; + assign n5523 = n7531 & ~n9294 & (~n6885 | ~n8449); + assign n5398_1 = ~n5523; + assign n5525 = n6957 & n6958 & (n4205 | n6959); + assign n5406_1 = ~n5525; + assign n5527 = n6137_1 & (Pg35 | ~Ng2999); + assign n5416 = ~n5527; + assign n5529 = n7827 & (Pg35 | ~Ng699); + assign n5421_1 = ~n5529; + assign n5531 = n6627 & n6628 & (n6470 | ~Ng1636); + assign n5426_1 = ~n5531; + assign n5533 = n7207 & n7208 & (n4205 | n7209); + assign n5431_1 = ~n5533; + assign n5535 = ~n7696 & (~Pg35 | n7695 | ~Ng2093); + assign n5436 = ~n5535; + assign n5537 = (Pg35 | ~Ng1052) & (n7889 | ~n9148); + assign n5451_1 = ~n5537; + assign n5539 = n6396 & n6397 & (~n6008_1 | n6398); + assign n5461 = ~n5539; + assign n5541 = n7968 & n7969 & (Ng956 | ~n8498); + assign n5466_1 = ~n5541; + assign n5543 = n6453 & ~n9445 & (~n5998_1 | n6454); + assign n5471_1 = ~n5543; + assign n5545 = n7465 & (n4205 | (Ng5849 & n7466)); + assign n5476_1 = ~n5545; + assign n5547 = n7337 & ~n9251 & (~Ng2685 | n7338); + assign n5486_1 = ~n5547; + assign n5549 = n6584 & n6585_1 & (n6395_1 | ~Ng2197); + assign n5491_1 = ~n5549; + assign n5551 = n6565_1 & (n6359_1 | ~Ng2421); + assign n5496_1 = ~n5551; + assign n5553 = n7891 & ~n9438 & (Pg35 | ~Ng1041); + assign n5501_1 = ~n5553; + assign n5555 = n7755 & n7832 & (~Pg35 | n7833); + assign n5506_1 = ~n5555; + assign n5557 = ~Ng4405 & (n7846 | ~Ng4388 | n7853); + assign n5511_1 = ~n5557; + assign n5559 = n5958 & (~Ng1536 | (Ng1526 & ~Ng1514)); + assign n5560 = Pg7946 ^ Ng1514; + assign n5516_1 = Pg35 & (n5559 | n5560); + assign n5562 = (~Ng6561 | n6657) & (~Ng6565 | n6658); + assign n5526_1 = ~n5562; + assign n5564 = n6168 & (Pg35 | ~Ng2936); + assign n5531_1 = ~n5564; + assign n5566 = n7813 & (~n6631 | Ng1345 | n7814); + assign n5536_1 = ~n5566; + assign n5568 = ~Pg35 | ~Ng4727; + assign n5549_1 = ~n5568; + assign n5570 = (~Pg17778 & (~Pg14828 | Pg12470)) | (Pg14828 & Pg12470); + assign n5554_1 = n5570 & ~Pg13099 & ~Pg17688 & Pg35 & ~Pg17722; + assign n5572 = n7193 & ~n9465 & (n4205 | n7194); + assign n5563_1 = ~n5572; + assign n5574 = n7367 & ~n9269 & (~Ng1858 | n7368); + assign n5578_1 = ~n5574; + assign n5576 = n7895 & (Pg35 | ~Ng246); + assign n5583_1 = ~n5576; + assign n5578 = n7315 & n7316 & (n4205 | n7317); + assign n5588_1 = ~n5578; + assign n5580 = n7719 & n7720 & (~Ng1740 | ~n8434); + assign n5593_1 = ~n5580; + assign n5582 = n6933 & n6934 & (n4205 | n6935); + assign n5598 = ~n5582; + assign n5584 = n6364 & n6365 & (~n6002 | n6366); + assign n5603_1 = ~n5584; + assign n5586 = n6430 & (Pg35 | ~Ng1955); + assign n5608_1 = ~n5586; + assign n5588 = n6942 & n6943 & (n4205 | n6944); + assign n5618_1 = ~n5588; + assign n5590 = n6895 & ~n9449 & (n4205 | n6654); + assign n5623_1 = ~n5590; + assign n5592 = n7234 & n7235 & (n4205 | n7236); + assign n5628 = ~n5592; + assign n5594 = n6603 & (Pg35 | ~Ng1974); + assign n5638 = ~n5594; + assign n5596 = n6477_1 & n6478 & (~n6010 | n6479); + assign n5643_1 = ~n5596; + assign n5598_1 = n6601 & n6602 & (~n8298 | ~Ng1982); + assign n5658_1 = ~n5598_1; + assign n5600 = n7144 & n7145 & (n4205 | n7146); + assign n5666_1 = ~n5600; + assign n5602 = n7802 & n7803 & (n7801 | ~n8472); + assign n5671 = ~n5602; + assign n5604 = ~Ng6381 | n8503; + assign n5676_1 = Ng6386 & (~Pg35 | n5604); + assign n5606 = n6848 & ~n9232 & (Pg35 | ~Ng5029); + assign n5695 = ~n5606; + assign n5608 = n6158 & (Pg35 | ~Ng4732); + assign n5700_1 = ~n5608; + assign n5610 = n7567 & (n4205 | (Ng3849 & n7568)); + assign n5710_1 = ~n5610; + assign n5612 = n7324 & n7325 & (n4205 | n7326); + assign n5718 = ~n5612; + assign n5614 = n7925 & (Pg35 | ~Ng5841); + assign n5723_1 = ~n5614; + assign n5616 = n6320_1 & n6321 & (n6312 | ~Ng4975); + assign n5728 = ~n5616; + assign n5618 = n6129 & n6130 & (Ng790 | n6131); + assign n5733_1 = ~n5618; + assign n5620 = n7000 & n7001 & (n4205 | n7002); + assign n5738_1 = ~n5620; + assign n5622 = n7366 & ~n9268 & (Pg35 | ~Ng1882); + assign n5743_1 = ~n5622; + assign n5624 = n7439 & ~n9282 & (~n6886 | ~n8442); + assign n5748 = ~n5624; + assign n5626 = n7762 & (Pg35 | ~Ng5619); + assign n5758_1 = ~n5626; + assign n5628_1 = (n7774 | ~n9144) & (n7775 | ~Ng4939); + assign n5763 = ~n5628_1; + assign n5630 = n7321 & n7322 & (n4205 | n7323); + assign n5772 = ~n5630; + assign n5632 = n7288 & n7289 & (n4205 | n7290); + assign n5781_1 = ~n5632; + assign n5634 = n7528 & (Pg35 | ~Ng5138); + assign n5786 = ~n5634; + assign n5636 = n7130 & ~n9462 & (n4205 | n7131); + assign n5791 = ~n5636; + assign n5638_1 = n7357 & ~n9263 & (~Ng2126 | n7358); + assign n5796 = ~n5638_1; + assign n5640 = n7365 & ~n9267 & (Pg35 | ~Ng1959); + assign n5811 = ~n5640; + assign n5642 = n7937 & n7938 & (Ng5097 | ~n8494); + assign n5816_1 = ~n5642; + assign n5644 = n7318 & n7319 & (n4205 | n7320); + assign n5821_1 = ~n5644; + assign n5646 = ~n7851 & ((Pg35 & Ng4388) | ~Ng4430); + assign n5833_1 = ~n5646; + assign n5648 = n7868 & (Pg35 | ~Ng2767); + assign n5838_1 = ~n5648; + assign n5650 = n7848 & n7849 & (n7844 | n7846); + assign n5846 = ~n5650; + assign n5652 = n6866 & n6867 & (Pg35 | ~Ng1361); + assign n5855_1 = ~n5652; + assign n5654 = n6407 & n6408 & (~n6008_1 | n6409); + assign n5869 = ~n5654; + assign n5656 = (n6377 | ~Ng2361) & (n6572 | ~Ng2331); + assign n5879_1 = ~n5656; + assign n5658 = n6877 & n6878 & (Ng582 | n6879); + assign n5888_1 = ~n5658; + assign n5660 = n7351 & ~n9259 & (Pg35 | ~Ng2307); + assign n5903_1 = ~n5660; + assign n5662_1 = n7820 & n7821 & (Ng907 | n7822); + assign n5908_1 = ~n5662_1; + assign n5664 = n7369 & (Pg35 | ~Ng1830); + assign n5918_1 = ~n5664; + assign n5666 = n7245 & n7246 & (n4205 | n7247); + assign n5923_1 = ~n5666; + assign n5668 = Ng2932 | Ng2999; + assign n5669 = n6085 & n6082 & n6083 & n6084; + assign n5928_1 = n5668 & Pg35; + assign n5671_1 = n6385_1 & n6386 & (~n6012_1 | n6387); + assign n5933_1 = ~n5671_1; + assign n5673 = n7825 & n7826 & (Pg35 | ~Ng681); + assign n5941_1 = ~n5673; + assign n5675 = n7740 & n7741 & (Pg35 | ~Ng827); + assign n5946_1 = ~n5675; + assign n5677 = n6513 & n6514 & (Pg35 | ~Ng5698); + assign n5951_1 = ~n5677; + assign n5679 = n6556 & ~n9429 & (~Ng2472 | n6555_1); + assign n5961_1 = ~n5679; + assign n5681 = n7012 & n7013 & (n4205 | n7014); + assign n5966_1 = ~n5681; + assign n5683 = n6449 & (Pg35 | ~Ng1821); + assign n5975_1 = ~n5683; + assign n5685 = n7270 & n7271 & (n4205 | n7272); + assign n5980_1 = ~n5685; + assign n5687 = n7948 & (Pg35 | ~Ng3841); + assign n5985_1 = ~n5687; + assign n5689 = n6590_1 & n6591 & (~n8291 | ~Ng2116); + assign n5990 = ~n5689; + assign n5691 = n7285 & n7286 & (n4205 | n7287); + assign n5998 = ~n5691; + assign n5693 = n7172 & n7173 & (n4205 | n7174); + assign n6003_1 = ~n5693; + assign n5695_1 = n6181 & (Pg35 | ~Ng2689); + assign n6032_1 = ~n5695_1; + assign n5697 = ~n8329 & (Pg35 | ~Ng4382); + assign n6037_1 = ~n5697; + assign n5699 = (n6658 | n6659) & (Pg35 | ~Ng6555); + assign n6042 = ~n5699; + assign n5701 = n7734 & (n7735 | ~Ng1141); + assign n6047_1 = ~n5701; + assign n5703 = n6625 & (Pg35 | ~Ng1706); + assign n6061 = ~n5703; + assign n5705 = n7405 & (Pg35 | ~Ng6523); + assign n6066_1 = ~n5705; + assign n5707 = n7291 & n7292 & (n4205 | n7293); + assign n6071_1 = ~n5707; + assign n5709 = ~n7723 & (~Pg35 | n7721 | ~Ng1691); + assign n6076_1 = ~n5709; + assign n5711 = n6169_1 & (Pg35 | ~Ng2922); + assign n6081 = ~n5711; + assign n5713 = n7931 & (Pg35 | ~Ng5148); + assign n6091 = ~n5713; + assign n5715 = ~\[4415] | n8506; + assign n6096 = Ng5348 & (~Pg35 | n5715); + assign n5717 = n6243 & (n6241 | n6242 | n6232); + assign n6104 = ~n5717; + assign n5719 = n6170 & (Pg35 | ~Ng2912); + assign n6109_1 = ~n5719; + assign n5721 = n7047 & n7048 & (n4205 | n7049); + assign n6119_1 = ~n5721; + assign n5723 = n6924 & n6925 & (n4205 | n6926); + assign n6127 = ~n5723; + assign n5725 = n6789 & n6790 & (n6785 | ~Ng2060); + assign n6132_1 = ~n5725; + assign n5727 = n7073 & n7074 & (n4205 | n7075); + assign n6142 = ~n5727; + assign n5729 = Pg135 | n6097; + assign n5730 = ~Ng4349 | ~Ng4358; + assign n5731 = ~Ng4633 | n8232; + assign n6152 = Pg35 & (n5729 | n5730 | n5731); + assign n5733 = n7630 & ~n9309 & (n7631 | ~Ng3129); + assign n6165 = ~n5733; + assign n5735 = (n6695 | n6701) & (Pg35 | ~Ng5164); + assign n6174_1 = ~n5735; + assign n5737 = n7926 & n7927 & (~n8390 | ~Ng5821); + assign n6183 = ~n5737; + assign n5739 = n6960 & n6961 & (n4205 | n6962); + assign n6188_1 = ~n5739; + assign n5741 = n7701 & n7702 & (~Ng2008 | ~n8428); + assign n6196 = ~n5741; + assign n5743 = n6533 & n6534 & (n6535 | ~Ng3703); + assign n6206 = ~n5743; + assign n5745 = n6142_1 & n6143; + assign n6216 = ~n5745; + assign n5747 = n7757 & ~n9330 & (n7758 | ~Ng411); + assign n6221 = ~n5747; + assign n5749 = n7186 & ~n9463 & (n4205 | n7187); + assign n6230 = ~n5749; + assign n5751 = n6180 & (Pg35 | ~Ng2697); + assign n6235 = ~n5751; + assign n5753_1 = n7960 & n7961 & (Ng1300 | ~n8496); + assign n6245 = ~n5753_1; + assign n5755 = n7156 & n7157 & (n4205 | n7158); + assign n6255 = ~n5755; + assign n5757 = n6854 & (n6855 | ~Ng5046 | ~n8722); + assign n6265 = ~n5757; + assign n5759 = ~n7687 & (~Pg35 | n7686 | ~Ng2250); + assign n6270 = ~n5759; + assign n5761 = ~n5991 & n6706 & (~n6860 | ~Ng4546); + assign n6279 = ~n5761; + assign n5763_1 = n6763 & n6764 & (Pg35 | ~Ng2461); + assign n6284 = ~n5763_1; + assign n5765 = n6171 & (Pg35 | ~Ng2907); + assign n6297 = ~n5765; + assign n5767 = n6767 & n6768 & (~Ng2357 | n6766); + assign n6302 = ~n5767; + assign n5769 = n6880 & n6881 & (Pg35 | ~Ng146); + assign n6310 = ~n5769; + assign n5771 = n6162 & (Pg35 | ~Ng4300); + assign n6315 = ~n5771; + assign n5773 = n6858 & (n6855 | Ng5016 | ~n8380); + assign n6320 = ~n5773; + assign n5775 = n7955 & n7956 & (~n8409 | ~Ng3119); + assign n6325_1 = ~n5775; + assign n5777 = ~n7965 & (~Ng1312 | (Pg35 & n5425)); + assign n6330 = ~n5777; + assign n5779 = n7553 & (Ng5115 | n7554) & ~n9296; + assign n6344_1 = ~n5779; + assign n5781 = n6539 & n6540 & (Pg35 | ~Ng3347); + assign n6349 = ~n5781; + assign n5783 = n6891 & (Pg35 | ~Ng6653); + assign n6354 = ~n5783; + assign n5785 = n7219 & n7220 & (n4205 | n7221); + assign n6364_1 = ~n5785; + assign n5787 = n7280 & n7281 & (n4205 | n7282); + assign n6369 = ~n5787; + assign n5789 = n7076 & ~n9459 & (n4205 | n7077); + assign n6380 = ~n5789; + assign n5791_1 = n7225 & (Pg35 | ~Ng3610); + assign n6385 = ~n5791_1; + assign n5793 = n6176 & (Pg35 | ~Ng2860); + assign n6390 = ~n5793; + assign n5795 = n7949 & n7950 & (~n8401 | ~Ng3821); + assign n6403 = ~n5795; + assign n5797 = n7944 & n7945 & (Pg35 | ~Ng4057); + assign n6408_1 = ~n5797; + assign n5799 = n7108 & (Pg35 | ~Ng5268); + assign n6417 = ~n5799; + assign n5801_1 = n6333 & n7656 & (Ng2735 | n7657); + assign n6422 = ~n5801_1; + assign n5803 = n6963 & n6964 & (n4205 | n6965); + assign n6432 = ~n5803; + assign n5805 = n7339 & (Pg35 | ~Ng2657); + assign n6437 = ~n5805; + assign n5807 = n7932 & n7933 & (n7934 | ~Ng5128); + assign n6447 = ~n5807; + assign n5809 = n7655 & ~n9312 & (Pg35 | ~Ng3111); + assign n6457 = ~n5809; + assign n5811_1 = n6199 & ~n9440 & (Pg35 | ~Ng4653); + assign n6462 = ~n5811_1; + assign n5813 = (Pg35 | ~Ng4349) & (n5968 | ~n8636); + assign n6467 = ~n5813; + assign n5815 = n6809 & n6810 & (n6805 | ~Ng1792); + assign n6472 = ~n5815; + assign n5817 = n6413_1 & (n6414 | ~Ng2084); + assign n6477 = ~n5817; + assign n5819 = n7330 & n7331 & (n4205 | n7332); + assign n6482 = ~n5819; + assign n5821 = n8233 ^ Ng4311; + assign n6487 = n5821 & ~n8235; + assign n5823 = n6341 & n6342 & (~n6000 | n6343); + assign n6492 = ~n5823; + assign n5825 = n7327 & n7328 & (n4205 | n7329); + assign n6517 = ~n5825; + assign n5827 = n7991 & n7992 & (Ng385 | n7993); + assign n6541 = ~n5827; + assign n5829 = n6426 & n6427_1 & (~n6004 | n6428); + assign n6546 = ~n5829; + assign n5831 = n7344 & (Pg35 | ~Ng2523); + assign n6551 = ~n5831; + assign n5833 = n7312 & n7313 & (n4205 | n7314); + assign n6580 = ~n5833; + assign n5835 = n6166 & (Pg35 | ~Ng2960); + assign n6585 = ~n5835; + assign n5837 = ~Ng5689 | ~n8505; + assign n6590 = Ng5694 & (~Pg35 | n5837); + assign n5839 = n7123 & ~n9460 & (n4205 | n7124); + assign n6595 = ~n5839; + assign n5841 = (~Ng3518 | n6727) & (~Ng3522 | n6728); + assign n6605 = ~n5841; + assign n5843 = n7632 & ~n9310 & (~n6890 | ~n8456); + assign n6610 = ~n5843; + assign n5845 = n7294 & n7295 & (n4205 | n7296); + assign n6615 = ~n5845; + assign n5847 = n7843 & (Pg35 | ~Ng4455); + assign n6620 = ~n5847; + assign n5849 = n6210 & n6211_1 & (n6206_1 | ~Ng4628); + assign n6624 = ~n5849; + assign n5851 = n6598 & (n6414 | ~Ng1996); + assign n6629 = ~n5851; + assign n5853 = n7841 & ~n8127 & (Pg35 | ~Ng4527); + assign n6638 = ~n5853; + assign n5855 = n7372 & ~n9272 & (~Ng1724 | n7373); + assign n6651 = ~n5855; + assign n5857 = (~Ng1379 | ~n9115) & (n6635 | ~Ng1373); + assign n6656 = ~n5857; + assign n5859_1 = (~Pg16744 & (~Pg13926 | Pg11388)) | (Pg13926 & Pg11388); + assign n6661 = n5859_1 & ~Pg14451 & ~Pg16627 & Pg35 & ~Pg16656; + assign n5861 = n6442_1 & n6443 & (~n6006 | n6444); + assign n6665 = ~n5861; + assign n5863 = n7053 & (Pg35 | ~Ng5615); + assign n6670 = ~n5863; + assign n5865 = Pg35 & (Ng5845 | Ng5831); + assign n5866 = Ng2724 | Ng2729; + assign n5867 = n8206 & Ng2735; + assign n5868 = ~n8373 & (n5866 | (n5867 & ~Ng2771)); + assign n5869_1 = n6058 & n6059 & n6060; + assign n3891_1 = ~n5869_1; + assign n5871 = n8259 | ~Ng1514; + assign n5872 = Pg17423 & (n5871 | ~Ng1526); + assign n5873 = Pg17320 & (Ng1526 | n5871); + assign n5874_1 = Ng4709 | ~Ng4785; + assign n5875 = n8208 | n8316; + assign n5876 = Ng4674 & (n5874_1 | n5875 | ~Ng4743); + assign n5877 = ~Ng3129 & ~Ng3143; + assign n5878 = ~n8373 & (n5866 | (n5867 & ~Ng2803)); + assign n2738_1 = ~n5669; + assign n5880 = Ng4420 | Ng4427; + assign n5881 = Pg35 & (Ng6537 | Ng6523); + assign n5882 = n8210 | n8317; + assign n5883 = ~Ng4888 | Ng4899 | Ng4975; + assign n5884_1 = Ng4836 & (n5882 | n5883); + assign n5885 = Pg35 & (Ng6191 | Ng6177); + assign n5886 = ~Ng1183 | n8288; + assign n5887 = Pg17400 & (n5886 | ~Ng1171); + assign n5888 = ~Ng4899 | Ng4975; + assign n5889 = Ng4871 & (n5882 | n5888 | ~Ng4944); + assign n2237_1 = ~n4252; + assign n2890_1 = ~n4909; + assign n5892 = n6075 & n6076 & n6077; + assign n1349_1 = ~n5892; + assign n5894 = Pg17316 & (Ng1171 | n5886); + assign n5895 = n6033 & n6034 & n6035; + assign n2511_1 = ~n5895; + assign n5897 = n5970 | ~Ng4180; + assign n5898_1 = ~n5997 & (n5897 | (Ng1105 & ~Ng947)); + assign n5899 = ~n8370 & (n5866 | (n5867 & ~Ng2783)); + assign n5648_1 = ~n5930; + assign n5901 = n6273 & n6272 & n6271 & n6269 & n6266 & n6267 & n6268 & n6270_1; + assign n5902 = Pg35 & (Ng3480 | Ng3494); + assign n5903 = n6042_1 & n6039 & n6040 & n6041; + assign n1586 = ~n5903; + assign n5905 = Pg35 & (Ng5152 | Ng5138); + assign n5906 = Pg35 & (Ng3845 | Ng3831); + assign n5907 = Ng4899 | ~Ng4975; + assign n5908 = Ng4864 & (n5882 | n5907 | ~Ng4933); + assign n5909 = Ng1514 | n8259; + assign n5910 = Pg17404 & (~Ng1526 | n5909); + assign n5911 = Ng1430 & (Ng1526 | n5909); + assign n5912 = n6050 & n6047 & n6048 & n6049; + assign n4939 = ~n5912; + assign n5914 = Ng1183 | n8288; + assign n5915 = ~Ng4698 | Ng4709 | Ng4785; + assign n5916 = ~n8255 & (n5866 | (n5867 & ~Ng2787)); + assign n4035_1 = ~n5929; + assign n5918 = Pg35 & (Ng5499 | Ng5485); + assign n5919 = ~n8370 & (n5866 | (n5867 & ~Ng2815)); + assign n5920 = ~n8255 & (n5866 | (n5867 & ~Ng2819)); + assign n5921 = Ng1087 & (Ng1171 | n5914); + assign n5922 = n5971 | ~Ng4180; + assign n5923 = ~n5999 & (n5922 | (Ng1300 & ~Ng1291)); + assign n5924 = ~Pg134 & (~Pg99 | ~Ng37); + assign n5925 = ~n7957 & (n5866 | (n5867 & ~Ng2807)); + assign n5926 = ~Ng4899 | ~Ng4975; + assign n5927 = Ng4878 & (n5882 | n5926 | ~Ng4955); + assign n3802_1 = ~n5945; + assign n5929 = n6123 & (n6124 | n6125 | n6126); + assign n5930 = n6108 & n6106 & n6103 & n6104_1 & n6105 & n6107; + assign n5931 = n8184 | n8185; + assign n6497 = ~Pg35 & Ng2975; + assign n5933 = Ng482 & ~Ng528 & Ng490; + assign n5934 = ~n8469 & (Ng528 | n5933); + assign n5935 = n5883 & n6136 & (n5907 | ~Ng4933); + assign n5936 = n5935 & \[4651] & \[4658] & ~n5924; + assign n2341_1 = ~n6122; + assign n5938 = n6310_1 & n6309 & n6308 & n6306 & n6303 & n6304 & n6305 & n6307; + assign n5939 = ~Ng4709 | Ng4785; + assign n5940 = Ng4681 & (n5875 | n5939 | ~Ng4754); + assign n5941 = ~n7957 & (n5866 | (n5867 & ~Ng2775)); + assign n5942 = ~n6001 & (n5922 | (Ng1472 & ~Ng1291)); + assign n3296_1 = ~n8177; + assign n5944 = ~n6003 & (n5897 | (Ng956 & ~Ng947)); + assign n5945 = ~n6109 & (n6090 | (n6110 & n6111)); + assign n2027_1 = ~n9418; + assign n5947 = n8226 | n8227; + assign n5948 = ~n6005 & (n5897 | (Ng1129 & ~Ng947)); + assign n5949 = n5915 & n6135 & (n5939 | ~Ng4754); + assign n5950 = n5949 & \[4651] & \[4658] & ~n5924; + assign n5951 = ~Ng4709 | ~Ng4785; + assign n5952 = Ng4688 & (n5875 | n5951 | ~Ng4765); + assign n5953 = ~n6007 & (n5922 | (Ng1478 & ~Ng1291)); + assign n5954 = ~n6009 & (n5897 | (Ng1135 & ~Ng947)); + assign n6179 = ~Pg35 & Ng4392; + assign n5956_1 = ~n6011 & (n5922 | (Ng1448 & ~Ng1291)); + assign n5957 = \[4436] & (~Pg12368 | Pg9048); + assign n5958 = n5963 & Pg7946 & (n5964 | n5965); + assign n5959 = n7386 & Pg7916 & n8439; + assign n5960 = ~Ng518 & ~Ng482 & ~n8181 & ~Ng499 & ~Ng528 & ~Ng490; + assign n5961 = n9154 & (~Ng718 | ~Ng655 | ~Ng753); + assign n5962 = n5960 & n5961 & (~Ng807 | ~Ng554); + assign n5963 = Ng1339 & Ng1521 & ~Ng1532; + assign n5964 = n8082 & Ng1367 & Ng1345 & Ng1379; + assign n5965 = Ng1351 | Ng1312; + assign n5966 = ~Pg113 & ~n5924; + assign n5967 = Pg72 | Pg73; + assign n5968 = Ng65 & (n5966 | n5967); + assign n5969 = ~Ng691 | Ng209; + assign n5970 = ~Pg134 & (n5969 | ~n6128); + assign n5971 = ~Pg134 & (n5091 | n5969); + assign n5972 = ~n4252 ^ n5912; + assign n5973 = ~n5895 ^ n5903; + assign n5974 = n4252 ^ n5912; + assign n5975 = n5895 ^ n5903; + assign n5976 = (n5972 | n5973) & (n5974 | n5975); + assign n5977 = ~n4909 ^ n5669; + assign n5978 = ~n5869_1 ^ n5892; + assign n5979 = n4909 ^ n5669; + assign n5980 = n5869_1 ^ n5892; + assign n5981 = (n5977 | n5978) & (n5979 | n5980); + assign n5982 = n7978 & n7979; + assign n5983 = Ng225 | n8137; + assign n5984 = ~n8137 | ~Ng225; + assign n5985 = ~n9436 & (n5982 | (n5983 & n5984)); + assign n2498_1 = ~n5949; + assign n6675 = ~n5935; + assign n5988 = Ng2357 | Ng2491 | Ng2223 | Ng2472 | Ng2204 | Ng2625 | Ng2338 | Ng2606; + assign n5989 = Ng2283 | Ng2685 | Ng2417 | Ng2537 | Ng2671 | Ng2551 | Ng2403 | Ng2269; + assign n5990_1 = ~n6860 & (~Pg73 | Pg72); + assign n5991 = ~n6860 & (Pg73 | ~Pg72); + assign n5992 = ~Pg35 & (~n6015 | ~n8158); + assign n5993 = Ng4578 & ~n6860; + assign n5994 = ~Ng2756 | ~Ng2748 | ~Ng2735 | ~Ng2741; + assign n5995 = n8198 & Pg35; + assign n5996 = n5994 & n5995 & (Ng2756 | Ng2748); + assign n5997 = ~n5970 & n6448 & (~Ng1105 | Ng947); + assign n5998_1 = Pg35 & (n5898_1 | (~\[4421] & n5997)); + assign n5999 = ~n5971 & n6336 & (~Ng1300 | Ng1291); + assign n6000 = Pg35 & (n5923 | (n5999 & ~Ng1585)); + assign n6001 = ~n5971 & n6355 & (~Ng1472 | Ng1291); + assign n6002 = Pg35 & (n5942 | (Ng1585 & n6001)); + assign n6003 = ~n5970 & n6410 & (~Ng956 | Ng947); + assign n6004 = Pg35 & (n5944 | (~\[4421] & n6003)); + assign n6005 = ~n5970 & n6429 & (~Ng1129 | Ng947); + assign n6006 = Pg35 & (n5948 | (\[4421] & n6005)); + assign n6007 = ~n5971 & n6391 & (~Ng1478 | Ng1291); + assign n6008_1 = Pg35 & (n5953 | (n6007 & Ng1585)); + assign n6009 = ~n5970 & n6466 & (~Ng1135 | Ng947); + assign n6010 = Pg35 & (n5954 | (n6009 & \[4421] )); + assign n6011 = ~n5971 & n6373_1 & (~Ng1448 | Ng1291); + assign n6012_1 = Pg35 & (n5956_1 | (~Ng1585 & n6011)); + assign n6013 = (n6027_1 | ~Ng758) & (~Ng586 | n8157); + assign n6014 = ~n5992 & n9071 & (n6063 | ~Ng613); + assign n6015 = n8147 | n8150; + assign n6016 = n6013 & n6014 & (n6015 | ~Ng794); + assign n6017_1 = (n6031 | ~Ng2950) & (n6056_1 | ~Ng2955); + assign n6018 = n6036 & n9070 & (~Ng2868 | n8149); + assign n6019 = n8151 | ~Ng51 | n8148; + assign n6020 = n6017_1 & n6018 & (~Ng37 | n6019); + assign n6021 = (Ng4927 | n8168) & (Ng4737 | n8169); + assign n6022 = (~Ng947 | n8163) & (~Ng4300 | n8166); + assign n6023 = (~Ng1291 | n8161) & (n6016 | n8142); + assign n6024 = n9072 & (~Ng4172 | n8155); + assign n6025 = (n6015 | ~Ng785) & (~Ng568 | n8157); + assign n6026 = ~n5992 & n9079 & (~\[4426] | n8159); + assign n6027_1 = n8151 | ~Ng51 | n8150; + assign n6028 = n6025 & n6026 & (n6027_1 | ~Ng744); + assign n6029 = (~Pg92 | n6019) & (~Pg127 | n8149); + assign n6030 = n9078 & (~Ng2975 | n6056_1); + assign n6031 = ~n8144 | ~Ng51 | n8150; + assign n6032 = n6029 & n6030 & (n6031 | ~Ng2970); + assign n6033 = (n8155 | ~Ng4146) & (n8166 | ~Ng4249); + assign n6034 = (n8173 | ~Ng2697) & (n6028 | n8142); + assign n6035 = n9080 & n9081 & (n8163 | ~Ng939); + assign n6036 = ~Ng51 | n8143 | ~n8144; + assign n6037 = (n8149 | ~Ng2890) & (n8174 | ~Ng2984); + assign n6038 = n6036 & n6037 & (~Pg100 | n6019); + assign n6039 = (n8161 | ~Ng1287) & (n8163 | ~Ng943); + assign n6040 = (n8166 | ~Ng4245) & (n8171 | ~Ng2145); + assign n6041 = (n8155 | ~Ng4157) & (n8173 | ~Ng2704); + assign n6042_1 = n9086 & (n8142 | (n9085 & n9083)); + assign n6043 = (n6031 | ~Ng2960) & (n6056_1 | ~Ng2965); + assign n6044 = (n8149 | ~Ng2873) & (~\[4433] | n6019); + assign n6045 = n8150 | ~Ng48 | n8146; + assign n6046 = n6043 & n6044 & (n6045 | ~Ng2878); + assign n6047 = (~Ng2689 | n8173) & (n8163 | Ng952); + assign n6048 = (n8155 | ~Ng4176) & (~Ng2130 | n8171); + assign n6049 = (n8161 | Ng1296) & (n8166 | ~Ng4253); + assign n6050 = n9077 & (n8142 | (n9076 & n9074)); + assign n6051 = (n8159 | ~Ng546) & (~Ng582 | n8157); + assign n6052 = ~n5992 & n9093 & (n6063 | ~Ng622); + assign n6053 = n6051 & n6052 & (n6027_1 | ~Ng767); + assign n6054 = (n6045 | ~Ng2864) & (n6080 | ~Ng2860); + assign n6055 = (n6031 | ~Ng2922) & (n8149 | Ng2994); + assign n6056_1 = n8150 | ~n8144 | Ng51; + assign n6057 = n6054 & n6055 & (n6056_1 | ~Ng2927); + assign n6058 = (n8168 | ~Ng4907) & (n8173 | ~Ng3151); + assign n6059 = (n8169 | ~Ng4717) & (n6053 | n8142); + assign n6060 = n9094 & n9095 & (n6057 | n8142); + assign n6061_1 = (~Ng595 | n8157) & (Pg35 | n8158); + assign n6062 = (n8159 | ~Ng538) & (n6027_1 | ~Ng776); + assign n6063 = n8143 | n8156; + assign n6064 = n6061_1 & n6062 & (n6063 | ~Ng632); + assign n6065 = (n8169 | ~Ng4727) & (n8171 | ~Ng6199); + assign n6066 = (n8168 | ~Ng4917) & (n8173 | ~Ng3853); + assign n6067 = (n8153 | ~Ng45) & (n6064 | n8142); + assign n6068 = n9089 & (n8142 | (n9088 & n9087)); + assign n6069 = (n6015 | ~Ng807) & (~Ng577 | n8157); + assign n6070 = ~n5992 & n9097 & (n8159 | ~Ng542); + assign n6071 = n6069 & n6070 & (n6027_1 | ~Ng763); + assign n6072 = (n6031 | ~Ng2936) & (n6080 | ~Ng2894); + assign n6073 = n6036 & n9096 & (n8149 | ~Ng2988); + assign n6074 = n6072 & n6073 & (n6056_1 | ~Ng2941); + assign n6075 = (n8169 | ~Ng4722) & (n6071 | n8142); + assign n6076 = (n8171 | ~Ng5160) & (n8173 | ~Ng6545); + assign n6077 = n9098 & n9099 & (n6074 | n8142); + assign n6078 = (n6045 | ~Ng2856) & (n6056_1 | ~Ng2917); + assign n6079 = (n6031 | ~Ng2912) & (n8149 | ~Ng2999); + assign n6080 = n8154 | ~Ng48 | n8150; + assign n6081_1 = n6078 & n6079 & (n6080 | ~Ng2852); + assign n6082 = (n8168 | ~Ng4922) & (n8173 | ~Ng3502); + assign n6083 = (n8169 | ~Ng4732) & (n8171 | ~Ng5853); + assign n6084 = (n8153 | ~Ng46) & (n6081_1 | n8142); + assign n6085 = n9092 & (n8142 | (n9091 & n9090)); + assign n6086 = n5981 ^ n5976; + assign n6087 = n6086 & (~Ng55 | (~Pg56 & Pg54)); + assign n6088 = ~n6086 & Ng55 & (Pg56 | ~Pg54); + assign n6089 = ~n8177 & ~Pg53 & ~Pg56 & ~Pg54; + assign n6090 = n8179 | Ng4311 | n8178; + assign n6091_1 = n5962 & (~Pg12184 | Pg11678); + assign n6092 = (n7743 | ~Ng554) & (Pg35 | ~Ng807); + assign n6093 = ~Ng794 | n6114; + assign n6094 = n9158 & (Ng4584 | ~Ng4608 | Ng4593); + assign n6095 = Ng4584 ^ Ng4608; + assign n6096_1 = Ng4601 ^ Ng4593; + assign n6097 = n6094 & (Ng4616 | n6095 | n6096_1); + assign n6098 = ~n6093 | ~Ng807 | n7743; + assign n6099 = Pg35 | ~Ng794; + assign n6100 = ~Ng632 | ~n6102 | n8183; + assign n6101 = Pg35 | ~Ng626; + assign n6102 = ~Ng626 | n6117; + assign n6103 = n8068 | n6269; + assign n6104_1 = ~Ng2070 | n6267 | Ng2040; + assign n6105 = ~Ng1936 | n6272 | Ng1906; + assign n6106 = ~Ng2227 | n6271 | Ng2197; + assign n6107 = (n8078 | n6266) & (n8080 | n6268); + assign n6108 = (n8070 | n6270_1) & (n8066 | n6273); + assign n6109 = ~n6124 & (~n9100 | ~n9101); + assign n6110 = (n5730 | n7445) & (n8191 | n8192); + assign n6111 = (n8188 | n7507) & (n8190 | n7476); + assign n6112 = ~Ng794 | ~n6114 | n7743; + assign n6113 = Pg35 | ~Ng790; + assign n6114 = ~Ng790 | n6131; + assign n6115 = ~Ng626 | ~n6117 | n8183; + assign n6116 = Pg35 | ~Ng622; + assign n6117 = ~Ng622 | n6134; + assign n6118 = (n8205 | n6306) & (n8207 | n6310_1); + assign n6119 = (n8203 | n6303) & (n8204 | n6305); + assign n6120 = (n8201 | n6309) & (n8202 | n6308); + assign n6121 = (n8197 | n6307) & (n8199 | n6304); + assign n6122 = n6121 & n6118 & n6119 & n6120; + assign n6123 = n8065 | n6090 | n7796; + assign n6124 = n8179 | ~Ng4311 | n8178; + assign n6125 = n5926 | n8211; + assign n6126 = ~Ng4878 | n8210; + assign n6127_1 = Ng2389 | Ng2657 | Ng2523 | Ng2255; + assign n6128 = Ng1193 & (Ng969 | Ng1008); + assign n6129 = ~Ng790 | ~n6131 | n7743; + assign n6130 = Pg35 | ~Ng785; + assign n6131 = ~Ng785 | n6148; + assign n6132 = ~Ng622 | ~n6134 | n8183; + assign n6133 = Pg35 | ~Ng617; + assign n6134 = ~Ng617 | n6151; + assign n6135 = (n5874_1 | ~Ng4743) & (n5951 | ~Ng4765); + assign n6136 = (n5888 | ~Ng4944) & (n5926 | ~Ng4955); + assign n6137_1 = ~Pg35 | ~Ng2994; + assign n6138 = (~Pg35 | ~Ng1287) & ~n8478; + assign n6139 = Pg35 | ~Ng1283; + assign n6140 = n4219 & (~Pg35 | ~Ng1296); + assign n6141 = Pg35 | ~Ng1291; + assign n6142_1 = n4217 & (~Pg35 | ~Ng943); + assign n6143 = Pg35 | ~Ng939; + assign n6144 = n4218 & (~Pg35 | ~Ng952); + assign n6145 = Pg35 | ~Ng947; + assign n6146 = ~Ng785 | ~n6148 | n7743; + assign n6147_1 = Pg35 | ~Ng781; + assign n6148 = ~Ng781 | n6186; + assign n6149 = ~Ng617 | ~n6151 | n8183; + assign n6150 = Pg35 | ~Ng613; + assign n6151 = ~Ng613 | n6189; + assign n6152_1 = ~Pg35 | ~Ng4927; + assign n6153 = ~Pg35 | ~Ng4912; + assign n6154 = ~Pg35 | ~Ng4907; + assign n6155 = ~Pg35 | ~Ng4922; + assign n6156_1 = ~Pg35 | ~Ng4737; + assign n6157 = ~Pg35 | ~Ng4722; + assign n6158 = ~Pg35 | ~Ng4717; + assign n6159 = ~Pg35 | ~Ng4732; + assign n6160_1 = ~Pg35 | ~Ng4245; + assign n6161 = ~Pg35 | ~Ng4249; + assign n6162 = ~Pg35 | ~Ng4253; + assign n6163 = ~Pg35 | ~Ng4157; + assign n6164 = ~Pg35 | ~Ng4146; + assign n6165_1 = ~Pg35 | ~Ng2988; + assign n6166 = ~Pg35 | ~Ng2970; + assign n6167 = ~Pg35 | ~Ng2960; + assign n6168 = ~Pg35 | ~Ng2950; + assign n6169_1 = ~Pg35 | ~Ng2936; + assign n6170 = ~Pg35 | ~Ng2922; + assign n6171 = ~Pg35 | ~Ng2912; + assign n6172 = ~Pg35 | ~Ng2907; + assign n6173 = ~Pg35 | ~Ng2868; + assign n6174 = ~Pg35 | ~Ng2873; + assign n6175 = (~Pg35 | ~Ng37) & n9187; + assign n6176 = ~Pg35 | ~Ng2894; + assign n6177 = ~Pg35 | ~Ng2860; + assign n6178 = ~Pg35 | ~Ng2852; + assign n6179_1 = ~Pg35 | ~Ng2844; + assign n6180 = ~Pg35 | ~Ng2704; + assign n6181 = ~Pg35 | ~Ng2697; + assign n6182 = ~Pg35 | ~Ng2145; + assign n6183_1 = ~Pg35 | ~Ng2138; + assign n6184 = ~Ng781 | ~n6186 | n7743; + assign n6185 = Pg35 | ~Ng776; + assign n6186 = ~Ng776 | n6257; + assign n6187 = ~Ng613 | ~n6189 | n8183; + assign n6188 = Pg35 | ~Ng608; + assign n6189 = ~Ng608 | n6259; + assign n6190 = (Pg35 | ~Ng4854) & (n6193 | ~Ng4859); + assign n6191 = ~Ng4849 | n8229; + assign n6192_1 = n6191 ^ Ng4854; + assign n6193 = ~Pg35 | ~n8228; + assign n6194 = n8229 | Ng4849 | ~n8228; + assign n6195 = (Pg35 | ~Ng4664) & (n6198 | ~Ng4669); + assign n6196_1 = ~Ng4659 | n8231; + assign n6197 = n6196_1 ^ Ng4664; + assign n6198 = ~Pg35 | ~n8230; + assign n6199 = n8231 | Ng4659 | ~n8230; + assign n6200 = n5968 | Ng4643; + assign n6201 = Pg35 & (Ng4621 | n6200); + assign n6202 = Ng4639 | n6205; + assign n6203 = ~n5968 & (~Ng4621 | Ng4639 | ~Ng4628); + assign n6204 = ~n5968 & Ng4340; + assign n6205 = ~Pg35 | n6200; + assign n6206_1 = n6202 & (Ng4621 | n6205); + assign n6207 = n6206_1 & (Ng4628 | n6205); + assign n6208 = ~Ng4621 | n6200; + assign n6209 = Pg35 & (Ng4633 | ~Ng4639 | n6208); + assign n6210 = n6208 | ~Ng4639 | Ng4628; + assign n6211_1 = Pg35 | ~Ng4621; + assign n6212 = ~n5968 & (~Ng4616 | ~n8234); + assign n6213 = (~Ng4616 | n6220) & (Pg35 | ~Ng4608); + assign n6214 = ~Ng4601 | n8061; + assign n6215 = (Pg35 | ~Ng4322) & (~Ng4332 | n8235); + assign n6216_1 = n5968 | n8062; + assign n6217 = ~Ng4608 | ~n6214 | n6220; + assign n6218 = Ng4608 | ~n6212 | n6214; + assign n6219 = Ng4601 ^ n8061; + assign n6220 = ~Pg35 | ~n6212; + assign n6221_1 = n8234 | n6220 | ~Ng4593; + assign n6222 = ~n8234 | ~n6212 | Ng4593; + assign n6223 = ~n8062 ^ Ng4584; + assign n6224 = n8236 | ~Ng4322 | n8235; + assign n6225 = ~n8236 | n6216_1 | Ng4322; + assign n6226_1 = ~n8329 & (~Pg35 | Ng2827); + assign n6227 = n9193 & (~Pg35 | ~n6229 | ~Ng2819); + assign n6228 = n5966 & Ng111; + assign n6229 = ~Ng2729 | n5994 | ~Ng2724; + assign n6230_1 = ~n8329 & (~Pg35 | Ng2811); + assign n6231 = n9194 & (~Pg35 | ~n6232 | ~Ng2807); + assign n6232 = Ng2729 | n5994 | ~Ng2724; + assign n6233 = ~n8329 & (~Pg35 | Ng2823); + assign n6234 = n9195 & (~Pg35 | ~n6235_1 | ~Ng2815); + assign n6235_1 = ~Ng2729 | n5994 | Ng2724; + assign n6236 = ~n8329 & (~Pg35 | Ng2799); + assign n6237 = n9196 & (~Pg35 | ~n6238 | ~Ng2803); + assign n6238 = n5994 | n5866; + assign n6239 = ~n8329 & (~Pg35 | Ng2795); + assign n6240_1 = n9197 & (~Pg35 | ~n6229 | ~Ng2787); + assign n6241 = n5966 & Ng85; + assign n6242 = ~n8329 & (~Pg35 | Ng2779); + assign n6243 = n9198 & (~Pg35 | ~n6232 | ~Ng2775); + assign n6244 = ~n8329 & (~Pg35 | Ng2791); + assign n6245_1 = n9199 & (~Pg35 | ~n6235_1 | ~Ng2783); + assign n6246 = ~n8329 & (~Pg35 | Ng2767); + assign n6247 = n9200 & (~Pg35 | ~n6238 | ~Ng2771); + assign n6248 = ~Ng182 ^ n9201; + assign n6249 = (Ng392 & ~Ng441) | (~Ng411 & (~Ng392 | ~Ng441)); + assign n6250_1 = ~Ng417 & n6248 & n6249 & ~Ng691; + assign n6251 = ~Ng703 & ~n5049 & n5050; + assign n6252 = Ng376 & Ng385 & Pg8719; + assign n6253 = Ng896 & (n6252 | n6251); + assign n6254 = (~Ng890 | ~Ng896) & (n6253 | ~Ng862); + assign n6255_1 = ~Ng776 | ~n6257 | n7743; + assign n6256 = Pg35 | ~Ng772; + assign n6257 = ~Ng772 | n6295; + assign n6258 = Pg35 | ~Ng604; + assign n6259 = ~Ng604 | n6297_1; + assign n6260_1 = ~Ng4141 & ~Ng4082; + assign n6261 = Ng4093 | Ng4098; + assign n6262 = ~Ng4076 | ~Ng4112; + assign n6263 = n6260_1 & (Ng4087 | n6261 | n6262); + assign n6264 = Pg113 & ~n5924; + assign n6265_1 = (~n6090 | ~n6124) & n6264; + assign n6266 = ~Ng504 | Ng528 | n8186; + assign n6267 = n8187 | Ng504 | Ng528; + assign n6268 = n8186 | Ng504 | Ng528; + assign n6269 = ~Ng528 | ~Ng504 | n8187; + assign n6270_1 = ~Ng504 | ~Ng528 | n8186; + assign n6271 = Ng504 | ~Ng528 | n8186; + assign n6272 = n8187 | Ng528 | ~Ng504; + assign n6273 = n8187 | ~Ng528 | Ng504; + assign n6274 = (~Ng4961 | ~n8237) & ~n8238; + assign n6275_1 = (~n8237 | ~Ng4950) & ~n8238; + assign n6276 = (~Pg35 | ~n8238) & (~n8237 | ~Ng4939); + assign n6277 = Pg35 | ~Ng4939; + assign n6278 = ~Pg35 | ~n6279_1 | ~Ng4933; + assign n6279_1 = n7774 & n8237; + assign n6280 = ~n8238 & (~n8237 | ~Ng4894); + assign n6281 = n8239 | ~Ng101; + assign n6282 = n6281 & (~Ng4771 | ~n8239); + assign n6283 = n6281 & (~n8239 | ~Ng4760); + assign n6284_1 = (~Pg35 | n6281) & (~n8239 | ~Ng4749); + assign n6285 = Pg35 | ~Ng4749; + assign n6286 = ~Pg35 | ~n6287 | ~Ng4743; + assign n6287 = n7790 & n8239; + assign n6288 = n6281 & (~n8239 | ~Ng4704); + assign n6289_1 = ~n5967 & (n5924 | Ng4507); + assign n6290 = ~Ng26960 | n6289_1 | Ng4477; + assign n6291 = n6290 & ~Ng4459 & (Ng4462 | ~Ng4473); + assign n6292 = Ng4643 & Pg35 & Ng4462 & ~Ng10384; + assign n6293_1 = ~Ng772 | ~n6295 | n7743; + assign n6294 = Pg35 | ~Ng767; + assign n6295 = ~Ng767 | n6488; + assign n6296 = Pg35 | ~Ng599; + assign n6297_1 = ~Ng599 | n6490; + assign n6298 = Ng142 | n8245; + assign n6299 = ~Ng142 | n7834 | ~n8245; + assign n6300 = n4520 & (Ng182 | Ng174 | Ng168); + assign n6301 = Ng160 | n9218; + assign n6302_1 = ~n9218 | ~Ng160 | n7402; + assign n6303 = n8200 | ~Ng2756 | Ng2741; + assign n6304 = n8195 | n8198; + assign n6305 = ~Ng2741 | n8196; + assign n6306 = ~Ng2756 | ~Ng2741 | n8200; + assign n6307 = Ng2741 | n8196; + assign n6308 = n8200 | Ng2741 | Ng2756; + assign n6309 = n8200 | Ng2756 | ~Ng2741; + assign n6310_1 = n8195 | ~n8206; + assign n6311 = n6126 ^ Ng4983; + assign n6312 = ~Pg35 | n6317; + assign n6313 = (n5907 | ~n8252) & (~Pg35 | n5888); + assign n6314 = (n6312 | ~Ng4899) & (n6313 | n8251); + assign n6315_1 = (Pg35 | ~Ng4991) & (n6312 | ~Ng4966); + assign n6316 = n6126 | ~Ng4983; + assign n6317 = n8251 | n8252; + assign n6318 = n6316 | Ng4991 | n6317; + assign n6319 = ~Ng4991 | n6312 | ~n6316; + assign n6320_1 = ~n8252 | Ng4975 | n8251; + assign n6321 = Pg35 | ~Ng4966; + assign n6322 = n8065 ^ Ng4793; + assign n6323 = ~Pg35 | n6328; + assign n6324 = (~Pg35 | n5939) & (n5874_1 | ~n8254); + assign n6325 = (n6323 | ~Ng4709) & (n6324 | n8253); + assign n6326 = (Pg35 | ~Ng4801) & (n6323 | ~Ng4776); + assign n6327 = n8065 | ~Ng4793; + assign n6328 = n8253 | n8254; + assign n6329 = n6327 | Ng4801 | n6328; + assign n6330_1 = ~Ng4801 | n6323 | ~n6327; + assign n6331 = ~n8254 | Ng4785 | n8253; + assign n6332 = Pg35 | ~Ng4776; + assign n6333 = ~Pg35 | Ng2841; + assign n6334 = n9223 & (~Pg35 | ~Ng2763 | ~n6335_1); + assign n6335_1 = ~Ng2759 | n6542; + assign n6336 = ~Ng2689 | ~Ng2697 | ~Ng2704; + assign n6337 = (~n6000 | n8261) & (~n8262 | ~Ng2567); + assign n6338 = ~n5923 & (~n5999 | Ng1589); + assign n6339 = (Pg35 & ~n8648) | (~Ng2629 & (~Pg35 | ~n8648)); + assign n6340_1 = ~Pg35 | n8263; + assign n6341 = Pg35 | ~Ng2571; + assign n6342 = ~Pg35 | ~n6343 | ~Ng2583; + assign n6343 = n8066 | ~n8263; + assign n6344 = Pg35 | ~Ng2583; + assign n6345 = ~Pg35 | ~Ng2579 | n8265; + assign n6346 = Pg35 | ~Ng2579; + assign n6347 = ~Pg35 | ~n6348 | ~Ng2575; + assign n6348 = ~Ng2629 | n8266; + assign n6349_1 = Pg35 | ~Ng2563; + assign n6350 = ~Pg35 | ~n6351 | ~Ng2571; + assign n6351 = ~n8263 | ~Ng2599 | Ng2629; + assign n6352 = Pg35 | ~Ng2567; + assign n6353 = ~Pg35 | ~n6354_1 | ~Ng2563; + assign n6354_1 = Ng2599 | n8266; + assign n6355 = ~Ng2689 | ~Ng2697 | Ng2704; + assign n6356 = (~n6002 | n8268) & (~n8269 | ~Ng2433); + assign n6357 = ~n5942 & (~n6001 | ~Ng1589); + assign n6358 = (Pg35 & ~n8650) | (~Ng2495 & (~Pg35 | ~n8650)); + assign n6359_1 = ~Pg35 | n8270; + assign n6360 = Pg35 | ~Ng2437; + assign n6361 = n8068 | ~n8270; + assign n6362 = Pg35 | ~Ng2449; + assign n6363 = ~Pg35 | ~Ng2445 | n8272; + assign n6364 = Pg35 | ~Ng2445; + assign n6365 = ~Pg35 | ~n6366 | ~Ng2441; + assign n6366 = ~Ng2495 | n8273; + assign n6367 = Pg35 | ~Ng2429; + assign n6368 = ~Pg35 | ~n6369_1 | ~Ng2437; + assign n6369_1 = ~n8270 | ~Ng2465 | Ng2495; + assign n6370 = Pg35 | ~Ng2433; + assign n6371 = ~Pg35 | ~n6372 | ~Ng2429; + assign n6372 = Ng2465 | n8273; + assign n6373_1 = ~Ng2704 | ~Ng2689 | Ng2697; + assign n6374 = (~n6012_1 | n8275) & (~n8276 | ~Ng2299); + assign n6375 = ~n5956_1 & (~n6011 | Ng1589); + assign n6376_1 = (Pg35 & ~n8652) | (~Ng2361 & (~Pg35 | ~n8652)); + assign n6377 = ~Pg35 | n8277; + assign n6378 = Pg35 | ~Ng2303; + assign n6379 = n8070 | ~n8277; + assign n6380_1 = Pg35 | ~Ng2315; + assign n6381 = ~Pg35 | ~Ng2311 | n8279; + assign n6382 = Pg35 | ~Ng2311; + assign n6383 = ~Pg35 | ~n6384 | ~Ng2307; + assign n6384 = ~Ng2361 | n8280; + assign n6385_1 = Pg35 | ~Ng2295; + assign n6386 = ~Pg35 | ~n6387 | ~Ng2303; + assign n6387 = ~n8277 | ~Ng2331 | Ng2361; + assign n6388 = Pg35 | ~Ng2299; + assign n6389 = ~Pg35 | ~n6390_1 | ~Ng2295; + assign n6390_1 = Ng2331 | n8280; + assign n6391 = Ng2704 | ~Ng2689 | Ng2697; + assign n6392 = (~n6008_1 | n8282) & (~n8283 | ~Ng2165); + assign n6393 = ~n5953 & (~n6007 | ~Ng1589); + assign n6394 = (Pg35 & ~n8654) | (~Ng2227 & (~Pg35 | ~n8654)); + assign n6395_1 = ~Pg35 | n8284; + assign n6396 = Pg35 | ~Ng2169; + assign n6397 = ~Pg35 | ~n6398 | ~Ng2181; + assign n6398 = Ng2197 | n8285; + assign n6399_1 = Pg35 | ~Ng2181; + assign n6400 = ~Pg35 | ~Ng2177 | n8287; + assign n6401 = Pg35 | ~Ng2177; + assign n6402 = ~Pg35 | ~n6403_1 | ~Ng2173; + assign n6403_1 = n8285 | ~Ng2153; + assign n6404 = Pg35 | ~Ng2161; + assign n6405 = ~Pg35 | ~n6406 | ~Ng2169; + assign n6406 = ~n8284 | ~Ng2197 | Ng2227; + assign n6407 = Pg35 | ~Ng2165; + assign n6408 = ~Pg35 | ~n6409 | ~Ng2161; + assign n6409 = ~Ng2153 | Ng2197 | ~n8284; + assign n6410 = ~Ng2130 | ~Ng2138 | ~Ng2145; + assign n6411 = (~n6004 | n8290) & (~n8291 | ~Ng2008); + assign n6412 = ~n5944 & (~n6003 | Ng1246); + assign n6413_1 = (Pg35 & ~n8656) | (~Ng2070 & (~Pg35 | ~n8656)); + assign n6414 = ~Pg35 | n8292; + assign n6415 = Pg35 | ~Ng2012; + assign n6416 = ~Pg35 | ~n6417_1 | ~Ng2024; + assign n6417_1 = Ng2040 | n8293; + assign n6418 = Pg35 | ~Ng2024; + assign n6419 = ~Pg35 | ~Ng2020 | n8295; + assign n6420 = Pg35 | ~Ng2020; + assign n6421 = ~Pg35 | ~n6422_1 | ~Ng2016; + assign n6422_1 = n8293 | ~Ng1996; + assign n6423 = Pg35 | ~Ng2004; + assign n6424 = ~Pg35 | ~n6425 | ~Ng2012; + assign n6425 = ~n8292 | ~Ng2040 | Ng2070; + assign n6426 = Pg35 | ~Ng2008; + assign n6427_1 = ~Pg35 | ~n6428 | ~Ng2004; + assign n6428 = ~Ng1996 | Ng2040 | ~n8292; + assign n6429 = ~Ng2130 | ~Ng2138 | Ng2145; + assign n6430 = (~n6006 | n8297) & (~n8298 | ~Ng1874); + assign n6431 = ~n5948 & (~n6005 | ~Ng1246); + assign n6432_1 = (Pg35 & ~n8658) | (~Ng1936 & (~Pg35 | ~n8658)); + assign n6433 = ~Pg35 | n8299; + assign n6434 = Pg35 | ~Ng1878; + assign n6435 = ~Pg35 | ~n6436 | ~Ng1890; + assign n6436 = Ng1906 | n8300; + assign n6437_1 = Pg35 | ~Ng1890; + assign n6438 = ~Pg35 | ~Ng1886 | n8302; + assign n6439 = Pg35 | ~Ng1886; + assign n6440 = ~Pg35 | ~n6441 | ~Ng1882; + assign n6441 = n8300 | ~Ng1862; + assign n6442_1 = Pg35 | ~Ng1870; + assign n6443 = ~Pg35 | ~n6444 | ~Ng1878; + assign n6444 = ~n8299 | ~Ng1906 | Ng1936; + assign n6445 = Pg35 | ~Ng1874; + assign n6446 = ~Pg35 | ~n6447_1 | ~Ng1870; + assign n6447_1 = ~Ng1862 | Ng1906 | ~n8299; + assign n6448 = ~Ng2145 | ~Ng2130 | Ng2138; + assign n6449 = (~n5998_1 | n8304) & (~n8305 | ~Ng1740); + assign n6450 = ~n5898_1 & (~n5997 | Ng1246); + assign n6451 = (Pg35 & ~n8660) | (~Ng1802 & (~Pg35 | ~n8660)); + assign n6452_1 = ~Pg35 | n8306; + assign n6453 = Pg35 | ~Ng1744; + assign n6454 = n8078 | ~n8306; + assign n6455 = Pg35 | ~Ng1756; + assign n6456 = ~Pg35 | ~Ng1752 | n8308; + assign n6457_1 = Pg35 | ~Ng1752; + assign n6458 = ~Pg35 | ~n6459 | ~Ng1748; + assign n6459 = ~Ng1802 | n8309; + assign n6460 = Pg35 | ~Ng1736; + assign n6461 = ~Pg35 | ~n6462_1 | ~Ng1744; + assign n6462_1 = ~n8306 | ~Ng1772 | Ng1802; + assign n6463 = Pg35 | ~Ng1740; + assign n6464 = ~Pg35 | ~n6465 | ~Ng1736; + assign n6465 = Ng1772 | n8309; + assign n6466 = Ng2145 | ~Ng2130 | Ng2138; + assign n6467_1 = (~n6010 | n8311) & (~n8312 | ~Ng1604); + assign n6468 = ~n5954 & (~n6009 | ~Ng1246); + assign n6469 = (Pg35 & ~n8662) | (~Ng1668 & (~Pg35 | ~n8662)); + assign n6470 = ~Pg35 | n8313; + assign n6471 = Pg35 | ~Ng1608; + assign n6472_1 = ~Pg35 | ~n6473 | ~Ng1620; + assign n6473 = n8080 | ~n8313; + assign n6474 = Pg35 | ~Ng1620; + assign n6475 = ~Pg35 | ~n6476 | ~Ng1616; + assign n6476 = Ng1592 | n8314; + assign n6477_1 = Pg35 | ~Ng1616; + assign n6478 = ~Pg35 | ~n6479 | ~Ng1612; + assign n6479 = ~Ng1668 | n8315; + assign n6480 = Pg35 | ~Ng1600; + assign n6481 = ~Pg35 | ~n6482_1 | ~Ng1608; + assign n6482_1 = Ng1668 | n8314; + assign n6483 = Pg35 | ~Ng1604; + assign n6484 = ~Pg35 | ~n6485 | ~Ng1600; + assign n6485 = Ng1636 | n8315; + assign n6486 = ~Ng767 | ~n6488 | n7743; + assign n6487_1 = Pg35 | ~Ng763; + assign n6488 = ~Ng763 | n6647; + assign n6489 = Pg35 | ~Ng595; + assign n6490 = ~Ng595 | n6649; + assign n6491 = Ng298 | n8244; + assign n6492_1 = ~n8244 | n7834 | ~Ng298; + assign n6493 = Ng157 | n8250; + assign n6494 = ~n8250 | n7402 | ~Ng157; + assign n6495 = (~Pg35 | n7426) & (n6500 | ~Ng6682); + assign n6496 = ~Ng6741 | Ng6682; + assign n6497_1 = n6495 & (~n5884_1 | n6496); + assign n6498 = Pg35 | ~Ng6736; + assign n6499 = ~Pg35 | ~n5884_1 | Ng6741 | ~n9420; + assign n6500 = ~Pg35 | n5884_1; + assign n6501 = (~Pg35 | n7454) & (n6506 | ~Ng6336); + assign n6502_1 = ~Ng6395 | Ng6336; + assign n6503 = n6501 & (~n5952 | n6502_1); + assign n6504 = Pg35 | ~Ng6390; + assign n6505 = ~Pg35 | ~n5952 | Ng6395 | ~n9421; + assign n6506 = ~Pg35 | n5952; + assign n6507_1 = (~Pg35 | n7488) & (n6512_1 | ~Ng5990); + assign n6508 = ~Ng6049 | Ng5990; + assign n6509 = n6507_1 & (~n5940 | n6508); + assign n6510 = Pg35 | ~Ng6044; + assign n6511 = ~Pg35 | ~n5940 | Ng6049 | ~n9423; + assign n6512_1 = ~Pg35 | n5940; + assign n6513 = n7791 | ~Ng5703; + assign n6514 = ~n9224 | Ng5703 | n8322; + assign n6515 = (~Pg35 | n7548) & (n6520 | ~Ng5297); + assign n6516 = ~Ng5357 | Ng5297; + assign n6517_1 = n6515 & (~n4151_1 | n6516); + assign n6518 = Pg35 | ~Ng5352; + assign n6519 = ~Pg35 | ~n4151_1 | Ng5357 | ~n9422; + assign n6520 = ~Pg35 | n4151_1; + assign n6521 = ~Pg35 | Ng2841; + assign n6522_1 = n9226 & (~Pg35 | ~Ng4104 | ~n6523); + assign n6523 = ~Ng4108 | n6712; + assign n6524 = (~Pg35 | n7590) & (n6529 | ~Ng3990); + assign n6525 = ~Ng4054 | Ng3990; + assign n6526_1 = n6524 & (~n5927 | n6525); + assign n6527 = Pg35 | ~Ng4049; + assign n6528 = ~Pg35 | ~n5927 | Ng4054 | ~n9419; + assign n6529 = ~Pg35 | n5927; + assign n6530 = (~Pg35 | n8327) & (n6535 | ~Ng3639); + assign n6531_1 = ~Ng3703 | Ng3639; + assign n6532 = n6530 & (~n5889 | n6531_1); + assign n6533 = Pg35 | ~Ng3698; + assign n6534 = ~Pg35 | ~n5889 | Ng3703 | ~n9424; + assign n6535 = ~Pg35 | n5889; + assign n6536_1 = (n7775 | ~Ng3288) & (~Pg35 | n7638); + assign n6537 = ~Ng3352 | Ng3288; + assign n6538 = n6536_1 & (~n5908 | n6537); + assign n6539 = n7775 | ~Ng3352; + assign n6540 = ~n9425 | Ng3352 | n8328; + assign n6541_1 = n9227 & (~Pg35 | ~Ng2759 | ~n6542); + assign n6542 = ~Ng2756 | n8258; + assign n6543 = ~Pg35 | n5966; + assign n6544 = n6543 & (~Pg35 | (n5911 & ~n6273)); + assign n6545 = Pg35 | ~Ng2555; + assign n6546_1 = Pg35 | ~Ng2671; + assign n6547 = Ng2675 | ~Pg35 | n8261; + assign n6548 = (~Ng2671 | ~n8262) & (n8261 | ~n8680); + assign n6549 = ~n6273 & n8330; + assign n6550 = Pg35 & (n6549 | ~n8263); + assign n6551_1 = n8266 | ~Pg35 | n6549; + assign n6552 = Pg35 | ~Ng2606; + assign n6553 = ~Ng2555 & (Ng2599 | ~n8263); + assign n6554 = ~Pg35 | n6549 | n6553 | Ng2629; + assign n6555_1 = n6543 & (~Pg35 | (n5872 & ~n6269)); + assign n6556 = Pg35 | ~Ng2421; + assign n6557 = Pg35 | ~Ng2537; + assign n6558 = Ng2541 | ~Pg35 | n8268; + assign n6559 = (~Ng2537 | ~n8269) & (n8268 | ~n8685); + assign n6560_1 = ~n6269 & n8330; + assign n6561 = Pg35 & (n6560_1 | ~n8270); + assign n6562 = n8273 | ~Pg35 | n6560_1; + assign n6563 = Pg35 | ~Ng2472; + assign n6564 = ~Ng2421 & (Ng2465 | ~n8270); + assign n6565_1 = ~Pg35 | n6560_1 | n6564 | Ng2495; + assign n6566 = n6543 & (~Pg35 | (n5910 & ~n6270_1)); + assign n6567 = Pg35 | ~Ng2287; + assign n6568 = Pg35 | ~Ng2403; + assign n6569 = Ng2407 | ~Pg35 | n8275; + assign n6570_1 = (~Ng2403 | ~n8276) & (n8275 | ~n8690); + assign n6571 = ~n6270_1 & n8330; + assign n6572 = Pg35 & (n6571 | ~n8277); + assign n6573 = n8280 | ~Pg35 | n6571; + assign n6574 = Pg35 | ~Ng2338; + assign n6575_1 = ~Ng2287 & (Ng2331 | ~n8277); + assign n6576 = ~Pg35 | n6571 | n6575_1 | Ng2361; + assign n6577 = n6543 & (~Pg35 | (n5873 & ~n6271)); + assign n6578 = Pg35 | ~Ng2153; + assign n6579 = Pg35 | ~Ng2269; + assign n6580_1 = Ng2273 | ~Pg35 | n8282; + assign n6581 = (~Ng2269 | ~n8283) & (n8282 | ~n8695); + assign n6582 = ~n6271 & n8330; + assign n6583 = Pg35 & (n6582 | ~n8284); + assign n6584 = ~Pg35 | n6582 | ~n8284 | ~Ng2153; + assign n6585_1 = Pg35 | ~Ng2204; + assign n6586 = ~Ng2153 & (Ng2197 | ~n8284); + assign n6587 = ~Pg35 | n6582 | n6586 | Ng2227; + assign n6588 = n6543 & (~Pg35 | (n5921 & ~n6267)); + assign n6589 = Pg35 | ~Ng1996; + assign n6590_1 = Pg35 | ~Ng2112; + assign n6591 = Ng2116 | ~Pg35 | n8290; + assign n6592 = (~Ng2112 | ~n8291) & (n8290 | ~n8700); + assign n6593 = ~n6267 & n8330; + assign n6594 = Pg35 & (n6593 | ~n8292); + assign n6595_1 = ~Pg35 | n6593 | ~n8292 | ~Ng1996; + assign n6596 = Pg35 | ~Ng2047; + assign n6597 = ~Ng1996 & (Ng2040 | ~n8292); + assign n6598 = ~Pg35 | n6593 | n6597 | Ng2070; + assign n6599 = n6543 & (~Pg35 | (n5887 & ~n6272)); + assign n6600_1 = Pg35 | ~Ng1862; + assign n6601 = Pg35 | ~Ng1978; + assign n6602 = Ng1982 | ~Pg35 | n8297; + assign n6603 = (~Ng1978 | ~n8298) & (n8297 | ~n8705); + assign n6604 = ~n6272 & n8330; + assign n6605_1 = Pg35 & (n6604 | ~n8299); + assign n6606 = ~Pg35 | n6604 | ~n8299 | ~Ng1862; + assign n6607 = Pg35 | ~Ng1913; + assign n6608 = ~Ng1862 & (Ng1906 | ~n8299); + assign n6609 = ~Pg35 | n6604 | n6608 | Ng1936; + assign n6610_1 = n6543 & (~Pg35 | (n5894 & ~n6266)); + assign n6611 = Pg35 | ~Ng1728; + assign n6612 = Pg35 | ~Ng1844; + assign n6613 = Ng1848 | ~Pg35 | n8304; + assign n6614 = (~Ng1844 | ~n8305) & (n8304 | ~n8710); + assign n6615_1 = ~n6266 & n8330; + assign n6616 = Pg35 & (n6615_1 | ~n8306); + assign n6617 = n8309 | ~Pg35 | n6615_1; + assign n6618 = Pg35 | ~Ng1779; + assign n6619 = ~Ng1728 & (Ng1772 | ~n8306); + assign n6620_1 = ~Pg35 | n6615_1 | n6619 | Ng1802; + assign n6621 = n6543 & (~Pg35 | (n4162 & ~n6268)); + assign n6622 = Pg35 | ~Ng1592; + assign n6623 = Pg35 | ~Ng1710; + assign n6624_1 = Ng1714 | ~Pg35 | n8311; + assign n6625 = (~Ng1710 | ~n8312) & (n8311 | ~n8715); + assign n6626 = (n6470 | ~Ng1668) & (n8314 | n9114); + assign n6627 = n9114 | ~Pg35 | n8315; + assign n6628 = Pg35 | ~Ng1644; + assign n6629_1 = ~Ng1592 & (Ng1636 | ~n8313); + assign n6630 = ~Pg35 | n6629_1 | Ng1668 | n9114; + assign n6631 = Ng1333 | Ng1322; + assign n6632 = n6631 & (Ng1345 | ~n8333); + assign n6633 = n6632 & (Ng1361 | ~n8333); + assign n6634_1 = n6633 & (Ng1367 | ~n8333); + assign n6635 = Pg35 & (~n6634_1 | Ng1379 | ~n8333); + assign n6636 = n8005 | ~Ng1274 | n5090; + assign n6637 = Pg35 | ~Ng1270; + assign n6638_1 = Ng990 | Ng979; + assign n6639 = n6638_1 & (Ng1002 | ~n8339); + assign n6640 = n6639 & (Ng1018 | ~n8339); + assign n6641 = n6640 & (Ng1024 | ~n8339); + assign n6642_1 = Pg35 & (~n6641 | Ng1036 | ~n8339); + assign n6643 = n8014 | ~Ng930 | n5097; + assign n6644 = Pg35 | ~Ng925; + assign n6645 = ~Ng763 | ~n6647 | n7743; + assign n6646_1 = Pg35 | ~Ng758; + assign n6647 = ~Ng758 | n6837; + assign n6648 = Pg35 | ~Ng590; + assign n6649 = ~Ng590 | n6839; + assign n6650 = Ng294 | n8243; + assign n6651_1 = ~n8243 | n7834 | ~Ng294; + assign n6652 = Ng153 | n8249; + assign n6653 = ~n8249 | n7402 | ~Ng153; + assign n6654 = ~Ng6561 | n8346; + assign n6655 = n6654 & (~n4287_1 | (Ng6561 & Ng6565)); + assign n6656_1 = n7942 & n8344; + assign n6657 = Pg35 & (Ng6565 | n6656_1); + assign n6658 = n6656_1 | ~Pg35 | Ng6561; + assign n6659 = ~Ng6555 | ~Ng6549; + assign n6660 = Ng6555 | ~Ng6549; + assign n6661_1 = ~Ng6555 | Ng6549; + assign n6662 = n6660 & (~Pg35 | n6661_1); + assign n6663 = ~Ng6215 | n8348; + assign n6664 = ~Pg35 | ~Ng6227; + assign n6665_1 = n6663 & (n6664 | (Ng6215 & Ng6219)); + assign n6666 = n8218 & n8347; + assign n6667 = Pg35 & (Ng6219 | n6666); + assign n6668 = n6666 | ~Pg35 | Ng6215; + assign n6669 = ~Ng6203 | ~Ng6209; + assign n6670_1 = ~Ng6203 | Ng6209; + assign n6671 = Ng6203 | ~Ng6209; + assign n6672 = n6670_1 & (~Pg35 | n6671); + assign n6673 = ~Ng5869 | n8350; + assign n6674 = n6673 & (~n1064_1 | (Ng5869 & Ng5873)); + assign n6675_1 = n8218 & n8344; + assign n6676 = Pg35 & (Ng5873 | n6675_1); + assign n6677 = n6675_1 | ~Pg35 | Ng5869; + assign n6678 = ~Ng5863 | ~Ng5857; + assign n6679 = Ng5863 | ~Ng5857; + assign n6680_1 = ~Ng5863 | Ng5857; + assign n6681 = n6679 & (~Pg35 | n6680_1); + assign n6682 = ~Ng5523 | n8351; + assign n6683 = ~Pg35 | ~Ng5535; + assign n6684 = n6682 & (n6683 | (Ng5523 & Ng5527)); + assign n6685 = ~n6261 & n8347; + assign n6686 = Pg35 & (Ng5527 | n6685); + assign n6687 = n6685 | ~Pg35 | Ng5523; + assign n6688 = ~Ng5517 | ~Ng5511; + assign n6689 = Ng5517 | ~Ng5511; + assign n6690 = ~Ng5517 | Ng5511; + assign n6691 = n6689 & (~Pg35 | n6690); + assign n6692 = ~Ng5176 | n8352; + assign n6693 = ~Pg35 | ~Ng5188; + assign n6694 = n6692 & (n6693 | (Ng5176 & Ng5180)); + assign n6695 = ~n6261 & n8344; + assign n6696 = Pg35 & (Ng5180 | n6695); + assign n6697 = n6695 | ~Pg35 | Ng5176; + assign n6698 = ~Ng5170 | ~Ng5164; + assign n6699 = Ng5170 | ~Ng5164; + assign n6700 = ~Ng5170 | Ng5164; + assign n6701 = n6699 & (~Pg35 | n6700); + assign n6702 = n9230 | ~Pg35 | Ng5057; + assign n6703 = ~n9230 | n6855 | ~Ng5057; + assign n6704 = (n6860 & ~Ng4549) | (~n5967 & (~n6860 | ~Ng4549)); + assign n6705 = ~n5993 & n6704; + assign n6706 = n6860 | ~Ng4575; + assign n6707 = (n6860 & ~Ng4504) | (~n5967 & (~n6860 | ~Ng4504)); + assign n6708 = n6860 | ~Ng4572; + assign n6709 = n6707 & n6708; + assign n6710 = ~\[4437] | n6860; + assign n6711 = n9231 & (~Pg35 | ~Ng4108 | ~n6712); + assign n6712 = ~Ng4098 | n8326; + assign n6713 = ~Ng3869 | n8365; + assign n6714 = ~Pg35 | ~Ng3881; + assign n6715 = n6713 & (n6714 | (Ng3869 & Ng3873)); + assign n6716 = n8220 & n8347; + assign n6717 = Pg35 & (Ng3873 | n6716); + assign n6718 = n6716 | ~Pg35 | Ng3869; + assign n6719 = ~Ng3857 | ~Ng3863; + assign n6720 = ~Ng3857 | Ng3863; + assign n6721 = Ng3857 | ~Ng3863; + assign n6722 = n6720 & (~Pg35 | n6721); + assign n6723 = ~Ng3518 | n8366; + assign n6724 = ~Pg35 | ~Ng3530; + assign n6725 = n6723 & (n6724 | (Ng3518 & Ng3522)); + assign n6726 = n8220 & n8344; + assign n6727 = Pg35 & (Ng3522 | n6726); + assign n6728 = n6726 | ~Pg35 | Ng3518; + assign n6729 = ~Ng3512 | ~Ng3506; + assign n6730 = Ng3512 | ~Ng3506; + assign n6731 = ~Ng3512 | Ng3506; + assign n6732 = n6730 & (~Pg35 | n6731); + assign n6733 = ~Ng3167 | n8367; + assign n6734 = ~Pg35 | ~Ng3179; + assign n6735 = n6733 & (n6734 | (Ng3167 & Ng3171)); + assign n6736 = n7942 & n8347; + assign n6737 = Pg35 & (Ng3171 | n6736); + assign n6738 = n6736 | ~Pg35 | Ng3167; + assign n6739 = ~Ng3161 | ~Ng3155; + assign n6740 = Ng3161 | ~Ng3155; + assign n6741 = ~Ng3161 | Ng3155; + assign n6742 = n6740 & (~Pg35 | n6741); + assign n6743 = Pg35 | ~Ng2748; + assign n6744 = n8258 ^ Ng2756; + assign n6745 = ~Pg35 | n5920; + assign n6746 = n6543 & (~Pg35 | ~n6306) & n6745; + assign n6747 = n8085 | ~n8329 | ~n5920 | n6306; + assign n6748 = Pg35 | ~Ng2610; + assign n6749 = n8369 | n6306 | ~n8368; + assign n6750 = (Pg35 | ~Ng2625) & (~Ng2610 | n8369); + assign n6751 = (n6745 & ~Ng2587) | (~Ng2610 & (~n6745 | ~Ng2587)); + assign n6752 = n6751 & n6749; + assign n6753 = ~n8415 | Ng2619 | n8369; + assign n6754 = (Pg35 | ~Ng2595) & (n6745 | ~Ng2587); + assign n6755 = ~Pg35 | n5919; + assign n6756 = n6543 & (~Pg35 | ~n6303) & n6755; + assign n6757 = n8087 | ~n8329 | ~n5919 | n6303; + assign n6758 = Pg35 | ~Ng2476; + assign n6759 = n8371 | n6303 | ~n8368; + assign n6760 = (Pg35 | ~Ng2491) & (~Ng2476 | n8371); + assign n6761 = (n6755 & ~Ng2453) | (~Ng2476 & (~n6755 | ~Ng2453)); + assign n6762 = n6761 & n6759; + assign n6763 = ~Pg35 | ~Ng2453 | n8416; + assign n6764 = n6759 & (Ng2485 | Ng2476 | n8371); + assign n6765 = ~Pg35 | n5925; + assign n6766 = n6543 & (~Pg35 | ~n6305) & n6765; + assign n6767 = n8089 | ~n8329 | ~n5925 | n6305; + assign n6768 = Pg35 | ~Ng2342; + assign n6769 = n8372 | n6305 | ~n8368; + assign n6770 = (Pg35 | ~Ng2357) & (~Ng2342 | n8372); + assign n6771 = (n6765 & ~Ng2319) | (~Ng2342 & (~n6765 | ~Ng2319)); + assign n6772 = n6771 & n6769; + assign n6773 = ~n8422 | Ng2351 | n8372; + assign n6774 = (Pg35 | ~Ng2327) & (n6765 | ~Ng2319); + assign n6775 = ~Pg35 | n5878; + assign n6776 = n6543 & (~Pg35 | ~n6307) & n6775; + assign n6777 = n8091 | ~n8329 | ~n5878 | n6307; + assign n6778 = Pg35 | ~Ng2208; + assign n6779 = n8374 | n6307 | ~n8368; + assign n6780 = (Pg35 | ~Ng2223) & (~Ng2208 | n8374); + assign n6781 = (n6775 & ~Ng2185) | (~Ng2208 & (~n6775 | ~Ng2185)); + assign n6782 = n6781 & n6779; + assign n6783 = ~n8425 | Ng2217 | n8374; + assign n6784 = (Pg35 | ~Ng2193) & (n6775 | ~Ng2185); + assign n6785 = ~Pg35 | n5916; + assign n6786 = n6543 & (~Pg35 | ~n6309) & n6785; + assign n6787 = n8093 | ~n8329 | ~n5916 | n6309; + assign n6788 = Pg35 | ~Ng2051; + assign n6789 = n8375 | n6309 | ~n8368; + assign n6790 = (Pg35 | ~Ng2066) & (~Ng2051 | n8375); + assign n6791 = (n6785 & ~Ng2028) | (~Ng2051 & (~n6785 | ~Ng2028)); + assign n6792 = n6791 & n6789; + assign n6793 = ~Pg35 | ~Ng2028 | n8426; + assign n6794 = n6789 & (Ng2051 | Ng2060 | n8375); + assign n6795 = ~Pg35 | n5899; + assign n6796 = n6543 & (~Pg35 | ~n6308) & n6795; + assign n6797 = n8095 | ~n8329 | ~n5899 | n6308; + assign n6798 = Pg35 | ~Ng1917; + assign n6799 = n8376 | n6308 | ~n8368; + assign n6800 = (Pg35 | ~Ng1932) & (~Ng1917 | n8376); + assign n6801 = (n6795 & ~Ng1894) | (~Ng1917 & (~n6795 | ~Ng1894)); + assign n6802 = n6801 & n6799; + assign n6803 = ~n8432 | Ng1926 | n8376; + assign n6804 = (Pg35 | ~Ng1902) & (n6795 | ~Ng1894); + assign n6805 = ~Pg35 | n5941; + assign n6806 = n6543 & (~Pg35 | ~n6304) & n6805; + assign n6807 = n8097 | ~n8329 | ~n5941 | n6304; + assign n6808 = Pg35 | ~Ng1783; + assign n6809 = n8377 | n6304 | ~n8368; + assign n6810 = (Pg35 | ~Ng1798) & (~Ng1783 | n8377); + assign n6811 = (n6805 & ~Ng1760) | (~Ng1783 & (~n6805 | ~Ng1760)); + assign n6812 = n6811 & n6809; + assign n6813 = ~n8435 | Ng1792 | n8377; + assign n6814 = (Pg35 | ~Ng1768) & (n6805 | ~Ng1760); + assign n6815 = ~Pg35 | n5868; + assign n6816 = n6543 & (~Pg35 | ~n6310_1) & n6815; + assign n6817 = n8099 | ~n8329 | ~n5868 | n6310_1; + assign n6818 = Pg35 | ~Ng1648; + assign n6819 = n8378 | n6310_1 | ~n8368; + assign n6820 = (Pg35 | ~Ng1664) & (~Ng1648 | n8378); + assign n6821 = (n6815 & ~Ng1624) | (~Ng1648 & (~n6815 | ~Ng1624)); + assign n6822 = n6821 & n6819; + assign n6823 = ~n8438 | Ng1657 | n8378; + assign n6824 = (Pg35 | ~Ng1632) & (n6815 | ~Ng1624); + assign n6825 = ~Ng1373 | ~Pg35 | n6634_1; + assign n6826 = Ng1373 | ~n6634_1 | n7814; + assign n6827 = ~Ng1270 | ~n6829 | n8005; + assign n6828 = Pg35 | ~Ng1263; + assign n6829 = ~Ng1263 | ~n8336; + assign n6830 = ~Ng1030 | ~Pg35 | n6641; + assign n6831 = Ng1030 | ~n6641 | n7819; + assign n6832 = ~Ng925 | ~n6834 | n8014; + assign n6833 = Pg35 | ~Ng918; + assign n6834 = ~Ng918 | ~n8342; + assign n6835 = ~Ng758 | ~n6837 | n7743; + assign n6836 = Pg35 | ~Ng749; + assign n6837 = ~Ng749 | n6876; + assign n6838 = Pg35 | ~Ng582; + assign n6839 = ~Ng582 | n6879; + assign n6840 = ~n8242 | Ng291; + assign n6841 = ~Ng291 | n7834 | n8242; + assign n6842 = ~n8248 | Ng150; + assign n6843 = ~Ng150 | n7402 | n8248; + assign n6844 = (~Ng2950 | ~Ng2955) & (~Ng2927 | ~Ng2922); + assign n6845 = ~Ng2936 | ~Ng2941; + assign n6846 = (~Ng2975 | ~Ng2970) & (~Ng2902 | ~Ng2907); + assign n6847 = (~Ng2965 | ~Ng2960) & (~Ng2917 | ~Ng2912); + assign n6848 = n6855 | ~n8353 | ~Ng5033 | ~n8355; + assign n6849 = n6855 | ~Ng5052 | ~n8357 | ~n9229; + assign n6850 = n8364 | ~Ng5029 | Ng5062; + assign n6851 = Pg35 & n6850 & (Ng5029 | ~Ng5062); + assign n6852 = ~Ng5029 | n6855 | Ng5016 | Ng5022; + assign n6853 = ~Pg35 | n8355; + assign n6854 = n9234 & (~Pg35 | Ng5046 | n8722); + assign n6855 = ~Pg35 | n8364; + assign n6856 = n9235 & (~Pg35 | Ng5041 | n8379); + assign n6857 = n9236 & (~Pg35 | Ng5037 | n8723); + assign n6858 = n9237 & (~Pg35 | ~Ng5016 | n8380); + assign n6859 = ~Ng4372 | ~Pg35 | Ng4581; + assign n6860 = ~Pg35 | ~Ng4581; + assign n6861 = n6859 & (n6860 | (Pg72 & Pg73)); + assign n6862 = Pg35 | ~Ng4093; + assign n6863 = n8326 ^ Ng4098; + assign n6864 = ~n8257 | ~Ng2748 | n7336; + assign n6865 = ~Ng2841 | Ng2748 | n8257; + assign n6866 = ~Ng1367 | ~Pg35 | n6633; + assign n6867 = n7814 | ~n6633 | Ng1367; + assign n6868 = n8336 | ~Ng1263 | n8005; + assign n6869 = Pg35 | ~Ng1259; + assign n6870 = ~Ng1024 | ~Pg35 | n6640; + assign n6871 = n7819 | ~n6640 | Ng1024; + assign n6872 = n8342 | ~Ng918 | n8014; + assign n6873 = Pg35 | ~Ng914; + assign n6874 = ~Ng749 | ~n6876 | n7743; + assign n6875 = Pg35 | ~Ng744; + assign n6876 = ~Ng744 | n7397; + assign n6877 = ~Ng582 | ~n6879 | n8183; + assign n6878 = Pg35 | ~Ng577; + assign n6879 = ~Ng577 | n7400; + assign n6880 = Ng164 | ~n8247; + assign n6881 = n8247 | n7402 | ~Ng164; + assign n6882 = (~n5880 | ~n8105) & ~n8213; + assign n6883 = n6885 | n6886; + assign n6884 = Pg35 & Ng5817; + assign n6885 = Pg35 & Ng5124; + assign n6886 = Pg35 & Ng6163; + assign n6887 = n6883 & (n6884 | (n6885 & n6886)); + assign n6888 = n8104 | n8101 | n8103 | n5880 | n8213 | n8105; + assign n6889 = Pg35 & Ng3817; + assign n6890 = Pg35 & Ng3115; + assign n6891 = (n4205 | n7404) & (~n8381 | ~Ng6657); + assign n6892 = Pg35 | ~Ng6649; + assign n6893 = ~Pg35 | ~n6894 | ~Ng6605; + assign n6894 = ~Ng6561 | n8383; + assign n6895 = Pg35 | ~Ng6645; + assign n6896 = Pg35 | ~Ng6641; + assign n6897 = ~Pg35 | ~n6898 | ~Ng6589; + assign n6898 = ~Ng6561 | n8384; + assign n6899 = Pg35 | ~Ng6637; + assign n6900 = n8222 | n6659; + assign n6901 = Pg35 | ~Ng6633; + assign n6902 = ~Pg35 | ~n6903 | ~Ng6649; + assign n6903 = n6659 | n8383; + assign n6904 = Pg35 | ~Ng6629; + assign n6905 = ~Pg35 | ~n6906 | ~Ng6645; + assign n6906 = n8346 | n6659; + assign n6907 = Pg35 | ~Ng6625; + assign n6908 = ~Pg35 | ~n6909 | ~Ng6641; + assign n6909 = n6659 | n8384; + assign n6910 = Pg35 | ~Ng6621; + assign n6911 = ~Pg35 | ~n6912 | ~Ng6637; + assign n6912 = n8222 | n6661_1; + assign n6913 = Pg35 | ~Ng6617; + assign n6914 = n6661_1 | n8383; + assign n6915 = Pg35 | ~Ng6613; + assign n6916 = ~Pg35 | ~n6917 | ~Ng6629; + assign n6917 = n8346 | n6661_1; + assign n6918 = Pg35 | ~Ng6609; + assign n6919 = ~Pg35 | ~n6920 | ~Ng6625; + assign n6920 = n6661_1 | n8384; + assign n6921 = Pg35 | ~Ng6601; + assign n6922 = ~Pg35 | ~n6923 | ~Ng6621; + assign n6923 = n8222 | n6660; + assign n6924 = Pg35 | ~Ng6593; + assign n6925 = ~Pg35 | ~n6926 | ~Ng6617; + assign n6926 = n8383 | n6660; + assign n6927 = Pg35 | ~Ng6585; + assign n6928 = ~Pg35 | ~n6929 | ~Ng6613; + assign n6929 = n8346 | n6660; + assign n6930 = Pg35 | ~Ng6581; + assign n6931 = ~Pg35 | ~n6932 | ~Ng6609; + assign n6932 = n8384 | n6660; + assign n6933 = Pg35 | ~Ng6605; + assign n6934 = ~Pg35 | ~n6935 | ~Ng6601; + assign n6935 = n8222 | n8385; + assign n6936 = Pg35 | ~Ng6597; + assign n6937 = ~Pg35 | ~n6938 | ~Ng6593; + assign n6938 = n8383 | n8385; + assign n6939 = Pg35 | ~Ng6589; + assign n6940 = ~Pg35 | ~n6941 | ~Ng6585; + assign n6941 = n8346 | n8385; + assign n6942 = Pg35 | ~Ng6573; + assign n6943 = ~Pg35 | ~n6944 | ~Ng6581; + assign n6944 = n8384 | n8385; + assign n6945 = (n4205 | n7435) & (~n8386 | ~Ng6311); + assign n6946 = Pg35 | ~Ng6303; + assign n6947 = ~Pg35 | ~n6948 | ~Ng6259; + assign n6948 = ~Ng6215 | n8387; + assign n6949 = Pg35 | ~Ng6299; + assign n6950 = ~Pg35 | ~n6663 | ~Ng6251; + assign n6951 = Pg35 | ~Ng6295; + assign n6952 = ~Pg35 | ~n6953 | ~Ng6243; + assign n6953 = ~Ng6215 | n8388; + assign n6954 = Pg35 | ~Ng6291; + assign n6955 = ~Pg35 | ~n6956 | ~Ng6307; + assign n6956 = n8217 | n6669; + assign n6957 = Pg35 | ~Ng6287; + assign n6958 = ~Pg35 | ~n6959 | ~Ng6303; + assign n6959 = n6669 | n8387; + assign n6960 = Pg35 | ~Ng6283; + assign n6961 = ~Pg35 | ~n6962 | ~Ng6299; + assign n6962 = n8348 | n6669; + assign n6963 = Pg35 | ~Ng6279; + assign n6964 = ~Pg35 | ~n6965 | ~Ng6295; + assign n6965 = n6669 | n8388; + assign n6966 = Pg35 | ~Ng6275; + assign n6967 = ~Pg35 | ~n6968 | ~Ng6291; + assign n6968 = n8217 | n6671; + assign n6969 = Pg35 | ~Ng6271; + assign n6970 = n6671 | n8387; + assign n6971 = Pg35 | ~Ng6267; + assign n6972 = n8348 | n6671; + assign n6973 = Pg35 | ~Ng6263; + assign n6974 = ~Pg35 | ~n6975 | ~Ng6279; + assign n6975 = n6671 | n8388; + assign n6976 = Pg35 | ~Ng6255; + assign n6977 = n8217 | n6670_1; + assign n6978 = Pg35 | ~Ng6247; + assign n6979 = ~Pg35 | ~n6980 | ~Ng6271; + assign n6980 = n8387 | n6670_1; + assign n6981 = Pg35 | ~Ng6239; + assign n6982 = ~Pg35 | ~n6983 | ~Ng6267; + assign n6983 = n8348 | n6670_1; + assign n6984 = Pg35 | ~Ng6235; + assign n6985 = ~Pg35 | ~n6986 | ~Ng6263; + assign n6986 = n8388 | n6670_1; + assign n6987 = Pg35 | ~Ng6259; + assign n6988 = ~Pg35 | ~n6989 | ~Ng6255; + assign n6989 = n8217 | n8389; + assign n6990 = Pg35 | ~Ng6251; + assign n6991 = ~Pg35 | ~n6992 | ~Ng6247; + assign n6992 = n8387 | n8389; + assign n6993 = Pg35 | ~Ng6243; + assign n6994 = ~Pg35 | ~n6995 | ~Ng6239; + assign n6995 = n8348 | n8389; + assign n6996 = Pg35 | ~Ng6227; + assign n6997 = ~Pg35 | ~n6998 | ~Ng6235; + assign n6998 = n8388 | n8389; + assign n6999 = (n4205 | n7466) & (~n8390 | ~Ng5965); + assign n7000 = Pg35 | ~Ng5957; + assign n7001 = ~Pg35 | ~n7002 | ~Ng5913; + assign n7002 = ~Ng5869 | n8391; + assign n7003 = Pg35 | ~Ng5953; + assign n7004 = Pg35 | ~Ng5949; + assign n7005 = ~Pg35 | ~n7006 | ~Ng5897; + assign n7006 = ~Ng5869 | n8392; + assign n7007 = Pg35 | ~Ng5945; + assign n7008 = n8223 | n6678; + assign n7009 = Pg35 | ~Ng5941; + assign n7010 = ~Pg35 | ~n7011 | ~Ng5957; + assign n7011 = n6678 | n8391; + assign n7012 = Pg35 | ~Ng5937; + assign n7013 = ~Pg35 | ~n7014 | ~Ng5953; + assign n7014 = n8350 | n6678; + assign n7015 = Pg35 | ~Ng5933; + assign n7016 = ~Pg35 | ~n7017 | ~Ng5949; + assign n7017 = n6678 | n8392; + assign n7018 = Pg35 | ~Ng5929; + assign n7019 = ~Pg35 | ~n7020 | ~Ng5945; + assign n7020 = n8223 | n6680_1; + assign n7021 = Pg35 | ~Ng5925; + assign n7022 = n6680_1 | n8391; + assign n7023 = Pg35 | ~Ng5921; + assign n7024 = ~Pg35 | ~n7025 | ~Ng5937; + assign n7025 = n8350 | n6680_1; + assign n7026 = Pg35 | ~Ng5917; + assign n7027 = ~Pg35 | ~n7028 | ~Ng5933; + assign n7028 = n6680_1 | n8392; + assign n7029 = Pg35 | ~Ng5909; + assign n7030 = ~Pg35 | ~n7031 | ~Ng5929; + assign n7031 = n8223 | n6679; + assign n7032 = Pg35 | ~Ng5901; + assign n7033 = ~Pg35 | ~n7034 | ~Ng5925; + assign n7034 = n8391 | n6679; + assign n7035 = Pg35 | ~Ng5893; + assign n7036 = ~Pg35 | ~n7037 | ~Ng5921; + assign n7037 = n8350 | n6679; + assign n7038 = Pg35 | ~Ng5889; + assign n7039 = ~Pg35 | ~n7040 | ~Ng5917; + assign n7040 = n8392 | n6679; + assign n7041 = Pg35 | ~Ng5913; + assign n7042 = ~Pg35 | ~n7043 | ~Ng5909; + assign n7043 = n8223 | n8393; + assign n7044 = Pg35 | ~Ng5905; + assign n7045 = ~Pg35 | ~n7046 | ~Ng5901; + assign n7046 = n8391 | n8393; + assign n7047 = Pg35 | ~Ng5897; + assign n7048 = ~Pg35 | ~n7049 | ~Ng5893; + assign n7049 = n8350 | n8393; + assign n7050 = Pg35 | ~Ng5881; + assign n7051 = ~Pg35 | ~n7052 | ~Ng5889; + assign n7052 = n8392 | n8393; + assign n7053 = (n4205 | n7497) & (~n8394 | ~Ng5619); + assign n7054 = Pg35 | ~Ng5611; + assign n7055 = ~Pg35 | ~n7056 | ~Ng5567; + assign n7056 = ~Ng5523 | n8395; + assign n7057 = Pg35 | ~Ng5607; + assign n7058 = Pg35 | ~Ng5603; + assign n7059 = ~Pg35 | ~n7060 | ~Ng5551; + assign n7060 = ~Ng5523 | n8396; + assign n7061 = Pg35 | ~Ng5599; + assign n7062 = ~Pg35 | ~n7063 | ~Ng5615; + assign n7063 = n8221 | n6688; + assign n7064 = Pg35 | ~Ng5595; + assign n7065 = ~Pg35 | ~n7066 | ~Ng5611; + assign n7066 = n6688 | n8395; + assign n7067 = Pg35 | ~Ng5591; + assign n7068 = ~Pg35 | ~n7069 | ~Ng5607; + assign n7069 = n8351 | n6688; + assign n7070 = Pg35 | ~Ng5587; + assign n7071 = ~Pg35 | ~n7072 | ~Ng5603; + assign n7072 = n6688 | n8396; + assign n7073 = Pg35 | ~Ng5583; + assign n7074 = ~Pg35 | ~n7075 | ~Ng5599; + assign n7075 = n8221 | n6690; + assign n7076 = Pg35 | ~Ng5579; + assign n7077 = n6690 | n8395; + assign n7078 = Pg35 | ~Ng5575; + assign n7079 = ~Pg35 | ~n7080 | ~Ng5591; + assign n7080 = n8351 | n6690; + assign n7081 = Pg35 | ~Ng5571; + assign n7082 = ~Pg35 | ~n7083 | ~Ng5587; + assign n7083 = n6690 | n8396; + assign n7084 = Pg35 | ~Ng5563; + assign n7085 = ~Pg35 | ~n7086 | ~Ng5583; + assign n7086 = n8221 | n6689; + assign n7087 = Pg35 | ~Ng5555; + assign n7088 = ~Pg35 | ~n7089 | ~Ng5579; + assign n7089 = n8395 | n6689; + assign n7090 = Pg35 | ~Ng5547; + assign n7091 = ~Pg35 | ~n7092 | ~Ng5575; + assign n7092 = n8351 | n6689; + assign n7093 = Pg35 | ~Ng5543; + assign n7094 = ~Pg35 | ~n7095 | ~Ng5571; + assign n7095 = n8396 | n6689; + assign n7096 = Pg35 | ~Ng5567; + assign n7097 = ~Pg35 | ~n7098 | ~Ng5563; + assign n7098 = n8221 | n8397; + assign n7099 = Pg35 | ~Ng5559; + assign n7100 = ~Pg35 | ~n7101 | ~Ng5555; + assign n7101 = n8395 | n8397; + assign n7102 = Pg35 | ~Ng5551; + assign n7103 = ~Pg35 | ~n7104 | ~Ng5547; + assign n7104 = n8351 | n8397; + assign n7105 = Pg35 | ~Ng5535; + assign n7106 = ~Pg35 | ~n7107 | ~Ng5543; + assign n7107 = n8396 | n8397; + assign n7108 = (n7934 | ~Ng5272) & (n4205 | n7527); + assign n7109 = Pg35 | ~Ng5264; + assign n7110 = ~Pg35 | ~n7111 | ~Ng5220; + assign n7111 = ~Ng5176 | n8398; + assign n7112 = Pg35 | ~Ng5260; + assign n7113 = ~Pg35 | ~n6692 | ~Ng5212; + assign n7114 = Pg35 | ~Ng5256; + assign n7115 = ~Pg35 | ~n7116 | ~Ng5204; + assign n7116 = ~Ng5176 | n8399; + assign n7117 = Pg35 | ~Ng5252; + assign n7118 = ~Pg35 | ~n7119 | ~Ng5268; + assign n7119 = n8225 | n6698; + assign n7120 = Pg35 | ~Ng5248; + assign n7121 = ~Pg35 | ~n7122 | ~Ng5264; + assign n7122 = n6698 | n8398; + assign n7123 = Pg35 | ~Ng5244; + assign n7124 = n8352 | n6698; + assign n7125 = Pg35 | ~Ng5240; + assign n7126 = ~Pg35 | ~n7127 | ~Ng5256; + assign n7127 = n6698 | n8399; + assign n7128 = Pg35 | ~Ng5236; + assign n7129 = n8225 | n6700; + assign n7130 = Pg35 | ~Ng5232; + assign n7131 = n6700 | n8398; + assign n7132 = Pg35 | ~Ng5228; + assign n7133 = ~Pg35 | ~n7134 | ~Ng5244; + assign n7134 = n8352 | n6700; + assign n7135 = Pg35 | ~Ng5224; + assign n7136 = ~Pg35 | ~n7137 | ~Ng5240; + assign n7137 = n6700 | n8399; + assign n7138 = Pg35 | ~Ng5216; + assign n7139 = ~Pg35 | ~n7140 | ~Ng5236; + assign n7140 = n8225 | n6699; + assign n7141 = Pg35 | ~Ng5208; + assign n7142 = ~Pg35 | ~n7143 | ~Ng5232; + assign n7143 = n8398 | n6699; + assign n7144 = Pg35 | ~Ng5200; + assign n7145 = ~Pg35 | ~n7146 | ~Ng5228; + assign n7146 = n8352 | n6699; + assign n7147 = Pg35 | ~Ng5196; + assign n7148 = ~Pg35 | ~n7149 | ~Ng5224; + assign n7149 = n8399 | n6699; + assign n7150 = Pg35 | ~Ng5220; + assign n7151 = ~Pg35 | ~n7152 | ~Ng5216; + assign n7152 = n8225 | n8400; + assign n7153 = Pg35 | ~Ng5212; + assign n7154 = ~Pg35 | ~n7155 | ~Ng5208; + assign n7155 = n8398 | n8400; + assign n7156 = Pg35 | ~Ng5204; + assign n7157 = ~Pg35 | ~n7158 | ~Ng5200; + assign n7158 = n8352 | n8400; + assign n7159 = Pg35 | ~Ng5188; + assign n7160 = ~Pg35 | ~n7161 | ~Ng5196; + assign n7161 = n8399 | n8400; + assign n7162 = (~Ng4507 & n9239) | (~Pg113 & (~Ng4507 | ~n9239)); + assign n7163 = n7162 & Pg35; + assign n7164 = n9241 | ~Pg115 | Ng4157; + assign n7165 = ~n9241 | Pg115 | Ng4157; + assign n7166 = n9240 | ~Pg126 | Ng4146; + assign n7167 = ~n9240 | Pg126 | Ng4146; + assign n7168 = n7167 & n7164 & n7165 & n7166; + assign n7169 = ~n8325 | n7566 | ~Ng4093; + assign n7170 = ~Ng2841 | Ng4093 | n8325; + assign n7171 = (n4205 | n7568) & (~n8401 | ~Ng3965); + assign n7172 = Pg35 | ~Ng3957; + assign n7173 = ~Pg35 | ~n7174 | ~Ng3913; + assign n7174 = ~Ng3869 | n8402; + assign n7175 = Pg35 | ~Ng3953; + assign n7176 = ~Pg35 | ~n6713 | ~Ng3905; + assign n7177 = Pg35 | ~Ng3949; + assign n7178 = ~Pg35 | ~n7179 | ~Ng3897; + assign n7179 = ~Ng3869 | n8403; + assign n7180 = Pg35 | ~Ng3945; + assign n7181 = ~Pg35 | ~n7182 | ~Ng3961; + assign n7182 = n8219 | n6719; + assign n7183 = Pg35 | ~Ng3941; + assign n7184 = ~Pg35 | ~n7185 | ~Ng3957; + assign n7185 = n6719 | n8402; + assign n7186 = Pg35 | ~Ng3937; + assign n7187 = n8365 | n6719; + assign n7188 = Pg35 | ~Ng3933; + assign n7189 = ~Pg35 | ~n7190 | ~Ng3949; + assign n7190 = n6719 | n8403; + assign n7191 = Pg35 | ~Ng3929; + assign n7192 = n8219 | n6721; + assign n7193 = Pg35 | ~Ng3925; + assign n7194 = n6721 | n8402; + assign n7195 = Pg35 | ~Ng3921; + assign n7196 = ~Pg35 | ~n7197 | ~Ng3937; + assign n7197 = n8365 | n6721; + assign n7198 = Pg35 | ~Ng3917; + assign n7199 = ~Pg35 | ~n7200 | ~Ng3933; + assign n7200 = n6721 | n8403; + assign n7201 = Pg35 | ~Ng3909; + assign n7202 = ~Pg35 | ~n7203 | ~Ng3929; + assign n7203 = n8219 | n6720; + assign n7204 = Pg35 | ~Ng3901; + assign n7205 = ~Pg35 | ~n7206 | ~Ng3925; + assign n7206 = n8402 | n6720; + assign n7207 = Pg35 | ~Ng3893; + assign n7208 = ~Pg35 | ~n7209 | ~Ng3921; + assign n7209 = n8365 | n6720; + assign n7210 = Pg35 | ~Ng3889; + assign n7211 = ~Pg35 | ~n7212 | ~Ng3917; + assign n7212 = n8403 | n6720; + assign n7213 = Pg35 | ~Ng3913; + assign n7214 = ~Pg35 | ~n7215 | ~Ng3909; + assign n7215 = n8219 | n8404; + assign n7216 = Pg35 | ~Ng3905; + assign n7217 = ~Pg35 | ~n7218 | ~Ng3901; + assign n7218 = n8402 | n8404; + assign n7219 = Pg35 | ~Ng3897; + assign n7220 = ~Pg35 | ~n7221 | ~Ng3893; + assign n7221 = n8365 | n8404; + assign n7222 = Pg35 | ~Ng3881; + assign n7223 = ~Pg35 | ~n7224 | ~Ng3889; + assign n7224 = n8403 | n8404; + assign n7225 = (n4205 | n7599) & (~n8405 | ~Ng3614); + assign n7226 = Pg35 | ~Ng3606; + assign n7227 = ~Pg35 | ~n7228 | ~Ng3562; + assign n7228 = ~Ng3518 | n8406; + assign n7229 = Pg35 | ~Ng3602; + assign n7230 = ~Pg35 | ~n6723 | ~Ng3554; + assign n7231 = Pg35 | ~Ng3598; + assign n7232 = ~Pg35 | ~n7233 | ~Ng3546; + assign n7233 = ~Ng3518 | n8407; + assign n7234 = Pg35 | ~Ng3594; + assign n7235 = ~Pg35 | ~n7236 | ~Ng3610; + assign n7236 = n8224 | n6729; + assign n7237 = Pg35 | ~Ng3590; + assign n7238 = ~Pg35 | ~n7239 | ~Ng3606; + assign n7239 = n6729 | n8406; + assign n7240 = Pg35 | ~Ng3586; + assign n7241 = n8366 | n6729; + assign n7242 = Pg35 | ~Ng3582; + assign n7243 = ~Pg35 | ~n7244 | ~Ng3598; + assign n7244 = n6729 | n8407; + assign n7245 = Pg35 | ~Ng3578; + assign n7246 = ~Pg35 | ~n7247 | ~Ng3594; + assign n7247 = n8224 | n6731; + assign n7248 = Pg35 | ~Ng3574; + assign n7249 = n6731 | n8406; + assign n7250 = Pg35 | ~Ng3570; + assign n7251 = ~Pg35 | ~n7252 | ~Ng3586; + assign n7252 = n8366 | n6731; + assign n7253 = Pg35 | ~Ng3566; + assign n7254 = ~Pg35 | ~n7255 | ~Ng3582; + assign n7255 = n6731 | n8407; + assign n7256 = Pg35 | ~Ng3558; + assign n7257 = n8224 | n6730; + assign n7258 = Pg35 | ~Ng3550; + assign n7259 = ~Pg35 | ~n7260 | ~Ng3574; + assign n7260 = n8406 | n6730; + assign n7261 = Pg35 | ~Ng3542; + assign n7262 = ~Pg35 | ~n7263 | ~Ng3570; + assign n7263 = n8366 | n6730; + assign n7264 = Pg35 | ~Ng3538; + assign n7265 = ~Pg35 | ~n7266 | ~Ng3566; + assign n7266 = n8407 | n6730; + assign n7267 = Pg35 | ~Ng3562; + assign n7268 = ~Pg35 | ~n7269 | ~Ng3558; + assign n7269 = n8224 | n8408; + assign n7270 = Pg35 | ~Ng3554; + assign n7271 = ~Pg35 | ~n7272 | ~Ng3550; + assign n7272 = n8406 | n8408; + assign n7273 = Pg35 | ~Ng3546; + assign n7274 = ~Pg35 | ~n7275 | ~Ng3542; + assign n7275 = n8366 | n8408; + assign n7276 = Pg35 | ~Ng3530; + assign n7277 = ~Pg35 | ~n7278 | ~Ng3538; + assign n7278 = n8407 | n8408; + assign n7279 = (n4205 | n7628) & (~n8409 | ~Ng3263); + assign n7280 = Pg35 | ~Ng3255; + assign n7281 = ~Pg35 | ~n7282 | ~Ng3211; + assign n7282 = ~Ng3167 | n8410; + assign n7283 = Pg35 | ~Ng3251; + assign n7284 = ~Pg35 | ~n6733 | ~Ng3203; + assign n7285 = Pg35 | ~Ng3247; + assign n7286 = ~Pg35 | ~n7287 | ~Ng3195; + assign n7287 = ~Ng3167 | n8411; + assign n7288 = Pg35 | ~Ng3243; + assign n7289 = ~Pg35 | ~n7290 | ~Ng3259; + assign n7290 = n8216 | n6739; + assign n7291 = Pg35 | ~Ng3239; + assign n7292 = ~Pg35 | ~n7293 | ~Ng3255; + assign n7293 = n6739 | n8410; + assign n7294 = Pg35 | ~Ng3235; + assign n7295 = ~Pg35 | ~n7296 | ~Ng3251; + assign n7296 = n8367 | n6739; + assign n7297 = Pg35 | ~Ng3231; + assign n7298 = ~Pg35 | ~n7299 | ~Ng3247; + assign n7299 = n6739 | n8411; + assign n7300 = Pg35 | ~Ng3227; + assign n7301 = ~Pg35 | ~n7302 | ~Ng3243; + assign n7302 = n8216 | n6741; + assign n7303 = Pg35 | ~Ng3223; + assign n7304 = n6741 | n8410; + assign n7305 = Pg35 | ~Ng3219; + assign n7306 = n8367 | n6741; + assign n7307 = Pg35 | ~Ng3215; + assign n7308 = ~Pg35 | ~n7309 | ~Ng3231; + assign n7309 = n6741 | n8411; + assign n7310 = Pg35 | ~Ng3207; + assign n7311 = n8216 | n6740; + assign n7312 = Pg35 | ~Ng3199; + assign n7313 = ~Pg35 | ~n7314 | ~Ng3223; + assign n7314 = n8410 | n6740; + assign n7315 = Pg35 | ~Ng3191; + assign n7316 = ~Pg35 | ~n7317 | ~Ng3219; + assign n7317 = n8367 | n6740; + assign n7318 = Pg35 | ~Ng3187; + assign n7319 = ~Pg35 | ~n7320 | ~Ng3215; + assign n7320 = n8411 | n6740; + assign n7321 = Pg35 | ~Ng3211; + assign n7322 = ~Pg35 | ~n7323 | ~Ng3207; + assign n7323 = n8216 | n8412; + assign n7324 = Pg35 | ~Ng3203; + assign n7325 = ~Pg35 | ~n7326 | ~Ng3199; + assign n7326 = n8410 | n8412; + assign n7327 = Pg35 | ~Ng3195; + assign n7328 = ~Pg35 | ~n7329 | ~Ng3191; + assign n7329 = n8367 | n8412; + assign n7330 = Pg35 | ~Ng3179; + assign n7331 = ~Pg35 | ~n7332 | ~Ng3187; + assign n7332 = n8411 | n8412; + assign n7333 = n9246 | ~Pg35 | n9245; + assign n7334 = n9250 | ~Pg35 | n9249; + assign n7335 = n8106 ^ Ng2741; + assign n7336 = ~Pg35 | ~Ng2841; + assign n7337 = Ng2681 | Ng2675 | ~n8414; + assign n7338 = ~Pg35 | n8413; + assign n7339 = (~n8414 & ~Ng2661) | (n7338 & (~n8414 | Ng2661)); + assign n7340 = n8415 | n8107 | n8369; + assign n7341 = n8369 | n8264 | n8205; + assign n7342 = Ng2547 | Ng2541 | ~n8418; + assign n7343 = ~Pg35 | n8417; + assign n7344 = (~Ng2527 & ~n8418) | (n7343 & (Ng2527 | ~n8418)); + assign n7345 = n8419 | n8108 | n8371; + assign n7346 = n8371 | n8271 | n8203; + assign n7347 = Ng2413 | Ng2407 | ~n8421; + assign n7348 = ~Pg35 | n8420; + assign n7349 = (~n8421 & ~Ng2393) | (n7348 & (~n8421 | Ng2393)); + assign n7350 = n8422 | n8109 | n8372; + assign n7351 = n8372 | n8278 | n8204; + assign n7352 = Ng2279 | Ng2273 | ~n8424; + assign n7353 = ~Pg35 | n8423; + assign n7354 = (~n8424 & ~Ng2259) | (n7353 & (~n8424 | Ng2259)); + assign n7355 = n8425 | n8110 | n8374; + assign n7356 = n8374 | n8286 | n8197; + assign n7357 = Ng2122 | Ng2116 | ~n8428; + assign n7358 = ~Pg35 | n8427; + assign n7359 = (~Ng2102 & ~n8428) | (n7358 & (Ng2102 | ~n8428)); + assign n7360 = n8429 | n8111 | n8375; + assign n7361 = n8375 | n8294 | n8201; + assign n7362 = Ng1988 | Ng1982 | ~n8431; + assign n7363 = ~Pg35 | n8430; + assign n7364 = (~Ng1968 & ~n8431) | (n7363 & (Ng1968 | ~n8431)); + assign n7365 = n8432 | n8112 | n8376; + assign n7366 = n8376 | n8301 | n8202; + assign n7367 = Ng1854 | Ng1848 | ~n8434; + assign n7368 = ~Pg35 | n8433; + assign n7369 = (~n8434 & ~Ng1834) | (n7368 & (~n8434 | Ng1834)); + assign n7370 = n8435 | n8113 | n8377; + assign n7371 = n8377 | n8307 | n8199; + assign n7372 = Ng1720 | Ng1714 | ~n8437; + assign n7373 = ~Pg35 | n8436; + assign n7374 = (~n8437 & ~Ng1700) | (n7373 & (~n8437 | Ng1700)); + assign n7375 = n8438 | n8114 | n8378; + assign n7376 = ~n8207 & ~n8378 & (~Ng1636 | Ng1592); + assign n7377 = ~n5559 & (~Ng1526 | ~n7379); + assign n7378 = (n7377 & (Pg35 | ~Ng1514)) | (~Pg35 & ~Ng1514); + assign n7379 = ~Pg7946 | ~Ng1514; + assign n7380 = ~Ng1361 | ~Pg35 | n6632; + assign n7381 = n7814 | ~n6632 | Ng1361; + assign n7382 = ~Ng1259 | ~n7384 | n8005; + assign n7383 = Pg35 | ~Ng1256; + assign n7384 = ~Ng1256 | ~n8335; + assign n7385 = n8083 & Ng1024 & Ng1002 & Ng1036; + assign n7386 = n7385 | Ng1008 | Ng969; + assign n7387 = ~n4474 & (~Ng1183 | ~n7389); + assign n7388 = (Pg35 & n7387) | (~Ng1171 & (~Pg35 | n7387)); + assign n7389 = ~Pg7916 | ~Ng1171; + assign n7390 = ~Ng1018 | ~Pg35 | n6639; + assign n7391 = n7819 | ~n6639 | Ng1018; + assign n7392 = ~Ng914 | ~n7394 | n8014; + assign n7393 = Pg35 | ~Ng911; + assign n7394 = ~Ng911 | ~n8341; + assign n7395 = ~Ng744 | ~n7397 | n7743; + assign n7396 = Pg35 | ~Ng739; + assign n7397 = ~n6091_1 | ~Ng739 | n8180; + assign n7398 = ~Ng577 | ~n7400 | n8183; + assign n7399 = Pg35 | ~Ng586; + assign n7400 = ~Ng586 | n7754; + assign n7401 = ~n4520 ^ Ng146; + assign n7402 = ~Pg35 | n8246; + assign n7403 = ~Ng6541 | ~n8381 | ~n8382; + assign n7404 = ~Ng6561 | n8222; + assign n7405 = (n7407 & (n8441 | Ng6527)) | (n8441 & ~Ng6527); + assign n7406 = Ng6519 | Ng6513 | n8441; + assign n7407 = ~Pg35 | ~n8440; + assign n7408 = ~Ng6505 | Ng6500 | n8441; + assign n7409 = (~Pg13099 | ~Ng6593) & (~Ng6605 | ~Ng6723); + assign n7410 = (~Pg17764 | ~Ng6649) & (~Pg17722 | ~Ng6597); + assign n7411 = (~Pg17871 | ~Ng6617) & (~Pg12470 | ~Ng6601); + assign n7412 = ~Ng6633 | ~Pg14749 | n7423; + assign n7413 = (n7410 | n6496) & (n7409 | n7426); + assign n7414 = ~Ng6741 | ~Ng6682; + assign n7415 = n7412 & n7413 & (n7411 | n7414); + assign n7416 = (~Pg13099 | ~Ng6581) & (~Ng6589 | ~Ng6723); + assign n7417 = (~Pg17871 | ~Ng6609) & (~Pg12470 | ~Ng6585); + assign n7418 = ~Ng6641 | ~Pg17764 | n7414; + assign n7419 = ~Ng6625 | ~Pg14749 | n7426; + assign n7420 = (n7417 | n6496) & (n7416 | n7423); + assign n7421 = n7418 & n7419 & n7420; + assign n7422 = n9123 & (~Pg17778 | n6496 | ~Ng6637); + assign n7423 = Ng6682 | Ng6741; + assign n7424 = n7422 & (~Pg14828 | n7423 | ~Ng6621); + assign n7425 = n9122 & (~Pg17778 | n7414 | ~Ng6629); + assign n7426 = Ng6741 | ~Ng6682; + assign n7427 = n7425 & (~Pg14828 | n7426 | ~Ng6613); + assign n7428 = (n7421 & Ng6727) | (n7415 & (n7421 | ~Ng6727)); + assign n7429 = (n7427 & n9279) | (n7424 & (n7427 | ~n9279)); + assign n7430 = ~Ng6727 | ~Pg17722 | n7414; + assign n7431 = n7428 & n7429 & (n7430 | ~Ng6657); + assign n7432 = Pg35 | ~Ng6505; + assign n7433 = ~Pg35 | ~n5884_1 | n7431; + assign n7434 = ~Ng6195 | ~n8382 | ~n8386; + assign n7435 = ~Ng6215 | n8217; + assign n7436 = (n7438 & (n8443 | Ng6181)) | (n8443 & ~Ng6181); + assign n7437 = Ng6173 | Ng6167 | n8443; + assign n7438 = ~Pg35 | ~n8442; + assign n7439 = ~Ng6159 | Ng6154 | n8443; + assign n7440 = (~Pg17743 | ~Ng6303) & (~Pg17685 | ~Ng6251); + assign n7441 = (~Pg13085 | ~Ng6247) & (~Ng6259 | ~Ng6377); + assign n7442 = (~Pg17845 | ~Ng6271) & (~Pg12422 | ~Ng6255); + assign n7443 = ~Ng6287 | ~Pg14705 | n7457; + assign n7444 = (n7441 | n7454) & (n7440 | n6502_1); + assign n7445 = ~Ng6395 | ~Ng6336; + assign n7446 = n7443 & n7444 & (n7442 | n7445); + assign n7447 = (~Pg13085 | ~Ng6235) & (~Ng6243 | ~Ng6377); + assign n7448 = (~Pg17845 | ~Ng6263) & (~Pg12422 | ~Ng6239); + assign n7449 = ~Ng6295 | ~Pg17743 | n7445; + assign n7450 = ~Ng6279 | ~Pg14705 | n7454; + assign n7451 = (n7448 | n6502_1) & (n7447 | n7457); + assign n7452 = n7449 & n7450 & n7451; + assign n7453 = n9125 & (~Pg17760 | n6502_1 | ~Ng6291); + assign n7454 = Ng6395 | ~Ng6336; + assign n7455 = n7453 & (~Pg17649 | n7454 | ~Ng6307); + assign n7456 = n9124 & (~Pg14779 | n7454 | ~Ng6267); + assign n7457 = Ng6336 | Ng6395; + assign n7458 = n7456 & (~Pg17649 | n7457 | ~Ng6299); + assign n7459 = (n7452 & Ng6381) | (n7446 & (n7452 | ~Ng6381)); + assign n7460 = (n7458 & n9283) | (n7455 & (n7458 | ~n9283)); + assign n7461 = ~Ng6381 | ~Pg17685 | n7445; + assign n7462 = n7459 & n7460 & (n7461 | ~Ng6311); + assign n7463 = Pg35 | ~Ng6159; + assign n7464 = ~Pg35 | ~n5952 | n7462; + assign n7465 = ~Ng5849 | ~n8382 | ~n8390; + assign n7466 = ~Ng5869 | n8223; + assign n7467 = (n7469 & (n8445 | Ng5835)) | (n8445 & ~Ng5835); + assign n7468 = Ng5827 | Ng5821 | n8445; + assign n7469 = ~Pg35 | ~n8444; + assign n7470 = ~Ng5813 | Ng5808 | n8445; + assign n7471 = (~Pg13068 | ~Ng5901) & (~Ng5913 | ~Ng6031); + assign n7472 = (~Pg17715 | ~Ng5957) & (~Pg17646 | ~Ng5905); + assign n7473 = (~Pg17819 | ~Ng5925) & (~Pg12350 | ~Ng5909); + assign n7474 = ~Ng5941 | ~Pg14673 | n7485; + assign n7475 = (n7472 | n6508) & (n7471 | n7488); + assign n7476 = ~Ng6049 | ~Ng5990; + assign n7477 = n7474 & n7475 & (n7473 | n7476); + assign n7478 = (~Pg13068 | ~Ng5889) & (~Ng5897 | ~Ng6031); + assign n7479 = (~Pg17819 | ~Ng5917) & (~Pg12350 | ~Ng5893); + assign n7480 = ~Ng5933 | ~Pg14673 | n7488; + assign n7481 = ~Ng5949 | ~Pg17715 | n7476; + assign n7482 = (n7479 | n6508) & (n7478 | n7485); + assign n7483 = n7480 & n7481 & n7482; + assign n7484 = n9127 & (~Pg17739 | n6508 | ~Ng5945); + assign n7485 = Ng5990 | Ng6049; + assign n7486 = n7484 & (~Pg14738 | n7485 | ~Ng5929); + assign n7487 = n9126 & (~Pg17739 | n7476 | ~Ng5937); + assign n7488 = Ng6049 | ~Ng5990; + assign n7489 = n7487 & (~Pg14738 | n7488 | ~Ng5921); + assign n7490 = (n7483 & Ng6035) | (n7477 & (n7483 | ~Ng6035)); + assign n7491 = (n7489 & n9287) | (n7486 & (n7489 | ~n9287)); + assign n7492 = ~Ng6035 | ~Pg17646 | n7476; + assign n7493 = n7490 & n7491 & (n7492 | ~Ng5965); + assign n7494 = Pg35 | ~Ng5813; + assign n7495 = ~Pg35 | ~n5940 | n7493; + assign n7496 = ~Ng5503 | ~n8382 | ~n8394; + assign n7497 = ~Ng5523 | n8221; + assign n7498 = (n7500 & (n8447 | Ng5489)) | (n8447 & ~Ng5489); + assign n7499 = Ng5481 | Ng5475 | n8447; + assign n7500 = ~Pg35 | ~n8446; + assign n7501 = Ng5462 | n8447 | ~Ng5467; + assign n7502 = (~Pg17678 | ~Ng5611) & (~Pg17604 | ~Ng5559); + assign n7503 = (~Pg13049 | ~Ng5555) & (~Ng5567 | ~Ng5685); + assign n7504 = (~Pg17813 | ~Ng5579) & (~Pg12300 | ~Ng5563); + assign n7505 = ~Ng5595 | ~Pg14635 | n7516; + assign n7506 = (n7503 | n7519) & (n7502 | n8321); + assign n7507 = ~Ng5703 | ~Ng5644; + assign n7508 = n7505 & n7506 & (n7504 | n7507); + assign n7509 = (~Pg17813 | ~Ng5571) & (~Pg12300 | ~Ng5547); + assign n7510 = (~Pg13049 | ~Ng5543) & (~Ng5551 | ~Ng5685); + assign n7511 = ~Ng5603 | ~Pg17678 | n7507; + assign n7512 = ~Ng5587 | ~Pg14635 | n7519; + assign n7513 = (n7510 | n7516) & (n7509 | n8321); + assign n7514 = n7511 & n7512 & n7513; + assign n7515 = n9129 & (~Pg17711 | n8321 | ~Ng5599); + assign n7516 = Ng5644 | Ng5703; + assign n7517 = n7515 & (~Pg14694 | n7516 | ~Ng5583); + assign n7518 = n9128 & (~Pg17711 | n7507 | ~Ng5591); + assign n7519 = Ng5703 | ~Ng5644; + assign n7520 = n7518 & (~Pg14694 | n7519 | ~Ng5575); + assign n7521 = (n7514 & Ng5689) | (n7508 & (n7514 | ~Ng5689)); + assign n7522 = (n7520 & n9291) | (n7517 & (n7520 | ~n9291)); + assign n7523 = ~Ng5689 | ~Pg17604 | n7507; + assign n7524 = n7521 & n7522 & (n7523 | ~Ng5619); + assign n7525 = n8322 | Ng5462 | n7524; + assign n7526 = ~n8382 | ~Ng5156 | n7934; + assign n7527 = ~Ng5176 | n8225; + assign n7528 = (n7530 & (n8450 | Ng5142)) | (n8450 & ~Ng5142); + assign n7529 = Ng5134 | Ng5128 | n8450; + assign n7530 = ~Pg35 | ~n8449; + assign n7531 = ~Ng5120 | Ng5115 | n8450; + assign n7532 = (~Pg17787 | ~Ng5232) & (~Pg12238 | ~Ng5216); + assign n7533 = (~Pg13039 | ~Ng5208) & (~Ng5220 | ~Ng5339); + assign n7534 = (~Pg17639 | ~Ng5264) & (~Pg17577 | ~Ng5212); + assign n7535 = ~Ng5248 | ~Pg14597 | n7545; + assign n7536 = (n7533 | n7548) & (n7532 | n8192); + assign n7537 = n7535 & n7536 & (n7534 | n6516); + assign n7538 = (~Pg17787 | ~Ng5224) & (~Pg12238 | ~Ng5200); + assign n7539 = (~Pg13039 | ~Ng5196) & (~Ng5204 | ~Ng5339); + assign n7540 = ~Ng5240 | ~Pg14597 | n7548; + assign n7541 = ~Ng5256 | ~Pg17639 | n8192; + assign n7542 = (n7539 | n7545) & (n7538 | n6516); + assign n7543 = n7540 & n7541 & n7542; + assign n7544 = n9131 & (~Pg17519 | n7548 | ~Ng5268); + assign n7545 = Ng5297 | Ng5357; + assign n7546 = n7544 & (~Pg14662 | n7545 | ~Ng5236); + assign n7547 = n9130 & (~Pg17674 | n8192 | ~Ng5244); + assign n7548 = Ng5357 | ~Ng5297; + assign n7549 = n7547 & (~Pg14662 | n7548 | ~Ng5228); + assign n7550 = (n7537 & (~\[4415] | n7543)) | (\[4415] & n7543); + assign n7551 = (n7549 & n9295) | (n7546 & (n7549 | ~n9295)); + assign n7552 = n7550 & n7551 & (~Ng5272 | ~n8448); + assign n7553 = Pg35 | ~Ng5120; + assign n7554 = ~Pg35 | ~n4151_1 | n7552; + assign n7555 = n5907 & n5888 & (Ng4927 | n5926); + assign n7556 = Ng4975 | ~Ng4912 | Ng4899; + assign n7557 = (n5888 | ~Ng4922) & (n5926 | ~Ng4917); + assign n7558 = n7556 & n7557 & (n5907 | ~Ng4907); + assign n7559 = ~Ng4966 & (~n5935 | ~Ng4983) & ~n9297; + assign n7560 = n5939 & n5874_1 & (Ng4737 | n5951); + assign n7561 = Ng4785 | ~Ng4722 | Ng4709; + assign n7562 = (n5874_1 | ~Ng4717) & (n5951 | ~Ng4727); + assign n7563 = n7561 & n7562 & (n5939 | ~Ng4732); + assign n7564 = ~Ng4776 & (~n5949 | ~Ng4793) & ~n9299; + assign n7565 = n8121 ^ Ng4087; + assign n7566 = ~Pg35 | ~Ng2841; + assign n7567 = ~Ng3849 | ~n8382 | ~n8401; + assign n7568 = ~Ng3869 | n8219; + assign n7569 = (n7571 & (n8452 | Ng3835)) | (n8452 & ~Ng3835); + assign n7570 = Ng3827 | Ng3821 | n8452; + assign n7571 = ~Pg35 | ~n8451; + assign n7572 = ~Ng3813 | Ng3808 | n8452; + assign n7573 = (~Pg14518 | ~Ng3901) & (~Ng3913 | ~Ng4031); + assign n7574 = (~Pg16748 | ~Ng3957) & (~Pg16693 | ~Ng3905); + assign n7575 = (~Pg16955 | ~Ng3925) & (~Pg11418 | ~Ng3909); + assign n7576 = ~Ng3941 | ~Pg13906 | n7587; + assign n7577 = (n7574 | n6525) & (n7573 | n7590); + assign n7578 = ~Ng4054 | ~Ng3990; + assign n7579 = n7576 & n7577 & (n7575 | n7578); + assign n7580 = (~Pg16955 | ~Ng3917) & (~Pg11418 | ~Ng3893); + assign n7581 = (~Pg14518 | ~Ng3889) & (~Ng3897 | ~Ng4031); + assign n7582 = ~Ng3949 | ~Pg16748 | n7578; + assign n7583 = ~Ng3933 | ~Pg13906 | n7590; + assign n7584 = (n7581 | n7587) & (n7580 | n6525); + assign n7585 = n7582 & n7583 & n7584; + assign n7586 = n9137 & (~Pg16659 | n7590 | ~Ng3961); + assign n7587 = Ng3990 | Ng4054; + assign n7588 = n7586 & (~Pg13966 | n7587 | ~Ng3929); + assign n7589 = n9136 & (~Pg16775 | n7578 | ~Ng3937); + assign n7590 = Ng4054 | ~Ng3990; + assign n7591 = n7589 & (~Pg13966 | n7590 | ~Ng3921); + assign n7592 = (n7585 & Ng4040) | (n7579 & (n7585 | ~Ng4040)); + assign n7593 = (n7591 & n9303) | (n7588 & (n7591 | ~n9303)); + assign n7594 = ~Ng4040 | ~Pg16693 | n7578; + assign n7595 = n7592 & n7593 & (n7594 | ~Ng3965); + assign n7596 = Pg35 | ~Ng3813; + assign n7597 = ~Pg35 | ~n5927 | n7595; + assign n7598 = ~Ng3498 | ~n8382 | ~n8405; + assign n7599 = ~Ng3518 | n8224; + assign n7600 = (n7602 & (n8454 | Ng3484)) | (n8454 & ~Ng3484); + assign n7601 = Ng3476 | Ng3470 | n8454; + assign n7602 = ~Pg35 | ~n8453; + assign n7603 = ~Ng3462 | Ng3457 | n8454; + assign n7604 = (~Pg16924 | ~Ng3574) & (~Pg11388 | ~Ng3558); + assign n7605 = (~Pg14451 | ~Ng3550) & (~Ng3562 | ~Ng3680); + assign n7606 = (~Pg16722 | ~Ng3606) & (~Pg16656 | ~Ng3554); + assign n7607 = ~Ng3590 | ~Pg13881 | n8455; + assign n7608 = (n7605 | n8327) & (n7604 | n7619); + assign n7609 = n7607 & n7608 & (n7606 | n6531_1); + assign n7610 = (~Pg14451 | ~Ng3538) & (~Ng3546 | ~Ng3680); + assign n7611 = (~Pg16924 | ~Ng3566) & (~Pg11388 | ~Ng3542); + assign n7612 = ~Ng3582 | ~Pg13881 | n8327; + assign n7613 = ~Ng3598 | ~Pg16722 | n7619; + assign n7614 = (n7611 | n6531_1) & (n7610 | n8455); + assign n7615 = n7612 & n7613 & n7614; + assign n7616 = n9139 & (~Pg16627 | n8327 | ~Ng3610); + assign n7617 = n7616 & (~Pg16744 | n6531_1 | ~Ng3594); + assign n7618 = n9138 & (~Pg13926 | n8327 | ~Ng3570); + assign n7619 = ~Ng3703 | ~Ng3639; + assign n7620 = n7618 & (~Pg16744 | n7619 | ~Ng3586); + assign n7621 = (n7615 & Ng3689) | (n7609 & (n7615 | ~Ng3689)); + assign n7622 = (n7620 & n9307) | (n7617 & (n7620 | ~n9307)); + assign n7623 = ~Ng3689 | ~Pg16656 | n7619; + assign n7624 = n7621 & n7622 & (n7623 | ~Ng3614); + assign n7625 = Pg35 | ~Ng3462; + assign n7626 = ~Pg35 | ~n5889 | n7624; + assign n7627 = ~Ng3147 | ~n8382 | ~n8409; + assign n7628 = ~Ng3167 | n8216; + assign n7629 = (n7631 & (n8457 | Ng3133)) | (n8457 & ~Ng3133); + assign n7630 = Ng3125 | Ng3119 | n8457; + assign n7631 = ~Pg35 | ~n8456; + assign n7632 = Ng3106 | n8457 | ~Ng3111; + assign n7633 = (~Pg16686 | ~Ng3255) & (~Pg16624 | ~Ng3203); + assign n7634 = (~Pg16874 | ~Ng3223) & (~Pg11349 | ~Ng3207); + assign n7635 = (~Pg14421 | ~Ng3199) & (~Ng3211 | ~Ng3329); + assign n7636 = ~Ng3239 | ~Pg13865 | n7649; + assign n7637 = (n7634 | n8189) & (n7633 | n6537); + assign n7638 = Ng3352 | ~Ng3288; + assign n7639 = n7636 & n7637 & (n7635 | n7638); + assign n7640 = (~Pg16874 | ~Ng3215) & (~Pg11349 | ~Ng3191); + assign n7641 = (~Pg14421 | ~Ng3187) & (~Ng3195 | ~Ng3329); + assign n7642 = ~Ng3247 | ~Pg16686 | n8189; + assign n7643 = ~Ng3231 | ~Pg13865 | n7638; + assign n7644 = (n7641 | n7649) & (n7640 | n6537); + assign n7645 = n7642 & n7643 & n7644; + assign n7646 = n9141 & (~Pg16718 | n6537 | ~Ng3243); + assign n7647 = n7646 & (~Pg16603 | n7638 | ~Ng3259); + assign n7648 = n9140 & (~Pg13895 | n7638 | ~Ng3219); + assign n7649 = Ng3288 | Ng3352; + assign n7650 = n7648 & (~Pg16603 | n7649 | ~Ng3251); + assign n7651 = (n7645 & Ng3338) | (n7639 & (n7645 | ~Ng3338)); + assign n7652 = (n7650 & n9311) | (n7647 & (n7650 | ~n9311)); + assign n7653 = ~Ng3338 | ~Pg16624 | n8189; + assign n7654 = n7651 & n7652 & (n7653 | ~Ng3263); + assign n7655 = n8328 | Ng3106 | n7654; + assign n7656 = n9313 & (~Pg35 | ~Ng2735 | ~n7657); + assign n7657 = ~Ng2729 | n8256; + assign n7658 = n5920 & (~n7659 | ~n8415); + assign n7659 = ~Ng2638 | ~Ng2652 | ~n8415; + assign n7660 = Ng2638 & (~Pg35 | (n5920 & n7659)); + assign n7661 = (~Ng2619 | ~Ng2571) & (~Ng2579 | ~Ng2587); + assign n7662 = Ng2587 | Ng2619 | ~Ng2575; + assign n7663 = (n8205 | ~Ng2583) & (~Ng2563 | n8415); + assign n7664 = n7662 & n7663 & (Ng2610 | n7661); + assign n7665 = n6745 | ~Ng2638; + assign n7666 = (Pg35 | ~Ng2619) & (n7664 | n8369); + assign n7667 = n5919 & (~n7668 | ~n8419); + assign n7668 = ~Ng2504 | ~Ng2518 | ~n8419; + assign n7669 = Ng2504 & (~Pg35 | (n5919 & n7668)); + assign n7670 = (~Ng2485 | ~Ng2437) & (~Ng2445 | ~Ng2453); + assign n7671 = Ng2453 | Ng2485 | ~Ng2441; + assign n7672 = (n8203 | ~Ng2449) & (~Ng2429 | n8419); + assign n7673 = n7671 & n7672 & (Ng2476 | n7670); + assign n7674 = n6755 | ~Ng2504; + assign n7675 = (Pg35 | ~Ng2485) & (n7673 | n8371); + assign n7676 = n8422 & Ng2384 & Ng2370; + assign n7677 = n5925 & (n7676 | ~n8422); + assign n7678 = Ng2370 & (~Pg35 | (n5925 & ~n7676)); + assign n7679 = (~Ng2351 | ~Ng2303) & (~Ng2311 | ~Ng2319); + assign n7680 = Ng2319 | Ng2351 | ~Ng2307; + assign n7681 = (n8204 | ~Ng2315) & (~Ng2295 | n8422); + assign n7682 = n7680 & n7681 & (Ng2342 | n7679); + assign n7683 = n6765 | ~Ng2370; + assign n7684 = (Pg35 | ~Ng2351) & (n7682 | n8372); + assign n7685 = n8425 & Ng2250 & Ng2236; + assign n7686 = n5878 & (n7685 | ~n8425); + assign n7687 = Ng2236 & (~Pg35 | (n5878 & ~n7685)); + assign n7688 = (~Ng2217 | ~Ng2169) & (~Ng2177 | ~Ng2185); + assign n7689 = Ng2185 | Ng2217 | ~Ng2173; + assign n7690 = (n8197 | ~Ng2181) & (~Ng2161 | n8425); + assign n7691 = n7689 & n7690 & (Ng2208 | n7688); + assign n7692 = n6775 | ~Ng2236; + assign n7693 = (Pg35 | ~Ng2217) & (n7691 | n8374); + assign n7694 = n8429 & Ng2093 & Ng2079; + assign n7695 = n5916 & (n7694 | ~n8429); + assign n7696 = Ng2079 & (~Pg35 | (n5916 & ~n7694)); + assign n7697 = (~Ng2060 | ~Ng2012) & (~Ng2020 | ~Ng2028); + assign n7698 = Ng2028 | Ng2060 | ~Ng2016; + assign n7699 = (n8201 | ~Ng2024) & (~Ng2004 | n8429); + assign n7700 = n7698 & n7699 & (Ng2051 | n7697); + assign n7701 = n6785 | ~Ng2079; + assign n7702 = (Pg35 | ~Ng2060) & (n7700 | n8375); + assign n7703 = n8432 & Ng1959 & Ng1945; + assign n7704 = n5899 & (n7703 | ~n8432); + assign n7705 = Ng1945 & (~Pg35 | (n5899 & ~n7703)); + assign n7706 = (~Ng1926 | ~Ng1878) & (~Ng1886 | ~Ng1894); + assign n7707 = Ng1894 | Ng1926 | ~Ng1882; + assign n7708 = (n8202 | ~Ng1890) & (~Ng1870 | n8432); + assign n7709 = n7707 & n7708 & (Ng1917 | n7706); + assign n7710 = n6795 | ~Ng1945; + assign n7711 = (Pg35 | ~Ng1926) & (n7709 | n8376); + assign n7712 = n5941 & (~n7713 | ~n8435); + assign n7713 = ~Ng1811 | ~Ng1825 | ~n8435; + assign n7714 = Ng1811 & (~Pg35 | (n5941 & n7713)); + assign n7715 = (~Ng1792 | ~Ng1744) & (~Ng1752 | ~Ng1760); + assign n7716 = Ng1760 | Ng1792 | ~Ng1748; + assign n7717 = (n8199 | ~Ng1756) & (~Ng1736 | n8435); + assign n7718 = n7716 & n7717 & (Ng1783 | n7715); + assign n7719 = n6805 | ~Ng1811; + assign n7720 = (Pg35 | ~Ng1792) & (n7718 | n8377); + assign n7721 = n5868 & (~n7722 | ~n8438); + assign n7722 = ~Ng1677 | ~Ng1691 | ~n8438; + assign n7723 = Ng1677 & (~Pg35 | (n5868 & n7722)); + assign n7724 = (~Ng1657 | ~Ng1608) & (~Ng1616 | ~Ng1624); + assign n7725 = Ng1624 | Ng1657 | ~Ng1612; + assign n7726 = (n8207 | ~Ng1620) & (~Ng1600 | n8438); + assign n7727 = n7725 & n7726 & (Ng1648 | n7724); + assign n7728 = n6815 | ~Ng1677; + assign n7729 = (Pg35 | ~Ng1657) & (n7727 | n8378); + assign n7730 = (Pg35 & ~n8771) | (~Ng1472 & (~Pg35 | ~n8771)); + assign n7731 = ~Pg35 | n5170; + assign n7732 = n8335 | ~Ng1256 | n8005; + assign n7733 = Pg35 | ~Ng1252; + assign n7734 = (Pg35 & ~n8779) | (~Ng1129 & (~Pg35 | ~n8779)); + assign n7735 = ~Pg35 | n4887; + assign n7736 = n8341 | ~Ng911 | n8014; + assign n7737 = Pg35 | ~Ng907; + assign n7738 = ~Ng847 | ~Ng812; + assign n7739 = n7738 & (Ng837 | ~Ng847); + assign n7740 = ~n7739 | ~n9326 | Ng723; + assign n7741 = ~Ng723 | n7904 | n9326; + assign n7742 = ~n6091_1 ^ Ng739; + assign n7743 = ~Pg35 | n8180; + assign n7744 = ~Ng699 | ~Ng681 | n8465 | Ng645 | n8466 | Ng650; + assign n7745 = Ng703 & (n7744 | ~n8122); + assign n7746 = n9327 | ~n7745 | Ng714; + assign n7747 = ~n9327 | n7751 | ~Ng714; + assign n7748 = ~n8467 | ~n7745 | Ng676; + assign n7749 = n8467 | n7751 | ~Ng676; + assign n7750 = ~n8122 ^ Ng671; + assign n7751 = ~Pg35 | ~n7745; + assign n7752 = ~Ng586 | ~n7754 | n8183; + assign n7753 = Pg35 | ~Ng572; + assign n7754 = ~Ng572 | n7831; + assign n7755 = ~Pg35 | n8468; + assign n7756 = n9328 & (~Pg35 | ~Ng490 | n8470); + assign n7757 = Ng417 | n9329 | n8027; + assign n7758 = ~Pg35 | ~n7976; + assign n7759 = n6500 | ~Ng5011; + assign n7760 = n6506 | ~Ng4826; + assign n7761 = n6512_1 | ~Ng4831; + assign n7762 = (n7791 | ~Ng4821) & (n7524 | n8322); + assign n7763 = ~\[4427] | n6520; + assign n7764 = (n7578 & Ng4049) | (n6525 & (n7578 | ~Ng4049)); + assign n7765 = (n7587 & (~Ng4045 | n7590)) | (Ng4045 & n7590); + assign n7766 = ~Ng4961 & (~n5927 | (n7764 & n7765)); + assign n7767 = n6529 | ~Ng4961; + assign n7768 = n8211 | n5888; + assign n7769 = (~Ng3694 & n8455) | (n8327 & (Ng3694 | n8455)); + assign n7770 = (n7619 & Ng3698) | (n6531_1 & (n7619 | ~Ng3698)); + assign n7771 = ~Ng4950 & (~n5889 | (n7769 & n7770)); + assign n7772 = n6535 | ~Ng4950; + assign n7773 = n8211 | n5907; + assign n7774 = n8211 | Ng4975 | Ng4899; + assign n7775 = ~Pg35 | n5908; + assign n7776 = (n7423 & (~Ng6732 | n7426)) | (Ng6732 & n7426); + assign n7777 = (n7414 & Ng6736) | (n6496 & (n7414 | ~Ng6736)); + assign n7778 = ~Ng4894 & (~n5884_1 | (n7776 & n7777)); + assign n7779 = n6500 | ~Ng4894; + assign n7780 = (~Ng6386 & n7457) | (n7454 & (Ng6386 | n7457)); + assign n7781 = (n7445 & Ng6390) | (n6502_1 & (n7445 | ~Ng6390)); + assign n7782 = ~Ng4771 & (~n5952 | (n7780 & n7781)); + assign n7783 = n6506 | ~Ng4771; + assign n7784 = n8209 | n5939; + assign n7785 = (n7485 & (~Ng6040 | n7488)) | (Ng6040 & n7488); + assign n7786 = (n7476 & Ng6044) | (n6508 & (n7476 | ~Ng6044)); + assign n7787 = ~Ng4760 & (~n5940 | (n7785 & n7786)); + assign n7788 = n6512_1 | ~Ng4760; + assign n7789 = n8209 | n5874_1; + assign n7790 = n8209 | Ng4785 | Ng4709; + assign n7791 = ~Pg35 | n5876; + assign n7792 = (n8192 & Ng5352) | (n6516 & (n8192 | ~Ng5352)); + assign n7793 = (n7545 & (~Ng5348 | n7548)) | (Ng5348 & n7548); + assign n7794 = ~Ng4704 & (~n4151_1 | (n7792 & n7793)); + assign n7795 = n6520 | ~Ng4704; + assign n7796 = n5951 | n8209; + assign n7797 = Pg35 & (Ng4057 | Ng4064 | ~n8471); + assign n7798 = Pg35 | ~Ng4119; + assign n7799 = ~Pg35 | ~n7800 | ~Ng4122; + assign n7800 = n8323 | ~n8471; + assign n7801 = ~Pg35 | ~Ng4145; + assign n7802 = Pg35 | ~Ng4116; + assign n7803 = ~Ng4119 | ~Pg35 | n8472; + assign n7804 = Pg35 | ~Ng4112; + assign n7805 = ~Ng4116 | ~Pg35 | n8473; + assign n7806 = n9336 & (~Pg35 | ~Ng4076 | ~n7807); + assign n7807 = ~n8324 | ~Ng4082; + assign n7808 = n6529 | ~Ng4035; + assign n7809 = n6535 | ~Ng3684; + assign n7810 = (n7775 | ~Ng3333) & (n7654 | n8328); + assign n7811 = Pg35 | ~Ng2724; + assign n7812 = n8256 ^ Ng2729; + assign n7813 = n9337 & (~Pg35 | n6631 | ~Ng1345); + assign n7814 = ~Pg35 | ~n8333; + assign n7815 = ~Ng1252 | ~n7817 | n8005; + assign n7816 = Pg35 | ~Ng1280; + assign n7817 = n8334 | ~Ng1280; + assign n7818 = n9338 & (~Pg35 | n6638_1 | ~Ng1002); + assign n7819 = ~Pg35 | ~n8339; + assign n7820 = ~Ng907 | ~n7822 | n8014; + assign n7821 = Pg35 | ~Ng936; + assign n7822 = n8340 | ~Ng936; + assign n7823 = n8464 | ~n7739 | Ng827; + assign n7824 = ~n8464 | n7904 | ~Ng827; + assign n7825 = n7758 | ~Ng699; + assign n7826 = ~Pg35 | n8474; + assign n7827 = (n7826 | ~Ng681) & (~Ng650 | ~n8475); + assign n7828 = ~n7986 & (~Ng703 | Ng714); + assign n7829 = ~Ng572 | ~n7831 | n8183; + assign n7830 = Pg35 | ~Ng568; + assign n7831 = ~Ng568 | n7909; + assign n7832 = Pg35 | ~Ng528; + assign n7833 = ~n5934 ^ Ng482; + assign n7834 = ~Pg35 | ~n8241; + assign n7835 = n5881 | n5885; + assign n7836 = n7835 & (n5918 | (n5881 & n5885)); + assign n7837 = ~n5905 & n5877 & ~n5902; + assign n7838 = ~n8212 & (n5877 | (~n5902 & ~n5905)); + assign n7839 = Ng4531 & Ng4581; + assign n7840 = Pg10306 & Pg35; + assign n7841 = ~Pg35 | ~Ng4515 | ~Ng4521; + assign n7842 = n7853 | Ng4392 | Ng4417; + assign n7843 = (~Pg35 | n7842) & (~Ng4392 | ~n8479); + assign n7844 = Ng4452 | Ng4438 | Ng4443 | Pg7245 | Pg7260; + assign n7845 = Pg35 & (~Ng4392 | n7844); + assign n7846 = ~Pg35 | Ng4392; + assign n7847 = ~Pg35 | ~Ng4392 | n7844; + assign n7848 = Pg35 | ~Ng4443; + assign n7849 = ~Ng4438 | ~Pg35 | Ng4382; + assign n7850 = Ng4401 ^ Ng4434; + assign n7851 = Pg35 & (n7850 | (Ng4388 & ~Ng4430)); + assign n7852 = ~Pg35 | ~Ng4423; + assign n7853 = Ng4411 | Ng4405 | Ng4375 | Pg7257 | Pg7243; + assign n7854 = Pg35 & (~Ng4392 | n7853); + assign n7855 = ~Ng4382 | ~n8479 | Ng4375; + assign n7856 = ~Ng4375 | Ng4382 | ~n8479; + assign n7857 = (n7842 & (Pg35 | ~Ng4388)) | (~Pg35 & ~Ng4388); + assign n7858 = ~Pg35 | ~Ng4392 | n7853; + assign n7859 = n7853 | n7846; + assign n7860 = Pg35 | ~Ng4141; + assign n7861 = ~n8324 ^ Ng4082; + assign n7862 = (~n5995 | ~Ng2827) & (~n5996 | Ng2595); + assign n7863 = (~n5995 | ~Ng2823) & (~n5996 | Ng2461); + assign n7864 = (~n5995 | ~Ng2811) & (~n5996 | Ng2327); + assign n7865 = (~n5995 | ~Ng2799) & (~n5996 | Ng2193); + assign n7866 = (~n5995 | ~Ng2795) & (~n5996 | Ng2036); + assign n7867 = (~n5995 | ~Ng2791) & (~n5996 | Ng1902); + assign n7868 = (~n5995 | ~Ng2779) & (~n5996 | Ng1768); + assign n7869 = (~n5995 | ~Ng2767) & (~n5996 | Ng1632); + assign n7870 = ~n8255 | n7336 | ~Ng2724; + assign n7871 = ~Ng2841 | Ng2724 | n8255; + assign n7872 = Pg35 | ~Ng1437; + assign n7873 = ~Pg35 | ~Ng1478 | n8481; + assign n7874 = Pg35 | ~Ng1467; + assign n7875 = ~Pg35 | ~Ng1472 | n8482; + assign n7876 = ~Pg35 | ~Ng1448 | n8483; + assign n7877 = Pg12923 & (Pg7946 | Pg19357 | Ng1333); + assign n7878 = Ng1395 & n7877; + assign n7879 = ~n5425 & (Ng1384 | ~Ng1351); + assign n7880 = ~Ng1389 | ~Pg35 | n7879; + assign n7881 = Ng1280 | n8334; + assign n7882 = ~Ng1280 | n8005 | ~n8334; + assign n7883 = Pg35 | ~Ng1094; + assign n7884 = ~Pg35 | ~Ng1135 | n8486; + assign n7885 = Pg35 | ~Ng1124; + assign n7886 = ~Pg35 | ~Ng1129 | n8487; + assign n7887 = ~Pg35 | ~Ng1105 | n8488; + assign n7888 = Pg12919 & (Pg7916 | Pg19334 | Ng990); + assign n7889 = (~Pg35 | ~Ng1061) & (~n7888 | ~Ng1052); + assign n7890 = ~n4558 & (~Ng1008 | Ng1041); + assign n7891 = ~Ng1046 | ~Pg35 | n7890; + assign n7892 = Ng936 | n8340; + assign n7893 = ~Ng936 | n8014 | ~n8340; + assign n7894 = Pg35 & ~Ng890; + assign n7895 = (n8492 | ~Ng872) & (~Ng446 | n8491); + assign n7896 = (~Ng246 | n8491) & (~Pg14167 | n8492); + assign n7897 = (~Ng269 | n8491) & (~Pg14147 | n8492); + assign n7898 = (~Ng239 | n8491) & (~Pg14125 | n8492); + assign n7899 = (~Ng262 | n8491) & (~Pg14096 | n8492); + assign n7900 = (~Ng232 | n8491) & (~Pg14217 | n8492); + assign n7901 = (~Ng255 | n8491) & (~Pg14201 | n8492); + assign n7902 = (~Ng225 | n8491) & (~Pg14189 | n8492); + assign n7903 = n8131 ^ Ng822; + assign n7904 = ~Pg35 | ~n7739; + assign n7905 = Pg35 & (~Ng847 | ~Ng843); + assign n7906 = ~Pg35 | ~\[4435] | n8122; + assign n7907 = ~Ng568 | ~n7909 | n8183; + assign n7908 = Pg35 | ~Ng562; + assign n7909 = ~n5957 | ~Ng562 | n8182; + assign n7910 = ~Ng355 & (~Pg35 | (Ng351 & ~Ng333)); + assign n7911 = ~\[4436] & ~Ng351; + assign n7912 = ~Ng305 & (Ng311 | ~Ng324); + assign n7913 = ~Pg35 | ~Ng336 | ~n8493; + assign n7914 = Pg35 | ~Ng311; + assign n7915 = ~Pg35 | n8493; + assign n7916 = (Pg35 & (Ng329 | n9349)) | (~Ng329 & n9349); + assign n7917 = (~Ng305 & Ng336) | (~Ng311 & (~Ng305 | ~Ng336)); + assign n7918 = ~Ng311 & ~Ng305; + assign n7919 = (~Ng6537 | ~n8381) & (n7404 | ~n8863); + assign n7920 = Pg35 | ~Ng6509; + assign n7921 = Ng6513 | ~Pg35 | n7404; + assign n7922 = (~Ng6191 | ~n8386) & (n7435 | ~n8873); + assign n7923 = Pg35 | ~Ng6163; + assign n7924 = Ng6167 | ~Pg35 | n7435; + assign n7925 = (~Ng5845 | ~n8390) & (n7466 | ~n8883); + assign n7926 = Pg35 | ~Ng5817; + assign n7927 = Ng5821 | ~Pg35 | n7466; + assign n7928 = (~Ng5499 | ~n8394) & (n7497 | ~n8893); + assign n7929 = Pg35 | ~Ng5471; + assign n7930 = Ng5475 | ~Pg35 | n7497; + assign n7931 = (~Ng5152 | n7934) & (n7527 | ~n8903); + assign n7932 = Pg35 | ~Ng5124; + assign n7933 = Ng5128 | ~Pg35 | n7527; + assign n7934 = ~Pg35 | ~n7527; + assign n7935 = Pg35 | ~Ng5097; + assign n7936 = ~Ng5097 | ~n8494; + assign n7937 = Pg35 | ~Ng5092; + assign n7938 = ~Pg35 | ~Ng5097 | n8494; + assign n7939 = Ng5092 & Pg35; + assign n7940 = ~Ng5077 | ~Pg35 | Ng5073; + assign n7941 = Pg35 & ~Ng5084; + assign n7942 = Ng4098 & ~Ng4093; + assign n7943 = n7942 & Ng4076 & ~Ng4064 & n6260_1 & Ng4087 & ~Ng4057; + assign n7944 = ~Ng2841 | n8323 | Ng4141; + assign n7945 = ~Ng4141 | n7566 | ~n8323; + assign n7946 = (Ng4064 & (Pg35 | ~Ng4072)) | (~Pg35 & ~Ng4072); + assign n7947 = n7946 & n6521; + assign n7948 = (~Ng3845 | ~n8401) & (n7568 | ~n8919); + assign n7949 = Pg35 | ~Ng3817; + assign n7950 = Ng3821 | ~Pg35 | n7568; + assign n7951 = (~Ng3494 | ~n8405) & (n7599 | ~n8929); + assign n7952 = Pg35 | ~Ng3466; + assign n7953 = Ng3470 | ~Pg35 | n7599; + assign n7954 = (n7628 | ~n8939) & (~n8409 | ~Ng3143); + assign n7955 = Pg35 | ~Ng3115; + assign n7956 = Ng3119 | ~Pg35 | n7628; + assign n7957 = ~Ng2715 | Ng2719; + assign n7958 = (Pg35 & n8370) | (~Ng2715 & (~Pg35 | n8370)); + assign n7959 = n7957 & n6333 & n7958; + assign n7960 = Pg35 | ~Ng1484; + assign n7961 = ~Pg35 | ~Ng1300 | n8496; + assign n7962 = ~Pg35 | ~n5425 | ~Ng1384; + assign n7963 = n8484 | Ng1384 | n5425; + assign n7964 = ~Ng1361 | ~Ng1373; + assign n7965 = ~n8484 & (~n6631 | (n7964 & ~n9355)); + assign n7966 = Pg35 & (~Pg12923 | Ng1266); + assign n7967 = Ng1249 | n8005; + assign n7968 = Pg35 | ~Ng1141; + assign n7969 = ~Pg35 | ~Ng956 | n8498; + assign n7970 = ~Pg35 | ~n4558 | ~Ng1041; + assign n7971 = n8489 | Ng1041 | n4558; + assign n7972 = ~Ng1018 | ~Ng1030; + assign n7973 = ~n8489 & (~n6638_1 | (n7972 & ~n9360)); + assign n7974 = Pg35 & (~Pg12919 | Ng921); + assign n7975 = Ng904 | n8014; + assign n7976 = ~Ng370 | ~Ng385 | n7993; + assign n7977 = Pg35 & (~n7739 | Ng832 | n7976); + assign n7978 = n8533 | n8534; + assign n7979 = n8138 | n8139; + assign n7980 = n5960 | ~Ng732; + assign n7981 = ~n8123 | ~Pg35 | n7986; + assign n7982 = Pg35 | ~Ng691; + assign n7983 = ~Pg35 | ~n7986; + assign n7984 = n5957 ^ Ng562; + assign n7985 = n7984 & (~Ng632 | ~Ng626) & ~n8183; + assign n7986 = ~Ng358 | ~Ng385 | Ng376; + assign n7987 = Pg35 & (n7986 | ~n8468); + assign n7988 = (~n7983 & ~Ng504) | (~Ng499 & (n7983 | ~Ng504)); + assign n7989 = (~Ng246 | n8499) & (~n8500 | ~Ng460); + assign n7990 = (~Ng446 | n8499) & (~Ng182 | ~n8500); + assign n7991 = Pg35 | ~Ng376; + assign n7992 = ~Pg35 | ~Ng385 | ~n7993; + assign n7993 = ~Ng376 | ~Ng358; + assign n7994 = Ng4322 | ~Pg35 | Ng4332 | Ng4311 | n8191; + assign n7995 = Ng4340 | ~Ng4643; + assign n7996 = Ng4593 | n8232 | Ng4584 | Ng4608 | ~Ng4633 | Ng4616 | n7994 | Ng4601; + assign n7997 = ~Pg35 | Ng4258; + assign n7998 = n7997 & (~Pg35 | Ng4264); + assign n7999 = n7998 & (~Pg35 | Ng4269); + assign n8000 = Pg35 & (~Ng4264 | Ng4273 | ~Ng4258); + assign n8001 = (Ng2715 & (Pg35 | ~Ng2712)) | (~Pg35 & ~Ng2712); + assign n8002 = n8001 & n6333; + assign n8003 = Pg35 | ~Ng1548; + assign n8004 = ~Pg35 | ~Ng1564 | n8495; + assign n8005 = ~Pg35 | ~Pg12923; + assign n8006 = Ng1548 & Pg35; + assign n8007 = n8140 & ~n5425 & ~n5965; + assign n8008 = n8007 & Pg35; + assign n8009 = Pg35 | ~Ng1589; + assign n8010 = ~Pg10527 | ~Pg35 | Pg17423; + assign n8011 = Pg35 & ~Pg12923; + assign n8012 = Pg35 | ~Ng1205; + assign n8013 = ~Pg35 | ~Ng1221 | n8497; + assign n8014 = ~Pg35 | ~Pg12919; + assign n8015 = Ng1205 & Pg35; + assign n8016 = n8141 & n5036_1; + assign n8017 = n8016 & Pg35; + assign n8018 = Pg35 | ~Ng1246; + assign n8019 = ~Pg10500 | ~Pg35 | Pg17400; + assign n8020 = Pg35 & ~Pg12919; + assign n8021 = Pg35 & n7738 & (~Ng832 | ~Ng827); + assign n8022 = ~n7976 & Ng847; + assign n8023 = Ng703 & (~Pg35 | (~Ng837 & n8022)); + assign n8024 = n7758 & (~Pg35 | (Ng837 & ~n7738)); + assign n8025 = (Pg35 & (Ng847 | n9398)) | (~Ng847 & n9398); + assign n8026 = Ng691 & ~Ng542; + assign n8027 = ~Pg35 | n7976; + assign n8028 = (n7758 | ~Ng475) & (n8027 | ~Ng246); + assign n8029 = (n7758 | ~Ng433) & (n8027 | ~Ng269); + assign n8030 = n7758 | ~Ng392; + assign n8031 = ~Ng854 | Ng703 | n8027; + assign n8032 = Pg35 & (Ng4269 | ~Ng4258); + assign n8033 = Ng4264 & Pg35; + assign n8034 = ~Ng4349 | n8063; + assign n8035 = Pg35 & n8034; + assign n8036 = ~n8126 & ~Ng2988; + assign n8037 = ~Ng4564 | ~Ng4555 | ~Ng4561 | ~Ng4558; + assign n8038 = n8037 & ~Ng2988; + assign n8039 = Pg35 & ~Ng2667; + assign n8040 = Pg35 & ~Ng2527; + assign n8041 = Pg35 & ~Ng2399; + assign n8042 = Pg35 & ~Ng2265; + assign n8043 = Pg35 & ~Ng2102; + assign n8044 = Pg35 & ~Ng1968; + assign n8045 = Pg35 & ~Ng1840; + assign n8046 = Pg35 & ~Ng1706; + assign n8047 = n8115 | ~Ng1542; + assign n8048 = Pg35 & n8047; + assign n8049 = n8117 | ~Ng1199; + assign n8050 = Pg35 & n8049; + assign n8051 = Pg35 & ~Ng6533; + assign n8052 = Pg35 & ~Ng6187; + assign n8053 = Pg35 & ~Ng5841; + assign n8054 = Pg35 & ~Ng5495; + assign n8055 = Pg35 & ~Ng5148; + assign n8056 = Pg35 & ~Ng3841; + assign n8057 = Pg35 & ~Ng3490; + assign n8058 = Pg35 & ~Ng3139; + assign n8059 = ~n6252 & (Pg35 | ~Ng385); + assign n1117 = ~n8059; + assign n8061 = ~Ng4593 | ~n8234; + assign n8062 = Ng4332 & Ng4322 & n8233; + assign n8063 = ~Ng4628 | n8232; + assign n8064 = Ng4349 ^ n8063; + assign n8065 = ~Ng4688 | n8208; + assign n8066 = Ng2599 | ~Ng2629; + assign n8067 = ~n8066 ^ Ng112; + assign n8068 = Ng2465 | ~Ng2495; + assign n8069 = ~n8068 ^ Ng112; + assign n8070 = Ng2331 | ~Ng2361; + assign n8071 = ~n8070 ^ Ng112; + assign n8072 = Ng2197 | ~Ng2227; + assign n8073 = ~n8072 ^ Ng112; + assign n8074 = Ng2040 | ~Ng2070; + assign n8075 = ~n8074 ^ Ng112; + assign n8076 = Ng1906 | ~Ng1936; + assign n8077 = ~n8076 ^ Ng112; + assign n8078 = Ng1772 | ~Ng1802; + assign n8079 = ~n8078 ^ Ng112; + assign n8080 = Ng1636 | ~Ng1668; + assign n8081 = ~n8080 ^ Ng112; + assign n8082 = ~Ng1339 ^ Ng1322; + assign n8083 = ~Ng996 ^ Ng979; + assign n8084 = Ng2610 | ~Ng2619; + assign n8085 = Ng110 ^ n8084; + assign n8086 = Ng2476 | ~Ng2485; + assign n8087 = Ng110 ^ n8086; + assign n8088 = Ng2342 | ~Ng2351; + assign n8089 = Ng110 ^ n8088; + assign n8090 = Ng2208 | ~Ng2217; + assign n8091 = Ng110 ^ n8090; + assign n8092 = Ng2051 | ~Ng2060; + assign n8093 = Ng110 ^ n8092; + assign n8094 = Ng1917 | ~Ng1926; + assign n8095 = Ng110 ^ n8094; + assign n8096 = Ng1783 | ~Ng1792; + assign n8097 = Ng110 ^ n8096; + assign n8098 = Ng1648 | ~Ng1657; + assign n8099 = Ng110 ^ n8098; + assign n8100 = Pg35 & Ng5471; + assign n8101 = (n6884 | n6883) & (n8100 | n6887); + assign n8102 = n6883 | n8100 | n6884; + assign n8103 = n6890 & n8102; + assign n8104 = n6889 & (n6890 | n8102); + assign n8105 = Pg35 & Ng3466; + assign n8106 = ~Ng2735 | n7657; + assign n8107 = ~Ng2652 ^ Ng2648; + assign n8108 = ~Ng2514 ^ Ng2518; + assign n8109 = ~Ng2384 ^ Ng2380; + assign n8110 = ~Ng2250 ^ Ng2246; + assign n8111 = ~Ng2089 ^ Ng2093; + assign n8112 = ~Ng1955 ^ Ng1959; + assign n8113 = ~Ng1821 ^ Ng1825; + assign n8114 = ~Ng1687 ^ Ng1691; + assign n8115 = ~Pg7946 | ~Ng1526 | n5963 | Ng1514; + assign n8116 = n8115 ^ Ng1542; + assign n8117 = ~Pg7916 | Ng1171 | ~Ng1183 | n8439; + assign n8118 = n8117 ^ Ng1199; + assign n8119 = ~n5935 ^ n7558; + assign n8120 = ~n5949 ^ n7563; + assign n8121 = ~Ng4076 | n7807; + assign n8122 = ~Ng504 & Ng499 & n5933 & ~n7976; + assign n8123 = Ng691 | ~Ng703 | n7744; + assign n8124 = (n7828 | ~Ng691) & (n7986 | n8123); + assign n8125 = (n5918 | n7835) & (n5865 | n7836); + assign n8126 = Ng4489 & Ng4483 & Ng4486 & Ng4492; + assign n8127 = ~Ng4521 & ~n9340 & (n8126 | Ng4527); + assign n8128 = ~n5958 & (~Ng1536 | (~n8047 & Ng1413)); + assign n8129 = ~n7878 ^ Ng1404; + assign n8130 = ~n5959 & (~Ng1193 | (~n8049 & Ng1070)); + assign n8131 = ~Ng817 | ~Ng832 | n7976; + assign n8132 = n8122 & (Ng728 | (Ng661 & Pg35)); + assign n8133 = n8495 & Ng1564; + assign n8134 = ~n8133 ^ Ng1559; + assign n8135 = n8497 & Ng1221; + assign n8136 = ~n8135 ^ Ng1216; + assign n8137 = Ng232 ^ Ng255; + assign n8138 = ~Ng246 ^ Ng269; + assign n8139 = ~Ng239 ^ Ng262; + assign n8140 = Ng1322 ^ Ng1579; + assign n8141 = Ng1236 ^ Ng979; + assign n8142 = ~Pg54 | Pg57 | Pg56 | Pg53 | Ng55; + assign n8143 = ~Ng50 | Ng16; + assign n8144 = Ng46 & Ng48 & Ng45 & Ng8 & ~Ng52; + assign n8145 = Ng45 | Ng46 | Ng8; + assign n8146 = Ng52 | ~Ng51 | n8145; + assign n8147 = Ng48 | n8146; + assign n8148 = Ng50 | ~Ng16; + assign n8149 = n8147 | n8148; + assign n8150 = Ng16 | Ng50; + assign n8151 = ~Ng52 | Ng48 | n8145; + assign n3827_1 = ~n8142; + assign n8153 = Pg53 | ~n8142; + assign n8154 = n8145 | Ng51 | Ng52; + assign n8155 = n8142 | n6080; + assign n8156 = Ng48 | n8154; + assign n8157 = n8151 | Ng51 | n8143; + assign n8158 = n8157 & n6063 & n6027_1; + assign n8159 = n8150 | n8156; + assign n8160 = n8148 | n8156; + assign n8161 = n8142 | n8160; + assign n8162 = n8143 | n8147; + assign n8163 = n8142 | n8162; + assign n8164 = ~Ng48 | n8143; + assign n8165 = n8146 | n8164; + assign n8166 = n8142 | n8165; + assign n8167 = n8142 | Ng48 | ~Ng50 | ~Ng16; + assign n8168 = n8146 | n8167; + assign n8169 = n8154 | n8167; + assign n8170 = n8154 | n8164; + assign n8171 = n8142 | n8170; + assign n8172 = Ng51 | n8145 | ~Ng52 | n8164; + assign n8173 = n8142 | n8172; + assign n8174 = n8148 | ~n8144 | Ng51; + assign n8175 = Ng1291 | n8161; + assign n8176 = Ng947 | n8163; + assign n8177 = n6087 | n6088; + assign n8178 = Ng4322 ^ Pg72; + assign n8179 = Ng4332 ^ Pg73; + assign n8180 = Pg11678 & ~Ng736; + assign n8181 = Ng370 | ~Ng385 | n7993; + assign n8182 = Pg9048 & ~Ng559; + assign n8183 = ~Pg35 | n8182; + assign n8184 = Ng490 ^ Pg73; + assign n8185 = Ng482 ^ Pg72; + assign n8186 = Ng518 | n5931; + assign n8187 = n5931 | ~Ng518; + assign n8188 = ~Ng4349 | Ng4358; + assign n8189 = ~Ng3352 | ~Ng3288; + assign n8190 = Ng4349 | ~Ng4358; + assign n8191 = Ng4358 | Ng4349; + assign n8192 = ~Ng5357 | ~Ng5297; + assign n8193 = Ng2759 ^ Pg72; + assign n8194 = Ng2763 ^ Pg73; + assign n8195 = n8193 | n8194; + assign n8196 = n8195 | ~Ng2756 | Ng2748; + assign n8197 = ~Ng2208 | Ng2217; + assign n8198 = ~Ng2741 | Ng2756 | Ng2748; + assign n8199 = ~Ng1783 | Ng1792; + assign n8200 = ~Ng2748 | n8195; + assign n8201 = ~Ng2051 | Ng2060; + assign n8202 = ~Ng1917 | Ng1926; + assign n8203 = ~Ng2476 | Ng2485; + assign n8204 = ~Ng2342 | Ng2351; + assign n8205 = ~Ng2610 | Ng2619; + assign n8206 = ~Ng2741 & ~Ng2756 & ~Ng2748; + assign n8207 = ~Ng1648 | Ng1657; + assign n8208 = ~Ng4669 | ~Ng4659 | ~Ng4653; + assign n8209 = ~Ng4793 | ~Ng4776 | Ng4801; + assign n8210 = ~Ng4859 | ~Ng4843 | ~Ng4849; + assign n8211 = ~Ng4983 | ~Ng4966 | Ng4991; + assign n8212 = n7835 | n5865 | n5918; + assign n8213 = Pg35 & Ng6509; + assign n8214 = n8102 | n5880 | n6890 | n8105 | n6889 | n8213; + assign n8215 = ~n8212 & ~n5906 & ~n5905 & n5877 & ~n5902; + assign n8216 = ~Ng3171 | ~Ng3179; + assign n8217 = ~Ng6219 | ~Ng6227; + assign n8218 = ~Ng4098 & Ng4093; + assign n8219 = ~Ng3873 | ~Ng3881; + assign n8220 = Ng4098 & Ng4093; + assign n8221 = ~Ng5527 | ~Ng5535; + assign n8222 = ~Ng6565 | ~Ng6573; + assign n8223 = ~Ng5873 | ~Ng5881; + assign n8224 = ~Ng3522 | ~Ng3530; + assign n8225 = ~Ng5180 | ~Ng5188; + assign n8226 = Ng4108 ^ Pg72; + assign n8227 = Ng4104 ^ Pg73; + assign n8228 = n6126 & ~n8251; + assign n8229 = ~Ng4878 | ~Ng4843; + assign n8230 = n8065 & ~n8253; + assign n8231 = ~Ng4688 | ~Ng4653; + assign n8232 = ~Ng4340 | ~Ng4621 | Ng4639; + assign n8233 = ~n8034 & Ng4358; + assign n8234 = Ng4584 & n8062; + assign n8235 = ~Pg35 | n6216_1; + assign n8236 = Ng4311 & n8233; + assign n8237 = n5924 | Ng4818 | \[4661] ; + assign n8238 = ~n8237 & Ng71; + assign n8239 = n5924 | Ng4818 | \[4661] ; + assign n8240 = (~Ng278 & n4385) | (~n4384 & (Ng278 | n4385)); + assign n8241 = n8240 & ~n5962 & Ng691; + assign n8242 = Ng287 & Ng283 & n8241; + assign n8243 = ~n8242 | ~Ng291; + assign n8244 = ~Ng294 | n8243; + assign n8245 = ~Ng298 | n8244; + assign n8246 = ~Ng691 | n5962 | n6300; + assign n8247 = n4520 & Ng146 & ~n8246; + assign n8248 = Ng164 & n8247; + assign n8249 = ~n8248 | ~Ng150; + assign n8250 = ~Ng153 | n8249; + assign n8251 = Ng63 & n5966 & ~n6124; + assign n8252 = ~n6316 & Ng4966; + assign n8253 = Ng63 & n5966 & ~n6090; + assign n8254 = ~n6327 & Ng4776; + assign n8255 = ~Ng2715 | ~Ng2719; + assign n8256 = ~Ng2724 | n8255; + assign n8257 = n8106 | ~Ng2741; + assign n8258 = ~Ng2748 | n8257; + assign n8259 = ~Ng1322 | Ng1564 | Ng1548 | ~Ng1404 | Ng1559 | Ng1554; + assign n8260 = ~Ng2629 & ~Ng2555; + assign n8261 = ~n8260 | ~n8263; + assign n8262 = n8261 & Pg35; + assign n8263 = n5911 | ~n5999; + assign n8264 = Ng2599 & ~Ng2555; + assign n8265 = n8263 & n8264; + assign n8266 = ~n8263 | ~Ng2555; + assign n8267 = ~Ng2495 & ~Ng2421; + assign n8268 = ~n8267 | ~n8270; + assign n8269 = n8268 & Pg35; + assign n8270 = n5872 | ~n6001; + assign n8271 = Ng2465 & ~Ng2421; + assign n8272 = n8270 & n8271; + assign n8273 = ~n8270 | ~Ng2421; + assign n8274 = ~Ng2361 & ~Ng2287; + assign n8275 = ~n8274 | ~n8277; + assign n8276 = n8275 & Pg35; + assign n8277 = n5910 | ~n6011; + assign n8278 = Ng2331 & ~Ng2287; + assign n8279 = n8277 & n8278; + assign n8280 = ~n8277 | ~Ng2287; + assign n8281 = ~Ng2227 & ~Ng2153; + assign n8282 = ~n8281 | ~n8284; + assign n8283 = n8282 & Pg35; + assign n8284 = n5873 | ~n6007; + assign n8285 = ~Ng2227 | ~n8284; + assign n8286 = Ng2197 & ~Ng2153; + assign n8287 = n8284 & n8286; + assign n8288 = ~Ng979 | Ng1221 | Ng1205 | Ng1211 | ~Ng1061 | Ng1216; + assign n8289 = ~Ng2070 & ~Ng1996; + assign n8290 = ~n8289 | ~n8292; + assign n8291 = n8290 & Pg35; + assign n8292 = n5921 | ~n6003; + assign n8293 = ~Ng2070 | ~n8292; + assign n8294 = Ng2040 & ~Ng1996; + assign n8295 = n8292 & n8294; + assign n8296 = ~Ng1936 & ~Ng1862; + assign n8297 = ~n8296 | ~n8299; + assign n8298 = n8297 & Pg35; + assign n8299 = n5887 | ~n6005; + assign n8300 = ~Ng1936 | ~n8299; + assign n8301 = Ng1906 & ~Ng1862; + assign n8302 = n8299 & n8301; + assign n8303 = ~Ng1802 & ~Ng1728; + assign n8304 = ~n8303 | ~n8306; + assign n8305 = n8304 & Pg35; + assign n8306 = n5894 | ~n5997; + assign n8307 = Ng1772 & ~Ng1728; + assign n8308 = n8306 & n8307; + assign n8309 = ~n8306 | ~Ng1728; + assign n8310 = ~Ng1592 & ~Ng1668; + assign n8311 = ~n8310 | ~n8313; + assign n8312 = n8311 & Pg35; + assign n8313 = n4162 | ~n6009; + assign n8314 = ~Ng1636 | ~n8313; + assign n8315 = ~Ng1592 | ~n8313; + assign n8316 = Ng4801 | Ng4793 | ~Ng4776; + assign n8317 = Ng4991 | Ng4983 | ~Ng4966; + assign n8318 = n5966 & Ng93; + assign n8319 = n6124 | ~n8318; + assign n8320 = n6090 | ~n8318; + assign n8321 = ~Ng5703 | Ng5644; + assign n8322 = ~Pg35 | ~n5876; + assign n8323 = ~Ng4057 | ~Ng4064; + assign n8324 = ~n8323 & Ng4141; + assign n8325 = ~Ng4087 | n8121; + assign n8326 = ~Ng4093 | n8325; + assign n8327 = Ng3703 | ~Ng3639; + assign n8328 = ~Pg35 | ~n5908; + assign n8329 = Pg35 & n5966; + assign n8330 = n5966 & Ng112; + assign n8331 = n8082 | Ng1351; + assign n8332 = ~n8082 | n7964 | ~Ng1351; + assign n8333 = ~n9355 & n8332 & ~Ng1312 & n8331; + assign n8334 = ~Pg12923 | ~Ng1266 | ~Ng1249; + assign n8335 = Ng1252 & ~n7817; + assign n8336 = Ng1259 & ~n7384; + assign n8337 = n8083 | Ng1008; + assign n8338 = ~n8083 | ~Ng1008 | n7972; + assign n8339 = ~n9360 & n8338 & ~Ng969 & n8337; + assign n8340 = ~Pg12919 | ~Ng921 | ~Ng904; + assign n8341 = Ng907 & ~n7822; + assign n8342 = Ng914 & ~n7394; + assign n8343 = Ng43 & ~n5947 & n5966; + assign n8344 = ~Ng4087 & n8343; + assign n4287_1 = Pg35 & Ng6573; + assign n8346 = ~Ng6565 | Ng6573; + assign n8347 = Ng4087 & n8343; + assign n8348 = ~Ng6219 | Ng6227; + assign n1064_1 = Pg35 & Ng5881; + assign n8350 = ~Ng5873 | Ng5881; + assign n8351 = ~Ng5527 | Ng5535; + assign n8352 = ~Ng5180 | Ng5188; + assign n8353 = ~Ng5029 | ~Ng5016 | ~Ng5062; + assign n8354 = ~Ng5033 | n8353 | ~Ng5037; + assign n8355 = ~Ng5022 | Ng5029 | Ng5016; + assign n8356 = n8355 | Ng5033 | Ng5037; + assign n8357 = n8356 | Ng5046 | Ng5041; + assign n8358 = Ng5057 & ~Ng5046 & Ng5022; + assign n8359 = Ng5062 & Ng5046 & ~Ng5057; + assign n8360 = n8358 & Pg84 & ~Ng5041; + assign n8361 = n8359 & ~Pg84 & Ng5052; + assign n8362 = n8358 & ~Pg84 & ~Ng5052; + assign n8363 = Pg84 & Ng5041 & n8359; + assign n8364 = n8360 | n8361 | n8362 | n8363; + assign n8365 = ~Ng3873 | Ng3881; + assign n8366 = ~Ng3522 | Ng3530; + assign n8367 = ~Ng3171 | Ng3179; + assign n8368 = n5966 & Ng110; + assign n8369 = ~Pg35 | ~n5920; + assign n8370 = Ng2715 | ~Ng2719; + assign n8371 = ~Pg35 | ~n5919; + assign n8372 = ~Pg35 | ~n5925; + assign n8373 = Ng2719 | Ng2715; + assign n8374 = ~Pg35 | ~n5878; + assign n8375 = ~Pg35 | ~n5916; + assign n8376 = ~Pg35 | ~n5899; + assign n8377 = ~Pg35 | ~n5941; + assign n8378 = ~Pg35 | ~n5868; + assign n8379 = n8356 & n8354; + assign n8380 = Ng5062 | Ng5022; + assign n8381 = n7404 & Pg35; + assign n8382 = Ng4180 & ~Ng4284; + assign n8383 = Ng6565 | ~Ng6573; + assign n8384 = Ng6565 | Ng6573; + assign n8385 = Ng6555 | Ng6549 | Ng6561; + assign n8386 = n7435 & Pg35; + assign n8387 = Ng6219 | ~Ng6227; + assign n8388 = Ng6219 | Ng6227; + assign n8389 = Ng6203 | Ng6215 | Ng6209; + assign n8390 = n7466 & Pg35; + assign n8391 = Ng5873 | ~Ng5881; + assign n8392 = Ng5873 | Ng5881; + assign n8393 = Ng5863 | Ng5857 | Ng5869; + assign n8394 = n7497 & Pg35; + assign n8395 = Ng5527 | ~Ng5535; + assign n8396 = Ng5527 | Ng5535; + assign n8397 = Ng5517 | Ng5511 | Ng5523; + assign n8398 = Ng5180 | ~Ng5188; + assign n8399 = Ng5180 | Ng5188; + assign n8400 = Ng5170 | Ng5164 | Ng5176; + assign n8401 = n7568 & Pg35; + assign n8402 = Ng3873 | ~Ng3881; + assign n8403 = Ng3873 | Ng3881; + assign n8404 = Ng3857 | Ng3869 | Ng3863; + assign n8405 = n7599 & Pg35; + assign n8406 = Ng3522 | ~Ng3530; + assign n8407 = Ng3522 | Ng3530; + assign n8408 = Ng3512 | Ng3506 | Ng3518; + assign n8409 = n7628 & Pg35; + assign n8410 = Ng3171 | ~Ng3179; + assign n8411 = Ng3171 | Ng3179; + assign n8412 = Ng3161 | Ng3155 | Ng3167; + assign n8413 = Ng2619 & n5920 & Ng2587; + assign n8414 = Pg35 & n8413; + assign n8415 = ~Ng2610 | Ng2587; + assign n8416 = Ng2485 & n5919; + assign n8417 = Ng2453 & n8416; + assign n8418 = Pg35 & n8417; + assign n8419 = ~Ng2476 | Ng2453; + assign n8420 = Ng2351 & n5925 & Ng2319; + assign n8421 = Pg35 & n8420; + assign n8422 = ~Ng2342 | Ng2319; + assign n8423 = Ng2217 & n5878 & Ng2185; + assign n8424 = Pg35 & n8423; + assign n8425 = ~Ng2208 | Ng2185; + assign n8426 = Ng2060 & n5916; + assign n8427 = Ng2028 & n8426; + assign n8428 = Pg35 & n8427; + assign n8429 = ~Ng2051 | Ng2028; + assign n8430 = Ng1926 & n5899 & Ng1894; + assign n8431 = Pg35 & n8430; + assign n8432 = ~Ng1917 | Ng1894; + assign n8433 = Ng1792 & n5941 & Ng1760; + assign n8434 = Pg35 & n8433; + assign n8435 = ~Ng1783 | Ng1760; + assign n8436 = Ng1657 & n5868 & Ng1624; + assign n8437 = Pg35 & n8436; + assign n8438 = ~Ng1648 | Ng1624; + assign n8439 = Ng996 & Ng1178 & ~Ng1189; + assign n8440 = ~n5884_1 | n7430; + assign n8441 = ~Pg35 | n8440; + assign n8442 = ~n5952 | n7461; + assign n8443 = ~Pg35 | n8442; + assign n8444 = ~n5940 | n7492; + assign n8445 = ~Pg35 | n8444; + assign n8446 = ~n5876 | n7523; + assign n8447 = ~Pg35 | n8446; + assign n8448 = \[4415] & Pg17577 & ~n8192; + assign n8449 = ~n4151_1 | ~n8448; + assign n8450 = ~Pg35 | n8449; + assign n8451 = ~n5927 | n7594; + assign n8452 = ~Pg35 | n8451; + assign n8453 = ~n5889 | n7623; + assign n8454 = ~Pg35 | n8453; + assign n8455 = Ng3639 | Ng3703; + assign n8456 = ~n5908 | n7653; + assign n8457 = ~Pg35 | n8456; + assign n8458 = Pg13272 & Ng1526 & ~Ng1514; + assign n8459 = Ng1514 & Ng1526 & Pg13272; + assign n8460 = Ng1514 & Pg13272 & ~Ng1526; + assign n8461 = Ng1183 & Pg13259 & ~Ng1171; + assign n8462 = Ng1183 & Ng1171 & Pg13259; + assign n8463 = Pg13259 & Ng1171 & ~Ng1183; + assign n8464 = n8131 | ~Ng822; + assign n8465 = Ng661 ^ Ng728; + assign n8466 = Ng655 ^ Ng718; + assign n8467 = n8122 & Ng671; + assign n8468 = ~Ng667 | Ng686; + assign n8469 = Ng513 | n7986 | ~Ng518; + assign n8470 = Ng482 & n5934; + assign n8471 = ~Ng4076 & ~n6261 & n6260_1 & ~Ng4087; + assign n8472 = n8471 & Ng4057 & ~Ng4064; + assign n8473 = n8471 & ~Ng4057 & Ng4064; + assign n8474 = n8181 | n8476 | n8477; + assign n8475 = n8474 & Pg35; + assign n8476 = ~Ng691 & (Ng411 | Ng424 | ~Ng417); + assign n8477 = Ng691 & (Ng499 | Ng518); + assign n8478 = n5091 & Pg35; + assign n8479 = n7853 & Pg35; + assign n8480 = Ng1442 & ~Ng1495; + assign n8481 = Ng1437 & n8460 & n8480; + assign n8482 = Ng1467 & n8459 & n8480; + assign n8483 = Ng1454 & n8458 & n8480; + assign n8484 = ~Pg35 | ~Ng1351; + assign n8485 = Ng1099 & ~Ng1152; + assign n8486 = Ng1094 & n8463 & n8485; + assign n8487 = Ng1124 & n8462 & n8485; + assign n8488 = Ng1111 & n8461 & n8485; + assign n8489 = ~Pg35 | ~Ng1008; + assign n8490 = ~Ng862 & Ng890 & ~Ng896; + assign n8491 = ~Pg35 | n8490; + assign n8492 = ~Pg35 | ~n8490; + assign n8493 = (Ng324 & ~Ng305) | (~Ng311 & (~Ng324 | ~Ng305)); + assign n8494 = Ng5084 & Ng5092; + assign n8495 = Ng1430 & Ng1548; + assign n8496 = Ng1484 & n5170 & n8480; + assign n8497 = Ng1087 & Ng1205; + assign n8498 = Ng1141 & n4887 & n8485; + assign n8499 = ~Pg35 | n8181; + assign n8500 = n8181 & Pg35; + assign n8501 = Pg8291 & Ng218; + assign n8502 = Pg17688 & Pg17778 & Pg14828 & Pg12470; + assign n8503 = ~Pg17760 | ~Pg17649 | ~Pg14779 | ~Pg12422; + assign n8504 = Pg17607 & Pg17739 & Pg14738 & Pg12350; + assign n8505 = Pg17580 & Pg17711 & Pg14694 & Pg12300; + assign n8506 = ~Pg17674 | ~Pg17519 | ~Pg14662 | ~Pg12238; + assign n8507 = ~Pg16775 | ~Pg16659 | ~Pg13966 | ~Pg11418; + assign n8508 = ~Pg16744 | ~Pg16627 | ~Pg13926 | ~Pg11388; + assign n8509 = ~Pg16718 | ~Pg16603 | ~Pg13895 | ~Pg11349; + assign n8510 = n8133 & Ng1554; + assign n8511 = n8135 & Ng1211; + assign n8512 = ~n7430 ^ n7431; + assign n8513 = n7461 ^ n7462; + assign n8514 = ~n7492 ^ n7493; + assign n8515 = ~n7523 ^ n7524; + assign n8516 = n8448 ^ n7552; + assign n8517 = ~n7594 ^ n7595; + assign n8518 = ~n7623 ^ n7624; + assign n8519 = ~n7653 ^ n7654; + assign n8520 = Ng1319 | n5091; + assign n8521 = ~Ng1448 ^ n8520; + assign n8522 = ~Ng1300 ^ n8520; + assign n8523 = ~Ng1472 ^ n8520; + assign n8524 = ~Ng1478 ^ n8520; + assign n8525 = ~n6128 | Ng976; + assign n8526 = ~Ng1105 ^ n8525; + assign n8527 = ~Ng956 ^ n8525; + assign n8528 = ~Ng1129 ^ n8525; + assign n8529 = ~Ng1135 ^ n8525; + assign n6560 = Ng4534 ^ n7840; + assign n4047_1 = Ng862 ^ n7894; + assign n1777 = Ng5084 ^ n7939; + assign n8533 = Ng246 ^ Ng269; + assign n8534 = Ng239 ^ Ng262; + assign n8535 = n5985 ^ n7980; + assign n6452 = Ng1430 ^ n8006; + assign n4627 = Ng1333 ^ n8008; + assign n1087_1 = Ng1087 ^ n8015; + assign n5768 = Ng990 ^ n8017; + assign n8540 = ~Pg9019 ^ Ng4291; + assign n8541 = ~Pg9019 ^ n8540; + assign n8542 = ~Pg8839 ^ Ng4281; + assign n8543 = ~Pg8839 ^ n8542; + assign n8544 = ~n9153 & (Pg35 | ~Ng2980); + assign n2483 = ~n8544; + assign n8546 = (Pg35 & n9162) | (~Ng4366 & (~Pg35 | n9162)); + assign n800_1 = ~n8546; + assign n8548 = ~n9164 & (Pg35 | ~Ng2955); + assign n3760 = ~n8548; + assign n8550 = ~n9166 & (Pg35 | ~Ng2941); + assign n1112_1 = ~n8550; + assign n8552 = ~n9168 & (Pg35 | ~Ng2927); + assign n1372_1 = ~n8552; + assign n8554 = ~n9169 & (Pg35 | ~Ng2965); + assign n2423 = ~n8554; + assign n8556 = ~n9171 & (Pg35 | ~Ng2917); + assign n4244 = ~n8556; + assign n8558 = ~n9172 & (Pg35 | ~Ng2902); + assign n4460 = ~n8558; + assign n8560 = ~n9174 & (Pg35 | ~Ng2970); + assign n2946_1 = ~n8560; + assign n8562 = Ng55 | Ng2980; + assign n8563 = (Pg35 & ~n8562) | (~Ng2886 & (~Pg35 | ~n8562)); + assign n1552_1 = ~n8563; + assign n8565 = ~Pg44 | Ng2890; + assign n8566 = (Pg35 & ~n8565) | (~Ng2873 & (~Pg35 | ~n8565)); + assign n5633 = ~n8566; + assign n8568 = Ng2946 | Ng2886; + assign n8569 = (Pg35 & ~n8568) | (~Ng2878 & (~Pg35 | ~n8568)); + assign n1752 = ~n8569; + assign n8571 = ~Pg91 | Ng2878; + assign n8572 = (Pg35 & ~n8571) | (~Ng2882 & (~Pg35 | ~n8571)); + assign n3832_1 = ~n8572; + assign n8574 = ~n9176 & (Pg35 | ~Ng2898); + assign n3871_1 = ~n8574; + assign n8576 = Ng2898 | ~n8215; + assign n8577 = (Pg35 & ~n8576) | (~Ng2864 & (~Pg35 | ~n8576)); + assign n1664_1 = ~n8577; + assign n8579 = Ng2864 | n8214; + assign n8580 = (Pg35 & ~n8579) | (~Ng2856 & (~Pg35 | ~n8579)); + assign n3975 = ~n8580; + assign n8582 = ~n9178 & (Pg35 | ~Ng2848); + assign n5653 = ~n8582; + assign n8584 = ~n9180 & (Pg35 | ~\[4433] ); + assign n2280_1 = ~n8584; + assign n8586 = Ng4242 | Ng4300; + assign n8587 = (~Pg35 & ~Ng4297) | (~n8586 & (Pg35 | ~Ng4297)); + assign n6646 = ~n8587; + assign n8589 = Ng4176 | Ng4072; + assign n8590 = (Pg35 & ~n8589) | (~Ng4172 & (~Pg35 | ~n8589)); + assign n4882 = ~n8590; + assign n8592 = Ng1283 | Ng1277; + assign n8593 = (Pg35 & ~n8592) | (~Ng1296 & (~Pg35 | ~n8592)); + assign n2111 = ~n8593; + assign n8595 = Ng933 | Ng939; + assign n8596 = (Pg35 & ~n8595) | (~Ng952 & (~Pg35 | ~n8595)); + assign n1247 = ~n8596; + assign n8598 = Ng534 | Ng301; + assign n8599 = (Pg35 & ~n8598) | (~Ng542 & (~Pg35 | ~n8598)); + assign n6536 = ~n8599; + assign n8601 = ~Ng691 | Ng546; + assign n8602 = (Pg35 & ~n8601) | (~Ng538 & (~Pg35 | ~n8601)); + assign n5956 = ~n8602; + assign n8604 = Ng199 | Ng222; + assign n8605 = (Pg35 & ~n8604) | (~\[4426] & (~Pg35 | ~n8604)); + assign n3675 = ~n8605; + assign n8607 = ~\[4435] | Ng550; + assign n8608 = (Pg35 & ~n8607) | (~Ng534 & (~Pg35 | ~n8607)); + assign n3927 = ~n8608; + assign n8610 = (~Pg35 & ~Ng37) | (~\[4433] & (Pg35 | ~Ng37)); + assign n6160 = ~n8610; + assign n4667_1 = ~n9188; + assign n5913_1 = ~n9189; + assign n8614 = (~Pg35 & ~Ng550) | (~\[4426] & (Pg35 | ~Ng550)); + assign n2793_1 = ~n8614; + assign n8616 = ~n9190 & (Ng4878 | n6193 | ~Ng4843); + assign n6260 = ~n8616; + assign n8618 = ~n9191 & (Ng4688 | n6198 | ~Ng4653); + assign n1868 = ~n8618; + assign n8620 = (Pg35 & n9192) | (~Ng4643 & (~Pg35 | n9192)); + assign n4249 = ~n8620; + assign n8622 = (n6254 & (Pg35 | ~Ng446)) | (~Pg35 & ~Ng446); + assign n3775 = ~n8622; + assign n8624 = (Pg35 & n9206) | (~Ng4961 & (~Pg35 | n9206)); + assign n4554 = ~n8624; + assign n8626 = (Pg35 & n9208) | (~Ng4950 & (~Pg35 | n9208)); + assign n3548 = ~n8626; + assign n8628 = (Pg35 & n9210) | (~Ng4894 & (~Pg35 | n9210)); + assign n2065_1 = ~n8628; + assign n8630 = (Pg35 & n9212) | (~Ng4771 & (~Pg35 | n9212)); + assign n4909_1 = ~n8630; + assign n8632 = (Pg35 & n9214) | (~Ng4760 & (~Pg35 | n9214)); + assign n1591_1 = ~n8632; + assign n8634 = (Pg35 & n9216) | (~Ng4704 & (~Pg35 | n9216)); + assign n6201_1 = ~n8634; + assign n8636 = (n8035 & Ng4358) | (~n8034 & (n8035 | ~Ng4358)); + assign n8637 = n9217 & (~Pg35 | n5968 | n8064); + assign n5613_1 = ~n8637; + assign n8639 = (Pg35 & n6291) | (~Ng4369 & (~Pg35 | n6291)); + assign n4953_1 = ~n8639; + assign n8641 = n9219 & (\[4437] | n5967 | ~Ng4581); + assign n8642 = (Pg35 & n9220) | (~Ng4492 & (~Pg35 | n9220)); + assign n6008 = ~n8642; + assign n8644 = n9221 & (n5967 | ~Ng4581 | Ng4575); + assign n8645 = (Pg35 & n9222) | (~Ng4564 & (~Pg35 | n9222)); + assign n1689_1 = ~n8645; + assign n8647 = n8263 & (n6338 | n8260 | ~Ng2643); + assign n8648 = n8647 & (~n9106 | (n5999 & ~Ng1589)); + assign n8649 = n8270 & (n6357 | n8267 | ~Ng2509); + assign n8650 = n8649 & ((n6001 & Ng1589) | ~n9107); + assign n8651 = n8277 & (n6375 | n8274 | ~Ng2375); + assign n8652 = n8651 & (~n9108 | (n6011 & ~Ng1589)); + assign n8653 = n8284 & (n6393 | n8281 | ~Ng2241); + assign n8654 = n8653 & ((n6007 & Ng1589) | ~n9109); + assign n8655 = n8292 & (n6412 | n8289 | ~Ng2084); + assign n8656 = n8655 & (~n9110 | (n6003 & ~Ng1246)); + assign n8657 = n8299 & (n6431 | n8296 | ~Ng1950); + assign n8658 = n8657 & ((n6005 & Ng1246) | ~n9111); + assign n8659 = n8306 & (n6450 | n8303 | ~Ng1816); + assign n8660 = n8659 & (~n9112 | (n5997 & ~Ng1246)); + assign n8661 = n8313 & (n6468 | n8310 | ~Ng1682); + assign n8662 = n8661 & ((n6009 & Ng1246) | ~n9113); + assign n8663 = (n5967 | Ng269) & (~Pg72 | Ng262); + assign n8664 = n8663 & (~Pg73 | (~Pg72 & Ng255)); + assign n8665 = (Pg35 & ~n8664) | (~\[4432] & (~Pg35 | ~n8664)); + assign n1317_1 = ~n8665; + assign n8667 = Ng239 | Pg73 | ~Pg72; + assign n8668 = Ng246 | n5967; + assign n8669 = (Ng232 & (~Pg72 | Ng225)) | (Pg72 & Ng225); + assign n8670 = n8667 & n8668 & (~Pg73 | n8669); + assign n8671 = (Pg35 & ~n8670) | (~Ng479 & (~Pg35 | ~n8670)); + assign n2247 = ~n8671; + assign n8673 = (n5876 & n8321) | (~Ng5644 & (~n5876 | n8321)); + assign n8674 = ~n9225 & (Pg35 | ~Ng5703); + assign n6086_1 = ~n8674; + assign n8676 = (Pg35 & ~n8644) | (~Ng4552 & (~Pg35 | ~n8644)); + assign n6413 = ~n8676; + assign n8678 = (Pg35 & ~n8641) | (~Ng4515 & (~Pg35 | ~n8641)); + assign n6340 = ~n8678; + assign n8680 = (Ng2667 & Ng2661) | (n8039 & (Ng2667 | ~Ng2661)); + assign n8681 = (~n8262 & ~Ng2661) | (~Ng2667 & (n8262 | ~Ng2661)); + assign n3623 = ~n8681; + assign n8683 = (~n8262 & ~Ng2643) | (~Ng2648 & (n8262 | ~Ng2643)); + assign n3538 = ~n8683; + assign n8685 = (n8040 & (~Ng2533 | Ng2527)) | (Ng2533 & Ng2527); + assign n8686 = (~n8269 & ~Ng2527) | (~Ng2533 & (n8269 | ~Ng2527)); + assign n6022_1 = ~n8686; + assign n8688 = (~n8269 & ~Ng2509) | (~Ng2514 & (n8269 | ~Ng2509)); + assign n2590_1 = ~n8688; + assign n8690 = (Ng2399 & Ng2393) | (n8041 & (Ng2399 | ~Ng2393)); + assign n8691 = (~n8276 & ~Ng2393) | (~Ng2399 & (n8276 | ~Ng2393)); + assign n1636_1 = ~n8691; + assign n8693 = (~n8276 & ~Ng2375) | (~Ng2380 & (n8276 | ~Ng2375)); + assign n3360 = ~n8693; + assign n8695 = (Ng2265 & Ng2259) | (n8042 & (Ng2265 | ~Ng2259)); + assign n8696 = (~n8283 & ~Ng2259) | (~Ng2265 & (n8283 | ~Ng2259)); + assign n4480 = ~n8696; + assign n8698 = (~n8283 & ~Ng2241) | (~Ng2246 & (n8283 | ~Ng2241)); + assign n5111 = ~n8698; + assign n8700 = (n8043 & (~Ng2108 | Ng2102)) | (Ng2108 & Ng2102); + assign n8701 = (~n8291 & ~Ng2102) | (~Ng2108 & (n8291 | ~Ng2102)); + assign n5261 = ~n8701; + assign n8703 = (~n8291 & ~Ng2084) | (~Ng2089 & (n8291 | ~Ng2084)); + assign n1026_1 = ~n8703; + assign n8705 = (n8044 & (~Ng1974 | Ng1968)) | (Ng1974 & Ng1968); + assign n8706 = (~n8298 & ~Ng1968) | (~Ng1974 & (n8298 | ~Ng1968)); + assign n4509_1 = ~n8706; + assign n8708 = (~n8298 & ~Ng1950) | (~Ng1955 & (n8298 | ~Ng1950)); + assign n4164 = ~n8708; + assign n8710 = (Ng1840 & Ng1834) | (n8045 & (Ng1840 | ~Ng1834)); + assign n8711 = (~n8305 & ~Ng1834) | (~Ng1840 & (n8305 | ~Ng1834)); + assign n3411 = ~n8711; + assign n8713 = (~n8305 & ~Ng1816) | (~Ng1821 & (n8305 | ~Ng1816)); + assign n5366_1 = ~n8713; + assign n8715 = (Ng1706 & Ng1700) | (n8046 & (Ng1706 | ~Ng1700)); + assign n8716 = (~n8312 & ~Ng1700) | (~Ng1706 & (n8312 | ~Ng1700)); + assign n1616 = ~n8716; + assign n8718 = (~n8312 & ~Ng1682) | (~Ng1687 & (n8312 | ~Ng1682)); + assign n6012 = ~n8718; + assign n8720 = n9228 & (~Pg35 | n8245 | ~Ng142); + assign n1826_1 = ~n8720; + assign n8722 = (n8354 & (Ng5041 | n8356)) | (~Ng5041 & n8356); + assign n8723 = (n8353 & (Ng5033 | n8355)) | (~Ng5033 & n8355); + assign n8724 = ~n9238 & (Ng283 | n7834 | ~Ng287); + assign n3812_1 = ~n8724; + assign n8726 = (n7168 & (Pg35 | ~Ng4122)) | (~Pg35 & ~Ng4122); + assign n1201_1 = ~n8726; + assign n8728 = (~n7338 & ~Ng2681) | (~Ng2675 & (n7338 | ~Ng2681)); + assign n6017 = ~n8728; + assign n8730 = (~n7343 & ~Ng2547) | (~Ng2541 & (n7343 | ~Ng2547)); + assign n712 = ~n8730; + assign n8732 = (~n7348 & ~Ng2413) | (~Ng2407 & (n7348 | ~Ng2413)); + assign n6056 = ~n8732; + assign n8734 = (~n7353 & ~Ng2279) | (~Ng2273 & (n7353 | ~Ng2279)); + assign n3047 = ~n8734; + assign n8736 = (~n7358 & ~Ng2122) | (~Ng2116 & (n7358 | ~Ng2122)); + assign n1844_1 = ~n8736; + assign n8738 = (~n7363 & ~Ng1988) | (~Ng1982 & (n7363 | ~Ng1988)); + assign n6442 = ~n8738; + assign n8740 = (~n7368 & ~Ng1854) | (~Ng1848 & (n7368 | ~Ng1854)); + assign n4379_1 = ~n8740; + assign n8742 = (~n7373 & ~Ng1720) | (~Ng1714 & (n7373 | ~Ng1720)); + assign n5850_1 = ~n8742; + assign n8744 = (n8048 & Ng1413) | (~n8047 & (n8048 | ~Ng1413)); + assign n8745 = n9275 & (~Pg35 | n5559 | n8116); + assign n5681_1 = ~n8745; + assign n8747 = (n8050 & Ng1070) | (~n8049 & (n8050 | ~Ng1070)); + assign n8748 = n9276 & (~Pg35 | n4474 | n8118); + assign n4622 = ~n8748; + assign n8750 = (~n7407 & ~Ng6519) | (~Ng6513 & (n7407 | ~Ng6519)); + assign n2560_1 = ~n8750; + assign n8752 = (~n7438 & ~Ng6173) | (~Ng6167 & (n7438 | ~Ng6173)); + assign n4452 = ~n8752; + assign n8754 = (~n7469 & ~Ng5827) | (~Ng5821 & (n7469 | ~Ng5827)); + assign n3340_1 = ~n8754; + assign n8756 = (~n7500 & ~Ng5481) | (~Ng5475 & (n7500 | ~Ng5481)); + assign n5806 = ~n8756; + assign n8758 = (~n7530 & ~Ng5134) | (~Ng5128 & (n7530 | ~Ng5134)); + assign n1327_1 = ~n8758; + assign n8760 = ~n7559 & n8211 & (n8119 | n8317); + assign n8761 = ~n7564 & n8209 & (n8120 | n8316); + assign n8762 = (~n7571 & ~Ng3827) | (~Ng3821 & (n7571 | ~Ng3827)); + assign n3586_1 = ~n8762; + assign n8764 = (~n7602 & ~Ng3476) | (~Ng3470 & (n7602 | ~Ng3476)); + assign n2178 = ~n8764; + assign n8766 = (~n7631 & ~Ng3125) | (~Ng3119 & (n7631 | ~Ng3125)); + assign n6395 = ~n8766; + assign n8768 = ~n9315 & (Pg35 | ~Ng1478); + assign n1532_1 = ~n8768; + assign n8770 = ~Ng1489 & ~Ng1442; + assign n8771 = n8522 & n5170 & (Ng1484 | n8770); + assign n8772 = ~n9317 & (Pg35 | ~Ng1448); + assign n2530 = ~n8772; + assign n8774 = ~n9319 & (Pg35 | ~Ng1442); + assign n1433_1 = ~n8774; + assign n8776 = ~n9321 & (Pg35 | ~Ng1135); + assign n6114_1 = ~n8776; + assign n8778 = ~Ng1146 & ~Ng1099; + assign n8779 = n8527 & n4887 & (Ng1141 | n8778); + assign n8780 = ~n9323 & (Pg35 | ~Ng1105); + assign n4549 = ~n8780; + assign n8782 = ~n9325 & (Pg35 | ~Ng1099); + assign n6502 = ~n8782; + assign n8784 = n9331 & (~Pg35 | n8360 | n8362); + assign n5411_1 = ~n8784; + assign n8786 = n9332 & (~Pg35 | n8361 | n8363); + assign n5376_1 = ~n8786; + assign n8788 = n9333 & (~Ng4521 | (Pg35 & n9334)); + assign n4099 = ~n8788; + assign n8790 = n9335 & (Pg35 | ~Ng2841); + assign n5753 = ~n8790; + assign n8792 = (~n7797 & ~Ng4145) | (~Ng4112 & (n7797 | ~Ng4145)); + assign n5481_1 = ~n8792; + assign n8794 = (~Ng661 & ~n8475) | (~Ng728 & (~Ng661 | n8475)); + assign n6427 = ~n8794; + assign n8796 = (~Ng718 & ~n8475) | (~Ng661 & (~Ng718 | n8475)); + assign n3106 = ~n8796; + assign n8798 = (~Ng655 & ~n8475) | (~Ng718 & (~Ng655 | n8475)); + assign n1287_1 = ~n8798; + assign n8800 = (~Ng650 & ~n8475) | (~Ng655 & (~Ng650 | n8475)); + assign n3439 = ~n8800; + assign n8802 = (Pg35 & n8124) | (~\[4435] & (~Pg35 | n8124)); + assign n6531 = ~n8802; + assign n8804 = (~Ng645 & ~n8475) | (~Ng681 & (~Ng645 | n8475)); + assign n1732_1 = ~n8804; + assign n8806 = (n7839 & (Pg35 | ~Ng4512)) | (~Pg35 & ~Ng4512); + assign n1036_1 = ~n8806; + assign n8808 = (~Pg35 & ~Ng4459) | (~Ng4473 & (Pg35 | ~Ng4459)); + assign n2570 = ~n8808; + assign n8810 = (Pg35 & n9339) | (~Ng4462 & (~Pg35 | n9339)); + assign n3720_1 = ~n8810; + assign n8812 = (~Pg35 & ~Ng4558) | (~Pg6749 & (Pg35 | ~Ng4558)); + assign n4075 = ~n8812; + assign n8814 = (~Pg35 & ~Ng4561) | (~Pg6750 & (Pg35 | ~Ng4561)); + assign n2803_1 = ~n8814; + assign n8816 = (~Pg35 & ~Ng4555) | (~Pg6748 & (Pg35 | ~Ng4555)); + assign n1224_1 = ~n8816; + assign n8818 = (~Pg35 & ~Ng4489) | (~Pg6750 & (Pg35 | ~Ng4489)); + assign n1257_1 = ~n8818; + assign n8820 = (~Pg35 & ~Ng4486) | (~Pg6749 & (Pg35 | ~Ng4486)); + assign n4504 = ~n8820; + assign n8822 = (~Pg35 & ~Ng4483) | (~Pg6748 & (Pg35 | ~Ng4483)); + assign n2354_1 = ~n8822; + assign n8824 = (n9241 & (Pg35 | ~Ng4153)) | (~Pg35 & ~Ng4153); + assign n1925_1 = ~n8824; + assign n8826 = (Pg35 & n9240) | (~Ng4104 & (~Pg35 | n9240)); + assign n5864 = ~n8826; + assign n8828 = n9341 & (Pg35 | ~Ng2841); + assign n4211_1 = ~n8828; + assign n8830 = (n8128 & (Pg35 | ~Ng1532)) | (~Pg35 & ~Ng1532); + assign n5558_1 = ~n8830; + assign n8832 = n9342 & (~Pg35 | n8129 | Ng1322); + assign n3792 = ~n8832; + assign n8834 = (n8130 & (Pg35 | ~Ng1189)) | (~Pg35 & ~Ng1189); + assign n5898 = ~n8834; + assign n8836 = (Pg35 & n9343) | (~Ng890 & (~Pg35 | n9343)); + assign n3490 = ~n8836; + assign n8838 = n9344 & (Ng812 | (n8022 & Ng843)); + assign n8839 = (~Ng732 & n9345) | (~Ng753 & (~Ng732 | ~n9345)); + assign n1537_1 = ~n8839; + assign n8841 = n8468 & ~n9346 & (~Ng528 | n8469); + assign n8842 = (Pg35 & ~n8841) | (~Ng518 & (~Pg35 | ~n8841)); + assign n2232_1 = ~n8842; + assign n8844 = Pg35 & (Ng333 | Ng355); + assign n8845 = (~Ng351 & ~n8844) | (Pg35 & (Ng351 | ~n8844)); + assign n1979_1 = ~n8845; + assign n8847 = n9347 & (Pg35 | ~Ng347); + assign n1742_1 = ~n8847; + assign n8849 = (Ng347 & (Pg35 | ~Ng333)) | (~Pg35 & ~Ng333); + assign n3558 = ~n8849; + assign n8851 = n9348 & (Pg35 | ~\[4436] ); + assign n5151_1 = ~n8851; + assign n8853 = (Pg35 & ~Ng316) | (~\[4431] & (~Pg35 | ~Ng316)); + assign n3651_1 = ~n8853; + assign n8855 = (n7912 & (Pg35 | ~Ng336)) | (~Pg35 & ~Ng336); + assign n6027 = ~n8855; + assign n8857 = (n7918 & (Pg35 | ~Ng316)) | (~Pg35 & ~Ng316); + assign n6275 = ~n8857; + assign n8859 = (~Pg35 & ~Ng305) | (~Pg6744 & (Pg35 | ~Ng305)); + assign n895_1 = ~n8859; + assign n8861 = (n8381 & ~Ng6505) | (~Ng6541 & (~n8381 | ~Ng6505)); + assign n5136_1 = ~n8861; + assign n8863 = (Ng6533 & Ng6527) | (n8051 & (Ng6533 | ~Ng6527)); + assign n8864 = (~n8381 & ~Ng6527) | (~Ng6533 & (n8381 | ~Ng6527)); + assign n5541_1 = ~n8864; + assign n8866 = ~Pg9817 & (Ng6444 | (Pg9743 & ~Ng6494)); + assign n8867 = (~Pg35 & ~Ng6494) | (~n8866 & (Pg35 | ~Ng6494)); + assign n3755_1 = ~n8867; + assign n8869 = (Pg35 & ~Ng6727) | (~Ng6444 & (~Pg35 | ~Ng6727)); + assign n2306 = ~n8869; + assign n8871 = (n8386 & ~Ng6159) | (~Ng6195 & (~n8386 | ~Ng6159)); + assign n2007_1 = ~n8871; + assign n8873 = (Ng6187 & Ng6181) | (n8052 & (Ng6187 | ~Ng6181)); + assign n8874 = (~n8386 & ~Ng6181) | (~Ng6187 & (n8386 | ~Ng6181)); + assign n1893_1 = ~n8874; + assign n8876 = ~Pg9741 & (Ng6098 | (Pg9682 & ~Ng6148)); + assign n8877 = (~Pg35 & ~Ng6148) | (~n8876 & (Pg35 | ~Ng6148)); + assign n4187 = ~n8877; + assign n8879 = (Pg35 & ~Ng6381) | (~Ng6098 & (~Pg35 | ~Ng6381)); + assign n1068_1 = ~n8879; + assign n8881 = (n8390 & ~Ng5813) | (~Ng5849 & (~n8390 | ~Ng5813)); + assign n741_1 = ~n8881; + assign n8883 = (Ng5841 & Ng5835) | (n8053 & (Ng5841 | ~Ng5835)); + assign n8884 = (~n8390 & ~Ng5835) | (~Ng5841 & (n8390 | ~Ng5835)); + assign n6289 = ~n8884; + assign n8886 = ~Pg9680 & (Ng5752 | (Pg9617 & ~Ng5802)); + assign n8887 = (~Pg35 & ~Ng5802) | (~n8886 & (Pg35 | ~Ng5802)); + assign n2408_1 = ~n8887; + assign n8889 = (Pg35 & ~Ng6035) | (~Ng5752 & (~Pg35 | ~Ng6035)); + assign n2328_1 = ~n8889; + assign n8891 = (n8394 & ~Ng5467) | (~Ng5503 & (~n8394 | ~Ng5467)); + assign n3416 = ~n8891; + assign n8893 = (Ng5495 & Ng5489) | (n8054 & (Ng5495 | ~Ng5489)); + assign n8894 = (~n8394 & ~Ng5489) | (~Ng5495 & (n8394 | ~Ng5489)); + assign n2379_1 = ~n8894; + assign n8896 = ~Pg9615 & (Ng5406 | (Pg9555 & ~Ng5456)); + assign n8897 = (~Pg35 & ~Ng5456) | (~n8896 & (Pg35 | ~Ng5456)); + assign n2984_1 = ~n8897; + assign n8899 = (Pg35 & ~Ng5689) | (~Ng5406 & (~Pg35 | ~Ng5689)); + assign n2848_1 = ~n8899; + assign n8901 = (~n7934 & ~Ng5120) | (~Ng5156 & (n7934 | ~Ng5120)); + assign n4574 = ~n8901; + assign n8903 = (Ng5148 & Ng5142) | (n8055 & (Ng5148 | ~Ng5142)); + assign n8904 = (n7934 & ~Ng5142) | (~Ng5148 & (~n7934 | ~Ng5142)); + assign n6565 = ~n8904; + assign n8906 = ~Pg9497 & (Ng5022 | (Pg9553 & ~Ng5112)); + assign n8907 = (~Pg35 & ~Ng5112) | (~n8906 & (Pg35 | ~Ng5112)); + assign n2285_1 = ~n8907; + assign n8909 = ~Pg9553 & (Ng5062 | (Pg9497 & ~Ng5109)); + assign n8910 = (~Pg35 & ~Ng5109) | (~n8909 & (Pg35 | ~Ng5109)); + assign n5175_1 = ~n8910; + assign n8912 = (~Pg35 & ~Ng5062) | (~\[4415] & (Pg35 | ~Ng5062)); + assign n3009_1 = ~n8912; + assign n8914 = (Ng5069 & Ng5084) | (Ng5073 & (Ng5069 | ~Ng5084)); + assign n8915 = ~n9351 & (n7566 | ~Ng4057 | Ng4064); + assign n6250 = ~n8915; + assign n8917 = (n8401 & ~Ng3813) | (~Ng3849 & (~n8401 | ~Ng3813)); + assign n1072_1 = ~n8917; + assign n8919 = (Ng3841 & Ng3835) | (n8056 & (Ng3841 | ~Ng3835)); + assign n8920 = (~n8401 & ~Ng3835) | (~Ng3841 & (n8401 | ~Ng3835)); + assign n6507 = ~n8920; + assign n8922 = ~Pg8398 & (Ng3752 | (Pg8344 & ~Ng3802)); + assign n8923 = (~Pg35 & ~Ng3802) | (~n8922 & (Pg35 | ~Ng3802)); + assign n2743 = ~n8923; + assign n8925 = (Pg35 & ~Ng4040) | (~Ng3752 & (~Pg35 | ~Ng4040)); + assign n2668_1 = ~n8925; + assign n8927 = (n8405 & ~Ng3462) | (~Ng3498 & (~n8405 | ~Ng3462)); + assign n5456_1 = ~n8927; + assign n8929 = (Ng3490 & Ng3484) | (n8057 & (Ng3490 | ~Ng3484)); + assign n8930 = (~n8405 & ~Ng3484) | (~Ng3490 & (n8405 | ~Ng3484)); + assign n815_1 = ~n8930; + assign n8932 = ~Pg8342 & (Ng3401 | (Pg8279 & ~Ng3451)); + assign n8933 = (~Pg35 & ~Ng3451) | (~n8932 & (Pg35 | ~Ng3451)); + assign n6147 = ~n8933; + assign n8935 = (Pg35 & ~Ng3689) | (~Ng3401 & (~Pg35 | ~Ng3689)); + assign n6634 = ~n8935; + assign n8937 = (n8409 & ~Ng3111) | (~Ng3147 & (~n8409 | ~Ng3111)); + assign n1232_1 = ~n8937; + assign n8939 = (Ng3139 & Ng3133) | (n8058 & (Ng3139 | ~Ng3133)); + assign n8940 = (~n8409 & ~Ng3133) | (~Ng3139 & (n8409 | ~Ng3133)); + assign n2242_1 = ~n8940; + assign n8942 = ~Pg8277 & (Ng3050 | (Pg8215 & ~Ng3100)); + assign n8943 = (~Pg35 & ~Ng3100) | (~n8942 & (Pg35 | ~Ng3100)); + assign n1831_1 = ~n8943; + assign n8945 = (Pg35 & ~Ng3338) | (~Ng3050 & (~Pg35 | ~Ng3338)); + assign n5971_1 = ~n8945; + assign n8947 = n9352 & (~Pg35 | n8134 | n8510); + assign n6211 = ~n8947; + assign n8949 = ~n8510 & ((n8133 & Ng1559) | Ng1554); + assign n8950 = (Pg35 & ~n8949) | (~Ng1559 & (~Pg35 | ~n8949)); + assign n5705_1 = ~n8950; + assign n8952 = (Pg35 & n9354) | (~Ng1521 & (~Pg35 | n9354)); + assign n5446_1 = ~n8952; + assign n8954 = n9357 & (~Pg35 | n8136 | n8511); + assign n2275 = ~n8954; + assign n8956 = ~n8511 & ((n8135 & Ng1216) | Ng1211); + assign n8957 = (Pg35 & ~n8956) | (~Ng1216 & (~Pg35 | ~n8956)); + assign n5326_1 = ~n8957; + assign n8959 = (Pg35 & n9359) | (~Ng1178 & (~Pg35 | n9359)); + assign n2493 = ~n8959; + assign n8961 = (~n8027 & ~Ng817) | (~n7758 & (~n8027 | Ng817)); + assign n8962 = (n7983 & ~Ng686) | (~Ng667 & (~n7983 | ~Ng686)); + assign n4311_1 = ~n8962; + assign n8964 = (n8500 & ~Ng452) | (~Ng460 & (~n8500 | ~Ng452)); + assign n726_1 = ~n8964; + assign n8966 = (~Ng174 & n8500) | (~Ng182 & (~Ng174 | ~n8500)); + assign n1969_1 = ~n8966; + assign n8968 = (~Ng168 & n8500) | (~Ng174 & (~Ng168 | ~n8500)); + assign n2956_1 = ~n8968; + assign n8970 = (Pg35 & n9362) | (~Ng358 & (~Pg35 | n9362)); + assign n5568_1 = ~n8970; + assign n8972 = (Pg35 & n9363) | (~Ng370 & (~Pg35 | n9363)); + assign n5874 = ~n8972; + assign n8974 = (n9365 & (Pg35 | ~Ng191)) | (~Pg35 & ~Ng191); + assign n4707_1 = ~n8974; + assign n8976 = (Pg35 & n9367) | (~Ng222 & (~Pg35 | n9367)); + assign n4138_1 = ~n8976; + assign n8978 = (Pg35 & Ng218) | (~Ng209 & (~Pg35 | Ng218)); + assign n3267 = ~n8978; + assign n8980 = n9368 & (~Pg35 | ~n5006 | Ng6736); + assign n5441_1 = ~n8980; + assign n8982 = (Pg35 & n9369) | (~Ng6723 & (~Pg35 | n9369)); + assign n1557_1 = ~n8982; + assign n8984 = n9370 & (~Pg35 | ~n5604 | Ng6390); + assign n1792 = ~n8984; + assign n8986 = (Pg35 & n9371) | (~Ng6377 & (~Pg35 | n9371)); + assign n4904 = ~n8986; + assign n8988 = n9372 & (~Pg35 | ~n5069_1 | Ng6044); + assign n2999_1 = ~n8988; + assign n8990 = (Pg35 & n9373) | (~Ng6031 & (~Pg35 | n9373)); + assign n6240 = ~n8990; + assign n8992 = n9374 & (~Pg35 | ~n5837 | Ng5698); + assign n5573_1 = ~n8992; + assign n8994 = (Pg35 & n9375) | (~Ng5685 & (~Pg35 | n9375)); + assign n3215 = ~n8994; + assign n8996 = n9376 & (~Pg35 | ~n5715 | Ng5352); + assign n6575 = ~n8996; + assign n8998 = (Pg35 & n9377) | (~Ng5339 & (~Pg35 | n9377)); + assign n1307_1 = ~n8998; + assign n9000 = (Pg35 & n9378) | (~Ng4308 & (~Pg35 | n9378)); + assign n2212 = ~n9000; + assign n9002 = (Pg35 & ~n9383) | (~Ng4235 & (~Pg35 | ~n9383)); + assign n4539 = ~n9002; + assign n9004 = n9384 & (~Pg35 | ~n4631_1 | Ng4049); + assign n2525 = ~n9004; + assign n9006 = (Pg35 & n9385) | (~Ng4031 & (~Pg35 | n9385)); + assign n707_1 = ~n9006; + assign n9008 = n9386 & (~Pg35 | ~n4267 | Ng3698); + assign n5801 = ~n9008; + assign n9010 = (Pg35 & n9387) | (~Ng3680 & (~Pg35 | n9387)); + assign n3476_1 = ~n9010; + assign n9012 = n9388 & (~Pg35 | ~n5184 | Ng3347); + assign n1669_1 = ~n9012; + assign n9014 = (Pg35 & n9389) | (~Ng3329 & (~Pg35 | n9389)); + assign n2979_1 = ~n9014; + assign n9016 = (Pg35 & ~Ng496) | (~Ng1554 & (~Pg35 | ~Ng496)); + assign n6052_1 = ~n9016; + assign n9018 = (Pg35 & n9391) | (~Ng1339 & (~Pg35 | n9391)); + assign n944_1 = ~n9018; + assign n9020 = (Pg35 & n9392) | (~Ng1306 & (~Pg35 | n9392)); + assign n1572_1 = ~n9020; + assign n9022 = (Pg35 & n9393) | (~Ng1526 & (~Pg35 | n9393)); + assign n6600 = ~n9022; + assign n9024 = (n7731 & ~Ng1495) | (~Ng1442 & (~n7731 | ~Ng1495)); + assign n1485_1 = ~n9024; + assign n9026 = (~n7731 & ~Ng1495) | (~Ng1489 & (n7731 | ~Ng1495)); + assign n1428_1 = ~n9026; + assign n9028 = (~Pg35 & ~Ng1211) | (~\[4432] & (Pg35 | ~Ng1211)); + assign n2169_1 = ~n9028; + assign n9030 = (Pg35 & n9395) | (~Ng996 & (~Pg35 | n9395)); + assign n3515 = ~n9030; + assign n9032 = (Pg35 & n9396) | (~Ng962 & (~Pg35 | n9396)); + assign n1596_1 = ~n9032; + assign n9034 = (Pg35 & n9397) | (~Ng1183 & (~Pg35 | n9397)); + assign n1277_1 = ~n9034; + assign n9036 = (n7735 & ~Ng1152) | (~Ng1099 & (~n7735 | ~Ng1152)); + assign n1122_1 = ~n9036; + assign n9038 = (~n7735 & ~Ng1152) | (~Ng1146 & (n7735 | ~Ng1152)); + assign n5298 = ~n9038; + assign n9040 = (n7758 & ~Ng854) | (~Ng847 & (~n7758 | ~Ng854)); + assign n785_1 = ~n9040; + assign n9042 = (~n7758 & ~Ng441) | (~Ng475 & (n7758 | ~Ng441)); + assign n3004_1 = ~n9042; + assign n9044 = (n7758 & ~Ng441) | (~Ng437 & (~n7758 | ~Ng441)); + assign n1737_1 = ~n9044; + assign n9046 = (~n7758 & ~Ng429) | (~Ng433 & (n7758 | ~Ng429)); + assign n4777_1 = ~n9046; + assign n9048 = (n7758 & ~Ng429) | (~Ng401 & (~n7758 | ~Ng429)); + assign n2994_1 = ~n9048; + assign n9050 = (~n7758 & ~Ng424) | (~Ng411 & (n7758 | ~Ng424)); + assign n5344_1 = ~n9050; + assign n9052 = (~n7758 & ~Ng405) | (~Ng392 & (n7758 | ~Ng405)); + assign n3223_1 = ~n9052; + assign n9054 = (Pg35 & n9401) | (~Ng2946 & (~Pg35 | n9401)); + assign n5884 = ~n9054; + assign n9056 = (Pg35 & n9402) | (~Ng4239 & (~Pg35 | n9402)); + assign n3788_1 = ~n9056; + assign n9058 = (n8540 & (Pg35 | ~Ng4291)) | (~Pg35 & ~Ng4291); + assign n4272_1 = ~n9058; + assign n9060 = (n8541 & (Pg35 | ~Ng4284)) | (~Pg35 & ~Ng4284); + assign n5007 = ~n9060; + assign n9062 = (n8542 & (Pg35 | ~Ng4281)) | (~Pg35 & ~Ng4281); + assign n6512 = ~n9062; + assign n9064 = (Pg35 & n8543) | (~Ng4245 & (~Pg35 | n8543)); + assign n4160_1 = ~n9064; + assign n9066 = (Pg35 & Ng4239) | (~Ng4273 & (~Pg35 | Ng4239)); + assign n6522 = ~n9066; + assign n9068 = (Pg35 & n9379) | (~Ng4180 & (~Pg35 | n9379)); + assign n2384_1 = ~n9068; + assign n9070 = n6045 | ~Ng2882; + assign n9071 = ~Ng534 | n8159; + assign n9072 = (n8153 | ~Ng16) & (n6020 | n8142); + assign n9073 = n6015 | ~Ng790; + assign n9074 = ~n5992 & n9073 & (n6027_1 | ~Ng749); + assign n9075 = (n6063 | ~Ng608) & (n8159 | Ng550); + assign n9076 = n9075 & (~Ng572 | n8157); + assign n9077 = (n8153 | ~Ng50) & (n6046 | n8142); + assign n9078 = (n6045 | ~Ng2886) & (~Ng2980 | n8174); + assign n9079 = n6063 | ~Ng604; + assign n9080 = (n8153 | ~Ng51) & (n6032 | n8142); + assign n9081 = (n8161 | ~Ng1283) & (n8171 | ~Ng2138); + assign n9082 = n6063 | ~Ng599; + assign n9083 = ~n5992 & n9082 & (n8157 | ~Ng562); + assign n9084 = (n6015 | ~Ng781) & (n6027_1 | ~Ng739); + assign n9085 = n9084 & (n8159 | ~Ng199); + assign n9086 = (n8153 | ~Ng52) & (n6038 | n8142); + assign n9087 = (n6045 | ~Ng2848) & (n6056_1 | ~Ng2902); + assign n9088 = (n6031 | ~Ng2907) & (n6080 | ~Ng2844); + assign n9089 = (~Ng1300 | n8175) & (~Ng956 | n8176); + assign n9090 = (Pg35 | n8158) & (n6027_1 | ~Ng772); + assign n9091 = (n6063 | ~Ng626) & (~Ng590 | n8157); + assign n9092 = (~Ng1472 | n8175) & (~Ng1129 | n8176); + assign n9093 = n6015 | ~Ng554; + assign n9094 = (~Ng1448 | n8175) & (~Ng1105 | n8176); + assign n9095 = (n8153 | ~Ng8) & (n8171 | ~Ng5507); + assign n9096 = n6045 | ~Ng2898; + assign n9097 = n6063 | ~Ng617; + assign n9098 = (~Ng1478 | n8175) & (~Ng1135 | n8176); + assign n9099 = (n8153 | ~Ng48) & (n8168 | ~Ng4912); + assign n9100 = (n8188 | n8189) & (n8190 | n7619); + assign n9101 = (n5730 | n7578) & (n8191 | n7414); + assign n9102 = (n7404 | ~n7942) & (n7466 | ~n8218); + assign n9103 = (n7599 | ~n8220) & (n6261 | n7527); + assign n9104 = (n7435 | ~n8218) & (n7628 | ~n7942); + assign n9105 = (n7568 | ~n8220) & (n6261 | n7497); + assign n9106 = ~n5923 & (n8260 | ~Ng2643); + assign n9107 = ~n5942 & (n8267 | ~Ng2509); + assign n9108 = ~n5956_1 & (n8274 | ~Ng2375); + assign n9109 = ~n5953 & (n8281 | ~Ng2241); + assign n9110 = ~n5944 & (n8289 | ~Ng2084); + assign n9111 = ~n5948 & (n8296 | ~Ng1950); + assign n9112 = ~n5898_1 & (n8303 | ~Ng1816); + assign n9113 = ~n5954 & (n8310 | ~Ng1682); + assign n9114 = ~n6268 & n8330; + assign n9115 = Pg35 & (~n6634_1 | (~Ng1373 & n8333)); + assign n9116 = Pg35 & (~n6641 | (~Ng1030 & n8339)); + assign n9117 = ~n8102 & (n6882 | (~n5880 & ~n8105)); + assign n9118 = (Ng2236 | n8373) & (Ng2370 | n7957); + assign n9119 = (n7957 | ~Ng2807) & (~Ng2803 | n8373); + assign n9120 = (Ng1945 | n8370) & (Ng2079 | n8255); + assign n9121 = (n7957 | ~Ng2775) & (~Ng2771 | n8373); + assign n9122 = ~Ng6645 | ~Pg17688 | n7423; + assign n9123 = ~Ng6653 | ~Pg17688 | n7426; + assign n9124 = ~Ng6283 | ~Pg17760 | n7445; + assign n9125 = ~Ng6275 | ~Pg14779 | n7457; + assign n9126 = ~Ng5953 | ~Pg17607 | n7485; + assign n9127 = ~Ng5961 | ~Pg17607 | n7488; + assign n9128 = ~Ng5607 | ~Pg17580 | n7516; + assign n9129 = ~Ng5615 | ~Pg17580 | n7519; + assign n9130 = ~Ng5260 | ~Pg17519 | n7545; + assign n9131 = ~Ng5252 | ~Pg17674 | n6516; + assign n9132 = (~Ng4836 | ~Ng5011) & (~Ng4864 | Ng3333); + assign n9133 = (~Ng4871 | ~Ng3684) & (~Ng4878 | Ng4035); + assign n9134 = (~\[4427] | ~Ng4646) & (~Ng4674 | Ng4821); + assign n9135 = (~Ng4681 | ~Ng4831) & (~Ng4688 | Ng4826); + assign n9136 = ~Ng3953 | ~Pg16659 | n7587; + assign n9137 = ~Ng3945 | ~Pg16775 | n6525; + assign n9138 = ~Ng3602 | ~Pg16627 | n8455; + assign n9139 = ~Ng3578 | ~Pg13926 | n8455; + assign n9140 = ~Ng3235 | ~Pg16718 | n8189; + assign n9141 = ~Ng3227 | ~Pg13895 | n7649; + assign n9142 = (n6537 & (n8189 | Ng3347)) | (n8189 & ~Ng3347); + assign n9143 = (n7638 & (~Ng3343 | n7649)) | (Ng3343 & n7649); + assign n9144 = ~n8328 & (Ng4939 | (n9142 & n9143)); + assign n9145 = (~Ng5694 & n7519) | (n7516 & (Ng5694 | n7519)); + assign n9146 = (n8321 & Ng5698) | (n7507 & (n8321 | ~Ng5698)); + assign n9147 = ~n8322 & (Ng4749 | (n9145 & n9146)); + assign n9148 = ~Ng979 & (~n7888 | ~Ng1061 | ~Ng1052); + assign n9149 = Ng832 & (~n7758 | (Pg35 & ~Ng817)); + assign n9150 = (~Pg35 | Pg19357) & (~Ng1395 | n8005); + assign n9151 = Pg17316 | Pg17400 | Pg17291; + assign n9152 = (n8014 | ~Ng1052) & (~Pg35 | Pg19334); + assign n9153 = Pg35 & (n6089 | Ng2984); + assign n9154 = Ng753 | Ng655 | Ng718; + assign n9155 = ~Ng4332 & (n5967 | (Pg90 & ~Ng2994)); + assign n9156 = ~Ng4322 & (n9155 | (Ng4332 & Ng4311)); + assign n9157 = ~Ng4332 & Ng4322 & (n5967 | ~Ng4515); + assign n9158 = Ng4608 | ~Ng4593 | Ng4601 | ~Ng4584; + assign n9159 = ~Ng4349 & (Ng4340 | n9156 | n9157); + assign n9160 = ~n9159 & (n5729 | Ng4340 | ~Ng4349); + assign n9161 = (Ng4340 & ~Ng4349) | (n5729 & (~Ng4340 | ~Ng4349)); + assign n9162 = (n9160 & (~Ng4358 | n9161)) | (Ng4358 & n9161); + assign n9163 = ~Pg91 | n4212 | n4213 | Ng2965; + assign n9164 = n9163 & Pg35; + assign n9165 = n4206_1 | n4207 | n4209 | n4210 | Ng2955 | n8214 | ~n8215 | Ng2946; + assign n9166 = n9165 & Pg35; + assign n9167 = Ng2941 | Ng4072 | Ng4153; + assign n9168 = n9167 & Pg35; + assign n9169 = Pg35 & ~n9426; + assign n9170 = Ng2932 | ~Pg44 | Ng2927; + assign n9171 = n9170 & Pg35; + assign n9172 = Pg35 & ~n9427; + assign n9173 = n5969 | Ng301 | Ng2902; + assign n9174 = n9173 & Pg35; + assign n9175 = Ng2882 | n4213 | n4212; + assign n9176 = n9175 & Pg35; + assign n9177 = Ng2856 | n4209 | n4210; + assign n9178 = n9177 & Pg35; + assign n9179 = Ng2848 | n4207 | n4206_1; + assign n9180 = n9179 & Pg35; + assign n9181 = n9103 & ~Ng4087 & n9102; + assign n9182 = n9105 & n9104 & Ng4087; + assign n9183 = (~Ng2724 & ~Ng2803) | (~Ng2807 & (Ng2724 | ~Ng2803)); + assign n9184 = (~Ng2724 & ~Ng2815) | (~Ng2819 & (Ng2724 | ~Ng2815)); + assign n9185 = (~Ng2724 & ~Ng2771) | (~Ng2775 & (Ng2724 | ~Ng2771)); + assign n9186 = (~Ng2724 & ~Ng2783) | (~Ng2787 & (Ng2724 | ~Ng2783)); + assign n9187 = Pg35 | ~Ng2894; + assign n9188 = ~Pg35 | ~Ng1291; + assign n9189 = ~Pg35 | ~Ng947; + assign n9190 = Ng4878 & (~Pg35 | (~Ng4843 & n8228)); + assign n9191 = Ng4688 & (~Pg35 | (~Ng4653 & n8230)); + assign n9192 = (~n6203 & n6204) | (~Ng4340 & (n6203 | n6204)); + assign n9193 = Pg35 | ~Ng2827; + assign n9194 = Pg35 | ~Ng2815; + assign n9195 = Pg35 | ~Ng2819; + assign n9196 = Pg35 | ~Ng2807; + assign n9197 = Pg35 | ~Ng2795; + assign n9198 = Pg35 | ~Ng2783; + assign n9199 = Pg35 | ~Ng2787; + assign n9200 = Pg35 | ~Ng2775; + assign n9201 = (Ng392 & ~Ng452) | (~Ng174 & (~Ng392 | ~Ng452)); + assign n9202 = (~Ng405 & ~Ng424) | (~Ng437 & (Ng405 | ~Ng424)); + assign n9203 = (~Ng405 & ~Ng437) | (~Ng401 & (Ng405 | ~Ng437)); + assign n9204 = (n9202 & (~Ng392 | n9203)) | (Ng392 & n9203); + assign n9205 = n7768 & n8237; + assign n9206 = (~Ng4955 & n9205) | (n6274 & (~Ng4955 | ~n9205)); + assign n9207 = n7773 & n8237; + assign n9208 = (~Ng4944 & n9207) | (n6275_1 & (~Ng4944 | ~n9207)); + assign n9209 = n6125 & n8237; + assign n9210 = (~Ng4888 & n9209) | (n6280 & (~Ng4888 | ~n9209)); + assign n9211 = n7784 & n8239; + assign n9212 = (~Ng4765 & n9211) | (n6282 & (~Ng4765 | ~n9211)); + assign n9213 = n7789 & n8239; + assign n9214 = (~Ng4754 & n9213) | (n6283 & (~Ng4754 | ~n9213)); + assign n9215 = n7796 & n8239; + assign n9216 = (~Ng4698 & n9215) | (n6288 & (~Ng4698 | ~n9215)); + assign n9217 = Pg35 | ~Ng4340; + assign n9218 = ~Ng157 | n8250; + assign n9219 = Ng4512 | Ng4581; + assign n9220 = (n5967 & ~n8641) | (n8036 & (~n5967 | ~n8641)); + assign n9221 = Ng4552 | Ng4581; + assign n9222 = (n5967 & ~n8644) | (n8038 & (~n5967 | ~n8644)); + assign n9223 = Pg35 | ~Ng2759; + assign n9224 = n8320 | ~n5876 | n8188; + assign n9225 = Pg35 & n9224 & (~n7519 | ~n8673); + assign n9226 = Pg35 | ~Ng4108; + assign n9227 = Pg35 | ~Ng2756; + assign n9228 = Pg35 | ~Ng301; + assign n9229 = ~Ng5046 | n8354 | ~Ng5041; + assign n9230 = (n8357 & (~Ng5052 | n9229)) | (Ng5052 & n9229); + assign n9231 = Pg35 | ~Ng4098; + assign n9232 = ~Ng5033 & (~n8353 | (Pg35 & ~n8355)); + assign n9233 = ~Ng5052 & (~n9229 | (Pg35 & ~n8357)); + assign n9234 = Pg35 | ~Ng5041; + assign n9235 = Pg35 | ~Ng5037; + assign n9236 = Pg35 | ~Ng5033; + assign n9237 = Pg35 | ~Ng5022; + assign n9238 = Ng283 & (~Pg35 | (~Ng287 & n8241)); + assign n9239 = ~Ng4473 | Ng4459; + assign n9240 = (~Pg120 & ~Ng4146) | (~Pg124 & (~Pg120 | Ng4146)); + assign n9241 = (~Pg114 & ~Ng4157) | (~Pg116 & (~Pg114 | Ng4157)); + assign n9242 = (~Ng2504 & ~Ng2715) | (~Ng2638 & (~Ng2504 | Ng2715)); + assign n9243 = (Ng2819 & (Ng2815 | Ng2715)) | (Ng2815 & ~Ng2715); + assign n9244 = ~n8206 | n5866 | Ng2735; + assign n9245 = n9244 & (~n9118 | (Ng2719 & n9242)); + assign n9246 = ~n9244 & (~n9119 | (Ng2719 & n9243)); + assign n9247 = (~Ng1677 & ~Ng2715) | (~Ng1811 & (~Ng1677 | Ng2715)); + assign n9248 = (Ng2787 & (Ng2783 | Ng2715)) | (Ng2783 & ~Ng2715); + assign n9249 = n9244 & (~n9120 | (~Ng2719 & n9247)); + assign n9250 = ~n9244 & (~n9121 | (Ng2719 & n9248)); + assign n9251 = Ng2681 & (~Pg35 | (Ng2675 & n8413)); + assign n9252 = Pg35 & Ng2657 & (~n5920 | n8415); + assign n9253 = Pg35 & Ng2595 & (~n5920 | n8205); + assign n9254 = Ng2547 & (~Pg35 | (Ng2541 & n8417)); + assign n9255 = Pg35 & Ng2523 & (~n5919 | n8419); + assign n9256 = Pg35 & Ng2461 & (~n5919 | n8203); + assign n9257 = Ng2413 & (~Pg35 | (Ng2407 & n8420)); + assign n9258 = Pg35 & Ng2389 & (~n5925 | n8422); + assign n9259 = Pg35 & Ng2327 & (~n5925 | n8204); + assign n9260 = Ng2279 & (~Pg35 | (Ng2273 & n8423)); + assign n9261 = Pg35 & Ng2255 & (~n5878 | n8425); + assign n9262 = Pg35 & Ng2193 & (~n5878 | n8197); + assign n9263 = Ng2122 & (~Pg35 | (Ng2116 & n8427)); + assign n9264 = Pg35 & Ng2098 & (~n5916 | n8429); + assign n9265 = Pg35 & Ng2036 & (~n5916 | n8201); + assign n9266 = Ng1988 & (~Pg35 | (Ng1982 & n8430)); + assign n9267 = Pg35 & Ng1964 & (~n5899 | n8432); + assign n9268 = Pg35 & Ng1902 & (~n5899 | n8202); + assign n9269 = Ng1854 & (~Pg35 | (Ng1848 & n8433)); + assign n9270 = Pg35 & Ng1830 & (~n5941 | n8435); + assign n9271 = Pg35 & Ng1768 & (~n5941 | n8199); + assign n9272 = Ng1720 & (~Pg35 | (Ng1714 & n8436)); + assign n9273 = Pg35 & Ng1696 & (~n5868 | n8438); + assign n9274 = Pg35 & Ng1632 & (~n5868 | n8207); + assign n9275 = Pg35 | ~Ng1536; + assign n9276 = Pg35 | ~Ng1193; + assign n9277 = Ng6519 & (~Pg35 | (~n8440 & Ng6513)); + assign n9278 = Ng6500 & (~Pg35 | (~n8440 & ~Ng6505)); + assign n9279 = ~Pg12470 ^ Ng6727; + assign n9280 = Pg35 & Ng6500 & (~n5884_1 | n8512); + assign n9281 = Ng6173 & (~Pg35 | (~n8442 & Ng6167)); + assign n9282 = Ng6154 & (~Pg35 | (~n8442 & ~Ng6159)); + assign n9283 = ~Pg12422 ^ Ng6381; + assign n9284 = Pg35 & Ng6154 & (~n5952 | ~n8513); + assign n9285 = Ng5827 & (~Pg35 | (~n8444 & Ng5821)); + assign n9286 = Ng5808 & (~Pg35 | (~n8444 & ~Ng5813)); + assign n9287 = ~Pg12350 ^ Ng6035; + assign n9288 = Pg35 & Ng5808 & (~n5940 | n8514); + assign n9289 = Ng5481 & (~Pg35 | (~n8446 & Ng5475)); + assign n9290 = (~Pg35 | (~n8446 & ~Ng5467)) & Ng5462; + assign n9291 = ~Pg12300 ^ Ng5689; + assign n9292 = Pg35 & Ng5462 & (~n5876 | n8515); + assign n9293 = Ng5134 & (~Pg35 | (~n8449 & Ng5128)); + assign n9294 = Ng5115 & (~Pg35 | (~n8449 & ~Ng5120)); + assign n9295 = ~\[4415] ^ Pg12238; + assign n9296 = Pg35 & Ng5115 & (~n4151_1 | n8516); + assign n9297 = ~Ng4983 & (n7555 | Ng4991); + assign n9298 = n9133 & n9132 & n4483; + assign n9299 = ~Ng4793 & (n7560 | Ng4801); + assign n9300 = n9135 & n9134 & n4637; + assign n9301 = Ng3827 & (~Pg35 | (~n8451 & Ng3821)); + assign n9302 = Ng3808 & (~Pg35 | (~n8451 & ~Ng3813)); + assign n9303 = ~Pg11418 ^ Ng4040; + assign n9304 = Pg35 & Ng3808 & (~n5927 | n8517); + assign n9305 = Ng3476 & (~Pg35 | (~n8453 & Ng3470)); + assign n9306 = Ng3457 & (~Pg35 | (~n8453 & ~Ng3462)); + assign n9307 = ~Pg11388 ^ Ng3689; + assign n9308 = Pg35 & Ng3457 & (~n5889 | n8518); + assign n9309 = Ng3125 & (~Pg35 | (~n8456 & Ng3119)); + assign n9310 = (~Pg35 | (~n8456 & ~Ng3111)) & Ng3106; + assign n9311 = ~Pg11349 ^ Ng3338; + assign n9312 = Pg35 & Ng3106 & (~n5908 | n8519); + assign n9313 = Pg35 | ~Ng2729; + assign n9314 = n8521 & n8458 & (Ng1454 | n8770); + assign n9315 = Pg35 & (n9314 | (~n8458 & Ng1454)); + assign n9316 = n8523 & n8459 & (Ng1467 | n8770); + assign n9317 = Pg35 & (n9316 | (~n8459 & Ng1467)); + assign n9318 = n8524 & n8460 & (Ng1437 | n8770); + assign n9319 = Pg35 & (n9318 | (~n8460 & Ng1437)); + assign n9320 = n8526 & n8461 & (Ng1111 | n8778); + assign n9321 = Pg35 & (n9320 | (~n8461 & Ng1111)); + assign n9322 = n8528 & n8462 & (Ng1124 | n8778); + assign n9323 = Pg35 & (n9322 | (~n8462 & Ng1124)); + assign n9324 = n8529 & n8463 & (Ng1094 | n8778); + assign n9325 = Pg35 & (n9324 | (~n8463 & Ng1094)); + assign n9326 = Ng827 & ~n8464; + assign n9327 = ~Ng676 | ~n8467; + assign n9328 = Pg35 | ~Ng482; + assign n9329 = ~Ng417 ^ n9204; + assign n9330 = Ng417 & (~Pg35 | (~n7976 & n9329)); + assign n9331 = Pg35 | ~Ng5057; + assign n9332 = Pg35 | ~Ng5069; + assign n9333 = Ng4521 | ~Pg35 | n5729; + assign n9334 = ~n8126 ^ Ng4527; + assign n9335 = ~Ng26936 | ~Pg35 | Ng4125; + assign n9336 = Pg35 | ~Ng4082; + assign n9337 = Pg35 | ~Ng1351; + assign n9338 = Pg35 | ~Ng1008; + assign n9339 = Ng10384 | Ng4473; + assign n9340 = n8126 & (~Pg35 | Ng4527); + assign n9341 = ~Ng26936 | ~Pg35 | Ng2712; + assign n9342 = Pg35 | ~Ng1395; + assign n9343 = (~Ng896 & ~Ng862) | (Ng890 & (Ng896 | ~Ng862)); + assign n9344 = ~Ng812 | ~n7758 | n7905; + assign n9345 = ~Pg35 | n5960; + assign n9346 = ~Ng528 & (n5933 | n8469); + assign n9347 = ~Pg35 | ~Pg7540 | Ng347; + assign n9348 = ~Pg35 | ~Ng329 | ~n8493 | Ng341; + assign n9349 = ~Pg35 | Ng311 | Ng305 | Ng26885; + assign n9350 = n7941 & ~Ng5080 & (Ng5069 | ~Ng5077); + assign n9351 = Ng4064 & (~Pg35 | (~Ng4057 & Ng2841)); + assign n9352 = Pg35 | ~Ng1564; + assign n9353 = ~Ng1526 | n7379; + assign n9354 = (~Ng1306 & n9353) | (~Ng1339 & (~Ng1306 | ~n9353)); + assign n9355 = ~n8082 & Ng1389; + assign n9356 = Ng1351 & (n9355 | n7964); + assign n9357 = Pg35 | ~Ng1221; + assign n9358 = ~Ng1183 | n7389; + assign n9359 = (~Ng962 & n9358) | (~Ng996 & (~Ng962 | ~n9358)); + assign n9360 = ~n8083 & Ng1046; + assign n9361 = Ng1008 & (n9360 | n7972); + assign n9362 = ~n6252 ^ Ng370; + assign n9363 = ~Ng376 ^ Ng358; + assign n9364 = ~Pg8358 ^ Ng191; + assign n9365 = (~Ng209 & (~n8501 | n9364)) | (n8501 & n9364); + assign n9366 = n8501 & n9364; + assign n9367 = ~Pg8358 ^ n9366; + assign n9368 = Pg35 | ~Ng6727; + assign n9369 = ~Ng6727 ^ n8502; + assign n9370 = Pg35 | ~Ng6381; + assign n9371 = n8503 ^ Ng6381; + assign n9372 = Pg35 | ~Ng6035; + assign n9373 = ~Ng6035 ^ n8504; + assign n9374 = Pg35 | ~Ng5689; + assign n9375 = ~Ng5689 ^ n8505; + assign n9376 = Pg35 | ~\[4415] ; + assign n9377 = n8506 ^ \[4415] ; + assign n9378 = ~Pg9251 ^ Ng4308; + assign n9379 = (Ng4145 & (~Ng4253 | Ng4164)) | (Ng4253 & Ng4164); + assign n9380 = ~Pg8870 | Ng4235; + assign n9381 = Pg8918 | Pg8917 | Pg8920 | Pg8919 | Pg11770 | Pg8916 | Pg8915; + assign n9382 = n9380 & (Pg8870 | (~Ng4235 & n9381)); + assign n9383 = n9382 ^ n9379; + assign n9384 = Pg35 | ~Ng4040; + assign n9385 = n8507 ^ Ng4040; + assign n9386 = Pg35 | ~Ng3689; + assign n9387 = n8508 ^ Ng3689; + assign n9388 = Pg35 | ~Ng3338; + assign n9389 = n8509 ^ Ng3338; + assign n9390 = Pg13272 | Pg7946 | Pg19357 | Ng1333 | Pg8475; + assign n9391 = n8007 ^ n9390; + assign n9392 = (~Pg7946 & ~Ng1532) | (~Ng1521 & (Pg7946 | ~Ng1532)); + assign n9393 = (~Pg7946 & ~Ng1521) | (~Ng1339 & (Pg7946 | ~Ng1521)); + assign n9394 = Pg13259 | Pg7916 | Pg19334 | Ng990 | Pg8416; + assign n9395 = n8016 ^ n9394; + assign n9396 = (~Pg7916 & ~Ng1189) | (~Ng1178 & (Pg7916 | ~Ng1189)); + assign n9397 = (~Pg7916 & ~Ng1178) | (~Ng996 & (Pg7916 | ~Ng1178)); + assign n9398 = n8027 | ~Ng822 | ~Ng817 | ~Ng723; + assign n9399 = ~Pg8786 | Ng4180; + assign n9400 = Pg8785 | Pg8787 | Pg8783 | Pg8784 | Pg11447 | Pg8788 | Pg8789; + assign n9401 = n9399 & (Pg8786 | (~Ng4180 & n9400)); + assign n9402 = Ng4297 | Pg10122; + assign n1335_1 = ~n6714; + assign n1472_1 = Pg35 & Pg113; + assign n2083 = ~n6734; + assign n2136 = ~n6202; + assign n3336 = ~n6683; + assign n3524 = ~n6693; + assign n3847_1 = Pg35 & Pg64; + assign n4156_1 = ~n6724; + assign n4331_1 = ~n7967; + assign n4369 = ~n7975; + assign n4587_1 = ~n7852; + assign n5686 = ~n7997; + assign n6226 = ~n6664; + assign n1242_1 = Pg35 & Pg125; + assign n9417 = Ng4125 | n6263 | Ng4057 | Ng4064; + assign n9418 = n5947 | n9181 | n9182; + assign n9419 = n8319 | n5730 | ~n5927; + assign n9420 = n8319 | ~n5884_1 | n8191; + assign n9421 = n8320 | n5730 | ~n5952; + assign n9422 = n8320 | ~n4151_1 | n8191; + assign n9423 = n8320 | ~n5940 | n8190; + assign n9424 = n8319 | ~n5889 | n8190; + assign n9425 = n8319 | ~n5908 | n8188; + assign n9426 = n4218 & n4219 & ~Ng2975; + assign n9427 = ~n8478 & n4217 & ~Ng2917; + assign n9428 = n8329 & n8067 & n5911 & ~n6273; + assign n9429 = n8329 & n8069 & n5872 & ~n6269; + assign n9430 = n8329 & n8071 & n5910 & ~n6270_1; + assign n9431 = n8329 & n8073 & n5873 & ~n6271; + assign n9432 = n8329 & n8075 & n5921 & ~n6267; + assign n9433 = n8329 & n8077 & n5887 & ~n6272; + assign n9434 = n8329 & n8079 & n5894 & ~n6266; + assign n9435 = n8329 & n8081 & n4162 & ~n6268; + assign n9436 = n7979 & n5983 & n7978 & n5984; + assign n9437 = ~Ng1389 & n7879 & ~n8484; + assign n9438 = ~Ng1046 & n7890 & ~n8489; + assign n9439 = n8229 & ~n6193 & Ng4849; + assign n9440 = n8231 & ~n6198 & Ng4659; + assign n9441 = Ng608 & n6259 & ~n8183; + assign n9442 = Ng604 & n6297_1 & ~n8183; + assign n9443 = n6361 & Ng2449 & Pg35; + assign n9444 = n6379 & Ng2315 & Pg35; + assign n9445 = n6454 & Ng1756 & Pg35; + assign n9446 = Ng599 & n6490 & ~n8183; + assign n9447 = Ng595 & n6649 & ~n8183; + assign n9448 = Ng590 & n6839 & ~n8183; + assign n9449 = n6654 & Ng6597 & Pg35; + assign n9450 = n6900 & Ng6653 & Pg35; + assign n9451 = n6914 & Ng6633 & Pg35; + assign n9452 = n6970 & Ng6287 & Pg35; + assign n9453 = n6972 & Ng6283 & Pg35; + assign n9454 = n6977 & Ng6275 & Pg35; + assign n9455 = n6673 & Ng5905 & Pg35; + assign n9456 = n7008 & Ng5961 & Pg35; + assign n9457 = n7022 & Ng5941 & Pg35; + assign n9458 = n6682 & Ng5559 & Pg35; + assign n9459 = n7077 & Ng5595 & Pg35; + assign n9460 = n7124 & Ng5260 & Pg35; + assign n9461 = n7129 & Ng5252 & Pg35; + assign n9462 = n7131 & Ng5248 & Pg35; + assign n9463 = n7187 & Ng3953 & Pg35; + assign n9464 = n7192 & Ng3945 & Pg35; + assign n9465 = n7194 & Ng3941 & Pg35; + assign n9466 = n7241 & Ng3602 & Pg35; + assign n9467 = n7249 & Ng3590 & Pg35; + assign n9468 = n7257 & Ng3578 & Pg35; + assign n9469 = n7304 & Ng3239 & Pg35; + assign n9470 = n7306 & Ng3235 & Pg35; + assign n9471 = n7311 & Ng3227 & Pg35; + assign n9472 = ~Pg35 & Ng1454; + assign n9473 = ~Pg35 & Ng1111; + assign n9474 = n7936 & \[4434] & Pg35; + assign n1457 = ~n6802; + assign n5056_1 = ~n6812; + assign n6335 = ~n6822; + assign n4736_1 = ~n8002; + assign n6137 = ~n6709; + assign n1517 = ~n6752; + assign n4020 = ~n6762; + assign n1993_1 = ~n6772; + assign n4412_1 = ~n6782; + assign n5893_1 = ~n6792; + assign n4422 = ~n7947; + assign n4432_1 = ~n7959; + assign n6359 = ~n6705; + assign n6570 = ~n7163; + assign Pg34956 = n4124_1; + assign Pg34839 = n4124_1; + assign Pg34788 = n4133; + assign Pg34437 = n4135; + assign Pg34436 = n4136; + assign Pg33959 = n4151_1; + assign Pg33894 = n4133; + assign Pg33533 = n4162; + assign Pg31861 = \[4415] ; + assign Pg31665 = n4135; + assign Pg31656 = n4136; + assign Pg30332 = \[4421] ; + assign Pg29221 = \[4426] ; + assign Pg29220 = \[4427] ; + assign Pg29219 = \[4428] ; + assign Pg29218 = \[4507] ; + assign Pg29217 = \[4430] ; + assign Pg29216 = \[4431] ; + assign Pg29215 = \[4432] ; + assign Pg29214 = \[4433] ; + assign Pg29213 = \[4434] ; + assign Pg29212 = \[4435] ; + assign Pg29211 = \[4436] ; + assign Pg29210 = \[4437] ; + assign Pg28753 = n4151_1; + assign Pg27831 = n4162; + assign Pg25219 = \[4415] ; + assign Pg24185 = Pg44; + assign Pg24184 = Pg135; + assign Pg24183 = Pg134; + assign Pg24182 = Pg127; + assign Pg24181 = Pg126; + assign Pg24180 = Pg125; + assign Pg24179 = Pg124; + assign Pg24178 = Pg120; + assign Pg24177 = Pg116; + assign Pg24176 = Pg115; + assign Pg24175 = Pg114; + assign Pg24174 = Pg113; + assign Pg24173 = Pg100; + assign Pg24172 = Pg99; + assign Pg24171 = Pg92; + assign Pg24170 = Pg91; + assign Pg24169 = Pg90; + assign Pg24168 = Pg84; + assign Pg24167 = Pg73; + assign Pg24166 = Pg72; + assign Pg24165 = Pg64; + assign Pg24164 = Pg57; + assign Pg24163 = Pg56; + assign Pg24162 = Pg54; + assign Pg24161 = Pg53; + assign Pg23683 = \[4421] ; + assign Pg21698 = Pg36; + assign Pg21292 = \[4426] ; + assign Pg21270 = \[4430] ; + assign Pg21245 = \[4427] ; + assign Pg21176 = \[4431] ; + assign Pg20901 = \[4432] ; + assign Pg20899 = \[4435] ; + assign Pg20763 = \[4436] ; + assign Pg20654 = \[4428] ; + assign Pg20652 = \[4433] ; + assign Pg20557 = \[4434] ; + assign Pg20049 = \[4437] ; + assign Pg18881 = \[4507] ; + assign Pg18101 = Pg6746; + assign Pg18100 = Pg6751; + assign Pg18099 = Pg6745; + assign Pg18098 = Pg6744; + assign Pg18097 = Pg6747; + assign Pg18096 = Pg6750; + assign Pg18095 = Pg6749; + assign Pg18094 = Pg6748; + assign Pg18092 = Pg6753; + assign Pg8403 = \[4651] ; + assign Pg8353 = \[4651] ; + assign Pg8283 = \[4658] ; + assign Pg8235 = \[4658] ; + assign Pg8178 = \[4661] ; + assign Pg8132 = \[4661] ; + assign n716 = Pg9048; + assign n780_1 = Pg17715; + assign n823_1 = Pg8920; + assign n837_1 = Pg16656; + assign n851_1 = Ng4571; + assign n914_1 = Pg17743; + assign n1022_1 = Pg16874; + assign n1045_1 = Pg16627; + assign n1136_1 = Pg17580; + assign n1174 = Pg12368; + assign n1177 = Pg17739; + assign n1205_1 = Pg14694; + assign n1228_1 = Pg17649; + assign n1331_1 = Pg17320; + assign n1358_1 = Pg14217; + assign n1411_1 = Pg17722; + assign n1423 = Pg8215; + assign n1442 = Pg10527; + assign n1481 = Pg16775; + assign n1495_1 = Ng26960; + assign n1513 = Pg12422; + assign n1650 = Pg16744; + assign n1717_1 = Pg9617; + assign n1816_1 = Pg11678; + assign n1840 = Pg17711; + assign n1912_1 = Pg14673; + assign n1920_1 = Pg17639; + assign n1959 = Pg16722; + assign n1983_1 = Pg17400; + assign n2002_1 = Pg8344; + assign n2031 = Pg13966; + assign n2074 = Pg17760; + assign n2096_1 = Pg8839; + assign n2120_1 = Pg10122; + assign n2124 = Pg12350; + assign n2127_1 = Pg19357; + assign n2150 = Pg7946; + assign n2261_1 = Pg14597; + assign n2289_1 = Pg14518; + assign n2297_1 = Pg16924; + assign n2309_1 = Pg17423; + assign n2313 = Pg7245; + assign n2331_1 = Pg9682; + assign n2345_1 = Pg14125; + assign n2432 = Pg11418; + assign n2445 = Pg14096; + assign n2458 = Pg8475; + assign n2502 = Pg8870; + assign n2619_1 = Ng26936; + assign n2663 = Pg9497; + assign n2701_1 = Pg11388; + assign n2729_1 = Pg14779; + assign n2752_1 = Pg11447; + assign n2755_1 = Pg12923; + assign n2774_1 = Pg8915; + assign n2876_1 = Pg9251; + assign n2885_1 = Pg8416; + assign n2934_1 = Ng6974; + assign n2937_1 = Pg11349; + assign n2941_1 = Ng26959; + assign n2975_1 = Pg17787; + assign n3061 = Pg14189; + assign n3079 = Pg8784; + assign n3082 = Pg17519; + assign n3219_1 = Pg19334; + assign n3232_1 = Pg9743; + assign n3270 = Pg7257; + assign n3279_1 = Ng10384; + assign n3282_1 = Pg17577; + assign n3379 = Pg16693; + assign n3382_1 = Pg17291; + assign n3435_1 = Pg12238; + assign n3468_1 = Pg16955; + assign n3471 = Pg10306; + assign n3480_1 = Pg17678; + assign n3561 = Pg7260; + assign n3595 = Pg13049; + assign n3608_1 = Pg13259; + assign n3627 = Pg8788; + assign n3779 = Pg17607; + assign n3900_1 = Pg14147; + assign n3903_1 = Pg13039; + assign n3971_1 = Pg14749; + assign n3984_1 = Pg14635; + assign n3992 = Pg16659; + assign n4010_1 = Pg10500; + assign n4039_1 = Pg14738; + assign n4042 = Pg8719; + assign n4066 = Pg12470; + assign n4084 = Pg8279; + assign n4151 = Pg12919; + assign n4178_1 = Pg17871; + assign n4206 = Pg8358; + assign n4235_1 = Pg13068; + assign n4263_1 = Pg14421; + assign n4340_1 = Pg14451; + assign n4393_1 = Pg8917; + assign n4456 = Pg14705; + assign n4489 = Pg17845; + assign n4492_1 = Pg17674; + assign n4495 = Pg8783; + assign n4578 = Pg14662; + assign n4640_1 = Pg13926; + assign n4648 = Pg8918; + assign n4731_1 = \[4507] ; + assign n4770_1 = Pg13085; + assign n4773_1 = Pg13099; + assign n4846_1 = Pg13272; + assign n4851_1 = Ng6972; + assign n4855_1 = Pg8916; + assign n4868_1 = Pg16748; + assign n4877 = \[4661] ; + assign n4890 = Pg7243; + assign n4894_1 = Pg14167; + assign n4948_1 = Pg7540; + assign n4987 = Pg17764; + assign n5060 = Pg13895; + assign n5083_1 = Pg9019; + assign n5107 = Pg8787; + assign n5160_1 = Pg8291; + assign n5237_1 = Pg12184; + assign n5265_1 = Pg17646; + assign n5269_1 = Ng25; + assign n5322 = Pg17819; + assign n5335_1 = Pg14201; + assign n5353_1 = Pg17404; + assign n5356_1 = Pg33435; + assign n5385_1 = \[4658] ; + assign n5389_1 = Pg17685; + assign n5402_1 = Pg17316; + assign n5521_1 = Ng26885; + assign n5545_1 = Pg16624; + assign n5662 = Pg17688; + assign n5690 = \[4651] ; + assign n5714 = Pg14828; + assign n5776 = Ng4520; + assign n5825_1 = Pg13906; + assign n5828_1 = Pg33079; + assign n5842_1 = Pg8785; + assign n5859 = Pg9553; + assign n5937 = Pg17778; + assign n5994_1 = Pg17813; + assign n6100_1 = Pg11770; + assign n6123_1 = Pg16718; + assign n6156 = Pg13881; + assign n6169 = Pg16686; + assign n6192 = Pg7916; + assign n6293 = Pg12300; + assign n6306_1 = Pg8919; + assign n6373 = Pg17604; + assign n6376 = Pg16603; + assign n6399 = Pg13865; + assign n6526 = Pg8789; + assign n6555 = Pg9555; + assign n6642 = Pg8786; + always @ (posedge clock) begin + Ng5057 <= n687; + Ng2771 <= n692_1; + Ng1882 <= n697_1; + Ng2299 <= n702_1; + Ng4040 <= n707_1; + Ng2547 <= n712; + Ng559 <= n716; + Ng3243 <= n721_1; + Ng452 <= n726_1; + Ng3542 <= n731_1; + Ng5232 <= n736_1; + Ng5813 <= n741_1; + Ng2907 <= n746_1; + Ng1744 <= n751_1; + Ng5909 <= n756_1; + Ng1802 <= n761_1; + Ng3554 <= n766_1; + Ng6219 <= n771_1; + Ng807 <= n776_1; + Ng6031 <= n780_1; + Ng847 <= n785_1; + Ng976 <= n790_1; + Ng4172 <= n795_1; + Ng4372 <= n800_1; + Ng3512 <= n805_1; + Ng749 <= n810_1; + Ng3490 <= n815_1; + Pg12350 <= n820_1; + Ng4235 <= n823_1; + Ng1600 <= n828_1; + Ng1714 <= n833_1; + Pg14451 <= n837_1; + Ng3155 <= n841_1; + Ng2236 <= n846_1; + Ng4555 <= n851_1; + Ng3698 <= n856_1; + Ng1736 <= n861_1; + Ng1968 <= n866_1; + Ng4621 <= n871_1; + Ng5607 <= n876_1; + Ng2657 <= n881_1; + Pg12300 <= n886_1; + Ng490 <= n890_1; + Ng311 <= n895_1; + Ng772 <= n900_1; + Ng5587 <= n905_1; + Ng6177 <= n910_1; + Ng6377 <= n914_1; + Ng3167 <= n919_1; + Ng5615 <= n924_1; + Ng4567 <= n929; + Ng3457 <= n934_1; + Ng6287 <= n939_1; + Pg7946 <= n944_1; + Ng2563 <= n948_1; + Ng4776 <= n953_1; + Ng4593 <= n958_1; + Ng6199 <= n963_1; + Ng2295 <= n968_1; + Ng1384 <= n973_1; + Ng1339 <= n978_1; + Ng5180 <= n983_1; + Ng2844 <= n988_1; + Ng1024 <= n993_1; + Ng5591 <= n998_1; + Ng3598 <= n1003_1; + Ng4264 <= n1008_1; + Ng767 <= n1013_1; + Ng5853 <= n1018_1; + Pg13865 <= n1022_1; + Ng2089 <= n1026_1; + Ng4933 <= n1031_1; + Ng4521 <= n1036_1; + Ng5507 <= n1041_1; + Pg16656 <= n1045_1; + Ng6291 <= n1049_1; + Ng294 <= n1054_1; + Ng5559 <= n1059_1; + Pg9617 <= n1064_1; + Pg9741 <= n1068_1; + Ng3813 <= n1072_1; + Ng562 <= n1077_1; + Ng608 <= n1082; + Ng1205 <= n1087_1; + Ng3909 <= n1092_1; + Ng6259 <= n1097_1; + Ng5905 <= n1102; + Ng921 <= n1107_1; + Ng2955 <= n1112_1; + Ng203 <= n1117; + Ng1099 <= n1122_1; + Ng4878 <= n1127; + Ng5204 <= n1132_1; + Pg17604 <= n1136_1; + Ng3606 <= n1140_1; + Ng1926 <= n1145_1; + Ng6215 <= n1150_1; + Ng3586 <= n1155_1; + Ng291 <= n1160_1; + Ng4674 <= n1165_1; + Ng3570 <= n1170_1; + Pg9048 <= n1174; + Pg17607 <= n1177; + Ng1862 <= n1181; + Ng676 <= n1186; + Ng843 <= n1191_1; + Ng4332 <= n1196_1; + Ng4153 <= n1201_1; + Pg17711 <= n1205_1; + Ng6336 <= n1209_1; + Ng622 <= n1214; + Ng3506 <= n1219_1; + Ng4558 <= n1224_1; + Pg17685 <= n1228_1; + Ng3111 <= n1232_1; + \[4430] <= n1237_1; + Ng26936 <= n1242_1; + Ng939 <= n1247; + Ng278 <= n1252; + Ng4492 <= n1257_1; + Ng4864 <= n1262; + Ng1036 <= n1267_1; + \[4427] <= n1272_1; + Ng1178 <= n1277_1; + Ng3239 <= n1282_1; + Ng718 <= n1287_1; + Ng6195 <= n1292_1; + Ng1135 <= n1297_1; + Ng6395 <= n1302; + \[4415] <= n1307_1; + Ng554 <= n1312_1; + Ng496 <= n1317_1; + Ng3853 <= n1322_1; + Ng5134 <= n1327_1; + Pg17404 <= n1331_1; + Pg8344 <= n1335_1; + Ng2485 <= n1339_1; + Ng925 <= n1344; + Ng48 <= n1349_1; + Ng5555 <= n1354_1; + Pg14096 <= n1358_1; + Ng1798 <= n1362_1; + Ng4076 <= n1367; + Ng2941 <= n1372_1; + Ng3905 <= n1377_1; + Ng763 <= n1382_1; + Ng6255 <= n1387_1; + Ng4375 <= n1392_1; + Ng4871 <= n1397_1; + Ng4722 <= n1402_1; + Ng590 <= n1407_1; + Pg13099 <= n1411_1; + Ng1632 <= n1415_1; + Pg12238 <= n1420; + Ng3100 <= n1423; + Ng1495 <= n1428_1; + Ng1437 <= n1433_1; + Ng6154 <= n1438_1; + Ng1579 <= n1442; + Ng5567 <= n1447; + Ng1752 <= n1452_1; + Ng1917 <= n1457; + Ng744 <= n1462_1; + Ng4737 <= n1467; + \[4661] <= n1472_1; + Ng6267 <= n1477; + Pg16659 <= n1481; + Ng1442 <= n1485_1; + Ng5965 <= n1490; + Ng4477 <= n1495_1; + Pg10500 <= n1500; + Ng4643 <= n1504; + Ng5264 <= n1509; + Pg14779 <= n1513; + Ng2610 <= n1517; + Ng5160 <= n1522_1; + Ng5933 <= n1527; + Ng1454 <= n1532_1; + Ng753 <= n1537_1; + Ng1296 <= n1542_1; + Ng3151 <= n1547_1; + Ng2980 <= n1552_1; + Ng6727 <= n1557_1; + Ng3530 <= n1562_1; + Ng4104 <= n1567; + Ng1532 <= n1572_1; + Pg9251 <= n1577_1; + Ng2177 <= n1581; + Ng52 <= n1586; + Ng4754 <= n1591_1; + Ng1189 <= n1596_1; + Ng2287 <= n1601_1; + Ng4273 <= n1606_1; + Ng1389 <= n1611_1; + Ng1706 <= n1616; + Ng5835 <= n1621_1; + Ng1171 <= n1626_1; + Ng4269 <= n1631_1; + Ng2399 <= n1636_1; + Ng4983 <= n1641_1; + Ng5611 <= n1646_1; + Pg16627 <= n1650; + Ng4572 <= n1654; + Ng3143 <= n1659; + Ng2898 <= n1664_1; + Ng3343 <= n1669_1; + Ng3235 <= n1674; + Ng4543 <= n1679_1; + Ng3566 <= n1684_1; + Ng4534 <= n1689_1; + Ng4961 <= n1694_1; + Ng4927 <= n1699_1; + Ng2259 <= n1704_1; + Ng2819 <= n1709_1; + Pg7257 <= n1714; + Ng5802 <= n1717_1; + Ng2852 <= n1722_1; + Ng417 <= n1727_1; + Ng681 <= n1732_1; + Ng437 <= n1737_1; + Ng351 <= n1742_1; + Ng5901 <= n1747_1; + Ng2886 <= n1752; + Ng3494 <= n1757_1; + Ng5511 <= n1762_1; + Ng3518 <= n1767_1; + Ng1604 <= n1772; + Ng5092 <= n1777; + Ng4831 <= n1782_1; + Ng4382 <= n1787_1; + Ng6386 <= n1792; + Ng479 <= n1797; + Ng3965 <= n1802; + Ng4749 <= n1807_1; + Ng2008 <= n1812_1; + Ng736 <= n1816_1; + Ng3933 <= n1821_1; + Ng222 <= n1826_1; + Ng3050 <= n1831_1; + Ng1052 <= n1836_1; + Pg17580 <= n1840; + Ng2122 <= n1844_1; + Ng2465 <= n1849_1; + Ng5889 <= n1854; + Ng4495 <= n1859_1; + Pg8719 <= n1864_1; + Ng4653 <= n1868; + Ng3179 <= n1873_1; + Ng1728 <= n1878_1; + Ng2433 <= n1883_1; + Ng3835 <= n1888_1; + Ng6187 <= n1893_1; + Ng4917 <= n1898_1; + Ng1070 <= n1903_1; + Ng822 <= n1908_1; + Pg17715 <= n1912_1; + Ng914 <= n1916_1; + Ng5339 <= n1920_1; + Ng4164 <= n1925_1; + Ng969 <= n1930_1; + Ng2807 <= n1935_1; + Ng4054 <= n1940_1; + Ng6191 <= n1945_1; + Ng5077 <= n1950_1; + Ng5523 <= n1955; + Ng3680 <= n1959; + Ng6637 <= n1964; + Ng174 <= n1969_1; + Ng1682 <= n1974_1; + Ng355 <= n1979_1; + Ng1087 <= n1983_1; + Ng1105 <= n1988; + Ng2342 <= n1993_1; + Ng6307 <= n1998_1; + Ng3802 <= n2002_1; + Ng6159 <= n2007_1; + Ng2255 <= n2012_1; + Ng2815 <= n2017_1; + Ng911 <= n2022_1; + Ng43 <= n2027_1; + Pg16775 <= n2031; + Ng1748 <= n2035; + Ng5551 <= n2040; + Ng3558 <= n2045; + Ng5499 <= n2050; + Ng2960 <= n2055_1; + Ng3901 <= n2060; + Ng4888 <= n2065_1; + Ng6251 <= n2070; + Pg17649 <= n2074; + Ng1373 <= n2078_1; + Pg8215 <= n2083; + Ng157 <= n2087; + Ng2783 <= n2092; + Ng4281 <= n2096_1; + Ng3574 <= n2101_1; + Ng2112 <= n2106_1; + Ng1283 <= n2111; + Ng433 <= n2116; + Ng4297 <= n2120_1; + Pg14738 <= n2124; + Pg13272 <= n2127_1; + Ng758 <= n2131_1; + Ng4639 <= n2136; + Ng6537 <= n2141_1; + Ng5543 <= n2146; + Pg8475 <= n2150; + Ng5961 <= n2154; + Ng6243 <= n2159_1; + Ng632 <= n2164_1; + Pg12919 <= n2169_1; + Ng3889 <= n2173_1; + Ng3476 <= n2178; + Ng1664 <= n2183_1; + Ng1246 <= n2188_1; + Ng6629 <= n2193; + Ng246 <= n2198; + Ng4049 <= n2203_1; + Pg7260 <= n2208_1; + Ng2932 <= n2212; + Ng4575 <= n2217_1; + Ng4098 <= n2222; + Ng4498 <= n2227; + Ng528 <= n2232_1; + Ng16 <= n2237_1; + Ng3139 <= n2242_1; + \[4432] <= n2247; + Ng4584 <= n2252; + Ng142 <= n2257; + Pg17639 <= n2261_1; + Ng5831 <= n2265; + Ng239 <= n2270_1; + Ng1216 <= n2275; + Ng2848 <= n2280_1; + Ng5022 <= n2285_1; + Pg16955 <= n2289_1; + Ng1030 <= n2293_1; + Pg13881 <= n2297_1; + Ng3231 <= n2301_1; + Pg9817 <= n2306; + Ng1430 <= n2309_1; + Ng4452 <= n2313; + Ng2241 <= n2318_1; + Ng1564 <= n2323_1; + Pg9680 <= n2328_1; + Ng6148 <= n2331_1; + Ng6649 <= n2336_1; + Ng110 <= n2341_1; + Pg14147 <= n2345_1; + Ng225 <= n2349_1; + Ng4486 <= n2354_1; + Ng4504 <= n2359_1; + Ng5873 <= n2364_1; + Ng5037 <= n2369_1; + Ng2319 <= n2374_1; + Ng5495 <= n2379_1; + Pg11770 <= n2384_1; + Ng5208 <= n2388_1; + Ng5579 <= n2393_1; + Ng5869 <= n2398_1; + Ng1589 <= n2403_1; + Ng5752 <= n2408_1; + Ng6279 <= n2413; + Ng5917 <= n2418; + Ng2975 <= n2423; + Ng6167 <= n2428_1; + Pg13966 <= n2432; + Ng2599 <= n2436_1; + Ng1448 <= n2441_1; + Pg14125 <= n2445; + Ng2370 <= n2449_1; + Ng5164 <= n2454_1; + Ng1333 <= n2458; + Ng153 <= n2463_1; + Ng6549 <= n2468_1; + Ng4087 <= n2473_1; + Ng4801 <= n2478_1; + Ng2984 <= n2483; + Ng3961 <= n2488_1; + Ng962 <= n2493; + Ng101 <= n2498_1; + Pg8918 <= n2502; + Ng6625 <= n2506; + Ng51 <= n2511_1; + Ng1018 <= n2516; + Pg17320 <= n2521_1; + Ng4045 <= n2525; + Ng1467 <= n2530; + Ng2461 <= n2535_1; + Ng2756 <= n2540; + Ng5990 <= n2545_1; + Ng1256 <= n2550_1; + Ng5029 <= n2555_1; + Ng6519 <= n2560_1; + Ng1816 <= n2565_1; + Ng4369 <= n2570; + Ng4578 <= n2575; + Ng4459 <= n2580_1; + Ng3831 <= n2585_1; + Ng2514 <= n2590_1; + Ng3288 <= n2595_1; + Ng2403 <= n2600_1; + Ng2145 <= n2605_1; + Ng1700 <= n2610_1; + Ng513 <= n2615_1; + Ng2841 <= n2619_1; + Ng5297 <= n2624_1; + Ng2763 <= n2629_1; + Ng4793 <= n2634_1; + Ng952 <= n2639_1; + Ng1263 <= n2644_1; + Ng1950 <= n2649_1; + Ng5138 <= n2654; + Ng2307 <= n2659_1; + Ng5109 <= n2663; + Pg8398 <= n2668_1; + Ng4664 <= n2672_1; + Ng2223 <= n2677_1; + Ng5808 <= n2682_1; + Ng6645 <= n2687_1; + Ng2016 <= n2692_1; + Ng3873 <= n2697; + Pg13926 <= n2701_1; + Ng2315 <= n2705_1; + Ng2811 <= n2710_1; + Ng5957 <= n2715_1; + Ng2047 <= n2720_1; + Ng3869 <= n2725_1; + Pg17760 <= n2729_1; + Ng5575 <= n2733_1; + Ng46 <= n2738_1; + Ng3752 <= n2743; + Ng3917 <= n2748_1; + Pg8783 <= n2752_1; + Ng1585 <= n2755_1; + Ng4388 <= n2760_1; + Ng6275 <= n2765_1; + Ng6311 <= n2770; + Pg8916 <= n2774_1; + Ng1041 <= n2778_1; + Ng2595 <= n2783_1; + Ng2537 <= n2788_1; + \[4426] <= n2793_1; + Ng4430 <= n2798_1; + Ng4564 <= n2803_1; + Ng4826 <= n2808_1; + Ng6239 <= n2813_1; + Ng232 <= n2818_1; + Ng5268 <= n2823_1; + Ng6545 <= n2828; + Ng2417 <= n2833_1; + Ng1772 <= n2838_1; + Ng5052 <= n2843_1; + Pg9615 <= n2848_1; + Ng1890 <= n2852_1; + Ng2629 <= n2857_1; + Ng572 <= n2862_1; + Ng2130 <= n2867_1; + Ng4108 <= n2872_1; + Ng4308 <= n2876_1; + Ng475 <= n2881_1; + Ng990 <= n2885_1; + Ng45 <= n2890_1; + Pg12184 <= n2895_1; + Ng3990 <= n2899_1; + Ng5881 <= n2904_1; + Ng1992 <= n2909_1; + Ng3171 <= n2914_1; + Ng812 <= n2919_1; + Ng832 <= n2924_1; + Ng5897 <= n2929_1; + Ng4571 <= n2934_1; + Pg13895 <= n2937_1; + Ng4455 <= n2941_1; + Ng2902 <= n2946_1; + Ng333 <= n2951_1; + Ng168 <= n2956_1; + Ng2823 <= n2961_1; + Ng3684 <= n2966_1; + Ng3639 <= n2971_1; + Pg14597 <= n2975_1; + Ng3338 <= n2979_1; + Ng5406 <= n2984_1; + Ng269 <= n2989_1; + Ng401 <= n2994_1; + Ng6040 <= n2999_1; + Ng441 <= n3004_1; + Pg9553 <= n3009_1; + Ng3808 <= n3013_1; + Ng10384 <= n3018_1; + Ng3957 <= n3023_1; + Ng4093 <= n3028_1; + Ng1760 <= n3033_1; + Pg12422 <= n3038_1; + Ng160 <= n3042_1; + Ng2279 <= n3047; + Ng3498 <= n3052; + Ng586 <= n3057; + Pg14201 <= n3061; + Ng2619 <= n3065_1; + Ng1183 <= n3070; + Ng1608 <= n3075; + Pg8785 <= n3079; + Pg17577 <= n3082; + Ng1779 <= n3086_1; + Ng2652 <= n3091; + Ng2193 <= n3096_1; + Ng2393 <= n3101_1; + Ng661 <= n3106; + Ng4950 <= n3111; + Ng5535 <= n3116_1; + Ng2834 <= n3121; + Ng1361 <= n3126; + Ng6235 <= n3131_1; + Ng1146 <= n3136; + Ng2625 <= n3141_1; + Ng150 <= n3146; + Ng1696 <= n3151_1; + Ng6555 <= n3156_1; + Pg14189 <= n3161; + Ng3881 <= n3165; + Ng6621 <= n3170_1; + Ng3470 <= n3175_1; + Ng3897 <= n3180_1; + Ng518 <= n3185_1; + Ng538 <= n3190; + Ng2606 <= n3195; + Ng1472 <= n3200; + Ng542 <= n3205; + Ng5188 <= n3210_1; + Ng5689 <= n3215; + Pg13259 <= n3219_1; + Ng405 <= n3223_1; + Ng5216 <= n3228; + Ng6494 <= n3232_1; + Ng4669 <= n3237; + Ng996 <= n3242_1; + Ng4531 <= n3247_1; + Ng2860 <= n3252; + Ng4743 <= n3257_1; + Ng6593 <= n3262_1; + Pg8291 <= n3267; + Ng4411 <= n3270; + Ng1413 <= n3275_1; + Ng26960 <= n3279_1; + Pg13039 <= n3282_1; + Ng6641 <= n3286_1; + Ng1936 <= n3291_1; + Ng55 <= n3296_1; + Ng504 <= n3301; + Ng2587 <= n3306_1; + Ng4480 <= n3311; + Ng2311 <= n3316_1; + Ng3602 <= n3321; + Ng5571 <= n3326_1; + Ng3578 <= n3331_1; + Pg9555 <= n3336; + Ng5827 <= n3340_1; + Ng3582 <= n3345; + Ng6271 <= n3350_1; + Ng4688 <= n3355_1; + Ng2380 <= n3360; + Ng5196 <= n3365_1; + Ng3227 <= n3370_1; + Ng2020 <= n3375; + Pg14518 <= n3379; + Pg17316 <= n3382_1; + Ng6541 <= n3386_1; + Ng3203 <= n3391_1; + Ng1668 <= n3396_1; + Ng4760 <= n3401_1; + Ng262 <= n3406_1; + Ng1840 <= n3411; + Ng5467 <= n3416; + Ng460 <= n3421_1; + Ng6209 <= n3426_1; + \[4436] <= n3431_1; + Pg14662 <= n3435_1; + Ng655 <= n3439; + Ng3502 <= n3444_1; + Ng2204 <= n3449; + Ng5256 <= n3454; + Ng4608 <= n3459_1; + Ng794 <= n3464_1; + Pg13906 <= n3468_1; + Ng4423 <= n3471; + Ng3689 <= n3476_1; + Ng5685 <= n3480_1; + Ng703 <= n3485_1; + Ng862 <= n3490; + Ng3247 <= n3495_1; + Ng2040 <= n3500_1; + Ng4146 <= n3505; + Ng4633 <= n3510_1; + Pg7916 <= n3515; + Ng4732 <= n3519_1; + Pg9497 <= n3524; + Ng5817 <= n3528_1; + Ng2351 <= n3533; + Ng2648 <= n3538; + Ng6736 <= n3543; + Ng4944 <= n3548; + Ng4072 <= n3553; + Pg7540 <= n3558; + Ng4443 <= n3561; + Ng3466 <= n3566_1; + Ng4116 <= n3571_1; + Ng5041 <= n3576; + Ng4434 <= n3581_1; + Ng3827 <= n3586_1; + Ng6500 <= n3591_1; + Pg17813 <= n3595; + Ng3133 <= n3599; + Ng3333 <= n3604; + Ng979 <= n3608_1; + Ng4681 <= n3613_1; + Ng298 <= n3618_1; + Ng2667 <= n3623; + Pg8789 <= n3627; + Ng1894 <= n3631; + Ng2988 <= n3636_1; + Ng3538 <= n3641; + Ng301 <= n3646_1; + Ng341 <= n3651_1; + Ng827 <= n3656_1; + Pg17291 <= n3661; + Ng2555 <= n3665_1; + Ng5011 <= n3670_1; + Ng199 <= n3675; + Ng6523 <= n3680_1; + Ng1526 <= n3685_1; + Ng4601 <= n3690_1; + Ng854 <= n3695; + Ng1484 <= n3700; + Ng4922 <= n3705; + Ng5080 <= n3710_1; + Ng5863 <= n3715_1; + Ng4581 <= n3720_1; + Ng2518 <= n3725; + Ng2567 <= n3730; + Ng568 <= n3735; + Ng3263 <= n3740; + Ng6613 <= n3745; + Ng6044 <= n3750_1; + Ng6444 <= n3755_1; + Ng2965 <= n3760; + Ng5857 <= n3765_1; + Ng1616 <= n3770_1; + Ng890 <= n3775; + Pg17646 <= n3779; + Ng3562 <= n3783_1; + Pg10122 <= n3788_1; + Ng1404 <= n3792; + Ng3817 <= n3797_1; + Ng93 <= n3802_1; + Ng4501 <= n3807_1; + Ng287 <= n3812_1; + Ng2724 <= n3817_1; + Ng4704 <= n3822_1; + Ng22 <= n3827_1; + Ng2878 <= n3832_1; + Ng5220 <= n3837_1; + Ng617 <= n3842_1; + Pg12368 <= n3847_1; + Ng316 <= n3851_1; + Ng1277 <= n3856; + Ng6513 <= n3861_1; + Ng336 <= n3866_1; + Ng2882 <= n3871_1; + Ng933 <= n3876_1; + Ng1906 <= n3881_1; + Ng305 <= n3886; + Ng8 <= n3891_1; + Ng2799 <= n3896; + Pg14167 <= n3900_1; + Pg17787 <= n3903_1; + Ng4912 <= n3907_1; + Ng4157 <= n3912; + Ng2541 <= n3917; + Ng2153 <= n3922; + Ng550 <= n3927; + Ng255 <= n3932; + Ng1945 <= n3937_1; + Ng5240 <= n3942_1; + Ng1478 <= n3947; + Ng3863 <= n3952_1; + Ng1959 <= n3957_1; + Ng3480 <= n3962; + Ng6653 <= n3967_1; + Pg17764 <= n3971_1; + Ng2864 <= n3975; + Ng4894 <= n3980_1; + Pg17678 <= n3984_1; + Ng3857 <= n3988; + Pg16693 <= n3992; + Ng499 <= n3996_1; + Ng1002 <= n4001; + Ng776 <= n4006; + Ng1236 <= n4010_1; + Ng4646 <= n4015; + Ng2476 <= n4020; + Ng1657 <= n4025_1; + Ng2375 <= n4030; + Ng63 <= n4035_1; + Pg17739 <= n4039_1; + Ng358 <= n4042; + Ng896 <= n4047_1; + Ng283 <= n4052_1; + Ng3161 <= n4057; + Ng2384 <= n4062; + Pg14828 <= n4066; + Ng4616 <= n4070_1; + Ng4561 <= n4075; + Ng2024 <= n4080; + Ng3451 <= n4084; + Ng2795 <= n4089_1; + Ng613 <= n4094_1; + Ng4527 <= n4099; + Ng1844 <= n4104; + Ng5937 <= n4109; + Ng4546 <= n4114_1; + Ng2523 <= n4119; + Pg11349 <= n4124; + Ng2643 <= n4128; + Ng1489 <= n4133_1; + Pg8358 <= n4138_1; + Ng2551 <= n4142_1; + Ng5156 <= n4147; + \[4421] <= n4151; + Pg8279 <= n4156_1; + Pg8839 <= n4160_1; + Ng1955 <= n4164; + Ng6049 <= n4169_1; + Ng2273 <= n4174; + Pg14749 <= n4178_1; + Ng4771 <= n4182_1; + Ng6098 <= n4187; + Ng3147 <= n4192_1; + Ng3347 <= n4197; + Ng2269 <= n4202_1; + Ng191 <= n4206; + Ng2712 <= n4211_1; + Ng626 <= n4216; + Ng2729 <= n4221_1; + Ng5357 <= n4226_1; + Ng4991 <= n4231_1; + Pg17819 <= n4235_1; + Ng4709 <= n4239_1; + Ng2927 <= n4244; + Ng4340 <= n4249; + Ng5929 <= n4254; + Ng4907 <= n4259_1; + Pg16874 <= n4263_1; + Ng4035 <= n4267_1; + Ng2946 <= n4272_1; + Ng918 <= n4277_1; + Ng4082 <= n4282; + Pg9743 <= n4287_1; + Ng2036 <= n4291_1; + Ng577 <= n4296_1; + Ng1620 <= n4301_1; + Ng2831 <= n4306; + Ng667 <= n4311_1; + Ng930 <= n4316_1; + Ng3937 <= n4321_1; + Ng817 <= n4326_1; + Ng1249 <= n4331_1; + Ng837 <= n4336_1; + Pg16924 <= n4340_1; + Ng599 <= n4344_1; + Ng5475 <= n4349_1; + Ng739 <= n4354_1; + Ng5949 <= n4359_1; + Ng6682 <= n4364_1; + Ng904 <= n4369; + Ng2873 <= n4374_1; + Ng1854 <= n4379_1; + Ng5084 <= n4384_1; + Ng5603 <= n4389_1; + Pg8870 <= n4393_1; + Ng2495 <= n4397_1; + Ng2437 <= n4402_1; + Ng2102 <= n4407_1; + Ng2208 <= n4412_1; + Ng2579 <= n4417_1; + Ng4064 <= n4422; + Ng4899 <= n4427_1; + Ng2719 <= n4432_1; + Ng4785 <= n4437; + Ng5583 <= n4442_1; + Ng781 <= n4447; + Ng6173 <= n4452; + Pg17743 <= n4456; + Ng2917 <= n4460; + Ng686 <= n4465_1; + Ng1252 <= n4470; + Ng671 <= n4475; + Ng2265 <= n4480; + Ng6283 <= n4485; + Pg14705 <= n4489; + Pg17519 <= n4492_1; + Pg8784 <= n4495; + Ng5527 <= n4499; + Ng4489 <= n4504; + Ng1974 <= n4509_1; + Ng1270 <= n4514; + Ng4966 <= n4519; + Ng6227 <= n4524; + Ng3929 <= n4529; + Ng5503 <= n4534; + Ng4242 <= n4539; + Ng5925 <= n4544_1; + Ng1124 <= n4549; + Ng4955 <= n4554; + Ng5224 <= n4559_1; + Ng2012 <= n4564_1; + Ng6203 <= n4569_1; + Ng5120 <= n4574; + Pg17674 <= n4578; + Ng2389 <= n4582_1; + Ng4438 <= n4587_1; + Ng2429 <= n4592; + Ng2787 <= n4597_1; + Ng1287 <= n4602; + Ng2675 <= n4607; + \[4507] <= n4612; + Ng4836 <= n4617; + Ng1199 <= n4622; + Pg19357 <= n4627; + Ng5547 <= n4631; + Ng2138 <= n4636; + Pg16744 <= n4640_1; + Ng2338 <= n4644; + Pg8919 <= n4648; + Ng6247 <= n4652_1; + Ng2791 <= n4657_1; + Ng3949 <= n4662; + Ng1291 <= n4667_1; + Ng5945 <= n4672_1; + Ng5244 <= n4677_1; + Ng2759 <= n4682; + Ng6741 <= n4687; + Ng785 <= n4692_1; + Ng1259 <= n4697_1; + Ng3484 <= n4702_1; + Ng209 <= n4707_1; + Ng6609 <= n4712_1; + Ng5517 <= n4717_1; + Ng2449 <= n4722_1; + Ng2575 <= n4727_1; + Ng65 <= n4731_1; + Ng2715 <= n4736_1; + Ng936 <= n4741_1; + Ng2098 <= n4746; + Ng4462 <= n4751_1; + Ng604 <= n4756; + Ng6589 <= n4761_1; + Ng1886 <= n4766; + Pg17845 <= n4770_1; + Pg17871 <= n4773_1; + Ng429 <= n4777_1; + Ng1870 <= n4782; + Ng4249 <= n4787_1; + Ng1825 <= n4792_1; + Ng1008 <= n4797; + Ng4392 <= n4802; + Ng3546 <= n4807_1; + Ng5236 <= n4812; + Ng1768 <= n4817; + Ng4854 <= n4822; + Ng3925 <= n4827; + Ng6509 <= n4832_1; + Ng732 <= n4837_1; + Ng2504 <= n4842_1; + Ng1322 <= n4846_1; + Ng4520 <= n4851_1; + Pg8917 <= n4855_1; + Ng2185 <= n4859_1; + Ng37 <= n4864_1; + Ng4031 <= n4868_1; + Ng2070 <= n4873_1; + \[4658] <= n4877; + Ng4176 <= n4882; + Pg11418 <= n4887_1; + Ng4405 <= n4890; + Ng872 <= n4894_1; + Ng6181 <= n4899; + Ng6381 <= n4904; + Ng4765 <= n4909_1; + Ng5563 <= n4914_1; + Ng1395 <= n4919_1; + Ng1913 <= n4924_1; + Ng2331 <= n4929_1; + Ng6263 <= n4934_1; + Ng50 <= n4939; + Ng3945 <= n4944; + Ng347 <= n4948_1; + Ng4473 <= n4953_1; + Ng1266 <= n4958_1; + Ng5489 <= n4963_1; + Ng714 <= n4968_1; + Ng2748 <= n4973; + Ng5471 <= n4978; + Ng4540 <= n4983_1; + Ng6723 <= n4987; + Ng6605 <= n4992; + Ng2445 <= n4997; + Ng2173 <= n5002; + Pg9019 <= n5007; + Ng2491 <= n5011_1; + Ng4849 <= n5016; + Ng2169 <= n5021; + Ng2283 <= n5026; + Ng6585 <= n5031_1; + \[4428] <= n5036; + Ng2407 <= n5041; + Ng2868 <= n5046_1; + Ng2767 <= n5051_1; + Ng1783 <= n5056_1; + Pg16718 <= n5060; + Ng1312 <= n5064; + Ng5212 <= n5069; + Ng4245 <= n5074_1; + Ng645 <= n5079_1; + Ng4291 <= n5083_1; + \[4435] <= n5088_1; + Ng182 <= n5093_1; + Ng1129 <= n5098; + Ng2227 <= n5103; + Pg8788 <= n5107; + Ng2246 <= n5111; + Ng1830 <= n5116; + Ng3590 <= n5121; + Ng392 <= n5126; + Ng1592 <= n5131; + Ng6505 <= n5136_1; + Ng1221 <= n5141; + Ng5921 <= n5146; + \[4431] <= n5151_1; + Ng146 <= n5156; + Ng218 <= n5160_1; + Ng1932 <= n5165_1; + Ng1624 <= n5170_1; + Ng5062 <= n5175_1; + Ng5462 <= n5180_1; + Ng2689 <= n5185_1; + Ng6573 <= n5190_1; + Ng1677 <= n5195_1; + Ng2028 <= n5200_1; + Ng2671 <= n5205_1; + Pg10527 <= n5210_1; + Pg7243 <= n5214_1; + Ng1848 <= n5218_1; + \[4434] <= n5223_1; + Ng5485 <= n5228_1; + Ng2741 <= n5233_1; + Pg11678 <= n5237_1; + Ng2638 <= n5241_1; + Ng4122 <= n5246_1; + Ng4322 <= n5251; + Ng5941 <= n5256_1; + Ng2108 <= n5261; + Pg13068 <= n5265_1; + Ng25 <= n5269_1; + Ng1644 <= n5273; + Ng595 <= n5278_1; + Ng2217 <= n5283_1; + Ng1319 <= n5288_1; + Ng2066 <= n5293_1; + Ng1152 <= n5298; + Ng5252 <= n5303_1; + Ng2165 <= n5308_1; + Ng2571 <= n5313_1; + Ng5176 <= n5318; + Pg14673 <= n5322; + Ng1211 <= n5326_1; + Ng2827 <= n5331_1; + Pg14217 <= n5335_1; + Ng4859 <= n5339_1; + Ng424 <= n5344_1; + Ng1274 <= n5349; + Pg17423 <= n5353_1; + Ng85 <= n5356_1; + Ng2803 <= n5361_1; + Ng1821 <= n5366_1; + Ng2509 <= n5371_1; + Ng5073 <= n5376_1; + Ng1280 <= n5381_1; + \[4651] <= n5385_1; + Pg13085 <= n5389_1; + Ng6633 <= n5393_1; + Ng5124 <= n5398_1; + Pg17400 <= n5402_1; + Ng6303 <= n5406_1; + Ng5069 <= n5411_1; + Ng2994 <= n5416; + Ng650 <= n5421_1; + Ng1636 <= n5426_1; + Ng3921 <= n5431_1; + Ng2093 <= n5436; + Ng6732 <= n5441_1; + Ng1306 <= n5446_1; + Ng1061 <= n5451_1; + Ng3462 <= n5456_1; + Ng2181 <= n5461; + Ng956 <= n5466_1; + Ng1756 <= n5471_1; + Ng5849 <= n5476_1; + Ng4112 <= n5481_1; + Ng2685 <= n5486_1; + Ng2197 <= n5491_1; + Ng2421 <= n5496_1; + Ng1046 <= n5501_1; + Ng482 <= n5506_1; + Ng4401 <= n5511_1; + Ng1514 <= n5516_1; + Ng329 <= n5521_1; + Ng6565 <= n5526_1; + Ng2950 <= n5531_1; + Ng1345 <= n5536_1; + Ng6533 <= n5541_1; + Pg14421 <= n5545_1; + Ng4727 <= n5549_1; + Pg12470 <= n5554_1; + Ng1536 <= n5558_1; + Ng3941 <= n5563_1; + Ng370 <= n5568_1; + Ng5694 <= n5573_1; + Ng1858 <= n5578_1; + Ng446 <= n5583_1; + Ng3219 <= n5588_1; + Ng1811 <= n5593_1; + Ng6601 <= n5598; + Ng2441 <= n5603_1; + Ng1874 <= n5608_1; + Ng4349 <= n5613_1; + Ng6581 <= n5618_1; + Ng6597 <= n5623_1; + Ng3610 <= n5628; + Ng2890 <= n5633; + Ng1978 <= n5638; + Ng1612 <= n5643_1; + Ng112 <= n5648_1; + Ng2856 <= n5653; + Ng1982 <= n5658_1; + Pg17722 <= n5662; + Ng5228 <= n5666_1; + Ng4119 <= n5671; + Ng6390 <= n5676_1; + Ng1542 <= n5681_1; + Ng4258 <= n5686; + Ng4818 <= n5690; + Ng5033 <= n5695; + Ng4717 <= n5700_1; + Ng1554 <= n5705_1; + Ng3849 <= n5710_1; + Pg17778 <= n5714; + Ng3199 <= n5718; + Ng5845 <= n5723_1; + Ng4975 <= n5728; + Ng790 <= n5733_1; + Ng5913 <= n5738_1; + Ng1902 <= n5743_1; + Ng6163 <= n5748; + Ng4125 <= n5753; + Ng4821 <= n5758_1; + Ng4939 <= n5763; + Pg19334 <= n5768; + Ng3207 <= n5772; + Ng4483 <= n5776; + Ng3259 <= n5781_1; + Ng5142 <= n5786; + Ng5248 <= n5791; + Ng2126 <= n5796; + Ng3694 <= n5801; + Ng5481 <= n5806; + Ng1964 <= n5811; + Ng5097 <= n5816_1; + Ng3215 <= n5821_1; + Pg16748 <= n5825_1; + Ng111 <= n5828_1; + Ng4427 <= n5833_1; + Ng2779 <= n5838_1; + Pg8786 <= n5842_1; + Pg7245 <= n5846; + Ng1720 <= n5850_1; + Ng1367 <= n5855_1; + Ng5112 <= n5859; + Ng4145 <= n5864; + Ng2161 <= n5869; + Ng376 <= n5874; + Ng2361 <= n5879_1; + Pg11447 <= n5884; + Ng582 <= n5888_1; + Ng2051 <= n5893_1; + Ng1193 <= n5898; + Ng2327 <= n5903_1; + Ng907 <= n5908_1; + Ng947 <= n5913_1; + Ng1834 <= n5918_1; + Ng3594 <= n5923_1; + Ng2999 <= n5928_1; + Ng2303 <= n5933_1; + Pg17688 <= n5937; + Ng699 <= n5941_1; + Ng723 <= n5946_1; + Ng5703 <= n5951_1; + Ng546 <= n5956; + Ng2472 <= n5961_1; + Ng5953 <= n5966_1; + Pg8277 <= n5971_1; + Ng1740 <= n5975_1; + Ng3550 <= n5980_1; + Ng3845 <= n5985_1; + Ng2116 <= n5990; + Pg14635 <= n5994_1; + Ng3195 <= n5998; + Ng3913 <= n6003_1; + Pg10306 <= n6008; + Ng1687 <= n6012; + Ng2681 <= n6017; + Ng2533 <= n6022_1; + Ng324 <= n6027; + Ng2697 <= n6032_1; + Ng4417 <= n6037_1; + Ng6561 <= n6042; + Ng1141 <= n6047_1; + Pg12923 <= n6052_1; + Ng2413 <= n6056; + Ng1710 <= n6061; + Ng6527 <= n6066_1; + Ng3255 <= n6071_1; + Ng1691 <= n6076_1; + Ng2936 <= n6081; + Ng5644 <= n6086_1; + Ng5152 <= n6091; + Ng5352 <= n6096; + Pg8915 <= n6100_1; + Ng2775 <= n6104; + Ng2922 <= n6109_1; + Ng1111 <= n6114_1; + Ng5893 <= n6119_1; + Pg16603 <= n6123_1; + Ng6617 <= n6127; + Ng2060 <= n6132_1; + Ng4512 <= n6137; + Ng5599 <= n6142; + Ng3401 <= n6147; + Ng4366 <= n6152; + Pg16722 <= n6156; + \[4433] <= n6160; + Ng3129 <= n6165; + Ng3329 <= n6169; + Ng5170 <= n6174_1; + Ng26959 <= n6179; + Ng5821 <= n6183; + Ng6299 <= n6188_1; + Pg8416 <= n6192; + Ng2079 <= n6196; + Ng4698 <= n6201_1; + Ng3703 <= n6206; + Ng1559 <= n6211; + Ng943 <= n6216; + Ng411 <= n6221; + Pg9682 <= n6226; + Ng3953 <= n6230; + Ng2704 <= n6235; + Ng6035 <= n6240; + Ng1300 <= n6245; + Ng4057 <= n6250; + Ng5200 <= n6255; + Ng4843 <= n6260; + Ng5046 <= n6265; + Ng2250 <= n6270; + Ng26885 <= n6275; + Ng4549 <= n6279; + Ng2453 <= n6284; + Ng5841 <= n6289; + Pg14694 <= n6293; + Ng2912 <= n6297; + Ng2357 <= n6302; + Pg8920 <= n6306_1; + Ng164 <= n6310; + Ng4253 <= n6315; + Ng5016 <= n6320; + Ng3119 <= n6325_1; + Ng1351 <= n6330; + Ng1648 <= n6335; + Ng6972 <= n6340; + Ng5115 <= n6344_1; + Ng3352 <= n6349; + Ng6657 <= n6354; + Ng4552 <= n6359; + Ng3893 <= n6364_1; + Ng3211 <= n6369; + Pg13049 <= n6373; + Pg16624 <= n6376; + Ng5595 <= n6380; + Ng3614 <= n6385; + Ng2894 <= n6390; + Ng3125 <= n6395; + Pg16686 <= n6399; + Ng3821 <= n6403; + Ng4141 <= n6408_1; + Ng6974 <= n6413; + Ng5272 <= n6417; + Ng2735 <= n6422; + Ng728 <= n6427; + Ng6295 <= n6432; + Ng2661 <= n6437; + Ng1988 <= n6442; + Ng5128 <= n6447; + Ng1548 <= n6452; + Ng3106 <= n6457; + Ng4659 <= n6462; + Ng4358 <= n6467; + Ng1792 <= n6472; + Ng2084 <= n6477; + Ng3187 <= n6482; + Ng4311 <= n6487; + Ng2583 <= n6492; + Ng3003 <= n6497; + Ng1094 <= n6502; + Ng3841 <= n6507; + Ng4284 <= n6512; + Ng3191 <= n6517; + Ng4239 <= n6522; + Ng4180 <= n6526; + Ng691 <= n6531; + Ng534 <= n6536; + Ng385 <= n6541; + Ng2004 <= n6546; + Ng2527 <= n6551; + Ng5456 <= n6555; + Ng4420 <= n6560; + Ng5148 <= n6565; + Ng4507 <= n6570; + Ng5348 <= n6575; + Ng3223 <= n6580; + Ng2970 <= n6585; + Ng5698 <= n6590; + Ng5260 <= n6595; + Ng1521 <= n6600; + Ng3522 <= n6605; + Ng3115 <= n6610; + Ng3251 <= n6615; + Pg12832 <= n6620; + Ng4628 <= n6624; + Ng1996 <= n6629; + Pg8342 <= n6634; + Ng4515 <= n6638; + Pg8787 <= n6642; + Ng4300 <= n6646; + Ng1724 <= n6651; + Ng1379 <= n6656; + Pg11388 <= n6661; + Ng1878 <= n6665; + Ng5619 <= n6670; + Ng71 <= n6675; + \[4437] <= n6680; + end +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/seq/seq.v b/openfpga_flow/benchmarks/MCNC_Verilog/seq/seq.v new file mode 100644 index 000000000..f9b0bf164 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/seq/seq.v @@ -0,0 +1,1127 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:33:45 2019 + +module seq ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, + i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_, + i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, + i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, i_39_, i_40_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, + i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, + i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, + i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, i_39_, + i_40_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_; + wire n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, + n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, + n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, + n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, + n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, + n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, + n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, + n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, + n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, + n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, + n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, + n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, + n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, + n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, + n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, + n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, + n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, + n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, + n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, + n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, + n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, + n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, + n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, + n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, + n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, + n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, + n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, + n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, + n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, + n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, + n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, + n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, + n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, + n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, + n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, + n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, + n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, + n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, + n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, + n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, + n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, + n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, + n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, + n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, + n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, + n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, + n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, + n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, + n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, + n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, + n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, + n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, + n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, + n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, + n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, + n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, + n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, + n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, + n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, + n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, + n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, + n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, + n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, + n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, + n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, + n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, + n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, + n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, + n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, + n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, + n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, + n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, + n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, + n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, + n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, + n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, + n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, + n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, + n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, + n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, + n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, + n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, + n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095; + assign o_0_ = ~n852; + assign o_1_ = ~n754; + assign o_2_ = ~n606; + assign o_3_ = ~n488; + assign o_4_ = ~n426; + assign o_5_ = ~n986 | ~n990 | ~n980 | ~n982 | n191 | n192 | n189 | n190; + assign o_6_ = ~n306; + assign o_7_ = ~n188; + assign o_8_ = ~n111; + assign o_9_ = ~n185; + assign o_10_ = ~n823 | ~n833 | n181 | ~n175 | n180; + assign o_11_ = ~n179; + assign o_12_ = ~n708 & ~n407 & i_8_ & n112; + assign o_13_ = ~n174; + assign o_14_ = ~n173; + assign o_15_ = ~n149; + assign o_16_ = ~n172; + assign o_17_ = ~n1076 | ~n1078 | ~n437 | ~n812 | n165 | n166 | n163 | n164; + assign o_18_ = ~n800; + assign o_19_ = ~n162; + assign o_20_ = ~n728; + assign o_21_ = ~n161; + assign o_22_ = n156 | n157 | n154 | n155 | n160 | ~n662 | n158 | n159; + assign o_23_ = ~n153; + assign o_24_ = ~n146; + assign o_25_ = ~n138; + assign o_26_ = ~n134; + assign o_27_ = ~n131; + assign o_28_ = ~n128; + assign o_29_ = ~n617; + assign o_30_ = ~n1029 | n122 | n123; + assign o_31_ = ~n128 | n116 | n117 | n115 | n113 | n114; + assign o_32_ = ~n1034; + assign o_33_ = ~n576; + assign o_34_ = ~n535; + assign n111 = n223 & n149 & (n224 | n225); + assign n112 = ~n1094 & (~i_37_ | (~n288 & ~n523)); + assign n113 = n200 & (~n715 | (~i_39_ & ~n277)); + assign n114 = ~n610 & n471 & n578; + assign n115 = n579 & ~n222 & ~n257; + assign n116 = n194 & n200; + assign n117 = n385 & (~n387 | ~n715); + assign n118 = ~n909 & ~n410 & ~n877; + assign n119 = ~n906 & ~n410 & ~n877; + assign n120 = ~n909 & ~n414 & ~n877; + assign n121 = ~n906 & ~n414 & ~n877; + assign n122 = ~n946 & (n582 | ~n701 | ~n864); + assign n123 = n118 | n119 | n120 | n121; + assign n124 = n355 | n911; + assign n125 = n577 | n284 | n536; + assign n126 = n515 | n284 | n577; + assign n127 = n899 | n760 | n816; + assign n128 = n127 & n126 & n124 & n125; + assign n129 = ~n117 & n141 & (~n194 | n627); + assign n130 = n954 & n953 & ~n622 & ~n619 & n618 & n328 & n312 & n319; + assign n131 = n129 & n130; + assign n132 = n630 | n476 | n360; + assign n133 = ~n199 & n135 & ~n195; + assign n134 = ~n203 & n132 & n133; + assign n135 = n872 | n893 | ~i_34_ | n611; + assign n136 = n607 & (n608 | n609); + assign n137 = n130 & ~n201; + assign n138 = n137 & n129 & n136 & n128 & n135; + assign n139 = ~n594 & ~i_37_ & i_39_; + assign n140 = ~n902 & (n139 | (~n307 & ~n594)); + assign n141 = n952 & ~n626 & ~n625 & n616 & n315 & ~n140 & ~n113 & ~n123; + assign n142 = n631 & ~n203 & ~n117 & n124; + assign n143 = n577 | n325 | i_39_; + assign n144 = ~n194 | n627; + assign n145 = n1034 & n126 & n127; + assign n146 = n145 & n144 & n143 & n142 & n137 & n133 & n136 & n141; + assign n147 = n407 | n644 | n284 | n462; + assign n148 = i_35_ | i_34_ | n640 | n307; + assign n149 = ~i_7_ | ~i_33_; + assign n150 = n646 | ~i_37_ | n400; + assign n151 = n646 | n515 | n645; + assign n152 = n648 | n519 | n647; + assign n153 = ~n1047 & ~n651 & n152 & n151 & n150 & n149 & n147 & n148; + assign n154 = ~n666 & (~n231 | ~n355 | ~n647); + assign n155 = ~i_40_ & (n667 | (~n338 & n663)); + assign n156 = ~n611 & n663; + assign n157 = n673 & n671 & n672; + assign n158 = ~n685 & (~n669 | (n674 & ~n920)); + assign n159 = n671 & ~i_7_ & i_32_; + assign n160 = ~n708 & n670 & i_37_ & ~n333; + assign n161 = n684 & i_33_ & (i_7_ | n680); + assign n162 = n765 & n766 & (n767 | n267); + assign n163 = n813 & ~n1093 & (~i_29_ | n814); + assign n164 = ~n859 & n649 & n650; + assign n165 = ~n926 & (~n514 | ~n675); + assign n166 = ~n428 & (~n1075 | (n471 & ~n610)); + assign n167 = n338 | n820; + assign n168 = n821 | n514; + assign n169 = n630 | n476 | n815 | n816; + assign n170 = n333 | n307 | n709 | n788; + assign n171 = n451 | n817 | i_40_; + assign n172 = ~n819 & n171 & n170 & n169 & n167 & n168; + assign n173 = n492 & (~i_13_ | n407 | n822); + assign n174 = n492 & (n536 | n333 | n537); + assign n175 = n817 | n549; + assign n176 = n918 | n405 | n917; + assign n177 = n826 | n447 | n825; + assign n178 = n823 & (n225 | n817); + assign n179 = ~n828 & n178 & n177 & n175 & n176; + assign n180 = i_15_ & n834 & i_20_ & i_21_; + assign n181 = n578 & (n830 | (n561 & ~n585)); + assign n182 = n857 | n583 | n456 | n350; + assign n183 = n222 | n221 | n220; + assign n184 = n149 & ~n215 & (n210 | n216); + assign n185 = n184 & n182 & n183; + assign n186 = n240 & n239 & n238 & n182; + assign n187 = n223 & (n869 | (n701 & n242)); + assign n188 = ~n245 & n187 & n184 & n186; + assign n189 = n293 & (n378 | (~i_23_ & ~n377)); + assign n190 = ~n910 & (~n890 | (~i_37_ & ~n307)); + assign n191 = n385 & (n194 | ~n908); + assign n192 = (n194 | n347) & (n384 | ~n951); + assign n193 = i_1_ | i_4_ | i_2_ | i_3_; + assign n194 = i_39_ & n653; + assign n195 = n193 & ~n896 & (n194 | ~n280); + assign n196 = ~n332 & (n628 | (i_0_ & i_4_)); + assign n197 = ~n333 & n629; + assign n198 = ~n225 & ~n933; + assign n199 = (n196 | n197) & (n198 | ~n955); + assign n200 = ~n414 & ~i_24_ & ~n375; + assign n201 = ~n593 & (~n609 | (~n489 & ~n900)); + assign n202 = i_2_ & ~n359; + assign n203 = n202 & ~n333 & (n198 | ~n955); + assign n204 = i_11_ | ~n861; + assign n205 = ~i_17_ | n314; + assign n206 = i_12_ | n413; + assign n207 = (n204 | n205) & (n206 | ~n229); + assign n208 = n211 & (~n729 | (n961 & n962)); + assign n209 = ~i_16_ | n314; + assign n210 = n207 & n208 & (n204 | n209); + assign n211 = i_12_ | ~i_15_ | ~i_17_ | ~n229; + assign n212 = n962 & n961; + assign n213 = n211 & (n212 | ~n729); + assign n214 = n207 & (n204 | n209); + assign n215 = ~n565 & ~n862 & (~n213 | ~n214); + assign n216 = n565 | n318; + assign n217 = ~i_18_ | n428; + assign n218 = n217 & (~i_15_ | ~n963); + assign n219 = n404 | ~n963; + assign n220 = n219 & (~i_19_ | i_21_ | n218); + assign n221 = ~i_23_ | n241; + assign n222 = n864 | n333; + assign n223 = n283 | n677 | n740 | ~n853; + assign n224 = n841 | n500; + assign n225 = ~i_38_ | n771; + assign n226 = i_12_ & n861; + assign n227 = i_22_ & (~n217 | (i_15_ & n226)); + assign n228 = i_15_ & i_22_; + assign n229 = i_11_ & n861; + assign n230 = i_19_ & (n227 | (n228 & n229)); + assign n231 = ~i_40_ | n440; + assign n232 = ~i_38_ | i_39_; + assign n233 = n231 & n232; + assign n234 = n428 | n580 | n265 | n613; + assign n235 = i_35_ | ~i_33_ | ~i_34_; + assign n236 = n779 | i_32_ | n428; + assign n237 = n234 & (~i_21_ | n235 | n236); + assign n238 = n856 | n583 | n225 | n519; + assign n239 = (~i_22_ | n237) & (n866 | ~n964); + assign n240 = n965 & (n864 | n869); + assign n241 = ~i_22_ | ~i_24_; + assign n242 = n870 | n596; + assign n243 = n242 | n241 | n218; + assign n244 = ~n225 | ~n690; + assign n245 = ~n333 & (~n243 | (n244 & ~n537)); + assign n246 = ~n872 & (~n966 | (~n225 & ~n875)); + assign n247 = n657 | n866 | ~n194 | ~n578; + assign n248 = n767 | i_37_ | n350; + assign n249 = n375 | n588 | ~i_24_ | ~n293; + assign n250 = ~n246 & (n536 | n775 | n875); + assign n251 = n250 & n249 & n247 & n248; + assign n252 = ~i_18_ | n253; + assign n253 = n314 & n310; + assign n254 = n252 & (~i_19_ | n253); + assign n255 = ~i_15_ | ~i_18_ | ~i_19_ | ~n293; + assign n256 = ~i_9_ | n323; + assign n257 = n255 & (n254 | n256); + assign n258 = (~i_29_ & n825) | (n366 & (i_29_ | n825)); + assign n259 = i_29_ | n323; + assign n260 = n258 & (~i_30_ | n259); + assign n261 = ~n382 & (~n468 | (~n277 & ~n283)); + assign n262 = n644 | n256 | ~n624; + assign n263 = n907 & n895; + assign n264 = ~n261 & n262 & (n260 | n263); + assign n265 = n859 | n400; + assign n266 = (n476 | n875) & (n400 | n474); + assign n267 = ~i_40_ | n876; + assign n268 = ~i_34_ | n858; + assign n269 = n265 & n266 & (n267 | n268); + assign n270 = i_10_ & i_27_; + assign n271 = n890 | n881 | n322; + assign n272 = (n456 | n887) & (n817 | n338); + assign n273 = n739 | n890 | n721; + assign n274 = n271 & n272 & (~i_11_ | n273); + assign n275 = n283 | n320; + assign n276 = i_36_ | n307; + assign n277 = i_36_ | n647; + assign n278 = n275 & n276 & (~i_39_ | n277); + assign n279 = n396 | ~n653; + assign n280 = i_39_ | n456; + assign n281 = n278 & n279 & n280; + assign n282 = n536 | n500; + assign n283 = ~i_39_ | ~i_40_; + assign n284 = i_37_ | n858; + assign n285 = n282 & (n283 | n284); + assign n286 = (~i_40_ | n325) & (n284 | n440); + assign n287 = n286 & n285; + assign n288 = ~i_38_ | i_40_; + assign n289 = ~n244 & (~i_37_ | n288); + assign n290 = i_12_ | i_11_; + assign n291 = n290 & n228 & ~n256; + assign n292 = i_18_ & n228; + assign n293 = ~n410 | ~n414; + assign n294 = ~n613 & (n291 | (n292 & n293)); + assign n295 = ~i_37_ & ~n558 & (n294 | ~n775); + assign n296 = ~n400 & (n295 | (~n474 & ~n775)); + assign n297 = ~n887 & (n194 | ~n611); + assign n298 = n256 | n504 | ~n624 | n878; + assign n299 = i_32_ | i_13_ | n877 | n382; + assign n300 = n880 | n771 | n875; + assign n301 = n967 & (n263 | n857 | n365); + assign n302 = ~n296 & n970 & (n289 | n337); + assign n303 = (n281 | n889) & (~i_40_ | n274); + assign n304 = n971 & (n269 | n888); + assign n305 = n251 & n973 & (n897 | n702); + assign n306 = n305 & n304 & n303 & n302 & n301 & n300 & n298 & n299; + assign n307 = i_38_ | ~i_40_; + assign n308 = n310 | n901; + assign n309 = n307 | n594; + assign n310 = ~i_11_ | ~i_15_; + assign n311 = n903 | n462 | n881; + assign n312 = (n310 | n311) & (n308 | n309); + assign n313 = ~n835 & ~n881 & (~n451 | ~n690); + assign n314 = ~i_12_ | ~i_15_; + assign n315 = ~n116 & ~n313 & (n311 | n314); + assign n316 = n903 | n253 | n216; + assign n317 = n902 & n308; + assign n318 = n594 | n863; + assign n319 = n316 & (n317 | n318); + assign n320 = i_36_ | i_37_; + assign n321 = n276 & n280 & (~i_39_ | n320); + assign n322 = i_15_ | n323; + assign n323 = i_7_ | i_5_; + assign n324 = n322 & (i_12_ | n323); + assign n325 = i_38_ | n858; + assign n326 = (~i_40_ | n325) & (~i_39_ | n284); + assign n327 = ~n376 & ~n881 & (~n324 | ~n411); + assign n328 = ~n139 | n308; + assign n329 = n974 & (n321 | n889); + assign n330 = (~n194 | n975) & (n318 | ~n1095); + assign n331 = n330 & n329 & n328 & n319 & n315 & n312 & ~n140 & ~n195; + assign n332 = i_7_ | n333; + assign n333 = i_34_ | n407; + assign n334 = (n333 | ~n914) & (n332 | ~n976); + assign n335 = (n334 | n916) & (n273 | ~n290); + assign n336 = n978 & (n821 | (n451 & n549)); + assign n337 = n767 | n463; + assign n338 = ~i_37_ | n232; + assign n339 = n335 & n336 & (n337 | n338); + assign n340 = n835 | ~i_15_ | ~n290; + assign n341 = n340 & (~i_15_ | i_18_ | ~n293); + assign n342 = n314 | n913; + assign n343 = n310 | n913; + assign n344 = i_21_ | n407; + assign n345 = i_19_ | n341; + assign n346 = n342 & n343 & (n344 | n345); + assign n347 = ~i_40_ & ~n908; + assign n348 = n790 | i_34_ | n898; + assign n349 = (n523 | n890) & (n400 | n912); + assign n350 = ~i_39_ | i_40_; + assign n351 = n463 | n645; + assign n352 = n348 & n349 & (n350 | n351); + assign n353 = n322 | n565 | n231; + assign n354 = i_38_ | n577; + assign n355 = ~i_38_ | n396; + assign n356 = n353 & n354 & (n317 | n355); + assign n357 = ~i_25_ & i_26_; + assign n358 = i_4_ & i_1_; + assign n359 = ~i_0_ | i_7_; + assign n360 = ~n914 & (n358 | n359); + assign n361 = n975 | n908; + assign n362 = n915 | n360 | n333; + assign n363 = n519 | n878 | n879 | n549; + assign n364 = n175 & n363 & n361 & n362; + assign n365 = ~i_29_ | n323; + assign n366 = ~i_28_ | n323; + assign n367 = n365 & n366 & (~i_30_ | n323); + assign n368 = n284 | n596; + assign n369 = n368 & n318; + assign n370 = i_14_ | n369 | n314 | n410; + assign n371 = i_34_ | n477; + assign n372 = n370 & (n367 | n350 | n371); + assign n373 = ~i_15_ | i_21_; + assign n374 = n333 | n536 | n439; + assign n375 = n657 | n874; + assign n376 = i_40_ | n859; + assign n377 = (n375 | n376) & (n373 | n374); + assign n378 = ~n235 & ~n779 & (~n906 | ~n909); + assign n379 = n721 | ~i_0_ | n657; + assign n380 = n350 | n379 | i_36_ | ~i_37_; + assign n381 = n279 | n693; + assign n382 = i_12_ | n411; + assign n383 = n381 | n382 | ~i_13_ | i_31_; + assign n384 = ~n909 & ~n410 & ~n657; + assign n385 = ~n410 & ~i_24_ & ~n375; + assign n386 = n260 & (i_30_ | n365); + assign n387 = ~n194 & (i_39_ | n277); + assign n388 = n956 | n919; + assign n389 = n451 | i_40_ | n821; + assign n390 = ~i_13_ | n886; + assign n391 = n388 & n389 & (n387 | n390); + assign n392 = i_13_ | n277 | n283 | ~n853; + assign n393 = n407 | n514 | ~i_40_ | n400; + assign n394 = n235 | n456 | i_32_ | ~i_39_; + assign n395 = n392 & n393 & (~i_13_ | n394); + assign n396 = i_39_ | i_40_; + assign n397 = n267 & (~i_37_ | n396); + assign n398 = n871 | i_34_ | n225; + assign n399 = (n523 | n376) & (n351 | n690); + assign n400 = i_36_ | n868; + assign n401 = n398 & n399 & (n397 | n400); + assign n402 = n322 & (~i_24_ | n323); + assign n403 = n373 | n256 | ~n290; + assign n404 = ~i_18_ | n373; + assign n405 = n403 & (~n293 | n404); + assign n406 = ~i_17_ | n407; + assign n407 = i_32_ | ~i_33_; + assign n408 = n406 & (~i_16_ | n407); + assign n409 = (i_11_ | n314) & (i_12_ | n310); + assign n410 = ~i_11_ | n323; + assign n411 = i_11_ | n323; + assign n412 = (n209 | n411) & (n206 | n410); + assign n413 = ~i_15_ | ~i_16_; + assign n414 = ~i_12_ | n323; + assign n415 = n412 & (i_14_ | n413 | n414); + assign n416 = (n406 | n415) & (n256 | ~n992); + assign n417 = ~n323 & ~n333 & (~n958 | ~n991); + assign n418 = ~i_39_ & (~n892 | ~n979); + assign n419 = ~n1089 & (i_40_ | (n175 & n957)); + assign n420 = n1004 & (n910 | n790); + assign n421 = (n267 | n821) & (n401 | n872); + assign n422 = n1003 & (n695 | n416); + assign n423 = ~n418 & (n474 | (n919 & n1002)); + assign n424 = n1000 & (~i_31_ | (~n417 & n1001)); + assign n425 = n998 & n135 & n176 & n997 & n995 & n996; + assign n426 = n425 & n424 & n423 & n422 & n421 & n420 & n419 & n391; + assign n427 = n929 | n428 | n400; + assign n428 = n854 & (i_5_ | n310); + assign n429 = n427 & (n428 | n400 | n344); + assign n430 = ~i_3_ | n432; + assign n431 = ~i_2_ | n432; + assign n432 = ~i_0_ | i_32_; + assign n433 = n430 & n431 & (n358 | n432); + assign n434 = ~n270 | n396 | n756 | ~n853; + assign n435 = n863 | ~n649 | ~n650; + assign n436 = (n859 | n926) & (n925 | ~n1014); + assign n437 = n436 & n435 & n434 & n149; + assign n438 = n858 | i_5_ | ~i_31_; + assign n439 = ~i_37_ | ~i_35_ | i_36_; + assign n440 = i_38_ | ~i_39_; + assign n441 = (n439 | n440) & (~n314 | n438); + assign n442 = ~i_39_ & n307; + assign n443 = ~i_35_ | n898; + assign n444 = ~i_36_ | n923; + assign n445 = (n283 | n444) & (n396 | n443); + assign n446 = ~n350 & (~n915 | (~n452 & ~n803)); + assign n447 = i_29_ | i_30_; + assign n448 = ~i_5_ & ~n907 & (i_28_ | n447); + assign n449 = n542 | n806 | ~i_15_ | i_17_; + assign n450 = ~n448 & (~i_36_ | n231 | n740); + assign n451 = ~i_37_ | n462; + assign n452 = i_9_ | i_5_; + assign n453 = n449 & n450 & (n451 | n452); + assign n454 = (~i_4_ | n432) & (i_32_ | ~n628); + assign n455 = n454 & n430 & n431; + assign n456 = i_36_ | n477; + assign n457 = n456 & (i_36_ | ~i_39_); + assign n458 = i_11_ & ~n452; + assign n459 = ~n928 & (~n1010 | (n458 & ~n867)); + assign n460 = n932 | i_36_ | ~n863; + assign n461 = ~n459 & n460 & (~i_40_ | ~n1009); + assign n462 = ~i_38_ | ~i_39_; + assign n463 = ~i_0_ | n884; + assign n464 = n288 & n462 & (n463 | n396); + assign n465 = ~i_9_ | ~i_14_ | ~n644 | n737; + assign n466 = ~i_14_ | ~n644; + assign n467 = n465 & (n466 | ~n729); + assign n468 = n456 | n771; + assign n469 = (i_13_ | n468) & (~i_15_ | ~n624); + assign n470 = n150 & (i_5_ | n407 | n371); + assign n471 = ~i_23_ & ~n407; + assign n472 = ~n690 & ~n875 & (~n344 | n471); + assign n473 = n929 & n344; + assign n474 = ~i_37_ | n307; + assign n475 = ~n472 & (n268 | n473 | n474); + assign n476 = i_40_ | n536; + assign n477 = ~i_37_ | i_38_; + assign n478 = n476 & n477; + assign n479 = n928 | n519 | n763; + assign n480 = n479 & (i_18_ | n373 | ~n829); + assign n481 = ~n693 & (~n1008 | (~n467 & ~n702)); + assign n482 = ~n333 & (~n441 | ~n1012 | ~n1013); + assign n483 = (n536 | n926) & (n453 | ~n853); + assign n484 = (n675 | n224) & (n464 | n761); + assign n485 = (n461 | n504) & (n859 | n427); + assign n486 = n1019 & n1020 & (n428 | n475); + assign n487 = n1017 & n1018 & (n927 | ~n1006); + assign n488 = n487 & n486 & n485 & n484 & n483 & ~n482 & n437 & ~n481; + assign n489 = i_31_ | n333; + assign n490 = (n368 | n489) & (n216 | ~n466); + assign n491 = n333 | n870; + assign n492 = n149 & (n491 | (n231 & n355)); + assign n493 = ~n904 & (i_9_ | ~n672); + assign n494 = ~i_31_ & ~n290 & (~n279 | ~n287); + assign n495 = n858 | ~i_5_ | n493; + assign n496 = (n788 | n690) & (n476 | n933); + assign n497 = n496 & ~n494 & n495; + assign n498 = ~i_34_ & ~n320 & (~n462 | ~n536); + assign n499 = (n400 | n675) & (n594 | ~n863); + assign n500 = ~i_37_ | n858; + assign n501 = ~n498 & n499 & (n231 | n500); + assign n502 = n763 | n718; + assign n503 = n504 | n280; + assign n504 = i_35_ | n855; + assign n505 = n502 & n503 & (n278 | n504); + assign n506 = ~n284 & ~i_15_ & i_39_; + assign n507 = ~n690 & ~i_35_ & ~i_37_; + assign n508 = ~n489 & (n506 | (n507 & ~n644)); + assign n509 = n815 | n739 | n935; + assign n510 = i_2_ | ~i_0_ | i_1_; + assign n511 = n657 | n444; + assign n512 = ~n283 | n235 | n277; + assign n513 = n509 & (n510 | (n511 & n512)); + assign n514 = i_37_ | n536; + assign n515 = i_38_ | i_40_; + assign n516 = n514 & (i_37_ | n515); + assign n517 = n511 & (~i_40_ | n338 | n739); + assign n518 = (n504 | n859) & (n690 | n718); + assign n519 = ~i_33_ | n858; + assign n520 = n517 & n518 & (n516 | n519); + assign n521 = n451 | ~i_40_ | n268; + assign n522 = n860 & n882; + assign n523 = ~i_36_ | n868; + assign n524 = n521 & (n522 | n523); + assign n525 = ~n510 & ~i_3_ & ~i_4_; + assign n526 = n525 & (~n706 | (i_39_ & ~n756)); + assign n527 = ~n526 & (~i_5_ | i_36_ | ~n674); + assign n528 = i_9_ & (n508 | (~n490 & ~n904)); + assign n529 = (n490 | n672) & (n497 | n333); + assign n530 = (n505 | n878) & (n224 | n355); + assign n531 = n501 | n936; + assign n532 = (n513 | n925) & (n520 | n648); + assign n533 = (n527 | ~n853) & (n524 | n934); + assign n534 = n749 & (~i_11_ | n550 | n741); + assign n535 = n534 & n533 & n532 & n531 & n530 & n529 & n492 & ~n528; + assign n536 = i_38_ | i_39_; + assign n537 = ~i_35_ | n871; + assign n538 = ~i_17_ | n539; + assign n539 = i_32_ | i_31_; + assign n540 = n538 & (~i_16_ | n539); + assign n541 = ~n540 & (~n503 | (~n504 & ~n542)); + assign n542 = i_36_ | n462; + assign n543 = n503 & (~i_40_ | n504 | n542); + assign n544 = n543 | i_14_ | n540; + assign n545 = (i_12_ | n1022) & (i_15_ | n940); + assign n546 = n462 | n500; + assign n547 = n544 & n545 & (n489 | n546); + assign n548 = n756 | n771 | n333; + assign n549 = i_37_ | n232; + assign n550 = n407 | n894; + assign n551 = n548 & (n270 | n549 | n550); + assign n552 = n1023 & (n218 | n241 | n941); + assign n553 = n1024 & (n350 | n756); + assign n554 = i_31_ | i_15_ | i_5_; + assign n555 = n552 & n553 & (n287 | n554); + assign n556 = n511 & (n235 | n277); + assign n557 = ~n815 & ~n657 & i_36_ & ~n476; + assign n558 = ~i_38_ | ~i_40_; + assign n559 = (n474 | n523) & (n558 | ~n959); + assign n560 = ~i_13_ & ~n407; + assign n561 = ~n231 & ~n268; + assign n562 = n560 & (n561 | (~n476 & ~n875)); + assign n563 = ~n863 | ~n890; + assign n564 = ~n881 & (~n307 | n563 | ~n770); + assign n565 = i_31_ | n407; + assign n566 = n284 | n355; + assign n567 = ~n562 & ~n564 & (n565 | n566); + assign n568 = ~n869 & (~n941 | ~n942); + assign n569 = ~n925 & (n557 | (~n510 & ~n556)); + assign n570 = (n204 | n1022) & (~i_32_ | i_33_); + assign n571 = (n333 | n555) & (n801 | ~n943); + assign n572 = (n381 | n554) & (n547 | ~n861); + assign n573 = ~n568 & (n931 | (n222 & n937)); + assign n574 = n1025 & (~n290 | n550 | n741); + assign n575 = ~n569 & n1026 & (n935 | n939); + assign n576 = n575 & n574 & n573 & n572 & n571 & n570 & n551 & n186; + assign n577 = n899 | n841 | n816; + assign n578 = n293 & n873; + assign n579 = ~i_23_ & n921; + assign n580 = ~i_21_ | ~i_23_; + assign n581 = ~n870 & n580 & ~n690; + assign n582 = ~n462 & ~n870; + assign n583 = i_28_ | i_5_ | i_29_; + assign n584 = n583 & (i_5_ | ~n960); + assign n585 = ~i_25_ | n407; + assign n586 = n585 & (~i_26_ | n407); + assign n587 = n841 | n566; + assign n588 = i_37_ | n771; + assign n589 = n400 | n613; + assign n590 = n587 & (n428 | n588 | n589); + assign n591 = ~i_22_ | n373; + assign n592 = (n217 | ~n921) & (n591 | ~n963); + assign n593 = n500 | n790; + assign n594 = i_34_ | n858; + assign n595 = n593 & (n594 | n225); + assign n596 = ~i_38_ | n283; + assign n597 = n596 & n476; + assign n598 = n1030 & (n771 | n870 | n931); + assign n599 = (n537 | n690) & (n1031 | n933); + assign n600 = n598 & n599 & (n597 | n439); + assign n601 = (n801 | n939) & (n588 | ~n943); + assign n602 = (n586 | n822) & (n600 | n333); + assign n603 = n224 | n790; + assign n604 = n1032 & (n592 | n596 | n589); + assign n605 = n374 | n220 | n221; + assign n606 = n605 & n604 & n603 & n602 & n184 & n601 & n590 & n551; + assign n607 = n900 | n608 | n489; + assign n608 = n771 | n803; + assign n609 = n447 | n366 | n489; + assign n610 = n400 | n376; + assign n611 = i_40_ | n514; + assign n612 = n610 & (n400 | n611); + assign n613 = ~i_24_ | n407; + assign n614 = (n612 | n613) & (n224 | n231); + assign n615 = n614 | ~n293 | n591; + assign n616 = n767 | n895; + assign n617 = n616 & n615 & n136 & ~n201; + assign n618 = i_23_ | n222 | ~n293 | n373; + assign n619 = ~n265 & (~n342 | ~n343); + assign n620 = ~n410 & n905; + assign n621 = ~n414 & n905; + assign n622 = ~n318 & (n620 | n621); + assign n623 = ~n375 & ~i_23_ & n293; + assign n624 = ~n350 & n653; + assign n625 = n624 & (n384 | n623 | ~n951); + assign n626 = ~n950 & (n194 | ~n949); + assign n627 = n906 | n657 | n410; + assign n628 = i_0_ & i_1_; + assign n629 = i_3_ & ~n359; + assign n630 = n333 | n443; + assign n631 = n515 | n630 | n360; + assign n632 = (i_37_ | n690) & (n463 | n923); + assign n633 = n632 & n588 & n514; + assign n634 = n290 & (i_9_ | i_16_); + assign n635 = i_9_ | i_16_ | i_36_ | ~i_39_; + assign n636 = n867 | n290; + assign n637 = n635 & n636 & (n307 | n634); + assign n638 = n1090 & (~i_37_ | n648 | n855); + assign n639 = n1035 & n1036 & (n894 | n646); + assign n640 = i_15_ | n407; + assign n641 = n638 & n639 & (n284 | n640); + assign n642 = i_3_ | n899; + assign n643 = n642 | i_38_; + assign n644 = i_11_ & i_12_; + assign n645 = ~i_37_ | n868; + assign n646 = ~i_0_ | n407; + assign n647 = i_38_ | i_37_; + assign n648 = i_32_ | i_0_ | ~i_5_; + assign n649 = ~n268 & ~n407; + assign n650 = n884 | i_2_ | i_3_; + assign n651 = n649 & (~n643 | (~n477 & n650)); + assign n652 = ~n841 & (~n1037 | (n283 & ~n803)); + assign n653 = i_38_ & ~n320; + assign n654 = ~n693 & (~n1038 | (i_40_ & n653)); + assign n655 = ~n594 & (~n922 | ~n936 | ~n1040); + assign n656 = ~n333 & (~n1043 | ~n1044 | ~n1045); + assign n657 = ~i_35_ | n855; + assign n658 = (n267 | n519) & (~n194 | n657); + assign n659 = ~n708 & (~n1049 | (~n333 & ~n955)); + assign n660 = ~i_5_ | n721; + assign n661 = (n514 | n718) & (n657 | n715); + assign n662 = ~n659 & (n660 | (n658 & n661)); + assign n663 = ~i_7_ & n792; + assign n664 = n663 & (~n1048 | (i_9_ & ~n314)); + assign n665 = ~i_11_ | i_7_ | ~i_9_; + assign n666 = ~n664 & (~i_15_ | n665 | ~n792); + assign n667 = ~n920 & ~n665 & ~n314 & ~i_31_ & ~i_37_; + assign n668 = n923 & ~n904 & n440 & n232 & n288; + assign n669 = n668 | ~i_33_ | n594; + assign n670 = (i_35_ & ~n690) | (~n225 & (~i_35_ | ~n690)); + assign n671 = i_33_ & ~n594; + assign n672 = ~i_16_ | ~i_17_; + assign n673 = ~i_9_ & ~n685; + assign n674 = ~i_15_ | n466; + assign n675 = i_38_ | n771; + assign n676 = (n675 | n443) & (n596 | n537); + assign n677 = ~i_36_ | n647; + assign n678 = n268 & (i_35_ | n677 | n396); + assign n679 = n500 | n596 | i_6_ | ~i_34_; + assign n680 = n679 & ~n1091 & (~i_32_ | n678); + assign n681 = n1050 & (n523 | n923); + assign n682 = (n645 | n690) & (n860 | n894); + assign n683 = n681 & n682 & (n516 | n268); + assign n684 = n323 | i_0_ | n683; + assign n685 = ~i_5_ | i_7_; + assign n686 = i_17_ | n407; + assign n687 = (n685 | n686) & (n407 | ~n673); + assign n688 = (~n673 | n686) & (i_16_ | n687); + assign n689 = ~n408 & (~n318 | (~n594 & ~n859)); + assign n690 = ~i_38_ | n350; + assign n691 = ~n689 & (n284 | n333 | n690); + assign n692 = n456 | n283; + assign n693 = i_35_ | n407; + assign n694 = ~n829 & (n692 | n693); + assign n695 = n318 & n862; + assign n696 = n408 | n695 | i_14_; + assign n697 = i_9_ & (~n696 | (~i_12_ & ~n691)); + assign n698 = ~i_16_ | n406 | ~n466 | n695; + assign n699 = n594 | n922; + assign n700 = ~n697 & n698 & (n493 | n699); + assign n701 = n870 | n476; + assign n702 = n283 | ~n653; + assign n703 = (n440 | n284) & (n771 | n325); + assign n704 = n468 & (~i_13_ | i_36_ | n675); + assign n705 = n704 & n703 & n702 & n701 & n566 & n282; + assign n706 = n771 | n444; + assign n707 = n706 & (i_40_ | n542); + assign n708 = i_0_ | n685; + assign n709 = i_7_ | n290; + assign n710 = (n705 | n709) & (n707 | n708); + assign n711 = n785 & n867 & n780; + assign n712 = n711 & (i_36_ | n288); + assign n713 = ~i_31_ | n721; + assign n714 = (n711 | n660) & (n712 | n713); + assign n715 = ~i_40_ | n908; + assign n716 = n279 & n715 & (~i_39_ | n277); + assign n717 = n1053 & n503 & (n716 | n504); + assign n718 = i_36_ | n855; + assign n719 = n658 & n717 & (n522 | n718); + assign n720 = (~i_13_ | n715) & (~i_9_ | ~n194); + assign n721 = i_7_ | i_32_; + assign n722 = (n719 | n721) & (n720 | n332); + assign n723 = i_11_ | n691 | i_7_ | ~i_9_; + assign n724 = (i_7_ | n700) & (n710 | n333); + assign n725 = n694 | n709; + assign n726 = (n714 | n504) & (i_15_ | n722); + assign n727 = n1054 & n1055 & (n688 | n594); + assign n728 = n727 & n726 & n725 & n724 & n662 & n723; + assign n729 = i_15_ & ~n672; + assign n730 = n729 & ~i_5_ & i_12_; + assign n731 = ~i_14_ & (n730 | (n226 & ~n737)); + assign n732 = ~n282 & (~n213 | ~n214 | n731); + assign n733 = n1058 & (n931 | (n1057 & n285)); + assign n734 = ~n732 & (n439 | (n283 & n355)); + assign n735 = n1030 & (n537 | (n350 & n440)); + assign n736 = n735 & n734 & n733 & n441; + assign n737 = ~i_15_ | n904; + assign n738 = (n428 | n672) & (n737 | ~n963); + assign n739 = ~i_36_ | n855; + assign n740 = i_11_ | ~i_12_; + assign n741 = ~i_40_ | n890; + assign n742 = n741 | n739 | n740; + assign n743 = ~n563 & (i_37_ | ~i_40_ | ~n232); + assign n744 = n560 & n938; + assign n745 = n744 & (~n1056 | (~n594 & ~n743)); + assign n746 = ~n931 & (~n381 | ~n694 | ~n883); + assign n747 = ~n504 & ~n702; + assign n748 = ~i_32_ & (~n742 | (~n738 & n747)); + assign n749 = n368 | n467 | n333; + assign n750 = n1059 & (n586 | n647 | n523); + assign n751 = n1060 & (~n863 | n920 | n932); + assign n752 = (n860 | n939) & (n736 | n333); + assign n753 = ~n746 & (~n943 | (n474 & n956)); + assign n754 = n753 & n752 & n751 & n750 & n749 & ~n748 & n149 & n590; + assign n755 = ~i_36_ | n477; + assign n756 = ~i_38_ | n871; + assign n757 = (~i_40_ | n755) & (n283 | n756); + assign n758 = n924 | n283 | n235; + assign n759 = n758 & (n757 | n657); + assign n760 = ~i_38_ | n630; + assign n761 = n841 | n284; + assign n762 = n760 & (n761 | (n536 & n515)); + assign n763 = i_40_ | n549; + assign n764 = n741 & n763; + assign n765 = (n821 | n935) & (n764 | n944); + assign n766 = n1062 & (n456 | n396 | n897); + assign n767 = n872 | n523; + assign n768 = ~i_15_ | i_40_ | ~n644 | n803; + assign n769 = n546 & n768; + assign n770 = i_37_ | n283; + assign n771 = i_39_ | ~i_40_; + assign n772 = n288 & n770 & (~i_37_ | n771); + assign n773 = (i_11_ | n307) & (n270 | n288); + assign n774 = ~n872 & (~n338 | ~n912); + assign n775 = ~n873 | ~n293 | n613; + assign n776 = ~n774 & (n775 | (n477 & n558)); + assign n777 = ~i_37_ | ~i_39_; + assign n778 = n675 & n690 & n777 & n588; + assign n779 = ~i_40_ | n867; + assign n780 = i_36_ | n232; + assign n781 = n779 & n277 & (i_40_ | n780); + assign n782 = n729 & ~i_7_ & ~n466; + assign n783 = (n253 | n256) & (~n293 | n413); + assign n784 = n333 | n816 | n915 | n815; + assign n785 = n924 & n277; + assign n786 = i_31_ | n504; + assign n787 = n784 & (n785 | n323 | n786); + assign n788 = i_37_ | n893; + assign n789 = (n476 | n788) & (~i_38_ | n351); + assign n790 = i_38_ | n350; + assign n791 = n790 & (i_39_ | i_37_); + assign n792 = ~i_31_ & n671; + assign n793 = ~n386 & n792 & (~n225 | ~n895); + assign n794 = ~n817 & (~n232 | (i_37_ & ~n350)); + assign n795 = n1092 & (~i_36_ | n773 | n891); + assign n796 = n1071 & (n588 | n887); + assign n797 = (n820 | n923) & (n855 | ~n1064); + assign n798 = n1069 & n1070 & (n787 | n396); + assign n799 = n1068 & n1067 & n1066 & n957 & n823 & ~n794 & ~n159 & ~n793; + assign n800 = n799 & n798 & n797 & n796 & n795 & n251; + assign n801 = n882 & n859; + assign n802 = n801 & n611; + assign n803 = ~i_38_ | n858; + assign n804 = n282 & (~i_39_ | n803); + assign n805 = n326 & n804 & (n284 | n288); + assign n806 = ~i_12_ | n452; + assign n807 = ~n458 & n806; + assign n808 = n546 & (n350 | n803); + assign n809 = n804 | n807 | ~i_15_ | i_17_; + assign n810 = n805 | n807 | ~i_15_ | i_16_; + assign n811 = n809 & n810 & (n808 | n452); + assign n812 = n433 | i_40_ | n755 | n657; + assign n813 = ~i_5_ & (~n907 | (~n350 & ~n456)); + assign n814 = n853 & ~i_31_ & ~i_28_ & i_30_; + assign n815 = i_2_ | ~n628; + assign n816 = i_7_ | i_3_ | ~i_4_; + assign n817 = n872 | n268; + assign n818 = ~n332 & n525; + assign n819 = n818 & (~n955 | (~n232 & ~n933)); + assign n820 = (i_40_ & n944) | (n821 & (~i_40_ | n944)); + assign n821 = n872 | n894; + assign n822 = n523 | n514; + assign n823 = n817 | n741; + assign n824 = ~n540 & ~n256 & ~n409; + assign n825 = i_28_ | n323; + assign n826 = n907 | i_31_ | n693; + assign n827 = ~n503 | n747; + assign n828 = n827 & (n824 | (~n412 & ~n538)); + assign n829 = ~n333 & n582; + assign n830 = i_24_ & i_23_ & i_25_ & n829; + assign n831 = n1053 & ~n865 & n917; + assign n832 = ~i_24_ | i_32_; + assign n833 = n831 | ~i_25_ | ~n293 | n832 | ~n873; + assign n834 = n293 & (~n1080 | (~n221 & n829)); + assign n835 = i_9_ | n323; + assign n836 = n252 | n832 | n835 | ~n865; + assign n837 = n863 | n400; + assign n838 = n256 | ~i_40_ | n254 | n613 | n837; + assign n839 = n928 | n786 | n410 | i_12_ | i_17_; + assign n840 = n839 & (~i_21_ | ~n293 | n375); + assign n841 = ~i_34_ | n407; + assign n842 = n325 | n283 | n841; + assign n843 = ~i_18_ & ~n340 & (~n222 | n829); + assign n844 = n293 & ~n927 & (n561 | ~n612); + assign n845 = ~n826 & (~n900 | (~n366 & ~n447)); + assign n846 = n579 & (~n836 | ~n838); + assign n847 = n331 & n1088 & (n350 | n957); + assign n848 = n1087 & n1086 & (n675 | n919); + assign n849 = ~n845 & n1084 & (n842 | n879); + assign n850 = n1083 & n1082 & (n222 | n345); + assign n851 = n1081 & n1054 & n953 & ~n843 & n616 & ~n201 & ~n113 & ~n199; + assign n852 = n851 & n850 & n849 & n848 & n847 & n178 & n142 & n391; + assign n853 = ~i_32_ & ~n504; + assign n854 = i_5_ | n314; + assign n855 = ~i_33_ | i_34_; + assign n856 = i_30_ | n539; + assign n857 = n856 | n504; + assign n858 = i_36_ | i_35_; + assign n859 = i_37_ | n462; + assign n860 = ~i_40_ | n859; + assign n861 = ~i_5_ & i_9_; + assign n862 = n860 | n594; + assign n863 = ~i_37_ | n536; + assign n864 = n439 | n675; + assign n865 = ~n468 & ~n657; + assign n866 = ~i_23_ | n832; + assign n867 = i_36_ | n440; + assign n868 = i_34_ | ~i_35_; + assign n869 = n333 | n428 | ~i_21_ | n241; + assign n870 = ~i_35_ | n320; + assign n871 = ~i_36_ | i_37_; + assign n872 = i_7_ | n407; + assign n873 = n228 & i_21_; + assign n874 = ~i_15_ | i_32_; + assign n875 = i_37_ | n868; + assign n876 = ~i_37_ | n440; + assign n877 = n235 | n692; + assign n878 = i_15_ | n539; + assign n879 = ~i_13_ | n323; + assign n880 = n879 | n640; + assign n881 = n594 | n565; + assign n882 = ~i_40_ | n863; + assign n883 = n333 | n307 | n439; + assign n884 = i_4_ | i_1_; + assign n885 = n489 | ~i_13_ | n382; + assign n886 = n382 | i_32_ | n657; + assign n887 = i_13_ | n886; + assign n888 = n640 | i_13_ | n323; + assign n889 = n879 | n504 | n878; + assign n890 = i_37_ | n440; + assign n891 = i_7_ | ~n853; + assign n892 = n756 | n270 | n891; + assign n893 = i_35_ | ~i_36_; + assign n894 = i_34_ | n893; + assign n895 = i_40_ | n876; + assign n896 = n235 | n721; + assign n897 = n650 | n896; + assign n898 = ~i_36_ | ~i_37_; + assign n899 = ~i_2_ | ~i_0_ | i_1_; + assign n900 = n825 | ~i_29_ | ~i_30_; + assign n901 = n835 | i_16_ | n565; + assign n902 = n314 | n901; + assign n903 = i_17_ | n835; + assign n904 = ~i_16_ & ~i_17_; + assign n905 = n904 & i_15_ & ~n565; + assign n906 = i_22_ | n874; + assign n907 = ~i_40_ | n780; + assign n908 = i_36_ | n536; + assign n909 = i_32_ | n373; + assign n910 = n463 | n817; + assign n911 = n788 | ~n270 | n332; + assign n912 = ~i_37_ | n515; + assign n913 = n344 | i_18_ | n835; + assign n914 = n629 | n202; + assign n915 = ~i_35_ | n477; + assign n916 = ~i_38_ | n893; + assign n917 = n657 | n702; + assign n918 = i_32_ | n241; + assign n919 = n400 | n880; + assign n920 = i_36_ | n504; + assign n921 = ~i_21_ & i_22_; + assign n922 = ~i_31_ | n407; + assign n923 = ~i_37_ | ~i_38_; + assign n924 = i_36_ | n923; + assign n925 = i_32_ | i_3_ | ~i_4_; + assign n926 = i_24_ | n428 | n407 | n400; + assign n927 = ~i_15_ | n407; + assign n928 = i_16_ | n874; + assign n929 = i_22_ | n407; + assign n930 = i_40_ | n235 | n899 | n925; + assign n931 = i_13_ | i_15_ | i_5_; + assign n932 = i_32_ | i_5_ | ~i_31_; + assign n933 = ~i_37_ | n893; + assign n934 = ~i_6_ | n407; + assign n935 = i_40_ | n863; + assign n936 = ~i_5_ | n407; + assign n937 = ~n829 & n842; + assign n938 = ~i_5_ & ~n290; + assign n939 = ~n649 | n650; + assign n940 = n565 | i_34_ | ~n507; + assign n941 = n283 | n870; + assign n942 = n647 | ~i_35_ | n396; + assign n943 = ~n400 & n744; + assign n944 = n400 | n872; + assign n945 = n333 | ~i_15_ | ~i_24_; + assign n946 = n945 | i_22_ | ~n293; + assign n947 = n277 | n396; + assign n948 = n400 | n882; + assign n949 = n947 & n468; + assign n950 = n906 | n657 | n414; + assign n951 = n909 | n657 | n414; + assign n952 = (n949 | n627) & (n947 | n951); + assign n953 = i_37_ | n317 | n594 | n288; + assign n954 = n1033 & (n346 | n948); + assign n955 = n596 | n788; + assign n956 = n514 & n859; + assign n957 = n379 | n924; + assign n958 = (i_38_ & n500) | (n284 & (~i_38_ | n500)); + assign n959 = (~i_37_ & ~n523) | (~n268 & (i_37_ | ~n523)); + assign n960 = (i_28_ & (i_29_ | i_30_)) | (i_29_ & ~i_30_); + assign n961 = i_5_ | n740; + assign n962 = i_12_ | i_5_ | ~i_11_; + assign n963 = n226 | n229; + assign n964 = n865 & (n230 | (n292 & n963)); + assign n965 = (n841 | n608) & (n233 | n761); + assign n966 = (n400 | n876) & (n647 | n523); + assign n967 = ~n578 | n224 | n231; + assign n968 = n882 | n881 | n322; + assign n969 = n968 & (i_31_ | n264 | ~n853); + assign n970 = n969 & (n257 | n221 | n883); + assign n971 = ~n297 & (n885 | (n287 & n566)); + assign n972 = (n821 | n895) & (n396 | n892); + assign n973 = n972 & (n588 | n390); + assign n974 = ~n327 & (n885 | (n282 & n326)); + assign n975 = n950 & n627; + assign n976 = n884 & i_0_; + assign n977 = n539 | n519 | n382 | n890; + assign n978 = n977 & (n400 | n514 | n888); + assign n979 = n357 | n677 | n657 | n721; + assign n980 = n248 & n607 & n127 & n383 & n979 & n380; + assign n981 = n907 | n857 | n259; + assign n982 = n981 & (n771 | n277 | n887); + assign n983 = (n232 | n911) & (n372 | n565); + assign n984 = n983 & (n817 | n770); + assign n985 = (n352 | n872) & (n356 | n284); + assign n986 = n984 & n985 & (n368 | ~n1095); + assign n987 = (n346 | n837) & (n975 | n280); + assign n988 = (~i_40_ & n364) | (n339 & (i_40_ | n364)); + assign n989 = n331 & n988 & (~n200 | n908); + assign n990 = n987 & n989 & (n882 | n821); + assign n991 = (~n283 | n803) & (~i_39_ | n325); + assign n992 = ~n408 & (~n409 | (~i_14_ & ~n314)); + assign n993 = n890 | n594 | n888; + assign n994 = n993 & (n456 | n390); + assign n995 = n447 | n825 | ~n853 | n907; + assign n996 = i_5_ | n713 | ~n904 | n920; + assign n997 = n268 | n876 | n880; + assign n998 = n893 | n332 | n283 | i_38_ | n740; + assign n999 = n491 | n402 | n675; + assign n1000 = n999 & (n386 | n407 | n593); + assign n1001 = i_36_ | ~n672 | n835 | ~n853; + assign n1002 = ~i_23_ | n257 | n589 | ~n921; + assign n1003 = (n395 | n382) & (n324 | n699); + assign n1004 = (n225 | n337) & (n817 | n895); + assign n1005 = ~i_32_ & (~n503 | (~n519 & ~n860)); + assign n1006 = ~n212 & (~n318 | (~n284 & ~n462)); + assign n1007 = n469 | i_12_ | i_5_; + assign n1008 = n1007 & (n931 | (n468 & ~n624)); + assign n1009 = ~n455 & (~n898 | (i_36_ & ~n462)); + assign n1010 = (n807 | n276) & (n457 | n806); + assign n1011 = (n442 | n933) & (n445 | n463); + assign n1012 = ~n446 & n1011 & (i_14_ | n438); + assign n1013 = (n439 | n515) & (~n244 | n537); + assign n1014 = ~n899 & (~n511 | (~n235 & ~n908)); + assign n1015 = i_17_ | n874 | n503 | n806; + assign n1016 = n1015 & (n854 | ~n904 | ~n1005); + assign n1017 = n1016 & (i_25_ | n407 | n822); + assign n1018 = n912 | n433 | n657; + assign n1019 = (n429 | n478) & (n807 | n480); + assign n1020 = (n320 | n930) & (n470 | n350); + assign n1021 = n827 & ~i_5_ & n466; + assign n1022 = ~n541 & n940; + assign n1023 = n931 | n942; + assign n1024 = (n476 | n933) & (n231 | n443); + assign n1025 = n174 & (~i_16_ | n538 | ~n1021); + assign n1026 = (n559 | n934) & (n567 | ~n938); + assign n1027 = n293 & (n581 | (~i_21_ & ~n701)); + assign n1028 = ~i_24_ | i_21_ | i_23_ | n222 | n257; + assign n1029 = n124 & n1028 & (n945 | ~n1027); + assign n1030 = n225 | ~i_35_ | i_37_; + assign n1031 = n307 & n440; + assign n1032 = n565 | n584 | n595; + assign n1033 = (~n384 | n947) & (n862 | ~n1095); + assign n1034 = n944 | i_40_ | n338; + assign n1035 = n936 | i_34_ | i_35_; + assign n1036 = n642 | n407 | n645; + assign n1037 = (n284 | n463) & (n1031 | n500); + assign n1038 = n907 & (n677 | n396); + assign n1039 = n462 | i_9_ | n407; + assign n1040 = n1039 & (n440 | n640); + assign n1041 = (~i_35_ | n633) & (n307 | n893); + assign n1042 = (n232 | n788) & (n350 | n915); + assign n1043 = n1041 & n1042 & (i_40_ | n916); + assign n1044 = (i_38_ | n537) & (n439 | ~n690); + assign n1045 = (~n283 | n456) & (~i_39_ | n933); + assign n1046 = (~i_38_ | n641) & (n637 | ~n853); + assign n1047 = n655 | n652 | n654 | ~n1046 | n656 | ~n937; + assign n1048 = n209 & (~i_16_ | n310); + assign n1049 = n760 & (n277 | ~n283 | n693); + assign n1050 = n898 | i_34_ | n225; + assign n1051 = n443 | i_0_ | n476; + assign n1052 = n1051 & (i_6_ | n676); + assign n1053 = n657 | n947; + assign n1054 = n677 | n891 | ~i_11_ | n283; + assign n1055 = n660 | n376 | n718; + assign n1056 = n566 & (n500 | n231); + assign n1057 = (n536 | n870) & (n1031 | n284); + assign n1058 = n596 | n933; + assign n1059 = n699 | i_5_ | n493; + assign n1060 = ~n745 & (n476 | n788 | n841); + assign n1061 = n759 | ~i_6_ | n721; + assign n1062 = n1061 & (n762 | n816 | n510); + assign n1063 = i_14_ & (~n209 | (i_17_ & ~n314)); + assign n1064 = ~n1074 & (n782 | (~n665 & n1063)); + assign n1065 = i_31_ | n769 | n855 | n256; + assign n1066 = n1065 & (n781 | n783 | n786); + assign n1067 = (n789 | n872) & (n791 | n910); + assign n1068 = n916 | ~i_40_ | ~n818; + assign n1069 = n888 | n771 | n875; + assign n1070 = ~n578 | n842; + assign n1071 = (n776 | n400) & (n778 | n821); + assign n1072 = ~n455 & (~n706 | (~n283 & ~n756)); + assign n1073 = n268 | n473 | n267; + assign n1074 = n282 & n368; + assign n1075 = n1073 & (n489 | ~n904 | n1074); + assign n1076 = (n489 | n811) & (n504 | ~n1072); + assign n1077 = (n277 | n930) & (n429 | n802); + assign n1078 = n1077 & (n630 | n790); + assign n1079 = ~n649 | ~i_22_ | n231; + assign n1080 = n1079 & (n831 | n918); + assign n1081 = n537 | n332 | n536 | i_25_ | i_26_; + assign n1082 = ~n844 & (n556 | n642 | n721); + assign n1083 = n885 | n284 | n288; + assign n1084 = n889 | i_40_ | ~n653; + assign n1085 = (n390 | n715) & (n337 | n923); + assign n1086 = ~n846 & n1085 & (~n194 | n840); + assign n1087 = (n775 | n948) & (n864 | n946); + assign n1088 = (~n621 | n862) & (n647 | n910); + assign n1089 = i_40_ & (~n994 | (~n514 & ~n910)); + assign n1090 = n519 | i_37_ | i_32_ | n634; + assign n1091 = ~i_34_ & (~n1052 | (i_32_ & n858)); + assign n1092 = i_36_ | n772 | n897; + assign n1093 = ~i_29_ & (~i_28_ | n857); + assign n1094 = ~i_37_ & (n268 | n515); + assign n1095 = n620 | n621; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/spla/spla.v b/openfpga_flow/benchmarks/MCNC_Verilog/spla/spla.v new file mode 100644 index 000000000..dad275454 --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/spla/spla.v @@ -0,0 +1,2462 @@ +// Benchmark "TOP" written by ABC on Mon Feb 4 17:34:12 2019 + +module spla ( + i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, + i_11_, i_12_, i_13_, i_14_, i_15_, + o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, + o_41_, o_42_, o_43_, o_44_, o_45_ ); + input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, + i_10_, i_11_, i_12_, i_13_, i_14_, i_15_; + output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, + o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, + o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, + o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, + o_41_, o_42_, o_43_, o_44_, o_45_; + wire n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, + n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, + n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, + n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, + n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, + n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, + n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, + n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, + n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, + n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, + n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, + n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, + n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, + n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, + n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, + n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, + n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, + n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, + n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, + n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, + n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, + n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, + n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, + n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, + n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, + n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, + n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, + n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, + n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, + n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, + n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, + n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, + n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, + n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, + n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, + n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, + n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, + n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, + n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, + n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, + n587, n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, + n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, + n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, + n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, + n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, + n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, + n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, + n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, + n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, + n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, + n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, + n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, + n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, + n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, + n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, + n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, + n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, + n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, + n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, + n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, + n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, + n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, + n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, + n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, + n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, + n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, + n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, + n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, + n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, + n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, + n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, + n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, + n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, + n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, + n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, + n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, + n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, + n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, + n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, + n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, + n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, + n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, + n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, + n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, + n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, + n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, + n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, + n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, + n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, + n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, + n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, + n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, + n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, + n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, + n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, + n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, + n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, + n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, + n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, + n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, + n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, + n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, + n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, + n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, + n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, + n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, + n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, + n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, + n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, + n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, + n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, + n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, + n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, + n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, + n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, + n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, + n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, + n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, + n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, + n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, + n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, + n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, + n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, + n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, + n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, + n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, + n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, + n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, + n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, + n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, + n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, + n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, + n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, + n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, + n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, + n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, + n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, + n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, + n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, + n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, + n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, + n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, + n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, + n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, + n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, + n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, + n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, + n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, + n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, + n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, + n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, + n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, + n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, + n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, + n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, + n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, + n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, + n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, + n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, + n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, + n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, + n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, + n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, + n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, + n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, + n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, + n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, + n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, + n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, + n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, + n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, + n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, + n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, + n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, + n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, + n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, + n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, + n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, + n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, + n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, + n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, + n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, + n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, + n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, + n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, + n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, + n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, + n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, + n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, + n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, + n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, + n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, + n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, + n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, + n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, + n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, + n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, + n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, + n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, + n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, + n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, + n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, + n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, + n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, + n2296, n2297, n2298; + assign o_0_ = ~n211; + assign o_1_ = ~n125; + assign o_2_ = n184 & ~n1084 & (~n984 | ~n1074); + assign o_3_ = ~n210; + assign o_4_ = ~n206; + assign o_5_ = ~n566; + assign o_6_ = ~n205; + assign o_7_ = ~n514; + assign o_8_ = i_3_ & ~i_0_ & ~i_1_; + assign o_9_ = ~n203; + assign o_10_ = ~n202; + assign o_11_ = ~n201; + assign o_12_ = ~n1064; + assign o_13_ = ~n200; + assign o_14_ = ~n1032; + assign o_15_ = ~n1024; + assign o_16_ = ~n195; + assign o_17_ = ~n1017; + assign o_18_ = ~n186; + assign o_19_ = n184 & i_5_ & i_3_ & ~i_4_ & ~n1074; + assign o_20_ = ~n1074 & n184 & n185; + assign o_21_ = n183 | n181 | n182; + assign o_22_ = ~n180; + assign o_23_ = ~n179; + assign o_24_ = n172 & ~n1083; + assign o_25_ = n172 & n173; + assign o_26_ = n163 | n167 | n171 | n158; + assign o_27_ = n162 | n168 | ~n174 | ~n2250; + assign o_28_ = n167 | n168 | n169 | n170; + assign o_29_ = n164 | n162 | n163 | ~n174 | n165 | n166; + assign o_30_ = n161 | n159 | n160 | n158 | ~n156 | n157; + assign o_31_ = n955 | n956 | ~n1605 | ~n2244; + assign o_32_ = ~n954; + assign o_33_ = ~n952; + assign o_34_ = ~n156; + assign o_35_ = ~n153; + assign o_36_ = ~n937; + assign o_37_ = ~n146; + assign o_38_ = ~n873; + assign o_39_ = ~n788; + assign o_40_ = ~n145; + assign o_41_ = n144 & n142 & n143; + assign o_42_ = ~n141; + assign o_43_ = ~n138; + assign o_44_ = ~n134; + assign o_45_ = ~n126; + assign n108 = ~n469 & (~n497 | ~n1574); + assign n109 = ~n349 & (~n484 | ~n1105); + assign n110 = n555 & n1101; + assign n111 = ~n781 | ~n1224; + assign n112 = n110 & (n111 | ~n463); + assign n113 = ~n796 & (~n845 | ~n849); + assign n114 = n218 | ~n268; + assign n115 = ~n405 & (n114 | ~n779); + assign n116 = ~n225 & (~n377 | ~n636); + assign n117 = n110 & (~n1105 | ~n1202); + assign n118 = ~n1458 | ~n1468; + assign n119 = ~n405 & (n118 | ~n1151 | ~n1231); + assign n120 = n385 | ~n945; + assign n121 = ~n796 & (n120 | ~n1005); + assign n122 = n1084 | ~n1515; + assign n123 = i_7_ | i_6_; + assign n124 = n122 | n123; + assign n125 = n983 & (~n144 | n984 | n985); + assign n126 = n517 & n669 & (n667 | n670); + assign n127 = n743 & n708 & n704 & n742 & n721 & n735 & n744 & n745; + assign n128 = n1649 & n1648 & n1647 & n1645 & n1644 & n409 & ~n701 & n1646; + assign n129 = n1655 & n1654 & n1653 & n1652 & n1650 & n1651 & n700; + assign n130 = n1643 & n749 & n1642 & n1641 & n336 & n1640; + assign n131 = n2160 & (n405 | (n1006 & n1547)); + assign n132 = n675 & n1677 & n698 & n1662 & n1669 & n1674 & n1684; + assign n133 = n2159 & n2158 & n2157 & n2156 & n2155 & n195 & ~n115 & ~n119; + assign n134 = n132 & n131 & n130 & n129 & n127 & n128 & n133 & ~n752; + assign n135 = n1699 & n1698 & n1697 & n1696 & ~n767 & ~n765 & ~n217 & n757; + assign n136 = ~n430 | n1115; + assign n137 = ~n430 | n1200; + assign n138 = n137 & n136 & n127 & n135; + assign n139 = n196 & n240 & (n241 | n242); + assign n140 = n197 & n480 & (n481 | n242); + assign n141 = n139 & n140; + assign n142 = ~i_11_ & ~i_9_ & ~i_10_; + assign n143 = ~i_8_ & n1119; + assign n144 = ~n1084 & n1700; + assign n145 = n768 & n519 & (n769 | n568); + assign n146 = n912 & n911 & n910 & n909 & n708 & n908 & n913 & n914; + assign n147 = ~n948 & (n456 | (n747 & n944)); + assign n148 = n2239 & (n943 | n755); + assign n149 = n2241 & n2242 & (n746 | n405); + assign n150 = n1359 & n1322 & n307 & n1488 & n367 & n420; + assign n151 = n1611 & n585 & n649 & n1779 & n807 & n1761; + assign n152 = n2238 & n2237 & n1909 & n1896 & n1857 & n1258 & ~n121 & ~n947; + assign n153 = ~n950 & n152 & n151 & n150 & n149 & n147 & n148 & ~n949; + assign n154 = n1080 & n1079 & n1078 & n1077 & n1075 & n1076 & n1081 & n1082; + assign n155 = n663 & n661; + assign n156 = n154 & n155; + assign n157 = ~n525 & ~n1787; + assign n158 = n963 | n964 | n965 | n966 | ~n2246 | n967 | n968; + assign n159 = n957 | n958 | n959 | n960 | ~n2247 | n961 | n962; + assign n160 = ~n516 & ~n525; + assign n161 = ~n525 & n1529; + assign n162 = n1521 | n1785 | n1786; + assign n163 = n1522 | n971 | n1783 | n1531; + assign n164 = ~n516 & ~n1214; + assign n165 = ~n1214 & n1529; + assign n166 = ~n1214 & ~n1787; + assign n167 = n1703 | n1784 | n1788 | n1789 | ~n124 | n978 | n1523 | n1532; + assign n168 = n972 | n973 | n974 | n975 | ~n2248 | n976 | n977; + assign n169 = ~n515 & n1529; + assign n170 = ~n515 & (~n516 | ~n1787); + assign n171 = ~n2249 & n185 & ~n1512; + assign n172 = ~n1512 & (n185 | n222); + assign n173 = ~i_6_ & i_7_; + assign n174 = n518 & (n969 | n970); + assign n175 = n774 & (n304 | n516); + assign n176 = n522 & (n516 | (n523 & n524)); + assign n177 = ~n1525 & ~n1534; + assign n178 = n122 & ~n958; + assign n179 = ~n1704 & ~n980 & ~n183 & n178 & n177 & n176 & n174 & n175; + assign n180 = n520 & n981 & (~n979 | n982); + assign n181 = ~n665 & n555 & n556; + assign n182 = ~n1117 & n556 & ~n665; + assign n183 = n1784 | n1783 | n966 | n974 | n1785 | n959; + assign n184 = ~n985 & n1700; + assign n185 = ~i_5_ & i_3_ & i_4_; + assign n186 = n1001 & n1000 & n999 & n998 & n875 & n997 & n1002 & n1003; + assign n187 = n684 | n1354; + assign n188 = n543 | n684; + assign n189 = ~n120 | n684; + assign n190 = n1262 | n684; + assign n191 = n684 | n1309; + assign n192 = n684 | n535; + assign n193 = n684 | n1340; + assign n194 = n686 & n1842 & n1305 & n1633 & n1621 & n908; + assign n195 = n192 & n191 & n190 & n189 & n187 & n188 & n193 & n194; + assign n196 = n1142 & n1140 & n1141; + assign n197 = n1476 & n1475 & n1474 & n479; + assign n198 = n603 & n602 & n600 & n601; + assign n199 = n590 & n1747 & n604; + assign n200 = n155 & n199 & n198 & n196 & n197; + assign n201 = n209 & ~n1704 & (n770 | n771); + assign n202 = n1071 & n1070 & n1069 & n1068 & n440 & n291 & n1072 & n1073; + assign n203 = n392 & n391 & n390 & n389 & n387 & n388 & n393 & n394; + assign n204 = n517 & n521 & n520 & n518 & n519; + assign n205 = n204 & n122 & n176; + assign n206 = ~n1536 & n177 & ~n1520; + assign n207 = n176 & (n770 | n771); + assign n208 = n122 & ~n1704; + assign n209 = n981 & n768 & n777 & n774; + assign n210 = n209 & n204 & n207 & n208; + assign n211 = ~n1515 & (~n144 | n985 | n1074); + assign n212 = n1099 & n1101; + assign n213 = n212 & (~n1118 | ~n1136); + assign n214 = ~n349 & (~n725 | ~n1634); + assign n215 = ~n469 & (~n1208 | ~n1224); + assign n216 = n1086 & n143; + assign n217 = ~n1261 & (n216 | ~n755); + assign n218 = ~n781 | ~n987; + assign n219 = ~n225 & (n218 | ~n570); + assign n220 = n1101 & n143; + assign n221 = n220 & (~n781 | ~n1127); + assign n222 = i_3_ & i_5_ & i_4_; + assign n223 = n225 | n1111; + assign n224 = n225 | n1110; + assign n225 = ~n555 | ~n1093; + assign n226 = n1090 | n1091; + assign n227 = n223 & n224 & (n225 | n226); + assign n228 = n1198 & n1204; + assign n229 = n1118 & n237; + assign n230 = n352 & n374; + assign n231 = n1088 | n1095; + assign n232 = n1095 | n1109; + assign n233 = n824 & n235; + assign n234 = n233 & n232 & n231 & n230 & n228 & n229; + assign n235 = n1109 | n1167; + assign n236 = n1109 | n1163; + assign n237 = n1090 | n1109; + assign n238 = n1103 | n1122; + assign n239 = n238 & n237 & n236 & n235 & n232; + assign n240 = n1747 & n2027 & (n2028 | n265); + assign n241 = i_11_ | ~i_9_ | ~i_10_; + assign n242 = n984 | ~n1138; + assign n243 = n1074 | ~n1086; + assign n244 = n1088 | n1104; + assign n245 = n1104 | n1109; + assign n246 = (n243 | n244) & (~n212 | n245); + assign n247 = n419 & n456; + assign n248 = ~n815 & ~n379 & n247 & ~n250; + assign n249 = ~n1154 & (~n728 | ~n987); + assign n250 = ~n349 | ~n796; + assign n251 = ~n988 & (n250 | ~n488 | ~n1166); + assign n252 = ~n249 & (n1164 | (n780 & n1129)); + assign n253 = ~n219 & (~n277 | (n1111 & n1151)); + assign n254 = ~n251 & n2040 & (n236 | n2012); + assign n255 = n1538 & n588 & n471 & n890 & n1771 & n921 & n639 & n635; + assign n256 = n2043 & n2044 & n2046 & n2045 & n658 & n246 & n2042 & n2041; + assign n257 = n1721 & n848 & n837 & n790 & n455 & n410 & n467 & n631; + assign n258 = n395 & n399 & n2039 & n627 & n641 & n462 & n1691 & n1690; + assign n259 = n719 & n1625 & n404 & n408 & n1641 & n415 & n2035 & n2038; + assign n260 = n257 & n256 & n255 & n254 & n252 & n253 & n258 & n259; + assign n261 = n1120 | ~n1138; + assign n262 = ~n142 | n261; + assign n263 = n478 | n261; + assign n264 = n1131 | n261; + assign n265 = i_11_ | i_9_ | ~i_10_; + assign n266 = n263 & n264 & (n265 | n261); + assign n267 = n225 | n1217; + assign n268 = n1226 & n1224 & n1225; + assign n269 = n1126 | n1196; + assign n270 = n267 & (n225 | (n268 & n269)); + assign n271 = n539 | ~n796; + assign n272 = ~n1210 & (n271 | ~n488); + assign n273 = n220 | ~n456; + assign n274 = n273 & (~n824 | ~n1204 | ~n1232); + assign n275 = ~n377 | ~n1307; + assign n276 = ~n1154 & (~n268 | n275 | ~n1213); + assign n277 = ~n243 | ~n405; + assign n278 = ~n226 | ~n1353; + assign n279 = n277 & (n278 | ~n1203 | ~n1231); + assign n280 = ~n243 | n818; + assign n281 = ~n488 | ~n349 | ~n456; + assign n282 = ~n1200 & (n271 | n280 | n281); + assign n283 = ~n274 & (n1197 | (n469 & n1157)); + assign n284 = ~n272 & (n2010 | (n643 & n1207)); + assign n285 = ~n276 & n2013 & (n1218 | n2014); + assign n286 = n889 & n1078 & n920 & n915 & n1768 & n2009 & n587 & n638; + assign n287 = n2020 & n2018 & n2017 & n2016 & ~n279 & ~n282; + assign n288 = n789 & n411 & n451 & n454 & n458 & n634 & n836 & n847; + assign n289 = n396 & n400 & n626 & n461 & n1722 & n630 & n1688 & n2008; + assign n290 = n2007 & n1591 & n1586 & n1626 & n407 & n403 & n2003 & n2006; + assign n291 = n288 & n287 & n286 & n285 & n283 & n284 & n289 & n290; + assign n292 = n236 | ~n421; + assign n293 = n456 | n1153; + assign n294 = n232 | ~n818; + assign n295 = n456 | n530; + assign n296 = n456 | n1149; + assign n297 = n236 | ~n925; + assign n298 = n1579 & n1566 & n577 & n1726 & n1618 & n591; + assign n299 = n1996 & n1995 & n1689 & n1630 & n1279 & n1267 & ~n217 & n655; + assign n300 = n1989 & n1705 & n1716 & n1694 & n718 & n1990 & n1986 & n1982; + assign n301 = n298 & n297 & n296 & n295 & n293 & n294 & n299 & n300; + assign n302 = n405 & n419; + assign n303 = n238 | n302; + assign n304 = n1089 | n1113; + assign n305 = n1089 | n1128; + assign n306 = n304 & n305; + assign n307 = n1306 & n303 & n1305 & n188 & n1303 & n1304; + assign n308 = n1302 & n1301 & n1300 & n1299 & n1297 & n1298; + assign n309 = n1294 & n1293 & n1292 & n1291 & n1289 & n1290 & n1295 & n1296; + assign n310 = n1287 & n1286 & n1285 & n1284 & n1282 & n1283 & n1288; + assign n311 = n1973 & n1974 & (~n216 | n238); + assign n312 = n1751 & n1686 & n1631 & n1559 & n1772 & n1749 & n1710 & n1972; + assign n313 = n1971 & n812 & n1752 & n1619 & n595 & n1583; + assign n314 = n1968 & n1657 & n1970 & n1969 & n1678 & n1596; + assign n315 = n312 & n311 & n310 & n309 & n307 & n308 & n313 & n314; + assign n316 = n1091 | n1167; + assign n317 = ~n220 | n316; + assign n318 = n456 | n316; + assign n319 = ~n818 | n824; + assign n320 = n456 | n484; + assign n321 = n456 | n1228; + assign n322 = ~n925 | n1227; + assign n323 = n1584 & n594 & n580 & n1565 & n1715; + assign n324 = n1330 & n1337 & n1953 & n1713 & n1767 & n1955 & n1954 & n1322; + assign n325 = n1950 & n786 & n785 & n1706 & n1951 & n1952 & n1949; + assign n326 = n323 & n322 & n321 & n320 & n318 & n319 & n324 & n325; + assign n327 = n1352 & n1351 & n1350 & n1349 & n1347 & n1348; + assign n328 = n1346 & n1345 & n1344 & n1343 & n1341 & n1342; + assign n329 = n1934 & (~n818 | n970); + assign n330 = (n419 | n726) & (~n216 | n1232); + assign n331 = n1933 & (n243 | n1045); + assign n332 = n1931 & n1632 & n1711 & n1628 & n1687 & n1932; + assign n333 = n596 & n1753 & n1545 & n811 & n1620 & n1616 & n582 & n1930; + assign n334 = n1928 & n1654 & n1672 & n1663 & n693 & n1656; + assign n335 = n332 & n331 & n330 & n329 & n327 & n328 & n333 & n334; + assign n336 = n243 | n1212; + assign n337 = n243 | n1097; + assign n338 = n1110 | n405; + assign n339 = n243 | n1225; + assign n340 = n243 | n1135; + assign n341 = n717 & n1595 & n1594 & n1610 & n1682 & n1681; + assign n342 = n1915 & n1575 & n579 & n1568 & n1567 & n1671 & n1651 & n1914; + assign n343 = n1359 & n1368 & n1919 & n1627 & n1922 & n1561 & n1921 & n1918; + assign n344 = n341 & n340 & n339 & n338 & n336 & n337 & n342 & n343; + assign n345 = n1088 | n1102; + assign n346 = n1102 | n1109; + assign n347 = ~n892 & n345 & n346; + assign n348 = n1214 & n780; + assign n349 = ~n555 | ~n1086; + assign n350 = (n348 | n349) & (n347 | ~n430); + assign n351 = n349 | n1127; + assign n352 = n1208 & n1127; + assign n353 = n643 & n1129; + assign n354 = n351 & (~n430 | (n352 & n353)); + assign n355 = ~n879 & n1136; + assign n356 = n355 | ~n421; + assign n357 = n225 | n1339; + assign n358 = n405 | n1340; + assign n359 = n349 | n1339; + assign n360 = n349 | n726; + assign n361 = n225 | n1232; + assign n362 = n469 | n1339; + assign n363 = n1161 | n1340; + assign n364 = n1846 & n1843 & n1845 & n1844 & n193 & n1697; + assign n365 = n362 & n361 & n360 & n359 & n357 & n358 & n363 & n364; + assign n366 = (~n385 | n419) & (n225 | n995); + assign n367 = n366 & n365; + assign n368 = ~n984 & n1101; + assign n369 = n368 & (~n1232 | ~n1340); + assign n370 = ~n110 | n780; + assign n371 = n2298 | n225; + assign n372 = ~n879 & n1215; + assign n373 = n370 & n371 & (~n110 | n372); + assign n374 = n345 & n346; + assign n375 = n1394 & ~n385 & n1280; + assign n376 = n375 & n374 & n231; + assign n377 = n515 & n1215; + assign n378 = n377 & ~n892; + assign n379 = ~n243 | n368; + assign n380 = n379 & (~n233 | ~n374); + assign n381 = n212 | n110; + assign n382 = ~n346 | ~n1281; + assign n383 = n381 & (n382 | n111); + assign n384 = n277 & (~n990 | ~n1133); + assign n385 = ~n1261 | ~n1308; + assign n386 = n368 & (n385 | ~n648); + assign n387 = (~n250 | ~n275) & (n243 | n1606); + assign n388 = (~n385 | n684) & (n302 | n652); + assign n389 = (n352 | n405) & (n355 | n796); + assign n390 = (n1152 | n738) & (n1781 | n1161); + assign n391 = n2069 & n2070 & n373 & n1076 & n418 & n367; + assign n392 = n291 & n260 & n335 & n326 & n301 & n315 & n227 & n2071; + assign n393 = n2058 & n2060 & n2062 & n2065 & n2067 & n2068 & n2056 & n2055; + assign n394 = n2054 & n2053 & n2051 & n2050 & n2049 & n2048 & ~n213 & n2047; + assign n395 = n225 | n1123; + assign n396 = n225 | n231; + assign n397 = n1089 | n1095; + assign n398 = n395 & n396 & (n225 | n397); + assign n399 = n225 | n1124; + assign n400 = n225 | n1204; + assign n401 = n1089 | n1090; + assign n402 = n399 & n400 & (n225 | n401); + assign n403 = n405 | n231; + assign n404 = n405 | n232; + assign n405 = ~n1086 | n1117; + assign n406 = n403 & n404 & (n405 | n397); + assign n407 = n405 | n1204; + assign n408 = n405 | n237; + assign n409 = n407 & n408 & (n405 | n401); + assign n410 = n225 | n1136; + assign n411 = n225 | n1198; + assign n412 = n1089 | n1106; + assign n413 = n410 & n411 & (n225 | n412); + assign n414 = n405 | n1198; + assign n415 = n405 | n1118; + assign n416 = n414 & n415 & (n405 | n412); + assign n417 = n349 | n1261; + assign n418 = n1406 & n190 & n1405 & n1019 & n1403 & n1404; + assign n419 = ~n1093 | n1117; + assign n420 = n417 & n418 & (n419 | n235); + assign n421 = ~n349 | n430; + assign n422 = ~n1136 & (n421 | ~n796); + assign n423 = n1431 & n1430 & n1429 & n1428 & n1426 & n1427 & n1432 & n1433; + assign n424 = n1377 & n2090 & (~n539 | n1124); + assign n425 = (~n815 | n1149) & (n243 | n1153); + assign n426 = (n2088 | n1261) & (n1461 | n346); + assign n427 = n2089 & (n235 | (~n539 & n1461)); + assign n428 = ~n422 & (n1127 | (~n421 & n1459)); + assign n429 = n426 & n425 & n424 & n420 & n301 & n423 & n427 & n428; + assign n430 = n1086 & n1099; + assign n431 = ~n1208 & (n430 | ~n1459); + assign n432 = n469 | n1307; + assign n433 = n469 | n1219; + assign n434 = ~n431 & (n824 | (n1461 & n1462)); + assign n435 = (~n546 | n1309) & (n231 | n2087); + assign n436 = n1517 | n1307; + assign n437 = (n1461 | n345) & (n1463 | n1219); + assign n438 = (n2088 | n1308) & (n2066 | n1228); + assign n439 = n326 & n1075 & (~n212 | n1224); + assign n440 = n437 & n436 & n435 & n434 & n432 & n433 & n438 & n439; + assign n441 = n368 & (~n636 | ~n1467); + assign n442 = n469 | n632; + assign n443 = n469 | n1465; + assign n444 = n469 | n628; + assign n445 = ~n110 | n632; + assign n446 = n2085 & (~n212 | (n463 & n632)); + assign n447 = (~n381 | n642) & (n684 | n1467); + assign n448 = n1473 & n1472 & n1471 & n1470 & ~n441 & n1469; + assign n449 = n2086 & (~n679 | n1481); + assign n450 = n447 & n446 & n445 & n444 & n442 & n443 & n448 & n449; + assign n451 = ~n220 | n231; + assign n452 = n397 & n232; + assign n453 = n451 & (~n220 | n452); + assign n454 = n456 | n1198; + assign n455 = n1118 | n456; + assign n456 = ~n1101 | n1120; + assign n457 = n454 & n455 & (n456 | n412); + assign n458 = ~n220 | n1198; + assign n459 = n412 & n1118; + assign n460 = n458 & (~n220 | n459); + assign n461 = n456 | n1208; + assign n462 = n456 | n1127; + assign n463 = n1089 | n1126; + assign n464 = n461 & n462 & (n456 | n463); + assign n465 = ~n233 | ~n482; + assign n466 = n220 & (n465 | ~n486); + assign n467 = n469 | n1123; + assign n468 = n469 | n231; + assign n469 = ~n1101 | n1114; + assign n470 = n467 & n468 & (n469 | n397); + assign n471 = n469 | n1136; + assign n472 = n469 | n1198; + assign n473 = n471 & n472 & (n469 | n412); + assign n474 = n2076 & (~n1053 | (n945 & n1048)); + assign n475 = ~n368 | n725; + assign n476 = n475 & n474 & n470 & n473; + assign n477 = ~n1099 | ~n1138; + assign n478 = ~i_11_ | i_9_ | i_10_; + assign n479 = n477 | n478; + assign n480 = n2075 & (n2028 | n478); + assign n481 = ~i_11_ | ~i_9_ | i_10_; + assign n482 = n1089 | n1167; + assign n483 = n482 | n349; + assign n484 = n1091 | n1102; + assign n485 = n1481 & n1480 & n589 & n1465 & n1467; + assign n486 = n1108 | n1167; + assign n487 = n486 & n485 & n484 & n226 & n316; + assign n488 = n225 & n302; + assign n489 = ~n421 & ~n818; + assign n490 = ~n1051 & n488 & n489; + assign n491 = n1090 | n1108; + assign n492 = n482 & n401 & n491 & n486; + assign n493 = ~n212 | n2293; + assign n494 = n493 & (~n212 | n491); + assign n495 = n1108 | n1126; + assign n496 = n1108 | n1163; + assign n497 = n1102 | n1108; + assign n498 = n497 & n495 & n496; + assign n499 = n381 & (~n346 | ~n495); + assign n500 = ~n796 & (~n397 | ~n530); + assign n501 = ~n419 | ~n850; + assign n502 = n501 & (~n1123 | ~n1136 | ~n1458); + assign n503 = n501 | ~n1154; + assign n504 = n503 & (~n530 | ~n1219 | ~n1307); + assign n505 = ~n488 & (~n463 | ~n482 | ~n781); + assign n506 = (n397 | n1460) & (~n277 | n1458); + assign n507 = (n1157 | n487) & (n1155 | n482); + assign n508 = (n1483 | n496) & (n1807 | n530); + assign n509 = (n2099 | n1479) & (n2011 | n725); + assign n510 = n2098 & n2097 & n2095 & ~n505 & ~n502 & ~n504; + assign n511 = n2093 & n2094 & n1708 & n896 & n1560 & n1540; + assign n512 = n1617 & n1624 & n1629 & n1647 & n844 & n1707 & n2091 & n1587; + assign n513 = n2104 & n2106 & n2108 & n2112 & n2110 & n2109 & n2114 & n2113; + assign n514 = n511 & n510 & n509 & n508 & n506 & n507 & n512 & n513; + assign n515 = n1106 | n1201; + assign n516 = ~n1099 | n1513; + assign n517 = ~n160 & ~n164 & (n515 | n516); + assign n518 = n970 | n516; + assign n519 = n1514 | n985; + assign n520 = n1514 | n665; + assign n521 = (n1514 | n776) & (n304 | n516); + assign n522 = ~n1119 | n1513; + assign n523 = n652 & n1230; + assign n524 = n1045 & n990; + assign n525 = n1089 | n1107; + assign n526 = n370 & (~n110 | n525); + assign n527 = ~n110 | n1215; + assign n528 = ~n382 & n1392; + assign n529 = n526 & n527 & (~n212 | n528); + assign n530 = n1104 | n1108; + assign n531 = ~n117 & (~n110 | (~n382 & n530)); + assign n532 = n1088 | n1107; + assign n533 = ~n213 & n531 & (~n212 | n532); + assign n534 = n1448 & n1447 & n1446 & n1445 & n1443 & n1444 & n1449 & n1450; + assign n535 = n1103 | n1206; + assign n536 = n534 & (~n368 | n535); + assign n537 = ~n1202 & (~n225 | n430); + assign n538 = ~n532 & (n110 | ~n1517); + assign n539 = ~n984 & n1093; + assign n540 = ~n1110 & (n421 | n539); + assign n541 = ~n1354 & (~n225 | ~n1161); + assign n542 = n1455 & n1454 & n800 & n1453 & n1451 & n1452 & n1456 & n1457; + assign n543 = n1089 | n1122; + assign n544 = n542 & (~n368 | n543); + assign n545 = ~n220 & n302; + assign n546 = ~n225 | n273; + assign n547 = ~n543 & (n546 | ~n1161); + assign n548 = (~n430 | n1129) & (n349 | n780); + assign n549 = (n405 | n990) & (~n220 | n1121); + assign n550 = (n304 | ~n815) & (~n421 | n1111); + assign n551 = (n545 | n1133) & (n1463 | n1046); + assign n552 = ~n547 & (n525 | (~n212 & n1517)); + assign n553 = n2115 & n1388 & n223; + assign n554 = n551 & n550 & n549 & n548 & n544 & n315 & n552 & n553; + assign n555 = i_8_ & ~n1083; + assign n556 = n1092 & ~n1512; + assign n557 = ~n776 & n555 & n556; + assign n558 = n1099 & n556; + assign n559 = n558 & ~n667; + assign n560 = n260 & n429 & (n796 | n235); + assign n561 = n554 & n1528 & n529 & n533; + assign n562 = (~n430 | n530) & (~n539 | n1111); + assign n563 = (~n110 | n781) & (n1225 | n2107); + assign n564 = n2133 & n2134 & (n2010 | n1121); + assign n565 = n2130 & n2120 & n2121 & n2124 & n2123 & n2131 & n2129 & n2128; + assign n566 = ~n1525 & n565 & n564 & n563 & n562 & n560 & n561 & ~n1520; + assign n567 = ~n1117 & n556 & ~n776; + assign n568 = n1074 | ~n1602; + assign n569 = n568 & (~n1099 | ~n1602); + assign n570 = n1109 | n1128; + assign n571 = n495 & n570; + assign n572 = n1087 | n1201; + assign n573 = (n469 | n572) & (~n368 | n571); + assign n574 = ~n368 | n1153; + assign n575 = n1578 & n1577 & n444 & n1575 & n1576; + assign n576 = n574 & n575 & (~n368 | ~n465); + assign n577 = n469 | n1153; + assign n578 = n469 | n824; + assign n579 = n469 | n1134; + assign n580 = n469 | n316; + assign n581 = n469 | n1133; + assign n582 = n469 | n726; + assign n583 = n469 | n727; + assign n584 = n443 & (n469 | n482); + assign n585 = n582 & n581 & n580 & n579 & n577 & n578 & n583 & n584; + assign n586 = ~n368 | n397; + assign n587 = ~n220 | n1200; + assign n588 = ~n220 | n1115; + assign n589 = n1106 | n1108; + assign n590 = n587 & n588 & (~n220 | n589); + assign n591 = n469 | n1124; + assign n592 = n469 | n1204; + assign n593 = n1110 | n469; + assign n594 = n226 | n469; + assign n595 = n1111 | n469; + assign n596 = n469 | n1338; + assign n597 = n469 | n1353; + assign n598 = n442 & (n469 | n401); + assign n599 = n596 & n595 & n594 & n593 & n591 & n592 & n597 & n598; + assign n600 = n456 | n245; + assign n601 = n456 | n613; + assign n602 = n456 | n1216; + assign n603 = (~n220 | n1574) & (~n273 | n747); + assign n604 = ~n220 | n613; + assign n605 = n1132 | n1201; + assign n606 = n604 & (n605 | ~n1053); + assign n607 = n615 & n412 & ~n385 & n401; + assign n608 = n486 & n1573; + assign n609 = n608 & n607 & n374; + assign n610 = n1128 | n1201; + assign n611 = n269 & n610; + assign n612 = (n469 | n495) & (~n368 | n611); + assign n613 = n1107 | n1201; + assign n614 = n613 | n469; + assign n615 = n1096 | n1201; + assign n616 = ~n220 | n615; + assign n617 = ~n220 | n605; + assign n618 = n2291 | n456; + assign n619 = n1932 & n1922 & n1955; + assign n620 = n756 & n1391; + assign n621 = n618 & n619 & (~n220 | n620); + assign n622 = n1209 & n632 & n1130; + assign n623 = n456 | n622; + assign n624 = n1466 & n737; + assign n625 = n456 | n624; + assign n626 = ~n220 | n1207; + assign n627 = ~n220 | n1125; + assign n628 = n1091 | n1096; + assign n629 = n626 & n627 & (~n220 | n628); + assign n630 = ~n220 | n1209; + assign n631 = ~n220 | n1130; + assign n632 = n1087 | n1091; + assign n633 = n630 & n631 & (~n220 | n632); + assign n634 = n456 | n1214; + assign n635 = n456 | n780; + assign n636 = n1091 | n1107; + assign n637 = n634 & n635 & (n456 | n636); + assign n638 = ~n220 | n1214; + assign n639 = ~n220 | n780; + assign n640 = n638 & n639 & (~n220 | n636); + assign n641 = n456 | n1129; + assign n642 = n1091 | n1128; + assign n643 = n1128 | n1196; + assign n644 = n641 & (n456 | (n642 & n643)); + assign n645 = n1339 & n1465 & n1280; + assign n646 = n456 | n645; + assign n647 = n1545 & n1544 & n1543 & n293 & n1542 & n318 & n646; + assign n648 = n535 & n543 & n1309; + assign n649 = n647 & (n648 | n456); + assign n650 = n1005 & n992 & n1006 & n1548 & n792; + assign n651 = n491 & n1546; + assign n652 = n1104 | n1196; + assign n653 = n1133 & n1134; + assign n654 = n653 & n652 & n651 & n650 & ~n385 & n610; + assign n655 = n1273 & n1272 & n1271 & n1270 & n1269 & n1268 & ~n221 & n828; + assign n656 = n1223 & n1241 & n1240 & n1238 & n1239; + assign n657 = (n456 | n1547) & (~n220 | n654); + assign n658 = n1148 & n1175 & n827 & n1173 & n1174; + assign n659 = n2146 & n1764 & n2145 & n1844 & n1405 & n2144; + assign n660 = n2147 & n621 & n1572 & n1570 & n1563 & n1557; + assign n661 = n659 & n658 & n657 & n309 & n655 & n656 & n660; + assign n662 = n993 | n456; + assign n663 = n662 & (~n220 | n572); + assign n664 = n1115 & n589; + assign n665 = n1104 | n1201; + assign n666 = (n469 | n665) & (~n368 | n664); + assign n667 = n1214 & n525 & n515; + assign n668 = ~n558 | n667; + assign n669 = n1605 & ~n1535 & n668 & n663 & n154 & n661; + assign n670 = n771 & n1604; + assign n671 = n405 | n1143; + assign n672 = n405 | n615; + assign n673 = n405 | n1217; + assign n674 = (~n277 | n939) & (n243 | n1573); + assign n675 = n674 & n673 & n671 & n672; + assign n676 = ~n405 & (~n645 | ~n1133 | ~n1210); + assign n677 = ~n243 & (~n233 | ~n1607); + assign n678 = ~n277 | n482; + assign n679 = ~n984 & n1086; + assign n680 = n679 & (~n1228 | ~n1613 | ~n2148); + assign n681 = n679 & (~n874 | ~n1466); + assign n682 = ~n1224 | ~n610 | ~n987; + assign n683 = n679 & (n682 | ~n1537 | ~n1614); + assign n684 = ~n1086 | n1114; + assign n685 = n1467 & n944; + assign n686 = n684 | n685; + assign n687 = ~n243 & (~n688 | ~n1115); + assign n688 = n613 & n1200; + assign n689 = n405 | n688; + assign n690 = n243 | n1204; + assign n691 = n237 | n243; + assign n692 = n243 | n1124; + assign n693 = n243 | n1338; + assign n694 = n1110 | n243; + assign n695 = n243 | n1205; + assign n696 = n1116 | n243; + assign n697 = n2154 & (n1111 | n243); + assign n698 = n695 & n694 & n693 & n692 & n690 & n691 & n696 & n697; + assign n699 = n1089 | n1102; + assign n700 = n699 | n405; + assign n701 = ~n405 & (n278 | ~n1111); + assign n702 = n231 | ~n430; + assign n703 = n845 & n397 & n628; + assign n704 = n702 & (~n430 | n703); + assign n705 = n349 | n1216; + assign n706 = n349 | n245; + assign n707 = (~n430 | n1007) & (~n421 | n747); + assign n708 = n707 & n705 & n706; + assign n709 = n143 & n1138; + assign n710 = n709 & (~n241 | ~n481 | ~n1112); + assign n711 = n636 & n632; + assign n712 = ~n421 | n711; + assign n713 = n349 | n1124; + assign n714 = n349 | n1204; + assign n715 = n2290 | n349; + assign n716 = n349 | n1338; + assign n717 = n349 | n1353; + assign n718 = n349 | n237; + assign n719 = n349 | n1116; + assign n720 = n2005 & (n349 | (n401 & n491)); + assign n721 = n718 & n717 & n716 & n715 & n713 & n714 & n719 & n720; + assign n722 = n653 & n316 & n1465; + assign n723 = n1207 & n1125; + assign n724 = n482 & n723 & n703 & n722; + assign n725 = n1095 | n1108; + assign n726 = n1167 | n1201; + assign n727 = n1103 | n1167; + assign n728 = n1153 & n653; + assign n729 = n728 & n727 & n725 & n645 & n316 & ~n465 & n726; + assign n730 = n349 | n1280; + assign n731 = n232 | ~n430; + assign n732 = (~n430 | n729) & (n349 | n724); + assign n733 = ~n421 | n809; + assign n734 = n1316 & n1948 & n1849 & n360 & n1357 & n1850; + assign n735 = n734 & n733 & n732 & n731 & n359 & n730; + assign n736 = n572 & n491; + assign n737 = n652 & n1281; + assign n738 = n530 & n1105; + assign n739 = n738 & n737 & n736 & n613 & n610 & n401 & ~n114 & ~n385; + assign n740 = n1199 & n994; + assign n741 = ~n918 & n740 & n650 & ~n275 & n412; + assign n742 = n1637 & n1636 & ~n710 & n712; + assign n743 = n1337 & n1279 & n308 & n1416 & n1035 & n1368; + assign n744 = n2152 & n2153 & (n349 | n610); + assign n745 = n2151 & n2150 & n2149 & n2037 & ~n214 & n2004; + assign n746 = n1574 & n990 & n1203; + assign n747 = n665 & n497; + assign n748 = n610 & n589 & n746 & n747; + assign n749 = n397 | n243; + assign n750 = ~n650 | ~n353 | ~n374; + assign n751 = ~n1458 | ~n1045 | ~n1231; + assign n752 = ~n243 & (n750 | n751 | ~n986); + assign n753 = n755 | n970; + assign n754 = n755 | n1121; + assign n755 = ~n1086 | n1120; + assign n756 = n1091 | n1113; + assign n757 = n753 & n754 & (n755 | n756); + assign n758 = n1468 & n1227; + assign n759 = n755 | n758; + assign n760 = n216 & (~n756 | ~n1231 | ~n1685); + assign n761 = n496 & n740; + assign n762 = n755 | n761; + assign n763 = n216 | ~n755; + assign n764 = ~n945 | ~n1467; + assign n765 = n763 & (n764 | ~n1308); + assign n766 = ~n238 | ~n1232; + assign n767 = n216 & (n766 | ~n944); + assign n768 = n985 | n775; + assign n769 = n770 & n1701; + assign n770 = n970 & n667; + assign n771 = n1074 | n1513; + assign n772 = ~n173 | n1513; + assign n773 = n304 & n523; + assign n774 = n772 & (n771 | (n773 & n524)); + assign n775 = n1117 | n1513; + assign n776 = n1113 | n1201; + assign n777 = n775 | n776; + assign n778 = n1215 & n1224; + assign n779 = n463 & n352; + assign n780 = n1103 | n1107; + assign n781 = n1108 | n1128; + assign n782 = n525 & n780 & n491 & n245 & n778 & n779 & n781 & n632; + assign n783 = n1708 & n1707 & n445 & n1705 & n1706; + assign n784 = n1172 & n1267 & (~n110 | n532); + assign n785 = ~n212 | n1204; + assign n786 = ~n110 | n1208; + assign n787 = n493 & n2161 & (~n212 | n782); + assign n788 = n787 & n786 & n785 & n784 & n783 & n533 & ~n112 & n529; + assign n789 = n268 | n419; + assign n790 = ~n218 | n419; + assign n791 = n789 & n790 & (n779 | n419); + assign n792 = n642 & n463; + assign n793 = n225 | n792; + assign n794 = n645 | n796; + assign n795 = n1133 & n1606; + assign n796 = ~n1093 | n1114; + assign n797 = n794 & (n795 | n796); + assign n798 = n605 | n469; + assign n799 = n469 | n643; + assign n800 = n469 | n1129; + assign n801 = ~n215 & (~n110 | n1614); + assign n802 = n2183 & (n456 | n495); + assign n803 = n2184 & n1485 & n644 & n791 & n1714 & n909; + assign n804 = n2182 & n2158 & n2000 & n1875 & n1471 & n1325 & ~n115 & n1292; + assign n805 = n877 & n2021 & n2074 & n2025 & n1792 & n1247 & n1249 & n2181; + assign n806 = n1963 & n1943 & n2136 & n1942 & n1366 & n1980 & n1367 & n2180; + assign n807 = n804 & n803 & n802 & n801 & n799 & n800 & n805 & n806; + assign n808 = n539 & (n465 | ~n1607); + assign n809 = n605 & n608; + assign n810 = (n615 | n796) & (~n271 | n809); + assign n811 = n225 | n1207; + assign n812 = n225 | n1125; + assign n813 = n628 & n1213; + assign n814 = n811 & n812 & (n813 | n225); + assign n815 = ~n225 | n818; + assign n816 = n815 & (~n482 | ~n486); + assign n817 = ~n225 & (~n1401 | ~n1465); + assign n818 = n1093 & n1099; + assign n819 = ~n645 | ~n1573; + assign n820 = n818 & (~n605 | ~n728 | n819); + assign n821 = ~n850 & (n465 | ~n645); + assign n822 = ~n419 & (n465 | ~n615); + assign n823 = ~n501 | n809; + assign n824 = n1088 | n1167; + assign n825 = n482 & n235 & n824 & n653 & n486 & n316; + assign n826 = ~n605 & (~n225 | n368); + assign n827 = ~n220 | n1143; + assign n828 = ~n220 | n1123; + assign n829 = n1634 | n469; + assign n830 = n456 | ~n465; + assign n831 = ~n826 & (n1217 | (~n368 & n469)); + assign n832 = n1240 & (~n1053 | (n486 & n1143)); + assign n833 = n1147 & n1764 & n1975 & n1872 & n2142 & n1347 & n1146 & n1145; + assign n834 = n1736 & n810 & n1677 & n675 & n1000 & n1723 & n1738 & n2179; + assign n835 = n832 & n831 & n830 & n829 & n827 & n828 & n833 & n834; + assign n836 = n1395 | n419; + assign n837 = n1396 | n419; + assign n838 = n836 & n837 & (n622 | n419); + assign n839 = ~n1338 | ~n1353; + assign n840 = ~n225 & (~n632 | ~n651 | n839); + assign n841 = ~n539 | n622; + assign n842 = n1395 & n1396; + assign n843 = n841 & (~n539 | n842); + assign n844 = ~n539 | n849; + assign n845 = n1635 & n1123 & n1213; + assign n846 = n844 & (~n539 | n845); + assign n847 = n2295 | n850; + assign n848 = n2294 | n850; + assign n849 = n231 & n452; + assign n850 = n1074 | ~n1093; + assign n851 = n847 & n848 & (n849 | n850); + assign n852 = n629 & n2167 & (n243 | n1197); + assign n853 = n1881 & n1803 & n2165 & n1835 & n1900 & n2081 & n1802 & n2164; + assign n854 = n1795 & n2163 & n1284 & n1344 & n1834 & n1891 & n1010 & n1793; + assign n855 = n2034 & n2007 & n1961 & n1409 & n1636 & n2151 & n2162 & n1873; + assign n856 = n853 & n852 & n704 & n130 & n846 & n851 & n854 & n855; + assign n857 = (n736 | n1398) & (n243 | ~n278); + assign n858 = (n2171 | n401) & (n2172 | n481); + assign n859 = (~n539 | n1025) & (n1168 | n1546); + assign n860 = n2080 & (n632 | (~n212 & n1152)); + assign n861 = n2173 & n494 & n633 & n843 & n856 & n698; + assign n862 = n1860 & n1446 & n1508 & n1820 & n1452 & n1445 & n1837 & n2170; + assign n863 = n1906 & n1839 & n1289 & n1323 & n1351 & n1435 & n1493 & n2169; + assign n864 = n2004 & n1474 & n1411 & n1301 & n2037 & n1853 & n1266 & n2168; + assign n865 = n862 & n861 & n860 & n859 & n857 & n858 & n863 & n864; + assign n866 = ~n1154 & (~n268 | ~n987); + assign n867 = n212 & (n111 | ~n779 | ~n1614); + assign n868 = n2191 & (~n368 | n463); + assign n869 = n865 & n1621 & n1662 & n807 & n835 & n1746; + assign n870 = n2188 & n2190 & (n1769 | n938); + assign n871 = n2001 & n1911 & n1897 & n1858 & ~n221 & ~n866; + assign n872 = n1310 & n1791 & n1863 & n1346 & n1282 & n1430 & n2185 & n2187; + assign n873 = n870 & n869 & n868 & n573 & n612 & n354 & n871 & n872; + assign n874 = n1574 & n747; + assign n875 = (n225 | n613) & (~n815 | n874); + assign n876 = ~n539 | n2297; + assign n877 = n2166 | n796; + assign n878 = n876 & n877 & (~n275 | ~n539); + assign n879 = ~n525 | ~n532; + assign n880 = n818 & (n275 | ~n636 | n879); + assign n881 = (~n212 | n780) & (~n368 | n636); + assign n882 = (n589 | ~n1051) & (~n430 | n2211); + assign n883 = (n2171 | n412) & (n2172 | n241); + assign n884 = n1674 & n398 & n640 & n878 & n1001 & n199; + assign n885 = n1799 & n1188 & n2210 & n1078 & n1869 & n1314 & n1257 & n2208; + assign n886 = n1181 & n1183 & n1171 & n1862 & n1498 & n1712 & n1426 & n2207; + assign n887 = n1941 & n1960 & n1825 & n1899 & n1274 & n1833 & n1854 & n2205; + assign n888 = n885 & n884 & n883 & n882 & n881 & n460 & n886 & n887; + assign n889 = n419 | ~n892; + assign n890 = n738 | n419; + assign n891 = n889 & n890 & (n624 | n419); + assign n892 = ~n1045 | ~n1203; + assign n893 = ~n225 & (n892 | ~n1548); + assign n894 = n1114 | ~n1138; + assign n895 = n261 & n894; + assign n896 = n2296 | n796; + assign n897 = ~n275 & n355; + assign n898 = n896 & (n897 | n796); + assign n899 = n2297 | n419; + assign n900 = ~n275 | n419; + assign n901 = n419 | n613; + assign n902 = n2196 & n1011 & (n993 | n225); + assign n903 = n1263 & n1907 & n1841 & n2031 & n1489 & n1264; + assign n904 = n898 & n1386 & n2197 & n473 & n457 & n373 & n1669 & n2198; + assign n905 = n662 & n1882 & n1926 & n2083 & n1840 & n1444 & n2195 & n2194; + assign n906 = n904 & n903 & n902 & n901 & n899 & n900 & n905; + assign n907 = ~n243 & (~n530 | ~n1045); + assign n908 = n1626 & n1625 & n1624 & n1623 & ~n681 & n1622; + assign n909 = n1709 & n264 & n798 & n797; + assign n910 = n246 & n350 & n198 & n666; + assign n911 = n906 & n856 & n835 & n875 & n888 & n1761; + assign n912 = n2222 & n2217 & n2218 & n2219 & n2220 & n2221 & n2216 & n2215; + assign n913 = n1326 & n1912 & n1191 & n1254 & n1293 & n1876 & n1379 & n2214; + assign n914 = n1429 & n1311 & n1496 & n2022 & n2213 & n1250 & n267 & n2212; + assign n915 = n1231 | n850; + assign n916 = n2291 | n419; + assign n917 = n915 & n916 & (n620 | n850); + assign n918 = ~n756 | ~n1468; + assign n919 = ~n225 & (n918 | ~n1151); + assign n920 = n1231 | n419; + assign n921 = n1151 | n419; + assign n922 = n920 & n921 & (~n118 | n419); + assign n923 = ~n225 & (~n776 | ~n994); + assign n924 = ~n349 & (~n2223 | ~n2224); + assign n925 = n1093 & n143; + assign n926 = n925 & (~n1231 | ~n1468 | ~n1613); + assign n927 = n236 & n756 & n589 & n725; + assign n928 = ~n496 & (n368 | ~n1769); + assign n929 = (n1156 | n1612) & (n1152 | n1468); + assign n930 = n1231 | n243; + assign n931 = (~n118 | n1460) & (~n368 | n664); + assign n932 = (~n280 | n1638) & (~n430 | n927); + assign n933 = n2079 & n1910 & n1378 & n1241 & n1233 & ~n928 & n1189; + assign n934 = n1022 & n1779 & n1692 & n1719 & n888 & n865 & n917 & n2234; + assign n935 = n1877 & n1291 & n1870 & n1312 & n1271 & n1507 & n1175 & n2232; + assign n936 = n1335 & n1361 & n1334 & n1276 & n1299 & n1360 & n1851 & n2230; + assign n937 = n934 & n933 & n932 & n931 & n929 & n930 & n935 & n936; + assign n938 = n610 & n495; + assign n939 = n605 & n486; + assign n940 = n496 & n944; + assign n941 = n940 & n939 & n938 & ~n764 & n482 & n747; + assign n942 = n985 & n1479; + assign n943 = n942 & ~n764 & ~n385 & n761; + assign n944 = n942 & n1144 & n1218; + assign n945 = n1089 | n1206; + assign n946 = n945 & n495 & n944 & n665; + assign n947 = n250 & (~n809 | ~n1780); + assign n948 = ~n419 & (~n824 | ~n1573); + assign n949 = ~n349 & (~n650 | ~n722 | ~n1127); + assign n950 = ~n225 & (~n1210 | ~n1465 | ~n1574); + assign n951 = n518 & (n769 | n1603); + assign n952 = n951 & n208 & n207 & n175 & ~n183 & n517; + assign n953 = ~n958 & n2243 & (n569 | n769); + assign n954 = n953 & n669 & n177; + assign n955 = n1119 & n556; + assign n956 = n173 & n556; + assign n957 = n1119 & n1530; + assign n958 = n1119 & n1518; + assign n959 = ~n304 & n1782; + assign n960 = n1119 & n1702; + assign n961 = ~n304 & n558; + assign n962 = ~n304 & n1529; + assign n963 = ~n990 & n1529; + assign n964 = ~n1083 & n1530; + assign n965 = ~n1083 & n1518; + assign n966 = ~n990 & n1782; + assign n967 = n558 & ~n990; + assign n968 = ~n1083 & n1702; + assign n969 = n670 & ~n979; + assign n970 = n1113 | n1196; + assign n971 = ~n652 & ~n2245; + assign n972 = n173 & n1530; + assign n973 = n173 & n1518; + assign n974 = ~n1230 & n1782; + assign n975 = n173 & n1702; + assign n976 = n558 & ~n1230; + assign n977 = ~n1230 & n1529; + assign n978 = ~n1045 & ~n2245; + assign n979 = n143 & n1602; + assign n980 = ~n1701 & (n979 | ~n1604); + assign n981 = n665 | n775; + assign n982 = n970 & n1701; + assign n983 = n2288 & (i_0_ | ~i_2_); + assign n984 = i_8_ | ~n173; + assign n985 = n1122 | n1201; + assign n986 = n1639 & n1638 & n736 & n607 & n740 & n737; + assign n987 = n305 & n1135; + assign n988 = n1096 | n1109; + assign n989 = n632 & n1338; + assign n990 = n1089 | n1104; + assign n991 = n988 & n613 & n987 & n268 & n986 & n650 & n989 & n990; + assign n992 = n776 & n1547; + assign n993 = n1200 & n664; + assign n994 = n1109 | n1113; + assign n995 = n648 & n1354 & n1340; + assign n996 = n995 & n993 & n992 & n605 & ~n764 & n994; + assign n997 = n1754 & n1753 & n1752 & n1751 & ~n893 & n1750; + assign n998 = n1768 & ~n919 & n1767; + assign n999 = n1739 & ~n840 & n227 & n402; + assign n1000 = n1727 & n1356 & n1726 & n1725 & n319 & n1724 & n1728 & n1729; + assign n1001 = n1749 & n1748 & ~n880 & n1484; + assign n1002 = n328 & n310 & n1315 & n1714 & n413 & n423; + assign n1003 = n2253 & n2252 & n2251 & n2163 & n2039 & n1237 & ~n116 & n371; + assign n1004 = ~n539 | n572; + assign n1005 = n1262 & n995; + assign n1006 = n1537 & n945 & ~n1027; + assign n1007 = n589 & n1574; + assign n1008 = n1007 & n1006 & n1005 & n688 & n651 & ~n114 & ~n385; + assign n1009 = n620 | n796; + assign n1010 = ~n539 | n2166; + assign n1011 = n993 | n796; + assign n1012 = ~n121 & (~n271 | (n992 & n1780)); + assign n1013 = n1501 & n1500 & n1499 & n1498 & n1496 & n1497 & n1502 & n1503; + assign n1014 = n1251 & n1250 & n1249 & n1248 & n1246 & n1247 & n1252 & n1253; + assign n1015 = n1187 & (~n539 | n1008); + assign n1016 = n1738 & n846 & n843 & n878 & n1798 & n898 & n810 & n797; + assign n1017 = n1014 & n1013 & n1012 & n1011 & n1009 & n1010 & n1015 & n1016; + assign n1018 = n1161 | n1308; + assign n1019 = n1261 | n1161; + assign n1020 = n1161 | n1309; + assign n1021 = n1161 | n535; + assign n1022 = n1772 & n1771 & n1770 & ~n926 & n297 & n322; + assign n1023 = n1845 & n1303 & (n2240 | n1161); + assign n1024 = n1022 & n1021 & n363 & n1020 & n1018 & n1019 & n135 & n1023; + assign n1025 = n572 & n651; + assign n1026 = n1025 & n1007 & ~n750 & n737 & n613 & ~n118 & n352; + assign n1027 = n766 | ~n1467; + assign n1028 = ~n419 & (~n945 | ~n992 | n1027); + assign n1029 = n1802 & n1801 & n899 & n1800 & n1799 & n901 & n1803 & n1804; + assign n1030 = n1723 & n791 & n1495; + assign n1031 = n1260 & n2226 & n2196 & n1709 & n2165 & n1731 & n1195 & n2255; + assign n1032 = n838 & n851 & n891 & n922 & n1029 & n917 & n1030 & n1031; + assign n1033 = n796 & n243; + assign n1034 = ~n456 & (~n1209 | ~n1339); + assign n1035 = n1412 & n1411 & n1410 & n1409 & n1407 & n1408 & n1413 & n1414; + assign n1036 = n1383 & n1382 & n1381 & n1380 & n1379 & n1378 & ~n369 & n799; + assign n1037 = n365 & (~n539 | n1338); + assign n1038 = (~n430 | n643) & (n349 | n1214); + assign n1039 = (n1033 | n726) & (n1463 | n1044); + assign n1040 = ~n1034 & (n225 | (n1045 & n1340)); + assign n1041 = n2256 & (~n220 | n970); + assign n1042 = n1039 & n1038 & n1037 & n335 & n1035 & n1036 & n1040 & n1041; + assign n1043 = ~n1053 & ~n815 & ~n421 & ~n220 & n243; + assign n1044 = n515 & n1211; + assign n1045 = n1102 | n1201; + assign n1046 = n1089 | n1096; + assign n1047 = n1046 & n525 & n1044 & n1045; + assign n1048 = n699 & n1468 & n463; + assign n1049 = n776 & n610 & n1048 & n665; + assign n1050 = ~n2107 & (~n305 | ~n1226); + assign n1051 = ~n243 | ~n850; + assign n1052 = n1051 & (~n353 | ~n1391); + assign n1053 = n368 | ~n469; + assign n1054 = ~n572 & (n1053 | ~n1398); + assign n1055 = ~n1281 & (~n243 | n381 | n501); + assign n1056 = ~n1054 & (n613 | (~n277 & n1166)); + assign n1057 = ~n1052 & (n1159 | (n482 & n1805)); + assign n1058 = n1670 & n2257 & (n2096 | n1049); + assign n1059 = n2258 & n2259 & n2261 & n2260; + assign n1060 = n2154 & n876 & n1571 & n1079 & n1655 & n1665 & n2158 & n1646; + assign n1061 = n1645 & n2150 & n794 & n841 & n1642 & n1739 & n1222 & n1147; + assign n1062 = n1798 & n1029 & n1552 & n606 & n1766 & n742 & n1042 & n2273; + assign n1063 = n2264 & n2265 & n2266 & n2267 & n2269 & n2268 & n2263 & n2262; + assign n1064 = n1061 & n1060 & n1059 & n1058 & n1056 & n1057 & n1062 & n1063; + assign n1065 = ~n532 & (n212 | n503); + assign n1066 = ~n226 & (~n225 | ~n349 | ~n1154); + assign n1067 = n539 & (~n231 | ~n726 | ~n1353); + assign n1068 = n2287 & (n796 | n824); + assign n1069 = ~n1536 & ~n1534 & n1042 & n1528; + assign n1070 = (n1154 | n1219) & (n1164 | n1209); + assign n1071 = n2286 & (~n273 | n1227); + assign n1072 = n2284 & n2285 & (n2010 | n970); + assign n1073 = n2278 & n2279 & n2280 & n2281 & n2283 & n2282 & n2276 & n2275; + assign n1074 = i_8_ | n123; + assign n1075 = n1425 & n1464; + assign n1076 = n1389 & n1386 & n1036 & n1402 & n1377; + assign n1077 = n2140 & (~n368 | (n572 & n874)); + assign n1078 = ~n368 | n1200; + assign n1079 = ~n368 | n613; + assign n1080 = (~n368 | n609) & (n940 | ~n1053); + assign n1081 = n2139 & n2138 & n2137 & n2136 & n2135 & n2034 & ~n108 & n2007; + assign n1082 = n1601 & n576 & n1592 & n198 & n590 & n599 & n573 & n2141; + assign n1083 = ~i_6_ | i_7_; + assign n1084 = ~i_5_ | i_3_ | i_4_; + assign n1085 = ~i_2_ & ~i_0_ & ~i_1_; + assign n1086 = ~n1084 & n1085; + assign n1087 = i_15_ | n481; + assign n1088 = ~i_14_ | i_12_ | ~i_13_; + assign n1089 = ~i_14_ | i_12_ | i_13_; + assign n1090 = ~i_15_ | n481; + assign n1091 = i_14_ | ~i_12_ | ~i_13_; + assign n1092 = ~i_5_ & ~i_3_ & i_4_; + assign n1093 = n1085 & n1092; + assign n1094 = ~i_11_ | ~i_9_ | ~i_10_; + assign n1095 = ~i_15_ | n1094; + assign n1096 = i_15_ | n1094; + assign n1097 = n1088 | n1096; + assign n1098 = n1046 & n1097; + assign n1099 = ~i_8_ & ~n1083; + assign n1100 = i_5_ & ~i_3_ & i_4_; + assign n1101 = n1085 & n1100; + assign n1102 = ~i_15_ | n265; + assign n1103 = i_14_ | ~i_12_ | i_13_; + assign n1104 = i_15_ | n265; + assign n1105 = n990 & n244; + assign n1106 = ~i_15_ | n241; + assign n1107 = i_15_ | n241; + assign n1108 = ~i_14_ | ~i_12_ | ~i_13_; + assign n1109 = ~i_14_ | ~i_12_ | i_13_; + assign n1110 = n1087 | n1088; + assign n1111 = n1087 | n1089; + assign n1112 = i_11_ | ~i_9_ | i_10_; + assign n1113 = i_15_ | n1112; + assign n1114 = ~i_8_ | ~n173; + assign n1115 = n1107 | n1109; + assign n1116 = n1087 | n1109; + assign n1117 = ~i_8_ | n123; + assign n1118 = n1106 | n1109; + assign n1119 = i_6_ & i_7_; + assign n1120 = ~i_8_ | ~n1119; + assign n1121 = n1103 | n1113; + assign n1122 = i_15_ | ~n142; + assign n1123 = n1096 | n1108; + assign n1124 = n1087 | n1108; + assign n1125 = n1096 | n1103; + assign n1126 = ~i_15_ | n478; + assign n1127 = n1109 | n1126; + assign n1128 = i_15_ | n478; + assign n1129 = n1103 | n1128; + assign n1130 = n1087 | n1103; + assign n1131 = ~i_11_ | i_9_ | ~i_10_; + assign n1132 = i_15_ | n1131; + assign n1133 = n1089 | n1132; + assign n1134 = n1088 | n1132; + assign n1135 = n1088 | n1128; + assign n1136 = n1107 | n1108; + assign n1137 = ~i_5_ & ~i_3_ & ~i_4_; + assign n1138 = n1085 & n1137; + assign n1139 = ~n555 | ~n1138; + assign n1140 = n241 | n1139; + assign n1141 = n265 | n477; + assign n1142 = n265 | n1139; + assign n1143 = n1109 | n1132; + assign n1144 = n1109 | n1122; + assign n1145 = n1123 | n456; + assign n1146 = n456 | n1097; + assign n1147 = n456 | n1046; + assign n1148 = n1147 & n1145 & n1146; + assign n1149 = n1108 | n1113; + assign n1150 = n1088 | n1113; + assign n1151 = n304 & n1149 & n1150; + assign n1152 = ~n430 & ~n818; + assign n1153 = n1108 | n1132; + assign n1154 = ~n539 & n1152; + assign n1155 = ~n1051 & n1154; + assign n1156 = ~n250 & n1155; + assign n1157 = n488 & n1156; + assign n1158 = ~n273 & ~n1053; + assign n1159 = n1157 & n1158; + assign n1160 = n684 & n1159; + assign n1161 = ~n1093 | n1120; + assign n1162 = n1161 & n1160; + assign n1163 = ~i_15_ | n1112; + assign n1164 = ~n1051 & ~n271 & n302; + assign n1165 = n850 & n1154; + assign n1166 = n469 & n1165; + assign n1167 = ~i_15_ | n1131; + assign n1168 = ~n220 & n850; + assign n1169 = ~n110 | n1115; + assign n1170 = ~n110 | n245; + assign n1171 = ~n212 | n1115; + assign n1172 = n1171 & n1169 & n1170; + assign n1173 = n1116 | n456; + assign n1174 = n988 | n456; + assign n1175 = ~n220 | n994; + assign n1176 = n1781 | n755; + assign n1177 = n755 | n1144; + assign n1178 = n225 | n1143; + assign n1179 = n456 | n1143; + assign n1180 = n1179 & n1178 & n706 & n671 & n1176 & n1177 & n600; + assign n1181 = n355 | ~n539; + assign n1182 = n245 | n796; + assign n1183 = ~n539 | n1115; + assign n1184 = n1151 | n796; + assign n1185 = ~n539 | n1151; + assign n1186 = n2026 & n2025 & n2024 & n2023 & n2021 & n2022; + assign n1187 = n1186 & n1185 & n1184 & n1183 & n1181 & n1182; + assign n1188 = n1115 | n850; + assign n1189 = n1151 | n850; + assign n1190 = n1781 | n419; + assign n1191 = n738 | n850; + assign n1192 = n355 | n850; + assign n1193 = n419 | n245; + assign n1194 = n2033 & n2032 & n1732 & n2031 & n2029 & n2030; + assign n1195 = n1193 & n1192 & n1191 & n1190 & n1188 & n1189 & n1194; + assign n1196 = i_14_ | i_12_ | ~i_13_; + assign n1197 = n1095 | n1196; + assign n1198 = n1088 | n1106; + assign n1199 = n1163 | n1196; + assign n1200 = n1106 | n1196; + assign n1201 = i_13_ | i_12_ | i_14_; + assign n1202 = n1102 | n1103; + assign n1203 = n1202 & n484; + assign n1204 = n1088 | n1090; + assign n1205 = n1090 | n1196; + assign n1206 = ~i_15_ | ~n142; + assign n1207 = n1096 | n1196; + assign n1208 = n1088 | n1126; + assign n1209 = n1087 | n1196; + assign n1210 = n727 & n316; + assign n1211 = n1095 | n1201; + assign n1212 = n1095 | n1103; + assign n1213 = n1211 & n1212; + assign n1214 = n1107 | n1196; + assign n1215 = n1103 | n1106; + assign n1216 = n1102 | n1196; + assign n1217 = n1167 | n1196; + assign n1218 = n1196 | n1206; + assign n1219 = n1091 | n1095; + assign n1220 = n456 | n1219; + assign n1221 = n456 | n1212; + assign n1222 = n456 | n1211; + assign n1223 = n1222 & n1220 & n1221; + assign n1224 = n1091 | n1126; + assign n1225 = n1103 | n1126; + assign n1226 = n1126 | n1201; + assign n1227 = n1088 | n1163; + assign n1228 = n1091 | n1163; + assign n1229 = n1103 | n1163; + assign n1230 = n1163 | n1201; + assign n1231 = n1230 & n1228 & n1229; + assign n1232 = n1122 | n1196; + assign n1233 = ~n818 | n1231; + assign n1234 = ~n818 | ~n892; + assign n1235 = ~n818 | n1205; + assign n1236 = n225 | n1199; + assign n1237 = n1236 & n1235 & n1233 & n1234; + assign n1238 = n456 | n1205; + assign n1239 = n456 | n1197; + assign n1240 = ~n220 | n1217; + assign n1241 = ~n220 | n1199; + assign n1242 = n1806 | n755; + assign n1243 = n755 | n1218; + assign n1244 = n456 | n1217; + assign n1245 = n602 & n1244 & n705 & n673 & n1242 & n1243 & n262; + assign n1246 = n1395 | n796; + assign n1247 = n268 | n796; + assign n1248 = n796 | n1205; + assign n1249 = n796 | n269; + assign n1250 = ~n539 | ~n892; + assign n1251 = n796 | ~n892; + assign n1252 = n796 | n1216; + assign n1253 = n1997 & n1998; + assign n1254 = n850 | ~n892; + assign n1255 = ~n275 | n850; + assign n1256 = n419 | n1216; + assign n1257 = n850 | n1200; + assign n1258 = n1806 | n419; + assign n1259 = n2002 & n2001 & n1730 & n900 & n1999 & n2000; + assign n1260 = n1259 & n1258 & n1257 & n1256 & n1254 & n1255; + assign n1261 = n1109 | n1206; + assign n1262 = n1108 | n1122; + assign n1263 = ~n110 | n1118; + assign n1264 = ~n110 | n1136; + assign n1265 = ~n110 | n1127; + assign n1266 = ~n212 | n237; + assign n1267 = n1266 & n1265 & n1263 & n1264; + assign n1268 = ~n220 | n346; + assign n1269 = ~n220 | n530; + assign n1270 = ~n220 | n1136; + assign n1271 = ~n220 | n1149; + assign n1272 = n456 | n1136; + assign n1273 = n1977 & n1975 & n1976; + assign n1274 = ~n430 | n1118; + assign n1275 = n349 | n1149; + assign n1276 = ~n430 | n1149; + assign n1277 = n349 | n1118; + assign n1278 = n1981 & n1980 & n1733 & n1756 & n1978 & n1979; + assign n1279 = n1278 & n292 & n1277 & n1276 & n1274 & n1275; + assign n1280 = n1103 | n1132; + assign n1281 = n1103 | n1104; + assign n1282 = ~n818 | n1129; + assign n1283 = ~n818 | n1130; + assign n1284 = ~n818 | n1125; + assign n1285 = n225 | n1130; + assign n1286 = n225 | n780; + assign n1287 = n225 | n1121; + assign n1288 = ~n818 | n1111; + assign n1289 = ~n220 | n1111; + assign n1290 = ~n220 | n1281; + assign n1291 = ~n220 | n304; + assign n1292 = n456 | n305; + assign n1293 = ~n220 | n990; + assign n1294 = ~n220 | n525; + assign n1295 = ~n220 | n1129; + assign n1296 = n1958 & n1956 & n1957; + assign n1297 = n349 | n304; + assign n1298 = n349 | n1121; + assign n1299 = n304 | ~n430; + assign n1300 = ~n430 | n1121; + assign n1301 = ~n430 | n1130; + assign n1302 = n1963 & n1962 & n1961 & n1960 & n1959 & n1757; + assign n1303 = n238 | n1161; + assign n1304 = n755 | n238; + assign n1305 = n238 | n684; + assign n1306 = n1727 & n1966 & n730 & n1965 & n1724 & n1964; + assign n1307 = n1091 | n1106; + assign n1308 = n1088 | n1206; + assign n1309 = n1091 | n1206; + assign n1310 = ~n818 | n1208; + assign n1311 = n345 | ~n818; + assign n1312 = ~n818 | n1227; + assign n1313 = ~n818 | n1204; + assign n1314 = ~n818 | n1198; + assign n1315 = n1314 & n1313 & n1312 & n1310 & n1311; + assign n1316 = n349 | n824; + assign n1317 = n405 | n824; + assign n1318 = n405 | n1308; + assign n1319 = n405 | n1309; + assign n1320 = n225 | n824; + assign n1321 = n1018 & n1935 & n1020 & n191; + assign n1322 = n1321 & n1320 & n1319 & n1318 & n1316 & n1317; + assign n1323 = ~n220 | n226; + assign n1324 = ~n220 | n345; + assign n1325 = n456 | n1224; + assign n1326 = ~n220 | n484; + assign n1327 = ~n220 | n1307; + assign n1328 = ~n220 | n1208; + assign n1329 = n1938 & n1936 & n1937; + assign n1330 = n1327 & n317 & n1326 & n1325 & n1323 & n1324 & n1328 & n1329; + assign n1331 = n349 | n1227; + assign n1332 = n349 | n1228; + assign n1333 = n349 | n1308; + assign n1334 = ~n430 | n1227; + assign n1335 = ~n430 | n1228; + assign n1336 = n1944 & n1943 & n1942 & n1941 & n1939 & n1940; + assign n1337 = n1336 & n1335 & n1334 & n1333 & n1331 & n1332; + assign n1338 = n1090 | n1201; + assign n1339 = n1132 | n1196; + assign n1340 = n1201 | n1206; + assign n1341 = ~n818 | n1209; + assign n1342 = n225 | n1214; + assign n1343 = n225 | n970; + assign n1344 = ~n818 | n1207; + assign n1345 = n225 | n1209; + assign n1346 = n643 | ~n818; + assign n1347 = ~n220 | n726; + assign n1348 = ~n220 | n1226; + assign n1349 = ~n220 | n643; + assign n1350 = n456 | n1226; + assign n1351 = ~n220 | n1338; + assign n1352 = n1926 & n1925 & n1923 & n1924; + assign n1353 = n1090 | n1103; + assign n1354 = n1088 | n1122; + assign n1355 = n405 | n535; + assign n1356 = n225 | n1134; + assign n1357 = n349 | n727; + assign n1358 = n405 | n1354; + assign n1359 = n187 & n1021 & n1358 & n1357 & n1355 & n1356 & n192; + assign n1360 = ~n430 | n1150; + assign n1361 = ~n430 | n1229; + assign n1362 = n349 | n1150; + assign n1363 = n349 | n1229; + assign n1364 = ~n430 | n1353; + assign n1365 = n349 | n1202; + assign n1366 = n349 | n1135; + assign n1367 = n349 | n1225; + assign n1368 = n1365 & n1364 & n1363 & n1362 & n1360 & n1361 & n1366 & n1367; + assign n1369 = n469 | n1118; + assign n1370 = ~n368 | n530; + assign n1371 = n469 | n346; + assign n1372 = ~n368 | n1118; + assign n1373 = ~n368 | n1136; + assign n1374 = n1821 & n1819 & n1820; + assign n1375 = n1822 & (~n368 | (n236 & n1262)); + assign n1376 = n1817 & n1816 & n1815 & n1814 & n1812 & n1813 & n1818 & n1811; + assign n1377 = n1374 & n1373 & n1372 & n1371 & n1369 & n1370 & n1375 & n1376; + assign n1378 = ~n368 | n970; + assign n1379 = ~n368 | n652; + assign n1380 = n469 | n1232; + assign n1381 = n469 | n1045; + assign n1382 = n1841 & n1840 & n1839 & n1838 & n1836 & n1837; + assign n1383 = n1835 & n1834 & n1833 & n1832 & n1830 & n1831 & n1829; + assign n1384 = n469 | n532; + assign n1385 = n469 | n525; + assign n1386 = n432 & n1384 & n1385; + assign n1387 = n469 | n1097; + assign n1388 = n469 | n1046; + assign n1389 = n433 & n1387 & n1388; + assign n1390 = n1281 & n1130; + assign n1391 = n970 & n1121; + assign n1392 = n1202 & n738; + assign n1393 = n419 & n1156; + assign n1394 = n652 & n1339; + assign n1395 = ~n278 & n1338; + assign n1396 = n1111 & n1124 & n1110; + assign n1397 = ~n1051 & n1152; + assign n1398 = ~n220 & n1397; + assign n1399 = ~n1053 & ~n679 & n405 & ~n539; + assign n1400 = n349 & n1398; + assign n1401 = n726 & n1210; + assign n1402 = ~n368 | n2298; + assign n1403 = n225 | n235; + assign n1404 = n225 | n1153; + assign n1405 = n456 | n1262; + assign n1406 = n1850 & n1849 & n1598 & n1848 & n1675 & n1847; + assign n1407 = n349 | n1226; + assign n1408 = n349 | n643; + assign n1409 = ~n430 | n1207; + assign n1410 = n349 | n1209; + assign n1411 = ~n430 | n1338; + assign n1412 = n349 | n1045; + assign n1413 = n349 | n652; + assign n1414 = n1856 & n1855 & n1854 & n1853 & n1851 & n1852; + assign n1415 = ~n430 | n2290; + assign n1416 = n1415 & n417 & n356 & n354 & ~n109 & n350; + assign n1417 = ~n368 | n1228; + assign n1418 = ~n368 | n1208; + assign n1419 = n469 | n1228; + assign n1420 = n469 | n1308; + assign n1421 = ~n368 | n1204; + assign n1422 = ~n368 | n484; + assign n1423 = n469 | n345; + assign n1424 = n1861 & n1860 & n1859 & n1858 & ~n215 & n1857; + assign n1425 = n1422 & n1421 & n1420 & n1419 & n1417 & n1418 & n1423 & n1424; + assign n1426 = ~n818 | n1118; + assign n1427 = n225 | n236; + assign n1428 = n225 | n1118; + assign n1429 = n346 | ~n818; + assign n1430 = n781 | ~n818; + assign n1431 = n225 | n1127; + assign n1432 = n1863 & n1862 & n1741; + assign n1433 = n1869 & n1868 & n1867 & n1866 & n1864 & n1865 & n1870 & n1871; + assign n1434 = ~n220 | n1110; + assign n1435 = ~n220 | n1353; + assign n1436 = ~n220 | n1135; + assign n1437 = n456 | n1225; + assign n1438 = n456 | n1215; + assign n1439 = ~n220 | n1215; + assign n1440 = n1874 & n1872 & n1873; + assign n1441 = n1880 & n1879 & n1878 & n1877 & n1875 & n1876 & n1881 & n1882; + assign n1442 = n1439 & n1438 & n1437 & n1436 & n1434 & n1435 & n1440 & n1441; + assign n1443 = ~n368 | n1225; + assign n1444 = n469 | n1215; + assign n1445 = ~n368 | n1110; + assign n1446 = ~n368 | n1353; + assign n1447 = n469 | n535; + assign n1448 = n1896 & n1894 & n1895; + assign n1449 = n1897 & (~n368 | n1354); + assign n1450 = n1892 & n1891 & n1890 & n1889 & n1887 & n1888 & n1893 & n1886; + assign n1451 = n469 | n1121; + assign n1452 = ~n368 | n1111; + assign n1453 = n469 | n238; + assign n1454 = n469 | n990; + assign n1455 = n1911 & n1909 & n1910; + assign n1456 = n1912 & (n238 | ~n368); + assign n1457 = n1904 & n1908 & n1907 & n1906 & n1742 & n1905; + assign n1458 = n1227 & n236; + assign n1459 = n850 & ~n212 & n302; + assign n1460 = ~n368 & ~n1051; + assign n1461 = ~n430 & n1460; + assign n1462 = n419 & ~n539; + assign n1463 = n225 & ~n250; + assign n1464 = (~n368 | n1309) & (~n1053 | n1227); + assign n1465 = n1091 | n1132; + assign n1466 = n1091 | n1104; + assign n1467 = n1091 | n1122; + assign n1468 = n1089 | n1163; + assign n1469 = n469 | n756; + assign n1470 = n469 | n1467; + assign n1471 = n469 | n642; + assign n1472 = n469 | n1466; + assign n1473 = n2083 & n2082 & n2081 & n2080 & n2078 & n2079; + assign n1474 = n481 | n477; + assign n1475 = n481 | n1139; + assign n1476 = n478 | n1139; + assign n1477 = ~n539 & n1400; + assign n1478 = n225 & n1400; + assign n1479 = n1108 | n1206; + assign n1480 = n628 & n711; + assign n1481 = n1466 & n756 & n642; + assign n1482 = ~n815 & n1164; + assign n1483 = ~n763 & ~n925; + assign n1484 = n225 | n725; + assign n1485 = n1484 & n916 & ~n112 & n618; + assign n1486 = n456 | n486; + assign n1487 = ~n465 | n796; + assign n1488 = n1487 & n189 & n1486 & n483; + assign n1489 = n2296 | n419; + assign n1490 = n1755 | n419; + assign n1491 = n2296 | n850; + assign n1492 = n849 | n419; + assign n1493 = n2291 | n850; + assign n1494 = n419 | n491; + assign n1495 = n1494 & n1493 & n1492 & n1491 & n1489 & n1490; + assign n1496 = ~n539 | n1755; + assign n1497 = n1755 | n796; + assign n1498 = ~n539 | n2296; + assign n1499 = ~n118 | n796; + assign n1500 = ~n118 | ~n539; + assign n1501 = ~n539 | n2291; + assign n1502 = n796 | n491; + assign n1503 = n2074 & n2072 & n2073; + assign n1504 = n456 | n491; + assign n1505 = n456 | n725; + assign n1506 = n849 | n456; + assign n1507 = ~n118 | ~n220; + assign n1508 = ~n220 | n2291; + assign n1509 = ~n120 | n456; + assign n1510 = n2077 & ~n466 & n464 & n460 & n453 & n457; + assign n1511 = n1508 & n1507 & n830 & n1506 & n1504 & n1505 & n1509 & n1510; + assign n1512 = i_2_ | i_0_ | ~i_1_; + assign n1513 = ~n1137 | n1512; + assign n1514 = ~n555 | n1513; + assign n1515 = i_0_ & ~i_1_; + assign n1516 = n1215 & n1212; + assign n1517 = ~n368 & n1463; + assign n1518 = n1100 & n1515; + assign n1519 = ~n271 & ~n679; + assign n1520 = n557 | n559 | n958 | n181; + assign n1521 = n558 & ~n970; + assign n1522 = n558 & ~n652; + assign n1523 = n558 & ~n1045; + assign n1524 = n1788 | n973 | n965; + assign n1525 = n967 | n1521 | n1522 | n976 | n1523 | n955 | n961 | n1524; + assign n1526 = n1384 & (n1463 | (n1516 & n1097)); + assign n1527 = n2116 & n2117 & n2118 & n1442 & n536 & n344; + assign n1528 = n1527 & n1526 & n1387 & ~n541 & ~n540 & ~n538 & n224 & ~n537; + assign n1529 = n556 & ~n1074; + assign n1530 = n1092 & n1515; + assign n1531 = ~n652 & n1529; + assign n1532 = ~n1045 & n1529; + assign n1533 = n962 | n1789 | n1786 | n964 | n957 | n972; + assign n1534 = n963 | n977 | n1531 | n1533 | n1532 | n956; + assign n1535 = n169 | n165 | n161; + assign n1536 = n1535 | n182 | n567; + assign n1537 = n269 & n570; + assign n1538 = ~n220 | n988; + assign n1539 = ~n220 | n1197; + assign n1540 = ~n220 | n725; + assign n1541 = n1540 & n1539 & n1538 & n616; + assign n1542 = n456 | n1133; + assign n1543 = n456 | n1134; + assign n1544 = n456 | n727; + assign n1545 = n456 | n726; + assign n1546 = n1205 & n1116; + assign n1547 = n495 & n940; + assign n1548 = n1466 & n699; + assign n1549 = n456 | ~n1027; + assign n1550 = n456 | n615; + assign n1551 = n2142 & n2143; + assign n1552 = n644 & n1549 & n637 & n640 & n633 & n629 & n1550 & n1551; + assign n1553 = n456 | n990; + assign n1554 = n456 | n244; + assign n1555 = n456 | n1202; + assign n1556 = n456 | n1045; + assign n1557 = n1556 & n1555 & n1554 & n295 & n1553 & n320 & n625; + assign n1558 = n456 | n1150; + assign n1559 = n456 | n304; + assign n1560 = ~n118 | n456; + assign n1561 = n456 | n1229; + assign n1562 = n456 | n1230; + assign n1563 = n1561 & n321 & n296 & n1560 & n1558 & n1559 & n1562; + assign n1564 = n1111 | n456; + assign n1565 = n226 | n456; + assign n1566 = n1124 | n456; + assign n1567 = n1110 | n456; + assign n1568 = n456 | n1353; + assign n1569 = n456 | n1338; + assign n1570 = n1569 & n1568 & n1567 & n1566 & n1564 & n1565 & n623; + assign n1571 = n456 | n605; + assign n1572 = n1244 & n1179 & n1486 & n1541 & n1571 & n617; + assign n1573 = n1217 & n1143; + assign n1574 = n1216 & n245; + assign n1575 = n469 | n1212; + assign n1576 = n469 | n1211; + assign n1577 = n469 | n1125; + assign n1578 = n469 | n1207; + assign n1579 = ~n368 | n1123; + assign n1580 = ~n368 | n1097; + assign n1581 = n232 | ~n368; + assign n1582 = n231 | ~n368; + assign n1583 = ~n368 | n1046; + assign n1584 = ~n368 | n1219; + assign n1585 = n1584 & n1583 & n1582 & n1581 & n1579 & n1580 & n586; + assign n1586 = n469 | n1200; + assign n1587 = n469 | n589; + assign n1588 = n469 | n1115; + assign n1589 = n1588 & n1587 & n1586 & n614; + assign n1590 = n469 | n994; + assign n1591 = n469 | n1199; + assign n1592 = n829 & n1590 & n1591; + assign n1593 = n316 | ~n368; + assign n1594 = ~n368 | n727; + assign n1595 = ~n368 | n1134; + assign n1596 = ~n368 | n1133; + assign n1597 = ~n368 | n726; + assign n1598 = n469 | n235; + assign n1599 = ~n368 | n1280; + assign n1600 = n1964 & n2084 & n1929 & n585 & n362 & n1585; + assign n1601 = n1598 & n1597 & n1596 & n1595 & n1593 & n1594 & n1599 & n1600; + assign n1602 = n1100 & ~n1512; + assign n1603 = n1512 | n1084 | ~n1099; + assign n1604 = n1603 & n569; + assign n1605 = n1512 | n123 | ~n222; + assign n1606 = n1401 & n1153 & n1134; + assign n1607 = n645 & n795; + assign n1608 = n405 | n726; + assign n1609 = n405 | n1153; + assign n1610 = n405 | n1134; + assign n1611 = n1610 & n1609 & ~n676 & n1608; + assign n1612 = n776 & n740; + assign n1613 = n1612 & n756 & n496; + assign n1614 = n495 & n642; + assign n1615 = ~n679 | n1225; + assign n1616 = ~n679 | n1226; + assign n1617 = ~n679 | n779; + assign n1618 = ~n679 | n781; + assign n1619 = ~n679 | n1129; + assign n1620 = n643 | ~n679; + assign n1621 = n1620 & n1619 & n1618 & n1617 & n1616 & ~n683 & n1615; + assign n1622 = ~n679 | n1281; + assign n1623 = n652 | ~n679; + assign n1624 = ~n679 | n1755; + assign n1625 = ~n679 | n738; + assign n1626 = ~n679 | ~n892; + assign n1627 = ~n679 | n1229; + assign n1628 = ~n679 | n1230; + assign n1629 = ~n118 | ~n679; + assign n1630 = ~n679 | n1149; + assign n1631 = ~n679 | n1121; + assign n1632 = ~n679 | n970; + assign n1633 = n1632 & n1631 & n1630 & n1629 & n1628 & ~n680 & n1627; + assign n1634 = n615 & n988 & n1197; + assign n1635 = n1219 & n1098; + assign n1636 = ~n709 | n1094; + assign n1637 = n349 | n572; + assign n1638 = n1151 & n620; + assign n1639 = n1468 & n725 & n530 & n244 & ~n278 & n1197; + assign n1640 = n243 | n1211; + assign n1641 = n988 | n243; + assign n1642 = n1762 | n243; + assign n1643 = n1983 & n1947 & n1984 & n1946 & n337 & n1969; + assign n1644 = n405 | n1205; + assign n1645 = n405 | n572; + assign n1646 = n622 | n405; + assign n1647 = n405 | n491; + assign n1648 = n1116 | n405; + assign n1649 = n1927 & n1985 & n338; + assign n1650 = n405 | n530; + assign n1651 = n405 | n244; + assign n1652 = n405 | n346; + assign n1653 = n405 | n345; + assign n1654 = n405 | n1045; + assign n1655 = n624 | n405; + assign n1656 = n243 | n1226; + assign n1657 = n243 | n305; + assign n1658 = n243 | n1224; + assign n1659 = n243 | n781; + assign n1660 = n243 | n1127; + assign n1661 = n243 | n1208; + assign n1662 = n340 & n1659 & n1658 & n1657 & n339 & n1656 & n1660 & n1661; + assign n1663 = n405 | n515; + assign n1664 = n1115 | n405; + assign n1665 = n2297 | n405; + assign n1666 = n405 | n1307; + assign n1667 = n405 | n1215; + assign n1668 = n1970 & n1988 & n1913; + assign n1669 = n1666 & n416 & n689 & n1665 & n1663 & n1664 & n1667 & n1668; + assign n1670 = n2297 | n243; + assign n1671 = n243 | n1215; + assign n1672 = n243 | n515; + assign n1673 = n1990 & n1952 & n1987 & n1951 & n1915 & n1967; + assign n1674 = n1673 & n1672 & n1671 & n1670 & ~n687 & n136 & n137; + assign n1675 = n405 | n235; + assign n1676 = n1762 | n405; + assign n1677 = n1676 & n1675 & n1611 & n1317 & ~n677 & n678; + assign n1678 = n405 | n1046; + assign n1679 = n405 | n1219; + assign n1680 = n405 | n1123; + assign n1681 = n405 | n1097; + assign n1682 = n405 | n1212; + assign n1683 = n405 | n1211; + assign n1684 = n1683 & n1682 & n1681 & n1680 & n1678 & n1679 & n406; + assign n1685 = n758 & n496 & n776; + assign n1686 = ~n216 | n1121; + assign n1687 = ~n216 | n970; + assign n1688 = ~n216 | n1199; + assign n1689 = ~n216 | n236; + assign n1690 = ~n216 | n1151; + assign n1691 = ~n216 | n994; + assign n1692 = n1691 & n1690 & n1689 & n1688 & n1687 & n1686 & ~n760 & n762; + assign n1693 = n1231 | n755; + assign n1694 = n755 | n236; + assign n1695 = n1151 | n755; + assign n1696 = n1695 & n1694 & n1693 & n759; + assign n1697 = n755 | n1232; + assign n1698 = n1692 & (n942 | n755); + assign n1699 = n1242 & n1176 & n1177 & n1763 & n1243 & n1304 & n2036 & n2008; + assign n1700 = ~i_2_ & i_0_ & i_1_; + assign n1701 = n524 & n773; + assign n1702 = n1137 & n1515; + assign n1703 = ~n123 & n1702; + assign n1704 = n968 | n1703 | n960 | n975; + assign n1705 = ~n110 | n237; + assign n1706 = ~n110 | n1204; + assign n1707 = ~n110 | n491; + assign n1708 = ~n110 | n2293; + assign n1709 = n1607 | n419; + assign n1710 = n225 | n1129; + assign n1711 = n225 | n643; + assign n1712 = n1635 | n225; + assign n1713 = n225 | n1208; + assign n1714 = n1713 & n1712 & n1711 & n1710 & n793 & n398 & ~n219 & n270; + assign n1715 = n231 | ~n818; + assign n1716 = ~n818 | n1123; + assign n1717 = ~n818 | n1635; + assign n1718 = n294 & (n397 | ~n818); + assign n1719 = n1718 & n1717 & n1715 & n1716; + assign n1720 = n1762 | n419; + assign n1721 = n728 | n850; + assign n1722 = n1401 | n850; + assign n1723 = n1722 & n1721 & n1720 & n823 & ~n821 & ~n822; + assign n1724 = n225 | n1280; + assign n1725 = n1634 | n225; + assign n1726 = n235 | ~n818; + assign n1727 = n225 | n1133; + assign n1728 = n1404 & n1403 & n1320; + assign n1729 = n2009 & n1719 & n1178 & ~n820 & ~n817 & ~n816 & n357 & n814; + assign n1730 = n2295 | n419; + assign n1731 = n2166 | n419; + assign n1732 = n2294 | n419; + assign n1733 = n349 | n232; + assign n1734 = n2076 & n1506 & n1808; + assign n1735 = n2156 & n1684 & n1550 & n1389 & n1239 & n1174 & ~n214 & n470; + assign n1736 = n1505 & n1733 & n1732 & n1492 & n1730 & n1731 & n1734 & n1735; + assign n1737 = n1762 | n796; + assign n1738 = n1737 & n1487 & ~n113 & ~n808; + assign n1739 = n225 | n572; + assign n1740 = n796 | n572; + assign n1741 = n225 | n237; + assign n1742 = n469 | n1130; + assign n1743 = n1494 & n1830 & n2029 & n1999; + assign n1744 = n721 & n599 & n783 & n128 & n999 & n838 & n1570 & n2177; + assign n1745 = n1246 & n2024 & n1502 & n1794 & n2026 & n1248 & n2176 & n2175; + assign n1746 = n1743 & n1742 & n1345 & n1285 & n1740 & n1741 & n1744 & n1745; + assign n1747 = n241 | n477; + assign n1748 = ~n818 | n1214; + assign n1749 = n780 | ~n818; + assign n1750 = n225 | n244; + assign n1751 = n225 | n990; + assign n1752 = n225 | n1281; + assign n1753 = n225 | n652; + assign n1754 = n225 | n345; + assign n1755 = n699 & n374; + assign n1756 = n349 | n530; + assign n1757 = n349 | n1281; + assign n1758 = n1979 & n1940 & n1824 & n1423 & ~n108 & n1371; + assign n1759 = n1497 & n1908 & n1252 & n1182 & n1251 & n2200 & n2023 & n2199; + assign n1760 = n2203 & n891 & n997 & n129 & n531 & n1557 & n2204 & n2202; + assign n1761 = n1760 & n1759 & n1758 & n1757 & n1756 & n1412 & ~n109 & n1365; + assign n1762 = n628 & n723; + assign n1763 = n755 | n776; + assign n1764 = n1762 | n456; + assign n1765 = n2225 & n757 & n2144 & n1009 & n2226 & n2159; + assign n1766 = n1676 & n1720 & n672 & n1764 & n1763 & n1737 & n601 & n1765; + assign n1767 = n225 | n1227; + assign n1768 = n1231 | n225; + assign n1769 = ~n220 & n1157; + assign n1770 = ~n925 | n970; + assign n1771 = ~n925 | n1151; + assign n1772 = ~n925 | n1121; + assign n1773 = (n1612 | n419) & (n456 | n496); + assign n1774 = ~n923 & (n469 | (n572 & n1685)); + assign n1775 = n1836 & n1469 & n1451 & n1343 & n1287 & ~n119 & n1236; + assign n1776 = n575 & n1563 & n1223 & n814 & n1592 & n1696; + assign n1777 = n906 & n1746 & n1736 & n998 & n1766 & n922; + assign n1778 = n2229 & n2228 & n1997 & n1725 & n1499 & n1427 & ~n113 & n1184; + assign n1779 = n1778 & n1777 & n1776 & n1775 & n1774 & n1773 & ~n924 & n1148; + assign n1780 = n747 & n610 & n740; + assign n1781 = n543 & n1262 & n1354; + assign n1782 = ~n1512 & n143 & ~n1084; + assign n1783 = ~n652 & n1782; + assign n1784 = ~n1045 & n1782; + assign n1785 = ~n970 & n1782; + assign n1786 = ~n970 & n1529; + assign n1787 = ~n558 & n670; + assign n1788 = ~n123 & n1518; + assign n1789 = ~n123 & n1530; + assign n1790 = ~n173 & ~n1119; + assign n1791 = ~n539 | n2292; + assign n1792 = n2292 | n796; + assign n1793 = ~n539 | n1762; + assign n1794 = n622 | n796; + assign n1795 = ~n539 | n615; + assign n1796 = n2297 | n796; + assign n1797 = n2193 & n2200 & n2213 & n1004 & n2231 & n2236; + assign n1798 = n1740 & n1795 & n1794 & n1793 & n1791 & n1792 & n1796 & n1797; + assign n1799 = n2297 | n850; + assign n1800 = n419 | n572; + assign n1801 = n622 | n850; + assign n1802 = n850 | n615; + assign n1803 = n1762 | n850; + assign n1804 = n2292 | n419; + assign n1805 = n412 & n397 & n401; + assign n1806 = n1340 & n1309 & n535; + assign n1807 = ~n381 & ~n679; + assign n1808 = n469 | n232; + assign n1809 = n469 | n236; + assign n1810 = n469 | n1149; + assign n1811 = n1810 & n1808 & n1809; + assign n1812 = n469 | n237; + assign n1813 = ~n368 | n1127; + assign n1814 = n469 | n1127; + assign n1815 = n469 | n781; + assign n1816 = n237 | ~n368; + assign n1817 = n469 | n1261; + assign n1818 = ~n368 | n1149; + assign n1819 = ~n368 | n781; + assign n1820 = ~n368 | n1124; + assign n1821 = n469 | n1262; + assign n1822 = n469 | n530; + assign n1823 = ~n368 | n1045; + assign n1824 = n469 | n652; + assign n1825 = ~n368 | n515; + assign n1826 = n469 | n1230; + assign n1827 = ~n368 | n1230; + assign n1828 = n469 | n1226; + assign n1829 = n1828 & n1827 & n1826 & n1825 & n1823 & n1824; + assign n1830 = n469 | n1209; + assign n1831 = ~n368 | n1226; + assign n1832 = ~n368 | n643; + assign n1833 = ~n368 | n1214; + assign n1834 = ~n368 | n1211; + assign n1835 = ~n368 | n1207; + assign n1836 = n469 | n970; + assign n1837 = ~n368 | n1338; + assign n1838 = n469 | n1340; + assign n1839 = ~n368 | n1209; + assign n1840 = n469 | n515; + assign n1841 = n469 | n1214; + assign n1842 = n1232 | n684; + assign n1843 = n1842 & (n302 | n1232); + assign n1844 = n456 | n1340; + assign n1845 = n1232 | n1161; + assign n1846 = n225 | n726; + assign n1847 = n405 | n1261; + assign n1848 = n405 | n1262; + assign n1849 = n349 | n235; + assign n1850 = n349 | n1153; + assign n1851 = ~n430 | n1230; + assign n1852 = ~n430 | n970; + assign n1853 = ~n430 | n1209; + assign n1854 = ~n430 | n1214; + assign n1855 = n349 | n1230; + assign n1856 = n349 | n970; + assign n1857 = n469 | n1309; + assign n1858 = ~n368 | n1224; + assign n1859 = ~n368 | n1198; + assign n1860 = n226 | ~n368; + assign n1861 = n469 | n484; + assign n1862 = n225 | n232; + assign n1863 = ~n818 | n1127; + assign n1864 = n225 | n346; + assign n1865 = n225 | n530; + assign n1866 = n225 | n1261; + assign n1867 = n225 | n1262; + assign n1868 = ~n818 | n1124; + assign n1869 = ~n818 | n1136; + assign n1870 = n236 | ~n818; + assign n1871 = n237 | ~n818; + assign n1872 = ~n220 | n727; + assign n1873 = ~n220 | n1212; + assign n1874 = ~n220 | n1225; + assign n1875 = n456 | n1135; + assign n1876 = ~n220 | n244; + assign n1877 = ~n220 | n1150; + assign n1878 = n456 | n1354; + assign n1879 = ~n220 | n1202; + assign n1880 = ~n220 | n532; + assign n1881 = ~n220 | n1097; + assign n1882 = n456 | n532; + assign n1883 = n469 | n1150; + assign n1884 = n469 | n1229; + assign n1885 = ~n368 | n1150; + assign n1886 = n1885 & n1883 & n1884; + assign n1887 = n469 | n1225; + assign n1888 = n244 | ~n368; + assign n1889 = ~n368 | n1202; + assign n1890 = ~n368 | n1215; + assign n1891 = ~n368 | n1212; + assign n1892 = ~n368 | n1229; + assign n1893 = n469 | n1135; + assign n1894 = n469 | n244; + assign n1895 = n469 | n1202; + assign n1896 = n469 | n1354; + assign n1897 = ~n368 | n1135; + assign n1898 = ~n368 | n990; + assign n1899 = ~n368 | n780; + assign n1900 = ~n368 | n1125; + assign n1901 = n469 | n304; + assign n1902 = n304 | ~n368; + assign n1903 = n469 | n305; + assign n1904 = n1903 & n1902 & n1901 & n1900 & n1898 & n1899; + assign n1905 = ~n368 | n1129; + assign n1906 = ~n368 | n1130; + assign n1907 = n469 | n780; + assign n1908 = n469 | n1281; + assign n1909 = n469 | n543; + assign n1910 = ~n368 | n1121; + assign n1911 = n305 | ~n368; + assign n1912 = ~n368 | n1281; + assign n1913 = n405 | n532; + assign n1914 = n1667 & n1913 & n694; + assign n1915 = n243 | n532; + assign n1916 = n593 & n583 & n1580 & n1543 & n1615 & n597; + assign n1917 = ~n818 | n1110; + assign n1918 = n1916 & n1917 & n1558 & n1555 & n1554 & n1544; + assign n1919 = n1750 & (~n679 | (n1135 & n1150)); + assign n1920 = (~n220 | n1354) & (~n815 | n1353); + assign n1921 = n1920 & (~n430 | n727); + assign n1922 = ~n220 | n1229; + assign n1923 = ~n220 | n1045; + assign n1924 = ~n220 | n515; + assign n1925 = ~n220 | n1211; + assign n1926 = n456 | n515; + assign n1927 = n405 | n1338; + assign n1928 = n1683 & n1597 & n716 & n1927 & n1640 & n1608; + assign n1929 = ~n368 | n1339; + assign n1930 = n1929 & n1576 & n1569; + assign n1931 = n1623 & n1556 & n1578 & n1562 & n1770 & n1748; + assign n1932 = ~n220 | n1230; + assign n1933 = (~n815 | n1338) & (n302 | n1339); + assign n1934 = (n349 | n1207) & (~n220 | n1340); + assign n1935 = n225 | n1308; + assign n1936 = ~n220 | n1219; + assign n1937 = ~n220 | n1224; + assign n1938 = n456 | n1307; + assign n1939 = n349 | n1198; + assign n1940 = n349 | n345; + assign n1941 = ~n430 | n1198; + assign n1942 = n349 | n1208; + assign n1943 = n349 | n1224; + assign n1944 = ~n430 | n1204; + assign n1945 = n1582 & n578 & n1593; + assign n1946 = n243 | n1219; + assign n1947 = n243 | n231; + assign n1948 = n349 | n231; + assign n1949 = n1948 & n1947 & n1946 & n1679 & n714 & n702 & n592 & n1945; + assign n1950 = n1666 & n1653 & n690 & n1658 & n1661; + assign n1951 = n243 | n1307; + assign n1952 = n243 | n1198; + assign n1953 = n1754 & (~n763 | (n1227 & n1308)); + assign n1954 = n1315 & (~n679 | (n1224 & n1228)); + assign n1955 = ~n220 | n1228; + assign n1956 = ~n220 | n1046; + assign n1957 = ~n220 | n305; + assign n1958 = n456 | n525; + assign n1959 = n349 | n1129; + assign n1960 = ~n430 | n780; + assign n1961 = ~n430 | n1125; + assign n1962 = n349 | n1130; + assign n1963 = n349 | n305; + assign n1964 = n469 | n1280; + assign n1965 = n225 | n238; + assign n1966 = n405 | n543; + assign n1967 = n243 | n525; + assign n1968 = n1967 & n1564 & n581 & n1599; + assign n1969 = n243 | n1046; + assign n1970 = n405 | n525; + assign n1971 = n1542 & n1553 & n1622 & n1577; + assign n1972 = (n1152 | n1281) & (n306 | ~n679); + assign n1973 = (n302 | n1280) & (~n212 | n780); + assign n1974 = (~n818 | n1121) & (n349 | n1125); + assign n1975 = ~n220 | n1153; + assign n1976 = n456 | n781; + assign n1977 = ~n220 | n1124; + assign n1978 = ~n430 | n1124; + assign n1979 = n349 | n346; + assign n1980 = n349 | n781; + assign n1981 = n237 | ~n430; + assign n1982 = n731 & n574 & n1581 & n1609 & n1680 & n713; + assign n1983 = n243 | n1123; + assign n1984 = n232 | n243; + assign n1985 = n405 | n1124; + assign n1986 = n1660 & n1659 & n1985 & n1983 & n1984; + assign n1987 = n1118 | n243; + assign n1988 = n405 | n1136; + assign n1989 = n1988 & n691 & n692 & n1987 & n1650 & n1652; + assign n1990 = n243 | n1136; + assign n1991 = ~n271 & ~n421; + assign n1992 = n419 & n796; + assign n1993 = (n1991 | n1123) & (n1992 | n1153); + assign n1994 = ~n430 & ~n539; + assign n1995 = n1993 & (n1994 | n781); + assign n1996 = (n243 | n530) & (~n220 | n1262); + assign n1997 = n1231 | n796; + assign n1998 = ~n539 | n1231; + assign n1999 = n419 | n1205; + assign n2000 = n419 | n269; + assign n2001 = n268 | n850; + assign n2002 = n1395 | n850; + assign n2003 = n472 & n468 & n1539; + assign n2004 = ~n430 | n1205; + assign n2005 = n349 | n1205; + assign n2006 = n695 & n2005 & n2004 & n137 & n753 & n1693 & n1644 & n414; + assign n2007 = ~n368 | n1197; + assign n2008 = ~n216 | n1806; + assign n2009 = ~n818 | n1401; + assign n2010 = n456 & n1164; + assign n2011 = n302 & n1156; + assign n2012 = ~n679 & n1164; + assign n2013 = (n2011 | n1199) & (n2012 | n1227); + assign n2014 = ~n216 & n1162; + assign n2015 = n1168 & ~n1053 & n225 & ~n539; + assign n2016 = (n1205 | n2015) & (n226 | ~n381); + assign n2017 = (n268 | n405) & (n316 | ~n421); + assign n2018 = (n1164 | n1214) & (n1156 | n1232); + assign n2019 = ~n430 | n726; + assign n2020 = n1237 & n266 & n656 & n1245 & n1260 & n1014 & n270 & n2019; + assign n2021 = n570 | n796; + assign n2022 = ~n539 | n738; + assign n2023 = n738 | n796; + assign n2024 = n1396 | n796; + assign n2025 = ~n218 | n796; + assign n2026 = n1116 | n796; + assign n2027 = n241 | n894; + assign n2028 = n242 & n894; + assign n2029 = n1116 | n419; + assign n2030 = n419 | n570; + assign n2031 = n355 | n419; + assign n2032 = ~n218 | n850; + assign n2033 = n1396 | n850; + assign n2034 = ~n368 | n988; + assign n2035 = n1588 & n1590 & n2034; + assign n2036 = ~n216 | n1781; + assign n2037 = ~n430 | n1116; + assign n2038 = n1664 & n2037 & n136 & n1695 & n2036 & n754 & n696 & n1648; + assign n2039 = ~n818 | n1116; + assign n2040 = (n248 | n1115) & (n2014 | n1144); + assign n2041 = (n1125 | n2010) & (n239 | ~n273); + assign n2042 = (~n250 | n653) & (n1116 | n2015); + assign n2043 = (n994 | n1157) & (~n381 | n1124); + assign n2044 = (n238 | n1156) & (~n218 | n405); + assign n2045 = n1172 & (~n220 | n1118); + assign n2046 = n1180 & n1187 & n1195 & n139; + assign n2047 = n1717 & n1712 & ~n117 & n715; + assign n2048 = ~n380 & (n2010 | (n1209 & n1390)); + assign n2049 = ~n383 & (~n273 | (n648 & n1391)); + assign n2050 = ~n384 & (~n212 | (n352 & n1392)); + assign n2051 = ~n386 & (~n818 | (n226 & ~n879)); + assign n2052 = ~n1053 & n1393; + assign n2053 = (n378 | n225) & (n1573 | n2052); + assign n2054 = ~n212 | n372; + assign n2055 = (n376 | n456) & (n230 | ~n679); + assign n2056 = (~n539 | n842) & (n1635 | n1991); + assign n2057 = ~n220 & n419; + assign n2058 = (n653 | n2057) & (n1156 | n1005); + assign n2059 = ~n271 & n1398; + assign n2060 = (n1164 | n1391) & (n375 | n2059); + assign n2061 = ~n271 & ~n501; + assign n2062 = (n233 | ~n430) & (n234 | n2061); + assign n2063 = n1399 & n225 & n1398; + assign n2064 = n1400 & n456 & n1399; + assign n2065 = (n1574 | n2063) & (n1537 | n2064); + assign n2066 = ~n216 & ~n925; + assign n2067 = (n1231 | n2066) & (n1463 | n1213); + assign n2068 = n740 | n2132; + assign n2069 = (~n271 | n726) & (~n815 | n1151); + assign n2070 = (~n110 | n530) & (n1158 | n1227); + assign n2071 = n1425 & n423 & n1442 & n534 & n344 & n542 & n1416 & n1035; + assign n2072 = n2291 | n796; + assign n2073 = ~n539 | n779; + assign n2074 = n779 | n796; + assign n2075 = n481 | n894; + assign n2076 = n469 | n725; + assign n2077 = n1755 | n456; + assign n2078 = ~n368 | n1466; + assign n2079 = ~n368 | n756; + assign n2080 = ~n368 | n632; + assign n2081 = ~n368 | n628; + assign n2082 = ~n368 | n642; + assign n2083 = n469 | n636; + assign n2084 = ~n368 | n1465; + assign n2085 = n2084 & (~n764 | (~n763 & n1161)); + assign n2086 = (n1483 | n1468) & (n2066 | n756); + assign n2087 = n850 & n796; + assign n2088 = n419 & ~n271 & ~n368; + assign n2089 = n2087 | n232; + assign n2090 = (~n212 | n781) & (n1161 | n1262); + assign n2091 = n1220 & n1145; + assign n2092 = ~n763 & n1393; + assign n2093 = ~n213 & (n2092 | (n1262 & n1309)); + assign n2094 = ~n499 & (n491 | (n225 & n1477)); + assign n2095 = ~n500 & (n699 | (n405 & n1478)); + assign n2096 = ~n679 & n1159; + assign n2097 = (n1805 | n489) & (n2096 | n498); + assign n2098 = (n492 | ~n1053) & (n490 | n1468); + assign n2099 = ~n763 & n1162; + assign n2100 = ~n501 & n796; + assign n2101 = (n2100 | n1124) & (n2087 | n781); + assign n2102 = n755 & n1482; + assign n2103 = (n1769 | n945) & (n2102 | n1228); + assign n2104 = n2101 & n2103 & (n1165 | n1153); + assign n2105 = n1164 & n1483; + assign n2106 = (~n379 | n412) & (n1149 | n2105); + assign n2107 = n1165 & n796 & n488; + assign n2108 = (~n273 | n485) & (n1224 | n2107); + assign n2109 = (n463 | n1400) & (~n385 | n1398); + assign n2110 = (n243 | n401) & (n484 | ~n679); + assign n2111 = (~n368 | n589) & (n755 | n756); + assign n2112 = n494 & n2111 & (~n539 | n1136); + assign n2113 = n1495 & n1013 & n140 & n476 & n450 & n1511 & n1488 & n1485; + assign n2114 = n416 & n413 & n409 & n406 & n398 & n402 & n429 & n440; + assign n2115 = n1385 & (n456 | (n1390 & n1280)); + assign n2116 = (n1134 | n2057) & (n535 | ~n546); + assign n2117 = (~n815 | n1150) & (n1229 | n2066); + assign n2118 = ~n212 | n1215; + assign n2119 = n1221 & (n1164 | (n1390 & n1353)); + assign n2120 = n2119 & (n243 | (n653 & n990)); + assign n2121 = (n229 | n2061) & (n1482 | n727); + assign n2122 = n247 & n1519; + assign n2123 = (n2122 | n346) & (n2052 | n1143); + assign n2124 = (~n503 | n1516) & (n232 | n1462); + assign n2125 = (n1202 | n2012) & (~n818 | n1392); + assign n2126 = (~n421 | n1105) & (n1280 | n2059); + assign n2127 = n1398 & n456 & n684; + assign n2128 = n2125 & n2126 & (n2127 | n1261); + assign n2129 = (n1519 | n1127) & (n2063 | n245); + assign n2130 = (n2102 | n1229) & (n2064 | n570); + assign n2131 = n1098 | n1154; + assign n2132 = ~n925 & n755 & ~n679 & ~n368 & n456; + assign n2133 = (n994 | n2132) & (~n879 | n1152); + assign n2134 = (n2092 | n535) & (n1156 | n1781); + assign n2135 = ~n368 | n651; + assign n2136 = n2289 | n469; + assign n2137 = n651 | n469; + assign n2138 = ~n368 | n1612; + assign n2139 = n608 | n469; + assign n2140 = n469 | n776; + assign n2141 = n536 & n544 & n666 & n1589 & n606 & n612 & n476 & n448; + assign n2142 = ~n220 | n645; + assign n2143 = n456 | n572; + assign n2144 = n620 | n456; + assign n2145 = n1612 | n456; + assign n2146 = n2289 | n456; + assign n2147 = n1442 & n1330 & n327 & n1552 & n649 & n1511; + assign n2148 = n1150 & n304; + assign n2149 = n993 | n349; + assign n2150 = n349 | n613; + assign n2151 = ~n430 | n1634; + assign n2152 = (~n421 | n741) & (~n430 | n739); + assign n2153 = n266 & (~n142 | n261); + assign n2154 = n622 | n243; + assign n2155 = n1358 & n1848 & n1319 & n1966 & n1355 & n358 & n1847 & n1318; + assign n2156 = n2166 | n405; + assign n2157 = n1612 | n405; + assign n2158 = n2292 | n405; + assign n2159 = n620 | n405; + assign n2160 = ~n277 | n748; + assign n2161 = ~n381 | n1614; + assign n2162 = n1936 & n1956; + assign n2163 = n813 | ~n818; + assign n2164 = n1925 & (n615 | (~n379 & ~n818)); + assign n2165 = n2166 | n850; + assign n2166 = n1197 & n725 & n988; + assign n2167 = (~n379 | n725) & (~n818 | n2166); + assign n2168 = n2135 & n1981 & n1944 & n1978 & n1364 & n1415 & n1421 & n1816; + assign n2169 = n1283 & n1341 & n2039 & n1235 & n1434 & n1977 & n1501 & n785; + assign n2170 = n1801 & n1871 & n1313 & n1868 & n1288 & n1917 & n2002 & n2033; + assign n2171 = ~n379 & n1152; + assign n2172 = n242 & ~n709; + assign n2173 = (~n368 | n572) & (~n818 | n1395); + assign n2174 = n1504 & n1173; + assign n2175 = n1812 & n2143 & n1962 & n2137 & n1410 & n1637 & n1238 & n2174; + assign n2176 = n2072 & n2075 & n1475; + assign n2177 = n1800 & (n349 | n632); + assign n2178 = ~n220 | n825; + assign n2179 = n453 & n647 & n1572 & n1601 & n735 & n576 & n1223 & n2178; + assign n2180 = n1903 & n1887 & n2146 & n1814 & n1893 & n1815 & n1828; + assign n2181 = n1476 & n1265 & n1407 & n1959 & n263 & n1408 & n786; + assign n2182 = n1350 & n1804 & n1862 & n1431 & n1437 & n1976 & n2030; + assign n2183 = (n1537 | n405) & (n469 | n463); + assign n2184 = n464 & (n478 | n894); + assign n2185 = n1874 & n1957 & n1937 & n2073 & n1418 & n1813; + assign n2186 = n1348 & n1328 & n1436 & n1819 & n1349 & n1295; + assign n2187 = n2082 & n1443 & n1831 & n2032 & n1832 & n1905 & n2186; + assign n2188 = ~n867 & (n478 | (n242 & n477)); + assign n2189 = (n1994 | n781) & (n1400 | n792); + assign n2190 = n2189 & (n1537 | n1477); + assign n2191 = (n352 | n850) & (n353 | ~n1051); + assign n2192 = n1438 & n1958 & n1938 & n1277 & n1939 & n1369; + assign n2193 = n796 | n613; + assign n2194 = n1140 & n2150 & n2027 & n2193 & n1796 & n1169 & n2192; + assign n2195 = n2149 & n1428 & n1342 & n1286 & ~n116 & n1272; + assign n2196 = n993 | n419; + assign n2197 = (n405 | n589) & (n349 | n412); + assign n2198 = n1589 & n637 & n413; + assign n2199 = n1170 & n1413 & n1142; + assign n2200 = n624 | n796; + assign n2201 = n1256 & n1490 & n1193; + assign n2202 = n1864 & n1861 & n1454 & n1894 & n2077 & n1822 & n1865 & n2201; + assign n2203 = n1472 & n1895 & n1381; + assign n2204 = (n895 | n265) & (n469 | n699); + assign n2205 = n1859 & n1373 & n1294 & n1327 & n1372 & n1439 & n1890; + assign n2206 = ~n818 | n993; + assign n2207 = n1880 & n2206 & n1270 & n1079 & n1402 & n1924; + assign n2208 = n2054 & n1491 & n1255 & n1192; + assign n2209 = ~n213 & (n613 | (n850 & n1152)); + assign n2210 = n2209 & (~n539 | (n589 & n688)); + assign n2211 = n636 & n897; + assign n2212 = n1889 & n1823 & n1370 & n1888 & n1422 & n1898 & n1141; + assign n2213 = ~n539 | n624; + assign n2214 = n1923 & n1290 & n1268 & n1324 & n1879 & n1269 & n2078; + assign n2215 = n1234 & (n1574 | (~n539 & n850)); + assign n2216 = ~n907 & (~n368 | (n874 & n1755)); + assign n2217 = (n1400 | n1548) & (n1397 | n1281); + assign n2218 = (~n277 | n746) & (~n212 | n528); + assign n2219 = (n1152 | n738) & (n1164 | n747); + assign n2220 = (n374 | ~n1051) & (n652 | n1398); + assign n2221 = n265 | n242; + assign n2222 = n2211 | n349; + assign n2223 = n1136 & n236 & n397 & n1215 & n532 & n1307; + assign n2224 = n1762 & ~n918 & n845 & n780 & n636 & n667; + assign n2225 = (n1992 | n615) & (n225 | n613); + assign n2226 = n620 | n419; + assign n2227 = n2157 & n1948 & n1826 & n1362 & n1331 & n1275; + assign n2228 = n1419 & n1901 & n1809 & n2145 & n1810 & n1883 & n1884 & n2227; + assign n2229 = n1363 & n1332 & n1297 & n1856 & n1855 & n1298; + assign n2230 = n1902 & n1417 & n1892 & n1827 & n731 & n2138 & n1885 & n1818; + assign n2231 = ~n539 | n620; + assign n2232 = n1185 & n1998 & n1300 & n1852 & n1500 & n828 & n2231; + assign n2233 = (~n709 | n1112) & (~n220 | n776); + assign n2234 = n2233 & n453 & n1541 & n1633 & n1585 & n621; + assign n2235 = n1509 & n1867 & n1866 & n1821 & n1878 & n1549; + assign n2236 = n796 | ~n1027; + assign n2237 = n1571 & n1333 & n1817 & n830 & n1420 & n2139 & n2236 & n2235; + assign n2238 = n1470 & n1838 & n1447 & n1190 & n1453 & n1380; + assign n2239 = (n946 | n469) & (n685 | n684); + assign n2240 = n1781 & ~n764 & n944; + assign n2241 = (n2240 | n1161) & (n488 | n941); + assign n2242 = n1180 & n1245 & (n992 | n796); + assign n2243 = ~n979 | n982; + assign n2244 = (~n172 | ~n1119) & (n1513 | n1790); + assign n2245 = n516 & n969; + assign n2246 = (n1083 | n122) & (n2245 | n990); + assign n2247 = (n122 | ~n1119) & (n304 | n2245); + assign n2248 = (n1230 | n2245) & (n122 | ~n173); + assign n2249 = n1083 & n1790; + assign n2250 = ~n159 & (~n222 | n1512 | n2249); + assign n2251 = n1935 & n1917 & n2206; + assign n2252 = n361 & n1965 & (n996 | n225); + assign n2253 = (n610 | ~n815) & (~n818 | n991); + assign n2254 = ~n1028 & (~n501 | (~n385 & n1780)); + assign n2255 = n2254 & (n1026 | n850); + assign n2256 = (n2066 | n1230) & (n247 | n652); + assign n2257 = ~n1050 & (n2092 | (n543 & n1340)); + assign n2258 = ~n1055 & (n990 | (~n381 & n1393)); + assign n2259 = (n1160 | n945) & (n2099 | n985); + assign n2260 = (~n503 | n1047) & (n1478 | n1481); + assign n2261 = (n615 | n1043) & (~n281 | n1465); + assign n2262 = (~n815 | n1480) & (n645 | n1155); + assign n2263 = (n1338 | n2100) & (~n1027 | n1477); + assign n2264 = (n726 | n1165) & (n524 | ~n679); + assign n2265 = (n1769 | n605) & (n2102 | n1230); + assign n2266 = (n2105 | n304) & (n2066 | n776); + assign n2267 = (n247 | n1466) & (n622 | n419); + assign n2268 = (~n381 | n401) & (~n421 | n628); + assign n2269 = (n488 | n1467) & (n1164 | n1111); + assign n2270 = (n1398 | n652) & (n1156 | n1133); + assign n2271 = (n456 | n632) & (~n110 | n463); + assign n2272 = n796 | n1045; + assign n2273 = n2270 & n2271 & n2272 & n450 & n554 & n526; + assign n2274 = n1146 & (n1156 | (n1806 & n1134)); + assign n2275 = n2274 & (n484 | (n225 & ~n421)); + assign n2276 = ~n1065 & (n244 | (n1393 & n1807)); + assign n2277 = (n228 | n2061) & (~n110 | n778); + assign n2278 = n2277 & (n1394 | n2059); + assign n2279 = (n2122 | n345) & (n2052 | n1217); + assign n2280 = ~n1066 & ~n1067 & (n1110 | n2100); + assign n2281 = (n2127 | n1308) & (n1519 | n1208); + assign n2282 = (n2063 | n1216) & (n2105 | n1150); + assign n2283 = (n2064 | n269) & (n247 | n231); + assign n2284 = (n2132 | n1199) & (n1210 | n243); + assign n2285 = (~n503 | n1097) & (n1354 | n2092); + assign n2286 = (n1135 | n2107) & (~n381 | n1202); + assign n2287 = (~n430 | n1045) & (n405 | n652); + assign n2288 = i_2_ | ~i_0_ | i_1_; + assign n2289 = n610 & n1537; + assign n2290 = n226 & n1110 & n1111; + assign n2291 = n401 & n237 & n1204; + assign n2292 = n642 & n353; + assign n2293 = n226 & n401 & n1124; + assign n2294 = n1123 & n1098; + assign n2295 = n1219 & n1213; + assign n2296 = n1198 & n459; + assign n2297 = n636 & n348; + assign n2298 = ~n879 & n1307; +endmodule + + diff --git a/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v b/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v new file mode 100644 index 000000000..6c2cf208b --- /dev/null +++ b/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v @@ -0,0 +1,1648 @@ +// Benchmark "top" written by ABC on Tue Mar 5 10:05:48 2019 + +module tseng ( clock, + tin_pv10_4_4_, tin_pv11_4_4_, tin_pv6_7_7_, tin_pv2_0_0_, + tin_pv10_3_3_, tin_pv1_2_2_, tin_pv11_3_3_, tin_pv4_3_3_, + tin_pv10_2_2_, tin_pv11_2_2_, tin_pv6_0_0_, tin_pv2_1_1_, + tin_pv10_1_1_, tin_pv1_3_3_, preset_0_0_, tin_pv11_1_1_, tin_pv4_4_4_, + tin_pready_0_0_, tin_pv10_0_0_, tin_pv11_0_0_, tin_pv6_1_1_, + tin_pv2_2_2_, tin_pv1_4_4_, tin_pv4_5_5_, tin_pv6_2_2_, tin_pv2_3_3_, + tin_pv1_5_5_, tin_pv4_6_6_, tin_pv6_3_3_, tin_pv2_4_4_, tin_pv1_6_6_, + tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_, + tin_pv4_0_0_, tin_pv6_5_5_, tin_pv2_6_6_, tin_pv10_7_7_, tin_pv1_0_0_, + tin_pv11_7_7_, tin_pv4_1_1_, tin_pv10_6_6_, tin_pv11_6_6_, + tin_pv6_6_6_, tin_pv2_7_7_, preset, tin_pv10_5_5_, tin_pv1_1_1_, + tin_pv11_5_5_, tin_pv4_2_2_, + pv14_2_2_, pv12_3_3_, pv10_4_4_, pv7_5_5_, pv3_6_6_, pv15_2_2_, + pv13_3_3_, pv11_4_4_, pv6_7_7_, pv2_0_0_, pv14_1_1_, pv12_2_2_, + pv10_3_3_, pv9_0_0_, pv5_1_1_, pv1_2_2_, pv15_1_1_, pv13_2_2_, + pv11_3_3_, pv8_2_2_, pv4_3_3_, pv14_0_0_, pv12_1_1_, pv10_2_2_, + pv7_6_6_, pv3_7_7_, pv15_0_0_, pv13_1_1_, pv11_2_2_, pv6_0_0_, + pv2_1_1_, pv12_0_0_, pv10_1_1_, pv9_1_1_, pv5_2_2_, pv1_3_3_, + pv13_0_0_, pv11_1_1_, pv8_3_3_, pv4_4_4_, pready_0_0_, pv10_0_0_, + pv7_7_7_, pv3_0_0_, pv11_0_0_, pv6_1_1_, pv2_2_2_, pv9_2_2_, pv5_3_3_, + pv1_4_4_, pv8_4_4_, pv4_5_5_, pv7_0_0_, pv3_1_1_, pv6_2_2_, pv2_3_3_, + pv9_3_3_, pv5_4_4_, pv1_5_5_, pv8_5_5_, pv4_6_6_, pv7_1_1_, pv3_2_2_, + pv6_3_3_, pv2_4_4_, pv9_4_4_, pv5_5_5_, pv1_6_6_, pv8_6_6_, pv4_7_7_, + pv7_2_2_, pv3_3_3_, pv6_4_4_, pv2_5_5_, pv14_7_7_, pv9_5_5_, pv5_6_6_, + pv1_7_7_, pv15_7_7_, pv8_7_7_, pv4_0_0_, pv14_6_6_, pv12_7_7_, + pv7_3_3_, pv3_4_4_, pv15_6_6_, pv13_7_7_, pv6_5_5_, pv2_6_6_, pdn, + pv14_5_5_, pv12_6_6_, pv10_7_7_, pv9_6_6_, pv5_7_7_, pv1_0_0_, + pv15_5_5_, pv13_6_6_, pv11_7_7_, pv8_0_0_, pv4_1_1_, pv14_4_4_, + pv12_5_5_, pv10_6_6_, pv7_4_4_, pv3_5_5_, pv15_4_4_, pv13_5_5_, + pv11_6_6_, pv6_6_6_, pv2_7_7_, pv14_3_3_, pv12_4_4_, pv10_5_5_, + pv9_7_7_, pv5_0_0_, pv1_1_1_, pv15_3_3_, pv13_4_4_, pv11_5_5_, + pv8_1_1_, pv4_2_2_ ); + input tin_pv10_4_4_, tin_pv11_4_4_, tin_pv6_7_7_, tin_pv2_0_0_, + tin_pv10_3_3_, tin_pv1_2_2_, tin_pv11_3_3_, tin_pv4_3_3_, + tin_pv10_2_2_, tin_pv11_2_2_, tin_pv6_0_0_, tin_pv2_1_1_, + tin_pv10_1_1_, tin_pv1_3_3_, preset_0_0_, tin_pv11_1_1_, tin_pv4_4_4_, + tin_pready_0_0_, tin_pv10_0_0_, tin_pv11_0_0_, tin_pv6_1_1_, + tin_pv2_2_2_, tin_pv1_4_4_, tin_pv4_5_5_, tin_pv6_2_2_, tin_pv2_3_3_, + tin_pv1_5_5_, tin_pv4_6_6_, tin_pv6_3_3_, tin_pv2_4_4_, tin_pv1_6_6_, + clock, tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_, + tin_pv4_0_0_, tin_pv6_5_5_, tin_pv2_6_6_, tin_pv10_7_7_, tin_pv1_0_0_, + tin_pv11_7_7_, tin_pv4_1_1_, tin_pv10_6_6_, tin_pv11_6_6_, + tin_pv6_6_6_, tin_pv2_7_7_, preset, tin_pv10_5_5_, tin_pv1_1_1_, + tin_pv11_5_5_, tin_pv4_2_2_; + output pv14_2_2_, pv12_3_3_, pv10_4_4_, pv7_5_5_, pv3_6_6_, pv15_2_2_, + pv13_3_3_, pv11_4_4_, pv6_7_7_, pv2_0_0_, pv14_1_1_, pv12_2_2_, + pv10_3_3_, pv9_0_0_, pv5_1_1_, pv1_2_2_, pv15_1_1_, pv13_2_2_, + pv11_3_3_, pv8_2_2_, pv4_3_3_, pv14_0_0_, pv12_1_1_, pv10_2_2_, + pv7_6_6_, pv3_7_7_, pv15_0_0_, pv13_1_1_, pv11_2_2_, pv6_0_0_, + pv2_1_1_, pv12_0_0_, pv10_1_1_, pv9_1_1_, pv5_2_2_, pv1_3_3_, + pv13_0_0_, pv11_1_1_, pv8_3_3_, pv4_4_4_, pready_0_0_, pv10_0_0_, + pv7_7_7_, pv3_0_0_, pv11_0_0_, pv6_1_1_, pv2_2_2_, pv9_2_2_, pv5_3_3_, + pv1_4_4_, pv8_4_4_, pv4_5_5_, pv7_0_0_, pv3_1_1_, pv6_2_2_, pv2_3_3_, + pv9_3_3_, pv5_4_4_, pv1_5_5_, pv8_5_5_, pv4_6_6_, pv7_1_1_, pv3_2_2_, + pv6_3_3_, pv2_4_4_, pv9_4_4_, pv5_5_5_, pv1_6_6_, pv8_6_6_, pv4_7_7_, + pv7_2_2_, pv3_3_3_, pv6_4_4_, pv2_5_5_, pv14_7_7_, pv9_5_5_, pv5_6_6_, + pv1_7_7_, pv15_7_7_, pv8_7_7_, pv4_0_0_, pv14_6_6_, pv12_7_7_, + pv7_3_3_, pv3_4_4_, pv15_6_6_, pv13_7_7_, pv6_5_5_, pv2_6_6_, pdn, + pv14_5_5_, pv12_6_6_, pv10_7_7_, pv9_6_6_, pv5_7_7_, pv1_0_0_, + pv15_5_5_, pv13_6_6_, pv11_7_7_, pv8_0_0_, pv4_1_1_, pv14_4_4_, + pv12_5_5_, pv10_6_6_, pv7_4_4_, pv3_5_5_, pv15_4_4_, pv13_5_5_, + pv11_6_6_, pv6_6_6_, pv2_7_7_, pv14_3_3_, pv12_4_4_, pv10_5_5_, + pv9_7_7_, pv5_0_0_, pv1_1_1_, pv15_3_3_, pv13_4_4_, pv11_5_5_, + pv8_1_1_, pv4_2_2_; + reg n_n4142, n_n3936, n_n3574, n_n3008, n_n3726, n_n3604, n_n3144, + n_n3782, n_n3067, n_n4258, n_n3225, n_n3180, n_n3274, n_n3475, n_n3687, + n_n3381, n_n3098, n_n4108, n_n3497, n_n3793, n_n4316, n_n4349, n_n3029, + n_n3619, n_n3264, n_n3780, ndn3_4, n_n4114, n_n3146, n_n3511, n_n3152, + n_n3833, n_n4282, n_n3305, n_n4392, n_n4224, n_n3198, n_n3204, n_n3024, + n_n4139, ndn3_15, n_n3133, n_n4074, n_n3270, n_n3858, n_n3456, n_n3521, + n_n3081, n_n4381, n_n3670, n_n4211, n_n3493, n_n3495, n_n3916, n_n3195, + n_n3525, n_n3729, n_n3876, ndn3_5, n_n3549, n_n3489, n_n3764, n_n3281, + n_n3707, n_n3517, n_n4160, n_n4222, n_n3012, n_n4071, n_n3372, n_n3344, + n_n3688, n_n3079, n_n3313, n_n3411, n_n3231, n_n3396, n_n3432, n_n3606, + n_n3733, n_n3556, n_n4040, n_n3120, n_n3221, n_n3173, n_n3851, n_n3113, + n_n3242, n_n3118, n_n3376, n_n4089, n_n3044, n_n3627, n_n3035, n_n3111, + n_n3321, n_n3443, n_n3215, ndn3_10, n_n4172, nlc1_2, n_n3590, n_n4110, + nlc3_3, n_n3576, n_n4129, n_n4189, n_n4286, n_n4383, pdn, n_n3567, + n_n3892, n_n3075, n_n3354, n_n3465, ndn3_6, n_n3617, n_n4162, n_n3207, + n_n4120, n_n3065, n_n4005, n_n3266, n_n4337, n_n3600, n_n3415, n_n4243, + n_n3872, n_n3648, n_n3358, n_n3350, ndn3_7, n_n3116, n_n3583, n_n3906, + n_n4131, n_n3316, n_n3061, n_n3048, n_n3886, n_n3919, n_n3128, n_n3995, + n_n4213, n_n3761, ndn3_8, n_n3252, n_n4366, n_n3328, n_n3988, n_n3348, + n_n3544, n_n3101, n_n4279, n_n3896, n_n3736, n_n4251, n_n3650, n_n3307, + n_n4294, n_n4334, n_n3955, n_n4164, n_n3155, n_n3749, n_n4233, n_n4347, + n_n3826, n_n3360, n_n3458, n_n3093, n_n3157, n_n3506, n_n3161, n_n3319, + n_n3429, n_n3971, n_n3449, n_n4270, n_n4288, n_n3183, n_n3130, nlak4_2, + n_n4047, n_n3978, n_n3239, n_n4145, n_n3890, n_n4003, n_n3091, n_n3985, + n_n3326, n_n4052, nsr4_2, n_n4099, n_n4375, n_n4067, n_n4290, n_n3898, + n_n4122, n_n3774, n_n3014, n_n4241, n_n3952, n_n3237, n_n3968, n_n3922, + n_n3551, n_n3379, n_n4275, n_n3570, n_n3854, n_n4057, n_n3451, n_n4037, + n_n3408, n_n4229, n_n4201, n_n3339, n_n4362, n_n3483, n_n3557, n_n4185, + n_n3069, n_n3643, n_n3404, n_n3057, n_n3020, n_n3828, n_n3631, n_n3138, + nsr1_2, n_n4065, n_n3679, n_n3287, n_n4351, n_n4059, n_n3436, nen3_10, + n_n3461, n_n4012, n_n3051, n_n3073, n_n3777, n_n3709, n_n3946, n_n3085, + n_n3259, n_n3504, n_n4045, n_n3954, n_n3136, n_n4372, n_n4236, n_n3040, + n_n3874, n_n3999, n_n3223, ndn1_34, n_n3743, n_n3657, n_n3213, n_n3095, + n_n3663, n_n3724, n_n3038, n_n3370, n_n3624, n_n3578, n_n3713, n_n3089, + n_n3211, n_n3367, n_n3434, n_n3126, n_n4192, n_n4136, n_n3053, n_n3938, + n_n3769, n_n4390, nsr3_17, n_n3903, n_n3658, nrq3_11, n_n3818, n_n3533, + n_n3463, n_n3175, n_n3055, n_n3202, n_n3385, n_n4077, n_n3142, n_n3901, + n_n3934, n_n3823, n_n3722, n_n4309, n_n4159, n_n4330, n_n3836, n_n3470, + n_n3331, n_n3883, n_n4299, n_n4157, ndn3_9, n_n3208, n_n3190, n_n4029, + n_n3042, nsr3_14, n_n4151, n_n3188, n_n4303, n_n3250, n_n3170, n_n3758, + n_n3910, n_n3108, n_n3150, n_n4320, n_n4360, n_n4247, n_n4199, n_n3966, + n_n3766, n_n4021, n_n4062, n_n3514, n_n3572, n_n4166, n_n3976, n_n3394, + n_n4095, n_n3863, n_n3720, ngfdn_3, n_n3756, n_n3667, n_n3342, n_n3529, + n_n4209, n_n4324, n_n3337, n_n4227, n_n4153, n_n3831, n_n3233, n_n4263, + n_n3413, n_n4182, n_n3841, n_n3441, n_n4026, n_n4342, n_n4102, n_n3277, + n_n4180, n_n3878, n_n3931, n_n3845, n_n3865, n_n3486, n_n4056, n_n3674, + n_n3959, n_n3608, n_n4080, n_n4018, n_n4354, n_n3797, n_n3739, n_n3646, + n_n3099, n_n3537, n_n3806, n_n3087, n_n4105, n_n3262, n_n4125, n_n3814, + n_n4093, nsr3_3; + wire n1835, n1836, n1837, n1838_1, n1839, n1840, n1841, n1842, n1843_1, + n1844, n1845, n1846, n1847, n1848_1, n1849, n1850, n1851, n1852, + n1853_1, n1854, n1855, n1856, n1857, n1858_1, n1859, n1860, n1861, + n1862, n1863_1, n1864, n1865, n1866, n1867, n1868_1, n1869, n1870, + n1871, n1872, n1873_1, n1874, n1875, n1876, n1877, n1878_1, n1879, + n1880, n1881, n1882, n1883_1, n1884, n1885, n1886, n1887, n1888_1, + n1889, n1890, n1891, n1892, n1893_1, n1894, n1895, n1896, n1897, + n1898_1, n1899, n1900, n1901, n1902, n1903_1, n1904, n1905, n1906, + n1907, n1908_1, n1909, n1910, n1911, n1912, n1913_1, n1914, n1915, + n1916, n1917, n1918_1, n1919, n1920, n1921, n1922, n1923_1, n1924, + n1925, n1926, n1927, n1928_1, n1929, n1930, n1931, n1932, n1933_1, + n1934, n1935, n1936, n1937, n1938_1, n1939, n1940, n1941, n1942, + n1943_1, n1944, n1945, n1946, n1947, n1948_1, n1949, n1950, n1951, + n1952, n1953_1, n1954, n1955, n1956, n1957, n1958_1, n1959, n1960, + n1961, n1962, n1963_1, n1964, n1965, n1966, n1967, n1968_1, n1969, + n1970, n1971, n1972, n1973_1, n1974, n1975, n1976, n1977, n1978_1, + n1979, n1980, n1981, n1982, n1983_1, n1984, n1985, n1986, n1987, + n1988_1, n1989, n1990, n1991, n1992, n1993_1, n1994, n1995, n1996, + n1997, n1998_1, n1999, n2000, n2001, n2002, n2003_1, n2004, n2005, + n2006, n2007, n2008_1, n2009, n2010, n2011, n2012, n2013_1, n2014, + n2015, n2016, n2017, n2018_1, n2019, n2020, n2021, n2022, n2023_1, + n2024, n2025, n2026, n2027, n2028_1, n2029, n2030, n2031, n2032, + n2033_1, n2034, n2035, n2036, n2037, n2038_1, n2039, n2040, n2041, + n2042, n2043_1, n2044, n2045, n2046, n2047, n2048_1, n2049, n2050, + n2051, n2052, n2053_1, n2054, n2055, n2056, n2057, n2058_1, n2059, + n2060, n2061, n2062, n2063_1, n2064, n2065, n2066, n2067, n2068_1, + n2069, n2070, n2071, n2072, n2073_1, n2074, n2075, n2076, n2077, + n2078_1, n2079, n2080, n2081, n2082, n2083_1, n2084, n2085, n2086, + n2087, n2088_1, n2089, n2090, n2091, n2092, n2093_1, n2094, n2095, + n2096, n2097, n2098_1, n2099, n2100, n2101, n2102, n2103_1, n2104, + n2105, n2106, n2107, n2108_1, n2109, n2110, n2111, n2112, n2113_1, + n2114, n2115, n2116, n2117, n2118_1, n2119, n2120, n2121, n2122, + n2123_1, n2124, n2125, n2126, n2127, n2128_1, n2129, n2130, n2131, + n2132, n2133_1, n2134, n2135, n2136, n2137, n2138_1, n2139, n2140, + n2141, n2142, n2143_1, n2144, n2145, n2146, n2147, n2148_1, n2149, + n2150, n2151, n2152, n2153_1, n2154, n2155, n2156, n2157, n2158_1, + n2159, n2160, n2161, n2162, n2163_1, n2164, n2165, n2166, n2167, + n2168_1, n2169, n2170, n2171, n2172, n2173_1, n2174, n2175, n2176, + n2177, n2178_1, n2179, n2180, n2181, n2182, n2183_1, n2184, n2185, + n2186, n2187, n2188_1, n2189, n2190, n2191, n2192, n2193_1, n2194, + n2195, n2196, n2197, n2198_1, n2199, n2200, n2201, n2202, n2203_1, + n2204, n2205, n2206, n2207, n2208_1, n2209, n2210, n2211, n2212, + n2213_1, n2214, n2215, n2216, n2217, n2218_1, n2219, n2220, n2221, + n2222, n2223_1, n2224, n2225, n2226, n2227, n2228_1, n2229, n2230, + n2231, n2232, n2233_1, n2234, n2235, n2236, n2237, n2238_1, n2239, + n2240, n2241, n2242, n2243_1, n2244, n2245, n2246, n2247, n2248_1, + n2249, n2250, n2251, n2252, n2253_1, n2254, n2255, n2256, n2257, + n2258_1, n2259, n2260, n2261, n2262, n2263_1, n2264, n2265, n2266, + n2267, n2268_1, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, + n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, + n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, + n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, + n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, + n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, + n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, + n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, + n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, + n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, + n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n349, n354, + n359, n364, n369, n374, n379, n384, n389, n394, n399, n404, n409, n414, + n419, n424, n429, n434, n439, n444, n449, n454, n459, n464, n469, n474, + n479, n484, n489, n494, n499, n504, n509, n514, n519, n524, n529, n534, + n539, n544, n549, n554, n559, n564, n569, n574, n579, n584, n589, n594, + n599, n604, n609, n614, n619, n624, n629, n634, n639, n644, n649, n654, + n659, n664, n669, n674, n679, n684, n689, n694, n699, n704, n709, n714, + n719, n724, n729, n734, n739, n744, n749, n754, n759, n764, n769, n774, + n779, n784, n789, n794, n799, n804, n809, n814, n819, n824, n829, n834, + n839, n844, n849, n854, n859, n864, n869, n874, n879, n884, n889, n894, + n898, n903, n908, n913, n918, n923, n928, n933, n938, n943, n948, n953, + n958, n963, n968, n973, n978, n983, n988, n993, n998, n1003, n1008, + n1013, n1018, n1023, n1028, n1033, n1038, n1043, n1048, n1053, n1058, + n1063, n1068, n1073, n1078, n1083, n1088, n1093, n1098, n1103, n1108, + n1113, n1118, n1123, n1128, n1133, n1138, n1143, n1148, n1153, n1158, + n1163, n1168, n1173, n1178, n1183, n1188, n1193, n1198, n1203, n1208, + n1213, n1218, n1223, n1228, n1233, n1238, n1243, n1248, n1253, n1258, + n1263, n1268, n1273, n1278, n1283, n1288, n1293, n1298, n1303, n1308, + n1313, n1318, n1323, n1328, n1333, n1338, n1343, n1348, n1353, n1358, + n1363, n1368, n1373, n1378, n1383, n1388, n1393, n1398, n1403, n1408, + n1413, n1418, n1423, n1428, n1433, n1438, n1443, n1448, n1453, n1458, + n1463, n1468, n1473, n1478, n1483, n1488, n1493, n1498, n1503, n1508, + n1513, n1518, n1523, n1528, n1533, n1538, n1543, n1548, n1553, n1558, + n1563, n1568, n1573, n1578, n1583, n1588, n1593, n1598, n1603, n1608, + n1613, n1618, n1623, n1628, n1633, n1638, n1643, n1648, n1653, n1658, + n1663, n1668, n1673, n1678, n1683, n1688, n1693, n1698, n1703, n1708, + n1713, n1718, n1723, n1728, n1733, n1738, n1743, n1748, n1753, n1758, + n1763, n1768, n1773, n1778, n1783, n1788, n1793, n1798, n1803, n1808, + n1813, n1818, n1823, n1828, n1833, n1838, n1843, n1848, n1853, n1858, + n1863, n1868, n1873, n1878, n1883, n1888, n1893, n1898, n1903, n1908, + n1913, n1918, n1923, n1928, n1933, n1938, n1943, n1948, n1953, n1958, + n1963, n1968, n1973, n1978, n1983, n1988, n1993, n1998, n2003, n2008, + n2013, n2018, n2023, n2028, n2033, n2038, n2043, n2048, n2053, n2058, + n2063, n2068, n2073, n2078, n2083, n2088, n2093, n2098, n2103, n2108, + n2113, n2118, n2123, n2128, n2133, n2138, n2143, n2148, n2153, n2158, + n2163, n2168, n2173, n2178, n2183, n2188, n2193, n2198, n2203, n2208, + n2213, n2218, n2223, n2228, n2233, n2238, n2243, n2248, n2253, n2258, + n2263, n2268; + assign pv14_2_2_ = n_n3358 & n_n4153; + assign pv12_3_3_ = n_n3631 & n_n3367; + assign pv10_4_4_ = n_n3042 ? n_n4136 : tin_pv10_4_4_; + assign pv7_5_5_ = n_n3130 & n_n3679; + assign pv3_6_6_ = n_n3252 & n_n3057; + assign pv15_2_2_ = n_n3113 & n_n4037; + assign pv13_3_3_ = n_n3600 & n_n3404; + assign pv11_4_4_ = n_n4120 ? n_n3966 : tin_pv11_4_4_; + assign pv6_7_7_ = n_n4164 ? n_n3370 : tin_pv6_7_7_; + assign pv2_0_0_ = n_n3211 ? n_n3910 : tin_pv2_0_0_; + assign pv14_1_1_ = n_n3012 & n_n3038; + assign pv12_2_2_ = n_n3067 & n_n3576; + assign pv10_3_3_ = n_n4129 ? n_n3213 : tin_pv10_3_3_; + assign pv9_0_0_ = n_n3128 & n_n3890; + assign pv5_1_1_ = n_n3443 & n_n3287; + assign pv1_2_2_ = n_n3470 ? n_n3537 : tin_pv1_2_2_; + assign pv15_1_1_ = n_n3606 & n_n3108; + assign pv13_2_2_ = n_n3379 & n_n3463; + assign pv11_3_3_ = n_n3432 ? n_n3583 : tin_pv11_3_3_; + assign pv8_2_2_ = n_n3456 & n_n3055; + assign pv4_3_3_ = n_n3489 ? n_n4309 : tin_pv4_3_3_; + assign pv14_0_0_ = n_n3761 & n_n3903; + assign pv12_1_1_ = n_n3264 & n_n4390; + assign pv10_2_2_ = n_n3065 ? n_n3549 : tin_pv10_2_2_; + assign pv7_6_6_ = n_n3670 & n_n3617; + assign pv3_7_7_ = n_n3590 & n_n4102; + assign pv15_0_0_ = n_n4003 & n_n3188; + assign pv13_1_1_ = n_n3221 & n_n3150; + assign pv11_2_2_ = n_n3152 ? n_n3823 : tin_pv11_2_2_; + assign pv6_0_0_ = n_n3029 ? n_n3506 : tin_pv6_0_0_; + assign pv2_1_1_ = n_n3999 ? n_n3646 : tin_pv2_1_1_; + assign pv12_0_0_ = n_n3098 & n_n3339; + assign pv10_1_1_ = n_n3872 ? n_n3270 : tin_pv10_1_1_; + assign pv9_1_1_ = n_n3024 & n_n3044; + assign pv5_2_2_ = n_n4286 & n_n3350; + assign pv1_3_3_ = n_n3441 ? n_n4180 : tin_pv1_3_3_; + assign pv13_0_0_ = n_n3061 & n_n3434; + assign pv11_1_1_ = n_n4185 ? n_n4142 : tin_pv11_1_1_; + assign pv8_3_3_ = n_n3146 & n_n3091; + assign pv4_4_4_ = n_n4110 ? n_n3627 : tin_pv4_4_4_; + assign pready_0_0_ = n_n4108 ? n_n3354 : tin_pready_0_0_; + assign pv10_0_0_ = n_n4282 ? n_n4209 : tin_pv10_0_0_; + assign pv7_7_7_ = n_n3136 & n_n4077; + assign pv3_0_0_ = n_n3173 & n_n3828; + assign pv11_0_0_ = n_n3233 ? n_n3514 : tin_pv11_0_0_; + assign pv6_1_1_ = n_n3144 ? n_n3952 : tin_pv6_1_1_; + assign pv2_2_2_ = n_n4354 ? n_n3202 : tin_pv2_2_2_; + assign pv9_2_2_ = n_n3736 & n_n3157; + assign pv5_3_3_ = n_n3321 & n_n4236; + assign pv1_4_4_ = n_n3863 ? n_n3806 : tin_pv1_4_4_; + assign pv8_4_4_ = n_n3344 & n_n3095; + assign pv4_5_5_ = n_n3087 ? n_n3733 : tin_pv4_5_5_; + assign pv7_0_0_ = n_n3161 & n_n3069; + assign pv3_1_1_ = n_n3048 & n_n3461; + assign pv6_2_2_ = n_n3307 ? n_n3138 : tin_pv6_2_2_; + assign pv2_3_3_ = n_n3874 ? n_n3465 : tin_pv2_3_3_; + assign pv9_3_3_ = n_n3906 & n_n3749; + assign pv5_4_4_ = n_n3793 & n_n4213; + assign pv1_5_5_ = n_n3101 ? n_n3313 : tin_pv1_5_5_; + assign pv8_5_5_ = n_n3116 & n_n3331; + assign pv4_6_6_ = n_n3774 ? n_n3413 : tin_pv4_6_6_; + assign pv7_1_1_ = n_n3415 & n_n3971; + assign pv3_2_2_ = n_n3190 & n_n3739; + assign pv6_3_3_ = n_n3204 ? n_n3486 : tin_pv6_3_3_; + assign pv2_4_4_ = n_n3643 ? n_n3133 : tin_pv2_4_4_; + assign pv9_4_4_ = n_n3687 & n_n3650; + assign pv5_5_5_ = n_n3266 & n_n3408; + assign pv1_6_6_ = n_n4018 ? n_n3118 : tin_pv1_6_6_; + assign pv8_6_6_ = n_n3180 & n_n3223; + assign pv4_7_7_ = n_n4114 ? n_n4166 : tin_pv4_7_7_; + assign pv7_2_2_ = n_n3497 & n_n4105; + assign pv3_3_3_ = n_n3274 & n_n4342; + assign pv6_4_4_ = n_n3093 ? n_n4065 : tin_pv6_4_4_; + assign pv2_5_5_ = n_n4059 ? n_n3780 : tin_pv2_5_5_; + assign pv14_7_7_ = n_n3449 & n_n4241; + assign pv9_5_5_ = n_n3985 & n_n4290; + assign pv5_6_6_ = n_n3567 & n_n3237; + assign pv1_7_7_ = n_n3544 ? n_n4199 : tin_pv1_7_7_; + assign pv15_7_7_ = n_n3079 & n_n3648; + assign pv8_7_7_ = n_n3525 & n_n3529; + assign pv4_0_0_ = n_n3826 ? n_n3517 : tin_pv4_0_0_; + assign pv14_6_6_ = n_n3713 & n_n3262; + assign pv12_7_7_ = n_n3764 & n_n3720; + assign pv7_3_3_ = n_n3411 & n_n4303; + assign pv3_4_4_ = n_n3729 & n_n4162; + assign pv15_6_6_ = n_n4375 & n_n3020; + assign pv13_7_7_ = n_n3372 & n_n3394; + assign pv6_5_5_ = n_n3348 ? n_n4189 : tin_pv6_5_5_; + assign pv2_6_6_ = n_n3120 ? n_n3385 : tin_pv2_6_6_; + assign pv14_5_5_ = n_n3008 & n_n3663; + assign pv12_6_6_ = n_n3782 & n_n3896; + assign pv10_7_7_ = n_n3521 ? n_n3225 : tin_pv10_7_7_; + assign pv9_6_6_ = n_n4243 & n_n3239; + assign pv5_7_7_ = n_n3111 & n_n4005; + assign pv1_0_0_ = n_n3551 ? n_n4192 : tin_pv1_0_0_; + assign pv15_5_5_ = n_n3277 & n_n3674; + assign pv13_6_6_ = n_n3155 & n_n3797; + assign pv11_7_7_ = n_n3360 ? n_n3376 : tin_pv11_7_7_; + assign pv8_0_0_ = n_n3014 & n_n4320; + assign pv4_1_1_ = n_n4089 ? n_n3722 : tin_pv4_1_1_; + assign pv14_4_4_ = n_n3326 & n_n3089; + assign pv12_5_5_ = n_n3619 & n_n3337; + assign pv10_6_6_ = n_n3570 ? n_n3342 : tin_pv10_6_6_; + assign pv7_4_4_ = n_n3073 & n_n3053; + assign pv3_5_5_ = n_n3436 & n_n3142; + assign pv15_4_4_ = n_n3305 & n_n3667; + assign pv13_5_5_ = n_n4139 & n_n3777; + assign pv11_6_6_ = n_n3504 ? n_n4279 : tin_pv11_6_6_; + assign pv6_6_6_ = n_n3836 ? n_n3429 : tin_pv6_6_6_; + assign pv2_7_7_ = n_n4131 ? n_n3126 : tin_pv2_7_7_; + assign pv14_3_3_ = n_n3396 & n_n3316; + assign pv12_4_4_ = n_n3231 & n_n3175; + assign pv10_5_5_ = n_n3381 ? n_n4247 : tin_pv10_5_5_; + assign pv9_7_7_ = n_n3319 & n_n3040; + assign pv5_0_0_ = n_n3195 & n_n3572; + assign pv1_1_1_ = n_n3215 ? n_n3183 : tin_pv1_1_1_; + assign pv15_3_3_ = n_n4172 & n_n3051; + assign pv13_4_4_ = n_n3075 & n_n3758; + assign pv11_5_5_ = n_n3081 ? n_n3207 : tin_pv11_5_5_; + assign pv8_1_1_ = n_n3938 & n_n3883; + assign pv4_2_2_ = n_n4347 ? n_n4372 : tin_pv4_2_2_; + assign n349 = n2312 | (n_n3724 & ~n1922 & n2315); + assign n354 = (pv11_1_1_ & n1835) | n2311; + assign n359 = n2309 | n2307 | n2308; + assign n364 = n2306 | (n_n3035 & n_n4157 & n1839); + assign n369 = n2305 | n2303 | n2304; + assign n374 = ~preset & n1837; + assign n379 = ~preset & (n_n3144 | (~pdn & n1870)); + assign n384 = ~preset & (n_n3782 | (~pdn & n1870)); + assign n389 = ~preset & (n_n3067 | (~pdn & n1870)); + assign n394 = (pv10_3_3_ & n1838_1) | n2302; + assign n399 = (n_n4360 & n1839) | n2301; + assign n404 = ~preset & (n_n3180 | (~pdn & n1870)); + assign n409 = ~preset & (n_n3274 | (~pdn & n1870)); + assign n414 = n_n3475 ? (n1841 | (n1840 & n1990)) : (n1840 & ~n1990); + assign n419 = (n_n3458 & n1839) | n2300; + assign n424 = ~preset & (n_n3381 | (~pdn & n1870)); + assign n429 = n2299 | (n_n3688 & n_n3624 & n1839); + assign n434 = ~preset & n1842; + assign n439 = n2298 | (n_n3901 & n1839 & n1890); + assign n444 = n2297 | (n1839 & (~n_n3916 ^ n1930)); + assign n449 = (n1844 & n1845) | n2282; + assign n454 = (pv6_0_0_ & n1846) | n2281; + assign n459 = ~preset & (n_n3029 | (~pdn & n1870)); + assign n464 = ~preset & (n_n3619 | (~pdn & n1870)); + assign n469 = ~preset & (n_n3264 | (~pdn & n1870)); + assign n474 = n2280 | (n1839 & (n_n4288 | n2319)); + assign n479 = n1847 & ~preset & ~ngfdn_3; + assign n484 = ~preset & (n_n4114 | (~pdn & n1870)); + assign n489 = ~preset & (n_n3146 | (~pdn & n1870)); + assign n494 = (pv1_5_5_ & n1848_1) | n2279; + assign n499 = ~preset & (n_n3152 | (~pdn & n1870)); + assign n504 = preset | (n_n3833 & n1850) | (~n1849 & ~n1850); + assign n509 = ~preset & (n_n4282 | (~pdn & n1870)); + assign n514 = ~preset & (n_n3305 | (~pdn & n1870)); + assign n519 = n2278 | (n1851 & (~n1905 ^ n1978_1)); + assign n524 = (pv4_5_5_ & n1852) | n2277; + assign n529 = ~preset & (~n1983_1 | ~n1984) & n2331; + assign n534 = ~preset & (n_n3204 | (~pdn & n1870)); + assign n539 = ~preset & (n_n3024 | (~pdn & n1870)); + assign n544 = ~preset & (n_n4139 | (~pdn & n1870)); + assign n549 = ~ngfdn_3 & ~preset & ndn3_15; + assign n554 = n2274 | (n1839 & (n_n3458 | n2332)); + assign n559 = n2262 | (n2038 & (~n1909 ^ n1974)); + assign n564 = (n_n3743 & n1839) | n2261; + assign n569 = (pv1_2_2_ & n1848_1) | n2260; + assign n574 = ~preset & (n_n3456 | (~pdn & n1870)); + assign n579 = ~preset & (n_n3521 | (~pdn & n1870)); + assign n584 = ~preset & (n_n3081 | (~pdn & n1870)); + assign n589 = n2257 | (n1853_1 & (n2258_1 | n2336)); + assign n594 = n2256 | (n_n3475 & n1839 & n1890); + assign n599 = (pv11_2_2_ & n1835) | n2255; + assign n604 = n_n4045 & n2337 & (n1890 | ~n2335); + assign n609 = (n1844 & n1851) | n2254; + assign n614 = n2253_1 | (n1845 & (~n1909 ^ n1974)); + assign n619 = ~preset & (n_n3195 | (~pdn & n1870)); + assign n624 = (n_n3242 & n1839) | n2252; + assign n629 = (n_n3916 & n1839) | n2251; + assign n634 = (pv10_4_4_ & n1838_1) | n2250; + assign n639 = ~preset & ~ngfdn_3 & (ndn3_4 | ndn3_5); + assign n644 = (n_n3946 & n1839) | n2249; + assign n649 = ~preset & (n_n3489 | (~pdn & n1870)); + assign n654 = n2248_1 | (n_n3242 & n_n3170 & n1839); + assign n659 = (pv2_3_3_ & n1854) | n2247; + assign n664 = n2246 | preset | n1855; + assign n669 = (n_n4159 & n1839) | n2245; + assign n674 = (pv4_1_1_ & n1852) | n2244; + assign n679 = n2243_1 | (n1845 & (~n1905 ^ n1978_1)); + assign n684 = n2242 | (n_n3936 & n_n3099 & n1839); + assign n689 = (pv6_5_5_ & n1846) | n2241; + assign n694 = ~preset & (n_n3372 | (~pdn & n1870)); + assign n699 = (n_n4074 & n1839) | n2240; + assign n704 = n2239 | (n2038 & (n1972 ^ n1973_1)); + assign n709 = n2238_1 | (n1839 & (n_n4233 | n2338)); + assign n714 = n2237 | (n_n3035 & n_n4157 & n1839); + assign n719 = ~preset & (n_n3411 | (~pdn & n1870)); + assign n724 = n2236 | (n_n4074 & n_n3578 & n1839); + assign n729 = ~preset & (n_n3396 | (~pdn & n1870)); + assign n734 = ~preset & (n_n3432 | (~pdn & n1870)); + assign n739 = ~preset & (n_n3606 | (~pdn & n1870)); + assign n744 = (n_n4224 & n1839) | n2235; + assign n749 = (pv11_6_6_ & n1835) | n2234; + assign n754 = n2233_1 | n2231 | n2232; + assign n759 = ~preset & (n_n3120 | (~pdn & n1870)); + assign n764 = (n_n4222 & n1839) | n2230; + assign n769 = (n_n3976 & n1839) | n2229; + assign n774 = ~preset & (n1987 ? n_n3851 : n1953_1); + assign n779 = n2228_1 | (n1839 & (n_n3495 | n2341)); + assign n784 = n2212 | n2213_1; + assign n789 = n2211 | (n_n3556 & n_n4122 & n1839); + assign n794 = n2210 | (n_n3483 & ~n1922 & n2315); + assign n799 = ~preset & (n_n4089 | (~pdn & n1870)); + assign n804 = (n_n4392 & n1839) | n2209; + assign n809 = (n_n4330 & n1839) | n2208_1; + assign n814 = (pv11_5_5_ & n1835) | n2207; + assign n819 = n2206 | (n1839 & (~n_n3841 ^ n1901)); + assign n824 = ~preset & (n_n3321 | (~pdn & n1870)); + assign n829 = ~preset & (n_n3443 | (~pdn & n1870)); + assign n834 = ~preset & (n_n3215 | (~pdn & n1870)); + assign n839 = ~preset & ~ngfdn_3 & (ndn3_10 | nen3_10); + assign n844 = n2205 | (n1839 & (n_n4351 | n2346)); + assign n849 = n1859 & ~preset & ~pdn; + assign n854 = ~preset & (n_n3590 | (~pdn & n1870)); + assign n859 = ~preset & (n_n4110 | (~pdn & n1870)); + assign n864 = ~n1858_1 & (nlc3_3 | (n1956 & n2347)); + assign n869 = n2204 | (n_n4211 & n_n3657 & n1839); + assign n874 = ~preset & (n_n4129 | (~pdn & n1870)); + assign n879 = (n_n4071 & n1839) | n2203_1; + assign n884 = (n1839 & n1860) | n2202; + assign n889 = (pv4_2_2_ & n1852) | n2201; + assign n894 = n1870 & ~preset & ~pdn; + assign n898 = ~preset & (n_n3567 | (~pdn & n1870)); + assign n903 = (pv6_6_6_ & n1846) | n2200; + assign n908 = ~preset & (n_n3075 | (~pdn & n1870)); + assign n913 = n2199 | (~preset & ~pdn & n1870); + assign n918 = n2198_1 | (n1839 & (n_n4351 | n2346)); + assign n923 = ~preset & ~ngfdn_3 & (ndn3_5 | ndn3_6); + assign n928 = ~preset & (n_n3617 | (~pdn & n1870)); + assign n933 = ~preset & (n_n4162 | (~pdn & n1870)); + assign n938 = n2197 | (n_n4012 & ~n1922 & n2315); + assign n943 = ~preset & (n_n4120 | (~pdn & n1870)); + assign n948 = ~preset & (n_n3065 | (~pdn & n1870)); + assign n953 = ~preset & (n_n4005 | (~pdn & n1870)); + assign n958 = ~preset & (n_n3266 | (~pdn & n1870)); + assign n963 = (pv6_7_7_ & n1846) | n2196; + assign n968 = ~preset & (n_n3600 | (~pdn & n1870)); + assign n973 = ~preset & (n_n3415 | (~pdn & n1870)); + assign n978 = (n_n4095 & n1839) | n2195; + assign n983 = ~preset & (n_n3872 | (~pdn & n1870)); + assign n988 = ~preset & (n_n3648 | (~pdn & n1870)); + assign n993 = n2194 | (n_n4211 & n_n3657 & n1839); + assign n998 = ~preset & (n_n3350 | (~pdn & n1870)); + assign n1003 = ~preset & ~ngfdn_3 & (ndn3_6 | ndn3_7); + assign n1008 = ~preset & (n_n3116 | (~pdn & n1870)); + assign n1013 = n2193_1 | (n_n3766 & ~n1922 & n2315); + assign n1018 = (n_n4351 & n1839) | n2192; + assign n1023 = ~preset & (n_n4131 | (~pdn & n1870)); + assign n1028 = n2191 | (n_n3085 & n_n3250 & n1839); + assign n1033 = (n_n3976 & n1839) | n2190; + assign n1038 = (n_n4222 & n1839) | n2189; + assign n1043 = (pv1_4_4_ & n1848_1) | n2188_1; + assign n1048 = (pv1_6_6_ & n1848_1) | n2187; + assign n1053 = (n_n3608 & n1839) | n2186; + assign n1058 = n2185 | n2183_1 | n2184; + assign n1063 = ~preset & (n_n4213 | (~pdn & n1870)); + assign n1068 = n2182 | (n_n3688 & n_n3624 & n1839); + assign n1073 = ~preset & ~ngfdn_3 & (ndn3_7 | ndn3_8); + assign n1078 = ~preset & (n_n3252 | (~pdn & n1870)); + assign n1083 = n_n4366 ? (n1841 | (n1840 & n1991)) : (n1840 & ~n1991); + assign n1088 = (pv2_1_1_ & n1854) | n2181; + assign n1093 = n2180 | n2178_1 | n2179; + assign n1098 = ~preset & (n_n3348 | (~pdn & n1870)); + assign n1103 = ~preset & (n_n3544 | (~pdn & n1870)); + assign n1108 = ~preset & (n_n3101 | (~pdn & n1870)); + assign n1113 = n2177 | (n_n4334 & ~n1922 & n2315); + assign n1118 = n2176 | (n_n3556 & n_n4122 & n1839); + assign n1123 = (n_n3495 & n1839) | n2175; + assign n1128 = (pv4_6_6_ & n1852) | n2174; + assign n1133 = ~preset & (n_n3650 | (~pdn & n1870)); + assign n1138 = ~preset & (n_n3307 | (~pdn & n1870)); + assign n1143 = (pv1_3_3_ & n1848_1) | n2173_1; + assign n1148 = n_n4334 ? (n1872 | n2171) : n1862; + assign n1153 = n2169 | (n1853_1 & (n2170 | n2350)); + assign n1158 = ~preset & (n_n4164 | (~pdn & n1870)); + assign n1163 = (n_n4145 & n1839) | n2168_1; + assign n1168 = ~preset & (n_n3749 | (~pdn & n1870)); + assign n1173 = n2166 | n2167; + assign n1178 = ~preset & (n_n4347 | (~pdn & n1870)); + assign n1183 = ~preset & (n_n3826 | (~pdn & n1870)); + assign n1188 = ~preset & (n_n3360 | (~pdn & n1870)); + assign n1193 = n2165 | (n1851 & (~n1909 ^ n1974)); + assign n1198 = ~preset & (n_n3093 | (~pdn & n1870)); + assign n1203 = ~preset & (n_n3157 | (~pdn & n1870)); + assign n1208 = (n_n4349 & n1839) | n2164; + assign n1213 = ~preset & (n_n3161 | (~pdn & n1870)); + assign n1218 = (n_n4233 & n1839) | n2163_1; + assign n1223 = (n_n3892 & n1839) | n2162; + assign n1228 = n2161 | (n_n4125 & n1839 & n1890); + assign n1233 = n2160 | (n_n3242 & n_n3170 & n1839); + assign n1238 = (pv4_7_7_ & n1852) | n2159; + assign n1243 = (n1851 & n1863_1) | n2158_1; + assign n1248 = n2157 | (n_n3936 & n_n3099 & n1839); + assign n1253 = ~preset & (n_n3130 | (~pdn & n1870)); + assign n1258 = ~n1864 & ~preset & nsr4_2; + assign n1263 = n2156 | (~preset & n_n4047 & ~n1886); + assign n1268 = (pv2_2_2_ & n1854) | n2155; + assign n1273 = ~preset & (n_n3239 | (~pdn & n1870)); + assign n1278 = n2153_1 | n2154; + assign n1283 = ~preset & (n_n3890 | (~pdn & n1870)); + assign n1288 = n2152 | (n1839 & (n_n3608 | n2324)); + assign n1293 = (n_n3085 & n1839) | n2151; + assign n1298 = (n_n4288 & n1839) | n2150; + assign n1303 = ~preset & (n_n3326 | (~pdn & n1870)); + assign n1308 = n2147 | (n1853_1 & (n2149 | n2352)); + assign n1313 = pdn | preset | (nsr4_2 & n1864); + assign n1318 = n2145 | (n1853_1 & (n2146 | n2353)); + assign n1323 = ~preset & (n_n4375 | (~pdn & n1870)); + assign n1328 = n1865 & ~preset & ~n1855; + assign n1333 = ~preset & (n_n4290 | (~pdn & n1870)); + assign n1338 = (n1845 & n1863_1) | n2144; + assign n1343 = n2142 | n2143_1; + assign n1348 = ~preset & (n_n3774 | (~pdn & n1870)); + assign n1353 = ~preset & (n_n3014 | (~pdn & n1870)); + assign n1358 = ~preset & (n_n4241 | (~pdn & n1870)); + assign n1363 = (n_n4201 & n1839) | n2141; + assign n1368 = n2140 | (n1839 & (~n_n4145 ^ n1895)); + assign n1373 = (pv6_2_2_ & n1846) | n2139; + assign n1378 = (pv6_4_4_ & n1846) | n2138_1; + assign n1383 = ~preset & (n_n3551 | (~pdn & n1870)); + assign n1388 = ~preset & (n_n3379 | (~pdn & n1870)); + assign n1393 = (n_n4275 & n1868_1) | n2133_1; + assign n1398 = ~preset & (n_n3570 | (~pdn & n1870)); + assign n1403 = (pv2_5_5_ & n1854) | n2132; + assign n1408 = n2131 | n2358; + assign n1413 = (pv2_7_7_ & n1854) | n2130; + assign n1418 = ~preset & (n_n4037 | (~pdn & n1870)); + assign n1423 = n2129 | (n1839 & (~n_n3898 ^ n1896)); + assign n1428 = n2127 | n2128_1; + assign n1433 = (pv6_1_1_ & n1846) | n2126; + assign n1438 = ~preset & (n_n3339 | (~pdn & n1870)); + assign n1443 = (pv10_5_5_ & n1838_1) | n2125; + assign n1448 = n2123_1 | (n_n4334 & ~n_n3483 & n1862); + assign n1453 = ~preset & n2357 & (n_n4099 ^ n1967); + assign n1458 = ~preset & (n_n4185 | (~pdn & n1870)); + assign n1463 = n2122 | (n_n3934 & n1839 & n1890); + assign n1468 = ~preset & (n_n3643 | (~pdn & n1870)); + assign n1473 = (n_n4229 & n1839) | n2121; + assign n1478 = (n_n4145 & n1839) | n2120; + assign n1483 = n2119 | (n1839 & (n_n4095 | n2345)); + assign n1488 = ~preset & (n_n3828 | (~pdn & n1870)); + assign n1493 = n2118_1 | (n_n3085 & n_n3250 & n1839); + assign n1498 = (n_n3968 & n1839) | n2117; + assign n1503 = pdn | preset | (~ngfdn_3 & ~n1870); + assign n1508 = (n_n3922 & n1839) | n2116; + assign n1513 = n2115 | (n_n4366 & n1839 & n1890); + assign n1518 = (n1839 & n1871) | n2114; + assign n1523 = n2112 | n2113_1; + assign n1528 = ~preset & (n_n4059 | (~pdn & n1870)); + assign n1533 = (n_n3898 & n1839) | n2111; + assign n1538 = ~preset & ~ngfdn_3 & (nen3_10 | ndn3_9); + assign n1543 = ~preset & (n_n3461 | (~pdn & n1870)); + assign n1548 = (n_n4012 & n1872) | n2110; + assign n1553 = ~preset & (n_n3051 | (~pdn & n1870)); + assign n1558 = n2109 | (n_n4047 & n1839 & n1890); + assign n1563 = (n_n3898 & n1839) | n2108_1; + assign n1568 = n2359 & (n2107 | (n1878_1 & n2317)); + assign n1573 = (pv10_2_2_ & n1838_1) | n2106; + assign n1578 = n2104 | n2105; + assign n1583 = (pv1_7_7_ & n1848_1) | n2103_1; + assign n1588 = ~preset & (n_n3504 | (~pdn & n1870)); + assign n1593 = n2362 | (n_n4045 & (n2102 | n2361)); + assign n1598 = ~n2100 & (~n1853_1 | (~n2101 & ~n2363)); + assign n1603 = n2099 | (n_n4324 & n1839 & n1890); + assign n1608 = (n_n4383 & n1839) | n2098_1; + assign n1613 = n2097 | (n1839 & (~n_n4229 ^ n1902)); + assign n1618 = ~preset & (n_n3040 | (~pdn & n1870)); + assign n1623 = ~preset & (n_n3874 | (~pdn & n1870)); + assign n1628 = ~preset & (n_n3999 | (~pdn & n1870)); + assign n1633 = (n_n4122 & n1839) | n2096; + assign n1638 = ndn1_34 & ~preset & ~pdn; + assign n1643 = (pv10_1_1_ & n1838_1) | n2095; + assign n1648 = (n2038 & n1844) | n2094; + assign n1653 = (n_n4258 & n1839) | n2093_1; + assign n1658 = ~preset & (n_n3095 | (~pdn & n1870)); + assign n1663 = ~preset & (n_n3663 | (~pdn & n1870)); + assign n1668 = n_n3724 ? n1874 : (n_n3814 & n1836); + assign n1673 = ~preset & (n_n3038 | (~pdn & n1870)); + assign n1678 = (n_n4337 & n1839) | n2092; + assign n1683 = (pv11_0_0_ & n1835) | n2091; + assign n1688 = (pv11_4_4_ & n1835) | n2090; + assign n1693 = n2089 | (n_n3556 & n_n4122 & n1839); + assign n1698 = n2088_1 | (n_n4074 & n_n3578 & n1839); + assign n1703 = ~preset & (n_n3211 | (~pdn & n1870)); + assign n1708 = ~preset & (n_n3367 | (~pdn & n1870)); + assign n1713 = ~preset & (n_n3434 | (~pdn & n1870)); + assign n1718 = n2087 | (n1839 & (n_n4233 | n2338)); + assign n1723 = n2086 | (n_n3688 & n_n3624 & n1839); + assign n1728 = (n_n3876 & n1839) | n2085; + assign n1733 = ~preset & (n_n3053 | (~pdn & n1870)); + assign n1738 = ~preset & (n_n3938 | (~pdn & n1870)); + assign n1743 = n2084 | (~preset & n_n3769 & ~n1886); + assign n1748 = n2083_1 | (n_n3936 & n_n3099 & n1839); + assign n1753 = n1858_1 | (nsr3_17 & (~nen3_10 | ~n1855)); + assign n1758 = ~preset & (n_n3903 | (~pdn & n1870)); + assign n1763 = n2364 & (n_n3658 | (n1890 & n2322)); + assign n1768 = ~preset & ~ngfdn_3 & (nrq3_11 | ~nsr3_14); + assign n1773 = n2082 | n2080 | n2081; + assign n1778 = (pv6_3_3_ & n1846) | n2079; + assign n1783 = (n_n4316 & n1839) | n2078_1; + assign n1788 = ~preset & (n_n3175 | (~pdn & n1870)); + assign n1793 = (n_n3657 & n1839) | n2077; + assign n1798 = n2076 | (n1839 & (n_n3495 | n2341)); + assign n1803 = n2075 | (n1839 & (n_n4095 | n2345)); + assign n1808 = ~preset & (n_n4077 | (~pdn & n1870)); + assign n1813 = ~preset & (n_n3142 | (~pdn & n1870)); + assign n1818 = n2074 | (~preset & n_n3901 & ~n1886); + assign n1823 = n2072 | (~n_n3934 & n_n3976 & n1840); + assign n1828 = n2071 | (n_n4227 & ~n1922 & n2315); + assign n1833 = (n_n4160 & n1839) | n2070; + assign n1838 = (n_n4182 & n1839) | n2069; + assign n1843 = (pv4_0_0_ & n1852) | n2068_1; + assign n1848 = (pv4_4_4_ & n1852) | n2067; + assign n1853 = ~preset & (n_n3836 | (~pdn & n1870)); + assign n1858 = ~preset & (n_n3470 | (~pdn & n1870)); + assign n1863 = (n_n4157 & n1839) | n2066; + assign n1868 = (n_n3099 & n1839) | n2065; + assign n1873 = (pv10_6_6_ & n1838_1) | n2064; + assign n1878 = (n2038 & n1863_1) | n2063_1; + assign n1883 = ~preset & ~ngfdn_3 & (ndn3_8 | ndn3_9); + assign n1888 = (pv1_1_1_ & n1848_1) | n2062; + assign n1893 = ~preset & (n_n3190 | (~pdn & n1870)); + assign n1898 = n2060 | (n1853_1 & (n2061 | n2365)); + assign n1903 = ~preset & (n_n3042 | (~pdn & n1870)); + assign n1908 = n2059 | preset | pdn; + assign n1913 = n2058_1 | preset | n2057; + assign n1918 = ~preset & (n_n3188 | (~pdn & n1870)); + assign n1923 = n2056 | (n_n3769 & n1839 & n1890); + assign n1928 = (pv11_3_3_ & n1835) | n2055; + assign n1933 = (pv11_7_7_ & n1835) | n2054; + assign n1938 = (n_n3916 & n1839) | n2053_1; + assign n1943 = n2052 | (n1839 & (n_n3608 | n2324)); + assign n1948 = n2051 | (n1839 & (n_n4392 | n2339)); + assign n1953 = ~preset & (n_n3150 | (~pdn & n1870)); + assign n1958 = (n_n3688 & n1839) | n2050; + assign n1963 = (pv10_7_7_ & n1838_1) | n2049; + assign n1968 = (n_n4362 & n1839) | n2048_1; + assign n1973 = n2047 | (n_n3242 & n_n3170 & n1839); + assign n1978 = n2046 | (n_n4275 & ~n1922 & n2315); + assign n1983 = n2045 | (n1836 & n2366); + assign n1988 = (pv2_4_4_ & n1854) | n2044; + assign n1993 = (pv2_6_6_ & n1854) | n2043_1; + assign n1998 = n2042 | (n_n3814 & ~n1922 & n2315); + assign n2003 = n2041 | (n1839 & (~n_n4159 ^ ~n_n3976)); + assign n2008 = (n_n4270 & n1839) | n2040; + assign n2013 = n2039 | (n1845 & (n1972 ^ n1973_1)); + assign n2018 = (n_n3841 & n1839) | n2038_1; + assign n2023 = n2036 | n2037; + assign n2028 = ~preset & (n_n3863 | (~pdn & n1870)); + assign n2033 = ~preset & (n_n3720 | (~pdn & n1870)); + assign n2038 = ~ngfdn_3 & ~preset & nrq3_11; + assign n2043 = (pv10_0_0_ & n1838_1) | n2035; + assign n2048 = n2034 | (n1839 & (n_n3458 | n2332)); + assign n2053 = (n_n4299 & n1839) | n2033_1; + assign n2058 = ~preset & (n_n3529 | (~pdn & n1870)); + assign n2063 = (n_n3756 & n1839) | n2032; + assign n2068 = n_n4324 ? (n1841 | (n1840 & n1994)) : (n1840 & ~n1994); + assign n2073 = n2031 | (n_n3035 & n_n4157 & n1839); + assign n2078 = n2030 | (n_n4227 & (n1874 | n2136)); + assign n2083 = ~preset & (n_n4153 | (~pdn & n1870)); + assign n2088 = n2029 | n2368; + assign n2093 = ~preset & (n_n3233 | (~pdn & n1870)); + assign n2098 = ~preset & n1881; + assign n2103 = (n_n4251 & n1839) | n2028_1; + assign n2108 = (pv4_3_3_ & n1852) | n2027; + assign n2113 = n2025 | n2026; + assign n2118 = ~preset & (n_n3441 | (~pdn & n1870)); + assign n2123 = ~preset & ~n1855 & (n_n4026 | n2024); + assign n2128 = (n_n4229 & n1839) | n2023_1; + assign n2133 = (n_n3841 & n1839) | n2022; + assign n2138 = n2021 | (n1839 & (n_n4288 | n2319)); + assign n2143 = n2020 | (n_n3085 & n_n3250 & n1839); + assign n2148 = (pv1_0_0_ & n1848_1) | n2019; + assign n2153 = (pv2_0_0_ & n1854) | n2018_1; + assign n2158 = n2016 | (n1853_1 & (n2017 | n2369)); + assign n2163 = n2014 | (n1853_1 & (n2015 | n2370)); + assign n2168 = (n_n3533 & n1839) | n2013_1; + assign n2173 = n1882 & ~preset & n_n4057; + assign n2178 = ~preset & (n_n3674 | (~pdn & n1870)); + assign n2183 = n2011 | (n_n3959 & n1884) | n2010; + assign n2188 = n2009 | (n1851 & (n1972 ^ n1973_1)); + assign n2193 = n2008_1 | n2006 | n2007; + assign n2198 = ~preset & (n_n4018 | (~pdn & n1870)); + assign n2203 = ~preset & (n_n4354 | (~pdn & n1870)); + assign n2208 = ~preset & (n_n3797 | (~pdn & n1870)); + assign n2213 = (n_n4316 & n1839) | n2005; + assign n2218 = n2004 | (n1839 & (n_n4392 | n2339)); + assign n2223 = n2003_1 | (n2038 & (~n1905 ^ n1978_1)); + assign n2228 = n2002 | (n_n4211 & n_n3657 & n1839); + assign n2233 = n2001 | (n_n4074 & n_n3578 & n1839); + assign n2238 = ~preset & (n_n3087 | (~pdn & n1870)); + assign n2243 = ~preset & (n_n4105 | (~pdn & n1870)); + assign n2248 = ~preset & (n_n3262 | (~pdn & n1870)); + assign n2253 = (n1886 & n2371) | (~preset & n_n4125 & ~n1886); + assign n2258 = n2000 | (~n_n3814 & n1836); + assign n2263 = ~n2374 | (~n1997 & (~n1878_1 | ~n2372)); + assign n2268 = n1858_1 | (nsr3_3 & (~n1956 | n1996)); + assign n1835 = ~ndn3_9 & ~preset & ndn3_8; + assign n1836 = n_n3709 & n_n3707 & ~preset & ~n_n3198; + assign n1837 = (~n_n3658 & (n1892 ? n2322 : n_n3604)) | (n_n3604 & (n_n3658 | ~n2322)); + assign n1838_1 = ~ndn3_8 & ~preset & ndn3_7; + assign n1839 = ~n1889 & ~nsr1_2 & ~preset & ~pdn; + assign n1840 = n_n4056 & ~n_n3557 & ~preset & n_n4057; + assign n1841 = ~preset & ~n1886; + assign n1842 = n_n4108 | (pdn & ~ndn1_34) | (~pdn & n1870); + assign n1843_1 = ~n_n3916 ^ n1930; + assign n1844 = n1979 ? ((n1906 & ~n1971) | (n1905 & (n1906 | ~n1971))) : ((~n1906 & n1971) | (~n1905 & (~n1906 | n1971))); + assign n1845 = nen3_10 & ~preset & ~ndn3_10; + assign n1846 = ~ndn3_7 & ~preset & ndn3_6; + assign n1847 = ~nsr3_3 | ndn3_4 | (pready_0_0_ & n1956); + assign n1848_1 = n2328 & (~nsr3_3 | (pready_0_0_ & n1956)); + assign n1849 = (n1857 & n1977) | (~n_n4360 & ((n1857 & n1960) | n1977)); + assign n1850 = n1897 | ~n2316 | n_n4067 | (~n_n4067 & n1922); + assign n1851 = ngfdn_3 & ~preset & ~ndn3_15; + assign n1852 = ~ndn3_6 & ~preset & ndn3_5; + assign n1853_1 = ~preset & (n1886 | n1900); + assign n1854 = ~ndn3_5 & ~preset & ndn3_4; + assign n1855 = ~n_n4093 | (n1903_1 & (n1897 | n2310)); + assign n1856 = ((~n_n3916 ^ n_n4040) & (~n1913_1 ^ ~n1930)) | ((~n_n3916 ^ ~n_n4040) & (n1913_1 ^ ~n1930)); + assign n1857 = ~n_n3841 ^ n1901; + assign n1858_1 = preset | pdn; + assign n1859 = nlc1_2 | (~preset_0_0_ & nsr1_2 & (~nlc1_2 | n_n4151)); + assign n1860 = n_n4316 ? (~n1938_1 ^ n1959) : (n1938_1 ^ n1959); + assign n1861 = ((~n_n3988 ^ n_n3898) & (~n1896 ^ ~n1914)) | ((~n_n3988 ^ ~n_n3898) & (n1896 ^ ~n1914)); + assign n1862 = n2349 & n_n4012 & n1836 & n1867; + assign n1863_1 = n1912 ? ((n1910 & n1911) | (n1909 & (n1910 | n1911))) : ((~n1910 & ~n1911) | (~n1909 & (~n1910 | ~n1911))); + assign n1864 = 1'b1; + assign n1865 = n_n4067 | (~n1897 & ~n1922 & n2316); + assign n1866 = ~n_n4145 ^ n1895; + assign n1867 = n_n3724 & n_n4227 & n_n3814; + assign n1868_1 = n1874 | n2134 | n2135 | n2136; + assign n1869 = ~n_n3898 ^ n1896; + assign n1870 = ~nsr1_2 | (preset_0_0_ & ~nlc1_2) | (nlc1_2 & ~n_n4151); + assign n1871 = ((~n_n4160 ^ ~n_n4222) & (~n_n4159 | (n_n4159 & n_n3976))) | (n_n4159 & ~n_n3976 & (~n_n4160 ^ n_n4222)); + assign n1872 = n2172 | (n2318 & (~n1878_1 | ~n2317)); + assign n1873_1 = ~n_n4229 ^ n1902; + assign n1874 = n2137 | (n2318 & (~n1878_1 | ~n2317)); + assign n1875 = ((~n_n4229 ^ n_n3818) & (~n1902 ^ ~n1944)) | ((~n_n4229 ^ ~n_n3818) & (n1902 ^ ~n1944)); + assign n1876 = ~n_n4159 ^ ~n_n3976; + assign n1877 = nrq3_11 & ~ngfdn_3; + assign n1878_1 = n2316 & ~n1897 & ~n2310; + assign n1879 = n_n3831 & ((n_n3851 & (n_n4026 | n1953_1)) | (~n_n4026 & n1953_1)); + assign n1880 = ~n2331 | ~n_n3709 | (n1983_1 & n1984); + assign n1881 = n_n4263 | (~nlc3_3 & n1956 & n2347); + assign n1882 = n1899 | (n_n4056 & (n1950 | ~n2357)); + assign n1883_1 = n_n3959 | (n_n4159 & n_n3976) | (~n_n4159 & ~n_n3976); + assign n1884 = n2012 | (n2318 & (~n1878_1 | ~n2317)); + assign n1885 = ((~n_n4145 ^ n_n4080) & (~n1895 ^ ~n1907)) | ((~n_n4145 ^ ~n_n4080) & (n1895 ^ ~n1907)); + assign n1886 = n_n4056 ? n2323 : (n1890 & n2322); + assign n1887 = (n_n3934 & n_n3976 & (n_n4222 ^ ~n_n4125)) | ((~n_n3934 | ~n_n3976) & (n_n4222 ^ n_n4125)); + assign n1888_1 = n_n4159 | n_n4160 | n_n4383; + assign n1889 = nlc1_2 ? ~n_n4151 : preset_0_0_; + assign n1890 = n_n3658 ? n_n3604 : (n2320 | n2321); + assign n1891 = n_n3955 | ~n_n3954 | n_n4029 | n_n3845; + assign n1892 = n2320 | n2321; + assign n1893_1 = (~n1856 & n1955) | (n1843_1 & (n1955 | (~n1856 & n1942))); + assign n1894 = (n1869 & n1893_1) | (~n1861 & (n1893_1 | (n1869 & n1968_1))); + assign n1895 = n1931 ? ((n_n3898 & (n1932 | n1933_1)) | (n1932 & n1933_1)) : ((~n1932 & ~n1933_1) | (~n_n3898 & (~n1932 | ~n1933_1))); + assign n1896 = n1932 ? ((n_n3916 & (n1962 | n1975)) | (n1962 & n1975)) : ((~n1962 & ~n1975) | (~n_n3916 & (~n1962 | ~n1975))); + assign n1897 = n_n4067 ? ~n_n3833 : n1849; + assign n1898_1 = n_n4056 & n_n4057 & ~n_n3557; + assign n1899 = n2322 & ~n_n4056 & n1890; + assign n1900 = ~n_n3493 & (~n_n4045 | (~n1890 & n2335)); + assign n1901 = n1947 ? ((n1931 & n1934) | (n_n4145 & (n1931 | n1934))) : ((~n1931 & ~n1934) | (~n_n4145 & (~n1931 | ~n1934))); + assign n1902 = n1927 ? ((n_n4316 & (n1938_1 | n1959)) | (n1938_1 & n1959)) : ((~n1938_1 & ~n1959) | (~n_n4316 & (~n1938_1 | ~n1959))); + assign n1903_1 = nen3_10 & nsr3_17; + assign n1904 = ~ndn3_15 & ngfdn_3; + assign n1905 = n2296 | n2294 | n2295; + assign n1906 = n2325 | (nrq3_11 & ~ngfdn_3 & n1871); + assign n1907 = (n_n3988 & n1914) | ((n_n3988 | n1914) & (n_n3898 ^ n1896)); + assign n1908_1 = (n_n4080 & n1907) | ((n_n4080 | n1907) & (~n_n4145 ^ ~n1895)); + assign n1909 = (n1957 & n1958_1) | ((n1957 | n1958_1) & (n2272 | n2273)); + assign n1910 = n2334 | (n1877 & (~n_n3916 ^ n1930)); + assign n1911 = n2265 | n2263_1 | n2264; + assign n1912 = (~n1918_1 & ~n2221 & ~n2222 & ~n2223_1) | (n1918_1 & (n2221 | n2222 | n2223_1)); + assign n1913_1 = (n_n3818 & n1944) | ((n_n3818 | n1944) & (~n_n4229 ^ ~n1902)); + assign n1914 = (n_n4040 & n1913_1) | ((n_n4040 | n1913_1) & (n_n3916 ^ n1930)); + assign n1915 = n2287 | n2285 | n2286; + assign n1916 = n2327 | n1915 | n2284; + assign n1917 = ~n_n3865 ^ n1891; + assign n1918_1 = n2343 | (n1877 & (~n_n3898 ^ n1896)); + assign n1919 = n_n3709 & ~n_n3198 & n_n3707; + assign n1920 = n2342 | (n1877 & (~n_n3841 ^ n1901)); + assign n1921 = n2226 | n2224 | n2225; + assign n1922 = n_n4026 ? ~n_n3851 : ~n1953_1; + assign n1923_1 = (n_n4047 & n1929) | (n_n3916 & (n_n4047 | n1929)); + assign n1924 = (n_n3898 & n1923_1) | (n_n4366 & (n_n3898 | n1923_1)); + assign n1925 = (n1843_1 & n1964) | (~n_n3876 & (n1964 | (n1843_1 & n1981))); + assign n1926 = (n1869 & n1925) | (~n_n4362 & (n1925 | (n1869 & n1965))); + assign n1927 = (~n_n4182 & (n_n4160 | n_n4383 | n_n4159)) | (~n_n4160 & ~n_n4383 & ~n_n4159 & n_n4182); + assign n1928_1 = (~n1940 & ~n2214 & ~n2215 & ~n2216) | (n1940 & (n2214 | n2215 | n2216)); + assign n1929 = (n_n3769 & n1976) | (n_n4229 & (n_n3769 | n1976)); + assign n1930 = n1962 ? ((n1927 & n1982) | (n_n4229 & (n1927 | n1982))) : ((~n1927 & ~n1982) | (~n_n4229 & (~n1927 | ~n1982))); + assign n1931 = (~n_n4251 & (n_n4224 | n1888_1 | ~n2314)) | (~n_n4224 & n_n4251 & ~n1888_1 & n2314); + assign n1932 = (~n_n4224 & (n_n4330 | n_n4182 | n1888_1)) | (n_n4224 & ~n_n4330 & ~n_n4182 & ~n1888_1); + assign n1933_1 = (n_n3916 & n1975) | ((n_n3916 | n1975) & (n_n4330 ^ n1961)); + assign n1934 = (n1932 & n1933_1) | (n_n3898 & (n1932 | n1933_1)); + assign n1935 = (n_n4222 & ((n_n3934 & n_n3976) | n_n4125)) | (n_n3934 & n_n3976 & n_n4125); + assign n1936 = (n_n3574 & (n_n3959 ? ~n1871 : (n1871 & n1876))) | (~n1871 & (~n_n3959 | ~n1876)) | (~n_n3574 & n1871 & ~n1876); + assign n1937 = n1983_1 & (~n1857 | (n1857 & (~n_n3726 ^ ~n1908_1))); + assign n1938_1 = (~n_n4160 & n_n4383 & ~n_n4159) | (~n_n4383 & (n_n4160 | n_n4159)); + assign n1939 = n1918_1 | n2221 | n2222 | n2223_1; + assign n1940 = n2344 | (n1877 & (~n_n4145 ^ n1895)); + assign n1941 = (n_n3995 & (n1860 ? (n1936 & ~n1943_1) : (~n1936 & n1943_1))) | (~n1860 & n1936) | (~n_n3995 & (n1860 ? (n1936 & n1943_1) : (~n1936 & ~n1943_1))); + assign n1942 = (n1875 & n1941) | (~n1873_1 & (n1941 | (n1875 & n1954))); + assign n1943_1 = (~n1871 & n1883_1) | (n_n3574 & (~n1871 | n1883_1)); + assign n1944 = (~n1860 & n1943_1) | (n_n3995 & (~n1860 | n1943_1)); + assign n1945 = (~n_n4381 & ~n_n4052 & ~n_n3865 & ~n1891) | (n_n4381 & (n_n4052 | n_n3865 | n1891)); + assign n1946 = n_n4224 | n_n4251 | n1888_1 | ~n2314; + assign n1947 = ~n_n4270 ^ ~n1946; + assign n1948_1 = (~n_n3955 & n_n3954 & ~n_n4029 & ~n_n3845) | (n_n4029 & (n_n3955 | ~n_n3954 | n_n3845)); + assign n1949 = (~n_n3955 & n_n3954 & ~n_n3845) | (n_n3845 & (n_n3955 | ~n_n3954)); + assign n1950 = ~n_n4099 ^ n1967; + assign n1951 = n_n4052 ^ (n_n3865 | n1891); + assign n1952 = ~n1957 ^ (n2268_1 | n2333); + assign n1953_1 = (~n1857 & n1960) | (n_n4360 & (n1960 | (~n1857 & n1977))); + assign n1954 = (n_n3995 & (n1860 ? (n1936 & n1943_1) : (~n1936 & ~n1943_1))) | (n1860 & ~n1936) | (~n_n3995 & (n1860 ? (n1936 & ~n1943_1) : (~n1936 & n1943_1))); + assign n1955 = (~n1875 & n1954) | (n1873_1 & (n1954 | (~n1875 & n1941))); + assign n1956 = nsr1_2 & ((nlc1_2 & n_n4151) | (~preset_0_0_ & (~nlc1_2 | n_n4151))); + assign n1957 = n2271 | n2269 | n2270; + assign n1958_1 = n2333 | (n1877 & (~n_n4229 ^ n1902)); + assign n1959 = (n_n4159 & ((n_n4222 & n_n3976) | (~n_n4160 & (n_n4222 | n_n3976)))) | (n_n4160 & n_n4222 & ~n_n4159); + assign n1960 = (~n1866 & n1966) | (n_n4299 & (n1966 | (~n1866 & n1926))); + assign n1961 = n_n4160 | n_n4383 | n_n4159 | n_n4182; + assign n1962 = ~n_n4330 ^ ~n1961; + assign n1963_1 = (n1860 & n1985) | (~n_n3946 & (n1985 | (n1860 & ~n1985))); + assign n1964 = (n1873_1 & n1963_1) | (~n_n4258 & (n1963_1 | (n1873_1 & n1980))); + assign n1965 = (~n1843_1 & n1981) | (n_n3876 & (n1981 | (~n1843_1 & n1964))); + assign n1966 = (~n1869 & n1965) | (n_n4362 & (n1965 | (~n1869 & n1925))); + assign n1967 = n_n4381 | n_n4052 | n_n3865 | n1891; + assign n1968_1 = (n1856 & n1942) | (~n1843_1 & (n1942 | (n1856 & n1955))); + assign n1969 = (~n1869 & n1968_1) | (n1861 & (n1968_1 | (~n1869 & n1893_1))); + assign n1970 = n2216 | n2214 | n2215; + assign n1971 = ~n1973_1 | (~n2289 & ~n2290 & ~n2291); + assign n1972 = n2291 | n2289 | n2290; + assign n1973_1 = n2326 | (n_n3934 & n1890 & n1904); + assign n1974 = (~n1910 & ~n2263_1 & ~n2264 & ~n2265) | (n1910 & (n2263_1 | n2264 | n2265)); + assign n1975 = (n1927 & n1982) | (n_n4229 & (n1927 | n1982)); + assign n1976 = (n_n3901 & n1935) | (n_n4316 & (n_n3901 | n1935)); + assign n1977 = (n1866 & n1926) | (~n_n4299 & (n1926 | (n1866 & n1966))); + assign n1978_1 = (n1972 & n1973_1 & (n2293 | n2325)) | (~n2293 & (~n1972 | ~n1973_1) & ~n2325); + assign n1979 = ~n1915 ^ (n2284 | n2327); + assign n1980 = (~n1860 & ~n1985) | (n_n3946 & (~n1985 | (~n1860 & n1985))); + assign n1981 = (~n1873_1 & n1980) | (n_n4258 & (n1980 | (~n1873_1 & n1963_1))); + assign n1982 = (n1938_1 & n1959) | (n_n4316 & (n1938_1 | n1959)); + assign n1983_1 = (n1885 & n1969) | (~n1866 & ((n1885 & n1894) | n1969)); + assign n1984 = (~n_n3841 & n1901) | (n_n3841 & ~n1901) | ((~n_n3841 ^ n1901) & (n_n3726 ^ n1908_1)); + assign n1985 = (n1871 & n2313) | (~n_n3743 & (n1871 | n2313)); + assign n1986 = (~n1970 & ~n2218_1 & ~n2219) | (~n1940 & (~n1970 | (~n2218_1 & ~n2219))); + assign n1987 = n1897 | n2310 | ~n2316 | n2340; + assign n1988_1 = ndn3_4 | (nsr3_3 & (~pready_0_0_ | ~n1956)); + assign n1989 = n1890 & ~n_n3493 & ~n_n4045; + assign n1990 = n_n4145 ? ((n_n4366 & (n_n3898 | n1923_1)) | (n_n3898 & n1923_1)) : ((~n_n3898 & ~n1923_1) | (~n_n4366 & (~n_n3898 | ~n1923_1))); + assign n1991 = n_n3898 ? ((n_n4047 & n1929) | (n_n3916 & (n_n4047 | n1929))) : ((~n_n4047 & ~n1929) | (~n_n3916 & (~n_n4047 | ~n1929))); + assign n1992 = n_n4047 ? ((n_n3769 & n1976) | (n_n4229 & (n_n3769 | n1976))) : ((~n_n3769 & ~n1976) | (~n_n4229 & (~n_n3769 | ~n1976))); + assign n1993_1 = n_n3769 ? ((n_n4316 & (n_n3901 | n1935)) | (n_n3901 & n1935)) : ((~n_n3901 & ~n1935) | (~n_n4316 & (~n_n3901 | ~n1935))); + assign n1994 = n_n3841 ? ((n_n4145 & n1924) | (n_n3475 & (n_n4145 | n1924))) : ((~n_n4145 & ~n1924) | (~n_n3475 & (~n_n4145 | ~n1924))); + assign n1995 = ~n_n3707 | (~n_n4026 & ~n1953_1) | (~n_n3851 & n_n4026); + assign n1996 = nsr4_2 & ((n_n4108 & ~n_n3354) | (~tin_pready_0_0_ & (~n_n4108 | ~n_n3354))); + assign n1997 = ~preset & (~n_n3831 | n1998_1 | n1999); + assign n1998_1 = n2373 & n2316 & ~n1897 & ~n2310; + assign n1999 = n2316 & ~n2310 & ~n1897 & n1995; + assign n2000 = n_n3814 & (~n1878_1 | ~n2317) & n2318; + assign n2001 = ~preset & n_n3806 & (pdn | ~n1870); + assign n2002 = ~preset & n_n3537 & (pdn | ~n1870); + assign n2003_1 = ~preset & n_n3099 & (~nrq3_11 | ngfdn_3); + assign n2004 = ~preset & n_n3646 & (pdn | ~n1870); + assign n2005 = ~preset & n_n3739 & (pdn | ~n1870); + assign n2006 = n2317 & n1878_1 & ~preset & n_n4299; + assign n2007 = n_n4080 & (~n1878_1 | ~n2317) & n2318; + assign n2008_1 = n1836 & (n_n4080 ? (~n1866 ^ ~n1907) : (n1866 ^ ~n1907)); + assign n2009 = ~preset & n_n3608 & (ndn3_15 | ~ngfdn_3); + assign n2010 = n2317 & n1878_1 & ~preset & n_n3756; + assign n2011 = ~n_n3959 & n1836 & (~n_n4159 ^ ~n_n3976); + assign n2012 = n1836 & (~n_n4159 ^ n_n3976); + assign n2013_1 = ~preset & n_n3486 & (pdn | ~n1870); + assign n2014 = ~n1900 & ~n1886 & ~preset & n_n3865; + assign n2015 = n_n3922 & (n1899 | n2259); + assign n2016 = ~n1900 & ~n1886 & ~preset & n_n3845; + assign n2017 = n_n3968 & (n1899 | n2259); + assign n2018_1 = ~preset & n_n3931 & (~ndn3_4 | ndn3_5); + assign n2019 = n1988_1 & ~preset & n_n3878; + assign n2020 = ~preset & n_n4180 & (pdn | ~n1870); + assign n2021 = ~preset & n_n3277 & (pdn | ~n1870); + assign n2022 = ~preset & n_n4102 & (pdn | ~n1870); + assign n2023_1 = ~preset & n_n4342 & (pdn | ~n1870); + assign n2024 = n2316 & ~n2310 & n1879 & ~n1897; + assign n2025 = ~preset & n_n3841 & (ndn3_10 | ~nen3_10); + assign n2026 = n1845 & (n1920 ? (~n1921 ^ ~n1986) : (n1921 ^ ~n1986)); + assign n2027 = ~preset & n_n4182 & (~ndn3_5 | ndn3_6); + assign n2028_1 = ~preset & n_n3413 & (pdn | ~n1870); + assign n2029 = n_n3831 & (n1897 | n2310 | ~n2316); + assign n2030 = n1836 & n_n3814 & n_n3724 & ~n_n4227; + assign n2031 = ~preset & n_n3337 & (pdn | ~n1870); + assign n2032 = ~preset & n_n4209 & (pdn | ~n1870); + assign n2033_1 = ~preset & n_n3342 & (pdn | ~n1870); + assign n2034 = ~preset & n_n3667 & (pdn | ~n1870); + assign n2035 = ~preset & n_n3756 & (~ndn3_7 | ndn3_8); + assign n2036 = ~preset & n_n4095 & (ndn3_15 | ~ngfdn_3); + assign n2037 = n1851 & (n1928_1 ^ (~n2218_1 & ~n2219)); + assign n2038_1 = ~preset & n_n3394 & (pdn | ~n1870); + assign n2039 = ~preset & n_n3976 & (ndn3_10 | ~nen3_10); + assign n2040 = ~preset & n_n4166 & (pdn | ~n1870); + assign n2041 = ~preset & n_n3572 & (pdn | ~n1870); + assign n2042 = ~preset & n_n3514 & (pdn | ~n1870); + assign n2043_1 = ~preset & n_n4062 & (~ndn3_4 | ndn3_5); + assign n2044 = ~preset & n_n4021 & (~ndn3_4 | ndn3_5); + assign n2045 = n_n3766 & (n1874 | n2135 | n2136); + assign n2046 = ~preset & n_n3966 & (pdn | ~n1870); + assign n2047 = ~preset & n_n4199 & (pdn | ~n1870); + assign n2048_1 = ~preset & n_n4247 & (pdn | ~n1870); + assign n2049 = ~preset & n_n4360 & (~ndn3_7 | ndn3_8); + assign n2050 = ~preset & n_n4320 & (pdn | ~n1870); + assign n2051 = ~preset & n_n3108 & (pdn | ~n1870); + assign n2052 = ~preset & n_n3910 & (pdn | ~n1870); + assign n2053_1 = ~preset & n_n3758 & (pdn | ~n1870); + assign n2054 = ~preset & n_n3170 & (~ndn3_8 | ndn3_9); + assign n2055 = ~preset & n_n3250 & (~ndn3_8 | ndn3_9); + assign n2056 = ~preset & n_n4303 & (pdn | ~n1870); + assign n2057 = nsr1_2 & ~preset_0_0_ & ~nlc1_2; + assign n2058_1 = n_n4151 & (nlc1_2 | ~nsr1_2 | (preset_0_0_ & ~nlc1_2)); + assign n2059 = nsr3_14 & (nsr3_17 | (n_n4045 & n1890)); + assign n2060 = ~n1900 & ~n1886 & ~preset & n_n4029; + assign n2061 = n_n3533 & (n1899 | n2259); + assign n2062 = n1988_1 & ~preset & n_n3208; + assign n2063_1 = ~preset & n_n4157 & (~nrq3_11 | ngfdn_3); + assign n2064 = ~preset & n_n4299 & (~ndn3_7 | ndn3_8); + assign n2065 = ~preset & n_n3883 & (pdn | ~n1870); + assign n2066 = ~preset & n_n3331 & (pdn | ~n1870); + assign n2067 = ~preset & n_n4330 & (~ndn3_5 | ndn3_6); + assign n2068_1 = ~preset & n_n4159 & (~ndn3_5 | ndn3_6); + assign n2069 = ~preset & n_n4309 & (pdn | ~n1870); + assign n2070 = ~preset & n_n3722 & (pdn | ~n1870); + assign n2071 = ~preset & n_n3823 & (pdn | ~n1870); + assign n2072 = n_n3934 & (n2073_1 | (~preset & ~n1886)); + assign n2073_1 = ~n_n3976 & n1840; + assign n2074 = n1840 & (n_n4316 ? (~n_n3901 ^ n1935) : (n_n3901 ^ n1935)); + assign n2075 = ~preset & n_n3385 & (pdn | ~n1870); + assign n2076 = ~preset & n_n3202 & (pdn | ~n1870); + assign n2077 = ~preset & n_n3055 & (pdn | ~n1870); + assign n2078_1 = ~preset & n_n3463 & (pdn | ~n1870); + assign n2079 = ~preset & n_n3533 & (~ndn3_6 | ndn3_7); + assign n2080 = n2317 & n1878_1 & ~preset & n_n4258; + assign n2081 = n_n3818 & (~n1878_1 | ~n2317) & n2318; + assign n2082 = n1836 & (n_n3818 ? (~n1873_1 ^ ~n1944) : (n1873_1 ^ ~n1944)); + assign n2083_1 = ~preset & n_n4390 & (pdn | ~n1870); + assign n2084 = n1840 & (~n_n4229 ^ n1993_1); + assign n2085 = ~preset & n_n4136 & (pdn | ~n1870); + assign n2086 = ~preset & n_n4192 & (pdn | ~n1870); + assign n2087 = ~preset & n_n3126 & (pdn | ~n1870); + assign n2088_1 = ~preset & n_n3089 & (pdn | ~n1870); + assign n2089 = ~preset & n_n3713 & (pdn | ~n1870); + assign n2090 = ~preset & n_n3578 & (~ndn3_8 | ndn3_9); + assign n2091 = ~preset & n_n3624 & (~ndn3_8 | ndn3_9); + assign n2092 = ~preset & n_n3370 & (pdn | ~n1870); + assign n2093_1 = ~preset & n_n3213 & (pdn | ~n1870); + assign n2094 = ~preset & n_n3657 & (~nrq3_11 | ngfdn_3); + assign n2095 = ~preset & n_n3743 & (~ndn3_7 | ndn3_8); + assign n2096 = ~preset & n_n3223 & (pdn | ~n1870); + assign n2097 = ~preset & n_n4236 & (pdn | ~n1870); + assign n2098_1 = ~preset & n_n4372 & (pdn | ~n1870); + assign n2099 = ~preset & n_n3136 & (pdn | ~n1870); + assign n2100 = ~n1900 & ~n1886 & ~preset & ~n_n3954; + assign n2101 = n_n4349 & (n1899 | n2259); + assign n2102 = n2360 & (~n_n4056 | n1950 | ~n2357); + assign n2103_1 = n1988_1 & ~preset & n_n3259; + assign n2104 = ~preset & n_n3085 & (~nrq3_11 | ngfdn_3); + assign n2105 = n2038 & (n1952 ^ (~n2272 & ~n2273)); + assign n2106 = ~preset & n_n3946 & (~ndn3_7 | ndn3_8); + assign n2107 = n_n3709 & ((n1983_1 & n1984) | ~n2331); + assign n2108_1 = ~preset & n_n3777 & (pdn | ~n1870); + assign n2109 = ~preset & n_n3073 & (pdn | ~n1870); + assign n2110 = n2349 & n1867 & ~n_n4012 & n1836; + assign n2111 = ~preset & n_n3436 & (pdn | ~n1870); + assign n2112 = ~preset & n_n4351 & (ndn3_15 | ~ngfdn_3); + assign n2113_1 = n1851 & (n1952 ^ (~n2272 & ~n2273)); + assign n2114 = ~preset & n_n3287 & (pdn | ~n1870); + assign n2115 = ~preset & n_n3679 & (pdn | ~n1870); + assign n2116 = ~preset & n_n4065 & (pdn | ~n1870); + assign n2117 = ~preset & n_n3138 & (pdn | ~n1870); + assign n2118_1 = ~preset & n_n3631 & (pdn | ~n1870); + assign n2119 = ~preset & n_n3020 & (pdn | ~n1870); + assign n2120 = ~preset & n_n3057 & (pdn | ~n1870); + assign n2121 = ~preset & n_n3404 & (pdn | ~n1870); + assign n2122 = ~preset & n_n3069 & (pdn | ~n1870); + assign n2123_1 = n_n3483 & (n1872 | n2124 | n2171); + assign n2124 = ~n_n4334 & n1836; + assign n2125 = ~preset & n_n4362 & (~ndn3_7 | ndn3_8); + assign n2126 = ~preset & n_n4201 & (~ndn3_6 | ndn3_7); + assign n2127 = ~preset & n_n4229 & (ndn3_10 | ~nen3_10); + assign n2128_1 = n1845 & (n1952 ^ (~n2272 & ~n2273)); + assign n2129 = ~preset & n_n3408 & (pdn | ~n1870); + assign n2130 = ~preset & n_n3451 & (~ndn3_4 | ndn3_5); + assign n2131 = n_n4057 & (~n_n4056 | n1950 | ~n2357); + assign n2132 = ~preset & n_n3854 & (~ndn3_4 | ndn3_5); + assign n2133_1 = n2354 & (n1919 | (n1878_1 & n2317)); + assign n2134 = ~n_n3766 & n1836; + assign n2135 = ~n_n4227 & n1836; + assign n2136 = ~n_n3724 & n1836; + assign n2137 = ~n_n3814 & n1836; + assign n2138_1 = ~preset & n_n3922 & (~ndn3_6 | ndn3_7); + assign n2139 = ~preset & n_n3968 & (~ndn3_6 | ndn3_7); + assign n2140 = ~preset & n_n3237 & (pdn | ~n1870); + assign n2141 = ~preset & n_n3952 & (pdn | ~n1870); + assign n2142 = ~preset & n_n4122 & (~nrq3_11 | ngfdn_3); + assign n2143_1 = n2038 & (n1928_1 ^ (~n2218_1 & ~n2219)); + assign n2144 = ~preset & n_n3898 & (ndn3_10 | ~nen3_10); + assign n2145 = ~n1900 & ~n1886 & ~preset & n_n4099; + assign n2146 = n_n4337 & (n1899 | n2259); + assign n2147 = ~n1900 & ~n1886 & ~preset & n_n4052; + assign n2148_1 = n1898_1 & (~n_n4052 ^ (n_n3865 | n1891)); + assign n2149 = n_n4071 & (n1899 | n2259); + assign n2150 = ~preset & n_n3985 & (pdn | ~n1870); + assign n2151 = ~preset & n_n3091 & (pdn | ~n1870); + assign n2152 = ~preset & n_n4003 & (pdn | ~n1870); + assign n2153_1 = ~preset & n_n4145 & (ndn3_10 | ~nen3_10); + assign n2154 = n1845 & (n1928_1 ^ (~n2218_1 & ~n2219)); + assign n2155 = ~preset & n_n3978 & (~ndn3_4 | ndn3_5); + assign n2156 = n1840 & (~n_n3916 ^ n1992); + assign n2157 = ~preset & n_n3183 & (pdn | ~n1870); + assign n2158_1 = ~preset & n_n4288 & (ndn3_15 | ~ngfdn_3); + assign n2159 = ~preset & n_n4270 & (~ndn3_5 | ndn3_6); + assign n2160 = ~preset & n_n3449 & (pdn | ~n1870); + assign n2161 = ~preset & n_n3971 & (pdn | ~n1870); + assign n2162 = ~preset & n_n3429 & (pdn | ~n1870); + assign n2163_1 = ~preset & n_n3319 & (pdn | ~n1870); + assign n2164 = ~preset & n_n3506 & (pdn | ~n1870); + assign n2165 = ~preset & n_n3458 & (ndn3_15 | ~ngfdn_3); + assign n2166 = ~preset & n_n4233 & (ndn3_15 | ~ngfdn_3); + assign n2167 = n1851 & (n1920 ? (~n1921 ^ ~n1986) : (n1921 ^ ~n1986)); + assign n2168_1 = ~preset & n_n3155 & (pdn | ~n1870); + assign n2169 = ~n1900 & ~n1886 & ~preset & n_n3955; + assign n2170 = n_n4201 & (n1899 | n2259); + assign n2171 = ~n_n4012 & n1836; + assign n2172 = n1836 & (~n_n4275 | ~n_n3766 | ~n1867); + assign n2173_1 = n1988_1 & ~preset & n_n4294; + assign n2174 = ~preset & n_n4251 & (~ndn3_5 | ndn3_6); + assign n2175 = ~preset & n_n3736 & (pdn | ~n1870); + assign n2176 = ~preset & n_n3896 & (pdn | ~n1870); + assign n2177 = ~preset & n_n4279 & (pdn | ~n1870); + assign n2178_1 = n2317 & n1878_1 & ~preset & n_n4362; + assign n2179 = n_n3988 & (~n1878_1 | ~n2317) & n2318; + assign n2180 = n1836 & (n_n3988 ? (~n1869 ^ ~n1914) : (n1869 ^ ~n1914)); + assign n2181 = ~preset & n_n3328 & (~ndn3_4 | ndn3_5); + assign n2182 = ~preset & n_n3761 & (pdn | ~n1870); + assign n2183_1 = n2317 & n1878_1 & ~preset & n_n3946; + assign n2184 = n_n3995 & (~n1878_1 | ~n2317) & n2318; + assign n2185 = n1836 & (n_n3995 ? (~n1860 ^ ~n1943_1) : (n1860 ^ ~n1943_1)); + assign n2186 = ~preset & n_n3128 & (pdn | ~n1870); + assign n2187 = n1988_1 & ~preset & n_n3919; + assign n2188_1 = n1988_1 & ~preset & n_n3886; + assign n2189 = ~preset & n_n3048 & (pdn | ~n1870); + assign n2190 = ~preset & n_n3061 & (pdn | ~n1870); + assign n2191 = ~preset & n_n3316 & (pdn | ~n1870); + assign n2192 = ~preset & n_n3906 & (pdn | ~n1870); + assign n2193_1 = ~preset & n_n3583 & (pdn | ~n1870); + assign n2194 = ~preset & n_n3358 & (pdn | ~n1870); + assign n2195 = ~preset & n_n4243 & (pdn | ~n1870); + assign n2196 = ~preset & n_n4337 & (~ndn3_6 | ndn3_7); + assign n2197 = ~preset & n_n3207 & (pdn | ~n1870); + assign n2198_1 = ~preset & n_n3465 & (pdn | ~n1870); + assign n2199 = n2348 & ((~pdn & ~n1870) | (ndn1_34 & (pdn | ~n1870))); + assign n2200 = ~preset & n_n3892 & (~ndn3_6 | ndn3_7); + assign n2201 = ~preset & n_n4383 & (~ndn3_5 | ndn3_6); + assign n2202 = ~preset & n_n4286 & (pdn | ~n1870); + assign n2203_1 = ~preset & n_n4189 & (pdn | ~n1870); + assign n2204 = ~preset & n_n3576 & (pdn | ~n1870); + assign n2205 = ~preset & n_n4172 & (pdn | ~n1870); + assign n2206 = ~preset & n_n3111 & (pdn | ~n1870); + assign n2207 = ~preset & n_n3035 & (~ndn3_8 | ndn3_9); + assign n2208_1 = ~preset & n_n3627 & (pdn | ~n1870); + assign n2209 = ~preset & n_n3044 & (pdn | ~n1870); + assign n2210 = ~preset & n_n3376 & (pdn | ~n1870); + assign n2211 = ~preset & n_n3118 & (pdn | ~n1870); + assign n2212 = ~preset & n_n3242 & (~nrq3_11 | ngfdn_3); + assign n2213_1 = n2038 & (n1920 ? (~n1921 ^ ~n1986) : (n1921 ^ ~n1986)); + assign n2214 = ngfdn_3 & n_n4122 & ~ndn3_15 & n_n3556; + assign n2215 = nen3_10 & ~ndn3_10 & n_n3919; + assign n2216 = n_n4145 & nrq3_11 & ~ngfdn_3; + assign n2217 = n_n4062 & ~ndn3_10 & nen3_10; + assign n2218_1 = n1939 & ((n1910 & n1911) | (n1909 & (n1910 | n1911))); + assign n2219 = n1918_1 & (n2221 | n2222 | n2223_1); + assign n2220 = nen3_10 & ~ndn3_10 & n_n3854; + assign n2221 = ngfdn_3 & n_n4157 & ~ndn3_15 & n_n3035; + assign n2222 = nen3_10 & n_n3511 & ~ndn3_10; + assign n2223_1 = n_n3898 & nrq3_11 & ~ngfdn_3; + assign n2224 = ngfdn_3 & n_n3170 & ~ndn3_15 & n_n3242; + assign n2225 = n_n3259 & ~ndn3_10 & nen3_10; + assign n2226 = n_n3841 & nrq3_11 & ~ngfdn_3; + assign n2227 = nen3_10 & ~ndn3_10 & n_n3451; + assign n2228_1 = ~preset & n_n3113 & (pdn | ~n1870); + assign n2229 = ~preset & n_n3173 & (pdn | ~n1870); + assign n2230 = ~preset & n_n3221 & (pdn | ~n1870); + assign n2231 = n2317 & n1878_1 & ~preset & n_n3876; + assign n2232 = n_n4040 & (~n1878_1 | ~n2317) & n2318; + assign n2233_1 = n1836 & (n_n4040 ? (~n1843_1 ^ ~n1913_1) : (n1843_1 ^ ~n1913_1)); + assign n2234 = ~preset & n_n3556 & (~ndn3_8 | ndn3_9); + assign n2235 = ~preset & n_n3733 & (pdn | ~n1870); + assign n2236 = ~preset & n_n3231 & (pdn | ~n1870); + assign n2237 = ~preset & n_n3313 & (pdn | ~n1870); + assign n2238_1 = ~preset & n_n3079 & (pdn | ~n1870); + assign n2239 = ~preset & n_n3688 & (~nrq3_11 | ngfdn_3); + assign n2240 = ~preset & n_n3344 & (pdn | ~n1870); + assign n2241 = ~preset & n_n4071 & (~ndn3_6 | ndn3_7); + assign n2242 = ~preset & n_n3012 & (pdn | ~n1870); + assign n2243_1 = ~preset & n_n4222 & (ndn3_10 | ~nen3_10); + assign n2244 = ~preset & n_n4160 & (~ndn3_5 | ndn3_6); + assign n2245 = ~preset & n_n3517 & (pdn | ~n1870); + assign n2246 = n_n3707 & (~n_n3709 | n1937 | ~n2331); + assign n2247 = ~preset & n_n3281 & (~ndn3_4 | ndn3_5); + assign n2248_1 = ~preset & n_n3764 & (pdn | ~n1870); + assign n2249 = ~preset & n_n3549 & (pdn | ~n1870); + assign n2250 = ~preset & n_n3876 & (~ndn3_7 | ndn3_8); + assign n2251 = ~preset & n_n3729 & (pdn | ~n1870); + assign n2252 = ~preset & n_n3525 & (pdn | ~n1870); + assign n2253_1 = ~preset & n_n3916 & (ndn3_10 | ~nen3_10); + assign n2254 = ~preset & n_n3495 & (ndn3_15 | ~ngfdn_3); + assign n2255 = ~preset & n_n4211 & (~ndn3_8 | ndn3_9); + assign n2256 = ~preset & n_n3670 & (pdn | ~n1870); + assign n2257 = ~n1900 & ~n1886 & ~preset & n_n4381; + assign n2258_1 = n_n3892 & (n1899 | n2259); + assign n2259 = ~n_n3493 & ~n1890 & (~n_n4045 | n2335); + assign n2260 = n1988_1 & ~preset & n_n3858; + assign n2261 = ~preset & n_n3270 & (pdn | ~n1870); + assign n2262 = ~preset & n_n4074 & (~nrq3_11 | ngfdn_3); + assign n2263_1 = ngfdn_3 & n_n3578 & ~ndn3_15 & n_n4074; + assign n2264 = nen3_10 & ~ndn3_10 & n_n3886; + assign n2265 = n_n3916 & nrq3_11 & ~ngfdn_3; + assign n2266 = n_n4021 & ~ndn3_10 & nen3_10; + assign n2267 = nen3_10 & n_n3281 & ~ndn3_10; + assign n2268_1 = nrq3_11 & ~ngfdn_3 & (n_n4229 ^ ~n1902); + assign n2269 = ngfdn_3 & n_n3250 & ~ndn3_15 & n_n3085; + assign n2270 = nen3_10 & ~ndn3_10 & n_n4294; + assign n2271 = n_n4229 & nrq3_11 & ~ngfdn_3; + assign n2272 = n1916 & ((n1906 & ~n1971) | (n1905 & (n1906 | ~n1971))); + assign n2273 = n1915 & (n2284 | n2327); + assign n2274 = ~preset & n_n3133 & (pdn | ~n1870); + assign n2275 = ~n1894 & (~n1969 | n2329); + assign n2276 = (~n_n4145 ^ ~n1895) & (~n_n4080 ^ n1907); + assign n2277 = ~preset & n_n4224 & (~ndn3_5 | ndn3_6); + assign n2278 = ~preset & n_n4392 & (ndn3_15 | ~ngfdn_3); + assign n2279 = n1988_1 & ~preset & n_n3511; + assign n2280 = ~preset & n_n3780 & (pdn | ~n1870); + assign n2281 = ~preset & n_n4349 & (~ndn3_6 | ndn3_7); + assign n2282 = ~preset & n_n4316 & (ndn3_10 | ~nen3_10); + assign n2283 = nen3_10 & ~ndn3_10 & n_n3978; + assign n2284 = n1877 & (n_n4316 ? (n1938_1 ^ ~n1959) : (~n1938_1 ^ ~n1959)); + assign n2285 = ngfdn_3 & n_n3657 & ~ndn3_15 & n_n4211; + assign n2286 = nen3_10 & n_n3858 & ~ndn3_10; + assign n2287 = n_n4316 & nrq3_11 & ~ngfdn_3; + assign n2288 = nrq3_11 & ~ngfdn_3 & (n_n4159 ^ n_n3976); + assign n2289 = ngfdn_3 & n_n3624 & ~ndn3_15 & n_n3688; + assign n2290 = n_n3878 & ~ndn3_10 & nen3_10; + assign n2291 = nrq3_11 & n_n3976 & ~ngfdn_3; + assign n2292 = nen3_10 & ~ndn3_10 & n_n3328; + assign n2293 = n1871 & nrq3_11 & ~ngfdn_3; + assign n2294 = n_n3099 & ngfdn_3 & n_n3936 & ~ndn3_15; + assign n2295 = n_n3208 & ~ndn3_10 & nen3_10; + assign n2296 = n_n4222 & nrq3_11 & ~ngfdn_3; + assign n2297 = ~preset & n_n3793 & (pdn | ~n1870); + assign n2298 = ~preset & n_n3497 & (pdn | ~n1870); + assign n2299 = ~preset & n_n3098 & (pdn | ~n1870); + assign n2300 = ~preset & n_n3687 & (pdn | ~n1870); + assign n2301 = ~preset & n_n3225 & (pdn | ~n1870); + assign n2302 = ~preset & n_n4258 & (~ndn3_7 | ndn3_8); + assign n2303 = n2317 & n1878_1 & ~preset & n_n4360; + assign n2304 = n_n3726 & (~n1878_1 | ~n2317) & n2318; + assign n2305 = n1836 & (n_n3726 ? (~n1857 ^ ~n1908_1) : (n1857 ^ ~n1908_1)); + assign n2306 = ~preset & n_n3008 & (pdn | ~n1870); + assign n2307 = n2317 & n1878_1 & ~preset & n_n3743; + assign n2308 = n_n3574 & (~n1878_1 | ~n2317) & n2318; + assign n2309 = n1836 & (n_n3574 ? (~n1871 ^ ~n1883_1) : (n1871 ^ ~n1883_1)); + assign n2310 = ~n_n4067 & (n_n4026 ? ~n_n3851 : ~n1953_1); + assign n2311 = ~preset & n_n3936 & (~ndn3_8 | ndn3_9); + assign n2312 = ~preset & n_n4142 & (pdn | ~n1870); + assign n2313 = ~n_n3756 & (~n_n4159 ^ ~n_n3976); + assign n2314 = ~n_n4182 & ~n_n4330; + assign n2315 = n1839 & ((~n_n4067 & ~n1849) | (n_n3833 & (n_n4067 | ~n1849))); + assign n2316 = nen3_10 & nsr3_17 & n_n4093; + assign n2317 = n1879 & ~n_n3709; + assign n2318 = ~preset & (n_n3198 | ~n_n3707 | ~n_n3709); + assign n2319 = n_n4157 & n_n3035; + assign n2320 = n_n4349 | n_n4071 | n_n3892 | n_n4337; + assign n2321 = n_n3968 | n_n3922 | n_n4201 | n_n3533; + assign n2322 = nsr3_14 & n_n4045 & ~nsr3_17; + assign n2323 = ~n_n3557 & n_n4057; + assign n2324 = n_n3624 & n_n3688; + assign n2325 = n2292 | (n_n4125 & n1890 & n1904); + assign n2326 = n2288 | (~ndn3_10 & nen3_10 & n_n3931); + assign n2327 = n2283 | (n_n3901 & n1890 & n1904); + assign n2328 = ~ndn3_4 & ~preset; + assign n2329 = (n_n4145 & ~n1895) | (~n_n4145 & n1895) | ((~n_n4145 ^ n1895) & (n_n4080 ^ n1907)); + assign n2330 = n1857 | n2276 | (~n1857 & (~n_n3726 ^ ~n1908_1)); + assign n2331 = n1919 & (n2275 | n2330); + assign n2332 = n_n3578 & n_n4074; + assign n2333 = n2267 | (n_n3769 & n1890 & n1904); + assign n2334 = n2266 | (n_n4047 & n1890 & n1904); + assign n2335 = nsr3_14 & ~nsr3_17; + assign n2336 = (n1898_1 & n1945) | (n_n4381 & n1989); + assign n2337 = n_n3493 & ~preset; + assign n2338 = n_n3170 & n_n3242; + assign n2339 = n_n3099 & n_n3936; + assign n2340 = n_n4026 | ~n_n3831 | (~n_n4026 & ~n1953_1); + assign n2341 = n_n3657 & n_n4211; + assign n2342 = n2227 | (n_n4324 & n1890 & n1904); + assign n2343 = n2220 | (n_n4366 & n1890 & n1904); + assign n2344 = n2217 | (n_n3475 & n1890 & n1904); + assign n2345 = n_n4122 & n_n3556; + assign n2346 = n_n3250 & n_n3085; + assign n2347 = nsr3_3 & ((n_n4108 & ~n_n3354) | (~tin_pready_0_0_ & (~n_n4108 | ~n_n3354))); + assign n2348 = n_n3354 & ~preset; + assign n2349 = n_n3766 & n_n4275; + assign n2350 = n_n3955 ? (n1989 | (~n_n3954 & n1898_1)) : (n_n3954 & n1898_1); + assign n2351 = nlak4_2 | (nlc3_3 & ~n_n4263); + assign n2352 = (n_n4052 & n1989) | n2148_1; + assign n2353 = n_n4099 ? ((n1898_1 & n1967) | n1989) : (n1898_1 & ~n1967); + assign n2354 = n1867 & n1836 & ~n_n4275 & n_n3766; + assign n2355 = ~n_n3954 & ~n_n3955; + assign n2356 = n2355 & ~n1949 & n1898_1 & ~n1948_1; + assign n2357 = n2356 & n1951 & ~n1917 & ~n1945; + assign n2358 = ~n_n4045 | preset | (~n1890 & n2335); + assign n2359 = n_n3707 & ~preset; + assign n2360 = n1890 & n_n4057; + assign n2361 = ~nsr3_14 | nsr3_17; + assign n2362 = ~n_n4045 | preset | (~n1890 & n2335); + assign n2363 = n_n3954 ? n1898_1 : n1989; + assign n2364 = ~preset & n_n4045 & (n1890 | ~n2335); + assign n2365 = (n1898_1 & n1948_1) | (n_n4029 & n1989); + assign n2366 = n_n3814 & n_n4227 & n_n3724 & ~n_n3766; + assign n2367 = n1879 & n_n3707; + assign n2368 = n1855 | preset | (n1880 & n2367); + assign n2369 = (n1898_1 & n1949) | (n_n3845 & n1989); + assign n2370 = n_n3865 ? ((n1891 & n1898_1) | n1989) : (~n1891 & n1898_1); + assign n2371 = n1887 & n1840; + assign n2372 = n2331 & ~n1937 & ~preset & n_n3709; + assign n2373 = n1849 & ~n_n4067; + assign n2374 = ~n2310 & n1903_1 & n_n4093 & ~n1897; + always @ (posedge clock) begin + n_n4142 <= n349; + n_n3936 <= n354; + n_n3574 <= n359; + n_n3008 <= n364; + n_n3726 <= n369; + n_n3604 <= n374; + n_n3144 <= n379; + n_n3782 <= n384; + n_n3067 <= n389; + n_n4258 <= n394; + n_n3225 <= n399; + n_n3180 <= n404; + n_n3274 <= n409; + n_n3475 <= n414; + n_n3687 <= n419; + n_n3381 <= n424; + n_n3098 <= n429; + n_n4108 <= n434; + n_n3497 <= n439; + n_n3793 <= n444; + n_n4316 <= n449; + n_n4349 <= n454; + n_n3029 <= n459; + n_n3619 <= n464; + n_n3264 <= n469; + n_n3780 <= n474; + ndn3_4 <= n479; + n_n4114 <= n484; + n_n3146 <= n489; + n_n3511 <= n494; + n_n3152 <= n499; + n_n3833 <= n504; + n_n4282 <= n509; + n_n3305 <= n514; + n_n4392 <= n519; + n_n4224 <= n524; + n_n3198 <= n529; + n_n3204 <= n534; + n_n3024 <= n539; + n_n4139 <= n544; + ndn3_15 <= n549; + n_n3133 <= n554; + n_n4074 <= n559; + n_n3270 <= n564; + n_n3858 <= n569; + n_n3456 <= n574; + n_n3521 <= n579; + n_n3081 <= n584; + n_n4381 <= n589; + n_n3670 <= n594; + n_n4211 <= n599; + n_n3493 <= n604; + n_n3495 <= n609; + n_n3916 <= n614; + n_n3195 <= n619; + n_n3525 <= n624; + n_n3729 <= n629; + n_n3876 <= n634; + ndn3_5 <= n639; + n_n3549 <= n644; + n_n3489 <= n649; + n_n3764 <= n654; + n_n3281 <= n659; + n_n3707 <= n664; + n_n3517 <= n669; + n_n4160 <= n674; + n_n4222 <= n679; + n_n3012 <= n684; + n_n4071 <= n689; + n_n3372 <= n694; + n_n3344 <= n699; + n_n3688 <= n704; + n_n3079 <= n709; + n_n3313 <= n714; + n_n3411 <= n719; + n_n3231 <= n724; + n_n3396 <= n729; + n_n3432 <= n734; + n_n3606 <= n739; + n_n3733 <= n744; + n_n3556 <= n749; + n_n4040 <= n754; + n_n3120 <= n759; + n_n3221 <= n764; + n_n3173 <= n769; + n_n3851 <= n774; + n_n3113 <= n779; + n_n3242 <= n784; + n_n3118 <= n789; + n_n3376 <= n794; + n_n4089 <= n799; + n_n3044 <= n804; + n_n3627 <= n809; + n_n3035 <= n814; + n_n3111 <= n819; + n_n3321 <= n824; + n_n3443 <= n829; + n_n3215 <= n834; + ndn3_10 <= n839; + n_n4172 <= n844; + nlc1_2 <= n849; + n_n3590 <= n854; + n_n4110 <= n859; + nlc3_3 <= n864; + n_n3576 <= n869; + n_n4129 <= n874; + n_n4189 <= n879; + n_n4286 <= n884; + n_n4383 <= n889; + pdn <= n894; + n_n3567 <= n898; + n_n3892 <= n903; + n_n3075 <= n908; + n_n3354 <= n913; + n_n3465 <= n918; + ndn3_6 <= n923; + n_n3617 <= n928; + n_n4162 <= n933; + n_n3207 <= n938; + n_n4120 <= n943; + n_n3065 <= n948; + n_n4005 <= n953; + n_n3266 <= n958; + n_n4337 <= n963; + n_n3600 <= n968; + n_n3415 <= n973; + n_n4243 <= n978; + n_n3872 <= n983; + n_n3648 <= n988; + n_n3358 <= n993; + n_n3350 <= n998; + ndn3_7 <= n1003; + n_n3116 <= n1008; + n_n3583 <= n1013; + n_n3906 <= n1018; + n_n4131 <= n1023; + n_n3316 <= n1028; + n_n3061 <= n1033; + n_n3048 <= n1038; + n_n3886 <= n1043; + n_n3919 <= n1048; + n_n3128 <= n1053; + n_n3995 <= n1058; + n_n4213 <= n1063; + n_n3761 <= n1068; + ndn3_8 <= n1073; + n_n3252 <= n1078; + n_n4366 <= n1083; + n_n3328 <= n1088; + n_n3988 <= n1093; + n_n3348 <= n1098; + n_n3544 <= n1103; + n_n3101 <= n1108; + n_n4279 <= n1113; + n_n3896 <= n1118; + n_n3736 <= n1123; + n_n4251 <= n1128; + n_n3650 <= n1133; + n_n3307 <= n1138; + n_n4294 <= n1143; + n_n4334 <= n1148; + n_n3955 <= n1153; + n_n4164 <= n1158; + n_n3155 <= n1163; + n_n3749 <= n1168; + n_n4233 <= n1173; + n_n4347 <= n1178; + n_n3826 <= n1183; + n_n3360 <= n1188; + n_n3458 <= n1193; + n_n3093 <= n1198; + n_n3157 <= n1203; + n_n3506 <= n1208; + n_n3161 <= n1213; + n_n3319 <= n1218; + n_n3429 <= n1223; + n_n3971 <= n1228; + n_n3449 <= n1233; + n_n4270 <= n1238; + n_n4288 <= n1243; + n_n3183 <= n1248; + n_n3130 <= n1253; + nlak4_2 <= n1258; + n_n4047 <= n1263; + n_n3978 <= n1268; + n_n3239 <= n1273; + n_n4145 <= n1278; + n_n3890 <= n1283; + n_n4003 <= n1288; + n_n3091 <= n1293; + n_n3985 <= n1298; + n_n3326 <= n1303; + n_n4052 <= n1308; + nsr4_2 <= n1313; + n_n4099 <= n1318; + n_n4375 <= n1323; + n_n4067 <= n1328; + n_n4290 <= n1333; + n_n3898 <= n1338; + n_n4122 <= n1343; + n_n3774 <= n1348; + n_n3014 <= n1353; + n_n4241 <= n1358; + n_n3952 <= n1363; + n_n3237 <= n1368; + n_n3968 <= n1373; + n_n3922 <= n1378; + n_n3551 <= n1383; + n_n3379 <= n1388; + n_n4275 <= n1393; + n_n3570 <= n1398; + n_n3854 <= n1403; + n_n4057 <= n1408; + n_n3451 <= n1413; + n_n4037 <= n1418; + n_n3408 <= n1423; + n_n4229 <= n1428; + n_n4201 <= n1433; + n_n3339 <= n1438; + n_n4362 <= n1443; + n_n3483 <= n1448; + n_n3557 <= n1453; + n_n4185 <= n1458; + n_n3069 <= n1463; + n_n3643 <= n1468; + n_n3404 <= n1473; + n_n3057 <= n1478; + n_n3020 <= n1483; + n_n3828 <= n1488; + n_n3631 <= n1493; + n_n3138 <= n1498; + nsr1_2 <= n1503; + n_n4065 <= n1508; + n_n3679 <= n1513; + n_n3287 <= n1518; + n_n4351 <= n1523; + n_n4059 <= n1528; + n_n3436 <= n1533; + nen3_10 <= n1538; + n_n3461 <= n1543; + n_n4012 <= n1548; + n_n3051 <= n1553; + n_n3073 <= n1558; + n_n3777 <= n1563; + n_n3709 <= n1568; + n_n3946 <= n1573; + n_n3085 <= n1578; + n_n3259 <= n1583; + n_n3504 <= n1588; + n_n4045 <= n1593; + n_n3954 <= n1598; + n_n3136 <= n1603; + n_n4372 <= n1608; + n_n4236 <= n1613; + n_n3040 <= n1618; + n_n3874 <= n1623; + n_n3999 <= n1628; + n_n3223 <= n1633; + ndn1_34 <= n1638; + n_n3743 <= n1643; + n_n3657 <= n1648; + n_n3213 <= n1653; + n_n3095 <= n1658; + n_n3663 <= n1663; + n_n3724 <= n1668; + n_n3038 <= n1673; + n_n3370 <= n1678; + n_n3624 <= n1683; + n_n3578 <= n1688; + n_n3713 <= n1693; + n_n3089 <= n1698; + n_n3211 <= n1703; + n_n3367 <= n1708; + n_n3434 <= n1713; + n_n3126 <= n1718; + n_n4192 <= n1723; + n_n4136 <= n1728; + n_n3053 <= n1733; + n_n3938 <= n1738; + n_n3769 <= n1743; + n_n4390 <= n1748; + nsr3_17 <= n1753; + n_n3903 <= n1758; + n_n3658 <= n1763; + nrq3_11 <= n1768; + n_n3818 <= n1773; + n_n3533 <= n1778; + n_n3463 <= n1783; + n_n3175 <= n1788; + n_n3055 <= n1793; + n_n3202 <= n1798; + n_n3385 <= n1803; + n_n4077 <= n1808; + n_n3142 <= n1813; + n_n3901 <= n1818; + n_n3934 <= n1823; + n_n3823 <= n1828; + n_n3722 <= n1833; + n_n4309 <= n1838; + n_n4159 <= n1843; + n_n4330 <= n1848; + n_n3836 <= n1853; + n_n3470 <= n1858; + n_n3331 <= n1863; + n_n3883 <= n1868; + n_n4299 <= n1873; + n_n4157 <= n1878; + ndn3_9 <= n1883; + n_n3208 <= n1888; + n_n3190 <= n1893; + n_n4029 <= n1898; + n_n3042 <= n1903; + nsr3_14 <= n1908; + n_n4151 <= n1913; + n_n3188 <= n1918; + n_n4303 <= n1923; + n_n3250 <= n1928; + n_n3170 <= n1933; + n_n3758 <= n1938; + n_n3910 <= n1943; + n_n3108 <= n1948; + n_n3150 <= n1953; + n_n4320 <= n1958; + n_n4360 <= n1963; + n_n4247 <= n1968; + n_n4199 <= n1973; + n_n3966 <= n1978; + n_n3766 <= n1983; + n_n4021 <= n1988; + n_n4062 <= n1993; + n_n3514 <= n1998; + n_n3572 <= n2003; + n_n4166 <= n2008; + n_n3976 <= n2013; + n_n3394 <= n2018; + n_n4095 <= n2023; + n_n3863 <= n2028; + n_n3720 <= n2033; + ngfdn_3 <= n2038; + n_n3756 <= n2043; + n_n3667 <= n2048; + n_n3342 <= n2053; + n_n3529 <= n2058; + n_n4209 <= n2063; + n_n4324 <= n2068; + n_n3337 <= n2073; + n_n4227 <= n2078; + n_n4153 <= n2083; + n_n3831 <= n2088; + n_n3233 <= n2093; + n_n4263 <= n2098; + n_n3413 <= n2103; + n_n4182 <= n2108; + n_n3841 <= n2113; + n_n3441 <= n2118; + n_n4026 <= n2123; + n_n4342 <= n2128; + n_n4102 <= n2133; + n_n3277 <= n2138; + n_n4180 <= n2143; + n_n3878 <= n2148; + n_n3931 <= n2153; + n_n3845 <= n2158; + n_n3865 <= n2163; + n_n3486 <= n2168; + n_n4056 <= n2173; + n_n3674 <= n2178; + n_n3959 <= n2183; + n_n3608 <= n2188; + n_n4080 <= n2193; + n_n4018 <= n2198; + n_n4354 <= n2203; + n_n3797 <= n2208; + n_n3739 <= n2213; + n_n3646 <= n2218; + n_n3099 <= n2223; + n_n3537 <= n2228; + n_n3806 <= n2233; + n_n3087 <= n2238; + n_n4105 <= n2243; + n_n3262 <= n2248; + n_n4125 <= n2253; + n_n3814 <= n2258; + n_n4093 <= n2263; + nsr3_3 <= n2268; + end +endmodule + + diff --git a/openfpga_flow/docs/KeyExampleTasks.txt b/openfpga_flow/docs/KeyExampleTasks.txt new file mode 100644 index 000000000..9f5f70b68 --- /dev/null +++ b/openfpga_flow/docs/KeyExampleTasks.txt @@ -0,0 +1,26 @@ +************************************************************************************************** +* Example VTR experiments complete with scripts, benchmarks, architectures, and expected results +************************************************************************************************** + +Starting out: + + basic_flow - Run the whole VTR flow to map a simple Verilog circuit to an FPGA architecture + +Advanced (Flagshp experiment): + + timing - Run the flagship VTR benchmarks on our comprehensive, realistic architecture file + + timing_chain - Same as above but this time with carry chains + +Legacy: + + regression_mcnc - Run VTR on the historical MCNC benchmarks on a legacy architecture file + (Note: This is only useful for comparing to the past, it is not realistic in the modern world) + + +Custom, unique logic blocks: + + regression_titan\titan_small - Simplified Altera Stratix IV (commercial FPGA) architecture capture + + regression_fpu_hard_block_arch - Custom hard FPU logic block architecture + diff --git a/openfpga_flow/misc/fpga_flow_script.conf b/openfpga_flow/misc/fpga_flow_script.conf new file mode 100644 index 000000000..3fd8c26db --- /dev/null +++ b/openfpga_flow/misc/fpga_flow_script.conf @@ -0,0 +1,31 @@ +# Standard Configuration Example +[dir_path] +script_base = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/ +benchmark_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Verilog/MCNC/ +yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys +odin2_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/odin2.exe +cirkit_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/cirkit +abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc +abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc +abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc +mpack1_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/mpack1 +m2net_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/m2net +mpack2_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/mpack2 +vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr +rpt_dir = /var/tmp/Openfpga/results +ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace + +[flow_conf] +#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr +flow_type = yosys_vpr +vpr_arch = ${PATH:OPENFPGA_PATH}/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +mpack1_abc_stdlib = Not_Required +m2net_conf = Not_Required +mpack2_arch = Not_Required +power_tech_xml = ${PATH:OPENFPGA_PATH}/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml + +[csv_tags] +mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf: +mpack2_tags = BLE Number: | BLE Fill Rate: +vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles: +vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff diff --git a/openfpga_flow/misc/fpga_flow_template.sh b/openfpga_flow/misc/fpga_flow_template.sh new file mode 100644 index 000000000..473e117b9 --- /dev/null +++ b/openfpga_flow/misc/fpga_flow_template.sh @@ -0,0 +1,38 @@ +#!/bin/bash + +# ========================================================================== +# Note: This shell script is parsed using python3 string templating system +# For correct parsing, please use $$ symbol in place of single \dollar sign +# variables can be declared using \dollar var_name +# Ref : https://docs.python.org/3/library/string.html#template-strings +# ========================================================================== +VTR_RUNTIME_ESTIMATE_SECONDS=1.70 +VTR_MEMORY_ESTIMATE_BYTES=0 + +VTR_RUNTIME_ESTIMATE_HUMAN_READABLE="2 seconds" +VTR_MEMORY_ESTIMATE_HUMAN_READABLE="0.00 MiB" + +#We redirect all command output to both stdout and the log file with 'tee'. + +#Begin I/O redirection +{ + + ${fpga_flow_script} \ + -conf ${conf_file} \ + -benchmark ${benchmark_list_file} \ + -rpt ${csv_rpt_file} \ + -vpr_fpga_verilog_dir ${verilog_output_path} \ + ${additional_params} + + #The IO redirection occurs in a sub-shell, + #so we need to exit it with the correct code + exit $$? + +} |& tee vtr_flow.out +#End I/O redirection + +#We used a pipe to redirect IO. +#To get the correct exit status we need to exit with the +#status of the first element in the pipeline (i.e. the real +#command run above) +exit $${PIPESTATUS[0]} diff --git a/openfpga_flow/misc/openfpga_benchmark_list.txt b/openfpga_flow/misc/openfpga_benchmark_list.txt new file mode 100644 index 000000000..3cf447f5a --- /dev/null +++ b/openfpga_flow/misc/openfpga_benchmark_list.txt @@ -0,0 +1,6 @@ +# Circuit Names, fixed routing channel width, +# PID/*.v, 120 +# up_counter/*.v, 30 +# MultiBitAdder/*.v, 30 +# i2c_master_top/*.v, 40 +asynch_fifo/*.v, 30 \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_task.conf b/openfpga_flow/scripts/run_fpga_task.conf new file mode 100644 index 000000000..bb4bc24f1 --- /dev/null +++ b/openfpga_flow/scripts/run_fpga_task.conf @@ -0,0 +1,9 @@ +[GENERAL CONFIGURATION] +task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks +circuits_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Verilog/MCNC/ +archs_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/arch +misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc +script_default=${PATH:OPENFPGA_PATH}/fpga_flow/scripts/fpga_flow.pl +csv_rpt_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/csv_rpt/ +verilog_output_path=${PATH:OPENFPGA_PATH}/openfpga_flow/verilog_op/ +temp_run_dir=${PATH:OPENFPGA_PATH} \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py new file mode 100644 index 000000000..e9c1eb948 --- /dev/null +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -0,0 +1,219 @@ +import os +import shutil +import time +import shlex +import argparse +from configparser import ConfigParser, ExtendedInterpolation +import logging +import glob +import subprocess +import threading +from string import Template + +# # Configure logging system +logging.basicConfig(level=logging.INFO, + format='%(levelname)s (%(threadName)-9s) - %(message)s') +logger = logging.getLogger('OpenFPGA_Task_logs') + +# # Reading command line arguments +parser = argparse.ArgumentParser() +parser.add_argument('tasks', nargs='+') +parser.add_argument('--maxthreads', + type=int, + default=2, + help="Number of fpga_flow threads to run " + + "default = 2, Typically <= Number of processors on the system") +parser.add_argument('--config', help="script configuration file") +args = parser.parse_args() + +# # Reading configuration file to get all the paths +# # Replace variables in the file with absolute paths +task_script_dir = os.path.dirname(os.path.abspath(__file__)) +script_env_vars = ({"PATH": { + "OPENFPGA_FLOW_PATH": task_script_dir, + "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir)) +}}) + +config = ConfigParser(interpolation=ExtendedInterpolation()) +config.read_dict(script_env_vars) +config.read_file(open(os.path.join(task_script_dir, 'run_fpga_task.conf'))) +gc = config["GENERAL CONFIGURATION"] + + +def main(): + # processors = os.cpu_count() + task_action = [] + for eachtask in args.tasks: + logger.info("Currently running task %s" % eachtask) + task_action += generate_single_task_actions(eachtask) + run_actions(task_action) + logger.info("Task execution completed") + exit() +# ================================= +# # Subroutines start here +# ================================= + + +def clean_up_and_exit(msg): + logger.error(msg) + logger.error("Existing . . . . . .") + exit() + + +def generate_single_task_actions(taskname): + """ + This script generates all the scripts required for each benchmark + """ + curr_task_dir = os.path.join(gc["task_dir"], taskname) + if not os.path.isdir(curr_task_dir): + clean_up_and_exit("Task directory not found") + os.chdir(curr_task_dir) + + curr_task_conf_file = os.path.join(curr_task_dir, "config", "task.conf") + if not os.path.isfile(curr_task_conf_file): + clean_up_and_exit( + "Missing configuration file for task %s" % curr_task_dir) + + task_conf = ConfigParser(allow_no_value=True, + interpolation=ExtendedInterpolation()) + task_conf.optionxform = str + task_conf.read_dict(script_env_vars) + task_conf.read_file(open(curr_task_conf_file)) + # Check required sections in config file + required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"] + missing_section = list(set(required_sec)-set(task_conf.sections())) + if missing_section: + clean_up_and_exit( + "Missing section %s in task configuration file" % " ".join(missing_section)) + + benchmark_list = [] + for _, bench_file in task_conf["BENCHMARKS"].items(): + if(glob.glob(bench_file)): + benchmark_list.append(bench_file) + else: + logger.warning( + "File Not Found: Skipping %s benchmark " % bench_file) + + # Check if all benchmark/architecture files exits + archfile_list = [] + for _, arch_file in task_conf["ARCHITECTURES"].items(): + arch_full_path = arch_file + if os.path.isfile(arch_full_path): + archfile_list.append(arch_full_path) + else: + logger.warning( + "File Not Found: Skipping %s architecture " % arch_file) + + script_list = [] + for eacharch in archfile_list: + script_list.append(create_run_script(gc["temp_run_dir"], + eacharch, + benchmark_list, + task_conf["GENERAL"]["power_tech_file"], + task_conf["SCRIPT_PARAM"])) + return script_list + + +def create_run_script(task_run_dir, archfile, benchmark_list, power_tech_file, additional_fpga_flow_params): + """ + Create_run_script function accespts run directory, architecture list and + fpga_flow configuration file and prepare final executable fpga_flow script + TODO : Replace this section after convert fpga_flow to python script + Config file creation and bechnmark list can be skipped + """ + # = = = = = = = = = File/Directory Consitancy Check = = = = = = = = = = + if not os.path.isdir(gc["misc_dir"]): + clean_up_and_exit("Miscellaneous directory does not exist") + + fpga_flow_script = os.path.join(gc["misc_dir"], "fpga_flow_template.sh") + if not os.path.isfile(fpga_flow_script): + clean_up_and_exit("Missing fpga_flow script template %s" % + fpga_flow_script) + + fpga_flow_conf_tmpl = os.path.join(gc["misc_dir"], "fpga_flow_script.conf") + if not os.path.isfile(fpga_flow_conf_tmpl): + clean_up_and_exit("fpga_flow configuration tempalte is missing %s" % + fpga_flow_conf_tmpl) + + # = = = = = = = = = = = = Create execution folder = = = = = = = = = = = = + # TODO : this directory should change as //{conf_opt} + curr_job_dir = os.path.join(task_run_dir, "tmp") + if os.path.isdir(curr_job_dir): + shutil.rmtree(curr_job_dir) + os.makedirs(curr_job_dir) + os.chdir(curr_job_dir) + + # = = = = = = = = = = = Create config file= = = = = = = = = = = = = = = = + fpga_flow_conf = ConfigParser( + strict=False, + interpolation=ExtendedInterpolation()) + fpga_flow_conf.read_dict(script_env_vars) + fpga_flow_conf.read_file(open(fpga_flow_conf_tmpl)) + + # HACK: Find better way to resolve all interpolations in the script and write back + for eachSection in fpga_flow_conf: + for eachkey in fpga_flow_conf[eachSection].keys(): + fpga_flow_conf[eachSection][eachkey] = fpga_flow_conf.get( + eachSection, eachkey) + + # Update configuration file with script realated parameters + fpga_flow_conf["flow_conf"]["vpr_arch"] = archfile + fpga_flow_conf["flow_conf"]["power_tech_xml"] = power_tech_file + + # Remove extra path section and create configuration file + fpga_flow_conf.remove_section("PATH") + with open("openfpga_job.conf", 'w') as configfile: + fpga_flow_conf.write(configfile) + + # = = = = = = = = = = = Create Benchmark List file = = = = = = = = = = = = + # TODO: This script strips common path from bechmark list and add + # only single directory and filename to benchmarklist file + # This can be imporoved by modifying fpga_flow script + with open("openfpga_benchmark_list.txt", 'w') as configfile: + configfile.write("# Circuit Names, fixed routing channel width\n") + for eachBenchMark in benchmark_list: + configfile.write(eachBenchMark.replace( + fpga_flow_conf["dir_path"]["benchmark_dir"], "")) + configfile.write(",30") + configfile.write("\n") + + # = = = = = = = = = Create fpga_flow_shell Script = = = = = = = = = = = = + d = { + "fpga_flow_script": shlex.quote(gc["script_default"]), + "conf_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_job.conf")), + "benchmark_list_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_benchmark_list.txt")), + "csv_rpt_file": shlex.quote(os.path.join(os.getcwd(), os.path.join(gc["csv_rpt_dir"], "fpga_flow.csv"))), + "verilog_output_path": shlex.quote(os.path.join(os.getcwd(), gc["verilog_output_path"])), + "additional_params": " \\\n ".join(["-%s %s" % (key, value or "") for key, value in additional_fpga_flow_params.items()]) + } + result = Template(open(fpga_flow_script).read()).substitute(d) + fpga_flow_script_path = os.path.join(os.getcwd(), "openfpga_flow.sh") + with open(fpga_flow_script_path, 'w') as configfile: + configfile.write(result) + return fpga_flow_script_path + + +def run_single_script(s, script_path): + logging.debug('Waiting to join the pool') + with s: + name = threading.currentThread().getName() + subprocess.run(["bash", script_path], stdout=subprocess.PIPE) + logging.info("%s Finished " % name) + + +def run_actions(actions): + thread_sema = threading.Semaphore(args.maxthreads) + thred_list = [] + for index, eachAction in enumerate(actions): + t = threading.Thread(target=run_single_script, + name='benchmark_' + str(index), + args=(thread_sema, eachAction)) + t.start() + thred_list.append(t) + + for eachthread in thred_list: + eachthread.join() + + +if __name__ == "__main__": + main() diff --git a/openfpga_flow/tasks/basic_flow/config/golden_results.txt b/openfpga_flow/tasks/basic_flow/config/golden_results.txt new file mode 100644 index 000000000..edde206c7 --- /dev/null +++ b/openfpga_flow/tasks/basic_flow/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1 diff --git a/openfpga_flow/tasks/basic_flow/config/task.conf b/openfpga_flow/tasks/basic_flow/config/task.conf new file mode 100644 index 000000000..c21b6dfb5 --- /dev/null +++ b/openfpga_flow/tasks/basic_flow/config/task.conf @@ -0,0 +1,54 @@ +############################################## +# Configuration file for running experiments +############################################## +[GENERAL] +# General Parameters for the script +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +# [Optional] Timeout for each fpga_flow script run in seconds +# Default = 20 min +timeout_each_job = 20*60 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/*.v + +[SYNTHESIS_PARAM] +# TODO: Not Implemented yet +# This section lists parameters required for yosys synthesis +# Need to update fpga_flow.pl script +bench_yosys_common=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys +bench0_top = memory_controller +bench0_yosys=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys + +[SCRIPT_PARAM] +# Currently these parameters are transfered to fpga_flow script +# but differeent combinations of parameters can be saved in the file and +# linked here as s file Example: -Default -Calculate_Power -GenerateSpice +N = 10 +K = 6 +ace_d = 0.5 +multi_thread = 1 +route_chan_width = 30 +vpr_fpga_x2p_rename_illegal_port = +vpr_fpga_verilog = +vpr_fpga_bitstream_generator = +vpr_fpga_verilog_print_autocheck_top_testbench = +vpr_fpga_verilog_include_timing = +vpr_fpga_verilog_include_signal_init = +vpr_fpga_verilog_formal_verification_top_netlist = +fix_route_chan_width = +power = +remove_designs = +vpr_fpga_spice_print_component_tb = +vpr_fpga_spice = spice_taskfile +vpr_fpga_spice_simulator_path = /uusoc/facility/cad_tools/Synopsys/lnis_tools/hspice/P2019 =.06/hspice/bin/ + +[POST_RUN] +# Not Implemented yet +# Parse info and how to parse +parse_file=vpr_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt diff --git a/openfpga_flow/tasks/basic_flow/latest b/openfpga_flow/tasks/basic_flow/latest new file mode 100644 index 000000000..d43b654a7 --- /dev/null +++ b/openfpga_flow/tasks/basic_flow/latest @@ -0,0 +1,5 @@ +XSym +0006 +de6ba653dd63797278d7fa829999bf6c +run003 + \ No newline at end of file diff --git a/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml b/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml new file mode 100644 index 000000000..5f577afb6 --- /dev/null +++ b/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml @@ -0,0 +1,7493 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 6b5ac2e1ef9a1a6cd29bbcb7d17721e3a64e1bb9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2019 12:45:03 -0600 Subject: [PATCH 036/482] add timing graph builder for circuit models --- .../fpga_spice_include/circuit_library.cpp | 166 +++++++++++++++++- .../SRC/fpga_spice_include/circuit_library.h | 19 +- 2 files changed, 178 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index b552ebd2b..132186cfe 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -33,6 +33,7 @@ * +-------------------------------------+ ***********************************************************************/ +#include #include #include "vtr_assert.h" @@ -58,6 +59,49 @@ CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& c return vtr::make_range(port_ids_[circuit_model_id].begin(), port_ids_[circuit_model_id].end()); } +/* Create a vector for all the ports whose directionality is input + * This includes all the ports other than whose types are OUPUT or INOUT + */ +std::vector CircuitLibrary::input_ports(const CircuitModelId& circuit_model_id) const { + std::vector input_ports; + for (const auto& port_id : ports(circuit_model_id)) { + /* We skip output ports */ + if ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, port_id)) + || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, port_id)) ) { + continue; + } + input_ports.push_back(port_id); + } + return input_ports; +} + +/* Create a vector for all the ports whose directionality is output + * This includes all the ports whose types are OUPUT or INOUT + */ +std::vector CircuitLibrary::output_ports(const CircuitModelId& circuit_model_id) const { + std::vector output_ports; + for (const auto& port_id : ports(circuit_model_id)) { + /* We skip output ports */ + if ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, port_id)) + && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, port_id)) ) { + continue; + } + output_ports.push_back(port_id); + } + return output_ports; +} + +/* Create a vector for the pin indices, which is bounded by the size of a port + * Start from 0 and end to port_size - 1 + */ +std::vector CircuitLibrary::pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + std::vector pin_range(port_size(circuit_model_id, circuit_port_id)); + /* Create a vector, with sequentially increasing numbers */ + std::iota(pin_range.begin(), pin_range.end(), 0); + return pin_range; +} + + /************************************************************************ * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ @@ -356,9 +400,9 @@ CircuitModelId CircuitLibrary::add_circuit_model() { edge_ids_.emplace_back(); port_in_edge_ids_.emplace_back(); port_out_edge_ids_.emplace_back(); - edge_src_ports_.emplace_back(); + edge_src_port_ids_.emplace_back(); edge_src_pin_ids_.emplace_back(); - edge_sink_ports_.emplace_back(); + edge_sink_port_ids_.emplace_back(); edge_sink_pin_ids_.emplace_back(); edge_trise_.emplace_back(); edge_tfall_.emplace_back(); @@ -594,6 +638,10 @@ CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circu port_lut_output_masks_[circuit_model_id].emplace_back(); port_sram_orgz_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); + /* For timing graphs */ + port_in_edge_ids_[circuit_model_id].emplace_back(); + port_out_edge_ids_[circuit_model_id].emplace_back(); + return circuit_port_id; } @@ -1229,6 +1277,25 @@ void CircuitLibrary::build_circuit_model_links() { /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { + /* Now we start allocating a timing graph + * Add outgoing edges for each input pin of the circuit model + */ + for (auto& from_port_id : input_ports(circuit_model_id)) { + /* Add edges for each input pin */ + for (auto& from_pin_id : pins(circuit_model_id, from_port_id)) { + /* We should walk through output pins here */ + for (auto& to_port_id : output_ports(circuit_model_id)) { + for (auto& to_pin_id : pins(circuit_model_id, to_port_id)) { + /* Skip self-loops */ + if (from_port_id == to_port_id) { + continue; + } + /* Add an edge to bridge the from_pin_id and to_pin_id */ + add_edge(circuit_model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); + } + } + } + } return; } @@ -1236,11 +1303,77 @@ void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circ void CircuitLibrary::build_timing_graphs() { /* Walk through each circuit model, build timing graph one by one */ for (auto& circuit_model_id : circuit_models()) { + /* Free the timing graph if it already exists, we will rebuild one */ + invalidate_circuit_model_timing_graph(circuit_model_id); build_circuit_model_timing_graph(circuit_model_id); + /* Annotate timing information */ } return; } +/************************************************************************ + * Internal mutators: build timing graphs + ***********************************************************************/ +/* Add an edge between two pins of two ports, and assign an default timing value */ +void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, + const CircuitPortId& from_port, const size_t& from_pin, + const CircuitPortId& to_port, const size_t& to_pin) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + + /* Create an edge in the edge id list */ + CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[circuit_model_id].size()); + /* Expand the edge list */ + edge_ids_[circuit_model_id].push_back(edge_id); + + /* Initialize other attributes */ + + /* Update the list of incoming edges for to_port */ + /* Resize upon need */ + if (to_pin >= port_in_edge_ids_[circuit_model_id][to_port].size()) { + port_in_edge_ids_[circuit_model_id][to_port].resize(to_pin + 1); + } + port_in_edge_ids_[circuit_model_id][to_port][to_pin] = edge_id; + + /* Update the list of outgoing edges for from_port */ + /* Resize upon need */ + if (from_pin >= port_out_edge_ids_[circuit_model_id][from_port].size()) { + port_out_edge_ids_[circuit_model_id][from_port].resize(from_pin + 1); + } + port_out_edge_ids_[circuit_model_id][from_port][from_pin] = edge_id; + + /* Update source ports and pins of the edge */ + edge_src_port_ids_[circuit_model_id].push_back(from_port); + edge_src_pin_ids_[circuit_model_id].push_back(from_pin); + + /* Update sink ports and pins of the edge */ + edge_sink_port_ids_[circuit_model_id].push_back(to_port); + edge_sink_pin_ids_[circuit_model_id].push_back(to_pin); + + /* Give a default value for timing values */ + edge_trise_[circuit_model_id].push_back(0); + edge_tfall_[circuit_model_id].push_back(0); + + return; +} + +void CircuitLibrary::set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise) { + /* validate the circuit_edge_id */ + VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); + + edge_trise_[circuit_model_id][circuit_edge_id] = trise; + return; +} + +void CircuitLibrary::set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall) { + /* validate the circuit_edge_id */ + VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); + + edge_tfall_[circuit_model_id][circuit_edge_id] = tfall; + return; +} + + /************************************************************************ * Internal mutators: build fast look-ups ***********************************************************************/ @@ -1290,7 +1423,6 @@ void CircuitLibrary::build_circuit_model_port_lookup(const CircuitModelId& circu return; } - /************************************************************************ * Internal invalidators/validators ***********************************************************************/ @@ -1311,6 +1443,12 @@ bool CircuitLibrary::valid_delay_type(const CircuitModelId& circuit_model_id, co return ( size_t(delay_type) < delay_types_[circuit_model_id].size() ) && ( delay_type == delay_types_[circuit_model_id][size_t(delay_type)] ); } +bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + return ( size_t(circuit_edge_id) < edge_ids_[circuit_model_id].size() ) && ( circuit_edge_id == edge_ids_[circuit_model_id][circuit_edge_id] ); +} + /* Invalidators */ /* Empty fast lookup for circuit_models*/ void CircuitLibrary::invalidate_circuit_model_lookup() const { @@ -1326,6 +1464,28 @@ void CircuitLibrary::invalidate_circuit_model_port_lookup(const CircuitModelId& return; } +/* Clear all the data structure related to the timing graph */ +void CircuitLibrary::invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + edge_ids_[circuit_model_id].clear(); + + for (const auto& port_id : ports(circuit_model_id)) { + port_in_edge_ids_[circuit_model_id][port_id].clear(); + port_out_edge_ids_[circuit_model_id][port_id].clear(); + } + + edge_src_port_ids_[circuit_model_id].clear(); + edge_src_pin_ids_[circuit_model_id].clear(); + + edge_sink_port_ids_[circuit_model_id].clear(); + edge_sink_pin_ids_[circuit_model_id].clear(); + + edge_trise_[circuit_model_id].clear(); + edge_tfall_[circuit_model_id].clear(); + return; +} + /************************************************************************ * End of file : circuit_library.cpp ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 612e99ff1..04c220876 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -217,8 +217,12 @@ class CircuitLibrary { }; public: /* Constructors */ public: /* Accessors: aggregates */ - public: /* Public Accessors: Basic data query on Circuit Models*/ circuit_model_range circuit_models() const; + circuit_port_range ports(const CircuitModelId& circuit_model_id) const; + std::vector input_ports(const CircuitModelId& circuit_model_id) const; + std::vector output_ports(const CircuitModelId& circuit_model_id) const; + std::vector pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + public: /* Public Accessors: Basic data query on Circuit Models*/ enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; std::string circuit_model_name(const CircuitModelId& circuit_model_id) const; std::string circuit_model_prefix(const CircuitModelId& circuit_model_id) const; @@ -233,7 +237,6 @@ class CircuitLibrary { bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ - circuit_port_range ports(const CircuitModelId& circuit_model_id) const; size_t num_ports(const CircuitModelId& circuit_model_id) const; enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -419,6 +422,12 @@ class CircuitLibrary { void build_circuit_model_links(); void build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); void build_timing_graphs(); + public: /* Internal mutators: build timing graphs */ + void add_edge(const CircuitModelId& circuit_model_id, + const CircuitPortId& from_port, const size_t& from_pin, + const CircuitPortId& to_port, const size_t& to_pin); + void set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise); + void set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall); public: /* Internal mutators: build fast look-ups */ void build_circuit_model_lookup(); void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); @@ -427,9 +436,11 @@ class CircuitLibrary { bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; + bool valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const; /* Invalidators */ void invalidate_circuit_model_lookup() const; void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; + void invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); private: /* Internal data */ /* Fundamental information */ vtr::vector circuit_model_ids_; @@ -494,9 +505,9 @@ class CircuitLibrary { vtr::vector> edge_ids_; vtr::vector>> port_in_edge_ids_; vtr::vector>> port_out_edge_ids_; - vtr::vector> edge_src_ports_; + vtr::vector> edge_src_port_ids_; vtr::vector> edge_src_pin_ids_; - vtr::vector> edge_sink_ports_; + vtr::vector> edge_sink_port_ids_; vtr::vector> edge_sink_pin_ids_; vtr::vector> edge_trise_; vtr::vector> edge_tfall_; From 3d7adb3dd974a0a1a0c17a25f8b59e3bb66682f8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2019 15:52:28 -0600 Subject: [PATCH 037/482] start developing parsers for delay values --- .../fpga_spice_include/circuit_library.cpp | 131 ++++++++++++++++-- .../SRC/fpga_spice_include/circuit_library.h | 11 +- 2 files changed, 125 insertions(+), 17 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 132186cfe..dd7862c3c 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -66,8 +66,7 @@ std::vector CircuitLibrary::input_ports(const CircuitModelId& cir std::vector input_ports; for (const auto& port_id : ports(circuit_model_id)) { /* We skip output ports */ - if ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, port_id)) - || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, port_id)) ) { + if ( false == is_input_port(circuit_model_id, port_id) ) { continue; } input_ports.push_back(port_id); @@ -81,12 +80,11 @@ std::vector CircuitLibrary::input_ports(const CircuitModelId& cir std::vector CircuitLibrary::output_ports(const CircuitModelId& circuit_model_id) const { std::vector output_ports; for (const auto& port_id : ports(circuit_model_id)) { - /* We skip output ports */ - if ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, port_id)) - && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, port_id)) ) { + /* We skip input ports */ + if ( false == is_output_port(circuit_model_id, port_id) ) { continue; } - output_ports.push_back(port_id); + output_ports.push_back(port_id); } return output_ports; } @@ -201,9 +199,47 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ /************************************************************************ * Public Accessors : Basic data query on Circuit Porst ***********************************************************************/ + +/* identify if this port is an input port */ +bool CircuitLibrary::is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + /* validate the circuit_model_id and circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ + return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, circuit_port_id)) + && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, circuit_port_id)) ); +} + +/* identify if this port is an output port */ +bool CircuitLibrary::is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + /* validate the circuit_model_id and circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ + return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, circuit_port_id)) + || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, circuit_port_id)) ); +} + +/* Given a name and return the port id */ +CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const std::string& name) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Walk through the ports and try to find a matched name */ + CircuitPortId ret = CIRCUIT_PORT_OPEN_ID; + size_t num_found = 0; + for (auto port_id : ports(circuit_model_id)) { + if (0 != name.compare(port_prefix(circuit_model_id, port_id))) { + continue; /* Not the one, go to the next*/ + } + ret = port_id; /* Find one */ + num_found++; + } + /* Make sure we will not find two ports with the same name */ + VTR_ASSERT_SAFE( (0 == num_found) || (1 == num_found) ); + return ret; +} + /* Access the type of a port of a circuit model */ size_t CircuitLibrary::num_ports(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_port_id */ + /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); return port_ids_[circuit_model_id].size(); } @@ -404,8 +440,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() { edge_src_pin_ids_.emplace_back(); edge_sink_port_ids_.emplace_back(); edge_sink_pin_ids_.emplace_back(); - edge_trise_.emplace_back(); - edge_tfall_.emplace_back(); + edge_timing_info_.emplace_back(); /* Delay information */ delay_types_.emplace_back(); @@ -1307,6 +1342,7 @@ void CircuitLibrary::build_timing_graphs() { invalidate_circuit_model_timing_graph(circuit_model_id); build_circuit_model_timing_graph(circuit_model_id); /* Annotate timing information */ + set_timing_graph_delays(circuit_model_id); } return; } @@ -1351,8 +1387,8 @@ void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, edge_sink_pin_ids_[circuit_model_id].push_back(to_pin); /* Give a default value for timing values */ - edge_trise_[circuit_model_id].push_back(0); - edge_tfall_[circuit_model_id].push_back(0); + std::vector timing_info(2, 0); + edge_timing_info_[circuit_model_id].emplace_back(timing_info); return; } @@ -1361,7 +1397,7 @@ void CircuitLibrary::set_edge_trise(const CircuitModelId& circuit_model_id, cons /* validate the circuit_edge_id */ VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - edge_trise_[circuit_model_id][circuit_edge_id] = trise; + edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(SPICE_MODEL_DELAY_RISE)] = trise; return; } @@ -1369,10 +1405,76 @@ void CircuitLibrary::set_edge_tfall(const CircuitModelId& circuit_model_id, cons /* validate the circuit_edge_id */ VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - edge_tfall_[circuit_model_id][circuit_edge_id] = tfall; + edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(SPICE_MODEL_DELAY_FALL)] = tfall; return; } +/* Decode input names of delay_info to CircuitPorts */ +std::vector CircuitLibrary::get_delay_info_input_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Parse the string */ +// MultiPortParser input_port_parser(delay_in_port_names[circuit_model_id][size_t(delay_type)]); +// input_port_parser.add_delima(" "); +// std::vector input_port_names = input_port_parser.port_names(); + + /* Find port ids with given names */ + std::vector input_port_ids; +// for (const auto& name : input_port_names) { + /* We must have a valid port ! */ +// VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port(circuit_model_id, name)); + /* Convert to CircuitPortId */ +// input_port_ids.push_back(port(circuit_model_id, name)); + /* This must be an input port! */ +// VTR_ASSERT_SAFE(true == is_input_port(circuit_model_id, input_port_ids.back())); +// } + return input_port_ids; +} + +/* Decode input names of delay_info to CircuitPorts */ +std::vector CircuitLibrary::get_delay_info_output_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Parse the string */ +// MultiPortParser output_port_parser(delay_out_port_names[circuit_model_id][size_t(delay_type)]); +// output_port_parser.add_delima(" "); +// std::vector output_port_names = output_port_parser.port_names(); + + /* Find port ids with given names */ + std::vector output_port_ids; +// for (const auto& name : output_port_names) { + /* We must have a valid port ! */ +// VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port(circuit_model_id, name)); + /* Convert to CircuitPortId */ +// output_port_ids.push_back(port(circuit_model_id, name)); + /* This must be an output port! */ +// VTR_ASSERT_SAFE(true == is_output_port(circuit_model_id, output_port_ids.back())); +// } + return output_port_ids; +} + + +/* Annotate delay values on a timing graph */ +void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Go one delay_info by another */ + for (size_t i_delay_type = 0; i_delay_type < delay_types_[circuit_model_id].size(); ++i_delay_type) { + /* Parse the input port names and output names. + * We will store the parsing results in vectors: + * 1. vector for port ids for each port name + * 2. vector for pin ids for each port name + */ + std::vector input_port_ids; + std::vector input_pin_ids; + + std::vector output_port_ids; + std::vector output_pin_ids; + } + return; +} /************************************************************************ * Internal mutators: build fast look-ups @@ -1481,8 +1583,7 @@ void CircuitLibrary::invalidate_circuit_model_timing_graph(const CircuitModelId& edge_sink_port_ids_[circuit_model_id].clear(); edge_sink_pin_ids_[circuit_model_id].clear(); - edge_trise_[circuit_model_id].clear(); - edge_tfall_[circuit_model_id].clear(); + edge_timing_info_[circuit_model_id].clear(); return; } diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 04c220876..72300d4e1 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -237,6 +237,9 @@ class CircuitLibrary { bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ + bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + CircuitPortId port(const CircuitModelId& circuit_model_id, const std::string& name) const; size_t num_ports(const CircuitModelId& circuit_model_id) const; enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -428,6 +431,11 @@ class CircuitLibrary { const CircuitPortId& to_port, const size_t& to_pin); void set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise); void set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall); + std::vector get_delay_info_input_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const; + std::vector get_delay_info_output_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const; + void set_timing_graph_delays(const CircuitModelId& circuit_model_id); public: /* Internal mutators: build fast look-ups */ void build_circuit_model_lookup(); void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); @@ -509,8 +517,7 @@ class CircuitLibrary { vtr::vector> edge_src_pin_ids_; vtr::vector> edge_sink_port_ids_; vtr::vector> edge_sink_pin_ids_; - vtr::vector> edge_trise_; - vtr::vector> edge_tfall_; + vtr::vector>> edge_timing_info_; /* x0 => trise, x1 => tfall */ /* Delay information */ vtr::vector> delay_types_; From f80e58c753d44c88f3438118bbcdbe8a3dfe17ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2019 16:36:22 -0600 Subject: [PATCH 038/482] developing a in-house tokenizer --- .../SRC/fpga_spice_include/string_token.cpp | 120 ++++++++++++++++++ .../SRC/fpga_spice_include/string_token.h | 81 ++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp new file mode 100644 index 000000000..3b1ae265c --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp @@ -0,0 +1,120 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: string_token.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/09 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/************************************************************************ + * Member functions for StringToken class + ***********************************************************************/ + +#include "string.h" + +#include "vtr_assert.h" + +#include "string_token.h" + +/************************************************************************ + * Constructors + ***********************************************************************/ +StringToken::StringToken (const std::string& data) { + set_data(data); +} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +/* Get the data string */ +std::string StringToken::data() const { + return data_; +} + +/* Split the string */ +std::vector StringToken::split() { + /* Return vector */ + std::vector ret; + + /* Add a default delim */ + if (true == delims_.empty()) { + add_default_delim(); + } + /* Create delims */ + std::string delims; + for (const auto& delim : delims_) { + delims.push_back(delim); + } + /* Get a writable char array */ + char* tmp = new char[data_.size() + 1]; + std::copy(data_.begin(), data_.end(), tmp); + tmp[data_.size()] = '\0'; + /* Split using strtok */ + char* result = strtok(tmp, delims.c_str()); + while (NULL != result) { + std::string result_str(result); + /* Store the token */ + ret.push_back(result_str); + /* Got to next */ + result = strtok(NULL, delims.c_str()); + } + + /* Free the tmp */ + delete[] tmp; + + return ret; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void StringToken::set_data(const std::string& data) { + data_ = data; + return; +} + +/* Add a delima to the list */ +void StringToken::add_delim(const char& delim) { + delims_.push_back(delim); +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +void StringToken::add_default_delim() { + VTR_ASSERT_SAFE(true == delims_.empty()); + delims_.push_back(' '); + return; +} + +/************************************************************************ + * End of file : string_token.cpp + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h new file mode 100644 index 000000000..3387659b2 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h @@ -0,0 +1,81 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: string_token.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/09 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef STRING_TOKEN_H +#define STRING_TOKEN_H + +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include +#include + + +/************************************************************************ + * This file includes a tokenizer for string objects + * It splits a string with given delima and return a vector of tokens + * It can accept different delima in splitting strings + ***********************************************************************/ + +class StringToken { + public : /* Constructors*/ + StringToken (const std::string& data); + public : /* Public Accessors */ + std::string data() const; + std::vector split(); + public : /* Public Mutators */ + void set_data(const std::string& data); + void add_delim(const char& delim); + private : /* Private Mutators */ + void add_default_delim(); + private: /* Internal data */ + std::string data_; /* Lines to be splited */ + std::vector delims_; +}; + +#endif + +/************************************************************************ + * End of file : string_token.h + ***********************************************************************/ + From 9ab57d1b2e5de93cc842a72f2a0764a0898b3945 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 9 Aug 2019 16:49:05 -0600 Subject: [PATCH 039/482] Added fpga_flow script - Working Yosys --- .../k6_N10_rram_memory_bank_SC_winbond90.xml | 2 +- .../misc/fpgaflow_default_tool_path.conf | 16 + openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys | 22 + openfpga_flow/scripts/run_fpga_flow.py | 393 ++++++++++++++++++ 4 files changed, 432 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/misc/fpgaflow_default_tool_path.conf create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys create mode 100644 openfpga_flow/scripts/run_fpga_flow.py diff --git a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml index f0c7e5752..d32efd8de 100644 --- a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +++ b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml @@ -168,7 +168,7 @@ - + diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf new file mode 100644 index 000000000..c33b4162a --- /dev/null +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -0,0 +1,16 @@ +# Standard Configuration Example +[CAD_TOOLS_PATH] +yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys +misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc +odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe +abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc +abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc +abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc +vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr +ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace + +[OPENFPGA_FLOW_CONFIG] +# You dont need to change any of these varaibles, +# Unless you are unhappy with intermidiate directories +# or modifying fpga_flow sript significantly +supported_flows = standard,vtr,vtr_standard,yosys_vpr diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys new file mode 100644 index 000000000..aeaded4b5 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys @@ -0,0 +1,22 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +${READ_VERILOG_FILE} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +synth -top ${TOP_MODULE} -flatten +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py new file mode 100644 index 000000000..d439ef6c1 --- /dev/null +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -0,0 +1,393 @@ +import os +import shutil +import time +import shlex +import glob +import argparse +from configparser import ConfigParser, ExtendedInterpolation +import logging +import glob +import subprocess +import threading +from string import Template +import xml.etree.ElementTree as ET + + +flow_script_dir = os.path.dirname(os.path.abspath(__file__)) +openfpga_base_dir = os.path.abspath( + os.path.join(flow_script_dir, os.pardir, os.pardir)) +default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc', + 'fpgaflow_default_tool_path.conf') +launch_dir = os.getcwd() + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Setting up print and logging system +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +logging.basicConfig(level=logging.INFO, + format='%(levelname)s (%(threadName)-9s) - %(message)s') +logger = logging.getLogger('OpenFPGA_Task_logs') + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Reading commnad-line argument +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +parser = argparse.ArgumentParser() +parser.add_argument('arch_file', type=str) +parser.add_argument('benchmark_files', type=str, nargs='+') +parser.add_argument('--top_module', type=str) +parser.add_argument('--fpga_flow', type=str, default="yosys_vpr") +parser.add_argument('--cad_tool_conf', + type=str, + default=default_cad_tool_conf, + help="CAD tool path and configurations") +parser.add_argument('--run_dir', + type=str, + default=os.path.join(openfpga_base_dir, 'tmp'), + help="Directory to store intermidiate file & final results") +args = parser.parse_args() + + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Reading CAD Tools path configuration file +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +script_env_vars = {"PATH": { + "OPENFPGA_FLOW_PATH": flow_script_dir, + "OPENFPGA_PATH": openfpga_base_dir}} + +config = ConfigParser(interpolation=ExtendedInterpolation()) +config.read_dict(script_env_vars) +config.read_file( + open(os.path.join(args.cad_tool_conf))) +cad_tools = config["CAD_TOOLS_PATH"] + + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Main program starts here +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +def main(): + validate_command_line_arguments(args) + prepare_run_directory(args.run_dir) + if (args.fpga_flow == "yosys_vpr"): + logger.info('Running "yosys_vpr" Flow') + run_yosys_with_abc() + exit() + if (args.fpga_flow == "vtr"): + run_odin2() + run_abc_vtr() + if (args.fpga_flow == "vtr_standard"): + run_abc_for_standarad() + run_ace2() + run_vpr() + exit() + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Subroutines starts here +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + +def validate_command_line_arguments(args): + """ + TODO : + This funtion validates all supplied paramters + and check for compatibility + Chec correct flow + Check if architecture and circuit files exist + if argument provide relative path replace to absolute + benchmark argument convert glob to list of files + Dont maintain the directory strcuture + Throw error for directory in benchmark + """ + logger.info("Parsing commnad line arguments - Pending implementation") + + # Filter provided architecrue files + args.arch_file = os.path.abspath(args.arch_file) + if not os.path.isfile(args.arch_file): + clean_up_and_exit("Architecure file not found. -%s", args.arch_file) + + # Filter provided benchmark files + for index, everyinput in enumerate(args.benchmark_files): + args.benchmark_files[index] = os.path.abspath(everyinput) + for everyfile in glob.glob(args.benchmark_files[index]): + if not os.path.isfile(everyfile): + clean_up_and_exit( + "Failed to copy benchmark file-%s", args.arch_file) + pass + + +def ask_user_quetion(condition, question): + if condition: + reply = str(input(question+' (y/n): ')).lower().strip() + if reply[:1] in ['n', 'no']: + return False + elif reply[:1] in ['y', 'yes']: + return True + else: + return ask_user_quetion(question, condition) + return True + + +def prepare_run_directory(run_dir): + """ + Prepares run directory to run + 1. Change current directory to run_dir + 2. Copy architecture XML file to run_dir + 3. Copy circuit files to run_dir + """ + logger.info("Run directory : %s" % run_dir) + if os.path.isdir(run_dir): + no_of_files = len(next(os.walk(run_dir))[2]) + if not ask_user_quetion((no_of_files > 100), + ("[run_dir:%s] already exist and contains %d " + + "files script will remove all the file, " + + "continue? ") % (run_dir, no_of_files)): + clean_up_and_exit("Aborted by user") + else: + shutil.rmtree(run_dir) + os.makedirs(run_dir) + # Clean run_dir is created change working directory + os.chdir(run_dir) + + # Create arch dir in run_dir and copy flattern architecrture file + os.mkdir("arch") + tmpl = Template(open(args.arch_file).read()) + arch_filename = os.path.basename(args.arch_file) + args.arch_file = os.path.join(run_dir, "arch", arch_filename) + with open(args.arch_file, 'w') as archfile: + archfile.write(tmpl.substitute(script_env_vars["PATH"])) + + # Create benchmark dir in run_dir and copy flattern architecrture file + os.mkdir("benchmark") + try: + for index, eachfile in enumerate(args.benchmark_files): + args.benchmark_files[index] = shutil.copy2( + eachfile, os.path.join(os.curdir, "benchmark")) + except: + logger.exception("Failed to copy all benchmark file to run_dir") + + +def clean_up_and_exit(msg, clean=False): + logger.error(msg) + logger.error("Existing . . . . . .") + exit() + + +def run_yosys_with_abc(): + # Extract lut Input size from architecture file + tree = ET.parse(args.arch_file) + root = tree.getroot() + try: + lut_size = max([int(pb_type.find("input").get("num_pins")) + for pb_type in root.iter("pb_type") + if pb_type.get("class") == "lut"]) + logger.info("Running Yosys with lut_size = %s", lut_size) + except: + logger.exception("Failed to extract lut_size from XML file") + clean_up_and_exit("") + + # Yosys script parameter mapping + ys_params = { + "READ_VERILOG_FILE": " \n".join([ + "read_verilog -nolatches " + shlex.quote(eachfile) + for eachfile in args.benchmark_files]), + "TOP_MODULE": args.top_module, + "LUT_SIZE": lut_size, + "OUTPUT_BLIF": args.top_module+".blif", + } + yosys_template = os.path.join( + cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") + tmpl = Template(open(yosys_template).read()) + with open("yosys.ys", 'w') as archfile: + archfile.write(tmpl.substitute(ys_params)) + + try: + with open('yosys_output.txt', 'w+') as output: + process = subprocess.run([cad_tools["yosys_path"], 'yosys1.ys'], + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.info("Yosys failed with returncode %d", + process.returncode) + except: + logger.exception("Failed to run yosys") + clean_up_and_exit("") + logger.info("Yosys output written in file yosys_output.txt") + + +def run_odin2(): + pass + + +def run_abc_vtr(): + pass + + +def run_abc_for_standarad(): + pass + + +def run_ace2(): + + pass + + +def run_vpr(): + pass +# def generate_single_task_actions(taskname): +# """ +# This script generates all the scripts required for each benchmark +# """ +# curr_task_dir=os.path.join(gc["task_dir"], taskname) +# if not os.path.isdir(curr_task_dir): +# clean_up_and_exit("Task directory not found") +# os.chdir(curr_task_dir) + +# curr_task_conf_file=os.path.join(curr_task_dir, "config", "task.conf") +# if not os.path.isfile(curr_task_conf_file): +# clean_up_and_exit( +# "Missing configuration file for task %s" % curr_task_dir) + +# task_conf=ConfigParser(allow_no_value = True, +# interpolation = ExtendedInterpolation()) +# task_conf.optionxform=str +# task_conf.read_dict(script_env_vars) +# task_conf.read_file(open(curr_task_conf_file)) +# # Check required sections in config file +# required_sec=["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"] +# missing_section=list(set(required_sec)-set(task_conf.sections())) +# if missing_section: +# clean_up_and_exit( +# "Missing section %s in task configuration file" % " ".join(missing_section)) + +# benchmark_list=[] +# for _, bench_file in task_conf["BENCHMARKS"].items(): +# if(glob.glob(bench_file)): +# benchmark_list.append(bench_file) +# else: +# logger.warning( +# "File Not Found: Skipping %s benchmark " % bench_file) + +# # Check if all benchmark/architecture files exits +# archfile_list=[] +# for _, arch_file in task_conf["ARCHITECTURES"].items(): +# arch_full_path=arch_file +# if os.path.isfile(arch_full_path): +# archfile_list.append(arch_full_path) +# else: +# logger.warning( +# "File Not Found: Skipping %s architecture " % arch_file) + +# script_list=[] +# for eacharch in archfile_list: +# script_list.append(create_run_script(gc["temp_run_dir"], +# eacharch, +# benchmark_list, +# task_conf["GENERAL"]["power_tech_file"], +# task_conf["SCRIPT_PARAM"])) +# return script_list + + +# def create_run_script(task_run_dir, archfile, benchmark_list, power_tech_file, additional_fpga_flow_params): +# """ +# Create_run_script function accespts run directory, architecture list and +# fpga_flow configuration file and prepare final executable fpga_flow script +# TODO : Replace this section after convert fpga_flow to python script +# Config file creation and bechnmark list can be skipped +# """ +# # = = = = = = = = = File/Directory Consitancy Check = = = = = = = = = = +# if not os.path.isdir(gc["misc_dir"]): +# clean_up_and_exit("Miscellaneous directory does not exist") + +# fpga_flow_script=os.path.join(gc["misc_dir"], "fpga_flow_template.sh") +# if not os.path.isfile(fpga_flow_script): +# clean_up_and_exit("Missing fpga_flow script template %s" % +# fpga_flow_script) + +# fpga_flow_conf_tmpl=os.path.join(gc["misc_dir"], "fpga_flow_script.conf") +# if not os.path.isfile(fpga_flow_conf_tmpl): +# clean_up_and_exit("fpga_flow configuration tempalte is missing %s" % +# fpga_flow_conf_tmpl) + +# # = = = = = = = = = = = = Create execution folder = = = = = = = = = = = = +# # TODO : this directory should change as //{conf_opt} +# curr_job_dir=os.path.join(task_run_dir, "tmp") +# if os.path.isdir(curr_job_dir): +# shutil.rmtree(curr_job_dir) +# os.makedirs(curr_job_dir) +# os.chdir(curr_job_dir) + +# # = = = = = = = = = = = Create config file= = = = = = = = = = = = = = = = +# fpga_flow_conf=ConfigParser( +# strict=False, +# interpolation=ExtendedInterpolation()) +# fpga_flow_conf.read_dict(script_env_vars) +# fpga_flow_conf.read_file(open(fpga_flow_conf_tmpl)) + +# # HACK: Find better way to resolve all interpolations in the script and write back +# for eachSection in fpga_flow_conf: +# for eachkey in fpga_flow_conf[eachSection].keys(): +# fpga_flow_conf[eachSection][eachkey] = fpga_flow_conf.get( +# eachSection, eachkey) + +# # Update configuration file with script realated parameters +# fpga_flow_conf["flow_conf"]["vpr_arch"] = archfile +# fpga_flow_conf["flow_conf"]["power_tech_xml"] = power_tech_file + +# # Remove extra path section and create configuration file +# fpga_flow_conf.remove_section("PATH") +# with open("openfpga_job.conf", 'w') as configfile: +# fpga_flow_conf.write(configfile) + +# # = = = = = = = = = = = Create Benchmark List file = = = = = = = = = = = = +# # TODO: This script strips common path from bechmark list and add +# # only single directory and filename to benchmarklist file +# # This can be imporoved by modifying fpga_flow script +# with open("openfpga_benchmark_list.txt", 'w') as configfile: +# configfile.write("# Circuit Names, fixed routing channel width\n") +# for eachBenchMark in benchmark_list: +# configfile.write(eachBenchMark.replace( +# fpga_flow_conf["dir_path"]["benchmark_dir"], "")) +# configfile.write(",30") +# configfile.write("\n") + +# # = = = = = = = = = Create fpga_flow_shell Script = = = = = = = = = = = = +# d = { +# "fpga_flow_script": shlex.quote(gc["script_default"]), +# "conf_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_job.conf")), +# "benchmark_list_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_benchmark_list.txt")), +# "csv_rpt_file": shlex.quote(os.path.join(os.getcwd(), os.path.join(gc["csv_rpt_dir"], "fpga_flow.csv"))), +# "verilog_output_path": shlex.quote(os.path.join(os.getcwd(), gc["verilog_output_path"])), +# "additional_params": " \\\n ".join(["-%s %s" % (key, value or "") for key, value in additional_fpga_flow_params.items()]) +# } +# result = Template(open(fpga_flow_script).read()).substitute(d) +# fpga_flow_script_path = os.path.join(os.getcwd(), "openfpga_flow.sh") +# with open(fpga_flow_script_path, 'w') as configfile: +# configfile.write(result) +# return fpga_flow_script_path + + +# def run_single_script(s, script_path): +# logging.debug('Waiting to join the pool') +# with s: +# name = threading.currentThread().getName() +# subprocess.run(["bash", script_path], stdout=subprocess.PIPE) +# logging.info("%s Finished " % name) + + +# def run_actions(actions): +# thread_sema = threading.Semaphore(args.maxthreads) +# thred_list = [] +# for index, eachAction in enumerate(actions): +# t = threading.Thread(target=run_single_script, +# name='benchmark_' + str(index), +# args=(thread_sema, eachAction)) +# t.start() +# thred_list.append(t) + +# for eachthread in thred_list: +# eachthread.join() + + +if __name__ == "__main__": + main() From 2c7d6e3de42d42d677295ee870edf6d418bbd036 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2019 17:48:55 -0600 Subject: [PATCH 040/482] adding port parsers --- libs/libvtrutil/src/vtr_geometry.h | 1 + libs/libvtrutil/src/vtr_geometry.tpp | 6 + .../SRC/fpga_spice_include/port_parser.cpp | 142 ++++++++++++++++++ .../SRC/fpga_spice_include/port_parser.h | 93 ++++++++++++ .../SRC/fpga_spice_include/string_token.cpp | 44 ++++-- .../SRC/fpga_spice_include/string_token.h | 3 + 6 files changed, 278 insertions(+), 11 deletions(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index ce9cfe59f..24d641cfa 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -63,6 +63,7 @@ class Point { public: //Mutators void set_x(T x_val); void set_y(T y_val); + void swap(); private: T x_; T y_; diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 76b1ad457..6ec15ded7 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -52,6 +52,12 @@ namespace vtr { y_ = y_val; } + template + void Point::swap() { + std::swap(x_, y_); + } + + /* * Rect */ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp new file mode 100644 index 000000000..945cac4d1 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp @@ -0,0 +1,142 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: port_parser.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/09 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/************************************************************************ + * Member functions for PortParser class + ***********************************************************************/ + +#include "string.h" + +#include "vtr_assert.h" +#include "vtr_geometry.h" + +#include "string_token.h" + +#include "port_parser.h" + +/************************************************************************ + * Constructors + ***********************************************************************/ +PortParser::PortParser (const std::string& data) { + set_data(data); + set_default_bracket(); + set_default_delim(); + parse(); +} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +/* Get the data string */ +std::string PortParser::data() const { + return data_; +} + + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void PortParser::set_data(const std::string& data) { + data_ = data; + parse(); + return; +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +/* Parse the data */ +void PortParser::parse() { + /* Create a tokenizer */ + StringToken tokenizer(data_); + + /* Split the data into and */ + std::vector port_tokens = tokenizer.split(bracket_.x()); + /* Make sure we have a port name! */ + VTR_ASSERT_SAFE ((1 == port_tokens.size()) || (2 == port_tokens.size())); + /* Store the port name! */ + port_name_ = port_tokens[0]; + + /* If we only have one token */ + if (1 == port_tokens.size()) { + pin_range_.set_x(-1); + pin_range_.set_y(-1); + return; /* We can finish here */ + } + + /* Chomp the ']' */ + tokenizer.set_data(port_tokens[1]); + std::vector pin_tokens = tokenizer.split(bracket_.y()); + /* Make sure we have a valid string! */ + VTR_ASSERT_SAFE (1 == port_tokens.size()); + + /* Split the pin string now */ + tokenizer.set_data(port_tokens[0]); + pin_tokens = tokenizer.split(delim_); + + /* Check if we have LSB and MSB or just one */ + if ( 1 == pin_tokens.size() ) { + /* Single pin */ + pin_range_.set_x(stoi(pin_tokens[0])); + pin_range_.set_y(stoi(pin_tokens[0])); + } else if ( 2 == pin_tokens.size() ) { + /* A number of pin */ + pin_range_.set_x(stoi(pin_tokens[0])); + pin_range_.set_y(stoi(pin_tokens[1])); + } + + /* Reorder to ensure LSB <= MSB */ + if (pin_range_.x() > pin_range_.y()) { + pin_range_.swap(); + } + + return; +} + +void PortParser::set_default_bracket() { + bracket_.set_x('['); + bracket_.set_y(']'); + return; +} + +void PortParser::set_default_delim() { + delim_ = ':'; + return; +} + +/************************************************************************ + * End of file : port_parser.cpp + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h new file mode 100644 index 000000000..3845b2c84 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h @@ -0,0 +1,93 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: port_parser.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/09 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef PORT_PARSER_H +#define PORT_PARSER_H + +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include +#include + +#include "string_token.h" + +/************************************************************************ + * This file includes parsers for port definition in the architecture XML + * language. Note that it is also compatiable to Verilog syntax. + * It means we may reuse this for constructing a structural Verilog parser + * Supported port definition: + * 1. [:] + * 2. [:] + * 3. [] + * 4. [] + * 5. + * In case 4 and 5, we will assign (-1,-1) for LSB and MSB + ***********************************************************************/ + +class PortParser{ + public : /* Constructors*/ + PortParser (const std::string& data); + public : /* Public Accessors */ + std::string data() const; + std::vector split(); + public : /* Public Mutators */ + void set_data(const std::string& data); + private : /* Private Mutators */ + void parse(); + void set_default_bracket(); + void set_default_delim(); + private: /* Internal data */ + std::string data_; /* Lines to be splited */ + vtr::Point bracket_; + char delim_; + std::string port_name_; + vtr::Point pin_range_; +}; + +#endif + +/************************************************************************ + * End of file : port_parser.h + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp index 3b1ae265c..f040f5214 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp @@ -58,20 +58,11 @@ std::string StringToken::data() const { return data_; } -/* Split the string */ -std::vector StringToken::split() { +/* Split the string using a given delim */ +std::vector StringToken::split(const std::string& delims) const { /* Return vector */ std::vector ret; - /* Add a default delim */ - if (true == delims_.empty()) { - add_default_delim(); - } - /* Create delims */ - std::string delims; - for (const auto& delim : delims_) { - delims.push_back(delim); - } /* Get a writable char array */ char* tmp = new char[data_.size() + 1]; std::copy(data_.begin(), data_.end(), tmp); @@ -92,6 +83,37 @@ std::vector StringToken::split() { return ret; } +/* Split the string using a given delim */ +std::vector StringToken::split(const char& delim) const { + /* Create delims */ + std::string delims(1, delim); + + return split(delims); +} + +/* Split the string using a given delim */ +std::vector StringToken::split(const char* delim) const { + /* Create delims */ + std::string delims(delim); + + return split(delims); +} + +/* Split the string */ +std::vector StringToken::split() { + /* Add a default delim */ + if (true == delims_.empty()) { + add_default_delim(); + } + /* Create delims */ + std::string delims; + for (const auto& delim : delims_) { + delims.push_back(delim); + } + + return split(delims); +} + /************************************************************************ * Public Mutators ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h index 3387659b2..d5385269d 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h @@ -62,6 +62,9 @@ class StringToken { StringToken (const std::string& data); public : /* Public Accessors */ std::string data() const; + std::vector split(const std::string& delims) const; + std::vector split(const char& delim) const; + std::vector split(const char* delim) const; std::vector split(); public : /* Public Mutators */ void set_data(const std::string& data); From c004699a146bd7f4dc23edc7cea5d9a6e45c5fc6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2019 21:00:41 -0600 Subject: [PATCH 041/482] complete parsers for ports --- .../fpga_spice_include/circuit_library.cpp | 92 +++++++++--------- .../SRC/fpga_spice_include/circuit_library.h | 5 +- .../SRC/fpga_spice_include}/device_port.cpp | 12 +++ .../SRC/fpga_spice_include}/device_port.h | 7 +- .../SRC/fpga_spice_include/port_parser.cpp | 94 ++++++++++++++++--- .../SRC/fpga_spice_include/port_parser.h | 34 ++++++- 6 files changed, 176 insertions(+), 68 deletions(-) rename vpr7_x2p/{vpr/SRC/fpga_x2p/base => libarchfpga/SRC/fpga_spice_include}/device_port.cpp (96%) rename vpr7_x2p/{vpr/SRC/fpga_x2p/base => libarchfpga/SRC/fpga_spice_include}/device_port.h (93%) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index dd7862c3c..46df9d44a 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -38,6 +38,7 @@ #include "vtr_assert.h" +#include "port_parser.h" #include "circuit_library.h" /************************************************************************ @@ -1409,69 +1410,58 @@ void CircuitLibrary::set_edge_tfall(const CircuitModelId& circuit_model_id, cons return; } -/* Decode input names of delay_info to CircuitPorts */ -std::vector CircuitLibrary::get_delay_info_input_port_ids(const CircuitModelId& circuit_model_id, - const enum spice_model_delay_type& delay_type) const { - /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* Parse the string */ -// MultiPortParser input_port_parser(delay_in_port_names[circuit_model_id][size_t(delay_type)]); -// input_port_parser.add_delima(" "); -// std::vector input_port_names = input_port_parser.port_names(); - - /* Find port ids with given names */ - std::vector input_port_ids; -// for (const auto& name : input_port_names) { - /* We must have a valid port ! */ -// VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port(circuit_model_id, name)); - /* Convert to CircuitPortId */ -// input_port_ids.push_back(port(circuit_model_id, name)); - /* This must be an input port! */ -// VTR_ASSERT_SAFE(true == is_input_port(circuit_model_id, input_port_ids.back())); -// } - return input_port_ids; -} - -/* Decode input names of delay_info to CircuitPorts */ -std::vector CircuitLibrary::get_delay_info_output_port_ids(const CircuitModelId& circuit_model_id, - const enum spice_model_delay_type& delay_type) const { - /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* Parse the string */ -// MultiPortParser output_port_parser(delay_out_port_names[circuit_model_id][size_t(delay_type)]); -// output_port_parser.add_delima(" "); -// std::vector output_port_names = output_port_parser.port_names(); - - /* Find port ids with given names */ - std::vector output_port_ids; -// for (const auto& name : output_port_names) { - /* We must have a valid port ! */ -// VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port(circuit_model_id, name)); - /* Convert to CircuitPortId */ -// output_port_ids.push_back(port(circuit_model_id, name)); - /* This must be an output port! */ -// VTR_ASSERT_SAFE(true == is_output_port(circuit_model_id, output_port_ids.back())); -// } - return output_port_ids; -} - - /* Annotate delay values on a timing graph */ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); /* Go one delay_info by another */ - for (size_t i_delay_type = 0; i_delay_type < delay_types_[circuit_model_id].size(); ++i_delay_type) { + for (const auto& delay_type : delay_types_[circuit_model_id]) { /* Parse the input port names and output names. * We will store the parsing results in vectors: * 1. vector for port ids for each port name * 2. vector for pin ids for each port name */ + + /* Parse the string for inputs */ + MultiPortParser input_port_parser(delay_in_port_names_[circuit_model_id][size_t(delay_type)]); + std::vector input_ports = input_port_parser.ports(); std::vector input_port_ids; std::vector input_pin_ids; + /* Check each element */ + for (const auto& port_info : input_ports) { + /* Try to find a port by the given name */ + CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); + /* We must have a valid port and Port width must be 1! */ + VTR_ASSERT_SAFE( (CIRCUIT_PORT_OPEN_ID != port_id) && (1 == port_info.get_width()) ); + /* The pin id should be valid! */ + VTR_ASSERT_SAFE(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + /* This must be an input port! */ + VTR_ASSERT_SAFE(true == is_input_port(circuit_model_id, port_id)); + /* Push to */ + input_port_ids.push_back(port_id); + input_pin_ids.push_back(port_info.get_lsb()); + } + /* Parse the string for outputs */ + MultiPortParser output_port_parser(delay_out_port_names_[circuit_model_id][size_t(delay_type)]); + std::vector output_ports = output_port_parser.ports(); std::vector output_port_ids; std::vector output_pin_ids; + /* Check each element */ + for (const auto& port_info : output_ports) { + /* Try to find a port by the given name */ + CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); + /* We must have a valid port and Port width must be 1! */ + VTR_ASSERT_SAFE( (CIRCUIT_PORT_OPEN_ID != port_id) && (1 == port_info.get_width()) ); + /* The pin id should be valid! */ + VTR_ASSERT_SAFE(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + /* This must be an output port! */ + VTR_ASSERT_SAFE(true == is_output_port(circuit_model_id, port_id)); + /* Push to */ + output_port_ids.push_back(port_id); + output_pin_ids.push_back(port_info.get_lsb()); + } + } return; } @@ -1539,6 +1529,12 @@ bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_i return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); } +bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + return ( size_t(pin_id) < port_size(circuit_model_id, circuit_port_id) ); +} + bool CircuitLibrary::valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const { /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 72300d4e1..8002c77c0 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -431,10 +431,6 @@ class CircuitLibrary { const CircuitPortId& to_port, const size_t& to_pin); void set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise); void set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall); - std::vector get_delay_info_input_port_ids(const CircuitModelId& circuit_model_id, - const enum spice_model_delay_type& delay_type) const; - std::vector get_delay_info_output_port_ids(const CircuitModelId& circuit_model_id, - const enum spice_model_delay_type& delay_type) const; void set_timing_graph_delays(const CircuitModelId& circuit_model_id); public: /* Internal mutators: build fast look-ups */ void build_circuit_model_lookup(); @@ -443,6 +439,7 @@ class CircuitLibrary { /* Validators */ bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; bool valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const; /* Invalidators */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.cpp similarity index 96% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.cpp rename to vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.cpp index 6ab88ac94..2e181fce5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.cpp @@ -37,14 +37,26 @@ size_t BasicPort::get_lsb() const { return lsb_; } +/* get the name */ +std::string BasicPort::get_name() const { + return name_; +} + /* Mutators */ /* copy */ void BasicPort::set(const BasicPort& basic_port) { + name_ = basic_port.get_name(); lsb_ = basic_port.get_lsb(); msb_ = basic_port.get_msb(); return; } + +/* set the port LSB and MSB */ +void BasicPort::set_name(const std::string& name) { + name_ = name; + return; +} /* set the port LSB and MSB */ void BasicPort::set_width(size_t width) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.h similarity index 93% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.h rename to vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.h index 905a4d0bf..fbf887421 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_port.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.h @@ -5,6 +5,8 @@ #ifndef DEVICE_PORT_H #define DEVICE_PORT_H +#include + /* A basic port */ class BasicPort { public: /* Constructors */ @@ -14,8 +16,11 @@ class BasicPort { size_t get_width() const; /* get the port width */ size_t get_msb() const; /* get the LSB */ size_t get_lsb() const; /* get the LSB */ + std::string get_name() const; /* get the name */ + bool is_valid() const; /* check if port size is valid > 0 */ public: /* Mutators */ void set(const BasicPort& basic_port); /* copy */ + void set_name(const std::string& name); /* set the port LSB and MSB */ void set_width(size_t width); /* set the port LSB and MSB */ void set_width(size_t lsb, size_t msb); /* set the port LSB and MSB */ void set_lsb(size_t lsb); @@ -28,8 +33,8 @@ class BasicPort { void combine(const BasicPort& port); /* Combine two ports */ private: /* internal functions */ void make_invalid(); /* Make a port invalid */ - bool is_valid() const; /* check if port size is valid > 0 */ private: /* Internal Data */ + std::string name_; /* Name of this port */ size_t msb_; /* Most Significant Bit of this port */ size_t lsb_; /* Least Significant Bit of this port */ }; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp index 945cac4d1..c9e5eff16 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp @@ -34,7 +34,7 @@ ***********************************************************************/ /************************************************************************ - * Member functions for PortParser class + * Member functions for Port parsers ***********************************************************************/ #include "string.h" @@ -46,6 +46,10 @@ #include "port_parser.h" +/************************************************************************ + * Member functions for PortParser class + ***********************************************************************/ + /************************************************************************ * Constructors ***********************************************************************/ @@ -64,6 +68,9 @@ std::string PortParser::data() const { return data_; } +BasicPort PortParser::port() const { + return port_; +} /************************************************************************ * Public Mutators @@ -87,12 +94,11 @@ void PortParser::parse() { /* Make sure we have a port name! */ VTR_ASSERT_SAFE ((1 == port_tokens.size()) || (2 == port_tokens.size())); /* Store the port name! */ - port_name_ = port_tokens[0]; + port_.set_name(port_tokens[0]); /* If we only have one token */ if (1 == port_tokens.size()) { - pin_range_.set_x(-1); - pin_range_.set_y(-1); + port_.set_width(0); return; /* We can finish here */ } @@ -109,17 +115,15 @@ void PortParser::parse() { /* Check if we have LSB and MSB or just one */ if ( 1 == pin_tokens.size() ) { /* Single pin */ - pin_range_.set_x(stoi(pin_tokens[0])); - pin_range_.set_y(stoi(pin_tokens[0])); + port_.set_width(stoi(pin_tokens[0]), stoi(pin_tokens[0])); } else if ( 2 == pin_tokens.size() ) { /* A number of pin */ - pin_range_.set_x(stoi(pin_tokens[0])); - pin_range_.set_y(stoi(pin_tokens[1])); + port_.set_width(stoi(pin_tokens[0]), stoi(pin_tokens[1])); } - /* Reorder to ensure LSB <= MSB */ - if (pin_range_.x() > pin_range_.y()) { - pin_range_.swap(); + /* Re-order to ensure LSB <= MSB */ + if (false == port_.is_valid()) { + port_.revert(); } return; @@ -136,6 +140,74 @@ void PortParser::set_default_delim() { return; } +/************************************************************************ + * Member functions for MultiPortParser class + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +MultiPortParser::MultiPortParser (const std::string& data) { + set_data(data); + set_default_delim(); + parse(); +} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +/* Get the data string */ +std::string MultiPortParser::data() const { + return data_; +} + +std::vector MultiPortParser::ports() const { + return ports_; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void MultiPortParser::set_data(const std::string& data) { + data_ = data; + parse(); + return; +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +/* Split the data line into fragments and parse one by one */ +void MultiPortParser::parse() { + /* Clear content */ + clear(); + + /* Create a tokenizer */ + StringToken tokenizer(data_); + + /* Split the data into and */ + std::vector port_tokens = tokenizer.split(delim_); + + /* Use PortParser for each token */ + for (const auto& port : port_tokens) { + PortParser port_parser(port); + /* Get the port name, LSB and MSB */ + ports_.push_back(port_parser.port()); + } + + return; +} + +void MultiPortParser::set_default_delim() { + delim_ = ' '; + return; +} + +void MultiPortParser::clear() { + ports_.clear(); + return; +} + /************************************************************************ * End of file : port_parser.cpp ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h index 3845b2c84..ddd527559 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h @@ -50,12 +50,19 @@ #include #include +#include "vtr_geometry.h" + +#include "device_port.h" #include "string_token.h" /************************************************************************ * This file includes parsers for port definition in the architecture XML * language. Note that it is also compatiable to Verilog syntax. * It means we may reuse this for constructing a structural Verilog parser + ***********************************************************************/ + +/************************************************************************ + * Class PortParser: single port parser * Supported port definition: * 1. [:] * 2. [:] @@ -64,13 +71,12 @@ * 5. * In case 4 and 5, we will assign (-1,-1) for LSB and MSB ***********************************************************************/ - class PortParser{ public : /* Constructors*/ PortParser (const std::string& data); public : /* Public Accessors */ std::string data() const; - std::vector split(); + BasicPort port() const; public : /* Public Mutators */ void set_data(const std::string& data); private : /* Private Mutators */ @@ -81,8 +87,28 @@ class PortParser{ std::string data_; /* Lines to be splited */ vtr::Point bracket_; char delim_; - std::string port_name_; - vtr::Point pin_range_; + BasicPort port_; +}; + +/************************************************************************ + * MultiPortParser: a parser for multiple ports in one line + ***********************************************************************/ +class MultiPortParser { + public : /* Constructors*/ + MultiPortParser (const std::string& data); + public : /* Public Accessors */ + std::string data() const; + std::vector ports() const; + public : /* Public Mutators */ + void set_data(const std::string& data); + private : /* Private Mutators */ + void parse(); + void set_default_delim(); + void clear(); + private: /* Internal data */ + std::string data_; /* Lines to be splited */ + char delim_; + std::vector ports_; }; #endif From fbdab32a2df6c584eb32bef0c23569454ef4823d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 10 Aug 2019 13:03:24 -0600 Subject: [PATCH 042/482] timing graph for circuit models are working --- .../fpga_spice_include/circuit_library.cpp | 91 ++++++++++--- .../SRC/fpga_spice_include/circuit_library.h | 11 +- .../SRC/fpga_spice_include/port_parser.cpp | 125 +++++++++++++++++- .../SRC/fpga_spice_include/port_parser.h | 28 ++++ .../SRC/fpga_spice_include/string_token.cpp | 32 +++++ .../SRC/fpga_spice_include/string_token.h | 4 + 6 files changed, 269 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 46df9d44a..240cefcf7 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -373,6 +373,29 @@ CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_ty return circuit_model_lookup_[size_t(type)].front(); } +/************************************************************************ + * Public Accessors: Timing graph + ***********************************************************************/ +/* Given the source and sink port information, find the edge connecting the two ports */ +CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& circuit_model_id, + const CircuitPortId& from_port, const size_t from_pin, + const CircuitPortId& to_port, const size_t to_pin) { + /* validate the circuit_pin_id */ + VTR_ASSERT_SAFE(valid_circuit_pin_id(circuit_model_id, from_port, from_pin)); + VTR_ASSERT_SAFE(valid_circuit_pin_id(circuit_model_id, to_port, to_pin)); + /* Walk through the edge list until we find the one */ + for (auto edge : edge_ids_[circuit_model_id]) { + if ( (from_port == edge_src_port_ids_[circuit_model_id][edge]) + && (from_pin == edge_src_pin_ids_[circuit_model_id][edge]) + && (to_port == edge_sink_port_ids_[circuit_model_id][edge]) + && (to_pin == edge_sink_pin_ids_[circuit_model_id][edge]) ) { + return edge; + } + } + /* Reach here it means we find nothing! */ + return CIRCUIT_EDGE_OPEN_ID; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -1388,25 +1411,21 @@ void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, edge_sink_pin_ids_[circuit_model_id].push_back(to_pin); /* Give a default value for timing values */ - std::vector timing_info(2, 0); - edge_timing_info_[circuit_model_id].emplace_back(timing_info); + std::vector timing_info(NUM_CIRCUIT_MODEL_DELAY_TYPES, 0); + edge_timing_info_[circuit_model_id].push_back(timing_info); return; } -void CircuitLibrary::set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise) { +void CircuitLibrary::set_edge_delay(const CircuitModelId& circuit_model_id, + const CircuitEdgeId& circuit_edge_id, + const enum spice_model_delay_type& delay_type, + const float& delay_value) { /* validate the circuit_edge_id */ VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); + VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); - edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(SPICE_MODEL_DELAY_RISE)] = trise; - return; -} - -void CircuitLibrary::set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall) { - /* validate the circuit_edge_id */ - VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - - edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(SPICE_MODEL_DELAY_FALL)] = tfall; + edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(delay_type)] = delay_value; return; } @@ -1428,11 +1447,20 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model std::vector input_port_ids; std::vector input_pin_ids; /* Check each element */ - for (const auto& port_info : input_ports) { + for (auto& port_info : input_ports) { /* Try to find a port by the given name */ CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT_SAFE( (CIRCUIT_PORT_OPEN_ID != port_id) && (1 == port_info.get_width()) ); + VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port_id); + if (0 == port_info.get_width()) { + /* we need to configure the port width if it is zero. + * This means that parser find some compact port defintion such as + */ + size_t port_width = port_size(circuit_model_id, port_id); + port_info.set_width(port_width); + } else { + VTR_ASSERT_SAFE(1 == port_info.get_width()); + } /* The pin id should be valid! */ VTR_ASSERT_SAFE(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); /* This must be an input port! */ @@ -1448,11 +1476,20 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model std::vector output_port_ids; std::vector output_pin_ids; /* Check each element */ - for (const auto& port_info : output_ports) { + for (auto& port_info : output_ports) { /* Try to find a port by the given name */ CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT_SAFE( (CIRCUIT_PORT_OPEN_ID != port_id) && (1 == port_info.get_width()) ); + VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port_id); + if (0 == port_info.get_width()) { + /* we need to configure the port width if it is zero. + * This means that parser find some compact port defintion such as + */ + size_t port_width = port_size(circuit_model_id, port_id); + port_info.set_width(port_width); + } else { + VTR_ASSERT_SAFE(1 == port_info.get_width()); + } /* The pin id should be valid! */ VTR_ASSERT_SAFE(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); /* This must be an output port! */ @@ -1462,6 +1499,28 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model output_pin_ids.push_back(port_info.get_lsb()); } + /* Parse the delay matrix */ + PortDelayParser port_delay_parser(delay_values_[circuit_model_id][size_t(delay_type)]); + + /* Make sure the delay matrix size matches */ + VTR_ASSERT_SAFE(port_delay_parser.height() == output_port_ids.size()); + VTR_ASSERT_SAFE(port_delay_parser.height() == output_pin_ids.size()); + VTR_ASSERT_SAFE(port_delay_parser.width() == input_port_ids.size()); + VTR_ASSERT_SAFE(port_delay_parser.width() == input_pin_ids.size()); + + /* Configure timing graph */ + for (size_t i = 0; i < port_delay_parser.height(); ++i) { + for (size_t j = 0; j < port_delay_parser.width(); ++j) { + float delay_value = port_delay_parser.delay(i, j); + CircuitEdgeId edge_id = edge(circuit_model_id, + input_port_ids[j], input_pin_ids[j], + output_port_ids[i], output_pin_ids[i]); + /* make sure we have an valid edge_id */ + VTR_ASSERT_SAFE(true == valid_circuit_edge_id(circuit_model_id, edge_id)); + set_edge_delay(circuit_model_id, edge_id, + delay_type, delay_value); + } + } } return; } diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 8002c77c0..cdaf5f426 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -256,6 +256,10 @@ class CircuitLibrary { public: /* Public Accessors: Methods to find circuit model */ CircuitModelId circuit_model(const std::string& name) const; CircuitModelId default_circuit_model(const enum e_spice_model_type& type) const; + public: /* Public Accessors: Timing graph */ + CircuitEdgeId edge(const CircuitModelId& circuit_model_id, + const CircuitPortId& from_port, const size_t from_pin, + const CircuitPortId& to_port, const size_t to_pin); public: /* Public Mutators */ CircuitModelId add_circuit_model(); /* Fundamental information */ @@ -429,8 +433,11 @@ class CircuitLibrary { void add_edge(const CircuitModelId& circuit_model_id, const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin); - void set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise); - void set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall); + void set_edge_delay(const CircuitModelId& circuit_model_id, + const CircuitEdgeId& circuit_edge_id, + const enum spice_model_delay_type& delay_type, + const float& delay_value); + /* validate the circuit_edge_id */ void set_timing_graph_delays(const CircuitModelId& circuit_model_id); public: /* Internal mutators: build fast look-ups */ void build_circuit_model_lookup(); diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp index c9e5eff16..9453787e3 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp @@ -54,10 +54,9 @@ * Constructors ***********************************************************************/ PortParser::PortParser (const std::string& data) { - set_data(data); set_default_bracket(); set_default_delim(); - parse(); + set_data(data); } /************************************************************************ @@ -148,9 +147,8 @@ void PortParser::set_default_delim() { * Constructors ***********************************************************************/ MultiPortParser::MultiPortParser (const std::string& data) { - set_data(data); set_default_delim(); - parse(); + set_data(data); } /************************************************************************ @@ -208,6 +206,125 @@ void MultiPortParser::clear() { return; } +/************************************************************************ + * Member functions for PortDelayParser class + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +PortDelayParser::PortDelayParser (const std::string& data) { + set_default_element_delim(); + set_default_line_delim(); + set_data(data); +} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +/* Get the data string */ +std::string PortDelayParser::data() const { + return data_; +} + +/* Get the size of delay matrix [height, width]*/ +size_t PortDelayParser::height() const { + return delay_matrix_.dim_size(0); +} + +size_t PortDelayParser::width() const { + return delay_matrix_.dim_size(1); +} + +vtr::Point PortDelayParser::delay_size() const { + vtr::Point matrix_size(height(), width()); + return matrix_size; +} + +float PortDelayParser::delay(size_t x, size_t y) const { + /* Make sure x and y are in range */ + VTR_ASSERT_SAFE( (x < width()) && (y < height()) ); + return delay_matrix_[x][y]; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void PortDelayParser::set_data(const std::string& data) { + data_ = data; + parse(); + return; +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +/* Split the data line into fragments and parse one by one */ +void PortDelayParser::parse() { + /* Clear content */ + clear(); + + /* Create a tokenizer */ + StringToken delay_tokenizer(data_); + /* Ensure a clean start! Trim whitespace at the beginning and end of the string */ + delay_tokenizer.trim(); + + /* Split the data into different lines */ + std::vector delay_lines = delay_tokenizer.split(line_delim_); + + /* The number of lines is actually the height of delay matrix */ + size_t matrix_height = delay_lines.size(); + size_t matrix_width = 0; + + /* Visit each line and split with element_delim */ + for (const auto& line : delay_lines) { + /* Create a tokenizer for each line */ + StringToken line_tokenizer(line); + std::vector delay_elements = line_tokenizer.split(element_delim_); + /* Get maximum number of length, which is the width of delay matrix */ + matrix_width = std::max(matrix_width, delay_elements.size()); + } + + /* Resize matrix */ + delay_matrix_.resize({matrix_height, matrix_width}); + + /* Fill matrix */ + for (const auto& line : delay_lines) { + /* Create a tokenizer for each line */ + StringToken line_tokenizer(line); + std::vector delay_elements = line_tokenizer.split(element_delim_); + /* Get maximum number of length, which is the width of delay matrix */ + for (const auto& element : delay_elements) { + delay_matrix_[size_t(&line - &delay_lines[0])][size_t(&element - &delay_elements[0])] = stof(element); + } + } + + return; +} + +void PortDelayParser::set_default_element_delim() { + /* Ensure a clean start */ + element_delim_.clear(); + element_delim_.push_back(' '); + element_delim_.push_back('\t'); + return; +} + +void PortDelayParser::set_default_line_delim() { + /* Ensure a clean start */ + line_delim_.clear(); + line_delim_.push_back('\n'); + line_delim_.push_back('\r'); + return; +} + +void PortDelayParser::clear() { + delay_matrix_.clear(); + return; +} + + + /************************************************************************ * End of file : port_parser.cpp ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h index ddd527559..9105a7082 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h @@ -50,6 +50,7 @@ #include #include +#include "vtr_ndmatrix.h" #include "vtr_geometry.h" #include "device_port.h" @@ -111,6 +112,33 @@ class MultiPortParser { std::vector ports_; }; +/************************************************************************ + * PortDelayParser: a parser for 2D delay matrix + ***********************************************************************/ +class PortDelayParser { + public : /* Constructors*/ + PortDelayParser (const std::string& data); + public : /* Public Accessors */ + std::string data() const; + size_t height() const; + size_t width() const; + vtr::Point delay_size() const; + float delay(size_t x, size_t y) const; + public : /* Public Mutators */ + void set_data(const std::string& data); + private : /* Private Mutators */ + void parse(); + void set_default_element_delim(); + void set_default_line_delim(); + void clear(); + private: /* Internal data */ + std::string data_; /* Lines to be splited */ + std::vector element_delim_; + std::vector line_delim_; + vtr::Matrix delay_matrix_; +}; + + #endif /************************************************************************ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp index f040f5214..2f6dab90c 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp @@ -99,6 +99,18 @@ std::vector StringToken::split(const char* delim) const { return split(delims); } +/* Split the string using a given delim */ +std::vector StringToken::split(const std::vector& delims) const { + /* Create delims */ + std::string delims_str; + for (const auto& delim : delims) { + delims_str.push_back(delim); + } + + return split(delims_str); +} + + /* Split the string */ std::vector StringToken::split() { /* Add a default delim */ @@ -127,6 +139,26 @@ void StringToken::add_delim(const char& delim) { delims_.push_back(delim); } +/* Remove the string repeated at the beginning of string */ +void StringToken::ltrim(const std::string& sensitive_word) { + size_t start = data_.find_first_not_of(sensitive_word); + data_ = (start == std::string::npos) ? "" : data_.substr(start); + return; +} + +/* Remove the string repeated at the end of string */ +void StringToken::rtrim(const std::string& sensitive_word) { + size_t end = data_.find_last_not_of(sensitive_word); + data_ = (end == std::string::npos) ? "" : data_.substr(0, end + 1); + return; +} + +void StringToken::trim() { + rtrim(" "); + ltrim(" "); + return; +} + /************************************************************************ * Internal Mutators ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h index d5385269d..c0a4c1614 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h @@ -65,10 +65,14 @@ class StringToken { std::vector split(const std::string& delims) const; std::vector split(const char& delim) const; std::vector split(const char* delim) const; + std::vector split(const std::vector& delim) const; std::vector split(); public : /* Public Mutators */ void set_data(const std::string& data); void add_delim(const char& delim); + void ltrim(const std::string& sensitive_word); + void rtrim(const std::string& sensitive_word); + void trim(); private : /* Private Mutators */ void add_default_delim(); private: /* Internal data */ From d4ae160d3a36227b65f1274141eac3d06355bdde Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Aug 2019 14:20:11 -0600 Subject: [PATCH 043/482] start adding circuit library checkers --- .../SRC/fpga_spice_include/read_xml_spice.h | 49 +++++++++++++++++++ vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 43 +++++++++++++++- 2 files changed, 91 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice.h index bb4d55b91..b22f478e9 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice.h @@ -1,6 +1,55 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: read_xml_spice.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2015/XX/XX | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef READ_XML_SPICE_H +#define READ_XML_SPICE_H + /* Xifan TANG: Spice Support*/ void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch); void ProcessSpiceSettings(ezxml_t Parent, t_spice* spice); + +#endif + +/************************************************************************ + * End of file : read_xml_spice.h + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index ba7cb7cec..63403cd94 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1,3 +1,40 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: read_xml_spice.c + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2015/XX/XX | Xifan Tang | Created + * +-------------------------------------+ + * | 2019/08/12 | Xifan Tang | Code construction for circuit library + * +-------------------------------------+ + ***********************************************************************/ + #include #include #include "util.h" @@ -11,6 +48,7 @@ #include "read_xml_spice.h" #include "circuit_library.h" +#include "check_circuit_library.h" /*********** Subroutines Declaration (only called in this source file) **********/ static void ProcessSpiceMeasParams(ezxml_t Parent, @@ -1787,6 +1825,7 @@ void ProcessSpiceSettings(ezxml_t Parent, } /* Build the CircuitLibrary here from spice_models */ spice->circuit_lib = build_circuit_library(spice->num_spice_model, spice->spice_models); + //check_circuit_library(spice->circuit_lib); /* Check codes*/ check_tech_lib(spice->tech_lib, spice->num_spice_model, spice->spice_models); @@ -1795,4 +1834,6 @@ void ProcessSpiceSettings(ezxml_t Parent, return; } - +/************************************************************************ + * End of file : read_xml_spice.c + ***********************************************************************/ From c56f289d3e44e6f72ebfb283a9a0f16015932191 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Aug 2019 16:45:33 -0600 Subject: [PATCH 044/482] add checkers for circuit library --- .../check_circuit_library.cpp | 254 ++++++++++++++++++ .../check_circuit_library.h | 60 +++++ .../fpga_spice_include/circuit_library.cpp | 33 +++ .../SRC/fpga_spice_include/circuit_library.h | 3 + .../SRC/fpga_spice_include/circuit_types.h | 4 + vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 2 +- 6 files changed, 355 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp create mode 100644 vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp new file mode 100644 index 000000000..f136dba4c --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp @@ -0,0 +1,254 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: check_circuit_library.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/12 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include "util.h" +#include "check_circuit_library.h" + + +/* 1. Circuit models have unique names, return the number of errors */ +static +size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { + size_t num_err = 0; + + for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { + /* Skip for the last element, because the inner loop will access it */ + if (i == circuit_lib.num_circuit_models() - 1) { + continue; + } + /* Get the name of reference */ + const std::string& i_name = circuit_lib.circuit_model_name(CircuitModelId(i)); + for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { + /* Compare the name of candidate */ + const std::string& j_name = circuit_lib.circuit_model_name(CircuitModelId(j)); + /* Compare the name and skip for different names */ + if (0 != i_name.compare(j_name)) { + continue; + } + vpr_printf(TIO_MESSAGE_ERROR, + "Circuit model(index=%d) and (index=%d) share the same name, which is invalid!\n", + i , j, i_name.c_str()); + /* Incremental the counter for errors */ + num_err++; + } + } + + return num_err; +} + + +/* 1. Circuit models have unique names, return the number of errors */ +static +size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { + size_t num_err = 0; + + for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { + /* Skip for the last element, because the inner loop will access it */ + if (i == circuit_lib.num_circuit_models() - 1) { + continue; + } + /* Get the name of reference */ + const std::string& i_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(i)); + for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { + /* Compare the name of candidate */ + const std::string& j_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(j)); + /* Compare the name and skip for different prefix */ + if (0 != i_prefix.compare(j_prefix)) { + continue; + } + vpr_printf(TIO_MESSAGE_ERROR, + "Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n", + circuit_lib.circuit_model_name(CircuitModelId(i)).c_str(), + circuit_lib.circuit_model_name(CircuitModelId(j)).c_str(), + i_prefix.c_str()); + /* Incremental the counter for errors */ + num_err++; + } + } + + return num_err; +} + +/* A generic function to check the port list of a circuit model in a given type */ +static +size_t check_circuit_model_required(const CircuitLibrary& circuit_lib, + const enum e_spice_model_type& circuit_model_type_to_check) { + size_t num_err = 0; + + /* We must have an IOPAD*/ + if ( 0 == circuit_lib.circuit_models_by_type(circuit_model_type_to_check).size()) { + vpr_printf(TIO_MESSAGE_ERROR, + "At least one %s circuit model is required!\n", + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]); + /* Incremental the counter for errors */ + num_err++; + } + + return num_err; +} + +/* A generic function to check the port list of a circuit model in a given type */ +static +size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, + const enum e_spice_model_type& circuit_model_type_to_check, + const std::vector& port_types_to_check) { + size_t num_err = 0; + + for (const auto& id : circuit_lib.circuit_models_by_type(circuit_model_type_to_check)) { + for (const auto& port_type: port_types_to_check) { + if (0 == circuit_lib.ports_by_type(id, port_type).size()) { + vpr_printf(TIO_MESSAGE_ERROR, + "%s circuit model(name=%s) does not have %s port\n", + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)], + circuit_lib.circuit_model_name(id).c_str(), + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); + /* Incremental the counter for errors */ + num_err++; + } + } + } + + return num_err; +} + +/************************************************************************ + * Check points to make sure we have a valid circuit library + * Detailed checkpoints: + * 1. Circuit models have unique names + * 2. Circuit models have unique prefix + * 3. Check IOPADs have input and output ports + * 4. Check MUXes has been defined and has input and output ports + ***********************************************************************/ +void check_circuit_library(const CircuitLibrary& circuit_lib) { + size_t num_err = 0; + + vpr_printf(TIO_MESSAGE_INFO, "Checking circuit models...\n"); + + /* 1. Circuit models have unique names + * For each circuit model, we always make sure it does not share any name with any circuit model locating after it + */ + num_err += check_circuit_library_unique_names(circuit_lib); + + /* 2. Circuit models have unique prefix + * For each circuit model, we always make sure it does not share any prefix with any circuit model locating after it + */ + num_err += check_circuit_library_unique_prefix(circuit_lib); + + /* 3. Check io has been defined and has input and output ports + * [a] We must have an IOPAD! + * [b] For each IOPAD, we must have at least an input, an output, an INOUT and an SRAM port + */ + num_err += check_circuit_model_required(circuit_lib, SPICE_MODEL_IOPAD); + + std::vector iopad_port_types_required; + iopad_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + iopad_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + iopad_port_types_required.push_back(SPICE_MODEL_PORT_INOUT); + iopad_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); + + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_IOPAD, iopad_port_types_required); + + /* 4. Check mux has been defined and has input and output ports + * [a] We must have a MUX! + * [b] For each MUX, we must have at least an input, an output, and an SRAM port + */ + num_err += check_circuit_model_required(circuit_lib, SPICE_MODEL_MUX); + + std::vector mux_port_types_required; + mux_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + mux_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + mux_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); + + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required); + + /* 5. We must have at least one SRAM or SCFF */ + if ( ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SRAM).size()) + && ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SCFF).size()) ) { + vpr_printf(TIO_MESSAGE_ERROR, + "At least one %s or %s circuit model is required!\n", + CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)], + CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SCFF)]); + /* Incremental the counter for errors */ + num_err++; + } + + /* 6. SRAM must have at least an input and an output ports*/ + std::vector sram_port_types_required; + sram_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + sram_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SRAM, sram_port_types_required); + + /* 7. SCFF must have at least an input and an output ports*/ + std::vector scff_port_types_required; + scff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); + scff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + scff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SCFF, scff_port_types_required); + + /* 8. FF must have at least an input and an output ports*/ + std::vector ff_port_types_required; + ff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); + ff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + ff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_FF, ff_port_types_required); + + /* 9. LUY must have at least an input, an output and a SRAM ports*/ + std::vector lut_port_types_required; + lut_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); + lut_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + lut_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_LUT, lut_port_types_required); + + /* If we have any errors, exit */ + vpr_printf(TIO_MESSAGE_ERROR, + "Finished checking circuit library with %d errors!\n", + num_err); + + if (0 < num_err) { + exit(1); + } + + return; +} + +/************************************************************************ + * End of file : check_circuit_library.cpp + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h new file mode 100644 index 000000000..4dd9d1307 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h @@ -0,0 +1,60 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: check_circuit_library.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/12 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef CHECK_CIRCUIT_LIBRARY_H +#define CHECK_CIRCUIT_LIBRARY_H + +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include "circuit_library.h" + +/* Check points to make sure we have a valid circuit library */ +void check_circuit_library(const CircuitLibrary& circuit_lib); + +#endif + +/************************************************************************ + * End of file : check_circuit_library.h + ***********************************************************************/ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 240cefcf7..e8487bdff 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -60,6 +60,34 @@ CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& c return vtr::make_range(port_ids_[circuit_model_id].begin(), port_ids_[circuit_model_id].end()); } +/* Find circuit models in the same type (defined by users) and return a list of ids */ +std::vector CircuitLibrary::circuit_models_by_type(const enum e_spice_model_type& type) const { + std::vector type_ids; + for (auto id : circuit_models()) { + /* Skip unmatched types */ + if (type != circuit_model_type(id)) { + continue; + } + /* Matched type, update the vector */ + type_ids.push_back(id); + } + return type_ids; +} + +/* Find the ports of a circuit model by a given type, return a list of qualified ports */ +std::vector CircuitLibrary::ports_by_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_port_type& type) const { + std::vector port_ids; + for (const auto& port_id : ports(circuit_model_id)) { + /* We skip unmatched ports */ + if ( type != port_type(circuit_model_id, port_id) ) { + continue; + } + port_ids.push_back(port_id); + } + return port_ids; +} + /* Create a vector for all the ports whose directionality is input * This includes all the ports other than whose types are OUPUT or INOUT */ @@ -104,6 +132,11 @@ std::vector CircuitLibrary::pins(const CircuitModelId& circuit_model_id, /************************************************************************ * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ +/* Get the number of circuit models */ +size_t CircuitLibrary::num_circuit_models() const { + return circuit_model_ids_.size(); +} + /* Access the type of a circuit model */ enum e_spice_model_type CircuitLibrary::circuit_model_type(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index cdaf5f426..b655730d0 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -219,10 +219,13 @@ class CircuitLibrary { public: /* Accessors: aggregates */ circuit_model_range circuit_models() const; circuit_port_range ports(const CircuitModelId& circuit_model_id) const; + std::vector circuit_models_by_type(const enum e_spice_model_type& type) const; + std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type) const; std::vector input_ports(const CircuitModelId& circuit_model_id) const; std::vector output_ports(const CircuitModelId& circuit_model_id) const; std::vector pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Basic data query on Circuit Models*/ + size_t num_circuit_models() const; enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; std::string circuit_model_name(const CircuitModelId& circuit_model_id) const; std::string circuit_model_prefix(const CircuitModelId& circuit_model_id) const; diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h index c13e91934..0ad9790dd 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h @@ -73,6 +73,8 @@ enum e_spice_model_type { SPICE_MODEL_GATE, NUM_CIRCUIT_MODEL_TYPES }; +/* Strings correspond to each port type */ +constexpr std::array CIRCUIT_MODEL_TYPE_STRING = {{"CHAN_WIRE", "WIRE", "MUX", "LUT", "FF", "SRAM", "HARDLOGIC", "SCFF", "IOPAD", "INVBUF", "PASSGATE", "GATE"}}; enum e_spice_model_design_tech { SPICE_MODEL_DESIGN_CMOS, @@ -125,6 +127,8 @@ enum e_spice_model_port_type { SPICE_MODEL_PORT_WLB, NUM_CIRCUIT_MODEL_PORT_TYPES }; +/* Strings correspond to each port type */ +constexpr std::array CIRCUIT_MODEL_PORT_TYPE_STRING = {{"INPUT", "OUTPUT", "INOUT", "CLOCK", "SRAM", "BL", "BLB", "WL", "WLB"}}; /* For SRAM */ enum e_sram_orgz { diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 63403cd94..ac0892cf8 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1825,7 +1825,7 @@ void ProcessSpiceSettings(ezxml_t Parent, } /* Build the CircuitLibrary here from spice_models */ spice->circuit_lib = build_circuit_library(spice->num_spice_model, spice->spice_models); - //check_circuit_library(spice->circuit_lib); + check_circuit_library(spice->circuit_lib); /* Check codes*/ check_tech_lib(spice->tech_lib, spice->num_spice_model, spice->spice_models); From 785124642484aa7620a0d8de9f95d04366cd0ba8 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 13 Aug 2019 11:08:30 -0600 Subject: [PATCH 045/482] Resolve merge issue --- vpr7_x2p/vpr/regression_verilog.sh | 4 ---- 1 file changed, 4 deletions(-) diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index d74c6eff4..7fecf74d1 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,12 +33,8 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -<<<<<<< HEAD -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_x2p_compact_routing_hierarchy --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis -======= echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping ->>>>>>> origin/dev cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path From 392f5798368c40b2a685dab1e2090270a6144e1d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 13:25:23 -0600 Subject: [PATCH 046/482] add linking functions for circuit models and architecture, memory sanitizing is ongoing --- .../check_circuit_library.cpp | 249 +++++++- .../check_circuit_library.h | 26 + .../fpga_spice_include/circuit_library.cpp | 386 +++++++----- .../SRC/fpga_spice_include/circuit_library.h | 4 + .../SRC/fpga_spice_include/circuit_types.h | 3 + .../SRC/fpga_spice_include/spice_types.h | 1 + .../libarchfpga/SRC/include/physical_types.h | 6 + vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 5 +- vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 1 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 1 - .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 9 +- .../fpga_x2p/base/link_arch_circuit_lib.cpp | 592 ++++++++++++++++++ .../SRC/fpga_x2p/base/link_arch_circuit_lib.h | 68 ++ 14 files changed, 1166 insertions(+), 186 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp index f136dba4c..98952927f 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp @@ -33,13 +33,27 @@ * +-------------------------------------+ ***********************************************************************/ +/************************************************************************ + * Function to perform fundamental checking for the circuit library + * such as + * 1. if default circuit models are defined + * 2. if any circuit models shared the same name or prefix + * 3. if nay circuit model miss mandatory ports + ***********************************************************************/ + /* Header files should be included in a sequence */ /* Standard header files required go first */ +#include "vtr_assert.h" + #include "util.h" + #include "check_circuit_library.h" -/* 1. Circuit models have unique names, return the number of errors */ +/************************************************************************ + * Circuit models have unique names, return the number of errors + * If not found, we give an error + ***********************************************************************/ static size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { size_t num_err = 0; @@ -70,7 +84,10 @@ size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { } -/* 1. Circuit models have unique names, return the number of errors */ +/************************************************************************ + * Circuit models have unique names, return the number of errors + * If not found, we give an error + ***********************************************************************/ static size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { size_t num_err = 0; @@ -102,7 +119,10 @@ size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { return num_err; } -/* A generic function to check the port list of a circuit model in a given type */ +/************************************************************************ + * A generic function to check the port list of a circuit model in a given type + * If not found, we give an error + ***********************************************************************/ static size_t check_circuit_model_required(const CircuitLibrary& circuit_lib, const enum e_spice_model_type& circuit_model_type_to_check) { @@ -120,7 +140,92 @@ size_t check_circuit_model_required(const CircuitLibrary& circuit_lib, return num_err; } -/* A generic function to check the port list of a circuit model in a given type */ +/************************************************************************ + * A generic function to check the port list of a circuit model in a given type + * If not found, we give an error + ***********************************************************************/ +size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const std::vector& port_types_to_check) { + size_t num_err = 0; + + for (const auto& port_type: port_types_to_check) { + if (0 == circuit_lib.ports_by_type(circuit_model, port_type).size()) { + vpr_printf(TIO_MESSAGE_ERROR, + "%s circuit model(name=%s) does not have %s port\n", + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], + circuit_lib.circuit_model_name(circuit_model).c_str(), + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); + /* Incremental the counter for errors */ + num_err++; + } + } + + return num_err; +} + +/************************************************************************ + * A generic function to check the port size of a given circuit model + * if the port size does not match, we give an error + ***********************************************************************/ +size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitPortId& circuit_port, + const size_t& port_size_to_check) { + + size_t num_err = 0; + + if (port_size_to_check != circuit_lib.port_size(circuit_model, circuit_port)) { + vpr_printf(TIO_MESSAGE_ERROR, + "Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n", + circuit_lib.circuit_model_name(circuit_model).c_str(), + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_model, circuit_port))], + port_size_to_check); + /* Incremental the counter for errors */ + num_err++; + } + + return num_err; +} + +/************************************************************************ + * A generic function to check the port size of a given circuit model + * if the number of ports in the given type does not match, we give an error + * for each port, if the port size does not match, we give an error + ***********************************************************************/ +size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const enum e_spice_model_port_type& port_type_to_check, + const size_t& num_ports_to_check, + const size_t& port_size_to_check, + const bool& include_global_ports) { + + size_t num_err = 0; + + std::vector ports = circuit_lib.ports_by_type(circuit_model, port_type_to_check, include_global_ports); + if (num_ports_to_check != ports.size()) { + vpr_printf(TIO_MESSAGE_ERROR, + "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", + num_ports_to_check, + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], + ports.size()); + num_err++; + } + for (const auto& port : ports) { + num_err += check_one_circuit_model_port_size_required(circuit_lib, + circuit_model, + port, port_size_to_check); + } + + return num_err; +} + +/************************************************************************ + * A generic function to check the port list of circuit models in a given type + * If not found, we give an error + ***********************************************************************/ static size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, const enum e_spice_model_type& circuit_model_type_to_check, @@ -128,22 +233,119 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, size_t num_err = 0; for (const auto& id : circuit_lib.circuit_models_by_type(circuit_model_type_to_check)) { - for (const auto& port_type: port_types_to_check) { - if (0 == circuit_lib.ports_by_type(id, port_type).size()) { - vpr_printf(TIO_MESSAGE_ERROR, - "%s circuit model(name=%s) does not have %s port\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)], - circuit_lib.circuit_model_name(id).c_str(), - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); - /* Incremental the counter for errors */ - num_err++; - } - } + num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check); } return num_err; } +/************************************************************************ + * A generic function to find the default circuit model with a given type + * If not found, we give an error + ***********************************************************************/ +static +size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib, + const enum e_spice_model_type& circuit_model_type) { + size_t num_err = 0; + + if (CIRCUIT_MODEL_OPEN_ID == circuit_lib.default_circuit_model(circuit_model_type)) { + vpr_printf(TIO_MESSAGE_ERROR, + "A default circuit model for the type %s! Try to define it in your architecture file!\n", + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]); + exit(1); + } + + return num_err; +} + +/************************************************************************ + * A function to check the port map of FF circuit model + ***********************************************************************/ +size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + size_t num_err = 0; + + /* Check the type of circuit model */ + VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.circuit_model_type(circuit_model)); + /* Check if we have D, Set and Reset */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_INPUT, + 3, 1, false); + /* Check if we have a clock */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_CLOCK, + 1, 1, false); + + + /* Check if we have output */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_OUTPUT, + 1, 1, false); + + return num_err; +} + +/************************************************************************ + * A function to check the port map of SCFF circuit model + ***********************************************************************/ +size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + size_t num_err = 0; + + /* Check the type of circuit model */ + VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.circuit_model_type(circuit_model)); + + /* Check if we have D, Set and Reset */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_INPUT, + 1, 1, false); + /* Check if we have a clock */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_CLOCK, + 1, 1, true); + + + /* Check if we have output */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_OUTPUT, + 2, 1, false); + + return num_err; +} + +/************************************************************************ + * A function to check the port map of SRAM circuit model + ***********************************************************************/ +size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const bool& check_blwl) { + size_t num_err = 0; + + /* Check the type of circuit model */ + VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.circuit_model_type(circuit_model)); + + /* Check if we has 1 output with size 2 */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_OUTPUT, + 1, 2, false); + /* basic check finished here */ + if (false == check_blwl) { + return num_err; + } + + /* If bl and wl are required, check their existence */ + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_BL, + 1, 1, false); + + num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, + SPICE_MODEL_PORT_WL, + 1, 1, false); + + return num_err; +} + + /************************************************************************ * Check points to make sure we have a valid circuit library * Detailed checkpoints: @@ -151,6 +353,12 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, * 2. Circuit models have unique prefix * 3. Check IOPADs have input and output ports * 4. Check MUXes has been defined and has input and output ports + * 5. We must have at least one SRAM or SCFF + * 6. SRAM must have at least an input and an output ports + * 7. SCFF must have at least a clock, an input and an output ports + * 8. FF must have at least a clock, an input and an output ports + * 9. LUT must have at least an input, an output and a SRAM ports + * 10. We must have default circuit models for these types: MUX, channel wires and wires ***********************************************************************/ void check_circuit_library(const CircuitLibrary& circuit_lib) { size_t num_err = 0; @@ -212,7 +420,7 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SRAM, sram_port_types_required); - /* 7. SCFF must have at least an input and an output ports*/ + /* 7. SCFF must have at least a clock, an input and an output ports*/ std::vector scff_port_types_required; scff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); scff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); @@ -220,7 +428,7 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SCFF, scff_port_types_required); - /* 8. FF must have at least an input and an output ports*/ + /* 8. FF must have at least a clock, an input and an output ports*/ std::vector ff_port_types_required; ff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); ff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); @@ -228,7 +436,7 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_FF, ff_port_types_required); - /* 9. LUY must have at least an input, an output and a SRAM ports*/ + /* 9. LUT must have at least an input, an output and a SRAM ports*/ std::vector lut_port_types_required; lut_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); lut_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); @@ -236,6 +444,11 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_LUT, lut_port_types_required); + /* 10. We must have default circuit models for these types: MUX, channel wires and wires */ + num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_MUX); + num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_CHAN_WIRE); + num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE); + /* If we have any errors, exit */ vpr_printf(TIO_MESSAGE_ERROR, "Finished checking circuit library with %d errors!\n", diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h index 4dd9d1307..f70133697 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h @@ -50,6 +50,32 @@ #include "circuit_library.h" /* Check points to make sure we have a valid circuit library */ +size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const std::vector& port_types_to_check); + +size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitPortId& circuit_port, + const size_t& port_size_to_check); + +size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const enum e_spice_model_port_type& port_type_to_check, + const size_t& num_ports_to_check, + const size_t& port_size_to_check, + const bool& include_global_ports); + +size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const bool& check_blwl); + void check_circuit_library(const CircuitLibrary& circuit_lib); #endif diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index e8487bdff..6bd5aab07 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -88,6 +88,29 @@ std::vector CircuitLibrary::ports_by_type(const CircuitModelId& c return port_ids; } +/* Find the ports of a circuit model by a given type, return a list of qualified ports + * with an option to include/exclude global ports + */ +std::vector CircuitLibrary::ports_by_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_port_type& type, + const bool& include_global_port) const { + std::vector port_ids; + for (const auto& port_id : ports(circuit_model_id)) { + /* We skip unmatched ports */ + if ( type != port_type(circuit_model_id, port_id) ) { + continue; + } + /* We skip global ports if specified */ + if ( (false == include_global_port) + && (true == port_is_global(circuit_model_id, port_id)) ) { + continue; + } + port_ids.push_back(port_id); + } + return port_ids; +} + + /* Create a vector for all the ports whose directionality is input * This includes all the ports other than whose types are OUPUT or INOUT */ @@ -140,96 +163,106 @@ size_t CircuitLibrary::num_circuit_models() const { /* Access the type of a circuit model */ enum e_spice_model_type CircuitLibrary::circuit_model_type(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return circuit_model_types_[circuit_model_id]; } /* Access the name of a circuit model */ std::string CircuitLibrary::circuit_model_name(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return circuit_model_names_[circuit_model_id]; } /* Access the prefix of a circuit model */ std::string CircuitLibrary::circuit_model_prefix(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return circuit_model_prefix_[circuit_model_id]; } /* Access the path + file of user-defined verilog netlist of a circuit model */ std::string CircuitLibrary::circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return circuit_model_verilog_netlists_[circuit_model_id]; } /* Access the path + file of user-defined spice netlist of a circuit model */ std::string CircuitLibrary::circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return circuit_model_spice_netlists_[circuit_model_id]; } /* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */ bool CircuitLibrary::circuit_model_is_default(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return circuit_model_is_default_[circuit_model_id]; } /* Access the dump_structural_verilog flag of a circuit model */ bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return dump_structural_verilog_[circuit_model_id]; } /* Access the dump_explicit_port_map flag of a circuit model */ bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return dump_explicit_port_map_[circuit_model_id]; } /* Access the design technology type of a circuit model */ enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return design_tech_types_[circuit_model_id]; } /* Access the is_power_gated flag of a circuit model */ bool CircuitLibrary::is_power_gated(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return is_power_gated_[circuit_model_id]; } /* Return a flag showing if inputs are buffered for a circuit model */ bool CircuitLibrary::is_input_buffered(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return buffer_existence_[circuit_model_id][INPUT]; } /* Return a flag showing if outputs are buffered for a circuit model */ bool CircuitLibrary::is_output_buffered(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return buffer_existence_[circuit_model_id][OUTPUT]; } /* Return a flag showing if intermediate stages of a LUT are buffered for a circuit model */ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate the circuit model type is LUT */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); return buffer_existence_[circuit_model_id][LUT_INTER_BUFFER]; } +/* Return the multiplex structure of a circuit model */ +enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + return mux_structure_[circuit_model_id]; +} + /************************************************************************ * Public Accessors : Basic data query on Circuit Porst ***********************************************************************/ @@ -237,7 +270,7 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ /* identify if this port is an input port */ bool CircuitLibrary::is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_model_id and circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, circuit_port_id)) && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, circuit_port_id)) ); @@ -246,7 +279,7 @@ bool CircuitLibrary::is_input_port(const CircuitModelId& circuit_model_id, const /* identify if this port is an output port */ bool CircuitLibrary::is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_model_id and circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, circuit_port_id)) || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, circuit_port_id)) ); @@ -255,7 +288,7 @@ bool CircuitLibrary::is_output_port(const CircuitModelId& circuit_model_id, cons /* Given a name and return the port id */ CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const std::string& name) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Walk through the ports and try to find a matched name */ CircuitPortId ret = CIRCUIT_PORT_OPEN_ID; size_t num_found = 0; @@ -267,22 +300,34 @@ CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const num_found++; } /* Make sure we will not find two ports with the same name */ - VTR_ASSERT_SAFE( (0 == num_found) || (1 == num_found) ); + VTR_ASSERT( (0 == num_found) || (1 == num_found) ); return ret; } /* Access the type of a port of a circuit model */ size_t CircuitLibrary::num_ports(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return port_ids_[circuit_model_id].size(); } +/* Access the type of a port of a circuit model + * with an option to include/exclude global ports + * when counting + */ +size_t CircuitLibrary::num_ports_by_type(const CircuitModelId& circuit_model_id, + const enum e_spice_model_port_type& port_type, + const bool& include_global_port) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + return ports_by_type(circuit_model_id, port_type, include_global_port).size(); +} + /* Access the type of a port of a circuit model */ enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_types_[circuit_model_id][circuit_port_id]; } @@ -290,7 +335,7 @@ enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& cir size_t CircuitLibrary::port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_sizes_[circuit_model_id][circuit_port_id]; } @@ -298,7 +343,7 @@ size_t CircuitLibrary::port_size(const CircuitModelId& circuit_model_id, std::string CircuitLibrary::port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_prefix_[circuit_model_id][circuit_port_id]; } @@ -306,7 +351,7 @@ std::string CircuitLibrary::port_prefix(const CircuitModelId& circuit_model_id, std::string CircuitLibrary::port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_lib_names_[circuit_model_id][circuit_port_id]; } @@ -314,7 +359,7 @@ std::string CircuitLibrary::port_lib_name(const CircuitModelId& circuit_model_id std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_inv_prefix_[circuit_model_id][circuit_port_id]; } @@ -322,7 +367,7 @@ std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_ size_t CircuitLibrary::port_default_value(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_default_values_[circuit_model_id][circuit_port_id]; } @@ -331,7 +376,7 @@ size_t CircuitLibrary::port_default_value(const CircuitModelId& circuit_model_id bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_is_mode_select_[circuit_model_id][circuit_port_id]; } @@ -339,7 +384,7 @@ bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, bool CircuitLibrary::port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_is_global_[circuit_model_id][circuit_port_id]; } @@ -347,7 +392,7 @@ bool CircuitLibrary::port_is_global(const CircuitModelId& circuit_model_id, bool CircuitLibrary::port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_is_reset_[circuit_model_id][circuit_port_id]; } @@ -355,7 +400,7 @@ bool CircuitLibrary::port_is_reset(const CircuitModelId& circuit_model_id, bool CircuitLibrary::port_is_set(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_is_set_[circuit_model_id][circuit_port_id]; } @@ -363,7 +408,7 @@ bool CircuitLibrary::port_is_set(const CircuitModelId& circuit_model_id, bool CircuitLibrary::port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_is_config_enable_[circuit_model_id][circuit_port_id]; } @@ -371,7 +416,7 @@ bool CircuitLibrary::port_is_config_enable(const CircuitModelId& circuit_model_i bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return port_is_prog_[circuit_model_id][circuit_port_id]; } @@ -379,6 +424,12 @@ bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, /************************************************************************ * Public Accessors : Methods to find circuit model ***********************************************************************/ +/* Find a circuit model by a given name and return its id */ +CircuitModelId CircuitLibrary::circuit_model(const char* name) const { + std::string name_str(name); + return circuit_model(name_str); +} + /* Find a circuit model by a given name and return its id */ CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { CircuitModelId ret = CIRCUIT_MODEL_OPEN_ID; @@ -403,7 +454,9 @@ CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { /* Get the CircuitModelId of a default circuit model with a given type */ CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_type& type) const { /* Default circuit model id is the first element by type in the fast look-up */ - return circuit_model_lookup_[size_t(type)].front(); + CircuitModelId default_id = circuit_model_lookup_[size_t(type)].front(); + VTR_ASSERT(true == circuit_model_is_default(default_id)); + return default_id; } /************************************************************************ @@ -414,8 +467,8 @@ CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& circuit_model_id, const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin) { /* validate the circuit_pin_id */ - VTR_ASSERT_SAFE(valid_circuit_pin_id(circuit_model_id, from_port, from_pin)); - VTR_ASSERT_SAFE(valid_circuit_pin_id(circuit_model_id, to_port, to_pin)); + VTR_ASSERT(valid_circuit_pin_id(circuit_model_id, from_port, from_pin)); + VTR_ASSERT(valid_circuit_pin_id(circuit_model_id, to_port, to_pin)); /* Walk through the edge list until we find the one */ for (auto edge : edge_ids_[circuit_model_id]) { if ( (from_port == edge_src_port_ids_[circuit_model_id][edge]) @@ -551,7 +604,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() { void CircuitLibrary::set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_types_[circuit_model_id] = type; /* Build the fast look-up for circuit models */ build_circuit_model_lookup(); @@ -561,7 +614,7 @@ void CircuitLibrary::set_circuit_model_type(const CircuitModelId& circuit_model_ /* Set the name of a Circuit Model */ void CircuitLibrary::set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_names_[circuit_model_id] = name; return; } @@ -569,7 +622,7 @@ void CircuitLibrary::set_circuit_model_name(const CircuitModelId& circuit_model_ /* Set the prefix of a Circuit Model */ void CircuitLibrary::set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_prefix_[circuit_model_id] = prefix; return; } @@ -577,7 +630,7 @@ void CircuitLibrary::set_circuit_model_prefix(const CircuitModelId& circuit_mode /* Set the verilog_netlist of a Circuit Model */ void CircuitLibrary::set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_verilog_netlists_[circuit_model_id] = verilog_netlist; return; } @@ -585,7 +638,7 @@ void CircuitLibrary::set_circuit_model_verilog_netlist(const CircuitModelId& cir /* Set the spice_netlist of a Circuit Model */ void CircuitLibrary::set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_spice_netlists_[circuit_model_id] = spice_netlist; return; } @@ -593,7 +646,7 @@ void CircuitLibrary::set_circuit_model_spice_netlist(const CircuitModelId& circu /* Set the is_default of a Circuit Model */ void CircuitLibrary::set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_is_default_[circuit_model_id] = is_default; return; } @@ -601,7 +654,7 @@ void CircuitLibrary::set_circuit_model_is_default(const CircuitModelId& circuit_ /* Set the dump_structural_verilog of a Circuit Model */ void CircuitLibrary::set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); dump_structural_verilog_[circuit_model_id] = dump_structural_verilog; return; } @@ -609,7 +662,7 @@ void CircuitLibrary::set_circuit_model_dump_structural_verilog(const CircuitMode /* Set the dump_explicit_port_map of a Circuit Model */ void CircuitLibrary::set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); dump_explicit_port_map_[circuit_model_id] = dump_explicit_port_map; return; } @@ -617,7 +670,7 @@ void CircuitLibrary::set_circuit_model_dump_explicit_port_map(const CircuitModel /* Set the type of design technology of a Circuit Model */ void CircuitLibrary::set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); design_tech_types_[circuit_model_id] = design_tech_type; return; } @@ -625,7 +678,7 @@ void CircuitLibrary::set_circuit_model_design_tech_type(const CircuitModelId& ci /* Set the power-gated flag of a Circuit Model */ void CircuitLibrary::set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); is_power_gated_[circuit_model_id] = is_power_gated; return; } @@ -650,9 +703,9 @@ void CircuitLibrary::set_circuit_model_output_buffer(const CircuitModelId& circu void CircuitLibrary::set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); /* Just call the base function and give the proper type */ set_circuit_model_buffer(circuit_model_id, LUT_INPUT_BUFFER, existence, circuit_model_name); return; @@ -662,9 +715,9 @@ void CircuitLibrary::set_circuit_model_lut_input_buffer(const CircuitModelId& ci void CircuitLibrary::set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); /* Just call the base function and give the proper type */ set_circuit_model_buffer(circuit_model_id, LUT_INPUT_INVERTER, existence, circuit_model_name); return; @@ -674,9 +727,9 @@ void CircuitLibrary::set_circuit_model_lut_input_inverter(const CircuitModelId& void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, const bool& existence, const std::string& circuit_model_name) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); /* Just call the base function and give the proper type */ set_circuit_model_buffer(circuit_model_id, LUT_INTER_BUFFER, existence, circuit_model_name); return; @@ -685,7 +738,7 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitMode void CircuitLibrary::set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, const std::string& location_map) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); buffer_location_maps_[circuit_model_id][LUT_INTER_BUFFER] = location_map; return; } @@ -694,7 +747,7 @@ void CircuitLibrary::set_circuit_model_lut_intermediate_buffer_location_map(cons /* Set pass-gate logic information of a circuit model */ void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); pass_gate_logic_circuit_model_names_[circuit_model_id] = circuit_model_name; return; } @@ -702,7 +755,7 @@ void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& cir /* Add a port to a circuit model */ CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Create a port id */ CircuitPortId circuit_port_id = CircuitPortId(port_ids_[circuit_model_id].size()); /* Update the id list */ @@ -742,7 +795,7 @@ void CircuitLibrary::set_port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const enum e_spice_model_port_type& port_type) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_types_[circuit_model_id][circuit_port_id] = port_type; /* Build the fast look-up for circuit model ports */ build_circuit_model_port_lookup(circuit_model_id); @@ -754,7 +807,7 @@ void CircuitLibrary::set_port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& port_size) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_sizes_[circuit_model_id][circuit_port_id] = port_size; return; } @@ -764,7 +817,7 @@ void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_prefix_[circuit_model_id][circuit_port_id] = port_prefix; return; } @@ -774,7 +827,7 @@ void CircuitLibrary::set_port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const std::string& lib_name) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_lib_names_[circuit_model_id][circuit_port_id] = lib_name; return; } @@ -784,7 +837,7 @@ void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const std::string& inv_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_inv_prefix_[circuit_model_id][circuit_port_id] = inv_prefix; return; } @@ -794,7 +847,7 @@ void CircuitLibrary::set_port_default_value(const CircuitModelId& circuit_model_ const CircuitPortId& circuit_port_id, const size_t& default_value) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_default_values_[circuit_model_id][circuit_port_id] = default_value; return; } @@ -804,7 +857,7 @@ void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& circuit_model const CircuitPortId& circuit_port_id, const bool& is_mode_select) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_is_mode_select_[circuit_model_id][circuit_port_id] = is_mode_select; return; } @@ -814,7 +867,7 @@ void CircuitLibrary::set_port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const bool& is_global) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_is_global_[circuit_model_id][circuit_port_id] = is_global; return; } @@ -824,7 +877,7 @@ void CircuitLibrary::set_port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const bool& is_reset) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_is_reset_[circuit_model_id][circuit_port_id] = is_reset; return; } @@ -834,7 +887,7 @@ void CircuitLibrary::set_port_is_set(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const bool& is_set) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_is_set_[circuit_model_id][circuit_port_id] = is_set; return; } @@ -844,7 +897,7 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& circuit_mod const CircuitPortId& circuit_port_id, const bool& is_config_enable) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_is_config_enable_[circuit_model_id][circuit_port_id] = is_config_enable; return; } @@ -854,7 +907,7 @@ void CircuitLibrary::set_port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const bool& is_prog) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_is_prog_[circuit_model_id][circuit_port_id] = is_prog; return; } @@ -864,7 +917,7 @@ void CircuitLibrary::set_port_circuit_model_name(const CircuitModelId& circuit_m const CircuitPortId& circuit_port_id, const std::string& circuit_model_name) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_circuit_model_names_[circuit_model_id][circuit_port_id] = circuit_model_name; return; } @@ -874,7 +927,7 @@ void CircuitLibrary::set_port_circuit_model_id(const CircuitModelId& circuit_mod const CircuitPortId& circuit_port_id, const CircuitModelId& port_circuit_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_circuit_model_ids_[circuit_model_id][circuit_port_id] = port_circuit_model_id; return; } @@ -884,7 +937,7 @@ void CircuitLibrary::set_port_inv_circuit_model_name(const CircuitModelId& circu const CircuitPortId& circuit_port_id, const std::string& inv_circuit_model_name) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_inv_circuit_model_names_[circuit_model_id][circuit_port_id] = inv_circuit_model_name; return; } @@ -894,7 +947,7 @@ void CircuitLibrary::set_port_inv_circuit_model_id(const CircuitModelId& circuit const CircuitPortId& circuit_port_id, const CircuitModelId& inv_circuit_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_inv_circuit_model_ids_[circuit_model_id][circuit_port_id] = inv_circuit_model_id; return; } @@ -904,7 +957,7 @@ void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& circuit_model_ const CircuitPortId& circuit_port_id, const std::string& tri_state_map) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); port_tri_state_maps_[circuit_model_id][circuit_port_id] = tri_state_map; return; } @@ -914,9 +967,9 @@ void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& circuit_model const CircuitPortId& circuit_port_id, const size_t& lut_frac_level) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); port_lut_frac_level_[circuit_model_id][circuit_port_id] = lut_frac_level; return; } @@ -926,9 +979,9 @@ void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& circuit_mode const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); port_lut_output_masks_[circuit_model_id][circuit_port_id] = lut_output_masks; return; } @@ -938,9 +991,9 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz) { /* validate the circuit_port_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); /* Make sure this is a SRAM port */ - VTR_ASSERT_SAFE(SPICE_MODEL_PORT_SRAM == port_type(circuit_model_id, circuit_port_id)); + VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(circuit_model_id, circuit_port_id)); port_sram_orgz_[circuit_model_id][circuit_port_id] = sram_orgz; return; } @@ -954,7 +1007,7 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, void CircuitLibrary::add_delay_info(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Check the range of vector */ if (size_t(delay_type) >= delay_types_[circuit_model_id].size()) { /* Resize */ @@ -971,9 +1024,9 @@ void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& circuit_model const enum spice_model_delay_type& delay_type, const std::string& in_port_names) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Validate delay_type */ - VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); delay_in_port_names_[circuit_model_id][size_t(delay_type)] = in_port_names; return; } @@ -982,9 +1035,9 @@ void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& circuit_mode const enum spice_model_delay_type& delay_type, const std::string& out_port_names) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Validate delay_type */ - VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); delay_out_port_names_[circuit_model_id][size_t(delay_type)] = out_port_names; return; } @@ -993,9 +1046,9 @@ void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type, const std::string& delay_values) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Validate delay_type */ - VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); delay_values_[circuit_model_id][size_t(delay_type)] = delay_values; return; } @@ -1004,9 +1057,9 @@ void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_buffer_type& buffer_type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); buffer_types_[circuit_model_id] = buffer_type; return; } @@ -1014,9 +1067,9 @@ void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id, const float& buffer_size) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); buffer_sizes_[circuit_model_id] = buffer_size; return; } @@ -1024,9 +1077,9 @@ void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& circuit_model_id, const size_t& num_levels) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); buffer_num_levels_[circuit_model_id] = num_levels; return; } @@ -1034,9 +1087,9 @@ void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& circuit_model_i void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, const size_t& f_per_stage) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); buffer_f_per_stage_[circuit_model_id] = f_per_stage; return; } @@ -1045,9 +1098,9 @@ void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& circuit_model_ void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); pass_gate_logic_types_[circuit_model_id] = pass_gate_logic_type; return; } @@ -1055,9 +1108,9 @@ void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_mode void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, const float& nmos_size) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); pass_gate_logic_sizes_[circuit_model_id].set_x(nmos_size); return; } @@ -1065,9 +1118,9 @@ void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, const float& pmos_size) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT_SAFE(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); pass_gate_logic_sizes_[circuit_model_id].set_y(pmos_size); return; } @@ -1076,9 +1129,10 @@ void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit void CircuitLibrary::set_mux_structure(const CircuitModelId& circuit_model_id, const enum e_spice_model_structure& mux_structure) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX */ - VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); mux_structure_[circuit_model_id] = mux_structure; return; } @@ -1086,9 +1140,10 @@ void CircuitLibrary::set_mux_structure(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_mux_num_levels(const CircuitModelId& circuit_model_id, const size_t& num_levels) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX */ - VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); mux_num_levels_[circuit_model_id] = num_levels; return; } @@ -1096,9 +1151,10 @@ void CircuitLibrary::set_mux_num_levels(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& circuit_model_id, const size_t& const_input_value) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX */ - VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); mux_const_input_values_[circuit_model_id] = const_input_value; return; } @@ -1106,9 +1162,10 @@ void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& circuit_mod void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, const bool& use_local_encoder) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX */ - VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); mux_use_local_encoder_[circuit_model_id] = use_local_encoder; return; } @@ -1116,9 +1173,10 @@ void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& circuit_mod void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, const bool& use_advanced_rram_design) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX */ - VTR_ASSERT_SAFE(SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate that the type of this circuit_model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); mux_use_advanced_rram_design_[circuit_model_id] = use_advanced_rram_design; return; } @@ -1127,9 +1185,9 @@ void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& circ void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_id, const bool& is_fracturable) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be LUT */ - VTR_ASSERT_SAFE(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); lut_is_fracturable_[circuit_model_id] = is_fracturable; return; } @@ -1138,9 +1196,9 @@ void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_ void CircuitLibrary::set_gate_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_gate_type& gate_type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be GATE */ - VTR_ASSERT_SAFE(SPICE_MODEL_GATE == circuit_model_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_GATE == circuit_model_type(circuit_model_id)); gate_types_[circuit_model_id] = gate_type; return; } @@ -1150,9 +1208,9 @@ void CircuitLibrary::set_gate_type(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id, const float& rlrs) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); rram_res_[circuit_model_id].set_x(rlrs); return; } @@ -1160,9 +1218,9 @@ void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_rram_rhrs(const CircuitModelId& circuit_model_id, const float& rhrs) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); rram_res_[circuit_model_id].set_y(rhrs); return; } @@ -1170,9 +1228,9 @@ void CircuitLibrary::set_rram_rhrs(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, const float& wprog_set_nmos) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); wprog_set_[circuit_model_id].set_x(wprog_set_nmos); return; } @@ -1180,9 +1238,9 @@ void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& circuit_model void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, const float& wprog_set_pmos) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); wprog_set_[circuit_model_id].set_y(wprog_set_pmos); return; } @@ -1190,9 +1248,9 @@ void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& circuit_model void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, const float& wprog_reset_nmos) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); wprog_reset_[circuit_model_id].set_x(wprog_reset_nmos); return; } @@ -1200,9 +1258,9 @@ void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& circuit_mod void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, const float& wprog_reset_pmos) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); wprog_reset_[circuit_model_id].set_y(wprog_reset_pmos); return; } @@ -1211,9 +1269,9 @@ void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& circuit_mod void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, const enum e_wire_model_type& wire_type) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_types_[circuit_model_id] = wire_type; return; @@ -1222,9 +1280,9 @@ void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, const float& r_val) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_rc_[circuit_model_id].set_x(r_val); return; @@ -1233,9 +1291,9 @@ void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, const float& c_val) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_rc_[circuit_model_id].set_y(c_val); return; @@ -1244,9 +1302,9 @@ void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, const size_t& num_level) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT_SAFE( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) + VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_num_levels_[circuit_model_id] = num_level; return; @@ -1263,7 +1321,7 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Check the range of vector */ if (size_t(buffer_type) >= buffer_existence_[circuit_model_id].size()) { /* Resize and assign values */ @@ -1285,7 +1343,7 @@ void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_mode */ void CircuitLibrary::link_port_circuit_model(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Walk through each ports, get the port id and find the circuit model id by name */ for (auto& port_id : ports(circuit_model_id)) { /* Bypass empty name */ @@ -1303,7 +1361,7 @@ void CircuitLibrary::link_port_circuit_model(const CircuitModelId& circuit_model */ void CircuitLibrary::link_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Walk through each ports, get the port id and find the circuit model id by name */ for (auto& port_id : ports(circuit_model_id)) { /* Bypass empty name */ @@ -1328,7 +1386,7 @@ void CircuitLibrary::link_port_circuit_models(const CircuitModelId& circuit_mode */ void CircuitLibrary::link_buffer_circuit_model(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Get the circuit model id by name, skip those with empty names*/ for (size_t buffer_id = 0; buffer_id < buffer_circuit_model_names_[circuit_model_id].size(); ++buffer_id) { if (true == buffer_circuit_model_names_[circuit_model_id][buffer_id].empty()) { @@ -1345,7 +1403,7 @@ void CircuitLibrary::link_buffer_circuit_model(const CircuitModelId& circuit_mod */ void CircuitLibrary::link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Get the circuit model id by name, skip those with empty names*/ if (true == pass_gate_logic_circuit_model_names_[circuit_model_id].empty()) { return; @@ -1412,7 +1470,7 @@ void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Create an edge in the edge id list */ CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[circuit_model_id].size()); @@ -1455,8 +1513,8 @@ void CircuitLibrary::set_edge_delay(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type, const float& delay_value) { /* validate the circuit_edge_id */ - VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - VTR_ASSERT_SAFE(valid_delay_type(circuit_model_id, delay_type)); + VTR_ASSERT(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); + VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(delay_type)] = delay_value; return; @@ -1465,7 +1523,7 @@ void CircuitLibrary::set_edge_delay(const CircuitModelId& circuit_model_id, /* Annotate delay values on a timing graph */ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* Go one delay_info by another */ for (const auto& delay_type : delay_types_[circuit_model_id]) { /* Parse the input port names and output names. @@ -1484,7 +1542,7 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model /* Try to find a port by the given name */ CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port_id); + VTR_ASSERT(CIRCUIT_PORT_OPEN_ID != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as @@ -1492,12 +1550,12 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model size_t port_width = port_size(circuit_model_id, port_id); port_info.set_width(port_width); } else { - VTR_ASSERT_SAFE(1 == port_info.get_width()); + VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT_SAFE(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); /* This must be an input port! */ - VTR_ASSERT_SAFE(true == is_input_port(circuit_model_id, port_id)); + VTR_ASSERT(true == is_input_port(circuit_model_id, port_id)); /* Push to */ input_port_ids.push_back(port_id); input_pin_ids.push_back(port_info.get_lsb()); @@ -1513,7 +1571,7 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model /* Try to find a port by the given name */ CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port_id); + VTR_ASSERT(CIRCUIT_PORT_OPEN_ID != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as @@ -1521,12 +1579,12 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model size_t port_width = port_size(circuit_model_id, port_id); port_info.set_width(port_width); } else { - VTR_ASSERT_SAFE(1 == port_info.get_width()); + VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT_SAFE(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); /* This must be an output port! */ - VTR_ASSERT_SAFE(true == is_output_port(circuit_model_id, port_id)); + VTR_ASSERT(true == is_output_port(circuit_model_id, port_id)); /* Push to */ output_port_ids.push_back(port_id); output_pin_ids.push_back(port_info.get_lsb()); @@ -1536,10 +1594,10 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model PortDelayParser port_delay_parser(delay_values_[circuit_model_id][size_t(delay_type)]); /* Make sure the delay matrix size matches */ - VTR_ASSERT_SAFE(port_delay_parser.height() == output_port_ids.size()); - VTR_ASSERT_SAFE(port_delay_parser.height() == output_pin_ids.size()); - VTR_ASSERT_SAFE(port_delay_parser.width() == input_port_ids.size()); - VTR_ASSERT_SAFE(port_delay_parser.width() == input_pin_ids.size()); + VTR_ASSERT(port_delay_parser.height() == output_port_ids.size()); + VTR_ASSERT(port_delay_parser.height() == output_pin_ids.size()); + VTR_ASSERT(port_delay_parser.width() == input_port_ids.size()); + VTR_ASSERT(port_delay_parser.width() == input_pin_ids.size()); /* Configure timing graph */ for (size_t i = 0; i < port_delay_parser.height(); ++i) { @@ -1549,7 +1607,7 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model input_port_ids[j], input_pin_ids[j], output_port_ids[i], output_pin_ids[i]); /* make sure we have an valid edge_id */ - VTR_ASSERT_SAFE(true == valid_circuit_edge_id(circuit_model_id, edge_id)); + VTR_ASSERT(true == valid_circuit_edge_id(circuit_model_id, edge_id)); set_edge_delay(circuit_model_id, edge_id, delay_type, delay_value); } @@ -1617,25 +1675,25 @@ bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_ bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); } bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); return ( size_t(pin_id) < port_size(circuit_model_id, circuit_port_id) ); } bool CircuitLibrary::valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return ( size_t(delay_type) < delay_types_[circuit_model_id].size() ) && ( delay_type == delay_types_[circuit_model_id][size_t(delay_type)] ); } bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); return ( size_t(circuit_edge_id) < edge_ids_[circuit_model_id].size() ) && ( circuit_edge_id == edge_ids_[circuit_model_id][circuit_edge_id] ); } @@ -1649,7 +1707,7 @@ void CircuitLibrary::invalidate_circuit_model_lookup() const { /* Empty fast lookup for circuit ports for a circuit_model */ void CircuitLibrary::invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); circuit_model_port_lookup_[size_t(circuit_model_id)].clear(); return; } @@ -1657,7 +1715,7 @@ void CircuitLibrary::invalidate_circuit_model_port_lookup(const CircuitModelId& /* Clear all the data structure related to the timing graph */ void CircuitLibrary::invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { /* validate the circuit_model_id */ - VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); edge_ids_[circuit_model_id].clear(); for (const auto& port_id : ports(circuit_model_id)) { diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index b655730d0..0b3ed3c06 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -221,6 +221,7 @@ class CircuitLibrary { circuit_port_range ports(const CircuitModelId& circuit_model_id) const; std::vector circuit_models_by_type(const enum e_spice_model_type& type) const; std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type) const; + std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector input_ports(const CircuitModelId& circuit_model_id) const; std::vector output_ports(const CircuitModelId& circuit_model_id) const; std::vector pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -239,11 +240,13 @@ class CircuitLibrary { bool is_input_buffered(const CircuitModelId& circuit_model_id) const; bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; + enum e_spice_model_structure mux_structure(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; CircuitPortId port(const CircuitModelId& circuit_model_id, const std::string& name) const; size_t num_ports(const CircuitModelId& circuit_model_id) const; + size_t num_ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -257,6 +260,7 @@ class CircuitLibrary { bool port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Methods to find circuit model */ + CircuitModelId circuit_model(const char* name) const; CircuitModelId circuit_model(const std::string& name) const; CircuitModelId default_circuit_model(const enum e_spice_model_type& type) const; public: /* Public Accessors: Timing graph */ diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h index 0ad9790dd..6d72b2242 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h @@ -89,6 +89,8 @@ enum e_spice_model_structure { SPICE_MODEL_STRUCTURE_CROSSBAR, NUM_CIRCUIT_MODEL_STRUCTURE_TYPES }; +/* Strings correspond to each type of mux structure */ +constexpr std::array CIRCUIT_MODEL_STRUCTURE_TYPE_STRING = {{"TREE-LIKE", "ONE-LEVEL", "MULTI-LEVEL", "CROSSBAR"}}; enum e_spice_model_buffer_type { SPICE_MODEL_BUF_INV, @@ -138,6 +140,7 @@ enum e_sram_orgz { SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */ NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES }; +constexpr std::array CIRCUIT_MODEL_SRAM_ORGZ_TYPE_STRING = {{"STANDALONE", "SCAN-CHAIN", "MEMORY_BANK", "LOCAL_ENCODER"}}; #endif diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index 1c333eb70..42ecbb3f2 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -396,6 +396,7 @@ struct s_spice_mux_model { struct s_sram_inf_orgz { char* spice_model_name; // Xifan TANG: Spice Support t_spice_model* spice_model; // Xifan TANG: Spice Support + CircuitModelId circuit_model; enum e_sram_orgz type; }; diff --git a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h index 24dee9ea8..81de09866 100644 --- a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h +++ b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h @@ -265,6 +265,7 @@ struct s_port { /* FPGA_SPICE_model support: * mapped SPICE model port */ t_spice_model_port* spice_model_port; + CircuitPortId circuit_model_port; char* physical_mode_pin; int physical_mode_pin_rotate_offset; /* The pin number will rotate by an offset unit when mapping to physical modes */ int phy_mode_pin_rotate_offset_acc; /* The pin number will rotate by an offset unit when mapping to physical modes */ @@ -341,6 +342,7 @@ struct s_interconnect { /* Xifan TANG: SPICE Support*/ char* spice_model_name; t_spice_model* spice_model; + CircuitModelId circuit_model; int fan_in; int fan_out; int num_mux; @@ -658,6 +660,7 @@ struct s_pb_type { char* physical_mode_name; char* spice_model_name; t_spice_model* spice_model; + CircuitModelId circuit_model; char* mode_bits; /* Mode bits to select */ int spice_model_sram_offset; char* physical_pb_type_name; @@ -846,6 +849,7 @@ typedef struct s_segment_inf { /* Xifan TANG: SPICE model support*/ char* spice_model_name; t_spice_model* spice_model; + CircuitModelId circuit_model; /* mrFPGA: Xifan TANG */ short seg_switch; /* end */ @@ -879,6 +883,7 @@ typedef struct s_switch_inf { /* Xifan TANG: spice support*/ char* spice_model_name; t_spice_model* spice_model; + CircuitModelId circuit_model; /* Xifan TANG: switch structure */ enum e_spice_model_structure structure; int switch_num_level; @@ -922,6 +927,7 @@ typedef struct s_direct_inf { /* Xifan Tang: FPGA-SPICE support */ char* spice_model_name; t_spice_model* spice_model; + CircuitModelId circuit_model; } t_direct_inf; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index ac0892cf8..b2e66728c 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1023,6 +1023,8 @@ static void ProcessSpiceModel(ezxml_t Parent, spice_model->design_tech_info.mux_info->structure = SPICE_MODEL_STRUCTURE_TREE; spice_model->design_tech_info.mux_info->add_const_input = FALSE; spice_model->design_tech_info.mux_info->const_input_val = 0; + spice_model->design_tech_info.mux_info->advanced_rram_design = FALSE; + spice_model->design_tech_info.mux_info->local_encoder = FALSE; } ezxml_set_attr(Node, "fracturable_lut", NULL); @@ -1632,7 +1634,8 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m } circuit_lib.set_circuit_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); } - if (NULL != spice_models[imodel].lut_intermediate_buffer) { + if ( (NULL != spice_models[imodel].lut_intermediate_buffer) + && (1 == spice_models[imodel].lut_intermediate_buffer->exist) ) { std::string model_name; if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) { model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 561362e1d..4b039d5c8 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1128,6 +1128,7 @@ typedef struct s_clb_to_clb_directs { int y_offset; int z_offset; t_spice_model* spice_model; + CircuitModelId circuit_model; char* name; } t_clb_to_clb_directs; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index 748e62ef5..7e9042806 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -1301,6 +1301,7 @@ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, return ret; } + t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type, int* port_num) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 34063fc95..075f9852c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -102,7 +102,6 @@ t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type, int* port_num); - enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin); t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 011eca31a..fc36ffff6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -33,6 +33,7 @@ #include "verilog_api.h" #include "fpga_x2p_unique_routing.h" +#include "link_arch_circuit_lib.h" #include "fpga_x2p_setup.h" /***** Subroutines Declarations *****/ @@ -1322,10 +1323,14 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, /* Start time count */ t_start = clock(); - vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-SPICE Tool suites Initilization begins...\n"); + vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-X2P Tool suites Initilization begins...\n"); - /* Initialize Arch SPICE MODELS*/ + /* FIXME: this function is going to be removed when new linking function is working + * Initialize Arch SPICE MODELS + */ init_check_arch_spice_models(Arch, &(vpr_setup.RoutingArch)); + /* Link circuit models to architecture */ + link_circuit_library_to_arch(Arch, &(vpr_setup.RoutingArch)); /* Initialize idle mode and physical mode of each pb_type and pb_graph_node */ init_check_arch_pb_type_idle_and_phy_mode(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp new file mode 100644 index 000000000..3cdd35eb1 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -0,0 +1,592 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: link_arch_circuit_lib.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/12 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * This file includes key functions to link circuit models to the architecture modules + ***********************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" +#include "route_common.h" + +/* Include vtr libraries */ +#include "vtr_assert.h" + +/* Include spice support headers*/ +#include "linkedlist.h" +#include "fpga_x2p_types.h" +#include "fpga_x2p_globals.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_timing_utils.h" +#include "fpga_x2p_backannotate_utils.h" +#include "fpga_x2p_pbtypes_utils.h" +#include "verilog_api.h" + +#include "check_circuit_library.h" +#include "link_arch_circuit_lib.h" + +/************************************************************************ + * Find a circuit model with a given name + * Case 1: if the circuit_model_name is not defined, + * we find a default circuit model and check its type + * Case 2: if the circuit_model_name is defined, + * we find a matched circuit model and check its type + ***********************************************************************/ +CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, + const CircuitLibrary& circuit_lib, + const enum e_spice_model_type& model_type) { + CircuitModelId circuit_model = CIRCUIT_MODEL_OPEN_ID; + /* If the circuit_model_name is not defined, we use the default*/ + if (NULL == circuit_model_name) { + circuit_model = circuit_lib.default_circuit_model(model_type); + } else { + circuit_model = circuit_lib.circuit_model(circuit_model_name); + } + + /* Check the circuit model, we should have one! */ + if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s!\n", + __FILE__, __LINE__, + circuit_lib.circuit_model_name(circuit_model).c_str()); + return circuit_model; /* Return here, no need to check the model_type */ + } + + /* Check the type of circuit model, make sure it is the one we want */ + if (model_type != circuit_lib.circuit_model_type(circuit_model)) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Invalid type when trying to find circuit model called %s! Expect %s but found %s!\n", + __FILE__, __LINE__, + circuit_model_name, + CIRCUIT_MODEL_TYPE_STRING[size_t(model_type)], + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))]); + } + + return circuit_model; +} + +/************************************************************************ + * Link circuit model to the SRAM organization + * Case 1: standalone organization required a SRAM circuit model + * Case 1: scan-chain organization required a SCFF circuit model + * Case 1: memory-bank organization required a SRAM circuit model + ***********************************************************************/ +static +void link_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, + const CircuitLibrary& circuit_lib) { + /* If cur_sram_inf_orgz is not initialized, do nothing */ + if (NULL == cur_sram_inf_orgz) { + return; + } + + /* Check the type of SRAM_Ciruit_MODEL required by different sram organization */ + /* check SRAM ports + * Checker for circuit models used by the SRAM organization + * either SRAMs or SCFFs + * 1. It will check the basic port required for SRAMs and SCFFs + * 2. It will check any special ports required for SRAMs and SCFFs + */ + switch (cur_sram_inf_orgz->type) { + case SPICE_SRAM_STANDALONE: + cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SRAM); + /* check SRAM ports */ + check_sram_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model, false); + break; + case SPICE_SRAM_MEMORY_BANK: + cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SRAM); + /* check if this one has bit lines and word lines */ + check_sram_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model, true); + break; + case SPICE_SRAM_SCAN_CHAIN: + /* check Scan-chain Flip-flop ports */ + cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SCFF); + check_scff_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model); + break; + case SPICE_SRAM_LOCAL_ENCODER: + /* Wipe out LOCAL ENCODER, it is not supported here ! */ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Local encoder SRAM organization is not supported!\n", + __FILE__, __LINE__); + exit(1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + /* RRAM Scan-chain is not supported yet. Now just forbidden this option */ + if ( (SPICE_SRAM_SCAN_CHAIN == cur_sram_inf_orgz->type) + && (SPICE_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(cur_sram_inf_orgz->circuit_model)) ) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) RRAM-based Scan-chain Flip-flop has not been supported yet!\n", + __FILE__, __LINE__); + exit(1); + } + + return; +} + +static +void link_sram_inf(t_sram_inf* cur_sram_inf, + const CircuitLibrary& circuit_lib) { + /* We have two branches: + * 1. SPICE SRAM organization information + * 2. Verilog SRAM organization information + */ + link_one_sram_inf_orgz(cur_sram_inf->spice_sram_inf_orgz, + circuit_lib); + + link_one_sram_inf_orgz(cur_sram_inf->verilog_sram_inf_orgz, + circuit_lib); + + return; +} + + +/************************************************************************** + * With given circuit port, find the pb_type port with same name and type + **************************************************************************/ +t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitPortId& circuit_port) { + t_port* ret = NULL; + size_t num_found = 0; + + /* Search ports */ + for (int iport = 0; iport < pb_type->num_ports; iport++) { + /* Match the name and port size*/ + if ( (0 == circuit_lib.port_prefix(circuit_model, circuit_port).compare(pb_type->ports[iport].name)) + && (size_t(pb_type->ports[iport].num_pins) == circuit_lib.port_size(circuit_model, circuit_port))) { + /* Match the type*/ + switch (circuit_lib.port_type(circuit_model, circuit_port)) { + case SPICE_MODEL_PORT_INPUT: + if ((IN_PORT == pb_type->ports[iport].type) + &&(0 == pb_type->ports[iport].is_clock)) { + ret = &(pb_type->ports[iport]); + num_found++; + } + break; + case SPICE_MODEL_PORT_OUTPUT: + if (OUT_PORT == pb_type->ports[iport].type) { + ret = &(pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_CLOCK: + if ((IN_PORT == pb_type->ports[iport].type)&&(1 == pb_type->ports[iport].is_clock)) { + ret = &(pb_type->ports[iport]); + num_found++; + } + break; + case SPICE_MODEL_PORT_INOUT : + if ((INOUT_PORT == pb_type->ports[iport].type)&&(0 == pb_type->ports[iport].is_clock)) { + ret = &(pb_type->ports[iport]); + num_found++; + } + break; + case SPICE_MODEL_PORT_SRAM: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for circuit model port(%s)!\n", + __FILE__, __LINE__, circuit_lib.port_prefix(circuit_model, circuit_port)); + exit(1); + } + } + } + + /* We should find only 1 match */ + if (1 < num_found) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", + __FILE__, __LINE__, pb_type->name, circuit_lib.port_prefix(circuit_model, circuit_port).c_str()); + exit(1); + } + + return ret; +} + + +/************************************************************************ + * Map (synchronize) pb_type ports to circuit model ports + ***********************************************************************/ +static +int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + + /* Check */ + assert(NULL != cur_pb_type); + + /* Initialize each port */ + for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { + cur_pb_type->ports[iport].circuit_model_port = CIRCUIT_PORT_OPEN_ID; + } + + /* Return if SPICE_MODEL is NULL */ + if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { + return 0; + } + + /* For each port, find a SPICE model port, which has the same name and port size */ + for (auto& port : circuit_lib.ports(circuit_model)) { + t_port* cur_pb_type_port = find_pb_type_port_match_circuit_model_port(cur_pb_type, circuit_lib, circuit_model, port); + /* Not every spice_model_port can find a mapped pb_type_port. + * Since a pb_type only includes necessary ports in technology mapping. + * ports for physical designs may be ignored ! + */ + if (NULL != cur_pb_type_port) { + cur_pb_type_port->circuit_model_port = port; + } + } + /* Although some spice_model_port may not have a corresponding pb_type_port + * but each pb_type_port should be mapped to a spice_model_port + */ + for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { + if (CIRCUIT_PORT_OPEN_ID == cur_pb_type->ports[iport].circuit_model_port) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", + __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, + circuit_lib.circuit_model_name(circuit_model).c_str()); + exit(1); + } + } + + return cur_pb_type->num_ports; +} + +/************************************************************************ + * Find a circuit model for an interconnect in pb_type + * Case 1: if the circuit_model_name is not defined, + * we find a default circuit model and check its type + * Case 2: if the circuit_model_name is defined, + * we find a matched circuit model and check its type + ***********************************************************************/ +static +void link_pb_type_interc_circuit_model_by_type(t_interconnect* cur_interc, + const CircuitLibrary& circuit_lib, + const enum e_spice_model_type& model_type) { + + /* If the circuit_model_name is not defined, we use the default*/ + cur_interc->circuit_model = link_circuit_model_by_name_and_type(cur_interc->spice_model_name, + circuit_lib, + model_type); + /* Check the circuit model, we should have one! */ + if (CIRCUIT_MODEL_OPEN_ID == cur_interc->circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Error in linking circuit model for interconnect(name %s)! Check [LINE%d] in architecture file)!\n", + __FILE__, __LINE__, + cur_interc->name, + cur_interc->line_num); + exit(1); + } + + /* Special check for MUXes: + * If the multiplexers do not have any input buffers, the loop breaker cannot be disabled + */ + if (SPICE_MODEL_MUX == model_type) { + if (NULL != cur_interc->loop_breaker_string) { + if (false == circuit_lib.is_input_buffered(cur_interc->circuit_model)) { + vpr_printf(TIO_MESSAGE_INFO, + "Line[%d] Cannot disable an interconnect without input buffering.\n", + cur_interc->line_num); + } + } + } + + return; +} + +/************************************************************************ + * Find a circuit model for an interconnect in pb_type + * Case 1: if this is a DIRECT interconnection, + * we will try to find a circuit model whose type is WIRE + * Case 2: if this is a COMPLETE interconnection, we should evaluate + * the number of multiplexer required. + * when it does require multiplexers + * we will try to find a circuit model whose type is MUX + * otherwise, + * we will try to find a circuit model whose type is WIRE + * Case 3: if this is a MUX interconnection, + * we will try to find a circuit model whose type is WIRE + ***********************************************************************/ +static +void link_pb_type_interc_circuit_model(t_interconnect* cur_interc, + const CircuitLibrary& circuit_lib) { + switch (cur_interc->type) { + case DIRECT_INTERC: + link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_WIRE); + break; + case COMPLETE_INTERC: + /* Special for Completer Interconnection: + * 1. The input number is 1, this infers a direct interconnection. + * 2. The input number is larger than 1, this infers multplexers + * according to interconnect[j].num_mux identify the number of input at this level + */ + if (0 == cur_interc->num_mux) { + link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_WIRE); + } else { + link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_MUX); + } + break; + case MUX_INTERC: + link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_MUX); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Unknown type of interconnection (name=%s) defined in architecture file(LINE%d)!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + return; +} + +/************************************************************************ + * Walk through the pb_types in a recursive way + * Find circuit_model_name definition in pb_types + * Try to match the name with defined spice_models + ***********************************************************************/ +static +void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type, + const CircuitLibrary& circuit_lib) { + if (NULL == cur_pb_type) { + vpr_printf(TIO_MESSAGE_WARNING, + "(File:%s,LINE[%d])cur_pb_type is null pointor!\n", + __FILE__, __LINE__); + return; + } + + /* If there is a circuit_model_name or physical_pb_type_name referring to a physical pb type, + * this is a leaf node! + */ + if ( TRUE == is_primitive_pb_type(cur_pb_type) ) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins SPICE modeling + */ + if (NULL != cur_pb_type->physical_pb_type_name) { + /* if this is not a physical pb_type, we do not care its circuit_model_name*/ + return; + } + /* Let's find a matched circuit model!*/ + cur_pb_type->circuit_model = circuit_lib.circuit_model(cur_pb_type->spice_model_name); + if (CIRCUIT_MODEL_OPEN_ID == cur_pb_type->circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s, in pb_type(%s)!\n", + __FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); + exit(1); + } + /* Map pb_type ports to SPICE model ports*/ + link_pb_type_port_to_circuit_model_ports(cur_pb_type, circuit_lib, cur_pb_type->circuit_model); + return; + } + + /* Otherwise, initialize it to be OPEN node */ + cur_pb_type->circuit_model = CIRCUIT_MODEL_OPEN_ID; + + /* Traversal the hierarchy*/ + for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Task 1: Find the interconnections and match the spice_model */ + for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + /* Initialize it to be OPEN node */ + cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CIRCUIT_MODEL_OPEN_ID; + link_pb_type_interc_circuit_model(&(cur_pb_type->modes[imode].interconnect[jinterc]), + circuit_lib); + } + /* Task 2: Find the child pb_type, do matching recursively */ + for (int ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { + link_pb_types_circuit_model_rec(&(cur_pb_type->modes[imode].pb_type_children[ipb]), circuit_lib); + } + } + return; +} + +/* Check if the spice model structure is the same with the switch_inf structure */ +static +size_t check_circuit_model_structure_match_switch_inf(const t_switch_inf& target_switch_inf, + const CircuitLibrary& circuit_lib) { + size_t num_err = 0; + + VTR_ASSERT_SAFE(CIRCUIT_MODEL_OPEN_ID != target_switch_inf.circuit_model); + if (target_switch_inf.structure != circuit_lib.mux_structure(target_switch_inf.circuit_model)) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Mismatch in MUX structure between circuit model(%s, %s) and switch_inf(%s, %s)!\n", + __FILE__, __LINE__, + circuit_lib.circuit_model_name(target_switch_inf.circuit_model).c_str(), + CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(circuit_lib.mux_structure(target_switch_inf.circuit_model))], + target_switch_inf.name, + CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(target_switch_inf.structure)]); + num_err++; + } + return num_err; +} + + +/************************************************************************ + * Initialize and check circuit models defined in architecture + * Tasks: + * 1. Link the circuit model defined in pb_types and routing switches + * 2. Add default circuit model for any inexplicit definition + ***********************************************************************/ +void link_circuit_library_to_arch(t_arch* arch, + t_det_routing_arch* routing_arch) { + + vpr_printf(TIO_MESSAGE_INFO, "Linking circuit models to modules in FPGA architecture...\n"); + + /* Check Circuit models first*/ + VTR_ASSERT_SAFE( (NULL != arch) && (NULL != arch->spice) ); + + /* 1. Link the spice model defined in pb_types and routing switches */ + /* Step A: Check routing switches, connection blocks*/ + if (0 >= arch->num_cb_switch) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d]) Define Switches for Connection Blocks is mandatory in FPGA X2P support! Miss this part in architecture file.\n", + __FILE__,__LINE__); + exit(1); + } + + for (int i = 0; i < arch->num_cb_switch; i++) { + arch->cb_switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->cb_switches[i].spice_model_name, + arch->spice->circuit_lib, SPICE_MODEL_MUX); + if (CIRCUIT_MODEL_OPEN_ID == arch->cb_switches[i].circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", + __FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); + exit(1); + } + /* Check the spice model structure is matched with the structure in switch_inf */ + if (0 < check_circuit_model_structure_match_switch_inf(arch->cb_switches[i], arch->spice->circuit_lib)) { + exit(1); + } + } + + /* Step B: Check switch list: Switch Box*/ + if (0 >= arch->num_switches) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d]) Define Switches for Switch Boxes is mandatory in FPGA X2P support! Miss this part in architecture file.\n", + __FILE__, __LINE__); + exit(1); + } + + for (int i = 0; i < arch->num_switches; i++) { + arch->Switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->Switches[i].spice_model_name, + arch->spice->circuit_lib, SPICE_MODEL_MUX); + if (CIRCUIT_MODEL_OPEN_ID == arch->Switches[i].circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", + __FILE__, __LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); + exit(1); + } + /* Check the spice model structure is matched with the structure in switch_inf */ + if (0 < check_circuit_model_structure_match_switch_inf(arch->Switches[i], arch->spice->circuit_lib)) { + exit(1); + } + } + + /* Update the switches in detailed routing architecture settings*/ + for (int i = 0; i < routing_arch->num_switch; i++) { + switch_inf[i].circuit_model = link_circuit_model_by_name_and_type(switch_inf[i].spice_model_name, + arch->spice->circuit_lib, SPICE_MODEL_MUX); + if (CIRCUIT_MODEL_OPEN_ID == switch_inf[i].circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", + __FILE__, __LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); + exit(1); + } + } + + /* Step C: Find SRAM Model*/ + link_sram_inf(&(arch->sram_inf), arch->spice->circuit_lib); + + /* Step D: Find the segment spice_model*/ + for (int i = 0; i < arch->num_segments; i++) { + arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name, + arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE); + if (CIRCUIT_MODEL_OPEN_ID == arch->Segments[i].circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Segment(Length:%d) is undefined in circuit models!\n", + __FILE__ ,__LINE__, + arch->Segments[i].spice_model_name, + arch->Segments[i].length); + exit(1); + } + } + + /* Step E: Direct connections between CLBs */ + for (int i = 0; i < arch->num_directs; i++) { + arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name, + arch->spice->circuit_lib, SPICE_MODEL_WIRE); + /* Check SPICE model type */ + if (CIRCUIT_MODEL_OPEN_ID == arch->Directs[i].circuit_model) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n", + __FILE__ ,__LINE__, + arch->Directs[i].spice_model_name, + arch->Directs[i].name); + exit(1); + } + /* Copy it to clb2clb_directs */ + clb2clb_direct[i].circuit_model = arch->Directs[i].circuit_model; + } + + /* 2. Search Complex Blocks (Pb_Types), Link spice_model according to the spice_model_name*/ + for (int i = 0; i < num_types; i++) { + if (NULL != type_descriptors[i].pb_type) { + link_pb_types_circuit_model_rec(type_descriptors[i].pb_type, arch->spice->circuit_lib); + } + } + + vpr_printf(TIO_MESSAGE_INFO, "Linking circuit models to modules in FPGA architecture...Completed\n"); + + return; +} + +/************************************************************************ + * End of file : link_arch_circuit_lib.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h new file mode 100644 index 000000000..1b134a78d --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h @@ -0,0 +1,68 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: link_arch_circuit_lib.h + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/08/12 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/* IMPORTANT: + * The following preprocessing flags are added to + * avoid compilation error when this headers are included in more than 1 times + */ +#ifndef LINK_ARCH_CIRCUIT_LIB_H +#define LINK_ARCH_CIRCUIT_LIB_H + +/* + * Notes in include header files in a head file + * Only include the neccessary header files + * that is required by the data types in the function/class declarations! + */ +/* Header files should be included in a sequence */ +/* Standard header files required go first */ + +CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, + const CircuitLibrary& circuit_lib, + const enum e_spice_model_type& model_type); + +t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitPortId& circuit_port); + +void link_circuit_library_to_arch(t_arch* arch, + t_det_routing_arch* routing_arch); + +#endif + +/************************************************************************ + * End of file : link_arch_circuit_lib.h + ***********************************************************************/ + From ef4d15df4e0bcf7b50d82555d3612cf473364d8b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 13:37:35 -0600 Subject: [PATCH 047/482] reorganize the libarchfpga repository --- vpr7_x2p/libarchfpga/SRC/{include => }/ReadLine.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/arch_types.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/arch_types_mrfpga.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/cad_types.h | 0 .../SRC/{fpga_spice_include => }/check_circuit_library.cpp | 0 .../SRC/{fpga_spice_include => }/check_circuit_library.h | 0 .../SRC/{fpga_spice_include => }/circuit_library.cpp | 0 .../libarchfpga/SRC/{fpga_spice_include => }/circuit_library.h | 0 .../libarchfpga/SRC/{fpga_spice_include => }/circuit_types.h | 0 .../libarchfpga/SRC/{fpga_spice_include => }/device_port.cpp | 0 vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/device_port.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/ezxml.h | 0 vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/linkedlist.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/logic_types.h | 0 vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/my_free_fwd.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/physical_types.h | 0 .../libarchfpga/SRC/{fpga_spice_include => }/port_parser.cpp | 0 vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/port_parser.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/read_xml_arch_file.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/read_xml_mrfpga.h | 0 .../libarchfpga/SRC/{fpga_spice_include => }/read_xml_spice.h | 0 .../SRC/{fpga_spice_include => }/read_xml_spice_util.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/read_xml_util.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/sides.h | 0 vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/spice_types.h | 0 .../libarchfpga/SRC/{fpga_spice_include => }/string_token.cpp | 0 .../libarchfpga/SRC/{fpga_spice_include => }/string_token.h | 0 vpr7_x2p/libarchfpga/SRC/{include => }/util.h | 0 vpr7_x2p/vpr/SRC/ctags_vpr_src.sh | 2 +- 29 files changed, 1 insertion(+), 1 deletion(-) rename vpr7_x2p/libarchfpga/SRC/{include => }/ReadLine.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/arch_types.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/arch_types_mrfpga.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/cad_types.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/check_circuit_library.cpp (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/check_circuit_library.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/circuit_library.cpp (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/circuit_library.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/circuit_types.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/device_port.cpp (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/device_port.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/ezxml.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/linkedlist.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/logic_types.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/my_free_fwd.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/physical_types.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/port_parser.cpp (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/port_parser.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/read_xml_arch_file.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/read_xml_mrfpga.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/read_xml_spice.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/read_xml_spice_util.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/read_xml_util.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/sides.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/spice_types.h (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/string_token.cpp (100%) rename vpr7_x2p/libarchfpga/SRC/{fpga_spice_include => }/string_token.h (100%) rename vpr7_x2p/libarchfpga/SRC/{include => }/util.h (100%) diff --git a/vpr7_x2p/libarchfpga/SRC/include/ReadLine.h b/vpr7_x2p/libarchfpga/SRC/ReadLine.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/ReadLine.h rename to vpr7_x2p/libarchfpga/SRC/ReadLine.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/arch_types.h b/vpr7_x2p/libarchfpga/SRC/arch_types.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/arch_types.h rename to vpr7_x2p/libarchfpga/SRC/arch_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/arch_types_mrfpga.h b/vpr7_x2p/libarchfpga/SRC/arch_types_mrfpga.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/arch_types_mrfpga.h rename to vpr7_x2p/libarchfpga/SRC/arch_types_mrfpga.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/cad_types.h b/vpr7_x2p/libarchfpga/SRC/cad_types.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/cad_types.h rename to vpr7_x2p/libarchfpga/SRC/cad_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.cpp rename to vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/check_circuit_library.h rename to vpr7_x2p/libarchfpga/SRC/check_circuit_library.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp rename to vpr7_x2p/libarchfpga/SRC/circuit_library.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h rename to vpr7_x2p/libarchfpga/SRC/circuit_library.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/circuit_types.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_types.h rename to vpr7_x2p/libarchfpga/SRC/circuit_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.cpp b/vpr7_x2p/libarchfpga/SRC/device_port.cpp similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.cpp rename to vpr7_x2p/libarchfpga/SRC/device_port.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.h b/vpr7_x2p/libarchfpga/SRC/device_port.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/device_port.h rename to vpr7_x2p/libarchfpga/SRC/device_port.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/ezxml.h b/vpr7_x2p/libarchfpga/SRC/ezxml.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/ezxml.h rename to vpr7_x2p/libarchfpga/SRC/ezxml.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/linkedlist.h b/vpr7_x2p/libarchfpga/SRC/linkedlist.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/linkedlist.h rename to vpr7_x2p/libarchfpga/SRC/linkedlist.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/logic_types.h b/vpr7_x2p/libarchfpga/SRC/logic_types.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/logic_types.h rename to vpr7_x2p/libarchfpga/SRC/logic_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/my_free_fwd.h b/vpr7_x2p/libarchfpga/SRC/my_free_fwd.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/my_free_fwd.h rename to vpr7_x2p/libarchfpga/SRC/my_free_fwd.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h b/vpr7_x2p/libarchfpga/SRC/physical_types.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/physical_types.h rename to vpr7_x2p/libarchfpga/SRC/physical_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp b/vpr7_x2p/libarchfpga/SRC/port_parser.cpp similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.cpp rename to vpr7_x2p/libarchfpga/SRC/port_parser.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h b/vpr7_x2p/libarchfpga/SRC/port_parser.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/port_parser.h rename to vpr7_x2p/libarchfpga/SRC/port_parser.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/read_xml_arch_file.h b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/read_xml_arch_file.h rename to vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/read_xml_mrfpga.h b/vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/read_xml_mrfpga.h rename to vpr7_x2p/libarchfpga/SRC/read_xml_mrfpga.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice.h b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice.h rename to vpr7_x2p/libarchfpga/SRC/read_xml_spice.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h b/vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/read_xml_spice_util.h rename to vpr7_x2p/libarchfpga/SRC/read_xml_spice_util.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/read_xml_util.h b/vpr7_x2p/libarchfpga/SRC/read_xml_util.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/read_xml_util.h rename to vpr7_x2p/libarchfpga/SRC/read_xml_util.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/sides.h b/vpr7_x2p/libarchfpga/SRC/sides.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/sides.h rename to vpr7_x2p/libarchfpga/SRC/sides.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/spice_types.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h rename to vpr7_x2p/libarchfpga/SRC/spice_types.h diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp b/vpr7_x2p/libarchfpga/SRC/string_token.cpp similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.cpp rename to vpr7_x2p/libarchfpga/SRC/string_token.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h b/vpr7_x2p/libarchfpga/SRC/string_token.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/fpga_spice_include/string_token.h rename to vpr7_x2p/libarchfpga/SRC/string_token.h diff --git a/vpr7_x2p/libarchfpga/SRC/include/util.h b/vpr7_x2p/libarchfpga/SRC/util.h similarity index 100% rename from vpr7_x2p/libarchfpga/SRC/include/util.h rename to vpr7_x2p/libarchfpga/SRC/util.h diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh index 5a37c337a..919a90230 100755 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh @@ -1,2 +1,2 @@ rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/include/*.[ch] ../../libarchfpga/SRC/fpga_spice_include/*.[ch] ../../libarchfpga/SRC/*.[ch] ../../pcre/SRC/*.[ch] +ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/*.[ch] ../../pcre/SRC/*.[ch] From c7526cb43cd531e4d35207a57a8682625cc5a4a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 14:19:40 -0600 Subject: [PATCH 048/482] memory sanitized --- vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp | 2 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 11 +++++++---- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + vpr7_x2p/libarchfpga/SRC/circuit_types.h | 2 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 5 +++-- vpr7_x2p/vpr/SRC/base/SetupVPR.c | 2 +- vpr7_x2p/vpr/SRC/ctags_vpr_src.sh | 2 +- 7 files changed, 15 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 98952927f..0b0f8fa69 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -450,7 +450,7 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE); /* If we have any errors, exit */ - vpr_printf(TIO_MESSAGE_ERROR, + vpr_printf(TIO_MESSAGE_INFO, "Finished checking circuit library with %d errors!\n", num_err); diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 6bd5aab07..4da76e417 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -48,6 +48,9 @@ /************************************************************************ * Constructors ***********************************************************************/ +CircuitLibrary::CircuitLibrary() { + return; +} /************************************************************************ * Public Accessors : aggregates @@ -1272,7 +1275,7 @@ void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_types_[circuit_model_id] = wire_type; return; } @@ -1283,7 +1286,7 @@ void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_rc_[circuit_model_id].set_x(r_val); return; } @@ -1294,7 +1297,7 @@ void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_rc_[circuit_model_id].set_y(c_val); return; } @@ -1305,7 +1308,7 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_num_levels_[circuit_model_id] = num_level; return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 0b3ed3c06..1717bb60f 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -216,6 +216,7 @@ class CircuitLibrary { INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INVERTER, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ }; public: /* Constructors */ + CircuitLibrary(); public: /* Accessors: aggregates */ circuit_model_range circuit_models() const; circuit_port_range ports(const CircuitModelId& circuit_model_id) const; diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/circuit_types.h index 6d72b2242..a2b86f38f 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_types.h @@ -114,7 +114,7 @@ enum e_spice_model_gate_type { enum e_wire_model_type { WIRE_MODEL_PIE, WIRE_MODEL_T, - NUM_WIRE_MODEL_TYPES, + NUM_WIRE_MODEL_TYPES }; enum e_spice_model_port_type { diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index b2e66728c..17ebb718a 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1028,7 +1028,6 @@ static void ProcessSpiceModel(ezxml_t Parent, } ezxml_set_attr(Node, "fracturable_lut", NULL); - spice_model->design_tech_info.gate_info = NULL; if (SPICE_MODEL_GATE == spice_model->type) { /* Malloc */ @@ -1073,13 +1072,15 @@ static void ProcessSpiceModel(ezxml_t Parent, /* LUT intermediate buffers */ Node = ezxml_child(Parent, "lut_intermediate_buffer"); - spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); + spice_model->lut_intermediate_buffer = NULL; if (Node) { + spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); /* Malloc the lut_input_buffer */ ProcessSpiceModelBuffer(Node,spice_model->lut_intermediate_buffer); FreeNode(Node); } else if ((SPICE_MODEL_LUT == spice_model->type) || (SPICE_MODEL_MUX == spice_model->type)) { + spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); /* Assign default values */ spice_model->lut_intermediate_buffer->exist = 0; spice_model->lut_intermediate_buffer->spice_model = NULL; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 7a78d6d97..5b0e90004 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1186,7 +1186,7 @@ static void SetupSynVerilogOpts(t_options Options, /* SynVerilog needs the input from spice modeling */ if (FALSE == arch->read_xml_spice) { arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog; - arch->spice = (t_spice*)my_malloc(sizeof(t_spice)); + arch->spice = (t_spice*)my_calloc(1, sizeof(t_spice)); } return; diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh index 919a90230..95bff29de 100755 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh @@ -1,2 +1,2 @@ rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/*.[ch] ../../pcre/SRC/*.[ch] +ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/* ../../pcre/SRC/*.[ch] From 4cffd8ac2d78a3cb1ee170e08ea70bac4822d743 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 15:37:42 -0600 Subject: [PATCH 049/482] keep route file updated with tileable rr_graph --- .../rr_graph/rr_graph_builder_utils.cpp | 27 +++++++++++++++++++ .../device/rr_graph/rr_graph_builder_utils.h | 3 +++ vpr7_x2p/vpr/SRC/route/route_common.c | 15 ++++++++++- 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp index 6752def9e..167d6d161 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp @@ -341,6 +341,33 @@ void add_edges_for_two_rr_nodes(const t_rr_graph* rr_graph, } +/************************************************************************ + * Get the track_id of a routing track w.r.t its coordinator + * In tileable routing architecture, the track_id changes SB by SB. + * Therefore the track_ids are stored in a vector, indexed by the relative coordinator + * based on the starting point of the track + * For routing tracks in INC_DIRECTION + * (xlow, ylow) should be the starting point + * + * (xlow, ylow) (xhigh, yhigh) + * track_id[0] -------------------------------> track_id[xhigh - xlow + yhigh - ylow] + * + * For routing tracks in DEC_DIRECTION + * (xhigh, yhigh) should be the starting point + * + * (xlow, ylow) (xhigh, yhigh) + * track_id[0] <------------------------------- track_id[xhigh - xlow + yhigh - ylow] + * + * + ***********************************************************************/ +short get_rr_node_actual_track_id(const t_rr_node* track_rr_node, + const DeviceCoordinator& coord) { + DeviceCoordinator low_coord(track_rr_node->xlow, track_rr_node->ylow); + size_t offset = (int)abs((int)coord.get_x() - (int)low_coord.get_x() + (int)coord.get_y() - (int)low_coord.get_y()); + return track_rr_node->track_ids[offset]; +} + + /************************************************************************ * Get the coordinator of a starting point of a routing track * For routing tracks in INC_DIRECTION diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h index c213546d5..5ef5382f3 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h @@ -35,6 +35,9 @@ void add_edges_for_two_rr_nodes(const t_rr_graph* rr_graph, const std::vector des_rr_node, const std::vector driver_switches); +short get_rr_node_actual_track_id(const t_rr_node* track_rr_node, + const DeviceCoordinator& coord); + DeviceCoordinator get_track_rr_node_start_coordinator(const t_rr_node* track_rr_node); DeviceCoordinator get_track_rr_node_end_coordinator(const t_rr_node* track_rr_node); diff --git a/vpr7_x2p/vpr/SRC/route/route_common.c b/vpr7_x2p/vpr/SRC/route/route_common.c index ad8f2d8eb..83b7c8070 100755 --- a/vpr7_x2p/vpr/SRC/route/route_common.c +++ b/vpr7_x2p/vpr/SRC/route/route_common.c @@ -20,6 +20,8 @@ #include "buffer_insertion.h" /* end */ +#include "rr_graph_builder_utils.h" + /* Xifan TANG: useful functions for pb_pin_eq_auto_detect */ void reassign_rr_node_net_num_from_scratch(); @@ -1214,7 +1216,18 @@ void print_route(char *route_file) { break; } - fprintf(fp, "%d ", rr_node[inode].ptc_num); + /* A kind of dirty fix for tileable routing, + * the track_ids is allocated by tileable routing. + * If the vector is not empty, it means tileable routing is enabled + * we need another function to get the track_id rather than ptc_num + */ + if (0 == rr_node[inode].track_ids.size()) { + fprintf(fp, "%d ", rr_node[inode].ptc_num); + } else { + /* Xifan Tang: for routing tracks, get the actual track ids */ + DeviceCoordinator cur_coord(ilow, jlow); + fprintf(fp, "%d ", get_rr_node_actual_track_id(&(rr_node[inode]), cur_coord)); + } /* Uncomment line below if you're debugging and want to see the switch types * * used in the routing. */ From 1118b28397fac4a335e4ab1290f31ed923656d72 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 16:11:04 -0600 Subject: [PATCH 050/482] use single subckt for switch box again, to abolish the multi-module subckt --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index eb736e27e..76bf438d0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2350,7 +2350,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_OUTPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3967,7 +3967,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Create a snapshot on sram_orgz_info */ t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); - /* Output unique side modules */ + /* Output unique side modules for (size_t side = 0; side < device_rr_gsb.get_max_num_sides(); ++side) { Side side_manager(side); for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) { @@ -3978,12 +3978,17 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, } } } + */ /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); + /* dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, explicit_port_mapping); + */ + dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir, + subckt_dir, unique_mirror, explicit_port_mapping); } /* Restore sram_orgz_info to the base */ From edfa72a666731a9423b55782490880a0564a60d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 16:47:28 -0600 Subject: [PATCH 051/482] try to fix the bug in clock net identification --- vpr7_x2p/vpr/SRC/base/read_blif.c | 5 ++++- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 6 ++---- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 1 + 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/read_blif.c b/vpr7_x2p/vpr/SRC/base/read_blif.c index 8e982725d..75008fc3f 100644 --- a/vpr7_x2p/vpr/SRC/base/read_blif.c +++ b/vpr7_x2p/vpr/SRC/base/read_blif.c @@ -524,7 +524,7 @@ static void add_latch(int doall, INP t_model *latch_model) { /* Store the initial value */ logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]); /* Add clock identification */ - logical_block[logical_block[num_logical_blocks - 1].clock_net].is_clock = TRUE; + logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE; /*END*/ num_latches++; @@ -722,6 +722,9 @@ static void add_subckt(int doall, t_model *user_models) { add_vpack_net(circuit_signal_name[i], RECEIVER, num_logical_blocks - 1, port->index, my_atoi(pin_number), TRUE, doall); + + /* Add clock identification */ + logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE; } else { logical_block[num_logical_blocks - 1].input_nets[port->index][my_atoi( pin_number)] = add_vpack_net( diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index 7e9042806..ca1f0a96a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -1005,8 +1005,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, cur_pb_type->physical_mode_num_conf_bits = 0; /* Recursively finish all the child pb_types*/ - if ((NULL == cur_pb_type->spice_model_name) - && (NULL == cur_pb_type->physical_pb_type_name)) { + if ( FALSE == is_primitive_pb_type(cur_pb_type)) { /* Find the mode that define_idle_mode*/ mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { @@ -1017,8 +1016,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, } /* Check if this has defined a spice_model*/ - if ((NULL != cur_pb_type->spice_model_name) - || (NULL != cur_pb_type->physical_pb_type_name)) { + if ( TRUE == is_primitive_pb_type(cur_pb_type)) { sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, cur_sram_orgz_info->type, 0); cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits; /* calculate the number of reserved configuration bits */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 5db74a44f..f87ff45a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1751,6 +1751,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* update stamped sram counter */ stamped_sram_cnt += cur_pb_type->physical_mode_num_conf_bits; /* Check */ + if (stamped_sram_cnt != get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)) assert(stamped_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); assert(stamped_iopad_cnt == iopad_verilog_model->cnt); /* Finish for primitive node, return */ From d2d8af541658ba2a9af954ebf1f7b8d8c56b2ac3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 17:34:09 -0600 Subject: [PATCH 052/482] bug fixing for pb_type num_conf_bits and num_iopads stats --- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 46 +++++++++++++++++++ .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 4 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 ++- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index ca1f0a96a..9da08d95b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -1023,6 +1023,7 @@ int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, cur_pb_type->physical_mode_num_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, cur_sram_orgz_info->type, 0); + } else { /* Count the sum of configuration bits of all the children pb_types */ /* Find the mode that define_idle_mode*/ mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); @@ -1232,6 +1233,28 @@ void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) { return; } +/******************************************************************** + * Initialize the number of configuration bits for each pb_type + * in the list of type descriptors + *******************************************************************/ +void init_pb_types_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) { + for (int itype = 0; itype < num_types; ++itype) { + /* bypass EMPTY_TYPES */ + if (EMPTY_TYPE == &(type_descriptors[itype])) { + continue; + } + int capacity= type_descriptors[itype].capacity; + assert(0 < capacity); + + /* check capacity and if this has been mapped */ + for (int iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + rec_count_num_conf_bits_pb_type_physical_mode(type_descriptors[itype].pb_type, cur_sram_orgz_info); + } + } + return; +} + /* With given spice_model_port, find the pb_type port with same name and type*/ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, t_spice_model_port* spice_model_port) { @@ -1793,6 +1816,29 @@ void init_grids_num_iopads() { return; } +/******************************************************************** + * Initialize the number of configuration bits for each pb_type + * in the list of type descriptors + *******************************************************************/ +void init_pb_types_num_iopads() { + for (int itype = 0; itype < num_types; ++itype) { + /* bypass EMPTY_TYPES */ + if (EMPTY_TYPE == &(type_descriptors[itype])) { + continue; + } + + int capacity= type_descriptors[itype].capacity; + assert(0 < capacity); + + /* check capacity and if this has been mapped */ + for (int iz = 0; iz < capacity; iz++) { + /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ + rec_count_num_iopads_pb_type_physical_mode(type_descriptors[itype].pb_type); + } + } + return; +} + /* Count the number of mode configuration bits of a grid (type_descriptor) in default mode */ void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type) { int mode_index, ipb, jpb; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 075f9852c..8a85329c0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -93,6 +93,8 @@ void init_one_grid_num_conf_bits(int ix, int iy, void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info); +void init_pb_types_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info); + void map_clb_pins_to_pb_graph_pins(); t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, @@ -135,6 +137,8 @@ void init_one_grid_num_iopads(int ix, int iy); void init_grids_num_iopads(); +void init_pb_types_num_iopads(); + void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type); void rec_count_num_mode_bits_pb(t_pb* cur_pb); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 41b2c634c..5c4d1f132 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -242,8 +242,10 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Initialize the number of configuration bits of all the grids */ vpr_printf(TIO_MESSAGE_INFO, "Count the number of configuration bits, IO pads in each logic block...\n"); /* init_grids_num_conf_bits(sram_verilog_orgz_type); */ - init_grids_num_conf_bits(sram_verilog_orgz_info); - init_grids_num_iopads(); + //init_grids_num_conf_bits(sram_verilog_orgz_info); + init_pb_types_num_conf_bits(sram_verilog_orgz_info); + //init_grids_num_iopads(); + init_pb_types_num_iopads(); /* init_grids_num_mode_bits(); */ dump_verilog_defines_preproc(src_dir_path, From 90aaed6e1f3957af9ee9ed8f1e264b48d1413c12 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 14 Aug 2019 09:10:13 -0600 Subject: [PATCH 053/482] Fix regression test --- .../k6_N10_sram_chain_HC_DPRAM_template.xml | 228 +++++++++--------- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 2 files changed, 115 insertions(+), 115 deletions(-) diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml index 07fb84b33..c03b83855 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -201,8 +201,8 @@ - - + + @@ -212,9 +212,9 @@ 10e-12 - - - + + + @@ -223,9 +223,9 @@ 10e-12 - - - + + + @@ -234,9 +234,9 @@ 10e-12 - - - + + + @@ -245,9 +245,9 @@ 10e-12 - - - + + + @@ -256,8 +256,8 @@ 10e-12 - - + + @@ -267,8 +267,8 @@ 10e-12 - - + + @@ -282,8 +282,8 @@ 10e-12 5e-12 5e-12 - - + + @@ -296,135 +296,135 @@ 10e-12 10e-12 - - + + - - + + - - + + - - + + - + - - + + - - + + - + - - + + - - + + - + - + - + - - - + + + - - + + - - - - - - - + + + + + + + - - - + + + - - - - - - - + + + + + + + - - + + - + - - - + + + - - + + - - - + + + - - + + - + - + - - + + - - + + - - + + @@ -432,17 +432,17 @@ - - + + - - - + + + - + - + - - - + + + @@ -482,7 +482,7 @@ - + @@ -499,25 +499,25 @@ 2.5x when looking up in Jeff's tables. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. This also leads to the switch being 46% of the total wire delay, which is reasonable. --> - + - + - + - + - + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -548,7 +548,7 @@ - + @@ -631,7 +631,7 @@ - + @@ -729,7 +729,7 @@ - - + - + - + - + - + - + - + diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 7fecf74d1..06672a0ae 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -9,7 +9,7 @@ verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirpath="$PWD" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" # VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" +template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " From df873903f8edb83d172fc40ec4ab4047adea9f28 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 14 Aug 2019 09:32:15 -0600 Subject: [PATCH 054/482] Bug fix for non fracturable LUT --- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 446897397..a487a5677 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -656,25 +656,25 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, } if (0 < num_mode_sram) { fprintf(fp, ", "); - } - if (TRUE == subckt_require_explicit_port_map) { - fprintf(fp, ".mode_out( "); - } - dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, - cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 0, VERILOG_PORT_CONKT); - if (TRUE == subckt_require_explicit_port_map) { - fprintf(fp, ")"); - } + if (TRUE == subckt_require_explicit_port_map) { + fprintf(fp, ".mode_out( "); + } + dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, + cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, + 0, VERILOG_PORT_CONKT); + if (TRUE == subckt_require_explicit_port_map) { + fprintf(fp, ")"); + } fprintf(fp, ", "); - if (TRUE == subckt_require_explicit_port_map) { - fprintf(fp, ".mode_outb( "); - } - dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, - cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 1, VERILOG_PORT_CONKT); - if (TRUE == subckt_require_explicit_port_map) { - fprintf(fp, ")"); + if (TRUE == subckt_require_explicit_port_map) { + fprintf(fp, ".mode_outb( "); + } + dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, + cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, + 1, VERILOG_PORT_CONKT); + if (TRUE == subckt_require_explicit_port_map) { + fprintf(fp, ")"); + } } break; case SPICE_SRAM_MEMORY_BANK: From 8e38aa60197f29c96402159f8cc8132a7971bdd4 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 14 Aug 2019 10:10:27 -0600 Subject: [PATCH 055/482] Merge with heterogeneous for unfracturable LUT bug fix --- fpga_flow/benchmarks/List/mcnc_benchmark.txt | 38 ++++++++++---------- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/fpga_flow/benchmarks/List/mcnc_benchmark.txt b/fpga_flow/benchmarks/List/mcnc_benchmark.txt index 2a505ce5d..799289cea 100644 --- a/fpga_flow/benchmarks/List/mcnc_benchmark.txt +++ b/fpga_flow/benchmarks/List/mcnc_benchmark.txt @@ -1,21 +1,21 @@ # Circuit Names, fixed routing channel width, -#alu4/*.v, 300 -#apex2/*.v, 300 -#apex4/*.v, 300 -#bigkey/*.v, 300 -#clma/*.v, 300 -#des/*.v, 300 -#diffeq/*.v, 300 -#dsip/*.v, 300 -#elliptic/*.v, 300 -#ex1010/*.v, 300 -#ex5p/*.v, 300 -#frisc/*.v, 300 -#misex3/*.v, 300 -#pdc/*.v, 300 +alu4/*.v, 300 +apex2/*.v, 300 +apex4/*.v, 300 +bigkey/*.v, 300 +clma/*.v, 300 +des/*.v, 300 +diffeq/*.v, 300 +dsip/*.v, 300 +elliptic/*.v, 300 +ex1010/*.v, 300 +ex5p/*.v, 300 +frisc/*.v, 300 +misex3/*.v, 300 +pdc/*.v, 300 s298/*.v, 30 -#s38417/*.v, 300 -#s38584/*.v, 300 -#seq/*.v, 300 -#spla/*.v, 300 -#tseng/*.v, 300 +s38417/*.v, 300 +s38584/*.v, 300 +seq/*.v, 300 +spla/*.v, 300 +tseng/*.v, 300 diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 06672a0ae..47608013f 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -10,7 +10,7 @@ verilog_output_dirpath="$PWD" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" # VPR critical inputs template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" +arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml" blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" From 35ad4a87e597611f514e5dc6786e7978a8ee4828 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 14 Aug 2019 12:51:17 -0600 Subject: [PATCH 056/482] add travis slack notification --- .travis.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis.yml b/.travis.yml index da8f68efa..7506d6422 100644 --- a/.travis.yml +++ b/.travis.yml @@ -104,3 +104,6 @@ after_failure: after_success: - .travis/after_success.sh +notifications: + slack: + secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw= From 5d3708651e3b2baf06081e6f1deca15c02ed21ab Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 15 Aug 2019 14:39:58 -0600 Subject: [PATCH 057/482] Added fpga_flow and fpga_task script + Missed local intermediate commits --- .../misc/fpgaflow_default_tool_path.conf | 32 + .../misc/yosys_template_yosys_vpr_flow.ys | 22 + openfpga_flow/scripts/run_fpga_flow.py | 837 ++++++++++++++---- openfpga_flow/scripts/run_fpga_task.py | 242 +++-- 4 files changed, 855 insertions(+), 278 deletions(-) create mode 100644 openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index c33b4162a..dbcd72b2b 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -8,9 +8,41 @@ abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace +pro_blif_path = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/pro_blif.pl +iverilog_path = iverilog +include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists [OPENFPGA_FLOW_CONFIG] # You dont need to change any of these varaibles, # Unless you are unhappy with intermidiate directories # or modifying fpga_flow sript significantly supported_flows = standard,vtr,vtr_standard,yosys_vpr + +[DEFAULT_PARSE_RESULT_VPR] +# parser format = , +clb_blocks = "Netlist clb blocks: ([0-9]+)", int +logic_delay = "Total logic delay: ([0-9.]+)", str +total_net_delay = "total net delay: ([0-9.]+)", str +total_routing_area = "Total routing area: ([0-9.]+)", str +total_logic_block_area = "Total used logic block area: ([0-9]+)", str +total_wire_length = "Total wirelength: ([0-9]+)", str +packing_time = "Packing took ([0-9.]+) seconds", str +placement_time = "Placement took ([0-9.]+) seconds", str +routing_time = "Routing took ([0-9.]+) seconds", str +average_net_length = "average net length: ([0-9.]+)", str +critical_path = "Final critical path: ([0-9.]+) ns", float +total_time_taken = "Routing took ([0-9.]+) seconds", float + +[DEFAULT_PARSE_RESULT_POWER] +pb_type_power="PB Types\s+([0-9]+)", float +routing_power="Routing\s+([0-9]+)", float +switch_box_power="Switch Box\s+([0-9]+)", float +connection_box_power="Connection Box\s+([0-9]+)", float +primitives_power="Primitives\s+([0-9]+)", float +interc_structures_power="Interc Structures\s+([0-9]+)", float +lut6_power="^\s+lut6\s+([0-9]+)", float +ff_power="^\s+ff\s+([0-9]+)", float + +[INTERMIDIATE_FILE_PREFIX] + + diff --git a/openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys b/openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys new file mode 100644 index 000000000..aeaded4b5 --- /dev/null +++ b/openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys @@ -0,0 +1,22 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +${READ_VERILOG_FILE} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +synth -top ${TOP_MODULE} -flatten +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index d439ef6c1..8c1e5d56e 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -10,73 +10,203 @@ import glob import subprocess import threading from string import Template +import re import xml.etree.ElementTree as ET - +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Initialise general paths for the script +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Copy directory where flow file exist flow_script_dir = os.path.dirname(os.path.abspath(__file__)) +# Find OpenFPGA base directory openfpga_base_dir = os.path.abspath( os.path.join(flow_script_dir, os.pardir, os.pardir)) -default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc', - 'fpgaflow_default_tool_path.conf') +# Copy directory from where script is laucnhed +# [req to resolve relative paths provided while launching script] launch_dir = os.getcwd() -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Setting up print and logging system -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -logging.basicConfig(level=logging.INFO, - format='%(levelname)s (%(threadName)-9s) - %(message)s') -logger = logging.getLogger('OpenFPGA_Task_logs') - -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Reading commnad-line argument -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -parser = argparse.ArgumentParser() -parser.add_argument('arch_file', type=str) -parser.add_argument('benchmark_files', type=str, nargs='+') -parser.add_argument('--top_module', type=str) -parser.add_argument('--fpga_flow', type=str, default="yosys_vpr") -parser.add_argument('--cad_tool_conf', - type=str, - default=default_cad_tool_conf, - help="CAD tool path and configurations") -parser.add_argument('--run_dir', - type=str, - default=os.path.join(openfpga_base_dir, 'tmp'), - help="Directory to store intermidiate file & final results") -args = parser.parse_args() - - -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Reading CAD Tools path configuration file -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Path section to append in configuration file to interpolate path script_env_vars = {"PATH": { "OPENFPGA_FLOW_PATH": flow_script_dir, "OPENFPGA_PATH": openfpga_base_dir}} -config = ConfigParser(interpolation=ExtendedInterpolation()) -config.read_dict(script_env_vars) -config.read_file( - open(os.path.join(args.cad_tool_conf))) -cad_tools = config["CAD_TOOLS_PATH"] +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Reading command-line argument +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Helper function to provide better alignment to help print + + +def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60) + + +parser = argparse.ArgumentParser(formatter_class=formatter) + +# Mandatory arguments +parser.add_argument('arch_file', type=str) +parser.add_argument('benchmark_files', type=str, nargs='+') + +# Optional arguments +parser.add_argument('--top_module', type=str, default="top") +parser.add_argument('--fpga_flow', type=str, default="yosys_vpr") +parser.add_argument('--cad_tool_conf', type=str, + help="CAD tools path overrides default setting") +parser.add_argument('--run_dir', type=str, + default=os.path.join(openfpga_base_dir, 'tmp'), + help="Directory to store intermidiate file & final results") +parser.add_argument('--yosys_tmpl', type=str, + help="Alternate yosys template, generates top_module.blif") + +# ACE2 and power estimation related arguments +parser.add_argument('--K', type=int, + help="LUT Size, if not specified extracted from arch file") +parser.add_argument('--power', action='store_true') +parser.add_argument('--power_tech', type=str, + help="Power tech xml file for power calculation") +parser.add_argument('--ace_d', type=float, + help="Specify the default signal density of PIs in ACE2") +parser.add_argument('--ace_p', type=float, + help="Specify the default signal probablity of PIs in ACE2") +parser.add_argument('--black_box_ace', action='store_true') + +# VPR Options +parser.add_argument('--min_route_chan_width', type=int, + help="Turn on min_route_chan_width") +parser.add_argument('--max_route_width_retry', type=int, default=100, + help="Maximum iterations to perform to reroute") +parser.add_argument('--fix_route_chan_width', type=int, + help="Turn on fix_route_chan_width") +parser.add_argument('--vpr_timing_pack_off', action='store_true', + help="Turn off the timing-driven pack for vpr") +parser.add_argument('--vpr_place_clb_pin_remap', action='store_true', + help="Turn on place_clb_pin_remap in VPR") +parser.add_argument('--vpr_max_router_iteration', type=int, + help="Specify the max router iteration in VPR") +parser.add_argument('--vpr_route_breadthfirst', action='store_true', + help="Use the breadth-first routing algorithm of VPR") +parser.add_argument('--vpr_use_tileable_route_chan_width', action='store_true', + help="Turn on the conversion to " + + "tileable_route_chan_width in VPR") + +# VPR - FPGA-X2P Extension +X2PParse = parser.add_argument_group('VPR-FPGA-X2P Extension') +X2PParse.add_argument('--vpr_fpga_x2p_rename_illegal_port', action='store_true', + help="Rename illegal ports option of VPR FPGA SPICE") +X2PParse.add_argument('--vpr_fpga_x2p_signal_density_weight', type=float, + help="Specify the signal_density_weight of VPR FPGA SPICE") +X2PParse.add_argument('--vpr_fpga_x2p_sim_window_size', type=float, + help="specify the sim_window_size of VPR FPGA SPICE") + +# VPR - FPGA-SPICE Extension +SPParse = parser.add_argument_group('FPGA-SPICE Extension') +SPParse.add_argument('--vpr_fpga_spice', type=str, + help="Print SPICE netlists in VPR") +SPParse.add_argument('--vpr_fpga_spice_sim_mt_num', type=int, + help="Specify the option sim_mt_num of VPR FPGA SPICE") +SPParse.add_argument('--vpr_fpga_spice_print_component_tb', action='store_true', + help="Output component-level testbench") +SPParse.add_argument('--vpr_fpga_spice_print_grid_tb', action='store_true', + help="Output grid-level testbench") +SPParse.add_argument('--vpr_fpga_spice_print_top_tb', action='store_true', + help="Output full-chip-level testbench") +SPParse.add_argument('--vpr_fpga_spice_leakage_only', action='store_true', + help="Turn on leakage_only mode in VPR FPGA SPICE") +SPParse.add_argument('--vpr_fpga_spice_parasitic_net_estimation_off', + action='store_true', + help="Turn off parasitic_net_estimation in VPR FPGA SPICE") +SPParse.add_argument('--vpr_fpga_spice_testbench_load_extraction_off', + action='store_true', + help="Turn off testbench_load_extraction in VPR FPGA SPICE") +SPParse.add_argument('--vpr_fpga_spice_simulator_path', type=str, + help="Specify simulator path") + +# VPR - FPGA-Verilog Extension +VeriPar = parser.add_argument_group('FPGA-Verilog Extension') +VeriPar.add_argument('--vpr_fpga_verilog', action='store_true', + help="Generator verilog of VPR FPGA SPICE") +VeriPar.add_argument('--vpr_fpga_verilog_dir', type=str, + help="path to store generated verilog files") +VeriPar.add_argument('--vpr_fpga_verilog_include_timing', action="store_true", + help="Print delay specification in Verilog files") +VeriPar.add_argument('--vpr_fpga_verilog_include_signal_init', + action="store_true", + help="Print signal initialization in Verilog files") +VeriPar.add_argument('--vpr_fpga_verilog_print_autocheck_top_testbench', + action="store_true", help="Print autochecked top-level " + + "testbench for Verilog Generator of VPR FPGA SPICE") +VeriPar.add_argument('--vpr_fpga_verilog_formal_verification_top_netlist', + action="store_true", help="Print formal top Verilog files") +VeriPar.add_argument('--vpr_fpga_verilog_include_icarus_simulator', + action="store_true", help="dd syntax and definition" + + " required to use Icarus Verilog simulator") +VeriPar.add_argument('--vpr_fpga_verilog_print_user_defined_template', + action="store_true", help="Unknown parameter") +VeriPar.add_argument('--vpr_fpga_verilog_print_report_timing_tcl', + action="store_true", help="Generate tcl script useful " + + "for timing report generation") +VeriPar.add_argument('--vpr_fpga_verilog_report_timing_rpt_path', + type=str, help="Specify path for report timing results") +VeriPar.add_argument('--vpr_fpga_verilog_print_sdc_pnr', action="store_true", + help="Generate sdc file to constraint Hardware P&R") +VeriPar.add_argument('--vpr_fpga_verilog_print_sdc_analysis', + action="store_true", help="Generate sdc file to do STA") +VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true", + help="Print top-level testbench for Verilog Generator " + + "of VPR FPGA SPICE") +VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb', + action="store_true", help="Print testbench" + + "for input blif file in Verilog Generator") +VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str, + help="Print modelsim " + + "simulation script", metavar="") + +# VPR - FPGA-Bitstream Extension +BSparse = parser.add_argument_group('FPGA-Bitstream Extension') +BSparse.add_argument('--vpr_fpga_bitstream_generator', action="store_true", + help="Generate FPGA-SPICE bitstream") + +# Regression test option +RegParse = parser.add_argument_group('Regression Test Extension') +RegParse.add_argument("--end_flow_with_test", action="store_true", + help="Run verification test at the end") + + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Global varaibles declaration +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Varible to store logger instance +logger = None +# arguments are parsed at the end of the script depending upon whether script +# is called externally or as a standalone +args = None +# variable to store script_configuration and cad tool paths +config, cad_tools = None, None # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Main program starts here # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + def main(): - validate_command_line_arguments(args) + check_required_file() + read_script_config() + validate_command_line_arguments() prepare_run_directory(args.run_dir) if (args.fpga_flow == "yosys_vpr"): logger.info('Running "yosys_vpr" Flow') run_yosys_with_abc() - exit() if (args.fpga_flow == "vtr"): run_odin2() run_abc_vtr() if (args.fpga_flow == "vtr_standard"): run_abc_for_standarad() - run_ace2() + if args.power: + run_ace2() + run_pro_blif_3arg() + run_rewrite_verilog() run_vpr() + if args.end_flow_with_test: + run_netlists_verification() exit() # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = @@ -84,7 +214,31 @@ def main(): # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -def validate_command_line_arguments(args): +def check_required_file(): + """ Function ensure existace of all required files for the script """ + files_dict = { + "CAD TOOL PATH": os.path.join(flow_script_dir, os.pardir, 'misc', + 'fpgaflow_default_tool_path.conf'), + } + for filename, filepath in files_dict.items(): + if not os.path.isfile(filepath): + clean_up_and_exit("Not able to locate deafult file " + filename) + + +def read_script_config(): + """ This fucntion reads default CAD tools path from configuration file """ + global config, cad_tools + config = ConfigParser(interpolation=ExtendedInterpolation()) + config.read_dict(script_env_vars) + default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc', + 'fpgaflow_default_tool_path.conf') + config.read_file(open(default_cad_tool_conf)) + if args.cad_tool_conf: + config.read_file(open(args.cad_tool_conf)) + cad_tools = config["CAD_TOOLS_PATH"] + + +def validate_command_line_arguments(): """ TODO : This funtion validates all supplied paramters @@ -95,6 +249,7 @@ def validate_command_line_arguments(args): benchmark argument convert glob to list of files Dont maintain the directory strcuture Throw error for directory in benchmark + check if args.powertech_file is provided for power measurement """ logger.info("Parsing commnad line arguments - Pending implementation") @@ -110,6 +265,13 @@ def validate_command_line_arguments(args): if not os.path.isfile(everyfile): clean_up_and_exit( "Failed to copy benchmark file-%s", args.arch_file) + + # Filter provided architecrue files + if args.power_tech: + args.power_tech = os.path.abspath(args.power_tech) + if not os.path.isfile(args.power_tech): + clean_up_and_exit( + "Power Tech file not found. -%s", args.power_tech) pass @@ -148,10 +310,11 @@ def prepare_run_directory(run_dir): # Create arch dir in run_dir and copy flattern architecrture file os.mkdir("arch") - tmpl = Template(open(args.arch_file).read()) + tmpl = Template( + open(args.arch_file, encoding='utf-8').read()) arch_filename = os.path.basename(args.arch_file) args.arch_file = os.path.join(run_dir, "arch", arch_filename) - with open(args.arch_file, 'w') as archfile: + with open(args.arch_file, 'w', encoding='utf-8') as archfile: archfile.write(tmpl.substitute(script_env_vars["PATH"])) # Create benchmark dir in run_dir and copy flattern architecrture file @@ -166,12 +329,14 @@ def prepare_run_directory(run_dir): def clean_up_and_exit(msg, clean=False): logger.error(msg) - logger.error("Existing . . . . . .") + logger.error("Exiting . . . . . .") exit() def run_yosys_with_abc(): - # Extract lut Input size from architecture file + """ + Execute yosys with ABC and optional blackbox support + """ tree = ET.parse(args.arch_file) root = tree.getroot() try: @@ -182,7 +347,7 @@ def run_yosys_with_abc(): except: logger.exception("Failed to extract lut_size from XML file") clean_up_and_exit("") - + args.K = lut_size # Yosys script parameter mapping ys_params = { "READ_VERILOG_FILE": " \n".join([ @@ -194,13 +359,12 @@ def run_yosys_with_abc(): } yosys_template = os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") - tmpl = Template(open(yosys_template).read()) + tmpl = Template(open(yosys_template, encoding='utf-8').read()) with open("yosys.ys", 'w') as archfile: archfile.write(tmpl.substitute(ys_params)) - try: with open('yosys_output.txt', 'w+') as output: - process = subprocess.run([cad_tools["yosys_path"], 'yosys1.ys'], + process = subprocess.run([cad_tools["yosys_path"], 'yosys.ys'], check=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE, @@ -212,7 +376,7 @@ def run_yosys_with_abc(): except: logger.exception("Failed to run yosys") clean_up_and_exit("") - logger.info("Yosys output written in file yosys_output.txt") + logger.info("Yosys output is written in file yosys_output.txt") def run_odin2(): @@ -228,166 +392,465 @@ def run_abc_for_standarad(): def run_ace2(): + if args.black_box_ace: + with open(args.top_module+'.blif', 'r') as fp: + blif_lines = fp.readlines() - pass + with open(args.top_module+'_bb.blif', 'w') as fp: + for eachline in blif_lines: + if ".names" in eachline: + input_nets = eachline.split()[1:] + if len(input_nets)-1 > args.K: + logger.error("One module in blif have more inputs" + + " than K value") + # Map CEll to each logic in blif + map_nets = (input_nets[:-1] + ["unconn"]*args.K)[:args.K] + map_nets = ["I[%d]=%s" % (indx, eachnet) + for indx, eachnet in enumerate(map_nets)] + map_nets += ["O[0]=%s\n" % input_nets[-1]] + fp.write(".subckt CELL ") + fp.write(" ".join(map_nets)) + else: + fp.write(eachline) + + declar_input = " ".join(["I[%d]" % i for i in range(args.K)]) + model_tmpl = "\n" + \ + ".model CELL\n" + \ + ".inputs " + declar_input + " \n" + \ + ".outputs O[0]\n" + \ + ".blackbox\n" + \ + ".end\n" + fp.write(model_tmpl) + # Prepare ACE run command + command = [ + "-b", args.top_module+('_bb.blif' if args.black_box_ace else ".blif"), + "-o", args.top_module+"_ace_out.act", + "-n", args.top_module+"_ace_out.blif", + "-c", "clk", + ] + command += ["-d", "%.4f" % args.ace_d] if args.ace_d else [""] + command += ["-p", "%.4f" % args.ace_d] if args.ace_p else [""] + try: + filename = args.top_module + '_ace2_output.txt' + with open(filename, 'w+') as output: + process = subprocess.run([cad_tools["ace_path"]] + command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.info("ACE2 failed with returncode %d", + process.returncode) + except: + logger.exception("Failed to run ACE2") + clean_up_and_exit("") + logger.info("ACE2 output is written in file %s" % filename) + + +def run_pro_blif_3arg(): + command = [ + "-i", args.top_module+"_ace_out.blif", + "-o", args.top_module+"_ace_corrected_out.blif", + "-initial_blif", args.top_module+'.blif', + ] + try: + filename = args.top_module+'_blif_3args_output.txt' + with open(filename, 'w+') as output: + process = subprocess.run(["perl", cad_tools["pro_blif_path"]] + + command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.info("blif_3args script failed with returncode %d", + process.returncode) + except: + logger.exception("Failed to run blif_3args") + clean_up_and_exit("") + logger.info("blif_3args output is written in file %s" % filename) def run_vpr(): - pass -# def generate_single_task_actions(taskname): -# """ -# This script generates all the scripts required for each benchmark -# """ -# curr_task_dir=os.path.join(gc["task_dir"], taskname) -# if not os.path.isdir(curr_task_dir): -# clean_up_and_exit("Task directory not found") -# os.chdir(curr_task_dir) + # Run Standard VPR Flow + min_channel_width = run_standard_vpr( + args.top_module+"_ace_corrected_out.blif", + -1, + args.top_module+"_min_chan_width_vpr.txt") + logger.info("Standard VPR flow routed with minimum %d Channels" % + min_channel_width) -# curr_task_conf_file=os.path.join(curr_task_dir, "config", "task.conf") -# if not os.path.isfile(curr_task_conf_file): -# clean_up_and_exit( -# "Missing configuration file for task %s" % curr_task_dir) + # Minimum routing channel width + if (args.min_route_chan_width): + logger.info("Executing minimum channel width routing") + min_channel_width *= 1+(args.min_route_chan_width/100) + min_channel_width = int(min_channel_width) + min_channel_width += 1 if (min_channel_width % 2) else 0 + logger.info("Trying to route using %d channels" % min_channel_width) -# task_conf=ConfigParser(allow_no_value = True, -# interpolation = ExtendedInterpolation()) -# task_conf.optionxform=str -# task_conf.read_dict(script_env_vars) -# task_conf.read_file(open(curr_task_conf_file)) -# # Check required sections in config file -# required_sec=["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"] -# missing_section=list(set(required_sec)-set(task_conf.sections())) -# if missing_section: -# clean_up_and_exit( -# "Missing section %s in task configuration file" % " ".join(missing_section)) + while(1): + res = run_vpr_route(args.top_module+"_ace_corrected_out.blif", + min_channel_width, + args.top_module+"_min_channel_reroute_vpr.txt") -# benchmark_list=[] -# for _, bench_file in task_conf["BENCHMARKS"].items(): -# if(glob.glob(bench_file)): -# benchmark_list.append(bench_file) -# else: -# logger.warning( -# "File Not Found: Skipping %s benchmark " % bench_file) + if res: + logger.info("Routing with channel width=%d successful" % + min_channel_width) + break + elif args.min_channel_width > (min_channel_width-2): + clean_up_and_exit("Failed to route within maximum " + + "iteration of channel width") + else: + logger.info("Unable to route using channel width %d" % + min_channel_width) + min_channel_width += 2 -# # Check if all benchmark/architecture files exits -# archfile_list=[] -# for _, arch_file in task_conf["ARCHITECTURES"].items(): -# arch_full_path=arch_file -# if os.path.isfile(arch_full_path): -# archfile_list.append(arch_full_path) -# else: -# logger.warning( -# "File Not Found: Skipping %s architecture " % arch_file) + extract_vpr_stats(args.top_module+"_min_channel_reroute_vpr.txt") -# script_list=[] -# for eacharch in archfile_list: -# script_list.append(create_run_script(gc["temp_run_dir"], -# eacharch, -# benchmark_list, -# task_conf["GENERAL"]["power_tech_file"], -# task_conf["SCRIPT_PARAM"])) -# return script_list + # Fixed routing channel width + elif args.fix_route_chan_width: + min_channel_width = run_standard_vpr( + args.top_module+"_ace_corrected_out.blif", + args.fix_route_chan_width, + args.top_module+"_fr_chan_width.txt") + logger.info("Fixed routing channel successfully routed with %d width" % + min_channel_width) + extract_vpr_stats(args.top_module+"_fr_chan_width.txt") + else: + extract_vpr_stats(args.top_module+"_min_chan_width.txt") + if args.power: + extract_vpr_power_esti(args.top_module+"_ace_corrected_out.power") -# def create_run_script(task_run_dir, archfile, benchmark_list, power_tech_file, additional_fpga_flow_params): -# """ -# Create_run_script function accespts run directory, architecture list and -# fpga_flow configuration file and prepare final executable fpga_flow script -# TODO : Replace this section after convert fpga_flow to python script -# Config file creation and bechnmark list can be skipped -# """ -# # = = = = = = = = = File/Directory Consitancy Check = = = = = = = = = = -# if not os.path.isdir(gc["misc_dir"]): -# clean_up_and_exit("Miscellaneous directory does not exist") +def run_standard_vpr(bench_blif, fixed_chan_width, logfile): + command = [cad_tools["vpr_path"], + args.arch_file, + bench_blif, + "--net_file", args.top_module+"_vpr.net", + "--place_file", args.top_module+"_vpr.place", + "--route_file", args.top_module+"_vpr.route", + "--full_stats", "--nodisp" + ] + # Power options + if args.power: + command += ["--power", + "--activity_file", args.top_module+"_ace_out.act", + "--tech_properties", args.power_tech] + # packer options + if args.vpr_timing_pack_off: + command += ["--timing_driven_clustering", "off"] + # channel width option + if fixed_chan_width >= 0: + command += ["-route_chan_width", fixed_chan_width] + if args.vpr_use_tileable_route_chan_width: + command += ["--use_tileable_route_chan_width"] -# fpga_flow_script=os.path.join(gc["misc_dir"], "fpga_flow_template.sh") -# if not os.path.isfile(fpga_flow_script): -# clean_up_and_exit("Missing fpga_flow script template %s" % -# fpga_flow_script) + # FPGA_Spice Options + if (args.power and args.vpr_fpga_spice): + command += ["--fpga_spice"] + if args.vpr_fpga_x2p_signal_density_weight: + command += ["--fpga_x2p_signal_density_weight", + args.vpr_fpga_x2p_signal_density_weight] + if args.vpr_fpga_x2p_sim_window_size: + command += ["--fpga_x2p_sim_window_size", + args.vpr_fpga_x2p_sim_window_size] + if args.vpr_fpga_spice_sim_mt_num: + command += ["--fpga_spice_sim_mt_num", + args.vpr_fpga_spice_sim_mt_num] + if args.vpr_fpga_spice_simulator_path: + command += ["--fpga_spice_simulator_path", + args.vpr_fpga_spice_simulator_path] + if args.vpr_fpga_spice_print_component_tb: + command += ["--fpga_spice_print_lut_testbench", + "--fpga_spice_print_hardlogic_testbench", + "--fpga_spice_print_pb_mux_testbench", + "--fpga_spice_print_cb_mux_testbench", + "--fpga_spice_print_sb_mux_testbench" + ] + if args.vpr_fpga_spice_print_grid_tb: + command += ["--fpga_spice_print_grid_testbench", + "--fpga_spice_print_cb_testbench", + "--fpga_spice_print_sb_testbench" + ] + if args.vpr_fpga_spice_print_top_tb: + command += ["--fpga_spice_print_top_testbench"] + if args.vpr_fpga_spice_leakage_only: + command += ["--fpga_spice_leakage_only"] + if args.vpr_fpga_spice_parasitic_net_estimation_off: + command += ["--fpga_spice_parasitic_net_estimation", "off"] + if args.vpr_fpga_spice_testbench_load_extraction_off: + command += ["--fpga_spice_testbench_load_extraction", "off"] -# fpga_flow_conf_tmpl=os.path.join(gc["misc_dir"], "fpga_flow_script.conf") -# if not os.path.isfile(fpga_flow_conf_tmpl): -# clean_up_and_exit("fpga_flow configuration tempalte is missing %s" % -# fpga_flow_conf_tmpl) + # FPGA Verilog options + if (args.power and args.vpr_fpga_verilog): + command += ["--fpga_verilog"] + if args.vpr_fpga_verilog_dir: + command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir] + if args.vpr_fpga_verilog_print_top_tb: + command += ["--fpga_verilog_print_top_testbench"] + if args.vpr_fpga_verilog_print_input_blif_tb: + command += ["--fpga_verilog_print_input_blif_testbench"] + if args.vpr_fpga_verilog_print_autocheck_top_testbench: + command += ["--fpga_verilog_print_autocheck_top_testbench", + args.top_module+"_output_verilog.v"] + if args.vpr_fpga_verilog_include_timing: + command += ["--fpga_verilog_include_timing"] + if args.vpr_fpga_verilog_include_signal_init: + command += ["--fpga_verilog_include_signal_init"] + if args.vpr_fpga_verilog_formal_verification_top_netlist: + command += ["--fpga_verilog_formal_verification_top_netlist"] + if args.vpr_fpga_verilog_print_modelsim_autodeck: + command += ["--fpga_verilog_print_modelsim_autodeck", + args.vpr_fpga_verilog_print_modelsim_autodeck] + if args.vpr_fpga_verilog_include_icarus_simulator: + command += ["--fpga_verilog_include_icarus_simulator"] + if args.vpr_fpga_verilog_print_report_timing_tcl: + command += ["--fpga_verilog_print_report_timing_tcl"] + if args.vpr_fpga_verilog_report_timing_rpt_path: + command += ["--fpga_verilog_report_timing_rpt_path", + args.vpr_fpga_verilog_report_timing_rpt_path] + if args.vpr_fpga_verilog_print_sdc_pnr: + command += ["--fpga_verilog_print_sdc_pnr"] + if args.vpr_fpga_verilog_print_user_defined_template: + command += ["--fpga_verilog_print_user_defined_template"] + if args.vpr_fpga_verilog_print_sdc_analysis: + command += ["--fpga_verilog_print_sdc_analysis"] -# # = = = = = = = = = = = = Create execution folder = = = = = = = = = = = = -# # TODO : this directory should change as //{conf_opt} -# curr_job_dir=os.path.join(task_run_dir, "tmp") -# if os.path.isdir(curr_job_dir): -# shutil.rmtree(curr_job_dir) -# os.makedirs(curr_job_dir) -# os.chdir(curr_job_dir) + # FPGA Bitstream Genration options + if args.vpr_fpga_verilog_print_sdc_analysis: + command += ["--fpga_bitstream_generator"] -# # = = = = = = = = = = = Create config file= = = = = = = = = = = = = = = = -# fpga_flow_conf=ConfigParser( -# strict=False, -# interpolation=ExtendedInterpolation()) -# fpga_flow_conf.read_dict(script_env_vars) -# fpga_flow_conf.read_file(open(fpga_flow_conf_tmpl)) + if args.vpr_fpga_x2p_rename_illegal_port or \ + args.vpr_fpga_spice or \ + args.vpr_fpga_verilog: + command += ["--fpga_x2p_rename_illegal_port"] -# # HACK: Find better way to resolve all interpolations in the script and write back -# for eachSection in fpga_flow_conf: -# for eachkey in fpga_flow_conf[eachSection].keys(): -# fpga_flow_conf[eachSection][eachkey] = fpga_flow_conf.get( -# eachSection, eachkey) + # Other VPR options + if args.vpr_place_clb_pin_remap: + command += ["--place_clb_pin_remap"] + if args.vpr_route_breadthfirst: + command += ["--router_algorithm", "breadth_first"] + if args.vpr_max_router_iteration: + command += ["--max_router_iterations", args.vpr_max_router_iteration] -# # Update configuration file with script realated parameters -# fpga_flow_conf["flow_conf"]["vpr_arch"] = archfile -# fpga_flow_conf["flow_conf"]["power_tech_xml"] = power_tech_file - -# # Remove extra path section and create configuration file -# fpga_flow_conf.remove_section("PATH") -# with open("openfpga_job.conf", 'w') as configfile: -# fpga_flow_conf.write(configfile) - -# # = = = = = = = = = = = Create Benchmark List file = = = = = = = = = = = = -# # TODO: This script strips common path from bechmark list and add -# # only single directory and filename to benchmarklist file -# # This can be imporoved by modifying fpga_flow script -# with open("openfpga_benchmark_list.txt", 'w') as configfile: -# configfile.write("# Circuit Names, fixed routing channel width\n") -# for eachBenchMark in benchmark_list: -# configfile.write(eachBenchMark.replace( -# fpga_flow_conf["dir_path"]["benchmark_dir"], "")) -# configfile.write(",30") -# configfile.write("\n") - -# # = = = = = = = = = Create fpga_flow_shell Script = = = = = = = = = = = = -# d = { -# "fpga_flow_script": shlex.quote(gc["script_default"]), -# "conf_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_job.conf")), -# "benchmark_list_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_benchmark_list.txt")), -# "csv_rpt_file": shlex.quote(os.path.join(os.getcwd(), os.path.join(gc["csv_rpt_dir"], "fpga_flow.csv"))), -# "verilog_output_path": shlex.quote(os.path.join(os.getcwd(), gc["verilog_output_path"])), -# "additional_params": " \\\n ".join(["-%s %s" % (key, value or "") for key, value in additional_fpga_flow_params.items()]) -# } -# result = Template(open(fpga_flow_script).read()).substitute(d) -# fpga_flow_script_path = os.path.join(os.getcwd(), "openfpga_flow.sh") -# with open(fpga_flow_script_path, 'w') as configfile: -# configfile.write(result) -# return fpga_flow_script_path + chan_width = None + try: + with open(logfile, 'w+') as output: + output.write(" ".join(command)+"\n") + process = subprocess.run(command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + for line in process.stdout.split('\n'): + if "Best routing" in line: + chan_width = re.search( + r"channel width factor of ([0-9]+)", line).group(1) + if "Circuit successfully routed" in line: + chan_width = re.search( + r"a channel width factor of ([0-9]+)", line).group(1) + output.write(process.stdout) + if process.returncode: + logger.info("Standard VPR run failed with returncode %d", + process.returncode) + except: + logger.exception("Failed to run VPR") + clean_up_and_exit("") + logger.info("VPR output is written in file %s" % logfile) + return int(chan_width) -# def run_single_script(s, script_path): -# logging.debug('Waiting to join the pool') -# with s: -# name = threading.currentThread().getName() -# subprocess.run(["bash", script_path], stdout=subprocess.PIPE) -# logging.info("%s Finished " % name) +def run_vpr_route(bench_blif, fixed_chan_width, logfile): + command = [cad_tools["vpr_path"], + args.arch_file, + bench_blif, + "--net_file", args.top_module+"_vpr.net", + "--place_file", args.top_module+"_vpr.place", + "--route_file", args.top_module+"_vpr.route", + "--full_stats", "--nodisp" + ] + if args.power: + command += [ + "--power", + "--activity_file", args.top_module+"_ace_out.act", + "--tech_properties", args.power_tech] + if fixed_chan_width >= 0: + command += ["-route_chan_width", "%d" % fixed_chan_width] + + # VPR - SPICE options + if args.power and args.vpr_fpga_spice: + command += "--fpga_spice" + if args.vpr_fpga_spice_print_cbsbtb: + command += ["--print_spice_cb_mux_testbench", + "--print_spice_sb_mux_testbench"] + if args.vpr_fpga_spice_print_pbtb: + command += ["--print_spice_pb_mux_testbench", + "--print_spice_lut_testbench", + "--print_spice_hardlogic_testbench"] + if args.vpr_fpga_spice_print_gridtb: + command += ["--print_spice_grid_testbench"] + if args.vpr_fpga_spice_print_toptb: + command += ["--print_spice_top_testbench"] + if args.vpr_fpga_spice_leakage_only: + command += ["--fpga_spice_leakage_only"] + if args.vpr_fpga_spice_parasitic_net_estimation_off: + command += ["--fpga_spice_parasitic_net_estimation_off"] + + if args.vpr_fpga_verilog: + command += ["--fpga_verilog"] + if args.vpr_fpga_x2p_rename_illegal_port: + command += ["--fpga_x2p_rename_illegal_port"] + + if args.vpr_max_router_iteration: + command += ["--max_router_iterations", args.vpr_max_router_iteration] + if args.vpr_route_breadthfirst: + command += ["--router_algorithm", "breadth_first"] + chan_width = None + try: + with open(logfile, 'w+') as output: + output.write(" ".join(command)+"\n") + process = subprocess.run(command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + for line in process.stdout.split('\n'): + if "Best routing" in line: + chan_width = re.search( + r"channel width factor of ([0-9]+)", line).group(1) + if "Circuit successfully routed" in line: + chan_width = re.search( + r"a channel width factor of ([0-9]+)", line).group(1) + output.write(process.stdout) + if process.returncode: + logger.info("Standard VPR run failed with returncode %d", + process.returncode) + except: + logger.exception("Failed to run VPR") + clean_up_and_exit("") + logger.info("VPR output is written in file %s" % logfile) + return chan_width -# def run_actions(actions): -# thread_sema = threading.Semaphore(args.maxthreads) -# thred_list = [] -# for index, eachAction in enumerate(actions): -# t = threading.Thread(target=run_single_script, -# name='benchmark_' + str(index), -# args=(thread_sema, eachAction)) -# t.start() -# thred_list.append(t) +def extract_vpr_stats(logfile): + # TODO: Sloppy code need improovement + # Without changing config input format -# for eachthread in thred_list: -# eachthread.join() + vpr_log = open(logfile).read() + resultDict = {} + for name, value in config.items("DEFAULT_PARSE_RESULT_VPR"): + reg_string, _ = value.split(",") + match = re.search(reg_string[1:-1], vpr_log) + if match: + extract_val = match.group(1) + resultDict[name] = extract_val + + dummyparser = ConfigParser() + dummyparser.read_dict({args.top_module+"_RESULTS": resultDict}) + + with open('vpr_stat.result', 'w') as configfile: + dummyparser.write(configfile) + logger.info("VPR statistics is extracted in file vpr_stat.result") + + +def extract_vpr_power_esti(logfile): + vpr_log = open(logfile).read() + resultDict = {} + for name, value in config.items("DEFAULT_PARSE_RESULT_VPR"): + reg_string, _ = value.split(",") + match = re.search(reg_string[1:-1], vpr_log) + if match: + extract_val = match.group(1) + resultDict[name] = extract_val + + dummyparser = ConfigParser() + dummyparser.read_dict({args.top_module+"_RESULTS": resultDict}) + + with open('vpr_power_stat.result', 'w') as configfile: + dummyparser.write(configfile) + logger.info("VPR_Power statistics are extracted vpr_power_stat.result") + + +def run_rewrite_verilog(): + # Rewrite the verilog after optimization + script_cmd = [ + "read_blif %s" % args.top_module+"_ace_corrected_out.blif", + "write_verilog %s" % args.top_module+"_output_verilog.v" + ] + command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] + try: + with open('yosys_rewrite_veri_output.txt', 'w+') as output: + process = subprocess.run(command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.info("Rewrite veri yosys run failed with returncode %d", + process.returncode) + except: + logger.exception("Failed to run VPR") + clean_up_and_exit("") + logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt") + + +def run_netlists_verification(): + compiled_file = "compiled_"+args.top_module + # include_netlists = args.top_module+"_include_netlists.v" + tb_top_formal = args.top_module+"_top_formal_verification_random_tb" + tb_top_autochecked = args.top_module+"_autocheck_top_tb" + # netlists_path = args.vpr_fpga_verilog_dir_val+"/SRC/" + + command = [cad_tools["iverilog_path"]] + command += ["-o", compiled_file] + command += [cad_tools["include_netlist_verification"]] + command += ["-s"] + if args.vpr_fpga_verilog_formal_verification_top_netlist: + command += [tb_top_formal] + else: + command += [tb_top_autochecked] + run_command("iverilog_verification", "iverilog_output.txt", command) + + vvp_command = ["vvp", compiled_file] + run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) + + +def run_command(taskname, logfile, command, exit_if_fail=True): + try: + with open(logfile, 'w+') as output: + output.write(" ".join(command)+"\n") + process = subprocess.run(command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.error("%s run failed with returncode %d" % + (taskname, process.returncode)) + except: + logger.exception() + if exit_if_fail: + clean_up_and_exit("Failed to run %s task" % taskname) + logger.info("%s is written in file %s" % (taskname, logfile)) + + +def external_call(parent_logger=None, passed_args=[]): + global logger, args + parent_logger = parent_logger + args = parser.parse_args(passed_args) + main() if __name__ == "__main__": + # Setting up print and logging system + logging.basicConfig(level=logging.INFO, + format='%(levelname)s (%(threadName)-9s) - %(message)s') + logger = logging.getLogger('OpenFPGA_Flow_Logs') + + # Parse commandline argument + args = parser.parse_args() main() diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index e9c1eb948..e9439427b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -9,31 +9,35 @@ import glob import subprocess import threading from string import Template +import pprint -# # Configure logging system +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configure logging system +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = logging.basicConfig(level=logging.INFO, format='%(levelname)s (%(threadName)-9s) - %(message)s') logger = logging.getLogger('OpenFPGA_Task_logs') -# # Reading command line arguments + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Read commandline arguments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = parser = argparse.ArgumentParser() parser.add_argument('tasks', nargs='+') -parser.add_argument('--maxthreads', - type=int, - default=2, - help="Number of fpga_flow threads to run " + - "default = 2, Typically <= Number of processors on the system") -parser.add_argument('--config', help="script configuration file") +parser.add_argument('--maxthreads', type=int, default=2, + help="Number of fpga_flow threads to run default = 2," + + "Typically <= Number of processors on the system") +parser.add_argument('--config', help="Override default configuration") args = parser.parse_args() -# # Reading configuration file to get all the paths -# # Replace variables in the file with absolute paths +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Read script configuration file +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = task_script_dir = os.path.dirname(os.path.abspath(__file__)) script_env_vars = ({"PATH": { "OPENFPGA_FLOW_PATH": task_script_dir, - "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir)) -}}) - + "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, + os.pardir))}}) config = ConfigParser(interpolation=ExtendedInterpolation()) config.read_dict(script_env_vars) config.read_file(open(os.path.join(task_script_dir, 'run_fpga_task.conf'))) @@ -41,17 +45,19 @@ gc = config["GENERAL CONFIGURATION"] def main(): - # processors = os.cpu_count() task_action = [] + validate_command_line_arguments() for eachtask in args.tasks: logger.info("Currently running task %s" % eachtask) - task_action += generate_single_task_actions(eachtask) - run_actions(task_action) + task_action += generate_each_task_actions(eachtask) + pprint.pprint(task_action) + # run_actions(task_action) logger.info("Task execution completed") exit() -# ================================= -# # Subroutines start here -# ================================= + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Subroutines starts here +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = def clean_up_and_exit(msg): @@ -60,10 +66,16 @@ def clean_up_and_exit(msg): exit() -def generate_single_task_actions(taskname): +def validate_command_line_arguments(): + pass + + +def generate_each_task_actions(taskname): """ This script generates all the scripts required for each benchmark """ + + # Check if task directory exists and consistent curr_task_dir = os.path.join(gc["task_dir"], taskname) if not os.path.isdir(curr_task_dir): clean_up_and_exit("Task directory not found") @@ -74,53 +86,101 @@ def generate_single_task_actions(taskname): clean_up_and_exit( "Missing configuration file for task %s" % curr_task_dir) + # Create run directory for current task run ./runxxx + run_dirs = [int(os.path.basename(x)[-3:]) for x in glob.glob('run*[0-9]')] + curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1) + try: + os.mkdir(curr_run_dir) + if os.path.islink('latest'): + os.unlink("latest") + os.symlink(curr_run_dir, "latest") + logger.info('Created "%s" directory for current task run' % + curr_run_dir) + except: + logger.exception() + logger.error("Failed to create new run directory in task directory") + + # Read task configuration file and check consistency task_conf = ConfigParser(allow_no_value=True, interpolation=ExtendedInterpolation()) - task_conf.optionxform = str task_conf.read_dict(script_env_vars) task_conf.read_file(open(curr_task_conf_file)) - # Check required sections in config file + required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"] missing_section = list(set(required_sec)-set(task_conf.sections())) if missing_section: - clean_up_and_exit( - "Missing section %s in task configuration file" % " ".join(missing_section)) + clean_up_and_exit("Missing sections %s" % " ".join(missing_section) + + " in task configuration file") - benchmark_list = [] - for _, bench_file in task_conf["BENCHMARKS"].items(): - if(glob.glob(bench_file)): - benchmark_list.append(bench_file) - else: - logger.warning( - "File Not Found: Skipping %s benchmark " % bench_file) - - # Check if all benchmark/architecture files exits + # Check if specified architecture files exist archfile_list = [] for _, arch_file in task_conf["ARCHITECTURES"].items(): arch_full_path = arch_file if os.path.isfile(arch_full_path): archfile_list.append(arch_full_path) else: - logger.warning( - "File Not Found: Skipping %s architecture " % arch_file) + clean_up_and_exit("Architecture file not found: " + + "%s " % arch_file) - script_list = [] - for eacharch in archfile_list: - script_list.append(create_run_script(gc["temp_run_dir"], - eacharch, - benchmark_list, - task_conf["GENERAL"]["power_tech_file"], - task_conf["SCRIPT_PARAM"])) - return script_list + # Check if specified benchmark files exist + benchmark_list, bench_files = [], [] + for bech_name, each_benchmark in task_conf["BENCHMARKS"].items(): + for eachpath in each_benchmark.split(","): + bench_files += glob.glob(eachpath) + for eachfile in bench_files: + if not os.path.isfile(eachfile): + clean_up_and_exit("Missing source file %s in benchmark %s " % + (eachfile, bech_name)) + + ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common") + benchmark_list.append({ + "files": bench_files, + "top_module": task_conf.get("SYNTHESIS_PARAM", bech_name+"_top", + fallback="top"), + "ys_script": task_conf.get("SYNTHESIS_PARAM", bech_name+"_yosys", + fallback=ys_for_task) + }) + + for eachbench in benchmark_list: + pprint.pprint(eachbench) + + # Create OpenFPGA flow run commnad for each combination of + # architecture, benchmark and parameters + flow_run_cmd_list = [] + print(archfile_list) + print(benchmark_list) + # for arch in archfile_list: + # for bench in benchmark_list: + # flow_run_dir = get_flow_rundir(arch, bench["top_module"]) + # print(flow_run_dir) + # flow_run_cmd_list.append(create_run_script( + # gc["temp_run_dir"], + # arch, + # bench, + # task_conf["GENERAL"]["power_tech_file"], + # task_conf["SCRIPT_PARAM"])) + return flow_run_cmd_list -def create_run_script(task_run_dir, archfile, benchmark_list, power_tech_file, additional_fpga_flow_params): +def get_flow_rundir(arch, top_module, flow_params=None): + path = [ + os.path.basename(arch).replace(".xml", ""), + top_module, + flow_params if flow_params else "common" + ] + return os.path.join(*path) + + +def create_run_script(curr_job_dir, archfile, benchmark_list, + power_tech_file, additional_fpga_flow_params): """ - Create_run_script function accespts run directory, architecture list and + Create_run_script function accepts run directory, architecture list and fpga_flow configuration file and prepare final executable fpga_flow script TODO : Replace this section after convert fpga_flow to python script Config file creation and bechnmark list can be skipped """ + print(archfile) + return # = = = = = = = = = File/Directory Consitancy Check = = = = = = = = = = if not os.path.isdir(gc["misc_dir"]): clean_up_and_exit("Miscellaneous directory does not exist") @@ -136,61 +196,61 @@ def create_run_script(task_run_dir, archfile, benchmark_list, power_tech_file, a fpga_flow_conf_tmpl) # = = = = = = = = = = = = Create execution folder = = = = = = = = = = = = - # TODO : this directory should change as //{conf_opt} - curr_job_dir = os.path.join(task_run_dir, "tmp") if os.path.isdir(curr_job_dir): shutil.rmtree(curr_job_dir) os.makedirs(curr_job_dir) - os.chdir(curr_job_dir) - # = = = = = = = = = = = Create config file= = = = = = = = = = = = = = = = - fpga_flow_conf = ConfigParser( - strict=False, - interpolation=ExtendedInterpolation()) - fpga_flow_conf.read_dict(script_env_vars) - fpga_flow_conf.read_file(open(fpga_flow_conf_tmpl)) + # Make execution command to run Open FPGA flow + command = [archfile] + benchmark_list - # HACK: Find better way to resolve all interpolations in the script and write back - for eachSection in fpga_flow_conf: - for eachkey in fpga_flow_conf[eachSection].keys(): - fpga_flow_conf[eachSection][eachkey] = fpga_flow_conf.get( - eachSection, eachkey) + # # = = = = = = = = = = = Create config file= = = = = = = = = = = = = = = = + # fpga_flow_conf = ConfigParser( + # strict=False, + # interpolation=ExtendedInterpolation()) + # fpga_flow_conf.read_dict(script_env_vars) + # fpga_flow_conf.read_file(open(fpga_flow_conf_tmpl)) - # Update configuration file with script realated parameters - fpga_flow_conf["flow_conf"]["vpr_arch"] = archfile - fpga_flow_conf["flow_conf"]["power_tech_xml"] = power_tech_file + # # HACK: Find better way to resolve all interpolations in the script and write back + # for eachSection in fpga_flow_conf: + # for eachkey in fpga_flow_conf[eachSection].keys(): + # fpga_flow_conf[eachSection][eachkey] = fpga_flow_conf.get( + # eachSection, eachkey) - # Remove extra path section and create configuration file - fpga_flow_conf.remove_section("PATH") - with open("openfpga_job.conf", 'w') as configfile: - fpga_flow_conf.write(configfile) + # # Update configuration file with script realated parameters + # fpga_flow_conf["flow_conf"]["vpr_arch"] = archfile + # fpga_flow_conf["flow_conf"]["power_tech_xml"] = power_tech_file - # = = = = = = = = = = = Create Benchmark List file = = = = = = = = = = = = - # TODO: This script strips common path from bechmark list and add - # only single directory and filename to benchmarklist file - # This can be imporoved by modifying fpga_flow script - with open("openfpga_benchmark_list.txt", 'w') as configfile: - configfile.write("# Circuit Names, fixed routing channel width\n") - for eachBenchMark in benchmark_list: - configfile.write(eachBenchMark.replace( - fpga_flow_conf["dir_path"]["benchmark_dir"], "")) - configfile.write(",30") - configfile.write("\n") + # # Remove extra path section and create configuration file + # fpga_flow_conf.remove_section("PATH") + # with open("openfpga_job.conf", 'w') as configfile: + # fpga_flow_conf.write(configfile) - # = = = = = = = = = Create fpga_flow_shell Script = = = = = = = = = = = = - d = { - "fpga_flow_script": shlex.quote(gc["script_default"]), - "conf_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_job.conf")), - "benchmark_list_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_benchmark_list.txt")), - "csv_rpt_file": shlex.quote(os.path.join(os.getcwd(), os.path.join(gc["csv_rpt_dir"], "fpga_flow.csv"))), - "verilog_output_path": shlex.quote(os.path.join(os.getcwd(), gc["verilog_output_path"])), - "additional_params": " \\\n ".join(["-%s %s" % (key, value or "") for key, value in additional_fpga_flow_params.items()]) - } - result = Template(open(fpga_flow_script).read()).substitute(d) - fpga_flow_script_path = os.path.join(os.getcwd(), "openfpga_flow.sh") - with open(fpga_flow_script_path, 'w') as configfile: - configfile.write(result) - return fpga_flow_script_path + # # = = = = = = = = = = = Create Benchmark List file = = = = = = = = = = = = + # # TODO: This script strips common path from bechmark list and add + # # only single directory and filename to benchmarklist file + # # This can be imporoved by modifying fpga_flow script + # with open("openfpga_benchmark_list.txt", 'w') as configfile: + # configfile.write("# Circuit Names, fixed routing channel width\n") + # for eachBenchMark in benchmark_list: + # configfile.write(eachBenchMark.replace( + # fpga_flow_conf["dir_path"]["benchmark_dir"], "")) + # configfile.write(",30") + # configfile.write("\n") + + # # = = = = = = = = = Create fpga_flow_shell Script = = = = = = = = = = = = + # d = { + # "fpga_flow_script": shlex.quote(gc["script_default"]), + # "conf_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_job.conf")), + # "benchmark_list_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_benchmark_list.txt")), + # "csv_rpt_file": shlex.quote(os.path.join(os.getcwd(), os.path.join(gc["csv_rpt_dir"], "fpga_flow.csv"))), + # "verilog_output_path": shlex.quote(os.path.join(os.getcwd(), gc["verilog_output_path"])), + # "additional_params": " \\\n ".join(["-%s %s" % (key, value or "") for key, value in additional_fpga_flow_params.items()]) + # } + # result = Template(open(fpga_flow_script).read()).substitute(d) + # fpga_flow_script_path = os.path.join(os.getcwd(), "openfpga_flow.sh") + # with open(fpga_flow_script_path, 'w') as configfile: + # configfile.write(result) + return command def run_single_script(s, script_path): From 4eb046760b4acf1e4ade6f42953dd0c11e9ea272 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 15 Aug 2019 21:57:59 -0600 Subject: [PATCH 058/482] still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix --- .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 8 +- .../SRC/fpga_x2p/base/fpga_x2p_mux_utils.c | 23 ++-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 27 ++++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 2 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 112 +++++++++--------- 5 files changed, 100 insertions(+), 72 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index 127cc0adb..844eb16e3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -199,9 +199,9 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, if ( (TRUE == cur_spice_model->design_tech_info.mux_info->local_encoder) && (2 < num_input_size) ) { if (SPICE_MODEL_STRUCTURE_ONELEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_sram_bits = ceil(log(num_sram_bits + 1) / log(2)); + num_sram_bits = determine_mux_local_encoder_num_inputs(num_sram_bits); } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_sram_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * ceil(log(num_sram_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level + 1) / log(2)); + num_sram_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * determine_mux_local_encoder_num_inputs(num_sram_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level); } } break; @@ -721,9 +721,9 @@ int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, if ( (TRUE == cur_spice_model->design_tech_info.mux_info->local_encoder) && (2 < num_input_size) ) { if (SPICE_MODEL_STRUCTURE_ONELEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_conf_bits = ceil(log(num_conf_bits + 1) / log(2)); + num_conf_bits = determine_mux_local_encoder_num_inputs(num_conf_bits); } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * ceil(log(num_conf_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level + 1) / log(2)); + num_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * determine_mux_local_encoder_num_inputs(num_conf_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level); } } break; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c index f47574b08..5e031e0c3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c @@ -204,7 +204,7 @@ int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, * We plus 1, which is all-zero condition for outputs ***************************************************************************************/ int determine_mux_local_encoder_num_inputs(int num_outputs) { - return ceil(log(num_outputs + 1) / log(2)); + return ceil(log(num_outputs) / log(2)); } /* Decoding a one-level MUX: @@ -233,8 +233,8 @@ int* decode_onelevel_mux_sram_bits(int fan_in, if (TRUE == use_local_encoder) { /* The encoder will convert the path_id to a binary number - * For example: when path_id=3, using a 4-input encoder - * the sram_bits will be the 4-digit binary number of 3: 0011 + * For example: when path_id=3 (use the 4th input), using a 4-input encoder + * the sram_bits will be the 4-digit binary number of 3: 0100 */ ret = my_itobin_int(path_id, num_sram_bits); } else { @@ -325,20 +325,25 @@ int* decode_multilevel_mux_sram_bits(int fan_in, /* Walk through each level and find the path_id and encode it */ for (int ilvl = 0; ilvl < mux_level; ++ilvl) { int start_idx = num_input_basis * ilvl; - int end_idx = num_input_basis * (ilvl + 1) - 1; - int encoded_path_id = 0; + int end_idx = num_input_basis * (ilvl + 1); + int encoded_path_id = -1; int checker = 0; for (int idx = start_idx; idx < end_idx; ++idx) { - if ('1' == ret[idx]) { + if (1 == ret[idx]) { checker++; - encoded_path_id = idx; + encoded_path_id = idx - start_idx; } } /* There should be at most one '1' */ assert( (0 == checker) || (1 == checker)); + /* If all-zero bits are found, it means that the stage is not used, assign to the last input by default */ + if (0 == checker) { + encoded_path_id = num_input_basis - 1; + } + assert (-1 != encoded_path_id); /* The encoder will convert the path_id to a binary number - * For example: when path_id=3, using a 4-input encoder - * the sram_bits will be the 4-digit binary number of 3: 0011 + * For example: when path_id=3 (use the 4th input), using a 4-input encoder + * the sram_bits will be the 4-digit binary number of 3: 0100 */ int* tmp_bits = my_itobin_int(encoded_path_id, num_bits_per_level); /* Copy tmp_bits to encoded bits */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index c30ac6926..5166a27a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -153,6 +153,7 @@ int create_dir_path(char* dir_path) { exit(1); return 0; } + return 0; } /* Cat string2 to the end of string1 */ @@ -576,6 +577,28 @@ t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, return ret; } +/* Convert an integer to an one-hot encoding integer array */ +char* my_ito1hot(int in_int, int bin_len) { + char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); + + /* Make sure we do not have any overflow! */ + if (! ( (-1 < in_int) && (in_int <= bin_len) ) ) + assert ( (-1 < in_int) && (in_int <= bin_len) ); + + /* Initialize */ + for (int i = 0; i < bin_len - 1; i++) { + ret[i] = '0'; + } + sprintf(ret + bin_len - 1, "%s", "0"); + + if (bin_len == in_int) { + return ret; /* all zero case */ + } + ret[in_int] = '1'; /* Keep a good sequence of bits */ + + return ret; +} + /* Converter an integer to a binary string */ int* my_itobin_int(int in_int, int bin_len) { int* ret = (int*) my_calloc (bin_len, sizeof(int)); @@ -588,7 +611,7 @@ int* my_itobin_int(int in_int, int bin_len) { temp = in_int; for (i = 0; i < bin_len; i++) { if (1 == temp % 2) { - ret[i] = 1; + ret[i] = 1; /* Keep a good sequence of bits */ } temp = temp / 2; } @@ -596,7 +619,6 @@ int* my_itobin_int(int in_int, int bin_len) { return ret; } - /* Converter an integer to a binary string */ char* my_itobin(int in_int, int bin_len) { char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); @@ -622,6 +644,7 @@ char* my_itobin(int in_int, int bin_len) { return ret; } + /* Convert a integer to a string*/ char* my_itoa(int input) { char* ret = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index b488456e6..bf8d0beaa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -58,6 +58,8 @@ t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_mod t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, e_spice_trans_type trans_type); +char* my_ito1hot(int in_int, int bin_len); + char* my_itobin(int in_int, int bin_len); int* my_itobin_int(int in_int, int bin_len); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index a820a5102..9f0369d9a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1497,10 +1497,10 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { /* Print local wires for local encoders */ - fprintf(fp, "wire [%d:0] %s_data;\n", + fprintf(fp, "wire [0:%d] %s_data;\n", spice_mux_arch.num_level * spice_mux_arch.num_input_basis - 1, sram_port[0]->prefix); - fprintf(fp, "wire [%d:0] %s_data_inv;\n", + fprintf(fp, "wire [0:%d] %s_data_inv;\n", spice_mux_arch.num_level * spice_mux_arch.num_input_basis - 1, sram_port[0]->prefix); } @@ -1670,6 +1670,37 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "wire [0:%d] mux2_l%d_in; \n", spice_mux_arch.num_input - 1, 1); /* input0 */ fprintf(fp, "wire [0:%d] mux2_l%d_in; \n", 0, 0); /* output */ + /* Instanciate local encoder circuit here */ + if ( (TRUE == spice_model.design_tech_info.mux_info->local_encoder) + && ( 2 < spice_mux_arch.num_input) ) { + /* Get the number of inputs */ + int num_outputs = spice_mux_arch.num_input; + int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); + + /* Print local wires for local encoders */ + fprintf(fp, "wire [0:%d] %s_data;\n", + spice_mux_arch.num_input - 1, + sram_port[0]->prefix); + fprintf(fp, "wire [0:%d] %s_data_inv;\n", + spice_mux_arch.num_input - 1, + sram_port[0]->prefix); + /* Find the decoder name */ + fprintf(fp, "%s %s_0_ (", + generate_verilog_decoder_subckt_name(num_inputs, num_outputs), + generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); + if (true == is_explicit_mapping) { + fprintf(fp, ".addr(%s), .data(%s_data), .data_inv(%s_data_inv) );\n", + sram_port[0]->prefix, + sram_port[0]->prefix, + sram_port[0]->prefix); + } else { + fprintf(fp, "%s, %s_data, %s_data_inv);\n", + sram_port[0]->prefix, + sram_port[0]->prefix, + sram_port[0]->prefix); + } + } + fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, @@ -1740,38 +1771,6 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, } fprintf(fp, "\n"); fprintf(fp, ");\n"); - - if (2 < spice_mux_arch.num_input) { - /* Instanciate local encoder circuit here */ - if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { - /* Get the number of inputs */ - int num_outputs = spice_mux_arch.num_input - 1; - int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); - - /* Print local wires for local encoders */ - fprintf(fp, "wire [%d:0] %s_data;\n", - spice_mux_arch.num_input - 1, - sram_port[0]->prefix); - fprintf(fp, "wire [%d:0] %s_data_inv;\n", - spice_mux_arch.num_input - 1, - sram_port[0]->prefix); - /* Find the decoder name */ - fprintf(fp, "%s %s_0_ (", - generate_verilog_decoder_subckt_name(num_inputs, num_outputs), - generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); - if (true == is_explicit_mapping) { - fprintf(fp, ".addr(%s), .data(%s_data), .data_inv(%s_data_inv) );\n", - sram_port[0]->prefix, - sram_port[0]->prefix, - sram_port[0]->prefix); - } else { - fprintf(fp, "%s, %s_data, %s_data_inv);\n", - sram_port[0]->prefix, - sram_port[0]->prefix, - sram_port[0]->prefix); - } - } - } return; } @@ -2870,9 +2869,8 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, * Outputs * * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) - * We plus 1, which is all-zero condition for outputs + * Considering this fact, there are only num_of_outputs conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) ***************************************************************************************/ static void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { @@ -2901,7 +2899,8 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { 0, num_inputs - 1); fprintf(fp, ",\n"); /* Outputs */ - dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, + fprintf(fp, "output "); + dump_verilog_generic_port(fp, VERILOG_PORT_REG, "data", 0, num_outputs - 1); fprintf(fp, ",\n"); @@ -2910,11 +2909,6 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { 0, num_outputs - 1); fprintf(fp, "\n);\n"); - dump_verilog_generic_port(fp, VERILOG_PORT_REG, - "data_reg", - 0, num_outputs - 1); - fprintf(fp, ";\n"); - /* Print the truth table of this encoder */ /* Internal logics */ /* We use a magic number -1 as the addr=1 should be mapped to ...1 @@ -2925,23 +2919,27 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { * will give a all-zero code * For example: * data is 5-bit while addr is 3-bit - * data=8'b0_0000 is reserved by addr=3'b000; - * data=8'b0_0001 will be encoded to addr=3'b001; - * data=8'b0_0010 will be encoded to addr=3'b010; - * data=8'b0_0100 will be encoded to addr=3'b011; - * data=8'b0_1000 will be encoded to addr=3'b100; - * data=8'b1_0000 will be encoded to addr=3'b101; + * data=8'b0_0000 will be encoded to addr=3'b001; + * data=8'b0_0001 will be encoded to addr=3'b010; + * data=8'b0_0010 will be encoded to addr=3'b011; + * data=8'b0_0100 will be encoded to addr=3'b100; + * data=8'b0_1000 will be encoded to addr=3'b101; + * data=8'b1_0000 will be encoded to addr=3'b110; * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000; */ - fprintf(fp, "always@(addr, data)\n"); - fprintf(fp, "begin\n"); - fprintf(fp, "\tdata_reg = %d'b0;\n", num_outputs); - fprintf(fp, "\tif ((0 < addr) && (addr < %d) ) begin\n", num_outputs); - fprintf(fp, "\t\tdata_reg = 1'b1 << (addr - 1);\n"); - fprintf(fp, "\tend\n"); - fprintf(fp, "end\n"); - fprintf(fp, "assign data = data_reg;\n"); + fprintf(fp, "always@(addr)\n"); + fprintf(fp, "case (addr)\n"); + /* Create a string for addr and data */ + for (int i = 0; i < num_outputs; ++i) { + fprintf(fp, "\t%d'b%s : data = %d'b%s;\n", + num_inputs, my_itobin(i, num_inputs), + num_outputs, my_ito1hot(i, num_outputs)); + } + fprintf(fp, "\tdefault : data = %d'b%s;\n", + num_outputs, my_ito1hot(num_outputs, num_outputs)); + fprintf(fp, "endcase\n"); + fprintf(fp, "assign data_inv = ~data;\n"); From 901932a4fc9ecdbd569dae837bc235563accc12e Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 16 Aug 2019 09:44:50 -0600 Subject: [PATCH 059/482] First draft: Working openfpga task flow --- openfpga_flow/scripts/run_fpga_flow.py | 13 +- openfpga_flow/scripts/run_fpga_task.conf | 7 +- openfpga_flow/scripts/run_fpga_task.py | 161 ++++++++---------- .../tasks/basic_flow/config/task.conf | 50 ++---- 4 files changed, 100 insertions(+), 131 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 8c1e5d56e..9ce20fd1b 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -1,4 +1,5 @@ import os +import sys import shutil import time import shlex @@ -188,6 +189,7 @@ config, cad_tools = None, None def main(): + logger.debug("Script Launched in "+os.getcwd()) check_required_file() read_script_config() validate_command_line_arguments() @@ -235,6 +237,8 @@ def read_script_config(): config.read_file(open(default_cad_tool_conf)) if args.cad_tool_conf: config.read_file(open(args.cad_tool_conf)) + if not "CAD_TOOLS_PATH" in config.sections(): + clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config") cad_tools = config["CAD_TOOLS_PATH"] @@ -251,7 +255,7 @@ def validate_command_line_arguments(): Throw error for directory in benchmark check if args.powertech_file is provided for power measurement """ - logger.info("Parsing commnad line arguments - Pending implementation") + logger.info("Validating commnad line arguments - Pending implementation") # Filter provided architecrue files args.arch_file = os.path.abspath(args.arch_file) @@ -272,6 +276,8 @@ def validate_command_line_arguments(): if not os.path.isfile(args.power_tech): clean_up_and_exit( "Power Tech file not found. -%s", args.power_tech) + + args.run_dir = os.path.abspath(args.run_dir) pass @@ -328,6 +334,7 @@ def prepare_run_directory(run_dir): def clean_up_and_exit(msg, clean=False): + logger.error("Current working directory : " + os.getcwd()) logger.error(msg) logger.error("Exiting . . . . . .") exit() @@ -840,14 +847,14 @@ def run_command(taskname, logfile, command, exit_if_fail=True): def external_call(parent_logger=None, passed_args=[]): global logger, args - parent_logger = parent_logger + logger = parent_logger args = parser.parse_args(passed_args) main() if __name__ == "__main__": # Setting up print and logging system - logging.basicConfig(level=logging.INFO, + logging.basicConfig(level=logging.INFO, stream=sys.stdout, format='%(levelname)s (%(threadName)-9s) - %(message)s') logger = logging.getLogger('OpenFPGA_Flow_Logs') diff --git a/openfpga_flow/scripts/run_fpga_task.conf b/openfpga_flow/scripts/run_fpga_task.conf index bb4bc24f1..2ccf44927 100644 --- a/openfpga_flow/scripts/run_fpga_task.conf +++ b/openfpga_flow/scripts/run_fpga_task.conf @@ -1,9 +1,4 @@ [GENERAL CONFIGURATION] task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks -circuits_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Verilog/MCNC/ -archs_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/arch misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc -script_default=${PATH:OPENFPGA_PATH}/fpga_flow/scripts/fpga_flow.pl -csv_rpt_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/csv_rpt/ -verilog_output_path=${PATH:OPENFPGA_PATH}/openfpga_flow/verilog_op/ -temp_run_dir=${PATH:OPENFPGA_PATH} \ No newline at end of file +script_default=${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index e9439427b..0c680e2c0 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -1,4 +1,5 @@ import os +import sys import shutil import time import shlex @@ -9,12 +10,13 @@ import glob import subprocess import threading from string import Template +import run_fpga_flow import pprint # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -logging.basicConfig(level=logging.INFO, +logging.basicConfig(level=logging.DEBUG, stream=sys.stdout, format='%(levelname)s (%(threadName)-9s) - %(message)s') logger = logging.getLogger('OpenFPGA_Task_logs') @@ -28,6 +30,8 @@ parser.add_argument('--maxthreads', type=int, default=2, help="Number of fpga_flow threads to run default = 2," + "Typically <= Number of processors on the system") parser.add_argument('--config', help="Override default configuration") +parser.add_argument('--test_run', action="store_true", + help="Dummy run shows final generated VPR commands") args = parser.parse_args() # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = @@ -45,13 +49,15 @@ gc = config["GENERAL CONFIGURATION"] def main(): - task_action = [] + validate_command_line_arguments() for eachtask in args.tasks: logger.info("Currently running task %s" % eachtask) - task_action += generate_each_task_actions(eachtask) - pprint.pprint(task_action) - # run_actions(task_action) + commands = generate_each_task_actions(eachtask) + if not args.test_run: + run_actions(commands) + else: + pprint.pprint(commands) logger.info("Task execution completed") exit() @@ -78,7 +84,7 @@ def generate_each_task_actions(taskname): # Check if task directory exists and consistent curr_task_dir = os.path.join(gc["task_dir"], taskname) if not os.path.isdir(curr_task_dir): - clean_up_and_exit("Task directory not found") + clean_up_and_exit("Task directory [%s] not found" % curr_task_dir) os.chdir(curr_task_dir) curr_task_conf_file = os.path.join(curr_task_dir, "config", "task.conf") @@ -97,8 +103,9 @@ def generate_each_task_actions(taskname): logger.info('Created "%s" directory for current task run' % curr_run_dir) except: - logger.exception() + logger.exception("") logger.error("Failed to create new run directory in task directory") + os.chdir(curr_run_dir) # Read task configuration file and check consistency task_conf = ConfigParser(allow_no_value=True, @@ -123,14 +130,15 @@ def generate_each_task_actions(taskname): "%s " % arch_file) # Check if specified benchmark files exist - benchmark_list, bench_files = [], [] + benchmark_list = [] for bech_name, each_benchmark in task_conf["BENCHMARKS"].items(): + bench_files = [] for eachpath in each_benchmark.split(","): - bench_files += glob.glob(eachpath) - for eachfile in bench_files: - if not os.path.isfile(eachfile): - clean_up_and_exit("Missing source file %s in benchmark %s " % - (eachfile, bech_name)) + files = glob.glob(eachpath) + if not len(files): + clean_up_and_exit(("No files added benchmark %s" % bech_name) + + " with path %s " % (eachpath)) + bench_files += files ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common") benchmark_list.append({ @@ -141,24 +149,15 @@ def generate_each_task_actions(taskname): fallback=ys_for_task) }) - for eachbench in benchmark_list: - pprint.pprint(eachbench) - # Create OpenFPGA flow run commnad for each combination of # architecture, benchmark and parameters flow_run_cmd_list = [] - print(archfile_list) - print(benchmark_list) - # for arch in archfile_list: - # for bench in benchmark_list: - # flow_run_dir = get_flow_rundir(arch, bench["top_module"]) - # print(flow_run_dir) - # flow_run_cmd_list.append(create_run_script( - # gc["temp_run_dir"], - # arch, - # bench, - # task_conf["GENERAL"]["power_tech_file"], - # task_conf["SCRIPT_PARAM"])) + + for arch in archfile_list: + for bench in benchmark_list: + flow_run_dir = get_flow_rundir(arch, bench["top_module"]) + cmd = create_run_command(flow_run_dir, arch, bench, task_conf) + flow_run_cmd_list.append(cmd) return flow_run_cmd_list @@ -168,19 +167,16 @@ def get_flow_rundir(arch, top_module, flow_params=None): top_module, flow_params if flow_params else "common" ] - return os.path.join(*path) + return os.path.abspath(os.path.join(*path)) -def create_run_script(curr_job_dir, archfile, benchmark_list, - power_tech_file, additional_fpga_flow_params): +def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): """ Create_run_script function accepts run directory, architecture list and fpga_flow configuration file and prepare final executable fpga_flow script TODO : Replace this section after convert fpga_flow to python script Config file creation and bechnmark list can be skipped """ - print(archfile) - return # = = = = = = = = = File/Directory Consitancy Check = = = = = = = = = = if not os.path.isdir(gc["misc_dir"]): clean_up_and_exit("Miscellaneous directory does not exist") @@ -197,77 +193,62 @@ def create_run_script(curr_job_dir, archfile, benchmark_list, # = = = = = = = = = = = = Create execution folder = = = = = = = = = = = = if os.path.isdir(curr_job_dir): - shutil.rmtree(curr_job_dir) + question = "One the result directory already exist.\n" + question += "%s\n" % curr_job_dir + reply = str(input(question+' (y/n): ')).lower().strip() + if reply[:1] in ['y', 'yes']: + shutil.rmtree(curr_job_dir) + else: + logger.info("Result directory removal denied by the user") + exit() os.makedirs(curr_job_dir) # Make execution command to run Open FPGA flow - command = [archfile] + benchmark_list + command = [archfile] + benchmark_obj["files"] + command += ["--top_module", benchmark_obj["top_module"]] + command += ["--run_dir", curr_job_dir] + if task_conf.getboolean("GENERAL", "power_analysis", fallback=False): + command += ["--power"] + command += ["--power_tech", + task_conf.get("GENERAL", "power_tech_file")] + if task_conf.getboolean("GENERAL", "spice_output", fallback=False): + command += ["--vpr_fpga_spice"] + if task_conf.getboolean("GENERAL", "verilog_output", fallback=False): + command += ["--vpr_fpga_verilog"] - # # = = = = = = = = = = = Create config file= = = = = = = = = = = = = = = = - # fpga_flow_conf = ConfigParser( - # strict=False, - # interpolation=ExtendedInterpolation()) - # fpga_flow_conf.read_dict(script_env_vars) - # fpga_flow_conf.read_file(open(fpga_flow_conf_tmpl)) - - # # HACK: Find better way to resolve all interpolations in the script and write back - # for eachSection in fpga_flow_conf: - # for eachkey in fpga_flow_conf[eachSection].keys(): - # fpga_flow_conf[eachSection][eachkey] = fpga_flow_conf.get( - # eachSection, eachkey) - - # # Update configuration file with script realated parameters - # fpga_flow_conf["flow_conf"]["vpr_arch"] = archfile - # fpga_flow_conf["flow_conf"]["power_tech_xml"] = power_tech_file - - # # Remove extra path section and create configuration file - # fpga_flow_conf.remove_section("PATH") - # with open("openfpga_job.conf", 'w') as configfile: - # fpga_flow_conf.write(configfile) - - # # = = = = = = = = = = = Create Benchmark List file = = = = = = = = = = = = - # # TODO: This script strips common path from bechmark list and add - # # only single directory and filename to benchmarklist file - # # This can be imporoved by modifying fpga_flow script - # with open("openfpga_benchmark_list.txt", 'w') as configfile: - # configfile.write("# Circuit Names, fixed routing channel width\n") - # for eachBenchMark in benchmark_list: - # configfile.write(eachBenchMark.replace( - # fpga_flow_conf["dir_path"]["benchmark_dir"], "")) - # configfile.write(",30") - # configfile.write("\n") - - # # = = = = = = = = = Create fpga_flow_shell Script = = = = = = = = = = = = - # d = { - # "fpga_flow_script": shlex.quote(gc["script_default"]), - # "conf_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_job.conf")), - # "benchmark_list_file": shlex.quote(os.path.join(os.getcwd(), "openfpga_benchmark_list.txt")), - # "csv_rpt_file": shlex.quote(os.path.join(os.getcwd(), os.path.join(gc["csv_rpt_dir"], "fpga_flow.csv"))), - # "verilog_output_path": shlex.quote(os.path.join(os.getcwd(), gc["verilog_output_path"])), - # "additional_params": " \\\n ".join(["-%s %s" % (key, value or "") for key, value in additional_fpga_flow_params.items()]) - # } - # result = Template(open(fpga_flow_script).read()).substitute(d) - # fpga_flow_script_path = os.path.join(os.getcwd(), "openfpga_flow.sh") - # with open(fpga_flow_script_path, 'w') as configfile: - # configfile.write(result) + # Add other paramters to pass + for key, values in task_conf["SCRIPT_PARAM"].items(): + command += ["--"+key, values] return command -def run_single_script(s, script_path): - logging.debug('Waiting to join the pool') +def run_single_script(s, command): + logger.debug('Added job in pool') with s: + logger.debug("Running OpenFPGA flow with " + " ".join(command)) name = threading.currentThread().getName() - subprocess.run(["bash", script_path], stdout=subprocess.PIPE) - logging.info("%s Finished " % name) + # run_fpga_flow.external_call(logger, command) + try: + logfile = "%s_out.log" % name + with open(logfile, 'w+') as output: + process = subprocess.run(["python3.5", gc["script_default"]]+command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + except: + logger.exception() + logger.info("%s Finished " % name) -def run_actions(actions): +def run_actions(actions_list): thread_sema = threading.Semaphore(args.maxthreads) thred_list = [] - for index, eachAction in enumerate(actions): + for index, commands in enumerate(actions_list): t = threading.Thread(target=run_single_script, - name='benchmark_' + str(index), - args=(thread_sema, eachAction)) + name='Job_%02d' % (index+1), + args=(thread_sema, commands)) t.start() thred_list.append(t) diff --git a/openfpga_flow/tasks/basic_flow/config/task.conf b/openfpga_flow/tasks/basic_flow/config/task.conf index c21b6dfb5..c7b4f243a 100644 --- a/openfpga_flow/tasks/basic_flow/config/task.conf +++ b/openfpga_flow/tasks/basic_flow/config/task.conf @@ -1,49 +1,35 @@ -############################################## +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments -############################################## +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + [GENERAL] -# General Parameters for the script -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml -# [Optional] Timeout for each fpga_flow script run in seconds -# Default = 20 min +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml +power_analysis = true +spice_output=false +verilog_output=false timeout_each_job = 20*60 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/*.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v [SYNTHESIS_PARAM] -# TODO: Not Implemented yet -# This section lists parameters required for yosys synthesis -# Need to update fpga_flow.pl script bench_yosys_common=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys -bench0_top = memory_controller +bench0_top = s298 +bench1_top = alu4 +bench2_top = s38417 bench0_yosys=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys [SCRIPT_PARAM] -# Currently these parameters are transfered to fpga_flow script -# but differeent combinations of parameters can be saved in the file and -# linked here as s file Example: -Default -Calculate_Power -GenerateSpice -N = 10 -K = 6 -ace_d = 0.5 -multi_thread = 1 -route_chan_width = 30 -vpr_fpga_x2p_rename_illegal_port = -vpr_fpga_verilog = -vpr_fpga_bitstream_generator = -vpr_fpga_verilog_print_autocheck_top_testbench = -vpr_fpga_verilog_include_timing = -vpr_fpga_verilog_include_signal_init = -vpr_fpga_verilog_formal_verification_top_netlist = -fix_route_chan_width = -power = -remove_designs = -vpr_fpga_spice_print_component_tb = -vpr_fpga_spice = spice_taskfile -vpr_fpga_spice_simulator_path = /uusoc/facility/cad_tools/Synopsys/lnis_tools/hspice/P2019 =.06/hspice/bin/ +min_route_chan_width=30 [POST_RUN] # Not Implemented yet From effbd332aa8b4716bd7958aec6bbffa5a01ae53f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 16 Aug 2019 10:59:44 -0600 Subject: [PATCH 060/482] Added task report generation --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- openfpga_flow/scripts/run_fpga_task.py | 53 +++++++++++++++++++++----- 2 files changed, 44 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 9ce20fd1b..9d55589f9 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -755,7 +755,7 @@ def extract_vpr_stats(logfile): resultDict[name] = extract_val dummyparser = ConfigParser() - dummyparser.read_dict({args.top_module+"_RESULTS": resultDict}) + dummyparser.read_dict({"RESULTS": resultDict}) with open('vpr_stat.result', 'w') as configfile: dummyparser.write(configfile) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 0c680e2c0..630c0da12 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -9,6 +9,7 @@ import logging import glob import subprocess import threading +import csv from string import Template import run_fpga_flow import pprint @@ -53,11 +54,12 @@ def main(): validate_command_line_arguments() for eachtask in args.tasks: logger.info("Currently running task %s" % eachtask) - commands = generate_each_task_actions(eachtask) + job_run_list = generate_each_task_actions(eachtask) if not args.test_run: - run_actions(commands) + run_actions(job_run_list) + collect_results(job_run_list) else: - pprint.pprint(commands) + pprint.pprint(job_run_list) logger.info("Task execution completed") exit() @@ -151,13 +153,19 @@ def generate_each_task_actions(taskname): # Create OpenFPGA flow run commnad for each combination of # architecture, benchmark and parameters + # Create run_job object [arch, bench, run_dir, commnad] flow_run_cmd_list = [] - - for arch in archfile_list: + for indx, arch in enumerate(archfile_list): for bench in benchmark_list: flow_run_dir = get_flow_rundir(arch, bench["top_module"]) - cmd = create_run_command(flow_run_dir, arch, bench, task_conf) - flow_run_cmd_list.append(cmd) + cmd = create_run_command( + flow_run_dir, arch, bench, task_conf) + flow_run_cmd_list.append({ + "arch": arch, + "bench": bench, + "name": "%s_arch%d" % (bench["top_module"], indx), + "run_dir": flow_run_dir, + "commands": cmd}) return flow_run_cmd_list @@ -242,13 +250,13 @@ def run_single_script(s, command): logger.info("%s Finished " % name) -def run_actions(actions_list): +def run_actions(job_run_list): thread_sema = threading.Semaphore(args.maxthreads) thred_list = [] - for index, commands in enumerate(actions_list): + for index, eachjob in enumerate(job_run_list): t = threading.Thread(target=run_single_script, name='Job_%02d' % (index+1), - args=(thread_sema, commands)) + args=(thread_sema, eachjob["commands"])) t.start() thred_list.append(t) @@ -256,5 +264,30 @@ def run_actions(actions_list): eachthread.join() +def collect_results(job_run_list): + task_result = [] + for run in job_run_list: + # Check if any result file exist + if not glob.glob(os.path.join(run["run_dir"], "*.result")): + logger.info("No result files found for %s" % run["name"]) + + # Read and merge result file + vpr_res = ConfigParser(allow_no_value=True, + interpolation=ExtendedInterpolation()) + vpr_res.read_file( + open(os.path.join(run["run_dir"], "vpr_stat.result"))) + result = dict(vpr_res["RESULTS"]) + result["name"] = run["name"] + task_result.append(result) + + pprint.pprint(task_result) + + with open("task_result.csv", 'w', newline='') as csvfile: + writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys()) + writer.writeheader() + for eachResult in task_result: + writer.writerow(eachResult) + + if __name__ == "__main__": main() From c43c3cdf257b4d8d7f07fab416229e2bc54e5435 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 16 Aug 2019 13:36:39 -0600 Subject: [PATCH 061/482] Added VPR output parse option --- openfpga_flow/scripts/run_fpga_flow.py | 24 ++++++++++++++++-------- openfpga_flow/scripts/run_fpga_task.py | 4 +--- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 9d55589f9..efdf01345 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -71,7 +71,7 @@ parser.add_argument('--ace_p', type=float, parser.add_argument('--black_box_ace', action='store_true') # VPR Options -parser.add_argument('--min_route_chan_width', type=int, +parser.add_argument('--min_route_chan_width', type=float, help="Turn on min_route_chan_width") parser.add_argument('--max_route_width_retry', type=int, default=100, help="Maximum iterations to perform to reroute") @@ -350,6 +350,7 @@ def run_yosys_with_abc(): lut_size = max([int(pb_type.find("input").get("num_pins")) for pb_type in root.iter("pb_type") if pb_type.get("class") == "lut"]) + logger.info("Extracted lut_size size from arch XML = %s", lut_size) logger.info("Running Yosys with lut_size = %s", lut_size) except: logger.exception("Failed to extract lut_size from XML file") @@ -491,11 +492,11 @@ def run_vpr(): # Minimum routing channel width if (args.min_route_chan_width): - logger.info("Executing minimum channel width routing") - min_channel_width *= 1+(args.min_route_chan_width/100) + min_channel_width *= args.min_route_chan_width min_channel_width = int(min_channel_width) min_channel_width += 1 if (min_channel_width % 2) else 0 - logger.info("Trying to route using %d channels" % min_channel_width) + logger.info(("Trying to route using %d channels" % min_channel_width) + + " (Slack of %d%%)" % ((args.min_route_chan_width-1)*100)) while(1): res = run_vpr_route(args.top_module+"_ace_corrected_out.blif", @@ -607,7 +608,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile): if args.vpr_fpga_verilog_include_signal_init: command += ["--fpga_verilog_include_signal_init"] if args.vpr_fpga_verilog_formal_verification_top_netlist: - command += ["--fpga_verilog_formal_verification_top_netlist"] + command += ["--fpga_verilog_print_formal_verification_top_netlist"] if args.vpr_fpga_verilog_print_modelsim_autodeck: command += ["--fpga_verilog_print_modelsim_autodeck", args.vpr_fpga_verilog_print_modelsim_autodeck] @@ -676,7 +677,8 @@ def run_vpr_route(bench_blif, fixed_chan_width, logfile): "--net_file", args.top_module+"_vpr.net", "--place_file", args.top_module+"_vpr.place", "--route_file", args.top_module+"_vpr.route", - "--full_stats", "--nodisp" + "--full_stats", "--nodisp", + "--route" ] if args.power: command += [ @@ -734,8 +736,9 @@ def run_vpr_route(bench_blif, fixed_chan_width, logfile): if process.returncode: logger.info("Standard VPR run failed with returncode %d", process.returncode) - except: + except Exception as e: logger.exception("Failed to run VPR") + process_failed_vpr_run(e.output) clean_up_and_exit("") logger.info("VPR output is written in file %s" % logfile) return chan_width @@ -852,10 +855,15 @@ def external_call(parent_logger=None, passed_args=[]): main() +def process_failed_vpr_run(vpr_output): + for line in vpr_output.split("\n"): + if "error" in line.lower(): + logger.error("-->>" + line) + if __name__ == "__main__": # Setting up print and logging system logging.basicConfig(level=logging.INFO, stream=sys.stdout, - format='%(levelname)s (%(threadName)-9s) - %(message)s') + format='%(levelname)s - %(message)s') logger = logging.getLogger('OpenFPGA_Flow_Logs') # Parse commandline argument diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 630c0da12..f740f0b5b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -246,7 +246,7 @@ def run_single_script(s, command): universal_newlines=True) output.write(process.stdout) except: - logger.exception() + logger.exception("Failed to launch openfpga flow") logger.info("%s Finished " % name) @@ -280,8 +280,6 @@ def collect_results(job_run_list): result["name"] = run["name"] task_result.append(result) - pprint.pprint(task_result) - with open("task_result.csv", 'w', newline='') as csvfile: writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys()) writer.writeheader() From b66e1203660c74283899e5ba5756bbd104e8c2d1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Aug 2019 15:32:23 -0600 Subject: [PATCH 062/482] patch on local encoders for unused configuration, avoid chip-burn issues --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 9f0369d9a..d3661126b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2937,7 +2937,7 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { num_outputs, my_ito1hot(i, num_outputs)); } fprintf(fp, "\tdefault : data = %d'b%s;\n", - num_outputs, my_ito1hot(num_outputs, num_outputs)); + num_outputs, my_ito1hot(num_outputs - 1, num_outputs)); fprintf(fp, "endcase\n"); fprintf(fp, "assign data_inv = ~data;\n"); From 5ece7ab6d0ae894235db4077d7baab84be91d65a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Aug 2019 15:58:14 -0600 Subject: [PATCH 063/482] start refactoring the bitstream part using spice_models --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 4 +-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 4 +-- .../SRC/fpga_x2p/bitstream/fpga_bitstream.c | 26 +++++++++---------- .../SRC/fpga_x2p/bitstream/fpga_bitstream.h | 8 +++--- 4 files changed, 20 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 5166a27a7..f86fc13e4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -170,8 +170,8 @@ char* my_strcat(const char* str1, } /* Split the path and program name*/ -int split_path_prog_name(char* prog_path, - char split_token, +int split_path_prog_name(const char* prog_path, + const char split_token, char** ret_path, char** ret_prog_name) { int i; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index bf8d0beaa..27803a005 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -17,8 +17,8 @@ int create_dir_path(char* dir_path); char* my_strcat(const char* str1, const char* str2); -int split_path_prog_name(char* prog_path, - char split_token, +int split_path_prog_name(const char* prog_path, + const char split_token, char** ret_path, char** ret_prog_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c index 78ec729e4..6eb9a0af3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c @@ -53,8 +53,8 @@ void dump_conf_bits_to_bitstream_file(FILE* fp, * In this file, the property of configuration bits will be shown as comments, * which is easy for developers to debug */ -void dump_fpga_spice_bitstream(char* bitstream_file_name, - char* circuit_name, +void dump_fpga_spice_bitstream(const char* bitstream_file_name, + const char* circuit_name, t_sram_orgz_info* cur_sram_orgz_info) { FILE* fp; @@ -288,8 +288,8 @@ void dump_conf_bits_to_bitstream_file(FILE* fp, /* Top-level function*/ void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup, t_arch Arch, - char* circuit_name, - char* bitstream_file_path, + const char* circuit_name, + const char* bitstream_file_path, t_sram_orgz_info** cur_sram_orgz_info) { /* Timer */ clock_t t_start; @@ -380,22 +380,20 @@ void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup, * Prepare all the variables required by the core generator */ void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup, - t_arch Arch, - char* circuit_name, - t_sram_orgz_info** cur_sram_orgz_info) { - char* bitstream_file_path = NULL; + t_arch Arch, + char* circuit_name, + t_sram_orgz_info** cur_sram_orgz_info) { + std::string bitstream_file_path; if (NULL == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file) { - bitstream_file_path = my_strcat(circuit_name, fpga_spice_bitstream_output_file_postfix); + bitstream_file_path = circuit_name; + bitstream_file_path.append(fpga_spice_bitstream_output_file_postfix); } else { - bitstream_file_path = my_strdup(vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file); + bitstream_file_path = vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file; } /* Run bitstream generation and dump output file */ - vpr_fpga_generate_bitstream(vpr_setup, Arch, circuit_name, bitstream_file_path, cur_sram_orgz_info); - - /* Free */ - my_free(bitstream_file_path); + vpr_fpga_generate_bitstream(vpr_setup, Arch, circuit_name, bitstream_file_path.c_str(), cur_sram_orgz_info); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h index 39213e9a1..9236b70ee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h @@ -2,14 +2,14 @@ void encode_decoder_addr(int input, int decoder_size, char* addr); -void dump_fpga_spice_bitstream(char* bitstream_file_name, - char* circuit_name, +void dump_fpga_spice_bitstream(const char* bitstream_file_name, + const char* circuit_name, t_sram_orgz_info* cur_sram_orgz_info); void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup, t_arch Arch, - char* circuit_name, - char* bitstream_file_path, + const char* circuit_name, + const char* bitstream_file_path, t_sram_orgz_info** cur_sram_orgz_info); void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup, From e456b6f90597091b2441de3c9ebcd131339539a4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Aug 2019 16:36:49 -0600 Subject: [PATCH 064/482] replace spice_models with circuit model in bitstream generator --- .../fpga_x2p/bitstream/fpga_bitstream_routing.c | 15 ++++++++++----- .../fpga_x2p/bitstream/fpga_bitstream_routing.h | 2 +- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c index 968cf8859..5790c1ba4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c @@ -38,6 +38,7 @@ /* Generate bitstream for a multiplexer of a switch block */ static void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, + const t_arch& arch, const RRGSB& rr_sb, t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, @@ -65,6 +66,7 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, assert((2 == mux_size)||(2 < mux_size)); /* Get verilog model*/ + CircuitModelId circuit_model = switch_inf[switch_index].circuit_model; verilog_model = switch_inf[switch_index].spice_model; /* Configuration bits for this MUX*/ @@ -80,7 +82,8 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, ((DEFAULT_PATH_ID < path_id) &&(path_id < mux_size))); /* Depend on both technology and structure of this MUX*/ - switch (verilog_model->design_tech) { + const CircuitLibrary& circuit_lib = arch.spice->circuit_lib; + switch (circuit_lib.design_tech_type(circuit_model)) { case SPICE_MODEL_DESIGN_CMOS: decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); break; @@ -213,6 +216,7 @@ void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, static void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, + const t_arch& arch, const RRGSB& rr_sb, t_sram_orgz_info* cur_sram_orgz_info, enum e_side chan_side, @@ -245,7 +249,7 @@ void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, /* No bitstream generation required by a special direct connection*/ } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ - fpga_spice_generate_bitstream_switch_box_mux(fp, rr_sb, cur_sram_orgz_info, + fpga_spice_generate_bitstream_switch_box_mux(fp, arch, rr_sb, cur_sram_orgz_info, cur_rr_node, num_drive_rr_nodes, drive_rr_nodes, cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); @@ -344,6 +348,7 @@ void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, */ static void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp, + const t_arch& arch, const RRGSB& rr_sb, t_sram_orgz_info* cur_sram_orgz_info) { /* Check */ @@ -362,7 +367,7 @@ void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp, ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - fpga_spice_generate_bitstream_switch_box_interc(fp, rr_sb, cur_sram_orgz_info, + fpga_spice_generate_bitstream_switch_box_interc(fp, arch, rr_sb, cur_sram_orgz_info, side_manager.get_side(), itrack); } @@ -797,7 +802,7 @@ void fpga_spice_generate_bitstream_routing_connection_box_subckt(FILE* fp, /* Top Function*/ /* Build the routing resource SPICE sub-circuits*/ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log_file_path, - t_arch arch, + const t_arch& arch, t_det_routing_arch* routing_arch, t_sram_orgz_info* cur_sram_orgz_info, boolean compact_routing_hierarchy) { @@ -841,7 +846,7 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy); - fpga_spice_generate_bitstream_routing_switch_box_subckt(fp, + fpga_spice_generate_bitstream_routing_switch_box_subckt(fp, arch, rr_sb, cur_sram_orgz_info); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h index f3b86957f..51df5bdd7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h @@ -1,7 +1,7 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log_file_path, - t_arch arch, + const t_arch& arch, t_det_routing_arch* routing_arch, t_sram_orgz_info* cur_sram_orgz_info, boolean compact_routing_hierarchy); From aa7f3bef7f292424349390fe8543f2d5c28df097 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Aug 2019 18:20:30 -0600 Subject: [PATCH 065/482] fixed bugs in configure pb_rr_graph and dependence on testbenches --- .../vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c | 14 ++++++++++---- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 5 ++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c index db283690c..04a8dc24e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c @@ -231,16 +231,22 @@ void connect_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_ assert(rr_node_type == local_rr_graph->rr_node[cur_rr_node_index].type); switch (rr_node_type) { - case INTRA_CLUSTER_EDGE: + case INTRA_CLUSTER_EDGE: { /* Check out all the output_edges belonging to the same physical mode */ + int cur_edge = 0; for (iedge = 0; iedge < cur_pb_graph_pin->num_output_edges; iedge++) { check_pb_graph_edge(*(cur_pb_graph_pin->output_edges[iedge])); - if (phy_mode_index == cur_pb_graph_pin->output_edges[iedge]->interconnect->parent_mode_index) { - local_rr_graph->rr_node[cur_rr_node_index].edges[iedge] = cur_pb_graph_pin->output_edges[iedge]->output_pins[0]->rr_node_index_physical_pb; - local_rr_graph->rr_node[cur_rr_node_index].switches[iedge] = local_rr_graph->delayless_switch_index; + /* Bypass fan-outs that are not in the physical mode */ + if (phy_mode_index != cur_pb_graph_pin->output_edges[iedge]->interconnect->parent_mode_index) { + continue; } + assert ( cur_edge < local_rr_graph->rr_node[cur_rr_node_index].num_edges); + local_rr_graph->rr_node[cur_rr_node_index].edges[cur_edge] = cur_pb_graph_pin->output_edges[iedge]->output_pins[0]->rr_node_index_physical_pb; + local_rr_graph->rr_node[cur_rr_node_index].switches[cur_edge] = local_rr_graph->delayless_switch_index; + cur_edge++; } break; + } case SOURCE: /* Connect the SOURCE nodes to the rr_node of cur_pb_graph_pin */ assert (0 == local_rr_graph->rr_node[cur_rr_node_index].fan_in); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 5c4d1f132..a0a3e773c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -310,7 +310,10 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, sram_verilog_orgz_info->type); /* Force enable bitstream generator when we need to output Verilog top testbench*/ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench) { + if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) + || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench) + || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) + || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist)) { vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream = TRUE; } From 7bfc48b8e4ef98900fa9586833ba2d881bd33719 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 17 Aug 2019 01:49:49 -0600 Subject: [PATCH 066/482] Moved spice and verilog netlist folder location --- .../SpiceNetlists/adder.sp | 0 .../vpr => openfpga_flow}/SpiceNetlists/ff.sp | 0 .../SpiceNetlists/ff_tb.sp | 0 .../SpiceNetlists/gate.sp | 0 .../vpr => openfpga_flow}/SpiceNetlists/io.sp | 0 .../SpiceNetlists/sram.sp | 0 .../VerilogNetlists/adder.v | 0 .../VerilogNetlists/ff.v | 28 +- .../VerilogNetlists/ff_tb.v | 0 .../VerilogNetlists/io.v | 0 .../VerilogNetlists/lb_tb.v | 0 .../VerilogNetlists/lut6.v | 0 .../VerilogNetlists/mux_tb.v | 0 .../VerilogNetlists/sram.v | 0 .../VerilogNetlists/sram_tb.v | 0 .../k6_N10_sram_chain_HC_DPRAM_template.xml | 1155 +++++++++++++++++ .../k6_N10_sram_chain_HC_template.xml | 1040 +++++++++++++++ .../k8_N10_sram_chain_FC_template.xml | 1139 ++++++++++++++++ run_test.sh | 43 + vpr7_x2p/vpr/go_ganesh.sh | 33 - vpr7_x2p/vpr/regression_verilog.sh | 41 - 21 files changed, 3391 insertions(+), 88 deletions(-) rename {vpr7_x2p/vpr => openfpga_flow}/SpiceNetlists/adder.sp (100%) rename {vpr7_x2p/vpr => openfpga_flow}/SpiceNetlists/ff.sp (100%) rename {vpr7_x2p/vpr => openfpga_flow}/SpiceNetlists/ff_tb.sp (100%) rename {vpr7_x2p/vpr => openfpga_flow}/SpiceNetlists/gate.sp (100%) rename {vpr7_x2p/vpr => openfpga_flow}/SpiceNetlists/io.sp (100%) rename {vpr7_x2p/vpr => openfpga_flow}/SpiceNetlists/sram.sp (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/adder.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/ff.v (87%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/ff_tb.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/io.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/lb_tb.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/lut6.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/mux_tb.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/sram.v (100%) rename {vpr7_x2p/vpr => openfpga_flow}/VerilogNetlists/sram_tb.v (100%) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml create mode 100644 openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml create mode 100644 run_test.sh delete mode 100755 vpr7_x2p/vpr/go_ganesh.sh delete mode 100755 vpr7_x2p/vpr/regression_verilog.sh diff --git a/vpr7_x2p/vpr/SpiceNetlists/adder.sp b/openfpga_flow/SpiceNetlists/adder.sp similarity index 100% rename from vpr7_x2p/vpr/SpiceNetlists/adder.sp rename to openfpga_flow/SpiceNetlists/adder.sp diff --git a/vpr7_x2p/vpr/SpiceNetlists/ff.sp b/openfpga_flow/SpiceNetlists/ff.sp similarity index 100% rename from vpr7_x2p/vpr/SpiceNetlists/ff.sp rename to openfpga_flow/SpiceNetlists/ff.sp diff --git a/vpr7_x2p/vpr/SpiceNetlists/ff_tb.sp b/openfpga_flow/SpiceNetlists/ff_tb.sp similarity index 100% rename from vpr7_x2p/vpr/SpiceNetlists/ff_tb.sp rename to openfpga_flow/SpiceNetlists/ff_tb.sp diff --git a/vpr7_x2p/vpr/SpiceNetlists/gate.sp b/openfpga_flow/SpiceNetlists/gate.sp similarity index 100% rename from vpr7_x2p/vpr/SpiceNetlists/gate.sp rename to openfpga_flow/SpiceNetlists/gate.sp diff --git a/vpr7_x2p/vpr/SpiceNetlists/io.sp b/openfpga_flow/SpiceNetlists/io.sp similarity index 100% rename from vpr7_x2p/vpr/SpiceNetlists/io.sp rename to openfpga_flow/SpiceNetlists/io.sp diff --git a/vpr7_x2p/vpr/SpiceNetlists/sram.sp b/openfpga_flow/SpiceNetlists/sram.sp similarity index 100% rename from vpr7_x2p/vpr/SpiceNetlists/sram.sp rename to openfpga_flow/SpiceNetlists/sram.sp diff --git a/vpr7_x2p/vpr/VerilogNetlists/adder.v b/openfpga_flow/VerilogNetlists/adder.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/adder.v rename to openfpga_flow/VerilogNetlists/adder.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v similarity index 87% rename from vpr7_x2p/vpr/VerilogNetlists/ff.v rename to openfpga_flow/VerilogNetlists/ff.v index cf15dc440..cc6598c46 100644 --- a/vpr7_x2p/vpr/VerilogNetlists/ff.v +++ b/openfpga_flow/VerilogNetlists/ff.v @@ -5,15 +5,15 @@ // Coder : Xifan TANG //----------------------------------------------------- //------ Include defines: preproc flags ----- -`include "GENERATED_DIR_KEYWORD/SRC/fpga_defines.v" +`include "./SRC/fpga_defines.v" module static_dff ( /* Global ports go first */ input set, // set input -input reset, // Reset input +input reset, // Reset input input clk, // Clock Input /* Local ports follow */ input D, // Data Input -output Q // Q output +output Q // Q output ); //------------Internal Variables-------- reg q_reg; @@ -29,7 +29,7 @@ end else begin end // Wire q_reg to Q -assign Q = q_reg; +assign Q = q_reg; endmodule //End Of Module static_dff @@ -42,12 +42,12 @@ endmodule //End Of Module static_dff module sc_dff ( /* Global ports go first */ input set, // set input -input reset, // Reset input +input reset, // Reset input input clk, // Clock Input /* Local ports follow */ input D, // Data Input -output Q, // Q output -output Qb // Q output +output Q, // Q output +output Qb // Q output ); //------------Internal Variables-------- reg q_reg; @@ -63,7 +63,7 @@ end else begin end // Wire q_reg to Q -assign Q = q_reg; +assign Q = q_reg; assign Qb = ~Q; endmodule //End Of Module static_dff @@ -76,13 +76,13 @@ endmodule //End Of Module static_dff //----------------------------------------------------- module sc_dff_compact ( /* Global ports go first */ -input reset, // Reset input +input reset, // Reset input //input set, // set input input clk, // Clock Input /* Local ports follow */ input D, // Data Input -output Q, // Q output -output Qb // Q output +output Q, // Q output +output Qb // Q output ); //------------Internal Variables-------- reg q_reg; @@ -98,16 +98,16 @@ end else begin end /* // Wire q_reg to Q -assign Q = q_reg; +assign Q = q_reg; assign Qb = ~Q; */ `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q -assign Q = q_reg; +assign Q = q_reg; assign Qb = ~q_reg; `else -assign Q = 1'bZ; +assign Q = 1'bZ; assign Qb = !Q; `endif diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff_tb.v b/openfpga_flow/VerilogNetlists/ff_tb.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/ff_tb.v rename to openfpga_flow/VerilogNetlists/ff_tb.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/io.v b/openfpga_flow/VerilogNetlists/io.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/io.v rename to openfpga_flow/VerilogNetlists/io.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/lb_tb.v b/openfpga_flow/VerilogNetlists/lb_tb.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/lb_tb.v rename to openfpga_flow/VerilogNetlists/lb_tb.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/lut6.v b/openfpga_flow/VerilogNetlists/lut6.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/lut6.v rename to openfpga_flow/VerilogNetlists/lut6.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/mux_tb.v b/openfpga_flow/VerilogNetlists/mux_tb.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/mux_tb.v rename to openfpga_flow/VerilogNetlists/mux_tb.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/sram.v rename to openfpga_flow/VerilogNetlists/sram.v diff --git a/vpr7_x2p/vpr/VerilogNetlists/sram_tb.v b/openfpga_flow/VerilogNetlists/sram_tb.v similarity index 100% rename from vpr7_x2p/vpr/VerilogNetlists/sram_tb.v rename to openfpga_flow/VerilogNetlists/sram_tb.v diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml new file mode 100644 index 000000000..c03b83855 --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -0,0 +1,1155 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml new file mode 100644 index 000000000..84d2c3ab3 --- /dev/null +++ b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml @@ -0,0 +1,1139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + 10e-12 0e-12 0e-12 + + + 10e-12 0e-12 0e-12 + + + + + + + + + + + 10e-12 + + + 10e-12 + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+./openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml \ +./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ +--top_module s298 \ +--power \ +--power_tech ./openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml \ +--min_route_chan_width 1.3 \ +--vpr_fpga_verilog \ +--vpr_fpga_verilog_dir ./SRC \ +--vpr_fpga_x2p_rename_illegal_port \ +--vpr_fpga_verilog_print_autocheck_top_testbench + + +# \ +# --end_flow_with_test \ +# --vpr_fpga_verilog_print_autocheck_top_testbench \ +# --vpr_fpga_verilog_include_icarus_simulator \ +# --vpr_fpga_verilog_formal_verification_top_netlist + + +# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/vpr', +# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/tmp/arch/k6_N10_rram_memory_bank_SC_winbond90.xml', 's298_ace_corrected_out.blif' +# '--net_file' +# 's298_vpr.net' +# '--place_file' +# 's298_vpr.place' +# '--route_file' +# 's298_vpr.route' +# '--full_stats' +# '--nodisp' +# '--power' +# '--activity_file' +# 's298_ace_out.act' +# '--tech_properties' +# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml' +# '--fpga_verilog' +# '--fpga_verilog_dir' +# './SRC' +# '--fpga_verilog_print_autocheck_top_testbench' +# 's298_output_verilog.v' +# '--fpga_verilog_print_formal_verification_top_netlist' +# '--fpga_verilog_include_icarus_simulator' +# '--fpga_x2p_rename_illegal_port' \ No newline at end of file diff --git a/vpr7_x2p/vpr/go_ganesh.sh b/vpr7_x2p/vpr/go_ganesh.sh deleted file mode 100755 index 7caaa4f09..000000000 --- a/vpr7_x2p/vpr/go_ganesh.sh +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash -echo "#################################################" -echo "The current shell environment is the following:" -echo $0 -echo "#################################################" - -# Example of how to run vprset circuit_name = pip_add -#set circuit_name = pip_add -circuit_name=sync_4bits_add -circuit_blif=${PWD}/Circuits/${circuit_name}.blif -arch_file=${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml -arch_file_template=${PWD}/ARCH/k6_N10_sram_chain_HC_template.xml -circuit_act=${PWD}/Circuits/${circuit_name}.act -circuit_verilog=${PWD}/Circuits/${circuit_name}.v -spice_output=${PWD}/spice_demo -verilog_output=${PWD}/verilog_demo -modelsim_ini=/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini -openfpga_path=${PWD}/../.. - -# Make sure a clean start -rm -rf ${spice_output} -rm -rf ${verilog_output} - -echo "*******************************" -echo "THIS SCRIPT NEEDS TO BE SOURCED" -echo "source ./go.sh" -echo "*******************************" - -sed "s:OPENFPGAPATH:${openfpga_path}:g" ${arch_file_template} > ${arch_file} - -# Pack, place, and route a heterogeneous FPGA -# Packing uses the AAPack algorithm -./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh deleted file mode 100755 index 47608013f..000000000 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/bash -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -benchmark="test_modes" -OpenFPGA_path="OPENFPGAPATHKEYWORD" -verilog_output_dirname="${benchmark}_Verilog" -verilog_output_dirpath="$PWD" -tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" -# VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml" -blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" -act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " -verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" -vpr_route_chan_width="300" -fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" -ff_path="$vpr_path/VerilogNetlists/ff.v" -new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" -ff_keyword="GENERATED_DIR_KEYWORD" -ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" -arch_ff_keyword="FFPATHKEYWORD" - -# Remove previous designs -rm -rf $verilog_output_dirpath/$verilog_output_dirname - -mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file -perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path -cd - - -# Run VPR -echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path -cd - From 66bb8a5e4bb63ae0d5669278a40e7f9f1600c67a Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 17 Aug 2019 02:20:04 -0600 Subject: [PATCH 067/482] Updated RRAM architecture file --- .../k6_N10_rram_memory_bank_SC_winbond90.xml | 216 +++++++++--------- 1 file changed, 108 insertions(+), 108 deletions(-) diff --git a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml index d32efd8de..c0d607084 100644 --- a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +++ b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml @@ -61,60 +61,60 @@ - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + @@ -122,8 +122,8 @@ - - + + @@ -131,8 +131,8 @@ - - + + @@ -140,126 +140,126 @@ - - + + - - + + - + - - - + + + - - + + - + - - + + - + - - - + + + - - + + - - - - - - + + + + + + - - - + + + - - - + + + - - + + - - - + + + - - - - + + + + - - - + + + - + - + - - - + + + - - + + - - - + + + - + - - + + - - + + - - + + @@ -270,7 +270,7 @@ - + @@ -287,28 +287,28 @@ 2.5x when looking up in Jeff's tables. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. This also leads to the switch being 46% of the total wire delay, which is reasonable. --> - + - + - + - + 1 1 1 1 1 1 1 1 1 - + 1 1 1 1 1 - + 1 1 1 @@ -326,7 +326,7 @@ - + @@ -410,7 +410,7 @@ @@ -425,7 +425,7 @@ - + @@ -439,7 +439,7 @@ - + @@ -454,7 +454,7 @@ - + @@ -478,7 +478,7 @@ Since all our outputs LUT outputs go to a BLE output, and have a delay of 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback to get the part that should be marked on the crossbar. --> - + From 12c998c12a51cf519d29738dbb5f27142c3d372f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 17 Aug 2019 16:22:52 -0600 Subject: [PATCH 068/482] Added dockerignore + minor changes in openfpga_flow script --- .dockerignore | 2 ++ Dockerfile | 4 ++-- openfpga_flow/scripts/run_fpga_flow.py | 14 +++++++++----- run_local.sh | 3 +++ 4 files changed, 16 insertions(+), 7 deletions(-) create mode 100644 .dockerignore create mode 100644 run_local.sh diff --git a/.dockerignore b/.dockerignore new file mode 100644 index 000000000..2e0e43deb --- /dev/null +++ b/.dockerignore @@ -0,0 +1,2 @@ +# Ignore everything +* \ No newline at end of file diff --git a/Dockerfile b/Dockerfile index 054914852..bf0ea6d24 100755 --- a/Dockerfile +++ b/Dockerfile @@ -7,9 +7,9 @@ RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl RUN mkdir -p /release /dev -RUN cd release && git clone --single-branch --branch documentation https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA +RUN cd release && git clone --single-branch --branch master https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA -RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -CMAKE_BUILD_TYPE=debug && make +RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -DCMAKE_BUILD_TYPE=debug -DCMAKE_NO_GRAPHICS=on && make -j RUN rm -rf /var/lib/apt/lists/* diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index efdf01345..d242daa03 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -507,7 +507,7 @@ def run_vpr(): logger.info("Routing with channel width=%d successful" % min_channel_width) break - elif args.min_channel_width > (min_channel_width-2): + elif args.max_route_width_retry < (min_channel_width-2): clean_up_and_exit("Failed to route within maximum " + "iteration of channel width") else: @@ -663,8 +663,9 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile): if process.returncode: logger.info("Standard VPR run failed with returncode %d", process.returncode) - except: + except Exception as e: logger.exception("Failed to run VPR") + process_failed_vpr_run(e.output) clean_up_and_exit("") logger.info("VPR output is written in file %s" % logfile) return int(chan_width) @@ -816,7 +817,8 @@ def run_netlists_verification(): command = [cad_tools["iverilog_path"]] command += ["-o", compiled_file] - command += [cad_tools["include_netlist_verification"]] + command += ["./SRC/%s_ace_corrected_out_include_netlists.v" % + args.top_module] command += ["-s"] if args.vpr_fpga_verilog_formal_verification_top_netlist: command += [tb_top_formal] @@ -841,8 +843,9 @@ def run_command(taskname, logfile, command, exit_if_fail=True): if process.returncode: logger.error("%s run failed with returncode %d" % (taskname, process.returncode)) - except: - logger.exception() + except Exception as e: + logger.exception("failed to execute %s" % taskname) + process_failed_vpr_run(e.output) if exit_if_fail: clean_up_and_exit("Failed to run %s task" % taskname) logger.info("%s is written in file %s" % (taskname, logfile)) @@ -860,6 +863,7 @@ def process_failed_vpr_run(vpr_output): if "error" in line.lower(): logger.error("-->>" + line) + if __name__ == "__main__": # Setting up print and logging system logging.basicConfig(level=logging.INFO, stream=sys.stdout, diff --git a/run_local.sh b/run_local.sh new file mode 100644 index 000000000..b560b1611 --- /dev/null +++ b/run_local.sh @@ -0,0 +1,3 @@ +#!/bin/bash +docker run -it --rm -v "${PWD}":/root/dev/OpenFPGA -w="/root/dev/OpenFPGA" goreganesh/open_fpga bash +pause From fb29fcfc06888e4f2858b84f387d568bfdb7675c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 17 Aug 2019 22:59:54 -0600 Subject: [PATCH 069/482] Added build files in .gitignore --- .gitignore | 7 ++++++- run_local.sh | 0 2 files changed, 6 insertions(+), 1 deletion(-) mode change 100644 => 100755 run_local.sh diff --git a/.gitignore b/.gitignore index 7e355cf96..cc77d456e 100644 --- a/.gitignore +++ b/.gitignore @@ -32,9 +32,14 @@ vpr7_x2p/vpr/vpr vpr7_x2p/printhandler/printhandlerdemo vpr7_x2p/libarchfpga/read_arch vpr7_x2p/pcre/pcredemo +ace2/ace +vpr7_x2p/libpcre/pcredemo +vpr7_x2p/libprinthandler/printhandlerdemo +vpr7_x2p/vpr/vpr_shell # Some local temporary files .vscode *_local.bat fpga_flow/csv_rpts -tmp/ \ No newline at end of file +tmp/ +build/ \ No newline at end of file diff --git a/run_local.sh b/run_local.sh old mode 100644 new mode 100755 From 7f6c1b3e00b794806ff377dcb80f7e3df89c35d0 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 18 Aug 2019 12:26:05 -0600 Subject: [PATCH 070/482] Code re-arrangement + Added support for subdirectory task in openfpga_task + Rearranged function order + Combined vpr re-route and standrad run function + Removed external_call function from fpga_flow script + Added .gitignore to task directory --- .gitignore | 4 +- openfpga_flow/scripts/run_fpga_flow.py | 110 ++++--------------------- openfpga_flow/scripts/run_fpga_task.py | 42 ++++++---- 3 files changed, 45 insertions(+), 111 deletions(-) diff --git a/.gitignore b/.gitignore index cc77d456e..fc6dbf3a5 100644 --- a/.gitignore +++ b/.gitignore @@ -42,4 +42,6 @@ vpr7_x2p/vpr/vpr_shell *_local.bat fpga_flow/csv_rpts tmp/ -build/ \ No newline at end of file +build/ + +message.txt \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index d242daa03..ad18e66ad 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -337,7 +337,7 @@ def clean_up_and_exit(msg, clean=False): logger.error("Current working directory : " + os.getcwd()) logger.error(msg) logger.error("Exiting . . . . . .") - exit() + exit(1) def run_yosys_with_abc(): @@ -499,9 +499,10 @@ def run_vpr(): " (Slack of %d%%)" % ((args.min_route_chan_width-1)*100)) while(1): - res = run_vpr_route(args.top_module+"_ace_corrected_out.blif", - min_channel_width, - args.top_module+"_min_channel_reroute_vpr.txt") + res = run_standard_vpr(args.top_module+"_ace_corrected_out.blif", + int(min_channel_width), + args.top_module+"_reroute_vpr.txt", + route_only=True) if res: logger.info("Routing with channel width=%d successful" % @@ -532,15 +533,17 @@ def run_vpr(): extract_vpr_power_esti(args.top_module+"_ace_corrected_out.power") -def run_standard_vpr(bench_blif, fixed_chan_width, logfile): +def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command = [cad_tools["vpr_path"], args.arch_file, bench_blif, "--net_file", args.top_module+"_vpr.net", "--place_file", args.top_module+"_vpr.place", "--route_file", args.top_module+"_vpr.route", - "--full_stats", "--nodisp" + "--full_stats", "--nodisp", ] + if route_only: + command += ["--route"] # Power options if args.power: command += ["--power", @@ -551,7 +554,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile): command += ["--timing_driven_clustering", "off"] # channel width option if fixed_chan_width >= 0: - command += ["-route_chan_width", fixed_chan_width] + command += ["--route_chan_width", "%d"%fixed_chan_width] if args.vpr_use_tileable_route_chan_width: command += ["--use_tileable_route_chan_width"] @@ -654,90 +657,16 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile): universal_newlines=True) for line in process.stdout.split('\n'): if "Best routing" in line: - chan_width = re.search( - r"channel width factor of ([0-9]+)", line).group(1) + chan_width = int(re.search( + r"channel width factor of ([0-9]+)", line).group(1)) if "Circuit successfully routed" in line: - chan_width = re.search( - r"a channel width factor of ([0-9]+)", line).group(1) + chan_width = int(re.search( + r"a channel width factor of ([0-9]+)", line).group(1)) output.write(process.stdout) if process.returncode: logger.info("Standard VPR run failed with returncode %d", process.returncode) - except Exception as e: - logger.exception("Failed to run VPR") - process_failed_vpr_run(e.output) - clean_up_and_exit("") - logger.info("VPR output is written in file %s" % logfile) - return int(chan_width) - - -def run_vpr_route(bench_blif, fixed_chan_width, logfile): - command = [cad_tools["vpr_path"], - args.arch_file, - bench_blif, - "--net_file", args.top_module+"_vpr.net", - "--place_file", args.top_module+"_vpr.place", - "--route_file", args.top_module+"_vpr.route", - "--full_stats", "--nodisp", - "--route" - ] - if args.power: - command += [ - "--power", - "--activity_file", args.top_module+"_ace_out.act", - "--tech_properties", args.power_tech] - if fixed_chan_width >= 0: - command += ["-route_chan_width", "%d" % fixed_chan_width] - - # VPR - SPICE options - if args.power and args.vpr_fpga_spice: - command += "--fpga_spice" - if args.vpr_fpga_spice_print_cbsbtb: - command += ["--print_spice_cb_mux_testbench", - "--print_spice_sb_mux_testbench"] - if args.vpr_fpga_spice_print_pbtb: - command += ["--print_spice_pb_mux_testbench", - "--print_spice_lut_testbench", - "--print_spice_hardlogic_testbench"] - if args.vpr_fpga_spice_print_gridtb: - command += ["--print_spice_grid_testbench"] - if args.vpr_fpga_spice_print_toptb: - command += ["--print_spice_top_testbench"] - if args.vpr_fpga_spice_leakage_only: - command += ["--fpga_spice_leakage_only"] - if args.vpr_fpga_spice_parasitic_net_estimation_off: - command += ["--fpga_spice_parasitic_net_estimation_off"] - - if args.vpr_fpga_verilog: - command += ["--fpga_verilog"] - if args.vpr_fpga_x2p_rename_illegal_port: - command += ["--fpga_x2p_rename_illegal_port"] - - if args.vpr_max_router_iteration: - command += ["--max_router_iterations", args.vpr_max_router_iteration] - if args.vpr_route_breadthfirst: - command += ["--router_algorithm", "breadth_first"] - chan_width = None - try: - with open(logfile, 'w+') as output: - output.write(" ".join(command)+"\n") - process = subprocess.run(command, - check=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - universal_newlines=True) - for line in process.stdout.split('\n'): - if "Best routing" in line: - chan_width = re.search( - r"channel width factor of ([0-9]+)", line).group(1) - if "Circuit successfully routed" in line: - chan_width = re.search( - r"a channel width factor of ([0-9]+)", line).group(1) - output.write(process.stdout) - if process.returncode: - logger.info("Standard VPR run failed with returncode %d", - process.returncode) - except Exception as e: + except (Exception, subprocess.CalledProcessError) as e: logger.exception("Failed to run VPR") process_failed_vpr_run(e.output) clean_up_and_exit("") @@ -843,7 +772,7 @@ def run_command(taskname, logfile, command, exit_if_fail=True): if process.returncode: logger.error("%s run failed with returncode %d" % (taskname, process.returncode)) - except Exception as e: + except (Exception, subprocess.CalledProcessError) as e: logger.exception("failed to execute %s" % taskname) process_failed_vpr_run(e.output) if exit_if_fail: @@ -851,13 +780,6 @@ def run_command(taskname, logfile, command, exit_if_fail=True): logger.info("%s is written in file %s" % (taskname, logfile)) -def external_call(parent_logger=None, passed_args=[]): - global logger, args - logger = parent_logger - args = parser.parse_args(passed_args) - main() - - def process_failed_vpr_run(vpr_output): for line in vpr_output.split("\n"): if "error" in line.lower(): diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index f740f0b5b..0612700d4 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -17,7 +17,7 @@ import pprint # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -logging.basicConfig(level=logging.DEBUG, stream=sys.stdout, +logging.basicConfig(level=logging.INFO, stream=sys.stdout, format='%(levelname)s (%(threadName)-9s) - %(message)s') logger = logging.getLogger('OpenFPGA_Task_logs') @@ -50,11 +50,12 @@ gc = config["GENERAL CONFIGURATION"] def main(): - validate_command_line_arguments() for eachtask in args.tasks: logger.info("Currently running task %s" % eachtask) + eachtask = eachtask.replace("\\", "/").split("/") job_run_list = generate_each_task_actions(eachtask) + eachtask = "_".join(eachtask) if not args.test_run: run_actions(job_run_list) collect_results(job_run_list) @@ -84,7 +85,7 @@ def generate_each_task_actions(taskname): """ # Check if task directory exists and consistent - curr_task_dir = os.path.join(gc["task_dir"], taskname) + curr_task_dir = os.path.join(gc["task_dir"], *(taskname)) if not os.path.isdir(curr_task_dir): clean_up_and_exit("Task directory [%s] not found" % curr_task_dir) os.chdir(curr_task_dir) @@ -148,7 +149,7 @@ def generate_each_task_actions(taskname): "top_module": task_conf.get("SYNTHESIS_PARAM", bech_name+"_top", fallback="top"), "ys_script": task_conf.get("SYNTHESIS_PARAM", bech_name+"_yosys", - fallback=ys_for_task) + fallback=ys_for_task), }) # Create OpenFPGA flow run commnad for each combination of @@ -165,7 +166,8 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%s_arch%d" % (bench["top_module"], indx), "run_dir": flow_run_dir, - "commands": cmd}) + "commands": cmd, + "status": False}) return flow_run_cmd_list @@ -230,23 +232,28 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): return command -def run_single_script(s, command): +def run_single_script(s, eachJob): logger.debug('Added job in pool') with s: - logger.debug("Running OpenFPGA flow with " + " ".join(command)) + logger.debug("Running OpenFPGA flow with " + + " ".join(eachJob["commands"])) name = threading.currentThread().getName() - # run_fpga_flow.external_call(logger, command) try: logfile = "%s_out.log" % name with open(logfile, 'w+') as output: - process = subprocess.run(["python3.5", gc["script_default"]]+command, + process = subprocess.run(["python3.5", + gc["script_default"]] + + eachJob["commands"], check=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=True) output.write(process.stdout) + eachJob["status"] = True except: - logger.exception("Failed to launch openfpga flow") + logger.error("Failed to execute openfpga flow - " + + eachJob["name"]) + # logger.exception("Failed to launch openfpga flow") logger.info("%s Finished " % name) @@ -256,7 +263,7 @@ def run_actions(job_run_list): for index, eachjob in enumerate(job_run_list): t = threading.Thread(target=run_single_script, name='Job_%02d' % (index+1), - args=(thread_sema, eachjob["commands"])) + args=(thread_sema, eachjob)) t.start() thred_list.append(t) @@ -267,6 +274,8 @@ def run_actions(job_run_list): def collect_results(job_run_list): task_result = [] for run in job_run_list: + if not run["status"]: + continue # Check if any result file exist if not glob.glob(os.path.join(run["run_dir"], "*.result")): logger.info("No result files found for %s" % run["name"]) @@ -280,11 +289,12 @@ def collect_results(job_run_list): result["name"] = run["name"] task_result.append(result) - with open("task_result.csv", 'w', newline='') as csvfile: - writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys()) - writer.writeheader() - for eachResult in task_result: - writer.writerow(eachResult) + if len(task_result): + with open("task_result.csv", 'w', newline='') as csvfile: + writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys()) + writer.writeheader() + for eachResult in task_result: + writer.writerow(eachResult) if __name__ == "__main__": From 6dc05b769be3197f5fc8baaeb44623d81529be1d Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 18:55:23 -0600 Subject: [PATCH 071/482] Added Power Model Files --- openfpga_flow/tech/PTM_130nm/130nm.pm | 145 + openfpga_flow/tech/PTM_130nm/130nm.xml | 7493 +++++++++++++++++++++++ openfpga_flow/tech/PTM_130nm/readme.txt | 17 + openfpga_flow/tech/PTM_22nm/22nm.pm | 140 + openfpga_flow/tech/PTM_22nm/22nm.xml | 7493 +++++++++++++++++++++++ openfpga_flow/tech/PTM_22nm/readme.txt | 2 + openfpga_flow/tech/PTM_45nm/45nm.pm | 141 + openfpga_flow/tech/PTM_45nm/45nm.xml | 7493 +++++++++++++++++++++++ openfpga_flow/tech/PTM_45nm/readme.txt | 17 + 9 files changed, 22941 insertions(+) create mode 100644 openfpga_flow/tech/PTM_130nm/130nm.pm create mode 100644 openfpga_flow/tech/PTM_130nm/130nm.xml create mode 100644 openfpga_flow/tech/PTM_130nm/readme.txt create mode 100644 openfpga_flow/tech/PTM_22nm/22nm.pm create mode 100644 openfpga_flow/tech/PTM_22nm/22nm.xml create mode 100644 openfpga_flow/tech/PTM_22nm/readme.txt create mode 100644 openfpga_flow/tech/PTM_45nm/45nm.pm create mode 100644 openfpga_flow/tech/PTM_45nm/45nm.xml create mode 100644 openfpga_flow/tech/PTM_45nm/readme.txt diff --git a/openfpga_flow/tech/PTM_130nm/130nm.pm b/openfpga_flow/tech/PTM_130nm/130nm.pm new file mode 100644 index 000000000..bcb5d7a86 --- /dev/null +++ b/openfpga_flow/tech/PTM_130nm/130nm.pm @@ -0,0 +1,145 @@ +* Beta Version released on 2/22/06 + +* PTM 130nm NMOS + +.model nmos nmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 2.25e-9 toxp = 1.6e-9 toxm = 2.25e-9 ++dtox = 0.65e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 2.25e-9 ++xl = -60e-9 ++vth0 = 0.3782 k1 = 0.4 k2 = 0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.2e-010 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 3.92e-008 ++ngate = 2e+020 ndep = 1.54e+018 nsd = 2e+020 phin = 0 ++cdsc = 0.0002 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.13 nfactor = 1.5 eta0 = 0.0092 etab = 0 ++vfb = -0.55 u0 = 0.05928 ua = 6e-010 ub = 1.2e-018 ++uc = 0 vsat = 100370 a0 = 1 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.06 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rdsw = 200 rsw = 100 rdw = 100 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 ++cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + +* PTM 130nm PMOS + +.model pmos pmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 2.35e-009 toxp = 1.6e-009 toxm = 2.35e-009 ++dtox = 0.75e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 2.35e-009 ++xl = -60e-9 ++vth0 = -0.321 k1 = 0.4 k2 = -0.01 k3 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tech/PTM_130nm/readme.txt b/openfpga_flow/tech/PTM_130nm/readme.txt new file mode 100644 index 000000000..92a81a99a --- /dev/null +++ b/openfpga_flow/tech/PTM_130nm/readme.txt @@ -0,0 +1,17 @@ +This technology file was generated using the Nano-CMOS tool from http://ptm.asu.edu/ + +The following default parameters were used: + +NMOS +Leff=49 nm 10% +Vth=0.18 V 30mV +Vdd=1.3 V +Tox=1.6 nm +Rdsw=200 Ohm + +PMOS +Leff=49 nm 10% +Vth=-0.18 V 30mV +Vdd=1.3 V +Tox=1.6 nm +Rdsw=240 Ohm \ No newline at end of file diff --git a/openfpga_flow/tech/PTM_22nm/22nm.pm b/openfpga_flow/tech/PTM_22nm/22nm.pm new file mode 100644 index 000000000..6e4cd7b81 --- /dev/null +++ b/openfpga_flow/tech/PTM_22nm/22nm.pm @@ -0,0 +1,140 @@ +* PTM High Performance 22nm Metal Gate / High-K / Strained-Si +* nominal Vdd = 0.8V + +.model nmos nmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 1.05e-009 toxp = 8e-010 toxm = 1.05e-009 ++dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 2e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 1.05e-009 ++xl = -9e-9 + ++vth0 = 0.50308 k1 = 0.4 k2 = 0 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 7.2e-009 ++ngate = 1e+023 ndep = 5.5e+018 nsd = 2e+020 phin = 0 ++cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.13 nfactor = 2.3 eta0 = 0.004 etab = 0 ++vfb = -0.55 u0 = 0.04 ua = 6e-010 ub = 1.2e-018 ++uc = 0 vsat = 250000 a0 = 1 ags = 0 ++a1 = 0 a2 = 1 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000 ++rsh = 5 rdsw = 145 rsw = 75 rdw = 75 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 ++cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 ++xrcrg1 = 12 xrcrg2 = 5 + ++cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 ++cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 ++dwj = 0 xgw = 0 xgl = 0 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + +.model pmos pmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 1.1e-009 toxp = 8e-010 toxm = 1.1e-009 ++dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 2e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 1.1e-009 ++xl = -9e-9 + ++vth0 = -0.4606 k1 = 0.4 k2 = -0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 ++dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 7.2e-009 ++ngate = 1e+023 ndep = 4.4e+018 nsd = 2e+020 phin = 0 ++cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.126 nfactor = 2.1 eta0 = 0.0038 etab = 0 ++vfb = 0.55 u0 = 0.0095 ua = 2e-009 ub = 5e-019 ++uc = 0 vsat = 210000 a0 = 1 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = 0 b1 = 0 ++keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 ++rsh = 5 rdsw = 145 rsw = 72.5 rdw = 72.5 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 ++cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 ++xrcrg1 = 12 xrcrg2 = 5 + ++cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 ++cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 ++dwj = 0 xgw = 0 xgl = 0 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 diff --git a/openfpga_flow/tech/PTM_22nm/22nm.xml b/openfpga_flow/tech/PTM_22nm/22nm.xml new file mode 100644 index 000000000..11adf783a --- /dev/null +++ b/openfpga_flow/tech/PTM_22nm/22nm.xml @@ -0,0 +1,7493 @@ + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tech/PTM_45nm/readme.txt b/openfpga_flow/tech/PTM_45nm/readme.txt new file mode 100644 index 000000000..52af5b0e4 --- /dev/null +++ b/openfpga_flow/tech/PTM_45nm/readme.txt @@ -0,0 +1,17 @@ +This technology file was generated using the Nano-CMOS tool from http://ptm.asu.edu/ + +The following default parameters were used: + +NMOS +Leff=17.5 nm 10% +Vth=0.18 V 30mV +Vdd=1 V +Tox=1.1 nm +Rdsw=155 Ohm + +PMOS +Leff=17.5 nm 10% +Vth=-0.18 V 30mV +Vdd=1 V +Tox=1.1 nm +Rdsw=155 Ohm \ No newline at end of file From cb5b16c9498317dc9ffd57015399819a7e0de6f5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 18:57:42 -0600 Subject: [PATCH 072/482] Moved required files to openfpga folder --- .../misc/fpgaflow_default_tool_path.conf | 2 +- openfpga_flow/scripts/pro_blif.pl | 447 ++++++++++++++++++ 2 files changed, 448 insertions(+), 1 deletion(-) create mode 100755 openfpga_flow/scripts/pro_blif.pl diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index dbcd72b2b..ce3e0a5c6 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -8,7 +8,7 @@ abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace -pro_blif_path = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/pro_blif.pl +pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl iverilog_path = iverilog include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists diff --git a/openfpga_flow/scripts/pro_blif.pl b/openfpga_flow/scripts/pro_blif.pl new file mode 100755 index 000000000..40203e136 --- /dev/null +++ b/openfpga_flow/scripts/pro_blif.pl @@ -0,0 +1,447 @@ +#!usr/bin/perl -w +use strict; +#use Shell; +use FileHandle; +#Use the time +use Time::gmtime; + +#Get Date +my $mydate = gmctime(); +my ($char_per_line) = (80); + +my ($fname,$frpt,$finitial); +my $add_default_clk = "off"; +my $latch_token; +my ($remove_buffers) = (0); +my ($default_clk_name) = ("clk"); +my @buffers_to_remove; +my @buffers_to_rename; + +sub print_usage() +{ + print "Usage:\n"; + print " perl [-options]\n"; + print " Options:(Mandatory!)\n"; + print " -i \n"; + print " -o \n"; + print " Options: (Optional)\n"; + print " -remove_buffers\n"; + print " -add_default_clk\n"; + print " -initial_blif \n"; + print "\n"; + return 0; +} + +sub opts_read() +{ + if (-1 == $#ARGV) { + print "Error: No input argument!\n"; + &print_usage(); + exit(1); + } else { + for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) { + if ("-i" eq $ARGV[$iargv]) { + $fname = $ARGV[$iargv+1]; + } elsif ("-o" eq $ARGV[$iargv]) { + $frpt = $ARGV[$iargv+1]; + } elsif ("-add_default_clk" eq $ARGV[$iargv]) { + $add_default_clk = "on"; + } elsif ("-initial_blif" eq $ARGV[$iargv]) { + $finitial = $ARGV[$iargv+1]; + } elsif ("-remove_buffers" eq $ARGV[$iargv]) { + $remove_buffers = 1; + } + } + } + return 0; +} + +# Print a line of blif netlist +sub fprint_blifln($ $ $) { + my ($FH, $tokens_ref, $char_per_line) = @_; + my ($cur_line_len) = (0); + my @tokens = @$tokens_ref; + + if ($char_per_line < 1) { + die "ERROR: (fprint_blifln) minimum acceptable number of chars in a line is 1!\n"; + } + # if the length of current line exceed the char_per_line, + # A continue line '\' is added and start a new line + for (my $itok = 0; $itok < ($#tokens+1); $itok++) { + if (!($tokens[$itok])) { + next; + } + # Contain any buffer names to be removed won't show up + if (1 == $remove_buffers) { + for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) { + if ($tokens[$itok] eq $buffers_to_remove[$ibuf]) { + $tokens[$itok] = $buffers_to_rename[$ibuf]; + } + } + } + $cur_line_len += length($tokens[$itok]); + if ($cur_line_len > $char_per_line) { + print $FH "\\"."\n"; + $cur_line_len = 0; + } + print $FH "$tokens[$itok] "; + $cur_line_len += length($tokens[$itok]); + } + print $FH "\n"; + +} + +sub read_blifline($ $) { + my ($FIN, $line_no_ptr) = @_; + my ($lines,$line) = ("",""); + + # Get one line + if (defined($line = <$FIN>)) { + chomp $line; + $lines = $line; + # Replace the < and > with [ and ], VPR does not support... + $lines =~ s//]/g; + while($lines =~ m/\\$/) { + $lines =~ s/\\$//; + if (defined($line = <$FIN>)) { + chomp $line; + $lines = $lines.$line; + $line =~ s//]/g; + } else { + return $lines; + } + } + return $lines; + } else { + return $lines; + } + +} + +sub process_blifmodel($ $) { + my ($FIN,$line_no_ptr) = @_; + my ($blackbox) = (0); + my ($lines); + my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded) = (0,0,0,0); + my @model_input_tokens; + my ($input_lines); + + while(!eof($FIN)) { + # Get one line + $lines = &read_blifline($FIN,$line_no_ptr); + # Check the tokens + if (!defined($lines)) { + next; + } + my @tokens = split('\s+',$lines); + # .end -> return + if (!defined($tokens[0])) { + next; + } + if (".end" eq $tokens[0]) { + return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk); + } elsif (".inputs" eq $tokens[0]) { + foreach my $temp(@tokens) { + if ($temp eq $default_clk_name) { + $have_default_clk = 1; + $clk_num++; + print "Found 1 clock: $temp in @tokens\n"; + last; + } + } + @model_input_tokens = @tokens; + } elsif (".blackbox" eq $tokens[0]) { + $blackbox = 1; + } elsif (".latch" eq $tokens[0]) { + # illegal definition exit + if ((3 != $#tokens)&&(5 != $#tokens)) { + die "ERROR: [LINE: $$line_no_ptr]illegal definition of latch!\n"; + } elsif (3 == $#tokens) { + # We need a default clock + if ($need_default_clk == 0) { + $need_default_clk = 1; + $clk_num++; + } + } elsif (5 == $#tokens) { + $clk_recorded = 0; + # Check if we have this clk names already + foreach my $tmp(@model_input_tokens) { + if ($tmp eq $tokens[4]) { + $clk_recorded = 1; + last; + } + } + # if have been recorded, we push it into the array + if (0 == $clk_recorded) { + $clk_num++; + push @model_input_tokens,$tokens[4]; + } + } + # Could be subckt or .names + } elsif (".names" eq $tokens[0]) { + if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) { + # We want to know is this a buffer??? + my $lut_lines = &read_blifline($FIN,$line_no_ptr); + my @lut_lines_tokens = split('\s+',$lut_lines); + if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) { + # push it to the array: buffers_to_remove + push @buffers_to_remove,$tokens[1]; + push @buffers_to_rename,$tokens[2]; + } + } + } + } + # Re-organise the input lines + #print @model_input_tokens; + $input_lines = ".inputs "; + foreach my $temp(@model_input_tokens) { + if (".inputs" ne $temp) { + $input_lines .= $temp." "; + } + } + $input_lines =~ s/\s+$//; + @model_input_tokens = split('\s+',$input_lines); + + return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk); +} + +sub scan_blif() +{ + my ($line,$lines); + my @tokens; + my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded); + my ($blackbox,$model_clk_num); + my @input_tokens; + my $input_lines; + my (@input_buffer); + my ($line_no) = (0); + + if (!defined($finitial)) { + $latch_token = "re clk"; + } else { + my $latch_token_found = 0; + my $count = 0; + my ($FIN0) = FileHandle->new; + if ($FIN0->open("< $finitial")) { + print "INFO: Parsing $finitial...\n"; + } else { + die "ERROR: Fail to open $finitial!\n"; + } + while((!$latch_token_found)&&(!eof($FIN0))){ + # Get one line + $lines = &read_blifline($FIN0); + if (!defined($lines)) { + next; + } + @tokens = split('\s+',$lines); + if(".latch" eq $tokens[0]) { + if($#tokens == 5){ + $latch_token = "$tokens[3] $tokens[4]"; + $latch_token_found = 1; + } + } + } + close($FIN0); + } + + # Pre-process the netlist + # Open src file first-scan to check if we have clock + my ($FIN) = FileHandle->new; + if ($FIN->open("< $fname")) { + print "INFO: Parsing $fname...\n"; + } else { + die "ERROR: Fail to open $fname!\n"; + } + while(!eof($FIN)) { + # Get one line + $lines = &read_blifline($FIN); + if (!defined($lines)) { + next; + } + @tokens = split('\s+',$lines); + if (!defined($tokens[0])) { + next; + } + # When we found .model we should check it. until .end comes. + # Check if it is a black box + if (".model" eq $tokens[0]) { + ($input_lines,$blackbox,$model_clk_num,$have_default_clk,$need_default_clk) = &process_blifmodel($FIN,\$line_no); + if (0 == $blackbox) { + @input_tokens = @$input_lines; + } + $clk_num += $model_clk_num; + } + } + close($FIN); + + # Add default clock + if ("on" eq $add_default_clk) { + print "INFO: $clk_num clock ports need to be added.\n"; + print "INFO: have_default_clk: $have_default_clk, need_default_clk: $need_default_clk\n"; + if ((0 == $have_default_clk)&&(1 == $need_default_clk)) { + push @input_tokens,$default_clk_name; + } + } + # Bypass some sensitive tokens + for(my $itok = 0; $itok < $#input_tokens+1; $itok++) { + if ("unconn" eq $input_tokens[$itok]) { + delete $input_tokens[$itok]; + } + } + # Print Buffer names to be removed + my $num_buffer_to_remove = $#buffers_to_remove + 1; + print "INFO: $num_buffer_to_remove buffer to be removed:\n"; + for(my $itok = 0; $itok < $#buffers_to_remove+1; $itok++) { + print $buffers_to_remove[$itok]." will be renamed to ".$buffers_to_rename[$itok]."\n"; + } + + + # Second scan - write + my ($inputs_written) = (0); + my ($FIN2) = FileHandle->new; + if ($FIN2->open("< $fname")) { + print "INFO: Parsing $fname the second time...\n"; + } else { + die "ERROR: Fail to open $fname!\n"; + } + # Open des file + my ($FOUT) = (FileHandle->new); + if (!($FOUT->open("> $frpt"))) { + die "Fail to create output file: $frpt!\n"; + } + while(!eof($FIN2)) { + $line = <$FIN2>; + chomp $line; + if ($line eq "") { + print $FOUT "\n"; + next; + } + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + # Check if this line start with ".latch", which we cares only + @tokens = split('\s+',$line); + if ((".inputs" eq $tokens[0])&&(0 == $inputs_written)) { + $lines = $line; + while($lines =~ m/\\$/) { + $line = <$FIN2>; + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + $lines =~ s/\\$//; + $lines = $lines.$line; + } + #print @input_tokens."\n"; + &fprint_blifln($FOUT,\@input_tokens,$char_per_line); + $inputs_written = 1; + next; + } + if (".outputs" eq $tokens[0]) { + $lines = $line; + while($lines =~ m/\\$/) { + $line = <$FIN2>; + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + $lines =~ s/\\$//; + $lines = $lines.$line; + } + my @output_tokens = split('\s',$lines); + for(my $itok = 0; $itok < $#output_tokens+1; $itok++) { + if ("unconn" eq $output_tokens[$itok]) { + delete $output_tokens[$itok]; + } + } + &fprint_blifln($FOUT,\@output_tokens,$char_per_line); + next; + + } + if (".latch" eq $tokens[0]) { + # check if we need complete it + if ($#tokens == 3) { + # Complete it + for (my $i=0; $i<3; $i++) { + print $FOUT "$tokens[$i] "; + } + print $FOUT "$latch_token $tokens[3]\n"; + } elsif ($#tokens == 5) { + # replace the clock name with clk + for (my $i=0; $i < ($#tokens+1); $i++) { + # if (4 == $i) { + # print $FOUT "clk "; + # } else { + print $FOUT "$tokens[$i] "; + # } + } + print $FOUT "\n"; + } else { + die "ERROR: [LINE: $line_no]illegal definition of latch!\n"; + } + next; + } elsif (".names" eq $tokens[0]) { + if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) { + # We want to know is this a buffer??? + my $lut_lines = &read_blifline($FIN2,\$line_no); + my @lut_lines_tokens = split('\s+',$lut_lines); + if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) { + # pass it. + next; + } else { + print $FOUT "$line\n"; + print $FOUT "$lut_lines\n"; + } + } else { + print $FOUT "$line\n"; + } + next; + } elsif ((".subckt" eq $tokens[0])&&(1 == $remove_buffers)) { + $lines = $line; + $lines =~ s/\s+$//; + while($lines =~ m/\\$/) { + $line = <$FIN2>; + chomp $line; + # Replace the < and > with [ and ], VPR does not support... + $line =~ s//]/g; + $lines =~ s/\\$//; + $lines = $lines.$line; + $lines =~ s/\s+$//; #ODIN II has some shit space after \ !!!!! + } + my @subckt_tokens = split('\s+',$lines); + for(my $itok = 0; $itok < $#subckt_tokens+1; $itok++) { + if (($itok > 1)&&("" ne $subckt_tokens[$itok])) { + my @port_tokens = split('=',$subckt_tokens[$itok]); + for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) { + if ($port_tokens[1] eq $buffers_to_remove[$ibuf]) { + $port_tokens[1] = $buffers_to_rename[$ibuf]; + } + } + $subckt_tokens[$itok] = join ('=',$port_tokens[0],$port_tokens[1]); + #print "See:".$subckt_tokens[$itok]."\n"; + } + } + &fprint_blifln($FOUT,\@subckt_tokens,$char_per_line); + + next; + } + + print $FOUT "$line\n"; + } + close($FIN2); + close($FOUT); + return 0; +} + +sub main() +{ + &opts_read(); + &scan_blif(); + return 0; +} + +&main(); +exit(0); From 5116aa2ae1cc795b65c5e620a3158b5d59a4aa81 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 19:02:50 -0600 Subject: [PATCH 073/482] Added architecture and replaced variables --- .../k6_N10_sram_chain_HC_DPRAM_template.xml | 240 ++--- .../k6_N10_sram_chain_HC_template.xml | 966 +++++++++--------- .../k8_N10_sram_chain_FC_template.xml | 252 ++--- 3 files changed, 730 insertions(+), 728 deletions(-) diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml index c03b83855..10cd18ddd 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -1,76 +1,76 @@ - - - + + - - @@ -161,7 +161,7 @@ - + @@ -192,15 +192,15 @@ - + - + - + @@ -344,7 +344,7 @@ - + @@ -386,7 +386,7 @@ - + @@ -398,7 +398,7 @@ - + @@ -411,7 +411,7 @@ - + @@ -421,7 +421,7 @@ - + @@ -433,7 +433,7 @@ - + @@ -445,29 +445,29 @@ - - + - + @@ -488,14 +488,14 @@ @@ -509,7 +509,7 @@ - @@ -524,7 +524,7 @@ @@ -591,7 +591,7 @@ - @@ -607,7 +607,7 @@ - + @@ -662,9 +662,9 @@ - - - + + + @@ -693,14 +693,14 @@ - @@ -715,8 +715,8 @@ - @@ -727,7 +727,7 @@ - + @@ -831,8 +831,8 @@ 255e-12 255e-12 - - + + @@ -845,7 +845,7 @@ - + @@ -855,7 +855,7 @@ - + @@ -864,7 +864,7 @@ - + @@ -883,11 +883,11 @@ 202e-12 202e-12 - + - + @@ -937,14 +937,14 @@ - + - + @@ -954,7 +954,7 @@ - + @@ -973,7 +973,7 @@ - + @@ -1009,7 +1009,7 @@ - + @@ -1027,7 +1027,7 @@ - + @@ -1039,11 +1039,11 @@ - - + + - + @@ -1055,13 +1055,13 @@ - @@ -1095,8 +1095,8 @@ - @@ -1147,7 +1147,7 @@ - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index ab5e95413..fa32d4e41 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -1,76 +1,76 @@ - - - - - - @@ -148,7 +148,7 @@ - + @@ -170,7 +170,7 @@ - + @@ -178,15 +178,15 @@ - + - + - + @@ -210,7 +210,7 @@ 10e-12 - + @@ -221,7 +221,7 @@ 10e-12 - + @@ -232,7 +232,7 @@ 10e-12 - + @@ -243,7 +243,7 @@ 10e-12 - + @@ -289,7 +289,8 @@ - + + @@ -297,7 +298,8 @@ - + + @@ -330,16 +332,16 @@ - - - - - - - - - - + + + + + + + + + + @@ -372,19 +374,19 @@ - - - - - - - - - - - + + + + + + + + + + + - + @@ -393,21 +395,21 @@ - + - - - - - - - - - + + + + + + + + + - + @@ -419,29 +421,29 @@ - - + - + @@ -460,16 +462,16 @@ - @@ -483,7 +485,7 @@ - @@ -498,7 +500,7 @@ - + @@ -531,7 +533,7 @@ @@ -558,7 +560,7 @@ - @@ -574,136 +576,136 @@ - + - - + - - - - - + + + + + + + + + + + + + + + + - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - - - - - - - - - - - - + + + + + - + 255e-12 255e-12 255e-12 255e-12 255e-12 - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + - - - + + + + + + + + + - - - - - - - - - - - - - - + + + + + - + 202e-12 202e-12 202e-12 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - + - - + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - + + + + + - - + + + + + + - - - - - - - - - - - + + + + + + + + + + - + 261e-12 261e-12 261e-12 261e-12 261e-12 261e-12 - - - - - - - - - + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + - + diff --git a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml index 84d2c3ab3..72c966086 100644 --- a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml +++ b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml @@ -1,76 +1,76 @@ - - - + + - - @@ -148,7 +148,7 @@ - + @@ -177,7 +177,7 @@ - + @@ -185,7 +185,7 @@ - + @@ -237,10 +237,10 @@ 10e-12 - 10e-12 + 10e-12 - 10e-12 + 10e-12 @@ -290,7 +290,7 @@ - + @@ -342,7 +342,7 @@ - + @@ -350,7 +350,7 @@ - + @@ -362,7 +362,7 @@ - + @@ -373,7 +373,7 @@ - + @@ -384,7 +384,7 @@ - + @@ -397,29 +397,29 @@ - - + - + @@ -440,14 +440,14 @@ @@ -459,7 +459,7 @@ - @@ -479,7 +479,7 @@ @@ -539,7 +539,7 @@ - @@ -555,20 +555,20 @@ - + - @@ -580,8 +580,8 @@ - @@ -592,7 +592,7 @@ - + @@ -707,8 +707,8 @@ 235e-12 235e-12 - - + + @@ -721,7 +721,7 @@ - + @@ -731,7 +731,7 @@ - + @@ -740,7 +740,7 @@ - + @@ -759,11 +759,11 @@ 195e-12 195e-12 - + - + @@ -813,14 +813,14 @@ - + - + @@ -830,7 +830,7 @@ - + @@ -849,7 +849,7 @@ - + @@ -898,11 +898,11 @@ - + - + @@ -919,7 +919,7 @@ - + @@ -960,11 +960,11 @@ - + - + @@ -981,7 +981,7 @@ - + @@ -1020,11 +1020,11 @@ - + - + @@ -1042,7 +1042,7 @@ - + @@ -1054,11 +1054,11 @@ - - + + - + @@ -1070,13 +1070,13 @@ - @@ -1091,8 +1091,8 @@ - @@ -1131,7 +1131,7 @@ - + From 8f8707ff98bbb26de50e5441cd1d859ddda88cc5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 19:04:14 -0600 Subject: [PATCH 074/482] Added option to filter results after parsing --- .../misc/fpgaflow_default_tool_path.conf | 20 +++---- openfpga_flow/scripts/run_fpga_flow.py | 55 ++++++++++--------- 2 files changed, 39 insertions(+), 36 deletions(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index ce3e0a5c6..cf4d3e289 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -20,7 +20,7 @@ supported_flows = standard,vtr,vtr_standard,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , -clb_blocks = "Netlist clb blocks: ([0-9]+)", int +clb_blocks = "Netlist clb blocks: ([0-9]+)", str logic_delay = "Total logic delay: ([0-9.]+)", str total_net_delay = "total net delay: ([0-9.]+)", str total_routing_area = "Total routing area: ([0-9.]+)", str @@ -30,18 +30,18 @@ packing_time = "Packing took ([0-9.]+) seconds", str placement_time = "Placement took ([0-9.]+) seconds", str routing_time = "Routing took ([0-9.]+) seconds", str average_net_length = "average net length: ([0-9.]+)", str -critical_path = "Final critical path: ([0-9.]+) ns", float +critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific total_time_taken = "Routing took ([0-9.]+) seconds", float [DEFAULT_PARSE_RESULT_POWER] -pb_type_power="PB Types\s+([0-9]+)", float -routing_power="Routing\s+([0-9]+)", float -switch_box_power="Switch Box\s+([0-9]+)", float -connection_box_power="Connection Box\s+([0-9]+)", float -primitives_power="Primitives\s+([0-9]+)", float -interc_structures_power="Interc Structures\s+([0-9]+)", float -lut6_power="^\s+lut6\s+([0-9]+)", float -ff_power="^\s+ff\s+([0-9]+)", float +pb_type_power="PB Types\s+([0-9]+)", str +routing_power="Routing\s+([0-9]+)", str +switch_box_power="Switch Box\s+([0-9]+)", str +connection_box_power="Connection Box\s+([0-9]+)", str +primitives_power="Primitives\s+([0-9]+)", str +interc_structures_power="Interc Structures\s+([0-9]+)", str +lut6_power="^\s+lut6\s+([0-9]+)", str +ff_power="^\s+ff\s+([0-9]+)", str [INTERMIDIATE_FILE_PREFIX] diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index ad18e66ad..4509c2ef3 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -674,43 +674,46 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): return chan_width -def extract_vpr_stats(logfile): - # TODO: Sloppy code need improovement - # Without changing config input format - +def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): + section = "DEFAULT_PARSE_RESULT_POWER" if parse_section == "power" \ + else "DEFAULT_PARSE_RESULT_VPR" vpr_log = open(logfile).read() resultDict = {} - for name, value in config.items("DEFAULT_PARSE_RESULT_VPR"): - reg_string, _ = value.split(",") + for name, value in config.items(section): + reg_string, filt_function = value.split(",") match = re.search(reg_string[1:-1], vpr_log) if match: + try: + if "lambda" in filt_function.strip(): + eval("ParseFunction = "+filt_function.strip()) + extract_val = ParseFunction(**match.groups()) + elif filt_function.strip() == "int": + extract_val = int(match.group(1)) + elif filt_function.strip() == "float": + extract_val = float(match.group(1)) + elif filt_function.strip() == "str": + extract_val = str(match.group(1)) + elif filt_function.strip() == "scientific": + try: + mult = {"m":1E-3, "u":1E-6, "n":1E-9, + "K":1E-3, "M":1E-6, "G":1E-9,}.get(match.group(2)[0], 1) + except: + mult = 1 + extract_val = float(match.group(1))*mult + else: extract_val = match.group(1) + except: + logger.exception("Filter failed") + extract_val= "Filter Failed" resultDict[name] = extract_val dummyparser = ConfigParser() dummyparser.read_dict({"RESULTS": resultDict}) - with open('vpr_stat.result', 'w') as configfile: + with open(r_filename+'.result', 'w') as configfile: dummyparser.write(configfile) - logger.info("VPR statistics is extracted in file vpr_stat.result") - - -def extract_vpr_power_esti(logfile): - vpr_log = open(logfile).read() - resultDict = {} - for name, value in config.items("DEFAULT_PARSE_RESULT_VPR"): - reg_string, _ = value.split(",") - match = re.search(reg_string[1:-1], vpr_log) - if match: - extract_val = match.group(1) - resultDict[name] = extract_val - - dummyparser = ConfigParser() - dummyparser.read_dict({args.top_module+"_RESULTS": resultDict}) - - with open('vpr_power_stat.result', 'w') as configfile: - dummyparser.write(configfile) - logger.info("VPR_Power statistics are extracted vpr_power_stat.result") + logger.info("%s result extracted in file %s" % + (parse_section,r_filename+'.result')) def run_rewrite_verilog(): From 616d7706c9d774940e5f55193f0c17d0552257da Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 19:05:08 -0600 Subject: [PATCH 075/482] Added list of intermidiate files filename --- .../misc/fpgaflow_default_tool_path.conf | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index cf4d3e289..78e1dc46a 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -44,5 +44,32 @@ lut6_power="^\s+lut6\s+([0-9]+)", str ff_power="^\s+ff\s+([0-9]+)", str [INTERMIDIATE_FILE_PREFIX] +# Yosys files +yosys_out_blif=${PATH:TOP_MODULE}_yosys_out.blif +yosys_output=yosys_output.txt +# ACE2 and intermidiate file +activity_file=${PATH:TOP_MODULE}_ace_out.act +ace_output_blif=${PATH:TOP_MODULE}_ace_out.blif +corrected_format_blif=${PATH:TOP_MODULE}.blif +blackbox_blif=${PATH:TOP_MODULE}_bb.blif + +# VPR Files +min_chann_vpr_output=${PATH:TOP_MODULE}_min_chan_width_vpr.txt +reroute_chan_vpr_output=${PATH:TOP_MODULE}_reroute_vpr.txt +fixed_chan_vpr_output=${PATH:TOP_MODULE}_fr_chan_width.txt +vpr_stat_parse_fn=vpr_stat.txt +vpr_power_stat_parse_fn=vpr_power_stat.txt +vpr_net_file=${PATH:TOP_MODULE}_vpr.net +vpr_place_file=${PATH:TOP_MODULE}_vpr.place +vpr_route_file=${PATH:TOP_MODULE}_vpr.route + +#Iverilog verification file +iverilog_output=iverilog_output.txt +vvp_output=vvp_sim_output.txt + +[CMD_ARGUMENT_DEPENDANCY] +vpr_fpga_verilog=vpr_fpga_verilog_dir +vpr_fpga_verilog_dir=vpr_fpga_verilog +arg1=arg2,arg3,arg4|arg5 From 8d0153d34e03f24ea7d633a2cbe2e80f2dcf2454 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 19:06:01 -0600 Subject: [PATCH 076/482] Added gitignore to skip run directory tracking --- openfpga_flow/tasks/.gitignore | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 openfpga_flow/tasks/.gitignore diff --git a/openfpga_flow/tasks/.gitignore b/openfpga_flow/tasks/.gitignore new file mode 100644 index 000000000..aa8593f74 --- /dev/null +++ b/openfpga_flow/tasks/.gitignore @@ -0,0 +1,2 @@ +**/run[0-9][0-9][0-9] +**/latest \ No newline at end of file From 53941eaf5c98dbc4809c0d804644dd2c0147ff4d Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 19:06:46 -0600 Subject: [PATCH 077/482] Changed yosys output file name --- openfpga_flow/scripts/run_fpga_flow.py | 37 +++++++++++++-------- run_test.sh | 45 ++++++-------------------- 2 files changed, 32 insertions(+), 50 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 4509c2ef3..237944904 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -363,7 +363,7 @@ def run_yosys_with_abc(): for eachfile in args.benchmark_files]), "TOP_MODULE": args.top_module, "LUT_SIZE": lut_size, - "OUTPUT_BLIF": args.top_module+".blif", + "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", } yosys_template = os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") @@ -401,7 +401,7 @@ def run_abc_for_standarad(): def run_ace2(): if args.black_box_ace: - with open(args.top_module+'.blif', 'r') as fp: + with open(args.top_module+'_yosys_out.blif', 'r') as fp: blif_lines = fp.readlines() with open(args.top_module+'_bb.blif', 'w') as fp: @@ -431,7 +431,8 @@ def run_ace2(): fp.write(model_tmpl) # Prepare ACE run command command = [ - "-b", args.top_module+('_bb.blif' if args.black_box_ace else ".blif"), + "-b", args.top_module + + ('_bb.blif' if args.black_box_ace else "_yosys_out.blif"), "-o", args.top_module+"_ace_out.act", "-n", args.top_module+"_ace_out.blif", "-c", "clk", @@ -459,8 +460,8 @@ def run_ace2(): def run_pro_blif_3arg(): command = [ "-i", args.top_module+"_ace_out.blif", - "-o", args.top_module+"_ace_corrected_out.blif", - "-initial_blif", args.top_module+'.blif', + "-o", args.top_module+".blif", + "-initial_blif", args.top_module+'_yosys_out.blif', ] try: filename = args.top_module+'_blif_3args_output.txt' @@ -484,7 +485,7 @@ def run_pro_blif_3arg(): def run_vpr(): # Run Standard VPR Flow min_channel_width = run_standard_vpr( - args.top_module+"_ace_corrected_out.blif", + args.top_module+".blif", -1, args.top_module+"_min_chan_width_vpr.txt") logger.info("Standard VPR flow routed with minimum %d Channels" % @@ -499,7 +500,7 @@ def run_vpr(): " (Slack of %d%%)" % ((args.min_route_chan_width-1)*100)) while(1): - res = run_standard_vpr(args.top_module+"_ace_corrected_out.blif", + res = run_standard_vpr(args.top_module+".blif", int(min_channel_width), args.top_module+"_reroute_vpr.txt", route_only=True) @@ -516,12 +517,12 @@ def run_vpr(): min_channel_width) min_channel_width += 2 - extract_vpr_stats(args.top_module+"_min_channel_reroute_vpr.txt") + extract_vpr_stats(args.top_module+"_reroute_vpr.txt") # Fixed routing channel width elif args.fix_route_chan_width: min_channel_width = run_standard_vpr( - args.top_module+"_ace_corrected_out.blif", + args.top_module+".blif", args.fix_route_chan_width, args.top_module+"_fr_chan_width.txt") logger.info("Fixed routing channel successfully routed with %d width" % @@ -530,7 +531,9 @@ def run_vpr(): else: extract_vpr_stats(args.top_module+"_min_chan_width.txt") if args.power: - extract_vpr_power_esti(args.top_module+"_ace_corrected_out.power") + extract_vpr_stats(logfile=args.top_module+".power", + r_filename="vpr_power_stat", + parse_section="power") def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): @@ -701,7 +704,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): mult = 1 extract_val = float(match.group(1))*mult else: - extract_val = match.group(1) + extract_val = match.group(1) except: logger.exception("Filter failed") extract_val= "Filter Failed" @@ -719,7 +722,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): def run_rewrite_verilog(): # Rewrite the verilog after optimization script_cmd = [ - "read_blif %s" % args.top_module+"_ace_corrected_out.blif", + "read_blif %s" % args.top_module+".blif", "write_verilog %s" % args.top_module+"_output_verilog.v" ] command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] @@ -749,7 +752,7 @@ def run_netlists_verification(): command = [cad_tools["iverilog_path"]] command += ["-o", compiled_file] - command += ["./SRC/%s_ace_corrected_out_include_netlists.v" % + command += ["./SRC/%s_include_netlists.v" % args.top_module] command += ["-s"] if args.vpr_fpga_verilog_formal_verification_top_netlist: @@ -759,7 +762,11 @@ def run_netlists_verification(): run_command("iverilog_verification", "iverilog_output.txt", command) vvp_command = ["vvp", compiled_file] - run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) + output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) + if "Succeed" in output: + logger.info("VVP Simulation Successful") + else: + logger.info(str(output).split("\n")[-1]) def run_command(taskname, logfile, command, exit_if_fail=True): @@ -780,7 +787,9 @@ def run_command(taskname, logfile, command, exit_if_fail=True): process_failed_vpr_run(e.output) if exit_if_fail: clean_up_and_exit("Failed to run %s task" % taskname) + return None logger.info("%s is written in file %s" % (taskname, logfile)) + return process.stdout def process_failed_vpr_run(vpr_output): diff --git a/run_test.sh b/run_test.sh index a4e6524bc..2acefd58d 100644 --- a/run_test.sh +++ b/run_test.sh @@ -1,43 +1,16 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -./openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml \ +./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ --top_module s298 \ --power \ ---power_tech ./openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml \ +--power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \ --min_route_chan_width 1.3 \ --vpr_fpga_verilog \ ---vpr_fpga_verilog_dir ./SRC \ +--vpr_fpga_verilog_dir . \ --vpr_fpga_x2p_rename_illegal_port \ ---vpr_fpga_verilog_print_autocheck_top_testbench - - -# \ -# --end_flow_with_test \ -# --vpr_fpga_verilog_print_autocheck_top_testbench \ -# --vpr_fpga_verilog_include_icarus_simulator \ -# --vpr_fpga_verilog_formal_verification_top_netlist - - -# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/vpr', -# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/tmp/arch/k6_N10_rram_memory_bank_SC_winbond90.xml', 's298_ace_corrected_out.blif' -# '--net_file' -# 's298_vpr.net' -# '--place_file' -# 's298_vpr.place' -# '--route_file' -# 's298_vpr.route' -# '--full_stats' -# '--nodisp' -# '--power' -# '--activity_file' -# 's298_ace_out.act' -# '--tech_properties' -# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml' -# '--fpga_verilog' -# '--fpga_verilog_dir' -# './SRC' -# '--fpga_verilog_print_autocheck_top_testbench' -# 's298_output_verilog.v' -# '--fpga_verilog_print_formal_verification_top_netlist' -# '--fpga_verilog_include_icarus_simulator' -# '--fpga_x2p_rename_illegal_port' \ No newline at end of file +--end_flow_with_test \ +--vpr_fpga_verilog_include_icarus_simulator \ +--vpr_fpga_verilog_formal_verification_top_netlist \ +--vpr_fpga_verilog_include_timing \ +--vpr_fpga_verilog_include_signal_init \ +--vpr_fpga_verilog_print_autocheck_top_testbench \ No newline at end of file From 08b0ef355080f1158d22c02992cb41d3754e7882 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 21:28:23 -0600 Subject: [PATCH 078/482] Updated validate_command_line_arguments function + Checks if valid flow is provided as a argument + Command line argument list validated with dependencies provided in configuration file --- .../misc/fpgaflow_default_tool_path.conf | 13 +++----- openfpga_flow/scripts/run_fpga_flow.py | 33 ++++++++++++------- 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 78e1dc46a..d33fc4e80 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -12,11 +12,8 @@ pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl iverilog_path = iverilog include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists -[OPENFPGA_FLOW_CONFIG] -# You dont need to change any of these varaibles, -# Unless you are unhappy with intermidiate directories -# or modifying fpga_flow sript significantly -supported_flows = standard,vtr,vtr_standard,yosys_vpr +[FLOW_SCRIPT_CONFIG] +valid_flows = standard,vtr,vtr_standard,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , @@ -69,7 +66,5 @@ iverilog_output=iverilog_output.txt vvp_output=vvp_sim_output.txt [CMD_ARGUMENT_DEPENDANCY] -vpr_fpga_verilog=vpr_fpga_verilog_dir -vpr_fpga_verilog_dir=vpr_fpga_verilog -arg1=arg2,arg3,arg4|arg5 - +vpr_fpga_verilog=vpr_fpga_verilog_dir|abc +vpr_fpga_verilog_dir=vpr_fpga_verilog \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 237944904..65e153073 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -246,16 +246,22 @@ def validate_command_line_arguments(): """ TODO : This funtion validates all supplied paramters - and check for compatibility - Chec correct flow - Check if architecture and circuit files exist - if argument provide relative path replace to absolute - benchmark argument convert glob to list of files - Dont maintain the directory strcuture - Throw error for directory in benchmark - check if args.powertech_file is provided for power measurement """ - logger.info("Validating commnad line arguments - Pending implementation") + logger.info("Validating commnad line arguments") + + # Check if flow supported + if not args.fpga_flow in config.get("FLOW_SCRIPT_CONFIG", "valid_flows"): + clean_up_and_exit("%s Flow not supported"%args.fpga_flow) + + # Check if argument list is consistant + for eacharg, dependent in config.items("CMD_ARGUMENT_DEPENDANCY"): + if getattr(args, eacharg, None): + dependent = dependent.split(",") + for eachdep in dependent: + if not any([getattr(args, i, 0) for i in eachdep.split("|")]): + clean_up_and_exit("'%s' argument depends on (%s) argumets"% + (eacharg, ", ".join(dependent).replace("|", " or "))) + exit() # Filter provided architecrue files args.arch_file = os.path.abspath(args.arch_file) @@ -265,20 +271,25 @@ def validate_command_line_arguments(): # Filter provided benchmark files for index, everyinput in enumerate(args.benchmark_files): args.benchmark_files[index] = os.path.abspath(everyinput) + if os.path.isdir(args.benchmark_files[index]): + logger.warning("Skipping directory in bench %s" % everyinput) + logger.warning("Directory is not support in benchmark list" + + "use wildcard pattern to add files") + continue for everyfile in glob.glob(args.benchmark_files[index]): if not os.path.isfile(everyfile): clean_up_and_exit( "Failed to copy benchmark file-%s", args.arch_file) - # Filter provided architecrue files + # Filter provided powertech files if args.power_tech: args.power_tech = os.path.abspath(args.power_tech) if not os.path.isfile(args.power_tech): clean_up_and_exit( "Power Tech file not found. -%s", args.power_tech) + # Expand run directory to absolute path args.run_dir = os.path.abspath(args.run_dir) - pass def ask_user_quetion(condition, question): From afee2229af06369525fc52284d16acfa0486d8c6 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 19 Aug 2019 21:32:52 -0600 Subject: [PATCH 079/482] Removed unused templates and file from openfpga_flow directory --- openfpga_flow/misc/fpga_flow_script.conf | 31 --------------- openfpga_flow/misc/fpga_flow_template.sh | 38 ------------------- .../misc/openfpga_benchmark_list.txt | 6 --- .../misc/yosys_template_yosys_vpr_flow.ys | 22 ----------- 4 files changed, 97 deletions(-) delete mode 100644 openfpga_flow/misc/fpga_flow_script.conf delete mode 100644 openfpga_flow/misc/fpga_flow_template.sh delete mode 100644 openfpga_flow/misc/openfpga_benchmark_list.txt delete mode 100644 openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys diff --git a/openfpga_flow/misc/fpga_flow_script.conf b/openfpga_flow/misc/fpga_flow_script.conf deleted file mode 100644 index 3fd8c26db..000000000 --- a/openfpga_flow/misc/fpga_flow_script.conf +++ /dev/null @@ -1,31 +0,0 @@ -# Standard Configuration Example -[dir_path] -script_base = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/ -benchmark_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Verilog/MCNC/ -yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys -odin2_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/odin2.exe -cirkit_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/cirkit -abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc -abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc -abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc -mpack1_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/mpack1 -m2net_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/m2net -mpack2_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/mpack2 -vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr -rpt_dir = /var/tmp/Openfpga/results -ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace - -[flow_conf] -#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -flow_type = yosys_vpr -vpr_arch = ${PATH:OPENFPGA_PATH}/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml -mpack1_abc_stdlib = Not_Required -m2net_conf = Not_Required -mpack2_arch = Not_Required -power_tech_xml = ${PATH:OPENFPGA_PATH}/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml - -[csv_tags] -mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf: -mpack2_tags = BLE Number: | BLE Fill Rate: -vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles: -vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff diff --git a/openfpga_flow/misc/fpga_flow_template.sh b/openfpga_flow/misc/fpga_flow_template.sh deleted file mode 100644 index 473e117b9..000000000 --- a/openfpga_flow/misc/fpga_flow_template.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/bash - -# ========================================================================== -# Note: This shell script is parsed using python3 string templating system -# For correct parsing, please use $$ symbol in place of single \dollar sign -# variables can be declared using \dollar var_name -# Ref : https://docs.python.org/3/library/string.html#template-strings -# ========================================================================== -VTR_RUNTIME_ESTIMATE_SECONDS=1.70 -VTR_MEMORY_ESTIMATE_BYTES=0 - -VTR_RUNTIME_ESTIMATE_HUMAN_READABLE="2 seconds" -VTR_MEMORY_ESTIMATE_HUMAN_READABLE="0.00 MiB" - -#We redirect all command output to both stdout and the log file with 'tee'. - -#Begin I/O redirection -{ - - ${fpga_flow_script} \ - -conf ${conf_file} \ - -benchmark ${benchmark_list_file} \ - -rpt ${csv_rpt_file} \ - -vpr_fpga_verilog_dir ${verilog_output_path} \ - ${additional_params} - - #The IO redirection occurs in a sub-shell, - #so we need to exit it with the correct code - exit $$? - -} |& tee vtr_flow.out -#End I/O redirection - -#We used a pipe to redirect IO. -#To get the correct exit status we need to exit with the -#status of the first element in the pipeline (i.e. the real -#command run above) -exit $${PIPESTATUS[0]} diff --git a/openfpga_flow/misc/openfpga_benchmark_list.txt b/openfpga_flow/misc/openfpga_benchmark_list.txt deleted file mode 100644 index 3cf447f5a..000000000 --- a/openfpga_flow/misc/openfpga_benchmark_list.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Circuit Names, fixed routing channel width, -# PID/*.v, 120 -# up_counter/*.v, 30 -# MultiBitAdder/*.v, 30 -# i2c_master_top/*.v, 40 -asynch_fifo/*.v, 30 \ No newline at end of file diff --git a/openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys b/openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys deleted file mode 100644 index aeaded4b5..000000000 --- a/openfpga_flow/misc/yosys_template_yosys_vpr_flow.ys +++ /dev/null @@ -1,22 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} -# Read verilog files -${READ_VERILOG_FILE} - -# Technology mapping -hierarchy -top ${TOP_MODULE} -proc -techmap -D NO_LUT -map +/adff2dff.v - -# Synthesis -synth -top ${TOP_MODULE} -flatten -clean - -# LUT mapping -abc -lut ${LUT_SIZE} - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_blif ${OUTPUT_BLIF} From 0b8473e96098484d4b1cd1959fa5dcdb63bf621e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 16 Aug 2019 23:07:21 -0600 Subject: [PATCH 080/482] start developing graphs for muxes, with aims to simplify netlist and bitstream generation --- vpr7_x2p/vpr/SRC/device/mux_graph.h | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 vpr7_x2p/vpr/SRC/device/mux_graph.h diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h new file mode 100644 index 000000000..1b57a9d58 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -0,0 +1,48 @@ +/************************************************** + * This file include a data structure to describe + * the internal structure of a multiplexer + * using a generic graph representation + *************************************************/ + +#ifndef MUX_ARCH_H +#define MUX_ARCH_H + +#include +#include "circuit_library.h" + +/* Strong Ids for MUXes */ +struct mux_id_tag; +typedef vtr::StrongId MuxId; + +class MuxGraph { + private: /* data types used only in this class */ + enum e_mux_graph_node_type { + MUX_INPUT_NODE, + MUX_INTERNAL_NODE, + MUX_OUTPUT_NODE + }; + private: /* Internal data */ + std::vector node_ids_; /* Unique ids for each node */ + std::vector node_levels_; /* at which level, each node belongs to */ + std::vector node_types_; /* type of each node, input/output/internal */ + std::vector> node_in_edges; /* ids of incoming edges to each node */ + std::vector> node_out_edges; /* ids of outgoing edges from each node */ + + std::vector edge_ids_; /* Unique ids for each edge */ + std::vector edge_types_; /* type of each edge: tgate/pass-gate */ + std::vector edge_sram_ids_; /* ids of SRAMs that control the edge */ + + std::vector sram_ids_; /* ids of SRAMs (configuration memories) */ + + /* fast look-up */ + typedef std::vector>> NodeLookup; + mutable NodeLookup node_lookup_; /* [num_levels][num_branches][num_nodes_per_branch] */ +}; + +class MuxLib { + private: /* Internal data */ + vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ + vtr::vector circuit_model_ids_; /* ids in the circuit library, each MUX graph belongs to*/ +} + +#endif From 638969c3c96bb00ed66e9b2a25bb04bbfeba9553 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Aug 2019 14:37:22 -0600 Subject: [PATCH 081/482] adding mux graph data structures --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 42 +++++++++++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 3 + vpr7_x2p/libarchfpga/SRC/circuit_types.h | 1 + vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 79 ++++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_graph.h | 27 +++++-- vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h | 16 ++++ vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 73 ++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_utils.h | 22 ++++++ 8 files changed, 255 insertions(+), 8 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/device/mux_graph.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h create mode 100644 vpr7_x2p/vpr/SRC/device/mux_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/mux_utils.h diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 4da76e417..2230680b6 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -266,6 +266,34 @@ enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& return mux_structure_[circuit_model_id]; } +/* Return if additional constant inputs are required for a circuit model + * Only applicable for MUX circuit model + */ +bool CircuitLibrary::mux_add_const_input(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + /* A -1 value for the const values means there is no const inputs */ + return ( size_t(-1) != mux_const_input_values_[circuit_model_id] ); +} + +/* Return if additional constant inputs are required for a circuit model + * Only applicable for MUX circuit model + */ +size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + /* A -1 value for the const values means there is no const inputs */ + /* A 0 value for the const values means it is logic 0 */ + /* A 1 value for the const values means it is logic 1 */ + return mux_const_input_values_[circuit_model_id]; +} + /************************************************************************ * Public Accessors : Basic data query on Circuit Porst ***********************************************************************/ @@ -1158,6 +1186,8 @@ void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& circuit_mod /* validate that the type of this circuit_model should be MUX or LUT */ VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + /* validate the const input values */ + VTR_ASSERT( valid_mux_const_input_value(const_input_value) ); mux_const_input_values_[circuit_model_id] = const_input_value; return; } @@ -1700,6 +1730,18 @@ bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& circuit_model_i return ( size_t(circuit_edge_id) < edge_ids_[circuit_model_id].size() ) && ( circuit_edge_id == edge_ids_[circuit_model_id][circuit_edge_id] ); } +/* Validate the value of constant input + * A -1 value for the const values means there is no const inputs + * A 0 value for the const values means it is logic 0 + * A 1 value for the const values means it is logic 1 + * Others are invalid + */ +bool CircuitLibrary::valid_mux_const_input_value(const size_t& const_input_value) const { + return ( (size_t(-1) == const_input_value) + || (0 == const_input_value) + || (1 == const_input_value) ); +} + /* Invalidators */ /* Empty fast lookup for circuit_models*/ void CircuitLibrary::invalidate_circuit_model_lookup() const { diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 1717bb60f..6bfcb5a92 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -242,6 +242,8 @@ class CircuitLibrary { bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; enum e_spice_model_structure mux_structure(const CircuitModelId& circuit_model_id) const; + bool mux_add_const_input(const CircuitModelId& circuit_model_id) const; + size_t mux_const_input_value(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -457,6 +459,7 @@ class CircuitLibrary { bool valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; bool valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const; + bool valid_mux_const_input_value(const size_t& const_input_value) const; /* Invalidators */ void invalidate_circuit_model_lookup() const; void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/circuit_types.h index a2b86f38f..eff20f141 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_types.h @@ -101,6 +101,7 @@ enum e_spice_model_buffer_type { enum e_spice_model_pass_gate_logic_type { SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR, + SPICE_MODEL_PASS_GATE_RRAM, /* RRAM can be treated as a special type of pass-gate logic */ NUM_CIRCUIT_MODEL_PASS_GATE_TYPES }; diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp new file mode 100644 index 000000000..8873fd969 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -0,0 +1,79 @@ +/************************************************** + * This file includes member functions for the + * data structures in mux_graph.h + *************************************************/ +#include "util.h" +#include "vtr_assert.h" +#include "mux_utils.h" +#include "mux_graph.h" + +/************************************************** + * Member functions for the class MuxGraph + *************************************************/ + +/************************************************** + * Constructor + *************************************************/ + +/* Create an object based on a Circuit Model which is MUX */ +MuxGraph::MuxGraph(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size) { + /* Build the graph for a given multiplexer model */ + build_mux_graph(circuit_lib, circuit_model, mux_size); +} + +/************************************************** + * Private mutators + *************************************************/ + +/* Build the graph for a given multiplexer model */ +void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size) { + /* Make sure this model is a MUX */ + VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)); + + /* Make sure mux_size is valid */ + VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); + + /* Depends on the mux size, the actual multiplexer structure may change! */ + + /* Branch on multiplexer structures, leading to different building strategies */ + switch (circuit_lib.mux_structure(circuit_model)) { + case SPICE_MODEL_STRUCTURE_ONELEVEL: + break; + case SPICE_MODEL_STRUCTURE_MULTILEVEL: + break; + case SPICE_MODEL_STRUCTURE_TREE: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", + __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); + exit(1); + } +} + +/************************************************** + * Private validartors + *************************************************/ + +/* valid ids */ +bool MuxGraph::valid_node_id(const size_t& node_id) const { + return (node_id < node_ids_.size()); +} + + +/************************************************** + * End of Member functions for the class MuxGraph + *************************************************/ + +/************************************************** + * Member functions for the class MuxLibrary + *************************************************/ + +/************************************************** + * End of Member functions for the class MuxLibrary + *************************************************/ + diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 1b57a9d58..8ded42e62 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -1,5 +1,5 @@ /************************************************** - * This file include a data structure to describe + * This file includes a data structure to describe * the internal structure of a multiplexer * using a generic graph representation *************************************************/ @@ -8,12 +8,9 @@ #define MUX_ARCH_H #include +#include "mux_graph_fwd.h" #include "circuit_library.h" -/* Strong Ids for MUXes */ -struct mux_id_tag; -typedef vtr::StrongId MuxId; - class MuxGraph { private: /* data types used only in this class */ enum e_mux_graph_node_type { @@ -21,6 +18,20 @@ class MuxGraph { MUX_INTERNAL_NODE, MUX_OUTPUT_NODE }; + public: /* Constructors */ + /* Create an object based on a Circuit Model which is MUX */ + MuxGraph(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size); + public: /* Public accessors */ + private: /* Private mutators*/ + /* Build the graph for a given multiplexer model */ + void build_mux_graph(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size); + private: /* Private validators */ + /* valid ids */ + bool valid_node_id(const size_t& node_id) const; private: /* Internal data */ std::vector node_ids_; /* Unique ids for each node */ std::vector node_levels_; /* at which level, each node belongs to */ @@ -35,14 +46,14 @@ class MuxGraph { std::vector sram_ids_; /* ids of SRAMs (configuration memories) */ /* fast look-up */ - typedef std::vector>> NodeLookup; + typedef std::vector>> NodeLookup; mutable NodeLookup node_lookup_; /* [num_levels][num_branches][num_nodes_per_branch] */ }; -class MuxLib { +class MuxLibrary { private: /* Internal data */ vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ vtr::vector circuit_model_ids_; /* ids in the circuit library, each MUX graph belongs to*/ -} +}; #endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h new file mode 100644 index 000000000..bf6fd3a5b --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h @@ -0,0 +1,16 @@ +/************************************************** + * This file includes only declarations for + * the data structures to describe multiplexer structures + * Please refer to mux_graph.h for more details + *************************************************/ +#ifndef MUX_GRAPH_FWD_H +#define MUX_GRAPH_FWD_H + +/* Strong Ids for MUXes */ +struct mux_id_tag; +typedef vtr::StrongId MuxId; + +class MuxGraph; +class MuxLibrary; + +#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp new file mode 100644 index 000000000..686e2d1f9 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -0,0 +1,73 @@ +/************************************************** + * This file includes a series of most utilized functions + * that are used to implement a multiplexer + *************************************************/ + +#include "vtr_assert.h" +#include "mux_utils.h" + +/* Validate the number of inputs for a multiplexer implementation, + * the minimum supported size is 2 + * otherwise, there is no need for a MUX + */ +bool valid_mux_implementation_num_inputs(const size_t& mux_size) { + return (2 <= mux_size); +} + +/************************************************** + * Find the actual number of inputs for a multiplexer implementation + * 1. if there are no requirements on constant inputs, mux_size is the actual one + * 2. if there exist constant inputs, mux_size should plus 1 + *************************************************/ +size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size) { + /* Should be either MUX or LUT + * LUTs do have an tree-like MUX, but there is no need for a constant input! + */ + VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); + + if (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) { + return mux_size; + } + + if (true == circuit_lib.mux_add_const_input(circuit_model)) { + return mux_size + 1; + } + return mux_size; +} + +/************************************************** + * Find the structure for a multiplexer implementation + * 1. In most cases, the structure should follow the + * mux_structure defined by users in the CircuitLibrary + * 2. However, a special case may apply when mux_size is 2 + * In such case, we will force a TREE structure + * regardless of users' specification as this is the + * most efficient structure + *************************************************/ +enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size) { + /* Get the number of inputs */ + size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, circuit_model, mux_size); + /* Ensure the mux size is valid ! */ + VTR_ASSERT(valid_mux_implementation_num_inputs(impl_mux_size)); + + /* Branch on the mux sizes */ + if (2 == impl_mux_size) { + /* Tree-like is the best structure of CMOS MUX2 */ + if (SPICE_MODEL_DESIGN_CMOS == circuit_lib.design_tech_type(circuit_model)) { + return SPICE_MODEL_STRUCTURE_TREE; + } + VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(circuit_model)); + /* One-level is the best structure of RRAM MUX2 */ + return SPICE_MODEL_STRUCTURE_ONELEVEL; + } + + return circuit_lib.mux_structure(circuit_model); +} + + + diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h new file mode 100644 index 000000000..feba04571 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -0,0 +1,22 @@ +/************************************************** + * This file includes only declaration for the + * functions in mux_utils.c + * Please refer to the source file for more details + *************************************************/ +#ifndef MUX_UTILS_H +#define MUX_UTILS_H + +#include "circuit_library.h" + +bool valid_mux_implementation_num_inputs(const size_t& mux_size); + +size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size); + + +enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size); + +#endif From dcca9f4f0f920dc03041969aa9c10dbb3d759c33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Aug 2019 21:42:43 -0600 Subject: [PATCH 082/482] finish mux graph builders --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 31 ++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 2 + vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 413 ++++++++++++++++++- vpr7_x2p/vpr/SRC/device/mux_graph.h | 99 ++++- vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h | 9 + vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 60 ++- vpr7_x2p/vpr/SRC/device/mux_utils.h | 5 + 7 files changed, 590 insertions(+), 29 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 2230680b6..9689c8132 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -256,6 +256,26 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ return buffer_existence_[circuit_model_id][LUT_INTER_BUFFER]; } +/* Find the type of pass-gate logic for a circuit model (recursive function) + * Two cases to be considered: + * 1. this is a pass-gate circuit model, just find the data and return + * 2. this circuit model includes a pass-gate, find the link to pass-gate circuit model and go recursively + */ +enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + + /* Return the data if this is a pass-gate circuit model */ + if (SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)) { + return pass_gate_logic_types_[circuit_model_id]; + } + + /* Otherwise, we need to make sure this circuit model contains a pass-gate */ + CircuitModelId pgl_model_id = pass_gate_logic_circuit_model_ids_[circuit_model_id]; + VTR_ASSERT( CircuitModelId::INVALID() != pgl_model_id ); + return pass_gate_logic_type(pgl_model_id); +} + /* Return the multiplex structure of a circuit model */ enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& circuit_model_id) const { /* validate the circuit_model_id */ @@ -266,6 +286,17 @@ enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& return mux_structure_[circuit_model_id]; } + +size_t CircuitLibrary::mux_num_levels(const CircuitModelId& circuit_model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) + || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + + return mux_num_levels_[circuit_model_id]; +} + /* Return if additional constant inputs are required for a circuit model * Only applicable for MUX circuit model */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 6bfcb5a92..211475098 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -241,7 +241,9 @@ class CircuitLibrary { bool is_input_buffered(const CircuitModelId& circuit_model_id) const; bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; + enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& circuit_model_id) const; enum e_spice_model_structure mux_structure(const CircuitModelId& circuit_model_id) const; + size_t mux_num_levels(const CircuitModelId& circuit_model_id) const; bool mux_add_const_input(const CircuitModelId& circuit_model_id) const; size_t mux_const_input_value(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 8873fd969..1a883f7c5 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -2,6 +2,9 @@ * This file includes member functions for the * data structures in mux_graph.h *************************************************/ +#include +#include + #include "util.h" #include "vtr_assert.h" #include "mux_utils.h" @@ -24,8 +27,335 @@ MuxGraph::MuxGraph(const CircuitLibrary& circuit_lib, } /************************************************** - * Private mutators + * Public Accessors : Aggregates *************************************************/ +//Accessors +MuxGraph::node_range MuxGraph::nodes() const { + return vtr::make_range(node_ids_.begin(), node_ids_.end()); +} + +MuxGraph::edge_range MuxGraph::edges() const { + return vtr::make_range(edge_ids_.begin(), edge_ids_.end()); +} + +MuxGraph::mem_range MuxGraph::memories() const { + return vtr::make_range(mem_ids_.begin(), mem_ids_.end()); +} + +/************************************************** + * Public Accessors: Data query + *************************************************/ + +/* Find the number of inputs in the MUX graph */ +size_t MuxGraph::num_inputs() const { + /* FIXME: need to check if the graph is valid or not */ + /* Sum up the number of INPUT nodes in each level */ + size_t num_inputs = 0; + for (auto node_per_level : node_lookup_) { + num_inputs += node_per_level[MUX_INPUT_NODE].size(); + } + return num_inputs; +} + +/* Find the number of levels in the MUX graph */ +size_t MuxGraph::num_levels() const { + /* FIXME: need to check if the graph is valid or not */ + return node_lookup_.size(); +} + +/* Find the number of configuration memories in the MUX graph */ +size_t MuxGraph::num_memory_bits() const { + /* FIXME: need to check if the graph is valid or not */ + return mem_ids_.size(); +} + +/* Find the sizes of each branch of a MUX */ +std::vector MuxGraph::branch_sizes() const { + std::vector branch; + /* Visit each internal nodes/output nodes and find the the number of incoming edges */ + for (auto node : node_ids_ ) { + /* Bypass input nodes */ + if ( (MUX_OUTPUT_NODE != node_types_[node]) + && (MUX_INTERNAL_NODE != node_types_[node]) ) { + continue; + } + + size_t branch_size = node_in_edges_[node].size(); + + /* make sure the branch size is valid */ + VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size)); + + /* Nodes with the same number of incoming edges, indicate the same size of branch circuit */ + std::vector::iterator it; + it = std::find(branch.begin(), branch.end(), branch_size); + /* if already exists a branch with the same size, skip updating the vector */ + if (it == branch.end()) { + continue; + } + branch.push_back(branch_size); + } + + /* Sort the branch by size */ + std::sort(branch.begin(), branch.end()); + + return branch; +} + +/************************************************** + * Private mutators: basic operations + *************************************************/ +/* Add a unconfigured node to the MuxGraph */ +MuxNodeId MuxGraph::add_node(const enum e_mux_graph_node_type& node_type) { + MuxNodeId node = MuxNodeId(node_ids_.size()); + /* Push to the node list */ + node_ids_.push_back(node); + /* Resize the other node-related vectors */ + node_types_.push_back(node_type); + node_input_ids_.push_back(-1); + node_levels_.push_back(-1); + node_in_edges_.emplace_back(); + node_out_edges_.emplace_back(); + + return node; +} + +/* Add a edge connecting two nodes */ +MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node) { + MuxEdgeId edge = MuxEdgeId(edge_ids_.size()); + /* Push to the node list */ + edge_ids_.push_back(edge); + /* Resize the other node-related vectors */ + edge_types_.push_back(NUM_CIRCUIT_MODEL_PASS_GATE_TYPES); + edge_mem_ids_.push_back(MuxMemId::INVALID()); + edge_inv_mem_.push_back(false); + + /* update the node_in_edges and node_out_edges */ + VTR_ASSERT(valid_node_id(from_node)); + node_out_edges_[from_node].push_back(edge); + + VTR_ASSERT(valid_node_id(to_node)); + node_in_edges_[to_node].push_back(edge); + + return edge; +} + +/* Add a memory bit to the MuxGraph */ +MuxMemId MuxGraph::add_mem() { + MuxMemId mem = MuxMemId(mem_ids_.size()); + /* Push to the node list */ + mem_ids_.push_back(mem); + /* Resize the other node-related vectors */ + + return mem; +} + +/* Link an edge to a memory bit */ +void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) { + /* Make sure we have valid edge and mem */ + VTR_ASSERT( valid_edge_id(edge) && valid_mem_id(mem) ); + + edge_mem_ids_[edge] = mem; +} + +/************************************************** + * Private mutators: graph builders + *************************************************/ + +/* Build a graph for a multi-level multiplexer implementation + * support both generic multi-level and tree-like multiplexers + * + * a N:1 multi-level MUX + * ---------------------- + * + * input_node --->+ + * | + * input_node --->| + * |--->+ + * ... | | + * | | + * input_node --->+ |---> ... + * | + * ... --->+ --->+ + * | + * ... ... |---> output_node + * | + * ... --->+ --->+ + * | + * input_node --->+ |---> ... + * | | + * input_node --->| | + * |--->+ + * ... | + * | + * input_node --->+ + * + * tree-like multiplexer graph will look like: + * -------------------------------------------- + * + * input_node --->+ + * |--->+ + * input_node --->+ |---> ... + * | + * --->+ --->+ + * ... ... ... |----> output_node + * ... --->+ --->+ + * |---> ... + * input_node --->+ | + * |--->+ + * input_node --->+ + * + */ +void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, + const size_t& num_levels, const size_t& num_inputs_per_branch, + const enum e_spice_model_pass_gate_logic_type& pgl_type) { + /* Number of memory bits is definite, add them */ + for (size_t i = 0; i < num_inputs_per_branch * num_levels; ++i) { + add_mem(); + } + + /* Create a fast node lookup locally. + * Only used for building the graph + * it sorts the nodes by levels and ids at each level + */ + std::vector> node_lookup; /* [num_levels][num_nodes_per_level] */ + node_lookup.resize(num_levels + 1); + + /* Number of outputs is definite, add and configure */ + MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); + node_levels_[output_node] = num_levels; + /* Update node lookup */ + node_lookup[num_levels].push_back(output_node); + + /* keep a list of node ids which can be candidates for input nodes */ + std::vector input_node_ids; + + /* Add internal nodes level by level, + * we start from the last level, following a strategy like tree growing + */ + for (size_t lvl = num_levels - 1; ; --lvl) { + /* Expand from the existing nodes + * Last level should expand from output_node + * Other levels will expand from internal nodes! + */ + for (MuxNodeId seed_node : node_lookup[lvl + 1]) { + /* Add a new node and connect to seed_node, until we reach the num_inputs_per_branch */ + for (size_t i = 0; i < num_inputs_per_branch; ++i) { + /* We deposite a type of INTERNAL_NODE, + * later it will be configured to INPUT if it is in the input list + */ + MuxNodeId expand_node = add_node(MUX_INTERNAL_NODE); + + /* Node level is deterministic */ + node_levels_[expand_node] = lvl; + + /* Create an edge and connect the two nodes */ + MuxEdgeId edge = add_edge(expand_node, seed_node); + /* Configure the edge */ + edge_types_[edge] = pgl_type; + + /* Memory id depends on the level and offset in the current branch + * if number of inputs per branch is 2, it indicates a tree-like multiplexer, + * every two edges will share one memory bit + * otherwise, each edge corresponds to a memory bit + */ + + if ( 2 == num_inputs_per_branch) { + MuxMemId mem_id = MuxMemId( (lvl - 1) ); + set_edge_mem_id(edge, mem_id); + /* If this is a second edge in the branch, we will assign it to an inverted edge */ + if (0 != i % num_inputs_per_branch) { + edge_inv_mem_[edge] = true; + } + } else { + MuxMemId mem_id = MuxMemId( (lvl - 1) * num_inputs_per_branch + i ); + set_edge_mem_id(edge, mem_id); + } + + /* Update node lookup */ + node_lookup[lvl].push_back(expand_node); + + /* Push the node to input list, and then remove the seed_node from the list */ + input_node_ids.push_back(expand_node); + /* Remove the node if the seed node is the list */ + std::vector::iterator it = find(input_node_ids.begin(), input_node_ids.end(), seed_node); + if (it != input_node_ids.end()) { + input_node_ids.erase(it); + } + + /* Check the number of input nodes, if already meet the demand, we can finish here */ + if (mux_size != input_node_ids.size()) { + continue; /* We need more inputs, keep looping */ + } + + /* The graph is done, we configure the input nodes and then we can return */ + /* We must be in level 0 !*/ + VTR_ASSERT( 0 == lvl ) ; + for (MuxNodeId input_node : input_node_ids) { + node_types_[input_node] = MUX_INPUT_NODE; + } + + /* Sort the nodes by the levels and offset */ + size_t input_cnt = 0; + for (auto lvl_nodes : node_lookup) { + for (MuxNodeId cand_node : lvl_nodes) { + if (MUX_INPUT_NODE != node_types_[cand_node]) { + continue; + } + /* Update the input node ids */ + node_input_ids_[cand_node] = input_cnt; + /* Update the counter */ + input_cnt++; + } + } + /* Make sure we visited all the inputs in the cache */ + VTR_ASSERT(input_cnt == input_node_ids.size()); + /* Finish building the graph for a multi-level multiplexer */ + return; + } + } + } + /* Finish building the graph for a multi-level multiplexer */ +} + +/* Build the graph for a given one-level multiplexer implementation + * a N:1 one-level MUX + * + * input_node --->+ + * | + * input_node --->| + * |--> output_node + * ... | + * | + * input_node --->+ + */ +void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, + const enum e_spice_model_pass_gate_logic_type& pgl_type) { + /* We definitely know how many nodes we need, + * N inputs, 1 output and 0 internal nodes + */ + MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); + node_levels_[output_node] = 1; + + for (size_t i = 0; i < mux_size; ++i) { + MuxNodeId input_node = add_node(MUX_INPUT_NODE); + /* All the node belong to level 0 (we have only 1 level) */ + node_input_ids_[input_node] = i; + node_levels_[input_node] = 0; + + /* We definitely know how many edges we need, + * the same as mux_size, add a edge connecting two nodes + */ + MuxEdgeId edge = add_edge(input_node, output_node); + /* Configure the edge */ + edge_types_[edge] = pgl_type; + + /* Create a memory bit*/ + MuxMemId mem = add_mem(); + /* Link the edge to a memory bit */ + set_edge_mem_id(edge, mem); + } + /* Finish building the graph for a one-level multiplexer */ +} /* Build the graph for a given multiplexer model */ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, @@ -37,33 +367,98 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, /* Make sure mux_size is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); - /* Depends on the mux size, the actual multiplexer structure may change! */ + size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, circuit_model, mux_size); + + /* Depends on the mux size, the implemented multiplexer structure may change! */ + enum e_spice_model_structure impl_structure = find_mux_implementation_structure(circuit_lib, circuit_model, impl_mux_size); /* Branch on multiplexer structures, leading to different building strategies */ - switch (circuit_lib.mux_structure(circuit_model)) { - case SPICE_MODEL_STRUCTURE_ONELEVEL: + switch (impl_structure) { + case SPICE_MODEL_STRUCTURE_TREE: { + /* Find the number of levels */ + size_t num_levels = find_treelike_mux_num_levels(mux_size); + + /* Find the number of inputs per branch, this is not final */ + size_t num_inputs_per_branch = 2; + + /* Build a multilevel mux graph */ + build_multilevel_mux_graph(impl_mux_size, num_levels, num_inputs_per_branch, circuit_lib.pass_gate_logic_type(circuit_model)); break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: + } + case SPICE_MODEL_STRUCTURE_ONELEVEL: { + build_onelevel_mux_graph(impl_mux_size, circuit_lib.pass_gate_logic_type(circuit_model)); break; - case SPICE_MODEL_STRUCTURE_TREE: + } + case SPICE_MODEL_STRUCTURE_MULTILEVEL: { + /* Find the number of inputs per branch, this is not final */ + size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(mux_size, circuit_lib.mux_num_levels(circuit_model)); + + /* Build a multilevel mux graph */ + build_multilevel_mux_graph(impl_mux_size, circuit_lib.mux_num_levels(circuit_model), + num_inputs_per_branch, + circuit_lib.pass_gate_logic_type(circuit_model)); break; + } default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); exit(1); } + + /* Since the graph is finalized, it is time to build the fast look-up */ + build_node_lookup(); +} + +/* Build fast node lookup */ +void MuxGraph::build_node_lookup() { + /* Invalidate the node lookup if necessary */ + invalidate_node_lookup(); + + /* Find the maximum number of levels */ + size_t num_levels = 0; + for (auto node : nodes()) { + num_levels = std::max((int)node_levels_[node], (int)num_levels); + } + + /* Resize node_lookup */ + node_lookup_.resize(num_levels + 1); + for (size_t lvl = 0; lvl < node_lookup_.size(); ++lvl) { + /* Resize by number of node types */ + node_lookup_[lvl].resize(NUM_MUX_NODE_TYPES); + } + + /* Fill the node lookup */ + for (auto node : nodes()) { + node_lookup_[node_levels_[node]][size_t(node_types_[node])].push_back(node); + } +} + +bool MuxGraph::valid_node_lookup() const { + return node_lookup_.empty(); +} + +/* Invalidate (empty) the node fast lookup*/ +void MuxGraph::invalidate_node_lookup() { + node_lookup_.clear(); } /************************************************** - * Private validartors + * Private validators *************************************************/ /* valid ids */ -bool MuxGraph::valid_node_id(const size_t& node_id) const { - return (node_id < node_ids_.size()); +bool MuxGraph::valid_node_id(const MuxNodeId& node) const { + return size_t(node) < node_ids_.size() && node_ids_[node] == node; } +bool MuxGraph::valid_edge_id(const MuxEdgeId& edge) const { + return size_t(edge) < edge_ids_.size() && edge_ids_[edge] == edge; +} + +bool MuxGraph::valid_mem_id(const MuxMemId& mem) const { + return size_t(mem) < mem_ids_.size() && mem_ids_[mem] == mem; +} /************************************************** * End of Member functions for the class MuxGraph diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 8ded42e62..7090093ac 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -2,12 +2,34 @@ * This file includes a data structure to describe * the internal structure of a multiplexer * using a generic graph representation + * A Branch is a N:1 MUX in the part of MUX graph + * + * branch_input --->+ + * | + * branch_input --->| + * |--> branch_out + * ... | + * | + * branch_input --->+ + * + * A short example of how a two-level MUX is organized by branches + * + * +-----------+ +--------+ + * mux_inputs--->| Branch[0] |--->| | + * +-----------+ | | + * ... | Branch |---> mux_out + * +-----------+ | [N+1] | + * mux_inputs--->| Branch[N] |--->| | + * +-----------+ +--------+ + * *************************************************/ + #ifndef MUX_ARCH_H #define MUX_ARCH_H -#include +#include "vtr_vector.h" +#include "vtr_range.h" #include "mux_graph_fwd.h" #include "circuit_library.h" @@ -16,38 +38,83 @@ class MuxGraph { enum e_mux_graph_node_type { MUX_INPUT_NODE, MUX_INTERNAL_NODE, - MUX_OUTPUT_NODE + MUX_OUTPUT_NODE, + NUM_MUX_NODE_TYPES }; + public: /* Types and ranges */ + typedef vtr::vector::const_iterator node_iterator; + typedef vtr::vector::const_iterator edge_iterator; + typedef vtr::vector::const_iterator mem_iterator; + + typedef vtr::Range node_range; + typedef vtr::Range edge_range; + typedef vtr::Range mem_range; public: /* Constructors */ /* Create an object based on a Circuit Model which is MUX */ MuxGraph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); - public: /* Public accessors */ - private: /* Private mutators*/ + public: /* Public accessors: Aggregates */ + node_range nodes() const; + edge_range edges() const; + mem_range memories() const; + public: /* Public accessors: Data query */ + /* Find the number of inputs in the MUX graph */ + size_t num_inputs() const; + /* Find the number of levels in the MUX graph */ + size_t num_levels() const; + /* Find the number of SRAMs in the MUX graph */ + size_t num_memory_bits() const; + /* Find the sizes of each branch of a MUX */ + std::vector branch_sizes() const; + private: /* Private mutators : basic operations */ + /* Add a unconfigured node to the MuxGraph */ + MuxNodeId add_node(const enum e_mux_graph_node_type& node_type); + /* Add a edge connecting two nodes */ + MuxEdgeId add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node); + /* Add a memory bit to the MuxGraph */ + MuxMemId add_mem(); + /* Link an edge to a mem */ + void set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem); + private: /* Private mutators : graph builders */ + void build_multilevel_mux_graph(const size_t& mux_size, + const size_t& num_levels, const size_t& num_inputs_per_branch, + const enum e_spice_model_pass_gate_logic_type& pgl_type); + /* Build the graph for a given one-level multiplexer implementation */ + void build_onelevel_mux_graph(const size_t& mux_size, + const enum e_spice_model_pass_gate_logic_type& pgl_type); /* Build the graph for a given multiplexer model */ void build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); + /* Build fast node lookup */ + void build_node_lookup(); private: /* Private validators */ /* valid ids */ - bool valid_node_id(const size_t& node_id) const; + bool valid_node_id(const MuxNodeId& node) const; + bool valid_edge_id(const MuxEdgeId& edge) const; + bool valid_mem_id(const MuxMemId& mem) const; + /* validate/invalidate node lookup */ + bool valid_node_lookup() const; + void invalidate_node_lookup(); private: /* Internal data */ - std::vector node_ids_; /* Unique ids for each node */ - std::vector node_levels_; /* at which level, each node belongs to */ - std::vector node_types_; /* type of each node, input/output/internal */ - std::vector> node_in_edges; /* ids of incoming edges to each node */ - std::vector> node_out_edges; /* ids of outgoing edges from each node */ + vtr::vector node_ids_; /* Unique ids for each node */ + vtr::vector node_types_; /* type of each node, input/output/internal */ + vtr::vector node_input_ids_; /* Unique ids for each node as an input of the MUX */ + vtr::vector node_levels_; /* at which level, each node belongs to */ + vtr::vector> node_in_edges_; /* ids of incoming edges to each node */ + vtr::vector> node_out_edges_; /* ids of outgoing edges from each node */ - std::vector edge_ids_; /* Unique ids for each edge */ - std::vector edge_types_; /* type of each edge: tgate/pass-gate */ - std::vector edge_sram_ids_; /* ids of SRAMs that control the edge */ + vtr::vector edge_ids_; /* Unique ids for each edge */ + vtr::vector edge_types_; /* type of each edge: tgate/pass-gate */ + vtr::vector edge_mem_ids_; /* ids of memory bit that control the edge */ + vtr::vector edge_inv_mem_; /* if the edge is controlled by an inverted output of a memory bit */ - std::vector sram_ids_; /* ids of SRAMs (configuration memories) */ + vtr::vector mem_ids_; /* ids of configuration memories */ /* fast look-up */ - typedef std::vector>> NodeLookup; - mutable NodeLookup node_lookup_; /* [num_levels][num_branches][num_nodes_per_branch] */ + typedef std::vector>> NodeLookup; + mutable NodeLookup node_lookup_; /* [num_levels][num_types][num_nodes_per_level] */ }; class MuxLibrary { diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h index bf6fd3a5b..f85051568 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h @@ -6,9 +6,18 @@ #ifndef MUX_GRAPH_FWD_H #define MUX_GRAPH_FWD_H +#include "vtr_strong_id.h" + /* Strong Ids for MUXes */ struct mux_id_tag; +struct mux_node_id_tag; +struct mux_edge_id_tag; +struct mux_mem_id_tag; + typedef vtr::StrongId MuxId; +typedef vtr::StrongId MuxNodeId; +typedef vtr::StrongId MuxEdgeId; +typedef vtr::StrongId MuxMemId; class MuxGraph; class MuxLibrary; diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 686e2d1f9..555304647 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -2,7 +2,9 @@ * This file includes a series of most utilized functions * that are used to implement a multiplexer *************************************************/ +#include +#include "util.h" #include "vtr_assert.h" #include "mux_utils.h" @@ -50,13 +52,11 @@ size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { - /* Get the number of inputs */ - size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, circuit_model, mux_size); /* Ensure the mux size is valid ! */ - VTR_ASSERT(valid_mux_implementation_num_inputs(impl_mux_size)); + VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); /* Branch on the mux sizes */ - if (2 == impl_mux_size) { + if (2 == mux_size) { /* Tree-like is the best structure of CMOS MUX2 */ if (SPICE_MODEL_DESIGN_CMOS == circuit_lib.design_tech_type(circuit_model)) { return SPICE_MODEL_STRUCTURE_TREE; @@ -69,5 +69,57 @@ enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibr return circuit_lib.mux_structure(circuit_model); } +/************************************************** + * Find the number of levels for a tree-like multiplexer implementation + *************************************************/ +size_t find_treelike_mux_num_levels(const size_t& mux_size) { + /* Do log2(mux_size), have a basic number */ + size_t level = (size_t)(log((double)mux_size)/log(2.)); + /* Fix the error, i.e. mux_size=5, level = 2, we have to complete */ + while (mux_size > pow(2.,(double)level)) { + level++; + } + return level; +} + +/************************************************** + * Find the number of inputs for majority of branches + * in a multi-level multiplexer implementation + *************************************************/ +size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, + const size_t& mux_level) { + /* Special Case: mux_size = 2 */ + if (2 == mux_size) { + return mux_size; + } + + if (1 == mux_level) { + return mux_size; + } + + if (2 == mux_level) { + size_t num_input_per_unit = (size_t)sqrt(mux_size); + while ( num_input_per_unit * num_input_per_unit < mux_size) { + num_input_per_unit++; + } + return num_input_per_unit; + } + + VTR_ASSERT_SAFE(2 < mux_level); + + size_t num_input_per_unit = 2; + while (pow((double)num_input_per_unit, (double)mux_level) < mux_size) { + num_input_per_unit++; + } + + if (!valid_mux_implementation_num_inputs(num_input_per_unit)) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Number of inputs of each basis should be at least 2!\n", + __FILE__, __LINE__); + exit(1); + } + + return num_input_per_unit; +} diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index feba04571..9e21305d8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -19,4 +19,9 @@ enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibr const CircuitModelId& circuit_model, const size_t& mux_size); +size_t find_treelike_mux_num_levels(const size_t& mux_size); + +size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, + const size_t& mux_level); + #endif From 153d506abb01d2769a61bd83b748c2c61000ccd4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Aug 2019 00:06:38 -0600 Subject: [PATCH 083/482] add graph-based mux decoding function --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 133 +++++++++++++++++++++--- vpr7_x2p/vpr/SRC/device/mux_graph.h | 17 ++- vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h | 2 + 3 files changed, 135 insertions(+), 17 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 1a883f7c5..6655619c8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -60,7 +60,8 @@ size_t MuxGraph::num_inputs() const { /* Find the number of levels in the MUX graph */ size_t MuxGraph::num_levels() const { /* FIXME: need to check if the graph is valid or not */ - return node_lookup_.size(); + /* The num_levels by definition excludes the level for outputs, so a deduection is applied */ + return node_lookup_.size() - 1; } /* Find the number of configuration memories in the MUX graph */ @@ -101,6 +102,57 @@ std::vector MuxGraph::branch_sizes() const { return branch; } +/* Get the node id of a given input */ +MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { + /* Use the node_lookup to accelerate the search */ + for (const auto& lvl : node_lookup_) { + for (const auto& cand_node : lvl[MUX_INPUT_NODE]) { + if (input_id == node_input_ids_[cand_node]) { + return cand_node; + } + } + } + + return MuxNodeId::INVALID(); +} + +/* Decode memory bits based on an input id */ +std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id) const { + /* initialize the memory bits: TODO: support default value */ + std::vector mem_bits(mem_ids_.size(), 0); + + /* valid the input */ + VTR_ASSERT_SAFE(valid_input_id(input_id)); + + /* Route the input to the output and update mem */ + MuxNodeId next_node = node_id(input_id); + while ( 0 < node_out_edges_[next_node].size() ) { + VTR_ASSERT_SAFE (1 == node_out_edges_[next_node].size()); + MuxEdgeId edge = node_out_edges_[next_node][0]; + + /* Configure the mem bits: + * if inv_mem is enabled, it means 0 to enable this edge + * otherwise, it is 1 to enable this edge + */ + MuxMemId mem = edge_mem_ids_[edge]; + VTR_ASSERT_SAFE (valid_mem_id(mem)); + if (true == edge_inv_mem_[edge]) { + mem_bits[size_t(mem)] = 0; + } else { + mem_bits[size_t(mem)] = 1; + } + + /* each edge must have 1 fan-out */ + VTR_ASSERT_SAFE (1 == edge_sink_nodes_[edge].size()); + + /* Visit the next node */ + next_node = edge_sink_nodes_[edge][0]; + } + VTR_ASSERT_SAFE(MUX_OUTPUT_NODE == node_types_[next_node]); + + return mem_bits; +} + /************************************************** * Private mutators: basic operations *************************************************/ @@ -111,7 +163,7 @@ MuxNodeId MuxGraph::add_node(const enum e_mux_graph_node_type& node_type) { node_ids_.push_back(node); /* Resize the other node-related vectors */ node_types_.push_back(node_type); - node_input_ids_.push_back(-1); + node_input_ids_.push_back(MuxInputId::INVALID()); node_levels_.push_back(-1); node_in_edges_.emplace_back(); node_out_edges_.emplace_back(); @@ -129,12 +181,14 @@ MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_nod edge_mem_ids_.push_back(MuxMemId::INVALID()); edge_inv_mem_.push_back(false); - /* update the node_in_edges and node_out_edges */ + /* update the edge-node connections */ VTR_ASSERT(valid_node_id(from_node)); + edge_src_nodes_[edge].push_back(from_node); node_out_edges_[from_node].push_back(edge); VTR_ASSERT(valid_node_id(to_node)); node_in_edges_[to_node].push_back(edge); + edge_sink_nodes_[edge].push_back(to_node); return edge; } @@ -302,7 +356,7 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, continue; } /* Update the input node ids */ - node_input_ids_[cand_node] = input_cnt; + node_input_ids_[cand_node] = MuxInputId(input_cnt); /* Update the counter */ input_cnt++; } @@ -339,7 +393,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, for (size_t i = 0; i < mux_size; ++i) { MuxNodeId input_node = add_node(MUX_INPUT_NODE); /* All the node belong to level 0 (we have only 1 level) */ - node_input_ids_[input_node] = i; + node_input_ids_[input_node] = MuxInputId(i); node_levels_[input_node] = 0; /* We definitely know how many edges we need, @@ -433,15 +487,6 @@ void MuxGraph::build_node_lookup() { node_lookup_[node_levels_[node]][size_t(node_types_[node])].push_back(node); } } - -bool MuxGraph::valid_node_lookup() const { - return node_lookup_.empty(); -} - -/* Invalidate (empty) the node fast lookup*/ -void MuxGraph::invalidate_node_lookup() { - node_lookup_.clear(); -} /************************************************** * Private validators @@ -460,6 +505,66 @@ bool MuxGraph::valid_mem_id(const MuxMemId& mem) const { return size_t(mem) < mem_ids_.size() && mem_ids_[mem] == mem; } +/* validate an input id (from which data path signal will be progagated to the output */ +bool MuxGraph::valid_input_id(const MuxInputId& input_id) const { + for (const auto& lvl : node_lookup_) { + for (const auto& node : lvl[MUX_INPUT_NODE]) { + if (size_t(input_id) > size_t(node_input_ids_[node])) { + return false; + } + } + } + + return true; +} + +bool MuxGraph::valid_node_lookup() const { + return node_lookup_.empty(); +} + +/* Invalidate (empty) the node fast lookup*/ +void MuxGraph::invalidate_node_lookup() { + node_lookup_.clear(); +} + +/* validate a mux graph and see if it is valid */ +bool MuxGraph::valid_mux_graph() const { + /* A valid MUX graph should be + * 1. every node has 1 fan-out except output node + * 2. every input can be routed to the output node + */ + for (const auto& node : nodes()) { + /* output node has 0 fan-out*/ + if (MUX_OUTPUT_NODE == node_types_[node]) { + continue; + } + /* other nodes should have 1 fan-out */ + if (1 != node_out_edges_[node].size()) { + return false; + } + } + + /* Try to route to output */ + for (const auto& node : nodes()) { + if (MUX_INPUT_NODE == node_types_[node]) { + MuxNodeId next_node = node; + while ( 0 < node_out_edges_[next_node].size() ) { + MuxEdgeId edge = node_out_edges_[next_node][0]; + /* each edge must have 1 fan-out */ + if (1 != edge_sink_nodes_[edge].size()) { + return false; + } + next_node = edge_sink_nodes_[edge][0]; + } + if (MUX_OUTPUT_NODE != node_types_[next_node]) { + return false; + } + } + } + + return true; +} + /************************************************** * End of Member functions for the class MuxGraph *************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 7090093ac..e9dd1e3bc 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -67,6 +67,10 @@ class MuxGraph { size_t num_memory_bits() const; /* Find the sizes of each branch of a MUX */ std::vector branch_sizes() const; + /* Get the node id of a given input */ + MuxNodeId node_id(const MuxInputId& input_id) const; + /* Decode memory bits based on an input id */ + std::vector decode_memory_bits(const MuxInputId& input_id) const; private: /* Private mutators : basic operations */ /* Add a unconfigured node to the MuxGraph */ MuxNodeId add_node(const enum e_mux_graph_node_type& node_type); @@ -94,18 +98,23 @@ class MuxGraph { bool valid_node_id(const MuxNodeId& node) const; bool valid_edge_id(const MuxEdgeId& edge) const; bool valid_mem_id(const MuxMemId& mem) const; + bool valid_input_id(const MuxInputId& input_id) const; /* validate/invalidate node lookup */ bool valid_node_lookup() const; void invalidate_node_lookup(); + /* validate graph */ + bool valid_mux_graph() const; private: /* Internal data */ vtr::vector node_ids_; /* Unique ids for each node */ - vtr::vector node_types_; /* type of each node, input/output/internal */ - vtr::vector node_input_ids_; /* Unique ids for each node as an input of the MUX */ - vtr::vector node_levels_; /* at which level, each node belongs to */ + vtr::vector node_types_; /* type of each node, input/output/internal */ + vtr::vector node_input_ids_; /* Unique ids for each node as an input of the MUX */ + vtr::vector node_levels_; /* at which level, each node belongs to */ vtr::vector> node_in_edges_; /* ids of incoming edges to each node */ vtr::vector> node_out_edges_; /* ids of outgoing edges from each node */ vtr::vector edge_ids_; /* Unique ids for each edge */ + vtr::vector> edge_src_nodes_; /* source nodes drive this edge */ + vtr::vector> edge_sink_nodes_; /* sink nodes this edge drives */ vtr::vector edge_types_; /* type of each edge: tgate/pass-gate */ vtr::vector edge_mem_ids_; /* ids of memory bit that control the edge */ vtr::vector edge_inv_mem_; /* if the edge is controlled by an inverted output of a memory bit */ @@ -119,8 +128,10 @@ class MuxGraph { class MuxLibrary { private: /* Internal data */ + /* MUX graph-based desription */ vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ vtr::vector circuit_model_ids_; /* ids in the circuit library, each MUX graph belongs to*/ + /* Local encoder description */ }; #endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h index f85051568..f4a163bb8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h @@ -13,11 +13,13 @@ struct mux_id_tag; struct mux_node_id_tag; struct mux_edge_id_tag; struct mux_mem_id_tag; +struct mux_input_id_tag; typedef vtr::StrongId MuxId; typedef vtr::StrongId MuxNodeId; typedef vtr::StrongId MuxEdgeId; typedef vtr::StrongId MuxMemId; +typedef vtr::StrongId MuxInputId; class MuxGraph; class MuxLibrary; From 893683fa95ce45a9c716a58f70f3134cb36f8dd3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 18 Aug 2019 12:31:59 -0600 Subject: [PATCH 084/482] start developing mux library --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 28 +++--- vpr7_x2p/vpr/SRC/device/mux_graph.h | 13 +-- vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h | 3 - vpr7_x2p/vpr/SRC/device/mux_library.cpp | 100 ++++++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_library.h | 47 ++++++++++ vpr7_x2p/vpr/SRC/device/mux_library_fwd.h | 20 +++++ 6 files changed, 180 insertions(+), 31 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library.h create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library_fwd.h diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 6655619c8..69e2da14e 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -48,7 +48,8 @@ MuxGraph::mem_range MuxGraph::memories() const { /* Find the number of inputs in the MUX graph */ size_t MuxGraph::num_inputs() const { - /* FIXME: need to check if the graph is valid or not */ + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_mux_graph()); /* Sum up the number of INPUT nodes in each level */ size_t num_inputs = 0; for (auto node_per_level : node_lookup_) { @@ -59,14 +60,16 @@ size_t MuxGraph::num_inputs() const { /* Find the number of levels in the MUX graph */ size_t MuxGraph::num_levels() const { - /* FIXME: need to check if the graph is valid or not */ + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_mux_graph()); /* The num_levels by definition excludes the level for outputs, so a deduection is applied */ return node_lookup_.size() - 1; } /* Find the number of configuration memories in the MUX graph */ size_t MuxGraph::num_memory_bits() const { - /* FIXME: need to check if the graph is valid or not */ + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_mux_graph()); return mem_ids_.size(); } @@ -487,6 +490,11 @@ void MuxGraph::build_node_lookup() { node_lookup_[node_levels_[node]][size_t(node_types_[node])].push_back(node); } } + +/* Invalidate (empty) the node fast lookup*/ +void MuxGraph::invalidate_node_lookup() { + node_lookup_.clear(); +} /************************************************** * Private validators @@ -522,11 +530,6 @@ bool MuxGraph::valid_node_lookup() const { return node_lookup_.empty(); } -/* Invalidate (empty) the node fast lookup*/ -void MuxGraph::invalidate_node_lookup() { - node_lookup_.clear(); -} - /* validate a mux graph and see if it is valid */ bool MuxGraph::valid_mux_graph() const { /* A valid MUX graph should be @@ -568,12 +571,3 @@ bool MuxGraph::valid_mux_graph() const { /************************************************** * End of Member functions for the class MuxGraph *************************************************/ - -/************************************************** - * Member functions for the class MuxLibrary - *************************************************/ - -/************************************************** - * End of Member functions for the class MuxLibrary - *************************************************/ - diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index e9dd1e3bc..dad40aaf7 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -24,9 +24,8 @@ * *************************************************/ - -#ifndef MUX_ARCH_H -#define MUX_ARCH_H +#ifndef MUX_GRAPH_H +#define MUX_GRAPH_H #include "vtr_vector.h" #include "vtr_range.h" @@ -126,12 +125,4 @@ class MuxGraph { mutable NodeLookup node_lookup_; /* [num_levels][num_types][num_nodes_per_level] */ }; -class MuxLibrary { - private: /* Internal data */ - /* MUX graph-based desription */ - vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ - vtr::vector circuit_model_ids_; /* ids in the circuit library, each MUX graph belongs to*/ - /* Local encoder description */ -}; - #endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h index f4a163bb8..815102e6d 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h @@ -9,19 +9,16 @@ #include "vtr_strong_id.h" /* Strong Ids for MUXes */ -struct mux_id_tag; struct mux_node_id_tag; struct mux_edge_id_tag; struct mux_mem_id_tag; struct mux_input_id_tag; -typedef vtr::StrongId MuxId; typedef vtr::StrongId MuxNodeId; typedef vtr::StrongId MuxEdgeId; typedef vtr::StrongId MuxMemId; typedef vtr::StrongId MuxInputId; class MuxGraph; -class MuxLibrary; #endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.cpp b/vpr7_x2p/vpr/SRC/device/mux_library.cpp new file mode 100644 index 000000000..717d1aac7 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library.cpp @@ -0,0 +1,100 @@ +/************************************************** + * This file includes member functions for the + * data structures in mux_library.h + *************************************************/ + +#include "vtr_assert.h" + +#include "mux_library.h" + +/************************************************** + * Member functions for the class MuxLibrary + *************************************************/ + + +/************************************************** + * Public accessors: data query + *************************************************/ +/* Get a MUX graph (read-only) */ +MuxId MuxLibrary::mux_graph(const CircuitModelId& circuit_model, + const size_t& mux_size) const { + /* Make sure we have a valid mux look-up */ + VTR_ASSERT_SAFE(valid_mux_lookup()); + /* Validate circuit model id and mux_size */ + VTR_ASSERT_SAFE(valid_mux_size(circuit_model, mux_size)); + + return mux_lookup_[circuit_model][mux_size]; +} + +const MuxGraph& MuxLibrary::mux_graph(const MuxId& mux_id) const { + VTR_ASSERT_SAFE(valid_mux_id(mux_id)); + return mux_graphs_[mux_id]; +} + +/************************************************** + * Private mutators: + *************************************************/ +/* Add a mux to the library */ +void MuxLibrary::add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { + /* First, check if there is already an existing graph */ + if (valid_mux_size(circuit_model, mux_size)) { + return; + } + + /* create a new id for the mux */ + MuxId mux = MuxId(mux_ids_.size()); + /* Push to the node list */ + mux_ids_.push_back(mux); + /* Add a mux graph */ + mux_graphs_.push_back(MuxGraph(circuit_lib, circuit_model, mux_size)); + + /* update mux_lookup*/ + mux_lookup_[circuit_model][mux_size] = mux; +} + +/************************************************** + * Private accessors: validator and invalidators + *************************************************/ +bool MuxLibrary::valid_mux_id(const MuxId& mux) const { + return size_t(mux) < mux_ids_.size() && mux_ids_[mux] == mux; +} + +bool MuxLibrary::valid_mux_lookup() const { + return mux_lookup_.empty(); +} + +bool MuxLibrary::valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const { + MuxLookup::iterator it = mux_lookup_.find(circuit_model); + return (it != mux_lookup_.end()); +} + +bool MuxLibrary::valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const { + if (false == valid_mux_circuit_model_id(circuit_model)) { + return false; + } + std::map::iterator it = mux_lookup_[circuit_model].find(mux_size); + return (it != mux_lookup_[circuit_model].end()); +} + +/************************************************** + * Private mutators: validator and invalidators + *************************************************/ + +/* Build fast node lookup */ +void MuxLibrary::build_mux_lookup() { + /* Invalidate the mux lookup if necessary */ + invalidate_mux_lookup(); +} + +/* Invalidate (empty) the mux fast lookup*/ +void MuxLibrary::invalidate_mux_lookup() { + mux_lookup_.clear(); +} + + +/************************************************** + * End of Member functions for the class MuxLibrary + *************************************************/ + + + diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h new file mode 100644 index 000000000..3c3b0329a --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library.h @@ -0,0 +1,47 @@ +/************************************************** + * This file includes a data structure to describe + * the multiplexer implementations in FPGA architectures + * MuxLibrary is a collection of multiplexers + * with various circuit-level description (related to + * the information available in CircuitLibrary + * and the input size of multiplexers) + *************************************************/ + +#ifndef MUX_LIBRARY_H +#define MUX_LIBRARY_H + +#include +#include "mux_graph.h" +#include "mux_library_fwd.h" + +class MuxLibrary { + public: /* Public accessors */ + /* Get a MUX graph (read-only) */ + MuxId mux_graph(const CircuitModelId& circuit_model, const size_t& mux_size) const; + const MuxGraph& mux_graph(const MuxId& mux_id) const; + public: /* Public mutators */ + /* Add a mux to the library */ + void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); + private: /* Private accessors */ + bool valid_mux_id(const MuxId& mux) const; + bool valid_mux_lookup() const; + bool valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const; + bool valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const; + private: /* Private mutators: mux_lookup */ + void build_mux_lookup(); + /* Invalidate (empty) the mux fast lookup*/ + void invalidate_mux_lookup(); + private: /* Internal data */ + /* MUX graph-based desription */ + vtr::vector mux_ids_; /* Unique identifier for each mux graph */ + vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ + + /* Local encoder description */ + //vtr::vector mux_local_encoders_; /* Graphs describing MUX internal structures */ + + /* a fast look-up to search mux_graphs with given circuit model and mux size */ + typedef std::map> MuxLookup; + mutable MuxLookup mux_lookup_; +}; + +#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_library_fwd.h new file mode 100644 index 000000000..7bc3091eb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library_fwd.h @@ -0,0 +1,20 @@ +/************************************************** + * This file includes only declarations for + * the data structures to describe multiplexer structures + * Please refer to mux_library.h for more details + *************************************************/ +#ifndef MUX_LIBRARY_FWD_H +#define MUX_LIBRARY_FWD_H + +#include "vtr_strong_id.h" + +/* Strong Ids for MUXes */ +struct mux_id_tag; +struct mux_local_decoder_id_tag; + +typedef vtr::StrongId MuxId; +typedef vtr::StrongId MuxLocalDecoderId; + +class MuxLibrary; + +#endif From bee070d7cc034d68ac4ea110d1ffd398eac7f2c3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Aug 2019 12:22:51 -0600 Subject: [PATCH 085/482] start plug in MUX library --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 29 ++++++++++++---- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 34 +++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_utils.h | 4 +++ .../SRC/fpga_x2p/verilog/verilog_submodules.c | 5 +++ 4 files changed, 65 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 69e2da14e..eb978750c 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -186,12 +186,14 @@ MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_nod /* update the edge-node connections */ VTR_ASSERT(valid_node_id(from_node)); + edge_src_nodes_.emplace_back(); edge_src_nodes_[edge].push_back(from_node); node_out_edges_[from_node].push_back(edge); VTR_ASSERT(valid_node_id(to_node)); - node_in_edges_[to_node].push_back(edge); + edge_sink_nodes_.emplace_back(); edge_sink_nodes_[edge].push_back(to_node); + node_in_edges_[to_node].push_back(edge); return edge; } @@ -265,8 +267,17 @@ void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) { void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, const size_t& num_levels, const size_t& num_inputs_per_branch, const enum e_spice_model_pass_gate_logic_type& pgl_type) { + /* Make sure mux_size for each branch is valid */ + VTR_ASSERT(valid_mux_implementation_num_inputs(num_inputs_per_branch)); + + /* In regular cases, there is 1 mem bit for each input of a branch */ + size_t num_mems_per_level = num_inputs_per_branch; + /* For 2-input branch, only 1 mem bit is needed for each level! */ + if (2 == num_inputs_per_branch) { + num_mems_per_level = 1; + } /* Number of memory bits is definite, add them */ - for (size_t i = 0; i < num_inputs_per_branch * num_levels; ++i) { + for (size_t i = 0; i < num_mems_per_level * num_levels; ++i) { add_mem(); } @@ -317,14 +328,14 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, */ if ( 2 == num_inputs_per_branch) { - MuxMemId mem_id = MuxMemId( (lvl - 1) ); + MuxMemId mem_id = MuxMemId(lvl); set_edge_mem_id(edge, mem_id); /* If this is a second edge in the branch, we will assign it to an inverted edge */ if (0 != i % num_inputs_per_branch) { edge_inv_mem_[edge] = true; } } else { - MuxMemId mem_id = MuxMemId( (lvl - 1) * num_inputs_per_branch + i ); + MuxMemId mem_id = MuxMemId( lvl * num_inputs_per_branch + i ); set_edge_mem_id(edge, mem_id); } @@ -387,6 +398,9 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, */ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, const enum e_spice_model_pass_gate_logic_type& pgl_type) { + /* Make sure mux_size is valid */ + VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); + /* We definitely know how many nodes we need, * N inputs, 1 output and 0 internal nodes */ @@ -419,7 +433,8 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { /* Make sure this model is a MUX */ - VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); /* Make sure mux_size is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); @@ -433,7 +448,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, switch (impl_structure) { case SPICE_MODEL_STRUCTURE_TREE: { /* Find the number of levels */ - size_t num_levels = find_treelike_mux_num_levels(mux_size); + size_t num_levels = find_treelike_mux_num_levels(impl_mux_size); /* Find the number of inputs per branch, this is not final */ size_t num_inputs_per_branch = 2; @@ -448,7 +463,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, } case SPICE_MODEL_STRUCTURE_MULTILEVEL: { /* Find the number of inputs per branch, this is not final */ - size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(mux_size, circuit_lib.mux_num_levels(circuit_model)); + size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(impl_mux_size, circuit_lib.mux_num_levels(circuit_model)); /* Build a multilevel mux graph */ build_multilevel_mux_graph(impl_mux_size, circuit_lib.mux_num_levels(circuit_model), diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 555304647..cc5b04ec8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -4,6 +4,7 @@ *************************************************/ #include +#include "spice_types.h" #include "util.h" #include "vtr_assert.h" #include "mux_utils.h" @@ -123,3 +124,36 @@ size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, return num_input_per_unit; } +/************************************************** + * Convert a linked list of MUX architecture to MuxLibrary + * TODO: this function will be deleted when MUXLibrary fully + * replace legacy data structures + *************************************************/ +MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head) { + t_llist* temp = muxes_head; + MuxLibrary mux_lib; + + /* Walk through the linked list */ + while(temp) { + VTR_ASSERT_SAFE(NULL != temp->dptr); + t_spice_mux_model* cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); + + /* Bypass the spice models who has a user-defined subckt */ + if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) { + /* Move on to the next*/ + temp = temp->next; + continue; + } + + /* Build a MUX graph for the model */ + /* Find the circuit model id by the name */ + CircuitModelId circuit_model = circuit_lib.circuit_model(cur_spice_mux_model->spice_model->name); + mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size); + + /* Move on to the next*/ + temp = temp->next; + } + + return mux_lib; +} + diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index 9e21305d8..730109957 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -6,7 +6,9 @@ #ifndef MUX_UTILS_H #define MUX_UTILS_H +#include "linkedlist.h" #include "circuit_library.h" +#include "mux_library.h" bool valid_mux_implementation_num_inputs(const size_t& mux_size); @@ -24,4 +26,6 @@ size_t find_treelike_mux_num_levels(const size_t& mux_size); size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, const size_t& mux_level); +MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index d3661126b..d9183c91e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -38,6 +38,8 @@ #include "verilog_submodules.h" +#include "mux_utils.h" + /***** Subroutines *****/ static @@ -2762,6 +2764,9 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Alloc the muxes*/ muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); + + /* TODO: this is temporary. Will be removed after code reconstruction */ + MuxLibrary mux_lib = convert_mux_arch_to_library(spice->circuit_lib, muxes_head); /* Print the muxes netlist*/ fp = fopen(verilog_name, "w"); From 69039aa742bfec5080b9e01f2badbd29a9e9b68b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Aug 2019 20:13:18 -0600 Subject: [PATCH 086/482] developed subgraph extraction and start refactoring mux generation --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 130 +++++++++++++++++- vpr7_x2p/vpr/SRC/device/mux_graph.h | 8 +- vpr7_x2p/vpr/SRC/device/mux_library.cpp | 14 ++ vpr7_x2p/vpr/SRC/device/mux_library.h | 9 ++ vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 1 - .../verilog/verilog_submodule_mux.cpp | 72 ++++++++++ .../fpga_x2p/verilog/verilog_submodule_mux.h | 20 +++ .../SRC/fpga_x2p/verilog/verilog_submodules.c | 38 ++++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 11 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 4 + 10 files changed, 297 insertions(+), 10 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index eb978750c..30a4c9b51 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -3,6 +3,7 @@ * data structures in mux_graph.h *************************************************/ #include +#include #include #include "util.h" @@ -15,7 +16,7 @@ *************************************************/ /************************************************** - * Constructor + * Public Constructors *************************************************/ /* Create an object based on a Circuit Model which is MUX */ @@ -26,20 +27,28 @@ MuxGraph::MuxGraph(const CircuitLibrary& circuit_lib, build_mux_graph(circuit_lib, circuit_model, mux_size); } +/************************************************** + * Private Constructors + *************************************************/ +/* Create an empty graph */ +MuxGraph::MuxGraph() { + return; +} + /************************************************** * Public Accessors : Aggregates *************************************************/ //Accessors MuxGraph::node_range MuxGraph::nodes() const { - return vtr::make_range(node_ids_.begin(), node_ids_.end()); + return vtr::make_range(node_ids_.begin(), node_ids_.end()); } MuxGraph::edge_range MuxGraph::edges() const { - return vtr::make_range(edge_ids_.begin(), edge_ids_.end()); + return vtr::make_range(edge_ids_.begin(), edge_ids_.end()); } MuxGraph::mem_range MuxGraph::memories() const { - return vtr::make_range(mem_ids_.begin(), mem_ids_.end()); + return vtr::make_range(mem_ids_.begin(), mem_ids_.end()); } /************************************************** @@ -93,7 +102,7 @@ std::vector MuxGraph::branch_sizes() const { std::vector::iterator it; it = std::find(branch.begin(), branch.end(), branch_size); /* if already exists a branch with the same size, skip updating the vector */ - if (it == branch.end()) { + if (it != branch.end()) { continue; } branch.push_back(branch_size); @@ -105,6 +114,117 @@ std::vector MuxGraph::branch_sizes() const { return branch; } +/* Build a subgraph from the given node + * The strategy is very simple, we just + * extract a 1-level graph from here + */ +MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { + /* Validate the node */ + VTR_ASSERT_SAFE(this->valid_node_id(root_node)); + + /* Generate an empty graph */ + MuxGraph mux_graph; + + /* A map to record node-to-node mapping from origin graph to subgraph */ + std::map node2node_map; + + /* A map to record edge-to-edge mapping from origin graph to subgraph */ + std::map edge2edge_map; + + /* Add output nodes to subgraph */ + MuxNodeId to_node_subgraph = mux_graph.add_node(MUX_OUTPUT_NODE); + mux_graph.node_levels_[to_node_subgraph] = 0; + /* Update the node-to-node map */ + node2node_map[root_node] = to_node_subgraph; + + /* Add input nodes and edges to subgraph */ + size_t input_cnt = 0; + for (auto edge_origin : this->node_in_edges_[root_node]) { + VTR_ASSERT_SAFE(1 == edge_src_nodes_[edge_origin].size()); + /* Add nodes */ + MuxNodeId from_node_origin = this->edge_src_nodes_[edge_origin][0]; + MuxNodeId from_node_subgraph = mux_graph.add_node(MUX_INPUT_NODE); + /* Configure the nodes */ + mux_graph.node_levels_[from_node_subgraph] = 0; + mux_graph.node_input_ids_[from_node_subgraph] = MuxInputId(input_cnt); + input_cnt++; + /* Update the node-to-node map */ + node2node_map[from_node_origin] = from_node_subgraph; + + /* Add edges */ + MuxEdgeId edge_subgraph = mux_graph.add_edge(node2node_map[from_node_origin], node2node_map[root_node]); + edge2edge_map[edge_origin] = edge_subgraph; + /* Configure edges */ + mux_graph.edge_types_[edge_subgraph] = this->edge_types_[edge_origin]; + mux_graph.edge_inv_mem_[edge_subgraph] = this->edge_inv_mem_[edge_origin]; + } + + /* A map to record mem-to-mem mapping from origin graph to subgraph */ + std::map mem2mem_map; + + /* Add memory bits and configure edges */ + for (auto edge_origin : this->node_in_edges_[root_node]) { + MuxMemId mem_origin = this->edge_mem_ids_[edge_origin]; + /* Try to find if the mem is already in the list */ + std::map::iterator it = mem2mem_map.find(mem_origin); + if (it != mem2mem_map.end()) { + /* Found, we skip mem addition. But make sure we have a valid one */ + VTR_ASSERT_SAFE(MuxMemId::INVALID() != mem2mem_map[mem_origin]); + /* configure the edge */ + mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem2mem_map[mem_origin]; + continue; + } + /* Not found, we add a memory bit and record in the mem-to-mem map */ + MuxMemId mem_subgraph = mux_graph.add_mem(); + mem2mem_map[mem_origin] = mem_subgraph; + } + + return mux_graph; +} + +/* Generate MUX graphs for its branches + * Similar to the branch_sizes() method, + * we search all the internal nodes and + * find out what are the input sizes of + * the branches. + * Then we extract unique subgraphs and return + */ +std::vector MuxGraph::build_mux_branch_graphs() const { + std::map branch_done; /* A map showing the status of graph generation */ + + std::vector branch_graphs; + + /* Visit each internal nodes/output nodes and find the the number of incoming edges */ + for (auto node : node_ids_ ) { + /* Bypass input nodes */ + if ( (MUX_OUTPUT_NODE != node_types_[node]) + && (MUX_INTERNAL_NODE != node_types_[node]) ) { + continue; + } + + size_t branch_size = node_in_edges_[node].size(); + + /* make sure the branch size is valid */ + VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size)); + + /* check if the branch have been done in sub-graph extraction! */ + std::map::iterator it = branch_done.find(branch_size); + /* if it is done, we can skip */ + if (it != branch_done.end()) { + VTR_ASSERT(branch_done[branch_size]); + continue; + } + + /* Generate a subgraph and push back */ + branch_graphs.push_back(subgraph(node)); + + /* Mark it is done for this branch size */ + branch_done[branch_size] = true; + } + + return branch_graphs; +} + /* Get the node id of a given input */ MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { /* Use the node_lookup to accelerate the search */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index dad40aaf7..fc5dd1f98 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -48,11 +48,14 @@ class MuxGraph { typedef vtr::Range node_range; typedef vtr::Range edge_range; typedef vtr::Range mem_range; - public: /* Constructors */ + public: /* Public Constructors */ /* Create an object based on a Circuit Model which is MUX */ MuxGraph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); + private: /* Private Constructors*/ + /* Create an empty graph */ + MuxGraph(); public: /* Public accessors: Aggregates */ node_range nodes() const; edge_range edges() const; @@ -66,6 +69,9 @@ class MuxGraph { size_t num_memory_bits() const; /* Find the sizes of each branch of a MUX */ std::vector branch_sizes() const; + /* Generate MUX graphs for its branches */ + MuxGraph subgraph(const MuxNodeId& node) const; + std::vector build_mux_branch_graphs() const; /* Get the node id of a given input */ MuxNodeId node_id(const MuxInputId& input_id) const; /* Decode memory bits based on an input id */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.cpp b/vpr7_x2p/vpr/SRC/device/mux_library.cpp index 717d1aac7..04ef5c378 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_library.cpp @@ -11,6 +11,12 @@ * Member functions for the class MuxLibrary *************************************************/ +/************************************************** + * Public accessors: aggregates + *************************************************/ +MuxLibrary::mux_range MuxLibrary::muxes() const { + return vtr::make_range(mux_ids_.begin(), mux_ids_.end()); +} /************************************************** * Public accessors: data query @@ -31,6 +37,12 @@ const MuxGraph& MuxLibrary::mux_graph(const MuxId& mux_id) const { return mux_graphs_[mux_id]; } +/* Get a mux circuit model id */ +CircuitModelId MuxLibrary::mux_circuit_model(const MuxId& mux_id) const { + VTR_ASSERT_SAFE(valid_mux_id(mux_id)); + return mux_circuit_models_[mux_id]; +} + /************************************************** * Private mutators: *************************************************/ @@ -47,6 +59,8 @@ void MuxLibrary::add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId mux_ids_.push_back(mux); /* Add a mux graph */ mux_graphs_.push_back(MuxGraph(circuit_lib, circuit_model, mux_size)); + /* Recorde mux cirucit model id */ + mux_circuit_models_.push_back(circuit_model); /* update mux_lookup*/ mux_lookup_[circuit_model][mux_size] = mux; diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h index 3c3b0329a..7ffefba09 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.h +++ b/vpr7_x2p/vpr/SRC/device/mux_library.h @@ -15,10 +15,18 @@ #include "mux_library_fwd.h" class MuxLibrary { + public: /* Types and ranges */ + typedef vtr::vector::const_iterator mux_iterator; + + typedef vtr::Range mux_range; + public: /* Public accessors: Aggregates */ + mux_range muxes() const; public: /* Public accessors */ /* Get a MUX graph (read-only) */ MuxId mux_graph(const CircuitModelId& circuit_model, const size_t& mux_size) const; const MuxGraph& mux_graph(const MuxId& mux_id) const; + /* Get a mux circuit model id */ + CircuitModelId mux_circuit_model(const MuxId& mux_id) const; public: /* Public mutators */ /* Add a mux to the library */ void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); @@ -35,6 +43,7 @@ class MuxLibrary { /* MUX graph-based desription */ vtr::vector mux_ids_; /* Unique identifier for each mux graph */ vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ + vtr::vector mux_circuit_models_; /* circuit model id in circuit library */ /* Local encoder description */ //vtr::vector mux_local_encoders_; /* Graphs describing MUX internal structures */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index cc5b04ec8..29cb0e5ec 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -156,4 +156,3 @@ MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llis return mux_lib; } - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp new file mode 100644 index 000000000..e5fe1cc66 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp @@ -0,0 +1,72 @@ +/*********************************************** + * This file includes functions to generate + * Verilog submodules for multiplexers. + * including both fundamental submodules + * such as a branch in a multiplexer + * and the full multiplexer + **********************************************/ + +#include "util.h" +#include "vtr_assert.h" + +#include "verilog_submodule_mux.h" + + +/*********************************************** + * Generate Verilog codes modeling an branch circuit + * for a multiplexer with the given size + **********************************************/ +static +void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + return; +} + +/*********************************************** + * Generate Verilog codes modeling an branch circuit + * for a multiplexer with the given size + **********************************************/ +void generate_verilog_mux_branch_module(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + /* Multiplexers built with different technology is in different organization */ + switch (circuit_lib.design_tech_type(circuit_model)) { + case SPICE_MODEL_DESIGN_CMOS: + if (true == circuit_lib.dump_structural_verilog(circuit_model)) { + generate_verilog_cmos_mux_branch_module_structural(fp, circuit_lib, circuit_model, mux_graph); + } else { + /* + dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name, + mux_size, + num_input_basis_subckt, + cur_spice_model, + special_basis); + */ + } + break; + case SPICE_MODEL_DESIGN_RRAM: + /* If requested, we can dump structural verilog for basis module */ + /* + if (true == circuit_lib.dump_structural_verilog(circuit_model)) { + dump_verilog_rram_mux_one_basis_module_structural(fp, mux_basis_subckt_name, + num_input_basis_subckt, + cur_spice_model); + } else { + dump_verilog_rram_mux_one_basis_module(fp, mux_basis_subckt_name, + num_input_basis_subckt, + cur_spice_model); + } + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", + __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); + exit(1); + } + + return; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h new file mode 100644 index 000000000..6e7e84b30 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h @@ -0,0 +1,20 @@ +/*********************************************** + * Header file for verilog_submodule_mux.cpp + **********************************************/ + +#ifndef VERILOG_SUBMODULE_MUX_H +#define VERILOG_SUBMODULE_MUX_H + +/* Include other header files which are dependency on the function declared below */ +#include + +#include "circuit_library.h" +#include "mux_graph.h" +#include "mux_library.h" + +void generate_verilog_mux_branch_module(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index d9183c91e..c1f2944f9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -39,6 +39,7 @@ #include "verilog_submodules.h" #include "mux_utils.h" +#include "verilog_submodule_mux.h" /***** Subroutines *****/ @@ -2765,9 +2766,6 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Alloc the muxes*/ muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); - /* TODO: this is temporary. Will be removed after code reconstruction */ - MuxLibrary mux_lib = convert_mux_arch_to_library(spice->circuit_lib, muxes_head); - /* Print the muxes netlist*/ fp = fopen(verilog_name, "w"); if (NULL == fp) { @@ -2831,6 +2829,40 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, temp = temp->next; } + /* Generate modules into a .bak file now. Rename after it is verified */ + std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name)); + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream sfp; + sfp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for Multiplexers (%s) ...\n", + verilog_fname.c_str()); + check_file_handler(sfp); + + /* TODO: this conversion is temporary. Will be removed after code reconstruction */ + MuxLibrary mux_lib = convert_mux_arch_to_library(spice->circuit_lib, muxes_head); + + /* Generate basis sub-circuit for unique branches shared by the multiplexers */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* Create a mux graph for the branch circuit */ + std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); + /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ + for (auto branch_mux_graph : branch_mux_graphs) { + generate_verilog_mux_branch_module(sfp, spice->circuit_lib, mux_circuit_model, branch_mux_graph); + } + } + + /* Dump MUX graph one by one */ + + /* Close the file steam */ + sfp.close(); + /* TODO: * Scan-chain configuration circuit does not need any BLs/WLs! * SRAM MUX does not need any reserved BL/WLs! diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 947bee272..dc62b3797 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -144,6 +144,17 @@ void dump_include_user_defined_verilog_netlists(FILE* fp, return; } +void check_file_handler(const std::fstream& fp) { + /* Make sure we have a valid file handler*/ + /* Print out debugging information for if the file is not opened/created properly */ + if (!fp.is_open() || !fp.good()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create file!\n", + __FILE__, __LINE__); + exit(1); + } +} + void dump_verilog_file_header(FILE* fp, char* usage) { if (NULL == fp) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 0a10d29a8..06aaba142 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -1,6 +1,8 @@ #ifndef VERILOG_UTILS_H #define VERILOG_UTILS_H +#include + void init_list_include_verilog_netlists(t_spice* spice); void init_include_user_defined_verilog_netlists(t_spice spice); @@ -8,6 +10,8 @@ void init_include_user_defined_verilog_netlists(t_spice spice); void dump_include_user_defined_verilog_netlists(FILE* fp, t_spice spice); +void check_file_handler(const std::fstream& fp); + void dump_verilog_file_header(FILE* fp, char* usage); From a7ac1e498081f09e574097e6edba35a0305b3d4d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Aug 2019 20:43:35 -0600 Subject: [PATCH 087/482] remame methods in circuit_library --- .../libarchfpga/SRC/check_circuit_library.cpp | 48 +- .../libarchfpga/SRC/check_circuit_library.h | 4 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 1432 ++++++++--------- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 378 +++-- .../libarchfpga/SRC/circuit_library_fwd.h | 21 + vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 44 +- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 6 +- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 8 +- .../fpga_x2p/base/link_arch_circuit_lib.cpp | 46 +- .../verilog/verilog_submodule_mux.cpp | 2 +- 10 files changed, 998 insertions(+), 991 deletions(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 0b0f8fa69..2f51fa9bb 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -58,16 +58,16 @@ static size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { size_t num_err = 0; - for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { + for (size_t i = 0; i < circuit_lib.num_models(); ++i) { /* Skip for the last element, because the inner loop will access it */ - if (i == circuit_lib.num_circuit_models() - 1) { + if (i == circuit_lib.num_models() - 1) { continue; } /* Get the name of reference */ - const std::string& i_name = circuit_lib.circuit_model_name(CircuitModelId(i)); - for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { + const std::string& i_name = circuit_lib.model_name(CircuitModelId(i)); + for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) { /* Compare the name of candidate */ - const std::string& j_name = circuit_lib.circuit_model_name(CircuitModelId(j)); + const std::string& j_name = circuit_lib.model_name(CircuitModelId(j)); /* Compare the name and skip for different names */ if (0 != i_name.compare(j_name)) { continue; @@ -92,24 +92,24 @@ static size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { size_t num_err = 0; - for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { + for (size_t i = 0; i < circuit_lib.num_models(); ++i) { /* Skip for the last element, because the inner loop will access it */ - if (i == circuit_lib.num_circuit_models() - 1) { + if (i == circuit_lib.num_models() - 1) { continue; } /* Get the name of reference */ - const std::string& i_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(i)); - for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { + const std::string& i_prefix = circuit_lib.model_prefix(CircuitModelId(i)); + for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) { /* Compare the name of candidate */ - const std::string& j_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(j)); + const std::string& j_prefix = circuit_lib.model_prefix(CircuitModelId(j)); /* Compare the name and skip for different prefix */ if (0 != i_prefix.compare(j_prefix)) { continue; } vpr_printf(TIO_MESSAGE_ERROR, "Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n", - circuit_lib.circuit_model_name(CircuitModelId(i)).c_str(), - circuit_lib.circuit_model_name(CircuitModelId(j)).c_str(), + circuit_lib.model_name(CircuitModelId(i)).c_str(), + circuit_lib.model_name(CircuitModelId(j)).c_str(), i_prefix.c_str()); /* Incremental the counter for errors */ num_err++; @@ -129,7 +129,7 @@ size_t check_circuit_model_required(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* We must have an IOPAD*/ - if ( 0 == circuit_lib.circuit_models_by_type(circuit_model_type_to_check).size()) { + if ( 0 == circuit_lib.models_by_type(circuit_model_type_to_check).size()) { vpr_printf(TIO_MESSAGE_ERROR, "At least one %s circuit model is required!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]); @@ -153,8 +153,8 @@ size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, if (0 == circuit_lib.ports_by_type(circuit_model, port_type).size()) { vpr_printf(TIO_MESSAGE_ERROR, "%s circuit model(name=%s) does not have %s port\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], - circuit_lib.circuit_model_name(circuit_model).c_str(), + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], + circuit_lib.model_name(circuit_model).c_str(), CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); /* Incremental the counter for errors */ num_err++; @@ -178,7 +178,7 @@ size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_ if (port_size_to_check != circuit_lib.port_size(circuit_model, circuit_port)) { vpr_printf(TIO_MESSAGE_ERROR, "Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n", - circuit_lib.circuit_model_name(circuit_model).c_str(), + circuit_lib.model_name(circuit_model).c_str(), CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_model, circuit_port))], port_size_to_check); /* Incremental the counter for errors */ @@ -208,7 +208,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", num_ports_to_check, CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], ports.size()); num_err++; @@ -232,7 +232,7 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, const std::vector& port_types_to_check) { size_t num_err = 0; - for (const auto& id : circuit_lib.circuit_models_by_type(circuit_model_type_to_check)) { + for (const auto& id : circuit_lib.models_by_type(circuit_model_type_to_check)) { num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check); } @@ -248,7 +248,7 @@ size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib, const enum e_spice_model_type& circuit_model_type) { size_t num_err = 0; - if (CIRCUIT_MODEL_OPEN_ID == circuit_lib.default_circuit_model(circuit_model_type)) { + if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) { vpr_printf(TIO_MESSAGE_ERROR, "A default circuit model for the type %s! Try to define it in your architecture file!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]); @@ -266,7 +266,7 @@ size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.model_type(circuit_model)); /* Check if we have D, Set and Reset */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, SPICE_MODEL_PORT_INPUT, @@ -293,7 +293,7 @@ size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.model_type(circuit_model)); /* Check if we have D, Set and Reset */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, @@ -322,7 +322,7 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.model_type(circuit_model)); /* Check if we has 1 output with size 2 */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, @@ -403,8 +403,8 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required); /* 5. We must have at least one SRAM or SCFF */ - if ( ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SRAM).size()) - && ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SCFF).size()) ) { + if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size()) + && ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SCFF).size()) ) { vpr_printf(TIO_MESSAGE_ERROR, "At least one %s or %s circuit model is required!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)], diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h index f70133697..2d0bd3f03 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h @@ -47,7 +47,9 @@ */ /* Header files should be included in a sequence */ /* Standard header files required go first */ -#include "circuit_library.h" +#include +#include "spice_types.h" +#include "circuit_library_fwd.h" /* Check points to make sure we have a valid circuit library */ size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 9689c8132..e39d81793 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -55,20 +55,20 @@ CircuitLibrary::CircuitLibrary() { /************************************************************************ * Public Accessors : aggregates ***********************************************************************/ -CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { - return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); +CircuitLibrary::model_range CircuitLibrary::models() const { + return vtr::make_range(model_ids_.begin(), model_ids_.end()); } -CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& circuit_model_id) const { - return vtr::make_range(port_ids_[circuit_model_id].begin(), port_ids_[circuit_model_id].end()); +CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& model_id) const { + return vtr::make_range(port_ids_[model_id].begin(), port_ids_[model_id].end()); } /* Find circuit models in the same type (defined by users) and return a list of ids */ -std::vector CircuitLibrary::circuit_models_by_type(const enum e_spice_model_type& type) const { +std::vector CircuitLibrary::models_by_type(const enum e_spice_model_type& type) const { std::vector type_ids; - for (auto id : circuit_models()) { + for (auto id : models()) { /* Skip unmatched types */ - if (type != circuit_model_type(id)) { + if (type != model_type(id)) { continue; } /* Matched type, update the vector */ @@ -78,12 +78,12 @@ std::vector CircuitLibrary::circuit_models_by_type(const enum e_ } /* Find the ports of a circuit model by a given type, return a list of qualified ports */ -std::vector CircuitLibrary::ports_by_type(const CircuitModelId& circuit_model_id, +std::vector CircuitLibrary::ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type) const { std::vector port_ids; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip unmatched ports */ - if ( type != port_type(circuit_model_id, port_id) ) { + if ( type != port_type(model_id, port_id) ) { continue; } port_ids.push_back(port_id); @@ -94,18 +94,18 @@ std::vector CircuitLibrary::ports_by_type(const CircuitModelId& c /* Find the ports of a circuit model by a given type, return a list of qualified ports * with an option to include/exclude global ports */ -std::vector CircuitLibrary::ports_by_type(const CircuitModelId& circuit_model_id, +std::vector CircuitLibrary::ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, const bool& include_global_port) const { std::vector port_ids; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip unmatched ports */ - if ( type != port_type(circuit_model_id, port_id) ) { + if ( type != port_type(model_id, port_id) ) { continue; } /* We skip global ports if specified */ if ( (false == include_global_port) - && (true == port_is_global(circuit_model_id, port_id)) ) { + && (true == port_is_global(model_id, port_id)) ) { continue; } port_ids.push_back(port_id); @@ -117,11 +117,11 @@ std::vector CircuitLibrary::ports_by_type(const CircuitModelId& c /* Create a vector for all the ports whose directionality is input * This includes all the ports other than whose types are OUPUT or INOUT */ -std::vector CircuitLibrary::input_ports(const CircuitModelId& circuit_model_id) const { +std::vector CircuitLibrary::input_ports(const CircuitModelId& model_id) const { std::vector input_ports; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip output ports */ - if ( false == is_input_port(circuit_model_id, port_id) ) { + if ( false == is_input_port(model_id, port_id) ) { continue; } input_ports.push_back(port_id); @@ -132,11 +132,11 @@ std::vector CircuitLibrary::input_ports(const CircuitModelId& cir /* Create a vector for all the ports whose directionality is output * This includes all the ports whose types are OUPUT or INOUT */ -std::vector CircuitLibrary::output_ports(const CircuitModelId& circuit_model_id) const { +std::vector CircuitLibrary::output_ports(const CircuitModelId& model_id) const { std::vector output_ports; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip input ports */ - if ( false == is_output_port(circuit_model_id, port_id) ) { + if ( false == is_output_port(model_id, port_id) ) { continue; } output_ports.push_back(port_id); @@ -147,8 +147,8 @@ std::vector CircuitLibrary::output_ports(const CircuitModelId& ci /* Create a vector for the pin indices, which is bounded by the size of a port * Start from 0 and end to port_size - 1 */ -std::vector CircuitLibrary::pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - std::vector pin_range(port_size(circuit_model_id, circuit_port_id)); +std::vector CircuitLibrary::pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + std::vector pin_range(port_size(model_id, circuit_port_id)); /* Create a vector, with sequentially increasing numbers */ std::iota(pin_range.begin(), pin_range.end(), 0); return pin_range; @@ -159,101 +159,101 @@ std::vector CircuitLibrary::pins(const CircuitModelId& circuit_model_id, * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ /* Get the number of circuit models */ -size_t CircuitLibrary::num_circuit_models() const { - return circuit_model_ids_.size(); +size_t CircuitLibrary::num_models() const { + return model_ids_.size(); } /* Access the type of a circuit model */ -enum e_spice_model_type CircuitLibrary::circuit_model_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_types_[circuit_model_id]; +enum e_spice_model_type CircuitLibrary::model_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_types_[model_id]; } /* Access the name of a circuit model */ -std::string CircuitLibrary::circuit_model_name(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_names_[circuit_model_id]; +std::string CircuitLibrary::model_name(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_names_[model_id]; } /* Access the prefix of a circuit model */ -std::string CircuitLibrary::circuit_model_prefix(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_prefix_[circuit_model_id]; +std::string CircuitLibrary::model_prefix(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_prefix_[model_id]; } /* Access the path + file of user-defined verilog netlist of a circuit model */ -std::string CircuitLibrary::circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_verilog_netlists_[circuit_model_id]; +std::string CircuitLibrary::model_verilog_netlist(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_verilog_netlists_[model_id]; } /* Access the path + file of user-defined spice netlist of a circuit model */ -std::string CircuitLibrary::circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_spice_netlists_[circuit_model_id]; +std::string CircuitLibrary::model_spice_netlist(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_spice_netlists_[model_id]; } /* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */ -bool CircuitLibrary::circuit_model_is_default(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_is_default_[circuit_model_id]; +bool CircuitLibrary::model_is_default(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_is_default_[model_id]; } /* Access the dump_structural_verilog flag of a circuit model */ -bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return dump_structural_verilog_[circuit_model_id]; +bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return dump_structural_verilog_[model_id]; } /* Access the dump_explicit_port_map flag of a circuit model */ -bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return dump_explicit_port_map_[circuit_model_id]; +bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return dump_explicit_port_map_[model_id]; } /* Access the design technology type of a circuit model */ -enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return design_tech_types_[circuit_model_id]; +enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return design_tech_types_[model_id]; } /* Access the is_power_gated flag of a circuit model */ -bool CircuitLibrary::is_power_gated(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return is_power_gated_[circuit_model_id]; +bool CircuitLibrary::is_power_gated(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return is_power_gated_[model_id]; } /* Return a flag showing if inputs are buffered for a circuit model */ -bool CircuitLibrary::is_input_buffered(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return buffer_existence_[circuit_model_id][INPUT]; +bool CircuitLibrary::is_input_buffered(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return buffer_existence_[model_id][INPUT]; } /* Return a flag showing if outputs are buffered for a circuit model */ -bool CircuitLibrary::is_output_buffered(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return buffer_existence_[circuit_model_id][OUTPUT]; +bool CircuitLibrary::is_output_buffered(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return buffer_existence_[model_id][OUTPUT]; } /* Return a flag showing if intermediate stages of a LUT are buffered for a circuit model */ -bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - return buffer_existence_[circuit_model_id][LUT_INTER_BUFFER]; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + return buffer_existence_[model_id][LUT_INTER_BUFFER]; } /* Find the type of pass-gate logic for a circuit model (recursive function) @@ -261,68 +261,68 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ * 1. this is a pass-gate circuit model, just find the data and return * 2. this circuit model includes a pass-gate, find the link to pass-gate circuit model and go recursively */ -enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Return the data if this is a pass-gate circuit model */ - if (SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)) { - return pass_gate_logic_types_[circuit_model_id]; + if (SPICE_MODEL_PASSGATE == model_type(model_id)) { + return pass_gate_logic_types_[model_id]; } /* Otherwise, we need to make sure this circuit model contains a pass-gate */ - CircuitModelId pgl_model_id = pass_gate_logic_circuit_model_ids_[circuit_model_id]; + CircuitModelId pgl_model_id = pass_gate_logic_model_ids_[model_id]; VTR_ASSERT( CircuitModelId::INVALID() != pgl_model_id ); return pass_gate_logic_type(pgl_model_id); } /* Return the multiplex structure of a circuit model */ -enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - return mux_structure_[circuit_model_id]; + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + return mux_structure_[model_id]; } -size_t CircuitLibrary::mux_num_levels(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +size_t CircuitLibrary::mux_num_levels(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); - return mux_num_levels_[circuit_model_id]; + return mux_num_levels_[model_id]; } /* Return if additional constant inputs are required for a circuit model * Only applicable for MUX circuit model */ -bool CircuitLibrary::mux_add_const_input(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +bool CircuitLibrary::mux_add_const_input(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); /* A -1 value for the const values means there is no const inputs */ - return ( size_t(-1) != mux_const_input_values_[circuit_model_id] ); + return ( size_t(-1) != mux_const_input_values_[model_id] ); } /* Return if additional constant inputs are required for a circuit model * Only applicable for MUX circuit model */ -size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); /* A -1 value for the const values means there is no const inputs */ /* A 0 value for the const values means it is logic 0 */ /* A 1 value for the const values means it is logic 1 */ - return mux_const_input_values_[circuit_model_id]; + return mux_const_input_values_[model_id]; } /************************************************************************ @@ -330,32 +330,32 @@ size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& circuit_model ***********************************************************************/ /* identify if this port is an input port */ -bool CircuitLibrary::is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - /* validate the circuit_model_id and circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); +bool CircuitLibrary::is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + /* validate the model_id and circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, circuit_port_id)) - && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, circuit_port_id)) ); + return ( (SPICE_MODEL_PORT_OUTPUT != port_type(model_id, circuit_port_id)) + && (SPICE_MODEL_PORT_INOUT != port_type(model_id, circuit_port_id)) ); } /* identify if this port is an output port */ -bool CircuitLibrary::is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - /* validate the circuit_model_id and circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); +bool CircuitLibrary::is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + /* validate the model_id and circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, circuit_port_id)) - || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, circuit_port_id)) ); + return ( (SPICE_MODEL_PORT_OUTPUT == port_type(model_id, circuit_port_id)) + || (SPICE_MODEL_PORT_INOUT == port_type(model_id, circuit_port_id)) ); } /* Given a name and return the port id */ -CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const std::string& name) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +CircuitPortId CircuitLibrary::port(const CircuitModelId& model_id, const std::string& name) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Walk through the ports and try to find a matched name */ - CircuitPortId ret = CIRCUIT_PORT_OPEN_ID; + CircuitPortId ret = CircuitPortId::INVALID(); size_t num_found = 0; - for (auto port_id : ports(circuit_model_id)) { - if (0 != name.compare(port_prefix(circuit_model_id, port_id))) { + for (auto port_id : ports(model_id)) { + if (0 != name.compare(port_prefix(model_id, port_id))) { continue; /* Not the one, go to the next*/ } ret = port_id; /* Find one */ @@ -367,119 +367,119 @@ CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const } /* Access the type of a port of a circuit model */ -size_t CircuitLibrary::num_ports(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return port_ids_[circuit_model_id].size(); +size_t CircuitLibrary::num_ports(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return port_ids_[model_id].size(); } /* Access the type of a port of a circuit model * with an option to include/exclude global ports * when counting */ -size_t CircuitLibrary::num_ports_by_type(const CircuitModelId& circuit_model_id, +size_t CircuitLibrary::num_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ports_by_type(circuit_model_id, port_type, include_global_port).size(); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ports_by_type(model_id, port_type, include_global_port).size(); } /* Access the type of a port of a circuit model */ -enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& circuit_model_id, +enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_types_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_types_[model_id][circuit_port_id]; } /* Access the type of a port of a circuit model */ -size_t CircuitLibrary::port_size(const CircuitModelId& circuit_model_id, +size_t CircuitLibrary::port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_sizes_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_sizes_[model_id][circuit_port_id]; } /* Access the prefix of a port of a circuit model */ -std::string CircuitLibrary::port_prefix(const CircuitModelId& circuit_model_id, +std::string CircuitLibrary::port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_prefix_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_prefix_[model_id][circuit_port_id]; } /* Access the lib_name of a port of a circuit model */ -std::string CircuitLibrary::port_lib_name(const CircuitModelId& circuit_model_id, +std::string CircuitLibrary::port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_lib_names_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_lib_names_[model_id][circuit_port_id]; } /* Access the inv_prefix of a port of a circuit model */ -std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_id, +std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_inv_prefix_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_inv_prefix_[model_id][circuit_port_id]; } /* Return the default value of a port of a circuit model */ -size_t CircuitLibrary::port_default_value(const CircuitModelId& circuit_model_id, +size_t CircuitLibrary::port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_default_values_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_default_values_[model_id][circuit_port_id]; } /* Return a flag if the port is used in mode-selection purpuse of a circuit model */ -bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_mode_select_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_mode_select_[model_id][circuit_port_id]; } /* Return a flag if the port is a global one of a circuit model */ -bool CircuitLibrary::port_is_global(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_global_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_global_[model_id][circuit_port_id]; } /* Return a flag if the port does a reset functionality in a circuit model */ -bool CircuitLibrary::port_is_reset(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_reset_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_reset_[model_id][circuit_port_id]; } /* Return a flag if the port does a set functionality in a circuit model */ -bool CircuitLibrary::port_is_set(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_set_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_set_[model_id][circuit_port_id]; } /* Return a flag if the port enables a configuration in a circuit model */ -bool CircuitLibrary::port_is_config_enable(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_config_enable_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_config_enable_[model_id][circuit_port_id]; } /* Return a flag if the port is used during programming a FPGA in a circuit model */ -bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_prog_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_prog_[model_id][circuit_port_id]; } @@ -487,17 +487,17 @@ bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, * Public Accessors : Methods to find circuit model ***********************************************************************/ /* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::circuit_model(const char* name) const { +CircuitModelId CircuitLibrary::model(const char* name) const { std::string name_str(name); - return circuit_model(name_str); + return model(name_str); } /* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { - CircuitModelId ret = CIRCUIT_MODEL_OPEN_ID; +CircuitModelId CircuitLibrary::model(const std::string& name) const { + CircuitModelId ret = CircuitModelId::INVALID(); size_t num_found = 0; - for (circuit_model_string_iterator it = circuit_model_names_.begin(); - it != circuit_model_names_.end(); + for (model_string_iterator it = model_names_.begin(); + it != model_names_.end(); it++) { /* Bypass unmatched names */ if ( 0 != name.compare(*it) ) { @@ -506,7 +506,7 @@ CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { /* Find one and record it * FIXME: I feel that we may have a better way in getting the CircuitModelId */ - ret = CircuitModelId(it - circuit_model_names_.begin()); + ret = CircuitModelId(it - model_names_.begin()); num_found++; } VTR_ASSERT((0 == num_found) || (1 == num_found)); @@ -514,10 +514,10 @@ CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { } /* Get the CircuitModelId of a default circuit model with a given type */ -CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_type& type) const { +CircuitModelId CircuitLibrary::default_model(const enum e_spice_model_type& type) const { /* Default circuit model id is the first element by type in the fast look-up */ - CircuitModelId default_id = circuit_model_lookup_[size_t(type)].front(); - VTR_ASSERT(true == circuit_model_is_default(default_id)); + CircuitModelId default_id = model_lookup_[size_t(type)].front(); + VTR_ASSERT(true == model_is_default(default_id)); return default_id; } @@ -525,43 +525,43 @@ CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_ty * Public Accessors: Timing graph ***********************************************************************/ /* Given the source and sink port information, find the edge connecting the two ports */ -CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& circuit_model_id, +CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin) { /* validate the circuit_pin_id */ - VTR_ASSERT(valid_circuit_pin_id(circuit_model_id, from_port, from_pin)); - VTR_ASSERT(valid_circuit_pin_id(circuit_model_id, to_port, to_pin)); + VTR_ASSERT(valid_circuit_pin_id(model_id, from_port, from_pin)); + VTR_ASSERT(valid_circuit_pin_id(model_id, to_port, to_pin)); /* Walk through the edge list until we find the one */ - for (auto edge : edge_ids_[circuit_model_id]) { - if ( (from_port == edge_src_port_ids_[circuit_model_id][edge]) - && (from_pin == edge_src_pin_ids_[circuit_model_id][edge]) - && (to_port == edge_sink_port_ids_[circuit_model_id][edge]) - && (to_pin == edge_sink_pin_ids_[circuit_model_id][edge]) ) { + for (auto edge : edge_ids_[model_id]) { + if ( (from_port == edge_src_port_ids_[model_id][edge]) + && (from_pin == edge_src_pin_ids_[model_id][edge]) + && (to_port == edge_sink_port_ids_[model_id][edge]) + && (to_pin == edge_sink_pin_ids_[model_id][edge]) ) { return edge; } } /* Reach here it means we find nothing! */ - return CIRCUIT_EDGE_OPEN_ID; + return CircuitEdgeId::INVALID(); } /************************************************************************ * Public Mutators ***********************************************************************/ /* Add a circuit model to the library, and return it Id */ -CircuitModelId CircuitLibrary::add_circuit_model() { +CircuitModelId CircuitLibrary::add_model() { /* Create a new id*/ - CircuitModelId circuit_model_id = CircuitModelId(circuit_model_ids_.size()); + CircuitModelId model_id = CircuitModelId(model_ids_.size()); /* Update the id list */ - circuit_model_ids_.push_back(circuit_model_id); + model_ids_.push_back(model_id); /* Initialize other attributes */ /* Fundamental information */ - circuit_model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES); - circuit_model_names_.emplace_back(); - circuit_model_prefix_.emplace_back(); - circuit_model_verilog_netlists_.emplace_back(); - circuit_model_spice_netlists_.emplace_back(); - circuit_model_is_default_.push_back(false); + model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES); + model_names_.emplace_back(); + model_prefix_.emplace_back(); + model_verilog_netlists_.emplace_back(); + model_spice_netlists_.emplace_back(); + model_is_default_.push_back(false); /* Verilog generator options */ dump_structural_verilog_.push_back(false); @@ -573,13 +573,13 @@ CircuitModelId CircuitLibrary::add_circuit_model() { /* Buffer existence */ buffer_existence_.emplace_back(); - buffer_circuit_model_names_.emplace_back(); - buffer_circuit_model_ids_.emplace_back(); + buffer_model_names_.emplace_back(); + buffer_model_ids_.emplace_back(); buffer_location_maps_.emplace_back(); /* Pass-gate-related parameters */ - pass_gate_logic_circuit_model_names_.emplace_back(); - pass_gate_logic_circuit_model_ids_.emplace_back(); + pass_gate_logic_model_names_.emplace_back(); + pass_gate_logic_model_ids_.emplace_back(); /* Port information */ port_ids_.emplace_back(); @@ -595,10 +595,10 @@ CircuitModelId CircuitLibrary::add_circuit_model() { port_is_set_.emplace_back(); port_is_config_enable_.emplace_back(); port_is_prog_.emplace_back(); - port_circuit_model_names_.emplace_back(); - port_circuit_model_ids_.emplace_back(); - port_inv_circuit_model_names_.emplace_back(); - port_inv_circuit_model_ids_.emplace_back(); + port_model_names_.emplace_back(); + port_model_ids_.emplace_back(); + port_inv_model_names_.emplace_back(); + port_inv_model_ids_.emplace_back(); port_tri_state_maps_.emplace_back(); port_lut_frac_level_.emplace_back(); port_lut_output_masks_.emplace_back(); @@ -654,409 +654,409 @@ CircuitModelId CircuitLibrary::add_circuit_model() { wire_num_levels_.push_back(-1); /* Update circuit port fast look-up */ - circuit_model_port_lookup_.emplace_back(); + model_port_lookup_.emplace_back(); /* Invalidate fast look-up*/ - invalidate_circuit_model_lookup(); + invalidate_model_lookup(); - return circuit_model_id; + return model_id; } /* Set the type of a Circuit Model */ -void CircuitLibrary::set_circuit_model_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_model_type(const CircuitModelId& model_id, const enum e_spice_model_type& type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_types_[circuit_model_id] = type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_types_[model_id] = type; /* Build the fast look-up for circuit models */ - build_circuit_model_lookup(); + build_model_lookup(); return; } /* Set the name of a Circuit Model */ -void CircuitLibrary::set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_names_[circuit_model_id] = name; +void CircuitLibrary::set_model_name(const CircuitModelId& model_id, const std::string& name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_names_[model_id] = name; return; } /* Set the prefix of a Circuit Model */ -void CircuitLibrary::set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_prefix_[circuit_model_id] = prefix; +void CircuitLibrary::set_model_prefix(const CircuitModelId& model_id, const std::string& prefix) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_prefix_[model_id] = prefix; return; } /* Set the verilog_netlist of a Circuit Model */ -void CircuitLibrary::set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_verilog_netlists_[circuit_model_id] = verilog_netlist; +void CircuitLibrary::set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_verilog_netlists_[model_id] = verilog_netlist; return; } /* Set the spice_netlist of a Circuit Model */ -void CircuitLibrary::set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_spice_netlists_[circuit_model_id] = spice_netlist; +void CircuitLibrary::set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_spice_netlists_[model_id] = spice_netlist; return; } /* Set the is_default of a Circuit Model */ -void CircuitLibrary::set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_is_default_[circuit_model_id] = is_default; +void CircuitLibrary::set_model_is_default(const CircuitModelId& model_id, const bool& is_default) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_is_default_[model_id] = is_default; return; } /* Set the dump_structural_verilog of a Circuit Model */ -void CircuitLibrary::set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - dump_structural_verilog_[circuit_model_id] = dump_structural_verilog; +void CircuitLibrary::set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + dump_structural_verilog_[model_id] = dump_structural_verilog; return; } /* Set the dump_explicit_port_map of a Circuit Model */ -void CircuitLibrary::set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - dump_explicit_port_map_[circuit_model_id] = dump_explicit_port_map; +void CircuitLibrary::set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + dump_explicit_port_map_[model_id] = dump_explicit_port_map; return; } /* Set the type of design technology of a Circuit Model */ -void CircuitLibrary::set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - design_tech_types_[circuit_model_id] = design_tech_type; +void CircuitLibrary::set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + design_tech_types_[model_id] = design_tech_type; return; } /* Set the power-gated flag of a Circuit Model */ -void CircuitLibrary::set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - is_power_gated_[circuit_model_id] = is_power_gated; +void CircuitLibrary::set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + is_power_gated_[model_id] = is_power_gated; return; } /* Set input buffer information for the circuit model */ -void CircuitLibrary::set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { +void CircuitLibrary::set_model_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, INPUT, existence, circuit_model_name); + set_model_buffer(model_id, INPUT, existence, model_name); return; } /* Set output buffer information for the circuit model */ -void CircuitLibrary::set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { +void CircuitLibrary::set_model_output_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, OUTPUT, existence, circuit_model_name); + set_model_buffer(model_id, OUTPUT, existence, model_name); return; } /* Set input buffer information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_lut_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, LUT_INPUT_BUFFER, existence, circuit_model_name); + set_model_buffer(model_id, LUT_INPUT_BUFFER, existence, model_name); return; } /* Set input inverter information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_lut_input_inverter(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, LUT_INPUT_INVERTER, existence, circuit_model_name); + set_model_buffer(model_id, LUT_INPUT_INVERTER, existence, model_name); return; } /* Set intermediate buffer information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_lut_intermediate_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, LUT_INTER_BUFFER, existence, circuit_model_name); + set_model_buffer(model_id, LUT_INTER_BUFFER, existence, model_name); return; } -void CircuitLibrary::set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, const std::string& location_map) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - buffer_location_maps_[circuit_model_id][LUT_INTER_BUFFER] = location_map; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + buffer_location_maps_[model_id][LUT_INTER_BUFFER] = location_map; return; } /* Set pass-gate logic information of a circuit model */ -void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - pass_gate_logic_circuit_model_names_[circuit_model_id] = circuit_model_name; +void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + pass_gate_logic_model_names_[model_id] = model_name; return; } /* Add a port to a circuit model */ -CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Create a port id */ - CircuitPortId circuit_port_id = CircuitPortId(port_ids_[circuit_model_id].size()); + CircuitPortId circuit_port_id = CircuitPortId(port_ids_[model_id].size()); /* Update the id list */ - port_ids_[circuit_model_id].push_back(circuit_port_id); + port_ids_[model_id].push_back(circuit_port_id); /* Initialize other attributes */ - port_types_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); - port_sizes_[circuit_model_id].push_back(-1); - port_prefix_[circuit_model_id].emplace_back(); - port_lib_names_[circuit_model_id].emplace_back(); - port_inv_prefix_[circuit_model_id].emplace_back(); - port_default_values_[circuit_model_id].push_back(-1); - port_is_mode_select_[circuit_model_id].push_back(false); - port_is_global_[circuit_model_id].push_back(false); - port_is_reset_[circuit_model_id].push_back(false); - port_is_set_[circuit_model_id].push_back(false); - port_is_config_enable_[circuit_model_id].push_back(false); - port_is_prog_[circuit_model_id].push_back(false); - port_circuit_model_names_[circuit_model_id].emplace_back(); - port_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); - port_inv_circuit_model_names_[circuit_model_id].emplace_back(); - port_inv_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); - port_tri_state_maps_[circuit_model_id].emplace_back(); - port_lut_frac_level_[circuit_model_id].push_back(-1); - port_lut_output_masks_[circuit_model_id].emplace_back(); - port_sram_orgz_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); + port_types_[model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); + port_sizes_[model_id].push_back(-1); + port_prefix_[model_id].emplace_back(); + port_lib_names_[model_id].emplace_back(); + port_inv_prefix_[model_id].emplace_back(); + port_default_values_[model_id].push_back(-1); + port_is_mode_select_[model_id].push_back(false); + port_is_global_[model_id].push_back(false); + port_is_reset_[model_id].push_back(false); + port_is_set_[model_id].push_back(false); + port_is_config_enable_[model_id].push_back(false); + port_is_prog_[model_id].push_back(false); + port_model_names_[model_id].emplace_back(); + port_model_ids_[model_id].push_back(CircuitModelId::INVALID()); + port_inv_model_names_[model_id].emplace_back(); + port_inv_model_ids_[model_id].push_back(CircuitModelId::INVALID()); + port_tri_state_maps_[model_id].emplace_back(); + port_lut_frac_level_[model_id].push_back(-1); + port_lut_output_masks_[model_id].emplace_back(); + port_sram_orgz_[model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); /* For timing graphs */ - port_in_edge_ids_[circuit_model_id].emplace_back(); - port_out_edge_ids_[circuit_model_id].emplace_back(); + port_in_edge_ids_[model_id].emplace_back(); + port_out_edge_ids_[model_id].emplace_back(); return circuit_port_id; } /* Set the type for a port of a circuit model */ -void CircuitLibrary::set_port_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_spice_model_port_type& port_type) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_types_[circuit_model_id][circuit_port_id] = port_type; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_types_[model_id][circuit_port_id] = port_type; /* Build the fast look-up for circuit model ports */ - build_circuit_model_port_lookup(circuit_model_id); + build_model_port_lookup(model_id); return; } /* Set the size for a port of a circuit model */ -void CircuitLibrary::set_port_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& port_size) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_sizes_[circuit_model_id][circuit_port_id] = port_size; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_sizes_[model_id][circuit_port_id] = port_size; return; } /* Set the prefix for a port of a circuit model */ -void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_prefix_[circuit_model_id][circuit_port_id] = port_prefix; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_prefix_[model_id][circuit_port_id] = port_prefix; return; } /* Set the lib_name for a port of a circuit model */ -void CircuitLibrary::set_port_lib_name(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& lib_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_lib_names_[circuit_model_id][circuit_port_id] = lib_name; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_lib_names_[model_id][circuit_port_id] = lib_name; return; } /* Set the inv_prefix for a port of a circuit model */ -void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& inv_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_inv_prefix_[circuit_model_id][circuit_port_id] = inv_prefix; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_inv_prefix_[model_id][circuit_port_id] = inv_prefix; return; } /* Set the default value for a port of a circuit model */ -void CircuitLibrary::set_port_default_value(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& default_value) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_default_values_[circuit_model_id][circuit_port_id] = default_value; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_default_values_[model_id][circuit_port_id] = default_value; return; } /* Set the is_mode_select for a port of a circuit model */ -void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_mode_select) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_mode_select_[circuit_model_id][circuit_port_id] = is_mode_select; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_mode_select_[model_id][circuit_port_id] = is_mode_select; return; } /* Set the is_global for a port of a circuit model */ -void CircuitLibrary::set_port_is_global(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_global) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_global_[circuit_model_id][circuit_port_id] = is_global; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_global_[model_id][circuit_port_id] = is_global; return; } /* Set the is_reset for a port of a circuit model */ -void CircuitLibrary::set_port_is_reset(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_reset) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_reset_[circuit_model_id][circuit_port_id] = is_reset; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_reset_[model_id][circuit_port_id] = is_reset; return; } /* Set the is_set for a port of a circuit model */ -void CircuitLibrary::set_port_is_set(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_set) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_set_[circuit_model_id][circuit_port_id] = is_set; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_set_[model_id][circuit_port_id] = is_set; return; } /* Set the is_config_enable for a port of a circuit model */ -void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_config_enable) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_config_enable_[circuit_model_id][circuit_port_id] = is_config_enable; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_config_enable_[model_id][circuit_port_id] = is_config_enable; return; } /* Set the is_prog for a port of a circuit model */ -void CircuitLibrary::set_port_is_prog(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_prog) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_prog_[circuit_model_id][circuit_port_id] = is_prog; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_prog_[model_id][circuit_port_id] = is_prog; return; } -/* Set the circuit_model_name for a port of a circuit model */ -void CircuitLibrary::set_port_circuit_model_name(const CircuitModelId& circuit_model_id, +/* Set the model_name for a port of a circuit model */ +void CircuitLibrary::set_port_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& circuit_model_name) { + const std::string& model_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_circuit_model_names_[circuit_model_id][circuit_port_id] = circuit_model_name; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_model_names_[model_id][circuit_port_id] = model_name; return; } -/* Set the circuit_model_id for a port of a circuit model */ -void CircuitLibrary::set_port_circuit_model_id(const CircuitModelId& circuit_model_id, +/* Set the model_id for a port of a circuit model */ +void CircuitLibrary::set_port_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& port_circuit_model_id) { + const CircuitModelId& port_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_circuit_model_ids_[circuit_model_id][circuit_port_id] = port_circuit_model_id; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_model_ids_[model_id][circuit_port_id] = port_model_id; return; } -/* Set the inv_circuit_model_name for a port of a circuit model */ -void CircuitLibrary::set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, +/* Set the inv_model_name for a port of a circuit model */ +void CircuitLibrary::set_port_inv_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& inv_circuit_model_name) { + const std::string& inv_model_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_inv_circuit_model_names_[circuit_model_id][circuit_port_id] = inv_circuit_model_name; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_inv_model_names_[model_id][circuit_port_id] = inv_model_name; return; } -/* Set the inv_circuit_model_id for a port of a circuit model */ -void CircuitLibrary::set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, +/* Set the inv_model_id for a port of a circuit model */ +void CircuitLibrary::set_port_inv_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_circuit_model_id) { + const CircuitModelId& inv_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_inv_circuit_model_ids_[circuit_model_id][circuit_port_id] = inv_circuit_model_id; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_inv_model_ids_[model_id][circuit_port_id] = inv_model_id; return; } /* Set the tri-state map for a port of a circuit model */ -void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& tri_state_map) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_tri_state_maps_[circuit_model_id][circuit_port_id] = tri_state_map; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_tri_state_maps_[model_id][circuit_port_id] = tri_state_map; return; } /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& lut_frac_level) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - port_lut_frac_level_[circuit_model_id][circuit_port_id] = lut_frac_level; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + port_lut_frac_level_[model_id][circuit_port_id] = lut_frac_level; return; } /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - port_lut_output_masks_[circuit_model_id][circuit_port_id] = lut_output_masks; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + port_lut_output_masks_[model_id][circuit_port_id] = lut_output_masks; return; } /* Set the SRAM organization for a port of a circuit model, only applicable to SRAM ports */ -void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Make sure this is a SRAM port */ - VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(circuit_model_id, circuit_port_id)); - port_sram_orgz_[circuit_model_id][circuit_port_id] = sram_orgz; + VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(model_id, circuit_port_id)); + port_sram_orgz_[model_id][circuit_port_id] = sram_orgz; return; } @@ -1066,311 +1066,311 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, * if yes, assign values * if no, resize and assign values */ -void CircuitLibrary::add_delay_info(const CircuitModelId& circuit_model_id, +void CircuitLibrary::add_delay_info(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Check the range of vector */ - if (size_t(delay_type) >= delay_types_[circuit_model_id].size()) { + if (size_t(delay_type) >= delay_types_[model_id].size()) { /* Resize */ - delay_types_[circuit_model_id].resize(size_t(delay_type) + 1); - delay_in_port_names_[circuit_model_id].resize(size_t(delay_type) + 1); - delay_out_port_names_[circuit_model_id].resize(size_t(delay_type) + 1); - delay_values_[circuit_model_id].resize(size_t(delay_type) + 1); + delay_types_[model_id].resize(size_t(delay_type) + 1); + delay_in_port_names_[model_id].resize(size_t(delay_type) + 1); + delay_out_port_names_[model_id].resize(size_t(delay_type) + 1); + delay_values_[model_id].resize(size_t(delay_type) + 1); } - delay_types_[circuit_model_id][size_t(delay_type)] = delay_type; + delay_types_[model_id][size_t(delay_type)] = delay_type; return; } -void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& in_port_names) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); - delay_in_port_names_[circuit_model_id][size_t(delay_type)] = in_port_names; + VTR_ASSERT(valid_delay_type(model_id, delay_type)); + delay_in_port_names_[model_id][size_t(delay_type)] = in_port_names; return; } -void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& out_port_names) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); - delay_out_port_names_[circuit_model_id][size_t(delay_type)] = out_port_names; + VTR_ASSERT(valid_delay_type(model_id, delay_type)); + delay_out_port_names_[model_id][size_t(delay_type)] = out_port_names; return; } -void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_delay_values(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& delay_values) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); - delay_values_[circuit_model_id][size_t(delay_type)] = delay_values; + VTR_ASSERT(valid_delay_type(model_id, delay_type)); + delay_values_[model_id][size_t(delay_type)] = delay_values; return; } /* Buffer/Inverter-related parameters */ -void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_type(const CircuitModelId& model_id, const enum e_spice_model_buffer_type& buffer_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_types_[circuit_model_id] = buffer_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_types_[model_id] = buffer_type; return; } -void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_size(const CircuitModelId& model_id, const float& buffer_size) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_sizes_[circuit_model_id] = buffer_size; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_sizes_[model_id] = buffer_size; return; } -void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& model_id, const size_t& num_levels) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_num_levels_[circuit_model_id] = num_levels; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_num_levels_[model_id] = num_levels; return; } -void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& model_id, const size_t& f_per_stage) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_f_per_stage_[circuit_model_id] = f_per_stage; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_f_per_stage_[model_id] = f_per_stage; return; } /* Pass-gate-related parameters */ -void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& model_id, const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); - pass_gate_logic_types_[circuit_model_id] = pass_gate_logic_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + pass_gate_logic_types_[model_id] = pass_gate_logic_type; return; } -void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& model_id, const float& nmos_size) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); - pass_gate_logic_sizes_[circuit_model_id].set_x(nmos_size); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + pass_gate_logic_sizes_[model_id].set_x(nmos_size); return; } -void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& model_id, const float& pmos_size) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); - pass_gate_logic_sizes_[circuit_model_id].set_y(pmos_size); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + pass_gate_logic_sizes_[model_id].set_y(pmos_size); return; } /* Multiplexer-related parameters */ -void CircuitLibrary::set_mux_structure(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_structure(const CircuitModelId& model_id, const enum e_spice_model_structure& mux_structure) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_structure_[circuit_model_id] = mux_structure; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_structure_[model_id] = mux_structure; return; } -void CircuitLibrary::set_mux_num_levels(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_num_levels(const CircuitModelId& model_id, const size_t& num_levels) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_num_levels_[circuit_model_id] = num_levels; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_num_levels_[model_id] = num_levels; return; } -void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& model_id, const size_t& const_input_value) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); /* validate the const input values */ VTR_ASSERT( valid_mux_const_input_value(const_input_value) ); - mux_const_input_values_[circuit_model_id] = const_input_value; + mux_const_input_values_[model_id] = const_input_value; return; } -void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& model_id, const bool& use_local_encoder) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_use_local_encoder_[circuit_model_id] = use_local_encoder; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_use_local_encoder_[model_id] = use_local_encoder; return; } -void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& model_id, const bool& use_advanced_rram_design) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_use_advanced_rram_design_[circuit_model_id] = use_advanced_rram_design; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_use_advanced_rram_design_[model_id] = use_advanced_rram_design; return; } /* LUT-related parameters */ -void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& model_id, const bool& is_fracturable) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - lut_is_fracturable_[circuit_model_id] = is_fracturable; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be LUT */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + lut_is_fracturable_[model_id] = is_fracturable; return; } /* Gate-related parameters */ -void CircuitLibrary::set_gate_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_gate_type(const CircuitModelId& model_id, const enum e_spice_model_gate_type& gate_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be GATE */ - VTR_ASSERT(SPICE_MODEL_GATE == circuit_model_type(circuit_model_id)); - gate_types_[circuit_model_id] = gate_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be GATE */ + VTR_ASSERT(SPICE_MODEL_GATE == model_type(model_id)); + gate_types_[model_id] = gate_type; return; } /* RRAM-related design technology information */ -void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_rlrs(const CircuitModelId& model_id, const float& rlrs) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - rram_res_[circuit_model_id].set_x(rlrs); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + rram_res_[model_id].set_x(rlrs); return; } -void CircuitLibrary::set_rram_rhrs(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_rhrs(const CircuitModelId& model_id, const float& rhrs) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - rram_res_[circuit_model_id].set_y(rhrs); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + rram_res_[model_id].set_y(rhrs); return; } -void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& model_id, const float& wprog_set_nmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_set_[circuit_model_id].set_x(wprog_set_nmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_set_[model_id].set_x(wprog_set_nmos); return; } -void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& model_id, const float& wprog_set_pmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_set_[circuit_model_id].set_y(wprog_set_pmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_set_[model_id].set_y(wprog_set_pmos); return; } -void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& model_id, const float& wprog_reset_nmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_reset_[circuit_model_id].set_x(wprog_reset_nmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_reset_[model_id].set_x(wprog_reset_nmos); return; } -void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& model_id, const float& wprog_reset_pmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_reset_[circuit_model_id].set_y(wprog_reset_pmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_reset_[model_id].set_y(wprog_reset_pmos); return; } /* Wire parameters */ -void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_type(const CircuitModelId& model_id, const enum e_wire_model_type& wire_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_types_[circuit_model_id] = wire_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_types_[model_id] = wire_type; return; } -void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_r(const CircuitModelId& model_id, const float& r_val) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_rc_[circuit_model_id].set_x(r_val); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_rc_[model_id].set_x(r_val); return; } -void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_c(const CircuitModelId& model_id, const float& c_val) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_rc_[circuit_model_id].set_y(c_val); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_rc_[model_id].set_y(c_val); return; } -void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_num_levels(const CircuitModelId& model_id, const size_t& num_level) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_num_levels_[circuit_model_id] = num_level; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_num_levels_[model_id] = num_level; return; } @@ -1382,130 +1382,130 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, * If yes, just assign values * If no, resize the vector and then assign values */ -void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Check the range of vector */ - if (size_t(buffer_type) >= buffer_existence_[circuit_model_id].size()) { + if (size_t(buffer_type) >= buffer_existence_[model_id].size()) { /* Resize and assign values */ - buffer_existence_[circuit_model_id].resize(size_t(buffer_type) + 1); - buffer_circuit_model_names_[circuit_model_id].resize(size_t(buffer_type) + 1); - buffer_circuit_model_ids_[circuit_model_id].resize(size_t(buffer_type) + 1); - buffer_location_maps_[circuit_model_id].resize(size_t(buffer_type) + 1); + buffer_existence_[model_id].resize(size_t(buffer_type) + 1); + buffer_model_names_[model_id].resize(size_t(buffer_type) + 1); + buffer_model_ids_[model_id].resize(size_t(buffer_type) + 1); + buffer_location_maps_[model_id].resize(size_t(buffer_type) + 1); } /* Now we are in the range, assign values */ - buffer_existence_[circuit_model_id][size_t(buffer_type)] = existence; - buffer_circuit_model_names_[circuit_model_id][size_t(buffer_type)] = circuit_model_name; - buffer_circuit_model_ids_[circuit_model_id][size_t(buffer_type)] = CIRCUIT_MODEL_OPEN_ID; /* Set an OPEN id here, which will be linked later */ + buffer_existence_[model_id][size_t(buffer_type)] = existence; + buffer_model_names_[model_id][size_t(buffer_type)] = model_name; + buffer_model_ids_[model_id][size_t(buffer_type)] = CircuitModelId::INVALID(); /* Set an OPEN id here, which will be linked later */ return; } -/* Link the circuit_model_id for each port of a circuit model. - * We search the inv_circuit_model_name in the CircuitLibrary and - * configure the port inv_circuit_model_id +/* Link the model_id for each port of a circuit model. + * We search the inv_model_name in the CircuitLibrary and + * configure the port inv_model_id */ -void CircuitLibrary::link_port_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_port_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports(circuit_model_id)) { + for (auto& port_id : ports(model_id)) { /* Bypass empty name */ - if (true == port_circuit_model_names_[circuit_model_id][port_id].empty()) { + if (true == port_model_names_[model_id][port_id].empty()) { continue; } - port_circuit_model_ids_[circuit_model_id][port_id] = circuit_model(port_circuit_model_names_[circuit_model_id][port_id]); + port_model_ids_[model_id][port_id] = model(port_model_names_[model_id][port_id]); } return; } -/* Link the inv_circuit_model_id for each port of a circuit model. - * We search the inv_circuit_model_name in the CircuitLibrary and - * configure the port inv_circuit_model_id +/* Link the inv_model_id for each port of a circuit model. + * We search the inv_model_name in the CircuitLibrary and + * configure the port inv_model_id */ -void CircuitLibrary::link_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_port_inv_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports(circuit_model_id)) { + for (auto& port_id : ports(model_id)) { /* Bypass empty name */ - if (true == port_inv_circuit_model_names_[circuit_model_id][port_id].empty()) { + if (true == port_inv_model_names_[model_id][port_id].empty()) { continue; } - port_inv_circuit_model_ids_[circuit_model_id][port_id] = circuit_model(port_inv_circuit_model_names_[circuit_model_id][port_id]); + port_inv_model_ids_[model_id][port_id] = model(port_inv_model_names_[model_id][port_id]); } return; } /* Link all the circuit model ids for each port of a circuit model */ -void CircuitLibrary::link_port_circuit_models(const CircuitModelId& circuit_model_id) { - link_port_circuit_model(circuit_model_id); - link_port_inv_circuit_model(circuit_model_id); +void CircuitLibrary::link_port_models(const CircuitModelId& model_id) { + link_port_model(model_id); + link_port_inv_model(model_id); return; } -/* Link the buffer_circuit_model - * We search the buffer_circuit_model_name in the CircuitLibrary and - * configure the buffer_circuit_model_id +/* Link the buffer_model + * We search the buffer_model_name in the CircuitLibrary and + * configure the buffer_model_id */ -void CircuitLibrary::link_buffer_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Get the circuit model id by name, skip those with empty names*/ - for (size_t buffer_id = 0; buffer_id < buffer_circuit_model_names_[circuit_model_id].size(); ++buffer_id) { - if (true == buffer_circuit_model_names_[circuit_model_id][buffer_id].empty()) { + for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) { + if (true == buffer_model_names_[model_id][buffer_id].empty()) { return; } - buffer_circuit_model_ids_[circuit_model_id][buffer_id] = circuit_model(buffer_circuit_model_names_[circuit_model_id][buffer_id]); + buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]); } return; } -/* Link the buffer_circuit_model - * We search the buffer_circuit_model_name in the CircuitLibrary and - * configure the buffer_circuit_model_id +/* Link the buffer_model + * We search the buffer_model_name in the CircuitLibrary and + * configure the buffer_model_id */ -void CircuitLibrary::link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_pass_gate_logic_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Get the circuit model id by name, skip those with empty names*/ - if (true == pass_gate_logic_circuit_model_names_[circuit_model_id].empty()) { + if (true == pass_gate_logic_model_names_[model_id].empty()) { return; } - pass_gate_logic_circuit_model_ids_[circuit_model_id] = circuit_model(pass_gate_logic_circuit_model_names_[circuit_model_id]); + pass_gate_logic_model_ids_[model_id] = model(pass_gate_logic_model_names_[model_id]); return; } -/* Build the links for attributes of each circuit_model by searching the circuit_model_names */ -void CircuitLibrary::build_circuit_model_links() { +/* Build the links for attributes of each model by searching the model_names */ +void CircuitLibrary::build_model_links() { /* Walk through each circuit model, build links one by one */ - for (auto& circuit_model_id : circuit_models()) { - /* Build links for buffers, pass-gates circuit_model */ - link_buffer_circuit_model(circuit_model_id); - link_pass_gate_logic_circuit_model(circuit_model_id); + for (auto& model_id : models()) { + /* Build links for buffers, pass-gates model */ + link_buffer_model(model_id); + link_pass_gate_logic_model(model_id); /* Build links for ports */ - link_port_circuit_models(circuit_model_id); + link_port_models(model_id); } return; } /* Build the timing graph for a circuit models*/ -void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { +void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { /* Now we start allocating a timing graph * Add outgoing edges for each input pin of the circuit model */ - for (auto& from_port_id : input_ports(circuit_model_id)) { + for (auto& from_port_id : input_ports(model_id)) { /* Add edges for each input pin */ - for (auto& from_pin_id : pins(circuit_model_id, from_port_id)) { + for (auto& from_pin_id : pins(model_id, from_port_id)) { /* We should walk through output pins here */ - for (auto& to_port_id : output_ports(circuit_model_id)) { - for (auto& to_pin_id : pins(circuit_model_id, to_port_id)) { + for (auto& to_port_id : output_ports(model_id)) { + for (auto& to_pin_id : pins(model_id, to_port_id)) { /* Skip self-loops */ if (from_port_id == to_port_id) { continue; } /* Add an edge to bridge the from_pin_id and to_pin_id */ - add_edge(circuit_model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); + add_edge(model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); } } } @@ -1516,12 +1516,12 @@ void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circ /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_timing_graphs() { /* Walk through each circuit model, build timing graph one by one */ - for (auto& circuit_model_id : circuit_models()) { + for (auto& model_id : models()) { /* Free the timing graph if it already exists, we will rebuild one */ - invalidate_circuit_model_timing_graph(circuit_model_id); - build_circuit_model_timing_graph(circuit_model_id); + invalidate_model_timing_graph(model_id); + build_model_timing_graph(model_id); /* Annotate timing information */ - set_timing_graph_delays(circuit_model_id); + set_timing_graph_delays(model_id); } return; } @@ -1530,66 +1530,66 @@ void CircuitLibrary::build_timing_graphs() { * Internal mutators: build timing graphs ***********************************************************************/ /* Add an edge between two pins of two ports, and assign an default timing value */ -void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, +void CircuitLibrary::add_edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Create an edge in the edge id list */ - CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[circuit_model_id].size()); + CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[model_id].size()); /* Expand the edge list */ - edge_ids_[circuit_model_id].push_back(edge_id); + edge_ids_[model_id].push_back(edge_id); /* Initialize other attributes */ /* Update the list of incoming edges for to_port */ /* Resize upon need */ - if (to_pin >= port_in_edge_ids_[circuit_model_id][to_port].size()) { - port_in_edge_ids_[circuit_model_id][to_port].resize(to_pin + 1); + if (to_pin >= port_in_edge_ids_[model_id][to_port].size()) { + port_in_edge_ids_[model_id][to_port].resize(to_pin + 1); } - port_in_edge_ids_[circuit_model_id][to_port][to_pin] = edge_id; + port_in_edge_ids_[model_id][to_port][to_pin] = edge_id; /* Update the list of outgoing edges for from_port */ /* Resize upon need */ - if (from_pin >= port_out_edge_ids_[circuit_model_id][from_port].size()) { - port_out_edge_ids_[circuit_model_id][from_port].resize(from_pin + 1); + if (from_pin >= port_out_edge_ids_[model_id][from_port].size()) { + port_out_edge_ids_[model_id][from_port].resize(from_pin + 1); } - port_out_edge_ids_[circuit_model_id][from_port][from_pin] = edge_id; + port_out_edge_ids_[model_id][from_port][from_pin] = edge_id; /* Update source ports and pins of the edge */ - edge_src_port_ids_[circuit_model_id].push_back(from_port); - edge_src_pin_ids_[circuit_model_id].push_back(from_pin); + edge_src_port_ids_[model_id].push_back(from_port); + edge_src_pin_ids_[model_id].push_back(from_pin); /* Update sink ports and pins of the edge */ - edge_sink_port_ids_[circuit_model_id].push_back(to_port); - edge_sink_pin_ids_[circuit_model_id].push_back(to_pin); + edge_sink_port_ids_[model_id].push_back(to_port); + edge_sink_pin_ids_[model_id].push_back(to_pin); /* Give a default value for timing values */ std::vector timing_info(NUM_CIRCUIT_MODEL_DELAY_TYPES, 0); - edge_timing_info_[circuit_model_id].push_back(timing_info); + edge_timing_info_[model_id].push_back(timing_info); return; } -void CircuitLibrary::set_edge_delay(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, const enum spice_model_delay_type& delay_type, const float& delay_value) { /* validate the circuit_edge_id */ - VTR_ASSERT(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); + VTR_ASSERT(valid_circuit_edge_id(model_id, circuit_edge_id)); + VTR_ASSERT(valid_delay_type(model_id, delay_type)); - edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(delay_type)] = delay_value; + edge_timing_info_[model_id][circuit_edge_id][size_t(delay_type)] = delay_value; return; } /* Annotate delay values on a timing graph */ -void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Go one delay_info by another */ - for (const auto& delay_type : delay_types_[circuit_model_id]) { + for (const auto& delay_type : delay_types_[model_id]) { /* Parse the input port names and output names. * We will store the parsing results in vectors: * 1. vector for port ids for each port name @@ -1597,65 +1597,65 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model */ /* Parse the string for inputs */ - MultiPortParser input_port_parser(delay_in_port_names_[circuit_model_id][size_t(delay_type)]); + MultiPortParser input_port_parser(delay_in_port_names_[model_id][size_t(delay_type)]); std::vector input_ports = input_port_parser.ports(); std::vector input_port_ids; std::vector input_pin_ids; /* Check each element */ for (auto& port_info : input_ports) { /* Try to find a port by the given name */ - CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); + CircuitPortId port_id = port(model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT(CIRCUIT_PORT_OPEN_ID != port_id); + VTR_ASSERT(CircuitPortId::INVALID() != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as */ - size_t port_width = port_size(circuit_model_id, port_id); + size_t port_width = port_size(model_id, port_id); port_info.set_width(port_width); } else { VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(model_id, port_id, port_info.get_lsb())); /* This must be an input port! */ - VTR_ASSERT(true == is_input_port(circuit_model_id, port_id)); + VTR_ASSERT(true == is_input_port(model_id, port_id)); /* Push to */ input_port_ids.push_back(port_id); input_pin_ids.push_back(port_info.get_lsb()); } /* Parse the string for outputs */ - MultiPortParser output_port_parser(delay_out_port_names_[circuit_model_id][size_t(delay_type)]); + MultiPortParser output_port_parser(delay_out_port_names_[model_id][size_t(delay_type)]); std::vector output_ports = output_port_parser.ports(); std::vector output_port_ids; std::vector output_pin_ids; /* Check each element */ for (auto& port_info : output_ports) { /* Try to find a port by the given name */ - CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); + CircuitPortId port_id = port(model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT(CIRCUIT_PORT_OPEN_ID != port_id); + VTR_ASSERT(CircuitPortId::INVALID() != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as */ - size_t port_width = port_size(circuit_model_id, port_id); + size_t port_width = port_size(model_id, port_id); port_info.set_width(port_width); } else { VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(model_id, port_id, port_info.get_lsb())); /* This must be an output port! */ - VTR_ASSERT(true == is_output_port(circuit_model_id, port_id)); + VTR_ASSERT(true == is_output_port(model_id, port_id)); /* Push to */ output_port_ids.push_back(port_id); output_pin_ids.push_back(port_info.get_lsb()); } /* Parse the delay matrix */ - PortDelayParser port_delay_parser(delay_values_[circuit_model_id][size_t(delay_type)]); + PortDelayParser port_delay_parser(delay_values_[model_id][size_t(delay_type)]); /* Make sure the delay matrix size matches */ VTR_ASSERT(port_delay_parser.height() == output_port_ids.size()); @@ -1667,12 +1667,12 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model for (size_t i = 0; i < port_delay_parser.height(); ++i) { for (size_t j = 0; j < port_delay_parser.width(); ++j) { float delay_value = port_delay_parser.delay(i, j); - CircuitEdgeId edge_id = edge(circuit_model_id, + CircuitEdgeId edge_id = edge(model_id, input_port_ids[j], input_pin_ids[j], output_port_ids[i], output_pin_ids[i]); /* make sure we have an valid edge_id */ - VTR_ASSERT(true == valid_circuit_edge_id(circuit_model_id, edge_id)); - set_edge_delay(circuit_model_id, edge_id, + VTR_ASSERT(true == valid_circuit_edge_id(model_id, edge_id)); + set_edge_delay(model_id, edge_id, delay_type, delay_value); } } @@ -1684,28 +1684,28 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model * Internal mutators: build fast look-ups ***********************************************************************/ /* Build fast look-up for circuit models */ -void CircuitLibrary::build_circuit_model_lookup() { +void CircuitLibrary::build_model_lookup() { /* invalidate fast look-up */ - invalidate_circuit_model_lookup(); + invalidate_model_lookup(); /* Classify circuit models by type */ - circuit_model_lookup_.resize(NUM_CIRCUIT_MODEL_TYPES); - /* Walk through circuit_models and categorize */ - for (auto& id : circuit_model_ids_) { - circuit_model_lookup_[circuit_model_types_[id]].push_back(id); + model_lookup_.resize(NUM_CIRCUIT_MODEL_TYPES); + /* Walk through models and categorize */ + for (auto& id : model_ids_) { + model_lookup_[model_types_[id]].push_back(id); } - /* Make the default circuit_model to be the first element for each type */ - for (auto& type : circuit_model_lookup_) { + /* Make the default model to be the first element for each type */ + for (auto& type : model_lookup_) { /* Skip zero-length parts of look-up */ if (true == type.empty()) { continue; } /* if the first element is already a default model, we skip this */ - if (true == circuit_model_is_default_[type[0]]) { + if (true == model_is_default_[type[0]]) { continue; } /* Check the array, and try to find a default model */ for (size_t id = 0; id < type.size(); ++id) { - if (false == circuit_model_is_default_[type[id]]) { + if (false == model_is_default_[type[id]]) { continue; } /* Once we find a default model, swap with the first element and finish the loop */ @@ -1717,14 +1717,14 @@ void CircuitLibrary::build_circuit_model_lookup() { } /* Build fast look-up for circuit model ports */ -void CircuitLibrary::build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) { +void CircuitLibrary::build_model_port_lookup(const CircuitModelId& model_id) { /* invalidate fast look-up */ - invalidate_circuit_model_port_lookup(circuit_model_id); + invalidate_model_port_lookup(model_id); /* Classify circuit models by type */ - circuit_model_port_lookup_[size_t(circuit_model_id)].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); - /* Walk through circuit_models and categorize */ - for (auto& port_id : port_ids_[circuit_model_id]) { - circuit_model_port_lookup_[size_t(circuit_model_id)][port_type(circuit_model_id, port_id)].push_back(port_id); + model_port_lookup_[size_t(model_id)].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + /* Walk through models and categorize */ + for (auto& port_id : port_ids_[model_id]) { + model_port_lookup_[size_t(model_id)][port_type(model_id, port_id)].push_back(port_id); } return; } @@ -1733,32 +1733,32 @@ void CircuitLibrary::build_circuit_model_port_lookup(const CircuitModelId& circu * Internal invalidators/validators ***********************************************************************/ /* Validators */ -bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_id) const { - return ( size_t(circuit_model_id) < circuit_model_ids_.size() ) && ( circuit_model_id == circuit_model_ids_[circuit_model_id] ); +bool CircuitLibrary::valid_model_id(const CircuitModelId& model_id) const { + return ( size_t(model_id) < model_ids_.size() ) && ( model_id == model_ids_[model_id] ); } -bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); +bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ( size_t(circuit_port_id) < port_ids_[model_id].size() ) && ( circuit_port_id == port_ids_[model_id][circuit_port_id] ); } -bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return ( size_t(pin_id) < port_size(circuit_model_id, circuit_port_id) ); +bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return ( size_t(pin_id) < port_size(model_id, circuit_port_id) ); } -bool CircuitLibrary::valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ( size_t(delay_type) < delay_types_[circuit_model_id].size() ) && ( delay_type == delay_types_[circuit_model_id][size_t(delay_type)] ); +bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ( size_t(delay_type) < delay_types_[model_id].size() ) && ( delay_type == delay_types_[model_id][size_t(delay_type)] ); } -bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ( size_t(circuit_edge_id) < edge_ids_[circuit_model_id].size() ) && ( circuit_edge_id == edge_ids_[circuit_model_id][circuit_edge_id] ); +bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ( size_t(circuit_edge_id) < edge_ids_[model_id].size() ) && ( circuit_edge_id == edge_ids_[model_id][circuit_edge_id] ); } /* Validate the value of constant input @@ -1774,38 +1774,38 @@ bool CircuitLibrary::valid_mux_const_input_value(const size_t& const_input_value } /* Invalidators */ -/* Empty fast lookup for circuit_models*/ -void CircuitLibrary::invalidate_circuit_model_lookup() const { - circuit_model_lookup_.clear(); +/* Empty fast lookup for models*/ +void CircuitLibrary::invalidate_model_lookup() const { + model_lookup_.clear(); return; } -/* Empty fast lookup for circuit ports for a circuit_model */ -void CircuitLibrary::invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_port_lookup_[size_t(circuit_model_id)].clear(); +/* Empty fast lookup for circuit ports for a model */ +void CircuitLibrary::invalidate_model_port_lookup(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_port_lookup_[size_t(model_id)].clear(); return; } /* Clear all the data structure related to the timing graph */ -void CircuitLibrary::invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - edge_ids_[circuit_model_id].clear(); +void CircuitLibrary::invalidate_model_timing_graph(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + edge_ids_[model_id].clear(); - for (const auto& port_id : ports(circuit_model_id)) { - port_in_edge_ids_[circuit_model_id][port_id].clear(); - port_out_edge_ids_[circuit_model_id][port_id].clear(); + for (const auto& port_id : ports(model_id)) { + port_in_edge_ids_[model_id][port_id].clear(); + port_out_edge_ids_[model_id][port_id].clear(); } - edge_src_port_ids_[circuit_model_id].clear(); - edge_src_pin_ids_[circuit_model_id].clear(); + edge_src_port_ids_[model_id].clear(); + edge_src_pin_ids_[model_id].clear(); - edge_sink_port_ids_[circuit_model_id].clear(); - edge_sink_pin_ids_[circuit_model_id].clear(); + edge_sink_port_ids_[model_id].clear(); + edge_sink_pin_ids_[model_id].clear(); - edge_timing_info_[circuit_model_id].clear(); + edge_timing_info_[model_id].clear(); return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 211475098..a74429347 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -49,7 +49,6 @@ /* Standard header files required go first */ #include -#include "vtr_strong_id.h" #include "vtr_geometry.h" #include "vtr_vector.h" @@ -57,22 +56,7 @@ #include "circuit_types.h" -/************************************************************************ - * Create strong id for Circuit Models/Ports to avoid illegal type casting - ***********************************************************************/ -struct circuit_model_id_tag; -struct circuit_port_id_tag; -struct circuit_edge_id_tag; - -typedef vtr::StrongId CircuitModelId; -typedef vtr::StrongId CircuitPortId; -typedef vtr::StrongId CircuitEdgeId; - - -/* Alias for open ids */ -#define CIRCUIT_MODEL_OPEN_ID CircuitModelId(-1) -#define CIRCUIT_PORT_OPEN_ID CircuitPortId(-1) -#define CIRCUIT_EDGE_OPEN_ID CircuitEdgeId(-1) +#include "circuit_library_fwd.h" /************************************************************************ * The class CircuitLibrary is a critical data structure for OpenFPGA @@ -81,20 +65,20 @@ typedef vtr::StrongId CircuitEdgeId; * It includes the following data: * * ------ Fundamental Information ----- - * 1. circuit_model_ids_ : unique identifier to find a circuit model + * 1. model_ids_ : unique identifier to find a circuit model * Use a strong id for search, to avoid illegal type casting - * 2. circuit_model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type - * 3. circuit_model_names_: unique names for each circuit models. + * 2. model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type + * 3. model_names_: unique names for each circuit models. * It should be the same as user-defined Verilog modules, if it is not auto-generated - * 4. circuit_model_prefix_: the prefix of a circuit model when it is instanciated + * 4. model_prefix_: the prefix of a circuit model when it is instanciated * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated * 7. is_default_: indicate if the circuit model is the default one among all those in the same type * * ------ Fast look-ups----- - * 1. circuit_model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users + * 1. model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users * It classifies CircuitModelIds by their type and set the default model in the first element for each type. - * 2. circuit_model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users + * 2. model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users * It classifies Ports by their types * * ------ Verilog generation options ----- @@ -109,12 +93,12 @@ typedef vtr::StrongId CircuitEdgeId; * Use vectors to simplify the defition of buffer existence: * index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER * 1. buffer_existence_: specify if this circuit model has an buffer - * 2. buffer_circuit_model_name_: specify the name of circuit model for the buffer - * 3. buffer_circuit_model_id_: specify the id of circuit model for the buffer + * 2. buffer_model_name_: specify the name of circuit model for the buffer + * 3. buffer_model_id_: specify the id of circuit model for the buffer * * ------ Pass-gate-related parameters ------ - * 1. pass_gate_logic_circuit_model_name_: specify the name of circuit model for the pass gate logic - * 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic + * 1. pass_gate_logic_model_name_: specify the name of circuit model for the pass gate logic + * 2. pass_gate_logic_model_id_: specify the id of circuit model for the pass gate logic * * ------ Port information ------ * 1. port_ids_: unique id of ports belonging to a circuit model @@ -129,10 +113,10 @@ typedef vtr::StrongId CircuitEdgeId; * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_circuit_model_name: the name of circuit model linked to the port - * 14. port_circuit_model_ids_: the Id of circuit model linked to the port - * 15. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port - * 16. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port + * 13. port_model_name: the name of circuit model linked to the port + * 14. port_model_ids_: the Id of circuit model linked to the port + * 15. port_inv_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used @@ -196,19 +180,19 @@ typedef vtr::StrongId CircuitEdgeId; * * ------ Metal wire-related parameters ------ * Note: only applicable to circuit models whose type is wires or channel wires - * 1. wire_types_: types of the metal wire for the circuit_model + * 1. wire_types_: types of the metal wire for the model * 2. wire_res_val_: resistance value of the metal wire for the circuit model * 3. wire_cap_val_: capacitance value of the metal wire for the circuit model * 4. wire_num_levels_: number of levels of the metal wire model for the circuit model ***********************************************************************/ class CircuitLibrary { public: /* Types */ - typedef vtr::vector::const_iterator circuit_model_iterator; - typedef vtr::vector::const_iterator circuit_model_string_iterator; + typedef vtr::vector::const_iterator model_iterator; + typedef vtr::vector::const_iterator model_string_iterator; typedef vtr::vector::const_iterator circuit_port_iterator; typedef vtr::vector::const_iterator circuit_edge_iterator; /* Create range */ - typedef vtr::Range circuit_model_range; + typedef vtr::Range model_range; typedef vtr::Range circuit_port_range; typedef vtr::Range circuit_edge_range; /* local enumeration for buffer existence */ @@ -218,272 +202,272 @@ class CircuitLibrary { public: /* Constructors */ CircuitLibrary(); public: /* Accessors: aggregates */ - circuit_model_range circuit_models() const; - circuit_port_range ports(const CircuitModelId& circuit_model_id) const; - std::vector circuit_models_by_type(const enum e_spice_model_type& type) const; - std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type) const; - std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - std::vector input_ports(const CircuitModelId& circuit_model_id) const; - std::vector output_ports(const CircuitModelId& circuit_model_id) const; - std::vector pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + model_range models() const; + circuit_port_range ports(const CircuitModelId& model_id) const; + std::vector models_by_type(const enum e_spice_model_type& type) const; + std::vector ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; + std::vector ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; + std::vector input_ports(const CircuitModelId& model_id) const; + std::vector output_ports(const CircuitModelId& model_id) const; + std::vector pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Basic data query on Circuit Models*/ - size_t num_circuit_models() const; - enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_name(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_prefix(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const; - bool circuit_model_is_default(const CircuitModelId& circuit_model_id) const; - bool dump_structural_verilog(const CircuitModelId& circuit_model_id) const; - bool dump_explicit_port_map(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_design_tech design_tech_type(const CircuitModelId& circuit_model_id) const; - bool is_power_gated(const CircuitModelId& circuit_model_id) const; - bool is_input_buffered(const CircuitModelId& circuit_model_id) const; - bool is_output_buffered(const CircuitModelId& circuit_model_id) const; - bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_structure mux_structure(const CircuitModelId& circuit_model_id) const; - size_t mux_num_levels(const CircuitModelId& circuit_model_id) const; - bool mux_add_const_input(const CircuitModelId& circuit_model_id) const; - size_t mux_const_input_value(const CircuitModelId& circuit_model_id) const; + size_t num_models() const; + enum e_spice_model_type model_type(const CircuitModelId& model_id) const; + std::string model_name(const CircuitModelId& model_id) const; + std::string model_prefix(const CircuitModelId& model_id) const; + std::string model_verilog_netlist(const CircuitModelId& model_id) const; + std::string model_spice_netlist(const CircuitModelId& model_id) const; + bool model_is_default(const CircuitModelId& model_id) const; + bool dump_structural_verilog(const CircuitModelId& model_id) const; + bool dump_explicit_port_map(const CircuitModelId& model_id) const; + enum e_spice_model_design_tech design_tech_type(const CircuitModelId& model_id) const; + bool is_power_gated(const CircuitModelId& model_id) const; + bool is_input_buffered(const CircuitModelId& model_id) const; + bool is_output_buffered(const CircuitModelId& model_id) const; + bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; + enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; + enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const; + size_t mux_num_levels(const CircuitModelId& model_id) const; + bool mux_add_const_input(const CircuitModelId& model_id) const; + size_t mux_const_input_value(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ - bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - CircuitPortId port(const CircuitModelId& circuit_model_id, const std::string& name) const; - size_t num_ports(const CircuitModelId& circuit_model_id) const; - size_t num_ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - std::string port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - std::string port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - size_t port_default_value(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_set(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + CircuitPortId port(const CircuitModelId& model_id, const std::string& name) const; + size_t num_ports(const CircuitModelId& model_id) const; + size_t num_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; + enum e_spice_model_port_type port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + size_t port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + std::string port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + std::string port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + std::string port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + size_t port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Methods to find circuit model */ - CircuitModelId circuit_model(const char* name) const; - CircuitModelId circuit_model(const std::string& name) const; - CircuitModelId default_circuit_model(const enum e_spice_model_type& type) const; + CircuitModelId model(const char* name) const; + CircuitModelId model(const std::string& name) const; + CircuitModelId default_model(const enum e_spice_model_type& type) const; public: /* Public Accessors: Timing graph */ - CircuitEdgeId edge(const CircuitModelId& circuit_model_id, + CircuitEdgeId edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin); public: /* Public Mutators */ - CircuitModelId add_circuit_model(); + CircuitModelId add_model(); /* Fundamental information */ - void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type); - void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name); - void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix); - void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist); - void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist); - void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default); + void set_model_type(const CircuitModelId& model_id, const enum e_spice_model_type& type); + void set_model_name(const CircuitModelId& model_id, const std::string& name); + void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix); + void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist); + void set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist); + void set_model_is_default(const CircuitModelId& model_id, const bool& is_default); /* Verilog generator options */ - void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog); - void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); + void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog); + void set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map); /* Design technology information */ - void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); - void set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated); + void set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type); + void set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated); /* Buffer existence */ - void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, + void set_model_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_output_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_input_inverter(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_intermediate_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, const std::string& location_map); /* Pass-gate-related parameters */ - void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name); + void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name); /* Port information */ - CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id); - void set_port_type(const CircuitModelId& circuit_model_id, + CircuitPortId add_model_port(const CircuitModelId& model_id); + void set_port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_spice_model_port_type& port_type); - void set_port_size(const CircuitModelId& circuit_model_id, + void set_port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& port_size); - void set_port_prefix(const CircuitModelId& circuit_model_id, + void set_port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix); - void set_port_lib_name(const CircuitModelId& circuit_model_id, + void set_port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& lib_name); - void set_port_inv_prefix(const CircuitModelId& circuit_model_id, + void set_port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& inv_prefix); - void set_port_default_value(const CircuitModelId& circuit_model_id, + void set_port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& default_val); - void set_port_is_mode_select(const CircuitModelId& circuit_model_id, + void set_port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_mode_select); - void set_port_is_global(const CircuitModelId& circuit_model_id, + void set_port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_global); - void set_port_is_reset(const CircuitModelId& circuit_model_id, + void set_port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_reset); - void set_port_is_set(const CircuitModelId& circuit_model_id, + void set_port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_set); - void set_port_is_config_enable(const CircuitModelId& circuit_model_id, + void set_port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_config_enable); - void set_port_is_prog(const CircuitModelId& circuit_model_id, + void set_port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_prog); - void set_port_circuit_model_name(const CircuitModelId& circuit_model_id, + void set_port_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& circuit_model_name); - void set_port_circuit_model_id(const CircuitModelId& circuit_model_id, + const std::string& model_name); + void set_port_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& port_circuit_model_id); - void set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, + const CircuitModelId& port_model_id); + void set_port_inv_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& inv_circuit_model_name); - void set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, + const std::string& inv_model_name); + void set_port_inv_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_circuit_model_id); - void set_port_tri_state_map(const CircuitModelId& circuit_model_id, + const CircuitModelId& inv_model_id); + void set_port_tri_state_map(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& tri_state_map); - void set_port_lut_frac_level(const CircuitModelId& circuit_model_id, + void set_port_lut_frac_level(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& lut_frac_level); - void set_port_lut_output_mask(const CircuitModelId& circuit_model_id, + void set_port_lut_output_mask(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks); - void set_port_sram_orgz(const CircuitModelId& circuit_model_id, + void set_port_sram_orgz(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz); /* Delay information */ - void add_delay_info(const CircuitModelId& circuit_model_id, + void add_delay_info(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type); - void set_delay_in_port_names(const CircuitModelId& circuit_model_id, + void set_delay_in_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& in_port_names); - void set_delay_out_port_names(const CircuitModelId& circuit_model_id, + void set_delay_out_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& out_port_names); - void set_delay_values(const CircuitModelId& circuit_model_id, + void set_delay_values(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& delay_values); /* Buffer/Inverter-related parameters */ - void set_buffer_type(const CircuitModelId& circuit_model_id, + void set_buffer_type(const CircuitModelId& model_id, const enum e_spice_model_buffer_type& buffer_type); - void set_buffer_size(const CircuitModelId& circuit_model_id, + void set_buffer_size(const CircuitModelId& model_id, const float& buffer_size); - void set_buffer_num_levels(const CircuitModelId& circuit_model_id, + void set_buffer_num_levels(const CircuitModelId& model_id, const size_t& num_levels); - void set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, + void set_buffer_f_per_stage(const CircuitModelId& model_id, const size_t& f_per_stage); /* Pass-gate-related parameters */ - void set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, + void set_pass_gate_logic_type(const CircuitModelId& model_id, const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type); - void set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, + void set_pass_gate_logic_nmos_size(const CircuitModelId& model_id, const float& nmos_size); - void set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, + void set_pass_gate_logic_pmos_size(const CircuitModelId& model_id, const float& pmos_size); /* Multiplexer-related parameters */ - void set_mux_structure(const CircuitModelId& circuit_model_id, + void set_mux_structure(const CircuitModelId& model_id, const enum e_spice_model_structure& mux_structure); - void set_mux_num_levels(const CircuitModelId& circuit_model_id, + void set_mux_num_levels(const CircuitModelId& model_id, const size_t& num_levels); - void set_mux_const_input_value(const CircuitModelId& circuit_model_id, + void set_mux_const_input_value(const CircuitModelId& model_id, const size_t& const_input_value); - void set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, + void set_mux_use_local_encoder(const CircuitModelId& model_id, const bool& use_local_encoder); - void set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, + void set_mux_use_advanced_rram_design(const CircuitModelId& model_id, const bool& use_advanced_rram_design); /* LUT-related parameters */ - void set_lut_is_fracturable(const CircuitModelId& circuit_model_id, + void set_lut_is_fracturable(const CircuitModelId& model_id, const bool& is_fracturable); /* Gate-related parameters */ - void set_gate_type(const CircuitModelId& circuit_model_id, + void set_gate_type(const CircuitModelId& model_id, const enum e_spice_model_gate_type& gate_type); /* RRAM-related design technology information */ - void set_rram_rlrs(const CircuitModelId& circuit_model_id, + void set_rram_rlrs(const CircuitModelId& model_id, const float& rlrs); - void set_rram_rhrs(const CircuitModelId& circuit_model_id, + void set_rram_rhrs(const CircuitModelId& model_id, const float& rhrs); - void set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_set_nmos(const CircuitModelId& model_id, const float& wprog_set_nmos); - void set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_set_pmos(const CircuitModelId& model_id, const float& wprog_set_pmos); - void set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_reset_nmos(const CircuitModelId& model_id, const float& wprog_reset_nmos); - void set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_reset_pmos(const CircuitModelId& model_id, const float& wprog_reset_pmos); /* Wire parameters */ - void set_wire_type(const CircuitModelId& circuit_model_id, + void set_wire_type(const CircuitModelId& model_id, const enum e_wire_model_type& wire_type); - void set_wire_r(const CircuitModelId& circuit_model_id, + void set_wire_r(const CircuitModelId& model_id, const float& r_val); - void set_wire_c(const CircuitModelId& circuit_model_id, + void set_wire_c(const CircuitModelId& model_id, const float& c_val); - void set_wire_num_levels(const CircuitModelId& circuit_model_id, + void set_wire_num_levels(const CircuitModelId& model_id, const size_t& num_level); public: /* Public Mutators: builders */ - void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); - void link_port_circuit_model(const CircuitModelId& circuit_model_id); - void link_port_inv_circuit_model(const CircuitModelId& circuit_model_id); - void link_port_circuit_models(const CircuitModelId& circuit_model_id); - void link_buffer_circuit_model(const CircuitModelId& circuit_model_id); - void link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id); - void build_circuit_model_links(); - void build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); + void set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& model_name); + void link_port_model(const CircuitModelId& model_id); + void link_port_inv_model(const CircuitModelId& model_id); + void link_port_models(const CircuitModelId& model_id); + void link_buffer_model(const CircuitModelId& model_id); + void link_pass_gate_logic_model(const CircuitModelId& model_id); + void build_model_links(); + void build_model_timing_graph(const CircuitModelId& model_id); void build_timing_graphs(); public: /* Internal mutators: build timing graphs */ - void add_edge(const CircuitModelId& circuit_model_id, + void add_edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin); - void set_edge_delay(const CircuitModelId& circuit_model_id, + void set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, const enum spice_model_delay_type& delay_type, const float& delay_value); /* validate the circuit_edge_id */ - void set_timing_graph_delays(const CircuitModelId& circuit_model_id); + void set_timing_graph_delays(const CircuitModelId& model_id); public: /* Internal mutators: build fast look-ups */ - void build_circuit_model_lookup(); - void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); + void build_model_lookup(); + void build_model_port_lookup(const CircuitModelId& model_id); private: /* Internal invalidators/validators */ /* Validators */ - bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; - bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; - bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; - bool valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const; + bool valid_model_id(const CircuitModelId& model_id) const; + bool valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; + bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const; + bool valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const; bool valid_mux_const_input_value(const size_t& const_input_value) const; /* Invalidators */ - void invalidate_circuit_model_lookup() const; - void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; - void invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); + void invalidate_model_lookup() const; + void invalidate_model_port_lookup(const CircuitModelId& model_id) const; + void invalidate_model_timing_graph(const CircuitModelId& model_id); private: /* Internal data */ /* Fundamental information */ - vtr::vector circuit_model_ids_; - vtr::vector circuit_model_types_; - vtr::vector circuit_model_names_; - vtr::vector circuit_model_prefix_; - vtr::vector circuit_model_verilog_netlists_; - vtr::vector circuit_model_spice_netlists_; - vtr::vector circuit_model_is_default_; + vtr::vector model_ids_; + vtr::vector model_types_; + vtr::vector model_names_; + vtr::vector model_prefix_; + vtr::vector model_verilog_netlists_; + vtr::vector model_spice_netlists_; + vtr::vector model_is_default_; /* fast look-up for circuit models to categorize by types * [type][num_ids] * Important: we force the default circuit model in the first element for each type */ typedef std::vector> CircuitModelLookup; - mutable CircuitModelLookup circuit_model_lookup_; /* [circuit_model_type][circuit_model_ids] */ + mutable CircuitModelLookup model_lookup_; /* [model_type][model_ids] */ typedef std::vector>> CircuitModelPortLookup; - mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_id][port_type][port_ids] */ + mutable CircuitModelPortLookup model_port_lookup_; /* [model_id][port_type][port_ids] */ /* Verilog generator options */ vtr::vector dump_structural_verilog_; @@ -495,13 +479,13 @@ class CircuitLibrary { /* Buffer existence */ vtr::vector> buffer_existence_; - vtr::vector> buffer_circuit_model_names_; - vtr::vector> buffer_circuit_model_ids_; + vtr::vector> buffer_model_names_; + vtr::vector> buffer_model_ids_; vtr::vector> buffer_location_maps_; /* Pass-gate-related parameters */ - vtr::vector pass_gate_logic_circuit_model_names_; - vtr::vector pass_gate_logic_circuit_model_ids_; + vtr::vector pass_gate_logic_model_names_; + vtr::vector pass_gate_logic_model_ids_; /* Port information */ vtr::vector> port_ids_; @@ -517,10 +501,10 @@ class CircuitLibrary { vtr::vector> port_is_set_; vtr::vector> port_is_config_enable_; vtr::vector> port_is_prog_; - vtr::vector> port_circuit_model_names_; - vtr::vector> port_circuit_model_ids_; - vtr::vector> port_inv_circuit_model_names_; - vtr::vector> port_inv_circuit_model_ids_; + vtr::vector> port_model_names_; + vtr::vector> port_model_ids_; + vtr::vector> port_inv_model_names_; + vtr::vector> port_inv_model_ids_; vtr::vector> port_tri_state_maps_; vtr::vector> port_lut_frac_level_; vtr::vector>> port_lut_output_masks_; diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h new file mode 100644 index 000000000..522fbbfcc --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h @@ -0,0 +1,21 @@ +/************************************************************************ + * A header file for CircuitLibrary class, including critical data declaration + * Please include this file only for using any CircuitLibrary data structure + * Refer to circuit_library.h for more details + ***********************************************************************/ + +/************************************************************************ + * Create strong id for Circuit Models/Ports to avoid illegal type casting + ***********************************************************************/ +#include "vtr_strong_id.h" + +struct circuit_model_id_tag; +struct circuit_port_id_tag; +struct circuit_edge_id_tag; + +typedef vtr::StrongId CircuitModelId; +typedef vtr::StrongId CircuitPortId; +typedef vtr::StrongId CircuitEdgeId; + +/* Short declaration of class */ +class CircuitLibrary; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 17ebb718a..e6f400fb2 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1573,38 +1573,38 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m /* Go spice_model by spice_model */ for (int imodel = 0; imodel < num_spice_model; ++imodel) { /* Add a spice model to the circuit_lib */ - CircuitModelId model_id = circuit_lib.add_circuit_model(); + CircuitModelId model_id = circuit_lib.add_model(); /* Fill fundamental attributes */ /* Basic information*/ - circuit_lib.set_circuit_model_type(model_id, spice_models[imodel].type); + circuit_lib.set_model_type(model_id, spice_models[imodel].type); std::string name(spice_models[imodel].name); - circuit_lib.set_circuit_model_name(model_id, name); + circuit_lib.set_model_name(model_id, name); std::string prefix(spice_models[imodel].prefix); - circuit_lib.set_circuit_model_prefix(model_id, prefix); + circuit_lib.set_model_prefix(model_id, prefix); if (NULL != spice_models[imodel].verilog_netlist) { std::string verilog_netlist(spice_models[imodel].verilog_netlist); - circuit_lib.set_circuit_model_verilog_netlist(model_id, verilog_netlist); + circuit_lib.set_model_verilog_netlist(model_id, verilog_netlist); } if (NULL != spice_models[imodel].model_netlist) { std::string spice_netlist(spice_models[imodel].model_netlist); - circuit_lib.set_circuit_model_spice_netlist(model_id, spice_netlist); + circuit_lib.set_model_spice_netlist(model_id, spice_netlist); } - circuit_lib.set_circuit_model_is_default(model_id, 0 != spice_models[imodel].is_default); + circuit_lib.set_model_is_default(model_id, 0 != spice_models[imodel].is_default); /* Verilog generatioin options */ - circuit_lib.set_circuit_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog); + circuit_lib.set_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog); - circuit_lib.set_circuit_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map); + circuit_lib.set_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map); /* Design technology information */ - circuit_lib.set_circuit_model_design_tech_type(model_id, spice_models[imodel].design_tech); + circuit_lib.set_model_design_tech_type(model_id, spice_models[imodel].design_tech); - circuit_lib.set_circuit_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated); + circuit_lib.set_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated); /* Buffer linking information */ if (NULL != spice_models[imodel].input_buffer) { @@ -1612,28 +1612,28 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m if (NULL != spice_models[imodel].input_buffer->spice_model_name) { model_name = spice_models[imodel].input_buffer->spice_model_name; } - circuit_lib.set_circuit_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name); + circuit_lib.set_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name); } if (NULL != spice_models[imodel].output_buffer) { std::string model_name; if (NULL != spice_models[imodel].output_buffer->spice_model_name) { model_name = spice_models[imodel].output_buffer->spice_model_name; } - circuit_lib.set_circuit_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name); + circuit_lib.set_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name); } if (NULL != spice_models[imodel].lut_input_buffer) { std::string model_name; if (NULL != spice_models[imodel].lut_input_buffer->spice_model_name) { model_name = spice_models[imodel].lut_input_buffer->spice_model_name; } - circuit_lib.set_circuit_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name); + circuit_lib.set_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name); } if (NULL != spice_models[imodel].lut_input_inverter) { std::string model_name; if (NULL != spice_models[imodel].lut_input_inverter->spice_model_name) { model_name = spice_models[imodel].lut_input_inverter->spice_model_name; } - circuit_lib.set_circuit_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); + circuit_lib.set_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); } if ( (NULL != spice_models[imodel].lut_intermediate_buffer) && (1 == spice_models[imodel].lut_intermediate_buffer->exist) ) { @@ -1641,19 +1641,19 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) { model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name; } - circuit_lib.set_circuit_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name); + circuit_lib.set_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name); std::string model_location_map; if (NULL != spice_models[imodel].lut_intermediate_buffer->location_map) { model_location_map = spice_models[imodel].lut_intermediate_buffer->location_map; } - circuit_lib.set_circuit_model_lut_intermediate_buffer_location_map(model_id, model_location_map); + circuit_lib.set_model_lut_intermediate_buffer_location_map(model_id, model_location_map); } /* Pass-gate-logic linking information */ if (NULL != spice_models[imodel].pass_gate_logic) { std::string model_name(spice_models[imodel].pass_gate_logic->spice_model_name); - circuit_lib.set_circuit_model_pass_gate_logic(model_id, model_name); + circuit_lib.set_model_pass_gate_logic(model_id, model_name); } /* Buffer information */ @@ -1728,7 +1728,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m /* Ports */ for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) { - CircuitPortId port_id = circuit_lib.add_circuit_model_port(model_id); + CircuitPortId port_id = circuit_lib.add_model_port(model_id); /* Fill fundamental attributes */ circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type); @@ -1756,12 +1756,12 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m if (NULL != spice_models[imodel].ports[iport].spice_model_name) { std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name); - circuit_lib.set_port_circuit_model_name(model_id, port_id, port_model_name); + circuit_lib.set_port_model_name(model_id, port_id, port_model_name); } if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) { std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name); - circuit_lib.set_port_inv_circuit_model_name(model_id, port_id, port_inv_model_name); + circuit_lib.set_port_inv_model_name(model_id, port_id, port_inv_model_name); } if (NULL != spice_models[imodel].ports[iport].tri_state_map) { @@ -1786,7 +1786,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m } /* Build circuit_model links */ - circuit_lib.build_circuit_model_links(); + circuit_lib.build_model_links(); /* Build timing graph */ circuit_lib.build_timing_graphs(); diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 30a4c9b51..1312384c1 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -553,8 +553,8 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { /* Make sure this model is a MUX */ - VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); + VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); /* Make sure mux_size is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); @@ -594,7 +594,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); exit(1); } diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 29cb0e5ec..f7eb9932c 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -28,10 +28,10 @@ size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, /* Should be either MUX or LUT * LUTs do have an tree-like MUX, but there is no need for a constant input! */ - VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); + VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); - if (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) { + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { return mux_size; } @@ -147,7 +147,7 @@ MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llis /* Build a MUX graph for the model */ /* Find the circuit model id by the name */ - CircuitModelId circuit_model = circuit_lib.circuit_model(cur_spice_mux_model->spice_model->name); + CircuitModelId circuit_model = circuit_lib.model(cur_spice_mux_model->spice_model->name); mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size); /* Move on to the next*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index 3cdd35eb1..c8dd0b8c3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -81,31 +81,31 @@ CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, const CircuitLibrary& circuit_lib, const enum e_spice_model_type& model_type) { - CircuitModelId circuit_model = CIRCUIT_MODEL_OPEN_ID; + CircuitModelId circuit_model = CircuitModelId::INVALID(); /* If the circuit_model_name is not defined, we use the default*/ if (NULL == circuit_model_name) { - circuit_model = circuit_lib.default_circuit_model(model_type); + circuit_model = circuit_lib.default_model(model_type); } else { - circuit_model = circuit_lib.circuit_model(circuit_model_name); + circuit_model = circuit_lib.model(circuit_model_name); } /* Check the circuit model, we should have one! */ - if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { + if (CircuitModelId::INVALID() == circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s!\n", __FILE__, __LINE__, - circuit_lib.circuit_model_name(circuit_model).c_str()); + circuit_lib.model_name(circuit_model).c_str()); return circuit_model; /* Return here, no need to check the model_type */ } /* Check the type of circuit model, make sure it is the one we want */ - if (model_type != circuit_lib.circuit_model_type(circuit_model)) { + if (model_type != circuit_lib.model_type(circuit_model)) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Invalid type when trying to find circuit model called %s! Expect %s but found %s!\n", __FILE__, __LINE__, circuit_model_name, CIRCUIT_MODEL_TYPE_STRING[size_t(model_type)], - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))]); + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))]); } return circuit_model; @@ -267,11 +267,11 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, /* Initialize each port */ for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { - cur_pb_type->ports[iport].circuit_model_port = CIRCUIT_PORT_OPEN_ID; + cur_pb_type->ports[iport].circuit_model_port = CircuitPortId::INVALID(); } /* Return if SPICE_MODEL is NULL */ - if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { + if (CircuitModelId::INVALID() == circuit_model) { return 0; } @@ -290,11 +290,11 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, * but each pb_type_port should be mapped to a spice_model_port */ for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { - if (CIRCUIT_PORT_OPEN_ID == cur_pb_type->ports[iport].circuit_model_port) { + if (CircuitPortId::INVALID() == cur_pb_type->ports[iport].circuit_model_port) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, - circuit_lib.circuit_model_name(circuit_model).c_str()); + circuit_lib.model_name(circuit_model).c_str()); exit(1); } } @@ -319,7 +319,7 @@ void link_pb_type_interc_circuit_model_by_type(t_interconnect* cur_interc, circuit_lib, model_type); /* Check the circuit model, we should have one! */ - if (CIRCUIT_MODEL_OPEN_ID == cur_interc->circuit_model) { + if (CircuitModelId::INVALID() == cur_interc->circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Error in linking circuit model for interconnect(name %s)! Check [LINE%d] in architecture file)!\n", __FILE__, __LINE__, @@ -415,8 +415,8 @@ void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type, return; } /* Let's find a matched circuit model!*/ - cur_pb_type->circuit_model = circuit_lib.circuit_model(cur_pb_type->spice_model_name); - if (CIRCUIT_MODEL_OPEN_ID == cur_pb_type->circuit_model) { + cur_pb_type->circuit_model = circuit_lib.model(cur_pb_type->spice_model_name); + if (CircuitModelId::INVALID() == cur_pb_type->circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s, in pb_type(%s)!\n", __FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); @@ -428,14 +428,14 @@ void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type, } /* Otherwise, initialize it to be OPEN node */ - cur_pb_type->circuit_model = CIRCUIT_MODEL_OPEN_ID; + cur_pb_type->circuit_model = CircuitModelId::INVALID(); /* Traversal the hierarchy*/ for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { /* Task 1: Find the interconnections and match the spice_model */ for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { /* Initialize it to be OPEN node */ - cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CIRCUIT_MODEL_OPEN_ID; + cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CircuitModelId::INVALID(); link_pb_type_interc_circuit_model(&(cur_pb_type->modes[imode].interconnect[jinterc]), circuit_lib); } @@ -453,12 +453,12 @@ size_t check_circuit_model_structure_match_switch_inf(const t_switch_inf& target const CircuitLibrary& circuit_lib) { size_t num_err = 0; - VTR_ASSERT_SAFE(CIRCUIT_MODEL_OPEN_ID != target_switch_inf.circuit_model); + VTR_ASSERT_SAFE(CircuitModelId::INVALID() != target_switch_inf.circuit_model); if (target_switch_inf.structure != circuit_lib.mux_structure(target_switch_inf.circuit_model)) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) Mismatch in MUX structure between circuit model(%s, %s) and switch_inf(%s, %s)!\n", __FILE__, __LINE__, - circuit_lib.circuit_model_name(target_switch_inf.circuit_model).c_str(), + circuit_lib.model_name(target_switch_inf.circuit_model).c_str(), CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(circuit_lib.mux_structure(target_switch_inf.circuit_model))], target_switch_inf.name, CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(target_switch_inf.structure)]); @@ -494,7 +494,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_cb_switch; i++) { arch->cb_switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->cb_switches[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CIRCUIT_MODEL_OPEN_ID == arch->cb_switches[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->cb_switches[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", __FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); @@ -517,7 +517,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_switches; i++) { arch->Switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->Switches[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CIRCUIT_MODEL_OPEN_ID == arch->Switches[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->Switches[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", __FILE__, __LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); @@ -533,7 +533,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < routing_arch->num_switch; i++) { switch_inf[i].circuit_model = link_circuit_model_by_name_and_type(switch_inf[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CIRCUIT_MODEL_OPEN_ID == switch_inf[i].circuit_model) { + if (CircuitModelId::INVALID() == switch_inf[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", __FILE__, __LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); @@ -548,7 +548,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_segments; i++) { arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE); - if (CIRCUIT_MODEL_OPEN_ID == arch->Segments[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->Segments[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Segment(Length:%d) is undefined in circuit models!\n", __FILE__ ,__LINE__, @@ -563,7 +563,7 @@ void link_circuit_library_to_arch(t_arch* arch, arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_WIRE); /* Check SPICE model type */ - if (CIRCUIT_MODEL_OPEN_ID == arch->Directs[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->Directs[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n", __FILE__ ,__LINE__, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp index e5fe1cc66..f60cef851 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp @@ -64,7 +64,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp, default: vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); exit(1); } From 29104b6fa5595f876cf994cf8764777a30c61d50 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Aug 2019 15:14:28 -0600 Subject: [PATCH 088/482] rework on the circuit model ports and start prototyping mux Verilog generation --- .../libarchfpga/SRC/check_circuit_library.cpp | 8 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 878 +++++++++--------- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 240 +++-- .../libarchfpga/SRC/circuit_library_fwd.h | 5 + vpr7_x2p/libarchfpga/SRC/circuit_types.h | 1 + vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 42 +- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 36 +- vpr7_x2p/vpr/SRC/device/mux_graph.h | 8 +- .../fpga_x2p/base/link_arch_circuit_lib.cpp | 15 +- .../SRC/fpga_x2p/base/link_arch_circuit_lib.h | 1 - .../vpr/SRC/fpga_x2p/base/module_manager.h | 27 + .../SRC/fpga_x2p/base/module_manager_fwd.h | 18 + .../verilog/verilog_compact_netlist.c | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_global.h | 8 +- .../verilog/verilog_submodule_mux.cpp | 166 +++- .../fpga_x2p/verilog/verilog_submodule_mux.h | 1 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 39 + .../fpga_x2p/verilog/verilog_writer_utils.h | 15 + 21 files changed, 879 insertions(+), 642 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 2f51fa9bb..8fc98cc50 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -150,7 +150,7 @@ size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, size_t num_err = 0; for (const auto& port_type: port_types_to_check) { - if (0 == circuit_lib.ports_by_type(circuit_model, port_type).size()) { + if (0 == circuit_lib.model_ports_by_type(circuit_model, port_type).size()) { vpr_printf(TIO_MESSAGE_ERROR, "%s circuit model(name=%s) does not have %s port\n", CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], @@ -175,11 +175,11 @@ size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_ size_t num_err = 0; - if (port_size_to_check != circuit_lib.port_size(circuit_model, circuit_port)) { + if (port_size_to_check != circuit_lib.port_size(circuit_port)) { vpr_printf(TIO_MESSAGE_ERROR, "Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n", circuit_lib.model_name(circuit_model).c_str(), - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_model, circuit_port))], + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_port))], port_size_to_check); /* Incremental the counter for errors */ num_err++; @@ -202,7 +202,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& size_t num_err = 0; - std::vector ports = circuit_lib.ports_by_type(circuit_model, port_type_to_check, include_global_ports); + std::vector ports = circuit_lib.model_ports_by_type(circuit_model, port_type_to_check, include_global_ports); if (num_ports_to_check != ports.size()) { vpr_printf(TIO_MESSAGE_ERROR, "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index e39d81793..1e45f5b7f 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -55,12 +55,12 @@ CircuitLibrary::CircuitLibrary() { /************************************************************************ * Public Accessors : aggregates ***********************************************************************/ -CircuitLibrary::model_range CircuitLibrary::models() const { +CircuitLibrary::circuit_model_range CircuitLibrary::models() const { return vtr::make_range(model_ids_.begin(), model_ids_.end()); } -CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& model_id) const { - return vtr::make_range(port_ids_[model_id].begin(), port_ids_[model_id].end()); +CircuitLibrary::circuit_port_range CircuitLibrary::ports() const { + return vtr::make_range(port_ids_.begin(), port_ids_.end()); } /* Find circuit models in the same type (defined by users) and return a list of ids */ @@ -77,84 +77,6 @@ std::vector CircuitLibrary::models_by_type(const enum e_spice_mo return type_ids; } -/* Find the ports of a circuit model by a given type, return a list of qualified ports */ -std::vector CircuitLibrary::ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type) const { - std::vector port_ids; - for (const auto& port_id : ports(model_id)) { - /* We skip unmatched ports */ - if ( type != port_type(model_id, port_id) ) { - continue; - } - port_ids.push_back(port_id); - } - return port_ids; -} - -/* Find the ports of a circuit model by a given type, return a list of qualified ports - * with an option to include/exclude global ports - */ -std::vector CircuitLibrary::ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type, - const bool& include_global_port) const { - std::vector port_ids; - for (const auto& port_id : ports(model_id)) { - /* We skip unmatched ports */ - if ( type != port_type(model_id, port_id) ) { - continue; - } - /* We skip global ports if specified */ - if ( (false == include_global_port) - && (true == port_is_global(model_id, port_id)) ) { - continue; - } - port_ids.push_back(port_id); - } - return port_ids; -} - - -/* Create a vector for all the ports whose directionality is input - * This includes all the ports other than whose types are OUPUT or INOUT - */ -std::vector CircuitLibrary::input_ports(const CircuitModelId& model_id) const { - std::vector input_ports; - for (const auto& port_id : ports(model_id)) { - /* We skip output ports */ - if ( false == is_input_port(model_id, port_id) ) { - continue; - } - input_ports.push_back(port_id); - } - return input_ports; -} - -/* Create a vector for all the ports whose directionality is output - * This includes all the ports whose types are OUPUT or INOUT - */ -std::vector CircuitLibrary::output_ports(const CircuitModelId& model_id) const { - std::vector output_ports; - for (const auto& port_id : ports(model_id)) { - /* We skip input ports */ - if ( false == is_output_port(model_id, port_id) ) { - continue; - } - output_ports.push_back(port_id); - } - return output_ports; -} - -/* Create a vector for the pin indices, which is bounded by the size of a port - * Start from 0 and end to port_size - 1 - */ -std::vector CircuitLibrary::pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { - std::vector pin_range(port_size(model_id, circuit_port_id)); - /* Create a vector, with sequentially increasing numbers */ - std::iota(pin_range.begin(), pin_range.end(), 0); - return pin_range; -} - - /************************************************************************ * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ @@ -256,24 +178,24 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& model_id return buffer_existence_[model_id][LUT_INTER_BUFFER]; } -/* Find the type of pass-gate logic for a circuit model (recursive function) +/* Find the id of pass-gate circuit model * Two cases to be considered: * 1. this is a pass-gate circuit model, just find the data and return * 2. this circuit model includes a pass-gate, find the link to pass-gate circuit model and go recursively */ -enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& model_id) const { +CircuitModelId CircuitLibrary::pass_gate_logic_model(const CircuitModelId& model_id) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Return the data if this is a pass-gate circuit model */ if (SPICE_MODEL_PASSGATE == model_type(model_id)) { - return pass_gate_logic_types_[model_id]; + return model_ids_[model_id]; } /* Otherwise, we need to make sure this circuit model contains a pass-gate */ CircuitModelId pgl_model_id = pass_gate_logic_model_ids_[model_id]; VTR_ASSERT( CircuitModelId::INVALID() != pgl_model_id ); - return pass_gate_logic_type(pgl_model_id); + return pgl_model_id; } /* Return the multiplex structure of a circuit model */ @@ -325,41 +247,36 @@ size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& model_id) con return mux_const_input_values_[model_id]; } +/* Return the type of gate for a circuit model + * Only applicable for GATE circuit model + */ +enum e_spice_model_gate_type CircuitLibrary::gate_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT(SPICE_MODEL_GATE == model_type(model_id)); + return gate_types_[model_id]; +} + /************************************************************************ - * Public Accessors : Basic data query on Circuit Porst + * Public Accessors : Basic data query on Circuit models' Circuit Port ***********************************************************************/ -/* identify if this port is an input port */ -bool CircuitLibrary::is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { - /* validate the model_id and circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT != port_type(model_id, circuit_port_id)) - && (SPICE_MODEL_PORT_INOUT != port_type(model_id, circuit_port_id)) ); -} - -/* identify if this port is an output port */ -bool CircuitLibrary::is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { - /* validate the model_id and circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT == port_type(model_id, circuit_port_id)) - || (SPICE_MODEL_PORT_INOUT == port_type(model_id, circuit_port_id)) ); -} - /* Given a name and return the port id */ -CircuitPortId CircuitLibrary::port(const CircuitModelId& model_id, const std::string& name) const { +CircuitPortId CircuitLibrary::model_port(const CircuitModelId& model_id, const std::string& name) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Walk through the ports and try to find a matched name */ CircuitPortId ret = CircuitPortId::INVALID(); size_t num_found = 0; - for (auto port_id : ports(model_id)) { - if (0 != name.compare(port_prefix(model_id, port_id))) { - continue; /* Not the one, go to the next*/ + for (auto model_ports_by_type : model_port_lookup_[model_id]) { + for (auto port_id : model_ports_by_type) { + if (0 != name.compare(port_prefix(port_id))) { + continue; /* Not the one, go to the next*/ + } + ret = port_id; /* Find one */ + num_found++; } - ret = port_id; /* Find one */ - num_found++; } /* Make sure we will not find two ports with the same name */ VTR_ASSERT( (0 == num_found) || (1 == num_found) ); @@ -367,122 +284,259 @@ CircuitPortId CircuitLibrary::port(const CircuitModelId& model_id, const std::st } /* Access the type of a port of a circuit model */ -size_t CircuitLibrary::num_ports(const CircuitModelId& model_id) const { +size_t CircuitLibrary::num_model_ports(const CircuitModelId& model_id) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); - return port_ids_[model_id].size(); + /* Search the port look up and return a list */ + size_t num_of_ports = 0; + for (auto model_ports_by_type : model_port_lookup_[model_id]) { + num_of_ports += model_ports_by_type.size(); + } + return num_of_ports; } /* Access the type of a port of a circuit model * with an option to include/exclude global ports * when counting */ -size_t CircuitLibrary::num_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& port_type, - const bool& include_global_port) const { +size_t CircuitLibrary::num_model_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& port_type, + const bool& include_global_port) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); - return ports_by_type(model_id, port_type, include_global_port).size(); + /* Search the port look up */ + VTR_ASSERT(port_type < model_port_lookup_[model_id].size()); + size_t num_ports = 0; + for (auto port : model_port_lookup_[model_id][port_type]) { + /* By pass non-global ports if required by user */ + if ( (false == include_global_port) + && (true == port_is_global(port)) ) { + continue; + } + num_ports++; + } + + return num_ports; +} + +/* Find all the ports belong to a circuit model */ +std::vector CircuitLibrary::model_ports(const CircuitModelId& model_id) const { + /* validate the circuit_model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* Search the port look up and return a list */ + std::vector port_ids; + for (auto model_ports_by_type : model_port_lookup_[model_id]) { + for (auto port_id : model_ports_by_type) { + port_ids.push_back(port_id); + } + } + return port_ids; +} + +/* Recursively find all the global ports in the circuit model / sub circuit_model */ +std::vector CircuitLibrary::model_global_ports(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + + /* Search all the ports */ + std::vector global_ports; + for (auto port : model_ports(model_id)) { + /* By pass non-global ports*/ + if (false == port_is_global(port)) { + continue; + } + /* This is a global port, update global_ports */ + global_ports.push_back(port); + } + + return global_ports; +} + +/* Find the ports of a circuit model by a given type, return a list of qualified ports */ +std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& type) const { + std::vector port_ids; + for (const auto& port_id : model_ports(model_id)) { + /* We skip unmatched ports */ + if ( type != port_type(port_id) ) { + continue; + } + port_ids.push_back(port_id); + } + return port_ids; +} + +/* Find the ports of a circuit model by a given type, return a list of qualified ports + * with an option to include/exclude global ports + */ +std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& type, + const bool& include_global_port) const { + std::vector port_ids; + for (const auto& port_id : model_port_lookup_[model_id][type]) { + /* We skip unmatched ports */ + if ( type != port_type(port_id) ) { + continue; + } + /* We skip global ports if specified */ + if ( (false == include_global_port) + && (true == port_is_global(port_id)) ) { + continue; + } + port_ids.push_back(port_id); + } + return port_ids; +} + + +/* Create a vector for all the ports whose directionality is input + * This includes all the ports other than whose types are OUPUT or INOUT + */ +std::vector CircuitLibrary::model_input_ports(const CircuitModelId& model_id) const { + std::vector input_ports; + for (const auto& port_id : model_ports(model_id)) { + /* We skip output ports */ + if ( false == is_input_port(port_id) ) { + continue; + } + input_ports.push_back(port_id); + } + return input_ports; +} + +/* Create a vector for all the ports whose directionality is output + * This includes all the ports whose types are OUPUT or INOUT + */ +std::vector CircuitLibrary::model_output_ports(const CircuitModelId& model_id) const { + std::vector output_ports; + for (const auto& port_id : model_ports(model_id)) { + /* We skip input ports */ + if ( false == is_output_port(port_id) ) { + continue; + } + output_ports.push_back(port_id); + } + return output_ports; +} + +/* Create a vector for the pin indices, which is bounded by the size of a port + * Start from 0 and end to port_size - 1 + */ +std::vector CircuitLibrary::pins(const CircuitPortId& circuit_port_id) const { + std::vector pin_range(port_size(circuit_port_id)); + /* Create a vector, with sequentially increasing numbers */ + std::iota(pin_range.begin(), pin_range.end(), 0); + return pin_range; +} + + +/************************************************************************ + * Public Accessors : Basic data query on Circuit Port + ***********************************************************************/ + +/* identify if this port is an input port */ +bool CircuitLibrary::is_input_port(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ + return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_port_id)) + && (SPICE_MODEL_PORT_INOUT != port_type(circuit_port_id)) ); +} + +/* identify if this port is an output port */ +bool CircuitLibrary::is_output_port(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ + return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_port_id)) + || (SPICE_MODEL_PORT_INOUT == port_type(circuit_port_id)) ); } /* Access the type of a port of a circuit model */ -enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_types_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_types_[circuit_port_id]; } /* Access the type of a port of a circuit model */ -size_t CircuitLibrary::port_size(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +size_t CircuitLibrary::port_size(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_sizes_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_sizes_[circuit_port_id]; } /* Access the prefix of a port of a circuit model */ -std::string CircuitLibrary::port_prefix(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +std::string CircuitLibrary::port_prefix(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_prefix_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_prefix_[circuit_port_id]; } /* Access the lib_name of a port of a circuit model */ -std::string CircuitLibrary::port_lib_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +std::string CircuitLibrary::port_lib_name(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_lib_names_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_lib_names_[circuit_port_id]; } /* Access the inv_prefix of a port of a circuit model */ -std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +std::string CircuitLibrary::port_inv_prefix(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_inv_prefix_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_inv_prefix_[circuit_port_id]; } /* Return the default value of a port of a circuit model */ -size_t CircuitLibrary::port_default_value(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +size_t CircuitLibrary::port_default_value(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_default_values_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_default_values_[circuit_port_id]; } /* Return a flag if the port is used in mode-selection purpuse of a circuit model */ -bool CircuitLibrary::port_is_mode_select(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +bool CircuitLibrary::port_is_mode_select(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_is_mode_select_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_mode_select_[circuit_port_id]; } /* Return a flag if the port is a global one of a circuit model */ -bool CircuitLibrary::port_is_global(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +bool CircuitLibrary::port_is_global(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_is_global_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_global_[circuit_port_id]; } /* Return a flag if the port does a reset functionality in a circuit model */ -bool CircuitLibrary::port_is_reset(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +bool CircuitLibrary::port_is_reset(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_is_reset_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_reset_[circuit_port_id]; } /* Return a flag if the port does a set functionality in a circuit model */ -bool CircuitLibrary::port_is_set(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +bool CircuitLibrary::port_is_set(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_is_set_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_set_[circuit_port_id]; } /* Return a flag if the port enables a configuration in a circuit model */ -bool CircuitLibrary::port_is_config_enable(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_is_config_enable_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_config_enable_[circuit_port_id]; } /* Return a flag if the port is used during programming a FPGA in a circuit model */ -bool CircuitLibrary::port_is_prog(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id) const { +bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return port_is_prog_[model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_prog_[circuit_port_id]; } - /************************************************************************ * Public Accessors : Methods to find circuit model ***********************************************************************/ @@ -496,7 +550,7 @@ CircuitModelId CircuitLibrary::model(const char* name) const { CircuitModelId CircuitLibrary::model(const std::string& name) const { CircuitModelId ret = CircuitModelId::INVALID(); size_t num_found = 0; - for (model_string_iterator it = model_names_.begin(); + for (circuit_model_string_iterator it = model_names_.begin(); it != model_names_.end(); it++) { /* Bypass unmatched names */ @@ -525,18 +579,17 @@ CircuitModelId CircuitLibrary::default_model(const enum e_spice_model_type& type * Public Accessors: Timing graph ***********************************************************************/ /* Given the source and sink port information, find the edge connecting the two ports */ -CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& model_id, - const CircuitPortId& from_port, const size_t from_pin, +CircuitEdgeId CircuitLibrary::edge(const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin) { /* validate the circuit_pin_id */ - VTR_ASSERT(valid_circuit_pin_id(model_id, from_port, from_pin)); - VTR_ASSERT(valid_circuit_pin_id(model_id, to_port, to_pin)); + VTR_ASSERT(valid_circuit_pin_id(from_port, from_pin)); + VTR_ASSERT(valid_circuit_pin_id(to_port, to_pin)); /* Walk through the edge list until we find the one */ - for (auto edge : edge_ids_[model_id]) { - if ( (from_port == edge_src_port_ids_[model_id][edge]) - && (from_pin == edge_src_pin_ids_[model_id][edge]) - && (to_port == edge_sink_port_ids_[model_id][edge]) - && (to_pin == edge_sink_pin_ids_[model_id][edge]) ) { + for (auto edge : edge_ids_) { + if ( (from_port == edge_src_port_ids_[edge]) + && (from_pin == edge_src_pin_ids_[edge]) + && (to_port == edge_sink_port_ids_[edge]) + && (to_pin == edge_sink_pin_ids_[edge]) ) { return edge; } } @@ -548,7 +601,7 @@ CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& model_id, * Public Mutators ***********************************************************************/ /* Add a circuit model to the library, and return it Id */ -CircuitModelId CircuitLibrary::add_model() { +CircuitModelId CircuitLibrary::add_model(const enum e_spice_model_type& type) { /* Create a new id*/ CircuitModelId model_id = CircuitModelId(model_ids_.size()); /* Update the id list */ @@ -556,7 +609,7 @@ CircuitModelId CircuitLibrary::add_model() { /* Initialize other attributes */ /* Fundamental information */ - model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES); + model_types_.push_back(type); model_names_.emplace_back(); model_prefix_.emplace_back(); model_verilog_netlists_.emplace_back(); @@ -581,39 +634,6 @@ CircuitModelId CircuitLibrary::add_model() { pass_gate_logic_model_names_.emplace_back(); pass_gate_logic_model_ids_.emplace_back(); - /* Port information */ - port_ids_.emplace_back(); - port_types_.emplace_back(); - port_sizes_.emplace_back(); - port_prefix_.emplace_back(); - port_lib_names_.emplace_back(); - port_inv_prefix_.emplace_back(); - port_default_values_.emplace_back(); - port_is_mode_select_.emplace_back(); - port_is_global_.emplace_back(); - port_is_reset_.emplace_back(); - port_is_set_.emplace_back(); - port_is_config_enable_.emplace_back(); - port_is_prog_.emplace_back(); - port_model_names_.emplace_back(); - port_model_ids_.emplace_back(); - port_inv_model_names_.emplace_back(); - port_inv_model_ids_.emplace_back(); - port_tri_state_maps_.emplace_back(); - port_lut_frac_level_.emplace_back(); - port_lut_output_masks_.emplace_back(); - port_sram_orgz_.emplace_back(); - - /* Timing graphs */ - edge_ids_.emplace_back(); - port_in_edge_ids_.emplace_back(); - port_out_edge_ids_.emplace_back(); - edge_src_port_ids_.emplace_back(); - edge_src_pin_ids_.emplace_back(); - edge_sink_port_ids_.emplace_back(); - edge_sink_pin_ids_.emplace_back(); - edge_timing_info_.emplace_back(); - /* Delay information */ delay_types_.emplace_back(); delay_in_port_names_.emplace_back(); @@ -653,24 +673,10 @@ CircuitModelId CircuitLibrary::add_model() { wire_rc_.emplace_back(); wire_num_levels_.push_back(-1); - /* Update circuit port fast look-up */ - model_port_lookup_.emplace_back(); - - /* Invalidate fast look-up*/ - invalidate_model_lookup(); - - return model_id; -} - -/* Set the type of a Circuit Model */ -void CircuitLibrary::set_model_type(const CircuitModelId& model_id, - const enum e_spice_model_type& type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_types_[model_id] = type; /* Build the fast look-up for circuit models */ build_model_lookup(); - return; + + return model_id; } /* Set the name of a Circuit Model */ @@ -747,7 +753,7 @@ void CircuitLibrary::set_model_is_power_gated(const CircuitModelId& model_id, co /* Set input buffer information for the circuit model */ void CircuitLibrary::set_model_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { + const bool& existence, const std::string& model_name) { /* Just call the base function and give the proper type */ set_model_buffer(model_id, INPUT, existence, model_name); return; @@ -755,7 +761,7 @@ void CircuitLibrary::set_model_input_buffer(const CircuitModelId& model_id, /* Set output buffer information for the circuit model */ void CircuitLibrary::set_model_output_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { + const bool& existence, const std::string& model_name) { /* Just call the base function and give the proper type */ set_model_buffer(model_id, OUTPUT, existence, model_name); return; @@ -763,7 +769,7 @@ void CircuitLibrary::set_model_output_buffer(const CircuitModelId& model_id, /* Set input buffer information for the circuit model, only applicable to LUTs! */ void CircuitLibrary::set_model_lut_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { + const bool& existence, const std::string& model_name) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ @@ -775,7 +781,7 @@ void CircuitLibrary::set_model_lut_input_buffer(const CircuitModelId& model_id, /* Set input inverter information for the circuit model, only applicable to LUTs! */ void CircuitLibrary::set_model_lut_input_inverter(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { + const bool& existence, const std::string& model_name) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ @@ -787,7 +793,7 @@ void CircuitLibrary::set_model_lut_input_inverter(const CircuitModelId& model_id /* Set intermediate buffer information for the circuit model, only applicable to LUTs! */ void CircuitLibrary::set_model_lut_intermediate_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { + const bool& existence, const std::string& model_name) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ @@ -798,7 +804,7 @@ void CircuitLibrary::set_model_lut_intermediate_buffer(const CircuitModelId& mod } void CircuitLibrary::set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, - const std::string& location_map) { + const std::string& location_map) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); buffer_location_maps_[model_id][LUT_INTER_BUFFER] = location_map; @@ -815,248 +821,222 @@ void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id, c } /* Add a port to a circuit model */ -CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id) { +CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, + const enum e_spice_model_port_type& port_type) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Create a port id */ - CircuitPortId circuit_port_id = CircuitPortId(port_ids_[model_id].size()); + CircuitPortId circuit_port_id = CircuitPortId(port_ids_.size()); /* Update the id list */ - port_ids_[model_id].push_back(circuit_port_id); + port_ids_.push_back(circuit_port_id); /* Initialize other attributes */ - port_types_[model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); - port_sizes_[model_id].push_back(-1); - port_prefix_[model_id].emplace_back(); - port_lib_names_[model_id].emplace_back(); - port_inv_prefix_[model_id].emplace_back(); - port_default_values_[model_id].push_back(-1); - port_is_mode_select_[model_id].push_back(false); - port_is_global_[model_id].push_back(false); - port_is_reset_[model_id].push_back(false); - port_is_set_[model_id].push_back(false); - port_is_config_enable_[model_id].push_back(false); - port_is_prog_[model_id].push_back(false); - port_model_names_[model_id].emplace_back(); - port_model_ids_[model_id].push_back(CircuitModelId::INVALID()); - port_inv_model_names_[model_id].emplace_back(); - port_inv_model_ids_[model_id].push_back(CircuitModelId::INVALID()); - port_tri_state_maps_[model_id].emplace_back(); - port_lut_frac_level_[model_id].push_back(-1); - port_lut_output_masks_[model_id].emplace_back(); - port_sram_orgz_[model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); + port_model_ids_.push_back(model_id); + port_types_.push_back(port_type); + port_sizes_.push_back(-1); + port_prefix_.emplace_back(); + port_lib_names_.emplace_back(); + port_inv_prefix_.emplace_back(); + port_default_values_.push_back(-1); + port_is_mode_select_.push_back(false); + port_is_global_.push_back(false); + port_is_reset_.push_back(false); + port_is_set_.push_back(false); + port_is_config_enable_.push_back(false); + port_is_prog_.push_back(false); + port_tri_state_model_names_.emplace_back(); + port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); + port_inv_model_names_.emplace_back(); + port_inv_model_ids_.push_back(CircuitModelId::INVALID()); + port_tri_state_maps_.emplace_back(); + port_lut_frac_level_.push_back(-1); + port_lut_output_masks_.emplace_back(); + port_sram_orgz_.push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); /* For timing graphs */ - port_in_edge_ids_[model_id].emplace_back(); - port_out_edge_ids_[model_id].emplace_back(); + port_in_edge_ids_.emplace_back(); + port_out_edge_ids_.emplace_back(); + + /* Build the fast look-up for circuit model ports */ + build_model_port_lookup(); return circuit_port_id; } -/* Set the type for a port of a circuit model */ -void CircuitLibrary::set_port_type(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const enum e_spice_model_port_type& port_type) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_types_[model_id][circuit_port_id] = port_type; - /* Build the fast look-up for circuit model ports */ - build_model_port_lookup(model_id); - return; -} - /* Set the size for a port of a circuit model */ -void CircuitLibrary::set_port_size(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_size(const CircuitPortId& circuit_port_id, const size_t& port_size) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_sizes_[model_id][circuit_port_id] = port_size; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_sizes_[circuit_port_id] = port_size; return; } /* Set the prefix for a port of a circuit model */ -void CircuitLibrary::set_port_prefix(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_prefix(const CircuitPortId& circuit_port_id, const std::string& port_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_prefix_[model_id][circuit_port_id] = port_prefix; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_prefix_[circuit_port_id] = port_prefix; return; } /* Set the lib_name for a port of a circuit model */ -void CircuitLibrary::set_port_lib_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_lib_name(const CircuitPortId& circuit_port_id, const std::string& lib_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_lib_names_[model_id][circuit_port_id] = lib_name; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_lib_names_[circuit_port_id] = lib_name; return; } /* Set the inv_prefix for a port of a circuit model */ -void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_inv_prefix(const CircuitPortId& circuit_port_id, const std::string& inv_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_inv_prefix_[model_id][circuit_port_id] = inv_prefix; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_inv_prefix_[circuit_port_id] = inv_prefix; return; } /* Set the default value for a port of a circuit model */ -void CircuitLibrary::set_port_default_value(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_default_value(const CircuitPortId& circuit_port_id, const size_t& default_value) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_default_values_[model_id][circuit_port_id] = default_value; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_default_values_[circuit_port_id] = default_value; return; } /* Set the is_mode_select for a port of a circuit model */ -void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_is_mode_select(const CircuitPortId& circuit_port_id, const bool& is_mode_select) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_is_mode_select_[model_id][circuit_port_id] = is_mode_select; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_mode_select_[circuit_port_id] = is_mode_select; return; } /* Set the is_global for a port of a circuit model */ -void CircuitLibrary::set_port_is_global(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_is_global(const CircuitPortId& circuit_port_id, const bool& is_global) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_is_global_[model_id][circuit_port_id] = is_global; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_global_[circuit_port_id] = is_global; return; } /* Set the is_reset for a port of a circuit model */ -void CircuitLibrary::set_port_is_reset(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_is_reset(const CircuitPortId& circuit_port_id, const bool& is_reset) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_is_reset_[model_id][circuit_port_id] = is_reset; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_reset_[circuit_port_id] = is_reset; return; } /* Set the is_set for a port of a circuit model */ -void CircuitLibrary::set_port_is_set(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_is_set(const CircuitPortId& circuit_port_id, const bool& is_set) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_is_set_[model_id][circuit_port_id] = is_set; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_set_[circuit_port_id] = is_set; return; } /* Set the is_config_enable for a port of a circuit model */ -void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_is_config_enable_[model_id][circuit_port_id] = is_config_enable; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_config_enable_[circuit_port_id] = is_config_enable; return; } /* Set the is_prog for a port of a circuit model */ -void CircuitLibrary::set_port_is_prog(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_is_prog_[model_id][circuit_port_id] = is_prog; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_prog_[circuit_port_id] = is_prog; return; } /* Set the model_name for a port of a circuit model */ -void CircuitLibrary::set_port_model_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const std::string& model_name) { +void CircuitLibrary::set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, + const std::string& model_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_model_names_[model_id][circuit_port_id] = model_name; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_tri_state_model_names_[circuit_port_id] = model_name; return; } /* Set the model_id for a port of a circuit model */ -void CircuitLibrary::set_port_model_id(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const CircuitModelId& port_model_id) { +void CircuitLibrary::set_port_tri_state_model_id(const CircuitPortId& circuit_port_id, + const CircuitModelId& port_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_model_ids_[model_id][circuit_port_id] = port_model_id; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_tri_state_model_ids_[circuit_port_id] = port_model_id; return; } /* Set the inv_model_name for a port of a circuit model */ -void CircuitLibrary::set_port_inv_model_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const std::string& inv_model_name) { +void CircuitLibrary::set_port_inv_model_name(const CircuitPortId& circuit_port_id, + const std::string& inv_model_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_inv_model_names_[model_id][circuit_port_id] = inv_model_name; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_inv_model_names_[circuit_port_id] = inv_model_name; return; } /* Set the inv_model_id for a port of a circuit model */ -void CircuitLibrary::set_port_inv_model_id(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_model_id) { +void CircuitLibrary::set_port_inv_model_id(const CircuitPortId& circuit_port_id, + const CircuitModelId& inv_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_inv_model_ids_[model_id][circuit_port_id] = inv_model_id; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_inv_model_ids_[circuit_port_id] = inv_model_id; return; } /* Set the tri-state map for a port of a circuit model */ -void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_tri_state_map(const CircuitPortId& circuit_port_id, const std::string& tri_state_map) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - port_tri_state_maps_[model_id][circuit_port_id] = tri_state_map; + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_tri_state_maps_[circuit_port_id] = tri_state_map; return; } /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_lut_frac_level(const CircuitPortId& circuit_port_id, const size_t& lut_frac_level) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - port_lut_frac_level_[model_id][circuit_port_id] = lut_frac_level; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(port_model_ids_[circuit_port_id])); + port_lut_frac_level_[circuit_port_id] = lut_frac_level; return; } /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_lut_output_mask(const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - port_lut_output_masks_[model_id][circuit_port_id] = lut_output_masks; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(port_model_ids_[circuit_port_id])); + port_lut_output_masks_[circuit_port_id] = lut_output_masks; return; } /* Set the SRAM organization for a port of a circuit model, only applicable to SRAM ports */ -void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, +void CircuitLibrary::set_port_sram_orgz(const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); /* Make sure this is a SRAM port */ - VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(model_id, circuit_port_id)); - port_sram_orgz_[model_id][circuit_port_id] = sram_orgz; + VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(circuit_port_id)); + port_sram_orgz_[circuit_port_id] = sram_orgz; return; } @@ -1383,7 +1363,7 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& model_id, * If no, resize the vector and then assign values */ void CircuitLibrary::set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, - const bool& existence, const std::string& model_name) { + const bool& existence, const std::string& model_name) { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); /* Check the range of vector */ @@ -1405,16 +1385,14 @@ void CircuitLibrary::set_model_buffer(const CircuitModelId& model_id, const enum * We search the inv_model_name in the CircuitLibrary and * configure the port inv_model_id */ -void CircuitLibrary::link_port_model(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); +void CircuitLibrary::link_port_tri_state_model() { /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports(model_id)) { + for (auto& port_id : ports()) { /* Bypass empty name */ - if (true == port_model_names_[model_id][port_id].empty()) { + if (true == port_tri_state_model_names_[port_id].empty()) { continue; } - port_model_ids_[model_id][port_id] = model(port_model_names_[model_id][port_id]); + port_tri_state_model_ids_[port_id] = model(port_tri_state_model_names_[port_id]); } return; } @@ -1423,27 +1401,18 @@ void CircuitLibrary::link_port_model(const CircuitModelId& model_id) { * We search the inv_model_name in the CircuitLibrary and * configure the port inv_model_id */ -void CircuitLibrary::link_port_inv_model(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); +void CircuitLibrary::link_port_inv_model() { /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports(model_id)) { + for (auto& port_id : ports()) { /* Bypass empty name */ - if (true == port_inv_model_names_[model_id][port_id].empty()) { + if (true == port_inv_model_names_[port_id].empty()) { continue; } - port_inv_model_ids_[model_id][port_id] = model(port_inv_model_names_[model_id][port_id]); + port_inv_model_ids_[port_id] = model(port_inv_model_names_[port_id]); } return; } -/* Link all the circuit model ids for each port of a circuit model */ -void CircuitLibrary::link_port_models(const CircuitModelId& model_id) { - link_port_model(model_id); - link_port_inv_model(model_id); - return; -} - /* Link the buffer_model * We search the buffer_model_name in the CircuitLibrary and * configure the buffer_model_id @@ -1476,36 +1445,26 @@ void CircuitLibrary::link_pass_gate_logic_model(const CircuitModelId& model_id) return; } -/* Build the links for attributes of each model by searching the model_names */ -void CircuitLibrary::build_model_links() { - /* Walk through each circuit model, build links one by one */ - for (auto& model_id : models()) { - /* Build links for buffers, pass-gates model */ - link_buffer_model(model_id); - link_pass_gate_logic_model(model_id); - /* Build links for ports */ - link_port_models(model_id); - } - return; -} - /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* Now we start allocating a timing graph * Add outgoing edges for each input pin of the circuit model */ - for (auto& from_port_id : input_ports(model_id)) { + for (const auto& from_port_id : model_input_ports(model_id)) { /* Add edges for each input pin */ - for (auto& from_pin_id : pins(model_id, from_port_id)) { + for (const auto& from_pin_id : pins(from_port_id)) { /* We should walk through output pins here */ - for (auto& to_port_id : output_ports(model_id)) { - for (auto& to_pin_id : pins(model_id, to_port_id)) { + for (const auto& to_port_id : model_output_ports(model_id)) { + for (const auto& to_pin_id : pins(to_port_id)) { /* Skip self-loops */ if (from_port_id == to_port_id) { continue; } /* Add an edge to bridge the from_pin_id and to_pin_id */ - add_edge(model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); + add_edge(from_port_id, from_pin_id, to_port_id, to_pin_id); } } } @@ -1513,12 +1472,29 @@ void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { return; } +/************************************************************************ + * Public Mutators: builders and linkers + ***********************************************************************/ +/* Build the links for attributes of each model by searching the model_names */ +void CircuitLibrary::build_model_links() { + /* Walk through each circuit model, build links one by one */ + for (auto& model_id : models()) { + /* Build links for buffers, pass-gates model */ + link_buffer_model(model_id); + link_pass_gate_logic_model(model_id); + } + /* Build links for ports */ + link_port_tri_state_model(); + link_port_inv_model(); + return; +} + /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_timing_graphs() { + /* Free the timing graph if it already exists, we will rebuild one */ + invalidate_model_timing_graph(); /* Walk through each circuit model, build timing graph one by one */ for (auto& model_id : models()) { - /* Free the timing graph if it already exists, we will rebuild one */ - invalidate_model_timing_graph(model_id); build_model_timing_graph(model_id); /* Annotate timing information */ set_timing_graph_delays(model_id); @@ -1530,44 +1506,40 @@ void CircuitLibrary::build_timing_graphs() { * Internal mutators: build timing graphs ***********************************************************************/ /* Add an edge between two pins of two ports, and assign an default timing value */ -void CircuitLibrary::add_edge(const CircuitModelId& model_id, - const CircuitPortId& from_port, const size_t& from_pin, +void CircuitLibrary::add_edge(const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Create an edge in the edge id list */ - CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[model_id].size()); + CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_.size()); /* Expand the edge list */ - edge_ids_[model_id].push_back(edge_id); + edge_ids_.push_back(edge_id); /* Initialize other attributes */ /* Update the list of incoming edges for to_port */ /* Resize upon need */ - if (to_pin >= port_in_edge_ids_[model_id][to_port].size()) { - port_in_edge_ids_[model_id][to_port].resize(to_pin + 1); + if (to_pin >= port_in_edge_ids_[to_port].size()) { + port_in_edge_ids_[to_port].resize(to_pin + 1); } - port_in_edge_ids_[model_id][to_port][to_pin] = edge_id; + port_in_edge_ids_[to_port][to_pin] = edge_id; /* Update the list of outgoing edges for from_port */ /* Resize upon need */ - if (from_pin >= port_out_edge_ids_[model_id][from_port].size()) { - port_out_edge_ids_[model_id][from_port].resize(from_pin + 1); + if (from_pin >= port_out_edge_ids_[from_port].size()) { + port_out_edge_ids_[from_port].resize(from_pin + 1); } - port_out_edge_ids_[model_id][from_port][from_pin] = edge_id; + port_out_edge_ids_[from_port][from_pin] = edge_id; /* Update source ports and pins of the edge */ - edge_src_port_ids_[model_id].push_back(from_port); - edge_src_pin_ids_[model_id].push_back(from_pin); + edge_src_port_ids_.push_back(from_port); + edge_src_pin_ids_.push_back(from_pin); /* Update sink ports and pins of the edge */ - edge_sink_port_ids_[model_id].push_back(to_port); - edge_sink_pin_ids_[model_id].push_back(to_pin); + edge_sink_port_ids_.push_back(to_port); + edge_sink_pin_ids_.push_back(to_pin); /* Give a default value for timing values */ std::vector timing_info(NUM_CIRCUIT_MODEL_DELAY_TYPES, 0); - edge_timing_info_[model_id].push_back(timing_info); + edge_timing_info_.push_back(timing_info); return; } @@ -1577,10 +1549,10 @@ void CircuitLibrary::set_edge_delay(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const float& delay_value) { /* validate the circuit_edge_id */ - VTR_ASSERT(valid_circuit_edge_id(model_id, circuit_edge_id)); + VTR_ASSERT(valid_circuit_edge_id(circuit_edge_id)); VTR_ASSERT(valid_delay_type(model_id, delay_type)); - edge_timing_info_[model_id][circuit_edge_id][size_t(delay_type)] = delay_value; + edge_timing_info_[circuit_edge_id][size_t(delay_type)] = delay_value; return; } @@ -1604,22 +1576,22 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& model_id) { /* Check each element */ for (auto& port_info : input_ports) { /* Try to find a port by the given name */ - CircuitPortId port_id = port(model_id, port_info.get_name()); + CircuitPortId port_id = model_port(model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ VTR_ASSERT(CircuitPortId::INVALID() != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as */ - size_t port_width = port_size(model_id, port_id); + size_t port_width = port_size(port_id); port_info.set_width(port_width); } else { VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(port_id, port_info.get_lsb())); /* This must be an input port! */ - VTR_ASSERT(true == is_input_port(model_id, port_id)); + VTR_ASSERT(true == is_input_port(port_id)); /* Push to */ input_port_ids.push_back(port_id); input_pin_ids.push_back(port_info.get_lsb()); @@ -1633,22 +1605,22 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& model_id) { /* Check each element */ for (auto& port_info : output_ports) { /* Try to find a port by the given name */ - CircuitPortId port_id = port(model_id, port_info.get_name()); + CircuitPortId port_id = model_port(model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ VTR_ASSERT(CircuitPortId::INVALID() != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as */ - size_t port_width = port_size(model_id, port_id); + size_t port_width = port_size(port_id); port_info.set_width(port_width); } else { VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(port_id, port_info.get_lsb())); /* This must be an output port! */ - VTR_ASSERT(true == is_output_port(model_id, port_id)); + VTR_ASSERT(true == is_output_port(port_id)); /* Push to */ output_port_ids.push_back(port_id); output_pin_ids.push_back(port_info.get_lsb()); @@ -1667,11 +1639,10 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& model_id) { for (size_t i = 0; i < port_delay_parser.height(); ++i) { for (size_t j = 0; j < port_delay_parser.width(); ++j) { float delay_value = port_delay_parser.delay(i, j); - CircuitEdgeId edge_id = edge(model_id, - input_port_ids[j], input_pin_ids[j], + CircuitEdgeId edge_id = edge(input_port_ids[j], input_pin_ids[j], output_port_ids[i], output_pin_ids[i]); /* make sure we have an valid edge_id */ - VTR_ASSERT(true == valid_circuit_edge_id(model_id, edge_id)); + VTR_ASSERT(true == valid_circuit_edge_id(edge_id)); set_edge_delay(model_id, edge_id, delay_type, delay_value); } @@ -1717,14 +1688,19 @@ void CircuitLibrary::build_model_lookup() { } /* Build fast look-up for circuit model ports */ -void CircuitLibrary::build_model_port_lookup(const CircuitModelId& model_id) { +void CircuitLibrary::build_model_port_lookup() { + /* For all the ports in the list, categorize by model_id and port_type */ /* invalidate fast look-up */ - invalidate_model_port_lookup(model_id); + invalidate_model_port_lookup(); /* Classify circuit models by type */ - model_port_lookup_[size_t(model_id)].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + model_port_lookup_.resize(model_ids_.size()); + for (const auto& model_id : model_ids_) { + model_port_lookup_[model_id].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + } /* Walk through models and categorize */ - for (auto& port_id : port_ids_[model_id]) { - model_port_lookup_[size_t(model_id)][port_type(model_id, port_id)].push_back(port_id); + for (const auto& port : port_ids_) { + CircuitModelId model_id = port_model_ids_[port]; + model_port_lookup_[model_id][port_type(port)].push_back(port); } return; } @@ -1737,16 +1713,14 @@ bool CircuitLibrary::valid_model_id(const CircuitModelId& model_id) const { return ( size_t(model_id) < model_ids_.size() ) && ( model_id == model_ids_[model_id] ); } -bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return ( size_t(circuit_port_id) < port_ids_[model_id].size() ) && ( circuit_port_id == port_ids_[model_id][circuit_port_id] ); +bool CircuitLibrary::valid_circuit_port_id(const CircuitPortId& circuit_port_id) const { + return ( size_t(circuit_port_id) < port_ids_.size() ) && ( circuit_port_id == port_ids_[circuit_port_id] ); } -bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { +bool CircuitLibrary::valid_circuit_pin_id(const CircuitPortId& circuit_port_id, const size_t& pin_id) const { /* validate the model_id */ - VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); - return ( size_t(pin_id) < port_size(model_id, circuit_port_id) ); + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return ( size_t(pin_id) < port_size(circuit_port_id) ); } bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const { @@ -1755,10 +1729,8 @@ bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum return ( size_t(delay_type) < delay_types_[model_id].size() ) && ( delay_type == delay_types_[model_id][size_t(delay_type)] ); } -bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return ( size_t(circuit_edge_id) < edge_ids_[model_id].size() ) && ( circuit_edge_id == edge_ids_[model_id][circuit_edge_id] ); +bool CircuitLibrary::valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const { + return ( size_t(circuit_edge_id) < edge_ids_.size() ) && ( circuit_edge_id == edge_ids_[circuit_edge_id] ); } /* Validate the value of constant input @@ -1781,31 +1753,27 @@ void CircuitLibrary::invalidate_model_lookup() const { } /* Empty fast lookup for circuit ports for a model */ -void CircuitLibrary::invalidate_model_port_lookup(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_port_lookup_[size_t(model_id)].clear(); +void CircuitLibrary::invalidate_model_port_lookup() const { + model_port_lookup_.clear(); return; } /* Clear all the data structure related to the timing graph */ -void CircuitLibrary::invalidate_model_timing_graph(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - edge_ids_[model_id].clear(); +void CircuitLibrary::invalidate_model_timing_graph() { + edge_ids_.clear(); - for (const auto& port_id : ports(model_id)) { - port_in_edge_ids_[model_id][port_id].clear(); - port_out_edge_ids_[model_id][port_id].clear(); + for (const auto& port_id : ports()) { + port_in_edge_ids_[port_id].clear(); + port_out_edge_ids_[port_id].clear(); } - edge_src_port_ids_[model_id].clear(); - edge_src_pin_ids_[model_id].clear(); + edge_src_port_ids_.clear(); + edge_src_pin_ids_.clear(); - edge_sink_port_ids_[model_id].clear(); - edge_sink_pin_ids_[model_id].clear(); + edge_sink_port_ids_.clear(); + edge_sink_pin_ids_.clear(); - edge_timing_info_[model_id].clear(); + edge_timing_info_.clear(); return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index a74429347..72172bf30 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -102,6 +102,7 @@ * * ------ Port information ------ * 1. port_ids_: unique id of ports belonging to a circuit model + * 1. port_model_ids_: unique id of the parent circuit model for the port * 2. port_types_: types of ports belonging to a circuit model * 3. port_sizes_: width of ports belonging to a circuit model * 4. port_prefix_: prefix of a port when instance of a circuit model @@ -113,8 +114,8 @@ * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_model_name: the name of circuit model linked to the port - * 14. port_model_ids_: the Id of circuit model linked to the port + * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port * 15. port_inv_model_names_: the name of inverter circuit model linked to the port * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port @@ -187,12 +188,12 @@ ***********************************************************************/ class CircuitLibrary { public: /* Types */ - typedef vtr::vector::const_iterator model_iterator; - typedef vtr::vector::const_iterator model_string_iterator; + typedef vtr::vector::const_iterator circuit_model_iterator; + typedef vtr::vector::const_iterator circuit_model_string_iterator; typedef vtr::vector::const_iterator circuit_port_iterator; typedef vtr::vector::const_iterator circuit_edge_iterator; /* Create range */ - typedef vtr::Range model_range; + typedef vtr::Range circuit_model_range; typedef vtr::Range circuit_port_range; typedef vtr::Range circuit_edge_range; /* local enumeration for buffer existence */ @@ -202,14 +203,9 @@ class CircuitLibrary { public: /* Constructors */ CircuitLibrary(); public: /* Accessors: aggregates */ - model_range models() const; - circuit_port_range ports(const CircuitModelId& model_id) const; + circuit_model_range models() const; + circuit_port_range ports() const; std::vector models_by_type(const enum e_spice_model_type& type) const; - std::vector ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; - std::vector ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - std::vector input_ports(const CircuitModelId& model_id) const; - std::vector output_ports(const CircuitModelId& model_id) const; - std::vector pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Basic data query on Circuit Models*/ size_t num_models() const; enum e_spice_model_type model_type(const CircuitModelId& model_id) const; @@ -225,41 +221,48 @@ class CircuitLibrary { bool is_input_buffered(const CircuitModelId& model_id) const; bool is_output_buffered(const CircuitModelId& model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; - enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; + CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const; size_t mux_num_levels(const CircuitModelId& model_id) const; bool mux_add_const_input(const CircuitModelId& model_id) const; size_t mux_const_input_value(const CircuitModelId& model_id) const; + enum e_spice_model_gate_type gate_type(const CircuitModelId& model_id) const; + public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ + CircuitPortId model_port(const CircuitModelId& model_id, const std::string& name) const; + size_t num_model_ports(const CircuitModelId& model_id) const; + size_t num_model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; + std::vector model_ports(const CircuitModelId& model_id) const; + std::vector model_global_ports(const CircuitModelId& model_id) const; + std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; + std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; + std::vector model_input_ports(const CircuitModelId& model_id) const; + std::vector model_output_ports(const CircuitModelId& model_id) const; + std::vector pins(const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ - bool is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - CircuitPortId port(const CircuitModelId& model_id, const std::string& name) const; - size_t num_ports(const CircuitModelId& model_id) const; - size_t num_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - enum e_spice_model_port_type port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - size_t port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - std::string port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - std::string port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - std::string port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - size_t port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool is_input_port(const CircuitPortId& circuit_port_id) const; + bool is_output_port(const CircuitPortId& circuit_port_id) const; + enum e_spice_model_port_type port_type(const CircuitPortId& circuit_port_id) const; + size_t port_size(const CircuitPortId& circuit_port_id) const; + std::string port_prefix(const CircuitPortId& circuit_port_id) const; + std::string port_lib_name(const CircuitPortId& circuit_port_id) const; + std::string port_inv_prefix(const CircuitPortId& circuit_port_id) const; + size_t port_default_value(const CircuitPortId& circuit_port_id) const; + bool port_is_mode_select(const CircuitPortId& circuit_port_id) const; + bool port_is_global(const CircuitPortId& circuit_port_id) const; + bool port_is_reset(const CircuitPortId& circuit_port_id) const; + bool port_is_set(const CircuitPortId& circuit_port_id) const; + bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; + bool port_is_prog(const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Methods to find circuit model */ CircuitModelId model(const char* name) const; CircuitModelId model(const std::string& name) const; CircuitModelId default_model(const enum e_spice_model_type& type) const; public: /* Public Accessors: Timing graph */ - CircuitEdgeId edge(const CircuitModelId& model_id, - const CircuitPortId& from_port, const size_t from_pin, + CircuitEdgeId edge(const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin); public: /* Public Mutators */ - CircuitModelId add_model(); + CircuitModelId add_model(const enum e_spice_model_type& type); /* Fundamental information */ - void set_model_type(const CircuitModelId& model_id, const enum e_spice_model_type& type); void set_model_name(const CircuitModelId& model_id, const std::string& name); void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix); void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist); @@ -273,80 +276,59 @@ class CircuitLibrary { void set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated); /* Buffer existence */ void set_model_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); + const bool& existence, const std::string& model_name); void set_model_output_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); + const bool& existence, const std::string& model_name); void set_model_lut_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); + const bool& existence, const std::string& model_name); void set_model_lut_input_inverter(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); + const bool& existence, const std::string& model_name); void set_model_lut_intermediate_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); + const bool& existence, const std::string& model_name); void set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, - const std::string& location_map); + const std::string& location_map); /* Pass-gate-related parameters */ void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name); /* Port information */ - CircuitPortId add_model_port(const CircuitModelId& model_id); - void set_port_type(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const enum e_spice_model_port_type& port_type); - void set_port_size(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + CircuitPortId add_model_port(const CircuitModelId& model_id, + const enum e_spice_model_port_type& port_type); + void set_port_size(const CircuitPortId& circuit_port_id, const size_t& port_size); - void set_port_prefix(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_prefix(const CircuitPortId& circuit_port_id, const std::string& port_prefix); - void set_port_lib_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_lib_name(const CircuitPortId& circuit_port_id, const std::string& lib_name); - void set_port_inv_prefix(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_inv_prefix(const CircuitPortId& circuit_port_id, const std::string& inv_prefix); - void set_port_default_value(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_default_value(const CircuitPortId& circuit_port_id, const size_t& default_val); - void set_port_is_mode_select(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_is_mode_select(const CircuitPortId& circuit_port_id, const bool& is_mode_select); - void set_port_is_global(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_is_global(const CircuitPortId& circuit_port_id, const bool& is_global); - void set_port_is_reset(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_is_reset(const CircuitPortId& circuit_port_id, const bool& is_reset); - void set_port_is_set(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_is_set(const CircuitPortId& circuit_port_id, const bool& is_set); - void set_port_is_config_enable(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); - void set_port_is_prog(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); - void set_port_model_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const std::string& model_name); - void set_port_model_id(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const CircuitModelId& port_model_id); - void set_port_inv_model_name(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const std::string& inv_model_name); - void set_port_inv_model_id(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_model_id); - void set_port_tri_state_map(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, + const std::string& model_name); + void set_port_tri_state_model_id(const CircuitPortId& circuit_port_id, + const CircuitModelId& port_model_id); + void set_port_inv_model_name(const CircuitPortId& circuit_port_id, + const std::string& inv_model_name); + void set_port_inv_model_id(const CircuitPortId& circuit_port_id, + const CircuitModelId& inv_model_id); + void set_port_tri_state_map(const CircuitPortId& circuit_port_id, const std::string& tri_state_map); - void set_port_lut_frac_level(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_lut_frac_level(const CircuitPortId& circuit_port_id, const size_t& lut_frac_level); - void set_port_lut_output_mask(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_lut_output_mask(const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks); - void set_port_sram_orgz(const CircuitModelId& model_id, - const CircuitPortId& circuit_port_id, + void set_port_sram_orgz(const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz); /* Delay information */ void add_delay_info(const CircuitModelId& model_id, @@ -415,19 +397,18 @@ class CircuitLibrary { const float& c_val); void set_wire_num_levels(const CircuitModelId& model_id, const size_t& num_level); - public: /* Public Mutators: builders */ + private: /* Private Mutators: builders */ void set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& model_name); - void link_port_model(const CircuitModelId& model_id); - void link_port_inv_model(const CircuitModelId& model_id); - void link_port_models(const CircuitModelId& model_id); + void link_port_tri_state_model(); + void link_port_inv_model(); void link_buffer_model(const CircuitModelId& model_id); void link_pass_gate_logic_model(const CircuitModelId& model_id); - void build_model_links(); void build_model_timing_graph(const CircuitModelId& model_id); + public: /* Public Mutators: builders */ + void build_model_links(); void build_timing_graphs(); public: /* Internal mutators: build timing graphs */ - void add_edge(const CircuitModelId& model_id, - const CircuitPortId& from_port, const size_t& from_pin, + void add_edge(const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin); void set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, @@ -437,19 +418,19 @@ class CircuitLibrary { void set_timing_graph_delays(const CircuitModelId& model_id); public: /* Internal mutators: build fast look-ups */ void build_model_lookup(); - void build_model_port_lookup(const CircuitModelId& model_id); + void build_model_port_lookup(); private: /* Internal invalidators/validators */ /* Validators */ bool valid_model_id(const CircuitModelId& model_id) const; - bool valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; - bool valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; + bool valid_circuit_port_id(const CircuitPortId& circuit_port_id) const; + bool valid_circuit_pin_id(const CircuitPortId& circuit_port_id, const size_t& pin_id) const; bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const; - bool valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const; + bool valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const; bool valid_mux_const_input_value(const size_t& const_input_value) const; /* Invalidators */ void invalidate_model_lookup() const; - void invalidate_model_port_lookup(const CircuitModelId& model_id) const; - void invalidate_model_timing_graph(const CircuitModelId& model_id); + void invalidate_model_port_lookup() const; + void invalidate_model_timing_graph(); private: /* Internal data */ /* Fundamental information */ vtr::vector model_ids_; @@ -466,7 +447,7 @@ class CircuitLibrary { */ typedef std::vector> CircuitModelLookup; mutable CircuitModelLookup model_lookup_; /* [model_type][model_ids] */ - typedef std::vector>> CircuitModelPortLookup; + typedef vtr::vector>> CircuitModelPortLookup; mutable CircuitModelPortLookup model_port_lookup_; /* [model_id][port_type][port_ids] */ /* Verilog generator options */ @@ -488,37 +469,38 @@ class CircuitLibrary { vtr::vector pass_gate_logic_model_ids_; /* Port information */ - vtr::vector> port_ids_; - vtr::vector> port_types_; - vtr::vector> port_sizes_; - vtr::vector> port_prefix_; - vtr::vector> port_lib_names_; - vtr::vector> port_inv_prefix_; - vtr::vector> port_default_values_; - vtr::vector> port_is_mode_select_; - vtr::vector> port_is_global_; - vtr::vector> port_is_reset_; - vtr::vector> port_is_set_; - vtr::vector> port_is_config_enable_; - vtr::vector> port_is_prog_; - vtr::vector> port_model_names_; - vtr::vector> port_model_ids_; - vtr::vector> port_inv_model_names_; - vtr::vector> port_inv_model_ids_; - vtr::vector> port_tri_state_maps_; - vtr::vector> port_lut_frac_level_; - vtr::vector>> port_lut_output_masks_; - vtr::vector> port_sram_orgz_; + vtr::vector port_ids_; + vtr::vector port_model_ids_; + vtr::vector port_types_; + vtr::vector port_sizes_; + vtr::vector port_prefix_; + vtr::vector port_lib_names_; + vtr::vector port_inv_prefix_; + vtr::vector port_default_values_; + vtr::vector port_is_mode_select_; + vtr::vector port_is_global_; + vtr::vector port_is_reset_; + vtr::vector port_is_set_; + vtr::vector port_is_config_enable_; + vtr::vector port_is_prog_; + vtr::vector port_tri_state_model_names_; + vtr::vector port_tri_state_model_ids_; + vtr::vector port_inv_model_names_; + vtr::vector port_inv_model_ids_; + vtr::vector port_tri_state_maps_; + vtr::vector port_lut_frac_level_; + vtr::vector> port_lut_output_masks_; + vtr::vector port_sram_orgz_; /* Timing graphs */ - vtr::vector> edge_ids_; - vtr::vector>> port_in_edge_ids_; - vtr::vector>> port_out_edge_ids_; - vtr::vector> edge_src_port_ids_; - vtr::vector> edge_src_pin_ids_; - vtr::vector> edge_sink_port_ids_; - vtr::vector> edge_sink_pin_ids_; - vtr::vector>> edge_timing_info_; /* x0 => trise, x1 => tfall */ + vtr::vector edge_ids_; + vtr::vector> port_in_edge_ids_; + vtr::vector> port_out_edge_ids_; + vtr::vector edge_src_port_ids_; + vtr::vector edge_src_pin_ids_; + vtr::vector edge_sink_port_ids_; + vtr::vector edge_sink_pin_ids_; + vtr::vector> edge_timing_info_; /* x0 => trise, x1 => tfall */ /* Delay information */ vtr::vector> delay_types_; diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h index 522fbbfcc..cef4fc4a0 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h @@ -7,6 +7,9 @@ /************************************************************************ * Create strong id for Circuit Models/Ports to avoid illegal type casting ***********************************************************************/ +#ifndef CIRCUIT_LIBRARY_FWD_H +#define CIRCUIT_LIBRARY_FWD_H + #include "vtr_strong_id.h" struct circuit_model_id_tag; @@ -19,3 +22,5 @@ typedef vtr::StrongId CircuitEdgeId; /* Short declaration of class */ class CircuitLibrary; + +#endif diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/circuit_types.h index eff20f141..92e8b1c61 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_types.h @@ -102,6 +102,7 @@ enum e_spice_model_pass_gate_logic_type { SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR, SPICE_MODEL_PASS_GATE_RRAM, /* RRAM can be treated as a special type of pass-gate logic */ + SPICE_MODEL_PASS_GATE_STDCELL, /* Standard cell as a special type of pass-gate logic */ NUM_CIRCUIT_MODEL_PASS_GATE_TYPES }; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index e6f400fb2..e59ebcaab 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1573,11 +1573,9 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m /* Go spice_model by spice_model */ for (int imodel = 0; imodel < num_spice_model; ++imodel) { /* Add a spice model to the circuit_lib */ - CircuitModelId model_id = circuit_lib.add_model(); + CircuitModelId model_id = circuit_lib.add_model(spice_models[imodel].type); /* Fill fundamental attributes */ /* Basic information*/ - circuit_lib.set_model_type(model_id, spice_models[imodel].type); - std::string name(spice_models[imodel].name); circuit_lib.set_model_name(model_id, name); @@ -1728,59 +1726,57 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m /* Ports */ for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) { - CircuitPortId port_id = circuit_lib.add_model_port(model_id); + CircuitPortId port_id = circuit_lib.add_model_port(model_id, spice_models[imodel].ports[iport].type); /* Fill fundamental attributes */ - circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type); - - circuit_lib.set_port_size(model_id, port_id, spice_models[imodel].ports[iport].size); + circuit_lib.set_port_size(port_id, spice_models[imodel].ports[iport].size); std::string port_prefix(spice_models[imodel].ports[iport].prefix); - circuit_lib.set_port_prefix(model_id, port_id, port_prefix); + circuit_lib.set_port_prefix(port_id, port_prefix); std::string port_lib_name(spice_models[imodel].ports[iport].lib_name); - circuit_lib.set_port_lib_name(model_id, port_id, port_lib_name); + circuit_lib.set_port_lib_name(port_id, port_lib_name); if (NULL != spice_models[imodel].ports[iport].inv_prefix) { std::string port_inv_prefix(spice_models[imodel].ports[iport].inv_prefix); - circuit_lib.set_port_inv_prefix(model_id, port_id, port_inv_prefix); + circuit_lib.set_port_inv_prefix(port_id, port_inv_prefix); } - circuit_lib.set_port_default_value(model_id, port_id, spice_models[imodel].ports[iport].default_val); + circuit_lib.set_port_default_value(port_id, spice_models[imodel].ports[iport].default_val); - circuit_lib.set_port_is_mode_select(model_id, port_id, TRUE == spice_models[imodel].ports[iport].mode_select); - circuit_lib.set_port_is_global(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_global); - circuit_lib.set_port_is_reset(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_reset); - circuit_lib.set_port_is_set(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_set); - circuit_lib.set_port_is_config_enable(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_config_enable); - circuit_lib.set_port_is_prog(model_id, port_id, TRUE == spice_models[imodel].ports[iport].is_prog); + circuit_lib.set_port_is_mode_select(port_id, TRUE == spice_models[imodel].ports[iport].mode_select); + circuit_lib.set_port_is_global(port_id, TRUE == spice_models[imodel].ports[iport].is_global); + circuit_lib.set_port_is_reset(port_id, TRUE == spice_models[imodel].ports[iport].is_reset); + circuit_lib.set_port_is_set(port_id, TRUE == spice_models[imodel].ports[iport].is_set); + circuit_lib.set_port_is_config_enable(port_id, TRUE == spice_models[imodel].ports[iport].is_config_enable); + circuit_lib.set_port_is_prog(port_id, TRUE == spice_models[imodel].ports[iport].is_prog); if (NULL != spice_models[imodel].ports[iport].spice_model_name) { std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name); - circuit_lib.set_port_model_name(model_id, port_id, port_model_name); + circuit_lib.set_port_tri_state_model_name(port_id, port_model_name); } if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) { std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name); - circuit_lib.set_port_inv_model_name(model_id, port_id, port_inv_model_name); + circuit_lib.set_port_inv_model_name(port_id, port_inv_model_name); } if (NULL != spice_models[imodel].ports[iport].tri_state_map) { std::string port_tri_state_map(spice_models[imodel].ports[iport].tri_state_map); - circuit_lib.set_port_tri_state_map(model_id, port_id, port_tri_state_map); + circuit_lib.set_port_tri_state_map(port_id, port_tri_state_map); } if (SPICE_MODEL_LUT == spice_models[imodel].type) { - circuit_lib.set_port_lut_frac_level(model_id, port_id, spice_models[imodel].ports[iport].lut_frac_level); + circuit_lib.set_port_lut_frac_level(port_id, spice_models[imodel].ports[iport].lut_frac_level); std::vector port_lut_output_mask; for (int ipin = 0; ipin < spice_models[imodel].ports[iport].size; ++ipin) { port_lut_output_mask.push_back(spice_models[imodel].ports[iport].lut_output_mask[ipin]); } - circuit_lib.set_port_lut_output_mask(model_id, port_id, port_lut_output_mask); + circuit_lib.set_port_lut_output_mask(port_id, port_lut_output_mask); } if (SPICE_MODEL_PORT_SRAM == spice_models[imodel].ports[iport].type) { - circuit_lib.set_port_sram_orgz(model_id, port_id, spice_models[imodel].ports[iport].organization); + circuit_lib.set_port_sram_orgz(port_id, spice_models[imodel].ports[iport].organization); } } } diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 1312384c1..70446bbe4 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -67,6 +67,19 @@ size_t MuxGraph::num_inputs() const { return num_inputs; } +/* Find the number of outputs in the MUX graph */ +size_t MuxGraph::num_outputs() const { + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_mux_graph()); + /* Sum up the number of INPUT nodes in each level */ + size_t num_outputs = 0; + for (auto node_per_level : node_lookup_) { + num_outputs += node_per_level[MUX_OUTPUT_NODE].size(); + } + return num_outputs; +} + + /* Find the number of levels in the MUX graph */ size_t MuxGraph::num_levels() const { /* need to check if the graph is valid or not */ @@ -133,7 +146,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Add output nodes to subgraph */ MuxNodeId to_node_subgraph = mux_graph.add_node(MUX_OUTPUT_NODE); - mux_graph.node_levels_[to_node_subgraph] = 0; + mux_graph.node_levels_[to_node_subgraph] = 1; /* Update the node-to-node map */ node2node_map[root_node] = to_node_subgraph; @@ -155,7 +168,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { MuxEdgeId edge_subgraph = mux_graph.add_edge(node2node_map[from_node_origin], node2node_map[root_node]); edge2edge_map[edge_origin] = edge_subgraph; /* Configure edges */ - mux_graph.edge_types_[edge_subgraph] = this->edge_types_[edge_origin]; + mux_graph.edge_models_[edge_subgraph] = this->edge_models_[edge_origin]; mux_graph.edge_inv_mem_[edge_subgraph] = this->edge_inv_mem_[edge_origin]; } @@ -179,6 +192,9 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { mem2mem_map[mem_origin] = mem_subgraph; } + /* Since the graph is finalized, it is time to build the fast look-up */ + mux_graph.build_node_lookup(); + return mux_graph; } @@ -300,7 +316,7 @@ MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_nod /* Push to the node list */ edge_ids_.push_back(edge); /* Resize the other node-related vectors */ - edge_types_.push_back(NUM_CIRCUIT_MODEL_PASS_GATE_TYPES); + edge_models_.push_back(CircuitModelId::INVALID()); edge_mem_ids_.push_back(MuxMemId::INVALID()); edge_inv_mem_.push_back(false); @@ -386,7 +402,7 @@ void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) { */ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, const size_t& num_levels, const size_t& num_inputs_per_branch, - const enum e_spice_model_pass_gate_logic_type& pgl_type) { + const CircuitModelId& pgl_model) { /* Make sure mux_size for each branch is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(num_inputs_per_branch)); @@ -439,7 +455,7 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, /* Create an edge and connect the two nodes */ MuxEdgeId edge = add_edge(expand_node, seed_node); /* Configure the edge */ - edge_types_[edge] = pgl_type; + edge_models_[edge] = pgl_model; /* Memory id depends on the level and offset in the current branch * if number of inputs per branch is 2, it indicates a tree-like multiplexer, @@ -517,7 +533,7 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, * input_node --->+ */ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, - const enum e_spice_model_pass_gate_logic_type& pgl_type) { + const CircuitModelId& pgl_model) { /* Make sure mux_size is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); @@ -538,7 +554,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, */ MuxEdgeId edge = add_edge(input_node, output_node); /* Configure the edge */ - edge_types_[edge] = pgl_type; + edge_models_[edge] = pgl_model; /* Create a memory bit*/ MuxMemId mem = add_mem(); @@ -574,11 +590,11 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, size_t num_inputs_per_branch = 2; /* Build a multilevel mux graph */ - build_multilevel_mux_graph(impl_mux_size, num_levels, num_inputs_per_branch, circuit_lib.pass_gate_logic_type(circuit_model)); + build_multilevel_mux_graph(impl_mux_size, num_levels, num_inputs_per_branch, circuit_lib.pass_gate_logic_model(circuit_model)); break; } case SPICE_MODEL_STRUCTURE_ONELEVEL: { - build_onelevel_mux_graph(impl_mux_size, circuit_lib.pass_gate_logic_type(circuit_model)); + build_onelevel_mux_graph(impl_mux_size, circuit_lib.pass_gate_logic_model(circuit_model)); break; } case SPICE_MODEL_STRUCTURE_MULTILEVEL: { @@ -588,7 +604,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, /* Build a multilevel mux graph */ build_multilevel_mux_graph(impl_mux_size, circuit_lib.mux_num_levels(circuit_model), num_inputs_per_branch, - circuit_lib.pass_gate_logic_type(circuit_model)); + circuit_lib.pass_gate_logic_model(circuit_model)); break; } default: diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index fc5dd1f98..0b76da5da 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -63,6 +63,8 @@ class MuxGraph { public: /* Public accessors: Data query */ /* Find the number of inputs in the MUX graph */ size_t num_inputs() const; + /* Find the number of outputs in the MUX graph */ + size_t num_outputs() const; /* Find the number of levels in the MUX graph */ size_t num_levels() const; /* Find the number of SRAMs in the MUX graph */ @@ -88,10 +90,10 @@ class MuxGraph { private: /* Private mutators : graph builders */ void build_multilevel_mux_graph(const size_t& mux_size, const size_t& num_levels, const size_t& num_inputs_per_branch, - const enum e_spice_model_pass_gate_logic_type& pgl_type); + const CircuitModelId& pgl_model) ; /* Build the graph for a given one-level multiplexer implementation */ void build_onelevel_mux_graph(const size_t& mux_size, - const enum e_spice_model_pass_gate_logic_type& pgl_type); + const CircuitModelId& pgl_model) ; /* Build the graph for a given multiplexer model */ void build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, @@ -120,7 +122,7 @@ class MuxGraph { vtr::vector edge_ids_; /* Unique ids for each edge */ vtr::vector> edge_src_nodes_; /* source nodes drive this edge */ vtr::vector> edge_sink_nodes_; /* sink nodes this edge drives */ - vtr::vector edge_types_; /* type of each edge: tgate/pass-gate */ + vtr::vector edge_models_; /* type of each edge: tgate/pass-gate */ vtr::vector edge_mem_ids_; /* ids of memory bit that control the edge */ vtr::vector edge_inv_mem_; /* if the edge is controlled by an inverted output of a memory bit */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index c8dd0b8c3..8a78d734e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -196,7 +196,6 @@ void link_sram_inf(t_sram_inf* cur_sram_inf, **************************************************************************/ t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, const CircuitPortId& circuit_port) { t_port* ret = NULL; size_t num_found = 0; @@ -204,10 +203,10 @@ t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, /* Search ports */ for (int iport = 0; iport < pb_type->num_ports; iport++) { /* Match the name and port size*/ - if ( (0 == circuit_lib.port_prefix(circuit_model, circuit_port).compare(pb_type->ports[iport].name)) - && (size_t(pb_type->ports[iport].num_pins) == circuit_lib.port_size(circuit_model, circuit_port))) { + if ( (0 == circuit_lib.port_prefix(circuit_port).compare(pb_type->ports[iport].name)) + && (size_t(pb_type->ports[iport].num_pins) == circuit_lib.port_size(circuit_port))) { /* Match the type*/ - switch (circuit_lib.port_type(circuit_model, circuit_port)) { + switch (circuit_lib.port_type(circuit_port)) { case SPICE_MODEL_PORT_INPUT: if ((IN_PORT == pb_type->ports[iport].type) &&(0 == pb_type->ports[iport].is_clock)) { @@ -236,7 +235,7 @@ t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for circuit model port(%s)!\n", - __FILE__, __LINE__, circuit_lib.port_prefix(circuit_model, circuit_port)); + __FILE__, __LINE__, circuit_lib.port_prefix(circuit_port)); exit(1); } } @@ -246,7 +245,7 @@ t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, if (1 < num_found) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", - __FILE__, __LINE__, pb_type->name, circuit_lib.port_prefix(circuit_model, circuit_port).c_str()); + __FILE__, __LINE__, pb_type->name, circuit_lib.port_prefix(circuit_port).c_str()); exit(1); } @@ -276,8 +275,8 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, } /* For each port, find a SPICE model port, which has the same name and port size */ - for (auto& port : circuit_lib.ports(circuit_model)) { - t_port* cur_pb_type_port = find_pb_type_port_match_circuit_model_port(cur_pb_type, circuit_lib, circuit_model, port); + for (auto& port : circuit_lib.model_ports(circuit_model)) { + t_port* cur_pb_type_port = find_pb_type_port_match_circuit_model_port(cur_pb_type, circuit_lib, port); /* Not every spice_model_port can find a mapped pb_type_port. * Since a pb_type only includes necessary ports in technology mapping. * ports for physical designs may be ignored ! diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h index 1b134a78d..f69314377 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h @@ -54,7 +54,6 @@ CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_nam t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, const CircuitPortId& circuit_port); void link_circuit_library_to_arch(t_arch* arch, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h new file mode 100644 index 000000000..76dc603e8 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -0,0 +1,27 @@ +/************************************************ + * This files includes data structures for + * module management. + * It keeps a list of modules that have been + * generated, the port map of the modules, + * parents and children of each modules + * This will ease instanciation of modules + * with explicit port map and outputting a + * hierarchy of modules + ***********************************************/ + +#ifndef MODULE_MANAGER_H +#define MODULE_MANAGER_H + +#include +#include "module_manager_fwd.h" +#include "device_port.h" + +class ModuleManager { + private: /* Internal data */ + vtr::vector ids_; + vtr::vector ports_; + vtr::vector> parents_; + vtr::vector> children_; +}; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h new file mode 100644 index 000000000..abaa0854b --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h @@ -0,0 +1,18 @@ +/************************************************** + * This file includes only declarations for + * the data structures for module managers + * Please refer to module_manager.h for more details + *************************************************/ +#ifndef MODULE_MANAGER_FWD_H +#define MODULE_MANAGER_FWD_H + +#include "vtr_strong_id.h" + +/* Strong Ids for MUXes */ +struct module_id_tag; + +typedef vtr::StrongId ModuleId; + +class ModuleManager; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4c0ec145f..8fc306335 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -803,9 +803,9 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); if (true == is_explicit_mapping) { - fprintf(fp, ")",itrack); + fprintf(fp, ")"); } - fprintf(fp, ",\n",itrack); + fprintf(fp, ",\n"); } fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side)); /* Dump OPINs of adjacent CLBs */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h index 4701b18de..73d75b766 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h @@ -1,3 +1,5 @@ +#ifndef VERILOG_GLOBAL_H +#define VERILOG_GLOBAL_H /* global parameters for dumping synthesizable verilog */ extern char* verilog_netlist_file_postfix; @@ -140,8 +142,10 @@ VERILOG_PORT_OUTPUT, VERILOG_PORT_INOUT, VERILOG_PORT_WIRE, VERILOG_PORT_REG, -VERILOG_PORT_CONKT +VERILOG_PORT_CONKT, +NUM_VERILOG_PORT_TYPES }; +constexpr std::array VERILOG_PORT_TYPE_STRING = {{"input", "output", "inout", "wire", "reg", ""}}; /* string version of enum e_verilog_port_type */ enum e_verilog_tb_type { VERILOG_TB_TOP, @@ -149,3 +153,5 @@ VERILOG_TB_BLIF_TOP, VERILOG_TB_AUTOCHECK_TOP, VERILOG_TB_FORMAL_VERIFICATION }; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp index f60cef851..23f62a77f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp @@ -5,12 +5,25 @@ * such as a branch in a multiplexer * and the full multiplexer **********************************************/ +#include #include "util.h" #include "vtr_assert.h" -#include "verilog_submodule_mux.h" +/* Device-level header files */ +#include "mux_graph.h" +#include "physical_types.h" +#include "vpr_types.h" +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_writer_utils.h" +#include "verilog_submodule_mux.h" /*********************************************** * Generate Verilog codes modeling an branch circuit @@ -20,7 +33,153 @@ static void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::string& module_name, const MuxGraph& mux_graph) { + /* Get the tgate model */ + CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model); + + /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ + if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); + return; + } + + /* Get model ports of tgate */ + std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT); + std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT); + VTR_ASSERT(3 == tgate_input_ports.size()); + VTR_ASSERT(1 == tgate_output_ports.size()); + + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of inputs */ + size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == num_outputs); + /* MUX graph must have only 1 level*/ + VTR_ASSERT(1 == mux_graph.num_levels()); + + /* Comment lines */ + fp << "//---- Structural Verilog for CMOS MUX basis module:" << module_name << "-----" << std::endl; + + /* Print the port list and definition */ + fp << "module " << module_name << "(" << std::endl; + + /* Create port information */ + BasicPort input_port; + /* Configure each input port */ + input_port.set_name(std::string("in")); + input_port.set_width(num_inputs); + + BasicPort output_port; + /* Configure each input port */ + output_port.set_name(std::string("out")); + output_port.set_width(num_outputs); + + BasicPort mem_port; + /* Configure each input port */ + mem_port.set_name(std::string("mem")); + mem_port.set_width(num_mems); + + BasicPort mem_inv_port; + /* Configure each input port */ + mem_inv_port.set_name(std::string("mem_inv")); + mem_inv_port.set_width(num_mems); + + /* TODO: Generate global ports */ + + + /* TODO: add a module to the Module Manager */ + + /* Port list */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl; + fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << "," << std::endl; + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_port) << "," << std::endl; + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_inv_port) << std::endl; + fp << ");" << std::endl; + + /* Verilog Behavior description for a MUX */ + fp << "//---- Structure-level description -----" << std::endl; + /* Special case: only one memory, switch case is simpler + * When mem = 1, propagate input 0; + * when mem = 0, propagate input 1; + */ + if (1 == num_mems) { + /* Transmission gates are connected to each input and also the output*/ + fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_0 "; + /* Dump explicit port map if required */ + if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { + fp << " ("; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[0]" << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port) << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")"; + fp << ");" << std::endl; + } else { + fp << " ("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port); + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port); + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << ");" << std::endl; + } + /* Transmission gates are connected to each input and also the output*/ + fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_1 "; + /* Dump explicit port map if required */ + if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { + fp << " ("; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[1]" << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port) << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")"; + fp << ");" << std::endl; + } else { + fp << " ("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port); + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port); + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << ");" << std::endl; + } + } else { + /* Other cases, we need to follow the rules: + * When mem[k] is enabled, switch on input[k] + * Only one memory bit is enabled! + */ + for (size_t i = 0; i < num_mems; i++) { + fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_" << i << " "; + if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { + fp << " ("; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[" << i << "]" << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << "mem[" << i << "]" << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << "mem_inv[" << i << "]" << "),"; + fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")"; + fp << ");" << std::endl; + } else { + fp << " ("; + fp << "in[" << i << "]"; + fp << ", " << "mem[" << i << "]"; + fp << ", " << "mem_inv[" << i << "]"; + fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << ");" << std::endl; + } + } + } + + /* Put an end to this module */ + fp << "endmodule" << std::endl; + + /* Comment lines */ + fp << "//---- END Structural Verilog CMOS MUX basis module: " << module_name << "-----" << std::endl << std::endl; + return; } @@ -31,12 +190,15 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, void generate_verilog_mux_branch_module(std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const size_t& mux_size, const MuxGraph& mux_graph) { + std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, verilog_mux_basis_posfix); + /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { case SPICE_MODEL_DESIGN_CMOS: if (true == circuit_lib.dump_structural_verilog(circuit_model)) { - generate_verilog_cmos_mux_branch_module_structural(fp, circuit_lib, circuit_model, mux_graph); + generate_verilog_cmos_mux_branch_module_structural(fp, circuit_lib, circuit_model, module_name, mux_graph); } else { /* dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h index 6e7e84b30..8c03d86e1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h @@ -15,6 +15,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const size_t& mux_size, const MuxGraph& mux_graph); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index c1f2944f9..2d058b491 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2854,7 +2854,8 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ for (auto branch_mux_graph : branch_mux_graphs) { - generate_verilog_mux_branch_module(sfp, spice->circuit_lib, mux_circuit_model, branch_mux_graph); + generate_verilog_mux_branch_module(sfp, spice->circuit_lib, mux_circuit_model, + mux_graph.num_inputs(), branch_mux_graph); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index dc62b3797..7251fdc83 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -144,7 +144,7 @@ void dump_include_user_defined_verilog_netlists(FILE* fp, return; } -void check_file_handler(const std::fstream& fp) { +void check_file_handler(std::fstream& fp) { /* Make sure we have a valid file handler*/ /* Print out debugging information for if the file is not opened/created properly */ if (!fp.is_open() || !fp.good()) { @@ -855,7 +855,6 @@ int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp, return dumped_port_cnt; } - /* Dump all the global ports that are stored in the linked list * Return the number of ports that have been dumped */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 06aaba142..53359f048 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -10,7 +10,7 @@ void init_include_user_defined_verilog_netlists(t_spice spice); void dump_include_user_defined_verilog_netlists(FILE* fp, t_spice spice); -void check_file_handler(const std::fstream& fp); +void check_file_handler(std::fstream& fp); void dump_verilog_file_header(FILE* fp, char* usage); @@ -52,6 +52,7 @@ void dump_verilog_subckt_header_file(t_llist* subckt_llist_head, char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type); + void dump_verilog_generic_port(FILE* fp, enum e_dump_verilog_port_type dump_port_type, char* port_name, int port_lsb, int port_msb); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp new file mode 100644 index 000000000..da8d2acc0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -0,0 +1,39 @@ +/************************************************ + * Include functions for most frequently + * used Verilog writers + ***********************************************/ +#include "vtr_assert.h" + +/* Device-level header files */ + +/* FPGA-X2P context header files */ +#include "spice_types.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_writer_utils.h" + +/* Generate a string of a Verilog port */ +std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type, + const BasicPort& port_info) { + std::string verilog_line; + + /* Ensure the port type is valid */ + VTR_ASSERT(verilog_port_type < NUM_VERILOG_PORT_TYPES); + + std::string size_str = "[" + std::to_string(port_info.get_lsb()) + ":" + std::to_string(port_info.get_msb()) + "]"; + + /* Only connection require a format of [:] + * others require a format of [:] + */ + if (VERILOG_PORT_CONKT == verilog_port_type) { + verilog_line = port_info.get_name() + " " + size_str; + } else { + verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; + verilog_line += "" + size_str + " " + port_info.get_name(); + } + + return verilog_line; +} + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h new file mode 100644 index 000000000..14f7a8e68 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -0,0 +1,15 @@ +/************************************************ + * Header file for verilog_writer_utils.cpp + * Include function declaration for most frequently + * used Verilog writers + ***********************************************/ +#ifndef VERILOG_WRITER_UTILS_H +#define VERILOG_WRITER_UTILS_H + +#include +#include "device_port.h" + +std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type, + const BasicPort& port_info); + +#endif From b7484ef17860e493b14630a03399ee73e88b411c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 20 Aug 2019 15:58:19 -0600 Subject: [PATCH 089/482] Removed traces of old template file --- openfpga_flow/scripts/run_fpga_flow.py | 4 ++-- openfpga_flow/scripts/run_fpga_task.py | 10 ---------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 65e153073..2a01e561e 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -261,7 +261,6 @@ def validate_command_line_arguments(): if not any([getattr(args, i, 0) for i in eachdep.split("|")]): clean_up_and_exit("'%s' argument depends on (%s) argumets"% (eacharg, ", ".join(dependent).replace("|", " or "))) - exit() # Filter provided architecrue files args.arch_file = os.path.abspath(args.arch_file) @@ -796,6 +795,7 @@ def run_command(taskname, logfile, command, exit_if_fail=True): except (Exception, subprocess.CalledProcessError) as e: logger.exception("failed to execute %s" % taskname) process_failed_vpr_run(e.output) + print(e.output) if exit_if_fail: clean_up_and_exit("Failed to run %s task" % taskname) return None @@ -811,7 +811,7 @@ def process_failed_vpr_run(vpr_output): if __name__ == "__main__": # Setting up print and logging system - logging.basicConfig(level=logging.INFO, stream=sys.stdout, + logging.basicConfig(level=logging.DEBUG, stream=sys.stdout, format='%(levelname)s - %(message)s') logger = logging.getLogger('OpenFPGA_Flow_Logs') diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 0612700d4..6d1bf4a4b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -191,16 +191,6 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): if not os.path.isdir(gc["misc_dir"]): clean_up_and_exit("Miscellaneous directory does not exist") - fpga_flow_script = os.path.join(gc["misc_dir"], "fpga_flow_template.sh") - if not os.path.isfile(fpga_flow_script): - clean_up_and_exit("Missing fpga_flow script template %s" % - fpga_flow_script) - - fpga_flow_conf_tmpl = os.path.join(gc["misc_dir"], "fpga_flow_script.conf") - if not os.path.isfile(fpga_flow_conf_tmpl): - clean_up_and_exit("fpga_flow configuration tempalte is missing %s" % - fpga_flow_conf_tmpl) - # = = = = = = = = = = = = Create execution folder = = = = = = = = = = = = if os.path.isdir(curr_job_dir): question = "One the result directory already exist.\n" From 60e8d2b29f2e8e58226ed8c12003f2712007d6d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Aug 2019 16:12:01 -0600 Subject: [PATCH 090/482] add missing files and try to refactor submodule essential --- openfpga_flow/tasks/basic_flow/latest | 6 +-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 11 +++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 4 ++ .../verilog/verilog_submodule_essential.cpp | 41 +++++++++++++++++++ .../verilog/verilog_submodule_essential.h | 19 +++++++++ .../verilog/verilog_submodule_mux.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 11 ----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 4 -- 8 files changed, 77 insertions(+), 21 deletions(-) mode change 100644 => 120000 openfpga_flow/tasks/basic_flow/latest create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h diff --git a/openfpga_flow/tasks/basic_flow/latest b/openfpga_flow/tasks/basic_flow/latest deleted file mode 100644 index d43b654a7..000000000 --- a/openfpga_flow/tasks/basic_flow/latest +++ /dev/null @@ -1,5 +0,0 @@ -XSym -0006 -de6ba653dd63797278d7fa829999bf6c -run003 - \ No newline at end of file diff --git a/openfpga_flow/tasks/basic_flow/latest b/openfpga_flow/tasks/basic_flow/latest new file mode 120000 index 000000000..9407a80a8 --- /dev/null +++ b/openfpga_flow/tasks/basic_flow/latest @@ -0,0 +1 @@ +run002 \ No newline at end of file diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index f86fc13e4..a3611a7a4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -228,6 +228,17 @@ char* chomp_file_name_postfix(char* file_name) { return ret; } +void check_file_handler(std::fstream& fp) { + /* Make sure we have a valid file handler*/ + /* Print out debugging information for if the file is not opened/created properly */ + if (!fp.is_open() || !fp.good()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create file!\n", + __FILE__, __LINE__); + exit(1); + } +} + /* Print SRAM bits, typically in a comment line */ void fprint_commented_sram_bits(FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 27803a005..1f7fc9c4e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -1,9 +1,13 @@ #ifndef FPGA_X2P_UTILS_H #define FPGA_X2P_UTILS_H +#include + #include "my_free_fwd.h" #include "rr_blocks_naming.h" +void check_file_handler(std::fstream& fp); + char* my_gettime(); char* format_dir_path(char* dir_path); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp new file mode 100644 index 000000000..f291690bb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp @@ -0,0 +1,41 @@ +/************************************************ + * Header file for verilog_submodule_essential.cpp + * Include function declaration on + * outputting Verilog netlists for essential gates + * which are inverters, buffers, transmission-gates + * logic gates etc. + ***********************************************/ +#include +#include "vtr_assert.h" + +/* Device-level header files */ +#include "spice_types.h" + +/* FPGA-X2P context header files */ +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_submodule_essential.h" + +void dump_verilog_submodule_essentials(const std::string& verilog_dir, + const std::string& submodule_dir, + const CircuitLibrary& circuit_lib) { + std::string verilog_fname = submodule_dir + essentials_verilog_file_name; + std::fstream fp; + + /* Create the file stream */ + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + /* Check if the file stream if valid or not */ + check_file_handler(fp); + + /* Create file */ + vpr_printf(TIO_MESSAGE_INFO, + "Generating Verilog netlist (%s) for essential gates...\n", + __FILE__, __LINE__, essentials_verilog_file_name); + + /* Close file handler*/ + fp.close(); + + return; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h new file mode 100644 index 000000000..049fbfda3 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h @@ -0,0 +1,19 @@ +/************************************************ + * Header file for verilog_submodule_essential.cpp + * Include function declaration on + * outputting Verilog netlists for essential gates + * which are inverters, buffers, transmission-gates + * logic gates etc. + ***********************************************/ + +#ifndef VERILOG_SUBMODULE_ESSENTIAL_H +#define VERILOG_SUBMODULE_ESSENTIAL_H + +#include +#include "circuit_library.h" + +void dump_verilog_submodule_essentials(const std::string& verilog_dir, + const std::string& submodule_dir, + const CircuitLibrary& circuit_lib); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp index 23f62a77f..d6f50e5c3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp @@ -18,10 +18,10 @@ /* FPGA-X2P context header files */ #include "spice_types.h" #include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" /* FPGA-Verilog context header files */ #include "verilog_global.h" -#include "verilog_utils.h" #include "verilog_writer_utils.h" #include "verilog_submodule_mux.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 7251fdc83..882906a43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -144,17 +144,6 @@ void dump_include_user_defined_verilog_netlists(FILE* fp, return; } -void check_file_handler(std::fstream& fp) { - /* Make sure we have a valid file handler*/ - /* Print out debugging information for if the file is not opened/created properly */ - if (!fp.is_open() || !fp.good()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create file!\n", - __FILE__, __LINE__); - exit(1); - } -} - void dump_verilog_file_header(FILE* fp, char* usage) { if (NULL == fp) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 53359f048..639843c57 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -1,8 +1,6 @@ #ifndef VERILOG_UTILS_H #define VERILOG_UTILS_H -#include - void init_list_include_verilog_netlists(t_spice* spice); void init_include_user_defined_verilog_netlists(t_spice spice); @@ -10,8 +8,6 @@ void init_include_user_defined_verilog_netlists(t_spice spice); void dump_include_user_defined_verilog_netlists(FILE* fp, t_spice spice); -void check_file_handler(std::fstream& fp); - void dump_verilog_file_header(FILE* fp, char* usage); From 5f55fc7b491957cb673e502bc49612de414c220a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Aug 2019 18:13:24 -0600 Subject: [PATCH 091/482] add missing files and developing essential gates --- openfpga_flow/tasks/basic_flow/latest | 2 +- .../libarchfpga/SRC/check_circuit_library.cpp | 2 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 29 +- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 2 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 43 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 24 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 24 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 5 +- .../verilog/verilog_submodule_essential.cpp | 274 +++++++++++++++++- .../verilog/verilog_submodule_essential.h | 6 +- .../verilog/verilog_submodule_mux.cpp | 15 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 47 +++ .../fpga_x2p/verilog/verilog_writer_utils.h | 6 + 13 files changed, 461 insertions(+), 18 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h diff --git a/openfpga_flow/tasks/basic_flow/latest b/openfpga_flow/tasks/basic_flow/latest index 9407a80a8..92a41ae5e 120000 --- a/openfpga_flow/tasks/basic_flow/latest +++ b/openfpga_flow/tasks/basic_flow/latest @@ -1 +1 @@ -run002 \ No newline at end of file +run003 \ No newline at end of file diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 8fc98cc50..b39925326 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -202,7 +202,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& size_t num_err = 0; - std::vector ports = circuit_lib.model_ports_by_type(circuit_model, port_type_to_check, include_global_ports); + std::vector ports = circuit_lib.model_ports_by_type(circuit_model, port_type_to_check, false == include_global_ports); if (num_ports_to_check != ports.size()) { vpr_printf(TIO_MESSAGE_ERROR, "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 1e45f5b7f..21466c998 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -352,6 +352,30 @@ std::vector CircuitLibrary::model_global_ports(const CircuitModel return global_ports; } +/* Recursively find all the global ports in the circuit model / sub circuit_model */ +std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& type) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + + /* Search all the ports */ + std::vector global_ports; + for (auto port : model_ports(model_id)) { + /* By pass non-global ports*/ + if (false == port_is_global(port)) { + continue; + } + /* We skip unmatched ports */ + if ( type != port_type(port) ) { + continue; + } + /* This is a global port, update global_ports */ + global_ports.push_back(port); + } + + return global_ports; +} + /* Find the ports of a circuit model by a given type, return a list of qualified ports */ std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type) const { @@ -371,7 +395,7 @@ std::vector CircuitLibrary::model_ports_by_type(const CircuitMode */ std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, - const bool& include_global_port) const { + const bool& ignore_global_port) const { std::vector port_ids; for (const auto& port_id : model_port_lookup_[model_id][type]) { /* We skip unmatched ports */ @@ -379,7 +403,7 @@ std::vector CircuitLibrary::model_ports_by_type(const CircuitMode continue; } /* We skip global ports if specified */ - if ( (false == include_global_port) + if ( (true == ignore_global_port) && (true == port_is_global(port_id)) ) { continue; } @@ -388,7 +412,6 @@ std::vector CircuitLibrary::model_ports_by_type(const CircuitMode return port_ids; } - /* Create a vector for all the ports whose directionality is input * This includes all the ports other than whose types are OUPUT or INOUT */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 72172bf30..2c4aa42d5 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -233,6 +233,8 @@ class CircuitLibrary { size_t num_model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_ports(const CircuitModelId& model_id) const; std::vector model_global_ports(const CircuitModelId& model_id) const; + std::vector model_global_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& type) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_input_ports(const CircuitModelId& model_id) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp new file mode 100644 index 000000000..0881d5221 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -0,0 +1,43 @@ +/************************************************ + * This file includes functions to + * generate module/port names for Verilog + * and SPICE netlists + ***********************************************/ +#include "vtr_assert.h" + +#include "fpga_x2p_naming.h" + +/************************************************ + * Generate the module name for a multiplexer in Verilog format + ***********************************************/ +std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const std::string& postfix) { + std::string module_name = circuit_lib.model_name(circuit_model); + module_name += "_size"; + module_name += std::to_string(mux_size); + module_name += postfix; + + return module_name; +} + +/************************************************ + * Generate the module name of a branch for a + * multiplexer in Verilog format + ***********************************************/ +std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const std::string& postfix) { + /* If the tgate spice model of this MUX is a MUX2 standard cell, + * the mux_subckt name will be the name of the standard cell + */ + CircuitModelId subckt_model = circuit_lib.pass_gate_logic_model(circuit_model); + if (SPICE_MODEL_GATE == circuit_lib.model_type(subckt_model)) { + VTR_ASSERT (SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(subckt_model)); + return circuit_lib.model_name(subckt_model); + } + + return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, postfix); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h new file mode 100644 index 000000000..ff91f4854 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -0,0 +1,24 @@ +/************************************************ + * Header file for fpga_x2p_naming.cpp + * Include functions to generate module/port names + * for Verilog and SPICE netlists + ***********************************************/ + +#ifndef FPGA_X2P_NAMING_H +#define FPGA_X2P_NAMING_H + +#include + +#include "circuit_library.h" + +std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const std::string& posfix) ; + +std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const std::string& posfix); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index a3611a7a4..53faf3ad7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -12,6 +12,7 @@ #include #include #include +#include /* Include vpr structs*/ #include "util.h" @@ -63,6 +64,7 @@ char* my_gettime() { return c_time_string; } + char* format_dir_path(char* dir_path) { int len = strlen(dir_path); /* String length without the last "\0"*/ int i; @@ -82,6 +84,26 @@ char* format_dir_path(char* dir_path) { return ret; } +/************************************************ + * Format a path of directory: + * 1. Replace "\" with "/" + * 2. add a "/" if the string does not end with a "/" + ***********************************************/ +std::string format_dir_path(const std::string& dir_path) { + std::string ret = dir_path; + + /* Replace "\" with "/" */ + std::replace(ret.begin(), ret.end(), '\\', '/'); + + /* Complete the string with a "/" if it does not end with that */ + if ('/' != ret.back()) { + ret.push_back('/'); + } + + return ret; +} + + int try_access_file(char* file_path) { /* F_OK checks existence and also R_OK, W_OK, X_OK, * for readable, writable, excutable @@ -3228,7 +3250,7 @@ int count_cb_info_num_ipin_rr_nodes(t_cb cur_cb_info) { /* Add a subckt file name to a linked list */ t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head, - char* subckt_file_path) { + const char* subckt_file_path) { t_llist* new_head = NULL; if (NULL == cur_head) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 1f7fc9c4e..1a518f439 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -10,7 +10,8 @@ void check_file_handler(std::fstream& fp); char* my_gettime(); -char* format_dir_path(char* dir_path); +char* format_dir_path(char* dir_path); /* TODO: TO BE REMOVED !!! */ +std::string format_dir_path(const std::string& dir_path); int try_access_file(char* file_path); @@ -380,7 +381,7 @@ boolean is_cb_exist(t_rr_type cb_type, int count_cb_info_num_ipin_rr_nodes(t_cb cur_cb_info); t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head, - char* subckt_file_path); + const char* subckt_file_path); boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head, char* subckt_file_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp index f291690bb..c04dcd042 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp @@ -16,12 +16,253 @@ /* FPGA-Verilog context header files */ #include "verilog_global.h" +#include "verilog_writer_utils.h" #include "verilog_submodule_essential.h" -void dump_verilog_submodule_essentials(const std::string& verilog_dir, - const std::string& submodule_dir, - const CircuitLibrary& circuit_lib) { - std::string verilog_fname = submodule_dir + essentials_verilog_file_name; + +/************************************************ + * Print a Verilog module of inverter or buffer + * or tapered buffer to a file + ***********************************************/ +static +void print_verilog_invbuf_module(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + fp << "//----- Verilog module for " << circuit_lib.model_name(circuit_model) << " -----" << std::endl; + + /* Find the input port, output port and global inputs*/ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* TODO: move the check codes to check_circuit_library.h */ + /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ + if (true == circuit_lib.is_power_gated(circuit_model)) { + /* Check all the ports we have are good for a power-gated circuit model */ + size_t num_err = 0; + /* We need at least one global port */ + if (0 == global_ports.size()) { + num_err++; + } + /* All the global ports should be config_enable */ + for (const auto& port : global_ports) { + if (false == circuit_lib.port_is_config_enable(port)) { + num_err++; + } + } + /* Report errors if there are any */ + if (0 < num_err) { + vpr_printf(TIO_MESSAGE_ERROR, + "Inverter/buffer circuit model (name=%s) is power-gated. At least one config-enable global port is required!\n", + circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + } + + /* dump module body */ + fp << "module " << circuit_lib.model_name(circuit_model) << " (" << std::endl; + + /* TODO: print global ports */ + for (const auto& port : global_ports) { + BasicPort basic_port; + /* Configure each input port */ + basic_port.set_name(circuit_lib.port_prefix(port)); + basic_port.set_width(circuit_lib.port_size(port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + } + + /* Dump ports */ + BasicPort input_port; + /* Configure each input port */ + input_port.set_name(circuit_lib.port_lib_name(input_ports[0])); + input_port.set_width(circuit_lib.port_size(input_ports[0])); + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl; + + BasicPort output_port; + /* Configure each input port */ + output_port.set_name(circuit_lib.port_lib_name(output_ports[0])); + output_port.set_width(circuit_lib.port_size(output_ports[0])); + fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << "," << std::endl; + fp << ");" << std::endl; + /* Finish dumping ports */ + +// /* Assign logics : depending on topology */ +// switch (invbuf_spice_model->design_tech_info.buffer_info->type) { +// case SPICE_MODEL_BUF_INV: +// if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { +// /* Create a sensitive list */ +// fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); +// fprintf(fp, "always @("); +// /* Power-gate port first*/ +// for (iport = 0; iport < num_powergate_port; iport++) { +// fprintf(fp, "%s,", powergate_port[iport]->lib_name); +// } +// fprintf(fp, "%s) begin\n", +// input_port[0]->lib_name); +// /* Dump the case of power-gated */ +// fprintf(fp, " if ("); +// port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ +// for (iport = 0; iport < num_powergate_port; iport++) { +// if (0 == powergate_port[iport]->default_val) { +// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { +// if ( 0 < port_cnt ) { +// fprintf(fp, "\n\t&&"); +// } +// /* Power-gated signal are disable during operating, enabled during configuration, +// * Therefore, we need to reverse them here +// */ +// fprintf(fp, "(~%s[%d])", +// powergate_port[iport]->lib_name, +// ipin); +// port_cnt++; /* Update port counter*/ +// } +// } else { +// assert (1 == powergate_port[iport]->default_val); +// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { +// if ( 0 < port_cnt ) { +// fprintf(fp, "\n\t&&"); +// } +// /* Power-gated signal are disable during operating, enabled during configuration, +// * Therefore, we need to reverse them here +// */ +// fprintf(fp, "(%s[%d])", +// powergate_port[iport]->lib_name, +// ipin); +// port_cnt++; /* Update port counter*/ +// } +// } +// } +// fprintf(fp, ") begin\n"); +// fprintf(fp, "\t\tassign %s_reg = ~%s;\n", +// output_port[0]->lib_name, +// input_port[0]->lib_name); +// fprintf(fp, "\tend else begin\n"); +// fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", +// output_port[0]->lib_name); +// fprintf(fp, "\tend\n"); +// fprintf(fp, "end\n"); +// fprintf(fp, "assign %s = %s_reg;\n", +// output_port[0]->lib_name, +// output_port[0]->lib_name); +// } else { +// fprintf(fp, "assign %s = (%s === 1'bz)? $random : ~%s;\n", +// output_port[0]->lib_name, +// input_port[0]->lib_name, +// input_port[0]->lib_name); +// } +// break; +// case SPICE_MODEL_BUF_BUF: +// if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { +// /* Create a sensitive list */ +// fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); +// fprintf(fp, "always @("); +// /* Power-gate port first*/ +// for (iport = 0; iport < num_powergate_port; iport++) { +// fprintf(fp, "%s,", powergate_port[iport]->lib_name); +// } +// fprintf(fp, "%s) begin\n", +// input_port[0]->lib_name); +// /* Dump the case of power-gated */ +// fprintf(fp, " if ("); +// port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ +// for (iport = 0; iport < num_powergate_port; iport++) { +// if (0 == powergate_port[iport]->default_val) { +// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { +// if ( 0 < port_cnt ) { +// fprintf(fp, "\n\t&&"); +// } +// /* Power-gated signal are disable during operating, enabled during configuration, +// * Therefore, we need to reverse them here +// */ +// fprintf(fp, "(~%s[%d])", +// powergate_port[iport]->lib_name, +// ipin); +// port_cnt++; /* Update port counter*/ +// } +// } else { +// assert (1 == powergate_port[iport]->default_val); +// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { +// if ( 0 < port_cnt ) { +// fprintf(fp, "\n\t&&"); +// } +// /* Power-gated signal are disable during operating, enabled during configuration, +// * Therefore, we need to reverse them here +// */ +// fprintf(fp, "(%s[%d])", +// powergate_port[iport]->lib_name, +// ipin); +// port_cnt++; /* Update port counter*/ +// } +// } +// } +// fprintf(fp, ") begin\n"); +// fprintf(fp, "\t\tassign %s_reg = %s;\n", +// output_port[0]->lib_name, +// input_port[0]->lib_name); +// fprintf(fp, "\tend else begin\n"); +// fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", +// output_port[0]->lib_name); +// fprintf(fp, "\tend\n"); +// fprintf(fp, "end\n"); +// fprintf(fp, "assign %s = %s_reg;\n", +// output_port[0]->lib_name, +// output_port[0]->lib_name); +// +// } else if (FALSE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf) { +// fprintf(fp, "assign %s = (%s === 1'bz)? $random : %s;\n", +// output_port[0]->lib_name, +// input_port[0]->lib_name, +// input_port[0]->lib_name); +// } else { +// assert (TRUE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf); +// fprintf(fp, "assign %s = (%s === 1'bz)? $random : ", +// output_port[0]->lib_name, +// input_port[0]->lib_name); +// /* depend on the stage, we may invert the output */ +// if (1 == invbuf_spice_model->design_tech_info.buffer_info->tap_buf_level % 2) { +// fprintf(fp, "~"); +// } +// fprintf(fp, "%s;\n", +// input_port[0]->lib_name); +// } +// break; +// default: +// vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", +// __FILE__, __LINE__, invbuf_spice_model->name); +// exit(1); +// } +// +// /* Print timing info */ +// dump_verilog_submodule_timing(fp, invbuf_spice_model); +// +// dump_verilog_submodule_signal_init(fp, invbuf_spice_model); + + fp << "endmodule" << std::endl << std::endl; + + return; +} + +/************************************************ + * Generate the Verilog netlist for essential gates + * include inverters, buffers, transmission-gates, + * etc. + ***********************************************/ +void print_verilog_submodule_essentials(const std::string& verilog_dir, + const std::string& submodule_dir, + const CircuitLibrary& circuit_lib) { + /* TODO: remove .bak when this part is completed and tested */ + std::string verilog_fname = submodule_dir + essentials_verilog_file_name + ".bak"; std::fstream fp; /* Create the file stream */ @@ -33,9 +274,34 @@ void dump_verilog_submodule_essentials(const std::string& verilog_dir, vpr_printf(TIO_MESSAGE_INFO, "Generating Verilog netlist (%s) for essential gates...\n", __FILE__, __LINE__, essentials_verilog_file_name); + + print_verilog_file_header(fp, "Essential gates"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + for (const auto& circuit_model : circuit_lib.models()) { + /* By pass user-defined modules */ + if (!circuit_lib.model_verilog_netlist(circuit_model).empty()) { + continue; + } + if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { + print_verilog_invbuf_module(fp, circuit_lib, circuit_model); + } + /* + if (SPICE_MODEL_PASSGATE == spice_models[imodel].type) { + dump_verilog_passgate_module(fp, &(spice_models[imodel])); + } + if (SPICE_MODEL_GATE == spice_models[imodel].type) { + dump_verilog_gate_module(fp, &(spice_models[imodel])); + } + */ + } /* Close file handler*/ fp.close(); + /* Add fname to the linked list */ + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h index 049fbfda3..648db98fd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h @@ -12,8 +12,8 @@ #include #include "circuit_library.h" -void dump_verilog_submodule_essentials(const std::string& verilog_dir, - const std::string& submodule_dir, - const CircuitLibrary& circuit_lib); +void print_verilog_submodule_essentials(const std::string& verilog_dir, + const std::string& submodule_dir, + const CircuitLibrary& circuit_lib); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp index d6f50e5c3..867576bd3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp @@ -45,8 +45,9 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, } /* Get model ports of tgate */ - std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT); - std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT); + std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); + std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT); VTR_ASSERT(3 == tgate_input_ports.size()); VTR_ASSERT(1 == tgate_output_ports.size()); @@ -95,7 +96,14 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, mem_inv_port.set_width(num_mems); /* TODO: Generate global ports */ - + for (const auto& port : tgate_global_ports) { + BasicPort basic_port; + /* Configure each input port */ + basic_port.set_name(circuit_lib.port_prefix(port)); + basic_port.set_width(circuit_lib.port_size(port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + } /* TODO: add a module to the Module Manager */ @@ -116,6 +124,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, /* Transmission gates are connected to each input and also the output*/ fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_0 "; /* Dump explicit port map if required */ + /* TODO: add global port support for tgate model */ if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { fp << " ("; fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[0]" << "),"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index da8d2acc0..154fcbb47 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -2,17 +2,64 @@ * Include functions for most frequently * used Verilog writers ***********************************************/ +#include +#include +#include +#include #include "vtr_assert.h" /* Device-level header files */ /* FPGA-X2P context header files */ #include "spice_types.h" +#include "fpga_x2p_utils.h" /* FPGA-Verilog context header files */ #include "verilog_global.h" #include "verilog_writer_utils.h" +/************************************************ + * Generate header comments for a Verilog netlist + * include the description + ***********************************************/ +void print_verilog_file_header(std::fstream& fp, + const std::string& usage) { + check_file_handler(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << "//-------------------------------------------" << std::endl; + fp << "//\tFPGA Synthesizable Verilog Netlist" << std::endl; + fp << "//\tDescription: " << usage << std::endl; + fp << "//\tAuthor: Xifan TANG" << std::endl; + fp << "//\t Organization: University of Utah" << std::endl; + fp << "//\tDate: " << std::ctime(&end_time) << std::endl; + fp << "//-------------------------------------------" << std::endl; + fp << "//----- Time scale -----" << std::endl; + fp << "`timescale 1ns / 1ps" << std::endl; + fp << "\n"; +} + + +/************************************************ + * Generate include files for a Verilog netlist + ***********************************************/ +void print_verilog_include_defines_preproc_file(std::fstream& fp, + const std::string& verilog_dir) { + check_file_handler(fp); + + /* Generate the file name */ + std::string include_file_path = format_dir_path(verilog_dir); + include_file_path += defines_verilog_file_name; + + fp << "//------ Include defines: preproc flags -----" << std::endl; + fp << "`include \"" << include_file_path << "\"" << std::endl; + fp << "//------ End Include defines: preproc flags -----" << std::endl; + + return; +} + /* Generate a string of a Verilog port */ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type, const BasicPort& port_info) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 14f7a8e68..33a52fd69 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -9,6 +9,12 @@ #include #include "device_port.h" +void print_verilog_file_header(std::fstream& fp, + const std::string& usage); + +void print_verilog_include_defines_preproc_file(std::fstream& fp, + const std::string& verilog_dir); + std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type, const BasicPort& port_info); From 59f1ac7310d77a5f20ea78d675d09462849b1ff6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Aug 2019 16:12:01 -0600 Subject: [PATCH 092/482] add missing files and try to refactor submodule essential --- openfpga_flow/tasks/basic_flow/latest | 1 - .../vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) delete mode 120000 openfpga_flow/tasks/basic_flow/latest diff --git a/openfpga_flow/tasks/basic_flow/latest b/openfpga_flow/tasks/basic_flow/latest deleted file mode 120000 index 92a41ae5e..000000000 --- a/openfpga_flow/tasks/basic_flow/latest +++ /dev/null @@ -1 +0,0 @@ -run003 \ No newline at end of file diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp index c04dcd042..de13bcdac 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp @@ -263,6 +263,7 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ std::string verilog_fname = submodule_dir + essentials_verilog_file_name + ".bak"; + std::fstream fp; /* Create the file stream */ From 19472ace4e7d367716d77bc6fb3c31937982e9fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Aug 2019 21:01:38 -0600 Subject: [PATCH 093/482] renaming files --- ...og_submodule_essential.cpp => verilog_essential_gates.cpp} | 2 +- ...erilog_submodule_essential.h => verilog_essential_gates.h} | 4 ++-- .../verilog/{verilog_submodule_mux.cpp => verilog_mux.cpp} | 2 +- .../verilog/{verilog_submodule_mux.h => verilog_mux.h} | 4 ++-- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) rename vpr7_x2p/vpr/SRC/fpga_x2p/verilog/{verilog_submodule_essential.cpp => verilog_essential_gates.cpp} (99%) rename vpr7_x2p/vpr/SRC/fpga_x2p/verilog/{verilog_submodule_essential.h => verilog_essential_gates.h} (88%) rename vpr7_x2p/vpr/SRC/fpga_x2p/verilog/{verilog_submodule_mux.cpp => verilog_mux.cpp} (99%) rename vpr7_x2p/vpr/SRC/fpga_x2p/verilog/{verilog_submodule_mux.h => verilog_mux.h} (91%) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp similarity index 99% rename from vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index de13bcdac..23750a755 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -17,7 +17,7 @@ /* FPGA-Verilog context header files */ #include "verilog_global.h" #include "verilog_writer_utils.h" -#include "verilog_submodule_essential.h" +#include "verilog_essential_gates.h" /************************************************ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h similarity index 88% rename from vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h index 648db98fd..fa9b13660 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_essential.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h @@ -6,8 +6,8 @@ * logic gates etc. ***********************************************/ -#ifndef VERILOG_SUBMODULE_ESSENTIAL_H -#define VERILOG_SUBMODULE_ESSENTIAL_H +#ifndef VERILOG_ESSENTIAL_GATES_H +#define VERILOG_ESSENTIAL_GATES_H #include #include "circuit_library.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp similarity index 99% rename from vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 867576bd3..c79e93c8b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -23,7 +23,7 @@ /* FPGA-Verilog context header files */ #include "verilog_global.h" #include "verilog_writer_utils.h" -#include "verilog_submodule_mux.h" +#include "verilog_mux.h" /*********************************************** * Generate Verilog codes modeling an branch circuit diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h similarity index 91% rename from vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index 8c03d86e1..c7dfd4bf8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -2,8 +2,8 @@ * Header file for verilog_submodule_mux.cpp **********************************************/ -#ifndef VERILOG_SUBMODULE_MUX_H -#define VERILOG_SUBMODULE_MUX_H +#ifndef VERILOG_MUX_H +#define VERILOG_MUX_H /* Include other header files which are dependency on the function declared below */ #include diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 2d058b491..d86aae1e9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -39,7 +39,7 @@ #include "verilog_submodules.h" #include "mux_utils.h" -#include "verilog_submodule_mux.h" +#include "verilog_mux.h" /***** Subroutines *****/ From a40e5c91caae148e7d17a19ae3dd8637bc7b7918 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Aug 2019 21:56:55 -0600 Subject: [PATCH 094/482] refactored power-gate inverter --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 11 ++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + .../verilog/verilog_essential_gates.cpp | 143 ++++++++++-------- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 1 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 4 + .../fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 6 files changed, 95 insertions(+), 67 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 21466c998..35278893c 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -258,6 +258,17 @@ enum e_spice_model_gate_type CircuitLibrary::gate_type(const CircuitModelId& mod return gate_types_[model_id]; } +/* Return the type of buffer for a circuit model + * Only applicable for BUF/INV circuit model + */ +enum e_spice_model_buffer_type CircuitLibrary::buffer_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + return buffer_types_[model_id]; +} + /************************************************************************ * Public Accessors : Basic data query on Circuit models' Circuit Port ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 2c4aa42d5..34debee59 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -227,6 +227,7 @@ class CircuitLibrary { bool mux_add_const_input(const CircuitModelId& model_id) const; size_t mux_const_input_value(const CircuitModelId& model_id) const; enum e_spice_model_gate_type gate_type(const CircuitModelId& model_id) const; + enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ CircuitPortId model_port(const CircuitModelId& model_id, const std::string& name) const; size_t num_model_ports(const CircuitModelId& model_id) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 23750a755..c0707616c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -19,6 +19,66 @@ #include "verilog_writer_utils.h" #include "verilog_essential_gates.h" +/************************************************ + * Print Verilog codes of a power-gated inverter + ***********************************************/ +static +void print_verilog_power_gated_inv_module(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitPortId& input_port, + const CircuitPortId& output_port, + const std::vector& power_gate_ports) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + fp << "//----- Verilog codes of a power-gated inverter -----" << std::endl; + + /* Create a sensitive list */ + fp << "\treg " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; + + fp << "\talways @(" << std::endl; + /* Power-gate port first*/ + for (const auto& power_gate_port : power_gate_ports) { + /* Skip first comma to dump*/ + if (0 < &power_gate_port - &power_gate_ports[0]) { + fp << ","; + } + fp << circuit_lib.port_lib_name(power_gate_port); + } + fp << circuit_lib.port_lib_name(input_port) << ") begin" << std::endl; + + /* Dump the case of power-gated */ + fp << "\t\tif ("; + /* For the first pin, we skip output comma */ + size_t port_cnt = 0; + for (const auto& power_gate_port : power_gate_ports) { + for (const auto& power_gate_pin : circuit_lib.pins(power_gate_port)) { + if (0 < port_cnt) { + fp << std::endl << "\t\t&&"; + } + fp << "("; + + /* Power-gated signal are disable during operating, enabled during configuration, + * Therefore, we need to reverse them here + */ + if (0 == circuit_lib.port_default_value(power_gate_port)) { + fp << "~"; + } + + fp << circuit_lib.port_lib_name(power_gate_port) << "[" << power_gate_pin << "])"; + + port_cnt++; /* Update port counter*/ + } + } + + fp << ") begin" << std::endl; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = ~" << circuit_lib.port_lib_name(input_port) << ";" << std::endl; + fp << "\t\tend else begin" << std::endl; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = 1'bz;" << std::endl; + fp << "\t\tend" << std::endl; + fp << "\tend" << std::endl; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; +} /************************************************ * Print a Verilog module of inverter or buffer @@ -97,72 +157,20 @@ void print_verilog_invbuf_module(std::fstream& fp, fp << ");" << std::endl; /* Finish dumping ports */ -// /* Assign logics : depending on topology */ -// switch (invbuf_spice_model->design_tech_info.buffer_info->type) { -// case SPICE_MODEL_BUF_INV: -// if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { -// /* Create a sensitive list */ -// fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); -// fprintf(fp, "always @("); -// /* Power-gate port first*/ -// for (iport = 0; iport < num_powergate_port; iport++) { -// fprintf(fp, "%s,", powergate_port[iport]->lib_name); -// } -// fprintf(fp, "%s) begin\n", -// input_port[0]->lib_name); -// /* Dump the case of power-gated */ -// fprintf(fp, " if ("); -// port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ -// for (iport = 0; iport < num_powergate_port; iport++) { -// if (0 == powergate_port[iport]->default_val) { -// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { -// if ( 0 < port_cnt ) { -// fprintf(fp, "\n\t&&"); -// } -// /* Power-gated signal are disable during operating, enabled during configuration, -// * Therefore, we need to reverse them here -// */ -// fprintf(fp, "(~%s[%d])", -// powergate_port[iport]->lib_name, -// ipin); -// port_cnt++; /* Update port counter*/ -// } -// } else { -// assert (1 == powergate_port[iport]->default_val); -// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { -// if ( 0 < port_cnt ) { -// fprintf(fp, "\n\t&&"); -// } -// /* Power-gated signal are disable during operating, enabled during configuration, -// * Therefore, we need to reverse them here -// */ -// fprintf(fp, "(%s[%d])", -// powergate_port[iport]->lib_name, -// ipin); -// port_cnt++; /* Update port counter*/ -// } -// } -// } -// fprintf(fp, ") begin\n"); -// fprintf(fp, "\t\tassign %s_reg = ~%s;\n", -// output_port[0]->lib_name, -// input_port[0]->lib_name); -// fprintf(fp, "\tend else begin\n"); -// fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", -// output_port[0]->lib_name); -// fprintf(fp, "\tend\n"); -// fprintf(fp, "end\n"); -// fprintf(fp, "assign %s = %s_reg;\n", -// output_port[0]->lib_name, -// output_port[0]->lib_name); + /* Assign logics : depending on topology */ + switch (circuit_lib.buffer_type(circuit_model)) { + case SPICE_MODEL_BUF_INV: + if (TRUE == circuit_lib.is_power_gated(circuit_model)) { + print_verilog_power_gated_inv_module(fp, circuit_lib, input_ports[0], output_ports[0], global_ports); + } // } else { // fprintf(fp, "assign %s = (%s === 1'bz)? $random : ~%s;\n", // output_port[0]->lib_name, // input_port[0]->lib_name, // input_port[0]->lib_name); // } -// break; -// case SPICE_MODEL_BUF_BUF: + break; + case SPICE_MODEL_BUF_BUF: // if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { // /* Create a sensitive list */ // fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); @@ -236,12 +244,13 @@ void print_verilog_invbuf_module(std::fstream& fp, // fprintf(fp, "%s;\n", // input_port[0]->lib_name); // } -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", -// __FILE__, __LINE__, invbuf_spice_model->name); -// exit(1); -// } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + exit(1); + } // // /* Print timing info */ // dump_verilog_submodule_timing(fp, invbuf_spice_model); @@ -302,7 +311,9 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, fp.close(); /* Add fname to the linked list */ + /* TODO: enable this when this function is completed submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index c79e93c8b..277a3ece8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -120,6 +120,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, * When mem = 1, propagate input 0; * when mem = 0, propagate input 1; */ + /* TODO: we should output the netlist following the connections in mux_graph */ if (1 == num_mems) { /* Transmission gates are connected to each input and also the output*/ fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_0 "; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index d86aae1e9..bc753174f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -40,6 +40,7 @@ #include "mux_utils.h" #include "verilog_mux.h" +#include "verilog_essential_gates.h" /***** Subroutines *****/ @@ -4055,6 +4056,9 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_submodule_essentials(verilog_dir, submodule_dir, Arch.spice->num_spice_model, Arch.spice->spice_models); + print_verilog_submodule_essentials(std::string(verilog_dir), + std::string(submodule_dir), + Arch.spice->circuit_lib); /* 1. MUXes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 154fcbb47..8902ce920 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -34,7 +34,7 @@ void print_verilog_file_header(std::fstream& fp, fp << "//\tDescription: " << usage << std::endl; fp << "//\tAuthor: Xifan TANG" << std::endl; fp << "//\t Organization: University of Utah" << std::endl; - fp << "//\tDate: " << std::ctime(&end_time) << std::endl; + fp << "//\tDate: " << std::ctime(&end_time) ; fp << "//-------------------------------------------" << std::endl; fp << "//----- Time scale -----" << std::endl; fp << "`timescale 1ns / 1ps" << std::endl; From a335a57c6c565f263efb447b3e1636e4e705a5a5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 21 Aug 2019 11:08:13 -0600 Subject: [PATCH 095/482] Added debug option to commnad line arguments --- .travis/script.sh | 10 +++------- openfpga_flow/scripts/run_fpga_flow.py | 7 +++++++ openfpga_flow/scripts/run_fpga_task.py | 12 +++++++++--- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index dc7e22986..18845748b 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -10,9 +10,9 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then #make mkdir build cd build - cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off + cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off make -j2 -else +else # For linux, we enable full package compilation #make mkdir build @@ -26,8 +26,4 @@ end_section "OpenFPGA.build" $SPACER cd - -./.travis/regression.sh - -#cd fpga_flow -#./regression_fpga_flow.sh -#cd - +python3.5 ./openfpga_flow/scripts/run_fpga_task.py basic_flow diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 2a01e561e..b3d5adef7 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -57,6 +57,8 @@ parser.add_argument('--run_dir', type=str, help="Directory to store intermidiate file & final results") parser.add_argument('--yosys_tmpl', type=str, help="Alternate yosys template, generates top_module.blif") +parser.add_argument('--debug', action="store_true", + help="Run script in debug mode") # ACE2 and power estimation related arguments parser.add_argument('--K', type=int, @@ -249,6 +251,10 @@ def validate_command_line_arguments(): """ logger.info("Validating commnad line arguments") + if args.debug: + logger.info("Setting loggger in debug mode") + logger.setLevel(logging.DEBUG) + # Check if flow supported if not args.fpga_flow in config.get("FLOW_SCRIPT_CONFIG", "valid_flows"): clean_up_and_exit("%s Flow not supported"%args.fpga_flow) @@ -780,6 +786,7 @@ def run_netlists_verification(): def run_command(taskname, logfile, command, exit_if_fail=True): + logger.info("Launching %s " % taskname) try: with open(logfile, 'w+') as output: output.write(" ".join(command)+"\n") diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 6d1bf4a4b..4ff388cd2 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -33,6 +33,8 @@ parser.add_argument('--maxthreads', type=int, default=2, parser.add_argument('--config', help="Override default configuration") parser.add_argument('--test_run', action="store_true", help="Dummy run shows final generated VPR commands") +parser.add_argument('--debug', action="store_true", + help="Run script in debug mode") args = parser.parse_args() # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = @@ -76,7 +78,9 @@ def clean_up_and_exit(msg): def validate_command_line_arguments(): - pass + if args.debug: + logger.info("Setting loggger in debug mode") + logger.setLevel(logging.DEBUG) def generate_each_task_actions(taskname): @@ -143,7 +147,8 @@ def generate_each_task_actions(taskname): " with path %s " % (eachpath)) bench_files += files - ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common") + ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common", + fallback="") benchmark_list.append({ "files": bench_files, "top_module": task_conf.get("SYNTHESIS_PARAM", bech_name+"_top", @@ -218,7 +223,8 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): # Add other paramters to pass for key, values in task_conf["SCRIPT_PARAM"].items(): - command += ["--"+key, values] + if args.debug: + command += ["--debug"] return command From e51ff447105528e09002f9b3cd509df39f2e6e0e Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 21 Aug 2019 11:08:47 -0600 Subject: [PATCH 096/482] Added execution time information in logs --- openfpga_flow/scripts/run_fpga_task.py | 43 +++++++++++++++++++------- 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 4ff388cd2..6009ad22b 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -2,6 +2,7 @@ import os import sys import shutil import time +from datetime import timedelta import shlex import argparse from configparser import ConfigParser, ExtendedInterpolation @@ -13,6 +14,10 @@ import csv from string import Template import run_fpga_flow import pprint +import importlib + +if importlib.util.find_spec("humanize"): + import humanize # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system @@ -35,6 +40,8 @@ parser.add_argument('--test_run', action="store_true", help="Dummy run shows final generated VPR commands") parser.add_argument('--debug', action="store_true", help="Run script in debug mode") +parser.add_argument('--skip_tread_logs', action="store_true", + help="Skips logs from running thread") args = parser.parse_args() # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = @@ -220,9 +227,13 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): command += ["--vpr_fpga_spice"] if task_conf.getboolean("GENERAL", "verilog_output", fallback=False): command += ["--vpr_fpga_verilog"] + command += ["--vpr_fpga_verilog_dir", "."] + command += ["--vpr_fpga_x2p_rename_illegal_port"] # Add other paramters to pass for key, values in task_conf["SCRIPT_PARAM"].items(): + command += ["--"+key, values] if values else ["--"+key] + if args.debug: command += ["--debug"] return command @@ -234,23 +245,31 @@ def run_single_script(s, eachJob): logger.debug("Running OpenFPGA flow with " + " ".join(eachJob["commands"])) name = threading.currentThread().getName() + eachJob["starttime"] = time.time() try: logfile = "%s_out.log" % name with open(logfile, 'w+') as output: - process = subprocess.run(["python3.5", - gc["script_default"]] + - eachJob["commands"], - check=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - universal_newlines=True) - output.write(process.stdout) + process = subprocess.Popen(["python3.5", + gc["script_default"]] + + eachJob["commands"], + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + universal_newlines=True) + for line in process.stdout: + if not args.skip_tread_logs: + logging.info(line[:-1]) + sys.stdout.buffer.flush() + output.write(line) + process.wait() eachJob["status"] = True except: - logger.error("Failed to execute openfpga flow - " + - eachJob["name"]) - # logger.exception("Failed to launch openfpga flow") - logger.info("%s Finished " % name) + logger.exception("Failed to execute openfpga flow - " + + eachJob["name"]) + eachJob["endtime"] = time.time() + timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) + timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \ + else str(timediff) + logger.info("%s Finished, Time Taken %s " % (name, timestr)) def run_actions(job_run_list): From 2f0acfad23c938db68feb3d147573d4705a17a32 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 21 Aug 2019 11:09:53 -0600 Subject: [PATCH 097/482] Updated travis to run regression task --- .travis/regression.sh | 50 ------------------- .travis/script.sh | 2 +- .../config/golden_results.txt | 2 + .../regression_quick/config/task.conf | 38 ++++++++++++++ 4 files changed, 41 insertions(+), 51 deletions(-) delete mode 100755 .travis/regression.sh create mode 100644 openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt create mode 100644 openfpga_flow/tasks/regression/regression_quick/config/task.conf diff --git a/.travis/regression.sh b/.travis/regression.sh deleted file mode 100755 index 5d9be167d..000000000 --- a/.travis/regression.sh +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/bash -# Regression test version 1.0 - -# Set variables -my_pwd=$PWD -fpga_flow_scripts=${my_pwd}/fpga_flow/scripts -vpr_path=${my_pwd}/vpr7_x2p/vpr -benchmark="test_modes" -include_netlists="_include_netlists.v" -compiled_file="compiled_$benchmark" -tb_formal_postfix="_top_formal_verification_random_tb" -verilog_output_dirname="${benchmark}_Verilog" -log_file="${benchmark}_sim.log" -new_reg_sh="my_regression.sh" - - -cd $fpga_flow_scripts - -perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh -o $vpr_path/$new_reg_sh - -cd $my_pwd - -# Move to vpr folder -cd $vpr_path - -# Remove former log file -rm -f $log_file -rm -f $compiled_file - -# Start the script -> run the fpga generation -> run the simulation -> check the log file -source $new_reg_sh -iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix -vvp $compiled_file -j 16 >> $log_file - -result=`grep "Succeed" $log_file` -if ["$result" = ""]; then - result=`grep "Failed" $log_file` - if ["$result" = ""]; then - echo "Unexpected error, Verification didn't run" - cd $my_pwd - exit 1 - else - echo "Verification failed" - cd $my_pwd - exit 2 - fi -else - echo "Verification succeed" - cd $my_pwd -fi diff --git a/.travis/script.sh b/.travis/script.sh index 18845748b..e0c463239 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -26,4 +26,4 @@ end_section "OpenFPGA.build" $SPACER cd - -python3.5 ./openfpga_flow/scripts/run_fpga_task.py basic_flow +python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick diff --git a/openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt b/openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt new file mode 100644 index 000000000..edde206c7 --- /dev/null +++ b/openfpga_flow/tasks/regression/regression_quick/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 298 249 10 10 19 99 130 1 0 2262 2.74023 -250.655 -2.74023 42 2555 15 2250 12 3.5255 -318.677 -3.5255 0 0 3.92691e+06 1.57199e+06 236681. 2366.81 297605. 2976.05 0.03 0.00 -1 -1 -1 0.15 0.27 0.64 0.06 1.70 -1 -1 -1 diff --git a/openfpga_flow/tasks/regression/regression_quick/config/task.conf b/openfpga_flow/tasks/regression/regression_quick/config/task.conf new file mode 100644 index 000000000..277a3b6b7 --- /dev/null +++ b/openfpga_flow/tasks/regression/regression_quick/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_22nm/22nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/tseng/tseng.v + +[SYNTHESIS_PARAM] +bench0_top = s298 +bench1_top = alu4 +bench2_top = tseng + +[SCRIPT_PARAM] +min_route_chan_width=1.3 +end_flow_with_test= +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= + +[POST_RUN] \ No newline at end of file From 764d7039b5655b30c7376b913fa72c217b32854e Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 21 Aug 2019 12:42:58 -0600 Subject: [PATCH 098/482] Import utils bug fixing for travis test --- openfpga_flow/scripts/run_fpga_task.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 6009ad22b..f5fd08b0e 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -14,9 +14,9 @@ import csv from string import Template import run_fpga_flow import pprint -import importlib +from importlib import util -if importlib.util.find_spec("humanize"): +if util.find_spec("humanize"): import humanize # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = From 9c43b1b753fd84629f2177bdf981efe6e1d49874 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 14:54:05 -0600 Subject: [PATCH 099/482] complete refacotriing the inv and buf part in submodules --- .../arch_lang/circuit_model_examples.rst | 19 +- docs/source/arch_lang/circuit_modules.rst | 14 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 83 +++++++- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 22 ++- vpr7_x2p/libarchfpga/SRC/device_port.cpp | 35 +++- vpr7_x2p/libarchfpga/SRC/device_port.h | 18 +- .../verilog/verilog_essential_gates.cpp | 177 ++++++++---------- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 28 +-- .../verilog/verilog_submodule_utils.cpp | 112 +++++++++++ .../verilog/verilog_submodule_utils.h | 21 +++ 10 files changed, 381 insertions(+), 148 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst index 9cde3e5cf..c7b6891fb 100644 --- a/docs/source/arch_lang/circuit_model_examples.rst +++ b/docs/source/arch_lang/circuit_model_examples.rst @@ -17,11 +17,11 @@ Inverters and Buffers * design_technology: - * **topology:** [inverter|buffer]. Specify the type of this component, can be either an inverter or a buffer. + * **topology:** [``inverter`` | ``buffer``]. Specify the type of this component, can be either an inverter or a buffer. * **size:** Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. We consider a two-level structure for a buffer here. The support for multi-level structure of a buffer will be introduced in the tapered options. - * **tapered:** [on|off]. Define if the buffer is a tapered (multi-level) buffer. *If "on" the following parameter are required.* + * **tapered:** [``on`` | ``off``]. Define if the buffer is a tapered (multi-level) buffer. *If ``on`` the following parameter are required.* * **tap_drive_level:** Define the number of levels of a tapered buffer. This parameter is valid only when tapered is turned on. @@ -54,6 +54,21 @@ This example shows: * Size of 1 for the output strength * The tapered parameter is not declared and is off by default +**Power-gated Inverter x1 example** + +The XML code describing an inverter which can be power-gated by the control signals ``EN`` and ``ENB`` : + +.. code-block:: xml + + + + + + + + + +.. note:: For power-gated inverters: all the control signals must be set as ``config_enable`` so that the testbench generation will generate testing waveforms. If the power-gated inverters are auto-generated , all the ``config_enable`` signals must be ``global`` signals as well. If the pwoer-gated inverters come from user-defined netlists, restrictions on ``global`` signals are free. **Buffer x2 example** diff --git a/docs/source/arch_lang/circuit_modules.rst b/docs/source/arch_lang/circuit_modules.rst index b4ab2b201..8454de53a 100644 --- a/docs/source/arch_lang/circuit_modules.rst +++ b/docs/source/arch_lang/circuit_modules.rst @@ -22,13 +22,13 @@ Define circuit_models * **circuit_model**: the child node defining transistor-level modeling parameters. - * **type**: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | scff | hard_logic | iopad ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-Verilog/SPICE can auto-generate Verilog/SPICE netlists. For the rest, FPGA-Verilog/SPICE requires a user-defined Verilog/SPICE netlist. + * **type**: can be [ ``inv_buf`` | ``pass_gate`` | ``gate`` | ``mux`` | ``wire`` | ``chan_wire`` | ``sram`` | ``lut`` | ``ff`` | ``scff`` | ``hard_logic`` | ``iopad`` ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-Verilog/SPICE can auto-generate Verilog/SPICE netlists. For the rest, FPGA-Verilog/SPICE requires a user-defined Verilog/SPICE netlist. * **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in Verilog/SPICE netlists. Note that for a customized Verilog/SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized Verilog/SPICE netlist. FPGA-Verilog/SPICE will check if the given name is conflicted with any reserved words. * **prefix**: specify the name of the circuit_model to shown in the auto-generated Verilog/SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique. - * **is_default**: can be [1|0], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-Verilog/SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default. + * **is_default**: can be [``1`` | ``0``], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-Verilog/SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default. * **spice_netlist**: specify the path and file name of a customized Verilog/SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. @@ -87,14 +87,14 @@ Transistor level * **circuit_model_name:** only valid when the type of port is sram. Specify the name of the circuit model which is connected to this port. - * **mode_select:** can be either true or false. Specify if this port controls the mode switching in a configurable logic block. Only valid when the type of this port is sram. (A configurable logic block can operate in different modes, which is controlled by SRAM bits.) + * **mode_select:** can be either ``true`` or ``false``. Specify if this port controls the mode switching in a configurable logic block. Only valid when the type of this port is sram. (A configurable logic block can operate in different modes, which is controlled by SRAM bits.) - * **is_global:** can be either true or false. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together. + * **is_global:** can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together. - * **is_set:** can be either true or false. Specify if this port controls a set signal. Only valid when is_global is true. All the set ports are connected to global set voltage stimuli in testbenches. + * **is_set:** can be either ``true`` or ``false``. Specify if this port controls a set signal. Only valid when is_global is true. All the set ports are connected to global set voltage stimuli in testbenches. - * **is_reset:** can be either true or false. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches. + * **is_reset:** can be either ``true`` or ``false``. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches. - * **is_config_enable:** can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to global configuration-enable voltage stimuli in testbenches. + * **is_config_enable:** can be either ``true`` or ``false``. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to global configuration-enable voltage stimuli in testbenches. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details. diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 35278893c..41a7d61db 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -269,6 +269,24 @@ enum e_spice_model_buffer_type CircuitLibrary::buffer_type(const CircuitModelId& return buffer_types_[model_id]; } +/* Return the number of levels of buffer for a circuit model + * Only applicable for BUF/INV circuit model + */ +size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + return buffer_num_levels_[model_id]; +} + +/* Return the number of levels of delay types for a circuit model */ +size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return delay_types_[model_id].size(); +} + /************************************************************************ * Public Accessors : Basic data query on Circuit models' Circuit Port ***********************************************************************/ @@ -571,6 +589,57 @@ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { return port_is_prog_[circuit_port_id]; } +/************************************************************************ + * Public Accessors : Methods to visit timing graphs + ***********************************************************************/ +/* Find all the edges belonging to a circuit model */ +std::vector CircuitLibrary::timing_edges_by_model(const CircuitModelId& model_id) const { + /* Validate the model id */ + VTR_ASSERT_SAFE(valid_model_id(model_id)); + + std::vector model_edges; + for (const auto& edge : edge_ids_) { + /* Bypass edges whose parent is not the model_id */ + if (model_id != edge_parent_model_ids_[edge]) { + continue; + } + /* Update the edge list */ + model_edges.push_back(edge); + } + return model_edges; +} + +/* Get source/sink nodes and delay of edges */ +CircuitPortId CircuitLibrary::timing_edge_src_port(const CircuitEdgeId& edge) const { + /* Validate the edge id */ + VTR_ASSERT_SAFE(valid_edge_id(edge)); + return edge_src_port_ids_[edge]; +} + +size_t CircuitLibrary::timing_edge_src_pin(const CircuitEdgeId& edge) const { + /* Validate the edge id */ + VTR_ASSERT_SAFE(valid_edge_id(edge)); + return edge_src_pin_ids_[edge]; +} + +CircuitPortId CircuitLibrary::timing_edge_sink_port(const CircuitEdgeId& edge) const { + /* Validate the edge id */ + VTR_ASSERT_SAFE(valid_edge_id(edge)); + return edge_sink_port_ids_[edge]; +} + +size_t CircuitLibrary::timing_edge_sink_pin(const CircuitEdgeId& edge) const { + /* Validate the edge id */ + VTR_ASSERT_SAFE(valid_edge_id(edge)); + return edge_sink_pin_ids_[edge]; +} + +float CircuitLibrary::timing_edge_delay(const CircuitEdgeId& edge, const enum spice_model_delay_type& delay_type) const { + /* Validate the edge id */ + VTR_ASSERT_SAFE(valid_edge_id(edge)); + return edge_timing_info_[edge][delay_type]; +} + /************************************************************************ * Public Accessors : Methods to find circuit model ***********************************************************************/ @@ -1498,7 +1567,7 @@ void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { continue; } /* Add an edge to bridge the from_pin_id and to_pin_id */ - add_edge(from_port_id, from_pin_id, to_port_id, to_pin_id); + add_edge(model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); } } } @@ -1540,14 +1609,19 @@ void CircuitLibrary::build_timing_graphs() { * Internal mutators: build timing graphs ***********************************************************************/ /* Add an edge between two pins of two ports, and assign an default timing value */ -void CircuitLibrary::add_edge(const CircuitPortId& from_port, const size_t& from_pin, +void CircuitLibrary::add_edge(const CircuitModelId& model_id, + const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* Create an edge in the edge id list */ CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_.size()); /* Expand the edge list */ edge_ids_.push_back(edge_id); /* Initialize other attributes */ + edge_parent_model_ids_.push_back(model_id); /* Update the list of incoming edges for to_port */ /* Resize upon need */ @@ -1757,6 +1831,11 @@ bool CircuitLibrary::valid_circuit_pin_id(const CircuitPortId& circuit_port_id, return ( size_t(pin_id) < port_size(circuit_port_id) ); } +bool CircuitLibrary::valid_edge_id(const CircuitEdgeId& edge_id) const { + /* validate the model_id */ + return ( size_t(edge_id) < edge_ids_.size() ) && ( edge_id == edge_ids_[edge_id] ); +} + bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 34debee59..d5842f049 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -218,16 +218,25 @@ class CircuitLibrary { bool dump_explicit_port_map(const CircuitModelId& model_id) const; enum e_spice_model_design_tech design_tech_type(const CircuitModelId& model_id) const; bool is_power_gated(const CircuitModelId& model_id) const; + /* General buffer information */ bool is_input_buffered(const CircuitModelId& model_id) const; bool is_output_buffered(const CircuitModelId& model_id) const; + /* LUT-related information */ bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; + /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; + /* Multiplexer information */ enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const; size_t mux_num_levels(const CircuitModelId& model_id) const; bool mux_add_const_input(const CircuitModelId& model_id) const; size_t mux_const_input_value(const CircuitModelId& model_id) const; + /* Gate information */ enum e_spice_model_gate_type gate_type(const CircuitModelId& model_id) const; + /* Buffer information */ enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const; + size_t buffer_num_levels(const CircuitModelId& model_id) const; + /* Delay information */ + size_t num_delay_info(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ CircuitPortId model_port(const CircuitModelId& model_id, const std::string& name) const; size_t num_model_ports(const CircuitModelId& model_id) const; @@ -256,6 +265,14 @@ class CircuitLibrary { bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; + public: /* Public Accessors: Timing graph */ + /* Get source/sink nodes and delay of edges */ + std::vector timing_edges_by_model(const CircuitModelId& model_id) const; + CircuitPortId timing_edge_src_port(const CircuitEdgeId& edge) const; + size_t timing_edge_src_pin(const CircuitEdgeId& edge) const; + CircuitPortId timing_edge_sink_port(const CircuitEdgeId& edge) const; + size_t timing_edge_sink_pin(const CircuitEdgeId& edge) const; + float timing_edge_delay(const CircuitEdgeId& edge, const enum spice_model_delay_type& delay_type) const; public: /* Public Accessors: Methods to find circuit model */ CircuitModelId model(const char* name) const; CircuitModelId model(const std::string& name) const; @@ -411,7 +428,8 @@ class CircuitLibrary { void build_model_links(); void build_timing_graphs(); public: /* Internal mutators: build timing graphs */ - void add_edge(const CircuitPortId& from_port, const size_t& from_pin, + void add_edge(const CircuitModelId& model_id, + const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin); void set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, @@ -427,6 +445,7 @@ class CircuitLibrary { bool valid_model_id(const CircuitModelId& model_id) const; bool valid_circuit_port_id(const CircuitPortId& circuit_port_id) const; bool valid_circuit_pin_id(const CircuitPortId& circuit_port_id, const size_t& pin_id) const; + bool valid_edge_id(const CircuitEdgeId& edge_id) const; bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const; bool valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const; bool valid_mux_const_input_value(const size_t& const_input_value) const; @@ -497,6 +516,7 @@ class CircuitLibrary { /* Timing graphs */ vtr::vector edge_ids_; + vtr::vector edge_parent_model_ids_; vtr::vector> port_in_edge_ids_; vtr::vector> port_out_edge_ids_; vtr::vector edge_src_port_ids_; diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.cpp b/vpr7_x2p/libarchfpga/SRC/device_port.cpp index 2e181fce5..2de15172d 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.cpp +++ b/vpr7_x2p/libarchfpga/SRC/device_port.cpp @@ -13,6 +13,27 @@ BasicPort::BasicPort() { msb_ = 0; } +/* Quick constructor */ +BasicPort::BasicPort(const char* name, const size_t& lsb, const size_t& msb) { + set_name(std::string(name)); + set_width(lsb, msb); +} + +BasicPort::BasicPort(const std::string& name, const size_t& lsb, const size_t& msb) { + set_name(name); + set_width(lsb, msb); +} + +BasicPort::BasicPort(const char* name, const size_t& width) { + set_name(std::string(name)); + set_width(width); +} + +BasicPort::BasicPort(const std::string& name, const size_t& width) { + set_name(name); + set_width(width); +} + /* Copy constructor */ BasicPort::BasicPort(const BasicPort& basic_port) { set(basic_port); @@ -59,7 +80,7 @@ void BasicPort::set_name(const std::string& name) { } /* set the port LSB and MSB */ -void BasicPort::set_width(size_t width) { +void BasicPort::set_width(const size_t& width) { if (0 == width) { make_invalid(); return; @@ -70,7 +91,7 @@ void BasicPort::set_width(size_t width) { } /* set the port LSB and MSB */ -void BasicPort::set_width(size_t lsb, size_t msb) { +void BasicPort::set_width(const size_t& lsb, const size_t& msb) { /* If lsb and msb is invalid, we make a default port */ if (lsb > msb) { make_invalid(); @@ -81,18 +102,18 @@ void BasicPort::set_width(size_t lsb, size_t msb) { return; } -void BasicPort::set_lsb(size_t lsb) { +void BasicPort::set_lsb(const size_t& lsb) { lsb_ = lsb; return; } -void BasicPort::set_msb(size_t msb) { +void BasicPort::set_msb(const size_t& msb) { msb_ = msb; return; } /* Increase the port width */ -void BasicPort::expand(size_t width) { +void BasicPort::expand(const size_t& width) { if (0 == width) { return; /* ignore zero-width port */ } @@ -114,7 +135,7 @@ void BasicPort::revert() { } /* rotate: increase both lsb and msb by an offset */ -bool BasicPort::rotate(size_t offset) { +bool BasicPort::rotate(const size_t& offset) { /* If current port is invalid or offset is 0, * we do nothing */ @@ -134,7 +155,7 @@ bool BasicPort::rotate(size_t offset) { } /* rotate: decrease both lsb and msb by an offset */ -bool BasicPort::counter_rotate(size_t offset) { +bool BasicPort::counter_rotate(const size_t& offset) { /* If current port is invalid or offset is 0, * we do nothing */ diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.h b/vpr7_x2p/libarchfpga/SRC/device_port.h index fbf887421..21666dcb4 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.h +++ b/vpr7_x2p/libarchfpga/SRC/device_port.h @@ -11,6 +11,10 @@ class BasicPort { public: /* Constructors */ BasicPort(); + BasicPort(const char* name, const size_t& lsb, const size_t& msb); + BasicPort(const char* name, const size_t& width); + BasicPort(const std::string& name, const size_t& lsb, const size_t& msb); + BasicPort(const std::string& name, const size_t& width); BasicPort(const BasicPort& basic_port); /* Copy constructor */ public: /* Accessors */ size_t get_width() const; /* get the port width */ @@ -21,14 +25,14 @@ class BasicPort { public: /* Mutators */ void set(const BasicPort& basic_port); /* copy */ void set_name(const std::string& name); /* set the port LSB and MSB */ - void set_width(size_t width); /* set the port LSB and MSB */ - void set_width(size_t lsb, size_t msb); /* set the port LSB and MSB */ - void set_lsb(size_t lsb); - void set_msb(size_t msb); - void expand(size_t width); /* Increase the port width */ + void set_width(const size_t& width); /* set the port LSB and MSB */ + void set_width(const size_t& lsb, const size_t& msb); /* set the port LSB and MSB */ + void set_lsb(const size_t& lsb); + void set_msb(const size_t& msb); + void expand(const size_t& width); /* Increase the port width */ void revert(); /* Swap lsb and msb */ - bool rotate(size_t offset); /* rotate */ - bool counter_rotate(size_t offset); /* counter rotate */ + bool rotate(const size_t& offset); /* rotate */ + bool counter_rotate(const size_t& offset); /* counter rotate */ void reset(); /* Reset to initial port */ void combine(const BasicPort& port); /* Combine two ports */ private: /* internal functions */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index c0707616c..cbe8d258a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -1,6 +1,5 @@ /************************************************ - * Header file for verilog_submodule_essential.cpp - * Include function declaration on + * This file includes functions on * outputting Verilog netlists for essential gates * which are inverters, buffers, transmission-gates * logic gates etc. @@ -17,17 +16,20 @@ /* FPGA-Verilog context header files */ #include "verilog_global.h" #include "verilog_writer_utils.h" +#include "verilog_submodule_utils.h" #include "verilog_essential_gates.h" /************************************************ - * Print Verilog codes of a power-gated inverter + * Print Verilog body codes of a power-gated inverter + * This function does NOT generate any port map ! ***********************************************/ static -void print_verilog_power_gated_inv_module(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitPortId& input_port, - const CircuitPortId& output_port, - const std::vector& power_gate_ports) { +void print_verilog_power_gated_invbuf_body(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitPortId& input_port, + const CircuitPortId& output_port, + const std::vector& power_gate_ports) { /* Ensure a valid file handler*/ check_file_handler(fp); @@ -72,7 +74,21 @@ void print_verilog_power_gated_inv_module(std::fstream& fp, } fp << ") begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = ~" << circuit_lib.port_lib_name(input_port) << ";" << std::endl; + fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = "; + + /* Branch on the type of inverter/buffer: + * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, + * we invert the input to output + * 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages, + * we wire the input to output + */ + if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + || ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { + fp << "~"; + } + + fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; fp << "\t\tend else begin" << std::endl; fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = 1'bz;" << std::endl; fp << "\t\tend" << std::endl; @@ -80,6 +96,38 @@ void print_verilog_power_gated_inv_module(std::fstream& fp, fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; } +/************************************************ + * Print Verilog body codes of a regular inverter + * This function does NOT generate any port map ! + ***********************************************/ +static +void print_verilog_invbuf_body(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitPortId& input_port, + const CircuitPortId& output_port) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + fp << "//----- Verilog codes of a regular inverter -----" << std::endl; + + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " == 1'bz)? $random : "; + + /* Branch on the type of inverter/buffer: + * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, + * we invert the input to output + * 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages, + * we wire the input to output + */ + if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + || ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { + fp << "~"; + } + + fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; +} + /************************************************ * Print a Verilog module of inverter or buffer * or tapered buffer to a file @@ -158,107 +206,32 @@ void print_verilog_invbuf_module(std::fstream& fp, /* Finish dumping ports */ /* Assign logics : depending on topology */ - switch (circuit_lib.buffer_type(circuit_model)) { - case SPICE_MODEL_BUF_INV: - if (TRUE == circuit_lib.is_power_gated(circuit_model)) { - print_verilog_power_gated_inv_module(fp, circuit_lib, input_ports[0], output_ports[0], global_ports); - } -// } else { -// fprintf(fp, "assign %s = (%s === 1'bz)? $random : ~%s;\n", -// output_port[0]->lib_name, -// input_port[0]->lib_name, -// input_port[0]->lib_name); -// } - break; - case SPICE_MODEL_BUF_BUF: -// if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { -// /* Create a sensitive list */ -// fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); -// fprintf(fp, "always @("); -// /* Power-gate port first*/ -// for (iport = 0; iport < num_powergate_port; iport++) { -// fprintf(fp, "%s,", powergate_port[iport]->lib_name); -// } -// fprintf(fp, "%s) begin\n", -// input_port[0]->lib_name); -// /* Dump the case of power-gated */ -// fprintf(fp, " if ("); -// port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ -// for (iport = 0; iport < num_powergate_port; iport++) { -// if (0 == powergate_port[iport]->default_val) { -// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { -// if ( 0 < port_cnt ) { -// fprintf(fp, "\n\t&&"); -// } -// /* Power-gated signal are disable during operating, enabled during configuration, -// * Therefore, we need to reverse them here -// */ -// fprintf(fp, "(~%s[%d])", -// powergate_port[iport]->lib_name, -// ipin); -// port_cnt++; /* Update port counter*/ -// } -// } else { -// assert (1 == powergate_port[iport]->default_val); -// for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { -// if ( 0 < port_cnt ) { -// fprintf(fp, "\n\t&&"); -// } -// /* Power-gated signal are disable during operating, enabled during configuration, -// * Therefore, we need to reverse them here -// */ -// fprintf(fp, "(%s[%d])", -// powergate_port[iport]->lib_name, -// ipin); -// port_cnt++; /* Update port counter*/ -// } -// } -// } -// fprintf(fp, ") begin\n"); -// fprintf(fp, "\t\tassign %s_reg = %s;\n", -// output_port[0]->lib_name, -// input_port[0]->lib_name); -// fprintf(fp, "\tend else begin\n"); -// fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", -// output_port[0]->lib_name); -// fprintf(fp, "\tend\n"); -// fprintf(fp, "end\n"); -// fprintf(fp, "assign %s = %s_reg;\n", -// output_port[0]->lib_name, -// output_port[0]->lib_name); -// -// } else if (FALSE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf) { -// fprintf(fp, "assign %s = (%s === 1'bz)? $random : %s;\n", -// output_port[0]->lib_name, -// input_port[0]->lib_name, -// input_port[0]->lib_name); -// } else { -// assert (TRUE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf); -// fprintf(fp, "assign %s = (%s === 1'bz)? $random : ", -// output_port[0]->lib_name, -// input_port[0]->lib_name); -// /* depend on the stage, we may invert the output */ -// if (1 == invbuf_spice_model->design_tech_info.buffer_info->tap_buf_level % 2) { -// fprintf(fp, "~"); -// } -// fprintf(fp, "%s;\n", -// input_port[0]->lib_name); -// } - break; - default: + /* Error out for unsupported technology */ + if ( ( SPICE_MODEL_BUF_INV != circuit_lib.buffer_type(circuit_model)) + && ( SPICE_MODEL_BUF_BUF != circuit_lib.buffer_type(circuit_model)) ) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); exit(1); } -// -// /* Print timing info */ -// dump_verilog_submodule_timing(fp, invbuf_spice_model); -// -// dump_verilog_submodule_signal_init(fp, invbuf_spice_model); + + if (TRUE == circuit_lib.is_power_gated(circuit_model)) { + /* Output Verilog codes for a power-gated inverter */ + print_verilog_power_gated_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0], global_ports); + } else { + /* Output Verilog codes for a regular inverter */ + print_verilog_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0]); + } + + /* Print timing info */ + print_verilog_submodule_timing(fp, circuit_lib, circuit_model); + + print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); fp << "endmodule" << std::endl << std::endl; + fp << "//----- END Verilog module for " << circuit_lib.model_name(circuit_model) << " -----" << std::endl; + return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 277a3ece8..2d12c11d7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -75,32 +75,20 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, fp << "module " << module_name << "(" << std::endl; /* Create port information */ - BasicPort input_port; /* Configure each input port */ - input_port.set_name(std::string("in")); - input_port.set_width(num_inputs); + BasicPort input_port("in", num_inputs); - BasicPort output_port; - /* Configure each input port */ - output_port.set_name(std::string("out")); - output_port.set_width(num_outputs); + /* Configure each output port */ + BasicPort output_port("out", num_outputs); - BasicPort mem_port; - /* Configure each input port */ - mem_port.set_name(std::string("mem")); - mem_port.set_width(num_mems); - - BasicPort mem_inv_port; - /* Configure each input port */ - mem_inv_port.set_name(std::string("mem_inv")); - mem_inv_port.set_width(num_mems); + /* Configure each memory port */ + BasicPort mem_port("mem", num_mems); + BasicPort mem_inv_port("mem_inv", num_mems); /* TODO: Generate global ports */ for (const auto& port : tgate_global_ports) { - BasicPort basic_port; - /* Configure each input port */ - basic_port.set_name(circuit_lib.port_prefix(port)); - basic_port.set_width(circuit_lib.port_size(port)); + /* Configure each global port */ + BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); /* Print port */ fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp new file mode 100644 index 000000000..696c61842 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -0,0 +1,112 @@ +/************************************************ + * This file includes most utilized functions for + * generating Verilog sub-modules + * such as timing matrix and signal initialization + ***********************************************/ +#include +#include +#include +#include "vtr_assert.h" + +/* Device-level header files */ +#include "spice_types.h" +#include "device_port.h" + +/* FPGA-X2P context header files */ +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_submodule_utils.h" + +/* All values are printed with this precision value. The higher the + * value, the more accurate timing assignment is. Using numeric_limits + * max_digits10 guarentees that no values change during a sequence of + * float -> string -> float conversions */ +constexpr int FLOAT_PRECISION = std::numeric_limits::max_digits10; + +/************************************************ + * Print a timing matrix defined in theecircuit model + * into a Verilog format. + * This function print all the timing edges available + * in the circuit model (any pin-to-pin delay) + ***********************************************/ +void print_verilog_submodule_timing(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* return if there is no delay info */ + if ( 0 == circuit_lib.num_delay_info(circuit_model)) { + return; + } + + /* Return if there is no ports */ + if (0 == circuit_lib.num_model_ports(circuit_model)) { + return; + } + + /* Ensure a valid file handler*/ + check_file_handler(fp); + + fp << std::endl; + fp << "`ifdef " << verilog_timing_preproc_flag << std::endl; + fp << "//------ BEGIN Pin-to-pin Timing constraints -----" << std::endl; + fp << "\tspecify" << std::endl; + + /* Read out pin-to-pin delays by finding out all the edges belonging to a circuit model */ + for (const auto& timing_edge : circuit_lib.timing_edges_by_model(circuit_model)) { + CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge); + size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge); + BasicPort src_port_info(circuit_lib.port_lib_name(src_port), src_pin, src_pin); + + CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge); + size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge); + BasicPort sink_port_info(circuit_lib.port_lib_name(sink_port), sink_pin, sink_pin); + + fp << "\t\t"; + fp << "(" << generate_verilog_port(VERILOG_PORT_CONKT, src_port_info); + fp << " => "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")"; + fp << " = "; + fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE); + fp << " => "; + fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) << ")"; + fp << ";" << std::endl; + } + + fp << "\tendspecify" << std::endl; + fp << "//------ END Pin-to-pin Timing constraints -----" << std::endl; + fp << "`endif" << std::endl; + +} + +void print_verilog_submodule_signal_init(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + fp << std::endl; + fp << "`ifdef " << verilog_signal_init_preproc_flag << std::endl; + fp << "//------ BEGIN driver initialization -----" << std::endl; + fp << "\tinitial begin" << std::endl; + fp << "\t`ifdef " << verilog_formal_verification_preproc_flag << std::endl; + + /* Only for formal verification: deposite a zero signal values */ + /* Initialize each input port */ + for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { + fp << "\t\t$deposit(" << circuit_lib.port_lib_name(input_port) << ", 1'b0);" << std::endl; + } + fp << "\t`else" << std::endl; + + /* Regular case: deposite initial signal values: a random value */ + for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { + fp << "\t\t$deposit(" << circuit_lib.port_lib_name(input_port) << ", $random);" << std::endl; + } + + fp << "\t`endif\n" << std::endl; + fp << "\tend" << std::endl; + fp << "//------ END driver initialization -----" << std::endl; + fp << "`endif" << std::endl; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h new file mode 100644 index 000000000..8d93deaaf --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h @@ -0,0 +1,21 @@ +/************************************************ + * Header file for verilog_submodule_utils.cpp + * Include function declaration on + * most utilized functions for Verilog modules + * such as timing matrix and signal initialization + ***********************************************/ + +#ifndef VERILOG_SUBMODULE_UTILS_H +#define VERILOG_SUBMODULE_UTILS_H + +#include + +void print_verilog_submodule_timing(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +void print_verilog_submodule_signal_init(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +#endif From 42b528be57516145cfbf04f476c2624cf9505445 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 15:11:25 -0600 Subject: [PATCH 100/482] doc updates --- .../arch_lang/circuit_model_examples.rst | 40 ++++++++++--------- docs/source/arch_lang/circuit_modules.rst | 20 +++++----- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst index c7b6891fb..0e49c3394 100644 --- a/docs/source/arch_lang/circuit_model_examples.rst +++ b/docs/source/arch_lang/circuit_model_examples.rst @@ -1,6 +1,6 @@ Circuit model examples ====================== -The next subsections are dedicated to detailed examples of each circuit model type. Through these examples awe give a global overview of the different implementations which are available for the user. +The next subsections are dedicated to detailed examples of each circuit model type. Through these examples, we give a global overview of the different implementations which are available for the user. Inverters and Buffers --------------------- @@ -21,7 +21,7 @@ Inverters and Buffers * **size:** Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. We consider a two-level structure for a buffer here. The support for multi-level structure of a buffer will be introduced in the tapered options. - * **tapered:** [``on`` | ``off``]. Define if the buffer is a tapered (multi-level) buffer. *If ``on`` the following parameter are required.* + * **tapered:** [``on`` | ``off``]. Define if the buffer is a tapered (multi-level) buffer. When ``on`` is defined, the following parameter are required.* * **tap_drive_level:** Define the number of levels of a tapered buffer. This parameter is valid only when tapered is turned on. @@ -147,7 +147,7 @@ Pass-gate Logic * design_technology: - * **topology:** [transmission_gate|pass_transistor]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor. + * **topology:** [``transmission_gate`` | ``pass_transistor``]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor. * **nmos_size:** the size of NMOS transistor in a transmission gate or pass_transistor, expressed in terms of the min_width defined in XML node . @@ -178,7 +178,7 @@ The XML code describing this pass-gate is: This example shows: - * Topology is **transmission_gate**, which means the component need entries for each transistor gate (pmos and nmos) + * Topology is ``transmission_gate``, which means the component need entries for each transistor gate (pmos and nmos) * 3 inputs considered, 1 for signal and 2 to control the transistors gates * No input or output buffer used, these parameters can be uninitialized @@ -206,7 +206,7 @@ The XML code describing this pass-gate is: This example shows: - * Topology is **pass_transistor**, which means the component need an entry for the transistor gate (nmos) + * Topology is ``pass_transistor``, which means the component need an entry for the transistor gate (nmos) * 2 inputs considered, 1 for signal and 1 to control the transistor gate * No input or output buffer used, these parameters can be uninitialized @@ -350,7 +350,7 @@ If we arbitrarily fix the number of Mux entries at 4, the following code could i **This example shows:** * The tree topology, 4 entries split in 2 2-to-1 Muxes then another one make the final selection. * The possibility to select the input or output buffers - * The number of entries parametrized by *size* in input port-type. + * The number of entries parametrized by ``size`` in input port-type. Look-Up Tables -------------- @@ -390,9 +390,9 @@ Instructions of defining design parameters: * **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers. -* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask. +* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, ``tri_state_map`` ="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask. -* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the tri_state_map. +* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the ``tri_state_map``. **LUT example** @@ -446,9 +446,11 @@ Flip-Flops Instructions of defining design parameters: -* **circuit_model type:** can be ff or scff. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop +* **circuit_model type:** can be ``ff`` or ``scff``. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop -* **port:** three types of ports (input, output and clock) should be defined. If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. +* **port:** three types of ports (``input``, ``output`` and ``clock``) should be defined. If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. + +.. note:: In a valid FPGA architecture, users should provide at least either a SCFF or a SRAM, so that the configurations can loaded to core logic. **FF example** @@ -528,15 +530,15 @@ Hard Logics Instructions of defining design parameters: -* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. +* **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. Routing Wire Segments --------------------- FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segments in FPGA architecture: - * One type is called **wire**, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively - * The other type is called **chan_wire**, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point. + * One type is called ``wire``, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively + * The other type is called ``chan_wire``, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point. .. code-block:: xml @@ -555,13 +557,13 @@ FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segme Instructions of defining design parameters: -* **type:** can be [wire|chan_wire]. The Verilog/SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing. +* **type:** can be [``wire`` | ``chan_wire``]. The Verilog/SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing. -* **port:** two types of ports (input and output) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. +* **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. * **wire_param:** - * **model_type:** can be [pi|T], corresponding to the π-type and T-type RC wire models. + * **model_type:** can be [``pi`` | ``T``], corresponding to the π-type and T-type RC wire models. * **res_val:** specify the total resistance of the wire * **cap_val:** specify the total capacitance of the wire. * **level:** specify the number of levels of the RC wire model. @@ -590,7 +592,7 @@ The code describing this wire is: **This example shows** - * How to use the *wire_param* for a π-type RC wire model + * How to use the ``wire_param`` for a π-type RC wire model * How to use this circuit_model to auto-generate the Verilog/SPICE netlist I/O pads @@ -615,7 +617,7 @@ I/O pads Instructions of defining design parameters: -* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. +* **port:** four types of ports (``input``, ``output``, ``inout`` and ``sram``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. **IO-pad example** @@ -643,6 +645,6 @@ The code describing this IO-Pad is: **This example shows** - * The association of the verilog netlist file *io.v* + * The association of the verilog netlist file ``io.v`` * The inout pad port_type, which means as inout as output. * The instantiation of a SCFF as sram diff --git a/docs/source/arch_lang/circuit_modules.rst b/docs/source/arch_lang/circuit_modules.rst index 8454de53a..6a6825a82 100644 --- a/docs/source/arch_lang/circuit_modules.rst +++ b/docs/source/arch_lang/circuit_modules.rst @@ -13,12 +13,12 @@ Define circuit_models + circuit_netlist="string" verilog_netlist="string" dump_structural_verilog="string"> -* **module_circuit_models**: the father node for all the spice models. All the spice models should be defined under this XML node. +* **module_circuit_models**: the father node for all the circuit models. All the circuit models should be defined under this XML node. * **circuit_model**: the child node defining transistor-level modeling parameters. @@ -28,9 +28,9 @@ Define circuit_models * **prefix**: specify the name of the circuit_model to shown in the auto-generated Verilog/SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique. - * **is_default**: can be [``1`` | ``0``], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-Verilog/SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default. + * **is_default**: can be [``1`` | ``0``], corresponding to [``true`` | ``false``] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any circuit model by users, FPGA-Verilog/SPICE will find the default circuit model defined in the same type and link. For a circuit model type, only one circuit model can be set as default. - * **spice_netlist**: specify the path and file name of a customized Verilog/SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. + * **circuit_netlist**: specify the path and file name of a customized Verilog/SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. * **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined. @@ -40,7 +40,7 @@ Define circuit_models .. note:: The user-defined netlists, such as LUTs, the decoding methodology should comply with the auto-generated LUTs (See Section 4.5) -.. note:: Under the XML node circuit_model, the features of transistor-level designs can be defined. In the following table, we show the common features supported for all the modules. Then, we will introduce unique features supported only for some spice models types. +.. note:: Under the XML node circuit_model, the features of transistor-level designs can be defined. In the following table, we show the common features supported for all the modules. Then, we will introduce unique features supported only for some circuit models types. Transistor level @@ -73,13 +73,13 @@ Transistor level * pass_gate_logic: defined the parameters in pass-gates, which are used in building multiplexers and LUTs. - * **circuit_model_name:** Specify the name of the circuit model which is used to implement transmission gate, the type of specified spice model should be pass_gate. + * **circuit_model_name:** Specify the name of the circuit model which is used to implement transmission gate, the type of specified circuit model should be pass_gate. * port: define the port list of a circuit model. * **type:** can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined. - * **prefix:** the name of the port. Each port will be shown as [i] in Verilog/SPICE netlists. + * **prefix:** the name of the port. Each port will be shown as ``[i]`` in Verilog/SPICE netlists. * **size:** bandwidth of the port. @@ -91,10 +91,10 @@ Transistor level * **is_global:** can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together. - * **is_set:** can be either ``true`` or ``false``. Specify if this port controls a set signal. Only valid when is_global is true. All the set ports are connected to global set voltage stimuli in testbenches. + * **is_set:** can be either ``true`` or ``false``. Specify if this port controls a set signal. Only valid when ``is_global`` is true. All the set ports are connected to global set voltage stimuli in testbenches. - * **is_reset:** can be either ``true`` or ``false``. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches. + * **is_reset:** can be either ``true`` or ``false``. Specify if this port controls a reset signal. Only valid when ``is_global`` is true. All the reset ports are connected to a global reset voltage stimuli in testbenches. - * **is_config_enable:** can be either ``true`` or ``false``. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to global configuration-enable voltage stimuli in testbenches. + * **is_config_enable:** can be either ``true`` or ``false``. Only valid when ``is_global`` is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details. From 5e156dc72579dfe41451007fa5aa7be4401a6ae2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 15:25:36 -0600 Subject: [PATCH 101/482] minor fix for OSX and update travis using ccache to speed up compilation --- .travis.yml | 2 ++ CMakeLists.txt | 6 ++++++ vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 7506d6422..3700a65bf 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,5 +1,7 @@ language: cpp +# cache results + # Currently sudo is not required, NO ENV is used # Supported Operating systems diff --git a/CMakeLists.txt b/CMakeLists.txt index f3d4730f9..6f9964539 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,5 +1,11 @@ cmake_minimum_required(VERSION 2.8.12) +find_program(CCACHE_FOUND ccache) +if(CCACHE_FOUND) + set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ccache) + set_property(GLOBAL PROPERTY RULE_LAUNCH_LINK ccache) +endif(CCACHE_FOUND) + if (${CMAKE_VERSION} VERSION_GREATER "3.8") #For cmake >= 3.9 INTERPROCEDURAL_OPTIMIZATION behaviour we need to explicitly #set the cmake policy version number diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 70446bbe4..a6879d770 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -610,7 +610,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } From 1a15b9efd4871d1df075b70f80c4d27dc85c160c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 15:27:07 -0600 Subject: [PATCH 102/482] update travis settings --- .travis.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis.yml b/.travis.yml index 3700a65bf..6a1566909 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,6 +1,9 @@ language: cpp # cache results +cache: + directories: + - $HOME/.ccache # Currently sudo is not required, NO ENV is used From b08ff465c9587c289333c15e681cdd702cbe1550 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 17:33:16 -0600 Subject: [PATCH 103/482] refactored pass-gate verilog generation --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 9 ++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + .../verilog/verilog_essential_gates.cpp | 130 +++++++++++++++--- .../verilog/verilog_submodule_utils.cpp | 10 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 33 +++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 9 ++ 6 files changed, 170 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 41a7d61db..32e6ad2b5 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -198,6 +198,15 @@ CircuitModelId CircuitLibrary::pass_gate_logic_model(const CircuitModelId& model return pgl_model_id; } +/* Return the type of pass gate logic module, only applicable to circuit model whose type is pass-gate logic */ +enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is PASSGATE */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + return pass_gate_logic_types_[model_id]; +} + /* Return the multiplex structure of a circuit model */ enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const { /* validate the model_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index d5842f049..b0f2fd210 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -225,6 +225,7 @@ class CircuitLibrary { bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; + enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; /* Multiplexer information */ enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const; size_t mux_num_levels(const CircuitModelId& model_id) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index cbe8d258a..25010abd2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -9,6 +9,7 @@ /* Device-level header files */ #include "spice_types.h" +#include "device_port.h" /* FPGA-X2P context header files */ #include "fpga_x2p_utils.h" @@ -33,7 +34,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, /* Ensure a valid file handler*/ check_file_handler(fp); - fp << "//----- Verilog codes of a power-gated inverter -----" << std::endl; + print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----")); /* Create a sensitive list */ fp << "\treg " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; @@ -109,7 +110,7 @@ void print_verilog_invbuf_body(std::fstream& fp, /* Ensure a valid file handler*/ check_file_handler(fp); - fp << "//----- Verilog codes of a regular inverter -----" << std::endl; + print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " == 1'bz)? $random : "; @@ -139,8 +140,6 @@ void print_verilog_invbuf_module(std::fstream& fp, /* Ensure a valid file handler*/ check_file_handler(fp); - fp << "//----- Verilog module for " << circuit_lib.model_name(circuit_model) << " -----" << std::endl; - /* Find the input port, output port and global inputs*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); @@ -178,14 +177,12 @@ void print_verilog_invbuf_module(std::fstream& fp, } /* dump module body */ - fp << "module " << circuit_lib.model_name(circuit_model) << " (" << std::endl; + print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); - /* TODO: print global ports */ + /* TODO: print global ports, this should be handled by ModuleManager */ for (const auto& port : global_ports) { - BasicPort basic_port; - /* Configure each input port */ - basic_port.set_name(circuit_lib.port_prefix(port)); - basic_port.set_width(circuit_lib.port_size(port)); + /* Configure each global port */ + BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); /* Print port */ fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; } @@ -201,7 +198,7 @@ void print_verilog_invbuf_module(std::fstream& fp, /* Configure each input port */ output_port.set_name(circuit_lib.port_lib_name(output_ports[0])); output_port.set_width(circuit_lib.port_size(output_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << "," << std::endl; + fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << std::endl; fp << ");" << std::endl; /* Finish dumping ports */ @@ -226,15 +223,114 @@ void print_verilog_invbuf_module(std::fstream& fp, /* Print timing info */ print_verilog_submodule_timing(fp, circuit_lib, circuit_model); + /* Print signal initialization */ print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - fp << "endmodule" << std::endl << std::endl; - - fp << "//----- END Verilog module for " << circuit_lib.model_name(circuit_model) << " -----" << std::endl; + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); return; } +/************************************************ + * Print a Verilog module of a pass-gate, + * either transmission-gate or pass-transistor + ***********************************************/ +static +void print_verilog_passgate_module(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + + switch (circuit_lib.pass_gate_logic_type(circuit_model)) { + case SPICE_MODEL_PASS_GATE_TRANSMISSION: + /* Make sure: + * There is only 3 input port (in, sel, selb), + * each size of which is 1 + */ + VTR_ASSERT( 3 == input_ports.size() ); + for (const auto& input_port : input_ports) { + VTR_ASSERT(1 == circuit_lib.port_size(input_port)); + } + break; + case SPICE_MODEL_PASS_GATE_TRANSISTOR: + /* Make sure: + * There is only 2 input port (in, sel), + * each size of which is 1 + */ + VTR_ASSERT( 2 == input_ports.size() ); + for (const auto& input_port : input_ports) { + VTR_ASSERT(1 == circuit_lib.port_size(input_port)); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + exit(1); + } + + /* Make sure: + * There is only 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* Print Verilog module */ + print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + + /* TODO: print global ports, this should be handled by ModuleManager */ + for (const auto& port : global_ports) { + /* Configure each global port */ + BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + } + + for (const auto& input_port : input_ports) { + /* Configure each global port */ + BasicPort basic_port(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + } + + /* Configure each global port */ + for (const auto& output_port : output_ports) { + BasicPort basic_port(circuit_lib.port_lib_name(output_port), circuit_lib.port_size(output_port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, basic_port); + /* Last port does not need a comma */ + if (output_port != output_ports.back()) { + fp << "," << std::endl; + } else { + fp << std::endl; + } + } + fp << ");" << std::endl; + + /* Dump logics: we propagate input to the output when the gate is '1' + * the input is blocked from output when the gate is '0' + */ + fp << "\tassign " << circuit_lib.port_lib_name(output_ports[0]) << " = "; + fp << circuit_lib.port_lib_name(input_ports[1]) << " ? " << circuit_lib.port_lib_name(input_ports[0]); + fp << " : 1'bz;" << std::endl; + + /* Print timing info */ + print_verilog_submodule_timing(fp, circuit_lib, circuit_model); + + /* Print signal initialization */ + print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); +} + /************************************************ * Generate the Verilog netlist for essential gates * include inverters, buffers, transmission-gates, @@ -270,10 +366,10 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { print_verilog_invbuf_module(fp, circuit_lib, circuit_model); } - /* - if (SPICE_MODEL_PASSGATE == spice_models[imodel].type) { - dump_verilog_passgate_module(fp, &(spice_models[imodel])); + if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { + print_verilog_passgate_module(fp, circuit_lib, circuit_model); } + /* if (SPICE_MODEL_GATE == spice_models[imodel].type) { dump_verilog_gate_module(fp, &(spice_models[imodel])); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp index 696c61842..e587c1096 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -50,7 +50,7 @@ void print_verilog_submodule_timing(std::fstream& fp, fp << std::endl; fp << "`ifdef " << verilog_timing_preproc_flag << std::endl; - fp << "//------ BEGIN Pin-to-pin Timing constraints -----" << std::endl; + print_verilog_comment(fp, std::string("------ BEGIN Pin-to-pin Timing constraints -----")); fp << "\tspecify" << std::endl; /* Read out pin-to-pin delays by finding out all the edges belonging to a circuit model */ @@ -69,13 +69,13 @@ void print_verilog_submodule_timing(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")"; fp << " = "; fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE); - fp << " => "; + fp << " , "; fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) << ")"; fp << ";" << std::endl; } fp << "\tendspecify" << std::endl; - fp << "//------ END Pin-to-pin Timing constraints -----" << std::endl; + print_verilog_comment(fp, std::string("------ END Pin-to-pin Timing constraints -----")); fp << "`endif" << std::endl; } @@ -88,7 +88,7 @@ void print_verilog_submodule_signal_init(std::fstream& fp, fp << std::endl; fp << "`ifdef " << verilog_signal_init_preproc_flag << std::endl; - fp << "//------ BEGIN driver initialization -----" << std::endl; + print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; fp << "\t`ifdef " << verilog_formal_verification_preproc_flag << std::endl; @@ -106,7 +106,7 @@ void print_verilog_submodule_signal_init(std::fstream& fp, fp << "\t`endif\n" << std::endl; fp << "\tend" << std::endl; - fp << "//------ END driver initialization -----" << std::endl; + print_verilog_comment(fp, std::string("------ END driver initialization -----")); fp << "`endif" << std::endl; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 8902ce920..2743cdb6f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -60,6 +60,39 @@ void print_verilog_include_defines_preproc_file(std::fstream& fp, return; } +/************************************************ + * Print a Verilog comment line + ***********************************************/ +void print_verilog_comment(std::fstream& fp, + const std::string& comment) { + check_file_handler(fp); + + fp << "// " << comment << std::endl; +} + +/************************************************ + * Print a Verilog module definition + ***********************************************/ +void print_verilog_module_definition(std::fstream& fp, + const std::string& module_name) { + check_file_handler(fp); + + print_verilog_comment(fp, std::string("//----- Verilog module for " + module_name + " -----")); + fp << "module " << module_name << "(" << std::endl; +} + +/************************************************ + * Print a Verilog module definition + ***********************************************/ +void print_verilog_module_end(std::fstream& fp, + const std::string& module_name) { + check_file_handler(fp); + + fp << "endmodule" << std::endl; + print_verilog_comment(fp, std::string("//----- END Verilog module for " + module_name + " -----")); + fp << std::endl; +} + /* Generate a string of a Verilog port */ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type, const BasicPort& port_info) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 33a52fd69..2f3d73bba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -15,6 +15,15 @@ void print_verilog_file_header(std::fstream& fp, void print_verilog_include_defines_preproc_file(std::fstream& fp, const std::string& verilog_dir); +void print_verilog_comment(std::fstream& fp, + const std::string& comment); + +void print_verilog_module_definition(std::fstream& fp, + const std::string& module_name); + +void print_verilog_module_end(std::fstream& fp, + const std::string& module_name); + std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type, const BasicPort& port_info); From d8eb9866a0f29200cbc1607c9005572b7a219ca5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 18:49:48 -0600 Subject: [PATCH 104/482] refactored gate verilog generation --- .../fpga_x2p/base/link_arch_circuit_lib.cpp | 5 +- .../verilog/verilog_essential_gates.cpp | 225 +++++++++++++++++- .../verilog/verilog_submodule_utils.cpp | 11 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 6 +- 4 files changed, 236 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index 8a78d734e..342524903 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -234,8 +234,9 @@ t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, case SPICE_MODEL_PORT_SRAM: break; default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for circuit model port(%s)!\n", - __FILE__, __LINE__, circuit_lib.port_prefix(circuit_port)); + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid type for circuit model port(%s)!\n", + __FILE__, __LINE__, circuit_lib.port_prefix(circuit_port).c_str()); exit(1); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 25010abd2..593da2889 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -331,6 +331,222 @@ void print_verilog_passgate_module(std::fstream& fp, print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); } +/************************************************ + * Print Verilog body codes of an N-input AND gate + ***********************************************/ +static +void print_verilog_and_or_gate_body(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const std::vector& input_ports, + const std::vector& output_ports) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* Find the logic operator for the gate */ + std::string gate_verilog_operator; + switch (circuit_lib.gate_type(circuit_model)) { + case SPICE_MODEL_GATE_AND: + gate_verilog_operator = "&"; + break; + case SPICE_MODEL_GATE_OR: + gate_verilog_operator = "|"; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + + /* Output verilog codes */ + print_verilog_comment(fp, std::string("----- Verilog codes of a " + std::to_string(input_ports.size()) + "-input " + std::to_string(output_ports.size()) + "-output AND gate -----")); + + for (const auto& output_port : output_ports) { + for (const auto& output_pin : circuit_lib.pins(output_port)) { + BasicPort output_port_info(circuit_lib.port_lib_name(output_port), output_pin, output_pin); + fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info); + fp << " = "; + + size_t port_cnt = 0; + for (const auto& input_port : input_ports) { + for (const auto& input_pin : circuit_lib.pins(input_port)) { + /* Do not output AND/OR operator for the first element in the loop */ + if (0 < port_cnt) { + fp << " " << gate_verilog_operator << " "; + } + + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), input_pin, input_pin); + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); + + /* Increment the counter for port */ + port_cnt++; + } + } + fp << ";" << std::endl; + } + } +} + +/************************************************ + * Print Verilog body codes of an 2-input MUX gate + ***********************************************/ +static +void print_verilog_mux2_gate_body(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const std::vector& input_ports, + const std::vector& output_ports) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* TODO: Move the check codes to check_circuit_library.cpp */ + size_t num_err = 0; + /* Check on the port sequence and map */ + /* MUX2 should only have 1 output port with size 1 */ + if (1 != output_ports.size()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) MUX2 circuit model (%s) must have only 1 output!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + num_err++; + } + for (const auto& output_port : output_ports) { + /* Bypass port size of 1 */ + if (1 == circuit_lib.port_size(output_port)) { + continue; + } + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Output port size of a MUX2 circuit model (%s) must be 1!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + num_err++; + } + /* MUX2 should only have 3 output port, each of which has a port size of 1 */ + if (3 != input_ports.size()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) MUX2 circuit model (%s) must have only 3 input!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + num_err++; + } + + for (const auto& input_port : input_ports) { + /* Bypass port size of 1 */ + if (1 == circuit_lib.port_size(input_port)) { + continue; + } + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Input size MUX2 circuit model (%s) must be 1!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + num_err++; + } + if (0 < num_err) { + exit(1); + } + + /* Now, we output the logic of MUX2 + * IMPORTANT Restriction: + * We always assum the first two inputs are data inputs + * the third input is the select port + */ + fp << "\tassign "; + BasicPort out_port_info(circuit_lib.port_lib_name(output_ports[0]), 0, 0); + BasicPort sel_port_info(circuit_lib.port_lib_name(input_ports[2]), 0, 0); + BasicPort in0_port_info(circuit_lib.port_lib_name(input_ports[0]), 0, 0); + BasicPort in1_port_info(circuit_lib.port_lib_name(input_ports[1]), 0, 0); + + fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info); + fp << " = "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, sel_port_info); + fp << " ? "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, in0_port_info); + fp << " : "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, in1_port_info); + fp << ";" << std::endl; +} + +/************************************************ + * Print a Verilog module of a logic gate + * which are standard cells + * Supported gate types: + * 1. N-input AND + * 2. N-input OR + * 3. 2-input MUX + ***********************************************/ +static +void print_verilog_gate_module(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + + /* Make sure: + * There is only 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* Print Verilog module */ + print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + + /* TODO: print global ports, this should be handled by ModuleManager */ + for (const auto& port : global_ports) { + /* Configure each global port */ + BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + } + + for (const auto& input_port : input_ports) { + /* Configure each global port */ + BasicPort basic_port(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + } + + /* Configure each global port */ + for (const auto& output_port : output_ports) { + BasicPort basic_port(circuit_lib.port_lib_name(output_port), circuit_lib.port_size(output_port)); + /* Print port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, basic_port); + /* Last port does not need a comma */ + if (output_port != output_ports.back()) { + fp << "," << std::endl; + } else { + fp << std::endl; + } + } + fp << ");" << std::endl; + + /* Dump logics */ + switch (circuit_lib.gate_type(circuit_model)) { + case SPICE_MODEL_GATE_AND: + case SPICE_MODEL_GATE_OR: + print_verilog_and_or_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports); + break; + case SPICE_MODEL_GATE_MUX2: + print_verilog_mux2_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + + /* Print timing info */ + print_verilog_submodule_timing(fp, circuit_lib, circuit_model); + + /* Print signal initialization */ + print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); +} + /************************************************ * Generate the Verilog netlist for essential gates * include inverters, buffers, transmission-gates, @@ -365,15 +581,16 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, } if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { print_verilog_invbuf_module(fp, circuit_lib, circuit_model); + continue; } if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { print_verilog_passgate_module(fp, circuit_lib, circuit_model); + continue; } - /* - if (SPICE_MODEL_GATE == spice_models[imodel].type) { - dump_verilog_gate_module(fp, &(spice_models[imodel])); + if (SPICE_MODEL_GATE == circuit_lib.model_type(circuit_model)) { + print_verilog_gate_module(fp, circuit_lib, circuit_model); + continue; } - */ } /* Close file handler*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp index e587c1096..39ba45e46 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -95,13 +95,20 @@ void print_verilog_submodule_signal_init(std::fstream& fp, /* Only for formal verification: deposite a zero signal values */ /* Initialize each input port */ for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { - fp << "\t\t$deposit(" << circuit_lib.port_lib_name(input_port) << ", 1'b0);" << std::endl; + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); + fp << "\t\t$deposit("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); + fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); + fp << ");" << std::endl; } fp << "\t`else" << std::endl; /* Regular case: deposite initial signal values: a random value */ for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { - fp << "\t\t$deposit(" << circuit_lib.port_lib_name(input_port) << ", $random);" << std::endl; + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); + fp << "\t\t$deposit("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); + fp << ", $random);" << std::endl; } fp << "\t`endif\n" << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 2743cdb6f..ec8dae1a1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -33,7 +33,7 @@ void print_verilog_file_header(std::fstream& fp, fp << "//\tFPGA Synthesizable Verilog Netlist" << std::endl; fp << "//\tDescription: " << usage << std::endl; fp << "//\tAuthor: Xifan TANG" << std::endl; - fp << "//\t Organization: University of Utah" << std::endl; + fp << "//\tOrganization: University of Utah" << std::endl; fp << "//\tDate: " << std::ctime(&end_time) ; fp << "//-------------------------------------------" << std::endl; fp << "//----- Time scale -----" << std::endl; @@ -107,10 +107,10 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p * others require a format of [:] */ if (VERILOG_PORT_CONKT == verilog_port_type) { - verilog_line = port_info.get_name() + " " + size_str; + verilog_line = port_info.get_name() + size_str; } else { verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; - verilog_line += "" + size_str + " " + port_info.get_name(); + verilog_line += " " + size_str + " " + port_info.get_name(); } return verilog_line; From 5a40c6713d2be95dd9690d4e9e2485a13b9e3d5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 21:50:26 -0600 Subject: [PATCH 105/482] managed to plug in refactored essential gates, dead codes to be removed --- .travis/script.sh | 2 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 9 +++++++-- .../fpga_x2p/verilog/verilog_essential_gates.cpp | 16 ++++++++-------- .../fpga_x2p/verilog/verilog_submodule_utils.cpp | 4 ++-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 ++ 5 files changed, 20 insertions(+), 13 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index dc7e22986..e87ed510b 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -11,7 +11,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then mkdir build cd build cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off - make -j2 + make -j16 else # For linux, we enable full package compilation #make diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index e59ebcaab..10c4b2bbe 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -510,13 +510,18 @@ static void ProcessSpiceModelBuffer(ezxml_t Node, ezxml_set_attr(Node, "topology", NULL); /*Find Tapered*/ + /* Set default values*/ + buffer->tapered_buf = 0; + buffer->tap_buf_level = 2; + buffer->f_per_stage = 4; + /* Parse XML */ Prop = my_strdup(FindProperty(Node, "tapered", read_buf_info)); if (NULL != Prop) { if (0 == strcmp(Prop,"on")) { buffer->tapered_buf = 1; /* Try to dig more properites ...*/ - buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 1); - buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4); + buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 2); + buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4); ezxml_set_attr(Node, "tap_drive_level", NULL); ezxml_set_attr(Node, "f_per_stage", NULL); } else if (0 == strcmp(FindProperty(Node,"tapered",TRUE),"off")) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 593da2889..a5378fcd9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -84,7 +84,8 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, * we wire the input to output */ if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) - || ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + || ( (SPICE_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)) + && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { fp << "~"; } @@ -112,7 +113,7 @@ void print_verilog_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); - fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " == 1'bz)? $random : "; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " === 1'bz)? $random : "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -121,7 +122,8 @@ void print_verilog_invbuf_body(std::fstream& fp, * we wire the input to output */ if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) - || ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + || ( (SPICE_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)) + && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { fp << "~"; } @@ -208,7 +210,7 @@ void print_verilog_invbuf_module(std::fstream& fp, && ( SPICE_MODEL_BUF_BUF != circuit_lib.buffer_type(circuit_model)) ) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } @@ -272,7 +274,7 @@ void print_verilog_passgate_module(std::fstream& fp, default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } @@ -556,7 +558,7 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ - std::string verilog_fname = submodule_dir + essentials_verilog_file_name + ".bak"; + std::string verilog_fname = submodule_dir + essentials_verilog_file_name; std::fstream fp; @@ -597,9 +599,7 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, fp.close(); /* Add fname to the linked list */ - /* TODO: enable this when this function is completed submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp index 39ba45e46..af28fc494 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -68,9 +68,9 @@ void print_verilog_submodule_timing(std::fstream& fp, fp << " => "; fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")"; fp << " = "; - fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE); + fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) / verilog_sim_timescale; fp << " , "; - fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) << ")"; + fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_FALL) / verilog_sim_timescale << ")"; fp << ";" << std::endl; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index bc753174f..27a84e6d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -4053,9 +4053,11 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); + /* To be removed when testing passed dump_verilog_submodule_essentials(verilog_dir, submodule_dir, Arch.spice->num_spice_model, Arch.spice->spice_models); + */ print_verilog_submodule_essentials(std::string(verilog_dir), std::string(submodule_dir), Arch.spice->circuit_lib); From 7b0c55ce151984a389e48b6682b45a6b1f5c3619 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 22:45:48 -0600 Subject: [PATCH 106/482] try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy) --- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 20 ++++++------------- .../verilog/verilog_submodule_utils.cpp | 10 ++++++---- 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 2d12c11d7..9255097c9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -68,11 +68,8 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, /* MUX graph must have only 1 level*/ VTR_ASSERT(1 == mux_graph.num_levels()); - /* Comment lines */ - fp << "//---- Structural Verilog for CMOS MUX basis module:" << module_name << "-----" << std::endl; - - /* Print the port list and definition */ - fp << "module " << module_name << "(" << std::endl; + /* Print Verilog module */ + print_verilog_module_definition(fp, module_name); /* Create port information */ /* Configure each input port */ @@ -103,7 +100,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, fp << ");" << std::endl; /* Verilog Behavior description for a MUX */ - fp << "//---- Structure-level description -----" << std::endl; + print_verilog_comment(fp, std::string("---- Structure-level description -----")); /* Special case: only one memory, switch case is simpler * When mem = 1, propagate input 0; * when mem = 0, propagate input 1; @@ -172,13 +169,8 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, } } - /* Put an end to this module */ - fp << "endmodule" << std::endl; - - /* Comment lines */ - fp << "//---- END Structural Verilog CMOS MUX basis module: " << module_name << "-----" << std::endl << std::endl; - - return; + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); } /*********************************************** @@ -224,7 +216,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp, default: vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp index af28fc494..191e1f7d3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -21,10 +21,12 @@ #include "verilog_submodule_utils.h" /* All values are printed with this precision value. The higher the - * value, the more accurate timing assignment is. Using numeric_limits - * max_digits10 guarentees that no values change during a sequence of - * float -> string -> float conversions */ -constexpr int FLOAT_PRECISION = std::numeric_limits::max_digits10; + * value, the more accurate timing assignment is. Using a number of 6 + * guarentees that a precision of femtosecond which is sufficent for + * electrical simulation (simulation timescale is 10-9 + */ +/* constexpr int FLOAT_PRECISION = std::numeric_limits::max_digits10; */ +constexpr int FLOAT_PRECISION = 6; /************************************************ * Print a timing matrix defined in theecircuit model From 1be5632e92d0781ee14b8899b144fbee108aee56 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 23:11:54 -0600 Subject: [PATCH 107/482] minor tuning on the delay assignment --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp index 191e1f7d3..3ddf25c03 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -71,7 +71,7 @@ void print_verilog_submodule_timing(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")"; fp << " = "; fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) / verilog_sim_timescale; - fp << " , "; + fp << ", "; fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_FALL) / verilog_sim_timescale << ")"; fp << ";" << std::endl; } From 43de2d7636675b7b3bba06f8130cc365de11c06d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 23:47:50 -0600 Subject: [PATCH 108/482] some tuning on Verilog port formatting --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index ec8dae1a1..554579768 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -107,6 +107,10 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p * others require a format of [:] */ if (VERILOG_PORT_CONKT == verilog_port_type) { + /* When LSB == MSB, we can use a simplified format []*/ + if ( 1 == port_info.get_width()) { + size_str = "[" + std::to_string(port_info.get_lsb()) + "]"; + } verilog_line = port_info.get_name() + size_str; } else { verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; From 3f45e6cc87578debe057c7c9f241e1317c9651a9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 22 Aug 2019 10:01:52 -0600 Subject: [PATCH 109/482] remove dead codes for essential gates code generation --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 543 ------------------ 1 file changed, 543 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 27a84e6d1..cb8ca95ef 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -132,544 +132,6 @@ void dump_verilog_submodule_signal_init(FILE* fp, return; } - -/* Dump a module of inverter or buffer or tapered buffer */ -static -void dump_verilog_invbuf_module(FILE* fp, - t_spice_model* invbuf_spice_model) { - int ipin, iport, port_cnt; - int num_input_port = 0; - int num_output_port = 0; - int num_powergate_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - t_spice_model_port** powergate_port = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "//----- Verilog module for %s -----\n", - invbuf_spice_model->name); - - /* Find the input port, output port*/ - input_port = find_spice_model_ports(invbuf_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(invbuf_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - powergate_port = find_spice_model_config_done_ports(invbuf_spice_model, SPICE_MODEL_PORT_INPUT, &num_powergate_port, FALSE); - - /* Make sure: - * There is only 1 input port and 1 output port, - * each size of which is 1 - */ - assert(1 == num_input_port); - assert(1 == input_port[0]->size); - assert(1 == num_output_port); - assert(1 == output_port[0]->size); - - /* If power-gated, we need to find enable signals */ - if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { - if (0 == num_powergate_port) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Inverter, buffer SPICE model is power-gated, but cannot find any power-gate port!\n", - __FILE__, __LINE__); - exit(1); - } - assert ( 0 < num_powergate_port); - } - - /* dump module body */ - fprintf(fp, "module %s (\n", - invbuf_spice_model->name); - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_lib_global_ports(fp, invbuf_spice_model, TRUE, FALSE, FALSE)) { - fprintf(fp, ",\n"); - } - /* Dump ports */ - fprintf(fp, "input [0:0] %s,\n", input_port[0]->lib_name); - fprintf(fp, "output [0:0] %s\n", output_port[0]->lib_name); - fprintf(fp, ");\n"); - /* Finish dumping ports */ - - /* Assign logics : depending on topology */ - switch (invbuf_spice_model->design_tech_info.buffer_info->type) { - case SPICE_MODEL_BUF_INV: - if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { - /* Create a sensitive list */ - fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); - fprintf(fp, "always @("); - /* Power-gate port first*/ - for (iport = 0; iport < num_powergate_port; iport++) { - fprintf(fp, "%s,", powergate_port[iport]->lib_name); - } - fprintf(fp, "%s) begin\n", - input_port[0]->lib_name); - /* Dump the case of power-gated */ - fprintf(fp, " if ("); - port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ - for (iport = 0; iport < num_powergate_port; iport++) { - if (0 == powergate_port[iport]->default_val) { - for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { - if ( 0 < port_cnt ) { - fprintf(fp, "\n\t&&"); - } - /* Power-gated signal are disable during operating, enabled during configuration, - * Therefore, we need to reverse them here - */ - fprintf(fp, "(~%s[%d])", - powergate_port[iport]->lib_name, - ipin); - port_cnt++; /* Update port counter*/ - } - } else { - assert (1 == powergate_port[iport]->default_val); - for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { - if ( 0 < port_cnt ) { - fprintf(fp, "\n\t&&"); - } - /* Power-gated signal are disable during operating, enabled during configuration, - * Therefore, we need to reverse them here - */ - fprintf(fp, "(%s[%d])", - powergate_port[iport]->lib_name, - ipin); - port_cnt++; /* Update port counter*/ - } - } - } - fprintf(fp, ") begin\n"); - fprintf(fp, "\t\tassign %s_reg = ~%s;\n", - output_port[0]->lib_name, - input_port[0]->lib_name); - fprintf(fp, "\tend else begin\n"); - fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", - output_port[0]->lib_name); - fprintf(fp, "\tend\n"); - fprintf(fp, "end\n"); - fprintf(fp, "assign %s = %s_reg;\n", - output_port[0]->lib_name, - output_port[0]->lib_name); - } else { - fprintf(fp, "assign %s = (%s === 1'bz)? $random : ~%s;\n", - output_port[0]->lib_name, - input_port[0]->lib_name, - input_port[0]->lib_name); - } - break; - case SPICE_MODEL_BUF_BUF: - if (TRUE == invbuf_spice_model->design_tech_info.power_gated) { - /* Create a sensitive list */ - fprintf(fp, "reg %s_reg;\n", output_port[0]->lib_name); - fprintf(fp, "always @("); - /* Power-gate port first*/ - for (iport = 0; iport < num_powergate_port; iport++) { - fprintf(fp, "%s,", powergate_port[iport]->lib_name); - } - fprintf(fp, "%s) begin\n", - input_port[0]->lib_name); - /* Dump the case of power-gated */ - fprintf(fp, " if ("); - port_cnt = 0; /* Initialize the counter: decide if we need to put down '&&' */ - for (iport = 0; iport < num_powergate_port; iport++) { - if (0 == powergate_port[iport]->default_val) { - for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { - if ( 0 < port_cnt ) { - fprintf(fp, "\n\t&&"); - } - /* Power-gated signal are disable during operating, enabled during configuration, - * Therefore, we need to reverse them here - */ - fprintf(fp, "(~%s[%d])", - powergate_port[iport]->lib_name, - ipin); - port_cnt++; /* Update port counter*/ - } - } else { - assert (1 == powergate_port[iport]->default_val); - for (ipin = 0; ipin < powergate_port[iport]->size; ipin++) { - if ( 0 < port_cnt ) { - fprintf(fp, "\n\t&&"); - } - /* Power-gated signal are disable during operating, enabled during configuration, - * Therefore, we need to reverse them here - */ - fprintf(fp, "(%s[%d])", - powergate_port[iport]->lib_name, - ipin); - port_cnt++; /* Update port counter*/ - } - } - } - fprintf(fp, ") begin\n"); - fprintf(fp, "\t\tassign %s_reg = %s;\n", - output_port[0]->lib_name, - input_port[0]->lib_name); - fprintf(fp, "\tend else begin\n"); - fprintf(fp, "\t\tassign %s_reg = 1'bz;\n", - output_port[0]->lib_name); - fprintf(fp, "\tend\n"); - fprintf(fp, "end\n"); - fprintf(fp, "assign %s = %s_reg;\n", - output_port[0]->lib_name, - output_port[0]->lib_name); - - } else if (FALSE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf) { - fprintf(fp, "assign %s = (%s === 1'bz)? $random : %s;\n", - output_port[0]->lib_name, - input_port[0]->lib_name, - input_port[0]->lib_name); - } else { - assert (TRUE == invbuf_spice_model->design_tech_info.buffer_info->tapered_buf); - fprintf(fp, "assign %s = (%s === 1'bz)? $random : ", - output_port[0]->lib_name, - input_port[0]->lib_name); - /* depend on the stage, we may invert the output */ - if (1 == invbuf_spice_model->design_tech_info.buffer_info->tap_buf_level % 2) { - fprintf(fp, "~"); - } - fprintf(fp, "%s;\n", - input_port[0]->lib_name); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", - __FILE__, __LINE__, invbuf_spice_model->name); - exit(1); - } - - /* Print timing info */ - dump_verilog_submodule_timing(fp, invbuf_spice_model); - - dump_verilog_submodule_signal_init(fp, invbuf_spice_model); - - fprintf(fp, "endmodule\n"); - - fprintf(fp, "\n"); - - /* Free */ - my_free(input_port); - my_free(output_port); - - return; -} - -/* Dump a module of pass-gate logic */ -static -void dump_verilog_passgate_module(FILE* fp, - t_spice_model* passgate_spice_model) { - int iport; - int num_input_port = 0; - int num_output_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Find the input port, output port*/ - input_port = find_spice_model_ports(passgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(passgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - - /* Make sure: - * There is only 1 output port, - * each size of which is 1 - */ - assert(1 == num_output_port); - assert(1 == output_port[0]->size); - - fprintf(fp, "//----- Verilog module for %s -----\n", - passgate_spice_model->name); - - /* dump module body */ - fprintf(fp, "module %s (\n", - passgate_spice_model->name); - - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_lib_global_ports(fp, passgate_spice_model, TRUE, FALSE, FALSE)) { - fprintf(fp, ",\n"); - } - - /* Assign ports : depending on topology */ - switch (passgate_spice_model->design_tech_info.pass_gate_info->type) { - case SPICE_MODEL_PASS_GATE_TRANSMISSION: - /* Make sure: - * There is only 3 input port (in, sel, selb), - * each size of which is 1 - */ - assert(3 == num_input_port); - for (iport = 0; iport < num_input_port; iport++) { - assert(1 == input_port[iport]->size); - } - /* Dump ports */ - fprintf(fp, "input [0:0] %s,\n", input_port[0]->lib_name); - fprintf(fp, "input [0:0] %s,\n", input_port[1]->lib_name); - fprintf(fp, "input [0:0] %s,\n", input_port[2]->lib_name); - fprintf(fp, "output [0:0] %s\n", output_port[0]->lib_name); - fprintf(fp, ");\n"); - /* Finish dumping ports */ - - break; - case SPICE_MODEL_PASS_GATE_TRANSISTOR: - /* Make sure: - * There is only 2 input port (in, sel), - * each size of which is 1 - */ - assert(2 == num_input_port); - for (iport = 0; iport < num_input_port; iport++) { - assert(1 == input_port[iport]->size); - } - /* Dump ports */ - fprintf(fp, "input [0:0] %s,\n", input_port[0]->lib_name); - fprintf(fp, "input [0:0] %s,\n", input_port[1]->lib_name); - fprintf(fp, "output [0:0] %s\n", output_port[0]->lib_name); - fprintf(fp, ");\n"); - /* Finish dumping ports */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", - __FILE__, __LINE__, passgate_spice_model->name); - exit(1); - } - - /* Dump logics */ - fprintf(fp, "assign %s = %s? %s : 1'bz;\n", - output_port[0]->lib_name, - input_port[1]->lib_name, - input_port[0]->lib_name); - - /* Print timing info */ - dump_verilog_submodule_timing(fp, passgate_spice_model); - - /* Print signal initialization */ - dump_verilog_submodule_signal_init(fp, passgate_spice_model); - - fprintf(fp, "endmodule\n"); - - fprintf(fp, "\n"); - - /* Free */ - my_free(input_port); - my_free(output_port); - - return; -} - -/* Dump a module of pass-gate logic */ -static -void dump_verilog_gate_module(FILE* fp, - t_spice_model* gate_spice_model) { - int iport, ipin, jport, jpin; - int num_input_port = 0; - int num_output_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Find the input port, output port*/ - input_port = find_spice_model_ports(gate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(gate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - - /* Make sure: - * There is only 1 output port, - * each size of which is 1 - */ - assert(1 == num_output_port); - assert(1 == output_port[0]->size); - - assert(0 < num_input_port); - - fprintf(fp, "//----- Verilog module for %s -----\n", - gate_spice_model->name); - - /* dump module body */ - fprintf(fp, "module %s (\n", - gate_spice_model->name); - - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_lib_global_ports(fp, gate_spice_model, TRUE, FALSE, FALSE)) { - fprintf(fp, ",\n"); - } - - /* Dump ports */ - for (iport = 0; iport < num_input_port; iport++) { - fprintf(fp, "input [0:%d] %s,\n", - input_port[iport]->size - 1, input_port[iport]->lib_name); - } - for (iport = 0; iport < num_output_port; iport++) { - fprintf(fp, "output [0:%d] %s\n", - output_port[iport]->size - 1, output_port[iport]->lib_name); - } - fprintf(fp, ");\n"); - - /* Dump logics */ - switch (gate_spice_model->design_tech_info.gate_info->type) { - case SPICE_MODEL_GATE_AND: - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_port[iport]->size; ipin++) { - fprintf(fp, "assign %s[%d] = ", - output_port[iport]->lib_name, ipin); - for (jport = 0; jport < num_input_port; jport++) { - for (jpin = 0; jpin < input_port[jport]->size; jpin++) { - fprintf(fp, "%s[%d]", - input_port[jport]->lib_name, jpin); - if ((jport == num_input_port - 1) && (jpin == input_port[jport]->size - 1)) { - continue; /* Stop output AND sign for the last element in the loop */ - } - fprintf(fp, " & "); - } - } - fprintf(fp, ";\n"); - } - } - break; - case SPICE_MODEL_GATE_OR: - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_port[iport]->size; ipin++) { - fprintf(fp, "assign %s[%d] = ", - output_port[iport]->lib_name, ipin); - for (jport = 0; jport < num_input_port; jport++) { - for (jpin = 0; jpin < input_port[jport]->size; jpin++) { - fprintf(fp, "%s[%d]", - input_port[jport]->lib_name, jpin); - if ((jport == num_input_port - 1) && (jpin == input_port[jport]->size - 1)) { - continue; /* Stop output AND sign for the last element in the loop */ - } - fprintf(fp, " | "); - } - } - fprintf(fp, ";\n"); - } - } - break; - case SPICE_MODEL_GATE_MUX2: - /* Check on the port sequence and map */ - /* MUX2 should only have 1 output port with size 1 */ - if (1 != num_output_port) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) MUX2 circuit model must have only 1 output!\n", - __FILE__, __LINE__); - exit(1); - } else if (1 != output_port[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Output size of a MUX2 circuit model must be 1!\n", - __FILE__, __LINE__); - exit(1); - } - /* MUX2 should only have 3 output port, each of which has a port size of 1 */ - if (3 != num_input_port) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) MUX2 circuit model must have only 3 input!\n", - __FILE__, __LINE__); - exit(1); - } else { - for (iport = 0; iport < num_input_port; iport++) { - /* Bypass port size of 1 */ - if (1 == input_port[iport]->size) { - continue; - } - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Input size MUX2 circuit model must be 1!\n", - __FILE__, __LINE__); - exit(1); - } - } - /* Now, we output the logic of MUX2 - * IMPORTANT Restriction: - * We always assum the first two inputs are data inputs - * the third input is the select port - */ - fprintf(fp, "assign %s[%d] = %s[%d] ? %s[%d] : %s[%d];\n", - output_port[0]->lib_name, 0, - input_port[2]->lib_name, 0, - input_port[0]->lib_name, 0, - input_port[1]->lib_name, 0); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid topology for spice model (%s)!\n", - __FILE__, __LINE__, gate_spice_model->name); - exit(1); - } - - - /* Print timing info */ - dump_verilog_submodule_timing(fp, gate_spice_model); - - /* Print signal initialization */ - dump_verilog_submodule_signal_init(fp, gate_spice_model); - - fprintf(fp, "endmodule\n"); - - fprintf(fp, "\n"); - - /* Free */ - my_free(input_port); - my_free(output_port); - - return; -} - -/* Dump Essential modules: - * 1. inverters - * 2. buffers - * 3. pass-gate logics */ -static -void dump_verilog_submodule_essentials(char* verilog_dir, char* submodule_dir, - int num_spice_model, - t_spice_model* spice_models) { - int imodel; - char* verilog_name = my_strcat(submodule_dir, essentials_verilog_file_name); - FILE* fp = NULL; - - /* Create file */ - fp = fopen(verilog_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s", - __FILE__, __LINE__, essentials_verilog_file_name); - exit(1); - } - dump_verilog_file_header(fp,"Essential gates"); - - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Output essential models*/ - for (imodel = 0; imodel < num_spice_model; imodel++) { - /* By pass user-defined modules */ - if (NULL != spice_models[imodel].verilog_netlist) { - continue; - } - if (SPICE_MODEL_INVBUF == spice_models[imodel].type) { - dump_verilog_invbuf_module(fp, &(spice_models[imodel])); - } - if (SPICE_MODEL_PASSGATE == spice_models[imodel].type) { - dump_verilog_passgate_module(fp, &(spice_models[imodel])); - } - if (SPICE_MODEL_GATE == spice_models[imodel].type) { - dump_verilog_gate_module(fp, &(spice_models[imodel])); - } - } - - /* Close file handler*/ - fclose(fp); - - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); - - /* Free */ - - return; -} - /* Dump a CMOS MUX basis module */ static void dump_verilog_cmos_mux_one_basis_module(FILE* fp, @@ -4053,11 +3515,6 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); - /* To be removed when testing passed - dump_verilog_submodule_essentials(verilog_dir, submodule_dir, - Arch.spice->num_spice_model, - Arch.spice->spice_models); - */ print_verilog_submodule_essentials(std::string(verilog_dir), std::string(submodule_dir), Arch.spice->circuit_lib); From d5ce1b557e7d6feacc593c99b9ebdf069e3cf995 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 16:56:58 -0600 Subject: [PATCH 110/482] Made thread logs prettier --- openfpga_flow/scripts/run_fpga_task.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index f5fd08b0e..b445c9d7e 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -88,6 +88,7 @@ def validate_command_line_arguments(): if args.debug: logger.info("Setting loggger in debug mode") logger.setLevel(logging.DEBUG) + logger.info("Set up to run %d Parallel threads", args.maxthreads) def generate_each_task_actions(taskname): @@ -239,6 +240,16 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): return command +def strip_child_logger_info(line): + try: + logtype, message = line.split(" - ", 1) + lognumb = {"CRITICAL": 50, "ERROR": 40, "WARNING": 30, + "INFO": 20, "DEBUG": 10, "NOTSET": 0} + logger.log(lognumb["INFO"], message) + except: + logger.info(line) + + def run_single_script(s, eachJob): logger.debug('Added job in pool') with s: @@ -257,7 +268,7 @@ def run_single_script(s, eachJob): universal_newlines=True) for line in process.stdout: if not args.skip_tread_logs: - logging.info(line[:-1]) + strip_child_logger_info(line[:-1]) sys.stdout.buffer.flush() output.write(line) process.wait() From 30cbe38d3db68700d9af3260376a1a142dd8013b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 17:00:59 -0600 Subject: [PATCH 111/482] Added Test Modes - Added blif VPR Option --- .../benchmarks/Test_Modes/test_modes.act | 67 +++++++++++++ .../benchmarks/Test_Modes/test_modes.blif | 94 +++++++++++++++++++ .../benchmarks/Test_Modes/test_modes.v | 78 +++++++++++++++ .../misc/fpgaflow_default_tool_path.conf | 2 +- openfpga_flow/scripts/run_fpga_flow.py | 37 ++++++-- 5 files changed, 270 insertions(+), 8 deletions(-) create mode 100644 openfpga_flow/benchmarks/Test_Modes/test_modes.act create mode 100644 openfpga_flow/benchmarks/Test_Modes/test_modes.blif create mode 100644 openfpga_flow/benchmarks/Test_Modes/test_modes.v diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.act b/openfpga_flow/benchmarks/Test_Modes/test_modes.act new file mode 100644 index 000000000..a58956a8e --- /dev/null +++ b/openfpga_flow/benchmarks/Test_Modes/test_modes.act @@ -0,0 +1,67 @@ +cint01 0.485400 0.188600 +n01 0.489000 0.213200 +cint02 0.502400 0.203200 +n02 0.509200 0.195200 +cint03 0.507200 0.192200 +n03 0.502400 0.201600 +cint04 0.463200 0.199400 +n04 0.522000 0.191000 +n05 0.486800 0.204800 +reg0 0.463000 0.195400 +reg1 0.487400 0.196600 +reg2 0.506200 0.195000 +reg3 0.492200 0.208200 +reg4 0.507200 0.204800 +reg5 0.500400 0.200600 +reg6 0.500800 0.203400 +reg7 0.509600 0.198800 +reg8 0.492200 0.188000 +reg9 0.504800 0.204400 +reg10 0.507600 0.203200 +reg11 0.494200 0.203600 +clk 0.534600 0.203800 +a_0 0.478200 0.203800 +a_1 0.514800 0.208600 +a_2 0.505800 0.204600 +a_3 0.500000 0.195200 +b_0 0.530800 0.192800 +b_1 0.495800 0.195400 +b_2 0.496600 0.201200 +b_3 0.492000 0.200200 +cin 0.502600 0.202200 +e 0.495200 0.201000 +f 0.504000 0.203400 +g 0.498200 0.202000 +reg_a_0 0.478200 0.203800 +reg_a_1 0.514800 0.208600 +reg_a_2 0.505800 0.204600 +reg_a_3 0.500000 0.195200 +reg_b_0 0.530800 0.192800 +reg_b_1 0.495800 0.195400 +reg_b_2 0.496600 0.201200 +reg_b_3 0.492000 0.200200 +reg_cin 0.502600 0.202200 +sum_0 0.489000 0.213200 +sum_1 0.509200 0.195200 +sum_2 0.502400 0.201600 +sum_3 0.522000 0.191000 +cout 0.486800 0.204800 +ref0 0.000000 0.000000 +n57 0.478200 0.097457 +n62 0.514800 0.107387 +n67 0.505800 0.103487 +n72 0.500000 0.097600 +n77 0.530800 0.102338 +n82 0.495800 0.096879 +n87 0.496600 0.099916 +n92 0.492000 0.098498 +n97 0.502600 0.101626 +d0 0.617800 0.046719 +x 0.492200 0.102476 +y 0.509600 0.101308 +z 0.494200 0.100619 +n102 0.489000 0.104255 +n106 0.509200 0.099396 +n110 0.502400 0.101284 +n114 0.522000 0.099702 +n118 0.486800 0.099697 diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.blif b/openfpga_flow/benchmarks/Test_Modes/test_modes.blif new file mode 100644 index 000000000..f7ed4cb33 --- /dev/null +++ b/openfpga_flow/benchmarks/Test_Modes/test_modes.blif @@ -0,0 +1,94 @@ +# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019 +.model test_modes +.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g +.outputs sum_0 sum_1 sum_2 sum_3 cout x y z + +.latch n57 reg_a_0 re clk 0 +.latch n62 reg_a_1 re clk 0 +.latch n67 reg_a_2 re clk 0 +.latch n72 reg_a_3 re clk 0 +.latch n77 reg_b_0 re clk 0 +.latch n82 reg_b_1 re clk 0 +.latch n87 reg_b_2 re clk 0 +.latch n92 reg_b_3 re clk 0 +.latch n97 reg_cin re clk 0 +.latch n102 sum_0 re clk 0 +.latch n106 sum_1 re clk 0 +.latch n110 sum_2 re clk 0 +.latch n114 sum_3 re clk 0 +.latch n118 cout re clk 0 + + +.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01 +.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02 +.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03 +.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04 +.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05 + +.subckt shift D=d0 clk=clk Q=reg0 +.subckt shift D=reg0 clk=clk Q=reg1 +.subckt shift D=reg1 clk=clk Q=reg2 +.subckt shift D=reg2 clk=clk Q=reg3 +.subckt shift D=reg3 clk=clk Q=reg4 +.subckt shift D=reg4 clk=clk Q=reg5 +.subckt shift D=reg5 clk=clk Q=reg6 +.subckt shift D=reg6 clk=clk Q=reg7 +.subckt shift D=reg7 clk=clk Q=reg8 +.subckt shift D=reg8 clk=clk Q=reg9 +.subckt shift D=reg9 clk=clk Q=reg10 +.subckt shift D=reg10 clk=clk Q=reg11 + +.names ref0 + 0 +.names a_0 n57 +1 1 +.names a_1 n62 +1 1 +.names a_2 n67 +1 1 +.names a_3 n72 +1 1 +.names b_0 n77 +1 1 +.names b_1 n82 +1 1 +.names b_2 n87 +1 1 +.names b_3 n92 +1 1 +.names cin n97 +1 1 +.names e f g d0 +1-1 1 +-0- 1 +.names reg3 x +1 1 +.names reg7 y +1 1 +.names reg11 z +1 1 +.names n01 n102 +1 1 +.names n02 n106 +1 1 +.names n03 n110 +1 1 +.names n04 n114 +1 1 +.names n05 n118 +1 1 +.end + + +.model adder +.inputs a b cin +.outputs cout sumout +.blackbox +.end + + +.model shift +.inputs D clk +.outputs Q +.blackbox +.end diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.v b/openfpga_flow/benchmarks/Test_Modes/test_modes.v new file mode 100644 index 000000000..8090d2903 --- /dev/null +++ b/openfpga_flow/benchmarks/Test_Modes/test_modes.v @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////// +// // +// Benchmark using all modes of k8 architecture // +// // +//////////////////////////////////////////////////////// + +`timescale 1 ns/ 1 ps + +module test_modes( + clk, + a_0, + a_1, + a_2, + a_3, + b_0, + b_1, + b_2, + b_3, + cin, + e, + f, + g, + sum_0, + sum_1, + sum_2, + sum_3, + cout, + x, + y, + z ); + + input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g; + output reg sum_0, sum_1, sum_2, sum_3, cout; + output wire x, y, z; + + wire d0; + wire [4:0] n0; + wire [3:0] a, b; + reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin; + + assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0}; + assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0}; + assign d0 = (e && g) || !f; + assign n0 = a + b + reg_cin; + assign x = reg3; + assign y = reg7; + assign z = reg11; + + always @(posedge clk) begin + reg0 <= d0; + reg1 <= reg0; + reg2 <= reg1; + reg3 <= reg2; + reg4 <= reg3; + reg5 <= reg4; + reg6 <= reg5; + reg7 <= reg6; + reg8 <= reg7; + reg9 <= reg8; + reg10 <= reg9; + reg11 <= reg10; + reg_a_0 <= a_0; + reg_a_1 <= a_1; + reg_a_2 <= a_2; + reg_a_3 <= a_3; + reg_b_0 <= b_0; + reg_b_1 <= b_1; + reg_b_2 <= b_2; + reg_b_3 <= b_3; + reg_cin <= cin; + sum_0 <= n0[0]; + sum_1 <= n0[1]; + sum_2 <= n0[2]; + sum_3 <= n0[3]; + cout <= n0[4]; + end + +endmodule diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index d33fc4e80..d41183ac8 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -13,7 +13,7 @@ iverilog_path = iverilog include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists [FLOW_SCRIPT_CONFIG] -valid_flows = standard,vtr,vtr_standard,yosys_vpr +valid_flows = standard,vpr_blif,vtr,vtr_standard,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index b3d5adef7..1844abb95 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -60,6 +60,13 @@ parser.add_argument('--yosys_tmpl', type=str, parser.add_argument('--debug', action="store_true", help="Run script in debug mode") +# Blif_VPR Only flow arguments +parser.add_argument('--activity_file', type=str, + help="Activity file used while running yosys flow") +parser.add_argument('--base_verilog', type=str, + help="Original Verilog file to run verification in " + + "blif_VPR flow") + # ACE2 and power estimation related arguments parser.add_argument('--K', type=int, help="LUT Size, if not specified extracted from arch file") @@ -99,6 +106,8 @@ X2PParse.add_argument('--vpr_fpga_x2p_signal_density_weight', type=float, help="Specify the signal_density_weight of VPR FPGA SPICE") X2PParse.add_argument('--vpr_fpga_x2p_sim_window_size', type=float, help="specify the sim_window_size of VPR FPGA SPICE") +X2PParse.add_argument('--vpr_fpga_x2p_compact_routing_hierarchy', + action="store_true", help="Compact_routing_hierarchy") # VPR - FPGA-SPICE Extension SPParse = parser.add_argument_group('FPGA-SPICE Extension') @@ -162,6 +171,8 @@ VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb', VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str, help="Print modelsim " + "simulation script", metavar="") +VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true", + help="Explicit Mapping") # VPR - FPGA-Bitstream Extension BSparse = parser.add_argument_group('FPGA-Bitstream Extension') @@ -199,15 +210,17 @@ def main(): if (args.fpga_flow == "yosys_vpr"): logger.info('Running "yosys_vpr" Flow') run_yosys_with_abc() - if (args.fpga_flow == "vtr"): - run_odin2() - run_abc_vtr() - if (args.fpga_flow == "vtr_standard"): - run_abc_for_standarad() + run_rewrite_verilog() if args.power: run_ace2() run_pro_blif_3arg() - run_rewrite_verilog() + if (args.fpga_flow == "vpr_blif"): + collect_files_for_vpr() + # if (args.fpga_flow == "vtr"): + # run_odin2() + # run_abc_vtr() + # if (args.fpga_flow == "vtr_standard"): + # run_abc_for_standarad() run_vpr() if args.end_flow_with_test: run_netlists_verification() @@ -295,6 +308,10 @@ def validate_command_line_arguments(): # Expand run directory to absolute path args.run_dir = os.path.abspath(args.run_dir) + if args.activity_file: + args.activity_file = os.path.abspath(args.activity_file) + if args.base_verilog: + args.base_verilog = os.path.abspath(args.base_verilog) def ask_user_quetion(condition, question): @@ -499,6 +516,7 @@ def run_pro_blif_3arg(): def run_vpr(): + if not args.fix_route_chan_width: # Run Standard VPR Flow min_channel_width = run_standard_vpr( args.top_module+".blif", @@ -573,7 +591,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command += ["--timing_driven_clustering", "off"] # channel width option if fixed_chan_width >= 0: - command += ["--route_chan_width", "%d"%fixed_chan_width] + command += ["--route_chan_width", "%d" % fixed_chan_width] if args.vpr_use_tileable_route_chan_width: command += ["--use_tileable_route_chan_width"] @@ -586,6 +604,9 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): if args.vpr_fpga_x2p_sim_window_size: command += ["--fpga_x2p_sim_window_size", args.vpr_fpga_x2p_sim_window_size] + if args.vpr_fpga_x2p_compact_routing_hierarchy: + command += ["--fpga_x2p_compact_routing_hierarchy"] + if args.vpr_fpga_spice_sim_mt_num: command += ["--fpga_spice_sim_mt_num", args.vpr_fpga_spice_sim_mt_num] @@ -627,6 +648,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): args.top_module+"_output_verilog.v"] if args.vpr_fpga_verilog_include_timing: command += ["--fpga_verilog_include_timing"] + if args.vpr_fpga_verilog_explicit_mapping: + command += ["--fpga_verilog_explicit_mapping"] if args.vpr_fpga_verilog_include_signal_init: command += ["--fpga_verilog_include_signal_init"] if args.vpr_fpga_verilog_formal_verification_top_netlist: From 77e2a7bca379ffc5f592876b98e488af4c40137c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 17:01:38 -0600 Subject: [PATCH 112/482] Added execution time logs in flow script --- openfpga_flow/scripts/run_fpga_flow.py | 93 +++++++++++++++++--------- 1 file changed, 61 insertions(+), 32 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 1844abb95..f9971b6aa 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -2,6 +2,7 @@ import os import sys import shutil import time +from datetime import timedelta import shlex import glob import argparse @@ -13,6 +14,9 @@ import threading from string import Template import re import xml.etree.ElementTree as ET +from importlib import util +if util.find_spec("humanize"): + import humanize # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Initialise general paths for the script @@ -188,13 +192,14 @@ RegParse.add_argument("--end_flow_with_test", action="store_true", # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Global varaibles declaration # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Varible to store logger instance -logger = None -# arguments are parsed at the end of the script depending upon whether script -# is called externally or as a standalone -args = None +# Setting up print and logging system +logging.basicConfig(level=logging.INFO, stream=sys.stdout, + format='%(levelname)s - %(message)s') +logger = logging.getLogger('OpenFPGA_Flow_Logs') + # variable to store script_configuration and cad tool paths config, cad_tools = None, None +ExecTime = {} # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Main program starts here @@ -211,9 +216,9 @@ def main(): logger.info('Running "yosys_vpr" Flow') run_yosys_with_abc() run_rewrite_verilog() - if args.power: - run_ace2() - run_pro_blif_3arg() + if args.power: + run_ace2() + run_pro_blif_3arg() if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() # if (args.fpga_flow == "vtr"): @@ -224,6 +229,20 @@ def main(): run_vpr() if args.end_flow_with_test: run_netlists_verification() + + ExecTime["End"] = time.time() + def timestr(x): return humanize.naturaldelta(timedelta(seconds=x)) \ + if "humanize" in sys.modules else str(int(x)) + " Sec " + TimeInfo = ("Openfpga_flow completed, " + + "Total Time Taken %s " % + timestr(ExecTime["End"]-ExecTime["Start"]) + + "VPR Time %s " % + timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"])) + TimeInfo += ("Verification Time %s " % + timestr(ExecTime["VerificationEnd"] - + ExecTime["VerificationStart"]) + if args.end_flow_with_test else "") + logger.info(TimeInfo) exit() # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = @@ -270,7 +289,7 @@ def validate_command_line_arguments(): # Check if flow supported if not args.fpga_flow in config.get("FLOW_SCRIPT_CONFIG", "valid_flows"): - clean_up_and_exit("%s Flow not supported"%args.fpga_flow) + clean_up_and_exit("%s Flow not supported" % args.fpga_flow) # Check if argument list is consistant for eacharg, dependent in config.items("CMD_ARGUMENT_DEPENDANCY"): @@ -278,8 +297,8 @@ def validate_command_line_arguments(): dependent = dependent.split(",") for eachdep in dependent: if not any([getattr(args, i, 0) for i in eachdep.split("|")]): - clean_up_and_exit("'%s' argument depends on (%s) argumets"% - (eacharg, ", ".join(dependent).replace("|", " or "))) + clean_up_and_exit("'%s' argument depends on (%s) argumets" % + (eacharg, ", ".join(dependent).replace("|", " or "))) # Filter provided architecrue files args.arch_file = os.path.abspath(args.arch_file) @@ -292,7 +311,7 @@ def validate_command_line_arguments(): if os.path.isdir(args.benchmark_files[index]): logger.warning("Skipping directory in bench %s" % everyinput) logger.warning("Directory is not support in benchmark list" + - "use wildcard pattern to add files") + "use wildcard pattern to add files") continue for everyfile in glob.glob(args.benchmark_files[index]): if not os.path.isfile(everyfile): @@ -515,15 +534,25 @@ def run_pro_blif_3arg(): logger.info("blif_3args output is written in file %s" % filename) +def collect_files_for_vpr(): + if len(args.benchmark_files) > 1: + logger.error("Expecting Single Benchmark BLif file.") + shutil.copy(args.benchmark_files[0], args.top_module+".blif") + shutil.copy(args.activity_file, args.top_module+"_ace_out.act") + shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v") + + def run_vpr(): + ExecTime["VPRStart"] = time.time() + if not args.fix_route_chan_width: - # Run Standard VPR Flow - min_channel_width = run_standard_vpr( - args.top_module+".blif", - -1, - args.top_module+"_min_chan_width_vpr.txt") - logger.info("Standard VPR flow routed with minimum %d Channels" % - min_channel_width) + # Run Standard VPR Flow + min_channel_width = run_standard_vpr( + args.top_module+".blif", + -1, + args.top_module+"_min_chan_width_vpr.txt") + logger.info("Standard VPR flow routed with minimum %d Channels" % + min_channel_width) # Minimum routing channel width if (args.min_route_chan_width): @@ -536,8 +565,8 @@ def run_vpr(): while(1): res = run_standard_vpr(args.top_module+".blif", int(min_channel_width), - args.top_module+"_reroute_vpr.txt", - route_only=True) + args.top_module+"_reroute_vpr.txt", + route_only=True) if res: logger.info("Routing with channel width=%d successful" % @@ -568,6 +597,7 @@ def run_vpr(): extract_vpr_stats(logfile=args.top_module+".power", r_filename="vpr_power_stat", parse_section="power") + ExecTime["VPREnd"] = time.time() def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): @@ -690,6 +720,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): chan_width = None try: + logger.debug("Running VPR : " + " ".join(command)) with open(logfile, 'w+') as output: output.write(" ".join(command)+"\n") process = subprocess.run(command, @@ -737,8 +768,8 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): extract_val = str(match.group(1)) elif filt_function.strip() == "scientific": try: - mult = {"m":1E-3, "u":1E-6, "n":1E-9, - "K":1E-3, "M":1E-6, "G":1E-9,}.get(match.group(2)[0], 1) + mult = {"m": 1E-3, "u": 1E-6, "n": 1E-9, + "K": 1E-3, "M": 1E-6, "G": 1E-9, }.get(match.group(2)[0], 1) except: mult = 1 extract_val = float(match.group(1))*mult @@ -746,7 +777,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): extract_val = match.group(1) except: logger.exception("Filter failed") - extract_val= "Filter Failed" + extract_val = "Filter Failed" resultDict[name] = extract_val dummyparser = ConfigParser() @@ -755,7 +786,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): with open(r_filename+'.result', 'w') as configfile: dummyparser.write(configfile) logger.info("%s result extracted in file %s" % - (parse_section,r_filename+'.result')) + (parse_section, r_filename+'.result')) def run_rewrite_verilog(): @@ -776,13 +807,15 @@ def run_rewrite_verilog(): if process.returncode: logger.info("Rewrite veri yosys run failed with returncode %d", process.returncode) - except: + except Exception as e: logger.exception("Failed to run VPR") + print(e.output) clean_up_and_exit("") logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt") def run_netlists_verification(): + ExecTime["VerificationStart"] = time.time() compiled_file = "compiled_"+args.top_module # include_netlists = args.top_module+"_include_netlists.v" tb_top_formal = args.top_module+"_top_formal_verification_random_tb" @@ -806,6 +839,7 @@ def run_netlists_verification(): logger.info("VVP Simulation Successful") else: logger.info(str(output).split("\n")[-1]) + ExecTime["VerificationEnd"] = time.time() def run_command(taskname, logfile, command, exit_if_fail=True): @@ -840,11 +874,6 @@ def process_failed_vpr_run(vpr_output): if __name__ == "__main__": - # Setting up print and logging system - logging.basicConfig(level=logging.DEBUG, stream=sys.stdout, - format='%(levelname)s - %(message)s') - logger = logging.getLogger('OpenFPGA_Flow_Logs') - - # Parse commandline argument + ExecTime["Start"] = time.time() args = parser.parse_args() main() From 8f80cb3c24d5bb5197cc948fa377a2ccb1ae69d6 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 17:02:12 -0600 Subject: [PATCH 113/482] Added Sample script to run blif VPR --- run_test.sh | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/run_test.sh b/run_test.sh index 2acefd58d..9d85ab91b 100644 --- a/run_test.sh +++ b/run_test.sh @@ -1,16 +1,46 @@ +# python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ +# ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ +# --top_module s298 \ +# --power \ +# --power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \ +# --min_route_chan_width 1.3 \ +# --vpr_fpga_verilog \ +# --vpr_fpga_verilog_dir . \ +# --vpr_fpga_x2p_rename_illegal_port \ +# --end_flow_with_test \ +# --vpr_fpga_verilog_include_icarus_simulator \ +# --vpr_fpga_verilog_formal_verification_top_netlist \ +# --vpr_fpga_verilog_include_timing \ +# --vpr_fpga_verilog_include_signal_init \ +# --vpr_fpga_verilog_print_autocheck_top_testbench + + + python3.5 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ -./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ ---top_module s298 \ +./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +--fpga_flow vpr_blif \ +--top_module test_modes \ +--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v\ --power \ ---power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \ ---min_route_chan_width 1.3 \ +--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +--fix_route_chan_width 300 \ --vpr_fpga_verilog \ --vpr_fpga_verilog_dir . \ --vpr_fpga_x2p_rename_illegal_port \ ---end_flow_with_test \ --vpr_fpga_verilog_include_icarus_simulator \ --vpr_fpga_verilog_formal_verification_top_netlist \ --vpr_fpga_verilog_include_timing \ --vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ No newline at end of file +--vpr_fpga_verilog_print_autocheck_top_testbench \ +--debug \ +--vpr_fpga_bitstream_generator \ +--vpr_fpga_verilog_print_user_defined_template \ +--vpr_fpga_verilog_print_report_timing_tcl \ +--vpr_fpga_verilog_print_sdc_pnr \ +--vpr_fpga_verilog_print_sdc_analysis \ +--vpr_fpga_x2p_compact_routing_hierarchy \ +--end_flow_with_test + From 5027f9c4b38598f8a7ce0ec06df2d9bc109b8d02 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 17:03:56 -0600 Subject: [PATCH 114/482] Added test mode script in travis --- .travis/script.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index e0c463239..f7aeef4cb 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -26,4 +26,6 @@ end_section "OpenFPGA.build" $SPACER cd - -python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick +# python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick +chmod 755 run_test.sh +./run_test.sh \ No newline at end of file From 4189ada1eb4c006c43d4dced30c97d63dd9dca9d Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 17:31:46 -0600 Subject: [PATCH 115/482] Fixed run test file --- run_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/run_test.sh b/run_test.sh index 9d85ab91b..d218e9c52 100644 --- a/run_test.sh +++ b/run_test.sh @@ -23,7 +23,7 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --fpga_flow vpr_blif \ --top_module test_modes \ --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v\ +--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ --power \ --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ --fix_route_chan_width 300 \ From 6e7de16ad46acc79bf868c38e2a70279fa83c4bc Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 22 Aug 2019 23:41:25 -0600 Subject: [PATCH 116/482] Solved bug in commnad rearrangement --- openfpga_flow/scripts/run_fpga_flow.py | 41 ++++++++------------------ openfpga_flow/scripts/run_fpga_task.py | 2 +- 2 files changed, 14 insertions(+), 29 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index f9971b6aa..4ea9fbf8b 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -215,10 +215,10 @@ def main(): if (args.fpga_flow == "yosys_vpr"): logger.info('Running "yosys_vpr" Flow') run_yosys_with_abc() - run_rewrite_verilog() if args.power: run_ace2() run_pro_blif_3arg() + run_rewrite_verilog() if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() # if (args.fpga_flow == "vtr"): @@ -741,7 +741,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): process.returncode) except (Exception, subprocess.CalledProcessError) as e: logger.exception("Failed to run VPR") - process_failed_vpr_run(e.output) + filter_failed_process_output(e.output) clean_up_and_exit("") logger.info("VPR output is written in file %s" % logfile) return chan_width @@ -796,22 +796,7 @@ def run_rewrite_verilog(): "write_verilog %s" % args.top_module+"_output_verilog.v" ] command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] - try: - with open('yosys_rewrite_veri_output.txt', 'w+') as output: - process = subprocess.run(command, - check=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - universal_newlines=True) - output.write(process.stdout) - if process.returncode: - logger.info("Rewrite veri yosys run failed with returncode %d", - process.returncode) - except Exception as e: - logger.exception("Failed to run VPR") - print(e.output) - clean_up_and_exit("") - logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt") + run_command("Yosys", "yosys_output.txt", command) def run_netlists_verification(): @@ -844,8 +829,8 @@ def run_netlists_verification(): def run_command(taskname, logfile, command, exit_if_fail=True): logger.info("Launching %s " % taskname) - try: - with open(logfile, 'w+') as output: + with open(logfile, 'w+') as output: + try: output.write(" ".join(command)+"\n") process = subprocess.run(command, check=True, @@ -856,18 +841,18 @@ def run_command(taskname, logfile, command, exit_if_fail=True): if process.returncode: logger.error("%s run failed with returncode %d" % (taskname, process.returncode)) - except (Exception, subprocess.CalledProcessError) as e: - logger.exception("failed to execute %s" % taskname) - process_failed_vpr_run(e.output) - print(e.output) - if exit_if_fail: - clean_up_and_exit("Failed to run %s task" % taskname) - return None + except (Exception, subprocess.CalledProcessError) as e: + logger.exception("failed to execute %s" % taskname) + filter_failed_process_output(e.output) + output.write(e.output) + if exit_if_fail: + clean_up_and_exit("Failed to run %s task" % taskname) + return None logger.info("%s is written in file %s" % (taskname, logfile)) return process.stdout -def process_failed_vpr_run(vpr_output): +def filter_failed_process_output(vpr_output): for line in vpr_output.split("\n"): if "error" in line.lower(): logger.error("-->>" + line) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index b445c9d7e..eb18c6cda 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -245,7 +245,7 @@ def strip_child_logger_info(line): logtype, message = line.split(" - ", 1) lognumb = {"CRITICAL": 50, "ERROR": 40, "WARNING": 30, "INFO": 20, "DEBUG": 10, "NOTSET": 0} - logger.log(lognumb["INFO"], message) + logger.log(lognumb[logtype.strip().upper()], message) except: logger.info(line) From 732e24767f648a067f81027b13b601c071952a7e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 22 Aug 2019 23:48:46 -0600 Subject: [PATCH 117/482] developing module manager --- .../libarchfpga/SRC/check_circuit_library.cpp | 36 +++++ vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 14 ++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 2 + .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 145 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 67 ++++++-- .../SRC/fpga_x2p/base/module_manager_fwd.h | 4 +- 6 files changed, 253 insertions(+), 15 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index b39925326..0b08d8f58 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -345,6 +345,39 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, return num_err; } +/* Check all the ports make sure, they satisfy the restriction */ +static +size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { + size_t num_err = 0; + + /* Check global ports: make sure all the global ports are input ports */ + for (const auto& port : circuit_lib.ports()) { + if ( (circuit_lib.port_is_global(port)) + && (!circuit_lib.is_input_port(port)) ) { + vpr_printf(TIO_MESSAGE_ERROR, + "Circuit port (type=%s) of model (name=%s) is defined as global but not an input port!\n", + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))], + circuit_lib.model_name(port).c_str()); + num_err++; + } + } + + /* Check set/reset/config_enable ports: make sure they are all global ports */ + for (const auto& port : circuit_lib.ports()) { + if ( ( (circuit_lib.port_is_set(port)) + || (circuit_lib.port_is_reset(port)) + || (circuit_lib.port_is_config_enable(port)) ) + && (!circuit_lib.port_is_global(port)) ) { + vpr_printf(TIO_MESSAGE_ERROR, + "Circuit port (type=%s) of model (name=%s) is defined as a set/reset/config_enable port but it is not global!\n", + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))], + circuit_lib.model_name(port).c_str()); + num_err++; + } + } + + return num_err; +} /************************************************************************ * Check points to make sure we have a valid circuit library @@ -375,6 +408,9 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { */ num_err += check_circuit_library_unique_prefix(circuit_lib); + /* Check global ports */ + num_err += check_circuit_library_ports(circuit_lib); + /* 3. Check io has been defined and has input and output ports * [a] We must have an IOPAD! * [b] For each IOPAD, we must have at least an input, an output, an INOUT and an SRAM port diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 32e6ad2b5..f5b2ba6af 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -598,6 +598,20 @@ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { return port_is_prog_[circuit_port_id]; } +/* Return the id of parent circuit model for a circuit port */ +CircuitModelId CircuitLibrary::port_parent_model(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_model_ids_[circuit_port_id]; +} + +/* Return the name of parent circuit model for a circuit port */ +std::string CircuitLibrary::model_name(const CircuitPortId& port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(port_id)); + return model_names_[port_parent_model(port_id)]; +} + /************************************************************************ * Public Accessors : Methods to visit timing graphs ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index b0f2fd210..cab53bec6 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -266,6 +266,8 @@ class CircuitLibrary { bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; + CircuitModelId port_parent_model(const CircuitPortId& circuit_port_id) const; + std::string model_name(const CircuitPortId& port_id) const; public: /* Public Accessors: Timing graph */ /* Get source/sink nodes and delay of edges */ std::vector timing_edges_by_model(const CircuitModelId& model_id) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp new file mode 100644 index 000000000..a260ab626 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -0,0 +1,145 @@ +/****************************************************************************** + * Memember functions for data structure ModuleManager + ******************************************************************************/ +#include +#include +#include "vtr_assert.h" + +#include "circuit_library.h" +#include "module_manager.h" + +/****************************************************************************** + * Public Constructors + ******************************************************************************/ + +/****************************************************************************** + * Public Mutators + ******************************************************************************/ +/* Add a module based on its circuit-level description */ +ModuleId ModuleManager::add_module_with_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + ModuleId module = add_module(circuit_lib.model_name(circuit_model)); + + /* Add ports */ + /* Find global ports and add one by one */ + for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { + BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + add_port(module, port_info, MODULE_GLOBAL_PORT); + } + + /* Find other ports and add one by one */ + /* Create a type-to-type map for ports */ + std::map port_type2type_map; + port_type2type_map[SPICE_MODEL_PORT_INOUT] = MODULE_INOUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_INPUT] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_CLOCK] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_SRAM] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BL] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BLB] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WL] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WLB] = MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = MODULE_OUTPUT_PORT; + + /* Input ports (ignore all the global ports when searching the circuit_lib */ + for (const auto& kv : port_type2type_map) { + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { + BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + add_port(module, port_info, kv.second); + } + } + + /* Return the new id */ + return module; +} + +/* Add a module */ +ModuleId ModuleManager::add_module(const std::string& name) { + /* Find if the name has been used. If used, return an invalid Id and report error! */ + std::map::iterator it = name_id_map_.find(name); + if (it != name_id_map_.end()) { + return ModuleId::INVALID(); + } + + /* Create an new id */ + ModuleId module = ModuleId(ids_.size()); + ids_.push_back(module); + + /* Allocate other attributes */ + names_.push_back(name); + parents_.emplace_back(); + children_.emplace_back(); + + port_ids_.emplace_back(); + ports_.emplace_back(); + port_types_.emplace_back(); + + /* Register in the name-to-id map */ + name_id_map_[name] = module; + + /* Build port lookup */ + port_lookup_.emplace_back(); + port_lookup_[module].resize(NUM_MODULE_PORT_TYPES); + + /* Return the new id */ + return module; +} + +/* Add a port to a module */ +ModulePortId ModuleManager::add_port(const ModuleId& module, + const BasicPort& port_info, const enum e_module_port_type& port_type) { + /* Validate the id of module */ + VTR_ASSERT( valid_module_id(module) ); + + /* Add port and fill port attributes */ + ModulePortId port = ModulePortId(port_ids_[module].size()); + port_ids_[module].push_back(port); + ports_[module].push_back(port_info); + port_types_[module].push_back(port_type); + + /* Update fast look-up for port */ + port_lookup_[module][port_type].push_back(port); + + return port; +} + +/* Add a child module to a parent module */ +void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module) { + /* Validate the id of both parent and child modules */ + VTR_ASSERT ( valid_module_id(parent_module) ); + VTR_ASSERT ( valid_module_id(child_module) ); + + /* Try to find if the parent module is already in the list */ + std::vector::iterator parent_it = std::find(parents_[child_module].begin(), parents_[child_module].end(), parent_module); + if (parent_it == parents_[child_module].end()) { + /* Update the parent module of child module */ + parents_[child_module].push_back(parent_module); + } + + std::vector::iterator child_it = std::find(children_[child_module].begin(), children_[child_module].end(), child_module); + if (child_it == children_[parent_module].end()) { + /* Update the child module of parent module */ + children_[parent_module].push_back(child_module); + } +} + +/****************************************************************************** + * Private validators/invalidators + ******************************************************************************/ +bool ModuleManager::valid_module_id(const ModuleId& module) const { + return ( size_t(module) < ids_.size() ) && ( module == ids_[module] ); +} + +bool ModuleManager::valid_module_port_id(const ModuleId& module, const ModulePortId& port) const { + if (false == valid_module_id(module)) { + return false; + } + return ( size_t(port) < port_ids_[module].size() ) && ( port == port_ids_[module][port] ); +} + +void ModuleManager::invalidate_name2id_map() { + name_id_map_.clear(); +} + +void ModuleManager::invalidate_port_lookup() { + port_lookup_.clear(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 76dc603e8..fc3d14ab3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -1,27 +1,66 @@ -/************************************************ - * This files includes data structures for - * module management. - * It keeps a list of modules that have been - * generated, the port map of the modules, - * parents and children of each modules - * This will ease instanciation of modules - * with explicit port map and outputting a - * hierarchy of modules - ***********************************************/ +/****************************************************************************** + * This files includes data structures for module management. + * It keeps a list of modules that have been generated, the port map of the modules, + * parents and children of each modules. This will ease instanciation of modules + * with explicit port map and outputting a hierarchy of modules + * + * Module includes the basic information: + * 1. unique identifier + * 2. module name: which should be unique + * 3. port list: basic information of all the ports belonging to the module + * 4. port types: types of each port, which will matter how we output the ports + * 5. parent modules: ids of parent modules + * 6. children modules: ids of child modules + ******************************************************************************/ #ifndef MODULE_MANAGER_H #define MODULE_MANAGER_H #include +#include #include "module_manager_fwd.h" #include "device_port.h" class ModuleManager { + private: /* Private data structures */ + enum e_module_port_type { + MODULE_GLOBAL_PORT, + MODULE_INOUT_PORT, + MODULE_INPUT_PORT, + MODULE_OUTPUT_PORT, + MODULE_CLOCK_PORT, + NUM_MODULE_PORT_TYPES + }; + public: /* Public Constructors */ + public: /* Public mutators */ + /* Add a module */ + ModuleId add_module_with_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); + ModuleId add_module(const std::string& name); + /* Add a port to a module */ + ModulePortId add_port(const ModuleId& module, + const BasicPort& port_info, const enum e_module_port_type& port_type); + /* Add a child module to a parent module */ + void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); + private: /* Private validators/invalidators */ + bool valid_module_id(const ModuleId& module) const; + bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; + void invalidate_name2id_map(); + void invalidate_port_lookup(); private: /* Internal data */ - vtr::vector ids_; - vtr::vector ports_; - vtr::vector> parents_; - vtr::vector> children_; + vtr::vector ids_; /* Unique identifier for each Module */ + vtr::vector names_; /* Unique identifier for each Module */ + vtr::vector> parents_; /* Parent modules that include the module */ + vtr::vector> children_; /* Child modules that this module contain */ + + vtr::vector> port_ids_; /* List of ports for each Module */ + vtr::vector> ports_; /* List of ports for each Module */ + vtr::vector> port_types_; /* Type of ports */ + + /* fast look-up for module */ + std::map name_id_map_; + /* fast look-up for ports */ + typedef vtr::vector>> PortLookup; + mutable PortLookup port_lookup_; /* [module_ids][port_types][port_ids] */ }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h index abaa0854b..798cc67f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h @@ -8,10 +8,12 @@ #include "vtr_strong_id.h" -/* Strong Ids for MUXes */ +/* Strong Ids for ModuleManager */ struct module_id_tag; +struct module_port_id_tag; typedef vtr::StrongId ModuleId; +typedef vtr::StrongId ModulePortId; class ModuleManager; From 520630c5e2b66cee901e0bcb0d849aa37151557c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 10:16:52 -0600 Subject: [PATCH 118/482] add more testing tasks --- ...0_sram_chain_HC_local_encoder_template.xml | 1042 +++++++++++++++++ run_test.sh | 59 +- 2 files changed, 1100 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml new file mode 100644 index 000000000..48e1503c7 --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml @@ -0,0 +1,1042 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/run_test.sh b/run_test.sh index d218e9c52..a696178f8 100644 --- a/run_test.sh +++ b/run_test.sh @@ -16,7 +16,7 @@ # --vpr_fpga_verilog_print_autocheck_top_testbench - +# Test popular multi-mode architecture python3.5 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ @@ -44,3 +44,60 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --vpr_fpga_x2p_compact_routing_hierarchy \ --end_flow_with_test +# Test Standard cell MUX2 +#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +#./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ +#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +#--fpga_flow vpr_blif \ +#--top_module test_modes \ +#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +#--power \ +#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +#--fix_route_chan_width 300 \ +#--vpr_fpga_verilog \ +#--vpr_fpga_verilog_dir . \ +#--vpr_fpga_x2p_rename_illegal_port \ +#--vpr_fpga_verilog_include_icarus_simulator \ +#--vpr_fpga_verilog_formal_verification_top_netlist \ +#--vpr_fpga_verilog_include_timing \ +#--vpr_fpga_verilog_include_signal_init \ +#--vpr_fpga_verilog_print_autocheck_top_testbench \ +#--debug \ +#--vpr_fpga_bitstream_generator \ +#--vpr_fpga_verilog_print_user_defined_template \ +#--vpr_fpga_verilog_print_report_timing_tcl \ +#--vpr_fpga_verilog_print_sdc_pnr \ +#--vpr_fpga_verilog_print_sdc_analysis \ +#--vpr_fpga_x2p_compact_routing_hierarchy \ +#--end_flow_with_test + +# Test local encoder feature +python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \ +./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +--fpga_flow vpr_blif \ +--top_module test_modes \ +--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +--power \ +--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +--fix_route_chan_width 300 \ +--vpr_fpga_verilog \ +--vpr_fpga_verilog_dir . \ +--vpr_fpga_x2p_rename_illegal_port \ +--vpr_fpga_verilog_include_icarus_simulator \ +--vpr_fpga_verilog_formal_verification_top_netlist \ +--vpr_fpga_verilog_include_timing \ +--vpr_fpga_verilog_include_signal_init \ +--vpr_fpga_verilog_print_autocheck_top_testbench \ +--debug \ +--vpr_fpga_bitstream_generator \ +--vpr_fpga_verilog_print_user_defined_template \ +--vpr_fpga_verilog_print_report_timing_tcl \ +--vpr_fpga_verilog_print_sdc_pnr \ +--vpr_fpga_verilog_print_sdc_analysis \ +--vpr_fpga_x2p_compact_routing_hierarchy \ +--end_flow_with_test + + From 28dde899db74ecc84f560f5c9b16693950ff9489 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 23 Aug 2019 12:44:45 -0600 Subject: [PATCH 119/482] Updated Architecture Template --- openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml index 72c966086..25577a130 100644 --- a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml +++ b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml @@ -290,7 +290,7 @@ - + @@ -362,7 +362,7 @@ - + From 82a186bf7c4c5e90c3779ba495ecd02e879b907f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 23 Aug 2019 12:45:17 -0600 Subject: [PATCH 120/482] Added python3.5 in travis script --- .travis/script.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/script.sh b/.travis/script.sh index f7aeef4cb..06909c457 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -12,6 +12,8 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then cd build cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off make -j2 + alias python3.5="python3" + ln -s /opt/local/bin/python3 /opt/loca/bin/python3.5 else # For linux, we enable full package compilation #make From 931b042750855e79e9fedede516db3f3306aec07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 12:52:01 -0600 Subject: [PATCH 121/482] refactoring module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 37 ------------- .../vpr/SRC/fpga_x2p/base/module_manager.h | 3 +- .../fpga_x2p/base/module_manager_utils.cpp | 52 +++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 14 +++++ 4 files changed, 67 insertions(+), 39 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index a260ab626..2affed6a4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -15,43 +15,6 @@ /****************************************************************************** * Public Mutators ******************************************************************************/ -/* Add a module based on its circuit-level description */ -ModuleId ModuleManager::add_module_with_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - ModuleId module = add_module(circuit_lib.model_name(circuit_model)); - - /* Add ports */ - /* Find global ports and add one by one */ - for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { - BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - add_port(module, port_info, MODULE_GLOBAL_PORT); - } - - /* Find other ports and add one by one */ - /* Create a type-to-type map for ports */ - std::map port_type2type_map; - port_type2type_map[SPICE_MODEL_PORT_INOUT] = MODULE_INOUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_INPUT] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_CLOCK] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_SRAM] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BL] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BLB] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WL] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WLB] = MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = MODULE_OUTPUT_PORT; - - /* Input ports (ignore all the global ports when searching the circuit_lib */ - for (const auto& kv : port_type2type_map) { - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { - BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - add_port(module, port_info, kv.second); - } - } - - /* Return the new id */ - return module; -} - /* Add a module */ ModuleId ModuleManager::add_module(const std::string& name) { /* Find if the name has been used. If used, return an invalid Id and report error! */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index fc3d14ab3..553974a7c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -22,7 +22,7 @@ #include "device_port.h" class ModuleManager { - private: /* Private data structures */ + public: /* Private data structures */ enum e_module_port_type { MODULE_GLOBAL_PORT, MODULE_INOUT_PORT, @@ -34,7 +34,6 @@ class ModuleManager { public: /* Public Constructors */ public: /* Public mutators */ /* Add a module */ - ModuleId add_module_with_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); ModuleId add_module(const std::string& name); /* Add a port to a module */ ModulePortId add_port(const ModuleId& module, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp new file mode 100644 index 000000000..f375c446c --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -0,0 +1,52 @@ +/****************************************************************************** + * This files includes most utilized functions + * for data structures for module management. + ******************************************************************************/ + +#include +#include + +#include "vtr_assert.h" + +#include "spice_types.h" + +#include "circuit_library.h" +#include "module_manager.h" +#include "module_manager_utils.h" + +ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { + ModuleId module = module_manager.add_module(circuit_lib.model_name(circuit_model)); + + /* Add ports */ + /* Find global ports and add one by one */ + for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { + BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); + } + + /* Find other ports and add one by one */ + /* Create a type-to-type map for ports */ + std::map port_type2type_map; + port_type2type_map[SPICE_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_CLOCK] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT; + + /* Input ports (ignore all the global ports when searching the circuit_lib */ + for (const auto& kv : port_type2type_map) { + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { + BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module, port_info, kv.second); + } + } + + /* Return the new id */ + return module; + +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h new file mode 100644 index 000000000..6868b71f7 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -0,0 +1,14 @@ +/****************************************************************************** + * This files includes declarations for most utilized functions + * for data structures for module management. + ******************************************************************************/ + +#ifndef MODULE_MANAGER_UTILS_H +#define MODULE_MANAGER_UTILS_H + +ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); + + +#endif + From e55c6d5b417f46092f4a10987f81f549a83f452b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 14:09:20 -0600 Subject: [PATCH 122/482] add more tests --- ...k6_N10_sram_chain_HC_tileable_template.xml | 1042 +++++++++++++++++ run_test.sh | 84 +- 2 files changed, 1099 insertions(+), 27 deletions(-) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml new file mode 100644 index 000000000..57967f2e9 --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml @@ -0,0 +1,1042 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/run_test.sh b/run_test.sh index a696178f8..58eb6e869 100644 --- a/run_test.sh +++ b/run_test.sh @@ -15,7 +15,6 @@ # --vpr_fpga_verilog_include_signal_init \ # --vpr_fpga_verilog_print_autocheck_top_testbench - # Test popular multi-mode architecture python3.5 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ @@ -26,7 +25,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ --power \ --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ ---fix_route_chan_width 300 \ +#--fix_route_chan_width 300 \ +--min_route_chan_width 1.3 \ --vpr_fpga_verilog \ --vpr_fpga_verilog_dir . \ --vpr_fpga_x2p_rename_illegal_port \ @@ -45,32 +45,33 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --end_flow_with_test # Test Standard cell MUX2 -#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -#./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ -#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ -#--fpga_flow vpr_blif \ -#--top_module test_modes \ -#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ -#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ -#--power \ -#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ +./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +--fpga_flow vpr_blif \ +--top_module test_modes \ +--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +--power \ +--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ #--fix_route_chan_width 300 \ -#--vpr_fpga_verilog \ -#--vpr_fpga_verilog_dir . \ -#--vpr_fpga_x2p_rename_illegal_port \ -#--vpr_fpga_verilog_include_icarus_simulator \ -#--vpr_fpga_verilog_formal_verification_top_netlist \ -#--vpr_fpga_verilog_include_timing \ -#--vpr_fpga_verilog_include_signal_init \ -#--vpr_fpga_verilog_print_autocheck_top_testbench \ -#--debug \ -#--vpr_fpga_bitstream_generator \ -#--vpr_fpga_verilog_print_user_defined_template \ -#--vpr_fpga_verilog_print_report_timing_tcl \ -#--vpr_fpga_verilog_print_sdc_pnr \ -#--vpr_fpga_verilog_print_sdc_analysis \ -#--vpr_fpga_x2p_compact_routing_hierarchy \ -#--end_flow_with_test +--min_route_chan_width 1.3 \ +--vpr_fpga_verilog \ +--vpr_fpga_verilog_dir . \ +--vpr_fpga_x2p_rename_illegal_port \ +--vpr_fpga_verilog_include_icarus_simulator \ +--vpr_fpga_verilog_formal_verification_top_netlist \ +--vpr_fpga_verilog_include_timing \ +--vpr_fpga_verilog_include_signal_init \ +--vpr_fpga_verilog_print_autocheck_top_testbench \ +--debug \ +--vpr_fpga_bitstream_generator \ +--vpr_fpga_verilog_print_user_defined_template \ +--vpr_fpga_verilog_print_report_timing_tcl \ +--vpr_fpga_verilog_print_sdc_pnr \ +--vpr_fpga_verilog_print_sdc_analysis \ +--vpr_fpga_x2p_compact_routing_hierarchy \ +--end_flow_with_test # Test local encoder feature python3.5 openfpga_flow/scripts/run_fpga_flow.py \ @@ -100,4 +101,33 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --vpr_fpga_x2p_compact_routing_hierarchy \ --end_flow_with_test +# Test tileable routing feature +#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +#./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \ +#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +#--fpga_flow vpr_blif \ +#--top_module test_modes \ +#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +#--power \ +#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +##--fix_route_chan_width 300 \ +#--min_route_chan_width 1.3 \ +#--vpr_fpga_verilog \ +#--vpr_fpga_verilog_dir . \ +#--vpr_fpga_x2p_rename_illegal_port \ +#--vpr_fpga_verilog_include_icarus_simulator \ +#--vpr_fpga_verilog_formal_verification_top_netlist \ +#--vpr_fpga_verilog_include_timing \ +#--vpr_fpga_verilog_include_signal_init \ +#--vpr_fpga_verilog_print_autocheck_top_testbench \ +#--debug \ +#--vpr_fpga_bitstream_generator \ +#--vpr_fpga_verilog_print_user_defined_template \ +#--vpr_fpga_verilog_print_report_timing_tcl \ +#--vpr_fpga_verilog_print_sdc_pnr \ +#--vpr_fpga_verilog_print_sdc_analysis \ +#--vpr_fpga_x2p_compact_routing_hierarchy \ +#--vpr_use_tileable_route_chan_width \ +#--end_flow_with_test From 3fb308244794c269cfd8325179b79fd1a68c9a77 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 14:09:20 -0600 Subject: [PATCH 123/482] add more tests --- ...k6_N10_sram_chain_HC_tileable_template.xml | 1042 +++++++++++++++++ run_test.sh | 84 +- 2 files changed, 1099 insertions(+), 27 deletions(-) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml new file mode 100644 index 000000000..57967f2e9 --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml @@ -0,0 +1,1042 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/run_test.sh b/run_test.sh index a696178f8..58eb6e869 100644 --- a/run_test.sh +++ b/run_test.sh @@ -15,7 +15,6 @@ # --vpr_fpga_verilog_include_signal_init \ # --vpr_fpga_verilog_print_autocheck_top_testbench - # Test popular multi-mode architecture python3.5 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ @@ -26,7 +25,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ --power \ --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ ---fix_route_chan_width 300 \ +#--fix_route_chan_width 300 \ +--min_route_chan_width 1.3 \ --vpr_fpga_verilog \ --vpr_fpga_verilog_dir . \ --vpr_fpga_x2p_rename_illegal_port \ @@ -45,32 +45,33 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --end_flow_with_test # Test Standard cell MUX2 -#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -#./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ -#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ -#--fpga_flow vpr_blif \ -#--top_module test_modes \ -#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ -#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ -#--power \ -#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ +./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +--fpga_flow vpr_blif \ +--top_module test_modes \ +--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +--power \ +--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ #--fix_route_chan_width 300 \ -#--vpr_fpga_verilog \ -#--vpr_fpga_verilog_dir . \ -#--vpr_fpga_x2p_rename_illegal_port \ -#--vpr_fpga_verilog_include_icarus_simulator \ -#--vpr_fpga_verilog_formal_verification_top_netlist \ -#--vpr_fpga_verilog_include_timing \ -#--vpr_fpga_verilog_include_signal_init \ -#--vpr_fpga_verilog_print_autocheck_top_testbench \ -#--debug \ -#--vpr_fpga_bitstream_generator \ -#--vpr_fpga_verilog_print_user_defined_template \ -#--vpr_fpga_verilog_print_report_timing_tcl \ -#--vpr_fpga_verilog_print_sdc_pnr \ -#--vpr_fpga_verilog_print_sdc_analysis \ -#--vpr_fpga_x2p_compact_routing_hierarchy \ -#--end_flow_with_test +--min_route_chan_width 1.3 \ +--vpr_fpga_verilog \ +--vpr_fpga_verilog_dir . \ +--vpr_fpga_x2p_rename_illegal_port \ +--vpr_fpga_verilog_include_icarus_simulator \ +--vpr_fpga_verilog_formal_verification_top_netlist \ +--vpr_fpga_verilog_include_timing \ +--vpr_fpga_verilog_include_signal_init \ +--vpr_fpga_verilog_print_autocheck_top_testbench \ +--debug \ +--vpr_fpga_bitstream_generator \ +--vpr_fpga_verilog_print_user_defined_template \ +--vpr_fpga_verilog_print_report_timing_tcl \ +--vpr_fpga_verilog_print_sdc_pnr \ +--vpr_fpga_verilog_print_sdc_analysis \ +--vpr_fpga_x2p_compact_routing_hierarchy \ +--end_flow_with_test # Test local encoder feature python3.5 openfpga_flow/scripts/run_fpga_flow.py \ @@ -100,4 +101,33 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --vpr_fpga_x2p_compact_routing_hierarchy \ --end_flow_with_test +# Test tileable routing feature +#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +#./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \ +#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +#--fpga_flow vpr_blif \ +#--top_module test_modes \ +#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +#--power \ +#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +##--fix_route_chan_width 300 \ +#--min_route_chan_width 1.3 \ +#--vpr_fpga_verilog \ +#--vpr_fpga_verilog_dir . \ +#--vpr_fpga_x2p_rename_illegal_port \ +#--vpr_fpga_verilog_include_icarus_simulator \ +#--vpr_fpga_verilog_formal_verification_top_netlist \ +#--vpr_fpga_verilog_include_timing \ +#--vpr_fpga_verilog_include_signal_init \ +#--vpr_fpga_verilog_print_autocheck_top_testbench \ +#--debug \ +#--vpr_fpga_bitstream_generator \ +#--vpr_fpga_verilog_print_user_defined_template \ +#--vpr_fpga_verilog_print_report_timing_tcl \ +#--vpr_fpga_verilog_print_sdc_pnr \ +#--vpr_fpga_verilog_print_sdc_analysis \ +#--vpr_fpga_x2p_compact_routing_hierarchy \ +#--vpr_use_tileable_route_chan_width \ +#--end_flow_with_test From 2e3f906d40042ea4116b78d6205f2558cae31479 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 23 Aug 2019 16:03:21 -0600 Subject: [PATCH 124/482] Solved bug in travis script file --- .travis/script.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index 06909c457..926d8c15e 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -13,7 +13,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off make -j2 alias python3.5="python3" - ln -s /opt/local/bin/python3 /opt/loca/bin/python3.5 + ln -s /opt/local/bin/python3 /opt/local/bin/python3.5 else # For linux, we enable full package compilation #make From 37a092e885bfb839d9c3b2b71f8fa42184209e13 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 16:36:30 -0600 Subject: [PATCH 125/482] add recursive global port searching for circuit library --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 131 +++++++++++++++++- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 13 +- .../fpga_x2p/base/module_manager_utils.cpp | 3 +- .../verilog/verilog_essential_gates.cpp | 6 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 2 +- 5 files changed, 142 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index f5b2ba6af..a423e5409 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -372,12 +372,14 @@ std::vector CircuitLibrary::model_ports(const CircuitModelId& mod } /* Recursively find all the global ports in the circuit model / sub circuit_model */ -std::vector CircuitLibrary::model_global_ports(const CircuitModelId& model_id) const { +std::vector CircuitLibrary::model_global_ports(const CircuitModelId& model_id, + const bool& recursive) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); - /* Search all the ports */ std::vector global_ports; + + /* Search all the ports */ for (auto port : model_ports(model_id)) { /* By pass non-global ports*/ if (false == port_is_global(port)) { @@ -387,12 +389,39 @@ std::vector CircuitLibrary::model_global_ports(const CircuitModel global_ports.push_back(port); } + /* Finish, if we do not need to go recursively */ + if (false == recursive) { + return global_ports; + } + + /* If go recursively, we search all the buffer/pass-gate circuit model ids */ + /* Go search every sub circuit model included the current circuit model */ + for (const auto& sub_model : sub_models_[model_id]) { + std::vector sub_global_ports = model_global_ports(sub_model, recursive); + for (const auto& sub_global_port : sub_global_ports) { + /* Add to global_ports, if it is not already found in the list */ + bool add_to_list = true; + for (const auto& global_port : global_ports) { + if (0 == port_prefix(sub_global_port).compare(port_prefix(global_port))) { + /* Same name, skip list update */ + add_to_list = false; + break; + } + } + if (true == add_to_list) { + /* Add the sub_global_port to the list */ + global_ports.push_back(sub_global_port); + } + } + } + return global_ports; } /* Recursively find all the global ports in the circuit model / sub circuit_model */ std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type) const { + const enum e_spice_model_port_type& type, + const bool& recursive) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -411,6 +440,32 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ global_ports.push_back(port); } + /* Finish, if we do not need to go recursively */ + if (false == recursive) { + return global_ports; + } + + /* If go recursively, we search all the buffer/pass-gate circuit model ids */ + /* Go search every sub circuit model included the current circuit model */ + for (const auto& sub_model : sub_models_[model_id]) { + std::vector sub_global_ports = model_global_ports_by_type(sub_model, type, recursive); + for (const auto& sub_global_port : sub_global_ports) { + /* Add to global_ports, if it is not already found in the list */ + bool add_to_list = true; + for (const auto& global_port : global_ports) { + if (0 == port_prefix(sub_global_port).compare(port_prefix(global_port))) { + /* Same name, skip list update */ + add_to_list = false; + break; + } + } + if (true == add_to_list) { + /* Add the sub_global_port to the list */ + global_ports.push_back(sub_global_port); + } + } + } + return global_ports; } @@ -741,6 +796,7 @@ CircuitModelId CircuitLibrary::add_model(const enum e_spice_model_type& type) { model_verilog_netlists_.emplace_back(); model_spice_netlists_.emplace_back(); model_is_default_.push_back(false); + sub_models_.emplace_back(); /* Verilog generator options */ dump_structural_verilog_.push_back(false); @@ -1569,7 +1625,70 @@ void CircuitLibrary::link_pass_gate_logic_model(const CircuitModelId& model_id) } pass_gate_logic_model_ids_[model_id] = model(pass_gate_logic_model_names_[model_id]); return; -} +} + +/* Find if a model is already in the submodel list */ +bool CircuitLibrary::is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + VTR_ASSERT(valid_model_id(submodel_id)); + + std::vector::iterator it = std::find(sub_models_[model_id].begin(), sub_models_[model_id].end(), submodel_id); + if (it == sub_models_[model_id].end()) { + return true; + } + return false; +} + +/* Build the sub module list for each circuit model, + * Find the linked circuit model id in + * pass-gate, buffers, ports */ +void CircuitLibrary::build_submodels() { + for (const auto& model: models()) { + /* Make sure a clean start */ + sub_models_[model].clear(); + + /* build a list of candidates */ + std::vector candidates; + + /* Find buffer models */ + for (const auto& buffer_model : buffer_model_ids_[model]) { + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() == buffer_model) { + continue; + } + candidates.push_back(buffer_model); + } + + /* Find pass-gate models */ + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() != pass_gate_logic_model_ids_[model]) { + candidates.push_back(pass_gate_logic_model_ids_[model]); + } + + /* Find each port circuit models */ + for (const auto& port: model_ports(model)) { + /* Find tri-state circuit models */ + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() != port_tri_state_model_ids_[port]) { + candidates.push_back(port_tri_state_model_ids_[port]); + } + /* Find inv circuit models */ + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() != port_inv_model_ids_[port]) { + candidates.push_back(port_inv_model_ids_[port]); + } + } + + /* Build a unique list */ + for (const auto& cand : candidates) { + /* Make sure the model id is unique in the list */ + if (true == is_unique_submodel(model,cand)) { + sub_models_[model].push_back(cand); + } + } + } +} /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { @@ -1612,6 +1731,10 @@ void CircuitLibrary::build_model_links() { /* Build links for ports */ link_port_tri_state_model(); link_port_inv_model(); + + /* Build submodels */ + build_submodels(); + return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index cab53bec6..a638ea8d1 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -74,6 +74,8 @@ * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated * 7. is_default_: indicate if the circuit model is the default one among all those in the same type + * 8. sub_models_: the sub circuit models included by a circuit model. It is a collection of unique circuit model ids + * found in the CircuitModelId of pass-gate/buffers/port-related circuit models. * * ------ Fast look-ups----- * 1. model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users @@ -243,9 +245,10 @@ class CircuitLibrary { size_t num_model_ports(const CircuitModelId& model_id) const; size_t num_model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_ports(const CircuitModelId& model_id) const; - std::vector model_global_ports(const CircuitModelId& model_id) const; + std::vector model_global_ports(const CircuitModelId& model_id, const bool& recursive) const; std::vector model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type) const; + const enum e_spice_model_port_type& type, + const bool& recursive) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_input_ports(const CircuitModelId& model_id) const; @@ -426,6 +429,8 @@ class CircuitLibrary { void link_port_inv_model(); void link_buffer_model(const CircuitModelId& model_id); void link_pass_gate_logic_model(const CircuitModelId& model_id); + bool is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id); + void build_submodels(); void build_model_timing_graph(const CircuitModelId& model_id); public: /* Public Mutators: builders */ void build_model_links(); @@ -466,6 +471,9 @@ class CircuitLibrary { vtr::vector model_spice_netlists_; vtr::vector model_is_default_; + /* Submodules that a circuit model contains */ + vtr::vector> sub_models_; + /* fast look-up for circuit models to categorize by types * [type][num_ids] * Important: we force the default circuit model in the first element for each type @@ -566,7 +574,6 @@ class CircuitLibrary { vtr::vector wire_types_; vtr::vector> wire_rc_; /* x => wire_res_val, y=> wire_cap_val */ vtr::vector wire_num_levels_; - }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index f375c446c..85502cc48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -20,7 +20,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Add ports */ /* Find global ports and add one by one */ - for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { + for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) { BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); } @@ -48,5 +48,4 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Return the new id */ return module; - } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index a5378fcd9..41d2fb560 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -145,7 +145,7 @@ void print_verilog_invbuf_module(std::fstream& fp, /* Find the input port, output port and global inputs*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Make sure: * There is only 1 input port and 1 output port, @@ -248,7 +248,7 @@ void print_verilog_passgate_module(std::fstream& fp, /* Find the input port, output port*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); switch (circuit_lib.pass_gate_logic_type(circuit_model)) { case SPICE_MODEL_PASS_GATE_TRANSMISSION: @@ -483,7 +483,7 @@ void print_verilog_gate_module(std::fstream& fp, /* Find the input port, output port*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Make sure: * There is only 1 output port, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 9255097c9..dce86830a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -47,7 +47,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, /* Get model ports of tgate */ std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT); + std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); VTR_ASSERT(3 == tgate_input_ports.size()); VTR_ASSERT(1 == tgate_output_ports.size()); From 8eebca9daace2a211da5d6fcdbaa96c7826b4b5c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 17:39:29 -0600 Subject: [PATCH 126/482] plug in module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 33 +++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 4 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 7 +- .../verilog/verilog_essential_gates.cpp | 117 ++++-------------- .../verilog/verilog_essential_gates.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 6 +- .../SRC/fpga_x2p/verilog/verilog_submodules.h | 6 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 47 ++++++- .../fpga_x2p/verilog/verilog_writer_utils.h | 7 ++ 9 files changed, 134 insertions(+), 96 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 2affed6a4..a6007be3d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -12,6 +12,39 @@ * Public Constructors ******************************************************************************/ +/****************************************************************************** + * Public Accessors + ******************************************************************************/ +/* Find the name of a module */ +std::string ModuleManager::module_name(const ModuleId& module_id) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module_id)); + return names_[module_id]; +} + +/* Get the string of a module port type */ +std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const { + std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; + return MODULE_PORT_TYPE_STRING[port_type]; +} + +/* Find a list of ports of a module by a given types */ +std::vector ModuleManager::module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module_id)); + + std::vector ports; + for (const auto& port : port_ids_[module_id]) { + /* Skip unmatched ports */ + if (port_type != port_types_[module_id][port]) { + continue; + } + ports.push_back(ports_[module_id][port]); + } + + return ports; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 553974a7c..2df7b2cf2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -32,6 +32,10 @@ class ModuleManager { NUM_MODULE_PORT_TYPES }; public: /* Public Constructors */ + public: /* Public accessors */ + std::string module_name(const ModuleId& module_id) const; + std::string module_port_type_str(const enum e_module_port_type& port_type) const; + std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a0a3e773c..6a7dc7029 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -32,6 +32,8 @@ #include "fpga_x2p_globals.h" #include "fpga_bitstream.h" +#include "module_manager.h" + /* Include SynVerilog headers */ #include "verilog_global.h" #include "verilog_utils.h" @@ -148,6 +150,9 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, t_sram_orgz_info* sram_verilog_orgz_info = NULL; + /* Module manager for the Verilog modules created */ + ModuleManager module_manager; + /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n"); @@ -269,7 +274,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ - dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path, + dump_verilog_submodules(module_manager, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, Arch, &vpr_setup.RoutingArch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 41d2fb560..8aba48226 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -13,6 +13,8 @@ /* FPGA-X2P context header files */ #include "fpga_x2p_utils.h" +#include "module_manager.h" +#include "module_manager_utils.h" /* FPGA-Verilog context header files */ #include "verilog_global.h" @@ -136,7 +138,8 @@ void print_verilog_invbuf_body(std::fstream& fp, * or tapered buffer to a file ***********************************************/ static -void print_verilog_invbuf_module(std::fstream& fp, +void print_verilog_invbuf_module(ModuleManager& module_manager, + std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Ensure a valid file handler*/ @@ -178,30 +181,11 @@ void print_verilog_invbuf_module(std::fstream& fp, } } - /* dump module body */ - print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - /* TODO: print global ports, this should be handled by ModuleManager */ - for (const auto& port : global_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - /* Dump ports */ - BasicPort input_port; - /* Configure each input port */ - input_port.set_name(circuit_lib.port_lib_name(input_ports[0])); - input_port.set_width(circuit_lib.port_size(input_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl; - - BasicPort output_port; - /* Configure each input port */ - output_port.set_name(circuit_lib.port_lib_name(output_ports[0])); - output_port.set_width(circuit_lib.port_size(output_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << std::endl; - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); /* Finish dumping ports */ /* Assign logics : depending on topology */ @@ -239,7 +223,8 @@ void print_verilog_invbuf_module(std::fstream& fp, * either transmission-gate or pass-transistor ***********************************************/ static -void print_verilog_passgate_module(std::fstream& fp, +void print_verilog_passgate_module(ModuleManager& module_manager, + std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Ensure a valid file handler*/ @@ -284,37 +269,12 @@ void print_verilog_passgate_module(std::fstream& fp, */ VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - /* Print Verilog module */ - print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - /* TODO: print global ports, this should be handled by ModuleManager */ - for (const auto& port : global_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - for (const auto& input_port : input_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - /* Configure each global port */ - for (const auto& output_port : output_ports) { - BasicPort basic_port(circuit_lib.port_lib_name(output_port), circuit_lib.port_size(output_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, basic_port); - /* Last port does not need a comma */ - if (output_port != output_ports.back()) { - fp << "," << std::endl; - } else { - fp << std::endl; - } - } - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ /* Dump logics: we propagate input to the output when the gate is '1' * the input is blocked from output when the gate is '0' @@ -474,7 +434,8 @@ void print_verilog_mux2_gate_body(std::fstream& fp, * 3. 2-input MUX ***********************************************/ static -void print_verilog_gate_module(std::fstream& fp, +void print_verilog_gate_module(ModuleManager& module_manager, + std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Ensure a valid file handler*/ @@ -491,37 +452,12 @@ void print_verilog_gate_module(std::fstream& fp, */ VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - /* Print Verilog module */ - print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - /* TODO: print global ports, this should be handled by ModuleManager */ - for (const auto& port : global_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - for (const auto& input_port : input_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - /* Configure each global port */ - for (const auto& output_port : output_ports) { - BasicPort basic_port(circuit_lib.port_lib_name(output_port), circuit_lib.port_size(output_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, basic_port); - /* Last port does not need a comma */ - if (output_port != output_ports.back()) { - fp << "," << std::endl; - } else { - fp << std::endl; - } - } - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ /* Dump logics */ switch (circuit_lib.gate_type(circuit_model)) { @@ -554,7 +490,8 @@ void print_verilog_gate_module(std::fstream& fp, * include inverters, buffers, transmission-gates, * etc. ***********************************************/ -void print_verilog_submodule_essentials(const std::string& verilog_dir, +void print_verilog_submodule_essentials(ModuleManager& module_manager, + const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ @@ -582,15 +519,15 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, continue; } if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { - print_verilog_invbuf_module(fp, circuit_lib, circuit_model); + print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model); continue; } if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { - print_verilog_passgate_module(fp, circuit_lib, circuit_model); + print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model); continue; } if (SPICE_MODEL_GATE == circuit_lib.model_type(circuit_model)) { - print_verilog_gate_module(fp, circuit_lib, circuit_model); + print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model); continue; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h index fa9b13660..bbdd60b69 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h @@ -12,7 +12,8 @@ #include #include "circuit_library.h" -void print_verilog_submodule_essentials(const std::string& verilog_dir, +void print_verilog_submodule_essentials(ModuleManager& module_manager, + const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index cb8ca95ef..230306d3c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3506,7 +3506,8 @@ void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, /* Dump verilog files of submodules to be used in FPGA components : * 1. MUXes */ -void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, +void dump_verilog_submodules(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, t_arch Arch, @@ -3515,7 +3516,8 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); - print_verilog_submodule_essentials(std::string(verilog_dir), + print_verilog_submodule_essentials(module_manager, + std::string(verilog_dir), std::string(submodule_dir), Arch.spice->circuit_lib); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h index a7a384501..1e6aa814b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h @@ -1,6 +1,10 @@ #ifndef VERILOG_SUBMODULES_H #define VERILOG_SUBMODULES_H -void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, + +#include "module_manager.h" + +void dump_verilog_submodules(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, t_arch Arch, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 554579768..81c9bed5f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -82,7 +82,52 @@ void print_verilog_module_definition(std::fstream& fp, } /************************************************ - * Print a Verilog module definition + * Print a Verilog module ports based on the module id + ***********************************************/ +void print_verilog_module_ports(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id) { + check_file_handler(fp); + + /* port type2type mapping */ + std::map port_type2type_map; + port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT; + port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT; + port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_INPUT; + + /* Port sequence: global, inout, input, output and clock ports, */ + size_t port_cnt = 0; + for (const auto& kv : port_type2type_map) { + for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { + if (0 != port_cnt) { + /* Do not dump a comma for the first port */ + fp << ", //----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + } + /* Print port */ + fp << "\t" << generate_verilog_port(kv.second, port) << std::endl; + port_cnt++; + } + } +} + +/************************************************ + * Print a Verilog module declaration (definition + port list + ***********************************************/ +void print_verilog_module_declaration(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id) { + check_file_handler(fp); + + print_verilog_module_definition(fp, module_manager.module_name(module_id)); + + print_verilog_module_ports(fp, module_manager, module_id); + + fp << std::endl << ");" << std::endl; +} + + +/************************************************ + * Print an end line for a Verilog module ***********************************************/ void print_verilog_module_end(std::fstream& fp, const std::string& module_name) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 2f3d73bba..3f65fb726 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -8,6 +8,7 @@ #include #include "device_port.h" +#include "module_manager.h" void print_verilog_file_header(std::fstream& fp, const std::string& usage); @@ -21,6 +22,12 @@ void print_verilog_comment(std::fstream& fp, void print_verilog_module_definition(std::fstream& fp, const std::string& module_name); +void print_verilog_module_ports(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id); + +void print_verilog_module_declaration(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id); + void print_verilog_module_end(std::fstream& fp, const std::string& module_name); From fcb31e4c24a8f06283e7de00863e73d59a9e0ed2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 18:41:16 -0600 Subject: [PATCH 127/482] add stats for verilog modules --- vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp | 5 +++++ vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h | 1 + vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index a6007be3d..6ec50b62b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -15,6 +15,11 @@ /****************************************************************************** * Public Accessors ******************************************************************************/ +/* Return number of modules */ +size_t ModuleManager::num_modules() const { + return ids_.size(); +} + /* Find the name of a module */ std::string ModuleManager::module_name(const ModuleId& module_id) const { /* Validate the module_id */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 2df7b2cf2..a73204daf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -33,6 +33,7 @@ class ModuleManager { }; public: /* Public Constructors */ public: /* Public accessors */ + size_t num_modules() const; std::string module_name(const ModuleId& module_id) const; std::string module_port_type_str(const enum e_module_port_type& port_type) const; std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 6a7dc7029..abbae27ac 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -420,6 +420,8 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, chomped_circuit_name, *(Arch.spice) ); + vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules()); + /* End time count */ t_end = clock(); From 39853408dd592d47cbd572c361d071de9c1f0f15 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 16:36:30 -0600 Subject: [PATCH 128/482] add recursive global port searching for circuit library --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 131 +++++++++++++++++- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 13 +- .../fpga_x2p/base/module_manager_utils.cpp | 3 +- .../verilog/verilog_essential_gates.cpp | 6 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 2 +- 5 files changed, 142 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index f5b2ba6af..a423e5409 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -372,12 +372,14 @@ std::vector CircuitLibrary::model_ports(const CircuitModelId& mod } /* Recursively find all the global ports in the circuit model / sub circuit_model */ -std::vector CircuitLibrary::model_global_ports(const CircuitModelId& model_id) const { +std::vector CircuitLibrary::model_global_ports(const CircuitModelId& model_id, + const bool& recursive) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); - /* Search all the ports */ std::vector global_ports; + + /* Search all the ports */ for (auto port : model_ports(model_id)) { /* By pass non-global ports*/ if (false == port_is_global(port)) { @@ -387,12 +389,39 @@ std::vector CircuitLibrary::model_global_ports(const CircuitModel global_ports.push_back(port); } + /* Finish, if we do not need to go recursively */ + if (false == recursive) { + return global_ports; + } + + /* If go recursively, we search all the buffer/pass-gate circuit model ids */ + /* Go search every sub circuit model included the current circuit model */ + for (const auto& sub_model : sub_models_[model_id]) { + std::vector sub_global_ports = model_global_ports(sub_model, recursive); + for (const auto& sub_global_port : sub_global_ports) { + /* Add to global_ports, if it is not already found in the list */ + bool add_to_list = true; + for (const auto& global_port : global_ports) { + if (0 == port_prefix(sub_global_port).compare(port_prefix(global_port))) { + /* Same name, skip list update */ + add_to_list = false; + break; + } + } + if (true == add_to_list) { + /* Add the sub_global_port to the list */ + global_ports.push_back(sub_global_port); + } + } + } + return global_ports; } /* Recursively find all the global ports in the circuit model / sub circuit_model */ std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type) const { + const enum e_spice_model_port_type& type, + const bool& recursive) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -411,6 +440,32 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ global_ports.push_back(port); } + /* Finish, if we do not need to go recursively */ + if (false == recursive) { + return global_ports; + } + + /* If go recursively, we search all the buffer/pass-gate circuit model ids */ + /* Go search every sub circuit model included the current circuit model */ + for (const auto& sub_model : sub_models_[model_id]) { + std::vector sub_global_ports = model_global_ports_by_type(sub_model, type, recursive); + for (const auto& sub_global_port : sub_global_ports) { + /* Add to global_ports, if it is not already found in the list */ + bool add_to_list = true; + for (const auto& global_port : global_ports) { + if (0 == port_prefix(sub_global_port).compare(port_prefix(global_port))) { + /* Same name, skip list update */ + add_to_list = false; + break; + } + } + if (true == add_to_list) { + /* Add the sub_global_port to the list */ + global_ports.push_back(sub_global_port); + } + } + } + return global_ports; } @@ -741,6 +796,7 @@ CircuitModelId CircuitLibrary::add_model(const enum e_spice_model_type& type) { model_verilog_netlists_.emplace_back(); model_spice_netlists_.emplace_back(); model_is_default_.push_back(false); + sub_models_.emplace_back(); /* Verilog generator options */ dump_structural_verilog_.push_back(false); @@ -1569,7 +1625,70 @@ void CircuitLibrary::link_pass_gate_logic_model(const CircuitModelId& model_id) } pass_gate_logic_model_ids_[model_id] = model(pass_gate_logic_model_names_[model_id]); return; -} +} + +/* Find if a model is already in the submodel list */ +bool CircuitLibrary::is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + VTR_ASSERT(valid_model_id(submodel_id)); + + std::vector::iterator it = std::find(sub_models_[model_id].begin(), sub_models_[model_id].end(), submodel_id); + if (it == sub_models_[model_id].end()) { + return true; + } + return false; +} + +/* Build the sub module list for each circuit model, + * Find the linked circuit model id in + * pass-gate, buffers, ports */ +void CircuitLibrary::build_submodels() { + for (const auto& model: models()) { + /* Make sure a clean start */ + sub_models_[model].clear(); + + /* build a list of candidates */ + std::vector candidates; + + /* Find buffer models */ + for (const auto& buffer_model : buffer_model_ids_[model]) { + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() == buffer_model) { + continue; + } + candidates.push_back(buffer_model); + } + + /* Find pass-gate models */ + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() != pass_gate_logic_model_ids_[model]) { + candidates.push_back(pass_gate_logic_model_ids_[model]); + } + + /* Find each port circuit models */ + for (const auto& port: model_ports(model)) { + /* Find tri-state circuit models */ + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() != port_tri_state_model_ids_[port]) { + candidates.push_back(port_tri_state_model_ids_[port]); + } + /* Find inv circuit models */ + /* Skip any invalid ids */ + if (CircuitModelId::INVALID() != port_inv_model_ids_[port]) { + candidates.push_back(port_inv_model_ids_[port]); + } + } + + /* Build a unique list */ + for (const auto& cand : candidates) { + /* Make sure the model id is unique in the list */ + if (true == is_unique_submodel(model,cand)) { + sub_models_[model].push_back(cand); + } + } + } +} /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { @@ -1612,6 +1731,10 @@ void CircuitLibrary::build_model_links() { /* Build links for ports */ link_port_tri_state_model(); link_port_inv_model(); + + /* Build submodels */ + build_submodels(); + return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index cab53bec6..a638ea8d1 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -74,6 +74,8 @@ * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated * 7. is_default_: indicate if the circuit model is the default one among all those in the same type + * 8. sub_models_: the sub circuit models included by a circuit model. It is a collection of unique circuit model ids + * found in the CircuitModelId of pass-gate/buffers/port-related circuit models. * * ------ Fast look-ups----- * 1. model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users @@ -243,9 +245,10 @@ class CircuitLibrary { size_t num_model_ports(const CircuitModelId& model_id) const; size_t num_model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_ports(const CircuitModelId& model_id) const; - std::vector model_global_ports(const CircuitModelId& model_id) const; + std::vector model_global_ports(const CircuitModelId& model_id, const bool& recursive) const; std::vector model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type) const; + const enum e_spice_model_port_type& type, + const bool& recursive) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_input_ports(const CircuitModelId& model_id) const; @@ -426,6 +429,8 @@ class CircuitLibrary { void link_port_inv_model(); void link_buffer_model(const CircuitModelId& model_id); void link_pass_gate_logic_model(const CircuitModelId& model_id); + bool is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id); + void build_submodels(); void build_model_timing_graph(const CircuitModelId& model_id); public: /* Public Mutators: builders */ void build_model_links(); @@ -466,6 +471,9 @@ class CircuitLibrary { vtr::vector model_spice_netlists_; vtr::vector model_is_default_; + /* Submodules that a circuit model contains */ + vtr::vector> sub_models_; + /* fast look-up for circuit models to categorize by types * [type][num_ids] * Important: we force the default circuit model in the first element for each type @@ -566,7 +574,6 @@ class CircuitLibrary { vtr::vector wire_types_; vtr::vector> wire_rc_; /* x => wire_res_val, y=> wire_cap_val */ vtr::vector wire_num_levels_; - }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index f375c446c..85502cc48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -20,7 +20,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Add ports */ /* Find global ports and add one by one */ - for (const auto& port : circuit_lib.model_global_ports(circuit_model)) { + for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) { BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); } @@ -48,5 +48,4 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Return the new id */ return module; - } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index a5378fcd9..41d2fb560 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -145,7 +145,7 @@ void print_verilog_invbuf_module(std::fstream& fp, /* Find the input port, output port and global inputs*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Make sure: * There is only 1 input port and 1 output port, @@ -248,7 +248,7 @@ void print_verilog_passgate_module(std::fstream& fp, /* Find the input port, output port*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); switch (circuit_lib.pass_gate_logic_type(circuit_model)) { case SPICE_MODEL_PASS_GATE_TRANSMISSION: @@ -483,7 +483,7 @@ void print_verilog_gate_module(std::fstream& fp, /* Find the input port, output port*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Make sure: * There is only 1 output port, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 9255097c9..dce86830a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -47,7 +47,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, /* Get model ports of tgate */ std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT); + std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); VTR_ASSERT(3 == tgate_input_ports.size()); VTR_ASSERT(1 == tgate_output_ports.size()); From ad06e9c98c011eb93e08d2c52583249d7a9fe0b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 17:39:29 -0600 Subject: [PATCH 129/482] plug in module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 33 +++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 4 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 7 +- .../verilog/verilog_essential_gates.cpp | 117 ++++-------------- .../verilog/verilog_essential_gates.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 6 +- .../SRC/fpga_x2p/verilog/verilog_submodules.h | 6 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 47 ++++++- .../fpga_x2p/verilog/verilog_writer_utils.h | 7 ++ 9 files changed, 134 insertions(+), 96 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 2affed6a4..a6007be3d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -12,6 +12,39 @@ * Public Constructors ******************************************************************************/ +/****************************************************************************** + * Public Accessors + ******************************************************************************/ +/* Find the name of a module */ +std::string ModuleManager::module_name(const ModuleId& module_id) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module_id)); + return names_[module_id]; +} + +/* Get the string of a module port type */ +std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const { + std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; + return MODULE_PORT_TYPE_STRING[port_type]; +} + +/* Find a list of ports of a module by a given types */ +std::vector ModuleManager::module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module_id)); + + std::vector ports; + for (const auto& port : port_ids_[module_id]) { + /* Skip unmatched ports */ + if (port_type != port_types_[module_id][port]) { + continue; + } + ports.push_back(ports_[module_id][port]); + } + + return ports; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 553974a7c..2df7b2cf2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -32,6 +32,10 @@ class ModuleManager { NUM_MODULE_PORT_TYPES }; public: /* Public Constructors */ + public: /* Public accessors */ + std::string module_name(const ModuleId& module_id) const; + std::string module_port_type_str(const enum e_module_port_type& port_type) const; + std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a0a3e773c..6a7dc7029 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -32,6 +32,8 @@ #include "fpga_x2p_globals.h" #include "fpga_bitstream.h" +#include "module_manager.h" + /* Include SynVerilog headers */ #include "verilog_global.h" #include "verilog_utils.h" @@ -148,6 +150,9 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, t_sram_orgz_info* sram_verilog_orgz_info = NULL; + /* Module manager for the Verilog modules created */ + ModuleManager module_manager; + /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n"); @@ -269,7 +274,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ - dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path, + dump_verilog_submodules(module_manager, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, Arch, &vpr_setup.RoutingArch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 41d2fb560..8aba48226 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -13,6 +13,8 @@ /* FPGA-X2P context header files */ #include "fpga_x2p_utils.h" +#include "module_manager.h" +#include "module_manager_utils.h" /* FPGA-Verilog context header files */ #include "verilog_global.h" @@ -136,7 +138,8 @@ void print_verilog_invbuf_body(std::fstream& fp, * or tapered buffer to a file ***********************************************/ static -void print_verilog_invbuf_module(std::fstream& fp, +void print_verilog_invbuf_module(ModuleManager& module_manager, + std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Ensure a valid file handler*/ @@ -178,30 +181,11 @@ void print_verilog_invbuf_module(std::fstream& fp, } } - /* dump module body */ - print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - /* TODO: print global ports, this should be handled by ModuleManager */ - for (const auto& port : global_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - /* Dump ports */ - BasicPort input_port; - /* Configure each input port */ - input_port.set_name(circuit_lib.port_lib_name(input_ports[0])); - input_port.set_width(circuit_lib.port_size(input_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl; - - BasicPort output_port; - /* Configure each input port */ - output_port.set_name(circuit_lib.port_lib_name(output_ports[0])); - output_port.set_width(circuit_lib.port_size(output_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << std::endl; - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); /* Finish dumping ports */ /* Assign logics : depending on topology */ @@ -239,7 +223,8 @@ void print_verilog_invbuf_module(std::fstream& fp, * either transmission-gate or pass-transistor ***********************************************/ static -void print_verilog_passgate_module(std::fstream& fp, +void print_verilog_passgate_module(ModuleManager& module_manager, + std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Ensure a valid file handler*/ @@ -284,37 +269,12 @@ void print_verilog_passgate_module(std::fstream& fp, */ VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - /* Print Verilog module */ - print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - /* TODO: print global ports, this should be handled by ModuleManager */ - for (const auto& port : global_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - for (const auto& input_port : input_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - /* Configure each global port */ - for (const auto& output_port : output_ports) { - BasicPort basic_port(circuit_lib.port_lib_name(output_port), circuit_lib.port_size(output_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, basic_port); - /* Last port does not need a comma */ - if (output_port != output_ports.back()) { - fp << "," << std::endl; - } else { - fp << std::endl; - } - } - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ /* Dump logics: we propagate input to the output when the gate is '1' * the input is blocked from output when the gate is '0' @@ -474,7 +434,8 @@ void print_verilog_mux2_gate_body(std::fstream& fp, * 3. 2-input MUX ***********************************************/ static -void print_verilog_gate_module(std::fstream& fp, +void print_verilog_gate_module(ModuleManager& module_manager, + std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { /* Ensure a valid file handler*/ @@ -491,37 +452,12 @@ void print_verilog_gate_module(std::fstream& fp, */ VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - /* Print Verilog module */ - print_verilog_module_definition(fp, circuit_lib.model_name(circuit_model)); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - /* TODO: print global ports, this should be handled by ModuleManager */ - for (const auto& port : global_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - for (const auto& input_port : input_ports) { - /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; - } - - /* Configure each global port */ - for (const auto& output_port : output_ports) { - BasicPort basic_port(circuit_lib.port_lib_name(output_port), circuit_lib.port_size(output_port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, basic_port); - /* Last port does not need a comma */ - if (output_port != output_ports.back()) { - fp << "," << std::endl; - } else { - fp << std::endl; - } - } - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ /* Dump logics */ switch (circuit_lib.gate_type(circuit_model)) { @@ -554,7 +490,8 @@ void print_verilog_gate_module(std::fstream& fp, * include inverters, buffers, transmission-gates, * etc. ***********************************************/ -void print_verilog_submodule_essentials(const std::string& verilog_dir, +void print_verilog_submodule_essentials(ModuleManager& module_manager, + const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ @@ -582,15 +519,15 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, continue; } if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { - print_verilog_invbuf_module(fp, circuit_lib, circuit_model); + print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model); continue; } if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { - print_verilog_passgate_module(fp, circuit_lib, circuit_model); + print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model); continue; } if (SPICE_MODEL_GATE == circuit_lib.model_type(circuit_model)) { - print_verilog_gate_module(fp, circuit_lib, circuit_model); + print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model); continue; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h index fa9b13660..bbdd60b69 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h @@ -12,7 +12,8 @@ #include #include "circuit_library.h" -void print_verilog_submodule_essentials(const std::string& verilog_dir, +void print_verilog_submodule_essentials(ModuleManager& module_manager, + const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index cb8ca95ef..230306d3c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3506,7 +3506,8 @@ void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, /* Dump verilog files of submodules to be used in FPGA components : * 1. MUXes */ -void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, +void dump_verilog_submodules(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, t_arch Arch, @@ -3515,7 +3516,8 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); - print_verilog_submodule_essentials(std::string(verilog_dir), + print_verilog_submodule_essentials(module_manager, + std::string(verilog_dir), std::string(submodule_dir), Arch.spice->circuit_lib); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h index a7a384501..1e6aa814b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h @@ -1,6 +1,10 @@ #ifndef VERILOG_SUBMODULES_H #define VERILOG_SUBMODULES_H -void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, + +#include "module_manager.h" + +void dump_verilog_submodules(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, t_arch Arch, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 554579768..81c9bed5f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -82,7 +82,52 @@ void print_verilog_module_definition(std::fstream& fp, } /************************************************ - * Print a Verilog module definition + * Print a Verilog module ports based on the module id + ***********************************************/ +void print_verilog_module_ports(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id) { + check_file_handler(fp); + + /* port type2type mapping */ + std::map port_type2type_map; + port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT; + port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT; + port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_INPUT; + + /* Port sequence: global, inout, input, output and clock ports, */ + size_t port_cnt = 0; + for (const auto& kv : port_type2type_map) { + for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { + if (0 != port_cnt) { + /* Do not dump a comma for the first port */ + fp << ", //----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + } + /* Print port */ + fp << "\t" << generate_verilog_port(kv.second, port) << std::endl; + port_cnt++; + } + } +} + +/************************************************ + * Print a Verilog module declaration (definition + port list + ***********************************************/ +void print_verilog_module_declaration(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id) { + check_file_handler(fp); + + print_verilog_module_definition(fp, module_manager.module_name(module_id)); + + print_verilog_module_ports(fp, module_manager, module_id); + + fp << std::endl << ");" << std::endl; +} + + +/************************************************ + * Print an end line for a Verilog module ***********************************************/ void print_verilog_module_end(std::fstream& fp, const std::string& module_name) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 2f3d73bba..3f65fb726 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -8,6 +8,7 @@ #include #include "device_port.h" +#include "module_manager.h" void print_verilog_file_header(std::fstream& fp, const std::string& usage); @@ -21,6 +22,12 @@ void print_verilog_comment(std::fstream& fp, void print_verilog_module_definition(std::fstream& fp, const std::string& module_name); +void print_verilog_module_ports(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id); + +void print_verilog_module_declaration(std::fstream& fp, + const ModuleManager& module_manager, const ModuleId& module_id); + void print_verilog_module_end(std::fstream& fp, const std::string& module_name); From 27b619554df98c3ced294e6be95e28a1b5a53361 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 18:41:16 -0600 Subject: [PATCH 130/482] add stats for verilog modules --- vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp | 5 +++++ vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h | 1 + vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index a6007be3d..6ec50b62b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -15,6 +15,11 @@ /****************************************************************************** * Public Accessors ******************************************************************************/ +/* Return number of modules */ +size_t ModuleManager::num_modules() const { + return ids_.size(); +} + /* Find the name of a module */ std::string ModuleManager::module_name(const ModuleId& module_id) const { /* Validate the module_id */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 2df7b2cf2..a73204daf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -33,6 +33,7 @@ class ModuleManager { }; public: /* Public Constructors */ public: /* Public accessors */ + size_t num_modules() const; std::string module_name(const ModuleId& module_id) const; std::string module_port_type_str(const enum e_module_port_type& port_type) const; std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 6a7dc7029..abbae27ac 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -420,6 +420,8 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, chomped_circuit_name, *(Arch.spice) ); + vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules()); + /* End time count */ t_end = clock(); From 63f40f48fa26d4fe110d45e3d13c67e10fc37049 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 24 Aug 2019 19:23:33 -0600 Subject: [PATCH 131/482] develop and plug mux_lib_builder, refactoring the mux submodule generation --- vpr7_x2p/vpr/SRC/device/mux_library.cpp | 10 + vpr7_x2p/vpr/SRC/device/mux_library.h | 2 + .../vpr/SRC/device/mux_library_builder.cpp | 186 ++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_library_builder.h | 14 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 4 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 9 +- .../verilog/verilog_essential_gates.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 125 +++++++++--- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.h | 12 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 48 +---- .../SRC/fpga_x2p/verilog/verilog_submodules.h | 2 + .../fpga_x2p/verilog/verilog_writer_utils.cpp | 9 +- 13 files changed, 343 insertions(+), 81 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library_builder.h diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.cpp b/vpr7_x2p/vpr/SRC/device/mux_library.cpp index 04ef5c378..ee51b087b 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_library.cpp @@ -43,6 +43,16 @@ CircuitModelId MuxLibrary::mux_circuit_model(const MuxId& mux_id) const { return mux_circuit_models_[mux_id]; } +/* Find the maximum mux size among the mux graphs */ +size_t MuxLibrary::max_mux_size() const { + /* Iterate over all the mux graphs and find their sizes */ + size_t max_mux_size = 0; + for (const auto& mux : mux_ids_) { + max_mux_size = std::max(max_mux_size, mux_graphs_[mux].num_inputs()); + } + return max_mux_size; +} + /************************************************** * Private mutators: *************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h index 7ffefba09..8f4ec71d8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.h +++ b/vpr7_x2p/vpr/SRC/device/mux_library.h @@ -27,6 +27,8 @@ class MuxLibrary { const MuxGraph& mux_graph(const MuxId& mux_id) const; /* Get a mux circuit model id */ CircuitModelId mux_circuit_model(const MuxId& mux_id) const; + /* Find the maximum mux size */ + size_t max_mux_size() const; public: /* Public mutators */ /* Add a mux to the library */ void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp b/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp new file mode 100644 index 000000000..9dc462572 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp @@ -0,0 +1,186 @@ +/******************************************************************** + * This file includes the functions of builders for MuxLibrary. + *******************************************************************/ +#include +#include +#include "vtr_assert.h" + +/* Device-level header files */ +#include "util.h" +#include "vpr_types.h" +#include "globals.h" + +/* FPGA-X2P context header files */ +#include "fpga_x2p_utils.h" + +#include "spice_types.h" +#include "circuit_library.h" +#include "mux_library.h" +#include "mux_library_builder.h" + +/******************************************************************** + * Update MuxLibrary with the unique multiplexer structures + * found in the global routing architecture + *******************************************************************/ +static +void build_routing_arch_mux_library(MuxLibrary& mux_lib, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_switch_inf* switches, + const CircuitLibrary& circuit_lib, + t_det_routing_arch* routing_arch) { + /* Current Version: Support Uni-directional routing architecture only*/ + if (UNI_DIRECTIONAL != routing_arch->directionality) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d]) FPGA X2P Only supports uni-directional routing architecture.\n", + __FILE__, __LINE__); + exit(1); + } + + /* The routing path is. + * OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN + * Each edge is a switch, for IPIN, the switch is a connection block, + * for the rest is a switch box + */ + /* Count the sizes of muliplexers in routing architecture */ + for (int inode = 0; inode < LL_num_rr_nodes; inode++) { + t_rr_node& node = LL_rr_node[inode]; + switch (node.type) { + case IPIN: { + /* Have to consider the fan_in only, it is a connection block (multiplexer)*/ + VTR_ASSERT((node.fan_in > 0) || (0 == node.fan_in)); + if ( (0 == node.fan_in) || (1 == node.fan_in)) { + break; + } + /* Find the circuit_model for multiplexers in connection blocks */ + const CircuitModelId& cb_switch_circuit_model = switches[node.driver_switch].circuit_model; + /* we should select a circuit model for the connection box*/ + VTR_ASSERT(CircuitModelId::INVALID() != cb_switch_circuit_model); + /* Add the mux to mux_library */ + mux_lib.add_mux(circuit_lib, cb_switch_circuit_model, node.fan_in); + break; + } + case CHANX: + case CHANY: { + /* Channels are the same, have to consider the fan_in as well, + * it could be a switch box if previous rr_node is a channel + * or it could be a connection box if previous rr_node is a IPIN or OPIN + */ + VTR_ASSERT((node.fan_in > 0) || (0 == node.fan_in)); + if ((0 == node.fan_in) || (1 == node.fan_in)) { + break; + } + /* Find the spice_model for multiplexers in switch blocks*/ + const CircuitModelId& sb_switch_circuit_model = switches[node.driver_switch].circuit_model; + /* we should select a circuit model for the Switch box*/ + VTR_ASSERT(CircuitModelId::INVALID() != sb_switch_circuit_model); + /* Add the mux to mux_library */ + mux_lib.add_mux(circuit_lib, sb_switch_circuit_model, node.fan_in); + break; + } + default: + /* We do not care other types of rr_node */ + break; + } + } +} + +/******************************************************************** + * Update MuxLibrary with the unique multiplexer structures + * found in programmable logic blocks + ********************************************************************/ +static +void build_pb_type_mux_library_rec(MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_pb_type* cur_pb_type) { + VTR_ASSERT(nullptr != cur_pb_type); + + /* If there is spice_model_name, this is a leaf node!*/ + if (TRUE == is_primitive_pb_type(cur_pb_type)) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins circuit modeling + */ + VTR_ASSERT(CircuitModelId::INVALID() != cur_pb_type->phy_pb_type->circuit_model); + return; + } + + /* Traversal the hierarchy, find all the multiplexer from the interconnection part */ + for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Then we have to statisitic the interconnections*/ + for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + /* Check the num_mux and fan_in of an interconnection */ + VTR_ASSERT ((0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) + || (0 < cur_pb_type->modes[imode].interconnect[jinterc].num_mux)); + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + continue; + } + CircuitModelId& interc_circuit_model = cur_pb_type->modes[imode].interconnect[jinterc].circuit_model; + VTR_ASSERT(CircuitModelId::INVALID() != interc_circuit_model); + /* Add the mux model to library */ + mux_lib.add_mux(circuit_lib, interc_circuit_model, cur_pb_type->modes[imode].interconnect[jinterc].fan_in); + } + } + + /* Go recursively to the lower level */ + for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { + for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { + build_pb_type_mux_library_rec(mux_lib, circuit_lib, + &cur_pb_type->modes[imode].pb_type_children[ichild]); + } + } +} + +/******************************************************************** + * Update MuxLibrary with the unique multiplexers required by + * LUTs in the circuit library + ********************************************************************/ +static +void build_lut_mux_library(MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib) { + /* Find all the circuit models which are LUTs in the circuit library */ + for (const auto& circuit_model : circuit_lib.models()) { + /* Bypass non-LUT circuit models */ + if (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) { + continue; + } + /* Find the MUX size required by the LUT */ + /* Get input ports which are not global ports! */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == input_ports.size()); + /* MUX size = 2^lut_size */ + size_t lut_mux_size = (size_t)pow(2., (double)(circuit_lib.port_size(input_ports[0]))); + /* Add mux to the mux library */ + mux_lib.add_mux(circuit_lib, circuit_model, lut_mux_size); + } +} + +/* Statistic for all the multiplexers in FPGA + * We determine the sizes and its structure (according to spice_model) for each type of multiplexers + * We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks + * In additional to multiplexers, this function also consider crossbars. + * All the statistics are stored in a linked list, as a return value + */ +MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_switch_inf* switches, + const CircuitLibrary& circuit_lib, + t_det_routing_arch* routing_arch) { + /* MuxLibrary to store the information of Multiplexers*/ + MuxLibrary mux_lib; + + /* Step 1: We should check the multiplexer spice models defined in routing architecture.*/ + build_routing_arch_mux_library(mux_lib, LL_num_rr_nodes, LL_rr_node, switches, circuit_lib, routing_arch); + + /* Step 2: Count the sizes of multiplexers in complex logic blocks */ + for (int itype = 0; itype < num_types; itype++) { + if (NULL != type_descriptors[itype].pb_type) { + build_pb_type_mux_library_rec(mux_lib, circuit_lib, type_descriptors[itype].pb_type); + } + } + + /* Step 3: count the size of multiplexer that will be used in LUTs*/ + build_lut_mux_library(mux_lib, circuit_lib); + + return mux_lib; +} + + + diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.h b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h new file mode 100644 index 000000000..8a0965dd4 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h @@ -0,0 +1,14 @@ +/******************************************************************** + * This file includes the function declaration of builders + * for MuxLibrary. + * See details in mux_library_builder.cpp + *******************************************************************/ +#ifndef MUX_LIBRARY_BUILDER_H +#define MUX_LIBRARY_BUILDER_H + +MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_switch_inf* switches, + const CircuitLibrary& circuit_lib, + t_det_routing_arch* routing_arch); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 0881d5221..769a49dad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -29,6 +29,7 @@ std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, + const size_t& branch_mux_size, const std::string& postfix) { /* If the tgate spice model of this MUX is a MUX2 standard cell, * the mux_subckt name will be the name of the standard cell @@ -38,6 +39,7 @@ std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circui VTR_ASSERT (SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(subckt_model)); return circuit_lib.model_name(subckt_model); } + std::string branch_postfix = postfix + "_size" + std::to_string(branch_mux_size); - return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, postfix); + return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index ff91f4854..bd67c61f4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -19,6 +19,7 @@ std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, + const size_t& branch_mux_size, const std::string& posfix); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index abbae27ac..989f580f7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -33,6 +33,8 @@ #include "fpga_bitstream.h" #include "module_manager.h" +#include "mux_library.h" +#include "mux_library_builder.h" /* Include SynVerilog headers */ #include "verilog_global.h" @@ -153,6 +155,11 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Module manager for the Verilog modules created */ ModuleManager module_manager; + /* Build Multiplexer library */ + MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); + + /* 0. basic units: inverter, buffers and pass-gate logics, */ + /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n"); @@ -274,7 +281,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ - dump_verilog_submodules(module_manager, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, + dump_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, Arch, &vpr_setup.RoutingArch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 8aba48226..a94828c5e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -507,7 +507,7 @@ void print_verilog_submodule_essentials(ModuleManager& module_manager, /* Create file */ vpr_printf(TIO_MESSAGE_INFO, "Generating Verilog netlist (%s) for essential gates...\n", - __FILE__, __LINE__, essentials_verilog_file_name); + __FILE__, __LINE__, verilog_fname.c_str()); print_verilog_file_header(fp, "Essential gates"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index dce86830a..f8e64cd70 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -12,6 +12,7 @@ /* Device-level header files */ #include "mux_graph.h" +#include "module_manager.h" #include "physical_types.h" #include "vpr_types.h" @@ -30,8 +31,9 @@ * for a multiplexer with the given size **********************************************/ static -void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, +void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + std::fstream& fp, const CircuitModelId& circuit_model, const std::string& module_name, const MuxGraph& mux_graph) { @@ -44,7 +46,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, return; } - /* Get model ports of tgate */ + /* TODO: move to check_circuit_library? Get model ports of tgate */ std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); @@ -68,36 +70,30 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, /* MUX graph must have only 1 level*/ VTR_ASSERT(1 == mux_graph.num_levels()); - /* Print Verilog module */ - print_verilog_module_definition(fp, module_name); - - /* Create port information */ - /* Configure each input port */ - BasicPort input_port("in", num_inputs); - - /* Configure each output port */ - BasicPort output_port("out", num_outputs); - - /* Configure each memory port */ - BasicPort mem_port("mem", num_mems); - BasicPort mem_inv_port("mem_inv", num_mems); - - /* TODO: Generate global ports */ + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ for (const auto& port : tgate_global_ports) { /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } + /* Add each input port */ + BasicPort input_port("in", num_inputs); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort output_port("out", num_outputs); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add each memory port */ + BasicPort mem_port("mem", num_mems); + module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port("mem_inv", num_mems); + module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - /* TODO: add a module to the Module Manager */ - - /* Port list */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << "," << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_port) << "," << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_inv_port) << std::endl; - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); /* Verilog Behavior description for a MUX */ print_verilog_comment(fp, std::string("---- Structure-level description -----")); @@ -177,18 +173,20 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, * Generate Verilog codes modeling an branch circuit * for a multiplexer with the given size **********************************************/ -void generate_verilog_mux_branch_module(std::fstream& fp, +static +void generate_verilog_mux_branch_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + std::fstream& fp, const CircuitModelId& circuit_model, const size_t& mux_size, const MuxGraph& mux_graph) { - std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, verilog_mux_basis_posfix); + std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { case SPICE_MODEL_DESIGN_CMOS: if (true == circuit_lib.dump_structural_verilog(circuit_model)) { - generate_verilog_cmos_mux_branch_module_structural(fp, circuit_lib, circuit_model, module_name, mux_graph); + generate_verilog_cmos_mux_branch_module_structural(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); } else { /* dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name, @@ -222,3 +220,68 @@ void generate_verilog_mux_branch_module(std::fstream& fp, return; } + +/*********************************************** + * Generate Verilog modules for all the unique + * multiplexers in the FPGA device + **********************************************/ +void print_verilog_submodule_muxes(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* submodule_dir) { + + /* TODO: Generate modules into a .bak file now. Rename after it is verified */ + std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name)); + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for Multiplexers (%s) ...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Multiplexers"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Generate basis sub-circuit for unique branches shared by the multiplexers */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* Create a mux graph for the branch circuit */ + std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); + /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ + for (auto branch_mux_graph : branch_mux_graphs) { + generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, + mux_graph.num_inputs(), branch_mux_graph); + } + } + + /* Dump MUX graph one by one */ + + /* Close the file steam */ + fp.close(); + + /* TODO: + * Scan-chain configuration circuit does not need any BLs/WLs! + * SRAM MUX does not need any reserved BL/WLs! + */ + /* Determine reserved Bit/Word Lines if a memory bank is specified, + * At least 1 BL/WL should be reserved! + */ + try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, + mux_lib.max_mux_size(), mux_lib.max_mux_size()); + + /* TODO: Add fname to the linked list when debugging is finished */ + /* + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); + */ +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index c7dfd4bf8..8b30d6820 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -11,11 +11,13 @@ #include "circuit_library.h" #include "mux_graph.h" #include "mux_library.h" +#include "module_manager.h" -void generate_verilog_mux_branch_module(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const MuxGraph& mux_graph); +void print_verilog_submodule_muxes(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* submodule_dir); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 230306d3c..7bd065cbe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -29,6 +29,7 @@ #include "fpga_x2p_globals.h" #include "fpga_x2p_mux_utils.h" #include "fpga_x2p_bitstream_utils.h" +#include "mux_library.h" /* Include verilog utils */ #include "verilog_global.h" @@ -2228,11 +2229,13 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Alloc the muxes*/ muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); - + /* Print the muxes netlist*/ fp = fopen(verilog_name, "w"); if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, verilog_name); + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s", + __FILE__, __LINE__, verilog_name); exit(1); } /* Generate the descriptions*/ @@ -2292,41 +2295,6 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, temp = temp->next; } - /* Generate modules into a .bak file now. Rename after it is verified */ - std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name)); - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream sfp; - sfp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for Multiplexers (%s) ...\n", - verilog_fname.c_str()); - check_file_handler(sfp); - - /* TODO: this conversion is temporary. Will be removed after code reconstruction */ - MuxLibrary mux_lib = convert_mux_arch_to_library(spice->circuit_lib, muxes_head); - - /* Generate basis sub-circuit for unique branches shared by the multiplexers */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* Create a mux graph for the branch circuit */ - std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); - /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ - for (auto branch_mux_graph : branch_mux_graphs) { - generate_verilog_mux_branch_module(sfp, spice->circuit_lib, mux_circuit_model, - mux_graph.num_inputs(), branch_mux_graph); - } - } - - /* Dump MUX graph one by one */ - - /* Close the file steam */ - sfp.close(); - /* TODO: * Scan-chain configuration circuit does not need any BLs/WLs! * SRAM MUX does not need any reserved BL/WLs! @@ -3507,6 +3475,7 @@ void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, * 1. MUXes */ void dump_verilog_submodules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, @@ -3514,7 +3483,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, t_det_routing_arch* routing_arch, t_syn_verilog_opts fpga_verilog_opts) { - /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); print_verilog_submodule_essentials(module_manager, std::string(verilog_dir), @@ -3525,6 +3493,10 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + + print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, + verilog_dir, submodule_dir); + vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h index 1e6aa814b..3d6a30e99 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h @@ -2,8 +2,10 @@ #define VERILOG_SUBMODULES_H #include "module_manager.h" +#include "mux_library.h" void dump_verilog_submodules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 81c9bed5f..f58ee587e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -55,7 +55,7 @@ void print_verilog_include_defines_preproc_file(std::fstream& fp, fp << "//------ Include defines: preproc flags -----" << std::endl; fp << "`include \"" << include_file_path << "\"" << std::endl; - fp << "//------ End Include defines: preproc flags -----" << std::endl; + fp << "//------ End Include defines: preproc flags -----" << std::endl << std::endl; return; } @@ -102,10 +102,11 @@ void print_verilog_module_ports(std::fstream& fp, for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { if (0 != port_cnt) { /* Do not dump a comma for the first port */ - fp << ", //----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + fp << "," << std::endl; } /* Print port */ - fp << "\t" << generate_verilog_port(kv.second, port) << std::endl; + fp << "\t//----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + fp << "\t" << generate_verilog_port(kv.second, port); port_cnt++; } } @@ -119,7 +120,7 @@ void print_verilog_module_declaration(std::fstream& fp, check_file_handler(fp); print_verilog_module_definition(fp, module_manager.module_name(module_id)); - + print_verilog_module_ports(fp, module_manager, module_id); fp << std::endl << ");" << std::endl; From f558437ae19e2fba4ea3426e52b2ddf1884d85a8 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 25 Aug 2019 00:23:39 -0600 Subject: [PATCH 132/482] Added task for vpr_blif flow --- .../misc/fpgaflow_default_tool_path.conf | 2 +- openfpga_flow/scripts/run_fpga_flow.py | 13 ++ openfpga_flow/scripts/run_fpga_task.py | 146 +++++++++++++----- .../tasks/basic_flow/config/task.conf | 15 +- .../tasks/blif_vpr_flow/config/task.conf | 60 +++++++ 5 files changed, 190 insertions(+), 46 deletions(-) create mode 100644 openfpga_flow/tasks/blif_vpr_flow/config/task.conf diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index d41183ac8..88d4504ab 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -28,7 +28,7 @@ placement_time = "Placement took ([0-9.]+) seconds", str routing_time = "Routing took ([0-9.]+) seconds", str average_net_length = "average net length: ([0-9.]+)", str critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific -total_time_taken = "Routing took ([0-9.]+) seconds", float +total_routing_time = "Routing took ([0-9.]+) seconds", float [DEFAULT_PARSE_RESULT_POWER] pb_type_power="PB Types\s+([0-9]+)", str diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 4ea9fbf8b..69bbe1063 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -535,10 +535,23 @@ def run_pro_blif_3arg(): def collect_files_for_vpr(): + # Sanitize provided Benchmark option if len(args.benchmark_files) > 1: logger.error("Expecting Single Benchmark BLif file.") + if not os.path.isfile(args.benchmark_files[0] or ""): + clean_up_and_exit("Provided Blif file not found") shutil.copy(args.benchmark_files[0], args.top_module+".blif") + + # Sanitize provided Activity file option + if not os.path.isfile(args.activity_file or ""): + logger.error("Activity File - %s" % args.activity_file) + clean_up_and_exit("Provided activity file not found") shutil.copy(args.activity_file, args.top_module+"_ace_out.act") + + # Sanitize provided Benchmark option + if not os.path.isfile(args.base_verilog or ""): + logger.error("Base Verilog File - %s" % args.base_verilog) + clean_up_and_exit("Provided base_verilog file not found") shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v") diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index eb18c6cda..62f1de6cc 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -12,9 +12,9 @@ import subprocess import threading import csv from string import Template -import run_fpga_flow import pprint from importlib import util +from collections import OrderedDict if util.find_spec("humanize"): import humanize @@ -23,7 +23,7 @@ if util.find_spec("humanize"): # Configure logging system # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = logging.basicConfig(level=logging.INFO, stream=sys.stdout, - format='%(levelname)s (%(threadName)-9s) - %(message)s') + format='%(levelname)s (%(threadName)10s) - %(message)s') logger = logging.getLogger('OpenFPGA_Task_logs') @@ -71,7 +71,7 @@ def main(): else: pprint.pprint(job_run_list) logger.info("Task execution completed") - exit() + exit(0) # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Subroutines starts here @@ -80,8 +80,8 @@ def main(): def clean_up_and_exit(msg): logger.error(msg) - logger.error("Existing . . . . . .") - exit() + logger.error("Exiting . . . . . .") + exit(1) def validate_command_line_arguments(): @@ -112,8 +112,8 @@ def generate_each_task_actions(taskname): curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1) try: os.mkdir(curr_run_dir) - if os.path.islink('latest'): - os.unlink("latest") + if os.path.islink('latest') or os.path.exists('latest'): + os.remove("latest") os.symlink(curr_run_dir, "latest") logger.info('Created "%s" directory for current task run' % curr_run_dir) @@ -128,12 +128,17 @@ def generate_each_task_actions(taskname): task_conf.read_dict(script_env_vars) task_conf.read_file(open(curr_task_conf_file)) - required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES", "POST_RUN"] + required_sec = ["GENERAL", "BENCHMARKS", "ARCHITECTURES"] missing_section = list(set(required_sec)-set(task_conf.sections())) if missing_section: clean_up_and_exit("Missing sections %s" % " ".join(missing_section) + " in task configuration file") + # Declare varibles to access sections + TaskFileSections = task_conf.sections() + SynthSection = task_conf["SYNTHESIS_PARAM"] + GeneralSection = task_conf["GENERAL"] + # Check if specified architecture files exist archfile_list = [] for _, arch_file in task_conf["ARCHITECTURES"].items(): @@ -143,10 +148,16 @@ def generate_each_task_actions(taskname): else: clean_up_and_exit("Architecture file not found: " + "%s " % arch_file) + if not len(archfile_list) == len(list(set(archfile_list))): + clean_up_and_exit("Found duplicate architectures in config file") # Check if specified benchmark files exist benchmark_list = [] for bech_name, each_benchmark in task_conf["BENCHMARKS"].items(): + # Declare varible to store paramteres for current benchmark + CurrBenchPara = {} + + # Parse benchmark file bench_files = [] for eachpath in each_benchmark.split(","): files = glob.glob(eachpath) @@ -155,15 +166,51 @@ def generate_each_task_actions(taskname): " with path %s " % (eachpath)) bench_files += files - ys_for_task = task_conf.get("SYNTHESIS_PARAM", "bench_yosys_common", - fallback="") - benchmark_list.append({ - "files": bench_files, - "top_module": task_conf.get("SYNTHESIS_PARAM", bech_name+"_top", - fallback="top"), - "ys_script": task_conf.get("SYNTHESIS_PARAM", bech_name+"_yosys", - fallback=ys_for_task), - }) + # Read provided benchmark configurations + # Common configurations + ys_for_task_common = SynthSection.get("bench_yosys_common") + chan_width_common = SynthSection.get("bench_chan_width_common") + + # Individual benchmark configuration + CurrBenchPara["files"] = bench_files + CurrBenchPara["top_module"] = SynthSection.get(bech_name+"_top", + fallback="top") + CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys", + fallback=ys_for_task_common) + CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", + fallback=chan_width_common) + + logger.info('Running "%s" flow' % + GeneralSection.get("fpga_flow", fallback="yosys_vpr")) + if GeneralSection.get("fpga_flow") == "vpr_blif": + # Check if activity file exist + if not SynthSection.get(bech_name+"_act"): + clean_up_and_exit("Missing argument %s" % (bech_name+"_act") + + "for vpr_blif flow") + CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") + + # Check if base verilog file exists + if not SynthSection.get(bech_name+"_verilog"): + clean_up_and_exit("Missing argument %s for vpr_blif flow" % + (bech_name+"_verilog")) + CurrBenchPara["verilog_file"] = SynthSection.get( + bech_name+"_verilog") + + # Add script parameter list in current benchmark + ScriptSections = [x for x in TaskFileSections if "SCRIPT_PARAM" in x] + script_para_list = {} + for eachset in ScriptSections: + command = [] + for key, values in task_conf[eachset].items(): + command += ["--"+key, values] if values else ["--"+key] + + # Set label for Sript Parameters + set_lbl = eachset.replace("SCRIPT_PARAM", "") + set_lbl = set_lbl[1:] if set_lbl else "Common" + script_para_list[set_lbl] = command + CurrBenchPara["script_params"] = script_para_list + + benchmark_list.append(CurrBenchPara) # Create OpenFPGA flow run commnad for each combination of # architecture, benchmark and parameters @@ -171,16 +218,21 @@ def generate_each_task_actions(taskname): flow_run_cmd_list = [] for indx, arch in enumerate(archfile_list): for bench in benchmark_list: - flow_run_dir = get_flow_rundir(arch, bench["top_module"]) - cmd = create_run_command( - flow_run_dir, arch, bench, task_conf) - flow_run_cmd_list.append({ - "arch": arch, - "bench": bench, - "name": "%s_arch%d" % (bench["top_module"], indx), - "run_dir": flow_run_dir, - "commands": cmd, - "status": False}) + for lbl, param in bench["script_params"].items(): + flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) + command = create_run_command( + curr_job_dir=flow_run_dir, + archfile=arch, + benchmark_obj=bench, + param=param, + task_conf=task_conf) + flow_run_cmd_list.append({ + "arch": arch, + "bench": bench, + "name": "%02d_arch%s_%s" % (indx, bench["top_module"], lbl), + "run_dir": flow_run_dir, + "commands": command, + "status": False}) return flow_run_cmd_list @@ -193,7 +245,7 @@ def get_flow_rundir(arch, top_module, flow_params=None): return os.path.abspath(os.path.join(*path)) -def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): +def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): """ Create_run_script function accepts run directory, architecture list and fpga_flow configuration file and prepare final executable fpga_flow script @@ -217,23 +269,37 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, task_conf): os.makedirs(curr_job_dir) # Make execution command to run Open FPGA flow + task_gc = task_conf["GENERAL"] command = [archfile] + benchmark_obj["files"] command += ["--top_module", benchmark_obj["top_module"]] command += ["--run_dir", curr_job_dir] - if task_conf.getboolean("GENERAL", "power_analysis", fallback=False): + + if task_gc.get("fpga_flow"): + command += ["--fpga_flow", task_gc.get("fpga_flow")] + + if benchmark_obj.get("activity_file"): + command += ["--activity_file", benchmark_obj.get("activity_file")] + + if benchmark_obj.get("verilog_file"): + command += ["--base_verilog", benchmark_obj.get("verilog_file")] + + if benchmark_obj.get("ys_script"): + command += ["--yosys_tmpl", benchmark_obj["ys_script"]] + + if task_gc.getboolean("power_analysis"): command += ["--power"] - command += ["--power_tech", - task_conf.get("GENERAL", "power_tech_file")] - if task_conf.getboolean("GENERAL", "spice_output", fallback=False): + command += ["--power_tech", task_gc.get("power_tech_file")] + + if task_gc.getboolean("spice_output"): command += ["--vpr_fpga_spice"] - if task_conf.getboolean("GENERAL", "verilog_output", fallback=False): + + if task_gc.getboolean("verilog_output"): command += ["--vpr_fpga_verilog"] command += ["--vpr_fpga_verilog_dir", "."] command += ["--vpr_fpga_x2p_rename_illegal_port"] # Add other paramters to pass - for key, values in task_conf["SCRIPT_PARAM"].items(): - command += ["--"+key, values] if values else ["--"+key] + command += param if args.debug: command += ["--debug"] @@ -272,6 +338,8 @@ def run_single_script(s, eachJob): sys.stdout.buffer.flush() output.write(line) process.wait() + if process.returncode: + raise subprocess.CalledProcessError(0, []) eachJob["status"] = True except: logger.exception("Failed to execute openfpga flow - " + @@ -280,7 +348,8 @@ def run_single_script(s, eachJob): timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \ else str(timediff) - logger.info("%s Finished, Time Taken %s " % (name, timestr)) + logger.info("%s Finished with returncode %d, Time Taken %s " % + (name, process.returncode, timestr)) def run_actions(job_run_list): @@ -301,6 +370,7 @@ def collect_results(job_run_list): task_result = [] for run in job_run_list: if not run["status"]: + logger.warning("Skipping %s run", run["name"]) continue # Check if any result file exist if not glob.glob(os.path.join(run["run_dir"], "*.result")): @@ -311,8 +381,10 @@ def collect_results(job_run_list): interpolation=ExtendedInterpolation()) vpr_res.read_file( open(os.path.join(run["run_dir"], "vpr_stat.result"))) - result = dict(vpr_res["RESULTS"]) + result = OrderedDict() result["name"] = run["name"] + result["TotalRunTime"] = int(run["endtime"]-run["starttime"]) + result.update(vpr_res["RESULTS"]) task_result.append(result) if len(task_result): diff --git a/openfpga_flow/tasks/basic_flow/config/task.conf b/openfpga_flow/tasks/basic_flow/config/task.conf index c7b4f243a..2b0a45e4b 100644 --- a/openfpga_flow/tasks/basic_flow/config/task.conf +++ b/openfpga_flow/tasks/basic_flow/config/task.conf @@ -18,18 +18,17 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/s38417/s38417.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/MCNC_Verilog/elliptic/elliptic.v [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys bench0_top = s298 -bench1_top = alu4 -bench2_top = s38417 -bench0_yosys=${PATH:OPENFPGA_PATH}/vtr_flow/yosys/typical_run.yosys +bench1_top = elliptic -[SCRIPT_PARAM] -min_route_chan_width=30 +[SCRIPT_PARAM_1] +min_route_chan_width=1.3 + +[SCRIPT_PARAM_2] +min_route_chan_width=1.8 [POST_RUN] # Not Implemented yet diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf new file mode 100644 index 000000000..0e0d86ef9 --- /dev/null +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -0,0 +1,60 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_1] +fix_route_chan_width=300 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_x2p_compact_routing_hierarchy= +# end_flow_with_test= + + +# [SCRIPT_PARAM_2] +# fix_route_chan_width=200 +# vpr_fpga_verilog_include_icarus_simulator= +# vpr_fpga_verilog_formal_verification_top_netlist= +# vpr_fpga_verilog_include_timing= +# vpr_fpga_verilog_include_signal_init= +# vpr_fpga_verilog_print_autocheck_top_testbench= +# vpr_fpga_bitstream_generator= +# vpr_fpga_verilog_print_user_defined_template= +# vpr_fpga_verilog_print_report_timing_tcl= +# vpr_fpga_verilog_print_sdc_pnr= +# vpr_fpga_verilog_print_sdc_analysis= +# vpr_fpga_x2p_compact_routing_hierarchy= +# end_flow_with_test= \ No newline at end of file From 632c9d69762bad148f0b11c0ddafdd3b8178bd52 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 25 Aug 2019 00:42:48 -0600 Subject: [PATCH 133/482] Added python execution path in config file --- openfpga_flow/scripts/run_fpga_task.conf | 1 + openfpga_flow/scripts/run_fpga_task.py | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.conf b/openfpga_flow/scripts/run_fpga_task.conf index 2ccf44927..de0dac668 100644 --- a/openfpga_flow/scripts/run_fpga_task.conf +++ b/openfpga_flow/scripts/run_fpga_task.conf @@ -1,4 +1,5 @@ [GENERAL CONFIGURATION] task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc +python_path=python3.5 script_default=${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 62f1de6cc..4a13184a0 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -326,9 +326,13 @@ def run_single_script(s, eachJob): try: logfile = "%s_out.log" % name with open(logfile, 'w+') as output: - process = subprocess.Popen(["python3.5", - gc["script_default"]] + - eachJob["commands"], + output.write("* "*20 + '\n') + output.write("RunDirectory : %s\n" % os.getcwd()) + command = [gc["python_path"], gc["script_default"]] + \ + eachJob["commands"] + output.write(" ".join(command) + '\n') + output.write("* "*20 + '\n') + process = subprocess.Popen(command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, universal_newlines=True) From c4180fad6db72162d8e9b977e37557d220072671 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 25 Aug 2019 00:49:04 -0600 Subject: [PATCH 134/482] Added .gitignore to build docs locally --- docs/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 docs/.gitignore diff --git a/docs/.gitignore b/docs/.gitignore new file mode 100644 index 000000000..c6a151b32 --- /dev/null +++ b/docs/.gitignore @@ -0,0 +1 @@ +_build/ \ No newline at end of file From 7a3ff941167718fd6077709d62f16655b30b739a Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 25 Aug 2019 01:28:21 -0600 Subject: [PATCH 135/482] Added blif task in travis script --- .travis/script.sh | 4 ++-- openfpga_flow/tasks/blif_vpr_flow/config/task.conf | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index f0aad4a05..02627958c 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -10,7 +10,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then #make mkdir build cd build - cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off + cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off make -j16 alias python3.5="python3" ln -s /opt/local/bin/python3 /opt/local/bin/python3.5 @@ -30,4 +30,4 @@ $SPACER cd - # python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick chmod 755 run_test.sh -./run_test.sh \ No newline at end of file +python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow \ No newline at end of file diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index 0e0d86ef9..d766554b4 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -15,7 +15,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +# arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml @@ -41,7 +41,7 @@ vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_x2p_compact_routing_hierarchy= -# end_flow_with_test= +end_flow_with_test= # [SCRIPT_PARAM_2] From c43fabb43cfc5780e201366cd9683cc72b6f52d9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 25 Aug 2019 10:31:45 -0600 Subject: [PATCH 136/482] developed verilog instance writer. refactoring on mux ongoing --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 2 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 16 ++++++++-------- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 8 +++----- .../SRC/fpga_x2p/verilog/verilog_writer_utils.h | 2 +- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 62b06be92..2607aa558 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -246,6 +246,8 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Not found, we add a memory bit and record in the mem-to-mem map */ MuxMemId mem_subgraph = mux_graph.add_mem(); mem2mem_map[mem_origin] = mem_subgraph; + /* configure the edge */ + mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem_subgraph; } /* Since the graph is finalized, it is time to build the fast look-up */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 908a78ff9..bad43d388 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -109,7 +109,7 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma /* Iterate over the outputs */ for (const auto& mux_output : mux_graph.outputs()) { /* TODO: the magic number 0 should be generated by MUX graph */ - BasicPort cur_output_port(output_port.get_name(), 0); + BasicPort cur_output_port(output_port.get_name(), 0, 0); /* if there is a connection between the input and output, a tgate will be outputted */ std::vector edges = mux_graph.find_edges(mux_input, mux_output); /* There should be only one edge or no edge*/ @@ -120,11 +120,11 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma } /* TODO: Output a tgate use a module manager */ /* Create a port-to-port name map */ - std::map port2port_name_map; + std::map port2port_name_map; /* input port */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[0])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_input_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[0])] = cur_input_port; /* output port */ - port2port_name_map[circuit_lib.port_lib_name(tgate_output_ports[0])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_output_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_output_ports[0])] = cur_output_port; /* Find the mem_id controlling the edge */ MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); BasicPort cur_mem_port(mem_port.get_name(), size_t(mux_mem), size_t(mux_mem)); @@ -132,12 +132,12 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma /* mem port */ if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_port); - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_inv_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_port; + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_inv_port; } else { /* wire mem_inv to mem of module, wire mem to mem_inv of module */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_inv_port); - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = generate_verilog_port(VERILOG_PORT_CONKT, cur_mem_port); + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_inv_port; + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_port; } /* Output an instance of the module */ print_verilog_module_instance(fp, module_manager, module_id, tgate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(tgate_model)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 2d104126b..fb78b8a86 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -132,7 +132,7 @@ void print_verilog_module_declaration(std::fstream& fp, void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& parent_module_id, const ModuleId& child_module_id, - std::map& port2port_name_map, + const std::map& port2port_name_map, const bool& explicit_port_map) { check_file_handler(fp); @@ -166,11 +166,9 @@ void print_verilog_module_instance(std::fstream& fp, fp << "." << port.get_name() << "("; } /* Try to find the instanced port name in the name map */ - std::map::iterator it = port2port_name_map.find(port.get_name()); - if (it != port2port_name_map.end()) { + if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) { /* Found it, we assign the port name */ - BasicPort instance_port(port.get_name(), 1); - fp << generate_verilog_port(kv.second, instance_port); + fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name())); } else { /* Not found, we give the default port name */ fp << generate_verilog_port(kv.second, port); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index c1283804c..03626e4b6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -31,7 +31,7 @@ void print_verilog_module_declaration(std::fstream& fp, void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& parent_module_id, const ModuleId& child_module_id, - std::map& port2port_name_map, + const std::map& port2port_name_map, const bool& explicit_port_map); void print_verilog_module_end(std::fstream& fp, From 8fc258cc933770266dc1a7f8344b336ceb96ad14 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 24 Aug 2019 19:23:33 -0600 Subject: [PATCH 137/482] develop and plug mux_lib_builder, refactoring the mux submodule generation --- vpr7_x2p/vpr/SRC/device/mux_library.cpp | 10 + vpr7_x2p/vpr/SRC/device/mux_library.h | 2 + .../vpr/SRC/device/mux_library_builder.cpp | 186 ++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_library_builder.h | 14 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 4 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 9 +- .../verilog/verilog_essential_gates.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 125 +++++++++--- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.h | 12 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 48 +---- .../SRC/fpga_x2p/verilog/verilog_submodules.h | 2 + .../fpga_x2p/verilog/verilog_writer_utils.cpp | 9 +- 13 files changed, 343 insertions(+), 81 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/mux_library_builder.h diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.cpp b/vpr7_x2p/vpr/SRC/device/mux_library.cpp index 04ef5c378..ee51b087b 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_library.cpp @@ -43,6 +43,16 @@ CircuitModelId MuxLibrary::mux_circuit_model(const MuxId& mux_id) const { return mux_circuit_models_[mux_id]; } +/* Find the maximum mux size among the mux graphs */ +size_t MuxLibrary::max_mux_size() const { + /* Iterate over all the mux graphs and find their sizes */ + size_t max_mux_size = 0; + for (const auto& mux : mux_ids_) { + max_mux_size = std::max(max_mux_size, mux_graphs_[mux].num_inputs()); + } + return max_mux_size; +} + /************************************************** * Private mutators: *************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h index 7ffefba09..8f4ec71d8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.h +++ b/vpr7_x2p/vpr/SRC/device/mux_library.h @@ -27,6 +27,8 @@ class MuxLibrary { const MuxGraph& mux_graph(const MuxId& mux_id) const; /* Get a mux circuit model id */ CircuitModelId mux_circuit_model(const MuxId& mux_id) const; + /* Find the maximum mux size */ + size_t max_mux_size() const; public: /* Public mutators */ /* Add a mux to the library */ void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp b/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp new file mode 100644 index 000000000..9dc462572 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp @@ -0,0 +1,186 @@ +/******************************************************************** + * This file includes the functions of builders for MuxLibrary. + *******************************************************************/ +#include +#include +#include "vtr_assert.h" + +/* Device-level header files */ +#include "util.h" +#include "vpr_types.h" +#include "globals.h" + +/* FPGA-X2P context header files */ +#include "fpga_x2p_utils.h" + +#include "spice_types.h" +#include "circuit_library.h" +#include "mux_library.h" +#include "mux_library_builder.h" + +/******************************************************************** + * Update MuxLibrary with the unique multiplexer structures + * found in the global routing architecture + *******************************************************************/ +static +void build_routing_arch_mux_library(MuxLibrary& mux_lib, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_switch_inf* switches, + const CircuitLibrary& circuit_lib, + t_det_routing_arch* routing_arch) { + /* Current Version: Support Uni-directional routing architecture only*/ + if (UNI_DIRECTIONAL != routing_arch->directionality) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s, LINE[%d]) FPGA X2P Only supports uni-directional routing architecture.\n", + __FILE__, __LINE__); + exit(1); + } + + /* The routing path is. + * OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN + * Each edge is a switch, for IPIN, the switch is a connection block, + * for the rest is a switch box + */ + /* Count the sizes of muliplexers in routing architecture */ + for (int inode = 0; inode < LL_num_rr_nodes; inode++) { + t_rr_node& node = LL_rr_node[inode]; + switch (node.type) { + case IPIN: { + /* Have to consider the fan_in only, it is a connection block (multiplexer)*/ + VTR_ASSERT((node.fan_in > 0) || (0 == node.fan_in)); + if ( (0 == node.fan_in) || (1 == node.fan_in)) { + break; + } + /* Find the circuit_model for multiplexers in connection blocks */ + const CircuitModelId& cb_switch_circuit_model = switches[node.driver_switch].circuit_model; + /* we should select a circuit model for the connection box*/ + VTR_ASSERT(CircuitModelId::INVALID() != cb_switch_circuit_model); + /* Add the mux to mux_library */ + mux_lib.add_mux(circuit_lib, cb_switch_circuit_model, node.fan_in); + break; + } + case CHANX: + case CHANY: { + /* Channels are the same, have to consider the fan_in as well, + * it could be a switch box if previous rr_node is a channel + * or it could be a connection box if previous rr_node is a IPIN or OPIN + */ + VTR_ASSERT((node.fan_in > 0) || (0 == node.fan_in)); + if ((0 == node.fan_in) || (1 == node.fan_in)) { + break; + } + /* Find the spice_model for multiplexers in switch blocks*/ + const CircuitModelId& sb_switch_circuit_model = switches[node.driver_switch].circuit_model; + /* we should select a circuit model for the Switch box*/ + VTR_ASSERT(CircuitModelId::INVALID() != sb_switch_circuit_model); + /* Add the mux to mux_library */ + mux_lib.add_mux(circuit_lib, sb_switch_circuit_model, node.fan_in); + break; + } + default: + /* We do not care other types of rr_node */ + break; + } + } +} + +/******************************************************************** + * Update MuxLibrary with the unique multiplexer structures + * found in programmable logic blocks + ********************************************************************/ +static +void build_pb_type_mux_library_rec(MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_pb_type* cur_pb_type) { + VTR_ASSERT(nullptr != cur_pb_type); + + /* If there is spice_model_name, this is a leaf node!*/ + if (TRUE == is_primitive_pb_type(cur_pb_type)) { + /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node + * This may bring software convience but ruins circuit modeling + */ + VTR_ASSERT(CircuitModelId::INVALID() != cur_pb_type->phy_pb_type->circuit_model); + return; + } + + /* Traversal the hierarchy, find all the multiplexer from the interconnection part */ + for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { + /* Then we have to statisitic the interconnections*/ + for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { + /* Check the num_mux and fan_in of an interconnection */ + VTR_ASSERT ((0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) + || (0 < cur_pb_type->modes[imode].interconnect[jinterc].num_mux)); + if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { + continue; + } + CircuitModelId& interc_circuit_model = cur_pb_type->modes[imode].interconnect[jinterc].circuit_model; + VTR_ASSERT(CircuitModelId::INVALID() != interc_circuit_model); + /* Add the mux model to library */ + mux_lib.add_mux(circuit_lib, interc_circuit_model, cur_pb_type->modes[imode].interconnect[jinterc].fan_in); + } + } + + /* Go recursively to the lower level */ + for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { + for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { + build_pb_type_mux_library_rec(mux_lib, circuit_lib, + &cur_pb_type->modes[imode].pb_type_children[ichild]); + } + } +} + +/******************************************************************** + * Update MuxLibrary with the unique multiplexers required by + * LUTs in the circuit library + ********************************************************************/ +static +void build_lut_mux_library(MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib) { + /* Find all the circuit models which are LUTs in the circuit library */ + for (const auto& circuit_model : circuit_lib.models()) { + /* Bypass non-LUT circuit models */ + if (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) { + continue; + } + /* Find the MUX size required by the LUT */ + /* Get input ports which are not global ports! */ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == input_ports.size()); + /* MUX size = 2^lut_size */ + size_t lut_mux_size = (size_t)pow(2., (double)(circuit_lib.port_size(input_ports[0]))); + /* Add mux to the mux library */ + mux_lib.add_mux(circuit_lib, circuit_model, lut_mux_size); + } +} + +/* Statistic for all the multiplexers in FPGA + * We determine the sizes and its structure (according to spice_model) for each type of multiplexers + * We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks + * In additional to multiplexers, this function also consider crossbars. + * All the statistics are stored in a linked list, as a return value + */ +MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_switch_inf* switches, + const CircuitLibrary& circuit_lib, + t_det_routing_arch* routing_arch) { + /* MuxLibrary to store the information of Multiplexers*/ + MuxLibrary mux_lib; + + /* Step 1: We should check the multiplexer spice models defined in routing architecture.*/ + build_routing_arch_mux_library(mux_lib, LL_num_rr_nodes, LL_rr_node, switches, circuit_lib, routing_arch); + + /* Step 2: Count the sizes of multiplexers in complex logic blocks */ + for (int itype = 0; itype < num_types; itype++) { + if (NULL != type_descriptors[itype].pb_type) { + build_pb_type_mux_library_rec(mux_lib, circuit_lib, type_descriptors[itype].pb_type); + } + } + + /* Step 3: count the size of multiplexer that will be used in LUTs*/ + build_lut_mux_library(mux_lib, circuit_lib); + + return mux_lib; +} + + + diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.h b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h new file mode 100644 index 000000000..8a0965dd4 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h @@ -0,0 +1,14 @@ +/******************************************************************** + * This file includes the function declaration of builders + * for MuxLibrary. + * See details in mux_library_builder.cpp + *******************************************************************/ +#ifndef MUX_LIBRARY_BUILDER_H +#define MUX_LIBRARY_BUILDER_H + +MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_switch_inf* switches, + const CircuitLibrary& circuit_lib, + t_det_routing_arch* routing_arch); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 0881d5221..769a49dad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -29,6 +29,7 @@ std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, + const size_t& branch_mux_size, const std::string& postfix) { /* If the tgate spice model of this MUX is a MUX2 standard cell, * the mux_subckt name will be the name of the standard cell @@ -38,6 +39,7 @@ std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circui VTR_ASSERT (SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(subckt_model)); return circuit_lib.model_name(subckt_model); } + std::string branch_postfix = postfix + "_size" + std::to_string(branch_mux_size); - return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, postfix); + return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index ff91f4854..bd67c61f4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -19,6 +19,7 @@ std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, + const size_t& branch_mux_size, const std::string& posfix); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index abbae27ac..989f580f7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -33,6 +33,8 @@ #include "fpga_bitstream.h" #include "module_manager.h" +#include "mux_library.h" +#include "mux_library_builder.h" /* Include SynVerilog headers */ #include "verilog_global.h" @@ -153,6 +155,11 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Module manager for the Verilog modules created */ ModuleManager module_manager; + /* Build Multiplexer library */ + MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); + + /* 0. basic units: inverter, buffers and pass-gate logics, */ + /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { vpr_printf(TIO_MESSAGE_ERROR, "FPGA synthesizable Verilog dumping only support uni-directional routing architecture!\n"); @@ -274,7 +281,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ - dump_verilog_submodules(module_manager, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, + dump_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, Arch, &vpr_setup.RoutingArch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 8aba48226..a94828c5e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -507,7 +507,7 @@ void print_verilog_submodule_essentials(ModuleManager& module_manager, /* Create file */ vpr_printf(TIO_MESSAGE_INFO, "Generating Verilog netlist (%s) for essential gates...\n", - __FILE__, __LINE__, essentials_verilog_file_name); + __FILE__, __LINE__, verilog_fname.c_str()); print_verilog_file_header(fp, "Essential gates"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index dce86830a..f8e64cd70 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -12,6 +12,7 @@ /* Device-level header files */ #include "mux_graph.h" +#include "module_manager.h" #include "physical_types.h" #include "vpr_types.h" @@ -30,8 +31,9 @@ * for a multiplexer with the given size **********************************************/ static -void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, +void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + std::fstream& fp, const CircuitModelId& circuit_model, const std::string& module_name, const MuxGraph& mux_graph) { @@ -44,7 +46,7 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, return; } - /* Get model ports of tgate */ + /* TODO: move to check_circuit_library? Get model ports of tgate */ std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); @@ -68,36 +70,30 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, /* MUX graph must have only 1 level*/ VTR_ASSERT(1 == mux_graph.num_levels()); - /* Print Verilog module */ - print_verilog_module_definition(fp, module_name); - - /* Create port information */ - /* Configure each input port */ - BasicPort input_port("in", num_inputs); - - /* Configure each output port */ - BasicPort output_port("out", num_outputs); - - /* Configure each memory port */ - BasicPort mem_port("mem", num_mems); - BasicPort mem_inv_port("mem_inv", num_mems); - - /* TODO: Generate global ports */ + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ for (const auto& port : tgate_global_ports) { /* Configure each global port */ - BasicPort basic_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - /* Print port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl; + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } + /* Add each input port */ + BasicPort input_port("in", num_inputs); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort output_port("out", num_outputs); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add each memory port */ + BasicPort mem_port("mem", num_mems); + module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port("mem_inv", num_mems); + module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - /* TODO: add a module to the Module Manager */ - - /* Port list */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << "," << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_port) << "," << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_inv_port) << std::endl; - fp << ");" << std::endl; + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); /* Verilog Behavior description for a MUX */ print_verilog_comment(fp, std::string("---- Structure-level description -----")); @@ -177,18 +173,20 @@ void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp, * Generate Verilog codes modeling an branch circuit * for a multiplexer with the given size **********************************************/ -void generate_verilog_mux_branch_module(std::fstream& fp, +static +void generate_verilog_mux_branch_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + std::fstream& fp, const CircuitModelId& circuit_model, const size_t& mux_size, const MuxGraph& mux_graph) { - std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, verilog_mux_basis_posfix); + std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { case SPICE_MODEL_DESIGN_CMOS: if (true == circuit_lib.dump_structural_verilog(circuit_model)) { - generate_verilog_cmos_mux_branch_module_structural(fp, circuit_lib, circuit_model, module_name, mux_graph); + generate_verilog_cmos_mux_branch_module_structural(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); } else { /* dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name, @@ -222,3 +220,68 @@ void generate_verilog_mux_branch_module(std::fstream& fp, return; } + +/*********************************************** + * Generate Verilog modules for all the unique + * multiplexers in the FPGA device + **********************************************/ +void print_verilog_submodule_muxes(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* submodule_dir) { + + /* TODO: Generate modules into a .bak file now. Rename after it is verified */ + std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name)); + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for Multiplexers (%s) ...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Multiplexers"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Generate basis sub-circuit for unique branches shared by the multiplexers */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* Create a mux graph for the branch circuit */ + std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); + /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ + for (auto branch_mux_graph : branch_mux_graphs) { + generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, + mux_graph.num_inputs(), branch_mux_graph); + } + } + + /* Dump MUX graph one by one */ + + /* Close the file steam */ + fp.close(); + + /* TODO: + * Scan-chain configuration circuit does not need any BLs/WLs! + * SRAM MUX does not need any reserved BL/WLs! + */ + /* Determine reserved Bit/Word Lines if a memory bank is specified, + * At least 1 BL/WL should be reserved! + */ + try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, + mux_lib.max_mux_size(), mux_lib.max_mux_size()); + + /* TODO: Add fname to the linked list when debugging is finished */ + /* + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); + */ +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index c7dfd4bf8..8b30d6820 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -11,11 +11,13 @@ #include "circuit_library.h" #include "mux_graph.h" #include "mux_library.h" +#include "module_manager.h" -void generate_verilog_mux_branch_module(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const MuxGraph& mux_graph); +void print_verilog_submodule_muxes(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* submodule_dir); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 230306d3c..7bd065cbe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -29,6 +29,7 @@ #include "fpga_x2p_globals.h" #include "fpga_x2p_mux_utils.h" #include "fpga_x2p_bitstream_utils.h" +#include "mux_library.h" /* Include verilog utils */ #include "verilog_global.h" @@ -2228,11 +2229,13 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Alloc the muxes*/ muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); - + /* Print the muxes netlist*/ fp = fopen(verilog_name, "w"); if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, verilog_name); + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s", + __FILE__, __LINE__, verilog_name); exit(1); } /* Generate the descriptions*/ @@ -2292,41 +2295,6 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, temp = temp->next; } - /* Generate modules into a .bak file now. Rename after it is verified */ - std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name)); - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream sfp; - sfp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for Multiplexers (%s) ...\n", - verilog_fname.c_str()); - check_file_handler(sfp); - - /* TODO: this conversion is temporary. Will be removed after code reconstruction */ - MuxLibrary mux_lib = convert_mux_arch_to_library(spice->circuit_lib, muxes_head); - - /* Generate basis sub-circuit for unique branches shared by the multiplexers */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* Create a mux graph for the branch circuit */ - std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); - /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ - for (auto branch_mux_graph : branch_mux_graphs) { - generate_verilog_mux_branch_module(sfp, spice->circuit_lib, mux_circuit_model, - mux_graph.num_inputs(), branch_mux_graph); - } - } - - /* Dump MUX graph one by one */ - - /* Close the file steam */ - sfp.close(); - /* TODO: * Scan-chain configuration circuit does not need any BLs/WLs! * SRAM MUX does not need any reserved BL/WLs! @@ -3507,6 +3475,7 @@ void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, * 1. MUXes */ void dump_verilog_submodules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, @@ -3514,7 +3483,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, t_det_routing_arch* routing_arch, t_syn_verilog_opts fpga_verilog_opts) { - /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); print_verilog_submodule_essentials(module_manager, std::string(verilog_dir), @@ -3525,6 +3493,10 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + + print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, + verilog_dir, submodule_dir); + vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h index 1e6aa814b..3d6a30e99 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h @@ -2,8 +2,10 @@ #define VERILOG_SUBMODULES_H #include "module_manager.h" +#include "mux_library.h" void dump_verilog_submodules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* submodule_dir, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 81c9bed5f..f58ee587e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -55,7 +55,7 @@ void print_verilog_include_defines_preproc_file(std::fstream& fp, fp << "//------ Include defines: preproc flags -----" << std::endl; fp << "`include \"" << include_file_path << "\"" << std::endl; - fp << "//------ End Include defines: preproc flags -----" << std::endl; + fp << "//------ End Include defines: preproc flags -----" << std::endl << std::endl; return; } @@ -102,10 +102,11 @@ void print_verilog_module_ports(std::fstream& fp, for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { if (0 != port_cnt) { /* Do not dump a comma for the first port */ - fp << ", //----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + fp << "," << std::endl; } /* Print port */ - fp << "\t" << generate_verilog_port(kv.second, port) << std::endl; + fp << "\t//----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + fp << "\t" << generate_verilog_port(kv.second, port); port_cnt++; } } @@ -119,7 +120,7 @@ void print_verilog_module_declaration(std::fstream& fp, check_file_handler(fp); print_verilog_module_definition(fp, module_manager.module_name(module_id)); - + print_verilog_module_ports(fp, module_manager, module_id); fp << std::endl << ");" << std::endl; From 056c45321bed08aa161ed795bc7a88fe4e5c36c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 23 Aug 2019 17:39:29 -0600 Subject: [PATCH 138/482] plug in module manager --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index f58ee587e..eab5e1b53 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -120,7 +120,7 @@ void print_verilog_module_declaration(std::fstream& fp, check_file_handler(fp); print_verilog_module_definition(fp, module_manager.module_name(module_id)); - + print_verilog_module_ports(fp, module_manager, module_id); fp << std::endl << ");" << std::endl; From 1cfc117b32f93b9d610eef9fcfb0f05386e81b47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 25 Aug 2019 10:31:45 -0600 Subject: [PATCH 139/482] developed verilog instance writer. refactoring on mux ongoing --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 2 + .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 107 +++++++----------- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 58 ++++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 6 + 4 files changed, 109 insertions(+), 64 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index a6879d770..3416dbadf 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -190,6 +190,8 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Not found, we add a memory bit and record in the mem-to-mem map */ MuxMemId mem_subgraph = mux_graph.add_mem(); mem2mem_map[mem_origin] = mem_subgraph; + /* configure the edge */ + mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem_subgraph; } /* Since the graph is finalized, it is time to build the fast look-up */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index f8e64cd70..b0ecb0e26 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -97,71 +97,50 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma /* Verilog Behavior description for a MUX */ print_verilog_comment(fp, std::string("---- Structure-level description -----")); - /* Special case: only one memory, switch case is simpler - * When mem = 1, propagate input 0; - * when mem = 0, propagate input 1; - */ - /* TODO: we should output the netlist following the connections in mux_graph */ - if (1 == num_mems) { - /* Transmission gates are connected to each input and also the output*/ - fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_0 "; - /* Dump explicit port map if required */ - /* TODO: add global port support for tgate model */ - if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { - fp << " ("; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[0]" << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port) << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")"; - fp << ");" << std::endl; - } else { - fp << " ("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port); - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port); - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << ");" << std::endl; - } - /* Transmission gates are connected to each input and also the output*/ - fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_1 "; - /* Dump explicit port map if required */ - if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { - fp << " ("; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[1]" << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port) << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")"; - fp << ");" << std::endl; - } else { - fp << " ("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port); - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port); - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << ");" << std::endl; - } - } else { - /* Other cases, we need to follow the rules: - * When mem[k] is enabled, switch on input[k] - * Only one memory bit is enabled! - */ - for (size_t i = 0; i < num_mems; i++) { - fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_" << i << " "; - if (true == circuit_lib.dump_explicit_port_map(tgate_model)) { - fp << " ("; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[" << i << "]" << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << "mem[" << i << "]" << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << "mem_inv[" << i << "]" << "),"; - fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")"; - fp << ");" << std::endl; - } else { - fp << " ("; - fp << "in[" << i << "]"; - fp << ", " << "mem[" << i << "]"; - fp << ", " << "mem_inv[" << i << "]"; - fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << ");" << std::endl; + + /* Output the netlist following the connections in mux_graph */ + /* Iterate over the inputs */ + for (const auto& mux_input : mux_graph.inputs()) { + BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); + /* Iterate over the outputs */ + for (const auto& mux_output : mux_graph.outputs()) { + /* TODO: the magic number 0 should be generated by MUX graph */ + BasicPort cur_output_port(output_port.get_name(), 0, 0); + /* if there is a connection between the input and output, a tgate will be outputted */ + std::vector edges = mux_graph.find_edges(mux_input, mux_output); + /* There should be only one edge or no edge*/ + VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); + /* No need to output tgates if there are no edges between two nodes */ + if (0 == edges.size()) { + continue; } + /* TODO: Output a tgate use a module manager */ + /* Create a port-to-port name map */ + std::map port2port_name_map; + /* input port */ + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[0])] = cur_input_port; + /* output port */ + port2port_name_map[circuit_lib.port_lib_name(tgate_output_ports[0])] = cur_output_port; + /* Find the mem_id controlling the edge */ + MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); + BasicPort cur_mem_port(mem_port.get_name(), size_t(mux_mem), size_t(mux_mem)); + BasicPort cur_mem_inv_port(mem_inv_port.get_name(), size_t(mux_mem), size_t(mux_mem)); + /* mem port */ + if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { + /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_port; + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_inv_port; + } else { + /* wire mem_inv to mem of module, wire mem to mem_inv of module */ + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_inv_port; + port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_port; + } + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, tgate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(tgate_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, tgate_module_id); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index eab5e1b53..c47278857 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -126,6 +126,64 @@ void print_verilog_module_declaration(std::fstream& fp, fp << std::endl << ");" << std::endl; } +/************************************************ + * Print an instance for a Verilog module + ***********************************************/ +void print_verilog_module_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module_id, const ModuleId& child_module_id, + const std::map& port2port_name_map, + const bool& explicit_port_map) { + + check_file_handler(fp); + + /* Print module name */ + fp << "\t" << module_manager.module_name(child_module_id) << " "; + /* Print instance name, _ */ + fp << module_manager.module_name(child_module_id) << "_" << module_manager.num_instance(parent_module_id, child_module_id) << "_" << " (" << std::endl; + + /* Print each port with/without explicit port map */ + /* port type2type mapping */ + std::map port_type2type_map; + port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT; + + /* Port sequence: global, inout, input, output and clock ports, */ + size_t port_cnt = 0; + for (const auto& kv : port_type2type_map) { + for (const auto& port : module_manager.module_ports_by_type(child_module_id, kv.first)) { + if (0 != port_cnt) { + /* Do not dump a comma for the first port */ + fp << "," << std::endl; + } + /* Print port */ + fp << "\t\t"; + /* if explicit port map is required, output the port name */ + if (true == explicit_port_map) { + fp << "." << port.get_name() << "("; + } + /* Try to find the instanced port name in the name map */ + if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) { + /* Found it, we assign the port name */ + fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name())); + } else { + /* Not found, we give the default port name */ + fp << generate_verilog_port(kv.second, port); + } + /* if explicit port map is required, output the pair of branket */ + if (true == explicit_port_map) { + fp << ")"; + } + port_cnt++; + } + } + + /* Print an end to the instance */ + fp << "\t" << ");" << std::endl; +} /************************************************ * Print an end line for a Verilog module diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 3f65fb726..03626e4b6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -28,6 +28,12 @@ void print_verilog_module_ports(std::fstream& fp, void print_verilog_module_declaration(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id); +void print_verilog_module_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module_id, const ModuleId& child_module_id, + const std::map& port2port_name_map, + const bool& explicit_port_map); + void print_verilog_module_end(std::fstream& fp, const std::string& module_name); From 14db2bf1a9ee71e0a774bc79710d3c9713ab9129 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 25 Aug 2019 16:35:49 -0600 Subject: [PATCH 140/482] minor fixing on comment --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index c47278857..887d5763d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -77,7 +77,7 @@ void print_verilog_module_definition(std::fstream& fp, const std::string& module_name) { check_file_handler(fp); - print_verilog_comment(fp, std::string("//----- Verilog module for " + module_name + " -----")); + print_verilog_comment(fp, std::string("----- Verilog module for " + module_name + " -----")); fp << "module " << module_name << "(" << std::endl; } From b6617a5adf1de53b456e3979f4ce329dbfc4fec4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 25 Aug 2019 16:37:46 -0600 Subject: [PATCH 141/482] fix bugs in verilog comment lines --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 887d5763d..8747b8c18 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -193,7 +193,7 @@ void print_verilog_module_end(std::fstream& fp, check_file_handler(fp); fp << "endmodule" << std::endl; - print_verilog_comment(fp, std::string("//----- END Verilog module for " + module_name + " -----")); + print_verilog_comment(fp, std::string("----- END Verilog module for " + module_name + " -----")); fp << std::endl; } From de8a6bc8337fc9339b2100d40079cb9c19a03968 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 26 Aug 2019 21:00:15 -0600 Subject: [PATCH 142/482] update regression tests --- .travis/script.sh | 3 +- .../tasks/blif_vpr_flow/config/task.conf | 31 ++-- run_test.sh | 133 ------------------ 3 files changed, 17 insertions(+), 150 deletions(-) delete mode 100644 run_test.sh diff --git a/.travis/script.sh b/.travis/script.sh index 02627958c..1cbec97e5 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -29,5 +29,4 @@ $SPACER cd - # python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick -chmod 755 run_test.sh -python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow \ No newline at end of file +python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 6 diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index d766554b4..e6b808ced 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -18,6 +18,7 @@ fpga_flow=vpr_blif # arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml +arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif @@ -28,7 +29,7 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_mode bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v bench0_chan_width = 300 -[SCRIPT_PARAM_1] +[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] fix_route_chan_width=300 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= @@ -44,17 +45,17 @@ vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= -# [SCRIPT_PARAM_2] -# fix_route_chan_width=200 -# vpr_fpga_verilog_include_icarus_simulator= -# vpr_fpga_verilog_formal_verification_top_netlist= -# vpr_fpga_verilog_include_timing= -# vpr_fpga_verilog_include_signal_init= -# vpr_fpga_verilog_print_autocheck_top_testbench= -# vpr_fpga_bitstream_generator= -# vpr_fpga_verilog_print_user_defined_template= -# vpr_fpga_verilog_print_report_timing_tcl= -# vpr_fpga_verilog_print_sdc_pnr= -# vpr_fpga_verilog_print_sdc_analysis= -# vpr_fpga_x2p_compact_routing_hierarchy= -# end_flow_with_test= \ No newline at end of file +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= diff --git a/run_test.sh b/run_test.sh deleted file mode 100644 index 58eb6e869..000000000 --- a/run_test.sh +++ /dev/null @@ -1,133 +0,0 @@ -# python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ -# ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ -# --top_module s298 \ -# --power \ -# --power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \ -# --min_route_chan_width 1.3 \ -# --vpr_fpga_verilog \ -# --vpr_fpga_verilog_dir . \ -# --vpr_fpga_x2p_rename_illegal_port \ -# --end_flow_with_test \ -# --vpr_fpga_verilog_include_icarus_simulator \ -# --vpr_fpga_verilog_formal_verification_top_netlist \ -# --vpr_fpga_verilog_include_timing \ -# --vpr_fpga_verilog_include_signal_init \ -# --vpr_fpga_verilog_print_autocheck_top_testbench - -# Test popular multi-mode architecture -python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ -./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ ---fpga_flow vpr_blif \ ---top_module test_modes \ ---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ ---power \ ---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ -#--fix_route_chan_width 300 \ ---min_route_chan_width 1.3 \ ---vpr_fpga_verilog \ ---vpr_fpga_verilog_dir . \ ---vpr_fpga_x2p_rename_illegal_port \ ---vpr_fpga_verilog_include_icarus_simulator \ ---vpr_fpga_verilog_formal_verification_top_netlist \ ---vpr_fpga_verilog_include_timing \ ---vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ ---debug \ ---vpr_fpga_bitstream_generator \ ---vpr_fpga_verilog_print_user_defined_template \ ---vpr_fpga_verilog_print_report_timing_tcl \ ---vpr_fpga_verilog_print_sdc_pnr \ ---vpr_fpga_verilog_print_sdc_analysis \ ---vpr_fpga_x2p_compact_routing_hierarchy \ ---end_flow_with_test - -# Test Standard cell MUX2 -python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ -./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ ---fpga_flow vpr_blif \ ---top_module test_modes \ ---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ ---power \ ---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ -#--fix_route_chan_width 300 \ ---min_route_chan_width 1.3 \ ---vpr_fpga_verilog \ ---vpr_fpga_verilog_dir . \ ---vpr_fpga_x2p_rename_illegal_port \ ---vpr_fpga_verilog_include_icarus_simulator \ ---vpr_fpga_verilog_formal_verification_top_netlist \ ---vpr_fpga_verilog_include_timing \ ---vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ ---debug \ ---vpr_fpga_bitstream_generator \ ---vpr_fpga_verilog_print_user_defined_template \ ---vpr_fpga_verilog_print_report_timing_tcl \ ---vpr_fpga_verilog_print_sdc_pnr \ ---vpr_fpga_verilog_print_sdc_analysis \ ---vpr_fpga_x2p_compact_routing_hierarchy \ ---end_flow_with_test - -# Test local encoder feature -python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \ -./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ ---fpga_flow vpr_blif \ ---top_module test_modes \ ---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ ---power \ ---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ ---fix_route_chan_width 300 \ ---vpr_fpga_verilog \ ---vpr_fpga_verilog_dir . \ ---vpr_fpga_x2p_rename_illegal_port \ ---vpr_fpga_verilog_include_icarus_simulator \ ---vpr_fpga_verilog_formal_verification_top_netlist \ ---vpr_fpga_verilog_include_timing \ ---vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ ---debug \ ---vpr_fpga_bitstream_generator \ ---vpr_fpga_verilog_print_user_defined_template \ ---vpr_fpga_verilog_print_report_timing_tcl \ ---vpr_fpga_verilog_print_sdc_pnr \ ---vpr_fpga_verilog_print_sdc_analysis \ ---vpr_fpga_x2p_compact_routing_hierarchy \ ---end_flow_with_test - -# Test tileable routing feature -#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ -#./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \ -#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ -#--fpga_flow vpr_blif \ -#--top_module test_modes \ -#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ -#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ -#--power \ -#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ -##--fix_route_chan_width 300 \ -#--min_route_chan_width 1.3 \ -#--vpr_fpga_verilog \ -#--vpr_fpga_verilog_dir . \ -#--vpr_fpga_x2p_rename_illegal_port \ -#--vpr_fpga_verilog_include_icarus_simulator \ -#--vpr_fpga_verilog_formal_verification_top_netlist \ -#--vpr_fpga_verilog_include_timing \ -#--vpr_fpga_verilog_include_signal_init \ -#--vpr_fpga_verilog_print_autocheck_top_testbench \ -#--debug \ -#--vpr_fpga_bitstream_generator \ -#--vpr_fpga_verilog_print_user_defined_template \ -#--vpr_fpga_verilog_print_report_timing_tcl \ -#--vpr_fpga_verilog_print_sdc_pnr \ -#--vpr_fpga_verilog_print_sdc_analysis \ -#--vpr_fpga_x2p_compact_routing_hierarchy \ -#--vpr_use_tileable_route_chan_width \ -#--end_flow_with_test - From ab6f1a5461d0467eb0cd26aca83f27598a67f3e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 26 Aug 2019 21:21:50 -0600 Subject: [PATCH 143/482] add mux output ids for mux_graph --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 31 ++++++++++++++++++- vpr7_x2p/vpr/SRC/device/mux_graph.h | 4 +++ vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h | 2 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 3 +- 4 files changed, 37 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 2607aa558..281747188 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -203,6 +203,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Add output nodes to subgraph */ MuxNodeId to_node_subgraph = mux_graph.add_node(MUX_OUTPUT_NODE); mux_graph.node_levels_[to_node_subgraph] = 1; + mux_graph.node_output_ids_[to_node_subgraph] = MuxOutputId(0); /* Update the node-to-node map */ node2node_map[root_node] = to_node_subgraph; @@ -308,6 +309,15 @@ MuxInputId MuxGraph::input_id(const MuxNodeId& node_id) const { return node_input_ids_[node_id]; } +/* Get the input id of a given node */ +MuxOutputId MuxGraph::output_id(const MuxNodeId& node_id) const { + /* Validate node id */ + VTR_ASSERT(valid_node_id(node_id)); + /* Must be an input */ + VTR_ASSERT(MUX_OUTPUT_NODE == node_types_[node_id]); + return node_output_ids_[node_id]; +} + /* Get the node id of a given input */ MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { /* Use the node_lookup to accelerate the search */ @@ -354,7 +364,10 @@ std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id) con /* Visit the next node */ next_node = edge_sink_nodes_[edge][0]; } + + /* valid the output */ VTR_ASSERT_SAFE(MUX_OUTPUT_NODE == node_types_[next_node]); + VTR_ASSERT_SAFE(valid_output_id(node_output_ids_[next_node])); return mem_bits; } @@ -370,6 +383,7 @@ MuxNodeId MuxGraph::add_node(const enum e_mux_graph_node_type& node_type) { /* Resize the other node-related vectors */ node_types_.push_back(node_type); node_input_ids_.push_back(MuxInputId::INVALID()); + node_output_ids_.push_back(MuxOutputId::INVALID()); node_levels_.push_back(-1); node_in_edges_.emplace_back(); node_out_edges_.emplace_back(); @@ -494,6 +508,7 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, /* Number of outputs is definite, add and configure */ MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); node_levels_[output_node] = num_levels; + node_output_ids_[output_node] = MuxOutputId(0); /* Update node lookup */ node_lookup[num_levels].push_back(output_node); @@ -609,6 +624,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, */ MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); node_levels_[output_node] = 1; + node_output_ids_[output_node] = MuxOutputId(0); for (size_t i = 0; i < mux_size; ++i) { MuxNodeId input_node = add_node(MUX_INPUT_NODE); @@ -731,7 +747,7 @@ bool MuxGraph::valid_mem_id(const MuxMemId& mem) const { return size_t(mem) < mem_ids_.size() && mem_ids_[mem] == mem; } -/* validate an input id (from which data path signal will be progagated to the output */ +/* validate an input id (from which data path signal will be progagated to the output) */ bool MuxGraph::valid_input_id(const MuxInputId& input_id) const { for (const auto& lvl : node_lookup_) { for (const auto& node : lvl[MUX_INPUT_NODE]) { @@ -744,6 +760,19 @@ bool MuxGraph::valid_input_id(const MuxInputId& input_id) const { return true; } +/* validate an output id */ +bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const { + for (const auto& lvl : node_lookup_) { + for (const auto& node : lvl[MUX_OUTPUT_NODE]) { + if (size_t(output_id) > size_t(node_output_ids_[node])) { + return false; + } + } + } + + return true; +} + bool MuxGraph::valid_node_lookup() const { return node_lookup_.empty(); } diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 87fda06ac..10f758809 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -86,6 +86,8 @@ class MuxGraph { MuxNodeId node_id(const MuxInputId& input_id) const; /* Get the input id of a given node */ MuxInputId input_id(const MuxNodeId& node_id) const; + /* Get the output id of a given node */ + MuxOutputId output_id(const MuxNodeId& node_id) const; /* Decode memory bits based on an input id */ std::vector decode_memory_bits(const MuxInputId& input_id) const; private: /* Private mutators : basic operations */ @@ -116,6 +118,7 @@ class MuxGraph { bool valid_edge_id(const MuxEdgeId& edge) const; bool valid_mem_id(const MuxMemId& mem) const; bool valid_input_id(const MuxInputId& input_id) const; + bool valid_output_id(const MuxOutputId& output_id) const; /* validate/invalidate node lookup */ bool valid_node_lookup() const; void invalidate_node_lookup(); @@ -125,6 +128,7 @@ class MuxGraph { vtr::vector node_ids_; /* Unique ids for each node */ vtr::vector node_types_; /* type of each node, input/output/internal */ vtr::vector node_input_ids_; /* Unique ids for each node as an input of the MUX */ + vtr::vector node_output_ids_; /* Unique ids for each node as an input of the MUX */ vtr::vector node_levels_; /* at which level, each node belongs to */ vtr::vector> node_in_edges_; /* ids of incoming edges to each node */ vtr::vector> node_out_edges_; /* ids of outgoing edges from each node */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h index 815102e6d..fca07ca2a 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h @@ -13,11 +13,13 @@ struct mux_node_id_tag; struct mux_edge_id_tag; struct mux_mem_id_tag; struct mux_input_id_tag; +struct mux_output_id_tag; typedef vtr::StrongId MuxNodeId; typedef vtr::StrongId MuxEdgeId; typedef vtr::StrongId MuxMemId; typedef vtr::StrongId MuxInputId; +typedef vtr::StrongId MuxOutputId; class MuxGraph; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index bad43d388..555971542 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -108,8 +108,7 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); /* Iterate over the outputs */ for (const auto& mux_output : mux_graph.outputs()) { - /* TODO: the magic number 0 should be generated by MUX graph */ - BasicPort cur_output_port(output_port.get_name(), 0, 0); + BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); /* if there is a connection between the input and output, a tgate will be outputted */ std::vector edges = mux_graph.find_edges(mux_input, mux_output); /* There should be only one edge or no edge*/ From f04565386fa34f890797ac454c6b2a52f76602b6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 27 Aug 2019 18:39:25 -0600 Subject: [PATCH 144/482] refactored behavioral mux branch verilog generation --- .travis/script.sh | 2 +- .../tasks/blif_vpr_flow/config/task.conf | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 256 +++++++++++++----- 3 files changed, 184 insertions(+), 75 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index 1cbec97e5..0d9e3b54e 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -29,4 +29,4 @@ $SPACER cd - # python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick -python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 6 +python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index e6b808ced..d796d6c8a 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=vpr_blif arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 555971542..70ca6f78d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -26,78 +26,34 @@ #include "verilog_writer_utils.h" #include "verilog_mux.h" -/*********************************************** - * Generate Verilog codes modeling an branch circuit +/********************************************************************* + * Generate structural Verilog codes (consist of transmission-gates or + * pass-transistor) modeling an branch circuit * for a multiplexer with the given size - **********************************************/ + *********************************************************************/ static -void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& circuit_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Get the tgate model */ - CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model); - - /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ - if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { - VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); - return; - } - - /* TODO: move to check_circuit_library? Get model ports of tgate */ - std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); - std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(3 == tgate_input_ports.size()); - VTR_ASSERT(1 == tgate_output_ports.size()); - +void generate_verilog_cmos_mux_branch_body_structural(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& tgate_model, + const ModuleId& module_id, + const BasicPort& input_port, + const BasicPort& output_port, + const BasicPort& mem_port, + const BasicPort& mem_inv_port, + const MuxGraph& mux_graph) { /* Make sure we have a valid file handler*/ check_file_handler(fp); - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of inputs */ - size_t num_inputs = mux_graph.num_inputs(); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == num_outputs); - /* MUX graph must have only 1 level*/ - VTR_ASSERT(1 == mux_graph.num_levels()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : tgate_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - BasicPort input_port("in", num_inputs); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Add each output port */ - BasicPort output_port("out", num_outputs); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Add each memory port */ - BasicPort mem_port("mem", num_mems); - module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port("mem_inv", num_mems); - module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - /* Get the module id of tgate in Module manager */ ModuleId tgate_module_id = module_manager.find_module(circuit_lib.model_name(tgate_model)); VTR_ASSERT(ModuleId::INVALID() != tgate_module_id); - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); + /* TODO: move to check_circuit_library? Get model ports of tgate */ + std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); + std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(3 == tgate_input_ports.size()); + VTR_ASSERT(1 == tgate_output_ports.size()); /* Verilog Behavior description for a MUX */ print_verilog_comment(fp, std::string("---- Structure-level description -----")); @@ -146,6 +102,167 @@ void generate_verilog_cmos_mux_branch_module_structural(ModuleManager& module_ma module_manager.add_child_module(module_id, tgate_module_id); } } +} + +/********************************************************************* + * Generate behavior-level Verilog codes modeling an branch circuit + * for a multiplexer with the given size + *********************************************************************/ +static +void generate_verilog_cmos_mux_branch_body_behavioral(std::fstream& fp, + const BasicPort& input_port, + const BasicPort& output_port, + const BasicPort& mem_port, + const MuxGraph& mux_graph, + const size_t& default_mem_val) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Verilog Behavior description for a MUX */ + print_verilog_comment(fp, std::string("---- Behavioral-level description -----")); + + /* Add an internal register for the output */ + BasicPort outreg_port("out_reg", mux_graph.num_outputs()); + /* Print the port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, outreg_port) << ";" << std::endl; + + /* Generate the case-switch table */ + fp << "\talways @(" << generate_verilog_port(VERILOG_PORT_CONKT, input_port) << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << ")" << std::endl; + fp << "\tcase (" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << ")" << std::endl; + + /* Output the netlist following the connections in mux_graph */ + /* Iterate over the inputs */ + for (const auto& mux_input : mux_graph.inputs()) { + BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); + /* Iterate over the outputs */ + for (const auto& mux_output : mux_graph.outputs()) { + BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); + /* if there is a connection between the input and output, a tgate will be outputted */ + std::vector edges = mux_graph.find_edges(mux_input, mux_output); + /* There should be only one edge or no edge*/ + VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); + /* No need to output tgates if there are no edges between two nodes */ + if (0 == edges.size()) { + continue; + } + /* For each case, generate the logic levels for all the inputs */ + /* In each case, only one mem is enabled */ + fp << "\t\t" << mem_port.get_width() << "'b"; + std::string case_code(mem_port.get_width(), default_mem_val); + + /* Find the mem_id controlling the edge */ + MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); + /* Flip a bit by the mem_id */ + if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { + case_code[size_t(mux_mem)] = '1'; + } else { + case_code[size_t(mux_mem)] = '0'; + } + fp << case_code << ": " << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << " <= "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_input_port) << ";" << std::endl; + } + } + + /* Default case: outputs are at high-impedance state 'z' */ + std::string default_case(mux_graph.num_outputs(), 'z'); + fp << "\t\tdefault: " << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << " <= "; + fp << mux_graph.num_outputs() << "'b" << default_case << ";" << std::endl; + + /* End the case */ + fp << "\tendcase" << std::endl; + + /* Wire registers to output ports */ + fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " = "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << ";" << std::endl; +} + +/********************************************************************* + * Generate Verilog codes modeling an branch circuit + * for a multiplexer with the given size + * Support structural and behavioral Verilog codes + *********************************************************************/ +static +void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& circuit_model, + const std::string& module_name, + const MuxGraph& mux_graph, + const bool& use_structural_verilog) { + /* Get the tgate model */ + CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model); + + /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ + if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); + return; + } + + std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); + + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of inputs */ + size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == num_outputs); + /* MUX graph must have only 1 level*/ + VTR_ASSERT(1 == mux_graph.num_levels()); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ + for (const auto& port : tgate_global_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port */ + BasicPort input_port("in", num_inputs); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort output_port("out", num_outputs); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add each memory port */ + BasicPort mem_port("mem", num_mems); + module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port("mem_inv", num_mems); + module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + + /* Print the internal logic in either structural or behavioral Verilog codes */ + if (true == use_structural_verilog) { + generate_verilog_cmos_mux_branch_body_structural(module_manager, circuit_lib, fp, tgate_model, module_id, input_port, output_port, mem_port, mem_inv_port, mux_graph); + } else { + VTR_ASSERT_SAFE(false == use_structural_verilog); + /* Get the default value of SRAM ports */ + std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); + std::vector non_mode_select_sram_ports; + /* We should have only have 1 sram port except those are mode_bits */ + for (const auto& port : sram_ports) { + if (true == circuit_lib.port_is_mode_select(port)) { + continue; + } + non_mode_select_sram_ports.push_back(port); + } + VTR_ASSERT(1 == non_mode_select_sram_ports.size()); + std::string mem_default_val = std::to_string(circuit_lib.port_default_value(non_mode_select_sram_ports[0])); + /* Mem string must be only 1-bit! */ + VTR_ASSERT(1 == mem_default_val.length()); + generate_verilog_cmos_mux_branch_body_behavioral(fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]); + } /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); @@ -167,17 +284,8 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { case SPICE_MODEL_DESIGN_CMOS: - if (true == circuit_lib.dump_structural_verilog(circuit_model)) { - generate_verilog_cmos_mux_branch_module_structural(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); - } else { - /* - dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name, - mux_size, - num_input_basis_subckt, - cur_spice_model, - special_basis); - */ - } + generate_verilog_cmos_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph, + circuit_lib.dump_structural_verilog(circuit_model)); break; case SPICE_MODEL_DESIGN_RRAM: /* If requested, we can dump structural verilog for basis module */ From 94538b50625ecf258491cea8d07e0921142249f2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 27 Aug 2019 18:44:58 -0600 Subject: [PATCH 145/482] add more testing architecture --- ...m_chain_HC_behavioral_verilog_template.xml | 1042 +++++++++++++++++ 1 file changed, 1042 insertions(+) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml new file mode 100644 index 000000000..4d26f30ad --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml @@ -0,0 +1,1042 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + From 715adc13ffdbb73050ea2abd174ea556bbdf6531 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 27 Aug 2019 21:25:38 -0600 Subject: [PATCH 146/482] Failed result do not throw error --- openfpga_flow/scripts/run_fpga_task.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 4a13184a0..5466e5b7e 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -343,7 +343,7 @@ def run_single_script(s, eachJob): output.write(line) process.wait() if process.returncode: - raise subprocess.CalledProcessError(0, []) + raise subprocess.CalledProcessError(0, command) eachJob["status"] = True except: logger.exception("Failed to execute openfpga flow - " + @@ -390,10 +390,13 @@ def collect_results(job_run_list): result["TotalRunTime"] = int(run["endtime"]-run["starttime"]) result.update(vpr_res["RESULTS"]) task_result.append(result) - + colnames = [] + for eachLbl in task_result: + colnames.extend(eachLbl.keys()) if len(task_result): with open("task_result.csv", 'w', newline='') as csvfile: - writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys()) + writer = csv.DictWriter( + csvfile, extrasaction='ignore', fieldnames=list(set(colnames))) writer.writeheader() for eachResult in task_result: writer.writerow(eachResult) From f54a8522fa01081a45ae0fcbd21e879df39fdcf9 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 27 Aug 2019 22:04:32 -0600 Subject: [PATCH 147/482] Log prints task stats --- openfpga_flow/scripts/run_fpga_task.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 5466e5b7e..6ef37b7f2 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -151,6 +151,10 @@ def generate_each_task_actions(taskname): if not len(archfile_list) == len(list(set(archfile_list))): clean_up_and_exit("Found duplicate architectures in config file") + # Get Flow information + logger.info('Running "%s" flow' % + GeneralSection.get("fpga_flow", fallback="yosys_vpr")) + # Check if specified benchmark files exist benchmark_list = [] for bech_name, each_benchmark in task_conf["BENCHMARKS"].items(): @@ -180,8 +184,7 @@ def generate_each_task_actions(taskname): CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) - logger.info('Running "%s" flow' % - GeneralSection.get("fpga_flow", fallback="yosys_vpr")) + if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist if not SynthSection.get(bech_name+"_act"): @@ -233,6 +236,10 @@ def generate_each_task_actions(taskname): "run_dir": flow_run_dir, "commands": command, "status": False}) + + logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' % + (len(archfile_list), len(benchmark_list), len(ScriptSections))) + logger.info('Created total %d jobs' % len(flow_run_cmd_list)) return flow_run_cmd_list From a25124b58cd370fa0403bb2a19a72aefada9303b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 29 Aug 2019 21:37:07 -0600 Subject: [PATCH 148/482] Added additional PATH variables --- openfpga_flow/scripts/run_fpga_task.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 6ef37b7f2..00ee85ee9 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -50,6 +50,11 @@ args = parser.parse_args() task_script_dir = os.path.dirname(os.path.abspath(__file__)) script_env_vars = ({"PATH": { "OPENFPGA_FLOW_PATH": task_script_dir, + "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"), + "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"), + "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"), + "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"), + "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"), "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir))}}) config = ConfigParser(interpolation=ExtendedInterpolation()) @@ -153,7 +158,7 @@ def generate_each_task_actions(taskname): # Get Flow information logger.info('Running "%s" flow' % - GeneralSection.get("fpga_flow", fallback="yosys_vpr")) + GeneralSection.get("fpga_flow", fallback="yosys_vpr")) # Check if specified benchmark files exist benchmark_list = [] @@ -184,7 +189,6 @@ def generate_each_task_actions(taskname): CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) - if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist if not SynthSection.get(bech_name+"_act"): From 02137805c715e4947362bd3e68920fcfd1356761 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 29 Aug 2019 22:13:18 -0600 Subject: [PATCH 149/482] Added python version check in flow and task scripts --- openfpga_flow/scripts/run_fpga_flow.py | 12 ++++++++++++ openfpga_flow/scripts/run_fpga_task.py | 13 +++++++++++++ 2 files changed, 25 insertions(+) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 69bbe1063..3a35830bd 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -1,3 +1,12 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Script Name : run_fpga_flow.py +# Description : This script designed to run different flows supported by +# OpensFPGA project. +# Args : python3 run_fpga_flow.py --help +# Author : Ganesh Gore +# Email : ganeshgore@utah.edu +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + import os import sys import shutil @@ -18,6 +27,9 @@ from importlib import util if util.find_spec("humanize"): import humanize +if sys.version_info[0] < 3: + raise Exception("run_fpga_task script must be using Python 3") + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Initialise general paths for the script # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 00ee85ee9..f5b6ee9bd 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -1,3 +1,13 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Script Name : run_fpga_task.py +# Description : This script designed to run openfpga_flow tasks, +# Opensfpga task are design to run opefpga_flow on each +# Combination of architecture, benchmark and script paramters +# Args : python3 run_fpga_task.py --help +# Author : Ganesh Gore +#Email : ganeshgore@utah.edu +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + import os import sys import shutil @@ -19,6 +29,9 @@ from collections import OrderedDict if util.find_spec("humanize"): import humanize +if sys.version_info[0] < 3: + raise Exception("run_fpga_task script must be using Python 3") + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = From 06c0dbb3288f8091c8dc26b13949383381c778f2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 15:19:34 -0600 Subject: [PATCH 150/482] Added docuementation for fpga_flow --- docs/Makefile | 9 +- docs/source/run_fpga_flow.rst | 181 +++++++++++++++++++++++++ openfpga_flow/scripts/run_fpga_flow.py | 18 ++- 3 files changed, 199 insertions(+), 9 deletions(-) create mode 100755 docs/source/run_fpga_flow.rst diff --git a/docs/Makefile b/docs/Makefile index 9d20886ea..1f299ec6b 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -7,7 +7,7 @@ SPHINXBUILD = sphinx-build SOURCEDIR = source BUILDDIR = build -PAPER = +PAPER = PAPEROPT_a4 = -D latex_paper_size=a4 PAPEROPT_letter = -D latex_paper_size=letter ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SOURCEDIR) @@ -16,7 +16,10 @@ ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SO help: @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) -clean: +livehtml: + sphinx-autobuild -b html $(ALL_SPHINXOPTS) $(BUILDDIR)/html + +clean: rm -rf $(BUILDDIR)/* .PHONY: help clean Makefile @@ -27,4 +30,4 @@ clean: @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) #html: # $(SPHINXBUILD) -b html $@ "$(SOURCEDIR)" "$(BUILDDIR)/html" $(SPHINXOPTS) - + diff --git a/docs/source/run_fpga_flow.rst b/docs/source/run_fpga_flow.rst new file mode 100755 index 000000000..7f22dbfec --- /dev/null +++ b/docs/source/run_fpga_flow.rst @@ -0,0 +1,181 @@ +.. _run_fpga_flow: + +run_fpga_flow +--------------- + +This python script executes the supported openfpga flow for a +single benchmark and architecture file for given script parameters. + +The script is located at:: + + ${OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py + +.. program:: run_fpga_flow.py + +Basic Usage +~~~~~~~~~~~ + +At a minimum ``open_fpga_flow.py`` requires following command-line arguments:: + + open_fpga_flow.py --top_module + +where: + + * ```` is the target :ref:`FPGA architecture ` + * ```` The list of files in the benchmark (Supports ../directory/\*.v) + * ```` The name of the top level module in Verilog project + +.. note:: + The script will create a ``tmp`` run directory in base OpenFPGA path, unless otherwise specified with the :option:`--run_dir` option. + All stages of the flow will be run within run directory. + Several intermediate files will be generated and maintian in run directory. + The path variables declared in architecture XML file will be resolved with absolute path and copied to the ``tmp/arch`` directory before executing flow. + All the benchmark files provided will be copied to ``tmp/bench`` directory without maintaining any directory structure. + **Users should ensure that no important files are kept in this directory as script will clear directory before each execution** + +OpenFPGA Variables +~~~~~~~~~~~~~~~~~~ +Frequently, while running OpenFPGA flow User is suppose to refer external files. +To avoid long names and referencing errors user can use +following openfpga variables. +These variables are resolved with absolute path while execution making +each run independent of launch directory. + + + * ```` Path to the base OpenFPGA directory + * ```` Path to the run_fpga_flow script directory + * ```` Path where spice netlists are saved + * ```` Path where verilog modules are saved + * ```` Path where all characterized XML files are stored + +For example in architecture file path vairable can be used as follows:: + + .... lib_path="${TECH_PATH}/PTM_45nm/45nm.pm" .... + +Output +~~~~~~ +Based on which flow is executed, resulting intermediate files are generated in run_directory + +The output log of the script provides status of each stage to the user. +If any stage failed to execute, the output log will indicate the stage at which execution failed, and execution traceback. + +In case of successful execution, The openfpga flow script will parse +parameters lited in configuration from different result files and will create +``vpr_stat.txt``, ``vpr_stat_power.txt`` \(optional\) file in run_directory. + +Advanced Usage +~~~~~~~~~~~~~~ + +User can pass additional *optional* command arguments to ``run_fpga_flow.py`` script:: + + run_fpga_flow.py [] [] [] [] [] [] + + +where: + + * ```` are additional arguments passed to ``run_fpga_flow.py`` (described below), + * ```` Any argument prefixed with ``--vpr-*`` will be forwarded to vpr script as it is. The detail of supported vpr argument is available ``Add corrrect reference`` + * ```` are any arguments not recognized by ``run_vtr_flow.pl``. These will be forwarded to VPR. + * ```` these arguments will be passed to ACE activity estimator program + +For example:: + + run_fpga_flow.py my_circuit.v my_arch.xml -track_memory_usage --pack --place + +will run the VTR flow to map the circuit ``my_circuit.v`` onto the architecture ``my_arch.xml``; the arguments ``--pack`` and ``--place`` will be passed to VPR (since they are unrecognized arguments to ``run_vtr_flow.pl``). +They will cause VPR to perform only :ref:`packing and placement `. + +Detailed Command-line Options +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + .. Note:: All the commnadline arguments starting with ``vpr_*`` , ``fpga-verilog_*`` , ``fpga-spice_*`` or ``fpga-bitstream_*`` will be passed to VPR without suffix + +General Arguments +^^^^^^^^^^^^^^^^^ + +.. option:: --top_module + + Provide top module name of the benchmark. Default ``top`` + +.. option:: --run_dir + + Using this option user can provide custom path as a run directory. Default is ``tmp`` directory in OpenFPGA root path. + +.. option:: --K + + This option defines the number of inputs to the LUT. By default script parses provided architecture file and finds out inputs to the biggest LUT. + +.. option:: --yosys_tmpl + + This option allows user to provide a custom yosys template + while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need. + +.. option:: --debug + + To enable detail logs printing + +.. option:: --flow_config + + User can provide option flow ocnfiguration file to override some of the default script paramteres. + for detail information refer :ref:`OpenFPGA Flow Configuration ` + +ACE Arguments +^^^^^^^^^^^^^ +.. option:: --black_box_ace + + Performs ACE simulation on black box [deprecated] + +VPR RUN Arguments +^^^^^^^^^^^^^^^^^ + +.. option:: --fix_route_chan_width + + Perfoms VPR implementation for fixed number of channels defined as the 'channel_number' + +.. option:: --min_route_chan_width + + Performs VPR implementation to get minimum channel width and then perform fixed channel rerouting with ``percentage_slack`` increase in the channle width. + +.. option:: --max_route_width_retry + + Number of times the channel width should be incresese and attempt VPR implmenetation, while performaning ``min_route_chan_width`` + +.. option:: --power +.. option:: --power_tech + + +blif_vpr_flow Arguments +^^^^^^^^^^^^^^^^^^^^^^^^ + +.. option:: --activity_file + + Activity to be used for the given benchmark while running ``blif_vpr_flow`` + +.. option:: --base_verilog + + Verilog benchmark file to perform verification while running ``bliff_vpr_flow`` + + + +.. _OpenFPGA_Conf_File: +OpenFPGA Flow Configuration file +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The OpenFPGA Flow configuration file consists of following sections + + * ``CAD_TOOLS_PATH`` + Lists executable file path for different CAD tools used in the script + + * ``FLOW_SCRIPT_CONFIG`` + Lists the supported flows by the script. + + * ``DEFAULT_PARSE_RESULT_VPR`` + Default prarameters to parse from Place, Pack and Route output. + + * ``DEFAULT_PARSE_RESULT_POWER`` + Default prarameters to parse from VPR power analysis output. + + * ``INTERMIDIATE_FILE_PREFIX`` + [Not implemented yet] + +Default OpenFPGA_flow Configuration file is located in ``open_fpga_flow\misc\fpgaflow_default_tool_path.conf``. +User supplied configuration file overrides or extendes the dafult configuration. \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3a35830bd..946954329 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -43,9 +43,15 @@ openfpga_base_dir = os.path.abspath( launch_dir = os.getcwd() # Path section to append in configuration file to interpolate path -script_env_vars = {"PATH": { - "OPENFPGA_FLOW_PATH": flow_script_dir, - "OPENFPGA_PATH": openfpga_base_dir}} +script_env_vars = ({"PATH": { + "OPENFPGA_FLOW_PATH": task_script_dir, + "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"), + "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"), + "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"), + "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"), + "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"), + "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, + os.pardir))}}) # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Reading command-line argument @@ -66,7 +72,7 @@ parser.add_argument('benchmark_files', type=str, nargs='+') # Optional arguments parser.add_argument('--top_module', type=str, default="top") parser.add_argument('--fpga_flow', type=str, default="yosys_vpr") -parser.add_argument('--cad_tool_conf', type=str, +parser.add_argument('--flow_config', type=str, help="CAD tools path overrides default setting") parser.add_argument('--run_dir', type=str, default=os.path.join(openfpga_base_dir, 'tmp'), @@ -281,8 +287,8 @@ def read_script_config(): default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc', 'fpgaflow_default_tool_path.conf') config.read_file(open(default_cad_tool_conf)) - if args.cad_tool_conf: - config.read_file(open(args.cad_tool_conf)) + if args.flow_config: + config.read_file(open(args.flow_config)) if not "CAD_TOOLS_PATH" in config.sections(): clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config") cad_tools = config["CAD_TOOLS_PATH"] From 3ce63e6163c567c224e4d49350aa8f657802ba6c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 15:26:14 -0600 Subject: [PATCH 151/482] Added abc and yosys cache in travis --- .travis.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 6a1566909..27488c034 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,9 +3,11 @@ language: cpp # cache results cache: directories: + - $HOME/abc + - $HOME/yosys - $HOME/.ccache -# Currently sudo is not required, NO ENV is used +# Currently sudo is not required, NO ENV is used # Supported Operating systems #os: From 32d47d6b8bb24762adbac1aebf3d89083f221352 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 16:13:47 -0600 Subject: [PATCH 152/482] Update document + Travis cache check --- docs/source/run_fpga_flow.rst | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/docs/source/run_fpga_flow.rst b/docs/source/run_fpga_flow.rst index 7f22dbfec..051b5064a 100755 --- a/docs/source/run_fpga_flow.rst +++ b/docs/source/run_fpga_flow.rst @@ -3,7 +3,7 @@ run_fpga_flow --------------- -This python script executes the supported openfpga flow for a +This python script executes the supported OpenFPGA flow for a single benchmark and architecture file for given script parameters. The script is located at:: @@ -45,7 +45,7 @@ each run independent of launch directory. * ```` Path to the base OpenFPGA directory * ```` Path to the run_fpga_flow script directory * ```` Path where spice netlists are saved - * ```` Path where verilog modules are saved + * ```` Path where Verilog modules are saved * ```` Path where all characterized XML files are stored For example in architecture file path vairable can be used as follows:: @@ -54,13 +54,13 @@ For example in architecture file path vairable can be used as follows:: Output ~~~~~~ -Based on which flow is executed, resulting intermediate files are generated in run_directory +Based on which flow is executed, resulting in intermediate files are generated in run_directory -The output log of the script provides status of each stage to the user. -If any stage failed to execute, the output log will indicate the stage at which execution failed, and execution traceback. +The output log of the script provides the status of each stage to the user. +If any stage failed to execute, the output log would indicate the stage at which execution failed, and execution traceback. -In case of successful execution, The openfpga flow script will parse -parameters lited in configuration from different result files and will create +In case of successful execution, The OpenFPGA flow script will parse +parameters listed in configuration from different result files and will create ``vpr_stat.txt``, ``vpr_stat_power.txt`` \(optional\) file in run_directory. Advanced Usage @@ -99,46 +99,46 @@ General Arguments .. option:: --run_dir - Using this option user can provide custom path as a run directory. Default is ``tmp`` directory in OpenFPGA root path. + Using this option user can provide a custom path as a run directory. Default is ``tmp`` directory in OpenFPGA root path. .. option:: --K - This option defines the number of inputs to the LUT. By default script parses provided architecture file and finds out inputs to the biggest LUT. + This option defines the number of inputs to the LUT. By default, the script parses provided architecture file and finds out inputs to the biggest LUT. .. option:: --yosys_tmpl - This option allows user to provide a custom yosys template - while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need. + This option allows the user to provide a custom Yosys template + While running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need. .. option:: --debug - To enable detail logs printing + To enable detail logs printing. .. option:: --flow_config - User can provide option flow ocnfiguration file to override some of the default script paramteres. + User can provide option flow configuration file to override some of the default script parameters. for detail information refer :ref:`OpenFPGA Flow Configuration ` ACE Arguments ^^^^^^^^^^^^^ .. option:: --black_box_ace - Performs ACE simulation on black box [deprecated] + Performs ACE simulation on the black box [deprecated] VPR RUN Arguments ^^^^^^^^^^^^^^^^^ .. option:: --fix_route_chan_width - Perfoms VPR implementation for fixed number of channels defined as the 'channel_number' + Performs VPR implementation for a fixed number of channels defined as the 'channel_number' .. option:: --min_route_chan_width - Performs VPR implementation to get minimum channel width and then perform fixed channel rerouting with ``percentage_slack`` increase in the channle width. + Performs VPR implementation to get minimum channel width and then perform fixed channel rerouting with ``percentage_slack`` increase in the channel width. .. option:: --max_route_width_retry - Number of times the channel width should be incresese and attempt VPR implmenetation, while performaning ``min_route_chan_width`` + Number of times the channel width should be increased and attempt VPR implementation, while performing ``min_route_chan_width`` .. option:: --power .. option:: --power_tech @@ -169,13 +169,13 @@ The OpenFPGA Flow configuration file consists of following sections Lists the supported flows by the script. * ``DEFAULT_PARSE_RESULT_VPR`` - Default prarameters to parse from Place, Pack and Route output. + List of default parameters to be parsed from Place, Pack, and Route output * ``DEFAULT_PARSE_RESULT_POWER`` - Default prarameters to parse from VPR power analysis output. + List of default parameters to be parsed from VPR power analysis output * ``INTERMIDIATE_FILE_PREFIX`` [Not implemented yet] Default OpenFPGA_flow Configuration file is located in ``open_fpga_flow\misc\fpgaflow_default_tool_path.conf``. -User supplied configuration file overrides or extendes the dafult configuration. \ No newline at end of file +User-supplied configuration file overrides or extends the default configuration. \ No newline at end of file From 31c4d40e66d300fe259c7e80f9489f8e05514cf0 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 20:00:44 -0600 Subject: [PATCH 153/482] Updated cache directory variable --- .travis.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 27488c034..8d119b059 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,8 +3,10 @@ language: cpp # cache results cache: directories: - - $HOME/abc - - $HOME/yosys + - $TRAVIS_BUILD_DIR/abc + - $TRAVIS_BUILD_DIR/yosys + - $TRAVIS_BUILD_DIR/ace2 + - $TRAVIS_BUILD_DIR/libs - $HOME/.ccache # Currently sudo is not required, NO ENV is used From d13c6a32ff46e33b216c4b2603e2ccf7a1dd9a15 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 20:45:54 -0600 Subject: [PATCH 154/482] Test travis cache --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 8d119b059..6a5d58344 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,6 +1,7 @@ language: cpp # cache results + cache: directories: - $TRAVIS_BUILD_DIR/abc From 3d4f7f66fd849e1876fe611503a6599cfd85d212 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 21:42:31 -0600 Subject: [PATCH 155/482] Updated to run with python3 --- .travis/script.sh | 32 ++++++++---------------- openfpga_flow/scripts/run_fpga_task.conf | 2 +- run_test.sh | 14 +++++------ 3 files changed, 19 insertions(+), 29 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index 02627958c..04c8d3fec 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -6,28 +6,18 @@ set -e $SPACER start_section "OpenFPGA.build" "${GREEN}Building..${NC}" -if [[ $TRAVIS_OS_NAME == 'osx' ]]; then - #make - mkdir build - cd build - cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off - make -j16 - alias python3.5="python3" - ln -s /opt/local/bin/python3 /opt/local/bin/python3.5 -else -# For linux, we enable full package compilation - #make - mkdir build - cd build - cmake --version - cmake .. -DCMAKE_BUILD_TYPE=debug - make -j16 -fi -end_section "OpenFPGA.build" +mkdir build +cd build + +if [[ $TRAVIS_OS_NAME == 'osx' ]]; then + cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off +else + cmake .. -DCMAKE_BUILD_TYPE=debug +fi + make -j16 +end_section "OpenFPGA.build" $SPACER cd - -# python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick -chmod 755 run_test.sh -python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow \ No newline at end of file +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_task.conf b/openfpga_flow/scripts/run_fpga_task.conf index de0dac668..a9c373c0f 100644 --- a/openfpga_flow/scripts/run_fpga_task.conf +++ b/openfpga_flow/scripts/run_fpga_task.conf @@ -1,5 +1,5 @@ [GENERAL CONFIGURATION] task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc -python_path=python3.5 +python_path=python3 script_default=${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py diff --git a/run_test.sh b/run_test.sh index 58eb6e869..027a1bea4 100644 --- a/run_test.sh +++ b/run_test.sh @@ -1,4 +1,4 @@ -# python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +# python3 openfpga_flow/scripts/run_fpga_flow.py \ # ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ # ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \ # --top_module s298 \ @@ -16,7 +16,7 @@ # --vpr_fpga_verilog_print_autocheck_top_testbench # Test popular multi-mode architecture -python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +python3 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ --fpga_flow vpr_blif \ @@ -45,7 +45,7 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --end_flow_with_test # Test Standard cell MUX2 -python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +python3 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ --fpga_flow vpr_blif \ @@ -73,8 +73,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --vpr_fpga_x2p_compact_routing_hierarchy \ --end_flow_with_test -# Test local encoder feature -python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +# Test local encoder feature +python3 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \ ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ --fpga_flow vpr_blif \ @@ -101,8 +101,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \ --vpr_fpga_x2p_compact_routing_hierarchy \ --end_flow_with_test -# Test tileable routing feature -#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ +# Test tileable routing feature +#python3 openfpga_flow/scripts/run_fpga_flow.py \ #./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \ #./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ #--fpga_flow vpr_blif \ From f4e99c150a14d742d1e4436c1d2368603e48bf92 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 21:55:32 -0600 Subject: [PATCH 156/482] resolve missing variable bug --- openfpga_flow/scripts/run_fpga_flow.py | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 946954329..8399ac63c 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -43,6 +43,7 @@ openfpga_base_dir = os.path.abspath( launch_dir = os.getcwd() # Path section to append in configuration file to interpolate path +task_script_dir = os.path.dirname(os.path.abspath(__file__)) script_env_vars = ({"PATH": { "OPENFPGA_FLOW_PATH": task_script_dir, "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"), From ad4c688206e100a3c1fc5545f4c1978322b9e35c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 22:04:57 -0600 Subject: [PATCH 157/482] Added print for JobID to architecture mapping --- openfpga_flow/scripts/run_fpga_task.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index f5b6ee9bd..04babac98 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -53,6 +53,8 @@ parser.add_argument('--test_run', action="store_true", help="Dummy run shows final generated VPR commands") parser.add_argument('--debug', action="store_true", help="Run script in debug mode") +parser.add_argument('--exit_on_fail', action="store_true", + help="Exit script with return code") parser.add_argument('--skip_tread_logs', action="store_true", help="Skips logs from running thread") args = parser.parse_args() @@ -372,6 +374,8 @@ def run_single_script(s, eachJob): except: logger.exception("Failed to execute openfpga flow - " + eachJob["name"]) + if args.exit_on_fail: + clean_up_and_exit("Faile to run task %s exiting" % name) eachJob["endtime"] = time.time() timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \ @@ -384,12 +388,12 @@ def run_actions(job_run_list): thread_sema = threading.Semaphore(args.maxthreads) thred_list = [] for index, eachjob in enumerate(job_run_list): + JobID = 'Job_%02d' % (index+1) + logger.info("Running %s = %s" % (JobID, eachjob["name"])) t = threading.Thread(target=run_single_script, - name='Job_%02d' % (index+1), - args=(thread_sema, eachjob)) + name=JobID, args=(thread_sema, eachjob)) t.start() thred_list.append(t) - for eachthread in thred_list: eachthread.join() From be6b11304e48a195c02fd8fb6648d77a35ca5388 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 22:36:18 -0600 Subject: [PATCH 158/482] Added travis fold for Python Task [ci skip] --- .travis/script.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index 04c8d3fec..61f53d776 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,5 +19,7 @@ fi end_section "OpenFPGA.build" $SPACER +start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow \ No newline at end of file +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow +end_section "OpenFPGA.TaskTun" From ac8cc230ed3d74726130c2c01ec9c7f70eace526 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 31 Aug 2019 22:53:42 -0600 Subject: [PATCH 159/482] Added Exit on fail option to travis task run --- .travis/common.sh | 4 +++- .travis/script.sh | 7 ++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/.travis/common.sh b/.travis/common.sh index 28d3cb3f9..d5a157049 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -15,6 +15,7 @@ export -f travis_time_start export -f travis_time_finish function start_section() { + $SPACER travis_fold start "$1" travis_time_start echo -e "${PURPLE}OpenFPGA${NC}: - $2${NC}" @@ -25,6 +26,7 @@ function end_section() { echo -e "${GRAY}-------------------------------------------------------------------${NC}" travis_time_finish travis_fold end "$1" + $SPACER } # For Mac OS, we use g++ and gcc as default compilers @@ -35,7 +37,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -else +else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 export CXX=g++-8 diff --git a/.travis/script.sh b/.travis/script.sh index 61f53d776..10cf00931 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -3,10 +3,7 @@ source .travis/common.sh set -e -$SPACER - start_section "OpenFPGA.build" "${GREEN}Building..${NC}" - mkdir build cd build @@ -17,9 +14,9 @@ else fi make -j16 end_section "OpenFPGA.build" -$SPACER + start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --exit_on_fail end_section "OpenFPGA.TaskTun" From 0439476abe2980c3c70e2fb2d50842d8a480f676 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 1 Sep 2019 00:08:14 -0600 Subject: [PATCH 160/482] Removed OSX allowed failure from travis --- .travis.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 6a5d58344..562418241 100644 --- a/.travis.yml +++ b/.travis.yml @@ -18,9 +18,6 @@ cache: # - osx # Create a matrix to branch the building environment matrix: - allow_failures: - - os: osx - #dist: trusty include: - os: linux # Compiler is specified in ./travis/common.sh From 241b001282d62313aa59dbb1b3fc019ec9c5fd87 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 1 Sep 2019 22:15:53 -0600 Subject: [PATCH 161/482] Added openfpga_task doc --- docs/source/index.rst | 11 +- docs/source/run_fpga_flow.rst | 6 +- docs/source/run_fpga_task.rst | 213 +++++++++++++++++++++++++ openfpga_flow/scripts/run_fpga_task.py | 1 + 4 files changed, 226 insertions(+), 5 deletions(-) create mode 100644 docs/source/run_fpga_task.rst diff --git a/docs/source/index.rst b/docs/source/index.rst index 1c5132355..51fd1b119 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -12,10 +12,15 @@ Welcome to OpenFPGA's documentation! motivation .. toctree:: - :caption: Getting Started + :caption: Getting Started eda_flow + run_fpga_flow + + run_fpga_task + + .. toctree:: :maxdepth: 2 :caption: Tools Guide @@ -37,10 +42,10 @@ Welcome to OpenFPGA's documentation! .. toctree:: :maxdepth: 2 :caption: Appendix - + contact reference - + For more information on the VTR see vtr_doc_ or vtr_github_ For more information on the Yosys see yosys_doc_ or yosys_github_ diff --git a/docs/source/run_fpga_flow.rst b/docs/source/run_fpga_flow.rst index 051b5064a..3a182f6d7 100755 --- a/docs/source/run_fpga_flow.rst +++ b/docs/source/run_fpga_flow.rst @@ -1,6 +1,6 @@ .. _run_fpga_flow: -run_fpga_flow +OpenFPGA Flow --------------- This python script executes the supported OpenFPGA flow for a @@ -33,6 +33,8 @@ where: All the benchmark files provided will be copied to ``tmp/bench`` directory without maintaining any directory structure. **Users should ensure that no important files are kept in this directory as script will clear directory before each execution** +.. _openfpga-variables: + OpenFPGA Variables ~~~~~~~~~~~~~~~~~~ Frequently, while running OpenFPGA flow User is suppose to refer external files. @@ -178,4 +180,4 @@ The OpenFPGA Flow configuration file consists of following sections [Not implemented yet] Default OpenFPGA_flow Configuration file is located in ``open_fpga_flow\misc\fpgaflow_default_tool_path.conf``. -User-supplied configuration file overrides or extends the default configuration. \ No newline at end of file +User-supplied configuration file overrides or extends the default configuration. diff --git a/docs/source/run_fpga_task.rst b/docs/source/run_fpga_task.rst new file mode 100644 index 000000000..c25527546 --- /dev/null +++ b/docs/source/run_fpga_task.rst @@ -0,0 +1,213 @@ +.. _run_fpga_task: + +OpenFPGA Task +--------------- + +Tasks provide a framework for running the :ref:`run_fpga_flow` on +multiple benchmarks, architectures and set of OpenFPGA parameters. +The structure of the framework is very similar to +`VTR-Tasks `_ +implementation with additional functionality and minor file extention changes. + +Task Directory +~~~~~~~~~~~~~~ + +The tasks are store in a ``TASK_DIRECTORY``, which by default points to +``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in +task directory consisting of ``../config/task.conf`` file can be reffered as a +task. + +To create as task name called ``basic_flow`` following directory has to exist:: + + ${TASK_DIRECTORY}/basic_flow/conf/task.conf + +Similarly ``regression/regression_quick`` expect following structure:: + + ${TASK_DIRECTORY}/regression/regression_quick/conf/task.conf + + +Running OpenFPGA Task: +~~~~~~~~~~~~~~~~~~~~~~ + +At a minimum ``open_fpga_flow.py`` requires following command-line arguments:: + + open_fpga_flow.py ... + +where: + + * ```` is the name of the task to run + + +Craeating A New OpenFPGA Task: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Create the folder ``${TASK_DIRECTORY}/`` and create a file called +``${TASK_DIRECTORY}//config/task.conf`` in it. + + + +Configuring a New Task +~~~~~~~~~~~~~~~~~~~~~~ + +The task configuration file ``task.conf`` consists of ``GENERAL``, +``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and +``SCRIPT_PARAM_`` sections. +Declaring all the above sections are mandatory. + +.. note:: + Configuration file supports all the OpenFPGA Variables refer + :ref:`openfpga-variables` section to know more. Variables in configuration + file is declares as ``${PATH:}`` + +General Section +^^^^^^^^^^^^^^^ + +.. option:: fpga_flow== + + Defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed. + +.. option:: power_analysis= + + Specifies whether to perform power analysis or not. + +.. option:: power_tech_file= + + Declares which tech XML file to be used while perforing Power Analysis. + +.. option:: spice_output= + + Setting up this variable generates Spice Netlist at the end of the flow. + Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow` + +.. option:: verilog_output= + + Setting up this variable generates Verilog Netlist at the end of the flow. + Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow` + +.. option:: timeout_each_job= + + Specifies the the timeout for each :ref:`run_fpga_flow` execution. Default + is set to ``20 min`` + + +Architectures Sections +^^^^^^^^^^^^^^^^^^^^^^ + + User can define the list of architecure files in this section. + +.. option:: arch= + + The ``arch_label`` variable can be any number of string without + white-spaces. ``xml_architecture_file_path`` is path to the actual XML + architecture file + +.. note:: + + In final OpenFPGA Task result the architecture will be referred by its + ``arch_label``. + +Benchmarks Sections +^^^^^^^^^^^^^^^^^^^ + + User can define the list of benchmarks files in this section. + +.. option:: bench= + + The ``bench_label`` variable can be any number of string without + white-spaces. ``xml_architecture_file_path`` is path to the actual XML + architecture file + + For Example following code shows how to define a benchmarks, + with single file multiple files and files added from specific directory. + + .. code-block:: text + + [BENCHMARKS] + # To declare single benchmark file + bench_design1=${BENCH_PATH}/design/top.v + + # To declare multiple benchmark file + bench_design2=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/sub_module.v + + # To add all files in specific directory to the benchmark + bench_design3=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/lib/*.v + +.. note:: + ``bench_label`` is referred again in ``Synthesis_Param`` section to + provide addional information about benchmark + +Synthesis Parameter Sections +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + User can define extra parameters for each benchmark defined in the + ``BENCHMARKS`` sections. + +.. option:: bench_top= + + This defines the Top Level module name for ``bench_label`` benchmark. + By default, the top level module name is cosidereed as a ``top``. + +.. option:: bench_yosys_tmpl= + + [TODO] + +.. option:: bench_chan_width= + + In case of running fixed channel width routing for each benchmark, + this option defines the channel width to be used for ``bench_label`` + benchmark + +.. option:: bench_act= + + In case of running ``blif_vpr_flow`` this option provides the activity files + to be used to generate testbench for ``bench_label`` benchmark + +.. option:: bench_verilog= + + In case of running ``blif_vpr_flow`` with verification this option provides + the source verilog design for ``bench_label`` benchmark to be used + while verification. + +Script Parameter Sections +^^^^^^^^^^^^^^^^^^^^^^^^^ +The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_`` where `parameter_set_label` can be any word without white spaces. +The section is referred with ``parameter_set_label`` in final result file. + +For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments. + +.. code-block:: text + + [SCRIPT_PARAM_Fixed_Routing_30] + # Execute fixed routing with channel with 30 + fix_route_chan_width=30 + + [SCRIPT_PARAM_Fixed_Routing_50] + # Execute fixed routing with channel with 50 + fix_route_chan_width=50 + +Example Task Configuration File +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +.. code-block:: text + + [GENERAL] + spice_output=false + verilog_output=false + power_analysis = true + power_tech_file = ${PATH:TECH_PATH}/winbond90nm/winbond90nm_power_properties.xml + timeout_each_job = 20*60 + + [ARCHITECTURES] + arch0=${PATH:ARCH_PATH}/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml + + [BENCHMARKS] + bench0=${PATH:BENCH_PATH}/MCNC_Verilog/s298/s298.v + bench1=${PATH:BENCH_PATH}/MCNC_Verilog/elliptic/elliptic.v + + [SYNTHESIS_PARAM] + bench0_top = s298 + bench1_top = elliptic + + [SCRIPT_PARAM_Slack_30] + min_route_chan_width=1.3 + + [SCRIPT_PARAM_Slack_80] + min_route_chan_width=1.8 + diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 04babac98..8125398b3 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -160,6 +160,7 @@ def generate_each_task_actions(taskname): GeneralSection = task_conf["GENERAL"] # Check if specified architecture files exist + # TODO Store it as a dictionary and take reference from the key archfile_list = [] for _, arch_file in task_conf["ARCHITECTURES"].items(): arch_full_path = arch_file From 48ec1eefcdb0b991da72d0e7893f180249b9c006 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 2 Sep 2019 02:45:05 -0600 Subject: [PATCH 162/482] Added fpga_task cmd options in doc [ci skip] --- docs/source/conf.py | 7 +- docs/source/run_fpga_flow.rst | 2 +- docs/source/run_fpga_task.rst | 89 +++++++++++++++++--------- openfpga_flow/scripts/run_fpga_task.py | 4 +- 4 files changed, 67 insertions(+), 35 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 0553bbcbd..0b149ed69 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -19,7 +19,7 @@ import shlex import sphinx_rtd_theme -# Uncomment for local build +# Uncomment for local build #html_theme = "sphinx_rtd_theme" #html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] @@ -55,7 +55,8 @@ extensions = [ 'sphinx.ext.todo', 'sphinx.ext.mathjax', 'sphinx.ext.graphviz', - 'sphinxcontrib.bibtex' + 'sphinxcontrib.bibtex', + 'sphinx.ext.autosectionlabel', ] # Add any paths that contain templates here, relative to this directory. @@ -89,7 +90,7 @@ pygments_style = 'sphinx' # If true, `todo` and `todoList` produce output, else they produce nothing. todo_include_todos = True -#Number figures for referencing +# Number figures for referencing numfig = True diff --git a/docs/source/run_fpga_flow.rst b/docs/source/run_fpga_flow.rst index 3a182f6d7..c73ebbdb9 100755 --- a/docs/source/run_fpga_flow.rst +++ b/docs/source/run_fpga_flow.rst @@ -114,7 +114,7 @@ General Arguments .. option:: --debug - To enable detail logs printing. + To enable detailed log printing. .. option:: --flow_config diff --git a/docs/source/run_fpga_task.rst b/docs/source/run_fpga_task.rst index c25527546..7e14c9d1f 100644 --- a/docs/source/run_fpga_task.rst +++ b/docs/source/run_fpga_task.rst @@ -4,17 +4,17 @@ OpenFPGA Task --------------- Tasks provide a framework for running the :ref:`run_fpga_flow` on -multiple benchmarks, architectures and set of OpenFPGA parameters. +multiple benchmarks, architectures, and set of OpenFPGA parameters. The structure of the framework is very similar to `VTR-Tasks `_ -implementation with additional functionality and minor file extention changes. +implementation with additional functionality and minor file extension changes. Task Directory ~~~~~~~~~~~~~~ -The tasks are store in a ``TASK_DIRECTORY``, which by default points to +The tasks are stored in a ``TASK_DIRECTORY``, which by default points to ``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in -task directory consisting of ``../config/task.conf`` file can be reffered as a +task directory consisting of ``../config/task.conf`` file can be referred to as a task. To create as task name called ``basic_flow`` following directory has to exist:: @@ -31,22 +31,55 @@ Running OpenFPGA Task: At a minimum ``open_fpga_flow.py`` requires following command-line arguments:: - open_fpga_flow.py ... + open_fpga_flow.py ... [] where: * ```` is the name of the task to run + * ```` Other command line arguments described below -Craeating A New OpenFPGA Task: -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Create the folder ``${TASK_DIRECTORY}/`` and create a file called -``${TASK_DIRECTORY}//config/task.conf`` in it. +Command-line Options +~~~~~~~~~~~~~~~~~~~~ + +.. option:: --maxthreads + + This option defines the number of threads to run while executing task. + Each combination of architecture, benchmark and set of OpenFPGA Flow options + runs in a individual thread. + +.. option:: --skip_thread_logs + + Passsing this option skips printing logs from each OpenFPGA Flow script run. + +.. option:: --exit_on_fail + + Passsing this option exits the OpenFPGA task script with returncode 1, + if any threads fail to execute successfully. It is mainly used to while + performing regression test. + +.. option:: --test_run + + This option allows to debug OpenFPGA Task script + by skiping actual execution of OpenFPGA flow . + Passing this option prints the list of + commnad generated to execute using OpenFPGA flow. + +.. option:: --debug + + To enable detailed log printing. +Creating a new OpenFPGA Task +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Configuring a New Task -~~~~~~~~~~~~~~~~~~~~~~ +- Create the folder ``${TASK_DIRECTORY}/`` +- Create a file ``${TASK_DIRECTORY}//config/task.conf`` in it +- Configure the task as explained in :ref:`Configuring a new OpenFPGA Task` + + +Configuring a new OpenFPGA Task +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The task configuration file ``task.conf`` consists of ``GENERAL``, ``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and @@ -54,16 +87,16 @@ The task configuration file ``task.conf`` consists of ``GENERAL``, Declaring all the above sections are mandatory. .. note:: - Configuration file supports all the OpenFPGA Variables refer - :ref:`openfpga-variables` section to know more. Variables in configuration - file is declares as ``${PATH:}`` + The configuration file supports all the OpenFPGA Variables refer + :ref:`openfpga-variables` section to know more. Variable in the configuration + file is declared as ``${PATH:}`` General Section ^^^^^^^^^^^^^^^ .. option:: fpga_flow== - Defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed. + This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed. .. option:: power_analysis= @@ -71,7 +104,7 @@ General Section .. option:: power_tech_file= - Declares which tech XML file to be used while perforing Power Analysis. + Declares which tech XML file to use while performing Power Analysis. .. option:: spice_output= @@ -85,14 +118,13 @@ General Section .. option:: timeout_each_job= - Specifies the the timeout for each :ref:`run_fpga_flow` execution. Default - is set to ``20 min`` + Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min. `` Architectures Sections ^^^^^^^^^^^^^^^^^^^^^^ - User can define the list of architecure files in this section. + User can define the list of architecture files in this section. .. option:: arch= @@ -102,7 +134,7 @@ Architectures Sections .. note:: - In final OpenFPGA Task result the architecture will be referred by its + In the final OpenFPGA Task result, the architecture will be referred by its ``arch_label``. Benchmarks Sections @@ -117,7 +149,7 @@ Benchmarks Sections architecture file For Example following code shows how to define a benchmarks, - with single file multiple files and files added from specific directory. + with a single file, multiple files and files added from a specific directory. .. code-block:: text @@ -133,17 +165,17 @@ Benchmarks Sections .. note:: ``bench_label`` is referred again in ``Synthesis_Param`` section to - provide addional information about benchmark + provide additional information about benchmark Synthesis Parameter Sections ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - User can define extra parameters for each benchmark defined in the + User can define extra parameters for each benchmark in the ``BENCHMARKS`` sections. .. option:: bench_top= - This defines the Top Level module name for ``bench_label`` benchmark. - By default, the top level module name is cosidereed as a ``top``. + This option defines the Top Level module name for ``bench_label`` benchmark. + By default, the top-level module name is considered as a ``top``. .. option:: bench_yosys_tmpl= @@ -163,13 +195,13 @@ Synthesis Parameter Sections .. option:: bench_verilog= In case of running ``blif_vpr_flow`` with verification this option provides - the source verilog design for ``bench_label`` benchmark to be used + the source Verilog design for ``bench_label`` benchmark to be used while verification. Script Parameter Sections ^^^^^^^^^^^^^^^^^^^^^^^^^ The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_`` where `parameter_set_label` can be any word without white spaces. -The section is referred with ``parameter_set_label`` in final result file. +The section is referred with ``parameter_set_label`` in the final result file. For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments. @@ -184,7 +216,7 @@ For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fi fix_route_chan_width=50 Example Task Configuration File -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. code-block:: text [GENERAL] @@ -210,4 +242,3 @@ Example Task Configuration File [SCRIPT_PARAM_Slack_80] min_route_chan_width=1.8 - diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 8125398b3..5b76d4208 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -55,7 +55,7 @@ parser.add_argument('--debug', action="store_true", help="Run script in debug mode") parser.add_argument('--exit_on_fail', action="store_true", help="Exit script with return code") -parser.add_argument('--skip_tread_logs', action="store_true", +parser.add_argument('--skip_thread_logs', action="store_true", help="Skips logs from running thread") args = parser.parse_args() @@ -364,7 +364,7 @@ def run_single_script(s, eachJob): stderr=subprocess.STDOUT, universal_newlines=True) for line in process.stdout: - if not args.skip_tread_logs: + if not args.skip_thread_logs: strip_child_logger_info(line[:-1]) sys.stdout.buffer.flush() output.write(line) From 395bf4fbdfaeb25db4ec4f87c7fe4f313e06df05 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 2 Sep 2019 14:30:18 -0600 Subject: [PATCH 163/482] refactored rram mux generation --- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 396 +++++++++++++++++- 1 file changed, 381 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 70ca6f78d..7c085ee33 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -178,7 +178,7 @@ void generate_verilog_cmos_mux_branch_body_behavioral(std::fstream& fp, /********************************************************************* * Generate Verilog codes modeling an branch circuit - * for a multiplexer with the given size + * for a CMOS multiplexer with the given size * Support structural and behavioral Verilog codes *********************************************************************/ static @@ -268,6 +268,384 @@ void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager, print_verilog_module_end(fp, module_name); } +/********************************************************************* + * Dump a structural verilog for RRAM MUX basis module + * This is only called when structural verilog dumping option is enabled for this spice model + * IMPORTANT: the structural verilog can NOT be used for functionality verification!!! + * TODO: This part is quite restricted to the way we implemented our RRAM FPGA + * Should be reworked to be more generic !!! + * + * By structural the schematic is splitted into two parts: left part and right part + * The left part includes BLB[0..N-1] and WL[0..N-1] signals as well as RRAMs + * The right part includes BLB[N] and WL[N] + * Corresponding Schematic is as follows: + * + * LEFT PART | RIGHT PART + * + * BLB[0] BLB[N] + * | | + * \|/ \|/ + * in[0] ---->RRAM[0]-----+ + * | + * BLB[1] | + * | | + * \|/ | + * in[1] ---->RRAM[1]-----+ + * |-----> out[0] + * ... + * | + * in[N-1] ---->RRAM[N-1]---+ + * /|\ /|\ + * | | + * BLB[N-1] WL[N] + * + * Working principle: + * 1. Set a RRAM[i]: enable BLB[i] and WL[N] + * 2. Reset a RRAM[i]: enable BLB[N] and WL[i] + * 3. Operation: disable all BLBs and WLs + * + * The structure is done in the way we implement the physical layout of RRAM MUX + * It is NOT the only road to the goal!!! + *********************************************************************/ +static +void generate_verilog_rram_mux_branch_body_structural(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const BasicPort& input_port, + const BasicPort& output_port, + const BasicPort& blb_port, + const BasicPort& wl_port, + const MuxGraph& mux_graph) { + std::string progTE_module_name("PROG_TE"); + std::string progBE_module_name("PROG_BE"); + + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Verilog Behavior description for a MUX */ + print_verilog_comment(fp, std::string("---- Structure-level description of RRAM MUX -----")); + + /* Print internal structure of 4T1R programming structures + * Written in structural Verilog + * The whole structure-level description is divided into two parts: + * 1. Left part consists of N PROG_TE modules, each of which + * includes a PMOS, a NMOS and a RRAM, which is actually the left + * part of a 4T1R programming structure + * 2. Right part includes only a PROG_BE module, which consists + * of a PMOS and a NMOS, which is actually the right part of a + * 4T1R programming sturcture + */ + /* Create a module for the progTE and register it in the module manager + * Structure of progTE + * + * +----------+ + * in--->| | + * BLB-->| progTE |--> out + * WL--->| | + * +----------+ + */ + ModuleId progTE_module_id = module_manager.add_module(progTE_module_name); + /* If there is already such as module inside, we just ned to find the module id */ + if (ModuleId::INVALID() == progTE_module_id) { + progTE_module_id = module_manager.find_module(progTE_module_name); + /* We should have a valid id! */ + VTR_ASSERT(ModuleId::INVALID() != progTE_module_id); + } + /* Add ports to the module */ + /* input port */ + BasicPort progTE_in_port("A", 1); + module_manager.add_port(progTE_module_id, progTE_in_port, ModuleManager::MODULE_INPUT_PORT); + /* WL port */ + BasicPort progTE_wl_port("WL", 1); + module_manager.add_port(progTE_module_id, progTE_wl_port, ModuleManager::MODULE_INPUT_PORT); + /* BLB port */ + BasicPort progTE_blb_port("BLB", 1); + module_manager.add_port(progTE_module_id, progTE_blb_port, ModuleManager::MODULE_INPUT_PORT); + /* output port */ + BasicPort progTE_out_port("Z", 1); + module_manager.add_port(progTE_module_id, progTE_out_port, ModuleManager::MODULE_INPUT_PORT); + + /* LEFT part: Verilog code generation */ + /* Iterate over the inputs */ + for (const auto& mux_input : mux_graph.inputs()) { + BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); + /* Iterate over the outputs */ + for (const auto& mux_output : mux_graph.outputs()) { + BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); + /* if there is a connection between the input and output, a tgate will be outputted */ + std::vector edges = mux_graph.find_edges(mux_input, mux_output); + /* There should be only one edge or no edge*/ + VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); + /* No need to output tgates if there are no edges between two nodes */ + if (0 == edges.size()) { + continue; + } + /* Create a port-to-port name map */ + std::map port2port_name_map; + /* input port */ + port2port_name_map[progTE_in_port.get_name()] = cur_input_port; + /* output port */ + port2port_name_map[progTE_out_port.get_name()] = cur_output_port; + /* Find the mem_id controlling the edge */ + MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); + BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_mem), size_t(mux_mem)); + BasicPort cur_wl_port(wl_port.get_name(), size_t(mux_mem), size_t(mux_mem)); + /* RRAM configuration port: there should not be any inverted edge in RRAM MUX! */ + VTR_ASSERT( false == mux_graph.is_edge_use_inv_mem(edges[0]) ); + /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ + port2port_name_map[progTE_blb_port.get_name()] = cur_blb_port; + port2port_name_map[progTE_wl_port.get_name()] = cur_wl_port; + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, progTE_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, progTE_module_id); + } + } + + /* Create a module for the progBE and register it in the module manager + * Structure of progBE + * + * +----------+ + * | | + * BLB-->| progBE |<-> out + * WL--->| | + * +----------+ + */ + ModuleId progBE_module_id = module_manager.add_module(progBE_module_name); + /* If there is already such as module inside, we just ned to find the module id */ + if (ModuleId::INVALID() == progBE_module_id) { + progBE_module_id = module_manager.find_module(progBE_module_name); + /* We should have a valid id! */ + VTR_ASSERT(ModuleId::INVALID() != progBE_module_id); + } + /* Add ports to the module */ + /* inout port */ + BasicPort progBE_inout_port("INOUT", 1); + module_manager.add_port(progBE_module_id, progBE_inout_port, ModuleManager::MODULE_INOUT_PORT); + /* WL port */ + BasicPort progBE_wl_port("WL", 1); + module_manager.add_port(progBE_module_id, progBE_wl_port, ModuleManager::MODULE_INPUT_PORT); + /* BLB port */ + BasicPort progBE_blb_port("BLB", 1); + module_manager.add_port(progBE_module_id, progBE_blb_port, ModuleManager::MODULE_INPUT_PORT); + + /* RIGHT part: Verilog code generation */ + /* Iterate over the outputs */ + for (const auto& mux_output : mux_graph.outputs()) { + BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); + /* Create a port-to-port name map */ + std::map port2port_name_map; + /* Wire the output port to the INOUT port */ + port2port_name_map[progBE_inout_port.get_name()] = cur_output_port; + /* Find the mem_id controlling the edge */ + BasicPort cur_blb_port(blb_port.get_name(), mux_graph.num_memory_bits(), mux_graph.num_memory_bits()); + BasicPort cur_wl_port(wl_port.get_name(), mux_graph.num_memory_bits(), mux_graph.num_memory_bits()); + port2port_name_map[progBE_blb_port.get_name()] = cur_blb_port; + port2port_name_map[progBE_wl_port.get_name()] = cur_wl_port; + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, progBE_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, progBE_module_id); + } +} + +/********************************************************************* + * Generate behavior-level Verilog codes modeling an branch circuit + * for a RRAM-based multiplexer with the given size + * Corresponding Schematic is as follows: + * + * BLB[0] BLB[N] + * | | + * \|/ \|/ + * in[0] ---->RRAM[0]-----+ + * | + * BLB[1] | + * | | + * \|/ | + * in[1] ---->RRAM[1]-----+ + * |-----> out[0] + * ... + * | + * in[N-1] ---->RRAM[N-1]---+ + * /|\ /|\ + * | | + * BLB[N-1] WL[N] + * + * Working principle: + * 1. Set a RRAM[i]: enable BLB[i] and WL[N] + * 2. Reset a RRAM[i]: enable BLB[N] and WL[i] + * 3. Operation: disable all BLBs and WLs + * + * TODO: Elaborate the codes to output the circuit logic + * following the mux_graph! + *********************************************************************/ +static +void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const BasicPort& input_port, + const BasicPort& output_port, + const BasicPort& blb_port, + const BasicPort& wl_port, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Verilog Behavior description for a MUX */ + print_verilog_comment(fp, std::string("---- Behavioral-level description of RRAM MUX -----")); + + /* Add an internal register for the output */ + BasicPort outreg_port("out_reg", mux_graph.num_inputs()); + /* Print the port */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, outreg_port) << ";" << std::endl; + + /* Print the internal logics */ + fp << "\t" << "always @("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, blb_port) << ";" << std::endl; + fp << ", "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port) << ";" << std::endl; + fp << ")" << std::endl; + fp << "\t" << "begin" << std::endl; + + /* Only when the last bit of wl is enabled, + * the propagating path can be changed + * (RRAM value can be changed) */ + fp << "\t\t" << "if ("; + BasicPort set_enable_port(wl_port.get_name(), wl_port.get_width() - 1, wl_port.get_width() - 1); + fp << generate_verilog_port(VERILOG_PORT_CONKT, set_enable_port); + /* We need two config-enable ports: prog_EN and prog_ENb */ + bool find_prog_EN = false; + bool find_prog_ENb = false; + for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) { + /* Bypass non-config-enable ports */ + if (false == circuit_lib.port_is_config_enable(port)) { + continue; + } + /* Reach here, the port should be is_config_enable */ + /* Create a port object */ + fp << " && "; + BasicPort prog_en_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); + if ( 1 == circuit_lib.port_default_value(port)) { + /* Default value = 0 means that this is a prog_EN port */ + fp << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port); + find_prog_EN = true; + } else { + /* Default value = 1 means that this is a prog_ENb port, add inversion in the if condition */ + fp << "(~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port) << ")"; + find_prog_ENb = true; + } + } + /* Check if we find any config_enable signals */ + if (false == find_prog_EN) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Unable to find a config_enable signal with default value 0 for a RRAM MUX (%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + if (false == find_prog_ENb) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Unable to find a config_enable signal with default value 1 for a RRAM MUX (%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + + /* Finish the if clause */ + fp << ") begin" << std::endl; + + for (const auto& mux_input : mux_graph.inputs()) { + fp << "\t\t" << "if (1 == "; + /* Create a temp port of a BLB bit */ + BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); + fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_blb_port); + fp << ") begin" << std::endl; + fp << "\t\t\t" << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port); + fp << " = " << size_t(mux_graph.input_id(mux_input)) << ";" << std::endl; + fp << "\t\t" << "end else " << std::endl; + } + fp << "\t\t\t" << "begin" << std::endl; + fp << "\t\t\t\t" << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port); + fp << " = 0;" << std::endl; + fp << "\t\t\t" << "end" << std::endl; + fp << "\t\t" << "end" << std::endl; + fp << "\t" << "end" << std::endl; + + fp << "\t" << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << " = "; + fp << input_port.get_name() << "["; + fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port); + fp << "];" << std::endl; +} + +/********************************************************************* + * Generate Verilog codes modeling an branch circuit + * for a RRAM-based multiplexer with the given size + * Support structural and behavioral Verilog codes + *********************************************************************/ +static +void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& circuit_model, + const std::string& module_name, + const MuxGraph& mux_graph, + const bool& use_structural_verilog) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of inputs */ + size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == num_outputs); + /* MUX graph must have only 1 level*/ + VTR_ASSERT(1 == mux_graph.num_levels()); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add programming enable/disable ports */ + /* Add each input port */ + BasicPort input_port("in", num_inputs); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort output_port("out", num_outputs); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add RRAM programming ports */ + BasicPort blb_port("bl", num_mems); + module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort wl_port("wl", num_mems); + module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + + /* Print the internal logic in either structural or behavioral Verilog codes */ + if (true == use_structural_verilog) { + generate_verilog_rram_mux_branch_body_structural(module_manager, circuit_lib, fp, module_id, circuit_model, input_port, output_port, blb_port, wl_port, mux_graph); + } else { + generate_verilog_rram_mux_branch_body_behavioral(fp, circuit_lib, circuit_model, input_port, output_port, blb_port, wl_port, mux_graph); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + /*********************************************** * Generate Verilog codes modeling an branch circuit * for a multiplexer with the given size @@ -288,18 +666,8 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, circuit_lib.dump_structural_verilog(circuit_model)); break; case SPICE_MODEL_DESIGN_RRAM: - /* If requested, we can dump structural verilog for basis module */ - /* - if (true == circuit_lib.dump_structural_verilog(circuit_model)) { - dump_verilog_rram_mux_one_basis_module_structural(fp, mux_basis_subckt_name, - num_input_basis_subckt, - cur_spice_model); - } else { - dump_verilog_rram_mux_one_basis_module(fp, mux_basis_subckt_name, - num_input_basis_subckt, - cur_spice_model); - } - */ + generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph, + circuit_lib.dump_structural_verilog(circuit_model)); break; default: vpr_printf(TIO_MESSAGE_ERROR, @@ -307,8 +675,6 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } - - return; } /*********************************************** From d2d750a15cb321960e979cc8e4ec769614f3dbbf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 2 Sep 2019 16:21:29 -0600 Subject: [PATCH 164/482] debugged rram mux branch Verilog generation --- ...am_memory_bank_SC_winbond90_behavioral.xml | 524 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 48 +- 2 files changed, 556 insertions(+), 16 deletions(-) create mode 100644 openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml diff --git a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml new file mode 100644 index 000000000..0e39ccc08 --- /dev/null +++ b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml @@ -0,0 +1,524 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + 2.094e-09 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 7c085ee33..885a322db 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -507,11 +507,11 @@ void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp, /* Print the internal logics */ fp << "\t" << "always @("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, blb_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_CONKT, blb_port); fp << ", "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port) << ";" << std::endl; - fp << ")" << std::endl; - fp << "\t" << "begin" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port); + fp << ")"; + fp << " begin" << std::endl; /* Only when the last bit of wl is enabled, * the propagating path can be changed @@ -531,11 +531,12 @@ void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp, /* Create a port object */ fp << " && "; BasicPort prog_en_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - if ( 1 == circuit_lib.port_default_value(port)) { + if ( 0 == circuit_lib.port_default_value(port)) { /* Default value = 0 means that this is a prog_EN port */ fp << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port); find_prog_EN = true; } else { + VTR_ASSERT ( 1 == circuit_lib.port_default_value(port)); /* Default value = 1 means that this is a prog_ENb port, add inversion in the if condition */ fp << "(~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port) << ")"; find_prog_ENb = true; @@ -559,19 +560,23 @@ void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp, fp << ") begin" << std::endl; for (const auto& mux_input : mux_graph.inputs()) { - fp << "\t\t" << "if (1 == "; + /* First if clause need tabs */ + if ( 0 == size_t(mux_graph.input_id(mux_input)) ) { + fp << "\t\t\t"; + } + fp << "if (1 == "; /* Create a temp port of a BLB bit */ BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_blb_port); fp << ") begin" << std::endl; - fp << "\t\t\t" << "assign "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port); + fp << "\t\t\t\t" << "assign "; + fp << outreg_port.get_name(); fp << " = " << size_t(mux_graph.input_id(mux_input)) << ";" << std::endl; - fp << "\t\t" << "end else " << std::endl; + fp << "\t\t\t" << "end else "; } - fp << "\t\t\t" << "begin" << std::endl; + fp << "begin" << std::endl; fp << "\t\t\t\t" << "assign "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port); + fp << outreg_port.get_name(); fp << " = 0;" << std::endl; fp << "\t\t\t" << "end" << std::endl; fp << "\t\t" << "end" << std::endl; @@ -581,7 +586,7 @@ void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); fp << " = "; fp << input_port.get_name() << "["; - fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port); + fp << outreg_port.get_name(); fp << "];" << std::endl; } @@ -618,18 +623,28 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId module_id = module_manager.add_module(module_name); VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ - /* Add programming enable/disable ports */ + /* Add each global programming enable/disable ports */ + std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + for (const auto& port : prog_enable_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } /* Add each input port */ BasicPort input_port("in", num_inputs); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); /* Add each output port */ BasicPort output_port("out", num_outputs); module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Add RRAM programming ports */ - BasicPort blb_port("bl", num_mems); + /* Add RRAM programming ports, + * RRAM MUXes require one more pair of BLB and WL + * to configure the memories. See schematic for details + */ + BasicPort blb_port("blb", num_mems + 1); module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort wl_port("wl", num_mems); + BasicPort wl_port("wl", num_mems + 1); module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); /* dump module definition + ports */ @@ -718,6 +733,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph.num_inputs(), branch_mux_graph); } + /* TODO: create MUX modules */ } /* Dump MUX graph one by one */ From a8c803f08f7cafd50869025c4c0f1fa4c911ff75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 2 Sep 2019 16:37:43 -0600 Subject: [PATCH 165/482] try to fix bugs in explicit port mapping --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index fc36ffff6..90690e48d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -1306,6 +1306,19 @@ void fpga_x2p_free(t_arch* Arch) { free_spice_model_routing_index_low_high(Arch->spice->num_spice_model, Arch->spice->spice_models); } +/******************************************************* + * This function will force the flag of + * dump_explicit_port_map to be true + * for all the circuit models in the circuit library + ******************************************************/ +static +void overwrite_circuit_library_dump_explicit_port_map(t_arch* Arch) { + /* Iterate over all the circuit models */ + for (const auto& circuit_model : Arch->spice->circuit_lib.models()) { + Arch->spice->circuit_lib.set_model_dump_explicit_port_map(circuit_model, true); + } +} + /* Top-level function of FPGA-SPICE setup */ void fpga_x2p_setup(t_vpr_setup vpr_setup, t_arch* Arch) { @@ -1329,8 +1342,14 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, * Initialize Arch SPICE MODELS */ init_check_arch_spice_models(Arch, &(vpr_setup.RoutingArch)); + /* Link circuit models to architecture */ link_circuit_library_to_arch(Arch, &(vpr_setup.RoutingArch)); + /* Overwrite explicit_port_map settings if user required */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog) { + vpr_printf(TIO_MESSAGE_INFO, "Detect explicit Verilog option is enabled. Force all the circuit models to dump explicit Verilog...\n"); + overwrite_circuit_library_dump_explicit_port_map(Arch); + } /* Initialize idle mode and physical mode of each pb_type and pb_graph_node */ init_check_arch_pb_type_idle_and_phy_mode(); From 37439578db5ac68b5a15e60679d8961b9d39944d Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 3 Sep 2019 10:32:14 -0600 Subject: [PATCH 166/482] Removed OSX package installer to test --- .travis/common.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/common.sh b/.travis/common.sh index d5a157049..ba667700e 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -36,7 +36,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / + # sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From f862ac02c8d0f18e6bdb2744c075d0bf39f28954 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 3 Sep 2019 11:05:10 -0600 Subject: [PATCH 167/482] Restored OSX header installation [ci skip] --- .travis/common.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/common.sh b/.travis/common.sh index ba667700e..d5a157049 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -36,7 +36,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - # sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / + sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From 4d183a3fe49557209f69236292a3e1b5ba844dfa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 3 Sep 2019 16:59:03 -0600 Subject: [PATCH 168/482] start developing mux Verilog module generation --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 9 + vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 19 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 163 +++++++++++++++++- 4 files changed, 187 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index a423e5409..916627edb 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -178,6 +178,15 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& model_id return buffer_existence_[model_id][LUT_INTER_BUFFER]; } +/* Return a flag showing if a LUT circuit model uses fracturable structure */ +bool CircuitLibrary::is_lut_fracturable(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is LUT */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + return lut_is_fracturable_[model_id]; +} + /* Find the id of pass-gate circuit model * Two cases to be considered: * 1. this is a pass-gate circuit model, just find the data and return diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index a638ea8d1..885834009 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -225,6 +225,7 @@ class CircuitLibrary { bool is_output_buffered(const CircuitModelId& model_id) const; /* LUT-related information */ bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; + bool is_lut_fracturable(const CircuitModelId& model_id) const; /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 769a49dad..0ae5ed5a2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -9,15 +9,28 @@ /************************************************ * Generate the module name for a multiplexer in Verilog format + * Different circuit model requires different names: + * 1. LUTs are named as _mux + * 2. MUXes are named as _size ***********************************************/ std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, const std::string& postfix) { std::string module_name = circuit_lib.model_name(circuit_model); - module_name += "_size"; - module_name += std::to_string(mux_size); - module_name += postfix; + /* Check the model type and give different names */ + if (SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) { + module_name += "_size"; + module_name += std::to_string(mux_size); + } else { + VTR_ASSERT(SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)); + module_name += "_mux"; + } + + /* Add postfix if it is not empty */ + if (!postfix.empty()) { + module_name += postfix; + } return module_name; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 885a322db..bc33c72bb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -692,6 +692,160 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, } } +/********************************************************************* + * Generate Verilog codes modeling a CMOS multiplexer with the given size + * The Verilog module will consist of three parts: + * 1. instances of the branch circuits of multiplexers which are generated before + * This builds up the multiplexing structure + * 2. Input buffers/inverters + * 3. Output buffers/inverters + *********************************************************************/ +static +void generate_verilog_cmos_mux_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& circuit_model, + const std::string& module_name, + const MuxGraph& mux_graph) { + /* Get the global ports required by MUX (and any submodules) */ + std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the sram ports from the mux */ + std::vector mux_sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); + + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Generate the Verilog netlist according to the mux_graph */ + /* TODO: Find out the number of data-path inputs */ + size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == mux_input_ports.size()); + VTR_ASSERT(1 == mux_input_ports.size()); + VTR_ASSERT(1 == num_outputs); + /* A quick check on the model ports */ + if ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) + || ((SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) + && (false == circuit_lib.is_lut_fracturable(circuit_model))) ) { + VTR_ASSERT(1 == mux_output_ports.size()); + VTR_ASSERT(1 == circuit_lib.port_size(mux_output_ports[0])); + } else { + VTR_ASSERT_SAFE( (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) + && (true == circuit_lib.is_lut_fracturable(circuit_model)) ); + for (const auto& port : mux_output_ports) { + VTR_ASSERT(0 < circuit_lib.port_size(port)); + } + } + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ + for (const auto& port : mux_global_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port + * Treat MUX and LUT differently + * 1. MUXes: we do not have a specific input sizes, it is inferred by architecture + * 2. LUTes: we do have a specific input sizes + */ + for (const auto& port : mux_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + input_port.set_width(circuit_lib.port_size(port)); + } + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Add each output port + * Treat MUX and LUT differently + * 1. MUXes: we do not have a specific output sizes, it is inferred by architecture + * 2. LUTes: we do have a specific input sizes + */ + for (const auto& port : mux_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + output_port.set_width(circuit_lib.port_size(port)); + } + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + /* Add each memory port */ + size_t sram_port_cnt = 0; + for (const auto& port : mux_sram_ports) { + /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules + * Here we just bypass it. + */ + if (true == circuit_lib.port_is_mode_select(port)) { + continue; + } + BasicPort mem_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), num_mems); + module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + /* Update counter */ + sram_port_cnt++; + } + /* Double check: We should have only 1 sram port outputted here! */ + VTR_ASSERT(1 == sram_port_cnt); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + + /* TODO: Print the internal logic in Verilog codes */ + /* TODO: Print the Multiplexing structure in Verilog codes */ + /* TODO: Print the input buffers in Verilog codes */ + /* TODO: Print the output buffers in Verilog codes */ + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + + +/*********************************************** + * Generate Verilog codes modeling a multiplexer + * with the given graph-level description + **********************************************/ +static +void generate_verilog_mux_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_graph.num_inputs(), std::string("")); + + /* Multiplexers built with different technology is in different organization */ + switch (circuit_lib.design_tech_type(circuit_model)) { + case SPICE_MODEL_DESIGN_CMOS: + /* SRAM-based Multiplexer Verilog module generation */ + generate_verilog_cmos_mux_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* TODO: RRAM-based Multiplexer Verilog module generation */ + /* + generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph, + circuit_lib.dump_structural_verilog(circuit_model)); + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } +} + + /*********************************************** * Generate Verilog modules for all the unique * multiplexers in the FPGA device @@ -733,10 +887,15 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph.num_inputs(), branch_mux_graph); } - /* TODO: create MUX modules */ } - /* Dump MUX graph one by one */ + /* Generate unique Verilog modules for the multiplexers */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* Create MUX circuits */ + generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph); + } /* Close the file steam */ fp.close(); From b6bb433edccf5c89a465510faba5e838ddceb19e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 3 Sep 2019 18:09:21 -0600 Subject: [PATCH 169/482] bug fixing for datapath mux size in Verilog generation --- vpr7_x2p/vpr/SRC/device/mux_library.h | 2 +- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 28 +++++++++++++- vpr7_x2p/vpr/SRC/device/mux_utils.h | 5 ++- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 38 ++++++++++--------- 4 files changed, 52 insertions(+), 21 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h index 8f4ec71d8..93e004252 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.h +++ b/vpr7_x2p/vpr/SRC/device/mux_library.h @@ -27,7 +27,7 @@ class MuxLibrary { const MuxGraph& mux_graph(const MuxId& mux_id) const; /* Get a mux circuit model id */ CircuitModelId mux_circuit_model(const MuxId& mux_id) const; - /* Find the maximum mux size */ + /* Find the mux sizes */ size_t max_mux_size() const; public: /* Public mutators */ /* Add a mux to the library */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index f7eb9932c..e6390561d 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -17,6 +17,32 @@ bool valid_mux_implementation_num_inputs(const size_t& mux_size) { return (2 <= mux_size); } +/************************************************** + * Find the actual number of datapath inputs for a multiplexer implementation + * 1. if there are no requirements on constant inputs, mux_size is the actual one + * 2. if there exist constant inputs, mux_size should minus 1 + * This function is mainly used to recover the number of datapath inputs + * for MUXGraphs which is a generic representation without labelling datapath inputs + *************************************************/ +size_t find_mux_num_datapath_inputs(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size) { + /* Should be either MUX or LUT + * LUTs do have an tree-like MUX, but there is no need for a constant input! + */ + VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); + + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + return mux_size; + } + + if (true == circuit_lib.mux_add_const_input(circuit_model)) { + return mux_size - 1; + } + return mux_size; +} + /************************************************** * Find the actual number of inputs for a multiplexer implementation * 1. if there are no requirements on constant inputs, mux_size is the actual one @@ -31,7 +57,7 @@ size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { return mux_size; } diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index 730109957..304e2d375 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -12,11 +12,14 @@ bool valid_mux_implementation_num_inputs(const size_t& mux_size); +size_t find_mux_num_datapath_inputs(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size); + size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); - enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index bc33c72bb..43c7072db 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -15,6 +15,7 @@ #include "module_manager.h" #include "physical_types.h" #include "vpr_types.h" +#include "mux_utils.h" /* FPGA-X2P context header files */ #include "spice_types.h" @@ -720,8 +721,8 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, check_file_handler(fp); /* Generate the Verilog netlist according to the mux_graph */ - /* TODO: Find out the number of data-path inputs */ - size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of data-path inputs */ + size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); /* Find out the number of outputs */ size_t num_outputs = mux_graph.num_outputs(); /* Find out the number of memory bits */ @@ -758,21 +759,21 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, } /* Add each input port * Treat MUX and LUT differently - * 1. MUXes: we do not have a specific input sizes, it is inferred by architecture - * 2. LUTes: we do have a specific input sizes + * 1. MUXes: we do not have a specific input/output sizes, it is inferred by architecture + * 2. LUTes: we do have specific input/output sizes, + * but the inputs of MUXes are the SRAM ports of LUTs + * and the SRAM ports of MUXes are the inputs of LUTs */ + size_t input_port_cnt = 0; for (const auto& port : mux_input_ports) { BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - input_port.set_width(circuit_lib.port_size(port)); - } module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Update counter */ + input_port_cnt++; } - /* Add each output port - * Treat MUX and LUT differently - * 1. MUXes: we do not have a specific output sizes, it is inferred by architecture - * 2. LUTes: we do have a specific input sizes - */ + /* Double check: We should have only 1 input port generated here! */ + VTR_ASSERT(1 == input_port_cnt); + for (const auto& port : mux_output_ports) { BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { @@ -780,7 +781,7 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, } module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); } - /* Add each memory port */ + size_t sram_port_cnt = 0; for (const auto& port : mux_sram_ports) { /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules @@ -796,9 +797,7 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, /* Update counter */ sram_port_cnt++; } - /* Double check: We should have only 1 sram port outputted here! */ - VTR_ASSERT(1 == sram_port_cnt); - + /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); @@ -822,7 +821,9 @@ void generate_verilog_mux_module(ModuleManager& module_manager, std::fstream& fp, const CircuitModelId& circuit_model, const MuxGraph& mux_graph) { - std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_graph.num_inputs(), std::string("")); + std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, + find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), + std::string("")); /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { @@ -885,7 +886,8 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ for (auto branch_mux_graph : branch_mux_graphs) { generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, - mux_graph.num_inputs(), branch_mux_graph); + find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), + branch_mux_graph); } } From fde9c8b4ec259f0fad9ffd793e1f21c185f7e347 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 3 Sep 2019 23:19:24 -0600 Subject: [PATCH 170/482] add frac_lut outputs to mux_graph generation --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 14 ++++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 2 + vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 73 +++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_graph.h | 4 + .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 2 - 5 files changed, 93 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 916627edb..8514d4bf5 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -662,6 +662,20 @@ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { return port_is_prog_[circuit_port_id]; } +/* Return which level the output port locates at a LUT multiplexing structure */ +size_t CircuitLibrary::port_lut_frac_level(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_lut_frac_level_[circuit_port_id]; +} + +/* Return indices of internal nodes in a LUT multiplexing structure to which the output port is wired to */ +std::vector CircuitLibrary::port_lut_output_masks(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_lut_output_masks_[circuit_port_id]; +} + /* Return the id of parent circuit model for a circuit port */ CircuitModelId CircuitLibrary::port_parent_model(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 885834009..51030ac90 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -270,6 +270,8 @@ class CircuitLibrary { bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; + size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; + std::vector port_lut_output_masks(const CircuitPortId& circuit_port_id) const; CircuitModelId port_parent_model(const CircuitPortId& circuit_port_id) const; std::string model_name(const CircuitPortId& port_id) const; public: /* Public Accessors: Timing graph */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 281747188..c6bfb452a 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -203,6 +203,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Add output nodes to subgraph */ MuxNodeId to_node_subgraph = mux_graph.add_node(MUX_OUTPUT_NODE); mux_graph.node_levels_[to_node_subgraph] = 1; + mux_graph.node_ids_at_level_[to_node_subgraph] = 0; mux_graph.node_output_ids_[to_node_subgraph] = MuxOutputId(0); /* Update the node-to-node map */ node2node_map[root_node] = to_node_subgraph; @@ -216,6 +217,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { MuxNodeId from_node_subgraph = mux_graph.add_node(MUX_INPUT_NODE); /* Configure the nodes */ mux_graph.node_levels_[from_node_subgraph] = 0; + mux_graph.node_ids_at_level_[from_node_subgraph] = input_cnt; mux_graph.node_input_ids_[from_node_subgraph] = MuxInputId(input_cnt); input_cnt++; /* Update the node-to-node map */ @@ -385,6 +387,7 @@ MuxNodeId MuxGraph::add_node(const enum e_mux_graph_node_type& node_type) { node_input_ids_.push_back(MuxInputId::INVALID()); node_output_ids_.push_back(MuxOutputId::INVALID()); node_levels_.push_back(-1); + node_ids_at_level_.push_back(-1); node_in_edges_.emplace_back(); node_out_edges_.emplace_back(); @@ -523,6 +526,7 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, * Last level should expand from output_node * Other levels will expand from internal nodes! */ + size_t node_cnt_per_level = 0; /* A counter to record node indices at each level */ for (MuxNodeId seed_node : node_lookup[lvl + 1]) { /* Add a new node and connect to seed_node, until we reach the num_inputs_per_branch */ for (size_t i = 0; i < num_inputs_per_branch; ++i) { @@ -533,6 +537,9 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, /* Node level is deterministic */ node_levels_[expand_node] = lvl; + node_ids_at_level_[expand_node] = node_cnt_per_level; + /* update level node counter */ + node_cnt_per_level++; /* Create an edge and connect the two nodes */ MuxEdgeId edge = add_edge(expand_node, seed_node); @@ -624,6 +631,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, */ MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); node_levels_[output_node] = 1; + node_ids_at_level_[output_node] = 0; node_output_ids_[output_node] = MuxOutputId(0); for (size_t i = 0; i < mux_size; ++i) { @@ -631,6 +639,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, /* All the node belong to level 0 (we have only 1 level) */ node_input_ids_[input_node] = MuxInputId(i); node_levels_[input_node] = 0; + node_ids_at_level_[input_node] = i; /* We definitely know how many edges we need, * the same as mux_size, add a edge connecting two nodes @@ -647,6 +656,64 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, /* Finish building the graph for a one-level multiplexer */ } +/* Convert some internal nodes to be additional outputs + * according to the fracturable LUT port definition + * We will iterate over each output port of a circuit model + * and find the frac_level and output_mask + * Then, the internal nodes at the frac_level will be converted + * to output nodes with a given output_mask + */ +void MuxGraph::add_fracturable_outputs(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Iterate over output ports */ + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true)) { + /* Get the fracturable_level */ + size_t frac_level = circuit_lib.port_lut_frac_level(port); + /* Bypass invalid frac_level */ + if (size_t(-1) == frac_level) { + continue; + } + /* Iterate over output masks */ + for (const auto& output_idx : circuit_lib.port_lut_output_masks(port)) { + size_t num_matched_nodes = 0; + /* Iterate over node and find the internal nodes, which match the frac_level and output_idx */ + for (const auto& node : node_lookup_[frac_level][MUX_INTERNAL_NODE]) { + if (node_ids_at_level_[node] != output_idx) { + /* Bypass condition */ + continue; + } + /* Reach here, this is the node we want + * Convert it to output nodes and update the counter + */ + node_types_[node] = MUX_OUTPUT_NODE; + node_output_ids_[node] = MuxOutputId(num_outputs()); + num_matched_nodes++; + } + /* Either find 1 or 0 matched nodes */ + if (0 != num_matched_nodes) { + /* We should find only one node that matches! */ + VTR_ASSERT(1 == num_matched_nodes); + /* Rebuild the node look-up */ + build_node_lookup(); + continue; /* Finish here, go to next */ + } + /* Sometime the wanted node is already an output, do a double check */ + for (const auto& node : node_lookup_[frac_level][MUX_OUTPUT_NODE]) { + if (node_ids_at_level_[node] != output_idx) { + /* Bypass condition */ + continue; + } + /* Reach here, this is the node we want + * Just update the counter + */ + num_matched_nodes++; + } + /* We should find only one node that matches! */ + VTR_ASSERT(1 == num_matched_nodes); + } + } +} + /* Build the graph for a given multiplexer model */ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, @@ -699,6 +766,12 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, /* Since the graph is finalized, it is time to build the fast look-up */ build_node_lookup(); + + /* For fracturable LUTs, we need to add more outputs to the MUX graph */ + if ( (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) + && (true == circuit_lib.is_lut_fracturable(circuit_model)) ) { + add_fracturable_outputs(circuit_lib, circuit_model); + } } /* Build fast node lookup */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 10f758809..3d676d40a 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -110,6 +110,9 @@ class MuxGraph { void build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); + /* Convert some internal node to outputs according to fracturable LUT circuit design specifications */ + void add_fracturable_outputs(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); /* Build fast node lookup */ void build_node_lookup(); private: /* Private validators */ @@ -130,6 +133,7 @@ class MuxGraph { vtr::vector node_input_ids_; /* Unique ids for each node as an input of the MUX */ vtr::vector node_output_ids_; /* Unique ids for each node as an input of the MUX */ vtr::vector node_levels_; /* at which level, each node belongs to */ + vtr::vector node_ids_at_level_; /* the index at the level that each node belongs to */ vtr::vector> node_in_edges_; /* ids of incoming edges to each node */ vtr::vector> node_out_edges_; /* ids of outgoing edges from each node */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 43c7072db..6bb4b08b5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -732,7 +732,6 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, /* MUX graph must have only 1 output */ VTR_ASSERT(1 == mux_input_ports.size()); VTR_ASSERT(1 == mux_input_ports.size()); - VTR_ASSERT(1 == num_outputs); /* A quick check on the model ports */ if ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) || ((SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) @@ -810,7 +809,6 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, print_verilog_module_end(fp, module_name); } - /*********************************************** * Generate Verilog codes modeling a multiplexer * with the given graph-level description From e623c19055952560f41252d78e24b8f41279a4b4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 4 Sep 2019 23:54:53 -0600 Subject: [PATCH 171/482] implementing mux Verilog generation. Bugs detected, fixing ongoing --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 16 ++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 59 +++++ vpr7_x2p/vpr/SRC/device/mux_graph.h | 13 ++ vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 28 +++ vpr7_x2p/vpr/SRC/device/mux_utils.h | 4 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 21 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 3 + .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 23 ++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 5 + .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 212 +++++++++++++++++- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 110 ++++++++- .../fpga_x2p/verilog/verilog_writer_utils.h | 4 + 13 files changed, 496 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 8514d4bf5..d2aca01c3 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -298,6 +298,22 @@ size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const { return buffer_num_levels_[model_id]; } +/* Return the location map of intermediate buffers + * that are inserted inside LUT multiplexing structures + */ +std::string CircuitLibrary::lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + /* if we have an intermediate buffer, we return something, otherwise return an empty map */ + if (true == is_lut_intermediate_buffered(model_id)) { + return buffer_location_maps_[model_id][LUT_INTER_BUFFER]; + } else { + return std::string(); + } +} + /* Return the number of levels of delay types for a circuit model */ size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const { /* validate the model_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 51030ac90..a2f5eab95 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -239,6 +239,7 @@ class CircuitLibrary { /* Buffer information */ enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const; size_t buffer_num_levels(const CircuitModelId& model_id) const; + std::string lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const; /* Delay information */ size_t num_delay_info(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index c6bfb452a..6656edca3 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -43,6 +43,20 @@ MuxGraph::node_range MuxGraph::nodes() const { return vtr::make_range(node_ids_.begin(), node_ids_.end()); } +/* Find the non-input nodes */ +std::vector MuxGraph::non_input_nodes() const { + std::vector node_list; + for (const auto& node : nodes()) { + /* Bypass any nodes which are not OUTPUT and INTERNAL */ + if (MUX_INPUT_NODE == node_types_[node]) { + continue; + } + /* Reach here, this is either an OUTPUT or INTERNAL node */ + node_list.push_back(node); + } + return node_list; +} + MuxGraph::edge_range MuxGraph::edges() const { return vtr::make_range(edge_ids_.begin(), edge_ids_.end()); } @@ -137,6 +151,47 @@ size_t MuxGraph::num_memory_bits() const { return mem_ids_.size(); } +/* Find the number of nodes at a given level in the MUX graph */ +size_t MuxGraph::num_nodes_at_level(const size_t& level) const { + /* validate the level numbers */ + VTR_ASSERT_SAFE(valid_level(level)); + VTR_ASSERT_SAFE(valid_mux_graph()); + + size_t num_nodes = 0; + for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) { + num_nodes += node_lookup_[level][node_type].size(); + } + return num_nodes; +} + +/* Find the level of a node */ +size_t MuxGraph::node_level(const MuxNodeId& node) const { + /* validate the node */ + VTR_ASSERT(valid_node_id(node)); + return node_levels_[node]; +} + +/* Find the index of a node at its level */ +size_t MuxGraph::node_index_at_level(const MuxNodeId& node) const { + /* validate the node */ + VTR_ASSERT(valid_node_id(node)); + return node_ids_at_level_[node]; +} + +/* Find the input edges for a node */ +std::vector MuxGraph::node_in_edges(const MuxNodeId& node) const { + /* validate the node */ + VTR_ASSERT(valid_node_id(node)); + return node_in_edges_[node]; +} + +/* Find the input nodes for a edge */ +std::vector MuxGraph::edge_src_nodes(const MuxEdgeId& edge) const { + /* validate the edge */ + VTR_ASSERT(valid_edge_id(edge)); + return edge_src_nodes_[edge]; +} + /* Find the mem that control the edge */ MuxMemId MuxGraph::find_edge_mem(const MuxEdgeId& edge) const { /* validate the edge */ @@ -846,6 +901,10 @@ bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const { return true; } +bool MuxGraph::valid_level(const size_t& level) const { + return level < num_levels(); +} + bool MuxGraph::valid_node_lookup() const { return node_lookup_.empty(); } diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 3d676d40a..7e1e7d128 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -58,6 +58,8 @@ class MuxGraph { MuxGraph(); public: /* Public accessors: Aggregates */ node_range nodes() const; + /* Find the non-input nodes */ + std::vector non_input_nodes() const; edge_range edges() const; mem_range memories() const; public: /* Public accessors: Data query */ @@ -73,6 +75,16 @@ class MuxGraph { size_t num_levels() const; /* Find the number of SRAMs in the MUX graph */ size_t num_memory_bits() const; + /* Find the number of nodes at a given level in the MUX graph */ + size_t num_nodes_at_level(const size_t& level) const; + /* Find the level of a node */ + size_t node_level(const MuxNodeId& node) const; + /* Find the index of a node at its level */ + size_t node_index_at_level(const MuxNodeId& node) const; + /* Find the input edges for a node */ + std::vector node_in_edges(const MuxNodeId& node) const; + /* Find the input nodes for a edge */ + std::vector edge_src_nodes(const MuxEdgeId& edge) const; /* Find the mem that control the edge */ MuxMemId find_edge_mem(const MuxEdgeId& edge) const; /* Identify if the edge is controlled by the inverted output of a mem */ @@ -122,6 +134,7 @@ class MuxGraph { bool valid_mem_id(const MuxMemId& mem) const; bool valid_input_id(const MuxInputId& input_id) const; bool valid_output_id(const MuxOutputId& output_id) const; + bool valid_level(const size_t& level) const; /* validate/invalidate node lookup */ bool valid_node_lookup() const; void invalidate_node_lookup(); diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index e6390561d..c15e3081f 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -150,6 +150,34 @@ size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, return num_input_per_unit; } +/************************************************** + * Find if there is an intermediate buffer + * locating at the multiplexing structure of a LUT + *************************************************/ +bool require_intermediate_buffer_at_mux_level(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& node_level) { + std::string intermediate_buffer_location_map; + + /* ONLY for LUTs: intermediate buffers may exist if specified */ + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + intermediate_buffer_location_map = circuit_lib.lut_intermediate_buffer_location_map(circuit_model); + } + /* If no location map is specified, we can return here */ + if (intermediate_buffer_location_map.empty()) { + return false; + } + /* We have a location map. Make sure we are in the range */ + if (node_level >= intermediate_buffer_location_map.length()) { + return false; + } + /* '1' indicates that the location is needed */ + if ('1' == intermediate_buffer_location_map[node_level]) { + return true; + } + return false; +} + /************************************************** * Convert a linked list of MUX architecture to MuxLibrary * TODO: this function will be deleted when MUXLibrary fully diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index 304e2d375..b4a20ebe4 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -29,6 +29,10 @@ size_t find_treelike_mux_num_levels(const size_t& mux_size); size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, const size_t& mux_level); +bool require_intermediate_buffer_at_mux_level(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& node_level); + MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 0ae5ed5a2..2f5cfa917 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -7,6 +7,27 @@ #include "fpga_x2p_naming.h" +/************************************************ + * Generate the node name for a multiplexing structure + * Case 1 : If there is an intermediate buffer followed by, + * the node name will be mux_l_in_buf + * Case 1 : If there is NO intermediate buffer followed by, + * the node name will be mux_l_in + ***********************************************/ +std::string generate_verilog_mux_node_name(const size_t& node_level, + const bool& add_buffer_postfix) { + /* Generate the basic node_name */ + std::string node_name = "mux_l" + std::to_string(node_level) + "_in"; + + /* Add a postfix upon requests */ + if (true == add_buffer_postfix) { + /* '1' indicates that the location is needed */ + node_name += "_buf"; + } + + return node_name; +} + /************************************************ * Generate the module name for a multiplexer in Verilog format * Different circuit model requires different names: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index bd67c61f4..3acf3574d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -11,6 +11,9 @@ #include "circuit_library.h" +std::string generate_verilog_mux_node_name(const size_t& node_level, + const bool& add_buffer_postfix); + std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 5b56823c1..f634af951 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -50,6 +50,29 @@ std::vector ModuleManager::module_ports_by_type(const ModuleId& modul return ports; } +/* Find a port of a module by a given name */ +ModulePortId ModuleManager::find_module_port(const ModuleId& module_id, const std::string& port_name) const { + /* Validate the module id */ + VTR_ASSERT(valid_module_id(module_id)); + + /* Iterate over the ports of the module */ + for (const auto& port : port_ids_[module_id]) { + if (0 == port_name.compare(ports_[module_id][port].get_name())) { + /* Find it, return the id */ + return port; + } + } + /* Not found, return an invalid id */ + return ModulePortId::INVALID(); +} + +/* Find the Port information with a given port id */ +BasicPort ModuleManager::module_port(const ModuleId& module_id, const ModulePortId& port_id) const { + /* Validate the module and port id */ + VTR_ASSERT(valid_module_port_id(module_id, port_id)); + return ports_[module_id][port_id]; +} + /* Find the module id by a given name, return invalid if not found */ ModuleId ModuleManager::find_module(const std::string& name) const { if (name_id_map_.find(name) != name_id_map_.end()) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index a3be0e5a8..b85681e3d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -37,6 +37,11 @@ class ModuleManager { std::string module_name(const ModuleId& module_id) const; std::string module_port_type_str(const enum e_module_port_type& port_type) const; std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; + /* Find a port of a module by a given name */ + ModulePortId find_module_port(const ModuleId& module_id, const std::string& port_name) const; + /* Find the Port information with a given port id */ + BasicPort module_port(const ModuleId& module_id, const ModulePortId& port_id) const; + /* Find a module by a given name */ ModuleId find_module(const std::string& name) const; /* Find the number of instances of a child module in the parent module */ size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 6bb4b08b5..de027c0b9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -6,6 +6,7 @@ * and the full multiplexer **********************************************/ #include +#include #include "util.h" #include "vtr_assert.h" @@ -74,7 +75,7 @@ void generate_verilog_cmos_mux_branch_body_structural(ModuleManager& module_mana if (0 == edges.size()) { continue; } - /* TODO: Output a tgate use a module manager */ + /* Output a tgate use a module manager */ /* Create a port-to-port name map */ std::map port2port_name_map; /* input port */ @@ -693,6 +694,213 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, } } +/******************************************************************** + * Generate the internal logic (multiplexing structure) for + * a multiplexer or LUT in Verilog codes + * This function will : + * 1. build a multiplexing structure by instanciating the branch circuits + * generated before or standard cells MUX2 + * 2. add intermediate buffers between multiplexing stages if specified. + *******************************************************************/ +static +void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Find the actual mux size */ + size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); + + /* TODO: these are duplicated codes, find a way to simplify it!!! + * Get the regular (non-mode-select) sram ports from the mux + */ + std::vector mux_regular_sram_ports; + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true)) { + /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules + * Here we just bypass it. + */ + if (true == circuit_lib.port_is_mode_select(port)) { + continue; + } + mux_regular_sram_ports.push_back(port); + } + VTR_ASSERT(1 == mux_regular_sram_ports.size()); + + print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a CMOS MUX module -----")); + /* Print local wires which are the nodes in the mux graph */ + for (size_t level = 0; level < mux_graph.num_levels(); ++level) { + /* Print the internal wires located at this level */ + BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; + /* Identify if an intermediate buffer is needed */ + if (false == require_intermediate_buffer_at_mux_level(circuit_lib, circuit_model, level)) { + continue; + } + BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; + } + print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); + + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX modules -----")); + /* Iterate over all the internal nodes and output nodes in the mux graph */ + for (const auto& node : mux_graph.non_input_nodes()) { + /* Get the size of branch circuit + * Instanciate an branch circuit by the size (fan-in) of the node + */ + size_t branch_size = mux_graph.node_in_edges(node).size(); + /* Instanciate the branch module: + * Case 1: the branch module is a standard cell MUX2 + * Case 2: the branch module is a tgate-based module + */ + std::string branch_module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); + /* Get the moduleId for the submodule */ + ModuleId branch_module_id = module_manager.find_module(branch_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != branch_module_id); + + /* Get the node level and index in the current level */ + size_t output_node_level = mux_graph.node_level(node); + size_t output_node_index_at_level = mux_graph.node_index_at_level(node); + + /* Get the nodes which drive the root_node */ + std::vector input_nodes; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the nodes drive the edge */ + for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { + input_nodes.push_back(src_node); + } + } + /* Number of inputs should match the branch_input_size!!! */ + VTR_ASSERT(input_nodes.size() == branch_size); + + /* Get the mems in the branch circuits */ + std::vector mems; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the mem control the edge */ + MuxMemId mem = mux_graph.find_edge_mem(edge); + /* Add the mem if it is not in the list */ + if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { + mems.push_back(mem); + } + } + + /* Create a port-to-port map */ + std::map port2port_name_map; + /* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */ + + /* TODO: for clean representation, need to merge the node names in [a:b] format, if possible!!! + * All the input node names organized in bus + */ + std::vector branch_node_input_ports; + for (const auto& input_node : input_nodes) { + /* Generate the port info of each input node */ + size_t input_node_level = mux_graph.node_level(input_node); + size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); + BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, require_intermediate_buffer_at_mux_level(circuit_lib, circuit_model, input_node_level)), input_node_index_at_level, input_node_index_at_level); + branch_node_input_ports.push_back(branch_node_input_port); + } + /* Try to combine the ports */ + std::vector combined_branch_node_input_ports = combine_verilog_ports(branch_node_input_ports); + /* If we have more than 1 port in the combined ports , + * + * output a local wire */ + VTR_ASSERT(0 < combined_branch_node_input_ports.size()); + /* Create the port info for the input */ + BasicPort instance_input_port; + if (1 == combined_branch_node_input_ports.size()) { + instance_input_port = combined_branch_node_input_ports[0]; + } else { + /* TODO: the naming could be more flexible? */ + instance_input_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_in"); + /* Deposite a [0:0] port */ + instance_input_port.set_width(1); + for (const auto& port : combined_branch_node_input_ports) { + instance_input_port.combine(port); + } + /* Print a local wire for the merged ports */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_input_port); + fp << " = " << generate_verilog_ports(combined_branch_node_input_ports); + fp << ";" << std::endl; + } + + /* Link nodes to input ports for the branch module */ + /* TODO: the naming could be more flexible? */ + ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in"); + VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); + /* Get the port from module */ + BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id); + /* Double check: Port width should match the number of input nodes */ + VTR_ASSERT(module_input_port.get_width() == instance_input_port.get_width()); + port2port_name_map[module_input_port.get_name()] = instance_input_port; + + /* Link nodes to output ports for the branch module */ + BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out"); + VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); + /* Get the port from module */ + BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id); + /* Double check: Port width should match the number of output nodes */ + VTR_ASSERT(module_output_port.get_width() == instance_output_port.get_width()); + port2port_name_map[module_output_port.get_name()] = module_output_port; + + /* All the mem node names organized in bus */ + std::vector branch_node_mem_ports; + for (const auto& mem : mems) { + /* Generate the port info of each mem node */ + BasicPort branch_node_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); + branch_node_mem_ports.push_back(branch_node_mem_port); + } + /* Try to combine the ports */ + std::vector combined_branch_node_mem_ports = combine_verilog_ports(branch_node_mem_ports); + /* If we have more than 1 port in the combined ports , + * + * output a local wire */ + VTR_ASSERT(0 < combined_branch_node_mem_ports.size()); + /* Create the port info for the input */ + BasicPort instance_mem_port; + if (1 == combined_branch_node_mem_ports.size()) { + instance_mem_port = combined_branch_node_mem_ports[0]; + } else { + /* TODO: the naming could be more flexible? */ + instance_mem_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_mem"); + /* Deposite a [0:0] port */ + instance_mem_port.set_width(1); + /* TODO: combine the ports could be a function? */ + for (const auto& port : combined_branch_node_mem_ports) { + instance_mem_port.combine(port); + } + /* Print a local wire for the merged ports */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_mem_port); + fp << " = " << generate_verilog_ports(combined_branch_node_mem_ports); + fp << ";" << std::endl; + } + + /* Link nodes to input ports for the branch module */ + /* TODO: the naming could be more flexible? */ + ModulePortId module_mem_port_id = module_manager.find_module_port(branch_module_id, "mem"); + VTR_ASSERT(ModulePortId::INVALID() != module_mem_port_id); + /* Get the port from module */ + BasicPort module_mem_port = module_manager.module_port(branch_module_id, module_mem_port_id); + /* Double check: Port width should match the number of input nodes */ + VTR_ASSERT(module_mem_port.get_width() == instance_mem_port.get_width()); + port2port_name_map[module_mem_port.get_name()] = instance_mem_port; + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, branch_module_id); + + /* TODO: Now we need to add intermediate buffers by instanciating the modules */ + } + print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX modules -----")); +} + /********************************************************************* * Generate Verilog codes modeling a CMOS multiplexer with the given size * The Verilog module will consist of three parts: @@ -731,7 +939,6 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, /* Check codes to ensure the port of Verilog netlists will match */ /* MUX graph must have only 1 output */ VTR_ASSERT(1 == mux_input_ports.size()); - VTR_ASSERT(1 == mux_input_ports.size()); /* A quick check on the model ports */ if ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) || ((SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) @@ -802,6 +1009,7 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, /* TODO: Print the internal logic in Verilog codes */ /* TODO: Print the Multiplexing structure in Verilog codes */ + generate_verilog_cmos_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); /* TODO: Print the input buffers in Verilog codes */ /* TODO: Print the output buffers in Verilog codes */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 8747b8c18..623f016d5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -128,6 +128,25 @@ void print_verilog_module_declaration(std::fstream& fp, /************************************************ * Print an instance for a Verilog module + * This function will output the port map + * by referring to a port-to-port mapping: + * -> + * The key of the port-to-port mapping is the + * port name of the module: + * The value of the port-to-port mapping is the + * port information of the instance + * With link between module and instance, the function + * can output a Verilog instance easily, supporting + * both explicit port mapping: + * .() + * and inexplicit port mapping + * + * + * Note that, it is not necessary that + * the port-to-port mapping covers all the module ports. + * Any instance/module port which are not specified in the + * port-to-port mapping will be output by the module + * port name. ***********************************************/ void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, @@ -168,6 +187,11 @@ void print_verilog_module_instance(std::fstream& fp, /* Try to find the instanced port name in the name map */ if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) { /* Found it, we assign the port name */ + /* TODO: make sure the port width matches! */ + ModulePortId module_port_id = module_manager.find_module_port(child_module_id, port.get_name()); + /* Get the port from module */ + BasicPort module_port = module_manager.module_port(child_module_id, module_port_id); + VTR_ASSERT(module_port.get_width() == port2port_name_map.at(port.get_name()).get_width()); fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name())); } else { /* Not found, we give the default port name */ @@ -197,7 +221,9 @@ void print_verilog_module_end(std::fstream& fp, fp << std::endl; } -/* Generate a string of a Verilog port */ +/************************************************ + * Generate a string of a Verilog port + ***********************************************/ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type, const BasicPort& port_info) { std::string verilog_line; @@ -224,4 +250,86 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p return verilog_line; } +/************************************************ + * This function takes a list of ports and + * combine the port string by comparing the name + * and width of ports. + * For example, two ports A and B share the same name is + * mergable as long as A's MSB + 1 == B's LSB + * Note that the port sequence really matters! + * This function will NOT change the sequence + * of ports in the list port_info + ***********************************************/ +std::vector combine_verilog_ports(const std::vector& ports) { + std::vector merged_ports; + /* Directly return if there are no ports */ + if (0 == ports.size()) { + return merged_ports; + } + /* Push the first port to the merged ports */ + merged_ports.push_back(ports[0]); + + /* Iterate over ports */ + for (const auto& port : ports) { + /* Bypass the first port, it is already in the list */ + if (&port == &ports[0]) { + continue; + } + /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */ + for (auto& merged_port : merged_ports) { + if (0 != port.get_name().compare(merged_port.get_name())) { + /* Unable to merge, add the port to merged port list */ + merged_ports.push_back(port); + /* Go to next */ + break; + } + /* May be merged, check LSB of port and MSB of merged_port */ + if (merged_port.get_msb() + 1 != port.get_lsb()) { + /* Unable to merge, add the port to merged port list */ + merged_ports.push_back(port); + /* Go to next */ + break; + } + /* Reach here, we should merge the ports, + * LSB of merged_port remains the same, + * MSB of merged_port will be updated + * to the MSB of port + */ + merged_port.set_msb(port.get_msb()); + break; + } + } + + return merged_ports; +} + +/************************************************ + * Generate the string of a list of verilog ports + ***********************************************/ +std::string generate_verilog_ports(const std::vector& merged_ports) { + + /* Output the string of ports: + * If there is only one port in the merged_port list + * we only output the port. + * If there are more than one port in the merged port list, we output an concatenated port: + * {, , ... } + */ + VTR_ASSERT(0 < merged_ports.size()); + if ( 1 == merged_ports.size()) { + /* Use connection type of verilog port */ + return generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]); + } + + std::string verilog_line = "{"; + for (const auto& port : merged_ports) { + /* The first port does not need a comma */ + if (&port != &merged_ports[0]) { + verilog_line += ", "; + } + verilog_line += generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]); + } + verilog_line += "}"; + + return verilog_line; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 03626e4b6..328a87831 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -40,4 +40,8 @@ void print_verilog_module_end(std::fstream& fp, std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type, const BasicPort& port_info); +std::vector combine_verilog_ports(const std::vector& ports); + +std::string generate_verilog_ports(const std::vector& merged_ports); + #endif From 702a7683a8def0ba8490cd5dbfef23df3f00545c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 5 Sep 2019 10:23:35 -0600 Subject: [PATCH 172/482] Ensure strict exit of fpga_flow on error --- openfpga_flow/scripts/run_fpga_flow.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 8399ac63c..fcd1d1721 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -452,6 +452,7 @@ def run_yosys_with_abc(): if process.returncode: logger.info("Yosys failed with returncode %d", process.returncode) + raise subprocess.CalledProcessError(0, command) except: logger.exception("Failed to run yosys") clean_up_and_exit("") @@ -522,6 +523,7 @@ def run_ace2(): if process.returncode: logger.info("ACE2 failed with returncode %d", process.returncode) + raise subprocess.CalledProcessError(0, command) except: logger.exception("Failed to run ACE2") clean_up_and_exit("") @@ -771,6 +773,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): if process.returncode: logger.info("Standard VPR run failed with returncode %d", process.returncode) + raise subprocess.CalledProcessError(0, command) except (Exception, subprocess.CalledProcessError) as e: logger.exception("Failed to run VPR") filter_failed_process_output(e.output) From bc9d95408ec2d813483b92a1a652ed3582f46f7e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 5 Sep 2019 16:09:28 -0600 Subject: [PATCH 173/482] bug fixed and refactored intermediate buffer addition --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 55 ++- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 3 +- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 8 + vpr7_x2p/vpr/SRC/device/mux_graph.h | 1 + vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 55 ++- vpr7_x2p/vpr/SRC/device/mux_utils.h | 8 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 384 ++++++++++++++++-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 64 ++- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 6 + 9 files changed, 504 insertions(+), 80 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index d2aca01c3..ecdd11c65 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -175,7 +175,12 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& model_id VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is LUT */ VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - return buffer_existence_[model_id][LUT_INTER_BUFFER]; + /* LUT inter buffer may not always exist */ + if (LUT_INTER_BUFFER < buffer_existence_[model_id].size()) { + return buffer_existence_[model_id][LUT_INTER_BUFFER]; + } else { + return false; + } } /* Return a flag showing if a LUT circuit model uses fracturable structure */ @@ -187,6 +192,38 @@ bool CircuitLibrary::is_lut_fracturable(const CircuitModelId& model_id) const { return lut_is_fracturable_[model_id]; } +/* Return the circuit model of intermediate buffers + * that are inserted inside LUT multiplexing structures + */ +CircuitModelId CircuitLibrary::lut_intermediate_buffer_model(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + /* if we have an intermediate buffer, we return something, otherwise return an empty map */ + if (true == is_lut_intermediate_buffered(model_id)) { + return buffer_model_ids_[model_id][LUT_INTER_BUFFER]; + } else { + return CircuitModelId::INVALID(); + } +} + +/* Return the location map of intermediate buffers + * that are inserted inside LUT multiplexing structures + */ +std::string CircuitLibrary::lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + /* if we have an intermediate buffer, we return something, otherwise return an empty map */ + if (true == is_lut_intermediate_buffered(model_id)) { + return buffer_location_maps_[model_id][LUT_INTER_BUFFER]; + } else { + return std::string(); + } +} + /* Find the id of pass-gate circuit model * Two cases to be considered: * 1. this is a pass-gate circuit model, just find the data and return @@ -298,22 +335,6 @@ size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const { return buffer_num_levels_[model_id]; } -/* Return the location map of intermediate buffers - * that are inserted inside LUT multiplexing structures - */ -std::string CircuitLibrary::lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is BUF */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* if we have an intermediate buffer, we return something, otherwise return an empty map */ - if (true == is_lut_intermediate_buffered(model_id)) { - return buffer_location_maps_[model_id][LUT_INTER_BUFFER]; - } else { - return std::string(); - } -} - /* Return the number of levels of delay types for a circuit model */ size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const { /* validate the model_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index a2f5eab95..351717cf1 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -226,6 +226,8 @@ class CircuitLibrary { /* LUT-related information */ bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; bool is_lut_fracturable(const CircuitModelId& model_id) const; + CircuitModelId lut_intermediate_buffer_model(const CircuitModelId& model_id) const; + std::string lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const; /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; @@ -239,7 +241,6 @@ class CircuitLibrary { /* Buffer information */ enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const; size_t buffer_num_levels(const CircuitModelId& model_id) const; - std::string lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const; /* Delay information */ size_t num_delay_info(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 6656edca3..294c6741f 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -144,6 +144,13 @@ size_t MuxGraph::num_levels() const { return node_lookup_.size() - 1; } +/* Find the actual number of levels in the MUX graph */ +size_t MuxGraph::num_node_levels() const { + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_mux_graph()); + return node_lookup_.size(); +} + /* Find the number of configuration memories in the MUX graph */ size_t MuxGraph::num_memory_bits() const { /* need to check if the graph is valid or not */ @@ -566,6 +573,7 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, /* Number of outputs is definite, add and configure */ MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); node_levels_[output_node] = num_levels; + node_ids_at_level_[output_node] = 0; node_output_ids_[output_node] = MuxOutputId(0); /* Update node lookup */ node_lookup[num_levels].push_back(output_node); diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 7e1e7d128..70f5a525e 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -73,6 +73,7 @@ class MuxGraph { std::vector find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const; /* Find the number of levels in the MUX graph */ size_t num_levels() const; + size_t num_node_levels() const; /* Find the number of SRAMs in the MUX graph */ size_t num_memory_bits() const; /* Find the number of nodes at a given level in the MUX graph */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index c15e3081f..3fafb1998 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -151,31 +151,52 @@ size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, } /************************************************** - * Find if there is an intermediate buffer - * locating at the multiplexing structure of a LUT + * Build a location map for intermediate buffers + * that may appear at the multiplexing structure of a LUT + * Here is a tricky thing: + * By default, the first and last stage should not exist any intermediate buffers + * For example: + * There are 5 stages in a 4-stage multiplexer is available for buffering + * but only 3 stages [1,2,3] are intermedate buffers + * and these are users' specification + * + * +-------+ +-------+ +-------+ +-------+ + * location | stage | location | stage | location | stage | location | stage | location + * [0] | [0] | [1] | [1] | [2] | [2] | [3] | [3] | [5] + * +-------+ +-------+ +-------+ +-------+ + * + * We will check if the length of location map matches the number of + * multiplexer levels. And then complete a location map + * for the given multiplexers *************************************************/ -bool require_intermediate_buffer_at_mux_level(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& node_level) { - std::string intermediate_buffer_location_map; +std::vector build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& num_mux_levels) { + /* Deposite a default location map */ + std::vector location_map(num_mux_levels, false); + std::string location_map_str; /* ONLY for LUTs: intermediate buffers may exist if specified */ if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - intermediate_buffer_location_map = circuit_lib.lut_intermediate_buffer_location_map(circuit_model); + location_map_str = circuit_lib.lut_intermediate_buffer_location_map(circuit_model); } /* If no location map is specified, we can return here */ - if (intermediate_buffer_location_map.empty()) { - return false; + if (location_map_str.empty()) { + return location_map; } - /* We have a location map. Make sure we are in the range */ - if (node_level >= intermediate_buffer_location_map.length()) { - return false; + + /* Check if the user-defined location map matches the number of mux levels*/ + VTR_ASSERT(num_mux_levels - 2 == location_map_str.length()); + + /* Apply the location_map string to the intermediate stages of multiplexers */ + for (size_t i = 0; i < location_map_str.length(); ++i) { + /* '1' indicates that an intermediate buffer is needed at the location */ + if ('1' == location_map_str[i]) { + location_map[i + 1] = true; + } } - /* '1' indicates that the location is needed */ - if ('1' == intermediate_buffer_location_map[node_level]) { - return true; - } - return false; + + return location_map; } /************************************************** diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index b4a20ebe4..c61db23c8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -6,6 +6,8 @@ #ifndef MUX_UTILS_H #define MUX_UTILS_H +#include + #include "linkedlist.h" #include "circuit_library.h" #include "mux_library.h" @@ -29,9 +31,9 @@ size_t find_treelike_mux_num_levels(const size_t& mux_size); size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, const size_t& mux_level); -bool require_intermediate_buffer_at_mux_level(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& node_level); +std::vector build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& num_mux_levels); MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index de027c0b9..e5899b978 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -695,20 +695,222 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, } /******************************************************************** - * Generate the internal logic (multiplexing structure) for - * a multiplexer or LUT in Verilog codes + * Generate the standard-cell-based internal logic (multiplexing structure) + * for a multiplexer or LUT in Verilog codes * This function will : - * 1. build a multiplexing structure by instanciating the branch circuits - * generated before or standard cells MUX2 + * 1. build a multiplexing structure by instanciating standard cells MUX2 * 2. add intermediate buffers between multiplexing stages if specified. *******************************************************************/ static -void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const MuxGraph& mux_graph) { +void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const CircuitModelId& std_cell_model, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* TODO: these are duplicated codes, find a way to simplify it!!! + * Get the regular (non-mode-select) sram ports from the mux + */ + std::vector mux_regular_sram_ports; + for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true)) { + /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules + * Here we just bypass it. + */ + if (true == circuit_lib.port_is_mode_select(port)) { + continue; + } + mux_regular_sram_ports.push_back(port); + } + VTR_ASSERT(1 == mux_regular_sram_ports.size()); + + /* Find the input ports and output ports of the standard cell */ + std::vector std_cell_input_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_INPUT, true); + std::vector std_cell_output_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Quick check the requirements on port map */ + VTR_ASSERT(3 == std_cell_input_ports.size()); + VTR_ASSERT(1 == std_cell_output_ports.size()); + + /* Build the location map of intermediate buffers */ + std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); + + print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a CMOS MUX module based on Standard Cells -----")); + + print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a CMOS MUX module -----")); + /* Print local wires which are the nodes in the mux graph */ + for (size_t level = 0; level < mux_graph.num_levels(); ++level) { + /* Print the internal wires located at this level */ + BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; + /* Identify if an intermediate buffer is needed */ + if (false == inter_buffer_location_map[level]) { + continue; + } + BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; + } + print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); + + /* Iterate over all the internal nodes and output nodes in the mux graph */ + for (const auto& node : mux_graph.non_input_nodes()) { + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX modules -----")); + /* Get the size of branch circuit + * Instanciate an branch circuit by the size (fan-in) of the node + */ + size_t branch_size = mux_graph.node_in_edges(node).size(); + + /* Get the nodes which drive the root_node */ + std::vector input_nodes; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the nodes drive the edge */ + for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { + input_nodes.push_back(src_node); + } + } + /* Number of inputs should match the branch_input_size!!! */ + VTR_ASSERT(input_nodes.size() == branch_size); + + /* Get the node level and index in the current level */ + size_t output_node_level = mux_graph.node_level(node); + size_t output_node_index_at_level = mux_graph.node_index_at_level(node); + + /* Get the mems in the branch circuits */ + std::vector mems; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the mem control the edge */ + MuxMemId mem = mux_graph.find_edge_mem(edge); + /* Add the mem if it is not in the list */ + if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { + mems.push_back(mem); + } + } + + /* Instanciate the branch module, which is a standard cell MUX2 + * We follow a fixed port map: + * TODO: the port map could be more flexible? + * input_port[0] of MUX2 standard cell is wired to input_node[0] + * input_port[1] of MUX2 standard cell is wired to input_node[1] + * output_port[0] of MUX2 standard cell is wired to output_node[0] + * input_port[2] of MUX2 standard cell is wired to mem_node[0] + */ + std::string branch_module_name= circuit_lib.model_name(std_cell_model); + /* Get the moduleId for the submodule */ + ModuleId branch_module_id = module_manager.find_module(branch_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != branch_module_id); + + /* Create a port-to-port map */ + std::map port2port_name_map; + + /* To match the standard cell MUX2: We should have only 2 input_nodes */ + VTR_ASSERT(2 == input_nodes.size()); + /* Build the link between input_node[0] and std_cell_input_port[0] + * Build the link between input_node[1] and std_cell_input_port[1] + */ + for (const auto& input_node : input_nodes) { + /* Generate the port info of each input node */ + size_t input_node_level = mux_graph.node_level(input_node); + size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); + BasicPort instance_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); + + /* Link nodes to input ports for the branch module */ + std::string module_input_port_name = circuit_lib.port_lib_name(std_cell_input_ports[&input_node - &input_nodes[0]]); + port2port_name_map[module_input_port_name] = instance_input_port; + } + + /* Build the link between output_node[0] and std_cell_output_port[0] */ + { /* Create a code block to accommodate the local variables */ + BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + std::string module_output_port_name = circuit_lib.port_lib_name(std_cell_output_ports[0]); + port2port_name_map[module_output_port_name] = instance_output_port; + } + + /* To match the standard cell MUX2: We should have only 1 mem_node */ + VTR_ASSERT(1 == mems.size()); + /* Build the link between mem_node[0] and std_cell_intput_port[2] */ + for (const auto& mem : mems) { + /* Generate the port info of each mem node */ + BasicPort instance_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); + std::string module_mem_port_name = circuit_lib.port_lib_name(std_cell_input_ports[2]); + port2port_name_map[module_mem_port_name] = instance_mem_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(std_cell_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, branch_module_id); + + print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX modules -----")); + + if (false == inter_buffer_location_map[output_node_level]) { + continue; /* No need for intermediate buffers */ + } + + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a intermediate buffer modules -----")); + + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Create a port-to-port map */ + std::map buffer_port2port_name_map; + + /* Build the link between buffer_input_port[0] and output_node_pre_buffer + * Build the link between buffer_output_port[0] and output_node_bufferred + */ + { /* Create a code block to accommodate the local variables */ + BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]); + buffer_port2port_name_map[module_input_port_name] = buffer_instance_input_port; + BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); + std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]); + buffer_port2port_name_map[module_output_port_name] = buffer_instance_output_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, buffer_module_id); + + print_verilog_comment(fp, std::string("---- END Instanciation of a intermediate buffer modules -----")); + } + + print_verilog_comment(fp, std::string("---- END Internal Logic of a CMOS MUX module based on Standard Cells -----")); +} + +/******************************************************************** + * Generate the pass-transistor/transmission-gate -based internal logic + * (multiplexing structure) for a multiplexer or LUT in Verilog codes + * This function will : + * 1. build a multiplexing structure by instanciating the branch circuits + * generated before + * 2. add intermediate buffers between multiplexing stages if specified. + *******************************************************************/ +static +void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -730,6 +932,11 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu } VTR_ASSERT(1 == mux_regular_sram_ports.size()); + /* Build the location map of intermediate buffers */ + std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); + + print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a CMOS MUX module based on Pass-transistor/Transmission-gates -----")); + print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a CMOS MUX module -----")); /* Print local wires which are the nodes in the mux graph */ for (size_t level = 0; level < mux_graph.num_levels(); ++level) { @@ -737,7 +944,7 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; /* Identify if an intermediate buffer is needed */ - if (false == require_intermediate_buffer_at_mux_level(circuit_lib, circuit_model, level)) { + if (false == inter_buffer_location_map[level]) { continue; } BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); @@ -745,22 +952,14 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu } print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX modules -----")); + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----")); /* Iterate over all the internal nodes and output nodes in the mux graph */ for (const auto& node : mux_graph.non_input_nodes()) { + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----")); /* Get the size of branch circuit * Instanciate an branch circuit by the size (fan-in) of the node */ size_t branch_size = mux_graph.node_in_edges(node).size(); - /* Instanciate the branch module: - * Case 1: the branch module is a standard cell MUX2 - * Case 2: the branch module is a tgate-based module - */ - std::string branch_module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); - /* Get the moduleId for the submodule */ - ModuleId branch_module_id = module_manager.find_module(branch_module_name); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != branch_module_id); /* Get the node level and index in the current level */ size_t output_node_level = mux_graph.node_level(node); @@ -788,19 +987,25 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu } } + /* Instanciate the branch module which is a tgate-based module + */ + std::string branch_module_name= generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); + /* Get the moduleId for the submodule */ + ModuleId branch_module_id = module_manager.find_module(branch_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != branch_module_id); + /* Create a port-to-port map */ std::map port2port_name_map; /* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */ - /* TODO: for clean representation, need to merge the node names in [a:b] format, if possible!!! - * All the input node names organized in bus - */ + /* All the input node names organized in bus */ std::vector branch_node_input_ports; for (const auto& input_node : input_nodes) { /* Generate the port info of each input node */ size_t input_node_level = mux_graph.node_level(input_node); size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, require_intermediate_buffer_at_mux_level(circuit_lib, circuit_model, input_node_level)), input_node_index_at_level, input_node_index_at_level); + BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); branch_node_input_ports.push_back(branch_node_input_port); } /* Try to combine the ports */ @@ -828,13 +1033,10 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu } /* Link nodes to input ports for the branch module */ - /* TODO: the naming could be more flexible? */ ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in"); VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); /* Get the port from module */ BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id); - /* Double check: Port width should match the number of input nodes */ - VTR_ASSERT(module_input_port.get_width() == instance_input_port.get_width()); port2port_name_map[module_input_port.get_name()] = instance_input_port; /* Link nodes to output ports for the branch module */ @@ -843,9 +1045,7 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); /* Get the port from module */ BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id); - /* Double check: Port width should match the number of output nodes */ - VTR_ASSERT(module_output_port.get_width() == instance_output_port.get_width()); - port2port_name_map[module_output_port.get_name()] = module_output_port; + port2port_name_map[module_output_port.get_name()] = instance_output_port; /* All the mem node names organized in bus */ std::vector branch_node_mem_ports; @@ -857,10 +1057,10 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu /* Try to combine the ports */ std::vector combined_branch_node_mem_ports = combine_verilog_ports(branch_node_mem_ports); /* If we have more than 1 port in the combined ports , - * - * output a local wire */ + * output a local wire + */ VTR_ASSERT(0 < combined_branch_node_mem_ports.size()); - /* Create the port info for the input */ + /* Create the port info for the mem */ BasicPort instance_mem_port; if (1 == combined_branch_node_mem_ports.size()) { instance_mem_port = combined_branch_node_mem_ports[0]; @@ -885,9 +1085,47 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu VTR_ASSERT(ModulePortId::INVALID() != module_mem_port_id); /* Get the port from module */ BasicPort module_mem_port = module_manager.module_port(branch_module_id, module_mem_port_id); - /* Double check: Port width should match the number of input nodes */ - VTR_ASSERT(module_mem_port.get_width() == instance_mem_port.get_width()); port2port_name_map[module_mem_port.get_name()] = instance_mem_port; + + /* TODO: the postfix _inv can be soft coded in the circuit library as a port_inv_postfix */ + /* Create the port info for the mem_inv */ + std::vector branch_node_mem_inv_ports; + for (const auto& mem : mems) { + /* Generate the port info of each mem node */ + BasicPort branch_node_mem_inv_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]) + "_inv", size_t(mem), size_t(mem)); + branch_node_mem_inv_ports.push_back(branch_node_mem_inv_port); + } + /* Try to combine the ports */ + std::vector combined_branch_node_mem_inv_ports = combine_verilog_ports(branch_node_mem_inv_ports); + /* If we have more than 1 port in the combined ports , + * output a local wire + */ + VTR_ASSERT(0 < combined_branch_node_mem_inv_ports.size()); + BasicPort instance_mem_inv_port; + if (1 == combined_branch_node_mem_inv_ports.size()) { + instance_mem_inv_port = combined_branch_node_mem_inv_ports[0]; + } else { + /* TODO: the naming could be more flexible? */ + instance_mem_inv_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_mem"); + /* Deposite a [0:0] port */ + instance_mem_inv_port.set_width(1); + /* TODO: combine the ports could be a function? */ + for (const auto& port : combined_branch_node_mem_inv_ports) { + instance_mem_inv_port.combine(port); + } + /* Print a local wire for the merged ports */ + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_mem_inv_port); + fp << " = " << generate_verilog_ports(combined_branch_node_mem_inv_ports); + fp << ";" << std::endl; + } + + /* Link nodes to input ports for the branch module */ + /* TODO: the naming could be more flexible? */ + ModulePortId module_mem_inv_port_id = module_manager.find_module_port(branch_module_id, "mem_inv"); + VTR_ASSERT(ModulePortId::INVALID() != module_mem_inv_port_id); + /* Get the port from module */ + BasicPort module_mem_inv_port = module_manager.module_port(branch_module_id, module_mem_inv_port_id); + port2port_name_map[module_mem_inv_port.get_name()] = instance_mem_inv_port; /* Output an instance of the module */ print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); @@ -896,9 +1134,56 @@ void generate_verilog_cmos_mux_module_multiplexing_structure(ModuleManager& modu */ module_manager.add_child_module(module_id, branch_module_id); - /* TODO: Now we need to add intermediate buffers by instanciating the modules */ + print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX module -----")); + + if (false == inter_buffer_location_map[output_node_level]) { + continue; /* No need for intermediate buffers */ + } + + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a intermediate buffer modules -----")); + + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Create a port-to-port map */ + std::map buffer_port2port_name_map; + + /* Build the link between buffer_input_port[0] and output_node_pre_buffer + * Build the link between buffer_output_port[0] and output_node_bufferred + */ + { /* Create a code block to accommodate the local variables */ + BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]); + buffer_port2port_name_map[module_input_port_name] = buffer_instance_input_port; + BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); + std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]); + buffer_port2port_name_map[module_output_port_name] = buffer_instance_output_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, buffer_module_id); + + print_verilog_comment(fp, std::string("---- END Instanciation of a intermediate buffer modules -----")); + } - print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX modules -----")); + + print_verilog_comment(fp, std::string("---- END Internal Logic of a CMOS MUX module based on Pass-transistor/Transmission-gates -----")); } /********************************************************************* @@ -1008,8 +1293,27 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, print_verilog_module_declaration(fp, module_manager, module_id); /* TODO: Print the internal logic in Verilog codes */ - /* TODO: Print the Multiplexing structure in Verilog codes */ - generate_verilog_cmos_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + /* TODO: Print the Multiplexing structure in Verilog codes + * TODO: branch the module port name by using standard cell MUX2 or TGATE, + * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input + * 2. Branch TGATE-based module has a fixed port name + * TODO: the naming could be more flexible? + */ + /* Get the tgate model */ + CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model); + /* Instanciate the branch module: + * Case 1: the branch module is a standard cell MUX2 + * Case 2: the branch module is a tgate-based module + */ + std::string branch_module_name; + if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); + generate_verilog_cmos_mux_module_mux2_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, tgate_model, mux_graph); + } else { + VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_lib.model_type(tgate_model)); + generate_verilog_cmos_mux_module_tgate_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + } + /* TODO: Print the input buffers in Verilog codes */ /* TODO: Print the output buffers in Verilog codes */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 7bd065cbe..cea48799d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3471,9 +3471,62 @@ void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, return; } -/* Dump verilog files of submodules to be used in FPGA components : +/********************************************************************* + * Register all the user-defined modules in the module manager + * Walk through the circuit library and add user-defined circuit models + * to the module_manager + ********************************************************************/ +static +void add_user_defined_verilog_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib) { + /* Module port depends on the model port attributes: + * Any model ports whose is_global_port() is true => MODULE_GLOBAL_PORT + * Inout model port: SPICE_MODEL_PORT_INOUT => MODULE_INOUT_PORT + * Input model port: SPICE_MODEL_PORT_INPUT/SRAM/BL/WL/BLB/WLB => MODULE_INPUT_PORT + * Output model port: SPICE_MODEL_PORT_OUTPUT => MODULE_OUTPUT_PORT + * Clock model port: SPICE_MODEL_PORT_CLOCK => MODULE_CLOCK_PORT + */ + std::map port_type2type_map; + port_type2type_map[SPICE_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT; + port_type2type_map[SPICE_MODEL_PORT_CLOCK] = ModuleManager::MODULE_CLOCK_PORT; + + /* Iterate over verilog modules */ + for (const auto& model : circuit_lib.models()) { + /* We only care about user-defined models */ + if (true == circuit_lib.model_verilog_netlist(model).empty()) { + continue; + } + /* Reach here, the model requires a user-defined Verilog netlist, + * Register it in the module_manager + */ + ModuleId module_id = module_manager.add_module(circuit_lib.model_name(model)); + /* Iterate over the ports of circuit model, and add them to module_manager */ + for (const auto& model_port : circuit_lib.model_ports(model)) { + /* Create port information */ + BasicPort module_port(circuit_lib.port_lib_name(model_port), circuit_lib.port_size(model_port)); + + /* Deposite a module port type */ + ModuleManager::e_module_port_type module_port_type = port_type2type_map[circuit_lib.port_type(model_port)]; + /* Force a global port type */ + if (true == circuit_lib.port_is_global(model_port)) { + module_port_type = ModuleManager::MODULE_GLOBAL_PORT; + } + module_manager.add_port(module_id, module_port, module_port_type); + } + } +} + +/********************************************************************* + * Dump verilog files of submodules to be used in FPGA components : * 1. MUXes - */ + ********************************************************************/ void dump_verilog_submodules(ModuleManager& module_manager, const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, @@ -3483,6 +3536,13 @@ void dump_verilog_submodules(ModuleManager& module_manager, t_det_routing_arch* routing_arch, t_syn_verilog_opts fpga_verilog_opts) { + /* TODO: Register all the user-defined modules in the module manager + * This should be done prior to other steps in this function, + * because they will be instanciated by other primitive modules + */ + vpr_printf(TIO_MESSAGE_INFO, "Registering user-defined modules...\n"); + add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib); + vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); print_verilog_submodule_essentials(module_manager, std::string(verilog_dir), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 623f016d5..01e515e3c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -156,6 +156,12 @@ void print_verilog_module_instance(std::fstream& fp, check_file_handler(fp); + /* Check: all the key ports in the port2port_name_map does exist in the child module */ + for (const auto& kv : port2port_name_map) { + ModulePortId module_port_id = module_manager.find_module_port(child_module_id, kv.first); + VTR_ASSERT(ModulePortId::INVALID() != module_port_id); + } + /* Print module name */ fp << "\t" << module_manager.module_name(child_module_id) << " "; /* Print instance name, _ */ From bcbcd463fedc238a2981dc9d6aa26a263c4ca662 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 6 Sep 2019 11:48:13 -0400 Subject: [PATCH 174/482] Added pending runs in log --- openfpga_flow/scripts/run_fpga_task.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 5b76d4208..06a5358fb 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -255,6 +255,7 @@ def generate_each_task_actions(taskname): "name": "%02d_arch%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, "commands": command, + "finished" : False, "status": False}) logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' % @@ -343,7 +344,7 @@ def strip_child_logger_info(line): logger.info(line) -def run_single_script(s, eachJob): +def run_single_script(s, eachJob, job_list): logger.debug('Added job in pool') with s: logger.debug("Running OpenFPGA flow with " + @@ -383,16 +384,19 @@ def run_single_script(s, eachJob): else str(timediff) logger.info("%s Finished with returncode %d, Time Taken %s " % (name, process.returncode, timestr)) + eachJob["finished"] = True + no_of_finished_job = sum([ not eachJ["finished"] for eachJ in job_list]) + logger.info("***** %d runs pending *****" % (no_of_finished_job)) -def run_actions(job_run_list): +def run_actions(job_list): thread_sema = threading.Semaphore(args.maxthreads) thred_list = [] - for index, eachjob in enumerate(job_run_list): + for index, eachjob in enumerate(job_list): JobID = 'Job_%02d' % (index+1) logger.info("Running %s = %s" % (JobID, eachjob["name"])) t = threading.Thread(target=run_single_script, - name=JobID, args=(thread_sema, eachjob)) + name=JobID, args=(thread_sema, eachjob, job_list)) t.start() thred_list.append(t) for eachthread in thred_list: From 59edd498626061e90fa5391623b31cff961e63e5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 6 Sep 2019 16:39:34 -0600 Subject: [PATCH 175/482] refactored CMOS MUX buffering --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 24 ++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 2 + vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 34 ++ vpr7_x2p/vpr/SRC/device/mux_graph.h | 2 + .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 355 +++++++++++------- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 167 +++++++- .../fpga_x2p/verilog/verilog_writer_utils.h | 22 ++ 7 files changed, 474 insertions(+), 132 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index ecdd11c65..95a172838 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -335,6 +335,30 @@ size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const { return buffer_num_levels_[model_id]; } +/* Find the circuit model id of the input buffer of a circuit model */ +CircuitModelId CircuitLibrary::input_buffer_model(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* INPUT buffer may not always exist */ + if (INPUT < buffer_existence_[model_id].size()) { + return buffer_model_ids_[model_id][INPUT]; + } else { + return CircuitModelId::INVALID(); + } +} + +/* Find the circuit model id of the output buffer of a circuit model */ +CircuitModelId CircuitLibrary::output_buffer_model(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* OUTPUT buffer may not always exist */ + if (OUTPUT < buffer_existence_[model_id].size()) { + return buffer_model_ids_[model_id][OUTPUT]; + } else { + return CircuitModelId::INVALID(); + } +} + /* Return the number of levels of delay types for a circuit model */ size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const { /* validate the model_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 351717cf1..a344dc8c7 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -241,6 +241,8 @@ class CircuitLibrary { /* Buffer information */ enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const; size_t buffer_num_levels(const CircuitModelId& model_id) const; + CircuitModelId input_buffer_model(const CircuitModelId& model_id) const; + CircuitModelId output_buffer_model(const CircuitModelId& model_id) const; /* Delay information */ size_t num_delay_info(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 294c6741f..91105ddbf 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -396,6 +396,40 @@ MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { return MuxNodeId::INVALID(); } +/* Get the node id w.r.t. the node level and node_index at the level + * Return an invalid value if not found + */ +MuxNodeId MuxGraph::node_id(const size_t& node_level, const size_t& node_index_at_level) const { + /* Ensure we have a valid node_look-up */ + VTR_ASSERT_SAFE(valid_node_lookup()); + + MuxNodeId ret_node = MuxNodeId::INVALID(); + + /* Search in the fast look up */ + if (node_level >= node_lookup_.size()) { + return ret_node; + } + + size_t node_cnt = 0; + /* Node level is valid, search in the node list */ + for (const auto& nodes_by_type : node_lookup_[node_level]) { + /* Search the node_index_at_level of each node */ + for (const auto& node : nodes_by_type) { + if (node_index_at_level != node_ids_at_level_[node]) { + continue; + } + /* Find the node, assign value and update the counter */ + ret_node = node; + node_cnt++; + } + } + + /* We should either find a node or nothing */ + VTR_ASSERT((0 == node_cnt) || (1 == node_cnt)); + + return ret_node; +} + /* Decode memory bits based on an input id */ std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id) const { /* initialize the memory bits: TODO: support default value */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 70f5a525e..856c7e0b1 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -97,6 +97,8 @@ class MuxGraph { std::vector build_mux_branch_graphs() const; /* Get the node id of a given input */ MuxNodeId node_id(const MuxInputId& input_id) const; + /* Get the node id w.r.t. the node level and node_index at the level */ + MuxNodeId node_id(const size_t& node_level, const size_t& node_index_at_level) const; /* Get the input id of a given node */ MuxInputId input_id(const MuxNodeId& node_id) const; /* Get the output id of a given node */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index e5899b978..7c430f1d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -753,6 +753,7 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; } print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); + fp << std::endl; /* Iterate over all the internal nodes and output nodes in the mux graph */ for (const auto& node : mux_graph.non_input_nodes()) { @@ -857,43 +858,18 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - /* Create a port-to-port map */ - std::map buffer_port2port_name_map; - - /* Build the link between buffer_input_port[0] and output_node_pre_buffer - * Build the link between buffer_output_port[0] and output_node_bufferred - */ - { /* Create a code block to accommodate the local variables */ - BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]); - buffer_port2port_name_map[module_input_port_name] = buffer_instance_input_port; - BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]); - buffer_port2port_name_map[module_output_port_name] = buffer_instance_output_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, buffer_module_id); + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); print_verilog_comment(fp, std::string("---- END Instanciation of a intermediate buffer modules -----")); + fp << std::endl; } print_verilog_comment(fp, std::string("---- END Internal Logic of a CMOS MUX module based on Standard Cells -----")); + fp << std::endl; } /******************************************************************** @@ -951,6 +927,7 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; } print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); + fp << std::endl; print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----")); /* Iterate over all the internal nodes and output nodes in the mux graph */ @@ -1008,28 +985,18 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); branch_node_input_ports.push_back(branch_node_input_port); } - /* Try to combine the ports */ - std::vector combined_branch_node_input_ports = combine_verilog_ports(branch_node_input_ports); - /* If we have more than 1 port in the combined ports , - * - * output a local wire */ - VTR_ASSERT(0 < combined_branch_node_input_ports.size()); + /* Create the port info for the input */ - BasicPort instance_input_port; - if (1 == combined_branch_node_input_ports.size()) { - instance_input_port = combined_branch_node_input_ports[0]; - } else { - /* TODO: the naming could be more flexible? */ - instance_input_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_in"); - /* Deposite a [0:0] port */ - instance_input_port.set_width(1); - for (const auto& port : combined_branch_node_input_ports) { - instance_input_port.combine(port); - } + /* TODO: the naming could be more flexible? */ + BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_in")); + /* If we have more than 1 port in the combined instance ports , + * output a local wire */ + if (1 < combine_verilog_ports(branch_node_input_ports).size()) { /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_input_port); - fp << " = " << generate_verilog_ports(combined_branch_node_input_ports); - fp << ";" << std::endl; + fp << "\t" << generate_verilog_local_wire(instance_input_port, branch_node_input_ports) << std::endl; + } else { + /* Safety check */ + VTR_ASSERT(1 == combine_verilog_ports(branch_node_input_ports).size()); } /* Link nodes to input ports for the branch module */ @@ -1054,29 +1021,18 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager BasicPort branch_node_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); branch_node_mem_ports.push_back(branch_node_mem_port); } - /* Try to combine the ports */ - std::vector combined_branch_node_mem_ports = combine_verilog_ports(branch_node_mem_ports); - /* If we have more than 1 port in the combined ports , - * output a local wire - */ - VTR_ASSERT(0 < combined_branch_node_mem_ports.size()); - /* Create the port info for the mem */ - BasicPort instance_mem_port; - if (1 == combined_branch_node_mem_ports.size()) { - instance_mem_port = combined_branch_node_mem_ports[0]; - } else { - /* TODO: the naming could be more flexible? */ - instance_mem_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_mem"); - /* Deposite a [0:0] port */ - instance_mem_port.set_width(1); - /* TODO: combine the ports could be a function? */ - for (const auto& port : combined_branch_node_mem_ports) { - instance_mem_port.combine(port); - } + + /* Create the port info for the input */ + /* TODO: the naming could be more flexible? */ + BasicPort instance_mem_port = generate_verilog_bus_port(branch_node_mem_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_mem")); + /* If we have more than 1 port in the combined instance ports , + * output a local wire */ + if (1 < combine_verilog_ports(branch_node_mem_ports).size()) { /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_mem_port); - fp << " = " << generate_verilog_ports(combined_branch_node_mem_ports); - fp << ";" << std::endl; + fp << "\t" << generate_verilog_local_wire(instance_mem_port, branch_node_mem_ports) << std::endl; + } else { + /* Safety check */ + VTR_ASSERT(1 == combine_verilog_ports(branch_node_mem_ports).size()); } /* Link nodes to input ports for the branch module */ @@ -1095,28 +1051,18 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager BasicPort branch_node_mem_inv_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]) + "_inv", size_t(mem), size_t(mem)); branch_node_mem_inv_ports.push_back(branch_node_mem_inv_port); } - /* Try to combine the ports */ - std::vector combined_branch_node_mem_inv_ports = combine_verilog_ports(branch_node_mem_inv_ports); - /* If we have more than 1 port in the combined ports , - * output a local wire - */ - VTR_ASSERT(0 < combined_branch_node_mem_inv_ports.size()); - BasicPort instance_mem_inv_port; - if (1 == combined_branch_node_mem_inv_ports.size()) { - instance_mem_inv_port = combined_branch_node_mem_inv_ports[0]; - } else { - /* TODO: the naming could be more flexible? */ - instance_mem_inv_port.set_name(generate_verilog_mux_node_name(output_node_level, false) + "_mem"); - /* Deposite a [0:0] port */ - instance_mem_inv_port.set_width(1); - /* TODO: combine the ports could be a function? */ - for (const auto& port : combined_branch_node_mem_inv_ports) { - instance_mem_inv_port.combine(port); - } + + /* Create the port info for the input */ + /* TODO: the naming could be more flexible? */ + BasicPort instance_mem_inv_port = generate_verilog_bus_port(branch_node_mem_inv_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_mem_inv")); + /* If we have more than 1 port in the combined instance ports , + * output a local wire */ + if (1 < combine_verilog_ports(branch_node_mem_inv_ports).size()) { /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, instance_mem_inv_port); - fp << " = " << generate_verilog_ports(combined_branch_node_mem_inv_ports); - fp << ";" << std::endl; + fp << "\t" << generate_verilog_local_wire(instance_mem_port, branch_node_mem_inv_ports) << std::endl; + } else { + /* Safety check */ + VTR_ASSERT(1 == combine_verilog_ports(branch_node_mem_inv_ports).size()); } /* Link nodes to input ports for the branch module */ @@ -1135,55 +1081,201 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager module_manager.add_child_module(module_id, branch_module_id); print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX module -----")); + fp << std::endl; if (false == inter_buffer_location_map[output_node_level]) { continue; /* No need for intermediate buffers */ } - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a intermediate buffer modules -----")); + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an intermediate buffer modules -----")); /* Now we need to add intermediate buffers by instanciating the modules */ CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); + + BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); - - /* Create a port-to-port map */ - std::map buffer_port2port_name_map; - - /* Build the link between buffer_input_port[0] and output_node_pre_buffer - * Build the link between buffer_output_port[0] and output_node_bufferred - */ - { /* Create a code block to accommodate the local variables */ - BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]); - buffer_port2port_name_map[module_input_port_name] = buffer_instance_input_port; - BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]); - buffer_port2port_name_map[module_output_port_name] = buffer_instance_output_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, buffer_module_id); - - print_verilog_comment(fp, std::string("---- END Instanciation of a intermediate buffer modules -----")); + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); + print_verilog_comment(fp, std::string("---- END Instanciation of an intermediate buffer module -----")); + fp << std::endl; } print_verilog_comment(fp, std::string("---- END Internal Logic of a CMOS MUX module based on Pass-transistor/Transmission-gates -----")); + fp << std::endl; +} + +/******************************************************************** + * Generate the input bufferes for a multiplexer or LUT in Verilog codes + * 1. If input are required to be buffered (specified by users), + * buffers will be added to all the datapath inputs. + * 2. If input are required to NOT be buffered (specified by users), + * all the datapath inputs will be short wired to MUX inputs. + * + * For those Multiplexers or LUTs require a constant input: + * the last input of multiplexer will be wired to a constant voltage level + *******************************************************************/ +static +void generate_verilog_cmos_mux_module_input_buffers(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* We should have only 1 input port! */ + VTR_ASSERT(1 == mux_input_ports.size()); + + /* Get the input port from MUX module */ + ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(mux_input_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); + /* Get the port from module */ + BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); + + /* Iterate over all the inputs in the MUX graph */ + for (const auto& input_node : mux_graph.inputs()) { + /* Fetch fundamental information from MUX graph w.r.t. the input node */ + MuxInputId input_index = mux_graph.input_id(input_node); + VTR_ASSERT(MuxInputId::INVALID() != input_index); + + size_t input_node_level = mux_graph.node_level(input_node); + size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); + + /* Create the port information of the MUX input, which is the input of buffer instance */ + BasicPort instance_input_port(module_input_port.get_name(), size_t(input_index), size_t(input_index)); + + /* Create the port information of the MUX graph input, which is the output of buffer instance */ + BasicPort instance_output_port(generate_verilog_mux_node_name(input_node_level, false), input_node_index_at_level, input_node_index_at_level); + + /* For last input: + * Add a constant value to the last input, if this MUX needs a constant input + */ + if ( (MuxInputId(mux_graph.num_inputs() - 1) == mux_graph.input_id(input_node)) + && (true == circuit_lib.mux_add_const_input(circuit_model)) ) { + /* Get the constant input value */ + size_t const_value = circuit_lib.mux_const_input_value(circuit_model); + VTR_ASSERT( (0 == const_value) || (1 == const_value) ); + /* For the output of the buffer instance: + * Get the last inputs from the MUX graph and generate the node name in MUX module. + */ + print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to a constant value -----")); + print_verilog_wire_constant_values(fp, instance_output_port, std::vector(1, const_value)); + print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to a constant value -----")); + fp << std::endl; + continue; /* Finish here */ + } + + /* If the inputs are not supposed to be buffered */ + if (false == circuit_lib.is_input_buffered(circuit_model)) { + print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to MUX module input -----")); + + /* Short wire all the datapath inputs to the MUX inputs */ + print_verilog_wire_connection(fp, instance_output_port, instance_input_port); + + print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to MUX module input -----")); + fp << std::endl; + continue; /* Finish here */ + } + + /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */ + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input buffer module -----")); + + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.input_buffer_model(circuit_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, instance_input_port, instance_output_port); + + print_verilog_comment(fp, std::string("---- END Instanciation of an input buffer module -----")); + fp << std::endl; + } +} + +/******************************************************************** + * Generate the output bufferes for a multiplexer or LUT in Verilog codes + * 1. If output are required to be buffered (specified by users), + * buffers will be added to all the outputs. + * 2. If output are required to NOT be buffered (specified by users), + * all the outputs will be short wired to MUX outputs. + *******************************************************************/ +static +void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Iterate over all the outputs in the MUX module */ + for (const auto& output_port : mux_output_ports) { + /* Get the output port from MUX module */ + ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(output_port)); + VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); + /* Get the port from module */ + BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); + + /* Iterate over each pin of the output port */ + for (const auto& pin : circuit_lib.pins(output_port)) { + /* Fetch fundamental information from MUX graph w.r.t. the input node */ + /* Deposite the last level of the graph, which is a default value */ + size_t output_node_level = mux_graph.num_node_levels() - 1; + /* If there is a fracturable level specified for the output, we find the exact level */ + if (size_t(-1) != circuit_lib.port_lut_frac_level(output_port)) { + output_node_level = circuit_lib.port_lut_frac_level(output_port); + } + /* Deposite a zero, which is a default value */ + size_t output_node_index_at_level = 0; + /* If there are output masks, we find the node_index */ + if (!circuit_lib.port_lut_output_masks(output_port).empty()) { + output_node_index_at_level = circuit_lib.port_lut_output_masks(output_port).at(pin); + } + /* Double check the node exists in the Mux Graph */ + VTR_ASSERT(MuxNodeId::INVALID() != mux_graph.node_id(output_node_level, output_node_index_at_level)); + + /* Create the port information of the MUX input, which is the input of buffer instance */ + BasicPort instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + + /* Create the port information of the module output at the given pin range, which is the output of buffer instance */ + BasicPort instance_output_port(module_output_port.get_name(), pin, pin); + + /* If the output is not supposed to be buffered */ + if (false == circuit_lib.is_output_buffered(circuit_model)) { + print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure output to MUX module output -----")); + + /* Short wire all the datapath inputs to the MUX inputs */ + print_verilog_wire_connection(fp, instance_output_port, instance_input_port); + + print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure output to MUX module output -----")); + fp << std::endl; + continue; /* Finish here */ + } + + /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */ + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an output buffer module -----")); + + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.output_buffer_model(circuit_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, instance_input_port, instance_output_port); + + print_verilog_comment(fp, std::string("---- END Instanciation of an output buffer module -----")); + fp << std::endl; + } + } } /********************************************************************* @@ -1293,8 +1385,8 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, print_verilog_module_declaration(fp, module_manager, module_id); /* TODO: Print the internal logic in Verilog codes */ - /* TODO: Print the Multiplexing structure in Verilog codes - * TODO: branch the module port name by using standard cell MUX2 or TGATE, + /* Print the Multiplexing structure in Verilog codes + * Separated generation strategy on using standard cell MUX2 or TGATE, * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input * 2. Branch TGATE-based module has a fixed port name * TODO: the naming could be more flexible? @@ -1314,8 +1406,9 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, generate_verilog_cmos_mux_module_tgate_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); } - /* TODO: Print the input buffers in Verilog codes */ - /* TODO: Print the output buffers in Verilog codes */ + /* Print the input and output buffers in Verilog codes */ + generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 01e515e3c..e5067c838 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -212,7 +212,7 @@ void print_verilog_module_instance(std::fstream& fp, } /* Print an end to the instance */ - fp << "\t" << ");" << std::endl; + fp << ");" << std::endl; } /************************************************ @@ -339,3 +339,168 @@ std::string generate_verilog_ports(const std::vector& merged_ports) { return verilog_line; } + +/******************************************************************** + * Generate a bus port (could be used to create a local wire) + * for a list of Verilog ports + * The bus port will be created by aggregating the ports in the list + * A bus port name may be need only there are many ports with + * different names. It is hard to name the bus port + *******************************************************************/ +BasicPort generate_verilog_bus_port(const std::vector& input_ports, + const std::string& bus_port_name) { + /* Try to combine the ports */ + std::vector combined_input_ports = combine_verilog_ports(input_ports); + + /* Create a port data structure that is to be returned */ + BasicPort bus_port; + + if (1 == combined_input_ports.size()) { + bus_port = combined_input_ports[0]; + } else { + /* TODO: the naming could be more flexible? */ + bus_port.set_name(bus_port_name); + /* Deposite a [0:0] port */ + bus_port.set_width(1); + for (const auto& port : combined_input_ports) { + bus_port.combine(port); + } + } + + return bus_port; +} + +/******************************************************************** + * Generate a bus wire declaration for a list of Verilog ports + * Output ports: the local_wire name + * Input ports: the driving ports + * When there are more than two ports, a bus wiring will be created + * {, , ... } + *******************************************************************/ +std::string generate_verilog_local_wire(const BasicPort& output_port, + const std::vector& input_ports) { + /* Try to combine the ports */ + std::vector combined_input_ports = combine_verilog_ports(input_ports); + + /* If we have more than 1 port in the combined ports , + * output a local wire */ + VTR_ASSERT(0 < combined_input_ports.size()); + + /* Must check: the port width matches */ + size_t input_ports_width = 0; + for (const auto& port : combined_input_ports) { + /* We must have valid ports! */ + VTR_ASSERT( 0 < port.get_width() ); + input_ports_width += port.get_width(); + } + VTR_ASSERT( input_ports_width == output_port.get_width() ); + + std::string wire_str; + wire_str += generate_verilog_port(VERILOG_PORT_WIRE, output_port); + wire_str += " = "; + wire_str += generate_verilog_ports(combined_input_ports); + wire_str += ";"; + + return wire_str; +} + +/******************************************************************** + * Generate a wire connection, that assigns constant values to a + * Verilog port + *******************************************************************/ +void print_verilog_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Must check: the port width matches */ + VTR_ASSERT( const_values.size() == output_port.get_width() ); + + fp << "\t"; + fp << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << " = "; + fp << const_values.size() << "'b"; + for (const auto& val : const_values) { + fp << val; + } + fp << ";" << std::endl; +} + +/******************************************************************** + * Generate a wire connection for two Verilog ports + * using "assign" syntax + *******************************************************************/ +void print_verilog_wire_connection(std::fstream& fp, + const BasicPort& output_port, + const BasicPort& input_port) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Must check: the port width matches */ + VTR_ASSERT( input_port.get_width() == output_port.get_width() ); + + fp << "\t"; + fp << "assign "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << " = "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); + fp << ";" << std::endl; +} + +/******************************************************************** + * Generate an instance of a buffer module + * with given information about the input and output ports of instance + * + * Buffer instance + * +----------------------------------------+ + * instance_input_port --->| buffer_input_port buffer_output_port|----> instance_output_port + * +----------------------------------------+ + * + * Restrictions: + * Buffer must have only 1 input (non-global) port and 1 output (non-global) port + *******************************************************************/ +void print_verilog_buffer_instance(std::fstream& fp, + ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const ModuleId& parent_module_id, + const CircuitModelId& buffer_model, + const BasicPort& instance_input_port, + const BasicPort& instance_output_port) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Create a port-to-port map */ + std::map buffer_port2port_name_map; + + /* Build the link between buffer_input_port[0] and output_node_pre_buffer + * Build the link between buffer_output_port[0] and output_node_bufferred + */ + { /* Create a code block to accommodate the local variables */ + std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]); + buffer_port2port_name_map[module_input_port_name] = instance_input_port; + std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]); + buffer_port2port_name_map[module_output_port_name] = instance_output_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, parent_module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model)); + + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(parent_module_id, buffer_module_id); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 328a87831..02430d7ec 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -44,4 +44,26 @@ std::vector combine_verilog_ports(const std::vector& ports std::string generate_verilog_ports(const std::vector& merged_ports); +BasicPort generate_verilog_bus_port(const std::vector& input_ports, + const std::string& bus_port_name); + +std::string generate_verilog_local_wire(const BasicPort& output_port, + const std::vector& input_ports); + +void print_verilog_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values); + +void print_verilog_wire_connection(std::fstream& fp, + const BasicPort& output_port, + const BasicPort& input_port); + +void print_verilog_buffer_instance(std::fstream& fp, + ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const ModuleId& parent_module_id, + const CircuitModelId& buffer_model, + const BasicPort& instance_input_port, + const BasicPort& instance_output_port); + #endif From d64bb1834679e219934f4897f4b44838afe7233c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 7 Sep 2019 12:36:22 -0400 Subject: [PATCH 176/482] Separated Modelsim tcl script generation --- openfpga_flow/misc/modelsim_template.j2 | 8 + openfpga_flow/scripts/run_modelsim.py | 86 +++++ .../verilog/verilog_formality_autodeck.c | 302 +++++++++--------- 3 files changed, 252 insertions(+), 144 deletions(-) create mode 100644 openfpga_flow/misc/modelsim_template.j2 create mode 100644 openfpga_flow/scripts/run_modelsim.py diff --git a/openfpga_flow/misc/modelsim_template.j2 b/openfpga_flow/misc/modelsim_template.j2 new file mode 100644 index 000000000..cfa43d11c --- /dev/null +++ b/openfpga_flow/misc/modelsim_template.j2 @@ -0,0 +1,8 @@ +read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN} } +set_top r:${SOURCE_TOP_DIR} +read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN} } + +set_top i:${IMPL_TOP_DIR} +match +${MATCH_MODUEL_LIST} +verify diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py new file mode 100644 index 000000000..e8dca5cb4 --- /dev/null +++ b/openfpga_flow/scripts/run_modelsim.py @@ -0,0 +1,86 @@ +from string import Template +import sys +import os +import argparse +import subprocess +import logging +from pprint import pprint + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configure logging system +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +logging.basicConfig(level=logging.INFO, stream=sys.stdout, + format='%(levelname)s (%(threadName)10s) - %(message)s') +logger = logging.getLogger('Modelsim_run_log') + +parser = argparse.ArgumentParser() +parser.add_argument('files', nargs='+') +parser.add_argument('--modelsim_template', type=str, + help="Modelsim verification template file") +parser.add_argument('--run_sim', action="store_true", + help="Execute generated script in formality") +args = parser.parse_args() + + +if not args.modelsim_template: + task_script_dir = os.path.dirname(os.path.abspath(__file__)) + args.modelsim_template = os.path.join(task_script_dir, os.pardir, + "misc", "modelsim_template.j2") + +args.modelsim_template = os.path.abspath(args.modelsim_template) + + +def main(): + for eachFile in args.files: + eachFile = os.path.abspath(eachFile) + directory = os.path.dirname(eachFile) + os.chdir(directory) + with open(eachFile, 'r') as fp: + lines = fp.read().split("\n") + SplitL = [indx for indx, eachL in enumerate(lines) if eachL == ""] + SplitL = list(zip([0] + SplitL[:-1], SplitL)) + for indx, eachSection in enumerate(SplitL): + SplitL[indx] = list(filter(None, lines[slice(*eachSection)])) + + match_str = "set_user_match r:%s i:%s -type port -noninverted" + lables = {"SOURCE_DESIGN": " ".join(SplitL[0]), + "SOURCE_TOP_DIR": "/WORK/" + " ".join(SplitL[1]), + "IMPL_DESIGN": " ".join(SplitL[2]), + "IMPL_TOP_DIR": "/WORK/" + " ".join(SplitL[3]), + "MATCH_MODUEL_LIST": "\n".join([match_str % tuple(eachPort.split()) for eachPort in SplitL[4]]) + } + + tmpl = Template(open(args.modelsim_template, encoding='utf-8').read()) + with open("Output.tcl", 'w', encoding='utf-8') as tclout: + tclout.write(tmpl.substitute(lables)) + if args.run_sim: + formality_run_string = ["formality", "-file", "Output.tcl"] + run_command("Modelsim run", "modelsim_run.log", formality_run_string) + else: + with open("Output.tcl", 'r', encoding='utf-8') as tclout: + print(tclout.read()) + + +def run_command(taskname, logfile, command, exit_if_fail=True): + logger.info("Launching %s " % taskname) + with open(logfile, 'w+') as output: + try: + output.write(" ".join(command)+"\n") + process = subprocess.run(command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.error("%s run failed with returncode %d" % + (taskname, process.returncode)) + except (Exception, subprocess.CalledProcessError) as e: + logger.exception("failed to execute %s" % taskname) + return None + logger.info("%s is written in file %s" % (taskname, logfile)) + return process.stdout + + +if __name__ == "__main__": + main() diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index db4de023d..0be59a137 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -39,203 +39,217 @@ #include "verilog_routing.h" #include "verilog_tcl_utils.h" - -static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){ - int i, j; -// char* tmp = NULL; - const t_pb_type *pb_type; - t_mode *mode; - t_pb_graph_node * node; -// char* index = NULL; +static void searching_used_latch(FILE *fp, t_pb *pb, int pb_index, char *chomped_circuit_name, char *inst_name) +{ + int i, j; + // char* tmp = NULL; + const t_pb_type *pb_type; + t_mode *mode; + t_pb_graph_node *node; + // char* index = NULL; - pb_type = pb->pb_graph_node->pb_type; - node = pb->pb_graph_node->physical_pb_graph_node; - mode = &pb_type->modes[pb->mode]; + pb_type = pb->pb_graph_node->pb_type; + node = pb->pb_graph_node->physical_pb_graph_node; + mode = &pb_type->modes[pb->mode]; -// tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index))))); -// tmp = ff_hierarchy; -// index = my_strcat("_", my_strcat(my_itoa(pb_index), "_")); + // tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index))))); + // tmp = ff_hierarchy; + // index = my_strcat("_", my_strcat(my_itoa(pb_index), "_")); - if (pb_type->num_modes > 0) { - for (i = 0; i < mode->num_pb_type_children; i++) { - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { -// if(strcmp(pb_type->name, mode->name) != 0) -// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index))); - if(pb->child_pbs[i][j].name != NULL) - searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name); - } - } - } else if((pb_type->class_type == LATCH_CLASS) && (pb->name)){ -// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_")))); - fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name, - pb->name, - inst_name, - gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node) ); - } - //free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp - return; + if (pb_type->num_modes > 0) + { + for (i = 0; i < mode->num_pb_type_children; i++) + { + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) + { + // if(strcmp(pb_type->name, mode->name) != 0) + // tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index))); + if (pb->child_pbs[i][j].name != NULL) + searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name); + } + } + } + else if ((pb_type->class_type == LATCH_CLASS) && (pb->name)) + { + // tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_")))); + fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name, + pb->name, + inst_name, + gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node)); + } + //free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp + return; } -static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){ - t_pb* pb; - char* inst_name = NULL; - const t_pb_type *pb_type; - t_mode *mode; - int i, j, x_pos, y_pos; - char* grid_x = NULL; - char* grid_y = NULL; +static void clb_iteration(FILE *fp, char *chomped_circuit_name, int h) +{ + t_pb *pb; + char *inst_name = NULL; + const t_pb_type *pb_type; + t_mode *mode; + int i, j, x_pos, y_pos; + char *grid_x = NULL; + char *grid_y = NULL; - x_pos = block[h].x; - y_pos = block[h].y; + x_pos = block[h].x; + y_pos = block[h].y; - pb = (t_pb*) block[h].pb; + pb = (t_pb *)block[h].pb; - pb_type = pb->pb_graph_node->pb_type; - mode = &pb_type->modes[pb->mode]; + pb_type = pb->pb_graph_node->pb_type; + mode = &pb_type->modes[pb->mode]; - grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_")); - grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_")); + grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_")); + grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_")); - - if (strcmp(pb_type->name, FILL_TYPE->name) == 0) { - inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid",my_strcat(grid_x, my_strcat(grid_y, "/" ))))))); - if (pb_type->num_modes > 0) { - for (i = 0; i < mode->num_pb_type_children; i++) { - inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_"))))); - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { - /* If child pb is not used but routing is used, I must print things differently */ - if ((pb->child_pbs[i] != NULL) - && (pb->child_pbs[i][j].name != NULL)) { - searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name); - } - } - } - } - } - return; + if (strcmp(pb_type->name, FILL_TYPE->name) == 0) + { + inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid", my_strcat(grid_x, my_strcat(grid_y, "/"))))))); + if (pb_type->num_modes > 0) + { + for (i = 0; i < mode->num_pb_type_children; i++) + { + inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_"))))); + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) + { + /* If child pb is not used but routing is used, I must print things differently */ + if ((pb->child_pbs[i] != NULL) && (pb->child_pbs[i][j].name != NULL)) + { + searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name); + } + } + } + } + } + return; } -static void match_registers(FILE *fp, char* chomped_circuit_name) { - int h; - - for(h = 0; h < copy_nb_clusters; h++) - clb_iteration(fp, chomped_circuit_name, h); -/* for(h = 0; h < copy_nb_clusters; h++){ - free_cb(copy_clb[h].pb); - free(copy_clb[h].name); - free(copy_clb[h].nets); - free(copy_clb[h].pb); - }*/ -// free(copy_clb); -// free(block); - return; -} - -static -void formality_include_user_defined_verilog_netlists(FILE* fp, - t_spice spice) { +static void formality_include_user_defined_verilog_netlists(FILE *fp, + t_spice spice) +{ int i; /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid File Handler!\n", + if (NULL == fp) + { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); exit(1); } /* Include user-defined sub-circuit netlist */ - for (i = 0; i < spice.num_include_netlist; i++) { - if (0 == spice.include_netlists[i].included) { + for (i = 0; i < spice.num_include_netlist; i++) + { + if (0 == spice.include_netlists[i].included) + { assert(NULL != spice.include_netlists[i].path); - fprintf(fp, "%s ", spice.include_netlists[i].path); + fprintf(fp, "%s \n", spice.include_netlists[i].path); spice.include_netlists[i].included = 1; - } else { + } + else + { assert(1 == spice.include_netlists[i].included); } - } + } return; } -void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, - char* fm_dir_formatted, - char* src_dir_formatted, - char* chomped_circuit_name, - t_spice spice){ - int iblock; - char* formality_script_file_name = NULL; - char* benchmark_path = NULL; - char* original_output_name = NULL; -/* int output_length; */ -/* int pos; */ - FILE* fp = NULL; +void write_formality_script(t_syn_verilog_opts fpga_verilog_opts, + char *fm_dir_formatted, + char *src_dir_formatted, + char *chomped_circuit_name, + t_spice spice) +{ + int iblock, h; + char *formScriptfp = NULL; + char *benchmark_path = NULL; + char *original_output_name = NULL; + /* int output_length; */ + /* int pos; */ + FILE *fp = NULL; - if(TRUE == fpga_verilog_opts.print_autocheck_top_testbench){ + if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) + { benchmark_path = fpga_verilog_opts.reference_verilog_benchmark_file; - } else { + } + else + { benchmark_path = "Insert verilog benchmark path"; } - formality_script_file_name = my_strcat(fm_dir_formatted, my_strcat(chomped_circuit_name, formality_script_name_postfix)); - fp = fopen(formality_script_file_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create formality script %s", - __FILE__, __LINE__, formality_script_file_name); - exit(1); - } + formScriptfp = my_strcat(fm_dir_formatted, + my_strcat(chomped_circuit_name, + formality_script_name_postfix)); + fp = fopen(formScriptfp, "w"); + if (NULL == fp) + { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create formality script %s", + __FILE__, __LINE__, formScriptfp); + exit(1); + } /* Load Verilog benchmark as reference */ - fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path); + fprintf(fp, "%s\n\n", benchmark_path); + /* Set reference top */ - fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name); + fprintf(fp, "%s\n\n", chomped_circuit_name); + /* Load generated verilog as implemnetation */ - fprintf(fp, "read_verilog -container i -libname WORK -05 { "); - fprintf(fp, "%s%s%s ", src_dir_formatted, - chomped_circuit_name, - verilog_top_postfix); - fprintf(fp, "%s%s%s ", src_dir_formatted, - chomped_circuit_name, - formal_verification_verilog_file_postfix); + fprintf(fp, "%s%s%s\n", src_dir_formatted, chomped_circuit_name, + verilog_top_postfix); + + fprintf(fp, "%s%s%s\n", src_dir_formatted, + chomped_circuit_name, + formal_verification_verilog_file_postfix); + init_include_user_defined_verilog_netlists(spice); formality_include_user_defined_verilog_netlists(fp, spice); - fprintf(fp, "%s%s%s ", src_dir_formatted, - default_rr_dir_name, - routing_verilog_file_name); - fprintf(fp, "%s%s%s ", src_dir_formatted, - default_lb_dir_name, - logic_block_verilog_file_name); - fprintf(fp, "%s%s%s ", src_dir_formatted, - default_submodule_dir_name, - submodule_verilog_file_name); - fprintf(fp, "}\n"); + fprintf(fp, "%s%s%s\n", src_dir_formatted, + default_rr_dir_name, + routing_verilog_file_name); + fprintf(fp, "%s%s%s\n", src_dir_formatted, + default_lb_dir_name, + logic_block_verilog_file_name); + fprintf(fp, "%s%s%s\n", src_dir_formatted, + default_submodule_dir_name, + submodule_verilog_file_name); + fprintf(fp, "\n"); + /* Set implementation top */ - fprintf(fp, "set_top i:/WORK/%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix)); + fprintf(fp, "%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix)); /* Run matching */ - fprintf(fp, "match\n"); + fprintf(fp, "\n"); /* Add manual matching for the outputs */ - for (iblock = 0; iblock < num_logical_blocks; iblock++) { + for (iblock = 0; iblock < num_logical_blocks; iblock++) + { original_output_name = NULL; - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { + if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) + { /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_OUTPAD == logical_block[iblock].type){ + assert((VPACK_INPAD == logical_block[iblock].type) || (VPACK_OUTPAD == logical_block[iblock].type)); + if (VPACK_OUTPAD == logical_block[iblock].type) + { /* output_length = strlen(logical_block[iblock].name); */ original_output_name = logical_block[iblock].name + 4; /* printf("%s", original_output_name); */ - fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n", + // fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n", + fprintf(fp, "/WORK/%s/%s /WORK/%s/%s[0]\n", chomped_circuit_name, - original_output_name, + original_output_name, my_strcat(chomped_circuit_name, formal_verification_top_postfix), - my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); + my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); } } } - match_registers(fp, chomped_circuit_name); + + for (h = 0; h < copy_nb_clusters; h++) + clb_iteration(fp, chomped_circuit_name, h); + /* Run verification */ - fprintf(fp, "verify\n"); + fprintf(fp, "\n"); /* Script END */ fclose(fp); From 62853c092f93c05f7a726e22a1146a299b642d69 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Sep 2019 15:16:29 -0600 Subject: [PATCH 177/482] refactoring local encoders. Ready to plug in --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 20 +- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + vpr7_x2p/vpr/SRC/device/decoder_library.cpp | 104 +++++++++ vpr7_x2p/vpr/SRC/device/decoder_library.h | 88 +++++++ vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h | 18 ++ .../vpr/SRC/device/decoder_library_utils.cpp | 53 +++++ .../vpr/SRC/device/decoder_library_utils.h | 14 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 21 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 3 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 35 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 5 + .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 18 ++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 5 + .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 216 ++++++++++++++++++ .../SRC/fpga_x2p/verilog/verilog_decoders.h | 24 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 4 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 3 + .../fpga_x2p/verilog/verilog_writer_utils.cpp | 117 ++++++++-- .../fpga_x2p/verilog/verilog_writer_utils.h | 17 +- 19 files changed, 733 insertions(+), 33 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/device/decoder_library.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/decoder_library.h create mode 100644 vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h create mode 100644 vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/device/decoder_library_utils.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 95a172838..d22574e09 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -253,7 +253,7 @@ enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(con return pass_gate_logic_types_[model_id]; } -/* Return the multiplex structure of a circuit model */ +/* Return the type of multiplexing structure of a circuit model */ enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -263,7 +263,7 @@ enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& return mux_structure_[model_id]; } - +/* Return the number of levels of multiplexing structure of a circuit model */ size_t CircuitLibrary::mux_num_levels(const CircuitModelId& model_id) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -275,7 +275,7 @@ size_t CircuitLibrary::mux_num_levels(const CircuitModelId& model_id) const { } /* Return if additional constant inputs are required for a circuit model - * Only applicable for MUX circuit model + * Only applicable for MUX/LUT circuit model */ bool CircuitLibrary::mux_add_const_input(const CircuitModelId& model_id) const { /* validate the model_id */ @@ -288,7 +288,7 @@ bool CircuitLibrary::mux_add_const_input(const CircuitModelId& model_id) const { } /* Return if additional constant inputs are required for a circuit model - * Only applicable for MUX circuit model + * Only applicable for MUX/LUT circuit model */ size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& model_id) const { /* validate the model_id */ @@ -302,6 +302,18 @@ size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& model_id) con return mux_const_input_values_[model_id]; } +/* Return if local encoders are used for a circuit model + * Only applicable for MUX/LUT circuit model + */ +bool CircuitLibrary::mux_use_local_encoder(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + return mux_use_local_encoder_[model_id]; +} + /* Return the type of gate for a circuit model * Only applicable for GATE circuit model */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index a344dc8c7..d74c61a45 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -236,6 +236,7 @@ class CircuitLibrary { size_t mux_num_levels(const CircuitModelId& model_id) const; bool mux_add_const_input(const CircuitModelId& model_id) const; size_t mux_const_input_value(const CircuitModelId& model_id) const; + bool mux_use_local_encoder(const CircuitModelId& model_id) const; /* Gate information */ enum e_spice_model_gate_type gate_type(const CircuitModelId& model_id) const; /* Buffer information */ diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library.cpp b/vpr7_x2p/vpr/SRC/device/decoder_library.cpp new file mode 100644 index 000000000..ba869712f --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/decoder_library.cpp @@ -0,0 +1,104 @@ +/*************************************************************************************** + * This file includes memeber functions for data structure DecoderLibrary + **************************************************************************************/ +#include "vtr_assert.h" +#include "decoder_library.h" + +/*************************************************************************************** + * Public Accessors: Aggregators + **************************************************************************************/ +DecoderLibrary::decoder_range DecoderLibrary::decoders() const { + return vtr::make_range(decoder_ids_.begin(), decoder_ids_.end()); +} + +/*************************************************************************************** + * Public Accessors: Data query + **************************************************************************************/ +/* Get the size of address input of a decoder */ +size_t DecoderLibrary::addr_size(const DecoderId& decoder) const { + VTR_ASSERT_SAFE(valid_decoder_id(decoder)); + return addr_sizes_[decoder]; +} + +/* Get the size of data output of a decoder */ +size_t DecoderLibrary::data_size(const DecoderId& decoder) const { + VTR_ASSERT_SAFE(valid_decoder_id(decoder)); + return data_sizes_[decoder]; +} + +/* Get the flag if a decoder includes an ENABLE signal */ +bool DecoderLibrary::use_enable(const DecoderId& decoder) const { + VTR_ASSERT_SAFE(valid_decoder_id(decoder)); + return use_enable_[decoder]; +} + +/* Get the flag if a decoder includes an DATA_IN signal */ +bool DecoderLibrary::use_data_in(const DecoderId& decoder) const { + VTR_ASSERT_SAFE(valid_decoder_id(decoder)); + return use_data_in_[decoder]; +} + +/* Get the flag if a decoder includes a data_inv port which is an inversion of the regular data output port */ +bool DecoderLibrary::use_data_inv_port(const DecoderId& decoder) const { + VTR_ASSERT_SAFE(valid_decoder_id(decoder)); + return use_data_inv_port_[decoder]; +} + +/* Find a decoder to the library, with the specification. + * If found, return the id of decoder. + * If not found, return an invalid id of decoder + * To avoid duplicated decoders, this function should be used before adding a decoder + * Example: + * DecoderId decoder_id == decoder_lib.find_decoder(); + * if (DecoderId::INVALID() == decoder_id) { + * // Add decoder + * } + */ +DecoderId DecoderLibrary::find_decoder(const size_t& addr_size, + const size_t& data_size, + const bool& use_enable, + const bool& use_data_in, + const bool& use_data_inv_port) const { + for (auto decoder : decoders()) { + if ( (addr_size == addr_sizes_[decoder]) + && (data_size == data_sizes_[decoder]) + && (use_enable == use_enable_[decoder]) + && (use_data_in == use_data_in_[decoder]) + && (use_data_inv_port == use_data_inv_port_[decoder]) ) { + return decoder; + } + } + + /* Not found, return an invalid id by default */ + return DecoderId::INVALID(); +} + +/*************************************************************************************** + * Public Validators + **************************************************************************************/ +/* Validate ids */ +bool DecoderLibrary::valid_decoder_id(const DecoderId& decoder) const { + return size_t(decoder) < decoder_ids_.size() && decoder_ids_[decoder] == decoder; +} + +/*************************************************************************************** + * Public Mutators : Basic Operations + **************************************************************************************/ +/* Add a decoder to the library */ +DecoderId DecoderLibrary::add_decoder(const size_t& addr_size, + const size_t& data_size, + const bool& use_enable, + const bool& use_data_in, + const bool& use_data_inv_port) { + DecoderId decoder = DecoderId(decoder_ids_.size()); + /* Push to the decoder list */ + decoder_ids_.push_back(decoder); + /* Resize the other related vectors */ + addr_sizes_.push_back(addr_size); + data_sizes_.push_back(data_size); + use_enable_.push_back(use_enable); + use_data_in_.push_back(use_data_in); + use_data_inv_port_.push_back(use_data_inv_port); + + return decoder; +} diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library.h b/vpr7_x2p/vpr/SRC/device/decoder_library.h new file mode 100644 index 000000000..c8eb1da7e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/decoder_library.h @@ -0,0 +1,88 @@ +/*************************************************************************************** + * This file includes key data structures to describe decoders which are used + * in FPGA fabrics + * A decoder is a circuit to convert a binary input to one-hot codes + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) + * All the decoders are assumed to follow the port map : + * + * Inputs + * | | ... | + * v v v + * +-----------+ + * / \ + * / Decoder \ + * +-----------------+ + * | | | ... | | | + * v v v v v v + * Outputs + + ***************************************************************************************/ + +#ifndef DECODER_LIBRARY_H +#define DECODER_LIBRARY_H + +#include "vtr_vector.h" +#include "vtr_range.h" +#include "decoder_library_fwd.h" + +class DecoderLibrary { + public: /* Types and ranges */ + typedef vtr::vector::const_iterator decoder_iterator; + + typedef vtr::Range decoder_range; + + public: /* Public accessors: Aggregates */ + /* Get all the decoders */ + decoder_range decoders() const; + + public: /* Public accessors: Data query */ + /* Get the size of address input of a decoder */ + size_t addr_size(const DecoderId& decoder) const; + /* Get the size of data output of a decoder */ + size_t data_size(const DecoderId& decoder) const; + /* Get the flag if a decoder includes an ENABLE signal */ + bool use_enable(const DecoderId& decoder) const; + /* Get the flag if a decoder includes an DATA_IN signal */ + bool use_data_in(const DecoderId& decoder) const; + /* Get the flag if a decoder includes a data_inv port which is an inversion of the regular data output port */ + bool use_data_inv_port(const DecoderId& decoder) const; + /* Find a decoder to the library, with the specification. + * If found, return the id of decoder. + * If not found, return an invalid id of decoder + * To avoid duplicated decoders, this function should be used before adding a decoder + * Example: + * DecoderId decoder_id == decoder_lib.find_decoder(); + * if (DecoderId::INVALID() == decoder_id) { + * // Add decoder + * } + */ + DecoderId find_decoder(const size_t& addr_size, + const size_t& data_size, + const bool& use_enable, + const bool& use_data_in, + const bool& use_data_inv_port) const; + + public: /* Public validators */ + /* valid ids */ + bool valid_decoder_id(const DecoderId& decoder) const; + + public: /* Private mutators : basic operations */ + /* Add a decoder to the library */ + DecoderId add_decoder(const size_t& addr_size, + const size_t& data_size, + const bool& use_enable, + const bool& use_data_in, + const bool& use_data_inv_port); + + private: /* Internal Data */ + vtr::vector decoder_ids_; + vtr::vector addr_sizes_; + vtr::vector data_sizes_; + vtr::vector use_enable_; + vtr::vector use_data_in_; + vtr::vector use_data_inv_port_; +}; + +#endif + diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h b/vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h new file mode 100644 index 000000000..1850dc27a --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h @@ -0,0 +1,18 @@ +/************************************************** + * This file includes only declarations for + * the data structures to describe decoders + * Please refer to decoder_library.h for more details + *************************************************/ +#ifndef DECODER_LIBRARY_FWD_H +#define DECODER_LIBRARY_FWD_H + +#include "vtr_strong_id.h" + +/* Strong Ids for MUXes */ +struct decoder_id_tag; + +typedef vtr::StrongId DecoderId; + +class DecoderLibrary; + +#endif diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp new file mode 100644 index 000000000..ca773819e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp @@ -0,0 +1,53 @@ +/*************************************************************************************** + * This file includes most utilized functions for the DecoderLibrary data structure + ***************************************************************************************/ +#include + +#include "vtr_assert.h" + +#include "decoder_library_utils.h" + +/*************************************************************************************** + * NOTE: This function is mainly designed for local decoders inside multiplexers + * Find the size of address lines for a decoder with a given data output size + * Addr lines + * | | ... | + * v v v + * +-----------+ + * / Local \ + * / Decoder \ + * +-----------------+ + * | | | ... | | | + * v v v v v v + * Data outputs + * + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) + * We plus 1, which is all-zero condition for outputs + ***************************************************************************************/ +size_t find_mux_local_decoder_addr_size(const size_t& data_size) { + /* Make sure we have a encoder which is at least 2 ! */ + VTR_ASSERT (2 <= data_size); + return ceil(log(data_size) / log(2)); +} + + +/*************************************************************************************** + * Try to find if the decoder already exists in the library, + * If there is no such decoder, add it to the library + ***************************************************************************************/ +DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, + const size_t data_size) { + size_t addr_size = find_mux_local_decoder_addr_size(data_size); + + DecoderId decoder_id = decoder_lib.find_decoder(addr_size, data_size, false, false, true); + + if (DecoderId::INVALID() == decoder_id) { + /* Add the decoder */ + return decoder_lib.add_decoder(addr_size, data_size, false, false, true); + } + + /* There is already a decoder in the library, return the decoder id */ + return decoder_id; +} diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h new file mode 100644 index 000000000..f0719f2e6 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h @@ -0,0 +1,14 @@ +/*************************************************************************************** + * Header file for most utilized functions for the DecoderLibrary data structure + ***************************************************************************************/ +#ifndef DECODER_LIBRARY_UTILS_H +#define DECODER_LIBRARY_UTILS_H + +#include "decoder_library.h" + +size_t find_mux_local_decoder_addr_size(const size_t& data_size); + +DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, + const size_t data_size); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 2f5cfa917..0389785f7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -1,8 +1,11 @@ -/************************************************ +/******************************************************************** * This file includes functions to * generate module/port names for Verilog * and SPICE netlists - ***********************************************/ + * + * IMPORTANT: keep all the naming functions in this file to be + * generic for both Verilog and SPICE generators + ********************************************************************/ #include "vtr_assert.h" #include "fpga_x2p_naming.h" @@ -77,3 +80,17 @@ std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circui return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix); } + +/************************************************ + * Generate the module name of a local decoder + * for multiplexer + ***********************************************/ +std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, + const size_t& data_size) { + std::string subckt_name = "decoder"; + subckt_name += std::to_string(addr_size); + subckt_name += "to"; + subckt_name += std::to_string(data_size); + + return subckt_name; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 3acf3574d..f429a9c32 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -25,4 +25,7 @@ std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circui const size_t& branch_mux_size, const std::string& posfix); +std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, + const size_t& data_size); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 53faf3ad7..c7a5df808 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -15,6 +15,7 @@ #include /* Include vpr structs*/ +#include "vtr_assert.h" #include "util.h" #include "physical_types.h" #include "vpr_types.h" @@ -632,6 +633,22 @@ char* my_ito1hot(int in_int, int bin_len) { return ret; } +/* Convert an integer to an one-hot encoding integer array */ +std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len) { + /* Make sure we do not have any overflow! */ + VTR_ASSERT ( (in_int <= bin_len) ); + + /* Initialize */ + std::vector ret(bin_len, 0); + + if (bin_len == in_int) { + return ret; /* all zero case */ + } + ret[in_int] = 1; /* Keep a good sequence of bits */ + + return ret; +} + /* Converter an integer to a binary string */ int* my_itobin_int(int in_int, int bin_len) { int* ret = (int*) my_calloc (bin_len, sizeof(int)); @@ -652,6 +669,24 @@ int* my_itobin_int(int in_int, int bin_len) { return ret; } +/* Converter an integer to a binary vector */ +std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len) { + std::vector ret(bin_len, 0); + + /* Make sure we do not have any overflow! */ + VTR_ASSERT ( (in_int < pow(2., bin_len)) ); + + size_t temp = in_int; + for (size_t i = 0; i < bin_len; i++) { + if (1 == temp % 2) { + ret[i] = 1; /* Keep a good sequence of bits */ + } + temp = temp / 2; + } + + return ret; +} + /* Converter an integer to a binary string */ char* my_itobin(int in_int, int bin_len) { char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 1a518f439..8d0408bcd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -2,6 +2,7 @@ #define FPGA_X2P_UTILS_H #include +#include #include "my_free_fwd.h" #include "rr_blocks_naming.h" @@ -65,10 +66,14 @@ t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, char* my_ito1hot(int in_int, int bin_len); +std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len); + char* my_itobin(int in_int, int bin_len); int* my_itobin_int(int in_int, int bin_len); +std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len); + char* my_itoa(int input); char* fpga_spice_create_one_subckt_filename(const char* file_name_prefix, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index f634af951..394dd85fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -99,6 +99,13 @@ size_t ModuleManager::num_instance(const ModuleId& parent_module, const ModuleId return 0; } +/* Find if a port is register */ +bool ModuleManager::port_is_register(const ModuleId& module, const ModulePortId& port) const { + /* validate both module id and port id*/ + VTR_ASSERT(valid_module_port_id(module, port)); + return port_is_register_[module][port]; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ @@ -123,6 +130,7 @@ ModuleId ModuleManager::add_module(const std::string& name) { port_ids_.emplace_back(); ports_.emplace_back(); port_types_.emplace_back(); + port_is_register_.emplace_back(); /* Register in the name-to-id map */ name_id_map_[name] = module; @@ -146,6 +154,7 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, port_ids_[module].push_back(port); ports_[module].push_back(port_info); port_types_[module].push_back(port_type); + port_is_register_[module].push_back(false); /* Update fast look-up for port */ port_lookup_[module][port_type].push_back(port); @@ -153,6 +162,15 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, return port; } +/* Set a port to be a register */ +void ModuleManager::set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register) { + /* Find the port */ + ModulePortId port = find_module_port(module, port_name); + /* Must find something, otherwise drop an error */ + VTR_ASSERT(ModulePortId::INVALID() != port); + port_is_register_[module][port] = is_register; +} + /* Add a child module to a parent module */ void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module) { /* Validate the id of both parent and child modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index b85681e3d..ae487153c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -45,12 +45,16 @@ class ModuleManager { ModuleId find_module(const std::string& name) const; /* Find the number of instances of a child module in the parent module */ size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const; + /* Find if a port is register */ + bool port_is_register(const ModuleId& module, const ModulePortId& port) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); /* Add a port to a module */ ModulePortId add_port(const ModuleId& module, const BasicPort& port_info, const enum e_module_port_type& port_type); + /* Set a port to be a register */ + void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register); /* Add a child module to a parent module */ void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); private: /* Private validators/invalidators */ @@ -68,6 +72,7 @@ class ModuleManager { vtr::vector> port_ids_; /* List of ports for each Module */ vtr::vector> ports_; /* List of ports for each Module */ vtr::vector> port_types_; /* Type of ports */ + vtr::vector> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: reg */ /* fast look-up for module */ std::map name_id_map_; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp new file mode 100644 index 000000000..a6a4c7bb2 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -0,0 +1,216 @@ +/*************************************************************************************** + * This file includes functions to generate Verilog modules of decoders + ***************************************************************************************/ +/* TODO: merge verilog_decoder.c to this source file and rename to verilog_decoder.cpp */ +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "decoder_library_utils.h" +#include "module_manager.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_decoders.h" + +/*************************************************************************************** + * Create a Verilog module for a decoder with a given output size + * + * Inputs + * | | ... | + * v v v + * +-----------+ + * / \ + * / Decoder \ + * +-----------------+ + * | | | ... | | | + * v v v v v v + * Outputs + * + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Considering this fact, there are only num_of_outputs conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) + ***************************************************************************************/ +static +void print_verilog_mux_local_decoder_module(std::fstream& fp, + ModuleManager& module_manager, + const DecoderLibrary& decoder_lib, + const DecoderId& decoder) { + /* Get the number of inputs */ + size_t addr_size = decoder_lib.addr_size(decoder); + size_t data_size = decoder_lib.data_size(decoder); + + /* Validate the FILE handler */ + check_file_handler(fp); + + /* TODO: create a name for the local encoder */ + std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each input port */ + BasicPort addr_port("addr", addr_size); + module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort data_port("data", data_size); + module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Data port is registered. It should be outputted as + * output reg [lsb:msb] data + */ + module_manager.set_port_is_register(module_id, data_port.get_name(), true); + /* Add data_in port */ + BasicPort data_inv_port("data_inv", data_size); + VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder)); + module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); + + /* Print the truth table of this decoder */ + /* Internal logics */ + /* We use a magic number -1 as the addr=1 should be mapped to ...1 + * Otherwise addr will map addr=1 to ..10 + * Note that there should be a range for the shift operators + * We should narrow the encoding to be applied to a given set of data + * This will lead to that any addr which falls out of the op code of data + * will give a all-zero code + * For example: + * data is 5-bit while addr is 3-bit + * data=8'b0_0000 will be encoded to addr=3'b001; + * data=8'b0_0001 will be encoded to addr=3'b010; + * data=8'b0_0010 will be encoded to addr=3'b011; + * data=8'b0_0100 will be encoded to addr=3'b100; + * data=8'b0_1000 will be encoded to addr=3'b101; + * data=8'b1_0000 will be encoded to addr=3'b110; + * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000; + */ + + fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl; + fp << "\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl; + /* Create a string for addr and data */ + for (size_t i = 0; i < data_size; ++i) { + /* TODO: give a namespace to the itobin function */ + fp << "\t\t" << generate_verilog_constant_values(my_itobin_vec(i, addr_size)); + fp << " : "; + fp << generate_verilog_port_constant_values(data_port, my_ito1hot_vec(i, data_size)); + fp << ";" << std::endl; + } + fp << "\t\t" << "default : "; + fp << generate_verilog_port_constant_values(data_port, my_ito1hot_vec(data_size - 1, data_size)); + fp << ";" << std::endl; + fp << "\t" << "endcase" << std::endl; + + print_verilog_wire_connection(fp, data_inv_port, data_port, true); + + print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); + + return; +} + + +/*************************************************************************************** + * This function will generate all the unique Verilog modules of local decoders for + * the multiplexers used in a FPGA fabric + * It will reach the goal in two steps: + * 1. Find the unique local decoders w.r.t. the number of inputs/outputs + * We will generate the subgraphs from the multiplexing graph of each multiplexers + * The number of memory bits is the number of outputs. + * From that we can infer the number of inputs of each local decoders. + * Here is an illustrative example of how local decoders are interfaced with multi-level MUXes + * + * +---------+ +---------+ + * | Local | | Local | + * | Decoder | | Decoder | + * | A | | B | + * +---------+ +---------+ + * | ... | | ... | + * v v v v + * +--------------+ +--------------+ + * | MUX Level 0 |--->| MUX Level 1 | + * +--------------+ +--------------+ + * 2. Generate local decoder Verilog modules using behavioral description. + * Note that the implementation of local decoders can be dependent on the technology + * and standard cell libraries. + * Therefore, behavioral Verilog is used and the local decoders should be synthesized + * before running the back-end flow for FPGA fabric + * See more details in the function print_verilog_mux_local_decoder() for more details + ***************************************************************************************/ +void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const std::string& verilog_dir, + const std::string& submodule_dir) { + + /* TODO: Generate modules into a .bak file now. Rename after it is verified */ + std::string verilog_fname(submodule_dir + local_encoder_verilog_file_name); + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for local decoders for multiplexers (%s)...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Local Decoders for Multiplexers"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a library for local encoders with different sizes */ + DecoderLibrary decoder_lib; + + /* Find unique local decoders for unique branches shared by the multiplexers */ + for (auto mux : mux_lib.muxes()) { + /* Local decoders are need only when users specify them */ + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* If this MUX does not need local decoder, we skip it */ + if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) { + continue; + } + + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + /* Create a mux graph for the branch circuit */ + std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); + /* Add the decoder to the decoder library */ + for (auto branch_mux_graph : branch_mux_graphs) { + /* Try to find if the decoder already exists in the library, + * If there is no such decoder, add it to the library + */ + add_mux_local_decoder_to_library(decoder_lib, branch_mux_graph.num_inputs()); + } + } + + /* Generate Verilog modules for the found unique local encoders */ + for (const auto& decoder : decoder_lib.decoders()) { + print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder); + } + + /* Close the file steam */ + fp.close(); + + /* TODO: Add fname to the linked list when debugging is finished */ + /* + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); + */ +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h new file mode 100644 index 000000000..88877b9e0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h @@ -0,0 +1,24 @@ +/*************************************************************************************** + * Header file for verilog_decoders.cpp + ***************************************************************************************/ +/* TODO: merge to verilog_decoder.h */ + +#ifndef VERILOG_DECODERS_H +#define VERILOG_DECODERS_H + +/* Include other header files which are dependency on the function declared below */ +#include +#include + +#include "circuit_library.h" +#include "mux_graph.h" +#include "mux_library.h" +#include "module_manager.h" + +void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const std::string& verilog_dir, + const std::string& submodule_dir); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 7c430f1d2..9426c258c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -1176,7 +1176,7 @@ void generate_verilog_cmos_mux_module_input_buffers(ModuleManager& module_manage print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to MUX module input -----")); /* Short wire all the datapath inputs to the MUX inputs */ - print_verilog_wire_connection(fp, instance_output_port, instance_input_port); + print_verilog_wire_connection(fp, instance_output_port, instance_input_port, false); print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to MUX module input -----")); fp << std::endl; @@ -1255,7 +1255,7 @@ void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manag print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure output to MUX module output -----")); /* Short wire all the datapath inputs to the MUX inputs */ - print_verilog_wire_connection(fp, instance_output_port, instance_input_port); + print_verilog_wire_connection(fp, instance_output_port, instance_input_port, false); print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure output to MUX module output -----")); fp << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index cea48799d..3f610a05d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -42,6 +42,7 @@ #include "mux_utils.h" #include "verilog_mux.h" #include "verilog_essential_gates.h" +#include "verilog_decoders.h" /***** Subroutines *****/ @@ -3560,6 +3561,8 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + + print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 2. LUTes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index e5067c838..674ce713e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -72,13 +72,45 @@ void print_verilog_comment(std::fstream& fp, /************************************************ * Print a Verilog module definition + * We use the following format: + * module (); ***********************************************/ void print_verilog_module_definition(std::fstream& fp, - const std::string& module_name) { + const ModuleManager& module_manager, const ModuleId& module_id) { check_file_handler(fp); - print_verilog_comment(fp, std::string("----- Verilog module for " + module_name + " -----")); - fp << "module " << module_name << "(" << std::endl; + print_verilog_comment(fp, std::string("----- Verilog module for " + module_manager.module_name(module_id) + " -----")); + + std::string module_head_line = "module " + module_manager.module_name(module_id) + "("; + fp << module_head_line; + + /* port type2type mapping */ + std::map port_type2type_map; + port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT; + + /* Port sequence: global, inout, input, output and clock ports, */ + size_t port_cnt = 0; + for (const auto& kv : port_type2type_map) { + for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { + if (0 != port_cnt) { + /* Do not dump a comma for the first port */ + fp << "," << std::endl; + } + /* Create a space for "module " except the first line! */ + if (0 != port_cnt) { + std::string port_whitespace(module_head_line.length(), ' '); + fp << port_whitespace; + } + /* Print port */ + fp << generate_verilog_port(kv.second, port); + port_cnt++; + } + } + fp << ");" << std::endl; } /************************************************ @@ -97,33 +129,45 @@ void print_verilog_module_ports(std::fstream& fp, port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_INPUT; /* Port sequence: global, inout, input, output and clock ports, */ - size_t port_cnt = 0; for (const auto& kv : port_type2type_map) { for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { - if (0 != port_cnt) { - /* Do not dump a comma for the first port */ - fp << "," << std::endl; + /* Print port */ + fp << "//----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; + fp << generate_verilog_port(kv.second, port); + fp << ";" << std::endl; + } + } + + /* Output any port that is registered */ + fp << "//----- Registered ports -----" << std::endl; + for (const auto& kv : port_type2type_map) { + for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { + /* Skip the ports that are not registered */ + ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); + VTR_ASSERT(ModulePortId::INVALID() != port_id); + if (false == module_manager.port_is_register(module_id, port_id)) { + continue; } /* Print port */ - fp << "\t//----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; - fp << "\t" << generate_verilog_port(kv.second, port); - port_cnt++; + fp << generate_verilog_port(VERILOG_PORT_REG, port); + fp << ";" << std::endl; } } } /************************************************ * Print a Verilog module declaration (definition + port list + * We use the following format: + * module (); + * ***********************************************/ void print_verilog_module_declaration(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id) { check_file_handler(fp); - print_verilog_module_definition(fp, module_manager.module_name(module_id)); + print_verilog_module_definition(fp, module_manager, module_id); print_verilog_module_ports(fp, module_manager, module_id); - - fp << std::endl << ");" << std::endl; } /************************************************ @@ -404,6 +448,35 @@ std::string generate_verilog_local_wire(const BasicPort& output_port, return wire_str; } +/******************************************************************** + * Generate a string for a constant value in Verilog format: + * <#.of bits>'b + *******************************************************************/ +std::string generate_verilog_constant_values(const std::vector& const_values) { + std::string str = std::to_string(const_values.size()); + str += "'b"; + for (const auto& val : const_values) { + str += std::to_string(val); + } + return str; +} + +/******************************************************************** + * Generate a verilog port with a deposite of constant values + ********************************************************************/ +std::string generate_verilog_port_constant_values(const BasicPort& output_port, + const std::vector& const_values) { + std::string port_str; + + /* Must check: the port width matches */ + VTR_ASSERT( const_values.size() == output_port.get_width() ); + + port_str = generate_verilog_port(VERILOG_PORT_CONKT, output_port); + port_str += " = "; + port_str += generate_verilog_constant_values(const_values); + return port_str; +} + /******************************************************************** * Generate a wire connection, that assigns constant values to a * Verilog port @@ -414,17 +487,9 @@ void print_verilog_wire_constant_values(std::fstream& fp, /* Make sure we have a valid file handler*/ check_file_handler(fp); - /* Must check: the port width matches */ - VTR_ASSERT( const_values.size() == output_port.get_width() ); - fp << "\t"; fp << "assign "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << " = "; - fp << const_values.size() << "'b"; - for (const auto& val : const_values) { - fp << val; - } + fp << generate_verilog_port_constant_values(output_port, const_values); fp << ";" << std::endl; } @@ -434,7 +499,8 @@ void print_verilog_wire_constant_values(std::fstream& fp, *******************************************************************/ void print_verilog_wire_connection(std::fstream& fp, const BasicPort& output_port, - const BasicPort& input_port) { + const BasicPort& input_port, + const bool& inverted) { /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -445,6 +511,11 @@ void print_verilog_wire_connection(std::fstream& fp, fp << "assign "; fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); fp << " = "; + + if (true == inverted) { + fp << "~"; + } + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); fp << ";" << std::endl; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 02430d7ec..a3d8e7206 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -10,6 +10,13 @@ #include "device_port.h" #include "module_manager.h" +/* Tips: for naming your function in this header/source file + * If a function outputs to a file, its name should begin with "print_verilog" + * If a function creates a string without outputting to a file, its name should begin with "generate_verilog" + * Please show respect to this naming convention, in order to keep a clean header/source file + * as well maintain a easy way to identify the functions + */ + void print_verilog_file_header(std::fstream& fp, const std::string& usage); @@ -20,7 +27,7 @@ void print_verilog_comment(std::fstream& fp, const std::string& comment); void print_verilog_module_definition(std::fstream& fp, - const std::string& module_name); + const ModuleManager& module_manager, const ModuleId& module_id); void print_verilog_module_ports(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id); @@ -50,13 +57,19 @@ BasicPort generate_verilog_bus_port(const std::vector& input_ports, std::string generate_verilog_local_wire(const BasicPort& output_port, const std::vector& input_ports); +std::string generate_verilog_constant_values(const std::vector& const_values); + +std::string generate_verilog_port_constant_values(const BasicPort& output_port, + const std::vector& const_values); + void print_verilog_wire_constant_values(std::fstream& fp, const BasicPort& output_port, const std::vector& const_values); void print_verilog_wire_connection(std::fstream& fp, const BasicPort& output_port, - const BasicPort& input_port); + const BasicPort& input_port, + const bool& inverted); void print_verilog_buffer_instance(std::fstream& fp, ModuleManager& module_manager, From 5f561ef5e3b71e67e503b0f5302168da9b8cb084 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Sep 2019 15:26:47 -0600 Subject: [PATCH 178/482] pass regression test when plug in refactored local encoders --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp | 6 ++---- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 2 ++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index a6a4c7bb2..5325af039 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -159,7 +159,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, /* TODO: Generate modules into a .bak file now. Rename after it is verified */ std::string verilog_fname(submodule_dir + local_encoder_verilog_file_name); - verilog_fname += ".bak"; + /* verilog_fname += ".bak"; */ /* Create the file stream */ std::fstream fp; @@ -209,8 +209,6 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, fp.close(); /* TODO: Add fname to the linked list when debugging is finished */ - /* - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); - */ + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 3f610a05d..b7f16b05d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3559,8 +3559,10 @@ void dump_verilog_submodules(ModuleManager& module_manager, verilog_dir, submodule_dir); vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); + /* dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + */ print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); From 82683d49cf77cb9a1c3ae2d2ee7d60af88a66dca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Sep 2019 15:34:20 -0600 Subject: [PATCH 179/482] remove legacy codes of local encoders --- .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 5 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 229 ------------------ 2 files changed, 1 insertion(+), 233 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index 5325af039..d24773c49 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -156,10 +156,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir) { - - /* TODO: Generate modules into a .bak file now. Rename after it is verified */ std::string verilog_fname(submodule_dir + local_encoder_verilog_file_name); - /* verilog_fname += ".bak"; */ /* Create the file stream */ std::fstream fp; @@ -208,7 +205,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, /* Close the file steam */ fp.close(); - /* TODO: Add fname to the linked list when debugging is finished */ + /* Add fname to the linked list when debugging is finished */ submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index b7f16b05d..0a2319edc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2327,230 +2327,6 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, return; } -/*************************************************************************************** - * Create a Verilog module for a encoder with a given output size - * Inputs - * | | | | | - * +-----------+ - * / \ - * / Encoder \ - * +-----------------+ - * | | | | | | | | - * Outputs - * - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) - ***************************************************************************************/ -static -void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) { - /* Make sure we have a encoder which is at least 2 ! */ - assert (2 <= num_outputs); - - /* Get the number of inputs */ - int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); - - /* Validate the FILE handler */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]Invalid file handler!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Print the name of encoder */ - fprintf(fp, "//-------- Local Decoder convert %d-bit addr to %d-bit data \n", - num_inputs, num_outputs); - fprintf(fp, "module %s(", generate_verilog_decoder_subckt_name(num_inputs, num_outputs)); - fprintf(fp, "\n"); - /* Inputs */ - dump_verilog_generic_port(fp, VERILOG_PORT_INPUT, - "addr", - 0, num_inputs - 1); - fprintf(fp, ",\n"); - /* Outputs */ - fprintf(fp, "output "); - dump_verilog_generic_port(fp, VERILOG_PORT_REG, - "data", - 0, num_outputs - 1); - fprintf(fp, ",\n"); - dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT, - "data_inv", - 0, num_outputs - 1); - fprintf(fp, "\n);\n"); - - /* Print the truth table of this encoder */ - /* Internal logics */ - /* We use a magic number -1 as the addr=1 should be mapped to ...1 - * Otherwise addr will map addr=1 to ..10 - * Note that there should be a range for the shift operators - * We should narrow the encoding to be applied to a given set of data - * This will lead to that any addr which falls out of the op code of data - * will give a all-zero code - * For example: - * data is 5-bit while addr is 3-bit - * data=8'b0_0000 will be encoded to addr=3'b001; - * data=8'b0_0001 will be encoded to addr=3'b010; - * data=8'b0_0010 will be encoded to addr=3'b011; - * data=8'b0_0100 will be encoded to addr=3'b100; - * data=8'b0_1000 will be encoded to addr=3'b101; - * data=8'b1_0000 will be encoded to addr=3'b110; - * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000; - */ - - fprintf(fp, "always@(addr)\n"); - fprintf(fp, "case (addr)\n"); - /* Create a string for addr and data */ - for (int i = 0; i < num_outputs; ++i) { - fprintf(fp, "\t%d'b%s : data = %d'b%s;\n", - num_inputs, my_itobin(i, num_inputs), - num_outputs, my_ito1hot(i, num_outputs)); - } - fprintf(fp, "\tdefault : data = %d'b%s;\n", - num_outputs, my_ito1hot(num_outputs - 1, num_outputs)); - fprintf(fp, "endcase\n"); - - fprintf(fp, "assign data_inv = ~data;\n"); - - - /* Finish */ - fprintf(fp, "endmodule\n"); - - fprintf(fp, "//-------- END Local Decoder convert %d-bit addr to %d-bit data \n\n", - num_inputs, num_outputs); - - return; -} - -/* We should count how many multiplexers with different sizes are needed */ -static -void dump_verilog_submodule_local_encoders(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* submodule_dir, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch, - bool is_explicit_mapping) { - - /* Statisitcs for input sizes and structures of MUXes - * used in FPGA architecture - */ - /* We have linked list whichs stores spice model information of multiplexer*/ - t_llist* muxes_head = NULL; - t_llist* temp = NULL; - FILE* fp = NULL; - char* verilog_name = my_strcat(submodule_dir, local_encoder_verilog_file_name); - int num_input_ports = 0; - t_spice_model_port** input_ports = NULL; - int num_sram_ports = 0; - t_spice_model_port** sram_ports = NULL; - - int num_input_basis = 0; - t_spice_mux_model* cur_spice_mux_model = NULL; - - /* Alloc the muxes*/ - muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); - - /* Print the muxes netlist*/ - fp = fopen(verilog_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, verilog_name); - exit(1); - } - /* Generate the descriptions*/ - dump_verilog_file_header(fp,"MUXes used in FPGA"); - - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a vector for local encoders with different sizes */ - std::vector encoder_sizes; - /* Make sure a clean start */ - encoder_sizes.clear(); - - /* Print mux netlist one by one*/ - temp = muxes_head; - while(temp) { - assert(NULL != temp->dptr); - cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); - /* Bypass the spice models who has a user-defined subckt */ - if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) { - input_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE); - sram_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_ports, TRUE); - assert(0 != num_input_ports); - assert(0 != num_sram_ports); - /* Check the Input port size */ - if (cur_spice_mux_model->size != input_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) size(%d) unmatch with the architecture needs(%d)!\n", - __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, input_ports[0]->size,cur_spice_mux_model->size); - exit(1); - } - /* Check the SRAM port size */ - num_input_basis = determine_num_input_basis_multilevel_mux(cur_spice_mux_model->size, - cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level); - if ((num_input_basis * cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level) != sram_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) SRAM size(%d) unmatch with the num of level(%d)!\n", - __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, sram_ports[0]->size, cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level*num_input_basis); - exit(1); - } - /* Move on to the next*/ - temp = temp->next; - continue; - } - /* Bypass those without local encoders, we only care SPICE models whose type is MUX! */ - if ( (SPICE_MODEL_MUX != cur_spice_mux_model->spice_model->type) - || (FALSE == cur_spice_mux_model->spice_model->design_tech_info.mux_info->local_encoder) ) { - /* Move on to the next*/ - temp = temp->next; - continue; - } - /* Reach here, we need to generate a local encoder Verilog module */ - /* Generate the spice_mux_arch */ - cur_spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); - init_spice_mux_arch(cur_spice_mux_model->spice_model, cur_spice_mux_model->spice_mux_arch, cur_spice_mux_model->size); - /* We will bypass all the TREE-LIKE multiplexers and those with 2-inputs */ - if ( (SPICE_MODEL_STRUCTURE_TREE == cur_spice_mux_model->spice_mux_arch->structure) - || ( 2 == cur_spice_mux_model->spice_mux_arch->num_input) ) { - /* Move on to the next*/ - temp = temp->next; - continue; - } - /* Find the size of local encoders */ - std::vector::iterator it = std::find(encoder_sizes.begin(), encoder_sizes.end(), cur_spice_mux_model->spice_mux_arch->num_input_basis); - /* See if a same-sized local encoder is already in the list */ - if (it == encoder_sizes.end()) { - /* Need to add to the list */ - encoder_sizes.push_back(cur_spice_mux_model->spice_mux_arch->num_input_basis); - } - /* Move on to the next*/ - temp = temp->next; - } - - - /* Print the local encoder subckt */ - for (size_t i = 0; i < encoder_sizes.size(); ++i) { - dump_verilog_mux_local_encoder_module(fp, encoder_sizes[i]); - } - - vpr_printf(TIO_MESSAGE_INFO,"Generated %d local encoders for Multiplexers.\n", - encoder_sizes.size()); - - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); - - /* Close the file*/ - fclose(fp); - - /* remember to free the linked list*/ - free_muxes_llist(muxes_head); - /* Free strings */ - free(verilog_name); - - return; -} - static void dump_verilog_wire_module(FILE* fp, char* wire_subckt_name, @@ -3559,11 +3335,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, verilog_dir, submodule_dir); vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); - /* - dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, - switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); - */ - print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 2. LUTes */ From 0711aa1bd6e1289708b891f2e78ed8b453920ee8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Sep 2019 16:56:14 -0600 Subject: [PATCH 180/482] minor bug fixing --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index d24773c49..c237c23f9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -190,10 +190,17 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); /* Add the decoder to the decoder library */ for (auto branch_mux_graph : branch_mux_graphs) { + /* The decoder size depends on the number of memories of a branch MUX. + * Note that only when there are >=2 memories, a decoder is needed + */ + size_t decoder_data_size = branch_mux_graph.num_memory_bits(); + if (2 > decoder_data_size) { + continue; + } /* Try to find if the decoder already exists in the library, * If there is no such decoder, add it to the library */ - add_mux_local_decoder_to_library(decoder_lib, branch_mux_graph.num_inputs()); + add_mux_local_decoder_to_library(decoder_lib, decoder_data_size); } } From 6a5b50facf10d040e4b94be43745c9192206c1fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Sep 2019 20:45:44 -0600 Subject: [PATCH 181/482] refactored RRAM MUX verilog generation --- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 416 +++++++++++++++++- 1 file changed, 407 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 9426c258c..df3d75a67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -608,6 +608,14 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, /* Make sure we have a valid file handler*/ check_file_handler(fp); + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the BL and WL ports from the mux */ + std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); + std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); + /* Generate the Verilog netlist according to the mux_graph */ /* Find out the number of inputs */ size_t num_inputs = mux_graph.num_inputs(); @@ -621,6 +629,11 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, VTR_ASSERT(1 == num_outputs); /* MUX graph must have only 1 level*/ VTR_ASSERT(1 == mux_graph.num_levels()); + /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ + VTR_ASSERT(1 == mux_input_ports.size()); + VTR_ASSERT(1 == mux_output_ports.size()); + VTR_ASSERT(1 == mux_blb_ports.size()); + VTR_ASSERT(1 == mux_wl_ports.size()); /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId module_id = module_manager.add_module(module_name); @@ -634,19 +647,23 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } + /* Add each input port */ - BasicPort input_port("in", num_inputs); + BasicPort input_port(circuit_lib.port_lib_name(mux_input_ports[0]), num_inputs); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ - BasicPort output_port("out", num_outputs); + BasicPort output_port(circuit_lib.port_lib_name(mux_output_ports[0]), num_outputs); module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add RRAM programming ports, * RRAM MUXes require one more pair of BLB and WL * to configure the memories. See schematic for details */ - BasicPort blb_port("blb", num_mems + 1); + BasicPort blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), num_mems + 1); module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort wl_port("wl", num_mems + 1); + + BasicPort wl_port(circuit_lib.port_lib_name(mux_wl_ports[0]), num_mems + 1); module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); /* dump module definition + ports */ @@ -929,7 +946,6 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); fp << std::endl; - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----")); /* Iterate over all the internal nodes and output nodes in the mux graph */ for (const auto& node : mux_graph.non_input_nodes()) { print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----")); @@ -1414,6 +1430,391 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, print_verilog_module_end(fp, module_name); } +/******************************************************************** + * Generate the 4T1R-based internal logic + * (multiplexing structure) for a multiplexer in Verilog codes + * This function will : + * 1. build a multiplexing structure by instanciating the branch circuits + * generated before + * 2. add intermediate buffers between multiplexing stages if specified. + *******************************************************************/ +static +void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const ModuleId& module_id, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Find the actual mux size */ + size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); + + /* Get the BL and WL ports from the mux */ + std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); + std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); + /* MUX graph must have only 1 BLB and 1 WL port */ + VTR_ASSERT(1 == mux_blb_ports.size()); + VTR_ASSERT(1 == mux_wl_ports.size()); + + /* Build the location map of intermediate buffers */ + std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); + + print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a RRAM-based MUX module -----")); + + print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a RRAM-based MUX module -----")); + /* Print local wires which are the nodes in the mux graph */ + for (size_t level = 0; level < mux_graph.num_levels(); ++level) { + /* Print the internal wires located at this level */ + BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; + /* Identify if an intermediate buffer is needed */ + if (false == inter_buffer_location_map[level]) { + continue; + } + BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; + } + print_verilog_comment(fp, std::string("---- END Internal wires of a RRAM-based MUX module -----")); + fp << std::endl; + + /* Iterate over all the internal nodes and output nodes in the mux graph */ + for (const auto& node : mux_graph.non_input_nodes()) { + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch RRAM-based MUX module -----")); + /* Get the size of branch circuit + * Instanciate an branch circuit by the size (fan-in) of the node + */ + size_t branch_size = mux_graph.node_in_edges(node).size(); + + /* Get the node level and index in the current level */ + size_t output_node_level = mux_graph.node_level(node); + size_t output_node_index_at_level = mux_graph.node_index_at_level(node); + + /* Get the nodes which drive the root_node */ + std::vector input_nodes; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the nodes drive the edge */ + for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { + input_nodes.push_back(src_node); + } + } + /* Number of inputs should match the branch_input_size!!! */ + VTR_ASSERT(input_nodes.size() == branch_size); + + /* Get the mems in the branch circuits */ + std::vector mems; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the mem control the edge */ + MuxMemId mem = mux_graph.find_edge_mem(edge); + /* Add the mem if it is not in the list */ + if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { + mems.push_back(mem); + } + } + + /* Instanciate the branch module which is a tgate-based module + */ + std::string branch_module_name= generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); + /* Get the moduleId for the submodule */ + ModuleId branch_module_id = module_manager.find_module(branch_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != branch_module_id); + + /* Create a port-to-port map */ + std::map port2port_name_map; + /* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */ + + /* All the input node names organized in bus */ + std::vector branch_node_input_ports; + for (const auto& input_node : input_nodes) { + /* Generate the port info of each input node */ + size_t input_node_level = mux_graph.node_level(input_node); + size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); + BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); + branch_node_input_ports.push_back(branch_node_input_port); + } + + /* Create the port info for the input */ + /* TODO: the naming could be more flexible? */ + BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_in")); + /* If we have more than 1 port in the combined instance ports , + * output a local wire */ + if (1 < combine_verilog_ports(branch_node_input_ports).size()) { + /* Print a local wire for the merged ports */ + fp << "\t" << generate_verilog_local_wire(instance_input_port, branch_node_input_ports) << std::endl; + } else { + /* Safety check */ + VTR_ASSERT(1 == combine_verilog_ports(branch_node_input_ports).size()); + } + + /* Link nodes to input ports for the branch module */ + ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in"); + VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); + /* Get the port from module */ + BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id); + port2port_name_map[module_input_port.get_name()] = instance_input_port; + + /* Link nodes to output ports for the branch module */ + BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out"); + VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); + /* Get the port from module */ + BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id); + port2port_name_map[module_output_port.get_name()] = instance_output_port; + + /* All the mem node names organized in bus + * RRAM-based MUX uses BLB and WL to control memories + */ + std::vector branch_node_blb_ports; + for (const auto& mem : mems) { + /* Generate the port info of each mem node: + */ + BasicPort branch_node_blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), size_t(mem), size_t(mem)); + branch_node_blb_ports.push_back(branch_node_blb_port); + } + /* Every stage, we have an additonal BLB and WL in controlling purpose + * The additional BLB is arranged at the tail of BLB port + * For example: + * The total port width is BLB[0 ... + - 1] + * The regular BLB used by branches are BLB[0 .. - 1] + * The additional BLB used by branches are BLB[ .. + - 1] + * + * output_node_level is always larger than the mem_level by 1 + */ + branch_node_blb_ports.push_back(BasicPort(circuit_lib.port_lib_name(mux_blb_ports[0]), + mux_graph.num_memory_bits() + output_node_level - 1, + mux_graph.num_memory_bits() + output_node_level - 1) + ); + + /* Create the port info for the input */ + /* TODO: the naming could be more flexible? */ + BasicPort instance_blb_port = generate_verilog_bus_port(branch_node_blb_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_blb")); + /* If we have more than 1 port in the combined instance ports , + * output a local wire */ + if (1 < combine_verilog_ports(branch_node_blb_ports).size()) { + /* Print a local wire for the merged ports */ + fp << "\t" << generate_verilog_local_wire(instance_blb_port, branch_node_blb_ports) << std::endl; + } else { + /* Safety check */ + VTR_ASSERT(1 == combine_verilog_ports(branch_node_blb_ports).size()); + } + + /* Link nodes to BLB ports for the branch module */ + ModulePortId module_blb_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_lib_name(mux_blb_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_blb_port_id); + /* Get the port from module */ + BasicPort module_blb_port = module_manager.module_port(branch_module_id, module_blb_port_id); + port2port_name_map[module_blb_port.get_name()] = instance_blb_port; + + std::vector branch_node_wl_ports; + for (const auto& mem : mems) { + /* Generate the port info of each mem node: + */ + BasicPort branch_node_blb_port(circuit_lib.port_lib_name(mux_wl_ports[0]), size_t(mem), size_t(mem)); + branch_node_wl_ports.push_back(branch_node_blb_port); + } + /* Every stage, we have an additonal BLB and WL in controlling purpose + * The additional BLB is arranged at the tail of BLB port + * For example: + * The total port width is WL[0 ... + - 1] + * The regular BLB used by branches are WL[0 .. - 1] + * The additional BLB used by branches are WL[ .. + - 1] + * + * output_node_level is always larger than the mem_level by 1 + */ + branch_node_wl_ports.push_back(BasicPort(circuit_lib.port_lib_name(mux_wl_ports[0]), + mux_graph.num_memory_bits() + output_node_level - 1, + mux_graph.num_memory_bits() + output_node_level - 1) + ); + + /* Create the port info for the WL */ + /* TODO: the naming could be more flexible? */ + BasicPort instance_wl_port = generate_verilog_bus_port(branch_node_wl_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_wl")); + /* If we have more than 1 port in the combined instance ports , + * output a local wire */ + if (1 < combine_verilog_ports(branch_node_wl_ports).size()) { + /* Print a local wire for the merged ports */ + fp << "\t" << generate_verilog_local_wire(instance_wl_port, branch_node_wl_ports) << std::endl; + } else { + /* Safety check */ + VTR_ASSERT(1 == combine_verilog_ports(branch_node_wl_ports).size()); + } + + /* Link nodes to BLB ports for the branch module */ + ModulePortId module_wl_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_lib_name(mux_wl_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_wl_port_id); + /* Get the port from module */ + BasicPort module_wl_port = module_manager.module_port(branch_module_id, module_wl_port_id); + port2port_name_map[module_wl_port.get_name()] = instance_wl_port; + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, branch_module_id); + + print_verilog_comment(fp, std::string("---- END Instanciation of a branch RRAM-based MUX module -----")); + fp << std::endl; + + if (false == inter_buffer_location_map[output_node_level]) { + continue; /* No need for intermediate buffers */ + } + + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an intermediate buffer modules -----")); + + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + + BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); + + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); + + print_verilog_comment(fp, std::string("---- END Instanciation of an intermediate buffer module -----")); + fp << std::endl; + } + + print_verilog_comment(fp, std::string("---- END Internal Logic of a RRAM-based MUX module -----")); + fp << std::endl; +} + +/********************************************************************* + * Generate Verilog codes modeling a RRAM-based multiplexer with the given size + * The Verilog module will consist of three parts: + * 1. instances of the branch circuits of multiplexers which are generated before + * This builds up the 4T1R-based multiplexing structure + * + * BLB WL + * | | ... + * v v + * +--------+ + * in[0]-->| | BLB WL + * ...| Branch |-----+ | | + * in -->| 0 | | v v + * [N-1] +--------+ | +--------+ + * ... -->| | + * BLBs WLs ...| Branch | + * | | ... -->| X | + * v v +--------+ + * +--------+ | + * -->| | | + * ...| Branch |----+ + * -->| i | + * +--------+ + * + * 2. Input buffers/inverters + * 3. Output buffers/inverters + *********************************************************************/ +static +void generate_verilog_rram_mux_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& circuit_model, + const std::string& module_name, + const MuxGraph& mux_graph) { + /* Error out for the conditions where we are not yet supported! */ + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + /* RRAM LUT is not supported now... */ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])RRAM-based LUT is not supported (Circuit model: %s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + + /* Get the global ports required by MUX (and any submodules) */ + std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the BL and WL ports from the mux */ + std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); + std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); + + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of data-path inputs */ + size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ + VTR_ASSERT(1 == mux_input_ports.size()); + VTR_ASSERT(1 == mux_blb_ports.size()); + VTR_ASSERT(1 == mux_wl_ports.size()); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ + for (const auto& port : mux_global_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port */ + size_t input_port_cnt = 0; + for (const auto& port : mux_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Update counter */ + input_port_cnt++; + } + /* Double check: We should have only 1 input port generated here! */ + VTR_ASSERT(1 == input_port_cnt); + + for (const auto& port : mux_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + output_port.set_width(circuit_lib.port_size(port)); + } + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* BLB port */ + for (const auto& port : mux_blb_ports) { + /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level + * So, the actual port width of BLB should be added by the number of levels of the MUX graph + */ + BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* WL port */ + for (const auto& port : mux_wl_ports) { + /* IMPORTANT: RRAM-based MUX has an additional WL pin per level + * So, the actual port width of WL should be added by the number of levels of the MUX graph + */ + BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + + /* TODO: Print the internal logic in Verilog codes */ + generate_verilog_rram_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + + /* Print the input and output buffers in Verilog codes */ + /* TODO, we should rename the follow functions to a generic name? Since they are applicable to both MUXes */ + generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + + /*********************************************** * Generate Verilog codes modeling a multiplexer * with the given graph-level description @@ -1436,10 +1837,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager, break; case SPICE_MODEL_DESIGN_RRAM: /* TODO: RRAM-based Multiplexer Verilog module generation */ - /* - generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph, - circuit_lib.dump_structural_verilog(circuit_model)); - */ + generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); break; default: vpr_printf(TIO_MESSAGE_ERROR, From 03993192120e7854ecd9344fb3aa8c68f6b8bd0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 11 Sep 2019 17:04:43 -0600 Subject: [PATCH 182/482] refactored LUT Verilog generation --- .../libarchfpga/SRC/check_circuit_library.cpp | 18 + vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 42 +- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 4 + .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 384 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/verilog/verilog_lut.h | 20 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 + 6 files changed, 469 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 0b08d8f58..d32578d2d 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -376,6 +376,24 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { } } + /* Check the tri-state map of ports, the length should match the port size! */ + for (const auto& port : circuit_lib.ports()) { + if (circuit_lib.port_tri_state_map(port).empty()) { + continue; /* No tri-state map is found, go to the next */ + } + if (circuit_lib.port_tri_state_map(port).length() == circuit_lib.port_size(port)) { + continue; /* Sizes match, go to the next */ + } + /* We have a problem here, sizes do not match, leave a message and raise the error flag */ + vpr_printf(TIO_MESSAGE_ERROR, + "Tri-state map (=%s) of circuit port (type=%s) of model (name=%s) does not match the port size (=%lu)!\n", + circuit_lib.port_tri_state_map(port).c_str(), + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))], + circuit_lib.model_name(port).c_str(), + circuit_lib.port_size(port)); + num_err++; + } + return num_err; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index d22574e09..7d0ea6ddc 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -192,6 +192,32 @@ bool CircuitLibrary::is_lut_fracturable(const CircuitModelId& model_id) const { return lut_is_fracturable_[model_id]; } +/* Return the circuit model of input buffers + * that are inserted between multiplexing structure and LUT inputs + */ +CircuitModelId CircuitLibrary::lut_input_inverter_model(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + /* We MUST have an input inverter */ + VTR_ASSERT(true == buffer_existence_[model_id][LUT_INPUT_INVERTER]); + return buffer_model_ids_[model_id][LUT_INPUT_INVERTER]; +} + +/* Return the circuit model of input buffers + * that are inserted between multiplexing structure and LUT inputs + */ +CircuitModelId CircuitLibrary::lut_input_buffer_model(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + /* We MUST have an input buffer */ + VTR_ASSERT(true == buffer_existence_[model_id][LUT_INPUT_BUFFER]); + return buffer_model_ids_[model_id][LUT_INPUT_BUFFER]; +} + /* Return the circuit model of intermediate buffers * that are inserted inside LUT multiplexing structures */ @@ -200,7 +226,7 @@ CircuitModelId CircuitLibrary::lut_intermediate_buffer_model(const CircuitModelI VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is BUF */ VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* if we have an intermediate buffer, we return something, otherwise return an empty map */ + /* if we have an intermediate buffer, we return something, otherwise return an invalid id */ if (true == is_lut_intermediate_buffered(model_id)) { return buffer_model_ids_[model_id][LUT_INTER_BUFFER]; } else { @@ -749,6 +775,20 @@ std::vector CircuitLibrary::port_lut_output_masks(const CircuitPortId& c return port_lut_output_masks_[circuit_port_id]; } +/* Return tri-state map of a port */ +std::string CircuitLibrary::port_tri_state_map(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_tri_state_maps_[circuit_port_id]; +} + +/* Return circuit model id which is used to tri-state a port */ +CircuitModelId CircuitLibrary::port_tri_state_model(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_tri_state_model_ids_[circuit_port_id]; +} + /* Return the id of parent circuit model for a circuit port */ CircuitModelId CircuitLibrary::port_parent_model(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index d74c61a45..acdf2efe6 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -226,6 +226,8 @@ class CircuitLibrary { /* LUT-related information */ bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; bool is_lut_fracturable(const CircuitModelId& model_id) const; + CircuitModelId lut_input_buffer_model(const CircuitModelId& model_id) const; + CircuitModelId lut_input_inverter_model(const CircuitModelId& model_id) const; CircuitModelId lut_intermediate_buffer_model(const CircuitModelId& model_id) const; std::string lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const; /* Pass-gate-logic information */ @@ -277,6 +279,8 @@ class CircuitLibrary { bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_masks(const CircuitPortId& circuit_port_id) const; + std::string port_tri_state_map(const CircuitPortId& circuit_port_id) const; + CircuitModelId port_tri_state_model(const CircuitPortId& circuit_port_id) const; CircuitModelId port_parent_model(const CircuitPortId& circuit_port_id) const; std::string model_name(const CircuitPortId& port_id) const; public: /* Public Accessors: Timing graph */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp new file mode 100644 index 000000000..25a691935 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -0,0 +1,384 @@ +/******************************************************************** + * This file includes functions to generate Verilog submodules for LUTs + ********************************************************************/ +#include +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "mux_graph.h" +#include "module_manager.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "mux_utils.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_submodule_utils.h" +#include "verilog_lut.h" + +/******************************************************************** + * Print a Verilog module for a LUT circuit model + * This function supports both single-output and fracturable LUTs + * The Verilog module will be organized in structural Verilog codes. + * It will instanciate: + * 1. Multiplexer used inside LUT + * 2. Input buffers + * 3. Input inverters + * 4. Output buffers. + * 6. AND/OR gates to tri-state LUT inputs + ********************************************************************/ +static +void print_verilog_submodule_lut(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& circuit_model) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* Get the global ports required by MUX (and any submodules) */ + std::vector lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the input ports from the mux */ + std::vector lut_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector lut_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */ + std::vector lut_regular_sram_ports; + std::vector lut_mode_select_sram_ports; + + { /* Create a code block to keep some variables in local */ + /* Get the sram ports from the mux */ + std::vector lut_sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); + for (const auto& port : lut_sram_ports) { + /* Bypass mode_select ports */ + if (true == circuit_lib.port_is_mode_select(port)) { + lut_mode_select_sram_ports.push_back(port); + continue; + } + VTR_ASSERT_SAFE (false == circuit_lib.port_is_mode_select(port)); + lut_regular_sram_ports.push_back(port); + } + } + + /* Make sure that the number of ports and sizes of ports are what we want */ + if (false == circuit_lib.is_lut_fracturable(circuit_model)) { + /* Single-output LUTs: + * We should have only 1 input port, 1 output port and 1 SRAM port + */ + VTR_ASSERT (1 == lut_input_ports.size()); + VTR_ASSERT (1 == lut_output_ports.size()); + VTR_ASSERT (1 == lut_regular_sram_ports.size()); + VTR_ASSERT (0 == lut_mode_select_sram_ports.size()); + } else { + VTR_ASSERT (true == circuit_lib.is_lut_fracturable(circuit_model)); + /* Fracturable LUT: + * We should have only 1 input port, a few output ports (fracturable outputs) + * and two SRAM ports + */ + VTR_ASSERT (1 == lut_input_ports.size()); + VTR_ASSERT (1 <= lut_output_ports.size()); + VTR_ASSERT (1 == lut_regular_sram_ports.size()); + VTR_ASSERT (1 == lut_mode_select_sram_ports.size()); + } + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(circuit_lib.model_name(circuit_model)); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ + for (const auto& port : lut_global_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port */ + for (const auto& port : lut_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Add each output port */ + for (const auto& port : lut_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + /* Add each regular (not mode select) SRAM port */ + for (const auto& port : lut_regular_sram_ports) { + BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); + module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* Add each mode-select SRAM port */ + for (const auto& port : lut_mode_select_sram_ports) { + BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); + module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + + /* Print local wires for mode selector */ + /* Local wires for the output of mode selector */ + BasicPort mode_select_output_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_mode"), circuit_lib.port_size(lut_input_ports[0])); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, mode_select_output_port) << ";" << std::endl; + /* Local wires for the output of input inverters */ + BasicPort inverted_input_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_b"), circuit_lib.port_size(lut_input_ports[0])); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, inverted_input_port) << ";" << std::endl; + /* Local wires for the output of input buffers */ + BasicPort buffered_input_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_buf"), circuit_lib.port_size(lut_input_ports[0])); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, buffered_input_port) << ";" << std::endl; + + /* Instanciate mode selecting circuit: AND/OR gate + * By following the tri-state map of LUT input port + * The wiring of input ports will be organized as follows + * + * LUT input + * | + * v + * +----------+ + * | mode | + * | selector | + * +----------+ + * | mode_select_output_port + * +-----------------+------------+ + * | | + * +----------+ +---------+ + * | Inverter | | Buffer | + * +----------+ +---------+ + * | inverter_input_port | buffered_input_port + * v v + * +--------------------------------------+ + * | LUT Multiplexing Structure | + * +--------------------------------------+ + */ + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of model-select gates -----")); + /* Get the tri-state port map for the input ports*/ + std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]); + size_t mode_select_port_lsb = 0; + for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { + BasicPort cur_mode_select_output_port(mode_select_output_port.get_name(), pin, pin); + BasicPort cur_input_port(circuit_lib.port_lib_name(lut_input_ports[0]), pin, pin); + /* For an empty tri-state map or a '-' sign in tri-state map, we can short-wire mode select_output_ports */ + if (tri_state_map.empty() || ('-' == tri_state_map[pin]) ) { + print_verilog_wire_connection(fp, cur_mode_select_output_port, cur_input_port, false); + continue; /* Finish here */ + } + /* Reach here, it means that we need a circuit for mode selection */ + BasicPort cur_lut_mode_select_sram_port(circuit_lib.port_lib_name(lut_mode_select_sram_ports[0]), mode_select_port_lsb, mode_select_port_lsb); + enum e_spice_model_gate_type required_gate_type; + if ('0' == tri_state_map[pin]) { + /* We need a 2-input AND gate, in order to tri-state the input + * Detailed circuit is as follow: + * +---------+ + * SRAM --->| 2-input |----> mode_select_output_port + * LUT input--->| AND | + * +---------+ + * When SRAM is set to logic 0, the LUT input is tri-stated + * When SRAM is set to logic 1, the LUT input is effective to the downstream circuits + */ + required_gate_type = SPICE_MODEL_GATE_AND; + } else { + VTR_ASSERT ('1' == tri_state_map[pin]); + /* We need a 2-input OR gate, in order to tri-state the input + * Detailed circuit is as follow: + * +---------+ + * SRAM --->| 2-input |----> mode_select_output_port + * LUT input--->| OR | + * +---------+ + * When SRAM is set to logic 1, the LUT input is tri-stated + * When SRAM is set to logic 0, the LUT input is effective to the downstream circuits + */ + required_gate_type = SPICE_MODEL_GATE_OR; + } + /* Get the circuit model of the gate */ + CircuitModelId gate_model = circuit_lib.port_tri_state_model(lut_input_ports[0]); + /* Check this is the gate we want ! */ + VTR_ASSERT (required_gate_type == circuit_lib.gate_type(gate_model)); + + /* Prepare for the gate instanciation */ + /* Get the input ports from the gate */ + std::vector gate_input_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the gate */ + std::vector gate_output_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Check the port sizes and width: + * we should have only 2 input ports, each of which has a size of 1 + * we should have only 1 output port, each of which has a size of 1 + */ + VTR_ASSERT (2 == gate_input_ports.size()); + for (const auto& port : gate_input_ports) { + VTR_ASSERT (1 == circuit_lib.port_size(port)); + } + VTR_ASSERT (1 == gate_output_ports.size()); + for (const auto& port : gate_output_ports) { + VTR_ASSERT (1 == circuit_lib.port_size(port)); + } + /* Find the module id of gate_model in the module manager */ + ModuleId gate_module_id = module_manager.find_module(circuit_lib.model_name(gate_model)); + /* We must have a valid id */ + VTR_ASSERT (ModuleId::INVALID() != gate_module_id); + /* Create a port-to-port map: + * Input[0] of the gate is wired to a SRAM mode-select port + * Input[1] of the gate is wired to the input port of LUT + * Output[0] of the gate is wired to the mode_select_output_port + */ + std::map port2port_name_map; + port2port_name_map[circuit_lib.port_lib_name(gate_input_ports[0])] = cur_lut_mode_select_sram_port; + port2port_name_map[circuit_lib.port_lib_name(gate_input_ports[1])] = cur_input_port; + port2port_name_map[circuit_lib.port_lib_name(gate_output_ports[0])] = cur_mode_select_output_port; + + /* Instanciate the gate */ + print_verilog_module_instance(fp, module_manager, module_id, gate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, gate_module_id); + /* update the lsb of mode select port size */ + mode_select_port_lsb++; + } + print_verilog_comment(fp, std::string("---- END Instanciation of model-select gates -----")); + /* Sanitity check */ + if ( true == circuit_lib.is_lut_fracturable(circuit_model) ) { + if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Circuit model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n", + __FILE__, __LINE__, + circuit_lib.model_name(circuit_model).c_str(), + tri_state_map.c_str(), + circuit_lib.port_size(lut_mode_select_sram_ports[0])); + exit(1); + } + } + + /* Add a blank-line splitter */ + fp << std::endl; + + /* Add inverters to mode_select output ports */ + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input inverters modules -----")); + /* Find the circuit model of the input inverter */ + CircuitModelId input_inverter_model = circuit_lib.lut_input_inverter_model(circuit_model); + VTR_ASSERT( CircuitModelId::INVALID() != input_inverter_model ); + /* Now we need to add inverters by instanciating the modules */ + for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { + /* Input of inverter is the output of mode select circuits */ + BasicPort inverter_instance_input_port(mode_select_output_port.get_name(), pin, pin); + /* Output of inverter is the inverted input port */ + BasicPort inverter_instance_output_port(inverted_input_port.get_name(), pin, pin); + + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, input_inverter_model, inverter_instance_input_port, inverter_instance_output_port); + } + print_verilog_comment(fp, std::string("---- END Instanciation of an input inverters modules -----")); + + /* Add buffers to mode_select output ports */ + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input buffer modules -----")); + /* Find the circuit model of the input inverter */ + CircuitModelId input_buffer_model = circuit_lib.lut_input_buffer_model(circuit_model); + VTR_ASSERT( CircuitModelId::INVALID() != input_buffer_model ); + /* Now we need to add inverters by instanciating the modules */ + for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { + /* Input of inverter is the output of mode select circuits */ + BasicPort buffer_instance_input_port(mode_select_output_port.get_name(), pin, pin); + /* Output of inverter is the inverted input port */ + BasicPort buffer_instance_output_port(buffered_input_port.get_name(), pin, pin); + + print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, input_buffer_model, buffer_instance_input_port, buffer_instance_output_port); + } + print_verilog_comment(fp, std::string("---- END Instanciation of an input buffer modules -----")); + + /* Instanciate the multiplexing structure for the LUT */ + print_verilog_comment(fp, std::string("---- BEGIN Instanciation of LUT multiplexer module -----")); + /* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */ + std::string lut_mux_module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, size_t(-1), std::string("")); + /* Find the module id of LUT MUX in the module manager */ + ModuleId lut_mux_module_id = module_manager.find_module(lut_mux_module_name); + /* We must have a valid id */ + VTR_ASSERT (ModuleId::INVALID() != lut_mux_module_id); + /* Create a port-to-port map: + * Input of the LUT MUX is wired to a regular SRAM port of LUT + * Outputs of the LUT MUX is wired to the output ports of LUT by name + * SRAM of the LUT MUX is wired to the buffered input port of LUT + * SRAM_inv of the LUT MUX is wired to the inverted input port of LUT + */ + std::map port2port_name_map; + port2port_name_map[circuit_lib.port_lib_name(lut_input_ports[0])] = BasicPort(circuit_lib.port_lib_name(lut_regular_sram_ports[0]), circuit_lib.port_size(lut_regular_sram_ports[0])); + /* Skip the output ports, if we do not need a new name for the port of instance */ + port2port_name_map[circuit_lib.port_lib_name(lut_regular_sram_ports[0])] = buffered_input_port; + /* TODO: be more flexible in naming !!! */ + port2port_name_map[std::string(circuit_lib.port_lib_name(lut_regular_sram_ports[0]) + "_inv")] = inverted_input_port; + + /* Instanciate the gate */ + print_verilog_module_instance(fp, module_manager, module_id, lut_mux_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, lut_mux_module_id); + + /* Print timing info */ + print_verilog_submodule_timing(fp, circuit_lib, circuit_model); + + /* Print signal initialization */ + print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); +} + +/******************************************************************** + * Print Verilog modules for the Look-Up Tables (LUTs) + * in the circuit library + ********************************************************************/ +void print_verilog_submodule_luts(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::string& verilog_dir, + const std::string& submodule_dir) { + /* TODO: remove .bak when this part is completed and tested */ + std::string verilog_fname = submodule_dir + luts_verilog_file_name + ".bak"; + + std::fstream fp; + + /* Create the file stream */ + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + /* Check if the file stream if valid or not */ + check_file_handler(fp); + + /* Create file */ + vpr_printf(TIO_MESSAGE_INFO, + "Generating Verilog netlist for LUTs (%s)...\n", + __FILE__, __LINE__, verilog_fname.c_str()); + + print_verilog_file_header(fp, "Look-Up Tables"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Search for each LUT circuit model */ + for (const auto& circuit_model : circuit_lib.models()) { + /* Bypass user-defined and non-LUT modules */ + if ( (!circuit_lib.model_verilog_netlist(circuit_model).empty()) + || (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) ) { + continue; + } + print_verilog_submodule_lut(module_manager, circuit_lib, fp, circuit_model); + } + + /* Close the file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* Add it when the Verilog generation is refactored + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h new file mode 100644 index 000000000..d6a8dba35 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h @@ -0,0 +1,20 @@ +/*********************************************** + * Header file for verilog_lut.cpp + **********************************************/ + +#ifndef VERILOG_LUT_H +#define VERILOG_LUT_H + +/* Include other header files which are dependency on the function declared below */ +#include +#include + +#include "circuit_library.h" +#include "module_manager.h" + +void print_verilog_submodule_luts(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::string& verilog_dir, + const std::string& submodule_dir); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 0a2319edc..1d8acb2ef 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -43,6 +43,7 @@ #include "verilog_mux.h" #include "verilog_essential_gates.h" #include "verilog_decoders.h" +#include "verilog_lut.h" /***** Subroutines *****/ @@ -3344,6 +3345,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, fpga_verilog_opts.include_timing, fpga_verilog_opts.include_signal_init, fpga_verilog_opts.dump_explicit_verilog); + print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 3. Hardwires */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); From 2bed51bf298be04cb066f91d705ed84c3b2ac05f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 11 Sep 2019 17:41:45 -0600 Subject: [PATCH 183/482] minor bug fix for echo --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 25a691935..519e59c2a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -355,7 +355,7 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, /* Create file */ vpr_printf(TIO_MESSAGE_INFO, "Generating Verilog netlist for LUTs (%s)...\n", - __FILE__, __LINE__, verilog_fname.c_str()); + verilog_fname.c_str()); print_verilog_file_header(fp, "Look-Up Tables"); From 79fa858f36a6a3b5df8d5c84b8d3671be90658b4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 11 Sep 2019 19:39:59 -0600 Subject: [PATCH 184/482] remove unused ports for Verilog modules --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 34 +++++++++++++++++-- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 8 ++++- .../verilog/verilog_essential_gates.cpp | 6 ++-- .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 8 ++--- 5 files changed, 47 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 7d0ea6ddc..5f82e12ae 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -529,7 +529,8 @@ std::vector CircuitLibrary::model_global_ports(const CircuitModel /* Recursively find all the global ports in the circuit model / sub circuit_model */ std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, - const bool& recursive) const { + const bool& recursive, + const std::vector& ignore_model_types) const { /* validate the model_id */ VTR_ASSERT(valid_model_id(model_id)); @@ -556,7 +557,21 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ /* If go recursively, we search all the buffer/pass-gate circuit model ids */ /* Go search every sub circuit model included the current circuit model */ for (const auto& sub_model : sub_models_[model_id]) { - std::vector sub_global_ports = model_global_ports_by_type(sub_model, type, recursive); + /* Bypass this sub model if user specified an ignore list */ + bool ignore = false; + for (const auto& ignore_model_type : ignore_model_types) { + if (ignore_model_type != model_type(sub_model)) { + continue; + } + ignore = true; + break; + } + if (true == ignore) { + continue; + } + + /* Now we can add global ports */ + std::vector sub_global_ports = model_global_ports_by_type(sub_model, type, recursive, ignore_model_types); for (const auto& sub_global_port : sub_global_ports) { /* Add to global_ports, if it is not already found in the list */ bool add_to_list = true; @@ -577,6 +592,21 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ return global_ports; } +/* Recursively find all the global ports in the circuit model / sub circuit_model + * but ignore all the SRAM and SCFF, which are configuration memories + */ +std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& type, + const bool& recursive, + const bool& ignore_config_memories) const { + std::vector ignore_list; + if (true == ignore_config_memories) { + ignore_list.push_back(SPICE_MODEL_SRAM); + ignore_list.push_back(SPICE_MODEL_SCFF); + } + return model_global_ports_by_type(model_id, type, recursive, ignore_list); +} + /* Find the ports of a circuit model by a given type, return a list of qualified ports */ std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type) const { diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index acdf2efe6..30ae83aab 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -256,7 +256,13 @@ class CircuitLibrary { std::vector model_global_ports(const CircuitModelId& model_id, const bool& recursive) const; std::vector model_global_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, - const bool& recursive) const; + const bool& recursive, + const std::vector& ignore_model_types) const; + std::vector model_global_ports_by_type(const CircuitModelId& model_id, + const enum e_spice_model_port_type& type, + const bool& recursive, + const bool& ignore_config_memories) const; + std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector model_input_ports(const CircuitModelId& model_id) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index a94828c5e..a38c50230 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -148,7 +148,7 @@ void print_verilog_invbuf_module(ModuleManager& module_manager, /* Find the input port, output port and global inputs*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); /* Make sure: * There is only 1 input port and 1 output port, @@ -233,7 +233,7 @@ void print_verilog_passgate_module(ModuleManager& module_manager, /* Find the input port, output port*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); switch (circuit_lib.pass_gate_logic_type(circuit_model)) { case SPICE_MODEL_PASS_GATE_TRANSMISSION: @@ -444,7 +444,7 @@ void print_verilog_gate_module(ModuleManager& module_manager, /* Find the input port, output port*/ std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); /* Make sure: * There is only 1 output port, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 519e59c2a..5adc9a558 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -45,7 +45,7 @@ void print_verilog_submodule_lut(ModuleManager& module_manager, check_file_handler(fp); /* Get the global ports required by MUX (and any submodules) */ - std::vector lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); /* Get the input ports from the mux */ std::vector lut_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Get the output ports from the mux */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index df3d75a67..4ec37f3cd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -200,7 +200,7 @@ void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager, return; } - std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); + std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true, true); /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -641,7 +641,7 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, /* Add module ports */ /* Add each global programming enable/disable ports */ - std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); for (const auto& port : prog_enable_ports) { /* Configure each global port */ BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); @@ -1310,7 +1310,7 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, const std::string& module_name, const MuxGraph& mux_graph) { /* Get the global ports required by MUX (and any submodules) */ - std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); /* Get the input ports from the mux */ std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Get the output ports from the mux */ @@ -1726,7 +1726,7 @@ void generate_verilog_rram_mux_module(ModuleManager& module_manager, } /* Get the global ports required by MUX (and any submodules) */ - std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); /* Get the input ports from the mux */ std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Get the output ports from the mux */ From 2b829238b5412cbddffa37d99004d8890d14b04d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 12 Sep 2019 20:49:02 -0600 Subject: [PATCH 185/482] refactored wire Verilog generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 34 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 + .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 7 + .../vpr/SRC/fpga_x2p/base/module_manager.h | 3 + .../fpga_x2p/base/module_manager_utils.cpp | 27 +- .../SRC/fpga_x2p/base/module_manager_utils.h | 9 +- .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.h | 2 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 7 + .../vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp | 236 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/verilog/verilog_wire.h | 23 ++ 11 files changed, 350 insertions(+), 5 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 0389785f7..32ae2f723 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -94,3 +94,37 @@ std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, return subckt_name; } + +/************************************************ + * Generate the module name of a routing track wire + ***********************************************/ +std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, + const size_t& segment_id) { + std::string segment_wire_subckt_name = wire_model_name + "_seg" + std::to_string(segment_id); + + return segment_wire_subckt_name; +} + +/********************************************************************* + * Generate the port name for the mid-output of a routing track wire + * Mid-output is the output that is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + + ********************************************************************/ +std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name) { + /* TODO: maybe have a postfix? */ + return std::string("mid_" + regular_output_name); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index f429a9c32..edd125ea7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -28,4 +28,9 @@ std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circui std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, const size_t& data_size); +std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, + const size_t& segment_id); + +std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 394dd85fb..8743b2ebb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -162,6 +162,13 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, return port; } +/* Set a name for a module */ +void ModuleManager::set_module_name(const ModuleId& module, const std::string& name) { + /* Validate the id of module */ + VTR_ASSERT( valid_module_id(module) ); + names_[module] = name; +} + /* Set a port to be a register */ void ModuleManager::set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register) { /* Find the port */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index ae487153c..5a9fcd507 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -18,6 +18,7 @@ #include #include +#include "vtr_vector.h" #include "module_manager_fwd.h" #include "device_port.h" @@ -53,6 +54,8 @@ class ModuleManager { /* Add a port to a module */ ModulePortId add_port(const ModuleId& module, const BasicPort& port_info, const enum e_module_port_type& port_type); + /* Set a name for a module */ + void set_module_name(const ModuleId& module, const std::string& name); /* Set a port to be a register */ void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register); /* Add a child module to a parent module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 85502cc48..7faf4a054 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -14,9 +14,17 @@ #include "module_manager.h" #include "module_manager_utils.h" +/****************************************************************************** + * Add a module to the module manager based on the circuit-level + * description of a circuit model + * This function add a module with a given customized name + * as well as add the ports of circuit model to the module manager + ******************************************************************************/ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { - ModuleId module = module_manager.add_module(circuit_lib.model_name(circuit_model)); + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::string& module_name) { + ModuleId module = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module); /* Add ports */ /* Find global ports and add one by one */ @@ -49,3 +57,18 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Return the new id */ return module; } + +/****************************************************************************** + * Add a module to the module manager based on the circuit-level + * description of a circuit model + * This function add a module in the name of the circuit model + * as well as add the ports of circuit model to the module manager + * + * This function is a wrapper of a more customizable function in the same name + ******************************************************************************/ +ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { + + return add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model, circuit_lib.model_name(circuit_model)); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 6868b71f7..c117b5a6c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -6,9 +6,16 @@ #ifndef MODULE_MANAGER_UTILS_H #define MODULE_MANAGER_UTILS_H +/* Include other header files which are dependency on the function declared below */ +#include "circuit_library.h" +#include "module_manager.h" + +ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::string& module_name); + ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); - #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index c237c23f9..47255c250 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -209,7 +209,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder); } - /* Close the file steam */ + /* Close the file stream */ fp.close(); /* Add fname to the linked list when debugging is finished */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index 8b30d6820..4919ff1fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -1,5 +1,5 @@ /*********************************************** - * Header file for verilog_submodule_mux.cpp + * Header file for verilog_mux.cpp **********************************************/ #ifndef VERILOG_MUX_H diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 1d8acb2ef..e0f2acc5d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -44,6 +44,7 @@ #include "verilog_essential_gates.h" #include "verilog_decoders.h" #include "verilog_lut.h" +#include "verilog_wire.h" /***** Subroutines *****/ @@ -3351,6 +3352,12 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); dump_verilog_submodule_wires(verilog_dir, submodule_dir, Arch.num_segments, Arch.Segments, Arch.spice->num_spice_model, Arch.spice->spice_models); + /* Create a vector of segments. TODO: should come from DeviceContext */ + std::vector L_segment_vec; + for (int i = 0; i < Arch.num_segments; ++i) { + L_segment_vec.push_back(Arch.Segments[i]); + } + print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); /* 4. Memories */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp new file mode 100644 index 000000000..c5e3778e6 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp @@ -0,0 +1,236 @@ +/*********************************************** + * This file includes functions to generate + * Verilog submodules for wires. + **********************************************/ +#include +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "module_manager.h" +#include "module_manager_utils.h" +#include "physical_types.h" +#include "vpr_types.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_submodule_utils.h" +#include "verilog_writer_utils.h" +#include "verilog_wire.h" + +/******************************************************************** + * Print a Verilog module of a regular wire segment + * Regular wire, which is 1-input and 1-output + * This type of wires are used in the local routing architecture + * +------+ + * input --->| wire |---> output + * +------+ + * + *******************************************************************/ +static +void print_verilog_wire_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& wire_model) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true, true); + + /* Makre sure the port size is what we want */ + VTR_ASSERT (1 == input_ports.size()); + VTR_ASSERT (1 == output_ports.size()); + VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); + VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Print the internal logic of Verilog module */ + /* Find the input port of the module */ + ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(input_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); + BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); + + /* Find the output port of the module */ + ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(output_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); + BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); + + /* Print wire declaration for the inputs and outputs */ + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_output_port) << ";" << std::endl; + + /* Direct shortcut */ + print_verilog_wire_connection(fp, module_output_port, module_input_port, false); + + /* Print timing info */ + print_verilog_submodule_timing(fp, circuit_lib, wire_model); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, circuit_lib.model_name(wire_model)); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print a Verilog module of a routing track wire segment + * Routing track wire, which is 1-input and dual output + * This type of wires are used in the global routing architecture. + * One of the output is wired to another Switch block multiplexer, + * while the mid-output is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + * + *******************************************************************/ +static +void print_verilog_routing_wire_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& wire_model, + const std::string& wire_subckt_name) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Makre sure the port size is what we want */ + VTR_ASSERT (1 == input_ports.size()); + VTR_ASSERT (1 == output_ports.size()); + VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); + VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model, wire_subckt_name); + + /* Add a mid-output port to the module */ + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Print the internal logic of Verilog module */ + /* Find the input port of the module */ + ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(input_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); + BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); + + /* Find the output port of the module */ + ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(output_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); + BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); + + /* Print wire declaration for the inputs and outputs */ + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_output_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_mid_output_port) << ";" << std::endl; + + /* Direct shortcut */ + print_verilog_wire_connection(fp, module_output_port, module_input_port, false); + print_verilog_wire_connection(fp, module_mid_output_port, module_input_port, false); + + /* Print timing info */ + print_verilog_submodule_timing(fp, circuit_lib, wire_model); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, circuit_lib.model_name(wire_model)); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +void print_verilog_submodule_wires(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::vector routing_segments, + const std::string& verilog_dir, + const std::string& submodule_dir) { + /* TODO: remove .bak when it is ready to be plugged in */ + std::string verilog_fname(submodule_dir + wires_verilog_file_name + ".bak"); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for wires (%s)...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Wires"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Print Verilog models for regular wires*/ + print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----")); + for (const auto& model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) { + /* Bypass user-defined circuit models */ + if (!circuit_lib.model_verilog_netlist(model).empty()) { + continue; + } + print_verilog_wire_module(module_manager, circuit_lib, fp, model); + } + print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----")); + + /* Create wire models for routing segments*/ + print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for routing track wires -----")); + + for (const auto& seg : routing_segments) { + VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); + VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); + /* Bypass user-defined circuit models */ + if (!circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) { + continue; + } + /* Give a unique name for subckt of wire_model of segment, + * circuit_model name is unique, and segment id is unique as well + */ + std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); + + /* Print a Verilog module */ + print_verilog_routing_wire_module(module_manager, circuit_lib, fp, seg.circuit_model, segment_wire_subckt_name); + } + print_verilog_comment(fp, std::string("----- END Verilog modules for routing track wires -----")); + + /* Close the file stream */ + fp.close(); + + /* Add fname to the linked list */ + /* Uncomment this when it is ready to be plugged in + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h new file mode 100644 index 000000000..1d4fc7c71 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h @@ -0,0 +1,23 @@ +/*********************************************** + * Header file for verilog_wire.cpp + **********************************************/ + +#ifndef VERILOG_WIRE_H +#define VERILOG_WIRE_H + +/* Include other header files which are dependency on the function declared below */ +#include +#include +#include "physical_types.h" +#include "vpr_types.h" + +#include "circuit_library.h" +#include "module_manager.h" + +void print_verilog_submodule_wires(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::vector routing_segments, + const std::string& verilog_dir, + const std::string& submodule_dir); + +#endif From c20e1824849ff3d67bc44a254b1614071e09c302 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 12 Sep 2019 20:56:30 -0600 Subject: [PATCH 186/482] plugged in the refactored wire Verilog generation --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 2 ++ vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp | 5 ++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index e0f2acc5d..25812f4c5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3349,9 +3349,11 @@ void dump_verilog_submodules(ModuleManager& module_manager, print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 3. Hardwires */ + /* vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); dump_verilog_submodule_wires(verilog_dir, submodule_dir, Arch.num_segments, Arch.Segments, Arch.spice->num_spice_model, Arch.spice->spice_models); + */ /* Create a vector of segments. TODO: should come from DeviceContext */ std::vector L_segment_vec; for (int i = 0; i < Arch.num_segments; ++i) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp index c5e3778e6..377865f3b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp @@ -175,8 +175,7 @@ void print_verilog_submodule_wires(ModuleManager& module_manager, std::vector routing_segments, const std::string& verilog_dir, const std::string& submodule_dir) { - /* TODO: remove .bak when it is ready to be plugged in */ - std::string verilog_fname(submodule_dir + wires_verilog_file_name + ".bak"); + std::string verilog_fname(submodule_dir + wires_verilog_file_name); /* Create the file stream */ std::fstream fp; @@ -229,8 +228,8 @@ void print_verilog_submodule_wires(ModuleManager& module_manager, /* Add fname to the linked list */ /* Uncomment this when it is ready to be plugged in - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); */ + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); return; } From 0e6c88dd52b5d3185b76c012da0c2d54c52ff2f8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 12 Sep 2019 21:06:53 -0600 Subject: [PATCH 187/482] delete legacy codes for wire Verilog generation --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 158 ------------------ 1 file changed, 158 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 25812f4c5..2bbbb0f0f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2329,75 +2329,6 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, return; } -static -void dump_verilog_wire_module(FILE* fp, - char* wire_subckt_name, - t_spice_model verilog_model) { - int num_input_port = 0; - int num_output_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check the wire model*/ - assert(NULL != verilog_model.wire_param); - assert(0 < verilog_model.wire_param->level); - /* Find the input port, output port*/ - input_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - - /* Asserts*/ - assert(1 == num_input_port); - assert(1 == num_output_port); - assert(1 == input_port[0]->size); - assert(1 == output_port[0]->size); - /* print the spice model*/ - fprintf(fp, "//-----Wire module, verilog_model_name=%s -----\n", verilog_model.name); - switch (verilog_model.type) { - case SPICE_MODEL_CHAN_WIRE: - /* Add an output at middle point for connecting CB inputs */ - fprintf(fp, "module %s (\n", wire_subckt_name); - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) { - fprintf(fp, ",\n"); - } - fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n", - input_port[0]->prefix, output_port[0]->prefix); - fprintf(fp, "\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); - fprintf(fp, "\tassign mid_out = %s;\n", input_port[0]->prefix); - break; - case SPICE_MODEL_WIRE: - /* Add an output at middle point for connecting CB inputs */ - fprintf(fp, "module %s (\n", - wire_subckt_name); - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE)) { - fprintf(fp, ",\n"); - } - fprintf(fp, "input wire %s, output wire %s);\n", - input_port[0]->prefix, output_port[0]->prefix); - /* Direct shortcut */ - fprintf(fp, "\t\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model! Expect [chan_wire|wire].\n", - __FILE__, __LINE__); - exit(1); - } - - /* Finish*/ - fprintf(fp, "endmodule\n"); - fprintf(fp, "//-----END Wire module, verilog_model_name=%s -----\n", verilog_model.name); - fprintf(fp, "\n"); - - return; -} - /* Dump one module of a LUT */ static void dump_verilog_submodule_one_lut(FILE* fp, @@ -2953,88 +2884,6 @@ void dump_verilog_submodule_luts(char* verilog_dir, return; } -static -void dump_verilog_submodule_wires(char* verilog_dir, - char* subckt_dir, - int num_segments, - t_segment_inf* segments, - int num_spice_model, - t_spice_model* spice_models) { - FILE* fp = NULL; - char* verilog_name = my_strcat(subckt_dir, wires_verilog_file_name); - char* seg_wire_subckt_name = NULL; - char* seg_index_str = NULL; - int iseg, imodel, len_seg_subckt_name; - - fp = fopen(verilog_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s",__FILE__, __LINE__, wires_verilog_file_name); - exit(1); - } - dump_verilog_file_header(fp,"Wires"); - - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Output wire models*/ - for (imodel = 0; imodel < num_spice_model; imodel++) { - /* Bypass user-defined spice models */ - if (NULL != spice_models[imodel].verilog_netlist) { - continue; - } - if (SPICE_MODEL_WIRE == spice_models[imodel].type) { - assert(NULL != spice_models[imodel].wire_param); - dump_verilog_wire_module(fp, spice_models[imodel].name, - spice_models[imodel]); - } - } - - /* Create wire models for routing segments*/ - fprintf(fp,"//----- Wire models for segments in routing -----\n"); - for (iseg = 0; iseg < num_segments; iseg++) { - assert(NULL != segments[iseg].spice_model); - assert(SPICE_MODEL_CHAN_WIRE == segments[iseg].spice_model->type); - assert(NULL != segments[iseg].spice_model->wire_param); - /* Give a unique name for subckt of wire_model of segment, - * spice_model name is unique, and segment name is unique as well - */ - seg_index_str = my_itoa(iseg); - len_seg_subckt_name = strlen(segments[iseg].spice_model->name) - + 4 + strlen(seg_index_str) + 1; /* '\0'*/ - seg_wire_subckt_name = (char*)my_malloc(sizeof(char)*len_seg_subckt_name); - sprintf(seg_wire_subckt_name,"%s_seg%s", - segments[iseg].spice_model->name, seg_index_str); - /* Bypass user-defined spice models */ - if (NULL != segments[iseg].spice_model->verilog_netlist) { - continue; - } - dump_verilog_wire_module(fp, seg_wire_subckt_name, - *(segments[iseg].spice_model)); - } - - /* Create module for hard-wired VDD and GND */ - /* - for (imodel = 0; imodel < num_spice_model; imodel++) { - if (SPICE_MODEL_VDD == spice_models[imodel].type) { - dump_verilog_hard_wired_vdd(fp, spice_models[imodel]); - } else if (SPICE_MODEL_GND == spice_models[imodel].type) { - dump_verilog_hard_wired_gnd(fp, spice_models[imodel]); - } - } - */ - - /* Close the file handler */ - fclose(fp); - - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); - - /*Free*/ - my_free(seg_index_str); - my_free(seg_wire_subckt_name); - - return; -} - static void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, @@ -3322,7 +3171,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Registering user-defined modules...\n"); add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib); - vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); print_verilog_submodule_essentials(module_manager, std::string(verilog_dir), std::string(submodule_dir), @@ -3336,7 +3184,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, verilog_dir, submodule_dir); - vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n"); print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 2. LUTes */ @@ -3349,11 +3196,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 3. Hardwires */ - /* - vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); - dump_verilog_submodule_wires(verilog_dir, submodule_dir, Arch.num_segments, Arch.Segments, - Arch.spice->num_spice_model, Arch.spice->spice_models); - */ /* Create a vector of segments. TODO: should come from DeviceContext */ std::vector L_segment_vec; for (int i = 0; i < Arch.num_segments; ++i) { From b920f0fc38843837ce7c10e1c0591701c8f1aa9f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 11:41:54 -0600 Subject: [PATCH 188/482] refactored user template Verilog generation --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 194 ++++++++++++++---- .../vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp | 2 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 5 +- 3 files changed, 157 insertions(+), 44 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 2bbbb0f0f..48449931b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -22,14 +22,18 @@ #include "vpr_utils.h" #include "path_delay.h" #include "stats.h" +#include "vtr_assert.h" /* Include FPGA-SPICE utils */ #include "linkedlist.h" #include "fpga_x2p_utils.h" +#include "fpga_x2p_naming.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_mux_utils.h" #include "fpga_x2p_bitstream_utils.h" #include "mux_library.h" +#include "module_manager.h" +#include "module_manager_utils.h" /* Include verilog utils */ #include "verilog_global.h" @@ -37,15 +41,16 @@ #include "verilog_pbtypes.h" #include "verilog_decoder.h" -#include "verilog_submodules.h" - #include "mux_utils.h" +#include "verilog_writer_utils.h" #include "verilog_mux.h" #include "verilog_essential_gates.h" #include "verilog_decoders.h" #include "verilog_lut.h" #include "verilog_wire.h" +#include "verilog_submodules.h" + /***** Subroutines *****/ static @@ -3106,49 +3111,152 @@ void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, ********************************************************************/ static void add_user_defined_verilog_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - /* Module port depends on the model port attributes: - * Any model ports whose is_global_port() is true => MODULE_GLOBAL_PORT - * Inout model port: SPICE_MODEL_PORT_INOUT => MODULE_INOUT_PORT - * Input model port: SPICE_MODEL_PORT_INPUT/SRAM/BL/WL/BLB/WLB => MODULE_INPUT_PORT - * Output model port: SPICE_MODEL_PORT_OUTPUT => MODULE_OUTPUT_PORT - * Clock model port: SPICE_MODEL_PORT_CLOCK => MODULE_CLOCK_PORT - */ - std::map port_type2type_map; - port_type2type_map[SPICE_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_CLOCK] = ModuleManager::MODULE_CLOCK_PORT; - - /* Iterate over verilog modules */ + const CircuitLibrary& circuit_lib, + const std::vector& routing_segments) { + /* Iterate over Verilog modules */ for (const auto& model : circuit_lib.models()) { /* We only care about user-defined models */ if (true == circuit_lib.model_verilog_netlist(model).empty()) { continue; } + /* Skip Routing channel wire models because they need a different name. Do it later */ + if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { + continue; + } /* Reach here, the model requires a user-defined Verilog netlist, * Register it in the module_manager */ - ModuleId module_id = module_manager.add_module(circuit_lib.model_name(model)); - /* Iterate over the ports of circuit model, and add them to module_manager */ - for (const auto& model_port : circuit_lib.model_ports(model)) { - /* Create port information */ - BasicPort module_port(circuit_lib.port_lib_name(model_port), circuit_lib.port_size(model_port)); - - /* Deposite a module port type */ - ModuleManager::e_module_port_type module_port_type = port_type2type_map[circuit_lib.port_type(model_port)]; - /* Force a global port type */ - if (true == circuit_lib.port_is_global(model_port)) { - module_port_type = ModuleManager::MODULE_GLOBAL_PORT; - } - module_manager.add_port(module_id, module_port, module_port_type); - } + add_circuit_model_to_module_manager(module_manager, circuit_lib, model); } + + /* Register the routing channel wires */ + for (const auto& seg : routing_segments) { + VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); + VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); + /* We care only user-defined circuit models */ + if (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) { + continue; + } + /* Give a unique name for subckt of wire_model of segment, + * circuit_model name is unique, and segment id is unique as well + */ + std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); + + /* Find the output port*/ + std::vector output_ports = circuit_lib.model_ports_by_type(seg.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Make sure the port size is what we want */ + VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); + + /* Add a mid-output port to the module */ + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + } +} + +/* Print a template for a user-defined circuit model + * The template will include just the port declaration of the Verilog module + * The template aims to help user to write Verilog codes with a guaranteed + * module definition, which can be correctly instanciated (with correct + * port mapping) in the FPGA fabric + */ +static +void print_one_verilog_template_module(const ModuleManager& module_manager, + std::fstream& fp, + const std::string& module_name) { + /* Ensure a valid file handler*/ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Template Verilog module for " + module_name + " -----")); + + /* Find the module in module manager, which should be already registered */ + /* TODO: routing channel wire model may have a different name! */ + ModuleId template_module = module_manager.find_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != template_module); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, template_module); + /* Finish dumping ports */ + + print_verilog_comment(fp, std::string("----- Internal logic should start here -----")); + + /* Add some empty lines as placeholders for the internal logic*/ + fp << std::endl << std::endl; + + print_verilog_comment(fp, std::string("----- Internal logic should end here -----")); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/* Print a template of all the submodules that are user-defined + * The template will include just the port declaration of the submodule + * The template aims to help user to write Verilog codes with a guaranteed + * module definition, which can be correctly instanciated (with correct + * port mapping) in the FPGA fabric + */ +static +void print_verilog_submodule_templates(const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector& routing_segments, + const std::string& verilog_dir, + const std::string& submodule_dir) { + std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name + ".bak"); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating template for user-defined Verilog modules (%s)...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Template for user-defined Verilog modules"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Output essential models*/ + for (const auto& model : circuit_lib.models()) { + /* Focus on user-defined modules, which must have a Verilog netlist defined */ + if (circuit_lib.model_verilog_netlist(model).empty()) { + continue; + } + /* Skip Routing channel wire models because they need a different name. Do it later */ + if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { + continue; + } + /* Print a Verilog template for the circuit model */ + print_one_verilog_template_module(module_manager, fp, circuit_lib.model_name(model)); + } + + /* Register the routing channel wires */ + for (const auto& seg : routing_segments) { + VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); + VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); + /* We care only user-defined circuit models */ + if (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) { + continue; + } + /* Give a unique name for subckt of wire_model of segment, + * circuit_model name is unique, and segment id is unique as well + */ + std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); + /* Print a Verilog template for the circuit model */ + print_one_verilog_template_module(module_manager, fp, segment_wire_subckt_name); + } + + /* close file stream */ + fp.close(); + + /* No need to add the template to the subckt include files! */ } /********************************************************************* @@ -3164,12 +3272,18 @@ void dump_verilog_submodules(ModuleManager& module_manager, t_det_routing_arch* routing_arch, t_syn_verilog_opts fpga_verilog_opts) { + /* Create a vector of segments. TODO: should come from DeviceContext */ + std::vector L_segment_vec; + for (int i = 0; i < Arch.num_segments; ++i) { + L_segment_vec.push_back(Arch.Segments[i]); + } + /* TODO: Register all the user-defined modules in the module manager * This should be done prior to other steps in this function, * because they will be instanciated by other primitive modules */ vpr_printf(TIO_MESSAGE_INFO, "Registering user-defined modules...\n"); - add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib); + add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib, L_segment_vec); print_verilog_submodule_essentials(module_manager, std::string(verilog_dir), @@ -3196,11 +3310,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 3. Hardwires */ - /* Create a vector of segments. TODO: should come from DeviceContext */ - std::vector L_segment_vec; - for (int i = 0; i < Arch.num_segments; ++i) { - L_segment_vec.push_back(Arch.Segments[i]); - } print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); /* 4. Memories */ @@ -3218,6 +3327,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, submodule_dir, Arch.spice->num_spice_model, Arch.spice->spice_models); + print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); } /* Create a header file to include all the subckts */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp index 377865f3b..4506aa106 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp @@ -123,7 +123,7 @@ void print_verilog_routing_wire_module(ModuleManager& module_manager, std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Makre sure the port size is what we want */ + /* Make sure the port size is what we want */ VTR_ASSERT (1 == input_ports.size()); VTR_ASSERT (1 == output_ports.size()); VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 674ce713e..ca832260b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -139,7 +139,8 @@ void print_verilog_module_ports(std::fstream& fp, } /* Output any port that is registered */ - fp << "//----- Registered ports -----" << std::endl; + fp << std::endl; + fp << "//----- BEGIN Registered ports -----" << std::endl; for (const auto& kv : port_type2type_map) { for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { /* Skip the ports that are not registered */ @@ -153,6 +154,8 @@ void print_verilog_module_ports(std::fstream& fp, fp << ";" << std::endl; } } + fp << "//----- END Registered ports -----" << std::endl; + fp << std::endl; } /************************************************ From d8b93490667297e0d9e827466c4a557298c54f95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 11:48:25 -0600 Subject: [PATCH 189/482] remove legacy codes --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 101 ------------------ 1 file changed, 101 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 48449931b..68a6b0afb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3008,102 +3008,6 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, return; } -/* Give a template for a user-defined module */ -static -void dump_one_verilog_template_module(FILE* fp, - t_spice_model* cur_spice_model) { - int iport; - int cnt = 0; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "//----- Template Verilog module for %s -----\n", - cur_spice_model->name); - - /* dump module body */ - fprintf(fp, "module %s (\n", - cur_spice_model->name); - - /* Dump ports */ - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - if (0 < cnt) { - fprintf(fp, ",\n"); - } - dump_verilog_generic_port(fp, - convert_spice_model_port_type_to_verilog_port_type(cur_spice_model->ports[iport].type), - cur_spice_model->ports[iport].lib_name, - cur_spice_model->ports[iport].size - 1, 0); - cnt++; - /* if there is an inv_prefix, we will dump the paired port */ - if (NULL == cur_spice_model->ports[iport].inv_prefix) { - continue; - } - if (0 < cnt) { - fprintf(fp, ",\n"); - } - dump_verilog_generic_port(fp, - convert_spice_model_port_type_to_verilog_port_type(cur_spice_model->ports[iport].type), - cur_spice_model->ports[iport].inv_prefix, - cur_spice_model->ports[iport].size - 1, 0); - cnt++; - } - - fprintf(fp, ");\n"); - - fprintf(fp, "\n//------ User-defined Verilog netlist model should start from here! -----\n"); - - - fprintf(fp, "endmodule\n"); - - fprintf(fp, "\n"); - - return; -} - -/* Give a template of all the submodules that are user-defined */ -static -void dump_verilog_submodule_templates(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* submodule_dir, - int num_spice_model, - t_spice_model* spice_models) { - int imodel; - char* verilog_name = my_strcat(submodule_dir, user_defined_template_verilog_file_name); - FILE* fp = NULL; - - /* Create file */ - fp = fopen(verilog_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Verilog netlist %s", - __FILE__, __LINE__, user_defined_template_verilog_file_name); - exit(1); - } - dump_verilog_file_header(fp,"User-defined netlists template"); - - /* Output essential models*/ - for (imodel = 0; imodel < num_spice_model; imodel++) { - /* Focus on user-defined modules */ - if (NULL == spice_models[imodel].verilog_netlist) { - continue; - } - /* Create the port template */ - dump_one_verilog_template_module(fp, &spice_models[imodel]); - } - - /* close file */ - fclose(fp); - - /* Free */ - my_free(verilog_name); - - return; -} - /********************************************************************* * Register all the user-defined modules in the module manager * Walk through the circuit library and add user-defined circuit models @@ -3322,11 +3226,6 @@ void dump_verilog_submodules(ModuleManager& module_manager, /* 6. Dump template for all the modules */ if (TRUE == fpga_verilog_opts.print_user_defined_template) { - dump_verilog_submodule_templates(cur_sram_orgz_info, - verilog_dir, - submodule_dir, - Arch.spice->num_spice_model, - Arch.spice->spice_models); print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); } From 56f40cf46cda4672814482f247f0245b9ec8608f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 12:22:57 -0600 Subject: [PATCH 190/482] light modification on Verilog Mux generation and start refactoring memory Verilog generation --- .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 93 +++++++++++++++++++ .../vpr/SRC/fpga_x2p/verilog/verilog_memory.h | 22 +++++ .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 10 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.h | 4 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 7 +- 5 files changed, 126 insertions(+), 10 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp new file mode 100644 index 000000000..fde7d9d03 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -0,0 +1,93 @@ +/********************************************************************* + * This file includes functions to generate Verilog submodules for + * the memories that are affiliated to multiplexers and other programmable + * circuit models, such as IOPADs, LUTs, etc. + ********************************************************************/ +#include +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "mux_graph.h" +#include "module_manager.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "mux_utils.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_memory.h" + +void print_verilog_submodule_memories(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const std::string& verilog_dir, + const std::string& submodule_dir) { + + /* TODO: Generate modules into a .bak file now. Rename after it is verified */ + std::string verilog_fname(submodule_dir + memories_verilog_file_name); + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for memories (%s) ...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Memories used in FPGA"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create the memory circuits for the multiplexer */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); + /* Create a Verilog module for the memories used by the multiplexer */ + /* Bypass the non-MUX circuit models (i.e., LUTs). + * They should be handled in a different way + * Memory circuits of LUT includes both regular and mode-select ports + */ + if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { + continue; + } + } + + /* Create the memory circuits for non-MUX circuit models. + * In this case, the memory modules are designed to interface + * the mode-select ports + */ + for (const auto& model : circuit_lib.models()) { + /* Bypass MUXes, they have already been considered */ + if (SPICE_MODEL_MUX == circuit_lib.model_type(model)) { + continue; + } + /* Bypass those modules without any SRAM ports */ + std::vector sram_ports = circuit_lib.model_ports_by_type(model, SPICE_MODEL_PORT_SRAM, true); + if (0 == sram_ports.size()) { + continue; + } + /* Create a Verilog module for the memories used by the circuit model */ + } + + /* Close the file stream */ + fp.close(); + + /* TODO: Add fname to the linked list when debugging is finished */ + /* + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h new file mode 100644 index 000000000..08ecc4ec3 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h @@ -0,0 +1,22 @@ +/*********************************************** + * Header file for verilog_memory.cpp + **********************************************/ + +#ifndef VERILOG_MEMORY_H +#define VERILOG_MEMORY_H + +/* Include other header files which are dependency on the function declared below */ +#include + +#include "circuit_library.h" +#include "mux_graph.h" +#include "mux_library.h" +#include "module_manager.h" + +void print_verilog_submodule_memories(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const std::string& verilog_dir, + const std::string& submodule_dir); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 4ec37f3cd..3244cce1b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -1856,11 +1856,11 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* submodule_dir) { + const std::string& verilog_dir, + const std::string& submodule_dir) { /* TODO: Generate modules into a .bak file now. Rename after it is verified */ - std::string verilog_fname(my_strcat(submodule_dir, muxes_verilog_file_name)); + std::string verilog_fname(submodule_dir + muxes_verilog_file_name); verilog_fname += ".bak"; /* Create the file stream */ @@ -1900,7 +1900,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph); } - /* Close the file steam */ + /* Close the file stream */ fp.close(); /* TODO: @@ -1915,7 +1915,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, /* TODO: Add fname to the linked list when debugging is finished */ /* - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index 4919ff1fb..2db3e1f45 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -17,7 +17,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* submodule_dir); + const std::string& verilog_dir, + const std::string& submodule_dir); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 68a6b0afb..980ecc2ba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -47,6 +47,7 @@ #include "verilog_essential_gates.h" #include "verilog_decoders.h" #include "verilog_lut.h" +#include "verilog_memory.h" #include "verilog_wire.h" #include "verilog_submodules.h" @@ -3110,7 +3111,7 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager, const std::vector& routing_segments, const std::string& verilog_dir, const std::string& submodule_dir) { - std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name + ".bak"); + std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name); /* Create the file stream */ std::fstream fp; @@ -3199,8 +3200,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); - print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, - verilog_dir, submodule_dir); + print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir)); print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); @@ -3220,6 +3220,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n"); dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 5. Dump decoder modules only when memory bank is required */ dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir); From 99c30fa7dd8b40303d608a5266f1da83e64f18d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 14:02:04 -0600 Subject: [PATCH 191/482] keep refactoring the memory Verilog generation --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 7 + vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 33 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 3 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 1 + .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 255 +++++++++++++++++- 6 files changed, 299 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 5f82e12ae..6eeb5fa7c 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -819,6 +819,13 @@ CircuitModelId CircuitLibrary::port_tri_state_model(const CircuitPortId& circuit return port_tri_state_model_ids_[circuit_port_id]; } +/* Return circuit model name which is used to tri-state a port */ +std::string CircuitLibrary::port_tri_state_model_name(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_tri_state_model_names_[circuit_port_id]; +} + /* Return the id of parent circuit model for a circuit port */ CircuitModelId CircuitLibrary::port_parent_model(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 30ae83aab..220be6a97 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -287,6 +287,7 @@ class CircuitLibrary { std::vector port_lut_output_masks(const CircuitPortId& circuit_port_id) const; std::string port_tri_state_map(const CircuitPortId& circuit_port_id) const; CircuitModelId port_tri_state_model(const CircuitPortId& circuit_port_id) const; + std::string port_tri_state_model_name(const CircuitPortId& circuit_port_id) const; CircuitModelId port_parent_model(const CircuitPortId& circuit_port_id) const; std::string model_name(const CircuitPortId& port_id) const; public: /* Public Accessors: Timing graph */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index c7a5df808..bdc3bbfbb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -3148,6 +3148,39 @@ void config_spice_models_sram_port_spice_model(int num_spice_model, return; } +/******************************************************************** + * Link the circuit model of SRAM ports of each circuit model + * to a default SRAM circuit model. + * This function aims to ease the XML writing, allowing users to skip + * the circuit model definition for SRAM ports that are used by default + * TODO: Maybe deprecated as we prefer strict definition + *******************************************************************/ +void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib, + const CircuitModelId& default_sram_model) { + for (const auto& model : circuit_lib.models()) { + for (const auto& port : circuit_lib.model_ports(model)) { + /* Bypass non SRAM ports */ + if (SPICE_MODEL_PORT_SRAM != circuit_lib.port_type(port)) { + continue; + } + /* Write for the default SRAM SPICE model! */ + circuit_lib.set_port_tri_state_model_id(port, default_sram_model); + /* Only show warning when we try to override the given spice_model_name ! */ + if (circuit_lib.port_tri_state_model_name(port).empty()) { + continue; + } + /* Give a warning !!! */ + if (0 != circuit_lib.model_name(default_sram_model).compare(circuit_lib.port_tri_state_model_name(port))) { + vpr_printf(TIO_MESSAGE_WARNING, + "Overwrite SRAM circuit model for circuit model port (name:%s, port:%s) to be the correct one (name:%s)!\n", + circuit_lib.model_name(model).c_str(), + circuit_lib.port_prefix(port).c_str(), + circuit_lib.model_name(default_sram_model).c_str()); + } + } + } +} + void determine_sb_port_coordinator(t_sb cur_sb_info, int side, int* port_x, int* port_y) { /* Check */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 8d0408bcd..8a5a0a9e4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -362,6 +362,9 @@ void config_spice_models_sram_port_spice_model(int num_spice_model, t_spice_model* spice_models, t_spice_model* default_sram_spice_model); +void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib, + const CircuitModelId& default_sram_model); + void determine_sb_port_coordinator(t_sb cur_sb_info, int side, int* port_x, int* port_y); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a6257608a..19c80b25e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -236,6 +236,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models, Arch.sram_inf.verilog_sram_inf_orgz->spice_model); + config_circuit_models_sram_port_to_default_sram_model(Arch.spice->circuit_lib, Arch.sram_inf.verilog_sram_inf_orgz->circuit_model); /* Assign global variables of input and output pads */ iopad_verilog_model = find_iopad_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index fde7d9d03..2dea66cc5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -26,6 +26,258 @@ #include "verilog_writer_utils.h" #include "verilog_memory.h" +/********************************************************************* + * Generate Verilog modules for the memories that are used + * by CMOS (SRAM-based) multiplexers + * We support: + * 1. Flat memory modules + * + * in[0] in[1] in[N] + * | | | + * v v v + * +-------+ +-------+ +-------+ + * | SRAM | | SRAM | ... | SRAM | + * | [0] | | [1] | | [N-1] | + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Multiplexer Configuration port | + * + * 2. TODO: Local decoders + * + * in[0] in[1] in[N] + * | | | + * v v v + * +-------+ +-------+ +-------+ + * | SRAM | | SRAM | ... | SRAM | + * | [0] | | [1] | | [N-1] | + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Local decoders | + * +------------------------------------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Multiplexer Configuration port | + * + * 3. TODO: Scan-chain organization + * + * in[0] in[1] in[N] + * | | | + * v v v + * +-------+ +-------+ +-------+ + * scan-chain--->| SRAM |--->| SRAM |--->... --->| SRAM |---->scan-chain + * input&clock | [0] | | [1] | | [N-1] | output + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +-----------------------------------------+ + * | Multiplexer Configuration port | + * + * 4. TODO: Memory bank organization + * + * Bit lines Word lines + * | | + * v v + * +------------------------------------+ + * | Multiplexer Configuration port | + * +------------------------------------+ + * | | | + * v v v + * +-------+ +-------+ +-------+ + * | SRAM | | SRAM | ... | SRAM | + * | [0] | | [1] | | [N-1] | + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Multiplexer Configuration port | + + * + ********************************************************************/ +static +void print_verilog_cmos_mux_memory_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Generate module name */ + std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, mux_model, + find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), + std::string(verilog_mem_posfix)); + + /* Get the sram ports from the mux */ + std::vector mux_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); + VTR_ASSERT( 1 == mux_sram_ports.size() ); + /* Get the circuit model for the memory circuit used by the multiplexer */ + CircuitModelId sram_model = circuit_lib.port_tri_state_model(mux_sram_ports[0]); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* Create a module and add to the module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Get the global ports required by the SRAM */ + std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true, true); + /* Get the input ports from the SRAM */ + std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the SRAM */ + std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the BL/WL ports from the SRAM */ + std::vector sram_bl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BL, true); + std::vector sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB, true); + std::vector sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WL, true); + std::vector sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB, true); + + /* Find the number of SRAMs in the module, this is also the port width */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Add module ports: the ports come from the SRAM modules */ + /* Add each global port */ + for (const auto& port : sram_global_ports) { + /* Configure each global port: global ports are shared among the SRAMs, so it is independent from the memory size */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port: port width should match the number of memories */ + for (const auto& port : sram_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_bl_ports) { + BasicPort bl_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, bl_port, ModuleManager::MODULE_INPUT_PORT); + } + for (const auto& port : sram_blb_ports) { + BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); + } + for (const auto& port : sram_wl_ports) { + BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); + } + for (const auto& port : sram_wlb_ports) { + BasicPort wlb_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, wlb_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Find the sram module in the module manager */ + ModuleId sram_module_id = module_manager.find_module(circuit_lib.model_name(sram_model)); + + /* Instanciate each submodule */ + for (size_t i = 0; i < num_mems; ++i) { + /* Create a port-to-port map */ + std::map port2port_name_map; + /* Map instance inputs [i] to SRAM module input */ + for (const auto& port : sram_input_ports) { + BasicPort instance_input_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; + } + /* Map instance outputs [i] to SRAM module input */ + for (const auto& port : sram_output_ports) { + BasicPort instance_output_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_output_port; + } + /* Map instance BL[i] and WL[i] to SRAM module input */ + for (const auto& port : sram_bl_ports) { + BasicPort instance_bl_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_bl_port; + } + for (const auto& port : sram_blb_ports) { + BasicPort instance_blb_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_blb_port; + } + for (const auto& port : sram_wl_ports) { + BasicPort instance_wl_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_wl_port; + } + for (const auto& port : sram_wlb_ports) { + BasicPort instance_wlb_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_wlb_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, sram_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(sram_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, sram_module_id); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + +/********************************************************************* + * Generate Verilog modules for the memories that are used + * by multiplexers + * + * +----------------+ + * mem_in --->| Memory Module |---> mem_out + * +----------------+ + * | | ... | | + * v v v v SRAM ports of multiplexer + * +---------------------+ + * in--->| Multiplexer Module |---> out + * +---------------------+ + ********************************************************************/ +static +void print_verilog_mux_memory_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + /* Multiplexers built with different technology is in different organization */ + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + print_verilog_cmos_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* We do not need a memory submodule for RRAM MUX, + * RRAM are embedded in the datapath + * TODO: generate local encoders for RRAM-based multiplexers here!!! + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + exit(1); + } +} + + +/********************************************************************* + * Generate Verilog modules for + * the memories that are affiliated to multiplexers and other programmable + * circuit models, such as IOPADs, LUTs, etc. + * + * We keep the memory modules separated from the multiplexers and other + * programmable circuit models, for the sake of supporting + * various configuration schemes. + * By following such organiztion, the Verilog modules of the circuit models + * implements the functionality (circuit logic) only, while the memory Verilog + * modules implements the memory circuits as well as configuration protocols. + * For example, the local decoders of multiplexers are implemented in the + * memory modules. + * Take another example, the memory circuit can implement the scan-chain or + * memory-bank organization for the memories. + ********************************************************************/ void print_verilog_submodule_memories(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, @@ -55,7 +307,6 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, for (auto mux : mux_lib.muxes()) { const MuxGraph& mux_graph = mux_lib.mux_graph(mux); CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); - /* Create a Verilog module for the memories used by the multiplexer */ /* Bypass the non-MUX circuit models (i.e., LUTs). * They should be handled in a different way * Memory circuits of LUT includes both regular and mode-select ports @@ -63,6 +314,8 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { continue; } + /* Create a Verilog module for the memories used by the multiplexer */ + print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph); } /* Create the memory circuits for non-MUX circuit models. From 009c0d63b507cc408502f8bf977d5cf5044f1c3e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 15:05:31 -0600 Subject: [PATCH 192/482] refactored the memory bank. Ready to plug-in the test --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 19 +++++ vpr7_x2p/libarchfpga/SRC/circuit_library.h | 4 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 13 +++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 ++ .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 76 +++++++++++++------ 5 files changed, 93 insertions(+), 24 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 6eeb5fa7c..6a7d23a64 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -592,6 +592,25 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ return global_ports; } + +/* Recursively find all the global ports in the circuit model / sub circuit_model + * whose port type matches users' specification + */ +std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, + const std::vector& types, + const bool& recursive, + const bool& ignore_config_memories) const { + std::vector global_ports; + std::vector ignore_list; + + for (const auto& port_type : types) { + std::vector global_port_by_type = model_global_ports_by_type(model_id, port_type, recursive, ignore_config_memories); + /* Insert the vector to the final global_ports */ + global_ports.insert(global_ports.begin(), global_port_by_type.begin(), global_port_by_type.end()); + } + return global_ports; +} + /* Recursively find all the global ports in the circuit model / sub circuit_model * but ignore all the SRAM and SCFF, which are configuration memories */ diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 220be6a97..56de466a7 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -258,6 +258,10 @@ class CircuitLibrary { const enum e_spice_model_port_type& type, const bool& recursive, const std::vector& ignore_model_types) const; + std::vector model_global_ports_by_type(const CircuitModelId& model_id, + const std::vector& type, + const bool& recursive, + const bool& ignore_config_memories) const; std::vector model_global_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, const bool& recursive, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 32ae2f723..66a28eff3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -122,9 +122,20 @@ std::string generate_segment_wire_subckt_name(const std::string& wire_model_name * input --->| Routing track wire |--------->| Switch Block * +--------------------+ output | * +-------------- - + * ********************************************************************/ std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name) { /* TODO: maybe have a postfix? */ return std::string("mid_" + regular_output_name); } + +/********************************************************************* + * Generate the module name for a memory sub-circuit + ********************************************************************/ +std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitModelId& sram_model, + const std::string& postfix) { + return std::string( circuit_lib.model_name(circuit_model) + "_" + circuit_lib.model_name(sram_model) + postfix ); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index edd125ea7..dbf6abff5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -33,4 +33,9 @@ std::string generate_segment_wire_subckt_name(const std::string& wire_model_name std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name); +std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const CircuitModelId& sram_model, + const std::string& postfix); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index 2dea66cc5..32026efdb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -99,31 +99,23 @@ * ********************************************************************/ static -void print_verilog_cmos_mux_memory_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { +void print_verilog_memory_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { /* Make sure we have a valid file handler*/ check_file_handler(fp); - /* Generate module name */ - std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, mux_model, - find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string(verilog_mem_posfix)); - - /* Get the sram ports from the mux */ - std::vector mux_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); - VTR_ASSERT( 1 == mux_sram_ports.size() ); - /* Get the circuit model for the memory circuit used by the multiplexer */ - CircuitModelId sram_model = circuit_lib.port_tri_state_model(mux_sram_ports[0]); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - /* Create a module and add to the module manager */ ModuleId module_id = module_manager.add_module(module_name); VTR_ASSERT(ModuleId::INVALID() != module_id); /* Get the global ports required by the SRAM */ - std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true, true); + std::vector global_port_types; + global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); + global_port_types.push_back(SPICE_MODEL_PORT_INPUT); + std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); /* Get the input ports from the SRAM */ std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); /* Get the output ports from the SRAM */ @@ -134,9 +126,6 @@ void print_verilog_cmos_mux_memory_module(ModuleManager& module_manager, std::vector sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WL, true); std::vector sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB, true); - /* Find the number of SRAMs in the module, this is also the port width */ - size_t num_mems = mux_graph.num_memory_bits(); - /* Add module ports: the ports come from the SRAM modules */ /* Add each global port */ for (const auto& port : sram_global_ports) { @@ -244,9 +233,25 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, const MuxGraph& mux_graph) { /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - print_verilog_cmos_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph); + case SPICE_MODEL_DESIGN_CMOS: { + /* Generate module name */ + std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, mux_model, + find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), + std::string(verilog_mem_posfix)); + + /* Get the sram ports from the mux */ + std::vector mux_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); + VTR_ASSERT( 1 == mux_sram_ports.size() ); + /* Get the circuit model for the memory circuit used by the multiplexer */ + CircuitModelId sram_model = circuit_lib.port_tri_state_model(mux_sram_ports[0]); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* Find the number of SRAMs in the module, this is also the port width */ + size_t num_mems = mux_graph.num_memory_bits(); + + print_verilog_memory_module(module_manager, circuit_lib, fp, module_name, sram_model, num_mems); break; + } case SPICE_MODEL_DESIGN_RRAM: /* We do not need a memory submodule for RRAM MUX, * RRAM are embedded in the datapath @@ -332,7 +337,32 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, if (0 == sram_ports.size()) { continue; } + /* Find the name of memory module */ + /* Get the total number of SRAMs */ + size_t num_mems = 0; + for (const auto& port : sram_ports) { + num_mems += circuit_lib.port_size(port); + } + /* Get the circuit model for the memory circuit used by the multiplexer */ + std::vector sram_models; + for (const auto& port : sram_ports) { + CircuitModelId sram_model = circuit_lib.port_tri_state_model(port); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + /* Found in the vector of sram_models, do not update and go to the next */ + if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) { + continue; + } + /* sram_model not found in the vector, update the sram_models */ + sram_models.push_back(sram_model); + } + /* Should have only 1 SRAM model */ + VTR_ASSERT( 1 == sram_models.size() ); + + /* Create the module name for the memory block */ + std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(verilog_mem_posfix)); + /* Create a Verilog module for the memories used by the circuit model */ + print_verilog_memory_module(module_manager, circuit_lib, fp, module_name, sram_models[0], num_mems); } /* Close the file stream */ From d6fc9c1c714d9b90a52f577d9bab93af9caf3a0a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 15:36:35 -0600 Subject: [PATCH 193/482] Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index 32026efdb..cb6754cea 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -288,8 +288,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir) { - - /* TODO: Generate modules into a .bak file now. Rename after it is verified */ + /* Plug in with the mux subckt */ std::string verilog_fname(submodule_dir + memories_verilog_file_name); verilog_fname += ".bak"; @@ -368,8 +367,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, /* Close the file stream */ fp.close(); - /* TODO: Add fname to the linked list when debugging is finished */ - /* + /* Add fname to the linked list submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); */ } From f9f3e290c0b3ff4f139d0ac8619018597f65b643 Mon Sep 17 00:00:00 2001 From: egiacomin Date: Wed, 17 Jul 2019 12:09:59 -0600 Subject: [PATCH 194/482] Update building.md --- tutorials/building.md | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tutorials/building.md b/tutorials/building.md index 7525493a4..a91448b36 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -1,7 +1,6 @@ # How to build? ## Dependencies - OpenFPGA requires all the following dependencies: - autoconf - automake @@ -39,10 +38,9 @@ OpenFPGA requires all the following dependencies: - qt5-default ## Docker - -If all these dependancies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). To ease customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: +If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: - docker run lnis/open_fpga:release
-*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".* +*Warning: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as "-v".* Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga @@ -50,8 +48,7 @@ Otherwise, a container where you can build OpenFPGA yourself can be created with [*docker download link*](https://www.docker.com/products/docker-desktop) ## Building - -To build the tool you have to go in OpenFPGA folder and do: +To build the tool, go in the OpenFPGA folder and do: - mkdir build && cd build - cmake .. -DCMAKE_BUILD_TYPE=debug - make (*WARNING using docker you cannot use "make -j", errors will happen*) From 63e6ed21b5cebdffe19175cc80e3bd0ba6903b1b Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 5 Aug 2019 14:06:07 -0600 Subject: [PATCH 195/482] Fully functional --- .../SRC/fpga_x2p/verilog/verilog_decoder.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 8 +- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 20 ++- .../SRC/fpga_x2p/verilog/verilog_routing.c | 8 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 114 ++++++++++++++---- .../verilog/verilog_top_netlist_utils.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 31 +++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 +- 8 files changed, 136 insertions(+), 52 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c index 3cb4f9a5a..4204a24f5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c @@ -372,7 +372,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp, inv_spice_model->name, inv_spice_model->prefix, instance_tag, inv_index); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index f87ff45a7..4e6ec1d4a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1142,7 +1142,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print the pin names! Input and output @@ -1278,7 +1278,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in); fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Inputs */ @@ -1874,7 +1874,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } else { if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, - FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), + FALSE)) { + fprintf(fp, ",\n"); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index a487a5677..a5d4012cc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -123,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -228,13 +228,17 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, } /* Call the subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ /*if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {*/ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } @@ -535,7 +539,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, formatted_subckt_prefix, cur_pb_type->name); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ @@ -610,14 +614,18 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, subckt_require_explicit_port_map = TRUE; } /* Call LUT subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* if we have to add global ports when dumping submodules of LUTs * otherwise, the port map here does not match that of submodules * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Connect inputs*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 76bf438d0..68e263466 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -836,7 +836,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1093,7 +1093,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -2975,7 +2975,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3222,7 +3222,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 980ecc2ba..2e92482b0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -170,7 +170,7 @@ void dump_verilog_cmos_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -288,7 +288,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -391,7 +391,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -457,7 +457,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -796,7 +796,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map), TRUE)) { fprintf(fp, ",\n"); } if (true == use_explicit_port_map) { @@ -839,7 +839,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -893,7 +893,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, spice_model.lut_intermediate_buffer->spice_model_name, nextlevel, out_idx); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1023,7 +1023,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1072,7 +1072,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1180,7 +1180,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, - my_bool_to_boolean(is_explicit_mapping))) { + my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -1345,7 +1345,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.name, mux_size); fprintf(fp, "module %s_mux(\n", spice_model.name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -1427,7 +1427,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1493,7 +1493,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, iport, ipin); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* check */ @@ -1603,7 +1603,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ @@ -1683,7 +1683,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(\n", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* inputs */ @@ -1701,7 +1701,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ @@ -1747,7 +1747,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -1832,7 +1832,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, gen_verilog_one_mux_module_name(&spice_model, mux_size)); } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -1888,7 +1888,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1951,7 +1951,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, spice_model.output_buffer->spice_model_name); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2335,6 +2335,74 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, return; } +void dump_verilog_wire_module(FILE* fp, + char* wire_subckt_name, + t_spice_model verilog_model) { + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check the wire model*/ + assert(NULL != verilog_model.wire_param); + assert(0 < verilog_model.wire_param->level); + /* Find the input port, output port*/ + input_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == input_port[0]->size); + assert(1 == output_port[0]->size); + /* print the spice model*/ + fprintf(fp, "//-----Wire module, verilog_model_name=%s -----\n", verilog_model.name); + switch (verilog_model.type) { + case SPICE_MODEL_CHAN_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, "module %s (\n", wire_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n", + input_port[0]->prefix, output_port[0]->prefix); + fprintf(fp, "\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); + fprintf(fp, "\tassign mid_out = %s;\n", input_port[0]->prefix); + break; + case SPICE_MODEL_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, "module %s (\n", + wire_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "input wire %s, output wire %s);\n", + input_port[0]->prefix, output_port[0]->prefix); + /* Direct shortcut */ + fprintf(fp, "\t\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model! Expect [chan_wire|wire].\n", + __FILE__, __LINE__); + exit(1); + } + + /* Finish*/ + fprintf(fp, "endmodule\n"); + fprintf(fp, "//-----END Wire module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "\n"); + + return; +} + /* Dump one module of a LUT */ static void dump_verilog_submodule_one_lut(FILE* fp, @@ -2379,7 +2447,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, fprintf(fp, "//-----LUT module, verilog_model_name=%s -----\n", verilog_model->name); fprintf(fp, "module %s (", verilog_model->name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print module port list */ @@ -2630,7 +2698,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_buffer->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2674,7 +2742,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_inverter->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index fc8e5a206..f3cc2c5b9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -934,7 +934,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, fprintf(fp, "%s ", cur_direct->spice_model->name); fprintf(fp, "%s_%d_ (", cur_direct->spice_model->prefix, cur_direct->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input: Print the source grid pin */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 882906a43..186cb5f68 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -851,7 +851,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map) { + boolean require_explicit_port_map, + boolean is_lib_name) { int dumped_port_cnt; boolean dump_comma = FALSE; t_spice_model_port* cur_spice_model_port = NULL; @@ -900,9 +901,13 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, } else { /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { - fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); - //cur_spice_model_port->prefix); + if (TRUE == is_lib_name) { + fprintf(fp, ".%s(", + cur_spice_model_port->lib_name); + } else { + fprintf(fp, ".%s(", + cur_spice_model_port->prefix); + } } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -1860,7 +1865,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -1913,7 +1918,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -1930,7 +1935,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -2026,7 +2031,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_num_sram); /* Input*/ @@ -2066,7 +2071,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -2083,7 +2088,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -3062,7 +3067,7 @@ void dump_verilog_mem_module_port_map(FILE* fp, * Other ports are not accepted!!! */ /* 1. Global ports! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map, TRUE)) { dump_first_comma = TRUE; } @@ -3179,7 +3184,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3227,7 +3232,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, case SPICE_SRAM_STANDALONE: /* SRAM subckts*/ /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_in[%d:%d], ", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 639843c57..84b456203 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -74,7 +74,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map); + boolean require_explicit_port_map, + boolean is_lib_name); int dump_verilog_global_ports(FILE* fp, t_llist* head, boolean dump_port_type, From 737cfb1086ce923aaa07bea73f5d99ab7f6c1102 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 8 Aug 2019 15:17:43 -0600 Subject: [PATCH 196/482] Correction to the explicit Verilog for FPGAs above 2x2 --- .../verilog/verilog_compact_netlist.c | 11 ++++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 38 +++++++++++++++++-- .../SRC/fpga_x2p/verilog/verilog_routing.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 8 ++++ .../SRC/fpga_x2p/verilog/verilog_tcl_utils.c | 4 ++ .../verilog/verilog_top_netlist_utils.c | 4 ++ 6 files changed, 59 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 8fc306335..c0fffbda9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -789,14 +789,15 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); + DeviceCoordinator unique_chan_coordinator = unique_mirror.get_side_block_coordinator(side_manager.get_side()); fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + gen_verilog_routing_channel_one_pin_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack), + unique_chan_coordinator.get_x(), unique_chan_coordinator.get_y(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack))); } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), @@ -815,6 +816,8 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } @@ -964,6 +967,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 68e263466..f343b8c69 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -313,6 +313,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping) { int height; @@ -360,7 +361,7 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(unique_x, unique_y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -565,6 +566,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, + 0, 0, /* No explicit mapping*/ FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: @@ -667,6 +669,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, + 0, /*Used in more recent version*/ + 0, /*Used in more recent version*/ FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: @@ -767,12 +771,16 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Find grid_x and grid_y */ grid_x = drive_rr_nodes[inode]->xlow; grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print a grid pin */ fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ + FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1029,7 +1037,9 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, false); + grid_x, grid_y, + 0,0,/*No explicit mapping */ + FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1803,6 +1813,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, } /* Dump OPINs of adjacent CLBs */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -1810,6 +1821,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ if (FALSE == dump_port_type) { fprintf(fp, ",\n"); @@ -2078,7 +2091,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ + 0,0, /*No explicit mapping */ + TRUE, false); /* Dump the direction of the port ! */ } } @@ -2315,6 +2329,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ + puts("CHECK4"); + const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -2322,6 +2338,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2524,6 +2542,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2772,6 +2792,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -2849,6 +2870,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3006,6 +3028,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3253,6 +3276,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,/*No explicit mapping*/ + 0,/*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3582,6 +3607,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, + 0,/*No explicit mapping */ + 0,/*No explicit mapping */ TRUE, false); } @@ -3785,6 +3812,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert((1 == side_cnt)||(2 == side_cnt)); side_cnt = 0; + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print the ports of grids*/ /* only check ipin_rr_nodes of cur_cb_info */ for (side = 0; side < cur_cb_info->num_sides; side++) { @@ -3802,6 +3830,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ TRUE, is_explicit_mapping); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index b126300e7..24b805a6b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -14,6 +14,7 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index b70163422..4311c341f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -638,6 +638,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -723,6 +725,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -1769,6 +1773,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } @@ -1827,6 +1833,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 256f281a9..c3df4ed95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -187,6 +187,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } @@ -231,6 +233,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index f3cc2c5b9..8e52d6f5a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -686,6 +686,8 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } @@ -833,6 +835,8 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, + 0, /*Used in a more recent version*/ + 0, /*Used in a more recent version*/ FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } From e64cfc5852ef6f4fb68ca8c63852e36f38686d53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 20:58:55 -0600 Subject: [PATCH 197/482] start refactoring memory decoders --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 1 - .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 147 ++++++++++++++++++ .../SRC/fpga_x2p/verilog/verilog_decoders.h | 5 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 1 - 5 files changed, 153 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 66a28eff3..6f559432d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -138,4 +138,3 @@ std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, const std::string& postfix) { return std::string( circuit_lib.model_name(circuit_model) + "_" + circuit_lib.model_name(sram_model) + postfix ); } - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index 47255c250..ea89dedd7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -216,3 +216,150 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); } +/*************************************************************************************** + * For scan-chain configuration organization: + * Generate the Verilog module of configuration module + * which connect configuration ports to SRAMs/SCFFs in a chain: + * + * +------+ +------+ +------+ + * sc_in--->| SCFF |--->| SCFF |---> ... --->| SCFF |----> sc_out + * +------+ +------+ +------+ + ***************************************************************************************/ +static +void print_verilog_scan_chain_config_module(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info) { + /* Validate the FILE handler */ + check_file_handler(fp); + + /* Get the total memory bits */ + int num_mem_bits = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + + /* Create a module definition for the configuration chain */ + print_verilog_comment(fp, std::string("----- BEGIN Configuration Peripheral for Scan-chain FFs -----")); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(std::string(verilog_config_peripheral_prefix)); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add the head of scan-chain: a 1-bit input port */ + BasicPort sc_head_port(std::string(top_netlist_scan_chain_head_prefix), 1); + module_manager.add_port(module_id, sc_head_port, ModuleManager::MODULE_INPUT_PORT); + /* Add the inputs of scan-chain FFs, which are the outputs of the module */ + BasicPort sc_input_port(std::string("chain_input"), num_mem_bits); + module_manager.add_port(module_id, sc_input_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add the outputs of scan-chain FFs, which are inputs of the module */ + BasicPort sc_output_port(std::string("chain_output"), num_mem_bits); + module_manager.add_port(module_id, sc_output_port, ModuleManager::MODULE_INPUT_PORT); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Declare the sc_output_port is a wire */ + fp << generate_verilog_port(VERILOG_PORT_WIRE, sc_output_port) << ";" << std::endl; + fp << std::endl; + + /* Connect scan-chain input to the first scan-chain input */ + BasicPort sc_first_input_port(sc_input_port.get_name(), 1); + print_verilog_wire_connection(fp, sc_first_input_port, sc_head_port, false); + + /* Connect the head of current scff to the tail of previous scff*/ + BasicPort chain_output_port(sc_input_port.get_name(), 1, num_mem_bits - 1); + BasicPort chain_input_port(sc_output_port.get_name(), 0, num_mem_bits - 2); + print_verilog_wire_connection(fp, chain_output_port, chain_input_port, false); + + print_verilog_comment(fp, std::string("----- END Configuration Peripheral for Scan-chain FFs -----")); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + return; +} + +/*************************************************************************************** + * Generate the configuration peripheral circuits for the top-level Verilog netlist + * This function will create Verilog modules depending on the configuration scheme: + * 1. Scan-chain: + * It will create a module which connects the Scan-Chain Flip-Flops (SCFFs) + * as a chain: + * + * +------+ +------+ +------+ + * sc_in--->| SCFF |--->| SCFF |---> ... --->| SCFF |----> sc_out + * +------+ +------+ +------+ + * + * 2. Memory bank: + * It will create a BL decoder and a WL decoder which will configure the SRAMs + * as a memory bank + * + * +------------------------+ + * | WL Decoder | + * +------------------------+ + * | | | ... | | + * v v v v v + * +---------+ +------------------------+ + * | |--->| | + * | | | | + * | BL |--->| | + * | Decoder | .. | FPGA Core logic | + * | | .. | | + * | |--->| | + * +---------+ +------------------------+ + ***************************************************************************************/ +void print_verilog_config_peripherals(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& submodule_dir) { + std::string verilog_fname(submodule_dir + config_peripheral_verilog_file_name); + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Print out debugging information for if the file is not opened/created properly */ + vpr_printf(TIO_MESSAGE_INFO, + "Creating Verilog netlist for configuration peripherals (%s)...\n", + verilog_fname.c_str()); + + print_verilog_file_header(fp, "Configuration Peripheral Circuits"); + + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a library for decoders */ + DecoderLibrary decoder_lib; + + switch(cur_sram_orgz_info->type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + print_verilog_scan_chain_config_module(module_manager, fp, cur_sram_orgz_info); + break; + case SPICE_SRAM_MEMORY_BANK: + /* TODO: Finish refactoring this part after the sram_orgz_info ! */ + /* + dump_verilog_decoder(fp, cur_sram_orgz_info); + dump_verilog_membank_config_module(fp, cur_sram_orgz_info); + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Close the file stream */ + fp.close(); + + /* Add fname to the linked list when debugging is finished */ + /* TODO: uncomment this when it is ready to be plugged-in + submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h index 88877b9e0..8f4a52816 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h @@ -21,4 +21,9 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, const std::string& verilog_dir, const std::string& submodule_dir); +void print_verilog_config_peripherals(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& submodule_dir); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 980ecc2ba..2ff74da87 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3224,6 +3224,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, /* 5. Dump decoder modules only when memory bank is required */ dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir); + print_verilog_config_peripherals(module_manager, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir)); /* 6. Dump template for all the modules */ if (TRUE == fpga_verilog_opts.print_user_defined_template) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 882906a43..816d75b68 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -1182,7 +1182,6 @@ void dump_verilog_mux_sram_one_local_outport(FILE* fp, return; } - /* Always dump the output ports of a SRAM */ void dump_verilog_sram_one_local_outport(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, From 29e80d157ccf85be07262d170adf88ccfe1282ec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 21:27:47 -0600 Subject: [PATCH 198/482] Start developing BitstreamContext --- .../vpr/SRC/fpga_x2p/base/bitstream_context.h | 31 +++++++++++++++++++ .../SRC/fpga_x2p/base/bitstream_context_fwd.h | 18 +++++++++++ 2 files changed, 49 insertions(+) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h new file mode 100644 index 000000000..6ee011182 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * This file introduces a data structure to store bitstream-related information + ******************************************************************************/ +#ifndef BITSTREAM_CONTEXT_H +#define BITSTREAM_CONTEXT_H + +#include "vtr_vector.h" +#include "bitstream_context_fwd.h" + +class BitstreamContext { + private: /* Internal data */ + enum e_sram_orgz config_scheme_; /* The type of configuration protocol */ + CircuitModelId& sram_model_; /* The memory circuit model used by the Bitstream generation */ + size_t num_memory_bits_; /* Number of memory bits */ + size_t num_bls_; /* Number of Bit Lines */ + size_t num_wls_; /* Number of Word Lines */ + + size_t num_reserved_bls_; /* Number of reserved Bit Lines, ONLY applicable to RRAM-based FPGA */ + size_t num_reserved_wls_; /* Number of reserved Word Lines, ONLY applicable to RRAM-based FPGA */ + /* Unique id of a bit in the Bitstream */ + vtr::vector bit_ids_; + /* Bit line address of a bit in the Bitream: ONLY applicable to memory-decoders */ + vtr::vector bl_addr_; + /* Word line address of a bit in the Bitream: ONLY applicable to memory-decoders */ + vtr::vector wl_addr_; + /* value of a bit in the Bitream */ + vtr::vector bit_val_; +}; + +#endif + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h new file mode 100644 index 000000000..29d85580e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h @@ -0,0 +1,18 @@ +/************************************************** + * This file includes only declarations for + * the data structures for module managers + * Please refer to module_manager.h for more details + *************************************************/ +#ifndef MODULE_MANAGER_FWD_H +#define MODULE_MANAGER_FWD_H + +#include "vtr_strong_id.h" + +/* Strong Ids for ModuleManager */ +struct config_bit_id_tag; + +typedef vtr::StrongId ConfigBitId; + +class BitstreamContext; + +#endif From f69ce708cae3ad3525075e7b2251b63545cb18c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 13 Sep 2019 21:59:52 -0600 Subject: [PATCH 199/482] rework on the order of top-level functions --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 28 ++++++++++++++++--- .../verilog/verilog_include_netlists.c | 3 ++ .../SRC/fpga_x2p/verilog/verilog_submodules.c | 6 +--- 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 19c80b25e..80d4df095 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -40,6 +40,8 @@ #include "verilog_global.h" #include "verilog_utils.h" #include "verilog_submodules.h" +#include "verilog_decoder.h" +#include "verilog_decoders.h" #include "verilog_pbtypes.h" #include "verilog_routing.h" #include "verilog_compact_netlist.h" @@ -266,6 +268,17 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, dump_verilog_simulation_preproc(src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + /* Generate primitive Verilog modules, which are corner stones of FPGA fabric + * Note that this function MUST be called before Verilog generation of + * core logic (i.e., logic blocks and routing resources) !!! + * This is because that this function will add the primitive Verilog modules to + * the module manager. + * Without the modules in the module manager, core logic generation is not possible!!! + */ + dump_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, + Arch, &vpr_setup.RoutingArch, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + /* Dump routing resources: switch blocks, connection blocks and channel tracks */ dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, @@ -280,10 +293,17 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, lb_dir_path, &Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); - /* Dump internal structures of submodules */ - dump_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, submodule_dir_path, - Arch, &vpr_setup.RoutingArch, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + /* Generate the Verilog module of the configuration peripheral protocol + * which loads bitstream to FPGA fabric + * + * IMPORTANT: this function should be called after Verilog generation of + * core logic (i.e., logic blocks and routing resources) !!! + * This is due to the configuration protocol requires the total + * number of memory cells across the FPGA fabric + */ + print_verilog_config_peripherals(module_manager, sram_verilog_orgz_info, std::string(src_dir_path), std::string(submodule_dir_path)); + /* TODO: This is the old function, which will be deprecated when refactoring is done */ + dump_verilog_config_peripherals(sram_verilog_orgz_info, src_dir_path, submodule_dir_path); /* Dump top-level verilog */ dump_compact_verilog_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c index dba96bb84..72b250231 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c @@ -113,6 +113,9 @@ void write_include_netlists (char* src_dir_formatted, fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, default_submodule_dir_name, submodule_verilog_file_name); + fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, + default_submodule_dir_name, + config_peripheral_verilog_file_name); init_include_user_defined_verilog_netlists(spice); include_netlists_include_user_defined_verilog_netlists(fp, spice); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 2ff74da87..93230b695 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3222,11 +3222,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); - /* 5. Dump decoder modules only when memory bank is required */ - dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir); - print_verilog_config_peripherals(module_manager, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir)); - - /* 6. Dump template for all the modules */ + /* 5. Dump template for all the modules */ if (TRUE == fpga_verilog_opts.print_user_defined_template) { print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); } From a6e592247ecb0a98d7d54bd62803170f863aa5f8 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 13 Sep 2019 22:50:20 -0600 Subject: [PATCH 200/482] Replaced options exit_on fail and show_thread logs --- openfpga_flow/scripts/run_fpga_task.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 06a5358fb..c6a7b5b94 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -53,9 +53,9 @@ parser.add_argument('--test_run', action="store_true", help="Dummy run shows final generated VPR commands") parser.add_argument('--debug', action="store_true", help="Run script in debug mode") -parser.add_argument('--exit_on_fail', action="store_true", +parser.add_argument('--continue_on_fail', action="store_true", help="Exit script with return code") -parser.add_argument('--skip_thread_logs', action="store_true", +parser.add_argument('--show_thread_logs', action="store_true", help="Skips logs from running thread") args = parser.parse_args() @@ -365,7 +365,7 @@ def run_single_script(s, eachJob, job_list): stderr=subprocess.STDOUT, universal_newlines=True) for line in process.stdout: - if not args.skip_thread_logs: + if args.show_thread_logs: strip_child_logger_info(line[:-1]) sys.stdout.buffer.flush() output.write(line) @@ -376,7 +376,7 @@ def run_single_script(s, eachJob, job_list): except: logger.exception("Failed to execute openfpga flow - " + eachJob["name"]) - if args.exit_on_fail: + if not args.continue_on_fail: clean_up_and_exit("Faile to run task %s exiting" % name) eachJob["endtime"] = time.time() timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) From bd9e57bc372f96aa0a330c7d68d5b96297db6e00 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 13 Sep 2019 23:30:42 -0600 Subject: [PATCH 201/482] Added better task name --- openfpga_flow/scripts/run_fpga_task.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index c6a7b5b94..590408f87 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -36,7 +36,7 @@ if sys.version_info[0] < 3: # Configure logging system # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = logging.basicConfig(level=logging.INFO, stream=sys.stdout, - format='%(levelname)s (%(threadName)10s) - %(message)s') + format='%(levelname)s (%(threadName)15s) - %(message)s') logger = logging.getLogger('OpenFPGA_Task_logs') @@ -392,11 +392,9 @@ def run_single_script(s, eachJob, job_list): def run_actions(job_list): thread_sema = threading.Semaphore(args.maxthreads) thred_list = [] - for index, eachjob in enumerate(job_list): - JobID = 'Job_%02d' % (index+1) - logger.info("Running %s = %s" % (JobID, eachjob["name"])) + for _ , eachjob in enumerate(job_list): t = threading.Thread(target=run_single_script, - name=JobID, args=(thread_sema, eachjob, job_list)) + name=eachjob["name"], args=(thread_sema, eachjob, job_list)) t.start() thred_list.append(t) for eachthread in thred_list: From 10eba0f78cd03d41961a874c0209254a457ecbfd Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 13 Sep 2019 23:31:23 -0600 Subject: [PATCH 202/482] Updated script.sh with new paramters --- .travis/script.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index 10cf00931..0de111068 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --exit_on_fail +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow end_section "OpenFPGA.TaskTun" From e5c99c8b1207ea276d6903c05be2bff7deaff90f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 13 Sep 2019 23:56:38 -0600 Subject: [PATCH 203/482] Quick terminate on fail added --- openfpga_flow/scripts/run_fpga_task.py | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 590408f87..9120505b6 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -252,7 +252,7 @@ def generate_each_task_actions(taskname): flow_run_cmd_list.append({ "arch": arch, "bench": bench, - "name": "%02d_arch%s_%s" % (indx, bench["top_module"], lbl), + "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, "commands": command, "finished" : False, @@ -345,14 +345,11 @@ def strip_child_logger_info(line): def run_single_script(s, eachJob, job_list): - logger.debug('Added job in pool') with s: - logger.debug("Running OpenFPGA flow with " + - " ".join(eachJob["commands"])) - name = threading.currentThread().getName() + thread_name = threading.currentThread().getName() eachJob["starttime"] = time.time() try: - logfile = "%s_out.log" % name + logfile = "%s_out.log" % thread_name with open(logfile, 'w+') as output: output.write("* "*20 + '\n') output.write("RunDirectory : %s\n" % os.getcwd()) @@ -360,6 +357,7 @@ def run_single_script(s, eachJob, job_list): eachJob["commands"] output.write(" ".join(command) + '\n') output.write("* "*20 + '\n') + logger.debug("Running OpenFPGA flow with [%s]" % command) process = subprocess.Popen(command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, @@ -371,19 +369,19 @@ def run_single_script(s, eachJob, job_list): output.write(line) process.wait() if process.returncode: - raise subprocess.CalledProcessError(0, command) + raise subprocess.CalledProcessError(0, " ".join(command)) eachJob["status"] = True except: logger.exception("Failed to execute openfpga flow - " + eachJob["name"]) if not args.continue_on_fail: - clean_up_and_exit("Faile to run task %s exiting" % name) + os._exit(1) eachJob["endtime"] = time.time() timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \ else str(timediff) logger.info("%s Finished with returncode %d, Time Taken %s " % - (name, process.returncode, timestr)) + (thread_name, process.returncode, timestr)) eachJob["finished"] = True no_of_finished_job = sum([ not eachJ["finished"] for eachJ in job_list]) logger.info("***** %d runs pending *****" % (no_of_finished_job)) @@ -391,13 +389,13 @@ def run_single_script(s, eachJob, job_list): def run_actions(job_list): thread_sema = threading.Semaphore(args.maxthreads) - thred_list = [] + thread_list = [] for _ , eachjob in enumerate(job_list): - t = threading.Thread(target=run_single_script, - name=eachjob["name"], args=(thread_sema, eachjob, job_list)) + t = threading.Thread(target=run_single_script, name=eachjob["name"], + args=(thread_sema, eachjob, job_list)) t.start() - thred_list.append(t) - for eachthread in thred_list: + thread_list.append(t) + for eachthread in thread_list: eachthread.join() From 81b9c5b2665615405f8bdd7b2103239737d7f4e9 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 14 Sep 2019 12:35:47 -0600 Subject: [PATCH 204/482] Added flag for VVP exit code --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index fcd1d1721..e1cec5bb8 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -853,7 +853,7 @@ def run_netlists_verification(): command += [tb_top_autochecked] run_command("iverilog_verification", "iverilog_output.txt", command) - vvp_command = ["vvp", compiled_file] + vvp_command = ["vvp", "-Ns", compiled_file] output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) if "Succeed" in output: logger.info("VVP Simulation Successful") From d5ebe66ad933ad33be218a33c0c4490394d2d8c5 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 16 Sep 2019 10:57:52 -0600 Subject: [PATCH 205/482] Bug fix --- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 14 +++++++++++++- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 6 ++---- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index d687a1468..5dd8025e2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2473,7 +2473,7 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordina /* Give a coordinator of a rr switch block, and return its unique mirror */ const RRGSB DeviceRRGSB::get_sb_unique_module(DeviceCoordinator& coordinator) const { - assert(validate_coordinator(coordinator)); + assert(validate_coordinator_edge(coordinator)); size_t sb_unique_module_id = sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()]; return get_sb_unique_module(sb_unique_module_id); } @@ -3072,6 +3072,18 @@ bool DeviceRRGSB::validate_coordinator(DeviceCoordinator& coordinator) const { return true; } +/* Validate if the (x,y) is the range of this device, but takes into consideration that edges are 1 off */ +bool DeviceRRGSB::validate_coordinator_edge(DeviceCoordinator& coordinator) const { + if (coordinator.get_x() >= rr_gsb_.capacity() + 1) { + return false; + } + if (coordinator.get_y() >= rr_gsb_[coordinator.get_x()].capacity() + 1) { + return false; + } + return true; +} + + /* Validate if the index in the range of unique_mirror vector*/ bool DeviceRRGSB::validate_side(enum e_side side) const { Side side_manager(side); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index 6dd2437fb..54348046a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -371,6 +371,7 @@ class DeviceRRGSB { void clear_segment_ids(); private: /* Validators */ bool validate_coordinator(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ + bool validate_coordinator_edge(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device but takes into consideration the fact that edges are 1 off */ bool validate_side(enum e_side side) const; /* validate if side is in the range of unique_side_module_ */ bool validate_sb_unique_module_index(size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ bool validate_cb_unique_module_index(t_rr_type cb_type, size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index f343b8c69..1c69aef44 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2329,8 +2329,6 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ - puts("CHECK4"); - const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(port_coordinator); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { fprintf(fp, " "); dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ @@ -2338,8 +2336,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, - unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } From d83cad7c2e3940d6b3d8eb2bebd56aff056571e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 16 Sep 2019 17:35:51 -0600 Subject: [PATCH 206/482] refactoring Verilog generation for routing channels --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 61 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 16 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 7 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 477 +++++++++++++++++- .../SRC/fpga_x2p/verilog/verilog_routing.h | 26 +- 5 files changed, 559 insertions(+), 28 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 6f559432d..295ba2227 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -138,3 +138,64 @@ std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, const std::string& postfix) { return std::string( circuit_lib.model_name(circuit_model) + "_" + circuit_lib.model_name(sram_model) + postfix ); } + +/********************************************************************* + * Generate the netlist name for a unique routing block + * It could be + * 1. Routing channel + * 2. Connection block + * 3. Switch block + * A unique block id should be given + *********************************************************************/ +std::string generate_routing_block_netlist_name(const std::string& prefix, + const size_t& block_id, + const std::string& postfix) { + return std::string( prefix + std::to_string(block_id) + postfix ); +} + +/********************************************************************* + * Generate the netlist name for a routing block with a given coordinate + * It could be + * 1. Routing channel + * 2. Connection block + * 3. Switch block + *********************************************************************/ +std::string generate_routing_block_netlist_name(const std::string& prefix, + const vtr::Point& coordinate, + const std::string& postfix) { + return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix ); +} + +/********************************************************************* + * Generate the module name for a unique routing channel + *********************************************************************/ +std::string generate_routing_channel_module_name(const t_rr_type& chan_type, + const size_t& block_id) { + /* Channel must be either CHANX or CHANY */ + VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); + + /* Create a map between chan_type and module_prefix */ + std::map module_prefix_map; + /* TODO: use a constexpr string to replace the fixed name? */ + module_prefix_map[CHANX] = std::string("chanx"); + module_prefix_map[CHANY] = std::string("chany"); + + return std::string( module_prefix_map[chan_type] + std::string("_") + std::to_string(block_id) + std::string("_") ); +} + +/********************************************************************* + * Generate the module name for a routing channel with a given coordinate + *********************************************************************/ +std::string generate_routing_channel_module_name(const t_rr_type& chan_type, + const vtr::Point& coordinate) { + /* Channel must be either CHANX or CHANY */ + VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); + + /* Create a map between chan_type and module_prefix */ + std::map module_prefix_map; + /* TODO: use a constexpr string to replace the fixed name? */ + module_prefix_map[CHANX] = std::string("chanx"); + module_prefix_map[CHANY] = std::string("chany"); + + return std::string( module_prefix_map[chan_type] + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + std::string("_") ); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index dbf6abff5..a3abf4440 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -9,7 +9,9 @@ #include +#include "vtr_geometry.h" #include "circuit_library.h" +#include "vpr_types.h" std::string generate_verilog_mux_node_name(const size_t& node_level, const bool& add_buffer_postfix); @@ -38,4 +40,18 @@ std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const std::string& postfix); +std::string generate_routing_block_netlist_name(const std::string& prefix, + const size_t& block_id, + const std::string& postfix); + +std::string generate_routing_block_netlist_name(const std::string& prefix, + const vtr::Point& block_id, + const std::string& postfix); + +std::string generate_routing_channel_module_name(const t_rr_type& chan_type, + const size_t& block_id); + +std::string generate_routing_channel_module_name(const t_rr_type& chan_type, + const vtr::Point& block_id); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 80d4df095..7f3540169 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -280,9 +280,9 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); /* Dump routing resources: switch blocks, connection blocks and channel tracks */ - dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch, - num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, - vpr_setup.FPGA_SPICE_Opts); + print_verilog_routing_resources(module_manager, sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch, + num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, + vpr_setup.FPGA_SPICE_Opts); /* Dump logic blocks * Branches to go: @@ -295,6 +295,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Generate the Verilog module of the configuration peripheral protocol * which loads bitstream to FPGA fabric + * TODO: generate the BL/WL decoders!!!! * * IMPORTANT: this function should be called after Verilog generation of * core logic (i.e., logic blocks and routing resources) !!! diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 76bf438d0..592b75d09 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1,7 +1,7 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ +/********************************************************************* + * This file includes functions that are used for + * Verilog generation of FPGA routing architecture (global routing) + *********************************************************************/ #include #include #include @@ -11,6 +11,7 @@ #include #include #include +#include #include /* Include vpr structs*/ @@ -24,6 +25,8 @@ #include "route_common.h" #include "vpr_utils.h" +#include "vtr_assert.h" + /* Include SPICE support headers*/ #include "linkedlist.h" #include "rr_blocks.h" @@ -34,12 +37,421 @@ #include "fpga_x2p_pbtypes_utils.h" #include "fpga_x2p_bitstream_utils.h" #include "fpga_x2p_globals.h" +#include "fpga_x2p_naming.h" /* Include Verilog support headers*/ #include "verilog_global.h" #include "verilog_utils.h" +#include "verilog_writer_utils.h" #include "verilog_routing.h" +/********************************************************************* + * Generate the Verilog module for a routing channel + * Routing track wire, which is 1-input and dual output + * This type of wires are used in the global routing architecture. + * One of the output is wired to another Switch block multiplexer, + * while the mid-output is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + * + * IMPORTANT: This function is designed for outputting unique Verilog modules + * of routing channels + * + * TODO: This function should be adapted to the RRGraph object + *********************************************************************/ +static +void print_verilog_routing_unique_chan_subckt(ModuleManager& module_manager, + const std::string& verilog_dir, + const std::string& subckt_dir, + const size_t& rr_chan_subckt_id, + const RRChan& rr_chan) { + std::string fname_prefix; + + /* TODO: use a constexpr String arrary to replace this switch cases? */ + /* Find the prefix for the Verilog file name */ + switch (rr_chan.get_type()) { + case CHANX: + fname_prefix = std::string(chanx_verilog_file_name_prefix); + break; + case CHANY: + fname_prefix = std::string(chany_verilog_file_name_prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, rr_chan_subckt_id, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id)); + + /* Add ports to the module */ + /* For the LEFT side of a X-direction routing channel + * or the BOTTOM bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are inputs of the module + * + * For the RIGHT side of a X-direction routing channel + * or the TOP bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are outputs of the module + * + * An example of X-direction routing channel consisting of W routing nodes: + * +--------------------------+ + * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) + * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) + * ... ... ... ... + * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) + * +--------------------------+ + * + * An example of Y-direction routing channel consisting of W routing nodes: + * + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + * ^ | ... | + * | v v + * +------------------------------ ... -------+ + * | out[0] in[1] in[X] | + * | | + * | | + * | in[0] out[1] ... out[X] | + * +------------------------------ ... -------+ + * ^ | | + * | v v + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + */ + /* Add ports at LEFT/BOTTOM side of the module */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id, itrack); + exit(1); + } + } + /* Add ports at RIGHT/TOP side of the module */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id, itrack); + exit(1); + } + } + /* Add middle-point output for connection box inputs */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* TODO: naming should be more flexible !!! */ + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Print short-wire connection: + * + * in[i] ----------> out[i] + * | + * +-----> mid_out[i] + */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* short connecting inputs and outputs: + * length of metal wire and parasitics are handled by semi-custom flow + */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + print_verilog_wire_connection(fp, output_port, input_port, false); + print_verilog_wire_connection(fp, mid_output_port, input_port, false); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* Uncomment this when it is ready + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} + +/********************************************************************* + * Generate the Verilog module for a routing channel + * Routing track wire, which is 1-input and dual output + * This type of wires are used in the global routing architecture. + * One of the output is wired to another Switch block multiplexer, + * while the mid-output is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + * + * IMPORTANT: This function is designed for outputting non-unique Verilog modules + * of routing channels + * + * TODO: This function should be adapted to the RRGraph object + *********************************************************************/ +static +void print_verilog_routing_chan_subckt(ModuleManager& module_manager, + const std::string& verilog_dir, + const std::string& subckt_dir, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + std::string fname_prefix; + + /* TODO: use a constexpr String arrary to replace this switch cases? */ + /* Find the prefix for the Verilog file name */ + switch (chan_type) { + case CHANX: + fname_prefix = std::string(chanx_verilog_file_name_prefix); + break; + case CHANY: + fname_prefix = std::string(chany_verilog_file_name_prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, chan_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(chan_type, chan_coordinate)); + + /* Collect rr_nodes for Tracks for chanx[ix][iy] */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, chan_coordinate.x(), chan_coordinate.y(), + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Add ports to the module */ + /* For the LEFT side of a X-direction routing channel + * or the BOTTOM bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are inputs of the module + * + * For the RIGHT side of a X-direction routing channel + * or the TOP bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are outputs of the module + * + * An example of X-direction routing channel consisting of W routing nodes: + * +--------------------------+ + * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) + * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) + * ... ... ... ... + * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) + * +--------------------------+ + * + * An example of Y-direction routing channel consisting of W routing nodes: + * + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + * ^ | ... | + * | v v + * +------------------------------ ... -------+ + * | out[0] in[1] in[X] | + * | | + * | | + * | in[0] out[1] ... out[X] | + * +------------------------------ ... -------+ + * ^ | | + * | v v + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + */ + /* Add ports at LEFT/BOTTOM side of the module */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + chan_coordinate.x(), chan_coordinate.y(), itrack); + exit(1); + } + } + /* Add ports at RIGHT/TOP side of the module */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + chan_coordinate.x(), chan_coordinate.y(), itrack); + exit(1); + } + } + /* Add middle-point output for connection box inputs */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + /* TODO: naming should be more flexible !!! */ + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Print short-wire connection: + * + * in[i] ----------> out[i] + * | + * +-----> mid_out[i] + */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + /* short connecting inputs and outputs: + * length of metal wire and parasitics are handled by semi-custom flow + */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + print_verilog_wire_connection(fp, output_port, input_port, false); + print_verilog_wire_connection(fp, mid_output_port, input_port, false); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* Uncomment this when it is ready + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + /* Free */ + my_free(chan_rr_nodes); + + return; +} + + static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, @@ -3894,18 +4306,33 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ return; } -/* Top Function*/ -/* Build the routing resource SPICE sub-circuits*/ -void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* subckt_dir, - t_arch arch, - t_det_routing_arch* routing_arch, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - t_rr_indexed_data* LL_rr_indexed_data, - t_fpga_spice_opts FPGA_SPICE_Opts) { - assert(UNI_DIRECTIONAL == routing_arch->directionality); +/********************************************************************* + * Top-level function: + * Build the Verilog modules for global routing architecture + * 1. Routing channels + * 2. Switch blocks + * 3. Connection blocks + * + * This function supports two styles in Verilog generation: + * 1. Explicit port mapping + * 2. Inexplicit port mapping + * + * This function also supports high hierarchical Verilog generation + * (when the compact_routing_hierarchy is set true) + * In this mode, Verilog generation will be done for only those + * unique modules in terms of internal logics + *********************************************************************/ +void print_verilog_routing_resources(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, /* To be replaced by RRGraph object */ + t_ivec*** LL_rr_node_indices, + t_rr_indexed_data* LL_rr_indexed_data, + const t_fpga_spice_opts& FPGA_SPICE_Opts) { + VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy; boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog; @@ -3934,12 +4361,18 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping); + + print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), + ichan, device_rr_chan.get_module(CHANX, ichan)); } /* Y - channels [1...ny][0..nx]*/ vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping); + + print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), + ichan, device_rr_chan.get_module(CHANY, ichan)); } } else { /* Output the full array of routing channels */ @@ -3949,6 +4382,12 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, arch.num_segments, explicit_port_mapping); + + vtr::Point chan_coordinate; + chan_coordinate.set_x(size_t(ix)); + chan_coordinate.set_y(size_t(iy)); + print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANX, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } } /* Y - channels [1...ny][0..nx]*/ @@ -3958,6 +4397,12 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, arch.num_segments, explicit_port_mapping); + + vtr::Point chan_coordinate; + chan_coordinate.set_x(size_t(ix)); + chan_coordinate.set_y(size_t(iy)); + print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANY, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index b126300e7..4ffe95d47 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -1,5 +1,12 @@ +/*********************************************** + * Header file for verilog_routing.cpp + **********************************************/ #ifndef VERILOG_ROUTING_H #define VERILOG_ROUTING_H + +/* Include other header files which are dependency on the function declared below */ +#include "module_manager.h" + void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, @@ -133,14 +140,15 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ bool is_explicit_mapping); -void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* subckt_dir, - t_arch arch, - t_det_routing_arch* routing_arch, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - t_rr_indexed_data* LL_rr_indexed_data, - t_fpga_spice_opts FPGA_SPICE_Opts); +void print_verilog_routing_resources(ModuleManager& module_manager, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + t_rr_indexed_data* LL_rr_indexed_data, + const t_fpga_spice_opts& FPGA_SPICE_Opts); #endif From 0963852091b576c789cb1b768b3c5ca321fbd5af Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 16 Sep 2019 18:38:37 -0600 Subject: [PATCH 207/482] remove useless global ports for routing channel modules Need to rework the top-netlist generator before the new module generator can be plugged-in --- .../verilog/verilog_compact_netlist.c | 2 ++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 35 +++++++++---------- .../verilog/verilog_top_netlist_utils.c | 2 ++ 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 8fc306335..01b8ff8d4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -1092,9 +1092,11 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ + /* if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } + */ /* LEFT/BOTTOM side port of CHANX/CHANY */ /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 592b75d09..f547743c8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -456,8 +456,7 @@ static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, size_t rr_chan_subckt_id, - const RRChan& rr_chan, - bool is_explicit_mapping) { + const RRChan& rr_chan) { FILE* fp = NULL; char* fname = NULL; @@ -491,9 +490,11 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1)); fprintf(fp, "\n"); /* dump global ports */ + /* if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } + */ /* Inputs and outputs, * Rules for CHANX: * print left-hand ports(in) first, then right-hand ports(out) @@ -583,8 +584,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int num_segment, - bool is_explicit_mapping) { + int num_segment) { int itrack, iseg, cost_index; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -629,9 +629,11 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(chan_type, x, y)); fprintf(fp, "\n"); /* dump global ports */ + /* if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } + */ /* Inputs and outputs, * Rules for CHANX: * print left-hand ports(in) first, then right-hand ports(out) @@ -933,8 +935,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, enum e_side chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node, - bool is_explicit_mapping) { + t_rr_node* drive_rr_node) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -1393,7 +1394,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int cur_bl, cur_wl; t_spice_model* mem_model = NULL; char* mem_subckt_name = NULL; - int num_input_port, num_output_port, num_sram_port; + int num_input_port, num_output_port; /* Check the file handler*/ if (NULL == fp) { @@ -1879,13 +1880,11 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node, - is_explicit_mapping); + num_drive_rr_nodes, cur_rr_node); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], - is_explicit_mapping); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, @@ -3194,10 +3193,10 @@ void dump_verilog_connection_box_short_interc(FILE* fp, /* SRC rr_node is the IPIN of a grid.*/ +static void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node, - bool is_explicit_mapping) { + t_rr_node* src_rr_node) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, side, index; @@ -3803,7 +3802,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node, is_explicit_mapping); + dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, @@ -4360,7 +4359,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, /* X - channels [1...nx][0..ny]*/ for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping); + ichan, device_rr_chan.get_module(CHANX, ichan)); print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), ichan, device_rr_chan.get_module(CHANX, ichan)); @@ -4369,7 +4368,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping); + ichan, device_rr_chan.get_module(CHANY, ichan)); print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), ichan, device_rr_chan.get_module(CHANY, ichan)); @@ -4381,7 +4380,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, for (int ix = 1; ix < (nx + 1); ix++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments, explicit_port_mapping); + arch.num_segments); vtr::Point chan_coordinate; chan_coordinate.set_x(size_t(ix)); @@ -4396,7 +4395,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, for (int iy = 1; iy < (ny + 1); iy++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments, explicit_port_mapping); + arch.num_segments); vtr::Point chan_coordinate; chan_coordinate.set_x(size_t(ix)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index fc8e5a206..58cf4aefe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -482,9 +482,11 @@ void dump_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ + /* if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } + */ /* LEFT/BOTTOM side port of CHANX/CHANY */ /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt From c5ee81541a6dd6ab24822a2d9597a56664130d81 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 16 Sep 2019 18:47:01 -0600 Subject: [PATCH 208/482] remove dead codes in routing module generation --- .../SRC/fpga_x2p/verilog/verilog_routing.c | 508 ------------------ 1 file changed, 508 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index f547743c8..d6f3bed34 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2121,514 +2121,6 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } - -/* Dump port list of a subckt describing a side of a switch block - * Only output ports will be printed on the specified side - * Only input ports will be printed on the other sides - */ -static -void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, - const RRGSB& rr_sb, - enum e_side sb_side, - size_t seg_id, - boolean dump_port_type, - bool is_explicit_mapping) { - /* Check file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid file handler!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Create a side manager */ - Side sb_side_manager(sb_side); - - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { - Side side_manager(side); - /* Print ports */ - fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str()); - DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - switch (rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - /* if this is the specified side, we only consider output ports */ - if (sb_side_manager.get_side() != side_manager.get_side()) { - break; - } - /* Bypass unwanted segments */ - if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { - continue; - } - fprintf(fp, " "); - if (TRUE == dump_port_type) { - fprintf(fp, "output "); - is_explicit_mapping = false; /* Both cannot be true together */ - } - if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - } - fprintf(fp, "%s", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } - fprintf(fp, ",\n"); - break; - case IN_PORT: - /* if this is not the specified side, we only consider input ports */ - if (sb_side_manager.get_side() == side_manager.get_side()) { - break; - } - fprintf(fp, " "); - if (TRUE == dump_port_type) { - fprintf(fp, "input "); - } - if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - } - fprintf(fp, "%s", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } - fprintf(fp, ",\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack); - exit(1); - } - } - - /* Dump OPINs of adjacent CLBs */ - for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - fprintf(fp, " "); - dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ - rr_sb.get_opin_node(side_manager.get_side(), inode)->ptc_num, - rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ - if (FALSE == dump_port_type) { - fprintf(fp, ",\n"); - } - } - } - - return; -} - - -/* Task: Print the subckt of a side of a Switch Box. - * For TOP side: - * 1. Channel Y [x][y+1] inputs - * 2. Grid[x][y+1] Right side outputs pins - * 3. Grid[x+1][y+1] Left side output pins - * For RIGHT side: - * 1. Channel X [x+1][y] inputs - * 2. Grid[x+1][y+1] Bottom side output pins - * 3. Grid[x+1][y] Top side output pins - * For BOTTOM side: - * 1. Channel Y [x][y] outputs - * 2. Grid[x][y] Right side output pins - * 3. Grid[x+1][y] Left side output pins - * For LEFT side: - * 1. Channel X [x][y] outputs - * 2. Grid[x][y] Top side output pins - * 3. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ -static -void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, char* subckt_dir, - size_t module_id, size_t seg_id, - const RRGSB& rr_sb, enum e_side side, - bool is_explicit_mapping) { - FILE* fp = NULL; - char* fname = NULL; - Side side_manager(side); - - /* Get the channel width on this side, if it is zero, we return */ - if (0 == rr_sb.get_chan_width(side)) { - return; - } - - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - int esti_sram_cnt = cur_num_sram + num_conf_bits; - - /* Create file name */ - std::string fname_prefix(sb_verilog_file_name_prefix); - fname_prefix += side_manager.c_str(); - - std::string file_description("Unique module for Switch Block side: "); - file_description += side_manager.c_str(); - file_description += "seg"; - file_description += std::to_string(seg_id); - - /* Create file handler */ - fp = verilog_create_one_subckt_file(subckt_dir, file_description.c_str(), - fname_prefix.c_str(), module_id, seg_id, &fname); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Comment lines */ - fprintf(fp, - "//----- Verilog Module of Unique Switch Box[%lu][%lu] at Side %s, Segment id: %lu -----\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str(), seg_id); - /* Print the definition of subckt*/ - fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { - fprintf(fp, ",\n"); - } - - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, - seg_id, TRUE, - false); - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - 0, - num_reserved_conf_bits - 1, - VERILOG_PORT_INPUT); - if (0 < num_reserved_conf_bits) { - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1, - VERILOG_PORT_INPUT); - - /* Dump ports only visible during formal verification*/ - if (0 < num_conf_bits) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1, - VERILOG_PORT_INPUT, false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1); - - /* Put down all the multiplexers */ - fprintf(fp, "//----- %s side Multiplexers -----\n", - side_manager.c_str()); - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) - ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - /* Bypass unwanted segments */ - if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { - continue; - } - dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, - side_manager.get_side(), - itrack, is_explicit_mapping); - } - } - - fprintf(fp, "endmodule\n"); - - /* Comment lines */ - fprintf(fp, - "//----- END Verilog Module of Switch Box[%lu][%lu] Side %s -----\n\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str()); - - /* Check */ - assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); - - /* Close file handler */ - fclose(fp); - - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - - /* Free chan_rr_nodes */ - my_free(fname); - - return; -} - -/* Task: Print the subckt of a Switch Box. - * Call the four submodules dumped in function: unique_side_module - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ -static -void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb, - bool is_explicit_mapping) { - FILE* fp = NULL; - char* fname = NULL; - - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits); - rr_gsb.set_sb_conf_bits_lsb(cur_num_sram); - rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1); - - /* Create file handler */ - fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ", - sb_verilog_file_name_prefix, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), &fname); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Comment lines */ - fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - /* Print the definition of subckt*/ - fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { - fprintf(fp, ",\n"); - } - - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - /* Print ports */ - fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.c_str()); - DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - fprintf(fp, " output %s,\n", - gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); - break; - case IN_PORT: - fprintf(fp, " input %s,\n", - gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack); - exit(1); - } - } - /* Dump OPINs of adjacent CLBs */ - fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.c_str()); - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - fprintf(fp, " "); - dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ - } - } - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - fprintf(fp, "//----- Reserved SRAM Ports -----\n"); - if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) { - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_reserved_conf_bits_lsb(), - rr_gsb.get_sb_reserved_conf_bits_msb(), - VERILOG_PORT_INPUT); - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - fprintf(fp, "//----- Regular SRAM Ports -----\n"); - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT); - - /* Dump ports only visible during formal verification*/ - if (0 < rr_gsb.get_sb_num_conf_bits()) { - fprintf(fp, "\n"); - fprintf(fp, "//----- SRAM Ports for formal verification -----\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, - false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb()); - - /* Call submodules */ - int cur_sram_lsb = cur_num_sram; - int cur_sram_msb = cur_num_sram; - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - fprintf(fp, "//----- %s side Submodule -----\n", - side_manager.c_str()); - - /* Get the channel width on this side, if it is zero, we return */ - if (0 == rr_gsb.get_chan_width(side_manager.get_side())) { - fprintf(fp, "//----- %s side has zero channel width, module dump skipped -----\n", - side_manager.c_str()); - continue; - } - - /* get segment ids */ - std::vector seg_ids = rr_gsb.get_chan(side_manager.get_side()).get_segment_ids(); - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - fprintf(fp, "//----- %s side Submodule with Segment id: %lu -----\n", - side_manager.c_str(), seg_ids[iseg]); - - /* Count the number of configuration bits to be consumed by this Switch block */ - int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); - - /* Cache the sram counter */ - cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1; - - /* Instanciate the subckt*/ - fprintf(fp, - "%s %s ( \n", - rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]), - rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg])); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { - fprintf(fp, ",\n"); - } - - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping); - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - 0, - side_num_reserved_conf_bits - 1, - VERILOG_PORT_CONKT); - if (0 < side_num_reserved_conf_bits) { - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, - cur_sram_lsb, - cur_sram_msb, - VERILOG_PORT_CONKT, is_explicit_mapping); - - /* Dump ports only visible during formal verification*/ - if (0 < side_num_conf_bits) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - cur_sram_lsb, - cur_sram_msb, - VERILOG_PORT_CONKT, is_explicit_mapping); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Update sram_lsb */ - cur_sram_lsb = cur_sram_msb + 1; - } - } - /* checker */ - assert(cur_sram_msb == cur_num_sram + num_conf_bits - 1); - - fprintf(fp, "endmodule\n"); - - /* Comment lines */ - fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - - /* Close file handler */ - fclose(fp); - - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - - /* Free chan_rr_nodes */ - my_free(fname); - - return; -} - - - /* Task: Print the subckt of a Switch Box. * A Switch Box subckt consists of following ports: * 1. Channel Y [x][y] inputs From 2294aecef2f7839b8a384e595c5abcb6239d2cb8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 16 Sep 2019 20:19:14 -0600 Subject: [PATCH 209/482] remove old codes and compact new codes --- .../SRC/fpga_x2p/verilog/verilog_routing.c | 21 ++----------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index d6f3bed34..8b314501e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -3874,9 +3874,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, arch.num_segments); - vtr::Point chan_coordinate; - chan_coordinate.set_x(size_t(ix)); - chan_coordinate.set_y(size_t(iy)); + vtr::Point chan_coordinate((size_t)ix, (size_t)iy); print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } @@ -3889,9 +3887,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, arch.num_segments); - vtr::Point chan_coordinate; - chan_coordinate.set_x(size_t(ix)); - chan_coordinate.set_y(size_t(iy)); + vtr::Point chan_coordinate((size_t)ix, (size_t)iy); print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } @@ -3903,19 +3899,6 @@ void print_verilog_routing_resources(ModuleManager& module_manager, /* Create a snapshot on sram_orgz_info */ t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); - /* Output unique side modules - for (size_t side = 0; side < device_rr_gsb.get_max_num_sides(); ++side) { - Side side_manager(side); - for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) { - for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) { - const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg); - size_t seg_id = device_rr_gsb.get_segment_id(iseg); - dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping); - } - } - } - */ - /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); From 5abbfd6a0fa95537afa4f3a2064256b8a132928f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 16 Sep 2019 20:45:02 -0600 Subject: [PATCH 210/482] add tileable routing to regression test --- ...k6_N10_sram_chain_HC_tileable_template.xml | 4 +- .../tasks/tileable_routing/config/task.conf | 57 +++++++++++++++++++ 2 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/tasks/tileable_routing/config/task.conf diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml index 57967f2e9..ce1615d0b 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml @@ -558,7 +558,7 @@ - + | |<---- bottom_pins + * | | + * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] + * inputs/outputs<--->| |<---> inputs/outputs + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * top_pins---->| |<---- top_pins + * | | + * +-----------------------------------------------+ + * ^ ^ ^ + * | | | + * | v | + * Grid[x][y] ChanY[x][y] Grid[x+1][y] + * right_pins inputs/outputs left_pins + * + * + ********************************************************************/ +static +void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + const RRGSB& rr_sb, + const bool& is_explicit_mapping) { + /* TODO: move this part to another function where we count the conf bits for all the switch blocks !!!*/ + /* Count the number of configuration bits to be consumed by this Switch block */ + int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb); + /* Estimate the sram_verilog_model->cnt */ + int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + int esti_sram_cnt = cur_num_sram + num_conf_bits; + RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ + rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits); + rr_gsb.set_sb_conf_bits_lsb(cur_num_sram); + rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1); + + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); + + /* Add ports to the module */ + /* Global ports: + * In the circuit_library, find all the circuit models that may be included in the Switch Block + * Collect the global ports from the circuit_models and merge with the same name + */ + std::vector global_ports = find_switch_block_global_ports(rr_gsb, circuit_lib, rr_switches); + for (const auto& port : global_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add routing channel ports at each side of the GSB */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); + + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); + std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + + switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + case OUT_PORT: + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + case IN_PORT: + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack); + exit(1); + } + } + /* Dump OPINs of adjacent CLBs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + std::string port_name = generate_grid_side_port_name(port_coord, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); + BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + } + } + + /* Add configuration ports */ + /* TODO: Reserved sram ports */ + /* + if (0 < rr_sb.get_sb_num_reserved_conf_bits()) { + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + rr_gsb.get_sb_reserved_conf_bits_lsb(), + rr_gsb.get_sb_reserved_conf_bits_msb(), + VERILOG_PORT_INPUT); + fprintf(fp, ",\n"); + } + */ + /* TODO: Normal sram ports */ + /* + dump_verilog_sram_ports(fp, cur_sram_orgz_info, + rr_gsb.get_sb_conf_bits_lsb(), + rr_gsb.get_sb_conf_bits_msb(), + VERILOG_PORT_INPUT); + */ + /* Dump ports only visible during formal verification*/ + /* + if (0 < rr_sb.get_sb_num_conf_bits()) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + rr_gsb.get_sb_conf_bits_lsb(), + rr_gsb.get_sb_conf_bits_msb(), + VERILOG_PORT_INPUT, is_explicit_mapping); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, "); \n"); + */ + + /* TODO: Local wires for memory configurations */ + /* + dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, + rr_gsb.get_sb_conf_bits_lsb(), + rr_gsb.get_sb_conf_bits_msb()); + */ + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} + /* Task: Print the subckt of a Switch Box. * A Switch Box subckt consists of following ports: * 1. Channel Y [x][y] inputs @@ -3797,6 +4010,24 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ return; } +/********************************************************************* + * Generate the port name for a Grid + *********************************************************************/ +std::string generate_grid_side_port_name(const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id) { + /* Output the pins on the side*/ + int height = get_grid_pin_height(coordinate.x(), coordinate.y(), (int)pin_id); + if (1 != grid[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", + __FILE__, __LINE__, + coordinate.x(), coordinate.y(), height, convert_side_index_to_string(side), pin_id); + exit(1); + } + return generate_grid_port_name(coordinate, (size_t)height, side, pin_id, true); +} + /********************************************************************* * Top-level function: * Build the Verilog modules for global routing architecture @@ -3814,6 +4045,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ * unique modules in terms of internal logics *********************************************************************/ void print_verilog_routing_resources(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, @@ -3827,6 +4059,13 @@ void print_verilog_routing_resources(ModuleManager& module_manager, boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy; boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog; + + /* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */ + std::vector rr_switches; + for (short i = 0; i < routing_arch.num_switch; ++i) { + rr_switches.push_back(switch_inf[i]); + } + /* Two major tasks: * 1. Generate sub-circuits for Routing Channels * 2. Generate sub-circuits for Switch Boxes @@ -3902,12 +4141,15 @@ void print_verilog_routing_resources(ModuleManager& module_manager, /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); - /* - dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, - subckt_dir, unique_mirror, explicit_port_mapping); - */ dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, explicit_port_mapping); + /* + print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib, + rr_switches, + cur_sram_orgz_info, std::string(verilog_dir), + std::string(subckt_dir), unique_mirror, + explicit_port_mapping); + */ } /* Restore sram_orgz_info to the base */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 4ffe95d47..11bcdf070 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -5,6 +5,7 @@ #define VERILOG_ROUTING_H /* Include other header files which are dependency on the function declared below */ +#include "mux_library.h" #include "module_manager.h" void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, @@ -140,7 +141,12 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ bool is_explicit_mapping); +std::string generate_grid_side_port_name(const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id); + void print_verilog_routing_resources(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, From 169732ccc1dace6357d61a2831aaa6283ccdd593 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 17 Sep 2019 22:09:37 -0600 Subject: [PATCH 213/482] Added verbose option in VVP output --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index a4ae24e18..9cb187b94 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -854,7 +854,7 @@ def run_netlists_verification(): command += [tb_top_autochecked] run_command("iverilog_verification", "iverilog_output.txt", command) - vvp_command = ["vvp", "-Ns", compiled_file] + vvp_command = ["vvp", "-Nvs", compiled_file] output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) if "Succeed" in output: logger.info("VVP Simulation Successful") From cd5fd6ce6c548de696bf2c4ac8e47741e6ded8a9 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 18 Sep 2019 12:14:26 -0600 Subject: [PATCH 214/482] Added explicit checking to VVP execution --- openfpga_flow/scripts/run_fpga_flow.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 9cb187b94..6a203e302 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -854,12 +854,14 @@ def run_netlists_verification(): command += [tb_top_autochecked] run_command("iverilog_verification", "iverilog_output.txt", command) - vvp_command = ["vvp", "-Nvs", compiled_file] + vvp_command = ["vvp", compiled_file] output = run_command("vvp_verification", "vvp_sim_output.txt", vvp_command) if "Succeed" in output: logger.info("VVP Simulation Successful") else: - logger.info(str(output).split("\n")[-1]) + logger.error(str(output).split("\n")[-1]) + if exit_if_fail: + clean_up_and_exit("Failed to run VVP verification") ExecTime["VerificationEnd"] = time.time() From 0f0d06aad7397ef7f9f92c6d37fb81717b32d318 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Sep 2019 15:04:51 -0600 Subject: [PATCH 215/482] add non-LUT intermediate buffer to test and apply minor bug fix --- ...C_non_lut_intermediate_buffer_template.xml | 1040 ++++++++++++++++ ...k6_N10_sram_chain_HC_tree_mux_template.xml | 1042 +++++++++++++++++ .../k8_N10_sram_chain_FC_template.xml | 34 +- .../tasks/blif_vpr_flow/config/task.conf | 12 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 3 +- 5 files changed, 2111 insertions(+), 20 deletions(-) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml new file mode 100644 index 000000000..ff9d23ac1 --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml @@ -0,0 +1,1040 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml new file mode 100644 index 000000000..c362da80c --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml @@ -0,0 +1,1042 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml index 25577a130..4ff2c0800 100644 --- a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml +++ b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml @@ -202,11 +202,23 @@ + + 10e-12 + + + 10e-12 + + + 10e-12 + + + 10e-12 + @@ -217,10 +229,10 @@ - 10e-12 0e-12 0e-12 + 10e-12 5e-12 5e-12 - 10e-12 0e-12 0e-12 + 10e-12 5e-12 5e-12 @@ -230,17 +242,11 @@ - - 10e-12 + + 10e-12 10e-12 - - 10e-12 - - - 10e-12 - - - 10e-12 + + 10e-12 10e-12 @@ -325,7 +331,7 @@ - + @@ -340,7 +346,7 @@ - + diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index d796d6c8a..f6c4498d2 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -17,9 +17,11 @@ fpga_flow=vpr_blif [ARCHITECTURES] # arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml -arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml -arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +#arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml +#arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif @@ -42,7 +44,7 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_x2p_compact_routing_hierarchy= +#vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= @@ -58,5 +60,5 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_x2p_compact_routing_hierarchy= +#vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 93230b695..f122dbdba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -726,7 +726,8 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, for (i = 0; i < spice_mux_arch.num_level + 1; i++) { inter_buf_loc[i] = FALSE; } - if (NULL != spice_model.lut_intermediate_buffer->location_map) { + if ( (TRUE == spice_model.lut_intermediate_buffer->exist) + && (NULL != spice_model.lut_intermediate_buffer->location_map) ) { assert ((size_t)spice_mux_arch.num_level - 1 == strlen(spice_model.lut_intermediate_buffer->location_map)); /* For intermediate buffers */ for (i = 0; i < spice_mux_arch.num_level - 1; i++) { From e0b253d30a34caee5f6767245b236711b50e7c51 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Sep 2019 15:15:03 -0600 Subject: [PATCH 216/482] minor fix for non-LUT intermedate buffer case --- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 3fafb1998..800b65198 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -177,9 +177,15 @@ std::vector build_mux_intermediate_buffer_location_map(const CircuitLibrar std::string location_map_str; /* ONLY for LUTs: intermediate buffers may exist if specified */ - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + if (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) { + return location_map; + } + + /* Get location map when the flag of intermediate buffer is on */ + if (true == circuit_lib.is_lut_intermediate_buffered(circuit_model)) { location_map_str = circuit_lib.lut_intermediate_buffer_location_map(circuit_model); } + /* If no location map is specified, we can return here */ if (location_map_str.empty()) { return location_map; From 4e7af5cdc538934898fec86673bafec2ae38f163 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Sep 2019 15:59:32 -0600 Subject: [PATCH 217/482] update tileable_routing test --- openfpga_flow/tasks/tileable_routing/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/tileable_routing/config/task.conf b/openfpga_flow/tasks/tileable_routing/config/task.conf index 78aa53cb0..3a7f092a6 100644 --- a/openfpga_flow/tasks/tileable_routing/config/task.conf +++ b/openfpga_flow/tasks/tileable_routing/config/task.conf @@ -38,7 +38,7 @@ vpr_fpga_verilog_print_user_defined_template= #vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= #[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 0ff0c8cf06c7b7af4db6ea309bd1ad56746452d6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 19 Sep 2019 15:43:25 -0600 Subject: [PATCH 218/482] bug fix for IO=1 --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 01b8ff8d4..9538bbcf2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -653,7 +653,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, } /* Dump ports only visible during formal verification*/ - if (0 < (cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1 + if (0 < (cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy])) { fprintf(fp, "\n"); fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); From cc0bfdd548ee97a2a042cbcd676fd7b43b3c9566 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 20 Sep 2019 10:27:26 -0600 Subject: [PATCH 219/482] Add testcase in regression test for architecture with 1 IO cell/IO block --- .../k6_N10_sram_chain_HC_1IO_template.xml | 1042 +++++++++++++++++ .../tasks/blif_vpr_flow/config/task.conf | 1 + 2 files changed, 1043 insertions(+) create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml new file mode 100644 index 000000000..fa32d4e41 --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml @@ -0,0 +1,1042 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index f6c4498d2..2a85f22cf 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -20,6 +20,7 @@ arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml #arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml #arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml From 50039a4b6e10aa64ce7b6eb3d61b6290ac2e77a2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 21 Sep 2019 23:35:56 -0600 Subject: [PATCH 220/482] Added remove run directory option --- openfpga_flow/scripts/run_fpga_task.py | 52 ++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 9120505b6..a46c99e79 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -5,7 +5,7 @@ # Combination of architecture, benchmark and script paramters # Args : python3 run_fpga_task.py --help # Author : Ganesh Gore -#Email : ganeshgore@utah.edu +# Email : ganeshgore@utah.edu # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = import os @@ -48,6 +48,11 @@ parser.add_argument('tasks', nargs='+') parser.add_argument('--maxthreads', type=int, default=2, help="Number of fpga_flow threads to run default = 2," + "Typically <= Number of processors on the system") +parser.add_argument('--remove_run_dir', type=str, + help="Remove run dir " + + "'all' to remove all." + + ", to remove specific run dir" + + "- To remove range of directory") parser.add_argument('--config', help="Override default configuration") parser.add_argument('--test_run', action="store_true", help="Dummy run shows final generated VPR commands") @@ -84,6 +89,8 @@ def main(): logger.info("Currently running task %s" % eachtask) eachtask = eachtask.replace("\\", "/").split("/") job_run_list = generate_each_task_actions(eachtask) + if args.remove_run_dir: + continue eachtask = "_".join(eachtask) if not args.test_run: run_actions(job_run_list) @@ -111,6 +118,40 @@ def validate_command_line_arguments(): logger.info("Set up to run %d Parallel threads", args.maxthreads) +def remove_run_dir(): + remove_dir = [] + try: + argval = args.remove_run_dir.lower() + if argval == "all": + for eachRun in glob.glob("run*"): + remove_dir += [eachRun] + elif "-" in argval: + minval, maxval = map(int, argval.split("-")) + if minval > maxval: + raise Exception("Enter valid range to remove") + for eachRun in glob.glob("run*"): + if minval <= int(eachRun[-3:]) <= maxval: + remove_dir += [eachRun] + elif "," in argval: + for eachRun in argval.split(","): + remove_dir += ["run%03d" % int(eachRun)] + else: + logger.error("Unknow argument to --remove_run_dir") + except: + logger.exception("Failed to parse remove rund_dir options") + + try: + for eachdir in remove_dir: + logger.info('Removing run_dir %s' % (eachdir)) + if os.path.exists('latest'): + if eachdir == os.readlink('latest'): + remove_dir += ["latest"] + shutil.rmtree(eachdir, ignore_errors=True) + except: + logger.exception("Failed to remove %s run directory" % + (eachdir or "Unknown")) + + def generate_each_task_actions(taskname): """ This script generates all the scripts required for each benchmark @@ -130,6 +171,9 @@ def generate_each_task_actions(taskname): # Create run directory for current task run ./runxxx run_dirs = [int(os.path.basename(x)[-3:]) for x in glob.glob('run*[0-9]')] curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1) + if args.remove_run_dir: + remove_run_dir() + return try: os.mkdir(curr_run_dir) if os.path.islink('latest') or os.path.exists('latest'): @@ -255,7 +299,7 @@ def generate_each_task_actions(taskname): "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, "commands": command, - "finished" : False, + "finished": False, "status": False}) logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' % @@ -383,14 +427,14 @@ def run_single_script(s, eachJob, job_list): logger.info("%s Finished with returncode %d, Time Taken %s " % (thread_name, process.returncode, timestr)) eachJob["finished"] = True - no_of_finished_job = sum([ not eachJ["finished"] for eachJ in job_list]) + no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list]) logger.info("***** %d runs pending *****" % (no_of_finished_job)) def run_actions(job_list): thread_sema = threading.Semaphore(args.maxthreads) thread_list = [] - for _ , eachjob in enumerate(job_list): + for _, eachjob in enumerate(job_list): t = threading.Thread(target=run_single_script, name=eachjob["name"], args=(thread_sema, eachjob, job_list)) t.start() From 5efea159c5bf2c4f09a9d2656b152596a61d735a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Sep 2019 11:14:33 -0600 Subject: [PATCH 221/482] Simplify part of regression test to min_route_chan_width --- .../tasks/blif_vpr_flow/config/task.conf | 29 +++++++++---------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index f6c4498d2..4ffabc5d7 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -32,21 +32,20 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_mode bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v bench0_chan_width = 300 -[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -fix_route_chan_width=300 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +##vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] min_route_chan_width=1.3 From 1e4177067df0ed02a76ebce7b97b1a882f809f1a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Sep 2019 11:21:43 -0600 Subject: [PATCH 222/482] remove port size in the module definition --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index ca832260b..377d34b3d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -105,8 +105,8 @@ void print_verilog_module_definition(std::fstream& fp, std::string port_whitespace(module_head_line.length(), ' '); fp << port_whitespace; } - /* Print port */ - fp << generate_verilog_port(kv.second, port); + /* Print port: only the port name is enough */ + fp << port.get_name(); port_cnt++; } } From 2c4372c506ab755bad348fd25cdefab7c7e37c3b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Sep 2019 12:16:43 -0600 Subject: [PATCH 223/482] add reserved BLB/WL port naming --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 20 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 2 ++ .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 2 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 21 +++++++++++-------- 4 files changed, 35 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 4c9bc85a2..3d9f52eb5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -282,3 +282,23 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, port_name += "_"; return port_name; } + + +/********************************************************************* + * Generate the port name for a reserved sram port, i.e., BLB/WL port + * When port_type is BLB, a string denoting to the reserved BLB port is generated + * When port_type is WL, a string denoting to the reserved WL port is generated + * + * DO NOT put any SRAM organization check codes HERE!!! + * Even though the reserved BLB/WL ports are used by RRAM-based FPGA only, + * try to keep this function does simple job. + * Check codes should be added outside, when print the ports to files!!! + *********************************************************************/ +std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type) { + VTR_ASSERT( (port_type == SPICE_MODEL_PORT_BLB) || (port_type == SPICE_MODEL_PORT_WL) ); + + if (SPICE_MODEL_PORT_BLB == port_type) { + return std::string("reserved_blb"); + } + return std::string("reserved_wl"); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index caad2c253..2cf4acb4f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -67,4 +67,6 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& pin_id, const bool& for_top_netlist); +std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index 28d133424..4965cf482 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -36,7 +36,7 @@ std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, /* Get the model, and try to add to the sub_model list */ CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model; /* Make sure it is a valid id */ - VTR_ASSERT( CircuitModelId::INVALID() == switch_circuit_model ); + VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model ); /* Get the model, and try to add to the sub_model list */ if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) { /* Not yet in the list, add it */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 8e59eb561..8a24fd155 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2279,15 +2279,20 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage /* Add configuration ports */ /* TODO: Reserved sram ports */ - /* if (0 < rr_sb.get_sb_num_reserved_conf_bits()) { - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_reserved_conf_bits_lsb(), - rr_gsb.get_sb_reserved_conf_bits_msb(), - VERILOG_PORT_INPUT); - fprintf(fp, ",\n"); + /* Check: this SRAM organization type must be memory-bank ! */ + VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); + + /* Add a reserved BLB port to the module */ + std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB); + BasicPort blb_module_port(blb_port_name, rr_gsb.get_sb_num_reserved_conf_bits()); + module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT); + + /* Add a reserved BLB port to the module */ + std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL); + BasicPort wl_module_port(wl_port_name, rr_gsb.get_sb_num_reserved_conf_bits()); + module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT); } - */ /* TODO: Normal sram ports */ /* dump_verilog_sram_ports(fp, cur_sram_orgz_info, @@ -4143,13 +4148,11 @@ void print_verilog_routing_resources(ModuleManager& module_manager, const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, explicit_port_mapping); - /* print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib, rr_switches, cur_sram_orgz_info, std::string(verilog_dir), std::string(subckt_dir), unique_mirror, explicit_port_mapping); - */ } /* Restore sram_orgz_info to the base */ From 8b3de892ef6bc2374fc87084c552e48e8861e1c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Sep 2019 12:18:44 -0600 Subject: [PATCH 224/482] simplify the regression test commands --- .travis/script.sh | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index abdd81b35..fa9e95ea8 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,6 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow -python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2 end_section "OpenFPGA.TaskTun" From d2ddbc19a3fea90ab6c8ca7b7372c9623300dcf7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Sep 2019 16:38:16 -0600 Subject: [PATCH 225/482] refactoring the reserved sram port generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 5 ++- .../fpga_x2p/base/module_manager_utils.cpp | 35 +++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 6 ++++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 21 ++++++----- 4 files changed, 53 insertions(+), 14 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 3d9f52eb5..6323e0ff4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -1,7 +1,6 @@ /******************************************************************** - * This file includes functions to - * generate module/port names for Verilog - * and SPICE netlists + * This file includes functions to generate module/port names for + * Verilog and SPICE netlists * * IMPORTANT: keep all the naming functions in this file to be * generic for both Verilog and SPICE generators diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 7faf4a054..585ab57ec 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -12,6 +12,9 @@ #include "circuit_library.h" #include "module_manager.h" + +#include "fpga_x2p_naming.h" + #include "module_manager_utils.h" /****************************************************************************** @@ -72,3 +75,35 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, return add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model, circuit_lib.model_name(circuit_model)); } +/******************************************************************** + * Add a list of ports that are used for reserved SRAM ports to a module + * in the module manager + * The reserved SRAM ports are mainly designed for RRAM-based FPGA, + * which are shared across modules. + * Note that different modules may require different size of reserved + * SRAM ports but their LSB must all start from 0 + * +---------+ + * reserved_sram_port[0:X] --->| ModuleA | + * +---------+ + * + * +---------+ + * reserved_sram_port[0:Y] --->| ModuleB | + * +---------+ + * + ********************************************************************/ +void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + const size_t& port_size) { + /* Add a reserved BLB port to the module */ + std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB); + BasicPort blb_module_port(blb_port_name, port_size); + /* Add generated ports to the ModuleManager */ + module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT); + + /* Add a reserved BLB port to the module */ + std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL); + BasicPort wl_module_port(wl_port_name, port_size); + /* Add generated ports to the ModuleManager */ + module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index c117b5a6c..796eccf69 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -7,6 +7,8 @@ #define MODULE_MANAGER_UTILS_H /* Include other header files which are dependency on the function declared below */ +#include +#include "device_port.h" #include "circuit_library.h" #include "module_manager.h" @@ -17,5 +19,9 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); +void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + const size_t& port_size); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 8a24fd155..e8600168c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -39,6 +39,8 @@ #include "fpga_x2p_bitstream_utils.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_naming.h" +#include "module_manager.h" +#include "module_manager_utils.h" /* Include Verilog support headers*/ #include "verilog_global.h" @@ -2278,20 +2280,13 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage } /* Add configuration ports */ - /* TODO: Reserved sram ports */ + /* Reserved sram ports */ if (0 < rr_sb.get_sb_num_reserved_conf_bits()) { /* Check: this SRAM organization type must be memory-bank ! */ VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); - - /* Add a reserved BLB port to the module */ - std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB); - BasicPort blb_module_port(blb_port_name, rr_gsb.get_sb_num_reserved_conf_bits()); - module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT); - - /* Add a reserved BLB port to the module */ - std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL); - BasicPort wl_module_port(wl_port_name, rr_gsb.get_sb_num_reserved_conf_bits()); - module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT); + /* Generate a list of ports */ + add_reserved_sram_ports_to_module_manager(module_manager, module_id, + rr_gsb.get_sb_num_reserved_conf_bits()); } /* TODO: Normal sram ports */ /* @@ -2316,6 +2311,10 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage fprintf(fp, "); \n"); */ + /* Print module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish printing ports */ + /* TODO: Local wires for memory configurations */ /* dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, From e1742b68ef278288996ab1ff006affc270d3dd68 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 23 Sep 2019 20:25:53 -0600 Subject: [PATCH 226/482] add pre-processing flag support for module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 18 +++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 5 ++ .../fpga_x2p/verilog/verilog_writer_utils.cpp | 67 +++++++++++++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 5 ++ 4 files changed, 95 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 8743b2ebb..67557bc95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -106,6 +106,13 @@ bool ModuleManager::port_is_register(const ModuleId& module, const ModulePortId& return port_is_register_[module][port]; } +/* Return the pre-processing flag of a port */ +std::string ModuleManager::port_preproc_flag(const ModuleId& module, const ModulePortId& port) const { + /* validate both module id and port id*/ + VTR_ASSERT(valid_module_port_id(module, port)); + return port_preproc_flags_[module][port]; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ @@ -131,6 +138,7 @@ ModuleId ModuleManager::add_module(const std::string& name) { ports_.emplace_back(); port_types_.emplace_back(); port_is_register_.emplace_back(); + port_preproc_flags_.emplace_back(); /* Register in the name-to-id map */ name_id_map_[name] = module; @@ -155,6 +163,7 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, ports_[module].push_back(port_info); port_types_[module].push_back(port_type); port_is_register_[module].push_back(false); + port_preproc_flags_[module].emplace_back(); /* Create an empty string for the pre-processing flags */ /* Update fast look-up for port */ port_lookup_[module][port_type].push_back(port); @@ -178,6 +187,15 @@ void ModuleManager::set_port_is_register(const ModuleId& module, const std::stri port_is_register_[module][port] = is_register; } +/* Set the preprocessing flag for a port */ +void ModuleManager::set_port_preproc_flag(const ModuleId& module, const std::string& port_name, const std::string& preproc_flag) { + /* Find the port */ + ModulePortId port = find_module_port(module, port_name); + /* Must find something, otherwise drop an error */ + VTR_ASSERT(ModulePortId::INVALID() != port); + port_preproc_flags_[module][port] = preproc_flag; +} + /* Add a child module to a parent module */ void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module) { /* Validate the id of both parent and child modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 5a9fcd507..038ca0010 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -48,6 +48,8 @@ class ModuleManager { size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const; /* Find if a port is register */ bool port_is_register(const ModuleId& module, const ModulePortId& port) const; + /* Return the pre-processing flag of a port */ + std::string port_preproc_flag(const ModuleId& module, const ModulePortId& port) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); @@ -58,6 +60,8 @@ class ModuleManager { void set_module_name(const ModuleId& module, const std::string& name); /* Set a port to be a register */ void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register); + /* Set the preprocessing flag for a port */ + void set_port_preproc_flag(const ModuleId& module, const std::string& port_name, const std::string& preproc_flag); /* Add a child module to a parent module */ void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); private: /* Private validators/invalidators */ @@ -76,6 +80,7 @@ class ModuleManager { vtr::vector> ports_; /* List of ports for each Module */ vtr::vector> port_types_; /* Type of ports */ vtr::vector> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: reg */ + vtr::vector> port_preproc_flags_; /* If a port is available only when a pre-processing flag is enabled. This is to record the pre-processing flags */ /* fast look-up for module */ std::map name_id_map_; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 377d34b3d..bd13fbeaf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -70,6 +70,25 @@ void print_verilog_comment(std::fstream& fp, fp << "// " << comment << std::endl; } +/************************************************ + * Print the declaration of a Verilog preprocessing flag + ***********************************************/ +void print_verilog_preprocessing_flag(std::fstream& fp, + const std::string& preproc_flag) { + check_file_handler(fp); + + fp << "`ifdef " << preproc_flag << std::endl; +} + +/************************************************ + * Print the endif of a Verilog preprocessing flag + ***********************************************/ +void print_verilog_endif(std::fstream& fp) { + check_file_handler(fp); + + fp << "endif" << std::endl; +} + /************************************************ * Print a Verilog module definition * We use the following format: @@ -100,6 +119,18 @@ void print_verilog_module_definition(std::fstream& fp, /* Do not dump a comma for the first port */ fp << "," << std::endl; } + + ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); + VTR_ASSERT(ModulePortId::INVALID() != port_id); + /* Print pre-processing flag for a port, if defined */ + std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); + if (false == preproc_flag.empty()) { + /* Start a new line because an ifdef line will be outputted */ + fp << std::endl; + /* Print an ifdef Verilog syntax */ + print_verilog_preprocessing_flag(fp, preproc_flag); + } + /* Create a space for "module " except the first line! */ if (0 != port_cnt) { std::string port_whitespace(module_head_line.length(), ' '); @@ -107,6 +138,15 @@ void print_verilog_module_definition(std::fstream& fp, } /* Print port: only the port name is enough */ fp << port.get_name(); + + if (false == preproc_flag.empty()) { + /* Start a new line because an endif line will be outputted */ + fp << std::endl; + /* Print an endif to pair the ifdef */ + print_verilog_endif(fp); + } + + /* Increase the counter */ port_cnt++; } } @@ -131,10 +171,24 @@ void print_verilog_module_ports(std::fstream& fp, /* Port sequence: global, inout, input, output and clock ports, */ for (const auto& kv : port_type2type_map) { for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { + ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); + VTR_ASSERT(ModulePortId::INVALID() != port_id); + /* Print pre-processing flag for a port, if defined */ + std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); + if (false == preproc_flag.empty()) { + /* Print an ifdef Verilog syntax */ + print_verilog_preprocessing_flag(fp, preproc_flag); + } + /* Print port */ fp << "//----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; fp << generate_verilog_port(kv.second, port); fp << ";" << std::endl; + + if (false == preproc_flag.empty()) { + /* Print an endif to pair the ifdef */ + print_verilog_endif(fp); + } } } @@ -149,9 +203,22 @@ void print_verilog_module_ports(std::fstream& fp, if (false == module_manager.port_is_register(module_id, port_id)) { continue; } + + /* Print pre-processing flag for a port, if defined */ + std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); + if (false == preproc_flag.empty()) { + /* Print an ifdef Verilog syntax */ + print_verilog_preprocessing_flag(fp, preproc_flag); + } + /* Print port */ fp << generate_verilog_port(VERILOG_PORT_REG, port); fp << ";" << std::endl; + + if (false == preproc_flag.empty()) { + /* Print an endif to pair the ifdef */ + print_verilog_endif(fp); + } } } fp << "//----- END Registered ports -----" << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index a3d8e7206..8ab7906e0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -26,6 +26,11 @@ void print_verilog_include_defines_preproc_file(std::fstream& fp, void print_verilog_comment(std::fstream& fp, const std::string& comment); +void print_verilog_preprocessing_flag(std::fstream& fp, + const std::string& preproc_flag); + +void print_verilog_endif(std::fstream& fp); + void print_verilog_module_definition(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id); From c911f15a6789d7709714359f4082eafcba9af22b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 23 Sep 2019 21:15:45 -0600 Subject: [PATCH 227/482] add formal verification port to SB Verilog generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 22 ++++++++++++++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 2 ++ .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 6 ++-- .../vpr/SRC/fpga_x2p/base/module_manager.h | 2 +- .../fpga_x2p/base/module_manager_utils.cpp | 20 +++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 7 +++++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 28 ++++++------------- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 21 +++++++------- 8 files changed, 73 insertions(+), 35 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 6323e0ff4..8884c3750 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -8,6 +8,7 @@ #include "vtr_assert.h" #include "sides.h" +#include "fpga_x2p_utils.h" #include "fpga_x2p_naming.h" /************************************************ @@ -228,7 +229,8 @@ std::string generate_routing_track_port_name(const t_rr_type& chan_type, port_name += std::string("in_"); break; default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", __FILE__, __LINE__); exit(1); } @@ -301,3 +303,21 @@ std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port } return std::string("reserved_wl"); } + +/********************************************************************* + * Generate the port name for a sram port, used for formal verification + * The port name is named after the cell name of SRAM in circuit library + * TODO: + * Use the new refactored data structure to replace the sram_orgz_info + *********************************************************************/ +std::string generate_formal_verification_sram_port_name(t_sram_orgz_info* cur_sram_orgz_info) { + /* Get memory_model */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); + VTR_ASSERT(NULL != mem_model); /* We must have a valid memory model */ + + std::string port_name = std::string(mem_model->name) + std::string("_out_fm"); + + return port_name; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 2cf4acb4f..ed49595d0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -69,4 +69,6 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type); +std::string generate_formal_verification_sram_port_name(t_sram_orgz_info* cur_sram_orgz_info); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 67557bc95..2a89a748c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -188,11 +188,9 @@ void ModuleManager::set_port_is_register(const ModuleId& module, const std::stri } /* Set the preprocessing flag for a port */ -void ModuleManager::set_port_preproc_flag(const ModuleId& module, const std::string& port_name, const std::string& preproc_flag) { - /* Find the port */ - ModulePortId port = find_module_port(module, port_name); +void ModuleManager::set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag) { /* Must find something, otherwise drop an error */ - VTR_ASSERT(ModulePortId::INVALID() != port); + VTR_ASSERT(valid_module_port_id(module, port)); port_preproc_flags_[module][port] = preproc_flag; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 038ca0010..8befd9be9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -61,7 +61,7 @@ class ModuleManager { /* Set a port to be a register */ void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register); /* Set the preprocessing flag for a port */ - void set_port_preproc_flag(const ModuleId& module, const std::string& port_name, const std::string& preproc_flag); + void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); /* Add a child module to a parent module */ void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); private: /* Private validators/invalidators */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 585ab57ec..da37f3a4b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -107,3 +107,23 @@ void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT); } +/******************************************************************** + * Add a list of ports that are used for formal verification to a module + * in the module manager + * + * The formal verification port will appear only when a pre-processing flag is defined + * This function will add the pre-processing flag along with the port + ********************************************************************/ +void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& preproc_flag, + const size_t& port_size) { + /* Create a port */ + std::string port_name = generate_formal_verification_sram_port_name(cur_sram_orgz_info); + BasicPort module_port(port_name, port_size); + /* Add generated ports to the ModuleManager */ + ModulePortId port_id = module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Add pre-processing flag if defined */ + module_manager.set_port_preproc_flag(module_id, port_id, preproc_flag); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 796eccf69..2fa5e98bf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -9,6 +9,7 @@ /* Include other header files which are dependency on the function declared below */ #include #include "device_port.h" +#include "spice_types.h" #include "circuit_library.h" #include "module_manager.h" @@ -23,5 +24,11 @@ void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, const ModuleId& module_id, const size_t& port_size); +void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& preproc_flag, + const size_t& port_size); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index e8600168c..a411f08f1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2204,11 +2204,10 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb); /* Estimate the sram_verilog_model->cnt */ int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - int esti_sram_cnt = cur_num_sram + num_conf_bits; RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits); - rr_gsb.set_sb_conf_bits_lsb(cur_num_sram); - rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1); + rr_gsb.set_sb_num_reserved_conf_bits(size_t(num_reserved_conf_bits)); + rr_gsb.set_sb_conf_bits_lsb(size_t(cur_num_sram)); + rr_gsb.set_sb_conf_bits_msb(size_t(cur_num_sram + num_conf_bits - 1)); /* Create the netlist */ vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); @@ -2281,7 +2280,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage /* Add configuration ports */ /* Reserved sram ports */ - if (0 < rr_sb.get_sb_num_reserved_conf_bits()) { + if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) { /* Check: this SRAM organization type must be memory-bank ! */ VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); /* Generate a list of ports */ @@ -2295,21 +2294,12 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage rr_gsb.get_sb_conf_bits_msb(), VERILOG_PORT_INPUT); */ - /* Dump ports only visible during formal verification*/ - /* - if (0 < rr_sb.get_sb_num_conf_bits()) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, is_explicit_mapping); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); + /* Add ports only visible during formal verification to the module */ + if (0 < rr_gsb.get_sb_num_conf_bits()) { + add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, cur_sram_orgz_info, + std::string(verilog_formal_verification_preproc_flag), + rr_gsb.get_sb_num_conf_bits()); } - fprintf(fp, "); \n"); - */ /* Print module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index bd13fbeaf..ce504a143 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -86,7 +86,7 @@ void print_verilog_preprocessing_flag(std::fstream& fp, void print_verilog_endif(std::fstream& fp) { check_file_handler(fp); - fp << "endif" << std::endl; + fp << "`endif" << std::endl; } /************************************************ @@ -113,6 +113,7 @@ void print_verilog_module_definition(std::fstream& fp, /* Port sequence: global, inout, input, output and clock ports, */ size_t port_cnt = 0; + bool printed_ifdef = false; /* A flag to tell if an ifdef has been printed for the last port */ for (const auto& kv : port_type2type_map) { for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { if (0 != port_cnt) { @@ -120,15 +121,22 @@ void print_verilog_module_definition(std::fstream& fp, fp << "," << std::endl; } + if (true == printed_ifdef) { + /* Print an endif to pair the ifdef */ + print_verilog_endif(fp); + /* Reset the flag */ + printed_ifdef = false; + } + ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); VTR_ASSERT(ModulePortId::INVALID() != port_id); /* Print pre-processing flag for a port, if defined */ std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); if (false == preproc_flag.empty()) { - /* Start a new line because an ifdef line will be outputted */ - fp << std::endl; /* Print an ifdef Verilog syntax */ print_verilog_preprocessing_flag(fp, preproc_flag); + /* Raise the flag */ + printed_ifdef = true; } /* Create a space for "module " except the first line! */ @@ -139,13 +147,6 @@ void print_verilog_module_definition(std::fstream& fp, /* Print port: only the port name is enough */ fp << port.get_name(); - if (false == preproc_flag.empty()) { - /* Start a new line because an endif line will be outputted */ - fp << std::endl; - /* Print an endif to pair the ifdef */ - print_verilog_endif(fp); - } - /* Increase the counter */ port_cnt++; } From 2b0e2615faae5e6a2a54963ad2e2ab12753c538a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 25 Sep 2019 16:09:58 -0600 Subject: [PATCH 228/482] refactored sram port addition to module manager --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 90 +++++++++++++++++-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 8 +- .../fpga_x2p/base/module_manager_utils.cpp | 85 +++++++++++++++++- .../SRC/fpga_x2p/base/module_manager_utils.h | 11 ++- .../SRC/fpga_x2p/verilog/verilog_routing.c | 21 +++-- 5 files changed, 194 insertions(+), 21 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 8884c3750..db19f59f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -308,16 +308,90 @@ std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port * Generate the port name for a sram port, used for formal verification * The port name is named after the cell name of SRAM in circuit library * TODO: - * Use the new refactored data structure to replace the sram_orgz_info + * Use the new refactored data structure to replace the t_sram_orgz_info *********************************************************************/ -std::string generate_formal_verification_sram_port_name(t_sram_orgz_info* cur_sram_orgz_info) { - /* Get memory_model */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - VTR_ASSERT(NULL != mem_model); /* We must have a valid memory model */ - - std::string port_name = std::string(mem_model->name) + std::string("_out_fm"); +std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model) { + std::string port_name = circuit_lib.model_name(sram_model) + std::string("_out_fm"); return port_name; } +/********************************************************************* + * Generate the port name for a regular sram port + * The port name is named after the cell name of SRAM in circuit library + * TODO: + * Use the new refactored data structure to replace the t_sram_orgz_info + *********************************************************************/ +std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_port_type& port_type) { + /* Get memory_model */ + + std::string port_name = circuit_lib.model_name(sram_model) + std::string("_"); + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: { + /* Two types of ports are available: + * (1) Regular output of a SRAM, enabled by port type of INPUT + * (2) Inverted output of a SRAM, enabled by port type of OUTPUT + */ + if (SPICE_MODEL_PORT_INPUT == port_type) { + port_name += std::string("out"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); + port_name += std::string("outb"); + } + break; + } + case SPICE_SRAM_SCAN_CHAIN: + /* Two types of ports are available: + * (1) Head of a chain of Scan-chain Flip-Flops (SCFFs), enabled by port type of INPUT + * (2) Tail of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of OUTPUT + * +------+ +------+ +------+ + * Head --->| SCFF |--->| SCFF |--->| SCFF |---> Tail + * +------+ +------+ +------+ + */ + if (SPICE_MODEL_PORT_INPUT == port_type) { + port_name += std::string("scff_head"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); + port_name += std::string("scff_tail"); + } + break; + case SPICE_SRAM_MEMORY_BANK: + /* Four types of ports are available: + * (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL + * (2) Word Lines (WLs) of a SRAM cell, enabled by port type of WL + * (3) Inverted Bit Lines (BLBs) of a SRAM cell, enabled by port type of BLB + * (4) Inverted Word Lines (WLBs) of a SRAM cell, enabled by port type of WLB + * + * BL BLB WL WLB BL BLB WL WLB BL BLB WL WLB + * [0] [0] [0] [0] [1] [1] [1] [1] [i] [i] [i] [i] + * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + * | | | | | | | | | | | | + * +----------+ +----------+ +----------+ + * | SRAM | | SRAM | ... | SRAM | + * +----------+ +----------+ +----------+ + */ + if (SPICE_MODEL_PORT_BL == port_type) { + port_name += std::string("bl"); + } else if (SPICE_MODEL_PORT_WL == port_type) { + port_name += std::string("wl"); + } else if (SPICE_MODEL_PORT_BLB == port_type) { + port_name += std::string("blb"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_WLB == port_type ); + port_name += std::string("wlb"); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + return port_name; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index ed49595d0..732f47e5f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -69,6 +69,12 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type); -std::string generate_formal_verification_sram_port_name(t_sram_orgz_info* cur_sram_orgz_info); +std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model); + +std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_port_type& port_type); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index da37f3a4b..bc844ca7c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -116,14 +116,95 @@ void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, ********************************************************************/ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, const ModuleId& module_id, - t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, const std::string& preproc_flag, const size_t& port_size) { /* Create a port */ - std::string port_name = generate_formal_verification_sram_port_name(cur_sram_orgz_info); + std::string port_name = generate_formal_verification_sram_port_name(circuit_lib, sram_model); BasicPort module_port(port_name, port_size); /* Add generated ports to the ModuleManager */ ModulePortId port_id = module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); /* Add pre-processing flag if defined */ module_manager.set_port_preproc_flag(module_id, port_id, preproc_flag); } + +/******************************************************************** + * Add a list of ports that are used for SRAM configuration to a module + * in the module manager + * The type and names of added ports strongly depend on the + * organization of SRAMs. + * 1. Standalone SRAMs: + * two ports will be added, which are regular output and inverted output + * 2. Scan-chain Flip-flops: + * two ports will be added, which are the head of scan-chain + * and the tail of scan-chain + * 3. Memory decoders: + * 2-4 ports will be added, depending on the ports available in the SRAM + * Among these, two ports are mandatory: BL and WL + * The other two ports are optional: BLB and WLB + * Note that the constraints are correletated to the checking rules + * in check_circuit_library() + ********************************************************************/ +void add_sram_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, + const size_t& port_size) { + /* Prepare a list of port types to be added, the port type will be used to create port names */ + std::vector model_port_types; + /* Prepare a list of module port types to be added, the port type will be used to specify the port type in Verilog/SPICE module */ + std::vector module_port_types; + /* Actual port size may be different from user specification. Think about SCFF */ + size_t sram_port_size = port_size; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + model_port_types.push_back(SPICE_MODEL_PORT_INPUT); + module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); + model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); + module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); + break; + case SPICE_SRAM_SCAN_CHAIN: + model_port_types.push_back(SPICE_MODEL_PORT_INPUT); + module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); + model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); + module_port_types.push_back(ModuleManager::MODULE_OUTPUT_PORT); + /* SCFF head/tail are single-bit ports */ + sram_port_size = 1; + break; + case SPICE_SRAM_MEMORY_BANK: { + std::vector ports_to_search; + ports_to_search.push_back(SPICE_MODEL_PORT_BL); + ports_to_search.push_back(SPICE_MODEL_PORT_WL); + ports_to_search.push_back(SPICE_MODEL_PORT_BLB); + ports_to_search.push_back(SPICE_MODEL_PORT_WLB); + /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */ + for (const auto& port_to_search : ports_to_search) { + std::vector found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search); + if (0 == found_port.size()) { + continue; + } + model_port_types.push_back(port_to_search); + module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /* Add ports to the module manager */ + for (size_t iport = 0; iport < model_port_types.size(); ++iport) { + /* Create a port */ + std::string port_name = generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, model_port_types[iport]); + BasicPort module_port(port_name, sram_port_size); + /* Add generated ports to the ModuleManager */ + module_manager.add_port(module_id, module_port, module_port_types[iport]); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 2fa5e98bf..7ab8892c1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -26,9 +26,18 @@ void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, const ModuleId& module_id, - t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, const std::string& preproc_flag, const size_t& port_size); +void add_sram_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, + const size_t& port_size); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index a411f08f1..d9f135892 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2287,16 +2287,19 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage add_reserved_sram_ports_to_module_manager(module_manager, module_id, rr_gsb.get_sb_num_reserved_conf_bits()); } - /* TODO: Normal sram ports */ - /* - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT); - */ - /* Add ports only visible during formal verification to the module */ + /* Normal sram ports */ if (0 < rr_gsb.get_sb_num_conf_bits()) { - add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, cur_sram_orgz_info, + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + add_sram_ports_to_module_manager(module_manager, module_id, + circuit_lib, sram_model, cur_sram_orgz_info->type, + rr_gsb.get_sb_num_conf_bits()); + /* Add ports only visible during formal verification to the module */ + add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, + cur_sram_orgz_info->type, std::string(verilog_formal_verification_preproc_flag), rr_gsb.get_sb_num_conf_bits()); } From a35e2936b2fa6b4dbcf4dfa91e022052663bf320 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 25 Sep 2019 16:44:00 -0600 Subject: [PATCH 229/482] Fix verilog generation for direct connexion from directlist --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 3 +-- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 90690e48d..59d240102 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -548,7 +548,6 @@ void init_check_arch_spice_models(t_arch* arch, get_default_spice_model(SPICE_MODEL_WIRE, arch->spice->num_spice_model, arch->spice->spice_models); - continue; } else { arch->Directs[i].spice_model = find_name_matched_spice_model(arch->Directs[i].spice_model_name, @@ -562,7 +561,7 @@ void init_check_arch_spice_models(t_arch* arch, arch->Directs[i].spice_model_name, arch->Directs[i].name); exit(1); - } else if (SPICE_MODEL_CHAN_WIRE != arch->Directs[i].spice_model->type) { + } else if (SPICE_MODEL_WIRE != arch->Directs[i].spice_model->type) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model(%s) type of CLB to CLB Direct Connection (name=%s)! Should be chan_wire!\n", __FILE__ , __LINE__, arch->Directs[i].spice_model_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 58cf4aefe..8cd04d16e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -926,7 +926,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, exit(1); } - for (ipin = 0; ipin < cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index; ipin++) { + for (ipin = 0; ipin < 1 + cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index; ipin++) { /* Update pin index and get the side of the pins on grids */ cur_from_clb_pin_index = cur_direct->from_clb_pin_start_index + ipin; cur_to_clb_pin_index = cur_direct->to_clb_pin_start_index + ipin; @@ -950,7 +950,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, dump_verilog_toplevel_one_grid_side_pin_with_given_index(fp, IPIN, cur_to_clb_pin_index, cur_to_clb_pin_side, - to_grid_x, from_grid_y, + to_grid_x, to_grid_y, FALSE); fprintf(fp, ");\n"); From 5bb40e7f7420b13e37b2ff482cb99dfa1dc50826 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 25 Sep 2019 21:05:02 -0600 Subject: [PATCH 230/482] refactored local wire generation for Switch block --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 75 ++++++++++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 + .../fpga_x2p/base/link_arch_circuit_lib.cpp | 8 +- .../fpga_x2p/base/module_manager_utils.cpp | 2 + .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 30 ++++- .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.h | 2 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 47 +++++-- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 123 ++++++++++++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 6 + 9 files changed, 275 insertions(+), 23 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index db19f59f2..3bb812ae7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -307,8 +307,6 @@ std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port /********************************************************************* * Generate the port name for a sram port, used for formal verification * The port name is named after the cell name of SRAM in circuit library - * TODO: - * Use the new refactored data structure to replace the t_sram_orgz_info *********************************************************************/ std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model) { @@ -318,17 +316,14 @@ std::string generate_formal_verification_sram_port_name(const CircuitLibrary& ci } /********************************************************************* - * Generate the port name for a regular sram port + * Generate the port name for a regular sram port which appears in the + * port list of a module * The port name is named after the cell name of SRAM in circuit library - * TODO: - * Use the new refactored data structure to replace the t_sram_orgz_info *********************************************************************/ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_sram_orgz& sram_orgz_type, const e_spice_model_port_type& port_type) { - /* Get memory_model */ - std::string port_name = circuit_lib.model_name(sram_model) + std::string("_"); switch (sram_orgz_type) { @@ -395,3 +390,69 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, return port_name; } + +/********************************************************************* + * Generate the port name for a regular sram port which is an internal + * wire of a module + * The port name is named after the cell name of SRAM in circuit library + *********************************************************************/ +std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_port_type& port_type) { + std::string port_name = circuit_lib.model_name(sram_model) + std::string("_"); + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: { + /* Two types of ports are available: + * (1) Regular output of a SRAM, enabled by port type of INPUT + * (2) Inverted output of a SRAM, enabled by port type of OUTPUT + */ + if (SPICE_MODEL_PORT_INPUT == port_type) { + port_name += std::string("out_local_bus"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); + port_name += std::string("outb_local_bus"); + } + break; + } + case SPICE_SRAM_SCAN_CHAIN: + /* Three types of ports are available: + * (1) Input of Scan-chain Flip-Flops (SCFFs), enabled by port type of INPUT + * (2) Output of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of OUTPUT + * (2) Inverted output of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of INOUT + * +------+ +------+ +------+ + * Head --->| SCFF |--->| SCFF |--->| SCFF |---> Tail + * +------+ +------+ +------+ + */ + if (SPICE_MODEL_PORT_INPUT == port_type) { + port_name += std::string("scff_in_local_bus"); + } else if ( SPICE_MODEL_PORT_OUTPUT == port_type ) { + port_name += std::string("scff_out_local_bus"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_INOUT == port_type ); + port_name += std::string("scff_outb_local_bus"); + } + break; + case SPICE_SRAM_MEMORY_BANK: { + /* Two types of ports are available: + * (1) Regular output of a SRAM, enabled by port type of INPUT + * (2) Inverted output of a SRAM, enabled by port type of OUTPUT + */ + if (SPICE_MODEL_PORT_INPUT == port_type) { + port_name += std::string("out_local_bus"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); + port_name += std::string("outb_local_bus"); + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + return port_name; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 732f47e5f..bf78578d9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -77,4 +77,9 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type, const e_spice_model_port_type& port_type); +std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_port_type& port_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index 342524903..579ae9631 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -482,7 +482,7 @@ void link_circuit_library_to_arch(t_arch* arch, /* Check Circuit models first*/ VTR_ASSERT_SAFE( (NULL != arch) && (NULL != arch->spice) ); - /* 1. Link the spice model defined in pb_types and routing switches */ + /* 1. Link the circuit model defined in pb_types and routing switches */ /* Step A: Check routing switches, connection blocks*/ if (0 >= arch->num_cb_switch) { vpr_printf(TIO_MESSAGE_ERROR, @@ -500,7 +500,7 @@ void link_circuit_library_to_arch(t_arch* arch, __FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); exit(1); } - /* Check the spice model structure is matched with the structure in switch_inf */ + /* Check the circuit model structure is matched with the structure in switch_inf */ if (0 < check_circuit_model_structure_match_switch_inf(arch->cb_switches[i], arch->spice->circuit_lib)) { exit(1); } @@ -544,7 +544,7 @@ void link_circuit_library_to_arch(t_arch* arch, /* Step C: Find SRAM Model*/ link_sram_inf(&(arch->sram_inf), arch->spice->circuit_lib); - /* Step D: Find the segment spice_model*/ + /* Step D: Find the segment circuit_model*/ for (int i = 0; i < arch->num_segments; i++) { arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE); @@ -562,7 +562,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_directs; i++) { arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_WIRE); - /* Check SPICE model type */ + /* Check Circuit model type */ if (CircuitModelId::INVALID() == arch->Directs[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index bc844ca7c..2694a02a0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -140,6 +140,8 @@ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_ * 2. Scan-chain Flip-flops: * two ports will be added, which are the head of scan-chain * and the tail of scan-chain + * IMPORTANT: the port size will be forced to 1 in this case + * because the head and tail are both 1-bit ports!!! * 3. Memory decoders: * 2-4 ports will be added, depending on the ports available in the SRAM * Among these, two ports are mandatory: BL and WL diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index 4965cf482..a078ed535 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -11,7 +11,7 @@ /********************************************************************* * This function will find the global ports required by a Switch Block - * module. It wil find all the circuit models in the circuit library + * module. It will find all the circuit models in the circuit library * that may be included in the Switch Block * Collect the global ports from the circuit_models and merge with the same name ********************************************************************/ @@ -60,3 +60,31 @@ std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, return global_ports; } + +/********************************************************************* + * This function will find the number of multiplexers required by + * a Switch Block module. + ********************************************************************/ +size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb) { + size_t num_muxes = 0; + /* Walk through the OUTPUT nodes at each side of a GSB, + * get the switch id of incoming edges + * and get the circuit model linked to the switch id + */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + /* Check if this node is driven by a multiplexer */ + if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { + continue; + } + /* This means we need a multiplexer, update the counter */ + num_muxes++; + } + } + return num_muxes; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h index 84c451239..d49a55539 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h @@ -14,4 +14,6 @@ std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, const CircuitLibrary& circuit_lib, const std::vector& switch_lib); +size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index d9f135892..8e5ece925 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -48,6 +48,27 @@ #include "verilog_writer_utils.h" #include "verilog_routing.h" +/******************************************************************** + * Print local wires that are used for SRAM configuration + * This function is supposed to be used by Verilog generation + * of switch blocks + * It will count the number of switch blocks, which is the + * port width for local wires when Configuration chain is used + ********************************************************************/ +static +void print_verilog_switch_block_local_sram_wires(std::fstream& fp, + const RRGSB& rr_gsb, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, + const size_t& port_size) { + size_t local_port_size = port_size; + if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { + local_port_size = find_switch_block_number_of_muxes(rr_gsb); + } + print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); +} + /********************************************************************* * Generate the Verilog module for a routing channel * Routing track wire, which is 1-input and dual output @@ -2287,13 +2308,15 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage add_reserved_sram_ports_to_module_manager(module_manager, module_id, rr_gsb.get_sb_num_reserved_conf_bits()); } + + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + /* Normal sram ports */ if (0 < rr_gsb.get_sb_num_conf_bits()) { - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); add_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, cur_sram_orgz_info->type, rr_gsb.get_sb_num_conf_bits()); @@ -2308,12 +2331,14 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage print_verilog_module_declaration(fp, module_manager, module_id); /* Finish printing ports */ - /* TODO: Local wires for memory configurations */ - /* - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb()); - */ + print_verilog_comment(fp, std::string("---- BEGIN local wires for SRAM data ports ----")); + /* Local wires for memory configurations */ + print_verilog_switch_block_local_sram_wires(fp, rr_gsb, circuit_lib, sram_model, cur_sram_orgz_info->type, + rr_gsb.get_sb_num_conf_bits()); + print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); + + /* TODO: Print routing multiplexers */ + /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index ce504a143..9f373308e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -12,6 +12,7 @@ /* FPGA-X2P context header files */ #include "spice_types.h" +#include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" /* FPGA-Verilog context header files */ @@ -646,3 +647,125 @@ void print_verilog_buffer_instance(std::fstream& fp, module_manager.add_child_module(parent_module_id, buffer_module_id); } +/******************************************************************** + * Print local wires that are used for SRAM configuration + * The local wires are strongly dependent on the organization of SRAMs. + * 1. Standalone SRAMs: + * No need for local wires, their outputs are port of the module + * + * Module + * +------------------------------+ + * | Sub-module | + * | +---------------------+ | + * | | sram_out|---->|---->sram_out + * | | | | + * | | sram_out|---->|---->sram_out + * | | | | + * | +---------------------+ | + * +------------------------------+ + * + * 2. Configuration-chain Flip-flops: + * two ports will be added, which are the head of scan-chain + * and the tail of scan-chain + * + * Module + * +-----------------------------------------+ + * | | + * | +------+ +------+ +------+ | + * | +->| CCFF |--->| CCFF | ... | CCFF |-+ | + * | | +------+ | +------+ | +------+ | | + * head--->|-+-----------+------------+-----------+->|--->tail + * | local wire | + * +-----------------------------------------+ + * 3. Memory decoders: + * two ports will be added, which are regular output and inverted output + * Note that the outputs are the data outputs of SRAMs + * BL/WLs of memory decoders are ports of module but not local wires + * + * Module + * +-----------------------------------------+ + * | | + * | +------+ +------+ +------+ | + * | | SRAM | | SRAM | ... | SRAM | | + * | +------+ +------+ +------+ | + * | ^ ^ ^ | + * | | | | | + * BL/WL--->|---------------------------------------->| + * | local wire | + * +-----------------------------------------+ + + * + ********************************************************************/ +void print_verilog_local_sram_wires(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, + const size_t& port_size) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Port size must be at least one! */ + if (0 == port_size) { + return; + } + + /* Depend on the configuraion style */ + switch(sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Nothing to do here */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* Generate the name of local wire for the CCFF inputs, CCFF output and inverted output */ + std::vector ccff_ports; + /* [0] => CCFF input */ + ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), port_size)); + /* [1] => CCFF output */ + ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), port_size)); + /* [2] => CCFF inverted output */ + ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INOUT), port_size)); + /* Print local wire definition */ + for (const auto& ccff_port : ccff_ports) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_port) << ";" << std::endl; + } + /* Connect first CCFF to the head */ + /* Head is always a 1-bit port */ + BasicPort ccff_head_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1); + BasicPort ccff_head_local_port(ccff_ports[0].get_name(), 1); + print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false); + /* Connect last CCFF to the tail */ + /* Tail is always a 1-bit port */ + BasicPort ccff_tail_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1); + BasicPort ccff_tail_local_port(ccff_ports[1].get_name(), ccff_ports[1].get_msb(), ccff_ports[1].get_msb()); + print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false); + /* Connect CCFFs into chains */ + /* If port size is 0 or 1, there is no need for the chain connection */ + if (2 > port_size) { + break; + } + /* Cascade the CCFF between head and tail */ + BasicPort ccff_chain_input_port(ccff_ports[0].get_name(), port_size - 1); + BasicPort ccff_chain_output_port(ccff_ports[1].get_name(), 1, port_size - 1); + print_verilog_wire_connection(fp, ccff_chain_output_port, ccff_chain_input_port, false); + break; + } + case SPICE_SRAM_MEMORY_BANK: { + /* Generate the name of local wire for the SRAM output and inverted output */ + std::vector sram_ports; + /* [0] => SRAM output */ + sram_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), port_size)); + /* [1] => SRAM inverted output */ + sram_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), port_size)); + /* Print local wire definition */ + for (const auto& sram_port : sram_ports) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_port) << ";" << std::endl; + } + + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 8ab7906e0..a272a74f5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -84,4 +84,10 @@ void print_verilog_buffer_instance(std::fstream& fp, const BasicPort& instance_input_port, const BasicPort& instance_output_port); +void print_verilog_local_sram_wires(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, + const size_t& port_size); + #endif From 056219f180325fb5e18d37aa2bdf691052742139 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Thu, 26 Sep 2019 11:32:57 -0600 Subject: [PATCH 231/482] Rename SCFF to CCFF, configuration chain flip flop --- .../libarchfpga/SRC/check_circuit_library.cpp | 28 ++++---- .../libarchfpga/SRC/check_circuit_library.h | 2 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 4 +- vpr7_x2p/libarchfpga/SRC/circuit_types.h | 4 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 4 +- vpr7_x2p/libarchfpga/SRC/spice_types.h | 10 +-- .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 18 ++--- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 10 +-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 2 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 60 ++++++++-------- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 10 +-- .../fpga_x2p/base/link_arch_circuit_lib.cpp | 12 ++-- .../fpga_x2p/base/module_manager_utils.cpp | 4 +- vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c | 6 +- .../verilog/verilog_compact_netlist.c | 6 +- .../SRC/fpga_x2p/verilog/verilog_decoder.c | 8 +-- .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 10 +-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../verilog/verilog_top_netlist_utils.c | 36 +++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 70 +++++++++---------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 2 +- 21 files changed, 154 insertions(+), 154 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index d32578d2d..f9e3bb9e1 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -286,14 +286,14 @@ size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, } /************************************************************************ - * A function to check the port map of SCFF circuit model + * A function to check the port map of CCFF circuit model ***********************************************************************/ -size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib, +size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_CCFF == circuit_lib.model_type(circuit_model)); /* Check if we have D, Set and Reset */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, @@ -404,9 +404,9 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { * 2. Circuit models have unique prefix * 3. Check IOPADs have input and output ports * 4. Check MUXes has been defined and has input and output ports - * 5. We must have at least one SRAM or SCFF + * 5. We must have at least one SRAM or CCFF * 6. SRAM must have at least an input and an output ports - * 7. SCFF must have at least a clock, an input and an output ports + * 7. CCFF must have at least a clock, an input and an output ports * 8. FF must have at least a clock, an input and an output ports * 9. LUT must have at least an input, an output and a SRAM ports * 10. We must have default circuit models for these types: MUX, channel wires and wires @@ -456,13 +456,13 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required); - /* 5. We must have at least one SRAM or SCFF */ + /* 5. We must have at least one SRAM or CCFF */ if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size()) - && ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SCFF).size()) ) { + && ( 0 == circuit_lib.models_by_type(SPICE_MODEL_CCFF).size()) ) { vpr_printf(TIO_MESSAGE_ERROR, "At least one %s or %s circuit model is required!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)], - CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SCFF)]); + CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_CCFF)]); /* Incremental the counter for errors */ num_err++; } @@ -474,13 +474,13 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SRAM, sram_port_types_required); - /* 7. SCFF must have at least a clock, an input and an output ports*/ - std::vector scff_port_types_required; - scff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); - scff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - scff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); + /* 7. CCFF must have at least a clock, an input and an output ports*/ + std::vector ccff_port_types_required; + ccff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); + ccff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); + ccff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SCFF, scff_port_types_required); + num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_CCFF, ccff_port_types_required); /* 8. FF must have at least a clock, an input and an output ports*/ std::vector ff_port_types_required; diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h index 2d0bd3f03..dd6114696 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h @@ -71,7 +71,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); -size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib, +size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 6a7d23a64..67bf9a37c 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -612,7 +612,7 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ } /* Recursively find all the global ports in the circuit model / sub circuit_model - * but ignore all the SRAM and SCFF, which are configuration memories + * but ignore all the SRAM and CCFF, which are configuration memories */ std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, @@ -621,7 +621,7 @@ std::vector CircuitLibrary::model_global_ports_by_type(const Circ std::vector ignore_list; if (true == ignore_config_memories) { ignore_list.push_back(SPICE_MODEL_SRAM); - ignore_list.push_back(SPICE_MODEL_SCFF); + ignore_list.push_back(SPICE_MODEL_CCFF); } return model_global_ports_by_type(model_id, type, recursive, ignore_list); } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/circuit_types.h index 92e8b1c61..9a0e72dda 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_types.h @@ -66,7 +66,7 @@ enum e_spice_model_type { SPICE_MODEL_FF, SPICE_MODEL_SRAM, SPICE_MODEL_HARDLOGIC, - SPICE_MODEL_SCFF, + SPICE_MODEL_CCFF, SPICE_MODEL_IOPAD, SPICE_MODEL_INVBUF, SPICE_MODEL_PASSGATE, @@ -74,7 +74,7 @@ enum e_spice_model_type { NUM_CIRCUIT_MODEL_TYPES }; /* Strings correspond to each port type */ -constexpr std::array CIRCUIT_MODEL_TYPE_STRING = {{"CHAN_WIRE", "WIRE", "MUX", "LUT", "FF", "SRAM", "HARDLOGIC", "SCFF", "IOPAD", "INVBUF", "PASSGATE", "GATE"}}; +constexpr std::array CIRCUIT_MODEL_TYPE_STRING = {{"CHAN_WIRE", "WIRE", "MUX", "LUT", "FF", "SRAM", "HARDLOGIC", "CCFF", "IOPAD", "INVBUF", "PASSGATE", "GATE"}}; enum e_spice_model_design_tech { SPICE_MODEL_DESIGN_CMOS, diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 10c4b2bbe..c630dc37f 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -915,7 +915,7 @@ static void ProcessSpiceModel(ezxml_t Parent, } else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"hard_logic")) { spice_model->type = SPICE_MODEL_HARDLOGIC; } else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"sff")) { - spice_model->type = SPICE_MODEL_SCFF; + spice_model->type = SPICE_MODEL_CCFF; } else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"iopad")) { spice_model->type = SPICE_MODEL_IOPAD; } else if (0 == strcmp(FindProperty(Parent,"type",TRUE),"inv_buf")) { @@ -1417,7 +1417,7 @@ static void check_spice_models(int num_spice_model, } } /* Check scan-chain dff has input and output, clock ports*/ - if (SPICE_MODEL_SCFF == spice_models[i].type) { + if (SPICE_MODEL_CCFF == spice_models[i].type) { has_sram = 1; has_clock_port = 0; has_in_port = 0; diff --git a/vpr7_x2p/libarchfpga/SRC/spice_types.h b/vpr7_x2p/libarchfpga/SRC/spice_types.h index 42ecbb3f2..542f5bcbd 100644 --- a/vpr7_x2p/libarchfpga/SRC/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/spice_types.h @@ -476,12 +476,12 @@ struct s_mem_bank_info { }; /* Scan-chain Flip-flops information */ -typedef struct s_scff_info t_scff_info; -struct s_scff_info { +typedef struct s_ccff_info t_ccff_info; +struct s_ccff_info { t_spice_model* mem_model; /* SPICE model of a memory bit */ int num_mem_bit; /* Number of memory bits in total */ - int num_scff; /* Number of Scan-chain flip-flops */ - /* TODO: More to be added, SCFF support is naive now */ + int num_ccff; /* Number of Scan-chain flip-flops */ + /* TODO: More to be added, CCFF support is naive now */ }; /* Standalone SRAMs information */ @@ -495,7 +495,7 @@ struct s_standalone_sram_info { struct s_sram_orgz_info { enum e_sram_orgz type; t_mem_bank_info* mem_bank_info; /* Only be allocated when orgz type is memory bank */ - t_scff_info* scff_info; /* Only be allocated when orgz type is scan-chain */ + t_ccff_info* ccff_info; /* Only be allocated when orgz type is scan-chain */ t_standalone_sram_info* standalone_sram_info; /* Only be allocated when orgz type is standalone */ /* Head of configuration bits, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index 844eb16e3..a4c87afa8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -270,7 +270,7 @@ int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, case SPICE_MODEL_FF: case SPICE_MODEL_SRAM: case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: case SPICE_MODEL_IOPAD: return count_num_sram_bits_one_generic_spice_model(cur_spice_model); default: @@ -336,7 +336,7 @@ int count_num_mode_bits_one_spice_model(t_spice_model* cur_spice_model) { case SPICE_MODEL_FF: case SPICE_MODEL_SRAM: case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: case SPICE_MODEL_IOPAD: return count_num_mode_bits_one_generic_spice_model(cur_spice_model); default: @@ -528,7 +528,7 @@ int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, case SPICE_MODEL_FF: case SPICE_MODEL_SRAM: case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: case SPICE_MODEL_IOPAD: /* Other block, we just count the number SRAM ports defined by user */ num_reserved_conf_bits = 0; @@ -829,7 +829,7 @@ int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model, case SPICE_MODEL_FF: case SPICE_MODEL_SRAM: case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: case SPICE_MODEL_IOPAD: return count_num_conf_bits_one_generic_spice_model(cur_spice_model, cur_sram_orgz_type); default: @@ -919,7 +919,7 @@ int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, /* add configuration bits of a MUX to linked-list * when SRAM organization type is scan-chain */ void -add_mux_scff_conf_bits_to_llist(int mux_size, +add_mux_ccff_conf_bits_to_llist(int mux_size, t_sram_orgz_info* cur_sram_orgz_info, int num_mux_sram_bits, int* mux_sram_bits, t_spice_model* mux_spice_model) { @@ -1134,7 +1134,7 @@ add_mux_conf_bits_to_llist(int mux_size, switch (cur_sram_orgz_info->type) { case SPICE_SRAM_STANDALONE: case SPICE_SRAM_SCAN_CHAIN: - add_mux_scff_conf_bits_to_llist(mux_size, cur_sram_orgz_info, + add_mux_ccff_conf_bits_to_llist(mux_size, cur_sram_orgz_info, num_mux_sram_bits, mux_sram_bits, mux_spice_model); break; @@ -1152,9 +1152,9 @@ add_mux_conf_bits_to_llist(int mux_size, return; } -/* Add SCFF configutration bits to a linked list*/ +/* Add CCFF configutration bits to a linked list*/ static -void add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, +void add_sram_ccff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int num_sram_bits, int* sram_bits) { int ibit, cur_mem_bit; t_conf_bit** sram_bit = NULL; @@ -1304,7 +1304,7 @@ add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, switch (cur_sram_orgz_info->type) { case SPICE_SRAM_STANDALONE: case SPICE_SRAM_SCAN_CHAIN: - add_sram_scff_conf_bits_to_llist(cur_sram_orgz_info, + add_sram_ccff_conf_bits_to_llist(cur_sram_orgz_info, num_sram_bits, sram_bits); break; case SPICE_SRAM_MEMORY_BANK: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index db19f59f2..501a774df 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -347,17 +347,17 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, } case SPICE_SRAM_SCAN_CHAIN: /* Two types of ports are available: - * (1) Head of a chain of Scan-chain Flip-Flops (SCFFs), enabled by port type of INPUT - * (2) Tail of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of OUTPUT + * (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT + * (2) Tail of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT * +------+ +------+ +------+ - * Head --->| SCFF |--->| SCFF |--->| SCFF |---> Tail + * Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail * +------+ +------+ +------+ */ if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("scff_head"); + port_name += std::string("ccff_head"); } else { VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name += std::string("scff_tail"); + port_name += std::string("ccff_tail"); } break; case SPICE_SRAM_MEMORY_BANK: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 59d240102..d88a27658 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -344,7 +344,7 @@ void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, break; case SPICE_SRAM_SCAN_CHAIN: vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit scan-chain organization...\n"); - if (SPICE_MODEL_SCFF != cur_sram_inf_orgz->spice_model->type) { + if (SPICE_MODEL_CCFF != cur_sram_inf_orgz->spice_model->type) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Scan-chain SRAM organization requires a SPICE model(type=sff)!\n", __FILE__, __LINE__); exit(1); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index bdc3bbfbb..0c2706814 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -1094,7 +1094,7 @@ char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type) case SPICE_MODEL_IOPAD: ret = "iopad"; break; - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: ret = "Scan-chain Flip-flop"; break; default: @@ -2220,7 +2220,7 @@ void check_sram_spice_model_ports(t_spice_model* cur_spice_model, } void check_ff_spice_model_ports(t_spice_model* cur_spice_model, - boolean is_scff) { + boolean is_ccff) { int iport; int num_input_ports; t_spice_model_port** input_ports = NULL; @@ -2232,22 +2232,22 @@ void check_ff_spice_model_ports(t_spice_model* cur_spice_model, int num_err = 0; /* Check the type of SPICE model */ - if (FALSE == is_scff) { + if (FALSE == is_ccff) { assert(SPICE_MODEL_FF == cur_spice_model->type); } else { - assert(SPICE_MODEL_SCFF == cur_spice_model->type); + assert(SPICE_MODEL_CCFF == cur_spice_model->type); } /* Check if we have D, Set and Reset */ input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, FALSE); - if (TRUE == is_scff) { + if (TRUE == is_ccff) { if (1 > num_input_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL should at least have an input port!\n", + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL should at least have an input port!\n", __FILE__, __LINE__); num_err++; } for (iport = 0; iport < num_input_ports; iport++) { if (1 != input_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL: each input port with size 1!\n", + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL: each input port with size 1!\n", __FILE__, __LINE__); num_err++; } @@ -2269,20 +2269,20 @@ void check_ff_spice_model_ports(t_spice_model* cur_spice_model, /* Check if we have clock */ clock_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_ports, FALSE); if (1 > num_clock_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|SCFF] SPICE MODEL should have at least 1 clock port!\n", + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|CCFF] SPICE MODEL should have at least 1 clock port!\n", __FILE__, __LINE__); num_err++; } for (iport = 0; iport < num_clock_ports; iport++) { if (1 != clock_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|SCFF] SPICE MODEL: 1 clock port with size 1!\n", + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|CCFF] SPICE MODEL: 1 clock port with size 1!\n", __FILE__, __LINE__); num_err++; } } /* Check if we have output */ output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE); - if (FALSE == is_scff) { + if (FALSE == is_ccff) { if (1 != output_ports[0]->size) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL: each output port with size 1!\n", __FILE__, __LINE__); @@ -2290,12 +2290,12 @@ void check_ff_spice_model_ports(t_spice_model* cur_spice_model, } } else { if (2 != num_output_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL should have 2 output ports!\n", + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL should have 2 output ports!\n", __FILE__, __LINE__); num_err++; for (iport = 0; iport < num_output_ports; iport++) { if (1 != output_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SCFF SPICE MODEL: the output port (%s) should have a size of 1!\n", + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL: the output port (%s) should have a size of 1!\n", __FILE__, __LINE__, output_ports[iport]->prefix); num_err++; } @@ -2462,11 +2462,11 @@ void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info) { return; } -t_scff_info* alloc_one_scff_info() { - return (t_scff_info*)my_malloc(sizeof(t_scff_info)); +t_ccff_info* alloc_one_ccff_info() { + return (t_ccff_info*)my_malloc(sizeof(t_ccff_info)); } -void free_one_scff_info(t_scff_info* scff_info) { +void free_one_ccff_info(t_ccff_info* ccff_info) { return; } @@ -2501,23 +2501,23 @@ void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info, return; } -void init_scff_info(t_scff_info* cur_scff_info, +void init_ccff_info(t_ccff_info* cur_ccff_info, t_spice_model* cur_mem_model) { - assert(NULL != cur_scff_info); + assert(NULL != cur_ccff_info); assert(NULL != cur_mem_model); - cur_scff_info->mem_model = cur_mem_model; - cur_scff_info->num_mem_bit = 0; - cur_scff_info->num_scff = 0; + cur_ccff_info->mem_model = cur_mem_model; + cur_ccff_info->num_mem_bit = 0; + cur_ccff_info->num_ccff = 0; return; } -void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info, +void update_ccff_info_num_mem_bit(t_ccff_info* cur_ccff_info, int num_mem_bit) { - assert(NULL != cur_scff_info); + assert(NULL != cur_ccff_info); - cur_scff_info->num_mem_bit = num_mem_bit; + cur_ccff_info->num_mem_bit = num_mem_bit; return; } @@ -2573,8 +2573,8 @@ void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, num_bl_per_sram, num_wl_per_sram); break; case SPICE_SRAM_SCAN_CHAIN: - cur_sram_orgz_info->scff_info = alloc_one_scff_info(); - init_scff_info(cur_sram_orgz_info->scff_info, cur_mem_model); + cur_sram_orgz_info->ccff_info = alloc_one_ccff_info(); + init_ccff_info(cur_sram_orgz_info->ccff_info, cur_mem_model); break; case SPICE_SRAM_STANDALONE: cur_sram_orgz_info->standalone_sram_info = alloc_one_standalone_sram_info(); @@ -2624,7 +2624,7 @@ void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, free_one_mem_bank_info(cur_sram_orgz_info->mem_bank_info); break; case SPICE_SRAM_SCAN_CHAIN: - free_one_scff_info(cur_sram_orgz_info->scff_info); + free_one_ccff_info(cur_sram_orgz_info->ccff_info); break; case SPICE_SRAM_STANDALONE: free_one_standalone_sram_info(cur_sram_orgz_info->standalone_sram_info); @@ -2831,7 +2831,7 @@ int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info) { case SPICE_SRAM_STANDALONE: return cur_sram_orgz_info->standalone_sram_info->num_mem_bit; case SPICE_SRAM_SCAN_CHAIN: - return cur_sram_orgz_info->scff_info->num_mem_bit; + return cur_sram_orgz_info->ccff_info->num_mem_bit; case SPICE_SRAM_MEMORY_BANK: return cur_sram_orgz_info->mem_bank_info->num_mem_bit; default: @@ -2854,7 +2854,7 @@ void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info, update_standalone_sram_info_num_mem_bit(cur_sram_orgz_info->standalone_sram_info, new_num_mem_bit); break; case SPICE_SRAM_SCAN_CHAIN: - update_scff_info_num_mem_bit(cur_sram_orgz_info->scff_info, new_num_mem_bit); + update_ccff_info_num_mem_bit(cur_sram_orgz_info->ccff_info, new_num_mem_bit); break; case SPICE_SRAM_MEMORY_BANK: update_mem_bank_info_num_mem_bit(cur_sram_orgz_info->mem_bank_info, new_num_mem_bit); @@ -2903,7 +2903,7 @@ void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, (*mem_model_ptr) = cur_sram_orgz_info->standalone_sram_info->mem_model; break; case SPICE_SRAM_SCAN_CHAIN: - (*mem_model_ptr) = cur_sram_orgz_info->scff_info->mem_model; + (*mem_model_ptr) = cur_sram_orgz_info->ccff_info->mem_model; break; case SPICE_SRAM_MEMORY_BANK: (*mem_model_ptr) = cur_sram_orgz_info->mem_bank_info->mem_model; @@ -2929,7 +2929,7 @@ void update_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, cur_sram_orgz_info->standalone_sram_info->mem_model = cur_mem_model; break; case SPICE_SRAM_SCAN_CHAIN: - cur_sram_orgz_info->scff_info->mem_model = cur_mem_model; + cur_sram_orgz_info->ccff_info->mem_model = cur_mem_model; break; case SPICE_SRAM_MEMORY_BANK: cur_sram_orgz_info->mem_bank_info->mem_model = cur_mem_model; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 8a5a0a9e4..114d2d604 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -235,7 +235,7 @@ void check_sram_spice_model_ports(t_spice_model* cur_spice_model, boolean include_bl_wl); void check_ff_spice_model_ports(t_spice_model* cur_spice_model, - boolean is_scff); + boolean is_ccff); /* Functions to manipulate t_conf_bit and t_conf_bit_info */ void free_conf_bit(t_conf_bit* conf_bit); @@ -270,9 +270,9 @@ t_mem_bank_info* alloc_one_mem_bank_info(); void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info); -t_scff_info* alloc_one_scff_info(); +t_ccff_info* alloc_one_ccff_info(); -void free_one_scff_info(t_scff_info* scff_info); +void free_one_ccff_info(t_ccff_info* ccff_info); t_standalone_sram_info* alloc_one_standalone_sram_info(); @@ -299,10 +299,10 @@ void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info, int num_mem_bit); -void init_scff_info(t_scff_info* cur_scff_info, +void init_ccff_info(t_ccff_info* cur_ccff_info, t_spice_model* cur_mem_model); -void update_scff_info_num_mem_bit(t_scff_info* cur_scff_info, +void update_ccff_info_num_mem_bit(t_ccff_info* cur_ccff_info, int num_mem_bit); void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index 342524903..fb48628c8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -114,7 +114,7 @@ CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_nam /************************************************************************ * Link circuit model to the SRAM organization * Case 1: standalone organization required a SRAM circuit model - * Case 1: scan-chain organization required a SCFF circuit model + * Case 1: configuration-chain organization required a CCFF circuit model * Case 1: memory-bank organization required a SRAM circuit model ***********************************************************************/ static @@ -128,9 +128,9 @@ void link_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, /* Check the type of SRAM_Ciruit_MODEL required by different sram organization */ /* check SRAM ports * Checker for circuit models used by the SRAM organization - * either SRAMs or SCFFs - * 1. It will check the basic port required for SRAMs and SCFFs - * 2. It will check any special ports required for SRAMs and SCFFs + * either SRAMs or CCFFs + * 1. It will check the basic port required for SRAMs and CCFFs + * 2. It will check any special ports required for SRAMs and CCFFs */ switch (cur_sram_inf_orgz->type) { case SPICE_SRAM_STANDALONE: @@ -145,8 +145,8 @@ void link_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, break; case SPICE_SRAM_SCAN_CHAIN: /* check Scan-chain Flip-flop ports */ - cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SCFF); - check_scff_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model); + cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_CCFF); + check_ccff_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model); break; case SPICE_SRAM_LOCAL_ENCODER: /* Wipe out LOCAL ENCODER, it is not supported here ! */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index bc844ca7c..86accaba9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -157,7 +157,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, std::vector model_port_types; /* Prepare a list of module port types to be added, the port type will be used to specify the port type in Verilog/SPICE module */ std::vector module_port_types; - /* Actual port size may be different from user specification. Think about SCFF */ + /* Actual port size may be different from user specification. Think about CCFF */ size_t sram_port_size = port_size; switch (sram_orgz_type) { @@ -172,7 +172,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); module_port_types.push_back(ModuleManager::MODULE_OUTPUT_PORT); - /* SCFF head/tail are single-bit ports */ + /* CCFF head/tail are single-bit ports */ sram_port_size = 1; break; case SPICE_SRAM_MEMORY_BANK: { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c index d24a6bcba..a75da71a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c @@ -351,10 +351,10 @@ void fprint_spice_sram_one_outport(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: if (0 == port_type_index) { - port_name = "scff_out"; + port_name = "ccff_out"; } else { assert(1 == port_type_index); - port_name = "scff_outb"; + port_name = "ccff_outb"; } break; case SPICE_SRAM_MEMORY_BANK: @@ -696,7 +696,7 @@ void fprint_global_pad_ports_spice_model(FILE* fp, case SPICE_MODEL_LUT: case SPICE_MODEL_FF: case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: case SPICE_MODEL_INVBUF: case SPICE_MODEL_PASSGATE: case SPICE_MODEL_GATE: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 9538bbcf2..28056e1c1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -79,7 +79,7 @@ char* generate_compact_verilog_grid_module_name(t_type_ptr phy_block_type, /* ONLY for compact Verilog netlists: * Update the grid_index_low and grid_index_high for each spice_models - * Currently, we focus on three spice_models: SRAMs/SCFFs/IOPADs + * Currently, we focus on three spice_models: SRAMs/CCFFs/IOPADs */ static void compact_verilog_update_one_spice_model_grid_index(t_type_ptr phy_block_type, @@ -102,7 +102,7 @@ void compact_verilog_update_one_spice_model_grid_index(t_type_ptr phy_block_type case SPICE_MODEL_HARDLOGIC: case SPICE_MODEL_GATE: break; - case SPICE_MODEL_SCFF: + case SPICE_MODEL_CCFF: case SPICE_MODEL_SRAM: stamped_cnt = spice_model[i].cnt; spice_model[i].grid_index_low[grid_x][grid_y] = stamped_cnt; @@ -158,7 +158,7 @@ void compact_verilog_update_sram_orgz_info_grid_index(t_sram_orgz_info* cur_sram /* ONLY for compact Verilog netlists: * Update the grid_index_low and grid_index_high for each spice_models - * Currently, we focus on three spice_models: SRAMs/SCFFs/IOPADs + * Currently, we focus on three spice_models: SRAMs/CCFFs/IOPADs * IMPORTANT: The sequence of for loop should be consistent with * 1. bitstream logic block * 2. verilog pbtypes logic block diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c index 3cb4f9a5a..bdfff337b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c @@ -241,7 +241,7 @@ void dump_verilog_decoder(FILE* fp, } /* For standalone-SRAM configuration organization: - * Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs + * Dump the module of configuration module which connect configuration ports to SRAMs/CCFFs */ static void dump_verilog_standalone_sram_config_module(FILE* fp, @@ -288,7 +288,7 @@ void dump_verilog_standalone_sram_config_module(FILE* fp, /* For scan-chain configuration organization: - * Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs + * Dump the module of configuration module which connect configuration ports to SRAMs/CCFFs */ static void dump_verilog_scan_chain_config_module(FILE* fp, @@ -331,7 +331,7 @@ void dump_verilog_scan_chain_config_module(FILE* fp, fprintf(fp, ";\n"); /* Verilog Module body */ - /* Connect the head of current scff to the tail of previous scff*/ + /* Connect the head of current ccff to the tail of previous ccff*/ fprintf(fp, " "); fprintf(fp, "assign "); dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 1, num_mem_bits - 1, -1, VERILOG_PORT_CONKT); @@ -405,7 +405,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp, } /* For Memory-bank configuration organization: - * Dump the module of configuration module which connect configuration ports to SRAMs/SCFFs + * Dump the module of configuration module which connect configuration ports to SRAMs/CCFFs */ static void dump_verilog_membank_config_module(FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index ea89dedd7..d3504109f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -219,10 +219,10 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, /*************************************************************************************** * For scan-chain configuration organization: * Generate the Verilog module of configuration module - * which connect configuration ports to SRAMs/SCFFs in a chain: + * which connect configuration ports to SRAMs/CCFFs in a chain: * * +------+ +------+ +------+ - * sc_in--->| SCFF |--->| SCFF |---> ... --->| SCFF |----> sc_out + * sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out * +------+ +------+ +------+ ***************************************************************************************/ static @@ -264,7 +264,7 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager, BasicPort sc_first_input_port(sc_input_port.get_name(), 1); print_verilog_wire_connection(fp, sc_first_input_port, sc_head_port, false); - /* Connect the head of current scff to the tail of previous scff*/ + /* Connect the head of current ccff to the tail of previous ccff*/ BasicPort chain_output_port(sc_input_port.get_name(), 1, num_mem_bits - 1); BasicPort chain_input_port(sc_output_port.get_name(), 0, num_mem_bits - 2); print_verilog_wire_connection(fp, chain_output_port, chain_input_port, false); @@ -281,11 +281,11 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager, * Generate the configuration peripheral circuits for the top-level Verilog netlist * This function will create Verilog modules depending on the configuration scheme: * 1. Scan-chain: - * It will create a module which connects the Scan-Chain Flip-Flops (SCFFs) + * It will create a module which connects the Scan-Chain Flip-Flops (CCFFs) * as a chain: * * +------+ +------+ +------+ - * sc_in--->| SCFF |--->| SCFF |---> ... --->| SCFF |----> sc_out + * sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out * +------+ +------+ +------+ * * 2. Memory bank: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index f122dbdba..72f7d0b66 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2041,7 +2041,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, /* Asserts*/ assert ((1 == num_sram_port) && (NULL != sram_port)); assert (NULL != sram_port[0]->spice_model); - assert ((SPICE_MODEL_SCFF == sram_port[0]->spice_model->type) + assert ((SPICE_MODEL_CCFF == sram_port[0]->spice_model->type) || (SPICE_MODEL_SRAM == sram_port[0]->spice_model->type)); /* Get the memory model */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 8cd04d16e..a06b8d35b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -191,8 +191,8 @@ void dump_verilog_top_netlist_scan_chain_ports(t_sram_orgz_info* cur_sram_orgz_i static void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp) { - t_spice_model* scff_mem_model = NULL; - int num_scffs; + t_spice_model* ccff_mem_model = NULL; + int num_ccffs; /* A valid file handler */ if (NULL == fp) { @@ -200,23 +200,23 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr exit(1); } - num_scffs = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &scff_mem_model); + num_ccffs = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model); /* Check */ - assert( SPICE_MODEL_SCFF == scff_mem_model->type ); + assert( SPICE_MODEL_CCFF == ccff_mem_model->type ); /* Delcare local wires */ - fprintf(fp, " wire [0:%d] %s_scff_in_local_bus;\n", - num_scffs - 1, scff_mem_model->prefix); + fprintf(fp, " wire [0:%d] %s_ccff_in_local_bus;\n", + num_ccffs - 1, ccff_mem_model->prefix); - fprintf(fp, " wire [0:%d] %s_scff_out_local_bus;\n", - num_scffs - 1, scff_mem_model->prefix); + fprintf(fp, " wire [0:%d] %s_ccff_out_local_bus;\n", + num_ccffs - 1, ccff_mem_model->prefix); /* Dump ports only visible during formal verification*/ fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); fprintf(fp, " "); dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - 0, num_scffs - 1, + 0, num_ccffs - 1, VERILOG_PORT_WIRE, false); fprintf(fp, ";\n"); fprintf(fp, "`endif\n"); @@ -224,8 +224,8 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr /* Exception for head: connect to primary inputs */ /* - fprintf(fp, " assign %s_scff_in[%d] = %s;\n", - scff_mem_model->prefix, 0, + fprintf(fp, " assign %s_ccff_in[%d] = %s;\n", + ccff_mem_model->prefix, 0, top_netlist_scan_chain_head_prefix); */ /* Connected the scan-chain flip-flops */ @@ -234,10 +234,10 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr fprintf(fp, " genvar i;\n"); fprintf(fp, " generate\n"); fprintf(fp, " for (i = %d; i < %d; i = i + 1) begin\n", - 1, num_scffs - 1); - fprintf(fp, "assign %s_scff_in[i] = %s_scff_out[i - 1];\n", - scff_mem_model->prefix, - scff_mem_model->prefix); + 1, num_ccffs - 1); + fprintf(fp, "assign %s_ccff_in[i] = %s_ccff_out[i - 1];\n", + ccff_mem_model->prefix, + ccff_mem_model->prefix); fprintf(fp, " end\n"); fprintf(fp, " endgenerate;\n"); */ @@ -1102,7 +1102,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ } fprintf(fp, ",\n"); if (true == is_explicit_mapping) { - fprintf(fp, ".scff_scff_in_local_bus ("); + fprintf(fp, ".ccff_ccff_in_local_bus ("); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { @@ -1110,7 +1110,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ } fprintf(fp, ",\n"); if (true == is_explicit_mapping) { - fprintf(fp, ".scff_scff_out_local_bus ("); + fprintf(fp, ".ccff_ccff_out_local_bus ("); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 816d75b68..76e7848ca 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -1214,12 +1214,12 @@ void dump_verilog_sram_one_local_outport(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: if (0 == port_type_index) { - port_name = "scff_out_local_bus"; + port_name = "ccff_out_local_bus"; } else if (1 == port_type_index) { - port_name = "scff_outb_local_bus"; + port_name = "ccff_outb_local_bus"; } else { assert(-1 == port_type_index); - port_name = "scff_in_local_bus"; + port_name = "ccff_in_local_bus"; } break; case SPICE_SRAM_MEMORY_BANK: @@ -1283,12 +1283,12 @@ void dump_verilog_sram_one_outport(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: if (0 == port_type_index) { - port_name = "scff_out"; + port_name = "ccff_out"; } else if (1 == port_type_index) { - port_name = "scff_outb"; + port_name = "ccff_outb"; } else { assert(-1 == port_type_index); - port_name = "scff_in"; + port_name = "ccff_in"; } break; case SPICE_SRAM_MEMORY_BANK: @@ -1380,7 +1380,7 @@ void dump_verilog_formal_verification_sram_ports(FILE* fp, port_name = "out_fm"; break; case SPICE_SRAM_SCAN_CHAIN: - mem_model = cur_sram_orgz_info->scff_info->mem_model; + mem_model = cur_sram_orgz_info->ccff_info->mem_model; port_name = "out_fm"; break; case SPICE_SRAM_MEMORY_BANK: @@ -1444,12 +1444,12 @@ void dump_verilog_sram_one_port(FILE* fp, } break; case SPICE_SRAM_SCAN_CHAIN: - mem_model = cur_sram_orgz_info->scff_info->mem_model; + mem_model = cur_sram_orgz_info->ccff_info->mem_model; if (0 == port_type_index) { - port_name = "scff_head"; + port_name = "ccff_head"; } else if (1 == port_type_index) { assert(1 == port_type_index); - port_name = "scff_tail"; + port_name = "ccff_tail"; /* Special case: scan-chain ff output should be an output always */ if (VERILOG_PORT_INPUT == dump_port_type) { actual_dump_port_type = VERILOG_PORT_OUTPUT; @@ -1588,7 +1588,7 @@ void dump_verilog_sram_local_ports(FILE* fp, case SPICE_SRAM_SCAN_CHAIN: /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ if (true == is_explicit_mapping) { - fprintf(fp, ".scff_scff_head("); + fprintf(fp, ".ccff_ccff_head("); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_lsb, sram_lsb, @@ -1599,7 +1599,7 @@ void dump_verilog_sram_local_ports(FILE* fp, fprintf(fp, ",\n"); /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ if (true == is_explicit_mapping) { - fprintf(fp, ".scff_scff_tail("); + fprintf(fp, ".ccff_ccff_tail("); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_msb, sram_msb, @@ -1827,7 +1827,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i assert(NULL != cur_sram_orgz_info); assert(NULL != cur_sram_verilog_model); assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type) - || (SPICE_MODEL_SCFF == cur_sram_verilog_model->type)); + || (SPICE_MODEL_CCFF == cur_sram_verilog_model->type)); /* Get current index of SRAM module */ cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); @@ -1993,7 +1993,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, assert(NULL != cur_sram_orgz_info); assert(NULL != cur_sram_verilog_model); assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type) - || (SPICE_MODEL_SCFF == cur_sram_verilog_model->type)); + || (SPICE_MODEL_CCFF == cur_sram_verilog_model->type)); /* Get current index of SRAM module */ cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); @@ -2119,7 +2119,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, return; } -void dump_verilog_scff_config_bus(FILE* fp, +void dump_verilog_ccff_config_bus(FILE* fp, t_spice_model* mem_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int lsb, int msb, @@ -2128,7 +2128,7 @@ void dump_verilog_scff_config_bus(FILE* fp, /* Check */ assert(NULL != mem_spice_model); - assert(SPICE_MODEL_SCFF == mem_spice_model->type); + assert(SPICE_MODEL_CCFF == mem_spice_model->type); /* Check the file handler*/ if (NULL == fp) { @@ -2172,17 +2172,17 @@ void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, /* Check */ assert(NULL != mem_spice_model); assert((SPICE_MODEL_SRAM == mem_spice_model->type) - || (SPICE_MODEL_SCFF == mem_spice_model->type)); + || (SPICE_MODEL_CCFF == mem_spice_model->type)); /* Depend on the style of configuraion circuit */ switch (cur_sram_orgz_info->type) { case SPICE_SRAM_STANDALONE: break; case SPICE_SRAM_SCAN_CHAIN: - /* We need to connect SCFF inputs and outputs in cacading + /* We need to connect CCFF inputs and outputs in cacading * Scan-chain FF outputs are directly wired to SRAM inputs of MUXes */ - /* Connect first SCFF to the head */ + /* Connect first CCFF to the head */ /* fprintf(fp, "assign "); dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram, -1, VERILOG_PORT_CONKT); @@ -2190,7 +2190,7 @@ void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, dump_verilog_sram_one_port(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram, 0, VERILOG_PORT_CONKT); fprintf(fp, ";\n"); */ - /* Connect last SCFF to the tail */ + /* Connect last CCFF to the tail */ /* fprintf(fp, "assign "); dump_verilog_sram_one_port(fp, cur_sram_orgz_info, cur_num_sram + num_mem_conf_bits - 1, cur_num_sram + num_mem_conf_bits - 1, 1, VERILOG_PORT_CONKT); @@ -2198,8 +2198,8 @@ void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model, dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_mem_conf_bits - 1, cur_num_sram + num_mem_conf_bits - 1, 0, VERILOG_PORT_CONKT); fprintf(fp, ";\n"); */ - /* Connect SCFFs into chains */ - /* Cascade the SCFF between head and tail */ + /* Connect CCFFs into chains */ + /* Cascade the CCFF between head and tail */ /* if (1 < num_mem_conf_bits) { fprintf(fp, "assign "); @@ -2359,10 +2359,10 @@ void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_WIRE); fprintf(fp, ";\n"); - /* We need to connect SCFF inputs and outputs in cacading + /* We need to connect CCFF inputs and outputs in cacading * Scan-chain FF outputs are directly wired to SRAM inputs of MUXes */ - /* Connect first SCFF to the head */ + /* Connect first CCFF to the head */ fprintf(fp, "assign "); dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, @@ -2373,7 +2373,7 @@ void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, cur_num_sram, cur_num_sram, -1, VERILOG_PORT_CONKT); fprintf(fp, ";\n"); - /* Connect last SCFF to the tail */ + /* Connect last CCFF to the tail */ fprintf(fp, "assign "); dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits - 1, cur_num_sram + num_mux_conf_bits - 1, @@ -2384,10 +2384,10 @@ void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model, cur_num_sram + num_mux_conf_bits - 1, cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); fprintf(fp, ";\n"); - /* Connect SCFFs into chains */ - /* Connect the first SCFF (LSB) to the head */ - /* Connect the last SCFF (MSB) to the tail */ - /* Cascade the SCFF between head and tail */ + /* Connect CCFFs into chains */ + /* Connect the first CCFF (LSB) to the head */ + /* Connect the last CCFF (MSB) to the tail */ + /* Cascade the CCFF between head and tail */ if (1 < num_mux_conf_bits) { fprintf(fp, "assign "); dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -2784,20 +2784,20 @@ void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur fprintf(fp, ";\n"); dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_WIRE); fprintf(fp, ";\n"); - /* Connect first SCFF to the head */ + /* Connect first CCFF to the head */ fprintf(fp, "assign "); dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, lsb, -1, VERILOG_PORT_CONKT); fprintf(fp, " = "); dump_verilog_sram_one_port(fp, cur_sram_orgz_info, lsb, lsb, 0, VERILOG_PORT_CONKT); fprintf(fp, ";\n"); - /* Connect last SCFF to the tail */ + /* Connect last CCFF to the tail */ fprintf(fp, "assign "); dump_verilog_sram_one_port(fp, cur_sram_orgz_info, msb, msb, 1, VERILOG_PORT_CONKT); fprintf(fp, " = "); dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, msb, msb, 0, VERILOG_PORT_CONKT); fprintf(fp, ";\n"); - /* Connect SCFFs into chains */ - /* Cascade the SCFF between head and tail */ + /* Connect CCFFs into chains */ + /* Cascade the CCFF between head and tail */ if (1 < msb - lsb) { fprintf(fp, "assign "); dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, @@ -3042,7 +3042,7 @@ int dump_verilog_mem_module_one_port_map(FILE* fp, /* * Dump the port map of a memory module - * which consist of a number of SRAMs/SCFFs etc. + * which consist of a number of SRAMs/CCFFs etc. */ void dump_verilog_mem_module_port_map(FILE* fp, t_spice_model* mem_model, @@ -3152,7 +3152,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, assert(NULL != cur_sram_orgz_info); assert(NULL != cur_sram_verilog_model); assert((SPICE_MODEL_SRAM == cur_sram_verilog_model->type) - || (SPICE_MODEL_SCFF == cur_sram_verilog_model->type)); + || (SPICE_MODEL_CCFF == cur_sram_verilog_model->type)); switch (cur_sram_orgz_info->type) { case SPICE_SRAM_MEMORY_BANK: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 639843c57..2a39d5fff 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -164,7 +164,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* sram_verilog_model); -void dump_verilog_scff_config_bus(FILE* fp, +void dump_verilog_ccff_config_bus(FILE* fp, t_spice_model* mem_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int lsb, int msb, From 3b13c959f39c1f51c007dd9d3b8a7dbdf3d9840d Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Thu, 26 Sep 2019 14:04:40 -0600 Subject: [PATCH 232/482] Finish renaming SCFF to CCFF --- .../SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 14 +++++++------- .../vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp | 12 ++++++------ vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h index 2ce9546a5..e32bb520a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h @@ -30,7 +30,7 @@ int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, enum e_sram_orgz cur_sram_orgz_type); void -add_mux_scff_conf_bits_to_llist(int mux_size, +add_mux_ccff_conf_bits_to_llist(int mux_size, t_sram_orgz_info* cur_sram_orgz_info, int num_mux_sram_bits, int* mux_sram_bits, t_spice_model* mux_spice_model); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index d1b6cb417..662a6e1d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -418,20 +418,20 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, } case SPICE_SRAM_SCAN_CHAIN: /* Three types of ports are available: - * (1) Input of Scan-chain Flip-Flops (SCFFs), enabled by port type of INPUT - * (2) Output of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of OUTPUT - * (2) Inverted output of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of INOUT + * (1) Input of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT + * (2) Output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT + * (2) Inverted output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of INOUT * +------+ +------+ +------+ - * Head --->| SCFF |--->| SCFF |--->| SCFF |---> Tail + * Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail * +------+ +------+ +------+ */ if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("scff_in_local_bus"); + port_name += std::string("ccff_in_local_bus"); } else if ( SPICE_MODEL_PORT_OUTPUT == port_type ) { - port_name += std::string("scff_out_local_bus"); + port_name += std::string("ccff_out_local_bus"); } else { VTR_ASSERT( SPICE_MODEL_PORT_INOUT == port_type ); - port_name += std::string("scff_outb_local_bus"); + port_name += std::string("ccff_outb_local_bus"); } break; case SPICE_SRAM_MEMORY_BANK: { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index d3504109f..0de1249cd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -222,7 +222,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, * which connect configuration ports to SRAMs/CCFFs in a chain: * * +------+ +------+ +------+ - * sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out + * cc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out * +------+ +------+ +------+ ***************************************************************************************/ static @@ -246,8 +246,8 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager, BasicPort sc_head_port(std::string(top_netlist_scan_chain_head_prefix), 1); module_manager.add_port(module_id, sc_head_port, ModuleManager::MODULE_INPUT_PORT); /* Add the inputs of scan-chain FFs, which are the outputs of the module */ - BasicPort sc_input_port(std::string("chain_input"), num_mem_bits); - module_manager.add_port(module_id, sc_input_port, ModuleManager::MODULE_OUTPUT_PORT); + BasicPort cc_input_port(std::string("chain_input"), num_mem_bits); + module_manager.add_port(module_id, cc_input_port, ModuleManager::MODULE_OUTPUT_PORT); /* Add the outputs of scan-chain FFs, which are inputs of the module */ BasicPort sc_output_port(std::string("chain_output"), num_mem_bits); module_manager.add_port(module_id, sc_output_port, ModuleManager::MODULE_INPUT_PORT); @@ -261,11 +261,11 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager, fp << std::endl; /* Connect scan-chain input to the first scan-chain input */ - BasicPort sc_first_input_port(sc_input_port.get_name(), 1); + BasicPort sc_first_input_port(cc_input_port.get_name(), 1); print_verilog_wire_connection(fp, sc_first_input_port, sc_head_port, false); /* Connect the head of current ccff to the tail of previous ccff*/ - BasicPort chain_output_port(sc_input_port.get_name(), 1, num_mem_bits - 1); + BasicPort chain_output_port(cc_input_port.get_name(), 1, num_mem_bits - 1); BasicPort chain_input_port(sc_output_port.get_name(), 0, num_mem_bits - 2); print_verilog_wire_connection(fp, chain_output_port, chain_input_port, false); @@ -285,7 +285,7 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager, * as a chain: * * +------+ +------+ +------+ - * sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out + * cc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out * +------+ +------+ +------+ * * 2. Memory bank: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c index 7bc682ad7..c6d563c37 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c @@ -131,7 +131,7 @@ char* top_netlist_normal_bl_port_postfix = "_bl"; char* top_netlist_normal_wl_port_postfix = "_wl"; char* top_netlist_normal_blb_port_postfix = "_blb"; char* top_netlist_normal_wlb_port_postfix = "_wlb"; -char* top_netlist_scan_chain_head_prefix = "sc_in"; +char* top_netlist_scan_chain_head_prefix = "cc_in"; char* top_tb_reset_port_name = "greset"; char* top_tb_set_port_name = "gset"; From 05eaa412b10e85778ba3273b38a8bb6cb042e216 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 26 Sep 2019 14:31:05 -0600 Subject: [PATCH 233/482] refactored short-connection of switch block --- .../SRC/fpga_x2p/verilog/verilog_routing.c | 164 ++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 8e5ece925..8dd57c443 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2145,6 +2145,157 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ +static +BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const PORTS& cur_rr_node_direction) { + /* Get the index in sb_info of cur_rr_node */ + int index = rr_sb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); + /* Make sure this node is included in this sb_info */ + VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); + + DeviceCoordinator chan_rr_node_coordinator = rr_sb.get_side_block_coordinator(chan_side); + + vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); + std::string chan_port_name = generate_routing_track_port_name(rr_sb.get_chan_node(chan_side, index)->type, + chan_port_coord, index, + rr_sb.get_chan_node_direction(chan_side, index)); + return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */ +} + +/********************************************************************* + * Print a short interconneciton in switch box + * There are two cases should be noticed. + * 1. The actual fan-in of cur_rr_node is 0. In this case, + the cur_rr_node need to be short connected to itself which is on the opposite side of this switch + * 2. The actual fan-in of cur_rr_node is 0. In this case, + * The cur_rr_node need to connected to the drive_rr_node + ********************************************************************/ +static +void print_verilog_unique_switch_box_short_interc(std::fstream& fp, + const RRGSB& rr_sb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const size_t& actual_fan_in, + t_rr_node* drive_rr_node) { + /* Check the driver*/ + if (0 == actual_fan_in) { + VTR_ASSERT(drive_rr_node == cur_rr_node); + } else { + VTR_ASSERT(1 == actual_fan_in); + } + + /* Check the file handler*/ + check_file_handler(fp); + + /* Find the name of output port */ + BasicPort output_port = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); + /* Find the name of input port */ + BasicPort input_port; + /* Generate the input port object */ + switch (drive_rr_node->type) { + /* case SOURCE: */ + case OPIN: { + /* Find the coordinator (grid_x and grid_y) for the input port */ + vtr::Point input_port_coord(drive_rr_node->xlow, drive_rr_node->ylow); + std::string input_port_name = generate_grid_side_port_name(input_port_coord, + rr_sb.get_opin_node_grid_side(drive_rr_node), + drive_rr_node->ptc_num); + input_port.set_name(input_port_name); + input_port.set_width(1); /* Every grid output has a port size of 1 */ + break; + } + case CHANX: + case CHANY: { + enum e_side input_pin_side = chan_side; + /* This should be an input in the data structure of RRGSB */ + if (cur_rr_node == drive_rr_node) { + /* To be strict, the input should locate on the opposite side. + * Use the else part if this may change in some architecture. + */ + Side side_manager(chan_side); + input_pin_side = side_manager.get_opposite(); + } else { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_sb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); + } + /* We need to be sure that drive_rr_node is part of the SB */ + input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_pin_side, drive_rr_node, IN_PORT); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + /* Print the wire connection in Verilog format */ + print_verilog_comment(fp, std::string("----- Short connection " + output_port.get_name() + " -----")); + print_verilog_wire_connection(fp, output_port, input_port, false); + fp << std::endl; +} + +/********************************************************************* + * Print the Verilog modules for a interconnection inside switch block + * The interconnection could be either a wire or a routing multiplexer, + * which depends on the fan-in of the rr_nodes in the switch block + ********************************************************************/ +static +void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info, + const RRGSB& rr_sb, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const e_side& chan_side, + const size_t& chan_node_id, + const bool& use_explicit_mapping) { + int num_drive_rr_nodes = 0; + t_rr_node** drive_rr_nodes = NULL; + + /* Get the node */ + t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id); + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + /* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */ + if (true == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { + num_drive_rr_nodes = 0; + drive_rr_nodes = NULL; + } else { + num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; + drive_rr_nodes = cur_rr_node->drive_rr_nodes; + /* Special: if there are zero-driver nodes. We skip here */ + if (0 == num_drive_rr_nodes) { + return; + } + } + + if (0 == num_drive_rr_nodes) { + /* Print a special direct connection*/ + print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, + num_drive_rr_nodes, cur_rr_node); + } else if (1 == num_drive_rr_nodes) { + /* Print a direct connection*/ + print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); + } else if (1 < num_drive_rr_nodes) { + /* Print the multiplexer, fan_in >= 2 */ + /* + dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, + num_drive_rr_nodes, drive_rr_nodes, + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + is_explicit_mapping); + */ + } /*Nothing should be done else*/ +} + /********************************************************************* * Generate the Verilog module for a Switch Box. * A Switch Box module consists of following ports: @@ -2338,6 +2489,19 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); /* TODO: Print routing multiplexers */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + print_verilog_comment(fp, std::string("----- " + side_manager.to_string() + " side Routing Multiplexers -----")); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + /* We care INC_DIRECTION tracks at this side*/ + if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, rr_sb, + circuit_lib, mux_lib, rr_switches, + side_manager.get_side(), + itrack, is_explicit_mapping); + } + } + } /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); From f0589cc2cfc27409a2fa3b62ec68e0a91a4c77e4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 26 Sep 2019 20:59:19 -0600 Subject: [PATCH 234/482] refactoring mux Verilog generation for switch blocks --- vpr7_x2p/vpr/SRC/device/mux_library.h | 3 +- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 49 +++ vpr7_x2p/vpr/SRC/device/mux_utils.h | 8 + .../SRC/fpga_x2p/base/fpga_x2p_mux_utils.c | 28 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 37 ++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 + .../vpr/SRC/fpga_x2p/base/module_manager.h | 3 +- .../fpga_x2p/base/module_manager_utils.cpp | 1 - .../SRC/fpga_x2p/base/module_manager_utils.h | 1 - .../SRC/fpga_x2p/verilog/verilog_routing.c | 297 +++++++++++++++--- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 12 files changed, 361 insertions(+), 75 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h index 93e004252..7e38f27b1 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library.h +++ b/vpr7_x2p/vpr/SRC/device/mux_library.h @@ -32,8 +32,9 @@ class MuxLibrary { public: /* Public mutators */ /* Add a mux to the library */ void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); - private: /* Private accessors */ + public: /* Public validators */ bool valid_mux_id(const MuxId& mux) const; + private: /* Private accessors */ bool valid_mux_lookup() const; bool valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const; bool valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const; diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 800b65198..dc153fcb9 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -3,10 +3,12 @@ * that are used to implement a multiplexer *************************************************/ #include +#include #include "spice_types.h" #include "util.h" #include "vtr_assert.h" +#include "decoder_library_utils.h" #include "mux_utils.h" /* Validate the number of inputs for a multiplexer implementation, @@ -237,3 +239,50 @@ MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llis return mux_lib; } + +/************************************************** + * Find the number of reserved configuration bits for a multiplexer + * The reserved configuration bits is only used by ReRAM-based multiplexers + * It is actually the shared BL/WLs among ReRAMs + *************************************************/ +size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + if (SPICE_MODEL_DESIGN_RRAM != circuit_lib.design_tech_type(mux_model)) { + return 0; + } + + std::vector mux_branch_sizes = mux_graph.branch_sizes(); + /* For tree-like multiplexers: they have two shared configuration bits */ + if ( (1 == mux_branch_sizes.size()) + && (2 == mux_branch_sizes[0]) ) { + return mux_branch_sizes[0]; + } + /* One-level multiplexer */ + if ( 1 == mux_graph.num_levels() ) { + return mux_graph.num_inputs(); + } + /* Multi-level multiplexers: TODO: This should be better tested and clarified + * Now the multi-level multiplexers are treated as cascaded one-level multiplexers + * Use the maximum branch sizes and multiply it by the number of levels + */ + std::vector::iterator max_mux_branch_size = std::max_element(mux_branch_sizes.begin(), mux_branch_sizes.end()); + return mux_graph.num_levels() * (*max_mux_branch_size); +} + +/************************************************** + * Find the number of configuration bits for a multiplexer + * In general, the number of configuration bits is + * the number of memory bits for a mux_graph + * However, when local decoders are used, this should be changed! + *************************************************/ +size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + if (true == circuit_lib.mux_use_local_encoder(mux_model)) { + return find_mux_local_decoder_addr_size(mux_graph.num_memory_bits()); + } + + return mux_graph.num_memory_bits(); +} + diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index c61db23c8..ee92cce49 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -37,4 +37,12 @@ std::vector build_mux_intermediate_buffer_location_map(const CircuitLibrar MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head); +size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph); + +size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c index 5e031e0c3..40c60d776 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c @@ -189,20 +189,20 @@ int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, /*************************************************************************************** * Find the number of inputs for a encoder with a given output size - * Inputs - * | | | | | - * +-----------+ - * / \ - * / Encoder \ - * +-----------------+ - * | | | | | | | | - * Outputs - * - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) - * We plus 1, which is all-zero condition for outputs - ***************************************************************************************/ + * Inputs + * | | | | | + * +-----------+ + * / \ + * / Encoder \ + * +-----------------+ + * | | | | | | | | + * Outputs + * + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) + * We plus 1, which is all-zero condition for outputs + ****************************************************************************************/ int determine_mux_local_encoder_num_inputs(int num_outputs) { return ceil(log(num_outputs) / log(2)); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index d1b6cb417..29cfdf34c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -259,28 +259,28 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& pin_id, const bool& for_top_netlist) { if (true == for_top_netlist) { - std::string port_name = "grid_"; + std::string port_name = std::string("grid_"); port_name += std::to_string(coordinate.x()); - port_name += "__"; + port_name += std::string("__"); port_name += std::to_string(coordinate.y()); - port_name += "__pin_"; + port_name += std::string("__pin_"); port_name += std::to_string(height); - port_name += "__"; + port_name += std::string("__"); port_name += std::to_string(size_t(side)); - port_name += "__"; + port_name += std::string("__"); port_name += std::to_string(pin_id); - port_name += "_"; + port_name += std::string("_"); return port_name; } /* For non-top netlist */ VTR_ASSERT( false == for_top_netlist ); Side side_manager(side); std::string port_name = std::string(side_manager.to_string()); - port_name += "_height_"; + port_name += std::string("_height_"); port_name += std::to_string(height); - port_name += "__pin_"; + port_name += std::string("__pin_"); port_name += std::to_string(pin_id); - port_name += "_"; + port_name += std::string("_"); return port_name; } @@ -456,3 +456,22 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, return port_name; } + +/********************************************************************* + * Generate the port name for the input bus of a routing multiplexer + * This is very useful in Verilog code generation where the inputs of + * a routing multiplexer may come from different ports. + * On the other side, the datapath input of a routing multiplexer + * is defined as a bus port. + * Therefore, to interface, a bus port is required, and this function + * give a name to the bus port + * To keep the bus port name unique to each multiplexer we will instance, + * a mux_instance_id should be provided by user + *********************************************************************/ +std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& mux_instance_id) { + std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_inbus"); + return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index bf78578d9..333a388d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -82,4 +82,9 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type, const e_spice_model_port_type& port_type); +std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& mux_instance_id); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 8befd9be9..297046059 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -64,9 +64,10 @@ class ModuleManager { void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); /* Add a child module to a parent module */ void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); - private: /* Private validators/invalidators */ + public: /* Public validators/invalidators */ bool valid_module_id(const ModuleId& module) const; bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; + private: /* Private validators/invalidators */ void invalidate_name2id_map(); void invalidate_port_lookup(); private: /* Internal data */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 16143976f..1aa0c9024 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -118,7 +118,6 @@ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_ const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, const std::string& preproc_flag, const size_t& port_size) { /* Create a port */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 7ab8892c1..17d395cdb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -28,7 +28,6 @@ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_ const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, const std::string& preproc_flag, const size_t& port_size); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 8dd57c443..6aa7ccb91 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -39,6 +39,7 @@ #include "fpga_x2p_bitstream_utils.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_naming.h" +#include "mux_utils.h" #include "module_manager.h" #include "module_manager_utils.h" @@ -2167,6 +2168,92 @@ BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb, return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */ } +/********************************************************************* + * Generate an input port for routing multiplexer inside the switch block + * In addition to give the Routing Resource node of the input + * Users should provide the side of input, which is different case by case: + * 1. When the input is a pin of a CLB/Logic Block, the input_side should + * be the side of the node on its grid! + * For example, the input pin is on the top side of a switch block + * but on the right side of a switch block + * +--------+ + * | | + * | Grid |---+ + * | | | + * +--------+ v input_pin + * +----------------+ + * | Switch Block | + * +----------------+ + * 2. When the input is a routing track, the input_side should be + * the side of the node locating on the switch block + ********************************************************************/ +static +BasicPort generate_switch_block_input_port(const RRGSB& rr_sb, + const e_side& input_side, + t_rr_node* input_rr_node) { + BasicPort input_port; + /* Generate the input port object */ + switch (input_rr_node->type) { + /* case SOURCE: */ + case OPIN: { + /* Find the coordinator (grid_x and grid_y) for the input port */ + vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); + std::string input_port_name = generate_grid_side_port_name(input_port_coord, + input_side, + input_rr_node->ptc_num); + input_port.set_name(input_port_name); + input_port.set_width(1); /* Every grid output has a port size of 1 */ + break; + } + case CHANX: + case CHANY: { + input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_side, input_rr_node, IN_PORT); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + return input_port; +} + +/********************************************************************* + * Generate a list of input ports for routing multiplexer inside the switch block + ********************************************************************/ +static +std::vector generate_switch_block_input_ports(const RRGSB& rr_sb, + const std::vector& input_rr_nodes) { + std::vector input_ports; + + for (auto input_rr_node : input_rr_nodes) { + enum e_side input_pin_side = NUM_SIDES; + switch (input_rr_node->type) { + case OPIN: + input_pin_side = rr_sb.get_opin_node_grid_side(input_rr_node); + break; + case CHANX: + case CHANY: { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_sb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); + VTR_ASSERT(NUM_SIDES != input_pin_side); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + input_ports.push_back(generate_switch_block_input_port(rr_sb, input_pin_side, input_rr_node)); + } + + return input_ports; +} + /********************************************************************* * Print a short interconneciton in switch box * There are two cases should be noticed. @@ -2180,38 +2267,21 @@ void print_verilog_unique_switch_box_short_interc(std::fstream& fp, const RRGSB& rr_sb, const e_side& chan_side, t_rr_node* cur_rr_node, - const size_t& actual_fan_in, t_rr_node* drive_rr_node) { - /* Check the driver*/ - if (0 == actual_fan_in) { - VTR_ASSERT(drive_rr_node == cur_rr_node); - } else { - VTR_ASSERT(1 == actual_fan_in); - } - /* Check the file handler*/ check_file_handler(fp); /* Find the name of output port */ BasicPort output_port = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); - /* Find the name of input port */ - BasicPort input_port; + enum e_side input_pin_side = chan_side; + /* Generate the input port object */ switch (drive_rr_node->type) { - /* case SOURCE: */ - case OPIN: { - /* Find the coordinator (grid_x and grid_y) for the input port */ - vtr::Point input_port_coord(drive_rr_node->xlow, drive_rr_node->ylow); - std::string input_port_name = generate_grid_side_port_name(input_port_coord, - rr_sb.get_opin_node_grid_side(drive_rr_node), - drive_rr_node->ptc_num); - input_port.set_name(input_port_name); - input_port.set_width(1); /* Every grid output has a port size of 1 */ + case OPIN: + input_pin_side = rr_sb.get_opin_node_grid_side(drive_rr_node); break; - } case CHANX: case CHANY: { - enum e_side input_pin_side = chan_side; /* This should be an input in the data structure of RRGSB */ if (cur_rr_node == drive_rr_node) { /* To be strict, the input should locate on the opposite side. @@ -2224,8 +2294,6 @@ void print_verilog_unique_switch_box_short_interc(std::fstream& fp, int index = -1; rr_sb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); } - /* We need to be sure that drive_rr_node is part of the SB */ - input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_pin_side, drive_rr_node, IN_PORT); break; } default: /* SOURCE, IPIN, SINK are invalid*/ @@ -2234,6 +2302,8 @@ void print_verilog_unique_switch_box_short_interc(std::fstream& fp, __FILE__, __LINE__); exit(1); } + /* Find the name of input port */ + BasicPort input_port = generate_switch_block_input_port(rr_sb, input_pin_side, drive_rr_node); /* Print the wire connection in Verilog format */ print_verilog_comment(fp, std::string("----- Short connection " + output_port.get_name() + " -----")); @@ -2241,6 +2311,145 @@ void print_verilog_unique_switch_box_short_interc(std::fstream& fp, fp << std::endl; } +/********************************************************************* + * Print a Verilog instance of a routing multiplexer as well as + * associated memory modules for a connection inside a switch block + ********************************************************************/ +static +void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info, + const ModuleId& sb_module, + const RRGSB& rr_sb, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const std::vector& drive_rr_nodes, + const size_t& switch_index, + const bool& is_explicit_mapping) { + /* Check the file handler*/ + check_file_handler(fp); + + /* Check */ + /* Check current rr_node is CHANX or CHANY*/ + VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); + + /* Get the circuit model id of the routing multiplexer */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); + size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, mux_model, datapath_mux_size); + VTR_ASSERT(true == valid_mux_implementation_num_inputs(impl_mux_size)); + + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, impl_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + + /* Find the module name of the multiplexer and try to find it in the module manager */ + std::string mux_module_name = generate_verilog_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + + /* Get the MUX instance id from the module manager */ + size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module); + + /* Print the input bus for the inputs of a multiplexer + * We use the datapath input size (mux_size) to name the bus + * just to following the naming convention when the tool is built + * The bus port size should be the input size of multiplexer implementation + */ + BasicPort inbus_port; + inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); + inbus_port.set_width(datapath_mux_size); + + /* Create the path of the input of multiplexer in the hierarchy + * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! + */ + std::string mux_input_hie_path = std::string(rr_sb.gen_sb_verilog_instance_name()) + std::string("/") + + mux_module_name + std::string("_") + + std::to_string(mux_instance_id) + std::string("_/in"); + cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); + + /* Generate input ports that are wired to the input bus of the routing multiplexer */ + std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); + /* Connect input ports to bus */ + fp << generate_verilog_local_wire(inbus_port, mux_input_ports); + + /* TODO: Find the number of reserved configuration bits for the routing multiplexer + num_mux_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(verilog_model, + cur_sram_orgz_info->type, + mux_size); + */ + + /* TODO: Find the number of configuration bits for the routing multiplexer + num_mux_conf_bits = count_num_conf_bits_one_spice_model(verilog_model, + cur_sram_orgz_info->type, + mux_size); + */ + + /* Print the configuration port bus */ + /* TODO: Print the configuration bus for the routing multiplexers + dump_verilog_mux_config_bus(fp, verilog_model, cur_sram_orgz_info, + mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + */ + + /* Dump ports visible only during formal verification */ + fp << std::endl; + print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); + /* TODO: Print the SRAM configuration ports for formal verification + dump_verilog_formal_verification_mux_sram_ports_wiring(fp, cur_sram_orgz_info, + verilog_model, mux_size, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1); + */ + print_verilog_endif(fp); + + /* TODO: Instanciate the Mux Module */ + /* TODO: add global ports */ + /* TODO: add input bus port */ + /* TODO: add output port */ + /* TODO: Add different configuraton port for the routing multiplexer + * Different design technology requires different configuration bus! + dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, + mux_size, cur_num_sram, num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); + */ + + /* TODO: Instanciate memory modules */ + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + /* Call the memory module defined for this SRAM-based MUX! */ + /* + mem_subckt_name = generate_verilog_mux_subckt_name(verilog_model, mux_size, verilog_mem_posfix); + dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, + verilog_model, mux_size, mem_model, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + is_explicit_mapping); + */ + break; + case SPICE_MODEL_DESIGN_RRAM: + /* RRAM-based MUX does not need any SRAM dumping + * But we have to get the number of configuration bits required by this MUX + * and update the number of memory bits + */ + /* + update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); + update_sram_orgz_info_num_blwl(cur_sram_orgz_info, + cur_bl + num_mux_conf_bits, + cur_wl + num_mux_conf_bits); + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid design technology for circuit model (%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + } +} + + /********************************************************************* * Print the Verilog modules for a interconnection inside switch block * The interconnection could be either a wire or a routing multiplexer, @@ -2250,6 +2459,7 @@ static void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, + const ModuleId& sb_module, const RRGSB& rr_sb, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, @@ -2257,42 +2467,38 @@ void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, const e_side& chan_side, const size_t& chan_node_id, const bool& use_explicit_mapping) { - int num_drive_rr_nodes = 0; - t_rr_node** drive_rr_nodes = NULL; + std::vector drive_rr_nodes; /* Get the node */ t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id); /* Determine if the interc lies inside a channel wire, that is interc between segments */ - /* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */ - if (true == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { - num_drive_rr_nodes = 0; - drive_rr_nodes = NULL; - } else { - num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; - drive_rr_nodes = cur_rr_node->drive_rr_nodes; + if (false == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { + for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { + drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); + } /* Special: if there are zero-driver nodes. We skip here */ - if (0 == num_drive_rr_nodes) { + if (0 == drive_rr_nodes.size()) { return; } } - if (0 == num_drive_rr_nodes) { + if (0 == drive_rr_nodes.size()) { /* Print a special direct connection*/ print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); - } else if (1 == num_drive_rr_nodes) { + cur_rr_node); + } else if (1 == drive_rr_nodes.size()) { /* Print a direct connection*/ print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); - } else if (1 < num_drive_rr_nodes) { + drive_rr_nodes[DEFAULT_SWITCH_ID]); + } else if (1 < drive_rr_nodes.size()) { /* Print the multiplexer, fan_in >= 2 */ - /* - dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], - is_explicit_mapping); - */ + print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, + sb_module, rr_sb, circuit_lib, mux_lib, + rr_switches, chan_side, cur_rr_node, + drive_rr_nodes, + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + use_explicit_mapping); } /*Nothing should be done else*/ } @@ -2473,7 +2679,6 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage rr_gsb.get_sb_num_conf_bits()); /* Add ports only visible during formal verification to the module */ add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, - cur_sram_orgz_info->type, std::string(verilog_formal_verification_preproc_flag), rr_gsb.get_sb_num_conf_bits()); } @@ -2495,7 +2700,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, rr_sb, + print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, module_id, rr_sb, circuit_lib, mux_lib, rr_switches, side_manager.get_side(), itrack, is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 72f7d0b66..9c17f8ac3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -994,7 +994,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, if (TRUE == spice_model.design_tech_info.mux_info->local_encoder) { /* Get the number of inputs */ int num_outputs = cur_num_input_basis; - int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); + int num_inputs = determine_mux_local_encoder_num_inputs(num_outputs); /* Find the decoder name */ fprintf(fp, "%s %s_%d_ (", generate_verilog_decoder_subckt_name(num_inputs, num_outputs), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 9f373308e..d989f090c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -449,7 +449,7 @@ std::string generate_verilog_ports(const std::vector& merged_ports) { if (&port != &merged_ports[0]) { verilog_line += ", "; } - verilog_line += generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]); + verilog_line += generate_verilog_port(VERILOG_PORT_CONKT, port); } verilog_line += "}"; From 091bbd4d9c96ea31e7c5c2ef08191aaee4b214e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 26 Sep 2019 22:53:07 -0600 Subject: [PATCH 235/482] start refactoring the num_config_bits for circuit model --- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 105 +++++++++++++++++- vpr7_x2p/vpr/SRC/device/mux_utils.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 14 +-- 3 files changed, 105 insertions(+), 17 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index dc153fcb9..9ac264997 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -271,18 +271,111 @@ size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib, } /************************************************** - * Find the number of configuration bits for a multiplexer + * Find the number of configuration bits for a CMOS multiplexer * In general, the number of configuration bits is * the number of memory bits for a mux_graph - * However, when local decoders are used, this should be changed! + * However, when local decoders are used, + * the number of configuration bits are reduced to log2(X) *************************************************/ -size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { +static +size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type) { + size_t num_config_bits = 0; + switch (sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + num_config_bits = mux_graph.num_memory_bits(); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + if (true == circuit_lib.mux_use_local_encoder(mux_model)) { + num_config_bits = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits()); + } + + return num_config_bits; +} + +/************************************************** + * Find the number of configuration bits for a RRAM multiplexer + * In general, the number of configuration bits is + * the number of levels for a mux_graph + * This is due to only the last BL/WL of the multiplexer is + * independent from each other + * However, when local decoders are used, + * the number of configuration bits should be consider all the + * shared(reserved) configuration bits and independent bits + *************************************************/ +static +size_t find_rram_mux_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type) { + size_t num_config_bits = 0; + switch (sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + /* In memory bank, by intensively share the Bit/Word Lines, + * we only need 1 additional BL and WL for each MUX level. + */ + num_config_bits = mux_graph.num_levels(); + break; + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + /* Currently we DO NOT SUPPORT THESE, given an invalid number */ + num_config_bits = size_t(-1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + if (true == circuit_lib.mux_use_local_encoder(mux_model)) { + /* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs + * The number of states of a local decoder only depends on how many + * memory bits that the multiplexer will have + * This may NOT be correct!!! + */ return find_mux_local_decoder_addr_size(mux_graph.num_memory_bits()); } - return mux_graph.num_memory_bits(); + return num_config_bits; } +/************************************************** + * Find the number of configuration bits for + * a routing multiplexer + * Two cases are considered here. + * They are placed in different branches (sub-functions) + * in order to be easy in extending to new technology! + *************************************************/ +size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type) { + size_t num_config_bits = size_t(-1); + + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + num_config_bits = find_rram_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); + break; + case SPICE_MODEL_DESIGN_RRAM: + num_config_bits = find_rram_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + exit(1); + } + + return num_config_bits; +} diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index ee92cce49..9fa1f12ca 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -43,6 +43,7 @@ size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib, size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, const CircuitModelId& mux_model, - const MuxGraph& mux_graph); + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 6aa7ccb91..5499c61d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2378,17 +2378,11 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Connect input ports to bus */ fp << generate_verilog_local_wire(inbus_port, mux_input_ports); - /* TODO: Find the number of reserved configuration bits for the routing multiplexer - num_mux_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(verilog_model, - cur_sram_orgz_info->type, - mux_size); - */ + /* Find the number of reserved configuration bits for the routing multiplexer */ + size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); - /* TODO: Find the number of configuration bits for the routing multiplexer - num_mux_conf_bits = count_num_conf_bits_one_spice_model(verilog_model, - cur_sram_orgz_info->type, - mux_size); - */ + /* Find the number of configuration bits for the routing multiplexer */ + size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); /* Print the configuration port bus */ /* TODO: Print the configuration bus for the routing multiplexers From ead014e7d833bc5a9500338faedb445d6755eb5c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Sep 2019 11:47:34 -0600 Subject: [PATCH 236/482] refactoring the configuration bus Verilog generation for MUXes --- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 5 +- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 2 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 44 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 12 + .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 14 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 11 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 298 ++++++++++++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 10 + 8 files changed, 385 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 56de466a7..69dc47a3d 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -471,11 +471,12 @@ class CircuitLibrary { public: /* Internal mutators: build fast look-ups */ void build_model_lookup(); void build_model_port_lookup(); - private: /* Internal invalidators/validators */ - /* Validators */ + public: /* Public invalidators/validators */ bool valid_model_id(const CircuitModelId& model_id) const; bool valid_circuit_port_id(const CircuitPortId& circuit_port_id) const; bool valid_circuit_pin_id(const CircuitPortId& circuit_port_id, const size_t& pin_id) const; + private: /* Internal invalidators/validators */ + /* Validators */ bool valid_edge_id(const CircuitEdgeId& edge_id) const; bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const; bool valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const; diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 9ac264997..6a6d169a9 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -365,7 +365,7 @@ size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: - num_config_bits = find_rram_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); + num_config_bits = find_cmos_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); break; case SPICE_MODEL_DESIGN_RRAM: num_config_bits = find_rram_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index fd5fac796..80628358d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -475,3 +475,47 @@ std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_inbus"); return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); } + +/********************************************************************* + * Generate the name of a bus port which is wired to the configuration + * ports of a routing multiplexer + * This port is supposed to be used locally inside a Verilog/SPICE module + *********************************************************************/ +std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& bus_id, + const bool& inverted) { + std::string postfix = std::string("_configbus") + std::to_string(bus_id); + /* Add a bar to the end of the name for inverted bus ports */ + if (true == inverted) { + postfix += std::string("_b"); + } + + return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); +} + +/********************************************************************* + * Generate the port name for a SRAM port of a routing multiplexer + * This name is used for local wires that connecting SRAM ports + * of routing multiplexers inside a Verilog/SPICE module + * Note that the SRAM ports of routing multiplexers share the same naming + * convention regardless of their configuration style + *********************************************************************/ +std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& mux_instance_id, + const e_spice_model_port_type& port_type) { + std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_"); + + if (SPICE_MODEL_PORT_INPUT == port_type) { + postfix += std::string("out"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); + postfix += std::string("outb"); + } + + return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 333a388d1..b633d011a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -87,4 +87,16 @@ std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, const size_t& mux_size, const size_t& mux_instance_id); +std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& bus_id, + const bool& inverted); + +std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& mux_instance_id, + const e_spice_model_port_type& port_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index cb6754cea..3b60c55ab 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -83,7 +83,7 @@ * | | * v v * +------------------------------------+ - * | Multiplexer Configuration port | + * | Memory Module Configuration port | * +------------------------------------+ * | | | * v v v @@ -133,7 +133,14 @@ void print_verilog_memory_module(ModuleManager& module_manager, BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } - /* Add each input port: port width should match the number of memories */ + /* TODO: when Configuration-chain style is selected, the port map should be different! + * It should have only a head as input, a tail as output and other regular output ports + */ + /* Add each input port: port width should match the number of memories + * The number of inputs will not match the number of memory bits of a multiplexer + * when local decoders are used. + * It should be calculated by the decoder builders! + */ for (const auto& port : sram_input_ports) { BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); @@ -206,8 +213,11 @@ void print_verilog_memory_module(ModuleManager& module_manager, * update the module manager with the relationship between the parent and child modules */ module_manager.add_child_module(module_id, sram_module_id); + + /* TODO: Wire the memory cells into a chain, when Configuration-chain style is selected!!! */ } + /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 5499c61d8..a6dcb10e8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2376,7 +2376,7 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Generate input ports that are wired to the input bus of the routing multiplexer */ std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); /* Connect input ports to bus */ - fp << generate_verilog_local_wire(inbus_port, mux_input_ports); + fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; /* Find the number of reserved configuration bits for the routing multiplexer */ size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); @@ -2384,11 +2384,10 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Find the number of configuration bits for the routing multiplexer */ size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - /* Print the configuration port bus */ - /* TODO: Print the configuration bus for the routing multiplexers - dump_verilog_mux_config_bus(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); - */ + /* Print the configuration bus for the routing multiplexers */ + print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, + datapath_mux_size, mux_instance_id, + mux_num_reserved_config_bits, mux_num_config_bits); /* Dump ports visible only during formal verification */ fp << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index d989f090c..90a59e2a2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -769,3 +769,301 @@ void print_verilog_local_sram_wires(std::fstream& fp, exit(1); } } + +/********************************************************************* + * Print a number of bus ports which are wired to the configuration + * ports of a CMOS (SRAM-based) routing multiplexer + * This port is supposed to be used locally inside a Verilog/SPICE module + * + * For standalone configuration style: + * ------------------------------------ + * No bus needed + * + * For configuration-chain configuration style: + * -------------------------------------------- + * + * Module Port + * | + * v + * bus_port --------+----------------+----> ... + * | | + * sram_outputs v v + * +-----------+ +-----------+ + * | Memory | | Memory | + * | Module[0] | | Module[1] | ... + * +-----------+ +-----------+ + * | | + * v v + * +-----------+ +-----------+ + * | Routing | | Routing | + * | MUX [0] | | MUX[1] | ... + * +-----------+ +-----------+ + * + * For memory-bank configuration style: + * ------------------------------------ + * + * Module Port + * | + * v + * bus_port --------+----------------+----> ... + * | | + * bl/wl/../sram_ports v v + * +-----------+ +-----------+ + * | Memory | | Memory | + * | Module[0] | | Module[1] | ... + * +-----------+ +-----------+ + * | | + * v v + * +-----------+ +-----------+ + * | Routing | | Routing | + * | MUX [0] | | MUX[1] | ... + * +-----------+ +-----------+ + * + *********************************************************************/ +static +void print_verilog_cmos_mux_config_bus(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const e_sram_orgz& sram_orgz_type, + const size_t& mux_size, + const size_t& mux_instance_id, + const size_t& num_conf_bits) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + switch(sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not need for configuration bus + * The configuration ports of SRAM are directly wired to the ports of modules + */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* To support chain-like configuration protocol, two configuration buses should be outputted + * One for the regular SRAM ports of a routing multiplexer + * The other for the inverted SRAM ports of a routing multiplexer + */ + BasicPort config_port(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, config_port) << ";" << std::endl; + BasicPort inverted_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_config_port) << ";" << std::endl; + break; + } + case SPICE_SRAM_MEMORY_BANK: { + /* To support memory-bank configuration, SRAM outputs are supposed to be exposed to the upper level as buses + * In addition, the BL/WL ports should be grouped and be exposed to the upper level as buses + */ + /* Print configuration bus to group BL/WLs */ + BasicPort bl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, false), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, bl_bus) << ";" << std::endl; + BasicPort wl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, false), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, wl_bus) << ";" << std::endl; + + /* Print bus to group SRAM outputs, this is to interface memory cells to routing multiplexers */ + BasicPort sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_output_bus) << ";" << std::endl; + BasicPort inverted_sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; + + /* TODO: This should be handled as a function */ + /* Get the SRAM model of the mux_model */ + std::vector sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM); + /* This may be too strict for a multiplexer, what if a routing multiplexer has a mode select port? */ + VTR_ASSERT( 1 == sram_ports.size() ); + CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_ports[0]); + VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); + std::vector blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB); + std::vector wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB); + + /* Connect SRAM BL/WLs to bus */ + BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_BL), + num_conf_bits); + print_verilog_wire_connection(fp, bl_bus, mux_bl_wire, false); + BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_WL), + num_conf_bits); + print_verilog_wire_connection(fp, wl_bus, mux_wl_wire, false); + + /* Print configuration bus to group BLBs, if the ports are available in SRAM models */ + if (0 < blb_ports.size()) { + BasicPort blb_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, true), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, blb_bus) << ";" << std::endl; + /* Connect SRAM BLBs to bus */ + BasicPort mux_blb_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_BLB), + num_conf_bits); + print_verilog_wire_connection(fp, blb_bus, mux_blb_wire, false); + } + + /* Print configuration bus to group WLBs, if the ports are available in SRAM models */ + if (0 < wlb_ports.size()) { + BasicPort wlb_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, true), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, wlb_bus) << ";" << std::endl; + /* Connect SRAM WLBs to bus */ + BasicPort mux_wlb_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_WLB), + num_conf_bits); + print_verilog_wire_connection(fp, wlb_bus, mux_wlb_wire, false); + } + + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/********************************************************************* + * Print a number of bus ports which are wired to the configuration + * ports of a ReRAM-based routing multiplexer + * This port is supposed to be used locally inside a Verilog/SPICE module + * + * Currently support: + * For memory-bank configuration style: + * ------------------------------------ + * Different than CMOS routing multiplexers, ReRAM multiplexers require + * reserved BL/WLs to be grouped in buses + * + * Module Port + * | + * v + * regular/reserved bus_port --+----------------+----> ... + * | | + * bl/wl/../sram_ports v v + * +-----------+ +-----------+ + * | Memory | | Memory | + * | Module[0] | | Module[1] | ... + * +-----------+ +-----------+ + * | | + * v v + * +-----------+ +-----------+ + * | Routing | | Routing | + * | MUX [0] | | MUX[1] | ... + * +-----------+ +-----------+ + * + *********************************************************************/ +static +void print_verilog_rram_mux_config_bus(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const e_sram_orgz& sram_orgz_type, + const size_t& mux_size, + const size_t& mux_instance_id, + const size_t& num_reserved_conf_bits, + const size_t& num_conf_bits) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + switch(sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not need for configuration bus + * The configuration ports of SRAM are directly wired to the ports of modules + */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* Not supported yet. + * Configuration chain may be only applied to ReRAM-based multiplexers with local decoders + */ + break; + } + case SPICE_SRAM_MEMORY_BANK: { + /* This is currently most used in ReRAM FPGAs */ + /* Print configuration bus to group reserved BL/WLs */ + BasicPort reserved_bl_bus(generate_reserved_sram_port_name(SPICE_MODEL_PORT_BL), + num_reserved_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, reserved_bl_bus) << ";" << std::endl; + BasicPort reserved_wl_bus(generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL), + num_reserved_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, reserved_wl_bus) << ";" << std::endl; + + /* Print configuration bus to group BL/WLs */ + BasicPort bl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, false), + num_conf_bits + num_reserved_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, bl_bus) << ";" << std::endl; + BasicPort wl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, false), + num_conf_bits + num_reserved_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, wl_bus) << ";" << std::endl; + + /* Print bus to group SRAM outputs, this is to interface memory cells to routing multiplexers */ + BasicPort sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_output_bus) << ";" << std::endl; + BasicPort inverted_sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + num_conf_bits); + fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; + + /* TODO: This should be handled as a function */ + /* Get the SRAM model of the mux_model */ + std::vector sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM); + /* This may be too strict for a multiplexer, what if a routing multiplexer has a mode select port? */ + VTR_ASSERT( 1 == sram_ports.size() ); + CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_ports[0]); + VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); + + /* Wire the reserved configuration bits to part of bl/wl buses */ + BasicPort bl_bus_reserved_bits(bl_bus.get_name(), num_reserved_conf_bits); + print_verilog_wire_connection(fp, bl_bus_reserved_bits, reserved_bl_bus, false); + BasicPort wl_bus_reserved_bits(wl_bus.get_name(), num_reserved_conf_bits); + print_verilog_wire_connection(fp, wl_bus_reserved_bits, reserved_wl_bus, false); + + /* Connect SRAM BL/WLs to bus */ + BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_BL), + num_conf_bits); + BasicPort bl_bus_regular_bits(bl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); + print_verilog_wire_connection(fp, bl_bus_regular_bits, mux_bl_wire, false); + BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_WL), + num_conf_bits); + BasicPort wl_bus_regular_bits(wl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); + print_verilog_wire_connection(fp, wl_bus_regular_bits, mux_wl_wire, false); + + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + +} + +/********************************************************************* + * Print a number of bus ports which are wired to the configuration + * ports of a routing multiplexer + *********************************************************************/ +void print_verilog_mux_config_bus(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const e_sram_orgz& sram_orgz_type, + const size_t& mux_size, + const size_t& mux_instance_id, + const size_t& num_reserved_conf_bits, + const size_t& num_conf_bits) { + /* Depend on the design technology of this MUX: + * bus connections are different + * SRAM MUX: bus is connected to the output ports of SRAM + * RRAM MUX: bus is connected to the BL/WL of MUX + * TODO: Maybe things will become even more complicated, + * the bus connections may depend on the type of configuration circuit... + * Currently, this is fine. + */ + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + print_verilog_cmos_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_conf_bits); + break; + case SPICE_MODEL_DESIGN_RRAM: + print_verilog_rram_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_reserved_conf_bits, num_conf_bits); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid design technology for routing multiplexer!\n", + __FILE__, __LINE__); + exit(1); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index a272a74f5..d129b9f01 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -90,4 +90,14 @@ void print_verilog_local_sram_wires(std::fstream& fp, const e_sram_orgz sram_orgz_type, const size_t& port_size); +void print_verilog_mux_config_bus(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const e_sram_orgz& sram_orgz_type, + const size_t& mux_size, + const size_t& mux_instance_id, + const size_t& num_reserved_conf_bits, + const size_t& num_conf_bits); + + #endif From dbe1625267b74ce62aecafdddc5c6f4ded1e7d8a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Sep 2019 13:51:22 -0600 Subject: [PATCH 237/482] Refactored Verilog wiring for formal verification ports in Switch Blocks --- .../libarchfpga/SRC/circuit_library_utils.cpp | 75 +++++++++++++++++++ .../libarchfpga/SRC/circuit_library_utils.h | 16 ++++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 27 ++++--- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 63 ++++++++++------ .../fpga_x2p/verilog/verilog_writer_utils.h | 6 ++ 5 files changed, 153 insertions(+), 34 deletions(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp create mode 100644 vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp new file mode 100644 index 000000000..d74b2b2d7 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -0,0 +1,75 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: circuit_library_utils.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/09/27 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ + +/************************************************************************ + * Function to perform fundamental operation for the circuit library + * These functions are not universal methods for the CircuitLibrary class + * They are made to ease the development in some specific purposes + * Please classify such functions in this file + ***********************************************************************/ + +/* Header files should be included in a sequence */ +/* Standard header files required go first */ +#include + +#include "vtr_assert.h" + +#include "util.h" + +#include "circuit_library_utils.h" + +/******************************************************************** + * Get the model id of a SRAM model that is used to configure + * a circuit model + *******************************************************************/ +std::vector get_circuit_sram_models(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* SRAM model id is stored in the sram ports of a circuit model */ + std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); + std::vector sram_models; + + /* Create a list of sram models, but avoid duplicated model ids */ + for (const auto& sram_port : sram_ports) { + CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port); + VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); + if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) { + continue; /* Already in the list, skip the addition */ + } + /* Not in the list, add it */ + sram_models.push_back(sram_model); + } + + return sram_models; +} diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h new file mode 100644 index 000000000..e80e5c388 --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h @@ -0,0 +1,16 @@ +/******************************************************************** + * Header file for circuit_library_utils.cpp + *******************************************************************/ +#ifndef CIRCUIT_LIBRARY_UTILS_H +#define CIRCUIT_LIBRARY_UTILS_H + +/* Header files should be included in a sequence */ +/* Standard header files required go first */ + +#include +#include "circuit_library.h" + +std::vector get_circuit_sram_models(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index a6dcb10e8..5e0d99f9c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2376,7 +2376,9 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Generate input ports that are wired to the input bus of the routing multiplexer */ std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); /* Connect input ports to bus */ + print_verilog_comment(fp, std::string("----- A local bus wire for multiplexer inputs -----")); fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; + fp << std::endl; /* Find the number of reserved configuration bits for the routing multiplexer */ size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); @@ -2385,31 +2387,32 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); /* Print the configuration bus for the routing multiplexers */ + print_verilog_comment(fp, std::string("----- Local wires to group configuration ports -----")); print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, datapath_mux_size, mux_instance_id, mux_num_reserved_config_bits, mux_num_config_bits); + fp << std::endl; /* Dump ports visible only during formal verification */ - fp << std::endl; + print_verilog_comment(fp, std::string("----- Local wires used in only formal verification purpose -----")); print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); - /* TODO: Print the SRAM configuration ports for formal verification - dump_verilog_formal_verification_mux_sram_ports_wiring(fp, cur_sram_orgz_info, - verilog_model, mux_size, - cur_num_sram, - cur_num_sram + num_mux_conf_bits - 1); - */ + /* Print the SRAM configuration ports for formal verification */ + print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, + datapath_mux_size, mux_instance_id, mux_num_config_bits); print_verilog_endif(fp); + fp << std::endl; - /* TODO: Instanciate the Mux Module */ - /* TODO: add global ports */ - /* TODO: add input bus port */ - /* TODO: add output port */ - /* TODO: Add different configuraton port for the routing multiplexer + /* TODO: Instanciate the MUX Module */ + /* TODO: create port-to-port map */ + /* Link input bus port to Switch Block inputs */ + /* Link output port to Switch Block outputs */ + /* Link SRAM port to different configuraton port for the routing multiplexer * Different design technology requires different configuration bus! dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits, is_explicit_mapping); */ + /* TODO: Print an instance of the MUX Module */ /* TODO: Instanciate memory modules */ switch (circuit_lib.design_tech_type(mux_model)) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 90a59e2a2..7e6cdd693 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -9,6 +9,7 @@ #include "vtr_assert.h" /* Device-level header files */ +#include "circuit_library_utils.h" /* FPGA-X2P context header files */ #include "spice_types.h" @@ -870,21 +871,18 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp, num_conf_bits); fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; - /* TODO: This should be handled as a function */ /* Get the SRAM model of the mux_model */ - std::vector sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM); - /* This may be too strict for a multiplexer, what if a routing multiplexer has a mode select port? */ - VTR_ASSERT( 1 == sram_ports.size() ); - CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_ports[0]); - VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); - std::vector blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB); - std::vector wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB); + std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ + VTR_ASSERT( 1 == sram_models.size() ); + std::vector blb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_BLB); + std::vector wlb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_WLB); /* Connect SRAM BL/WLs to bus */ - BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_BL), + BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BL), num_conf_bits); print_verilog_wire_connection(fp, bl_bus, mux_bl_wire, false); - BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_WL), + BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WL), num_conf_bits); print_verilog_wire_connection(fp, wl_bus, mux_wl_wire, false); @@ -894,7 +892,7 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp, num_conf_bits); fp << generate_verilog_port(VERILOG_PORT_WIRE, blb_bus) << ";" << std::endl; /* Connect SRAM BLBs to bus */ - BasicPort mux_blb_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_BLB), + BasicPort mux_blb_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BLB), num_conf_bits); print_verilog_wire_connection(fp, blb_bus, mux_blb_wire, false); } @@ -905,7 +903,7 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp, num_conf_bits); fp << generate_verilog_port(VERILOG_PORT_WIRE, wlb_bus) << ";" << std::endl; /* Connect SRAM WLBs to bus */ - BasicPort mux_wlb_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_WLB), + BasicPort mux_wlb_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WLB), num_conf_bits); print_verilog_wire_connection(fp, wlb_bus, mux_wlb_wire, false); } @@ -913,7 +911,8 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp, break; } default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid SRAM organization!\n", __FILE__, __LINE__); exit(1); } @@ -998,13 +997,10 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp, num_conf_bits); fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; - /* TODO: This should be handled as a function */ /* Get the SRAM model of the mux_model */ - std::vector sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM); - /* This may be too strict for a multiplexer, what if a routing multiplexer has a mode select port? */ - VTR_ASSERT( 1 == sram_ports.size() ); - CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_ports[0]); - VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); + std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ + VTR_ASSERT( 1 == sram_models.size() ); /* Wire the reserved configuration bits to part of bl/wl buses */ BasicPort bl_bus_reserved_bits(bl_bus.get_name(), num_reserved_conf_bits); @@ -1013,11 +1009,11 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp, print_verilog_wire_connection(fp, wl_bus_reserved_bits, reserved_wl_bus, false); /* Connect SRAM BL/WLs to bus */ - BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_BL), + BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BL), num_conf_bits); BasicPort bl_bus_regular_bits(bl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); print_verilog_wire_connection(fp, bl_bus_regular_bits, mux_bl_wire, false); - BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_WL), + BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WL), num_conf_bits); BasicPort wl_bus_regular_bits(wl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); print_verilog_wire_connection(fp, wl_bus_regular_bits, mux_wl_wire, false); @@ -1025,7 +1021,8 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp, break; } default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid SRAM organization!\n", __FILE__, __LINE__); exit(1); } @@ -1067,3 +1064,25 @@ void print_verilog_mux_config_bus(std::fstream& fp, } } +/********************************************************************* + * Print a wire to connect MUX configuration ports + * This function connects the sram ports to the ports of a Verilog module + * used for formal verification + *********************************************************************/ +void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& mux_instance_id, + const size_t& num_conf_bits) { + BasicPort mux_sram_output(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + num_conf_bits); + /* Get the SRAM model of the mux_model */ + std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ + VTR_ASSERT( 1 == sram_models.size() ); + BasicPort formal_verification_port(generate_formal_verification_sram_port_name(circuit_lib, sram_models[0]), + num_conf_bits); + print_verilog_wire_connection(fp, mux_sram_output, formal_verification_port, false); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index d129b9f01..c95bfbb18 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -99,5 +99,11 @@ void print_verilog_mux_config_bus(std::fstream& fp, const size_t& num_reserved_conf_bits, const size_t& num_conf_bits); +void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const size_t& mux_instance_id, + const size_t& num_conf_bits); #endif From a3e9b4aea93373ab38896de8a29cbc056e98b6b2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 27 Sep 2019 13:58:48 -0600 Subject: [PATCH 238/482] Added mINI/lib - INI Read write to project --- libs/CMakeLists.txt | 2 + libs/external/CMakeLists.txt | 1 + libs/external/libini/CMakeLists.txt | 12 + libs/external/libini/src/ini.h | 755 ++++++++++++++++++++++++++++ vpr7_x2p/vpr/CMakeLists.txt | 14 +- 5 files changed, 778 insertions(+), 6 deletions(-) create mode 100644 libs/external/CMakeLists.txt create mode 100644 libs/external/libini/CMakeLists.txt create mode 100755 libs/external/libini/src/ini.h diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index aed5d49c0..990d003d2 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -2,6 +2,8 @@ #add_subdirectory(libarchfpga) add_subdirectory(libvtrutil) add_subdirectory(liblog) +add_subdirectory(external) +#add_subdirectory(external) #add_subdirectory(libpugiutil) #add_subdirectory(libeasygl) #add_subdirectory(librtlnumber) diff --git a/libs/external/CMakeLists.txt b/libs/external/CMakeLists.txt new file mode 100644 index 000000000..dc4be51bd --- /dev/null +++ b/libs/external/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory(libini) \ No newline at end of file diff --git a/libs/external/libini/CMakeLists.txt b/libs/external/libini/CMakeLists.txt new file mode 100644 index 000000000..2730c6325 --- /dev/null +++ b/libs/external/libini/CMakeLists.txt @@ -0,0 +1,12 @@ +cmake_minimum_required(VERSION 2.8.12) + +project(libini) + +file(GLOB_RECURSE LIB_HEADERS src/*.h) +files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) + +#Create the library +add_library(libini STATIC + ${LIB_HEADERS}) +target_include_directories(libini PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX) \ No newline at end of file diff --git a/libs/external/libini/src/ini.h b/libs/external/libini/src/ini.h new file mode 100755 index 000000000..cb323192f --- /dev/null +++ b/libs/external/libini/src/ini.h @@ -0,0 +1,755 @@ +/* + * The MIT License (MIT) + * Copyright (c) 2018 Danijel Durakovic + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do + * so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/////////////////////////////////////////////////////////////////////////////// +// +// /mINI/ v0.9.7 +// An INI file reader and writer for the modern age. +// +/////////////////////////////////////////////////////////////////////////////// +// +// A tiny utility library for manipulating INI files with a straightforward +// API and a minimal footprint. It conforms to the (somewhat) standard INI +// format - sections and keys are case insensitive and all leading and +// trailing whitespace is ignored. Comments are lines that begin with a +// semicolon. Trailing comments are allowed on section lines. +// +// Files are read on demand, upon which data is kept in memory and the file +// is closed. This utility supports lazy writing, which only writes changes +// and updates to a file and preserves custom formatting and comments. A lazy +// write invoked by a write() call will read the output file, find what +// changes have been made and update the file accordingly. If you only need to +// generate files, use generate() instead. Section and key order is preserved +// on read, write and insert. +// +/////////////////////////////////////////////////////////////////////////////// +// +// /* BASIC USAGE EXAMPLE: */ +// +// /* read from file */ +// mINI::INIFile file("myfile.ini"); +// mINI::INIStructure ini; +// file.read(ini); +// +// /* read value; gets a reference to actual value in the structure. +// if key or section don't exist, a new empty value will be created */ +// std::string& value = ini["section"]["key"]; +// +// /* read value safely; gets a copy of value in the structure. +// does not alter the structure */ +// std::string value = ini.get("section").get("key"); +// +// /* set or update values */ +// ini["section"]["key"] = "value"; +// +// /* set multiple values */ +// ini["section2"].set({ +// {"key1", "value1"}, +// {"key2", "value2"} +// }); +// +// /* write updates back to file, preserving comments and formatting */ +// file.write(ini); +// +// /* or generate a file (overwrites the original) */ +// file.generate(ini); +// +/////////////////////////////////////////////////////////////////////////////// +// +// Long live the INI file!!! +// +/////////////////////////////////////////////////////////////////////////////// + +#ifndef MINI_INI_H_ +#define MINI_INI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace mINI +{ +namespace INIStringUtil +{ +const std::string whitespaceDelimiters = " \t\n\r\f\v"; +inline void trim(std::string &str) +{ + str.erase(str.find_last_not_of(whitespaceDelimiters) + 1); + str.erase(0, str.find_first_not_of(whitespaceDelimiters)); +} +#ifndef MINI_CASE_SENSITIVE +inline void toLower(std::string &str) +{ + std::transform(str.begin(), str.end(), str.begin(), ::tolower); +} +#endif +inline void replace(std::string &str, std::string const &a, std::string const &b) +{ + if (!a.empty()) + { + std::size_t pos = 0; + while ((pos = str.find(a, pos)) != std::string::npos) + { + str.replace(pos, a.size(), b); + pos += b.size(); + } + } +} +#ifdef _WIN32 +const std::string endl = "\r\n"; +#else +const std::string endl = "\n"; +#endif +}; // namespace INIStringUtil + +template +class INIMap +{ +private: + using T_DataIndexMap = std::unordered_map; + using T_DataItem = std::pair; + using T_DataContainer = std::vector; + using T_MultiArgs = typename std::vector>; + + T_DataIndexMap dataIndexMap; + T_DataContainer data; + + inline std::size_t setEmpty(std::string &key) + { + std::size_t index = data.size(); + dataIndexMap[key] = index; + data.emplace_back(key, T()); + return index; + } + +public: + using const_iterator = typename T_DataContainer::const_iterator; + + INIMap() {} + + INIMap(INIMap const &other) + { + std::size_t data_size = other.data.size(); + for (std::size_t i = 0; i < data_size; ++i) + { + auto const &key = other.data[i].first; + auto const &obj = other.data[i].second; + data.emplace_back(key, obj); + } + dataIndexMap = T_DataIndexMap(other.dataIndexMap); + } + + T &operator[](std::string key) + { + INIStringUtil::trim(key); +#ifndef MINI_CASE_SENSITIVE + INIStringUtil::toLower(key); +#endif + auto it = dataIndexMap.find(key); + bool hasIt = (it != dataIndexMap.end()); + std::size_t index = (hasIt) ? it->second : setEmpty(key); + return data[index].second; + } + T get(std::string key) const + { + INIStringUtil::trim(key); +#ifndef MINI_CASE_SENSITIVE + INIStringUtil::toLower(key); +#endif + auto it = dataIndexMap.find(key); + if (it == dataIndexMap.end()) + { + return T(); + } + return T(data[it->second].second); + } + bool has(std::string key) const + { + INIStringUtil::trim(key); +#ifndef MINI_CASE_SENSITIVE + INIStringUtil::toLower(key); +#endif + return (dataIndexMap.count(key) == 1); + } + void set(std::string key, T obj) + { + INIStringUtil::trim(key); +#ifndef MINI_CASE_SENSITIVE + INIStringUtil::toLower(key); +#endif + auto it = dataIndexMap.find(key); + if (it != dataIndexMap.end()) + { + data[it->second].second = obj; + } + else + { + dataIndexMap[key] = data.size(); + data.emplace_back(key, obj); + } + } + void set(T_MultiArgs const &multiArgs) + { + for (auto const &it : multiArgs) + { + auto const &key = it.first; + auto const &obj = it.second; + set(key, obj); + } + } + bool remove(std::string key) + { + INIStringUtil::trim(key); +#ifndef MINI_CASE_SENSITIVE + INIStringUtil::toLower(key); +#endif + auto it = dataIndexMap.find(key); + if (it != dataIndexMap.end()) + { + std::size_t index = it->second; + data.erase(data.begin() + index); + dataIndexMap.erase(it); + for (auto &it2 : dataIndexMap) + { + auto &vi = it2.second; + if (vi > index) + { + vi--; + } + } + return true; + } + return false; + } + void clear() + { + data.clear(); + dataIndexMap.clear(); + } + std::size_t size() const + { + return data.size(); + } + const_iterator begin() const { return data.begin(); } + const_iterator end() const { return data.end(); } +}; + +using INIStructure = INIMap>; + +namespace INIParser +{ +using T_ParseValues = std::pair; + +enum class PDataType : char +{ + PDATA_NONE, + PDATA_COMMENT, + PDATA_SECTION, + PDATA_KEYVALUE, + PDATA_UNKNOWN +}; + +inline PDataType parseLine(std::string line, T_ParseValues &parseData) +{ + parseData.first.clear(); + parseData.second.clear(); + INIStringUtil::trim(line); + if (line.empty()) + { + return PDataType::PDATA_NONE; + } + char firstCharacter = line[0]; + if (firstCharacter == ';') + { + return PDataType::PDATA_COMMENT; + } + if (firstCharacter == '[') + { + auto commentAt = line.find_first_of(';'); + if (commentAt != std::string::npos) + { + line = line.substr(0, commentAt); + } + auto closingBracketAt = line.find_last_of(']'); + if (closingBracketAt != std::string::npos) + { + auto section = line.substr(1, closingBracketAt - 1); + INIStringUtil::trim(section); + parseData.first = section; + return PDataType::PDATA_SECTION; + } + } + auto lineNorm = line; + INIStringUtil::replace(lineNorm, "\\=", " "); + auto equalsAt = lineNorm.find_first_of('='); + if (equalsAt != std::string::npos) + { + auto key = line.substr(0, equalsAt); + INIStringUtil::trim(key); + INIStringUtil::replace(key, "\\=", "="); + auto value = line.substr(equalsAt + 1); + INIStringUtil::trim(value); + parseData.first = key; + parseData.second = value; + return PDataType::PDATA_KEYVALUE; + } + return PDataType::PDATA_UNKNOWN; +} +}; // namespace INIParser + +class INIReader +{ +public: + using T_LineData = std::vector; + using T_LineDataPtr = std::shared_ptr; + +private: + std::ifstream fileReadStream; + T_LineDataPtr lineData; + + T_LineData readFile() + { + std::string fileContents; + fileReadStream.seekg(0, std::ios::end); + fileContents.resize(fileReadStream.tellg()); + fileReadStream.seekg(0, std::ios::beg); + std::size_t fileSize = fileContents.size(); + fileReadStream.read(&fileContents[0], fileSize); + fileReadStream.close(); + T_LineData output; + if (fileSize == 0) + { + return output; + } + std::string buffer; + buffer.reserve(50); + for (std::size_t i = 0; i < fileSize; ++i) + { + char &c = fileContents[i]; + if (c == '\n') + { + output.emplace_back(buffer); + buffer.clear(); + continue; + } + if (c != '\0' && c != '\r') + { + buffer += c; + } + } + output.emplace_back(buffer); + return output; + } + +public: + INIReader(std::string const &filename, bool keepLineData = false) + { + fileReadStream.open(filename, std::ios::in | std::ios::binary); + if (keepLineData) + { + lineData = std::make_shared(); + } + } + ~INIReader() {} + + bool operator>>(INIStructure &data) + { + if (!fileReadStream.is_open()) + { + return false; + } + T_LineData fileLines = readFile(); + std::string section; + bool inSection = false; + INIParser::T_ParseValues parseData; + for (auto const &line : fileLines) + { + auto parseResult = INIParser::parseLine(line, parseData); + if (parseResult == INIParser::PDataType::PDATA_SECTION) + { + inSection = true; + data[section = parseData.first]; + } + else if (inSection && parseResult == INIParser::PDataType::PDATA_KEYVALUE) + { + auto const &key = parseData.first; + auto const &value = parseData.second; + data[section][key] = value; + } + if (lineData && parseResult != INIParser::PDataType::PDATA_UNKNOWN) + { + if (parseResult == INIParser::PDataType::PDATA_KEYVALUE && !inSection) + { + continue; + } + lineData->emplace_back(line); + } + } + return true; + } + T_LineDataPtr getLines() + { + return lineData; + } +}; + +class INIGenerator +{ +private: + std::ofstream fileWriteStream; + +public: + bool prettyPrint = false; + + INIGenerator(std::string const &filename) + { + fileWriteStream.open(filename, std::ios::out | std::ios::binary); + } + ~INIGenerator() {} + + bool operator<<(INIStructure const &data) + { + if (!fileWriteStream.is_open()) + { + return false; + } + if (!data.size()) + { + return true; + } + auto it = data.begin(); + for (;;) + { + auto const §ion = it->first; + auto const &collection = it->second; + fileWriteStream + << "[" + << section + << "]"; + if (collection.size()) + { + fileWriteStream << INIStringUtil::endl; + auto it2 = collection.begin(); + for (;;) + { + auto key = it2->first; + INIStringUtil::replace(key, "=", "\\="); + auto value = it2->second; + INIStringUtil::trim(value); + fileWriteStream + << key + << ((prettyPrint) ? " = " : "=") + << value; + if (++it2 == collection.end()) + { + break; + } + fileWriteStream << INIStringUtil::endl; + } + } + if (++it == data.end()) + { + break; + } + fileWriteStream << INIStringUtil::endl; + if (prettyPrint) + { + fileWriteStream << INIStringUtil::endl; + } + } + return true; + } +}; + +class INIWriter +{ +private: + using T_LineData = std::vector; + using T_LineDataPtr = std::shared_ptr; + + std::string filename; + + T_LineData getLazyOutput(T_LineDataPtr const &lineData, INIStructure &data, INIStructure &original) + { + T_LineData output; + INIParser::T_ParseValues parseData; + std::string sectionCurrent; + bool parsingSection = false; + bool continueToNextSection = false; + bool discardNextEmpty = false; + bool writeNewKeys = false; + std::size_t lastKeyLine = 0; + for (auto line = lineData->begin(); line != lineData->end(); ++line) + { + if (!writeNewKeys) + { + auto parseResult = INIParser::parseLine(*line, parseData); + if (parseResult == INIParser::PDataType::PDATA_SECTION) + { + if (parsingSection) + { + writeNewKeys = true; + parsingSection = false; + --line; + continue; + } + sectionCurrent = parseData.first; + if (data.has(sectionCurrent)) + { + parsingSection = true; + continueToNextSection = false; + discardNextEmpty = false; + output.emplace_back(*line); + lastKeyLine = output.size(); + } + else + { + continueToNextSection = true; + discardNextEmpty = true; + continue; + } + } + else if (parseResult == INIParser::PDataType::PDATA_KEYVALUE) + { + if (continueToNextSection) + { + continue; + } + if (data.has(sectionCurrent)) + { + auto &collection = data[sectionCurrent]; + auto const &key = parseData.first; + auto const &value = parseData.second; + if (collection.has(key)) + { + auto outputValue = collection[key]; + if (value == outputValue) + { + output.emplace_back(*line); + } + else + { + INIStringUtil::trim(outputValue); + auto lineNorm = *line; + INIStringUtil::replace(lineNorm, "\\=", " "); + auto equalsAt = lineNorm.find_first_of('='); + auto valueAt = lineNorm.find_first_not_of( + INIStringUtil::whitespaceDelimiters, + equalsAt + 1); + std::string outputLine = line->substr(0, valueAt); + if (prettyPrint && equalsAt + 1 == valueAt) + { + outputLine += " "; + } + outputLine += outputValue; + output.emplace_back(outputLine); + } + lastKeyLine = output.size(); + } + } + } + else + { + if (discardNextEmpty && line->empty()) + { + discardNextEmpty = false; + } + else if (parseResult != INIParser::PDataType::PDATA_UNKNOWN) + { + output.emplace_back(*line); + } + } + } + if (writeNewKeys || std::next(line) == lineData->end()) + { + T_LineData linesToAdd; + if (data.has(sectionCurrent) && original.has(sectionCurrent)) + { + auto const &collection = data[sectionCurrent]; + auto const &collectionOriginal = original[sectionCurrent]; + for (auto const &it : collection) + { + auto key = it.first; + if (collectionOriginal.has(key)) + { + continue; + } + auto value = it.second; + INIStringUtil::replace(key, "=", "\\="); + INIStringUtil::trim(value); + linesToAdd.emplace_back( + key + ((prettyPrint) ? " = " : "=") + value); + } + } + if (!linesToAdd.empty()) + { + output.insert( + output.begin() + lastKeyLine, + linesToAdd.begin(), + linesToAdd.end()); + } + if (writeNewKeys) + { + writeNewKeys = false; + --line; + } + } + } + for (auto const &it : data) + { + auto const §ion = it.first; + if (original.has(section)) + { + continue; + } + if (prettyPrint && output.size() > 0 && !output.back().empty()) + { + output.emplace_back(); + } + output.emplace_back("[" + section + "]"); + auto const &collection = it.second; + for (auto const &it2 : collection) + { + auto key = it2.first; + auto value = it2.second; + INIStringUtil::replace(key, "=", "\\="); + INIStringUtil::trim(value); + output.emplace_back( + key + ((prettyPrint) ? " = " : "=") + value); + } + } + return output; + } + +public: + bool prettyPrint = false; + + INIWriter(std::string const &filename) + : filename(filename) + { + } + ~INIWriter() {} + + bool operator<<(INIStructure &data) + { + struct stat buf; + bool fileExists = (stat(filename.c_str(), &buf) == 0); + if (!fileExists) + { + INIGenerator generator(filename); + generator.prettyPrint = prettyPrint; + return generator << data; + } + INIStructure originalData; + T_LineDataPtr lineData; + bool readSuccess = false; + { + INIReader reader(filename, true); + if ((readSuccess = reader >> originalData)) + { + lineData = reader.getLines(); + } + } + if (!readSuccess) + { + return false; + } + T_LineData output = getLazyOutput(lineData, data, originalData); + std::ofstream fileWriteStream(filename, std::ios::out | std::ios::binary); + if (fileWriteStream.is_open()) + { + if (output.size()) + { + auto line = output.begin(); + for (;;) + { + fileWriteStream << *line; + if (++line == output.end()) + { + break; + } + fileWriteStream << INIStringUtil::endl; + } + } + return true; + } + return false; + } +}; + +class INIFile +{ +private: + std::string filename; + +public: + INIFile(std::string const &filename) + : filename(filename) + { + } + + ~INIFile() {} + + bool read(INIStructure &data) const + { + if (data.size()) + { + data.clear(); + } + if (filename.empty()) + { + return false; + } + INIReader reader(filename); + return reader >> data; + } + bool generate(INIStructure const &data, bool pretty = false) const + { + if (filename.empty()) + { + return false; + } + INIGenerator generator(filename); + generator.prettyPrint = pretty; + return generator << data; + } + bool write(INIStructure &data, bool pretty = false) const + { + if (filename.empty()) + { + return false; + } + INIWriter writer(filename); + writer.prettyPrint = pretty; + return writer << data; + } +}; +} // namespace mINI + +#endif // MINI_INI_H_ diff --git a/vpr7_x2p/vpr/CMakeLists.txt b/vpr7_x2p/vpr/CMakeLists.txt index 4d97fcf0d..0fa11717e 100644 --- a/vpr7_x2p/vpr/CMakeLists.txt +++ b/vpr7_x2p/vpr/CMakeLists.txt @@ -3,7 +3,7 @@ cmake_minimum_required(VERSION 2.8.12) if (${CMAKE_VERSION} VERSION_GREATER "3.8") #For cmake >= 3.9 INTERPROCEDURAL_OPTIMIZATION behaviour we need to explicitly #set the cmake policy version number - cmake_policy(VERSION 3.9) + cmake_policy(VERSION 3.9) # If we are using verison < 3.9 then setting INTERPROCEDURAL_OPTIMIZATION # has no effect unless an Intel compiler is used @@ -29,13 +29,13 @@ else () endif() if (NOT ENABLE_VPR_GRAPHIC_CXX_FLAG) - # Add a flag to notify compiler not to consider graphic-related source codes + # Add a flag to notify compiler not to consider graphic-related source codes set (DISABLE_GRAPHIC_FLAGS "-DNO_GRAPHICS") set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${DISABLE_GRAPHIC_FLAGS}") message(STATUS "Add flags to disable graphics in VPR compilation: ${DISABLE_GRAPHIC_FLAGS}") endif() -# We need readline to compile +# We need readline to compile find_package(Readline REQUIRED) #Collect the source files @@ -65,12 +65,14 @@ if (ENABLE_VPR_GRAPHIC_CXX_FLAG) libarchfpga X11 libvtrutil - readline) -else () + readline + libini) +else () target_link_libraries(libvpr libarchfpga libvtrutil - readline) + readline + libini) endif() #Create the executables From 438b592a8a92d1e0c0ebdb8a106c62957b9f80fc Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 27 Sep 2019 14:00:27 -0600 Subject: [PATCH 239/482] Appended VPR to genereate INI File --- .../verilog/verilog_formality_autodeck.c | 316 +++++++++++------- 1 file changed, 187 insertions(+), 129 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index 0be59a137..33f587a75 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -10,6 +10,8 @@ #include #include #include +#define MINI_CASE_SENSITIVE +#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -39,82 +41,81 @@ #include "verilog_routing.h" #include "verilog_tcl_utils.h" -static void searching_used_latch(FILE *fp, t_pb *pb, int pb_index, char *chomped_circuit_name, char *inst_name) -{ +mINI::INIStructure ini; + +static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){ int i, j; - // char* tmp = NULL; + char WriteBuffer[200]; + char INI_lbl[100]; +// char* tmp = NULL; const t_pb_type *pb_type; t_mode *mode; - t_pb_graph_node *node; - // char* index = NULL; + t_pb_graph_node * node; +// char* index = NULL; pb_type = pb->pb_graph_node->pb_type; node = pb->pb_graph_node->physical_pb_graph_node; mode = &pb_type->modes[pb->mode]; - // tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index))))); - // tmp = ff_hierarchy; - // index = my_strcat("_", my_strcat(my_itoa(pb_index), "_")); +// tmp = (char*) my_malloc(sizeof(1 + (strlen(ff_hierarchy) + 1 + strlen(my_strcat(pb_type->name, index))))); +// tmp = ff_hierarchy; +// index = my_strcat("_", my_strcat(my_itoa(pb_index), "_")); - if (pb_type->num_modes > 0) - { - for (i = 0; i < mode->num_pb_type_children; i++) - { - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) - { - // if(strcmp(pb_type->name, mode->name) != 0) - // tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index))); - if (pb->child_pbs[i][j].name != NULL) + if (pb_type->num_modes > 0) { + for (i = 0; i < mode->num_pb_type_children; i++) { + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { +// if(strcmp(pb_type->name, mode->name) != 0) +// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->name, index))); + if(pb->child_pbs[i][j].name != NULL) searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name); } } - } - else if ((pb_type->class_type == LATCH_CLASS) && (pb->name)) - { - // tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_")))); + } else if((pb_type->class_type == LATCH_CLASS) && (pb->name)){ +// tmp = my_strcat(tmp, my_strcat("/", my_strcat(pb_type->physical_pb_type_name, my_strcat(index, "/dff_0_")))); fprintf(fp, "set_user_match r:/WORK/%s/%s_reg i:/WORK/%s/%sdff_0 -type cell -noninverted\n", chomped_circuit_name, - pb->name, - inst_name, - gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node)); + pb->name, + inst_name, + gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node) ); + sprintf(WriteBuffer, "%s/%sdff_0 ", + inst_name, gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node)); + + sprintf(INI_lbl, "%s_reg", pb->name); + ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; } //free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp return; } -static void clb_iteration(FILE *fp, char *chomped_circuit_name, int h) -{ - t_pb *pb; - char *inst_name = NULL; +static void clb_iteration(FILE *fp, char* chomped_circuit_name, int h){ + t_pb* pb; + char* inst_name = NULL; const t_pb_type *pb_type; t_mode *mode; int i, j, x_pos, y_pos; - char *grid_x = NULL; - char *grid_y = NULL; + char* grid_x = NULL; + char* grid_y = NULL; x_pos = block[h].x; y_pos = block[h].y; - pb = (t_pb *)block[h].pb; + pb = (t_pb*) block[h].pb; pb_type = pb->pb_graph_node->pb_type; mode = &pb_type->modes[pb->mode]; - grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_")); + grid_x = my_strcat("_", my_strcat(my_itoa(x_pos), "_")); grid_y = my_strcat("_", my_strcat(my_itoa(y_pos), "_")); - if (strcmp(pb_type->name, FILL_TYPE->name) == 0) - { - inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid", my_strcat(grid_x, my_strcat(grid_y, "/"))))))); - if (pb_type->num_modes > 0) - { - for (i = 0; i < mode->num_pb_type_children; i++) - { + + if (strcmp(pb_type->name, FILL_TYPE->name) == 0) { + inst_name = my_strcat(chomped_circuit_name, my_strcat(formal_verification_top_postfix, my_strcat("/", my_strcat(formal_verification_top_module_uut_name, my_strcat("/grid",my_strcat(grid_x, my_strcat(grid_y, "/" ))))))); + if (pb_type->num_modes > 0) { + for (i = 0; i < mode->num_pb_type_children; i++) { inst_name = my_strcat(inst_name, my_strcat("grid_", my_strcat(pb_type->name, my_strcat("_", my_strcat(my_itoa(i), "_"))))); - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) - { + for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { /* If child pb is not used but routing is used, I must print things differently */ - if ((pb->child_pbs[i] != NULL) && (pb->child_pbs[i][j].name != NULL)) - { + if ((pb->child_pbs[i] != NULL) + && (pb->child_pbs[i][j].name != NULL)) { searching_used_latch(fp, &pb->child_pbs[i][j], j, chomped_circuit_name, inst_name); } } @@ -124,14 +125,29 @@ static void clb_iteration(FILE *fp, char *chomped_circuit_name, int h) return; } -static void formality_include_user_defined_verilog_netlists(FILE *fp, - t_spice spice) -{ +static void match_registers(FILE *fp, char* chomped_circuit_name) { + int h; + + for(h = 0; h < copy_nb_clusters; h++) + clb_iteration(fp, chomped_circuit_name, h); +/* for(h = 0; h < copy_nb_clusters; h++){ + free_cb(copy_clb[h].pb); + free(copy_clb[h].name); + free(copy_clb[h].nets); + free(copy_clb[h].pb); + }*/ +// free(copy_clb); +// free(block); + return; +} + +static +void formality_include_user_defined_verilog_netlists(FILE* fp, + t_spice spice) { int i; /* A valid file handler*/ - if (NULL == fp) - { + if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); @@ -139,16 +155,12 @@ static void formality_include_user_defined_verilog_netlists(FILE *fp, } /* Include user-defined sub-circuit netlist */ - for (i = 0; i < spice.num_include_netlist; i++) - { - if (0 == spice.include_netlists[i].included) - { + for (i = 0; i < spice.num_include_netlist; i++) { + if (0 == spice.include_netlists[i].included) { assert(NULL != spice.include_netlists[i].path); - fprintf(fp, "%s \n", spice.include_netlists[i].path); + fprintf(fp, "%s ", spice.include_netlists[i].path); spice.include_netlists[i].included = 1; - } - else - { + } else { assert(1 == spice.include_netlists[i].included); } } @@ -156,102 +168,148 @@ static void formality_include_user_defined_verilog_netlists(FILE *fp, return; } -void write_formality_script(t_syn_verilog_opts fpga_verilog_opts, - char *fm_dir_formatted, - char *src_dir_formatted, - char *chomped_circuit_name, - t_spice spice) -{ - int iblock, h; - char *formScriptfp = NULL; - char *benchmark_path = NULL; - char *original_output_name = NULL; - /* int output_length; */ - /* int pos; */ - FILE *fp = NULL; +void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, + char* fm_dir_formatted, + char* src_dir_formatted, + char* chomped_circuit_name, + t_spice spice){ + int iblock, i, FileCounter=0; + char* formality_script_file_name = NULL; + char* benchmark_path = NULL; + char* original_output_name = NULL; + char WriteBuffer[200]; + char INI_lbl[20]; +/* int output_length; */ +/* int pos; */ + FILE* fp = NULL; - if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) - { + if(TRUE == fpga_verilog_opts.print_autocheck_top_testbench) benchmark_path = fpga_verilog_opts.reference_verilog_benchmark_file; - } else - { benchmark_path = "Insert verilog benchmark path"; - } - formScriptfp = my_strcat(fm_dir_formatted, - my_strcat(chomped_circuit_name, - formality_script_name_postfix)); - fp = fopen(formScriptfp, "w"); - if (NULL == fp) - { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create formality script %s", - __FILE__, __LINE__, formScriptfp); - exit(1); - } + formality_script_file_name = my_strcat(fm_dir_formatted, my_strcat(chomped_circuit_name, formality_script_name_postfix)); + fp = fopen(formality_script_file_name, "w"); + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create formality script %s", + __FILE__, __LINE__, formality_script_file_name); + exit(1); + } /* Load Verilog benchmark as reference */ - fprintf(fp, "%s\n\n", benchmark_path); + fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path); + ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; /* Set reference top */ - fprintf(fp, "%s\n\n", chomped_circuit_name); + fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name); + ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; /* Load generated verilog as implemnetation */ - fprintf(fp, "%s%s%s\n", src_dir_formatted, chomped_circuit_name, + fprintf(fp, "read_verilog -container i -libname WORK -05 { "); + fprintf(fp, "%s%s%s ", src_dir_formatted, + chomped_circuit_name, + verilog_top_postfix); + sprintf(WriteBuffer, "%s%s%s", src_dir_formatted, chomped_circuit_name, verilog_top_postfix); + sprintf(INI_lbl, "impl_netlist_%02d",FileCounter++); + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; - fprintf(fp, "%s%s%s\n", src_dir_formatted, - chomped_circuit_name, - formal_verification_verilog_file_postfix); + fprintf(fp, "%s%s%s ", src_dir_formatted, + chomped_circuit_name, + formal_verification_verilog_file_postfix); + sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, + chomped_circuit_name, formal_verification_verilog_file_postfix); + sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; init_include_user_defined_verilog_netlists(spice); - formality_include_user_defined_verilog_netlists(fp, spice); - fprintf(fp, "%s%s%s\n", src_dir_formatted, - default_rr_dir_name, - routing_verilog_file_name); - fprintf(fp, "%s%s%s\n", src_dir_formatted, - default_lb_dir_name, - logic_block_verilog_file_name); - fprintf(fp, "%s%s%s\n", src_dir_formatted, - default_submodule_dir_name, - submodule_verilog_file_name); - fprintf(fp, "\n"); + // formality_include_user_defined_verilog_netlists(fp, spice); - /* Set implementation top */ - fprintf(fp, "%s\n", my_strcat(chomped_circuit_name, formal_verification_top_postfix)); - /* Run matching */ - fprintf(fp, "\n"); - /* Add manual matching for the outputs */ - for (iblock = 0; iblock < num_logical_blocks; iblock++) - { - original_output_name = NULL; - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) - { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) || (VPACK_OUTPAD == logical_block[iblock].type)); - if (VPACK_OUTPAD == logical_block[iblock].type) - { - /* output_length = strlen(logical_block[iblock].name); */ - original_output_name = logical_block[iblock].name + 4; - /* printf("%s", original_output_name); */ - // fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n", - fprintf(fp, "/WORK/%s/%s /WORK/%s/%s[0]\n", - chomped_circuit_name, - original_output_name, - my_strcat(chomped_circuit_name, formal_verification_top_postfix), - my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); - } + /* Include user-defined sub-circuit netlist */ + for (i = 0; i < spice.num_include_netlist; i++) { + if (0 == spice.include_netlists[i].included) { + assert(NULL != spice.include_netlists[i].path); + fprintf(fp, "%s ", spice.include_netlists[i].path); + sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); + ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; + spice.include_netlists[i].included = 1; + } else { + assert(1 == spice.include_netlists[i].included); } } - for (h = 0; h < copy_nb_clusters; h++) - clb_iteration(fp, chomped_circuit_name, h); + fprintf(fp, "%s%s%s ", src_dir_formatted, + default_rr_dir_name, + routing_verilog_file_name); + sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, + default_rr_dir_name, + routing_verilog_file_name); + sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + fprintf(fp, "%s%s%s ", src_dir_formatted, + default_lb_dir_name, + logic_block_verilog_file_name); + sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, + default_lb_dir_name, + logic_block_verilog_file_name); + sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + fprintf(fp, "%s%s%s ", src_dir_formatted, + default_submodule_dir_name, + submodule_verilog_file_name); + sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, + default_submodule_dir_name, + submodule_verilog_file_name); + sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + fprintf(fp, "}\n"); + /* Set implementation top */ + fprintf(fp, "set_top i:/WORK/%s\n", my_strcat(chomped_circuit_name, + formal_verification_top_postfix)); + sprintf(WriteBuffer, "%s", my_strcat(chomped_circuit_name, + formal_verification_top_postfix)); + ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; + + /* Run matching */ + fprintf(fp, "match\n"); + /* Add manual matching for the outputs */ + for (iblock = 0; iblock < num_logical_blocks; iblock++) { + original_output_name = NULL; + if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { + /* Make sure We find the correct logical block !*/ + assert((VPACK_INPAD == logical_block[iblock].type) + ||(VPACK_OUTPAD == logical_block[iblock].type)); + if(VPACK_OUTPAD == logical_block[iblock].type){ + /* output_length = strlen(logical_block[iblock].name); */ + original_output_name = logical_block[iblock].name + 4; + /* printf("%s", original_output_name); */ + fprintf(fp, "set_user_match r:/WORK/%s/%s i:/WORK/%s/%s[0] -type port -noninverted\n", + chomped_circuit_name, + original_output_name, + my_strcat(chomped_circuit_name, formal_verification_top_postfix), + my_strcat(logical_block[iblock].name, + formal_verification_top_module_port_postfix)); + + sprintf(WriteBuffer, "%s/%s[0]", + my_strcat(chomped_circuit_name, formal_verification_top_postfix), + my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); + + sprintf(INI_lbl, "%s", original_output_name); + ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; + } + } + } + match_registers(fp, chomped_circuit_name); /* Run verification */ - fprintf(fp, "\n"); + fprintf(fp, "verify\n"); /* Script END */ fclose(fp); + mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); + file.generate(ini, true); return; } From d269472dafe64817ef4cdca21d4426612b5345e5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 27 Sep 2019 14:00:57 -0600 Subject: [PATCH 240/482] Updated formality python script --- openfpga_flow/misc/formality_template.tcl | 20 ++++++ openfpga_flow/misc/modelsim_template.j2 | 8 --- .../{run_modelsim.py => run_formality.py} | 67 ++++++++++++------- 3 files changed, 63 insertions(+), 32 deletions(-) create mode 100644 openfpga_flow/misc/formality_template.tcl delete mode 100644 openfpga_flow/misc/modelsim_template.j2 rename openfpga_flow/scripts/{run_modelsim.py => run_formality.py} (50%) diff --git a/openfpga_flow/misc/formality_template.tcl b/openfpga_flow/misc/formality_template.tcl new file mode 100644 index 000000000..2eb607ae9 --- /dev/null +++ b/openfpga_flow/misc/formality_template.tcl @@ -0,0 +1,20 @@ +# = = = = = = = = = = = = = = = = = = = = = = +# Auto generated using OpenFPGA +# = = = = = = = = = = = = = = = = = = = = = = + +# Benchmark Source Files +read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN_FILES} } +set_top r:${SOURCE_TOP_MODULE} + +# Benchmark Implementation Files +read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN_FILES} } +set_top i:${IMPL_TOP_DIR} + +match +# Port Mapping +${PORT_MAP_LIST} + +# Register Mapping +${REGISTER_MAP_LIST} + +verify diff --git a/openfpga_flow/misc/modelsim_template.j2 b/openfpga_flow/misc/modelsim_template.j2 deleted file mode 100644 index cfa43d11c..000000000 --- a/openfpga_flow/misc/modelsim_template.j2 +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog -container r -libname WORK -05 { ${SOURCE_DESIGN} } -set_top r:${SOURCE_TOP_DIR} -read_verilog -container i -libname WORK -05 { ${IMPL_DESIGN} } - -set_top i:${IMPL_TOP_DIR} -match -${MATCH_MODUEL_LIST} -verify diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_formality.py similarity index 50% rename from openfpga_flow/scripts/run_modelsim.py rename to openfpga_flow/scripts/run_formality.py index e8dca5cb4..f1d781626 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_formality.py @@ -1,10 +1,12 @@ from string import Template import sys import os +import pprint import argparse import subprocess import logging from pprint import pprint +from configparser import ConfigParser # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system @@ -13,55 +15,72 @@ logging.basicConfig(level=logging.INFO, stream=sys.stdout, format='%(levelname)s (%(threadName)10s) - %(message)s') logger = logging.getLogger('Modelsim_run_log') +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Parse commandline arguments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = parser = argparse.ArgumentParser() parser.add_argument('files', nargs='+') -parser.add_argument('--modelsim_template', type=str, +parser.add_argument('--formality_template', type=str, help="Modelsim verification template file") parser.add_argument('--run_sim', action="store_true", help="Execute generated script in formality") args = parser.parse_args() - -if not args.modelsim_template: +# Consider default formality script template +if not args.formality_template: task_script_dir = os.path.dirname(os.path.abspath(__file__)) - args.modelsim_template = os.path.join(task_script_dir, os.pardir, - "misc", "modelsim_template.j2") + args.formality_template = os.path.join(task_script_dir, os.pardir, + "misc", "formality_template.tcl") -args.modelsim_template = os.path.abspath(args.modelsim_template) +args.formality_template = os.path.abspath(args.formality_template) def main(): for eachFile in args.files: eachFile = os.path.abspath(eachFile) - directory = os.path.dirname(eachFile) - os.chdir(directory) - with open(eachFile, 'r') as fp: - lines = fp.read().split("\n") - SplitL = [indx for indx, eachL in enumerate(lines) if eachL == ""] - SplitL = list(zip([0] + SplitL[:-1], SplitL)) - for indx, eachSection in enumerate(SplitL): - SplitL[indx] = list(filter(None, lines[slice(*eachSection)])) + pDir = os.path.dirname(eachFile) + os.chdir(pDir) - match_str = "set_user_match r:%s i:%s -type port -noninverted" - lables = {"SOURCE_DESIGN": " ".join(SplitL[0]), - "SOURCE_TOP_DIR": "/WORK/" + " ".join(SplitL[1]), - "IMPL_DESIGN": " ".join(SplitL[2]), - "IMPL_TOP_DIR": "/WORK/" + " ".join(SplitL[3]), - "MATCH_MODUEL_LIST": "\n".join([match_str % tuple(eachPort.split()) for eachPort in SplitL[4]]) - } + config = ConfigParser() + config.read(eachFile) - tmpl = Template(open(args.modelsim_template, encoding='utf-8').read()) - with open("Output.tcl", 'w', encoding='utf-8') as tclout: + port_map = ("set_user_match r:%s/%%s i:/WORK/%%s -type port -noninverted" % ( + "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"] + )) + cell_map = ("set_user_match r:%s/%%s i:/WORK/%%s -type cell -noninverted" % ( + "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"] + )) + + lables = { + "SOURCE_DESIGN_FILES": config["BENCHMARK_INFO"]["benchmark_netlist"], + "SOURCE_TOP_MODULE": "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"], + + "IMPL_DESIGN_FILES": " ".join( + [val for key, val in config["FPGA_INFO"].items() + if "impl_netlist_" in key]), + "IMPL_TOP_DIR": "/WORK/" + config["FPGA_INFO"]["impl_top_module"], + + "PORT_MAP_LIST": "\n".join([port_map % + ele for ele in + config["PORT_MATCHING"].items()]), + "REGISTER_MAP_LIST": "\n".join([cell_map % + ele for ele in + config["REGISTER_MATCH"].items()]), + } + + tmpl = Template(open(args.formality_template, encoding='utf-8').read()) + with open(os.path.join(pDir, "Output.tcl"), 'w', encoding='utf-8') as tclout: tclout.write(tmpl.substitute(lables)) if args.run_sim: formality_run_string = ["formality", "-file", "Output.tcl"] - run_command("Modelsim run", "modelsim_run.log", formality_run_string) + run_command("Formality Run", "formality_run.log", formality_run_string) else: with open("Output.tcl", 'r', encoding='utf-8') as tclout: print(tclout.read()) def run_command(taskname, logfile, command, exit_if_fail=True): + os.chdir(os.pardir) logger.info("Launching %s " % taskname) with open(logfile, 'w+') as output: try: From 167778cf57bf0f486dd6578ca82fbe3e75baee26 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Sep 2019 16:05:47 -0600 Subject: [PATCH 241/482] refactoring MUX Verilog instanciation in Switch block --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 60 ++++++++++++++- vpr7_x2p/vpr/SRC/device/mux_graph.h | 11 +++ vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 11 ++- .../SRC/fpga_x2p/verilog/verilog_routing.c | 76 ++++++++++++++----- 4 files changed, 133 insertions(+), 25 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 91105ddbf..608ffa4b5 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -65,6 +65,14 @@ MuxGraph::mem_range MuxGraph::memories() const { return vtr::make_range(mem_ids_.begin(), mem_ids_.end()); } +std::vector MuxGraph::levels() const { + std::vector graph_levels; + for (size_t lvl = 0; lvl < num_levels(); ++lvl) { + graph_levels.push_back(lvl); + } + return graph_levels; +} + /************************************************** * Public Accessors: Data query *************************************************/ @@ -158,6 +166,14 @@ size_t MuxGraph::num_memory_bits() const { return mem_ids_.size(); } +/* Find the number of SRAMs at a level in the MUX graph */ +size_t MuxGraph::num_memory_bits_at_level(const size_t& level) const { + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_level(level)); + VTR_ASSERT_SAFE(valid_mux_graph()); + return mem_lookup_[level].size(); +} + /* Find the number of nodes at a given level in the MUX graph */ size_t MuxGraph::num_nodes_at_level(const size_t& level) const { /* validate the level numbers */ @@ -310,6 +326,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { } /* Not found, we add a memory bit and record in the mem-to-mem map */ MuxMemId mem_subgraph = mux_graph.add_mem(); + mux_graph.set_mem_level(mem_subgraph, 0); mem2mem_map[mem_origin] = mem_subgraph; /* configure the edge */ mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem_subgraph; @@ -317,6 +334,7 @@ MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { /* Since the graph is finalized, it is time to build the fast look-up */ mux_graph.build_node_lookup(); + mux_graph.build_mem_lookup(); return mux_graph; } @@ -519,11 +537,20 @@ MuxMemId MuxGraph::add_mem() { MuxMemId mem = MuxMemId(mem_ids_.size()); /* Push to the node list */ mem_ids_.push_back(mem); + mem_levels_.push_back(size_t(-1)); /* Resize the other node-related vectors */ return mem; } +/* Configure the level of a memory */ +void MuxGraph::set_mem_level(const MuxMemId& mem, const size_t& level) { + /* Make sure we have valid edge and mem */ + VTR_ASSERT( valid_mem_id(mem) ); + + mem_levels_[mem] = level; +} + /* Link an edge to a memory bit */ void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) { /* Make sure we have valid edge and mem */ @@ -593,8 +620,11 @@ void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, num_mems_per_level = 1; } /* Number of memory bits is definite, add them */ - for (size_t i = 0; i < num_mems_per_level * num_levels; ++i) { - add_mem(); + for (size_t ilvl = 0; ilvl < num_levels; ++ilvl) { + for (size_t imem = 0; imem < num_mems_per_level; ++imem) { + MuxMemId mem = add_mem(); + mem_levels_[mem] = ilvl; + } } /* Create a fast node lookup locally. @@ -747,6 +777,7 @@ void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, /* Create a memory bit*/ MuxMemId mem = add_mem(); + mem_levels_[mem] = 0; /* Link the edge to a memory bit */ set_edge_mem_id(edge, mem); } @@ -863,6 +894,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, /* Since the graph is finalized, it is time to build the fast look-up */ build_node_lookup(); + build_mem_lookup(); /* For fracturable LUTs, we need to add more outputs to the MUX graph */ if ( (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) @@ -895,10 +927,34 @@ void MuxGraph::build_node_lookup() { } } +/* Build fast mem lookup */ +void MuxGraph::build_mem_lookup() { + /* Invalidate the mem lookup if necessary */ + invalidate_mem_lookup(); + + /* Find the maximum number of levels */ + size_t num_levels = 0; + for (auto mem : memories()) { + num_levels = std::max((int)mem_levels_[mem], (int)num_levels); + } + + /* Resize mem_lookup */ + mem_lookup_.resize(num_levels + 1); + for (auto mem : memories()) { + /* Categorize mem nodes into mem_lookup */ + mem_lookup_[mem_levels_[mem]].push_back(mem); + } +} + /* Invalidate (empty) the node fast lookup*/ void MuxGraph::invalidate_node_lookup() { node_lookup_.clear(); } + +/* Invalidate (empty) the mem fast lookup*/ +void MuxGraph::invalidate_mem_lookup() { + mem_lookup_.clear(); +} /************************************************** * Private validators diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 856c7e0b1..ddb80e6f4 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -62,6 +62,7 @@ class MuxGraph { std::vector non_input_nodes() const; edge_range edges() const; mem_range memories() const; + std::vector levels() const; public: /* Public accessors: Data query */ /* Find the number of inputs in the MUX graph */ size_t num_inputs() const; @@ -76,6 +77,8 @@ class MuxGraph { size_t num_node_levels() const; /* Find the number of SRAMs in the MUX graph */ size_t num_memory_bits() const; + /* Find the number of SRAMs at a level in the MUX graph */ + size_t num_memory_bits_at_level(const size_t& level) const; /* Find the number of nodes at a given level in the MUX graph */ size_t num_nodes_at_level(const size_t& level) const; /* Find the level of a node */ @@ -112,6 +115,8 @@ class MuxGraph { MuxEdgeId add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node); /* Add a memory bit to the MuxGraph */ MuxMemId add_mem(); + /* Configure the level of a memory */ + void set_mem_level(const MuxMemId& mem, const size_t& level); /* Link an edge to a mem */ void set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem); private: /* Private mutators : graph builders */ @@ -130,6 +135,8 @@ class MuxGraph { const CircuitModelId& circuit_model); /* Build fast node lookup */ void build_node_lookup(); + /* Build fast mem lookup */ + void build_mem_lookup(); private: /* Private validators */ /* valid ids */ bool valid_node_id(const MuxNodeId& node) const; @@ -141,6 +148,7 @@ class MuxGraph { /* validate/invalidate node lookup */ bool valid_node_lookup() const; void invalidate_node_lookup(); + void invalidate_mem_lookup(); /* validate graph */ bool valid_mux_graph() const; private: /* Internal data */ @@ -161,10 +169,13 @@ class MuxGraph { vtr::vector edge_inv_mem_; /* if the edge is controlled by an inverted output of a memory bit */ vtr::vector mem_ids_; /* ids of configuration memories */ + vtr::vector mem_levels_; /* ids of configuration memories */ /* fast look-up */ typedef std::vector>> NodeLookup; mutable NodeLookup node_lookup_; /* [num_levels][num_types][num_nodes_per_level] */ + typedef std::vector> MemLookup; + mutable MemLookup mem_lookup_; /* [num_levels][num_mems_per_level] */ }; #endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 6a6d169a9..53e71f1f8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -283,6 +283,7 @@ size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib, const MuxGraph& mux_graph, const e_sram_orgz& sram_orgz_type) { size_t num_config_bits = 0; + switch (sram_orgz_type) { case SPICE_SRAM_MEMORY_BANK: case SPICE_SRAM_SCAN_CHAIN: @@ -296,10 +297,16 @@ size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib, exit(1); } - if (true == circuit_lib.mux_use_local_encoder(mux_model)) { - num_config_bits = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits()); + if (false == circuit_lib.mux_use_local_encoder(mux_model)) { + return num_config_bits; } + num_config_bits = 0; + /* Multiplexer local encoders are applied to memory bits at each stage */ + for (const auto& lvl : mux_graph.levels()) { + num_config_bits += find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); + } + return num_config_bits; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 5e0d99f9c..19a006e41 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -2328,7 +2329,7 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, t_rr_node* cur_rr_node, const std::vector& drive_rr_nodes, const size_t& switch_index, - const bool& is_explicit_mapping) { + const bool& use_explicit_mapping) { /* Check the file handler*/ check_file_handler(fp); @@ -2341,11 +2342,9 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Find the input size of the implementation of a routing multiplexer */ size_t datapath_mux_size = drive_rr_nodes.size(); - size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, mux_model, datapath_mux_size); - VTR_ASSERT(true == valid_mux_implementation_num_inputs(impl_mux_size)); /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, impl_mux_size); + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); /* Find the module name of the multiplexer and try to find it in the module manager */ @@ -2365,19 +2364,12 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); inbus_port.set_width(datapath_mux_size); - /* Create the path of the input of multiplexer in the hierarchy - * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! - */ - std::string mux_input_hie_path = std::string(rr_sb.gen_sb_verilog_instance_name()) + std::string("/") - + mux_module_name + std::string("_") - + std::to_string(mux_instance_id) + std::string("_/in"); - cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); - /* Generate input ports that are wired to the input bus of the routing multiplexer */ std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); /* Connect input ports to bus */ - print_verilog_comment(fp, std::string("----- A local bus wire for multiplexer inputs -----")); + print_verilog_comment(fp, std::string("----- BEGIN A local bus wire for multiplexer inputs -----")); fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; + print_verilog_comment(fp, std::string("----- END A local bus wire for multiplexer inputs -----")); fp << std::endl; /* Find the number of reserved configuration bits for the routing multiplexer */ @@ -2387,32 +2379,66 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); /* Print the configuration bus for the routing multiplexers */ - print_verilog_comment(fp, std::string("----- Local wires to group configuration ports -----")); + print_verilog_comment(fp, std::string("----- BEGIN Local wires to group configuration ports -----")); print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, datapath_mux_size, mux_instance_id, mux_num_reserved_config_bits, mux_num_config_bits); + print_verilog_comment(fp, std::string("----- END Local wires to group configuration ports -----")); fp << std::endl; /* Dump ports visible only during formal verification */ - print_verilog_comment(fp, std::string("----- Local wires used in only formal verification purpose -----")); + print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); /* Print the SRAM configuration ports for formal verification */ + /* TODO: align with the port width of formal verification port of SB module */ print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, datapath_mux_size, mux_instance_id, mux_num_config_bits); print_verilog_endif(fp); + print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); fp << std::endl; - /* TODO: Instanciate the MUX Module */ - /* TODO: create port-to-port map */ + /* Instanciate the MUX Module */ + /* Create port-to-port map */ + std::map mux_port2port_name_map; + /* Link input bus port to Switch Block inputs */ + std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == mux_model_input_ports.size()); + /* Use the port name convention in the circuit library */ + mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_input_ports[0])] = inbus_port; + /* Link output port to Switch Block outputs */ + std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == mux_model_output_ports.size()); + /* Use the port name convention in the circuit library */ + mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_output_ports[0])] = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); + /* Link SRAM port to different configuraton port for the routing multiplexer * Different design technology requires different configuration bus! - dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, - num_mux_conf_bits, is_explicit_mapping); */ - /* TODO: Print an instance of the MUX Module */ + std::vector mux_model_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); + VTR_ASSERT( 1 == mux_model_sram_ports.size() ); + /* For the regular SRAM port, module port use the same name */ + std::string mux_module_sram_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]); + BasicPort mux_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + mux_num_config_bits); + mux_port2port_name_map[mux_module_sram_port_name] = mux_config_port; + + /* For the inverted SRAM port */ + std::string mux_module_sram_inv_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]) + std::string("_inv"); + BasicPort mux_config_inv_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + mux_num_config_bits); + mux_port2port_name_map[mux_module_sram_inv_port_name] = mux_config_inv_port; + + /* Print an instance of the MUX Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a routing multiplexer -----")); + print_verilog_module_instance(fp, module_manager, sb_module, mux_module, mux_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of a routing multiplexer -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(sb_module, mux_module); /* TODO: Instanciate memory modules */ switch (circuit_lib.design_tech_type(mux_model)) { @@ -2443,6 +2469,14 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, "(File:%s,[LINE%d])Invalid design technology for circuit model (%s)!\n", __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); } + + /* Create the path of the input of multiplexer in the hierarchy + * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! + */ + std::string mux_input_hie_path = std::string(rr_sb.gen_sb_verilog_instance_name()) + std::string("/") + + mux_module_name + std::string("_") + + std::to_string(mux_instance_id) + std::string("_/in"); + cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); } From a93d7e57f7d96f7d6dcebbb38f22256a4dfa64c4 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 27 Sep 2019 16:53:00 -0600 Subject: [PATCH 242/482] Scan chain support in directlist --- vpr7_x2p/libarchfpga/SRC/physical_types.h | 4 + vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c | 74 ++++++++ vpr7_x2p/libarchfpga/SRC/spice_types.h | 14 ++ vpr7_x2p/vpr/SRC/base/vpr_types.h | 4 + .../verilog/verilog_top_netlist_utils.c | 163 ++++++++++++++++-- vpr7_x2p/vpr/SRC/util/vpr_utils.c | 5 +- 6 files changed, 250 insertions(+), 14 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/physical_types.h b/vpr7_x2p/libarchfpga/SRC/physical_types.h index 81de09866..e9fb0745e 100644 --- a/vpr7_x2p/libarchfpga/SRC/physical_types.h +++ b/vpr7_x2p/libarchfpga/SRC/physical_types.h @@ -924,6 +924,10 @@ typedef struct s_direct_inf { int y_offset; int z_offset; int line; + /* Aurelien: point to point support in direct connection from directlist */ + enum e_point2point_interconnection_type interconnection_type; + enum e_point2point_interconnection_dir x_dir; + enum e_point2point_interconnection_dir y_dir; /* Xifan Tang: FPGA-SPICE support */ char* spice_model_name; t_spice_model* spice_model; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c index d852e07dd..55a05bba9 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c @@ -3578,6 +3578,9 @@ static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs, const char *direct_name; const char *from_pin_name; const char *to_pin_name; + const char *point2point_type; + const char *x_dir; + const char *y_dir; ezxml_t Node; @@ -3632,6 +3635,77 @@ static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs, ezxml_set_attr(Node, "y_offset", NULL); ezxml_set_attr(Node, "z_offset", NULL); + // Aurelien: Read point to point connection parameters + if((!FindProperty(Node, "interconnection_type", FALSE)) || + (0 == strcmp(FindProperty(Node, "interconnection_type", FALSE), "NONE"))) { + (*Directs)[i].interconnection_type = NO_P2P; + } else if(0 == strcmp(FindProperty(Node, "interconnection_type", FALSE), "column")) { + (*Directs)[i].interconnection_type = P2P_DIRECT_COLUMN; + } else if(0 == strcmp(FindProperty(Node, "interconnection_type", FALSE), "row")) { + (*Directs)[i].interconnection_type = P2P_DIRECT_ROW; + } else { + (*Directs)[i].interconnection_type = NUM_POINT2POINT_INTERCONNECT_TYPE; + vpr_printf(TIO_MESSAGE_ERROR, + "Invalid point to point connection '%s' in directlist. '%s' value should be '%s', '%s' or '%s' !\n", + (*Directs)[i].name, + "interconnection_type", + "column", + "row", + "NONE" ); + exit(1); + } + if((P2P_DIRECT_COLUMN == (*Directs)[i].interconnection_type) || + (P2P_DIRECT_ROW == (*Directs)[i].interconnection_type)){ + if(0 == strcmp(FindProperty(Node, "x_dir", TRUE), "positive")){ + (*Directs)[i].x_dir = POSITIVE_DIR; + } else if(0 == strcmp(FindProperty(Node, "x_dir", TRUE), "negative")){ + (*Directs)[i].x_dir = NEGATIVE_DIR; + } else { + (*Directs)[i].x_dir = NUM_POINT2POINT_INTERCONNECT_DIR; + vpr_printf(TIO_MESSAGE_ERROR, + "Invalid point to point connection '%s' in directlist. '%s' value should be '%s' or '%s' !\n", + (*Directs)[i].name, + "x_dir", + "positive", + "negative" ); + } + if(0 == strcmp(FindProperty(Node, "y_dir", TRUE), "positive")){ + (*Directs)[i].y_dir = POSITIVE_DIR; + } else if(0 == strcmp(FindProperty(Node, "y_dir", TRUE), "negative")){ + (*Directs)[i].y_dir = NEGATIVE_DIR; + } else { + (*Directs)[i].y_dir = NUM_POINT2POINT_INTERCONNECT_DIR; + vpr_printf(TIO_MESSAGE_ERROR, + "Invalid point to point connection '%s' in directlist. '%s' value should be '%s' or '%s' !\n", + (*Directs)[i].name, + "y_dir", + "positive", + "negative" ); + } + } else { + if(NULL == FindProperty(Node, "x_dir", FALSE)){ + (*Directs)[i].x_dir = NUM_POINT2POINT_INTERCONNECT_DIR; + } else if(0 == strcmp(FindProperty(Node, "x_dir", FALSE), "positive")){ + (*Directs)[i].x_dir = POSITIVE_DIR; + } else if(0 == strcmp(FindProperty(Node, "x_dir", FALSE), "negative")){ + (*Directs)[i].x_dir = NEGATIVE_DIR; + } else { + (*Directs)[i].x_dir = NUM_POINT2POINT_INTERCONNECT_DIR; + } + if(NULL == FindProperty(Node, "y_dir", FALSE)){ + (*Directs)[i].y_dir = NUM_POINT2POINT_INTERCONNECT_DIR; + } else if(0 == strcmp(FindProperty(Node, "y_dir", FALSE), "positive")){ + (*Directs)[i].y_dir = POSITIVE_DIR; + } else if(0 == strcmp(FindProperty(Node, "y_dir", FALSE), "negative")){ + (*Directs)[i].y_dir = NEGATIVE_DIR; + } else { + (*Directs)[i].y_dir = NUM_POINT2POINT_INTERCONNECT_DIR; + } + } + ezxml_set_attr(Node, "x_dir", NULL); + ezxml_set_attr(Node, "y_dir", NULL); + ezxml_set_attr(Node, "interconnection_type", NULL); + /* Check that the direct chain connection is not zero in both direction */ if ((*Directs)[i].x_offset == 0 && (*Directs)[i].y_offset == 0) { vpr_printf(TIO_MESSAGE_ERROR, diff --git a/vpr7_x2p/libarchfpga/SRC/spice_types.h b/vpr7_x2p/libarchfpga/SRC/spice_types.h index 542f5bcbd..26f30b164 100644 --- a/vpr7_x2p/libarchfpga/SRC/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/spice_types.h @@ -5,6 +5,20 @@ #include "linkedlist.h" #include "circuit_library.h" +/* Aurelien: point to point connection */ +enum e_point2point_interconnection_type { + NO_P2P, + P2P_DIRECT_COLUMN, + P2P_DIRECT_ROW, + NUM_POINT2POINT_INTERCONNECT_TYPE +}; + +enum e_point2point_interconnection_dir { + POSITIVE_DIR, + NEGATIVE_DIR, + NUM_POINT2POINT_INTERCONNECT_DIR +}; + /* Xifan TANG: Spice support*/ enum e_spice_tech_lib_type { SPICE_LIB_INDUSTRY, diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 4b039d5c8..820ee7126 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1123,6 +1123,10 @@ typedef struct s_clb_to_clb_directs { t_type_descriptor *to_clb_type; int to_clb_pin_start_index; int to_clb_pin_end_index; + /* Aurelien: point to point support in direct connection from directlist */ + enum e_point2point_interconnection_type interconnection_type; + enum e_point2point_interconnection_dir x_dir; + enum e_point2point_interconnection_dir y_dir; /* Xifan Tang: add useful addition info to this struct */ int x_offset; int y_offset; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index a06b8d35b..0bb9cff78 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -39,6 +39,7 @@ #include "verilog_decoder.h" #include "verilog_top_netlist_utils.h" + /* Local Subroutines declaration */ /******** Subroutines ***********/ @@ -959,7 +960,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, } return; -} +} /* Apply CLB to CLB direct connections to a Verilog netlist */ @@ -990,12 +991,12 @@ void dump_verilog_clb2clb_directs(FILE* fp, */ for (idirect = 0; idirect < num_directs; idirect++) { /* Bypass unmatch types */ - if (grid[ix][iy].type != direct[idirect].from_clb_type) { - continue; - } /* Apply x/y_offset */ to_clb_x = ix + direct[idirect].x_offset; to_clb_y = iy + direct[idirect].y_offset; + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + continue; + } /* see if the destination CLB is in the bound */ if ((FALSE == is_grid_coordinate_in_range(0, nx, to_clb_x)) ||(FALSE == is_grid_coordinate_in_range(0, ny, to_clb_y))) { @@ -1006,21 +1007,157 @@ void dump_verilog_clb2clb_directs(FILE* fp, continue; } */ - /* Check if the to_clb_type matches */ - if (grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) { - continue; - } /* Bypass x/y_offset = 1 * since it may be addressed in Connection blocks if (1 == (x_offset + y_offset)) { continue; } */ - /* Now we can print a direct connection with the spice models */ - dump_verilog_one_clb2clb_direct(fp, - ix, iy, - to_clb_x, to_clb_y, - &direct[idirect]); + + /* Check if the to_clb_type matches */ + if (grid[to_clb_x][to_clb_y].type == direct[idirect].to_clb_type) { + /* Now we can print a direct connection with the spice models */ + dump_verilog_one_clb2clb_direct(fp, + ix, iy, + to_clb_x, to_clb_y, + &direct[idirect]); + /* Check if we can make a point to point connection between direct connection */ + }else if((P2P_DIRECT_COLUMN == direct[idirect].interconnection_type) || + (P2P_DIRECT_ROW == direct[idirect].interconnection_type)){ + /* Check in which case we are to adapt coordinates */ + if((P2P_DIRECT_COLUMN == direct[idirect].interconnection_type) && + (POSITIVE_DIR == direct[idirect].x_dir) && + (POSITIVE_DIR == direct[idirect].y_dir)){ // Bottom to Top on Right + if (grid[ix][iy].type == direct[idirect].from_clb_type) { + to_clb_x = ix + 1; + to_clb_y = ny + 1; + do{ // Find next available type + to_clb_y --; // Scan types from Top to Bottom + if(0 > to_clb_y){ // If scan fails scan the column on the Right until match or no more column + to_clb_x ++; + to_clb_y = ny; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (nx > to_clb_x)); + } + } else if((P2P_DIRECT_COLUMN == direct[idirect].interconnection_type) && + (POSITIVE_DIR == direct[idirect].x_dir) && + (NEGATIVE_DIR == direct[idirect].y_dir)){ // Top to Bottom on Right + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = ix + 1; + to_clb_y = -1; + do{ // Find next available type + to_clb_y ++; // Scan types from Bottom to Top + if(ny < to_clb_y){ // If scan fails scan the column on the Right until match or no more column + to_clb_x ++; + to_clb_y = 0; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (nx >= to_clb_x)); + } + } else if((P2P_DIRECT_COLUMN == direct[idirect].interconnection_type) && + (NEGATIVE_DIR == direct[idirect].x_dir) && + (NEGATIVE_DIR == direct[idirect].y_dir)){ // Top to Bottom on Left + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = ix - 1; + to_clb_y = -1; + do{ // Find next available type + to_clb_y ++; // Scan types from Bottom to Top + if(ny < to_clb_y){ // If scan fails scan the column on the Left until match or no more column + to_clb_x --; + to_clb_y = 0; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (0 <= to_clb_x)); + } + } else if((P2P_DIRECT_COLUMN == direct[idirect].interconnection_type) && + (NEGATIVE_DIR == direct[idirect].x_dir) && + (POSITIVE_DIR == direct[idirect].y_dir)){ // Bottom to Top on Left + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = ix - 1; + to_clb_y = ny + 1; + do{ // Find next available type + to_clb_y --; // Scan types from Top to Bottom + if(0 > to_clb_y){ // If scan fails scan the column on the Left until match or no more column + to_clb_x --; + to_clb_y = ny; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (0 <= to_clb_x)); + } + } else if((P2P_DIRECT_ROW == direct[idirect].interconnection_type) && + (POSITIVE_DIR == direct[idirect].x_dir) && + (POSITIVE_DIR == direct[idirect].y_dir)){ // Left to Right Above + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = nx + 1; + to_clb_y = iy + 1; + do{ // Find next available type + to_clb_x --; // Scan types from Right to Left + if(0 > to_clb_x){ // If scan fails scan the row above until match or no more row + to_clb_x = nx; + to_clb_y ++; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (ny >= to_clb_y)); + } + } else if((P2P_DIRECT_ROW == direct[idirect].interconnection_type) && + (POSITIVE_DIR == direct[idirect].x_dir) && + (NEGATIVE_DIR == direct[idirect].y_dir)){ // Left to Right Below + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = nx + 1; + to_clb_y = iy - 1; + do{ // Find next available type + to_clb_x --; // Scan types from Right to Left + if(0 > to_clb_x){ // If scan fails scan the row below until match or no more row + to_clb_x = nx; + to_clb_y --; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (0 <= to_clb_y)); + } + } else if((P2P_DIRECT_ROW == direct[idirect].interconnection_type) && + (NEGATIVE_DIR == direct[idirect].x_dir) && + (NEGATIVE_DIR == direct[idirect].y_dir)){ // Right to Left Below + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = -1; + to_clb_y = iy - 1; + do{ // Find next available type + to_clb_x ++; // Scan types from Left to Right + if(nx < to_clb_x){ // If scan fails scan the row below until match or no more row + to_clb_x = 0; + to_clb_y --; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (0 <= to_clb_y)); + } + } else if((P2P_DIRECT_ROW == direct[idirect].interconnection_type) && + (NEGATIVE_DIR == direct[idirect].x_dir) && + (POSITIVE_DIR == direct[idirect].y_dir)){ // Right to Left Above + if (grid[ix][iy].type != direct[idirect].from_clb_type) { + to_clb_x = -1; + to_clb_y = iy + 1; + do{ // Find next available type + to_clb_x ++; // Scan types from Left to Right + if(nx < to_clb_x){ // If scan fails scan the row below until match or no more row + to_clb_x = 0; + to_clb_y ++; + } + } while((grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) && + (ny >= to_clb_y)); + } + } + if(grid[to_clb_x][to_clb_y].type == direct[idirect].from_clb_type){ + /* Now we can print a direct connection with the spice models */ + fprintf(fp, " //----- Point to Point from grid_%d__%d_ to grid_%d__%d_ -----\n", ix, iy, + to_clb_x, to_clb_y); + dump_verilog_one_clb2clb_direct(fp, + ix, iy, + to_clb_x, to_clb_y, + &direct[idirect]); + fprintf(fp, " //----- END Point to Point from grid_%d__%d_ to grid_%d__%d_ -----\n", ix, iy, + to_clb_x, to_clb_y); + } + } } } } diff --git a/vpr7_x2p/vpr/SRC/util/vpr_utils.c b/vpr7_x2p/vpr/SRC/util/vpr_utils.c index 93ef9fe24..049eef7c5 100755 --- a/vpr7_x2p/vpr/SRC/util/vpr_utils.c +++ b/vpr7_x2p/vpr/SRC/util/vpr_utils.c @@ -1245,7 +1245,10 @@ t_clb_to_clb_directs * alloc_and_load_clb_to_clb_directs(INP const t_direct_inf vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Range mismatch from %s to %s.\n", directs[i].line, directs[i].from_pin, directs[i].to_pin); exit(1); } - + /* Aurelien: assign point to point parameters */ + clb_to_clb_directs[i].interconnection_type = directs[i].interconnection_type; + clb_to_clb_directs[i].x_dir = directs[i].x_dir; + clb_to_clb_directs[i].y_dir = directs[i].y_dir; /* Xifan Tang: assign values to x,y,z_offset */ clb_to_clb_directs[i].x_offset = directs[i].x_offset; clb_to_clb_directs[i].y_offset = directs[i].y_offset; From 1e187f3d1536c1e09c306f75ac8a5a82d23eeb07 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Sep 2019 18:08:37 -0600 Subject: [PATCH 243/482] start adding memory circuit to Switch blocks --- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 2 +- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 2 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 31 ++++----- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 22 +++---- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 4 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 2 +- .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 17 +++-- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 64 +++++++++---------- .../SRC/fpga_x2p/verilog/verilog_routing.c | 53 +++++++-------- 9 files changed, 97 insertions(+), 100 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 67bf9a37c..5b7c7b62d 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -1875,7 +1875,7 @@ void CircuitLibrary::build_submodels() { /* Build a unique list */ for (const auto& cand : candidates) { /* Make sure the model id is unique in the list */ - if (true == is_unique_submodel(model,cand)) { + if (true == is_unique_submodel(model, cand)) { sub_models_[model].push_back(cand); } } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 69dc47a3d..8080d2ea3 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -453,8 +453,8 @@ class CircuitLibrary { void link_buffer_model(const CircuitModelId& model_id); void link_pass_gate_logic_model(const CircuitModelId& model_id); bool is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id); - void build_submodels(); void build_model_timing_graph(const CircuitModelId& model_id); + void build_submodels(); public: /* Public Mutators: builders */ void build_model_links(); void build_timing_graphs(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 80628358d..1ef933bc1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -9,6 +9,7 @@ #include "sides.h" #include "fpga_x2p_utils.h" +#include "circuit_library_utils.h" #include "fpga_x2p_naming.h" /************************************************ @@ -18,8 +19,8 @@ * Case 1 : If there is NO intermediate buffer followed by, * the node name will be mux_l_in ***********************************************/ -std::string generate_verilog_mux_node_name(const size_t& node_level, - const bool& add_buffer_postfix) { +std::string generate_mux_node_name(const size_t& node_level, + const bool& add_buffer_postfix) { /* Generate the basic node_name */ std::string node_name = "mux_l" + std::to_string(node_level) + "_in"; @@ -38,10 +39,10 @@ std::string generate_verilog_mux_node_name(const size_t& node_level, * 1. LUTs are named as _mux * 2. MUXes are named as _size ***********************************************/ -std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const std::string& postfix) { +std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const std::string& postfix) { std::string module_name = circuit_lib.model_name(circuit_model); /* Check the model type and give different names */ if (SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) { @@ -64,11 +65,11 @@ std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, * Generate the module name of a branch for a * multiplexer in Verilog format ***********************************************/ -std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const size_t& branch_mux_size, - const std::string& postfix) { +std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const size_t& branch_mux_size, + const std::string& postfix) { /* If the tgate spice model of this MUX is a MUX2 standard cell, * the mux_subckt name will be the name of the standard cell */ @@ -79,7 +80,7 @@ std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circui } std::string branch_postfix = postfix + "_size" + std::to_string(branch_mux_size); - return generate_verilog_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix); + return generate_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix); } /************************************************ @@ -473,7 +474,7 @@ std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, const size_t& mux_size, const size_t& mux_instance_id) { std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_inbus"); - return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); + return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); } /********************************************************************* @@ -492,7 +493,7 @@ std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, postfix += std::string("_b"); } - return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); + return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); } /********************************************************************* @@ -516,6 +517,6 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, postfix += std::string("outb"); } - return generate_verilog_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); + return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index b633d011a..0a6d4f069 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -13,19 +13,19 @@ #include "circuit_library.h" #include "vpr_types.h" -std::string generate_verilog_mux_node_name(const size_t& node_level, - const bool& add_buffer_postfix); +std::string generate_mux_node_name(const size_t& node_level, + const bool& add_buffer_postfix); -std::string generate_verilog_mux_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const std::string& posfix) ; +std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const std::string& posfix) ; -std::string generate_verilog_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const size_t& branch_mux_size, - const std::string& posfix); +std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const size_t& mux_size, + const size_t& branch_mux_size, + const std::string& posfix); std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, const size_t& data_size); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 0c2706814..9f73bc651 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -3179,6 +3179,10 @@ void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circu } } } + /* TODO: this should be done right after XML parsing!!! + * Rebuild the submodels for circuit_library, because we have created links for ports + */ + circuit_lib.build_model_links(); } void determine_sb_port_coordinator(t_sb cur_sb_info, int side, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 5adc9a558..5c7e27449 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -299,7 +299,7 @@ void print_verilog_submodule_lut(ModuleManager& module_manager, /* Instanciate the multiplexing structure for the LUT */ print_verilog_comment(fp, std::string("---- BEGIN Instanciation of LUT multiplexer module -----")); /* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */ - std::string lut_mux_module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, size_t(-1), std::string("")); + std::string lut_mux_module_name = generate_mux_subckt_name(circuit_lib, circuit_model, size_t(-1), std::string("")); /* Find the module id of LUT MUX in the module manager */ ModuleId lut_mux_module_id = module_manager.find_module(lut_mux_module_name); /* We must have a valid id */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index 3b60c55ab..dd8f4775d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -14,6 +14,7 @@ #include "module_manager.h" #include "physical_types.h" #include "vpr_types.h" +#include "circuit_library_utils.h" #include "mux_utils.h" /* FPGA-X2P context header files */ @@ -217,6 +218,7 @@ void print_verilog_memory_module(ModuleManager& module_manager, /* TODO: Wire the memory cells into a chain, when Configuration-chain style is selected!!! */ } + /* TODO: Add local decoders here if required */ /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); @@ -245,21 +247,18 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: { /* Generate module name */ - std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, mux_model, - find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string(verilog_mem_posfix)); + std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, + find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), + std::string(verilog_mem_posfix)); /* Get the sram ports from the mux */ - std::vector mux_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); - VTR_ASSERT( 1 == mux_sram_ports.size() ); - /* Get the circuit model for the memory circuit used by the multiplexer */ - CircuitModelId sram_model = circuit_lib.port_tri_state_model(mux_sram_ports[0]); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + VTR_ASSERT( 1 == sram_models.size() ); /* Find the number of SRAMs in the module, this is also the port width */ size_t num_mems = mux_graph.num_memory_bits(); - print_verilog_memory_module(module_manager, circuit_lib, fp, module_name, sram_model, num_mems); + print_verilog_memory_module(module_manager, circuit_lib, fp, module_name, sram_models[0], num_mems); break; } case SPICE_MODEL_DESIGN_RRAM: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 3244cce1b..ac9bd2f0d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -691,7 +691,7 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, const CircuitModelId& circuit_model, const size_t& mux_size, const MuxGraph& mux_graph) { - std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); + std::string module_name = generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { @@ -760,13 +760,13 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& /* Print local wires which are the nodes in the mux graph */ for (size_t level = 0; level < mux_graph.num_levels(); ++level) { /* Print the internal wires located at this level */ - BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); + BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; /* Identify if an intermediate buffer is needed */ if (false == inter_buffer_location_map[level]) { continue; } - BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); + BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; } print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); @@ -832,7 +832,7 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& /* Generate the port info of each input node */ size_t input_node_level = mux_graph.node_level(input_node); size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort instance_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); + BasicPort instance_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); /* Link nodes to input ports for the branch module */ std::string module_input_port_name = circuit_lib.port_lib_name(std_cell_input_ports[&input_node - &input_nodes[0]]); @@ -841,7 +841,7 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& /* Build the link between output_node[0] and std_cell_output_port[0] */ { /* Create a code block to accommodate the local variables */ - BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); std::string module_output_port_name = circuit_lib.port_lib_name(std_cell_output_ports[0]); port2port_name_map[module_output_port_name] = instance_output_port; } @@ -876,8 +876,8 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); @@ -934,13 +934,13 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* Print local wires which are the nodes in the mux graph */ for (size_t level = 0; level < mux_graph.num_levels(); ++level) { /* Print the internal wires located at this level */ - BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); + BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; /* Identify if an intermediate buffer is needed */ if (false == inter_buffer_location_map[level]) { continue; } - BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); + BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; } print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); @@ -982,7 +982,7 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* Instanciate the branch module which is a tgate-based module */ - std::string branch_module_name= generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); + std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); /* Get the moduleId for the submodule */ ModuleId branch_module_id = module_manager.find_module(branch_module_name); /* We must have one */ @@ -998,13 +998,13 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* Generate the port info of each input node */ size_t input_node_level = mux_graph.node_level(input_node); size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); + BasicPort branch_node_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); branch_node_input_ports.push_back(branch_node_input_port); } /* Create the port info for the input */ /* TODO: the naming could be more flexible? */ - BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_in")); + BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_mux_node_name(output_node_level, false) + "_in")); /* If we have more than 1 port in the combined instance ports , * output a local wire */ if (1 < combine_verilog_ports(branch_node_input_ports).size()) { @@ -1023,7 +1023,7 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager port2port_name_map[module_input_port.get_name()] = instance_input_port; /* Link nodes to output ports for the branch module */ - BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out"); VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); /* Get the port from module */ @@ -1040,7 +1040,7 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* Create the port info for the input */ /* TODO: the naming could be more flexible? */ - BasicPort instance_mem_port = generate_verilog_bus_port(branch_node_mem_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_mem")); + BasicPort instance_mem_port = generate_verilog_bus_port(branch_node_mem_ports, std::string(generate_mux_node_name(output_node_level, false) + "_mem")); /* If we have more than 1 port in the combined instance ports , * output a local wire */ if (1 < combine_verilog_ports(branch_node_mem_ports).size()) { @@ -1070,7 +1070,7 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* Create the port info for the input */ /* TODO: the naming could be more flexible? */ - BasicPort instance_mem_inv_port = generate_verilog_bus_port(branch_node_mem_inv_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_mem_inv")); + BasicPort instance_mem_inv_port = generate_verilog_bus_port(branch_node_mem_inv_ports, std::string(generate_mux_node_name(output_node_level, false) + "_mem_inv")); /* If we have more than 1 port in the combined instance ports , * output a local wire */ if (1 < combine_verilog_ports(branch_node_mem_inv_ports).size()) { @@ -1110,8 +1110,8 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); @@ -1167,7 +1167,7 @@ void generate_verilog_cmos_mux_module_input_buffers(ModuleManager& module_manage BasicPort instance_input_port(module_input_port.get_name(), size_t(input_index), size_t(input_index)); /* Create the port information of the MUX graph input, which is the output of buffer instance */ - BasicPort instance_output_port(generate_verilog_mux_node_name(input_node_level, false), input_node_index_at_level, input_node_index_at_level); + BasicPort instance_output_port(generate_mux_node_name(input_node_level, false), input_node_index_at_level, input_node_index_at_level); /* For last input: * Add a constant value to the last input, if this MUX needs a constant input @@ -1261,7 +1261,7 @@ void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manag VTR_ASSERT(MuxNodeId::INVALID() != mux_graph.node_id(output_node_level, output_node_index_at_level)); /* Create the port information of the MUX input, which is the input of buffer instance */ - BasicPort instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); /* Create the port information of the module output at the given pin range, which is the output of buffer instance */ BasicPort instance_output_port(module_output_port.get_name(), pin, pin); @@ -1467,13 +1467,13 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* Print local wires which are the nodes in the mux graph */ for (size_t level = 0; level < mux_graph.num_levels(); ++level) { /* Print the internal wires located at this level */ - BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); + BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; /* Identify if an intermediate buffer is needed */ if (false == inter_buffer_location_map[level]) { continue; } - BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); + BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; } print_verilog_comment(fp, std::string("---- END Internal wires of a RRAM-based MUX module -----")); @@ -1515,7 +1515,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* Instanciate the branch module which is a tgate-based module */ - std::string branch_module_name= generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); + std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); /* Get the moduleId for the submodule */ ModuleId branch_module_id = module_manager.find_module(branch_module_name); /* We must have one */ @@ -1531,13 +1531,13 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* Generate the port info of each input node */ size_t input_node_level = mux_graph.node_level(input_node); size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); + BasicPort branch_node_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); branch_node_input_ports.push_back(branch_node_input_port); } /* Create the port info for the input */ /* TODO: the naming could be more flexible? */ - BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_in")); + BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_mux_node_name(output_node_level, false) + "_in")); /* If we have more than 1 port in the combined instance ports , * output a local wire */ if (1 < combine_verilog_ports(branch_node_input_ports).size()) { @@ -1556,7 +1556,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu port2port_name_map[module_input_port.get_name()] = instance_input_port; /* Link nodes to output ports for the branch module */ - BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out"); VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); /* Get the port from module */ @@ -1589,7 +1589,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* Create the port info for the input */ /* TODO: the naming could be more flexible? */ - BasicPort instance_blb_port = generate_verilog_bus_port(branch_node_blb_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_blb")); + BasicPort instance_blb_port = generate_verilog_bus_port(branch_node_blb_ports, std::string(generate_mux_node_name(output_node_level, false) + "_blb")); /* If we have more than 1 port in the combined instance ports , * output a local wire */ if (1 < combine_verilog_ports(branch_node_blb_ports).size()) { @@ -1630,7 +1630,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* Create the port info for the WL */ /* TODO: the naming could be more flexible? */ - BasicPort instance_wl_port = generate_verilog_bus_port(branch_node_wl_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_wl")); + BasicPort instance_wl_port = generate_verilog_bus_port(branch_node_wl_ports, std::string(generate_mux_node_name(output_node_level, false) + "_wl")); /* If we have more than 1 port in the combined instance ports , * output a local wire */ if (1 < combine_verilog_ports(branch_node_wl_ports).size()) { @@ -1669,8 +1669,8 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); + BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); @@ -1825,9 +1825,9 @@ void generate_verilog_mux_module(ModuleManager& module_manager, std::fstream& fp, const CircuitModelId& circuit_model, const MuxGraph& mux_graph) { - std::string module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, - find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), - std::string("")); + std::string module_name = generate_mux_subckt_name(circuit_lib, circuit_model, + find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), + std::string("")); /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(circuit_model)) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 19a006e41..e838a9981 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2348,7 +2348,7 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_verilog_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); ModuleId mux_module = module_manager.find_module(mux_module_name); VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); @@ -2440,35 +2440,28 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, */ module_manager.add_child_module(sb_module, mux_module); - /* TODO: Instanciate memory modules */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - /* Call the memory module defined for this SRAM-based MUX! */ - /* - mem_subckt_name = generate_verilog_mux_subckt_name(verilog_model, mux_size, verilog_mem_posfix); - dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, - verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, - is_explicit_mapping); - */ - break; - case SPICE_MODEL_DESIGN_RRAM: - /* RRAM-based MUX does not need any SRAM dumping - * But we have to get the number of configuration bits required by this MUX - * and update the number of memory bits - */ - /* - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); - update_sram_orgz_info_num_blwl(cur_sram_orgz_info, - cur_bl + num_mux_conf_bits, - cur_wl + num_mux_conf_bits); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid design technology for circuit model (%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - } + /* Instanciate memory modules */ + /* Find the name and module id of the memory module */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + ModuleId mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + + /* Create port-to-port map */ + std::map mem_port2port_name_map; + + /* Link input port to Switch block configuration bus */ + + /* Link output port to MUX configuration port */ + + /* Print an instance of the MUX Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); + print_verilog_module_instance(fp, module_manager, sb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(sb_module, mem_module); /* Create the path of the input of multiplexer in the hierarchy * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! From 4da50356276347c7c956ba0c3bb5aeb8762f837a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Sep 2019 20:50:12 -0600 Subject: [PATCH 244/482] Connect CCFFs in a chain in a Verilog module --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 16 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 4 + .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 345 ++++++++++++++---- .../vpr/SRC/fpga_x2p/verilog/verilog_memory.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 6 + .../SRC/fpga_x2p/verilog/verilog_submodules.c | 10 +- 6 files changed, 303 insertions(+), 79 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 1ef933bc1..8323acfd4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -316,6 +316,22 @@ std::string generate_formal_verification_sram_port_name(const CircuitLibrary& ci return port_name; } +/********************************************************************* + * Generate the head port name of a configuration chain + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_configuration_chain_head_name() { + return std::string("ccff_head"); +} + +/********************************************************************* + * Generate the tail port name of a configuration chain + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_configuration_chain_tail_name() { + return std::string("ccff_tail"); +} + /********************************************************************* * Generate the port name for a regular sram port which appears in the * port list of a module diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 0a6d4f069..f68fee17d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -72,6 +72,10 @@ std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model); +std::string generate_configuration_chain_head_name(); + +std::string generate_configuration_chain_tail_name(); + std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_sram_orgz& sram_orgz_type, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index dd8f4775d..d260b6ec7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -28,10 +28,7 @@ #include "verilog_memory.h" /********************************************************************* - * Generate Verilog modules for the memories that are used - * by CMOS (SRAM-based) multiplexers - * We support: - * 1. Flat memory modules + * Flat memory modules * * in[0] in[1] in[N] * | | | @@ -44,68 +41,15 @@ * v v v * +------------------------------------+ * | Multiplexer Configuration port | - * - * 2. TODO: Local decoders - * - * in[0] in[1] in[N] - * | | | - * v v v - * +-------+ +-------+ +-------+ - * | SRAM | | SRAM | ... | SRAM | - * | [0] | | [1] | | [N-1] | - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Local decoders | - * +------------------------------------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Multiplexer Configuration port | - * - * 3. TODO: Scan-chain organization - * - * in[0] in[1] in[N] - * | | | - * v v v - * +-------+ +-------+ +-------+ - * scan-chain--->| SRAM |--->| SRAM |--->... --->| SRAM |---->scan-chain - * input&clock | [0] | | [1] | | [N-1] | output - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +-----------------------------------------+ - * | Multiplexer Configuration port | - * - * 4. TODO: Memory bank organization - * - * Bit lines Word lines - * | | - * v v - * +------------------------------------+ - * | Memory Module Configuration port | - * +------------------------------------+ - * | | | - * v v v - * +-------+ +-------+ +-------+ - * | SRAM | | SRAM | ... | SRAM | - * | [0] | | [1] | | [N-1] | - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Multiplexer Configuration port | - * ********************************************************************/ static -void print_verilog_memory_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { +void print_verilog_memory_standalone_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -121,6 +65,220 @@ void print_verilog_memory_module(ModuleManager& module_manager, std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); /* Get the output ports from the SRAM */ std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Add module ports: the ports come from the SRAM modules */ + /* Add each global port */ + for (const auto& port : sram_global_ports) { + /* Configure each global port: global ports are shared among the SRAMs, so it is independent from the memory size */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port */ + for (const auto& port : sram_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Find the sram module in the module manager */ + ModuleId sram_module_id = module_manager.find_module(circuit_lib.model_name(sram_model)); + + /* Instanciate each submodule */ + for (size_t i = 0; i < num_mems; ++i) { + /* Create a port-to-port map */ + std::map port2port_name_map; + /* Map instance inputs [i] to SRAM module input */ + for (const auto& port : sram_input_ports) { + BasicPort instance_input_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; + } + /* Map instance outputs [i] to SRAM module input */ + for (const auto& port : sram_output_ports) { + BasicPort instance_output_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_output_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, sram_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(sram_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, sram_module_id); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + +/********************************************************************* + * Scan-chain organization + * + * +-------+ +-------+ +-------+ + * scan-chain--->| CCFF |--->| CCFF |--->... --->| CCFF |---->scan-chain + * input&clock | [0] | | [1] | | [N-1] | output + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +-----------------------------------------+ + * | Multiplexer Configuration port | + * + ********************************************************************/ +static +void print_verilog_memory_chain_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Create a module and add to the module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Get the global ports required by the SRAM */ + std::vector global_port_types; + global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); + global_port_types.push_back(SPICE_MODEL_PORT_INPUT); + std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); + /* Get the input ports from the SRAM */ + std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); + /* Should have only 1 input port */ + VTR_ASSERT( 1 == sram_input_ports.size() ); + /* Get the output ports from the SRAM */ + std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Add module ports: the ports come from the SRAM modules */ + /* Add each global port */ + for (const auto& port : sram_global_ports) { + /* Configure each global port: global ports are shared among the SRAMs, so it is independent from the memory size */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add an input port, which is the head of configuration chain in the module */ + /* TODO: restriction!!! + * consider only the first input of the CCFF model as the D port, + * which will be connected to the head of the chain + */ + BasicPort chain_head_port(generate_configuration_chain_head_name(), + circuit_lib.port_size(sram_input_ports[0])); + module_manager.add_port(module_id, chain_head_port, ModuleManager::MODULE_INPUT_PORT); + /* Add an output port, which is the tail of configuration chain in the module */ + /* TODO: restriction!!! + * consider only the first output of the CCFF model as the Q port, + * which will be connected to the tail of the chain + */ + BasicPort chain_tail_port(generate_configuration_chain_tail_name(), + circuit_lib.port_size(sram_output_ports[0])); + module_manager.add_port(module_id, chain_tail_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Find the sram module in the module manager */ + ModuleId sram_module_id = module_manager.find_module(circuit_lib.model_name(sram_model)); + + /* Instanciate each submodule */ + for (size_t i = 0; i < num_mems; ++i) { + /* Create a port-to-port map */ + std::map port2port_name_map; + /* Map instance inputs [i] to SRAM module input */ + for (const auto& port : sram_input_ports) { + BasicPort instance_input_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; + } + /* Map instance outputs [i] to SRAM module input */ + for (const auto& port : sram_output_ports) { + BasicPort instance_output_port(circuit_lib.port_lib_name(port), i, i); + port2port_name_map[circuit_lib.port_lib_name(port)] = instance_output_port; + } + + /* Output an instance of the module */ + print_verilog_module_instance(fp, module_manager, module_id, sram_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(sram_model)); + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, sram_module_id); + } + + /* Wire the memory cells into a chain + * The head of the chain will be wired to the input port of the first CCFF + * The tail of the chain will be wired to the output port of the last CCFF + * The output of each CCFF will be wired to the input of the next CCFFF in the chain + */ + BasicPort first_ccff_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 0, 0); + print_verilog_wire_connection(fp, first_ccff_input_port, chain_head_port, false); + + BasicPort last_ccff_output_port(circuit_lib.port_lib_name(sram_output_ports[0]), num_mems - 1, num_mems - 1); + print_verilog_wire_connection(fp, chain_tail_port, last_ccff_output_port, false); + + BasicPort chain_output_port(circuit_lib.port_lib_name(sram_output_ports[0]), 1, num_mems - 1); + BasicPort chain_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 0, num_mems - 2); + print_verilog_wire_connection(fp, chain_input_port, chain_output_port, false); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + +/********************************************************************* + * Memory bank organization + * + * Bit lines(BL/BLB) Word lines (WL/WLB) + * | | + * v v + * +------------------------------------+ + * | Memory Module Configuration port | + * +------------------------------------+ + * | | | + * v v v + * +-------+ +-------+ +-------+ + * | SRAM | | SRAM | ... | SRAM | + * | [0] | | [1] | | [N-1] | + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Multiplexer Configuration port | + * + ********************************************************************/ +static +void print_verilog_memory_bank_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Create a module and add to the module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Get the global ports required by the SRAM */ + std::vector global_port_types; + global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); + global_port_types.push_back(SPICE_MODEL_PORT_INPUT); + std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); + /* Get the input ports from the SRAM */ + std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); + /* A SRAM cell with BL/WL should not have any input */ + VTR_ASSERT( 0 == sram_input_ports.size() ); + /* Get the output ports from the SRAM */ + std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); /* Get the BL/WL ports from the SRAM */ std::vector sram_bl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BL, true); std::vector sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB, true); @@ -134,14 +292,7 @@ void print_verilog_memory_module(ModuleManager& module_manager, BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } - /* TODO: when Configuration-chain style is selected, the port map should be different! - * It should have only a head as input, a tail as output and other regular output ports - */ - /* Add each input port: port width should match the number of memories - * The number of inputs will not match the number of memory bits of a multiplexer - * when local decoders are used. - * It should be calculated by the decoder builders! - */ + /* Add each input port */ for (const auto& port : sram_input_ports) { BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); @@ -214,16 +365,54 @@ void print_verilog_memory_module(ModuleManager& module_manager, * update the module manager with the relationship between the parent and child modules */ module_manager.add_child_module(module_id, sram_module_id); - - /* TODO: Wire the memory cells into a chain, when Configuration-chain style is selected!!! */ } - /* TODO: Add local decoders here if required */ + /* TODO: if a local memory decoder is required, instanciate it here */ /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); } + +/********************************************************************* + * Generate Verilog modules for the memories that are used + * by a circuit model + * The organization of memory circuit will depend on the style of + * configuration protocols + * Currently, we support + * 1. Flat SRAM organization + * 2. Configuration chain + * 3. Memory bank (memory decoders) + ********************************************************************/ +static +void print_verilog_memory_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + std::fstream& fp, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + print_verilog_memory_standalone_module(module_manager, circuit_lib, fp, + module_name, sram_model, num_mems); + break; + case SPICE_SRAM_SCAN_CHAIN: + print_verilog_memory_chain_module(module_manager, circuit_lib, fp, + module_name, sram_model, num_mems); + break; + case SPICE_SRAM_MEMORY_BANK: + print_verilog_memory_bank_module(module_manager, circuit_lib, fp, + module_name, sram_model, num_mems); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, LINE%d) Invalid SRAM organization!\n", + __FILE__, __LINE__); + } +} + + /********************************************************************* * Generate Verilog modules for the memories that are used * by multiplexers @@ -240,6 +429,7 @@ void print_verilog_memory_module(ModuleManager& module_manager, static void print_verilog_mux_memory_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph) { @@ -258,7 +448,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, /* Find the number of SRAMs in the module, this is also the port width */ size_t num_mems = mux_graph.num_memory_bits(); - print_verilog_memory_module(module_manager, circuit_lib, fp, module_name, sram_models[0], num_mems); + print_verilog_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, module_name, sram_models[0], num_mems); break; } case SPICE_MODEL_DESIGN_RRAM: @@ -295,6 +485,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, void print_verilog_submodule_memories(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, const std::string& verilog_dir, const std::string& submodule_dir) { /* Plug in with the mux subckt */ @@ -328,7 +519,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, continue; } /* Create a Verilog module for the memories used by the multiplexer */ - print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph); + print_verilog_mux_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, mux_model, mux_graph); } /* Create the memory circuits for non-MUX circuit models. @@ -370,7 +561,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(verilog_mem_posfix)); /* Create a Verilog module for the memories used by the circuit model */ - print_verilog_memory_module(module_manager, circuit_lib, fp, module_name, sram_models[0], num_mems); + print_verilog_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, module_name, sram_models[0], num_mems); } /* Close the file stream */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h index 08ecc4ec3..eee29cb23 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h @@ -16,6 +16,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, const std::string& verilog_dir, const std::string& submodule_dir); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index ac9bd2f0d..f38cd106a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -1381,6 +1381,10 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); } + + /* TODO: the size of of memory ports depend on + * if a local encoder is used for the mux or not + */ size_t sram_port_cnt = 0; for (const auto& port : mux_sram_ports) { /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules @@ -1426,6 +1430,8 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); + /* TODO: add local decoder instance here */ + /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 9c17f8ac3..40095d8a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3201,9 +3201,13 @@ void dump_verilog_submodules(ModuleManager& module_manager, dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); + /* NOTE: local decoders generation must go before the MUX generation!!! + * because local decoders modules will be instanciated in the MUX modules + */ + print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, + std::string(verilog_dir), std::string(submodule_dir)); print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir)); - print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 2. LUTes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n"); @@ -3221,7 +3225,9 @@ void dump_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n"); dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); - print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); + print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, + cur_sram_orgz_info->type, + std::string(verilog_dir), std::string(submodule_dir)); /* 5. Dump template for all the modules */ if (TRUE == fpga_verilog_opts.print_user_defined_template) { From 433fc734607b67d1be7819a0fce8a55bda0cf8c4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Sep 2019 23:10:43 -0600 Subject: [PATCH 245/482] refactored local encoder support for Verilog MUX generation --- .../libarchfpga/SRC/circuit_library_utils.cpp | 22 +++- .../libarchfpga/SRC/circuit_library_utils.h | 7 +- vpr7_x2p/libarchfpga/SRC/device_port.cpp | 12 +- .../vpr/SRC/device/decoder_library_utils.cpp | 6 +- .../vpr/SRC/device/decoder_library_utils.h | 2 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 27 +++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 6 + .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 22 +++- .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 107 +++++++++++++----- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 6 +- 11 files changed, 173 insertions(+), 46 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp index d74b2b2d7..63fcb15eb 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -54,8 +54,8 @@ * Get the model id of a SRAM model that is used to configure * a circuit model *******************************************************************/ -std::vector get_circuit_sram_models(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { +std::vector find_circuit_sram_models(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { /* SRAM model id is stored in the sram ports of a circuit model */ std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); std::vector sram_models; @@ -73,3 +73,21 @@ std::vector get_circuit_sram_models(const CircuitLibrary& circui return sram_models; } + +/******************************************************************** + * Find regular (not mode select) sram ports of a circuit model + *******************************************************************/ +std::vector find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); + std::vector regular_sram_ports; + + for (const auto& port : sram_ports) { + if (true == circuit_lib.port_is_mode_select(port)) { + continue; + } + regular_sram_ports.push_back(port); + } + + return regular_sram_ports; +} diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h index e80e5c388..f4323f391 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h @@ -10,7 +10,10 @@ #include #include "circuit_library.h" -std::vector get_circuit_sram_models(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); +std::vector find_circuit_sram_models(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + +std::vector find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); #endif diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.cpp b/vpr7_x2p/libarchfpga/SRC/device_port.cpp index 2de15172d..38241f198 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.cpp +++ b/vpr7_x2p/libarchfpga/SRC/device_port.cpp @@ -136,10 +136,14 @@ void BasicPort::revert() { /* rotate: increase both lsb and msb by an offset */ bool BasicPort::rotate(const size_t& offset) { - /* If current port is invalid or offset is 0, - * we do nothing - */ - if ((0 == offset) || (0 == get_width())) { + /* If offset is 0, we do nothing */ + if (0 == offset) { + return true; + } + + /* If current width is 0, we set a width using the offset! */ + if (0 == get_width()) { + set_width(offset); return true; } /* check if leads to overflow: diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp index ca773819e..47ec9a9a9 100644 --- a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp @@ -27,12 +27,14 @@ * We plus 1, which is all-zero condition for outputs ***************************************************************************************/ size_t find_mux_local_decoder_addr_size(const size_t& data_size) { - /* Make sure we have a encoder which is at least 2 ! */ + /* if data size is 1, it is an corner case for the decoder (addr = 1) */ + if (1 == data_size) { + return 1; + } VTR_ASSERT (2 <= data_size); return ceil(log(data_size) / log(2)); } - /*************************************************************************************** * Try to find if the decoder already exists in the library, * If there is no such decoder, add it to the library diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h index f0719f2e6..100f04da7 100644 --- a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h +++ b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h @@ -6,6 +6,8 @@ #include "decoder_library.h" +bool need_mux_local_decoder(const size_t& data_size); + size_t find_mux_local_decoder_addr_size(const size_t& data_size); DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 8323acfd4..1ab7a2ebd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -332,6 +332,33 @@ std::string generate_configuration_chain_tail_name() { return std::string("ccff_tail"); } +/********************************************************************* + * Generate the addr port (input) for a local decoder of a multiplexer + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_mux_local_decoder_addr_port_name() { + return std::string("addr"); +} + + + +/********************************************************************* + * Generate the data port (output) for a local decoder of a multiplexer + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_mux_local_decoder_data_port_name() { + return std::string("data"); +} + +/********************************************************************* + * Generate the inverted data port (output) for a local decoder of a multiplexer + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_mux_local_decoder_data_inv_port_name() { + return std::string("data_inv"); +} + + /********************************************************************* * Generate the port name for a regular sram port which appears in the * port list of a module diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index f68fee17d..f3b748a77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -76,6 +76,12 @@ std::string generate_configuration_chain_head_name(); std::string generate_configuration_chain_tail_name(); +std::string generate_mux_local_decoder_addr_port_name(); + +std::string generate_mux_local_decoder_data_port_name(); + +std::string generate_mux_local_decoder_data_inv_port_name(); + std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_sram_orgz& sram_orgz_type, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index 0de1249cd..4e3a7c422 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -59,17 +59,17 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, VTR_ASSERT(ModuleId::INVALID() != module_id); /* Add module ports */ /* Add each input port */ - BasicPort addr_port("addr", addr_size); + BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size); module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT); /* Add each output port */ - BasicPort data_port("data", data_size); + BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size); module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT); /* Data port is registered. It should be outputted as * output reg [lsb:msb] data */ module_manager.set_port_is_register(module_id, data_port.get_name(), true); /* Add data_in port */ - BasicPort data_inv_port("data_inv", data_size); + BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size); VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder)); module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT); @@ -81,6 +81,20 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, /* Print the truth table of this decoder */ /* Internal logics */ + /* Early exit: Corner case for data size = 1 the logic is very simple: + * data = addr; + * data_inv = ~data_inv + */ + if (1 == data_size) { + print_verilog_wire_connection(fp, addr_port, data_port, false); + print_verilog_wire_connection(fp, data_inv_port, data_port, true); + print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); + return; + } + /* We use a magic number -1 as the addr=1 should be mapped to ...1 * Otherwise addr will map addr=1 to ..10 * Note that there should be a range for the shift operators @@ -194,7 +208,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, * Note that only when there are >=2 memories, a decoder is needed */ size_t decoder_data_size = branch_mux_graph.num_memory_bits(); - if (2 > decoder_data_size) { + if (0 == decoder_data_size) { continue; } /* Try to find if the decoder already exists in the library, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index d260b6ec7..61090aaab 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -442,7 +442,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, std::string(verilog_mem_posfix)); /* Get the sram ports from the mux */ - std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); VTR_ASSERT( 1 == sram_models.size() ); /* Find the number of SRAMs in the module, this is also the port width */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index f38cd106a..0f4b10579 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -17,6 +17,8 @@ #include "physical_types.h" #include "vpr_types.h" #include "mux_utils.h" +#include "circuit_library_utils.h" +#include "decoder_library_utils.h" /* FPGA-X2P context header files */ #include "spice_types.h" @@ -853,6 +855,10 @@ void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& /* Generate the port info of each mem node */ BasicPort instance_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); std::string module_mem_port_name = circuit_lib.port_lib_name(std_cell_input_ports[2]); + /* If use local decoders, we should use another name for the mem port */ + if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { + instance_mem_port.set_name(generate_mux_local_decoder_data_port_name()); + } port2port_name_map[module_mem_port_name] = instance_mem_port; } @@ -910,19 +916,8 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager /* Find the actual mux size */ size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - /* TODO: these are duplicated codes, find a way to simplify it!!! - * Get the regular (non-mode-select) sram ports from the mux - */ - std::vector mux_regular_sram_ports; - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true)) { - /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules - * Here we just bypass it. - */ - if (true == circuit_lib.port_is_mode_select(port)) { - continue; - } - mux_regular_sram_ports.push_back(port); - } + /* Get the regular (non-mode-select) sram ports from the mux */ + std::vector mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model); VTR_ASSERT(1 == mux_regular_sram_ports.size()); /* Build the location map of intermediate buffers */ @@ -1035,6 +1030,10 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager for (const auto& mem : mems) { /* Generate the port info of each mem node */ BasicPort branch_node_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); + /* If use local decoders, we should use another name for the mem port */ + if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { + branch_node_mem_port.set_name(generate_mux_local_decoder_data_port_name()); + } branch_node_mem_ports.push_back(branch_node_mem_port); } @@ -1065,6 +1064,10 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager for (const auto& mem : mems) { /* Generate the port info of each mem node */ BasicPort branch_node_mem_inv_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]) + "_inv", size_t(mem), size_t(mem)); + /* If use local decoders, we should use another name for the mem port */ + if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { + branch_node_mem_inv_port.set_name(generate_mux_local_decoder_data_inv_port_name()); + } branch_node_mem_inv_ports.push_back(branch_node_mem_inv_port); } @@ -1315,8 +1318,11 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); /* Get the output ports from the mux */ std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the sram ports from the mux */ - std::vector mux_sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); + /* Get the sram ports from the mux + * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules + * Here we just bypass it. + */ + std::vector mux_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model); /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -1329,6 +1335,18 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, /* Find out the number of memory bits */ size_t num_mems = mux_graph.num_memory_bits(); + /* The size of of memory ports depend on + * if a local encoder is used for the mux or not + * Multiplexer local encoders are applied to memory bits at each stage + */ + if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { + num_mems = 0; + for (const auto& lvl : mux_graph.levels()) { + size_t data_size = mux_graph.num_memory_bits_at_level(lvl); + num_mems += find_mux_local_decoder_addr_size(data_size); + } + } + /* Check codes to ensure the port of Verilog netlists will match */ /* MUX graph must have only 1 output */ VTR_ASSERT(1 == mux_input_ports.size()); @@ -1381,18 +1399,8 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); } - - /* TODO: the size of of memory ports depend on - * if a local encoder is used for the mux or not - */ size_t sram_port_cnt = 0; for (const auto& port : mux_sram_ports) { - /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules - * Here we just bypass it. - */ - if (true == circuit_lib.port_is_mode_select(port)) { - continue; - } BasicPort mem_port(circuit_lib.port_lib_name(port), num_mems); module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), num_mems); @@ -1400,11 +1408,56 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, /* Update counter */ sram_port_cnt++; } + VTR_ASSERT(1 == sram_port_cnt); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); - /* TODO: Print the internal logic in Verilog codes */ + /* Add local decoder instance here */ + if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { + BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits()); + BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); + /* Print local wires to bridge the port of module and memory inputs + * of each MUX branch instance + */ + fp << generate_verilog_port(VERILOG_PORT_WIRE, decoder_data_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_WIRE, decoder_data_inv_port) << ";" << std::endl; + + /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ + BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); + BasicPort lvl_data_port(decoder_data_port.get_name(), 0); + BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); + for (const auto& lvl : mux_graph.levels()) { + size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); + size_t data_size = mux_graph.num_memory_bits_at_level(lvl); + /* Update the LSB and MSB of addr and data port for the current level */ + lvl_addr_port.rotate(addr_size); + lvl_data_port.rotate(data_size); + lvl_data_inv_port.rotate(data_size); + /* Print the instance of local decoder */ + std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); + ModuleId decoder_module = module_manager.find_module(decoder_module_name); + VTR_ASSERT(ModuleId::INVALID() != decoder_module); + + /* Create a port-to-port map */ + std::map decoder_port2port_name_map; + decoder_port2port_name_map[generate_mux_local_decoder_addr_port_name()] = lvl_addr_port; + decoder_port2port_name_map[generate_mux_local_decoder_data_port_name()] = lvl_data_port; + decoder_port2port_name_map[generate_mux_local_decoder_data_inv_port_name()] = lvl_data_inv_port; + + /* Print an instance of the MUX Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a local decoder -----")); + print_verilog_module_instance(fp, module_manager, module_id, decoder_module, decoder_port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); + print_verilog_comment(fp, std::string("----- END Instanciation of a local decoder -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(module_id, decoder_module); + } + } + + /* Print the internal logic in Verilog codes */ /* Print the Multiplexing structure in Verilog codes * Separated generation strategy on using standard cell MUX2 or TGATE, * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input @@ -1430,8 +1483,6 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager, generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - /* TODO: add local decoder instance here */ - /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 7e6cdd693..72590fc9e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -872,7 +872,7 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; /* Get the SRAM model of the mux_model */ - std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ VTR_ASSERT( 1 == sram_models.size() ); std::vector blb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_BLB); @@ -998,7 +998,7 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; /* Get the SRAM model of the mux_model */ - std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ VTR_ASSERT( 1 == sram_models.size() ); @@ -1078,7 +1078,7 @@ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, BasicPort mux_sram_output(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), num_conf_bits); /* Get the SRAM model of the mux_model */ - std::vector sram_models = get_circuit_sram_models(circuit_lib, mux_model); + std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ VTR_ASSERT( 1 == sram_models.size() ); BasicPort formal_verification_port(generate_formal_verification_sram_port_name(circuit_lib, sram_models[0]), From 1983e565570057dc8623149f413bf5570b742326 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 28 Sep 2019 21:02:14 -0600 Subject: [PATCH 246/482] make local configuration bus generation more general --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 37 ++-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 4 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 4 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 170 +++++++----------- 4 files changed, 91 insertions(+), 124 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 1ab7a2ebd..91942aed4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -539,27 +539,40 @@ std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); } +/********************************************************************* + * Generate the port name for a SRAM port of a circuit + * This name is used for local wires that connecting SRAM ports + * of a circuit model inside a Verilog/SPICE module + * Note that the SRAM ports share the same naming + * convention regardless of their configuration style + *********************************************************************/ +std::string generate_local_sram_port_name(const std::string& port_prefix, + const size_t& instance_id, + const e_spice_model_port_type& port_type) { + std::string port_name = port_prefix + std::string("_") + std::to_string(instance_id) + std::string("_"); + + if (SPICE_MODEL_PORT_INPUT == port_type) { + port_name += std::string("out"); + } else { + VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); + port_name += std::string("outb"); + } + + return port_name; +} + /********************************************************************* * Generate the port name for a SRAM port of a routing multiplexer * This name is used for local wires that connecting SRAM ports * of routing multiplexers inside a Verilog/SPICE module * Note that the SRAM ports of routing multiplexers share the same naming * convention regardless of their configuration style - *********************************************************************/ + **********************************************************************/ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& mux_model, const size_t& mux_size, const size_t& mux_instance_id, const e_spice_model_port_type& port_type) { - std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_"); - - if (SPICE_MODEL_PORT_INPUT == port_type) { - postfix += std::string("out"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - postfix += std::string("outb"); - } - - return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); + std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string()); + return generate_local_sram_port_name(prefix, mux_instance_id, port_type); } - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index f3b748a77..ee5441e84 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -103,6 +103,10 @@ std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, const size_t& bus_id, const bool& inverted); +std::string generate_local_sram_port_name(const std::string& port_prefix, + const size_t& instance_id, + const e_spice_model_port_type& port_type); + std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& mux_model, const size_t& mux_size, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index e838a9981..8ed8eb209 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2449,9 +2449,9 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Create port-to-port map */ std::map mem_port2port_name_map; - /* Link input port to Switch block configuration bus */ + /* TODO: Link input port to Switch block configuration bus */ - /* Link output port to MUX configuration port */ + /* TODO: Link output port to MUX configuration port */ /* Print an instance of the MUX Module */ print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 72590fc9e..a16bef561 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -776,59 +776,61 @@ void print_verilog_local_sram_wires(std::fstream& fp, * ports of a CMOS (SRAM-based) routing multiplexer * This port is supposed to be used locally inside a Verilog/SPICE module * + * The following shows a few representative examples: + * * For standalone configuration style: * ------------------------------------ * No bus needed * - * For configuration-chain configuration style: - * -------------------------------------------- + * Configuration chain-style + * ------------------------- + * wire [0:N] config_bus * - * Module Port - * | - * v - * bus_port --------+----------------+----> ... - * | | - * sram_outputs v v - * +-----------+ +-----------+ - * | Memory | | Memory | - * | Module[0] | | Module[1] | ... - * +-----------+ +-----------+ - * | | - * v v - * +-----------+ +-----------+ - * | Routing | | Routing | - * | MUX [0] | | MUX[1] | ... - * +-----------+ +-----------+ + * config_bus config_bus config_bus config_bus + * [0] [1] [2] [N] + * | | | | + * v v v v + * ccff_head ----------+ +---------+ +------------+ +----> ccff_tail + * | ^ | ^ | ^ + * head v |tail v | v | + * +----------+ +----------+ +----------+ + * | Memory | | Memory | | Memory | + * | Module | | Module | ... | Module | + * | [0] | | [1] | | [N] | + * +----------+ +----------+ +----------+ + * | | | + * v v v + * +----------+ +----------+ +----------+ + * | MUX | | MUX | | MUX | + * | Module | | Module | ... | Module | + * | [0] | | [1] | | [N] | + * +----------+ +----------+ +----------+ * - * For memory-bank configuration style: - * ------------------------------------ - * - * Module Port - * | - * v - * bus_port --------+----------------+----> ... - * | | - * bl/wl/../sram_ports v v - * +-----------+ +-----------+ - * | Memory | | Memory | - * | Module[0] | | Module[1] | ... - * +-----------+ +-----------+ - * | | - * v v - * +-----------+ +-----------+ - * | Routing | | Routing | - * | MUX [0] | | MUX[1] | ... - * +-----------+ +-----------+ + * Memory bank-style + * ----------------- + * BL/WL bus --+------------+--------------------> + * | | | + * BL/WL v BL/WL v BL/WL v + * +----------+ +----------+ +----------+ + * | Memory | | Memory | | Memory | + * | Module | | Module | ... | Module | + * | [0] | | [1] | | [N] | + * +----------+ +----------+ +----------+ + * | | | + * v v v + * +----------+ +----------+ +----------+ + * | MUX | | MUX | | MUX | + * | Module | | Module | ... | Module | + * | [0] | | [1] | | [N] | + * +----------+ +----------+ +----------+ * *********************************************************************/ static -void print_verilog_cmos_mux_config_bus(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const e_sram_orgz& sram_orgz_type, - const size_t& mux_size, - const size_t& mux_instance_id, - const size_t& num_conf_bits) { +void print_verilog_local_config_bus(std::fstream& fp, + const std::string& prefix, + const e_sram_orgz& sram_orgz_type, + const size_t& instance_id, + const size_t& num_conf_bits) { /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -838,78 +840,20 @@ void print_verilog_cmos_mux_config_bus(std::fstream& fp, * The configuration ports of SRAM are directly wired to the ports of modules */ break; - case SPICE_SRAM_SCAN_CHAIN: { - /* To support chain-like configuration protocol, two configuration buses should be outputted + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_MEMORY_BANK: { + /* Two configuration buses should be outputted * One for the regular SRAM ports of a routing multiplexer * The other for the inverted SRAM ports of a routing multiplexer */ - BasicPort config_port(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + BasicPort config_port(generate_local_sram_port_name(prefix, instance_id, SPICE_MODEL_PORT_INPUT), num_conf_bits); fp << generate_verilog_port(VERILOG_PORT_WIRE, config_port) << ";" << std::endl; - BasicPort inverted_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + BasicPort inverted_config_port(generate_local_sram_port_name(prefix, instance_id, SPICE_MODEL_PORT_OUTPUT), num_conf_bits); fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_config_port) << ";" << std::endl; break; } - case SPICE_SRAM_MEMORY_BANK: { - /* To support memory-bank configuration, SRAM outputs are supposed to be exposed to the upper level as buses - * In addition, the BL/WL ports should be grouped and be exposed to the upper level as buses - */ - /* Print configuration bus to group BL/WLs */ - BasicPort bl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, false), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, bl_bus) << ";" << std::endl; - BasicPort wl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, false), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, wl_bus) << ";" << std::endl; - - /* Print bus to group SRAM outputs, this is to interface memory cells to routing multiplexers */ - BasicPort sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_output_bus) << ";" << std::endl; - BasicPort inverted_sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; - - /* Get the SRAM model of the mux_model */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); - /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ - VTR_ASSERT( 1 == sram_models.size() ); - std::vector blb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_BLB); - std::vector wlb_ports = circuit_lib.model_ports_by_type(sram_models[0], SPICE_MODEL_PORT_WLB); - - /* Connect SRAM BL/WLs to bus */ - BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BL), - num_conf_bits); - print_verilog_wire_connection(fp, bl_bus, mux_bl_wire, false); - BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WL), - num_conf_bits); - print_verilog_wire_connection(fp, wl_bus, mux_wl_wire, false); - - /* Print configuration bus to group BLBs, if the ports are available in SRAM models */ - if (0 < blb_ports.size()) { - BasicPort blb_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, true), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, blb_bus) << ";" << std::endl; - /* Connect SRAM BLBs to bus */ - BasicPort mux_blb_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BLB), - num_conf_bits); - print_verilog_wire_connection(fp, blb_bus, mux_blb_wire, false); - } - - /* Print configuration bus to group WLBs, if the ports are available in SRAM models */ - if (0 < wlb_ports.size()) { - BasicPort wlb_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, true), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, wlb_bus) << ";" << std::endl; - /* Connect SRAM WLBs to bus */ - BasicPort mux_wlb_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WLB), - num_conf_bits); - print_verilog_wire_connection(fp, wlb_bus, mux_wlb_wire, false); - } - - break; - } default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization!\n", @@ -1031,7 +975,11 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp, /********************************************************************* * Print a number of bus ports which are wired to the configuration - * ports of a routing multiplexer + * ports of a memory module, which consists of a number of configuration + * memory cells, such as SRAMs. + * Note that the configuration bus will only interface the memory + * module, rather than the programming routing multiplexers, LUTs, IOs + * etc. This helps us to keep clean and simple Verilog generation *********************************************************************/ void print_verilog_mux_config_bus(std::fstream& fp, const CircuitLibrary& circuit_lib, @@ -1050,9 +998,11 @@ void print_verilog_mux_config_bus(std::fstream& fp, * Currently, this is fine. */ switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - print_verilog_cmos_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_conf_bits); + case SPICE_MODEL_DESIGN_CMOS: { + std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string()); + print_verilog_local_config_bus(fp, prefix, sram_orgz_type, mux_instance_id, num_conf_bits); break; + } case SPICE_MODEL_DESIGN_RRAM: print_verilog_rram_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_reserved_conf_bits, num_conf_bits); break; From 3726e691f4b4e18062ec727a3b004299a3dae53b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 28 Sep 2019 21:36:56 -0600 Subject: [PATCH 247/482] simplify the local wire generation for ccffs --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 9 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 2 + .../fpga_x2p/verilog/verilog_writer_utils.cpp | 103 ++++++++++-------- 3 files changed, 65 insertions(+), 49 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 91942aed4..b63ee1f48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -340,8 +340,6 @@ std::string generate_mux_local_decoder_addr_port_name() { return std::string("addr"); } - - /********************************************************************* * Generate the data port (output) for a local decoder of a multiplexer * TODO: This could be replaced as a constexpr string @@ -358,6 +356,13 @@ std::string generate_mux_local_decoder_data_inv_port_name() { return std::string("data_inv"); } +/********************************************************************* + * Generate the port name of a local configuration bus + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_local_config_bus_port_name() { + return std::string("config_bus"); +} /********************************************************************* * Generate the port name for a regular sram port which appears in the diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index ee5441e84..91488b24f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -82,6 +82,8 @@ std::string generate_mux_local_decoder_data_port_name(); std::string generate_mux_local_decoder_data_inv_port_name(); +std::string generate_local_config_bus_port_name(); + std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_sram_orgz& sram_orgz_type, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index a16bef561..4b93c2cd2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -651,7 +651,8 @@ void print_verilog_buffer_instance(std::fstream& fp, /******************************************************************** * Print local wires that are used for SRAM configuration * The local wires are strongly dependent on the organization of SRAMs. - * 1. Standalone SRAMs: + * Standalone SRAMs: + * ----------------- * No need for local wires, their outputs are port of the module * * Module @@ -665,36 +666,61 @@ void print_verilog_buffer_instance(std::fstream& fp, * | +---------------------+ | * +------------------------------+ * - * 2. Configuration-chain Flip-flops: - * two ports will be added, which are the head of scan-chain - * and the tail of scan-chain + * Configuration chain-style + * ------------------------- + * wire [0:N] config_bus * - * Module - * +-----------------------------------------+ - * | | - * | +------+ +------+ +------+ | - * | +->| CCFF |--->| CCFF | ... | CCFF |-+ | - * | | +------+ | +------+ | +------+ | | - * head--->|-+-----------+------------+-----------+->|--->tail - * | local wire | - * +-----------------------------------------+ - * 3. Memory decoders: + * + * Module + * +--------------------------------------------------------------+ + * | config_bus config_bus config_bus config_bus | + * | [0] [1] [2] [N] | + * | | | | | | + * | v v v v | + * ccff_head| ----------+ +---------+ +------------+ +----------------|-> ccff_tail + * | | ^ | ^ | ^ | + * | head v |tail v | v | | + * | +----------+ +----------+ +----------+ | + * | | Memory | | Memory | | Memory | | + * | | Module | | Module | ... | Module | | + * | | [0] | | [1] | | [N] | | + * | +----------+ +----------+ +----------+ | + * | | | | | + * | v v v | + * | +----------+ +----------+ +----------+ | + * | | MUX | | MUX | | MUX | | + * | | Module | | Module | ... | Module | | + * | | [0] | | [1] | | [N] | | + * | +----------+ +----------+ +----------+ | + * | | + * +--------------------------------------------------------------+ + * + * Memory bank-style + * ----------------- * two ports will be added, which are regular output and inverted output * Note that the outputs are the data outputs of SRAMs * BL/WLs of memory decoders are ports of module but not local wires * - * Module - * +-----------------------------------------+ - * | | - * | +------+ +------+ +------+ | - * | | SRAM | | SRAM | ... | SRAM | | - * | +------+ +------+ +------+ | - * | ^ ^ ^ | - * | | | | | - * BL/WL--->|---------------------------------------->| - * | local wire | - * +-----------------------------------------+ - + * Module + * +-------------------------------------------------+ + * | | + BL/WL bus --+--------+------------+-----------------+ | + * | | | | | + * | BL/WL v BL/WL v BL/WL v | + * | +----------+ +----------+ +----------+ | + * | | Memory | | Memory | | Memory | | + * | | Module | | Module | ... | Module | | + * | | [0] | | [1] | | [N] | | + * | +----------+ +----------+ +----------+ | + * | | | | | + * | v v v | + * | +----------+ +----------+ +----------+ | + * | | MUX | | MUX | | MUX | | + * | | Module | | Module | ... | Module | | + * | | [0] | | [1] | | [N] | | + * | +----------+ +----------+ +----------+ | + * | | + * +-------------------------------------------------+ * ********************************************************************/ void print_verilog_local_sram_wires(std::fstream& fp, @@ -717,36 +743,19 @@ void print_verilog_local_sram_wires(std::fstream& fp, break; case SPICE_SRAM_SCAN_CHAIN: { /* Generate the name of local wire for the CCFF inputs, CCFF output and inverted output */ - std::vector ccff_ports; /* [0] => CCFF input */ - ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), port_size)); - /* [1] => CCFF output */ - ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), port_size)); - /* [2] => CCFF inverted output */ - ccff_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INOUT), port_size)); - /* Print local wire definition */ - for (const auto& ccff_port : ccff_ports) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_port) << ";" << std::endl; - } + BasicPort ccff_config_bus_port(generate_local_config_bus_port_name(), port_size); + fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_config_bus_port) << ";" << std::endl; /* Connect first CCFF to the head */ /* Head is always a 1-bit port */ BasicPort ccff_head_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1); - BasicPort ccff_head_local_port(ccff_ports[0].get_name(), 1); + BasicPort ccff_head_local_port(ccff_config_bus_port.get_name(), 1); print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false); /* Connect last CCFF to the tail */ /* Tail is always a 1-bit port */ BasicPort ccff_tail_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1); - BasicPort ccff_tail_local_port(ccff_ports[1].get_name(), ccff_ports[1].get_msb(), ccff_ports[1].get_msb()); + BasicPort ccff_tail_local_port(ccff_config_bus_port.get_name(), ccff_config_bus_port.get_msb(), ccff_config_bus_port.get_msb()); print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false); - /* Connect CCFFs into chains */ - /* If port size is 0 or 1, there is no need for the chain connection */ - if (2 > port_size) { - break; - } - /* Cascade the CCFF between head and tail */ - BasicPort ccff_chain_input_port(ccff_ports[0].get_name(), port_size - 1); - BasicPort ccff_chain_output_port(ccff_ports[1].get_name(), 1, port_size - 1); - print_verilog_wire_connection(fp, ccff_chain_output_port, ccff_chain_input_port, false); break; } case SPICE_SRAM_MEMORY_BANK: { From b082e60c103c815d9946fa741fd8e67c50043cec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Sep 2019 18:20:56 -0600 Subject: [PATCH 248/482] start refactoring instanciation of memory modules --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 16 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 4 + .../fpga_x2p/base/module_manager_utils.cpp | 148 ++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 7 + .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 6 +- .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 41 +++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 17 +- 7 files changed, 222 insertions(+), 17 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index b63ee1f48..d39d4961a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -332,6 +332,22 @@ std::string generate_configuration_chain_tail_name() { return std::string("ccff_tail"); } +/********************************************************************* + * Generate the memory output port name of a configuration chain + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_configuration_chain_data_out_name() { + return std::string("mem_out"); +} + +/********************************************************************* + * Generate the inverted memory output port name of a configuration chain + * TODO: This could be replaced as a constexpr string + *********************************************************************/ +std::string generate_configuration_chain_inverted_data_out_name() { + return std::string("mem_outb"); +} + /********************************************************************* * Generate the addr port (input) for a local decoder of a multiplexer * TODO: This could be replaced as a constexpr string diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 91488b24f..6d7f9c88c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -76,6 +76,10 @@ std::string generate_configuration_chain_head_name(); std::string generate_configuration_chain_tail_name(); +std::string generate_configuration_chain_data_out_name(); + +std::string generate_configuration_chain_inverted_data_out_name(); + std::string generate_mux_local_decoder_addr_port_name(); std::string generate_mux_local_decoder_data_port_name(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 1aa0c9024..e442b0223 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -209,3 +209,151 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, module_manager.add_port(module_id, module_port, module_port_types[iport]); } } + +/********************************************************************* + * Create a port-to-port map for a CMOS memory module + * + * Configuration Chain + * ------------------- + * + * config_bus (head) config_bus (tail) + * | ^ + * v | + * +-------------------------------------+ + * | CMOS-based Memory Module | + * +-------------------------------------+ + * | | + * v v + * sram_out sram_outb + * + * + * Memory bank + * ----------- + * + * config_bus (BL) config_bus (WL) + * | | + * v v + * +-------------------------------------+ + * | CMOS-based Memory Module | + * +-------------------------------------+ + * | | + * v v + * sram_out sram_outb + * + **********************************************************************/ +static +std::map generate_cmos_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const std::vector& config_bus_ports, + const std::vector& mem_output_bus_ports, + const e_sram_orgz& sram_orgz_type) { + std::map port2port_name_map; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Nothing to do */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* Link the head port of the memory module: + * the LSB of config bus port is the head port index + */ + VTR_ASSERT( 1 == config_bus_ports.size() ); + BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); + port2port_name_map[generate_configuration_chain_head_name()] = head_port; + + /* Link the tail port of the memory module: + * the MSB of config bus port is the tail port index + */ + BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); + port2port_name_map[generate_configuration_chain_tail_name()] = tail_port; + + /* Link the SRAM output ports of the memory module */ + VTR_ASSERT( 2 == mem_output_bus_ports.size() ); + port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0]; + port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1]; + break; + } + case SPICE_SRAM_MEMORY_BANK: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return port2port_name_map; +} + +/********************************************************************* + * Create a port-to-port map for a ReRAM-based memory module + * Memory bank + * ----------- + * + * config_bus (BL) config_bus (WL) + * | | + * v v + * +-------------------------------------+ + * | ReRAM-based Memory Module | + * +-------------------------------------+ + * | | + * v v + * Mem_out Mem_outb + **********************************************************************/ +static +std::map generate_rram_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const e_sram_orgz& sram_orgz_type) { + std::map port2port_name_map; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not supported */ + break; + case SPICE_SRAM_SCAN_CHAIN: + /* TODO: to be supported */ + break; + case SPICE_SRAM_MEMORY_BANK: + /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return port2port_name_map; +} + +/********************************************************************* + * Create a port-to-port map for a memory module + * The content of the port-to-port map will depend not only + * the design technology of the memory cells but also the + * configuration styles of FPGA fabric. + * Here we will branch on the design technology + **********************************************************************/ +std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const std::vector& config_bus_ports, + const std::vector& mem_output_bus_ports, + const e_spice_model_design_tech& mem_design_tech, + const e_sram_orgz& sram_orgz_type) { + std::map port2port_name_map; + + switch (mem_design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + port2port_name_map = generate_cmos_mem_module_port2port_map(module_manager, mem_module, config_bus_ports, mem_output_bus_ports, sram_orgz_type); + break; + case SPICE_MODEL_DESIGN_RRAM: + port2port_name_map = generate_rram_mem_module_port2port_map(module_manager, mem_module, sram_orgz_type); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of memory design technology !\n", + __FILE__, __LINE__); + exit(1); + } + + return port2port_name_map; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 17d395cdb..bee3e7ff8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -38,5 +38,12 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, const e_sram_orgz sram_orgz_type, const size_t& port_size); +std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const std::vector& config_bus_ports, + const std::vector& mem_output_bus_ports, + const e_spice_model_design_tech& mem_design_tech, + const e_sram_orgz& sram_orgz_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index a078ed535..197da9c8b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -77,10 +77,14 @@ size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb) { if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { continue; } - /* Check if this node is driven by a multiplexer */ + /* Check if this node is just a passing wire */ if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { continue; } + /* Check if this node has more than 2 drivers */ + if (2 > rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { + continue; + } /* This means we need a multiplexer, update the counter */ num_muxes++; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index 61090aaab..09c2501f3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -155,6 +155,8 @@ void print_verilog_memory_chain_module(ModuleManager& module_manager, VTR_ASSERT( 1 == sram_input_ports.size() ); /* Get the output ports from the SRAM */ std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Should have only 1 or 2 output port */ + VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) ); /* Add module ports: the ports come from the SRAM modules */ /* Add each global port */ @@ -180,8 +182,15 @@ void print_verilog_memory_chain_module(ModuleManager& module_manager, circuit_lib.port_size(sram_output_ports[0])); module_manager.add_port(module_id, chain_tail_port, ModuleManager::MODULE_INPUT_PORT); /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); + for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { + std::string port_name; + if (0 == iport) { + port_name = generate_configuration_chain_data_out_name(); + } else { + VTR_ASSERT( 1 == iport); + port_name = generate_configuration_chain_inverted_data_out_name(); + } + BasicPort output_port(port_name, num_mems); module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); } @@ -202,9 +211,16 @@ void print_verilog_memory_chain_module(ModuleManager& module_manager, port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; } /* Map instance outputs [i] to SRAM module input */ - for (const auto& port : sram_output_ports) { - BasicPort instance_output_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_output_port; + for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { + std::string port_name; + if (0 == iport) { + port_name = generate_configuration_chain_data_out_name(); + } else { + VTR_ASSERT( 1 == iport); + port_name = generate_configuration_chain_inverted_data_out_name(); + } + BasicPort instance_output_port(port_name, i, i); + port2port_name_map[circuit_lib.port_lib_name(sram_output_ports[iport])] = instance_output_port; } /* Output an instance of the module */ @@ -223,11 +239,11 @@ void print_verilog_memory_chain_module(ModuleManager& module_manager, BasicPort first_ccff_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 0, 0); print_verilog_wire_connection(fp, first_ccff_input_port, chain_head_port, false); - BasicPort last_ccff_output_port(circuit_lib.port_lib_name(sram_output_ports[0]), num_mems - 1, num_mems - 1); + BasicPort last_ccff_output_port(generate_configuration_chain_data_out_name(), num_mems - 1, num_mems - 1); print_verilog_wire_connection(fp, chain_tail_port, last_ccff_output_port, false); - BasicPort chain_output_port(circuit_lib.port_lib_name(sram_output_ports[0]), 1, num_mems - 1); - BasicPort chain_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 0, num_mems - 2); + BasicPort chain_output_port(generate_configuration_chain_data_out_name(), 0, num_mems - 2); + BasicPort chain_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 1, num_mems - 1); print_verilog_wire_connection(fp, chain_input_port, chain_output_port, false); /* Put an end to the Verilog module */ @@ -433,6 +449,10 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph) { + /* Find the actual number of configuration bits, based on the mux graph + * Due to the use of local decoders inside mux, this may be + */ + size_t num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: { @@ -445,10 +465,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); VTR_ASSERT( 1 == sram_models.size() ); - /* Find the number of SRAMs in the module, this is also the port width */ - size_t num_mems = mux_graph.num_memory_bits(); - - print_verilog_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, module_name, sram_models[0], num_mems); + print_verilog_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, module_name, sram_models[0], num_config_bits); break; } case SPICE_MODEL_DESIGN_RRAM: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 8ed8eb209..d08f5eb15 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -66,7 +66,8 @@ void print_verilog_switch_block_local_sram_wires(std::fstream& fp, const size_t& port_size) { size_t local_port_size = port_size; if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { - local_port_size = find_switch_block_number_of_muxes(rr_gsb); + /* Plus 1 for the wire size to connect to the tail of the configuration chain */ + local_port_size = find_switch_block_number_of_muxes(rr_gsb) + 1; } print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); } @@ -2449,9 +2450,17 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, /* Create port-to-port map */ std::map mem_port2port_name_map; - /* TODO: Link input port to Switch block configuration bus */ - - /* TODO: Link output port to MUX configuration port */ + /* TODO: Make the port2port map generation more generic!!! */ + std::vector config_ports; + config_ports.push_back(BasicPort(generate_local_config_bus_port_name(), mux_instance_id - 1, mux_instance_id)); + std::vector mem_output_ports; + mem_output_ports.push_back(mux_config_port); + mem_output_ports.push_back(mux_config_inv_port); + mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, + config_ports, + mem_output_ports, + circuit_lib.design_tech_type(mux_model), + cur_sram_orgz_info->type); /* Print an instance of the MUX Module */ print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); From 5ac79f480539b96a5728f9b45aeeca781aebfd5b Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 30 Sep 2019 10:00:46 -0600 Subject: [PATCH 249/482] Point to point documentation --- .../arch_lang/figures/point2point_example.png | Bin 0 -> 60198 bytes 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a/docs/source/arch_lang/index.rst +++ b/docs/source/arch_lang/index.rst @@ -8,6 +8,8 @@ Extended Architecture Description Language :maxdepth: 2 generality + + interconnect spice_sim_setting diff --git a/docs/source/arch_lang/interconnect.rst b/docs/source/arch_lang/interconnect.rst new file mode 100644 index 000000000..d55bacc7a --- /dev/null +++ b/docs/source/arch_lang/interconnect.rst @@ -0,0 +1,92 @@ +Interconnection extensions +========================== + +This section will introduce extensions on the architecture description file about existing interconnection description. + +Directlist +---------- + +The original direct connections in the directlist section is doccumented here_. Its description is given below: + +.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections + +.. code-block:: xml + + + + + +.. note:: These options are required + +Our extension include three more options: + +.. code-block:: xml + + + + + +* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply. This option is optional and do not need to be set for any direct connection in the direclist. If this option is set *x_dir* and *y_dir* are required. + +* **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: + + * x_dir="positive": + + * interconnection_type="column": a column will be connected to a column on the **right**, if it exists. + + * interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists. + + * x_dir="negative": + + * interconnection_type="column": a column will be connected to a column on the **left**, if it exists. + + * interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists. + +* **y_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: + + * y_dir="positive": + + * interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists. + + * interconnection_type="row": a row will be connected on an **above** row, if it exists. + + * y_dir="positive": + + * interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists. + + * interconnection_type="row": a row will be connected on a row **below**, if it exists. + +Example +------- + +For this example, we will study a scan-chain implementation.The description could be: + +.. code-block:: xml + + + + + +:numref:`fig_p2p_expl` is the graphical representation of the above scan-chain description on a 4x4 FPGA. + +.. _fig_p2p_expl: + +.. figure:: ./figures/point2point_example.png + :scale: 100% + :alt: example of scan-chain implementation + + +In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB together. + +Truth table +----------- + +A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his own point to point connection, a truth table with our new parameters id provided below. + +:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate. + +.. _fig_p2p_expl: + +.. figure:: ./figures/point2point_truthtable.png + :scale: 100% + :alt: point to point truth table From 74f7a3cfb2f083093e077a653ad0277cdfa22de8 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 30 Sep 2019 10:29:42 -0600 Subject: [PATCH 250/482] Doc fixing --- .../figures/point2point_truthtable.png | Bin 90308 -> 92444 bytes docs/source/arch_lang/interconnect.rst | 20 ++++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/docs/source/arch_lang/figures/point2point_truthtable.png b/docs/source/arch_lang/figures/point2point_truthtable.png index d92256174f043dbaaf02bfa52e5598ed85f3fee1..b425c6251ff76b7f4fe55e9fa9a787f1089d97f3 100644 GIT binary patch literal 92444 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a/docs/source/arch_lang/interconnect.rst b/docs/source/arch_lang/interconnect.rst index d55bacc7a..7f13ace52 100644 --- a/docs/source/arch_lang/interconnect.rst +++ b/docs/source/arch_lang/interconnect.rst @@ -26,7 +26,9 @@ Our extension include three more options: -* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply. This option is optional and do not need to be set for any direct connection in the direclist. If this option is set *x_dir* and *y_dir* are required. +.. note:: these options are optional. However, if *interconnection_type* is set *x_dir* and *y_dir* are required. + +* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply. * **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: @@ -50,7 +52,7 @@ Our extension include three more options: * interconnection_type="row": a row will be connected on an **above** row, if it exists. - * y_dir="positive": + * y_dir="negative": * interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists. @@ -67,13 +69,13 @@ For this example, we will study a scan-chain implementation.The description coul -:numref:`fig_p2p_expl` is the graphical representation of the above scan-chain description on a 4x4 FPGA. +:numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA. -.. _fig_p2p_expl: +.. _fig_p2p_exple: .. figure:: ./figures/point2point_example.png - :scale: 100% - :alt: example of scan-chain implementation + + An example of scan-chain implementation In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB together. @@ -85,8 +87,8 @@ A point to point connection can be applied in different ways than showed in the :numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate. -.. _fig_p2p_expl: +.. _fig_p2p_trtable: .. figure:: ./figures/point2point_truthtable.png - :scale: 100% - :alt: point to point truth table + + Point to point truth table From e2867019e1031f85da79b410471ad2bd4bf9d728 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 30 Sep 2019 10:38:02 -0600 Subject: [PATCH 251/482] Typo fixing --- docs/source/arch_lang/interconnect.rst | 38 +++++++++++++------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/docs/source/arch_lang/interconnect.rst b/docs/source/arch_lang/interconnect.rst index 7f13ace52..a6542ccb5 100644 --- a/docs/source/arch_lang/interconnect.rst +++ b/docs/source/arch_lang/interconnect.rst @@ -1,12 +1,12 @@ Interconnection extensions ========================== -This section will introduce extensions on the architecture description file about existing interconnection description. +This section introduces extensions on the architecture description file about existing interconnection description. Directlist ---------- -The original direct connections in the directlist section is doccumented here_. Its description is given below: +The original direct connections in the directlist section are documented here_. Its description is given below: .. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections @@ -32,36 +32,36 @@ Our extension include three more options: * **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: - * x_dir="positive": + * x_dir="positive": - * interconnection_type="column": a column will be connected to a column on the **right**, if it exists. + * interconnection_type="column": a column will be connected to a column on the **right**, if it exists. - * interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists. + * interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists. - * x_dir="negative": + * x_dir="negative": - * interconnection_type="column": a column will be connected to a column on the **left**, if it exists. + * interconnection_type="column": a column will be connected to a column on the **left**, if it exists. - * interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists. + * interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists. * **y_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: - * y_dir="positive": + * y_dir="positive": - * interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists. + * interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists. - * interconnection_type="row": a row will be connected on an **above** row, if it exists. + * interconnection_type="row": a row will be connected on an **above** row, if it exists. - * y_dir="negative": + * y_dir="negative": - * interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists. + * interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists. - * interconnection_type="row": a row will be connected on a row **below**, if it exists. + * interconnection_type="row": a row will be connected on a row **below**, if it exists. Example ------- -For this example, we will study a scan-chain implementation.The description could be: +For this example, we will study a scan-chain implementation. The description could be: .. code-block:: xml @@ -75,15 +75,15 @@ For this example, we will study a scan-chain implementation.The description coul .. figure:: ./figures/point2point_example.png - An example of scan-chain implementation + An example of scan-chain implementation -In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB together. +In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB. Truth table ----------- -A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his own point to point connection, a truth table with our new parameters id provided below. +A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below. :numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate. @@ -91,4 +91,4 @@ A point to point connection can be applied in different ways than showed in the .. figure:: ./figures/point2point_truthtable.png - Point to point truth table + Point to point truth table From 36f7624b95e200cc9172e473b6f3e783823defa5 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 1 Oct 2019 13:07:27 -0600 Subject: [PATCH 252/482] Point to point truth table typo fix --- .../figures/point2point_truthtable.png | Bin 92444 -> 92450 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/docs/source/arch_lang/figures/point2point_truthtable.png b/docs/source/arch_lang/figures/point2point_truthtable.png index b425c6251ff76b7f4fe55e9fa9a787f1089d97f3..d81bab338750a4dfc7aa9a4d65ef718c5141b234 100644 GIT binary patch literal 92450 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zX)6%ELd*R0^=G(Nk*BsaZ^$XXj)k3&vn1q7C}ZjziKMukF~ypbEs?+!v;W;)dm7jop@mz-1~lmC8^QVW27UW?xMGJs z5?XOpd9je>>tL_qI}!Y2_s53TG0M0gbv_ok*q)-XEkp$NU(`{zl2}(nFTK?*fx2bu z7-u`lzYS1kYs+q#50kBLs3_<4?dOQV5-$8E`}6hJ+jYBm6f6sC9eJ@oMvp$T2&hi( zZW$tuHrrwHiTZ%QkTfTsH~xd!^?5}w+f@Ac?TKw`c!zkhvR6qWg6KbXp426_qpdQq z0Rf-(H?(l8c5Vm2fu|v00}Pj%D%a)jEkiol6~s=2k2>r=?66%5x2`B4u?i9REF8mJ&HR0khf5WE9PB9q(_P7akq6$+3MC;Qa&rT&3F4 zwv+CDc(Ca4O|I?M4WQL0tZiCoZfxC78es2L^)`6769GV!)p+*YSsvz6;_X>T*^5!1 zxd67r028wN<1x3IWNT(i5rnnU5KjJHnc-zW{CoF{9QDyNitM@)g}OH_p$3yOqJI4PZMT6*$pm- zh;;QGrk0TlOp5JRKU=wzVhGAd-S>7w5;+J}l|B{>*7^qG+sU>EiM3wIyQp$_2?{RM tW`cn?o~K<1*eAG+!2!7>YL0Gl>`U Date: Tue, 1 Oct 2019 14:49:42 -0600 Subject: [PATCH 253/482] Buggy version but need help on debugging --- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 2 +- .../fpga_x2p/verilog/verilog_compact_netlist.c | 5 +++++ .../vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 17 +++++++++-------- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 5dd8025e2..9413e02fa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2473,7 +2473,7 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordina /* Give a coordinator of a rr switch block, and return its unique mirror */ const RRGSB DeviceRRGSB::get_sb_unique_module(DeviceCoordinator& coordinator) const { - assert(validate_coordinator_edge(coordinator)); + assert(validate_coordinator(coordinator)); size_t sb_unique_module_id = sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()]; return get_sb_unique_module(sb_unique_module_id); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index c0fffbda9..603f37ae1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -1319,15 +1319,20 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, /* Quote Routing structures: Channels */ if (TRUE == compact_routing_hierarchy ) { + fprintf(fp, "//TEST1\n"); dump_compact_verilog_defined_channels(fp, is_explicit_mapping); } else { + fprintf(fp, "//TEST2\n"); + dump_compact_verilog_defined_channels(fp, is_explicit_mapping); dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } /* Quote Routing structures: Switch Boxes */ if (TRUE == compact_routing_hierarchy ) { + fprintf(fp, "//TEST3\n"); dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } else { + fprintf(fp, "//TEST4\n"); dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 1c69aef44..d124f3b05 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2200,7 +2200,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sram_lsb, cur_sram_msb, - VERILOG_PORT_CONKT, is_explicit_mapping); + VERILOG_PORT_CONKT, + false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2297,7 +2298,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2336,9 +2337,9 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ + rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + TRUE, false); /* Dump the direction of the port ! */ } } @@ -2366,7 +2367,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2569,7 +2570,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3861,7 +3862,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info->conf_bits_lsb, cur_cb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } From 7c3ab384101ac7f899ed29cf0d0ed58d563c3aa7 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 1 Oct 2019 16:40:16 -0600 Subject: [PATCH 254/482] Hot fix --- .../tasks/blif_vpr_flow/config/task.conf | 17 ++++++ .../verilog/verilog_compact_netlist.c | 53 +++++++++---------- 2 files changed, 41 insertions(+), 29 deletions(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index d796d6c8a..867f75964 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -60,3 +60,20 @@ vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= + + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] +fix_route_chan_width=300 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_verilog_explicit_mapping= +end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 603f37ae1..112335c0b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -1110,27 +1110,27 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".in%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; case DEC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".out%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; default: @@ -1150,27 +1150,27 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".out%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; case DEC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".in%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; default: @@ -1319,20 +1319,15 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, /* Quote Routing structures: Channels */ if (TRUE == compact_routing_hierarchy ) { - fprintf(fp, "//TEST1\n"); dump_compact_verilog_defined_channels(fp, is_explicit_mapping); } else { - fprintf(fp, "//TEST2\n"); - dump_compact_verilog_defined_channels(fp, is_explicit_mapping); dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } /* Quote Routing structures: Switch Boxes */ if (TRUE == compact_routing_hierarchy ) { - fprintf(fp, "//TEST3\n"); dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } else { - fprintf(fp, "//TEST4\n"); dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/ } From 6b3e1fd410546a181c6cc8d2f28be5fa4c7930db Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 2 Oct 2019 08:54:56 -0600 Subject: [PATCH 255/482] Get backup verilog_routing.c --- .../SRC/fpga_x2p/verilog/verilog_routing.c | 1588 ++++++----------- 1 file changed, 518 insertions(+), 1070 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index d08f5eb15..947f53288 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1,7 +1,7 @@ -/********************************************************************* - * This file includes functions that are used for - * Verilog generation of FPGA routing architecture (global routing) - *********************************************************************/ +/***********************************/ +/* SPICE Modeling for VPR */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ #include #include #include @@ -11,8 +11,6 @@ #include #include #include -#include -#include #include /* Include vpr structs*/ @@ -26,12 +24,9 @@ #include "route_common.h" #include "vpr_utils.h" -#include "vtr_assert.h" - /* Include SPICE support headers*/ #include "linkedlist.h" #include "rr_blocks.h" -#include "rr_blocks_utils.h" #include "fpga_x2p_types.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_backannotate_utils.h" @@ -39,451 +34,18 @@ #include "fpga_x2p_pbtypes_utils.h" #include "fpga_x2p_bitstream_utils.h" #include "fpga_x2p_globals.h" -#include "fpga_x2p_naming.h" -#include "mux_utils.h" -#include "module_manager.h" -#include "module_manager_utils.h" /* Include Verilog support headers*/ #include "verilog_global.h" #include "verilog_utils.h" -#include "verilog_writer_utils.h" #include "verilog_routing.h" -/******************************************************************** - * Print local wires that are used for SRAM configuration - * This function is supposed to be used by Verilog generation - * of switch blocks - * It will count the number of switch blocks, which is the - * port width for local wires when Configuration chain is used - ********************************************************************/ -static -void print_verilog_switch_block_local_sram_wires(std::fstream& fp, - const RRGSB& rr_gsb, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, - const size_t& port_size) { - size_t local_port_size = port_size; - if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { - /* Plus 1 for the wire size to connect to the tail of the configuration chain */ - local_port_size = find_switch_block_number_of_muxes(rr_gsb) + 1; - } - print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); -} - -/********************************************************************* - * Generate the Verilog module for a routing channel - * Routing track wire, which is 1-input and dual output - * This type of wires are used in the global routing architecture. - * One of the output is wired to another Switch block multiplexer, - * while the mid-output is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * - * IMPORTANT: This function is designed for outputting unique Verilog modules - * of routing channels - * - * TODO: This function should be adapted to the RRGraph object - *********************************************************************/ -static -void print_verilog_routing_unique_chan_subckt(ModuleManager& module_manager, - const std::string& verilog_dir, - const std::string& subckt_dir, - const size_t& rr_chan_subckt_id, - const RRChan& rr_chan) { - std::string fname_prefix; - - /* TODO: use a constexpr String arrary to replace this switch cases? */ - /* Find the prefix for the Verilog file name */ - switch (rr_chan.get_type()) { - case CHANX: - fname_prefix = std::string(chanx_verilog_file_name_prefix); - break; - case CHANY: - fname_prefix = std::string(chany_verilog_file_name_prefix); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", - __FILE__, __LINE__); - exit(1); - } - - std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, rr_chan_subckt_id, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id)); - - /* Add ports to the module */ - /* For the LEFT side of a X-direction routing channel - * or the BOTTOM bottom side of a Y-direction routing channel - * Routing Resource Nodes in INC_DIRECTION are inputs of the module - * - * For the RIGHT side of a X-direction routing channel - * or the TOP bottom side of a Y-direction routing channel - * Routing Resource Nodes in INC_DIRECTION are outputs of the module - * - * An example of X-direction routing channel consisting of W routing nodes: - * +--------------------------+ - * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) - * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) - * ... ... ... ... - * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) - * +--------------------------+ - * - * An example of Y-direction routing channel consisting of W routing nodes: - * - * nodeA nodeB nodeX - * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) - * ^ | ... | - * | v v - * +------------------------------ ... -------+ - * | out[0] in[1] in[X] | - * | | - * | | - * | in[0] out[1] ... out[X] | - * +------------------------------ ... -------+ - * ^ | | - * | v v - * nodeA nodeB nodeX - * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) - */ - /* Add ports at LEFT/BOTTOM side of the module */ - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - switch (rr_chan.get_node(itrack)->direction) { - case INC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - break; - } - case DEC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - } - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu]_in/out[%lu]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(rr_chan.get_type()), - rr_chan_subckt_id, itrack); - exit(1); - } - } - /* Add ports at RIGHT/TOP side of the module */ - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - switch (rr_chan.get_node(itrack)->direction) { - case INC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - } - case DEC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - break; - } - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu]_in/out[%lu]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(rr_chan.get_type()), - rr_chan_subckt_id, itrack); - exit(1); - } - } - /* Add middle-point output for connection box inputs */ - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - /* TODO: naming should be more flexible !!! */ - BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Print short-wire connection: - * - * in[i] ----------> out[i] - * | - * +-----> mid_out[i] - */ - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - /* short connecting inputs and outputs: - * length of metal wire and parasitics are handled by semi-custom flow - */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); - print_verilog_wire_connection(fp, output_port, input_port, false); - print_verilog_wire_connection(fp, mid_output_port, input_port, false); - } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the linked list */ - /* Uncomment this when it is ready - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ - - return; -} - -/********************************************************************* - * Generate the Verilog module for a routing channel - * Routing track wire, which is 1-input and dual output - * This type of wires are used in the global routing architecture. - * One of the output is wired to another Switch block multiplexer, - * while the mid-output is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * - * IMPORTANT: This function is designed for outputting non-unique Verilog modules - * of routing channels - * - * TODO: This function should be adapted to the RRGraph object - *********************************************************************/ -static -void print_verilog_routing_chan_subckt(ModuleManager& module_manager, - const std::string& verilog_dir, - const std::string& subckt_dir, - const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int chan_width = 0; - t_rr_node** chan_rr_nodes = NULL; - - std::string fname_prefix; - - /* TODO: use a constexpr String arrary to replace this switch cases? */ - /* Find the prefix for the Verilog file name */ - switch (chan_type) { - case CHANX: - fname_prefix = std::string(chanx_verilog_file_name_prefix); - break; - case CHANY: - fname_prefix = std::string(chany_verilog_file_name_prefix); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", - __FILE__, __LINE__); - exit(1); - } - - std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, chan_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(chan_type, chan_coordinate)); - - /* Collect rr_nodes for Tracks for chanx[ix][iy] */ - chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, chan_coordinate.x(), chan_coordinate.y(), - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Add ports to the module */ - /* For the LEFT side of a X-direction routing channel - * or the BOTTOM bottom side of a Y-direction routing channel - * Routing Resource Nodes in INC_DIRECTION are inputs of the module - * - * For the RIGHT side of a X-direction routing channel - * or the TOP bottom side of a Y-direction routing channel - * Routing Resource Nodes in INC_DIRECTION are outputs of the module - * - * An example of X-direction routing channel consisting of W routing nodes: - * +--------------------------+ - * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) - * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) - * ... ... ... ... - * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) - * +--------------------------+ - * - * An example of Y-direction routing channel consisting of W routing nodes: - * - * nodeA nodeB nodeX - * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) - * ^ | ... | - * | v v - * +------------------------------ ... -------+ - * | out[0] in[1] in[X] | - * | | - * | | - * | in[0] out[1] ... out[X] | - * +------------------------------ ... -------+ - * ^ | | - * | v v - * nodeA nodeB nodeX - * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) - */ - /* Add ports at LEFT/BOTTOM side of the module */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - break; - } - case DEC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - } - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(chan_type), - chan_coordinate.x(), chan_coordinate.y(), itrack); - exit(1); - } - } - /* Add ports at RIGHT/TOP side of the module */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - } - case DEC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - break; - } - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(chan_type), - chan_coordinate.x(), chan_coordinate.y(), itrack); - exit(1); - } - } - /* Add middle-point output for connection box inputs */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - /* TODO: naming should be more flexible !!! */ - BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Print short-wire connection: - * - * in[i] ----------> out[i] - * | - * +-----> mid_out[i] - */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - /* short connecting inputs and outputs: - * length of metal wire and parasitics are handled by semi-custom flow - */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); - print_verilog_wire_connection(fp, output_port, input_port, false); - print_verilog_wire_connection(fp, mid_output_port, input_port, false); - } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the linked list */ - /* Uncomment this when it is ready - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ - - /* Free */ - my_free(chan_rr_nodes); - - return; -} - - static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, size_t rr_chan_subckt_id, - const RRChan& rr_chan) { + const RRChan& rr_chan, + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -517,11 +79,9 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1)); fprintf(fp, "\n"); /* dump global ports */ - /* if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } - */ /* Inputs and outputs, * Rules for CHANX: * print left-hand ports(in) first, then right-hand ports(out) @@ -611,7 +171,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int num_segment) { + int num_segment, + bool is_explicit_mapping) { int itrack, iseg, cost_index; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -656,11 +217,9 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(chan_type, x, y)); fprintf(fp, "\n"); /* dump global ports */ - /* if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } - */ /* Inputs and outputs, * Rules for CHANX: * print left-hand ports(in) first, then right-hand ports(out) @@ -754,6 +313,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping) { int height; @@ -801,7 +361,7 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(unique_x, unique_y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -962,7 +522,8 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, enum e_side chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node) { + t_rr_node* drive_rr_node, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -1005,6 +566,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, + 0, 0, /* No explicit mapping*/ FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: @@ -1107,6 +669,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, + 0, /*Used in more recent version*/ + 0, /*Used in more recent version*/ FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: @@ -1207,12 +771,16 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Find grid_x and grid_y */ grid_x = drive_rr_nodes[inode]->xlow; grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print a grid pin */ fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ + FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1276,7 +844,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1421,7 +989,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int cur_bl, cur_wl; t_spice_model* mem_model = NULL; char* mem_subckt_name = NULL; - int num_input_port, num_output_port; + int num_input_port, num_output_port, num_sram_port; /* Check the file handler*/ if (NULL == fp) { @@ -1469,7 +1037,9 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, false); + grid_x, grid_y, + 0,0,/*No explicit mapping */ + FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1533,7 +1103,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -1907,11 +1477,13 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); + num_drive_rr_nodes, cur_rr_node, + is_explicit_mapping); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], + is_explicit_mapping); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, @@ -2148,409 +1720,137 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ + +/* Dump port list of a subckt describing a side of a switch block + * Only output ports will be printed on the specified side + * Only input ports will be printed on the other sides + */ static -BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const PORTS& cur_rr_node_direction) { - /* Get the index in sb_info of cur_rr_node */ - int index = rr_sb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); - /* Make sure this node is included in this sb_info */ - VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); - - DeviceCoordinator chan_rr_node_coordinator = rr_sb.get_side_block_coordinator(chan_side); - - vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); - std::string chan_port_name = generate_routing_track_port_name(rr_sb.get_chan_node(chan_side, index)->type, - chan_port_coord, index, - rr_sb.get_chan_node_direction(chan_side, index)); - return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */ -} - -/********************************************************************* - * Generate an input port for routing multiplexer inside the switch block - * In addition to give the Routing Resource node of the input - * Users should provide the side of input, which is different case by case: - * 1. When the input is a pin of a CLB/Logic Block, the input_side should - * be the side of the node on its grid! - * For example, the input pin is on the top side of a switch block - * but on the right side of a switch block - * +--------+ - * | | - * | Grid |---+ - * | | | - * +--------+ v input_pin - * +----------------+ - * | Switch Block | - * +----------------+ - * 2. When the input is a routing track, the input_side should be - * the side of the node locating on the switch block - ********************************************************************/ -static -BasicPort generate_switch_block_input_port(const RRGSB& rr_sb, - const e_side& input_side, - t_rr_node* input_rr_node) { - BasicPort input_port; - /* Generate the input port object */ - switch (input_rr_node->type) { - /* case SOURCE: */ - case OPIN: { - /* Find the coordinator (grid_x and grid_y) for the input port */ - vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); - std::string input_port_name = generate_grid_side_port_name(input_port_coord, - input_side, - input_rr_node->ptc_num); - input_port.set_name(input_port_name); - input_port.set_width(1); /* Every grid output has a port size of 1 */ - break; - } - case CHANX: - case CHANY: { - input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_side, input_rr_node, IN_PORT); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); +void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, + const RRGSB& rr_sb, + enum e_side sb_side, + size_t seg_id, + boolean dump_port_type, + bool is_explicit_mapping) { + /* Check file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid file handler!\n", + __FILE__, __LINE__); exit(1); - } + } - return input_port; -} + /* Create a side manager */ + Side sb_side_manager(sb_side); -/********************************************************************* - * Generate a list of input ports for routing multiplexer inside the switch block - ********************************************************************/ -static -std::vector generate_switch_block_input_ports(const RRGSB& rr_sb, - const std::vector& input_rr_nodes) { - std::vector input_ports; + for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { + Side side_manager(side); + /* Print ports */ + fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str()); + DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); - for (auto input_rr_node : input_rr_nodes) { - enum e_side input_pin_side = NUM_SIDES; - switch (input_rr_node->type) { - case OPIN: - input_pin_side = rr_sb.get_opin_node_grid_side(input_rr_node); - break; - case CHANX: - case CHANY: { - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_sb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); - VTR_ASSERT(NUM_SIDES != input_pin_side); - break; + for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { + switch (rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + case OUT_PORT: + /* if this is the specified side, we only consider output ports */ + if (sb_side_manager.get_side() != side_manager.get_side()) { + break; + } + /* Bypass unwanted segments */ + if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { + continue; + } + fprintf(fp, " "); + if (TRUE == dump_port_type) { + fprintf(fp, "output "); + is_explicit_mapping = false; /* Both cannot be true together */ + } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); + break; + case IN_PORT: + /* if this is not the specified side, we only consider input ports */ + if (sb_side_manager.get_side() == side_manager.get_side()) { + break; + } + fprintf(fp, " "); + if (TRUE == dump_port_type) { + fprintf(fp, "input "); + } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack); + exit(1); + } } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - input_ports.push_back(generate_switch_block_input_port(rr_sb, input_pin_side, input_rr_node)); + + /* Dump OPINs of adjacent CLBs */ + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(port_coordinator); + for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + fprintf(fp, " "); + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ + rr_sb.get_opin_node(side_manager.get_side(), inode)->ptc_num, + rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ + if (FALSE == dump_port_type) { + fprintf(fp, ",\n"); + } + } } - - return input_ports; -} - -/********************************************************************* - * Print a short interconneciton in switch box - * There are two cases should be noticed. - * 1. The actual fan-in of cur_rr_node is 0. In this case, - the cur_rr_node need to be short connected to itself which is on the opposite side of this switch - * 2. The actual fan-in of cur_rr_node is 0. In this case, - * The cur_rr_node need to connected to the drive_rr_node - ********************************************************************/ -static -void print_verilog_unique_switch_box_short_interc(std::fstream& fp, - const RRGSB& rr_sb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - t_rr_node* drive_rr_node) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Find the name of output port */ - BasicPort output_port = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); - enum e_side input_pin_side = chan_side; - - /* Generate the input port object */ - switch (drive_rr_node->type) { - case OPIN: - input_pin_side = rr_sb.get_opin_node_grid_side(drive_rr_node); - break; - case CHANX: - case CHANY: { - /* This should be an input in the data structure of RRGSB */ - if (cur_rr_node == drive_rr_node) { - /* To be strict, the input should locate on the opposite side. - * Use the else part if this may change in some architecture. - */ - Side side_manager(chan_side); - input_pin_side = side_manager.get_opposite(); - } else { - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_sb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); - } - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - /* Find the name of input port */ - BasicPort input_port = generate_switch_block_input_port(rr_sb, input_pin_side, drive_rr_node); - - /* Print the wire connection in Verilog format */ - print_verilog_comment(fp, std::string("----- Short connection " + output_port.get_name() + " -----")); - print_verilog_wire_connection(fp, output_port, input_port, false); - fp << std::endl; -} - -/********************************************************************* - * Print a Verilog instance of a routing multiplexer as well as - * associated memory modules for a connection inside a switch block - ********************************************************************/ -static -void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info, - const ModuleId& sb_module, - const RRGSB& rr_sb, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const std::vector& drive_rr_nodes, - const size_t& switch_index, - const bool& use_explicit_mapping) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Check */ - /* Check current rr_node is CHANX or CHANY*/ - VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Get the circuit model id of the routing multiplexer */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - - /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); - - /* Get the MUX instance id from the module manager */ - size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module); - - /* Print the input bus for the inputs of a multiplexer - * We use the datapath input size (mux_size) to name the bus - * just to following the naming convention when the tool is built - * The bus port size should be the input size of multiplexer implementation - */ - BasicPort inbus_port; - inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); - inbus_port.set_width(datapath_mux_size); - - /* Generate input ports that are wired to the input bus of the routing multiplexer */ - std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); - /* Connect input ports to bus */ - print_verilog_comment(fp, std::string("----- BEGIN A local bus wire for multiplexer inputs -----")); - fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; - print_verilog_comment(fp, std::string("----- END A local bus wire for multiplexer inputs -----")); - fp << std::endl; - - /* Find the number of reserved configuration bits for the routing multiplexer */ - size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); - - /* Find the number of configuration bits for the routing multiplexer */ - size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - - /* Print the configuration bus for the routing multiplexers */ - print_verilog_comment(fp, std::string("----- BEGIN Local wires to group configuration ports -----")); - print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, - datapath_mux_size, mux_instance_id, - mux_num_reserved_config_bits, mux_num_config_bits); - print_verilog_comment(fp, std::string("----- END Local wires to group configuration ports -----")); - fp << std::endl; - - /* Dump ports visible only during formal verification */ - print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); - print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); - /* Print the SRAM configuration ports for formal verification */ - /* TODO: align with the port width of formal verification port of SB module */ - print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, - datapath_mux_size, mux_instance_id, mux_num_config_bits); - print_verilog_endif(fp); - print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); - fp << std::endl; - - /* Instanciate the MUX Module */ - /* Create port-to-port map */ - std::map mux_port2port_name_map; - - /* Link input bus port to Switch Block inputs */ - std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == mux_model_input_ports.size()); - /* Use the port name convention in the circuit library */ - mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_input_ports[0])] = inbus_port; - - /* Link output port to Switch Block outputs */ - std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == mux_model_output_ports.size()); - /* Use the port name convention in the circuit library */ - mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_output_ports[0])] = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); - - /* Link SRAM port to different configuraton port for the routing multiplexer - * Different design technology requires different configuration bus! - */ - std::vector mux_model_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); - VTR_ASSERT( 1 == mux_model_sram_ports.size() ); - /* For the regular SRAM port, module port use the same name */ - std::string mux_module_sram_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]); - BasicPort mux_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), - mux_num_config_bits); - mux_port2port_name_map[mux_module_sram_port_name] = mux_config_port; - - /* For the inverted SRAM port */ - std::string mux_module_sram_inv_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]) + std::string("_inv"); - BasicPort mux_config_inv_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), - mux_num_config_bits); - mux_port2port_name_map[mux_module_sram_inv_port_name] = mux_config_inv_port; - - /* Print an instance of the MUX Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a routing multiplexer -----")); - print_verilog_module_instance(fp, module_manager, sb_module, mux_module, mux_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of a routing multiplexer -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(sb_module, mux_module); - - /* Instanciate memory modules */ - /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); - ModuleId mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - - /* Create port-to-port map */ - std::map mem_port2port_name_map; - - /* TODO: Make the port2port map generation more generic!!! */ - std::vector config_ports; - config_ports.push_back(BasicPort(generate_local_config_bus_port_name(), mux_instance_id - 1, mux_instance_id)); - std::vector mem_output_ports; - mem_output_ports.push_back(mux_config_port); - mem_output_ports.push_back(mux_config_inv_port); - mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, - config_ports, - mem_output_ports, - circuit_lib.design_tech_type(mux_model), - cur_sram_orgz_info->type); - - /* Print an instance of the MUX Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); - print_verilog_module_instance(fp, module_manager, sb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(sb_module, mem_module); - - /* Create the path of the input of multiplexer in the hierarchy - * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! - */ - std::string mux_input_hie_path = std::string(rr_sb.gen_sb_verilog_instance_name()) + std::string("/") - + mux_module_name + std::string("_") - + std::to_string(mux_instance_id) + std::string("_/in"); - cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); + + return; } -/********************************************************************* - * Print the Verilog modules for a interconnection inside switch block - * The interconnection could be either a wire or a routing multiplexer, - * which depends on the fan-in of the rr_nodes in the switch block - ********************************************************************/ -static -void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info, - const ModuleId& sb_module, - const RRGSB& rr_sb, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const e_side& chan_side, - const size_t& chan_node_id, - const bool& use_explicit_mapping) { - std::vector drive_rr_nodes; - - /* Get the node */ - t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id); - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - if (false == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { - for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { - drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); - } - /* Special: if there are zero-driver nodes. We skip here */ - if (0 == drive_rr_nodes.size()) { - return; - } - } - - if (0 == drive_rr_nodes.size()) { - /* Print a special direct connection*/ - print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - cur_rr_node); - } else if (1 == drive_rr_nodes.size()) { - /* Print a direct connection*/ - print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - drive_rr_nodes[DEFAULT_SWITCH_ID]); - } else if (1 < drive_rr_nodes.size()) { - /* Print the multiplexer, fan_in >= 2 */ - print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, - sb_module, rr_sb, circuit_lib, mux_lib, - rr_switches, chan_side, cur_rr_node, - drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], - use_explicit_mapping); - } /*Nothing should be done else*/ -} - -/********************************************************************* - * Generate the Verilog module for a Switch Box. - * A Switch Box module consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * Location of a Switch Box in FPGA fabric: +/* Task: Print the subckt of a side of a Switch Box. + * For TOP side: + * 1. Channel Y [x][y+1] inputs + * 2. Grid[x][y+1] Right side outputs pins + * 3. Grid[x+1][y+1] Left side output pins + * For RIGHT side: + * 1. Channel X [x+1][y] inputs + * 2. Grid[x+1][y+1] Bottom side output pins + * 3. Grid[x+1][y] Top side output pins + * For BOTTOM side: + * 1. Channel Y [x][y] outputs + * 2. Grid[x][y] Right side output pins + * 3. Grid[x+1][y] Left side output pins + * For LEFT side: + * 1. Channel X [x][y] outputs + * 2. Grid[x][y] Top side output pins + * 3. Grid[x][y+1] Bottom side output pins * * -------------- -------------- * | | | | @@ -2569,45 +1869,165 @@ void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, * | [x][y] | [x][y] | [x+1][y] | * | | | | * -------------- -------------- - * - * Switch Block pin location map - * - * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] - * right_pins inputs/outputs left_pins - * | ^ | - * | | | - * v v v - * +-----------------------------------------------+ - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * bottom_pins---->| |<---- bottom_pins - * | | - * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] - * inputs/outputs<--->| |<---> inputs/outputs - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * top_pins---->| |<---- top_pins - * | | - * +-----------------------------------------------+ - * ^ ^ ^ - * | | | - * | v | - * Grid[x][y] ChanY[x][y] Grid[x+1][y] - * right_pins inputs/outputs left_pins - * - * - ********************************************************************/ + */ static -void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& subckt_dir, - const RRGSB& rr_sb, - const bool& is_explicit_mapping) { - /* TODO: move this part to another function where we count the conf bits for all the switch blocks !!!*/ +void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, char* subckt_dir, + size_t module_id, size_t seg_id, + const RRGSB& rr_sb, enum e_side side, + bool is_explicit_mapping) { + FILE* fp = NULL; + char* fname = NULL; + Side side_manager(side); + + /* Get the channel width on this side, if it is zero, we return */ + if (0 == rr_sb.get_chan_width(side)) { + return; + } + + /* Count the number of configuration bits to be consumed by this Switch block */ + int num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + int num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); + /* Estimate the sram_verilog_model->cnt */ + int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + int esti_sram_cnt = cur_num_sram + num_conf_bits; + + /* Create file name */ + std::string fname_prefix(sb_verilog_file_name_prefix); + fname_prefix += side_manager.c_str(); + + std::string file_description("Unique module for Switch Block side: "); + file_description += side_manager.c_str(); + file_description += "seg"; + file_description += std::to_string(seg_id); + + /* Create file handler */ + fp = verilog_create_one_subckt_file(subckt_dir, file_description.c_str(), + fname_prefix.c_str(), module_id, seg_id, &fname); + + /* Print preprocessing flags */ + verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Comment lines */ + fprintf(fp, + "//----- Verilog Module of Unique Switch Box[%lu][%lu] at Side %s, Segment id: %lu -----\n", + rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str(), seg_id); + /* Print the definition of subckt*/ + fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { + fprintf(fp, ",\n"); + } + + dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, + seg_id, TRUE, + false); + + /* Put down configuration port */ + /* output of each configuration bit */ + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + 0, + num_reserved_conf_bits - 1, + VERILOG_PORT_INPUT); + if (0 < num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + dump_verilog_sram_ports(fp, cur_sram_orgz_info, + cur_num_sram, + esti_sram_cnt - 1, + VERILOG_PORT_INPUT); + + /* Dump ports only visible during formal verification*/ + if (0 < num_conf_bits) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + cur_num_sram, + esti_sram_cnt - 1, + VERILOG_PORT_INPUT, false); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, "); \n"); + + /* Local wires for memory configurations */ + dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, + cur_num_sram, + esti_sram_cnt - 1); + + /* Put down all the multiplexers */ + fprintf(fp, "//----- %s side Multiplexers -----\n", + side_manager.c_str()); + for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { + assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) + ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); + /* We care INC_DIRECTION tracks at this side*/ + if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + /* Bypass unwanted segments */ + if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { + continue; + } + dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, + side_manager.get_side(), + itrack, is_explicit_mapping); + } + } + + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, + "//----- END Verilog Module of Switch Box[%lu][%lu] Side %s -----\n\n", + rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str()); + + /* Check */ + assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); + + /* Close file handler */ + fclose(fp); + + /* Add fname to the linked list */ + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + + /* Free chan_rr_nodes */ + my_free(fname); + + return; +} + +/* Task: Print the subckt of a Switch Box. + * Call the four submodules dumped in function: unique_side_module + * + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + */ +static +void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, char* subckt_dir, + const RRGSB& rr_sb, + bool is_explicit_mapping) { + FILE* fp = NULL; + char* fname = NULL; + /* Count the number of configuration bits to be consumed by this Switch block */ int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); /* Count the number of reserved configuration bits to be consumed by this Switch block */ @@ -2615,58 +2035,45 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage /* Estimate the sram_verilog_model->cnt */ int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - rr_gsb.set_sb_num_reserved_conf_bits(size_t(num_reserved_conf_bits)); - rr_gsb.set_sb_conf_bits_lsb(size_t(cur_num_sram)); - rr_gsb.set_sb_conf_bits_msb(size_t(cur_num_sram + num_conf_bits - 1)); + rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits); + rr_gsb.set_sb_conf_bits_lsb(cur_num_sram); + rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1); - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); + /* Create file handler */ + fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ", + sb_verilog_file_name_prefix, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), &fname); /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); + verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); - - /* Add ports to the module */ - /* Global ports: - * In the circuit_library, find all the circuit models that may be included in the Switch Block - * Collect the global ports from the circuit_models and merge with the same name - */ - std::vector global_ports = find_switch_block_global_ports(rr_gsb, circuit_lib, rr_switches); - for (const auto& port : global_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT); + /* Comment lines */ + fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + /* Print the definition of subckt*/ + fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { + fprintf(fp, ",\n"); } - /* Add routing channel ports at each side of the GSB */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); + /* Print ports */ + fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.c_str()); DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); - std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); + case OUT_PORT: + fprintf(fp, " output %s,\n", + gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); break; case IN_PORT: - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + fprintf(fp, " input %s,\n", + gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); break; default: vpr_printf(TIO_MESSAGE_ERROR, @@ -2676,87 +2083,156 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage } } /* Dump OPINs of adjacent CLBs */ + fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.c_str()); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string port_name = generate_grid_side_port_name(port_coord, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); - BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ - /* Grid outputs are inputs of switch blocks */ - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + fprintf(fp, " "); + dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + 0,0, /*No explicit mapping */ + TRUE, false); /* Dump the direction of the port ! */ } } - /* Add configuration ports */ + /* Put down configuration port */ + /* output of each configuration bit */ /* Reserved sram ports */ + fprintf(fp, "//----- Reserved SRAM Ports -----\n"); if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) { - /* Check: this SRAM organization type must be memory-bank ! */ - VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); - /* Generate a list of ports */ - add_reserved_sram_ports_to_module_manager(module_manager, module_id, - rr_gsb.get_sb_num_reserved_conf_bits()); + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + rr_gsb.get_sb_reserved_conf_bits_lsb(), + rr_gsb.get_sb_reserved_conf_bits_msb(), + VERILOG_PORT_INPUT); + fprintf(fp, ",\n"); } - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - /* Normal sram ports */ + fprintf(fp, "//----- Regular SRAM Ports -----\n"); + dump_verilog_sram_ports(fp, cur_sram_orgz_info, + rr_gsb.get_sb_conf_bits_lsb(), + rr_gsb.get_sb_conf_bits_msb(), + VERILOG_PORT_INPUT); + + /* Dump ports only visible during formal verification*/ if (0 < rr_gsb.get_sb_num_conf_bits()) { - add_sram_ports_to_module_manager(module_manager, module_id, - circuit_lib, sram_model, cur_sram_orgz_info->type, - rr_gsb.get_sb_num_conf_bits()); - /* Add ports only visible during formal verification to the module */ - add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, - std::string(verilog_formal_verification_preproc_flag), - rr_gsb.get_sb_num_conf_bits()); + fprintf(fp, "\n"); + fprintf(fp, "//----- SRAM Ports for formal verification -----\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + rr_gsb.get_sb_conf_bits_lsb(), + rr_gsb.get_sb_conf_bits_msb(), + VERILOG_PORT_INPUT, + false); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); } + fprintf(fp, "); \n"); - /* Print module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish printing ports */ - - print_verilog_comment(fp, std::string("---- BEGIN local wires for SRAM data ports ----")); /* Local wires for memory configurations */ - print_verilog_switch_block_local_sram_wires(fp, rr_gsb, circuit_lib, sram_model, cur_sram_orgz_info->type, - rr_gsb.get_sb_num_conf_bits()); - print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); + dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, + rr_gsb.get_sb_conf_bits_lsb(), + rr_gsb.get_sb_conf_bits_msb()); - /* TODO: Print routing multiplexers */ + /* Call submodules */ + int cur_sram_lsb = cur_num_sram; + int cur_sram_msb = cur_num_sram; for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); - print_verilog_comment(fp, std::string("----- " + side_manager.to_string() + " side Routing Multiplexers -----")); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, module_id, rr_sb, - circuit_lib, mux_lib, rr_switches, - side_manager.get_side(), - itrack, is_explicit_mapping); - } + fprintf(fp, "//----- %s side Submodule -----\n", + side_manager.c_str()); + + /* Get the channel width on this side, if it is zero, we return */ + if (0 == rr_gsb.get_chan_width(side_manager.get_side())) { + fprintf(fp, "//----- %s side has zero channel width, module dump skipped -----\n", + side_manager.c_str()); + continue; + } + + /* get segment ids */ + std::vector seg_ids = rr_gsb.get_chan(side_manager.get_side()).get_segment_ids(); + for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { + fprintf(fp, "//----- %s side Submodule with Segment id: %lu -----\n", + side_manager.c_str(), seg_ids[iseg]); + + /* Count the number of configuration bits to be consumed by this Switch block */ + int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); + + /* Cache the sram counter */ + cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1; + + /* Instanciate the subckt*/ + fprintf(fp, + "%s %s ( \n", + rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]), + rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg])); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { + fprintf(fp, ",\n"); + } + + dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping); + + /* Put down configuration port */ + /* output of each configuration bit */ + /* Reserved sram ports */ + dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, + 0, + side_num_reserved_conf_bits - 1, + VERILOG_PORT_CONKT); + if (0 < side_num_reserved_conf_bits) { + fprintf(fp, ",\n"); + } + /* Normal sram ports */ + dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, + cur_sram_lsb, + cur_sram_msb, + VERILOG_PORT_CONKT, is_explicit_mapping); + + /* Dump ports only visible during formal verification*/ + if (0 < side_num_conf_bits) { + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); + fprintf(fp, ",\n"); + dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, + cur_sram_lsb, + cur_sram_msb, + VERILOG_PORT_CONKT, + false); + fprintf(fp, "\n"); + fprintf(fp, "`endif\n"); + } + fprintf(fp, "); \n"); + + /* Update sram_lsb */ + cur_sram_lsb = cur_sram_msb + 1; } } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; + /* checker */ + assert(cur_sram_msb == cur_num_sram + num_conf_bits - 1); + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + /* Close file handler */ - fp.close(); + fclose(fp); /* Add fname to the linked list */ - /* - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + + /* Free chan_rr_nodes */ + my_free(fname); return; } + + /* Task: Print the subckt of a Switch Box. * A Switch Box subckt consists of following ports: * 1. Channel Y [x][y] inputs @@ -2822,7 +2298,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2861,7 +2337,9 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ + rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + TRUE, false); /* Dump the direction of the port ! */ } } @@ -2889,7 +2367,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3063,6 +2541,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -3090,7 +2570,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3311,6 +2791,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3321,10 +2802,10 @@ void dump_verilog_connection_box_short_interc(FILE* fp, /* SRC rr_node is the IPIN of a grid.*/ -static void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + bool is_explicit_mapping) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, side, index; @@ -3388,6 +2869,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3514,7 +2996,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3545,6 +3027,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3761,7 +3244,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3792,6 +3275,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,/*No explicit mapping*/ + 0,/*No explicit mapping*/ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3930,7 +3415,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); + dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node, is_explicit_mapping); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, @@ -4121,6 +3606,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, + 0,/*No explicit mapping */ + 0,/*No explicit mapping */ TRUE, false); } @@ -4324,6 +3811,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert((1 == side_cnt)||(2 == side_cnt)); side_cnt = 0; + //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print the ports of grids*/ /* only check ipin_rr_nodes of cur_cb_info */ for (side = 0; side < cur_cb_info->num_sides; side++) { @@ -4341,6 +3829,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ TRUE, is_explicit_mapping); } @@ -4372,7 +3862,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info->conf_bits_lsb, cur_cb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -4433,62 +3923,21 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ return; } -/********************************************************************* - * Generate the port name for a Grid - *********************************************************************/ -std::string generate_grid_side_port_name(const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - int height = get_grid_pin_height(coordinate.x(), coordinate.y(), (int)pin_id); - if (1 != grid[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", - __FILE__, __LINE__, - coordinate.x(), coordinate.y(), height, convert_side_index_to_string(side), pin_id); - exit(1); - } - return generate_grid_port_name(coordinate, (size_t)height, side, pin_id, true); -} - -/********************************************************************* - * Top-level function: - * Build the Verilog modules for global routing architecture - * 1. Routing channels - * 2. Switch blocks - * 3. Connection blocks - * - * This function supports two styles in Verilog generation: - * 1. Explicit port mapping - * 2. Inexplicit port mapping - * - * This function also supports high hierarchical Verilog generation - * (when the compact_routing_hierarchy is set true) - * In this mode, Verilog generation will be done for only those - * unique modules in terms of internal logics - *********************************************************************/ -void print_verilog_routing_resources(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* subckt_dir, - const t_arch& arch, - const t_det_routing_arch& routing_arch, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, /* To be replaced by RRGraph object */ - t_ivec*** LL_rr_node_indices, - t_rr_indexed_data* LL_rr_indexed_data, - const t_fpga_spice_opts& FPGA_SPICE_Opts) { - VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); +/* Top Function*/ +/* Build the routing resource SPICE sub-circuits*/ +void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + t_arch arch, + t_det_routing_arch* routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, + t_rr_indexed_data* LL_rr_indexed_data, + t_fpga_spice_opts FPGA_SPICE_Opts) { + assert(UNI_DIRECTIONAL == routing_arch->directionality); boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy; boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog; - - /* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */ - std::vector rr_switches; - for (short i = 0; i < routing_arch.num_switch; ++i) { - rr_switches.push_back(switch_inf[i]); - } - /* Two major tasks: * 1. Generate sub-circuits for Routing Channels * 2. Generate sub-circuits for Switch Boxes @@ -4513,19 +3962,13 @@ void print_verilog_routing_resources(ModuleManager& module_manager, /* X - channels [1...nx][0..ny]*/ for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANX, ichan)); - - print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), - ichan, device_rr_chan.get_module(CHANX, ichan)); + ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANY, ichan)); - - print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), - ichan, device_rr_chan.get_module(CHANY, ichan)); + ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping); } } else { /* Output the full array of routing channels */ @@ -4534,11 +3977,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, for (int ix = 1; ix < (nx + 1); ix++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments); - - vtr::Point chan_coordinate((size_t)ix, (size_t)iy); - print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANX, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + arch.num_segments, explicit_port_mapping); } } /* Y - channels [1...ny][0..nx]*/ @@ -4547,11 +3986,7 @@ void print_verilog_routing_resources(ModuleManager& module_manager, for (int iy = 1; iy < (ny + 1); iy++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments); - - vtr::Point chan_coordinate((size_t)ix, (size_t)iy); - print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANY, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + arch.num_segments, explicit_port_mapping); } } } @@ -4561,16 +3996,28 @@ void print_verilog_routing_resources(ModuleManager& module_manager, /* Create a snapshot on sram_orgz_info */ t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); + /* Output unique side modules + for (size_t side = 0; side < device_rr_gsb.get_max_num_sides(); ++side) { + Side side_manager(side); + for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) { + for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) { + const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg); + size_t seg_id = device_rr_gsb.get_segment_id(iseg); + dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping); + } + } + } + */ + /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); + /* + dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, + subckt_dir, unique_mirror, explicit_port_mapping); + */ dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, explicit_port_mapping); - print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib, - rr_switches, - cur_sram_orgz_info, std::string(verilog_dir), - std::string(subckt_dir), unique_mirror, - explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -4680,3 +4127,4 @@ void print_verilog_routing_resources(ModuleManager& module_manager, return; } + From 01ff48415898aab07cedc91ec089e200e2ef6797 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 2 Oct 2019 10:22:28 -0600 Subject: [PATCH 256/482] Explicit verilog passing all tests --- .../SRC/fpga_x2p/verilog/verilog_routing.c | 1542 +++++++++++------ .../verilog/verilog_top_netlist_utils.c | 10 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 11 +- 3 files changed, 1074 insertions(+), 489 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 947f53288..ff68546a3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1,7 +1,7 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ +/********************************************************************* + * This file includes functions that are used for + * Verilog generation of FPGA routing architecture (global routing) + *********************************************************************/ #include #include #include @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include /* Include vpr structs*/ @@ -24,9 +26,12 @@ #include "route_common.h" #include "vpr_utils.h" +#include "vtr_assert.h" + /* Include SPICE support headers*/ #include "linkedlist.h" #include "rr_blocks.h" +#include "rr_blocks_utils.h" #include "fpga_x2p_types.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_backannotate_utils.h" @@ -34,18 +39,451 @@ #include "fpga_x2p_pbtypes_utils.h" #include "fpga_x2p_bitstream_utils.h" #include "fpga_x2p_globals.h" +#include "fpga_x2p_naming.h" +#include "mux_utils.h" +#include "module_manager.h" +#include "module_manager_utils.h" /* Include Verilog support headers*/ #include "verilog_global.h" #include "verilog_utils.h" +#include "verilog_writer_utils.h" #include "verilog_routing.h" +/******************************************************************** + * Print local wires that are used for SRAM configuration + * This function is supposed to be used by Verilog generation + * of switch blocks + * It will count the number of switch blocks, which is the + * port width for local wires when Configuration chain is used + ********************************************************************/ +static +void print_verilog_switch_block_local_sram_wires(std::fstream& fp, + const RRGSB& rr_gsb, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type, + const size_t& port_size) { + size_t local_port_size = port_size; + if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { + /* Plus 1 for the wire size to connect to the tail of the configuration chain */ + local_port_size = find_switch_block_number_of_muxes(rr_gsb) + 1; + } + print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); +} + +/********************************************************************* + * Generate the Verilog module for a routing channel + * Routing track wire, which is 1-input and dual output + * This type of wires are used in the global routing architecture. + * One of the output is wired to another Switch block multiplexer, + * while the mid-output is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + * + * IMPORTANT: This function is designed for outputting unique Verilog modules + * of routing channels + * + * TODO: This function should be adapted to the RRGraph object + *********************************************************************/ +static +void print_verilog_routing_unique_chan_subckt(ModuleManager& module_manager, + const std::string& verilog_dir, + const std::string& subckt_dir, + const size_t& rr_chan_subckt_id, + const RRChan& rr_chan) { + std::string fname_prefix; + + /* TODO: use a constexpr String arrary to replace this switch cases? */ + /* Find the prefix for the Verilog file name */ + switch (rr_chan.get_type()) { + case CHANX: + fname_prefix = std::string(chanx_verilog_file_name_prefix); + break; + case CHANY: + fname_prefix = std::string(chany_verilog_file_name_prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, rr_chan_subckt_id, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id)); + + /* Add ports to the module */ + /* For the LEFT side of a X-direction routing channel + * or the BOTTOM bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are inputs of the module + * + * For the RIGHT side of a X-direction routing channel + * or the TOP bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are outputs of the module + * + * An example of X-direction routing channel consisting of W routing nodes: + * +--------------------------+ + * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) + * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) + * ... ... ... ... + * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) + * +--------------------------+ + * + * An example of Y-direction routing channel consisting of W routing nodes: + * + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + * ^ | ... | + * | v v + * +------------------------------ ... -------+ + * | out[0] in[1] in[X] | + * | | + * | | + * | in[0] out[1] ... out[X] | + * +------------------------------ ... -------+ + * ^ | | + * | v v + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + */ + /* Add ports at LEFT/BOTTOM side of the module */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id, itrack); + exit(1); + } + } + /* Add ports at RIGHT/TOP side of the module */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id, itrack); + exit(1); + } + } + /* Add middle-point output for connection box inputs */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* TODO: naming should be more flexible !!! */ + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Print short-wire connection: + * + * in[i] ----------> out[i] + * | + * +-----> mid_out[i] + */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* short connecting inputs and outputs: + * length of metal wire and parasitics are handled by semi-custom flow + */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + print_verilog_wire_connection(fp, output_port, input_port, false); + print_verilog_wire_connection(fp, mid_output_port, input_port, false); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* Uncomment this when it is ready + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} + +/********************************************************************* + * Generate the Verilog module for a routing channel + * Routing track wire, which is 1-input and dual output + * This type of wires are used in the global routing architecture. + * One of the output is wired to another Switch block multiplexer, + * while the mid-output is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + * + * IMPORTANT: This function is designed for outputting non-unique Verilog modules + * of routing channels + * + * TODO: This function should be adapted to the RRGraph object + *********************************************************************/ +static +void print_verilog_routing_chan_subckt(ModuleManager& module_manager, + const std::string& verilog_dir, + const std::string& subckt_dir, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices) { + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + std::string fname_prefix; + + /* TODO: use a constexpr String arrary to replace this switch cases? */ + /* Find the prefix for the Verilog file name */ + switch (chan_type) { + case CHANX: + fname_prefix = std::string(chanx_verilog_file_name_prefix); + break; + case CHANY: + fname_prefix = std::string(chany_verilog_file_name_prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, chan_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(chan_type, chan_coordinate)); + + /* Collect rr_nodes for Tracks for chanx[ix][iy] */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, chan_coordinate.x(), chan_coordinate.y(), + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Add ports to the module */ + /* For the LEFT side of a X-direction routing channel + * or the BOTTOM bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are inputs of the module + * + * For the RIGHT side of a X-direction routing channel + * or the TOP bottom side of a Y-direction routing channel + * Routing Resource Nodes in INC_DIRECTION are outputs of the module + * + * An example of X-direction routing channel consisting of W routing nodes: + * +--------------------------+ + * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) + * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) + * ... ... ... ... + * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) + * +--------------------------+ + * + * An example of Y-direction routing channel consisting of W routing nodes: + * + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + * ^ | ... | + * | v v + * +------------------------------ ... -------+ + * | out[0] in[1] in[X] | + * | | + * | | + * | in[0] out[1] ... out[X] | + * +------------------------------ ... -------+ + * ^ | | + * | v v + * nodeA nodeB nodeX + * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) + */ + /* Add ports at LEFT/BOTTOM side of the module */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + chan_coordinate.x(), chan_coordinate.y(), itrack); + exit(1); + } + } + /* Add ports at RIGHT/TOP side of the module */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + switch (chan_rr_nodes[itrack]->direction) { + case INC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + } + case DEC_DIRECTION: { + /* TODO: naming should be more flexible !!! */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + break; + } + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(chan_type), + chan_coordinate.x(), chan_coordinate.y(), itrack); + exit(1); + } + } + /* Add middle-point output for connection box inputs */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + /* TODO: naming should be more flexible !!! */ + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish dumping ports */ + + /* Print short-wire connection: + * + * in[i] ----------> out[i] + * | + * +-----> mid_out[i] + */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + /* short connecting inputs and outputs: + * length of metal wire and parasitics are handled by semi-custom flow + */ + BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); + BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); + BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); + print_verilog_wire_connection(fp, output_port, input_port, false); + print_verilog_wire_connection(fp, mid_output_port, input_port, false); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* Uncomment this when it is ready + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + /* Free */ + my_free(chan_rr_nodes); + + return; +} + + static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, size_t rr_chan_subckt_id, - const RRChan& rr_chan, - bool is_explicit_mapping) { + const RRChan& rr_chan) { FILE* fp = NULL; char* fname = NULL; @@ -79,9 +517,11 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1)); fprintf(fp, "\n"); /* dump global ports */ + /* if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } + */ /* Inputs and outputs, * Rules for CHANX: * print left-hand ports(in) first, then right-hand ports(out) @@ -171,8 +611,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int num_segment, - bool is_explicit_mapping) { + int num_segment) { int itrack, iseg, cost_index; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -217,9 +656,11 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(chan_type, x, y)); fprintf(fp, "\n"); /* dump global ports */ + /* if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } + */ /* Inputs and outputs, * Rules for CHANX: * print left-hand ports(in) first, then right-hand ports(out) @@ -522,8 +963,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, enum e_side chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node, - bool is_explicit_mapping) { + t_rr_node* drive_rr_node) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -771,7 +1211,6 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Find grid_x and grid_y */ grid_x = drive_rr_nodes[inode]->xlow; grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ - //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print a grid pin */ fprintf(fp, "assign %s_size%d_%d_inbus[%d] = ", verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); @@ -989,7 +1428,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int cur_bl, cur_wl; t_spice_model* mem_model = NULL; char* mem_subckt_name = NULL; - int num_input_port, num_output_port, num_sram_port; + int num_input_port, num_output_port; /* Check the file handler*/ if (NULL == fp) { @@ -1477,13 +1916,11 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node, - is_explicit_mapping); + num_drive_rr_nodes, cur_rr_node); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], - is_explicit_mapping); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, @@ -1720,287 +2157,409 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } - -/* Dump port list of a subckt describing a side of a switch block - * Only output ports will be printed on the specified side - * Only input ports will be printed on the other sides - */ +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ static -void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, - const RRGSB& rr_sb, - enum e_side sb_side, - size_t seg_id, - boolean dump_port_type, - bool is_explicit_mapping) { - /* Check file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid file handler!\n", - __FILE__, __LINE__); - exit(1); - } +BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const PORTS& cur_rr_node_direction) { + /* Get the index in sb_info of cur_rr_node */ + int index = rr_sb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); + /* Make sure this node is included in this sb_info */ + VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); - /* Create a side manager */ - Side sb_side_manager(sb_side); + DeviceCoordinator chan_rr_node_coordinator = rr_sb.get_side_block_coordinator(chan_side); - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { - Side side_manager(side); - /* Print ports */ - fprintf(fp, "//----- Inputs/outputs of %s side -----\n", side_manager.c_str()); - DeviceCoordinator port_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - switch (rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - /* if this is the specified side, we only consider output ports */ - if (sb_side_manager.get_side() != side_manager.get_side()) { - break; - } - /* Bypass unwanted segments */ - if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { - continue; - } - fprintf(fp, " "); - if (TRUE == dump_port_type) { - fprintf(fp, "output "); - is_explicit_mapping = false; /* Both cannot be true together */ - } - if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - } - fprintf(fp, "%s", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } - fprintf(fp, ",\n"); - break; - case IN_PORT: - /* if this is not the specified side, we only consider input ports */ - if (sb_side_manager.get_side() == side_manager.get_side()) { - break; - } - fprintf(fp, " "); - if (TRUE == dump_port_type) { - fprintf(fp, "input "); - } - if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - } - fprintf(fp, "%s", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } - fprintf(fp, ",\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_sb.get_sb_x(), rr_sb.get_sb_y(), itrack); - exit(1); - } - } - - /* Dump OPINs of adjacent CLBs */ - //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(port_coordinator); - for (size_t inode = 0; inode < rr_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - fprintf(fp, " "); - dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ - rr_sb.get_opin_node(side_manager.get_side(), inode)->ptc_num, - rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ - if (FALSE == dump_port_type) { - fprintf(fp, ",\n"); - } - } - } - - return; + vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); + std::string chan_port_name = generate_routing_track_port_name(rr_sb.get_chan_node(chan_side, index)->type, + chan_port_coord, index, + rr_sb.get_chan_node_direction(chan_side, index)); + return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */ } - -/* Task: Print the subckt of a side of a Switch Box. - * For TOP side: - * 1. Channel Y [x][y+1] inputs - * 2. Grid[x][y+1] Right side outputs pins - * 3. Grid[x+1][y+1] Left side output pins - * For RIGHT side: - * 1. Channel X [x+1][y] inputs - * 2. Grid[x+1][y+1] Bottom side output pins - * 3. Grid[x+1][y] Top side output pins - * For BOTTOM side: - * 1. Channel Y [x][y] outputs - * 2. Grid[x][y] Right side output pins - * 3. Grid[x+1][y] Left side output pins - * For LEFT side: - * 1. Channel X [x][y] outputs - * 2. Grid[x][y] Top side output pins - * 3. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ +/********************************************************************* + * Generate an input port for routing multiplexer inside the switch block + * In addition to give the Routing Resource node of the input + * Users should provide the side of input, which is different case by case: + * 1. When the input is a pin of a CLB/Logic Block, the input_side should + * be the side of the node on its grid! + * For example, the input pin is on the top side of a switch block + * but on the right side of a switch block + * +--------+ + * | | + * | Grid |---+ + * | | | + * +--------+ v input_pin + * +----------------+ + * | Switch Block | + * +----------------+ + * 2. When the input is a routing track, the input_side should be + * the side of the node locating on the switch block + ********************************************************************/ static -void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, char* subckt_dir, - size_t module_id, size_t seg_id, - const RRGSB& rr_sb, enum e_side side, - bool is_explicit_mapping) { - FILE* fp = NULL; - char* fname = NULL; - Side side_manager(side); - - /* Get the channel width on this side, if it is zero, we return */ - if (0 == rr_sb.get_chan_width(side)) { - return; +BasicPort generate_switch_block_input_port(const RRGSB& rr_sb, + const e_side& input_side, + t_rr_node* input_rr_node) { + BasicPort input_port; + /* Generate the input port object */ + switch (input_rr_node->type) { + /* case SOURCE: */ + case OPIN: { + /* Find the coordinator (grid_x and grid_y) for the input port */ + vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); + std::string input_port_name = generate_grid_side_port_name(input_port_coord, + input_side, + input_rr_node->ptc_num); + input_port.set_name(input_port_name); + input_port.set_width(1); /* Every grid output has a port size of 1 */ + break; + } + case CHANX: + case CHANY: { + input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_side, input_rr_node, IN_PORT); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); } - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side, seg_id); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - int esti_sram_cnt = cur_num_sram + num_conf_bits; + return input_port; +} - /* Create file name */ - std::string fname_prefix(sb_verilog_file_name_prefix); - fname_prefix += side_manager.c_str(); +/********************************************************************* + * Generate a list of input ports for routing multiplexer inside the switch block + ********************************************************************/ +static +std::vector generate_switch_block_input_ports(const RRGSB& rr_sb, + const std::vector& input_rr_nodes) { + std::vector input_ports; - std::string file_description("Unique module for Switch Block side: "); - file_description += side_manager.c_str(); - file_description += "seg"; - file_description += std::to_string(seg_id); - - /* Create file handler */ - fp = verilog_create_one_subckt_file(subckt_dir, file_description.c_str(), - fname_prefix.c_str(), module_id, seg_id, &fname); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Comment lines */ - fprintf(fp, - "//----- Verilog Module of Unique Switch Box[%lu][%lu] at Side %s, Segment id: %lu -----\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str(), seg_id); - /* Print the definition of subckt*/ - fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { - fprintf(fp, ",\n"); - } - - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, - seg_id, TRUE, - false); - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - 0, - num_reserved_conf_bits - 1, - VERILOG_PORT_INPUT); - if (0 < num_reserved_conf_bits) { - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1, - VERILOG_PORT_INPUT); - - /* Dump ports only visible during formal verification*/ - if (0 < num_conf_bits) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1, - VERILOG_PORT_INPUT, false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - cur_num_sram, - esti_sram_cnt - 1); - - /* Put down all the multiplexers */ - fprintf(fp, "//----- %s side Multiplexers -----\n", - side_manager.c_str()); - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) - ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - /* Bypass unwanted segments */ - if (seg_id != rr_sb.get_chan_node_segment(side_manager.get_side(), itrack)) { - continue; - } - dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, - side_manager.get_side(), - itrack, is_explicit_mapping); + for (auto input_rr_node : input_rr_nodes) { + enum e_side input_pin_side = NUM_SIDES; + switch (input_rr_node->type) { + case OPIN: + input_pin_side = rr_sb.get_opin_node_grid_side(input_rr_node); + break; + case CHANX: + case CHANY: { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_sb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); + VTR_ASSERT(NUM_SIDES != input_pin_side); + break; } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + input_ports.push_back(generate_switch_block_input_port(rr_sb, input_pin_side, input_rr_node)); } - - fprintf(fp, "endmodule\n"); - /* Comment lines */ - fprintf(fp, - "//----- END Verilog Module of Switch Box[%lu][%lu] Side %s -----\n\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y(), side_manager.c_str()); + return input_ports; +} + +/********************************************************************* + * Print a short interconneciton in switch box + * There are two cases should be noticed. + * 1. The actual fan-in of cur_rr_node is 0. In this case, + the cur_rr_node need to be short connected to itself which is on the opposite side of this switch + * 2. The actual fan-in of cur_rr_node is 0. In this case, + * The cur_rr_node need to connected to the drive_rr_node + ********************************************************************/ +static +void print_verilog_unique_switch_box_short_interc(std::fstream& fp, + const RRGSB& rr_sb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + t_rr_node* drive_rr_node) { + /* Check the file handler*/ + check_file_handler(fp); + + /* Find the name of output port */ + BasicPort output_port = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); + enum e_side input_pin_side = chan_side; + + /* Generate the input port object */ + switch (drive_rr_node->type) { + case OPIN: + input_pin_side = rr_sb.get_opin_node_grid_side(drive_rr_node); + break; + case CHANX: + case CHANY: { + /* This should be an input in the data structure of RRGSB */ + if (cur_rr_node == drive_rr_node) { + /* To be strict, the input should locate on the opposite side. + * Use the else part if this may change in some architecture. + */ + Side side_manager(chan_side); + input_pin_side = side_manager.get_opposite(); + } else { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_sb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); + } + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + /* Find the name of input port */ + BasicPort input_port = generate_switch_block_input_port(rr_sb, input_pin_side, drive_rr_node); + + /* Print the wire connection in Verilog format */ + print_verilog_comment(fp, std::string("----- Short connection " + output_port.get_name() + " -----")); + print_verilog_wire_connection(fp, output_port, input_port, false); + fp << std::endl; +} + +/********************************************************************* + * Print a Verilog instance of a routing multiplexer as well as + * associated memory modules for a connection inside a switch block + ********************************************************************/ +static +void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info, + const ModuleId& sb_module, + const RRGSB& rr_sb, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const std::vector& drive_rr_nodes, + const size_t& switch_index, + const bool& use_explicit_mapping) { + /* Check the file handler*/ + check_file_handler(fp); /* Check */ - assert(esti_sram_cnt == get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info)); + /* Check current rr_node is CHANX or CHANY*/ + VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - /* Close file handler */ - fclose(fp); + /* Get the circuit model id of the routing multiplexer */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); - /* Free chan_rr_nodes */ - my_free(fname); + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - return; + /* Find the module name of the multiplexer and try to find it in the module manager */ + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + + /* Get the MUX instance id from the module manager */ + size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module); + + /* Print the input bus for the inputs of a multiplexer + * We use the datapath input size (mux_size) to name the bus + * just to following the naming convention when the tool is built + * The bus port size should be the input size of multiplexer implementation + */ + BasicPort inbus_port; + inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); + inbus_port.set_width(datapath_mux_size); + + /* Generate input ports that are wired to the input bus of the routing multiplexer */ + std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); + /* Connect input ports to bus */ + print_verilog_comment(fp, std::string("----- BEGIN A local bus wire for multiplexer inputs -----")); + fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; + print_verilog_comment(fp, std::string("----- END A local bus wire for multiplexer inputs -----")); + fp << std::endl; + + /* Find the number of reserved configuration bits for the routing multiplexer */ + size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); + + /* Find the number of configuration bits for the routing multiplexer */ + size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); + + /* Print the configuration bus for the routing multiplexers */ + print_verilog_comment(fp, std::string("----- BEGIN Local wires to group configuration ports -----")); + print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, + datapath_mux_size, mux_instance_id, + mux_num_reserved_config_bits, mux_num_config_bits); + print_verilog_comment(fp, std::string("----- END Local wires to group configuration ports -----")); + fp << std::endl; + + /* Dump ports visible only during formal verification */ + print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); + print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); + /* Print the SRAM configuration ports for formal verification */ + /* TODO: align with the port width of formal verification port of SB module */ + print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, + datapath_mux_size, mux_instance_id, mux_num_config_bits); + print_verilog_endif(fp); + print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); + fp << std::endl; + + /* Instanciate the MUX Module */ + /* Create port-to-port map */ + std::map mux_port2port_name_map; + + /* Link input bus port to Switch Block inputs */ + std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == mux_model_input_ports.size()); + /* Use the port name convention in the circuit library */ + mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_input_ports[0])] = inbus_port; + + /* Link output port to Switch Block outputs */ + std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == mux_model_output_ports.size()); + /* Use the port name convention in the circuit library */ + mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_output_ports[0])] = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); + + /* Link SRAM port to different configuraton port for the routing multiplexer + * Different design technology requires different configuration bus! + */ + std::vector mux_model_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); + VTR_ASSERT( 1 == mux_model_sram_ports.size() ); + /* For the regular SRAM port, module port use the same name */ + std::string mux_module_sram_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]); + BasicPort mux_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + mux_num_config_bits); + mux_port2port_name_map[mux_module_sram_port_name] = mux_config_port; + + /* For the inverted SRAM port */ + std::string mux_module_sram_inv_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]) + std::string("_inv"); + BasicPort mux_config_inv_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + mux_num_config_bits); + mux_port2port_name_map[mux_module_sram_inv_port_name] = mux_config_inv_port; + + /* Print an instance of the MUX Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a routing multiplexer -----")); + print_verilog_module_instance(fp, module_manager, sb_module, mux_module, mux_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of a routing multiplexer -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(sb_module, mux_module); + + /* Instanciate memory modules */ + /* Find the name and module id of the memory module */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + ModuleId mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + + /* Create port-to-port map */ + std::map mem_port2port_name_map; + + /* TODO: Make the port2port map generation more generic!!! */ + std::vector config_ports; + config_ports.push_back(BasicPort(generate_local_config_bus_port_name(), mux_instance_id - 1, mux_instance_id)); + std::vector mem_output_ports; + mem_output_ports.push_back(mux_config_port); + mem_output_ports.push_back(mux_config_inv_port); + mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, + config_ports, + mem_output_ports, + circuit_lib.design_tech_type(mux_model), + cur_sram_orgz_info->type); + + /* Print an instance of the MUX Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); + print_verilog_module_instance(fp, module_manager, sb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(sb_module, mem_module); + + /* Create the path of the input of multiplexer in the hierarchy + * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! + */ + std::string mux_input_hie_path = std::string(rr_sb.gen_sb_verilog_instance_name()) + std::string("/") + + mux_module_name + std::string("_") + + std::to_string(mux_instance_id) + std::string("_/in"); + cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); } -/* Task: Print the subckt of a Switch Box. - * Call the four submodules dumped in function: unique_side_module + +/********************************************************************* + * Print the Verilog modules for a interconnection inside switch block + * The interconnection could be either a wire or a routing multiplexer, + * which depends on the fan-in of the rr_nodes in the switch block + ********************************************************************/ +static +void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info, + const ModuleId& sb_module, + const RRGSB& rr_sb, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const e_side& chan_side, + const size_t& chan_node_id, + const bool& use_explicit_mapping) { + std::vector drive_rr_nodes; + + /* Get the node */ + t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id); + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (false == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { + for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { + drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); + } + /* Special: if there are zero-driver nodes. We skip here */ + if (0 == drive_rr_nodes.size()) { + return; + } + } + + if (0 == drive_rr_nodes.size()) { + /* Print a special direct connection*/ + print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, + cur_rr_node); + } else if (1 == drive_rr_nodes.size()) { + /* Print a direct connection*/ + print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, + drive_rr_nodes[DEFAULT_SWITCH_ID]); + } else if (1 < drive_rr_nodes.size()) { + /* Print the multiplexer, fan_in >= 2 */ + print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, + sb_module, rr_sb, circuit_lib, mux_lib, + rr_switches, chan_side, cur_rr_node, + drive_rr_nodes, + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + use_explicit_mapping); + } /*Nothing should be done else*/ +} + +/********************************************************************* + * Generate the Verilog module for a Switch Box. + * A Switch Box module consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * Location of a Switch Box in FPGA fabric: * * -------------- -------------- * | | | | @@ -2019,15 +2578,45 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr * | [x][y] | [x][y] | [x+1][y] | * | | | | * -------------- -------------- - */ + * + * Switch Block pin location map + * + * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] + * right_pins inputs/outputs left_pins + * | ^ | + * | | | + * v v v + * +-----------------------------------------------+ + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * bottom_pins---->| |<---- bottom_pins + * | | + * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] + * inputs/outputs<--->| |<---> inputs/outputs + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * top_pins---->| |<---- top_pins + * | | + * +-----------------------------------------------+ + * ^ ^ ^ + * | | | + * | v | + * Grid[x][y] ChanY[x][y] Grid[x+1][y] + * right_pins inputs/outputs left_pins + * + * + ********************************************************************/ static -void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb, - bool is_explicit_mapping) { - FILE* fp = NULL; - char* fname = NULL; - +void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + const RRGSB& rr_sb, + const bool& is_explicit_mapping) { + /* TODO: move this part to another function where we count the conf bits for all the switch blocks !!!*/ /* Count the number of configuration bits to be consumed by this Switch block */ int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); /* Count the number of reserved configuration bits to be consumed by this Switch block */ @@ -2035,45 +2624,58 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or /* Estimate the sram_verilog_model->cnt */ int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - rr_gsb.set_sb_num_reserved_conf_bits(num_reserved_conf_bits); - rr_gsb.set_sb_conf_bits_lsb(cur_num_sram); - rr_gsb.set_sb_conf_bits_msb(cur_num_sram + num_conf_bits - 1); + rr_gsb.set_sb_num_reserved_conf_bits(size_t(num_reserved_conf_bits)); + rr_gsb.set_sb_conf_bits_lsb(size_t(cur_num_sram)); + rr_gsb.set_sb_conf_bits_msb(size_t(cur_num_sram + num_conf_bits - 1)); - /* Create file handler */ - fp = verilog_create_one_subckt_file(subckt_dir, "Unique Switch Block ", - sb_verilog_file_name_prefix, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), &fname); + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir); + print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Comment lines */ - fprintf(fp, "//----- Verilog Module of Unique Switch Box[%lu][%lu] -----\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - /* Print the definition of subckt*/ - fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { - fprintf(fp, ",\n"); + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); + + /* Add ports to the module */ + /* Global ports: + * In the circuit_library, find all the circuit models that may be included in the Switch Block + * Collect the global ports from the circuit_models and merge with the same name + */ + std::vector global_ports = find_switch_block_global_ports(rr_gsb, circuit_lib, rr_switches); + for (const auto& port : global_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT); } - + /* Add routing channel ports at each side of the GSB */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); - /* Print ports */ - fprintf(fp, "//----- Channel Inputs/outputs of %s side -----\n", side_manager.c_str()); DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); + std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - fprintf(fp, " output %s,\n", - gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); + case OUT_PORT: + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); break; case IN_PORT: - fprintf(fp, " input %s,\n", - gen_verilog_routing_channel_one_pin_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack), - port_coordinator.get_x(), port_coordinator.get_y(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack))); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); break; default: vpr_printf(TIO_MESSAGE_ERROR, @@ -2083,156 +2685,87 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or } } /* Dump OPINs of adjacent CLBs */ - fprintf(fp, "//----- Grid Inputs/outputs of %s side -----\n", side_manager.c_str()); for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - fprintf(fp, " "); - dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an input of a SB */ - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - 0,0, /*No explicit mapping */ - TRUE, false); /* Dump the direction of the port ! */ + vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + std::string port_name = generate_grid_side_port_name(port_coord, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); + BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); } } - /* Put down configuration port */ - /* output of each configuration bit */ + /* Add configuration ports */ /* Reserved sram ports */ - fprintf(fp, "//----- Reserved SRAM Ports -----\n"); if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) { - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_reserved_conf_bits_lsb(), - rr_gsb.get_sb_reserved_conf_bits_msb(), - VERILOG_PORT_INPUT); - fprintf(fp, ",\n"); + /* Check: this SRAM organization type must be memory-bank ! */ + VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); + /* Generate a list of ports */ + add_reserved_sram_ports_to_module_manager(module_manager, module_id, + rr_gsb.get_sb_num_reserved_conf_bits()); } + + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + /* Normal sram ports */ - fprintf(fp, "//----- Regular SRAM Ports -----\n"); - dump_verilog_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT); - - /* Dump ports only visible during formal verification*/ if (0 < rr_gsb.get_sb_num_conf_bits()) { - fprintf(fp, "\n"); - fprintf(fp, "//----- SRAM Ports for formal verification -----\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, - false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); + add_sram_ports_to_module_manager(module_manager, module_id, + circuit_lib, sram_model, cur_sram_orgz_info->type, + rr_gsb.get_sb_num_conf_bits()); + /* Add ports only visible during formal verification to the module */ + add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, + std::string(verilog_formal_verification_preproc_flag), + rr_gsb.get_sb_num_conf_bits()); } - fprintf(fp, "); \n"); + /* Print module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish printing ports */ + + print_verilog_comment(fp, std::string("---- BEGIN local wires for SRAM data ports ----")); /* Local wires for memory configurations */ - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - rr_gsb.get_sb_conf_bits_lsb(), - rr_gsb.get_sb_conf_bits_msb()); + print_verilog_switch_block_local_sram_wires(fp, rr_gsb, circuit_lib, sram_model, cur_sram_orgz_info->type, + rr_gsb.get_sb_num_conf_bits()); + print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); - /* Call submodules */ - int cur_sram_lsb = cur_num_sram; - int cur_sram_msb = cur_num_sram; + /* TODO: Print routing multiplexers */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); - fprintf(fp, "//----- %s side Submodule -----\n", - side_manager.c_str()); - - /* Get the channel width on this side, if it is zero, we return */ - if (0 == rr_gsb.get_chan_width(side_manager.get_side())) { - fprintf(fp, "//----- %s side has zero channel width, module dump skipped -----\n", - side_manager.c_str()); - continue; - } - - /* get segment ids */ - std::vector seg_ids = rr_gsb.get_chan(side_manager.get_side()).get_segment_ids(); - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - fprintf(fp, "//----- %s side Submodule with Segment id: %lu -----\n", - side_manager.c_str(), seg_ids[iseg]); - - /* Count the number of configuration bits to be consumed by this Switch block */ - int side_num_conf_bits = count_verilog_switch_box_side_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, side_manager.get_side(), seg_ids[iseg]); - - /* Cache the sram counter */ - cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1; - - /* Instanciate the subckt*/ - fprintf(fp, - "%s %s ( \n", - rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]), - rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg])); - /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { - fprintf(fp, ",\n"); - } - - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping); - - /* Put down configuration port */ - /* output of each configuration bit */ - /* Reserved sram ports */ - dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info, - 0, - side_num_reserved_conf_bits - 1, - VERILOG_PORT_CONKT); - if (0 < side_num_reserved_conf_bits) { - fprintf(fp, ",\n"); - } - /* Normal sram ports */ - dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, - cur_sram_lsb, - cur_sram_msb, - VERILOG_PORT_CONKT, is_explicit_mapping); - - /* Dump ports only visible during formal verification*/ - if (0 < side_num_conf_bits) { - fprintf(fp, "\n"); - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, ",\n"); - dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, - cur_sram_lsb, - cur_sram_msb, - VERILOG_PORT_CONKT, - false); - fprintf(fp, "\n"); - fprintf(fp, "`endif\n"); - } - fprintf(fp, "); \n"); - - /* Update sram_lsb */ - cur_sram_lsb = cur_sram_msb + 1; + print_verilog_comment(fp, std::string("----- " + side_manager.to_string() + " side Routing Multiplexers -----")); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + /* We care INC_DIRECTION tracks at this side*/ + if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, module_id, rr_sb, + circuit_lib, mux_lib, rr_switches, + side_manager.get_side(), + itrack, is_explicit_mapping); + } } } - /* checker */ - assert(cur_sram_msb == cur_num_sram + num_conf_bits - 1); + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; - fprintf(fp, "endmodule\n"); - - /* Comment lines */ - fprintf(fp, "//----- END Verilog Module of Switch Box[%lu][%lu] -----\n\n", rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - /* Close file handler */ - fclose(fp); + fp.close(); /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - - /* Free chan_rr_nodes */ - my_free(fname); + /* + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ return; } - - /* Task: Print the subckt of a Switch Box. * A Switch Box subckt consists of following ports: * 1. Channel Y [x][y] inputs @@ -2337,9 +2870,9 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE, false); /* Dump the direction of the port ! */ + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2541,8 +3074,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, - 0,/*used in more recent version*/ - 0,/*used in more recent version*/ + cur_sb_info->opin_rr_node[side][inode]->xlow, + cur_sb_info->opin_rr_node[side][inode]->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2570,7 +3103,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT, false); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2802,10 +3335,10 @@ void dump_verilog_connection_box_short_interc(FILE* fp, /* SRC rr_node is the IPIN of a grid.*/ +static void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node, - bool is_explicit_mapping) { + t_rr_node* src_rr_node) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, side, index; @@ -3027,7 +3560,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - 0,0, /*No explicit mapping*/ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3275,8 +3808,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - 0,/*No explicit mapping*/ - 0,/*No explicit mapping*/ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3415,7 +3947,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node, is_explicit_mapping); + dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, @@ -3606,8 +4138,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, - 0,/*No explicit mapping */ - 0,/*No explicit mapping */ + 0,0, /*No explicit mapping */ TRUE, false); } @@ -3811,7 +4342,6 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert((1 == side_cnt)||(2 == side_cnt)); side_cnt = 0; - //const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, coordinator); /* Print the ports of grids*/ /* only check ipin_rr_nodes of cur_cb_info */ for (side = 0; side < cur_cb_info->num_sides; side++) { @@ -3862,7 +4392,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info->conf_bits_lsb, cur_cb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT, false); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3923,21 +4453,62 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ return; } -/* Top Function*/ -/* Build the routing resource SPICE sub-circuits*/ -void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* subckt_dir, - t_arch arch, - t_det_routing_arch* routing_arch, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - t_rr_indexed_data* LL_rr_indexed_data, - t_fpga_spice_opts FPGA_SPICE_Opts) { - assert(UNI_DIRECTIONAL == routing_arch->directionality); +/********************************************************************* + * Generate the port name for a Grid + *********************************************************************/ +std::string generate_grid_side_port_name(const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id) { + /* Output the pins on the side*/ + int height = get_grid_pin_height(coordinate.x(), coordinate.y(), (int)pin_id); + if (1 != grid[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", + __FILE__, __LINE__, + coordinate.x(), coordinate.y(), height, convert_side_index_to_string(side), pin_id); + exit(1); + } + return generate_grid_port_name(coordinate, (size_t)height, side, pin_id, true); +} + +/********************************************************************* + * Top-level function: + * Build the Verilog modules for global routing architecture + * 1. Routing channels + * 2. Switch blocks + * 3. Connection blocks + * + * This function supports two styles in Verilog generation: + * 1. Explicit port mapping + * 2. Inexplicit port mapping + * + * This function also supports high hierarchical Verilog generation + * (when the compact_routing_hierarchy is set true) + * In this mode, Verilog generation will be done for only those + * unique modules in terms of internal logics + *********************************************************************/ +void print_verilog_routing_resources(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + const t_arch& arch, + const t_det_routing_arch& routing_arch, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, /* To be replaced by RRGraph object */ + t_ivec*** LL_rr_node_indices, + t_rr_indexed_data* LL_rr_indexed_data, + const t_fpga_spice_opts& FPGA_SPICE_Opts) { + VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy; boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog; + + /* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */ + std::vector rr_switches; + for (short i = 0; i < routing_arch.num_switch; ++i) { + rr_switches.push_back(switch_inf[i]); + } + /* Two major tasks: * 1. Generate sub-circuits for Routing Channels * 2. Generate sub-circuits for Switch Boxes @@ -3962,13 +4533,19 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* X - channels [1...nx][0..ny]*/ for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping); + ichan, device_rr_chan.get_module(CHANX, ichan)); + + print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), + ichan, device_rr_chan.get_module(CHANX, ichan)); } /* Y - channels [1...ny][0..nx]*/ vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping); + ichan, device_rr_chan.get_module(CHANY, ichan)); + + print_verilog_routing_unique_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), + ichan, device_rr_chan.get_module(CHANY, ichan)); } } else { /* Output the full array of routing channels */ @@ -3977,7 +4554,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int ix = 1; ix < (nx + 1); ix++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments, explicit_port_mapping); + arch.num_segments); + + vtr::Point chan_coordinate((size_t)ix, (size_t)iy); + print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANX, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } } /* Y - channels [1...ny][0..nx]*/ @@ -3986,7 +4567,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int iy = 1; iy < (ny + 1); iy++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments, explicit_port_mapping); + arch.num_segments); + + vtr::Point chan_coordinate((size_t)ix, (size_t)iy); + print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANY, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } } } @@ -3996,28 +4581,16 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Create a snapshot on sram_orgz_info */ t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); - /* Output unique side modules - for (size_t side = 0; side < device_rr_gsb.get_max_num_sides(); ++side) { - Side side_manager(side); - for (size_t iseg = 0; iseg < device_rr_gsb.get_num_segments(); ++iseg) { - for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) { - const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg); - size_t seg_id = device_rr_gsb.get_segment_id(iseg); - dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping); - } - } - } - */ - /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); - /* - dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, - subckt_dir, unique_mirror, explicit_port_mapping); - */ dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, explicit_port_mapping); + print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib, + rr_switches, + cur_sram_orgz_info, std::string(verilog_dir), + std::string(subckt_dir), unique_mirror, + explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -4127,4 +4700,3 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, return; } - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 1da674e78..ad025a567 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -1215,6 +1215,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ FILE* fp, bool is_explicit_mapping) { int num_mem_bits = 0; + t_spice_model* ccff_mem_model = NULL; /* Check */ assert(SPICE_SRAM_SCAN_CHAIN == cur_sram_orgz_info->type); @@ -1226,6 +1227,9 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ /* Get the total memory bits */ num_mem_bits = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + /* Get model of the configuration chain */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model); + /* Dump each Scan-chain FF */ fprintf(fp, "//------ Configuration peripheral for Scan-chain FFs -----\n"); fprintf(fp, "%s %s_0_ (\n", @@ -1243,7 +1247,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ } fprintf(fp, ",\n"); if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_in_local_bus ("); + fprintf(fp, ".%s_ccff_in_local_bus (", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { @@ -1251,7 +1256,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ } fprintf(fp, ",\n"); if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_out_local_bus ("); + fprintf(fp, ".%s_ccff_out_local_bus (", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 1a34c7921..f6a159f22 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -1560,6 +1560,7 @@ void dump_verilog_sram_local_ports(FILE* fp, t_spice_model_port** blb_port = NULL; t_spice_model_port** wlb_port = NULL; t_spice_model* cur_sram_verilog_model = NULL; + t_spice_model* ccff_mem_model = NULL; /* Check the file handler*/ if (NULL == fp) { @@ -1577,6 +1578,10 @@ void dump_verilog_sram_local_ports(FILE* fp, __FILE__, __LINE__, sram_lsb, sram_msb); return; } + + /* Get model of the configuration chain */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model); + switch (cur_sram_orgz_info->type) { case SPICE_SRAM_STANDALONE: case SPICE_SRAM_MEMORY_BANK: @@ -1593,7 +1598,8 @@ void dump_verilog_sram_local_ports(FILE* fp, case SPICE_SRAM_SCAN_CHAIN: /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_head("); + fprintf(fp, ".%s_ccff_head(", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_lsb, sram_lsb, @@ -1604,7 +1610,8 @@ void dump_verilog_sram_local_ports(FILE* fp, fprintf(fp, ",\n"); /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_tail("); + fprintf(fp, ".%s_ccff_tail(", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_msb, sram_msb, From c7e1f7d90b1b7ffbea6eb98880dc5829102b0ad0 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 10:17:04 -0600 Subject: [PATCH 257/482] Added explicit_verilog to regression test in a clean way --- .travis/script.sh | 2 +- .../tasks/blif_vpr_flow/config/task.conf | 5 +-- .../tasks/explicit_verilog/config/task.conf | 41 +++++++++++++++++++ 3 files changed, 44 insertions(+), 4 deletions(-) create mode 100644 openfpga_flow/tasks/explicit_verilog/config/task.conf diff --git a/.travis/script.sh b/.travis/script.sh index fa9e95ea8..37e96e1a8 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2 end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index cf283f22a..d3fc4fedc 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -64,7 +64,7 @@ vpr_fpga_verilog_print_sdc_analysis= end_flow_with_test= -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT] fix_route_chan_width=300 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= @@ -76,6 +76,5 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_x2p_compact_routing_hierarchy= -vpr_fpga_verilog_explicit_mapping= +#vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf new file mode 100644 index 000000000..be4320161 --- /dev/null +++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] +fix_route_chan_width=300 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_verilog_explicit_mapping= +end_flow_with_test= From db059af8b80cb28621bf317ed977dfc34a9914ce Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 13:33:28 -0600 Subject: [PATCH 258/482] Lighten the regression test --- .../tasks/blif_vpr_flow/config/task.conf | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index d3fc4fedc..c54ce8403 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -63,18 +63,3 @@ vpr_fpga_verilog_print_sdc_analysis= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT] -fix_route_chan_width=300 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= From 95596bb4f825c740f0d3929c5dad36d520227a54 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 13:50:01 -0600 Subject: [PATCH 259/482] Correction on the cb vs sb corrdinator. Does not fix the problem though --- .../vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 96aea8d43..38d705461 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -953,13 +953,13 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ /* Print each INPUT Pins of a grid */ if (true == is_explicit_mapping) { if (RIGHT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type) + 1, unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (TOP == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (LEFT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (BOTTOM == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, From 6f7023658efe50ba18d76c559066fe15a33673f7 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 14:59:04 -0600 Subject: [PATCH 260/482] Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though" This reverts commit 95596bb4f825c740f0d3929c5dad36d520227a54. --- .../vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 38d705461..96aea8d43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -953,13 +953,13 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ /* Print each INPUT Pins of a grid */ if (true == is_explicit_mapping) { if (RIGHT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type) + 1, unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (TOP == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (LEFT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (BOTTOM == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, From 7aa24f407ece13bb8c78b43259c69f7dcf35b239 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 4 Oct 2019 11:20:46 -0600 Subject: [PATCH 261/482] Fix explicit port name in CBs --- .../SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 96aea8d43..c38742ddc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -950,16 +950,19 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ side_manager.c_str()); for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + t_rr_node* uni_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); /* Print each INPUT Pins of a grid */ if (true == is_explicit_mapping) { if (RIGHT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1 -(grid[rr_gsb.get_grid_coordinator().get_x()][rr_gsb.get_grid_coordinator().get_y()].offset), +get_grid_pin_height(uni_ipin_node->xlow, uni_ipin_node->ylow,uni_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), +uni_ipin_node->ptc_num); } else if (TOP == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(uni_ipin_node->xlow, uni_ipin_node->ylow,uni_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), uni_ipin_node->ptc_num); } else if (LEFT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1 -(grid[rr_gsb.get_grid_coordinator().get_x()][rr_gsb.get_grid_coordinator().get_y()].offset), get_grid_pin_height(uni_ipin_node->xlow, uni_ipin_node->ylow,uni_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), uni_ipin_node->ptc_num); } else if (BOTTOM == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() -(grid[rr_gsb.get_grid_coordinator().get_x()][rr_gsb.get_grid_coordinator().get_y()-1].offset), get_grid_pin_height(uni_ipin_node->xlow, uni_ipin_node->ylow,uni_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), uni_ipin_node->ptc_num); } } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, From b905c0c68c6b3826a6884688f193e9ce53e64ace Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 4 Oct 2019 22:45:45 -0600 Subject: [PATCH 262/482] refactored memory module Verilog generation for scan-chains --- .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp | 272 ++++++++++++++++++ .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.h | 25 ++ .../fpga_x2p/base/module_manager_utils.cpp | 147 ---------- .../SRC/fpga_x2p/base/module_manager_utils.h | 7 - .../SRC/fpga_x2p/verilog/verilog_routing.c | 27 +- 5 files changed, 318 insertions(+), 160 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp new file mode 100644 index 000000000..2fd7c9872 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp @@ -0,0 +1,272 @@ +/********************************************************************* + * This file includes functions that are used for + * generating ports for memory modules + *********************************************************************/ +#include "vtr_assert.h" +#include "util.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_mem_utils.h" + +/********************************************************************* + * Create a port-to-port map for a CMOS memory module + * + * Configuration Chain + * ------------------- + * + * config_bus (head) config_bus (tail) + * | ^ + * v | + * +-------------------------------------+ + * | CMOS-based Memory Module | + * +-------------------------------------+ + * | | + * v v + * sram_out sram_outb + * + * + * Memory bank + * ----------- + * + * config_bus (BL) config_bus (WL) + * | | + * v v + * +-------------------------------------+ + * | CMOS-based Memory Module | + * +-------------------------------------+ + * | | + * v v + * sram_out sram_outb + * + **********************************************************************/ +static +std::map generate_cmos_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const BasicPort& config_bus, + const std::vector& mem_output_bus_ports, + const e_sram_orgz& sram_orgz_type) { + std::map port2port_name_map; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Nothing to do */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* Link the head port of the memory module: + * the LSB of config bus port is the head port index + */ + std::vector config_bus_ports; + config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1)); + BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); + port2port_name_map[generate_configuration_chain_head_name()] = head_port; + + /* Link the tail port of the memory module: + * the MSB of config bus port is the tail port index + */ + BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); + port2port_name_map[generate_configuration_chain_tail_name()] = tail_port; + + /* Link the SRAM output ports of the memory module */ + VTR_ASSERT( 2 == mem_output_bus_ports.size() ); + port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0]; + port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1]; + break; + } + case SPICE_SRAM_MEMORY_BANK: + /* TODO: */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return port2port_name_map; +} + +/********************************************************************* + * Create a port-to-port map for a ReRAM-based memory module + * Memory bank + * ----------- + * + * config_bus (BL) config_bus (WL) + * | | + * v v + * +-------------------------------------+ + * | ReRAM-based Memory Module | + * +-------------------------------------+ + * | | + * v v + * Mem_out Mem_outb + **********************************************************************/ +static +std::map generate_rram_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const BasicPort& config_bus, + const std::vector& mem_output_bus_ports, + const e_sram_orgz& sram_orgz_type) { + std::map port2port_name_map; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not supported */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* Link the head port of the memory module: + * the LSB of config bus port is the head port index + */ + std::vector config_bus_ports; + config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1)); + BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); + port2port_name_map[generate_configuration_chain_head_name()] = head_port; + + /* Link the tail port of the memory module: + * the MSB of config bus port is the tail port index + */ + BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); + port2port_name_map[generate_configuration_chain_tail_name()] = tail_port; + + /* Link the SRAM output ports of the memory module */ + VTR_ASSERT( 2 == mem_output_bus_ports.size() ); + port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0]; + port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1]; + break; + } + case SPICE_SRAM_MEMORY_BANK: + /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return port2port_name_map; +} + +/********************************************************************* + * Create a port-to-port map for a memory module + * The content of the port-to-port map will depend not only + * the design technology of the memory cells but also the + * configuration styles of FPGA fabric. + * Here we will branch on the design technology + **********************************************************************/ +std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const BasicPort& config_bus, + const std::vector& mem_output_bus_ports, + const e_spice_model_design_tech& mem_design_tech, + const e_sram_orgz& sram_orgz_type) { + std::map port2port_name_map; + + switch (mem_design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + port2port_name_map = generate_cmos_mem_module_port2port_map(module_manager, mem_module, config_bus, mem_output_bus_ports, sram_orgz_type); + break; + case SPICE_MODEL_DESIGN_RRAM: + port2port_name_map = generate_rram_mem_module_port2port_map(module_manager, mem_module, config_bus, mem_output_bus_ports, sram_orgz_type); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of memory design technology !\n", + __FILE__, __LINE__); + exit(1); + } + + return port2port_name_map; +} + +/********************************************************************* + * Update the LSB and MSB of a configuration bus based on the number of + * memory bits of a CMOS memory module. + **********************************************************************/ +static +void update_cmos_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, + const size_t& num_config_bits, + BasicPort& config_bus) { + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not supported */ + break; + case SPICE_SRAM_SCAN_CHAIN: + /* Scan-chain of a memory module only has a head and a tail. + * LSB and MSB of configuration bus will be shifted to the next head. + */ + VTR_ASSERT(true == config_bus.rotate(1)); + break; + case SPICE_SRAM_MEMORY_BANK: + /* In this case, a memory module has a number of BL/WL and BLB/WLB (possibly). + * LSB and MSB of configuration bus will be shifted by the number of BL/WL/BLB/WLB. + */ + VTR_ASSERT(true == config_bus.rotate(num_config_bits)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/********************************************************************* + * Update the LSB and MSB of a configuration bus based on the number of + * memory bits of a ReRAM memory module. + **********************************************************************/ +static +void update_rram_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, + const size_t& num_config_bits, + BasicPort& config_bus) { + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not supported */ + break; + case SPICE_SRAM_SCAN_CHAIN: + /* Scan-chain of a memory module only has a head and a tail. + * LSB and MSB of configuration bus will be shifted to the next head. + * TODO: this may be changed later!!! + */ + VTR_ASSERT(true == config_bus.rotate(1)); + break; + case SPICE_SRAM_MEMORY_BANK: + /* In this case, a memory module contains unique BL/WL or BLB/WLB, + * which are not shared with other modules + * TODO: this may be changed later!!! + */ + VTR_ASSERT(true == config_bus.rotate(1)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/********************************************************************* + * Update the LSB and MSB of a configuration bus based on the number of + * memory bits of a module. + * Note that this function is designed to do such simple job, in purpose of + * being independent from adding ports or printing ports. + * As such, this function can be re-used in bitstream generation + * when Verilog generation is not needed. + * DO NOT update the configuration bus in the function of adding/printing ports + **********************************************************************/ +void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, + const e_spice_model_design_tech& mem_design_tech, + const size_t& num_config_bits, + BasicPort& config_bus) { + switch (mem_design_tech) { + case SPICE_MODEL_DESIGN_CMOS: + update_cmos_mem_module_config_bus(sram_orgz_type, num_config_bits, config_bus); + break; + case SPICE_MODEL_DESIGN_RRAM: + update_rram_mem_module_config_bus(sram_orgz_type, num_config_bits, config_bus); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of memory design technology !\n", + __FILE__, __LINE__); + exit(1); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h new file mode 100644 index 000000000..5a25cdcbd --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h @@ -0,0 +1,25 @@ +/******************************************************************** + * Header file for fpga_x2p_mem_utils.cpp + **********************************************************************/ +#ifndef FPGA_X2P_MEM_UTILS_H +#define FPGA_X2P_MEM_UTILS_H + +/* Header files are included for the data types appear in the function declaration below */ +#include +#include "device_port.h" +#include "spice_types.h" +#include "module_manager.h" + +std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, + const ModuleId& mem_module, + const BasicPort& config_bus, + const std::vector& mem_output_bus_ports, + const e_spice_model_design_tech& mem_design_tech, + const e_sram_orgz& sram_orgz_type); + +void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, + const e_spice_model_design_tech& mem_design_tech, + const size_t& num_config_bits, + BasicPort& config_bus); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index e442b0223..6b7c9bdc9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -210,150 +210,3 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, } } -/********************************************************************* - * Create a port-to-port map for a CMOS memory module - * - * Configuration Chain - * ------------------- - * - * config_bus (head) config_bus (tail) - * | ^ - * v | - * +-------------------------------------+ - * | CMOS-based Memory Module | - * +-------------------------------------+ - * | | - * v v - * sram_out sram_outb - * - * - * Memory bank - * ----------- - * - * config_bus (BL) config_bus (WL) - * | | - * v v - * +-------------------------------------+ - * | CMOS-based Memory Module | - * +-------------------------------------+ - * | | - * v v - * sram_out sram_outb - * - **********************************************************************/ -static -std::map generate_cmos_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const std::vector& config_bus_ports, - const std::vector& mem_output_bus_ports, - const e_sram_orgz& sram_orgz_type) { - std::map port2port_name_map; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Nothing to do */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - /* Link the head port of the memory module: - * the LSB of config bus port is the head port index - */ - VTR_ASSERT( 1 == config_bus_ports.size() ); - BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); - port2port_name_map[generate_configuration_chain_head_name()] = head_port; - - /* Link the tail port of the memory module: - * the MSB of config bus port is the tail port index - */ - BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); - port2port_name_map[generate_configuration_chain_tail_name()] = tail_port; - - /* Link the SRAM output ports of the memory module */ - VTR_ASSERT( 2 == mem_output_bus_ports.size() ); - port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0]; - port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1]; - break; - } - case SPICE_SRAM_MEMORY_BANK: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - return port2port_name_map; -} - -/********************************************************************* - * Create a port-to-port map for a ReRAM-based memory module - * Memory bank - * ----------- - * - * config_bus (BL) config_bus (WL) - * | | - * v v - * +-------------------------------------+ - * | ReRAM-based Memory Module | - * +-------------------------------------+ - * | | - * v v - * Mem_out Mem_outb - **********************************************************************/ -static -std::map generate_rram_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const e_sram_orgz& sram_orgz_type) { - std::map port2port_name_map; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not supported */ - break; - case SPICE_SRAM_SCAN_CHAIN: - /* TODO: to be supported */ - break; - case SPICE_SRAM_MEMORY_BANK: - /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - return port2port_name_map; -} - -/********************************************************************* - * Create a port-to-port map for a memory module - * The content of the port-to-port map will depend not only - * the design technology of the memory cells but also the - * configuration styles of FPGA fabric. - * Here we will branch on the design technology - **********************************************************************/ -std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const std::vector& config_bus_ports, - const std::vector& mem_output_bus_ports, - const e_spice_model_design_tech& mem_design_tech, - const e_sram_orgz& sram_orgz_type) { - std::map port2port_name_map; - - switch (mem_design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - port2port_name_map = generate_cmos_mem_module_port2port_map(module_manager, mem_module, config_bus_ports, mem_output_bus_ports, sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_RRAM: - port2port_name_map = generate_rram_mem_module_port2port_map(module_manager, mem_module, sram_orgz_type); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of memory design technology !\n", - __FILE__, __LINE__); - exit(1); - } - - return port2port_name_map; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index bee3e7ff8..17d395cdb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -38,12 +38,5 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, const e_sram_orgz sram_orgz_type, const size_t& port_size); -std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const std::vector& config_bus_ports, - const std::vector& mem_output_bus_ports, - const e_spice_model_design_tech& mem_design_tech, - const e_sram_orgz& sram_orgz_type); - #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index d08f5eb15..d784888d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -43,6 +43,7 @@ #include "mux_utils.h" #include "module_manager.h" #include "module_manager_utils.h" +#include "fpga_x2p_mem_utils.h" /* Include Verilog support headers*/ #include "verilog_global.h" @@ -2321,6 +2322,7 @@ static void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, + BasicPort& config_bus, const ModuleId& sb_module, const RRGSB& rr_sb, const CircuitLibrary& circuit_lib, @@ -2451,18 +2453,22 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, std::map mem_port2port_name_map; /* TODO: Make the port2port map generation more generic!!! */ - std::vector config_ports; - config_ports.push_back(BasicPort(generate_local_config_bus_port_name(), mux_instance_id - 1, mux_instance_id)); + /* Link the SRAM ports of the routing multiplexer to the memory module */ std::vector mem_output_ports; mem_output_ports.push_back(mux_config_port); mem_output_ports.push_back(mux_config_inv_port); mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, - config_ports, + config_bus, mem_output_ports, circuit_lib.design_tech_type(mux_model), cur_sram_orgz_info->type); + /* Update the config bus for the module */ + update_mem_module_config_bus(cur_sram_orgz_info->type, + circuit_lib.design_tech_type(mux_model), + mux_num_config_bits, + config_bus); - /* Print an instance of the MUX Module */ + /* Print an instance of the memory module associated with the routing multiplexer */ print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); print_verilog_module_instance(fp, module_manager, sb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); @@ -2491,6 +2497,7 @@ static void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, + BasicPort& config_bus, const ModuleId& sb_module, const RRGSB& rr_sb, const CircuitLibrary& circuit_lib, @@ -2525,7 +2532,7 @@ void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, drive_rr_nodes[DEFAULT_SWITCH_ID]); } else if (1 < drive_rr_nodes.size()) { /* Print the multiplexer, fan_in >= 2 */ - print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, + print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, config_bus, sb_module, rr_sb, circuit_lib, mux_lib, rr_switches, chan_side, cur_rr_node, drive_rr_nodes, @@ -2725,6 +2732,11 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage rr_gsb.get_sb_num_conf_bits()); print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); + /* Create a counter for the configuration bus */ + BasicPort config_bus; + /* Counter start from 0 */ + config_bus.set_width(0, 0); + /* TODO: Print routing multiplexers */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); @@ -2732,7 +2744,8 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, module_id, rr_sb, + print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, config_bus, + module_id, rr_sb, circuit_lib, mux_lib, rr_switches, side_manager.get_side(), itrack, is_explicit_mapping); @@ -2740,6 +2753,8 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage } } + /* TODO: Add check code for config_bus. The MSB should match the number of configuration bits!!! */ + /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); From 2d7e8d9811446cf2bfd84e8a939fb645622fbb6d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 5 Oct 2019 11:07:26 -0600 Subject: [PATCH 263/482] add check codes for memory buses --- .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp | 32 +++++++++++++++++++ .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.h | 4 +++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 27 +++++++++++++++- 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp index 2fd7c9872..f95f99a88 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp @@ -270,3 +270,35 @@ void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, exit(1); } } + +/******************************************************************** + * Check if the MSB of a configuration bus of a switch block + * matches the expected value + ********************************************************************/ +bool check_mem_config_bus(const e_sram_orgz& sram_orgz_type, + const BasicPort& config_bus, + const size_t& local_expected_msb) { + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Not supported */ + return false; + break; + case SPICE_SRAM_SCAN_CHAIN: + /* TODO: comment on why + */ + return (local_expected_msb == config_bus.get_msb()); + break; + case SPICE_SRAM_MEMORY_BANK: + /* TODO: comment on why + */ + return (local_expected_msb == config_bus.get_msb()); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + /* Reach here, it means something goes wrong, return a false value */ + return false; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h index 5a25cdcbd..831aca5a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h @@ -22,4 +22,8 @@ void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, const size_t& num_config_bits, BasicPort& config_bus); +bool check_mem_config_bus(const e_sram_orgz& sram_orgz_type, + const BasicPort& config_bus, + const size_t& local_expected_msb); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 61201e9fb..dc18bee40 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -63,7 +63,7 @@ void print_verilog_switch_block_local_sram_wires(std::fstream& fp, const RRGSB& rr_gsb, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, + const e_sram_orgz& sram_orgz_type, const size_t& port_size) { size_t local_port_size = port_size; if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { @@ -73,6 +73,28 @@ void print_verilog_switch_block_local_sram_wires(std::fstream& fp, print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); } +/******************************************************************** + * Check if the MSB of a configuration bus of a switch block + * matches the expected value + * Exception: + * 1. Configuration bus for configuration chain will follow + * the number of multiplexers in the switch block + ********************************************************************/ +static +bool check_switch_block_mem_config_bus(const e_sram_orgz& sram_orgz_type, + const RRGSB& rr_gsb, + const BasicPort& config_bus, + const size_t& expected_msb) { + size_t local_expected_msb = expected_msb; + if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { + /* Note the size of local wires is number of routing multiplexers + 1 + * Wire MSB is the number of routing multiplexers in the configuration chain + */ + local_expected_msb = find_switch_block_number_of_muxes(rr_gsb); + } + return check_mem_config_bus(sram_orgz_type, config_bus, local_expected_msb); +} + /********************************************************************* * Generate the Verilog module for a routing channel * Routing track wire, which is 1-input and dual output @@ -2763,6 +2785,9 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage } /* TODO: Add check code for config_bus. The MSB should match the number of configuration bits!!! */ + VTR_ASSERT(true == check_switch_block_mem_config_bus(cur_sram_orgz_info->type, + rr_gsb, config_bus, + rr_gsb.get_sb_num_conf_bits())); /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); From 027272c976850945c7c714cfee704bc88704efec Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Sat, 5 Oct 2019 12:10:55 -0600 Subject: [PATCH 264/482] Faster regression test --- .travis/script.sh | 2 +- openfpga_flow/tasks/explicit_verilog/config/task.conf | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index 37e96e1a8..73e2a1ed2 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3 end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf index be4320161..0634a32c5 100644 --- a/openfpga_flow/tasks/explicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf @@ -16,6 +16,7 @@ fpga_flow=vpr_blif [ARCHITECTURES] arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +#arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif @@ -27,7 +28,7 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] -fix_route_chan_width=300 +min_route_chan_width=1.3 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_include_timing= @@ -39,3 +40,4 @@ vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_x2p_compact_routing_hierarchy= vpr_fpga_verilog_explicit_mapping= end_flow_with_test= + From c920047ee8c206c86a174e7718a2396cf54c84b8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 5 Oct 2019 18:14:23 -0600 Subject: [PATCH 265/482] refactored Verilog generation for connection blocks --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 74 ++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 11 + .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 84 +++ .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.h | 8 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 646 ++++++++++++++++++ 5 files changed, 823 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index d39d4961a..597329292 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -168,6 +168,30 @@ std::string generate_routing_block_netlist_name(const std::string& prefix, return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix ); } +/********************************************************************* + * Generate the netlist name for a connection block with a given coordinate + *********************************************************************/ +std::string generate_connection_block_netlist_name(const t_rr_type& cb_type, + const vtr::Point& coordinate, + const std::string& postfix) { + std::string prefix("cb"); + switch (cb_type) { + case CHANX: + prefix += std::string("x_"); + break; + case CHANY: + prefix += std::string("y_"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid type of connection block!\n", + __FILE__, __LINE__); + exit(1); + } + + return generate_routing_block_netlist_name(prefix, coordinate, postfix); +} + /********************************************************************* * Generate the module name for a unique routing channel *********************************************************************/ @@ -242,6 +266,33 @@ std::string generate_routing_track_port_name(const t_rr_type& chan_type, return port_name; } +/********************************************************************* + * Generate the middle output port name for a routing track + * with a given coordinate + *********************************************************************/ +std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, + const vtr::Point& coordinate, + const size_t& track_id) { + /* Channel must be either CHANX or CHANY */ + VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); + + /* Create a map between chan_type and module_prefix */ + std::map module_prefix_map; + /* TODO: use a constexpr string to replace the fixed name? */ + module_prefix_map[CHANX] = std::string("chanx"); + module_prefix_map[CHANY] = std::string("chany"); + + std::string port_name = module_prefix_map[chan_type]; + port_name += std::string("_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("__")); + + port_name += std::string("midout_"); + + /* Add the track id to the port name */ + port_name += std::to_string(track_id) + std::string("_"); + + return port_name; +} + /********************************************************************* * Generate the module name for a switch block with a given coordinate *********************************************************************/ @@ -249,6 +300,29 @@ std::string generate_switch_block_module_name(const vtr::Point& coordina return std::string( "sb_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") ); } +/********************************************************************* + * Generate the module name for a connection block with a given coordinate + *********************************************************************/ +std::string generate_connection_block_module_name(const t_rr_type& cb_type, + const vtr::Point& coordinate) { + std::string prefix("cb"); + switch (cb_type) { + case CHANX: + prefix += std::string("x_"); + break; + case CHANY: + prefix += std::string("y_"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid type of connection block!\n", + __FILE__, __LINE__); + exit(1); + } + + return std::string( prefix + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") ); +} + /********************************************************************* * Generate the port name for a Grid * TODO: add more comments about why we need different names for diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 6d7f9c88c..bd7ced7b8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -48,6 +48,10 @@ std::string generate_routing_block_netlist_name(const std::string& prefix, const vtr::Point& block_id, const std::string& postfix); +std::string generate_connection_block_netlist_name(const t_rr_type& cb_type, + const vtr::Point& coordinate, + const std::string& postfix); + std::string generate_routing_channel_module_name(const t_rr_type& chan_type, const size_t& block_id); @@ -59,8 +63,15 @@ std::string generate_routing_track_port_name(const t_rr_type& chan_type, const size_t& track_id, const PORTS& port_direction); +std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, + const vtr::Point& coordinate, + const size_t& track_id); + std::string generate_switch_block_module_name(const vtr::Point& coordinate); +std::string generate_connection_block_module_name(const t_rr_type& cb_type, + const vtr::Point& coordinate); + std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& height, const e_side& side, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index 197da9c8b..9184e29d6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -8,6 +8,64 @@ #include "vpr_types.h" #include "fpga_x2p_types.h" #include "rr_blocks_utils.h" + +/********************************************************************* + * This function will find the global ports required by a Connection Block + * module. It will find all the circuit models in the circuit library + * that may be included in the connection block + * Collect the global ports from the circuit_models and merge with the same name + ********************************************************************/ +std::vector find_connection_block_global_ports(const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const std::vector& switch_lib) { + std::vector sub_models; + /* Walk through the OUTPUT nodes at each side of a GSB, + * get the switch id of incoming edges + * and get the circuit model linked to the switch id + */ + std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + /* Find the size of routing multiplexers driving this IPIN node */ + int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; + /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ + if (2 > mux_size) { + continue; + } + /* Find the driver switch of the node */ + short driver_switch = rr_gsb.get_ipin_node(cb_ipin_side, inode)->drive_switches[DEFAULT_SWITCH_ID]; + /* Find the circuit model id of the driver switch */ + VTR_ASSERT( (size_t)driver_switch < switch_lib.size() ); + /* Get the model, and try to add to the sub_model list */ + CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model; + /* Make sure it is a valid id */ + VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model ); + /* Get the model, and try to add to the sub_model list */ + if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) { + /* Not yet in the list, add it */ + sub_models.push_back(switch_circuit_model); + } + } + } + + std::vector global_ports; + /* Iterate over the model list, and add the global ports*/ + for (const auto& model : sub_models) { + std::vector temp_global_ports = circuit_lib.model_global_ports(model, true); + /* Add the temp_global_ports to the list to be returned, make sure we do not have any duplicated ports */ + for (const auto& port_candidate : temp_global_ports) { + if (global_ports.end() == std::find(global_ports.begin(), global_ports.end(), port_candidate)) { + /* Not yet in the list, add it */ + global_ports.push_back(port_candidate); + } + } + } + + return global_ports; +} + /********************************************************************* * This function will find the global ports required by a Switch Block @@ -61,6 +119,32 @@ std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, return global_ports; } +/********************************************************************* + * This function will find the number of multiplexers required by + * a connection Block module. + ********************************************************************/ +size_t find_connection_block_number_of_muxes(const RRGSB& rr_gsb, + const t_rr_type& cb_type) { + size_t num_muxes = 0; + + std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + /* Find the size of routing multiplexers driving this IPIN node */ + int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; + /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ + if (2 > mux_size) { + continue; + } + /* This means we need a multiplexer, update the counter */ + num_muxes++; + } + } + + return num_muxes; +} + /********************************************************************* * This function will find the number of multiplexers required by * a Switch Block module. diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h index d49a55539..0ad9113fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h @@ -10,10 +10,18 @@ #include "circuit_library.h" #include "rr_blocks.h" +std::vector find_connection_block_global_ports(const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const std::vector& switch_lib); + std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, const CircuitLibrary& circuit_lib, const std::vector& switch_lib); +size_t find_connection_block_number_of_muxes(const RRGSB& rr_gsb, + const t_rr_type& cb_type); + size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index dc18bee40..4ba51216f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -51,6 +51,30 @@ #include "verilog_writer_utils.h" #include "verilog_routing.h" +/******************************************************************** + * Print local wires that are used for SRAM configuration + * This function is supposed to be used by Verilog generation + * of connection blocks + * It will count the number of connection blocks, which is the + * port width for local wires when Configuration chain is used + ********************************************************************/ +static +void print_verilog_connection_block_local_sram_wires(std::fstream& fp, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type, + const size_t& port_size) { + size_t local_port_size = port_size; + if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { + /* Plus 1 for the wire size to connect to the tail of the configuration chain */ + local_port_size = find_connection_block_number_of_muxes(rr_gsb, cb_type) + 1; + } + print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); +} + + /******************************************************************** * Print local wires that are used for SRAM configuration * This function is supposed to be used by Verilog generation @@ -2180,6 +2204,29 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ +static +BasicPort generate_verilog_connection_box_ipin_port(const RRGSB& rr_gsb, + t_rr_node* src_rr_node) { + + /* Ensure the src_rr_node is an input pin of a CLB */ + VTR_ASSERT(IPIN == src_rr_node->type); + /* Create port description for input pin of a CLB */ + vtr::Point port_coord(src_rr_node->xlow, src_rr_node->ylow); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + enum e_side cb_ipin_side = NUM_SIDES; + int cb_ipin_index = -1; + rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); + /* We need to be sure that drive_rr_node is part of the CB */ + VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); + std::string port_name = generate_grid_side_port_name(port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, cb_ipin_index), + rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); + return BasicPort(port_name, 1); /* Every grid output has a port size of 1 */ +} + /********************************************************************* * Generate a port for a routing track of a swtich block ********************************************************************/ @@ -2202,6 +2249,39 @@ BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb, return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */ } +/********************************************************************* + * Generate an input port for routing multiplexer inside the connection block + * which is the middle output of a routing track + ********************************************************************/ +static +BasicPort generate_connection_block_chan_port(const RRGSB& rr_gsb, + const t_rr_type& cb_type, + t_rr_node* chan_rr_node) { + BasicPort input_port; + /* Generate the input port object */ + switch (chan_rr_node->type) { + case CHANX: + case CHANY: { + /* Create port description for the routing track middle output */ + vtr::Point middle_output_port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); + /* Create a port description for the middle output */ + std::string middle_output_port_name = generate_routing_track_middle_output_port_name(cb_type, middle_output_port_coord, chan_node_track_id); + input_port.set_name(middle_output_port_name); + input_port.set_width(1); + break; + } + default: /* OPIN, SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + return input_port; +} + + /********************************************************************* * Generate an input port for routing multiplexer inside the switch block * In addition to give the Routing Resource node of the input @@ -2254,6 +2334,24 @@ BasicPort generate_switch_block_input_port(const RRGSB& rr_sb, return input_port; } +/********************************************************************* + * Generate a list of routing track middle output ports + * for routing multiplexer inside the connection block + ********************************************************************/ +static +std::vector generate_connection_block_mux_input_ports(const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector& input_rr_nodes) { + std::vector input_ports; + + for (auto input_rr_node : input_rr_nodes) { + input_ports.push_back(generate_connection_block_chan_port(rr_gsb, cb_type, input_rr_node)); + } + + return input_ports; +} + + /********************************************************************* * Generate a list of input ports for routing multiplexer inside the switch block ********************************************************************/ @@ -3301,6 +3399,46 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c return num_reserved_conf_bits; } +/********************************************************************* + * Print a short interconneciton in connection + ********************************************************************/ +static +void print_verilog_connection_box_short_interc(std::fstream& fp, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + t_rr_node* src_rr_node) { + /* Check the file handler*/ + check_file_handler(fp); + + /* Ensure we have only one 1 driver node */ + VTR_ASSERT_SAFE(1 == src_rr_node->fan_in); + + /* Find the driver node */ + t_rr_node* drive_rr_node = src_rr_node->drive_rr_nodes[0]; + + /* We have OPINs since we may have direct connections: + * These connections should be handled by other functions in the compact_netlist.c + * So we just return here for OPINs + */ + if (OPIN == drive_rr_node->type) { + return; + } + + VTR_ASSERT((CHANX == drive_rr_node->type) || (CHANY == drive_rr_node->type)); + + /* Create port description for the routing track middle output */ + BasicPort middle_output_port = generate_connection_block_chan_port(rr_gsb, cb_type, drive_rr_node); + + /* Create port description for input pin of a CLB */ + BasicPort input_port = generate_verilog_connection_box_ipin_port(rr_gsb, src_rr_node); + + /* Print the wire connection */ + print_verilog_wire_connection(fp, input_port, middle_output_port, false); + + return; +} + + /* SRC rr_node is the IPIN of a grid.*/ static void dump_verilog_connection_box_short_interc(FILE* fp, @@ -3451,6 +3589,186 @@ void dump_verilog_connection_box_short_interc(FILE* fp, return; } +/********************************************************************* + * Print a Verilog instance of a routing multiplexer as well as + * associated memory modules for a connection inside a connection block + ********************************************************************/ +static +void print_verilog_connection_box_mux(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info, + BasicPort& config_bus, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* cur_rr_node, + const bool& use_explicit_mapping) { + /* Check the file handler*/ + check_file_handler(fp); + + /* Check */ + /* Check current rr_node is an input pin of a CLB */ + VTR_ASSERT(IPIN == cur_rr_node->type); + + /* Build a vector of driver rr_nodes */ + std::vector drive_rr_nodes; + for (int inode = 0; inode < cur_rr_node->num_drive_rr_nodes; inode++) { + drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[inode]); + } + + int switch_index = cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]; + + /* Get the circuit model id of the routing multiplexer */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); + + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + + /* Find the module name of the multiplexer and try to find it in the module manager */ + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + + /* Get the MUX instance id from the module manager */ + size_t mux_instance_id = module_manager.num_instance(cb_module, mux_module); + + /* Print the input bus for the inputs of a multiplexer + * We use the datapath input size (mux_size) to name the bus + * just to following the naming convention when the tool is built + * The bus port size should be the input size of multiplexer implementation + */ + BasicPort inbus_port; + inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); + inbus_port.set_width(datapath_mux_size); + + /* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */ + std::vector mux_input_ports = generate_connection_block_mux_input_ports(rr_gsb, cb_type, drive_rr_nodes); + /* Connect input ports to bus */ + print_verilog_comment(fp, std::string("----- BEGIN A local bus wire for multiplexer inputs -----")); + fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; + print_verilog_comment(fp, std::string("----- END A local bus wire for multiplexer inputs -----")); + fp << std::endl; + + /* Find the number of reserved configuration bits for the routing multiplexer */ + size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); + + /* Find the number of configuration bits for the routing multiplexer */ + size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); + + /* Print the configuration bus for the routing multiplexers */ + print_verilog_comment(fp, std::string("----- BEGIN Local wires to group configuration ports -----")); + print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, + datapath_mux_size, mux_instance_id, + mux_num_reserved_config_bits, mux_num_config_bits); + print_verilog_comment(fp, std::string("----- END Local wires to group configuration ports -----")); + fp << std::endl; + + /* Dump ports visible only during formal verification */ + print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); + print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); + /* Print the SRAM configuration ports for formal verification */ + /* TODO: align with the port width of formal verification port of SB module */ + print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, + datapath_mux_size, mux_instance_id, mux_num_config_bits); + print_verilog_endif(fp); + print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); + fp << std::endl; + + /* Instanciate the MUX Module */ + /* Create port-to-port map */ + std::map mux_port2port_name_map; + + /* Link input bus port to routing track middle outputs */ + std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == mux_model_input_ports.size()); + /* Use the port name convention in the circuit library */ + mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_input_ports[0])] = inbus_port; + + /* Link output port to Connection Block output: src_rr_node */ + std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == mux_model_output_ports.size()); + /* Use the port name convention in the circuit library */ + mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_output_ports[0])] = generate_verilog_connection_box_ipin_port(rr_gsb, cur_rr_node); + + /* Link SRAM port to different configuraton port for the routing multiplexer + * Different design technology requires different configuration bus! + */ + std::vector mux_model_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); + VTR_ASSERT( 1 == mux_model_sram_ports.size() ); + /* For the regular SRAM port, module port use the same name */ + std::string mux_module_sram_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]); + BasicPort mux_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), + mux_num_config_bits); + mux_port2port_name_map[mux_module_sram_port_name] = mux_config_port; + + /* For the inverted SRAM port */ + std::string mux_module_sram_inv_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]) + std::string("_inv"); + BasicPort mux_config_inv_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), + mux_num_config_bits); + mux_port2port_name_map[mux_module_sram_inv_port_name] = mux_config_inv_port; + + /* Print an instance of the MUX Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a routing multiplexer -----")); + print_verilog_module_instance(fp, module_manager, cb_module, mux_module, mux_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of a routing multiplexer -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(cb_module, mux_module); + + /* Instanciate memory modules */ + /* Find the name and module id of the memory module */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + ModuleId mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + + /* Create port-to-port map */ + std::map mem_port2port_name_map; + + /* TODO: Make the port2port map generation more generic!!! */ + /* Link the SRAM ports of the routing multiplexer to the memory module */ + std::vector mem_output_ports; + mem_output_ports.push_back(mux_config_port); + mem_output_ports.push_back(mux_config_inv_port); + mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, + config_bus, + mem_output_ports, + circuit_lib.design_tech_type(mux_model), + cur_sram_orgz_info->type); + /* Update the config bus for the module */ + update_mem_module_config_bus(cur_sram_orgz_info->type, + circuit_lib.design_tech_type(mux_model), + mux_num_config_bits, + config_bus); + + /* Print an instance of the memory module associated with the routing multiplexer */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); + print_verilog_module_instance(fp, module_manager, cb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(cb_module, mem_module); + + /* Create the path of the input of multiplexer in the hierarchy + * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! + */ + std::string mux_input_hie_path = std::string(rr_gsb.gen_cb_verilog_instance_name(cb_type)) + std::string("/") + + mux_module_name + std::string("_") + + std::to_string(mux_instance_id) + std::string("_/in"); + cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); +} + + static void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -3943,6 +4261,43 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, return; } +/******************************************************************** + * Print internal connections of a connection block + * For a IPIN node that is driven by only 1 fan-in, + * a short wire will be created + * For a IPIN node that is driven by more than two fan-ins, + * a routing multiplexer will be instanciated + ********************************************************************/ +static +void print_verilog_connection_box_interc(ModuleManager& module_manager, + std::fstream& fp, + t_sram_orgz_info* cur_sram_orgz_info, + BasicPort& config_bus, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* src_rr_node, + const bool& use_explicit_mapping) { + if (1 > src_rr_node->fan_in) { + return; /* This port has no driver, skip it */ + } else if (1 == src_rr_node->fan_in) { + /* Print a direct connection */ + print_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); + + } else if (1 < src_rr_node->fan_in) { + /* Print the multiplexer, fan_in >= 2 */ + print_verilog_connection_box_mux(module_manager, fp, cur_sram_orgz_info, config_bus, + cb_module, rr_gsb, cb_type, + circuit_lib, mux_lib, rr_switches, + src_rr_node, use_explicit_mapping); + } /*Nothing should be done else*/ + + return; +} + static void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -4090,6 +4445,279 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o return num_reserved_conf_bits; } +/******************************************************************** + * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) + * Actually it is very similiar to switch box but + * the difference is connection boxes connect Grid INPUT Pins to channels + * NOTE: direct connection between CLBs should NOT be included inside this + * module! They should be added in the top-level module as their connection + * is not limited to adjacent CLBs!!! + * + * Location of a X- and Y-direction Connection Block in FPGA fabric + * +------------+ +-------------+ + * | |------>| | + * | CLB |<------| Y-direction | + * | | ... | Connection | + * | |------>| Block | + * +------------+ +-------------+ + * | ^ ... | | ^ ... | + * v | v v | v + * +-------------------+ +-------------+ + * --->| |--->| | + * <---| X-direction |<---| Switch | + * ...| Connection block |... | Block | + * --->| |--->| | + * +-------------------+ +-------------+ + * + * Internal structure: + * This is an example of a X-direction connection block + * Note that middle output ports are shorted wire from inputs of routing tracks, + * which are also the inputs of routing multiplexer of the connection block + * + * CLB Input Pins + * (IPINs) + * ^ ^ ^ + * | | ... | + * +--------------------------+ + * | ^ ^ ^ | + * | | | ... | | + * | +--------------------+ | + * | | routing | | + * | | multiplexers | | + * | +--------------------+ | + * | middle outputs | + * | of routing channel | + * | ^ ^ ^ ^ ^ ^ ^ ^ | + * | | | | | ... | | | | | + * in[0] -->|------------------------->|---> out[0] + * out[1] <--|<-------------------------|<--- in[1] + * | ... | + * in[W-2] -->|------------------------->|---> out[W-2] + * out[W-1] <--|<-------------------------|<--- in[W-1] + * +--------------------------+ + * + * W: routing channel width + * + ********************************************************************/ +static +void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + const RRGSB& rr_cb, + const t_rr_type& cb_type, + const bool& use_explicit_mapping) { + RRGSB rr_gsb = rr_cb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ + + /* TODO: These should be done when initializing the tool */ + /* Count the number of configuration bits to be consumed by this Switch block */ + int num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, cb_type); + /* Count the number of reserved configuration bits to be consumed by this Switch block */ + int num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, cb_type); + /* Estimate the sram_verilog_model->cnt */ + int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + /* Record index */ + rr_gsb.set_cb_num_reserved_conf_bits(cb_type, num_reserved_conf_bits); + rr_gsb.set_cb_conf_bits_lsb(cb_type, cur_num_sram); + rr_gsb.set_cb_conf_bits_msb(cb_type, cur_num_sram + num_conf_bits - 1); + + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); + + /* Add ports to the module */ + /* Global ports: + * In the circuit_library, find all the circuit models that may be included in the Connection Block + * Collect the global ports from the circuit_models and merge with the same name + */ + std::vector global_ports = find_connection_block_global_ports(rr_gsb, cb_type, circuit_lib, rr_switches); + for (const auto& port : global_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT); + } + + /* Add the input and output ports of routing tracks in the channel + * Routing tracks pass through the connection blocks + */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + IN_PORT); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + } + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + OUT_PORT); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* Add the input pins of grids, which are output ports of the connection block */ + std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); + std::string port_name = generate_grid_side_port_name(port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), + ipin_node->ptc_num); + BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); + } + } + + /* Add configuration ports */ + /* Reserved sram ports */ + if (0 < rr_gsb.get_cb_num_reserved_conf_bits(cb_type)) { + /* Check: this SRAM organization type must be memory-bank ! */ + VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); + /* Generate a list of ports */ + add_reserved_sram_ports_to_module_manager(module_manager, module_id, + rr_gsb.get_cb_num_reserved_conf_bits(cb_type)); + } + + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* Normal sram ports */ + if (0 < rr_gsb.get_cb_num_conf_bits(cb_type)) { + add_sram_ports_to_module_manager(module_manager, module_id, + circuit_lib, sram_model, cur_sram_orgz_info->type, + rr_gsb.get_cb_num_conf_bits(cb_type)); + /* Add ports only visible during formal verification to the module */ + add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, + std::string(verilog_formal_verification_preproc_flag), + rr_gsb.get_cb_num_conf_bits(cb_type)); + } + + /* Print module definition + ports */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish printing ports */ + + /* Print an empty line a splitter */ + fp << std::endl; + + /* Print local wires, which are middle outputs of routing tracks */ + print_verilog_comment(fp, std::string("---- BEGIN local wires for middle output ports of routing tracks ----")); + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + /* Create a port description for the middle output */ + std::string port_name = generate_routing_track_middle_output_port_name(cb_type, + port_coord, itrack); + BasicPort middle_output_port(port_name, 1); + fp << generate_verilog_port(VERILOG_PORT_WIRE, middle_output_port) << ";" << std::endl; + } + print_verilog_comment(fp, std::string("---- END local wires for middle output ports of routing tracks ----")); + /* Print an empty line a splitter */ + fp << std::endl; + + /* Print short-wire connection for each routing track : + * Each input port is short-wired to its output port and middle output port + * + * in[i] ----------> out[i] + * | + * +-----> mid_out[i] + */ + print_verilog_comment(fp, std::string("---- BEGIN wire connection between inputs, outputs and middle outputs of routing tracks ----")); + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + /* Create a port description for the input */ + std::string input_port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + IN_PORT); + BasicPort input_port(input_port_name, 1); /* Every track has a port size of 1 */ + + /* Create a port description for the output */ + std::string output_port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + OUT_PORT); + BasicPort output_port(output_port_name, 1); /* Every track has a port size of 1 */ + + /* Create a port description for the middle output */ + std::string middle_output_port_name = generate_routing_track_middle_output_port_name(cb_type, port_coord, itrack); + BasicPort middle_output_port(middle_output_port_name, 1); + + /* Print short-wires: input port ---> output port */ + print_verilog_wire_connection(fp, output_port, input_port, false); + /* Print short-wires: input port ---> middle output port */ + print_verilog_wire_connection(fp, middle_output_port, input_port, false); + } + print_verilog_comment(fp, std::string("---- END wire connection between inputs, outputs and middle outputs of routing tracks ----")); + + /* Print an empty line a splitter */ + fp << std::endl; + + print_verilog_comment(fp, std::string("---- BEGIN local wires for SRAM data ports ----")); + /* Print local wires for memory configurations */ + print_verilog_connection_block_local_sram_wires(fp, rr_gsb, cb_type, circuit_lib, sram_model, cur_sram_orgz_info->type, + rr_gsb.get_cb_num_conf_bits(cb_type)); + print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); + + /* Print an empty line a splitter */ + fp << std::endl; + + /* Create a counter for the configuration bus */ + BasicPort config_bus; + /* Counter start from 0 */ + config_bus.set_width(0, 0); + + /* TODO: Print routing multiplexers or direct interconnect*/ + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + print_verilog_connection_box_interc(module_manager, fp, cur_sram_orgz_info, + config_bus, module_id, rr_gsb, cb_type, + circuit_lib, mux_lib, rr_switches, + rr_gsb.get_ipin_node(cb_ipin_side, inode), + use_explicit_mapping); + } + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + */ +} + + + /* Print connection boxes * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) * Actually it is very similiar to switch box but @@ -4672,6 +5300,15 @@ void print_verilog_routing_resources(ModuleManager& module_manager, dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX, explicit_port_mapping); + + print_verilog_routing_connection_box_unique_module(module_manager, + arch.spice->circuit_lib, mux_lib, + rr_switches, + cur_sram_orgz_info, + std::string(verilog_dir), + std::string(subckt_dir), + unique_mirror, CHANX, + explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ @@ -4680,6 +5317,15 @@ void print_verilog_routing_resources(ModuleManager& module_manager, dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY, explicit_port_mapping); + + print_verilog_routing_connection_box_unique_module(module_manager, + arch.spice->circuit_lib, mux_lib, + rr_switches, + cur_sram_orgz_info, + std::string(verilog_dir), + std::string(subckt_dir), + unique_mirror, CHANY, + explicit_port_mapping); } /* Restore sram_orgz_info to the base */ From 393f0b0ac3899646ceb6a644e91d98023c2fbe33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 5 Oct 2019 21:16:48 -0600 Subject: [PATCH 266/482] align formal verification port inside refactored routing blocks --- .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 80 +++++++++++++++++ .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.h | 14 +++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 87 ++++++++++++++++--- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 13 ++- .../fpga_x2p/verilog/verilog_writer_utils.h | 3 +- 5 files changed, 182 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index 9184e29d6..96dff6375 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -6,6 +6,7 @@ #include "vtr_assert.h" #include "vpr_types.h" +#include "mux_utils.h" #include "fpga_x2p_types.h" #include "rr_blocks_utils.h" @@ -176,3 +177,82 @@ size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb) { return num_muxes; } +/********************************************************************* + * Find the number of configuration bits of a Connection Block + ********************************************************************/ +size_t find_connection_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb, + const t_rr_type& cb_type) { + size_t num_conf_bits = 0; + + std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + /* Find the size of routing multiplexers driving this IPIN node */ + int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; + /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ + if (2 > mux_size) { + continue; + } + + /* Get the circuit model id of the routing multiplexer */ + size_t switch_index = rr_gsb.get_ipin_node(cb_ipin_side, inode)->drive_switches[DEFAULT_SWITCH_ID]; + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + num_conf_bits += find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); + } + } + + return num_conf_bits; +} + + +/********************************************************************* + * Find the number of configuration bits of a Switch Block + ********************************************************************/ +size_t find_switch_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb) { + size_t num_conf_bits = 0; + + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + /* Check if this node is just a passing wire */ + if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { + continue; + } + /* Check if this node has more than 2 drivers */ + if (2 > rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { + continue; + } + /* Get the circuit model id of the routing multiplexer */ + size_t switch_index = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->drive_switches[DEFAULT_SWITCH_ID]; + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes; + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + num_conf_bits += find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); + } + } + + return num_conf_bits; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h index 0ad9113fb..78bb981d5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h @@ -9,6 +9,7 @@ #include "physical_types.h" #include "circuit_library.h" #include "rr_blocks.h" +#include "mux_library.h" std::vector find_connection_block_global_ports(const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -24,4 +25,17 @@ size_t find_connection_block_number_of_muxes(const RRGSB& rr_gsb, size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb); +size_t find_connection_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb, + const t_rr_type& cb_type); + +size_t find_switch_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 4ba51216f..57eb32e21 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -97,6 +97,30 @@ void print_verilog_switch_block_local_sram_wires(std::fstream& fp, print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); } +/******************************************************************** + * Check if the MSB of a configuration bus of a connection block + * matches the expected value + * Exception: + * 1. Configuration bus for configuration chain will follow + * the number of multiplexers in the connection block + ********************************************************************/ +static +bool check_connection_block_mem_config_bus(const e_sram_orgz& sram_orgz_type, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const BasicPort& config_bus, + const size_t& expected_msb) { + size_t local_expected_msb = expected_msb; + if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { + /* Note the size of local wires is number of routing multiplexers + 1 + * Wire MSB is the number of routing multiplexers in the configuration chain + */ + local_expected_msb = find_connection_block_number_of_muxes(rr_gsb, cb_type); + } + return check_mem_config_bus(sram_orgz_type, config_bus, local_expected_msb); +} + + /******************************************************************** * Check if the MSB of a configuration bus of a switch block * matches the expected value @@ -2452,6 +2476,7 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, BasicPort& config_bus, + BasicPort& fm_config_bus, const ModuleId& sb_module, const RRGSB& rr_sb, const CircuitLibrary& circuit_lib, @@ -2522,9 +2547,15 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); /* Print the SRAM configuration ports for formal verification */ - /* TODO: align with the port width of formal verification port of SB module */ + /* Update config bus for formal verification, + * shift with number of configuration bit of the MUX + */ + fm_config_bus.set_width(fm_config_bus.get_msb() + 1, fm_config_bus.get_msb() + mux_num_config_bits); + + /* Align with the port width of formal verification port of SB module */ print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, - datapath_mux_size, mux_instance_id, mux_num_config_bits); + datapath_mux_size, mux_instance_id, + mux_num_config_bits, fm_config_bus); print_verilog_endif(fp); print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); fp << std::endl; @@ -2627,6 +2658,7 @@ void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, BasicPort& config_bus, + BasicPort& fm_config_bus, const ModuleId& sb_module, const RRGSB& rr_sb, const CircuitLibrary& circuit_lib, @@ -2661,7 +2693,8 @@ void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, drive_rr_nodes[DEFAULT_SWITCH_ID]); } else if (1 < drive_rr_nodes.size()) { /* Print the multiplexer, fan_in >= 2 */ - print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, config_bus, + print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, + config_bus, fm_config_bus, sb_module, rr_sb, circuit_lib, mux_lib, rr_switches, chan_side, cur_rr_node, drive_rr_nodes, @@ -2745,7 +2778,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage const bool& is_explicit_mapping) { /* TODO: move this part to another function where we count the conf bits for all the switch blocks !!!*/ /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_switch_box_conf_bits(cur_sram_orgz_info, rr_sb); + int num_conf_bits = find_switch_block_num_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_sb); /* Count the number of reserved configuration bits to be consumed by this Switch block */ int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb); /* Estimate the sram_verilog_model->cnt */ @@ -2866,6 +2899,11 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage /* Counter start from 0 */ config_bus.set_width(0, 0); + /* Create a counter for the configuration bus used for formal verification */ + BasicPort fm_config_bus; + /* fm_config_bus has an invalid width here. It is designed to be easy to rotate */ + fm_config_bus.set_width(0, -1); + /* TODO: Print routing multiplexers */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); @@ -2873,7 +2911,8 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, config_bus, + print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, + config_bus, fm_config_bus, module_id, rr_sb, circuit_lib, mux_lib, rr_switches, side_manager.get_side(), @@ -2882,10 +2921,13 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage } } - /* TODO: Add check code for config_bus. The MSB should match the number of configuration bits!!! */ + /* Add check code for config_bus. + * The MSB should match the number of configuration bits!!! + */ VTR_ASSERT(true == check_switch_block_mem_config_bus(cur_sram_orgz_info->type, rr_gsb, config_bus, rr_gsb.get_sb_num_conf_bits())); + VTR_ASSERT(fm_config_bus.get_msb() == rr_gsb.get_sb_num_conf_bits() - 1); /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); @@ -3598,6 +3640,7 @@ void print_verilog_connection_box_mux(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, BasicPort& config_bus, + BasicPort& fm_config_bus, const ModuleId& cb_module, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -3674,9 +3717,14 @@ void print_verilog_connection_box_mux(ModuleManager& module_manager, print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); /* Print the SRAM configuration ports for formal verification */ - /* TODO: align with the port width of formal verification port of SB module */ + /* Update config bus for formal verification, + * shift with number of configuration bit of the MUX + */ + fm_config_bus.set_width(fm_config_bus.get_msb() + 1, fm_config_bus.get_msb() + mux_num_config_bits); + /* Align with the port width of formal verification port of SB module */ print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, - datapath_mux_size, mux_instance_id, mux_num_config_bits); + datapath_mux_size, mux_instance_id, + mux_num_config_bits, fm_config_bus); print_verilog_endif(fp); print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); fp << std::endl; @@ -4273,6 +4321,7 @@ void print_verilog_connection_box_interc(ModuleManager& module_manager, std::fstream& fp, t_sram_orgz_info* cur_sram_orgz_info, BasicPort& config_bus, + BasicPort& fm_config_bus, const ModuleId& cb_module, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -4289,7 +4338,8 @@ void print_verilog_connection_box_interc(ModuleManager& module_manager, } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - print_verilog_connection_box_mux(module_manager, fp, cur_sram_orgz_info, config_bus, + print_verilog_connection_box_mux(module_manager, fp, cur_sram_orgz_info, + config_bus, fm_config_bus, cb_module, rr_gsb, cb_type, circuit_lib, mux_lib, rr_switches, src_rr_node, use_explicit_mapping); @@ -4514,7 +4564,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma /* TODO: These should be done when initializing the tool */ /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = count_verilog_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, cb_type); + int num_conf_bits = (int)find_connection_block_num_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_gsb, cb_type); /* Count the number of reserved configuration bits to be consumed by this Switch block */ int num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, cb_type); /* Estimate the sram_verilog_model->cnt */ @@ -4689,18 +4739,33 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma /* Counter start from 0 */ config_bus.set_width(0, 0); + /* Create a counter for the configuration bus used for formal verification */ + BasicPort fm_config_bus; + /* fm_config_bus has an invalid width here. It is designed to be easy to rotate */ + fm_config_bus.set_width(0, -1); + /* TODO: Print routing multiplexers or direct interconnect*/ for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { print_verilog_connection_box_interc(module_manager, fp, cur_sram_orgz_info, - config_bus, module_id, rr_gsb, cb_type, + config_bus, fm_config_bus, + module_id, rr_gsb, cb_type, circuit_lib, mux_lib, rr_switches, rr_gsb.get_ipin_node(cb_ipin_side, inode), use_explicit_mapping); } } + /* Add check code for config_bus. + * The MSB should match the number of configuration bits!!! + */ + VTR_ASSERT(true == check_connection_block_mem_config_bus(cur_sram_orgz_info->type, + rr_gsb, cb_type, config_bus, + rr_gsb.get_cb_num_conf_bits(cb_type))); + VTR_ASSERT(fm_config_bus.get_msb() == rr_gsb.get_cb_num_conf_bits(cb_type) - 1); + + /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 4b93c2cd2..2a4025cf3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -1027,21 +1027,28 @@ void print_verilog_mux_config_bus(std::fstream& fp, * Print a wire to connect MUX configuration ports * This function connects the sram ports to the ports of a Verilog module * used for formal verification + * + * Note: MSB and LSB of formal verification configuration bus MUST be updated + * before running this function !!!! *********************************************************************/ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& mux_model, const size_t& mux_size, const size_t& mux_instance_id, - const size_t& num_conf_bits) { + const size_t& num_conf_bits, + const BasicPort& fm_config_bus) { BasicPort mux_sram_output(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), num_conf_bits); /* Get the SRAM model of the mux_model */ std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ VTR_ASSERT( 1 == sram_models.size() ); - BasicPort formal_verification_port(generate_formal_verification_sram_port_name(circuit_lib, sram_models[0]), - num_conf_bits); + BasicPort formal_verification_port; + formal_verification_port.set_name(generate_formal_verification_sram_port_name(circuit_lib, sram_models[0])); + VTR_ASSERT(num_conf_bits == fm_config_bus.get_width()); + formal_verification_port.set_lsb(fm_config_bus.get_lsb()); + formal_verification_port.set_msb(fm_config_bus.get_msb()); print_verilog_wire_connection(fp, mux_sram_output, formal_verification_port, false); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index c95bfbb18..e53ac0a40 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -104,6 +104,7 @@ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, const CircuitModelId& mux_model, const size_t& mux_size, const size_t& mux_instance_id, - const size_t& num_conf_bits); + const size_t& num_conf_bits, + const BasicPort& fm_config_bus); #endif From 1e183e7885831342a15feec99d593fdc6fd932b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 6 Oct 2019 16:57:53 -0600 Subject: [PATCH 267/482] refactored shared config bits calculation --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 45 ++++++++ vpr7_x2p/vpr/SRC/device/mux_graph.h | 5 + vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 106 ++++++++++++++++++ vpr7_x2p/vpr/SRC/device/mux_utils.h | 5 + .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 79 +++++++++++++ .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.h | 13 +++ .../SRC/fpga_x2p/verilog/verilog_routing.c | 4 +- 7 files changed, 255 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 608ffa4b5..4ce432657 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -73,6 +73,14 @@ std::vector MuxGraph::levels() const { return graph_levels; } +std::vector MuxGraph::node_levels() const { + std::vector graph_levels; + for (size_t lvl = 0; lvl < num_node_levels(); ++lvl) { + graph_levels.push_back(lvl); + } + return graph_levels; +} + /************************************************** * Public Accessors: Data query *************************************************/ @@ -261,6 +269,43 @@ std::vector MuxGraph::branch_sizes() const { return branch; } +/* Find the sizes of each branch of a MUX at a given level */ +std::vector MuxGraph::branch_sizes(const size_t& level) const { + std::vector branch; + /* Visit each internal nodes/output nodes and find the the number of incoming edges */ + for (auto node : node_ids_ ) { + /* Bypass input nodes */ + if ( (MUX_OUTPUT_NODE != node_types_[node]) + && (MUX_INTERNAL_NODE != node_types_[node]) ) { + continue; + } + /* Bypass nodes that is not at the level */ + if ( level != node_levels_[node]) { + continue; + } + + size_t branch_size = node_in_edges_[node].size(); + + /* make sure the branch size is valid */ + VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size)); + + /* Nodes with the same number of incoming edges, indicate the same size of branch circuit */ + std::vector::iterator it; + it = std::find(branch.begin(), branch.end(), branch_size); + /* if already exists a branch with the same size, skip updating the vector */ + if (it != branch.end()) { + continue; + } + branch.push_back(branch_size); + } + + /* Sort the branch by size */ + std::sort(branch.begin(), branch.end()); + + return branch; +} + + /* Build a subgraph from the given node * The strategy is very simple, we just * extract a 1-level graph from here diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index ddb80e6f4..ed1f4773d 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -62,7 +62,10 @@ class MuxGraph { std::vector non_input_nodes() const; edge_range edges() const; mem_range memories() const; + /* Find the number of levels in terms of the multiplexer */ std::vector levels() const; + /* Find the actual number of levels in the graph */ + std::vector node_levels() const; public: /* Public accessors: Data query */ /* Find the number of inputs in the MUX graph */ size_t num_inputs() const; @@ -95,6 +98,8 @@ class MuxGraph { bool is_edge_use_inv_mem(const MuxEdgeId& edge) const; /* Find the sizes of each branch of a MUX */ std::vector branch_sizes() const; + /* Find the sizes of each branch of a MUX at a given level */ + std::vector branch_sizes(const size_t& level) const; /* Generate MUX graphs for its branches */ MuxGraph subgraph(const MuxNodeId& node) const; std::vector build_mux_branch_graphs() const; diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 53e71f1f8..6446cfe8e 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -386,3 +386,109 @@ size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, return num_config_bits; } + +/************************************************** + * Find the number of shared configuration bits for a CMOS multiplexer + * Currently, all the supported CMOS multiplexers + * do NOT require any shared configuration bits + *************************************************/ +static +size_t find_cmos_mux_num_shared_config_bits(const e_sram_orgz& sram_orgz_type) { + size_t num_shared_config_bits = 0; + + switch (sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + num_shared_config_bits = 0; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return num_shared_config_bits; +} + +/************************************************** + * Find the number of shared configuration bits for a ReRAM multiplexer + *************************************************/ +static +size_t find_rram_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type) { + size_t num_shared_config_bits = 0; + switch (sram_orgz_type) { + case SPICE_SRAM_MEMORY_BANK: { + /* In memory bank, the number of shared configuration bits is + * the sum of largest branch size at each level + */ + for (auto lvl : mux_graph.node_levels()) { + /* Find the maximum branch size: + * Note that branch_sizes() returns a sorted vector + * The last one is the maximum + */ + num_shared_config_bits += mux_graph.branch_sizes(lvl).back(); + } + break; + } + case SPICE_SRAM_SCAN_CHAIN: + case SPICE_SRAM_STANDALONE: + /* Currently we DO NOT SUPPORT THESE, given an invalid number */ + num_shared_config_bits = size_t(-1); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + if (true == circuit_lib.mux_use_local_encoder(mux_model)) { + /* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs + * The number of states of a local decoder only depends on how many + * memory bits that the multiplexer will have + * This may NOT be correct!!! + * If local encoders are introduced, zero shared configuration bits are required + */ + return 0; + } + + return num_shared_config_bits; +} + +/************************************************** + * Find the number of shared configuration bits for + * a routing multiplexer + * Two cases are considered here. + * They are placed in different branches (sub-functions) + * in order to be easy in extending to new technology! + * + * Note: currently, shared configuration bits are demanded + * by ReRAM-based multiplexers only + *************************************************/ +size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type) { + size_t num_shared_config_bits = size_t(-1); + + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + num_shared_config_bits = find_cmos_mux_num_shared_config_bits(sram_orgz_type); + break; + case SPICE_MODEL_DESIGN_RRAM: + num_shared_config_bits = find_rram_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + exit(1); + } + + return num_shared_config_bits; +} diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h index 9fa1f12ca..04d4ad7ff 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.h @@ -46,4 +46,9 @@ size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, const MuxGraph& mux_graph, const e_sram_orgz& sram_orgz_type); +size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph, + const e_sram_orgz& sram_orgz_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index 96dff6375..9cd735aeb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -256,3 +256,82 @@ size_t find_switch_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, return num_conf_bits; } +/********************************************************************* + * Find the number of shared configuration bits of a Connection Block + ********************************************************************/ +size_t find_connection_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb, + const t_rr_type& cb_type) { + size_t num_shared_conf_bits = 0; + + std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + /* Find the size of routing multiplexers driving this IPIN node */ + int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; + /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ + if (2 > mux_size) { + continue; + } + + /* Get the circuit model id of the routing multiplexer */ + size_t switch_index = rr_gsb.get_ipin_node(cb_ipin_side, inode)->drive_switches[DEFAULT_SWITCH_ID]; + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + num_shared_conf_bits += find_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); + } + } + + return num_shared_conf_bits; +} + +/********************************************************************* + * Find the number of shared configuration bits of a Switch Block + ********************************************************************/ +size_t find_switch_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb) { + size_t num_shared_conf_bits = 0; + + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + /* Check if this node is just a passing wire */ + if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { + continue; + } + /* Check if this node has more than 2 drivers */ + if (2 > rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { + continue; + } + /* Get the circuit model id of the routing multiplexer */ + size_t switch_index = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->drive_switches[DEFAULT_SWITCH_ID]; + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes; + /* Get the multiplexing graph from the Mux Library */ + MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + num_shared_conf_bits += find_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); + } + } + + return num_shared_conf_bits; +} + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h index 78bb981d5..711517a0c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h @@ -38,4 +38,17 @@ size_t find_switch_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, const std::vector& rr_switches, const RRGSB& rr_gsb); +size_t find_connection_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb, + const t_rr_type& cb_type); + +size_t find_switch_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + const RRGSB& rr_gsb); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 57eb32e21..9cebf20ac 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2780,7 +2780,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage /* Count the number of configuration bits to be consumed by this Switch block */ int num_conf_bits = find_switch_block_num_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_sb); /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_switch_box_reserved_conf_bits(cur_sram_orgz_info, rr_sb); + int num_reserved_conf_bits = find_switch_block_num_shared_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_sb); /* Estimate the sram_verilog_model->cnt */ int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ @@ -4566,7 +4566,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma /* Count the number of configuration bits to be consumed by this Switch block */ int num_conf_bits = (int)find_connection_block_num_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_gsb, cb_type); /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = count_verilog_connection_box_reserved_conf_bits(cur_sram_orgz_info, rr_gsb, cb_type); + int num_reserved_conf_bits = (int)find_connection_block_num_shared_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_gsb, cb_type); /* Estimate the sram_verilog_model->cnt */ int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); /* Record index */ From 3ca6f08aa4cc76f7a26efba4ccfd2a10c5c6f54c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 6 Oct 2019 19:27:55 -0600 Subject: [PATCH 268/482] start refactoring physical block Verilog generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 35 ++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 10 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 10 +- .../verilog/verilog_compact_netlist.c | 186 +++++++++++++++--- .../verilog/verilog_compact_netlist.h | 22 ++- 5 files changed, 225 insertions(+), 38 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 597329292..3c41111e3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -671,3 +671,38 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string()); return generate_local_sram_port_name(prefix, mux_instance_id, port_type); } + +/********************************************************************* + * Generate the netlist name of a physical block + **********************************************************************/ +std::string generate_physical_block_netlist_name(const std::string& block_name, + const bool& is_block_io, + const e_side& io_side, + const std::string& postfix) { + /* Add the name of physical block */ + std::string module_name(block_name); + + if (true == is_block_io) { + Side side_manager(io_side); + module_name += std::string("_"); + module_name += std::string(side_manager.to_string()); + } + + module_name += postfix; + + return module_name; +} + +/********************************************************************* + * Generate the module name of a physical block + **********************************************************************/ +std::string generate_physical_block_module_name(const std::string& prefix, + const std::string& block_name, + const bool& is_block_io, + const e_side& io_side) { + std::string module_name(prefix); + + module_name += generate_physical_block_netlist_name(block_name, is_block_io, io_side, std::string()); + + return module_name; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index bd7ced7b8..8673de395 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -130,4 +130,14 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, const size_t& mux_instance_id, const e_spice_model_port_type& port_type); +std::string generate_physical_block_netlist_name(const std::string& block_name, + const bool& is_block_io, + const e_side& io_side, + const std::string& postfix); + +std::string generate_physical_block_module_name(const std::string& prefix, + const std::string& block_name, + const bool& is_block_io, + const e_side& io_side); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index f35a024aa..025199f20 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -280,7 +280,8 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); /* Dump routing resources: switch blocks, connection blocks and channel tracks */ - print_verilog_routing_resources(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch, + print_verilog_routing_resources(module_manager, mux_lib, sram_verilog_orgz_info, + src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, vpr_setup.FPGA_SPICE_Opts); @@ -289,9 +290,10 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, * 1. a compact output * 2. a full-size output */ - dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, - lb_dir_path, &Arch, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + print_compact_verilog_logic_blocks(module_manager, mux_lib, + sram_verilog_orgz_info, src_dir_path, + lb_dir_path, Arch, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Generate the Verilog module of the configuration peripheral protocol * which loads bitstream to FPGA fabric diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index c38742ddc..191941080 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -12,6 +12,7 @@ #include /* Include vpr structs*/ +#include "vtr_assert.h" #include "util.h" #include "physical_types.h" #include "vpr_types.h" @@ -29,6 +30,7 @@ #include "fpga_x2p_bitstream_utils.h" #include "spice_mux.h" #include "fpga_x2p_globals.h" +#include "fpga_x2p_naming.h" /* Include Synthesizable Verilog headers */ #include "verilog_global.h" @@ -36,6 +38,7 @@ #include "verilog_primitives.h" #include "verilog_pbtypes.h" #include "verilog_routing.h" +#include "verilog_writer_utils.h" #include "verilog_top_netlist_utils.h" #include "verilog_compact_netlist.h" @@ -274,6 +277,113 @@ void compact_verilog_update_grid_spice_model_and_sram_orgz_info(t_sram_orgz_info return; } +/***************************************************************************** + * This function will create a Verilog file and print out a Verilog netlist + * for a type of physical block + * + * For IO blocks: + * The param 'border_side' is required, which is specify which side of fabric + * the I/O block locates at. + *****************************************************************************/ +void print_verilog_physical_block(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + t_type_ptr phy_block_type, + const e_side& border_side, + const bool& use_explicit_mapping) { + /* Check code: if this is an IO block, the border side MUST be valid */ + if (IO_TYPE == phy_block_type) { + VTR_ASSERT(NUM_SIDES != border_side); + } + + /* Give a name to the Verilog netlist */ + /* Create the file name for Verilog */ + std::string verilog_fname(subckt_dir + + generate_physical_block_netlist_name(std::string(phy_block_type->name), + IO_TYPE == phy_block_type, + border_side, + std::string(verilog_netlist_file_postfix)) + ); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + + /* Echo status */ + if (IO_TYPE == phy_block_type) { + Side side_manager(border_side); + vpr_printf(TIO_MESSAGE_INFO, + "Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n", + verilog_fname.c_str(), phy_block_type->name, + side_manager.c_str()); + } else { + vpr_printf(TIO_MESSAGE_INFO, + "Writing FPGA Verilog Netlist (%s) for logic block %s...\n", + verilog_fname.c_str(), phy_block_type->name); + } + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]")); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */ + for (int iz = 0; iz < phy_block_type->capacity; ++iz) { + /* ONLY output one Verilog module (which is unique), others are the same */ + if (0 < iz) { + continue; + } + /* TODO: use a Depth-First Search Algorithm to print the sub-modules + * Note: DFS is the right way. Do NOT use BFS. + * DFS can guarantee that all the sub-modules can be registered properly + * to its parent in module manager + */ + print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); + print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); + } + + /* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */ + std::string module_name = generate_physical_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); + ModuleId module_id = module_manager.add_module(module_name); + + /* TODO: Add ports to the module */ + + + /* TODO: Print the module definition for the top-level Verilog module of physical block */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish printing ports */ + + /* Print an empty line a splitter */ + fp << std::endl; + + /* TODO: instanciate all the sub modules */ + for (int iz = 0; iz < phy_block_type->capacity; ++iz) { + } + + /* Put an end to the top-level Verilog module of physical block */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* + grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ +} + /* Create a Verilog file and dump a module consisting of a I/O block, * The pins appear in the port list will depend on the selected border side */ @@ -511,63 +621,81 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf * 2. Only one module for each CLB (FILL_TYPE) * 3. Only one module for each heterogeneous block */ -void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* subckt_dir, - t_arch* arch, - bool is_explicit_mapping) { - int itype, iside, num_sides; - int* stamped_spice_model_cnt = NULL; - t_sram_orgz_info* stamped_sram_orgz_info = NULL; - +void print_compact_verilog_logic_blocks(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + t_arch& arch, + const bool& is_explicit_mapping) { /* Create a snapshot on spice_model counter */ - stamped_spice_model_cnt = snapshot_spice_model_counter(arch->spice->num_spice_model, - arch->spice->spice_models); + int* stamped_spice_model_cnt = snapshot_spice_model_counter(arch.spice->num_spice_model, + arch.spice->spice_models); /* Create a snapshot on sram_orgz_info */ - stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); + t_sram_orgz_info* stamped_sram_orgz_info = snapshot_sram_orgz_info(cur_sram_orgz_info); /* Enumerate the types, dump one Verilog module for each */ - for (itype = 0; itype < num_types; itype++) { + for (int itype = 0; itype < num_types; itype++) { if (EMPTY_TYPE == &type_descriptors[itype]) { /* Bypass empty type or NULL */ continue; } else if (IO_TYPE == &type_descriptors[itype]) { - num_sides = 4; - /* Special for I/O block, generate one module for each border side */ - for (iside = 0; iside < num_sides; iside++) { + /* Special for I/O block, generate one module for each border side */ + for (int iside = 0; iside < NUM_SIDES; iside++) { + Side side_manager(iside); dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, &type_descriptors[itype], iside, is_explicit_mapping); + + print_verilog_physical_block(module_manager, mux_lib, arch.spice->circuit_lib, + cur_sram_orgz_info, + std::string(verilog_dir), std::string(subckt_dir), + &type_descriptors[itype], + side_manager.get_side(), + is_explicit_mapping); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { - /* For CLB */ - dump_compact_verilog_one_physical_block(cur_sram_orgz_info, - verilog_dir, subckt_dir, - &type_descriptors[itype], -1, - is_explicit_mapping); - continue; - } else { - /* For heterogenenous blocks */ + /* For CLB */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, &type_descriptors[itype], -1, is_explicit_mapping); + print_verilog_physical_block(module_manager, mux_lib, arch.spice->circuit_lib, + cur_sram_orgz_info, + std::string(verilog_dir), std::string(subckt_dir), + &type_descriptors[itype], + NUM_SIDES, + is_explicit_mapping); + continue; + } else { + /* For heterogenenous blocks */ + dump_compact_verilog_one_physical_block(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &type_descriptors[itype], -1, + is_explicit_mapping); + + print_verilog_physical_block(module_manager, mux_lib, arch.spice->circuit_lib, + cur_sram_orgz_info, + std::string(verilog_dir), std::string(subckt_dir), + &type_descriptors[itype], + NUM_SIDES, + is_explicit_mapping); } } /* Output a header file for all the logic blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating header file for grid submodules...\n"); + vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid submodules...\n"); dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head, subckt_dir, logic_block_verilog_file_name); /* Recover spice_model counter */ - set_spice_model_counter(arch->spice->num_spice_model, - arch->spice->spice_models, + set_spice_model_counter(arch.spice->num_spice_model, + arch.spice->spice_models, stamped_spice_model_cnt); /* Restore sram_orgz_info to the base */ @@ -577,8 +705,8 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, * THIS FUNCTION MUST GO AFTER OUTPUTING PHYSICAL LOGIC BLOCKS!!! */ compact_verilog_update_grid_spice_model_and_sram_orgz_info(cur_sram_orgz_info, - arch->spice->num_spice_model, - arch->spice->spice_models); + arch.spice->num_spice_model, + arch.spice->spice_models); /* Free */ free_sram_orgz_info(stamped_sram_orgz_info, stamped_sram_orgz_info->type); my_free (stamped_spice_model_cnt); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 5086722d2..2cf7931e7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -1,6 +1,16 @@ #ifndef VERILOG_COMPACT_NETLIST_H #define VERILOG_COMPACT_NETLIST_H +void print_verilog_physical_block(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir_path, + const std::string& subckt_dir_path, + t_type_ptr phy_block_type, + const e_side& border_side, + const bool& use_explicit_mapping); + void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir_path, char* subckt_dir_path, @@ -8,11 +18,13 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf int border_side, bool is_explicit_mapping); -void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, - char* verilog_dir, - char* subckt_dir, - t_arch* arch, - bool is_explicit_mapping); +void print_compact_verilog_logic_blocks(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + t_arch& arch, + const bool& is_explicit_mapping); void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, From 997bfdbb95bb8e1311613060ab73e5f3fc257944 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2019 16:03:15 -0600 Subject: [PATCH 269/482] move the refactored function for physical block Verilog generation to a new source file --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 9 +- .../verilog/verilog_compact_netlist.c | 134 +----------- .../verilog/verilog_compact_netlist.h | 13 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 199 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.h | 21 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 4 +- 7 files changed, 234 insertions(+), 150 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 025199f20..01c0b88a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -43,6 +43,7 @@ #include "verilog_decoder.h" #include "verilog_decoders.h" #include "verilog_pbtypes.h" +#include "verilog_grid.h" #include "verilog_routing.h" #include "verilog_compact_netlist.h" #include "verilog_top_testbench.h" @@ -290,11 +291,15 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, * 1. a compact output * 2. a full-size output */ - print_compact_verilog_logic_blocks(module_manager, mux_lib, - sram_verilog_orgz_info, src_dir_path, + print_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + print_verilog_grids(module_manager, Arch.spice->circuit_lib, mux_lib, + sram_verilog_orgz_info, + std::string(src_dir_path), std::string(lb_dir_path), + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + /* Generate the Verilog module of the configuration peripheral protocol * which loads bitstream to FPGA fabric * TODO: generate the BL/WL decoders!!!! diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 191941080..56c27c307 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -37,6 +37,7 @@ #include "verilog_utils.h" #include "verilog_primitives.h" #include "verilog_pbtypes.h" +#include "verilog_grid.h" #include "verilog_routing.h" #include "verilog_writer_utils.h" #include "verilog_top_netlist_utils.h" @@ -277,113 +278,6 @@ void compact_verilog_update_grid_spice_model_and_sram_orgz_info(t_sram_orgz_info return; } -/***************************************************************************** - * This function will create a Verilog file and print out a Verilog netlist - * for a type of physical block - * - * For IO blocks: - * The param 'border_side' is required, which is specify which side of fabric - * the I/O block locates at. - *****************************************************************************/ -void print_verilog_physical_block(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& subckt_dir, - t_type_ptr phy_block_type, - const e_side& border_side, - const bool& use_explicit_mapping) { - /* Check code: if this is an IO block, the border side MUST be valid */ - if (IO_TYPE == phy_block_type) { - VTR_ASSERT(NUM_SIDES != border_side); - } - - /* Give a name to the Verilog netlist */ - /* Create the file name for Verilog */ - std::string verilog_fname(subckt_dir - + generate_physical_block_netlist_name(std::string(phy_block_type->name), - IO_TYPE == phy_block_type, - border_side, - std::string(verilog_netlist_file_postfix)) - ); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - - /* Echo status */ - if (IO_TYPE == phy_block_type) { - Side side_manager(border_side); - vpr_printf(TIO_MESSAGE_INFO, - "Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n", - verilog_fname.c_str(), phy_block_type->name, - side_manager.c_str()); - } else { - vpr_printf(TIO_MESSAGE_INFO, - "Writing FPGA Verilog Netlist (%s) for logic block %s...\n", - verilog_fname.c_str(), phy_block_type->name); - } - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]")); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */ - for (int iz = 0; iz < phy_block_type->capacity; ++iz) { - /* ONLY output one Verilog module (which is unique), others are the same */ - if (0 < iz) { - continue; - } - /* TODO: use a Depth-First Search Algorithm to print the sub-modules - * Note: DFS is the right way. Do NOT use BFS. - * DFS can guarantee that all the sub-modules can be registered properly - * to its parent in module manager - */ - print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - } - - /* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string module_name = generate_physical_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); - ModuleId module_id = module_manager.add_module(module_name); - - /* TODO: Add ports to the module */ - - - /* TODO: Print the module definition for the top-level Verilog module of physical block */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish printing ports */ - - /* Print an empty line a splitter */ - fp << std::endl; - - /* TODO: instanciate all the sub modules */ - for (int iz = 0; iz < phy_block_type->capacity; ++iz) { - } - - /* Put an end to the top-level Verilog module of physical block */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the linked list */ - /* - grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ -} - /* Create a Verilog file and dump a module consisting of a I/O block, * The pins appear in the port list will depend on the selected border side */ @@ -621,9 +515,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf * 2. Only one module for each CLB (FILL_TYPE) * 3. Only one module for each heterogeneous block */ -void print_compact_verilog_logic_blocks(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, +void print_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_arch& arch, @@ -647,13 +539,6 @@ void print_compact_verilog_logic_blocks(ModuleManager& module_manager, verilog_dir, subckt_dir, &type_descriptors[itype], iside, is_explicit_mapping); - - print_verilog_physical_block(module_manager, mux_lib, arch.spice->circuit_lib, - cur_sram_orgz_info, - std::string(verilog_dir), std::string(subckt_dir), - &type_descriptors[itype], - side_manager.get_side(), - is_explicit_mapping); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { @@ -662,13 +547,6 @@ void print_compact_verilog_logic_blocks(ModuleManager& module_manager, verilog_dir, subckt_dir, &type_descriptors[itype], -1, is_explicit_mapping); - - print_verilog_physical_block(module_manager, mux_lib, arch.spice->circuit_lib, - cur_sram_orgz_info, - std::string(verilog_dir), std::string(subckt_dir), - &type_descriptors[itype], - NUM_SIDES, - is_explicit_mapping); continue; } else { /* For heterogenenous blocks */ @@ -676,13 +554,6 @@ void print_compact_verilog_logic_blocks(ModuleManager& module_manager, verilog_dir, subckt_dir, &type_descriptors[itype], -1, is_explicit_mapping); - - print_verilog_physical_block(module_manager, mux_lib, arch.spice->circuit_lib, - cur_sram_orgz_info, - std::string(verilog_dir), std::string(subckt_dir), - &type_descriptors[itype], - NUM_SIDES, - is_explicit_mapping); } } @@ -692,7 +563,6 @@ void print_compact_verilog_logic_blocks(ModuleManager& module_manager, subckt_dir, logic_block_verilog_file_name); - /* Recover spice_model counter */ set_spice_model_counter(arch.spice->num_spice_model, arch.spice->spice_models, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 2cf7931e7..3b5c71862 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -1,15 +1,6 @@ #ifndef VERILOG_COMPACT_NETLIST_H #define VERILOG_COMPACT_NETLIST_H -void print_verilog_physical_block(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir_path, - const std::string& subckt_dir_path, - t_type_ptr phy_block_type, - const e_side& border_side, - const bool& use_explicit_mapping); void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir_path, @@ -18,9 +9,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf int border_side, bool is_explicit_mapping); -void print_compact_verilog_logic_blocks(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, +void print_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_arch& arch, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp new file mode 100644 index 000000000..48d77f753 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -0,0 +1,199 @@ +/******************************************************************** + * This file includes functions to print Verilog modules for a Grid + * (CLBs, I/Os, heterogeneous blocks etc.) + *******************************************************************/ +/* System header files */ +#include +#include + +/* Header files from external libs */ +#include "util.h" +#include "vtr_assert.h" + +/* Header files for VPR */ +#include "vpr_types.h" +#include "globals.h" + +/* Header files for FPGA X2P tool suite */ +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* Header files for Verilog generator */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "verilog_writer_utils.h" +#include "verilog_grid.h" + +/***************************************************************************** + * This function will create a Verilog file and print out a Verilog netlist + * for a type of physical block + * + * For IO blocks: + * The param 'border_side' is required, which is specify which side of fabric + * the I/O block locates at. + *****************************************************************************/ +static +void print_verilog_grid(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + t_type_ptr phy_block_type, + const e_side& border_side, + const bool& use_explicit_mapping) { + /* Check code: if this is an IO block, the border side MUST be valid */ + if (IO_TYPE == phy_block_type) { + VTR_ASSERT(NUM_SIDES != border_side); + } + + /* Give a name to the Verilog netlist */ + /* Create the file name for Verilog */ + std::string verilog_fname(subckt_dir + + generate_physical_block_netlist_name(std::string(phy_block_type->name), + IO_TYPE == phy_block_type, + border_side, + std::string(verilog_netlist_file_postfix)) + ); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Echo status */ + if (IO_TYPE == phy_block_type) { + Side side_manager(border_side); + vpr_printf(TIO_MESSAGE_INFO, + "Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n", + verilog_fname.c_str(), phy_block_type->name, + side_manager.c_str()); + } else { + vpr_printf(TIO_MESSAGE_INFO, + "Writing FPGA Verilog Netlist (%s) for logic block %s...\n", + verilog_fname.c_str(), phy_block_type->name); + } + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]")); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */ + for (int iz = 0; iz < phy_block_type->capacity; ++iz) { + /* ONLY output one Verilog module (which is unique), others are the same */ + if (0 < iz) { + continue; + } + /* TODO: use a Depth-First Search Algorithm to print the sub-modules + * Note: DFS is the right way. Do NOT use BFS. + * DFS can guarantee that all the sub-modules can be registered properly + * to its parent in module manager + */ + print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); + + /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ + /* + dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix, + phy_block_type->pb_graph_head, iz, + is_explicit_mapping); + */ + print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); + } + + /* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */ + std::string module_name = generate_physical_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); + ModuleId module_id = module_manager.add_module(module_name); + + /* TODO: Add ports to the module */ + + + /* TODO: Print the module definition for the top-level Verilog module of physical block */ + print_verilog_module_declaration(fp, module_manager, module_id); + /* Finish printing ports */ + + /* Print an empty line a splitter */ + fp << std::endl; + + /* TODO: instanciate all the sub modules */ + for (int iz = 0; iz < phy_block_type->capacity; ++iz) { + } + + /* Put an end to the top-level Verilog module of physical block */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* + grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ +} + +/***************************************************************************** + * Create logic block modules in a compact way: + * 1. Only one module for each I/O on each border side (IO_TYPE) + * 2. Only one module for each CLB (FILL_TYPE) + * 3. Only one module for each heterogeneous block + ****************************************************************************/ +void print_verilog_grids(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + const bool& is_explicit_mapping) { + /* Enumerate the types, dump one Verilog module for each */ + for (int itype = 0; itype < num_types; itype++) { + if (EMPTY_TYPE == &type_descriptors[itype]) { + /* Bypass empty type or NULL */ + continue; + } else if (IO_TYPE == &type_descriptors[itype]) { + /* Special for I/O block, generate one module for each border side */ + for (int iside = 0; iside < NUM_SIDES; iside++) { + Side side_manager(iside); + print_verilog_grid(module_manager, mux_lib, circuit_lib, + cur_sram_orgz_info, + verilog_dir, subckt_dir, + &type_descriptors[itype], + side_manager.get_side(), + is_explicit_mapping); + } + continue; + } else if (FILL_TYPE == &type_descriptors[itype]) { + /* For CLB */ + print_verilog_grid(module_manager, mux_lib, circuit_lib, + cur_sram_orgz_info, + verilog_dir, subckt_dir, + &type_descriptors[itype], + NUM_SIDES, + is_explicit_mapping); + continue; + } else { + /* For heterogenenous blocks */ + print_verilog_grid(module_manager, mux_lib, circuit_lib, + cur_sram_orgz_info, + verilog_dir, subckt_dir, + &type_descriptors[itype], + NUM_SIDES, + is_explicit_mapping); + } + } + + /* Output a header file for all the logic blocks */ + vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n"); + std::string grid_verilog_fname(logic_block_verilog_file_name); + /* TODO: remove .bak when it is ready */ + grid_verilog_fname += ".bak"; + dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head, + subckt_dir.c_str(), + grid_verilog_fname.c_str()); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h new file mode 100644 index 000000000..b99ffd430 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h @@ -0,0 +1,21 @@ +/******************************************************************** + * Header file for verilog_grid.cpp + *******************************************************************/ +#ifndef VERILOG_GRID_H +#define VERILOG_GRID_H + +/* Only include headers related to the data structures used in the following function declaration */ +#include +#include "vpr_types.h" +#include "module_manager.h" +#include "mux_library.h" + +void print_verilog_grids(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& verilog_dir, + const std::string& subckt_dir, + const bool& is_explicit_mapping); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index f6a159f22..0bdad0ee8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -433,8 +433,8 @@ FILE* verilog_create_one_subckt_file(char* subckt_dir, * that can be easily imported in a top-level netlist */ void dump_verilog_subckt_header_file(t_llist* subckt_llist_head, - char* subckt_dir, - char* header_file_name) { + const char* subckt_dir, + const char* header_file_name) { FILE* fp = NULL; char* verilog_fname = NULL; t_llist* temp = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index ab5a98d2f..1fac4fff5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -43,8 +43,8 @@ FILE* verilog_create_one_subckt_file(char* subckt_dir, char** verilog_fname); void dump_verilog_subckt_header_file(t_llist* subckt_llist_head, - char* subckt_dir, - char* header_file_name); + const char* subckt_dir, + const char* header_file_name); char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type); From 86c9af872e634df962b2652dd012f0bee37b9bb0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2019 17:39:00 -0600 Subject: [PATCH 270/482] refactoring physical block Verilog generation --- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 151 +++++++++++++++++- 1 file changed, 145 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 48d77f753..5b103a726 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -16,7 +16,9 @@ /* Header files for FPGA X2P tool suite */ #include "fpga_x2p_naming.h" +#include "fpga_x2p_types.h" #include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" /* Header files for Verilog generator */ #include "verilog_global.h" @@ -24,6 +26,143 @@ #include "verilog_writer_utils.h" #include "verilog_grid.h" +/******************************************************************** + * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) + * This function will traverse the graph of complex logic block (t_pb_graph_node) + * in a recursive way, using a Depth First Search (DFS) algorithm. + * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph + * will be printed out first, while the top-level will be printed out in the last + * + * Note: this function will print a unique Verilog module for each type of + * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly + * hierarchical Verilog organization as well as simplify the Verilog file sizes. + * + * Note: DFS is the right way. Do NOT use BFS. + * DFS can guarantee that all the sub-modules can be registered properly + * to its parent in module manager + *******************************************************************/ +static +void print_verilog_physical_blocks_rec(std::fstream& fp, + ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_sram_orgz_info* cur_sram_orgz_info, + t_pb_graph_node* physical_pb_graph_node, + const bool& use_explicit_mapping) { + /* Check the file handler*/ + check_file_handler(fp); + + /* Check cur_pb_graph_node*/ + if (NULL == physical_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get the pb_type definition related to the node */ + t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + /* Find the mode that physical implementation of a pb_type */ + int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type)); + + /* For non-leaf node in the pb_type graph: + * Recursively Depth-First Generate all the child pb_type at the level + */ + if (FALSE == is_primitive_pb_type(physical_pb_type)) { + for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { + /* Go recursive to visit the children */ + print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, + cur_sram_orgz_info, + &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), + use_explicit_mapping); + } + } + + /* For leaf node, a primitive Verilog module will be generated */ + if (TRUE == is_primitive_pb_type(physical_pb_type)) { + /* Branch on the type of this physical pb_type, different Verilog modules are generated */ + switch (physical_pb_type->class_type) { + case LUT_CLASS: + /* TODO: refactor this function + dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, + cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); + */ + break; + case LATCH_CLASS: + VTR_ASSERT(0 == physical_pb_type->num_modes); + /* TODO: refactor this function + dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, + cur_pb_graph_node, pb_type_index, + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); + */ + break; + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* TODO: refactor this function + dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, + cur_pb_graph_node , pb_type_index, + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, physical_pb_type->name); + exit(1); + } + /* Finish for primitive node, return */ + return; + } + + /* TODO: Generate the name of the Verilog module for this pb_type */ + + /* TODO: Register the Verilog module in module manager */ + + /* TODO: Add ports to the Verilog module */ + + /* TODO: Count I/O (INOUT) ports from the sub-modules under this Verilog module */ + /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module */ + /* TODO: Count SRAM ports from the sub-modules under this Verilog module */ + /* TODO: Count formal verification ports from the sub-modules under this Verilog module */ + + /* TODO: Print Verilog module declaration */ + /* Comment lines */ + print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); + + /* TODO: Print local wires (bus wires for memory configuration) */ + /* + dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, + stamped_sram_cnt, + stamped_sram_cnt + num_conf_bits - 1); + */ + + /* TODO: Instanciate all the child Verilog modules */ + for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ipb++) { + /* Each child may exist multiple times in the hierarchy*/ + for (int jpb = 0; jpb < physical_pb_type->modes[physical_mode_index].pb_type_children[ipb].num_pb; jpb++) { + /* we should make sure this placement index == child_pb_type[jpb] */ + VTR_ASSERT(jpb == physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb].placement_index); + } + } + /* TODO: Print programmable/non-programmable interconnections inside the Verilog module */ + /* + dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, + cur_pb_graph_node, mode_index, + is_explicit_mapping); + */ + + /* Print an end to the Verilog module */ + print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); + + return; +} + + /***************************************************************************** * This function will create a Verilog file and print out a Verilog netlist * for a type of physical block @@ -96,11 +235,11 @@ void print_verilog_grid(ModuleManager& module_manager, print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ - /* - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix, - phy_block_type->pb_graph_head, iz, - is_explicit_mapping); - */ + print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, + cur_sram_orgz_info, + phy_block_type->pb_graph_head, + use_explicit_mapping); + print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); } @@ -132,7 +271,7 @@ void print_verilog_grid(ModuleManager& module_manager, fp.close(); /* Add fname to the linked list */ - /* + /* TODO: add it when it is ready grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str()); */ } From 173b886314f418dea503428ea029dbf4a97900a3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 7 Oct 2019 21:09:54 -0600 Subject: [PATCH 271/482] add module name generation for pb_types --- .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp | 19 +- .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.h | 4 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 76 ++++++-- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 17 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 163 ++++++++++++++---- .../SRC/fpga_x2p/verilog/verilog_routing.c | 6 +- 6 files changed, 212 insertions(+), 73 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp index f95f99a88..265330f40 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp @@ -39,9 +39,7 @@ * **********************************************************************/ static -std::map generate_cmos_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const BasicPort& config_bus, +std::map generate_cmos_mem_module_port2port_map(const BasicPort& config_bus, const std::vector& mem_output_bus_ports, const e_sram_orgz& sram_orgz_type) { std::map port2port_name_map; @@ -100,9 +98,7 @@ std::map generate_cmos_mem_module_port2port_map(const Mo * Mem_out Mem_outb **********************************************************************/ static -std::map generate_rram_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const BasicPort& config_bus, +std::map generate_rram_mem_module_port2port_map(const BasicPort& config_bus, const std::vector& mem_output_bus_ports, const e_sram_orgz& sram_orgz_type) { std::map port2port_name_map; @@ -152,9 +148,7 @@ std::map generate_rram_mem_module_port2port_map(const Mo * configuration styles of FPGA fabric. * Here we will branch on the design technology **********************************************************************/ -std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const BasicPort& config_bus, +std::map generate_mem_module_port2port_map(const BasicPort& config_bus, const std::vector& mem_output_bus_ports, const e_spice_model_design_tech& mem_design_tech, const e_sram_orgz& sram_orgz_type) { @@ -162,10 +156,10 @@ std::map generate_mem_module_port2port_map(const ModuleM switch (mem_design_tech) { case SPICE_MODEL_DESIGN_CMOS: - port2port_name_map = generate_cmos_mem_module_port2port_map(module_manager, mem_module, config_bus, mem_output_bus_ports, sram_orgz_type); + port2port_name_map = generate_cmos_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type); break; case SPICE_MODEL_DESIGN_RRAM: - port2port_name_map = generate_rram_mem_module_port2port_map(module_manager, mem_module, config_bus, mem_output_bus_ports, sram_orgz_type); + port2port_name_map = generate_rram_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type); break; default: vpr_printf(TIO_MESSAGE_ERROR, @@ -215,7 +209,6 @@ void update_cmos_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, **********************************************************************/ static void update_rram_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, - const size_t& num_config_bits, BasicPort& config_bus) { switch (sram_orgz_type) { case SPICE_SRAM_STANDALONE: @@ -261,7 +254,7 @@ void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, update_cmos_mem_module_config_bus(sram_orgz_type, num_config_bits, config_bus); break; case SPICE_MODEL_DESIGN_RRAM: - update_rram_mem_module_config_bus(sram_orgz_type, num_config_bits, config_bus); + update_rram_mem_module_config_bus(sram_orgz_type, config_bus); break; default: vpr_printf(TIO_MESSAGE_ERROR, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h index 831aca5a8..fef569c5a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h @@ -10,9 +10,7 @@ #include "spice_types.h" #include "module_manager.h" -std::map generate_mem_module_port2port_map(const ModuleManager& module_manager, - const ModuleId& mem_module, - const BasicPort& config_bus, +std::map generate_mem_module_port2port_map(const BasicPort& config_bus, const std::vector& mem_output_bus_ports, const e_spice_model_design_tech& mem_design_tech, const e_sram_orgz& sram_orgz_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 3c41111e3..fa87405d9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -673,12 +673,12 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, } /********************************************************************* - * Generate the netlist name of a physical block + * Generate the netlist name of a grid block **********************************************************************/ -std::string generate_physical_block_netlist_name(const std::string& block_name, - const bool& is_block_io, - const e_side& io_side, - const std::string& postfix) { +std::string generate_grid_block_netlist_name(const std::string& block_name, + const bool& is_block_io, + const e_side& io_side, + const std::string& postfix) { /* Add the name of physical block */ std::string module_name(block_name); @@ -694,15 +694,69 @@ std::string generate_physical_block_netlist_name(const std::string& block_name, } /********************************************************************* - * Generate the module name of a physical block + * Generate the module name of a grid block **********************************************************************/ -std::string generate_physical_block_module_name(const std::string& prefix, - const std::string& block_name, - const bool& is_block_io, - const e_side& io_side) { +std::string generate_grid_block_module_name(const std::string& prefix, + const std::string& block_name, + const bool& is_block_io, + const e_side& io_side) { std::string module_name(prefix); - module_name += generate_physical_block_netlist_name(block_name, is_block_io, io_side, std::string()); + module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string()); + + return module_name; +} + +/********************************************************************* + * Generate the module name of a physical block + * To ensure a unique name for each physical block inside the graph of complex blocks + * (pb_graph_nodes), this function trace backward to the top-level node + * in the graph and add the name of these parents + * The final name will be in the following format: + * __ ... + * + * TODO: to make sure the length of this name does not exceed the size of + * chars in a line of a file!!! + **********************************************************************/ +std::string generate_physical_block_module_name(const std::string& prefix, + t_pb_type* physical_pb_type) { + std::string module_name(physical_pb_type->name); + + t_pb_type* parent_pb_type = physical_pb_type; + + /* Backward trace until we meet the top-level pb_type */ + while (1) { + /* If there is no parent mode, this is a top-level pb_type, quit the loop here */ + t_mode* parent_mode = parent_pb_type->parent_mode; + if (NULL == parent_mode) { + break; + } + + /* Add the mode name to the module name */ + module_name = std::string("mode[") + std::string(parent_mode->name) + std::string("]_") + module_name; + + /* Backtrace to the upper level */ + parent_pb_type = parent_mode->parent_pb_type; + + /* If there is no parent pb_type, this is a top-level pb_type, quit the loop here */ + if (NULL == parent_pb_type) { + break; + } + + /* Add the current pb_type name to the module name */ + module_name = std::string(parent_pb_type->name) + std::string("_") + module_name; + } + + /* Exception for top-level pb_type: add an virtual mode name (same name as the pb_type) + * This is to follow the naming convention as non top-level pb_types + * In addition, the name can be really unique, being different than the grid blocks + */ + if (NULL == physical_pb_type->parent_mode) { + module_name += std::string("_mode[") + std::string(physical_pb_type->name) + std::string("]"); + } + + /* Add the prefix */ + module_name = prefix + module_name; return module_name; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 8673de395..7d65a9605 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -130,14 +130,17 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, const size_t& mux_instance_id, const e_spice_model_port_type& port_type); -std::string generate_physical_block_netlist_name(const std::string& block_name, - const bool& is_block_io, - const e_side& io_side, - const std::string& postfix); +std::string generate_grid_block_netlist_name(const std::string& block_name, + const bool& is_block_io, + const e_side& io_side, + const std::string& postfix); + +std::string generate_grid_block_module_name(const std::string& prefix, + const std::string& block_name, + const bool& is_block_io, + const e_side& io_side); std::string generate_physical_block_module_name(const std::string& prefix, - const std::string& block_name, - const bool& is_block_io, - const e_side& io_side); + t_pb_type* physical_pb_type); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 5b103a726..f7105a104 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -26,6 +26,88 @@ #include "verilog_writer_utils.h" #include "verilog_grid.h" +/******************************************************************** + * Print Verilog modules of a LUT as a primitive node in the + * pb_graph_node graph + * This function will instanciate the LUT Verilog module + * generated in the print_verilog_submodule_luts() + * + * Verilog module structure: + * + * Primitive LUT + * +---------------------------------------+ + * | | + * | +---------+ +---------+ | + * in |----->| |--->| |<------|configuration lines + * | | LUT_MUX |... | LUT_MEM | | + * out|<-----| |--->| | | + * | +---------+ +---------+ | + * | | + * +---------------------------------------+ + * + *******************************************************************/ +static +void print_verilog_primitive_lut(std::fstream& fp, + ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + t_pb_graph_node* lut_pb_graph_node, + const e_side& io_side, + const bool& use_explicit_mapping) { + /* Ensure a valid file handler */ + check_file_handler(fp); + + /* Ensure a valid pb_graph_node */ + if (NULL == lut_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid lut_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find the circuit model id linked to the pb_graph_node */ + CircuitModelId& lut_model = lut_pb_graph_node->pb_type->circuit_model; + + /* The circuit model must be a LUT */ + VTR_ASSERT(SPICE_MODEL_LUT == circuit_lib.model_type(lut_model)); + + /* Generate the module name for this primitive pb_graph_node*/ + std::string lut_module_name_prefix(grid_verilog_file_name_prefix); + /* Add side string to the name if it is valid */ + if (NUM_SIDES != io_side) { + Side side_manager(io_side); + lut_module_name_prefix += std::string(side_manager.to_string()); + lut_module_name_prefix += std::string("_"); + } + std::string lut_module_name = generate_physical_block_module_name(lut_module_name_prefix, lut_pb_graph_node->pb_type); + + /* TODO: Create a module of the primitive LUT + * and register it to module manager + */ + ModuleId lut_module = module_manager.add_module(lut_module_name); + VTR_ASSERT(ModuleId::INVALID() != lut_module); + + /* TODO: find the global ports required by the primitive LUT */ + + /* TODO: Print the module definition for the top-level Verilog module of physical block */ + print_verilog_module_declaration(fp, module_manager, lut_module); + /* Finish printing ports */ + + /* TODO: Create local wires as configuration bus */ + + /* TODO: Create a bus wire for the inputs of the LUT */ + + /* TODO: Instanciate LUT MUX module */ + + /* TODO: Instanciate associated memory module for the LUT */ + + /* Print an end to the Verilog module */ + print_verilog_module_end(fp, module_manager.module_name(lut_module)); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + /******************************************************************** * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) * This function will traverse the graph of complex logic block (t_pb_graph_node) @@ -48,6 +130,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* physical_pb_graph_node, + const e_side& io_side, const bool& use_explicit_mapping) { /* Check the file handler*/ check_file_handler(fp); @@ -75,6 +158,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, cur_sram_orgz_info, &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), + io_side, use_explicit_mapping); } } @@ -84,12 +168,11 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* Branch on the type of this physical pb_type, different Verilog modules are generated */ switch (physical_pb_type->class_type) { case LUT_CLASS: - /* TODO: refactor this function - dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, - cur_pb_graph_node, pb_type_index, - cur_pb_type->spice_model, - my_bool_to_boolean(is_explicit_mapping)); - */ + print_verilog_primitive_lut(fp, module_manager, circuit_lib, + cur_sram_orgz_info, + physical_pb_graph_node, + io_side, + use_explicit_mapping); break; case LATCH_CLASS: VTR_ASSERT(0 == physical_pb_type->num_modes); @@ -119,9 +202,19 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, return; } - /* TODO: Generate the name of the Verilog module for this pb_type */ + /* Generate the name of the Verilog module for this pb_type */ + std::string pb_module_name_prefix(grid_verilog_file_name_prefix); + /* Add side string to the name if it is valid */ + if (NUM_SIDES != io_side) { + Side side_manager(io_side); + pb_module_name_prefix += std::string(side_manager.to_string()); + pb_module_name_prefix += std::string("_"); + } + std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); - /* TODO: Register the Verilog module in module manager */ + /* Register the Verilog module in module manager */ + ModuleId pb_module = module_manager.add_module(pb_module_name); + VTR_ASSERT(ModuleId::INVALID() != pb_module); /* TODO: Add ports to the Verilog module */ @@ -130,7 +223,9 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* TODO: Count SRAM ports from the sub-modules under this Verilog module */ /* TODO: Count formal verification ports from the sub-modules under this Verilog module */ - /* TODO: Print Verilog module declaration */ + /* Print Verilog module declaration */ + print_verilog_module_declaration(fp, module_manager, pb_module); + /* Comment lines */ print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); @@ -157,12 +252,14 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, */ /* Print an end to the Verilog module */ - print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); + print_verilog_module_end(fp, module_manager.module_name(pb_module)); - return; + print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); + + /* Add an empty line as a splitter */ + fp << std::endl; } - /***************************************************************************** * This function will create a Verilog file and print out a Verilog netlist * for a type of physical block @@ -189,10 +286,10 @@ void print_verilog_grid(ModuleManager& module_manager, /* Give a name to the Verilog netlist */ /* Create the file name for Verilog */ std::string verilog_fname(subckt_dir - + generate_physical_block_netlist_name(std::string(phy_block_type->name), - IO_TYPE == phy_block_type, - border_side, - std::string(verilog_netlist_file_postfix)) + + generate_grid_block_netlist_name(std::string(phy_block_type->name), + IO_TYPE == phy_block_type, + border_side, + std::string(verilog_netlist_file_postfix)) ); /* TODO: remove the bak file when the file is ready */ verilog_fname += ".bak"; @@ -222,30 +319,26 @@ void print_verilog_grid(ModuleManager& module_manager, print_verilog_include_defines_preproc_file(fp, verilog_dir); /* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */ - for (int iz = 0; iz < phy_block_type->capacity; ++iz) { - /* ONLY output one Verilog module (which is unique), others are the same */ - if (0 < iz) { - continue; - } - /* TODO: use a Depth-First Search Algorithm to print the sub-modules - * Note: DFS is the right way. Do NOT use BFS. - * DFS can guarantee that all the sub-modules can be registered properly - * to its parent in module manager - */ - print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); + /* TODO: use a Depth-First Search Algorithm to print the sub-modules + * Note: DFS is the right way. Do NOT use BFS. + * DFS can guarantee that all the sub-modules can be registered properly + * to its parent in module manager + */ + print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ - print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, - cur_sram_orgz_info, - phy_block_type->pb_graph_head, - use_explicit_mapping); + /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ + print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, + cur_sram_orgz_info, + phy_block_type->pb_graph_head, + border_side, + use_explicit_mapping); - print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - } + print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); /* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string module_name = generate_physical_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); + std::string module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); /* TODO: Add ports to the module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 9cebf20ac..8c92880d6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2617,8 +2617,7 @@ void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, std::vector mem_output_ports; mem_output_ports.push_back(mux_config_port); mem_output_ports.push_back(mux_config_inv_port); - mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, - config_bus, + mem_port2port_name_map = generate_mem_module_port2port_map(config_bus, mem_output_ports, circuit_lib.design_tech_type(mux_model), cur_sram_orgz_info->type); @@ -3786,8 +3785,7 @@ void print_verilog_connection_box_mux(ModuleManager& module_manager, std::vector mem_output_ports; mem_output_ports.push_back(mux_config_port); mem_output_ports.push_back(mux_config_inv_port); - mem_port2port_name_map = generate_mem_module_port2port_map(module_manager, mem_module, - config_bus, + mem_port2port_name_map = generate_mem_module_port2port_map(config_bus, mem_output_ports, circuit_lib.design_tech_type(mux_model), cur_sram_orgz_info->type); From 512e9f4e8ec769e6ff1b7740ab067c5c3783594c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Oct 2019 12:10:26 -0600 Subject: [PATCH 272/482] refactoring Verilog generation for primitive pb_types --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 132 ++++++++++-------- 2 files changed, 73 insertions(+), 63 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index fa87405d9..913c17e12 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -733,7 +733,7 @@ std::string generate_physical_block_module_name(const std::string& prefix, } /* Add the mode name to the module name */ - module_name = std::string("mode[") + std::string(parent_mode->name) + std::string("]_") + module_name; + module_name = std::string("mode_") + std::string(parent_mode->name) + std::string("__") + module_name; /* Backtrace to the upper level */ parent_pb_type = parent_mode->parent_pb_type; @@ -752,7 +752,7 @@ std::string generate_physical_block_module_name(const std::string& prefix, * In addition, the name can be really unique, being different than the grid blocks */ if (NULL == physical_pb_type->parent_mode) { - module_name += std::string("_mode[") + std::string(physical_pb_type->name) + std::string("]"); + module_name += std::string("_mode_") + std::string(physical_pb_type->name) + std::string("_"); } /* Add the prefix */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index f7105a104..3d3e45e55 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -27,19 +27,25 @@ #include "verilog_grid.h" /******************************************************************** - * Print Verilog modules of a LUT as a primitive node in the - * pb_graph_node graph - * This function will instanciate the LUT Verilog module - * generated in the print_verilog_submodule_luts() + * Print Verilog modules of a primitive node in the pb_graph_node graph + * This generic function can support all the different types of primitive nodes + * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders. + * + * The Verilog module will consist of two parts: + * 1. Logic module of the primitive node + * This module performs the logic function of the block + * 2. Memory module of the primitive node + * This module stores the configuration bits for the logic module + * if the logic module is a programmable resource, such as LUT * * Verilog module structure: * - * Primitive LUT + * Primitive block * +---------------------------------------+ * | | * | +---------+ +---------+ | * in |----->| |--->| |<------|configuration lines - * | | LUT_MUX |... | LUT_MEM | | + * | | Logic |... | Memory | | * out|<-----| |--->| | | * | +---------+ +---------+ | * | | @@ -47,50 +53,82 @@ * *******************************************************************/ static -void print_verilog_primitive_lut(std::fstream& fp, - ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, - t_pb_graph_node* lut_pb_graph_node, - const e_side& io_side, - const bool& use_explicit_mapping) { +void print_verilog_primitive_block(std::fstream& fp, + ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + t_pb_graph_node* primitive_pb_graph_node, + const e_side& io_side, + const bool& use_explicit_mapping) { /* Ensure a valid file handler */ check_file_handler(fp); /* Ensure a valid pb_graph_node */ - if (NULL == lut_pb_graph_node) { + if (NULL == primitive_pb_graph_node) { vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid lut_pb_graph_node!\n", + "(File:%s,[LINE%d]) Invalid primitive_pb_graph_node!\n", __FILE__, __LINE__); exit(1); } /* Find the circuit model id linked to the pb_graph_node */ - CircuitModelId& lut_model = lut_pb_graph_node->pb_type->circuit_model; - - /* The circuit model must be a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_lib.model_type(lut_model)); + CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model; /* Generate the module name for this primitive pb_graph_node*/ - std::string lut_module_name_prefix(grid_verilog_file_name_prefix); - /* Add side string to the name if it is valid */ + std::string primitive_module_name_prefix(grid_verilog_file_name_prefix); + /* Add side string to the name if it is valid, this is mainly for I/O block */ if (NUM_SIDES != io_side) { Side side_manager(io_side); - lut_module_name_prefix += std::string(side_manager.to_string()); - lut_module_name_prefix += std::string("_"); + primitive_module_name_prefix += std::string(side_manager.to_string()); + primitive_module_name_prefix += std::string("_"); } - std::string lut_module_name = generate_physical_block_module_name(lut_module_name_prefix, lut_pb_graph_node->pb_type); + std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); - /* TODO: Create a module of the primitive LUT - * and register it to module manager + /* Create a module of the primitive LUT and register it to module manager */ + ModuleId primitive_module = module_manager.add_module(primitive_module_name); + /* Ensure that the module has been created and thus unique! */ + VTR_ASSERT(ModuleId::INVALID() != primitive_module); + + /* Find the global ports required by the primitive node, and add them to the module */ + std::vector primitive_model_global_ports = circuit_lib.model_global_ports_by_type(primitive_model, SPICE_MODEL_PORT_INPUT, true, false); + for (auto port : primitive_model_global_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Find the inout ports required by the primitive node, and add them to the module + * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric */ - ModuleId lut_module = module_manager.add_module(lut_module_name); - VTR_ASSERT(ModuleId::INVALID() != lut_module); + std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); + for (auto port : primitive_model_inout_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INOUT_PORT); + } + /* Find the input ports required by the primitive node, and add them to the module */ + std::vector primitive_model_input_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INPUT); + for (auto port : primitive_model_input_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Find the output ports required by the primitive node, and add them to the module */ + std::vector primitive_model_output_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_OUTPUT); + for (auto port : primitive_model_output_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); + } + /* Find the clock ports required by the primitive node, and add them to the module */ + std::vector primitive_model_clock_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_CLOCK); + for (auto port : primitive_model_clock_ports) { + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_CLOCK_PORT); + } - /* TODO: find the global ports required by the primitive LUT */ + /* Add configuration ports */ + /* TODO: Shared SRAM ports*/ + /* TODO: Regular (independent) SRAM ports */ + /* TODO: SRAM ports for formal verfiication */ - /* TODO: Print the module definition for the top-level Verilog module of physical block */ - print_verilog_module_declaration(fp, module_manager, lut_module); + /* Print the module definition for the top-level Verilog module of physical block */ + print_verilog_module_declaration(fp, module_manager, primitive_module); /* Finish printing ports */ /* TODO: Create local wires as configuration bus */ @@ -102,7 +140,7 @@ void print_verilog_primitive_lut(std::fstream& fp, /* TODO: Instanciate associated memory module for the LUT */ /* Print an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(lut_module)); + print_verilog_module_end(fp, module_manager.module_name(primitive_module)); /* Add an empty line as a splitter */ fp << std::endl; @@ -165,39 +203,11 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* For leaf node, a primitive Verilog module will be generated */ if (TRUE == is_primitive_pb_type(physical_pb_type)) { - /* Branch on the type of this physical pb_type, different Verilog modules are generated */ - switch (physical_pb_type->class_type) { - case LUT_CLASS: - print_verilog_primitive_lut(fp, module_manager, circuit_lib, + print_verilog_primitive_block(fp, module_manager, circuit_lib, cur_sram_orgz_info, physical_pb_graph_node, io_side, use_explicit_mapping); - break; - case LATCH_CLASS: - VTR_ASSERT(0 == physical_pb_type->num_modes); - /* TODO: refactor this function - dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, - cur_pb_graph_node, pb_type_index, - cur_pb_type->spice_model, - my_bool_to_boolean(is_explicit_mapping)); - */ - break; - case UNKNOWN_CLASS: - case MEMORY_CLASS: - /* TODO: refactor this function - dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, - cur_pb_graph_node , pb_type_index, - cur_pb_type->spice_model, - my_bool_to_boolean(is_explicit_mapping)); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Unknown class type of pb_type(%s)!\n", - __FILE__, __LINE__, physical_pb_type->name); - exit(1); - } /* Finish for primitive node, return */ return; } From ea2942640e8fe7ae47c058a281d9e71cee293593 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Oct 2019 14:03:17 -0600 Subject: [PATCH 273/482] refactored port addition for pb_types in Verilog generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 28 ++++++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 ++ .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 65 +++++++++++++++++-- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 6 ++ .../fpga_x2p/base/link_arch_circuit_lib.cpp | 6 +- .../fpga_x2p/base/module_manager_utils.cpp | 42 ++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 5 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 41 +++++------- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 1 + 9 files changed, 168 insertions(+), 31 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 913c17e12..76c0e7086 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -760,3 +760,31 @@ std::string generate_physical_block_module_name(const std::string& prefix, return module_name; } + + +/********************************************************************* + * Generate the port name of a Verilog module describing a pb_type + * The name convention is + * _ + ********************************************************************/ +std::string generate_pb_type_port_name(t_port* pb_type_port) { + std::string port_name; + + port_name = std::string(pb_type_port->parent_pb_type->name) + std::string("_") + std::string(pb_type_port->name); + + return port_name; +} + +/********************************************************************* + * Generate the global I/O port name of a Verilog module + * This is mainly used by I/O circuit models + ********************************************************************/ +std::string generate_fpga_global_io_port_name(const std::string& prefix, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + std::string port_name(prefix); + + port_name += circuit_lib.model_name(circuit_model); + + return port_name; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 7d65a9605..989c60714 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -143,4 +143,9 @@ std::string generate_grid_block_module_name(const std::string& prefix, std::string generate_physical_block_module_name(const std::string& prefix, t_pb_type* physical_pb_type); +std::string generate_pb_type_port_name(t_port* pb_type_port); + +std::string generate_fpga_global_io_port_name(const std::string& prefix, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index 9da08d95b..b1eb28306 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -1,7 +1,15 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ +/******************************************************************** + * This file includes most utilized functions to operate on pb_type + * related data structures, including t_pb_type, t_pb_graph_node, t_pb + * + * Note: + * If you want to classify functions, functions in this file should meet + * at least one of it + * 1. non-generic data query of pb_type - related data structures + * 2. non-generic mutator/copy the pb_type + * + * Generic accessors/mutators should be a method of the data structure + ********************************************************************/ #include #include #include @@ -12,6 +20,7 @@ #include /* Include vpr structs*/ +#include "vtr_assert.h" #include "util.h" #include "physical_types.h" #include "vpr_types.h" @@ -1322,6 +1331,54 @@ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, return ret; } +/******************************************************************** + * Return a list of ports of a pb_type which matches the ports defined + * in its linked circuit model + * This function will only care if the port type matches + *******************************************************************/ +std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, + enum e_spice_model_port_type port_type) { + std::vector ports; + + for (int iport = 0; iport < pb_type->num_ports; ++iport) { + /* Check the circuit_port id of the port ? */ + VTR_ASSERT(CircuitPortId::INVALID() != pb_type->ports[iport].circuit_model_port); + switch (port_type) { + case SPICE_MODEL_PORT_INPUT: + if ( (IN_PORT == pb_type->ports[iport].type) + && (0 == pb_type->ports[iport].is_clock) ) { + ports.push_back(&pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_OUTPUT: + if ( (OUT_PORT == pb_type->ports[iport].type) + && (0 == pb_type->ports[iport].is_clock) ) { + ports.push_back(&pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_INOUT: + if ( (INOUT_PORT == pb_type->ports[iport].type) + && (0 == pb_type->ports[iport].is_clock) ) { + ports.push_back(&pb_type->ports[iport]); + } + break; + case SPICE_MODEL_PORT_CLOCK: + if ( (IN_PORT == pb_type->ports[iport].type) + && (1 == pb_type->ports[iport].is_clock) ) { + ports.push_back(&pb_type->ports[iport]); + } + break; + /* Configuration ports are not in pb_type definition */ + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid type for port!\n", + __FILE__, __LINE__); + exit(1); + } + } + + return ports; +} t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 8a85329c0..ee5db00f4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -1,6 +1,9 @@ #ifndef FPGA_X2P_PBTYPES_UTILS_H #define FPGA_X2P_PBTYPES_UTILS_H +/* Only include header files those are required by the data types in the following function declaration */ +#include +#include "fpga_x2p_types.h" #include "fpga_x2p_bitstream_utils.h" void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge); @@ -100,6 +103,9 @@ void map_clb_pins_to_pb_graph_pins(); t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, t_spice_model_port* spice_model_port); +std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, + enum e_spice_model_port_type port_type); + t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type, int* port_num); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index 8e1848932..86d3aabee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -270,12 +270,12 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, cur_pb_type->ports[iport].circuit_model_port = CircuitPortId::INVALID(); } - /* Return if SPICE_MODEL is NULL */ + /* Return if circuit model is NULL */ if (CircuitModelId::INVALID() == circuit_model) { return 0; } - /* For each port, find a SPICE model port, which has the same name and port size */ + /* For each port, find a circuit model port, which has the same name and port size */ for (auto& port : circuit_lib.model_ports(circuit_model)) { t_port* cur_pb_type_port = find_pb_type_port_match_circuit_model_port(cur_pb_type, circuit_lib, port); /* Not every spice_model_port can find a mapped pb_type_port. @@ -292,7 +292,7 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { if (CircuitPortId::INVALID() == cur_pb_type->ports[iport].circuit_model_port) { vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", + "(File:%s, [LINE%d]) Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, circuit_lib.model_name(circuit_model).c_str()); exit(1); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 6b7c9bdc9..120ed3958 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -14,6 +14,7 @@ #include "module_manager.h" #include "fpga_x2p_naming.h" +#include "fpga_x2p_pbtypes_utils.h" #include "module_manager_utils.h" @@ -210,3 +211,44 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, } } +/******************************************************************** + * Add ports of a pb_type block to module manager + * Port addition will follow the sequence: inout, input, output, clock + * This will help use to keep a clean module definition when printing out + * To avoid port mismatch between the pb_type and its linked circuit model + * This function will also check that each pb_type port is actually exist + * in the linked circuit model + *******************************************************************/ +void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_pb_type* cur_pb_type) { + + /* Find the inout ports required by the primitive pb_type, and add them to the module */ + std::vector pb_type_inout_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT); + for (auto port : pb_type_inout_ports) { + BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INOUT_PORT); + } + + /* Find the input ports required by the primitive pb_type, and add them to the module */ + std::vector pb_type_input_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT); + for (auto port : pb_type_input_ports) { + BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* Find the output ports required by the primitive pb_type, and add them to the module */ + std::vector pb_type_output_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT); + for (auto port : pb_type_output_ports) { + BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* Find the clock ports required by the primitive pb_type, and add them to the module */ + std::vector pb_type_clock_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK); + for (auto port : pb_type_clock_ports) { + BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); + module_manager.add_port(module_id, module_port, ModuleManager::MODULE_CLOCK_PORT); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 17d395cdb..cbdc04891 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -10,6 +10,7 @@ #include #include "device_port.h" #include "spice_types.h" +#include "vpr_types.h" #include "circuit_library.h" #include "module_manager.h" @@ -38,5 +39,9 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, const e_sram_orgz sram_orgz_type, const size_t& port_size); +void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_pb_type* cur_pb_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 3d3e45e55..5e56b5327 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -19,6 +19,8 @@ #include "fpga_x2p_types.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_pbtypes_utils.h" +#include "module_manager_utils.h" +#include "fpga_x2p_globals.h" /* Header files for Verilog generator */ #include "verilog_global.h" @@ -90,37 +92,28 @@ void print_verilog_primitive_block(std::fstream& fp, VTR_ASSERT(ModuleId::INVALID() != primitive_module); /* Find the global ports required by the primitive node, and add them to the module */ - std::vector primitive_model_global_ports = circuit_lib.model_global_ports_by_type(primitive_model, SPICE_MODEL_PORT_INPUT, true, false); + std::vector primitive_model_global_ports = circuit_lib.model_global_ports(primitive_model, true); for (auto port : primitive_model_global_ports) { + /* The global I/O of the FPGA has a special name */ BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INPUT_PORT); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GLOBAL_PORT); } + /* Find the inout ports required by the primitive node, and add them to the module * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric */ - std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); - for (auto port : primitive_model_inout_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INOUT_PORT); - } - /* Find the input ports required by the primitive node, and add them to the module */ - std::vector primitive_model_input_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INPUT); - for (auto port : primitive_model_input_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INPUT_PORT); - } - /* Find the output ports required by the primitive node, and add them to the module */ - std::vector primitive_model_output_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_OUTPUT); - for (auto port : primitive_model_output_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); - } - /* Find the clock ports required by the primitive node, and add them to the module */ - std::vector primitive_model_clock_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_CLOCK); - for (auto port : primitive_model_clock_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_CLOCK_PORT); + if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { + std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); + for (auto port : primitive_model_inout_ports) { + BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INOUT_PORT); + } } + /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here. + * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P, + * no ports of the circuit model will be missing here + */ + add_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); /* Add configuration ports */ /* TODO: Shared SRAM ports*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 4e6ec1d4a..4a54959b4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -12,6 +12,7 @@ #include /* Include vpr structs*/ +#include "vtr_assert.h" #include "util.h" #include "physical_types.h" #include "vpr_types.h" From 6bed89c2371d979133d32c5274c4329c24f5b68e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Oct 2019 18:00:04 -0600 Subject: [PATCH 274/482] refactored counting config bits for circuit model and update Verilog generation for primitive pb_types --- .../libarchfpga/SRC/circuit_library_utils.cpp | 98 +++++++++++++++++++ .../libarchfpga/SRC/circuit_library_utils.h | 8 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 31 +++++- 3 files changed, 134 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp index 63fcb15eb..373a46117 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -91,3 +91,101 @@ std::vector find_circuit_regular_sram_ports(const CircuitLibrary& return regular_sram_ports; } + +/******************************************************************** + * Find the number of shared configuration bits for a ReRAM circuit + * TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!! + *******************************************************************/ +static +size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& rram_model, + const e_sram_orgz& sram_orgz_type) { + size_t num_shared_config_bits = 0; + + /* Branch on the organization of configuration protocol */ + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_SCAN_CHAIN: + break; + case SPICE_SRAM_MEMORY_BANK: { + /* Find BL/WL ports */ + std::vector blb_ports = circuit_lib.model_ports_by_type(rram_model, SPICE_MODEL_PORT_BLB); + for (auto blb_port : blb_ports) { + num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1); + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } + + return num_shared_config_bits; +} + +/******************************************************************** + * A generic function to find the number of shared configuration bits + * for circuit model + * It will return 0 for CMOS circuits + * It will return the maximum shared configuration bits across ReRAM models + * + * Note: This function may give WRONG results when all the SRAM ports + * are not properly linked to its circuit models! + * So, it should be called after the SRAM linking is done!!! + * + * IMPORTANT: This function should NOT be used to find the number of shared configuration bits + * for a multiplexer, because the multiplexer size is determined during + * the FPGA architecture generation (NOT during the XML parsing). + *******************************************************************/ +size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const e_sram_orgz& sram_orgz_type) { + size_t num_shared_config_bits = 0; + + std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); + for (auto sram_port : sram_ports) { + CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port); + VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); + + /* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */ + switch (circuit_lib.design_tech_type(sram_model)) { + case SPICE_MODEL_DESIGN_CMOS: + /* CMOS circuit do not need shared configuration bits */ + break; + case SPICE_MODEL_DESIGN_RRAM: + /* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */ + num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type)); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid design technology for SRAM model!\n", + __FILE__, __LINE__); + exit(1); + } + } + + return num_shared_config_bits; +} + +/******************************************************************** + * A generic function to find the number of configuration bits + * for circuit model + * It will sum up the sizes of all the sram ports + * + * IMPORTANT: This function should NOT be used to find the number of configuration bits + * for a multiplexer, because the multiplexer size is determined during + * the FPGA architecture generation (NOT during the XML parsing). + *******************************************************************/ +size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + size_t num_config_bits = 0; + + std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); + for (auto sram_port : sram_ports) { + num_config_bits += circuit_lib.port_size(sram_port); + } + + return num_config_bits; +} diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h index f4323f391..2fa705c25 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h @@ -8,6 +8,7 @@ /* Standard header files required go first */ #include +#include "spice_types.h" #include "circuit_library.h" std::vector find_circuit_sram_models(const CircuitLibrary& circuit_lib, @@ -16,4 +17,11 @@ std::vector find_circuit_sram_models(const CircuitLibrary& circu std::vector find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); +size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const e_sram_orgz& sram_orgz_type); + +size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 5e56b5327..f4c719900 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -9,6 +9,7 @@ /* Header files from external libs */ #include "util.h" #include "vtr_assert.h" +#include "circuit_library_utils.h" /* Header files for VPR */ #include "vpr_types.h" @@ -116,9 +117,33 @@ void print_verilog_primitive_block(std::fstream& fp, add_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); /* Add configuration ports */ - /* TODO: Shared SRAM ports*/ - /* TODO: Regular (independent) SRAM ports */ - /* TODO: SRAM ports for formal verfiication */ + /* Shared SRAM ports*/ + size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, cur_sram_orgz_info->type); + if (0 < num_shared_config_bits) { + /* Check: this SRAM organization type must be memory-bank ! */ + VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); + /* Generate a list of ports */ + add_reserved_sram_ports_to_module_manager(module_manager, primitive_module, + num_shared_config_bits); + } + + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* Regular (independent) SRAM ports */ + size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model); + if (0 < num_config_bits) { + add_sram_ports_to_module_manager(module_manager, primitive_module, + circuit_lib, sram_model, cur_sram_orgz_info->type, + num_config_bits); + /* Add ports only visible during formal verification to the module */ + add_formal_verification_sram_ports_to_module_manager(module_manager, primitive_module, circuit_lib, sram_model, + std::string(verilog_formal_verification_preproc_flag), + num_config_bits); + } /* Print the module definition for the top-level Verilog module of physical block */ print_verilog_module_declaration(fp, module_manager, primitive_module); From 6f42aac626a1c6ca8687da8f73d066ce99a9df7a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Oct 2019 20:14:38 -0600 Subject: [PATCH 275/482] add wire connection in Verilog module declaration --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 18 ++++++++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 5 +++ .../fpga_x2p/base/module_manager_utils.cpp | 8 +++++ .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 4 +++ .../fpga_x2p/verilog/verilog_writer_utils.cpp | 33 +++++++++++++++++++ 5 files changed, 68 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 2a89a748c..bdcbf174e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -99,6 +99,13 @@ size_t ModuleManager::num_instance(const ModuleId& parent_module, const ModuleId return 0; } +/* Find if a port is a wire connection */ +bool ModuleManager::port_is_wire(const ModuleId& module, const ModulePortId& port) const { + /* validate both module id and port id*/ + VTR_ASSERT(valid_module_port_id(module, port)); + return port_is_wire_[module][port]; +} + /* Find if a port is register */ bool ModuleManager::port_is_register(const ModuleId& module, const ModulePortId& port) const { /* validate both module id and port id*/ @@ -137,6 +144,7 @@ ModuleId ModuleManager::add_module(const std::string& name) { port_ids_.emplace_back(); ports_.emplace_back(); port_types_.emplace_back(); + port_is_wire_.emplace_back(); port_is_register_.emplace_back(); port_preproc_flags_.emplace_back(); @@ -162,6 +170,7 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, port_ids_[module].push_back(port); ports_[module].push_back(port_info); port_types_[module].push_back(port_type); + port_is_wire_[module].push_back(false); port_is_register_[module].push_back(false); port_preproc_flags_[module].emplace_back(); /* Create an empty string for the pre-processing flags */ @@ -178,6 +187,15 @@ void ModuleManager::set_module_name(const ModuleId& module, const std::string& n names_[module] = name; } +/* Set a port to be a wire */ +void ModuleManager::set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire) { + /* Find the port */ + ModulePortId port = find_module_port(module, port_name); + /* Must find something, otherwise drop an error */ + VTR_ASSERT(ModulePortId::INVALID() != port); + port_is_wire_[module][port] = is_wire; +} + /* Set a port to be a register */ void ModuleManager::set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register) { /* Find the port */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 297046059..c99d3ffa1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -46,6 +46,8 @@ class ModuleManager { ModuleId find_module(const std::string& name) const; /* Find the number of instances of a child module in the parent module */ size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const; + /* Find if a port is a wire connection */ + bool port_is_wire(const ModuleId& module, const ModulePortId& port) const; /* Find if a port is register */ bool port_is_register(const ModuleId& module, const ModulePortId& port) const; /* Return the pre-processing flag of a port */ @@ -58,6 +60,8 @@ class ModuleManager { const BasicPort& port_info, const enum e_module_port_type& port_type); /* Set a name for a module */ void set_module_name(const ModuleId& module, const std::string& name); + /* Set a port to be a wire */ + void set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire); /* Set a port to be a register */ void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register); /* Set the preprocessing flag for a port */ @@ -80,6 +84,7 @@ class ModuleManager { vtr::vector> port_ids_; /* List of ports for each Module */ vtr::vector> ports_; /* List of ports for each Module */ vtr::vector> port_types_; /* Type of ports */ + vtr::vector> port_is_wire_; /* If the port is a wire, use for Verilog port definition. If enabled: reg */ vtr::vector> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: reg */ vtr::vector> port_preproc_flags_; /* If a port is available only when a pre-processing flag is enabled. This is to record the pre-processing flags */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 120ed3958..9f744bd24 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -228,6 +228,8 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, for (auto port : pb_type_inout_ports) { BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INOUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, module_port.get_name(), true); } /* Find the input ports required by the primitive pb_type, and add them to the module */ @@ -235,6 +237,8 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, for (auto port : pb_type_input_ports) { BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, module_port.get_name(), true); } /* Find the output ports required by the primitive pb_type, and add them to the module */ @@ -242,6 +246,8 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, for (auto port : pb_type_output_ports) { BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, module_port.get_name(), true); } /* Find the clock ports required by the primitive pb_type, and add them to the module */ @@ -249,6 +255,8 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, for (auto port : pb_type_clock_ports) { BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); module_manager.add_port(module_id, module_port, ModuleManager::MODULE_CLOCK_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, module_port.get_name(), true); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 5c7e27449..50f924c32 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -104,11 +104,15 @@ void print_verilog_submodule_lut(ModuleManager& module_manager, for (const auto& port : lut_input_ports) { BasicPort input_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, input_port.get_name(), true); } /* Add each output port */ for (const auto& port : lut_output_ports) { BasicPort output_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, output_port.get_name(), true); } /* Add each regular (not mode select) SRAM port */ for (const auto& port : lut_regular_sram_ports) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 2a4025cf3..141a2c367 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -194,6 +194,39 @@ void print_verilog_module_ports(std::fstream& fp, } } } + + /* Output any port that is also wire connection */ + fp << std::endl; + fp << "//----- BEGIN wire-connection ports -----" << std::endl; + for (const auto& kv : port_type2type_map) { + for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { + /* Skip the ports that are not registered */ + ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); + VTR_ASSERT(ModulePortId::INVALID() != port_id); + if (false == module_manager.port_is_wire(module_id, port_id)) { + continue; + } + + /* Print pre-processing flag for a port, if defined */ + std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); + if (false == preproc_flag.empty()) { + /* Print an ifdef Verilog syntax */ + print_verilog_preprocessing_flag(fp, preproc_flag); + } + + /* Print port */ + fp << generate_verilog_port(VERILOG_PORT_WIRE, port); + fp << ";" << std::endl; + + if (false == preproc_flag.empty()) { + /* Print an endif to pair the ifdef */ + print_verilog_endif(fp); + } + } + } + fp << "//----- END wire-connection ports -----" << std::endl; + fp << std::endl; + /* Output any port that is registered */ fp << std::endl; From 9cb6e64ab3b7f3241ac6995e6de73e6ebfe7e27e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Oct 2019 21:29:42 -0600 Subject: [PATCH 276/482] refactoring instanciation inside primitive pb_type Verilog module --- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 20 +++++++++++ .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 7 ++++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 35 ++++++++++++++++--- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 1 - .../fpga_x2p/verilog/verilog_writer_utils.h | 6 ++++ 5 files changed, 64 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index b1eb28306..83fcf2121 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -38,6 +38,7 @@ #include "fpga_x2p_lut_utils.h" #include "fpga_x2p_bitstream_utils.h" #include "fpga_x2p_pbtypes_utils.h" +#include "fpga_x2p_naming.h" #include "fpga_x2p_globals.h" /* Make sure the edge has only one input pin and output pin*/ @@ -1331,6 +1332,25 @@ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, return ret; } +/******************************************************************** + * Add the port-to-port mapping between a pb_type and its linked circuit model + * This function is mainly used to create instance of the module for a pb_type + *******************************************************************/ +void generate_pb_type_circuit_port2port_name_map(std::map& port2port_name_map, + t_pb_type* cur_pb_type, + const CircuitLibrary& circuit_lib) { + for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) { + t_port* pb_type_port = &(cur_pb_type->ports[iport]); + /* Must have a linked circuit model port */ + VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port); + std::string module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port); + /* Generate the module port name of pb_type */ + BasicPort instance_port(generate_pb_type_port_name(pb_type_port), circuit_lib.port_size(pb_type_port->circuit_model_port)); + /* Create the port of primitive model */ + port2port_name_map[module_port_name] = instance_port; + } +} + /******************************************************************** * Return a list of ports of a pb_type which matches the ports defined * in its linked circuit model diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index ee5db00f4..d7c969efa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -3,6 +3,9 @@ /* Only include header files those are required by the data types in the following function declaration */ #include +#include +#include "device_port.h" +#include "circuit_library.h" #include "fpga_x2p_types.h" #include "fpga_x2p_bitstream_utils.h" @@ -103,6 +106,10 @@ void map_clb_pins_to_pb_graph_pins(); t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, t_spice_model_port* spice_model_port); +void generate_pb_type_circuit_port2port_name_map(std::map& port2port_name_map, + t_pb_type* cur_pb_type, + const CircuitLibrary& circuit_lib); + std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index f4c719900..dd6822c35 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -149,13 +149,40 @@ void print_verilog_primitive_block(std::fstream& fp, print_verilog_module_declaration(fp, module_manager, primitive_module); /* Finish printing ports */ - /* TODO: Create local wires as configuration bus */ + /* Find the module id in the module manager */ + ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model)); + VTR_ASSERT(ModuleId::INVALID() != logic_module); + size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); - /* TODO: Create a bus wire for the inputs of the LUT */ + /* Local wires for memory configurations */ + print_verilog_comment(fp, std::string("---- BEGIN local configuration bus ----")); + print_verilog_local_config_bus(fp, circuit_lib.model_name(primitive_model), cur_sram_orgz_info->type, logic_instance_id, num_config_bits); + print_verilog_comment(fp, std::string("---- END local configuration bus ----")); - /* TODO: Instanciate LUT MUX module */ + /* Add an empty line as a splitter */ + fp << std::endl; - /* TODO: Instanciate associated memory module for the LUT */ + /* TODO: Instanciate the logic module */ + /* Create port-to-port map */ + std::map logic_port2port_name_map; + /* Link the logic model ports to pb_type ports */ + generate_pb_type_circuit_port2port_name_map(logic_port2port_name_map, primitive_pb_graph_node->pb_type, circuit_lib); + /* TODO: Link both regular and mode-select SRAM ports */ + + /* Print an instance of the logic Module */ + print_verilog_comment(fp, std::string("----- BEGIN Instanciation of " + circuit_lib.model_name(primitive_model) + " -----")); + print_verilog_module_instance(fp, module_manager, primitive_module, logic_module, logic_port2port_name_map, use_explicit_mapping); + print_verilog_comment(fp, std::string("----- END Instanciation of " + circuit_lib.model_name(primitive_model) + " -----")); + fp << std::endl; + /* IMPORTANT: this update MUST be called after the instance outputting!!!! + * update the module manager with the relationship between the parent and child modules + */ + module_manager.add_child_module(primitive_module, logic_module); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* TODO: Instanciate associated memory module */ /* Print an end to the Verilog module */ print_verilog_module_end(fp, module_manager.module_name(primitive_module)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 141a2c367..d582c59bd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -867,7 +867,6 @@ void print_verilog_local_sram_wires(std::fstream& fp, * +----------+ +----------+ +----------+ * *********************************************************************/ -static void print_verilog_local_config_bus(std::fstream& fp, const std::string& prefix, const e_sram_orgz& sram_orgz_type, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index e53ac0a40..5e390ed02 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -90,6 +90,12 @@ void print_verilog_local_sram_wires(std::fstream& fp, const e_sram_orgz sram_orgz_type, const size_t& port_size); +void print_verilog_local_config_bus(std::fstream& fp, + const std::string& prefix, + const e_sram_orgz& sram_orgz_type, + const size_t& instance_id, + const size_t& num_conf_bits); + void print_verilog_mux_config_bus(std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& mux_model, From 557d8b60f35fe757c2e1b84c8fd4467921665077 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 9 Oct 2019 20:30:16 -0600 Subject: [PATCH 277/482] start implementing module graph-based connection --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 132 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 34 +++++ .../SRC/fpga_x2p/base/module_manager_fwd.h | 4 + 3 files changed, 170 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index bdcbf174e..6f0bc0e69 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -148,6 +148,18 @@ ModuleId ModuleManager::add_module(const std::string& name) { port_is_register_.emplace_back(); port_preproc_flags_.emplace_back(); + net_ids_.emplace_back(); + net_names_.emplace_back(); + net_src_module_ids_.emplace_back(); + net_src_instance_ids_.emplace_back(); + net_src_port_ids_.emplace_back(); + net_src_pin_ids_.emplace_back(); + + net_sink_module_ids_.emplace_back(); + net_sink_instance_ids_.emplace_back(); + net_sink_port_ids_.emplace_back(); + net_sink_pin_ids_.emplace_back(); + /* Register in the name-to-id map */ name_id_map_[name] = module; @@ -155,6 +167,11 @@ ModuleId ModuleManager::add_module(const std::string& name) { port_lookup_.emplace_back(); port_lookup_[module].resize(NUM_MODULE_PORT_TYPES); + /* Build fast look-up for nets */ + net_lookup_.emplace_back(); + /* Reserve the instance 0 for the module */ + net_lookup_[module][module].emplace_back(); + /* Return the new id */ return module; } @@ -177,6 +194,10 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, /* Update fast look-up for port */ port_lookup_[module][port_type].push_back(port); + /* Update fast look-up for nets */ + VTR_ASSERT_SAFE(1 == net_lookup_[module][module].size()); + net_lookup_[module][module][0][port].resize(port_info.get_width()); + return port; } @@ -234,6 +255,106 @@ void ModuleManager::add_child_module(const ModuleId& parent_module, const Module /* Increase the counter of instances */ num_child_instances_[parent_module][child_it - children_[parent_module].begin()]++; } + + /* Update fast look-up for nets */ + size_t instance_id = net_lookup_[parent_module][child_module].size(); + /* Find the ports for the child module and update the fast look-up */ + for (ModulePortId child_port : port_ids_[child_module]) { + net_lookup_[parent_module][child_module].emplace_back(); + net_lookup_[parent_module][child_module][instance_id][child_port].resize(ports_[child_module][child_port].get_width()); + } +} + +/* Add a net to the connection graph of the module */ +ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { + /* Validate the module id */ + VTR_ASSERT ( valid_module_id(module) ); + + /* Create an new id */ + ModuleNetId net = ModuleNetId(net_ids_[module].size()); + net_ids_[module].push_back(net); + + /* Allocate net-related data structures */ + net_names_[module].emplace_back(); + net_src_module_ids_[module].emplace_back(); + net_src_instance_ids_[module].emplace_back(); + net_src_port_ids_[module].emplace_back(); + net_src_pin_ids_[module].emplace_back(); + + net_sink_module_ids_[module].emplace_back(); + net_sink_instance_ids_[module].emplace_back(); + net_sink_port_ids_[module].emplace_back(); + net_sink_pin_ids_[module].emplace_back(); + + return net; +} + +/* Add a source to a net in the connection graph */ +void ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNetId& net, + const ModuleId& src_module, const size_t& instance_id, + const ModulePortId& src_port, const size_t& src_pin) { + /* Validate the module and net id */ + VTR_ASSERT(valid_module_net_id(module, net)); + + /* Validate the source module */ + VTR_ASSERT(valid_module_id(src_module)); + net_src_module_ids_[module][net].push_back(src_module); + + /* if it has the same id as module, our instance id will be by default 0 */ + size_t src_instance_id = instance_id; + if (src_module == module) { + src_instance_id = 0; + net_src_instance_ids_[module][net].push_back(src_instance_id); + } else { + /* Check the instance id of the src module */ + VTR_ASSERT (src_instance_id < num_instance(module, src_module)); + net_src_instance_ids_[module][net].push_back(src_instance_id); + } + + /* Validate the port exists in the src module */ + VTR_ASSERT(valid_module_port_id(src_module, src_port)); + net_src_port_ids_[module][net].push_back(src_port); + + /* Validate the pin id is in the range of the port width */ + VTR_ASSERT(src_pin < module_port(src_module, src_port).get_width()); + net_src_pin_ids_[module][net].push_back(src_pin); + + /* Update fast look-up for nets */ + net_lookup_[module][src_module][src_instance_id][src_port][src_pin] = net; +} + +/* Add a sink to a net in the connection graph */ +void ModuleManager::add_module_net_sink(const ModuleId& module, const ModuleNetId& net, + const ModuleId& sink_module, const size_t& instance_id, + const ModulePortId& sink_port, const size_t& sink_pin) { + /* Validate the module and net id */ + VTR_ASSERT(valid_module_net_id(module, net)); + + /* Validate the source module */ + VTR_ASSERT(valid_module_id(sink_module)); + net_sink_module_ids_[module][net].push_back(sink_module); + + /* if it has the same id as module, our instance id will be by default 0 */ + size_t sink_instance_id = instance_id; + if (sink_module == module) { + sink_instance_id = 0; + net_sink_instance_ids_[module][net].push_back(sink_instance_id); + } else { + /* Check the instance id of the src module */ + VTR_ASSERT (sink_instance_id < num_instance(module, sink_module)); + net_sink_instance_ids_[module][net].push_back(sink_instance_id); + } + + /* Validate the port exists in the sink module */ + VTR_ASSERT(valid_module_port_id(sink_module, sink_port)); + net_sink_port_ids_[module][net].push_back(sink_port); + + /* Validate the pin id is in the range of the port width */ + VTR_ASSERT(sink_pin < module_port(sink_module, sink_port).get_width()); + net_sink_pin_ids_[module][net].push_back(sink_pin); + + /* Update fast look-up for nets */ + net_lookup_[module][sink_module][sink_instance_id][sink_port][sink_pin] = net; } /****************************************************************************** @@ -250,6 +371,13 @@ bool ModuleManager::valid_module_port_id(const ModuleId& module, const ModulePor return ( size_t(port) < port_ids_[module].size() ) && ( port == port_ids_[module][port] ); } +bool ModuleManager::valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const { + if (false == valid_module_id(module)) { + return false; + } + return ( size_t(net) < net_ids_[module].size() ) && ( net == net_ids_[module][net] ); +} + void ModuleManager::invalidate_name2id_map() { name_id_map_.clear(); } @@ -257,3 +385,7 @@ void ModuleManager::invalidate_name2id_map() { void ModuleManager::invalidate_port_lookup() { port_lookup_.clear(); } + +void ModuleManager::invalidate_net_lookup() { + net_lookup_.clear(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index c99d3ffa1..70c7c46bf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -68,19 +68,33 @@ class ModuleManager { void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); /* Add a child module to a parent module */ void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); + /* Add a net to the connection graph of the module */ + ModuleNetId create_module_net(const ModuleId& module); + /* Add a source to a net in the connection graph */ + void add_module_net_source(const ModuleId& module, const ModuleNetId& net, + const ModuleId& src_module, const size_t& instance_id, + const ModulePortId& src_port, const size_t& src_pin); + /* Add a sink to a net in the connection graph */ + void add_module_net_sink(const ModuleId& module, const ModuleNetId& net, + const ModuleId& sink_module, const size_t& instance_id, + const ModulePortId& sink_port, const size_t& sink_pin); public: /* Public validators/invalidators */ bool valid_module_id(const ModuleId& module) const; bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; + bool valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const; private: /* Private validators/invalidators */ void invalidate_name2id_map(); void invalidate_port_lookup(); + void invalidate_net_lookup(); private: /* Internal data */ + /* Module-level data */ vtr::vector ids_; /* Unique identifier for each Module */ vtr::vector names_; /* Unique identifier for each Module */ vtr::vector> parents_; /* Parent modules that include the module */ vtr::vector> children_; /* Child modules that this module contain */ vtr::vector> num_child_instances_; /* Number of children instance in each child module */ + /* Port-level data */ vtr::vector> port_ids_; /* List of ports for each Module */ vtr::vector> ports_; /* List of ports for each Module */ vtr::vector> port_types_; /* Type of ports */ @@ -88,11 +102,31 @@ class ModuleManager { vtr::vector> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: reg */ vtr::vector> port_preproc_flags_; /* If a port is available only when a pre-processing flag is enabled. This is to record the pre-processing flags */ + /* Graph-level data: + * We use nets to model the connection between pins of modules and instances. + * To avoid large memory footprint, we do NOT create pins, + * To enable fast look-up on pins, we create a fast look-up + */ + vtr::vector> net_ids_; /* List of nets for each Module */ + vtr::vector> net_names_; /* Name of net */ + vtr::vector>> net_src_module_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_src_instance_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_src_port_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_src_pin_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_sink_module_ids_; /* Pin ids that the net drives */ + vtr::vector>> net_sink_instance_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_sink_port_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_sink_pin_ids_; /* Pin ids that drive the net */ + /* fast look-up for module */ std::map name_id_map_; /* fast look-up for ports */ typedef vtr::vector>> PortLookup; mutable PortLookup port_lookup_; /* [module_ids][port_types][port_ids] */ + + /* fast look-up for nets */ + typedef vtr::vector>>>> NetLookup; + mutable NetLookup net_lookup_; /* [module_ids][module_ids][instance_ids][port_ids][pin_ids] */ }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h index 798cc67f2..37509ebac 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h @@ -11,9 +11,13 @@ /* Strong Ids for ModuleManager */ struct module_id_tag; struct module_port_id_tag; +struct module_pin_id_tag; +struct module_net_id_tag; typedef vtr::StrongId ModuleId; typedef vtr::StrongId ModulePortId; +typedef vtr::StrongId ModulePinId; +typedef vtr::StrongId ModuleNetId; class ModuleManager; From edad988ebb0f19c793ce630a8d84af15671c4e59 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 9 Oct 2019 21:14:30 -0600 Subject: [PATCH 278/482] add net accessor and mutators to module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 49 ++++++++++++++++++- .../vpr/SRC/fpga_x2p/base/module_manager.h | 9 ++++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 6f0bc0e69..853ca2643 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -120,6 +120,42 @@ std::string ModuleManager::port_preproc_flag(const ModuleId& module, const Modul return port_preproc_flags_[module][port]; } + +/* Find a net from an instance of a module */ +ModuleNetId ModuleManager::module_instance_port_net(const ModuleId& parent_module, + const ModuleId& child_module, const size_t& child_instance, + const ModulePortId& child_port, const size_t& child_pin) const { + /* Validate parent_module */ + VTR_ASSERT(valid_module_id(parent_module)); + + /* Validate child_module */ + VTR_ASSERT(valid_module_id(child_module)); + + /* Validate instance id */ + if (child_module == parent_module) { + /* Assume a default instance id as zero */ + VTR_ASSERT(0 == child_instance); + } else { + VTR_ASSERT(child_instance < num_instance(parent_module, child_module)); + } + + /* Validate child_port */ + VTR_ASSERT(valid_module_port_id(child_module, child_port)); + + /* Validate child_pin */ + VTR_ASSERT(child_pin < module_port(child_module, child_port).get_width()); + + return net_lookup_[parent_module][child_module][child_instance][child_port][child_pin]; +} + +/* Find the name of net */ +std::string ModuleManager::net_name(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_names_[module][net]; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ @@ -196,7 +232,7 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, /* Update fast look-up for nets */ VTR_ASSERT_SAFE(1 == net_lookup_[module][module].size()); - net_lookup_[module][module][0][port].resize(port_info.get_width()); + net_lookup_[module][module][0][port].resize(port_info.get_width(), ModuleNetId::INVALID()); return port; } @@ -261,7 +297,7 @@ void ModuleManager::add_child_module(const ModuleId& parent_module, const Module /* Find the ports for the child module and update the fast look-up */ for (ModulePortId child_port : port_ids_[child_module]) { net_lookup_[parent_module][child_module].emplace_back(); - net_lookup_[parent_module][child_module][instance_id][child_port].resize(ports_[child_module][child_port].get_width()); + net_lookup_[parent_module][child_module][instance_id][child_port].resize(ports_[child_module][child_port].get_width(), ModuleNetId::INVALID()); } } @@ -289,6 +325,15 @@ ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { return net; } +/* Set the name of net */ +void ModuleManager::set_net_name(const ModuleId& module, const ModuleNetId& net, + const std::string& name) { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + net_names_[module][net] = name; +} + /* Add a source to a net in the connection graph */ void ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNetId& net, const ModuleId& src_module, const size_t& instance_id, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 70c7c46bf..99858cd7a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -52,6 +52,12 @@ class ModuleManager { bool port_is_register(const ModuleId& module, const ModulePortId& port) const; /* Return the pre-processing flag of a port */ std::string port_preproc_flag(const ModuleId& module, const ModulePortId& port) const; + /* Find a net from an instance of a module */ + ModuleNetId module_instance_port_net(const ModuleId& parent_module, + const ModuleId& child_module, const size_t& child_instance, + const ModulePortId& child_port, const size_t& child_pin) const; + /* Find the name of net */ + std::string net_name(const ModuleId& module, const ModuleNetId& net) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); @@ -70,6 +76,9 @@ class ModuleManager { void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); /* Add a net to the connection graph of the module */ ModuleNetId create_module_net(const ModuleId& module); + /* Set the name of net */ + void set_net_name(const ModuleId& module, const ModuleNetId& net, + const std::string& name); /* Add a source to a net in the connection graph */ void add_module_net_source(const ModuleId& module, const ModuleNetId& net, const ModuleId& src_module, const size_t& instance_id, From e5956467fd9d9e60d27813604c8ab06723decfcc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Oct 2019 14:43:32 -0600 Subject: [PATCH 279/482] developing verilog writer for modules --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 116 +++++++++++++++++- .../vpr/SRC/fpga_x2p/base/module_manager.h | 36 ++++++ .../verilog/verilog_module_writer.cpp | 85 +++++++++++++ .../fpga_x2p/verilog/verilog_module_writer.h | 15 +++ .../fpga_x2p/verilog/verilog_writer_utils.h | 1 + 5 files changed, 252 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 853ca2643..f7e7b1e6c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -2,6 +2,7 @@ * Memember functions for data structure ModuleManager ******************************************************************************/ #include +#include #include #include "vtr_assert.h" @@ -12,6 +13,49 @@ * Public Constructors ******************************************************************************/ +/************************************************** + * Public Accessors : Aggregates + *************************************************/ +/* Find all the modules */ +ModuleManager::module_range ModuleManager::modules() const { + return vtr::make_range(ids_.begin(), ids_.end()); +} + +/* Find all the nets belonging to a module */ +ModuleManager::module_net_range ModuleManager::module_nets(const ModuleId& module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module)); + return vtr::make_range(net_ids_[module].begin(), net_ids_[module].end()); +} + +/* Find all the child modules under a parent module */ +std::vector ModuleManager::child_modules(const ModuleId& parent_module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(parent_module)); + return children_[parent_module]; +} + +/* Find all the instances under a parent module */ +std::vector ModuleManager::child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(parent_module)); + /* Ensure that the child module is in the child list of parent module */ + size_t child_index = children_[parent_module].size(); + for (size_t i = 0; i < children_[parent_module].size(); ++i) { + if (child_module == children_[parent_module][i]) { + child_index = i; + break; + } + } + VTR_ASSERT(child_index != children_[parent_module].size()); + + /* Create a vector, with sequentially increasing numbers */ + std::vector instance_range(num_child_instances_[parent_module][child_index]); + std::iota(instance_range.begin(), instance_range.end(), 0); + + return instance_range; +} + /****************************************************************************** * Public Accessors ******************************************************************************/ @@ -20,6 +64,13 @@ size_t ModuleManager::num_modules() const { return ids_.size(); } +/* Return number of net of a module */ +size_t ModuleManager::num_nets(const ModuleId& module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module)); + return net_ids_[module].size(); +} + /* Find the name of a module */ std::string ModuleManager::module_name(const ModuleId& module_id) const { /* Validate the module_id */ @@ -120,7 +171,6 @@ std::string ModuleManager::port_preproc_flag(const ModuleId& module, const Modul return port_preproc_flags_[module][port]; } - /* Find a net from an instance of a module */ ModuleNetId ModuleManager::module_instance_port_net(const ModuleId& parent_module, const ModuleId& child_module, const size_t& child_instance, @@ -156,6 +206,70 @@ std::string ModuleManager::net_name(const ModuleId& module, const ModuleNetId& n return net_names_[module][net]; } +/* Find the source modules of a net */ +std::vector ModuleManager::net_source_modules(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_src_module_ids_[module][net]; +} + +/* Find the ids of source instances of a net */ +std::vector ModuleManager::net_source_instances(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_src_instance_ids_[module][net]; +} + +/* Find the source ports of a net */ +std::vector ModuleManager::net_source_ports(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_src_port_ids_[module][net]; +} + +/* Find the source pin indices of a net */ +std::vector ModuleManager::net_source_pins(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_src_pin_ids_[module][net]; +} + +/* Find the sink modules of a net */ +std::vector ModuleManager::net_sink_modules(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_sink_module_ids_[module][net]; +} + +/* Find the ids of sink instances of a net */ +std::vector ModuleManager::net_sink_instances(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_sink_instance_ids_[module][net]; +} + +/* Find the sink ports of a net */ +std::vector ModuleManager::net_sink_ports(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_sink_port_ids_[module][net]; +} + +/* Find the sink pin indices of a net */ +std::vector ModuleManager::net_sink_pins(const ModuleId& module, const ModuleNetId& net) const { + /* Validate module net */ + VTR_ASSERT(valid_module_net_id(module, net)); + + return net_sink_pin_ids_[module][net]; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 99858cd7a..5204f0de3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -32,9 +32,29 @@ class ModuleManager { MODULE_CLOCK_PORT, NUM_MODULE_PORT_TYPES }; + public: /* Public Constructors */ + + public: /* Types and ranges */ + typedef vtr::vector::const_iterator module_iterator; + typedef vtr::vector::const_iterator module_net_iterator; + + typedef vtr::Range module_range; + typedef vtr::Range module_net_range; + + public: /* Public aggregators */ + /* Find all the modules */ + module_range modules() const; + /* Find all the nets belonging to a module */ + module_net_range module_nets(const ModuleId& module) const; + /* Find all the child modules under a parent module */ + std::vector child_modules(const ModuleId& parent_module) const; + /* Find all the instances under a parent module */ + std::vector child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const; + public: /* Public accessors */ size_t num_modules() const; + size_t num_nets(const ModuleId& module) const; std::string module_name(const ModuleId& module_id) const; std::string module_port_type_str(const enum e_module_port_type& port_type) const; std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; @@ -58,6 +78,22 @@ class ModuleManager { const ModulePortId& child_port, const size_t& child_pin) const; /* Find the name of net */ std::string net_name(const ModuleId& module, const ModuleNetId& net) const; + /* Find the source modules of a net */ + std::vector net_source_modules(const ModuleId& module, const ModuleNetId& net) const; + /* Find the ids of source instances of a net */ + std::vector net_source_instances(const ModuleId& module, const ModuleNetId& net) const; + /* Find the source ports of a net */ + std::vector net_source_ports(const ModuleId& module, const ModuleNetId& net) const; + /* Find the source pin indices of a net */ + std::vector net_source_pins(const ModuleId& module, const ModuleNetId& net) const; + /* Find the sink modules of a net */ + std::vector net_sink_modules(const ModuleId& module, const ModuleNetId& net) const; + /* Find the ids of sink instances of a net */ + std::vector net_sink_instances(const ModuleId& module, const ModuleNetId& net) const; + /* Find the sink ports of a net */ + std::vector net_sink_ports(const ModuleId& module, const ModuleNetId& net) const; + /* Find the sink pin indices of a net */ + std::vector net_sink_pins(const ModuleId& module, const ModuleNetId& net) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp new file mode 100644 index 000000000..c54d73619 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -0,0 +1,85 @@ +/******************************************************************** + * This file includes functions to write a Verilog module + * based on its definition in Module Manager + * + * Note that Verilog writer functions are just an outputter for the + * module definition. + * You should NOT modify any content of the module manager + * Please use const keyword to restrict this! + *******************************************************************/ +#include "vtr_assert.h" +#include "fpga_x2p_utils.h" +#include "verilog_writer_utils.h" +#include "verilog_module_writer.h" + +/******************************************************************** + * Collect all the nets that are going to be local wires + * And organize it in a vector of ports + * Verilog wire writter function will use the output of this function + * to write up local wire declaration in Verilog format + * + * Here is the strategy to identify local wires: + * Iterate over the nets inside the module. + * A net is a local wire if it connects between two instances, + * This is valid when all the sinks of the net are pins/ports of instances + *******************************************************************/ +static +std::vector find_verilog_module_local_wires(const ModuleManager& module_manager, + const ModuleId& module_id) { + std::vector local_wire_ports; + + /* Find local wires between instances */ + for (ModuleNetId module_net : module_manager.module_nets(module_id)) { + /* A flag to identify local wire */ + bool is_local_wire = false; + + /* Each net must only one 1 source */ + VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size()); + + /* Check if source module is the module itself */ + if (module_id != module_manager.net_source_modules(module_id, module_net)[0]) { + is_local_wire = true; + } + + /* Check all the sink modules of the net */ + for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { + if (module_id == sink_module) { + is_local_wire = false; + } + } + + /* TODO: Push the Verilog port the list, try to combine the ports if we can */ + } + + return local_wire_ports; +} + +/******************************************************************** + * Write a Verilog module to a file + * This is a key function, maybe most frequently called in our Verilog writer + * Note that file stream must be valid + *******************************************************************/ +void writer_verilog_module_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id) { + /* Ensure a valid file stream */ + check_file_handler(fp); + + /* Ensure we have a valid module_id */ + VTR_ASSERT(module_manager.valid_module_id(module_id)); + + /* Print module declaration */ + print_verilog_module_declaration(fp, module_manager, module_id); + + /* TODO: Print internal wires */ + + /* TODO: Print instances */ + for (ModuleId child_module : module_manager.child_modules(module_id)) { + for (size_t instance : module_manager.child_module_instances(module_id, child_module)) { + /* Print an instance */ + } + } + + /* Print an end for the module */ + print_verilog_module_end(fp, module_manager.module_name(module_id)); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h new file mode 100644 index 000000000..bb7b401fb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h @@ -0,0 +1,15 @@ +/******************************************************************** + * Header file for verilog_module_writer.cpp + *******************************************************************/ + +#ifndef VERILOG_MODULE_WRITER_H +#define VERILOG_MODULE_WRITER_H + +#include +#include "module_manager.h" + +void writer_verilog_module_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 5e390ed02..1840f447f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -7,6 +7,7 @@ #define VERILOG_WRITER_UTILS_H #include +#include "verilog_global.h" #include "device_port.h" #include "module_manager.h" From f2b3341d87e8f2eb1e0853583634b25af98e7cd5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Oct 2019 20:09:55 -0600 Subject: [PATCH 280/482] developing verilog writer for generic module graph --- vpr7_x2p/libarchfpga/SRC/device_port.cpp | 24 +- vpr7_x2p/libarchfpga/SRC/device_port.h | 2 + .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 76 ++++-- .../vpr/SRC/fpga_x2p/base/module_manager.h | 59 +++-- .../SRC/fpga_x2p/base/module_manager_fwd.h | 4 + .../fpga_x2p/base/module_manager_utils.cpp | 28 +++ .../SRC/fpga_x2p/base/module_manager_utils.h | 4 +- .../verilog/verilog_module_writer.cpp | 230 +++++++++++++++--- .../fpga_x2p/verilog/verilog_module_writer.h | 7 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 31 +++ .../fpga_x2p/verilog/verilog_writer_utils.h | 6 + 11 files changed, 395 insertions(+), 76 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.cpp b/vpr7_x2p/libarchfpga/SRC/device_port.cpp index 38241f198..04ee4facf 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.cpp +++ b/vpr7_x2p/libarchfpga/SRC/device_port.cpp @@ -1,6 +1,8 @@ +#include #include #include -#include + +#include "vtr_assert.h" #include "device_port.h" @@ -63,6 +65,24 @@ std::string BasicPort::get_name() const { return name_; } +/* Make a range of the pin indices */ +std::vector BasicPort::pins() const { + std::vector pin_indices; + + /* Return if the port is invalid */ + if (false == is_valid()) { + return pin_indices; /* Return an empty vector */ + } + /* For valid ports, create a vector whose length is the port width */ + pin_indices.resize(get_width()); + /* Fill in an incremental sequence */ + std::iota(pin_indices.begin(), pin_indices.end(), get_lsb()); + /* Ensure the last one is MSB */ + VTR_ASSERT(get_msb() == pin_indices.back()); + + return pin_indices; +} + /* Mutators */ /* copy */ void BasicPort::set(const BasicPort& basic_port) { @@ -188,7 +208,7 @@ void BasicPort::reset() { void BasicPort::combine(const BasicPort& port) { /* LSB follows the current LSB */ /* MSB increases */ - assert( 0 < port.get_width() ); /* Make sure port is valid */ + VTR_ASSERT(0 < port.get_width() ); /* Make sure port is valid */ /* If current port is invalid, we do not combine */ if (0 == get_width()) { return; diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.h b/vpr7_x2p/libarchfpga/SRC/device_port.h index 21666dcb4..eb4a91b86 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.h +++ b/vpr7_x2p/libarchfpga/SRC/device_port.h @@ -6,6 +6,7 @@ #define DEVICE_PORT_H #include +#include /* A basic port */ class BasicPort { @@ -22,6 +23,7 @@ class BasicPort { size_t get_lsb() const; /* get the LSB */ std::string get_name() const; /* get the name */ bool is_valid() const; /* check if port size is valid > 0 */ + std::vector pins() const; /* Make a range of the pin indices */ public: /* Mutators */ void set(const BasicPort& basic_port); /* copy */ void set_name(const std::string& name); /* set the port LSB and MSB */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index f7e7b1e6c..41a5f723e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -56,6 +56,20 @@ std::vector ModuleManager::child_module_instances(const ModuleId& parent return instance_range; } +/* Find the source ids of modules */ +ModuleManager::module_net_src_range ModuleManager::module_net_sources(const ModuleId& module, const ModuleNetId& net) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_net_id(module, net)); + return vtr::make_range(net_src_ids_[module][net].begin(), net_src_ids_[module][net].end()); +} + +/* Find the sink ids of modules */ +ModuleManager::module_net_sink_range ModuleManager::module_net_sinks(const ModuleId& module, const ModuleNetId& net) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_net_id(module, net)); + return vtr::make_range(net_sink_ids_[module][net].begin(), net_sink_ids_[module][net].end()); +} + /****************************************************************************** * Public Accessors ******************************************************************************/ @@ -101,6 +115,24 @@ std::vector ModuleManager::module_ports_by_type(const ModuleId& modul return ports; } +/* Find a list of port ids of a module by a given types */ +std::vector ModuleManager::module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module_id)); + + std::vector port_ids; + for (const auto& port : port_ids_[module_id]) { + /* Skip unmatched ports */ + if (port_type != port_types_[module_id][port]) { + continue; + } + port_ids.push_back(port_ids_[module_id][port]); + } + + return port_ids; +} + + /* Find a port of a module by a given name */ ModulePortId ModuleManager::find_module_port(const ModuleId& module_id, const std::string& port_name) const { /* Validate the module id */ @@ -207,7 +239,7 @@ std::string ModuleManager::net_name(const ModuleId& module, const ModuleNetId& n } /* Find the source modules of a net */ -std::vector ModuleManager::net_source_modules(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_source_modules(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -215,7 +247,7 @@ std::vector ModuleManager::net_source_modules(const ModuleId& module, } /* Find the ids of source instances of a net */ -std::vector ModuleManager::net_source_instances(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_source_instances(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -223,7 +255,7 @@ std::vector ModuleManager::net_source_instances(const ModuleId& module, } /* Find the source ports of a net */ -std::vector ModuleManager::net_source_ports(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_source_ports(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -231,7 +263,7 @@ std::vector ModuleManager::net_source_ports(const ModuleId& module } /* Find the source pin indices of a net */ -std::vector ModuleManager::net_source_pins(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_source_pins(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -239,7 +271,7 @@ std::vector ModuleManager::net_source_pins(const ModuleId& module, const } /* Find the sink modules of a net */ -std::vector ModuleManager::net_sink_modules(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_sink_modules(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -247,7 +279,7 @@ std::vector ModuleManager::net_sink_modules(const ModuleId& module, co } /* Find the ids of sink instances of a net */ -std::vector ModuleManager::net_sink_instances(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_sink_instances(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -255,7 +287,7 @@ std::vector ModuleManager::net_sink_instances(const ModuleId& module, co } /* Find the sink ports of a net */ -std::vector ModuleManager::net_sink_ports(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_sink_ports(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -263,7 +295,7 @@ std::vector ModuleManager::net_sink_ports(const ModuleId& module, } /* Find the sink pin indices of a net */ -std::vector ModuleManager::net_sink_pins(const ModuleId& module, const ModuleNetId& net) const { +vtr::vector ModuleManager::net_sink_pins(const ModuleId& module, const ModuleNetId& net) const { /* Validate module net */ VTR_ASSERT(valid_module_net_id(module, net)); @@ -300,11 +332,13 @@ ModuleId ModuleManager::add_module(const std::string& name) { net_ids_.emplace_back(); net_names_.emplace_back(); + net_src_ids_.emplace_back(); net_src_module_ids_.emplace_back(); net_src_instance_ids_.emplace_back(); net_src_port_ids_.emplace_back(); net_src_pin_ids_.emplace_back(); + net_sink_ids_.emplace_back(); net_sink_module_ids_.emplace_back(); net_sink_instance_ids_.emplace_back(); net_sink_port_ids_.emplace_back(); @@ -426,11 +460,13 @@ ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { /* Allocate net-related data structures */ net_names_[module].emplace_back(); + net_src_ids_[module].emplace_back(); net_src_module_ids_[module].emplace_back(); net_src_instance_ids_[module].emplace_back(); net_src_port_ids_[module].emplace_back(); net_src_pin_ids_[module].emplace_back(); + net_sink_ids_[module].emplace_back(); net_sink_module_ids_[module].emplace_back(); net_sink_instance_ids_[module].emplace_back(); net_sink_port_ids_[module].emplace_back(); @@ -449,12 +485,16 @@ void ModuleManager::set_net_name(const ModuleId& module, const ModuleNetId& net, } /* Add a source to a net in the connection graph */ -void ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNetId& net, - const ModuleId& src_module, const size_t& instance_id, - const ModulePortId& src_port, const size_t& src_pin) { +ModuleNetSrcId ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNetId& net, + const ModuleId& src_module, const size_t& instance_id, + const ModulePortId& src_port, const size_t& src_pin) { /* Validate the module and net id */ VTR_ASSERT(valid_module_net_id(module, net)); + /* Create a new id for src node */ + ModuleNetSrcId net_src = ModuleNetSrcId(net_src_ids_[module][net].size()); + net_src_ids_[module][net].push_back(net_src); + /* Validate the source module */ VTR_ASSERT(valid_module_id(src_module)); net_src_module_ids_[module][net].push_back(src_module); @@ -480,15 +520,21 @@ void ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNe /* Update fast look-up for nets */ net_lookup_[module][src_module][src_instance_id][src_port][src_pin] = net; + + return net_src; } /* Add a sink to a net in the connection graph */ -void ModuleManager::add_module_net_sink(const ModuleId& module, const ModuleNetId& net, - const ModuleId& sink_module, const size_t& instance_id, - const ModulePortId& sink_port, const size_t& sink_pin) { +ModuleNetSinkId ModuleManager::add_module_net_sink(const ModuleId& module, const ModuleNetId& net, + const ModuleId& sink_module, const size_t& instance_id, + const ModulePortId& sink_port, const size_t& sink_pin) { /* Validate the module and net id */ VTR_ASSERT(valid_module_net_id(module, net)); + /* Create a new id for sink node */ + ModuleNetSinkId net_sink = ModuleNetSinkId(net_sink_ids_[module][net].size()); + net_sink_ids_[module][net].push_back(net_sink); + /* Validate the source module */ VTR_ASSERT(valid_module_id(sink_module)); net_sink_module_ids_[module][net].push_back(sink_module); @@ -514,6 +560,8 @@ void ModuleManager::add_module_net_sink(const ModuleId& module, const ModuleNetI /* Update fast look-up for nets */ net_lookup_[module][sink_module][sink_instance_id][sink_port][sink_pin] = net; + + return net_sink; } /****************************************************************************** diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 5204f0de3..6bba3a67a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -38,9 +38,13 @@ class ModuleManager { public: /* Types and ranges */ typedef vtr::vector::const_iterator module_iterator; typedef vtr::vector::const_iterator module_net_iterator; + typedef vtr::vector::const_iterator module_net_src_iterator; + typedef vtr::vector::const_iterator module_net_sink_iterator; typedef vtr::Range module_range; typedef vtr::Range module_net_range; + typedef vtr::Range module_net_src_range; + typedef vtr::Range module_net_sink_range; public: /* Public aggregators */ /* Find all the modules */ @@ -51,6 +55,10 @@ class ModuleManager { std::vector child_modules(const ModuleId& parent_module) const; /* Find all the instances under a parent module */ std::vector child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const; + /* Find the source ids of modules */ + module_net_src_range module_net_sources(const ModuleId& module, const ModuleNetId& net) const; + /* Find the sink ids of modules */ + module_net_sink_range module_net_sinks(const ModuleId& module, const ModuleNetId& net) const; public: /* Public accessors */ size_t num_modules() const; @@ -58,6 +66,7 @@ class ModuleManager { std::string module_name(const ModuleId& module_id) const; std::string module_port_type_str(const enum e_module_port_type& port_type) const; std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; + std::vector module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; /* Find a port of a module by a given name */ ModulePortId find_module_port(const ModuleId& module_id, const std::string& port_name) const; /* Find the Port information with a given port id */ @@ -79,21 +88,22 @@ class ModuleManager { /* Find the name of net */ std::string net_name(const ModuleId& module, const ModuleNetId& net) const; /* Find the source modules of a net */ - std::vector net_source_modules(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_source_modules(const ModuleId& module, const ModuleNetId& net) const; /* Find the ids of source instances of a net */ - std::vector net_source_instances(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_source_instances(const ModuleId& module, const ModuleNetId& net) const; /* Find the source ports of a net */ - std::vector net_source_ports(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_source_ports(const ModuleId& module, const ModuleNetId& net) const; /* Find the source pin indices of a net */ - std::vector net_source_pins(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_source_pins(const ModuleId& module, const ModuleNetId& net) const; + /* Find the sink modules of a net */ - std::vector net_sink_modules(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_sink_modules(const ModuleId& module, const ModuleNetId& net) const; /* Find the ids of sink instances of a net */ - std::vector net_sink_instances(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_sink_instances(const ModuleId& module, const ModuleNetId& net) const; /* Find the sink ports of a net */ - std::vector net_sink_ports(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_sink_ports(const ModuleId& module, const ModuleNetId& net) const; /* Find the sink pin indices of a net */ - std::vector net_sink_pins(const ModuleId& module, const ModuleNetId& net) const; + vtr::vector net_sink_pins(const ModuleId& module, const ModuleNetId& net) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); @@ -116,13 +126,13 @@ class ModuleManager { void set_net_name(const ModuleId& module, const ModuleNetId& net, const std::string& name); /* Add a source to a net in the connection graph */ - void add_module_net_source(const ModuleId& module, const ModuleNetId& net, - const ModuleId& src_module, const size_t& instance_id, - const ModulePortId& src_port, const size_t& src_pin); + ModuleNetSrcId add_module_net_source(const ModuleId& module, const ModuleNetId& net, + const ModuleId& src_module, const size_t& instance_id, + const ModulePortId& src_port, const size_t& src_pin); /* Add a sink to a net in the connection graph */ - void add_module_net_sink(const ModuleId& module, const ModuleNetId& net, - const ModuleId& sink_module, const size_t& instance_id, - const ModulePortId& sink_port, const size_t& sink_pin); + ModuleNetSinkId add_module_net_sink(const ModuleId& module, const ModuleNetId& net, + const ModuleId& sink_module, const size_t& instance_id, + const ModulePortId& sink_port, const size_t& sink_pin); public: /* Public validators/invalidators */ bool valid_module_id(const ModuleId& module) const; bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; @@ -154,14 +164,19 @@ class ModuleManager { */ vtr::vector> net_ids_; /* List of nets for each Module */ vtr::vector> net_names_; /* Name of net */ - vtr::vector>> net_src_module_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_src_instance_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_src_port_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_src_pin_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_sink_module_ids_; /* Pin ids that the net drives */ - vtr::vector>> net_sink_instance_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_sink_port_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_sink_pin_ids_; /* Pin ids that drive the net */ + + vtr::vector>> net_src_ids_; /* Unique id of the source that drive the net */ + vtr::vector>> net_src_module_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_src_instance_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_src_port_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_src_pin_ids_; /* Pin ids that drive the net */ + + + vtr::vector>> net_sink_ids_; /* Unique ids of the sink that the net drives */ + vtr::vector>> net_sink_module_ids_; /* Pin ids that the net drives */ + vtr::vector>> net_sink_instance_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_sink_port_ids_; /* Pin ids that drive the net */ + vtr::vector>> net_sink_pin_ids_; /* Pin ids that drive the net */ /* fast look-up for module */ std::map name_id_map_; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h index 37509ebac..bffc2df6a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h @@ -13,11 +13,15 @@ struct module_id_tag; struct module_port_id_tag; struct module_pin_id_tag; struct module_net_id_tag; +struct module_net_src_id_tag; +struct module_net_sink_id_tag; typedef vtr::StrongId ModuleId; typedef vtr::StrongId ModulePortId; typedef vtr::StrongId ModulePinId; typedef vtr::StrongId ModuleNetId; +typedef vtr::StrongId ModuleNetSrcId; +typedef vtr::StrongId ModuleNetSinkId; class ModuleManager; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 9f744bd24..f24683bba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -260,3 +260,31 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, } } +/******************************************************************** + * Identify if a net is a local wire inside a module: + * A net is a local wire if it connects between two instances, + * It means that any of its source and sink modules should not include current module_id + *******************************************************************/ +bool module_net_is_local_wire(const ModuleManager& module_manager, + const ModuleId& module_id, const ModuleNetId& module_net) { + /* A flag to identify local wire */ + /* Check all the sink modules of the net, + * if we have a source module is the current module, this is not local wire + */ + for (ModuleId src_module : module_manager.net_source_modules(module_id, module_net)) { + if (module_id == src_module) { + /* Here, this is not a local wire */ + return false; + } + } + + /* Check all the sink modules of the net */ + for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { + if (module_id == sink_module) { + /* Here, this is not a local wire */ + return false; + } + } + + return true; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index cbdc04891..ce86a1f55 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -43,5 +43,7 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, const ModuleId& module_id, t_pb_type* cur_pb_type); -#endif +bool module_net_is_local_wire(const ModuleManager& module_manager, + const ModuleId& module_id, const ModuleNetId& module_net); +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index c54d73619..7d8256744 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -9,49 +9,192 @@ *******************************************************************/ #include "vtr_assert.h" #include "fpga_x2p_utils.h" +#include "module_manager_utils.h" #include "verilog_writer_utils.h" #include "verilog_module_writer.h" /******************************************************************** - * Collect all the nets that are going to be local wires + * Name a net for a local wire for a verilog module + * 1. If this is a local wire, name it after the __ + * 2. If this is not a local wire, name it after the port name of parent module + * + * In addition, it will assign the pin index as well + * + * Restriction: this function requires each net has single driver + * which is definitely always true in circuits. + *******************************************************************/ +static +BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manager, + const ModuleId& module_id, + const ModuleNetId& module_net) { + /* Check all the sink modules of the net, + * if we have a source module is the current module, this is not local wire + */ + for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) { + if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) { + /* Here, this is not a local wire, return the port name of the src_port */ + ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id]; + size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id]; + return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index); + } + } + + /* Check all the sink modules of the net */ + for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) { + if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) { + /* Here, this is not a local wire, return the port name of the sink_port */ + ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id]; + size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id]; + return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index); + } + } + + /* Reach here, this is a local wire */ + std::string net_name; + + /* Each net must only one 1 source */ + VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size()); + + /* Get the source module */ + ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)]; + /* Get the instance id */ + size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)]; + /* Get the port id */ + ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)]; + /* Get the pin id */ + size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)]; + + net_name = module_manager.module_name(net_src_module); + net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_"); + net_name += module_manager.module_port(module_id, net_src_port).get_name(); + + return BasicPort(net_name, net_src_pin, net_src_pin); +} + +/******************************************************************** + * Find all the nets that are going to be local wires * And organize it in a vector of ports * Verilog wire writter function will use the output of this function * to write up local wire declaration in Verilog format - * - * Here is the strategy to identify local wires: - * Iterate over the nets inside the module. - * A net is a local wire if it connects between two instances, - * This is valid when all the sinks of the net are pins/ports of instances *******************************************************************/ static std::vector find_verilog_module_local_wires(const ModuleManager& module_manager, const ModuleId& module_id) { - std::vector local_wire_ports; - - /* Find local wires between instances */ + std::vector local_wires; + + /* Local wires come from the child modules */ for (ModuleNetId module_net : module_manager.module_nets(module_id)) { - /* A flag to identify local wire */ - bool is_local_wire = false; - - /* Each net must only one 1 source */ - VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size()); - - /* Check if source module is the module itself */ - if (module_id != module_manager.net_source_modules(module_id, module_net)[0]) { - is_local_wire = true; + /* We only care local wires */ + if (false == module_net_is_local_wire(module_manager, module_id, module_net)) { + continue; } - - /* Check all the sink modules of the net */ - for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { - if (module_id == sink_module) { - is_local_wire = false; - } + /* Find the name for this local wire */ + BasicPort local_wire_candidate = generate_verilog_port_for_module_net(module_manager, module_id, module_net); + /* Try to find a port in the list that can absorb the current local wire */ + bool merged = false; + for (BasicPort& local_wire : local_wires) { + /* check if the candidate can be combined to an existing local wire */ + if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) { + /* Merge the ports */ + local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate); + merged = true; + break; + } + } + /* If not merged, push the port to the list */ + if (false == merged) { + local_wires.push_back(local_wire_candidate); } - - /* TODO: Push the Verilog port the list, try to combine the ports if we can */ } - return local_wire_ports; + return local_wires; +} + +/******************************************************************** + * Write a Verilog instance to a file + * This function will name the input and output connections to + * the inputs/output or local wires available in the parent module + * + * Parent_module + * +-----------------------------+ + * | | + * | +--------------+ | + * | | | | + * | | child_module | | + * | | [instance] | | + * | +--------------+ | + * | | + * +-----------------------------+ + * + *******************************************************************/ +static +void write_verilog_instance_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const ModuleId& child_module, + const size_t& instance_id, + const bool& use_explicit_port_map) { + /* Ensure a valid file stream */ + check_file_handler(fp); + + /* Print module name */ + fp << "\t" << module_manager.module_name(child_module) << " "; + /* Print instance name, _ */ + fp << module_manager.module_name(child_module) << "_" << module_manager.num_instance(parent_module, child_module) << "_" << " (" << std::endl; + + /* Print each port with/without explicit port map */ + /* port type2type mapping */ + std::map port_type2type_map; + port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT; + + /* Port sequence: global, inout, input, output and clock ports, */ + size_t port_cnt = 0; + for (const auto& kv : port_type2type_map) { + for (const ModulePortId& child_port_id : module_manager.module_port_ids_by_type(child_module, kv.first)) { + BasicPort child_port = module_manager.module_port(child_module, child_port_id); + if (0 != port_cnt) { + /* Do not dump a comma for the first port */ + fp << "," << std::endl; + } + /* Print port */ + fp << "\t\t"; + /* if explicit port map is required, output the port name */ + if (true == use_explicit_port_map) { + fp << "." << child_port.get_name() << "("; + } + + /* Create the port name and width to be used by the instance */ + std::vector instance_ports; + for (size_t child_pin : child_port.pins()) { + /* Find the net linked to the pin */ + ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id, + child_port_id, child_pin); + /* Find the name for this child port */ + BasicPort instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net); + /* Create the port information for the net */ + instance_ports.push_back(instance_port); + } + /* Try to merge the ports */ + std::vector merged_ports = combine_verilog_ports(instance_ports); + + /* Print a verilog port by combining the instance ports */ + fp << generate_verilog_ports(merged_ports); + + /* if explicit port map is required, output the pair of branket */ + if (true == use_explicit_port_map) { + fp << ")"; + } + port_cnt++; + } + } + + /* Print an end to the instance */ + fp << ");" << std::endl; + } /******************************************************************** @@ -59,27 +202,46 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu * This is a key function, maybe most frequently called in our Verilog writer * Note that file stream must be valid *******************************************************************/ -void writer_verilog_module_to_file(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id) { - /* Ensure a valid file stream */ - check_file_handler(fp); - +void write_verilog_module_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const bool& use_explicit_port_map) { /* Ensure we have a valid module_id */ VTR_ASSERT(module_manager.valid_module_id(module_id)); /* Print module declaration */ print_verilog_module_declaration(fp, module_manager, module_id); + + /* Print an empty line as splitter */ + fp << std::endl; /* TODO: Print internal wires */ + std::vector local_wires = find_verilog_module_local_wires(module_manager, module_id); + for (BasicPort local_wire : local_wires) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl; + } - /* TODO: Print instances */ + /* Print an empty line as splitter */ + fp << std::endl; + + /* TODO: Print local connection (from module inputs to output! */ + + /* Print an empty line as splitter */ + fp << std::endl; + + /* Print instances */ for (ModuleId child_module : module_manager.child_modules(module_id)) { for (size_t instance : module_manager.child_module_instances(module_id, child_module)) { /* Print an instance */ + write_verilog_instance_to_file(fp, module_manager, module_id, child_module, instance, use_explicit_port_map); + /* Print an empty line as splitter */ + fp << std::endl; } } /* Print an end for the module */ print_verilog_module_end(fp, module_manager.module_name(module_id)); + + /* Print an empty line as splitter */ + fp << std::endl; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h index bb7b401fb..0846384b7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h @@ -8,8 +8,9 @@ #include #include "module_manager.h" -void writer_verilog_module_to_file(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id); +void write_verilog_module_to_file(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const bool& use_explicit_port_map); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index d582c59bd..0341ef0a9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -406,6 +406,37 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p return verilog_line; } +/******************************************************************** + * Evaluate if two Verilog ports can be merged: + * If the port name is same, it can merged + *******************************************************************/ +bool two_verilog_ports_mergeable(const BasicPort& portA, + const BasicPort& portB) { + if (0 == portA.get_name().compare(portB.get_name())) { + return true; + } + return false; +} + +/******************************************************************** + * Merge two Verilog ports, return the merged port + * The ports should have the same name + * The new LSB will be minimum of the LSBs of the two ports + * The new MSB will the maximum of the MSBs of the two ports + *******************************************************************/ +BasicPort merge_two_verilog_ports(const BasicPort& portA, + const BasicPort& portB) { + BasicPort merged_port; + + VTR_ASSERT(true == two_verilog_ports_mergeable(portA, portB)); + + merged_port.set_name(portA.get_name()); + merged_port.set_lsb((size_t)std::min((int)portA.get_lsb(), (int)portB.get_lsb())); + merged_port.set_msb((size_t)std::max((int)portA.get_msb(), (int)portB.get_msb())); + + return merged_port; +} + /************************************************ * This function takes a list of ports and * combine the port string by comparing the name diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 1840f447f..f06e72baf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -53,6 +53,12 @@ void print_verilog_module_end(std::fstream& fp, std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type, const BasicPort& port_info); +bool two_verilog_ports_mergeable(const BasicPort& portA, + const BasicPort& portB); + +BasicPort merge_two_verilog_ports(const BasicPort& portA, + const BasicPort& portB); + std::vector combine_verilog_ports(const std::vector& ports); std::string generate_verilog_ports(const std::vector& merged_ports); From 1f650aac734c5cfe3b98793ce5ebf34958b19b3b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Oct 2019 20:54:31 -0600 Subject: [PATCH 281/482] add local direct connection Verilog code generation --- .../fpga_x2p/base/module_manager_utils.cpp | 40 ++++++- .../SRC/fpga_x2p/base/module_manager_utils.h | 3 + .../verilog/verilog_module_writer.cpp | 102 +++++++++++++++++- 3 files changed, 139 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index f24683bba..658bddee8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -267,7 +267,6 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, *******************************************************************/ bool module_net_is_local_wire(const ModuleManager& module_manager, const ModuleId& module_id, const ModuleNetId& module_net) { - /* A flag to identify local wire */ /* Check all the sink modules of the net, * if we have a source module is the current module, this is not local wire */ @@ -288,3 +287,42 @@ bool module_net_is_local_wire(const ModuleManager& module_manager, return true; } + +/******************************************************************** + * Identify if a net is a local short connection inside a module: + * The short connection is defined as the direct connection + * between an input port of the module and an output port of the module + * + * module + * +-----------------------------+ + * | | + * inputA--->|---------------------------->|--->outputB + * | | + * | | + * | | + * +-----------------------------+ + *******************************************************************/ +bool module_net_include_local_short_connection(const ModuleManager& module_manager, + const ModuleId& module_id, const ModuleNetId& module_net) { + /* Check all the sink modules of the net, + * if we have a source module is the current module, this is not local wire + */ + bool contain_module_input = false; + for (ModuleId src_module : module_manager.net_source_modules(module_id, module_net)) { + if (module_id == src_module) { + contain_module_input = true; + break; + } + } + + /* Check all the sink modules of the net */ + bool contain_module_output = false; + for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { + if (module_id == sink_module) { + contain_module_output = true; + break; + } + } + + return contain_module_input & contain_module_output; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index ce86a1f55..9bcd5b154 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -46,4 +46,7 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, bool module_net_is_local_wire(const ModuleManager& module_manager, const ModuleId& module_id, const ModuleNetId& module_net); +bool module_net_include_local_short_connection(const ModuleManager& module_manager, + const ModuleId& module_id, const ModuleNetId& module_net); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index 7d8256744..a5ab907b5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -13,6 +13,12 @@ #include "verilog_writer_utils.h" #include "verilog_module_writer.h" +/******************************************************************** + * Local constant variables for naming purpose + instance_port.set_name(VERILOG_MODULE_LOCAL_GND_WIRE_NAME); + *******************************************************************/ +constexpr char* VERILOG_MODULE_LOCAL_GND_WIRE_NAME = "VERILOG_CONSTANT_GND"; + /******************************************************************** * Name a net for a local wire for a verilog module * 1. If this is a local wire, name it after the __ @@ -110,6 +116,79 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu return local_wires; } +/******************************************************************** + * Print a Verilog wire connection + * We search all the sources of the net, + * if we find a module input, we try to find a module output + * among the sinks of the net + * If we find such a pair, we print a wire connection + *******************************************************************/ +static +void print_verilog_module_local_short_connection(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const ModuleNetId& module_net) { + /* Ensure a valid file stream */ + check_file_handler(fp); + + for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) { + ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src]; + if (module_id != src_module) { + continue; + } + /* Find the source port and pin information */ + ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src]; + size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src]; + BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin); + + /* We have found a module input, now check all the sink modules of the net */ + for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) { + ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink]; + if (module_id != sink_module) { + continue; + } + + /* Find the sink port and pin information */ + ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink]; + size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink]; + BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin); + + /* We need to print a wire connection here */ + print_verilog_wire_connection(fp, sink_port, src_port, false); + } + } +} + +/******************************************************************** + * Print short connections inside a Verilog module + * The short connection is defined as the direct connection + * between an input port of the module and an output port of the module + * This type of connection is not covered when printing Verilog instances + * Therefore, they are covered in this function + * + * module + * +-----------------------------+ + * | | + * inputA--->|---------------------------->|--->outputB + * | | + * | | + * | | + * +-----------------------------+ + *******************************************************************/ +static +void print_verilog_module_local_short_connections(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id) { + /* Local wires come from the child modules */ + for (ModuleNetId module_net : module_manager.module_nets(module_id)) { + /* We only care the nets that indicate short connections */ + if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) { + continue; + } + print_verilog_module_local_short_connection(fp, module_manager, module_id, module_net); + } +} + /******************************************************************** * Write a Verilog instance to a file * This function will name the input and output connections to @@ -173,8 +252,18 @@ void write_verilog_instance_to_file(std::fstream& fp, /* Find the net linked to the pin */ ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id, child_port_id, child_pin); - /* Find the name for this child port */ - BasicPort instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net); + BasicPort instance_port; + if (ModuleNetId::INVALID() == net) { + /* For unused net: assign a constant 0 value + * TODO: make it flexible to select between 0 and 1 + */ + /* TODO: output a warning? This could be potential issues for Verilog netlists */ + instance_port.set_name(VERILOG_MODULE_LOCAL_GND_WIRE_NAME); + instance_port.set_width(1); + } else { + /* Find the name for this child port */ + instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net); + } /* Create the port information for the net */ instance_ports.push_back(instance_port); } @@ -194,7 +283,6 @@ void write_verilog_instance_to_file(std::fstream& fp, /* Print an end to the instance */ fp << ");" << std::endl; - } /******************************************************************** @@ -215,7 +303,10 @@ void write_verilog_module_to_file(std::fstream& fp, /* Print an empty line as splitter */ fp << std::endl; - /* TODO: Print internal wires */ + /* Print constant GND wires */ + BasicPort constant_gnd_local_wire(VERILOG_MODULE_LOCAL_GND_WIRE_NAME, 1); + fp << generate_verilog_port(VERILOG_PORT_WIRE, constant_gnd_local_wire) << ";" << std::endl; + /* Print internal wires */ std::vector local_wires = find_verilog_module_local_wires(module_manager, module_id); for (BasicPort local_wire : local_wires) { fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl; @@ -224,7 +315,8 @@ void write_verilog_module_to_file(std::fstream& fp, /* Print an empty line as splitter */ fp << std::endl; - /* TODO: Print local connection (from module inputs to output! */ + /* Print local connection (from module inputs to output! */ + print_verilog_module_local_short_connections(fp, module_manager, module_id); /* Print an empty line as splitter */ fp << std::endl; From c9950162d11b6d94f553cfb9f200f1414fbe2ccb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 10 Oct 2019 22:02:46 -0600 Subject: [PATCH 282/482] start plug in new Verilog writer. Start debugging --- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 19 ----- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 4 -- .../fpga_x2p/base/module_manager_utils.cpp | 71 +++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 6 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 42 +++-------- .../verilog/verilog_module_writer.cpp | 18 +---- 6 files changed, 89 insertions(+), 71 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index 83fcf2121..a202513eb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -1332,25 +1332,6 @@ t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, return ret; } -/******************************************************************** - * Add the port-to-port mapping between a pb_type and its linked circuit model - * This function is mainly used to create instance of the module for a pb_type - *******************************************************************/ -void generate_pb_type_circuit_port2port_name_map(std::map& port2port_name_map, - t_pb_type* cur_pb_type, - const CircuitLibrary& circuit_lib) { - for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) { - t_port* pb_type_port = &(cur_pb_type->ports[iport]); - /* Must have a linked circuit model port */ - VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port); - std::string module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port); - /* Generate the module port name of pb_type */ - BasicPort instance_port(generate_pb_type_port_name(pb_type_port), circuit_lib.port_size(pb_type_port->circuit_model_port)); - /* Create the port of primitive model */ - port2port_name_map[module_port_name] = instance_port; - } -} - /******************************************************************** * Return a list of ports of a pb_type which matches the ports defined * in its linked circuit model diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index d7c969efa..954984e89 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -106,10 +106,6 @@ void map_clb_pins_to_pb_graph_pins(); t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, t_spice_model_port* spice_model_port); -void generate_pb_type_circuit_port2port_name_map(std::map& port2port_name_map, - t_pb_type* cur_pb_type, - const CircuitLibrary& circuit_lib); - std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, enum e_spice_model_port_type port_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 658bddee8..ea1b034ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -6,6 +6,7 @@ #include #include +#include "util.h" #include "vtr_assert.h" #include "spice_types.h" @@ -326,3 +327,73 @@ bool module_net_include_local_short_connection(const ModuleManager& module_manag return contain_module_input & contain_module_output; } + +/******************************************************************** + * Add the port-to-port connection between a pb_type and its linked circuit model + * This function is mainly used to create instance of the module for a pb_type + * + * Note: this function SHOULD be called after the pb_type_module is created + * and its child module is created! + *******************************************************************/ +void add_primitive_pb_type_module_nets(ModuleManager& module_manager, + const ModuleId& pb_type_module, + const ModuleId& child_module, + const size_t& child_instance_id, + const CircuitLibrary& circuit_lib, + t_pb_type* cur_pb_type) { + for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) { + t_port* pb_type_port = &(cur_pb_type->ports[iport]); + /* Must have a linked circuit model port */ + VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port); + + /* Find the source port in pb_type module */ + /* Get the src module port id */ + ModulePortId src_module_port_id = module_manager.find_module_port(pb_type_module, generate_pb_type_port_name(pb_type_port)); + VTR_ASSERT(ModulePortId::INVALID() != src_module_port_id); + BasicPort src_port = module_manager.module_port(pb_type_module, src_module_port_id); + + /* Get the des module port id */ + std::string des_module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port); + ModulePortId des_module_port_id = module_manager.find_module_port(child_module, des_module_port_name); + VTR_ASSERT(ModulePortId::INVALID() != des_module_port_id); + BasicPort des_port = module_manager.module_port(child_module, des_module_port_id); + + /* Port size must match */ + if (src_port.get_width() != des_port.get_width()) + VTR_ASSERT(src_port.get_width() == des_port.get_width()); + + /* For each pin, generate the nets. + * For non-output ports (input ports, inout ports and clock ports), + * src_port is the source of the net + * For output ports + * src_port is the sink of the net + */ + switch (pb_type_port->type) { + case IN_PORT: + case INOUT_PORT: + for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(pb_type_module); + /* Add net source */ + module_manager.add_module_net_source(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]); + } + break; + case OUT_PORT: + for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(pb_type_module); + /* Add net source */ + module_manager.add_module_net_sink(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_source(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid port of pb_type!\n", + __FILE__, __LINE__); + exit(1); + } + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 9bcd5b154..4bfa2125c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -49,4 +49,10 @@ bool module_net_is_local_wire(const ModuleManager& module_manager, bool module_net_include_local_short_connection(const ModuleManager& module_manager, const ModuleId& module_id, const ModuleNetId& module_net); +void add_primitive_pb_type_module_nets(ModuleManager& module_manager, + const ModuleId& pb_type_module, + const ModuleId& child_module, + const size_t& child_instance_id, + const CircuitLibrary& circuit_lib, + t_pb_type* cur_pb_type); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index dd6822c35..9151fafc7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -27,6 +27,7 @@ #include "verilog_global.h" #include "verilog_utils.h" #include "verilog_writer_utils.h" +#include "verilog_module_writer.h" #include "verilog_grid.h" /******************************************************************** @@ -145,47 +146,22 @@ void print_verilog_primitive_block(std::fstream& fp, num_config_bits); } - /* Print the module definition for the top-level Verilog module of physical block */ - print_verilog_module_declaration(fp, module_manager, primitive_module); - /* Finish printing ports */ - /* Find the module id in the module manager */ ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model)); VTR_ASSERT(ModuleId::INVALID() != logic_module); size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); - - /* Local wires for memory configurations */ - print_verilog_comment(fp, std::string("---- BEGIN local configuration bus ----")); - print_verilog_local_config_bus(fp, circuit_lib.model_name(primitive_model), cur_sram_orgz_info->type, logic_instance_id, num_config_bits); - print_verilog_comment(fp, std::string("---- END local configuration bus ----")); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* TODO: Instanciate the logic module */ - /* Create port-to-port map */ - std::map logic_port2port_name_map; - /* Link the logic model ports to pb_type ports */ - generate_pb_type_circuit_port2port_name_map(logic_port2port_name_map, primitive_pb_graph_node->pb_type, circuit_lib); - /* TODO: Link both regular and mode-select SRAM ports */ - - /* Print an instance of the logic Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of " + circuit_lib.model_name(primitive_model) + " -----")); - print_verilog_module_instance(fp, module_manager, primitive_module, logic_module, logic_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of " + circuit_lib.model_name(primitive_model) + " -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ + /* Add the logic module as a child of primitive module */ module_manager.add_child_module(primitive_module, logic_module); - /* Add an empty line as a splitter */ - fp << std::endl; + /* Add nets to connect the logic model ports to pb_type ports */ + add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); - /* TODO: Instanciate associated memory module */ + /* TODO: add the associated memory module as a child of primitive module */ - /* Print an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(primitive_module)); + /* TODO: Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ + + /* TODO: write the verilog module */ + write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index a5ab907b5..ea43f35e0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -13,12 +13,6 @@ #include "verilog_writer_utils.h" #include "verilog_module_writer.h" -/******************************************************************** - * Local constant variables for naming purpose - instance_port.set_name(VERILOG_MODULE_LOCAL_GND_WIRE_NAME); - *******************************************************************/ -constexpr char* VERILOG_MODULE_LOCAL_GND_WIRE_NAME = "VERILOG_CONSTANT_GND"; - /******************************************************************** * Name a net for a local wire for a verilog module * 1. If this is a local wire, name it after the __ @@ -254,12 +248,9 @@ void write_verilog_instance_to_file(std::fstream& fp, child_port_id, child_pin); BasicPort instance_port; if (ModuleNetId::INVALID() == net) { - /* For unused net: assign a constant 0 value - * TODO: make it flexible to select between 0 and 1 - */ - /* TODO: output a warning? This could be potential issues for Verilog netlists */ - instance_port.set_name(VERILOG_MODULE_LOCAL_GND_WIRE_NAME); - instance_port.set_width(1); + /* We give the same port name as child module, this case happens to global ports */ + instance_port.set_name(module_manager.module_port(child_module, child_port_id).get_name()); + instance_port.set_width(child_pin, child_pin); } else { /* Find the name for this child port */ instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net); @@ -303,9 +294,6 @@ void write_verilog_module_to_file(std::fstream& fp, /* Print an empty line as splitter */ fp << std::endl; - /* Print constant GND wires */ - BasicPort constant_gnd_local_wire(VERILOG_MODULE_LOCAL_GND_WIRE_NAME, 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, constant_gnd_local_wire) << ";" << std::endl; /* Print internal wires */ std::vector local_wires = find_verilog_module_local_wires(module_manager, module_id); for (BasicPort local_wire : local_wires) { From 663b1b76658fb02e94165476296eba366a003d02 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Oct 2019 13:07:14 -0600 Subject: [PATCH 283/482] refactorint net addition for configuration signals in module graph --- .../libarchfpga/SRC/circuit_library_utils.cpp | 19 ++ .../libarchfpga/SRC/circuit_library_utils.h | 3 + .../fpga_x2p/base/module_manager_utils.cpp | 232 ++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 10 + .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 23 +- 5 files changed, 283 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp index 373a46117..3a0a7d91a 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -92,6 +92,25 @@ std::vector find_circuit_regular_sram_ports(const CircuitLibrary& return regular_sram_ports; } +/******************************************************************** + * Find mode select sram ports of a circuit model + *******************************************************************/ +std::vector find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); + std::vector mode_select_sram_ports; + + for (const auto& port : sram_ports) { + if (false == circuit_lib.port_is_mode_select(port)) { + continue; + } + mode_select_sram_ports.push_back(port); + } + + return mode_select_sram_ports; +} + + /******************************************************************** * Find the number of shared configuration bits for a ReRAM circuit * TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!! diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h index 2fa705c25..03485a014 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h @@ -17,6 +17,9 @@ std::vector find_circuit_sram_models(const CircuitLibrary& circu std::vector find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); +std::vector find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model); + size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const e_sram_orgz& sram_orgz_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index ea1b034ad..52e73c6c0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -12,10 +12,12 @@ #include "spice_types.h" #include "circuit_library.h" +#include "circuit_library_utils.h" #include "module_manager.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_pbtypes_utils.h" +#include "fpga_x2p_mem_utils.h" #include "module_manager_utils.h" @@ -397,3 +399,233 @@ void add_primitive_pb_type_module_nets(ModuleManager& module_manager, } } +/******************************************************************** + * Add the port-to-port connection between a logic module + * and a memory module + * Create nets to wire SRAM ports between logic module and memory module + * + * The information about SRAM ports of logic module are stored in the + * mem_output_bus_ports, where element [0] denotes the SRAM port while + * element [1] denotes the SRAMb port + * + * +---------+ +--------+ + * | | regular SRAM port | | + * | Logic |-----------------------+ | Memory | + * | Module | mode-select SRAM port |->| Module | + * | |-----------------------+ | | + * +---------+ +--------+ + * + * There could be multiple SRAM ports of logic module, which are wired to + * the SRAM ports of memory module + * + * Note: this function SHOULD be called after the pb_type_module is created + * and its child module (logic_module and memory_module) is created! + * + * Note: this function only handle either SRAM or SRAMb ports. + * So, this function may be called twice to complete the wiring + *******************************************************************/ +static +void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_manager, + const ModuleId& parent_module, + const ModuleId& logic_module, + const size_t& logic_instance_id, + const ModuleId& memory_module, + const size_t& memory_instance_id, + const std::vector& logic_module_sram_port_ids, + const ModulePortId& mem_module_sram_port_id) { + /* Find mem_output_bus ports in logic module */ + std::vector logic_module_sram_ports; + for (const ModulePortId& logic_module_sram_port_id : logic_module_sram_port_ids) { + logic_module_sram_ports.push_back(module_manager.module_port(logic_module, logic_module_sram_port_id)); + } + + /* Create a list of virtual ports to align with the SRAM port of logic module + * Physical ports: + * + * logic_module_sram_port[0] logic_module_sram_port[1] + * + * LSB[0]------------>MSB[0] LSB------------------>MSB + * + * memory_sram_port + * LSBY---------------------------------------------->MSBY + * + * Virtual ports: + * mem_module_sram_port[0] mem_module_sram_port[1] + * LSBY--------------->MSBX MSBX+1------------------>MSBY + * + */ + BasicPort mem_module_port = module_manager.module_port(memory_module, mem_module_sram_port_id); + std::vector virtual_mem_module_ports; + + /* Create a counter for the LSB of virtual ports */ + size_t port_lsb = 0; + for (const BasicPort& logic_module_sram_port : logic_module_sram_ports) { + BasicPort virtual_port; + virtual_port.set_name(mem_module_port.get_name()); + virtual_port.set_width(port_lsb, port_lsb + logic_module_sram_port.get_width() - 1); + virtual_mem_module_ports.push_back(virtual_port); + port_lsb = virtual_port.get_msb() + 1; + } + /* port_lsb should be aligned with the MSB of memory_sram_port */ + VTR_ASSERT(port_lsb == mem_module_port.get_msb() + 1); + + /* Wire port to port */ + for (size_t port_index = 0; port_index < logic_module_sram_ports.size(); ++port_index) { + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, memory_module, memory_instance_id, mem_module_sram_port_id, virtual_mem_module_ports[port_index].pins()[pin_id]); + } + } +} + +/******************************************************************** + * Add the port-to-port connection between a logic module + * and a memory module + * Create nets to wire SRAM ports between logic module and memory module + * + * + * +---------+ +--------+ + * | | SRAM ports | | + * | Logic |----------------------->| Memory | + * | Module | SRAMb ports | Module | + * | |----------------------->| | + * +---------+ +--------+ + * + * Note: this function SHOULD be called after the pb_type_module is created + * and its child module (logic_module and memory_module) is created! + * + *******************************************************************/ +void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const ModuleId& logic_module, + const size_t& logic_instance_id, + const ModuleId& memory_module, + const size_t& memory_instance_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& logic_model) { + + /* Connect SRAM port */ + /* Find SRAM ports in the circuit model for logic module */ + std::vector logic_model_sram_port_names; + /* Regular sram port goes first */ + for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { + logic_model_sram_port_names.push_back(circuit_lib.port_lib_name(regular_sram_port)); + } + /* Mode-select sram port goes first */ + for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { + logic_model_sram_port_names.push_back(circuit_lib.port_lib_name(mode_select_sram_port)); + } + /* Find the port ids in the memory */ + std::vector logic_module_sram_port_ids; + for (const std::string& logic_model_sram_port_name : logic_model_sram_port_names) { + /* Skip non-exist ports */ + if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sram_port_name)) { + continue; + } + logic_module_sram_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sram_port_name)); + } + + /* Get the SRAM port name of memory model */ + /* TODO: this should be a constant expression and it should be the same for all the memory module! */ + std::string memory_model_sram_port_name = generate_configuration_chain_data_out_name(); + /* Find the corresponding ports in memory module */ + ModulePortId mem_module_sram_port_id = module_manager.find_module_port(memory_module, memory_model_sram_port_name); + + /* Do wiring only when we have sram ports */ + if ( (false == logic_module_sram_port_ids.empty()) + || (ModulePortId::INVALID() == mem_module_sram_port_id) ) { + add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module, + logic_module, logic_instance_id, + memory_module, memory_instance_id, + logic_module_sram_port_ids, mem_module_sram_port_id); + } + + /* Connect SRAMb port */ + /* Find SRAM ports in the circuit model for logic module */ + std::vector logic_model_sramb_port_names; + /* Regular sram port goes first */ + for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { + logic_model_sramb_port_names.push_back(circuit_lib.port_lib_name(regular_sram_port) + std::string("_inv")); + } + /* Mode-select sram port goes first */ + for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { + logic_model_sramb_port_names.push_back(circuit_lib.port_lib_name(mode_select_sram_port) + std::string("_inv")); + } + /* Find the port ids in the memory */ + std::vector logic_module_sramb_port_ids; + for (const std::string& logic_model_sramb_port_name : logic_model_sramb_port_names) { + /* Skip non-exist ports */ + if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sramb_port_name)) { + continue; + } + logic_module_sramb_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sramb_port_name)); + } + + /* Get the SRAM port name of memory model */ + std::string memory_model_sramb_port_name = generate_configuration_chain_inverted_data_out_name(); + /* Find the corresponding ports in memory module */ + ModulePortId mem_module_sramb_port_id = module_manager.find_module_port(memory_module, memory_model_sramb_port_name); + + /* Do wiring only when we have sramb ports */ + if ( (false == logic_module_sramb_port_ids.empty()) + || (ModulePortId::INVALID() == mem_module_sramb_port_id) ) { + add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module, + logic_module, logic_instance_id, + memory_module, memory_instance_id, + logic_module_sramb_port_ids, mem_module_sramb_port_id); + } +} + +/******************************************************************** + * TODO: + * Add the port-to-port connection between a logic module + * and a memory module inside a primitive module + * + * Create nets to wire the control signals of memory module to + * the configuration ports of primitive module + * + * Primitive module + * +----------------------------+ + * | +--------+ | + * config | | | | + * ports --->|--------------->| Memory | | + * | | Module | | + * | | | | + * | +--------+ | + * +----------------------------+ + * The detailed config ports really depend on the type + * of SRAM organization. + * + * Note: this function SHOULD be called after the pb_type_module is created + * and its child module (logic_module and memory_module) is created! + *******************************************************************/ + +/******************************************************************** + * TODO: + * Add the port-to-port connection between a logic module + * and a memory module inside a primitive module + * + * Create nets to wire the formal verification ports of + * primitive module to SRAM ports of logic module + * + * Primitive module + * + * formal_port_sram + * +-----------------------------------------------+ + * | ^ | + * | +---------+ | +--------+ | + * | | | SRAM | | | | + * | | Logic |--------+--->| Memory | | + * | | Module | SRAMb | Module | | + * | | |--------+--->| | | + * | +---------+ | +--------+ | + * | v | + * +-----------------------------------------------+ + * formal_port_sramb + * + *******************************************************************/ + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 4bfa2125c..e67127fcd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -55,4 +55,14 @@ void add_primitive_pb_type_module_nets(ModuleManager& module_manager, const size_t& child_instance_id, const CircuitLibrary& circuit_lib, t_pb_type* cur_pb_type); + +void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const ModuleId& logic_module, + const size_t& logic_instance_id, + const ModuleId& memory_module, + const size_t& memory_instance_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& logic_model); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 9151fafc7..95360ccf8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -156,11 +156,26 @@ void print_verilog_primitive_block(std::fstream& fp, /* Add nets to connect the logic model ports to pb_type ports */ add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); - /* TODO: add the associated memory module as a child of primitive module */ + /* Add the associated memory module as a child of primitive module */ + std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix)); + ModuleId memory_module = module_manager.find_module(memory_module_name); - /* TODO: Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ - - /* TODO: write the verilog module */ + /* If there is no memory module required, we can skip the assocated net addition */ + if (ModuleId::INVALID() != memory_module) { + size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); + /* Add the memory module as a child of primitive module */ + module_manager.add_child_module(primitive_module, memory_module); + + /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ + add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module, + logic_module, logic_instance_id, + memory_module, memory_instance_id, + circuit_lib, primitive_model); + /* TODO: Add nets to connect configuration ports from memory module to primitive module */ + /* TODO: Add nets to connect formal verification ports from memory module to primitive module */ + } + + /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping); /* Add an empty line as a splitter */ From 50f7d1eae36585a9023b95e4e9ee2c4850211ffb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Oct 2019 14:20:04 -0600 Subject: [PATCH 284/482] bug fixing in Verilog port merging and instanciation --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 2 +- .../SRC/fpga_x2p/base/module_manager_utils.cpp | 3 +++ .../fpga_x2p/verilog/verilog_module_writer.cpp | 14 ++++++++++---- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 18 ++++++++++-------- 4 files changed, 24 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 41a5f723e..c5e07776c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -50,7 +50,7 @@ std::vector ModuleManager::child_module_instances(const ModuleId& parent VTR_ASSERT(child_index != children_[parent_module].size()); /* Create a vector, with sequentially increasing numbers */ - std::vector instance_range(num_child_instances_[parent_module][child_index]); + std::vector instance_range(num_child_instances_[parent_module][child_index], 0); std::iota(instance_range.begin(), instance_range.end(), 0); return instance_range; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 52e73c6c0..670748142 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -474,6 +474,9 @@ void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_m /* Create a net for each pin */ for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(parent_module); + /* TODO: Give a name to make it clear */ + std::string net_name = module_manager.module_name(logic_module) + std::string("_") + logic_module_sram_ports[port_index].get_name(); + module_manager.set_net_name(parent_module, net, net_name); /* Add net source */ module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]); /* Add net sink */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index ea43f35e0..0103015c7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -50,6 +50,7 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag } /* Reach here, this is a local wire */ + std::string net_name; /* Each net must only one 1 source */ @@ -64,9 +65,14 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag /* Get the pin id */ size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)]; - net_name = module_manager.module_name(net_src_module); - net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_"); - net_name += module_manager.module_port(module_id, net_src_port).get_name(); + /* Load user-defined name if we have it */ + if (false == module_manager.net_name(module_id, module_net).empty()) { + net_name = module_manager.net_name(module_id, module_net); + } else { + net_name = module_manager.module_name(net_src_module); + net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_"); + net_name += module_manager.module_port(module_id, net_src_port).get_name(); + } return BasicPort(net_name, net_src_pin, net_src_pin); } @@ -213,7 +219,7 @@ void write_verilog_instance_to_file(std::fstream& fp, /* Print module name */ fp << "\t" << module_manager.module_name(child_module) << " "; /* Print instance name, _ */ - fp << module_manager.module_name(child_module) << "_" << module_manager.num_instance(parent_module, child_module) << "_" << " (" << std::endl; + fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl; /* Print each port with/without explicit port map */ /* port type2type mapping */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 0341ef0a9..4b9931c2c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -464,19 +464,16 @@ std::vector combine_verilog_ports(const std::vector& ports continue; } /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */ + bool merged = false; for (auto& merged_port : merged_ports) { if (0 != port.get_name().compare(merged_port.get_name())) { - /* Unable to merge, add the port to merged port list */ - merged_ports.push_back(port); - /* Go to next */ - break; + /* Unable to merge, Go to next */ + continue; } /* May be merged, check LSB of port and MSB of merged_port */ if (merged_port.get_msb() + 1 != port.get_lsb()) { - /* Unable to merge, add the port to merged port list */ - merged_ports.push_back(port); - /* Go to next */ - break; + /* Unable to merge, Go to next */ + continue; } /* Reach here, we should merge the ports, * LSB of merged_port remains the same, @@ -484,8 +481,13 @@ std::vector combine_verilog_ports(const std::vector& ports * to the MSB of port */ merged_port.set_msb(port.get_msb()); + merged = true; break; } + if (false == merged) { + /* Unable to merge, add the port to merged port list */ + merged_ports.push_back(port); + } } return merged_ports; From 73a5977e0d54bdbba9fa42e9ff1efc7259f1bc1c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Oct 2019 18:00:37 -0600 Subject: [PATCH 285/482] Debugged Verilog generation for primitive pb_types --- .../fpga_x2p/base/module_manager_utils.cpp | 233 +++++++++++++++++- .../SRC/fpga_x2p/base/module_manager_utils.h | 9 + .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 26 +- 3 files changed, 261 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 670748142..a3dbd5c91 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -583,11 +583,209 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man } } -/******************************************************************** +/********************************************************************* + * Add the port-to-port connection between all the memory modules + * and their parent module + * + * Create nets to wire the control signals of memory module to + * the configuration ports of primitive module + * + * Configuration Chain + * ------------------- + * + * config_bus (head) config_bus (tail) + * | ^ + * primitive | | + * +---------------------------------------------+ + * | | | | + * | v | | + * | +-------------------------------------+ | + * | | CMOS-based Memory Modules | | + * | +-------------------------------------+ | + * | | | | + * | v v | + * | sram_out sram_outb | + * | | + * +---------------------------------------------+ + * + * Memory bank + * ----------- + * + * config_bus (BL) config_bus (WL) + * | | + * primitive | | + * +---------------------------------------------+ + * | | | | + * | v v | + * | +-------------------------------------+ | + * | | CMOS-based Memory Modules | | + * | +-------------------------------------+ | + * | | | | + * | v v | + * | sram_out sram_outb | + * | | + * +---------------------------------------------+ + * + **********************************************************************/ +static +void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type, + const CircuitLibrary& circuit_lib, + const std::vector& memory_models) { + /* Ensure that the size of memory_model vector matches the memory_module vector */ + VTR_ASSERT( (memory_modules.size() == memory_instances.size()) + && (memory_modules.size() == memory_models.size()) ); + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Nothing to do */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + /* Connect all the memory modules under the parent module in a chain + * + * +--------+ +--------+ +--------+ + * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail + * | Module | | Module | | Module | + * | [0] | | [1] | | [N-1] | + * +--------+ +--------+ +--------+ + * For the 1st memory module: + * net source is the configuration chain head of the primitive module + * net sink is the configuration chain head of the next memory module + * + * For the rest of memory modules: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain head of the next memory module + */ + for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) { + ModuleId net_src_module_id; + size_t net_src_instance_id; + ModulePortId net_src_port_id; + + ModuleId net_sink_module_id; + size_t net_sink_instance_id; + ModulePortId net_sink_port_id; + + if (0 == mem_index) { + /* Find the port name of configuration chain head */ + std::string src_port_name = generate_sram_port_name(circuit_lib, memory_models[mem_index], sram_orgz_type, SPICE_MODEL_PORT_INPUT); + net_src_module_id = parent_module; + net_src_instance_id = 0; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_head_name(); + net_sink_module_id = memory_modules[mem_index]; + net_sink_instance_id = memory_instances[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + } else { + /* Find the port name of previous memory module */ + std::string src_port_name = generate_configuration_chain_tail_name(); + net_src_module_id = memory_modules[mem_index - 1]; + net_src_instance_id = memory_instances[mem_index - 1]; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_head_name(); + net_sink_module_id = memory_modules[mem_index]; + net_sink_instance_id = memory_instances[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + } + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + /* Port sizes of source and sink should match */ + VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { + /* Create a net and add source and sink to it */ + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + } + } + + /* For the last memory module: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain tail of the primitive module + */ + /* Find the port name of previous memory module */ + std::string src_port_name = generate_configuration_chain_tail_name(); + ModuleId net_src_module_id = memory_modules.back(); + size_t net_src_instance_id = memory_instances.back(); + ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_sram_port_name(circuit_lib, memory_models.back(), sram_orgz_type, SPICE_MODEL_PORT_OUTPUT); + ModuleId net_sink_module_id = parent_module; + size_t net_sink_instance_id = 0; + ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + /* Port sizes of source and sink should match */ + VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { + /* Create a net and add source and sink to it */ + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + } + break; + } + case SPICE_SRAM_MEMORY_BANK: + /* TODO: */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/********************************************************************* * TODO: * Add the port-to-port connection between a logic module * and a memory module inside a primitive module * + * Memory bank + * ----------- + * config_bus (BL) config_bus (WL) shared_config_bugs(shared_BL/WLs) + * | | | | + * primitive | | | | + * +------------------------------------------------------------+ + * | | | | | | + * | v v v v | + * | +----------------------------------------------------+ | + * | | ReRAM-based Memory Module | | + * | +----------------------------------------------------+ | + * | | | | + * | v v | + * | mem_out mem_outb | + * | | + * +------------------------------------------------------------+ + * + **********************************************************************/ + +/******************************************************************** + * TODO: + * Add the port-to-port connection between a memory module + * and the configuration bus of a primitive module + * * Create nets to wire the control signals of memory module to * the configuration ports of primitive module * @@ -603,9 +801,42 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man * The detailed config ports really depend on the type * of SRAM organization. * + * The config_bus in the argument is the reserved address of configuration + * bus in the parent_module for this memory module + * + * The configuration bus connection will depend not only + * the design technology of the memory cells but also the + * configuration styles of FPGA fabric. + * Here we will branch on the design technology + * * Note: this function SHOULD be called after the pb_type_module is created * and its child module (logic_module and memory_module) is created! *******************************************************************/ +void add_module_nets_memory_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_design_tech& mem_tech, + const CircuitLibrary& circuit_lib, + const std::vector& memory_models) { + switch (mem_tech) { + case SPICE_MODEL_DESIGN_CMOS: + add_module_nets_cmos_memory_config_bus(module_manager, parent_module, + memory_modules, memory_instances, + sram_orgz_type, + circuit_lib, memory_models); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* TODO: */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of memory design technology !\n", + __FILE__, __LINE__); + exit(1); + } +} /******************************************************************** * TODO: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index e67127fcd..1d6ce9995 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -65,4 +65,13 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man const CircuitLibrary& circuit_lib, const CircuitModelId& logic_model); +void add_module_nets_memory_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_design_tech& mem_tech, + const CircuitLibrary& circuit_lib, + const std::vector& memory_models); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 95360ccf8..dab8387db 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -140,10 +140,6 @@ void print_verilog_primitive_block(std::fstream& fp, add_sram_ports_to_module_manager(module_manager, primitive_module, circuit_lib, sram_model, cur_sram_orgz_info->type, num_config_bits); - /* Add ports only visible during formal verification to the module */ - add_formal_verification_sram_ports_to_module_manager(module_manager, primitive_module, circuit_lib, sram_model, - std::string(verilog_formal_verification_preproc_flag), - num_config_bits); } /* Find the module id in the module manager */ @@ -160,6 +156,13 @@ void print_verilog_primitive_block(std::fstream& fp, std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix)); ModuleId memory_module = module_manager.find_module(memory_module_name); + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + std::vector memory_models; + /* If there is no memory module required, we can skip the assocated net addition */ if (ModuleId::INVALID() != memory_module) { size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); @@ -171,8 +174,19 @@ void print_verilog_primitive_block(std::fstream& fp, logic_module, logic_instance_id, memory_module, memory_instance_id, circuit_lib, primitive_model); - /* TODO: Add nets to connect configuration ports from memory module to primitive module */ - /* TODO: Add nets to connect formal verification ports from memory module to primitive module */ + /* Record memory-related information */ + memory_modules.push_back(memory_module); + memory_instances.push_back(memory_instance_id); + memory_models.push_back(sram_model); + } + /* Add all the nets to connect configuration ports from memory module to primitive modules + * This is a one-shot addition that covers all the memory modules in this primitive module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, primitive_module, + memory_modules, memory_instances, + cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model), + circuit_lib, memory_models); } /* Write the verilog module */ From b3ca0d32a4b1928dda1bdcd5b2c706ae246982f2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Oct 2019 19:47:36 -0600 Subject: [PATCH 286/482] remove configuration bus naming dependency on SRAM circuit models --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 22 +++++++++---------- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 4 +--- .../fpga_x2p/base/module_manager_utils.cpp | 20 ++++++----------- .../SRC/fpga_x2p/base/module_manager_utils.h | 4 +--- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 5 +---- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 8 +++---- 6 files changed, 24 insertions(+), 39 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 76c0e7086..41ccade95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -459,11 +459,9 @@ std::string generate_local_config_bus_port_name() { * port list of a module * The port name is named after the cell name of SRAM in circuit library *********************************************************************/ -std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type, +std::string generate_sram_port_name(const e_sram_orgz& sram_orgz_type, const e_spice_model_port_type& port_type) { - std::string port_name = circuit_lib.model_name(sram_model) + std::string("_"); + std::string port_name; switch (sram_orgz_type) { case SPICE_SRAM_STANDALONE: { @@ -472,10 +470,10 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, * (2) Inverted output of a SRAM, enabled by port type of OUTPUT */ if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("out"); + port_name = std::string("mem_out"); } else { VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name += std::string("outb"); + port_name = std::string("mem_outb"); } break; } @@ -488,10 +486,10 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, * +------+ +------+ +------+ */ if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("ccff_head"); + port_name = std::string("ccff_head"); } else { VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name += std::string("ccff_tail"); + port_name = std::string("ccff_tail"); } break; case SPICE_SRAM_MEMORY_BANK: @@ -510,14 +508,14 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, * +----------+ +----------+ +----------+ */ if (SPICE_MODEL_PORT_BL == port_type) { - port_name += std::string("bl"); + port_name = std::string("bl"); } else if (SPICE_MODEL_PORT_WL == port_type) { - port_name += std::string("wl"); + port_name = std::string("wl"); } else if (SPICE_MODEL_PORT_BLB == port_type) { - port_name += std::string("blb"); + port_name = std::string("blb"); } else { VTR_ASSERT( SPICE_MODEL_PORT_WLB == port_type ); - port_name += std::string("wlb"); + port_name = std::string("wlb"); } break; default: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 989c60714..8d7826165 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -99,9 +99,7 @@ std::string generate_mux_local_decoder_data_inv_port_name(); std::string generate_local_config_bus_port_name(); -std::string generate_sram_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type, +std::string generate_sram_port_name(const e_sram_orgz& sram_orgz_type, const e_spice_model_port_type& port_type); std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index a3dbd5c91..5e325e44a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -207,7 +207,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, /* Add ports to the module manager */ for (size_t iport = 0; iport < model_port_types.size(); ++iport) { /* Create a port */ - std::string port_name = generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, model_port_types[iport]); + std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]); BasicPort module_port(port_name, sram_port_size); /* Add generated ports to the ModuleManager */ module_manager.add_port(module_id, module_port, module_port_types[iport]); @@ -632,12 +632,9 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, const std::vector& memory_modules, const std::vector& memory_instances, - const e_sram_orgz& sram_orgz_type, - const CircuitLibrary& circuit_lib, - const std::vector& memory_models) { + const e_sram_orgz& sram_orgz_type) { /* Ensure that the size of memory_model vector matches the memory_module vector */ - VTR_ASSERT( (memory_modules.size() == memory_instances.size()) - && (memory_modules.size() == memory_models.size()) ); + VTR_ASSERT(memory_modules.size() == memory_instances.size()); switch (sram_orgz_type) { case SPICE_SRAM_STANDALONE: @@ -670,7 +667,7 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, if (0 == mem_index) { /* Find the port name of configuration chain head */ - std::string src_port_name = generate_sram_port_name(circuit_lib, memory_models[mem_index], sram_orgz_type, SPICE_MODEL_PORT_INPUT); + std::string src_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT); net_src_module_id = parent_module; net_src_instance_id = 0; net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); @@ -723,7 +720,7 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ - std::string sink_port_name = generate_sram_port_name(circuit_lib, memory_models.back(), sram_orgz_type, SPICE_MODEL_PORT_OUTPUT); + std::string sink_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT); ModuleId net_sink_module_id = parent_module; size_t net_sink_instance_id = 0; ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); @@ -817,15 +814,12 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager, const std::vector& memory_modules, const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_tech, - const CircuitLibrary& circuit_lib, - const std::vector& memory_models) { + const e_spice_model_design_tech& mem_tech) { switch (mem_tech) { case SPICE_MODEL_DESIGN_CMOS: add_module_nets_cmos_memory_config_bus(module_manager, parent_module, memory_modules, memory_instances, - sram_orgz_type, - circuit_lib, memory_models); + sram_orgz_type); break; case SPICE_MODEL_DESIGN_RRAM: /* TODO: */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 1d6ce9995..78155d325 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -70,8 +70,6 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager, const std::vector& memory_modules, const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_tech, - const CircuitLibrary& circuit_lib, - const std::vector& memory_models); + const e_spice_model_design_tech& mem_tech); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index dab8387db..848e61a87 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -161,7 +161,6 @@ void print_verilog_primitive_block(std::fstream& fp, */ std::vector memory_modules; std::vector memory_instances; - std::vector memory_models; /* If there is no memory module required, we can skip the assocated net addition */ if (ModuleId::INVALID() != memory_module) { @@ -177,7 +176,6 @@ void print_verilog_primitive_block(std::fstream& fp, /* Record memory-related information */ memory_modules.push_back(memory_module); memory_instances.push_back(memory_instance_id); - memory_models.push_back(sram_model); } /* Add all the nets to connect configuration ports from memory module to primitive modules * This is a one-shot addition that covers all the memory modules in this primitive module! @@ -185,8 +183,7 @@ void print_verilog_primitive_block(std::fstream& fp, if (false == memory_modules.empty()) { add_module_nets_memory_config_bus(module_manager, primitive_module, memory_modules, memory_instances, - cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model), - circuit_lib, memory_models); + cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); } /* Write the verilog module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 4b9931c2c..344509935 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -814,12 +814,12 @@ void print_verilog_local_sram_wires(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_config_bus_port) << ";" << std::endl; /* Connect first CCFF to the head */ /* Head is always a 1-bit port */ - BasicPort ccff_head_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1); + BasicPort ccff_head_port(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1); BasicPort ccff_head_local_port(ccff_config_bus_port.get_name(), 1); print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false); /* Connect last CCFF to the tail */ /* Tail is always a 1-bit port */ - BasicPort ccff_tail_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1); + BasicPort ccff_tail_port(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1); BasicPort ccff_tail_local_port(ccff_config_bus_port.get_name(), ccff_config_bus_port.get_msb(), ccff_config_bus_port.get_msb()); print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false); break; @@ -1027,11 +1027,11 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp, print_verilog_wire_connection(fp, wl_bus_reserved_bits, reserved_wl_bus, false); /* Connect SRAM BL/WLs to bus */ - BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BL), + BasicPort mux_bl_wire(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_BL), num_conf_bits); BasicPort bl_bus_regular_bits(bl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); print_verilog_wire_connection(fp, bl_bus_regular_bits, mux_bl_wire, false); - BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WL), + BasicPort mux_wl_wire(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_WL), num_conf_bits); BasicPort wl_bus_regular_bits(wl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); print_verilog_wire_connection(fp, wl_bus_regular_bits, mux_wl_wire, false); From d1948c82ebbe28d2c27d692fe279caf6d5bb80d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 11 Oct 2019 21:43:47 -0600 Subject: [PATCH 287/482] Refactoring Verilog generation intermediate level of pb_types and SRAM port generation --- .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp | 101 +++++++++++++++ .../SRC/fpga_x2p/base/fpga_x2p_mem_utils.h | 7 ++ .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 2 +- .../fpga_x2p/base/module_manager_utils.cpp | 117 ++++++++++-------- .../SRC/fpga_x2p/base/module_manager_utils.h | 12 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 90 ++++++++++---- 6 files changed, 248 insertions(+), 81 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp index 265330f40..01e26632a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp @@ -295,3 +295,104 @@ bool check_mem_config_bus(const e_sram_orgz& sram_orgz_type, /* Reach here, it means something goes wrong, return a false value */ return false; } + +/******************************************************************** + * Generate a list of ports that are used for SRAM configuration to a module + * The type and names of added ports strongly depend on the + * organization of SRAMs. + * 1. Standalone SRAMs: + * two ports will be added, which are regular output and inverted output + * 2. Scan-chain Flip-flops: + * two ports will be added, which are the head of scan-chain + * and the tail of scan-chain + * IMPORTANT: the port size will be forced to 1 in this case + * because the head and tail are both 1-bit ports!!! + * 3. Memory decoders: + * 2-4 ports will be added, depending on the ports available in the SRAM + * Among these, two ports are mandatory: BL and WL + * The other two ports are optional: BLB and WLB + * Note that the constraints are correletated to the checking rules + * in check_circuit_library() + ********************************************************************/ +std::vector generate_sram_port_names(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type) { + std::vector sram_port_names; + /* Prepare a list of port types to be added, the port type will be used to create port names */ + std::vector model_port_types; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + model_port_types.push_back(SPICE_MODEL_PORT_INPUT); + model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); + break; + case SPICE_SRAM_SCAN_CHAIN: + model_port_types.push_back(SPICE_MODEL_PORT_INPUT); + model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); + break; + case SPICE_SRAM_MEMORY_BANK: { + std::vector ports_to_search; + ports_to_search.push_back(SPICE_MODEL_PORT_BL); + ports_to_search.push_back(SPICE_MODEL_PORT_WL); + ports_to_search.push_back(SPICE_MODEL_PORT_BLB); + ports_to_search.push_back(SPICE_MODEL_PORT_WLB); + /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */ + for (const auto& port_to_search : ports_to_search) { + std::vector found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search); + if (0 == found_port.size()) { + continue; + } + model_port_types.push_back(port_to_search); + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + /* Add ports to the module manager */ + for (size_t iport = 0; iport < model_port_types.size(); ++iport) { + /* Create a port */ + std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]); + sram_port_names.push_back(port_name); + } + + return sram_port_names; +} + +/******************************************************************** + * Generate a list of ports that are used for SRAM configuration to a module + * 1. Standalone SRAMs: + * use the suggested port_size + * 2. Scan-chain Flip-flops: + * IMPORTANT: the port size will be forced to 1 in this case + * 3. Memory decoders: + * use the suggested port_size + ********************************************************************/ +size_t generate_sram_port_size(const e_sram_orgz sram_orgz_type, + const size_t& num_config_bits) { + size_t sram_port_size = num_config_bits; + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + /* CCFF head/tail are single-bit ports */ + sram_port_size = 1; + break; + case SPICE_SRAM_MEMORY_BANK: + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); + } + + return sram_port_size; +} + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h index fef569c5a..852b14b99 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h @@ -24,4 +24,11 @@ bool check_mem_config_bus(const e_sram_orgz& sram_orgz_type, const BasicPort& config_bus, const size_t& local_expected_msb); +std::vector generate_sram_port_names(const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz sram_orgz_type); + +size_t generate_sram_port_size(const e_sram_orgz sram_orgz_type, + const size_t& num_config_bits); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index c5e07776c..1d9d507f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -442,9 +442,9 @@ void ModuleManager::add_child_module(const ModuleId& parent_module, const Module /* Update fast look-up for nets */ size_t instance_id = net_lookup_[parent_module][child_module].size(); + net_lookup_[parent_module][child_module].emplace_back(); /* Find the ports for the child module and update the fast look-up */ for (ModulePortId child_port : port_ids_[child_module]) { - net_lookup_[parent_module][child_module].emplace_back(); net_lookup_[parent_module][child_module][instance_id][child_port].resize(ports_[child_module][child_port].get_width(), ModuleNetId::INVALID()); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 5e325e44a..9e151d2ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -133,6 +133,7 @@ void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_ module_manager.set_port_preproc_flag(module_id, port_id, preproc_flag); } + /******************************************************************** * Add a list of ports that are used for SRAM configuration to a module * in the module manager @@ -157,60 +158,15 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_sram_orgz sram_orgz_type, - const size_t& port_size) { - /* Prepare a list of port types to be added, the port type will be used to create port names */ - std::vector model_port_types; - /* Prepare a list of module port types to be added, the port type will be used to specify the port type in Verilog/SPICE module */ - std::vector module_port_types; - /* Actual port size may be different from user specification. Think about CCFF */ - size_t sram_port_size = port_size; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - model_port_types.push_back(SPICE_MODEL_PORT_INPUT); - module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); - model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); - module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); - break; - case SPICE_SRAM_SCAN_CHAIN: - model_port_types.push_back(SPICE_MODEL_PORT_INPUT); - module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); - model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); - module_port_types.push_back(ModuleManager::MODULE_OUTPUT_PORT); - /* CCFF head/tail are single-bit ports */ - sram_port_size = 1; - break; - case SPICE_SRAM_MEMORY_BANK: { - std::vector ports_to_search; - ports_to_search.push_back(SPICE_MODEL_PORT_BL); - ports_to_search.push_back(SPICE_MODEL_PORT_WL); - ports_to_search.push_back(SPICE_MODEL_PORT_BLB); - ports_to_search.push_back(SPICE_MODEL_PORT_WLB); - /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */ - for (const auto& port_to_search : ports_to_search) { - std::vector found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search); - if (0 == found_port.size()) { - continue; - } - model_port_types.push_back(port_to_search); - module_port_types.push_back(ModuleManager::MODULE_INPUT_PORT); - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } + const size_t& num_config_bits) { + std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); + size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); /* Add ports to the module manager */ - for (size_t iport = 0; iport < model_port_types.size(); ++iport) { - /* Create a port */ - std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]); - BasicPort module_port(port_name, sram_port_size); + for (const std::string& sram_port_name : sram_port_names) { /* Add generated ports to the ModuleManager */ - module_manager.add_port(module_id, module_port, module_port_types[iport]); + BasicPort sram_port(sram_port_name, sram_port_size); + module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT); } } @@ -222,9 +178,9 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, * This function will also check that each pb_type port is actually exist * in the linked circuit model *******************************************************************/ -void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - t_pb_type* cur_pb_type) { +void add_primitive_pb_type_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_pb_type* cur_pb_type) { /* Find the inout ports required by the primitive pb_type, and add them to the module */ std::vector pb_type_inout_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT); @@ -263,6 +219,32 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, } } +/******************************************************************** + * Add ports of a pb_type block to module manager + * This function is designed for non-primitive pb_types, which are + * NOT linked to any circuit model. + * Actually, this makes things much simpler. + * We just iterate over all the ports and add it to the module + * with the naming convention + *******************************************************************/ +void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_pb_type* cur_pb_type) { + /* Create a type-to-type mapping between module ports and pb_type ports */ + std::map port_type2type_map; + port_type2type_map[IN_PORT] = ModuleManager::MODULE_INPUT_PORT; + port_type2type_map[OUT_PORT] = ModuleManager::MODULE_OUTPUT_PORT; + port_type2type_map[INOUT_PORT] = ModuleManager::MODULE_INOUT_PORT; + + for (int port = 0; port < cur_pb_type->num_ports; ++port) { + t_port* pb_type_port = &(cur_pb_type->ports[port]); + BasicPort module_port(generate_pb_type_port_name(pb_type_port), pb_type_port->num_pins); + module_manager.add_port(module_id, module_port, port_type2type_map[pb_type_port->type]); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(module_id, module_port.get_name(), true); + } +} + /******************************************************************** * Identify if a net is a local wire inside a module: * A net is a local wire if it connects between two instances, @@ -832,6 +814,33 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager, } } +/******************************************************************** + * Find the size of configuration ports for module + *******************************************************************/ +size_t find_module_num_config_bits(const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type) { + std::vector config_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); + size_t num_config_bits = 0; /* By default it has zero configuration bits*/ + + /* Try to find these ports in the module manager */ + for (const std::string& config_port_name : config_port_names) { + ModulePortId module_port_id = module_manager.find_module_port(module_id, config_port_name); + /* If the port does not exist, go to the next */ + if (false == module_manager.valid_module_port_id(module_id, module_port_id)) { + continue; + } + /* The port exist, find the port size and update the num_config_bits if the size is larger */ + BasicPort module_port = module_manager.module_port(module_id, module_port_id); + num_config_bits = std::max((int)num_config_bits, (int)module_port.get_width()); + } + + return num_config_bits; +} + + /******************************************************************** * TODO: * Add the port-to-port connection between a logic module diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 78155d325..d135f6596 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -37,7 +37,11 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_sram_orgz sram_orgz_type, - const size_t& port_size); + const size_t& num_config_bits); + +void add_primitive_pb_type_ports_to_module_manager(ModuleManager& module_manager, + const ModuleId& module_id, + t_pb_type* cur_pb_type); void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, const ModuleId& module_id, @@ -72,4 +76,10 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager, const e_sram_orgz& sram_orgz_type, const e_spice_model_design_tech& mem_tech); +size_t find_module_num_config_bits(const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 848e61a87..5ef9ae6d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -115,7 +115,7 @@ void print_verilog_primitive_block(std::fstream& fp, * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P, * no ports of the circuit model will be missing here */ - add_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); + add_primitive_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); /* Add configuration ports */ /* Shared SRAM ports*/ @@ -273,43 +273,83 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, ModuleId pb_module = module_manager.add_module(pb_module_name); VTR_ASSERT(ModuleId::INVALID() != pb_module); - /* TODO: Add ports to the Verilog module */ + /* Add ports to the Verilog module */ + add_pb_type_ports_to_module_manager(module_manager, pb_module, physical_pb_type); - /* TODO: Count I/O (INOUT) ports from the sub-modules under this Verilog module */ - /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module */ - /* TODO: Count SRAM ports from the sub-modules under this Verilog module */ - /* TODO: Count formal verification ports from the sub-modules under this Verilog module */ - - /* Print Verilog module declaration */ - print_verilog_module_declaration(fp, module_manager, pb_module); - - /* Comment lines */ - print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); - - /* TODO: Print local wires (bus wires for memory configuration) */ - /* - dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info, - stamped_sram_cnt, - stamped_sram_cnt + num_conf_bits - 1); + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus */ + std::vector memory_modules; + std::vector memory_instances; + + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* TODO: Add all the child Verilog modules as instances */ + for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { + /* Get the name and module id for this child pb_type */ + std::string child_pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); + ModuleId child_pb_module = module_manager.find_module(child_pb_module_name); + /* We must have one valid id! */ + VTR_ASSERT(true == module_manager.valid_module_id(child_pb_module)); - /* TODO: Instanciate all the child Verilog modules */ - for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ipb++) { /* Each child may exist multiple times in the hierarchy*/ - for (int jpb = 0; jpb < physical_pb_type->modes[physical_mode_index].pb_type_children[ipb].num_pb; jpb++) { + for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { /* we should make sure this placement index == child_pb_type[jpb] */ - VTR_ASSERT(jpb == physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb].placement_index); + VTR_ASSERT(inst == physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst].placement_index); + + size_t child_instance_id = module_manager.num_instance(pb_module, child_pb_module); + /* Add the memory module as a child of primitive module */ + module_manager.add_child_module(pb_module, child_pb_module); + /* TODO: Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, child_pb_module, + circuit_lib, sram_model, + cur_sram_orgz_info->type)) { + memory_modules.push_back(child_pb_module); + memory_instances.push_back(child_instance_id); + } } } - /* TODO: Print programmable/non-programmable interconnections inside the Verilog module */ + + /* TODO: Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + + /* TODO: Count I/O (INOUT) ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + + /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + + /* TODO: Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + + /* TODO: Add modules and nets for programmable/non-programmable interconnections + * inside the Verilog module */ /* dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index, is_explicit_mapping); */ - /* Print an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(pb_module)); + + /* Comment lines */ + print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); + + /* Write the verilog module */ + write_verilog_module_to_file(fp, module_manager, pb_module, use_explicit_mapping); print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); From 85644d07aec5d061c62d536e5b29958c163bdbc8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 12 Oct 2019 21:55:53 -0600 Subject: [PATCH 288/482] refactoring pb interc Verilog generation --- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 402 +++++++++++++++++- .../verilog/verilog_module_writer.cpp | 2 +- 2 files changed, 393 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 5ef9ae6d1..6da5e196f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -193,6 +193,386 @@ void print_verilog_primitive_block(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * This function add a net for a pin-to-pin connection defined in pb_graph + * It supports two cases for the pin-to-pin connection + * 1. The net source is a pb_graph_pin while the net sink is a pin of an interconnection + * 2. The net source is a pin of an interconnection while the net sink a pb_graph_pin + * The type is enabled by an argument pin2pin_interc_type + *******************************************************************/ +static +void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, + const ModuleId& pb_module, + const ModuleId& interc_module, + const size_t& interc_instance, + const std::string& interc_port_name, + const std::string& module_name_prefix, + t_pb_graph_pin* pb_graph_pin, + const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { + + ModuleNetId pin2pin_net = module_manager.create_module_net(pb_module); + + /* Find port and pin ids for the module, which is the parent of pb_graph_pin */ + t_pb_type* pin_pb_type = pb_graph_pin->parent_node->pb_type; + /* Find the module contains the source pin */ + ModuleId pin_pb_type_module = module_manager.find_module(generate_physical_block_module_name(module_name_prefix, pin_pb_type)); + VTR_ASSERT(true == module_manager.valid_module_id(pin_pb_type_module)); + size_t pin_pb_type_instance = 0; /* Deposite the instance with a zero, which is the default value is the source module is actually pb_module itself */ + if (pin_pb_type_module != pb_module) { + pin_pb_type_instance = pb_graph_pin->parent_node->placement_index; + /* Ensure this is an valid instance */ + VTR_ASSERT(pin_pb_type_instance < module_manager.num_instance(pb_module, pin_pb_type_module)); + } + ModulePortId pin_module_port_id = module_manager.find_module_port(pin_pb_type_module, generate_pb_type_port_name(pb_graph_pin->port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(pin_pb_type_module, pin_module_port_id)); + size_t pin_module_pin_id = pb_graph_pin->pin_number; + /* Ensure this is an valid pin index */ + VTR_ASSERT(pin_module_pin_id < module_manager.module_port(pin_pb_type_module, pin_module_port_id).get_width()); + + /* Find port and pin ids for the interconnection module */ + ModulePortId interc_port_id = module_manager.find_module_port(interc_module, interc_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(interc_module, interc_port_id)); + size_t interc_pin_id = 0; + /* Ensure this is an valid pin index */ + VTR_ASSERT(interc_pin_id < module_manager.module_port(interc_module, interc_port_id).get_width()); + + /* Add net sources and sinks: + * For input-to-input connection, net_source is pin_graph_pin, while net_sink is interc pin + * For output-to-output connection, net_source is interc pin, while net_sink is pin_graph pin + */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + module_manager.add_module_net_source(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); + module_manager.add_module_net_sink(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); + break; + case OUTPUT2OUTPUT_INTERC: + module_manager.add_module_net_source(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); + module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins + * /|\ + * | + * input_pins, edges, output_pins + * + * This function does the following task: + * 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Add mux/direct connection as a child module to pb_module + * 4. Add nets related to the mux/direction + *******************************************************************/ +static +void add_module_pb_graph_pin_interc(ModuleManager& module_manager, + const ModuleId& pb_module, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& module_name_prefix, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* physical_mode) { + /* Find the number of fan-in and detailed interconnection information + * related to the destination pb_graph_pin + */ + int fan_in = 0; + t_interconnect* cur_interc = NULL; + find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); + + /* If no interconnection is needed, we can return early */ + if ((NULL == cur_interc) || (0 == fan_in)) { + return; + } + + /* Initialize the interconnection type that will be physically implemented in module */ + enum e_interconnect verilog_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); + + /* Branch on the type of physical implementation, + * We add instances of programmable interconnection + */ + switch (verilog_interc_type) { + case DIRECT_INTERC: { + /* Ensure direct interc has only one fan-in */ + VTR_ASSERT(1 == fan_in); + + /* For more than one mode defined, the direct interc has more than one input_edge , + * We need to find which edge is connected the pin we want + */ + int iedge = 0; + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { + break; + } + } + t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + + /* Ensure that circuit model is a wire */ + VTR_ASSERT(SPICE_MODEL_WIRE == circuit_lib.model_type(cur_interc->circuit_model)); + /* Find the wire module in the module manager */ + ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(cur_interc->circuit_model)); + VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); + /* Get the instance id and add an instance of wire */ + size_t wire_instance = module_manager.num_instance(pb_module, wire_module); + module_manager.add_child_module(pb_module, wire_module); + + /* Find input ports of the wire module */ + std::vector wire_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ + VTR_ASSERT(1 == wire_model_inputs.size()); + /* Find output ports of the wire module */ + std::vector wire_model_outputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */ + VTR_ASSERT(1 == wire_model_outputs.size()); + + /* Add nets to connect the wires to ports of pb_module */ + /* First net is to connect input of src_pb_graph_node to input of the wire module */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + wire_module, wire_instance, + circuit_lib.port_lib_name(wire_model_inputs[0]), + module_name_prefix, + src_pb_graph_pin, + INPUT2INPUT_INTERC); + + /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + wire_module, wire_instance, + circuit_lib.port_lib_name(wire_model_outputs[0]), + module_name_prefix, + des_pb_graph_pin, + OUTPUT2OUTPUT_INTERC); + break; + } + case COMPLETE_INTERC: + case MUX_INTERC: { + /* Check: MUX should have at least 2 fan_in */ + VTR_ASSERT((2 == fan_in)||(2 < fan_in)); + /* Ensure that circuit model is a MUX */ + VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.model_type(cur_interc->circuit_model)); + /* Find the wire module in the module manager */ + ModuleId mux_module = module_manager.find_module(generate_mux_subckt_name(circuit_lib, cur_interc->circuit_model, fan_in, std::string())); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + + /* Instanciate the MUX */ + size_t mux_instance = module_manager.num_instance(pb_module, mux_module); + module_manager.add_child_module(pb_module, mux_module); + + /* TODO: Instance the memory module for the MUX */ + /* TODO: Create nets to wire between the MUX and it memory module */ + /* TODO: Create nets to wire between the MUX and PB module */ + + int ipin = 0; + for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (physical_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + continue; + } + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + ipin++; + } + VTR_ASSERT(ipin == fan_in); + + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } + + return; +} + + +/******************************************************************** + * Add modules and nets for programmable/non-programmable interconnections + * which end to a port of pb_module + * This function will add the following elements to a module + * 1. Instances of direct connections + * 2. Instances of programmable routing multiplexers + * 3. nets to connect direct connections/multiplexer + * + * +-----------------------------------------+ + * | + * | +--------------+ +------------+ + * |--->| |--->| | + * |... | Multiplexers |... | | + * |--->| |--->| | + * | +--------------+ | des_pb_ | + * | | graph_node | + * | +--------------+ | | + * |--->| |--->| | + * | ...| Direct |... | | + * |--->| Connections |--->| | + * | +--------------+ +------------+ + * | + * +----------------------------------------+ + + * + * Note: this function should be run after ALL the child pb_modules + * have been added to the pb_module and ALL the ports defined + * in pb_type have been added to the pb_module!!! + * + ********************************************************************/ +static +void add_module_pb_graph_port_interc(ModuleManager& module_manager, + const ModuleId& pb_module, + const CircuitLibrary& circuit_lib, + t_pb_graph_node* des_pb_graph_node, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& module_name_prefix, + const e_spice_pb_port_type& pb_port_type, + t_mode* physical_mode) { + switch (pb_port_type) { + case SPICE_PB_PORT_INPUT: { + for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { + /* Get the selected edge of current pin*/ + add_module_pb_graph_pin_interc(module_manager, pb_module, + circuit_lib, + cur_sram_orgz_info, + module_name_prefix, + &(des_pb_graph_node->input_pins[iport][ipin]), + physical_mode); + } + } + break; + } + case SPICE_PB_PORT_OUTPUT: { + for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { + add_module_pb_graph_pin_interc(module_manager, pb_module, + circuit_lib, + cur_sram_orgz_info, + module_name_prefix, + &(des_pb_graph_node->output_pins[iport][ipin]), + physical_mode); + } + } + break; + } + case SPICE_PB_PORT_CLOCK: { + for (int iport = 0; iport < des_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_clock_pins[iport]; ++ipin) { + add_module_pb_graph_pin_interc(module_manager, pb_module, + circuit_lib, + cur_sram_orgz_info, + module_name_prefix, + &(des_pb_graph_node->clock_pins[iport][ipin]), + physical_mode); + } + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid pb port type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * TODO: + * Add modules and nets for programmable/non-programmable interconnections + * inside a module of pb_type + * This function will add the following elements to a module + * 1. Instances of direct connections + * 2. Instances of programmable routing multiplexers + * 3. nets to connect direct connections/multiplexer + * + * Pb_module + * +--------------------------------------------------------------+ + * | | + * | +--------------+ +------------+ +--------------+ | + * |--->| |--->| |--->| |--->| + * |... | Multiplexers |... | |... | Multiplexers |... | + * |--->| |--->| |--->| |--->| + * | +--------------+ | Child | +--------------+ | + * | | Pb_modules | | + * | +--------------+ | | +--------------+ | + * |--->| |--->| |--->| |--->| + * | ...| Direct |... | |... | Direct |... | + * |--->| Connections |--->| |--->| Connections |--->| + * | +--------------+ +------------+ +--------------+ | + * | | + * +--------------------------------------------------------------+ + * + * Note: this function should be run after ALL the child pb_modules + * have been added to the pb_module and ALL the ports defined + * in pb_type have been added to the pb_module!!! + * + ********************************************************************/ +static +void add_module_pb_graph_interc(ModuleManager& module_manager, + const ModuleId& pb_module, + const CircuitLibrary& circuit_lib, + t_pb_graph_node* physical_pb_graph_node, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& module_name_prefix, + const int& physical_mode_index) { + /* Check cur_pb_graph_node*/ + if (NULL == physical_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Assign physical mode */ + t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + add_module_pb_graph_port_interc(module_manager, pb_module, + circuit_lib, + physical_pb_graph_node, + cur_sram_orgz_info, + module_name_prefix, + SPICE_PB_PORT_OUTPUT, + physical_mode); + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (int child = 0; child < physical_pb_graph_node->pb_type->modes[physical_mode_index].num_pb_type_children; ++child) { + for (int inst = 0; inst < physical_pb_graph_node->pb_type->modes[physical_mode_index].pb_type_children[child].num_pb; ++inst) { + t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][child][inst]); + /* For each child_pb_graph_node input pins*/ + add_module_pb_graph_port_interc(module_manager, pb_module, + circuit_lib, + child_pb_graph_node, + cur_sram_orgz_info, + module_name_prefix, + SPICE_PB_PORT_INPUT, + physical_mode); + + /* For each child_pb_graph_node clock pins*/ + add_module_pb_graph_port_interc(module_manager, pb_module, + circuit_lib, + child_pb_graph_node, + cur_sram_orgz_info, + module_name_prefix, + SPICE_PB_PORT_CLOCK, + physical_mode); + } + } +} + + /******************************************************************** * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) * This function will traverse the graph of complex logic block (t_pb_graph_node) @@ -298,13 +678,16 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* Each child may exist multiple times in the hierarchy*/ for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - /* we should make sure this placement index == child_pb_type[jpb] */ - VTR_ASSERT(inst == physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst].placement_index); - size_t child_instance_id = module_manager.num_instance(pb_module, child_pb_module); + /* Ensure the instance of this child module is the same as placement index, + * This check is necessary because placement_index is used to identify instance id for children + * when adding local interconnection for this pb_type + */ + VTR_ASSERT(child_instance_id == (size_t)physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst].placement_index); + /* Add the memory module as a child of primitive module */ module_manager.add_child_module(pb_module, child_pb_module); - /* TODO: Identify if this sub module includes configuration bits, + /* Identify if this sub module includes configuration bits, * we will update the memory module and instance list */ if (0 < find_module_num_config_bits(module_manager, child_pb_module, @@ -338,12 +721,11 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* TODO: Add modules and nets for programmable/non-programmable interconnections * inside the Verilog module */ - /* - dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, - cur_pb_graph_node, mode_index, - is_explicit_mapping); - */ - + add_module_pb_graph_interc(module_manager, pb_module, + circuit_lib, physical_pb_graph_node, + cur_sram_orgz_info, + pb_module_name_prefix, + physical_mode_index); /* Comment lines */ print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index 0103015c7..b7f25c0f9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -71,7 +71,7 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag } else { net_name = module_manager.module_name(net_src_module); net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_"); - net_name += module_manager.module_port(module_id, net_src_port).get_name(); + net_name += module_manager.module_port(net_src_module, net_src_port).get_name(); } return BasicPort(net_name, net_src_pin, net_src_pin); From 0f50251b3b8d964d997d8ac57a8d8a5461d22cbd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 13 Oct 2019 11:11:19 -0600 Subject: [PATCH 289/482] add mux and associated memory modules in refactoring Verilog generation for pb_types --- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 137 +++++++++++++----- 1 file changed, 98 insertions(+), 39 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 6da5e196f..90cdf3bcf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -206,6 +206,7 @@ void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, const ModuleId& interc_module, const size_t& interc_instance, const std::string& interc_port_name, + const size_t& interc_pin_id, const std::string& module_name_prefix, t_pb_graph_pin* pb_graph_pin, const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { @@ -232,7 +233,6 @@ void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, /* Find port and pin ids for the interconnection module */ ModulePortId interc_port_id = module_manager.find_module_port(interc_module, interc_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(interc_module, interc_port_id)); - size_t interc_pin_id = 0; /* Ensure this is an valid pin index */ VTR_ASSERT(interc_pin_id < module_manager.module_port(interc_module, interc_port_id).get_width()); @@ -274,8 +274,9 @@ void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, static void add_module_pb_graph_pin_interc(ModuleManager& module_manager, const ModuleId& pb_module, + std::vector& memory_modules, + std::vector& memory_instances, const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& module_name_prefix, t_pb_graph_pin* des_pb_graph_pin, t_mode* physical_mode) { @@ -294,6 +295,15 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Initialize the interconnection type that will be physically implemented in module */ enum e_interconnect verilog_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); + /* Find input ports of the wire module */ + std::vector interc_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ + /* Find output ports of the wire module */ + std::vector interc_model_outputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */ + + /* Ensure that we have only 1 input port and 1 output port, this is valid for both wire and MUX */ + VTR_ASSERT(1 == interc_model_inputs.size()); + VTR_ASSERT(1 == interc_model_outputs.size()); + /* Branch on the type of physical implementation, * We add instances of programmable interconnection */ @@ -321,19 +331,17 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Get the instance id and add an instance of wire */ size_t wire_instance = module_manager.num_instance(pb_module, wire_module); module_manager.add_child_module(pb_module, wire_module); - - /* Find input ports of the wire module */ - std::vector wire_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ - VTR_ASSERT(1 == wire_model_inputs.size()); - /* Find output ports of the wire module */ - std::vector wire_model_outputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */ - VTR_ASSERT(1 == wire_model_outputs.size()); + + /* Ensure input and output ports of the wire model has only 1 pin respectively */ + VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0])); + VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); /* Add nets to connect the wires to ports of pb_module */ /* First net is to connect input of src_pb_graph_node to input of the wire module */ add_module_pb_graph_pin2pin_net(module_manager, pb_module, wire_module, wire_instance, - circuit_lib.port_lib_name(wire_model_inputs[0]), + circuit_lib.port_lib_name(interc_model_inputs[0]), + 0, /* wire input port has only 1 pin */ module_name_prefix, src_pb_graph_pin, INPUT2INPUT_INTERC); @@ -341,7 +349,8 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ add_module_pb_graph_pin2pin_net(module_manager, pb_module, wire_module, wire_instance, - circuit_lib.port_lib_name(wire_model_outputs[0]), + circuit_lib.port_lib_name(interc_model_outputs[0]), + 0, /* wire output port has only 1 pin */ module_name_prefix, des_pb_graph_pin, OUTPUT2OUTPUT_INTERC); @@ -361,33 +370,77 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, size_t mux_instance = module_manager.num_instance(pb_module, mux_module); module_manager.add_child_module(pb_module, mux_module); - /* TODO: Instance the memory module for the MUX */ - /* TODO: Create nets to wire between the MUX and it memory module */ - /* TODO: Create nets to wire between the MUX and PB module */ - - int ipin = 0; + /* Instanciate a memory module for the MUX */ + std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, + cur_interc->circuit_model, + fan_in, + std::string(verilog_mem_posfix)); + ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); + size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module); + module_manager.add_child_module(pb_module, mux_mem_module); + + /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */ + add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, + mux_module, mux_instance, + mux_mem_module, mux_mem_instance, + circuit_lib, cur_interc->circuit_model); + + /* Update memory modules and memory instance list */ + memory_modules.push_back(mux_mem_module); + memory_instances.push_back(mux_mem_instance); + + /* Ensure output port of the MUX model has only 1 pin, + * while the input port size is dependent on the architecture conext, + * no constaints on the circuit model definition + */ + VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); + + /* Create nets to wire between the MUX and PB module */ + /* Add a net to wire the inputs of the multiplexer to its source pb_graph_pin inside pb_module + * Here is a tricky part. + * Not every input edges from the destination pb_graph_pin is used in the physical_model of pb_type + * So, we will skip these input edges when building nets + */ + int mux_input_pin_id = 0; for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { if (physical_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { continue; } + /* Ensure that the input edge has only 1 input pin! */ check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - ipin++; + t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + /* Add a net, set its source and sink */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + mux_module, mux_instance, + circuit_lib.port_lib_name(interc_model_inputs[0]), + mux_input_pin_id, + module_name_prefix, + src_pb_graph_pin, + INPUT2INPUT_INTERC); + mux_input_pin_id++; } - VTR_ASSERT(ipin == fan_in); + /* Ensure all the fan_in has been covered */ + VTR_ASSERT(mux_input_pin_id == fan_in); + /* Add a net to wire the output of the multiplexer to des_pb_graph_pin */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + mux_module, mux_instance, + circuit_lib.port_lib_name(interc_model_outputs[0]), + 0, /* MUX should have only 1 pin in its output port */ + module_name_prefix, + des_pb_graph_pin, + OUTPUT2OUTPUT_INTERC); break; } default: vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + "(File:%s,[LINE%d])Invalid interconnection type for %s [at Architecture XML LINE%d]!\n", __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); exit(1); } - - return; } - /******************************************************************** * Add modules and nets for programmable/non-programmable interconnections * which end to a port of pb_module @@ -421,9 +474,10 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, static void add_module_pb_graph_port_interc(ModuleManager& module_manager, const ModuleId& pb_module, + std::vector& memory_modules, + std::vector& memory_instances, const CircuitLibrary& circuit_lib, t_pb_graph_node* des_pb_graph_node, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& module_name_prefix, const e_spice_pb_port_type& pb_port_type, t_mode* physical_mode) { @@ -433,8 +487,8 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager, for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { /* Get the selected edge of current pin*/ add_module_pb_graph_pin_interc(module_manager, pb_module, + memory_modules, memory_instances, circuit_lib, - cur_sram_orgz_info, module_name_prefix, &(des_pb_graph_node->input_pins[iport][ipin]), physical_mode); @@ -446,8 +500,8 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager, for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { add_module_pb_graph_pin_interc(module_manager, pb_module, + memory_modules, memory_instances, circuit_lib, - cur_sram_orgz_info, module_name_prefix, &(des_pb_graph_node->output_pins[iport][ipin]), physical_mode); @@ -459,8 +513,8 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager, for (int iport = 0; iport < des_pb_graph_node->num_clock_ports; ++iport) { for (int ipin = 0; ipin < des_pb_graph_node->num_clock_pins[iport]; ++ipin) { add_module_pb_graph_pin_interc(module_manager, pb_module, + memory_modules, memory_instances, circuit_lib, - cur_sram_orgz_info, module_name_prefix, &(des_pb_graph_node->clock_pins[iport][ipin]), physical_mode); @@ -470,7 +524,7 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager, } default: vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid pb port type!\n", + "(File:%s,[LINE%d]) Invalid pb port type!\n", __FILE__, __LINE__); exit(1); } @@ -510,9 +564,10 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager, static void add_module_pb_graph_interc(ModuleManager& module_manager, const ModuleId& pb_module, + std::vector& memory_modules, + std::vector& memory_instances, const CircuitLibrary& circuit_lib, t_pb_graph_node* physical_pb_graph_node, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& module_name_prefix, const int& physical_mode_index) { /* Check cur_pb_graph_node*/ @@ -534,9 +589,9 @@ void add_module_pb_graph_interc(ModuleManager& module_manager, * input_pins, edges, output_pins */ add_module_pb_graph_port_interc(module_manager, pb_module, + memory_modules, memory_instances, circuit_lib, physical_pb_graph_node, - cur_sram_orgz_info, module_name_prefix, SPICE_PB_PORT_OUTPUT, physical_mode); @@ -553,18 +608,18 @@ void add_module_pb_graph_interc(ModuleManager& module_manager, t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][child][inst]); /* For each child_pb_graph_node input pins*/ add_module_pb_graph_port_interc(module_manager, pb_module, + memory_modules, memory_instances, circuit_lib, child_pb_graph_node, - cur_sram_orgz_info, module_name_prefix, SPICE_PB_PORT_INPUT, physical_mode); /* For each child_pb_graph_node clock pins*/ add_module_pb_graph_port_interc(module_manager, pb_module, + memory_modules, memory_instances, circuit_lib, child_pb_graph_node, - cur_sram_orgz_info, module_name_prefix, SPICE_PB_PORT_CLOCK, physical_mode); @@ -668,7 +723,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, CircuitModelId sram_model = circuit_lib.model(mem_model->name); VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - /* TODO: Add all the child Verilog modules as instances */ + /* Add all the child Verilog modules as instances */ for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { /* Get the name and module id for this child pb_type */ std::string child_pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); @@ -699,6 +754,15 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, } } + /* Add modules and nets for programmable/non-programmable interconnections + * inside the Verilog module + */ + add_module_pb_graph_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, physical_pb_graph_node, + pb_module_name_prefix, + physical_mode_index); + /* TODO: Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), * we just need to find all the global ports from the child modules and build a list of it @@ -719,13 +783,8 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, * we just need to find all the I/O ports from the child modules and build a list of it */ - /* TODO: Add modules and nets for programmable/non-programmable interconnections - * inside the Verilog module */ - add_module_pb_graph_interc(module_manager, pb_module, - circuit_lib, physical_pb_graph_node, - cur_sram_orgz_info, - pb_module_name_prefix, - physical_mode_index); + /* TODO: Add module nets to connect memory cells inside */ + /* Comment lines */ print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); From cab4bd680783cd6671e85782a055efe0d635b721 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 13 Oct 2019 16:23:22 -0600 Subject: [PATCH 290/482] add gpio ports to pb_type modules --- vpr7_x2p/libarchfpga/SRC/device_port.cpp | 50 ++++++++++++ vpr7_x2p/libarchfpga/SRC/device_port.h | 5 ++ .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 9 ++- .../vpr/SRC/fpga_x2p/base/module_manager.h | 15 ++-- .../fpga_x2p/base/module_manager_utils.cpp | 77 +++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 6 ++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 11 +-- .../verilog/verilog_module_writer.cpp | 45 ++++++++++- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 2 + 9 files changed, 208 insertions(+), 12 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.cpp b/vpr7_x2p/libarchfpga/SRC/device_port.cpp index 04ee4facf..d02229970 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.cpp +++ b/vpr7_x2p/libarchfpga/SRC/device_port.cpp @@ -83,6 +83,34 @@ std::vector BasicPort::pins() const { return pin_indices; } +/* Check if a port can be merged with this port: their name should be the same */ +bool BasicPort::mergeable(const BasicPort& portA) const { + return (0 == this->get_name().compare(portA.get_name())); +} + +/* Check if a port is contained by this port: + * this function will check if the (LSB, MSB) of portA + * is contained by the (LSB, MSB) of this port + */ +bool BasicPort::contained(const BasicPort& portA) const { + return ( lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_ ); +} + +/* Overloaded operators */ +/* Two ports are the same only when: + * 1. port names are the same + * 2. LSBs are the same + * 3. MSBs are the same + */ +bool BasicPort::operator== (const BasicPort& portA) const { + if ( (0 == this->get_name().compare(portA.get_name())) + && (this->get_lsb() == portA.get_lsb()) + && (this->get_msb() == portA.get_msb()) ) { + return true; + } + return false; +} + /* Mutators */ /* copy */ void BasicPort::set(const BasicPort& basic_port) { @@ -218,6 +246,28 @@ void BasicPort::combine(const BasicPort& port) { return; } +/* A restricted combine function for two ports, + * Following conditions will be applied: + * 1. the two ports have the same name + * Note: you must run mergable() function first + * to make sure this assumption is valid + * 2. the new MSB will be the maximum MSB of the two ports + * 3. the new LSB will be the minimum LSB of the two ports + * 4. both ports should be valid!!! + */ +void BasicPort::merge(const BasicPort& portA) { + VTR_ASSERT(true == this->mergeable(portA)); + VTR_ASSERT(true == this->is_valid() && true == portA.is_valid()); + /* We skip merging if the portA is already contained by this port */ + if (true == this->contained(portA)) { + return; + } + /* LSB follows the minium LSB of the two ports */ + lsb_ = std::min((int)lsb_, (int)portA.get_lsb()); + /* MSB follows the minium MSB of the two ports */ + msb_ = std::max((int)msb_, (int)portA.get_msb()); + return; +} /* Internal functions */ /* Make a port to be invalid: msb < lsb */ diff --git a/vpr7_x2p/libarchfpga/SRC/device_port.h b/vpr7_x2p/libarchfpga/SRC/device_port.h index eb4a91b86..149a7f78b 100644 --- a/vpr7_x2p/libarchfpga/SRC/device_port.h +++ b/vpr7_x2p/libarchfpga/SRC/device_port.h @@ -17,6 +17,8 @@ class BasicPort { BasicPort(const std::string& name, const size_t& lsb, const size_t& msb); BasicPort(const std::string& name, const size_t& width); BasicPort(const BasicPort& basic_port); /* Copy constructor */ + public: /* Overloaded operators */ + bool operator== (const BasicPort& portA) const; public: /* Accessors */ size_t get_width() const; /* get the port width */ size_t get_msb() const; /* get the LSB */ @@ -24,6 +26,8 @@ class BasicPort { std::string get_name() const; /* get the name */ bool is_valid() const; /* check if port size is valid > 0 */ std::vector pins() const; /* Make a range of the pin indices */ + bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */ + bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */ public: /* Mutators */ void set(const BasicPort& basic_port); /* copy */ void set_name(const std::string& name); /* set the port LSB and MSB */ @@ -37,6 +41,7 @@ class BasicPort { bool counter_rotate(const size_t& offset); /* counter rotate */ void reset(); /* Reset to initial port */ void combine(const BasicPort& port); /* Combine two ports */ + void merge(const BasicPort& portA); private: /* internal functions */ void make_invalid(); /* Make a port invalid */ private: /* Internal Data */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 1d9d507f2..46a9b7d74 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -21,6 +21,13 @@ ModuleManager::module_range ModuleManager::modules() const { return vtr::make_range(ids_.begin(), ids_.end()); } +/* Find all the ports belonging to a module */ +ModuleManager::module_port_range ModuleManager::module_ports(const ModuleId& module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(module)); + return vtr::make_range(port_ids_[module].begin(), port_ids_[module].end()); +} + /* Find all the nets belonging to a module */ ModuleManager::module_net_range ModuleManager::module_nets(const ModuleId& module) const { /* Validate the module_id */ @@ -94,7 +101,7 @@ std::string ModuleManager::module_name(const ModuleId& module_id) const { /* Get the string of a module port type */ std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const { - std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; + std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; return MODULE_PORT_TYPE_STRING[port_type]; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 6bba3a67a..4c1222e0f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -25,11 +25,12 @@ class ModuleManager { public: /* Private data structures */ enum e_module_port_type { - MODULE_GLOBAL_PORT, - MODULE_INOUT_PORT, - MODULE_INPUT_PORT, - MODULE_OUTPUT_PORT, - MODULE_CLOCK_PORT, + MODULE_GLOBAL_PORT, /* Global inputs */ + MODULE_GPIO_PORT, /* General-purpose IOs, which are data IOs of the fabric */ + MODULE_INOUT_PORT, /* Normal (non-global) inout ports */ + MODULE_INPUT_PORT, /* Normal (non-global) input ports */ + MODULE_OUTPUT_PORT, /* Normal (non-global) output ports */ + MODULE_CLOCK_PORT, /* Nromal (non-global) clock ports*/ NUM_MODULE_PORT_TYPES }; @@ -37,11 +38,13 @@ class ModuleManager { public: /* Types and ranges */ typedef vtr::vector::const_iterator module_iterator; + typedef vtr::vector::const_iterator module_port_iterator; typedef vtr::vector::const_iterator module_net_iterator; typedef vtr::vector::const_iterator module_net_src_iterator; typedef vtr::vector::const_iterator module_net_sink_iterator; typedef vtr::Range module_range; + typedef vtr::Range module_port_range; typedef vtr::Range module_net_range; typedef vtr::Range module_net_src_range; typedef vtr::Range module_net_sink_range; @@ -49,6 +52,8 @@ class ModuleManager { public: /* Public aggregators */ /* Find all the modules */ module_range modules() const; + /* Find all the ports belonging to a module */ + module_port_range module_ports(const ModuleId& module) const; /* Find all the nets belonging to a module */ module_net_range module_nets(const ModuleId& module) const; /* Find all the child modules under a parent module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 9e151d2ad..752a7f740 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -840,6 +840,83 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager, return num_config_bits; } +/******************************************************************** + * Add global ports to the module: + * In this function, the following tasks are done: + * 1. find all the GPIO ports from the child modules and build a list of it, + * 2. Merge all the GPIO ports with the same name + * 3. add the ports to the pb_module + * + * Note: This function should be call ONLY after all the sub modules (instances) + * have been added to the pb_module! + * Otherwise, some GPIO ports of the sub modules may be missed! + *******************************************************************/ +void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id) { + std::vector gpio_ports_to_add; + + /* Iterate over the child modules */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + /* Find all the global ports, whose port type is special */ + for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) { + /* If this port is not mergeable, we update the list */ + bool is_mergeable = false; + for (BasicPort& gpio_port_to_add : gpio_ports_to_add) { + if (false == gpio_port_to_add.mergeable(gpio_port)) { + continue; + } + is_mergeable = true; + /* For mergeable ports, we do a strong merge */ + gpio_port_to_add.merge(gpio_port); + break; + } + if (false == is_mergeable) { + /* Reach here, this is an unique gpio port, update the list */ + gpio_ports_to_add.push_back(gpio_port); + } + } + } + + /* Add the gpio ports for the module */ + for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) { + module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT); + } +} + +/******************************************************************** + * Add GPIO ports to the module: + * In this function, the following tasks are done: + * 1. find all the global ports from the child modules and build a list of it, + * 2. add the ports to the pb_module + * + * Note: This function should be call ONLY after all the sub modules (instances) + * have been added to the pb_module! + * Otherwise, some global ports of the sub modules may be missed! + *******************************************************************/ +void add_module_global_ports_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id) { + std::vector global_ports_to_add; + + /* Iterate over the child modules */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + /* Find all the global ports, whose port type is special */ + for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) { + /* Search in the global port list to be added, if this is unique, we update the list */ + std::vector::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port); + if (it != global_ports_to_add.end()) { + continue; + } + /* Reach here, this is an unique global port, update the list */ + global_ports_to_add.push_back(global_port); + } + } + + /* Add the global ports for the module */ + for (const BasicPort& global_port_to_add : global_ports_to_add) { + module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_GLOBAL_PORT); + } +} + /******************************************************************** * TODO: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index d135f6596..3fc390961 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -82,4 +82,10 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager, const CircuitModelId& sram_model, const e_sram_orgz& sram_orgz_type); +void add_module_global_ports_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id); + +void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 90cdf3bcf..3e39af9e6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -30,6 +30,7 @@ #include "verilog_module_writer.h" #include "verilog_grid.h" + /******************************************************************** * Print Verilog modules of a primitive node in the pb_graph_node graph * This generic function can support all the different types of primitive nodes @@ -108,7 +109,7 @@ void print_verilog_primitive_block(std::fstream& fp, std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); for (auto port : primitive_model_inout_ports) { BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INOUT_PORT); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); } } /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here. @@ -627,7 +628,6 @@ void add_module_pb_graph_interc(ModuleManager& module_manager, } } - /******************************************************************** * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) * This function will traverse the graph of complex logic block (t_pb_graph_node) @@ -763,15 +763,17 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, pb_module_name_prefix, physical_mode_index); - /* TODO: Add global ports to the pb_module: + /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), * we just need to find all the global ports from the child modules and build a list of it */ + add_module_global_ports_from_child_modules(module_manager, pb_module); - /* TODO: Count I/O (INOUT) ports from the sub-modules under this Verilog module + /* Count GPIO ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ + add_module_gpio_ports_from_child_modules(module_manager, pb_module); /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), @@ -785,7 +787,6 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* TODO: Add module nets to connect memory cells inside */ - /* Comment lines */ print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index b7f25c0f9..908bc8555 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -7,12 +7,24 @@ * You should NOT modify any content of the module manager * Please use const keyword to restrict this! *******************************************************************/ +#include #include "vtr_assert.h" #include "fpga_x2p_utils.h" #include "module_manager_utils.h" #include "verilog_writer_utils.h" #include "verilog_module_writer.h" +/******************************************************************** + * Generate the name of a local wire for a undriven port inside Verilog + * module + *******************************************************************/ +static +std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager, + const ModuleId& module, + const ModulePortId& module_port_id) { + return module_manager.module_port(module, module_port_id).get_name(); +} + /******************************************************************** * Name a net for a local wire for a verilog module * 1. If this is a local wire, name it after the __ @@ -113,6 +125,36 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu } } + /* Local wires could also happen for undriven ports of child module */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + for (size_t instance : module_manager.child_module_instances(module_id, child)) { + for (const ModulePortId& child_port_id : module_manager.module_ports(child)) { + BasicPort child_port = module_manager.module_port(child, child_port_id); + std::vector undriven_pins; + for (size_t child_pin : child_port.pins()) { + /* Find the net linked to the pin */ + ModuleNetId net = module_manager.module_instance_port_net(module_id, child, instance, + child_port_id, child_pin); + /* We only care undriven ports */ + if (ModuleNetId::INVALID() == net) { + undriven_pins.push_back(child_pin); + } + } + if (true == undriven_pins.empty()) { + continue; + } + /* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */ + BasicPort instance_port; + instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id)); + /* We give the same port name as child module, this case happens to global ports */ + instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()), + *std::max_element(undriven_pins.begin(), undriven_pins.end())); + + local_wires.push_back(instance_port); + } + } + } + return local_wires; } @@ -225,6 +267,7 @@ void write_verilog_instance_to_file(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; @@ -255,7 +298,7 @@ void write_verilog_instance_to_file(std::fstream& fp, BasicPort instance_port; if (ModuleNetId::INVALID() == net) { /* We give the same port name as child module, this case happens to global ports */ - instance_port.set_name(module_manager.module_port(child_module, child_port_id).get_name()); + instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id)); instance_port.set_width(child_pin, child_pin); } else { /* Find the name for this child port */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 344509935..ad7ddc5f0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -108,6 +108,7 @@ void print_verilog_module_definition(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; @@ -166,6 +167,7 @@ void print_verilog_module_ports(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INPUT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT; port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT; From b5813997615f671c10a7820475ac2ce40c24939c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 13 Oct 2019 17:45:32 -0600 Subject: [PATCH 291/482] add memory ports and nets to intermediate pb_types --- .../fpga_x2p/base/module_manager_utils.cpp | 68 +++++++++++++++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 12 ++++ .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 26 +++++-- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 4 files changed, 102 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 752a7f740..f401fdd3c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -814,6 +814,31 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager, } } +/******************************************************************** + * Find the size of shared(reserved) configuration ports for module + *******************************************************************/ +size_t find_module_num_shared_config_bits(const ModuleManager& module_manager, + const ModuleId& module_id) { + std::vector shared_config_port_names; + shared_config_port_names.push_back(generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB)); + shared_config_port_names.push_back(generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL)); + size_t num_shared_config_bits = 0; /* By default it has zero configuration bits*/ + + /* Try to find these ports in the module manager */ + for (const std::string& shared_config_port_name : shared_config_port_names) { + ModulePortId module_port_id = module_manager.find_module_port(module_id, shared_config_port_name); + /* If the port does not exist, go to the next */ + if (false == module_manager.valid_module_port_id(module_id, module_port_id)) { + continue; + } + /* The port exist, find the port size and update the num_config_bits if the size is larger */ + BasicPort module_port = module_manager.module_port(module_id, module_port_id); + num_shared_config_bits = std::max((int)num_shared_config_bits, (int)module_port.get_width()); + } + + return num_shared_config_bits; +} + /******************************************************************** * Find the size of configuration ports for module *******************************************************************/ @@ -917,6 +942,49 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager, } } +/******************************************************************** + * Find the number of shared configuration bits for a module + * by selected the maximum number of shared configuration bits of child modules + * + * Note: This function should be call ONLY after all the sub modules (instances) + * have been added to the pb_module! + * Otherwise, some global ports of the sub modules may be missed! + *******************************************************************/ +size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id) { + size_t num_shared_config_bits = 0; + + /* Iterate over the child modules */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_module_num_shared_config_bits(module_manager, child)); + } + + return num_shared_config_bits; +} + +/******************************************************************** + * Find the number of configuration bits for a module + * by summing up the number of configuration bits of child modules + * + * Note: This function should be call ONLY after all the sub modules (instances) + * have been added to the pb_module! + * Otherwise, some global ports of the sub modules may be missed! + *******************************************************************/ +size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type) { + size_t num_config_bits = 0; + + /* Iterate over the child modules */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + num_config_bits += find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type); + } + + return num_config_bits; +} + /******************************************************************** * TODO: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 3fc390961..b0884192b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -76,6 +76,9 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager, const e_sram_orgz& sram_orgz_type, const e_spice_model_design_tech& mem_tech); +size_t find_module_num_shared_config_bits(const ModuleManager& module_manager, + const ModuleId& module_id); + size_t find_module_num_config_bits(const ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, @@ -88,4 +91,13 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager, void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, const ModuleId& module_id); +size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id); + +size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + const e_sram_orgz& sram_orgz_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 3e39af9e6..94b0d98e1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -775,17 +775,33 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, */ add_module_gpio_ports_from_child_modules(module_manager, pb_module); - /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module + /* Count shared SRAM ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, pb_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, pb_module, module_num_shared_config_bits); + } - /* TODO: Count SRAM ports from the sub-modules under this Verilog module + /* Count SRAM ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type); + printf("Add %lu configuration bits to module %s\n", module_num_config_bits, module_manager.module_name(pb_module).c_str()); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); + } - /* TODO: Add module nets to connect memory cells inside */ + /* Add module nets to connect memory cells inside + * This is a one-shot addition that covers all the memory modules in this pb module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, pb_module, + memory_modules, memory_instances, + cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); + } /* Comment lines */ print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); @@ -857,8 +873,8 @@ void print_verilog_grid(ModuleManager& module_manager, /* Print preprocessing flags */ print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */ - /* TODO: use a Depth-First Search Algorithm to print the sub-modules + /* Print Verilog modules for all the pb_types/pb_graph_nodes + * use a Depth-First Search Algorithm to print the sub-modules * Note: DFS is the right way. Do NOT use BFS. * DFS can guarantee that all the sub-modules can be registered properly * to its parent in module manager diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index ad7ddc5f0..f2a26b347 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -468,7 +468,7 @@ std::vector combine_verilog_ports(const std::vector& ports /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */ bool merged = false; for (auto& merged_port : merged_ports) { - if (0 != port.get_name().compare(merged_port.get_name())) { + if (false == port.mergeable(merged_port)) { /* Unable to merge, Go to next */ continue; } From 6793c67c8d6821c7f9ce02d9852f91d7da9e4b05 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 13 Oct 2019 21:07:30 -0600 Subject: [PATCH 292/482] refactored pb_type and grid Verilog generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 1 - .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 313 +++++++++++++++++- 2 files changed, 298 insertions(+), 16 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 41ccade95..1023ab66d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -359,7 +359,6 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, return port_name; } - /********************************************************************* * Generate the port name for a reserved sram port, i.e., BLB/WL port * When port_type is BLB, a string denoting to the reserved BLB port is generated diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 94b0d98e1..0e736121d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -7,6 +7,7 @@ #include /* Header files from external libs */ +#include "vtr_geometry.h" #include "util.h" #include "vtr_assert.h" #include "circuit_library_utils.h" @@ -30,6 +31,211 @@ #include "verilog_module_writer.h" #include "verilog_grid.h" +/******************************************************************** + * Find the side where I/O pins locate on a grid I/O block + * 1. I/O grids on the top side of FPGA only have ports on its bottom side + * 2. I/O grids on the right side of FPGA only have ports on its left side + * 3. I/O grids on the bottom side of FPGA only have ports on its top side + * 4. I/O grids on the left side of FPGA only have ports on its right side + *******************************************************************/ +static +e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor, + const e_side& border_side) { + VTR_ASSERT(IO_TYPE == grid_type_descriptor); + Side side_manager(border_side); + return side_manager.get_opposite(); +} + +/******************************************************************** + * Add ports/pins to a grid module + * This function will iterate over all the pins that are defined + * in type_descripter and give a name by its height, side and index + * + * In particular, for I/O grid, only part of the ports on required + * on a specific side. + *******************************************************************/ +static +void add_grid_module_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + t_type_ptr grid_type_descriptor, + const e_side& border_side) { + /* Ensure that we have a valid grid_type_descriptor */ + VTR_ASSERT(NULL != grid_type_descriptor); + + /* Find the pin side for I/O grids*/ + std::vector grid_pin_sides; + /* For I/O grids, we care only one side + * Otherwise, we will iterate all the 4 sides + */ + if (IO_TYPE == grid_type_descriptor) { + grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); + } else { + grid_pin_sides.push_back(TOP); + grid_pin_sides.push_back(RIGHT); + grid_pin_sides.push_back(BOTTOM); + grid_pin_sides.push_back(LEFT); + } + + /* Create a map between pin class type and grid pin direction */ + std::map pin_type2type_map; + pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT; + pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT; + + /* Iterate over sides, height and pins */ + for (const e_side& side : grid_pin_sides) { + for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) { + for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) { + if (1 != grid_type_descriptor->pinloc[iheight][side][ipin]) { + continue; + } + /* Reach here, it means this pin is on this side */ + int class_id = grid_type_descriptor->pin_class[ipin]; + e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; + /* Generate the pin name, + * we give a empty coordinate but it will not be used (see details in the function + */ + vtr::Point dummy_coordinate; + std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false); + BasicPort grid_port(port_name, 0, 0); + /* Add the port to the module */ + module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); + } + } + } +} + +/******************************************************************** + * Add module nets to connect a port of child pb_module + * to the grid module + *******************************************************************/ +static +void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, + const ModuleId& grid_module, + const ModuleId& child_module, + const size_t& child_instance, + t_type_ptr grid_type_descriptor, + t_pb_graph_pin* pb_graph_pin, + const e_side& border_side, + const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { + /* Find the pin side for I/O grids*/ + std::vector grid_pin_sides; + /* For I/O grids, we care only one side + * Otherwise, we will iterate all the 4 sides + */ + if (IO_TYPE == grid_type_descriptor) { + grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); + } else { + grid_pin_sides.push_back(TOP); + grid_pin_sides.push_back(RIGHT); + grid_pin_sides.push_back(BOTTOM); + grid_pin_sides.push_back(LEFT); + } + + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster + + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity; + int pin_height = grid_type_descriptor->pin_height[grid_pin_index]; + for (const e_side& side : grid_pin_sides) { + if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + continue; + } + /* Reach here, it means this pin is on this side */ + /* Create a net to connect the grid pin to child module pin */ + ModuleNetId net = module_manager.create_module_net(grid_module); + /* Find the port in grid_module */ + vtr::Point dummy_coordinate; + std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false); + ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); + /* Grid port always has only 1 pin, it is assumed when adding these ports to the module + * if you need a change, please also change the port adding codes + */ + size_t grid_module_pin_id = 0; + /* Find the port in child module */ + std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); + ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); + size_t child_module_pin_id = pb_graph_pin->pin_number; + /* Add net sources and sinks: + * For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin + * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin + */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); + module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); + break; + case OUTPUT2OUTPUT_INTERC: + module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); + module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + } +} + + +/******************************************************************** + * Add module nets to connect ports/pins of a grid module + * to its child modules + * This function will iterate over all the pins that are defined + * in type_descripter and find the corresponding pin in the top + * pb_graph_node of the grid + *******************************************************************/ +static +void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + const ModuleId& child_module, + const size_t& child_instance, + t_type_ptr grid_type_descriptor, + const e_side& border_side) { + /* Ensure that we have a valid grid_type_descriptor */ + VTR_ASSERT(NULL != grid_type_descriptor); + t_pb_graph_node* top_pb_graph_node = grid_type_descriptor->pb_graph_head; + VTR_ASSERT(NULL != top_pb_graph_node); + + for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { + add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, + child_module, child_instance, + grid_type_descriptor, + &(top_pb_graph_node->input_pins[iport][ipin]), + border_side, + INPUT2INPUT_INTERC); + + } + } + + for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { + add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, + child_module, child_instance, + grid_type_descriptor, + &(top_pb_graph_node->output_pins[iport][ipin]), + border_side, + OUTPUT2OUTPUT_INTERC); + } + } + + for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { + add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, + child_module, child_instance, + grid_type_descriptor, + &(top_pb_graph_node->clock_pins[iport][ipin]), + border_side, + INPUT2INPUT_INTERC); + } + } +} /******************************************************************** * Print Verilog modules of a primitive node in the pb_graph_node graph @@ -789,7 +995,6 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, * we just need to find all the I/O ports from the child modules and build a list of it */ size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type); - printf("Add %lu configuration bits to module %s\n", module_num_config_bits, module_manager.module_name(pb_module).c_str()); if (0 < module_num_config_bits) { add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); } @@ -890,27 +1095,105 @@ void print_verilog_grid(ModuleManager& module_manager, print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - /* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Create a Verilog Module for the top-level physical block, and add to module manager */ + std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); + ModuleId grid_module = module_manager.add_module(grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - /* TODO: Add ports to the module */ + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - /* TODO: Print the module definition for the top-level Verilog module of physical block */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish printing ports */ + /* Generate the name of the Verilog module for this pb_type */ + std::string pb_module_name_prefix(grid_verilog_file_name_prefix); + /* Add side string to the name if it is valid */ + if (NUM_SIDES != border_side) { + Side side_manager(border_side); + pb_module_name_prefix += std::string(side_manager.to_string()); + pb_module_name_prefix += std::string("_"); + } + std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type); + ModuleId pb_module = module_manager.find_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - /* Print an empty line a splitter */ - fp << std::endl; - - /* TODO: instanciate all the sub modules */ + /* Add all the sub modules */ for (int iz = 0; iz < phy_block_type->capacity; ++iz) { + size_t pb_instance_id = module_manager.num_instance(grid_module, pb_module); + module_manager.add_child_module(grid_module, pb_module); + /* Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, pb_module, + circuit_lib, sram_model, + cur_sram_orgz_info->type)) { + memory_modules.push_back(pb_module); + memory_instances.push_back(pb_instance_id); + } } - /* Put an end to the top-level Verilog module of physical block */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); + /* Add grid ports(pins) to the module */ + add_grid_module_pb_type_ports(module_manager, grid_module, + phy_block_type, border_side); + + /* Add module nets to connect the pb_type ports to sub modules */ + for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { + add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, + pb_module, child_instance, + phy_block_type, border_side); + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, grid_module); + + /* Count GPIO ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + add_module_gpio_ports_from_child_modules(module_manager, grid_module); + + /* Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, grid_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, grid_module, module_num_shared_config_bits); + } + + /* Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, grid_module, circuit_lib, sram_model, cur_sram_orgz_info->type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, grid_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); + } + + /* Add module nets to connect memory cells inside + * This is a one-shot addition that covers all the memory modules in this pb module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, grid_module, + memory_modules, memory_instances, + cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); + } + + /* Write the verilog module */ + print_verilog_comment(fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); + write_verilog_module_to_file(fp, module_manager, grid_module, use_explicit_mapping); + + print_verilog_comment(fp, std::string("----- END Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); /* Add an empty line as a splitter */ fp << std::endl; From f779ad7ecf464a978d44d47e91dfbb68069ddde9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Oct 2019 15:53:04 -0600 Subject: [PATCH 293/482] bug fixing for global and gpio port wiring; start refactoring top-level module --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 18 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 + .../fpga_x2p/base/module_manager_utils.cpp | 135 ++++++++++++++---- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 11 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 127 ++++++++++++++++ .../SRC/fpga_x2p/verilog/verilog_top_module.h | 20 +++ 6 files changed, 287 insertions(+), 29 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 1023ab66d..40d99b7e6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -785,3 +785,21 @@ std::string generate_fpga_global_io_port_name(const std::string& prefix, return port_name; } + +/********************************************************************* + * Generate the module name for the top-level module + * The top-level module is actually the FPGA fabric + * We give a fixed name here, because it is independent from benchmark file + ********************************************************************/ +std::string generate_fpga_top_module_name() { + return std::string("fpga_top"); +} + +/********************************************************************* + * Generate the netlist name for the top-level module + * The top-level module is actually the FPGA fabric + * We give a fixed name here, because it is independent from benchmark file + ********************************************************************/ +std::string generate_fpga_top_netlist_name(const std::string& postfix) { + return std::string("fpga_top" + postfix); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 8d7826165..33bad6e40 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -146,4 +146,9 @@ std::string generate_pb_type_port_name(t_port* pb_type_port); std::string generate_fpga_global_io_port_name(const std::string& prefix, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); + +std::string generate_fpga_top_module_name(); + +std::string generate_fpga_top_netlist_name(const std::string& postfix); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index f401fdd3c..a703ee379 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -866,11 +866,12 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager, } /******************************************************************** - * Add global ports to the module: + * Add GPIO ports to the module: * In this function, the following tasks are done: * 1. find all the GPIO ports from the child modules and build a list of it, * 2. Merge all the GPIO ports with the same name * 3. add the ports to the pb_module + * 4. add module nets to connect to the GPIO ports of each sub module * * Note: This function should be call ONLY after all the sub modules (instances) * have been added to the pb_module! @@ -882,37 +883,84 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, /* Iterate over the child modules */ for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Find all the global ports, whose port type is special */ - for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) { - /* If this port is not mergeable, we update the list */ - bool is_mergeable = false; - for (BasicPort& gpio_port_to_add : gpio_ports_to_add) { - if (false == gpio_port_to_add.mergeable(gpio_port)) { - continue; + /* Iterate over the child instances */ + for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) { + /* Find all the global ports, whose port type is special */ + for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) { + /* If this port is not mergeable, we update the list */ + bool is_mergeable = false; + for (BasicPort& gpio_port_to_add : gpio_ports_to_add) { + if (false == gpio_port_to_add.mergeable(gpio_port)) { + continue; + } + is_mergeable = true; + /* For mergeable ports, we combine the port + * Note: do NOT use the merge() method! + * the GPIO ports should be accumulated by the sizes of ports + * not by the LSB/MSB range !!! + */ + gpio_port_to_add.combine(gpio_port); + break; + } + if (false == is_mergeable) { + /* Reach here, this is an unique gpio port, update the list */ + gpio_ports_to_add.push_back(gpio_port); } - is_mergeable = true; - /* For mergeable ports, we do a strong merge */ - gpio_port_to_add.merge(gpio_port); - break; - } - if (false == is_mergeable) { - /* Reach here, this is an unique gpio port, update the list */ - gpio_ports_to_add.push_back(gpio_port); } } } + /* Record the port id for each type of GPIO port */ + std::vector gpio_port_ids; /* Add the gpio ports for the module */ for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) { - module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT); + ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT); + gpio_port_ids.push_back(port_id); } + + /* Set up a counter for each type of GPIO port */ + std::vector gpio_port_lsb(gpio_ports_to_add.size(), 0); + /* Add module nets to connect the GPIOs of the module to the GPIOs of the sub module */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + /* Iterate over the child instances */ + for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) { + /* Find all the global ports, whose port type is special */ + for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GPIO_PORT)) { + BasicPort child_gpio_port = module_manager.module_port(child, child_gpio_port_id); + /* Find the port with the same name! */ + for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) { + if (false == gpio_ports_to_add[iport].mergeable(child_gpio_port)) { + continue; + } + /* For each pin of the child port, create a net and do wiring */ + for (const size_t& pin_id : child_gpio_port.pins()) { + /* Reach here, it means this is the port we want, create a net and configure its source and sink */ + ModuleNetId net = module_manager.create_module_net(module_id); + module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); + module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); + /* Update the LSB counter */ + gpio_port_lsb[iport]++; + } + /* We finish for this child gpio port */ + break; + } + } + } + } + + /* Check: all the lsb should now match the size of each GPIO port */ + for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) { + if (gpio_ports_to_add[iport].get_width() != gpio_port_lsb[iport]) + VTR_ASSERT(gpio_ports_to_add[iport].get_width() == gpio_port_lsb[iport]); + } } /******************************************************************** - * Add GPIO ports to the module: + * Add global ports to the module: * In this function, the following tasks are done: * 1. find all the global ports from the child modules and build a list of it, * 2. add the ports to the pb_module + * 3. add the module nets to connect the pb_module global ports to those of child modules * * Note: This function should be call ONLY after all the sub modules (instances) * have been added to the pb_module! @@ -924,21 +972,54 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager, /* Iterate over the child modules */ for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Find all the global ports, whose port type is special */ - for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) { - /* Search in the global port list to be added, if this is unique, we update the list */ - std::vector::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port); - if (it != global_ports_to_add.end()) { - continue; + /* Iterate over the child instances */ + for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) { + /* Find all the global ports, whose port type is special */ + for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) { + /* Search in the global port list to be added, if this is unique, we update the list */ + std::vector::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port); + if (it != global_ports_to_add.end()) { + continue; + } + /* Reach here, this is an unique global port, update the list */ + global_ports_to_add.push_back(global_port); } - /* Reach here, this is an unique global port, update the list */ - global_ports_to_add.push_back(global_port); } } + /* Record the port id for each type of global port */ + std::vector global_port_ids; /* Add the global ports for the module */ for (const BasicPort& global_port_to_add : global_ports_to_add) { - module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_GLOBAL_PORT); + ModulePortId port_id = module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_GLOBAL_PORT); + global_port_ids.push_back(port_id); + } + + /* Add module nets to connect the global ports of the module to the global ports of the sub module */ + /* Iterate over the child modules */ + for (const ModuleId& child : module_manager.child_modules(module_id)) { + /* Iterate over the child instances */ + for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) { + /* Find all the global ports, whose port type is special */ + for (ModulePortId child_global_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) { + BasicPort child_global_port = module_manager.module_port(child, child_global_port_id); + /* Search in the global port list to be added, find the port id */ + std::vector::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), child_global_port); + VTR_ASSERT(it != global_ports_to_add.end()); + ModulePortId module_global_port_id = global_port_ids[it - global_ports_to_add.begin()]; + BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id); + /* The global ports should match in size */ + VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width()); + /* For each pin of the child port, create a net and do wiring */ + for (size_t pin_id = 0; pin_id < child_global_port.pins().size(); ++pin_id) { + /* Reach here, it means this is the port we want, create a net and configure its source and sink */ + ModuleNetId net = module_manager.create_module_net(module_id); + module_manager.add_module_net_source(module_id, net, module_id, 0, module_global_port_id, module_global_port.pins()[pin_id]); + module_manager.add_module_net_sink(module_id, net, child, child_instance, child_global_port_id, child_global_port.pins()[pin_id]); + /* We finish for this child gpio port */ + } + } + } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 01c0b88a7..d29648472 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -45,6 +45,7 @@ #include "verilog_pbtypes.h" #include "verilog_grid.h" #include "verilog_routing.h" +#include "verilog_top_module.h" #include "verilog_compact_netlist.h" #include "verilog_top_testbench.h" #include "verilog_autocheck_top_testbench.h" @@ -298,7 +299,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, print_verilog_grids(module_manager, Arch.spice->circuit_lib, mux_lib, sram_verilog_orgz_info, std::string(src_dir_path), std::string(lb_dir_path), - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Generate the Verilog module of the configuration peripheral protocol * which loads bitstream to FPGA fabric @@ -313,7 +314,13 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* TODO: This is the old function, which will be deprecated when refactoring is done */ dump_verilog_config_peripherals(sram_verilog_orgz_info, src_dir_path, submodule_dir_path); - /* Dump top-level verilog */ + /* Print top-level Verilog module */ + print_verilog_top_module(module_manager, Arch.spice->circuit_lib, sram_verilog_orgz_info, + std::string(vpr_setup.FileNameOpts.ArchFile), + std::string(src_dir_path), + TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + + /* TODO: This is the old function, which will be deprecated when refactoring is done */ dump_compact_verilog_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, top_netlist_path, src_dir_path, submodule_dir_path, lb_dir_path, rr_dir_path, num_rr_nodes, rr_node, rr_node_indices, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp new file mode 100644 index 000000000..e6a2459dc --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -0,0 +1,127 @@ +/******************************************************************** + * This file includes functions that are used to print the top-level + * module for the FPGA fabric in Verilog format + *******************************************************************/ +#include + +#include "vtr_assert.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "module_manager_utils.h" + +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_module_writer.h" +#include "verilog_top_module.h" + +/******************************************************************** + * Print the top-level module for the FPGA fabric in Verilog format + * This function will + * 1. name the top-level module + * 2. include dependent netlists + * - User defined netlists + * - Auto-generated netlists + * 3. Add the submodules to the top-level graph + * 4. Add module nets to connect datapath ports + * 5. Add module nets/submodules to connect configuration ports + *******************************************************************/ +void print_verilog_top_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& arch_name, + const std::string& verilog_dir, + const bool& use_explicit_mapping) { + /* Create a module as the top-level fabric, and add it to the module manager */ + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.add_module(top_module_name); + + /* TODO: Add sub modules, which are grid, SB and CBX/CBY modules as instances */ + + /* TODO: Add module nets to connect the sub modules */ + + /* TODO: Add global ports to the top-level module */ + + /* TODO: Add module nets to connect the top-level ports to sub modules */ + + /* TODO: Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, top_module); + + /* TODO: Count GPIO ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + add_module_gpio_ports_from_child_modules(module_manager, top_module); + + /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, top_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, top_module, module_num_shared_config_bits); + } + + /* TODO: this should be added to the cur_sram_orgz_info !!! */ + t_spice_model* mem_model = NULL; + get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); + CircuitModelId sram_model = circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* TODO: Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, cur_sram_orgz_info->type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); + } + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* TODO: Add module nets to connect memory cells inside + * This is a one-shot addition that covers all the memory modules in this pb module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, top_module, + memory_modules, memory_instances, + cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); + } + + /* Start printing out Verilog netlists */ + /* Create the file name for Verilog netlist */ + std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + vpr_printf(TIO_MESSAGE_INFO, + "Writing Verilog Netlist for top-level module of FPGA fabric (%s)...\n", + verilog_fname.c_str()); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA architecture: " + std::string(arch_name))); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Write the module content in Verilog format */ + write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h new file mode 100644 index 000000000..acf5c2f14 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h @@ -0,0 +1,20 @@ +/******************************************************************** + * Header file for verilog_top_module.cpp + *******************************************************************/ +#ifndef VERILOG_TOP_MODULE_H +#define VERILOG_TOP_MODULE_H + +#include +#include "spice_types.h" +#include "circuit_library.h" +#include "module_manager.h" + +void print_verilog_top_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + t_sram_orgz_info* cur_sram_orgz_info, + const std::string& arch_name, + const std::string& verilog_dir, + const bool& use_explicit_mapping); + + +#endif From bd6a0c6a550bc591ea5337f96c7173a8c794beec Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Oct 2019 17:47:10 -0600 Subject: [PATCH 294/482] refactored grid instance addition to top module --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 16 ++- .../fpga_x2p/verilog/verilog_top_module.cpp | 133 ++++++++++++++++++ .../SRC/fpga_x2p/verilog/verilog_top_module.h | 4 + 3 files changed, 152 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index d29648472..96bb08c38 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -10,8 +10,10 @@ #include #include #include +#include /* Include vpr structs*/ +#include "vtr_geometry.h" #include "util.h" #include "physical_types.h" #include "vpr_types.h" @@ -315,7 +317,19 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, dump_verilog_config_peripherals(sram_verilog_orgz_info, src_dir_path, submodule_dir_path); /* Print top-level Verilog module */ - print_verilog_top_module(module_manager, Arch.spice->circuit_lib, sram_verilog_orgz_info, + vtr::Point device_size(nx + 2, ny + 2); + std::vector> grids; + /* Fill the grid vectors */ + grids.resize(device_size.x()); + for (size_t ix = 0; ix < device_size.x(); ++ix) { + grids[ix].resize(device_size.y()); + for (size_t iy = 0; iy < device_size.y(); ++iy) { + grids[ix][iy] = grid[ix][iy]; + } + } + print_verilog_top_module(module_manager, Arch.spice->circuit_lib, + device_size, grids, + sram_verilog_orgz_info, std::string(vpr_setup.FileNameOpts.ArchFile), std::string(src_dir_path), TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index e6a2459dc..52bf921e8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -3,9 +3,13 @@ * module for the FPGA fabric in Verilog format *******************************************************************/ #include +#include #include "vtr_assert.h" +#include "vpr_types.h" +#include "globals.h" + #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" #include "module_manager_utils.h" @@ -15,6 +19,128 @@ #include "verilog_module_writer.h" #include "verilog_top_module.h" + +/******************************************************************** + * Add a instance of a grid module to the top module + *******************************************************************/ +static +void add_top_module_grid_instance(ModuleManager& module_manager, + const ModuleId& top_module, + t_type_ptr grid_type, + const e_side& border_side) { + /* Find the module name for this type of grid */ + std::string grid_module_name_prefix(grid_verilog_file_name_prefix); + /* Add side string to the name if it is valid */ + if (NUM_SIDES != border_side) { + Side side_manager(border_side); + grid_module_name_prefix += std::string(side_manager.to_string()); + grid_module_name_prefix += std::string("_"); + } + std::string grid_module_name = generate_physical_block_module_name(grid_module_name_prefix, grid_type->pb_graph_head->pb_type); + ModuleId grid_module = module_manager.find_module(grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); + /* Add the module to top_module */ + module_manager.add_child_module(top_module, grid_module); +} + +/******************************************************************** + * Add all the grids as sub-modules across the fabric + * The grid modules are created for each unique type of grid (based + * on the type in data structure data_structure + * Here, we will iterate over the full fabric (coordinates) + * and instanciate the grid modules + * + * This function assumes an island-style floorplanning for FPGA fabric + * + * +-----------------------------------+ + * | I/O grids | + * | TOP side | + * +-----------------------------------+ + * + * +-----------+ +-----------------------------------+ +------------+ + * | | | | | | + * | I/O grids | | Core grids | | I/O grids | + * | LEFT side | | (CLB, Heterogeneous blocks, etc.) | | RIGHT side | + * | | | | | | + * +-----------+ +-----------------------------------+ +------------+ + * + * +-----------------------------------+ + * | I/O grids | + * | BOTTOM side | + * +-----------------------------------+ + * + *******************************************************************/ +static +void add_top_module_grid_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids) { + /* Instanciate core grids */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + /* Bypass EMPTY grid */ + if (EMPTY_TYPE == grids[ix][iy].type) { + continue; + } + /* Skip height > 1 tiles (mostly heterogeneous blocks) */ + if (0 < grids[ix][iy].offset) { + continue; + } + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE != grids[ix][iy].type); + /* Add a grid module to top_module*/ + add_top_module_grid_instance(module_manager, top_module, + grids[ix][iy].type, + NUM_SIDES); + } + } + + /* Instanciate I/O grids */ + /* Create the coordinate range for each side of FPGA fabric */ + std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; + std::map>> io_coordinates; + + /* TOP side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); + } + + /* RIGHT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); + } + + /* BOTTOM side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); + } + + /* LEFT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[LEFT].push_back(vtr::Point(0, iy)); + } + + /* Add instances of I/O grids to top_module */ + for (const e_side& io_side : io_sides) { + for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + /* Bypass EMPTY grid */ + if (EMPTY_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type) { + continue; + } + /* Skip height > 1 tiles (mostly heterogeneous blocks) */ + if (0 < grids[io_coordinate.x()][io_coordinate.y()].offset) { + continue; + } + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); + /* Add a grid module to top_module*/ + add_top_module_grid_instance(module_manager, top_module, + grids[io_coordinate.x()][io_coordinate.y()].type, + io_side); + } + } +} + /******************************************************************** * Print the top-level module for the FPGA fabric in Verilog format * This function will @@ -28,6 +154,8 @@ *******************************************************************/ void print_verilog_top_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, @@ -37,8 +165,13 @@ void print_verilog_top_module(ModuleManager& module_manager, ModuleId top_module = module_manager.add_module(top_module_name); /* TODO: Add sub modules, which are grid, SB and CBX/CBY modules as instances */ + /* Add all the grids across the fabric */ + add_top_module_grid_instances(module_manager, top_module, device_size, grids); + /* Add all the SBs across the fabric */ + /* Add all the CBX and CBYs across the fabric */ /* TODO: Add module nets to connect the sub modules */ + /* TODO: Add inter-CLB direct connections */ /* TODO: Add global ports to the top-level module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h index acf5c2f14..b5d4f3586 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h @@ -5,12 +5,16 @@ #define VERILOG_TOP_MODULE_H #include +#include "vtr_geometry.h" +#include "vpr_types.h" #include "spice_types.h" #include "circuit_library.h" #include "module_manager.h" void print_verilog_top_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, From 4b56b755f2ac99d6855c8387d03c805c0a3a376c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Oct 2019 21:06:10 -0600 Subject: [PATCH 295/482] refactored instanciation of routing modules in top module --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 3 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 74 ++++++++++++++++++- .../SRC/fpga_x2p/verilog/verilog_top_module.h | 3 + 3 files changed, 78 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 96bb08c38..a6fea293f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -328,10 +328,11 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, } } print_verilog_top_module(module_manager, Arch.spice->circuit_lib, - device_size, grids, + device_size, grids, device_rr_gsb, sram_verilog_orgz_info, std::string(vpr_setup.FileNameOpts.ArchFile), std::string(src_dir_path), + TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* TODO: This is the old function, which will be deprecated when refactoring is done */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 52bf921e8..60f347048 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -141,6 +141,73 @@ void add_top_module_grid_instances(ModuleManager& module_manager, } } +/******************************************************************** + * Add switch blocks across the FPGA fabric to the top-level module + *******************************************************************/ +static +void add_top_module_switch_block_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy) { + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + vtr::Point sb_coordinate(ix, iy); + /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator sb_coord(sb_coordinate.x(), sb_coordinate.y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + sb_coordinate.set_x(unique_mirror.get_sb_x()); + sb_coordinate.set_y(unique_mirror.get_sb_y()); + } + std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + /* Add the module to top_module */ + module_manager.add_child_module(top_module, sb_module); + } + } +} + +/******************************************************************** + * Add switch blocks across the FPGA fabric to the top-level module + *******************************************************************/ +static +void add_top_module_connection_block_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const t_rr_type& cb_type, + const bool& compact_routing_hierarchy) { + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + vtr::Point cb_coordinate(ix, iy); + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + const DeviceCoordinator cb_coordinator = rr_gsb.get_cb_coordinator(cb_type); + if ( (TRUE != is_cb_exist(cb_type, cb_coordinator.get_x(), cb_coordinator.get_y())) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator cb_coord(cb_coordinate.x(), cb_coordinate.y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); + cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); + } + std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); + ModuleId cb_module = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + /* Add the module to top_module */ + module_manager.add_child_module(top_module, cb_module); + } + } +} + /******************************************************************** * Print the top-level module for the FPGA fabric in Verilog format * This function will @@ -156,19 +223,24 @@ void print_verilog_top_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const vtr::Point& device_size, const std::vector>& grids, + const DeviceRRGSB& L_device_rr_gsb, t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, + const bool& compact_routing_hierarchy, const bool& use_explicit_mapping) { /* Create a module as the top-level fabric, and add it to the module manager */ std::string top_module_name = generate_fpga_top_module_name(); ModuleId top_module = module_manager.add_module(top_module_name); - /* TODO: Add sub modules, which are grid, SB and CBX/CBY modules as instances */ + /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ /* Add all the grids across the fabric */ add_top_module_grid_instances(module_manager, top_module, device_size, grids); /* Add all the SBs across the fabric */ + add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); /* Add all the CBX and CBYs across the fabric */ + add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); + add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); /* TODO: Add module nets to connect the sub modules */ /* TODO: Add inter-CLB direct connections */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h index b5d4f3586..33fefa2c4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h @@ -8,6 +8,7 @@ #include "vtr_geometry.h" #include "vpr_types.h" #include "spice_types.h" +#include "rr_blocks.h" #include "circuit_library.h" #include "module_manager.h" @@ -15,9 +16,11 @@ void print_verilog_top_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const vtr::Point& device_size, const std::vector>& grids, + const DeviceRRGSB& L_device_rr_gsb, t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, + const bool& compact_routing_hierarchy, const bool& use_explicit_mapping); From eaf8ecee86d0c1680e93692edc9f5729077d6be5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 15 Oct 2019 16:07:34 -0600 Subject: [PATCH 296/482] added _vpr.txt subscript to vpr log files --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 6a203e302..75ce54af7 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -621,7 +621,7 @@ def run_vpr(): min_channel_width = run_standard_vpr( args.top_module+".blif", args.fix_route_chan_width, - args.top_module+"_fr_chan_width.txt") + args.top_module+"_fr_chan_width_vpr.txt") logger.info("Fixed routing channel successfully routed with %d width" % min_channel_width) extract_vpr_stats(args.top_module+"_fr_chan_width.txt") From c034b871bb4c7eb169c00bd0a70df15b1ce04276 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 15 Oct 2019 16:08:25 -0600 Subject: [PATCH 297/482] Made activity file independent of power option --- openfpga_flow/scripts/run_fpga_flow.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 75ce54af7..2abaee97d 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -234,10 +234,11 @@ def main(): if (args.fpga_flow == "yosys_vpr"): logger.info('Running "yosys_vpr" Flow') run_yosys_with_abc() + # TODO Make it optional if activity file is provided + run_ace2() + run_pro_blif_3arg() if args.power: - run_ace2() - run_pro_blif_3arg() - run_rewrite_verilog() + run_rewrite_verilog() if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() # if (args.fpga_flow == "vtr"): @@ -642,13 +643,13 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): "--place_file", args.top_module+"_vpr.place", "--route_file", args.top_module+"_vpr.route", "--full_stats", "--nodisp", + "--activity_file", args.top_module+"_ace_out.act", ] if route_only: command += ["--route"] # Power options if args.power: command += ["--power", - "--activity_file", args.top_module+"_ace_out.act", "--tech_properties", args.power_tech] # packer options if args.vpr_timing_pack_off: @@ -700,7 +701,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command += ["--fpga_spice_testbench_load_extraction", "off"] # FPGA Verilog options - if (args.power and args.vpr_fpga_verilog): + if args.vpr_fpga_verilog: command += ["--fpga_verilog"] if args.vpr_fpga_verilog_dir: command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir] From 071757dc52400671ecdc01fbbc356919ed501726 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 15 Oct 2019 16:08:51 -0600 Subject: [PATCH 298/482] add module nets to connect grids and sbs --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 81 +++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 10 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 21 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 6 + .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 31 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 5 + .../SRC/fpga_x2p/verilog/verilog_routing.h | 1 + .../fpga_x2p/verilog/verilog_top_module.cpp | 382 ++++++++++++++++-- 8 files changed, 469 insertions(+), 68 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 40d99b7e6..3e1e14c57 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -669,6 +669,23 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, return generate_local_sram_port_name(prefix, mux_instance_id, port_type); } +/********************************************************************* + * Generate the prefix for naming a grid block netlist or a grid module + * This function will consider the io side and add it to the prefix + **********************************************************************/ +std::string generate_grid_block_prefix(const std::string& prefix, + const e_side& io_side) { + std::string block_prefix(prefix); + + if (NUM_SIDES != io_side) { + Side side_manager(io_side); + block_prefix += std::string("_"); + block_prefix += std::string(side_manager.to_string()); + } + + return block_prefix; +} + /********************************************************************* * Generate the netlist name of a grid block **********************************************************************/ @@ -680,9 +697,7 @@ std::string generate_grid_block_netlist_name(const std::string& block_name, std::string module_name(block_name); if (true == is_block_io) { - Side side_manager(io_side); - module_name += std::string("_"); - module_name += std::string(side_manager.to_string()); + module_name = generate_grid_block_prefix(block_name, io_side); } module_name += postfix; @@ -704,6 +719,7 @@ std::string generate_grid_block_module_name(const std::string& prefix, return module_name; } + /********************************************************************* * Generate the module name of a physical block * To ensure a unique name for each physical block inside the graph of complex blocks @@ -758,6 +774,65 @@ std::string generate_physical_block_module_name(const std::string& prefix, return module_name; } +/********************************************************************* + * This function is a wrapper for the function generate_physical_block_module_name() + * which can automatically decode the io_side and add a prefix + **********************************************************************/ +std::string generate_grid_physical_block_module_name(const std::string& prefix, + t_pb_type* pb_type, + const e_side& border_side) { + std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side); + return generate_physical_block_module_name(module_name_prefix, pb_type); +} + +/******************************************************************** + * This function try to infer if a grid locates at the border of a + * FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides + * 1. if this grid is on the border, it will return the side it locates, + * 2. if this grid is in the center, it will return an valid value NUM_SIDES + * + * In this function, we assume that the corner grids are actually empty! + * + * +-------+ +----------------------------+ +-------+ + * | EMPTY | | TOP side I/O | | EMPTY | + * +-------+ +----------------------------+ +-------+ + * + * +-------+ +----------------------------+ +-------+ + * | | | | | | + * | | | | | | + * | | | | | | + * | LEFT | | | | RIGHT | + * | side | | Core grids | | side | + * | I/O | | | | I/O | + * | | | | | | + * | | | | | | + * | | | | | | + * | | | | | | + * +-------+ +----------------------------+ +-------+ + * + * +-------+ +----------------------------+ +-------+ + * | EMPTY | | BOTTOM side I/O | | EMPTY | + * +-------+ +----------------------------+ +-------+ + *******************************************************************/ +e_side find_grid_border_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate) { + e_side grid_side = NUM_SIDES; + + if (device_size.y() - 1 == grid_coordinate.y()) { + return TOP; + } + if (device_size.x() - 1 == grid_coordinate.x()) { + return RIGHT; + } + if (0 == grid_coordinate.y()) { + return BOTTOM; + } + if (0 == grid_coordinate.x()) { + return LEFT; + } + + return grid_side; +} /********************************************************************* * Generate the port name of a Verilog module describing a pb_type diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 33bad6e40..b40a6e095 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -128,6 +128,9 @@ std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, const size_t& mux_instance_id, const e_spice_model_port_type& port_type); +std::string generate_grid_block_prefix(const std::string& prefix, + const e_side& io_side); + std::string generate_grid_block_netlist_name(const std::string& block_name, const bool& is_block_io, const e_side& io_side, @@ -141,6 +144,13 @@ std::string generate_grid_block_module_name(const std::string& prefix, std::string generate_physical_block_module_name(const std::string& prefix, t_pb_type* physical_pb_type); +std::string generate_grid_physical_block_module_name(const std::string& prefix, + t_pb_type* pb_type, + const e_side& border_side); + +e_side find_grid_border_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate); + std::string generate_pb_type_port_name(t_port* pb_type_port); std::string generate_fpga_global_io_port_name(const std::string& prefix, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index a202513eb..45844dd75 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -2136,6 +2136,27 @@ t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb, return (&(cur_hardlogic_pb->child_pbs[0][0])); } +/******************************************************************** + * Find the height of a pin in a grid definition + *******************************************************************/ +size_t find_grid_pin_height(const std::vector>& grids, + const vtr::Point& grid_coordinate, + const size_t& pin_index) { + t_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type; + + /* Return if this is an empty type */ + if ( (NULL == grid_type) + || (EMPTY_TYPE == grid_type)) { + return size_t(-1); + } + + /* Check if the pin index is in the range */ + VTR_ASSERT(pin_index < size_t(grid_type->num_pins)); + + /* Find the pin_height */ + return grid_type->pin_height[pin_index]; +} + int get_grid_pin_height(int grid_x, int grid_y, int pin_index) { int pin_height; t_type_ptr grid_type = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 954984e89..19c1e72f7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -4,7 +4,9 @@ /* Only include header files those are required by the data types in the following function declaration */ #include #include +#include "vtr_geometry.h" #include "device_port.h" +#include "vpr_types.h" #include "circuit_library.h" #include "fpga_x2p_types.h" #include "fpga_x2p_bitstream_utils.h" @@ -165,6 +167,10 @@ t_phy_pb* get_lut_child_phy_pb(t_phy_pb* cur_lut_pb, t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb, int mode_index); +size_t find_grid_pin_height(const std::vector>& grids, + const vtr::Point& grid_coordinate, + const size_t& pin_index); + int get_grid_pin_height(int grid_x, int grid_y, int pin_index); int get_grid_pin_side(int grid_x, int grid_y, int pin_index); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 0e736121d..4d377a115 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -70,10 +70,7 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager, if (IO_TYPE == grid_type_descriptor) { grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); } else { - grid_pin_sides.push_back(TOP); - grid_pin_sides.push_back(RIGHT); - grid_pin_sides.push_back(BOTTOM); - grid_pin_sides.push_back(LEFT); + grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } /* Create a map between pin class type and grid pin direction */ @@ -286,13 +283,7 @@ void print_verilog_primitive_block(std::fstream& fp, CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model; /* Generate the module name for this primitive pb_graph_node*/ - std::string primitive_module_name_prefix(grid_verilog_file_name_prefix); - /* Add side string to the name if it is valid, this is mainly for I/O block */ - if (NUM_SIDES != io_side) { - Side side_manager(io_side); - primitive_module_name_prefix += std::string(side_manager.to_string()); - primitive_module_name_prefix += std::string("_"); - } + std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); /* Create a module of the primitive LUT and register it to module manager */ @@ -901,13 +892,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, } /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix(grid_verilog_file_name_prefix); - /* Add side string to the name if it is valid */ - if (NUM_SIDES != io_side) { - Side side_manager(io_side); - pb_module_name_prefix += std::string(side_manager.to_string()); - pb_module_name_prefix += std::string("_"); - } + std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); /* Register the Verilog module in module manager */ @@ -1096,7 +1081,7 @@ void print_verilog_grid(ModuleManager& module_manager, print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); /* Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side); + std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); ModuleId grid_module = module_manager.add_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); @@ -1114,13 +1099,7 @@ void print_verilog_grid(ModuleManager& module_manager, /* Generate the name of the Verilog module for this pb_type */ std::string pb_module_name_prefix(grid_verilog_file_name_prefix); - /* Add side string to the name if it is valid */ - if (NUM_SIDES != border_side) { - Side side_manager(border_side); - pb_module_name_prefix += std::string(side_manager.to_string()); - pb_module_name_prefix += std::string("_"); - } - std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type); + std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side); ModuleId pb_module = module_manager.find_module(pb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 8c92880d6..13dc670f0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -5186,6 +5186,11 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ /********************************************************************* * Generate the port name for a Grid + * This is a wrapper function for generate_port_name() + * which can automatically decode the port name by the pin side and height + * + * TODO: This function is dependent on the global variable: grid + * This should be replaced by a local variable!!! *********************************************************************/ std::string generate_grid_side_port_name(const vtr::Point& coordinate, const e_side& side, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 1e12d0b45..8cb8b8ecf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -7,6 +7,7 @@ /* Include other header files which are dependency on the function declared below */ #include "mux_library.h" #include "module_manager.h" +#include "rr_blocks.h" void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 60f347048..d9091e9f1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -12,35 +12,56 @@ #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" #include "module_manager_utils.h" #include "verilog_global.h" +#include "verilog_routing.h" #include "verilog_writer_utils.h" #include "verilog_module_writer.h" #include "verilog_top_module.h" +/******************************************************************** + * Generate the name for a grid block, by considering + * 1. if it locates on the border with given device size + * 2. its type + * + * This function is mainly used in the top-level module generation + *******************************************************************/ +static +std::string generate_grid_block_module_name_in_top_module(const std::string& prefix, + const vtr::Point& device_size, + const std::vector>& grids, + const vtr::Point& grid_coordinate) { + /* Determine if the grid locates at the border */ + e_side border_side = find_grid_border_side(device_size, grid_coordinate); + + return generate_grid_block_module_name(prefix, std::string(grids[grid_coordinate.x()][grid_coordinate.y()].type->name), + IO_TYPE == grids[grid_coordinate.x()][grid_coordinate.y()].type, border_side); +} + /******************************************************************** * Add a instance of a grid module to the top module *******************************************************************/ static -void add_top_module_grid_instance(ModuleManager& module_manager, - const ModuleId& top_module, - t_type_ptr grid_type, - const e_side& border_side) { +size_t add_top_module_grid_instance(ModuleManager& module_manager, + const ModuleId& top_module, + t_type_ptr grid_type, + const e_side& border_side) { /* Find the module name for this type of grid */ std::string grid_module_name_prefix(grid_verilog_file_name_prefix); - /* Add side string to the name if it is valid */ - if (NUM_SIDES != border_side) { - Side side_manager(border_side); - grid_module_name_prefix += std::string(side_manager.to_string()); - grid_module_name_prefix += std::string("_"); - } - std::string grid_module_name = generate_physical_block_module_name(grid_module_name_prefix, grid_type->pb_graph_head->pb_type); + std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); + /* Record the instance id */ + size_t grid_instance = module_manager.num_instance(top_module, grid_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, grid_module); + + printf("Added grid module %s to top-level module\n", grid_module_name.c_str()); + + return grid_instance; } /******************************************************************** @@ -50,8 +71,12 @@ void add_top_module_grid_instance(ModuleManager& module_manager, * Here, we will iterate over the full fabric (coordinates) * and instanciate the grid modules * + * Return an 2-D array of instance ids of the grid modules that + * have been added + * * This function assumes an island-style floorplanning for FPGA fabric * + * * +-----------------------------------+ * | I/O grids | * | TOP side | @@ -71,10 +96,18 @@ void add_top_module_grid_instance(ModuleManager& module_manager, * *******************************************************************/ static -void add_top_module_grid_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids) { +std::vector> add_top_module_grid_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids) { + /* Reserve an array for the instance ids */ + std::vector> grid_instance_ids; + grid_instance_ids.resize(grids.size()); + for (size_t x = 0; x < grids.size(); ++x) { + /* Deposite an invalid value */ + grid_instance_ids[x].resize(grids[x].size(), size_t(-1)); + } + /* Instanciate core grids */ for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { @@ -89,9 +122,9 @@ void add_top_module_grid_instances(ModuleManager& module_manager, /* We should not meet any I/O grid */ VTR_ASSERT(IO_TYPE != grids[ix][iy].type); /* Add a grid module to top_module*/ - add_top_module_grid_instance(module_manager, top_module, - grids[ix][iy].type, - NUM_SIDES); + grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module, + grids[ix][iy].type, + NUM_SIDES); } } @@ -134,22 +167,33 @@ void add_top_module_grid_instances(ModuleManager& module_manager, /* We should not meet any I/O grid */ VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); /* Add a grid module to top_module*/ - add_top_module_grid_instance(module_manager, top_module, - grids[io_coordinate.x()][io_coordinate.y()].type, - io_side); + grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side); } } + + return grid_instance_ids; } /******************************************************************** * Add switch blocks across the FPGA fabric to the top-level module + * Return an 2-D array of instance ids of the switch blocks that + * have been added *******************************************************************/ static -void add_top_module_switch_block_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy) { +std::vector> add_top_module_switch_block_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy) { DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + + /* Reserve an array for the instance ids */ + std::vector> sb_instance_ids; + sb_instance_ids.resize(sb_range.get_x()); + for (size_t x = 0; x < sb_range.get_x(); ++x) { + /* Deposite an invalid value */ + sb_instance_ids[x].resize(sb_range.get_y(), size_t(-1)); + } + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { vtr::Point sb_coordinate(ix, iy); @@ -163,22 +207,35 @@ void add_top_module_switch_block_instances(ModuleManager& module_manager, std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); ModuleId sb_module = module_manager.find_module(sb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + /* Record the instance id */ + sb_instance_ids[ix][iy] = module_manager.num_instance(top_module, sb_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, sb_module); } } + + return sb_instance_ids; } /******************************************************************** * Add switch blocks across the FPGA fabric to the top-level module *******************************************************************/ static -void add_top_module_connection_block_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { +std::vector> add_top_module_connection_block_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const t_rr_type& cb_type, + const bool& compact_routing_hierarchy) { DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + /* Reserve an array for the instance ids */ + std::vector> cb_instance_ids; + cb_instance_ids.resize(cb_range.get_x()); + for (size_t x = 0; x < cb_range.get_x(); ++x) { + /* Deposite an invalid value */ + cb_instance_ids[x].resize(cb_range.get_y(), size_t(-1)); + } + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { vtr::Point cb_coordinate(ix, iy); @@ -202,10 +259,254 @@ void add_top_module_connection_block_instances(ModuleManager& module_manager, std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); ModuleId cb_module = module_manager.find_module(cb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + /* Record the instance id */ + cb_instance_ids[ix][iy] = module_manager.num_instance(top_module, cb_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, cb_module); } } + + return cb_instance_ids; +} + +/******************************************************************** + * Add module nets to connect a GSB to adjacent grid ports/pins + * as well as connection blocks + * This function will create nets for the following types of connections + * between grid output pins of Switch block and adjacent grids + * In this case, the net source is the grid pin, while the net sink + * is the switch block pin + * + * +------------+ +------------+ + * | | | | + * | Grid | | Grid | + * | [x][y+1] | | [x+1][y+1] | + * | | | | + * +------------+ +------------+ + * | | + * | +------------+ | + * +------>| |<-----+ + * | Switch | + * | Block | + * +------>| [x][y] |<-----+ + * | +------------+ | + * | | + * | | + * +------------+ +------------+ + * | | | | + * | Grid | | Grid | + * | [x][y] | | [x+1][y] | + * | | | | + * +------------+ +------------+ + * + *******************************************************************/ +static +void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const RRGSB& rr_gsb, + const std::vector>& sb_instance_ids) { + vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + /* Connect grid output pins (OPIN) to switch block grid pins */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + /* Collect source-related information */ + /* Generate the grid module name by considering if it locates on the border */ + vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); + std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); + ModuleId src_grid_module = module_manager.find_module(src_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); + size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; + size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num; + size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index); + std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false); + ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); + BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); + + /* Collect sink-related information */ + std::string sink_sb_module_name = generate_switch_block_module_name(sb_coordinate); + ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); + size_t sink_sb_instance = sb_instance_ids[sb_coordinate.x()][sb_coordinate.y()]; + vtr::Point sink_sb_port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + std::string sink_sb_port_name = generate_grid_side_port_name(sink_sb_port_coord, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + src_grid_pin_index); + ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); + BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(top_module); + /* Configure the net source */ + printf("src_grid_module_name: %s[%lu][%lu], src_grid_instance_id: %lu (%lu)\n", + src_grid_module_name.c_str(), + grid_coordinate.x(),grid_coordinate.y(), + src_grid_instance, module_manager.num_instance(top_module, src_grid_module)); + module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]); + } + } + } +} + +/******************************************************************** + * TODO: This function will create nets for the connections + * between grid input pins and connection blocks + * In this case, the net source is the connection block pin, + * while the net sink is the grid input + * + * +------------+ +------------------+ +------------+ + * | | | | | | + * | Grid |<-----| Connection Block |----->| Grid | + * | [x][y+1] | | Y-direction | | [x+1][y+1] | + * | | | [x][y+1] | | | + * +------------+ +------------------+ +------------+ + * ^ + * | + * +------------+ +------------------+ + * | Connection | | | + * | Block | | Switch Block | + * | X-direction| | [x][y] | + * | [x][y] | | | + * +------------+ +------------------+ + * | + * v + * +------------+ + * | | + * | Grid | + * | [x][y] | + * | | + * +------------+ + * + *******************************************************************/ +static +void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const RRGSB& rr_gsb, + const std::vector>& cbx_instance_ids, + const std::vector>& cby_instance_ids) { +} + +/******************************************************************** + * TODO: This function will create nets for the connections + * between connection block and switch block pins + * Two cases should be considered: + * a. The switch block pin denotes an input of a routing track + * The net source is an output of a routing track of connection block + * while the net sink is an input of a routing track of switch block + * b. The switch block pin denotes an output of a routing track + * The net source is an output of routing track of switch block + * while the net sink is an input of a routing track of connection block + * + * +------------+ +------------------+ +------------+ + * | | | | | | + * | Grid | | Connection Block | | Grid | + * | [x][y+1] | | Y-direction | | [x+1][y+1] | + * | | | [x][y+1] | | | + * +------------+ +------------------+ +------------+ + * | ^ + * v | + * +------------+ +------------------+ +------------+ + * | Connection |----->| |----->| Connection | + * | Block | | Switch Block | | Block | + * | X-direction|<-----| [x][y] |<-----| X-direction| + * | [x][y] | | | | [x+1][y] | + * +------------+ +------------------+ +------------+ + * | ^ + * v | + * +------------+ +------------------+ + * | | | | + * | Grid | | Connection Block | + * | [x][y] | | Y-direction | + * | | | [x][y] | + * +------------+ +------------------+ + + *******************************************************************/ +static +void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, + const ModuleId& top_module, + const RRGSB& rr_gsb, + const std::vector>& sb_instance_ids, + const std::vector>& cbx_instance_ids, + const std::vector>& cby_instance_ids) { +} + + +/******************************************************************** + * Add module nets to connect the grid ports/pins to Connection Blocks + * and Switch Blocks + * To make it easy, this function will iterate over all the General + * Switch Blocks (GSBs), through which we can obtain the coordinates + * of all the grids, connection blocks and switch blocks that are + * supposed to be connected tightly. + * + * As such, we have completed all the connection for each grid. + * There is no need to iterate over the grids + * + * +-------------------------+ +---------------------------------+ + * | | | Y-direction CB | + * | Grid[x][y+1] | | [x][y + 1] | + * | | +---------------------------------+ + * +-------------------------+ + * TOP SIDE + * +-------------+ +---------------------------------+ + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | X-direction | | | + * | CB | LEFT SIDE | Switch Block | RIGHT SIDE + * | [x][y] | | [x][y] | + * | | | | + * | | | CHAN_NODES CHAN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * +-------------+ +---------------------------------+ + * BOTTOM SIDE + *******************************************************************/ +static +void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& sb_instance_ids, + const std::vector>& cbx_instance_ids, + const std::vector>& cby_instance_ids) { + DeviceCoordinator gsb_range = L_device_rr_gsb.get_gsb_range(); + for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { + vtr::Point gsb_coordinate(ix, iy); + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + /* Connect the grid pins of the GSB to adjacent grids */ + add_top_module_nets_connect_grids_and_sb(module_manager, top_module, + device_size, grids, grid_instance_ids, + rr_gsb, sb_instance_ids); + + add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + device_size, grids, grid_instance_ids, + rr_gsb, cbx_instance_ids, cby_instance_ids); + + add_top_module_nets_connect_sb_and_cb(module_manager, top_module, + rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids); + } + } } /******************************************************************** @@ -235,33 +536,36 @@ void print_verilog_top_module(ModuleManager& module_manager, /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ /* Add all the grids across the fabric */ - add_top_module_grid_instances(module_manager, top_module, device_size, grids); + std::vector> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, device_size, grids); /* Add all the SBs across the fabric */ - add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); + std::vector> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); /* Add all the CBX and CBYs across the fabric */ - add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); - add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); + std::vector> cbx_instance_ids = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); + std::vector> cby_instance_ids = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); /* TODO: Add module nets to connect the sub modules */ + add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids); /* TODO: Add inter-CLB direct connections */ - /* TODO: Add global ports to the top-level module */ + /* TODO: Add ports to the top-level module */ /* TODO: Add module nets to connect the top-level ports to sub modules */ - /* TODO: Add global ports to the pb_module: + /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), * we just need to find all the global ports from the child modules and build a list of it */ add_module_global_ports_from_child_modules(module_manager, top_module); - /* TODO: Count GPIO ports from the sub-modules under this Verilog module + /* Add GPIO ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ add_module_gpio_ports_from_child_modules(module_manager, top_module); - /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module + /* Add shared SRAM ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ @@ -276,7 +580,7 @@ void print_verilog_top_module(ModuleManager& module_manager, CircuitModelId sram_model = circuit_lib.model(mem_model->name); VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - /* TODO: Count SRAM ports from the sub-modules under this Verilog module + /* Add SRAM ports from the sub-modules under this Verilog module * This is a much easier job after adding sub modules (instances), * we just need to find all the I/O ports from the child modules and build a list of it */ From 6a131202080873d93cd6398a15cf080b2338f57e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 15 Oct 2019 16:28:46 -0600 Subject: [PATCH 299/482] rename grid modules to be clear --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 7 ++++--- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp | 6 ------ 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 3e1e14c57..0bfba0658 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -679,8 +679,8 @@ std::string generate_grid_block_prefix(const std::string& prefix, if (NUM_SIDES != io_side) { Side side_manager(io_side); - block_prefix += std::string("_"); block_prefix += std::string(side_manager.to_string()); + block_prefix += std::string("_"); } return block_prefix; @@ -697,7 +697,9 @@ std::string generate_grid_block_netlist_name(const std::string& block_name, std::string module_name(block_name); if (true == is_block_io) { - module_name = generate_grid_block_prefix(block_name, io_side); + Side side_manager(io_side); + module_name += std::string("_"); + module_name += std::string(side_manager.to_string()); } module_name += postfix; @@ -719,7 +721,6 @@ std::string generate_grid_block_module_name(const std::string& prefix, return module_name; } - /********************************************************************* * Generate the module name of a physical block * To ensure a unique name for each physical block inside the graph of complex blocks diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index d9091e9f1..841463b94 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -59,8 +59,6 @@ size_t add_top_module_grid_instance(ModuleManager& module_manager, /* Add the module to top_module */ module_manager.add_child_module(top_module, grid_module); - printf("Added grid module %s to top-level module\n", grid_module_name.c_str()); - return grid_instance; } @@ -348,10 +346,6 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(top_module); /* Configure the net source */ - printf("src_grid_module_name: %s[%lu][%lu], src_grid_instance_id: %lu (%lu)\n", - src_grid_module_name.c_str(), - grid_coordinate.x(),grid_coordinate.y(), - src_grid_instance, module_manager.num_instance(top_module, src_grid_module)); module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]); /* Configure the net sink */ module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]); From c9d8311a9340f1c857822d2719c131a80647fd15 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 15 Oct 2019 18:00:55 -0600 Subject: [PATCH 300/482] bug fixing for grid-gsb connections in top module when using compact routing --- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 4 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 4 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 164 ++++++++++++++++-- 3 files changed, 150 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 9413e02fa..9e1867de1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2339,7 +2339,7 @@ DeviceCoordinator DeviceRRGSB::get_gsb_range() const { } /* Get a rr switch block in the array with a coordinator */ -const RRGSB DeviceRRGSB::get_gsb(DeviceCoordinator& coordinator) const { +const RRGSB DeviceRRGSB::get_gsb(const DeviceCoordinator& coordinator) const { assert(validate_coordinator(coordinator)); return rr_gsb_[coordinator.get_x()][coordinator.get_y()]; } @@ -3062,7 +3062,7 @@ void DeviceRRGSB::clear_segment_ids() { /* Validate if the (x,y) is the range of this device */ -bool DeviceRRGSB::validate_coordinator(DeviceCoordinator& coordinator) const { +bool DeviceRRGSB::validate_coordinator(const DeviceCoordinator& coordinator) const { if (coordinator.get_x() >= rr_gsb_.capacity()) { return false; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index 54348046a..f1b519f13 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -328,7 +328,7 @@ class DeviceRRGSB { public: /* Contructors */ public: /* Accessors */ DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */ - const RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ + const RRGSB get_gsb(const DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */ size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */ @@ -370,7 +370,7 @@ class DeviceRRGSB { void clear_gsb_unique_module_id(); /* clean the content */ void clear_segment_ids(); private: /* Validators */ - bool validate_coordinator(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ + bool validate_coordinator(const DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ bool validate_coordinator_edge(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device but takes into consideration the fact that edges are 1 off */ bool validate_side(enum e_side side) const; /* validate if side is in the range of unique_side_module_ */ bool validate_sb_unique_module_index(size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 841463b94..bb3d9aa04 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -304,13 +304,37 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, const vtr::Point& device_size, const std::vector>& grids, const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, const RRGSB& rr_gsb, - const std::vector>& sb_instance_ids) { - vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + const std::vector>& sb_instance_ids, + const bool& compact_routing_hierarchy) { + + /* We could have two different coordinators, one is the instance, the other is the module */ + vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); + module_gsb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_coordinate.set_y(unique_mirror.get_y()); + } + + /* This is the source cb that is added to the top module */ + const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); + vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); + + /* Collect sink-related information */ + std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate); + ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); + size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; + /* Connect grid output pins (OPIN) to switch block grid pins */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { Side side_manager(side); - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { /* Collect source-related information */ /* Generate the grid module name by considering if it locates on the border */ vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); @@ -326,14 +350,10 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); /* Collect sink-related information */ - std::string sink_sb_module_name = generate_switch_block_module_name(sb_coordinate); - ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); - size_t sink_sb_instance = sb_instance_ids[sb_coordinate.x()][sb_coordinate.y()]; - vtr::Point sink_sb_port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); std::string sink_sb_port_name = generate_grid_side_port_name(sink_sb_port_coord, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); @@ -355,7 +375,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, } /******************************************************************** - * TODO: This function will create nets for the connections + * This function will create nets for the connections * between grid input pins and connection blocks * In this case, the net source is the connection block pin, * while the net sink is the grid input @@ -383,6 +403,31 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, * | | * +------------+ * + * + * Relationship between source connection block and its unique module + * Take an example of a CBY + * + * grid_pin name should follow unique module of Grid[x][y+1] + * cb_pin name should follow unique module of CBY[x][y+1] + * + * However, instace id should follow the origin Grid and Connection block + * + * + * +------------+ +------------------+ + * | | | | + * | Grid |<------------| Connection Block | + * | [x][y+1] | | Y-direction | + * | | | [x][y+1] | + * +------------+ +------------------+ + * ^ + * || unique mirror + * +------------+ +------------------+ + * | | | | + * | Grid |<------------| Connection Block | + * | [i][j+1] | | Y-direction | + * | | | [i][j+1] | + * +------------+ +------------------+ + * *******************************************************************/ static void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, @@ -390,9 +435,83 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, const vtr::Point& device_size, const std::vector>& grids, const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, const RRGSB& rr_gsb, - const std::vector>& cbx_instance_ids, - const std::vector>& cby_instance_ids) { + const t_rr_type& cb_type, + const std::vector>& cb_instance_ids, + const bool& compact_routing_hierarchy) { + /* We could have two different coordinators, one is the instance, the other is the module */ + vtr::Point instance_cb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + + /* Skip those Connection blocks that do not exist */ + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + return; + } + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, gsb_coord); + module_gsb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_coordinate.set_y(unique_mirror.get_y()); + } + + /* This is the source cb that is added to the top module */ + const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); + vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); + + /* Collect source-related information */ + std::string src_cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); + ModuleId src_cb_module = module_manager.find_module(src_cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_cb_module)); + /* Instance id should follow the instance cb coordinate */ + size_t src_cb_instance = cb_instance_ids[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; + + /* Iterate over the output pins of the Connection Block */ + std::vector cb_ipin_sides = module_cb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < module_cb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + /* Collect source-related information */ + t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode); + vtr::Point cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow); + std::string src_cb_port_name = generate_grid_side_port_name(cb_src_port_coord, + module_cb.get_ipin_node_grid_side(cb_ipin_side, inode), + module_ipin_node->ptc_num); + ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id)); + BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); + + /* Collect sink-related information */ + /* Note that we use the instance cb pin here, because it has the correct coordinator for the grid!!! */ + t_rr_node* instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + vtr::Point grid_coordinate(instance_ipin_node->xlow, instance_ipin_node->ylow); + std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); + ModuleId sink_grid_module = module_manager.find_module(sink_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; + size_t sink_grid_pin_index = instance_ipin_node->ptc_num; + size_t sink_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, sink_grid_pin_index); + std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_height, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), sink_grid_pin_index, false); + ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id)); + BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(top_module); + /* Configure the net source */ + module_manager.add_module_net_source(top_module, net, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, net, sink_grid_module, sink_grid_instance, sink_grid_port_id, sink_grid_port.pins()[pin_id]); + } + } + } } /******************************************************************** @@ -482,7 +601,8 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, const DeviceRRGSB& L_device_rr_gsb, const std::vector>& sb_instance_ids, const std::vector>& cbx_instance_ids, - const std::vector>& cby_instance_ids) { + const std::vector>& cby_instance_ids, + const bool& compact_routing_hierarchy) { DeviceCoordinator gsb_range = L_device_rr_gsb.get_gsb_range(); for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { @@ -491,11 +611,18 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, /* Connect the grid pins of the GSB to adjacent grids */ add_top_module_nets_connect_grids_and_sb(module_manager, top_module, device_size, grids, grid_instance_ids, - rr_gsb, sb_instance_ids); + L_device_rr_gsb, rr_gsb, sb_instance_ids, + compact_routing_hierarchy); add_top_module_nets_connect_grids_and_cb(module_manager, top_module, device_size, grids, grid_instance_ids, - rr_gsb, cbx_instance_ids, cby_instance_ids); + L_device_rr_gsb, rr_gsb, CHANX, cbx_instance_ids, + compact_routing_hierarchy); + + add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, rr_gsb, CHANY, cby_instance_ids, + compact_routing_hierarchy); add_top_module_nets_connect_sb_and_cb(module_manager, top_module, rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids); @@ -540,7 +667,8 @@ void print_verilog_top_module(ModuleManager& module_manager, /* TODO: Add module nets to connect the sub modules */ add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, device_size, grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids); + L_device_rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids, + compact_routing_hierarchy); /* TODO: Add inter-CLB direct connections */ /* TODO: Add ports to the top-level module */ From 945e138e62015f8af8518272ad3ae29c50407a93 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 15 Oct 2019 22:02:25 -0600 Subject: [PATCH 301/482] debugged the gsb-grid connection in top module. --- .../fpga_x2p/verilog/verilog_top_module.cpp | 218 +++++++++++++++--- 1 file changed, 187 insertions(+), 31 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index bb3d9aa04..ccf6ced3a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -40,6 +40,50 @@ std::string generate_grid_block_module_name_in_top_module(const std::string& pre IO_TYPE == grids[grid_coordinate.x()][grid_coordinate.y()].type, border_side); } +/******************************************************************** + * Find the cb_type of a GSB in the top-level module + * depending on the side of SB + * TOP/BOTTOM side: CHANY + * RIGHT/LEFT side: CHANX + *******************************************************************/ +static +t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { + VTR_ASSERT(NUM_SIDES != sb_side); + + if ((TOP == sb_side) || (BOTTOM == sb_side)) { + return CHANY; + } + + VTR_ASSERT((RIGHT == sb_side) || (LEFT == sb_side)); + return CHANX; +} + +/******************************************************************** + * Find the GSB coordinate for a CB in the top-level module + * depending on the side of a SB + * TODO: use vtr::Point to replace DeviceCoordinator + *******************************************************************/ +static +DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb, + const e_side& sb_side) { + VTR_ASSERT(NUM_SIDES != sb_side); + + DeviceCoordinator gsb_coordinate; + + if ((TOP == sb_side) || (LEFT == sb_side)) { + gsb_coordinate.set_x(rr_gsb.get_x()); + gsb_coordinate.set_y(rr_gsb.get_y()); + return gsb_coordinate; + } + + VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); + DeviceCoordinator side_coord = rr_gsb.get_side_block_coordinator(sb_side); + + gsb_coordinate.set_x(side_coord.get_x()); + gsb_coordinate.set_y(side_coord.get_y()); + + return gsb_coordinate; +} /******************************************************************** * Add a instance of a grid module to the top module @@ -194,10 +238,11 @@ std::vector> add_top_module_switch_block_instances(ModuleMan for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - vtr::Point sb_coordinate(ix, iy); /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_x()); if (true == compact_routing_hierarchy) { - DeviceCoordinator sb_coord(sb_coordinate.x(), sb_coordinate.y()); + DeviceCoordinator sb_coord(ix, iy); const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); sb_coordinate.set_x(unique_mirror.get_sb_x()); sb_coordinate.set_y(unique_mirror.get_sb_y()); @@ -206,7 +251,7 @@ std::vector> add_top_module_switch_block_instances(ModuleMan ModuleId sb_module = module_manager.find_module(sb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); /* Record the instance id */ - sb_instance_ids[ix][iy] = module_manager.num_instance(top_module, sb_module); + sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, sb_module); } @@ -236,12 +281,12 @@ std::vector> add_top_module_connection_block_instances(Modul for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - vtr::Point cb_coordinate(ix, iy); /* Check if the connection block exists in the device! * Some of them do NOT exist due to heterogeneous blocks (height > 1) * We will skip those modules */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); const DeviceCoordinator cb_coordinator = rr_gsb.get_cb_coordinator(cb_type); if ( (TRUE != is_cb_exist(cb_type, cb_coordinator.get_x(), cb_coordinator.get_y())) || (true != rr_gsb.is_cb_exist(cb_type))) { @@ -249,7 +294,7 @@ std::vector> add_top_module_connection_block_instances(Modul } /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ if (true == compact_routing_hierarchy) { - DeviceCoordinator cb_coord(cb_coordinate.x(), cb_coordinate.y()); + DeviceCoordinator cb_coord(ix, iy); const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); @@ -258,7 +303,7 @@ std::vector> add_top_module_connection_block_instances(Modul ModuleId cb_module = module_manager.find_module(cb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); /* Record the instance id */ - cb_instance_ids[ix][iy] = module_manager.num_instance(top_module, cb_module); + cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, cb_module); } @@ -441,7 +486,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, const std::vector>& cb_instance_ids, const bool& compact_routing_hierarchy) { /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_cb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + vtr::Point instance_cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); /* Skip those Connection blocks that do not exist */ @@ -485,7 +530,9 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); /* Collect sink-related information */ - /* Note that we use the instance cb pin here, because it has the correct coordinator for the grid!!! */ + /* Note that we use the instance cb pin here!!! + * because it has the correct coordinator for the grid!!! + */ t_rr_node* instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); vtr::Point grid_coordinate(instance_ipin_node->xlow, instance_ipin_node->ylow); std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); @@ -515,7 +562,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, } /******************************************************************** - * TODO: This function will create nets for the connections + * This function will create nets for the connections * between connection block and switch block pins * Two cases should be considered: * a. The switch block pin denotes an input of a routing track @@ -541,23 +588,133 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, * +------------+ +------------------+ +------------+ * | ^ * v | - * +------------+ +------------------+ - * | | | | - * | Grid | | Connection Block | - * | [x][y] | | Y-direction | - * | | | [x][y] | - * +------------+ +------------------+ - + * +------------+ +------------------+ +------------+ + * | | | | | | + * | Grid | | Connection Block | | Grid | + * | [x][y] | | Y-direction | | [x][y+1] | + * | | | [x][y] | | | + * +------------+ +------------------+ +------------+ + * + * Here, to achieve the purpose, we can simply iterate over the + * four sides of switch block and make connections to adjancent + * connection blocks + * *******************************************************************/ static void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, const RRGSB& rr_gsb, const std::vector>& sb_instance_ids, - const std::vector>& cbx_instance_ids, - const std::vector>& cby_instance_ids) { -} + const std::map>>& cb_instance_ids, + const bool& compact_routing_hierarchy) { + /* We could have two different coordinators, one is the instance, the other is the module */ + vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + DeviceCoordinator module_gsb_sb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); + module_gsb_sb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_sb_coordinate.set_y(unique_mirror.get_y()); + } + + /* This is the source cb that is added to the top module */ + const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_sb_coordinate); + vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); + std::string sb_module_name = generate_switch_block_module_name(module_sb_coordinate); + ModuleId sb_module_id = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module_id)); + size_t sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; + + /* Connect grid output pins (OPIN) to switch block grid pins */ + for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { + Side side_manager(side); + /* Iterate over the routing tracks on this side */ + DeviceCoordinator port_coordinator = module_sb.get_side_block_coordinator(side_manager.get_side()); + /* Early skip: if there is no routing tracks at this side */ + if (0 == module_sb.get_chan_width(side_manager.get_side())) { + continue; + } + /* Find the Connection Block module */ + /* We find the original connection block and then spot its unique mirror! + * Do NOT use module_sb here!!! + */ + t_rr_type cb_type = find_top_module_cb_type_by_sb_side(side_manager.get_side()); + DeviceCoordinator instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); + DeviceCoordinator module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); + + /* Skip those Connection blocks that do not exist */ + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, module_gsb_cb_coordinate); + module_gsb_cb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_cb_coordinate.set_y(unique_mirror.get_y()); + } + + const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); + vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); + std::string cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); + ModuleId cb_module_id = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module_id)); + const RRGSB& instance_cb = L_device_rr_gsb.get_gsb(instance_gsb_cb_coordinate); + vtr::Point instance_cb_coordinate(instance_cb.get_cb_x(cb_type), instance_cb.get_cb_y(cb_type)); + size_t cb_instance = cb_instance_ids.at(cb_type)[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; + + for (size_t itrack = 0; itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) { + vtr::Point sb_port_coord(port_coordinator.get_x(), port_coordinator.get_y()); + std::string sb_port_name = generate_routing_track_port_name(module_sb.get_chan_node(side_manager.get_side(), itrack)->type, + sb_port_coord, itrack, + module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + /* Prepare SB-related port information */ + ModulePortId sb_port_id = module_manager.find_module_port(sb_module_id, sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module_id, sb_port_id)); + BasicPort sb_port = module_manager.module_port(sb_module_id, sb_port_id); + + /* Prepare CB-related port information */ + PORTS cb_port_direction = OUT_PORT; + /* The cb port direction should be opposite to the sb port !!! */ + if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + cb_port_direction = IN_PORT; + } else { + VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + } + vtr::Point cb_port_coord(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); + std::string cb_port_name = generate_routing_track_port_name(cb_type, + cb_port_coord, itrack, + cb_port_direction); + ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id)); + BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(cb_port.get_width() == sb_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(top_module); + /* Configure the net source and sink: + * If sb port is an output (source), cb port is an input (sink) + * If sb port is an input (sink), cb port is an output (source) + */ + if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); + module_manager.add_module_net_source(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); + } else { + VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + module_manager.add_module_net_source(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); + module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); + } + } + } + } +} /******************************************************************** * Add module nets to connect the grid ports/pins to Connection Blocks @@ -600,8 +757,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, const std::vector>& grid_instance_ids, const DeviceRRGSB& L_device_rr_gsb, const std::vector>& sb_instance_ids, - const std::vector>& cbx_instance_ids, - const std::vector>& cby_instance_ids, + const std::map>>& cb_instance_ids, const bool& compact_routing_hierarchy) { DeviceCoordinator gsb_range = L_device_rr_gsb.get_gsb_range(); for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { @@ -616,16 +772,18 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, add_top_module_nets_connect_grids_and_cb(module_manager, top_module, device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, CHANX, cbx_instance_ids, + L_device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), compact_routing_hierarchy); add_top_module_nets_connect_grids_and_cb(module_manager, top_module, device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, CHANY, cby_instance_ids, + L_device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), compact_routing_hierarchy); add_top_module_nets_connect_sb_and_cb(module_manager, top_module, - rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids); + L_device_rr_gsb, rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy); + } } } @@ -654,6 +812,8 @@ void print_verilog_top_module(ModuleManager& module_manager, /* Create a module as the top-level fabric, and add it to the module manager */ std::string top_module_name = generate_fpga_top_module_name(); ModuleId top_module = module_manager.add_module(top_module_name); + + std::map>> cb_instance_ids; /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ /* Add all the grids across the fabric */ @@ -661,20 +821,16 @@ void print_verilog_top_module(ModuleManager& module_manager, /* Add all the SBs across the fabric */ std::vector> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); /* Add all the CBX and CBYs across the fabric */ - std::vector> cbx_instance_ids = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); - std::vector> cby_instance_ids = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); + cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); + cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); /* TODO: Add module nets to connect the sub modules */ add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, device_size, grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cbx_instance_ids, cby_instance_ids, + L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy); /* TODO: Add inter-CLB direct connections */ - /* TODO: Add ports to the top-level module */ - - /* TODO: Add module nets to connect the top-level ports to sub modules */ - /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), * we just need to find all the global ports from the child modules and build a list of it From 190449c06fbef2222945a097f09833dda6759cf9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Oct 2019 17:29:04 -0600 Subject: [PATCH 302/482] refactoring top-level module with clb2clb direct connection --- .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 67 ++++++ .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 6 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 8 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 214 +++++++++++++++++- .../SRC/fpga_x2p/verilog/verilog_top_module.h | 1 + 5 files changed, 294 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index 45844dd75..b1c25acdc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -2138,6 +2138,7 @@ t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb, /******************************************************************** * Find the height of a pin in a grid definition + * TODO: this should be a method of a grid class!!! *******************************************************************/ size_t find_grid_pin_height(const std::vector>& grids, const vtr::Point& grid_coordinate, @@ -2181,6 +2182,72 @@ int get_grid_pin_height(int grid_x, int grid_y, int pin_index) { return pin_height; } +/******************************************************************** + * Find the side where a pin locates on a grid + * TODO: this should be a method of a grid class!!! + *******************************************************************/ +e_side find_grid_pin_side(const vtr::Point& device_size, + const std::vector>& grids, + const vtr::Point& grid_coordinate, + const size_t& pin_height, + const size_t& pin_index) { + t_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type; + + /* Return an invalid side value if this is an empty type */ + if ( (NULL == grid_type) + || (EMPTY_TYPE == grid_type)) { + return NUM_SIDES; + } + + /* Check if the pin index is in the range */ + VTR_ASSERT(pin_index < size_t(grid_type->num_pins)); + + std::vector pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; + /* It could happen that some grids locate on the border of the device, + * In these case, only one side is allowed for the pin + */ + /* TOP side of the device */ + if (grid_coordinate.y() == device_size.y() - 1) { + Side side_manager(TOP); + pin_sides.clear(); + pin_sides.push_back(side_manager.get_opposite()); + } + + /* RIGHT side of the device */ + if (grid_coordinate.x() == device_size.x() - 1) { + Side side_manager(RIGHT); + pin_sides.clear(); + pin_sides.push_back(side_manager.get_opposite()); + } + + /* BOTTOM side of the device */ + if (grid_coordinate.y() == 0) { + Side side_manager(BOTTOM); + pin_sides.clear(); + pin_sides.push_back(side_manager.get_opposite()); + } + + /* LEFT side of the device */ + if (grid_coordinate.x() == 0) { + Side side_manager(LEFT); + pin_sides.clear(); + pin_sides.push_back(side_manager.get_opposite()); + } + + std::vector found_pin_sides; + for (const e_side& pin_side : pin_sides) { + if (1 == grid_type->pinloc[pin_height][pin_side][pin_index]) { + found_pin_sides.push_back(pin_side); + } + } + + /* We should find only one side ! */ + VTR_ASSERT(1 == found_pin_sides.size()); + + return found_pin_sides[0]; +} + + int get_grid_pin_side(int grid_x, int grid_y, int pin_index) { int pin_height, side, pin_side; t_type_ptr grid_type = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 19c1e72f7..c019beb80 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -175,6 +175,12 @@ int get_grid_pin_height(int grid_x, int grid_y, int pin_index); int get_grid_pin_side(int grid_x, int grid_y, int pin_index); +e_side find_grid_pin_side(const vtr::Point& device_size, + const std::vector>& grids, + const vtr::Point& grid_coordinate, + const size_t& pin_height, + const size_t& pin_index); + int* decode_mode_bits(char* mode_bits, int* num_sram_bits); enum e_interconnect determine_actual_pb_interc_type(t_interconnect* def_interc, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a6fea293f..c0c35d1bd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -319,7 +319,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Print top-level Verilog module */ vtr::Point device_size(nx + 2, ny + 2); std::vector> grids; - /* Fill the grid vectors */ + /* Organize a vector (matrix) of grids to feed the top-level module generation */ grids.resize(device_size.x()); for (size_t ix = 0; ix < device_size.x(); ++ix) { grids[ix].resize(device_size.y()); @@ -327,8 +327,14 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, grids[ix][iy] = grid[ix][iy]; } } + /* Organize a vector (matrix) of clb2clb directs to feed the top-level module generation */ + std::vector clb2clb_directs; + for (int i = 0; i < num_clb2clb_directs; ++i) { + clb2clb_directs.push_back(clb2clb_direct[i]); + } print_verilog_top_module(module_manager, Arch.spice->circuit_lib, device_size, grids, device_rr_gsb, + clb2clb_directs, sram_verilog_orgz_info, std::string(vpr_setup.FileNameOpts.ArchFile), std::string(src_dir_path), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index ccf6ced3a..71bda6e8d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -21,6 +21,15 @@ #include "verilog_module_writer.h" #include "verilog_top_module.h" +/******************************************************************** + * Check if the grid coorindate given is in the device grid range + *******************************************************************/ +static +bool is_grid_coordinate_exist_in_device(const vtr::Point& device_size, + const vtr::Point& grid_coordinate) { + return (grid_coordinate < device_size); +} + /******************************************************************** * Generate the name for a grid block, by considering * 1. if it locates on the border with given device size @@ -788,6 +797,205 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, } } +/******************************************************************** + * Add module net for one direction connection between two CLBs or + * two grids + * This function will + * 1. find the pin id and port id of the source clb port in module manager + * 2. find the pin id and port id of the destination clb port in module manager + * 3. add a direct connection module to the top module + * 4. add a first module net and configure its source and sink, + * in order to connect the source pin to the input of the top module + * 4. add a second module net and configure its source and sink, + * in order to connect the sink pin to the output of the top module + *******************************************************************/ +static +void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const vtr::Point& src_clb_coord, + const vtr::Point& des_clb_coord, + const t_clb_to_clb_directs& direct) { + /* Find the source port and destination port on the CLBs */ + BasicPort src_clb_port; + BasicPort des_clb_port; + + src_clb_port.set_width(direct.from_clb_pin_start_index, direct.from_clb_pin_end_index); + des_clb_port.set_width(direct.to_clb_pin_start_index, direct.to_clb_pin_end_index); + + /* Check bandwidth match between from_clb and to_clb pins */ + if (src_clb_port.get_width() != des_clb_port.get_width()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Unmatch pin bandwidth in direct connection (name=%s)!\n", + __FILE__, __LINE__, direct.name); + exit(1); + } + + /* Find the module name of source clb */ + t_type_ptr src_grid_type = grids[src_clb_coord.x()][src_clb_coord.y()].type; + e_side src_grid_border_side = find_grid_border_side(device_size, src_clb_coord); + std::string src_module_name_prefix(grid_verilog_file_name_prefix); + std::string src_module_name = generate_grid_block_module_name(src_module_name_prefix, std::string(src_grid_type->name), IO_TYPE == src_grid_type, src_grid_border_side); + ModuleId src_grid_module = module_manager.find_module(src_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); + /* Record the instance id */ + size_t src_grid_instance = grid_instance_ids[src_clb_coord.x()][src_clb_coord.y()]; + + /* Find the module name of sink clb */ + t_type_ptr sink_grid_type = grids[des_clb_coord.x()][des_clb_coord.y()].type; + e_side sink_grid_border_side = find_grid_border_side(device_size, des_clb_coord); + std::string sink_module_name_prefix(grid_verilog_file_name_prefix); + std::string sink_module_name = generate_grid_block_module_name(sink_module_name_prefix, std::string(sink_grid_type->name), IO_TYPE == sink_grid_type, sink_grid_border_side); + ModuleId sink_grid_module = module_manager.find_module(sink_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + /* Record the instance id */ + size_t sink_grid_instance = grid_instance_ids[des_clb_coord.x()][des_clb_coord.y()]; + + /* Find the module id of a direct connection module */ + std::string direct_module_name = circuit_lib.model_name(direct.circuit_model); + ModuleId direct_module = module_manager.find_module(direct_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(direct_module)); + + /* Find inputs and outputs of the direct circuit module */ + std::vector direct_input_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == direct_input_ports.size()); + ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_input_port_id)); + VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_input_port_id).get_width()); + + std::vector direct_output_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == direct_output_ports.size()); + ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id)); + VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width()); + + for (size_t pin_id : src_clb_port.pins()) { + /* Generate the pin name of source port/pin in the grid */ + size_t src_pin_height = find_grid_pin_height(grids, src_clb_coord, src_clb_port.pins()[pin_id]); + e_side src_pin_grid_side = find_grid_pin_side(device_size, grids, src_clb_coord, src_pin_height, src_clb_port.pins()[pin_id]); + std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_height, src_pin_grid_side, src_clb_port.pins()[pin_id], false); + ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id)); + VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width()); + + /* Generate the pin name of sink port/pin in the grid */ + size_t sink_pin_height = find_grid_pin_height(grids, des_clb_coord, des_clb_port.pins()[pin_id]); + e_side sink_pin_grid_side = find_grid_pin_side(device_size, grids, des_clb_coord, sink_pin_height, des_clb_port.pins()[pin_id]); + std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_height, sink_pin_grid_side, des_clb_port.pins()[pin_id], false); + ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id)); + VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width()); + + /* Add a submodule of direct connection module to the top-level module */ + size_t direct_instance_id = module_manager.num_instance(top_module, direct_module); + module_manager.add_child_module(top_module, direct_module); + + /* Create the 1st module net */ + ModuleNetId net_direct_src = module_manager.create_module_net(top_module); + /* Connect the wire between src_pin of clb and direct_instance input*/ + module_manager.add_module_net_source(top_module, net_direct_src, src_grid_module, src_grid_instance, src_port_id, 0); + module_manager.add_module_net_sink(top_module, net_direct_src, direct_module, direct_instance_id, direct_input_port_id, 0); + + /* Create the 2nd module net */ + ModuleNetId net_direct_sink = module_manager.create_module_net(top_module); + /* Connect the wire between direct_instance output and sink_pin of clb */ + module_manager.add_module_net_source(top_module, net_direct_sink, direct_module, direct_instance_id, direct_output_port_id, 0); + module_manager.add_module_net_sink(top_module, net_direct_sink, sink_grid_module, sink_grid_instance, sink_port_id, 0); + } +} + +/******************************************************************** + * Add module net of clb-to-clb direct connections to module manager + * Note that the direct connections are not limited to CLBs only. + * It can be more generic and thus cover all the grid types, + * such as heterogeneous blocks + * + * This function supports the following types of direct connection: + * 1. Direct connection between grids in the same column or row + * +------+ +------+ + * | | | | + * | Grid |----->| Grid | + * | | | | + * +------+ +------+ + * | direction connection + * v + * +------+ + * | | + * | Grid | + * | | + * +------+ + * + * 2. Direct connections across columns and rows + * +------+ + * | | + * | v + * +------+ | +------+ + * | | | | | + * | Grid | | | Grid | + * | | | | | + * +------+ | +------+ + * | + * +------+ | +------+ + * | | | | | + * | Grid | | | Grid | + * | | | | | + * +------+ | +------+ + * | | + * +------+ + * + *******************************************************************/ +static +void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { + /* Scan the grid, visit each grid and apply direct connections */ + for (size_t ix = 0; ix < device_size.x(); ++ix) { + for (size_t iy = 0; iy < device_size.y(); ++iy) { + /* Bypass EMPTY_TYPE*/ + if ( (NULL == grids[ix][iy].type) + || (EMPTY_TYPE == grids[ix][iy].type)) { + continue; + } + /* Bypass any grid with a non-zero offset! They have been visited in the offset=0 case */ + if (0 != grids[ix][iy].offset) { + continue; + } + /* Check each clb2clb directs by comparing the source and destination clb types + * Direct connections are made only for those matched clbs + */ + for (const t_clb_to_clb_directs& direct : clb2clb_directs) { + /* Bypass unmatched clb type */ + if (grids[ix][iy].type != direct.from_clb_type) { + continue; + } + + /* See if the destination CLB is in the bound */ + vtr::Point src_clb_coord(ix, iy); + vtr::Point des_clb_coord(ix + direct.x_offset, iy + direct.y_offset); + if (false == is_grid_coordinate_exist_in_device(device_size, des_clb_coord)) { + continue; + } + + /* Check if the destination clb_type matches */ + if (grids[des_clb_coord.x()][des_clb_coord.y()].type == direct.to_clb_type) { + /* Add a module net for a direct connection with the two grids in top_model */ + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); + } + } + } + } +} + /******************************************************************** * Print the top-level module for the FPGA fabric in Verilog format * This function will @@ -804,6 +1012,7 @@ void print_verilog_top_module(ModuleManager& module_manager, const vtr::Point& device_size, const std::vector>& grids, const DeviceRRGSB& L_device_rr_gsb, + const std::vector& clb2clb_directs, t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, @@ -824,12 +1033,15 @@ void print_verilog_top_module(ModuleManager& module_manager, cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); - /* TODO: Add module nets to connect the sub modules */ + /* Add module nets to connect the sub modules */ add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, device_size, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy); /* TODO: Add inter-CLB direct connections */ + add_top_module_nets_clb2clb_direct_connections(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + clb2clb_directs); /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h index 33fefa2c4..6516a9780 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h @@ -17,6 +17,7 @@ void print_verilog_top_module(ModuleManager& module_manager, const vtr::Point& device_size, const std::vector>& grids, const DeviceRRGSB& L_device_rr_gsb, + const std::vector& clb2clb_directs, t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, From 4171a674b1ae7c391e5a1ce0e2e4a52e6278bacf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Oct 2019 23:06:59 -0600 Subject: [PATCH 303/482] refactored clb2clb direct connects for cross-column/row --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 57 ++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 4 + .../fpga_x2p/verilog/verilog_top_module.cpp | 281 ++++++++++++++++-- 3 files changed, 316 insertions(+), 26 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 0bfba0658..082e333a0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -835,6 +835,63 @@ e_side find_grid_border_side(const vtr::Point& device_size, return grid_side; } +/******************************************************************** + * This function try to infer if a grid locates at the border of the + * core FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides + * 1. if this grid is on the border and it matches the given side, return true, + * 2. if this grid is in the center, return false + * + * In this function, we assume that the corner grids are actually empty! + * + * +-------+ +----------------------------+ +-------+ + * | EMPTY | | TOP side I/O | | EMPTY | + * +-------+ +----------------------------+ +-------+ + * + * +-------+ +----------------------------+ +-------+ + * | | | TOP | | | + * | | |----------------------------| | | + * | | | | | | | | + * | LEFT | | | | | | RIGHT | + * | side | | LEFT | Core grids | RIGHT| | side | + * | I/O | | | | | | I/O | + * | | | | | | | | + * | | | | | | | | + * | | |---------------------| | | | + * | | | BOTTOM | | | | + * +-------+ +----------------------------+ +-------+ + * + * +-------+ +----------------------------+ +-------+ + * | EMPTY | | BOTTOM side I/O | | EMPTY | + * +-------+ +----------------------------+ +-------+ + * + * Note: for the blocks on the four corners of the core grids + * Please refer to the figure above to infer its border_side + *******************************************************************/ +bool is_core_grid_on_given_border_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate, + const e_side& border_side) { + + if ( (device_size.y() - 2 == grid_coordinate.y()) + && (TOP == border_side) ) { + return true; + } + if ( (device_size.x() - 2 == grid_coordinate.x()) + && (RIGHT == border_side) ) { + return true; + } + if ( (1 == grid_coordinate.y()) + && (BOTTOM == border_side) ) { + return true; + } + if ( (1 == grid_coordinate.x()) + && (LEFT == border_side) ) { + return true; + } + + return false; +} + + /********************************************************************* * Generate the port name of a Verilog module describing a pb_type * The name convention is diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index b40a6e095..00aa66b0d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -151,6 +151,10 @@ std::string generate_grid_physical_block_module_name(const std::string& prefix, e_side find_grid_border_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); +bool is_core_grid_on_given_border_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate, + const e_side& border_side); + std::string generate_pb_type_port_name(t_port* pb_type_port); std::string generate_fpga_global_io_port_name(const std::string& prefix, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 71bda6e8d..5aa5e323a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -4,6 +4,7 @@ *******************************************************************/ #include #include +#include #include "vtr_assert.h" @@ -913,7 +914,7 @@ void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, * It can be more generic and thus cover all the grid types, * such as heterogeneous blocks * - * This function supports the following types of direct connection: + * This function supports the following type of direct connection: * 1. Direct connection between grids in the same column or row * +------+ +------+ * | | | | @@ -928,33 +929,15 @@ void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, * | | * +------+ * - * 2. Direct connections across columns and rows - * +------+ - * | | - * | v - * +------+ | +------+ - * | | | | | - * | Grid | | | Grid | - * | | | | | - * +------+ | +------+ - * | - * +------+ | +------+ - * | | | | | - * | Grid | | | Grid | - * | | | | | - * +------+ | +------+ - * | | - * +------+ - * *******************************************************************/ static -void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { +void add_top_module_nets_intra_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { /* Scan the grid, visit each grid and apply direct connections */ for (size_t ix = 0; ix < device_size.x(); ++ix) { for (size_t iy = 0; iy < device_size.y(); ++iy) { @@ -996,6 +979,252 @@ void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manage } } +/******************************************************************** + * Find the coordinate of a grid in a specific column + * with a given type + * This function will return the coordinate of the grid that satifies + * the type requirement + *******************************************************************/ +static +vtr::Point find_grid_coordinate_given_type(const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& candidate_coords, + t_type_ptr wanted_grid_type) { + for (vtr::Point coord : candidate_coords) { + /* If the next column is not longer in device range, we can return */ + if (false == is_grid_coordinate_exist_in_device(device_size, coord)) { + continue; + } + if (wanted_grid_type == grids[coord.x()][coord.y()].type) { + return coord; + } + } + /* Return an valid coordinate */ + return vtr::Point(size_t(-1), size_t(-1)); +} + +/******************************************************************** + * Find the coordinate of the destination clb/heterogeneous block + * considering intra column/row direct connections in core grids + *******************************************************************/ +static +vtr::Point find_intra_direct_destination_coordinate(const vtr::Point& device_size, + const std::vector>& grids, + const vtr::Point src_coord, + const t_clb_to_clb_directs& direct) { + vtr::Point des_coord(size_t(-1), size_t(-1)); + t_type_ptr src_grid_type = grids[src_coord.x()][src_coord.y()].type; + + std::vector x_search_space; + std::vector y_search_space; + + /* Cross column connection from Bottom to Top on Right + * The next column may NOT have the grid type we want! + * Think about heterogeneous architecture! + * Our search space will start from the next column + * and ends at the RIGHT side of fabric + */ + if (P2P_DIRECT_COLUMN == direct.interconnection_type) { + if (POSITIVE_DIR == direct.x_dir) { + /* By default our search space in x-direction is like + * -----> + */ + for (size_t ix = src_coord.x() + 1; ix < device_size.x() - 1; ++ix) { + x_search_space.push_back(ix); + } + } else { + VTR_ASSERT(NEGATIVE_DIR == direct.x_dir); + /* By default our search space in x-direction is like + * <----- + */ + for (size_t ix = src_coord.x() - 1; ix >= 1; --ix) { + x_search_space.push_back(ix); + } + } + + /* By default our search space in y-direction is like + * y_search_space + * | + * | + * v + */ + for (size_t iy = 1 ; iy < device_size.y() - 1; ++iy) { + y_search_space.push_back(iy); + } + + if (NEGATIVE_DIR == direct.y_dir) { + std::reverse(y_search_space.begin(), y_search_space.end()); + } + } + + + /* Cross row connection from Bottom to Top on Right + * The next column may NOT have the grid type we want! + * Think about heterogeneous architecture! + * Our search space will start from the next column + * and ends at the RIGHT side of fabric + */ + if (P2P_DIRECT_ROW == direct.interconnection_type) { + if (POSITIVE_DIR == direct.x_dir) { + /* By default our search space in y-direction is like + * | + * | + * v + */ + for (size_t iy = src_coord.y() + 1; iy < device_size.y() - 1; ++iy) { + y_search_space.push_back(iy); + } + } else { + VTR_ASSERT(NEGATIVE_DIR == direct.y_dir); + /* By default our search space in y-direction is like + * ^ + * | + * | + */ + for (size_t iy = src_coord.y() - 1; iy >= 1; --iy) { + y_search_space.push_back(iy); + } + } + + /* By default our search space in x-direction is like + * x_search_space ------> + */ + for (size_t ix = 1 ; ix < device_size.x() - 1; ++ix) { + x_search_space.push_back(ix); + } + + if (NEGATIVE_DIR == direct.x_dir) { + std::reverse(x_search_space.begin(), x_search_space.end()); + } + } + + for (size_t ix : x_search_space) { + std::vector> next_col_coords; + for (size_t iy : y_search_space) { + next_col_coords.push_back(vtr::Point(ix, iy)); + } + vtr::Point des_coord_cand = find_grid_coordinate_given_type(device_size, grids, next_col_coords, src_grid_type); + /* For a valid coordinate, we can return */ + if ( (size_t(-1) != des_coord_cand.x()) + && (size_t(-1) != des_coord_cand.y()) ) { + return des_coord_cand; + } + } + return des_coord; +} + +/******************************************************************** + * Add module net of clb-to-clb direct connections to module manager + * Note that the direct connections are not limited to CLBs only. + * It can be more generic and thus cover all the grid types, + * such as heterogeneous blocks + * + * This function supports the following type of direct connection: + * + * 1. Direct connections across columns and rows + * +------+ + * | | + * | v + * +------+ | +------+ + * | | | | | + * | Grid | | | Grid | + * | | | | | + * +------+ | +------+ + * | + * +------+ | +------+ + * | | | | | + * | Grid | | | Grid | + * | | | | | + * +------+ | +------+ + * | | + * +------+ + * + * Note that: this will only apply to the core grids! + * I/Os or any blocks on the border of fabric are NOT supported! + * + *******************************************************************/ +static +void add_top_module_nets_inter_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { + + std::vector border_sides = {TOP, RIGHT, BOTTOM, LEFT}; + + /* Scan the grid, visit each grid and apply direct connections */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + /* Bypass EMPTY_TYPE*/ + if ( (NULL == grids[ix][iy].type) + || (EMPTY_TYPE == grids[ix][iy].type)) { + continue; + } + /* Bypass any grid with a non-zero offset! They have been visited in the offset=0 case */ + if (0 != grids[ix][iy].offset) { + continue; + } + + vtr::Point src_clb_coord(ix, iy); + /* We only care clb/heterogeneous blocks on the border of core logic! */ + for (const e_side& border_side : border_sides) { + if (false == is_core_grid_on_given_border_side(device_size, src_clb_coord, border_side)) { + continue; + } + /* Go through the direct connection list, see if we need intra-column/row connection here */ + for (const t_clb_to_clb_directs& direct: clb2clb_directs) { + if ( (P2P_DIRECT_COLUMN != direct.interconnection_type) + && (P2P_DIRECT_ROW != direct.interconnection_type)) { + continue; + } + /* Bypass unmatched clb type */ + if (grids[src_clb_coord.x()][src_clb_coord.y()].type != direct.from_clb_type) { + continue; + } + /* Reach here it means we may of great possibility to add direct connection */ + /* Find the coordinate of the destination clb */ + vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); + /* If destination clb is valid, we should add something */ + if ( (size_t(-1) == des_clb_coord.x()) + || (size_t(-1) == des_clb_coord.y()) ) { + continue; + } + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); + } + } + } + } +} + +/******************************************************************** + * Add module net of clb-to-clb direct connections to module manager + * Note that the direct connections are not limited to CLBs only. + * It can be more generic and thus cover all the grid types, + * such as heterogeneous blocks + *******************************************************************/ +static +void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { + + add_top_module_nets_intra_clb2clb_direct_connections(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + clb2clb_directs); + + add_top_module_nets_inter_clb2clb_direct_connections(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + clb2clb_directs); +} + /******************************************************************** * Print the top-level module for the FPGA fabric in Verilog format * This function will From cfec8d70ab7214e4089220697e43362a0c7a523f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 11:20:09 -0600 Subject: [PATCH 304/482] improved refactoring on clb2clb connection by considering flexible arch --- .../fpga_x2p/verilog/verilog_top_module.cpp | 261 ++++++++++++------ 1 file changed, 184 insertions(+), 77 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 5aa5e323a..29a9f5122 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -1015,8 +1015,8 @@ vtr::Point find_intra_direct_destination_coordinate(const vtr::Point des_coord(size_t(-1), size_t(-1)); t_type_ptr src_grid_type = grids[src_coord.x()][src_coord.y()].type; - std::vector x_search_space; - std::vector y_search_space; + std::vector first_search_space; + std::vector second_search_space; /* Cross column connection from Bottom to Top on Right * The next column may NOT have the grid type we want! @@ -1026,34 +1026,60 @@ vtr::Point find_intra_direct_destination_coordinate(const vtr::Point + /* Our first search space will be in x-direction: + * + * x ... nx + * +-----+ + * |Grid | -----> + * +-----+ */ for (size_t ix = src_coord.x() + 1; ix < device_size.x() - 1; ++ix) { - x_search_space.push_back(ix); + first_search_space.push_back(ix); } } else { VTR_ASSERT(NEGATIVE_DIR == direct.x_dir); - /* By default our search space in x-direction is like - * <----- + /* Our first search space will be in x-direction: + * + * 1 ... x + * +-----+ + * < -------|Grid | + * +-----+ */ for (size_t ix = src_coord.x() - 1; ix >= 1; --ix) { - x_search_space.push_back(ix); + first_search_space.push_back(ix); } } - /* By default our search space in y-direction is like - * y_search_space - * | - * | - * v + /* Our second search space will be in y-direction: + * + * +------+ + * | Grid | ny + * +------+ + * | . + * | . + * v . + * +------+ + * | Grid | 1 + * +------+ */ for (size_t iy = 1 ; iy < device_size.y() - 1; ++iy) { - y_search_space.push_back(iy); + second_search_space.push_back(iy); } + /* For negative direction, our second search space will be in y-direction: + * + * +------+ + * | Grid | ny + * +------+ + * ^ . + * | . + * | . + * +------+ + * | Grid | 1 + * +------+ + */ if (NEGATIVE_DIR == direct.y_dir) { - std::reverse(y_search_space.begin(), y_search_space.end()); + std::reverse(second_search_space.begin(), second_search_space.end()); } } @@ -1065,45 +1091,78 @@ vtr::Point find_intra_direct_destination_coordinate(const vtr::Point= 1; --iy) { - y_search_space.push_back(iy); + first_search_space.push_back(iy); } } - /* By default our search space in x-direction is like - * x_search_space ------> + /* Our second search space will be in x-direction: + * + * 1 ... nx + * +------+ +------+ + * | Grid |------>| Grid | + * +------+ +------+ */ for (size_t ix = 1 ; ix < device_size.x() - 1; ++ix) { - x_search_space.push_back(ix); + second_search_space.push_back(ix); } + /* For negative direction, + * our second search space will be in x-direction: + * + * 1 ... nx + * +------+ +------+ + * | Grid |<------| Grid | + * +------+ +------+ + */ if (NEGATIVE_DIR == direct.x_dir) { - std::reverse(x_search_space.begin(), x_search_space.end()); + std::reverse(second_search_space.begin(), second_search_space.end()); } } - for (size_t ix : x_search_space) { - std::vector> next_col_coords; - for (size_t iy : y_search_space) { - next_col_coords.push_back(vtr::Point(ix, iy)); + for (size_t ix : first_search_space) { + std::vector> next_col_row_coords; + for (size_t iy : second_search_space) { + if (P2P_DIRECT_COLUMN == direct.interconnection_type) { + next_col_row_coords.push_back(vtr::Point(ix, iy)); + } else { + VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); + /* For cross-row connection, our search space is flipped */ + next_col_row_coords.push_back(vtr::Point(iy, ix)); + } } - vtr::Point des_coord_cand = find_grid_coordinate_given_type(device_size, grids, next_col_coords, src_grid_type); + vtr::Point des_coord_cand = find_grid_coordinate_given_type(device_size, grids, next_col_row_coords, src_grid_type); /* For a valid coordinate, we can return */ if ( (size_t(-1) != des_coord_cand.x()) && (size_t(-1) != des_coord_cand.y()) ) { @@ -1154,49 +1213,97 @@ void add_top_module_nets_inter_clb2clb_direct_connections(ModuleManager& module_ std::vector border_sides = {TOP, RIGHT, BOTTOM, LEFT}; - /* Scan the grid, visit each grid and apply direct connections */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - /* Bypass EMPTY_TYPE*/ - if ( (NULL == grids[ix][iy].type) - || (EMPTY_TYPE == grids[ix][iy].type)) { - continue; - } - /* Bypass any grid with a non-zero offset! They have been visited in the offset=0 case */ - if (0 != grids[ix][iy].offset) { - continue; - } - - vtr::Point src_clb_coord(ix, iy); - /* We only care clb/heterogeneous blocks on the border of core logic! */ - for (const e_side& border_side : border_sides) { - if (false == is_core_grid_on_given_border_side(device_size, src_clb_coord, border_side)) { + /* Go through the direct connection list, see if we need intra-column/row connection here */ + for (const t_clb_to_clb_directs& direct: clb2clb_directs) { + if ( (P2P_DIRECT_COLUMN != direct.interconnection_type) + && (P2P_DIRECT_ROW != direct.interconnection_type)) { + continue; + } + /* For cross-column connection, we will search the first valid grid in each column + * from y = 1 to y = ny + * + * +------+ + * | Grid | y=ny + * +------+ + * ^ + * | search direction (when y_dir is negative) + * ... + * | + * +------+ + * | Grid | y=1 + * +------+ + * + */ + if (P2P_DIRECT_COLUMN == direct.interconnection_type) { + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + std::vector> next_col_src_grid_coords; + /* For negative y- direction, we should start from y = ny */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); + } + /* For positive y- direction, we should start from y = 1 */ + if (POSITIVE_DIR == direct.y_dir) { + std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); + } + vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); + /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ + if ( (size_t(-1) == src_clb_coord.x()) + || (size_t(-1) == src_clb_coord.y()) ) { continue; } - /* Go through the direct connection list, see if we need intra-column/row connection here */ - for (const t_clb_to_clb_directs& direct: clb2clb_directs) { - if ( (P2P_DIRECT_COLUMN != direct.interconnection_type) - && (P2P_DIRECT_ROW != direct.interconnection_type)) { - continue; - } - /* Bypass unmatched clb type */ - if (grids[src_clb_coord.x()][src_clb_coord.y()].type != direct.from_clb_type) { - continue; - } - /* Reach here it means we may of great possibility to add direct connection */ - /* Find the coordinate of the destination clb */ - vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); - /* If destination clb is valid, we should add something */ - if ( (size_t(-1) == des_clb_coord.x()) - || (size_t(-1) == des_clb_coord.y()) ) { - continue; - } - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } + /* For a valid coordinate, we can find the coordinate of the destination clb */ + vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); + /* If destination clb is valid, we should add something */ + if ( (size_t(-1) == des_clb_coord.x()) + || (size_t(-1) == des_clb_coord.y()) ) { + continue; + } + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); } + continue; /* Go to next direct type */ + } + + /* Reach here, it must be a cross-row connection */ + VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); + /* For cross-row connection, we will search the first valid grid in each column + * from x = 1 to x = nx + * + * x=1 x=nx + * +------+ +------+ + * | Grid | <--- ... ---- | Grid | + * +------+ +------+ + * + */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + std::vector> next_col_src_grid_coords; + /* For negative x- direction, we should start from x = nx */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); + } + /* For positive x- direction, we should start from x = 1 */ + if (POSITIVE_DIR == direct.x_dir) { + std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); + } + vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); + /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ + if ( (size_t(-1) == src_clb_coord.x()) + || (size_t(-1) == src_clb_coord.y()) ) { + continue; + } + /* For a valid coordinate, we can find the coordinate of the destination clb */ + vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); + /* If destination clb is valid, we should add something */ + if ( (size_t(-1) == des_clb_coord.x()) + || (size_t(-1) == des_clb_coord.y()) ) { + continue; + } + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); } } } @@ -1267,7 +1374,7 @@ void print_verilog_top_module(ModuleManager& module_manager, device_size, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy); - /* TODO: Add inter-CLB direct connections */ + /* Add inter-CLB direct connections */ add_top_module_nets_clb2clb_direct_connections(module_manager, top_module, circuit_lib, device_size, grids, grid_instance_ids, clb2clb_directs); From 8c1158fc5ca33676439c8e2a0cfe000467bb8568 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 15:33:25 -0600 Subject: [PATCH 305/482] refactor memory organization at the top-level module --- .../base/build_top_module_directs.cpp | 563 ++++++++++++++++++ .../fpga_x2p/base/build_top_module_directs.h | 18 + .../fpga_x2p/base/build_top_module_memory.cpp | 425 +++++++++++++ .../fpga_x2p/base/build_top_module_memory.h | 32 + .../fpga_x2p/base/module_manager_utils.cpp | 208 +++---- .../SRC/fpga_x2p/base/module_manager_utils.h | 6 + vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 4 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 4 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 562 +---------------- 9 files changed, 1171 insertions(+), 651 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.cpp new file mode 100644 index 000000000..536ab15c8 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.cpp @@ -0,0 +1,563 @@ +/******************************************************************** + * This file includes functions that are used to add module nets + * for direct connections between CLBs/heterogeneous blocks + * in the top-level module of a FPGA fabric + *******************************************************************/ +#include + +#include "vtr_assert.h" +#include "util.h" +#include "device_port.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_pbtypes_utils.h" +#include "module_manager_utils.h" + +#include "globals.h" +#include "verilog_global.h" + +#include "build_top_module_directs.h" + +/******************************************************************** + * Check if the grid coorindate given is in the device grid range + *******************************************************************/ +static +bool is_grid_coordinate_exist_in_device(const vtr::Point& device_size, + const vtr::Point& grid_coordinate) { + return (grid_coordinate < device_size); +} + +/******************************************************************** + * Add module net for one direction connection between two CLBs or + * two grids + * This function will + * 1. find the pin id and port id of the source clb port in module manager + * 2. find the pin id and port id of the destination clb port in module manager + * 3. add a direct connection module to the top module + * 4. add a first module net and configure its source and sink, + * in order to connect the source pin to the input of the top module + * 4. add a second module net and configure its source and sink, + * in order to connect the sink pin to the output of the top module + *******************************************************************/ +static +void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const vtr::Point& src_clb_coord, + const vtr::Point& des_clb_coord, + const t_clb_to_clb_directs& direct) { + /* Find the source port and destination port on the CLBs */ + BasicPort src_clb_port; + BasicPort des_clb_port; + + src_clb_port.set_width(direct.from_clb_pin_start_index, direct.from_clb_pin_end_index); + des_clb_port.set_width(direct.to_clb_pin_start_index, direct.to_clb_pin_end_index); + + /* Check bandwidth match between from_clb and to_clb pins */ + if (src_clb_port.get_width() != des_clb_port.get_width()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Unmatch pin bandwidth in direct connection (name=%s)!\n", + __FILE__, __LINE__, direct.name); + exit(1); + } + + /* Find the module name of source clb */ + t_type_ptr src_grid_type = grids[src_clb_coord.x()][src_clb_coord.y()].type; + e_side src_grid_border_side = find_grid_border_side(device_size, src_clb_coord); + std::string src_module_name_prefix(grid_verilog_file_name_prefix); + std::string src_module_name = generate_grid_block_module_name(src_module_name_prefix, std::string(src_grid_type->name), IO_TYPE == src_grid_type, src_grid_border_side); + ModuleId src_grid_module = module_manager.find_module(src_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); + /* Record the instance id */ + size_t src_grid_instance = grid_instance_ids[src_clb_coord.x()][src_clb_coord.y()]; + + /* Find the module name of sink clb */ + t_type_ptr sink_grid_type = grids[des_clb_coord.x()][des_clb_coord.y()].type; + e_side sink_grid_border_side = find_grid_border_side(device_size, des_clb_coord); + std::string sink_module_name_prefix(grid_verilog_file_name_prefix); + std::string sink_module_name = generate_grid_block_module_name(sink_module_name_prefix, std::string(sink_grid_type->name), IO_TYPE == sink_grid_type, sink_grid_border_side); + ModuleId sink_grid_module = module_manager.find_module(sink_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + /* Record the instance id */ + size_t sink_grid_instance = grid_instance_ids[des_clb_coord.x()][des_clb_coord.y()]; + + /* Find the module id of a direct connection module */ + std::string direct_module_name = circuit_lib.model_name(direct.circuit_model); + ModuleId direct_module = module_manager.find_module(direct_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(direct_module)); + + /* Find inputs and outputs of the direct circuit module */ + std::vector direct_input_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == direct_input_ports.size()); + ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_input_port_id)); + VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_input_port_id).get_width()); + + std::vector direct_output_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == direct_output_ports.size()); + ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id)); + VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width()); + + for (size_t pin_id : src_clb_port.pins()) { + /* Generate the pin name of source port/pin in the grid */ + size_t src_pin_height = find_grid_pin_height(grids, src_clb_coord, src_clb_port.pins()[pin_id]); + e_side src_pin_grid_side = find_grid_pin_side(device_size, grids, src_clb_coord, src_pin_height, src_clb_port.pins()[pin_id]); + std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_height, src_pin_grid_side, src_clb_port.pins()[pin_id], false); + ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id)); + VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width()); + + /* Generate the pin name of sink port/pin in the grid */ + size_t sink_pin_height = find_grid_pin_height(grids, des_clb_coord, des_clb_port.pins()[pin_id]); + e_side sink_pin_grid_side = find_grid_pin_side(device_size, grids, des_clb_coord, sink_pin_height, des_clb_port.pins()[pin_id]); + std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_height, sink_pin_grid_side, des_clb_port.pins()[pin_id], false); + ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id)); + VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width()); + + /* Add a submodule of direct connection module to the top-level module */ + size_t direct_instance_id = module_manager.num_instance(top_module, direct_module); + module_manager.add_child_module(top_module, direct_module); + + /* Create the 1st module net */ + ModuleNetId net_direct_src = module_manager.create_module_net(top_module); + /* Connect the wire between src_pin of clb and direct_instance input*/ + module_manager.add_module_net_source(top_module, net_direct_src, src_grid_module, src_grid_instance, src_port_id, 0); + module_manager.add_module_net_sink(top_module, net_direct_src, direct_module, direct_instance_id, direct_input_port_id, 0); + + /* Create the 2nd module net */ + ModuleNetId net_direct_sink = module_manager.create_module_net(top_module); + /* Connect the wire between direct_instance output and sink_pin of clb */ + module_manager.add_module_net_source(top_module, net_direct_sink, direct_module, direct_instance_id, direct_output_port_id, 0); + module_manager.add_module_net_sink(top_module, net_direct_sink, sink_grid_module, sink_grid_instance, sink_port_id, 0); + } +} + + +/******************************************************************** + * Add module net of clb-to-clb direct connections to module manager + * Note that the direct connections are not limited to CLBs only. + * It can be more generic and thus cover all the grid types, + * such as heterogeneous blocks + * + * This function supports the following type of direct connection: + * 1. Direct connection between grids in the same column or row + * +------+ +------+ + * | | | | + * | Grid |----->| Grid | + * | | | | + * +------+ +------+ + * | direction connection + * v + * +------+ + * | | + * | Grid | + * | | + * +------+ + * + *******************************************************************/ +static +void add_top_module_nets_intra_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { + /* Scan the grid, visit each grid and apply direct connections */ + for (size_t ix = 0; ix < device_size.x(); ++ix) { + for (size_t iy = 0; iy < device_size.y(); ++iy) { + /* Bypass EMPTY_TYPE*/ + if ( (NULL == grids[ix][iy].type) + || (EMPTY_TYPE == grids[ix][iy].type)) { + continue; + } + /* Bypass any grid with a non-zero offset! They have been visited in the offset=0 case */ + if (0 != grids[ix][iy].offset) { + continue; + } + /* Check each clb2clb directs by comparing the source and destination clb types + * Direct connections are made only for those matched clbs + */ + for (const t_clb_to_clb_directs& direct : clb2clb_directs) { + /* Bypass unmatched clb type */ + if (grids[ix][iy].type != direct.from_clb_type) { + continue; + } + + /* See if the destination CLB is in the bound */ + vtr::Point src_clb_coord(ix, iy); + vtr::Point des_clb_coord(ix + direct.x_offset, iy + direct.y_offset); + if (false == is_grid_coordinate_exist_in_device(device_size, des_clb_coord)) { + continue; + } + + /* Check if the destination clb_type matches */ + if (grids[des_clb_coord.x()][des_clb_coord.y()].type == direct.to_clb_type) { + /* Add a module net for a direct connection with the two grids in top_model */ + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); + } + } + } + } +} + +/******************************************************************** + * Find the coordinate of a grid in a specific column + * with a given type + * This function will return the coordinate of the grid that satifies + * the type requirement + *******************************************************************/ +static +vtr::Point find_grid_coordinate_given_type(const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& candidate_coords, + t_type_ptr wanted_grid_type) { + for (vtr::Point coord : candidate_coords) { + /* If the next column is not longer in device range, we can return */ + if (false == is_grid_coordinate_exist_in_device(device_size, coord)) { + continue; + } + if (wanted_grid_type == grids[coord.x()][coord.y()].type) { + return coord; + } + } + /* Return an valid coordinate */ + return vtr::Point(size_t(-1), size_t(-1)); +} + +/******************************************************************** + * Find the coordinate of the destination clb/heterogeneous block + * considering intra column/row direct connections in core grids + *******************************************************************/ +static +vtr::Point find_intra_direct_destination_coordinate(const vtr::Point& device_size, + const std::vector>& grids, + const vtr::Point src_coord, + const t_clb_to_clb_directs& direct) { + vtr::Point des_coord(size_t(-1), size_t(-1)); + t_type_ptr src_grid_type = grids[src_coord.x()][src_coord.y()].type; + + std::vector first_search_space; + std::vector second_search_space; + + /* Cross column connection from Bottom to Top on Right + * The next column may NOT have the grid type we want! + * Think about heterogeneous architecture! + * Our search space will start from the next column + * and ends at the RIGHT side of fabric + */ + if (P2P_DIRECT_COLUMN == direct.interconnection_type) { + if (POSITIVE_DIR == direct.x_dir) { + /* Our first search space will be in x-direction: + * + * x ... nx + * +-----+ + * |Grid | -----> + * +-----+ + */ + for (size_t ix = src_coord.x() + 1; ix < device_size.x() - 1; ++ix) { + first_search_space.push_back(ix); + } + } else { + VTR_ASSERT(NEGATIVE_DIR == direct.x_dir); + /* Our first search space will be in x-direction: + * + * 1 ... x + * +-----+ + * < -------|Grid | + * +-----+ + */ + for (size_t ix = src_coord.x() - 1; ix >= 1; --ix) { + first_search_space.push_back(ix); + } + } + + /* Our second search space will be in y-direction: + * + * +------+ + * | Grid | ny + * +------+ + * | . + * | . + * v . + * +------+ + * | Grid | 1 + * +------+ + */ + for (size_t iy = 1 ; iy < device_size.y() - 1; ++iy) { + second_search_space.push_back(iy); + } + + /* For negative direction, our second search space will be in y-direction: + * + * +------+ + * | Grid | ny + * +------+ + * ^ . + * | . + * | . + * +------+ + * | Grid | 1 + * +------+ + */ + if (NEGATIVE_DIR == direct.y_dir) { + std::reverse(second_search_space.begin(), second_search_space.end()); + } + } + + + /* Cross row connection from Bottom to Top on Right + * The next column may NOT have the grid type we want! + * Think about heterogeneous architecture! + * Our search space will start from the next column + * and ends at the RIGHT side of fabric + */ + if (P2P_DIRECT_ROW == direct.interconnection_type) { + if (POSITIVE_DIR == direct.y_dir) { + /* Our first search space will be in y-direction: + * + * +------+ + * | Grid | ny + * +------+ + * ^ . + * | . + * | . + * +------+ + * | Grid | y + * +------+ + */ + for (size_t iy = src_coord.y() + 1; iy < device_size.y() - 1; ++iy) { + first_search_space.push_back(iy); + } + } else { + VTR_ASSERT(NEGATIVE_DIR == direct.y_dir); + /* For negative y-direction, + * Our first search space will be in y-direction: + * + * +------+ + * | Grid | ny + * +------+ + * | . + * | . + * v . + * +------+ + * | Grid | y + * +------+ + */ + for (size_t iy = src_coord.y() - 1; iy >= 1; --iy) { + first_search_space.push_back(iy); + } + } + + /* Our second search space will be in x-direction: + * + * 1 ... nx + * +------+ +------+ + * | Grid |------>| Grid | + * +------+ +------+ + */ + for (size_t ix = 1 ; ix < device_size.x() - 1; ++ix) { + second_search_space.push_back(ix); + } + + /* For negative direction, + * our second search space will be in x-direction: + * + * 1 ... nx + * +------+ +------+ + * | Grid |<------| Grid | + * +------+ +------+ + */ + if (NEGATIVE_DIR == direct.x_dir) { + std::reverse(second_search_space.begin(), second_search_space.end()); + } + } + + for (size_t ix : first_search_space) { + std::vector> next_col_row_coords; + for (size_t iy : second_search_space) { + if (P2P_DIRECT_COLUMN == direct.interconnection_type) { + next_col_row_coords.push_back(vtr::Point(ix, iy)); + } else { + VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); + /* For cross-row connection, our search space is flipped */ + next_col_row_coords.push_back(vtr::Point(iy, ix)); + } + } + vtr::Point des_coord_cand = find_grid_coordinate_given_type(device_size, grids, next_col_row_coords, src_grid_type); + /* For a valid coordinate, we can return */ + if ( (size_t(-1) != des_coord_cand.x()) + && (size_t(-1) != des_coord_cand.y()) ) { + return des_coord_cand; + } + } + return des_coord; +} + +/******************************************************************** + * Add module net of clb-to-clb direct connections to module manager + * Note that the direct connections are not limited to CLBs only. + * It can be more generic and thus cover all the grid types, + * such as heterogeneous blocks + * + * This function supports the following type of direct connection: + * + * 1. Direct connections across columns and rows + * +------+ + * | | + * | v + * +------+ | +------+ + * | | | | | + * | Grid | | | Grid | + * | | | | | + * +------+ | +------+ + * | + * +------+ | +------+ + * | | | | | + * | Grid | | | Grid | + * | | | | | + * +------+ | +------+ + * | | + * +------+ + * + * Note that: this will only apply to the core grids! + * I/Os or any blocks on the border of fabric are NOT supported! + * + *******************************************************************/ +static +void add_top_module_nets_inter_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { + + std::vector border_sides = {TOP, RIGHT, BOTTOM, LEFT}; + + /* Go through the direct connection list, see if we need intra-column/row connection here */ + for (const t_clb_to_clb_directs& direct: clb2clb_directs) { + if ( (P2P_DIRECT_COLUMN != direct.interconnection_type) + && (P2P_DIRECT_ROW != direct.interconnection_type)) { + continue; + } + /* For cross-column connection, we will search the first valid grid in each column + * from y = 1 to y = ny + * + * +------+ + * | Grid | y=ny + * +------+ + * ^ + * | search direction (when y_dir is negative) + * ... + * | + * +------+ + * | Grid | y=1 + * +------+ + * + */ + if (P2P_DIRECT_COLUMN == direct.interconnection_type) { + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + std::vector> next_col_src_grid_coords; + /* For negative y- direction, we should start from y = ny */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); + } + /* For positive y- direction, we should start from y = 1 */ + if (POSITIVE_DIR == direct.y_dir) { + std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); + } + vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); + /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ + if ( (size_t(-1) == src_clb_coord.x()) + || (size_t(-1) == src_clb_coord.y()) ) { + continue; + } + /* For a valid coordinate, we can find the coordinate of the destination clb */ + vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); + /* If destination clb is valid, we should add something */ + if ( (size_t(-1) == des_clb_coord.x()) + || (size_t(-1) == des_clb_coord.y()) ) { + continue; + } + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); + } + continue; /* Go to next direct type */ + } + + /* Reach here, it must be a cross-row connection */ + VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); + /* For cross-row connection, we will search the first valid grid in each column + * from x = 1 to x = nx + * + * x=1 x=nx + * +------+ +------+ + * | Grid | <--- ... ---- | Grid | + * +------+ +------+ + * + */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + std::vector> next_col_src_grid_coords; + /* For negative x- direction, we should start from x = nx */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); + } + /* For positive x- direction, we should start from x = 1 */ + if (POSITIVE_DIR == direct.x_dir) { + std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); + } + vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); + /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ + if ( (size_t(-1) == src_clb_coord.x()) + || (size_t(-1) == src_clb_coord.y()) ) { + continue; + } + /* For a valid coordinate, we can find the coordinate of the destination clb */ + vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); + /* If destination clb is valid, we should add something */ + if ( (size_t(-1) == des_clb_coord.x()) + || (size_t(-1) == des_clb_coord.y()) ) { + continue; + } + add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + src_clb_coord, des_clb_coord, + direct); + } + } +} + +/******************************************************************** + * Add module net of clb-to-clb direct connections to module manager + * Note that the direct connections are not limited to CLBs only. + * It can be more generic and thus cover all the grid types, + * such as heterogeneous blocks + *******************************************************************/ +void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs) { + + add_top_module_nets_intra_clb2clb_direct_connections(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + clb2clb_directs); + + add_top_module_nets_inter_clb2clb_direct_connections(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + clb2clb_directs); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.h new file mode 100644 index 000000000..4c6f759ee --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.h @@ -0,0 +1,18 @@ +#ifndef BUILD_TOP_MODULE_DIRECTS_H +#define BUILD_TOP_MODULE_DIRECTS_H + +#include +#include "vtr_geometry.h" +#include "vpr_types.h" +#include "module_manager.h" +#include "circuit_library.h" + +void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const std::vector& clb2clb_directs); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.cpp new file mode 100644 index 000000000..8331edad5 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.cpp @@ -0,0 +1,425 @@ +/******************************************************************** + * This file includes functions that are used to organize memories + * in the top module of FPGA fabric + *******************************************************************/ +#include "vtr_assert.h" + +#include "fpga_x2p_utils.h" +#include "fpga_x2p_naming.h" + +#include "globals.h" +#include "verilog_global.h" + +#include "module_manager_utils.h" +#include "build_top_module_memory.h" + +/******************************************************************** + * This function adds the CBX/CBY of a tile + * to the memory modules and memory instances + * This function is designed for organizing memory modules in top-level + * module + *******************************************************************/ +static +void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + t_sram_orgz_info* cur_sram_orgz_info, + const std::vector>& cb_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const bool& compact_routing_hierarchy, + std::vector& memory_modules, + std::vector& memory_instances) { + /* If the CB does not exist, we can skip addition */ + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + return; + } + + vtr::Point cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + if (true == compact_routing_hierarchy) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, DeviceCoordinator(cb_coord.x(), cb_coord.y())); + cb_coord.set_x(unique_mirror.get_cb_x(cb_type)); + cb_coord.set_y(unique_mirror.get_cb_y(cb_type)); + } + + std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coord); + ModuleId cb_module = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + + /* Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, cb_module, + circuit_lib, sram_model, + cur_sram_orgz_info->type)) { + memory_modules.push_back(cb_module); + memory_instances.push_back(cb_instance_ids[cb_coord.x()][cb_coord.y()]); + } +} + +/******************************************************************** + * This function adds the SB, CBX, CBY and Grid of a tile + * to the memory modules and memory instances + * This function is designed for organizing memory modules in top-level + * module + *******************************************************************/ +static +void organize_top_module_tile_memory_modules(const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + t_sram_orgz_info* cur_sram_orgz_info, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& sb_instance_ids, + const std::map>>& cb_instance_ids, + const bool& compact_routing_hierarchy, + const vtr::Point& tile_coord, + const e_side& tile_border_side, + std::vector& memory_modules, + std::vector& memory_instances) { + + vtr::Point gsb_coord_range(L_device_rr_gsb.get_gsb_range().get_x(), L_device_rr_gsb.get_gsb_range().get_y()); + + vtr::Point gsb_coord(tile_coord.x(), tile_coord.y() - 1); + + /* We do NOT consider SB and CBs if the gsb is not in the range! */ + if ( (gsb_coord.x() < gsb_coord_range.x()) + && (gsb_coord.y() < gsb_coord_range.y()) ) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(gsb_coord.x(), gsb_coord.y()); + /* Find Switch Block: unique module id and instance id! + * Note that switch block does always exist in a GSB + */ + vtr::Point sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + if (true == compact_routing_hierarchy) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(DeviceCoordinator(sb_coord.x(), sb_coord.y())); + sb_coord.set_x(unique_mirror.get_sb_x()); + sb_coord.set_y(unique_mirror.get_sb_y()); + } + std::string sb_module_name = generate_switch_block_module_name(sb_coord); + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, sb_module, + circuit_lib, sram_model, + cur_sram_orgz_info->type)) { + memory_modules.push_back(sb_module); + memory_instances.push_back(sb_instance_ids[sb_coord.x()][sb_coord.y()]); + } + + /* Try to find and add CBX and CBY */ + organize_top_module_tile_cb_modules(module_manager, circuit_lib, + sram_model, cur_sram_orgz_info, + cb_instance_ids.at(CHANX), + L_device_rr_gsb, rr_gsb, CHANX, + compact_routing_hierarchy, + memory_modules, memory_instances); + + organize_top_module_tile_cb_modules(module_manager, circuit_lib, + sram_model, cur_sram_orgz_info, + cb_instance_ids.at(CHANY), + L_device_rr_gsb, rr_gsb, CHANY, + compact_routing_hierarchy, + memory_modules, memory_instances); + } + + /* Find the module name for this type of grid */ + t_type_ptr grid_type = grids[tile_coord.x()][tile_coord.y()].type; + std::string grid_module_name_prefix(grid_verilog_file_name_prefix); + std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, tile_border_side); + ModuleId grid_module = module_manager.find_module(grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); + + /* Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, grid_module, + circuit_lib, sram_model, + cur_sram_orgz_info->type)) { + memory_modules.push_back(grid_module); + memory_instances.push_back(grid_instance_ids[tile_coord.x()][tile_coord.y()]); + } +} + +/******************************************************************** + * Organize the list of memory modules and instances + * This function will record all the sub modules of the top-level module + * (those have memory ports) to two lists: + * 1. memory_modules records the module ids + * 2. memory_instances records the instance ids + * To keep a clean memory connection between sub modules and top-level module, + * the sequence of memory_modules and memory_instances will follow + * a chain of tiles considering their physical location + * + * Inter tile connection: + * +--------------------------------------------------------+ + * | +------+------+-----+------+ | + * | | I/O | I/O | ... | I/O | | + * | | TOP | TOP | | TOP | | + * | +------+------+-----+------+ | + * | +---------------------------------->tail | + * | +------+ | +------+------+-----+------+ +------+ | + * | | | | | | | | | | | | + * | | I/O | | | Tile | Tile | ... | Tile | | I/O | | + * | | LEFT | | | [h+1]| [h+2]| | [n] | |RIGHT | | + * | +------+ | +------+------+-----+------+ +------+ | + * | +-------------------------------+ | + * | ... ... ... ... ... | ... | + * | +-------------------------------+ | + * | +------+ | +------+------+-----+------+ +------+ | + * | | | | | | | | | | | | + * | | I/O | | | Tile | Tile | ... | Tile | | I/O | | + * | | LEFT | | | [i+1]| [i+2]| | [j] | |RIGHT | | + * | +------+ | +------+------+-----+------+ +------+ | + * | +-------------------------------+ | + * | +------+ +------+------+-----+------+ | +------+ | + * | | | | | | | | | | | | + * | | I/O | | Tile | Tile | ... | Tile | | | I/O | | + * | | LEFT | | [0] | [1] | | [i] | | |RIGHT | | + * | +------+ +------+------+-----+------+ | +------+ | + * +-------------------------------------------+ | + * +------+------+-----+------+ | + * | I/O | I/O | ... | I/O | | + * |BOTTOM|BOTTOM| |BOTTOM| | + * +------+------+-----+------+ | + * head >-----------------------------------------------+ + * + * Inner tile connection + * + * Tile + * +---------------+----------+ + * <-+---------------+ + | + * | | | | + * | CLB | | CBY | + * | +-|-+ | + * | | | | + * +---------------+----------+ + * | +-+----+-----+---<--- + * | CBX | SB | + * | | | + * +---------------+----------+ + * + *******************************************************************/ +void organize_top_module_memory_modules(const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + t_sram_orgz_info* cur_sram_orgz_info, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& sb_instance_ids, + const std::map>>& cb_instance_ids, + const bool& compact_routing_hierarchy, + std::vector& memory_modules, + std::vector& memory_instances) { + /* Ensure clean vectors to return */ + VTR_ASSERT(true == memory_modules.empty()); + VTR_ASSERT(true == memory_instances.empty()); + + /* First, organize the I/O tiles on the border */ + /* Special for the I/O tileas on RIGHT and BOTTOM, + * which are only I/O blocks, which do NOT contain CBs and SBs + */ + std::vector io_sides{BOTTOM, RIGHT, TOP, LEFT}; + std::map>> io_coords; + + /* BOTTOM side I/Os */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coords[BOTTOM].push_back(vtr::Point(ix, 0)); + } + + /* RIGHT side I/Os */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coords[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); + } + + /* TOP side I/Os */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coords[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); + } + + /* LEFT side I/Os */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coords[LEFT].push_back(vtr::Point(0, iy)); + } + + for (const e_side& io_side : io_sides) { + for (const vtr::Point& io_coord : io_coords[io_side]) { + /* Identify the GSB that surrounds the grid */ + organize_top_module_tile_memory_modules(module_manager, + circuit_lib, sram_model, cur_sram_orgz_info, + grids, grid_instance_ids, + L_device_rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy, + io_coord, io_side, + memory_modules, memory_instances); + } + } + + /* For the core grids */ + std::vector> core_coords; + bool positive_direction = true; + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + /* For positive direction: -----> */ + if (true == positive_direction) { + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + core_coords.push_back(vtr::Point(ix, iy)); + } + } else { + VTR_ASSERT(false == positive_direction); + /* For negative direction: -----> */ + for (size_t ix = device_size.x() - 2; ix >= 1; --ix) { + core_coords.push_back(vtr::Point(ix, iy)); + } + } + /* Flip the positive direction to be negative */ + positive_direction = !positive_direction; + } + + for (const vtr::Point& core_coord : core_coords) { + organize_top_module_tile_memory_modules(module_manager, + circuit_lib, sram_model, cur_sram_orgz_info, + grids, grid_instance_ids, + L_device_rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy, + core_coord, NUM_SIDES, + memory_modules, memory_instances); + } +} + + +/********************************************************************* + * Add the port-to-port connection between all the memory modules + * and their parent module + * + * Create nets to wire the control signals of memory module to + * the configuration ports of primitive module + * + * Configuration Chain + * ------------------- + * + * config_bus (head) config_bus (tail) + * | ^ + * primitive | | + * +---------------------------------------------+ + * | | | | + * | v | | + * | +-------------------------------------+ | + * | | CMOS-based Memory Modules | | + * | +-------------------------------------+ | + * | | | | + * | v v | + * | sram_out sram_outb | + * | | + * +---------------------------------------------+ + * + * Memory bank + * ----------- + * + * config_bus (BL) config_bus (WL) + * | | + * primitive | | + * +---------------------------------------------+ + * | | | | + * | v v | + * | +-------------------------------------+ | + * | | CMOS-based Memory Modules | | + * | +-------------------------------------+ | + * | | | | + * | v v | + * | sram_out sram_outb | + * | | + * +---------------------------------------------+ + * + **********************************************************************/ +static +void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type) { + /* Ensure that the size of memory_model vector matches the memory_module vector */ + VTR_ASSERT(memory_modules.size() == memory_instances.size()); + + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* Nothing to do */ + break; + case SPICE_SRAM_SCAN_CHAIN: { + add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, memory_modules, memory_instances, sram_orgz_type); + break; + } + case SPICE_SRAM_MEMORY_BANK: + /* TODO: */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + + +/******************************************************************** + * TODO: + * Add the port-to-port connection between a memory module + * and the configuration bus of a primitive module + * + * Create nets to wire the control signals of memory module to + * the configuration ports of primitive module + * + * Primitive module + * +----------------------------+ + * | +--------+ | + * config | | | | + * ports --->|--------------->| Memory | | + * | | Module | | + * | | | | + * | +--------+ | + * +----------------------------+ + * The detailed config ports really depend on the type + * of SRAM organization. + * + * The config_bus in the argument is the reserved address of configuration + * bus in the parent_module for this memory module + * + * The configuration bus connection will depend not only + * the design technology of the memory cells but also the + * configuration styles of FPGA fabric. + * Here we will branch on the design technology + * + * Note: this function SHOULD be called after the pb_type_module is created + * and its child module (logic_module and memory_module) is created! + *******************************************************************/ +void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_design_tech& mem_tech) { + switch (mem_tech) { + case SPICE_MODEL_DESIGN_CMOS: + add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module, + memory_modules, memory_instances, + sram_orgz_type); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* TODO: */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of memory design technology !\n", + __FILE__, __LINE__); + exit(1); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.h new file mode 100644 index 000000000..66afa2a51 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.h @@ -0,0 +1,32 @@ +#ifndef BUILD_TOP_MODULE_MEMORY_H +#define BUILD_TOP_MODULE_MEMORY_H + +#include +#include +#include "module_manager.h" +#include "spice_types.h" +#include "circuit_library.h" +#include "rr_blocks.h" + +void organize_top_module_memory_modules(const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& sram_model, + t_sram_orgz_info* cur_sram_orgz_info, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& sb_instance_ids, + const std::map>>& cb_instance_ids, + const bool& compact_routing_hierarchy, + std::vector& memory_modules, + std::vector& memory_instances); + +void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type, + const e_spice_model_design_tech& mem_tech); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index a703ee379..f7e6b7c8b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -565,6 +565,113 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man } } +/* Connect all the memory modules under the parent module in a chain + * + * +--------+ +--------+ +--------+ + * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail + * | Module | | Module | | Module | + * | [0] | | [1] | | [N-1] | + * +--------+ +--------+ +--------+ + * For the 1st memory module: + * net source is the configuration chain head of the primitive module + * net sink is the configuration chain head of the next memory module + * + * For the rest of memory modules: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain head of the next memory module + */ +void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type) { + for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) { + ModuleId net_src_module_id; + size_t net_src_instance_id; + ModulePortId net_src_port_id; + + ModuleId net_sink_module_id; + size_t net_sink_instance_id; + ModulePortId net_sink_port_id; + + if (0 == mem_index) { + /* Find the port name of configuration chain head */ + std::string src_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT); + net_src_module_id = parent_module; + net_src_instance_id = 0; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_head_name(); + net_sink_module_id = memory_modules[mem_index]; + net_sink_instance_id = memory_instances[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + } else { + /* Find the port name of previous memory module */ + std::string src_port_name = generate_configuration_chain_tail_name(); + net_src_module_id = memory_modules[mem_index - 1]; + net_src_instance_id = memory_instances[mem_index - 1]; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_head_name(); + net_sink_module_id = memory_modules[mem_index]; + net_sink_instance_id = memory_instances[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + } + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + /* Port sizes of source and sink should match */ + VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { + /* Create a net and add source and sink to it */ + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + } + } + + /* For the last memory module: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain tail of the primitive module + */ + /* Find the port name of previous memory module */ + std::string src_port_name = generate_configuration_chain_tail_name(); + ModuleId net_src_module_id = memory_modules.back(); + size_t net_src_instance_id = memory_instances.back(); + ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT); + ModuleId net_sink_module_id = parent_module; + size_t net_sink_instance_id = 0; + ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + /* Port sizes of source and sink should match */ + VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { + /* Create a net and add source and sink to it */ + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + } +} + /********************************************************************* * Add the port-to-port connection between all the memory modules * and their parent module @@ -623,106 +730,7 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, /* Nothing to do */ break; case SPICE_SRAM_SCAN_CHAIN: { - /* Connect all the memory modules under the parent module in a chain - * - * +--------+ +--------+ +--------+ - * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail - * | Module | | Module | | Module | - * | [0] | | [1] | | [N-1] | - * +--------+ +--------+ +--------+ - * For the 1st memory module: - * net source is the configuration chain head of the primitive module - * net sink is the configuration chain head of the next memory module - * - * For the rest of memory modules: - * net source is the configuration chain tail of the previous memory module - * net sink is the configuration chain head of the next memory module - */ - for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) { - ModuleId net_src_module_id; - size_t net_src_instance_id; - ModulePortId net_src_port_id; - - ModuleId net_sink_module_id; - size_t net_sink_instance_id; - ModulePortId net_sink_port_id; - - if (0 == mem_index) { - /* Find the port name of configuration chain head */ - std::string src_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT); - net_src_module_id = parent_module; - net_src_instance_id = 0; - net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_configuration_chain_head_name(); - net_sink_module_id = memory_modules[mem_index]; - net_sink_instance_id = memory_instances[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - } else { - /* Find the port name of previous memory module */ - std::string src_port_name = generate_configuration_chain_tail_name(); - net_src_module_id = memory_modules[mem_index - 1]; - net_src_instance_id = memory_instances[mem_index - 1]; - net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_configuration_chain_head_name(); - net_sink_module_id = memory_modules[mem_index]; - net_sink_instance_id = memory_instances[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - } - - /* Get the pin id for source port */ - BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); - /* Get the pin id for sink port */ - BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); - /* Port sizes of source and sink should match */ - VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { - /* Create a net and add source and sink to it */ - ModuleNetId net = module_manager.create_module_net(parent_module); - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); - } - } - - /* For the last memory module: - * net source is the configuration chain tail of the previous memory module - * net sink is the configuration chain tail of the primitive module - */ - /* Find the port name of previous memory module */ - std::string src_port_name = generate_configuration_chain_tail_name(); - ModuleId net_src_module_id = memory_modules.back(); - size_t net_src_instance_id = memory_instances.back(); - ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT); - ModuleId net_sink_module_id = parent_module; - size_t net_sink_instance_id = 0; - ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - - /* Get the pin id for source port */ - BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); - /* Get the pin id for sink port */ - BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); - /* Port sizes of source and sink should match */ - VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { - /* Create a net and add source and sink to it */ - ModuleNetId net = module_manager.create_module_net(parent_module); - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); - } + add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, memory_modules, memory_instances, sram_orgz_type); break; } case SPICE_SRAM_MEMORY_BANK: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index b0884192b..d1ab892b4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -69,6 +69,12 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man const CircuitLibrary& circuit_lib, const CircuitModelId& logic_model); +void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const e_sram_orgz& sram_orgz_type); + void add_module_nets_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, const std::vector& memory_modules, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 9e1867de1..bd06d87d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2449,7 +2449,7 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, size_t index) } /* Give a coordinator of a rr switch block, and return its unique mirror */ -const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& coordinator) const { +const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) const { assert (validate_cb_type(cb_type)); assert(validate_coordinator(coordinator)); size_t cb_unique_module_id; @@ -2472,7 +2472,7 @@ const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, DeviceCoordina } /* Give a coordinator of a rr switch block, and return its unique mirror */ -const RRGSB DeviceRRGSB::get_sb_unique_module(DeviceCoordinator& coordinator) const { +const RRGSB DeviceRRGSB::get_sb_unique_module(const DeviceCoordinator& coordinator) const { assert(validate_coordinator(coordinator)); size_t sb_unique_module_id = sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()]; return get_sb_unique_module(sb_unique_module_id); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index f1b519f13..125975da3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -338,9 +338,9 @@ class DeviceRRGSB { const RRGSB get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ const RRGSB get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ const RRGSB get_sb_unique_module(size_t index) const; /* Get a rr switch block which a unique mirror */ - const RRGSB get_sb_unique_module(DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ + const RRGSB get_sb_unique_module(const DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ const RRGSB& get_cb_unique_module(t_rr_type cb_type, size_t index) const; /* Get a rr switch block which a unique mirror */ - const RRGSB& get_cb_unique_module(t_rr_type cb_type, DeviceCoordinator& coordinator) const; + const RRGSB& get_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) const; size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */ size_t get_num_segments() const; /* Get the size of segment_ids */ size_t get_segment_id(size_t index) const; /* Get a segment id */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 29a9f5122..136cef804 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -15,6 +15,8 @@ #include "fpga_x2p_utils.h" #include "fpga_x2p_pbtypes_utils.h" #include "module_manager_utils.h" +#include "build_top_module_memory.h" +#include "build_top_module_directs.h" #include "verilog_global.h" #include "verilog_routing.h" @@ -22,15 +24,6 @@ #include "verilog_module_writer.h" #include "verilog_top_module.h" -/******************************************************************** - * Check if the grid coorindate given is in the device grid range - *******************************************************************/ -static -bool is_grid_coordinate_exist_in_device(const vtr::Point& device_size, - const vtr::Point& grid_coordinate) { - return (grid_coordinate < device_size); -} - /******************************************************************** * Generate the name for a grid block, by considering * 1. if it locates on the border with given device size @@ -236,6 +229,7 @@ std::vector> add_top_module_switch_block_instances(ModuleMan const ModuleId& top_module, const DeviceRRGSB& L_device_rr_gsb, const bool& compact_routing_hierarchy) { + /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); /* Reserve an array for the instance ids */ @@ -798,540 +792,6 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, } } -/******************************************************************** - * Add module net for one direction connection between two CLBs or - * two grids - * This function will - * 1. find the pin id and port id of the source clb port in module manager - * 2. find the pin id and port id of the destination clb port in module manager - * 3. add a direct connection module to the top module - * 4. add a first module net and configure its source and sink, - * in order to connect the source pin to the input of the top module - * 4. add a second module net and configure its source and sink, - * in order to connect the sink pin to the output of the top module - *******************************************************************/ -static -void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const vtr::Point& src_clb_coord, - const vtr::Point& des_clb_coord, - const t_clb_to_clb_directs& direct) { - /* Find the source port and destination port on the CLBs */ - BasicPort src_clb_port; - BasicPort des_clb_port; - - src_clb_port.set_width(direct.from_clb_pin_start_index, direct.from_clb_pin_end_index); - des_clb_port.set_width(direct.to_clb_pin_start_index, direct.to_clb_pin_end_index); - - /* Check bandwidth match between from_clb and to_clb pins */ - if (src_clb_port.get_width() != des_clb_port.get_width()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Unmatch pin bandwidth in direct connection (name=%s)!\n", - __FILE__, __LINE__, direct.name); - exit(1); - } - - /* Find the module name of source clb */ - t_type_ptr src_grid_type = grids[src_clb_coord.x()][src_clb_coord.y()].type; - e_side src_grid_border_side = find_grid_border_side(device_size, src_clb_coord); - std::string src_module_name_prefix(grid_verilog_file_name_prefix); - std::string src_module_name = generate_grid_block_module_name(src_module_name_prefix, std::string(src_grid_type->name), IO_TYPE == src_grid_type, src_grid_border_side); - ModuleId src_grid_module = module_manager.find_module(src_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); - /* Record the instance id */ - size_t src_grid_instance = grid_instance_ids[src_clb_coord.x()][src_clb_coord.y()]; - - /* Find the module name of sink clb */ - t_type_ptr sink_grid_type = grids[des_clb_coord.x()][des_clb_coord.y()].type; - e_side sink_grid_border_side = find_grid_border_side(device_size, des_clb_coord); - std::string sink_module_name_prefix(grid_verilog_file_name_prefix); - std::string sink_module_name = generate_grid_block_module_name(sink_module_name_prefix, std::string(sink_grid_type->name), IO_TYPE == sink_grid_type, sink_grid_border_side); - ModuleId sink_grid_module = module_manager.find_module(sink_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); - /* Record the instance id */ - size_t sink_grid_instance = grid_instance_ids[des_clb_coord.x()][des_clb_coord.y()]; - - /* Find the module id of a direct connection module */ - std::string direct_module_name = circuit_lib.model_name(direct.circuit_model); - ModuleId direct_module = module_manager.find_module(direct_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(direct_module)); - - /* Find inputs and outputs of the direct circuit module */ - std::vector direct_input_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == direct_input_ports.size()); - ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_input_port_id)); - VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_input_port_id).get_width()); - - std::vector direct_output_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == direct_output_ports.size()); - ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id)); - VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width()); - - for (size_t pin_id : src_clb_port.pins()) { - /* Generate the pin name of source port/pin in the grid */ - size_t src_pin_height = find_grid_pin_height(grids, src_clb_coord, src_clb_port.pins()[pin_id]); - e_side src_pin_grid_side = find_grid_pin_side(device_size, grids, src_clb_coord, src_pin_height, src_clb_port.pins()[pin_id]); - std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_height, src_pin_grid_side, src_clb_port.pins()[pin_id], false); - ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id)); - VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width()); - - /* Generate the pin name of sink port/pin in the grid */ - size_t sink_pin_height = find_grid_pin_height(grids, des_clb_coord, des_clb_port.pins()[pin_id]); - e_side sink_pin_grid_side = find_grid_pin_side(device_size, grids, des_clb_coord, sink_pin_height, des_clb_port.pins()[pin_id]); - std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_height, sink_pin_grid_side, des_clb_port.pins()[pin_id], false); - ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id)); - VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width()); - - /* Add a submodule of direct connection module to the top-level module */ - size_t direct_instance_id = module_manager.num_instance(top_module, direct_module); - module_manager.add_child_module(top_module, direct_module); - - /* Create the 1st module net */ - ModuleNetId net_direct_src = module_manager.create_module_net(top_module); - /* Connect the wire between src_pin of clb and direct_instance input*/ - module_manager.add_module_net_source(top_module, net_direct_src, src_grid_module, src_grid_instance, src_port_id, 0); - module_manager.add_module_net_sink(top_module, net_direct_src, direct_module, direct_instance_id, direct_input_port_id, 0); - - /* Create the 2nd module net */ - ModuleNetId net_direct_sink = module_manager.create_module_net(top_module); - /* Connect the wire between direct_instance output and sink_pin of clb */ - module_manager.add_module_net_source(top_module, net_direct_sink, direct_module, direct_instance_id, direct_output_port_id, 0); - module_manager.add_module_net_sink(top_module, net_direct_sink, sink_grid_module, sink_grid_instance, sink_port_id, 0); - } -} - -/******************************************************************** - * Add module net of clb-to-clb direct connections to module manager - * Note that the direct connections are not limited to CLBs only. - * It can be more generic and thus cover all the grid types, - * such as heterogeneous blocks - * - * This function supports the following type of direct connection: - * 1. Direct connection between grids in the same column or row - * +------+ +------+ - * | | | | - * | Grid |----->| Grid | - * | | | | - * +------+ +------+ - * | direction connection - * v - * +------+ - * | | - * | Grid | - * | | - * +------+ - * - *******************************************************************/ -static -void add_top_module_nets_intra_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { - /* Scan the grid, visit each grid and apply direct connections */ - for (size_t ix = 0; ix < device_size.x(); ++ix) { - for (size_t iy = 0; iy < device_size.y(); ++iy) { - /* Bypass EMPTY_TYPE*/ - if ( (NULL == grids[ix][iy].type) - || (EMPTY_TYPE == grids[ix][iy].type)) { - continue; - } - /* Bypass any grid with a non-zero offset! They have been visited in the offset=0 case */ - if (0 != grids[ix][iy].offset) { - continue; - } - /* Check each clb2clb directs by comparing the source and destination clb types - * Direct connections are made only for those matched clbs - */ - for (const t_clb_to_clb_directs& direct : clb2clb_directs) { - /* Bypass unmatched clb type */ - if (grids[ix][iy].type != direct.from_clb_type) { - continue; - } - - /* See if the destination CLB is in the bound */ - vtr::Point src_clb_coord(ix, iy); - vtr::Point des_clb_coord(ix + direct.x_offset, iy + direct.y_offset); - if (false == is_grid_coordinate_exist_in_device(device_size, des_clb_coord)) { - continue; - } - - /* Check if the destination clb_type matches */ - if (grids[des_clb_coord.x()][des_clb_coord.y()].type == direct.to_clb_type) { - /* Add a module net for a direct connection with the two grids in top_model */ - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } - } - } - } -} - -/******************************************************************** - * Find the coordinate of a grid in a specific column - * with a given type - * This function will return the coordinate of the grid that satifies - * the type requirement - *******************************************************************/ -static -vtr::Point find_grid_coordinate_given_type(const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& candidate_coords, - t_type_ptr wanted_grid_type) { - for (vtr::Point coord : candidate_coords) { - /* If the next column is not longer in device range, we can return */ - if (false == is_grid_coordinate_exist_in_device(device_size, coord)) { - continue; - } - if (wanted_grid_type == grids[coord.x()][coord.y()].type) { - return coord; - } - } - /* Return an valid coordinate */ - return vtr::Point(size_t(-1), size_t(-1)); -} - -/******************************************************************** - * Find the coordinate of the destination clb/heterogeneous block - * considering intra column/row direct connections in core grids - *******************************************************************/ -static -vtr::Point find_intra_direct_destination_coordinate(const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point src_coord, - const t_clb_to_clb_directs& direct) { - vtr::Point des_coord(size_t(-1), size_t(-1)); - t_type_ptr src_grid_type = grids[src_coord.x()][src_coord.y()].type; - - std::vector first_search_space; - std::vector second_search_space; - - /* Cross column connection from Bottom to Top on Right - * The next column may NOT have the grid type we want! - * Think about heterogeneous architecture! - * Our search space will start from the next column - * and ends at the RIGHT side of fabric - */ - if (P2P_DIRECT_COLUMN == direct.interconnection_type) { - if (POSITIVE_DIR == direct.x_dir) { - /* Our first search space will be in x-direction: - * - * x ... nx - * +-----+ - * |Grid | -----> - * +-----+ - */ - for (size_t ix = src_coord.x() + 1; ix < device_size.x() - 1; ++ix) { - first_search_space.push_back(ix); - } - } else { - VTR_ASSERT(NEGATIVE_DIR == direct.x_dir); - /* Our first search space will be in x-direction: - * - * 1 ... x - * +-----+ - * < -------|Grid | - * +-----+ - */ - for (size_t ix = src_coord.x() - 1; ix >= 1; --ix) { - first_search_space.push_back(ix); - } - } - - /* Our second search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * | . - * | . - * v . - * +------+ - * | Grid | 1 - * +------+ - */ - for (size_t iy = 1 ; iy < device_size.y() - 1; ++iy) { - second_search_space.push_back(iy); - } - - /* For negative direction, our second search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * ^ . - * | . - * | . - * +------+ - * | Grid | 1 - * +------+ - */ - if (NEGATIVE_DIR == direct.y_dir) { - std::reverse(second_search_space.begin(), second_search_space.end()); - } - } - - - /* Cross row connection from Bottom to Top on Right - * The next column may NOT have the grid type we want! - * Think about heterogeneous architecture! - * Our search space will start from the next column - * and ends at the RIGHT side of fabric - */ - if (P2P_DIRECT_ROW == direct.interconnection_type) { - if (POSITIVE_DIR == direct.y_dir) { - /* Our first search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * ^ . - * | . - * | . - * +------+ - * | Grid | y - * +------+ - */ - for (size_t iy = src_coord.y() + 1; iy < device_size.y() - 1; ++iy) { - first_search_space.push_back(iy); - } - } else { - VTR_ASSERT(NEGATIVE_DIR == direct.y_dir); - /* For negative y-direction, - * Our first search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * | . - * | . - * v . - * +------+ - * | Grid | y - * +------+ - */ - for (size_t iy = src_coord.y() - 1; iy >= 1; --iy) { - first_search_space.push_back(iy); - } - } - - /* Our second search space will be in x-direction: - * - * 1 ... nx - * +------+ +------+ - * | Grid |------>| Grid | - * +------+ +------+ - */ - for (size_t ix = 1 ; ix < device_size.x() - 1; ++ix) { - second_search_space.push_back(ix); - } - - /* For negative direction, - * our second search space will be in x-direction: - * - * 1 ... nx - * +------+ +------+ - * | Grid |<------| Grid | - * +------+ +------+ - */ - if (NEGATIVE_DIR == direct.x_dir) { - std::reverse(second_search_space.begin(), second_search_space.end()); - } - } - - for (size_t ix : first_search_space) { - std::vector> next_col_row_coords; - for (size_t iy : second_search_space) { - if (P2P_DIRECT_COLUMN == direct.interconnection_type) { - next_col_row_coords.push_back(vtr::Point(ix, iy)); - } else { - VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); - /* For cross-row connection, our search space is flipped */ - next_col_row_coords.push_back(vtr::Point(iy, ix)); - } - } - vtr::Point des_coord_cand = find_grid_coordinate_given_type(device_size, grids, next_col_row_coords, src_grid_type); - /* For a valid coordinate, we can return */ - if ( (size_t(-1) != des_coord_cand.x()) - && (size_t(-1) != des_coord_cand.y()) ) { - return des_coord_cand; - } - } - return des_coord; -} - -/******************************************************************** - * Add module net of clb-to-clb direct connections to module manager - * Note that the direct connections are not limited to CLBs only. - * It can be more generic and thus cover all the grid types, - * such as heterogeneous blocks - * - * This function supports the following type of direct connection: - * - * 1. Direct connections across columns and rows - * +------+ - * | | - * | v - * +------+ | +------+ - * | | | | | - * | Grid | | | Grid | - * | | | | | - * +------+ | +------+ - * | - * +------+ | +------+ - * | | | | | - * | Grid | | | Grid | - * | | | | | - * +------+ | +------+ - * | | - * +------+ - * - * Note that: this will only apply to the core grids! - * I/Os or any blocks on the border of fabric are NOT supported! - * - *******************************************************************/ -static -void add_top_module_nets_inter_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { - - std::vector border_sides = {TOP, RIGHT, BOTTOM, LEFT}; - - /* Go through the direct connection list, see if we need intra-column/row connection here */ - for (const t_clb_to_clb_directs& direct: clb2clb_directs) { - if ( (P2P_DIRECT_COLUMN != direct.interconnection_type) - && (P2P_DIRECT_ROW != direct.interconnection_type)) { - continue; - } - /* For cross-column connection, we will search the first valid grid in each column - * from y = 1 to y = ny - * - * +------+ - * | Grid | y=ny - * +------+ - * ^ - * | search direction (when y_dir is negative) - * ... - * | - * +------+ - * | Grid | y=1 - * +------+ - * - */ - if (P2P_DIRECT_COLUMN == direct.interconnection_type) { - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - std::vector> next_col_src_grid_coords; - /* For negative y- direction, we should start from y = ny */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); - } - /* For positive y- direction, we should start from y = 1 */ - if (POSITIVE_DIR == direct.y_dir) { - std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); - } - vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); - /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ - if ( (size_t(-1) == src_clb_coord.x()) - || (size_t(-1) == src_clb_coord.y()) ) { - continue; - } - /* For a valid coordinate, we can find the coordinate of the destination clb */ - vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); - /* If destination clb is valid, we should add something */ - if ( (size_t(-1) == des_clb_coord.x()) - || (size_t(-1) == des_clb_coord.y()) ) { - continue; - } - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } - continue; /* Go to next direct type */ - } - - /* Reach here, it must be a cross-row connection */ - VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); - /* For cross-row connection, we will search the first valid grid in each column - * from x = 1 to x = nx - * - * x=1 x=nx - * +------+ +------+ - * | Grid | <--- ... ---- | Grid | - * +------+ +------+ - * - */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - std::vector> next_col_src_grid_coords; - /* For negative x- direction, we should start from x = nx */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); - } - /* For positive x- direction, we should start from x = 1 */ - if (POSITIVE_DIR == direct.x_dir) { - std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); - } - vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); - /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ - if ( (size_t(-1) == src_clb_coord.x()) - || (size_t(-1) == src_clb_coord.y()) ) { - continue; - } - /* For a valid coordinate, we can find the coordinate of the destination clb */ - vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); - /* If destination clb is valid, we should add something */ - if ( (size_t(-1) == des_clb_coord.x()) - || (size_t(-1) == des_clb_coord.y()) ) { - continue; - } - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } - } -} - -/******************************************************************** - * Add module net of clb-to-clb direct connections to module manager - * Note that the direct connections are not limited to CLBs only. - * It can be more generic and thus cover all the grid types, - * such as heterogeneous blocks - *******************************************************************/ -static -void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { - - add_top_module_nets_intra_clb2clb_direct_connections(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - clb2clb_directs); - - add_top_module_nets_inter_clb2clb_direct_connections(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - clb2clb_directs); -} - /******************************************************************** * Print the top-level module for the FPGA fabric in Verilog format * This function will @@ -1421,13 +881,21 @@ void print_verilog_top_module(ModuleManager& module_manager, std::vector memory_modules; std::vector memory_instances; - /* TODO: Add module nets to connect memory cells inside + /* Organize the list of memory modules and instances */ + organize_top_module_memory_modules(module_manager, + circuit_lib, sram_model, cur_sram_orgz_info, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy, + memory_modules, memory_instances); + + /* Add module nets to connect memory cells inside * This is a one-shot addition that covers all the memory modules in this pb module! */ if (false == memory_modules.empty()) { - add_module_nets_memory_config_bus(module_manager, top_module, - memory_modules, memory_instances, - cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); + add_top_module_nets_memory_config_bus(module_manager, top_module, + memory_modules, memory_instances, + cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); } /* Start printing out Verilog netlists */ From db38f21412007de62768e300322351306364090d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 17:59:03 -0600 Subject: [PATCH 306/482] add netlist manager class --- .../vpr/SRC/fpga_x2p/base/netlist_manager.cpp | 184 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/netlist_manager.h | 86 ++++++++ .../SRC/fpga_x2p/base/netlist_manager_fwd.h | 20 ++ 3 files changed, 290 insertions(+) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp new file mode 100644 index 000000000..3d9d212ca --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp @@ -0,0 +1,184 @@ +/****************************************************************************** + * This files includes memeber functions for data structure NetlistManager + ******************************************************************************/ +#include + +#include "vtr_assert.h" +#include "netlist_manager.h" + +/****************************************************************************** + * Public aggregators + ******************************************************************************/ +/* Find all the netlists */ +NetlistManager::netlist_range NetlistManager::netlists() const { + return vtr::make_range(netlist_ids_.begin(), netlist_ids_.end()); +} + +/* Find all the modules that are included in a netlist */ +std::vector NetlistManager::netlist_modules(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + return included_module_ids_[netlist]; +} + + +/****************************************************************************** + * Public accessors + ******************************************************************************/ +/* Find the name of a netlist */ +std::string NetlistManager::netlist_name(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + return netlist_names_[netlist]; +} + +/* Find a netlist by its name */ +NetlistId NetlistManager::find_netlist(const std::string& netlist_name) const { + if (name_id_map_.find(netlist_name) != name_id_map_.end()) { + /* Found, return the id */ + return name_id_map_.at(netlist_name); + } + /* Not found, return an invalid id */ + return NetlistId::INVALID(); +} + +/* Find if a module belongs to a netlist */ +bool NetlistManager::is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + for (const ModuleId& included_module : included_module_ids_[netlist]) { + /* Already in the netlist, return true */ + if (module == included_module) { + return true; + } + } + + /* Not in the netlist, return false */ + return false; +} + +/* Find the netlist that a module belongs to */ +NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const { + /* Find if the module has been added to a netlist. If used, return false! */ + /* Not found, return an invalid value */ + if ( module_netlist_map_.end() + != module_netlist_map_.find(module)) { + return NetlistId::INVALID(); + } + return module_netlist_map_.at(module); +} + + +/* Find all the preprocessing flags that are included in a netlist */ +std::vector NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + std::vector flags; + + for (const PreprocessingFlagId& flag_id : included_preprocessing_flag_ids_[netlist]) { + VTR_ASSERT(true == valid_preprocessing_flag_id(flag_id)); + flags.push_back(preprocessing_flag_names_[flag_id]); + } + + return flags; +} + +/****************************************************************************** + * Public mutators + ******************************************************************************/ +/* Add a netlist to the library */ +NetlistId NetlistManager::add_netlist(const std::string& name) { + /* Find if the name has been used. If used, return an invalid Id! */ + std::map::iterator it = name_id_map_.find(name); + if (it != name_id_map_.end()) { + return NetlistId::INVALID(); + } + + /* Create a new id */ + NetlistId netlist = NetlistId(netlist_ids_.size()); + netlist_ids_.push_back(netlist); + + /* Allocate related attributes */ + netlist_names_.push_back(name); + included_module_ids_.emplace_back(); + included_preprocessing_flag_ids_.emplace_back(); + + /* Register in the name-to-id map */ + name_id_map_[name] = netlist; + + return netlist; +} + +/* Add a module to a netlist in the library */ +bool NetlistManager::add_netlist_module(const NetlistId& netlist, const ModuleId& module) { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + /* Find if the module already in the netlist */ + std::vector::iterator module_it = std::find(included_module_ids_[netlist].begin(), included_module_ids_[netlist].end(), module); + if (module_it != included_module_ids_[netlist].end()) { + /* Already in the netlist, nothing to do */ + return true; + } + /* Try to register it in module-to-netlist map */ + /* Find if the module has been added to a netlist. If used, return false! */ + std::map::iterator map_it = module_netlist_map_.find(module); + if (map_it != module_netlist_map_.end()) { + return false; + } + + /* Does not exist! Should add it to the list */ + included_module_ids_[netlist].push_back(module); + /* Register it in module-to-netlist map */ + module_netlist_map_[module] = netlist; + return true; +} + +/* Add a pre-processing flag to a netlist */ +void NetlistManager::add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag) { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + PreprocessingFlagId flag = PreprocessingFlagId(preprocessing_flag_ids_.size()); + + /* Find if the module already in the netlist */ + for (const PreprocessingFlagId& id : preprocessing_flag_ids_) { + if (0 != preprocessing_flag.compare(preprocessing_flag_names_[id])) { + continue; + } + /* Already in the list of pre-processing flags, push it ot the */ + flag = id; + break; + } + + /* Update the list if we need */ + if (flag == PreprocessingFlagId(preprocessing_flag_ids_.size())) { + preprocessing_flag_ids_.push_back(flag); + preprocessing_flag_names_.push_back(preprocessing_flag); + } + + /* Check if the flag is already in the netlist */ + std::vector::iterator it = std::find(included_preprocessing_flag_ids_[netlist].begin(), included_preprocessing_flag_ids_[netlist].end(), flag); + if (it == included_preprocessing_flag_ids_[netlist].end()) { + /* Not in the list, we add it */ + included_preprocessing_flag_ids_[netlist].push_back(flag); + } +} + +/****************************************************************************** + * Public validators/invalidators + ******************************************************************************/ +bool NetlistManager::valid_netlist_id(const NetlistId& netlist) const { + return (size_t(netlist) < netlist_ids_.size()) && (netlist == netlist_ids_[netlist]); +} + +/****************************************************************************** + * Private validators/invalidators + ******************************************************************************/ +bool NetlistManager::valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const { + return (size_t(flag) < preprocessing_flag_ids_.size()) && (flag == preprocessing_flag_ids_[flag]); +} + +void NetlistManager::invalidate_name2id_map() { + name_id_map_.clear(); +} + +void NetlistManager::invalidate_module2netlist_map() { + module_netlist_map_.clear(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h new file mode 100644 index 000000000..2e0b4f2c0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h @@ -0,0 +1,86 @@ +/****************************************************************************** + * This files includes data structures for netlist management. + * It keeps a list of netlists that have been created + * Each netlist includes a list of ids of modules that are stored in ModuleManager + * + * When we want to dump out a netlist in Verilog/SPICE format, + * the netlist manager can generate the dependency on other netlists + * This can help us tracking the dependency and generate `include` files easily + * + * Cross-reference: + * + * +---------+ +---------+ + * | | ModuleId | | + * | Netlist |-------------->| Module | + * | Manager | | Manager | + * | | | | + * +---------+ +---------+ + * + ******************************************************************************/ +#ifndef NETLIST_MANAGER_H +#define NETLIST_MANAGER_H + +#include +#include +#include +#include "vtr_vector.h" +#include "netlist_manager_fwd.h" +#include "module_manager.h" + +class NetlistManager { + public: /* Types and ranges */ + typedef vtr::vector::const_iterator netlist_iterator; + + typedef vtr::Range netlist_range; + + public: /* Public aggregators */ + /* Find all the netlists */ + netlist_range netlists() const; + /* Find all the modules that are included in a netlist */ + std::vector netlist_modules(const NetlistId& netlist) const; + /* Find all the preprocessing flags that are included in a netlist */ + std::vector netlist_preprocessing_flags(const NetlistId& netlist) const; + + public: /* Public accessors */ + /* Find the name of a netlist */ + std::string netlist_name(const NetlistId& netlist) const; + /* Find a netlist by its name */ + NetlistId find_netlist(const std::string& netlist_name) const; + /* Find if a module belongs to a netlist */ + bool is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const; + /* Find the netlist that a module belongs to */ + NetlistId find_module_netlist(const ModuleId& module) const; + + public: /* Public mutators */ + /* Add a netlist to the library */ + NetlistId add_netlist(const std::string& name); + /* Add a module to a netlist in the library */ + bool add_netlist_module(const NetlistId& netlist, const ModuleId& module); + /* Add a pre-processing flag to a netlist */ + void add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag); + + public: /* Public validators/invalidators */ + bool valid_netlist_id(const NetlistId& netlist) const; + + private: /* Private validators/invalidators */ + bool valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const; + void invalidate_name2id_map(); + void invalidate_module2netlist_map(); + + private: /* Internal data */ + vtr::vector netlist_ids_; + vtr::vector netlist_names_; + vtr::vector> included_module_ids_; + vtr::vector> included_preprocessing_flag_ids_; + + vtr::vector preprocessing_flag_ids_; + vtr::vector preprocessing_flag_names_; + + /* fast look-up for netlist */ + std::map name_id_map_; + /* fast look-up for modules in netlists */ + std::map module_netlist_map_; +}; + +#endif + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h new file mode 100644 index 000000000..bdf58f58b --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h @@ -0,0 +1,20 @@ +/************************************************** + * This file includes only declarations for + * the data structures for netlist managers + * Please refer to netlist_manager.h for more details + *************************************************/ +#ifndef NETLIST_MANAGER_FWD_H +#define NETLIST_MANAGER_FWD_H + +#include "vtr_strong_id.h" + +/* Strong Ids for ModuleManager */ +struct netlist_id_tag; +struct preprocessing_flag_id_tag; + +typedef vtr::StrongId NetlistId; +typedef vtr::StrongId PreprocessingFlagId; + +class NetlistManager; + +#endif From 3b82d62d03cc59410e773ff0f2d37a09ce815778 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 20:02:02 -0600 Subject: [PATCH 307/482] start developing module graph builders --- vpr7_x2p/vpr/SRC/device/mux_library_builder.h | 4 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 11 ++- .../module_builder/build_device_modules.cpp | 73 +++++++++++++++++++ .../module_builder/build_device_modules.h | 12 +++ .../build_top_module_directs.cpp | 0 .../build_top_module_directs.h | 0 .../build_top_module_memory.cpp | 0 .../build_top_module_memory.h | 0 8 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h rename vpr7_x2p/vpr/SRC/fpga_x2p/{base => module_builder}/build_top_module_directs.cpp (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{base => module_builder}/build_top_module_directs.h (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{base => module_builder}/build_top_module_memory.cpp (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{base => module_builder}/build_top_module_memory.h (100%) diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.h b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h index 8a0965dd4..ed66ad686 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_library_builder.h +++ b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h @@ -6,6 +6,10 @@ #ifndef MUX_LIBRARY_BUILDER_H #define MUX_LIBRARY_BUILDER_H +#include "vpr_types.h" +#include "circuit_library.h" +#include "mux_library.h" + MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_switch_inf* switches, const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 858607a58..4cde95684 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -30,11 +30,14 @@ #include "verilog_api.h" #include "fpga_bitstream.h" +#include "mux_library_builder.h" +#include "build_device_modules.h" + #include "fpga_x2p_api.h" /* Top-level API of FPGA-SPICE */ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, - t_arch Arch) { + t_arch Arch) { t_sram_orgz_info* sram_bitstream_orgz_info = NULL; /* Common initializations and malloc operations */ @@ -43,6 +46,12 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, fpga_x2p_setup(vpr_setup, &Arch); } + /* Build multiplexer graphs */ + MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); + + /* Build module graphs */ + ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib); + /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) { vpr_fpga_spice(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp new file mode 100644 index 000000000..bbdfb0210 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp @@ -0,0 +1,73 @@ +/******************************************************************** + * This file includes the main function to build module graphs + * for the FPGA fabric + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "util.h" +#include "spice_types.h" +#include "fpga_x2p_utils.h" + +#include "build_device_modules.h" + +/******************************************************************** + * The main function to be called for building module graphs + * for a FPGA fabric + *******************************************************************/ +ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, + const t_arch& arch, + const MuxLibrary& mux_lib) { + /* Check if the routing architecture we support*/ + if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR, + "FPGA X2P only supports uni-directional routing architecture!\n"); + exit(1); + } + + /* We don't support mrFPGA */ +#ifdef MRFPGA_H + if (is_mrFPGA) { + vpr_printf(TIO_MESSAGE_ERROR, + "FPGA X2P does not support mrFPGA!\n"); + exit(1); + } +#endif + + /* Module Graph builder formally starts*/ + vpr_printf(TIO_MESSAGE_INFO, "\nStart building module graphs for FPGA fabric...\n"); + + /* Module manager to be built */ + ModuleManager module_manager; + + /* Start time count */ + clock_t t_start = clock(); + + /* Assign the SRAM model applied to the FPGA fabric */ + VTR_ASSERT(NULL != arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ + t_spice_model* mem_model = arch.sram_inf.verilog_sram_inf_orgz->spice_model; + /* initialize the SRAM organization information struct */ + CircuitModelId sram_model = arch.spice->circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* TODO: This should be moved to FPGA-X2P setup + * Check all the SRAM port is using the correct SRAM circuit model + */ + config_spice_models_sram_port_spice_model(arch.spice->num_spice_model, + arch.spice->spice_models, + arch.sram_inf.verilog_sram_inf_orgz->spice_model); + config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model); + + /* TODO: Build elmentary modules */ + + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "Building module graphs took %g seconds\n", run_time_sec); + + + return module_manager; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h new file mode 100644 index 000000000..91bd7b629 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h @@ -0,0 +1,12 @@ +#ifndef BUILD_DEVICE_MODULES_H +#define BUILD_DEVICE_MODULES_H + +#include "vpr_types.h" +#include "mux_library.h" +#include "module_manager.h" + +ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, + const t_arch& arch, + const MuxLibrary& mux_lib); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_directs.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/build_top_module_memory.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h From 7c1bce4b5984d611f01593afad43bdc66eecd97f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 20:41:05 -0600 Subject: [PATCH 308/482] add module builders for essential gates --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- ...ice_modules.cpp => build_module_graph.cpp} | 19 ++++++++++++++++++- ..._device_modules.h => build_module_graph.h} | 4 ++-- 3 files changed, 21 insertions(+), 4 deletions(-) rename vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/{build_device_modules.cpp => build_module_graph.cpp} (82%) rename vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/{build_device_modules.h => build_module_graph.h} (82%) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 4cde95684..847c23742 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -31,7 +31,7 @@ #include "fpga_bitstream.h" #include "mux_library_builder.h" -#include "build_device_modules.h" +#include "build_module_graph.h" #include "fpga_x2p_api.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp similarity index 82% rename from vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index bbdfb0210..d918f5940 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -10,7 +10,8 @@ #include "spice_types.h" #include "fpga_x2p_utils.h" -#include "build_device_modules.h" +#include "build_essential_modules.h" +#include "build_module_graph.h" /******************************************************************** * The main function to be called for building module graphs @@ -60,7 +61,23 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model); /* TODO: Build elmentary modules */ + build_essential_modules(module_manager, arch.spice->circuit_lib); + /* TODO: Build local encoders for multiplexers, this MUST be called before multiplexer building */ + + /* TODO: Build multiplexer modules */ + + /* TODO: Build LUT modules */ + + /* TODO: Build wire modules */ + + /* TODO: Build memory modules */ + + /* TODO: Build grid and programmable block modules */ + + /* TODO: Build global routing architecture modules */ + + /* TODO: Build FPGA fabric top-level module */ /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h similarity index 82% rename from vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h index 91bd7b629..3e3ad5806 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h @@ -1,5 +1,5 @@ -#ifndef BUILD_DEVICE_MODULES_H -#define BUILD_DEVICE_MODULES_H +#ifndef BUILD_MODULE_GRAPH_H +#define BUILD_MODULE_GRAPH_H #include "vpr_types.h" #include "mux_library.h" From fbe56a06c47bceb9e4eb873c711c573999975dd1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 21:01:10 -0600 Subject: [PATCH 309/482] add decoder module builders --- .../module_builder/build_decoder_modules.cpp | 131 ++++++++++++++++++ .../module_builder/build_decoder_modules.h | 15 ++ .../module_builder/build_module_graph.cpp | 6 +- 3 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp new file mode 100644 index 000000000..e8b02998e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp @@ -0,0 +1,131 @@ +/*************************************************************************************** + * This file includes functions that are used to build modules for decoders, including: + * 1. Local decoders used by multiplexers ONLY + * 2. Decoders used by grid/routing/top-level module for memory address decoding + ***************************************************************************************/ +#include +#include "util.h" +#include "vtr_assert.h" + +#include "fpga_x2p_naming.h" +#include "decoder_library_utils.h" +#include "module_manager_utils.h" + +#include "build_decoder_modules.h" + +/*************************************************************************************** + * Create a module for a decoder with a given output size + * + * Inputs + * | | ... | + * v v v + * +-----------+ + * / \ + * / Decoder \ + * +-----------------+ + * | | | ... | | | + * v v v v v v + * Outputs + * + * The outputs are assumes to be one-hot codes (at most only one '1' exist) + * Considering this fact, there are only num_of_outputs conditions to be encoded. + * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) + ***************************************************************************************/ +static +void build_mux_local_decoder_module(ModuleManager& module_manager, + const DecoderLibrary& decoder_lib, + const DecoderId& decoder) { + /* Get the number of inputs */ + size_t addr_size = decoder_lib.addr_size(decoder); + size_t data_size = decoder_lib.data_size(decoder); + + /* TODO: create a name for the local encoder */ + std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); + /* Add module ports */ + /* Add each input port */ + BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size); + module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size); + module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Data port is registered. It should be outputted as + * output reg [lsb:msb] data + */ + module_manager.set_port_is_register(module_id, data_port.get_name(), true); + /* Add data_in port */ + BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size); + VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder)); + module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT); +} + + +/*************************************************************************************** + * This function will generate all the unique Verilog modules of local decoders for + * the multiplexers used in a FPGA fabric + * It will reach the goal in two steps: + * 1. Find the unique local decoders w.r.t. the number of inputs/outputs + * We will generate the subgraphs from the multiplexing graph of each multiplexers + * The number of memory bits is the number of outputs. + * From that we can infer the number of inputs of each local decoders. + * Here is an illustrative example of how local decoders are interfaced with multi-level MUXes + * + * +---------+ +---------+ + * | Local | | Local | + * | Decoder | | Decoder | + * | A | | B | + * +---------+ +---------+ + * | ... | | ... | + * v v v v + * +--------------+ +--------------+ + * | MUX Level 0 |--->| MUX Level 1 | + * +--------------+ +--------------+ + * 2. Generate local decoder Verilog modules using behavioral description. + * Note that the implementation of local decoders can be dependent on the technology + * and standard cell libraries. + * Therefore, behavioral Verilog is used and the local decoders should be synthesized + * before running the back-end flow for FPGA fabric + * See more details in the function print_verilog_mux_local_decoder() for more details + ***************************************************************************************/ +void build_mux_local_decoder_modules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib) { + /* Create a library for local encoders with different sizes */ + DecoderLibrary decoder_lib; + + /* Find unique local decoders for unique branches shared by the multiplexers */ + for (auto mux : mux_lib.muxes()) { + /* Local decoders are need only when users specify them */ + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* If this MUX does not need local decoder, we skip it */ + if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) { + continue; + } + + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + /* Create a mux graph for the branch circuit */ + std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); + /* Add the decoder to the decoder library */ + for (auto branch_mux_graph : branch_mux_graphs) { + /* The decoder size depends on the number of memories of a branch MUX. + * Note that only when there are >=2 memories, a decoder is needed + */ + size_t decoder_data_size = branch_mux_graph.num_memory_bits(); + if (0 == decoder_data_size) { + continue; + } + /* Try to find if the decoder already exists in the library, + * If there is no such decoder, add it to the library + */ + add_mux_local_decoder_to_library(decoder_lib, decoder_data_size); + } + } + + /* Generate Verilog modules for the found unique local encoders */ + for (const auto& decoder : decoder_lib.decoders()) { + build_mux_local_decoder_module(module_manager, decoder_lib, decoder); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h new file mode 100644 index 000000000..888eae41f --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h @@ -0,0 +1,15 @@ +/*************************************************************************************** + * Header file for build_decoder_modules.cpp + ***************************************************************************************/ +#ifndef BUILD_DECODER_MODULES_H +#define BUILD_DECODER_MODULES_H + +#include "module_manager.h" +#include "mux_library.h" +#include "circuit_library.h" + +void build_mux_local_decoder_modules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index d918f5940..bcedb949c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -11,6 +11,7 @@ #include "fpga_x2p_utils.h" #include "build_essential_modules.h" +#include "build_decoder_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -60,10 +61,11 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, arch.sram_inf.verilog_sram_inf_orgz->spice_model); config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model); - /* TODO: Build elmentary modules */ + /* Build elmentary modules */ build_essential_modules(module_manager, arch.spice->circuit_lib); - /* TODO: Build local encoders for multiplexers, this MUST be called before multiplexer building */ + /* Build local encoders for multiplexers, this MUST be called before multiplexer building */ + build_mux_local_decoder_modules(module_manager, mux_lib, arch.spice->circuit_lib); /* TODO: Build multiplexer modules */ From b1cafcdbde8c26e3301891acde44c05294d5579d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 21:04:35 -0600 Subject: [PATCH 310/482] add missing files --- .../build_essential_modules.cpp | 165 ++++++++++++++++++ .../module_builder/build_essential_modules.h | 10 ++ 2 files changed, 175 insertions(+) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp new file mode 100644 index 000000000..3458cd819 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -0,0 +1,165 @@ +/******************************************************************** + * This function includes the module builders for essential logic gates + * which are the leaf circuit model in the circuit library + *******************************************************************/ +#include +#include "util.h" +#include "vtr_assert.h" + +#include "module_manager_utils.h" +#include "build_essential_modules.h" + +/************************************************ + * Build a module of inverter or buffer + * or tapered buffer to a file + ***********************************************/ +static +void build_invbuf_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Find the input port, output port and global inputs*/ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); + + /* Make sure: + * There is only 1 input port and 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* TODO: move the check codes to check_circuit_library.h */ + /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ + if (true == circuit_lib.is_power_gated(circuit_model)) { + /* Check all the ports we have are good for a power-gated circuit model */ + size_t num_err = 0; + /* We need at least one global port */ + if (0 == global_ports.size()) { + num_err++; + } + /* All the global ports should be config_enable */ + for (const auto& port : global_ports) { + if (false == circuit_lib.port_is_config_enable(port)) { + num_err++; + } + } + /* Report errors if there are any */ + if (0 < num_err) { + vpr_printf(TIO_MESSAGE_ERROR, + "Inverter/buffer circuit model (name=%s) is power-gated. At least one config-enable global port is required!\n", + circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + } + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); +} + +/************************************************ + * Build a module of a pass-gate, + * either transmission-gate or pass-transistor + ***********************************************/ +static +void build_passgate_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); + + switch (circuit_lib.pass_gate_logic_type(circuit_model)) { + case SPICE_MODEL_PASS_GATE_TRANSMISSION: + /* Make sure: + * There is only 3 input port (in, sel, selb), + * each size of which is 1 + */ + VTR_ASSERT( 3 == input_ports.size() ); + for (const auto& input_port : input_ports) { + VTR_ASSERT(1 == circuit_lib.port_size(input_port)); + } + break; + case SPICE_MODEL_PASS_GATE_TRANSISTOR: + /* Make sure: + * There is only 2 input port (in, sel), + * each size of which is 1 + */ + VTR_ASSERT( 2 == input_ports.size() ); + for (const auto& input_port : input_ports) { + VTR_ASSERT(1 == circuit_lib.port_size(input_port)); + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + + /* Make sure: + * There is only 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); +} + +/************************************************ + * Build a module of a logic gate + * which are standard cells + * Supported gate types: + * 1. N-input AND + * 2. N-input OR + * 3. 2-input MUX + ***********************************************/ +static +void build_gate_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model) { + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); + + /* Make sure: + * There is only 1 output port, + * each size of which is 1 + */ + VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); +} + + +/************************************************ + * Generate the modules for essential gates + * include inverters, buffers, transmission-gates, + * etc. + ***********************************************/ +void build_essential_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib) { + + for (const auto& circuit_model : circuit_lib.models()) { + if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { + build_invbuf_module(module_manager, circuit_lib, circuit_model); + continue; + } + if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { + build_passgate_module(module_manager, circuit_lib, circuit_model); + continue; + } + if (SPICE_MODEL_GATE == circuit_lib.model_type(circuit_model)) { + build_gate_module(module_manager, circuit_lib, circuit_model); + continue; + } + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h new file mode 100644 index 000000000..2ad073740 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h @@ -0,0 +1,10 @@ +#ifndef BUILD_ESSENTIAL_MODULES_H +#define BUILD_ESSENTIAL_MODULES_H + +#include "circuit_library.h" +#include "module_manager.h" + +void build_essential_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib); + +#endif From 04f0fbebf7a0244058ed02e1ed1a8123896cfe64 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Oct 2019 21:59:22 -0600 Subject: [PATCH 311/482] plug in module graph to feed verilog writers --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 9 ++-- .../build_essential_modules.cpp | 54 +++++++++++++++++++ .../module_builder/build_essential_modules.h | 4 ++ .../module_builder/build_module_graph.cpp | 11 ++++ .../vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h | 9 +++- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 +-- .../vpr/SRC/fpga_x2p/verilog/verilog_api.h | 10 +++- .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 8 +-- .../verilog/verilog_essential_gates.cpp | 9 ++-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 15 ++++-- 11 files changed, 114 insertions(+), 23 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 847c23742..20e2bd1d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -26,13 +26,14 @@ #include "fpga_x2p_utils.h" #include "fpga_x2p_backannotate_utils.h" #include "fpga_x2p_setup.h" -#include "spice_api.h" -#include "verilog_api.h" -#include "fpga_bitstream.h" #include "mux_library_builder.h" #include "build_module_graph.h" +#include "spice_api.h" +#include "verilog_api.h" +#include "fpga_bitstream.h" + #include "fpga_x2p_api.h" /* Top-level API of FPGA-SPICE */ @@ -59,7 +60,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Xifan TANG: Synthesizable verilog dumping */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) { - vpr_fpga_verilog(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); + vpr_fpga_verilog(module_manager, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); } /* Xifan Tang: Bitstream Generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 3458cd819..006584d36 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -6,6 +6,7 @@ #include "util.h" #include "vtr_assert.h" +#include "fpga_x2p_naming.h" #include "module_manager_utils.h" #include "build_essential_modules.h" @@ -163,3 +164,56 @@ void build_essential_modules(ModuleManager& module_manager, } } +/********************************************************************* + * Register all the user-defined modules in the module manager + * Walk through the circuit library and add user-defined circuit models + * to the module_manager + ********************************************************************/ +void build_user_defined_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector& routing_segments) { + /* Iterate over Verilog modules */ + for (const auto& model : circuit_lib.models()) { + /* We only care about user-defined models */ + if ( (true == circuit_lib.model_verilog_netlist(model).empty()) + && (true == circuit_lib.model_verilog_netlist(model).empty()) ) { + continue; + } + /* Skip Routing channel wire models because they need a different name. Do it later */ + if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { + continue; + } + /* Reach here, the model requires a user-defined Verilog netlist, + * Register it in the module_manager + */ + add_circuit_model_to_module_manager(module_manager, circuit_lib, model); + } + + /* Register the routing channel wires */ + for (const auto& seg : routing_segments) { + VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); + VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); + /* We care only user-defined circuit models */ + if ( (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) + && (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) ) { + continue; + } + /* Give a unique name for subckt of wire_model of segment, + * circuit_model name is unique, and segment id is unique as well + */ + std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); + + /* Find the output port*/ + std::vector output_ports = circuit_lib.model_ports_by_type(seg.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Make sure the port size is what we want */ + VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); + + /* Add a mid-output port to the module */ + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h index 2ad073740..d91c529fc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h @@ -7,4 +7,8 @@ void build_essential_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib); +void build_user_defined_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector& routing_segments); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index bcedb949c..39cfdd453 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -61,6 +61,17 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, arch.sram_inf.verilog_sram_inf_orgz->spice_model); config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model); + /* Create a vector of segments. TODO: should come from DeviceContext */ + std::vector L_segment_vec; + for (int i = 0; i < arch.num_segments; ++i) { + L_segment_vec.push_back(arch.Segments[i]); + } + /* Register all the user-defined modules in the module manager + * This should be done prior to other steps in this function, + * because they will be instanciated by other primitive modules + */ + build_user_defined_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); + /* Build elmentary modules */ build_essential_modules(module_manager, arch.spice->circuit_lib); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c index f030867b4..6a6ded446 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c @@ -51,7 +51,7 @@ void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) { return; } - vpr_fpga_verilog(env->vpr_setup, env->arch, + vpr_fpga_verilog(env->module_manager, env->vpr_setup, env->arch, env->vpr_setup.FileNameOpts.CircuitName); return; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h index db7fd771c..1b7df8dc1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h @@ -1,3 +1,9 @@ +#ifndef SHELL_TYPES_H +#define SHELL_TYPES_H + +#include "vpr_types.h" +#include "module_manager.h" + typedef struct s_cmd_category t_cmd_category; typedef struct s_shell_cmd t_shell_cmd; @@ -28,6 +34,7 @@ struct s_shell_cmd { }; struct s_shell_env { + ModuleManager module_manager; t_arch arch; t_vpr_setup vpr_setup; t_shell_cmd* cmd; @@ -36,4 +43,4 @@ struct s_shell_env { #define LAST_CMD_NAME NULL - +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index c0c35d1bd..18a740293 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -117,7 +117,8 @@ void free_global_routing_conf_bits() { } /* Top-level function*/ -void vpr_fpga_verilog(t_vpr_setup vpr_setup, +void vpr_fpga_verilog(ModuleManager& module_manager, + t_vpr_setup vpr_setup, t_arch Arch, char* circuit_name) { /* Timer */ @@ -158,9 +159,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, t_sram_orgz_info* sram_verilog_orgz_info = NULL; - /* Module manager for the Verilog modules created */ - ModuleManager module_manager; - /* Build Multiplexer library */ MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h index a8135f44b..1fc9c6104 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h @@ -1,4 +1,12 @@ +#ifndef VERILOG_API_H +#define VERILOG_API_H -void vpr_fpga_verilog(t_vpr_setup vpr_setup, +#include "vpr_types.h" +#include "module_manager.h" + +void vpr_fpga_verilog(ModuleManager& module_manager, + t_vpr_setup vpr_setup, t_arch Arch, char* circuit_name); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index 4e3a7c422..7021e3b43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -55,23 +55,19 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); + ModuleId module_id = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); /* Add module ports */ /* Add each input port */ BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size); - module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT); /* Add each output port */ BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size); - module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT); /* Data port is registered. It should be outputted as * output reg [lsb:msb] data */ - module_manager.set_port_is_register(module_id, data_port.get_name(), true); /* Add data_in port */ BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size); VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder)); - module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index a38c50230..a00788b08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -182,7 +182,8 @@ void print_verilog_invbuf_module(ModuleManager& module_manager, } /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); + ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); @@ -270,7 +271,8 @@ void print_verilog_passgate_module(ModuleManager& module_manager, VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); + ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); @@ -453,7 +455,8 @@ void print_verilog_gate_module(ModuleManager& module_manager, VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); + ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 3a2723ec2..91080490b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3098,9 +3098,13 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager, continue; } /* Reach here, the model requires a user-defined Verilog netlist, - * Register it in the module_manager + * Try to find it in the module manager + * If not found, register it in the module_manager */ - add_circuit_model_to_module_manager(module_manager, circuit_lib, model); + ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model)); + if (ModuleId::INVALID() == module_id) { + add_circuit_model_to_module_manager(module_manager, circuit_lib, model); + } } /* Register the routing channel wires */ @@ -3116,7 +3120,12 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager, */ std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - /* Create a Verilog Module based on the circuit model, and add to module manager */ + /* Try to find the module in the module manager, + * If not found, create a Verilog Module based on the circuit model, + * and add to module manager */ + if (ModuleId::INVALID() != module_manager.find_module(segment_wire_subckt_name)) { + continue; + } ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); /* Find the output port*/ From 520e145af2ae99f05e92470e364fda9ca42a42e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 19 Oct 2019 19:13:52 -0600 Subject: [PATCH 312/482] move mux_lib to fpga_x2p_setup --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c | 3 ++- vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h | 3 ++- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 4 +--- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h | 2 ++ 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 20e2bd1d1..8ab75ad0c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -60,7 +60,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Xifan TANG: Synthesizable verilog dumping */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) { - vpr_fpga_verilog(module_manager, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); + vpr_fpga_verilog(module_manager, mux_lib, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); } /* Xifan Tang: Bitstream Generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c index 6a6ded446..b1551efde 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c @@ -51,7 +51,8 @@ void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) { return; } - vpr_fpga_verilog(env->module_manager, env->vpr_setup, env->arch, + vpr_fpga_verilog(env->module_manager, env->mux_lib, + env->vpr_setup, env->arch, env->vpr_setup.FileNameOpts.CircuitName); return; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h index 1b7df8dc1..fe80b970b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h @@ -2,9 +2,9 @@ #define SHELL_TYPES_H #include "vpr_types.h" +#include "mux_library.h" #include "module_manager.h" - typedef struct s_cmd_category t_cmd_category; typedef struct s_shell_cmd t_shell_cmd; typedef struct s_shell_env t_shell_env; @@ -35,6 +35,7 @@ struct s_shell_cmd { struct s_shell_env { ModuleManager module_manager; + MuxLibrary mux_lib; t_arch arch; t_vpr_setup vpr_setup; t_shell_cmd* cmd; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 18a740293..b2ecbae94 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -118,6 +118,7 @@ void free_global_routing_conf_bits() { /* Top-level function*/ void vpr_fpga_verilog(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_vpr_setup vpr_setup, t_arch Arch, char* circuit_name) { @@ -159,9 +160,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, t_sram_orgz_info* sram_verilog_orgz_info = NULL; - /* Build Multiplexer library */ - MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); - /* 0. basic units: inverter, buffers and pass-gate logics, */ /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h index 1fc9c6104..9fc1e4b25 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h @@ -2,9 +2,11 @@ #define VERILOG_API_H #include "vpr_types.h" +#include "mux_library.h" #include "module_manager.h" void vpr_fpga_verilog(ModuleManager& module_manager, + const MuxLibrary& mux_lib, t_vpr_setup vpr_setup, t_arch Arch, char* circuit_name); From b2f57ecf81f01639b53ae83aacf42ffe2ad3be38 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 00:00:30 -0600 Subject: [PATCH 313/482] plug in MUX module graph generation, still local encoders contain dangling net, bug fixing --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 41 +- vpr7_x2p/vpr/SRC/device/mux_graph.h | 4 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 34 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 8 + .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 94 +- .../vpr/SRC/fpga_x2p/base/module_manager.h | 11 + .../SRC/fpga_x2p/base/module_manager_fwd.h | 2 + .../build_essential_modules.cpp | 30 + .../module_builder/build_essential_modules.h | 2 + .../module_builder/build_module_graph.cpp | 10 +- .../module_builder/build_mux_modules.cpp | 1464 +++++++++++++++++ .../module_builder/build_mux_modules.h | 19 + .../verilog/verilog_module_writer.cpp | 38 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 824 +--------- 14 files changed, 1792 insertions(+), 789 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 4ce432657..b453ffef8 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -45,15 +45,24 @@ MuxGraph::node_range MuxGraph::nodes() const { /* Find the non-input nodes */ std::vector MuxGraph::non_input_nodes() const { + /* Must be an valid graph */ + VTR_ASSERT_SAFE(valid_mux_graph()); std::vector node_list; - for (const auto& node : nodes()) { - /* Bypass any nodes which are not OUTPUT and INTERNAL */ - if (MUX_INPUT_NODE == node_types_[node]) { - continue; + + /* Build the node list, level by level */ + for (size_t level = 0; level < num_node_levels(); ++level) { + for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) { + /* Bypass any nodes which are not OUTPUT and INTERNAL */ + if (size_t(MUX_INPUT_NODE) == node_type) { + continue; + } + /* Reach here, this is either an OUTPUT or INTERNAL node */ + for (auto node : node_lookup_[level][node_type]) { + node_list.push_back(node); + } } - /* Reach here, this is either an OUTPUT or INTERNAL node */ - node_list.push_back(node); } + return node_list; } @@ -436,15 +445,29 @@ MuxInputId MuxGraph::input_id(const MuxNodeId& node_id) const { return node_input_ids_[node_id]; } -/* Get the input id of a given node */ +/* Identify if the node is an input of the MUX */ +bool MuxGraph::is_node_input(const MuxNodeId& node_id) const { + /* Validate node id */ + VTR_ASSERT(true == valid_node_id(node_id)); + return (MUX_INPUT_NODE == node_types_[node_id]); +} + +/* Get the output id of a given node */ MuxOutputId MuxGraph::output_id(const MuxNodeId& node_id) const { /* Validate node id */ VTR_ASSERT(valid_node_id(node_id)); - /* Must be an input */ + /* Must be an output */ VTR_ASSERT(MUX_OUTPUT_NODE == node_types_[node_id]); return node_output_ids_[node_id]; } +/* Identify if the node is an output of the MUX */ +bool MuxGraph::is_node_output(const MuxNodeId& node_id) const { + /* Validate node id */ + VTR_ASSERT(true == valid_node_id(node_id)); + return (MUX_OUTPUT_NODE == node_types_[node_id]); +} + /* Get the node id of a given input */ MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { /* Use the node_lookup to accelerate the search */ @@ -1045,7 +1068,7 @@ bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const { } bool MuxGraph::valid_level(const size_t& level) const { - return level < num_levels(); + return level < num_node_levels(); } bool MuxGraph::valid_node_lookup() const { diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index ed1f4773d..6774389f0 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -109,8 +109,12 @@ class MuxGraph { MuxNodeId node_id(const size_t& node_level, const size_t& node_index_at_level) const; /* Get the input id of a given node */ MuxInputId input_id(const MuxNodeId& node_id) const; + /* Identify if the node is an input of the MUX */ + bool is_node_input(const MuxNodeId& node_id) const; /* Get the output id of a given node */ MuxOutputId output_id(const MuxNodeId& node_id) const; + /* Identify if the node is an output of the MUX */ + bool is_node_output(const MuxNodeId& node_id) const; /* Decode memory bits based on an input id */ std::vector decode_memory_bits(const MuxInputId& input_id) const; private: /* Private mutators : basic operations */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 082e333a0..acd88162e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -33,6 +33,19 @@ std::string generate_mux_node_name(const size_t& node_level, return node_name; } + /************************************************ + * Generate the instance name for a branch circuit in multiplexing structure + * Case 1 : If there is an intermediate buffer followed by, + * the node name will be mux_l_in_buf + * Case 1 : If there is NO intermediate buffer followed by, + * the node name will be mux_l_in + ***********************************************/ +std::string generate_mux_branch_instance_name(const size_t& node_level, + const size_t& node_index_at_level, + const bool& add_buffer_postfix) { + return std::string(generate_mux_node_name(node_level, add_buffer_postfix) + "_" + std::to_string(node_index_at_level) + "_"); +} + /************************************************ * Generate the module name for a multiplexer in Verilog format * Different circuit model requires different names: @@ -936,3 +949,24 @@ std::string generate_fpga_top_module_name() { std::string generate_fpga_top_netlist_name(const std::string& postfix) { return std::string("fpga_top" + postfix); } + +/********************************************************************* + * Generate the module name for a constant generator + * either VDD or GND, depending on the input argument + ********************************************************************/ +std::string generate_const_value_module_name(const size_t& const_val) { + if (0 == const_val) { + return std::string("gnd"); + } + + VTR_ASSERT (1 == const_val); + return std::string("vdd"); +} + +/********************************************************************* + * Generate the output port name for a constant generator module + * either VDD or GND, depending on the input argument + ********************************************************************/ +std::string generate_const_value_module_output_port_name(const size_t& const_val) { + return generate_const_value_module_name(const_val); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 00aa66b0d..6ab310f5c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -16,6 +16,10 @@ std::string generate_mux_node_name(const size_t& node_level, const bool& add_buffer_postfix); +std::string generate_mux_branch_instance_name(const size_t& node_level, + const size_t& node_index_at_level, + const bool& add_buffer_postfix); + std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size, @@ -165,4 +169,8 @@ std::string generate_fpga_top_module_name(); std::string generate_fpga_top_netlist_name(const std::string& postfix); +std::string generate_const_value_module_name(const size_t& const_val); + +std::string generate_const_value_module_output_port_name(const size_t& const_val); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 46a9b7d74..3eab7112a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -175,18 +175,51 @@ ModuleId ModuleManager::find_module(const std::string& name) const { /* Find the number of instances of a child module in the parent module */ size_t ModuleManager::num_instance(const ModuleId& parent_module, const ModuleId& child_module) const { - /* validate both module ids */ - VTR_ASSERT(valid_module_id(parent_module)); - VTR_ASSERT(valid_module_id(child_module)); - /* Try to find the child_module in the children list of parent_module*/ - for (size_t i = 0; i < children_[parent_module].size(); ++i) { - if (child_module == children_[parent_module][i]) { - /* Found, return the number of instances */ - return num_child_instances_[parent_module][i]; + size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); + if (size_t(-1) == child_index) { + /* Not found, return a zero */ + return 0; + } + + return num_child_instances_[parent_module][child_index]; +} + +/* Find the instance name of a child module */ +std::string ModuleManager::instance_name(const ModuleId& parent_module, const ModuleId& child_module, + const size_t& instance_id) const { + /* Validate the id of both parent and child modules */ + VTR_ASSERT ( valid_module_id(parent_module) ); + VTR_ASSERT ( valid_module_id(child_module) ); + + /* Find the index of child module in the child list of parent module */ + size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); + VTR_ASSERT (child_index < children_[parent_module].size()); + /* Ensure that instance id is valid */ + VTR_ASSERT (instance_id < num_instance(parent_module, child_module)); + return child_instance_names_[parent_module][child_index][instance_id]; +} + +/* Find the instance id of a given instance name */ +size_t ModuleManager::instance_id(const ModuleId& parent_module, const ModuleId& child_module, + const std::string& instance_name) const { + /* Validate the id of both parent and child modules */ + VTR_ASSERT ( valid_module_id(parent_module) ); + VTR_ASSERT ( valid_module_id(child_module) ); + + /* Find the index of child module in the child list of parent module */ + size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); + VTR_ASSERT (child_index < children_[parent_module].size()); + + /* Search the instance name list and try to find a match */ + for (size_t name_id = 0; name_id < child_instance_names_[parent_module][child_index].size(); ++name_id) { + const std::string& name = child_instance_names_[parent_module][child_index][name_id]; + if (0 == name.compare(instance_name)) { + return name_id; } } - /* Not found, return a zero */ - return 0; + + /* Not found, return an invalid name */ + return size_t(-1); } /* Find if a port is a wire connection */ @@ -309,6 +342,24 @@ vtr::vector ModuleManager::net_sink_pins(const ModuleId return net_sink_pin_ids_[module][net]; } +/****************************************************************************** + * Private Accessors + ******************************************************************************/ +size_t ModuleManager::find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const { + /* validate both module ids */ + VTR_ASSERT(valid_module_id(parent_module)); + VTR_ASSERT(valid_module_id(child_module)); + /* Try to find the child_module in the children list of parent_module*/ + for (size_t i = 0; i < children_[parent_module].size(); ++i) { + if (child_module == children_[parent_module][i]) { + /* Found, return the number of instances */ + return i; + } + } + /* Not found: return an valid value */ + return size_t(-1); +} + /****************************************************************************** * Public Mutators ******************************************************************************/ @@ -329,6 +380,7 @@ ModuleId ModuleManager::add_module(const std::string& name) { parents_.emplace_back(); children_.emplace_back(); num_child_instances_.emplace_back(); + child_instance_names_.emplace_back(); port_ids_.emplace_back(); ports_.emplace_back(); @@ -442,9 +494,13 @@ void ModuleManager::add_child_module(const ModuleId& parent_module, const Module /* Update the child module of parent module */ children_[parent_module].push_back(child_module); num_child_instances_[parent_module].push_back(1); /* By default give one */ + /* Update the instance name list */ + child_instance_names_[parent_module].emplace_back(); + child_instance_names_[parent_module].back().emplace_back(); } else { /* Increase the counter of instances */ num_child_instances_[parent_module][child_it - children_[parent_module].begin()]++; + child_instance_names_[parent_module][child_it - children_[parent_module].begin()].emplace_back(); } /* Update fast look-up for nets */ @@ -456,6 +512,24 @@ void ModuleManager::add_child_module(const ModuleId& parent_module, const Module } } +/* Set the instance name of a child module */ +void ModuleManager::set_child_instance_name(const ModuleId& parent_module, + const ModuleId& child_module, + const size_t& instance_id, + const std::string& instance_name) { + /* Validate the id of both parent and child modules */ + VTR_ASSERT ( valid_module_id(parent_module) ); + VTR_ASSERT ( valid_module_id(child_module) ); + /* Ensure that the instance id is in range */ + VTR_ASSERT ( instance_id < num_instance(parent_module, child_module)); + /* Try to find the child_module in the children list of parent_module*/ + size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); + /* We must find something! */ + VTR_ASSERT(size_t(-1) != child_index); + /* Set the name */ + child_instance_names_[parent_module][child_index][instance_id] = instance_name; +} + /* Add a net to the connection graph of the module */ ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { /* Validate the module id */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 4c1222e0f..5001205ba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -80,6 +80,12 @@ class ModuleManager { ModuleId find_module(const std::string& name) const; /* Find the number of instances of a child module in the parent module */ size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const; + /* Find the instance name of a child module */ + std::string instance_name(const ModuleId& parent_module, const ModuleId& child_module, + const size_t& instance_id) const; + /* Find the instance id of a given instance name */ + size_t instance_id(const ModuleId& parent_module, const ModuleId& child_module, + const std::string& instance_name) const; /* Find if a port is a wire connection */ bool port_is_wire(const ModuleId& module, const ModulePortId& port) const; /* Find if a port is register */ @@ -109,6 +115,8 @@ class ModuleManager { vtr::vector net_sink_ports(const ModuleId& module, const ModuleNetId& net) const; /* Find the sink pin indices of a net */ vtr::vector net_sink_pins(const ModuleId& module, const ModuleNetId& net) const; + private: /* Private accessors */ + size_t find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const; public: /* Public mutators */ /* Add a module */ ModuleId add_module(const std::string& name); @@ -125,6 +133,8 @@ class ModuleManager { void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); /* Add a child module to a parent module */ void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); + /* Set the instance name of a child module */ + void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name); /* Add a net to the connection graph of the module */ ModuleNetId create_module_net(const ModuleId& module); /* Set the name of net */ @@ -153,6 +163,7 @@ class ModuleManager { vtr::vector> parents_; /* Parent modules that include the module */ vtr::vector> children_; /* Child modules that this module contain */ vtr::vector> num_child_instances_; /* Number of children instance in each child module */ + vtr::vector>> child_instance_names_; /* Number of children instance in each child module */ /* Port-level data */ vtr::vector> port_ids_; /* List of ports for each Module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h index bffc2df6a..6f85339bc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h @@ -10,6 +10,7 @@ /* Strong Ids for ModuleManager */ struct module_id_tag; +struct instance_id_tag; /* TODO: use instance id in module_manager */ struct module_port_id_tag; struct module_pin_id_tag; struct module_net_id_tag; @@ -17,6 +18,7 @@ struct module_net_src_id_tag; struct module_net_sink_id_tag; typedef vtr::StrongId ModuleId; +typedef vtr::StrongId InstanceId; typedef vtr::StrongId ModulePortId; typedef vtr::StrongId ModulePinId; typedef vtr::StrongId ModuleNetId; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 006584d36..ccd94a001 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -217,3 +217,33 @@ void build_user_defined_modules(ModuleManager& module_manager, } } +/********************************************************************* + * This function will build a constant generator modules + * and add it to the module manager + * It could be either + * 1. VDD or 2. GND + * Each module will have only one output port + ********************************************************************/ +static +void build_constant_generator_module(ModuleManager& module_manager, + const size_t& const_value) { + ModuleId const_module = module_manager.add_module(generate_const_value_module_name(const_value)); + /* Add one output port */ + BasicPort const_output_port(generate_const_value_module_output_port_name(const_value), 1); + module_manager.add_port(const_module, const_output_port, ModuleManager::MODULE_OUTPUT_PORT); +} + +/********************************************************************* + * This function will add two constant generator modules + * to the module manager + * 1. VDD + * 2. GND + ********************************************************************/ +void build_constant_generator_modules(ModuleManager& module_manager) { + + /* VDD */ + build_constant_generator_module(module_manager, 1); + + /* GND */ + build_constant_generator_module(module_manager, 0); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h index d91c529fc..34200f68b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h @@ -11,4 +11,6 @@ void build_user_defined_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::vector& routing_segments); +void build_constant_generator_modules(ModuleManager& module_manager); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index 39cfdd453..c97f031ba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -12,6 +12,7 @@ #include "build_essential_modules.h" #include "build_decoder_modules.h" +#include "build_mux_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -66,9 +67,13 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, for (int i = 0; i < arch.num_segments; ++i) { L_segment_vec.push_back(arch.Segments[i]); } + + /* Add constant generator modules: VDD and GND */ + build_constant_generator_modules(module_manager); + /* Register all the user-defined modules in the module manager * This should be done prior to other steps in this function, - * because they will be instanciated by other primitive modules + * because they will be instanciated by other primitive modules */ build_user_defined_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); @@ -78,7 +83,8 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, /* Build local encoders for multiplexers, this MUST be called before multiplexer building */ build_mux_local_decoder_modules(module_manager, mux_lib, arch.spice->circuit_lib); - /* TODO: Build multiplexer modules */ + /* Build multiplexer modules */ + build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib); /* TODO: Build LUT modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp new file mode 100644 index 000000000..5385da9ae --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -0,0 +1,1464 @@ +/*********************************************** + * This file includes functions to generate + * Verilog submodules for multiplexers. + * including both fundamental submodules + * such as a branch in a multiplexer + * and the full multiplexer + **********************************************/ +#include +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "mux_graph.h" +#include "module_manager.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "mux_utils.h" +#include "circuit_library_utils.h" +#include "decoder_library_utils.h" +#include "module_manager_utils.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +/* TODO: we should have a header file for naming constexpr only */ +#include "verilog_global.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "build_mux_modules.h" + +/********************************************************************* + * Generate structural Verilog codes (consist of transmission-gates or + * pass-transistor) modeling an branch circuit + * for a multiplexer with the given size + * + * +----------+ + * input[0] --->| tgate[0] |-+ + * +----------+ | + * | + * +----------+ | + * input[1] --->| tgate[1] |-+--->output[0] + * +----------+ | + * | + * ... ... | + * | + * +----------+ | + * input[i] --->| tgate[i] |-+ + * +----------+ + *********************************************************************/ +static +void build_cmos_mux_branch_body(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& tgate_model, + const ModuleId& mux_module, + const ModulePortId& module_input_port, + const ModulePortId& module_output_port, + const ModulePortId& module_mem_port, + const ModulePortId& module_mem_inv_port, + const MuxGraph& mux_graph) { + /* Get the module id of tgate in Module manager */ + ModuleId tgate_module_id = module_manager.find_module(circuit_lib.model_name(tgate_model)); + VTR_ASSERT(ModuleId::INVALID() != tgate_module_id); + + /* Get model ports of tgate */ + std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); + std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(3 == tgate_input_ports.size()); + VTR_ASSERT(1 == tgate_output_ports.size()); + + /* Find the module ports of tgate module */ + /* Input port is the data path input of the tgate, whose size must be 1 ! */ + ModulePortId tgate_module_input = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_input)); + BasicPort tgate_module_input_port = module_manager.module_port(tgate_module_id, tgate_module_input); + VTR_ASSERT(1 == tgate_module_input_port.get_width()); + + /* Mem port is the memory of the tgate, whose size must be 1 ! */ + ModulePortId tgate_module_mem = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_input_ports[1])); + VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem)); + BasicPort tgate_module_mem_port = module_manager.module_port(tgate_module_id, tgate_module_mem); + VTR_ASSERT(1 == tgate_module_mem_port.get_width()); + + /* Mem inv port is the inverted memory of the tgate, whose size must be 1 ! */ + ModulePortId tgate_module_mem_inv = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_input_ports[2])); + VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem_inv)); + BasicPort tgate_module_mem_inv_port = module_manager.module_port(tgate_module_id, tgate_module_mem_inv); + VTR_ASSERT(1 == tgate_module_mem_inv_port.get_width()); + + /* Output port is the data path output of the tgate, whose size must be 1 ! */ + ModulePortId tgate_module_output = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_output)); + BasicPort tgate_module_output_port = module_manager.module_port(tgate_module_id, tgate_module_output); + VTR_ASSERT(1 == tgate_module_output_port.get_width()); + + /* Ensure that input port size does match mux inputs */ + BasicPort input_port = module_manager.module_port(mux_module, module_input_port); + VTR_ASSERT(input_port.get_width() == mux_graph.num_inputs()); + + /* Add module nets for each mux inputs */ + std::vector mux_input_nets; + for (const size_t& pin : input_port.pins()) { + ModuleNetId input_net = module_manager.create_module_net(mux_module); + mux_input_nets.push_back(input_net); + /* Configure the source for each net */ + module_manager.add_module_net_source(mux_module, input_net, mux_module, 0, module_input_port, pin); + } + + /* Ensure that output port size does match mux outputs */ + BasicPort output_port = module_manager.module_port(mux_module, module_output_port); + VTR_ASSERT(output_port.get_width() == mux_graph.num_outputs()); + + /* Add module nets for each mux outputs */ + std::vector mux_output_nets; + for (const size_t& pin : output_port.pins()) { + ModuleNetId output_net = module_manager.create_module_net(mux_module); + mux_output_nets.push_back(output_net); + /* Configure the sink for each net */ + module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port, pin); + } + + /* Ensure that mem port size does match mux outputs */ + BasicPort mem_port = module_manager.module_port(mux_module, module_mem_port); + VTR_ASSERT(mem_port.get_width() == mux_graph.num_memory_bits()); + + /* Add module nets for each mem inputs */ + std::vector mux_mem_nets; + for (const size_t& pin : mem_port.pins()) { + ModuleNetId mem_net = module_manager.create_module_net(mux_module); + mux_mem_nets.push_back(mem_net); + /* Configure the source for each net */ + module_manager.add_module_net_source(mux_module, mem_net, mux_module, 0, module_mem_port, pin); + } + + /* Ensure that mem_inv port size does match mux outputs */ + BasicPort mem_inv_port = module_manager.module_port(mux_module, module_mem_inv_port); + VTR_ASSERT(mem_inv_port.get_width() == mux_graph.num_memory_bits()); + + /* Add module nets for each mem inverted inputs */ + std::vector mux_mem_inv_nets; + for (const size_t& pin : mem_inv_port.pins()) { + ModuleNetId mem_net = module_manager.create_module_net(mux_module); + mux_mem_inv_nets.push_back(mem_net); + /* Configure the source for each net */ + module_manager.add_module_net_source(mux_module, mem_net, mux_module, 0, module_mem_inv_port, pin); + } + + /* Build a module following the connections in mux_graph */ + /* Iterate over the inputs */ + for (const auto& mux_input : mux_graph.inputs()) { + /* Iterate over the outputs */ + for (const auto& mux_output : mux_graph.outputs()) { + /* Add the a tgate to bridge the mux input and output */ + size_t tgate_instance = module_manager.num_instance(mux_module, tgate_module_id); + module_manager.add_child_module(mux_module, tgate_module_id); + + /* Add module nets to connect the mux input and tgate input */ + module_manager.add_module_net_sink(mux_module, mux_input_nets[size_t(mux_graph.input_id(mux_input))], tgate_module_id, tgate_instance, tgate_module_input, tgate_module_input_port.get_lsb()); + + /* if there is a connection between the input and output, a tgate will be outputted */ + std::vector edges = mux_graph.find_edges(mux_input, mux_output); + /* There should be only one edge or no edge*/ + VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); + /* No need to output tgates if there are no edges between two nodes */ + if (0 == edges.size()) { + continue; + } + + /* Add module nets to connect the mux output and tgate output */ + module_manager.add_module_net_source(mux_module, mux_output_nets[size_t(mux_graph.output_id(mux_output))], tgate_module_id, tgate_instance, tgate_module_output, tgate_module_output_port.get_lsb()); + + MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); + /* Add module nets to connect the mem input and tgate mem input */ + if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { + /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ + module_manager.add_module_net_sink(mux_module, mux_mem_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem, tgate_module_mem_port.get_lsb()); + module_manager.add_module_net_sink(mux_module, mux_mem_inv_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem_inv, tgate_module_mem_inv_port.get_lsb()); + } else { + /* wire mem_inv to mem of module, wire mem to mem_inv of module */ + module_manager.add_module_net_sink(mux_module, mux_mem_inv_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem, tgate_module_mem_port.get_lsb()); + module_manager.add_module_net_sink(mux_module, mux_mem_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem_inv, tgate_module_mem_inv_port.get_lsb()); + } + } + } +} + +/********************************************************************* + * Generate Verilog codes modeling an branch circuit + * for a CMOS multiplexer with the given size + * Support structural and behavioral Verilog codes + *********************************************************************/ +static +void build_cmos_mux_branch_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const std::string& module_name, + const MuxGraph& mux_graph) { + /* Get the tgate model */ + CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model); + + /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ + if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); + return; + } + + std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true, true); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of inputs */ + size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == num_outputs); + /* MUX graph must have only 1 level*/ + VTR_ASSERT(1 == mux_graph.num_levels()); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId mux_module = module_manager.add_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + /* Add module ports */ + /* Add each input port */ + BasicPort input_port("in", num_inputs); + ModulePortId module_input_port = module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Add each output port */ + BasicPort output_port("out", num_outputs); + ModulePortId module_output_port = module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Add each memory port */ + BasicPort mem_port("mem", num_mems); + ModulePortId module_mem_port = module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port("mem_inv", num_mems); + ModulePortId module_mem_inv_port = module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + + /* By default we give a structural description, + * Writers can freely write the module in their styles + * For instance, Verilog writer can ignore the internal structure and write in behavioral codes + */ + build_cmos_mux_branch_body(module_manager, circuit_lib, tgate_model, mux_module, module_input_port, module_output_port, module_mem_port, module_mem_inv_port, mux_graph); + + /* Add global ports to the mux module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, mux_module); +} + +/********************************************************************* + * Generate Verilog codes modeling an branch circuit + * for a RRAM-based multiplexer with the given size + * Support structural and behavioral Verilog codes + *********************************************************************/ +static +void build_rram_mux_branch_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const std::string& module_name, + const MuxGraph& mux_graph) { + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the BL and WL ports from the mux */ + std::vector mux_blb_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_BLB, true); + std::vector mux_wl_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_WL, true); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of inputs */ + size_t num_inputs = mux_graph.num_inputs(); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == num_outputs); + /* MUX graph must have only 1 level*/ + VTR_ASSERT(1 == mux_graph.num_levels()); + /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ + VTR_ASSERT(1 == mux_input_ports.size()); + VTR_ASSERT(1 == mux_output_ports.size()); + VTR_ASSERT(1 == mux_blb_ports.size()); + VTR_ASSERT(1 == mux_wl_ports.size()); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId mux_module = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != mux_module); + + /* Add module ports */ + /* Add each global programming enable/disable ports */ + std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true, true); + for (const auto& port : prog_enable_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(mux_module, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + + /* Add each input port */ + BasicPort input_port(circuit_lib.port_lib_name(mux_input_ports[0]), num_inputs); + module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); + + /* Add each output port */ + BasicPort output_port(circuit_lib.port_lib_name(mux_output_ports[0]), num_outputs); + module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + + /* Add RRAM programming ports, + * RRAM MUXes require one more pair of BLB and WL + * to configure the memories. See schematic for details + */ + BasicPort blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), num_mems + 1); + module_manager.add_port(mux_module, blb_port, ModuleManager::MODULE_INPUT_PORT); + + BasicPort wl_port(circuit_lib.port_lib_name(mux_wl_ports[0]), num_mems + 1); + module_manager.add_port(mux_module, wl_port, ModuleManager::MODULE_INPUT_PORT); + + /* Note: we do not generate the internal structure of the ReRAM-based MUX + * circuit as a module graph! + * This is mainly due to that the internal structure could be different + * in Verilog or SPICE netlists + * Leave the writers to customize this + */ +} + +/*********************************************** + * Generate Verilog codes modeling an branch circuit + * for a multiplexer with the given size + **********************************************/ +static +void build_mux_branch_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size, + const MuxGraph& mux_graph) { + std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); + + /* Multiplexers built with different technology is in different organization */ + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + build_cmos_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph); + break; + case SPICE_MODEL_DESIGN_RRAM: + build_rram_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + exit(1); + } +} + +/******************************************************************** + * Generate the standard-cell-based internal logic (multiplexing structure) + * for a multiplexer or LUT in Verilog codes + * This function will : + * 1. build a multiplexing structure by instanciating standard cells MUX2 + * 2. add intermediate buffers between multiplexing stages if specified. + *******************************************************************/ +static +void build_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const ModuleId& mux_module, + const CircuitModelId& mux_model, + const CircuitModelId& std_cell_model, + const vtr::vector& mux_module_input_nets, + const vtr::vector& mux_module_output_nets, + const vtr::vector& mux_module_mem_nets, + const MuxGraph& mux_graph) { + /* Get the regular (non-mode-select) sram ports from the mux */ + std::vector mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); + VTR_ASSERT(1 == mux_regular_sram_ports.size()); + + /* Find the input ports and output ports of the standard cell */ + std::vector std_cell_input_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_INPUT, true); + std::vector std_cell_output_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Quick check the requirements on port map */ + VTR_ASSERT(3 == std_cell_input_ports.size()); + VTR_ASSERT(1 == std_cell_output_ports.size()); + + /* Find module information of the standard cell MUX2 */ + std::string std_cell_module_name = circuit_lib.model_name(std_cell_model); + /* Get the moduleId for the submodule */ + ModuleId std_cell_module_id = module_manager.find_module(std_cell_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != std_cell_module_id); + + /* Find the module ports of the standard cell MUX2 module */ + std::vector std_cell_module_inputs; + std::vector std_cell_module_input_ports; + /* Input 0 port is the first data path input of the tgate, whose size must be 1 ! */ + for (size_t port_id = 0; port_id < 2; ++port_id) { + std_cell_module_inputs.push_back(module_manager.find_module_port(std_cell_module_id, circuit_lib.port_lib_name(std_cell_input_ports[port_id]))); + VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_inputs[port_id])); + std_cell_module_input_ports.push_back(module_manager.module_port(std_cell_module_id, std_cell_module_inputs[port_id])); + VTR_ASSERT(1 == std_cell_module_input_ports[port_id].get_width()); + } + + /* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */ + ModulePortId std_cell_module_mem = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_lib_name(std_cell_input_ports[2])); + VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_mem)); + BasicPort std_cell_module_mem_port = module_manager.module_port(std_cell_module_id, std_cell_module_mem); + VTR_ASSERT(1 == std_cell_module_mem_port.get_width()); + + /* Output port is the data path output of the standard cell MUX2, whose size must be 1 ! */ + ModulePortId std_cell_module_output = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_lib_name(std_cell_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_output)); + BasicPort std_cell_module_output_port = module_manager.module_port(std_cell_module_id, std_cell_module_output); + VTR_ASSERT(1 == std_cell_module_output_port.get_width()); + + /* Cache Net ids for each level of the multiplexer */ + std::vector> module_nets_by_level; + module_nets_by_level.resize(mux_graph.num_node_levels()); + for (size_t level = 0; level < mux_graph.num_node_levels(); ++level) { + /* Print the internal wires located at this level */ + module_nets_by_level[level].resize(mux_graph.num_nodes_at_level(level)); + } + + /* Build the location map of intermediate buffers */ + std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, mux_model, mux_graph.num_node_levels()); + + /* Add all the branch modules and intermediate buffers */ + for (const auto& node : mux_graph.non_input_nodes()) { + /* Get the size of branch circuit + * Instanciate an branch circuit by the size (fan-in) of the node + */ + size_t branch_size = mux_graph.node_in_edges(node).size(); + /* To match the standard cell MUX2: We should have only 2 input_nodes */ + VTR_ASSERT(2 == branch_size); + + /* Find the instance id */ + size_t std_cell_instance_id = module_manager.num_instance(mux_module, std_cell_module_id); + /* Add the module to mux_module */ + module_manager.add_child_module(mux_module, std_cell_module_id); + + /* Get the node level and index in the current level */ + size_t output_node_level = mux_graph.node_level(node); + size_t output_node_index_at_level = mux_graph.node_index_at_level(node); + /* Set a name for the instance */ + std::string std_cell_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, false); + module_manager.set_child_instance_name(mux_module, std_cell_module_id, std_cell_instance_id, std_cell_instance_name); + + /* Add module nets to wire to next stage modules */ + ModuleNetId branch_net; + if (true == mux_graph.is_node_output(node)) { + /* This is an output node, we should use existing output nets */ + MuxOutputId output_id = mux_graph.output_id(node); + branch_net = mux_module_output_nets[output_id]; + } else { + VTR_ASSERT(false == mux_graph.is_node_output(node)); + branch_net = module_manager.create_module_net(mux_module); + } + module_manager.add_module_net_source(mux_module, branch_net, std_cell_module_id, std_cell_instance_id, std_cell_module_output, std_cell_module_output_port.get_lsb()); + + /* Record the module net id in the cache */ + module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net; + + /* Wire the branch module memory ports to the nets of MUX memory ports */ + /* Get the mems in the branch circuits */ + std::vector mems; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the mem control the edge */ + MuxMemId mem = mux_graph.find_edge_mem(edge); + /* Add the mem if it is not in the list */ + if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { + mems.push_back(mem); + } + } + /* Connect mem to mem net one by one + * Note that standard cell MUX2 only needs mem but NOT mem_inv + */ + for (const MuxMemId& mem : mems) { + module_manager.add_module_net_sink(mux_module, mux_module_mem_nets[mem], std_cell_module_id, std_cell_instance_id, std_cell_module_mem, std_cell_module_mem_port.get_lsb()); + } + + /* Wire the branch module inputs to the nets in previous stage */ + /* Get the nodes which drive the root_node */ + std::vector input_nodes; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the nodes drive the edge */ + for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { + input_nodes.push_back(src_node); + } + } + /* Number of inputs should match the branch_input_size!!! */ + VTR_ASSERT(input_nodes.size() == branch_size); + /* To match the standard cell MUX2: We should have only 2 input_nodes */ + VTR_ASSERT(2 == input_nodes.size()); + /* build the link between input_node[0] and std_cell_input_port[0] + * build the link between input_node[1] and std_cell_input_port[1] + */ + for (size_t node_id = 0; node_id < input_nodes.size(); ++node_id) { + /* Find the port info of each input node */ + size_t input_node_level = mux_graph.node_level(input_nodes[node_id]); + size_t input_node_index_at_level = mux_graph.node_index_at_level(input_nodes[node_id]); + /* For inputs of mux, the net id is reserved */ + if (true == mux_graph.is_node_input(input_nodes[node_id])) { + /* Get node input id */ + MuxInputId input_id = mux_graph.input_id(input_nodes[node_id]); + module_manager.add_module_net_sink(mux_module, mux_module_input_nets[input_id], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb()); + } else { + VTR_ASSERT (false == mux_graph.is_node_input(input_nodes[node_id])); + /* Find the input port of standard cell */ + module_manager.add_module_net_sink(mux_module, module_nets_by_level[input_node_level][input_node_index_at_level], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb()); + } + } + + /* Identify if an intermediate buffer is needed */ + if (false == inter_buffer_location_map[output_node_level]) { + continue; + } + /* Add an intermediate buffer to mux_module if needed */ + if (true == mux_graph.is_node_output(node)) { + /* Output node does not need buffer addition here, it is handled outside this function */ + continue; + } + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(mux_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Find the instance id */ + size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); + /* Add the module to mux_module */ + module_manager.add_child_module(mux_module, buffer_module_id); + /* Set a name for the instance */ + std::string buffer_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, true); + module_manager.set_child_instance_name(mux_module, buffer_module_id, buffer_instance_id, buffer_instance_name); + + /* Add module nets to wire to the buffer module */ + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Find the input and output module ports */ + ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); + ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); + + /* Port size should be 1 ! */ + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); + + /* Connect the module net from branch output to buffer input */ + module_manager.add_module_net_sink(mux_module, branch_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); + + /* Create a module net which sources from buffer output */ + ModuleNetId buffer_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + + /* Record the module net id in the cache */ + module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net; + } +} + +/******************************************************************** + * Generate the pass-transistor/transmission-gate -based internal logic + * (multiplexing structure) for a multiplexer or LUT in Verilog codes + * This function will : + * 1. build a multiplexing structure by instanciating the branch circuits + * generated before + * 2. add intermediate buffers between multiplexing stages if specified. + *******************************************************************/ +static +void build_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const ModuleId& mux_module, + const CircuitModelId& circuit_model, + const vtr::vector& mux_module_input_nets, + const vtr::vector& mux_module_output_nets, + const vtr::vector& mux_module_mem_nets, + const vtr::vector& mux_module_mem_inv_nets, + const MuxGraph& mux_graph) { + /* Find the actual mux size */ + size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); + + /* Get the regular (non-mode-select) sram ports from the mux */ + std::vector mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model); + VTR_ASSERT(1 == mux_regular_sram_ports.size()); + + /* Cache Net ids for each level of the multiplexer */ + std::vector> module_nets_by_level; + module_nets_by_level.resize(mux_graph.num_node_levels()); + for (size_t level = 0; level < mux_graph.num_node_levels(); ++level) { + /* Print the internal wires located at this level */ + module_nets_by_level[level].resize(mux_graph.num_nodes_at_level(level)); + } + + /* Build the location map of intermediate buffers */ + std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); + + /* Add all the branch modules and intermediate buffers */ + for (const auto& node : mux_graph.non_input_nodes()) { + /* Get the size of branch circuit + * Instanciate an branch circuit by the size (fan-in) of the node + */ + size_t branch_size = mux_graph.node_in_edges(node).size(); + + /* Instanciate the branch module which is a tgate-based module + */ + std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); + /* Get the moduleId for the submodule */ + ModuleId branch_module_id = module_manager.find_module(branch_module_name); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != branch_module_id); + + /* Find the instance id */ + size_t branch_instance_id = module_manager.num_instance(mux_module, branch_module_id); + /* Add the module to mux_module */ + module_manager.add_child_module(mux_module, branch_module_id); + + /* Get the node level and index in the current level */ + size_t output_node_level = mux_graph.node_level(node); + size_t output_node_index_at_level = mux_graph.node_index_at_level(node); + /* Set a name for the instance */ + std::string branch_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, false); + module_manager.set_child_instance_name(mux_module, branch_module_id, branch_instance_id, branch_instance_name); + + /* Get the output port id of branch module */ + ModulePortId branch_module_output_port_id = module_manager.find_module_port(branch_module_id, std::string("out")); + BasicPort branch_module_output_port = module_manager.module_port(branch_module_id, branch_module_output_port_id); + + /* Add module nets to wire to next stage modules */ + ModuleNetId branch_net; + if (true == mux_graph.is_node_output(node)) { + /* This is an output node, we should use existing output nets */ + MuxOutputId output_id = mux_graph.output_id(node); + branch_net = mux_module_output_nets[output_id]; + } else { + VTR_ASSERT(false == mux_graph.is_node_output(node)); + branch_net = module_manager.create_module_net(mux_module); + } + module_manager.add_module_net_source(mux_module, branch_net, branch_module_id, branch_instance_id, branch_module_output_port_id, branch_module_output_port.get_lsb()); + + /* Record the module net id in the cache */ + module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net; + + /* Wire the branch module memory ports to the nets of MUX memory ports */ + /* Get the mems in the branch circuits */ + std::vector mems; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the mem control the edge */ + MuxMemId mem = mux_graph.find_edge_mem(edge); + /* Add the mem if it is not in the list */ + if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { + mems.push_back(mem); + } + } + + /* Get mem/mem_inv ports of branch module */ + ModulePortId branch_module_mem_port_id = module_manager.find_module_port(branch_module_id, std::string("mem")); + BasicPort branch_module_mem_port = module_manager.module_port(branch_module_id, branch_module_mem_port_id); + ModulePortId branch_module_mem_inv_port_id = module_manager.find_module_port(branch_module_id, std::string("mem_inv")); + BasicPort branch_module_mem_inv_port = module_manager.module_port(branch_module_id, branch_module_mem_inv_port_id); + + /* Note that we do NOT care inverted edge-to-mem connection. + * It is handled in branch module generation!!! + */ + /* Connect mem/mem_inv to mem/mem_inv net one by one */ + for (size_t mem_id = 0; mem_id < mems.size(); ++mem_id) { + module_manager.add_module_net_sink(mux_module, mux_module_mem_nets[mems[mem_id]], branch_module_id, branch_instance_id, branch_module_mem_port_id, branch_module_mem_port.pins()[mem_id]); + module_manager.add_module_net_sink(mux_module, mux_module_mem_inv_nets[mems[mem_id]], branch_module_id, branch_instance_id, branch_module_mem_inv_port_id, branch_module_mem_inv_port.pins()[mem_id]); + } + + /* Wire the branch module inputs to the nets in previous stage */ + /* Get the input port id of branch module */ + ModulePortId branch_module_input_port_id = module_manager.find_module_port(branch_module_id, std::string("in")); + BasicPort branch_module_input_port = module_manager.module_port(branch_module_id, branch_module_input_port_id); + + /* Get the nodes which drive the root_node */ + std::vector input_nodes; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the nodes drive the edge */ + for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { + input_nodes.push_back(src_node); + } + } + /* Number of inputs should match the branch_input_size!!! */ + VTR_ASSERT(input_nodes.size() == branch_size); + /* build the link between input_node and branch circuit input_port[0] + */ + for (size_t node_id = 0; node_id < input_nodes.size(); ++node_id) { + /* Find the port info of each input node */ + size_t input_node_level = mux_graph.node_level(input_nodes[node_id]); + size_t input_node_index_at_level = mux_graph.node_index_at_level(input_nodes[node_id]); + /* For inputs of mux, the net id is reserved */ + if (true == mux_graph.is_node_input(input_nodes[node_id])) { + /* Get node input id */ + MuxInputId input_id = mux_graph.input_id(input_nodes[node_id]); + module_manager.add_module_net_sink(mux_module, mux_module_input_nets[input_id], branch_module_id, branch_instance_id, branch_module_input_port_id, branch_module_input_port.pins()[node_id]); + } else { + VTR_ASSERT (false == mux_graph.is_node_input(input_nodes[node_id])); + module_manager.add_module_net_sink(mux_module, module_nets_by_level[input_node_level][input_node_index_at_level], branch_module_id, branch_instance_id, branch_module_input_port_id, branch_module_input_port.pins()[node_id]); + } + } + + /* Identify if an intermediate buffer is needed */ + if (false == inter_buffer_location_map[output_node_level]) { + continue; + } + /* Add an intermediate buffer to mux_module if needed */ + if (true == mux_graph.is_node_output(node)) { + /* Output node does not need buffer addition here, it is handled outside this function */ + continue; + } + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Find the instance id */ + size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); + /* Add the module to mux_module */ + module_manager.add_child_module(mux_module, buffer_module_id); + /* Set a name for the instance */ + std::string buffer_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, true); + module_manager.set_child_instance_name(mux_module, buffer_module_id, buffer_instance_id, buffer_instance_name); + + /* Add module nets to wire to the buffer module */ + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Find the input and output module ports */ + ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); + ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); + + /* Port size should be 1 ! */ + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); + + /* Connect the module net from branch output to buffer input */ + module_manager.add_module_net_sink(mux_module, branch_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); + + /* Create a module net which sources from buffer output */ + ModuleNetId buffer_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + + /* Record the module net id in the cache */ + module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net; + } +} + +/********************************************************************* + * This function will add nets and input buffers (if needed) + * to a mux module + * Module net represents the connections when there are no input buffers + * mux_input_net[0] + * | + * v +------------ + * mux_in[0] ----------->| + * | + * | + * | + * | Multiplexing + * mux_input_net[i] | Structure + * | | + * v | + * mux_in[0] ----------->| + * | + * + * + * Module net represents the connections when there are input buffers + * mux_input_net[0] + * | + * +-----------------+ v +------------ + * mux_in[0] ----->| input_buffer[0] |-----> | + * +-----------------+ | + * | + * ... | + * | Multiplexing + * mux_input_net[i] | Structure + * | | + * +-----------------+ v | + * mux_in[0] ----->| input_buffer[0] |-----> | + * +-----------------+ | + *********************************************************************/ +static +vtr::vector build_mux_module_input_buffers(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const ModuleId& mux_module, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + vtr::vector mux_input_nets(mux_graph.num_inputs(), ModuleNetId::INVALID()); + + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + /* We should have only 1 input port! */ + VTR_ASSERT(1 == mux_input_ports.size()); + + /* Get the input port from MUX module */ + ModulePortId module_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_input_ports[0])); + VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); + /* Get the port from module */ + BasicPort module_input_port = module_manager.module_port(mux_module, module_input_port_id); + + /* Iterate over all the inputs in the MUX graph */ + for (const auto& input_node : mux_graph.inputs()) { + /* Fetch fundamental information from MUX graph w.r.t. the input node */ + MuxInputId input_index = mux_graph.input_id(input_node); + VTR_ASSERT(MuxInputId::INVALID() != input_index); + + /* For last input: + * Add a constant value to the last input, if this MUX needs a constant input + */ + if ( (MuxInputId(mux_graph.num_inputs() - 1) == mux_graph.input_id(input_node)) + && (true == circuit_lib.mux_add_const_input(mux_model)) ) { + /* Get the constant input value */ + size_t const_value = circuit_lib.mux_const_input_value(mux_model); + VTR_ASSERT( (0 == const_value) || (1 == const_value) ); + /* Instanciate a VDD module (default module) + * and build a net between VDD and the MUX input + */ + /* Get the moduleId for the buffer module */ + ModuleId const_val_module_id = module_manager.find_module(generate_const_value_module_name(const_value)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != const_val_module_id); + size_t const_val_instance = module_manager.num_instance(mux_module, const_val_module_id); + module_manager.add_child_module(mux_module, const_val_module_id); + ModulePortId const_port_id = module_manager.find_module_port(const_val_module_id, generate_const_value_module_output_port_name(const_value)); + + ModuleNetId input_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, input_net, const_val_module_id, const_val_instance, const_port_id, 0); + mux_input_nets[input_index] = input_net; + continue; + } + + /* When we do not need any buffer, create a net for the input directly */ + if (false == circuit_lib.is_input_buffered(mux_model)) { + ModuleNetId input_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, input_net, mux_module, 0, module_input_port_id, size_t(input_index)); + mux_input_nets[input_index] = input_net; + continue; + } + + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.input_buffer_model(mux_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Find the instance id */ + size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); + /* Add the module to mux_module */ + module_manager.add_child_module(mux_module, buffer_module_id); + + /* Add module nets to wire to the buffer module */ + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Find the input and output module ports */ + ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); + ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); + + /* Port size should be 1 ! */ + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); + + /* Connect the module net from branch output to buffer input */ + ModuleNetId buffer_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, buffer_net, mux_module, 0, module_input_port_id, size_t(input_index)); + module_manager.add_module_net_sink(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); + + /* Create a module net which sources from buffer output */ + ModuleNetId input_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, input_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + mux_input_nets[input_index] = input_net; + } + + return mux_input_nets; +} + +/********************************************************************* + * This function will add nets and input buffers (if needed) + * to a mux module + * Module net represents the connections when there are no output buffers + * + * mux_output_net[0] + * ------------+ | + * | v + * |--------> mux_output[0] + * | + * | + * Multiplexer | ... + * Strcuture | + * |--------> mux_output[i] + * | ^ + * | | + * ------------+ mux_output_net[i] + * + * Module net represents the connections when there are output buffers + * + * mux_output_net[0] + * ------------+ | + * | | + * | v +------------------+ + * |------->| output_buffer[0] |------> mux_output[0] + * | +------------------+ + * | + * Multiplexer | ... + * Strcuture | + * | +------------------+ + * |------->| output_buffer[i] |------> mux_output[i] + * | ^ +------------------+ + * | | + * | | + * ------------+ mux_output_net[i] + + * + *********************************************************************/ +static +vtr::vector build_mux_module_output_buffers(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const ModuleId& mux_module, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + + /* Create module nets for output ports */ + vtr::vector mux_output_nets(mux_graph.num_outputs(), ModuleNetId::INVALID()); + + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Iterate over all the outputs in the MUX module */ + for (const auto& output_port : mux_output_ports) { + /* Get the output port from MUX module */ + ModulePortId module_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(output_port)); + VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); + /* Get the port from module */ + BasicPort module_output_port = module_manager.module_port(mux_module, module_output_port_id); + + /* Iterate over each pin of the output port */ + for (const size_t& pin : circuit_lib.pins(output_port)) { + /* Fetch fundamental information from MUX graph w.r.t. the input node */ + /* Deposite the last level of the graph, which is a default value */ + size_t output_node_level = mux_graph.num_node_levels() - 1; + /* If there is a fracturable level specified for the output, we find the exact level */ + if (size_t(-1) != circuit_lib.port_lut_frac_level(output_port)) { + output_node_level = circuit_lib.port_lut_frac_level(output_port); + } + /* Deposite a zero, which is a default value */ + size_t output_node_index_at_level = 0; + /* If there are output masks, we find the node_index */ + if (!circuit_lib.port_lut_output_masks(output_port).empty()) { + output_node_index_at_level = circuit_lib.port_lut_output_masks(output_port).at(pin); + } + /* Double check the node exists in the Mux Graph */ + MuxNodeId node_id = mux_graph.node_id(output_node_level, output_node_index_at_level); + VTR_ASSERT(MuxNodeId::INVALID() != node_id); + MuxOutputId output_index = mux_graph.output_id(node_id); + + /* Create the port information of the module output at the given pin range, which is the output of buffer instance */ + BasicPort instance_output_port(module_output_port.get_name(), pin, pin); + + /* If the output is not supposed to be buffered, create a net for the input directly */ + if (false == circuit_lib.is_output_buffered(mux_model)) { + ModuleNetId output_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin); + mux_output_nets[output_index] = output_net; + continue; /* Finish here */ + } + + /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */ + /* Now we need to add intermediate buffers by instanciating the modules */ + CircuitModelId buffer_model = circuit_lib.output_buffer_model(mux_model); + /* We must have a valid model id */ + VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); + /* Get the moduleId for the buffer module */ + ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); + /* We must have one */ + VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); + + /* Find the instance id */ + size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); + /* Add the module to mux_module */ + module_manager.add_child_module(mux_module, buffer_module_id); + + /* Add module nets to wire to the buffer module */ + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); + std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == buffer_model_input_ports.size()); + VTR_ASSERT(1 == buffer_model_output_ports.size()); + + /* Find the input and output module ports */ + ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); + ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); + + /* Port size should be 1 ! */ + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); + VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); + + /* Connect the module net from buffer output to MUX output */ + ModuleNetId buffer_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + module_manager.add_module_net_sink(mux_module, buffer_net, mux_module, 0, module_output_port_id, pin); + + /* Create a module net which sinks at buffer input */ + ModuleNetId output_net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_sink(mux_module, output_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); + mux_output_nets[output_index] = output_net; + } + } + + return mux_output_nets; +} + +/********************************************************************* + * Generate module of a CMOS multiplexer with the given size + * The module will consist of three parts: + * 1. instances of the branch circuits of multiplexers which are generated before + * This builds up the multiplexing structure + * 2. Input buffers/inverters + * 3. Output buffers/inverters + *********************************************************************/ +static +void build_cmos_mux_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const std::string& module_name, + const MuxGraph& mux_graph) { + /* Get the global ports required by MUX (and any submodules) */ + std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true, true); + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the sram ports from the mux + * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules + * Here we just bypass it. + */ + std::vector mux_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of data-path inputs */ + size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* The size of of memory ports depend on + * if a local encoder is used for the mux or not + * Multiplexer local encoders are applied to memory bits at each stage + */ + if (true == circuit_lib.mux_use_local_encoder(mux_model)) { + num_mems = 0; + for (const auto& lvl : mux_graph.levels()) { + size_t data_size = mux_graph.num_memory_bits_at_level(lvl); + num_mems += find_mux_local_decoder_addr_size(data_size); + } + } + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 output */ + VTR_ASSERT(1 == mux_input_ports.size()); + /* A quick check on the model ports */ + if ((SPICE_MODEL_MUX == circuit_lib.model_type(mux_model)) + || ((SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) + && (false == circuit_lib.is_lut_fracturable(mux_model))) ) { + VTR_ASSERT(1 == mux_output_ports.size()); + VTR_ASSERT(1 == circuit_lib.port_size(mux_output_ports[0])); + } else { + VTR_ASSERT_SAFE( (SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) + && (true == circuit_lib.is_lut_fracturable(mux_model)) ); + for (const auto& port : mux_output_ports) { + VTR_ASSERT(0 < circuit_lib.port_size(port)); + } + } + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId mux_module = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != mux_module); + /* Add module ports */ + /* Add each input port + * Treat MUX and LUT differently + * 1. MUXes: we do not have a specific input/output sizes, it is inferred by architecture + * 2. LUTes: we do have specific input/output sizes, + * but the inputs of MUXes are the SRAM ports of LUTs + * and the SRAM ports of MUXes are the inputs of LUTs + */ + size_t input_port_cnt = 0; + for (const auto& port : mux_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Update counter */ + input_port_cnt++; + } + /* Double check: We should have only 1 input port generated here! */ + VTR_ASSERT(1 == input_port_cnt); + + /* Add input buffers and update module nets for inputs */ + vtr::vector mux_input_nets = build_mux_module_input_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph); + + for (const auto& port : mux_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + if (SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) { + output_port.set_width(circuit_lib.port_size(port)); + } + module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* TODO: Add output buffers and update module nets for outputs */ + vtr::vector mux_output_nets = build_mux_module_output_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph); + + size_t sram_port_cnt = 0; + for (const auto& port : mux_sram_ports) { + BasicPort mem_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), num_mems); + module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + /* Update counter */ + sram_port_cnt++; + } + VTR_ASSERT(1 == sram_port_cnt); + + /* Create module nets for mem and mem_inv ports */ + vtr::vector mux_mem_nets; + vtr::vector mux_mem_inv_nets; + /* Create nets here, and we will configure the net source later */ + for (size_t mem = 0; mem < mux_graph.num_memory_bits(); ++mem) { + ModuleNetId mem_net = module_manager.create_module_net(mux_module); + mux_mem_nets.push_back(mem_net); + ModuleNetId mem_inv_net = module_manager.create_module_net(mux_module); + mux_mem_inv_nets.push_back(mem_inv_net); + } + + if (false == circuit_lib.mux_use_local_encoder(mux_model)) { + /* Add mem and mem_inv nets here */ + size_t mem_net_cnt = 0; + for (const auto& port : mux_sram_ports) { + ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(port)); + BasicPort mem_port = module_manager.module_port(mux_module, mem_port_id); + for (const size_t& pin : mem_port.pins()) { + MuxMemId mem_id = MuxMemId(mem_net_cnt); + /* Set the module net source */ + module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mem_port_id, pin); + /* Update counter */ + mem_net_cnt++; + } + } + VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); + + /* Add mem and mem_inv nets here */ + size_t mem_inv_net_cnt = 0; + for (const auto& port : mux_sram_ports) { + ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_lib_name(port) + "_inv")); + BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id); + for (const size_t& pin : mem_inv_port.pins()) { + MuxMemId mem_id = MuxMemId(mem_inv_net_cnt); + /* Set the module net source */ + module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_id], mux_module, 0, mem_inv_port_id, pin); + /* Update counter */ + mem_inv_net_cnt++; + } + } + VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); + } else { + /* Add local decoder instance here */ + VTR_ASSERT(true == circuit_lib.mux_use_local_encoder(mux_model)); + BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits()); + BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); + + /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ + ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0])); + BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); + BasicPort lvl_data_port(decoder_data_port.get_name(), 0); + BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); + + /* Counter for mem index */ + size_t mem_net_cnt = 0; + size_t mem_inv_net_cnt = 0; + + for (const auto& lvl : mux_graph.levels()) { + size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); + size_t data_size = mux_graph.num_memory_bits_at_level(lvl); + /* Update the LSB and MSB of addr and data port for the current level */ + lvl_addr_port.rotate(addr_size); + lvl_data_port.rotate(data_size); + lvl_data_inv_port.rotate(data_size); + + std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); + ModuleId decoder_module = module_manager.find_module(decoder_module_name); + VTR_ASSERT(ModuleId::INVALID() != decoder_module); + + size_t decoder_instance = module_manager.num_instance(mux_module, decoder_module); + module_manager.add_child_module(mux_module, decoder_module); + + /* Add module nets to connect sram ports of MUX to address port */ + ModulePortId decoder_module_addr_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_addr_port_name()); + BasicPort decoder_module_addr_port = module_manager.module_port(decoder_module, decoder_module_addr_port_id); + VTR_ASSERT(decoder_module_addr_port.get_width() == lvl_addr_port.get_width()); + + /* Build pin-to-pin net connection */ + for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, net, mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]); + module_manager.add_module_net_sink(mux_module, net, decoder_module, decoder_instance, decoder_module_addr_port_id, decoder_module_addr_port.pins()[pin_id]); + } + + /* Add module nets to connect data port to MUX mem ports */ + ModulePortId decoder_module_data_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_port_name()); + BasicPort decoder_module_data_port = module_manager.module_port(decoder_module, decoder_module_data_port_id); + + /* Build pin-to-pin net connection */ + for (const size_t& pin : decoder_module_data_port.pins()) { + ModuleNetId net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_port_id, pin); + module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_port.get_name() + "_" + std::to_string(pin) + "_")); + /* Add the module nets to mux_mem_nets cache */ + mux_mem_nets[MuxMemId(mem_net_cnt)] = net; + mem_net_cnt++; + } + + ModulePortId decoder_module_data_inv_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_inv_port_name()); + BasicPort decoder_module_data_inv_port = module_manager.module_port(decoder_module, decoder_module_data_inv_port_id); + + /* Build pin-to-pin net connection */ + for (const size_t& pin : decoder_module_data_inv_port.pins()) { + ModuleNetId net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_inv_port_id, pin); + module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_inv_port.get_name() + "_" + std::to_string(pin) + "_")); + /* Add the module nets to mux_mem_inv_nets cache */ + mux_mem_inv_nets[MuxMemId(mem_inv_net_cnt)] = net; + mem_inv_net_cnt++; + } + } + VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); + VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); + } + + /* Print the internal logic in Verilog codes */ + /* Print the Multiplexing structure in Verilog codes + * Separated generation strategy on using standard cell MUX2 or TGATE, + * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input + * 2. Branch TGATE-based module has a fixed port name + * TODO: the naming could be more flexible? + */ + /* Get the tgate model */ + CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model); + /* Instanciate the branch module: + * Case 1: the branch module is a standard cell MUX2 + * Case 2: the branch module is a tgate-based module + */ + std::string branch_module_name; + if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); + build_cmos_mux_module_mux2_multiplexing_structure(module_manager, circuit_lib, mux_module, mux_model, tgate_model, mux_input_nets, mux_output_nets, mux_mem_nets, mux_graph); + } else { + VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_lib.model_type(tgate_model)); + build_cmos_mux_module_tgate_multiplexing_structure(module_manager, circuit_lib, mux_module, mux_model, mux_input_nets, mux_output_nets, mux_mem_nets, mux_mem_inv_nets, mux_graph); + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, mux_module); +} + +/********************************************************************* + * Generate a module of a RRAM-based multiplexer with the given size + * The module will consist of three parts: + * 1. instances of the branch circuits of multiplexers which are generated before + * This builds up the 4T1R-based multiplexing structure + * + * BLB WL + * | | ... + * v v + * +--------+ + * in[0]-->| | BLB WL + * ...| Branch |-----+ | | + * in -->| 0 | | v v + * [N-1] +--------+ | +--------+ + * ... -->| | + * BLBs WLs ...| Branch | + * | | ... -->| X | + * v v +--------+ + * +--------+ | + * -->| | | + * ...| Branch |----+ + * -->| i | + * +--------+ + * + * 2. Input buffers/inverters + * 3. Output buffers/inverters + *********************************************************************/ +static +void build_rram_mux_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const std::string& module_name, + const MuxGraph& mux_graph) { + /* Error out for the conditions where we are not yet supported! */ + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + /* RRAM LUT is not supported now... */ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])RRAM-based LUT is not supported (Circuit model: %s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } + + /* Get the global ports required by MUX (and any submodules) */ + std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); + /* Get the input ports from the mux */ + std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the BL and WL ports from the mux */ + std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); + std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); + + /* Generate the Verilog netlist according to the mux_graph */ + /* Find out the number of data-path inputs */ + size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); + /* Find out the number of outputs */ + size_t num_outputs = mux_graph.num_outputs(); + /* Find out the number of memory bits */ + size_t num_mems = mux_graph.num_memory_bits(); + + /* Check codes to ensure the port of Verilog netlists will match */ + /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ + VTR_ASSERT(1 == mux_input_ports.size()); + VTR_ASSERT(1 == mux_blb_ports.size()); + VTR_ASSERT(1 == mux_wl_ports.size()); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId module_id = module_manager.add_module(module_name); + VTR_ASSERT(ModuleId::INVALID() != module_id); + /* Add module ports */ + /* Add each global port */ + for (const auto& port : mux_global_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port */ + size_t input_port_cnt = 0; + for (const auto& port : mux_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Update counter */ + input_port_cnt++; + } + /* Double check: We should have only 1 input port generated here! */ + VTR_ASSERT(1 == input_port_cnt); + + for (const auto& port : mux_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { + output_port.set_width(circuit_lib.port_size(port)); + } + module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* BLB port */ + for (const auto& port : mux_blb_ports) { + /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level + * So, the actual port width of BLB should be added by the number of levels of the MUX graph + */ + BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* WL port */ + for (const auto& port : mux_wl_ports) { + /* IMPORTANT: RRAM-based MUX has an additional WL pin per level + * So, the actual port width of WL should be added by the number of levels of the MUX graph + */ + BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* TODO: Add the input and output buffers in Verilog codes */ + + /* TODO: Print the internal logic in Verilog codes */ +} + +/*********************************************** + * Generate Verilog codes modeling a multiplexer + * with the given graph-level description + **********************************************/ +static +void build_mux_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const MuxGraph& mux_graph) { + std::string module_name = generate_mux_subckt_name(circuit_lib, circuit_model, + find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), + std::string("")); + + /* Multiplexers built with different technology is in different organization */ + switch (circuit_lib.design_tech_type(circuit_model)) { + case SPICE_MODEL_DESIGN_CMOS: + /* SRAM-based Multiplexer Verilog module generation */ + build_cmos_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* TODO: RRAM-based Multiplexer Verilog module generation */ + build_rram_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + exit(1); + } +} + + +/*********************************************** + * Generate Verilog modules for all the unique + * multiplexers in the FPGA device + **********************************************/ +void build_mux_modules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib) { + + /* Generate basis sub-circuit for unique branches shared by the multiplexers */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* Create a mux graph for the branch circuit */ + std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); + /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ + for (auto branch_mux_graph : branch_mux_graphs) { + build_mux_branch_module(module_manager, circuit_lib, mux_circuit_model, + find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), + branch_mux_graph); + } + } + + /* Generate unique Verilog modules for the multiplexers */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); + /* Create MUX circuits */ + build_mux_module(module_manager, circuit_lib, mux_circuit_model, mux_graph); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h new file mode 100644 index 000000000..7b65b56b9 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h @@ -0,0 +1,19 @@ +/*********************************************** + * Header file for verilog_mux.cpp + **********************************************/ + +#ifndef BUILD_MUX_MODULES_H +#define BUILD_MUX_MODULES_H + +/* Include other header files which are dependency on the function declared below */ +#include "spice_types.h" +#include "circuit_library.h" +#include "mux_graph.h" +#include "mux_library.h" +#include "module_manager.h" + +void build_mux_modules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index 908bc8555..4ba620dbd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -62,11 +62,30 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag } /* Reach here, this is a local wire */ - std::string net_name; + if (false == module_manager.net_name(module_id, module_net).empty()) { + net_name = module_manager.net_name(module_id, module_net); + printf("net_name:%s\n", net_name.c_str()); + } + /* Each net must only one 1 source */ + if (1 != module_manager.net_source_modules(module_id, module_net).size()) { + for (auto src_module : module_manager.net_source_modules(module_id, module_net)) { + printf("net_source_module: %s\n", + module_manager.module_name(src_module).c_str()); + } + for (auto sink_module : module_manager.net_sink_modules(module_id, module_net)) { + printf("net_sink_module: %s\n", + module_manager.module_name(sink_module).c_str()); + for (auto sink_port : module_manager.net_sink_ports(module_id, module_net)) { + printf("\tnet_sink_port: %s\n", + module_manager.module_port(sink_module, sink_port).get_name().c_str()); + } + } + VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size()); + } /* Get the source module */ ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)]; @@ -102,6 +121,12 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu /* Local wires come from the child modules */ for (ModuleNetId module_net : module_manager.module_nets(module_id)) { + /* Bypass dangling nets */ + if ( (0 == module_manager.net_source_modules(module_id, module_net).size()) + && (0 == module_manager.net_source_modules(module_id, module_net).size()) ) { + continue; + } + /* We only care local wires */ if (false == module_net_is_local_wire(module_manager, module_id, module_net)) { continue; @@ -260,8 +285,15 @@ void write_verilog_instance_to_file(std::fstream& fp, /* Print module name */ fp << "\t" << module_manager.module_name(child_module) << " "; - /* Print instance name, _ */ - fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl; + /* Print instance name: + * if we have an instance name, use it; + * if not, we use a default name _ + */ + if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) { + fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl; + } else { + fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl; + } /* Print each port with/without explicit port map */ /* port type2type mapping */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 0f4b10579..232d7fdf4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -28,86 +28,9 @@ /* FPGA-Verilog context header files */ #include "verilog_global.h" #include "verilog_writer_utils.h" +#include "verilog_module_writer.h" #include "verilog_mux.h" -/********************************************************************* - * Generate structural Verilog codes (consist of transmission-gates or - * pass-transistor) modeling an branch circuit - * for a multiplexer with the given size - *********************************************************************/ -static -void generate_verilog_cmos_mux_branch_body_structural(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& tgate_model, - const ModuleId& module_id, - const BasicPort& input_port, - const BasicPort& output_port, - const BasicPort& mem_port, - const BasicPort& mem_inv_port, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Get the module id of tgate in Module manager */ - ModuleId tgate_module_id = module_manager.find_module(circuit_lib.model_name(tgate_model)); - VTR_ASSERT(ModuleId::INVALID() != tgate_module_id); - - /* TODO: move to check_circuit_library? Get model ports of tgate */ - std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); - std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(3 == tgate_input_ports.size()); - VTR_ASSERT(1 == tgate_output_ports.size()); - - /* Verilog Behavior description for a MUX */ - print_verilog_comment(fp, std::string("---- Structure-level description -----")); - - /* Output the netlist following the connections in mux_graph */ - /* Iterate over the inputs */ - for (const auto& mux_input : mux_graph.inputs()) { - BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); - /* Iterate over the outputs */ - for (const auto& mux_output : mux_graph.outputs()) { - BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); - /* if there is a connection between the input and output, a tgate will be outputted */ - std::vector edges = mux_graph.find_edges(mux_input, mux_output); - /* There should be only one edge or no edge*/ - VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); - /* No need to output tgates if there are no edges between two nodes */ - if (0 == edges.size()) { - continue; - } - /* Output a tgate use a module manager */ - /* Create a port-to-port name map */ - std::map port2port_name_map; - /* input port */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[0])] = cur_input_port; - /* output port */ - port2port_name_map[circuit_lib.port_lib_name(tgate_output_ports[0])] = cur_output_port; - /* Find the mem_id controlling the edge */ - MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); - BasicPort cur_mem_port(mem_port.get_name(), size_t(mux_mem), size_t(mux_mem)); - BasicPort cur_mem_inv_port(mem_inv_port.get_name(), size_t(mux_mem), size_t(mux_mem)); - /* mem port */ - if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { - /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_port; - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_inv_port; - } else { - /* wire mem_inv to mem of module, wire mem to mem_inv of module */ - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[1])] = cur_mem_inv_port; - port2port_name_map[circuit_lib.port_lib_name(tgate_input_ports[2])] = cur_mem_port; - } - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, tgate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(tgate_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, tgate_module_id); - } - } -} - /********************************************************************* * Generate behavior-level Verilog codes modeling an branch circuit * for a multiplexer with the given size @@ -186,15 +109,14 @@ void generate_verilog_cmos_mux_branch_body_behavioral(std::fstream& fp, * Support structural and behavioral Verilog codes *********************************************************************/ static -void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& circuit_model, - const std::string& module_name, - const MuxGraph& mux_graph, - const bool& use_structural_verilog) { +void print_verilog_cmos_mux_branch_module_behavioral(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::fstream& fp, + const CircuitModelId& mux_model, + const std::string& module_name, + const MuxGraph& mux_graph) { /* Get the tgate model */ - CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model); + CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model); /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { @@ -202,8 +124,6 @@ void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager, return; } - std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true, true); - /* Make sure we have a valid file handler*/ check_file_handler(fp); @@ -222,51 +142,27 @@ void generate_verilog_cmos_mux_branch_module(ModuleManager& module_manager, VTR_ASSERT(1 == mux_graph.num_levels()); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : tgate_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ + ModuleId mux_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + /* Find module ports */ + /* Find each input port */ BasicPort input_port("in", num_inputs); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Add each output port */ + /* Find each output port */ BasicPort output_port("out", num_outputs); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Add each memory port */ + /* Find each memory port */ BasicPort mem_port("mem", num_mems); - module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port("mem_inv", num_mems); - module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); + print_verilog_module_declaration(fp, module_manager, mux_module); - /* Print the internal logic in either structural or behavioral Verilog codes */ - if (true == use_structural_verilog) { - generate_verilog_cmos_mux_branch_body_structural(module_manager, circuit_lib, fp, tgate_model, module_id, input_port, output_port, mem_port, mem_inv_port, mux_graph); - } else { - VTR_ASSERT_SAFE(false == use_structural_verilog); - /* Get the default value of SRAM ports */ - std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); - std::vector non_mode_select_sram_ports; - /* We should have only have 1 sram port except those are mode_bits */ - for (const auto& port : sram_ports) { - if (true == circuit_lib.port_is_mode_select(port)) { - continue; - } - non_mode_select_sram_ports.push_back(port); - } - VTR_ASSERT(1 == non_mode_select_sram_ports.size()); - std::string mem_default_val = std::to_string(circuit_lib.port_default_value(non_mode_select_sram_ports[0])); - /* Mem string must be only 1-bit! */ - VTR_ASSERT(1 == mem_default_val.length()); - generate_verilog_cmos_mux_branch_body_behavioral(fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]); - } + /* Print the internal logic in behavioral Verilog codes */ + /* Get the default value of SRAM ports */ + std::vector regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); + VTR_ASSERT(1 == regular_sram_ports.size()); + std::string mem_default_val = std::to_string(circuit_lib.port_default_value(regular_sram_ports[0])); + /* Mem string must be only 1-bit! */ + VTR_ASSERT(1 == mem_default_val.length()); + generate_verilog_cmos_mux_branch_body_behavioral(fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]); /* Put an end to the Verilog module */ print_verilog_module_end(fp, module_name); @@ -638,35 +534,22 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, VTR_ASSERT(1 == mux_wl_ports.size()); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); + ModuleId module_id = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - /* Add module ports */ - /* Add each global programming enable/disable ports */ - std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - for (const auto& port : prog_enable_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - - /* Add each input port */ + /* Find each input port */ BasicPort input_port(circuit_lib.port_lib_name(mux_input_ports[0]), num_inputs); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Add each output port */ + /* Find each output port */ BasicPort output_port(circuit_lib.port_lib_name(mux_output_ports[0]), num_outputs); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Add RRAM programming ports, + /* Find RRAM programming ports, * RRAM MUXes require one more pair of BLB and WL * to configure the memories. See schematic for details */ BasicPort blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), num_mems + 1); - module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); BasicPort wl_port(circuit_lib.port_lib_name(mux_wl_ports[0]), num_mems + 1); - module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); @@ -690,442 +573,38 @@ static void generate_verilog_mux_branch_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, - const CircuitModelId& circuit_model, + const CircuitModelId& mux_model, const size_t& mux_size, const MuxGraph& mux_graph) { - std::string module_name = generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); + std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(circuit_model)) { + switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: - generate_verilog_cmos_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph, - circuit_lib.dump_structural_verilog(circuit_model)); + if (true == circuit_lib.dump_structural_verilog(mux_model)) { + /* Structural verilog can be easily generated by module writer */ + ModuleId mux_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + write_verilog_module_to_file(fp, module_manager, mux_module, circuit_lib.dump_explicit_port_map(mux_model)); + /* Add an empty line as a splitter */ + fp << std::endl; + } else { + /* Behavioral verilog requires customized generation */ + print_verilog_cmos_mux_branch_module_behavioral(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph); + } break; case SPICE_MODEL_DESIGN_RRAM: - generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph, - circuit_lib.dump_structural_verilog(circuit_model)); + generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph, + circuit_lib.dump_structural_verilog(mux_model)); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); exit(1); } } -/******************************************************************** - * Generate the standard-cell-based internal logic (multiplexing structure) - * for a multiplexer or LUT in Verilog codes - * This function will : - * 1. build a multiplexing structure by instanciating standard cells MUX2 - * 2. add intermediate buffers between multiplexing stages if specified. - *******************************************************************/ -static -void generate_verilog_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const CircuitModelId& std_cell_model, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* TODO: these are duplicated codes, find a way to simplify it!!! - * Get the regular (non-mode-select) sram ports from the mux - */ - std::vector mux_regular_sram_ports; - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true)) { - /* Multiplexing structure does not mode_sram_ports, they are handled in LUT modules - * Here we just bypass it. - */ - if (true == circuit_lib.port_is_mode_select(port)) { - continue; - } - mux_regular_sram_ports.push_back(port); - } - VTR_ASSERT(1 == mux_regular_sram_ports.size()); - - /* Find the input ports and output ports of the standard cell */ - std::vector std_cell_input_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_INPUT, true); - std::vector std_cell_output_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Quick check the requirements on port map */ - VTR_ASSERT(3 == std_cell_input_ports.size()); - VTR_ASSERT(1 == std_cell_output_ports.size()); - - /* Build the location map of intermediate buffers */ - std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); - - print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a CMOS MUX module based on Standard Cells -----")); - - print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a CMOS MUX module -----")); - /* Print local wires which are the nodes in the mux graph */ - for (size_t level = 0; level < mux_graph.num_levels(); ++level) { - /* Print the internal wires located at this level */ - BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; - /* Identify if an intermediate buffer is needed */ - if (false == inter_buffer_location_map[level]) { - continue; - } - BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; - } - print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); - fp << std::endl; - - /* Iterate over all the internal nodes and output nodes in the mux graph */ - for (const auto& node : mux_graph.non_input_nodes()) { - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX modules -----")); - /* Get the size of branch circuit - * Instanciate an branch circuit by the size (fan-in) of the node - */ - size_t branch_size = mux_graph.node_in_edges(node).size(); - - /* Get the nodes which drive the root_node */ - std::vector input_nodes; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the nodes drive the edge */ - for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { - input_nodes.push_back(src_node); - } - } - /* Number of inputs should match the branch_input_size!!! */ - VTR_ASSERT(input_nodes.size() == branch_size); - - /* Get the node level and index in the current level */ - size_t output_node_level = mux_graph.node_level(node); - size_t output_node_index_at_level = mux_graph.node_index_at_level(node); - - /* Get the mems in the branch circuits */ - std::vector mems; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the mem control the edge */ - MuxMemId mem = mux_graph.find_edge_mem(edge); - /* Add the mem if it is not in the list */ - if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { - mems.push_back(mem); - } - } - - /* Instanciate the branch module, which is a standard cell MUX2 - * We follow a fixed port map: - * TODO: the port map could be more flexible? - * input_port[0] of MUX2 standard cell is wired to input_node[0] - * input_port[1] of MUX2 standard cell is wired to input_node[1] - * output_port[0] of MUX2 standard cell is wired to output_node[0] - * input_port[2] of MUX2 standard cell is wired to mem_node[0] - */ - std::string branch_module_name= circuit_lib.model_name(std_cell_model); - /* Get the moduleId for the submodule */ - ModuleId branch_module_id = module_manager.find_module(branch_module_name); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != branch_module_id); - - /* Create a port-to-port map */ - std::map port2port_name_map; - - /* To match the standard cell MUX2: We should have only 2 input_nodes */ - VTR_ASSERT(2 == input_nodes.size()); - /* Build the link between input_node[0] and std_cell_input_port[0] - * Build the link between input_node[1] and std_cell_input_port[1] - */ - for (const auto& input_node : input_nodes) { - /* Generate the port info of each input node */ - size_t input_node_level = mux_graph.node_level(input_node); - size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort instance_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); - - /* Link nodes to input ports for the branch module */ - std::string module_input_port_name = circuit_lib.port_lib_name(std_cell_input_ports[&input_node - &input_nodes[0]]); - port2port_name_map[module_input_port_name] = instance_input_port; - } - - /* Build the link between output_node[0] and std_cell_output_port[0] */ - { /* Create a code block to accommodate the local variables */ - BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - std::string module_output_port_name = circuit_lib.port_lib_name(std_cell_output_ports[0]); - port2port_name_map[module_output_port_name] = instance_output_port; - } - - /* To match the standard cell MUX2: We should have only 1 mem_node */ - VTR_ASSERT(1 == mems.size()); - /* Build the link between mem_node[0] and std_cell_intput_port[2] */ - for (const auto& mem : mems) { - /* Generate the port info of each mem node */ - BasicPort instance_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); - std::string module_mem_port_name = circuit_lib.port_lib_name(std_cell_input_ports[2]); - /* If use local decoders, we should use another name for the mem port */ - if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { - instance_mem_port.set_name(generate_mux_local_decoder_data_port_name()); - } - port2port_name_map[module_mem_port_name] = instance_mem_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(std_cell_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, branch_module_id); - - print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX modules -----")); - - if (false == inter_buffer_location_map[output_node_level]) { - continue; /* No need for intermediate buffers */ - } - - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a intermediate buffer modules -----")); - - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); - - print_verilog_comment(fp, std::string("---- END Instanciation of a intermediate buffer modules -----")); - fp << std::endl; - } - - print_verilog_comment(fp, std::string("---- END Internal Logic of a CMOS MUX module based on Standard Cells -----")); - fp << std::endl; -} - -/******************************************************************** - * Generate the pass-transistor/transmission-gate -based internal logic - * (multiplexing structure) for a multiplexer or LUT in Verilog codes - * This function will : - * 1. build a multiplexing structure by instanciating the branch circuits - * generated before - * 2. add intermediate buffers between multiplexing stages if specified. - *******************************************************************/ -static -void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Find the actual mux size */ - size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - - /* Get the regular (non-mode-select) sram ports from the mux */ - std::vector mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model); - VTR_ASSERT(1 == mux_regular_sram_ports.size()); - - /* Build the location map of intermediate buffers */ - std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); - - print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a CMOS MUX module based on Pass-transistor/Transmission-gates -----")); - - print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a CMOS MUX module -----")); - /* Print local wires which are the nodes in the mux graph */ - for (size_t level = 0; level < mux_graph.num_levels(); ++level) { - /* Print the internal wires located at this level */ - BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; - /* Identify if an intermediate buffer is needed */ - if (false == inter_buffer_location_map[level]) { - continue; - } - BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; - } - print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----")); - fp << std::endl; - - /* Iterate over all the internal nodes and output nodes in the mux graph */ - for (const auto& node : mux_graph.non_input_nodes()) { - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----")); - /* Get the size of branch circuit - * Instanciate an branch circuit by the size (fan-in) of the node - */ - size_t branch_size = mux_graph.node_in_edges(node).size(); - - /* Get the node level and index in the current level */ - size_t output_node_level = mux_graph.node_level(node); - size_t output_node_index_at_level = mux_graph.node_index_at_level(node); - - /* Get the nodes which drive the root_node */ - std::vector input_nodes; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the nodes drive the edge */ - for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { - input_nodes.push_back(src_node); - } - } - /* Number of inputs should match the branch_input_size!!! */ - VTR_ASSERT(input_nodes.size() == branch_size); - - /* Get the mems in the branch circuits */ - std::vector mems; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the mem control the edge */ - MuxMemId mem = mux_graph.find_edge_mem(edge); - /* Add the mem if it is not in the list */ - if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { - mems.push_back(mem); - } - } - - /* Instanciate the branch module which is a tgate-based module - */ - std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); - /* Get the moduleId for the submodule */ - ModuleId branch_module_id = module_manager.find_module(branch_module_name); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != branch_module_id); - - /* Create a port-to-port map */ - std::map port2port_name_map; - /* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */ - - /* All the input node names organized in bus */ - std::vector branch_node_input_ports; - for (const auto& input_node : input_nodes) { - /* Generate the port info of each input node */ - size_t input_node_level = mux_graph.node_level(input_node); - size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort branch_node_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); - branch_node_input_ports.push_back(branch_node_input_port); - } - - /* Create the port info for the input */ - /* TODO: the naming could be more flexible? */ - BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_mux_node_name(output_node_level, false) + "_in")); - /* If we have more than 1 port in the combined instance ports , - * output a local wire */ - if (1 < combine_verilog_ports(branch_node_input_ports).size()) { - /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_local_wire(instance_input_port, branch_node_input_ports) << std::endl; - } else { - /* Safety check */ - VTR_ASSERT(1 == combine_verilog_ports(branch_node_input_ports).size()); - } - - /* Link nodes to input ports for the branch module */ - ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in"); - VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - /* Get the port from module */ - BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id); - port2port_name_map[module_input_port.get_name()] = instance_input_port; - - /* Link nodes to output ports for the branch module */ - BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out"); - VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - /* Get the port from module */ - BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id); - port2port_name_map[module_output_port.get_name()] = instance_output_port; - - /* All the mem node names organized in bus */ - std::vector branch_node_mem_ports; - for (const auto& mem : mems) { - /* Generate the port info of each mem node */ - BasicPort branch_node_mem_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]), size_t(mem), size_t(mem)); - /* If use local decoders, we should use another name for the mem port */ - if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { - branch_node_mem_port.set_name(generate_mux_local_decoder_data_port_name()); - } - branch_node_mem_ports.push_back(branch_node_mem_port); - } - - /* Create the port info for the input */ - /* TODO: the naming could be more flexible? */ - BasicPort instance_mem_port = generate_verilog_bus_port(branch_node_mem_ports, std::string(generate_mux_node_name(output_node_level, false) + "_mem")); - /* If we have more than 1 port in the combined instance ports , - * output a local wire */ - if (1 < combine_verilog_ports(branch_node_mem_ports).size()) { - /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_local_wire(instance_mem_port, branch_node_mem_ports) << std::endl; - } else { - /* Safety check */ - VTR_ASSERT(1 == combine_verilog_ports(branch_node_mem_ports).size()); - } - - /* Link nodes to input ports for the branch module */ - /* TODO: the naming could be more flexible? */ - ModulePortId module_mem_port_id = module_manager.find_module_port(branch_module_id, "mem"); - VTR_ASSERT(ModulePortId::INVALID() != module_mem_port_id); - /* Get the port from module */ - BasicPort module_mem_port = module_manager.module_port(branch_module_id, module_mem_port_id); - port2port_name_map[module_mem_port.get_name()] = instance_mem_port; - - /* TODO: the postfix _inv can be soft coded in the circuit library as a port_inv_postfix */ - /* Create the port info for the mem_inv */ - std::vector branch_node_mem_inv_ports; - for (const auto& mem : mems) { - /* Generate the port info of each mem node */ - BasicPort branch_node_mem_inv_port(circuit_lib.port_lib_name(mux_regular_sram_ports[0]) + "_inv", size_t(mem), size_t(mem)); - /* If use local decoders, we should use another name for the mem port */ - if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { - branch_node_mem_inv_port.set_name(generate_mux_local_decoder_data_inv_port_name()); - } - branch_node_mem_inv_ports.push_back(branch_node_mem_inv_port); - } - - /* Create the port info for the input */ - /* TODO: the naming could be more flexible? */ - BasicPort instance_mem_inv_port = generate_verilog_bus_port(branch_node_mem_inv_ports, std::string(generate_mux_node_name(output_node_level, false) + "_mem_inv")); - /* If we have more than 1 port in the combined instance ports , - * output a local wire */ - if (1 < combine_verilog_ports(branch_node_mem_inv_ports).size()) { - /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_local_wire(instance_mem_port, branch_node_mem_inv_ports) << std::endl; - } else { - /* Safety check */ - VTR_ASSERT(1 == combine_verilog_ports(branch_node_mem_inv_ports).size()); - } - - /* Link nodes to input ports for the branch module */ - /* TODO: the naming could be more flexible? */ - ModulePortId module_mem_inv_port_id = module_manager.find_module_port(branch_module_id, "mem_inv"); - VTR_ASSERT(ModulePortId::INVALID() != module_mem_inv_port_id); - /* Get the port from module */ - BasicPort module_mem_inv_port = module_manager.module_port(branch_module_id, module_mem_inv_port_id); - port2port_name_map[module_mem_inv_port.get_name()] = instance_mem_inv_port; - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, branch_module_id); - - print_verilog_comment(fp, std::string("---- END Instanciation of a branch CMOS MUX module -----")); - fp << std::endl; - - if (false == inter_buffer_location_map[output_node_level]) { - continue; /* No need for intermediate buffers */ - } - - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an intermediate buffer modules -----")); - - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); - - print_verilog_comment(fp, std::string("---- END Instanciation of an intermediate buffer module -----")); - fp << std::endl; - } - - print_verilog_comment(fp, std::string("---- END Internal Logic of a CMOS MUX module based on Pass-transistor/Transmission-gates -----")); - fp << std::endl; -} - /******************************************************************** * Generate the input bufferes for a multiplexer or LUT in Verilog codes * 1. If input are required to be buffered (specified by users), @@ -1297,196 +776,6 @@ void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manag } } -/********************************************************************* - * Generate Verilog codes modeling a CMOS multiplexer with the given size - * The Verilog module will consist of three parts: - * 1. instances of the branch circuits of multiplexers which are generated before - * This builds up the multiplexing structure - * 2. Input buffers/inverters - * 3. Output buffers/inverters - *********************************************************************/ -static -void generate_verilog_cmos_mux_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& circuit_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Get the global ports required by MUX (and any submodules) */ - std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the sram ports from the mux - * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules - * Here we just bypass it. - */ - std::vector mux_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model); - - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of data-path inputs */ - size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* The size of of memory ports depend on - * if a local encoder is used for the mux or not - * Multiplexer local encoders are applied to memory bits at each stage - */ - if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { - num_mems = 0; - for (const auto& lvl : mux_graph.levels()) { - size_t data_size = mux_graph.num_memory_bits_at_level(lvl); - num_mems += find_mux_local_decoder_addr_size(data_size); - } - } - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == mux_input_ports.size()); - /* A quick check on the model ports */ - if ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) - || ((SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) - && (false == circuit_lib.is_lut_fracturable(circuit_model))) ) { - VTR_ASSERT(1 == mux_output_ports.size()); - VTR_ASSERT(1 == circuit_lib.port_size(mux_output_ports[0])); - } else { - VTR_ASSERT_SAFE( (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) - && (true == circuit_lib.is_lut_fracturable(circuit_model)) ); - for (const auto& port : mux_output_ports) { - VTR_ASSERT(0 < circuit_lib.port_size(port)); - } - } - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : mux_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port - * Treat MUX and LUT differently - * 1. MUXes: we do not have a specific input/output sizes, it is inferred by architecture - * 2. LUTes: we do have specific input/output sizes, - * but the inputs of MUXes are the SRAM ports of LUTs - * and the SRAM ports of MUXes are the inputs of LUTs - */ - size_t input_port_cnt = 0; - for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Update counter */ - input_port_cnt++; - } - /* Double check: We should have only 1 input port generated here! */ - VTR_ASSERT(1 == input_port_cnt); - - for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - output_port.set_width(circuit_lib.port_size(port)); - } - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - size_t sram_port_cnt = 0; - for (const auto& port : mux_sram_ports) { - BasicPort mem_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), num_mems); - module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - /* Update counter */ - sram_port_cnt++; - } - VTR_ASSERT(1 == sram_port_cnt); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - - /* Add local decoder instance here */ - if (true == circuit_lib.mux_use_local_encoder(circuit_model)) { - BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits()); - BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); - /* Print local wires to bridge the port of module and memory inputs - * of each MUX branch instance - */ - fp << generate_verilog_port(VERILOG_PORT_WIRE, decoder_data_port) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_WIRE, decoder_data_inv_port) << ";" << std::endl; - - /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ - BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); - BasicPort lvl_data_port(decoder_data_port.get_name(), 0); - BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); - for (const auto& lvl : mux_graph.levels()) { - size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); - size_t data_size = mux_graph.num_memory_bits_at_level(lvl); - /* Update the LSB and MSB of addr and data port for the current level */ - lvl_addr_port.rotate(addr_size); - lvl_data_port.rotate(data_size); - lvl_data_inv_port.rotate(data_size); - /* Print the instance of local decoder */ - std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); - ModuleId decoder_module = module_manager.find_module(decoder_module_name); - VTR_ASSERT(ModuleId::INVALID() != decoder_module); - - /* Create a port-to-port map */ - std::map decoder_port2port_name_map; - decoder_port2port_name_map[generate_mux_local_decoder_addr_port_name()] = lvl_addr_port; - decoder_port2port_name_map[generate_mux_local_decoder_data_port_name()] = lvl_data_port; - decoder_port2port_name_map[generate_mux_local_decoder_data_inv_port_name()] = lvl_data_inv_port; - - /* Print an instance of the MUX Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a local decoder -----")); - print_verilog_module_instance(fp, module_manager, module_id, decoder_module, decoder_port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - print_verilog_comment(fp, std::string("----- END Instanciation of a local decoder -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, decoder_module); - } - } - - /* Print the internal logic in Verilog codes */ - /* Print the Multiplexing structure in Verilog codes - * Separated generation strategy on using standard cell MUX2 or TGATE, - * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input - * 2. Branch TGATE-based module has a fixed port name - * TODO: the naming could be more flexible? - */ - /* Get the tgate model */ - CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model); - /* Instanciate the branch module: - * Case 1: the branch module is a standard cell MUX2 - * Case 2: the branch module is a tgate-based module - */ - std::string branch_module_name; - if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { - VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); - generate_verilog_cmos_mux_module_mux2_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, tgate_model, mux_graph); - } else { - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_lib.model_type(tgate_model)); - generate_verilog_cmos_mux_module_tgate_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - } - - /* Print the input and output buffers in Verilog codes */ - generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - /******************************************************************** * Generate the 4T1R-based internal logic * (multiplexing structure) for a multiplexer in Verilog codes @@ -1880,26 +1169,31 @@ static void generate_verilog_mux_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, - const CircuitModelId& circuit_model, + const CircuitModelId& mux_model, const MuxGraph& mux_graph) { - std::string module_name = generate_mux_subckt_name(circuit_lib, circuit_model, - find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), + std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, + find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), std::string("")); /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(circuit_model)) { - case SPICE_MODEL_DESIGN_CMOS: - /* SRAM-based Multiplexer Verilog module generation */ - generate_verilog_cmos_mux_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: { + /* Use Verilog writer to print the module to file */ + ModuleId mux_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + write_verilog_module_to_file(fp, module_manager, mux_module, circuit_lib.dump_explicit_port_map(mux_model)); + /* Add an empty line as a splitter */ + fp << std::endl; break; + } case SPICE_MODEL_DESIGN_RRAM: /* TODO: RRAM-based Multiplexer Verilog module generation */ - generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph); + generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); exit(1); } } From fe433f3e50a4bf6e117b2914a655bb669d0f39fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 12:23:00 -0600 Subject: [PATCH 314/482] bug fixed for local encoders and module nets creation --- .../module_builder/build_mux_modules.cpp | 273 +++++++++++------- .../verilog/verilog_module_writer.cpp | 28 +- 2 files changed, 168 insertions(+), 133 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 5385da9ae..39f524ecd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -1028,6 +1028,161 @@ vtr::vector build_mux_module_output_buffers(ModuleMana return mux_output_nets; } +/********************************************************************* + * This function will + * 1. Build local encoders for a MUX module (if specified) + * 2. Build nets between memory ports of a MUX module and branch circuits + * This happens when local encoders are not needed + * + * MUX module + * +--------------------- + * | mux_mem_nets/mux_mem_inv_nets + * | | + * | v +--------- + * mem-+-------->| + * | | Branch Module + * | | + * + * 3. Build nets between local encoders and memory ports of a MUX module + * This happens when local encoders are needed + * 4. Build nets between local encoders and branch circuits + * This happens when local encoders are needed + * + * MUX module + * +--------------------- + * | + * | +-------+ mux_mem_nets/mux_mem_inv_nets + * | | | | + * mem--+------>| | v +--------- + * | | Local |-------->| + * | |Encoder| | Branch + * | | | | Module + * | | | | + * | | | | + * + *********************************************************************/ +static +void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manager, + const ModuleId& mux_module, + const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const std::vector& mux_sram_ports, + const MuxGraph& mux_graph, + vtr::vector& mux_mem_nets, + vtr::vector& mux_mem_inv_nets) { + + /* Create nets here, and we will configure the net source later */ + for (size_t mem = 0; mem < mux_graph.num_memory_bits(); ++mem) { + ModuleNetId mem_net = module_manager.create_module_net(mux_module); + mux_mem_nets.push_back(mem_net); + ModuleNetId mem_inv_net = module_manager.create_module_net(mux_module); + mux_mem_inv_nets.push_back(mem_inv_net); + } + + if (false == circuit_lib.mux_use_local_encoder(mux_model)) { + /* Add mem and mem_inv nets here */ + size_t mem_net_cnt = 0; + for (const auto& port : mux_sram_ports) { + ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(port)); + BasicPort mem_port = module_manager.module_port(mux_module, mem_port_id); + for (const size_t& pin : mem_port.pins()) { + MuxMemId mem_id = MuxMemId(mem_net_cnt); + /* Set the module net source */ + module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mem_port_id, pin); + /* Update counter */ + mem_net_cnt++; + } + } + VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); + + /* Add mem and mem_inv nets here */ + size_t mem_inv_net_cnt = 0; + for (const auto& port : mux_sram_ports) { + ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_lib_name(port) + "_inv")); + BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id); + for (const size_t& pin : mem_inv_port.pins()) { + MuxMemId mem_id = MuxMemId(mem_inv_net_cnt); + /* Set the module net source */ + module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_id], mux_module, 0, mem_inv_port_id, pin); + /* Update counter */ + mem_inv_net_cnt++; + } + } + VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); + return; /* Finish here if local encoders are not required */ + } + + /* Add local decoder instance here */ + VTR_ASSERT(true == circuit_lib.mux_use_local_encoder(mux_model)); + BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits()); + BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); + + /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ + ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0])); + BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); + BasicPort lvl_data_port(decoder_data_port.get_name(), 0); + BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); + + /* Counter for mem index */ + size_t mem_net_cnt = 0; + size_t mem_inv_net_cnt = 0; + + for (const auto& lvl : mux_graph.levels()) { + size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); + size_t data_size = mux_graph.num_memory_bits_at_level(lvl); + /* Update the LSB and MSB of addr and data port for the current level */ + lvl_addr_port.rotate(addr_size); + lvl_data_port.rotate(data_size); + lvl_data_inv_port.rotate(data_size); + + std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); + ModuleId decoder_module = module_manager.find_module(decoder_module_name); + VTR_ASSERT(ModuleId::INVALID() != decoder_module); + + size_t decoder_instance = module_manager.num_instance(mux_module, decoder_module); + module_manager.add_child_module(mux_module, decoder_module); + + /* Add module nets to connect sram ports of MUX to address port */ + ModulePortId decoder_module_addr_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_addr_port_name()); + BasicPort decoder_module_addr_port = module_manager.module_port(decoder_module, decoder_module_addr_port_id); + VTR_ASSERT(decoder_module_addr_port.get_width() == lvl_addr_port.get_width()); + + /* Build pin-to-pin net connection */ + for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(mux_module); + module_manager.add_module_net_source(mux_module, net, mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]); + module_manager.add_module_net_sink(mux_module, net, decoder_module, decoder_instance, decoder_module_addr_port_id, decoder_module_addr_port.pins()[pin_id]); + } + + /* Add module nets to connect data port to MUX mem ports */ + ModulePortId decoder_module_data_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_port_name()); + BasicPort decoder_module_data_port = module_manager.module_port(decoder_module, decoder_module_data_port_id); + + /* Build pin-to-pin net connection */ + for (const size_t& pin : decoder_module_data_port.pins()) { + ModuleNetId net = mux_mem_nets[MuxMemId(mem_net_cnt)]; + module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_port_id, pin); + module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_port.get_name() + "_" + std::to_string(pin) + "_")); + /* Add the module nets to mux_mem_nets cache */ + mem_net_cnt++; + } + + ModulePortId decoder_module_data_inv_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_inv_port_name()); + BasicPort decoder_module_data_inv_port = module_manager.module_port(decoder_module, decoder_module_data_inv_port_id); + + /* Build pin-to-pin net connection */ + for (const size_t& pin : decoder_module_data_inv_port.pins()) { + ModuleNetId net = mux_mem_inv_nets[MuxMemId(mem_inv_net_cnt)]; + module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_inv_port_id, pin); + module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_inv_port.get_name() + "_" + std::to_string(pin) + "_")); + /* Add the module nets to mux_mem_inv_nets cache */ + mem_inv_net_cnt++; + } + } + VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); + VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); +} + /********************************************************************* * Generate module of a CMOS multiplexer with the given size * The module will consist of three parts: @@ -1140,118 +1295,12 @@ void build_cmos_mux_module(ModuleManager& module_manager, /* Create module nets for mem and mem_inv ports */ vtr::vector mux_mem_nets; vtr::vector mux_mem_inv_nets; - /* Create nets here, and we will configure the net source later */ - for (size_t mem = 0; mem < mux_graph.num_memory_bits(); ++mem) { - ModuleNetId mem_net = module_manager.create_module_net(mux_module); - mux_mem_nets.push_back(mem_net); - ModuleNetId mem_inv_net = module_manager.create_module_net(mux_module); - mux_mem_inv_nets.push_back(mem_inv_net); - } - - if (false == circuit_lib.mux_use_local_encoder(mux_model)) { - /* Add mem and mem_inv nets here */ - size_t mem_net_cnt = 0; - for (const auto& port : mux_sram_ports) { - ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(port)); - BasicPort mem_port = module_manager.module_port(mux_module, mem_port_id); - for (const size_t& pin : mem_port.pins()) { - MuxMemId mem_id = MuxMemId(mem_net_cnt); - /* Set the module net source */ - module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mem_port_id, pin); - /* Update counter */ - mem_net_cnt++; - } - } - VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); - - /* Add mem and mem_inv nets here */ - size_t mem_inv_net_cnt = 0; - for (const auto& port : mux_sram_ports) { - ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_lib_name(port) + "_inv")); - BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id); - for (const size_t& pin : mem_inv_port.pins()) { - MuxMemId mem_id = MuxMemId(mem_inv_net_cnt); - /* Set the module net source */ - module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_id], mux_module, 0, mem_inv_port_id, pin); - /* Update counter */ - mem_inv_net_cnt++; - } - } - VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); - } else { - /* Add local decoder instance here */ - VTR_ASSERT(true == circuit_lib.mux_use_local_encoder(mux_model)); - BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits()); - BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); - - /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ - ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0])); - BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); - BasicPort lvl_data_port(decoder_data_port.get_name(), 0); - BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); - - /* Counter for mem index */ - size_t mem_net_cnt = 0; - size_t mem_inv_net_cnt = 0; - - for (const auto& lvl : mux_graph.levels()) { - size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); - size_t data_size = mux_graph.num_memory_bits_at_level(lvl); - /* Update the LSB and MSB of addr and data port for the current level */ - lvl_addr_port.rotate(addr_size); - lvl_data_port.rotate(data_size); - lvl_data_inv_port.rotate(data_size); - - std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); - ModuleId decoder_module = module_manager.find_module(decoder_module_name); - VTR_ASSERT(ModuleId::INVALID() != decoder_module); - - size_t decoder_instance = module_manager.num_instance(mux_module, decoder_module); - module_manager.add_child_module(mux_module, decoder_module); - - /* Add module nets to connect sram ports of MUX to address port */ - ModulePortId decoder_module_addr_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_addr_port_name()); - BasicPort decoder_module_addr_port = module_manager.module_port(decoder_module, decoder_module_addr_port_id); - VTR_ASSERT(decoder_module_addr_port.get_width() == lvl_addr_port.get_width()); - - /* Build pin-to-pin net connection */ - for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, net, mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]); - module_manager.add_module_net_sink(mux_module, net, decoder_module, decoder_instance, decoder_module_addr_port_id, decoder_module_addr_port.pins()[pin_id]); - } - - /* Add module nets to connect data port to MUX mem ports */ - ModulePortId decoder_module_data_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_port_name()); - BasicPort decoder_module_data_port = module_manager.module_port(decoder_module, decoder_module_data_port_id); - - /* Build pin-to-pin net connection */ - for (const size_t& pin : decoder_module_data_port.pins()) { - ModuleNetId net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_port_id, pin); - module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_port.get_name() + "_" + std::to_string(pin) + "_")); - /* Add the module nets to mux_mem_nets cache */ - mux_mem_nets[MuxMemId(mem_net_cnt)] = net; - mem_net_cnt++; - } - - ModulePortId decoder_module_data_inv_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_inv_port_name()); - BasicPort decoder_module_data_inv_port = module_manager.module_port(decoder_module, decoder_module_data_inv_port_id); - - /* Build pin-to-pin net connection */ - for (const size_t& pin : decoder_module_data_inv_port.pins()) { - ModuleNetId net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_inv_port_id, pin); - module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_inv_port.get_name() + "_" + std::to_string(pin) + "_")); - /* Add the module nets to mux_mem_inv_nets cache */ - mux_mem_inv_nets[MuxMemId(mem_inv_net_cnt)] = net; - mem_inv_net_cnt++; - } - } - VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); - VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); - } - + + build_mux_module_local_encoders_and_memory_nets(module_manager, mux_module, + circuit_lib, mux_model, mux_sram_ports, + mux_graph, + mux_mem_nets, mux_mem_inv_nets); + /* Print the internal logic in Verilog codes */ /* Print the Multiplexing structure in Verilog codes * Separated generation strategy on using standard cell MUX2 or TGATE, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index 4ba620dbd..2a495e91a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -64,28 +64,8 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag /* Reach here, this is a local wire */ std::string net_name; - if (false == module_manager.net_name(module_id, module_net).empty()) { - net_name = module_manager.net_name(module_id, module_net); - printf("net_name:%s\n", net_name.c_str()); - } - /* Each net must only one 1 source */ - if (1 != module_manager.net_source_modules(module_id, module_net).size()) { - for (auto src_module : module_manager.net_source_modules(module_id, module_net)) { - printf("net_source_module: %s\n", - module_manager.module_name(src_module).c_str()); - } - for (auto sink_module : module_manager.net_sink_modules(module_id, module_net)) { - printf("net_sink_module: %s\n", - module_manager.module_name(sink_module).c_str()); - for (auto sink_port : module_manager.net_sink_ports(module_id, module_net)) { - printf("\tnet_sink_port: %s\n", - module_manager.module_port(sink_module, sink_port).get_name().c_str()); - } - } - VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size()); - } /* Get the source module */ ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)]; @@ -121,11 +101,17 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu /* Local wires come from the child modules */ for (ModuleNetId module_net : module_manager.module_nets(module_id)) { - /* Bypass dangling nets */ + /* Bypass dangling nets: + * Xifan Tang: I comment this part because it will shadow our problems in creating module graph + * Indeed this make a robust and a smooth Verilog module writing + * But I do want the module graph create is nice and clean !!! + */ + /* if ( (0 == module_manager.net_source_modules(module_id, module_net).size()) && (0 == module_manager.net_source_modules(module_id, module_net).size()) ) { continue; } + */ /* We only care local wires */ if (false == module_net_is_local_wire(module_manager, module_id, module_net)) { From bd37f0d54295aea5f3d3d2362156b554194df4ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 13:16:15 -0600 Subject: [PATCH 315/482] correct bugs in decoder data port alignment to memory ports of multiplexing structure --- .../vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 39f524ecd..ca7aca309 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -1157,12 +1157,11 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag /* Add module nets to connect data port to MUX mem ports */ ModulePortId decoder_module_data_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_port_name()); BasicPort decoder_module_data_port = module_manager.module_port(decoder_module, decoder_module_data_port_id); - + /* Build pin-to-pin net connection */ - for (const size_t& pin : decoder_module_data_port.pins()) { + for (const size_t& pin : decoder_module_data_port.pins()) { ModuleNetId net = mux_mem_nets[MuxMemId(mem_net_cnt)]; module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_port_id, pin); - module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_port.get_name() + "_" + std::to_string(pin) + "_")); /* Add the module nets to mux_mem_nets cache */ mem_net_cnt++; } @@ -1174,7 +1173,6 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag for (const size_t& pin : decoder_module_data_inv_port.pins()) { ModuleNetId net = mux_mem_inv_nets[MuxMemId(mem_inv_net_cnt)]; module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_inv_port_id, pin); - module_manager.set_net_name(mux_module, net, std::string(decoder_module_data_inv_port.get_name() + "_" + std::to_string(pin) + "_")); /* Add the module nets to mux_mem_inv_nets cache */ mem_inv_net_cnt++; } From f002f7e30f66c3ba5e6a5b979423fb30b6d93896 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 14:17:09 -0600 Subject: [PATCH 316/482] add const 0 and 1 module Verilog generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 4 +- .../verilog/verilog_essential_gates.cpp | 37 +++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index acd88162e..97f5068a9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -956,11 +956,11 @@ std::string generate_fpga_top_netlist_name(const std::string& postfix) { ********************************************************************/ std::string generate_const_value_module_name(const size_t& const_val) { if (0 == const_val) { - return std::string("gnd"); + return std::string("const0"); } VTR_ASSERT (1 == const_val); - return std::string("vdd"); + return std::string("const1"); } /********************************************************************* diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index a00788b08..13cd62ada 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -13,6 +13,7 @@ /* FPGA-X2P context header files */ #include "fpga_x2p_utils.h" +#include "fpga_x2p_naming.h" #include "module_manager.h" #include "module_manager_utils.h" @@ -488,6 +489,36 @@ void print_verilog_gate_module(ModuleManager& module_manager, print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); } +/************************************************ + * Generate the Verilog netlist for a constant generator, + * i.e., either VDD or GND + ***********************************************/ +static +void print_verilog_constant_generator_module(const ModuleManager& module_manager, + std::fstream& fp, + const size_t& const_value) { + /* Find the module in module manager */ + std::string module_name = generate_const_value_module_name(const_value); + ModuleId const_val_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(const_val_module)); + + /* Ensure a valid file handler*/ + check_file_handler(fp); + + /* dump module definition + ports */ + print_verilog_module_declaration(fp, module_manager, const_val_module); + /* Finish dumping ports */ + + /* Find the only output*/ + for (const ModulePortId& module_port_id : module_manager.module_ports(const_val_module)) { + BasicPort module_port = module_manager.module_port(const_val_module, module_port_id); + print_verilog_wire_constant_values(fp, module_port, std::vector(1, const_value)); + } + + /* Put an end to the Verilog module */ + print_verilog_module_end(fp, module_name); +} + /************************************************ * Generate the Verilog netlist for essential gates * include inverters, buffers, transmission-gates, @@ -516,6 +547,12 @@ void print_verilog_submodule_essentials(ModuleManager& module_manager, print_verilog_include_defines_preproc_file(fp, verilog_dir); + /* Print constant generators */ + /* VDD */ + print_verilog_constant_generator_module(module_manager, fp, 0); + /* GND */ + print_verilog_constant_generator_module(module_manager, fp, 1); + for (const auto& circuit_model : circuit_lib.models()) { /* By pass user-defined modules */ if (!circuit_lib.model_verilog_netlist(circuit_model).empty()) { From 81093f0db6722c2a9a4f5215f2034e53d11d42e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 17:54:15 -0600 Subject: [PATCH 317/482] add lut module generation and simplify Verilog generation codes --- .../module_builder/build_lut_modules.cpp | 402 ++++++++++++++++++ .../module_builder/build_lut_modules.h | 13 + .../module_builder/build_module_graph.cpp | 4 +- .../build_module_graph_utils.cpp | 82 ++++ .../module_builder/build_module_graph_utils.h | 22 + .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 327 +------------- 6 files changed, 530 insertions(+), 320 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp new file mode 100644 index 000000000..c7057712b --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp @@ -0,0 +1,402 @@ +/******************************************************************** + * This file include functions that create modules for + * the Look-Up Tables (LUTs) + ********************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "util.h" +#include "spice_types.h" + +#include "fpga_x2p_naming.h" +#include "circuit_library_utils.h" +#include "module_manager.h" +#include "module_manager_utils.h" + +#include "build_module_graph_utils.h" +#include "build_lut_modules.h" + +/******************************************************************** + * Build a module for a LUT circuit model + * This function supports both single-output and fracturable LUTs + * The module will be organized in a connected graph of the following instances: + * 1. Multiplexer used inside LUT + * 2. Input buffers + * 3. Input inverters + * 4. Output buffers. + * 6. AND/OR gates to tri-state LUT inputs + ********************************************************************/ +static +void build_lut_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& lut_model) { + /* Get the global ports required by LUT + * Note that this function will only add global ports from LUT circuit model definition itself + * We should NOT go recursively here. + * The global ports of sub module will be handled by another function !!! + * add_module_global_ports_from_child_modules(module_manager, lut_module); + */ + std::vector lut_global_ports = circuit_lib.model_global_ports_by_type(lut_model, SPICE_MODEL_PORT_INPUT, false, true); + /* Get the input ports from the mux */ + std::vector lut_input_ports = circuit_lib.model_ports_by_type(lut_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the mux */ + std::vector lut_output_ports = circuit_lib.model_ports_by_type(lut_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */ + std::vector lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model); + std::vector lut_mode_select_sram_ports = find_circuit_mode_select_sram_ports(circuit_lib, lut_model); + + /*********************************************** + * Model Port Sanity Check + ***********************************************/ + /* Make sure that the number of ports and sizes of ports are what we want */ + if (false == circuit_lib.is_lut_fracturable(lut_model)) { + /* Single-output LUTs: + * We should have only 1 input port, 1 output port and 1 SRAM port + */ + VTR_ASSERT (1 == lut_input_ports.size()); + VTR_ASSERT (1 == lut_output_ports.size()); + VTR_ASSERT (1 == lut_regular_sram_ports.size()); + VTR_ASSERT (0 == lut_mode_select_sram_ports.size()); + } else { + VTR_ASSERT (true == circuit_lib.is_lut_fracturable(lut_model)); + /* Fracturable LUT: + * We should have only 1 input port, a few output ports (fracturable outputs) + * and two SRAM ports + */ + VTR_ASSERT (1 == lut_input_ports.size()); + VTR_ASSERT (1 <= lut_output_ports.size()); + VTR_ASSERT (1 == lut_regular_sram_ports.size()); + VTR_ASSERT (1 == lut_mode_select_sram_ports.size()); + } + + /*********************************************** + * Module Port addition + ***********************************************/ + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId lut_module = module_manager.add_module(circuit_lib.model_name(lut_model)); + VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); + /* Add module ports */ + /* Add each global port */ + for (const auto& port : lut_global_ports) { + /* Configure each global port */ + BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, global_port, ModuleManager::MODULE_GLOBAL_PORT); + } + /* Add each input port */ + for (const auto& port : lut_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, input_port, ModuleManager::MODULE_INPUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(lut_module, input_port.get_name(), true); + } + /* Add each output port */ + for (const auto& port : lut_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + /* Set the port to be wire-connection */ + module_manager.set_port_is_wire(lut_module, output_port.get_name(), true); + } + /* Add each regular (not mode select) SRAM port */ + for (const auto& port : lut_regular_sram_ports) { + BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* Add each mode-select SRAM port */ + for (const auto& port : lut_mode_select_sram_ports) { + BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); + module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); + } + + /*********************************************** + * Child module addition: Model-select gates + ***********************************************/ + /* Module nets after the mode-selection circuit, this could include LUT inputs */ + std::vector mode_selected_nets; + /* Instanciate mode selecting circuit: AND/OR gate + * By following the tri-state map of LUT input port + * The wiring of input ports will be organized as follows + * + * LUT input + * | + * v + * +----------+ + * | mode | + * | selector | + * +----------+ + * | mode_selected_nets + * v + * +-----------------+------------+ + * | | + * v v + * +----------+ +---------+ + * | Inverter | | Buffer | + * +----------+ +---------+ + * | inverter_output_net | buffered_output_net + * v v + * +--------------------------------------+ + * | LUT Multiplexing Structure | + * +--------------------------------------+ + */ + /* Get the tri-state port map for the input ports*/ + std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]); + size_t mode_select_port_lsb = 0; + for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { + ModulePortId lut_module_input_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(lut_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_input_port_id)); + + /* Create a module net for the connection */ + ModuleNetId net = module_manager.create_module_net(lut_module); + /* Set the source of the net to an lut input port */ + module_manager.add_module_net_source(lut_module, net, lut_module, 0, lut_module_input_port_id, pin); + + /* For an empty tri-state map or a '-' sign in tri-state map, we can short-wire mode select_output_ports */ + if (tri_state_map.empty() || ('-' == tri_state_map[pin]) ) { + /* Update the output nets of the mode-select layer */ + mode_selected_nets.push_back(net); + continue; /* Finish here */ + } + + e_spice_model_gate_type required_gate_type = NUM_SPICE_MODEL_GATE_TYPES; + /* Reach here, it means that we need a circuit for mode selection */ + if ('0' == tri_state_map[pin]) { + /* We need a 2-input AND gate, in order to tri-state the input + * Detailed circuit is as follow: + * +---------+ + * SRAM --->| 2-input |----> mode_select_output_port + * LUT input--->| AND | + * +---------+ + * When SRAM is set to logic 0, the LUT input is tri-stated + * When SRAM is set to logic 1, the LUT input is effective to the downstream circuits + */ + required_gate_type = SPICE_MODEL_GATE_AND; + } else { + VTR_ASSERT ('1' == tri_state_map[pin]); + /* We need a 2-input OR gate, in order to tri-state the input + * Detailed circuit is as follow: + * +---------+ + * SRAM --->| 2-input |----> mode_select_output_port + * LUT input--->| OR | + * +---------+ + * When SRAM is set to logic 1, the LUT input is tri-stated + * When SRAM is set to logic 0, the LUT input is effective to the downstream circuits + */ + required_gate_type = SPICE_MODEL_GATE_OR; + } + /* Get the circuit model of the gate */ + CircuitModelId gate_model = circuit_lib.port_tri_state_model(lut_input_ports[0]); + /* Check this is the gate we want ! */ + VTR_ASSERT (required_gate_type == circuit_lib.gate_type(gate_model)); + + /* Prepare for the gate instanciation */ + /* Get the input ports from the gate */ + std::vector gate_input_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the gate */ + std::vector gate_output_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Check the port sizes and width: + * we should have only 2 input ports, each of which has a size of 1 + * we should have only 1 output port, each of which has a size of 1 + */ + VTR_ASSERT (2 == gate_input_ports.size()); + VTR_ASSERT (1 == gate_output_ports.size()); + /* Find the module id of gate_model in the module manager */ + ModuleId gate_module = module_manager.find_module(circuit_lib.model_name(gate_model)); + /* We must have a valid id */ + VTR_ASSERT (true == module_manager.valid_module_id(gate_module)); + size_t gate_instance = module_manager.num_instance(lut_module, gate_module); + module_manager.add_child_module(lut_module, gate_module); + + /* Create a port-to-port net connection: + * Input[0] of the gate is wired to a SRAM mode-select port + * Input[1] of the gate is wired to the input port of LUT + * Output[0] of the gate is wired to the mode_select_output_port + */ + /* Create a module net for the connection */ + ModuleNetId gate_sram_net = module_manager.create_module_net(lut_module); + + /* Find the module port id of the SRAM port of LUT module */ + ModulePortId lut_module_mode_select_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(lut_mode_select_sram_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_mode_select_port_id)); + /* Set the source of the net to an mode-select SRAM port of the LUT module */ + module_manager.add_module_net_source(lut_module, gate_sram_net, lut_module, 0, lut_module_mode_select_port_id, mode_select_port_lsb); + + /* Find the module port id of the SRAM port of LUT module */ + ModulePortId gate_module_input0_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_lib_name(gate_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input0_port_id)); + /* Set the sink of the net to an input[0] port of the gate module */ + VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input0_port_id).get_width()); + for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input0_port_id).pins()) { + module_manager.add_module_net_sink(lut_module, gate_sram_net, gate_module, gate_instance, gate_module_input0_port_id, gate_pin); + } + + /* Use the existing net to connect to the input[1] port of the gate module */ + ModulePortId gate_module_input1_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_lib_name(gate_input_ports[1])); + VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input1_port_id)); + VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input1_port_id).get_width()); + for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input1_port_id).pins()) { + module_manager.add_module_net_sink(lut_module, net, gate_module, gate_instance, gate_module_input1_port_id, gate_pin); + } + + /* Create a module net for the output connection */ + ModuleNetId gate_output_net = module_manager.create_module_net(lut_module); + ModulePortId gate_module_output_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_lib_name(gate_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_output_port_id)); + BasicPort gate_module_output_port = module_manager.module_port(gate_module, gate_module_output_port_id); + VTR_ASSERT(1 == gate_module_output_port.get_width()); + module_manager.add_module_net_source(lut_module, gate_output_net, gate_module, gate_instance, gate_module_output_port_id, gate_module_output_port.get_lsb()); + + /* Update the output nets of the mode-select layer */ + mode_selected_nets.push_back(gate_output_net); + + /* update the lsb of mode select port size */ + mode_select_port_lsb++; + } + + /* Sanitity check */ + if ( true == circuit_lib.is_lut_fracturable(lut_model) ) { + if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Circuit model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n", + __FILE__, __LINE__, + circuit_lib.model_name(lut_model).c_str(), + tri_state_map.c_str(), + circuit_lib.port_size(lut_mode_select_sram_ports[0])); + exit(1); + } + } + + /*********************************************** + * Child module addition: Input inverters + ***********************************************/ + /* Find the circuit model of the input inverter */ + CircuitModelId input_inverter_model = circuit_lib.lut_input_inverter_model(lut_model); + VTR_ASSERT( CircuitModelId::INVALID() != input_inverter_model ); + + std::vector lut_mux_sram_inv_nets; + /* Now we need to add inverters by instanciating the modules */ + for (size_t pin = 0; pin < circuit_lib.port_size(lut_input_ports[0]); ++pin) { + ModuleNetId lut_mux_sram_inv_net = add_inverter_buffer_child_module_and_nets(module_manager, lut_module, + circuit_lib, input_inverter_model, + mode_selected_nets[pin]); + /* Update the net vector */ + lut_mux_sram_inv_nets.push_back(lut_mux_sram_inv_net); + } + + /*********************************************** + * Child module addition: Input buffers + ***********************************************/ + /* Add buffers to mode_select output ports */ + /* Find the circuit model of the input inverter */ + CircuitModelId input_buffer_model = circuit_lib.lut_input_buffer_model(lut_model); + VTR_ASSERT( CircuitModelId::INVALID() != input_buffer_model ); + + std::vector lut_mux_sram_nets; + /* Now we need to add inverters by instanciating the modules and add module nets */ + for (size_t pin = 0; pin < circuit_lib.port_size(lut_input_ports[0]); ++pin) { + ModuleNetId lut_mux_sram_net = add_inverter_buffer_child_module_and_nets(module_manager, lut_module, + circuit_lib, input_buffer_model, + mode_selected_nets[pin]); + /* Update the net vector */ + lut_mux_sram_nets.push_back(lut_mux_sram_net); + } + + /*********************************************** + * Child module addition: LUT MUX + ***********************************************/ + /* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */ + std::string lut_mux_module_name = generate_mux_subckt_name(circuit_lib, lut_model, size_t(-1), std::string("")); + /* Find the module id of LUT MUX in the module manager */ + ModuleId lut_mux_module = module_manager.find_module(lut_mux_module_name); + /* We must have a valid id */ + VTR_ASSERT (ModuleId::INVALID() != lut_mux_module); + /* Instanciate a LUT MUX as child module */ + size_t lut_mux_instance = module_manager.num_instance(lut_module, lut_mux_module); + module_manager.add_child_module(lut_module, lut_mux_module); + + /* TODO: Build module nets to connect + * 1. SRAM ports of LUT MUX module to output ports of input buffer + * 2. Inverted SRAM ports of LUT MUX module to output ports of input inverters + * 3. Data input of LUT MUX module to SRAM port of LUT + * 4. Data output of LUT MUX module to output ports of LUT + */ + ModulePortId lut_mux_sram_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_lib_name(lut_regular_sram_ports[0])); + BasicPort lut_mux_sram_port = module_manager.module_port(lut_mux_module, lut_mux_sram_port_id); + VTR_ASSERT(lut_mux_sram_port.get_width() == lut_mux_sram_nets.size()); + /* Wire the port to lut_mux_sram_net */ + for (const size_t& pin : lut_mux_sram_port.pins()) { + module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin); + } + + ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_lib_name(lut_regular_sram_ports[0]) + "_inv")); + BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id); + VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size()); + /* Wire the port to lut_mux_sram_net */ + for (const size_t& pin : lut_mux_sram_inv_port.pins()) { + module_manager.add_module_net_sink(lut_module, lut_mux_sram_inv_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_inv_port_id, pin); + } + + /* lut_module + * +------------ + * | +------ + * sram -->|---->| (lut_mux_input_port) + * | ^ | LUT MUX + * | | | + * | + * net + */ + ModulePortId lut_sram_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(lut_regular_sram_ports[0])); + BasicPort lut_sram_port = module_manager.module_port(lut_module, lut_sram_port_id); + ModulePortId lut_mux_input_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_lib_name(lut_input_ports[0])); + BasicPort lut_mux_input_port = module_manager.module_port(lut_mux_module, lut_mux_input_port_id); + VTR_ASSERT(lut_mux_input_port.get_width() == lut_sram_port.get_width()); + /* Wire the port to lut_mux_sram_net */ + for (size_t pin_id = 0; pin_id < lut_mux_input_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(lut_module); + module_manager.add_module_net_source(lut_module, net, lut_module, 0, lut_sram_port_id, lut_sram_port.pins()[pin_id]); + module_manager.add_module_net_sink(lut_module, net, lut_mux_module, lut_mux_instance, lut_mux_input_port_id, lut_mux_input_port.pins()[pin_id]); + } + + for (const auto& port : lut_output_ports) { + ModulePortId lut_output_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(port)); + BasicPort lut_output_port = module_manager.module_port(lut_module, lut_output_port_id); + ModulePortId lut_mux_output_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_lib_name(port)); + BasicPort lut_mux_output_port = module_manager.module_port(lut_mux_module, lut_mux_output_port_id); + VTR_ASSERT(lut_mux_output_port.get_width() == lut_output_port.get_width()); + /* Wire the port to lut_mux_sram_net */ + for (size_t pin_id = 0; pin_id < lut_output_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(lut_module); + module_manager.add_module_net_source(lut_module, net, lut_mux_module, lut_mux_instance, lut_mux_output_port_id, lut_mux_output_port.pins()[pin_id]); + module_manager.add_module_net_sink(lut_module, net, lut_module, 0, lut_output_port_id, lut_output_port.pins()[pin_id]); + } + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, lut_module); +} + +/******************************************************************** + * Print Verilog modules for the Look-Up Tables (LUTs) + * in the circuit library + ********************************************************************/ +void build_lut_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib) { + + /* Search for each LUT circuit model */ + for (const auto& lut_model : circuit_lib.models()) { + /* Bypas non-LUT modules */ + if (SPICE_MODEL_LUT != circuit_lib.model_type(lut_model)) { + continue; + } + build_lut_module(module_manager, circuit_lib, lut_model); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h new file mode 100644 index 000000000..68990d2cc --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h @@ -0,0 +1,13 @@ +/******************************************************************** + * Header file for build_lut_modules.cpp + ********************************************************************/ +#ifndef BUILD_LUT_MODULES_H +#define BUILD_LUT_MODULES_H + +#include "circuit_library.h" +#include "module_manager.h" + +void build_lut_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index c97f031ba..36b23e401 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -13,6 +13,7 @@ #include "build_essential_modules.h" #include "build_decoder_modules.h" #include "build_mux_modules.h" +#include "build_lut_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -86,7 +87,8 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, /* Build multiplexer modules */ build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib); - /* TODO: Build LUT modules */ + /* Build LUT modules */ + build_lut_modules(module_manager, arch.spice->circuit_lib); /* TODO: Build wire modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp new file mode 100644 index 000000000..6b1df195a --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp @@ -0,0 +1,82 @@ +/******************************************************************** + * This file includes most utilized functions that are used to + * build module graphs + ********************************************************************/ +#include +#include "vtr_assert.h" + +#include "build_module_graph_utils.h" + +/******************************************************************** + * Find input port of a buffer/inverter module + ********************************************************************/ +ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& model_id, + const e_spice_model_port_type& port_type) { + /* We must have a valid module id */ + VTR_ASSERT(true == module_manager.valid_module_id(module_id)); + /* Check the type of model */ + VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_lib.model_type(model_id)); + + /* Add module nets to wire to the buffer module */ + /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ + std::vector model_ports = circuit_lib.model_ports_by_type(model_id, port_type, true); + VTR_ASSERT(1 == model_ports.size()); + + /* Find the input and output module ports */ + ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(model_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id)); + + return module_port_id; +} + +/******************************************************************** + * Add inverter/buffer module to a parent module + * and complete the wiring to the input port of inverter/buffer + * This function will return the wire created for the output port of inverter/buffer + * + * parent_module + * +----------------------------------------------------------------- + * | + * | input_net output_net + * | | | + * | v +---------------+ v + * | src_module_port --------->| child_module |--------> + * | +---------------+ + * + ********************************************************************/ +ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager, + const ModuleId& parent_module, + const CircuitLibrary& circuit_lib, + const CircuitModelId& model_id, + const ModuleNetId& input_net) { + /* We must have a valid module id */ + VTR_ASSERT(true == module_manager.valid_module_id(parent_module)); + + std::string module_name = circuit_lib.model_name(model_id); + ModuleId child_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(child_module)); + + ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, SPICE_MODEL_PORT_INPUT); + ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, SPICE_MODEL_PORT_OUTPUT); + + /* Port size should be 1 ! */ + VTR_ASSERT(1 == module_manager.module_port(child_module, module_input_port_id).get_width()); + VTR_ASSERT(1 == module_manager.module_port(child_module, module_output_port_id).get_width()); + + /* Instanciate a child module */ + size_t child_instance = module_manager.num_instance(parent_module, child_module); + module_manager.add_child_module(parent_module, child_module); + + /* Use the net to connect to the input net of buffer */ + module_manager.add_module_net_sink(parent_module, input_net, child_module, child_instance, module_input_port_id, 0); + + /* Create a net to bridge the input inverter and LUT MUX */ + ModuleNetId output_net = module_manager.create_module_net(parent_module); + module_manager.add_module_net_source(parent_module, output_net, child_module, child_instance, module_output_port_id, 0); + + return output_net; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h new file mode 100644 index 000000000..e5b3de2ca --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h @@ -0,0 +1,22 @@ +/******************************************************************** + * Header file for build_module_graph_utils.cpp + ********************************************************************/ +#ifndef BUILD_MODULE_GRAPH_UTILS_H +#define BUILD_MODULE_GRAPH_UTILS_H + +#include "module_manager.h" +#include "circuit_library.h" + +ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, + const ModuleId& module_id, + const CircuitLibrary& circuit_lib, + const CircuitModelId& model_id, + const e_spice_model_port_type& port_type); + +ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager, + const ModuleId& parent_module, + const CircuitLibrary& circuit_lib, + const CircuitModelId& model_id, + const ModuleNetId& input_net); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 50f924c32..b5fa63060 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -20,324 +20,10 @@ #include "fpga_x2p_utils.h" /* FPGA-Verilog context header files */ -#include "verilog_global.h" #include "verilog_writer_utils.h" -#include "verilog_submodule_utils.h" +#include "verilog_module_writer.h" #include "verilog_lut.h" -/******************************************************************** - * Print a Verilog module for a LUT circuit model - * This function supports both single-output and fracturable LUTs - * The Verilog module will be organized in structural Verilog codes. - * It will instanciate: - * 1. Multiplexer used inside LUT - * 2. Input buffers - * 3. Input inverters - * 4. Output buffers. - * 6. AND/OR gates to tri-state LUT inputs - ********************************************************************/ -static -void print_verilog_submodule_lut(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& circuit_model) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Get the global ports required by MUX (and any submodules) */ - std::vector lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - /* Get the input ports from the mux */ - std::vector lut_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector lut_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */ - std::vector lut_regular_sram_ports; - std::vector lut_mode_select_sram_ports; - - { /* Create a code block to keep some variables in local */ - /* Get the sram ports from the mux */ - std::vector lut_sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); - for (const auto& port : lut_sram_ports) { - /* Bypass mode_select ports */ - if (true == circuit_lib.port_is_mode_select(port)) { - lut_mode_select_sram_ports.push_back(port); - continue; - } - VTR_ASSERT_SAFE (false == circuit_lib.port_is_mode_select(port)); - lut_regular_sram_ports.push_back(port); - } - } - - /* Make sure that the number of ports and sizes of ports are what we want */ - if (false == circuit_lib.is_lut_fracturable(circuit_model)) { - /* Single-output LUTs: - * We should have only 1 input port, 1 output port and 1 SRAM port - */ - VTR_ASSERT (1 == lut_input_ports.size()); - VTR_ASSERT (1 == lut_output_ports.size()); - VTR_ASSERT (1 == lut_regular_sram_ports.size()); - VTR_ASSERT (0 == lut_mode_select_sram_ports.size()); - } else { - VTR_ASSERT (true == circuit_lib.is_lut_fracturable(circuit_model)); - /* Fracturable LUT: - * We should have only 1 input port, a few output ports (fracturable outputs) - * and two SRAM ports - */ - VTR_ASSERT (1 == lut_input_ports.size()); - VTR_ASSERT (1 <= lut_output_ports.size()); - VTR_ASSERT (1 == lut_regular_sram_ports.size()); - VTR_ASSERT (1 == lut_mode_select_sram_ports.size()); - } - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(circuit_lib.model_name(circuit_model)); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : lut_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - for (const auto& port : lut_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, input_port.get_name(), true); - } - /* Add each output port */ - for (const auto& port : lut_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, output_port.get_name(), true); - } - /* Add each regular (not mode select) SRAM port */ - for (const auto& port : lut_regular_sram_ports) { - BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); - module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* Add each mode-select SRAM port */ - for (const auto& port : lut_mode_select_sram_ports) { - BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); - module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - - /* Print local wires for mode selector */ - /* Local wires for the output of mode selector */ - BasicPort mode_select_output_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_mode"), circuit_lib.port_size(lut_input_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, mode_select_output_port) << ";" << std::endl; - /* Local wires for the output of input inverters */ - BasicPort inverted_input_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_b"), circuit_lib.port_size(lut_input_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, inverted_input_port) << ";" << std::endl; - /* Local wires for the output of input buffers */ - BasicPort buffered_input_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_buf"), circuit_lib.port_size(lut_input_ports[0])); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, buffered_input_port) << ";" << std::endl; - - /* Instanciate mode selecting circuit: AND/OR gate - * By following the tri-state map of LUT input port - * The wiring of input ports will be organized as follows - * - * LUT input - * | - * v - * +----------+ - * | mode | - * | selector | - * +----------+ - * | mode_select_output_port - * +-----------------+------------+ - * | | - * +----------+ +---------+ - * | Inverter | | Buffer | - * +----------+ +---------+ - * | inverter_input_port | buffered_input_port - * v v - * +--------------------------------------+ - * | LUT Multiplexing Structure | - * +--------------------------------------+ - */ - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of model-select gates -----")); - /* Get the tri-state port map for the input ports*/ - std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]); - size_t mode_select_port_lsb = 0; - for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { - BasicPort cur_mode_select_output_port(mode_select_output_port.get_name(), pin, pin); - BasicPort cur_input_port(circuit_lib.port_lib_name(lut_input_ports[0]), pin, pin); - /* For an empty tri-state map or a '-' sign in tri-state map, we can short-wire mode select_output_ports */ - if (tri_state_map.empty() || ('-' == tri_state_map[pin]) ) { - print_verilog_wire_connection(fp, cur_mode_select_output_port, cur_input_port, false); - continue; /* Finish here */ - } - /* Reach here, it means that we need a circuit for mode selection */ - BasicPort cur_lut_mode_select_sram_port(circuit_lib.port_lib_name(lut_mode_select_sram_ports[0]), mode_select_port_lsb, mode_select_port_lsb); - enum e_spice_model_gate_type required_gate_type; - if ('0' == tri_state_map[pin]) { - /* We need a 2-input AND gate, in order to tri-state the input - * Detailed circuit is as follow: - * +---------+ - * SRAM --->| 2-input |----> mode_select_output_port - * LUT input--->| AND | - * +---------+ - * When SRAM is set to logic 0, the LUT input is tri-stated - * When SRAM is set to logic 1, the LUT input is effective to the downstream circuits - */ - required_gate_type = SPICE_MODEL_GATE_AND; - } else { - VTR_ASSERT ('1' == tri_state_map[pin]); - /* We need a 2-input OR gate, in order to tri-state the input - * Detailed circuit is as follow: - * +---------+ - * SRAM --->| 2-input |----> mode_select_output_port - * LUT input--->| OR | - * +---------+ - * When SRAM is set to logic 1, the LUT input is tri-stated - * When SRAM is set to logic 0, the LUT input is effective to the downstream circuits - */ - required_gate_type = SPICE_MODEL_GATE_OR; - } - /* Get the circuit model of the gate */ - CircuitModelId gate_model = circuit_lib.port_tri_state_model(lut_input_ports[0]); - /* Check this is the gate we want ! */ - VTR_ASSERT (required_gate_type == circuit_lib.gate_type(gate_model)); - - /* Prepare for the gate instanciation */ - /* Get the input ports from the gate */ - std::vector gate_input_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the gate */ - std::vector gate_output_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Check the port sizes and width: - * we should have only 2 input ports, each of which has a size of 1 - * we should have only 1 output port, each of which has a size of 1 - */ - VTR_ASSERT (2 == gate_input_ports.size()); - for (const auto& port : gate_input_ports) { - VTR_ASSERT (1 == circuit_lib.port_size(port)); - } - VTR_ASSERT (1 == gate_output_ports.size()); - for (const auto& port : gate_output_ports) { - VTR_ASSERT (1 == circuit_lib.port_size(port)); - } - /* Find the module id of gate_model in the module manager */ - ModuleId gate_module_id = module_manager.find_module(circuit_lib.model_name(gate_model)); - /* We must have a valid id */ - VTR_ASSERT (ModuleId::INVALID() != gate_module_id); - /* Create a port-to-port map: - * Input[0] of the gate is wired to a SRAM mode-select port - * Input[1] of the gate is wired to the input port of LUT - * Output[0] of the gate is wired to the mode_select_output_port - */ - std::map port2port_name_map; - port2port_name_map[circuit_lib.port_lib_name(gate_input_ports[0])] = cur_lut_mode_select_sram_port; - port2port_name_map[circuit_lib.port_lib_name(gate_input_ports[1])] = cur_input_port; - port2port_name_map[circuit_lib.port_lib_name(gate_output_ports[0])] = cur_mode_select_output_port; - - /* Instanciate the gate */ - print_verilog_module_instance(fp, module_manager, module_id, gate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, gate_module_id); - /* update the lsb of mode select port size */ - mode_select_port_lsb++; - } - print_verilog_comment(fp, std::string("---- END Instanciation of model-select gates -----")); - /* Sanitity check */ - if ( true == circuit_lib.is_lut_fracturable(circuit_model) ) { - if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Circuit model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n", - __FILE__, __LINE__, - circuit_lib.model_name(circuit_model).c_str(), - tri_state_map.c_str(), - circuit_lib.port_size(lut_mode_select_sram_ports[0])); - exit(1); - } - } - - /* Add a blank-line splitter */ - fp << std::endl; - - /* Add inverters to mode_select output ports */ - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input inverters modules -----")); - /* Find the circuit model of the input inverter */ - CircuitModelId input_inverter_model = circuit_lib.lut_input_inverter_model(circuit_model); - VTR_ASSERT( CircuitModelId::INVALID() != input_inverter_model ); - /* Now we need to add inverters by instanciating the modules */ - for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { - /* Input of inverter is the output of mode select circuits */ - BasicPort inverter_instance_input_port(mode_select_output_port.get_name(), pin, pin); - /* Output of inverter is the inverted input port */ - BasicPort inverter_instance_output_port(inverted_input_port.get_name(), pin, pin); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, input_inverter_model, inverter_instance_input_port, inverter_instance_output_port); - } - print_verilog_comment(fp, std::string("---- END Instanciation of an input inverters modules -----")); - - /* Add buffers to mode_select output ports */ - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input buffer modules -----")); - /* Find the circuit model of the input inverter */ - CircuitModelId input_buffer_model = circuit_lib.lut_input_buffer_model(circuit_model); - VTR_ASSERT( CircuitModelId::INVALID() != input_buffer_model ); - /* Now we need to add inverters by instanciating the modules */ - for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { - /* Input of inverter is the output of mode select circuits */ - BasicPort buffer_instance_input_port(mode_select_output_port.get_name(), pin, pin); - /* Output of inverter is the inverted input port */ - BasicPort buffer_instance_output_port(buffered_input_port.get_name(), pin, pin); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, input_buffer_model, buffer_instance_input_port, buffer_instance_output_port); - } - print_verilog_comment(fp, std::string("---- END Instanciation of an input buffer modules -----")); - - /* Instanciate the multiplexing structure for the LUT */ - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of LUT multiplexer module -----")); - /* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */ - std::string lut_mux_module_name = generate_mux_subckt_name(circuit_lib, circuit_model, size_t(-1), std::string("")); - /* Find the module id of LUT MUX in the module manager */ - ModuleId lut_mux_module_id = module_manager.find_module(lut_mux_module_name); - /* We must have a valid id */ - VTR_ASSERT (ModuleId::INVALID() != lut_mux_module_id); - /* Create a port-to-port map: - * Input of the LUT MUX is wired to a regular SRAM port of LUT - * Outputs of the LUT MUX is wired to the output ports of LUT by name - * SRAM of the LUT MUX is wired to the buffered input port of LUT - * SRAM_inv of the LUT MUX is wired to the inverted input port of LUT - */ - std::map port2port_name_map; - port2port_name_map[circuit_lib.port_lib_name(lut_input_ports[0])] = BasicPort(circuit_lib.port_lib_name(lut_regular_sram_ports[0]), circuit_lib.port_size(lut_regular_sram_ports[0])); - /* Skip the output ports, if we do not need a new name for the port of instance */ - port2port_name_map[circuit_lib.port_lib_name(lut_regular_sram_ports[0])] = buffered_input_port; - /* TODO: be more flexible in naming !!! */ - port2port_name_map[std::string(circuit_lib.port_lib_name(lut_regular_sram_ports[0]) + "_inv")] = inverted_input_port; - - /* Instanciate the gate */ - print_verilog_module_instance(fp, module_manager, module_id, lut_mux_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, lut_mux_module_id); - - /* Print timing info */ - print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); -} - /******************************************************************** * Print Verilog modules for the Look-Up Tables (LUTs) * in the circuit library @@ -366,13 +52,16 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, print_verilog_include_defines_preproc_file(fp, verilog_dir); /* Search for each LUT circuit model */ - for (const auto& circuit_model : circuit_lib.models()) { + for (const auto& lut_model : circuit_lib.models()) { /* Bypass user-defined and non-LUT modules */ - if ( (!circuit_lib.model_verilog_netlist(circuit_model).empty()) - || (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) ) { + if ( (!circuit_lib.model_verilog_netlist(lut_model).empty()) + || (SPICE_MODEL_LUT != circuit_lib.model_type(lut_model)) ) { continue; } - print_verilog_submodule_lut(module_manager, circuit_lib, fp, circuit_model); + /* Find the module id */ + ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model)); + VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); + write_verilog_module_to_file(fp, module_manager, lut_module, circuit_lib.dump_explicit_port_map(lut_model)); } /* Close the file handler */ From c076da9bab77773773a6a08d2ec833c51f4f0b5a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 18:48:34 -0600 Subject: [PATCH 318/482] remove redundant codes --- .../module_builder/build_mux_modules.cpp | 134 ++---------------- 1 file changed, 9 insertions(+), 125 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index ca7aca309..7f9db8293 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -20,6 +20,7 @@ #include "circuit_library_utils.h" #include "decoder_library_utils.h" #include "module_manager_utils.h" +#include "build_module_graph_utils.h" /* FPGA-X2P context header files */ #include "spice_types.h" @@ -524,40 +525,9 @@ void build_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_man CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(mux_model); /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); - - /* Find the instance id */ - size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); - /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, buffer_module_id); - /* Set a name for the instance */ - std::string buffer_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, true); - module_manager.set_child_instance_name(mux_module, buffer_module_id, buffer_instance_id, buffer_instance_name); - - /* Add module nets to wire to the buffer module */ - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); - - /* Find the input and output module ports */ - ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); - ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); - - /* Port size should be 1 ! */ - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); - - /* Connect the module net from branch output to buffer input */ - module_manager.add_module_net_sink(mux_module, branch_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); /* Create a module net which sources from buffer output */ - ModuleNetId buffer_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + ModuleNetId buffer_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, branch_net); /* Record the module net id in the cache */ module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net; @@ -718,40 +688,8 @@ void build_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_ma CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); - /* Find the instance id */ - size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); - /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, buffer_module_id); - /* Set a name for the instance */ - std::string buffer_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, true); - module_manager.set_child_instance_name(mux_module, buffer_module_id, buffer_instance_id, buffer_instance_name); - - /* Add module nets to wire to the buffer module */ - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); - - /* Find the input and output module ports */ - ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); - ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); - - /* Port size should be 1 ! */ - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); - - /* Connect the module net from branch output to buffer input */ - module_manager.add_module_net_sink(mux_module, branch_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); - - /* Create a module net which sources from buffer output */ - ModuleNetId buffer_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + ModuleNetId buffer_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, branch_net); /* Record the module net id in the cache */ module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net; @@ -854,39 +792,13 @@ vtr::vector build_mux_module_input_buffers(ModuleManage CircuitModelId buffer_model = circuit_lib.input_buffer_model(mux_model); /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); - - /* Find the instance id */ - size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); - /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, buffer_module_id); - - /* Add module nets to wire to the buffer module */ - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); - - /* Find the input and output module ports */ - ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); - ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); - - /* Port size should be 1 ! */ - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); /* Connect the module net from branch output to buffer input */ ModuleNetId buffer_net = module_manager.create_module_net(mux_module); module_manager.add_module_net_source(mux_module, buffer_net, mux_module, 0, module_input_port_id, size_t(input_index)); - module_manager.add_module_net_sink(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); /* Create a module net which sources from buffer output */ - ModuleNetId input_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, input_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); + ModuleNetId input_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, buffer_net); mux_input_nets[input_index] = input_net; } @@ -988,40 +900,12 @@ vtr::vector build_mux_module_output_buffers(ModuleMana CircuitModelId buffer_model = circuit_lib.output_buffer_model(mux_model); /* We must have a valid model id */ VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); - - /* Find the instance id */ - size_t buffer_instance_id = module_manager.num_instance(mux_module, buffer_module_id); - /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, buffer_module_id); - - /* Add module nets to wire to the buffer module */ - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); - - /* Find the input and output module ports */ - ModulePortId buffer_input_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_input_ports[0])); - ModulePortId buffer_output_port_id = module_manager.find_module_port(buffer_module_id, circuit_lib.port_lib_name(buffer_model_output_ports[0])); - - /* Port size should be 1 ! */ - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_input_port_id).get_width()); - VTR_ASSERT(1 == module_manager.module_port(buffer_module_id, buffer_output_port_id).get_width()); - - /* Connect the module net from buffer output to MUX output */ - ModuleNetId buffer_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, buffer_net, buffer_module_id, buffer_instance_id, buffer_output_port_id, module_manager.module_port(buffer_module_id, buffer_output_port_id).get_lsb()); - module_manager.add_module_net_sink(mux_module, buffer_net, mux_module, 0, module_output_port_id, pin); - + /* Create a module net which sinks at buffer input */ - ModuleNetId output_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_sink(mux_module, output_net, buffer_module_id, buffer_instance_id, buffer_input_port_id, module_manager.module_port(buffer_module_id, buffer_input_port_id).get_lsb()); - mux_output_nets[output_index] = output_net; + ModuleNetId input_net = module_manager.create_module_net(mux_module); + ModuleNetId output_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, output_net); + module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin); + mux_output_nets[output_index] = input_net; } } From 3cf7950bc1e96171b75035d3ae4481660c1c2109 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 21 Oct 2019 20:20:34 -0600 Subject: [PATCH 319/482] add wire module generation and simplify Verilog generation for wires --- .../module_builder/build_module_graph.cpp | 4 +- .../module_builder/build_wire_modules.cpp | 134 ++++++++++++++++++ .../module_builder/build_wire_modules.h | 20 +++ .../vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp | 29 ++-- 4 files changed, 173 insertions(+), 14 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index 36b23e401..d4196672d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -14,6 +14,7 @@ #include "build_decoder_modules.h" #include "build_mux_modules.h" #include "build_lut_modules.h" +#include "build_wire_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -90,7 +91,8 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, /* Build LUT modules */ build_lut_modules(module_manager, arch.spice->circuit_lib); - /* TODO: Build wire modules */ + /* Build wire modules */ + build_wire_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); /* TODO: Build memory modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp new file mode 100644 index 000000000..020329e63 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp @@ -0,0 +1,134 @@ +/*********************************************** + * This file includes functions to generate + * Verilog submodules for wires. + **********************************************/ +#include +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "module_manager.h" +#include "module_manager_utils.h" +#include "physical_types.h" +#include "vpr_types.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "build_wire_modules.h" + +/******************************************************************** + * Print a Verilog module of a regular wire segment + * Regular wire, which is 1-input and 1-output + * This type of wires are used in the local routing architecture + * +------+ + * input --->| wire |---> output + * +------+ + * + *******************************************************************/ +static +void build_wire_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& wire_model) { + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); + std::vector global_ports = circuit_lib.model_global_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true, true); + + /* Makre sure the port size is what we want */ + VTR_ASSERT (1 == input_ports.size()); + VTR_ASSERT (1 == output_ports.size()); + VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); + VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); +} + +/******************************************************************** + * Build module of a routing track wire segment + * Routing track wire, which is 1-input and dual output + * This type of wires are used in the global routing architecture. + * One of the output is wired to another Switch block multiplexer, + * while the mid-output is wired to a Connection block multiplexer. + * + * | CLB | + * +------------+ + * ^ + * | + * +------------------------------+ + * | Connection block multiplexer | + * +------------------------------+ + * ^ + * | mid-output +-------------- + * +--------------------+ | + * input --->| Routing track wire |--------->| Switch Block + * +--------------------+ output | + * +-------------- + * + *******************************************************************/ +static +void build_routing_wire_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const CircuitModelId& wire_model, + const std::string& wire_subckt_name) { + /* Find the input port, output port*/ + std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); + std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Make sure the port size is what we want */ + VTR_ASSERT (1 == input_ports.size()); + VTR_ASSERT (1 == output_ports.size()); + VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); + VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId wire_module = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model, wire_subckt_name); + + /* Add a mid-output port to the module */ + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + module_manager.add_port(wire_module, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); +} + +/******************************************************************** + * This function will only create wire modules with a number of + * ports that are defined by users. + * It will NOT insert any internal logic, which should be handled + * by Verilog/SPICE writers + *******************************************************************/ +void build_wire_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::vector routing_segments) { + /* Print Verilog models for regular wires*/ + for (const auto& wire_model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) { + /* Bypass user-defined circuit models */ + if ( (!circuit_lib.model_spice_netlist(wire_model).empty()) + && (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) { + continue; + } + build_wire_module(module_manager, circuit_lib, wire_model); + } + + for (const auto& seg : routing_segments) { + VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); + VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); + /* Bypass user-defined circuit models */ + if ( (!circuit_lib.model_spice_netlist(seg.circuit_model).empty()) + && (!circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) ) { + continue; + } + /* Give a unique name for subckt of wire_model of segment, + * circuit_model name is unique, and segment id is unique as well + */ + std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); + + /* Print a Verilog module */ + build_routing_wire_module(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h new file mode 100644 index 000000000..a68eb22b0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h @@ -0,0 +1,20 @@ +/*********************************************** + * Header file for verilog_wire.cpp + **********************************************/ + +#ifndef BUILD_WIRE_MODULES_H +#define BUILD_WIRE_MODULES_H + +/* Include other header files which are dependency on the function declared below */ +#include +#include "physical_types.h" +#include "vpr_types.h" + +#include "circuit_library.h" +#include "module_manager.h" + +void build_wire_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + std::vector routing_segments); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp index 4506aa106..b8b9443bc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp @@ -54,22 +54,23 @@ void print_verilog_wire_module(ModuleManager& module_manager, VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); + ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(wire_model)); + VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); + print_verilog_module_declaration(fp, module_manager, wire_module); /* Finish dumping ports */ /* Print the internal logic of Verilog module */ /* Find the input port of the module */ - ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(input_ports[0])); + ModulePortId module_input_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(input_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); + BasicPort module_input_port = module_manager.module_port(wire_module, module_input_port_id); /* Find the output port of the module */ - ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(output_ports[0])); + ModulePortId module_output_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(output_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); + BasicPort module_output_port = module_manager.module_port(wire_module, module_output_port_id); /* Print wire declaration for the inputs and outputs */ fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl; @@ -130,26 +131,28 @@ void print_verilog_routing_wire_module(ModuleManager& module_manager, VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model, wire_subckt_name); + ModuleId wire_module = module_manager.find_module(wire_subckt_name); + VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); /* Add a mid-output port to the module */ BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); - module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); + ModulePortId module_mid_output_port_id = module_manager.find_module_port(wire_module, module_mid_output_port.get_name()); + VTR_ASSERT(ModulePortId::INVALID() != module_mid_output_port_id); /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); + print_verilog_module_declaration(fp, module_manager, wire_module); /* Finish dumping ports */ /* Print the internal logic of Verilog module */ /* Find the input port of the module */ - ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(input_ports[0])); + ModulePortId module_input_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(input_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); + BasicPort module_input_port = module_manager.module_port(wire_module, module_input_port_id); /* Find the output port of the module */ - ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(output_ports[0])); + ModulePortId module_output_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(output_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); + BasicPort module_output_port = module_manager.module_port(wire_module, module_output_port_id); /* Print wire declaration for the inputs and outputs */ fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl; From 9cf8683acdb2dfb6b30f3e4e7892bb3b9205504c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Oct 2019 15:31:08 -0600 Subject: [PATCH 320/482] add module generation for memories --- .../fpga_x2p/base/module_manager_utils.cpp | 5 +- .../module_builder/build_memory_modules.cpp | 685 ++++++++++++++++++ .../module_builder/build_memory_modules.h | 20 + .../module_builder/build_module_graph.cpp | 5 +- .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 6 +- .../vpr/SRC/fpga_x2p/verilog/verilog_lut.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 439 +---------- .../vpr/SRC/fpga_x2p/verilog/verilog_memory.h | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 19 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 11 +- 11 files changed, 762 insertions(+), 438 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index f7e6b7c8b..ac5561032 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -565,7 +565,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man } } -/* Connect all the memory modules under the parent module in a chain +/******************************************************************** + * Connect all the memory modules under the parent module in a chain * * +--------+ +--------+ +--------+ * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail @@ -579,7 +580,7 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man * For the rest of memory modules: * net source is the configuration chain tail of the previous memory module * net sink is the configuration chain head of the next memory module - */ + *********************************************************************/ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, const std::vector& memory_modules, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp new file mode 100644 index 000000000..25cc6d877 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -0,0 +1,685 @@ +/********************************************************************* + * This file includes functions to generate Verilog submodules for + * the memories that are affiliated to multiplexers and other programmable + * circuit models, such as IOPADs, LUTs, etc. + ********************************************************************/ +#include +#include + +#include "util.h" +#include "vtr_assert.h" + +/* Device-level header files */ +#include "mux_graph.h" +#include "module_manager.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "circuit_library_utils.h" +#include "module_manager_utils.h" +#include "mux_utils.h" + +/* FPGA-X2P context header files */ +#include "spice_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +/* FPGA-Verilog context header files */ +#include "verilog_global.h" +#include "build_memory_modules.h" + +/********************************************************************* + * Add module nets to connect an input port of a memory module to + * an input port of its child module + * Restriction: this function is really designed for memory modules + * 1. It assumes that input port name of child module is the same as memory module + * 2. It assumes exact pin-to-pin mapping: + * j-th pin of input port of the i-th child module is wired to the j + i*W -th + * pin of input port of the memory module, where W is the size of port + ********************************************************************/ +static +void add_module_input_nets_to_mem_modules(ModuleManager& module_manager, + const ModuleId& mem_module, + const CircuitLibrary& circuit_lib, + const std::vector& circuit_ports, + const ModuleId& child_module, + const size_t& child_index, + const size_t& child_instance) { + /* Wire inputs of parent module to inputs of child modules */ + for (const auto& port : circuit_ports) { + ModulePortId src_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_lib_name(port)); + ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(port)); + for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(mem_module); + /* Source pin is shifted by the number of memories */ + size_t src_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, src_port_id).pins()[pin_id]; + /* Source node of the input net is the input of memory module */ + module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id); + /* Sink node of the input net is the input of sram module */ + size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id]; + module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id); + } + } +} + +/********************************************************************* + * Add module nets to connect an output port of a memory module to + * an output port of its child module + * Restriction: this function is really designed for memory modules + * 1. It assumes that output port name of child module is the same as memory module + * 2. It assumes exact pin-to-pin mapping: + * j-th pin of output port of the i-th child module is wired to the j + i*W -th + * pin of output port of the memory module, where W is the size of port + ********************************************************************/ +static +void add_module_output_nets_to_mem_modules(ModuleManager& module_manager, + const ModuleId& mem_module, + const CircuitLibrary& circuit_lib, + const std::vector& circuit_ports, + const ModuleId& child_module, + const size_t& child_index, + const size_t& child_instance) { + /* Wire inputs of parent module to inputs of child modules */ + for (const auto& port : circuit_ports) { + ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(port)); + ModulePortId sink_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_lib_name(port)); + for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(mem_module); + /* Source pin is shifted by the number of memories */ + size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id]; + /* Source node of the input net is the input of memory module */ + module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id); + /* Sink node of the input net is the input of sram module */ + size_t sink_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id]; + module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id); + } + } +} + +/********************************************************************* + * Add module nets to connect an output port of a configuration-chain + * memory module to an output port of its child module + * Restriction: this function is really designed for memory modules + * 1. It assumes that output port name of child module is the same as memory module + * 2. It assumes exact pin-to-pin mapping: + * j-th pin of output port of the i-th child module is wired to the j + i*W -th + * pin of output port of the memory module, where W is the size of port + * 3. It assumes fixed port name for output ports + ********************************************************************/ +static +void add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, + const ModuleId& mem_module, + const std::string& mem_module_output_name, + const CircuitLibrary& circuit_lib, + const CircuitPortId& circuit_port, + const ModuleId& child_module, + const size_t& child_index, + const size_t& child_instance) { + /* Wire inputs of parent module to inputs of child modules */ + ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(circuit_port)); + ModulePortId sink_port_id = module_manager.find_module_port(mem_module, mem_module_output_name); + for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(mem_module); + /* Source pin is shifted by the number of memories */ + size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id]; + /* Source node of the input net is the input of memory module */ + module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id); + /* Sink node of the input net is the input of sram module */ + size_t sink_pin_id = child_index * circuit_lib.port_size(circuit_port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id]; + module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id); + } +} + +/******************************************************************** + * Connect all the memory modules under the parent module in a chain + * + * +--------+ +--------+ +--------+ + * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail + * | Module | | Module | | Module | + * | [0] | | [1] | | [N-1] | + * +--------+ +--------+ +--------+ + * For the 1st memory module: + * net source is the configuration chain head of the primitive module + * net sink is the configuration chain head of the next memory module + * + * For the rest of memory modules: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain head of the next memory module + * + * Note that: + * This function is designed for memory modules ONLY! + * Do not use it to replace the + * add_module_nets_cmos_memory_chain_config_bus() !!! + *********************************************************************/ +static +void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, + const ModuleId& parent_module, + const std::vector& memory_modules, + const std::vector& memory_instances, + const CircuitLibrary& circuit_lib, + const CircuitPortId& model_input_port, + const CircuitPortId& model_output_port) { + for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) { + ModuleId net_src_module_id; + size_t net_src_instance_id; + ModulePortId net_src_port_id; + + ModuleId net_sink_module_id; + size_t net_sink_instance_id; + ModulePortId net_sink_port_id; + + if (0 == mem_index) { + /* Find the port name of configuration chain head */ + std::string src_port_name = generate_configuration_chain_head_name(); + net_src_module_id = parent_module; + net_src_instance_id = 0; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = circuit_lib.port_lib_name(model_input_port); + net_sink_module_id = memory_modules[mem_index]; + net_sink_instance_id = memory_instances[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + } else { + /* Find the port name of previous memory module */ + std::string src_port_name = circuit_lib.port_lib_name(model_output_port); + net_src_module_id = memory_modules[mem_index - 1]; + net_src_instance_id = memory_instances[mem_index - 1]; + net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = circuit_lib.port_lib_name(model_input_port); + net_sink_module_id = memory_modules[mem_index]; + net_sink_instance_id = memory_instances[mem_index]; + net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + } + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + /* Port sizes of source and sink should match */ + VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { + /* Create a net and add source and sink to it */ + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + } + } + + /* For the last memory module: + * net source is the configuration chain tail of the previous memory module + * net sink is the configuration chain tail of the primitive module + */ + /* Find the port name of previous memory module */ + std::string src_port_name = circuit_lib.port_lib_name(model_output_port); + ModuleId net_src_module_id = memory_modules.back(); + size_t net_src_instance_id = memory_instances.back(); + ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); + + /* Find the port name of next memory module */ + std::string sink_port_name = generate_configuration_chain_tail_name(); + ModuleId net_sink_module_id = parent_module; + size_t net_sink_instance_id = 0; + ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); + + /* Get the pin id for source port */ + BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); + /* Get the pin id for sink port */ + BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); + /* Port sizes of source and sink should match */ + VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { + /* Create a net and add source and sink to it */ + ModuleNetId net = module_manager.create_module_net(parent_module); + /* Add net source */ + module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); + /* Add net sink */ + module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + } +} + +/********************************************************************* + * Flat memory modules + * + * in[0] in[1] in[N] + * | | | + * v v v + * +-------+ +-------+ +-------+ + * | SRAM | | SRAM | ... | SRAM | + * | [0] | | [1] | | [N-1] | + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Multiplexer Configuration port | + * + ********************************************************************/ +static +void build_memory_standalone_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + /* Get the global ports required by the SRAM */ + std::vector global_port_types; + global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); + global_port_types.push_back(SPICE_MODEL_PORT_INPUT); + std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); + /* Get the input ports from the SRAM */ + std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); + /* Get the output ports from the SRAM */ + std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + + /* Create a module and add to the module manager */ + ModuleId mem_module = module_manager.add_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); + + /* Add each input port */ + for (const auto& port : sram_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); + module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* Find the sram module in the module manager */ + ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); + + /* Instanciate each submodule */ + for (size_t i = 0; i < num_mems; ++i) { + size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); + module_manager.add_child_module(mem_module, sram_mem_module); + + /* Build module nets */ + /* Wire inputs of parent module to inputs of child modules */ + add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_mem_instance); + /* Wire inputs of parent module to outputs of child modules */ + add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_mem_instance); + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, mem_module); +} + +/********************************************************************* + * Scan-chain organization + * + * +-------+ +-------+ +-------+ + * scan-chain--->| CCFF |--->| CCFF |--->... --->| CCFF |---->scan-chain + * input&clock | [0] | | [1] | | [N-1] | output + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +-----------------------------------------+ + * | Multiplexer Configuration port | + * + ********************************************************************/ +static +void build_memory_chain_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + + /* Get the input ports from the SRAM */ + std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); + /* Should have only 1 input port */ + VTR_ASSERT( 1 == sram_input_ports.size() ); + /* Get the output ports from the SRAM */ + std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Should have only 1 or 2 output port */ + VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) ); + + /* Create a module and add to the module manager */ + ModuleId mem_module = module_manager.add_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); + + /* Add an input port, which is the head of configuration chain in the module */ + /* TODO: restriction!!! + * consider only the first input of the CCFF model as the D port, + * which will be connected to the head of the chain + */ + BasicPort chain_head_port(generate_configuration_chain_head_name(), + circuit_lib.port_size(sram_input_ports[0])); + module_manager.add_port(mem_module, chain_head_port, ModuleManager::MODULE_INPUT_PORT); + /* Add an output port, which is the tail of configuration chain in the module */ + /* TODO: restriction!!! + * consider only the first output of the CCFF model as the Q port, + * which will be connected to the tail of the chain + */ + BasicPort chain_tail_port(generate_configuration_chain_tail_name(), + circuit_lib.port_size(sram_output_ports[0])); + module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_INPUT_PORT); + + /* Add each output port: port width should match the number of memories */ + for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { + std::string port_name; + if (0 == iport) { + port_name = generate_configuration_chain_data_out_name(); + } else { + VTR_ASSERT( 1 == iport); + port_name = generate_configuration_chain_inverted_data_out_name(); + } + BasicPort output_port(port_name, num_mems); + module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* Find the sram module in the module manager */ + ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); + + std::vector memory_modules; + std::vector memory_instances; + + /* Instanciate each submodule */ + for (size_t i = 0; i < num_mems; ++i) { + size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); + module_manager.add_child_module(mem_module, sram_mem_module); + memory_modules.push_back(sram_mem_module); + memory_instances.push_back(sram_mem_instance); + + /* Build module nets to wire outputs of sram modules to outputs of memory module */ + for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { + std::string port_name; + if (0 == iport) { + port_name = generate_configuration_chain_data_out_name(); + } else { + VTR_ASSERT( 1 == iport); + port_name = generate_configuration_chain_inverted_data_out_name(); + } + add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, port_name, circuit_lib, sram_output_ports[iport], + sram_mem_module, i, sram_mem_instance); + } + } + + /* Build module nets to wire the configuration chain */ + add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, memory_modules, memory_instances, + circuit_lib, sram_input_ports[0], sram_output_ports[0]); + + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, mem_module); +} + +/********************************************************************* + * Memory bank organization + * + * Bit lines(BL/BLB) Word lines (WL/WLB) + * | | + * v v + * +------------------------------------+ + * | Memory Module Configuration port | + * +------------------------------------+ + * | | | + * v v v + * +-------+ +-------+ +-------+ + * | SRAM | | SRAM | ... | SRAM | + * | [0] | | [1] | | [N-1] | + * +-------+ +-------+ +-------+ + * | | ... | + * v v v + * +------------------------------------+ + * | Multiplexer Configuration port | + * + ********************************************************************/ +static +void build_memory_bank_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + /* Get the global ports required by the SRAM */ + std::vector global_port_types; + global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); + global_port_types.push_back(SPICE_MODEL_PORT_INPUT); + std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); + /* Get the input ports from the SRAM */ + std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); + /* A SRAM cell with BL/WL should not have any input */ + VTR_ASSERT( 0 == sram_input_ports.size() ); + /* Get the output ports from the SRAM */ + std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); + /* Get the BL/WL ports from the SRAM */ + std::vector sram_bl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BL, true); + std::vector sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB, true); + std::vector sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WL, true); + std::vector sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB, true); + + /* Create a module and add to the module manager */ + ModuleId mem_module = module_manager.add_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); + + /* Add module ports: the ports come from the SRAM modules */ + /* Add each input port */ + for (const auto& port : sram_input_ports) { + BasicPort input_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT); + } + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_output_ports) { + BasicPort output_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); + } + /* Add each output port: port width should match the number of memories */ + for (const auto& port : sram_bl_ports) { + BasicPort bl_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT); + } + for (const auto& port : sram_blb_ports) { + BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + module_manager.add_port(mem_module, blb_port, ModuleManager::MODULE_INPUT_PORT); + } + for (const auto& port : sram_wl_ports) { + BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT); + } + for (const auto& port : sram_wlb_ports) { + BasicPort wlb_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + module_manager.add_port(mem_module, wlb_port, ModuleManager::MODULE_INPUT_PORT); + } + + /* Find the sram module in the module manager */ + ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); + + /* Instanciate each submodule */ + for (size_t i = 0; i < num_mems; ++i) { + /* Memory seed module instanciation */ + size_t sram_instance = module_manager.num_instance(mem_module, sram_mem_module); + module_manager.add_child_module(mem_module, sram_mem_module); + + /* Build module nets */ + /* Wire inputs of parent module to inputs of child modules */ + add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_instance); + /* Wire inputs of parent module to outputs of child modules */ + add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance); + /* Wire BL/WLs of parent module to BL/WLs of child modules */ + add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_bl_ports, sram_mem_module, i, sram_instance); + add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_blb_ports, sram_mem_module, i, sram_instance); + add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wl_ports, sram_mem_module, i, sram_instance); + add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wlb_ports, sram_mem_module, i, sram_instance); + } + + /* TODO: if a local memory decoder is required, instanciate it here */ + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, mem_module); +} + + +/********************************************************************* + * Generate Verilog modules for the memories that are used + * by a circuit model + * The organization of memory circuit will depend on the style of + * configuration protocols + * Currently, we support + * 1. Flat SRAM organization + * 2. Configuration chain + * 3. Memory bank (memory decoders) + ********************************************************************/ +static +void build_memory_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const std::string& module_name, + const CircuitModelId& sram_model, + const size_t& num_mems) { + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + build_memory_standalone_module(module_manager, circuit_lib, + module_name, sram_model, num_mems); + break; + case SPICE_SRAM_SCAN_CHAIN: + build_memory_chain_module(module_manager, circuit_lib, + module_name, sram_model, num_mems); + break; + case SPICE_SRAM_MEMORY_BANK: + build_memory_bank_module(module_manager, circuit_lib, + module_name, sram_model, num_mems); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, LINE%d) Invalid SRAM organization!\n", + __FILE__, __LINE__); + } +} + + +/********************************************************************* + * Generate Verilog modules for the memories that are used + * by multiplexers + * + * +----------------+ + * mem_in --->| Memory Module |---> mem_out + * +----------------+ + * | | ... | | + * v v v v SRAM ports of multiplexer + * +---------------------+ + * in--->| Multiplexer Module |---> out + * +---------------------+ + ********************************************************************/ +static +void build_mux_memory_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& mux_model, + const MuxGraph& mux_graph) { + /* Find the actual number of configuration bits, based on the mux graph + * Due to the use of local decoders inside mux, this may be + */ + size_t num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); + /* Multiplexers built with different technology is in different organization */ + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: { + /* Generate module name */ + std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, + find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), + std::string(verilog_mem_posfix)); + + /* Get the sram ports from the mux */ + std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); + VTR_ASSERT( 1 == sram_models.size() ); + + build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_config_bits); + break; + } + case SPICE_MODEL_DESIGN_RRAM: + /* We do not need a memory submodule for RRAM MUX, + * RRAM are embedded in the datapath + * TODO: generate local encoders for RRAM-based multiplexers here!!! + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + exit(1); + } +} + +/********************************************************************* + * Build modules for + * the memories that are affiliated to multiplexers and other programmable + * circuit models, such as IOPADs, LUTs, etc. + * + * We keep the memory modules separated from the multiplexers and other + * programmable circuit models, for the sake of supporting + * various configuration schemes. + * By following such organiztion, the Verilog modules of the circuit models + * implements the functionality (circuit logic) only, while the memory Verilog + * modules implements the memory circuits as well as configuration protocols. + * For example, the local decoders of multiplexers are implemented in the + * memory modules. + * Take another example, the memory circuit can implement the scan-chain or + * memory-bank organization for the memories. + ********************************************************************/ +void build_memory_modules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type) { + + /* Create the memory circuits for the multiplexer */ + for (auto mux : mux_lib.muxes()) { + const MuxGraph& mux_graph = mux_lib.mux_graph(mux); + CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); + /* Bypass the non-MUX circuit models (i.e., LUTs). + * They should be handled in a different way + * Memory circuits of LUT includes both regular and mode-select ports + */ + if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { + continue; + } + /* Create a Verilog module for the memories used by the multiplexer */ + build_mux_memory_module(module_manager, circuit_lib, sram_orgz_type, mux_model, mux_graph); + } + + /* Create the memory circuits for non-MUX circuit models. + * In this case, the memory modules are designed to interface + * the mode-select ports + */ + for (const auto& model : circuit_lib.models()) { + /* Bypass MUXes, they have already been considered */ + if (SPICE_MODEL_MUX == circuit_lib.model_type(model)) { + continue; + } + /* Bypass those modules without any SRAM ports */ + std::vector sram_ports = circuit_lib.model_ports_by_type(model, SPICE_MODEL_PORT_SRAM, true); + if (0 == sram_ports.size()) { + continue; + } + /* Find the name of memory module */ + /* Get the total number of SRAMs */ + size_t num_mems = 0; + for (const auto& port : sram_ports) { + num_mems += circuit_lib.port_size(port); + } + /* Get the circuit model for the memory circuit used by the multiplexer */ + std::vector sram_models = find_circuit_sram_models(circuit_lib, model); + /* Should have only 1 SRAM model */ + VTR_ASSERT( 1 == sram_models.size() ); + + /* Create the module name for the memory block */ + std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(verilog_mem_posfix)); + + /* Create a Verilog module for the memories used by the circuit model */ + build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems); + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h new file mode 100644 index 000000000..3597c5d95 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h @@ -0,0 +1,20 @@ +/*********************************************** + * Header file for verilog_memory.cpp + **********************************************/ + +#ifndef BUILD_MEMORY_MODULE_H +#define BUILD_MEMORY_MODULE_H + +/* Include other header files which are dependency on the function declared below */ + +#include "circuit_library.h" +#include "mux_graph.h" +#include "mux_library.h" +#include "module_manager.h" + +void build_memory_modules(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index d4196672d..666e42876 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -15,6 +15,7 @@ #include "build_mux_modules.h" #include "build_lut_modules.h" #include "build_wire_modules.h" +#include "build_memory_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -94,7 +95,9 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, /* Build wire modules */ build_wire_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); - /* TODO: Build memory modules */ + /* Build memory modules */ + build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib, + arch.sram_inf.verilog_sram_inf_orgz->type); /* TODO: Build grid and programmable block modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index b5fa63060..7bd605d01 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -31,7 +31,8 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, - const std::string& submodule_dir) { + const std::string& submodule_dir, + const bool& use_explicit_port_map) { /* TODO: remove .bak when this part is completed and tested */ std::string verilog_fname = submodule_dir + luts_verilog_file_name + ".bak"; @@ -61,7 +62,8 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, /* Find the module id */ ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model)); VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); - write_verilog_module_to_file(fp, module_manager, lut_module, circuit_lib.dump_explicit_port_map(lut_model)); + write_verilog_module_to_file(fp, module_manager, lut_module, + use_explicit_port_map || circuit_lib.dump_explicit_port_map(lut_model)); } /* Close the file handler */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h index d6a8dba35..6eee42b61 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h @@ -15,6 +15,7 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, - const std::string& submodule_dir); + const std::string& submodule_dir, + const bool& use_explicit_port_map); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index 09c2501f3..c898aac26 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -25,410 +25,9 @@ /* FPGA-Verilog context header files */ #include "verilog_global.h" #include "verilog_writer_utils.h" +#include "verilog_module_writer.h" #include "verilog_memory.h" -/********************************************************************* - * Flat memory modules - * - * in[0] in[1] in[N] - * | | | - * v v v - * +-------+ +-------+ +-------+ - * | SRAM | | SRAM | ... | SRAM | - * | [0] | | [1] | | [N-1] | - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Multiplexer Configuration port | - * - ********************************************************************/ -static -void print_verilog_memory_standalone_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Create a module and add to the module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Get the global ports required by the SRAM */ - std::vector global_port_types; - global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); - global_port_types.push_back(SPICE_MODEL_PORT_INPUT); - std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); - /* Get the input ports from the SRAM */ - std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the SRAM */ - std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Add module ports: the ports come from the SRAM modules */ - /* Add each global port */ - for (const auto& port : sram_global_ports) { - /* Configure each global port: global ports are shared among the SRAMs, so it is independent from the memory size */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - for (const auto& port : sram_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - } - /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Find the sram module in the module manager */ - ModuleId sram_module_id = module_manager.find_module(circuit_lib.model_name(sram_model)); - - /* Instanciate each submodule */ - for (size_t i = 0; i < num_mems; ++i) { - /* Create a port-to-port map */ - std::map port2port_name_map; - /* Map instance inputs [i] to SRAM module input */ - for (const auto& port : sram_input_ports) { - BasicPort instance_input_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; - } - /* Map instance outputs [i] to SRAM module input */ - for (const auto& port : sram_output_ports) { - BasicPort instance_output_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_output_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, sram_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(sram_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, sram_module_id); - } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - -/********************************************************************* - * Scan-chain organization - * - * +-------+ +-------+ +-------+ - * scan-chain--->| CCFF |--->| CCFF |--->... --->| CCFF |---->scan-chain - * input&clock | [0] | | [1] | | [N-1] | output - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +-----------------------------------------+ - * | Multiplexer Configuration port | - * - ********************************************************************/ -static -void print_verilog_memory_chain_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Create a module and add to the module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Get the global ports required by the SRAM */ - std::vector global_port_types; - global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); - global_port_types.push_back(SPICE_MODEL_PORT_INPUT); - std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); - /* Get the input ports from the SRAM */ - std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); - /* Should have only 1 input port */ - VTR_ASSERT( 1 == sram_input_ports.size() ); - /* Get the output ports from the SRAM */ - std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Should have only 1 or 2 output port */ - VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) ); - - /* Add module ports: the ports come from the SRAM modules */ - /* Add each global port */ - for (const auto& port : sram_global_ports) { - /* Configure each global port: global ports are shared among the SRAMs, so it is independent from the memory size */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add an input port, which is the head of configuration chain in the module */ - /* TODO: restriction!!! - * consider only the first input of the CCFF model as the D port, - * which will be connected to the head of the chain - */ - BasicPort chain_head_port(generate_configuration_chain_head_name(), - circuit_lib.port_size(sram_input_ports[0])); - module_manager.add_port(module_id, chain_head_port, ModuleManager::MODULE_INPUT_PORT); - /* Add an output port, which is the tail of configuration chain in the module */ - /* TODO: restriction!!! - * consider only the first output of the CCFF model as the Q port, - * which will be connected to the tail of the chain - */ - BasicPort chain_tail_port(generate_configuration_chain_tail_name(), - circuit_lib.port_size(sram_output_ports[0])); - module_manager.add_port(module_id, chain_tail_port, ModuleManager::MODULE_INPUT_PORT); - /* Add each output port: port width should match the number of memories */ - for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { - std::string port_name; - if (0 == iport) { - port_name = generate_configuration_chain_data_out_name(); - } else { - VTR_ASSERT( 1 == iport); - port_name = generate_configuration_chain_inverted_data_out_name(); - } - BasicPort output_port(port_name, num_mems); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Find the sram module in the module manager */ - ModuleId sram_module_id = module_manager.find_module(circuit_lib.model_name(sram_model)); - - /* Instanciate each submodule */ - for (size_t i = 0; i < num_mems; ++i) { - /* Create a port-to-port map */ - std::map port2port_name_map; - /* Map instance inputs [i] to SRAM module input */ - for (const auto& port : sram_input_ports) { - BasicPort instance_input_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; - } - /* Map instance outputs [i] to SRAM module input */ - for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { - std::string port_name; - if (0 == iport) { - port_name = generate_configuration_chain_data_out_name(); - } else { - VTR_ASSERT( 1 == iport); - port_name = generate_configuration_chain_inverted_data_out_name(); - } - BasicPort instance_output_port(port_name, i, i); - port2port_name_map[circuit_lib.port_lib_name(sram_output_ports[iport])] = instance_output_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, sram_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(sram_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, sram_module_id); - } - - /* Wire the memory cells into a chain - * The head of the chain will be wired to the input port of the first CCFF - * The tail of the chain will be wired to the output port of the last CCFF - * The output of each CCFF will be wired to the input of the next CCFFF in the chain - */ - BasicPort first_ccff_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 0, 0); - print_verilog_wire_connection(fp, first_ccff_input_port, chain_head_port, false); - - BasicPort last_ccff_output_port(generate_configuration_chain_data_out_name(), num_mems - 1, num_mems - 1); - print_verilog_wire_connection(fp, chain_tail_port, last_ccff_output_port, false); - - BasicPort chain_output_port(generate_configuration_chain_data_out_name(), 0, num_mems - 2); - BasicPort chain_input_port(circuit_lib.port_lib_name(sram_input_ports[0]), 1, num_mems - 1); - print_verilog_wire_connection(fp, chain_input_port, chain_output_port, false); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - -/********************************************************************* - * Memory bank organization - * - * Bit lines(BL/BLB) Word lines (WL/WLB) - * | | - * v v - * +------------------------------------+ - * | Memory Module Configuration port | - * +------------------------------------+ - * | | | - * v v v - * +-------+ +-------+ +-------+ - * | SRAM | | SRAM | ... | SRAM | - * | [0] | | [1] | | [N-1] | - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Multiplexer Configuration port | - * - ********************************************************************/ -static -void print_verilog_memory_bank_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Create a module and add to the module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Get the global ports required by the SRAM */ - std::vector global_port_types; - global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); - global_port_types.push_back(SPICE_MODEL_PORT_INPUT); - std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); - /* Get the input ports from the SRAM */ - std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); - /* A SRAM cell with BL/WL should not have any input */ - VTR_ASSERT( 0 == sram_input_ports.size() ); - /* Get the output ports from the SRAM */ - std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the BL/WL ports from the SRAM */ - std::vector sram_bl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BL, true); - std::vector sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB, true); - std::vector sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WL, true); - std::vector sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB, true); - - /* Add module ports: the ports come from the SRAM modules */ - /* Add each global port */ - for (const auto& port : sram_global_ports) { - /* Configure each global port: global ports are shared among the SRAMs, so it is independent from the memory size */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - for (const auto& port : sram_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - } - /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_bl_ports) { - BasicPort bl_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, bl_port, ModuleManager::MODULE_INPUT_PORT); - } - for (const auto& port : sram_blb_ports) { - BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); - } - for (const auto& port : sram_wl_ports) { - BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); - } - for (const auto& port : sram_wlb_ports) { - BasicPort wlb_port(circuit_lib.port_lib_name(port), num_mems); - module_manager.add_port(module_id, wlb_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Find the sram module in the module manager */ - ModuleId sram_module_id = module_manager.find_module(circuit_lib.model_name(sram_model)); - - /* Instanciate each submodule */ - for (size_t i = 0; i < num_mems; ++i) { - /* Create a port-to-port map */ - std::map port2port_name_map; - /* Map instance inputs [i] to SRAM module input */ - for (const auto& port : sram_input_ports) { - BasicPort instance_input_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_input_port; - } - /* Map instance outputs [i] to SRAM module input */ - for (const auto& port : sram_output_ports) { - BasicPort instance_output_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_output_port; - } - /* Map instance BL[i] and WL[i] to SRAM module input */ - for (const auto& port : sram_bl_ports) { - BasicPort instance_bl_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_bl_port; - } - for (const auto& port : sram_blb_ports) { - BasicPort instance_blb_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_blb_port; - } - for (const auto& port : sram_wl_ports) { - BasicPort instance_wl_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_wl_port; - } - for (const auto& port : sram_wlb_ports) { - BasicPort instance_wlb_port(circuit_lib.port_lib_name(port), i, i); - port2port_name_map[circuit_lib.port_lib_name(port)] = instance_wlb_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, sram_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(sram_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, sram_module_id); - } - - /* TODO: if a local memory decoder is required, instanciate it here */ - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - - -/********************************************************************* - * Generate Verilog modules for the memories that are used - * by a circuit model - * The organization of memory circuit will depend on the style of - * configuration protocols - * Currently, we support - * 1. Flat SRAM organization - * 2. Configuration chain - * 3. Memory bank (memory decoders) - ********************************************************************/ -static -void print_verilog_memory_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - std::fstream& fp, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - print_verilog_memory_standalone_module(module_manager, circuit_lib, fp, - module_name, sram_model, num_mems); - break; - case SPICE_SRAM_SCAN_CHAIN: - print_verilog_memory_chain_module(module_manager, circuit_lib, fp, - module_name, sram_model, num_mems); - break; - case SPICE_SRAM_MEMORY_BANK: - print_verilog_memory_bank_module(module_manager, circuit_lib, fp, - module_name, sram_model, num_mems); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, LINE%d) Invalid SRAM organization!\n", - __FILE__, __LINE__); - } -} - - /********************************************************************* * Generate Verilog modules for the memories that are used * by multiplexers @@ -445,14 +44,10 @@ void print_verilog_memory_module(ModuleManager& module_manager, static void print_verilog_mux_memory_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, std::fstream& fp, const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { - /* Find the actual number of configuration bits, based on the mux graph - * Due to the use of local decoders inside mux, this may be - */ - size_t num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); + const MuxGraph& mux_graph, + const bool& use_explicit_port_map) { /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: { @@ -460,12 +55,14 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), std::string(verilog_mem_posfix)); + ModuleId mem_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); + /* Write the module content in Verilog format */ + write_verilog_module_to_file(fp, module_manager, mem_module, + use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model)); - /* Get the sram ports from the mux */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); - VTR_ASSERT( 1 == sram_models.size() ); - - print_verilog_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, module_name, sram_models[0], num_config_bits); + /* Add an empty line as a splitter */ + fp << std::endl; break; } case SPICE_MODEL_DESIGN_RRAM: @@ -502,9 +99,9 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, void print_verilog_submodule_memories(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, const std::string& verilog_dir, - const std::string& submodule_dir) { + const std::string& submodule_dir, + const bool& use_explicit_port_map) { /* Plug in with the mux subckt */ std::string verilog_fname(submodule_dir + memories_verilog_file_name); verilog_fname += ".bak"; @@ -536,7 +133,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, continue; } /* Create a Verilog module for the memories used by the multiplexer */ - print_verilog_mux_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, mux_model, mux_graph); + print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph, use_explicit_port_map); } /* Create the memory circuits for non-MUX circuit models. @@ -577,8 +174,14 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, /* Create the module name for the memory block */ std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(verilog_mem_posfix)); - /* Create a Verilog module for the memories used by the circuit model */ - print_verilog_memory_module(module_manager, circuit_lib, sram_orgz_type, fp, module_name, sram_models[0], num_mems); + ModuleId mem_module = module_manager.find_module(module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); + /* Write the module content in Verilog format */ + write_verilog_module_to_file(fp, module_manager, mem_module, + use_explicit_port_map || circuit_lib.dump_explicit_port_map(model)); + + /* Add an empty line as a splitter */ + fp << std::endl; } /* Close the file stream */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h index eee29cb23..bfba1c391 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h @@ -16,8 +16,8 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, const std::string& verilog_dir, - const std::string& submodule_dir); + const std::string& submodule_dir, + const bool& use_explicit_port_map); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 232d7fdf4..413d57e5a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -575,7 +575,8 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, std::fstream& fp, const CircuitModelId& mux_model, const size_t& mux_size, - const MuxGraph& mux_graph) { + const MuxGraph& mux_graph, + const bool& use_explicit_port_map) { std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); /* Multiplexers built with different technology is in different organization */ @@ -585,7 +586,8 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, /* Structural verilog can be easily generated by module writer */ ModuleId mux_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - write_verilog_module_to_file(fp, module_manager, mux_module, circuit_lib.dump_explicit_port_map(mux_model)); + write_verilog_module_to_file(fp, module_manager, mux_module, + use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model)); /* Add an empty line as a splitter */ fp << std::endl; } else { @@ -1170,7 +1172,8 @@ void generate_verilog_mux_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { + const MuxGraph& mux_graph, + const bool& use_explicit_port_map) { std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), std::string("")); @@ -1181,7 +1184,8 @@ void generate_verilog_mux_module(ModuleManager& module_manager, /* Use Verilog writer to print the module to file */ ModuleId mux_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - write_verilog_module_to_file(fp, module_manager, mux_module, circuit_lib.dump_explicit_port_map(mux_model)); + write_verilog_module_to_file(fp, module_manager, mux_module, + use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model)); /* Add an empty line as a splitter */ fp << std::endl; break; @@ -1208,7 +1212,8 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, t_sram_orgz_info* cur_sram_orgz_info, const std::string& verilog_dir, - const std::string& submodule_dir) { + const std::string& submodule_dir, + const bool& use_explicit_port_map) { /* TODO: Generate modules into a .bak file now. Rename after it is verified */ std::string verilog_fname(submodule_dir + muxes_verilog_file_name); @@ -1239,7 +1244,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, for (auto branch_mux_graph : branch_mux_graphs) { generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), - branch_mux_graph); + branch_mux_graph, use_explicit_port_map); } } @@ -1248,7 +1253,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, const MuxGraph& mux_graph = mux_lib.mux_graph(mux); CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); /* Create MUX circuits */ - generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph); + generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph, use_explicit_port_map); } /* Close the file stream */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index 2db3e1f45..51f3c7d7b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -18,6 +18,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, t_sram_orgz_info* cur_sram_orgz_info, const std::string& verilog_dir, - const std::string& submodule_dir); + const std::string& submodule_dir, + const bool& use_explicit_port_map); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 91080490b..a4199308d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3283,7 +3283,9 @@ void dump_verilog_submodules(ModuleManager& module_manager, */ print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); - print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir)); + print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, + std::string(verilog_dir), std::string(submodule_dir), + fpga_verilog_opts.dump_explicit_verilog); /* 2. LUTes */ @@ -3293,7 +3295,8 @@ void dump_verilog_submodules(ModuleManager& module_manager, fpga_verilog_opts.include_timing, fpga_verilog_opts.include_signal_init, fpga_verilog_opts.dump_explicit_verilog); - print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); + print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir), + fpga_verilog_opts.dump_explicit_verilog); /* 3. Hardwires */ print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); @@ -3303,8 +3306,8 @@ void dump_verilog_submodules(ModuleManager& module_manager, dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, - cur_sram_orgz_info->type, - std::string(verilog_dir), std::string(submodule_dir)); + std::string(verilog_dir), std::string(submodule_dir), + fpga_verilog_opts.dump_explicit_verilog); /* 5. Dump template for all the modules */ if (TRUE == fpga_verilog_opts.print_user_defined_template) { From 89c8d089a38df5c4b60e23c5d585fee1c2979c2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Oct 2019 16:14:11 -0600 Subject: [PATCH 321/482] add grid module generation --- .../module_builder/build_grid_modules.cpp | 1124 +++++++++++++++++ .../module_builder/build_grid_modules.h | 18 + .../module_builder/build_memory_modules.h | 6 +- .../module_builder/build_module_graph.cpp | 7 +- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 957 +------------- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.h | 5 +- 7 files changed, 1167 insertions(+), 953 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp new file mode 100644 index 000000000..68579a252 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -0,0 +1,1124 @@ +/******************************************************************** + * This file includes functions to print Verilog modules for a Grid + * (CLBs, I/Os, heterogeneous blocks etc.) + *******************************************************************/ +/* System header files */ +#include + +/* Header files from external libs */ +#include "vtr_geometry.h" +#include "util.h" +#include "vtr_assert.h" +#include "circuit_library_utils.h" + +/* Header files for VPR */ +#include "vpr_types.h" +#include "globals.h" + +/* Header files for FPGA X2P tool suite */ +#include "fpga_x2p_naming.h" +#include "fpga_x2p_types.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" +#include "module_manager_utils.h" +#include "fpga_x2p_globals.h" + +/* Header files for Verilog generator */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "build_grid_modules.h" + +/******************************************************************** + * Find the side where I/O pins locate on a grid I/O block + * 1. I/O grids on the top side of FPGA only have ports on its bottom side + * 2. I/O grids on the right side of FPGA only have ports on its left side + * 3. I/O grids on the bottom side of FPGA only have ports on its top side + * 4. I/O grids on the left side of FPGA only have ports on its right side + *******************************************************************/ +static +e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor, + const e_side& border_side) { + VTR_ASSERT(IO_TYPE == grid_type_descriptor); + Side side_manager(border_side); + return side_manager.get_opposite(); +} + +/******************************************************************** + * Add ports/pins to a grid module + * This function will iterate over all the pins that are defined + * in type_descripter and give a name by its height, side and index + * + * In particular, for I/O grid, only part of the ports on required + * on a specific side. + *******************************************************************/ +static +void add_grid_module_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + t_type_ptr grid_type_descriptor, + const e_side& border_side) { + /* Ensure that we have a valid grid_type_descriptor */ + VTR_ASSERT(NULL != grid_type_descriptor); + + /* Find the pin side for I/O grids*/ + std::vector grid_pin_sides; + /* For I/O grids, we care only one side + * Otherwise, we will iterate all the 4 sides + */ + if (IO_TYPE == grid_type_descriptor) { + grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); + } else { + grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; + } + + /* Create a map between pin class type and grid pin direction */ + std::map pin_type2type_map; + pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT; + pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT; + + /* Iterate over sides, height and pins */ + for (const e_side& side : grid_pin_sides) { + for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) { + for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) { + if (1 != grid_type_descriptor->pinloc[iheight][side][ipin]) { + continue; + } + /* Reach here, it means this pin is on this side */ + int class_id = grid_type_descriptor->pin_class[ipin]; + e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; + /* Generate the pin name, + * we give a empty coordinate but it will not be used (see details in the function + */ + vtr::Point dummy_coordinate; + std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false); + BasicPort grid_port(port_name, 0, 0); + /* Add the port to the module */ + module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); + } + } + } +} + +/******************************************************************** + * Add module nets to connect a port of child pb_module + * to the grid module + *******************************************************************/ +static +void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, + const ModuleId& grid_module, + const ModuleId& child_module, + const size_t& child_instance, + t_type_ptr grid_type_descriptor, + t_pb_graph_pin* pb_graph_pin, + const e_side& border_side, + const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { + /* Find the pin side for I/O grids*/ + std::vector grid_pin_sides; + /* For I/O grids, we care only one side + * Otherwise, we will iterate all the 4 sides + */ + if (IO_TYPE == grid_type_descriptor) { + grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); + } else { + grid_pin_sides.push_back(TOP); + grid_pin_sides.push_back(RIGHT); + grid_pin_sides.push_back(BOTTOM); + grid_pin_sides.push_back(LEFT); + } + + /* num_pins/capacity = the number of pins that each type_descriptor has. + * Capacity defines the number of type_descriptors in each grid + * so the pin index at grid level = pin_index_in_type_descriptor + * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor + */ + size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster + + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity; + int pin_height = grid_type_descriptor->pin_height[grid_pin_index]; + for (const e_side& side : grid_pin_sides) { + if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) { + continue; + } + /* Reach here, it means this pin is on this side */ + /* Create a net to connect the grid pin to child module pin */ + ModuleNetId net = module_manager.create_module_net(grid_module); + /* Find the port in grid_module */ + vtr::Point dummy_coordinate; + std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false); + ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); + /* Grid port always has only 1 pin, it is assumed when adding these ports to the module + * if you need a change, please also change the port adding codes + */ + size_t grid_module_pin_id = 0; + /* Find the port in child module */ + std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); + ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); + size_t child_module_pin_id = pb_graph_pin->pin_number; + /* Add net sources and sinks: + * For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin + * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin + */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); + module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); + break; + case OUTPUT2OUTPUT_INTERC: + module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); + module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } + } +} + + +/******************************************************************** + * Add module nets to connect ports/pins of a grid module + * to its child modules + * This function will iterate over all the pins that are defined + * in type_descripter and find the corresponding pin in the top + * pb_graph_node of the grid + *******************************************************************/ +static +void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + const ModuleId& child_module, + const size_t& child_instance, + t_type_ptr grid_type_descriptor, + const e_side& border_side) { + /* Ensure that we have a valid grid_type_descriptor */ + VTR_ASSERT(NULL != grid_type_descriptor); + t_pb_graph_node* top_pb_graph_node = grid_type_descriptor->pb_graph_head; + VTR_ASSERT(NULL != top_pb_graph_node); + + for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { + add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, + child_module, child_instance, + grid_type_descriptor, + &(top_pb_graph_node->input_pins[iport][ipin]), + border_side, + INPUT2INPUT_INTERC); + + } + } + + for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { + add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, + child_module, child_instance, + grid_type_descriptor, + &(top_pb_graph_node->output_pins[iport][ipin]), + border_side, + OUTPUT2OUTPUT_INTERC); + } + } + + for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { + add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, + child_module, child_instance, + grid_type_descriptor, + &(top_pb_graph_node->clock_pins[iport][ipin]), + border_side, + INPUT2INPUT_INTERC); + } + } +} + +/******************************************************************** + * Print Verilog modules of a primitive node in the pb_graph_node graph + * This generic function can support all the different types of primitive nodes + * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders. + * + * The Verilog module will consist of two parts: + * 1. Logic module of the primitive node + * This module performs the logic function of the block + * 2. Memory module of the primitive node + * This module stores the configuration bits for the logic module + * if the logic module is a programmable resource, such as LUT + * + * Verilog module structure: + * + * Primitive block + * +---------------------------------------+ + * | | + * | +---------+ +---------+ | + * in |----->| |--->| |<------|configuration lines + * | | Logic |... | Memory | | + * out|<-----| |--->| | | + * | +---------+ +---------+ | + * | | + * +---------------------------------------+ + * + *******************************************************************/ +static +void build_primitive_block_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + t_pb_graph_node* primitive_pb_graph_node, + const e_side& io_side) { + /* Ensure a valid pb_graph_node */ + if (NULL == primitive_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid primitive_pb_graph_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Find the circuit model id linked to the pb_graph_node */ + CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model; + + /* Generate the module name for this primitive pb_graph_node*/ + std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); + std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); + + /* Create a module of the primitive LUT and register it to module manager */ + ModuleId primitive_module = module_manager.add_module(primitive_module_name); + /* Ensure that the module has been created and thus unique! */ + VTR_ASSERT(ModuleId::INVALID() != primitive_module); + + /* Find the global ports required by the primitive node, and add them to the module */ + std::vector primitive_model_global_ports = circuit_lib.model_global_ports(primitive_model, true); + for (auto port : primitive_model_global_ports) { + /* The global I/O of the FPGA has a special name */ + BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GLOBAL_PORT); + } + + /* Find the inout ports required by the primitive node, and add them to the module + * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric + */ + if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { + std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); + for (auto port : primitive_model_inout_ports) { + BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); + module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); + } + } + /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here. + * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P, + * no ports of the circuit model will be missing here + */ + add_primitive_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); + + /* Add configuration ports */ + /* Shared SRAM ports*/ + size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, sram_orgz_type); + if (0 < num_shared_config_bits) { + /* Check: this SRAM organization type must be memory-bank ! */ + VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == sram_orgz_type ); + /* Generate a list of ports */ + add_reserved_sram_ports_to_module_manager(module_manager, primitive_module, + num_shared_config_bits); + } + + /* Regular (independent) SRAM ports */ + size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model); + if (0 < num_config_bits) { + add_sram_ports_to_module_manager(module_manager, primitive_module, + circuit_lib, sram_model, sram_orgz_type, + num_config_bits); + } + + /* Find the module id in the module manager */ + ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model)); + VTR_ASSERT(ModuleId::INVALID() != logic_module); + size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); + /* Add the logic module as a child of primitive module */ + module_manager.add_child_module(primitive_module, logic_module); + + /* Add nets to connect the logic model ports to pb_type ports */ + add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); + + /* Add the associated memory module as a child of primitive module */ + std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix)); + ModuleId memory_module = module_manager.find_module(memory_module_name); + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* If there is no memory module required, we can skip the assocated net addition */ + if (ModuleId::INVALID() != memory_module) { + size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); + /* Add the memory module as a child of primitive module */ + module_manager.add_child_module(primitive_module, memory_module); + + /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ + add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module, + logic_module, logic_instance_id, + memory_module, memory_instance_id, + circuit_lib, primitive_model); + /* Record memory-related information */ + memory_modules.push_back(memory_module); + memory_instances.push_back(memory_instance_id); + } + /* Add all the nets to connect configuration ports from memory module to primitive modules + * This is a one-shot addition that covers all the memory modules in this primitive module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, primitive_module, + memory_modules, memory_instances, + sram_orgz_type, circuit_lib.design_tech_type(sram_model)); + } +} + +/******************************************************************** + * This function add a net for a pin-to-pin connection defined in pb_graph + * It supports two cases for the pin-to-pin connection + * 1. The net source is a pb_graph_pin while the net sink is a pin of an interconnection + * 2. The net source is a pin of an interconnection while the net sink a pb_graph_pin + * The type is enabled by an argument pin2pin_interc_type + *******************************************************************/ +static +void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, + const ModuleId& pb_module, + const ModuleId& interc_module, + const size_t& interc_instance, + const std::string& interc_port_name, + const size_t& interc_pin_id, + const std::string& module_name_prefix, + t_pb_graph_pin* pb_graph_pin, + const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { + + ModuleNetId pin2pin_net = module_manager.create_module_net(pb_module); + + /* Find port and pin ids for the module, which is the parent of pb_graph_pin */ + t_pb_type* pin_pb_type = pb_graph_pin->parent_node->pb_type; + /* Find the module contains the source pin */ + ModuleId pin_pb_type_module = module_manager.find_module(generate_physical_block_module_name(module_name_prefix, pin_pb_type)); + VTR_ASSERT(true == module_manager.valid_module_id(pin_pb_type_module)); + size_t pin_pb_type_instance = 0; /* Deposite the instance with a zero, which is the default value is the source module is actually pb_module itself */ + if (pin_pb_type_module != pb_module) { + pin_pb_type_instance = pb_graph_pin->parent_node->placement_index; + /* Ensure this is an valid instance */ + VTR_ASSERT(pin_pb_type_instance < module_manager.num_instance(pb_module, pin_pb_type_module)); + } + ModulePortId pin_module_port_id = module_manager.find_module_port(pin_pb_type_module, generate_pb_type_port_name(pb_graph_pin->port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(pin_pb_type_module, pin_module_port_id)); + size_t pin_module_pin_id = pb_graph_pin->pin_number; + /* Ensure this is an valid pin index */ + VTR_ASSERT(pin_module_pin_id < module_manager.module_port(pin_pb_type_module, pin_module_port_id).get_width()); + + /* Find port and pin ids for the interconnection module */ + ModulePortId interc_port_id = module_manager.find_module_port(interc_module, interc_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(interc_module, interc_port_id)); + /* Ensure this is an valid pin index */ + VTR_ASSERT(interc_pin_id < module_manager.module_port(interc_module, interc_port_id).get_width()); + + /* Add net sources and sinks: + * For input-to-input connection, net_source is pin_graph_pin, while net_sink is interc pin + * For output-to-output connection, net_source is interc pin, while net_sink is pin_graph pin + */ + switch (pin2pin_interc_type) { + case INPUT2INPUT_INTERC: + module_manager.add_module_net_source(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); + module_manager.add_module_net_sink(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); + break; + case OUTPUT2OUTPUT_INTERC: + module_manager.add_module_net_source(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); + module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins + * /|\ + * | + * input_pins, edges, output_pins + * + * This function does the following task: + * 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Add mux/direct connection as a child module to pb_module + * 4. Add nets related to the mux/direction + *******************************************************************/ +static +void add_module_pb_graph_pin_interc(ModuleManager& module_manager, + const ModuleId& pb_module, + std::vector& memory_modules, + std::vector& memory_instances, + const CircuitLibrary& circuit_lib, + const std::string& module_name_prefix, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* physical_mode) { + /* Find the number of fan-in and detailed interconnection information + * related to the destination pb_graph_pin + */ + int fan_in = 0; + t_interconnect* cur_interc = NULL; + find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); + + /* If no interconnection is needed, we can return early */ + if ((NULL == cur_interc) || (0 == fan_in)) { + return; + } + + /* Initialize the interconnection type that will be physically implemented in module */ + enum e_interconnect verilog_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); + + /* Find input ports of the wire module */ + std::vector interc_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ + /* Find output ports of the wire module */ + std::vector interc_model_outputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */ + + /* Ensure that we have only 1 input port and 1 output port, this is valid for both wire and MUX */ + VTR_ASSERT(1 == interc_model_inputs.size()); + VTR_ASSERT(1 == interc_model_outputs.size()); + + /* Branch on the type of physical implementation, + * We add instances of programmable interconnection + */ + switch (verilog_interc_type) { + case DIRECT_INTERC: { + /* Ensure direct interc has only one fan-in */ + VTR_ASSERT(1 == fan_in); + + /* For more than one mode defined, the direct interc has more than one input_edge , + * We need to find which edge is connected the pin we want + */ + int iedge = 0; + for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { + break; + } + } + t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + + /* Ensure that circuit model is a wire */ + VTR_ASSERT(SPICE_MODEL_WIRE == circuit_lib.model_type(cur_interc->circuit_model)); + /* Find the wire module in the module manager */ + ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(cur_interc->circuit_model)); + VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); + /* Get the instance id and add an instance of wire */ + size_t wire_instance = module_manager.num_instance(pb_module, wire_module); + module_manager.add_child_module(pb_module, wire_module); + + /* Ensure input and output ports of the wire model has only 1 pin respectively */ + VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0])); + VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); + + /* Add nets to connect the wires to ports of pb_module */ + /* First net is to connect input of src_pb_graph_node to input of the wire module */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + wire_module, wire_instance, + circuit_lib.port_lib_name(interc_model_inputs[0]), + 0, /* wire input port has only 1 pin */ + module_name_prefix, + src_pb_graph_pin, + INPUT2INPUT_INTERC); + + /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + wire_module, wire_instance, + circuit_lib.port_lib_name(interc_model_outputs[0]), + 0, /* wire output port has only 1 pin */ + module_name_prefix, + des_pb_graph_pin, + OUTPUT2OUTPUT_INTERC); + break; + } + case COMPLETE_INTERC: + case MUX_INTERC: { + /* Check: MUX should have at least 2 fan_in */ + VTR_ASSERT((2 == fan_in)||(2 < fan_in)); + /* Ensure that circuit model is a MUX */ + VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.model_type(cur_interc->circuit_model)); + /* Find the wire module in the module manager */ + ModuleId mux_module = module_manager.find_module(generate_mux_subckt_name(circuit_lib, cur_interc->circuit_model, fan_in, std::string())); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + + /* Instanciate the MUX */ + size_t mux_instance = module_manager.num_instance(pb_module, mux_module); + module_manager.add_child_module(pb_module, mux_module); + + /* Instanciate a memory module for the MUX */ + std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, + cur_interc->circuit_model, + fan_in, + std::string(verilog_mem_posfix)); + ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); + size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module); + module_manager.add_child_module(pb_module, mux_mem_module); + + /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */ + add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, + mux_module, mux_instance, + mux_mem_module, mux_mem_instance, + circuit_lib, cur_interc->circuit_model); + + /* Update memory modules and memory instance list */ + memory_modules.push_back(mux_mem_module); + memory_instances.push_back(mux_mem_instance); + + /* Ensure output port of the MUX model has only 1 pin, + * while the input port size is dependent on the architecture conext, + * no constaints on the circuit model definition + */ + VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); + + /* Create nets to wire between the MUX and PB module */ + /* Add a net to wire the inputs of the multiplexer to its source pb_graph_pin inside pb_module + * Here is a tricky part. + * Not every input edges from the destination pb_graph_pin is used in the physical_model of pb_type + * So, we will skip these input edges when building nets + */ + int mux_input_pin_id = 0; + for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (physical_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { + continue; + } + /* Ensure that the input edge has only 1 input pin! */ + check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); + t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + /* Add a net, set its source and sink */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + mux_module, mux_instance, + circuit_lib.port_lib_name(interc_model_inputs[0]), + mux_input_pin_id, + module_name_prefix, + src_pb_graph_pin, + INPUT2INPUT_INTERC); + mux_input_pin_id++; + } + /* Ensure all the fan_in has been covered */ + VTR_ASSERT(mux_input_pin_id == fan_in); + + /* Add a net to wire the output of the multiplexer to des_pb_graph_pin */ + add_module_pb_graph_pin2pin_net(module_manager, pb_module, + mux_module, mux_instance, + circuit_lib.port_lib_name(interc_model_outputs[0]), + 0, /* MUX should have only 1 pin in its output port */ + module_name_prefix, + des_pb_graph_pin, + OUTPUT2OUTPUT_INTERC); + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid interconnection type for %s [at Architecture XML LINE%d]!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } +} + +/******************************************************************** + * Add modules and nets for programmable/non-programmable interconnections + * which end to a port of pb_module + * This function will add the following elements to a module + * 1. Instances of direct connections + * 2. Instances of programmable routing multiplexers + * 3. nets to connect direct connections/multiplexer + * + * +-----------------------------------------+ + * | + * | +--------------+ +------------+ + * |--->| |--->| | + * |... | Multiplexers |... | | + * |--->| |--->| | + * | +--------------+ | des_pb_ | + * | | graph_node | + * | +--------------+ | | + * |--->| |--->| | + * | ...| Direct |... | | + * |--->| Connections |--->| | + * | +--------------+ +------------+ + * | + * +----------------------------------------+ + + * + * Note: this function should be run after ALL the child pb_modules + * have been added to the pb_module and ALL the ports defined + * in pb_type have been added to the pb_module!!! + * + ********************************************************************/ +static +void add_module_pb_graph_port_interc(ModuleManager& module_manager, + const ModuleId& pb_module, + std::vector& memory_modules, + std::vector& memory_instances, + const CircuitLibrary& circuit_lib, + t_pb_graph_node* des_pb_graph_node, + const std::string& module_name_prefix, + const e_spice_pb_port_type& pb_port_type, + t_mode* physical_mode) { + switch (pb_port_type) { + case SPICE_PB_PORT_INPUT: { + for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { + /* Get the selected edge of current pin*/ + add_module_pb_graph_pin_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, + module_name_prefix, + &(des_pb_graph_node->input_pins[iport][ipin]), + physical_mode); + } + } + break; + } + case SPICE_PB_PORT_OUTPUT: { + for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { + add_module_pb_graph_pin_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, + module_name_prefix, + &(des_pb_graph_node->output_pins[iport][ipin]), + physical_mode); + } + } + break; + } + case SPICE_PB_PORT_CLOCK: { + for (int iport = 0; iport < des_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_clock_pins[iport]; ++ipin) { + add_module_pb_graph_pin_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, + module_name_prefix, + &(des_pb_graph_node->clock_pins[iport][ipin]), + physical_mode); + } + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid pb port type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * TODO: + * Add modules and nets for programmable/non-programmable interconnections + * inside a module of pb_type + * This function will add the following elements to a module + * 1. Instances of direct connections + * 2. Instances of programmable routing multiplexers + * 3. nets to connect direct connections/multiplexer + * + * Pb_module + * +--------------------------------------------------------------+ + * | | + * | +--------------+ +------------+ +--------------+ | + * |--->| |--->| |--->| |--->| + * |... | Multiplexers |... | |... | Multiplexers |... | + * |--->| |--->| |--->| |--->| + * | +--------------+ | Child | +--------------+ | + * | | Pb_modules | | + * | +--------------+ | | +--------------+ | + * |--->| |--->| |--->| |--->| + * | ...| Direct |... | |... | Direct |... | + * |--->| Connections |--->| |--->| Connections |--->| + * | +--------------+ +------------+ +--------------+ | + * | | + * +--------------------------------------------------------------+ + * + * Note: this function should be run after ALL the child pb_modules + * have been added to the pb_module and ALL the ports defined + * in pb_type have been added to the pb_module!!! + * + ********************************************************************/ +static +void add_module_pb_graph_interc(ModuleManager& module_manager, + const ModuleId& pb_module, + std::vector& memory_modules, + std::vector& memory_instances, + const CircuitLibrary& circuit_lib, + t_pb_graph_node* physical_pb_graph_node, + const std::string& module_name_prefix, + const int& physical_mode_index) { + /* Check cur_pb_graph_node*/ + if (NULL == physical_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Assign physical mode */ + t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + add_module_pb_graph_port_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, + physical_pb_graph_node, + module_name_prefix, + SPICE_PB_PORT_OUTPUT, + physical_mode); + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (int child = 0; child < physical_pb_graph_node->pb_type->modes[physical_mode_index].num_pb_type_children; ++child) { + for (int inst = 0; inst < physical_pb_graph_node->pb_type->modes[physical_mode_index].pb_type_children[child].num_pb; ++inst) { + t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][child][inst]); + /* For each child_pb_graph_node input pins*/ + add_module_pb_graph_port_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, + child_pb_graph_node, + module_name_prefix, + SPICE_PB_PORT_INPUT, + physical_mode); + + /* For each child_pb_graph_node clock pins*/ + add_module_pb_graph_port_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, + child_pb_graph_node, + module_name_prefix, + SPICE_PB_PORT_CLOCK, + physical_mode); + } + } +} + +/******************************************************************** + * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) + * This function will traverse the graph of complex logic block (t_pb_graph_node) + * in a recursive way, using a Depth First Search (DFS) algorithm. + * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph + * will be printed out first, while the top-level will be printed out in the last + * + * Note: this function will print a unique Verilog module for each type of + * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly + * hierarchical Verilog organization as well as simplify the Verilog file sizes. + * + * Note: DFS is the right way. Do NOT use BFS. + * DFS can guarantee that all the sub-modules can be registered properly + * to its parent in module manager + *******************************************************************/ +static +void rec_build_physical_block_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + t_pb_graph_node* physical_pb_graph_node, + const e_side& io_side) { + /* Check cur_pb_graph_node*/ + if (NULL == physical_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get the pb_type definition related to the node */ + t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + /* Find the mode that physical implementation of a pb_type */ + int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type)); + + /* For non-leaf node in the pb_type graph: + * Recursively Depth-First Generate all the child pb_type at the level + */ + if (FALSE == is_primitive_pb_type(physical_pb_type)) { + for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { + /* Go recursive to visit the children */ + rec_build_physical_block_modules(module_manager, circuit_lib, mux_lib, + sram_orgz_type, sram_model, + &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), + io_side); + } + } + + /* For leaf node, a primitive Verilog module will be generated */ + if (TRUE == is_primitive_pb_type(physical_pb_type)) { + build_primitive_block_module(module_manager, circuit_lib, + sram_orgz_type, sram_model, + physical_pb_graph_node, + io_side); + /* Finish for primitive node, return */ + return; + } + + /* Generate the name of the Verilog module for this pb_type */ + std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); + std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); + + /* Register the Verilog module in module manager */ + ModuleId pb_module = module_manager.add_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); + + /* Add ports to the Verilog module */ + add_pb_type_ports_to_module_manager(module_manager, pb_module, physical_pb_type); + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* Add all the child Verilog modules as instances */ + for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { + /* Get the name and module id for this child pb_type */ + std::string child_pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); + ModuleId child_pb_module = module_manager.find_module(child_pb_module_name); + /* We must have one valid id! */ + VTR_ASSERT(true == module_manager.valid_module_id(child_pb_module)); + + /* Each child may exist multiple times in the hierarchy*/ + for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { + size_t child_instance_id = module_manager.num_instance(pb_module, child_pb_module); + /* Ensure the instance of this child module is the same as placement index, + * This check is necessary because placement_index is used to identify instance id for children + * when adding local interconnection for this pb_type + */ + VTR_ASSERT(child_instance_id == (size_t)physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst].placement_index); + + /* Add the memory module as a child of primitive module */ + module_manager.add_child_module(pb_module, child_pb_module); + /* Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, child_pb_module, + circuit_lib, sram_model, + sram_orgz_type)) { + memory_modules.push_back(child_pb_module); + memory_instances.push_back(child_instance_id); + } + } + } + + /* Add modules and nets for programmable/non-programmable interconnections + * inside the Verilog module + */ + add_module_pb_graph_interc(module_manager, pb_module, + memory_modules, memory_instances, + circuit_lib, physical_pb_graph_node, + pb_module_name_prefix, + physical_mode_index); + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, pb_module); + + /* Count GPIO ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + add_module_gpio_ports_from_child_modules(module_manager, pb_module); + + /* Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, pb_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, pb_module, module_num_shared_config_bits); + } + + /* Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); + } + + /* Add module nets to connect memory cells inside + * This is a one-shot addition that covers all the memory modules in this pb module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, pb_module, + memory_modules, memory_instances, + sram_orgz_type, circuit_lib.design_tech_type(sram_model)); + } +} + +/***************************************************************************** + * This function will create a Verilog file and print out a Verilog netlist + * for a type of physical block + * + * For IO blocks: + * The param 'border_side' is required, which is specify which side of fabric + * the I/O block locates at. + *****************************************************************************/ +static +void build_grid_module(ModuleManager& module_manager, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + t_type_ptr phy_block_type, + const e_side& border_side) { + /* Check code: if this is an IO block, the border side MUST be valid */ + if (IO_TYPE == phy_block_type) { + VTR_ASSERT(NUM_SIDES != border_side); + } + + /* Build modules for all the pb_types/pb_graph_nodes + * use a Depth-First Search Algorithm to print the sub-modules + * Note: DFS is the right way. Do NOT use BFS. + * DFS can guarantee that all the sub-modules can be registered properly + * to its parent in module manager + */ + /* Build modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ + rec_build_physical_block_modules(module_manager, circuit_lib, mux_lib, + sram_orgz_type, sram_model, + phy_block_type->pb_graph_head, + border_side); + + /* Create a Verilog Module for the top-level physical block, and add to module manager */ + std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); + ModuleId grid_module = module_manager.add_module(grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* Generate the name of the Verilog module for this pb_type */ + std::string pb_module_name_prefix(grid_verilog_file_name_prefix); + std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side); + ModuleId pb_module = module_manager.find_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); + + /* Add all the sub modules */ + for (int iz = 0; iz < phy_block_type->capacity; ++iz) { + size_t pb_instance_id = module_manager.num_instance(grid_module, pb_module); + module_manager.add_child_module(grid_module, pb_module); + /* Identify if this sub module includes configuration bits, + * we will update the memory module and instance list + */ + if (0 < find_module_num_config_bits(module_manager, pb_module, + circuit_lib, sram_model, + sram_orgz_type)) { + memory_modules.push_back(pb_module); + memory_instances.push_back(pb_instance_id); + } + } + + /* Add grid ports(pins) to the module */ + add_grid_module_pb_type_ports(module_manager, grid_module, + phy_block_type, border_side); + + /* Add module nets to connect the pb_type ports to sub modules */ + for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { + add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, + pb_module, child_instance, + phy_block_type, border_side); + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, grid_module); + + /* Count GPIO ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + add_module_gpio_ports_from_child_modules(module_manager, grid_module); + + /* Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, grid_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, grid_module, module_num_shared_config_bits); + } + + /* Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); + } + + /* Add module nets to connect memory cells inside + * This is a one-shot addition that covers all the memory modules in this pb module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, grid_module, + memory_modules, memory_instances, + sram_orgz_type, circuit_lib.design_tech_type(sram_model)); + } +} + +/***************************************************************************** + * Create logic block modules in a compact way: + * 1. Only one module for each I/O on each border side (IO_TYPE) + * 2. Only one module for each CLB (FILL_TYPE) + * 3. Only one module for each heterogeneous block + ****************************************************************************/ +void build_grid_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model) { + /* Enumerate the types, dump one Verilog module for each */ + for (int itype = 0; itype < num_types; itype++) { + if (EMPTY_TYPE == &type_descriptors[itype]) { + /* Bypass empty type or NULL */ + continue; + } else if (IO_TYPE == &type_descriptors[itype]) { + /* Special for I/O block, generate one module for each border side */ + for (int iside = 0; iside < NUM_SIDES; iside++) { + Side side_manager(iside); + build_grid_module(module_manager, mux_lib, circuit_lib, + sram_orgz_type, sram_model, + &type_descriptors[itype], + side_manager.get_side()); + } + continue; + } else if (FILL_TYPE == &type_descriptors[itype]) { + /* For CLB */ + build_grid_module(module_manager, mux_lib, circuit_lib, + sram_orgz_type, sram_model, + &type_descriptors[itype], + NUM_SIDES); + continue; + } else { + /* For heterogenenous blocks */ + build_grid_module(module_manager, mux_lib, circuit_lib, + sram_orgz_type, sram_model, + &type_descriptors[itype], + NUM_SIDES); + } + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h new file mode 100644 index 000000000..ad1880e1c --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h @@ -0,0 +1,18 @@ +/******************************************************************** + * Header file for build_grid_modules.cpp + *******************************************************************/ +#ifndef BUILD_GRID_MODULES_H +#define BUILD_GRID_MODULES_H + +/* Only include headers related to the data structures used in the following function declaration */ +#include "vpr_types.h" +#include "module_manager.h" +#include "mux_library.h" + +void build_grid_modules(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h index 3597c5d95..276fa4fad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h @@ -1,9 +1,9 @@ /*********************************************** - * Header file for verilog_memory.cpp + * Header file for build_memory_modules.cpp **********************************************/ -#ifndef BUILD_MEMORY_MODULE_H -#define BUILD_MEMORY_MODULE_H +#ifndef BUILD_MEMORY_MODULES_H +#define BUILD_MEMORY_MODULES_H /* Include other header files which are dependency on the function declared below */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index 666e42876..ad9ac0098 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -16,6 +16,7 @@ #include "build_lut_modules.h" #include "build_wire_modules.h" #include "build_memory_modules.h" +#include "build_grid_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -63,7 +64,7 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, config_spice_models_sram_port_spice_model(arch.spice->num_spice_model, arch.spice->spice_models, arch.sram_inf.verilog_sram_inf_orgz->spice_model); - config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model); + config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, sram_model); /* Create a vector of segments. TODO: should come from DeviceContext */ std::vector L_segment_vec; @@ -99,7 +100,9 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->type); - /* TODO: Build grid and programmable block modules */ + /* Build grid and programmable block modules */ + build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib, + arch.sram_inf.verilog_sram_inf_orgz->type, sram_model); /* TODO: Build global routing architecture modules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index b2ecbae94..fae787353 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -294,8 +294,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager, lb_dir_path, Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); - print_verilog_grids(module_manager, Arch.spice->circuit_lib, mux_lib, - sram_verilog_orgz_info, + print_verilog_grids(module_manager, std::string(src_dir_path), std::string(lb_dir_path), TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 4d377a115..a7a7f877d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -31,209 +31,6 @@ #include "verilog_module_writer.h" #include "verilog_grid.h" -/******************************************************************** - * Find the side where I/O pins locate on a grid I/O block - * 1. I/O grids on the top side of FPGA only have ports on its bottom side - * 2. I/O grids on the right side of FPGA only have ports on its left side - * 3. I/O grids on the bottom side of FPGA only have ports on its top side - * 4. I/O grids on the left side of FPGA only have ports on its right side - *******************************************************************/ -static -e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor, - const e_side& border_side) { - VTR_ASSERT(IO_TYPE == grid_type_descriptor); - Side side_manager(border_side); - return side_manager.get_opposite(); -} - -/******************************************************************** - * Add ports/pins to a grid module - * This function will iterate over all the pins that are defined - * in type_descripter and give a name by its height, side and index - * - * In particular, for I/O grid, only part of the ports on required - * on a specific side. - *******************************************************************/ -static -void add_grid_module_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - t_type_ptr grid_type_descriptor, - const e_side& border_side) { - /* Ensure that we have a valid grid_type_descriptor */ - VTR_ASSERT(NULL != grid_type_descriptor); - - /* Find the pin side for I/O grids*/ - std::vector grid_pin_sides; - /* For I/O grids, we care only one side - * Otherwise, we will iterate all the 4 sides - */ - if (IO_TYPE == grid_type_descriptor) { - grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); - } else { - grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; - } - - /* Create a map between pin class type and grid pin direction */ - std::map pin_type2type_map; - pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT; - pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT; - - /* Iterate over sides, height and pins */ - for (const e_side& side : grid_pin_sides) { - for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) { - for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) { - if (1 != grid_type_descriptor->pinloc[iheight][side][ipin]) { - continue; - } - /* Reach here, it means this pin is on this side */ - int class_id = grid_type_descriptor->pin_class[ipin]; - e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; - /* Generate the pin name, - * we give a empty coordinate but it will not be used (see details in the function - */ - vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false); - BasicPort grid_port(port_name, 0, 0); - /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); - } - } - } -} - -/******************************************************************** - * Add module nets to connect a port of child pb_module - * to the grid module - *******************************************************************/ -static -void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, - const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { - /* Find the pin side for I/O grids*/ - std::vector grid_pin_sides; - /* For I/O grids, we care only one side - * Otherwise, we will iterate all the 4 sides - */ - if (IO_TYPE == grid_type_descriptor) { - grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); - } else { - grid_pin_sides.push_back(TOP); - grid_pin_sides.push_back(RIGHT); - grid_pin_sides.push_back(BOTTOM); - grid_pin_sides.push_back(LEFT); - } - - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster - + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity; - int pin_height = grid_type_descriptor->pin_height[grid_pin_index]; - for (const e_side& side : grid_pin_sides) { - if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - continue; - } - /* Reach here, it means this pin is on this side */ - /* Create a net to connect the grid pin to child module pin */ - ModuleNetId net = module_manager.create_module_net(grid_module); - /* Find the port in grid_module */ - vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false); - ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); - /* Grid port always has only 1 pin, it is assumed when adding these ports to the module - * if you need a change, please also change the port adding codes - */ - size_t grid_module_pin_id = 0; - /* Find the port in child module */ - std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); - ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); - size_t child_module_pin_id = pb_graph_pin->pin_number; - /* Add net sources and sinks: - * For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin - * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin - */ - switch (pin2pin_interc_type) { - case INPUT2INPUT_INTERC: - module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); - break; - case OUTPUT2OUTPUT_INTERC: - module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } - } -} - - -/******************************************************************** - * Add module nets to connect ports/pins of a grid module - * to its child modules - * This function will iterate over all the pins that are defined - * in type_descripter and find the corresponding pin in the top - * pb_graph_node of the grid - *******************************************************************/ -static -void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - const e_side& border_side) { - /* Ensure that we have a valid grid_type_descriptor */ - VTR_ASSERT(NULL != grid_type_descriptor); - t_pb_graph_node* top_pb_graph_node = grid_type_descriptor->pb_graph_head; - VTR_ASSERT(NULL != top_pb_graph_node); - - for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, - INPUT2INPUT_INTERC); - - } - } - - for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, - OUTPUT2OUTPUT_INTERC); - } - } - - for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, - INPUT2INPUT_INTERC); - } - } -} - /******************************************************************** * Print Verilog modules of a primitive node in the pb_graph_node graph * This generic function can support all the different types of primitive nodes @@ -263,8 +60,6 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, static void print_verilog_primitive_block(std::fstream& fp, ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* primitive_pb_graph_node, const e_side& io_side, const bool& use_explicit_mapping) { @@ -279,110 +74,14 @@ void print_verilog_primitive_block(std::fstream& fp, exit(1); } - /* Find the circuit model id linked to the pb_graph_node */ - CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model; - /* Generate the module name for this primitive pb_graph_node*/ std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); /* Create a module of the primitive LUT and register it to module manager */ - ModuleId primitive_module = module_manager.add_module(primitive_module_name); + ModuleId primitive_module = module_manager.find_module(primitive_module_name); /* Ensure that the module has been created and thus unique! */ - VTR_ASSERT(ModuleId::INVALID() != primitive_module); - - /* Find the global ports required by the primitive node, and add them to the module */ - std::vector primitive_model_global_ports = circuit_lib.model_global_ports(primitive_model, true); - for (auto port : primitive_model_global_ports) { - /* The global I/O of the FPGA has a special name */ - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GLOBAL_PORT); - } - - /* Find the inout ports required by the primitive node, and add them to the module - * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric - */ - if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { - std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); - for (auto port : primitive_model_inout_ports) { - BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); - } - } - /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here. - * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P, - * no ports of the circuit model will be missing here - */ - add_primitive_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); - - /* Add configuration ports */ - /* Shared SRAM ports*/ - size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, cur_sram_orgz_info->type); - if (0 < num_shared_config_bits) { - /* Check: this SRAM organization type must be memory-bank ! */ - VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); - /* Generate a list of ports */ - add_reserved_sram_ports_to_module_manager(module_manager, primitive_module, - num_shared_config_bits); - } - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Regular (independent) SRAM ports */ - size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model); - if (0 < num_config_bits) { - add_sram_ports_to_module_manager(module_manager, primitive_module, - circuit_lib, sram_model, cur_sram_orgz_info->type, - num_config_bits); - } - - /* Find the module id in the module manager */ - ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model)); - VTR_ASSERT(ModuleId::INVALID() != logic_module); - size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); - /* Add the logic module as a child of primitive module */ - module_manager.add_child_module(primitive_module, logic_module); - - /* Add nets to connect the logic model ports to pb_type ports */ - add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); - - /* Add the associated memory module as a child of primitive module */ - std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix)); - ModuleId memory_module = module_manager.find_module(memory_module_name); - - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - - /* If there is no memory module required, we can skip the assocated net addition */ - if (ModuleId::INVALID() != memory_module) { - size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); - /* Add the memory module as a child of primitive module */ - module_manager.add_child_module(primitive_module, memory_module); - - /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ - add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module, - logic_module, logic_instance_id, - memory_module, memory_instance_id, - circuit_lib, primitive_model); - /* Record memory-related information */ - memory_modules.push_back(memory_module); - memory_instances.push_back(memory_instance_id); - } - /* Add all the nets to connect configuration ports from memory module to primitive modules - * This is a one-shot addition that covers all the memory modules in this primitive module! - */ - if (false == memory_modules.empty()) { - add_module_nets_memory_config_bus(module_manager, primitive_module, - memory_modules, memory_instances, - cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); - } + VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); /* Write the verilog module */ write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping); @@ -391,440 +90,6 @@ void print_verilog_primitive_block(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * This function add a net for a pin-to-pin connection defined in pb_graph - * It supports two cases for the pin-to-pin connection - * 1. The net source is a pb_graph_pin while the net sink is a pin of an interconnection - * 2. The net source is a pin of an interconnection while the net sink a pb_graph_pin - * The type is enabled by an argument pin2pin_interc_type - *******************************************************************/ -static -void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, - const ModuleId& pb_module, - const ModuleId& interc_module, - const size_t& interc_instance, - const std::string& interc_port_name, - const size_t& interc_pin_id, - const std::string& module_name_prefix, - t_pb_graph_pin* pb_graph_pin, - const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { - - ModuleNetId pin2pin_net = module_manager.create_module_net(pb_module); - - /* Find port and pin ids for the module, which is the parent of pb_graph_pin */ - t_pb_type* pin_pb_type = pb_graph_pin->parent_node->pb_type; - /* Find the module contains the source pin */ - ModuleId pin_pb_type_module = module_manager.find_module(generate_physical_block_module_name(module_name_prefix, pin_pb_type)); - VTR_ASSERT(true == module_manager.valid_module_id(pin_pb_type_module)); - size_t pin_pb_type_instance = 0; /* Deposite the instance with a zero, which is the default value is the source module is actually pb_module itself */ - if (pin_pb_type_module != pb_module) { - pin_pb_type_instance = pb_graph_pin->parent_node->placement_index; - /* Ensure this is an valid instance */ - VTR_ASSERT(pin_pb_type_instance < module_manager.num_instance(pb_module, pin_pb_type_module)); - } - ModulePortId pin_module_port_id = module_manager.find_module_port(pin_pb_type_module, generate_pb_type_port_name(pb_graph_pin->port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(pin_pb_type_module, pin_module_port_id)); - size_t pin_module_pin_id = pb_graph_pin->pin_number; - /* Ensure this is an valid pin index */ - VTR_ASSERT(pin_module_pin_id < module_manager.module_port(pin_pb_type_module, pin_module_port_id).get_width()); - - /* Find port and pin ids for the interconnection module */ - ModulePortId interc_port_id = module_manager.find_module_port(interc_module, interc_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(interc_module, interc_port_id)); - /* Ensure this is an valid pin index */ - VTR_ASSERT(interc_pin_id < module_manager.module_port(interc_module, interc_port_id).get_width()); - - /* Add net sources and sinks: - * For input-to-input connection, net_source is pin_graph_pin, while net_sink is interc pin - * For output-to-output connection, net_source is interc pin, while net_sink is pin_graph pin - */ - switch (pin2pin_interc_type) { - case INPUT2INPUT_INTERC: - module_manager.add_module_net_source(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); - module_manager.add_module_net_sink(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); - break; - case OUTPUT2OUTPUT_INTERC: - module_manager.add_module_net_source(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); - module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins - * /|\ - * | - * input_pins, edges, output_pins - * - * This function does the following task: - * 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Add mux/direct connection as a child module to pb_module - * 4. Add nets related to the mux/direction - *******************************************************************/ -static -void add_module_pb_graph_pin_interc(ModuleManager& module_manager, - const ModuleId& pb_module, - std::vector& memory_modules, - std::vector& memory_instances, - const CircuitLibrary& circuit_lib, - const std::string& module_name_prefix, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* physical_mode) { - /* Find the number of fan-in and detailed interconnection information - * related to the destination pb_graph_pin - */ - int fan_in = 0; - t_interconnect* cur_interc = NULL; - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); - - /* If no interconnection is needed, we can return early */ - if ((NULL == cur_interc) || (0 == fan_in)) { - return; - } - - /* Initialize the interconnection type that will be physically implemented in module */ - enum e_interconnect verilog_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); - - /* Find input ports of the wire module */ - std::vector interc_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ - /* Find output ports of the wire module */ - std::vector interc_model_outputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */ - - /* Ensure that we have only 1 input port and 1 output port, this is valid for both wire and MUX */ - VTR_ASSERT(1 == interc_model_inputs.size()); - VTR_ASSERT(1 == interc_model_outputs.size()); - - /* Branch on the type of physical implementation, - * We add instances of programmable interconnection - */ - switch (verilog_interc_type) { - case DIRECT_INTERC: { - /* Ensure direct interc has only one fan-in */ - VTR_ASSERT(1 == fan_in); - - /* For more than one mode defined, the direct interc has more than one input_edge , - * We need to find which edge is connected the pin we want - */ - int iedge = 0; - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { - break; - } - } - t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - - /* Ensure that circuit model is a wire */ - VTR_ASSERT(SPICE_MODEL_WIRE == circuit_lib.model_type(cur_interc->circuit_model)); - /* Find the wire module in the module manager */ - ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(cur_interc->circuit_model)); - VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); - /* Get the instance id and add an instance of wire */ - size_t wire_instance = module_manager.num_instance(pb_module, wire_module); - module_manager.add_child_module(pb_module, wire_module); - - /* Ensure input and output ports of the wire model has only 1 pin respectively */ - VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0])); - VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); - - /* Add nets to connect the wires to ports of pb_module */ - /* First net is to connect input of src_pb_graph_node to input of the wire module */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - wire_module, wire_instance, - circuit_lib.port_lib_name(interc_model_inputs[0]), - 0, /* wire input port has only 1 pin */ - module_name_prefix, - src_pb_graph_pin, - INPUT2INPUT_INTERC); - - /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - wire_module, wire_instance, - circuit_lib.port_lib_name(interc_model_outputs[0]), - 0, /* wire output port has only 1 pin */ - module_name_prefix, - des_pb_graph_pin, - OUTPUT2OUTPUT_INTERC); - break; - } - case COMPLETE_INTERC: - case MUX_INTERC: { - /* Check: MUX should have at least 2 fan_in */ - VTR_ASSERT((2 == fan_in)||(2 < fan_in)); - /* Ensure that circuit model is a MUX */ - VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.model_type(cur_interc->circuit_model)); - /* Find the wire module in the module manager */ - ModuleId mux_module = module_manager.find_module(generate_mux_subckt_name(circuit_lib, cur_interc->circuit_model, fan_in, std::string())); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - - /* Instanciate the MUX */ - size_t mux_instance = module_manager.num_instance(pb_module, mux_module); - module_manager.add_child_module(pb_module, mux_module); - - /* Instanciate a memory module for the MUX */ - std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, - cur_interc->circuit_model, - fan_in, - std::string(verilog_mem_posfix)); - ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); - size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module); - module_manager.add_child_module(pb_module, mux_mem_module); - - /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */ - add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, - mux_module, mux_instance, - mux_mem_module, mux_mem_instance, - circuit_lib, cur_interc->circuit_model); - - /* Update memory modules and memory instance list */ - memory_modules.push_back(mux_mem_module); - memory_instances.push_back(mux_mem_instance); - - /* Ensure output port of the MUX model has only 1 pin, - * while the input port size is dependent on the architecture conext, - * no constaints on the circuit model definition - */ - VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); - - /* Create nets to wire between the MUX and PB module */ - /* Add a net to wire the inputs of the multiplexer to its source pb_graph_pin inside pb_module - * Here is a tricky part. - * Not every input edges from the destination pb_graph_pin is used in the physical_model of pb_type - * So, we will skip these input edges when building nets - */ - int mux_input_pin_id = 0; - for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (physical_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - continue; - } - /* Ensure that the input edge has only 1 input pin! */ - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - /* Add a net, set its source and sink */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - mux_module, mux_instance, - circuit_lib.port_lib_name(interc_model_inputs[0]), - mux_input_pin_id, - module_name_prefix, - src_pb_graph_pin, - INPUT2INPUT_INTERC); - mux_input_pin_id++; - } - /* Ensure all the fan_in has been covered */ - VTR_ASSERT(mux_input_pin_id == fan_in); - - /* Add a net to wire the output of the multiplexer to des_pb_graph_pin */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - mux_module, mux_instance, - circuit_lib.port_lib_name(interc_model_outputs[0]), - 0, /* MUX should have only 1 pin in its output port */ - module_name_prefix, - des_pb_graph_pin, - OUTPUT2OUTPUT_INTERC); - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid interconnection type for %s [at Architecture XML LINE%d]!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } -} - -/******************************************************************** - * Add modules and nets for programmable/non-programmable interconnections - * which end to a port of pb_module - * This function will add the following elements to a module - * 1. Instances of direct connections - * 2. Instances of programmable routing multiplexers - * 3. nets to connect direct connections/multiplexer - * - * +-----------------------------------------+ - * | - * | +--------------+ +------------+ - * |--->| |--->| | - * |... | Multiplexers |... | | - * |--->| |--->| | - * | +--------------+ | des_pb_ | - * | | graph_node | - * | +--------------+ | | - * |--->| |--->| | - * | ...| Direct |... | | - * |--->| Connections |--->| | - * | +--------------+ +------------+ - * | - * +----------------------------------------+ - - * - * Note: this function should be run after ALL the child pb_modules - * have been added to the pb_module and ALL the ports defined - * in pb_type have been added to the pb_module!!! - * - ********************************************************************/ -static -void add_module_pb_graph_port_interc(ModuleManager& module_manager, - const ModuleId& pb_module, - std::vector& memory_modules, - std::vector& memory_instances, - const CircuitLibrary& circuit_lib, - t_pb_graph_node* des_pb_graph_node, - const std::string& module_name_prefix, - const e_spice_pb_port_type& pb_port_type, - t_mode* physical_mode) { - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: { - for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { - /* Get the selected edge of current pin*/ - add_module_pb_graph_pin_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - module_name_prefix, - &(des_pb_graph_node->input_pins[iport][ipin]), - physical_mode); - } - } - break; - } - case SPICE_PB_PORT_OUTPUT: { - for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { - add_module_pb_graph_pin_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - module_name_prefix, - &(des_pb_graph_node->output_pins[iport][ipin]), - physical_mode); - } - } - break; - } - case SPICE_PB_PORT_CLOCK: { - for (int iport = 0; iport < des_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_clock_pins[iport]; ++ipin) { - add_module_pb_graph_pin_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - module_name_prefix, - &(des_pb_graph_node->clock_pins[iport][ipin]), - physical_mode); - } - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * TODO: - * Add modules and nets for programmable/non-programmable interconnections - * inside a module of pb_type - * This function will add the following elements to a module - * 1. Instances of direct connections - * 2. Instances of programmable routing multiplexers - * 3. nets to connect direct connections/multiplexer - * - * Pb_module - * +--------------------------------------------------------------+ - * | | - * | +--------------+ +------------+ +--------------+ | - * |--->| |--->| |--->| |--->| - * |... | Multiplexers |... | |... | Multiplexers |... | - * |--->| |--->| |--->| |--->| - * | +--------------+ | Child | +--------------+ | - * | | Pb_modules | | - * | +--------------+ | | +--------------+ | - * |--->| |--->| |--->| |--->| - * | ...| Direct |... | |... | Direct |... | - * |--->| Connections |--->| |--->| Connections |--->| - * | +--------------+ +------------+ +--------------+ | - * | | - * +--------------------------------------------------------------+ - * - * Note: this function should be run after ALL the child pb_modules - * have been added to the pb_module and ALL the ports defined - * in pb_type have been added to the pb_module!!! - * - ********************************************************************/ -static -void add_module_pb_graph_interc(ModuleManager& module_manager, - const ModuleId& pb_module, - std::vector& memory_modules, - std::vector& memory_instances, - const CircuitLibrary& circuit_lib, - t_pb_graph_node* physical_pb_graph_node, - const std::string& module_name_prefix, - const int& physical_mode_index) { - /* Check cur_pb_graph_node*/ - if (NULL == physical_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Assign physical mode */ - t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]); - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - add_module_pb_graph_port_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - physical_pb_graph_node, - module_name_prefix, - SPICE_PB_PORT_OUTPUT, - physical_mode); - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (int child = 0; child < physical_pb_graph_node->pb_type->modes[physical_mode_index].num_pb_type_children; ++child) { - for (int inst = 0; inst < physical_pb_graph_node->pb_type->modes[physical_mode_index].pb_type_children[child].num_pb; ++inst) { - t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][child][inst]); - /* For each child_pb_graph_node input pins*/ - add_module_pb_graph_port_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - child_pb_graph_node, - module_name_prefix, - SPICE_PB_PORT_INPUT, - physical_mode); - - /* For each child_pb_graph_node clock pins*/ - add_module_pb_graph_port_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - child_pb_graph_node, - module_name_prefix, - SPICE_PB_PORT_CLOCK, - physical_mode); - } - } -} - /******************************************************************** * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) * This function will traverse the graph of complex logic block (t_pb_graph_node) @@ -843,9 +108,6 @@ void add_module_pb_graph_interc(ModuleManager& module_manager, static void print_verilog_physical_blocks_rec(std::fstream& fp, ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* physical_pb_graph_node, const e_side& io_side, const bool& use_explicit_mapping) { @@ -872,8 +134,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, if (FALSE == is_primitive_pb_type(physical_pb_type)) { for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { /* Go recursive to visit the children */ - print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, - cur_sram_orgz_info, + print_verilog_physical_blocks_rec(fp, module_manager, &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), io_side, use_explicit_mapping); @@ -882,8 +143,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, /* For leaf node, a primitive Verilog module will be generated */ if (TRUE == is_primitive_pb_type(physical_pb_type)) { - print_verilog_primitive_block(fp, module_manager, circuit_lib, - cur_sram_orgz_info, + print_verilog_primitive_block(fp, module_manager, physical_pb_graph_node, io_side, use_explicit_mapping); @@ -896,102 +156,8 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); /* Register the Verilog module in module manager */ - ModuleId pb_module = module_manager.add_module(pb_module_name); - VTR_ASSERT(ModuleId::INVALID() != pb_module); - - /* Add ports to the Verilog module */ - add_pb_type_ports_to_module_manager(module_manager, pb_module, physical_pb_type); - - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Add all the child Verilog modules as instances */ - for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { - /* Get the name and module id for this child pb_type */ - std::string child_pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); - ModuleId child_pb_module = module_manager.find_module(child_pb_module_name); - /* We must have one valid id! */ - VTR_ASSERT(true == module_manager.valid_module_id(child_pb_module)); - - /* Each child may exist multiple times in the hierarchy*/ - for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - size_t child_instance_id = module_manager.num_instance(pb_module, child_pb_module); - /* Ensure the instance of this child module is the same as placement index, - * This check is necessary because placement_index is used to identify instance id for children - * when adding local interconnection for this pb_type - */ - VTR_ASSERT(child_instance_id == (size_t)physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst].placement_index); - - /* Add the memory module as a child of primitive module */ - module_manager.add_child_module(pb_module, child_pb_module); - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, child_pb_module, - circuit_lib, sram_model, - cur_sram_orgz_info->type)) { - memory_modules.push_back(child_pb_module); - memory_instances.push_back(child_instance_id); - } - } - } - - /* Add modules and nets for programmable/non-programmable interconnections - * inside the Verilog module - */ - add_module_pb_graph_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, physical_pb_graph_node, - pb_module_name_prefix, - physical_mode_index); - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, pb_module); - - /* Count GPIO ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - add_module_gpio_ports_from_child_modules(module_manager, pb_module); - - /* Count shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, pb_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, pb_module, module_num_shared_config_bits); - } - - /* Count SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); - } - - /* Add module nets to connect memory cells inside - * This is a one-shot addition that covers all the memory modules in this pb module! - */ - if (false == memory_modules.empty()) { - add_module_nets_memory_config_bus(module_manager, pb_module, - memory_modules, memory_instances, - cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); - } + ModuleId pb_module = module_manager.find_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); /* Comment lines */ print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); @@ -1015,9 +181,6 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, *****************************************************************************/ static void print_verilog_grid(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& verilog_dir, const std::string& subckt_dir, t_type_ptr phy_block_type, @@ -1072,8 +235,7 @@ void print_verilog_grid(ModuleManager& module_manager, print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ - print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib, - cur_sram_orgz_info, + print_verilog_physical_blocks_rec(fp, module_manager, phy_block_type->pb_graph_head, border_side, use_explicit_mapping); @@ -1082,92 +244,9 @@ void print_verilog_grid(ModuleManager& module_manager, /* Create a Verilog Module for the top-level physical block, and add to module manager */ std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); - ModuleId grid_module = module_manager.add_module(grid_module_name); + ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix(grid_verilog_file_name_prefix); - std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side); - ModuleId pb_module = module_manager.find_module(pb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - - /* Add all the sub modules */ - for (int iz = 0; iz < phy_block_type->capacity; ++iz) { - size_t pb_instance_id = module_manager.num_instance(grid_module, pb_module); - module_manager.add_child_module(grid_module, pb_module); - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, pb_module, - circuit_lib, sram_model, - cur_sram_orgz_info->type)) { - memory_modules.push_back(pb_module); - memory_instances.push_back(pb_instance_id); - } - } - - /* Add grid ports(pins) to the module */ - add_grid_module_pb_type_ports(module_manager, grid_module, - phy_block_type, border_side); - - /* Add module nets to connect the pb_type ports to sub modules */ - for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { - add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, - pb_module, child_instance, - phy_block_type, border_side); - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, grid_module); - - /* Count GPIO ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - add_module_gpio_ports_from_child_modules(module_manager, grid_module); - - /* Count shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, grid_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, grid_module, module_num_shared_config_bits); - } - - /* Count SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, grid_module, circuit_lib, sram_model, cur_sram_orgz_info->type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, grid_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); - } - - /* Add module nets to connect memory cells inside - * This is a one-shot addition that covers all the memory modules in this pb module! - */ - if (false == memory_modules.empty()) { - add_module_nets_memory_config_bus(module_manager, grid_module, - memory_modules, memory_instances, - cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); - } - /* Write the verilog module */ print_verilog_comment(fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); write_verilog_module_to_file(fp, module_manager, grid_module, use_explicit_mapping); @@ -1193,12 +272,9 @@ void print_verilog_grid(ModuleManager& module_manager, * 3. Only one module for each heterogeneous block ****************************************************************************/ void print_verilog_grids(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& verilog_dir, const std::string& subckt_dir, - const bool& is_explicit_mapping) { + const bool& use_explicit_mapping) { /* Enumerate the types, dump one Verilog module for each */ for (int itype = 0; itype < num_types; itype++) { if (EMPTY_TYPE == &type_descriptors[itype]) { @@ -1208,31 +284,28 @@ void print_verilog_grids(ModuleManager& module_manager, /* Special for I/O block, generate one module for each border side */ for (int iside = 0; iside < NUM_SIDES; iside++) { Side side_manager(iside); - print_verilog_grid(module_manager, mux_lib, circuit_lib, - cur_sram_orgz_info, + print_verilog_grid(module_manager, verilog_dir, subckt_dir, &type_descriptors[itype], side_manager.get_side(), - is_explicit_mapping); + use_explicit_mapping); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { /* For CLB */ - print_verilog_grid(module_manager, mux_lib, circuit_lib, - cur_sram_orgz_info, + print_verilog_grid(module_manager, verilog_dir, subckt_dir, &type_descriptors[itype], NUM_SIDES, - is_explicit_mapping); + use_explicit_mapping); continue; } else { /* For heterogenenous blocks */ - print_verilog_grid(module_manager, mux_lib, circuit_lib, - cur_sram_orgz_info, + print_verilog_grid(module_manager, verilog_dir, subckt_dir, &type_descriptors[itype], NUM_SIDES, - is_explicit_mapping); + use_explicit_mapping); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h index b99ffd430..d1bc8cdfb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h @@ -11,11 +11,8 @@ #include "mux_library.h" void print_verilog_grids(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& verilog_dir, const std::string& subckt_dir, - const bool& is_explicit_mapping); + const bool& use_explicit_mapping); #endif From dafab3907e517ee19918f440ca1e4e3d748fbb6f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Oct 2019 11:46:55 -0600 Subject: [PATCH 322/482] refactored routing module generation and verilog writing --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 23 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_types.h | 1 + .../module_builder/build_module_graph.cpp | 19 +- .../module_builder/build_module_graph.h | 7 +- .../build_module_graph_utils.cpp | 25 + .../module_builder/build_module_graph_utils.h | 11 + .../module_builder/build_routing_modules.cpp | 1166 ++++++++++ .../module_builder/build_routing_modules.h | 33 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 17 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 1952 +++-------------- .../SRC/fpga_x2p/verilog/verilog_routing.h | 20 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 6 +- 12 files changed, 1644 insertions(+), 1636 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 8ab75ad0c..099047c33 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -10,6 +10,7 @@ #include #include #include +#include /* Include vpr structs*/ #include "util.h" @@ -34,6 +35,7 @@ #include "verilog_api.h" #include "fpga_bitstream.h" +#include "fpga_x2p_globals.h" #include "fpga_x2p_api.h" /* Top-level API of FPGA-SPICE */ @@ -50,8 +52,27 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Build multiplexer graphs */ MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); + /* TODO: Build global routing architecture modules */ + /* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */ + std::vector rr_switches; + for (short i = 0; i < vpr_setup.RoutingArch.num_switch; ++i) { + rr_switches.push_back(switch_inf[i]); + } + + /* TODO: This should be done outside this function!!! */ + vtr::Point device_size(nx + 2, ny + 2); + std::vector> grids; + /* Organize a vector (matrix) of grids to feed the top-level module generation */ + grids.resize(device_size.x()); + for (size_t ix = 0; ix < device_size.x(); ++ix) { + grids[ix].resize(device_size.y()); + for (size_t iy = 0; iy < device_size.y(); ++iy) { + grids[ix][iy] = grid[ix][iy]; + } + } + /* Build module graphs */ - ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib); + ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib, grids, rr_switches, device_rr_gsb); /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h index 796707d78..982377120 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h @@ -1,6 +1,7 @@ #ifndef FPGA_X2P_TYPES_H #define FPGA_X2P_TYPES_H +#include "vpr_types.h" #include "route_common.h" /* Define the basic data structures used for FPGA-SPICE */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index ad9ac0098..f6b8c23cd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -2,6 +2,7 @@ * This file includes the main function to build module graphs * for the FPGA fabric *******************************************************************/ +#include #include #include @@ -17,6 +18,7 @@ #include "build_wire_modules.h" #include "build_memory_modules.h" #include "build_grid_modules.h" +#include "build_routing_modules.h" #include "build_module_graph.h" /******************************************************************** @@ -25,7 +27,10 @@ *******************************************************************/ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, const t_arch& arch, - const MuxLibrary& mux_lib) { + const MuxLibrary& mux_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const DeviceRRGSB& L_device_rr_gsb) { /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { vpr_printf(TIO_MESSAGE_ERROR, @@ -104,7 +109,17 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib, arch.sram_inf.verilog_sram_inf_orgz->type, sram_model); - /* TODO: Build global routing architecture modules */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { + build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, + arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, grids, + vpr_setup.RoutingArch, rr_switches); + } else { + VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); + build_flatten_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, + arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, grids, + vpr_setup.RoutingArch, rr_switches); + } + /* TODO: Build FPGA fabric top-level module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h index 3e3ad5806..2cea75913 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h @@ -1,12 +1,17 @@ #ifndef BUILD_MODULE_GRAPH_H #define BUILD_MODULE_GRAPH_H +#include #include "vpr_types.h" +#include "rr_blocks.h" #include "mux_library.h" #include "module_manager.h" ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, const t_arch& arch, - const MuxLibrary& mux_lib); + const MuxLibrary& mux_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const DeviceRRGSB& L_device_rr_gsb); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp index 6b1df195a..f58296e11 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp @@ -5,8 +5,33 @@ #include #include "vtr_assert.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_pbtypes_utils.h" #include "build_module_graph_utils.h" +/********************************************************************* + * Generate the port name for a Grid + * This is a wrapper function for generate_port_name() + * which can automatically decode the port name by the pin side and height + *********************************************************************/ +std::string generate_grid_side_port_name(const std::vector>& grids, + const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id) { + /* Output the pins on the side*/ + size_t height = find_grid_pin_height(grids, coordinate, pin_id); + if (1 != grids[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { + Side side_manager(side); + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", + __FILE__, __LINE__, + coordinate.x(), coordinate.y(), height, side_manager.c_str(), pin_id); + exit(1); + } + return generate_grid_port_name(coordinate, height, side, pin_id, true); +} + + /******************************************************************** * Find input port of a buffer/inverter module ********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h index e5b3de2ca..d4816c8e0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h @@ -4,9 +4,20 @@ #ifndef BUILD_MODULE_GRAPH_UTILS_H #define BUILD_MODULE_GRAPH_UTILS_H +#include +#include +#include "spice_types.h" +#include "sides.h" +#include "vtr_geometry.h" +#include "vpr_types.h" #include "module_manager.h" #include "circuit_library.h" +std::string generate_grid_side_port_name(const std::vector>& grids, + const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id); + ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp new file mode 100644 index 000000000..61ee8fd29 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -0,0 +1,1166 @@ +/******************************************************************** + * This file includes functions that are used to build modules + * for global routing architecture of a FPGA fabric + * Covering: + * 1. Connection blocks + * 2. Switch blocks + *******************************************************************/ +#include + +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "sides.h" +#include "util.h" +#include "device_coordinator.h" + +#include "fpga_x2p_types.h" +#include "fpga_x2p_naming.h" + +#include "fpga_x2p_utils.h" +#include "module_manager_utils.h" +#include "build_module_graph_utils.h" + +#include "build_routing_modules.h" +#include "verilog_global.h" + +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ +static +ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const PORTS& cur_rr_node_direction) { + /* Get the index in sb_info of cur_rr_node */ + int index = rr_gsb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); + /* Make sure this node is included in this sb_info */ + VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); + + DeviceCoordinator chan_rr_node_coordinator = rr_gsb.get_side_block_coordinator(chan_side); + + vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); + std::string chan_port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(chan_side, index)->type, + chan_port_coord, index, + rr_gsb.get_chan_node_direction(chan_side, index)); + + /* Must find a valid port id in the Switch Block module */ + ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, chan_port_id)); + return chan_port_id; +} + +/********************************************************************* + * Generate an input port for routing multiplexer inside the switch block + * In addition to give the Routing Resource node of the input + * Users should provide the side of input, which is different case by case: + * 1. When the input is a pin of a CLB/Logic Block, the input_side should + * be the side of the node on its grid! + * For example, the input pin is on the top side of a switch block + * but on the right side of a switch block + * +--------+ + * | | + * | Grid |---+ + * | | | + * +--------+ v input_pin + * +----------------+ + * | Switch Block | + * +----------------+ + * 2. When the input is a routing track, the input_side should be + * the side of the node locating on the switch block + ********************************************************************/ +static +ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const e_side& input_side, + t_rr_node* input_rr_node) { + /* Deposit an invalid value */ + ModulePortId input_port_id = ModulePortId::INVALID(); + /* Generate the input port object */ + switch (input_rr_node->type) { + /* case SOURCE: */ + case OPIN: { + /* Find the coordinator (grid_x and grid_y) for the input port */ + vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); + std::string input_port_name = generate_grid_side_port_name(grids, + input_port_coord, + input_side, + input_rr_node->ptc_num); + /* Must find a valid port id in the Switch Block module */ + input_port_id = module_manager.find_module_port(sb_module, input_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port_id)); + break; + } + case CHANX: + case CHANY: { + input_port_id = find_switch_block_module_chan_port(module_manager, sb_module, + rr_gsb, input_side, input_rr_node, IN_PORT); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + return input_port_id; +} + +/********************************************************************* + * Generate a list of input ports for routing multiplexer inside the switch block + ********************************************************************/ +static +std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const std::vector& input_rr_nodes) { + std::vector input_ports; + + for (auto input_rr_node : input_rr_nodes) { + enum e_side input_pin_side = NUM_SIDES; + switch (input_rr_node->type) { + case OPIN: + input_pin_side = rr_gsb.get_opin_node_grid_side(input_rr_node); + break; + case CHANX: + case CHANY: { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_gsb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); + VTR_ASSERT(NUM_SIDES != input_pin_side); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, input_rr_node)); + } + + return input_ports; +} + + +/********************************************************************* + * Generate a short interconneciton in switch box + * There are two cases should be noticed. + * 1. The actual fan-in of cur_rr_node is 0. In this case, + the cur_rr_node need to be short connected to itself + which is on the opposite side of this switch block + * 2. The actual fan-in of cur_rr_node is 0. In this case, + * The cur_rr_node need to connected to the drive_rr_node + ********************************************************************/ +static +void build_switch_block_module_short_interc(ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + t_rr_node* drive_rr_node, + const std::vector>& grids, + const std::map& input_port_to_module_nets) { + /* Find the name of output port */ + ModulePortId output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); + enum e_side input_pin_side = chan_side; + + /* Generate the input port object */ + switch (drive_rr_node->type) { + case OPIN: + input_pin_side = rr_gsb.get_opin_node_grid_side(drive_rr_node); + break; + case CHANX: + case CHANY: { + /* This should be an input in the data structure of RRGSB */ + if (cur_rr_node == drive_rr_node) { + /* To be strict, the input should locate on the opposite side. + * Use the else part if this may change in some architecture. + */ + Side side_manager(chan_side); + input_pin_side = side_manager.get_opposite(); + } else { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_gsb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); + } + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + /* Find the name of input port */ + ModulePortId input_port_id = find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, drive_rr_node); + + /* The input port and output port must match in size */ + BasicPort input_port = module_manager.module_port(sb_module, input_port_id); + BasicPort output_port = module_manager.module_port(sb_module, output_port_id); + VTR_ASSERT(input_port.get_width() == output_port.get_width()); + + /* Create a module net for this short-wire connection */ + for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) { + ModuleNetId net = input_port_to_module_nets.at(input_port_id); + /* Skip Configuring the net source, it is done before */ + /* Configure the net sink */ + module_manager.add_module_net_sink(sb_module, net, sb_module, 0, output_port_id, output_port.pins()[pin_id]); + } +} + +/********************************************************************* + * Build a instance of a routing multiplexer as well as + * associated memory modules for a connection inside a switch block + ********************************************************************/ +static +void build_switch_block_mux_module(ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const std::vector& drive_rr_nodes, + const size_t& switch_index, + const std::map& input_port_to_module_nets, + std::vector& memory_modules, + std::vector& memory_instances) { + /* Check current rr_node is CHANX or CHANY*/ + VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); + + /* Get the circuit model id of the routing multiplexer */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); + + /* Find the module name of the multiplexer and try to find it in the module manager */ + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + + /* Get the MUX instance id from the module manager */ + size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module); + /* Instanciate the MUX Module */ + module_manager.add_child_module(sb_module, mux_module); + + /* Generate input ports that are wired to the input bus of the routing multiplexer */ + std::vector sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_gsb, grids, drive_rr_nodes); + + /* Link input bus port to Switch Block inputs */ + std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == mux_model_input_ports.size()); + /* Find the module port id of the input port */ + ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); + BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); + + /* Check port size should match */ + VTR_ASSERT(mux_input_port.get_width() == sb_input_port_ids.size()); + for (size_t pin_id = 0; pin_id < sb_input_port_ids.size(); ++pin_id) { + /* Use the exising net */ + ModuleNetId net = input_port_to_module_nets.at(sb_input_port_ids[pin_id]); + /* Configure the net source */ + module_manager.add_module_net_source(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0); + /* Configure the net sink */ + module_manager.add_module_net_sink(sb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]); + } + + /* Link output port to Switch Block outputs */ + std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == mux_model_output_ports.size()); + /* Use the port name convention in the circuit library */ + ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); + BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); + ModulePortId sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); + + /* Check port size should match */ + VTR_ASSERT(1 == mux_output_port.get_width()); + for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(sb_module); + /* Skip Configuring the net source, it is done before */ + /* Configure the net sink */ + module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, 0); + } + + /* Instanciate memory modules */ + /* Find the name and module id of the memory module */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + ModuleId mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + + size_t mem_instance_id = module_manager.num_instance(sb_module, mem_module); + module_manager.add_child_module(sb_module, mem_module); + + /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ + add_module_nets_between_logic_and_memory_sram_bus(module_manager, sb_module, + mux_module, mux_instance_id, + mem_module, mem_instance_id, + circuit_lib, mux_model); + /* Update memory and instance list */ + memory_modules.push_back(mem_module); + memory_instances.push_back(mem_instance_id); +} + +/********************************************************************* + * Generate child modules for a interconnection inside switch block + * The interconnection could be either a wire or a routing multiplexer, + * which depends on the fan-in of the rr_nodes in the switch block + ********************************************************************/ +static +void build_switch_block_interc_modules(ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const e_side& chan_side, + const size_t& chan_node_id, + const std::map& input_port_to_module_nets, + std::vector& memory_modules, + std::vector& memory_instances) { + std::vector drive_rr_nodes; + + /* Get the node */ + t_rr_node* cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id); + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (false == rr_gsb.is_sb_node_passing_wire(chan_side, chan_node_id)) { + for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { + drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); + } + /* Special: if there are zero-driver nodes. We skip here */ + if (0 == drive_rr_nodes.size()) { + return; + } + } + + if (0 == drive_rr_nodes.size()) { + /* Print a special direct connection*/ + build_switch_block_module_short_interc(module_manager, sb_module, + rr_gsb, chan_side, cur_rr_node, + cur_rr_node, grids, + input_port_to_module_nets); + } else if (1 == drive_rr_nodes.size()) { + /* Print a direct connection*/ + build_switch_block_module_short_interc(module_manager, sb_module, + rr_gsb, chan_side, cur_rr_node, + drive_rr_nodes[DEFAULT_SWITCH_ID], + grids, + input_port_to_module_nets); + } else if (1 < drive_rr_nodes.size()) { + /* Print the multiplexer, fan_in >= 2 */ + build_switch_block_mux_module(module_manager, + sb_module, rr_gsb, circuit_lib, + grids, rr_switches, chan_side, cur_rr_node, + drive_rr_nodes, + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + input_port_to_module_nets, + memory_modules, memory_instances); + } /*Nothing should be done else*/ +} + + +/******************************************************************** + * Build a module for a switch block whose detailed description is + * available in a RRGSB object + * A Switch Box module consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * Location of a Switch Box in FPGA fabric: + * + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + * + * Switch Block pin location map + * + * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] + * right_pins inputs/outputs left_pins + * | ^ | + * | | | + * v v v + * +-----------------------------------------------+ + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * bottom_pins---->| |<---- bottom_pins + * | | + * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] + * inputs/outputs<--->| |<---> inputs/outputs + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * top_pins---->| |<---- top_pins + * | | + * +-----------------------------------------------+ + * ^ ^ ^ + * | | | + * | v | + * Grid[x][y] ChanY[x][y] Grid[x+1][y] + * right_pins inputs/outputs left_pins + * + * + ********************************************************************/ +static +void build_switch_block_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const RRGSB& rr_gsb) { + /* Create a Module of Switch Block and add to module manager */ + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + ModuleId sb_module = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); + + /* Create a cache (fast look up) for module nets whose source are input ports */ + std::map input_port_to_module_nets; + + /* Add routing channel ports at each side of the GSB */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); + + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); + std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + + switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + case OUT_PORT: + module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); + break; + case IN_PORT: { + ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Cache the input net */ + ModuleNetId net = module_manager.create_module_net(sb_module); + module_manager.add_module_net_source(sb_module, net, sb_module, 0, input_port_id, 0); + input_port_to_module_nets[input_port_id] = net; + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", + __FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack); + exit(1); + } + } + /* Dump OPINs of adjacent CLBs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + std::string port_name = generate_grid_side_port_name(grids, port_coord, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); + BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + + /* Cache the input net */ + ModuleNetId net = module_manager.create_module_net(sb_module); + module_manager.add_module_net_source(sb_module, net, sb_module, 0, input_port_id, 0); + input_port_to_module_nets[input_port_id] = net; + } + } + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* Add routing multiplexers as child modules */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + /* We care INC_DIRECTION tracks at this side*/ + if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + build_switch_block_interc_modules(module_manager, + sb_module, rr_gsb, + circuit_lib, grids, rr_switches, + side_manager.get_side(), + itrack, + input_port_to_module_nets, + memory_modules, memory_instances); + } + } + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, sb_module); + + /* Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, sb_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, sb_module, module_num_shared_config_bits); + } + + /* Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); + } + + /* Add all the nets to connect configuration ports from memory module to primitive modules + * This is a one-shot addition that covers all the memory modules in this primitive module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, sb_module, + memory_modules, memory_instances, + sram_orgz_type, circuit_lib.design_tech_type(sram_model)); + } +} + +/********************************************************************* + * Generate an input port for routing multiplexer inside the connection block + * which is the middle output of a routing track + ********************************************************************/ +static +ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + t_rr_node* chan_rr_node) { + ModulePortId input_port_id; + /* Generate the input port object */ + switch (chan_rr_node->type) { + case CHANX: + case CHANY: { + /* Create port description for the routing track middle output */ + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); + /* Create a port description for the middle output */ + std::string input_port_name = generate_routing_track_port_name(cb_type, + port_coord, chan_node_track_id, + IN_PORT); + /* Must find a valid port id in the Switch Block module */ + input_port_id = module_manager.find_module_port(cb_module, input_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id)); + break; + } + default: /* OPIN, SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + return input_port_id; +} + +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ +static +ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + t_rr_node* src_rr_node) { + + /* Ensure the src_rr_node is an input pin of a CLB */ + VTR_ASSERT(IPIN == src_rr_node->type); + /* Create port description for input pin of a CLB */ + vtr::Point port_coord(src_rr_node->xlow, src_rr_node->ylow); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + enum e_side cb_ipin_side = NUM_SIDES; + int cb_ipin_index = -1; + rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); + /* We need to be sure that drive_rr_node is part of the CB */ + VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); + std::string port_name = generate_grid_side_port_name(grids, + port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, cb_ipin_index), + rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); + + /* Must find a valid port id in the Switch Block module */ + ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, ipin_port_id)); + return ipin_port_id; +} + +/********************************************************************* + * Generate a list of routing track middle output ports + * for routing multiplexer inside the connection block + ********************************************************************/ +static +std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector& input_rr_nodes) { + std::vector input_ports; + + for (auto input_rr_node : input_rr_nodes) { + input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, input_rr_node)); + } + + return input_ports; +} + +/********************************************************************* + * Print a short interconneciton in connection + ********************************************************************/ +static +void build_connection_block_module_short_interc(ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector>& grids, + t_rr_node* src_rr_node, + const std::map& input_port_to_module_nets) { + /* Ensure we have only one 1 driver node */ + VTR_ASSERT_SAFE(1 == src_rr_node->fan_in); + + /* Find the driver node */ + t_rr_node* drive_rr_node = src_rr_node->drive_rr_nodes[0]; + + /* We have OPINs since we may have direct connections: + * These connections should be handled by other functions in the compact_netlist.c + * So we just return here for OPINs + */ + if (OPIN == drive_rr_node->type) { + return; + } + + VTR_ASSERT((CHANX == drive_rr_node->type) || (CHANY == drive_rr_node->type)); + + /* Create port description for the routing track middle output */ + ModulePortId input_port_id = find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, drive_rr_node); + + /* Create port description for input pin of a CLB */ + ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, src_rr_node); + + /* The input port and output port must match in size */ + BasicPort input_port = module_manager.module_port(cb_module, input_port_id); + BasicPort ipin_port = module_manager.module_port(cb_module, ipin_port_id); + VTR_ASSERT(input_port.get_width() == ipin_port.get_width()); + + /* Create a module net for this short-wire connection */ + for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) { + ModuleNetId net = input_port_to_module_nets.at(input_port_id); + /* Skip Configuring the net source, it is done before */ + /* Configure the net sink */ + module_manager.add_module_net_sink(cb_module, net, cb_module, 0, ipin_port_id, ipin_port.pins()[pin_id]); + } +} + +/********************************************************************* + * Build a instance of a routing multiplexer as well as + * associated memory modules for a connection inside a connection block + ********************************************************************/ +static +void build_connection_block_mux_module(ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* cur_rr_node, + const std::map& input_port_to_module_nets, + std::vector& memory_modules, + std::vector& memory_instances) { + /* Check current rr_node is an input pin of a CLB */ + VTR_ASSERT(IPIN == cur_rr_node->type); + + /* Build a vector of driver rr_nodes */ + std::vector drive_rr_nodes; + for (int inode = 0; inode < cur_rr_node->num_drive_rr_nodes; inode++) { + drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[inode]); + } + + int switch_index = cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]; + + /* Get the circuit model id of the routing multiplexer */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); + + /* Find the module name of the multiplexer and try to find it in the module manager */ + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + + /* Get the MUX instance id from the module manager */ + size_t mux_instance_id = module_manager.num_instance(cb_module, mux_module); + module_manager.add_child_module(cb_module, mux_module); + + /* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */ + std::vector cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_gsb, cb_type, drive_rr_nodes); + + /* Link input bus port to Switch Block inputs */ + std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == mux_model_input_ports.size()); + /* Find the module port id of the input port */ + ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); + BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); + + /* Check port size should match */ + VTR_ASSERT(mux_input_port.get_width() == cb_input_port_ids.size()); + for (size_t pin_id = 0; pin_id < cb_input_port_ids.size(); ++pin_id) { + /* Use the exising net */ + ModuleNetId net = input_port_to_module_nets.at(cb_input_port_ids[pin_id]); + /* Configure the net source */ + module_manager.add_module_net_source(cb_module, net, cb_module, 0, cb_input_port_ids[pin_id], 0); + /* Configure the net sink */ + module_manager.add_module_net_sink(cb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]); + } + + /* Link output port to Switch Block outputs */ + std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); + VTR_ASSERT(1 == mux_model_output_ports.size()); + /* Use the port name convention in the circuit library */ + ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_output_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); + BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); + ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, cur_rr_node); + + /* Check port size should match */ + VTR_ASSERT(1 == mux_output_port.get_width()); + for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(cb_module); + /* Skip Configuring the net source, it is done before */ + /* Configure the net sink */ + module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, 0); + } + + /* Instanciate memory modules */ + /* Find the name and module id of the memory module */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + ModuleId mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + + size_t mem_instance_id = module_manager.num_instance(cb_module, mem_module); + module_manager.add_child_module(cb_module, mem_module); + + /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ + add_module_nets_between_logic_and_memory_sram_bus(module_manager, cb_module, + mux_module, mux_instance_id, + mem_module, mem_instance_id, + circuit_lib, mux_model); + /* Update memory and instance list */ + memory_modules.push_back(mem_module); + memory_instances.push_back(mem_instance_id); +} + +/******************************************************************** + * Print internal connections of a connection block + * For a IPIN node that is driven by only 1 fan-in, + * a short wire will be created + * For a IPIN node that is driven by more than two fan-ins, + * a routing multiplexer will be instanciated + ********************************************************************/ +static +void build_connection_block_interc_modules(ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* src_rr_node, + const std::map& input_port_to_module_nets, + std::vector& memory_modules, + std::vector& memory_instances) { + if (1 > src_rr_node->fan_in) { + return; /* This port has no driver, skip it */ + } else if (1 == src_rr_node->fan_in) { + /* Print a direct connection */ + build_connection_block_module_short_interc(module_manager, cb_module, rr_gsb, cb_type, grids, src_rr_node, input_port_to_module_nets); + + } else if (1 < src_rr_node->fan_in) { + /* Print the multiplexer, fan_in >= 2 */ + build_connection_block_mux_module(module_manager, + cb_module, rr_gsb, cb_type, + circuit_lib, grids, rr_switches, + src_rr_node, + input_port_to_module_nets, + memory_modules, memory_instances); + } /*Nothing should be done else*/ +} + +/******************************************************************** + * Generate a module of a connection Box (Type: [CHANX|CHANY]) + * Actually it is very similiar to switch box but + * the difference is connection boxes connect Grid INPUT Pins to channels + * NOTE: direct connection between CLBs should NOT be included inside this + * module! They should be added in the top-level module as their connection + * is not limited to adjacent CLBs!!! + * + * Location of a X- and Y-direction Connection Block in FPGA fabric + * +------------+ +-------------+ + * | |------>| | + * | CLB |<------| Y-direction | + * | | ... | Connection | + * | |------>| Block | + * +------------+ +-------------+ + * | ^ ... | | ^ ... | + * v | v v | v + * +-------------------+ +-------------+ + * --->| |--->| | + * <---| X-direction |<---| Switch | + * ...| Connection block |... | Block | + * --->| |--->| | + * +-------------------+ +-------------+ + * + * Internal structure: + * This is an example of a X-direction connection block + * Note that middle output ports are shorted wire from inputs of routing tracks, + * which are also the inputs of routing multiplexer of the connection block + * + * CLB Input Pins + * (IPINs) + * ^ ^ ^ + * | | ... | + * +--------------------------+ + * | ^ ^ ^ | + * | | | ... | | + * | +--------------------+ | + * | | routing | | + * | | multiplexers | | + * | +--------------------+ | + * | middle outputs | + * | of routing channel | + * | ^ ^ ^ ^ ^ ^ ^ ^ | + * | | | | | ... | | | | | + * in[0] -->|------------------------->|---> out[0] + * out[1] <--|<-------------------------|<--- in[1] + * | ... | + * in[W-2] -->|------------------------->|---> out[W-2] + * out[W-1] <--|<-------------------------|<--- in[W-1] + * +--------------------------+ + * + * W: routing channel width + * + ********************************************************************/ +static +void build_connection_block_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const RRGSB& rr_gsb, + const t_rr_type& cb_type) { + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId cb_module = module_manager.add_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); + + /* Add the input and output ports of routing tracks in the channel + * Routing tracks pass through the connection blocks + */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + IN_PORT); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + } + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + OUT_PORT); + BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ + module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); + } + + /* Add the input pins of grids, which are output ports of the connection block */ + std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); + std::string port_name = generate_grid_side_port_name(grids, + port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), + ipin_node->ptc_num); + BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); + } + } + + /* Create a cache (fast look up) for module nets whose source are input ports */ + std::map input_port_to_module_nets; + + /* TODO: Generate short-wire connection for each routing track : + * Each input port is short-wired to its output port and middle output port + * + * in[i] ----------> out[i] + * | + * +-----> mid_out[i] + */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + /* Create a port description for the input */ + std::string input_port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + IN_PORT); + ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name); + BasicPort input_port = module_manager.module_port(cb_module, input_port_id); + + /* Create a port description for the output */ + std::string output_port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + OUT_PORT); + ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name); + BasicPort output_port = module_manager.module_port(cb_module, output_port_id); + + /* Ensure port size matching */ + VTR_ASSERT(1 == input_port.get_width()); + VTR_ASSERT(input_port.get_width() == output_port.get_width()); + + /* Create short-wires: input port ---> output port + * Do short-wires: input port ---> middle output port + */ + for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(cb_module); + module_manager.add_module_net_source(cb_module, net, cb_module, 0, input_port_id, input_port.pins()[pin_id]); + module_manager.add_module_net_sink(cb_module, net, cb_module, 0, output_port_id, output_port.pins()[pin_id]); + /* Cache the module net */ + input_port_to_module_nets[input_port_id] = net; + } + } + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* TODO: Add sub modules of routing multiplexers or direct interconnect*/ + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + build_connection_block_interc_modules(module_manager, + cb_module, rr_gsb, cb_type, + circuit_lib, grids, rr_switches, + rr_gsb.get_ipin_node(cb_ipin_side, inode), + input_port_to_module_nets, + memory_modules, memory_instances); + } + } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, cb_module); + + /* Count shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, cb_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, cb_module, module_num_shared_config_bits); + } + + /* Count SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); + } + + /* Add all the nets to connect configuration ports from memory module to primitive modules + * This is a one-shot addition that covers all the memory modules in this primitive module! + */ + if (false == memory_modules.empty()) { + add_module_nets_memory_config_bus(module_manager, cb_module, + memory_modules, memory_instances, + sram_orgz_type, circuit_lib.design_tech_type(sram_model)); + } +} + + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and build a module for each of them + *******************************************************************/ +static +void build_flatten_connection_block_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const CircuitLibrary& circuit_lib, + const std::vector>& grids, + const std::vector& rr_switches, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const t_rr_type& cb_type) { + /* Build unique X-direction connection block modules */ + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + if ( (TRUE != is_cb_exist(CHANX, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + build_connection_block_module(module_manager, + circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + rr_gsb, cb_type); + } + } +} + +/******************************************************************** + * A top-level function of this file + * Build all the modules for global routing architecture of a FPGA fabric + * in a flatten way: + * Each connection block and switch block will be generated as a unique module + * Covering: + * 1. Connection blocks + * 2. Switch blocks + *******************************************************************/ +void build_flatten_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const std::vector>& grids, + const t_det_routing_arch& routing_arch, + const std::vector& rr_switches) { + /* We only support uni-directional routing architecture now */ + VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); + + /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + + /* Build unique switch block modules */ + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + build_switch_block_module(module_manager, circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + rr_gsb); + } + } + + build_flatten_connection_block_modules(module_manager, L_device_rr_gsb, + circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + CHANX); + + build_flatten_connection_block_modules(module_manager, L_device_rr_gsb, + circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + CHANY); + +} + +/******************************************************************** + * A top-level function of this file + * Build all the unique modules for global routing architecture of a FPGA fabric + * This function will use unique module list built in device_rr_gsb, + * to build only unique modules (in terms of graph connections) of + * 1. Connection blocks + * 2. Switch blocks + * + * Note: this function SHOULD be called only when + * the option compact_routing_hierarchy is turned on!!! + *******************************************************************/ +void build_unique_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const std::vector>& grids, + const t_det_routing_arch& routing_arch, + const std::vector& rr_switches) { + /* We only support uni-directional routing architecture now */ + VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); + + /* Build unique switch block modules */ + for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb); + build_switch_block_module(module_manager, circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + unique_mirror); + } + + /* Build unique X-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); + + build_connection_block_module(module_manager, + circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + unique_mirror, CHANX); + } + + /* Build unique X-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); + + build_connection_block_module(module_manager, + circuit_lib, + grids, rr_switches, + sram_orgz_type, sram_model, + unique_mirror, CHANY); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h new file mode 100644 index 000000000..8f00aad2b --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h @@ -0,0 +1,33 @@ +/******************************************************************** + * Header file for build_routing_modules.cpp + *******************************************************************/ +#ifndef BUILD_ROUTING_MODULES_H +#define BUILD_ROUTING_MODULES_H + +#include "spice_types.h" +#include "vpr_types.h" +#include "rr_blocks.h" +#include "mux_library.h" +#include "circuit_library.h" +#include "module_manager.h" + +void build_flatten_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const std::vector>& grids, + const t_det_routing_arch& routing_arch, + const std::vector& rr_switches); + +void build_unique_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const std::vector>& grids, + const t_det_routing_arch& routing_arch, + const std::vector& rr_switches); + + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index fae787353..c4f2805a5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -13,6 +13,7 @@ #include /* Include vpr structs*/ +#include "vtr_assert.h" #include "vtr_geometry.h" #include "util.h" #include "physical_types.h" @@ -280,11 +281,25 @@ void vpr_fpga_verilog(ModuleManager& module_manager, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); /* Dump routing resources: switch blocks, connection blocks and channel tracks */ - print_verilog_routing_resources(module_manager, mux_lib, sram_verilog_orgz_info, + print_verilog_routing_resources(module_manager, sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, vpr_setup.FPGA_SPICE_Opts); + if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { + print_verilog_unique_routing_modules(module_manager, device_rr_gsb, + vpr_setup.RoutingArch, + std::string(src_dir_path), std::string(rr_dir_path), + TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + } else { + VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); + print_verilog_flatten_routing_modules(module_manager, device_rr_gsb, + vpr_setup.RoutingArch, + std::string(src_dir_path), std::string(rr_dir_path), + TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + } + + /* Dump logic blocks * Branches to go: * 1. a compact output diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 13dc670f0..d7943f805 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -49,100 +49,9 @@ #include "verilog_global.h" #include "verilog_utils.h" #include "verilog_writer_utils.h" +#include "verilog_module_writer.h" #include "verilog_routing.h" -/******************************************************************** - * Print local wires that are used for SRAM configuration - * This function is supposed to be used by Verilog generation - * of connection blocks - * It will count the number of connection blocks, which is the - * port width for local wires when Configuration chain is used - ********************************************************************/ -static -void print_verilog_connection_block_local_sram_wires(std::fstream& fp, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type, - const size_t& port_size) { - size_t local_port_size = port_size; - if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { - /* Plus 1 for the wire size to connect to the tail of the configuration chain */ - local_port_size = find_connection_block_number_of_muxes(rr_gsb, cb_type) + 1; - } - print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); -} - - -/******************************************************************** - * Print local wires that are used for SRAM configuration - * This function is supposed to be used by Verilog generation - * of switch blocks - * It will count the number of switch blocks, which is the - * port width for local wires when Configuration chain is used - ********************************************************************/ -static -void print_verilog_switch_block_local_sram_wires(std::fstream& fp, - const RRGSB& rr_gsb, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type, - const size_t& port_size) { - size_t local_port_size = port_size; - if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { - /* Plus 1 for the wire size to connect to the tail of the configuration chain */ - local_port_size = find_switch_block_number_of_muxes(rr_gsb) + 1; - } - print_verilog_local_sram_wires(fp, circuit_lib, sram_model, sram_orgz_type, local_port_size); -} - -/******************************************************************** - * Check if the MSB of a configuration bus of a connection block - * matches the expected value - * Exception: - * 1. Configuration bus for configuration chain will follow - * the number of multiplexers in the connection block - ********************************************************************/ -static -bool check_connection_block_mem_config_bus(const e_sram_orgz& sram_orgz_type, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const BasicPort& config_bus, - const size_t& expected_msb) { - size_t local_expected_msb = expected_msb; - if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { - /* Note the size of local wires is number of routing multiplexers + 1 - * Wire MSB is the number of routing multiplexers in the configuration chain - */ - local_expected_msb = find_connection_block_number_of_muxes(rr_gsb, cb_type); - } - return check_mem_config_bus(sram_orgz_type, config_bus, local_expected_msb); -} - - -/******************************************************************** - * Check if the MSB of a configuration bus of a switch block - * matches the expected value - * Exception: - * 1. Configuration bus for configuration chain will follow - * the number of multiplexers in the switch block - ********************************************************************/ -static -bool check_switch_block_mem_config_bus(const e_sram_orgz& sram_orgz_type, - const RRGSB& rr_gsb, - const BasicPort& config_bus, - const size_t& expected_msb) { - size_t local_expected_msb = expected_msb; - if (SPICE_SRAM_SCAN_CHAIN == sram_orgz_type) { - /* Note the size of local wires is number of routing multiplexers + 1 - * Wire MSB is the number of routing multiplexers in the configuration chain - */ - local_expected_msb = find_switch_block_number_of_muxes(rr_gsb); - } - return check_mem_config_bus(sram_orgz_type, config_bus, local_expected_msb); -} - /********************************************************************* * Generate the Verilog module for a routing channel * Routing track wire, which is 1-input and dual output @@ -340,216 +249,6 @@ void print_verilog_routing_unique_chan_subckt(ModuleManager& module_manager, return; } -/********************************************************************* - * Generate the Verilog module for a routing channel - * Routing track wire, which is 1-input and dual output - * This type of wires are used in the global routing architecture. - * One of the output is wired to another Switch block multiplexer, - * while the mid-output is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * - * IMPORTANT: This function is designed for outputting non-unique Verilog modules - * of routing channels - * - * TODO: This function should be adapted to the RRGraph object - *********************************************************************/ -static -void print_verilog_routing_chan_subckt(ModuleManager& module_manager, - const std::string& verilog_dir, - const std::string& subckt_dir, - const vtr::Point& chan_coordinate, - const t_rr_type& chan_type, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int chan_width = 0; - t_rr_node** chan_rr_nodes = NULL; - - std::string fname_prefix; - - /* TODO: use a constexpr String arrary to replace this switch cases? */ - /* Find the prefix for the Verilog file name */ - switch (chan_type) { - case CHANX: - fname_prefix = std::string(chanx_verilog_file_name_prefix); - break; - case CHANY: - fname_prefix = std::string(chany_verilog_file_name_prefix); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", - __FILE__, __LINE__); - exit(1); - } - - std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(fname_prefix, chan_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, "Verilog modules for routing channel in X- and Y-direction"); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(generate_routing_channel_module_name(chan_type, chan_coordinate)); - - /* Collect rr_nodes for Tracks for chanx[ix][iy] */ - chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, chan_coordinate.x(), chan_coordinate.y(), - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Add ports to the module */ - /* For the LEFT side of a X-direction routing channel - * or the BOTTOM bottom side of a Y-direction routing channel - * Routing Resource Nodes in INC_DIRECTION are inputs of the module - * - * For the RIGHT side of a X-direction routing channel - * or the TOP bottom side of a Y-direction routing channel - * Routing Resource Nodes in INC_DIRECTION are outputs of the module - * - * An example of X-direction routing channel consisting of W routing nodes: - * +--------------------------+ - * nodeA(INC_DIRECTION)--->| in[0] out[0] |---> nodeA(INC_DIRECTION) - * nodeB(DEC_DIRECTION)<---| out[1] in[1] |<--- nodeB(DEC_DIRECTION) - * ... ... ... ... - * nodeX(INC_DIRECTION)--->| in[W-1] out[W-1] |---> nodeX(INC_DIRECTION) - * +--------------------------+ - * - * An example of Y-direction routing channel consisting of W routing nodes: - * - * nodeA nodeB nodeX - * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) - * ^ | ... | - * | v v - * +------------------------------ ... -------+ - * | out[0] in[1] in[X] | - * | | - * | | - * | in[0] out[1] ... out[X] | - * +------------------------------ ... -------+ - * ^ | | - * | v v - * nodeA nodeB nodeX - * (INC_DIRECTION) (DEC_DIRECTION) (DEC_DIRECTION) - */ - /* Add ports at LEFT/BOTTOM side of the module */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - break; - } - case DEC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - } - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(chan_type), - chan_coordinate.x(), chan_coordinate.y(), itrack); - exit(1); - } - } - /* Add ports at RIGHT/TOP side of the module */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - } - case DEC_DIRECTION: { - /* TODO: naming should be more flexible !!! */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - break; - } - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of rr_node %s[%lu][%lu]_in/out[%lu]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(chan_type), - chan_coordinate.x(), chan_coordinate.y(), itrack); - exit(1); - } - } - /* Add middle-point output for connection box inputs */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - /* TODO: naming should be more flexible !!! */ - BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); - module_manager.add_port(module_id, mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Print short-wire connection: - * - * in[i] ----------> out[i] - * | - * +-----> mid_out[i] - */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - /* short connecting inputs and outputs: - * length of metal wire and parasitics are handled by semi-custom flow - */ - BasicPort input_port(std::string("in" + std::to_string(itrack)), 1); - BasicPort output_port(std::string("out" + std::to_string(itrack)), 1); - BasicPort mid_output_port(std::string("mid_out" + std::to_string(itrack)), 1); - print_verilog_wire_connection(fp, output_port, input_port, false); - print_verilog_wire_connection(fp, mid_output_port, input_port, false); - } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the linked list */ - /* Uncomment this when it is ready - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ - - /* Free */ - my_free(chan_rr_nodes); - - return; -} - - static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, @@ -2227,724 +1926,7 @@ void update_routing_connection_box_conf_bits(t_sram_orgz_info* cur_sram_orgz_inf return; } - -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ -static -BasicPort generate_verilog_connection_box_ipin_port(const RRGSB& rr_gsb, - t_rr_node* src_rr_node) { - - /* Ensure the src_rr_node is an input pin of a CLB */ - VTR_ASSERT(IPIN == src_rr_node->type); - /* Create port description for input pin of a CLB */ - vtr::Point port_coord(src_rr_node->xlow, src_rr_node->ylow); - /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - enum e_side cb_ipin_side = NUM_SIDES; - int cb_ipin_index = -1; - rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); - /* We need to be sure that drive_rr_node is part of the CB */ - VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); - std::string port_name = generate_grid_side_port_name(port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, cb_ipin_index), - rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); - return BasicPort(port_name, 1); /* Every grid output has a port size of 1 */ -} - -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ -static -BasicPort generate_verilog_unique_switch_box_chan_port(const RRGSB& rr_sb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const PORTS& cur_rr_node_direction) { - /* Get the index in sb_info of cur_rr_node */ - int index = rr_sb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); - /* Make sure this node is included in this sb_info */ - VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); - - DeviceCoordinator chan_rr_node_coordinator = rr_sb.get_side_block_coordinator(chan_side); - - vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); - std::string chan_port_name = generate_routing_track_port_name(rr_sb.get_chan_node(chan_side, index)->type, - chan_port_coord, index, - rr_sb.get_chan_node_direction(chan_side, index)); - return BasicPort(chan_port_name, 1); /* Every track has a port size of 1 */ -} - -/********************************************************************* - * Generate an input port for routing multiplexer inside the connection block - * which is the middle output of a routing track - ********************************************************************/ -static -BasicPort generate_connection_block_chan_port(const RRGSB& rr_gsb, - const t_rr_type& cb_type, - t_rr_node* chan_rr_node) { - BasicPort input_port; - /* Generate the input port object */ - switch (chan_rr_node->type) { - case CHANX: - case CHANY: { - /* Create port description for the routing track middle output */ - vtr::Point middle_output_port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); - /* Create a port description for the middle output */ - std::string middle_output_port_name = generate_routing_track_middle_output_port_name(cb_type, middle_output_port_coord, chan_node_track_id); - input_port.set_name(middle_output_port_name); - input_port.set_width(1); - break; - } - default: /* OPIN, SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - return input_port; -} - - -/********************************************************************* - * Generate an input port for routing multiplexer inside the switch block - * In addition to give the Routing Resource node of the input - * Users should provide the side of input, which is different case by case: - * 1. When the input is a pin of a CLB/Logic Block, the input_side should - * be the side of the node on its grid! - * For example, the input pin is on the top side of a switch block - * but on the right side of a switch block - * +--------+ - * | | - * | Grid |---+ - * | | | - * +--------+ v input_pin - * +----------------+ - * | Switch Block | - * +----------------+ - * 2. When the input is a routing track, the input_side should be - * the side of the node locating on the switch block - ********************************************************************/ -static -BasicPort generate_switch_block_input_port(const RRGSB& rr_sb, - const e_side& input_side, - t_rr_node* input_rr_node) { - BasicPort input_port; - /* Generate the input port object */ - switch (input_rr_node->type) { - /* case SOURCE: */ - case OPIN: { - /* Find the coordinator (grid_x and grid_y) for the input port */ - vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); - std::string input_port_name = generate_grid_side_port_name(input_port_coord, - input_side, - input_rr_node->ptc_num); - input_port.set_name(input_port_name); - input_port.set_width(1); /* Every grid output has a port size of 1 */ - break; - } - case CHANX: - case CHANY: { - input_port = generate_verilog_unique_switch_box_chan_port(rr_sb, input_side, input_rr_node, IN_PORT); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - return input_port; -} - -/********************************************************************* - * Generate a list of routing track middle output ports - * for routing multiplexer inside the connection block - ********************************************************************/ -static -std::vector generate_connection_block_mux_input_ports(const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector& input_rr_nodes) { - std::vector input_ports; - - for (auto input_rr_node : input_rr_nodes) { - input_ports.push_back(generate_connection_block_chan_port(rr_gsb, cb_type, input_rr_node)); - } - - return input_ports; -} - - -/********************************************************************* - * Generate a list of input ports for routing multiplexer inside the switch block - ********************************************************************/ -static -std::vector generate_switch_block_input_ports(const RRGSB& rr_sb, - const std::vector& input_rr_nodes) { - std::vector input_ports; - - for (auto input_rr_node : input_rr_nodes) { - enum e_side input_pin_side = NUM_SIDES; - switch (input_rr_node->type) { - case OPIN: - input_pin_side = rr_sb.get_opin_node_grid_side(input_rr_node); - break; - case CHANX: - case CHANY: { - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_sb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); - VTR_ASSERT(NUM_SIDES != input_pin_side); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - input_ports.push_back(generate_switch_block_input_port(rr_sb, input_pin_side, input_rr_node)); - } - - return input_ports; -} - -/********************************************************************* - * Print a short interconneciton in switch box - * There are two cases should be noticed. - * 1. The actual fan-in of cur_rr_node is 0. In this case, - the cur_rr_node need to be short connected to itself which is on the opposite side of this switch - * 2. The actual fan-in of cur_rr_node is 0. In this case, - * The cur_rr_node need to connected to the drive_rr_node - ********************************************************************/ -static -void print_verilog_unique_switch_box_short_interc(std::fstream& fp, - const RRGSB& rr_sb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - t_rr_node* drive_rr_node) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Find the name of output port */ - BasicPort output_port = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); - enum e_side input_pin_side = chan_side; - - /* Generate the input port object */ - switch (drive_rr_node->type) { - case OPIN: - input_pin_side = rr_sb.get_opin_node_grid_side(drive_rr_node); - break; - case CHANX: - case CHANY: { - /* This should be an input in the data structure of RRGSB */ - if (cur_rr_node == drive_rr_node) { - /* To be strict, the input should locate on the opposite side. - * Use the else part if this may change in some architecture. - */ - Side side_manager(chan_side); - input_pin_side = side_manager.get_opposite(); - } else { - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_sb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); - } - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - /* Find the name of input port */ - BasicPort input_port = generate_switch_block_input_port(rr_sb, input_pin_side, drive_rr_node); - - /* Print the wire connection in Verilog format */ - print_verilog_comment(fp, std::string("----- Short connection " + output_port.get_name() + " -----")); - print_verilog_wire_connection(fp, output_port, input_port, false); - fp << std::endl; -} - -/********************************************************************* - * Print a Verilog instance of a routing multiplexer as well as - * associated memory modules for a connection inside a switch block - ********************************************************************/ -static -void print_verilog_unique_switch_box_mux(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info, - BasicPort& config_bus, - BasicPort& fm_config_bus, - const ModuleId& sb_module, - const RRGSB& rr_sb, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const std::vector& drive_rr_nodes, - const size_t& switch_index, - const bool& use_explicit_mapping) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Check */ - /* Check current rr_node is CHANX or CHANY*/ - VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Get the circuit model id of the routing multiplexer */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - - /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); - - /* Get the MUX instance id from the module manager */ - size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module); - - /* Print the input bus for the inputs of a multiplexer - * We use the datapath input size (mux_size) to name the bus - * just to following the naming convention when the tool is built - * The bus port size should be the input size of multiplexer implementation - */ - BasicPort inbus_port; - inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); - inbus_port.set_width(datapath_mux_size); - - /* Generate input ports that are wired to the input bus of the routing multiplexer */ - std::vector mux_input_ports = generate_switch_block_input_ports(rr_sb, drive_rr_nodes); - /* Connect input ports to bus */ - print_verilog_comment(fp, std::string("----- BEGIN A local bus wire for multiplexer inputs -----")); - fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; - print_verilog_comment(fp, std::string("----- END A local bus wire for multiplexer inputs -----")); - fp << std::endl; - - /* Find the number of reserved configuration bits for the routing multiplexer */ - size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); - - /* Find the number of configuration bits for the routing multiplexer */ - size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - - /* Print the configuration bus for the routing multiplexers */ - print_verilog_comment(fp, std::string("----- BEGIN Local wires to group configuration ports -----")); - print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, - datapath_mux_size, mux_instance_id, - mux_num_reserved_config_bits, mux_num_config_bits); - print_verilog_comment(fp, std::string("----- END Local wires to group configuration ports -----")); - fp << std::endl; - - /* Dump ports visible only during formal verification */ - print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); - print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); - /* Print the SRAM configuration ports for formal verification */ - /* Update config bus for formal verification, - * shift with number of configuration bit of the MUX - */ - fm_config_bus.set_width(fm_config_bus.get_msb() + 1, fm_config_bus.get_msb() + mux_num_config_bits); - - /* Align with the port width of formal verification port of SB module */ - print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, - datapath_mux_size, mux_instance_id, - mux_num_config_bits, fm_config_bus); - print_verilog_endif(fp); - print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); - fp << std::endl; - - /* Instanciate the MUX Module */ - /* Create port-to-port map */ - std::map mux_port2port_name_map; - - /* Link input bus port to Switch Block inputs */ - std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == mux_model_input_ports.size()); - /* Use the port name convention in the circuit library */ - mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_input_ports[0])] = inbus_port; - - /* Link output port to Switch Block outputs */ - std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == mux_model_output_ports.size()); - /* Use the port name convention in the circuit library */ - mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_output_ports[0])] = generate_verilog_unique_switch_box_chan_port(rr_sb, chan_side, cur_rr_node, OUT_PORT); - - /* Link SRAM port to different configuraton port for the routing multiplexer - * Different design technology requires different configuration bus! - */ - std::vector mux_model_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); - VTR_ASSERT( 1 == mux_model_sram_ports.size() ); - /* For the regular SRAM port, module port use the same name */ - std::string mux_module_sram_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]); - BasicPort mux_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), - mux_num_config_bits); - mux_port2port_name_map[mux_module_sram_port_name] = mux_config_port; - - /* For the inverted SRAM port */ - std::string mux_module_sram_inv_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]) + std::string("_inv"); - BasicPort mux_config_inv_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), - mux_num_config_bits); - mux_port2port_name_map[mux_module_sram_inv_port_name] = mux_config_inv_port; - - /* Print an instance of the MUX Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a routing multiplexer -----")); - print_verilog_module_instance(fp, module_manager, sb_module, mux_module, mux_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of a routing multiplexer -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(sb_module, mux_module); - - /* Instanciate memory modules */ - /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); - ModuleId mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - - /* Create port-to-port map */ - std::map mem_port2port_name_map; - - /* TODO: Make the port2port map generation more generic!!! */ - /* Link the SRAM ports of the routing multiplexer to the memory module */ - std::vector mem_output_ports; - mem_output_ports.push_back(mux_config_port); - mem_output_ports.push_back(mux_config_inv_port); - mem_port2port_name_map = generate_mem_module_port2port_map(config_bus, - mem_output_ports, - circuit_lib.design_tech_type(mux_model), - cur_sram_orgz_info->type); - /* Update the config bus for the module */ - update_mem_module_config_bus(cur_sram_orgz_info->type, - circuit_lib.design_tech_type(mux_model), - mux_num_config_bits, - config_bus); - - /* Print an instance of the memory module associated with the routing multiplexer */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); - print_verilog_module_instance(fp, module_manager, sb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(sb_module, mem_module); - - /* Create the path of the input of multiplexer in the hierarchy - * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! - */ - std::string mux_input_hie_path = std::string(rr_sb.gen_sb_verilog_instance_name()) + std::string("/") - + mux_module_name + std::string("_") - + std::to_string(mux_instance_id) + std::string("_/in"); - cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); -} - - -/********************************************************************* - * Print the Verilog modules for a interconnection inside switch block - * The interconnection could be either a wire or a routing multiplexer, - * which depends on the fan-in of the rr_nodes in the switch block - ********************************************************************/ -static -void print_verilog_unique_switch_box_interc(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info, - BasicPort& config_bus, - BasicPort& fm_config_bus, - const ModuleId& sb_module, - const RRGSB& rr_sb, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const e_side& chan_side, - const size_t& chan_node_id, - const bool& use_explicit_mapping) { - std::vector drive_rr_nodes; - - /* Get the node */ - t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id); - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - if (false == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { - for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { - drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); - } - /* Special: if there are zero-driver nodes. We skip here */ - if (0 == drive_rr_nodes.size()) { - return; - } - } - - if (0 == drive_rr_nodes.size()) { - /* Print a special direct connection*/ - print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - cur_rr_node); - } else if (1 == drive_rr_nodes.size()) { - /* Print a direct connection*/ - print_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - drive_rr_nodes[DEFAULT_SWITCH_ID]); - } else if (1 < drive_rr_nodes.size()) { - /* Print the multiplexer, fan_in >= 2 */ - print_verilog_unique_switch_box_mux(module_manager, fp, cur_sram_orgz_info, - config_bus, fm_config_bus, - sb_module, rr_sb, circuit_lib, mux_lib, - rr_switches, chan_side, cur_rr_node, - drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], - use_explicit_mapping); - } /*Nothing should be done else*/ -} - -/********************************************************************* - * Generate the Verilog module for a Switch Box. - * A Switch Box module consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * Location of a Switch Box in FPGA fabric: - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * - * Switch Block pin location map - * - * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] - * right_pins inputs/outputs left_pins - * | ^ | - * | | | - * v v v - * +-----------------------------------------------+ - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * bottom_pins---->| |<---- bottom_pins - * | | - * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] - * inputs/outputs<--->| |<---> inputs/outputs - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * top_pins---->| |<---- top_pins - * | | - * +-----------------------------------------------+ - * ^ ^ ^ - * | | | - * | v | - * Grid[x][y] ChanY[x][y] Grid[x+1][y] - * right_pins inputs/outputs left_pins - * - * - ********************************************************************/ -static -void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& subckt_dir, - const RRGSB& rr_sb, - const bool& is_explicit_mapping) { - /* TODO: move this part to another function where we count the conf bits for all the switch blocks !!!*/ - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = find_switch_block_num_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_sb); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = find_switch_block_num_shared_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_sb); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - RRGSB rr_gsb = rr_sb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - rr_gsb.set_sb_num_reserved_conf_bits(size_t(num_reserved_conf_bits)); - rr_gsb.set_sb_conf_bits_lsb(size_t(cur_num_sram)); - rr_gsb.set_sb_conf_bits_msb(size_t(cur_num_sram + num_conf_bits - 1)); - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); - - /* Add ports to the module */ - /* Global ports: - * In the circuit_library, find all the circuit models that may be included in the Switch Block - * Collect the global ports from the circuit_models and merge with the same name - */ - std::vector global_ports = find_switch_block_global_ports(rr_gsb, circuit_lib, rr_switches); - for (const auto& port : global_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add routing channel ports at each side of the GSB */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); - std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - - switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - case IN_PORT: - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack); - exit(1); - } - } - /* Dump OPINs of adjacent CLBs */ - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string port_name = generate_grid_side_port_name(port_coord, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); - BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ - /* Grid outputs are inputs of switch blocks */ - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); - } - } - - /* Add configuration ports */ - /* Reserved sram ports */ - if (0 < rr_gsb.get_sb_num_reserved_conf_bits()) { - /* Check: this SRAM organization type must be memory-bank ! */ - VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); - /* Generate a list of ports */ - add_reserved_sram_ports_to_module_manager(module_manager, module_id, - rr_gsb.get_sb_num_reserved_conf_bits()); - } - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Normal sram ports */ - if (0 < rr_gsb.get_sb_num_conf_bits()) { - add_sram_ports_to_module_manager(module_manager, module_id, - circuit_lib, sram_model, cur_sram_orgz_info->type, - rr_gsb.get_sb_num_conf_bits()); - /* Add ports only visible during formal verification to the module */ - add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, - std::string(verilog_formal_verification_preproc_flag), - rr_gsb.get_sb_num_conf_bits()); - } - - /* Print module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish printing ports */ - - print_verilog_comment(fp, std::string("---- BEGIN local wires for SRAM data ports ----")); - /* Local wires for memory configurations */ - print_verilog_switch_block_local_sram_wires(fp, rr_gsb, circuit_lib, sram_model, cur_sram_orgz_info->type, - rr_gsb.get_sb_num_conf_bits()); - print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); - - /* Create a counter for the configuration bus */ - BasicPort config_bus; - /* Counter start from 0 */ - config_bus.set_width(0, 0); - - /* Create a counter for the configuration bus used for formal verification */ - BasicPort fm_config_bus; - /* fm_config_bus has an invalid width here. It is designed to be easy to rotate */ - fm_config_bus.set_width(0, -1); - - /* TODO: Print routing multiplexers */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - print_verilog_comment(fp, std::string("----- " + side_manager.to_string() + " side Routing Multiplexers -----")); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - print_verilog_unique_switch_box_interc(module_manager, fp, cur_sram_orgz_info, - config_bus, fm_config_bus, - module_id, rr_sb, - circuit_lib, mux_lib, rr_switches, - side_manager.get_side(), - itrack, is_explicit_mapping); - } - } - } - - /* Add check code for config_bus. - * The MSB should match the number of configuration bits!!! - */ - VTR_ASSERT(true == check_switch_block_mem_config_bus(cur_sram_orgz_info->type, - rr_gsb, config_bus, - rr_gsb.get_sb_num_conf_bits())); - VTR_ASSERT(fm_config_bus.get_msb() == rr_gsb.get_sb_num_conf_bits() - 1); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the linked list */ - /* - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ - - return; -} - /* Task: Print the subckt of a Switch Box. * A Switch Box subckt consists of following ports: * 1. Channel Y [x][y] inputs @@ -3440,46 +2422,6 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c return num_reserved_conf_bits; } -/********************************************************************* - * Print a short interconneciton in connection - ********************************************************************/ -static -void print_verilog_connection_box_short_interc(std::fstream& fp, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - t_rr_node* src_rr_node) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Ensure we have only one 1 driver node */ - VTR_ASSERT_SAFE(1 == src_rr_node->fan_in); - - /* Find the driver node */ - t_rr_node* drive_rr_node = src_rr_node->drive_rr_nodes[0]; - - /* We have OPINs since we may have direct connections: - * These connections should be handled by other functions in the compact_netlist.c - * So we just return here for OPINs - */ - if (OPIN == drive_rr_node->type) { - return; - } - - VTR_ASSERT((CHANX == drive_rr_node->type) || (CHANY == drive_rr_node->type)); - - /* Create port description for the routing track middle output */ - BasicPort middle_output_port = generate_connection_block_chan_port(rr_gsb, cb_type, drive_rr_node); - - /* Create port description for input pin of a CLB */ - BasicPort input_port = generate_verilog_connection_box_ipin_port(rr_gsb, src_rr_node); - - /* Print the wire connection */ - print_verilog_wire_connection(fp, input_port, middle_output_port, false); - - return; -} - - /* SRC rr_node is the IPIN of a grid.*/ static void dump_verilog_connection_box_short_interc(FILE* fp, @@ -3630,191 +2572,6 @@ void dump_verilog_connection_box_short_interc(FILE* fp, return; } -/********************************************************************* - * Print a Verilog instance of a routing multiplexer as well as - * associated memory modules for a connection inside a connection block - ********************************************************************/ -static -void print_verilog_connection_box_mux(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info, - BasicPort& config_bus, - BasicPort& fm_config_bus, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* cur_rr_node, - const bool& use_explicit_mapping) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Check */ - /* Check current rr_node is an input pin of a CLB */ - VTR_ASSERT(IPIN == cur_rr_node->type); - - /* Build a vector of driver rr_nodes */ - std::vector drive_rr_nodes; - for (int inode = 0; inode < cur_rr_node->num_drive_rr_nodes; inode++) { - drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[inode]); - } - - int switch_index = cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - - /* Get the circuit model id of the routing multiplexer */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - - /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); - - /* Get the MUX instance id from the module manager */ - size_t mux_instance_id = module_manager.num_instance(cb_module, mux_module); - - /* Print the input bus for the inputs of a multiplexer - * We use the datapath input size (mux_size) to name the bus - * just to following the naming convention when the tool is built - * The bus port size should be the input size of multiplexer implementation - */ - BasicPort inbus_port; - inbus_port.set_name(generate_mux_input_bus_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id)); - inbus_port.set_width(datapath_mux_size); - - /* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */ - std::vector mux_input_ports = generate_connection_block_mux_input_ports(rr_gsb, cb_type, drive_rr_nodes); - /* Connect input ports to bus */ - print_verilog_comment(fp, std::string("----- BEGIN A local bus wire for multiplexer inputs -----")); - fp << generate_verilog_local_wire(inbus_port, mux_input_ports) << std::endl; - print_verilog_comment(fp, std::string("----- END A local bus wire for multiplexer inputs -----")); - fp << std::endl; - - /* Find the number of reserved configuration bits for the routing multiplexer */ - size_t mux_num_reserved_config_bits = find_mux_num_reserved_config_bits(circuit_lib, mux_model, mux_graph); - - /* Find the number of configuration bits for the routing multiplexer */ - size_t mux_num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - - /* Print the configuration bus for the routing multiplexers */ - print_verilog_comment(fp, std::string("----- BEGIN Local wires to group configuration ports -----")); - print_verilog_mux_config_bus(fp, circuit_lib, mux_model, cur_sram_orgz_info->type, - datapath_mux_size, mux_instance_id, - mux_num_reserved_config_bits, mux_num_config_bits); - print_verilog_comment(fp, std::string("----- END Local wires to group configuration ports -----")); - fp << std::endl; - - /* Dump ports visible only during formal verification */ - print_verilog_comment(fp, std::string("----- BEGIN Local wires used in only formal verification purpose -----")); - print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); - /* Print the SRAM configuration ports for formal verification */ - /* Update config bus for formal verification, - * shift with number of configuration bit of the MUX - */ - fm_config_bus.set_width(fm_config_bus.get_msb() + 1, fm_config_bus.get_msb() + mux_num_config_bits); - /* Align with the port width of formal verification port of SB module */ - print_verilog_formal_verification_mux_sram_ports_wiring(fp, circuit_lib, mux_model, - datapath_mux_size, mux_instance_id, - mux_num_config_bits, fm_config_bus); - print_verilog_endif(fp); - print_verilog_comment(fp, std::string("----- END Local wires used in only formal verification purpose -----")); - fp << std::endl; - - /* Instanciate the MUX Module */ - /* Create port-to-port map */ - std::map mux_port2port_name_map; - - /* Link input bus port to routing track middle outputs */ - std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == mux_model_input_ports.size()); - /* Use the port name convention in the circuit library */ - mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_input_ports[0])] = inbus_port; - - /* Link output port to Connection Block output: src_rr_node */ - std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == mux_model_output_ports.size()); - /* Use the port name convention in the circuit library */ - mux_port2port_name_map[circuit_lib.port_lib_name(mux_model_output_ports[0])] = generate_verilog_connection_box_ipin_port(rr_gsb, cur_rr_node); - - /* Link SRAM port to different configuraton port for the routing multiplexer - * Different design technology requires different configuration bus! - */ - std::vector mux_model_sram_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_SRAM, true); - VTR_ASSERT( 1 == mux_model_sram_ports.size() ); - /* For the regular SRAM port, module port use the same name */ - std::string mux_module_sram_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]); - BasicPort mux_config_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), - mux_num_config_bits); - mux_port2port_name_map[mux_module_sram_port_name] = mux_config_port; - - /* For the inverted SRAM port */ - std::string mux_module_sram_inv_port_name = circuit_lib.port_lib_name(mux_model_sram_ports[0]) + std::string("_inv"); - BasicPort mux_config_inv_port(generate_mux_sram_port_name(circuit_lib, mux_model, datapath_mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), - mux_num_config_bits); - mux_port2port_name_map[mux_module_sram_inv_port_name] = mux_config_inv_port; - - /* Print an instance of the MUX Module */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of a routing multiplexer -----")); - print_verilog_module_instance(fp, module_manager, cb_module, mux_module, mux_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of a routing multiplexer -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(cb_module, mux_module); - - /* Instanciate memory modules */ - /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); - ModuleId mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - - /* Create port-to-port map */ - std::map mem_port2port_name_map; - - /* TODO: Make the port2port map generation more generic!!! */ - /* Link the SRAM ports of the routing multiplexer to the memory module */ - std::vector mem_output_ports; - mem_output_ports.push_back(mux_config_port); - mem_output_ports.push_back(mux_config_inv_port); - mem_port2port_name_map = generate_mem_module_port2port_map(config_bus, - mem_output_ports, - circuit_lib.design_tech_type(mux_model), - cur_sram_orgz_info->type); - /* Update the config bus for the module */ - update_mem_module_config_bus(cur_sram_orgz_info->type, - circuit_lib.design_tech_type(mux_model), - mux_num_config_bits, - config_bus); - - /* Print an instance of the memory module associated with the routing multiplexer */ - print_verilog_comment(fp, std::string("----- BEGIN Instanciation of memory cells for a routing multiplexer -----")); - print_verilog_module_instance(fp, module_manager, cb_module, mem_module, mem_port2port_name_map, use_explicit_mapping); - print_verilog_comment(fp, std::string("----- END Instanciation of memory cells for a routing multiplexer -----")); - fp << std::endl; - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(cb_module, mem_module); - - /* Create the path of the input of multiplexer in the hierarchy - * TODO: this MUST be deprecated later because module manager is created to handle these problems!!! - */ - std::string mux_input_hie_path = std::string(rr_gsb.gen_cb_verilog_instance_name(cb_type)) + std::string("/") - + mux_module_name + std::string("_") - + std::to_string(mux_instance_id) + std::string("_/in"); - cur_rr_node->name_mux = my_strdup(mux_input_hie_path.c_str()); -} - - static void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -4307,45 +3064,6 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, return; } -/******************************************************************** - * Print internal connections of a connection block - * For a IPIN node that is driven by only 1 fan-in, - * a short wire will be created - * For a IPIN node that is driven by more than two fan-ins, - * a routing multiplexer will be instanciated - ********************************************************************/ -static -void print_verilog_connection_box_interc(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info, - BasicPort& config_bus, - BasicPort& fm_config_bus, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* src_rr_node, - const bool& use_explicit_mapping) { - if (1 > src_rr_node->fan_in) { - return; /* This port has no driver, skip it */ - } else if (1 == src_rr_node->fan_in) { - /* Print a direct connection */ - print_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); - - } else if (1 < src_rr_node->fan_in) { - /* Print the multiplexer, fan_in >= 2 */ - print_verilog_connection_box_mux(module_manager, fp, cur_sram_orgz_info, - config_bus, fm_config_bus, - cb_module, rr_gsb, cb_type, - circuit_lib, mux_lib, rr_switches, - src_rr_node, use_explicit_mapping); - } /*Nothing should be done else*/ - - return; -} - static void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -4493,294 +3211,6 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o return num_reserved_conf_bits; } -/******************************************************************** - * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) - * Actually it is very similiar to switch box but - * the difference is connection boxes connect Grid INPUT Pins to channels - * NOTE: direct connection between CLBs should NOT be included inside this - * module! They should be added in the top-level module as their connection - * is not limited to adjacent CLBs!!! - * - * Location of a X- and Y-direction Connection Block in FPGA fabric - * +------------+ +-------------+ - * | |------>| | - * | CLB |<------| Y-direction | - * | | ... | Connection | - * | |------>| Block | - * +------------+ +-------------+ - * | ^ ... | | ^ ... | - * v | v v | v - * +-------------------+ +-------------+ - * --->| |--->| | - * <---| X-direction |<---| Switch | - * ...| Connection block |... | Block | - * --->| |--->| | - * +-------------------+ +-------------+ - * - * Internal structure: - * This is an example of a X-direction connection block - * Note that middle output ports are shorted wire from inputs of routing tracks, - * which are also the inputs of routing multiplexer of the connection block - * - * CLB Input Pins - * (IPINs) - * ^ ^ ^ - * | | ... | - * +--------------------------+ - * | ^ ^ ^ | - * | | | ... | | - * | +--------------------+ | - * | | routing | | - * | | multiplexers | | - * | +--------------------+ | - * | middle outputs | - * | of routing channel | - * | ^ ^ ^ ^ ^ ^ ^ ^ | - * | | | | | ... | | | | | - * in[0] -->|------------------------->|---> out[0] - * out[1] <--|<-------------------------|<--- in[1] - * | ... | - * in[W-2] -->|------------------------->|---> out[W-2] - * out[W-1] <--|<-------------------------|<--- in[W-1] - * +--------------------------+ - * - * W: routing channel width - * - ********************************************************************/ -static -void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& subckt_dir, - const RRGSB& rr_cb, - const t_rr_type& cb_type, - const bool& use_explicit_mapping) { - RRGSB rr_gsb = rr_cb; /* IMPORTANT: this copy will be removed when the config ports are initialized when created!!! */ - - /* TODO: These should be done when initializing the tool */ - /* Count the number of configuration bits to be consumed by this Switch block */ - int num_conf_bits = (int)find_connection_block_num_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_gsb, cb_type); - /* Count the number of reserved configuration bits to be consumed by this Switch block */ - int num_reserved_conf_bits = (int)find_connection_block_num_shared_conf_bits(cur_sram_orgz_info, circuit_lib, mux_lib, rr_switches, rr_gsb, cb_type); - /* Estimate the sram_verilog_model->cnt */ - int cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - /* Record index */ - rr_gsb.set_cb_num_reserved_conf_bits(cb_type, num_reserved_conf_bits); - rr_gsb.set_cb_conf_bits_lsb(cb_type, cur_num_sram); - rr_gsb.set_cb_conf_bits_msb(cb_type, cur_num_sram + num_conf_bits - 1); - - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); - - /* Add ports to the module */ - /* Global ports: - * In the circuit_library, find all the circuit models that may be included in the Connection Block - * Collect the global ports from the circuit_models and merge with the same name - */ - std::vector global_ports = find_connection_block_global_ports(rr_gsb, cb_type, circuit_lib, rr_switches); - for (const auto& port : global_ports) { - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_GLOBAL_PORT); - } - - /* Add the input and output ports of routing tracks in the channel - * Routing tracks pass through the connection blocks - */ - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - IN_PORT); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); - } - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - OUT_PORT); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* Add the input pins of grids, which are output ports of the connection block */ - std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); - std::string port_name = generate_grid_side_port_name(port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), - ipin_node->ptc_num); - BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ - /* Grid outputs are inputs of switch blocks */ - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); - } - } - - /* Add configuration ports */ - /* Reserved sram ports */ - if (0 < rr_gsb.get_cb_num_reserved_conf_bits(cb_type)) { - /* Check: this SRAM organization type must be memory-bank ! */ - VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); - /* Generate a list of ports */ - add_reserved_sram_ports_to_module_manager(module_manager, module_id, - rr_gsb.get_cb_num_reserved_conf_bits(cb_type)); - } - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Normal sram ports */ - if (0 < rr_gsb.get_cb_num_conf_bits(cb_type)) { - add_sram_ports_to_module_manager(module_manager, module_id, - circuit_lib, sram_model, cur_sram_orgz_info->type, - rr_gsb.get_cb_num_conf_bits(cb_type)); - /* Add ports only visible during formal verification to the module */ - add_formal_verification_sram_ports_to_module_manager(module_manager, module_id, circuit_lib, sram_model, - std::string(verilog_formal_verification_preproc_flag), - rr_gsb.get_cb_num_conf_bits(cb_type)); - } - - /* Print module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish printing ports */ - - /* Print an empty line a splitter */ - fp << std::endl; - - /* Print local wires, which are middle outputs of routing tracks */ - print_verilog_comment(fp, std::string("---- BEGIN local wires for middle output ports of routing tracks ----")); - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - /* Create a port description for the middle output */ - std::string port_name = generate_routing_track_middle_output_port_name(cb_type, - port_coord, itrack); - BasicPort middle_output_port(port_name, 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, middle_output_port) << ";" << std::endl; - } - print_verilog_comment(fp, std::string("---- END local wires for middle output ports of routing tracks ----")); - /* Print an empty line a splitter */ - fp << std::endl; - - /* Print short-wire connection for each routing track : - * Each input port is short-wired to its output port and middle output port - * - * in[i] ----------> out[i] - * | - * +-----> mid_out[i] - */ - print_verilog_comment(fp, std::string("---- BEGIN wire connection between inputs, outputs and middle outputs of routing tracks ----")); - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - /* Create a port description for the input */ - std::string input_port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - IN_PORT); - BasicPort input_port(input_port_name, 1); /* Every track has a port size of 1 */ - - /* Create a port description for the output */ - std::string output_port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - OUT_PORT); - BasicPort output_port(output_port_name, 1); /* Every track has a port size of 1 */ - - /* Create a port description for the middle output */ - std::string middle_output_port_name = generate_routing_track_middle_output_port_name(cb_type, port_coord, itrack); - BasicPort middle_output_port(middle_output_port_name, 1); - - /* Print short-wires: input port ---> output port */ - print_verilog_wire_connection(fp, output_port, input_port, false); - /* Print short-wires: input port ---> middle output port */ - print_verilog_wire_connection(fp, middle_output_port, input_port, false); - } - print_verilog_comment(fp, std::string("---- END wire connection between inputs, outputs and middle outputs of routing tracks ----")); - - /* Print an empty line a splitter */ - fp << std::endl; - - print_verilog_comment(fp, std::string("---- BEGIN local wires for SRAM data ports ----")); - /* Print local wires for memory configurations */ - print_verilog_connection_block_local_sram_wires(fp, rr_gsb, cb_type, circuit_lib, sram_model, cur_sram_orgz_info->type, - rr_gsb.get_cb_num_conf_bits(cb_type)); - print_verilog_comment(fp, std::string("---- END local wires for SRAM data ports ----")); - - /* Print an empty line a splitter */ - fp << std::endl; - - /* Create a counter for the configuration bus */ - BasicPort config_bus; - /* Counter start from 0 */ - config_bus.set_width(0, 0); - - /* Create a counter for the configuration bus used for formal verification */ - BasicPort fm_config_bus; - /* fm_config_bus has an invalid width here. It is designed to be easy to rotate */ - fm_config_bus.set_width(0, -1); - - /* TODO: Print routing multiplexers or direct interconnect*/ - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - print_verilog_connection_box_interc(module_manager, fp, cur_sram_orgz_info, - config_bus, fm_config_bus, - module_id, rr_gsb, cb_type, - circuit_lib, mux_lib, rr_switches, - rr_gsb.get_ipin_node(cb_ipin_side, inode), - use_explicit_mapping); - } - } - - /* Add check code for config_bus. - * The MSB should match the number of configuration bits!!! - */ - VTR_ASSERT(true == check_connection_block_mem_config_bus(cur_sram_orgz_info->type, - rr_gsb, cb_type, config_bus, - rr_gsb.get_cb_num_conf_bits(cb_type))); - VTR_ASSERT(fm_config_bus.get_msb() == rr_gsb.get_cb_num_conf_bits(cb_type) - 1); - - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the linked list */ - /* - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - */ -} - - - /* Print connection boxes * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) * Actually it is very similiar to switch box but @@ -5184,29 +3614,6 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ return; } -/********************************************************************* - * Generate the port name for a Grid - * This is a wrapper function for generate_port_name() - * which can automatically decode the port name by the pin side and height - * - * TODO: This function is dependent on the global variable: grid - * This should be replaced by a local variable!!! - *********************************************************************/ -std::string generate_grid_side_port_name(const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - int height = get_grid_pin_height(coordinate.x(), coordinate.y(), (int)pin_id); - if (1 != grid[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", - __FILE__, __LINE__, - coordinate.x(), coordinate.y(), height, convert_side_index_to_string(side), pin_id); - exit(1); - } - return generate_grid_port_name(coordinate, (size_t)height, side, pin_id, true); -} - /********************************************************************* * Top-level function: * Build the Verilog modules for global routing architecture @@ -5224,7 +3631,6 @@ std::string generate_grid_side_port_name(const vtr::Point& coordinate, * unique modules in terms of internal logics *********************************************************************/ void print_verilog_routing_resources(ModuleManager& module_manager, - const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, @@ -5292,9 +3698,6 @@ void print_verilog_routing_resources(ModuleManager& module_manager, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, arch.num_segments); - vtr::Point chan_coordinate((size_t)ix, (size_t)iy); - print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANX, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } } /* Y - channels [1...ny][0..nx]*/ @@ -5305,9 +3708,6 @@ void print_verilog_routing_resources(ModuleManager& module_manager, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, arch.num_segments); - vtr::Point chan_coordinate((size_t)ix, (size_t)iy); - print_verilog_routing_chan_subckt(module_manager, std::string(verilog_dir), std::string(subckt_dir), chan_coordinate, CHANY, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); } } } @@ -5322,11 +3722,6 @@ void print_verilog_routing_resources(ModuleManager& module_manager, const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, explicit_port_mapping); - print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib, - rr_switches, - cur_sram_orgz_info, std::string(verilog_dir), - std::string(subckt_dir), unique_mirror, - explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -5369,14 +3764,6 @@ void print_verilog_routing_resources(ModuleManager& module_manager, verilog_dir, subckt_dir, unique_mirror, CHANX, explicit_port_mapping); - print_verilog_routing_connection_box_unique_module(module_manager, - arch.spice->circuit_lib, mux_lib, - rr_switches, - cur_sram_orgz_info, - std::string(verilog_dir), - std::string(subckt_dir), - unique_mirror, CHANX, - explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ @@ -5386,14 +3773,6 @@ void print_verilog_routing_resources(ModuleManager& module_manager, verilog_dir, subckt_dir, unique_mirror, CHANY, explicit_port_mapping); - print_verilog_routing_connection_box_unique_module(module_manager, - arch.spice->circuit_lib, mux_lib, - rr_switches, - cur_sram_orgz_info, - std::string(verilog_dir), - std::string(subckt_dir), - unique_mirror, CHANY, - explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -5454,3 +3833,332 @@ void print_verilog_routing_resources(ModuleManager& module_manager, return; } + + +/******************************************************************** + * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) + * Actually it is very similiar to switch box but + * the difference is connection boxes connect Grid INPUT Pins to channels + * NOTE: direct connection between CLBs should NOT be included inside this + * module! They should be added in the top-level module as their connection + * is not limited to adjacent CLBs!!! + * + * Location of a X- and Y-direction Connection Block in FPGA fabric + * +------------+ +-------------+ + * | |------>| | + * | CLB |<------| Y-direction | + * | | ... | Connection | + * | |------>| Block | + * +------------+ +-------------+ + * | ^ ... | | ^ ... | + * v | v v | v + * +-------------------+ +-------------+ + * --->| |--->| | + * <---| X-direction |<---| Switch | + * ...| Connection block |... | Block | + * --->| |--->| | + * +-------------------+ +-------------+ + * + * Internal structure: + * This is an example of a X-direction connection block + * Note that middle output ports are shorted wire from inputs of routing tracks, + * which are also the inputs of routing multiplexer of the connection block + * + * CLB Input Pins + * (IPINs) + * ^ ^ ^ + * | | ... | + * +--------------------------+ + * | ^ ^ ^ | + * | | | ... | | + * | +--------------------+ | + * | | routing | | + * | | multiplexers | | + * | +--------------------+ | + * | middle outputs | + * | of routing channel | + * | ^ ^ ^ ^ ^ ^ ^ ^ | + * | | | | | ... | | | | | + * in[0] -->|------------------------->|---> out[0] + * out[1] <--|<-------------------------|<--- in[1] + * | ... | + * in[W-2] -->|------------------------->|---> out[W-2] + * out[W-1] <--|<-------------------------|<--- in[W-1] + * +--------------------------+ + * + * W: routing channel width + * + ********************************************************************/ +static +void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager, + const std::string& verilog_dir, + const std::string& subckt_dir, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const bool& use_explicit_port_map) { + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + + /* Write the verilog module */ + write_verilog_module_to_file(fp, module_manager, cb_module, use_explicit_port_map); + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + */ +} + +/********************************************************************* + * Generate the Verilog module for a Switch Box. + * A Switch Box module consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * Location of a Switch Box in FPGA fabric: + * + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + * + * Switch Block pin location map + * + * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] + * right_pins inputs/outputs left_pins + * | ^ | + * | | | + * v v v + * +-----------------------------------------------+ + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * bottom_pins---->| |<---- bottom_pins + * | | + * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] + * inputs/outputs<--->| |<---> inputs/outputs + * | | + * Grid[x][y+1] | | Grid[x+1][y+1] + * top_pins---->| |<---- top_pins + * | | + * +-----------------------------------------------+ + * ^ ^ ^ + * | | | + * | v | + * Grid[x][y] ChanY[x][y] Grid[x+1][y] + * right_pins inputs/outputs left_pins + * + * + ********************************************************************/ +static +void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, + const std::string& verilog_dir, + const std::string& subckt_dir, + const RRGSB& rr_gsb, + const bool& use_explicit_port_map) { + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); + /* TODO: remove the bak file when the file is ready */ + verilog_fname += ".bak"; + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); + + /* Print preprocessing flags */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Create a Verilog Module based on the circuit model, and add to module manager */ + ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Write the verilog module */ + write_verilog_module_to_file(fp, module_manager, sb_module, use_explicit_port_map); + + /* Close file handler */ + fp.close(); + + /* Add fname to the linked list */ + /* + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + */ + + return; +} + + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and build a module for each of them + *******************************************************************/ +static +void print_verilog_flatten_connection_block_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const std::string& verilog_dir, + const std::string& subckt_dir, + const t_rr_type& cb_type, + const bool& use_explicit_port_map) { + /* Build unique X-direction connection block modules */ + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + if ( (TRUE != is_cb_exist(CHANX, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + print_verilog_routing_connection_box_unique_module(module_manager, + verilog_dir, + subckt_dir, + rr_gsb, cb_type, + use_explicit_port_map); + } + } +} + +/******************************************************************** + * A top-level function of this file + * Print all the modules for global routing architecture of a FPGA fabric + * in Verilog format in a flatten way: + * Each connection block and switch block will be generated as a unique module + * Covering: + * 1. Connection blocks + * 2. Switch blocks + *******************************************************************/ +void print_verilog_flatten_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const t_det_routing_arch& routing_arch, + const std::string& verilog_dir, + const std::string& subckt_dir, + const bool& use_explicit_port_map) { + /* We only support uni-directional routing architecture now */ + VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); + + /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + + /* Build unique switch block modules */ + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + print_verilog_routing_switch_box_unique_module(module_manager, + verilog_dir, + subckt_dir, + rr_gsb, + use_explicit_port_map); + } + } + + print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); + + print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + +} + + +/******************************************************************** + * A top-level function of this file + * Print all the unique modules for global routing architecture of a FPGA fabric + * in Verilog format, including: + * 1. Connection blocks + * 2. Switch blocks + * + * Note: this function SHOULD be called only when + * the option compact_routing_hierarchy is turned on!!! + *******************************************************************/ +void print_verilog_unique_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const t_det_routing_arch& routing_arch, + const std::string& verilog_dir, + const std::string& subckt_dir, + const bool& use_explicit_port_map) { + /* We only support uni-directional routing architecture now */ + VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); + + /* Build unique switch block modules */ + for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb); + print_verilog_routing_switch_box_unique_module(module_manager, + verilog_dir, + subckt_dir, + unique_mirror, + use_explicit_port_map); + } + + /* Build unique X-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); + + print_verilog_routing_connection_box_unique_module(module_manager, + verilog_dir, + subckt_dir, + unique_mirror, CHANX, + use_explicit_port_map); + } + + /* Build unique X-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); + + print_verilog_routing_connection_box_unique_module(module_manager, + verilog_dir, + subckt_dir, + unique_mirror, CHANY, + use_explicit_port_map); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 8cb8b8ecf..23132fcdc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -142,13 +142,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ boolean compact_routing_hierarchy, bool is_explicit_mapping); - -std::string generate_grid_side_port_name(const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id); - void print_verilog_routing_resources(ModuleManager& module_manager, - const MuxLibrary& mux_lib, t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, @@ -159,4 +153,18 @@ void print_verilog_routing_resources(ModuleManager& module_manager, t_rr_indexed_data* LL_rr_indexed_data, const t_fpga_spice_opts& FPGA_SPICE_Opts); +void print_verilog_flatten_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const t_det_routing_arch& routing_arch, + const std::string& verilog_dir, + const std::string& subckt_dir, + const bool& use_explicit_port_map); + +void print_verilog_unique_routing_modules(ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const t_det_routing_arch& routing_arch, + const std::string& verilog_dir, + const std::string& subckt_dir, + const bool& use_explicit_port_map); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 136cef804..9939c406f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -19,7 +19,7 @@ #include "build_top_module_directs.h" #include "verilog_global.h" -#include "verilog_routing.h" +#include "build_module_graph_utils.h" #include "verilog_writer_utils.h" #include "verilog_module_writer.h" #include "verilog_top_module.h" @@ -401,7 +401,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, /* Collect sink-related information */ vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string sink_sb_port_name = generate_grid_side_port_name(sink_sb_port_coord, + std::string sink_sb_port_name = generate_grid_side_port_name(grids, sink_sb_port_coord, module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); @@ -526,7 +526,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, /* Collect source-related information */ t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode); vtr::Point cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow); - std::string src_cb_port_name = generate_grid_side_port_name(cb_src_port_coord, + std::string src_cb_port_name = generate_grid_side_port_name(grids, cb_src_port_coord, module_cb.get_ipin_node_grid_side(cb_ipin_side, inode), module_ipin_node->ptc_num); ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); From fb2f003d5b1b6220a12eacd91ea18ec6b70c1f6f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Oct 2019 12:16:58 -0600 Subject: [PATCH 323/482] add top module generation and refactored verilog generation for top module --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 10 +- .../module_builder/build_module_graph.cpp | 10 +- .../module_builder/build_module_graph.h | 2 + .../module_builder/build_top_module.cpp | 889 ++++++++++++++++++ .../module_builder/build_top_module.h | 25 + .../build_top_module_memory.cpp | 20 +- .../module_builder/build_top_module_memory.h | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 22 +- .../fpga_x2p/verilog/verilog_top_module.cpp | 866 +---------------- .../SRC/fpga_x2p/verilog/verilog_top_module.h | 13 - 10 files changed, 949 insertions(+), 910 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 099047c33..3f1ee9e03 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -71,8 +71,16 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, } } + /* Organize a vector (matrix) of clb2clb directs to feed the top-level module generation */ + std::vector clb2clb_directs; + for (int i = 0; i < num_clb2clb_directs; ++i) { + clb2clb_directs.push_back(clb2clb_direct[i]); + } + /* Build module graphs */ - ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib, grids, rr_switches, device_rr_gsb); + ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib, + device_size, grids, + rr_switches, clb2clb_directs, device_rr_gsb); /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index f6b8c23cd..b35f2d152 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -19,6 +19,7 @@ #include "build_memory_modules.h" #include "build_grid_modules.h" #include "build_routing_modules.h" +#include "build_top_module.h" #include "build_module_graph.h" /******************************************************************** @@ -28,8 +29,10 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, const t_arch& arch, const MuxLibrary& mux_lib, + const vtr::Point& device_size, const std::vector>& grids, const std::vector& rr_switches, + const std::vector& clb2clb_directs, const DeviceRRGSB& L_device_rr_gsb) { /* Check if the routing architecture we support*/ if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { @@ -121,7 +124,12 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, } - /* TODO: Build FPGA fabric top-level module */ + /* Build FPGA fabric top-level module */ + build_top_module(module_manager, arch.spice->circuit_lib, + device_size, grids, L_device_rr_gsb, + clb2clb_directs, + arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, + TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h index 2cea75913..f1375668f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h @@ -10,8 +10,10 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, const t_arch& arch, const MuxLibrary& mux_lib, + const vtr::Point& device_size, const std::vector>& grids, const std::vector& rr_switches, + const std::vector& clb2clb_directs, const DeviceRRGSB& L_device_rr_gsb); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp new file mode 100644 index 000000000..e3e6d13c4 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -0,0 +1,889 @@ +/******************************************************************** + * This file includes functions that are used to print the top-level + * module for the FPGA fabric in Verilog format + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" + +#include "vpr_types.h" +#include "globals.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" +#include "module_manager_utils.h" +#include "build_top_module_memory.h" +#include "build_top_module_directs.h" + +#include "verilog_global.h" +#include "build_module_graph_utils.h" +#include "build_top_module.h" + +/******************************************************************** + * Generate the name for a grid block, by considering + * 1. if it locates on the border with given device size + * 2. its type + * + * This function is mainly used in the top-level module generation + *******************************************************************/ +static +std::string generate_grid_block_module_name_in_top_module(const std::string& prefix, + const vtr::Point& device_size, + const std::vector>& grids, + const vtr::Point& grid_coordinate) { + /* Determine if the grid locates at the border */ + e_side border_side = find_grid_border_side(device_size, grid_coordinate); + + return generate_grid_block_module_name(prefix, std::string(grids[grid_coordinate.x()][grid_coordinate.y()].type->name), + IO_TYPE == grids[grid_coordinate.x()][grid_coordinate.y()].type, border_side); +} + +/******************************************************************** + * Find the cb_type of a GSB in the top-level module + * depending on the side of SB + * TOP/BOTTOM side: CHANY + * RIGHT/LEFT side: CHANX + *******************************************************************/ +static +t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { + VTR_ASSERT(NUM_SIDES != sb_side); + + if ((TOP == sb_side) || (BOTTOM == sb_side)) { + return CHANY; + } + + VTR_ASSERT((RIGHT == sb_side) || (LEFT == sb_side)); + return CHANX; +} + +/******************************************************************** + * Find the GSB coordinate for a CB in the top-level module + * depending on the side of a SB + * TODO: use vtr::Point to replace DeviceCoordinator + *******************************************************************/ +static +DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb, + const e_side& sb_side) { + VTR_ASSERT(NUM_SIDES != sb_side); + + DeviceCoordinator gsb_coordinate; + + if ((TOP == sb_side) || (LEFT == sb_side)) { + gsb_coordinate.set_x(rr_gsb.get_x()); + gsb_coordinate.set_y(rr_gsb.get_y()); + return gsb_coordinate; + } + + VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); + DeviceCoordinator side_coord = rr_gsb.get_side_block_coordinator(sb_side); + + gsb_coordinate.set_x(side_coord.get_x()); + gsb_coordinate.set_y(side_coord.get_y()); + + return gsb_coordinate; +} + +/******************************************************************** + * Add a instance of a grid module to the top module + *******************************************************************/ +static +size_t add_top_module_grid_instance(ModuleManager& module_manager, + const ModuleId& top_module, + t_type_ptr grid_type, + const e_side& border_side) { + /* Find the module name for this type of grid */ + std::string grid_module_name_prefix(grid_verilog_file_name_prefix); + std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); + ModuleId grid_module = module_manager.find_module(grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); + /* Record the instance id */ + size_t grid_instance = module_manager.num_instance(top_module, grid_module); + /* Add the module to top_module */ + module_manager.add_child_module(top_module, grid_module); + + return grid_instance; +} + +/******************************************************************** + * Add all the grids as sub-modules across the fabric + * The grid modules are created for each unique type of grid (based + * on the type in data structure data_structure + * Here, we will iterate over the full fabric (coordinates) + * and instanciate the grid modules + * + * Return an 2-D array of instance ids of the grid modules that + * have been added + * + * This function assumes an island-style floorplanning for FPGA fabric + * + * + * +-----------------------------------+ + * | I/O grids | + * | TOP side | + * +-----------------------------------+ + * + * +-----------+ +-----------------------------------+ +------------+ + * | | | | | | + * | I/O grids | | Core grids | | I/O grids | + * | LEFT side | | (CLB, Heterogeneous blocks, etc.) | | RIGHT side | + * | | | | | | + * +-----------+ +-----------------------------------+ +------------+ + * + * +-----------------------------------+ + * | I/O grids | + * | BOTTOM side | + * +-----------------------------------+ + * + *******************************************************************/ +static +std::vector> add_top_module_grid_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids) { + /* Reserve an array for the instance ids */ + std::vector> grid_instance_ids; + grid_instance_ids.resize(grids.size()); + for (size_t x = 0; x < grids.size(); ++x) { + /* Deposite an invalid value */ + grid_instance_ids[x].resize(grids[x].size(), size_t(-1)); + } + + /* Instanciate core grids */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + /* Bypass EMPTY grid */ + if (EMPTY_TYPE == grids[ix][iy].type) { + continue; + } + /* Skip height > 1 tiles (mostly heterogeneous blocks) */ + if (0 < grids[ix][iy].offset) { + continue; + } + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE != grids[ix][iy].type); + /* Add a grid module to top_module*/ + grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module, + grids[ix][iy].type, + NUM_SIDES); + } + } + + /* Instanciate I/O grids */ + /* Create the coordinate range for each side of FPGA fabric */ + std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; + std::map>> io_coordinates; + + /* TOP side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); + } + + /* RIGHT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); + } + + /* BOTTOM side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); + } + + /* LEFT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[LEFT].push_back(vtr::Point(0, iy)); + } + + /* Add instances of I/O grids to top_module */ + for (const e_side& io_side : io_sides) { + for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + /* Bypass EMPTY grid */ + if (EMPTY_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type) { + continue; + } + /* Skip height > 1 tiles (mostly heterogeneous blocks) */ + if (0 < grids[io_coordinate.x()][io_coordinate.y()].offset) { + continue; + } + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); + /* Add a grid module to top_module*/ + grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side); + } + } + + return grid_instance_ids; +} + +/******************************************************************** + * Add switch blocks across the FPGA fabric to the top-level module + * Return an 2-D array of instance ids of the switch blocks that + * have been added + *******************************************************************/ +static +std::vector> add_top_module_switch_block_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy) { + /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + + /* Reserve an array for the instance ids */ + std::vector> sb_instance_ids; + sb_instance_ids.resize(sb_range.get_x()); + for (size_t x = 0; x < sb_range.get_x(); ++x) { + /* Deposite an invalid value */ + sb_instance_ids[x].resize(sb_range.get_y(), size_t(-1)); + } + + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_x()); + if (true == compact_routing_hierarchy) { + DeviceCoordinator sb_coord(ix, iy); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + sb_coordinate.set_x(unique_mirror.get_sb_x()); + sb_coordinate.set_y(unique_mirror.get_sb_y()); + } + std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + /* Record the instance id */ + sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module); + /* Add the module to top_module */ + module_manager.add_child_module(top_module, sb_module); + } + } + + return sb_instance_ids; +} + +/******************************************************************** + * Add switch blocks across the FPGA fabric to the top-level module + *******************************************************************/ +static +std::vector> add_top_module_connection_block_instances(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const t_rr_type& cb_type, + const bool& compact_routing_hierarchy) { + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + /* Reserve an array for the instance ids */ + std::vector> cb_instance_ids; + cb_instance_ids.resize(cb_range.get_x()); + for (size_t x = 0; x < cb_range.get_x(); ++x) { + /* Deposite an invalid value */ + cb_instance_ids[x].resize(cb_range.get_y(), size_t(-1)); + } + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + const DeviceCoordinator cb_coordinator = rr_gsb.get_cb_coordinator(cb_type); + if ( (TRUE != is_cb_exist(cb_type, cb_coordinator.get_x(), cb_coordinator.get_y())) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator cb_coord(ix, iy); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); + cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); + } + std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); + ModuleId cb_module = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + /* Record the instance id */ + cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module); + /* Add the module to top_module */ + module_manager.add_child_module(top_module, cb_module); + } + } + + return cb_instance_ids; +} + +/******************************************************************** + * Add module nets to connect a GSB to adjacent grid ports/pins + * as well as connection blocks + * This function will create nets for the following types of connections + * between grid output pins of Switch block and adjacent grids + * In this case, the net source is the grid pin, while the net sink + * is the switch block pin + * + * +------------+ +------------+ + * | | | | + * | Grid | | Grid | + * | [x][y+1] | | [x+1][y+1] | + * | | | | + * +------------+ +------------+ + * | | + * | +------------+ | + * +------>| |<-----+ + * | Switch | + * | Block | + * +------>| [x][y] |<-----+ + * | +------------+ | + * | | + * | | + * +------------+ +------------+ + * | | | | + * | Grid | | Grid | + * | [x][y] | | [x+1][y] | + * | | | | + * +------------+ +------------+ + * + *******************************************************************/ +static +void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const RRGSB& rr_gsb, + const std::vector>& sb_instance_ids, + const bool& compact_routing_hierarchy) { + + /* We could have two different coordinators, one is the instance, the other is the module */ + vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); + module_gsb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_coordinate.set_y(unique_mirror.get_y()); + } + + /* This is the source cb that is added to the top module */ + const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); + vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); + + /* Collect sink-related information */ + std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate); + ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); + size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; + + /* Connect grid output pins (OPIN) to switch block grid pins */ + for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + /* Collect source-related information */ + /* Generate the grid module name by considering if it locates on the border */ + vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); + std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); + ModuleId src_grid_module = module_manager.find_module(src_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); + size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; + size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num; + size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index); + std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false); + ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); + BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); + + /* Collect sink-related information */ + vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, + module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); + std::string sink_sb_port_name = generate_grid_side_port_name(grids, sink_sb_port_coord, + module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), + src_grid_pin_index); + ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); + BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(top_module); + /* Configure the net source */ + module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]); + } + } + } +} + +/******************************************************************** + * This function will create nets for the connections + * between grid input pins and connection blocks + * In this case, the net source is the connection block pin, + * while the net sink is the grid input + * + * +------------+ +------------------+ +------------+ + * | | | | | | + * | Grid |<-----| Connection Block |----->| Grid | + * | [x][y+1] | | Y-direction | | [x+1][y+1] | + * | | | [x][y+1] | | | + * +------------+ +------------------+ +------------+ + * ^ + * | + * +------------+ +------------------+ + * | Connection | | | + * | Block | | Switch Block | + * | X-direction| | [x][y] | + * | [x][y] | | | + * +------------+ +------------------+ + * | + * v + * +------------+ + * | | + * | Grid | + * | [x][y] | + * | | + * +------------+ + * + * + * Relationship between source connection block and its unique module + * Take an example of a CBY + * + * grid_pin name should follow unique module of Grid[x][y+1] + * cb_pin name should follow unique module of CBY[x][y+1] + * + * However, instace id should follow the origin Grid and Connection block + * + * + * +------------+ +------------------+ + * | | | | + * | Grid |<------------| Connection Block | + * | [x][y+1] | | Y-direction | + * | | | [x][y+1] | + * +------------+ +------------------+ + * ^ + * || unique mirror + * +------------+ +------------------+ + * | | | | + * | Grid |<------------| Connection Block | + * | [i][j+1] | | Y-direction | + * | | | [i][j+1] | + * +------------+ +------------------+ + * + *******************************************************************/ +static +void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector>& cb_instance_ids, + const bool& compact_routing_hierarchy) { + /* We could have two different coordinators, one is the instance, the other is the module */ + vtr::Point instance_cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + + /* Skip those Connection blocks that do not exist */ + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + return; + } + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, gsb_coord); + module_gsb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_coordinate.set_y(unique_mirror.get_y()); + } + + /* This is the source cb that is added to the top module */ + const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); + vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); + + /* Collect source-related information */ + std::string src_cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); + ModuleId src_cb_module = module_manager.find_module(src_cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_cb_module)); + /* Instance id should follow the instance cb coordinate */ + size_t src_cb_instance = cb_instance_ids[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; + + /* Iterate over the output pins of the Connection Block */ + std::vector cb_ipin_sides = module_cb.get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < module_cb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + /* Collect source-related information */ + t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode); + vtr::Point cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow); + std::string src_cb_port_name = generate_grid_side_port_name(grids, cb_src_port_coord, + module_cb.get_ipin_node_grid_side(cb_ipin_side, inode), + module_ipin_node->ptc_num); + ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id)); + BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); + + /* Collect sink-related information */ + /* Note that we use the instance cb pin here!!! + * because it has the correct coordinator for the grid!!! + */ + t_rr_node* instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + vtr::Point grid_coordinate(instance_ipin_node->xlow, instance_ipin_node->ylow); + std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); + ModuleId sink_grid_module = module_manager.find_module(sink_grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); + size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; + size_t sink_grid_pin_index = instance_ipin_node->ptc_num; + size_t sink_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, sink_grid_pin_index); + std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_height, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), sink_grid_pin_index, false); + ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id)); + BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(top_module); + /* Configure the net source */ + module_manager.add_module_net_source(top_module, net, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]); + /* Configure the net sink */ + module_manager.add_module_net_sink(top_module, net, sink_grid_module, sink_grid_instance, sink_grid_port_id, sink_grid_port.pins()[pin_id]); + } + } + } +} + +/******************************************************************** + * This function will create nets for the connections + * between connection block and switch block pins + * Two cases should be considered: + * a. The switch block pin denotes an input of a routing track + * The net source is an output of a routing track of connection block + * while the net sink is an input of a routing track of switch block + * b. The switch block pin denotes an output of a routing track + * The net source is an output of routing track of switch block + * while the net sink is an input of a routing track of connection block + * + * +------------+ +------------------+ +------------+ + * | | | | | | + * | Grid | | Connection Block | | Grid | + * | [x][y+1] | | Y-direction | | [x+1][y+1] | + * | | | [x][y+1] | | | + * +------------+ +------------------+ +------------+ + * | ^ + * v | + * +------------+ +------------------+ +------------+ + * | Connection |----->| |----->| Connection | + * | Block | | Switch Block | | Block | + * | X-direction|<-----| [x][y] |<-----| X-direction| + * | [x][y] | | | | [x+1][y] | + * +------------+ +------------------+ +------------+ + * | ^ + * v | + * +------------+ +------------------+ +------------+ + * | | | | | | + * | Grid | | Connection Block | | Grid | + * | [x][y] | | Y-direction | | [x][y+1] | + * | | | [x][y] | | | + * +------------+ +------------------+ +------------+ + * + * Here, to achieve the purpose, we can simply iterate over the + * four sides of switch block and make connections to adjancent + * connection blocks + * + *******************************************************************/ +static +void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb, + const RRGSB& rr_gsb, + const std::vector>& sb_instance_ids, + const std::map>>& cb_instance_ids, + const bool& compact_routing_hierarchy) { + /* We could have two different coordinators, one is the instance, the other is the module */ + vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + DeviceCoordinator module_gsb_sb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); + module_gsb_sb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_sb_coordinate.set_y(unique_mirror.get_y()); + } + + /* This is the source cb that is added to the top module */ + const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_sb_coordinate); + vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); + std::string sb_module_name = generate_switch_block_module_name(module_sb_coordinate); + ModuleId sb_module_id = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module_id)); + size_t sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; + + /* Connect grid output pins (OPIN) to switch block grid pins */ + for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { + Side side_manager(side); + /* Iterate over the routing tracks on this side */ + DeviceCoordinator port_coordinator = module_sb.get_side_block_coordinator(side_manager.get_side()); + /* Early skip: if there is no routing tracks at this side */ + if (0 == module_sb.get_chan_width(side_manager.get_side())) { + continue; + } + /* Find the Connection Block module */ + /* We find the original connection block and then spot its unique mirror! + * Do NOT use module_sb here!!! + */ + t_rr_type cb_type = find_top_module_cb_type_by_sb_side(side_manager.get_side()); + DeviceCoordinator instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); + DeviceCoordinator module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); + + /* Skip those Connection blocks that do not exist */ + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + + /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ + if (true == compact_routing_hierarchy) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, module_gsb_cb_coordinate); + module_gsb_cb_coordinate.set_x(unique_mirror.get_x()); + module_gsb_cb_coordinate.set_y(unique_mirror.get_y()); + } + + const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); + vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); + std::string cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); + ModuleId cb_module_id = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module_id)); + const RRGSB& instance_cb = L_device_rr_gsb.get_gsb(instance_gsb_cb_coordinate); + vtr::Point instance_cb_coordinate(instance_cb.get_cb_x(cb_type), instance_cb.get_cb_y(cb_type)); + size_t cb_instance = cb_instance_ids.at(cb_type)[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; + + for (size_t itrack = 0; itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) { + vtr::Point sb_port_coord(port_coordinator.get_x(), port_coordinator.get_y()); + std::string sb_port_name = generate_routing_track_port_name(module_sb.get_chan_node(side_manager.get_side(), itrack)->type, + sb_port_coord, itrack, + module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + /* Prepare SB-related port information */ + ModulePortId sb_port_id = module_manager.find_module_port(sb_module_id, sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module_id, sb_port_id)); + BasicPort sb_port = module_manager.module_port(sb_module_id, sb_port_id); + + /* Prepare CB-related port information */ + PORTS cb_port_direction = OUT_PORT; + /* The cb port direction should be opposite to the sb port !!! */ + if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + cb_port_direction = IN_PORT; + } else { + VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + } + vtr::Point cb_port_coord(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); + std::string cb_port_name = generate_routing_track_port_name(cb_type, + cb_port_coord, itrack, + cb_port_direction); + ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id)); + BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id); + + /* Source and sink port should match in size */ + VTR_ASSERT(cb_port.get_width() == sb_port.get_width()); + + /* Create a net for each pin */ + for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(top_module); + /* Configure the net source and sink: + * If sb port is an output (source), cb port is an input (sink) + * If sb port is an input (sink), cb port is an output (source) + */ + if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); + module_manager.add_module_net_source(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); + } else { + VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + module_manager.add_module_net_source(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); + module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); + } + } + } + } +} + +/******************************************************************** + * Add module nets to connect the grid ports/pins to Connection Blocks + * and Switch Blocks + * To make it easy, this function will iterate over all the General + * Switch Blocks (GSBs), through which we can obtain the coordinates + * of all the grids, connection blocks and switch blocks that are + * supposed to be connected tightly. + * + * As such, we have completed all the connection for each grid. + * There is no need to iterate over the grids + * + * +-------------------------+ +---------------------------------+ + * | | | Y-direction CB | + * | Grid[x][y+1] | | [x][y + 1] | + * | | +---------------------------------+ + * +-------------------------+ + * TOP SIDE + * +-------------+ +---------------------------------+ + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | X-direction | | | + * | CB | LEFT SIDE | Switch Block | RIGHT SIDE + * | [x][y] | | [x][y] | + * | | | | + * | | | CHAN_NODES CHAN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * +-------------+ +---------------------------------+ + * BOTTOM SIDE + *******************************************************************/ +static +void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, + const ModuleId& top_module, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector>& grid_instance_ids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& sb_instance_ids, + const std::map>>& cb_instance_ids, + const bool& compact_routing_hierarchy) { + DeviceCoordinator gsb_range = L_device_rr_gsb.get_gsb_range(); + for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { + vtr::Point gsb_coordinate(ix, iy); + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + /* Connect the grid pins of the GSB to adjacent grids */ + add_top_module_nets_connect_grids_and_sb(module_manager, top_module, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, rr_gsb, sb_instance_ids, + compact_routing_hierarchy); + + add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), + compact_routing_hierarchy); + + add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), + compact_routing_hierarchy); + + add_top_module_nets_connect_sb_and_cb(module_manager, top_module, + L_device_rr_gsb, rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy); + + } + } +} + +/******************************************************************** + * Print the top-level module for the FPGA fabric in Verilog format + * This function will + * 1. name the top-level module + * 2. include dependent netlists + * - User defined netlists + * - Auto-generated netlists + * 3. Add the submodules to the top-level graph + * 4. Add module nets to connect datapath ports + * 5. Add module nets/submodules to connect configuration ports + *******************************************************************/ +void build_top_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector& clb2clb_directs, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const bool& compact_routing_hierarchy) { + /* Create a module as the top-level fabric, and add it to the module manager */ + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.add_module(top_module_name); + + std::map>> cb_instance_ids; + + /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ + /* Add all the grids across the fabric */ + std::vector> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, device_size, grids); + /* Add all the SBs across the fabric */ + std::vector> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); + /* Add all the CBX and CBYs across the fabric */ + cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); + cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); + + /* Add module nets to connect the sub modules */ + add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy); + /* Add inter-CLB direct connections */ + add_top_module_nets_clb2clb_direct_connections(module_manager, top_module, circuit_lib, + device_size, grids, grid_instance_ids, + clb2clb_directs); + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, top_module); + + /* Add GPIO ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + add_module_gpio_ports_from_child_modules(module_manager, top_module); + + /* Add shared SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, top_module); + if (0 < module_num_shared_config_bits) { + add_reserved_sram_ports_to_module_manager(module_manager, top_module, module_num_shared_config_bits); + } + + /* Add SRAM ports from the sub-modules under this Verilog module + * This is a much easier job after adding sub modules (instances), + * we just need to find all the I/O ports from the child modules and build a list of it + */ + size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type); + if (0 < module_num_config_bits) { + add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); + } + + /* Vectors to record all the memory modules have been added + * They are used to add module nets of configuration bus + */ + std::vector memory_modules; + std::vector memory_instances; + + /* Organize the list of memory modules and instances */ + organize_top_module_memory_modules(module_manager, + circuit_lib, sram_orgz_type, sram_model, + device_size, grids, grid_instance_ids, + L_device_rr_gsb, sb_instance_ids, cb_instance_ids, + compact_routing_hierarchy, + memory_modules, memory_instances); + + /* Add module nets to connect memory cells inside + * This is a one-shot addition that covers all the memory modules in this pb module! + */ + if (false == memory_modules.empty()) { + add_top_module_nets_memory_config_bus(module_manager, top_module, + memory_modules, memory_instances, + sram_orgz_type, circuit_lib.design_tech_type(sram_model)); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h new file mode 100644 index 000000000..86d41bf09 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h @@ -0,0 +1,25 @@ +/******************************************************************** + * Header file for build_top_module.cpp + *******************************************************************/ +#ifndef BUILD_TOP_MODULE_H +#define BUILD_TOP_MODULE_H + +#include +#include "vtr_geometry.h" +#include "vpr_types.h" +#include "spice_types.h" +#include "rr_blocks.h" +#include "circuit_library.h" +#include "module_manager.h" + +void build_top_module(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector& clb2clb_directs, + const e_sram_orgz& sram_orgz_type, + const CircuitModelId& sram_model, + const bool& compact_routing_hierarchy); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp index 8331edad5..442e8953d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp @@ -22,8 +22,8 @@ static void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, - t_sram_orgz_info* cur_sram_orgz_info, const std::vector>& cb_instance_ids, const DeviceRRGSB& L_device_rr_gsb, const RRGSB& rr_gsb, @@ -54,7 +54,7 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, */ if (0 < find_module_num_config_bits(module_manager, cb_module, circuit_lib, sram_model, - cur_sram_orgz_info->type)) { + sram_orgz_type)) { memory_modules.push_back(cb_module); memory_instances.push_back(cb_instance_ids[cb_coord.x()][cb_coord.y()]); } @@ -69,8 +69,8 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, static void organize_top_module_tile_memory_modules(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, - t_sram_orgz_info* cur_sram_orgz_info, const std::vector>& grids, const std::vector>& grid_instance_ids, const DeviceRRGSB& L_device_rr_gsb, @@ -109,21 +109,21 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager */ if (0 < find_module_num_config_bits(module_manager, sb_module, circuit_lib, sram_model, - cur_sram_orgz_info->type)) { + sram_orgz_type)) { memory_modules.push_back(sb_module); memory_instances.push_back(sb_instance_ids[sb_coord.x()][sb_coord.y()]); } /* Try to find and add CBX and CBY */ organize_top_module_tile_cb_modules(module_manager, circuit_lib, - sram_model, cur_sram_orgz_info, + sram_orgz_type, sram_model, cb_instance_ids.at(CHANX), L_device_rr_gsb, rr_gsb, CHANX, compact_routing_hierarchy, memory_modules, memory_instances); organize_top_module_tile_cb_modules(module_manager, circuit_lib, - sram_model, cur_sram_orgz_info, + sram_orgz_type, sram_model, cb_instance_ids.at(CHANY), L_device_rr_gsb, rr_gsb, CHANY, compact_routing_hierarchy, @@ -142,7 +142,7 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager */ if (0 < find_module_num_config_bits(module_manager, grid_module, circuit_lib, sram_model, - cur_sram_orgz_info->type)) { + sram_orgz_type)) { memory_modules.push_back(grid_module); memory_instances.push_back(grid_instance_ids[tile_coord.x()][tile_coord.y()]); } @@ -209,8 +209,8 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager *******************************************************************/ void organize_top_module_memory_modules(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, - t_sram_orgz_info* cur_sram_orgz_info, const vtr::Point& device_size, const std::vector>& grids, const std::vector>& grid_instance_ids, @@ -255,7 +255,7 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, for (const vtr::Point& io_coord : io_coords[io_side]) { /* Identify the GSB that surrounds the grid */ organize_top_module_tile_memory_modules(module_manager, - circuit_lib, sram_model, cur_sram_orgz_info, + circuit_lib, sram_orgz_type, sram_model, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, @@ -286,7 +286,7 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, for (const vtr::Point& core_coord : core_coords) { organize_top_module_tile_memory_modules(module_manager, - circuit_lib, sram_model, cur_sram_orgz_info, + circuit_lib, sram_orgz_type, sram_model, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h index 66afa2a51..42312c8bc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h @@ -10,8 +10,8 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, + const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, - t_sram_orgz_info* cur_sram_orgz_info, const vtr::Point& device_size, const std::vector>& grids, const std::vector>& grid_instance_ids, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index c4f2805a5..0526e6a90 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -326,29 +326,9 @@ void vpr_fpga_verilog(ModuleManager& module_manager, /* TODO: This is the old function, which will be deprecated when refactoring is done */ dump_verilog_config_peripherals(sram_verilog_orgz_info, src_dir_path, submodule_dir_path); - /* Print top-level Verilog module */ - vtr::Point device_size(nx + 2, ny + 2); - std::vector> grids; - /* Organize a vector (matrix) of grids to feed the top-level module generation */ - grids.resize(device_size.x()); - for (size_t ix = 0; ix < device_size.x(); ++ix) { - grids[ix].resize(device_size.y()); - for (size_t iy = 0; iy < device_size.y(); ++iy) { - grids[ix][iy] = grid[ix][iy]; - } - } - /* Organize a vector (matrix) of clb2clb directs to feed the top-level module generation */ - std::vector clb2clb_directs; - for (int i = 0; i < num_clb2clb_directs; ++i) { - clb2clb_directs.push_back(clb2clb_direct[i]); - } - print_verilog_top_module(module_manager, Arch.spice->circuit_lib, - device_size, grids, device_rr_gsb, - clb2clb_directs, - sram_verilog_orgz_info, + print_verilog_top_module(module_manager, std::string(vpr_setup.FileNameOpts.ArchFile), std::string(src_dir_path), - TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* TODO: This is the old function, which will be deprecated when refactoring is done */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index 9939c406f..e2c183387 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -9,789 +9,15 @@ #include "vtr_assert.h" #include "vpr_types.h" -#include "globals.h" -#include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "module_manager_utils.h" -#include "build_top_module_memory.h" -#include "build_top_module_directs.h" +#include "fpga_x2p_naming.h" #include "verilog_global.h" -#include "build_module_graph_utils.h" #include "verilog_writer_utils.h" #include "verilog_module_writer.h" #include "verilog_top_module.h" -/******************************************************************** - * Generate the name for a grid block, by considering - * 1. if it locates on the border with given device size - * 2. its type - * - * This function is mainly used in the top-level module generation - *******************************************************************/ -static -std::string generate_grid_block_module_name_in_top_module(const std::string& prefix, - const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point& grid_coordinate) { - /* Determine if the grid locates at the border */ - e_side border_side = find_grid_border_side(device_size, grid_coordinate); - - return generate_grid_block_module_name(prefix, std::string(grids[grid_coordinate.x()][grid_coordinate.y()].type->name), - IO_TYPE == grids[grid_coordinate.x()][grid_coordinate.y()].type, border_side); -} - -/******************************************************************** - * Find the cb_type of a GSB in the top-level module - * depending on the side of SB - * TOP/BOTTOM side: CHANY - * RIGHT/LEFT side: CHANX - *******************************************************************/ -static -t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); - - if ((TOP == sb_side) || (BOTTOM == sb_side)) { - return CHANY; - } - - VTR_ASSERT((RIGHT == sb_side) || (LEFT == sb_side)); - return CHANX; -} - -/******************************************************************** - * Find the GSB coordinate for a CB in the top-level module - * depending on the side of a SB - * TODO: use vtr::Point to replace DeviceCoordinator - *******************************************************************/ -static -DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb, - const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); - - DeviceCoordinator gsb_coordinate; - - if ((TOP == sb_side) || (LEFT == sb_side)) { - gsb_coordinate.set_x(rr_gsb.get_x()); - gsb_coordinate.set_y(rr_gsb.get_y()); - return gsb_coordinate; - } - - VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); - DeviceCoordinator side_coord = rr_gsb.get_side_block_coordinator(sb_side); - - gsb_coordinate.set_x(side_coord.get_x()); - gsb_coordinate.set_y(side_coord.get_y()); - - return gsb_coordinate; -} - -/******************************************************************** - * Add a instance of a grid module to the top module - *******************************************************************/ -static -size_t add_top_module_grid_instance(ModuleManager& module_manager, - const ModuleId& top_module, - t_type_ptr grid_type, - const e_side& border_side) { - /* Find the module name for this type of grid */ - std::string grid_module_name_prefix(grid_verilog_file_name_prefix); - std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); - ModuleId grid_module = module_manager.find_module(grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - /* Record the instance id */ - size_t grid_instance = module_manager.num_instance(top_module, grid_module); - /* Add the module to top_module */ - module_manager.add_child_module(top_module, grid_module); - - return grid_instance; -} - -/******************************************************************** - * Add all the grids as sub-modules across the fabric - * The grid modules are created for each unique type of grid (based - * on the type in data structure data_structure - * Here, we will iterate over the full fabric (coordinates) - * and instanciate the grid modules - * - * Return an 2-D array of instance ids of the grid modules that - * have been added - * - * This function assumes an island-style floorplanning for FPGA fabric - * - * - * +-----------------------------------+ - * | I/O grids | - * | TOP side | - * +-----------------------------------+ - * - * +-----------+ +-----------------------------------+ +------------+ - * | | | | | | - * | I/O grids | | Core grids | | I/O grids | - * | LEFT side | | (CLB, Heterogeneous blocks, etc.) | | RIGHT side | - * | | | | | | - * +-----------+ +-----------------------------------+ +------------+ - * - * +-----------------------------------+ - * | I/O grids | - * | BOTTOM side | - * +-----------------------------------+ - * - *******************************************************************/ -static -std::vector> add_top_module_grid_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids) { - /* Reserve an array for the instance ids */ - std::vector> grid_instance_ids; - grid_instance_ids.resize(grids.size()); - for (size_t x = 0; x < grids.size(); ++x) { - /* Deposite an invalid value */ - grid_instance_ids[x].resize(grids[x].size(), size_t(-1)); - } - - /* Instanciate core grids */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grids[ix][iy].type) { - continue; - } - /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[ix][iy].offset) { - continue; - } - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE != grids[ix][iy].type); - /* Add a grid module to top_module*/ - grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module, - grids[ix][iy].type, - NUM_SIDES); - } - } - - /* Instanciate I/O grids */ - /* Create the coordinate range for each side of FPGA fabric */ - std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; - std::map>> io_coordinates; - - /* TOP side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); - } - - /* RIGHT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); - } - - /* BOTTOM side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); - } - - /* LEFT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[LEFT].push_back(vtr::Point(0, iy)); - } - - /* Add instances of I/O grids to top_module */ - for (const e_side& io_side : io_sides) { - for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type) { - continue; - } - /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[io_coordinate.x()][io_coordinate.y()].offset) { - continue; - } - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); - /* Add a grid module to top_module*/ - grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side); - } - } - - return grid_instance_ids; -} - -/******************************************************************** - * Add switch blocks across the FPGA fabric to the top-level module - * Return an 2-D array of instance ids of the switch blocks that - * have been added - *******************************************************************/ -static -std::vector> add_top_module_switch_block_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy) { - /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - - /* Reserve an array for the instance ids */ - std::vector> sb_instance_ids; - sb_instance_ids.resize(sb_range.get_x()); - for (size_t x = 0; x < sb_range.get_x(); ++x) { - /* Deposite an invalid value */ - sb_instance_ids[x].resize(sb_range.get_y(), size_t(-1)); - } - - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_x()); - if (true == compact_routing_hierarchy) { - DeviceCoordinator sb_coord(ix, iy); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - sb_coordinate.set_x(unique_mirror.get_sb_x()); - sb_coordinate.set_y(unique_mirror.get_sb_y()); - } - std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - /* Record the instance id */ - sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module); - /* Add the module to top_module */ - module_manager.add_child_module(top_module, sb_module); - } - } - - return sb_instance_ids; -} - -/******************************************************************** - * Add switch blocks across the FPGA fabric to the top-level module - *******************************************************************/ -static -std::vector> add_top_module_connection_block_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - /* Reserve an array for the instance ids */ - std::vector> cb_instance_ids; - cb_instance_ids.resize(cb_range.get_x()); - for (size_t x = 0; x < cb_range.get_x(); ++x) { - /* Deposite an invalid value */ - cb_instance_ids[x].resize(cb_range.get_y(), size_t(-1)); - } - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - const DeviceCoordinator cb_coordinator = rr_gsb.get_cb_coordinator(cb_type); - if ( (TRUE != is_cb_exist(cb_type, cb_coordinator.get_x(), cb_coordinator.get_y())) - || (true != rr_gsb.is_cb_exist(cb_type))) { - continue; - } - /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator cb_coord(ix, iy); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); - cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); - } - std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); - ModuleId cb_module = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - /* Record the instance id */ - cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module); - /* Add the module to top_module */ - module_manager.add_child_module(top_module, cb_module); - } - } - - return cb_instance_ids; -} - -/******************************************************************** - * Add module nets to connect a GSB to adjacent grid ports/pins - * as well as connection blocks - * This function will create nets for the following types of connections - * between grid output pins of Switch block and adjacent grids - * In this case, the net source is the grid pin, while the net sink - * is the switch block pin - * - * +------------+ +------------+ - * | | | | - * | Grid | | Grid | - * | [x][y+1] | | [x+1][y+1] | - * | | | | - * +------------+ +------------+ - * | | - * | +------------+ | - * +------>| |<-----+ - * | Switch | - * | Block | - * +------>| [x][y] |<-----+ - * | +------------+ | - * | | - * | | - * +------------+ +------------+ - * | | | | - * | Grid | | Grid | - * | [x][y] | | [x+1][y] | - * | | | | - * +------------+ +------------+ - * - *******************************************************************/ -static -void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const std::vector>& sb_instance_ids, - const bool& compact_routing_hierarchy) { - - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); - module_gsb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); - vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); - - /* Collect sink-related information */ - std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate); - ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); - size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; - - /* Connect grid output pins (OPIN) to switch block grid pins */ - for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - /* Collect source-related information */ - /* Generate the grid module name by considering if it locates on the border */ - vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); - std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); - ModuleId src_grid_module = module_manager.find_module(src_grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); - size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; - size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num; - size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index); - std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false); - ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); - BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); - - /* Collect sink-related information */ - vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string sink_sb_port_name = generate_grid_side_port_name(grids, sink_sb_port_coord, - module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - src_grid_pin_index); - ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); - BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source */ - module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]); - } - } - } -} - -/******************************************************************** - * This function will create nets for the connections - * between grid input pins and connection blocks - * In this case, the net source is the connection block pin, - * while the net sink is the grid input - * - * +------------+ +------------------+ +------------+ - * | | | | | | - * | Grid |<-----| Connection Block |----->| Grid | - * | [x][y+1] | | Y-direction | | [x+1][y+1] | - * | | | [x][y+1] | | | - * +------------+ +------------------+ +------------+ - * ^ - * | - * +------------+ +------------------+ - * | Connection | | | - * | Block | | Switch Block | - * | X-direction| | [x][y] | - * | [x][y] | | | - * +------------+ +------------------+ - * | - * v - * +------------+ - * | | - * | Grid | - * | [x][y] | - * | | - * +------------+ - * - * - * Relationship between source connection block and its unique module - * Take an example of a CBY - * - * grid_pin name should follow unique module of Grid[x][y+1] - * cb_pin name should follow unique module of CBY[x][y+1] - * - * However, instace id should follow the origin Grid and Connection block - * - * - * +------------+ +------------------+ - * | | | | - * | Grid |<------------| Connection Block | - * | [x][y+1] | | Y-direction | - * | | | [x][y+1] | - * +------------+ +------------------+ - * ^ - * || unique mirror - * +------------+ +------------------+ - * | | | | - * | Grid |<------------| Connection Block | - * | [i][j+1] | | Y-direction | - * | | | [i][j+1] | - * +------------+ +------------------+ - * - *******************************************************************/ -static -void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector>& cb_instance_ids, - const bool& compact_routing_hierarchy) { - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* Skip those Connection blocks that do not exist */ - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { - return; - } - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, gsb_coord); - module_gsb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); - vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); - - /* Collect source-related information */ - std::string src_cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); - ModuleId src_cb_module = module_manager.find_module(src_cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_cb_module)); - /* Instance id should follow the instance cb coordinate */ - size_t src_cb_instance = cb_instance_ids[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; - - /* Iterate over the output pins of the Connection Block */ - std::vector cb_ipin_sides = module_cb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < module_cb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - /* Collect source-related information */ - t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode); - vtr::Point cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow); - std::string src_cb_port_name = generate_grid_side_port_name(grids, cb_src_port_coord, - module_cb.get_ipin_node_grid_side(cb_ipin_side, inode), - module_ipin_node->ptc_num); - ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id)); - BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); - - /* Collect sink-related information */ - /* Note that we use the instance cb pin here!!! - * because it has the correct coordinator for the grid!!! - */ - t_rr_node* instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point grid_coordinate(instance_ipin_node->xlow, instance_ipin_node->ylow); - std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); - ModuleId sink_grid_module = module_manager.find_module(sink_grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); - size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; - size_t sink_grid_pin_index = instance_ipin_node->ptc_num; - size_t sink_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, sink_grid_pin_index); - std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_height, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), sink_grid_pin_index, false); - ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id)); - BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source */ - module_manager.add_module_net_source(top_module, net, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(top_module, net, sink_grid_module, sink_grid_instance, sink_grid_port_id, sink_grid_port.pins()[pin_id]); - } - } - } -} - -/******************************************************************** - * This function will create nets for the connections - * between connection block and switch block pins - * Two cases should be considered: - * a. The switch block pin denotes an input of a routing track - * The net source is an output of a routing track of connection block - * while the net sink is an input of a routing track of switch block - * b. The switch block pin denotes an output of a routing track - * The net source is an output of routing track of switch block - * while the net sink is an input of a routing track of connection block - * - * +------------+ +------------------+ +------------+ - * | | | | | | - * | Grid | | Connection Block | | Grid | - * | [x][y+1] | | Y-direction | | [x+1][y+1] | - * | | | [x][y+1] | | | - * +------------+ +------------------+ +------------+ - * | ^ - * v | - * +------------+ +------------------+ +------------+ - * | Connection |----->| |----->| Connection | - * | Block | | Switch Block | | Block | - * | X-direction|<-----| [x][y] |<-----| X-direction| - * | [x][y] | | | | [x+1][y] | - * +------------+ +------------------+ +------------+ - * | ^ - * v | - * +------------+ +------------------+ +------------+ - * | | | | | | - * | Grid | | Connection Block | | Grid | - * | [x][y] | | Y-direction | | [x][y+1] | - * | | | [x][y] | | | - * +------------+ +------------------+ +------------+ - * - * Here, to achieve the purpose, we can simply iterate over the - * four sides of switch block and make connections to adjancent - * connection blocks - * - *******************************************************************/ -static -void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy) { - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - DeviceCoordinator module_gsb_sb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); - module_gsb_sb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_sb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_sb_coordinate); - vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); - std::string sb_module_name = generate_switch_block_module_name(module_sb_coordinate); - ModuleId sb_module_id = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module_id)); - size_t sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; - - /* Connect grid output pins (OPIN) to switch block grid pins */ - for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { - Side side_manager(side); - /* Iterate over the routing tracks on this side */ - DeviceCoordinator port_coordinator = module_sb.get_side_block_coordinator(side_manager.get_side()); - /* Early skip: if there is no routing tracks at this side */ - if (0 == module_sb.get_chan_width(side_manager.get_side())) { - continue; - } - /* Find the Connection Block module */ - /* We find the original connection block and then spot its unique mirror! - * Do NOT use module_sb here!!! - */ - t_rr_type cb_type = find_top_module_cb_type_by_sb_side(side_manager.get_side()); - DeviceCoordinator instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); - DeviceCoordinator module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); - - /* Skip those Connection blocks that do not exist */ - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { - continue; - } - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, module_gsb_cb_coordinate); - module_gsb_cb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_cb_coordinate.set_y(unique_mirror.get_y()); - } - - const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); - vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); - std::string cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); - ModuleId cb_module_id = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module_id)); - const RRGSB& instance_cb = L_device_rr_gsb.get_gsb(instance_gsb_cb_coordinate); - vtr::Point instance_cb_coordinate(instance_cb.get_cb_x(cb_type), instance_cb.get_cb_y(cb_type)); - size_t cb_instance = cb_instance_ids.at(cb_type)[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; - - for (size_t itrack = 0; itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) { - vtr::Point sb_port_coord(port_coordinator.get_x(), port_coordinator.get_y()); - std::string sb_port_name = generate_routing_track_port_name(module_sb.get_chan_node(side_manager.get_side(), itrack)->type, - sb_port_coord, itrack, - module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); - /* Prepare SB-related port information */ - ModulePortId sb_port_id = module_manager.find_module_port(sb_module_id, sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module_id, sb_port_id)); - BasicPort sb_port = module_manager.module_port(sb_module_id, sb_port_id); - - /* Prepare CB-related port information */ - PORTS cb_port_direction = OUT_PORT; - /* The cb port direction should be opposite to the sb port !!! */ - if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - cb_port_direction = IN_PORT; - } else { - VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); - } - vtr::Point cb_port_coord(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); - std::string cb_port_name = generate_routing_track_port_name(cb_type, - cb_port_coord, itrack, - cb_port_direction); - ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id)); - BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(cb_port.get_width() == sb_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source and sink: - * If sb port is an output (source), cb port is an input (sink) - * If sb port is an input (sink), cb port is an output (source) - */ - if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); - module_manager.add_module_net_source(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); - } else { - VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); - module_manager.add_module_net_source(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); - module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); - } - } - } - } -} - -/******************************************************************** - * Add module nets to connect the grid ports/pins to Connection Blocks - * and Switch Blocks - * To make it easy, this function will iterate over all the General - * Switch Blocks (GSBs), through which we can obtain the coordinates - * of all the grids, connection blocks and switch blocks that are - * supposed to be connected tightly. - * - * As such, we have completed all the connection for each grid. - * There is no need to iterate over the grids - * - * +-------------------------+ +---------------------------------+ - * | | | Y-direction CB | - * | Grid[x][y+1] | | [x][y + 1] | - * | | +---------------------------------+ - * +-------------------------+ - * TOP SIDE - * +-------------+ +---------------------------------+ - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | X-direction | | | - * | CB | LEFT SIDE | Switch Block | RIGHT SIDE - * | [x][y] | | [x][y] | - * | | | | - * | | | CHAN_NODES CHAN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * +-------------+ +---------------------------------+ - * BOTTOM SIDE - *******************************************************************/ -static -void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy) { - DeviceCoordinator gsb_range = L_device_rr_gsb.get_gsb_range(); - for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { - vtr::Point gsb_coordinate(ix, iy); - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - /* Connect the grid pins of the GSB to adjacent grids */ - add_top_module_nets_connect_grids_and_sb(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, sb_instance_ids, - compact_routing_hierarchy); - - add_top_module_nets_connect_grids_and_cb(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), - compact_routing_hierarchy); - - add_top_module_nets_connect_grids_and_cb(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), - compact_routing_hierarchy); - - add_top_module_nets_connect_sb_and_cb(module_manager, top_module, - L_device_rr_gsb, rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy); - - } - } -} - /******************************************************************** * Print the top-level module for the FPGA fabric in Verilog format * This function will @@ -804,99 +30,13 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, * 5. Add module nets/submodules to connect configuration ports *******************************************************************/ void print_verilog_top_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& clb2clb_directs, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, - const bool& compact_routing_hierarchy, const bool& use_explicit_mapping) { /* Create a module as the top-level fabric, and add it to the module manager */ std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.add_module(top_module_name); - - std::map>> cb_instance_ids; - - /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ - /* Add all the grids across the fabric */ - std::vector> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, device_size, grids); - /* Add all the SBs across the fabric */ - std::vector> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); - /* Add all the CBX and CBYs across the fabric */ - cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); - cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); - - /* Add module nets to connect the sub modules */ - add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy); - /* Add inter-CLB direct connections */ - add_top_module_nets_clb2clb_direct_connections(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - clb2clb_directs); - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, top_module); - - /* Add GPIO ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - add_module_gpio_ports_from_child_modules(module_manager, top_module); - - /* Add shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, top_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, top_module, module_num_shared_config_bits); - } - - /* TODO: this should be added to the cur_sram_orgz_info !!! */ - t_spice_model* mem_model = NULL; - get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model); - CircuitModelId sram_model = circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Add SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, cur_sram_orgz_info->type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits); - } - - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - - /* Organize the list of memory modules and instances */ - organize_top_module_memory_modules(module_manager, - circuit_lib, sram_model, cur_sram_orgz_info, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy, - memory_modules, memory_instances); - - /* Add module nets to connect memory cells inside - * This is a one-shot addition that covers all the memory modules in this pb module! - */ - if (false == memory_modules.empty()) { - add_top_module_nets_memory_config_bus(module_manager, top_module, - memory_modules, memory_instances, - cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model)); - } + ModuleId top_module = module_manager.find_module(top_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); /* Start printing out Verilog netlists */ /* Create the file name for Verilog netlist */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h index 6516a9780..aa26e011a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h @@ -5,24 +5,11 @@ #define VERILOG_TOP_MODULE_H #include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "spice_types.h" -#include "rr_blocks.h" -#include "circuit_library.h" #include "module_manager.h" void print_verilog_top_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& clb2clb_directs, - t_sram_orgz_info* cur_sram_orgz_info, const std::string& arch_name, const std::string& verilog_dir, - const bool& compact_routing_hierarchy, const bool& use_explicit_mapping); - #endif From 12162a02bcc06c2c530df41e545be9c49f8172a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Oct 2019 14:20:04 -0600 Subject: [PATCH 324/482] critical bug fixing for compact routing hierarchy and top module generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 25 +++--- .../fpga_x2p/base/fpga_x2p_unique_routing.c | 84 ++++++++++--------- .../fpga_x2p/base/fpga_x2p_unique_routing.h | 8 +- .../module_builder/build_top_module.cpp | 2 +- 4 files changed, 62 insertions(+), 57 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index d88a27658..a94dd1789 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -1427,20 +1427,21 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, /* Idenify mirror and rotatable Switch blocks and Connection blocks */ identify_mirror_switch_blocks(); identify_mirror_connection_blocks(); - - /* Assign Gobal variable: build the Routing Resource Channels */ - device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data); - device_rr_gsb = build_device_rr_gsb(vpr_setup.FPGA_SPICE_Opts.output_sb_xml, - vpr_setup.FPGA_SPICE_Opts.sb_xml_dir, - num_rr_nodes, rr_node, rr_node_indices, - Arch->num_segments, rr_indexed_data); - - /* Rotatable will be done in the next step - identify_rotatable_switch_blocks(); - identify_rotatable_connection_blocks(); - */ } + /* Assign Gobal variable: build the Routing Resource Channels */ + device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data); + device_rr_gsb = build_device_rr_gsb(TRUE == vpr_setup.FPGA_SPICE_Opts.output_sb_xml, + TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, + vpr_setup.FPGA_SPICE_Opts.sb_xml_dir, + num_rr_nodes, rr_node, rr_node_indices, + Arch->num_segments, rr_indexed_data); + + /* Rotatable will be done in the next step + identify_rotatable_switch_blocks(); + identify_rotatable_connection_blocks(); + */ + /* Not should be done when read_act_file is disabled */ if (FALSE == vpr_setup.FPGA_SPICE_Opts.read_act_file) { return; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index a2ced20b1..4385cd5f7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1318,9 +1318,11 @@ void sort_rr_gsb_drive_rr_nodes(const RRGSB& rr_gsb) { * Each switch block in the FPGA fabric will be an instance of these modules. * We maintain a map from each instance to each module */ -DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, +DeviceRRGSB build_device_rr_gsb(const bool& output_sb_xml, + const bool& compact_routing_hierarchy, + char* sb_xml_dir, + const int& LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, const int& num_segments, t_rr_indexed_data* LL_rr_indexed_data) { /* Timer */ clock_t t_start; @@ -1382,9 +1384,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n", run_time_sec_profiling); vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec); - - - if (TRUE == output_sb_xml) { + if (true == output_sb_xml) { create_dir_path(sb_xml_dir); write_device_rr_gsb_to_xml(sb_xml_dir, LL_device_rr_gsb); @@ -1397,42 +1397,44 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, /* Build a list of unique modules for each Switch Block */ /* Build a list of unique modules for each side of each Switch Block */ - LL_device_rr_gsb.build_unique_module(); + if (true == compact_routing_hierarchy) { + LL_device_rr_gsb.build_unique_module(); - vpr_printf(TIO_MESSAGE_INFO, - "Detect %lu routing segments used by switch blocks.\n", - LL_device_rr_gsb.get_num_segments()); + vpr_printf(TIO_MESSAGE_INFO, + "Detect %lu routing segments used by switch blocks.\n", + LL_device_rr_gsb.get_num_segments()); + + /* Report number of unique CB Modules */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d unique connection blocks from %d X-channel connection blocks.\n", + LL_device_rr_gsb.get_num_cb_unique_module(CHANX), (nx + 0) * (ny + 1) ); + + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d unique connection blocks from %d Y-channel connection blocks.\n", + LL_device_rr_gsb.get_num_cb_unique_module(CHANY), (nx + 1) * (ny + 0) ); + + + /* Report number of unique SB modules */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d unique switch blocks from %d switch blocks.\n", + LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); + + /* Report number of unique GSB modules */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d unique GSBs from %d GSBs.\n", + LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); - /* Report number of unique CB Modules */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique connection blocks from %d X-channel connection blocks.\n", - LL_device_rr_gsb.get_num_cb_unique_module(CHANX), (nx + 0) * (ny + 1) ); - - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique connection blocks from %d Y-channel connection blocks.\n", - LL_device_rr_gsb.get_num_cb_unique_module(CHANY), (nx + 1) * (ny + 0) ); - - - /* Report number of unique SB modules */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique switch blocks from %d switch blocks.\n", - LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); - - /* Report number of unique GSB modules */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique GSBs from %d GSBs.\n", - LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); - - /* Report number of unique mirrors */ - for (size_t side = 0; side < LL_device_rr_gsb.get_max_num_sides(); ++side) { - Side side_manager(side); - /* get segment ids */ - for (size_t iseg = 0; iseg < LL_device_rr_gsb.get_num_segments(); ++iseg) { - vpr_printf(TIO_MESSAGE_INFO, - "For side %s, segment id %lu: Detect %d independent switch blocks from %d switch blocks.\n", - side_manager.c_str(), LL_device_rr_gsb.get_segment_id(iseg), - LL_device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg), - (nx + 1) * (ny + 1) ); + /* Report number of unique mirrors */ + for (size_t side = 0; side < LL_device_rr_gsb.get_max_num_sides(); ++side) { + Side side_manager(side); + /* get segment ids */ + for (size_t iseg = 0; iseg < LL_device_rr_gsb.get_num_segments(); ++iseg) { + vpr_printf(TIO_MESSAGE_INFO, + "For side %s, segment id %lu: Detect %d independent switch blocks from %d switch blocks.\n", + side_manager.c_str(), LL_device_rr_gsb.get_segment_id(iseg), + LL_device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg), + (nx + 1) * (ny + 1) ); + } } } @@ -1440,7 +1442,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, t_end = clock(); run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n\n", run_time_sec); + vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniquifying took %g seconds\n\n", run_time_sec); return LL_device_rr_gsb; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h index e0df9c185..ce8b3d999 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h @@ -14,9 +14,11 @@ DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, * Each switch block in the FPGA fabric will be an instance of these modules. * We maintain a map from each instance to each module */ -DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, +DeviceRRGSB build_device_rr_gsb(const bool& output_sb_xml, + const bool& compact_routing_hierarchy, + char* sb_xml_dir, + const int& LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, const int& num_segments, t_rr_indexed_data* LL_rr_indexed_data); /* Rotatable will be done in the next step diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index e3e6d13c4..dc004ff02 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -241,7 +241,7 @@ std::vector> add_top_module_switch_block_instances(ModuleMan for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_x()); + vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); if (true == compact_routing_hierarchy) { DeviceCoordinator sb_coord(ix, iy); const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); From a18f1305cde4aec9aed2d813bd0ab2baba18292d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Oct 2019 15:44:13 -0600 Subject: [PATCH 325/482] add configurable child list to module manager --- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 36 +++++++++++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 15 +++++ .../fpga_x2p/base/module_manager_utils.cpp | 30 +++------ .../SRC/fpga_x2p/base/module_manager_utils.h | 4 -- .../module_builder/build_grid_modules.cpp | 20 ++---- .../module_builder/build_memory_modules.cpp | 29 ++++----- .../module_builder/build_routing_modules.cpp | 52 ++++----------- .../module_builder/build_top_module.cpp | 14 +---- .../build_top_module_memory.cpp | 63 +++++++------------ .../module_builder/build_top_module_memory.h | 9 +-- 10 files changed, 117 insertions(+), 155 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index 3eab7112a..bdd636071 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -63,6 +63,22 @@ std::vector ModuleManager::child_module_instances(const ModuleId& parent return instance_range; } +/* Find all the configurable child modules under a parent module */ +std::vector ModuleManager::configurable_children(const ModuleId& parent_module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(parent_module)); + + return configurable_children_[parent_module]; +} + +/* Find all the instances of configurable child modules under a parent module */ +std::vector ModuleManager::configurable_child_instances(const ModuleId& parent_module) const { + /* Validate the module_id */ + VTR_ASSERT(valid_module_id(parent_module)); + + return configurable_child_instances_[parent_module]; +} + /* Find the source ids of modules */ ModuleManager::module_net_src_range ModuleManager::module_net_sources(const ModuleId& module, const ModuleNetId& net) const { /* Validate the module_id */ @@ -381,6 +397,8 @@ ModuleId ModuleManager::add_module(const std::string& name) { children_.emplace_back(); num_child_instances_.emplace_back(); child_instance_names_.emplace_back(); + configurable_children_.emplace_back(); + configurable_child_instances_.emplace_back(); port_ids_.emplace_back(); ports_.emplace_back(); @@ -530,6 +548,24 @@ void ModuleManager::set_child_instance_name(const ModuleId& parent_module, child_instance_names_[parent_module][child_index][instance_id] = instance_name; } +/* Add a configurable child module to module + * Note: this function should be called after add_child_module! + * It will check if the child module does exist in the parent module + * And the instance id is in range or not + */ +void ModuleManager::add_configurable_child(const ModuleId& parent_module, + const ModuleId& child_module, + const size_t& child_instance) { + /* Validate the id of both parent and child modules */ + VTR_ASSERT ( valid_module_id(parent_module) ); + VTR_ASSERT ( valid_module_id(child_module) ); + /* Ensure that the instance id is in range */ + VTR_ASSERT ( child_instance < num_instance(parent_module, child_module)); + + configurable_children_[parent_module].push_back(child_module); + configurable_child_instances_[parent_module].push_back(child_instance); +} + /* Add a net to the connection graph of the module */ ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { /* Validate the module id */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 5001205ba..1efcd0d24 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -60,6 +60,10 @@ class ModuleManager { std::vector child_modules(const ModuleId& parent_module) const; /* Find all the instances under a parent module */ std::vector child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const; + /* Find all the configurable child modules under a parent module */ + std::vector configurable_children(const ModuleId& parent_module) const; + /* Find all the instances of configurable child modules under a parent module */ + std::vector configurable_child_instances(const ModuleId& parent_module) const; /* Find the source ids of modules */ module_net_src_range module_net_sources(const ModuleId& module, const ModuleNetId& net) const; /* Find the sink ids of modules */ @@ -135,6 +139,8 @@ class ModuleManager { void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); /* Set the instance name of a child module */ void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name); + /* Add a configurable child module to module */ + void add_configurable_child(const ModuleId& module, const ModuleId& child_module, const size_t& child_instance); /* Add a net to the connection graph of the module */ ModuleNetId create_module_net(const ModuleId& module); /* Set the name of net */ @@ -165,6 +171,15 @@ class ModuleManager { vtr::vector> num_child_instances_; /* Number of children instance in each child module */ vtr::vector>> child_instance_names_; /* Number of children instance in each child module */ + /* Configurable child modules are used to record the position of configurable modules in bitstream + * The sequence of children in the list denotes which one is configured first, etc. + * Note that the sequence can be totally different from the children_ list + * This is really dependent how the configuration protocol is organized + * which should be made by users/designers + */ + vtr::vector> configurable_children_; /* Child modules with configurable memory bits that this module contain */ + vtr::vector> configurable_child_instances_; /* Instances of child modules with configurable memory bits that this module contain */ + /* Port-level data */ vtr::vector> port_ids_; /* List of ports for each Module */ vtr::vector> ports_; /* List of ports for each Module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index ac5561032..43dcd7707 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -583,10 +583,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man *********************************************************************/ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type) { - for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) { + for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { ModuleId net_src_module_id; size_t net_src_instance_id; ModulePortId net_src_port_id; @@ -604,20 +602,20 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, /* Find the port name of next memory module */ std::string sink_port_name = generate_configuration_chain_head_name(); - net_sink_module_id = memory_modules[mem_index]; - net_sink_instance_id = memory_instances[mem_index]; + net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; + net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); } else { /* Find the port name of previous memory module */ std::string src_port_name = generate_configuration_chain_tail_name(); - net_src_module_id = memory_modules[mem_index - 1]; - net_src_instance_id = memory_instances[mem_index - 1]; + net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; + net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1]; net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ std::string sink_port_name = generate_configuration_chain_head_name(); - net_sink_module_id = memory_modules[mem_index]; - net_sink_instance_id = memory_instances[mem_index]; + net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; + net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); } @@ -645,8 +643,8 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, */ /* Find the port name of previous memory module */ std::string src_port_name = generate_configuration_chain_tail_name(); - ModuleId net_src_module_id = memory_modules.back(); - size_t net_src_instance_id = memory_instances.back(); + ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); + size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back(); ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ @@ -720,18 +718,13 @@ void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, static void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type) { - /* Ensure that the size of memory_model vector matches the memory_module vector */ - VTR_ASSERT(memory_modules.size() == memory_instances.size()); - switch (sram_orgz_type) { case SPICE_SRAM_STANDALONE: /* Nothing to do */ break; case SPICE_SRAM_SCAN_CHAIN: { - add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, memory_modules, memory_instances, sram_orgz_type); + add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type); break; } case SPICE_SRAM_MEMORY_BANK: @@ -802,14 +795,11 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, *******************************************************************/ void add_module_nets_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type, const e_spice_model_design_tech& mem_tech) { switch (mem_tech) { case SPICE_MODEL_DESIGN_CMOS: add_module_nets_cmos_memory_config_bus(module_manager, parent_module, - memory_modules, memory_instances, sram_orgz_type); break; case SPICE_MODEL_DESIGN_RRAM: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index d1ab892b4..5156e7af2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -71,14 +71,10 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type); void add_module_nets_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type, const e_spice_model_design_tech& mem_tech); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 68579a252..7a84fbac1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -359,15 +359,13 @@ void build_primitive_block_module(ModuleManager& module_manager, memory_module, memory_instance_id, circuit_lib, primitive_model); /* Record memory-related information */ - memory_modules.push_back(memory_module); - memory_instances.push_back(memory_instance_id); + module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id); } /* Add all the nets to connect configuration ports from memory module to primitive modules * This is a one-shot addition that covers all the memory modules in this primitive module! */ if (false == memory_modules.empty()) { add_module_nets_memory_config_bus(module_manager, primitive_module, - memory_modules, memory_instances, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } } @@ -908,8 +906,7 @@ void rec_build_physical_block_modules(ModuleManager& module_manager, if (0 < find_module_num_config_bits(module_manager, child_pb_module, circuit_lib, sram_model, sram_orgz_type)) { - memory_modules.push_back(child_pb_module); - memory_instances.push_back(child_instance_id); + module_manager.add_configurable_child(pb_module, child_pb_module, child_instance_id); } } } @@ -958,7 +955,6 @@ void rec_build_physical_block_modules(ModuleManager& module_manager, */ if (false == memory_modules.empty()) { add_module_nets_memory_config_bus(module_manager, pb_module, - memory_modules, memory_instances, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } } @@ -1001,12 +997,6 @@ void build_grid_module(ModuleManager& module_manager, ModuleId grid_module = module_manager.add_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - /* Generate the name of the Verilog module for this pb_type */ std::string pb_module_name_prefix(grid_verilog_file_name_prefix); std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side); @@ -1023,8 +1013,7 @@ void build_grid_module(ModuleManager& module_manager, if (0 < find_module_num_config_bits(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type)) { - memory_modules.push_back(pb_module); - memory_instances.push_back(pb_instance_id); + module_manager.add_configurable_child(grid_module, pb_module, pb_instance_id); } } @@ -1072,9 +1061,8 @@ void build_grid_module(ModuleManager& module_manager, /* Add module nets to connect memory cells inside * This is a one-shot addition that covers all the memory modules in this pb module! */ - if (false == memory_modules.empty()) { + if (0 < module_manager.configurable_children(grid_module).size()) { add_module_nets_memory_config_bus(module_manager, grid_module, - memory_modules, memory_instances, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index 25cc6d877..54bde223b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -153,12 +153,10 @@ void add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, static void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const CircuitLibrary& circuit_lib, const CircuitPortId& model_input_port, const CircuitPortId& model_output_port) { - for (size_t mem_index = 0; mem_index < memory_modules.size(); ++mem_index) { + for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { ModuleId net_src_module_id; size_t net_src_instance_id; ModulePortId net_src_port_id; @@ -176,20 +174,20 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, /* Find the port name of next memory module */ std::string sink_port_name = circuit_lib.port_lib_name(model_input_port); - net_sink_module_id = memory_modules[mem_index]; - net_sink_instance_id = memory_instances[mem_index]; + net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; + net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); } else { /* Find the port name of previous memory module */ std::string src_port_name = circuit_lib.port_lib_name(model_output_port); - net_src_module_id = memory_modules[mem_index - 1]; - net_src_instance_id = memory_instances[mem_index - 1]; + net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; + net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1]; net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ std::string sink_port_name = circuit_lib.port_lib_name(model_input_port); - net_sink_module_id = memory_modules[mem_index]; - net_sink_instance_id = memory_instances[mem_index]; + net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; + net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); } @@ -217,8 +215,8 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, */ /* Find the port name of previous memory module */ std::string src_port_name = circuit_lib.port_lib_name(model_output_port); - ModuleId net_src_module_id = memory_modules.back(); - size_t net_src_instance_id = memory_instances.back(); + ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); + size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back(); ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ @@ -299,6 +297,7 @@ void build_memory_standalone_module(ModuleManager& module_manager, for (size_t i = 0; i < num_mems; ++i) { size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); module_manager.add_child_module(mem_module, sram_mem_module); + module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance); /* Build module nets */ /* Wire inputs of parent module to inputs of child modules */ @@ -380,15 +379,11 @@ void build_memory_chain_module(ModuleManager& module_manager, /* Find the sram module in the module manager */ ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); - std::vector memory_modules; - std::vector memory_instances; - /* Instanciate each submodule */ for (size_t i = 0; i < num_mems; ++i) { size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); module_manager.add_child_module(mem_module, sram_mem_module); - memory_modules.push_back(sram_mem_module); - memory_instances.push_back(sram_mem_instance); + module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance); /* Build module nets to wire outputs of sram modules to outputs of memory module */ for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { @@ -405,7 +400,7 @@ void build_memory_chain_module(ModuleManager& module_manager, } /* Build module nets to wire the configuration chain */ - add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, memory_modules, memory_instances, + add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, circuit_lib, sram_input_ports[0], sram_output_ports[0]); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 61ee8fd29..3635ef47e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -229,9 +229,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager, t_rr_node* cur_rr_node, const std::vector& drive_rr_nodes, const size_t& switch_index, - const std::map& input_port_to_module_nets, - std::vector& memory_modules, - std::vector& memory_instances) { + const std::map& input_port_to_module_nets) { /* Check current rr_node is CHANX or CHANY*/ VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); @@ -306,8 +304,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager, mem_module, mem_instance_id, circuit_lib, mux_model); /* Update memory and instance list */ - memory_modules.push_back(mem_module); - memory_instances.push_back(mem_instance_id); + module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id); } /********************************************************************* @@ -324,9 +321,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager, const std::vector& rr_switches, const e_side& chan_side, const size_t& chan_node_id, - const std::map& input_port_to_module_nets, - std::vector& memory_modules, - std::vector& memory_instances) { + const std::map& input_port_to_module_nets) { std::vector drive_rr_nodes; /* Get the node */ @@ -363,8 +358,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager, grids, rr_switches, chan_side, cur_rr_node, drive_rr_nodes, cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], - input_port_to_module_nets, - memory_modules, memory_instances); + input_port_to_module_nets); } /*Nothing should be done else*/ } @@ -497,12 +491,6 @@ void build_switch_block_module(ModuleManager& module_manager, } } - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - /* Add routing multiplexers as child modules */ for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); @@ -514,8 +502,7 @@ void build_switch_block_module(ModuleManager& module_manager, circuit_lib, grids, rr_switches, side_manager.get_side(), itrack, - input_port_to_module_nets, - memory_modules, memory_instances); + input_port_to_module_nets); } } } @@ -547,9 +534,8 @@ void build_switch_block_module(ModuleManager& module_manager, /* Add all the nets to connect configuration ports from memory module to primitive modules * This is a one-shot addition that covers all the memory modules in this primitive module! */ - if (false == memory_modules.empty()) { + if (0 < module_manager.configurable_children(sb_module).size()) { add_module_nets_memory_config_bus(module_manager, sb_module, - memory_modules, memory_instances, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } } @@ -701,9 +687,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, const std::vector>& grids, const std::vector& rr_switches, t_rr_node* cur_rr_node, - const std::map& input_port_to_module_nets, - std::vector& memory_modules, - std::vector& memory_instances) { + const std::map& input_port_to_module_nets) { /* Check current rr_node is an input pin of a CLB */ VTR_ASSERT(IPIN == cur_rr_node->type); @@ -785,8 +769,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, mem_module, mem_instance_id, circuit_lib, mux_model); /* Update memory and instance list */ - memory_modules.push_back(mem_module); - memory_instances.push_back(mem_instance_id); + module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id); } /******************************************************************** @@ -805,9 +788,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager, const std::vector>& grids, const std::vector& rr_switches, t_rr_node* src_rr_node, - const std::map& input_port_to_module_nets, - std::vector& memory_modules, - std::vector& memory_instances) { + const std::map& input_port_to_module_nets) { if (1 > src_rr_node->fan_in) { return; /* This port has no driver, skip it */ } else if (1 == src_rr_node->fan_in) { @@ -820,8 +801,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager, cb_module, rr_gsb, cb_type, circuit_lib, grids, rr_switches, src_rr_node, - input_port_to_module_nets, - memory_modules, memory_instances); + input_port_to_module_nets); } /*Nothing should be done else*/ } @@ -973,12 +953,6 @@ void build_connection_block_module(ModuleManager& module_manager, } } - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - /* TODO: Add sub modules of routing multiplexers or direct interconnect*/ for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; @@ -987,8 +961,7 @@ void build_connection_block_module(ModuleManager& module_manager, cb_module, rr_gsb, cb_type, circuit_lib, grids, rr_switches, rr_gsb.get_ipin_node(cb_ipin_side, inode), - input_port_to_module_nets, - memory_modules, memory_instances); + input_port_to_module_nets); } } @@ -1019,9 +992,8 @@ void build_connection_block_module(ModuleManager& module_manager, /* Add all the nets to connect configuration ports from memory module to primitive modules * This is a one-shot addition that covers all the memory modules in this primitive module! */ - if (false == memory_modules.empty()) { + if (0 < module_manager.configurable_children(cb_module).size()) { add_module_nets_memory_config_bus(module_manager, cb_module, - memory_modules, memory_instances, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index dc004ff02..032ccb90a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -864,26 +864,18 @@ void build_top_module(ModuleManager& module_manager, add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); } - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - /* Organize the list of memory modules and instances */ - organize_top_module_memory_modules(module_manager, + organize_top_module_memory_modules(module_manager, top_module, circuit_lib, sram_orgz_type, sram_model, device_size, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy, - memory_modules, memory_instances); + compact_routing_hierarchy); /* Add module nets to connect memory cells inside * This is a one-shot addition that covers all the memory modules in this pb module! */ - if (false == memory_modules.empty()) { + if (0 < module_manager.configurable_children(top_module).size()) { add_top_module_nets_memory_config_bus(module_manager, top_module, - memory_modules, memory_instances, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp index 442e8953d..2566286da 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp @@ -20,7 +20,8 @@ * module *******************************************************************/ static -void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, +void organize_top_module_tile_cb_modules(ModuleManager& module_manager, + const ModuleId& top_module, const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, @@ -28,9 +29,7 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, const DeviceRRGSB& L_device_rr_gsb, const RRGSB& rr_gsb, const t_rr_type& cb_type, - const bool& compact_routing_hierarchy, - std::vector& memory_modules, - std::vector& memory_instances) { + const bool& compact_routing_hierarchy) { /* If the CB does not exist, we can skip addition */ if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) || (true != rr_gsb.is_cb_exist(cb_type))) { @@ -55,8 +54,7 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, if (0 < find_module_num_config_bits(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type)) { - memory_modules.push_back(cb_module); - memory_instances.push_back(cb_instance_ids[cb_coord.x()][cb_coord.y()]); + module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[cb_coord.x()][cb_coord.y()]); } } @@ -67,7 +65,8 @@ void organize_top_module_tile_cb_modules(const ModuleManager& module_manager, * module *******************************************************************/ static -void organize_top_module_tile_memory_modules(const ModuleManager& module_manager, +void organize_top_module_tile_memory_modules(ModuleManager& module_manager, + const ModuleId& top_module, const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, @@ -78,9 +77,7 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager const std::map>>& cb_instance_ids, const bool& compact_routing_hierarchy, const vtr::Point& tile_coord, - const e_side& tile_border_side, - std::vector& memory_modules, - std::vector& memory_instances) { + const e_side& tile_border_side) { vtr::Point gsb_coord_range(L_device_rr_gsb.get_gsb_range().get_x(), L_device_rr_gsb.get_gsb_range().get_y()); @@ -110,24 +107,21 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager if (0 < find_module_num_config_bits(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type)) { - memory_modules.push_back(sb_module); - memory_instances.push_back(sb_instance_ids[sb_coord.x()][sb_coord.y()]); + module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[sb_coord.x()][sb_coord.y()]); } /* Try to find and add CBX and CBY */ - organize_top_module_tile_cb_modules(module_manager, circuit_lib, + organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib, sram_orgz_type, sram_model, cb_instance_ids.at(CHANX), L_device_rr_gsb, rr_gsb, CHANX, - compact_routing_hierarchy, - memory_modules, memory_instances); + compact_routing_hierarchy); - organize_top_module_tile_cb_modules(module_manager, circuit_lib, + organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib, sram_orgz_type, sram_model, cb_instance_ids.at(CHANY), L_device_rr_gsb, rr_gsb, CHANY, - compact_routing_hierarchy, - memory_modules, memory_instances); + compact_routing_hierarchy); } /* Find the module name for this type of grid */ @@ -143,8 +137,7 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager if (0 < find_module_num_config_bits(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type)) { - memory_modules.push_back(grid_module); - memory_instances.push_back(grid_instance_ids[tile_coord.x()][tile_coord.y()]); + module_manager.add_configurable_child(top_module, grid_module, grid_instance_ids[tile_coord.x()][tile_coord.y()]); } } @@ -207,7 +200,8 @@ void organize_top_module_tile_memory_modules(const ModuleManager& module_manager * +---------------+----------+ * *******************************************************************/ -void organize_top_module_memory_modules(const ModuleManager& module_manager, +void organize_top_module_memory_modules(ModuleManager& module_manager, + const ModuleId& top_module, const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, @@ -217,12 +211,9 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, const DeviceRRGSB& L_device_rr_gsb, const std::vector>& sb_instance_ids, const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy, - std::vector& memory_modules, - std::vector& memory_instances) { + const bool& compact_routing_hierarchy) { /* Ensure clean vectors to return */ - VTR_ASSERT(true == memory_modules.empty()); - VTR_ASSERT(true == memory_instances.empty()); + VTR_ASSERT(true == module_manager.configurable_children(top_module).empty()); /* First, organize the I/O tiles on the border */ /* Special for the I/O tileas on RIGHT and BOTTOM, @@ -254,13 +245,12 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, for (const e_side& io_side : io_sides) { for (const vtr::Point& io_coord : io_coords[io_side]) { /* Identify the GSB that surrounds the grid */ - organize_top_module_tile_memory_modules(module_manager, + organize_top_module_tile_memory_modules(module_manager, top_module, circuit_lib, sram_orgz_type, sram_model, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, - io_coord, io_side, - memory_modules, memory_instances); + io_coord, io_side); } } @@ -285,13 +275,12 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, } for (const vtr::Point& core_coord : core_coords) { - organize_top_module_tile_memory_modules(module_manager, + organize_top_module_tile_memory_modules(module_manager, top_module, circuit_lib, sram_orgz_type, sram_model, grids, grid_instance_ids, L_device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, - core_coord, NUM_SIDES, - memory_modules, memory_instances); + core_coord, NUM_SIDES); } } @@ -343,18 +332,13 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, static void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type) { - /* Ensure that the size of memory_model vector matches the memory_module vector */ - VTR_ASSERT(memory_modules.size() == memory_instances.size()); - switch (sram_orgz_type) { case SPICE_SRAM_STANDALONE: /* Nothing to do */ break; case SPICE_SRAM_SCAN_CHAIN: { - add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, memory_modules, memory_instances, sram_orgz_type); + add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, SPICE_SRAM_SCAN_CHAIN); break; } case SPICE_SRAM_MEMORY_BANK: @@ -402,14 +386,11 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, *******************************************************************/ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type, const e_spice_model_design_tech& mem_tech) { switch (mem_tech) { case SPICE_MODEL_DESIGN_CMOS: add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module, - memory_modules, memory_instances, sram_orgz_type); break; case SPICE_MODEL_DESIGN_RRAM: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h index 42312c8bc..1ccc2b7d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h @@ -8,7 +8,8 @@ #include "circuit_library.h" #include "rr_blocks.h" -void organize_top_module_memory_modules(const ModuleManager& module_manager, +void organize_top_module_memory_modules(ModuleManager& module_manager, + const ModuleId& top_module, const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, @@ -18,14 +19,10 @@ void organize_top_module_memory_modules(const ModuleManager& module_manager, const DeviceRRGSB& L_device_rr_gsb, const std::vector>& sb_instance_ids, const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy, - std::vector& memory_modules, - std::vector& memory_instances); + const bool& compact_routing_hierarchy); void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, const ModuleId& parent_module, - const std::vector& memory_modules, - const std::vector& memory_instances, const e_sram_orgz& sram_orgz_type, const e_spice_model_design_tech& mem_tech); From 2787a07f0db4eeff865f25a634eef5b6bbcb5404 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Oct 2019 17:34:21 -0600 Subject: [PATCH 326/482] start refactoring bitstream generation --- .../SRC/fpga_x2p/base/bitstream_context.cpp | 46 ++++++++++++++++ .../vpr/SRC/fpga_x2p/base/bitstream_context.h | 55 ++++++++++++++----- .../SRC/fpga_x2p/base/bitstream_context_fwd.h | 10 ++-- 3 files changed, 92 insertions(+), 19 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp new file mode 100644 index 000000000..95b3ec978 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp @@ -0,0 +1,46 @@ +/****************************************************************************** + * This file includes member functions for data structure BitstreamContext + ******************************************************************************/ +#include "vtr_assert.h" +#include "bitstream_context.h" + +/************************************************** + * Public Accessors : Aggregates + *************************************************/ +/* Find all the configuration bits */ +BitstreamContext::config_bit_range BitstreamContext::bits() const { + return vtr::make_range(bit_ids_.begin(), bit_ids_.end()); +} + +/****************************************************************************** + * Public Accessors + ******************************************************************************/ +bool BitstreamContext::bit_value(const ConfigBitId& bit_id) const { + /* Ensure a valid id */ + VTR_ASSERT(true == valid_bit_id(bit_id)); + + return bit_values_[bit_id]; +} + + +/****************************************************************************** + * Public Mutators + ******************************************************************************/ +ConfigBitId BitstreamContext::add_bit(const bool& bit_value) { + ConfigBitId bit = ConfigBitId(bit_ids_.size()); + /* Add a new bit, and allocate associated data structures */ + bit_ids_.push_back(bit); + bit_values_.push_back(bit_value); + shared_config_bit_values_.emplace_back(); + bit_parent_modules_.emplace_back(); + bit_parent_instances_.emplace_back(); + + return bit; +} + +/****************************************************************************** + * Public Validators + ******************************************************************************/ +bool BitstreamContext::valid_bit_id(const ConfigBitId& bit_id) const { + return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h index 6ee011182..651726784 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h @@ -4,27 +4,54 @@ #ifndef BITSTREAM_CONTEXT_H #define BITSTREAM_CONTEXT_H +#include #include "vtr_vector.h" +#include "module_manager.h" + #include "bitstream_context_fwd.h" class BitstreamContext { - private: /* Internal data */ - enum e_sram_orgz config_scheme_; /* The type of configuration protocol */ - CircuitModelId& sram_model_; /* The memory circuit model used by the Bitstream generation */ - size_t num_memory_bits_; /* Number of memory bits */ - size_t num_bls_; /* Number of Bit Lines */ - size_t num_wls_; /* Number of Word Lines */ + public: /* Types and ranges */ + typedef vtr::vector::const_iterator config_bit_iterator; + + typedef vtr::Range config_bit_range; + + public: /* Public aggregators */ + /* Find all the configuration bits */ + config_bit_range bits() const; + + public: /* Public Accessors */ + bool bit_value(const ConfigBitId& bit_id) const; + + public: /* Public Mutators */ + ConfigBitId add_bit(const bool& bit_value); + + public: /* Public Validators */ + bool valid_bit_id(const ConfigBitId& bit_id) const; + + private: /* Internal data */ + size_t num_shared_bits_; /* Number of reserved Bit/WL Lines, ONLY applicable to RRAM-based FPGA */ - size_t num_reserved_bls_; /* Number of reserved Bit Lines, ONLY applicable to RRAM-based FPGA */ - size_t num_reserved_wls_; /* Number of reserved Word Lines, ONLY applicable to RRAM-based FPGA */ /* Unique id of a bit in the Bitstream */ vtr::vector bit_ids_; - /* Bit line address of a bit in the Bitream: ONLY applicable to memory-decoders */ - vtr::vector bl_addr_; - /* Word line address of a bit in the Bitream: ONLY applicable to memory-decoders */ - vtr::vector wl_addr_; - /* value of a bit in the Bitream */ - vtr::vector bit_val_; + /* value of a bit in the Bitstream */ + vtr::vector bit_values_; + /* value of a shared configuration bits in the Bitstream */ + vtr::vector> shared_config_bit_values_; + + /* Back-annotation for the bits */ + /* Parent Module of a bit in the Bitstream + * For each bit, the list of ModuleId and instance ids reflect its position in the module tree + * The first ModuleId/Instance is the direct parent module/instance of the bit + * while the last ModuleId/instance is the top-level module/instance of the bit + * For example: a bit could be back traced by + * []/.../[] + */ + vtr::vector> bit_parent_modules_; + vtr::vector> bit_parent_instances_; + + /* Fast lookup for bitstream */ + std::map bit_lookup_; }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h index 29d85580e..5309b82bc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h @@ -1,14 +1,14 @@ /************************************************** * This file includes only declarations for - * the data structures for module managers - * Please refer to module_manager.h for more details + * the data structures for bitstream database + * Please refer to bitstream_context.h for more details *************************************************/ -#ifndef MODULE_MANAGER_FWD_H -#define MODULE_MANAGER_FWD_H +#ifndef BITSTREAM_CONTEXT_FWD_H +#define BITSTREAM_CONTEXT_MANAGER_FWD_H #include "vtr_strong_id.h" -/* Strong Ids for ModuleManager */ +/* Strong Ids for BitstreamContext */ struct config_bit_id_tag; typedef vtr::StrongId ConfigBitId; From f26dbfe0805c31a2f7365508f8c1c0a47771d8c5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Oct 2019 20:24:52 -0600 Subject: [PATCH 327/482] add instance name for top-level modules to ease readability --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 20 ++++++++++++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 6 +++++ .../module_builder/build_top_module.cpp | 26 ++++++++++++++++--- 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 97f5068a9..43beec5a2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -734,6 +734,26 @@ std::string generate_grid_block_module_name(const std::string& prefix, return module_name; } +/********************************************************************* + * Generate the instance name of a grid block + **********************************************************************/ +std::string generate_grid_block_instance_name(const std::string& prefix, + const std::string& block_name, + const bool& is_block_io, + const e_side& io_side, + const vtr::Point& grid_coord) { + std::string module_name(prefix); + + module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string()); + module_name += std::string("_"); + module_name += std::to_string(grid_coord.x()); + module_name += std::string("_"); + module_name += std::to_string(grid_coord.y()); + + return module_name; +} + + /********************************************************************* * Generate the module name of a physical block * To ensure a unique name for each physical block inside the graph of complex blocks diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 6ab310f5c..a602dc4be 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -145,6 +145,12 @@ std::string generate_grid_block_module_name(const std::string& prefix, const bool& is_block_io, const e_side& io_side); +std::string generate_grid_block_instance_name(const std::string& prefix, + const std::string& block_name, + const bool& is_block_io, + const e_side& io_side, + const vtr::Point& grid_coord); + std::string generate_physical_block_module_name(const std::string& prefix, t_pb_type* physical_pb_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index 032ccb90a..01af77409 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -92,7 +92,8 @@ static size_t add_top_module_grid_instance(ModuleManager& module_manager, const ModuleId& top_module, t_type_ptr grid_type, - const e_side& border_side) { + const e_side& border_side, + const vtr::Point& grid_coord) { /* Find the module name for this type of grid */ std::string grid_module_name_prefix(grid_verilog_file_name_prefix); std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); @@ -102,6 +103,11 @@ size_t add_top_module_grid_instance(ModuleManager& module_manager, size_t grid_instance = module_manager.num_instance(top_module, grid_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, grid_module); + /* Set an unique name to the instance + * Note: it is your risk to gurantee the name is unique! + */ + std::string instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side, grid_coord); + module_manager.set_child_instance_name(top_module, grid_module, grid_instance, instance_name); return grid_instance; } @@ -164,9 +170,10 @@ std::vector> add_top_module_grid_instances(ModuleManager& mo /* We should not meet any I/O grid */ VTR_ASSERT(IO_TYPE != grids[ix][iy].type); /* Add a grid module to top_module*/ + vtr::Point grid_coord(ix, iy); grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module, grids[ix][iy].type, - NUM_SIDES); + NUM_SIDES, grid_coord); } } @@ -209,7 +216,7 @@ std::vector> add_top_module_grid_instances(ModuleManager& mo /* We should not meet any I/O grid */ VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); /* Add a grid module to top_module*/ - grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side); + grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side, io_coordinate); } } @@ -255,6 +262,12 @@ std::vector> add_top_module_switch_block_instances(ModuleMan sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, sb_module); + /* Set an unique name to the instance + * Note: it is your risk to gurantee the name is unique! + */ + module_manager.set_child_instance_name(top_module, sb_module, + sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], + generate_switch_block_module_name(vtr::Point(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()))); } } @@ -307,6 +320,13 @@ std::vector> add_top_module_connection_block_instances(Modul cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module); /* Add the module to top_module */ module_manager.add_child_module(top_module, cb_module); + /* Set an unique name to the instance + * Note: it is your risk to gurantee the name is unique! + */ + module_manager.set_child_instance_name(top_module, cb_module, + cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], + generate_connection_block_module_name(cb_type, vtr::Point(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))); + } } From 13c62fdcf8bb63801cad630f70c0a70615523c68 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Oct 2019 15:43:29 -0600 Subject: [PATCH 328/482] add more methods to bitstream manager (renamed from bitstream context) --- .../SRC/fpga_x2p/base/bitstream_context.cpp | 46 ------ .../vpr/SRC/fpga_x2p/base/bitstream_context.h | 58 ------- .../SRC/fpga_x2p/base/bitstream_manager.cpp | 141 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/bitstream_manager.h | 122 +++++++++++++++ ..._context_fwd.h => bitstream_manager_fwd.h} | 10 +- 5 files changed, 269 insertions(+), 108 deletions(-) delete mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp delete mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h rename vpr7_x2p/vpr/SRC/fpga_x2p/base/{bitstream_context_fwd.h => bitstream_manager_fwd.h} (60%) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp deleted file mode 100644 index 95b3ec978..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.cpp +++ /dev/null @@ -1,46 +0,0 @@ -/****************************************************************************** - * This file includes member functions for data structure BitstreamContext - ******************************************************************************/ -#include "vtr_assert.h" -#include "bitstream_context.h" - -/************************************************** - * Public Accessors : Aggregates - *************************************************/ -/* Find all the configuration bits */ -BitstreamContext::config_bit_range BitstreamContext::bits() const { - return vtr::make_range(bit_ids_.begin(), bit_ids_.end()); -} - -/****************************************************************************** - * Public Accessors - ******************************************************************************/ -bool BitstreamContext::bit_value(const ConfigBitId& bit_id) const { - /* Ensure a valid id */ - VTR_ASSERT(true == valid_bit_id(bit_id)); - - return bit_values_[bit_id]; -} - - -/****************************************************************************** - * Public Mutators - ******************************************************************************/ -ConfigBitId BitstreamContext::add_bit(const bool& bit_value) { - ConfigBitId bit = ConfigBitId(bit_ids_.size()); - /* Add a new bit, and allocate associated data structures */ - bit_ids_.push_back(bit); - bit_values_.push_back(bit_value); - shared_config_bit_values_.emplace_back(); - bit_parent_modules_.emplace_back(); - bit_parent_instances_.emplace_back(); - - return bit; -} - -/****************************************************************************** - * Public Validators - ******************************************************************************/ -bool BitstreamContext::valid_bit_id(const ConfigBitId& bit_id) const { - return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h deleted file mode 100644 index 651726784..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** - * This file introduces a data structure to store bitstream-related information - ******************************************************************************/ -#ifndef BITSTREAM_CONTEXT_H -#define BITSTREAM_CONTEXT_H - -#include -#include "vtr_vector.h" -#include "module_manager.h" - -#include "bitstream_context_fwd.h" - -class BitstreamContext { - public: /* Types and ranges */ - typedef vtr::vector::const_iterator config_bit_iterator; - - typedef vtr::Range config_bit_range; - - public: /* Public aggregators */ - /* Find all the configuration bits */ - config_bit_range bits() const; - - public: /* Public Accessors */ - bool bit_value(const ConfigBitId& bit_id) const; - - public: /* Public Mutators */ - ConfigBitId add_bit(const bool& bit_value); - - public: /* Public Validators */ - bool valid_bit_id(const ConfigBitId& bit_id) const; - - private: /* Internal data */ - size_t num_shared_bits_; /* Number of reserved Bit/WL Lines, ONLY applicable to RRAM-based FPGA */ - - /* Unique id of a bit in the Bitstream */ - vtr::vector bit_ids_; - /* value of a bit in the Bitstream */ - vtr::vector bit_values_; - /* value of a shared configuration bits in the Bitstream */ - vtr::vector> shared_config_bit_values_; - - /* Back-annotation for the bits */ - /* Parent Module of a bit in the Bitstream - * For each bit, the list of ModuleId and instance ids reflect its position in the module tree - * The first ModuleId/Instance is the direct parent module/instance of the bit - * while the last ModuleId/instance is the top-level module/instance of the bit - * For example: a bit could be back traced by - * []/.../[] - */ - vtr::vector> bit_parent_modules_; - vtr::vector> bit_parent_instances_; - - /* Fast lookup for bitstream */ - std::map bit_lookup_; -}; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp new file mode 100644 index 000000000..c26423b3e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp @@ -0,0 +1,141 @@ +/****************************************************************************** + * This file includes member functions for data structure BitstreamManager + ******************************************************************************/ +#include + +#include "vtr_assert.h" +#include "bitstream_manager.h" + +/************************************************** + * Public Accessors : Aggregates + *************************************************/ +/* Find all the configuration bits */ +BitstreamManager::config_bit_range BitstreamManager::bits() const { + return vtr::make_range(bit_ids_.begin(), bit_ids_.end()); +} + +/* Find all the configuration blocks */ +BitstreamManager::config_block_range BitstreamManager::blocks() const { + return vtr::make_range(block_ids_.begin(), block_ids_.end()); +} + +/****************************************************************************** + * Public Accessors + ******************************************************************************/ +bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const { + /* Ensure a valid id */ + VTR_ASSERT(true == valid_bit_id(bit_id)); + + return bit_values_[bit_id]; +} + +std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + return block_names_[block_id]; +} + +ConfigBlockId BitstreamManager::block_parent(const ConfigBlockId& block_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + return parent_block_ids_[block_id]; +} + +std::vector BitstreamManager::block_children(const ConfigBlockId& block_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + return child_block_ids_[block_id]; +} + +std::vector BitstreamManager::block_bits(const ConfigBlockId& block_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + return block_bit_ids_[block_id]; +} + +ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_bit_id(bit_id)); + + return bit_parent_block_ids_[bit_id]; +} + +/****************************************************************************** + * Public Mutators + ******************************************************************************/ +ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { + ConfigBitId bit = ConfigBitId(bit_ids_.size()); + /* Add a new bit, and allocate associated data structures */ + bit_ids_.push_back(bit); + bit_values_.push_back(bit_value); + shared_config_bit_values_.emplace_back(); + bit_parent_block_ids_.push_back(ConfigBlockId::INVALID()); + + return bit; +} + +ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { + ConfigBlockId block = ConfigBlockId(block_ids_.size()); + /* Add a new bit, and allocate associated data structures */ + block_ids_.push_back(block); + block_names_.push_back(block_name); + block_bit_ids_.emplace_back(); + parent_block_ids_.push_back(ConfigBlockId::INVALID()); + child_block_ids_.emplace_back(); + + return block; +} + +void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block) { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(parent_block)); + VTR_ASSERT(true == valid_block_id(child_block)); + + /* We should have only a parent block for each block! */ + VTR_ASSERT(ConfigBlockId::INVALID() == parent_block_ids_[child_block]); + + /* Ensure the child block is not in the list of children of the parent block */ + std::vector::iterator it = std::find(child_block_ids_[parent_block].begin(), child_block_ids_[parent_block].end(), child_block); + VTR_ASSERT(it == child_block_ids_[parent_block].end()); + + /* Add the child_block to the parent_block */ + child_block_ids_[parent_block].push_back(child_block); + /* Register the block in the parent of the block */ + parent_block_ids_[child_block] = parent_block; +} + +void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit) { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block)); + VTR_ASSERT(true == valid_bit_id(bit)); + + /* We should have only a parent block for each bit! */ + VTR_ASSERT(ConfigBlockId::INVALID() == bit_parent_block_ids_[bit]); + + /* Add the bit to the block */ + block_bit_ids_[block].push_back(bit); + /* Register the block in the parent of the bit */ + bit_parent_block_ids_[bit] = block; +} + +void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits) { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_bit_id(bit)); + + shared_config_bit_values_[bit] = shared_config_bits; +} + +/****************************************************************************** + * Public Validators + ******************************************************************************/ +bool BitstreamManager::valid_bit_id(const ConfigBitId& bit_id) const { + return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]); +} + +bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const { + return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h new file mode 100644 index 000000000..ac35b7539 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h @@ -0,0 +1,122 @@ +/****************************************************************************** + * This file introduces a data structure to store bitstream-related information + * + * General concept + * --------------- + * The idea is to create a unified data structure that stores all the configuration bits + * with proper annotation to which modules in FPGA fabric it belongs to. + * 1. It can be easily organized in fabric-dependent representation + * (generate a sequence of bitstream which exactly fit the configuration protocol of FPGA fabric) + * 2. Or it can be easily organized in fabric-independent representation (think about XML file) + * + * Cross-reference + * --------------- + * May be used only when you want to bind the bitstream to a specific FPGA fabric! + * If you do so, please make sure the block name is exactly same as the instance name + * of a child module in ModuleManager!!! + * The configurable modules/instances in module manager are arranged + * in the sequence to fit different configuration protocol. + * By using the link between ModuleManager and BitstreamManager, + * we can build a sequence of configuration bits to fit different configuration protocols. + * + * +------------------+ +-----------------+ + * | | block_name == instance_name | | + * | BitstreamManager |-------------------------------->| ModuleManager | + * | | | | + * +------------------+ +-----------------+ + * + * Restrictions: + * 1. Each block inside BitstreamManager should have only 1 parent block + * and multiple child block + * 2. Each bit inside BitstreamManager should have only 1 parent block + * + ******************************************************************************/ +#ifndef BITSTREAM_MANAGER_H +#define BITSTREAM_MANAGER_H + +#include +#include "vtr_vector.h" + +#include "bitstream_manager_fwd.h" + +class BitstreamManager { + public: /* Types and ranges */ + typedef vtr::vector::const_iterator config_bit_iterator; + typedef vtr::vector::const_iterator config_block_iterator; + + typedef vtr::Range config_bit_range; + typedef vtr::Range config_block_range; + + public: /* Public aggregators */ + /* Find all the configuration bits */ + config_bit_range bits() const; + + config_block_range blocks() const; + + public: /* Public Accessors */ + /* Find the value of bitstream */ + bool bit_value(const ConfigBitId& bit_id) const; + + /* Find a name of a block */ + std::string block_name(const ConfigBlockId& block_id) const; + + /* Find the parent of a block */ + ConfigBlockId block_parent(const ConfigBlockId& block_id) const; + + /* Find the children of a block */ + std::vector block_children(const ConfigBlockId& block_id) const; + + /* Find all the bits that belong to a block */ + std::vector block_bits(const ConfigBlockId& block_id) const; + + /* Find the parent block of a bit */ + ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const; + + public: /* Public Mutators */ + /* Add a new configuration bit to the bitstream manager */ + ConfigBitId add_bit(const bool& bit_value); + + /* Add a new block of configuration bits to the bitstream manager */ + ConfigBlockId add_block(const std::string& block_name); + + /* Set a block as a child block of another */ + void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block); + + /* Add a configuration bit to a block */ + void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit); + + /* Add share configuration bits to a configuration bit */ + void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits); + + public: /* Public Validators */ + bool valid_bit_id(const ConfigBitId& bit_id) const; + + bool valid_block_id(const ConfigBlockId& block_id) const; + + private: /* Internal data */ + /* Unique id of a block of bits in the Bitstream */ + vtr::vector block_ids_; + vtr::vector> block_bit_ids_; + + /* Back-annotation for the bits */ + /* Parent block of a bit in the Bitstream + * For each bit, the block name can be designed to be same as the instance name in a module + * to reflect its position in the module tree (ModuleManager) + * Note that the blocks here all unique, unlike ModuleManager where modules can be instanciated + * Therefore, this block graph can be considered as a flattened graph of ModuleGraph + */ + vtr::vector block_names_; + vtr::vector parent_block_ids_; + vtr::vector> child_block_ids_; + + /* Unique id of a bit in the Bitstream */ + vtr::vector bit_ids_; + vtr::vector bit_parent_block_ids_; + /* value of a bit in the Bitstream */ + vtr::vector bit_values_; + /* value of a shared configuration bits in the Bitstream */ + vtr::vector> shared_config_bit_values_; +}; + +#endif + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_fwd.h similarity index 60% rename from vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_fwd.h index 5309b82bc..a9cebe55a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_fwd.h @@ -1,18 +1,20 @@ /************************************************** * This file includes only declarations for * the data structures for bitstream database - * Please refer to bitstream_context.h for more details + * Please refer to bitstream_manager.h for more details *************************************************/ -#ifndef BITSTREAM_CONTEXT_FWD_H -#define BITSTREAM_CONTEXT_MANAGER_FWD_H +#ifndef BITSTREAM_MANAGER_FWD_H +#define BITSTREAM_MANAGER_FWD_H #include "vtr_strong_id.h" /* Strong Ids for BitstreamContext */ +struct config_block_id_tag; struct config_bit_id_tag; +typedef vtr::StrongId ConfigBlockId; typedef vtr::StrongId ConfigBitId; -class BitstreamContext; +class BitstreamManager; #endif From 838173f3c4445494eadbbcd8d311f9588ad3f5fb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Oct 2019 21:01:11 -0600 Subject: [PATCH 329/482] start refactoring bitstream generator --- vpr7_x2p/libarchfpga/SRC/linkedlist.h | 2 + vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 158 +++++++++++-- vpr7_x2p/vpr/SRC/device/mux_graph.h | 18 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 13 ++ .../bitstream/build_device_bitstream.cpp | 91 ++++++++ .../bitstream/build_device_bitstream.h | 26 +++ .../bitstream/build_mux_bitstream.cpp | 105 +++++++++ .../fpga_x2p/bitstream/build_mux_bitstream.h | 21 ++ .../bitstream/build_routing_bitstream.cpp | 214 ++++++++++++++++++ .../bitstream/build_routing_bitstream.h | 23 ++ .../module_builder/build_module_graph.cpp | 8 +- 11 files changed, 658 insertions(+), 21 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h diff --git a/vpr7_x2p/libarchfpga/SRC/linkedlist.h b/vpr7_x2p/libarchfpga/SRC/linkedlist.h index 0557da545..3cedabcbb 100644 --- a/vpr7_x2p/libarchfpga/SRC/linkedlist.h +++ b/vpr7_x2p/libarchfpga/SRC/linkedlist.h @@ -1,6 +1,8 @@ #ifndef LINKEDLIST_H #define LINKEDLIST_H +#include "util.h" + /*General Purpose Linked List*/ typedef struct s_llist t_llist; struct s_llist diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index b453ffef8..23230ae74 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -3,6 +3,7 @@ * data structures in mux_graph.h *************************************************/ #include +#include #include #include @@ -482,6 +483,21 @@ MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { return MuxNodeId::INVALID(); } +/* Get the node id of a given output */ +MuxNodeId MuxGraph::node_id(const MuxOutputId& output_id) const { + /* Use the node_lookup to accelerate the search */ + for (const auto& lvl : node_lookup_) { + for (const auto& cand_node : lvl[MUX_OUTPUT_NODE]) { + if (output_id == node_output_ids_[cand_node]) { + return cand_node; + } + } + } + + return MuxNodeId::INVALID(); +} + + /* Get the node id w.r.t. the node level and node_index at the level * Return an invalid value if not found */ @@ -516,19 +532,41 @@ MuxNodeId MuxGraph::node_id(const size_t& node_level, const size_t& node_index_a return ret_node; } -/* Decode memory bits based on an input id */ -std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id) const { +/* Decode memory bits based on an input id and an output id */ +std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id, + const MuxOutputId& output_id) const { /* initialize the memory bits: TODO: support default value */ - std::vector mem_bits(mem_ids_.size(), 0); + std::vector mem_bits(mem_ids_.size(), false); - /* valid the input */ + /* valid the input and output */ VTR_ASSERT_SAFE(valid_input_id(input_id)); + VTR_ASSERT_SAFE(valid_output_id(output_id)); - /* Route the input to the output and update mem */ - MuxNodeId next_node = node_id(input_id); - while ( 0 < node_out_edges_[next_node].size() ) { - VTR_ASSERT_SAFE (1 == node_out_edges_[next_node].size()); - MuxEdgeId edge = node_out_edges_[next_node][0]; + /* Mark all the nodes as not visited */ + vtr::vector visited(nodes().size(), false); + + /* Create a queue for Breadth-First Search */ + std::list queue; + + /* Mark the input node as visited and enqueue it */ + visited[node_id(input_id)] = true; + queue.push_back(node_id(input_id)); + + /* Create a flag to indicate if the route is success or not */ + bool route_success = false; + + while(!queue.empty()) { + /* Dequeue a mux node from queue, + * we will walk through all the fan-in of this node in this loop + */ + MuxNodeId node_to_expand = queue.front(); + queue.pop_front(); + /* Get all fan-in nodes of the dequeued node + * If the node has not been visited, + * then mark it visited and enqueue it + */ + VTR_ASSERT_SAFE (1 == node_out_edges_[node_to_expand].size()); + MuxEdgeId edge = node_out_edges_[node_to_expand][0]; /* Configure the mem bits: * if inv_mem is enabled, it means 0 to enable this edge @@ -537,25 +575,113 @@ std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id) con MuxMemId mem = edge_mem_ids_[edge]; VTR_ASSERT_SAFE (valid_mem_id(mem)); if (true == edge_inv_mem_[edge]) { - mem_bits[size_t(mem)] = 0; + mem_bits[size_t(mem)] = false; } else { - mem_bits[size_t(mem)] = 1; + mem_bits[size_t(mem)] = true; } /* each edge must have 1 fan-out */ VTR_ASSERT_SAFE (1 == edge_sink_nodes_[edge].size()); - /* Visit the next node */ - next_node = edge_sink_nodes_[edge][0]; + /* Get the fan-out node */ + MuxNodeId next_node = edge_sink_nodes_[edge][0]; + + /* If next node is the output node we want, we can finish here */ + if (next_node == node_id(output_id)) { + route_success = true; + break; + } + + /* Add next node to the queue if not visited yet */ + if (false == visited[next_node]) { + visited[next_node] = true; + queue.push_back(next_node); + } } - /* valid the output */ - VTR_ASSERT_SAFE(MUX_OUTPUT_NODE == node_types_[next_node]); - VTR_ASSERT_SAFE(valid_output_id(node_output_ids_[next_node])); + /* Routing must be success! */ + VTR_ASSERT(true == route_success); return mem_bits; } +/* Find the input node that the memory bits will route an output node to + * This function backward propagate from the output node to an input node + * assuming the memory bits are applied + */ +MuxInputId MuxGraph::find_input_node_driven_by_output_node(const std::map& memory_bits, + const MuxOutputId& output_id) const { + /* Ensure that the memory bits fit the size of memory bits in this MUX */ + VTR_ASSERT(memory_bits.size() == mem_ids_.size()); + + /* valid the output */ + VTR_ASSERT_SAFE(valid_output_id(output_id)); + + /* Start from the output node */ + /* Mark all the nodes as not visited */ + vtr::vector visited(nodes().size(), false); + + /* Create a queue for Breadth-First Search */ + std::list queue; + + /* Mark the output node as visited and enqueue it */ + visited[node_id(output_id)] = true; + queue.push_back(node_id(output_id)); + + /* Record the destination input id */ + MuxInputId des_input_id = MuxInputId::INVALID(); + + while(!queue.empty()) { + /* Dequeue a mux node from queue, + * we will walk through all the fan-in of this node in this loop + */ + MuxNodeId node_to_expand = queue.front(); + queue.pop_front(); + /* Get all fan-in nodes of the dequeued node + * If the node has not been visited, + * then mark it visited and enqueue it + */ + MuxEdgeId next_edge = MuxEdgeId::INVALID(); + for (const MuxEdgeId& edge : node_in_edges_[node_to_expand]) { + /* Configure the mem bits and find the edge that will propagate the signal + * if inv_mem is enabled, it means false to enable this edge + * otherwise, it is true to enable this edge + */ + MuxMemId mem = edge_mem_ids_[edge]; + VTR_ASSERT_SAFE (valid_mem_id(mem)); + if (edge_inv_mem_[edge] == !memory_bits.at(mem)) { + next_edge = edge; + break; + } + } + /* We must have a valid next edge */ + VTR_ASSERT(MuxEdgeId::INVALID() != next_edge); + + /* each edge must have 1 fan-out */ + VTR_ASSERT_SAFE (1 == edge_src_nodes_[next_edge].size()); + + /* Get the fan-in node */ + MuxNodeId next_node = edge_src_nodes_[next_edge][0]; + + /* If next node is an input node, we can finish here */ + if (true == is_node_input(next_node)) { + des_input_id = input_id(next_node); + break; + } + + /* Add next node to the queue if not visited yet */ + if (false == visited[next_node]) { + visited[next_node] = true; + queue.push_back(next_node); + } + } + + /* Routing must be success! */ + VTR_ASSERT(MuxInputId::INVALID() != des_input_id); + + return des_input_id; +} + /************************************************** * Private mutators: basic operations *************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 6774389f0..18fc5464c 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -27,6 +27,7 @@ #ifndef MUX_GRAPH_H #define MUX_GRAPH_H +#include #include "vtr_vector.h" #include "vtr_range.h" #include "mux_graph_fwd.h" @@ -105,6 +106,8 @@ class MuxGraph { std::vector build_mux_branch_graphs() const; /* Get the node id of a given input */ MuxNodeId node_id(const MuxInputId& input_id) const; + /* Get the node id of a given output */ + MuxNodeId node_id(const MuxOutputId& output_id) const; /* Get the node id w.r.t. the node level and node_index at the level */ MuxNodeId node_id(const size_t& node_level, const size_t& node_index_at_level) const; /* Get the input id of a given node */ @@ -115,8 +118,19 @@ class MuxGraph { MuxOutputId output_id(const MuxNodeId& node_id) const; /* Identify if the node is an output of the MUX */ bool is_node_output(const MuxNodeId& node_id) const; - /* Decode memory bits based on an input id */ - std::vector decode_memory_bits(const MuxInputId& input_id) const; + /* Decode memory bits based on an input id and an output id + * This function will start from the input node + * and do a forward propagation until reaching the output node + */ + std::vector decode_memory_bits(const MuxInputId& input_id, + const MuxOutputId& output_id) const; + /* Find the input node that the memory bits will route an output node to + * This function backward propagate from the output node to an input node + * assuming the memory bits are applied + * Note: This function is mainly used for decoding LUT MUXes + */ + MuxInputId find_input_node_driven_by_output_node(const std::map& memory_bits, + const MuxOutputId& output_id) const; private: /* Private mutators : basic operations */ /* Add a unconfigured node to the MuxGraph */ MuxNodeId add_node(const enum e_mux_graph_node_type& node_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 3f1ee9e03..7572b15fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -30,6 +30,7 @@ #include "mux_library_builder.h" #include "build_module_graph.h" +#include "build_device_bitstream.h" #include "spice_api.h" #include "verilog_api.h" @@ -82,6 +83,18 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, device_size, grids, rr_switches, clb2clb_directs, device_rr_gsb); + /* Build bitstream database if needed */ + BitstreamManager bitstream_manager; + if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) + &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) + &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { + bitstream_manager = build_device_bitstream(vpr_setup, Arch, module_manager, + Arch.spice->circuit_lib, mux_lib, + device_size, grids, + rr_switches, rr_node, device_rr_gsb); + + } + /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) { vpr_fpga_spice(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp new file mode 100644 index 000000000..5acf7fe33 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp @@ -0,0 +1,91 @@ +/******************************************************************** + * This file includes functions to build bitstream from a mapped + * FPGA fabric. + * We decode the bitstream from configuration of routing multiplexers + * and Look-Up Tables (LUTs) which locate in CLBs and global routing architecture + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "util.h" + +#include "fpga_x2p_naming.h" + +#include "build_routing_bitstream.h" +#include "build_device_bitstream.h" + +/******************************************************************** + * Top-level function to build a bistream from the FPGA device + * 1. It will organize the bitstream w.r.t. the hierarchy of module graphs + * describing the FPGA fabric + * 2. It will decode configuration bits from routing multiplexers used in + * global routing architecture + * 3. It will decode configuration bits from routing multiplexers and LUTs + * used in CLBs + * + * Note: this function create a bitstream which is binding to the module graphs + * of the FPGA fabric that FPGA-X2P generates! + * But it can be used to output a generic bitstream for VPR mapping FPGA + *******************************************************************/ +BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, + const t_arch& arch, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const DeviceRRGSB& L_device_rr_gsb) { + /* Check if the routing architecture we support*/ + if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { + vpr_printf(TIO_MESSAGE_ERROR, + "FPGA X2P only supports uni-directional routing architecture!\n"); + exit(1); + } + + /* We don't support mrFPGA */ +#ifdef MRFPGA_H + if (is_mrFPGA) { + vpr_printf(TIO_MESSAGE_ERROR, + "FPGA X2P does not support mrFPGA!\n"); + exit(1); + } +#endif + + /* Bistream builder formally starts*/ + vpr_printf(TIO_MESSAGE_INFO, "\nStart building bitstream for FPGA fabric...\n"); + + /* Bitstream manager to be built */ + BitstreamManager bitstream_manager; + + /* Start time count */ + clock_t t_start = clock(); + + /* Assign the SRAM model applied to the FPGA fabric */ + VTR_ASSERT(NULL != arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ + t_spice_model* mem_model = arch.sram_inf.verilog_sram_inf_orgz->spice_model; + /* initialize the SRAM organization information struct */ + CircuitModelId sram_model = arch.spice->circuit_lib.model(mem_model->name); + VTR_ASSERT(CircuitModelId::INVALID() != sram_model); + + /* Create the top-level block for bitstream + * This is related to the top-level module of fpga + */ + std::string top_block_name = generate_fpga_top_module_name(); + ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); + + /* Create bitstream from routing architectures */ + build_routing_bitstream(bitstream_manager, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "Building bitstream took %g seconds\n", + run_time_sec); + + return bitstream_manager; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h new file mode 100644 index 000000000..58afd42fb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h @@ -0,0 +1,26 @@ +/******************************************************************** + * Header file for build_device_bitstream.cpp + *******************************************************************/ +#ifndef BUILD_DEVICE_BITSTREAM_H +#define BUILD_DEVICE_BITSTREAM_H + +#include +#include "bitstream_manager.h" +#include "vpr_types.h" +#include "module_manager.h" +#include "circuit_library.h" +#include "mux_library.h" +#include "rr_blocks.h" + +BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, + const t_arch& arch, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const vtr::Point& device_size, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const DeviceRRGSB& L_device_rr_gsb); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp new file mode 100644 index 000000000..b2dccc1eb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp @@ -0,0 +1,105 @@ +/******************************************************************** + * This file includes functions to build bitstream from routing multiplexers + * which are based on different technology + *******************************************************************/ +#include "vtr_assert.h" + +#include "mux_utils.h" +#include "fpga_x2p_types.h" + +#include "build_mux_bitstream.h" + +/******************************************************************** + * Find the default path id of a MUX + * This is applied when the path id specified is DEFAULT_PATH_ID, + * which is not correlated to the MUX implementation + * This function is binding the default path id to the implemented structure + * 1. If the MUX has a constant input, the default path id will be + * directed to the last input of the MUX, which is the constant input + * 2. If the MUX does not have a constant input, the default path id + * will the first input of the MUX. + * + * Restriction: + * we assume the default path is the first input of the MUX + * Change if this is not what you want + *******************************************************************/ +size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size) { + size_t default_path_id; + + if (TRUE == circuit_lib.mux_add_const_input(mux_model)) { + default_path_id = mux_size; /* When there is a constant input, use the last path */ + } else { + default_path_id = DEFAULT_MUX_PATH_ID; /* When there is no constant input, use the default one */ + } + + return default_path_id; +} + +/******************************************************************** + * This function generates bitstream for a CMOS routing multiplexer + * Thanks to MuxGraph object has already describe the internal multiplexing + * structure, bitstream generation is simply done by routing the signal + * to from a given input to the output + * All the memory bits can be generated by an API of MuxGraph + * + * To be generic, this function only returns a vector bit values + * without touching an bitstream-relate data structure + *******************************************************************/ +static +std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxLibrary& mux_lib, + const size_t& mux_size, + const int& path_id) { + /* Note that the size of implemented mux could be different than the mux size we see here, + * due to the constant inputs + * We will find the input size of implemented MUX and fetch the graph-based representation in MUX library + */ + size_t implemented_mux_size = find_mux_implementation_num_inputs(circuit_lib, mux_model, mux_size); + MuxId mux_graph_id = mux_lib.mux_graph(mux_model, implemented_mux_size); + const MuxGraph mux_graph = mux_lib.mux_graph(mux_graph_id); + + size_t datapath_id = path_id; + + /* Find the path_id related to the implementation */ + if (DEFAULT_PATH_ID == path_id) { + datapath_id = find_mux_default_path_id(circuit_lib, mux_model, implemented_mux_size); + } else { + VTR_ASSERT( datapath_id < mux_size); + } + + /* We should have only one output for this MUX! */ + VTR_ASSERT(1 == mux_graph.outputs().size()); + + /* Generate the memory bits */ + return mux_graph.decode_memory_bits(MuxInputId(datapath_id), mux_graph.output_id(mux_graph.outputs()[0])); +} + +/******************************************************************** + * This function generates bitstream for a routing multiplexer + * supporting both CMOS and ReRAM multiplexer designs + *******************************************************************/ +std::vector build_mux_bitstream(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxLibrary& mux_lib, + const size_t& mux_size, + const int& path_id) { + std::vector mux_bitstream; + + switch (circuit_lib.design_tech_type(mux_model)) { + case SPICE_MODEL_DESIGN_CMOS: + mux_bitstream = build_cmos_mux_bitstream(circuit_lib, mux_model, mux_lib, mux_size, path_id); + break; + case SPICE_MODEL_DESIGN_RRAM: + /* TODO: ReRAM MUX needs a different bitstream generation strategy */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid design technology for circuit model (%s)!\n", + __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); + exit(1); + } + return mux_bitstream; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h new file mode 100644 index 000000000..227eabdf9 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h @@ -0,0 +1,21 @@ +/******************************************************************** + * Header file for build_mux_bitstream.cpp + *******************************************************************/ +#ifndef BUILD_MUX_BITSTREAM_H +#define BUILD_MUX_BITSTREAM_H + +#include +#include "circuit_library.h" +#include "mux_library.h" + +size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const size_t& mux_size); + +std::vector build_mux_bitstream(const CircuitLibrary& circuit_lib, + const CircuitModelId& mux_model, + const MuxLibrary& mux_lib, + const size_t& mux_size, + const int& path_id); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp new file mode 100644 index 000000000..d244aa312 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp @@ -0,0 +1,214 @@ +/******************************************************************** + * This file includes functions to build bitstream from global routing + * architecture of a mapped FPGA fabric + * We decode the bitstream from configuration of routing multiplexers + * which locate in global routing architecture + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "util.h" +#include "mux_utils.h" +#include "fpga_x2p_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +#include "build_mux_bitstream.h" +#include "build_routing_bitstream.h" + +/******************************************************************** + * This function generates bitstream for a routing multiplexer + * This function will identify if a node indicates a routing multiplexer + * If not a routing multiplexer, no bitstream is needed here + * If yes, we will generate the bitstream for the routing multiplexer + *******************************************************************/ +static +void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const RRGSB& rr_gsb, + t_rr_node* cur_rr_node, + const std::vector& drive_rr_nodes, + const int& switch_index) { + /* Check current rr_node is CHANX or CHANY*/ + VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); + + /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); + + /* Find out which routing path is used in this MUX */ + int path_id = DEFAULT_PATH_ID; + for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { + if (drive_rr_nodes[inode] == &(L_rr_node[cur_rr_node->prev_node])) { + path_id = (int)inode; + break; + } + } + + /* Ensure that our path id makes sense! */ + VTR_ASSERT( (DEFAULT_PATH_ID == path_id) + || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) + ); + + /* Generate bitstream depend on both technology and structure of this MUX */ + std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); + + /* Add the bistream to the bitstream manager */ + for (const bool& bit : mux_bitstream) { + bitstream_manager.add_bit(bit); + } +} + +/******************************************************************** + * This function generates bitstream for an interconnection, + * i.e., a routing multiplexer, in a Switch Block + * This function will identify if a node indicates a routing multiplexer + * If not a routing multiplexer, no bitstream is needed here + * If yes, we will generate the bitstream for the routing multiplexer + *******************************************************************/ +static +void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const RRGSB& rr_gsb, + const e_side& chan_side, + const size_t& chan_node_id) { + + std::vector drive_rr_nodes; + + /* Get the node */ + t_rr_node* cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id); + + /* Determine if the interc lies inside a channel wire, that is interc between segments */ + if (false == rr_gsb.is_sb_node_passing_wire(chan_side, chan_node_id)) { + for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { + drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); + } + /* Special: if there are zero-driver nodes. We skip here */ + if (0 == drive_rr_nodes.size()) { + return; + } + } + + if ( (0 == drive_rr_nodes.size()) + || (0 == drive_rr_nodes.size()) ) { + /* No bitstream generation required by a special direct connection*/ + return; + } else if (1 < drive_rr_nodes.size()) { + /* This is a routing multiplexer! Generate bitstream */ + build_switch_block_mux_bitstream(bitstream_manager, module_manager, + circuit_lib, mux_lib, rr_switches, L_rr_node, + rr_gsb, cur_rr_node, drive_rr_nodes, + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); + } /*Nothing should be done else*/ +} + +/******************************************************************** + * This function generates bitstream for a Switch Block + * and add it to the bitstream manager + * This function will spot all the routing multiplexers in a Switch Block + * using a simple but effective rule: + * The fan-in of each output node. + * If there are more than 2 fan-in, there is a routing multiplexer + * + * Note that the output nodes typically spread over all the sides of a Switch Block + * So, we will iterate over that. + *******************************************************************/ +static +void build_switch_block_bitstream(BitstreamManager& bitstream_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const RRGSB& rr_sb) { + /* TODO: Create a block for the bitstream which corresponds to the Switch block */ + + /* Iterate over all the multiplexers */ + for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { + VTR_ASSERT( (CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) + || (CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); + /* Only output port indicates a routing multiplexer */ + if (OUT_PORT != rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + build_switch_block_interc_bitstream(bitstream_manager, module_manager, + circuit_lib, mux_lib, rr_switches, L_rr_node, + rr_sb, side_manager.get_side(), itrack); + } + } +} + +/******************************************************************** + * Top-level function to create bitstream for global routing architecture + * Two major tasks: + * 1. Generate bitstreams for Switch Blocks + * 2. Generate bitstreams for both X-direction and Y-direction Connection Blocks + *******************************************************************/ +void build_routing_bitstream(BitstreamManager& bitstream_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const DeviceRRGSB& L_device_rr_gsb) { + + /* Generate bitstream for each switch blocks + * To organize the bitstream in blocks, we create a block for each switch block + * and give names which are same as they are in top-level module managers + */ + vpr_printf(TIO_MESSAGE_INFO, + "Generating bitstream for Switch blocks...\n"); + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + build_switch_block_bitstream(bitstream_manager, module_manager, + circuit_lib, mux_lib, rr_switches, L_rr_node, + rr_gsb); + } + } + + /* Generate bitstream for each connection blocks + * To organize the bitstream in blocks, we create a block for each connection block + * and give names which are same as they are in top-level module managers + */ + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks ...\n"); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + /* X - channels [1...nx][0..ny]*/ + if ((TRUE == is_cb_exist(CHANX, ix, iy)) + &&(true == rr_gsb.is_cb_exist(CHANX))) { + /* + fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, + rr_gsb, CHANX, + cur_sram_orgz_info); + */ + } + /* Y - channels [1...ny][0..nx]*/ + if ((TRUE == is_cb_exist(CHANY, ix, iy)) + &&(true == rr_gsb.is_cb_exist(CHANY))) { + /* + fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, + rr_gsb, CHANY, + cur_sram_orgz_info); + */ + } + } + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h new file mode 100644 index 000000000..62935d901 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h @@ -0,0 +1,23 @@ +/******************************************************************** + * Header file for build_routing_bitstream.cpp + *******************************************************************/ +#ifndef BUILD_ROUTING_BITSTREAM_H +#define BUILD_ROUTING_BITSTREAM_H + +#include +#include "bitstream_manager.h" +#include "vpr_types.h" +#include "module_manager.h" +#include "circuit_library.h" +#include "mux_library.h" +#include "rr_blocks.h" + +void build_routing_bitstream(BitstreamManager& bitstream_manager, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const DeviceRRGSB& L_device_rr_gsb); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp index b35f2d152..ef1a03830 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp @@ -51,7 +51,8 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, #endif /* Module Graph builder formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, "\nStart building module graphs for FPGA fabric...\n"); + vpr_printf(TIO_MESSAGE_INFO, + "\nStart building module graphs for FPGA fabric...\n"); /* Module manager to be built */ ModuleManager module_manager; @@ -135,8 +136,9 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, clock_t t_end = clock(); float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Building module graphs took %g seconds\n", run_time_sec); - + vpr_printf(TIO_MESSAGE_INFO, + "Building module graphs took %g seconds\n", + run_time_sec); return module_manager; } From 97193794c41077acd5cd6d6b00de4bc51084cba0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Oct 2019 21:27:42 -0600 Subject: [PATCH 330/482] correct bugs in organizing child modules in top-level module --- .../SRC/fpga_x2p/module_builder/build_top_module_memory.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp index 2566286da..39bf029ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp @@ -233,12 +233,12 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, } /* TOP side I/Os */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + for (size_t ix = device_size.x() - 2; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); } /* LEFT side I/Os */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + for (size_t iy = device_size.y() - 2; iy >= 1; --iy) { io_coords[LEFT].push_back(vtr::Point(0, iy)); } From c38513c838c1b1914a8c9600872dd7c624030adf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Oct 2019 22:49:24 -0600 Subject: [PATCH 331/482] add local encoder support in bitstream generation refactoring --- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 18 +++++-- vpr7_x2p/vpr/SRC/device/mux_graph.h | 6 ++- .../bitstream/build_mux_bitstream.cpp | 51 ++++++++++++++++++- 3 files changed, 67 insertions(+), 8 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 23230ae74..b54dcd0c2 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -192,6 +192,14 @@ size_t MuxGraph::num_memory_bits_at_level(const size_t& level) const { return mem_lookup_[level].size(); } +/* Return memory id at level */ +std::vector MuxGraph::memories_at_level(const size_t& level) const { + /* need to check if the graph is valid or not */ + VTR_ASSERT_SAFE(valid_level(level)); + VTR_ASSERT_SAFE(valid_mux_graph()); + return mem_lookup_[level]; +} + /* Find the number of nodes at a given level in the MUX graph */ size_t MuxGraph::num_nodes_at_level(const size_t& level) const { /* validate the level numbers */ @@ -533,10 +541,10 @@ MuxNodeId MuxGraph::node_id(const size_t& node_level, const size_t& node_index_a } /* Decode memory bits based on an input id and an output id */ -std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id, - const MuxOutputId& output_id) const { +vtr::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id, + const MuxOutputId& output_id) const { /* initialize the memory bits: TODO: support default value */ - std::vector mem_bits(mem_ids_.size(), false); + vtr::vector mem_bits(mem_ids_.size(), false); /* valid the input and output */ VTR_ASSERT_SAFE(valid_input_id(input_id)); @@ -575,9 +583,9 @@ std::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id, MuxMemId mem = edge_mem_ids_[edge]; VTR_ASSERT_SAFE (valid_mem_id(mem)); if (true == edge_inv_mem_[edge]) { - mem_bits[size_t(mem)] = false; + mem_bits[mem] = false; } else { - mem_bits[size_t(mem)] = true; + mem_bits[mem] = true; } /* each edge must have 1 fan-out */ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h index 18fc5464c..014e0a59b 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.h @@ -83,6 +83,8 @@ class MuxGraph { size_t num_memory_bits() const; /* Find the number of SRAMs at a level in the MUX graph */ size_t num_memory_bits_at_level(const size_t& level) const; + /* Return memory id at level */ + std::vector memories_at_level(const size_t& level) const; /* Find the number of nodes at a given level in the MUX graph */ size_t num_nodes_at_level(const size_t& level) const; /* Find the level of a node */ @@ -122,8 +124,8 @@ class MuxGraph { * This function will start from the input node * and do a forward propagation until reaching the output node */ - std::vector decode_memory_bits(const MuxInputId& input_id, - const MuxOutputId& output_id) const; + vtr::vector decode_memory_bits(const MuxInputId& input_id, + const MuxOutputId& output_id) const; /* Find the input node that the memory bits will route an output node to * This function backward propagate from the output node to an input node * assuming the memory bits are applied diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp index b2dccc1eb..644fe730e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp @@ -3,9 +3,12 @@ * which are based on different technology *******************************************************************/ #include "vtr_assert.h" +#include "vtr_vector.h" #include "mux_utils.h" +#include "decoder_library_utils.h" #include "fpga_x2p_types.h" +#include "fpga_x2p_utils.h" #include "build_mux_bitstream.h" @@ -74,7 +77,53 @@ std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, VTR_ASSERT(1 == mux_graph.outputs().size()); /* Generate the memory bits */ - return mux_graph.decode_memory_bits(MuxInputId(datapath_id), mux_graph.output_id(mux_graph.outputs()[0])); + vtr::vector raw_bitstream = mux_graph.decode_memory_bits(MuxInputId(datapath_id), mux_graph.output_id(mux_graph.outputs()[0])); + + std::vector mux_bitstream; + for (const bool& bit : mux_bitstream) { + mux_bitstream.push_back(bit); + } + + /* Consider local encoder support, we need further encode the bitstream */ + if (false == circuit_lib.mux_use_local_encoder(mux_model)) { + return mux_bitstream; + } + + /* Clear the mux_bitstream, we need to apply encoding */ + mux_bitstream.clear(); + + /* Encode the memory bits level by level, + * One local encoder is used for each level of multiplexers + */ + for (const size_t& level : mux_graph.levels()) { + /* The encoder will convert the path_id to a binary number + * For example: when path_id=3 (use the 4th input), using a 4-input encoder + * the sram_bits will be the 4-digit binary number of 3: 0100 + */ + std::vector encoder_data; + for (size_t mem_index = 0; mem_index < mux_graph.memories_at_level(level).size(); ++mem_index) { + /* Conversion rule: true = 1, false = 0 */ + if (true == raw_bitstream[mux_graph.memories_at_level(level)[mem_index]]) { + encoder_data.push_back(mem_index); + } + } + /* There should be at most one '1' */ + VTR_ASSERT( (0 == encoder_data.size()) || (1 == encoder_data.size())); + /* Convert to encoded bits */ + std::vector encoder_addr; + if (0 == encoder_data.size()) { + encoder_addr = my_itobin_vec(0, find_mux_local_decoder_addr_size(mux_graph.memories_at_level(level).size())); + } else { + VTR_ASSERT(1 == encoder_data.size()); + encoder_addr = my_itobin_vec(encoder_data[0], find_mux_local_decoder_addr_size(mux_graph.memories_at_level(level).size())); + } + /* Build final mux bitstream */ + for (const size_t& bit : encoder_addr) { + mux_bitstream.push_back((bool)bit); + } + } + + return mux_bitstream; } /******************************************************************** From a1cd1ea8b4dfe7b6f70df8dfd138fa397011d320 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Oct 2019 22:51:24 -0600 Subject: [PATCH 332/482] fix travis error for MacOS --- .travis.yml | 2 +- .travis/common.sh | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index 562418241..196e35e40 100644 --- a/.travis.yml +++ b/.travis.yml @@ -66,7 +66,7 @@ matrix: - os: osx osx_image: xcode10.2 # we target latest MacOS Mojave sudo: true - compiler: gcc-4.9 # Use clang instead of gcc in MacOS + compiler: gcc-6 # Use clang instead of gcc in MacOS addons: homebrew: packages: diff --git a/.travis/common.sh b/.travis/common.sh index d5a157049..9110a94b4 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -31,12 +31,12 @@ function end_section() { # For Mac OS, we use g++ and gcc as default compilers if [[ $TRAVIS_OS_NAME == 'osx' ]]; then - export CC=gcc-4.9 - export CXX=g++-4.9 + export CC=gcc-6 + export CXX=g++-6 # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / + sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From 1ee7dd80b2f86b9d58b89faf7e232febbe9a01d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Oct 2019 22:52:08 -0600 Subject: [PATCH 333/482] remove MacOS header file installation --- .travis/common.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/common.sh b/.travis/common.sh index 9110a94b4..071652090 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -36,7 +36,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted + #sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From cc63adf6e0ead56eaf1c0dbffe457326aa9e7778 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 09:36:36 -0600 Subject: [PATCH 334/482] bring back MacOS header file package installation in Travis --- .travis/common.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/common.sh b/.travis/common.sh index 071652090..9110a94b4 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -36,7 +36,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - #sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted + sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From 0b687669c8ab30bc6ffbd6e8538f057b26e431ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 10:42:12 -0600 Subject: [PATCH 335/482] affliate configuration bitstream to sb blocks --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 17 ++++++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 5 ++ .../fpga_x2p/base/fpga_x2p_reserved_words.h | 13 +++++ .../bitstream/build_device_bitstream.cpp | 2 +- .../bitstream/build_routing_bitstream.cpp | 51 ++++++++++++++----- .../bitstream/build_routing_bitstream.h | 1 + .../module_builder/build_grid_modules.cpp | 5 +- .../module_builder/build_memory_modules.cpp | 5 +- .../module_builder/build_routing_modules.cpp | 13 +++-- 9 files changed, 89 insertions(+), 23 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 43beec5a2..ae644c2c2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -734,6 +734,22 @@ std::string generate_grid_block_module_name(const std::string& prefix, return module_name; } +/********************************************************************* + * Generate the instance name for a configurable memory module in a Switch Block + ********************************************************************/ +std::string generate_sb_memory_instance_name(const std::string& prefix, + const e_side& sb_side, + const size_t& track_id, + const std::string& postfix) { + std::string instance_name(prefix); + instance_name += std::string("_") + Side(sb_side).to_string(); + instance_name += std::string("_track_") + std::to_string(track_id); + instance_name += postfix; + + return instance_name; +} + + /********************************************************************* * Generate the instance name of a grid block **********************************************************************/ @@ -753,7 +769,6 @@ std::string generate_grid_block_instance_name(const std::string& prefix, return module_name; } - /********************************************************************* * Generate the module name of a physical block * To ensure a unique name for each physical block inside the graph of complex blocks diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index a602dc4be..716b6e594 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -76,6 +76,11 @@ std::string generate_switch_block_module_name(const vtr::Point& coordina std::string generate_connection_block_module_name(const t_rr_type& cb_type, const vtr::Point& coordinate); +std::string generate_sb_memory_instance_name(const std::string& prefix, + const e_side& sb_side, + const size_t& track_id, + const std::string& postfix); + std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& height, const e_side& side, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h new file mode 100644 index 000000000..870df00ae --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h @@ -0,0 +1,13 @@ +/******************************************************************** + * This file includes all the reserved words that are used in + * naming module, blocks, instances and cells in FPGA X2P support, + * including: + * Verilog generation, SPICE generation and bitstream generation + *******************************************************************/ +#ifndef FPGA_X2P_RESERVED_WORDS_H +#define FPGA_X2P_RESERVED_WORDS_H + +constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; +constexpr char* MEMORY_MODULE_POSTFIX = "_mem"; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp index 5acf7fe33..4d82facba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp @@ -77,7 +77,7 @@ BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); /* Create bitstream from routing architectures */ - build_routing_bitstream(bitstream_manager, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb); + build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb); /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp index d244aa312..d0f34349d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp @@ -10,6 +10,7 @@ #include "vtr_assert.h" #include "util.h" #include "mux_utils.h" +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_types.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" @@ -25,12 +26,12 @@ *******************************************************************/ static void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& mux_mem_block, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const std::vector& rr_switches, t_rr_node* L_rr_node, - const RRGSB& rr_gsb, t_rr_node* cur_rr_node, const std::vector& drive_rr_nodes, const int& switch_index) { @@ -60,9 +61,18 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, /* Generate bitstream depend on both technology and structure of this MUX */ std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); + /* Find the module in module manager and ensure the bitstream size matches! */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); + ModuleId mux_mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module)); + ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name()); + VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width()); + /* Add the bistream to the bitstream manager */ for (const bool& bit : mux_bitstream) { - bitstream_manager.add_bit(bit); + ConfigBitId config_bit = bitstream_manager.add_bit(bit); + /* Link the memory bits to the mux mem block */ + bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); } } @@ -75,6 +85,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, *******************************************************************/ static void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& sb_configurable_block, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, @@ -105,10 +116,14 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, /* No bitstream generation required by a special direct connection*/ return; } else if (1 < drive_rr_nodes.size()) { + /* Create the block denoting the memory instances that drives this node in Switch Block */ + std::string mem_block_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string("")); + ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); + bitstream_manager.add_child_block(sb_configurable_block, mux_mem_block); /* This is a routing multiplexer! Generate bitstream */ - build_switch_block_mux_bitstream(bitstream_manager, module_manager, + build_switch_block_mux_bitstream(bitstream_manager, mux_mem_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, - rr_gsb, cur_rr_node, drive_rr_nodes, + cur_rr_node, drive_rr_nodes, cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); } /*Nothing should be done else*/ } @@ -126,27 +141,28 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, *******************************************************************/ static void build_switch_block_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& sb_configurable_block, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const std::vector& rr_switches, t_rr_node* L_rr_node, - const RRGSB& rr_sb) { - /* TODO: Create a block for the bitstream which corresponds to the Switch block */ + const RRGSB& rr_gsb) { /* Iterate over all the multiplexers */ - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - VTR_ASSERT( (CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) - || (CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + VTR_ASSERT( (CHANX == rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type) + || (CHANY == rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type)); /* Only output port indicates a routing multiplexer */ - if (OUT_PORT != rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { + if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { continue; } - build_switch_block_interc_bitstream(bitstream_manager, module_manager, + build_switch_block_interc_bitstream(bitstream_manager, sb_configurable_block, + module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, - rr_sb, side_manager.get_side(), itrack); + rr_gsb, side_manager.get_side(), itrack); } } } @@ -158,6 +174,7 @@ void build_switch_block_bitstream(BitstreamManager& bitstream_manager, * 2. Generate bitstreams for both X-direction and Y-direction Connection Blocks *******************************************************************/ void build_routing_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& top_configurable_block, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, @@ -175,7 +192,13 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - build_switch_block_bitstream(bitstream_manager, module_manager, + /* Create a block for the bitstream which corresponds to the Switch block */ + vtr::Point sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + ConfigBlockId sb_configurable_block = bitstream_manager.add_block(generate_switch_block_module_name(sb_coord)); + /* Set switch block as a child of top block */ + bitstream_manager.add_child_block(top_configurable_block, sb_configurable_block); + + build_switch_block_bitstream(bitstream_manager, sb_configurable_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, rr_gsb); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h index 62935d901..eaf9aec5d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h @@ -13,6 +13,7 @@ #include "rr_blocks.h" void build_routing_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& top_configurable_block, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 7a84fbac1..7df5f5e77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -16,6 +16,7 @@ #include "globals.h" /* Header files for FPGA X2P tool suite */ +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_types.h" #include "fpga_x2p_utils.h" @@ -338,7 +339,7 @@ void build_primitive_block_module(ModuleManager& module_manager, add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); /* Add the associated memory module as a child of primitive module */ - std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix)); + std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(MEMORY_MODULE_POSTFIX)); ModuleId memory_module = module_manager.find_module(memory_module_name); /* Vectors to record all the memory modules have been added @@ -551,7 +552,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, cur_interc->circuit_model, fan_in, - std::string(verilog_mem_posfix)); + std::string(MEMORY_MODULE_POSTFIX)); ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index 54bde223b..d040fdc53 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -20,6 +20,7 @@ /* FPGA-X2P context header files */ #include "spice_types.h" +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" @@ -586,7 +587,7 @@ void build_mux_memory_module(ModuleManager& module_manager, /* Generate module name */ std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string(verilog_mem_posfix)); + std::string(MEMORY_MODULE_POSTFIX)); /* Get the sram ports from the mux */ std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); @@ -671,7 +672,7 @@ void build_memory_modules(ModuleManager& module_manager, VTR_ASSERT( 1 == sram_models.size() ); /* Create the module name for the memory block */ - std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(verilog_mem_posfix)); + std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX)); /* Create a Verilog module for the memories used by the circuit model */ build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 3635ef47e..2eebbce62 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -13,6 +13,7 @@ #include "util.h" #include "device_coordinator.h" +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_types.h" #include "fpga_x2p_naming.h" @@ -226,6 +227,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager, const std::vector>& grids, const std::vector& rr_switches, const e_side& chan_side, + const size_t& chan_node_id, t_rr_node* cur_rr_node, const std::vector& drive_rr_nodes, const size_t& switch_index, @@ -291,12 +293,17 @@ void build_switch_block_mux_module(ModuleManager& module_manager, /* Instanciate memory modules */ /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); ModuleId mem_module = module_manager.find_module(mem_module_name); VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); size_t mem_instance_id = module_manager.num_instance(sb_module, mem_module); module_manager.add_child_module(sb_module, mem_module); + /* Give an instance name: this name should be consistent with the block name given in bitstream manager, + * If you want to bind the bitstream generation to modules + */ + std::string mem_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string("")); + module_manager.set_child_instance_name(sb_module, mem_module, mem_instance_id, mem_instance_name); /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ add_module_nets_between_logic_and_memory_sram_bus(module_manager, sb_module, @@ -355,7 +362,7 @@ void build_switch_block_interc_modules(ModuleManager& module_manager, /* Print the multiplexer, fan_in >= 2 */ build_switch_block_mux_module(module_manager, sb_module, rr_gsb, circuit_lib, - grids, rr_switches, chan_side, cur_rr_node, + grids, rr_switches, chan_side, chan_node_id, cur_rr_node, drive_rr_nodes, cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], input_port_to_module_nets); @@ -756,7 +763,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, /* Instanciate memory modules */ /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(verilog_mem_posfix)); + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); ModuleId mem_module = module_manager.find_module(mem_module_name); VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); From cb147c1180d5b1b94babf712ad88e1a36580f20d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 10:44:40 -0600 Subject: [PATCH 336/482] try to fix MacOS in travisCI --- .travis.yml | 3 +-- .travis/common.sh | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 196e35e40..a93e425cc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -64,7 +64,7 @@ matrix: - zip - qt5-default - os: osx - osx_image: xcode10.2 # we target latest MacOS Mojave + osx_image: xcode11.2 # we target latest MacOS Mojave sudo: true compiler: gcc-6 # Use clang instead of gcc in MacOS addons: @@ -77,7 +77,6 @@ matrix: - fontconfig - git - gcc@6 - - gcc@4.9 - gawk - icarus-verilog - libxml++ diff --git a/.travis/common.sh b/.travis/common.sh index 9110a94b4..071652090 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -36,7 +36,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted + #sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From 4b7a9dfa63809ff95135143cd6507d74b679670a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 13:06:48 -0600 Subject: [PATCH 337/482] add instance name correlation between module and bitstream generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 42 +++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 12 + .../fpga_x2p/base/fpga_x2p_reserved_words.h | 1 + .../bitstream/build_device_bitstream.cpp | 2 +- .../bitstream/build_routing_bitstream.cpp | 215 +++++++++++++++--- .../bitstream/build_routing_bitstream.h | 1 + .../build_module_graph_utils.cpp | 23 -- .../module_builder/build_module_graph_utils.h | 5 - .../module_builder/build_routing_modules.cpp | 21 +- 9 files changed, 259 insertions(+), 63 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index ae644c2c2..84681c64b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -8,7 +8,9 @@ #include "vtr_assert.h" #include "sides.h" +#include "vpr_types.h" #include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" #include "circuit_library_utils.h" #include "fpga_x2p_naming.h" @@ -372,6 +374,28 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, return port_name; } +/********************************************************************* + * Generate the port name for a Grid + * This is a wrapper function for generate_port_name() + * which can automatically decode the port name by the pin side and height + *********************************************************************/ +std::string generate_grid_side_port_name(const std::vector>& grids, + const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id) { + /* Output the pins on the side*/ + size_t height = find_grid_pin_height(grids, coordinate, pin_id); + if (1 != grids[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { + Side side_manager(side); + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", + __FILE__, __LINE__, + coordinate.x(), coordinate.y(), height, side_manager.c_str(), pin_id); + exit(1); + } + return generate_grid_port_name(coordinate, height, side, pin_id, true); +} + /********************************************************************* * Generate the port name for a reserved sram port, i.e., BLB/WL port * When port_type is BLB, a string denoting to the reserved BLB port is generated @@ -742,13 +766,29 @@ std::string generate_sb_memory_instance_name(const std::string& prefix, const size_t& track_id, const std::string& postfix) { std::string instance_name(prefix); - instance_name += std::string("_") + Side(sb_side).to_string(); + instance_name += Side(sb_side).to_string(); instance_name += std::string("_track_") + std::to_string(track_id); instance_name += postfix; return instance_name; } +/********************************************************************* + * Generate the instance name for a configurable memory module in a Connection Block + ********************************************************************/ +std::string generate_cb_memory_instance_name(const std::string& prefix, + const std::vector>& grids, + const vtr::Point& coordinate, + const e_side& cb_side, + const size_t& pin_id, + const std::string& postfix) { + std::string instance_name(prefix); + + instance_name += generate_grid_side_port_name(grids, coordinate, cb_side, pin_id); + instance_name += postfix; + + return instance_name; +} /********************************************************************* * Generate the instance name of a grid block diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 716b6e594..225d34094 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -81,12 +81,24 @@ std::string generate_sb_memory_instance_name(const std::string& prefix, const size_t& track_id, const std::string& postfix); +std::string generate_cb_memory_instance_name(const std::string& prefix, + const std::vector>& grids, + const vtr::Point& coordinate, + const e_side& cb_side, + const size_t& pin_id, + const std::string& postfix); + std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& height, const e_side& side, const size_t& pin_id, const bool& for_top_netlist); +std::string generate_grid_side_port_name(const std::vector>& grids, + const vtr::Point& coordinate, + const e_side& side, + const size_t& pin_id); + std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type); std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h index 870df00ae..4bf842c23 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h @@ -8,6 +8,7 @@ #define FPGA_X2P_RESERVED_WORDS_H constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; +constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* MEMORY_MODULE_POSTFIX = "_mem"; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp index 4d82facba..986c65cb8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp @@ -77,7 +77,7 @@ BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); /* Create bitstream from routing architectures */ - build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb); + build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, grids, rr_switches, L_rr_node, L_device_rr_gsb); /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp index d0f34349d..c6fd9f056 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp @@ -59,7 +59,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, ); /* Generate bitstream depend on both technology and structure of this MUX */ - std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); + std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); /* Find the module in module manager and ensure the bitstream size matches! */ std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); @@ -141,7 +141,7 @@ void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, *******************************************************************/ static void build_switch_block_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& sb_configurable_block, + const ConfigBlockId& sb_config_block, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, @@ -159,7 +159,7 @@ void build_switch_block_bitstream(BitstreamManager& bitstream_manager, if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { continue; } - build_switch_block_interc_bitstream(bitstream_manager, sb_configurable_block, + build_switch_block_interc_bitstream(bitstream_manager, sb_config_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, rr_gsb, side_manager.get_side(), itrack); @@ -167,6 +167,178 @@ void build_switch_block_bitstream(BitstreamManager& bitstream_manager, } } +/******************************************************************** + * This function generates bitstream for a routing multiplexer + * in a Connection block + * This function will identify if a node indicates a routing multiplexer + * If not a routing multiplexer, no bitstream is needed here + * If yes, we will generate the bitstream for the routing multiplexer + *******************************************************************/ +static +void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& mux_mem_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + t_rr_node* src_rr_node) { + /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ + int switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find drive_rr_nodes*/ + size_t datapath_mux_size = (size_t)(src_rr_node->num_drive_rr_nodes); + + /* Configuration bits for MUX*/ + int path_id = DEFAULT_PATH_ID; + for (size_t inode = 0; inode < datapath_mux_size; ++inode) { + if (src_rr_node->drive_rr_nodes[inode] == &(L_rr_node[src_rr_node->prev_node])) { + path_id = (int)inode; + break; + } + } + + /* Ensure that our path id makes sense! */ + VTR_ASSERT( (DEFAULT_PATH_ID == path_id) + || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) + ); + + /* Generate bitstream depend on both technology and structure of this MUX */ + std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); + + /* Find the module in module manager and ensure the bitstream size matches! */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); + ModuleId mux_mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module)); + ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name()); + VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width()); + + /* Add the bistream to the bitstream manager */ + for (const bool& bit : mux_bitstream) { + ConfigBitId config_bit = bitstream_manager.add_bit(bit); + /* Link the memory bits to the mux mem block */ + bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); + } +} + + +/******************************************************************** + * This function generates bitstream for an interconnection, + * i.e., a routing multiplexer, in a Connection Block + * This function will identify if a node indicates a routing multiplexer + * If not a routing multiplexer, no bitstream is needed here + * If yes, we will generate the bitstream for the routing multiplexer + *******************************************************************/ +static +void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& cb_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const RRGSB& rr_gsb, + const e_side& cb_ipin_side, + const size_t& ipin_index) { + + t_rr_node* src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); + if (1 == src_rr_node->fan_in) { + /* No bitstream generation required by a special direct connection*/ + } else if (1 < src_rr_node->fan_in) { + /* Create the block denoting the memory instances that drives this node in Switch Block */ + vtr::Point ipin_coord(src_rr_node->xlow, src_rr_node->ylow); + std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, grids, ipin_coord, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), src_rr_node->ptc_num, std::string("")); + ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); + bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block); + /* This is a routing multiplexer! Generate bitstream */ + build_connection_block_mux_bitstream(bitstream_manager, mux_mem_block, + module_manager, circuit_lib, mux_lib, rr_switches, + L_rr_node, src_rr_node); + } /*Nothing should be done else*/ +} + +/******************************************************************** + * This function generates bitstream for a Connection Block + * and add it to the bitstream manager + * This function will spot all the routing multiplexers in a Connection Block + * using a simple but effective rule: + * The fan-in of each output node. + * If there are more than 2 fan-in, there is a routing multiplexer + * + * Note that the output nodes are the IPIN rr node in a Connection Block + * So, we will iterate over that. + *******************************************************************/ +static +void build_connection_block_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& cb_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const RRGSB& rr_gsb, + const t_rr_type& cb_type) { + + /* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */ + std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); + + for (size_t side = 0; side < cb_sides.size(); ++side) { + enum e_side cb_ipin_side = cb_sides[side]; + Side side_manager(cb_ipin_side); + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + build_connection_block_interc_bitstream(bitstream_manager, cb_configurable_block, + module_manager, circuit_lib, mux_lib, + grids, rr_switches, L_rr_node, + rr_gsb, + cb_ipin_side, inode); + } + } +} + +/******************************************************************** + * Create bitstream for a X-direction or Y-direction Connection Blocks + *******************************************************************/ +static +void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, + const ConfigBlockId& top_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, + const DeviceRRGSB& L_device_rr_gsb, + const t_rr_type& cb_type) { + + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + /* Create a block for the bitstream which corresponds to the Switch block */ + vtr::Point cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + ConfigBlockId cb_configurable_block = bitstream_manager.add_block(generate_connection_block_module_name(cb_type, cb_coord)); + /* Set switch block as a child of top block */ + bitstream_manager.add_child_block(top_configurable_block, cb_configurable_block); + + build_connection_block_bitstream(bitstream_manager, cb_configurable_block, module_manager, + circuit_lib, mux_lib, grids, rr_switches, L_rr_node, + rr_gsb, cb_type); + } + } +} + /******************************************************************** * Top-level function to create bitstream for global routing architecture * Two major tasks: @@ -178,6 +350,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb) { @@ -208,30 +381,16 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, * To organize the bitstream in blocks, we create a block for each connection block * and give names which are same as they are in top-level module managers */ - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks ...\n"); + vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-directionConnection blocks ...\n"); + + build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, + circuit_lib, mux_lib, grids, rr_switches, L_rr_node, + L_device_rr_gsb, CHANX); + + vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-directionConnection blocks ...\n"); + + build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, + circuit_lib, mux_lib, grids, rr_switches, L_rr_node, + L_device_rr_gsb, CHANY); - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - /* X - channels [1...nx][0..ny]*/ - if ((TRUE == is_cb_exist(CHANX, ix, iy)) - &&(true == rr_gsb.is_cb_exist(CHANX))) { - /* - fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, - rr_gsb, CHANX, - cur_sram_orgz_info); - */ - } - /* Y - channels [1...ny][0..nx]*/ - if ((TRUE == is_cb_exist(CHANY, ix, iy)) - &&(true == rr_gsb.is_cb_exist(CHANY))) { - /* - fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, - rr_gsb, CHANY, - cur_sram_orgz_info); - */ - } - } - } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h index eaf9aec5d..e22e3322d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h @@ -17,6 +17,7 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp index f58296e11..241b5f631 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp @@ -9,29 +9,6 @@ #include "fpga_x2p_pbtypes_utils.h" #include "build_module_graph_utils.h" -/********************************************************************* - * Generate the port name for a Grid - * This is a wrapper function for generate_port_name() - * which can automatically decode the port name by the pin side and height - *********************************************************************/ -std::string generate_grid_side_port_name(const std::vector>& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - size_t height = find_grid_pin_height(grids, coordinate, pin_id); - if (1 != grids[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { - Side side_manager(side); - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", - __FILE__, __LINE__, - coordinate.x(), coordinate.y(), height, side_manager.c_str(), pin_id); - exit(1); - } - return generate_grid_port_name(coordinate, height, side, pin_id, true); -} - - /******************************************************************** * Find input port of a buffer/inverter module ********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h index d4816c8e0..a1610632b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h @@ -13,11 +13,6 @@ #include "module_manager.h" #include "circuit_library.h" -std::string generate_grid_side_port_name(const std::vector>& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id); - ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 2eebbce62..a015bbd2c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -693,8 +693,10 @@ void build_connection_block_mux_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::vector>& grids, const std::vector& rr_switches, - t_rr_node* cur_rr_node, + const e_side& cb_ipin_side, + const size_t& ipin_index, const std::map& input_port_to_module_nets) { + t_rr_node* cur_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); /* Check current rr_node is an input pin of a CLB */ VTR_ASSERT(IPIN == cur_rr_node->type); @@ -770,6 +772,13 @@ void build_connection_block_mux_module(ModuleManager& module_manager, size_t mem_instance_id = module_manager.num_instance(cb_module, mem_module); module_manager.add_child_module(cb_module, mem_module); + /* Give an instance name: this name should be consistent with the block name given in bitstream manager, + * If you want to bind the bitstream generation to modules + */ + vtr::Point ipin_coord(cur_rr_node->xlow, cur_rr_node->ylow); + std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, grids, ipin_coord, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), cur_rr_node->ptc_num, std::string("")); + module_manager.set_child_instance_name(cb_module, mem_module, mem_instance_id, mem_instance_name); + /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ add_module_nets_between_logic_and_memory_sram_bus(module_manager, cb_module, mux_module, mux_instance_id, @@ -794,8 +803,10 @@ void build_connection_block_interc_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::vector>& grids, const std::vector& rr_switches, - t_rr_node* src_rr_node, + const e_side& cb_ipin_side, + const size_t& ipin_index, const std::map& input_port_to_module_nets) { + t_rr_node* src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); if (1 > src_rr_node->fan_in) { return; /* This port has no driver, skip it */ } else if (1 == src_rr_node->fan_in) { @@ -807,7 +818,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager, build_connection_block_mux_module(module_manager, cb_module, rr_gsb, cb_type, circuit_lib, grids, rr_switches, - src_rr_node, + cb_ipin_side, ipin_index, input_port_to_module_nets); } /*Nothing should be done else*/ } @@ -967,7 +978,7 @@ void build_connection_block_module(ModuleManager& module_manager, build_connection_block_interc_modules(module_manager, cb_module, rr_gsb, cb_type, circuit_lib, grids, rr_switches, - rr_gsb.get_ipin_node(cb_ipin_side, inode), + cb_ipin_side, inode, input_port_to_module_nets); } } @@ -1029,7 +1040,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager, * We will skip those modules */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if ( (TRUE != is_cb_exist(CHANX, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) || (true != rr_gsb.is_cb_exist(cb_type))) { continue; } From fc2562fc6c77136db20ba423e772813a3b10aa43 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 13:08:10 -0600 Subject: [PATCH 338/482] change travis to an older version of XCode/MacOS but rather stable --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index a93e425cc..ddf8f247a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -64,7 +64,7 @@ matrix: - zip - qt5-default - os: osx - osx_image: xcode11.2 # we target latest MacOS Mojave + osx_image: xcode9.4.1 # we target latest MacOS Mojave sudo: true compiler: gcc-6 # Use clang instead of gcc in MacOS addons: From 3310bac65b0eccdcfbf61768224976a97346228a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 21:49:47 -0600 Subject: [PATCH 339/482] refactored grid bitstream generation --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 18 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 4 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.c | 38 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 4 + .../fpga_x2p/base/fpga_x2p_reserved_words.h | 5 + .../bitstream/build_device_bitstream.cpp | 4 + .../bitstream/build_grid_bitstream.cpp | 751 ++++++++++++++++++ .../fpga_x2p/bitstream/build_grid_bitstream.h | 22 + .../bitstream/build_lut_bitstream.cpp | 457 +++++++++++ .../fpga_x2p/bitstream/build_lut_bitstream.h | 34 + .../module_builder/build_grid_modules.cpp | 15 +- .../module_builder/build_top_module.cpp | 7 +- 12 files changed, 1352 insertions(+), 7 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 84681c64b..2091cb8ba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -790,6 +790,24 @@ std::string generate_cb_memory_instance_name(const std::string& prefix, return instance_name; } +/********************************************************************* + * Generate the instance name for a configurable memory module in a + * physical block of a grid + ********************************************************************/ +std::string generate_pb_memory_instance_name(const std::string& prefix, + t_pb_graph_pin* pb_graph_pin, + const std::string& postfix) { + std::string instance_name(prefix); + instance_name += std::string(pb_graph_pin->parent_node->pb_type->name); + instance_name += std::string("_"); + instance_name += std::string(pb_graph_pin->port->name); + instance_name += std::string("_"); + instance_name += std::to_string(pb_graph_pin->pin_number); + instance_name += postfix; + + return instance_name; +} + /********************************************************************* * Generate the instance name of a grid block **********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 225d34094..2d4f08f08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -88,6 +88,10 @@ std::string generate_cb_memory_instance_name(const std::string& prefix, const size_t& pin_id, const std::string& postfix); +std::string generate_pb_memory_instance_name(const std::string& prefix, + t_pb_graph_pin* pb_graph_pin, + const std::string& postfix); + std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& height, const e_side& side, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c index b1c25acdc..45de820d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c @@ -3205,6 +3205,25 @@ void get_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb, return; } +/******************************************************************** + * Find the vpack_net_num of all the input pins of a LUT physical pb + *******************************************************************/ +std::vector find_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb) { + std::vector lut_pin_net; + + /* Check */ + VTR_ASSERT (1 == lut_phy_pb->pb_graph_node->num_input_ports); + lut_pin_net.resize(lut_phy_pb->pb_graph_node->num_input_pins[0]); + + /* Fill the array */ + for (size_t ipin = 0; ipin < lut_pin_net.size(); ++ipin) { + int inode = lut_phy_pb->pb_graph_node->input_pins[0][ipin].rr_node_index_physical_pb; + lut_pin_net[ipin] = lut_phy_pb->rr_graph->rr_node[inode].vpack_net_num; + } + + return lut_pin_net; +} + /* Get the vpack_net_num of all the input pins of a LUT physical pb */ void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb, int* num_lut_pin, int** lut_pin_net) { @@ -3225,6 +3244,25 @@ void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb, return; } + +/******************************************************************** + * Get the vpack_net_num of all the input pins of a LUT physical pb + *******************************************************************/ +std::vector find_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block) { + /* Ensure there is only one pin in the LUT logical block */ + VTR_ASSERT (NULL == lut_logical_block->model->inputs[0].next); + + std::vector lut_pin_nets(lut_logical_block->model->inputs[0].size); + + /* Fill the array */ + for (size_t ipin = 0; ipin < lut_pin_nets.size(); ++ipin) { + lut_pin_nets[ipin] = lut_logical_block->input_nets[0][ipin]; + } + + return lut_pin_nets; +} + + /* Get the vpack_net_num of all the input pins of a LUT physical pb */ void get_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block, int* num_lut_pin, int** lut_pin_net) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index c019beb80..27d473508 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -247,12 +247,16 @@ void alloc_and_load_phy_pb_children_for_one_mapped_block(t_pb* cur_pb, void get_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb, int* num_lut_pin, int** lut_pin_net); +std::vector find_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb); + void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb, int* num_lut_pin, int** lut_pin_net); void get_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block, int* num_lut_pin, int** lut_pin_net); +std::vector find_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block); + void rec_reset_pb_type_temp_placement_index(t_pb_type* cur_pb_type); void rec_reset_pb_type_phy_pb_type(t_pb_type* cur_pb_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h index 4bf842c23..a48fb9080 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h @@ -7,6 +7,11 @@ #ifndef FPGA_X2P_RESERVED_WORDS_H #define FPGA_X2P_RESERVED_WORDS_H +/* Grid naming constant strings */ +constexpr char* GRID_MODULE_NAME_PREFIX = "grid_"; + +/* Memory naming constant strings */ +constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* MEMORY_MODULE_POSTFIX = "_mem"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp index 986c65cb8..378171707 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp @@ -12,6 +12,7 @@ #include "fpga_x2p_naming.h" +#include "build_grid_bitstream.h" #include "build_routing_bitstream.h" #include "build_device_bitstream.h" @@ -76,6 +77,9 @@ BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, std::string top_block_name = generate_fpga_top_module_name(); ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); + /* Create bitstream from grids */ + build_grid_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, device_size, grids); + /* Create bitstream from routing architectures */ build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, grids, rr_switches, L_rr_node, L_device_rr_gsb); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp new file mode 100644 index 000000000..cadaecf6e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp @@ -0,0 +1,751 @@ +/******************************************************************** + * This file includes functions that are used for building bitstreams + * for grids (CLBs, heterogenerous blocks, I/Os, etc.) + *******************************************************************/ +#include + +#include "vtr_assert.h" +#include "vtr_vector.h" + +#include "util.h" +#include "mux_utils.h" +#include "vpr_types.h" +#include "globals.h" + +#include "circuit_library_utils.h" + +#include "fpga_x2p_reserved_words.h" +#include "fpga_x2p_types.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" + +#include "build_mux_bitstream.h" +#include "build_lut_bitstream.h" +#include "build_grid_bitstream.h" + +/******************************************************************** + * Decode mode bits "01..." to a bitstream vector + *******************************************************************/ +static +std::vector generate_mode_select_bitstream(const std::string& mode_bits) { + std::vector mode_select_bitstream; + + for (size_t i = 0; i < mode_bits.length(); ++i) { + /* Error out for unexpected bits */ + if ( ('0' != mode_bits[i]) && ('1' != mode_bits[i]) ) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid mode_bits(%s)!\n", + __FILE__, __LINE__, mode_bits.c_str()); + exit(1); + } + mode_select_bitstream.push_back('1' == mode_bits[i]); + } + + return mode_select_bitstream; +} + +/******************************************************************** + * Generate bitstream for a primitive node and add it to bitstream manager + *******************************************************************/ +static +void build_primitive_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + t_phy_pb* primitive_pb, + t_pb_type* primitive_pb_type) { + + /* Ensure a valid physical pritimive pb */ + if (NULL == primitive_pb_type) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid primitive_pb_type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Asserts */ + if (NULL != primitive_pb) { + VTR_ASSERT (primitive_pb->pb_graph_node->pb_type->phy_pb_type == primitive_pb_type); + } + + CircuitModelId primitive_model = primitive_pb_type->circuit_model; + VTR_ASSERT(CircuitModelId::INVALID() != primitive_model); + VTR_ASSERT( (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) + || (SPICE_MODEL_HARDLOGIC == circuit_lib.model_type(primitive_model)) + || (SPICE_MODEL_FF == circuit_lib.model_type(primitive_model)) ); + + /* Find SRAM ports for mode-selection */ + std::vector primitive_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, primitive_model); + + /* We may have a port for mode select or not. */ + VTR_ASSERT( (0 == primitive_mode_select_ports.size()) + || (1 == primitive_mode_select_ports.size()) ); + + /* Generate bitstream for mode-select ports */ + if (0 == primitive_mode_select_ports.size()) { + return; /* Nothing to do, return directly */ + } + + std::vector mode_select_bitstream; + if (NULL != primitive_pb) { + mode_select_bitstream = generate_mode_select_bitstream(std::string(primitive_pb->mode_bits)); + } else { /* get default mode_bits */ + mode_select_bitstream = generate_mode_select_bitstream(std::string(primitive_pb_type->mode_bits)); + } + + /* Ensure the length of bitstream matches the side of memory circuits */ + std::vector sram_models = find_circuit_sram_models(circuit_lib, primitive_model); + VTR_ASSERT(1 == sram_models.size()); + std::string mem_block_name = generate_memory_module_name(circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX)); + ModuleId mem_module = module_manager.find_module(mem_block_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name()); + VTR_ASSERT(mode_select_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width()); + + /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */ + ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name); + bitstream_manager.add_child_block(parent_configurable_block, mem_block); + + /* Add the bitstream to the bitstream manager */ + for (const bool& bit : mode_select_bitstream) { + ConfigBitId config_bit = bitstream_manager.add_bit(bit); + /* Link the memory bits to the mux mem block */ + bitstream_manager.add_bit_to_block(mem_block, config_bit); + } +} + +/******************************************************************** + * Generate bitstream for a LUT and add it to bitstream manager + * This function supports both single-output and fracturable LUTs + *******************************************************************/ +static +void build_lut_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_phy_pb* lut_pb, + t_pb_type* lut_pb_type) { + + /* Ensure a valid physical pritimive pb */ + if (NULL == lut_pb_type) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid lut_pb_type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Asserts */ + if (NULL != lut_pb) { + VTR_ASSERT (lut_pb->pb_graph_node->pb_type->phy_pb_type == lut_pb_type); + } + + CircuitModelId lut_model = lut_pb_type->circuit_model; + VTR_ASSERT (CircuitModelId::INVALID() != lut_model); + VTR_ASSERT (SPICE_MODEL_LUT == circuit_lib.model_type(lut_model)); + + /* Find the input ports for LUT size, this is used to decode the LUT memory bits! */ + std::vector model_input_ports = circuit_lib.model_ports_by_type(lut_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == model_input_ports.size()); + size_t lut_size = circuit_lib.port_size(model_input_ports[0]); + + /* Find SRAM ports for truth tables and mode-selection */ + std::vector lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model); + std::vector lut_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, lut_model); + /* We should always 1 regular sram port, where truth table is loaded to */ + VTR_ASSERT(1 == lut_regular_sram_ports.size()); + /* We may have a port for mode select or not. This depends on if the LUT is fracturable or not */ + VTR_ASSERT( (0 == lut_mode_select_ports.size()) + || (1 == lut_mode_select_ports.size()) ); + + std::vector lut_bitstream; + /* Generate bitstream for the LUT */ + if ( (NULL == lut_pb) + || ((NULL != lut_pb && 0 == lut_pb->num_logical_blocks)) ) { + /* An empty pb means that this is an unused LUT, + * we give an empty truth table, which are full of default values (defined by users) + */ + for (size_t i = 0; i < circuit_lib.port_size(lut_regular_sram_ports[0]); ++i) { + VTR_ASSERT( (0 == circuit_lib.port_default_value(lut_regular_sram_ports[0])) + || (1 == circuit_lib.port_default_value(lut_regular_sram_ports[0])) ); + lut_bitstream.push_back(1 == circuit_lib.port_default_value(lut_regular_sram_ports[0])); + } + } else { + VTR_ASSERT (NULL != lut_pb); + /* Pre-allocate truth tables for a LUT, + * Note: for fracturable LUTs, there could be several truth tables + * since multiple functions are mapped to the same LUT but to different outputs + */ + std::vector truth_tables; + truth_tables.resize(lut_pb->num_logical_blocks); + + /* Find truth tables and decode them one by one + * Fracturable LUT may have multiple truth tables, + * which should be grouped in a unique one + * And then we derive the truth table + */ + for (int i = 0; i < lut_pb->num_logical_blocks; ++i) { + int mapped_logical_block_index = lut_pb->logical_block[i]; + /* For wired LUT we provide a default truth table */ + if (TRUE == lut_pb->is_wired_lut[i]) { + /* Build a post-routing lut truth table */ + std::vector lut_pin_nets = find_mapped_lut_phy_pb_input_pin_vpack_net_num(lut_pb); + truth_tables[i] = build_post_routing_wired_lut_truth_table(lut_pb->rr_graph->rr_node[lut_pb->lut_output_pb_graph_pin[i]->rr_node_index_physical_pb].vpack_net_num, lut_pin_nets.size(), lut_pin_nets); + } else { + /* For regular LUTs, we generate the truth tables */ + VTR_ASSERT (FALSE == lut_pb->is_wired_lut[i]); + VTR_ASSERT (VPACK_COMB == logical_block[mapped_logical_block_index].type); + /* Get the mapped vpack_net_num of this physical LUT pb */ + std::vector lut_pin_nets = find_mapped_lut_phy_pb_input_pin_vpack_net_num(lut_pb); + /* Consider LUT pin remapping when assign lut truth tables */ + /* Match truth table and post-routing results */ + truth_tables[i] = build_post_routing_lut_truth_table(&logical_block[mapped_logical_block_index], + lut_pin_nets.size(), lut_pin_nets); + } + /* Adapt truth table for a fracturable LUT + * TODO: Determine fixed input bits for this truth table: + * 1. input bits within frac_level (all '-' if not specified) + * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') + */ + truth_tables[i] = adapt_truth_table_for_frac_lut(circuit_lib, lut_pb->lut_output_pb_graph_pin[i], + truth_tables[i]); + } + /* Find MUX graph correlated to the LUT */ + MuxId lut_mux_id = mux_lib.mux_graph(lut_model, (size_t)pow(2., lut_size)); + const MuxGraph& mux_graph = mux_lib.mux_graph(lut_mux_id); + /* Ensure the LUT MUX has the expected input and SRAM port sizes */ + VTR_ASSERT(mux_graph.num_memory_bits() == lut_size); + VTR_ASSERT(mux_graph.num_inputs() == (size_t)pow(2., lut_size)); + /* Generate LUT bitstream */ + lut_bitstream = build_frac_lut_bitstream(circuit_lib, mux_graph, + lut_pb, truth_tables, + circuit_lib.port_default_value(lut_regular_sram_ports[0])); + } + + /* Generate bitstream for mode-select ports */ + if (0 != lut_mode_select_ports.size()) { + std::vector mode_select_bitstream; + if (NULL != lut_pb) { + mode_select_bitstream = generate_mode_select_bitstream(std::string(lut_pb->mode_bits)); + } else { /* get default mode_bits */ + mode_select_bitstream = generate_mode_select_bitstream(std::string(lut_pb_type->mode_bits)); + } + /* Conjunct the mode-select bitstream to the lut bitstream */ + for (const bool& bit : mode_select_bitstream) { + lut_bitstream.push_back(bit); + } + } + + /* Ensure the length of bitstream matches the side of memory circuits */ + std::vector sram_models = find_circuit_sram_models(circuit_lib, lut_model); + VTR_ASSERT(1 == sram_models.size()); + std::string mem_block_name = generate_memory_module_name(circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX)); + ModuleId mem_module = module_manager.find_module(mem_block_name); + VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); + ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name()); + VTR_ASSERT(lut_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width()); + + /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */ + ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name); + bitstream_manager.add_child_block(parent_configurable_block, mem_block); + + /* Add the bitstream to the bitstream manager */ + for (const bool& bit : lut_bitstream) { + ConfigBitId config_bit = bitstream_manager.add_bit(bit); + /* Link the memory bits to the mux mem block */ + bitstream_manager.add_bit_to_block(mem_block, config_bit); + } +} + + +/******************************************************************** + * This function generates bitstream for a programmable routing + * multiplexer which drives an output pin of physical_pb_graph_node and its the input_edges + * + * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins + * /|\ + * | + * input_pins, edges, output_pins + *******************************************************************/ +static +void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* physical_mode, + const int& path_id) { + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Select and print the SPICE netlist + */ + int fan_in = 0; + t_interconnect* cur_interc = NULL; + find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); + + if ((NULL == cur_interc) || (0 == fan_in)) { + /* No interconnection matched */ + return; + } + + enum e_interconnect interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); + switch (interc_type) { + case DIRECT_INTERC: + /* Nothing to do, return */ + break; + case COMPLETE_INTERC: + case MUX_INTERC: { + /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ + CircuitModelId mux_model = cur_interc->circuit_model; + VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.model_type(mux_model)); + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = fan_in; + VTR_ASSERT(true == valid_mux_implementation_num_inputs(datapath_mux_size)); + + /* Generate bitstream depend on both technology and structure of this MUX */ + std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); + + /* Create the block denoting the memory instances that drives this node in physical_block */ + std::string mem_block_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); + ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); + bitstream_manager.add_child_block(parent_configurable_block, mux_mem_block); + + /* Find the module in module manager and ensure the bitstream size matches! */ + std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); + ModuleId mux_mem_module = module_manager.find_module(mem_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module)); + ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name()); + VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width()); + + /* Add the bistream to the bitstream manager */ + for (const bool& bit : mux_bitstream) { + ConfigBitId config_bit = bitstream_manager.add_bit(bit); + /* Link the memory bits to the mux mem block */ + bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", + __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); + exit(1); + } +} + +/******************************************************************** + * This function generates bitstream for the programmable routing + * multiplexers in a pb_graph node + *******************************************************************/ +static +void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_pb_graph_node* physical_pb_graph_node, + t_phy_pb* physical_pb, + const e_spice_pb_port_type& pb_port_type, + t_mode* physical_mode) { + switch (pb_port_type) { + case SPICE_PB_PORT_INPUT: + for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { + /* If this is a idle block, we set 0 to the selected edge*/ + /* Get the selected edge of current pin*/ + int path_id; + if (NULL == physical_pb) { + path_id = DEFAULT_PATH_ID; + } else { + VTR_ASSERT(NULL != physical_pb); + t_rr_node* pb_rr_nodes = physical_pb->rr_graph->rr_node; + int node_index = physical_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; + int prev_node = pb_rr_nodes[node_index].prev_node; + /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = DEFAULT_PATH_ID; + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + VTR_ASSERT(DEFAULT_PATH_ID != path_id); + } + /* TODO: This should be done outside this function! + * Path id for the sdc generation + */ + pb_rr_nodes[node_index].id_path = path_id; + } + build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, + module_manager, circuit_lib, mux_lib, + &(physical_pb_graph_node->input_pins[iport][ipin]), + physical_mode, + path_id); + } + } + break; + case SPICE_PB_PORT_OUTPUT: + for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { + /* If this is a idle block, we set 0 to the selected edge*/ + /* Get the selected edge of current pin*/ + int path_id; + if (NULL == physical_pb) { + path_id = DEFAULT_PATH_ID; + } else { + VTR_ASSERT(NULL != physical_pb); + t_rr_node* pb_rr_nodes = physical_pb->rr_graph->rr_node; + int node_index = physical_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; + int prev_node = pb_rr_nodes[node_index].prev_node; + /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = DEFAULT_PATH_ID; + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + VTR_ASSERT(DEFAULT_PATH_ID != path_id); + } + /* TODO: This should be done outside this function! + * Path id for the sdc generation + */ + pb_rr_nodes[node_index].id_path = path_id; + } + build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, + module_manager, circuit_lib, mux_lib, + &(physical_pb_graph_node->output_pins[iport][ipin]), + physical_mode, + path_id); + } + } + break; + case SPICE_PB_PORT_CLOCK: + for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { + /* If this is a idle block, we set 0 to the selected edge*/ + /* Get the selected edge of current pin*/ + int path_id; + if (NULL == physical_pb) { + path_id = DEFAULT_PATH_ID; + } else { + VTR_ASSERT(NULL != physical_pb); + t_rr_node* pb_rr_nodes = physical_pb->rr_graph->rr_node; + int node_index = physical_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; + int prev_node = pb_rr_nodes[node_index].prev_node; + /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ + /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ + if (OPEN == prev_node) { + path_id = DEFAULT_PATH_ID; + } else { + /* Find the path_id */ + path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); + VTR_ASSERT(DEFAULT_PATH_ID != path_id); + } + /* TODO: This should be done outside this function! + * Path id for the sdc generation + */ + pb_rr_nodes[node_index].id_path = path_id; + } + build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, + module_manager, circuit_lib, mux_lib, + &(physical_pb_graph_node->clock_pins[iport][ipin]), + physical_mode, + path_id); + + } + } + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid pb port type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * This function generates bitstream for the programmable routing + * multiplexers in a pb_graph node + *******************************************************************/ +static +void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + t_pb_graph_node* physical_pb_graph_node, + t_phy_pb* physical_pb, + const int& physical_mode_index) { + /* Check if the pb_graph node is valid or not */ + if (NULL == physical_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid physical_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Assign current mode */ + t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]); + + /* We check output_pins of physical_pb_graph_node and its the input_edges + * Iterate over the interconnections between outputs of physical_pb_graph_node + * and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> physical_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, + module_manager, circuit_lib, mux_lib, + physical_pb_graph_node, physical_pb, + SPICE_PB_PORT_OUTPUT, physical_mode); + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Iterate over the interconnections between inputs of physical_pb_graph_node + * and inputs of child_pb_graph_node + * physical_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ipb++) { + for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; jpb++) { + t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb]); + /* branch on empty pb */ + t_phy_pb* child_pb = NULL; + if (NULL != physical_pb) { + child_pb = &(physical_pb->child_pbs[ipb][jpb]); + } + /* For each child_pb_graph_node input pins*/ + build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, + module_manager, circuit_lib, mux_lib, + child_pb_graph_node, child_pb, + SPICE_PB_PORT_INPUT, physical_mode); + /* For clock pins, we should do the same work */ + build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, + module_manager, circuit_lib, mux_lib, + child_pb_graph_node, child_pb, + SPICE_PB_PORT_CLOCK, physical_mode); + } + } +} + + +/******************************************************************** + * This function generates bitstream for a physical block, which is + * a child block of a grid + * This function will follow a recursive way in generating bitstreams + * It will follow the same sequence in visiting all the sub blocks + * in a physical as we did during module generation + * + * Note: if you want to bind your bitstream with a FPGA fabric generated by FPGA-X2P + * Please follow the same sequence in visiting pb_graph nodes!!! + * For more details, you may refer to function rec_build_physical_block_modules() + *******************************************************************/ +static +void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_configurable_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const e_side& border_side, + t_phy_pb* physical_pb, + t_pb_graph_node* physical_pb_graph_node) { + /* Get the physical pb_type that is linked to the pb_graph node */ + t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + /* Find the mode that define_idle_mode*/ + int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type)); + + /* Create a block for the physical block under the grid block in bitstream manager */ + std::string pb_block_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string pb_block_name = generate_physical_block_module_name(pb_block_name_prefix, physical_pb_type); + ConfigBlockId pb_configurable_block = bitstream_manager.add_block(pb_block_name); + bitstream_manager.add_child_block(parent_configurable_block, pb_configurable_block); + + /* Recursively finish all the child pb_types*/ + if (false == is_primitive_pb_type(physical_pb_type)) { + for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { + for (int jpb = 0; jpb < physical_pb_type->modes[physical_mode_index].pb_type_children[ipb].num_pb; ++jpb) { + t_phy_pb* child_pb = NULL; + /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ + if (NULL != physical_pb) { + child_pb = get_phy_child_pb_for_phy_pb_graph_node(physical_pb, ipb, jpb); + } + /* Go recursively */ + rec_build_physical_block_bitstream(bitstream_manager, pb_configurable_block, + module_manager, circuit_lib, mux_lib, + border_side, + child_pb, + &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb])); + } + } + } + + /* Check if this has defined a spice_model*/ + if (true == is_primitive_pb_type(physical_pb_type)) { + switch (physical_pb_type->class_type) { + case LUT_CLASS: + /* Special case for LUT !!! + * Mapped logical block information is stored in child_pbs of this pb!!! + */ + build_lut_bitstream(bitstream_manager, pb_configurable_block, + module_manager, circuit_lib, mux_lib, + physical_pb, physical_pb_type); + break; + case LATCH_CLASS: + case UNKNOWN_CLASS: + case MEMORY_CLASS: + /* For other types of blocks, we can apply a generic therapy */ + build_primitive_bitstream(bitstream_manager, pb_configurable_block, + module_manager, circuit_lib, + physical_pb, physical_pb_type); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Unknown class type of pb_type(%s)!\n", + __FILE__, __LINE__, physical_pb_type->name); + exit(1); + } + /* Finish for primitive node, return */ + return; + } + + /* Generate the bitstream for the interconnection in this physical block */ + build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block, + module_manager, circuit_lib, mux_lib, + physical_pb->pb_graph_node, physical_pb, physical_mode_index); +} + +/******************************************************************** + * This function generates bitstream for a grid, which could be a + * CLB, a heterogenerous block, an I/O, etc. + * Note that each grid may contain a number of physical blocks, + * this function will iterate over them + *******************************************************************/ +static +void build_physical_block_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& top_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const std::vector>& grids, + const vtr::Point& grid_coordinate, + const e_side& border_side) { + /* Create a block for the grid in bitstream manager */ + t_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type; + std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); + std::string grid_block_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), + IO_TYPE == grid_type, border_side, grid_coordinate); + ConfigBlockId grid_configurable_block = bitstream_manager.add_block(grid_block_name); + bitstream_manager.add_child_block(top_block, grid_configurable_block); + + /* Iterate over the capacity of the grid */ + for (int z = 0; z < grids[grid_coordinate.x()][grid_coordinate.y()].type->capacity; ++z) { + /* Get the top-level node of the pb_graph */ + t_pb_graph_node* top_pb_graph_node = grid_type->pb_graph_head; + VTR_ASSERT(NULL != top_pb_graph_node); + + /* Check in all the mapped blocks(clustered logic block), there is a match x,y,z*/ + t_block* mapped_block = search_mapped_block(grid_coordinate.x(), grid_coordinate.y(), z); + t_phy_pb* top_pb; + if (NULL != mapped_block) { + top_pb = (t_phy_pb*)mapped_block->phy_pb; + VTR_ASSERT(NULL != top_pb); + } + + /* Recursively traverse the pb_graph and generate bitstream */ + rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, + module_manager, circuit_lib, mux_lib, + border_side, + top_pb, top_pb_graph_node); + } +} + + +/******************************************************************** + * Top-level function of this file: + * Generate bitstreams for all the grids, including + * 1. core grids that sit in the center of the fabric + * 2. side grids (I/O grids) that sit in the borders for the fabric + *******************************************************************/ +void build_grid_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& top_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const vtr::Point& device_size, + const std::vector>& grids) { + + vpr_printf(TIO_MESSAGE_INFO, + "Generating bitstream for core grids...\n"); + + /* Generate bitstream for the core logic block one by one */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + /* Bypass EMPTY grid */ + if (EMPTY_TYPE == grids[ix][iy].type) { + continue; + } + /* Skip height > 1 tiles (mostly heterogeneous blocks) */ + if (0 < grids[ix][iy].offset) { + continue; + } + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE != grids[ix][iy].type); + /* Ensure a valid usage */ + VTR_ASSERT((0 == grids[ix][iy].usage)||(0 < grids[ix][iy].usage)); + /* Add a grid module to top_module*/ + vtr::Point grid_coord(ix, iy); + build_physical_block_bitstream(bitstream_manager, top_block, module_manager, + circuit_lib, mux_lib, grids, grid_coord, NUM_SIDES); + } + } + + vpr_printf(TIO_MESSAGE_INFO, + "Generating bitstream for I/O grids...\n"); + + /* Create the coordinate range for each side of FPGA fabric */ + std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; + std::map>> io_coordinates; + + /* TOP side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); + } + + /* RIGHT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); + } + + /* BOTTOM side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); + } + + /* LEFT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[LEFT].push_back(vtr::Point(0, iy)); + } + + /* Add instances of I/O grids to top_module */ + for (const e_side& io_side : io_sides) { + for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + /* Bypass EMPTY grid */ + if (EMPTY_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type) { + continue; + } + /* Skip height > 1 tiles (mostly heterogeneous blocks) */ + if (0 < grids[io_coordinate.x()][io_coordinate.y()].offset) { + continue; + } + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); + build_physical_block_bitstream(bitstream_manager, top_block, module_manager, + circuit_lib, mux_lib, grids, io_coordinate, io_side); + } + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h new file mode 100644 index 000000000..3568e4f29 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h @@ -0,0 +1,22 @@ +/******************************************************************** + * Header file for build_grid_bitstream.cpp + *******************************************************************/ +#ifndef BUILD_GRID_BITSTREAM_H +#define BUILD_GRID_BITSTREAM_H + +#include +#include "vtr_geometry.h" +#include "vpr_types.h" +#include "bitstream_manager.h" +#include "module_manager.h" +#include "circuit_library.h" +#include "mux_library.h" + +void build_grid_bitstream(BitstreamManager& bitstream_manager, + const ConfigBlockId& top_block, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, + const vtr::Point& device_size, + const std::vector>& grids); +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp new file mode 100644 index 000000000..7c22d1e0c --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp @@ -0,0 +1,457 @@ +/********************************************************************* + * This file includes functions that are used for building bitstreams + * for Look-Up Tables + ********************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "util.h" +#include "vpr_types.h" +#include "string_token.h" + +#include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" + +#include "build_lut_bitstream.h" + +/******************************************************************** + * Adapt the truth table from the short-wire connection + * from the input nets of a LUT to an output of a LUT + * + * LUT + * +-------------+ + * lut_input--->|----+ | + * | | | + * | +------->|---> lut_output + * | | + * +-------------+ + * + * In this case, LUT is configured as a wiring module + * This function will generate a truth for the wiring LUT + ********************************************************************/ +LutTruthTable build_post_routing_wired_lut_truth_table(const int& lut_output_vpack_net_num, + const size_t& lut_size, + const std::vector& lut_pin_vpack_net_num) { + LutTruthTable tt; + + /* There is always only one line in this truth table */ + tt.resize(1); + + /* Pre-allocate the truth table: + * Each truth table line is organized in BLIF format: + * |<---LUT size--->| + * < a string of 0 or 1> <0 or 1> + * The first of characters represent the input values of each LUT input + * Here, we add 2 characters, which denote the space and a digit (0|1) + * By default, we set all the inputs as don't care value '-' + * + * For more details, please refer to the BLIF format documentation + */ + tt[0].resize(lut_size, '-'); + /* Fill the truth table !!! */ + for (size_t inet = 0; inet < lut_size; ++inet) { + /* Find the vpack_num in the lut_input_pin, we fix it to be 1 */ + if (lut_output_vpack_net_num == lut_pin_vpack_net_num[inet]) { + tt[0][inet] = '1'; + } + } + tt[0] += std::string(" 1"); + + return tt; +} + +/******************************************************************** + * Provide the truth table of a mapped logical block + * 1. Reorgainze the truth table to be consistent with the mapped nets of a LUT + * 2. Allocate the truth table in a clean string and return + ********************************************************************/ +LutTruthTable build_post_routing_lut_truth_table(t_logical_block* mapped_logical_block, + const size_t& lut_size, + const std::vector& lut_pin_vpack_net_num) { + if (NULL == mapped_logical_block) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid mapped_logical_block!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Create a map between the lut net ids and logical block net ids */ + std::vector lut_to_lb_net_mapping(lut_size, OPEN); + /* Find nets mapped to a logical block */ + std::vector lb_pin_vpack_net_num = find_lut_logical_block_input_pin_vpack_net_num(mapped_logical_block); + /* Create a pin-to-pin net_num mapping */ + for (size_t inet = 0; inet < lut_size; ++inet) { + /* Bypass open nets */ + if (OPEN == lut_pin_vpack_net_num[inet]) { + continue; + } + VTR_ASSERT_SAFE (OPEN != lut_pin_vpack_net_num[inet]); + /* Find the position (offset) of each vpack_net_num in lb_pins */ + for (size_t jnet = 0; jnet < lb_pin_vpack_net_num.size(); ++jnet) { + if (lut_pin_vpack_net_num[inet] == lb_pin_vpack_net_num[jnet]) { + lut_to_lb_net_mapping[inet] = jnet; + break; + } + } + /* Not neccesary to find a one, some luts just share part of their pins */ + } + + /* Count the lines of truth table stored in the mapped logical block */ + struct s_linked_vptr* head = mapped_logical_block->truth_table; + + /* Convert the truth_tables stored in the mapped logical block */ + LutTruthTable truth_table; + + /* Handle the truth table pin remapping + * Note that we cannot simply copy the original truth table from the mapped logical block + * Due to the logic equivalence of LUT pins, the nets are not longer in the sequences + * that are defined in the original truth table + * An illustrative example: + * + * Original Truth Table Post VPR Truth Table + * + * +-------+ +-------+ + * net0 --->| | net1--->| | + * net1 --->| LUT | net0--->| LUT | + * ... | | ... | | + * +-------+ +-------+ + */ + while (head) { + /* Cache a line of truth table */ + std::string tt_line; + + /* Reorganize the original truth table */ + for (size_t inet = 0; inet < lut_size; ++inet) { + /* Open net implies a don't care, or some nets are not in the list */ + if ( (OPEN == lut_pin_vpack_net_num[inet]) + || (OPEN == lut_to_lb_net_mapping[inet])) { + tt_line.push_back('-'); + continue; + } + /* Find the desired truth table bit */ + tt_line.push_back(((char*)(head->data_vptr))[lut_to_lb_net_mapping[inet]]); + } + + /* Copy the last two characters from original truth table, which is not changed even after VPR implementation */ + int lb_truth_table_size = strlen((char*)(head->data_vptr)); + tt_line += std::string((char*)(head->data_vptr) + lb_truth_table_size - 2, 2); + + /* Add the line to truth table */ + truth_table.push_back(tt_line); + + /* Go to next line */ + head = head->next; + } + + return truth_table; +} + +/******************************************************************** + * Adapt truth table for a fracturable LUT + * Determine fixed input bits for this truth table: + * 1. input bits within frac_level (all '-' if not specified) + * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') + ********************************************************************/ +LutTruthTable adapt_truth_table_for_frac_lut(const CircuitLibrary& circuit_lib, + t_pb_graph_pin* lut_out_pb_graph_pin, + const LutTruthTable& truth_table) { + LutTruthTable adapt_truth_table; + + /* Find the output port of LUT that this logical block is mapped to */ + VTR_ASSERT(NULL != lut_out_pb_graph_pin); + /* find the corresponding SPICE model output port and assoicated lut_output_mask */ + CircuitPortId lut_model_output_port = lut_out_pb_graph_pin->port->circuit_model_port; + size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port); + + /* No adaption required for when the lut_frac_level is not set */ + if (size_t(OPEN) == lut_frac_level) { + return truth_table; + } + + /* Find the corresponding circuit model output port and assoicated lut_output_mask */ + size_t lut_output_mask = circuit_lib.port_lut_output_masks(lut_model_output_port)[lut_out_pb_graph_pin->pin_number]; + + /* Apply modification to the truth table */ + for (const std::string& tt_line : truth_table) { + /* Last two chars are fixed */ + size_t lut_size = tt_line.length() - 2; + /* Get the number of bits to be masked (modified) */ + int num_mask_bits = lut_size - lut_frac_level; + /* Check if we need to modify any bits */ + VTR_ASSERT(0 <= num_mask_bits); + if ( 0 == num_mask_bits ) { + continue; + } + /* Modify bits starting from lut_frac_level */ + /* Decode the lut_output_mask to LUT input codes */ + int temp = pow(2., num_mask_bits) - 1 - lut_output_mask; + std::vector mask_bits = my_itobin_vec(temp, num_mask_bits); + /* Copy the bits to the truth table line */ + std::string adapt_tt_line = tt_line; + for (const size_t& mask_bit : mask_bits) { + adapt_tt_line.insert(lut_frac_level, std::to_string(mask_bit)); + } + + /* Push to adapted truth table */ + adapt_truth_table.push_back(adapt_tt_line); + } + + return adapt_truth_table; +} + +/******************************************************************** + * Determine if the truth table of a LUT is a on-set or a off-set + *******************************************************************/ +static +bool lut_truth_table_use_on_set(const LutTruthTable& truth_table) { + bool on_set = false; + bool off_set = false; + + for (const std::string& tt_line : truth_table) { + switch (tt_line.back()) { + case '1': + on_set = true; + break; + case '0': + off_set = true; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid truth_table_line ending(=%c)!\n", + __FILE__, __LINE__, tt_line.back()); + exit(1); + } + } + + /* Prefer on_set if both are true */ + if (true == on_set && true == off_set) { + on_set = true; + off_set = false; + } + + return on_set; +} + +/******************************************************************** + * Complete a line in truth table with a given lut size + * Due to the size of truth table may be less than the lut size. + * i.e. in LUT-6 architecture, there exists LUT1-6 in technology-mapped netlists + * So, in truth table line, there may be 10- 1 + * In this case, we should complete it by --10- 1 + *******************************************************************/ +static +std::string complete_truth_table_line(const size_t& lut_size, + const std::string& input_truth_table_line) { + std::string ret; + + /* Split one line of truth table line*/ + StringToken string_tokenizer(input_truth_table_line); + std::vector tokens = string_tokenizer.split(' '); + /* Check, only 2 tokens*/ + /* Sometimes, the truth table is ' 0' or ' 1', which corresponds to a constant */ + if (1 == tokens.size()) { + /* restore the token[0]*/ + tokens.insert(tokens.begin(), std::string("-")); + } + + /* After processing, there should be 2 tokens. */ + VTR_ASSERT(2 == tokens.size()); + + /* Complete the truth table line*/ + size_t cover_len = tokens[0].length(); + VTR_ASSERT( (cover_len < lut_size) || (cover_len == lut_size) ); + + /* Copy the original truth table line */ + ret = tokens[0]; + + /* Add the number of '-' we should add in the back !!! */ + for (size_t j = cover_len; j < lut_size; ++j) { + ret.push_back('-'); + } + + /* Copy the original truth table line */ + ret.push_back(' '); + ret.append(tokens[1]); + + /* Check if the size of ret matches our expectation */ + VTR_ASSERT(lut_size + 2 == ret.size()); + + return ret; +} + +/******************************************************************** + * For each lut_bit_lines, we should recover the truth table, + * and then set the sram bits to "1" if the truth table defines so. + * Start_point: the position we start decode recursively + *******************************************************************/ +static +void rec_build_lut_bitstream_per_line(std::vector& lut_bitstream, + const size_t& lut_size, + const std::string& truth_table_line, + const size_t& start_point) { + std::string temp_line(truth_table_line); + + /* Check the length of sram bits and truth table line */ + VTR_ASSERT(lut_size + 2 == truth_table_line.length()); /* lut_size + space + '1' */ + + /* End of truth_table_line should be "space" and "1" */ + VTR_ASSERT( (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 1")) + || (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 0")) ); + + /* Make sure before start point there is no '-' */ + VTR_ASSERT(start_point < truth_table_line.length()); + for (size_t i = 0; i < start_point; ++i) { + VTR_ASSERT('-' != truth_table_line[i]); + } + + /* Configure sram bits recursively */ + for (size_t i = start_point; i < lut_size; ++i) { + if ('-' == truth_table_line[i]) { + /* if we find a dont_care, we don't do configure now but recursively*/ + /* '0' branch */ + temp_line[i] = '0'; + rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, temp_line, start_point + 1); + /* '1' branch */ + temp_line[i] = '1'; + rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, temp_line, start_point + 1); + return; + } + } + + /* TODO: Use MuxGraph to decode this!!! */ + /* Decode bitstream only when there are only 0 or 1 in the truth table */ + size_t sram_id = 0; + for (size_t i = 0; i < lut_size; ++i) { + /* Should be either '0' or '1' */ + switch (truth_table_line[i]) { + case '0': + /* We assume the 1-lut pass sram1 when input = 0 */ + sram_id += (size_t)pow(2., (double)(i)); + break; + case '1': + /* We assume the 1-lut pass sram0 when input = 1 */ + break; + case '-': + default : + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid truth_table bit(%c), should be [0|1|]!\n", + __FILE__, __LINE__, truth_table_line[i]); + exit(1); + } + } + /* Set the sram bit to '1'*/ + VTR_ASSERT(sram_id < lut_bitstream.size()); + if (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 1")) { + lut_bitstream[sram_id] = true; /* on set*/ + } else if (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 0")) { + lut_bitstream[sram_id] = false; /* off set */ + } else { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid truth_table_line ending(=%s)!\n", + __FILE__, __LINE__, truth_table_line.substr(lut_size, 2)); + exit(1); + } +} + + +/******************************************************************** + * Generate the bitstream for a single-output LUT with a given truth table + * As truth tables may come from different logic blocks, truth tables could be in on and off sets + * We first build a base SRAM bits, where different parts are set to tbe on/off sets + * Then, we can decode SRAM bits as regular process + *******************************************************************/ +static +std::vector build_single_output_lut_bitstream(const LutTruthTable& truth_table, + const MuxGraph& lut_mux_graph, + const size_t& default_sram_bit_value) { + size_t lut_size = lut_mux_graph.num_memory_bits(); + size_t bitstream_size = lut_mux_graph.num_inputs(); + std::vector lut_bitstream(bitstream_size, false); + LutTruthTable completed_truth_table; + bool on_set = false; + bool off_set = false; + + /* if No truth_table, do default*/ + if (0 == truth_table.size()) { + switch (default_sram_bit_value) { + case 0: + on_set = true; + off_set = false; + break; + case 1: + on_set = false; + off_set = true; + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid default_signal_init_value(=%lu)!\n", + __FILE__, __LINE__, default_sram_bit_value); + exit(1); + } + } else { + on_set = lut_truth_table_use_on_set(truth_table); + off_set = !on_set; + } + + /* Read in truth table lines, decode one by one */ + for (const std::string& tt_line : truth_table) { + /* Complete the truth table line by line*/ + completed_truth_table.push_back(complete_truth_table_line(lut_size, tt_line)); + } + + /* Initial all the bits in the bitstream */ + if (true == on_set) { + lut_bitstream.resize(bitstream_size, false); + } else if (true == off_set) { + lut_bitstream.resize(bitstream_size, true); + } + + for (const std::string& tt_line : completed_truth_table) { + /* Update the truth table, sram_bits */ + rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, tt_line, 0); + } + + return lut_bitstream; +} + +/******************************************************************** + * Generate bitstream for a fracturable LUT (also applicable to single-output LUT) + * Check type of truth table of each mapped logical block + * if it is on-set, we give a all 0 base bitstream + * if it is off-set, we give a all 1 base bitstream + *******************************************************************/ +std::vector build_frac_lut_bitstream(const CircuitLibrary& circuit_lib, + const MuxGraph& lut_mux_graph, + t_phy_pb* lut_pb, + const std::vector& truth_tables, + const size_t& default_sram_bit_value) { + /* Initialization */ + std::vector lut_bitstream(lut_mux_graph.num_inputs(), default_sram_bit_value); + + for (int ilb = 0; ilb < lut_pb->num_logical_blocks; ++ilb) { + /* Find the corresponding circuit model output port and assoicated lut_output_mask */ + CircuitPortId lut_model_output_port = lut_pb->lut_output_pb_graph_pin[ilb]->port->circuit_model_port; + size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port); + + /* Find the corresponding circuit model output port and assoicated lut_output_mask */ + size_t lut_output_mask = circuit_lib.port_lut_output_masks(lut_model_output_port)[lut_pb->lut_output_pb_graph_pin[ilb]->pin_number]; + + /* Decode lut sram bits */ + std::vector temp_bitstream = build_single_output_lut_bitstream(truth_tables[ilb], lut_mux_graph, default_sram_bit_value); + + /* Depending on the frac-level, we get the location(starting/end points) of sram bits */ + size_t length_of_temp_bitstream_to_copy = (size_t)pow(2., (double)(lut_frac_level)); + size_t bitstream_offset = length_of_temp_bitstream_to_copy * lut_output_mask; + /* Ensure the offset is in range */ + VTR_ASSERT(bitstream_offset < lut_bitstream.size()); + VTR_ASSERT(bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream.size()); + + /* Copy to the segment of bitstream */ + for (size_t bit = bitstream_offset; bit < bitstream_offset + length_of_temp_bitstream_to_copy; ++bit) { + lut_bitstream[bit] = temp_bitstream[bit]; + } + } + + return lut_bitstream; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h new file mode 100644 index 000000000..09e8ef37a --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h @@ -0,0 +1,34 @@ +/******************************************************************** + * Header file for build_lut_bitstream.cpp + ********************************************************************/ +#ifndef BUILD_LUT_BITSTREAM_H +#define BUILD_LUT_BITSTREAM_H + +#include +#include "circuit_library.h" +#include "mux_graph.h" +#include "vpr_types.h" + +/* Alias name for data structure of LUT truth table */ +typedef std::vector LutTruthTable; + +/* Declaration for functions */ +LutTruthTable build_post_routing_wired_lut_truth_table(const int& lut_output_vpack_net_num, + const size_t& lut_size, + const std::vector& lut_pin_vpack_net_num); + +LutTruthTable build_post_routing_lut_truth_table(t_logical_block* mapped_logical_block, + const size_t& lut_size, + const std::vector& lut_pin_vpack_net_num); + +LutTruthTable adapt_truth_table_for_frac_lut(const CircuitLibrary& circuit_lib, + t_pb_graph_pin* lut_out_pb_graph_pin, + const LutTruthTable& truth_table); + +std::vector build_frac_lut_bitstream(const CircuitLibrary& circuit_lib, + const MuxGraph& lut_mux_graph, + t_phy_pb* lut_pb, + const std::vector& truth_tables, + const size_t& default_sram_bit_value); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 7df5f5e77..f5ca6ce77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -277,7 +277,7 @@ void build_primitive_block_module(ModuleManager& module_manager, CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model; /* Generate the module name for this primitive pb_graph_node*/ - std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); + std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), io_side); std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); /* Create a module of the primitive LUT and register it to module manager */ @@ -353,6 +353,8 @@ void build_primitive_block_module(ModuleManager& module_manager, size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); /* Add the memory module as a child of primitive module */ module_manager.add_child_module(primitive_module, memory_module); + /* Set an instance name to bind to a block in bitstream generation */ + module_manager.set_child_instance_name(primitive_module, memory_module, memory_instance_id, memory_module_name); /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module, @@ -557,6 +559,11 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module); module_manager.add_child_module(pb_module, mux_mem_module); + /* Give an instance name: this name should be consistent with the block name given in bitstream manager, + * If you want to bind the bitstream generation to modules + */ + std::string mux_mem_instance_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); + module_manager.set_child_instance_name(pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name); /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */ add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, @@ -866,7 +873,7 @@ void rec_build_physical_block_modules(ModuleManager& module_manager, } /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); + std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), io_side); std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); /* Register the Verilog module in module manager */ @@ -994,12 +1001,12 @@ void build_grid_module(ModuleManager& module_manager, border_side); /* Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); + std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); ModuleId grid_module = module_manager.add_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix(grid_verilog_file_name_prefix); + std::string pb_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side); ModuleId pb_module = module_manager.find_module(pb_module_name); VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index 01af77409..ccb83fee1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -10,6 +10,7 @@ #include "vpr_types.h" #include "globals.h" +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_pbtypes_utils.h" @@ -95,7 +96,7 @@ size_t add_top_module_grid_instance(ModuleManager& module_manager, const e_side& border_side, const vtr::Point& grid_coord) { /* Find the module name for this type of grid */ - std::string grid_module_name_prefix(grid_verilog_file_name_prefix); + std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); ModuleId grid_module = module_manager.find_module(grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); @@ -404,7 +405,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, /* Collect source-related information */ /* Generate the grid module name by considering if it locates on the border */ vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); - std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); + std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), device_size, grids, grid_coordinate); ModuleId src_grid_module = module_manager.find_module(src_grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; @@ -556,7 +557,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, */ t_rr_node* instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); vtr::Point grid_coordinate(instance_ipin_node->xlow, instance_ipin_node->ylow); - std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(grid_verilog_file_name_prefix), device_size, grids, grid_coordinate); + std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), device_size, grids, grid_coordinate); ModuleId sink_grid_module = module_manager.find_module(sink_grid_module_name); VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; From db9beec77c59e430de99e4d1a5642782df177970 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 21:52:30 -0600 Subject: [PATCH 340/482] try to fix Travis MacOS issue --- .travis.yml | 5 +++-- .travis/common.sh | 6 +++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/.travis.yml b/.travis.yml index ddf8f247a..562418241 100644 --- a/.travis.yml +++ b/.travis.yml @@ -64,9 +64,9 @@ matrix: - zip - qt5-default - os: osx - osx_image: xcode9.4.1 # we target latest MacOS Mojave + osx_image: xcode10.2 # we target latest MacOS Mojave sudo: true - compiler: gcc-6 # Use clang instead of gcc in MacOS + compiler: gcc-4.9 # Use clang instead of gcc in MacOS addons: homebrew: packages: @@ -77,6 +77,7 @@ matrix: - fontconfig - git - gcc@6 + - gcc@4.9 - gawk - icarus-verilog - libxml++ diff --git a/.travis/common.sh b/.travis/common.sh index 071652090..1f39d6d50 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -31,12 +31,12 @@ function end_section() { # For Mac OS, we use g++ and gcc as default compilers if [[ $TRAVIS_OS_NAME == 'osx' ]]; then - export CC=gcc-6 - export CXX=g++-6 + export CC=gcc-4.9 + export CXX=g++-4.9 # export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH" # export PATH="/usr/local/opt/qt/bin:$PATH" # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h - #sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted + sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted else # For linux, we use g++-8 and gcc-8 as default compilers export CC=gcc-8 From ca2b836128a23989d2d06e867ee0a8d650d4cc91 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 25 Oct 2019 22:13:48 -0600 Subject: [PATCH 341/482] temporary remove MacOS from travis. Will bring back when debugged --- .travis.yml | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/.travis.yml b/.travis.yml index 562418241..b7256b307 100644 --- a/.travis.yml +++ b/.travis.yml @@ -63,25 +63,25 @@ matrix: - valgrind - zip - qt5-default - - os: osx - osx_image: xcode10.2 # we target latest MacOS Mojave - sudo: true - compiler: gcc-4.9 # Use clang instead of gcc in MacOS - addons: - homebrew: - packages: - - bison - - cmake - - ctags - - flex - - fontconfig - - git - - gcc@6 - - gcc@4.9 - - gawk - - icarus-verilog - - libxml++ - - qt5 +# - os: osx +# osx_image: xcode10.2 # we target latest MacOS Mojave +# sudo: true +# compiler: gcc-4.9 # Use clang instead of gcc in MacOS +# addons: +# homebrew: +# packages: +# - bison +# - cmake +# - ctags +# - flex +# - fontconfig +# - git +# - gcc@6 +# - gcc@4.9 +# - gawk +# - icarus-verilog +# - libxml++ +# - qt5 before_install: - source .travis/common.sh From 0a9c89be0b3edc7c528d3ad415cd74ae0273b43b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Oct 2019 12:41:23 -0600 Subject: [PATCH 342/482] add bitstream writers and start debugging --- .../SRC/fpga_x2p/base/bitstream_manager.cpp | 24 +++ .../vpr/SRC/fpga_x2p/base/bitstream_manager.h | 10 ++ .../fpga_x2p/base/bitstream_manager_utils.cpp | 37 +++++ .../fpga_x2p/base/bitstream_manager_utils.h | 10 ++ vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 21 ++- .../fpga_x2p/base/fpga_x2p_reserved_words.h | 4 + .../fpga_x2p/bitstream/bitstream_writer.cpp | 140 ++++++++++++++++++ .../SRC/fpga_x2p/bitstream/bitstream_writer.h | 13 ++ .../SRC/fpga_x2p/bitstream/fpga_bitstream.c | 1 - 9 files changed, 255 insertions(+), 5 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp index c26423b3e..10e6873f1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp @@ -36,6 +36,16 @@ std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const { return block_names_[block_id]; } +ConfigBlockId BitstreamManager::find_block(const std::string& block_name) const { + if (block_lookup_.find(block_name) != block_lookup_.end()) { + /* Find it, return the id */ + return block_lookup_.at(block_name); + } + /* Not found, return an invalid id */ + return ConfigBlockId::INVALID(); + +} + ConfigBlockId BitstreamManager::block_parent(const ConfigBlockId& block_id) const { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block_id)); @@ -79,6 +89,12 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { } ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { + /* Find if the name has been used. If used, return an invalid Id and report error! */ + std::map::iterator it = block_lookup_.find(block_name); + if (it != block_lookup_.end()) { + return ConfigBlockId::INVALID(); + } + ConfigBlockId block = ConfigBlockId(block_ids_.size()); /* Add a new bit, and allocate associated data structures */ block_ids_.push_back(block); @@ -139,3 +155,11 @@ bool BitstreamManager::valid_bit_id(const ConfigBitId& bit_id) const { bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const { return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]); } + +/****************************************************************************** + * Private Validators + ******************************************************************************/ +void BitstreamManager::invalidate_block_lookup() { + block_lookup_.clear(); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h index ac35b7539..1041d43d4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h @@ -35,6 +35,7 @@ #define BITSTREAM_MANAGER_H #include +#include #include "vtr_vector.h" #include "bitstream_manager_fwd.h" @@ -60,6 +61,9 @@ class BitstreamManager { /* Find a name of a block */ std::string block_name(const ConfigBlockId& block_id) const; + /* Find a block by name */ + ConfigBlockId find_block(const std::string& block_name) const; + /* Find the parent of a block */ ConfigBlockId block_parent(const ConfigBlockId& block_id) const; @@ -93,6 +97,9 @@ class BitstreamManager { bool valid_block_id(const ConfigBlockId& block_id) const; + private: /* Private Validators */ + void invalidate_block_lookup(); + private: /* Internal data */ /* Unique id of a block of bits in the Bitstream */ vtr::vector block_ids_; @@ -116,6 +123,9 @@ class BitstreamManager { vtr::vector bit_values_; /* value of a shared configuration bits in the Bitstream */ vtr::vector> shared_config_bit_values_; + + /* Fast look-up for block */ + std::map block_lookup_; }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp new file mode 100644 index 000000000..3428c96ad --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp @@ -0,0 +1,37 @@ +/******************************************************************** + * This file includes most utilized functions for data structure + * BitstreamManager + * + * Note: These functions are not generic enough so that they + * should NOT be a member function! + *******************************************************************/ +#include + +#include "vtr_assert.h" +#include "util.h" + +#include "bitstream_manager_utils.h" + +/******************************************************************** + * Recursively find the hierarchy of a block of bitstream manager + * Return a vector of the block ids, where the top-level block + * locates in the head, while the leaf block locates in the tail + * top, next, ... , block + *******************************************************************/ +std::vector find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, + const ConfigBlockId& block) { + std::vector block_hierarchy; + ConfigBlockId temp_block = block; + + /* Generate a tree of parent block */ + while (true == bitstream_manager.valid_block_id(temp_block)) { + block_hierarchy.push_back(temp_block); + /* Go to upper level */ + temp_block = bitstream_manager.block_parent(temp_block); + } + + /* Reverse the vector, so that top block stay in the first */ + std::reverse(block_hierarchy.begin(), block_hierarchy.end()); + + return block_hierarchy; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h new file mode 100644 index 000000000..2cf4276d0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h @@ -0,0 +1,10 @@ +#ifndef BITSTREAM_MANAGER_UTILS_H +#define BITSTREAM_MANAGER_UTILS_H + +#include +#include "bitstream_manager.h" + +std::vector find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, + const ConfigBlockId& block); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 7572b15fb..091abbf1e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -31,11 +31,13 @@ #include "mux_library_builder.h" #include "build_module_graph.h" #include "build_device_bitstream.h" +#include "bitstream_writer.h" #include "spice_api.h" #include "verilog_api.h" #include "fpga_bitstream.h" +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_api.h" @@ -85,14 +87,25 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Build bitstream database if needed */ BitstreamManager bitstream_manager; - if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) - &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) - &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { + if ( (TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) + && (FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) + && (FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { + bitstream_manager = build_device_bitstream(vpr_setup, Arch, module_manager, Arch.spice->circuit_lib, mux_lib, device_size, grids, rr_switches, rr_node, device_rr_gsb); - + /* Write bitstream to files */ + std::string bitstream_file_path; + + if (NULL == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file) { + bitstream_file_path = std::string(vpr_setup.FileNameOpts.CircuitName); + bitstream_file_path.append(BITSTREAM_XML_FILE_NAME_POSTFIX); + } else { + bitstream_file_path = vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file; + } + + write_arch_independent_bitstream_to_xml_file(bitstream_manager, bitstream_file_path); } /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h index a48fb9080..face6ad8f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h @@ -16,4 +16,8 @@ constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* MEMORY_MODULE_POSTFIX = "_mem"; + +/* Bitstream file strings */ +constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml"; + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp new file mode 100644 index 000000000..54a7fe351 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp @@ -0,0 +1,140 @@ +/******************************************************************** + * This file includes functions that output bitstream database + * to files in different formats + *******************************************************************/ +#include +#include +#include + +#include "vtr_assert.h" +#include "util.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +#include "bitstream_manager_utils.h" +#include "bitstream_writer.h" + +/******************************************************************** + * This function write header information to a bitstream file + *******************************************************************/ +static +void write_bitstream_xml_file_head(std::fstream& fp) { + check_file_handler(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << "" << std::endl; + fp << std::endl; +} + +/******************************************************************** + * Recursively write the bitstream of a block to a xml file + * This function will use a Depth-First Search in outputting bitstream + * for each block + * 1. For block with bits as children, we will output the XML lines + * 2. For block without bits/child blocks, we can return + * 3. For block with child blocks, we visit each child recursively + *******************************************************************/ +static +void rec_write_block_bitstream_to_xml_file(std::fstream& fp, + const BitstreamManager& bitstream_manager, + const ConfigBlockId& block) { + check_file_handler(fp); + + /* Dive to child blocks if this block has any */ + for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) { + rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, child_block); + } + + if (0 == bitstream_manager.block_bits(block).size()) { + return; + } + + /* Write the bits of this block */ + fp << "" << std::endl; + + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, block); + + /* Output hierarchy of this parent*/ + fp << "\t" << std::endl; + size_t hierarchy_counter = 0; + for (const ConfigBlockId& temp_block : block_hierarchy) { + fp << "\t\t" << std::endl; + hierarchy_counter++; + } + fp << "\t" << std::endl; + + /* Output child bits under this block */ + size_t bit_counter = 0; + fp << "\t" << std::endl; + for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) { + fp << "\t\t" << std::endl; + bit_counter++; + } + fp << "\t" << std::endl; + + fp << "" < +#include "bitstream_manager.h" + +void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, + const std::string& fname); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c index 6eb9a0af3..c2e0a03d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c @@ -394,7 +394,6 @@ void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup, /* Run bitstream generation and dump output file */ vpr_fpga_generate_bitstream(vpr_setup, Arch, circuit_name, bitstream_file_path.c_str(), cur_sram_orgz_info); - } From 7649d9228e3a4c0306cfff9df87700942bb93714 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Oct 2019 16:40:14 -0600 Subject: [PATCH 343/482] fixed bugs in refactored bitstream generation --- .../SRC/fpga_x2p/base/bitstream_manager.cpp | 22 ------ .../vpr/SRC/fpga_x2p/base/bitstream_manager.h | 9 --- .../fpga_x2p/base/bitstream_manager_utils.cpp | 17 +++++ .../fpga_x2p/base/bitstream_manager_utils.h | 2 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 4 +- .../fpga_x2p/bitstream/bitstream_writer.cpp | 9 ++- .../bitstream/build_grid_bitstream.cpp | 4 +- .../bitstream/build_lut_bitstream.cpp | 75 +++++++++++++++++-- .../bitstream/build_mux_bitstream.cpp | 10 ++- .../module_builder/build_mux_modules.cpp | 2 +- 10 files changed, 105 insertions(+), 49 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp index 10e6873f1..03b4c2e00 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp @@ -36,16 +36,6 @@ std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const { return block_names_[block_id]; } -ConfigBlockId BitstreamManager::find_block(const std::string& block_name) const { - if (block_lookup_.find(block_name) != block_lookup_.end()) { - /* Find it, return the id */ - return block_lookup_.at(block_name); - } - /* Not found, return an invalid id */ - return ConfigBlockId::INVALID(); - -} - ConfigBlockId BitstreamManager::block_parent(const ConfigBlockId& block_id) const { /* Ensure the input ids are valid */ VTR_ASSERT(true == valid_block_id(block_id)); @@ -89,12 +79,6 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { } ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { - /* Find if the name has been used. If used, return an invalid Id and report error! */ - std::map::iterator it = block_lookup_.find(block_name); - if (it != block_lookup_.end()) { - return ConfigBlockId::INVALID(); - } - ConfigBlockId block = ConfigBlockId(block_ids_.size()); /* Add a new bit, and allocate associated data structures */ block_ids_.push_back(block); @@ -156,10 +140,4 @@ bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const { return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]); } -/****************************************************************************** - * Private Validators - ******************************************************************************/ -void BitstreamManager::invalidate_block_lookup() { - block_lookup_.clear(); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h index 1041d43d4..57708face 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h @@ -61,9 +61,6 @@ class BitstreamManager { /* Find a name of a block */ std::string block_name(const ConfigBlockId& block_id) const; - /* Find a block by name */ - ConfigBlockId find_block(const std::string& block_name) const; - /* Find the parent of a block */ ConfigBlockId block_parent(const ConfigBlockId& block_id) const; @@ -97,9 +94,6 @@ class BitstreamManager { bool valid_block_id(const ConfigBlockId& block_id) const; - private: /* Private Validators */ - void invalidate_block_lookup(); - private: /* Internal data */ /* Unique id of a block of bits in the Bitstream */ vtr::vector block_ids_; @@ -123,9 +117,6 @@ class BitstreamManager { vtr::vector bit_values_; /* value of a shared configuration bits in the Bitstream */ vtr::vector> shared_config_bit_values_; - - /* Fast look-up for block */ - std::map block_lookup_; }; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp index 3428c96ad..24fad3fd3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp @@ -35,3 +35,20 @@ std::vector find_bitstream_manager_block_hierarchy(const Bitstrea return block_hierarchy; } + + +/******************************************************************** + * Find all the top-level blocks in a bitstream manager, + * which have no parents + *******************************************************************/ +std::vector find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager) { + std::vector top_blocks; + for (const ConfigBlockId& blk : bitstream_manager.blocks()) { + if (ConfigBlockId::INVALID() != bitstream_manager.block_parent(blk)) { + continue; + } + top_blocks.push_back(blk); + } + + return top_blocks; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h index 2cf4276d0..196aa0506 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h @@ -7,4 +7,6 @@ std::vector find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, const ConfigBlockId& block); +std::vector find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 091abbf1e..0d6a111e7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -88,8 +88,8 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Build bitstream database if needed */ BitstreamManager bitstream_manager; if ( (TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) - && (FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) - && (FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { + || (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) + || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { bitstream_manager = build_device_bitstream(vpr_setup, Arch, module_manager, Arch.spice->circuit_lib, mux_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp index 54a7fe351..cdcfe164c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp @@ -121,11 +121,14 @@ void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstr write_bitstream_xml_file_head(fp); std::string top_block_name = generate_fpga_top_module_name(); - /* Find the top block */ - ConfigBlockId top_block = bitstream_manager.find_block(top_block_name); + /* Find the top block, which has not parents */ + std::vector top_block = find_bitstream_manager_top_blocks(bitstream_manager); + /* Make sure we have only 1 top block and its name matches the top module */ + VTR_ASSERT(1 == top_block.size()); + VTR_ASSERT(0 == top_block_name.compare(bitstream_manager.block_name(top_block[0]))); /* Write bitstream, block by block, in a recursive way */ - rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block); + rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block[0]); /* Close file handler */ fp.close(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp index cadaecf6e..90e110fab 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp @@ -616,7 +616,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Generate the bitstream for the interconnection in this physical block */ build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block, module_manager, circuit_lib, mux_lib, - physical_pb->pb_graph_node, physical_pb, physical_mode_index); + physical_pb_graph_node, physical_pb, physical_mode_index); } /******************************************************************** @@ -650,7 +650,7 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Check in all the mapped blocks(clustered logic block), there is a match x,y,z*/ t_block* mapped_block = search_mapped_block(grid_coordinate.x(), grid_coordinate.y(), z); - t_phy_pb* top_pb; + t_phy_pb* top_pb = NULL; if (NULL != mapped_block) { top_pb = (t_phy_pb*)mapped_block->phy_pb; VTR_ASSERT(NULL != top_pb); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp index 7c22d1e0c..80ffe1cdf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp @@ -29,6 +29,13 @@ * * In this case, LUT is configured as a wiring module * This function will generate a truth for the wiring LUT + * + * For example: + * The truth table of the case where the 3rd input of + * a 4-input LUT is wired to output + * + * --1- 1 + * ********************************************************************/ LutTruthTable build_post_routing_wired_lut_truth_table(const int& lut_output_vpack_net_num, const size_t& lut_size, @@ -116,7 +123,11 @@ LutTruthTable build_post_routing_lut_truth_table(t_logical_block* mapped_logical * net1 --->| LUT | net0--->| LUT | * ... | | ... | | * +-------+ +-------+ - */ + * + * Truth table line Truth table line + * .names net0 net1 out .names net1 net0 out + * 01 1 10 1 + */ while (head) { /* Cache a line of truth table */ std::string tt_line; @@ -147,11 +158,62 @@ LutTruthTable build_post_routing_lut_truth_table(t_logical_block* mapped_logical return truth_table; } + +/******************************************************************** + * Generate the mask bits for a truth table + * This function actually converts an integer to a binary vector + *******************************************************************/ +static +std::string generate_mask_bits(const size_t& mask_code, + const size_t& num_mask_bits) { + std::vector mask_bits(num_mask_bits, 0); + + /* Make sure we do not have any overflow! */ + VTR_ASSERT ( (mask_code < pow(2., num_mask_bits)) ); + + size_t temp = mask_code; + for (size_t i = 0; i < num_mask_bits; ++i) { + if (1 == temp % 2) { + mask_bits[i] = 1; /* Keep a good sequence of bits */ + } + temp = temp / 2; + } + + std::string mask_bits_str; + for (const size_t& mask_bit : mask_bits) { + VTR_ASSERT( 0 == mask_bit || 1 == mask_bit ); + if (0 == mask_bit) { + mask_bits_str.push_back('1'); + continue; + } + mask_bits_str.push_back('0'); + } + + return mask_bits_str; +} + /******************************************************************** * Adapt truth table for a fracturable LUT * Determine fixed input bits for this truth table: * 1. input bits within frac_level (all '-' if not specified) * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') + * + * For example: + * A 4-input function is mapped to input[0..3] of a 6-input fracturable LUT + * Plus, it uses the 2nd output of the fracturable LUT + * The truth table of the 4-input function is + * 1001 1 + * while truth table of a 6-input LUT requires 6 characters + * Therefore, it must be adapted by adding mask bits, which are + * a number of fixed digits to configure the fracturable LUT to + * operate in a 4-input LUT mode + * The mask bits can be decoded from the index of output used in the fracturable LUT + * For the 2nd output, it will be '01', the binary representation of index '1' + * Now the truth table will be adapt to + * 100101 1 + * where the first 4 digits come from the original truth table + * the 2 following digits are mask bits + * ********************************************************************/ LutTruthTable adapt_truth_table_for_frac_lut(const CircuitLibrary& circuit_lib, t_pb_graph_pin* lut_out_pb_graph_pin, @@ -181,17 +243,17 @@ LutTruthTable adapt_truth_table_for_frac_lut(const CircuitLibrary& circuit_lib, /* Check if we need to modify any bits */ VTR_ASSERT(0 <= num_mask_bits); if ( 0 == num_mask_bits ) { + /* No modification needed, push to adapted truth table */ + adapt_truth_table.push_back(tt_line); continue; } /* Modify bits starting from lut_frac_level */ /* Decode the lut_output_mask to LUT input codes */ int temp = pow(2., num_mask_bits) - 1 - lut_output_mask; - std::vector mask_bits = my_itobin_vec(temp, num_mask_bits); + std::string mask_bits_str = generate_mask_bits(temp, num_mask_bits); /* Copy the bits to the truth table line */ std::string adapt_tt_line = tt_line; - for (const size_t& mask_bit : mask_bits) { - adapt_tt_line.insert(lut_frac_level, std::to_string(mask_bit)); - } + adapt_tt_line.replace(lut_frac_level, mask_bits_str.size(), mask_bits_str); /* Push to adapted truth table */ adapt_truth_table.push_back(adapt_tt_line); @@ -283,7 +345,8 @@ std::string complete_truth_table_line(const size_t& lut_size, /******************************************************************** * For each lut_bit_lines, we should recover the truth table, * and then set the sram bits to "1" if the truth table defines so. - * Start_point: the position we start decode recursively + * Start_point: the position we start converting don't care sign '-' + * to explicit '0' or '1' *******************************************************************/ static void rec_build_lut_bitstream_per_line(std::vector& lut_bitstream, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp index 644fe730e..f48de7afb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp @@ -32,7 +32,7 @@ size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib, size_t default_path_id; if (TRUE == circuit_lib.mux_add_const_input(mux_model)) { - default_path_id = mux_size; /* When there is a constant input, use the last path */ + default_path_id = mux_size - 1; /* When there is a constant input, use the last path */ } else { default_path_id = DEFAULT_MUX_PATH_ID; /* When there is no constant input, use the default one */ } @@ -61,7 +61,8 @@ std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, * We will find the input size of implemented MUX and fetch the graph-based representation in MUX library */ size_t implemented_mux_size = find_mux_implementation_num_inputs(circuit_lib, mux_model, mux_size); - MuxId mux_graph_id = mux_lib.mux_graph(mux_model, implemented_mux_size); + /* Note that the mux graph is indexed using datapath MUX size!!!! */ + MuxId mux_graph_id = mux_lib.mux_graph(mux_model, mux_size); const MuxGraph mux_graph = mux_lib.mux_graph(mux_graph_id); size_t datapath_id = path_id; @@ -72,7 +73,8 @@ std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, } else { VTR_ASSERT( datapath_id < mux_size); } - + /* Path id should makes sense */ + VTR_ASSERT(datapath_id < mux_graph.inputs().size()); /* We should have only one output for this MUX! */ VTR_ASSERT(1 == mux_graph.outputs().size()); @@ -80,7 +82,7 @@ std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, vtr::vector raw_bitstream = mux_graph.decode_memory_bits(MuxInputId(datapath_id), mux_graph.output_id(mux_graph.outputs()[0])); std::vector mux_bitstream; - for (const bool& bit : mux_bitstream) { + for (const bool& bit : raw_bitstream) { mux_bitstream.push_back(bit); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 7f9db8293..901947d80 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -903,7 +903,7 @@ vtr::vector build_mux_module_output_buffers(ModuleMana /* Create a module net which sinks at buffer input */ ModuleNetId input_net = module_manager.create_module_net(mux_module); - ModuleNetId output_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, output_net); + ModuleNetId output_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, input_net); module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin); mux_output_nets[output_index] = input_net; } From f1163518313f4ecf0828d4400966edbb36e481ce Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 26 Oct 2019 17:25:45 -0600 Subject: [PATCH 344/482] add instance name for each pb graph node --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 31 +++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 10 ++++++ .../bitstream/build_grid_bitstream.cpp | 10 +++--- .../module_builder/build_grid_modules.cpp | 11 +++++++ 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 2091cb8ba..18db75d24 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -881,6 +881,21 @@ std::string generate_physical_block_module_name(const std::string& prefix, return module_name; } + +/********************************************************************* + * Generate the instance name for physical block with a given index + **********************************************************************/ +std::string generate_physical_block_instance_name(const std::string& prefix, + t_pb_type* pb_type, + const size_t& index) { + std::string instance_name = generate_physical_block_module_name(prefix, pb_type); + /* Add index to the name */ + instance_name += std::string("_"); + instance_name += std::to_string(index); + + return instance_name; +} + /********************************************************************* * This function is a wrapper for the function generate_physical_block_module_name() * which can automatically decode the io_side and add a prefix @@ -892,6 +907,22 @@ std::string generate_grid_physical_block_module_name(const std::string& prefix, return generate_physical_block_module_name(module_name_prefix, pb_type); } +/********************************************************************* + * Generate the instance name for physical block in Grid with a given index + **********************************************************************/ +std::string generate_grid_physical_block_instance_name(const std::string& prefix, + t_pb_type* pb_type, + const e_side& border_side, + const size_t& index) { + std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side); + std::string instance_name = generate_physical_block_module_name(module_name_prefix, pb_type); + /* Add index to the name */ + instance_name += std::string("_"); + instance_name += std::to_string(index); + + return instance_name; +} + /******************************************************************** * This function try to infer if a grid locates at the border of a * FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 2d4f08f08..156b21350 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -175,10 +175,20 @@ std::string generate_grid_block_instance_name(const std::string& prefix, std::string generate_physical_block_module_name(const std::string& prefix, t_pb_type* physical_pb_type); +std::string generate_physical_block_instance_name(const std::string& prefix, + t_pb_type* pb_type, + const size_t& index); + std::string generate_grid_physical_block_module_name(const std::string& prefix, t_pb_type* pb_type, const e_side& border_side); +std::string generate_grid_physical_block_instance_name(const std::string& prefix, + t_pb_type* pb_type, + const e_side& border_side, + const size_t& index); + + e_side find_grid_border_side(const vtr::Point& device_size, const vtr::Point& grid_coordinate); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp index 90e110fab..41cfa7d8d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp @@ -552,7 +552,8 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, const MuxLibrary& mux_lib, const e_side& border_side, t_phy_pb* physical_pb, - t_pb_graph_node* physical_pb_graph_node) { + t_pb_graph_node* physical_pb_graph_node, + const size_t& pb_graph_node_index) { /* Get the physical pb_type that is linked to the pb_graph node */ t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; @@ -561,7 +562,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, /* Create a block for the physical block under the grid block in bitstream manager */ std::string pb_block_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string pb_block_name = generate_physical_block_module_name(pb_block_name_prefix, physical_pb_type); + std::string pb_block_name = generate_physical_block_instance_name(pb_block_name_prefix, physical_pb_type, pb_graph_node_index); ConfigBlockId pb_configurable_block = bitstream_manager.add_block(pb_block_name); bitstream_manager.add_child_block(parent_configurable_block, pb_configurable_block); @@ -579,7 +580,8 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, module_manager, circuit_lib, mux_lib, border_side, child_pb, - &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb])); + &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb]), + jpb); } } } @@ -660,7 +662,7 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, module_manager, circuit_lib, mux_lib, border_side, - top_pb, top_pb_graph_node); + top_pb, top_pb_graph_node, z); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index f5ca6ce77..7d55a7b28 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -908,6 +908,11 @@ void rec_build_physical_block_modules(ModuleManager& module_manager, /* Add the memory module as a child of primitive module */ module_manager.add_child_module(pb_module, child_pb_module); + + /* Set an instance name to bind to a block in bitstream generation */ + std::string child_pb_instance_name = generate_physical_block_instance_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild]), inst); + module_manager.set_child_instance_name(pb_module, child_pb_module, child_instance_id, child_pb_instance_name); + /* Identify if this sub module includes configuration bits, * we will update the memory module and instance list */ @@ -1015,6 +1020,12 @@ void build_grid_module(ModuleManager& module_manager, for (int iz = 0; iz < phy_block_type->capacity; ++iz) { size_t pb_instance_id = module_manager.num_instance(grid_module, pb_module); module_manager.add_child_module(grid_module, pb_module); + + /* Give the child module with a unique instance name */ + std::string instance_name = generate_grid_physical_block_instance_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side, iz); + /* Set an instance name to bind to a block in bitstream generation */ + module_manager.set_child_instance_name(grid_module, pb_module, pb_instance_id, instance_name); + /* Identify if this sub module includes configuration bits, * we will update the memory module and instance list */ From 2b06cfc3cfe08a0f53e786d9103fa04eedd09662 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Oct 2019 18:47:33 -0600 Subject: [PATCH 345/482] added fabric bitstream generator and fixed critical bugs in top module graph --- .../SRC/fpga_x2p/base/bitstream_manager.cpp | 23 +++ .../vpr/SRC/fpga_x2p/base/bitstream_manager.h | 3 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 7 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 25 +++- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 2 - .../bitstream/build_device_bitstream.cpp | 8 +- .../bitstream/build_fabric_bitstream.cpp | 135 ++++++++++++++++++ .../bitstream/build_fabric_bitstream.h | 11 ++ .../bitstream/build_routing_bitstream.cpp | 15 +- .../bitstream/build_routing_bitstream.h | 1 - .../build_essential_modules.cpp | 14 ++ .../module_builder/build_grid_modules.cpp | 2 + .../module_builder/build_routing_modules.cpp | 3 +- .../module_builder/build_top_module.cpp | 5 +- .../build_top_module_memory.cpp | 36 ++++- 15 files changed, 263 insertions(+), 27 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp index 03b4c2e00..f5de0b2bc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp @@ -64,6 +64,29 @@ ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) cons return bit_parent_block_ids_[bit_id]; } +/* Find the child block in a bitstream manager with a given name */ +ConfigBlockId BitstreamManager::find_child_block(const ConfigBlockId& block_id, + const std::string& child_block_name) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_block_id(block_id)); + + std::vector candidates; + + for (const ConfigBlockId& child : block_children(block_id)) { + if (0 == child_block_name.compare(block_name(child))) { + candidates.push_back(child); + } + } + + /* We should have 0 or 1 candidate! */ + VTR_ASSERT(0 == candidates.size() || 1 == candidates.size()); + if (0 == candidates.size()) { + /* Not found, return an invalid value */ + return ConfigBlockId::INVALID(); + } + return candidates[0]; +} + /****************************************************************************** * Public Mutators ******************************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h index 57708face..e09526199 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h @@ -73,6 +73,9 @@ class BitstreamManager { /* Find the parent block of a bit */ ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const; + /* Find the child block in a bitstream manager with a given name */ + ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const; + public: /* Public Mutators */ /* Add a new configuration bit to the bitstream manager */ ConfigBitId add_bit(const bool& bit_value); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 0d6a111e7..bab269b24 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -31,6 +31,7 @@ #include "mux_library_builder.h" #include "build_module_graph.h" #include "build_device_bitstream.h" +#include "build_fabric_bitstream.h" #include "bitstream_writer.h" #include "spice_api.h" @@ -87,14 +88,20 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Build bitstream database if needed */ BitstreamManager bitstream_manager; + std::vector fabric_bitstream; if ( (TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) || (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { + /* Build fabric independent bitstream */ bitstream_manager = build_device_bitstream(vpr_setup, Arch, module_manager, Arch.spice->circuit_lib, mux_lib, device_size, grids, rr_switches, rr_node, device_rr_gsb); + + /* Build fabric dependent bitstream */ + fabric_bitstream = build_fabric_dependent_bitstream(bitstream_manager, module_manager); + /* Write bitstream to files */ std::string bitstream_file_path; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 18db75d24..a90a301e2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -760,6 +760,9 @@ std::string generate_grid_block_module_name(const std::string& prefix, /********************************************************************* * Generate the instance name for a configurable memory module in a Switch Block + * To keep a unique name in each module and also consider unique routing modules, + * please do NOT include any coordinates in the naming!!! + * Consider only relative coordinate, such as side! ********************************************************************/ std::string generate_sb_memory_instance_name(const std::string& prefix, const e_side& sb_side, @@ -775,16 +778,18 @@ std::string generate_sb_memory_instance_name(const std::string& prefix, /********************************************************************* * Generate the instance name for a configurable memory module in a Connection Block + * To keep a unique name in each module and also consider unique routing modules, + * please do NOT include any coordinates in the naming!!! + * Consider only relative coordinate, such as side! ********************************************************************/ std::string generate_cb_memory_instance_name(const std::string& prefix, - const std::vector>& grids, - const vtr::Point& coordinate, const e_side& cb_side, const size_t& pin_id, const std::string& postfix) { std::string instance_name(prefix); - instance_name += generate_grid_side_port_name(grids, coordinate, cb_side, pin_id); + instance_name += Side(cb_side).to_string(); + instance_name += std::string("_ipin_") + std::to_string(pin_id); instance_name += postfix; return instance_name; @@ -793,12 +798,26 @@ std::string generate_cb_memory_instance_name(const std::string& prefix, /********************************************************************* * Generate the instance name for a configurable memory module in a * physical block of a grid + * To guarentee a unique name for pb_graph pin, + * the instance name includes the index of parent node + * as well as the port name and pin index of this pin + * + * Exceptions: + * For OUTPUT ports, due to hierarchical module organization, + * their parent nodes will be uniquified + * So, we should not add any index here ********************************************************************/ std::string generate_pb_memory_instance_name(const std::string& prefix, t_pb_graph_pin* pb_graph_pin, const std::string& postfix) { std::string instance_name(prefix); instance_name += std::string(pb_graph_pin->parent_node->pb_type->name); + + if (IN_PORT == pb_graph_pin->port->type) { + instance_name += std::string("_"); + instance_name += std::to_string(pb_graph_pin->parent_node->placement_index); + } + instance_name += std::string("_"); instance_name += std::string(pb_graph_pin->port->name); instance_name += std::string("_"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 156b21350..ece002039 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -82,8 +82,6 @@ std::string generate_sb_memory_instance_name(const std::string& prefix, const std::string& postfix); std::string generate_cb_memory_instance_name(const std::string& prefix, - const std::vector>& grids, - const vtr::Point& coordinate, const e_side& cb_side, const size_t& pin_id, const std::string& postfix); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp index 378171707..4720c7bf4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp @@ -17,7 +17,7 @@ #include "build_device_bitstream.h" /******************************************************************** - * Top-level function to build a bistream from the FPGA device + * A top-level function to build a bistream from the FPGA device * 1. It will organize the bitstream w.r.t. the hierarchy of module graphs * describing the FPGA fabric * 2. It will decode configuration bits from routing multiplexers used in @@ -56,7 +56,7 @@ BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, #endif /* Bistream builder formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, "\nStart building bitstream for FPGA fabric...\n"); + vpr_printf(TIO_MESSAGE_INFO, "\nStart building fabric-independent bitstream for FPGA...\n"); /* Bitstream manager to be built */ BitstreamManager bitstream_manager; @@ -81,7 +81,7 @@ BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, build_grid_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, device_size, grids); /* Create bitstream from routing architectures */ - build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, grids, rr_switches, L_rr_node, L_device_rr_gsb); + build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb); /* End time count */ clock_t t_end = clock(); @@ -93,3 +93,5 @@ BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, return bitstream_manager; } + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp new file mode 100644 index 000000000..b9fc3bbcb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp @@ -0,0 +1,135 @@ +/******************************************************************** + * This file includes functions to build fabric dependent bitstream + *******************************************************************/ +#include +#include +#include + +#include "vtr_assert.h" +#include "util.h" +#include "fpga_x2p_naming.h" + +#include "bitstream_manager_utils.h" +#include "build_fabric_bitstream.h" + +/******************************************************************** + * This function will walk through all the configurable children under a module + * in a recursive way, following a Depth-First Search (DFS) strategy + * For each configuration child, we use its instance name as a key to spot the + * configuration bits in bitstream manager. + * Note that it is guarentee that the instance name in module manager is + * consistent with the block names in bitstream manager + * We use this link to reorganize the bitstream in the sequence of memories as we stored + * in the configurable_children) and configurable_child_instances() of each module of module manager + *******************************************************************/ +static +void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, + const ConfigBlockId& parent_block, + const ModuleManager& module_manager, + const ModuleId& parent_module, + std::vector& fabric_bitstream) { + + /* Depth-first search: if we have any children in the parent_block, + * we dive to the next level first! + */ + if (0 < bitstream_manager.block_children(parent_block).size()) { + for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) { + ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; + size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; + /* Get the instance name and ensure it is not empty */ + std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); + + /* Find the child block that matches the instance name! */ + ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); + /* We must have one valid block id! */ + if (true != bitstream_manager.valid_block_id(child_block)) + VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + + /* Go recursively */ + rec_build_module_fabric_dependent_bitstream(bitstream_manager, child_block, + module_manager, child_module, + fabric_bitstream); + } + /* Ensure that there should be no configuration bits in the parent block */ + VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); + } + + /* Note that, reach here, it means that this is a leaf node. + * We add the configuration bits to the fabric_bitstream, + * And then, we can return + */ + for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) { + fabric_bitstream.push_back(config_bit); + } +} + +/******************************************************************** + * A top-level function re-organizes the bitstream for a specific + * FPGA fabric, where configuration bits are organized in the sequence + * that can be directly loaded to the FPGA configuration protocol. + * Support: + * 1. Configuration chain + * 2. Memory decoders + * This function does NOT modify the bitstream database + * Instead, it builds a vector of ids for configuration bits in bitstream manager + * + * This function can be called ONLY after the function build_device_bitstream() + * Note that this function does NOT decode bitstreams from circuit implementation + * It was done in the function build_device_bitstream() + *******************************************************************/ +std::vector build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, + const ModuleManager& module_manager) { + std::vector fabric_bitstream; + + vpr_printf(TIO_MESSAGE_INFO, "\nBuilding fabric dependent bitstream...\n"); + + /* Start time count */ + clock_t t_start = clock(); + + /* Get the top module name in module manager, which is our starting point */ + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.find_module(top_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + + /* Find the top block in bitstream manager, which has not parents */ + std::vector top_block = find_bitstream_manager_top_blocks(bitstream_manager); + /* Make sure we have only 1 top block and its name matches the top module */ + VTR_ASSERT(1 == top_block.size()); + VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0]))); + + rec_build_module_fabric_dependent_bitstream(bitstream_manager, top_block[0], + module_manager, top_module, + fabric_bitstream); + + /* Time-consuming sanity check: Uncomment these codes only for debugging!!! + * Check which configuration bits are not touched + */ + /* + for (const ConfigBitId& config_bit : bitstream_manager.bits()) { + std::vector::iterator it = std::find(fabric_bitstream.begin(), fabric_bitstream.end(), config_bit); + if (it == fabric_bitstream.end()) { + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bitstream_manager.bit_parent_block(config_bit)); + std::string block_hierarchy_name; + for (const ConfigBlockId& temp_block : block_hierarchy) { + block_hierarchy_name += std::string("/") + bitstream_manager.block_name(temp_block); + } + vpr_printf(TIO_MESSAGE_INFO, + "bit (parent_block = %s) is not touched!\n", + block_hierarchy_name.c_str()); + } + } + */ + + /* Ensure our fabric bitstream is in the same size as device bistream */ + VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size()); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "Building fabric dependent bitstream took %g seconds\n", + run_time_sec); + + return fabric_bitstream; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h new file mode 100644 index 000000000..828b8e2de --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h @@ -0,0 +1,11 @@ +#ifndef BUILD_FABRIC_BITSTREAM_H +#define BUILD_FABRIC_BITSTREAM_H + +#include +#include "bitstream_manager.h" +#include "module_manager.h" + +std::vector build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, + const ModuleManager& module_manager); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp index c6fd9f056..c650d7704 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp @@ -236,7 +236,6 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const RRGSB& rr_gsb, @@ -248,8 +247,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager /* No bitstream generation required by a special direct connection*/ } else if (1 < src_rr_node->fan_in) { /* Create the block denoting the memory instances that drives this node in Switch Block */ - vtr::Point ipin_coord(src_rr_node->xlow, src_rr_node->ylow); - std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, grids, ipin_coord, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), src_rr_node->ptc_num, std::string("")); + std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), src_rr_node->ptc_num, std::string("")); ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block); /* This is a routing multiplexer! Generate bitstream */ @@ -276,7 +274,6 @@ void build_connection_block_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const RRGSB& rr_gsb, @@ -291,7 +288,7 @@ void build_connection_block_bitstream(BitstreamManager& bitstream_manager, for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { build_connection_block_interc_bitstream(bitstream_manager, cb_configurable_block, module_manager, circuit_lib, mux_lib, - grids, rr_switches, L_rr_node, + rr_switches, L_rr_node, rr_gsb, cb_ipin_side, inode); } @@ -307,7 +304,6 @@ void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb, @@ -333,7 +329,7 @@ void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, bitstream_manager.add_child_block(top_configurable_block, cb_configurable_block); build_connection_block_bitstream(bitstream_manager, cb_configurable_block, module_manager, - circuit_lib, mux_lib, grids, rr_switches, L_rr_node, + circuit_lib, mux_lib, rr_switches, L_rr_node, rr_gsb, cb_type); } } @@ -350,7 +346,6 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb) { @@ -384,13 +379,13 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-directionConnection blocks ...\n"); build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, - circuit_lib, mux_lib, grids, rr_switches, L_rr_node, + circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb, CHANX); vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-directionConnection blocks ...\n"); build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, - circuit_lib, mux_lib, grids, rr_switches, L_rr_node, + circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb, CHANY); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h index e22e3322d..eaf9aec5d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h @@ -17,7 +17,6 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const std::vector>& grids, const std::vector& rr_switches, t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index ccd94a001..3145017c3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -3,6 +3,7 @@ * which are the leaf circuit model in the circuit library *******************************************************************/ #include +#include #include "util.h" #include "vtr_assert.h" @@ -240,10 +241,23 @@ void build_constant_generator_module(ModuleManager& module_manager, * 2. GND ********************************************************************/ void build_constant_generator_modules(ModuleManager& module_manager) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building modules for constant generator..."); /* VDD */ build_constant_generator_module(module_manager, 1); /* GND */ build_constant_generator_module(module_manager, 0); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 7d55a7b28..432cbde9b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -564,6 +564,8 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, */ std::string mux_mem_instance_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); module_manager.set_child_instance_name(pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name); + /* Add this MUX as a configurable child to the pb_module */ + module_manager.add_configurable_child(pb_module, mux_mem_module, mux_mem_instance); /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */ add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index a015bbd2c..019872fc3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -775,8 +775,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, /* Give an instance name: this name should be consistent with the block name given in bitstream manager, * If you want to bind the bitstream generation to modules */ - vtr::Point ipin_coord(cur_rr_node->xlow, cur_rr_node->ylow); - std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, grids, ipin_coord, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), cur_rr_node->ptc_num, std::string("")); + std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), cur_rr_node->ptc_num, std::string("")); module_manager.set_child_instance_name(cb_module, mem_module, mem_instance_id, mem_instance_name); /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index ccb83fee1..f2e6539ac 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -310,6 +310,7 @@ std::vector> add_top_module_connection_block_instances(Modul /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ if (true == compact_routing_hierarchy) { DeviceCoordinator cb_coord(ix, iy); + /* Note: use GSB coordinate when inquire for unique modules!!! */ const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); @@ -324,10 +325,10 @@ std::vector> add_top_module_connection_block_instances(Modul /* Set an unique name to the instance * Note: it is your risk to gurantee the name is unique! */ + std::string cb_instance_name = generate_connection_block_module_name(cb_type, vtr::Point(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))); module_manager.set_child_instance_name(top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], - generate_connection_block_module_name(cb_type, vtr::Point(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))); - + cb_instance_name); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp index 39bf029ad..e795ab7ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp @@ -39,7 +39,8 @@ void organize_top_module_tile_cb_modules(ModuleManager& module_manager, vtr::Point cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ if (true == compact_routing_hierarchy) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, DeviceCoordinator(cb_coord.x(), cb_coord.y())); + /* Note: use GSB coordinate when inquire for unique modules!!! */ + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, DeviceCoordinator(rr_gsb.get_x(), rr_gsb.get_y())); cb_coord.set_x(unique_mirror.get_cb_x(cb_type)); cb_coord.set_y(unique_mirror.get_cb_y(cb_type)); } @@ -54,7 +55,8 @@ void organize_top_module_tile_cb_modules(ModuleManager& module_manager, if (0 < find_module_num_config_bits(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type)) { - module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[cb_coord.x()][cb_coord.y()]); + /* Note that use the original CB coodinate for instance id searching ! */ + module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)]); } } @@ -107,7 +109,7 @@ void organize_top_module_tile_memory_modules(ModuleManager& module_manager, if (0 < find_module_num_config_bits(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type)) { - module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[sb_coord.x()][sb_coord.y()]); + module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()]); } /* Try to find and add CBX and CBY */ @@ -126,6 +128,16 @@ void organize_top_module_tile_memory_modules(ModuleManager& module_manager, /* Find the module name for this type of grid */ t_type_ptr grid_type = grids[tile_coord.x()][tile_coord.y()].type; + + /* Skip EMPTY Grid */ + if (EMPTY_TYPE == grid_type) { + return; + } + /* Skip height>1 Grid, which should already been processed when offset=0 */ + if (0 < grids[tile_coord.x()][tile_coord.y()].offset) { + return; + } + std::string grid_module_name_prefix(grid_verilog_file_name_prefix); std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, tile_border_side); ModuleId grid_module = module_manager.find_module(grid_module_name); @@ -232,10 +244,26 @@ void organize_top_module_memory_modules(ModuleManager& module_manager, io_coords[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); } - /* TOP side I/Os */ + /* TOP side I/Os + * Special case for TOP side: We need tile at ix = 0, which has a SB!!! + * + * TOP-LEFT CORNER of FPGA fabric + * + * +--------+ +-------+ + * | EMPTY | | EMPTY | + * | Grid | | CBX | + * | [0][x] | | | + * +--------+ +-------+ + * +--------+ +--------+ + * | EMPTY | | SB | + * | CBX | | [0][x] | + * +--------+ +--------+ + * + */ for (size_t ix = device_size.x() - 2; ix >= 1; --ix) { io_coords[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); } + io_coords[TOP].push_back(vtr::Point(0, device_size.y() - 1)); /* LEFT side I/Os */ for (size_t iy = device_size.y() - 2; iy >= 1; --iy) { From 35073f48cf9e16be1e593befa11a1dfa5ff4ea48 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Oct 2019 19:10:21 -0600 Subject: [PATCH 346/482] add runtime profiling to module graph builders --- .../module_builder/build_decoder_modules.cpp | 15 +++++++++ .../build_essential_modules.cpp | 31 +++++++++++++++++-- .../module_builder/build_grid_modules.cpp | 15 +++++++++ .../module_builder/build_lut_modules.cpp | 14 +++++++++ .../module_builder/build_memory_modules.cpp | 14 +++++++++ .../module_builder/build_mux_modules.cpp | 14 +++++++++ .../module_builder/build_routing_modules.cpp | 28 +++++++++++++++++ .../module_builder/build_top_module.cpp | 15 +++++++++ .../module_builder/build_wire_modules.cpp | 15 +++++++++ 9 files changed, 159 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp index e8b02998e..ff9999f64 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp @@ -4,6 +4,7 @@ * 2. Decoders used by grid/routing/top-level module for memory address decoding ***************************************************************************************/ #include +#include #include "util.h" #include "vtr_assert.h" @@ -93,6 +94,12 @@ void build_mux_local_decoder_module(ModuleManager& module_manager, void build_mux_local_decoder_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building local encoder (for multiplexers) modules..."); + /* Create a library for local encoders with different sizes */ DecoderLibrary decoder_lib; @@ -128,4 +135,12 @@ void build_mux_local_decoder_modules(ModuleManager& module_manager, for (const auto& decoder : decoder_lib.decoders()) { build_mux_local_decoder_module(module_manager, decoder_lib, decoder); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 3145017c3..a474ab26c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -148,6 +148,11 @@ void build_gate_module(ModuleManager& module_manager, ***********************************************/ void build_essential_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building essential (inverter/buffer/logic gate) modules..."); for (const auto& circuit_model : circuit_lib.models()) { if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { @@ -163,6 +168,14 @@ void build_essential_modules(ModuleManager& module_manager, continue; } } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } /********************************************************************* @@ -173,6 +186,12 @@ void build_essential_modules(ModuleManager& module_manager, void build_user_defined_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::vector& routing_segments) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building user-defined modules..."); + /* Iterate over Verilog modules */ for (const auto& model : circuit_lib.models()) { /* We only care about user-defined models */ @@ -216,6 +235,14 @@ void build_user_defined_modules(ModuleManager& module_manager, BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } /********************************************************************* @@ -245,7 +272,7 @@ void build_constant_generator_modules(ModuleManager& module_manager) { clock_t t_start = clock(); vpr_printf(TIO_MESSAGE_INFO, - "Building modules for constant generator..."); + "Building constant generator modules..."); /* VDD */ build_constant_generator_module(module_manager, 1); @@ -258,6 +285,6 @@ void build_constant_generator_modules(ModuleManager& module_manager) { float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", + "took %.2g seconds\n", run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 432cbde9b..f348cf870 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -3,6 +3,7 @@ * (CLBs, I/Os, heterogeneous blocks etc.) *******************************************************************/ /* System header files */ +#include #include /* Header files from external libs */ @@ -1099,6 +1100,12 @@ void build_grid_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building grid modules..."); + /* Enumerate the types, dump one Verilog module for each */ for (int itype = 0; itype < num_types; itype++) { if (EMPTY_TYPE == &type_descriptors[itype]) { @@ -1129,5 +1136,13 @@ void build_grid_modules(ModuleManager& module_manager, NUM_SIDES); } } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp index c7057712b..75795bd50 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp @@ -2,6 +2,7 @@ * This file include functions that create modules for * the Look-Up Tables (LUTs) ********************************************************************/ +#include #include #include @@ -389,6 +390,11 @@ void build_lut_module(ModuleManager& module_manager, ********************************************************************/ void build_lut_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building Look-Up Table (LUT) modules..."); /* Search for each LUT circuit model */ for (const auto& lut_model : circuit_lib.models()) { @@ -398,5 +404,13 @@ void build_lut_modules(ModuleManager& module_manager, } build_lut_module(module_manager, circuit_lib, lut_model); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index d040fdc53..863c1bcc1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -3,6 +3,7 @@ * the memories that are affiliated to multiplexers and other programmable * circuit models, such as IOPADs, LUTs, etc. ********************************************************************/ +#include #include #include @@ -630,6 +631,11 @@ void build_memory_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building memory modules..."); /* Create the memory circuits for the multiplexer */ for (auto mux : mux_lib.muxes()) { @@ -677,5 +683,13 @@ void build_memory_modules(ModuleManager& module_manager, /* Create a Verilog module for the memories used by the circuit model */ build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 901947d80..2386000c5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -5,6 +5,7 @@ * such as a branch in a multiplexer * and the full multiplexer **********************************************/ +#include #include #include @@ -1369,6 +1370,11 @@ void build_mux_module(ModuleManager& module_manager, void build_mux_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building multiplexer modules..."); /* Generate basis sub-circuit for unique branches shared by the multiplexers */ for (auto mux : mux_lib.muxes()) { @@ -1391,5 +1397,13 @@ void build_mux_modules(ModuleManager& module_manager, /* Create MUX circuits */ build_mux_module(module_manager, circuit_lib, mux_circuit_model, mux_graph); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 019872fc3..b1c687e77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -5,6 +5,7 @@ * 1. Connection blocks * 2. Switch blocks *******************************************************************/ +#include #include #include "vtr_assert.h" @@ -1069,6 +1070,12 @@ void build_flatten_routing_modules(ModuleManager& module_manager, const std::vector>& grids, const t_det_routing_arch& routing_arch, const std::vector& rr_switches) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building routing modules..."); + /* We only support uni-directional routing architecture now */ VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); @@ -1098,6 +1105,13 @@ void build_flatten_routing_modules(ModuleManager& module_manager, sram_orgz_type, sram_model, CHANY); + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } /******************************************************************** @@ -1119,6 +1133,12 @@ void build_unique_routing_modules(ModuleManager& module_manager, const std::vector>& grids, const t_det_routing_arch& routing_arch, const std::vector& rr_switches) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building unique routing modules..."); + /* We only support uni-directional routing architecture now */ VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); @@ -1152,4 +1172,12 @@ void build_unique_routing_modules(ModuleManager& module_manager, sram_orgz_type, sram_model, unique_mirror, CHANY); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index f2e6539ac..9acb7bc59 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -2,6 +2,7 @@ * This file includes functions that are used to print the top-level * module for the FPGA fabric in Verilog format *******************************************************************/ +#include #include #include @@ -831,6 +832,12 @@ void build_top_module(ModuleManager& module_manager, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, const bool& compact_routing_hierarchy) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building FPGA fabric module..."); + /* Create a module as the top-level fabric, and add it to the module manager */ std::string top_module_name = generate_fpga_top_module_name(); ModuleId top_module = module_manager.add_module(top_module_name); @@ -900,4 +907,12 @@ void build_top_module(ModuleManager& module_manager, add_top_module_nets_memory_config_bus(module_manager, top_module, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp index 020329e63..f338110c8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp @@ -2,6 +2,7 @@ * This file includes functions to generate * Verilog submodules for wires. **********************************************/ +#include #include #include @@ -105,6 +106,12 @@ void build_routing_wire_module(ModuleManager& module_manager, void build_wire_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::vector routing_segments) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building wire modules..."); + /* Print Verilog models for regular wires*/ for (const auto& wire_model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) { /* Bypass user-defined circuit models */ @@ -131,4 +138,12 @@ void build_wire_modules(ModuleManager& module_manager, /* Print a Verilog module */ build_routing_wire_module(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } From 55eea6c4d5b3f2afedd0f4a39e7efe7525102f3c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Oct 2019 20:12:48 -0600 Subject: [PATCH 347/482] rename files to be clear --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- .../{build_module_graph.cpp => build_device_module.cpp} | 2 +- .../{build_module_graph.h => build_device_module.h} | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/{build_module_graph.cpp => build_device_module.cpp} (99%) rename vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/{build_module_graph.h => build_device_module.h} (92%) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index bab269b24..c24dd30a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -29,7 +29,7 @@ #include "fpga_x2p_setup.h" #include "mux_library_builder.h" -#include "build_module_graph.h" +#include "build_device_module.h" #include "build_device_bitstream.h" #include "build_fabric_bitstream.h" #include "bitstream_writer.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp similarity index 99% rename from vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp index ef1a03830..49b904257 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp @@ -20,7 +20,7 @@ #include "build_grid_modules.h" #include "build_routing_modules.h" #include "build_top_module.h" -#include "build_module_graph.h" +#include "build_device_module.h" /******************************************************************** * The main function to be called for building module graphs diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.h similarity index 92% rename from vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.h index f1375668f..40ce9e9c5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.h @@ -1,5 +1,5 @@ -#ifndef BUILD_MODULE_GRAPH_H -#define BUILD_MODULE_GRAPH_H +#ifndef BUILD_DEVICE_MODULE_H +#define BUILD_DEVICE_MODULE_H #include #include "vpr_types.h" From ccabe4ce2a943aa3cbae851f8655cc1762db9825 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Oct 2019 14:45:51 -0600 Subject: [PATCH 348/482] refactoring Verilog formal verification top testbench using random vectors --- vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 23 +- .../verilog_formal_random_top_testbench.c | 10 +- .../verilog_formal_random_top_testbench.cpp | 590 ++++++++++++++++++ .../verilog_formal_random_top_testbench.h | 24 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 18 +- .../fpga_x2p/verilog/verilog_writer_utils.h | 3 + 7 files changed, 648 insertions(+), 21 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 820ee7126..7b87d664a 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -245,6 +245,7 @@ typedef struct s_logical_block { /* Xifan TANG: SPICE model support*/ /* For mapping */ + CircuitModelId mapped_circuit_model; t_spice_model* mapped_spice_model; int mapped_spice_model_index; /* index of spice_model in completed FPGA netlist */ int temp_used; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 0526e6a90..d7b40c0ba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -153,8 +153,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, char* formal_verification_top_netlist_file_path = NULL; char* autocheck_top_testbench_file_name = NULL; char* autocheck_top_testbench_file_path = NULL; - char* random_top_testbench_file_name = NULL; - char* random_top_testbench_file_path = NULL; char* chomped_parent_dir = NULL; char* chomped_circuit_name = NULL; @@ -396,6 +394,12 @@ void vpr_fpga_verilog(ModuleManager& module_manager, my_free(top_testbench_file_path); } + /* Create vectors for logical blocks */ + std::vector L_logical_blocks; + for (int i = 0; i < num_logical_blocks; ++i) { + L_logical_blocks.push_back(logical_block[i]); + } + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) { formal_verification_top_netlist_file_name = my_strcat(chomped_circuit_name, formal_verification_verilog_file_postfix); formal_verification_top_netlist_file_path = my_strcat(src_dir_path, formal_verification_top_netlist_file_name); @@ -407,11 +411,20 @@ void vpr_fpga_verilog(ModuleManager& module_manager, src_dir_path, chomped_circuit_name, *(Arch.spice)); - random_top_testbench_file_name = my_strcat(chomped_circuit_name, random_top_testbench_verilog_file_postfix); - random_top_testbench_file_path = my_strcat(src_dir_path, random_top_testbench_file_name); + + /* Print out top-level testbench using random vectors */ + std::string random_top_testbench_file_path = std::string(src_dir_path) + + std::string(chomped_circuit_name) + + std::string(random_top_testbench_verilog_file_postfix); + /* FIXME: old function TO BE REMOVED */ dump_verilog_random_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, - random_top_testbench_file_path, src_dir_path, + random_top_testbench_file_path.c_str(), src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); + /* TODO: remove the .bak when it is ready */ + print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path + ".bak", + std::string(src_dir_path), L_logical_blocks, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); + /* Free */ my_free(formal_verification_top_netlist_file_name); my_free(formal_verification_top_netlist_file_path); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c index 1389815a8..8081dec57 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c @@ -352,11 +352,11 @@ void dump_verilog_top_random_stimuli(FILE* fp, } void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, - char* circuit_name, - char* top_netlist_name, - char* verilog_dir_path, - t_syn_verilog_opts fpga_verilog_opts, - t_spice verilog) { + char* circuit_name, + const char* top_netlist_name, + char* verilog_dir_path, + t_syn_verilog_opts fpga_verilog_opts, + t_spice verilog) { FILE* fp = NULL; char* title = my_strcat("FPGA Verilog Testbench for Formal Top-level netlist of Design: ", circuit_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp new file mode 100644 index 000000000..74d48a4a3 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -0,0 +1,590 @@ +/******************************************************************** + * This file includes functions that are used to generate a Verilog + * testbench for the top-level module (FPGA fabric), in purpose of + * running formal verification with random input vectors + *******************************************************************/ +#include +#include +#include +#include +#include + +/* Include external library headers*/ +#include "device_port.h" +#include "vtr_assert.h" +#include "util.h" + +/* Include VPR headers*/ + +/* Include FPGA-X2P headers*/ +#include "fpga_x2p_utils.h" + +/* Include FPGA Verilog headers*/ +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_formal_random_top_testbench.h" + +/******************************************************************** + * Local variables used only in this file + *******************************************************************/ +constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb"; +constexpr char* FPGA_PORT_POSTFIX = "_gfpga"; +constexpr char* BENCHMARK_PORT_POSTFIX = "_bench"; +constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag"; +constexpr char* DEFAULT_CLOCK_NAME = "clk"; +constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT"; +constexpr char* FPGA_INSTANCE_NAME = "REF_DUT"; +constexpr char* ERROR_COUNTER = "nb_error"; +constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; + +/******************************************************************** + * Find the clock port name to be used in this testbench + *******************************************************************/ +static +std::vector find_verilog_top_clock_port_name(const std::vector& L_logical_blocks) { + std::vector clock_port_names; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + /* Find the clock signals */ + if ( (VPACK_INPAD == lb.type) && (TRUE == lb.is_clock) ) { + clock_port_names.push_back(std::string(lb.name)); + } + } + + return clock_port_names; +} + +/******************************************************************** + * Generate the clock port name to be used in this testbench + * + * Restrictions: + * Assume this is a single clock benchmark + *******************************************************************/ +static +BasicPort generate_verilog_top_clock_port(const std::vector& clock_port_names) { + if (0 == clock_port_names.size()) { + return BasicPort(std::string(DEFAULT_CLOCK_NAME), 1); + } + + VTR_ASSERT(1 == clock_port_names.size()); + return BasicPort(clock_port_names[0], 1); +} + +/******************************************************************** + * Print the module ports for the Verilog testbench + * using random vectors + * This function generates + * 1. the input ports to drive both input benchmark module and FPGA fabric module + * 2. the output ports for input benchmark module + * 3. the output ports for FPGA fabric module + * 4. the error checking ports + *******************************************************************/ +static +void print_verilog_top_random_testbench_ports(std::fstream& fp, + const std::string& circuit_name, + const std::vector& clock_port_names, + const std::vector& L_logical_blocks) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Print the declaration for the module */ + fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl; + + /* Instantiate register for inputs stimulis */ + print_verilog_comment(fp, std::string("----- Shared inputs -------")); + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_INPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort input_port(std::string(lb.name), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Create a clock port if the benchmark does not have one! + * The clock is used for counting and synchronizing input stimulus + */ + if (0 == clock_port_names.size()) { + BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + print_verilog_comment(fp, std::string("----- Default clock port is added here since benchmark does not contain one -------")); + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, clock_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate wires for FPGA fabric outputs */ + print_verilog_comment(fp, std::string("----- FPGA fabric outputs -------")); + + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + std::string(FPGA_PORT_POSTFIX)), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate wire for benchmark output */ + print_verilog_comment(fp, std::string("----- Benchmark outputs -------")); + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + std::string(BENCHMARK_PORT_POSTFIX)), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate register for output comparison */ + print_verilog_comment(fp, std::string("----- Output vectors checking flags -------")); + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + std::string(CHECKFLAG_PORT_POSTFIX)), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Condition ends for the benchmark instanciation */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate an integer to count the number of error + * and determine if the simulation succeed or failed + */ + print_verilog_comment(fp, std::string("----- Error counter -------")); + fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Instanciate the FPGA fabric module + *******************************************************************/ +static +void print_verilog_random_testbench_instance(std::fstream& fp, + const std::string& module_name, + const std::string& instance_name, + const std::string& output_port_postfix, + const std::vector& L_logical_blocks) { + + /* Validate the file stream */ + check_file_handler(fp); + + fp << "\t" << module_name << " " << instance_name << "(" << std::endl; + + size_t port_counter = 0; + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + /* The first port does not need a comma */ + if(0 < port_counter){ + fp << "," << std::endl; + } + /* Input port follows the logical block name while output port requires a special postfix */ + if (VPACK_INPAD == lb.type){ + fp << "\t\t" << std::string(lb.name); + } else { + VTR_ASSERT_SAFE(VPACK_OUTPAD == lb.type); + fp << "\t\t" << std::string(lb.name) << output_port_postfix; + } + /* Update the counter */ + port_counter++; + } + fp << "\t);" << std::endl; +} + + + +/******************************************************************** + * Instanciate the input benchmark module + *******************************************************************/ +static +void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, + const std::string& reference_verilog_top_name, + const std::vector& L_logical_blocks) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); + + print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); + + print_verilog_random_testbench_instance(fp, reference_verilog_top_name, + std::string(reference_verilog_top_name + std::string(BENCHMARK_INSTANCE_NAME)), + std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks); + + print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Condition ends for the benchmark instanciation */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Compute the time period for the simulation + *******************************************************************/ +static +int get_simulation_time(const int& num_op_clock_cycles, + const float& op_clock_period) { + /* Take into account the prog_reset and reset cycles + * 1e9 is to change the unit to ns rather than second + */ + return (MAGIC_NUMBER_FOR_SIMULATION_TIME * num_op_clock_cycles * op_clock_period) / verilog_sim_timescale; +} + +/******************************************************************** + * Print Verilog codes to set up a timeout for the simulation + * and dump the waveform to VCD files + * + * Note that: these codes are tuned for Icarus simulator!!! + *******************************************************************/ +static +void print_verilog_timeout_and_vcd(std::fstream& fp, + const std::string& circuit_name, + const int& simulation_time) { + /* Validate the file stream */ + check_file_handler(fp); + + /* The following verilog codes are tuned for Icarus */ + print_verilog_preprocessing_flag(fp, std::string(icarus_simulator_flag)); + + print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------")); + + fp << "\tinitial begin" << std::endl; + fp << "\t\t$dumpfile(\"" << circuit_name << "_formal.vcd\");" << std::endl; + fp << "\t\t$dumpvars(1, " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ");" << std::endl; + fp << "\tend" << std::endl; + + fp << "\tinitial begin" << std::endl; + fp << "\t\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; + fp << "\t\t$display(\"Simulation start\");" << std::endl; + print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); + fp << "\t\t#" << simulation_time << std::endl; + fp << "\t\tif(" << ERROR_COUNTER << " == 0) begin" << std::endl; + fp << "\t\t\t$display(\"Simulation Succeed\");" << std::endl; + fp << "\t\tend else begin" << std::endl; + fp << "\t\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << ERROR_COUNTER << ");" << std::endl; + fp << "\t\tend" << std::endl; + fp << "\t\t$finish;" << std::endl; + fp << "\tend" << std::endl; + + print_verilog_comment(fp, std::string("----- END Icarus requirement -------")); + + /* Condition ends for the Icarus requirement */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print Verilog codes to check the equivalence of output vectors + * + * Restriction: this function only supports single clock benchmarks! + *******************************************************************/ +static +void print_verilog_top_random_testbench_check(std::fstream& fp, + const std::vector& L_logical_blocks, + const std::vector& clock_port_names) { + + /* Validate the file stream */ + check_file_handler(fp); + + /* Add output autocheck conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); + + print_verilog_comment(fp, std::string("----- Begin checking output vectors -------")); + + BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + + fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + if (VPACK_OUTPAD == lb.type){ + fp << "\t\tif(!(" << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX); + fp << " === " << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX); + fp << ") && !(" << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX); + fp << " === 1'bx)) begin" << std::endl; + fp << "\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << " <= 1'b1;" << std::endl; + fp << "\t\tend else begin" << std::endl; + fp << "\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << "<= 1'b0;" << std::endl; + fp << "\t\tend" << std::endl; + } + } + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + fp << "\talways@(posedge " << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << ") begin" << std::endl; + fp << "\t\tif(" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << ") begin" << std::endl; + fp << "\t\t\t" << ERROR_COUNTER << " = " << ERROR_COUNTER << " + 1;" << std::endl; + fp << "\t\t\t$display(\"Mismatch on " << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX) << " at time = " << std::string("%t") << "\", $realtime);" << std::endl; + fp << "\t\tend" << std::endl; + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + } + + /* Condition ends */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Instanciate the FPGA fabric module + *******************************************************************/ +static +void print_verilog_random_testbench_fpga_instance(std::fstream& fp, + const std::string& circuit_name, + const std::vector& L_logical_blocks) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------")); + + + print_verilog_random_testbench_instance(fp, circuit_name, + std::string(circuit_name + std::string(formal_verification_top_postfix)), + std::string(FPGA_PORT_POSTFIX), L_logical_blocks); + + print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Generate random stimulus for the input ports + *******************************************************************/ +static +void print_verilog_top_random_stimuli(std::fstream& fp, + const t_spice_params& simulation_parameters, + const std::vector& L_logical_blocks, + const std::vector& clock_port_names) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Initialization -------")); + + fp << "\tinitial begin" << std::endl; + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + /* Clock ports will be initialized later */ + if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { + fp << "\t\t" << std::string(lb.name) << " <= 1'b0;" << std::endl; + } + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Creae clock stimuli */ + BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; + fp << "\twhile(1) begin" << std::endl; + fp << "\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << " <= !"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << ";" << std::endl; + fp << "\t\tend" << std::endl; + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + + // Not ready yet to determine if input is reset +/* + fprintf(fp, "//----- Reset Stimulis\n"); + fprintf(fp, " initial begin\n"); + fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " while(1) begin\n"); + fprintf(fp, " #%.3f\n", (rand() % 15) + 0.5); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " #%.3f\n", (rand() % 10000) + 200); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " end\n"); + fprintf(fp, " end\n\n"); +*/ + + print_verilog_comment(fp, std::string("----- Input Stimulus -------")); + fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + /* Clock ports will be initialized later */ + if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { + fp << "\t\t" << std::string(lb.name) << " <= $random;" << std::endl; + } + } + + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/********************************************************************* + * Top-level function in this file: + * Create a Verilog testbench using random input vectors + * The testbench consists of two modules, i.e., Design Under Test (DUT) + * 1. top-level module of FPGA fabric + * 2. top-level module of users' benchmark, + * i.e., the input benchmark of VPR flow + * +----------+ + * | FPGA | +------------+ + * +----->| Fabric |------>| | + * | | | | | + * | +----------+ | | + * | | Output | + * random_input_vectors -----+ | Vector |---->Functional correct? + * | | Comparator | + * | +-----------+ | | + * | | Input | | | + * +----->| Benchmark |----->| | + * +-----------+ +------------+ + * + * Same input vectors are given to drive both DUTs. + * The output vectors of the DUTs are compared to verify if they + * have the same functionality. + * A flag will be raised to indicate the result + ********************************************************************/ +void print_verilog_random_top_testbench(const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir, + const std::vector& L_logical_blocks, + const t_syn_verilog_opts& fpga_verilog_opts, + const t_spice_params& simulation_parameters) { + vpr_printf(TIO_MESSAGE_INFO, + "Writing Random Testbench for FPGA Top-level Verilog netlist for %s...", + circuit_name.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Generate a brief description on the Verilog file*/ + std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name; + print_verilog_file_header(fp, title); + + /* Print preprocessing flags and external netlists */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(defines_verilog_simulation_file_name))); + + print_verilog_include_netlist(fp, std::string(fpga_verilog_opts.reference_verilog_benchmark_file)); + + /* Preparation: find all the clock ports */ + std::vector clock_port_names = find_verilog_top_clock_port_name(L_logical_blocks); + + /* Start of testbench */ + print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, L_logical_blocks); + + /* Call defined top-level module */ + print_verilog_random_testbench_fpga_instance(fp, circuit_name, L_logical_blocks); + + /* Call defined benchmark */ + print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, L_logical_blocks); + + /* Add stimuli for reset, set, clock and iopad signals */ + print_verilog_top_random_stimuli(fp, simulation_parameters, L_logical_blocks, clock_port_names); + + print_verilog_top_random_testbench_check(fp, L_logical_blocks, clock_port_names); + + int simulation_time = get_simulation_time(simulation_parameters.meas_params.sim_num_clock_cycle, + 1./simulation_parameters.stimulate_params.op_clock_freq); + + /* Add Icarus requirement */ + print_verilog_timeout_and_vcd(fp, circuit_name, simulation_time); + + /* Testbench ends*/ + print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)); + + /* Close the file stream */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h index 56ebf0093..4ebda1eb4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h @@ -1,8 +1,22 @@ +#ifndef VERILOG_FORMAL_RANDOME_TOP_TESTBENCH +#define VERILOG_FORMAL_RANDOME_TOP_TESTBENCH + +#include +#include "vpr_types.h" +#include "spice_types.h" void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, - char* circuit_name, - char* top_netlist_name, - char* verilog_dir_path, - t_syn_verilog_opts fpga_verilog_opts, - t_spice verilog); + char* circuit_name, + const char* top_netlist_name, + char* verilog_dir_path, + t_syn_verilog_opts fpga_verilog_opts, + t_spice verilog); +void print_verilog_random_top_testbench(const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir, + const std::vector& L_logical_blocks, + const t_syn_verilog_opts& fpga_verilog_opts, + const t_spice_params& simulation_parameters); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index f2a26b347..555f059d0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -43,23 +43,29 @@ void print_verilog_file_header(std::fstream& fp, fp << "\n"; } +/******************************************************************** + * Print Verilog codes to include a netlist + *******************************************************************/ +void print_verilog_include_netlist(std::fstream& fp, + const std::string& netlist_name) { + check_file_handler(fp); + + fp << "//------ Include external netlist: " << netlist_name << " -----" << std::endl; + fp << "`include \"" << netlist_name << "\"" << std::endl; + fp << "//------ End include external netlist: " << netlist_name << " -----" << std::endl; +} /************************************************ * Generate include files for a Verilog netlist ***********************************************/ void print_verilog_include_defines_preproc_file(std::fstream& fp, const std::string& verilog_dir) { - check_file_handler(fp); /* Generate the file name */ std::string include_file_path = format_dir_path(verilog_dir); include_file_path += defines_verilog_file_name; - fp << "//------ Include defines: preproc flags -----" << std::endl; - fp << "`include \"" << include_file_path << "\"" << std::endl; - fp << "//------ End Include defines: preproc flags -----" << std::endl << std::endl; - - return; + print_verilog_include_netlist(fp, include_file_path); } /************************************************ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index f06e72baf..b4f13ffcf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -21,6 +21,9 @@ void print_verilog_file_header(std::fstream& fp, const std::string& usage); +void print_verilog_include_netlist(std::fstream& fp, + const std::string& netlist_name); + void print_verilog_include_defines_preproc_file(std::fstream& fp, const std::string& verilog_dir); From c047fd3cb220fc73b6746bd4a5c9809c80547a13 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Oct 2019 15:10:29 -0600 Subject: [PATCH 349/482] plugged in the refactored formal verification Verilog testbench using random vectors --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 8 +++++--- .../verilog_formal_random_top_testbench.cpp | 16 ++++++++-------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index d7b40c0ba..22ccf2cb5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -394,7 +394,9 @@ void vpr_fpga_verilog(ModuleManager& module_manager, my_free(top_testbench_file_path); } - /* Create vectors for logical blocks */ + /* TODO: this should be outside this function! + * Create vectors for logical blocks + */ std::vector L_logical_blocks; for (int i = 0; i < num_logical_blocks; ++i) { L_logical_blocks.push_back(logical_block[i]); @@ -418,10 +420,10 @@ void vpr_fpga_verilog(ModuleManager& module_manager, + std::string(random_top_testbench_verilog_file_postfix); /* FIXME: old function TO BE REMOVED */ dump_verilog_random_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, - random_top_testbench_file_path.c_str(), src_dir_path, + std::string(random_top_testbench_file_path + ".bak").c_str(), src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); /* TODO: remove the .bak when it is ready */ - print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path + ".bak", + print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 74d48a4a3..6ba4c534c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -33,7 +33,7 @@ constexpr char* BENCHMARK_PORT_POSTFIX = "_bench"; constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag"; constexpr char* DEFAULT_CLOCK_NAME = "clk"; constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT"; -constexpr char* FPGA_INSTANCE_NAME = "REF_DUT"; +constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT"; constexpr char* ERROR_COUNTER = "nb_error"; constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; @@ -250,7 +250,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); print_verilog_random_testbench_instance(fp, reference_verilog_top_name, - std::string(reference_verilog_top_name + std::string(BENCHMARK_INSTANCE_NAME)), + std::string(BENCHMARK_INSTANCE_NAME), std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -402,8 +402,8 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------")); - print_verilog_random_testbench_instance(fp, circuit_name, - std::string(circuit_name + std::string(formal_verification_top_postfix)), + print_verilog_random_testbench_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)), + std::string(FPGA_INSTANCE_NAME), std::string(FPGA_PORT_POSTFIX), L_logical_blocks); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); @@ -443,10 +443,10 @@ void print_verilog_top_random_stimuli(std::fstream& fp, /* Creae clock stimuli */ BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); - fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; - fp << "\twhile(1) begin" << std::endl; - fp << "\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; + fp << "\t\twhile(1) begin" << std::endl; + fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; + fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); fp << " <= !"; fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); fp << ";" << std::endl; From fe005f1f568da7e0d4595599a1ba757d310a95a5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Oct 2019 15:21:14 -0600 Subject: [PATCH 350/482] remove legacy codes for Verilog formal verification testbench generation --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 5 - .../verilog_formal_random_top_testbench.c | 412 ------------------ .../verilog_formal_random_top_testbench.h | 11 +- 3 files changed, 2 insertions(+), 426 deletions(-) delete mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 22ccf2cb5..2052b6828 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -418,11 +418,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, std::string random_top_testbench_file_path = std::string(src_dir_path) + std::string(chomped_circuit_name) + std::string(random_top_testbench_verilog_file_postfix); - /* FIXME: old function TO BE REMOVED */ - dump_verilog_random_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, - std::string(random_top_testbench_file_path + ".bak").c_str(), src_dir_path, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); - /* TODO: remove the .bak when it is ready */ print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c deleted file mode 100644 index 8081dec57..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c +++ /dev/null @@ -1,412 +0,0 @@ -/***********************************/ -/* Dump Synthesizable Veriolog */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "route_common.h" -#include "vpr_utils.h" - -/* Include spice support headers*/ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "fpga_x2p_globals.h" -#include "fpga_bitstream.h" - -/* Include verilog support headers*/ -#include "verilog_global.h" -#include "verilog_utils.h" -#include "verilog_routing.h" -#include "verilog_pbtypes.h" -#include "verilog_decoder.h" -#include "verilog_top_netlist_utils.h" -#include "verilog_top_testbench.h" - -#include "verilog_formal_random_top_testbench.h" - -/* Local variables */ -static char* formal_random_top_tb_postfix = "_top_formal_verification_random_tb"; -static char* gfpga_postfix = "_gfpga"; -static char* bench_postfix = "_bench"; -static char* flag_postfix = "_flag"; -static char* def_clk_name = "clk"; -static char* error_counter = "nb_error"; -static char* clock_input_name = NULL; - -/* Local Subroutines declaration */ - -/******** Subroutines ***********/ -static -void dump_verilog_top_random_testbench_ports(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - char* circuit_name, - t_syn_verilog_opts fpga_verilog_opts){ - int iblock; - boolean bench_as_clk = FALSE; - t_spice_model* mem_model = NULL; - - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - fprintf(fp, "`include \"%s\"\n", fpga_verilog_opts.reference_verilog_benchmark_file); - - fprintf(fp, "module %s%s;\n", circuit_name, formal_random_top_tb_postfix); -// Instantiate register for inputs stimulis - fprintf(fp, "//----- Shared inputs\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_INPAD == logical_block[iblock].type) { - fprintf(fp, " reg %s;\n", logical_block[iblock].name); - if(logical_block[iblock].is_clock) - bench_as_clk = TRUE; - } - } - } - if(FALSE == bench_as_clk) - fprintf(fp, " reg %s;\n", def_clk_name); -// Instantiate wire for gfpga output - fprintf(fp, "\n//----- GFPGA outputs\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_OUTPAD == logical_block[iblock].type) { - fprintf(fp, " wire %s%s;\n", logical_block[iblock].name, gfpga_postfix); - } - } - } -// Instantiate wire for benchmark output - fprintf(fp, "\n`ifdef %s\n//----- Benchmark outputs\n", autochecked_simulation_flag); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_OUTPAD == logical_block[iblock].type) { - fprintf(fp, " wire %s%s;\n", logical_block[iblock].name, bench_postfix); - } - } - } -// Instantiate register for output comparison - fprintf(fp, "\n//----- Output flags\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_OUTPAD == logical_block[iblock].type) { - fprintf(fp, " reg %s%s;\n", logical_block[iblock].name, flag_postfix); - } - } - } fprintf(fp, "`endif\n"); -// Instantiate an integer to count the number of error and determine if the simulation succeed or failed - fprintf(fp, "\n//----- Error counter \n"); - fprintf(fp, " integer %s = 0;\n\n", error_counter); - - return; -} - -static -void dump_verilog_top_random_testbench_call_benchmark(FILE* fp, - char* reference_verilog_top_name){ - int iblock; - - fprintf(fp, "`ifdef %s\n", autochecked_simulation_flag); - fprintf(fp, "// Reference Benchmark instanciation\n"); - fprintf(fp, " %s ref_U0(\n", reference_verilog_top_name); - - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(iblock > 0){ - fprintf(fp, ",\n"); - } - if(VPACK_INPAD == logical_block[iblock].type){ - fprintf(fp, " %s", logical_block[iblock].name); - } else if(VPACK_OUTPAD == logical_block[iblock].type){ - fprintf(fp, " %s%s", - logical_block[iblock].name, - bench_postfix); - } - } - } - fprintf(fp, " );\n"); - fprintf(fp, "// End Benchmark instanciation\n`endif\n\n"); - - return; -} - -static -int get_simulation_time(//int num_prog_clock_cycles, - //float prog_clock_period, - int num_op_clock_cycles, - float op_clock_period) { - int total_time_period = 0; - - /* Take into account the prog_reset and reset cycles */ - total_time_period = (100 * (2 * num_op_clock_cycles * op_clock_period)) * 1000000000; // * 1000000000 is to change the unit to ns rather than second - - return total_time_period; -} - -static -void dump_verilog_timeout_and_vcd(FILE * fp, - char* circuit_name, - t_spice verilog) { - //t_sram_orgz_info* cur_sram_orgz_info){ - int simulation_time; - - simulation_time = get_simulation_time(//get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info), - //1./verilog.spice_params.stimulate_params.prog_clock_freq, - verilog.spice_params.meas_params.sim_num_clock_cycle, - 1./verilog.spice_params.stimulate_params.op_clock_freq); - - fprintf(fp, " // Begin Icarus requirement\n"); - fprintf(fp, "`ifdef %s\n", icarus_simulator_flag); - fprintf(fp, " initial begin\n"); - fprintf(fp, " $dumpfile(\"%s_formal.vcd\");\n", circuit_name); - fprintf(fp, " $dumpvars(1, %s%s);\n", circuit_name, - formal_random_top_tb_postfix); - fprintf(fp, " end\n\n"); - fprintf(fp, " initial begin\n"); - fprintf(fp, " $timeformat(-9, 2, \"ns\", 20);\n"); - fprintf(fp, " $display(\"Simulation start\");\n"); - fprintf(fp, " #%i // Can be changed by the user for his need\n", simulation_time); - fprintf(fp, " if(%s == 0) begin\n", error_counter); - fprintf(fp, " $display(\"Simulation Succeed\");\n"); - fprintf(fp, " end else begin\n"); - fprintf(fp, " $display(\"Simulation Failed with %s error(s)\", %s);\n", "%d", error_counter); - fprintf(fp, " end\n"); - fprintf(fp, " $finish;\n"); - fprintf(fp, " end\n"); - fprintf(fp, "`endif\n\n"); - return; -} - -static -void dump_verilog_top_random_testbench_check(FILE* fp){ - int iblock; - fprintf(fp, " // Begin checking\n"); - fprintf(fp, " always@(negedge %s) begin\n", clock_input_name); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_OUTPAD == logical_block[iblock].type){ - fprintf(fp, " if(!(%s%s === %s%s) && !(%s%s === 1'bx)) begin\n", - logical_block[iblock].name, - gfpga_postfix, - logical_block[iblock].name, - bench_postfix, - logical_block[iblock].name, - bench_postfix); - fprintf(fp, " %s%s <= 1'b1;\n", logical_block[iblock].name, - flag_postfix); - fprintf(fp, " end else begin\n %s%s <= 1'b0;\n end\n", logical_block[iblock].name, - flag_postfix); - } - } - } - fprintf(fp, " end\n\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_OUTPAD == logical_block[iblock].type){ - fprintf(fp, " always@(posedge %s%s) begin\n", logical_block[iblock].name, - flag_postfix); - fprintf(fp, " if(%s%s) begin\n", logical_block[iblock].name, - flag_postfix); - fprintf(fp, " %s = %s + 1;\n", error_counter, error_counter); - fprintf(fp, " $display(\"Mismatch on %s%s at time = %s\", $realtime);\n", logical_block[iblock].name, - gfpga_postfix, "%t"); - fprintf(fp, " end\n"); - fprintf(fp, " end\n"); - } - } - } - return; -} - -static -void dump_verilog_random_testbench_call_top_module(FILE* fp, - char* circuit_name) { - int iblock; - - fprintf(fp, "// GFPGA instanciation\n"); - fprintf(fp, " %s%s DUT(\n", circuit_name, formal_verification_top_postfix); - - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(iblock > 0){ - fprintf(fp, ",\n"); - } - if(VPACK_INPAD == logical_block[iblock].type){ - fprintf(fp, " %s", logical_block[iblock].name); - } else if(VPACK_OUTPAD == logical_block[iblock].type){ - fprintf(fp, " %s%s", - logical_block[iblock].name, - gfpga_postfix); - } - } - } - fprintf(fp, " );\n"); - fprintf(fp, "// End GFPGA instanciation\n\n"); -} - -static -void dump_verilog_top_random_stimuli(FILE* fp, - t_spice verilog){ - int iblock; - - fprintf(fp, "//----- Initialization\n"); - fprintf(fp, " initial begin\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_INPAD == logical_block[iblock].type) { - fprintf(fp, " %s <= 1'b0;\n", logical_block[iblock].name); - if(logical_block[iblock].is_clock) - clock_input_name = logical_block[iblock].name; - /* if(logical_block[iblock].is_reset) - reset_input_name = logical_block[iblock].name; */ - } - } - } - if(NULL == clock_input_name){ - clock_input_name = def_clk_name; - fprintf(fp, " %s <= 1'b0;\n", def_clk_name); - } - fprintf(fp, " while(1) begin\n"); - fprintf(fp, " #%.1f\n", ((0.5/verilog.spice_params.stimulate_params.op_clock_freq)/verilog_sim_timescale)); - fprintf(fp, " %s <= !%s;\n", clock_input_name, clock_input_name); - fprintf(fp, " end\n"); - fprintf(fp, " end\n\n"); -/* fprintf(fp, "//----- Reset Stimulis\n"); // Not ready yet to determine if input is reset - fprintf(fp, " initial begin\n"); - fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " while(1) begin\n"); - fprintf(fp, " #%.3f\n", (rand() % 15) + 0.5); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " #%.3f\n", (rand() % 10000) + 200); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " end\n"); - fprintf(fp, " end\n\n"); */ - fprintf(fp, "//----- Input Stimulis\n"); - fprintf(fp, " always@(negedge %s) begin\n", clock_input_name); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type) - ||(VPACK_OUTPAD == logical_block[iblock].type)); - if(VPACK_INPAD == logical_block[iblock].type) { - //if((logical_block[iblock].is_clock || logical_block[iblock].is_reset ) == 0 ) - if(logical_block[iblock].is_clock == 0 ) - fprintf(fp, " %s <= $random;\n", logical_block[iblock].name); - } - } - } - fprintf(fp, " end\n\n"); - return; -} - -void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, - char* circuit_name, - const char* top_netlist_name, - char* verilog_dir_path, - t_syn_verilog_opts fpga_verilog_opts, - t_spice verilog) { - FILE* fp = NULL; - char* title = my_strcat("FPGA Verilog Testbench for Formal Top-level netlist of Design: ", circuit_name); - - /* Check if the path exists*/ - fp = fopen(top_netlist_name,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create top Verilog testbench %s!", - __FILE__, __LINE__, top_netlist_name); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, - "Writing Random Testbench for FPGA Top-level Verilog netlist for %s...\n", - circuit_name); - - /* Print the title */ - dump_verilog_file_header(fp, title); - my_free(title); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, verilog_dir_path); - verilog_include_simulation_defines_file(fp, verilog_dir_path); - - /* Start of testbench */ - dump_verilog_top_random_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); - - /* Call defined top-level module */ - dump_verilog_random_testbench_call_top_module(fp, circuit_name); - - /* Call defined benchmark */ - dump_verilog_top_random_testbench_call_benchmark(fp, circuit_name); - - /* Add stimuli for reset, set, clock and iopad signals */ - dump_verilog_top_random_stimuli(fp, verilog); - - /* Add output autocheck */ - fprintf(fp, "`ifdef %s\n", autochecked_simulation_flag); - dump_verilog_top_random_testbench_check(fp); - fprintf(fp, "`endif\n\n"); - - /* Add Icarus requirement */ - dump_verilog_timeout_and_vcd(fp, circuit_name , verilog/*, cur_sram_orgz_info*/); - - /* Testbench ends*/ - fprintf(fp, "endmodule\n"); - - /* Close the file*/ - fclose(fp); - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h index 4ebda1eb4..baab0d1e5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h @@ -1,17 +1,10 @@ -#ifndef VERILOG_FORMAL_RANDOME_TOP_TESTBENCH -#define VERILOG_FORMAL_RANDOME_TOP_TESTBENCH +#ifndef VERILOG_FORMAL_RANDOM_TOP_TESTBENCH +#define VERILOG_FORMAL_RANDOM_TOP_TESTBENCH #include #include "vpr_types.h" #include "spice_types.h" -void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, - char* circuit_name, - const char* top_netlist_name, - char* verilog_dir_path, - t_syn_verilog_opts fpga_verilog_opts, - t_spice verilog); - void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, const std::string& verilog_dir, From 5cb3717433b775fc58228a1380f98c423e158ff1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Oct 2019 15:57:17 -0600 Subject: [PATCH 351/482] add single mode test case to regression test. debugging now --- ...m_chain_FC_behavioral_verilog_template.xml | 631 ++++++++++++++++++ .../test_modes/k4_N4/K4N4_test_modes.act | 16 + .../test_modes/k4_N4/K4N4_test_modes.blif | 40 ++ .../test_modes/k4_N4/K4N4_test_modes.v | 54 ++ .../k6_N10/K6N10_test_modes.act} | 0 .../k6_N10/K6N10_test_modes.blif} | 0 .../k6_N10/K6N10_test_modes.v} | 0 .../tasks/blif_vpr_flow/config/task.conf | 6 +- .../tasks/explicit_verilog/config/task.conf | 6 +- .../tasks/single_mode/config/task.conf | 58 ++ .../tasks/tileable_routing/config/task.conf | 6 +- 11 files changed, 808 insertions(+), 9 deletions(-) create mode 100644 openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml create mode 100644 openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act create mode 100644 openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif create mode 100644 openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v rename openfpga_flow/benchmarks/{Test_Modes/test_modes.act => test_modes/k6_N10/K6N10_test_modes.act} (100%) rename openfpga_flow/benchmarks/{Test_Modes/test_modes.blif => test_modes/k6_N10/K6N10_test_modes.blif} (100%) rename openfpga_flow/benchmarks/{Test_Modes/test_modes.v => test_modes/k6_N10/K6N10_test_modes.v} (100%) create mode 100644 openfpga_flow/tasks/single_mode/config/task.conf diff --git a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml new file mode 100644 index 000000000..29f091673 --- /dev/null +++ b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml @@ -0,0 +1,631 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[5:0] clb.O[1:0] + clb.I[11:6] clb.O[3:2] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act new file mode 100644 index 000000000..159a6071f --- /dev/null +++ b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act @@ -0,0 +1,16 @@ +clk 0.5 0.2 +a 0.5 0.2 +b 0.5 0.2 +c 0.5 0.2 +XOR 0.5 0.2 +XNOR 0.5 0.2 +OR 0.5 0.2 +NOR 0.5 0.2 +AND 0.5 0.2 +NAND 0.5 0.2 +XOR_sync 0.5 0.2 +XNOR_sync 0.5 0.2 +OR_sync 0.5 0.2 +NOR_sync 0.5 0.2 +AND_sync 0.5 0.2 +NAND_sync 0.5 0.2 diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif new file mode 100644 index 000000000..d74125339 --- /dev/null +++ b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif @@ -0,0 +1,40 @@ +.model K4n4_test +.inputs clk a b c +.outputs XOR XNOR AND NAND OR NOR XOR_sync XNOR_sync AND_sync NAND_sync OR_sync NOR_sync + +.names a b c XOR +100 1 +010 1 +001 1 +111 1 + +.names a b c XNOR +011 1 +101 1 +110 1 +000 1 + +.names a b c AND +111 1 + +.names a b c NAND +0-- 1 +-0- 1 +--0 1 + +.names a b c OR +1-- 1 +-1- 1 +--1 1 + +.names a b c NOR +000 1 + +.latch XOR XOR_sync re clk 0 +.latch XNOR XNOR_sync re clk 0 +.latch OR OR_sync re clk 0 +.latch NOR NOR_sync re clk 0 +.latch AND AND_sync re clk 0 +.latch NAND NAND_sync re clk 0 + +.end diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v new file mode 100644 index 000000000..5826ed571 --- /dev/null +++ b/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps + +module K4n4_test ( + clk, + a, + b, + c, + XOR, + XNOR, + AND, + NAND, + OR, + NOR, + XOR_sync, + XNOR_sync, + AND_sync, + NAND_sync, + OR_sync, + NOR_sync ); + + input wire clk; + input wire a; + input wire b; + input wire c; + output wire XOR; + output wire XNOR; + output wire AND; + output wire NAND; + output wire OR; + output wire NOR; + output reg XOR_sync; + output reg XNOR_sync; + output reg AND_sync; + output reg NAND_sync; + output reg OR_sync; + output reg NOR_sync; + + assign XOR = a ^ b ^ c; + assign XNOR = !XOR; + assign OR = a || b || c; + assign NOR = !( a || b || c); + assign AND = a && b && c; + assign NAND = !(a && b && c); + + always @(posedge clk) begin + XOR_sync = XOR; + XNOR_sync = XNOR; + OR_sync = OR; + NOR_sync = NOR; + AND_sync = AND; + NAND_sync = NAND; + end + +endmodule diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.act b/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act similarity index 100% rename from openfpga_flow/benchmarks/Test_Modes/test_modes.act rename to openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.blif b/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif similarity index 100% rename from openfpga_flow/benchmarks/Test_Modes/test_modes.blif rename to openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.v b/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v similarity index 100% rename from openfpga_flow/benchmarks/Test_Modes/test_modes.v rename to openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index c54ce8403..7cadfce2c 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -25,12 +25,12 @@ arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO #arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif [SYNTHESIS_PARAM] bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v bench0_chan_width = 300 #[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf index 0634a32c5..2a640bfae 100644 --- a/openfpga_flow/tasks/explicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf @@ -19,12 +19,12 @@ arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem #arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif [SYNTHESIS_PARAM] bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] diff --git a/openfpga_flow/tasks/single_mode/config/task.conf b/openfpga_flow/tasks/single_mode/config/task.conf new file mode 100644 index 000000000..f7086ab77 --- /dev/null +++ b/openfpga_flow/tasks/single_mode/config/task.conf @@ -0,0 +1,58 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = K4n4_test +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v +bench0_chan_width = 100 + +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_verilog_explicit_mapping= +#vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= diff --git a/openfpga_flow/tasks/tileable_routing/config/task.conf b/openfpga_flow/tasks/tileable_routing/config/task.conf index 3a7f092a6..860a9ba32 100644 --- a/openfpga_flow/tasks/tileable_routing/config/task.conf +++ b/openfpga_flow/tasks/tileable_routing/config/task.conf @@ -18,12 +18,12 @@ fpga_flow=vpr_blif arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif [SYNTHESIS_PARAM] bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v bench0_chan_width = 300 [SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] From 10491c429145ee5391e66ad5aca3301066ab7e46 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 28 Oct 2019 17:04:10 -0600 Subject: [PATCH 352/482] bring single mode test case online with bug fixing --- .travis/script.sh | 2 +- .../tasks/single_mode/config/task.conf | 4 +- .../verilog_formal_random_top_testbench.cpp | 37 ++++++++++++++----- 3 files changed, 30 insertions(+), 13 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index 73e2a1ed2..599c35adf 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3 +python3 openfpga_flow/scripts/run_fpga_task.py single_mode blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3 end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/single_mode/config/task.conf b/openfpga_flow/tasks/single_mode/config/task.conf index f7086ab77..4d721002b 100644 --- a/openfpga_flow/tasks/single_mode/config/task.conf +++ b/openfpga_flow/tasks/single_mode/config/task.conf @@ -53,6 +53,6 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_verilog_explicit_mapping= -#vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_verilog_explicit_mapping= +vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 6ba4c534c..8ac025eff 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -426,6 +426,20 @@ void print_verilog_top_random_stimuli(std::fstream& fp, print_verilog_comment(fp, std::string("----- Initialization -------")); fp << "\tinitial begin" << std::endl; + /* Create clock stimuli */ + BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; + fp << "\t\twhile(1) begin" << std::endl; + fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; + fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << " <= !"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << ";" << std::endl; + fp << "\t\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + for (const t_logical_block& lb : L_logical_blocks) { /* Bypass non-I/O logical blocks ! */ if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { @@ -441,17 +455,20 @@ void print_verilog_top_random_stimuli(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; - /* Creae clock stimuli */ - BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; - fp << "\t\twhile(1) begin" << std::endl; - fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; - fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); - fp << " <= !"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); - fp << ";" << std::endl; - fp << "\t\tend" << std::endl; + /* Set 0 to registers for checking flags */ + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + std::string(CHECKFLAG_PORT_POSTFIX)), 1); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; + } + fp << "\tend" << std::endl; + /* Finish initialization */ /* Add an empty line as splitter */ fp << std::endl; From 7c116aac2ff5c96bc180ce5f048bcfd9e74bfb67 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Oct 2019 13:54:35 -0600 Subject: [PATCH 353/482] added Verilog generation for preconfig top module --- .../libarchfpga/SRC/check_circuit_library.cpp | 77 +++- .../libarchfpga/SRC/circuit_library_utils.cpp | 32 ++ .../libarchfpga/SRC/circuit_library_utils.h | 2 + .../SRC/fpga_x2p/base/bitstream_manager.cpp | 18 + .../vpr/SRC/fpga_x2p/base/bitstream_manager.h | 3 + .../fpga_x2p/base/bitstream_manager_utils.cpp | 1 - vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 16 +- .../base/fpga_x2p_benchmark_utils.cpp | 146 ++++++ .../fpga_x2p/base/fpga_x2p_benchmark_utils.h | 16 + .../vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c | 3 +- vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h | 9 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 42 +- .../vpr/SRC/fpga_x2p/verilog/verilog_api.h | 8 + .../verilog_formal_random_top_testbench.cpp | 25 +- .../verilog/verilog_preconfig_top_module.cpp | 429 ++++++++++++++++++ .../verilog/verilog_preconfig_top_module.h | 24 + .../verilog_verification_top_netlist.c | 2 +- .../verilog_verification_top_netlist.h | 2 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 80 ++-- .../fpga_x2p/verilog/verilog_writer_utils.h | 9 +- 20 files changed, 866 insertions(+), 78 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index f9e3bb9e1..4ceab180e 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -49,7 +49,6 @@ #include "check_circuit_library.h" - /************************************************************************ * Circuit models have unique names, return the number of errors * If not found, we give an error @@ -394,6 +393,82 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { num_err++; } + /* Check all the global ports which sare the same name also share the same attributes: + * default_value, is_config, is_reset, is_set etc. + */ + std::vector global_ports; + + /* Collect all the global ports */ + for (auto port : circuit_lib.ports()) { + /* By pass non-global ports*/ + if (false == circuit_lib.port_is_global(port)) { + continue; + } + global_ports.push_back(port); + } + + for (size_t iport = 0; iport < global_ports.size() - 1; ++iport) { + for (size_t jport = iport + 1; jport < global_ports.size(); ++jport) { + /* Bypass those do not share the same name */ + if (0 != circuit_lib.port_lib_name(global_ports[iport]).compare(circuit_lib.port_lib_name(global_ports[jport]))) { + continue; + } + + /* Check if a same port share the same attributes */ + CircuitModelId iport_parent_model = circuit_lib.port_parent_model(global_ports[iport]); + CircuitModelId jport_parent_model = circuit_lib.port_parent_model(global_ports[jport]); + + if (circuit_lib.port_default_value(global_ports[iport]) != circuit_lib.port_default_value(global_ports[jport])) { + vpr_printf(TIO_MESSAGE_ERROR, + "Global ports %s from circuit model %s and %s share the same name but have different dfefault values(%lu and %lu)!\n", + circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.model_name(iport_parent_model).c_str(), + circuit_lib.model_name(jport_parent_model).c_str(), + circuit_lib.port_default_value(global_ports[iport]), + circuit_lib.port_default_value(global_ports[jport]) + ); + num_err++; + } + + if (circuit_lib.port_is_reset(global_ports[iport]) != circuit_lib.port_is_reset(global_ports[jport])) { + vpr_printf(TIO_MESSAGE_ERROR, + "Global ports %s from circuit model %s and %s share the same name but have different is_reset attributes!\n", + circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.model_name(iport_parent_model).c_str(), + circuit_lib.model_name(jport_parent_model).c_str() + ); + num_err++; + } + if (circuit_lib.port_is_set(global_ports[iport]) != circuit_lib.port_is_set(global_ports[jport])) { + vpr_printf(TIO_MESSAGE_ERROR, + "Global ports %s from circuit model %s and %s share the same name but have different is_set attributes!\n", + circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.model_name(iport_parent_model).c_str(), + circuit_lib.model_name(jport_parent_model).c_str() + ); + num_err++; + } + if (circuit_lib.port_is_config_enable(global_ports[iport]) != circuit_lib.port_is_config_enable(global_ports[jport])) { + vpr_printf(TIO_MESSAGE_ERROR, + "Global ports %s from circuit model %s and %s share the same name but have different is_config_enable attributes!\n", + circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.model_name(iport_parent_model).c_str(), + circuit_lib.model_name(jport_parent_model).c_str() + ); + num_err++; + } + if (circuit_lib.port_is_prog(global_ports[iport]) != circuit_lib.port_is_prog(global_ports[jport])) { + vpr_printf(TIO_MESSAGE_ERROR, + "Global ports %s from circuit model %s and %s share the same name but have different is_prog attributes!\n", + circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.model_name(iport_parent_model).c_str(), + circuit_lib.model_name(jport_parent_model).c_str() + ); + num_err++; + } + } + } + return num_err; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp index 3a0a7d91a..cb7641b0a 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -208,3 +208,35 @@ size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, return num_config_bits; } + +/******************************************************************** + * A generic function to find all the global ports in a circuit library + * + * IMPORTANT: This function will uniquify the global ports whose share + * share the same name !!! + *******************************************************************/ +std::vector find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) { + std::vector global_ports; + + for (auto port : circuit_lib.ports()) { + /* By pass non-global ports*/ + if (false == circuit_lib.port_is_global(port)) { + continue; + } + /* Check if a same port with the same name has already been in the list */ + bool add_to_list = true; + for (const auto& global_port : global_ports) { + if (0 == circuit_lib.port_lib_name(port).compare(circuit_lib.port_lib_name(global_port))) { + /* Same name, skip list update */ + add_to_list = false; + break; + } + } + if (true == add_to_list) { + /* Add the global_port to the list */ + global_ports.push_back(port); + } + } + + return global_ports; +} diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h index 03485a014..c0c8251c7 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h @@ -27,4 +27,6 @@ size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); +std::vector find_circuit_library_global_ports(const CircuitLibrary& circuit_lib); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp index f5de0b2bc..9daa919d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp @@ -64,6 +64,24 @@ ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) cons return bit_parent_block_ids_[bit_id]; } +size_t BitstreamManager::bit_index_in_parent_block(const ConfigBitId& bit_id) const { + /* Ensure the input ids are valid */ + VTR_ASSERT(true == valid_bit_id(bit_id)); + + ConfigBlockId bit_parent_block = bit_parent_block_ids_[bit_id]; + + VTR_ASSERT(true == valid_block_id(bit_parent_block)); + + for (size_t index = 0; index < block_bits(bit_parent_block).size(); ++index) { + if (bit_id == block_bits(bit_parent_block)[index]) { + return index; + } + } + + /* Not found, return in valid value */ + return size_t(-1); +} + /* Find the child block in a bitstream manager with a given name */ ConfigBlockId BitstreamManager::find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h index e09526199..a5c3a0f02 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h @@ -73,6 +73,9 @@ class BitstreamManager { /* Find the parent block of a bit */ ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const; + /* Find the index of a configuration bit in its parent block */ + size_t bit_index_in_parent_block(const ConfigBitId& bit_id) const; + /* Find the child block in a bitstream manager with a given name */ ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp index 24fad3fd3..9a17662eb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp @@ -36,7 +36,6 @@ std::vector find_bitstream_manager_block_hierarchy(const Bitstrea return block_hierarchy; } - /******************************************************************** * Find all the top-level blocks in a bitstream manager, * which have no parents diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index c24dd30a8..4665bc0bb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -81,6 +81,18 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, clb2clb_directs.push_back(clb2clb_direct[i]); } + /* Organize a vector for logical blocks to feed Verilog generator */ + std::vector L_logical_blocks; + for (int i = 0; i < num_logical_blocks; ++i) { + L_logical_blocks.push_back(logical_block[i]); + } + + /* Organize a vector for blocks to feed Verilog generator */ + std::vector L_blocks; + for (int i = 0; i < num_blocks; ++i) { + L_blocks.push_back(block[i]); + } + /* Build module graphs */ ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib, device_size, grids, @@ -122,7 +134,9 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* Xifan TANG: Synthesizable verilog dumping */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) { - vpr_fpga_verilog(module_manager, mux_lib, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); + vpr_fpga_verilog(module_manager, bitstream_manager, fabric_bitstream, mux_lib, + L_logical_blocks, device_size, grids, L_blocks, + vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); } /* Xifan Tang: Bitstream Generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp new file mode 100644 index 000000000..6931da0da --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp @@ -0,0 +1,146 @@ +/******************************************************************** + * This file includes most utilized functions to manipulate data + * structures that are related to the input benchmark circuit + *******************************************************************/ +#include "vtr_assert.h" +#include "sides.h" + +#include "fpga_x2p_benchmark_utils.h" + +/******************************************************************** + * Find the clock port name to be used in this testbench + *******************************************************************/ +std::vector find_benchmark_clock_port_name(const std::vector& L_logical_blocks) { + std::vector clock_port_names; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + /* Find the clock signals */ + if ( (VPACK_INPAD == lb.type) && (TRUE == lb.is_clock) ) { + clock_port_names.push_back(std::string(lb.name)); + } + } + + return clock_port_names; +} + +/******************************************************************** + * Find the I/O index in the FPGA top-level module + * that an I/O logical block is mapped to + * Note that this function follows the sequence in I/O grid instanciation + * in build_top_module(), where I/Os are instanciated from + * TOP, RIGHT, BOTTOM to LEFT sides. + * Therefore, the I/O indices will follow this sequence, where 0 starts + * from the TOP side + * + * This function will use the clb_index in each t_logical_block + * to spot a t_block that the I/O is mapped + * Through the t_block, we can find a detailed coordinate (x,y,z), + * based on which we can infer the I/O index in the top-level module + * + * Restrictions: if you change the sequence in I/O grid instanciation + * in the top-level module, this function MUST be changed!!! + *******************************************************************/ +size_t find_benchmark_io_index(const t_logical_block& io_lb, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks) { + /* Ensure this is an I/O logical block */ + VTR_ASSERT(VPACK_INPAD == io_lb.type || VPACK_OUTPAD == io_lb.type); + + /* Ensure the clb index in the range */ + VTR_ASSERT((size_t)io_lb.clb_index < L_blocks.size() ); + + /* Get the block (x, y, z) */ + size_t x = L_blocks[(size_t)io_lb.clb_index].x; + size_t y = L_blocks[(size_t)io_lb.clb_index].y; + size_t z = L_blocks[(size_t)io_lb.clb_index].z; + + /* Ensure the (x,y,z) is in the range of device */ + VTR_ASSERT( x < device_size.x() && y < device_size.y() ); + VTR_ASSERT( z < (size_t)L_grids[x][y].type->capacity ); + + /* Infer the I/O index: + * If the I/O is on the top side, the index will start from 0 + * If the I/O is on the right side, the index will start from capacity * nx + * If the I/O is on the bottom side, the index will start from capacity * (nx + ny) + * If the I/O is on the bottom side, the index will start from capacity * (2 * nx + ny) + */ + std::map io_index_offset; + io_index_offset[TOP] = 0; + + /* For RIGHT side, sum the capacity of TOP side grids */ + io_index_offset[RIGHT] = 0; + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_index_offset[RIGHT] += L_grids[ix][device_size.y() - 1].type->capacity; + } + + /* For BOTTOM side, sum the capacity of RIGHT side grids */ + io_index_offset[BOTTOM] = io_index_offset[RIGHT]; + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_index_offset[BOTTOM] += L_grids[device_size.x() - 1][iy].type->capacity; + } + + /* For LEFT side, sum the capacity of BOTTOM side grids */ + io_index_offset[LEFT] = io_index_offset[BOTTOM]; + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_index_offset[LEFT] += L_grids[ix][0].type->capacity; + } + + /* Find I/O grid side, I do not capasulate this in a function, because it is not so general */ + e_side io_side = NUM_SIDES; + if (0 == y) { + io_side = BOTTOM; + } + if (0 == x) { + io_side = LEFT; + } + if (device_size.x() - 1 == x) { + io_side = RIGHT; + } + if (device_size.y() - 1 == y) { + io_side = TOP; + } + VTR_ASSERT(NUM_SIDES != io_side); + + /* Now generate the io index */ + size_t io_index = size_t(-1); + /* TOP side I/Os */ + if (device_size.y() - 1 == y) { + io_index = io_index_offset[io_side]; + for (size_t ix = 1; ix < x - 1; ++ix) { + io_index += L_grids[ix][y].type->capacity; + } + io_index += z; + } + /* RIGHT side I/Os */ + if (device_size.x() - 1 == x) { + io_index = io_index_offset[io_side]; + for (size_t iy = 1; iy < y - 1; ++iy) { + io_index += L_grids[x][iy].type->capacity; + } + io_index += z; + } + /* BOTTOM side I/Os */ + if (0 == y) { + io_index = io_index_offset[io_side]; + for (size_t ix = 1; ix < x - 1; ++ix) { + io_index += L_grids[ix][y].type->capacity; + } + io_index += z; + } + /* LEFT side I/Os */ + if (0 == x) { + io_index = io_index_offset[io_side]; + for (size_t iy = 1; iy < y - 1; ++iy) { + io_index += L_grids[x][iy].type->capacity; + } + io_index += z; + } + + return io_index; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h new file mode 100644 index 000000000..5cdbd5049 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h @@ -0,0 +1,16 @@ +#ifndef FPGA_X2P_BENCHMARK_UTILS_H +#define FPGA_X2P_BENCHMARK_UTILS_H + +#include +#include +#include "vpr_types.h" +#include "vtr_geometry.h" + +std::vector find_benchmark_clock_port_name(const std::vector& L_logical_blocks); + +size_t find_benchmark_io_index(const t_logical_block& io_lb, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c index b1551efde..65598d97d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c @@ -51,7 +51,8 @@ void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) { return; } - vpr_fpga_verilog(env->module_manager, env->mux_lib, + vpr_fpga_verilog(env->module_manager, env->bitstream_manager, env->fabric_bitstream, + env->mux_lib, env->logical_blocks, env->device_size, env->grids, env->blocks, env->vpr_setup, env->arch, env->vpr_setup.FileNameOpts.CircuitName); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h index fe80b970b..21325b4da 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h @@ -1,9 +1,12 @@ #ifndef SHELL_TYPES_H #define SHELL_TYPES_H +#include +#include "vtr_geometry.h" #include "vpr_types.h" #include "mux_library.h" #include "module_manager.h" +#include "bitstream_manager.h" typedef struct s_cmd_category t_cmd_category; typedef struct s_shell_cmd t_shell_cmd; @@ -35,7 +38,13 @@ struct s_shell_cmd { struct s_shell_env { ModuleManager module_manager; + BitstreamManager bitstream_manager; + std::vector fabric_bitstream; MuxLibrary mux_lib; + std::vector logical_blocks; + vtr::Point device_size; + std::vector> grids; + std::vector blocks; t_arch arch; t_vpr_setup vpr_setup; t_shell_cmd* cmd; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 2052b6828..e06b825f6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -38,6 +38,7 @@ #include "module_manager.h" #include "mux_library.h" #include "mux_library_builder.h" +#include "circuit_library_utils.h" /* Include SynVerilog headers */ #include "verilog_global.h" @@ -53,6 +54,7 @@ #include "verilog_top_testbench.h" #include "verilog_autocheck_top_testbench.h" #include "verilog_formal_random_top_testbench.h" +#include "verilog_preconfig_top_module.h" #include "verilog_verification_top_netlist.h" #include "verilog_modelsim_autodeck.h" #include "verilog_report_timing.h" @@ -119,7 +121,13 @@ void free_global_routing_conf_bits() { /* Top-level function*/ void vpr_fpga_verilog(ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, const MuxLibrary& mux_lib, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, t_vpr_setup vpr_setup, t_arch Arch, char* circuit_name) { @@ -149,8 +157,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, char* blif_testbench_file_path = NULL; char* bitstream_file_name = NULL; char* bitstream_file_path = NULL; - char* formal_verification_top_netlist_file_name = NULL; - char* formal_verification_top_netlist_file_path = NULL; char* autocheck_top_testbench_file_name = NULL; char* autocheck_top_testbench_file_path = NULL; @@ -393,20 +399,23 @@ void vpr_fpga_verilog(ModuleManager& module_manager, my_free(top_testbench_file_name); my_free(top_testbench_file_path); } - - /* TODO: this should be outside this function! - * Create vectors for logical blocks - */ - std::vector L_logical_blocks; - for (int i = 0; i < num_logical_blocks; ++i) { - L_logical_blocks.push_back(logical_block[i]); - } + + std::vector global_ports = find_circuit_library_global_ports(Arch.spice->circuit_lib); if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) { - formal_verification_top_netlist_file_name = my_strcat(chomped_circuit_name, formal_verification_verilog_file_postfix); - formal_verification_top_netlist_file_path = my_strcat(src_dir_path, formal_verification_top_netlist_file_name); + std::string formal_verification_top_netlist_file_path = std::string(src_dir_path) + + std::string(chomped_circuit_name) + + std::string(formal_verification_verilog_file_postfix); + /* TODO: this is an old function, to be shadowed */ dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, - formal_verification_top_netlist_file_path, src_dir_path); + formal_verification_top_netlist_file_path.c_str(), src_dir_path); + /* TODO: new function: to be tested */ + print_verilog_preconfig_top_module(module_manager, bitstream_manager, fabric_bitstream, + Arch.spice->circuit_lib, global_ports, L_logical_blocks, + device_size, L_grids, L_blocks, + std::string(chomped_circuit_name), formal_verification_top_netlist_file_path + std::string(".bak"), + std::string(src_dir_path)); + /* Output script for formality */ write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, fm_dir_path, @@ -421,10 +430,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); - - /* Free */ - my_free(formal_verification_top_netlist_file_name); - my_free(formal_verification_top_netlist_file_path); } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { @@ -433,9 +438,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, autocheck_top_testbench_file_path, src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); - /* Free */ - my_free(autocheck_top_testbench_file_name); - my_free(autocheck_top_testbench_file_path); } /* Output Modelsim Autodeck scripts */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h index 9fc1e4b25..95358f85c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h @@ -1,12 +1,20 @@ #ifndef VERILOG_API_H #define VERILOG_API_H +#include #include "vpr_types.h" #include "mux_library.h" #include "module_manager.h" +#include "bitstream_manager.h" void vpr_fpga_verilog(ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, const MuxLibrary& mux_lib, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, t_vpr_setup vpr_setup, t_arch Arch, char* circuit_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 8ac025eff..777f55fd8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -18,6 +18,7 @@ /* Include FPGA-X2P headers*/ #include "fpga_x2p_utils.h" +#include "fpga_x2p_benchmark_utils.h" /* Include FPGA Verilog headers*/ #include "verilog_global.h" @@ -37,28 +38,6 @@ constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT"; constexpr char* ERROR_COUNTER = "nb_error"; constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; -/******************************************************************** - * Find the clock port name to be used in this testbench - *******************************************************************/ -static -std::vector find_verilog_top_clock_port_name(const std::vector& L_logical_blocks) { - std::vector clock_port_names; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - /* Find the clock signals */ - if ( (VPACK_INPAD == lb.type) && (TRUE == lb.is_clock) ) { - clock_port_names.push_back(std::string(lb.name)); - } - } - - return clock_port_names; -} - /******************************************************************** * Generate the clock port name to be used in this testbench * @@ -568,7 +547,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, print_verilog_include_netlist(fp, std::string(fpga_verilog_opts.reference_verilog_benchmark_file)); /* Preparation: find all the clock ports */ - std::vector clock_port_names = find_verilog_top_clock_port_name(L_logical_blocks); + std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); /* Start of testbench */ print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, L_logical_blocks); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp new file mode 100644 index 000000000..ced31628d --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -0,0 +1,429 @@ +/******************************************************************** + * This file includes functions that are used to generate + * a Verilog module of a pre-configured FPGA fabric + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "device_port.h" +#include "util.h" + +#include "bitstream_manager_utils.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_benchmark_utils.h" + +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_preconfig_top_module.h" + +/******************************************************************** + * Print module declaration and ports for the pre-configured + * FPGA top module + * The module ports do exactly match the input benchmark + *******************************************************************/ +static +void print_verilog_preconfig_top_module_ports(std::fstream& fp, + const std::string& circuit_name, + const std::vector& L_logical_blocks) { + + /* Validate the file stream */ + check_file_handler(fp); + + /* Module declaration */ + fp << "module " << circuit_name << std::string(formal_verification_top_module_postfix); + fp << " (" << std::endl; + + /* Add module ports */ + size_t port_counter = 0; + + /* Port type-to-type mapping */ + std::map port_type2type_map; + port_type2type_map[VPACK_INPAD] = VERILOG_PORT_INPUT; + port_type2type_map[VPACK_OUTPAD] = VERILOG_PORT_OUTPUT; + + /* Print all the I/Os of the circuit implementation to be tested*/ + for (const t_logical_block& lb : L_logical_blocks) { + /* We only care I/O logical blocks !*/ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + if (0 < port_counter) { + fp << "," << std::endl; + } + /* Both input and output ports have only size of 1 */ + BasicPort module_port(std::string(std::string(lb.name) + std::string(formal_verification_top_module_port_postfix)), 1); + fp << generate_verilog_port(port_type2type_map[lb.type], module_port); + + /* Update port counter */ + port_counter++; + } + + fp << ");" << std::endl; + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print internal wires for the pre-configured FPGA top module + * The internal wires are tailored for the ports of FPGA top module + * which will be different in various configuration protocols + *******************************************************************/ +static +void print_verilog_preconfig_top_module_internal_wires(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Global ports of top-level module */ + print_verilog_comment(fp, std::string("----- Global ports of FPGA fabric -----")); + for (const BasicPort& global_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, global_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Datapath I/Os of FPGA fabric */ + print_verilog_comment(fp, std::string("----- I/Os of FPGA fabric -----")); + for (const BasicPort& gpio_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, gpio_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Datapath I/Os of FPGA fabric */ + print_verilog_comment(fp, std::string("----- Configuration protocols of FPGA fabric -----")); + for (const BasicPort& input_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_INPUT_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, input_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print an instance of the FPGA top-level module + *******************************************************************/ +static +void print_verilog_preconfig_top_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Include defined top-level module */ + print_verilog_comment(fp, std::string("----- FPGA top-level module to be capsulated -----")); + + /* Create an empty port-to-port name mapping, because we use default names */ + std::map port2port_name_map; + + /* Use explicit port mapping for a clean instanciation */ + print_verilog_module_instance(fp, module_manager, top_module, + std::string(formal_verification_top_module_uut_name), + port2port_name_map, true); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Connect global ports of FPGA top module to constants except: + * 1. operating clock, which should be wired to the clock port of + * this pre-configured FPGA top module + *******************************************************************/ +static +void print_verilog_preconfig_top_module_connect_global_ports(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& benchmark_clock_port_names) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Begin Connect Global ports of FPGA top module -----")); + + /* Global ports of the top module in module manager do not carry any attributes, + * such as is_clock, is_set, etc. + * Therefore, for each global port in the top module, we find the circuit port in the circuit library + * which share the same name. We can access to the attributes. + * To gurantee the correct link between global ports in module manager and those in circuit library + * We have performed some critical check in check_circuit_library() for global ports, + * where we guarantee all the global ports share the same name must have the same attributes. + * So that each global port with the same name is unique! + */ + for (const BasicPort& module_global_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { + CircuitPortId linked_circuit_port_id = CircuitPortId::INVALID(); + /* Find the circuit port with the same name */ + for (const CircuitPortId& circuit_port_id : global_ports) { + if (0 != module_global_port.get_name().compare(circuit_lib.port_lib_name(circuit_port_id))) { + continue; + } + linked_circuit_port_id = circuit_port_id; + break; + } + /* Must find one valid circuit port */ + VTR_ASSERT(CircuitPortId::INVALID() != linked_circuit_port_id); + /* Port size should match! */ + VTR_ASSERT(module_global_port.get_width() == circuit_lib.port_size(linked_circuit_port_id)); + /* Now, for operating clock port, we should wire it to the clock of benchmark! */ + if ( (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(linked_circuit_port_id)) + && (false == circuit_lib.port_is_prog(linked_circuit_port_id)) ) { + /* Wiring to each pin of the global port: benchmark clock is always 1-bit */ + for (const size_t& pin : module_global_port.pins()) { + for (const std::string& clock_port_name : benchmark_clock_port_names) { + BasicPort module_clock_pin(module_global_port.get_name(), pin, pin); + BasicPort benchmark_clock_pin(clock_port_name + std::string(formal_verification_top_module_port_postfix), 1); + print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin, false); + } + } + /* Finish, go to the next */ + continue; + } + + /* For other ports, give an default value */ + std::vector default_values(module_global_port.get_width(), circuit_lib.port_default_value(linked_circuit_port_id)); + print_verilog_wire_constant_values(fp, module_global_port, default_values); + } + + print_verilog_comment(fp, std::string("----- End Connect Global ports of FPGA top module -----")); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * This function adds stimuli to I/Os of FPGA fabric + * 1. For mapped I/Os, this function will wire them to the input ports + * of the pre-configured FPGA top module + * 2. For unmapped I/Os, this function will assign a constant value + * by default + *******************************************************************/ +static +void print_verilog_preconfig_top_module_connect_ios(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks) { + /* Validate the file stream */ + check_file_handler(fp); + + /* In this function, we support only 1 type of I/Os */ + VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size()); + BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0]; + + /* Keep tracking which I/Os have been used */ + std::vector io_used(module_io_port.get_width(), false); + + /* See if this I/O should be wired to a benchmark input/output */ + /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs + * This brings convenience to checking functionality + */ + print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); + for (const t_logical_block& io_lb : L_logical_blocks) { + /* We only care I/O logical blocks !*/ + if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) { + continue; + } + + /* Find the index of the mapped GPIO in top-level FPGA fabric */ + size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks); + + /* Ensure that IO index is in range */ + BasicPort module_mapped_io_port = module_io_port; + /* Set the port pin index */ + VTR_ASSERT(io_index < module_mapped_io_port.get_width()); + module_mapped_io_port.set_width(io_index, io_index); + + /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 */ + BasicPort benchmark_io_port(std::string(std::string(io_lb.name)+ std::string(formal_verification_top_module_port_postfix)), 1); + + print_verilog_comment(fp, std::string("----- Blif Benchmark inout " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); + print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); + + /* Mark this I/O has been used/wired */ + io_used[io_index] = true; + } + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Wire the unused iopads to a constant */ + print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----")); + for (size_t io_index = 0; io_index < io_used.size(); ++io_index) { + /* Bypass used iopads */ + if (true == io_used[io_index]) { + continue; + } + + /* Wire to a contant */ + BasicPort module_unused_io_port = module_io_port; + /* Set the port pin index */ + module_unused_io_port.set_width(io_index, io_index); + + std::vector default_values(module_unused_io_port.get_width(), verilog_default_signal_init_value); + print_verilog_wire_constant_values(fp, module_unused_io_port, default_values); + } + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Impose the bitstream on the configuration memories + *******************************************************************/ +static +void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream) { + print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); + + for (const ConfigBitId& config_bit_id : fabric_bitstream) { + ConfigBlockId bit_parent_block = bitstream_manager.bit_parent_block(config_bit_id); + /* Build the hierarchical path of the configuration bit in modules */ + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bit_parent_block); + /* Drop the first block, which is the top module, it should be replaced by the instance name here */ + /* Ensure that this is the module we want to drop! */ + VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); + block_hierarchy.erase(block_hierarchy.begin()); + /* Build the full hierarchy path */ + std::string bit_hierarchy_path(formal_verification_top_module_uut_name); + for (const ConfigBlockId& temp_block : block_hierarchy) { + bit_hierarchy_path += std::string("."); + bit_hierarchy_path += bitstream_manager.block_name(temp_block); + } + bit_hierarchy_path += std::string("."); + bit_hierarchy_path += generate_configuration_chain_data_out_name(); + + /* Find the bit index in the parent block */ + BasicPort config_port(bit_hierarchy_path, + bitstream_manager.bit_index_in_parent_block(config_bit_id), + bitstream_manager.bit_index_in_parent_block(config_bit_id)); + + /* Wire it to the configuration bit */ + std::vector default_values(config_port.get_width(), bitstream_manager.bit_value(config_bit_id)); + print_verilog_wire_constant_values(fp, config_port, default_values); + } + + print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); +} + + +/******************************************************************** + * Top-level function to generate a Verilog module of + * a pre-configured FPGA fabric. + * + * Pre-configured FPGA fabric + * +-------------------------------------------- + * | + * | FPGA fabric + * | +-------------------------------+ + * | | | + * | 0/1---->|FPGA global ports | + * | | | + * benchmark_clock----->|--------->|FPGA_clock | + * | | | + * benchmark_inputs---->|--------->|FPGA mapped I/Os | + * | | | + * benchmark_outputs<---|<---------|FPGA mapped I/Os | + * | | | + * | 0/1---->|FPGA unmapped I/Os | + * | | | + * fabric_bitstream---->|--------->|Internal_configuration_ports | + * | +-------------------------------+ + * | + * +------------------------------------------- + * + * Note: we do NOT put this module in the module manager. + * Because, it is not a standard module, where we force configuration signals + * This module is a wrapper for the FPGA fabric to be compatible in + * the port map of input benchmark. + * It includes wires to force constant values to part of FPGA datapath I/Os + * All these are hard to implement as a module in module manager + *******************************************************************/ +void print_verilog_preconfig_top_module(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir) { + vpr_printf(TIO_MESSAGE_INFO, + "Writing pre-configured FPGA top-level Verilog netlist for design %s...", + circuit_name.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Generate a brief description on the Verilog file*/ + std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name; + print_verilog_file_header(fp, title); + + /* Print preprocessing flags and external netlists */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(defines_verilog_simulation_file_name))); + + /* Print module declaration and ports */ + print_verilog_preconfig_top_module_ports(fp, circuit_name, L_logical_blocks); + + /* Find the top_module */ + ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + + /* Print internal wires */ + print_verilog_preconfig_top_module_internal_wires(fp, module_manager, top_module); + + /* Instanciate FPGA top-level module */ + print_verilog_preconfig_top_instance(fp, module_manager, top_module); + + /* Find clock ports in benchmark */ + std::vector benchmark_clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); + + /* Connect FPGA top module global ports to constant or benchmark global signals! */ + print_verilog_preconfig_top_module_connect_global_ports(fp, module_manager, top_module, + circuit_lib, global_ports, + benchmark_clock_port_names); + + /* Connect I/Os to benchmark I/Os or constant driver */ + print_verilog_preconfig_top_module_connect_ios(fp, module_manager, top_module, + L_logical_blocks, device_size, L_grids, + L_blocks); + + /* Assign FPGA internal SRAM/Memory ports to bitstream values */ + print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, + bitstream_manager, fabric_bitstream); + + /* Testbench ends*/ + print_verilog_module_end(fp, std::string(circuit_name) + std::string(formal_verification_top_module_postfix)); + + /* Close the file stream */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h new file mode 100644 index 000000000..441de0836 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h @@ -0,0 +1,24 @@ +#ifndef VERILOG_PRECONFIG_TOP_MODULE_H +#define VERILOG_PRECONFIG_TOP_MODULE_H + +#include +#include +#include "spice_types.h" +#include "vpr_types.h" +#include "module_manager.h" +#include "bitstream_manager.h" + +void print_verilog_preconfig_top_module(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c index 74ac2317d..8a4c72a19 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c @@ -387,7 +387,7 @@ void dump_verilog_formal_verification_top_netlist_initialization(t_sram_orgz_inf */ void dump_verilog_formal_verification_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, - char* top_netlist_name, + const char* top_netlist_name, char* verilog_dir_path) { FILE* fp = NULL; char* title = my_strcat("FPGA Verilog Top-level netlist in formal verification purpose of Design: ", circuit_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.h index fb8e6ed1b..776374152 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.h @@ -1,6 +1,6 @@ void dump_verilog_formal_verification_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, - char* top_netlist_name, + const char* top_netlist_name, char* verilog_dir_path); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 555f059d0..66174ebb8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -284,46 +284,46 @@ void print_verilog_module_declaration(std::fstream& fp, print_verilog_module_ports(fp, module_manager, module_id); } -/************************************************ - * Print an instance for a Verilog module - * This function will output the port map - * by referring to a port-to-port mapping: + +/******************************************************************** + * Print an instance in Verilog format (a generic version) + * This function will require user to provide an instance name + * + * This function will output the port map by referring to a port-to-port + * mapping: * -> - * The key of the port-to-port mapping is the - * port name of the module: - * The value of the port-to-port mapping is the - * port information of the instance - * With link between module and instance, the function - * can output a Verilog instance easily, supporting - * both explicit port mapping: + * The key of the port-to-port mapping is the port name of the module: + * The value of the port-to-port mapping is the port information of the instance + * With link between module and instance, the function can output a Verilog + * instance easily, supporting both explicit port mapping: * .() * and inexplicit port mapping * * - * Note that, it is not necessary that - * the port-to-port mapping covers all the module ports. - * Any instance/module port which are not specified in the - * port-to-port mapping will be output by the module - * port name. - ***********************************************/ + * Note that, it is not necessary that the port-to-port mapping + * covers all the module ports. + * Any instance/module port which are not specified in the port-to-port + * mapping will be output by the module port name. + *******************************************************************/ void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& parent_module_id, const ModuleId& child_module_id, + const ModuleId& module_id, + const std::string& instance_name, const std::map& port2port_name_map, - const bool& explicit_port_map) { + const bool& use_explicit_port_map) { check_file_handler(fp); /* Check: all the key ports in the port2port_name_map does exist in the child module */ for (const auto& kv : port2port_name_map) { - ModulePortId module_port_id = module_manager.find_module_port(child_module_id, kv.first); + ModulePortId module_port_id = module_manager.find_module_port(module_id, kv.first); VTR_ASSERT(ModulePortId::INVALID() != module_port_id); } /* Print module name */ - fp << "\t" << module_manager.module_name(child_module_id) << " "; - /* Print instance name, _ */ - fp << module_manager.module_name(child_module_id) << "_" << module_manager.num_instance(parent_module_id, child_module_id) << "_" << " (" << std::endl; + fp << "\t" << module_manager.module_name(module_id) << " "; + /* Print instance name */ + fp << instance_name << " (" << std::endl; /* Print each port with/without explicit port map */ /* port type2type mapping */ @@ -337,7 +337,7 @@ void print_verilog_module_instance(std::fstream& fp, /* Port sequence: global, inout, input, output and clock ports, */ size_t port_cnt = 0; for (const auto& kv : port_type2type_map) { - for (const auto& port : module_manager.module_ports_by_type(child_module_id, kv.first)) { + for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { if (0 != port_cnt) { /* Do not dump a comma for the first port */ fp << "," << std::endl; @@ -345,16 +345,16 @@ void print_verilog_module_instance(std::fstream& fp, /* Print port */ fp << "\t\t"; /* if explicit port map is required, output the port name */ - if (true == explicit_port_map) { + if (true == use_explicit_port_map) { fp << "." << port.get_name() << "("; } /* Try to find the instanced port name in the name map */ if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) { /* Found it, we assign the port name */ /* TODO: make sure the port width matches! */ - ModulePortId module_port_id = module_manager.find_module_port(child_module_id, port.get_name()); + ModulePortId module_port_id = module_manager.find_module_port(module_id, port.get_name()); /* Get the port from module */ - BasicPort module_port = module_manager.module_port(child_module_id, module_port_id); + BasicPort module_port = module_manager.module_port(module_id, module_port_id); VTR_ASSERT(module_port.get_width() == port2port_name_map.at(port.get_name()).get_width()); fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name())); } else { @@ -362,7 +362,7 @@ void print_verilog_module_instance(std::fstream& fp, fp << generate_verilog_port(kv.second, port); } /* if explicit port map is required, output the pair of branket */ - if (true == explicit_port_map) { + if (true == use_explicit_port_map) { fp << ")"; } port_cnt++; @@ -373,6 +373,30 @@ void print_verilog_module_instance(std::fstream& fp, fp << ");" << std::endl; } + +/************************************************ + * Print an instance for a Verilog module + * This function is a wrapper for the generic version of + * print_verilog_module_instance() + * This function create an instance name based on the index + * of the child module in its parent module + ***********************************************/ +void print_verilog_module_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module_id, const ModuleId& child_module_id, + const std::map& port2port_name_map, + const bool& use_explicit_port_map) { + + /* Create instance name, _ */ + std::string instance_name = module_manager.module_name(child_module_id) + + "_" + + std::to_string(module_manager.num_instance(parent_module_id, child_module_id)) + + "_"; + + print_verilog_module_instance(fp, module_manager, child_module_id, instance_name, + port2port_name_map, use_explicit_port_map); +} + /************************************************ * Print an end line for a Verilog module ***********************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index b4f13ffcf..6040cb07f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -44,11 +44,18 @@ void print_verilog_module_ports(std::fstream& fp, void print_verilog_module_declaration(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& module_id); +void print_verilog_module_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const std::string& instance_name, + const std::map& port2port_name_map, + const bool& use_explicit_port_map); + void print_verilog_module_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& parent_module_id, const ModuleId& child_module_id, const std::map& port2port_name_map, - const bool& explicit_port_map); + const bool& use_explicit_port_map); void print_verilog_module_end(std::fstream& fp, const std::string& module_name); From 1faacfa3cf8856c01975bcfdd96597daf1fdf11d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Oct 2019 14:23:09 -0600 Subject: [PATCH 354/482] keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c index 72b250231..3e20e6bb0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c @@ -95,6 +95,7 @@ void write_include_netlists (char* src_dir_formatted, chomped_circuit_name, random_top_testbench_verilog_file_postfix); fprintf(fp, " `endif\n"); + /* TODO: bring these testbench onboard when it is ready fprintf(fp, "`elsif %s\n", initial_simulation_flag); fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, @@ -104,6 +105,7 @@ void write_include_netlists (char* src_dir_formatted, chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix); fprintf(fp, "`endif\n"); + */ fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, default_rr_dir_name, routing_verilog_file_name); From 4398cffaaa7576740dd72445f95ea254db89aef9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Oct 2019 22:32:36 -0600 Subject: [PATCH 355/482] single mode is working, multi-mode is under debugging --- openfpga_flow/VerilogNetlists/ff.v | 8 ++-- ...m_chain_FC_behavioral_verilog_template.xml | 10 ++--- .../base/fpga_x2p_benchmark_utils.cpp | 8 ++-- .../fpga_x2p/base/module_manager_utils.cpp | 43 +++++++++++++++--- .../bitstream/build_lut_bitstream.cpp | 8 +++- .../module_builder/build_grid_modules.cpp | 45 +++++++++++-------- .../module_builder/build_memory_modules.cpp | 2 +- .../module_builder/build_routing_modules.cpp | 20 +++++---- .../module_builder/build_top_module.cpp | 37 ++++++++++++--- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 4 +- .../verilog/verilog_include_netlists.c | 10 +++-- .../vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp | 3 +- .../SRC/fpga_x2p/verilog/verilog_memory.cpp | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 2 +- .../verilog/verilog_preconfig_top_module.cpp | 30 +++++-------- .../SRC/fpga_x2p/verilog/verilog_routing.c | 30 ++++++++++--- .../fpga_x2p/verilog/verilog_top_module.cpp | 2 +- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 3 +- 19 files changed, 177 insertions(+), 94 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v index cc6598c46..7e902c73a 100644 --- a/openfpga_flow/VerilogNetlists/ff.v +++ b/openfpga_flow/VerilogNetlists/ff.v @@ -76,9 +76,9 @@ endmodule //End Of Module static_dff //----------------------------------------------------- module sc_dff_compact ( /* Global ports go first */ -input reset, // Reset input +input pReset, // Reset input //input set, // set input -input clk, // Clock Input +input prog_clk, // Clock Input /* Local ports follow */ input D, // Data Input output Q, // Q output @@ -88,8 +88,8 @@ output Qb // Q output reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset /*or posedge set*/) -if (reset) begin +always @ ( posedge prog_clk or posedge pReset /*or posedge set*/) +if (pReset) begin q_reg <= 1'b0; //end else if (set) begin // q_reg <= 1'b1; diff --git a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml index 29f091673..29badf323 100644 --- a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml +++ b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml @@ -321,12 +321,12 @@ - + - - - - + + + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp index 6931da0da..df748c83a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp @@ -112,7 +112,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb, /* TOP side I/Os */ if (device_size.y() - 1 == y) { io_index = io_index_offset[io_side]; - for (size_t ix = 1; ix < x - 1; ++ix) { + for (size_t ix = 1; ix < x ; ++ix) { io_index += L_grids[ix][y].type->capacity; } io_index += z; @@ -120,7 +120,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb, /* RIGHT side I/Os */ if (device_size.x() - 1 == x) { io_index = io_index_offset[io_side]; - for (size_t iy = 1; iy < y - 1; ++iy) { + for (size_t iy = 1; iy < y; ++iy) { io_index += L_grids[x][iy].type->capacity; } io_index += z; @@ -128,7 +128,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb, /* BOTTOM side I/Os */ if (0 == y) { io_index = io_index_offset[io_side]; - for (size_t ix = 1; ix < x - 1; ++ix) { + for (size_t ix = 1; ix < x; ++ix) { io_index += L_grids[ix][y].type->capacity; } io_index += z; @@ -136,7 +136,7 @@ size_t find_benchmark_io_index(const t_logical_block& io_lb, /* LEFT side I/Os */ if (0 == x) { io_index = io_index_offset[io_side]; - for (size_t iy = 1; iy < y - 1; ++iy) { + for (size_t iy = 1; iy < y; ++iy) { io_index += L_grids[x][iy].type->capacity; } io_index += z; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 43dcd7707..7fe3bf2df 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -35,7 +35,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Add ports */ /* Find global ports and add one by one */ - for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) { + for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) { BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); } @@ -163,10 +163,41 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager, size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); /* Add ports to the module manager */ - for (const std::string& sram_port_name : sram_port_names) { - /* Add generated ports to the ModuleManager */ - BasicPort sram_port(sram_port_name, sram_port_size); - module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT); + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + case SPICE_SRAM_MEMORY_BANK: { + for (const std::string& sram_port_name : sram_port_names) { + /* Add generated ports to the ModuleManager */ + BasicPort sram_port(sram_port_name, sram_port_size); + module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT); + } + break; + } + case SPICE_SRAM_SCAN_CHAIN: { + /* Note that configuration chain tail is an output while head is an input + * IMPORTANT: this is co-designed with function generate_sram_port_names() + * If the return vector is changed, the following codes MUST be adapted! + */ + VTR_ASSERT(2 == sram_port_names.size()); + size_t port_counter = 0; + for (const std::string& sram_port_name : sram_port_names) { + /* Add generated ports to the ModuleManager */ + BasicPort sram_port(sram_port_name, sram_port_size); + if (0 == port_counter) { + module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT); + } else { + VTR_ASSERT(1 == port_counter); + module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_OUTPUT_PORT); + } + port_counter++; + } + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d]) Invalid type of SRAM organization !\n", + __FILE__, __LINE__); + exit(1); } } @@ -457,7 +488,7 @@ void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_m for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(parent_module); /* TODO: Give a name to make it clear */ - std::string net_name = module_manager.module_name(logic_module) + std::string("_") + logic_module_sram_ports[port_index].get_name(); + std::string net_name = module_manager.module_name(logic_module) + std::string("_") + std::to_string(logic_instance_id) + std::string("_") + logic_module_sram_ports[port_index].get_name(); module_manager.set_net_name(parent_module, net, net_name); /* Add net source */ module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp index 80ffe1cdf..ec700ca82 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp @@ -183,10 +183,10 @@ std::string generate_mask_bits(const size_t& mask_code, for (const size_t& mask_bit : mask_bits) { VTR_ASSERT( 0 == mask_bit || 1 == mask_bit ); if (0 == mask_bit) { - mask_bits_str.push_back('1'); + mask_bits_str.push_back('0'); continue; } - mask_bits_str.push_back('0'); + mask_bits_str.push_back('1'); } return mask_bits_str; @@ -496,6 +496,10 @@ std::vector build_frac_lut_bitstream(const CircuitLibrary& circuit_lib, /* Find the corresponding circuit model output port and assoicated lut_output_mask */ CircuitPortId lut_model_output_port = lut_pb->lut_output_pb_graph_pin[ilb]->port->circuit_model_port; size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port); + /* By default, lut_frac_level will be the lut_size, i.e., number of levels of the mux graph */ + if ( size_t(-1) == lut_frac_level ) { + lut_frac_level = lut_mux_graph.num_levels(); + } /* Find the corresponding circuit model output port and assoicated lut_output_mask */ size_t lut_output_mask = circuit_lib.port_lut_output_masks(lut_model_output_port)[lut_pb->lut_output_pb_graph_pin[ilb]->pin_number]; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index f348cf870..57eca34e7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -286,24 +286,6 @@ void build_primitive_block_module(ModuleManager& module_manager, /* Ensure that the module has been created and thus unique! */ VTR_ASSERT(ModuleId::INVALID() != primitive_module); - /* Find the global ports required by the primitive node, and add them to the module */ - std::vector primitive_model_global_ports = circuit_lib.model_global_ports(primitive_model, true); - for (auto port : primitive_model_global_ports) { - /* The global I/O of the FPGA has a special name */ - BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GLOBAL_PORT); - } - - /* Find the inout ports required by the primitive node, and add them to the module - * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric - */ - if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { - std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); - for (auto port : primitive_model_inout_ports) { - BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); - module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); - } - } /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here. * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P, * no ports of the circuit model will be missing here @@ -372,6 +354,33 @@ void build_primitive_block_module(ModuleManager& module_manager, add_module_nets_memory_config_bus(module_manager, primitive_module, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } + + /* Add global ports to the pb_module: + * This is a much easier job after adding sub modules (instances), + * we just need to find all the global ports from the child modules and build a list of it + */ + add_module_global_ports_from_child_modules(module_manager, primitive_module); + + /* Find the inout ports required by the primitive node, and add them to the module + * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric + */ + if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { + std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); + for (auto port : primitive_model_inout_ports) { + BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); + ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); + ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_lib_name(port)); + BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id); + VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width()); + + /* Wire the GPIO port form primitive_module to the logic module!*/ + for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) { + ModuleNetId net = module_manager.create_module_net(primitive_module); + module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_gpio_port_id, module_port.pins()[pin_id]); + module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_gpio_port_id, logic_gpio_port.pins()[pin_id]); + } + } + } } /******************************************************************** diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index 863c1bcc1..02dca4351 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -363,7 +363,7 @@ void build_memory_chain_module(ModuleManager& module_manager, */ BasicPort chain_tail_port(generate_configuration_chain_tail_name(), circuit_lib.port_size(sram_output_ports[0])); - module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_INPUT_PORT); + module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT); /* Add each output port: port width should match the number of memories */ for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index b1c687e77..94de58fea 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -282,14 +282,16 @@ void build_switch_block_mux_module(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); ModulePortId sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); + BasicPort sb_output_port = module_manager.module_port(sb_module, sb_output_port_id); /* Check port size should match */ - VTR_ASSERT(1 == mux_output_port.get_width()); + VTR_ASSERT(sb_output_port.get_width() == mux_output_port.get_width()); for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(sb_module); - /* Skip Configuring the net source, it is done before */ + /* Configuring the net source */ + module_manager.add_module_net_source(sb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]); /* Configure the net sink */ - module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, 0); + module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, sb_output_port.pins()[pin_id]); } /* Instanciate memory modules */ @@ -754,14 +756,16 @@ void build_connection_block_mux_module(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, cur_rr_node); + BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id); /* Check port size should match */ - VTR_ASSERT(1 == mux_output_port.get_width()); + VTR_ASSERT(cb_output_port.get_width() == mux_output_port.get_width()); for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(cb_module); - /* Skip Configuring the net source, it is done before */ + /* Configuring the net source */ + module_manager.add_module_net_source(cb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]); /* Configure the net sink */ - module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, 0); + module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, cb_output_port.pins()[pin_id]); } /* Instanciate memory modules */ @@ -932,7 +936,7 @@ void build_connection_block_module(ModuleManager& module_manager, /* Create a cache (fast look up) for module nets whose source are input ports */ std::map input_port_to_module_nets; - /* TODO: Generate short-wire connection for each routing track : + /* Generate short-wire connection for each routing track : * Each input port is short-wired to its output port and middle output port * * in[i] ----------> out[i] @@ -971,7 +975,7 @@ void build_connection_block_module(ModuleManager& module_manager, } } - /* TODO: Add sub modules of routing multiplexers or direct interconnect*/ + /* Add sub modules of routing multiplexers or direct interconnect*/ for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index 9acb7bc59..a8a5d66e9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -79,10 +79,18 @@ DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb, } VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); - DeviceCoordinator side_coord = rr_gsb.get_side_block_coordinator(sb_side); - gsb_coordinate.set_x(side_coord.get_x()); - gsb_coordinate.set_y(side_coord.get_y()); + /* RIGHT side: x + 1 */ + if (RIGHT == sb_side) { + gsb_coordinate.set_x(rr_gsb.get_x() + 1); + gsb_coordinate.set_y(rr_gsb.get_y()); + } + + /* BOTTOM side: y - 1 */ + if (BOTTOM == sb_side) { + gsb_coordinate.set_x(rr_gsb.get_x()); + gsb_coordinate.set_y(rr_gsb.get_y() - 1); + } return gsb_coordinate; } @@ -669,10 +677,25 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, DeviceCoordinator instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); DeviceCoordinator module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); - /* Skip those Connection blocks that do not exist */ - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { - continue; + /* Skip those Connection blocks that do not exist: + * 1. The CB does not exist in the device level! We should skip! + * 2. The CB does exist but we need to make sure if the GSB includes such CBs + * For TOP and LEFT side, check the existence using RRGSB method is_cb_exist() + * FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist() + */ + if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) { + if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) + || (true != rr_gsb.is_cb_exist(cb_type))) { + continue; + } + } + + if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) { + const RRGSB& adjancent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); + if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) + || (true != adjancent_gsb.is_cb_exist(cb_type))) { + continue; + } } /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index e06b825f6..844abd25d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -408,12 +408,12 @@ void vpr_fpga_verilog(ModuleManager& module_manager, + std::string(formal_verification_verilog_file_postfix); /* TODO: this is an old function, to be shadowed */ dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, - formal_verification_top_netlist_file_path.c_str(), src_dir_path); + std::string(formal_verification_top_netlist_file_path + std::string(".bak")).c_str(), src_dir_path); /* TODO: new function: to be tested */ print_verilog_preconfig_top_module(module_manager, bitstream_manager, fabric_bitstream, Arch.spice->circuit_lib, global_ports, L_logical_blocks, device_size, L_grids, L_blocks, - std::string(chomped_circuit_name), formal_verification_top_netlist_file_path + std::string(".bak"), + std::string(chomped_circuit_name), formal_verification_top_netlist_file_path, std::string(src_dir_path)); /* Output script for formality */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index a7a7f877d..3f5656b4a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -200,7 +200,7 @@ void print_verilog_grid(ModuleManager& module_manager, std::string(verilog_netlist_file_postfix)) ); /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; + //verilog_fname += ".bak"; /* Echo status */ if (IO_TYPE == phy_block_type) { @@ -313,7 +313,7 @@ void print_verilog_grids(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n"); std::string grid_verilog_fname(logic_block_verilog_file_name); /* TODO: remove .bak when it is ready */ - grid_verilog_fname += ".bak"; + //grid_verilog_fname += ".bak"; dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head, subckt_dir.c_str(), grid_verilog_fname.c_str()); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c index 3e20e6bb0..19f6bbc50 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c @@ -23,6 +23,7 @@ #include "linkedlist.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_globals.h" +#include "fpga_x2p_naming.h" /* Include verilog utils */ #include "verilog_global.h" @@ -82,10 +83,13 @@ void write_include_netlists (char* src_dir_formatted, verilog_include_defines_preproc_file(fp, src_dir_formatted); verilog_include_simulation_defines_file(fp, src_dir_formatted); - + /* fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, verilog_top_postfix); + */ + fprintf(fp, "`include \"%s%s\"\n", src_dir_formatted, + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix)).c_str()); fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, @@ -95,8 +99,8 @@ void write_include_netlists (char* src_dir_formatted, chomped_circuit_name, random_top_testbench_verilog_file_postfix); fprintf(fp, " `endif\n"); - /* TODO: bring these testbench onboard when it is ready fprintf(fp, "`elsif %s\n", initial_simulation_flag); + /* TODO: bring these testbench onboard when it is ready fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, top_testbench_verilog_file_postfix); @@ -104,8 +108,8 @@ void write_include_netlists (char* src_dir_formatted, fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix); - fprintf(fp, "`endif\n"); */ + fprintf(fp, "`endif\n"); fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, default_rr_dir_name, routing_verilog_file_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 7bd605d01..5a0232b5c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -34,7 +34,8 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, const std::string& submodule_dir, const bool& use_explicit_port_map) { /* TODO: remove .bak when this part is completed and tested */ - std::string verilog_fname = submodule_dir + luts_verilog_file_name + ".bak"; + std::string verilog_fname = submodule_dir + luts_verilog_file_name; + //verilog_fname +=".bak"; std::fstream fp; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index c898aac26..ee0b63e9f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -104,7 +104,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, const bool& use_explicit_port_map) { /* Plug in with the mux subckt */ std::string verilog_fname(submodule_dir + memories_verilog_file_name); - verilog_fname += ".bak"; + //verilog_fname += ".bak"; /* Create the file stream */ std::fstream fp; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 413d57e5a..7fd71767d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -1217,7 +1217,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, /* TODO: Generate modules into a .bak file now. Rename after it is verified */ std::string verilog_fname(submodule_dir + muxes_verilog_file_name); - verilog_fname += ".bak"; + //verilog_fname += ".bak"; /* Create the file stream */ std::fstream fp; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index ced31628d..d3bf11bb2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -80,25 +80,10 @@ void print_verilog_preconfig_top_module_internal_wires(std::fstream& fp, check_file_handler(fp); /* Global ports of top-level module */ - print_verilog_comment(fp, std::string("----- Global ports of FPGA fabric -----")); - for (const BasicPort& global_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, global_port) << ";" << std::endl; - } - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Datapath I/Os of FPGA fabric */ - print_verilog_comment(fp, std::string("----- I/Os of FPGA fabric -----")); - for (const BasicPort& gpio_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, gpio_port) << ";" << std::endl; - } - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Datapath I/Os of FPGA fabric */ - print_verilog_comment(fp, std::string("----- Configuration protocols of FPGA fabric -----")); - for (const BasicPort& input_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_INPUT_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, input_port) << ";" << std::endl; + print_verilog_comment(fp, std::string("----- Local wires for FPGA fabric -----")); + for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { + BasicPort module_port = module_manager.module_port(top_module, module_port_id); + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; } /* Add an empty line as a splitter */ fp << std::endl; @@ -244,7 +229,12 @@ void print_verilog_preconfig_top_module_connect_ios(std::fstream& fp, BasicPort benchmark_io_port(std::string(std::string(io_lb.name)+ std::string(formal_verification_top_module_port_postfix)), 1); print_verilog_comment(fp, std::string("----- Blif Benchmark inout " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); - print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); + if (VPACK_INPAD == io_lb.type) { + print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); + } else { + VTR_ASSERT(VPACK_OUTPAD == io_lb.type); + print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); + } /* Mark this I/O has been used/wired */ io_used[io_index] = true; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index d7943f805..2c995e864 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2101,7 +2101,9 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or fclose(fp); /* Add fname to the linked list */ + /* routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + */ /* Free chan_rr_nodes */ my_free(fname); @@ -2302,7 +2304,9 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info fclose(fp); /* Add fname to the linked list */ + /* routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + */ /* Free chan_rr_nodes */ my_free(fname); @@ -3368,7 +3372,9 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra fclose(fp); /* Add fname to the linked list */ + /* routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + */ /* Free */ my_free(fname); @@ -3606,7 +3612,9 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ fclose(fp); /* Add fname to the linked list */ + /* routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + */ /* Free */ my_free(fname); @@ -3826,10 +3834,12 @@ void print_verilog_routing_resources(ModuleManager& module_manager, } /* Output a header file for all the routing blocks */ + /* vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head, subckt_dir, routing_verilog_file_name); + */ return; } @@ -3900,7 +3910,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix))); /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; + //verilog_fname += ".bak"; /* Create the file stream */ std::fstream fp; @@ -3927,9 +3937,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma fp.close(); /* Add fname to the linked list */ - /* - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); - */ + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); } /********************************************************************* @@ -4005,7 +4013,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; + //verilog_fname += ".bak"; /* Create the file stream */ std::fstream fp; @@ -4029,9 +4037,7 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage fp.close(); /* Add fname to the linked list */ - /* routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ return; } @@ -4108,6 +4114,10 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager, print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); + dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head, + subckt_dir.c_str(), + routing_verilog_file_name); } @@ -4161,4 +4171,10 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager, unique_mirror, CHANY, use_explicit_port_map); } + + vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); + dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head, + subckt_dir.c_str(), + routing_verilog_file_name); + } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp index e2c183387..2cfeecf1b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp @@ -42,7 +42,7 @@ void print_verilog_top_module(ModuleManager& module_manager, /* Create the file name for Verilog netlist */ std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix))); /* TODO: remove the bak file when the file is ready */ - verilog_fname += ".bak"; + //verilog_fname += ".bak"; vpr_printf(TIO_MESSAGE_INFO, "Writing Verilog Netlist for top-level module of FPGA fabric (%s)...\n", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 66174ebb8..b6c8bdd0a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -173,7 +173,7 @@ void print_verilog_module_ports(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT; - port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT; port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT; @@ -329,6 +329,7 @@ void print_verilog_module_instance(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; From 55fbd72293d8a52b0d33aa428145d00e7bddd4c4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 15:50:42 -0600 Subject: [PATCH 356/482] many bugs have been fixed --- .../tasks/blif_vpr_flow/config/task.conf | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 6 ++- .../verilog/verilog_preconfig_top_module.cpp | 41 ++++++++++++------- .../verilog/verilog_preconfig_top_module.h | 1 - .../fpga_x2p/verilog/verilog_writer_utils.cpp | 18 ++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 4 ++ 7 files changed, 55 insertions(+), 18 deletions(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index 7cadfce2c..16fab45de 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -60,6 +60,7 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_verilog_explicit_mapping= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 844abd25d..bb5af9ac5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -410,7 +410,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager, dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, std::string(formal_verification_top_netlist_file_path + std::string(".bak")).c_str(), src_dir_path); /* TODO: new function: to be tested */ - print_verilog_preconfig_top_module(module_manager, bitstream_manager, fabric_bitstream, + print_verilog_preconfig_top_module(module_manager, bitstream_manager, Arch.spice->circuit_lib, global_ports, L_logical_blocks, device_size, L_grids, L_blocks, std::string(chomped_circuit_name), formal_verification_top_netlist_file_path, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 3f5656b4a..401484e30 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -141,12 +141,14 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, } } - /* For leaf node, a primitive Verilog module will be generated */ + /* For leaf node, a primitive Verilog module will be generated. + * Note that the primitive may be mapped to a standard cell, we force to use that + */ if (TRUE == is_primitive_pb_type(physical_pb_type)) { print_verilog_primitive_block(fp, module_manager, physical_pb_graph_node, io_side, - use_explicit_mapping); + true); /* Finish for primitive node, return */ return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index d3bf11bb2..731a3630e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -271,14 +271,17 @@ static void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream) { + const BitstreamManager& bitstream_manager) { print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); + fp << "initial begin" << std::endl; - for (const ConfigBitId& config_bit_id : fabric_bitstream) { - ConfigBlockId bit_parent_block = bitstream_manager.bit_parent_block(config_bit_id); + for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { + /* We only cares blocks with configuration bits */ + if (0 == bitstream_manager.block_bits(config_block_id).size()) { + continue; + } /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bit_parent_block); + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); /* Drop the first block, which is the top module, it should be replaced by the instance name here */ /* Ensure that this is the module we want to drop! */ VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); @@ -290,18 +293,29 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, bit_hierarchy_path += bitstream_manager.block_name(temp_block); } bit_hierarchy_path += std::string("."); - bit_hierarchy_path += generate_configuration_chain_data_out_name(); /* Find the bit index in the parent block */ - BasicPort config_port(bit_hierarchy_path, - bitstream_manager.bit_index_in_parent_block(config_bit_id), - bitstream_manager.bit_index_in_parent_block(config_bit_id)); + BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(), + bitstream_manager.block_bits(config_block_id).size()); - /* Wire it to the configuration bit */ - std::vector default_values(config_port.get_width(), bitstream_manager.bit_value(config_bit_id)); - print_verilog_wire_constant_values(fp, config_port, default_values); + BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(), + bitstream_manager.block_bits(config_block_id).size()); + + /* Wire it to the configuration bit: access both data out and data outb ports */ + std::vector config_data_values; + for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { + config_data_values.push_back(bitstream_manager.bit_value(config_bit)); + } + print_verilog_deposit_wire_constant_values(fp, config_data_port, config_data_values); + + std::vector config_datab_values; + for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { + config_datab_values.push_back(!bitstream_manager.bit_value(config_bit)); + } + print_verilog_deposit_wire_constant_values(fp, config_datab_port, config_datab_values); } + fp << "end" << std::endl; print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); } @@ -340,7 +354,6 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, *******************************************************************/ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const std::vector& L_logical_blocks, @@ -401,7 +414,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, /* Assign FPGA internal SRAM/Memory ports to bitstream values */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, - bitstream_manager, fabric_bitstream); + bitstream_manager); /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(formal_verification_top_module_postfix)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h index 441de0836..aae0a5c67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h @@ -10,7 +10,6 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const std::vector& L_logical_blocks, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index b6c8bdd0a..e119fa2ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -665,6 +665,24 @@ void print_verilog_wire_constant_values(std::fstream& fp, fp << ";" << std::endl; } +/******************************************************************** + * Deposit constant values to a Verilog port + *******************************************************************/ +void print_verilog_deposit_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + fp << "\t"; + fp << "$deposit("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << ", "; + fp << generate_verilog_constant_values(const_values); + fp << ");" << std::endl; +} + + /******************************************************************** * Generate a wire connection for two Verilog ports * using "assign" syntax diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 6040cb07f..62724f36b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -88,6 +88,10 @@ void print_verilog_wire_constant_values(std::fstream& fp, const BasicPort& output_port, const std::vector& const_values); +void print_verilog_deposit_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values); + void print_verilog_wire_connection(std::fstream& fp, const BasicPort& output_port, const BasicPort& input_port, From 7460dc8cabc610c9397f436e5a8c30f3fefaafa1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 19:10:36 -0600 Subject: [PATCH 357/482] pass current regression tests --- .../bitstream/build_mux_bitstream.cpp | 14 +- .../module_builder/build_mux_modules.cpp | 19 +++ .../SRC/fpga_x2p/verilog/verilog_decoders.cpp | 4 +- .../verilog/verilog_preconfig_top_module.cpp | 127 +++++++++++++++++- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 15 +++ .../fpga_x2p/verilog/verilog_writer_utils.h | 4 + 6 files changed, 173 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp index f48de7afb..9edd25b0b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp @@ -99,10 +99,18 @@ std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, */ for (const size_t& level : mux_graph.levels()) { /* The encoder will convert the path_id to a binary number - * For example: when path_id=3 (use the 4th input), using a 4-input encoder - * the sram_bits will be the 4-digit binary number of 3: 0100 + * For example: when path_id=3 (use the 4th input), using a 2-input encoder + * the sram_bits will be the 2-digit binary number of 3: 10 */ std::vector encoder_data; + + /* Exception: there is only 1 memory at this level, bitstream will not be changed!!! */ + if (1 == mux_graph.memories_at_level(level).size()) { + mux_bitstream.push_back(raw_bitstream[mux_graph.memories_at_level(level)[0]]); + continue; + } + + /* Otherwise: we follow a regular recipe */ for (size_t mem_index = 0; mem_index < mux_graph.memories_at_level(level).size(); ++mem_index) { /* Conversion rule: true = 1, false = 0 */ if (true == raw_bitstream[mux_graph.memories_at_level(level)[mem_index]]) { @@ -121,7 +129,7 @@ std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, } /* Build final mux bitstream */ for (const size_t& bit : encoder_addr) { - mux_bitstream.push_back((bool)bit); + mux_bitstream.push_back(1 == bit); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 2386000c5..529f1e760 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -1004,6 +1004,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0])); + ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0]) + "_inv"); BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); BasicPort lvl_data_port(decoder_data_port.get_name(), 0); BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); @@ -1020,6 +1021,24 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag lvl_data_port.rotate(data_size); lvl_data_inv_port.rotate(data_size); + /* Exception: if the data size is one, we just need wires! */ + if (1 == data_size) { + for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) { + MuxMemId mem_id = MuxMemId(mem_net_cnt); + /* Set the module net source */ + module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]); + /* Update counter */ + mem_net_cnt++; + + MuxMemId mem_inv_id = MuxMemId(mem_inv_net_cnt); + /* Set the module net source */ + module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_inv_id], mux_module, 0, mux_module_sram_inv_port_id, lvl_addr_port.pins()[pin_id]); + /* Update counter */ + mem_inv_net_cnt++; + } + continue; + } + std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); ModuleId decoder_module = module_manager.find_module(decoder_module_name); VTR_ASSERT(ModuleId::INVALID() != decoder_module); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index 7021e3b43..569b9127f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -82,8 +82,8 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, * data_inv = ~data_inv */ if (1 == data_size) { - print_verilog_wire_connection(fp, addr_port, data_port, false); - print_verilog_wire_connection(fp, data_inv_port, data_port, true); + print_verilog_wire_connection(fp, data_port, addr_port, false); + print_verilog_wire_connection(fp, data_inv_port, addr_port, true); print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index 731a3630e..14ca60752 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -266,13 +266,101 @@ void print_verilog_preconfig_top_module_connect_ios(std::fstream& fp, /******************************************************************** * Impose the bitstream on the configuration memories + * This function uses 'assign' syntax to impost the bitstream at mem port + * while uses 'force' syntax to impost the bitstream at mem_inv port *******************************************************************/ static -void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager) { - print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); +void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const BitstreamManager& bitstream_manager) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----")); + + for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { + /* We only cares blocks with configuration bits */ + if (0 == bitstream_manager.block_bits(config_block_id).size()) { + continue; + } + /* Build the hierarchical path of the configuration bit in modules */ + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); + /* Drop the first block, which is the top module, it should be replaced by the instance name here */ + /* Ensure that this is the module we want to drop! */ + VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); + block_hierarchy.erase(block_hierarchy.begin()); + /* Build the full hierarchy path */ + std::string bit_hierarchy_path(formal_verification_top_module_uut_name); + for (const ConfigBlockId& temp_block : block_hierarchy) { + bit_hierarchy_path += std::string("."); + bit_hierarchy_path += bitstream_manager.block_name(temp_block); + } + bit_hierarchy_path += std::string("."); + + /* Find the bit index in the parent block */ + BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(), + bitstream_manager.block_bits(config_block_id).size()); + + /* Wire it to the configuration bit: access both data out and data outb ports */ + std::vector config_data_values; + for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { + config_data_values.push_back(bitstream_manager.bit_value(config_bit)); + } + print_verilog_wire_constant_values(fp, config_data_port, config_data_values); + } + + fp << "initial begin" << std::endl; + + for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { + /* We only cares blocks with configuration bits */ + if (0 == bitstream_manager.block_bits(config_block_id).size()) { + continue; + } + /* Build the hierarchical path of the configuration bit in modules */ + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); + /* Drop the first block, which is the top module, it should be replaced by the instance name here */ + /* Ensure that this is the module we want to drop! */ + VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); + block_hierarchy.erase(block_hierarchy.begin()); + /* Build the full hierarchy path */ + std::string bit_hierarchy_path(formal_verification_top_module_uut_name); + for (const ConfigBlockId& temp_block : block_hierarchy) { + bit_hierarchy_path += std::string("."); + bit_hierarchy_path += bitstream_manager.block_name(temp_block); + } + bit_hierarchy_path += std::string("."); + + /* Find the bit index in the parent block */ + BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(), + bitstream_manager.block_bits(config_block_id).size()); + + std::vector config_datab_values; + for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { + config_datab_values.push_back(!bitstream_manager.bit_value(config_bit)); + } + print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values); + } + + fp << "end" << std::endl; + + print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----")); +} + +/******************************************************************** + * Impose the bitstream on the configuration memories + * This function uses '$deposit' syntax to do so + *******************************************************************/ +static +void print_verilog_preconfig_top_module_deposit_bitstream(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const BitstreamManager& bitstream_manager) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Begin deposit bitstream to configuration memories -----")); + fp << "initial begin" << std::endl; for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { @@ -316,6 +404,35 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, } fp << "end" << std::endl; + + print_verilog_comment(fp, std::string("----- End deposit bitstream to configuration memories -----")); +} + +/******************************************************************** + * Impose the bitstream on the configuration memories + * We branch here for different simulators: + * 1. iVerilog Icarus prefers using 'assign' syntax to force the values + * 2. Mentor Modelsim prefers using '$deposit' syntax to do so + *******************************************************************/ +static +void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const BitstreamManager& bitstream_manager) { + print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); + + print_verilog_preprocessing_flag(fp, std::string(icarus_simulator_flag)); + + /* Use assign syntax for Icarus simulator */ + print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, bitstream_manager); + + fp << "`else" << std::endl; + + /* Use assign syntax for Icarus simulator */ + print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, bitstream_manager); + + print_verilog_endif(fp); + print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index e119fa2ad..b79af9f7b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -682,6 +682,21 @@ void print_verilog_deposit_wire_constant_values(std::fstream& fp, fp << ");" << std::endl; } +/******************************************************************** + * Generate a wire connection, that assigns constant values to a + * Verilog port + *******************************************************************/ +void print_verilog_force_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + fp << "\t"; + fp << "force "; + fp << generate_verilog_port_constant_values(output_port, const_values); + fp << ";" << std::endl; +} /******************************************************************** * Generate a wire connection for two Verilog ports diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 62724f36b..f64ea6ed7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -92,6 +92,10 @@ void print_verilog_deposit_wire_constant_values(std::fstream& fp, const BasicPort& output_port, const std::vector& const_values); +void print_verilog_force_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values); + void print_verilog_wire_connection(std::fstream& fp, const BasicPort& output_port, const BasicPort& input_port, From 5531422186567e19c673d08bd153d9a1f4cc95e3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 19:37:06 -0600 Subject: [PATCH 358/482] update regression test with no-explicit port mapping cases --- openfpga_flow/tasks/blif_vpr_flow/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index 16fab45de..152fcd6be 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -60,7 +60,7 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= +#vpr_fpga_verilog_explicit_mapping= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= From 858c1aefce748cfde7ecab181123acc1e2c22a82 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 19:50:34 -0600 Subject: [PATCH 359/482] try use force for Icarus --- .../vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index 14ca60752..810e37dbd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -278,6 +278,7 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp, check_file_handler(fp); print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----")); + fp << "initial begin" << std::endl; for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { /* We only cares blocks with configuration bits */ @@ -307,8 +308,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp, for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { config_data_values.push_back(bitstream_manager.bit_value(config_bit)); } - print_verilog_wire_constant_values(fp, config_data_port, config_data_values); + print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values); } + fp << "end" << std::endl; fp << "initial begin" << std::endl; From 7eac8be475cdd290927cb32504a04a633b419718 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 20:04:20 -0600 Subject: [PATCH 360/482] try to upgrade travis OS linux for the latest iverilog --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index b7256b307..9f391b2c2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -22,6 +22,7 @@ matrix: - os: linux # Compiler is specified in ./travis/common.sh sudo: false + dist: bionic compiler: g++-8 addons: apt: From de787187249a3f7ffa67442823b80098e9b44957 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 20:07:32 -0600 Subject: [PATCH 361/482] remove unused gcc setting in travis --- .travis.yml | 2 -- 1 file changed, 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 9f391b2c2..e433d4894 100644 --- a/.travis.yml +++ b/.travis.yml @@ -43,8 +43,6 @@ matrix: - fontconfig - g++-8 - gcc-8 - - g++-4.9 - - gcc-4.9 - gdb - git - gperf From 81180939ca5d3fbdbbf379e8983a4aa997b3591f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Thu, 31 Oct 2019 09:56:57 -0600 Subject: [PATCH 362/482] Bug fix: Missing exit_if_fail flag in fpga_flow script --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 2abaee97d..110a0f506 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -836,7 +836,7 @@ def run_rewrite_verilog(): run_command("Yosys", "yosys_output.txt", command) -def run_netlists_verification(): +def run_netlists_verification(exit_if_fail=True): ExecTime["VerificationStart"] = time.time() compiled_file = "compiled_"+args.top_module # include_netlists = args.top_module+"_include_netlists.v" From a6a3e7c36bf2add0fe23db799f8fdb8939ab9a52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 31 Oct 2019 19:31:27 -0600 Subject: [PATCH 363/482] adding mcnc_big20 to regression test --- .../benchmarks/mcnc_big20/alu4/alu4.act | 453 + .../benchmarks/mcnc_big20/alu4/alu4.blif | 1360 ++ .../benchmarks/mcnc_big20/alu4/alu4.v | 896 ++ .../benchmarks/mcnc_big20/apex2/apex2.act | 655 + .../benchmarks/mcnc_big20/apex2/apex2.blif | 1667 +++ .../benchmarks/mcnc_big20/apex2/apex2.v | 1275 ++ .../benchmarks/mcnc_big20/apex4/apex4.act | 575 + .../benchmarks/mcnc_big20/apex4/apex4.blif | 1595 +++ .../benchmarks/mcnc_big20/apex4/apex4.v | 1145 ++ .../benchmarks/mcnc_big20/bigkey/bigkey.act | 1160 ++ .../benchmarks/mcnc_big20/bigkey/bigkey.blif | 2803 ++++ .../benchmarks/mcnc_big20/bigkey/bigkey.v | 2697 ++++ .../benchmarks/mcnc_big20/clma/clma.act | 2928 +++++ .../benchmarks/mcnc_big20/clma/clma.blif | 8638 ++++++++++++ .../benchmarks/mcnc_big20/clma/clma.v | 5543 ++++++++ .../benchmarks/mcnc_big20/des/des.act | 1061 ++ .../benchmarks/mcnc_big20/des/des.blif | 3276 +++++ openfpga_flow/benchmarks/mcnc_big20/des/des.v | 1870 +++ .../benchmarks/mcnc_big20/diffeq/diffeq.act | 870 ++ .../benchmarks/mcnc_big20/diffeq/diffeq.blif | 2376 ++++ .../benchmarks/mcnc_big20/diffeq/diffeq.v | 2329 ++++ .../benchmarks/mcnc_big20/dsip/dsip.act | 1115 ++ .../benchmarks/mcnc_big20/dsip/dsip.blif | 2780 ++++ .../benchmarks/mcnc_big20/dsip/dsip.v | 2641 ++++ .../mcnc_big20/elliptic/elliptic.act | 3040 +++++ .../mcnc_big20/elliptic/elliptic.blif | 7378 +++++++++++ .../benchmarks/mcnc_big20/elliptic/elliptic.v | 8198 ++++++++++++ .../benchmarks/mcnc_big20/ex1010/ex1010.act | 591 + .../benchmarks/mcnc_big20/ex1010/ex1010.blif | 1775 +++ .../benchmarks/mcnc_big20/ex1010/ex1010.v | 1176 ++ .../benchmarks/mcnc_big20/ex5p/ex5p.act | 283 + .../benchmarks/mcnc_big20/ex5p/ex5p.blif | 732 ++ .../benchmarks/mcnc_big20/ex5p/ex5p.v | 562 + .../benchmarks/mcnc_big20/frisc/frisc.act | 2622 ++++ .../benchmarks/mcnc_big20/frisc/frisc.blif | 7023 ++++++++++ .../benchmarks/mcnc_big20/frisc/frisc.v | 7100 ++++++++++ .../benchmarks/mcnc_big20/misex3/misex3.act | 361 + .../benchmarks/mcnc_big20/misex3/misex3.blif | 1064 ++ .../benchmarks/mcnc_big20/misex3/misex3.v | 712 + .../benchmarks/mcnc_big20/pdc/pdc.act | 1422 ++ .../benchmarks/mcnc_big20/pdc/pdc.blif | 4513 +++++++ openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v | 2832 ++++ .../benchmarks/mcnc_big20/s298/s298.act | 36 + .../benchmarks/mcnc_big20/s298/s298.blif | 90 + .../benchmarks/mcnc_big20/s298/s298.v | 106 + .../benchmarks/mcnc_big20/s38417/s38417.act | 4010 ++++++ .../benchmarks/mcnc_big20/s38417/s38417.blif | 10494 +++++++++++++++ .../benchmarks/mcnc_big20/s38417/s38417.v | 10966 ++++++++++++++++ .../benchmarks/mcnc_big20/s38584/s38584.act | 3643 +++++ .../benchmarks/mcnc_big20/s38584/s38584.blif | 9097 +++++++++++++ .../benchmarks/mcnc_big20/s38584/s38584.v | 9933 ++++++++++++++ .../benchmarks/mcnc_big20/seq/seq.act | 644 + .../benchmarks/mcnc_big20/seq/seq.blif | 1752 +++ openfpga_flow/benchmarks/mcnc_big20/seq/seq.v | 1251 ++ .../benchmarks/mcnc_big20/spla/spla.act | 1340 ++ .../benchmarks/mcnc_big20/spla/spla.blif | 4195 ++++++ .../benchmarks/mcnc_big20/spla/spla.v | 2668 ++++ .../benchmarks/mcnc_big20/tseng/tseng.act | 1077 ++ .../benchmarks/mcnc_big20/tseng/tseng.blif | 2605 ++++ .../benchmarks/mcnc_big20/tseng/tseng.v | 2871 ++++ .../tasks/mcnc_big20/config/task.conf | 156 + .../verilog/verilog_preconfig_top_module.cpp | 4 +- 62 files changed, 170027 insertions(+), 3 deletions(-) create mode 100644 openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act create mode 100644 openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif create mode 100644 openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v create mode 100644 openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act create mode 100644 openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif create mode 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0.003630 +n461 0.983800 0.120489 +n462 0.998000 0.191415 +n463 0.968000 0.000008 diff --git a/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif b/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif new file mode 100644 index 000000000..a6f929896 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif @@ -0,0 +1,1360 @@ +# Benchmark "alu4" written by ABC on Tue Mar 12 09:24:16 2019 +.model alu4 +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ + i_13_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ +.names n26 n29 n28 i_3_ n31 n30 o_0_ +0000-- 0 +000-00 0 +.names i_2_ n27 n26 +10 1 +.names i_7_ i_10_ i_9_ n27 +00- 1 +1-0 1 +.names i_1_ i_6_ i_10_ i_9_ n28 +101- 1 +11-1 1 +.names i_0_ i_5_ i_10_ i_9_ n29 +101- 1 +11-1 1 +.names i_10_ i_8_ n30 +10 1 +.names i_9_ i_8_ n31 +11 1 +.names n33 i_3_ n35 n34 n31 n30 o_1_ +0000-- 1 +01--1- 1 +01---1 1 +101--- 1 +10-1-- 1 +11--00 1 +.names i_4_ i_13_ n33 +10 1 +.names i_12_ i_8_ n34 +11 1 +.names i_11_ i_8_ n35 +10 1 +.names i_5_ i_6_ n36 +00 1 +.names i_0_ i_6_ i_1_ i_5_ n37 +10-- 0 +--10 0 +.names i_12_ n39 i_2_ i_3_ n37 i_7_ n38 +010--- 1 +01--1- 1 +0-0--1 1 +0--0-- 1 +.names n40 n36 n39 +00 1 +.names i_7_ i_1_ i_0_ i_6_ i_5_ n40 +011-- 1 +01--0 1 +0-10- 1 +.names n42 n27 n35 n34 i_3_ n41 +0---- 0 +-1000 0 +.names i_0_ i_1_ i_2_ n42 +111 1 +.names i_2_ i_5_ i_6_ i_0_ i_1_ n43 +111-- 0 +11--1 0 +1-11- 0 +.names i_7_ i_1_ i_6_ i_0_ i_5_ n44 +0---- 1 +-00-- 1 +---00 1 +.names i_0_ i_2_ i_1_ i_5_ i_7_ i_6_ n45 +000--- 1 +0--1-- 1 +-0--1- 1 +--0--1 1 +---111 1 +.names i_7_ i_3_ i_1_ i_5_ i_0_ i_6_ n46 +1111-- 1 +111-1- 1 +11-1-1 1 +11--11 1 +.names i_2_ i_3_ i_5_ i_6_ i_0_ i_1_ n47 +1111-- 0 +111--1 0 +11-11- 0 +.names i_2_ i_3_ n48 +00 1 +.names i_0_ i_1_ i_2_ n49 +000 1 +.names i_8_ i_3_ n50 +10 1 +.names i_3_ i_1_ i_6_ i_0_ i_5_ n51 +1---- 0 +-11-- 0 +---11 0 +.names i_3_ i_6_ i_1_ i_0_ i_5_ n52 +1---- 0 +-01-- 0 +---10 0 +.names i_4_ i_3_ n53 +10 1 +.names i_7_ i_6_ i_9_ n54 +110 1 +.names i_5_ n56 n55 +10 1 +.names i_1_ i_6_ n56 +10 1 +.names i_11_ i_7_ i_9_ n57 +000 1 +.names n59 n60 n61 n58 +00- 1 +0-1 1 +.names i_4_ i_1_ i_7_ i_8_ i_10_ n59 +10000 1 +.names i_4_ i_2_ i_10_ n60 +100 1 +.names i_6_ i_3_ i_8_ i_1_ n61 +11-- 1 +1--1 1 +-11- 1 +.names i_4_ i_7_ i_6_ i_8_ i_10_ n62 +10000 1 +.names n64 n66 n65 n67 n63 +001- 1 +00-0 1 +.names i_9_ i_10_ i_3_ n35 n34 n64 +00000 1 +.names i_7_ i_10_ i_12_ i_11_ n65 +00-0 0 +100- 0 +.names i_6_ i_10_ i_5_ i_1_ i_12_ i_11_ n66 +0000-0 1 +10000- 1 +.names i_5_ i_2_ i_6_ i_1_ n67 +000- 1 +00-0 1 +.names i_9_ i_2_ n65 n55 i_7_ i_12_ n68 +000--- 1 +00-110 1 +.names i_4_ n49 i_3_ i_9_ i_10_ n69 +110-- 0 +1--00 0 +.names i_4_ i_8_ i_9_ n70 +110 1 +.names i_7_ i_6_ i_2_ i_1_ n71 +11-- 1 +1--0 1 +-10- 1 +.names i_5_ n73 n53 n74 i_6_ i_1_ n72 +011-0- 1 +011--0 1 +0--1-- 1 +.names i_7_ i_10_ n73 +00 1 +.names i_4_ i_1_ i_2_ i_8_ i_10_ n74 +10000 1 +.names n346 n76 n75 +10 1 +.names i_0_ n77 n78 n76 +01- 1 +0-0 1 +.names i_4_ i_8_ i_6_ i_2_ i_10_ i_9_ n77 +10000- 1 +1110-0 1 +.names i_4_ i_7_ i_6_ i_3_ i_10_ i_9_ n78 +10000- 0 +1110-0 0 +.names i_4_ i_6_ i_0_ i_2_ i_9_ i_3_ n79 +110000 1 +.names i_0_ i_6_ i_1_ n81 i_12_ i_11_ n80 +000--0 1 +010-0- 1 +0--0-- 1 +.names n62 n82 n70 n83 i_2_ n81 +1---- 0 +-11-- 0 +---00 0 +.names i_7_ i_6_ n82 +11 1 +.names i_7_ i_6_ i_10_ i_9_ i_12_ i_11_ n83 +0----1 1 +1---1- 1 +-01--- 1 +-1-1-- 1 +.names i_4_ i_10_ n85 n49 i_8_ n84 +101-- 1 +10-10 1 +.names i_0_ i_3_ i_2_ i_6_ i_1_ i_7_ n85 +0000-- 1 +00--00 1 +.names i_3_ i_1_ i_0_ n87 n88 i_4_ n86 +00010- 0 +110-1- 0 +1-0111 0 +-00101 0 +.names i_12_ i_11_ i_13_ i_10_ n87 +1000 1 +.names i_11_ i_10_ i_12_ n88 +110 1 +.names n93 i_12_ n90 n91 n92 n89 +100-- 1 +10-1- 1 +10--1 1 +.names i_9_ i_11_ i_7_ i_3_ i_8_ n90 +101-- 0 +10-11 0 +.names i_3_ i_5_ i_4_ n91 +110 1 +.names i_10_ i_11_ i_7_ n92 +100 1 +.names i_2_ i_1_ i_0_ n93 +110 1 +.names i_11_ i_10_ n94 +11 1 +.names n96 n97 i_6_ i_5_ n98 i_4_ n95 +11---- 1 +1-1000 1 +.names i_12_ i_11_ n96 +10 1 +.names i_10_ i_7_ i_6_ i_3_ i_5_ i_8_ n97 +111100 1 +.names i_3_ i_2_ i_0_ i_8_ i_10_ i_7_ n98 +110--- 0 +---111 0 +.names i_0_ i_1_ i_2_ n99 +100 1 +.names n104 n102 n103 i_3_ n101 n31 n100 +101--- 1 +1--111 1 +.names i_7_ i_6_ n101 +00 1 +.names i_3_ i_2_ i_0_ i_9_ i_8_ i_7_ n102 +110--- 0 +---100 0 +.names i_4_ i_6_ n103 +00 1 +.names i_11_ i_5_ i_12_ n104 +110 1 +.names i_3_ i_4_ n105 +10 1 +.names i_11_ i_13_ i_9_ i_4_ i_12_ i_3_ n106 +1001-- 0 +100-00 0 +.names i_1_ i_2_ i_11_ i_0_ n107 +1100 1 +.names i_11_ i_12_ i_13_ n108 +100 1 +.names i_8_ i_10_ i_7_ i_3_ i_6_ i_1_ n109 +10000- 1 +1000-0 1 +.names i_11_ i_13_ i_10_ n110 +000 1 +.names i_12_ i_13_ i_9_ n111 +000 1 +.names i_12_ n113 n112 +11 1 +.names i_11_ i_13_ n113 +10 1 +.names i_0_ i_5_ n115 n116 i_2_ n117 n114 +101--- 0 +10-1-- 0 +1---10 0 +.names i_11_ i_12_ i_3_ i_10_ i_8_ n115 +11110 1 +.names i_11_ i_10_ i_2_ i_7_ i_6_ i_12_ n116 +11100- 1 +1110-1 1 +.names i_9_ i_10_ i_6_ i_12_ i_11_ n117 +110-1 0 +1111- 0 +.names n57 i_2_ n119 n124 n55 n118 +0-1-- 0 +10-11 0 +-11-- 0 +.names n123 n96 n121 n122 n104 n120 n119 +111--- 1 +11-0-- 1 +1---10 1 +.names i_8_ i_7_ i_6_ i_3_ i_2_ i_1_ n120 +00---1 0 +0-0-1- 0 +-001-- 0 +.names i_8_ i_2_ i_6_ i_5_ n121 +1110 1 +.names i_7_ i_5_ i_6_ i_3_ i_1_ i_8_ n122 +1011-- 0 +10--11 0 +.names i_4_ i_0_ n123 +00 1 +.names i_12_ i_13_ n124 +10 1 +.names n49 n126 n127 n125 +11- 1 +1-1 1 +.names i_12_ i_4_ i_5_ i_13_ i_3_ n126 +11100 1 +.names i_11_ i_4_ i_13_ i_5_ i_3_ n127 +11000 1 +.names i_7_ i_8_ n128 +11 1 +.names i_12_ i_9_ n129 +11 1 +.names i_8_ i_6_ i_5_ n133 n131 n132 n130 +1101-- 1 +110-10 1 +.names i_11_ i_13_ i_9_ n131 +100 1 +.names i_0_ i_2_ i_4_ i_12_ i_3_ n132 +001-- 0 +00-00 0 +.names i_9_ i_12_ i_3_ i_2_ i_11_ i_0_ n133 +111100 1 +.names n135 n136 n67 n91 n42 i_9_ n134 +1----- 0 +-11--- 0 +---111 0 +.names i_12_ i_4_ i_5_ i_13_ i_9_ i_10_ n135 +111000 1 +.names i_11_ i_7_ i_12_ i_13_ i_10_ n136 +11000 1 +.names i_11_ i_1_ i_2_ i_12_ i_0_ i_8_ n137 +111000 1 +.names n139 n99 i_8_ i_3_ i_12_ i_11_ n138 +1100-0 1 +11100- 1 +.names i_13_ i_9_ n139 +00 1 +.names i_1_ i_9_ n140 +11 1 +.names i_0_ i_2_ i_7_ i_3_ i_8_ n141 +111-- 1 +11-11 1 +.names i_12_ i_11_ i_13_ i_0_ i_1_ i_2_ n142 +100000 1 +.names i_11_ i_3_ i_1_ i_12_ i_4_ i_0_ n143 +111000 1 +.names i_3_ i_8_ n142 n87 i_9_ n144 +001-- 1 +00-10 1 +.names n101 n146 n88 i_2_ i_0_ n145 +11--- 1 +1-110 1 +.names i_12_ i_4_ i_13_ i_0_ i_10_ i_3_ n146 +110000 1 +.names i_12_ i_13_ i_10_ n147 +100 1 +.names n99 n71 i_12_ n148 +00- 1 +0-0 1 +.names i_0_ n152 n150 n155 n154 n156 n149 +01---- 1 +0-01-- 1 +0---10 1 +.names n56 i_7_ n151 i_3_ i_8_ n150 +01-0- 1 +01--1 1 +0-0-- 1 +.names i_1_ i_2_ n151 +11 1 +.names i_12_ i_13_ n153 i_1_ i_6_ i_11_ n152 +01---- 1 +10-000 1 +1-1--- 1 +.names i_11_ i_13_ i_2_ i_7_ i_6_ i_10_ n153 +000000 1 +.names i_7_ i_6_ i_8_ n154 +000 1 +.names i_10_ i_12_ n155 +10 1 +.names i_12_ i_10_ i_11_ i_3_ i_13_ i_4_ n156 +0111-- 0 +0-1--0 0 +10000- 0 +10--01 0 +.names n108 n54 i_2_ i_6_ i_1_ n157 +110-- 1 +1--10 1 +.names i_7_ i_6_ i_8_ n158 +111 1 +.names i_1_ i_3_ n159 +11 1 +.names i_11_ i_4_ i_13_ i_9_ n160 +1100 1 +.names i_11_ i_12_ i_13_ i_0_ i_1_ i_2_ n161 +100000 1 +.names n113 n62 n59 n60 n61 n162 +11--- 1 +1-1-- 1 +1--10 1 +.names i_10_ n160 n50 n108 i_9_ n163 +01--- 1 +0-110 1 +.names n173 n166 n165 n170 n90 n93 n164 +10001- 1 +1000-0 1 +.names n42 i_10_ i_7_ i_3_ i_8_ n165 +110-- 1 +11-10 1 +.names i_1_ n169 n167 n168 i_6_ n166 +111-- 1 +1--10 1 +.names i_2_ i_3_ n167 +11 1 +.names i_10_ i_11_ n168 +10 1 +.names i_10_ i_11_ i_8_ n169 +100 1 +.names n172 n33 i_10_ i_8_ n171 n170 +010-- 1 +0--11 1 +.names i_12_ i_13_ i_10_ n171 +000 1 +.names i_0_ i_3_ i_2_ i_6_ i_1_ i_7_ n172 +1000-- 0 +10--00 0 +.names n160 n174 i_12_ i_2_ i_6_ n92 n173 +10---- 0 +--1111 0 +.names i_0_ i_2_ i_6_ i_3_ i_8_ i_1_ n174 +0010-- 0 +00--10 0 +.names n176 n73 i_6_ i_3_ i_8_ i_12_ n175 +11000- 1 +1100-0 1 +.names i_11_ i_13_ n176 +00 1 +.names n178 i_5_ n153 n179 n180 i_4_ n177 +00001- 1 +0000-1 1 +.names i_10_ i_6_ i_1_ i_13_ i_12_ i_11_ n178 +0000-0 1 +01000- 1 +101--- 1 +1--1-- 1 +.names i_4_ i_13_ i_7_ i_6_ i_8_ i_10_ n179 +100000 1 +.names i_11_ i_10_ i_12_ i_6_ i_8_ i_7_ n180 +111--- 0 +11-000 0 +.names i_7_ i_6_ i_11_ i_13_ i_9_ i_8_ n181 +110000 1 +.names i_12_ i_13_ n182 +00 1 +.names i_11_ i_12_ i_9_ i_4_ i_3_ i_8_ n183 +1110-- 1 +111-11 1 +.names i_9_ i_12_ i_4_ i_3_ i_13_ n184 +0-1-0 0 +110-- 0 +11-1- 0 +.names i_9_ i_12_ i_2_ i_7_ i_6_ i_11_ n185 +11111- 1 +1111-1 1 +.names n187 i_9_ n65 i_13_ i_2_ n186 +1---- 0 +-0000 0 +.names n33 i_9_ i_10_ n187 +100 1 +.names i_1_ n189 i_6_ n111 i_5_ n188 +00--- 1 +0-111 1 +.names n33 i_5_ i_7_ i_8_ i_10_ i_9_ n189 +10000- 0 +1111-0 0 +.names i_6_ i_5_ i_7_ i_13_ i_10_ i_9_ n190 +00000- 0 +1110-0 0 +.names n140 i_10_ n182 n67 i_11_ n191 +11--- 0 +1-110 0 +.names i_13_ i_9_ i_10_ n35 n34 n192 +00000 1 +.names i_9_ i_10_ i_7_ i_6_ i_12_ i_11_ n193 +1100-1 0 +11111- 0 +.names n195 i_11_ i_13_ n70 n31 i_3_ n194 +100-0- 1 +100--0 1 +111--- 1 +11-0-- 1 +.names n50 n108 n34 i_11_ i_4_ n195 +11--- 0 +--100 0 +.names i_12_ i_4_ i_13_ i_11_ i_3_ i_10_ n196 +00-1-- 0 +110--0 0 +1-000- 0 +.names i_11_ i_4_ i_3_ i_2_ n198 i_13_ n197 +0010-- 0 +1100-0 0 +----0- 0 +.names i_10_ i_11_ n33 n31 i_3_ n70 n198 +0110-- 0 +10--10 0 +.names n202 n187 n201 i_2_ n200 i_7_ n199 +100-1- 0 +100--1 0 +---0-- 0 +.names i_3_ i_10_ i_8_ n33 n176 n182 n200 +000-1- 0 +001--1 0 +00-1-- 0 +.names n27 n33 n34 n35 i_13_ n201 +001-- 1 +00-1- 1 +00--1 1 +.names i_9_ i_10_ i_3_ i_11_ i_12_ i_13_ n202 +000000 0 +111--- 0 +.names n205 i_2_ n204 n70 n124 n53 n203 +10-0-0 1 +10--0- 1 +1110-- 1 +1-1-0- 1 +.names n139 i_3_ i_8_ i_4_ i_12_ i_11_ n204 +100--0 0 +101-0- 0 +10-1-- 0 +.names i_3_ i_4_ i_2_ i_12_ i_8_ i_13_ n205 +1000-- 0 +111-10 0 +.names n26 n105 n207 i_3_ i_12_ n206 +11--- 0 +--110 0 +.names i_7_ i_9_ i_8_ n207 +111 1 +.names i_13_ n81 n78 n77 n208 +1--- 0 +-110 0 +.names n176 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n358 n130 n125 n439 n440 n441 +10000- 1 +1000-0 1 +.names i_12_ n360 i_9_ n359 n140 i_6_ n442 +011--- 0 +0---11 0 +-101-- 0 +.names i_7_ n142 n143 n140 n141 n443 +01--- 0 +0-1-- 0 +---11 0 +.names n443 n442 n362 n145 n144 n138 n444 +110000 1 +.names n185 n184 n181 n158 i_3_ n111 n445 +010--0 1 +01--1- 1 +0-00-- 1 +0--01- 1 +.names n177 n175 n374 n445 i_5_ n183 n446 +10---- 1 +--1110 1 +.names i_0_ n376 n372 n446 n186 n188 n447 +0----- 0 +-11110 0 +.names n182 i_8_ i_10_ i_3_ i_7_ i_2_ n448 +1100-0 1 +110-0- 1 +---10- 1 +.names i_6_ i_3_ n30 i_1_ n31 i_12_ n449 +00---- 1 +0-11-- 1 +11--10 1 +.names n237 n238 n241 i_11_ n448 n449 n450 +000-0- 1 +000--0 1 +00-0-- 1 +.names i_1_ i_2_ i_5_ i_0_ i_7_ i_6_ n451 +000111 1 +010101 1 +011001 1 +100110 1 +101010 1 +110100 1 +111000 1 +.names n242 n400 n451 i_8_ n53 n452 +1---- 1 +-0--- 1 +--111 1 +.names i_7_ i_6_ n169 n295 i_1_ i_2_ n453 +001--- 1 +0-1-0- 1 +11-1-- 1 +1--10- 1 +-01--0 1 +-1-1-0 1 +.names n404 n299 n297 n296 n453 i_0_ n454 +11100- 0 +1110-1 0 +.names n410 n407 n281 n454 n266 n455 +0000- 1 +000-0 1 +.names i_11_ i_9_ i_13_ i_3_ i_8_ i_12_ n456 +1001-- 1 +100-10 1 +.names n456 i_3_ i_10_ n416 n302 n319 n457 +1000-- 0 +100--0 0 +11-10- 0 +.names n420 n457 n415 n307 i_3_ n412 n458 +11001- 1 +1100-0 1 +.names i_5_ i_6_ i_3_ n293 n288 i_9_ n459 +110-11 0 +1111-- 0 +.names n250 n421 n328 n459 n460 +0--- 1 +-111 1 +.names i_8_ i_7_ n323 i_10_ n277 i_6_ n461 +00--10 0 +1111-- 0 +.names n422 n266 n461 n99 n97 i_8_ n462 +101--- 1 +10---1 1 +1-1-0- 1 +---0-- 1 +.names n460 n426 n462 n424 n332 n329 n463 +111000 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v b/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v new file mode 100644 index 000000000..7933f62cb --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v @@ -0,0 +1,896 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module alu4(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_); + input i_0_; + input i_10_; + input i_11_; + input i_12_; + input i_13_; + input i_1_; + input i_2_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + input i_9_; + wire n100; + wire n101; + wire n102; + wire n103; + wire n104; + wire n105; + wire n106; + wire n107; + wire n108; + wire n109; + wire n110; + wire n111; + wire n112; + wire n113; + wire n114; + wire n115; + wire n116; + wire n117; + wire n118; + wire n119; + wire n120; + wire n121; + wire n122; + wire n123; + wire n124; + wire n125; + wire n126; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n26; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n27; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n28; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n29; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n30; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n31; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n33; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n34; + wire n340; + wire n341; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n35; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n36; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n37; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n377; + wire n378; + wire n38; + wire n380; + wire n381; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n39; + wire n390; + wire n391; + wire n392; + wire n393; + wire n394; + wire n395; + wire n397; + wire n398; + wire n399; + wire n40; + wire n400; + wire n401; + wire n402; + wire n403; + wire n404; + wire n405; + wire n406; + wire n407; + wire n408; + wire n409; + wire n41; + wire n410; + wire n411; + wire n412; + wire n413; + wire n414; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n42; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n427; + wire n428; + wire n43; + wire n430; + wire n431; + wire n432; + wire n433; + wire n434; + wire n436; + wire n437; + wire n438; + wire n439; + wire n44; + wire n440; + wire n441; + wire n442; + wire n443; + wire n444; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n45; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n455; + wire n456; + wire n457; + wire n458; + wire n459; + wire n46; + wire n460; + wire n461; + wire n462; + wire n463; + wire n47; + wire n48; + wire n49; + wire n50; + wire n51; + wire n52; + wire n53; + wire n54; + wire n55; + wire n56; + wire n57; + wire n58; + wire n59; + wire n60; + wire n61; + wire n62; + wire n63; + wire n64; + wire n65; + wire n66; + wire n67; + wire n68; + wire n69; + wire n70; + wire n71; + wire n72; + wire n73; + wire n74; + wire n75; + wire n76; + wire n77; + wire n78; + wire n79; + wire n80; + wire n81; + wire n82; + wire n83; + wire n84; + wire n85; + wire n86; + wire n87; + wire n88; + wire n89; + wire n90; + wire n91; + wire n92; + wire n93; + wire n94; + wire n95; + wire n96; + wire n97; + wire n98; + wire n99; + output o_0_; + output o_1_; + output o_2_; + output o_3_; + output o_4_; + output o_5_; + output o_6_; + output o_7_; + assign o_0_ = 64'hfffefffefffefefe >> { n30, n31, i_3_, n28, n29, n26 }; + assign n34 = 4'h8 >> { i_8_, i_12_ }; + assign n124 = 4'h2 >> { i_13_, i_12_ }; + assign n125 = 8'ha8 >> { n127, n126, n49 }; + assign n126 = 32'd128 >> { i_3_, i_13_, i_5_, i_4_, i_12_ }; + assign n127 = 32'd8 >> { i_3_, i_5_, i_13_, i_4_, i_11_ }; + assign n128 = 4'h8 >> { i_8_, i_7_ }; + assign n129 = 4'h8 >> { i_9_, i_12_ }; + assign n130 = 64'h0800080008080800 >> { n132, n131, n133, i_5_, i_6_, i_8_ }; + assign n131 = 8'h02 >> { i_9_, i_13_, i_11_ }; + assign n132 = 32'd4025479150 >> { i_3_, i_12_, i_4_, i_2_, i_0_ }; + assign n133 = 64'h0000000000008000 >> { i_0_, i_11_, i_2_, i_3_, i_12_, i_9_ }; + assign n35 = 4'h2 >> { i_8_, i_11_ }; + assign n134 = 64'h0015151515151515 >> { i_9_, n42, n91, n67, n136, n135 }; + assign n135 = 64'h0000000000000080 >> { i_10_, i_9_, i_13_, i_5_, i_4_, i_12_ }; + assign n136 = 32'd8 >> { i_10_, i_13_, i_12_, i_7_, i_11_ }; + assign n137 = 64'h0000000000000080 >> { i_8_, i_0_, i_12_, i_2_, i_1_, i_11_ }; + assign n138 = 64'h0000008000080088 >> { i_11_, i_12_, i_3_, i_8_, n99, n139 }; + assign n139 = 4'h1 >> { i_9_, i_13_ }; + assign n140 = 4'h8 >> { i_9_, i_1_ }; + assign n141 = 32'd2290122880 >> { i_8_, i_3_, i_7_, i_2_, i_0_ }; + assign n142 = 64'h0000000000000002 >> { i_2_, i_1_, i_0_, i_13_, i_11_, i_12_ }; + assign n143 = 64'h0000000000000080 >> { i_0_, i_4_, i_12_, i_1_, i_3_, i_11_ }; + assign n36 = 4'h1 >> { i_6_, i_5_ }; + assign n144 = 32'd269488400 >> { i_9_, n87, n142, i_8_, i_3_ }; + assign n145 = 32'd2290657416 >> { i_0_, i_2_, n88, n146, n101 }; + assign n146 = 64'h0000000000000008 >> { i_3_, i_10_, i_0_, i_13_, i_4_, i_12_ }; + assign n147 = 8'h02 >> { i_10_, i_13_, i_12_ }; + assign n148 = 8'h15 >> { i_12_, n71, n99 }; + assign n149 = 64'h4544454455554544 >> { n156, n154, n155, n150, n152, i_0_ }; + assign n150 = 32'd1162151237 >> { i_8_, i_3_, n151, i_7_, n56 }; + assign n151 = 4'h8 >> { i_2_, i_1_ }; + assign n152 = 64'he4e4e4e4e4e4e4e6 >> { i_11_, i_6_, i_1_, n153, i_13_, i_12_ }; + assign n153 = 64'h0000000000000001 >> { i_10_, i_6_, i_7_, i_2_, i_13_, i_11_ }; + assign n37 = 16'hdd0d >> { i_5_, i_1_, i_6_, i_0_ }; + assign n154 = 8'h01 >> { i_8_, i_6_, i_7_ }; + assign n155 = 4'h2 >> { i_12_, i_10_ }; + assign n156 = 64'hbfff9dddafafafad >> { i_4_, i_13_, i_3_, i_11_, i_10_, i_12_ }; + assign n157 = 32'd134785544 >> { i_1_, i_6_, i_2_, n54, n108 }; + assign n158 = 8'h80 >> { i_8_, i_6_, i_7_ }; + assign n159 = 4'h8 >> { i_3_, i_1_ }; + assign n160 = 16'h0008 >> { i_9_, i_13_, i_4_, i_11_ }; + assign n161 = 64'h0000000000000002 >> { i_2_, i_1_, i_0_, i_13_, i_12_, i_11_ }; + assign n162 = 32'd2829626024 >> { n61, n60, n59, n62, n113 }; + assign n163 = 32'd1145328708 >> { i_9_, n108, n50, n160, i_10_ }; + assign n38 = 64'h4555055544550455 >> { i_7_, n37, i_3_, i_2_, n39, i_12_ }; + assign n164 = 64'h0002000000020002 >> { n93, n90, n170, n165, n166, n173 }; + assign n165 = 32'd134776840 >> { i_8_, i_3_, i_7_, i_10_, n42 }; + assign n166 = 32'd2155915904 >> { i_6_, n168, n167, n169, i_1_ }; + assign n167 = 4'h8 >> { i_3_, i_2_ }; + assign n168 = 4'h2 >> { i_11_, i_10_ }; + assign n169 = 8'h02 >> { i_8_, i_11_, i_10_ }; + assign n170 = 32'd1426326532 >> { n171, i_8_, i_10_, n33, n172 }; + assign n171 = 8'h01 >> { i_10_, i_13_, i_12_ }; + assign n172 = 64'hfffdfffdfffddddd >> { i_7_, i_1_, i_6_, i_2_, i_3_, i_0_ }; + assign n173 = 64'h0ddddddddddddddd >> { n92, i_6_, i_2_, i_12_, n174, n160 }; + assign n39 = 4'h1 >> { n36, n40 }; + assign n174 = 64'hffefffefeeeeffef >> { i_1_, i_8_, i_3_, i_6_, i_2_, i_0_ }; + assign n175 = 64'h0000000800080008 >> { i_12_, i_8_, i_3_, i_6_, n73, n176 }; + assign n176 = 4'h1 >> { i_13_, i_11_ }; + assign n177 = 64'h0001000100010000 >> { i_4_, n180, n179, n153, i_5_, n178 }; + assign n178 = 64'haa20aa24aa21aa25 >> { i_11_, i_12_, i_13_, i_1_, i_6_, i_10_ }; + assign n179 = 64'h0000000000000002 >> { i_10_, i_8_, i_6_, i_7_, i_13_, i_4_ }; + assign n180 = 64'h7f7f7f7f7f7f7f77 >> { i_7_, i_8_, i_6_, i_12_, i_10_, i_11_ }; + assign n181 = 64'h0000000000000008 >> { i_8_, i_9_, i_13_, i_11_, i_6_, i_7_ }; + assign n182 = 4'h1 >> { i_13_, i_12_ }; + assign n183 = 64'h8080008000800080 >> { i_8_, i_3_, i_4_, i_9_, i_12_, i_11_ }; + assign n40 = 32'd1079002196 >> { i_5_, i_6_, i_0_, i_1_, i_7_ }; + assign n184 = 32'd2012686247 >> { i_13_, i_3_, i_4_, i_12_, i_9_ }; + assign n185 = 64'h8000800080000000 >> { i_11_, i_6_, i_7_, i_2_, i_12_, i_9_ }; + assign n186 = 32'd1431655764 >> { i_2_, i_13_, n65, i_9_, n187 }; + assign n187 = 8'h02 >> { i_10_, i_9_, n33 }; + assign n188 = 32'd1360072977 >> { i_5_, n111, i_6_, n189, i_1_ }; + assign n189 = 64'hfffffffd7fff7ffd >> { i_9_, i_10_, i_8_, i_7_, i_5_, n33 }; + assign n190 = 64'hfffffffeff7fff7e >> { i_9_, i_10_, i_13_, i_7_, i_5_, i_6_ }; + assign n191 = 32'd2004309879 >> { i_11_, n67, n182, i_10_, n140 }; + assign n192 = 32'd1 >> { n34, n35, i_10_, i_9_, i_13_ }; + assign n193 = 64'h7ff7fff77fffffff >> { i_11_, i_12_, i_6_, i_7_, i_10_, i_9_ }; + assign n41 = 32'd2863311522 >> { i_3_, n34, n35, n27, n42 }; + assign n194 = 64'h8088828a828a828a >> { i_3_, n31, n70, i_13_, i_11_, n195 }; + assign n195 = 32'd2004317959 >> { i_4_, i_11_, n34, n108, n50 }; + assign n196 = 64'heeffeef5e6f7e6f5 >> { i_10_, i_3_, i_11_, i_13_, i_4_, i_12_ }; + assign n197 = 64'hffef0000ffe70000 >> { i_13_, n198, i_2_, i_3_, i_4_, i_11_ }; + assign n198 = 64'hffbfffbfdd9dffbf >> { n70, i_3_, n31, n33, i_11_, i_10_ }; + assign n199 = 64'hfd00fd00fd00ff00 >> { i_7_, n200, i_2_, n201, n187, n202 }; + assign n200 = 64'heeeeeeefeefeeeff >> { n182, n176, n33, i_8_, i_10_, i_3_ }; + assign n201 = 32'd286331152 >> { i_13_, n35, n34, n33, n27 }; + assign n202 = 64'h7f7f7f7f7f7f7f7e >> { i_13_, i_12_, i_11_, i_3_, i_10_, i_9_ }; + assign n203 = 64'h0080a2a200a2a2a2 >> { n53, n124, n70, n204, i_2_, n205 }; + assign n42 = 8'h80 >> { i_2_, i_1_, i_0_ }; + assign n204 = 64'hddffdddfddfddddd >> { i_11_, i_12_, i_4_, i_8_, i_3_, n139 }; + assign n205 = 64'hfffdfffd7f7dfffd >> { i_13_, i_8_, i_12_, i_2_, i_4_, i_3_ }; + assign n206 = 32'd2004289399 >> { i_12_, i_3_, n207, n105, n26 }; + assign n207 = 8'h80 >> { i_8_, i_9_, i_7_ }; + assign n208 = 16'h5515 >> { n77, n78, n81, i_13_ }; + assign n209 = 32'd526344 >> { i_12_, i_8_, i_6_, n73, n176 }; + assign n210 = 8'h15 >> { n111, n158, n181 }; + assign n211 = 4'h8 >> { i_10_, i_9_ }; + assign n212 = 64'hfa50fa50c800c040 >> { i_13_, i_7_, i_9_, i_10_, i_2_, i_6_ }; + assign n213 = 32'd33685506 >> { n217, n216, n214, n215, n218 }; + assign n43 = 32'd1467441023 >> { i_1_, i_0_, i_6_, i_5_, i_2_ }; + assign n214 = 64'h0800080008000808 >> { i_3_, i_11_, i_4_, i_8_, n73, n124 }; + assign n215 = 8'h08 >> { i_7_, n155, i_2_ }; + assign n216 = 4'h2 >> { i_12_, i_11_ }; + assign n217 = 64'hfdd0fdddffd0ffdd >> { i_10_, i_2_, i_4_, i_8_, i_7_, i_3_ }; + assign n218 = 32'd3149642681 >> { i_7_, i_2_, i_11_, i_13_, i_12_ }; + assign n219 = 4'h2 >> { i_11_, n124 }; + assign n220 = 64'haa08aa00aa08aa08 >> { i_2_, n73, n74, i_1_, n53, n124 }; + assign n221 = 64'h5454545455545454 >> { i_4_, n227, n216, n226, n222, i_1_ }; + assign n222 = 32'd1157973317 >> { n224, n223, n225, i_7_, i_6_ }; + assign n223 = 32'd2155905160 >> { i_3_, i_12_, i_4_, n131, i_8_ }; + assign n26 = 4'h2 >> { n27, i_2_ }; + assign n44 = 32'd1465341951 >> { i_5_, i_0_, i_6_, i_1_, i_7_ }; + assign n224 = 64'h7077f0ff70777077 >> { i_4_, n31, n108, i_2_, n96, i_3_ }; + assign n225 = 32'd3104422667 >> { n53, n90, i_2_, i_13_, i_11_ }; + assign n226 = 32'd134744064 >> { i_2_, i_7_, i_11_, n103, n34 }; + assign n227 = 8'h02 >> { i_8_, i_7_, i_6_ }; + assign n228 = 64'h0200020002020200 >> { i_3_, n108, n160, i_2_, i_1_, i_8_ }; + assign n229 = 64'h2200222022202220 >> { i_2_, i_7_, n230, n35, i_10_, n33 }; + assign n230 = 8'h02 >> { i_3_, i_2_, i_1_ }; + assign n231 = 64'h0800080008080800 >> { i_4_, i_11_, i_3_, i_8_, n151, i_10_ }; + assign n232 = 64'h8000800080008808 >> { i_3_, i_11_, i_4_, i_8_, n54, n124 }; + assign n233 = 32'd572662434 >> { i_8_, i_6_, n110, n234, n230 }; + assign n45 = 64'hff3f5f0f77335501 >> { i_6_, i_7_, i_5_, i_1_, i_2_, i_0_ }; + assign n234 = 64'hfdfffdfffdfdfdff >> { i_12_, i_8_, i_4_, i_13_, i_9_, i_6_ }; + assign n235 = 64'h1555555555555555 >> { i_3_, i_7_, i_12_, n56, n30, n236 }; + assign n236 = 64'h0008000000080008 >> { i_7_, i_9_, i_6_, i_11_, i_2_, i_10_ }; + assign n237 = 64'h0000000000000080 >> { i_10_, i_9_, i_13_, i_6_, i_4_, i_12_ }; + assign n238 = 64'h8880080008000800 >> { n105, i_1_, i_2_, i_12_, i_9_, n82 }; + assign n239 = 16'h0080 >> { i_6_, i_7_, n34, n168 }; + assign n240 = 32'd1431393360 >> { i_11_, i_12_, i_1_, i_6_, n28 }; + assign n241 = 64'h2000200022222000 >> { i_2_, n70, n27, n53, i_1_, n124 }; + assign n242 = 32'd2861206154 >> { n243, n49, n245, n54, n244 }; + assign n243 = 8'h08 >> { i_8_, i_6_, i_7_ }; + assign n46 = 64'h8888880080808000 >> { i_6_, i_0_, i_5_, i_1_, i_3_, i_7_ }; + assign n244 = 8'h80 >> { i_3_, i_5_, i_4_ }; + assign n245 = 64'hfffffffffffffbd7 >> { i_8_, i_0_, i_6_, i_7_, i_2_, i_1_ }; + assign n246 = 64'h0000000080000000 >> { i_9_, i_3_, i_7_, i_1_, i_0_, i_4_ }; + assign n247 = 64'hfffffffffdfff77f >> { i_8_, i_2_, i_6_, i_1_, i_7_, i_0_ }; + assign n248 = 64'h2222222222222202 >> { n258, n254, n256, n249, i_5_, n105 }; + assign n249 = 64'h00110fff01110fff >> { n171, n251, n250, n252, n161, n253 }; + assign n250 = 8'h08 >> { i_2_, i_1_, i_0_ }; + assign n251 = 8'h08 >> { i_6_, i_8_, i_7_ }; + assign n252 = 64'h0000000000000002 >> { i_10_, i_6_, i_7_, i_13_, i_11_, i_8_ }; + assign n253 = 64'h0000000000000008 >> { i_10_, i_1_, i_13_, i_11_, i_2_, i_0_ }; + assign n47 = 64'h777f7f7f77ff7fff >> { i_1_, i_0_, i_6_, i_5_, i_3_, i_2_ }; + assign n254 = 16'ha888 >> { n171, n255, n107, n158 }; + assign n255 = 8'h08 >> { i_1_, i_2_, i_0_ }; + assign n256 = 32'd2290122880 >> { i_10_, i_6_, n158, n108, n257 }; + assign n257 = 8'h02 >> { i_1_, i_0_, i_2_ }; + assign n258 = 8'h80 >> { n99, n87, n259 }; + assign n259 = 8'h08 >> { i_7_, i_6_, i_8_ }; + assign n260 = 16'h0008 >> { i_13_, i_11_, i_12_, i_10_ }; + assign n261 = 8'h02 >> { i_2_, i_0_, i_1_ }; + assign n262 = 8'h02 >> { i_6_, i_7_, i_8_ }; + assign n263 = 64'haaa8a8a8a8a8a8a8 >> { i_8_, i_5_, n82, n265, n264, n266 }; + assign n48 = 4'h1 >> { i_3_, i_2_ }; + assign n264 = 64'h8888800080008000 >> { i_1_, i_5_, i_6_, i_0_, i_10_, n167 }; + assign n265 = 32'd134742024 >> { i_5_, i_0_, i_11_, i_6_, n48 }; + assign n266 = 4'h2 >> { i_12_, i_13_ }; + assign n267 = 64'h5555555515555555 >> { i_2_, n270, n36, n128, n105, n268 }; + assign n268 = 64'h0000008000080088 >> { i_11_, i_12_, i_4_, i_5_, n269, i_10_ }; + assign n269 = 8'h80 >> { i_3_, i_2_, i_1_ }; + assign n270 = 16'h0002 >> { i_10_, i_13_, i_12_, i_11_ }; + assign n271 = 64'h0002020202020202 >> { i_6_, n279, n278, n272, n273, n274 }; + assign n272 = 64'h0000080000000880 >> { i_13_, i_5_, i_10_, i_4_, n154, i_3_ }; + assign n273 = 8'h80 >> { n158, n139, n244 }; + assign n49 = 8'h01 >> { i_2_, i_1_, i_0_ }; + assign n274 = 64'h0000777077707770 >> { n275, n276, n202, i_4_, n243, n277 }; + assign n275 = 32'd128 >> { i_7_, i_12_, i_10_, i_13_, i_8_ }; + assign n276 = 8'h01 >> { i_3_, i_6_, i_5_ }; + assign n277 = 64'h0000000000000080 >> { i_3_, i_9_, i_13_, i_5_, i_4_, i_11_ }; + assign n278 = 4'h2 >> { i_3_, i_5_ }; + assign n279 = 32'd128 >> { i_8_, i_11_, i_7_, i_13_, i_9_ }; + assign n280 = 32'd4278189309 >> { n210, n209, i_3_, i_4_, i_5_ }; + assign n281 = 64'h2020202020202022 >> { i_13_, n283, i_10_, n282, i_9_, i_4_ }; + assign n282 = 64'h8000800080808000 >> { i_10_, i_1_, i_6_, n128, n124, i_5_ }; + assign n283 = 32'd125269879 >> { i_2_, i_0_, n159, n40, n35 }; + assign n50 = 4'h2 >> { i_3_, i_8_ }; + assign n284 = 8'h02 >> { i_8_, i_6_, i_7_ }; + assign n285 = 64'hfff7ffffffff7ff7 >> { i_6_, i_1_, i_7_, i_2_, i_8_, i_0_ }; + assign n286 = 64'h0082000200800000 >> { n108, n131, i_5_, i_3_, i_4_, n262 }; + assign n287 = 64'h0000077707770777 >> { n288, n276, n243, n289, n154, n127 }; + assign n288 = 16'h0002 >> { i_8_, i_7_, i_11_, i_13_ }; + assign n289 = 64'h0000000000000008 >> { i_3_, i_13_, i_4_, i_11_, i_12_, i_5_ }; + assign n290 = 64'h0ddddddddddddddd >> { n129, n91, n259, n176, n291, n266 }; + assign n291 = 64'haeeeeeeeeeeeeeee >> { i_7_, i_5_, i_8_, i_6_, i_11_, i_3_ }; + assign n292 = 32'd2105540095 >> { n294, n293, i_6_, i_5_, i_3_ }; + assign n293 = 32'd128 >> { i_7_, i_11_, i_8_, i_13_, i_9_ }; + assign n51 = 32'd1381653 >> { i_5_, i_0_, i_6_, i_1_, i_3_ }; + assign n294 = 32'd128 >> { i_8_, i_12_, i_7_, i_13_, i_10_ }; + assign n295 = 8'h08 >> { i_11_, i_9_, i_8_ }; + assign n296 = 64'h0000000000000002 >> { i_3_, i_6_, i_2_, i_5_, i_11_, i_10_ }; + assign n297 = 32'd2004289399 >> { n298, n31, i_10_, n92, n51 }; + assign n298 = 64'h015533770f5f3fff >> { i_6_, i_7_, i_5_, i_1_, i_2_, i_0_ }; + assign n299 = 64'hddcdefcdffefefef >> { n295, i_6_, i_1_, n169, i_2_, i_5_ }; + assign n300 = 64'h0000dd0ddd0ddd0d >> { n262, n270, n302, n301, n247, n87 }; + assign n301 = 16'h0002 >> { i_9_, i_13_, i_12_, i_11_ }; + assign n302 = 64'hffffffff7dffff7f >> { i_0_, i_6_, i_1_, i_2_, i_7_, i_8_ }; + assign n303 = 64'h0000dd0ddd0ddd0d >> { n181, i_12_, n285, n301, n245, n87 }; + assign n52 = 32'd1162149957 >> { i_5_, i_0_, i_1_, i_6_, i_3_ }; + assign n304 = 16'h0002 >> { i_10_, i_9_, i_13_, i_11_ }; + assign n305 = 64'hdddfdfdfddffdfff >> { i_1_, i_3_, i_6_, i_8_, i_9_, i_7_ }; + assign n306 = 32'd8 >> { i_10_, i_7_, i_13_, n36, n35 }; + assign n307 = 64'haaaaaaaaaaaaaaa2 >> { n316, n318, n314, n315, n308, n257 }; + assign n308 = 64'h0000077707770777 >> { n312, n310, n311, n284, n309, n313 }; + assign n309 = 8'h80 >> { i_3_, i_6_, i_5_ }; + assign n310 = 16'h0080 >> { i_11_, i_7_, i_13_, i_9_ }; + assign n311 = 64'h0000000000000008 >> { i_3_, i_9_, i_5_, i_13_, i_4_, i_11_ }; + assign n312 = 16'h0009 >> { i_6_, i_5_, i_3_, i_8_ }; + assign n313 = 32'd8 >> { i_8_, i_7_, i_12_, i_13_, i_10_ }; + assign n53 = 4'h2 >> { i_3_, i_4_ }; + assign n314 = 32'd32768 >> { i_5_, n105, n113, n227, n155 }; + assign n315 = 16'h8000 >> { n176, n91, n129, n251 }; + assign n316 = 4'h8 >> { n260, n317 }; + assign n317 = 64'h0000000000000008 >> { i_8_, i_6_, i_7_, i_4_, i_5_, i_3_ }; + assign n318 = 8'h80 >> { n278, n275, i_6_ }; + assign n319 = 64'hffdfffdfddddffdf >> { i_7_, i_1_, i_6_, i_2_, i_4_, i_0_ }; + assign n320 = 32'd1431639381 >> { i_7_, n36, n321, n30, n322 }; + assign n321 = 4'h2 >> { i_11_, i_13_ }; + assign n322 = 32'd128 >> { i_12_, i_11_, i_13_, i_10_, i_9_ }; + assign n323 = 8'h02 >> { i_3_, i_5_, i_6_ }; + assign n27 = 8'h1b >> { i_9_, i_10_, i_7_ }; + assign n54 = 8'h08 >> { i_9_, i_6_, i_7_ }; + assign n324 = 8'h02 >> { i_3_, i_6_, i_5_ }; + assign n325 = 16'h8000 >> { n128, n266, n324, i_10_ }; + assign n326 = 4'h8 >> { n227, n311 }; + assign n327 = 32'd8 >> { i_9_, i_13_, i_4_, i_3_, i_5_ }; + assign n328 = 64'hffff7fff7fffffff >> { i_3_, i_8_, n36, i_10_, n266, i_7_ }; + assign n329 = 32'd1414813012 >> { n58, n112, n331, n330, i_5_ }; + assign n330 = 64'h0080008088880080 >> { i_8_, n151, i_6_, n167, n304, i_4_ }; + assign n331 = 32'd128 >> { i_7_, i_11_, n269, n30, n103 }; + assign n332 = 16'h2aaa >> { n333, n334, n335, n93 }; + assign n333 = 64'he7f7efffefffefff >> { n207, n321, n275, i_5_, i_6_, i_3_ }; + assign n55 = 4'h2 >> { n56, i_5_ }; + assign n334 = 16'h0777 >> { n279, n323, n243, n311 }; + assign n335 = 64'h7777777707777777 >> { i_6_, i_3_, n313, i_5_, n155, n317 }; + assign n336 = 64'h0000077707770777 >> { n323, n275, n279, n324, n284, n277 }; + assign n337 = 32'd2860548224 >> { n155, n227, n101, n169, n327 }; + assign n338 = 64'h8000800080008888 >> { n45, i_8_, n36, n167, n321, n211 }; + assign n339 = 64'h5f4c0f0c5d4c0d0c >> { i_7_, n37, n45, n26, i_8_, n36 }; + assign n340 = 64'h0222022213330222 >> { n62, n58, n71, n70, n84, i_5_ }; + assign n341 = 64'h0000000000000080 >> { n68, n72, n80, n63, n75, n69 }; + assign o_3_ = 16'h7fff >> { n340, n344, n341, o_2_ }; + assign n343 = 64'h5707130355051101 >> { i_8_, i_6_, i_7_, i_2_, i_1_, i_3_ }; + assign n56 = 4'h2 >> { i_6_, i_1_ }; + assign n344 = 16'hff7f >> { i_9_, n343, i_5_, i_4_ }; + assign n345 = 64'h2030253522322737 >> { i_2_, i_10_, i_3_, i_7_, i_9_, i_8_ }; + assign n346 = 32'd1431655701 >> { i_1_, i_0_, i_4_, n345, n79 }; + assign n347 = 64'ha2a2eea2a0a0eca0 >> { n49, n148, n139, n85, i_8_, n147 }; + assign n348 = 64'h55005d085d085d08 >> { i_4_, n347, n164, n149, n444, i_5_ }; + assign n349 = 64'hfaaaf888f888f888 >> { i_10_, n42, n109, n108, n107, n105 }; + assign n350 = 64'h5555454d5555004c >> { i_1_, i_5_, i_6_, i_4_, i_3_, i_8_ }; + assign n351 = 64'h0f008f881f119f99 >> { i_11_, i_12_, i_4_, i_3_, i_5_, i_7_ }; + assign n352 = 64'h0000000800800088 >> { i_9_, i_10_, i_13_, i_5_, n351, n99 }; + assign n353 = 64'h0081008188891191 >> { i_2_, i_6_, i_1_, i_7_, i_8_, i_5_ }; + assign n57 = 8'h01 >> { i_9_, i_7_, i_11_ }; + assign n354 = 64'hff77fff7ff7fffff >> { n110, n111, i_3_, i_8_, i_0_, n353 }; + assign n355 = 64'h0808080808088808 >> { n76, n84, n346, n112, n114, n354 }; + assign n356 = 64'h4602020244000002 >> { i_4_, i_3_, i_11_, i_13_, i_10_, i_12_ }; + assign n357 = 64'h80aa008080800080 >> { i_6_, i_3_, i_4_, i_1_, i_8_, i_5_ }; + assign n358 = 16'h8000 >> { n357, i_7_, i_0_, n129 }; + assign n359 = 16'h0008 >> { i_3_, i_13_, i_0_, i_4_ }; + assign n360 = 64'h058045c405004544 >> { i_11_, i_1_, i_6_, i_2_, i_7_, i_9_ }; + assign n361 = 64'he8a8c888e0a0c000 >> { i_8_, i_7_, i_6_, i_3_, i_2_, i_1_ }; + assign n362 = 64'h5444444444444444 >> { i_9_, i_0_, i_12_, n361, n137, i_4_ }; + assign n363 = 64'hd8d85058c8884008 >> { i_2_, i_4_, i_3_, i_12_, i_8_, i_11_ }; + assign n58 = 8'h51 >> { n61, n60, n59 }; + assign n364 = 64'h9999b9999888a888 >> { n140, i_9_, i_7_, n363, i_13_, i_11_ }; + assign n365 = 32'd2867571439 >> { i_6_, n157, i_13_, n364, i_0_ }; + assign n366 = 64'hdf7fdf7f5777df7f >> { i_6_, i_3_, i_8_, i_1_, i_0_, i_2_ }; + assign n367 = 64'h55d5f5f54480f5f5 >> { n158, n366, i_7_, i_10_, n159, i_0_ }; + assign n368 = 32'd4286447487 >> { i_12_, i_4_, i_0_, i_11_, n367 }; + assign n369 = 64'h0000000000000008 >> { i_3_, i_9_, i_0_, i_13_, i_4_, i_11_ }; + assign n370 = 32'd926381879 >> { i_6_, i_1_, n369, i_7_, n161 }; + assign n371 = 64'h2050205022722050 >> { i_11_, n182, i_8_, n33, i_9_, i_6_ }; + assign n372 = 32'd4286578557 >> { i_10_, i_2_, i_6_, i_5_, n371 }; + assign n373 = 32'd1434408318 >> { i_11_, i_13_, i_1_, i_6_, i_9_ }; + assign n59 = 32'd2 >> { i_10_, i_8_, i_7_, i_1_, i_4_ }; + assign n374 = 32'd2863311522 >> { i_2_, i_13_, i_12_, n54, n373 }; + assign n375 = 32'd1997010695 >> { i_2_, n190, n53, n129, n94 }; + assign n376 = 32'd2147518472 >> { n192, n193, i_3_, n375, n191 }; + assign n377 = 64'hfa52aa02fa72aa22 >> { n30, n33, i_12_, i_3_, i_13_, i_7_ }; + assign n378 = 64'hfbddeaccf9dde8cc >> { n196, n194, n377, i_8_, i_2_, i_7_ }; + assign o_6_ = 64'hff77fff7ff7fffff >> { n197, n203, n199, i_7_, n378, n206 }; + assign n380 = 64'h92b293b312321333 >> { i_9_, n219, n155, i_3_, i_8_, i_2_ }; + assign n381 = 64'h1150554011105540 >> { i_12_, n380, i_1_, n213, i_8_, n220 }; + assign o_5_ = 64'hfff5fffdfff7ffff >> { n391, n381, n386, n221, i_6_, n393 }; + assign n383 = 32'd538976290 >> { i_7_, i_8_, i_12_, i_4_, i_11_ }; + assign n60 = 8'h02 >> { i_10_, i_2_, i_4_ }; + assign n384 = 64'h6e6e6e6e446e6e6e >> { n53, i_12_, n207, i_9_, n383, i_6_ }; + assign n385 = 16'h2131 >> { i_10_, n384, n212, i_6_ }; + assign n386 = 32'd2863311402 >> { n208, n388, n385, n186, i_1_ }; + assign n387 = 64'he444e040e040e040 >> { i_6_, n31, i_12_, n211, i_11_, i_7_ }; + assign n388 = 32'd3722304909 >> { n192, n209, n210, n387, i_3_ }; + assign n389 = 64'h1113131313131313 >> { i_12_, i_7_, i_3_, n167, n231, n169 }; + assign n390 = 64'h9dddbfffbfffbfff >> { n94, n105, n53, n131, i_7_, i_1_ }; + assign n391 = 32'd8 >> { n163, n228, n229, n390, n389 }; + assign n392 = 64'hffaeaeaeaeaeaeae >> { n34, i_2_, n28, n240, n167, n239 }; + assign n393 = 64'h0008000800000008 >> { i_4_, n392, n232, n233, n450, n235 }; + assign n61 = 16'heac8 >> { i_1_, i_8_, i_3_, i_6_ }; + assign n394 = 64'hff81ff01ff80ff00 >> { n30, n31, n211, i_5_, i_7_, i_6_ }; + assign n395 = 64'h55d5d5d5d5d5d5d5 >> { i_13_, i_3_, n394, n280, n271, n42 }; + assign o_7_ = 64'hffffffff7fffffff >> { n403, n398, n395, n455, n458, n463 }; + assign n397 = 64'h2222222202222222 >> { i_9_, i_4_, i_5_, n343, n72, n69 }; + assign n398 = 32'd232588629 >> { n75, n452, n147, n397, n112 }; + assign n399 = 64'ha8cca0cc88cc80cc >> { i_8_, i_6_, i_5_, i_1_, i_3_, i_2_ }; + assign n400 = 64'h00ff007f00f70077 >> { n247, i_9_, n246, i_5_, n399, i_4_ }; + assign n401 = 32'd2726330496 >> { n87, n261, n42, i_6_, i_8_ }; + assign n402 = 64'hf970b920d9509900 >> { n49, n257, n401, n260, i_7_, i_6_ }; + assign n403 = 64'hff00fd00fd00fd00 >> { n91, n402, i_9_, n248, n263, n267 }; + assign n62 = 32'd2 >> { i_10_, i_8_, i_6_, i_7_, i_4_ }; + assign n404 = 64'h7f7f7f7f557f7f7f >> { i_11_, i_7_, n52, n46, i_10_, i_9_ }; + assign n405 = 64'h64ec74fc44cc54dc >> { n73, i_2_, n285, i_1_, i_5_, i_4_ }; + assign n406 = 64'h88a8002000200020 >> { n99, n284, i_0_, n243, i_5_, n155 }; + assign n407 = 32'd2155905024 >> { i_4_, n406, i_3_, n405, n131 }; + assign n408 = 64'h0042004000400040 >> { i_10_, i_11_, i_13_, i_4_, i_12_, i_3_ }; + assign n409 = 64'hfffffff77fffffff >> { i_3_, i_8_, i_6_, i_5_, i_7_, n408 }; + assign n410 = 64'haaaaaaaa2aaaaaaa >> { n286, n409, n287, n290, n292, n49 }; + assign n411 = 64'h2202020202020202 >> { i_7_, i_1_, i_0_, n43, i_9_, n87 }; + assign n412 = 64'h0500454415115555 >> { n300, n303, n411, i_8_, i_5_, i_4_ }; + assign n413 = 64'hae2eae2eff7fae2e >> { i_7_, i_3_, i_9_, i_8_, i_2_, i_6_ }; + assign n63 = 16'h1011 >> { n67, n65, n66, n64 }; + assign n414 = 64'hdd7f5d5fff7f5f5f >> { n304, n305, n413, n147, i_6_, i_0_ }; + assign n415 = 8'ha2 >> { n306, n414, i_4_ }; + assign n416 = 64'h7745774577557745 >> { i_1_, i_6_, i_4_, i_2_, i_5_, i_3_ }; + assign n417 = 64'h5d5d5d5d595d5d5d >> { i_9_, n227, n260, i_4_, i_5_, i_2_ }; + assign n418 = 16'h0080 >> { i_12_, i_1_, i_6_, n207 }; + assign n419 = 16'hfff7 >> { i_7_, n37, n211, n321 }; + assign n420 = 64'h0880aaaa8880aaaa >> { n418, i_3_, n417, i_2_, n419, n320 }; + assign n421 = 64'h15373737153f3f3f >> { n168, n243, n155, n277, n227, n327 }; + assign n422 = 64'hf5fdf7fff7fff7ff >> { i_9_, n288, n293, i_6_, i_3_, i_5_ }; + assign n423 = 64'h929ab2ba828aa2aa >> { n288, n293, n294, i_6_, i_5_, i_3_ }; + assign n28 = 16'ha820 >> { i_9_, i_10_, i_6_, i_1_ }; + assign n64 = 32'd1 >> { n34, n35, i_3_, i_10_, i_9_ }; + assign n424 = 64'haaaaaa28aaaaaa20 >> { i_9_, n326, n325, i_3_, n423, n261 }; + assign n425 = 64'hd7f7dfffdfffdfff >> { i_8_, n310, n313, i_6_, i_5_, i_3_ }; + assign n426 = 32'd286347537 >> { n337, n336, n425, n255, n338 }; + assign n427 = 64'h2022202000220020 >> { n44, n27, i_8_, n43, n46, n47 }; + assign n428 = 64'h555d050d557f050f >> { i_11_, n427, i_0_, i_12_, i_5_, n28 }; + assign o_2_ = 64'hfdfdfffdfffdfffd >> { n38, n339, i_11_, n41, n29, n428 }; + assign n430 = 64'h3120312075753120 >> { i_10_, n33, n110, n108, i_3_, i_8_ }; + assign n431 = 64'h0022202202222222 >> { n99, n49, n430, i_8_, n163, n370 }; + assign n432 = 32'd2863327914 >> { n162, n431, n365, n368, i_5_ }; + assign n433 = 64'hfdf5fff7fff7fff7 >> { i_0_, n94, n86, i_7_, i_5_, n350 }; + assign n65 = 16'hfdec >> { i_11_, i_12_, i_10_, i_7_ }; + assign n434 = 64'h0000000000008000 >> { n95, n352, n438, n118, n355, n441 }; + assign o_4_ = 64'hffffffffffff7fff >> { n89, n447, n434, n348, n433, n432 }; + assign n436 = 64'h0000200000002008 >> { i_13_, i_11_, i_3_, i_9_, i_5_, i_12_ }; + assign n437 = 64'ha0e02060a0f12071 >> { n106, i_6_, i_0_, n436, i_1_, i_5_ }; + assign n438 = 64'h0000aa2a0000bf7f >> { n349, n100, i_8_, n437, i_7_, i_5_ }; + assign n439 = 64'ha8982010a898a898 >> { i_4_, i_3_, i_10_, n356, i_0_, i_2_ }; + assign n440 = 64'h8006000680040004 >> { n94, n129, i_6_, i_8_, i_5_, i_0_ }; + assign n441 = 64'h0000000200020002 >> { n440, n439, n125, n130, n358, n134 }; + assign n442 = 64'ha2aab3bfb3bfb3bf >> { i_6_, n140, n359, i_9_, n360, i_12_ }; + assign n443 = 32'd11250603 >> { n141, n140, n143, n142, i_7_ }; + assign n66 = 64'h0000000200010003 >> { i_11_, i_12_, i_1_, i_5_, i_10_, i_6_ }; + assign n444 = 64'h0000000000000008 >> { n138, n144, n145, n362, n442, n443 }; + assign n445 = 64'h4455000544550405 >> { n111, i_3_, n158, n181, n184, n185 }; + assign n446 = 64'h22222222f2222222 >> { n183, i_5_, n445, n374, n175, n177 }; + assign n447 = 64'haaaaaaaa2aaaaaaa >> { n188, n186, n446, n372, n376, i_0_ }; + assign n448 = 64'h0000ff080008ff08 >> { i_2_, i_7_, i_3_, i_10_, i_8_, n182 }; + assign n449 = 64'h51115111d9995111 >> { i_12_, n31, i_1_, n30, i_3_, i_6_ }; + assign n450 = 64'h0011011101110111 >> { n449, n448, i_11_, n241, n238, n237 }; + assign n451 = 64'h0100044002200880 >> { i_6_, i_7_, i_0_, i_5_, i_2_, i_1_ }; + assign n452 = 32'd4223384507 >> { n53, i_8_, n451, n400, n242 }; + assign n453 = 64'h9810fa50fc30fe70 >> { i_2_, i_1_, n295, n169, i_6_, i_7_ }; + assign n67 = 16'h0111 >> { i_1_, i_6_, i_2_, i_5_ }; + assign n454 = 64'hff7fff7fffffff7f >> { i_0_, n453, n296, n297, n299, n404 }; + assign n455 = 32'd65793 >> { n266, n454, n281, n407, n410 }; + assign n456 = 64'h0200020002020200 >> { i_12_, i_8_, i_3_, i_13_, i_9_, i_11_ }; + assign n457 = 64'hfffd77fdfdfd75fd >> { n319, n302, n416, i_10_, i_3_, n456 }; + assign n458 = 64'h0008000000080008 >> { n412, i_3_, n307, n415, n457, n420 }; + assign n459 = 64'h77f77fff7fff7fff >> { i_9_, n288, n293, i_3_, i_6_, i_5_ }; + assign n460 = 16'hd555 >> { n459, n328, n421, n250 }; + assign n461 = 64'h7fff7fff6eee7fff >> { i_6_, n277, i_10_, n323, i_7_, i_8_ }; + assign n462 = 64'h22ffa2ff20ffa0ff >> { i_8_, n97, n99, n461, n266, n422 }; + assign n463 = 64'h0000000000000080 >> { n329, n332, n424, n462, n426, n460 }; + assign n68 = 64'h0101010111010101 >> { i_12_, i_7_, n55, n65, i_2_, i_9_ }; + assign n69 = 32'd4160223061 >> { i_10_, i_9_, i_3_, n49, i_4_ }; + assign n70 = 8'h08 >> { i_9_, i_8_, i_4_ }; + assign n71 = 16'h8cae >> { i_1_, i_2_, i_6_, i_7_ }; + assign n72 = 64'h5500554055405540 >> { i_1_, i_6_, n74, n53, n73, i_5_ }; + assign n73 = 4'h1 >> { i_10_, i_7_ }; + assign n29 = 16'ha820 >> { i_9_, i_10_, i_5_, i_0_ }; + assign n74 = 32'd2 >> { i_10_, i_8_, i_2_, i_1_, i_4_ }; + assign n75 = 4'h2 >> { n76, n346 }; + assign n76 = 8'h45 >> { n78, n77, i_0_ }; + assign n77 = 64'h0000000200800082 >> { i_9_, i_10_, i_2_, i_6_, i_8_, i_4_ }; + assign n78 = 64'hfffffffdff7fff7d >> { i_9_, i_10_, i_3_, i_6_, i_7_, i_4_ }; + assign n79 = 64'h0000000000000008 >> { i_3_, i_9_, i_2_, i_0_, i_6_, i_4_ }; + assign n80 = 64'h0055045501550555 >> { i_11_, i_12_, n81, i_1_, i_6_, i_0_ }; + assign n81 = 32'd353703168 >> { i_2_, n83, n70, n82, n62 }; + assign n82 = 4'h8 >> { i_6_, i_7_ }; + assign n83 = 64'hfffffd75febafc30 >> { i_11_, i_12_, i_9_, i_10_, i_6_, i_7_ }; + assign n30 = 4'h2 >> { i_8_, i_10_ }; + assign n84 = 32'd538976800 >> { i_8_, n49, n85, i_10_, i_4_ }; + assign n85 = 64'h0001000100011111 >> { i_7_, i_1_, i_6_, i_2_, i_3_, i_0_ }; + assign n86 = 64'hf5f7fcfff7f7feff >> { i_4_, n88, n87, i_0_, i_1_, i_3_ }; + assign n87 = 16'h0002 >> { i_10_, i_13_, i_11_, i_12_ }; + assign n88 = 8'h08 >> { i_12_, i_10_, i_11_ }; + assign n89 = 32'd572662274 >> { n92, n91, n90, i_12_, n93 }; + assign n90 = 32'd3722436575 >> { i_8_, i_3_, i_7_, i_11_, i_9_ }; + assign n91 = 8'h08 >> { i_4_, i_5_, i_3_ }; + assign n92 = 8'h02 >> { i_7_, i_11_, i_10_ }; + assign n93 = 8'h08 >> { i_0_, i_1_, i_2_ }; + assign n31 = 4'h8 >> { i_8_, i_9_ }; + assign n94 = 4'h8 >> { i_10_, i_11_ }; + assign n95 = 64'h88888888888888a8 >> { i_4_, n98, i_5_, i_6_, n97, n96 }; + assign n96 = 4'h2 >> { i_11_, i_12_ }; + assign n97 = 64'h0000000000008000 >> { i_8_, i_5_, i_3_, i_6_, i_7_, i_10_ }; + assign n98 = 64'h00f7f7f7f7f7f7f7 >> { i_7_, i_10_, i_8_, i_0_, i_2_, i_3_ }; + assign n99 = 8'h02 >> { i_2_, i_1_, i_0_ }; + assign n100 = 64'haa20202020202020 >> { n31, n101, i_3_, n103, n102, n104 }; + assign n101 = 4'h1 >> { i_6_, i_7_ }; + assign n102 = 64'hf7f7f7f7f7f700f7 >> { i_7_, i_8_, i_9_, i_0_, i_2_, i_3_ }; + assign n103 = 4'h1 >> { i_6_, i_4_ }; + assign o_1_ = 64'h666566656665aaa9 >> { n30, n31, n34, n35, i_3_, n33 }; + assign n104 = 8'h08 >> { i_12_, i_5_, i_11_ }; + assign n105 = 4'h2 >> { i_4_, i_3_ }; + assign n106 = 64'hfdfffdfffdfffdfd >> { i_3_, i_12_, i_4_, i_9_, i_13_, i_11_ }; + assign n107 = 16'h0008 >> { i_0_, i_11_, i_2_, i_1_ }; + assign n108 = 8'h02 >> { i_13_, i_12_, i_11_ }; + assign n109 = 64'h0000000200020002 >> { i_1_, i_6_, i_3_, i_7_, i_10_, i_8_ }; + assign n110 = 8'h01 >> { i_10_, i_13_, i_11_ }; + assign n111 = 8'h01 >> { i_9_, i_13_, i_12_ }; + assign n112 = 4'h8 >> { n113, i_12_ }; + assign n113 = 4'h2 >> { i_13_, i_11_ }; + assign n33 = 4'h2 >> { i_13_, i_4_ }; + assign n114 = 64'hdddfdddf5555dddf >> { n117, i_2_, n116, n115, i_5_, i_0_ }; + assign n115 = 32'd32768 >> { i_8_, i_10_, i_3_, i_12_, i_11_ }; + assign n116 = 64'h0080008000000080 >> { i_12_, i_6_, i_7_, i_2_, i_10_, i_11_ }; + assign n117 = 32'd2012708863 >> { i_11_, i_12_, i_6_, i_10_, i_9_ }; + assign n118 = 32'd221196079 >> { n55, n124, n119, i_2_, n57 }; + assign n119 = 64'h80888088aaaa8088 >> { n120, n104, n122, n121, n96, n123 }; + assign n120 = 64'he8eaeceef8fafcff >> { i_1_, i_2_, i_3_, i_6_, i_7_, i_8_ }; + assign n121 = 16'h0080 >> { i_5_, i_6_, i_2_, i_8_ }; + assign n122 = 64'hdddddfffdfffdfff >> { i_8_, i_1_, i_3_, i_6_, i_5_, i_7_ }; + assign n123 = 4'h1 >> { i_0_, i_4_ }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act new file mode 100644 index 000000000..9bc344191 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act @@ -0,0 +1,655 @@ +i_0_ 0.517800 0.509800 +i_1_ 0.507400 0.499600 +i_2_ 0.508800 0.498400 +i_3_ 0.478800 0.507400 +i_4_ 0.491600 0.501200 +i_5_ 0.499600 0.504400 +i_6_ 0.494200 0.516000 +i_7_ 0.502600 0.504000 +i_8_ 0.510400 0.482400 +i_9_ 0.516800 0.499800 +i_10_ 0.493000 0.507200 +i_11_ 0.495600 0.504600 +i_12_ 0.502800 0.507600 +i_13_ 0.494600 0.500600 +i_14_ 0.504800 0.502800 +i_15_ 0.487600 0.495200 +i_16_ 0.504000 0.505200 +i_17_ 0.497400 0.512600 +i_18_ 0.502200 0.502200 +i_19_ 0.495200 0.500000 +i_20_ 0.491000 0.493200 +i_21_ 0.495600 0.501600 +i_22_ 0.495200 0.503200 +i_23_ 0.505400 0.491000 +i_24_ 0.518400 0.508200 +i_25_ 0.502400 0.500800 +i_26_ 0.494600 0.494600 +i_27_ 0.497000 0.486400 +i_28_ 0.500400 0.500600 +i_29_ 0.503400 0.500800 +i_30_ 0.489000 0.511800 +i_31_ 0.495400 0.503000 +i_32_ 0.481000 0.510800 +i_33_ 0.500800 0.501600 +i_34_ 0.498400 0.496200 +i_35_ 0.512400 0.485400 +i_36_ 0.493000 0.499400 +i_37_ 0.497000 0.501000 +i_38_ 0.505800 0.501600 +n45 0.000600 0.025535 +n46 0.007400 0.237365 +n47 0.016000 0.000507 +n48 0.006400 0.000028 +n49 0.123000 0.026212 +n50 0.500600 0.125514 +n51 0.122000 0.026567 +n52 0.239600 0.095360 +n53 0.016000 0.004553 +n54 0.246800 0.094778 +n55 0.134400 0.030214 +n56 0.244200 0.089975 +n57 0.995200 0.000000 +n58 0.000000 0.000000 +n59 0.997800 0.025852 +n60 0.128000 0.029538 +n61 0.058400 0.007102 +n62 0.123000 0.025653 +n63 0.962800 0.090969 +n64 0.252200 0.094921 +n65 0.067000 0.006902 +n66 0.000000 0.000000 +n67 0.008200 0.237452 +n68 0.015400 0.000489 +n69 0.016000 0.000444 +n70 0.241000 0.098188 +n71 0.124000 0.026377 +n72 0.261000 0.089271 +n73 0.125400 0.025966 +n74 0.260000 0.099153 +n75 0.234000 0.097721 +n76 0.242600 0.092149 +n77 0.063800 0.008474 +n78 0.969400 0.000965 +n79 0.003600 0.121985 +n80 0.000000 0.000464 +n81 0.000200 0.000006 +n82 0.125400 0.026450 +n83 0.243400 0.094495 +n84 0.125000 0.026618 +n85 0.997400 0.000000 +n86 0.000000 0.000015 +n87 0.117600 0.026356 +n88 0.128800 0.029209 +n89 0.244800 0.102081 +n90 0.015000 0.000426 +n91 0.002800 0.236969 +n92 0.123800 0.027757 +n93 0.030400 0.001734 +n94 0.057800 0.006902 +n95 0.000200 0.000000 +n96 0.113000 0.024458 +n97 0.122200 0.025590 +n98 0.015400 0.000472 +n99 0.128200 0.027168 +n100 0.016200 0.000474 +n101 0.001600 0.000010 +n102 0.250200 0.091886 +n103 0.031200 0.001879 +n104 0.184400 0.031650 +n105 0.129200 0.028722 +n106 0.000000 0.000000 +n107 0.012200 0.000510 +n108 0.117600 0.028205 +n109 0.995000 0.000000 +n110 0.000200 0.000050 +n111 0.999400 0.000474 +n112 0.122000 0.028443 +n113 0.061600 0.006943 +n114 0.014600 0.000454 +n115 0.015800 0.000444 +n116 0.008000 0.005167 +n117 0.126800 0.026916 +n118 0.997200 0.000068 +n119 0.019200 0.000431 +n120 0.186000 0.007014 +n121 0.014600 0.000464 +n122 0.232200 0.017175 +n123 0.018200 0.000443 +n124 0.995600 0.001698 +n125 0.015200 0.000482 +n126 0.063800 0.007433 +n127 0.118200 0.025867 +n128 0.033400 0.002072 +n129 0.015800 0.000501 +n130 0.000000 0.000000 +n131 0.000000 0.000000 +n132 0.007000 0.000111 +n133 0.059000 0.007017 +n134 0.991000 0.000001 +n135 0.014200 0.000485 +n136 0.129000 0.028071 +n137 0.033400 0.002054 +n138 0.991800 0.000063 +n139 0.996400 0.000000 +n140 0.003000 0.000025 +n141 0.242000 0.089340 +n142 0.014600 0.000529 +n143 0.996800 0.000429 +n144 0.115000 0.025850 +n145 0.129200 0.026603 +n146 0.123000 0.027116 +n147 0.016600 0.000492 +n148 0.031000 0.002016 +n149 0.054800 0.006993 +n150 0.002400 0.000009 +n151 0.132600 0.029850 +n152 0.032200 0.001795 +n153 0.014400 0.000444 +n154 0.982200 0.003292 +n155 0.111400 0.025404 +n156 0.011400 0.000444 +n157 0.006600 0.000057 +n158 0.010400 0.000358 +n159 0.134000 0.010573 +n160 0.122200 0.028002 +n161 0.077000 0.007987 +n162 0.277200 0.152811 +n163 0.129600 0.028505 +n164 0.257400 0.100855 +n165 0.032800 0.001762 +n166 0.996400 0.000000 +n167 0.003600 0.000015 +n168 0.005200 0.000078 +n169 0.251400 0.091190 +n170 0.118400 0.025466 +n171 0.116600 0.024777 +n172 0.000000 0.000000 +n173 0.129400 0.029266 +n174 0.999000 0.000092 +n175 0.130000 0.029735 +n176 0.082200 0.007550 +n177 0.253800 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0.044400 0.002077 +n635 0.039800 0.000019 +n636 0.898800 0.162778 +n637 0.000200 0.000015 +n638 0.997600 0.000000 +n639 0.989400 0.228063 +n640 0.000000 0.000001 +n641 0.276000 0.094945 +n642 0.013800 0.185645 +n643 0.000400 0.138614 +n644 0.502200 0.150843 +n645 0.999600 0.000000 +n646 0.001800 0.119488 +n647 0.005600 0.000019 +n648 0.991600 0.000018 +n649 0.984800 0.000000 +n650 0.048600 0.007295 +n651 0.007600 0.004766 +n652 0.003400 0.280438 +n653 0.999600 0.130579 +n654 0.998600 0.000000 +n655 0.999000 0.000002 +n656 0.381600 0.038059 +n657 0.000200 0.000000 +n658 0.011400 0.000427 +n659 0.001000 0.000013 +n660 0.998800 0.000000 diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif new file mode 100644 index 000000000..7ba78bd10 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif @@ -0,0 +1,1667 @@ +# Benchmark "apex2" written by ABC on Tue Mar 12 09:34:21 2019 +.model apex2 +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ + i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ \ + i_25_ i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ \ + i_37_ i_38_ +.outputs o_0_ o_1_ o_2_ +.names n48 n46 i_10_ n52 i_30_ n45 +110-- 1 +1--10 1 +.names n47 i_9_ n46 +10 1 +.names i_8_ i_7_ i_2_ i_6_ i_5_ i_4_ n47 +000000 1 +.names i_37_ n51 n49 n50 n48 +1110 1 +.names i_17_ i_16_ i_23_ n49 +000 1 +.names i_34_ i_24_ i_35_ n50 +0-0 1 +11- 1 +.names i_27_ i_29_ i_28_ n51 +000 1 +.names i_8_ i_7_ n52 +00 1 +.names n54 n55 i_24_ n53 +110 1 +.names i_29_ i_28_ n54 +00 1 +.names i_31_ i_30_ i_32_ n55 +000 1 +.names i_37_ i_35_ n56 +10 1 +.names n58 n66 n72 n74 n73 i_7_ n57 +1----- 0 +-1---- 0 +--1110 0 +.names i_17_ i_16_ n63 n59 n58 +0000 1 +.names n47 n62 n60 n61 n59 +11-- 0 +1-11 0 +.names i_3_ i_2_ i_4_ n60 +100 1 +.names i_18_ i_9_ i_6_ i_5_ n61 +0000 1 +.names i_19_ i_11_ i_9_ n62 +000 1 +.names n64 n65 i_34_ n54 i_24_ n63 +11--- 0 +1-110 0 +.names i_23_ i_27_ n64 +00 1 +.names i_35_ i_34_ i_29_ i_28_ n65 +1000 1 +.names n71 n67 n69 n70 n66 +1110 1 +.names n68 i_9_ n67 +10 1 +.names i_8_ i_7_ i_6_ i_5_ i_0_ i_4_ n68 +000000 1 +.names i_29_ i_26_ i_24_ i_23_ i_27_ i_28_ n69 +100000 1 +.names i_10_ i_13_ n70 +10 1 +.names i_20_ i_17_ i_16_ n71 +000 1 +.names i_35_ i_34_ n72 +10 1 +.names i_30_ i_29_ i_28_ n73 +000 1 +.names i_31_ i_32_ n74 +00 1 +.names i_24_ i_23_ n75 +00 1 +.names i_34_ i_37_ n76 +11 1 +.names i_7_ i_31_ i_30_ i_32_ n77 +0000 1 +.names n595 n180 n166 n138 n130 n79 n78 +111100 1 +.names i_32_ i_37_ n109 n80 n85 n79 +01-1- 1 +01--0 1 +0-0-- 1 +.names n81 n84 n83 i_11_ n80 +1110 1 +.names n82 n69 i_19_ i_20_ i_17_ n81 +11000 1 +.names i_5_ i_0_ i_4_ n82 +000 1 +.names i_14_ i_16_ n83 +00 1 +.names i_7_ i_9_ i_6_ n84 +000 1 +.names n95 n106 n101 i_35_ n86 n91 n85 +0001-- 1 +000-00 1 +.names n90 n87 n89 n88 n70 n86 +11110 1 +.names i_17_ i_14_ i_16_ n87 +000 1 +.names i_2_ i_5_ i_4_ n88 +000 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n653 +0-1--- 0 +0--110 0 +-1---- 0 +.names n278 n653 n287 n284 n56 n76 n654 +0110-- 1 +01-00- 1 +0-1--0 1 +0---00 1 +.names n364 n268 i_29_ i_28_ i_32_ n655 +11000 0 +.names i_34_ i_33_ i_32_ i_8_ i_25_ i_26_ n656 +01---- 0 +0----1 0 +-1--1- 0 +--11-- 0 +.names n363 n89 n655 n365 n618 n656 n657 +11-1-- 1 +11--11 1 +1-0--- 1 +.names i_38_ i_35_ i_30_ i_24_ i_29_ i_28_ n658 +100000 1 +.names n406 n658 n402 i_25_ i_34_ i_33_ n659 +1110-- 1 +111--0 1 +11-01- 1 +11--10 1 +.names n620 n394 n409 n400 n659 n509 n660 +11000- 1 +1100-0 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v new file mode 100644 index 000000000..b1e082d06 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v @@ -0,0 +1,1275 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module apex2(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, o_0_, o_1_, o_2_); + input i_0_; + input i_10_; + input i_11_; + input i_12_; + input i_13_; + input i_14_; + input i_15_; + input i_16_; + input i_17_; + input i_18_; + input i_19_; + input i_1_; + input i_20_; + input i_21_; + input i_22_; + input i_23_; + input i_24_; + input i_25_; + input i_26_; + input i_27_; + input i_28_; + input i_29_; + input i_2_; + input i_30_; + input i_31_; + input i_32_; + input i_33_; + input i_34_; + input i_35_; + input i_36_; + input i_37_; + input i_38_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + input i_9_; + wire n100; + wire n101; + wire n102; + wire n103; + wire n104; + wire n105; + wire n106; + wire n107; + wire n108; + wire n109; + wire n110; + wire n111; + wire n112; + wire n113; + wire n114; + wire n115; + wire n116; + wire n117; + wire n118; + wire n119; + wire n120; + wire n121; + wire n122; + wire n123; + wire n124; + wire n125; + wire n126; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n377; + wire n378; + wire n379; + wire n380; + wire n381; + wire n382; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n390; + wire n391; + wire n392; + wire n393; + wire n394; + wire n395; + wire n396; + wire n397; + wire n398; + wire n399; + wire n400; + wire n401; + wire n402; + wire n403; + wire n404; + wire n405; + wire n406; + wire n407; + wire n408; + wire n409; + wire n410; + wire n411; + wire n412; + wire n413; + wire n414; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n427; + wire n428; + wire n429; + wire n430; + wire n431; + wire n432; + wire n433; + wire n434; + wire n435; + wire n436; + wire n437; + wire n438; + wire n439; + wire n440; + wire n441; + wire n442; + wire n443; + wire n444; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n45; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n455; + wire n456; + wire n457; + wire n458; + wire n459; + wire n46; + wire n460; + wire n461; + wire n462; + wire n463; + wire n464; + wire n465; + wire n466; + wire n467; + wire n468; + wire n469; + wire n47; + wire n470; + wire n471; + wire n472; + wire n473; + wire n474; + wire n475; + wire n476; + wire n477; + wire n478; + wire n479; + wire n48; + wire n480; + wire n481; + wire n482; + wire n483; + wire n484; + wire n485; + wire n486; + wire n487; + wire n488; + wire n489; + wire n49; + wire n490; + wire n491; + wire n492; + wire n493; + wire n495; + wire n496; + wire n497; + wire n498; + wire n499; + wire n50; + wire n500; + wire n501; + wire n502; + wire n503; + wire n504; + wire n505; + wire n506; + wire n507; + wire n508; + wire n509; + wire n51; + wire n510; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n52; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n53; + wire n530; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n54; + wire n540; + wire n541; + wire n542; + wire n543; + wire n544; + wire n545; + wire n546; + wire n547; + wire n548; + wire n549; + wire n55; + wire n550; + wire n551; + wire n552; + wire n553; + wire n554; + wire n555; + wire n556; + wire n557; + wire n558; + wire n559; + wire n56; + wire n560; + wire n561; + wire n562; + wire n563; + wire n564; + wire n565; + wire n566; + wire n567; + wire n568; + wire n569; + wire n57; + wire n570; + wire n571; + wire n572; + wire n573; + wire n574; + wire n575; + wire n576; + wire n577; + wire n578; + wire n579; + wire n58; + wire n580; + wire n581; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n588; + wire n589; + wire n59; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n598; + wire n599; + wire n60; + wire n600; + wire n601; + wire n602; + wire n603; + wire n604; + wire n605; + wire n606; + wire n607; + wire n608; + wire n609; + wire n61; + wire n610; + wire n612; + wire n613; + wire n614; + wire n615; + wire n616; + wire n617; + wire n618; + wire n619; + wire n62; + wire n620; + wire n621; + wire n622; + wire n623; + wire n624; + wire n625; + wire n626; + wire n627; + wire n628; + wire n629; + wire n63; + wire n630; + wire n631; + wire n632; + wire n633; + wire n634; + wire n635; + wire n636; + wire n637; + wire n638; + wire n639; + wire n64; + wire n640; + wire n641; + wire n642; + wire n643; + wire n644; + wire n645; + wire n646; + wire n647; + wire n648; + wire n649; + wire n65; + wire n650; + wire n651; + wire n652; + wire n653; + wire n654; + wire n655; + wire n656; + wire n657; + wire n658; + wire n659; + wire n66; + wire n660; + wire n67; + wire n68; + wire n69; + wire n70; + wire n71; + wire n72; + wire n73; + wire n74; + wire n75; + wire n76; + wire n77; + wire n78; + wire n79; + wire n80; + wire n81; + wire n82; + wire n83; + wire n84; + wire n85; + wire n86; + wire n87; + wire n88; + wire n89; + wire n90; + wire n91; + wire n92; + wire n93; + wire n94; + wire n95; + wire n96; + wire n97; + wire n98; + wire n99; + output o_0_; + output o_1_; + output o_2_; + assign n45 = 32'd134785544 >> { i_30_, n52, i_10_, n46, n48 }; + assign n54 = 4'h1 >> { i_28_, i_29_ }; + assign n144 = 8'h01 >> { i_23_, i_16_, i_13_ }; + assign n145 = 8'h01 >> { i_23_, i_17_, i_19_ }; + assign n146 = 8'h01 >> { i_16_, i_13_, i_11_ }; + assign n147 = 64'h0000000000000001 >> { i_4_, i_12_, i_5_, i_6_, i_2_, i_7_ }; + assign n148 = 32'd1 >> { i_4_, i_1_, i_5_, i_6_, i_2_ }; + assign n149 = 16'h0001 >> { i_23_, i_16_, i_17_, i_13_ }; + assign n150 = 32'd2860548224 >> { n152, n151, n119, n153, i_34_ }; + assign n151 = 8'h02 >> { i_32_, i_31_, i_33_ }; + assign n152 = 32'd8 >> { i_28_, i_23_, i_24_, i_25_, i_20_ }; + assign n153 = 64'h0000000000000002 >> { i_16_, i_13_, i_33_, i_35_, i_8_, i_37_ }; + assign n55 = 8'h01 >> { i_32_, i_30_, i_31_ }; + assign n154 = 16'h777f >> { i_34_, n117, n51, n56 }; + assign n155 = 8'h01 >> { i_23_, i_24_, i_16_ }; + assign n156 = 64'h0000000000000001 >> { i_23_, i_24_, i_16_, i_14_, i_17_, i_8_ }; + assign n157 = 64'ha888888888888888 >> { n162, i_31_, n72, n126, n158, i_7_ }; + assign n158 = 64'h20202020aa202020 >> { n50, n160, i_20_, n161, i_24_, n159 }; + assign n159 = 64'h0001010100111111 >> { i_12_, i_14_, i_13_, i_17_, i_23_, i_16_ }; + assign n160 = 8'h02 >> { i_28_, i_27_, i_31_ }; + assign n161 = 64'h0002000202020002 >> { i_29_, i_34_, i_26_, i_28_, i_27_, i_31_ }; + assign n162 = 32'd1381653 >> { i_13_, i_14_, i_12_, i_17_, i_16_ }; + assign n163 = 4'h8 >> { n164, i_37_ }; + assign n56 = 4'h2 >> { i_35_, i_37_ }; + assign n164 = 4'h1 >> { i_32_, i_33_ }; + assign n165 = 32'd2 >> { i_28_, i_29_, i_27_, i_24_, i_34_ }; + assign n166 = 64'h1111111101111111 >> { n154, n178, n75, n179, n172, n167 }; + assign n167 = 32'd2827520136 >> { n171, n73, n151, n168, i_34_ }; + assign n168 = 32'd2155907200 >> { i_12_, n169, n104, n99, n170 }; + assign n169 = 4'h1 >> { i_16_, i_13_ }; + assign n170 = 8'h02 >> { i_23_, i_24_, i_22_ }; + assign n171 = 8'h02 >> { i_23_, i_24_, i_25_ }; + assign n172 = 16'h0008 >> { n174, i_27_, n177, n173 }; + assign n173 = 4'h8 >> { n72, i_37_ }; + assign n57 = 64'h1111111101111111 >> { i_7_, n73, n74, n72, n66, n58 }; + assign n174 = 64'h007f7f7f7f7f7f7f >> { n120, n121, n175, n52, n148, n176 }; + assign n175 = 8'h01 >> { i_32_, i_28_, i_29_ }; + assign n176 = 64'h0001000100010101 >> { i_13_, i_33_, i_14_, i_28_, i_29_, i_16_ }; + assign n177 = 4'h1 >> { i_23_, i_17_ }; + assign n178 = 4'h2 >> { i_17_, n120 }; + assign n179 = 64'h0000000000000001 >> { i_4_, i_5_, i_6_, i_9_, i_2_, i_8_ }; + assign n180 = 64'h0101010001010101 >> { i_25_, n188, n181, n184, n189, n185 }; + assign n181 = 8'h57 >> { n94, n72, n182 }; + assign n182 = 8'h08 >> { i_32_, n183, i_33_ }; + assign n183 = 8'h01 >> { i_28_, i_30_, i_31_ }; + assign n58 = 16'h0001 >> { n59, n63, i_16_, i_17_ }; + assign n184 = 16'h0080 >> { i_14_, n48, n46, i_13_ }; + assign n185 = 64'h0200020002020200 >> { i_33_, n169, n83, n186, i_20_, n56 }; + assign n186 = 64'hfefefefffefffeff >> { n495, n69, n187, i_0_, i_12_, i_8_ }; + assign n187 = 64'h0000000000000001 >> { i_28_, i_27_, i_23_, i_24_, i_30_, i_26_ }; + assign n188 = 8'h15 >> { n127, n73, i_20_ }; + assign n189 = 8'h80 >> { n75, n190, i_21_ }; + assign n190 = 64'h0000000000000008 >> { i_32_, i_28_, i_30_, i_31_, i_29_, i_34_ }; + assign n191 = 32'd1162151237 >> { i_35_, n194, n193, n59, n192 }; + assign n192 = 8'h80 >> { n169, n52, n137 }; + assign n193 = 8'h01 >> { i_16_, i_17_, i_13_ }; + assign n59 = 16'h5777 >> { n61, n60, n62, n47 }; + assign n194 = 64'h0000000000000001 >> { i_4_, i_1_, i_5_, i_6_, i_2_, i_8_ }; + assign n195 = 16'h0111 >> { n127, n201, n196, n199 }; + assign n196 = 64'ha888a888aaaaa888 >> { n198, n69, n197, n193, n190, n170 }; + assign n197 = 16'h0008 >> { i_28_, i_27_, i_29_, i_34_ }; + assign n198 = 32'd4277858026 >> { i_14_, i_12_, i_13_, i_17_, i_16_ }; + assign n199 = 32'd8 >> { n200, i_20_, i_21_, i_2_, n69 }; + assign n200 = 16'hfeee >> { i_13_, i_14_, i_12_, i_16_ }; + assign n201 = 4'h8 >> { n202, i_22_ }; + assign n202 = 32'd2 >> { i_32_, i_28_, i_30_, i_31_, i_29_ }; + assign n203 = 64'h8a888a888a880a00 >> { i_21_, i_22_, n54, n205, n204, n55 }; + assign n60 = 8'h02 >> { i_4_, i_2_, i_3_ }; + assign n204 = 16'h0008 >> { i_28_, i_34_, i_35_, i_29_ }; + assign n205 = 64'hf7fff7fff5fdf7ff >> { i_7_, i_37_, i_25_, i_34_, i_33_, i_35_ }; + assign n206 = 32'd128 >> { i_28_, i_27_, i_33_, i_25_, i_34_ }; + assign n207 = 8'h80 >> { n75, n197, i_21_ }; + assign n208 = 8'h01 >> { i_28_, i_27_, i_23_ }; + assign n209 = 4'h8 >> { i_33_, i_25_ }; + assign n210 = 64'h0777077707770fff >> { i_21_, i_22_, n211, n171, n204, n64 }; + assign n211 = 64'h0002000202020002 >> { i_29_, i_34_, i_26_, i_28_, i_27_, i_33_ }; + assign n212 = 64'h0000000000008000 >> { i_20_, i_18_, n216, n213, n215, n226 }; + assign n213 = 4'h2 >> { i_17_, n69 }; + assign n61 = 16'h0001 >> { i_5_, i_6_, i_9_, i_18_ }; + assign n214 = 8'h01 >> { i_16_, i_13_, i_9_ }; + assign n215 = 32'd2 >> { i_5_, i_6_, i_35_, i_8_, i_37_ }; + assign n216 = 8'h02 >> { i_4_, i_0_, i_3_ }; + assign n217 = 16'h0080 >> { i_27_, n76, n218, n75 }; + assign n218 = 8'h01 >> { i_28_, i_29_, i_33_ }; + assign n219 = 64'ha8a0a8a0a8a8a8a0 >> { n224, n226, n228, n221, i_37_, n220 }; + assign n220 = 8'h08 >> { i_20_, i_29_, n75 }; + assign n221 = 32'd2155915904 >> { n222, n215, n193, n223, n113 }; + assign n222 = 32'd4278124270 >> { i_13_, i_33_, i_14_, i_16_, i_17_ }; + assign n223 = 64'h0000000000000002 >> { i_32_, i_33_, i_5_, i_6_, i_7_, i_37_ }; + assign n62 = 8'h01 >> { i_9_, i_11_, i_19_ }; + assign n224 = 16'h7757 >> { i_18_, n107, n225, n68 }; + assign n225 = 4'h1 >> { i_11_, i_19_ }; + assign n226 = 16'h0222 >> { i_33_, i_14_, i_9_, n227 }; + assign n227 = 16'h0111 >> { i_13_, i_14_, i_17_, i_16_ }; + assign n228 = 16'h2202 >> { n83, i_33_, n200, n68 }; + assign n229 = 32'd16843008 >> { n231, n230, i_29_, i_30_, i_33_ }; + assign n230 = 64'h0000000000000001 >> { i_23_, i_24_, i_12_, i_16_, i_13_, i_8_ }; + assign n231 = 64'h0000000000000001 >> { i_23_, i_24_, i_16_, i_17_, i_13_, i_8_ }; + assign n232 = 8'h80 >> { n75, n169, n137 }; + assign n233 = 64'h8888800080008000 >> { n60, n61, n88, n133, n75, n193 }; + assign n63 = 32'd2004309879 >> { i_24_, n54, i_34_, n65, n64 }; + assign n234 = 16'h0080 >> { i_12_, n170, i_29_, n83 }; + assign n235 = 64'hd0d0f0d0f0d0f0d0 >> { n236, n241, n269, n267, n261, n245 }; + assign n236 = 8'h01 >> { n237, n238, n239 }; + assign n237 = 16'h0008 >> { i_23_, i_8_, n83, n137 }; + assign n238 = 16'h0080 >> { i_11_, n179, n145, n83 }; + assign n239 = 16'h0080 >> { i_23_, n141, n240, n87 }; + assign n240 = 64'h0000000000000002 >> { i_4_, i_5_, i_6_, i_2_, i_8_, i_3_ }; + assign n241 = 64'hbabababa00bababa >> { i_32_, n148, n242, n244, n243, i_33_ }; + assign n242 = 4'h2 >> { i_23_, n87 }; + assign n243 = 8'h08 >> { i_8_, n144, n137 }; + assign n46 = 4'h2 >> { i_9_, n47 }; + assign n64 = 4'h1 >> { i_27_, i_23_ }; + assign n244 = 64'h007f7f7f7f7f7f7f >> { n145, n179, n146, n141, n149, n240 }; + assign n245 = 32'd33694210 >> { n249, n246, n252, n257, n254 }; + assign n246 = 32'd1431655701 >> { n247, i_8_, n112, n113, n248 }; + assign n247 = 16'heeea >> { i_13_, i_33_, i_14_, i_16_ }; + assign n248 = 16'h0222 >> { i_13_, i_14_, i_16_, i_2_ }; + assign n249 = 16'h0080 >> { n251, n82, n250, n56 }; + assign n250 = 8'h01 >> { i_6_, i_9_, i_8_ }; + assign n251 = 32'd4289658542 >> { i_33_, i_14_, i_13_, i_10_, i_16_ }; + assign n252 = 8'h08 >> { i_20_, n253, n177 }; + assign n253 = 4'h2 >> { i_28_, i_29_ }; + assign n65 = 16'h0002 >> { i_28_, i_29_, i_34_, i_35_ }; + assign n254 = 32'd125269879 >> { n255, n149, n148, n256, n162 }; + assign n255 = 64'h0000000000000002 >> { i_32_, i_28_, i_29_, i_33_, i_35_, i_37_ }; + assign n256 = 32'd8 >> { i_28_, i_22_, i_23_, i_29_, i_21_ }; + assign n257 = 64'h0000000000008000 >> { i_0_, i_20_, n260, n259, n258, n162 }; + assign n258 = 4'h1 >> { i_23_, i_16_ }; + assign n259 = 32'd33686050 >> { i_13_, i_33_, i_14_, i_35_, i_37_ }; + assign n260 = 8'h01 >> { i_32_, i_28_, i_30_ }; + assign n261 = 64'ha888a888a888a000 >> { n266, n265, n262, n264, n82, n263 }; + assign n262 = 4'h2 >> { n222, n56 }; + assign n263 = 4'h2 >> { i_32_, n253 }; + assign n66 = 16'h0080 >> { n70, n69, n67, n71 }; + assign n264 = 64'h1111100010001000 >> { n61, n216, n82, n133, i_23_, i_20_ }; + assign n265 = 32'd8 >> { i_12_, i_6_, i_20_, n259, n258 }; + assign n266 = 32'd128 >> { n251, i_20_, n177, i_37_, n84 }; + assign n267 = 4'h2 >> { i_27_, n268 }; + assign n268 = 4'h1 >> { i_24_, i_26_ }; + assign n269 = 4'h8 >> { n56, n54 }; + assign n270 = 8'h08 >> { i_30_, n271, i_31_ }; + assign n271 = 16'h0111 >> { i_17_, i_12_, i_16_, i_13_ }; + assign n272 = 32'd2155905024 >> { n233, n232, n56, n164, i_34_ }; + assign n273 = 32'd2282227720 >> { n140, n149, n143, n164, n173 }; + assign n67 = 4'h2 >> { i_9_, n68 }; + assign n274 = 32'd128 >> { i_33_, i_10_, n149, n46, n173 }; + assign n275 = 64'h4444444454444444 >> { i_33_, i_34_, n230, n56, n276, i_30_ }; + assign n276 = 64'h0000000000008000 >> { i_23_, i_33_, n271, n52, n72, i_37_ }; + assign n277 = 4'h8 >> { n88, n114 }; + assign n278 = 64'haaa8a8a8a8a8a8a8 >> { n84, n146, n81, n280, n279, n163 }; + assign n279 = 64'h0000000000000080 >> { i_17_, i_20_, i_18_, n107, n69, n214 }; + assign n280 = 64'h0808080008000800 >> { n99, n100, n98, i_20_, n169, n96 }; + assign n281 = 32'd32768 >> { n70, n88, n89, n87, n282 }; + assign n282 = 64'h0000000000000001 >> { i_32_, i_28_, i_29_, i_27_, i_23_, i_24_ }; + assign n283 = 8'h80 >> { n227, n125, n282 }; + assign n68 = 64'h0000000000000001 >> { i_4_, i_0_, i_5_, i_6_, i_7_, i_8_ }; + assign n284 = 32'd128 >> { i_31_, i_7_, n73, n75, n164 }; + assign n285 = 64'h0000000000008000 >> { i_23_, i_24_, n286, n271, n102, n52 }; + assign n286 = 8'h01 >> { i_29_, i_30_, i_33_ }; + assign n287 = 64'h1111001101010001 >> { n241, n290, n92, n165, n288, n291 }; + assign n288 = 32'd128 >> { i_20_, i_19_, n82, n213, n289 }; + assign n289 = 8'h02 >> { n247, i_11_, n250 }; + assign n290 = 64'hfffffff7fffdfff5 >> { i_26_, i_23_, i_24_, i_28_, i_34_, n164 }; + assign n291 = 64'h0000000080000000 >> { i_27_, n87, n54, n194, n75, i_34_ }; + assign n292 = 64'hefefefefefefaaef >> { i_32_, i_35_, n93, n67, i_10_, i_33_ }; + assign n293 = 16'h0008 >> { i_0_, i_8_, n187, n259 }; + assign n69 = 64'h0000000000000002 >> { i_28_, i_27_, i_23_, i_24_, i_26_, i_29_ }; + assign n294 = 16'ha888 >> { n352, n242, n296, n295 }; + assign n295 = 16'h5444 >> { n51, n72, n165, i_32_ }; + assign n296 = 8'h08 >> { i_23_, n147, n83 }; + assign n297 = 64'h7777777777770777 >> { n63, i_12_, n83, n47, n298, n122 }; + assign n298 = 64'h0000000000000080 >> { i_0_, i_30_, i_20_, n117, n75, n52 }; + assign n299 = 64'h0000000000000001 >> { i_32_, i_28_, i_29_, i_27_, i_23_, i_17_ }; + assign n300 = 64'h0202020002000200 >> { n277, n282, n301, i_33_, i_35_, i_34_ }; + assign n301 = 16'h0080 >> { i_10_, n179, n119, n169 }; + assign n302 = 32'd2860548224 >> { n315, n316, n309, n314, n303 }; + assign n303 = 32'd134776840 >> { n308, i_18_, n304, i_9_, n307 }; + assign n70 = 4'h2 >> { i_13_, i_10_ }; + assign n304 = 4'h1 >> { n305, n306 }; + assign n305 = 64'h0000000000000001 >> { i_3_, i_4_, i_1_, i_5_, i_6_, i_2_ }; + assign n306 = 64'h0000000000000001 >> { i_3_, i_4_, i_12_, i_5_, i_6_, i_2_ }; + assign n307 = 4'h1 >> { n225, i_13_ }; + assign n308 = 64'hfffffffefffefffe >> { i_1_, i_12_, i_4_, i_5_, i_6_, i_2_ }; + assign n309 = 32'd1431655761 >> { n310, n312, n313, n311, i_32_ }; + assign n310 = 32'd1 >> { i_28_, i_22_, i_24_, i_25_, i_26_ }; + assign n311 = 64'hfffefffefffffffe >> { i_34_, i_26_, i_24_, i_33_, i_28_, i_29_ }; + assign n312 = 32'd2 >> { i_28_, i_29_, i_24_, i_25_, i_34_ }; + assign n313 = 32'd1 >> { i_28_, i_29_, i_24_, i_25_, i_26_ }; + assign n71 = 8'h01 >> { i_16_, i_17_, i_20_ }; + assign n314 = 4'h2 >> { i_35_, i_38_ }; + assign n315 = 4'h1 >> { i_22_, i_24_ }; + assign n316 = 64'h0000000000000002 >> { i_32_, i_28_, i_33_, i_35_, i_26_, i_38_ }; + assign n317 = 64'h2020202022202020 >> { i_30_, n322, n320, n318, i_33_, n314 }; + assign n318 = 16'h0080 >> { n308, n175, n319, n268 }; + assign n319 = 4'h2 >> { i_10_, i_9_ }; + assign n320 = 8'h08 >> { i_10_, n321, n315 }; + assign n321 = 16'h2022 >> { i_2_, i_12_, i_8_, i_9_ }; + assign n322 = 4'h1 >> { i_28_, i_26_ }; + assign n323 = 32'd1430274112 >> { n325, n324, n183, n326, i_8_ }; + assign n72 = 4'h2 >> { i_34_, i_35_ }; + assign n324 = 8'h02 >> { i_31_, i_35_, i_38_ }; + assign n325 = 64'h0000000000000001 >> { i_28_, i_22_, i_24_, i_30_, i_25_, i_26_ }; + assign n326 = 64'h0000000000000002 >> { i_22_, i_24_, i_33_, i_35_, i_26_, i_38_ }; + assign n327 = 64'h5454545454545455 >> { n333, n336, n55, n332, n328, i_28_ }; + assign n328 = 16'h88a8 >> { n308, n329, n331, n330 }; + assign n329 = 4'h1 >> { i_32_, i_7_ }; + assign n330 = 32'd2 >> { i_22_, i_24_, i_33_, i_26_, i_38_ }; + assign n331 = 16'h0001 >> { i_30_, i_2_, i_7_, i_8_ }; + assign n332 = 64'haa00aa08aa08aa08 >> { n334, n333, n335, n55, n72, i_22_ }; + assign n333 = 16'h0777 >> { i_14_, i_13_, i_12_, i_17_ }; + assign n73 = 8'h01 >> { i_28_, i_29_, i_30_ }; + assign n334 = 8'h01 >> { i_27_, i_23_, i_16_ }; + assign n335 = 32'd143130752 >> { i_35_, i_24_, i_34_, i_14_, i_33_ }; + assign n336 = 32'd4008635918 >> { i_29_, i_34_, i_35_, i_26_, i_24_ }; + assign n337 = 64'h80808080aa808080 >> { i_29_, n72, n182, i_33_, n338, i_14_ }; + assign n338 = 8'h01 >> { i_28_, i_24_, i_26_ }; + assign n339 = 64'h5555555555551555 >> { i_22_, i_21_, n162, n69, i_20_, n340 }; + assign n340 = 32'd2147483648 >> { n64, n65, n271, i_14_, i_33_ }; + assign n341 = 64'h0001010100111111 >> { n267, n348, n349, n342, n347, n343 }; + assign n342 = 4'h8 >> { n162, n256 }; + assign n343 = 8'h02 >> { n344, n345, n346 }; + assign n47 = 64'h0000000000000001 >> { i_4_, i_5_, i_6_, i_2_, i_7_, i_8_ }; + assign n74 = 4'h1 >> { i_32_, i_31_ }; + assign n344 = 64'hfffffffdfffdfffd >> { i_25_, i_33_, i_28_, i_30_, i_26_, i_38_ }; + assign n345 = 32'd1970796023 >> { i_18_, i_19_, i_3_, i_11_, i_10_ }; + assign n346 = 64'h0000000000000002 >> { i_22_, i_24_, i_13_, i_7_, i_8_, i_12_ }; + assign n347 = 16'h0080 >> { i_26_, n315, i_27_, n253 }; + assign n348 = 32'd1430274112 >> { i_14_, i_13_, i_12_, i_17_, i_24_ }; + assign n349 = 32'd33686016 >> { i_30_, i_32_, i_29_, i_28_, i_34_ }; + assign n350 = 64'h1111111111111101 >> { i_29_, i_24_, n351, n362, n361, n617 }; + assign n351 = 16'h1115 >> { n353, n352, i_38_, n354 }; + assign n352 = 32'd2860548224 >> { n61, n60, n88, n133, n329 }; + assign n353 = 8'h02 >> { n70, i_9_, n47 }; + assign n75 = 4'h1 >> { i_23_, i_24_ }; + assign n354 = 32'd2860548224 >> { n141, n240, n225, n179, n324 }; + assign n355 = 64'h1111133313331333 >> { n61, n60, n133, n88, n357, n356 }; + assign n356 = 8'h01 >> { i_32_, i_29_, i_31_ }; + assign n357 = 16'h0001 >> { i_29_, i_30_, i_31_, i_8_ }; + assign n358 = 16'h0008 >> { i_33_, i_35_, i_34_, i_38_ }; + assign n359 = 64'h0000000000000080 >> { n308, n360, i_32_, n319, n314, i_34_ }; + assign n360 = 16'hfeee >> { i_25_, i_33_, i_28_, i_29_ }; + assign n361 = 64'h0000000000000080 >> { i_29_, i_24_, i_30_, n362, n52, i_38_ }; + assign n362 = 8'h01 >> { i_28_, i_25_, i_26_ }; + assign n363 = 4'h2 >> { n70, n88 }; + assign n76 = 4'h8 >> { i_37_, i_34_ }; + assign n364 = 32'd2 >> { i_33_, i_6_, i_9_, i_7_, i_38_ }; + assign n365 = 32'd1430274112 >> { n366, n367, n315, n316, i_31_ }; + assign n366 = 8'h02 >> { i_32_, i_35_, i_38_ }; + assign n367 = 64'h0000000100010001 >> { i_22_, i_29_, i_28_, i_24_, i_25_, i_26_ }; + assign n368 = 8'h01 >> { i_28_, i_29_, i_31_ }; + assign n369 = 64'h0155015500550155 >> { i_7_, n371, n378, n323, n370, n372 }; + assign n370 = 8'h80 >> { n329, n325, i_38_ }; + assign n371 = 4'h8 >> { n260, n330 }; + assign n372 = 32'd2290122880 >> { n376, n373, n375, n374, n377 }; + assign n373 = 4'h1 >> { i_24_, i_25_ }; + assign n77 = 16'h0001 >> { i_32_, i_30_, i_31_, i_7_ }; + assign n374 = 16'h0001 >> { i_28_, i_22_, i_24_, i_26_ }; + assign n375 = 16'h0002 >> { i_30_, i_33_, i_35_, i_38_ }; + assign n376 = 32'd2 >> { i_28_, i_30_, i_35_, i_26_, i_38_ }; + assign n377 = 8'h02 >> { i_3_, i_8_, i_9_ }; + assign n378 = 4'h2 >> { i_3_, i_10_ }; + assign n379 = 64'h0000000000000002 >> { n380, n384, n390, n391, n392, n387 }; + assign n380 = 32'd134776840 >> { i_25_, n383, n381, n73, n268 }; + assign n381 = 64'hffdfffdfffdfdddd >> { i_32_, i_7_, i_35_, n382, i_33_, i_38_ }; + assign n382 = 4'h1 >> { i_31_, i_8_ }; + assign n383 = 16'h0002 >> { i_32_, i_31_, i_35_, i_38_ }; + assign n78 = 64'h0000000000008000 >> { n79, n130, n138, n166, n180, n595 }; + assign n384 = 64'h0000000000000008 >> { i_3_, i_22_, i_13_, i_2_, n385, i_19_ }; + assign n385 = 16'h0080 >> { n209, n338, n386, i_9_ }; + assign n386 = 16'h0002 >> { i_32_, i_30_, i_35_, i_38_ }; + assign n387 = 64'h5555555555551555 >> { n388, i_10_, n148, n315, i_9_, n389 }; + assign n388 = 8'h15 >> { n366, n362, n316 }; + assign n389 = 16'h1110 >> { n65, n338, n55, n334 }; + assign n390 = 32'd128 >> { i_30_, i_35_, n320, n362, i_38_ }; + assign n391 = 64'h8000000000000000 >> { n75, n51, n271, i_14_, i_33_, i_34_ }; + assign n392 = 64'h0000000000000080 >> { n308, n360, i_24_, n314, n393, i_34_ }; + assign n393 = 8'h02 >> { i_10_, i_8_, i_9_ }; + assign n79 = 32'd1157973317 >> { n85, n80, n109, i_37_, i_32_ }; + assign n394 = 64'h000fffff00011111 >> { n399, n358, n398, n53, n397, n395 }; + assign n395 = 32'd2290122880 >> { n61, n60, n62, n47, n396 }; + assign n396 = 4'h2 >> { i_33_, i_38_ }; + assign n397 = 16'h0008 >> { n308, i_33_, n314, n382 }; + assign n398 = 64'h2222200020002000 >> { n141, n240, n225, n179, i_24_, n368 }; + assign n399 = 8'h51 >> { i_29_, n338, n374 }; + assign n400 = 64'h0080008000800000 >> { n403, n401, i_24_, n404, i_9_, i_19_ }; + assign n401 = 32'd1430274112 >> { n402, n375, n73, n358, i_32_ }; + assign n402 = 8'h01 >> { i_28_, i_29_, i_26_ }; + assign n403 = 32'd572530720 >> { n54, i_34_, n402, i_25_, n386 }; + assign n80 = 16'h0080 >> { i_11_, n83, n84, n81 }; + assign n404 = 4'h2 >> { i_13_, i_18_ }; + assign n405 = 4'h2 >> { i_8_, i_9_ }; + assign n406 = 8'h02 >> { i_13_, i_8_, i_9_ }; + assign n407 = 32'd2290122880 >> { n329, i_38_, n408, n89, n362 }; + assign n408 = 16'h0002 >> { i_31_, i_35_, i_8_, i_38_ }; + assign n409 = 8'h08 >> { n225, n410, n404 }; + assign n410 = 32'd2290122880 >> { n376, n373, n375, n374, n321 }; + assign n411 = 64'h2020202022202020 >> { i_35_, n413, i_11_, n412, n209, n322 }; + assign n412 = 4'h2 >> { n308, n52 }; + assign n413 = 32'd2829626024 >> { n308, i_18_, n306, n305, n406 }; + assign n81 = 32'd8 >> { i_17_, i_20_, i_19_, n69, n82 }; + assign n414 = 4'h1 >> { i_30_, i_2_ }; + assign n415 = 16'h8088 >> { n416, n407, n88, i_13_ }; + assign n416 = 64'hdfdfdfdf55dfdfdf >> { i_33_, n250, n324, n364, i_32_, n322 }; + assign n417 = 8'h08 >> { n388, n137, n319 }; + assign n418 = 16'h5515 >> { i_2_, n376, n419, n420 }; + assign n419 = 4'h2 >> { i_31_, n164 }; + assign n420 = 16'h8880 >> { i_21_, i_20_, n253, i_34_ }; + assign n421 = 32'd2863311402 >> { n308, i_8_, n314, n319, n422 }; + assign n422 = 64'h5055707770777077 >> { i_38_, n329, n383, n308, n408, n414 }; + assign n423 = 64'h0000008000800080 >> { i_25_, i_33_, i_32_, n314, n268, n183 }; + assign n82 = 8'h01 >> { i_4_, i_0_, i_5_ }; + assign n424 = 16'h5515 >> { n159, n253, n268, n425 }; + assign n425 = 64'h0008000800080000 >> { i_21_, i_20_, i_28_, i_34_, i_29_, i_35_ }; + assign n426 = 4'h2 >> { i_13_, i_11_ }; + assign n427 = 64'h4c4c4c4c444c4c4c >> { n458, n431, n630, i_35_, i_38_, n436 }; + assign n428 = 4'h8 >> { n362, n356 }; + assign n429 = 32'd2290657416 >> { i_25_, n393, n268, n430, n73 }; + assign n430 = 16'h0080 >> { i_24_, n319, n164, i_34_ }; + assign n431 = 64'hdfdfdfdfdfdfdf55 >> { i_25_, i_26_, n434, i_34_, n432, n54 }; + assign n432 = 64'hff7fff7f7777ff7f >> { n304, n426, n308, n433, n373, n405 }; + assign n433 = 4'h8 >> { n404, i_11_ }; + assign n83 = 4'h1 >> { i_16_, i_14_ }; + assign n434 = 32'd3755991005 >> { n308, i_8_, n435, i_24_, n319 }; + assign n435 = 4'h1 >> { i_32_, i_30_ }; + assign n436 = 64'h0002000200020202 >> { n443, n457, n373, n442, n437, n444 }; + assign n437 = 64'hc8c8c8c8c8c888c8 >> { n441, n412, n439, n438, n72, n440 }; + assign n438 = 4'h2 >> { i_25_, n54 }; + assign n439 = 16'hdfdd >> { i_32_, n47, n70, n121 }; + assign n440 = 64'h1111100010001000 >> { n142, n141, n225, n121, n360, i_32_ }; + assign n441 = 64'h0000000100010001 >> { i_8_, i_32_, i_29_, i_30_, i_7_, i_28_ }; + assign n442 = 64'h1010101010101110 >> { n360, i_32_, n72, n309, n308, i_7_ }; + assign n443 = 32'd2290122880 >> { n88, n133, n132, n136, n368 }; + assign n48 = 16'h0080 >> { n50, n49, n51, i_37_ }; + assign n84 = 8'h01 >> { i_6_, i_9_, i_7_ }; + assign n444 = 64'h0002000200020000 >> { n454, n59, n447, n445, n455, n449 }; + assign n445 = 64'h8888800080008000 >> { n61, n60, n88, n133, n368, n446 }; + assign n446 = 32'd1 >> { i_32_, i_24_, i_33_, i_35_, i_26_ }; + assign n447 = 32'd2147516544 >> { i_32_, n47, n121, n448, n218 }; + assign n448 = 16'h2022 >> { i_10_, i_13_, i_34_, i_35_ }; + assign n449 = 64'h7707770700007707 >> { n453, n452, n450, n451, n310, n331 }; + assign n450 = 64'hfffefffeeeeefffe >> { i_25_, i_34_, i_33_, i_26_, i_24_, i_28_ }; + assign n451 = 32'd1 >> { i_32_, i_29_, i_30_, i_31_, i_35_ }; + assign n452 = 32'd2 >> { i_28_, i_29_, i_33_, i_34_, i_35_ }; + assign n453 = 16'hfeee >> { i_8_, i_32_, i_7_, i_30_ }; + assign n85 = 64'h0100010001000101 >> { n91, n86, i_35_, n101, n106, n95 }; + assign n454 = 16'h1101 >> { n209, n65, n312, n367 }; + assign n455 = 32'd572662274 >> { n452, n456, n311, n308, n52 }; + assign n456 = 64'h0001000100000001 >> { i_34_, i_26_, i_24_, i_25_, i_28_, i_29_ }; + assign n457 = 8'h08 >> { i_7_, n402, n435 }; + assign n458 = 64'h8a8a88888a0a8808 >> { n456, i_11_, n459, n311, i_19_, n413 }; + assign n459 = 4'h2 >> { n209, n374 }; + assign n460 = 16'h1101 >> { i_7_, n371, n323, n370 }; + assign n461 = 64'hffffff7fff7fff7f >> { i_25_, i_33_, i_32_, n314, n268, n183 }; + assign n462 = 64'hefefeeefefffeeff >> { i_11_, i_3_, i_19_, i_18_, i_22_, i_13_ }; + assign n463 = 8'h08 >> { n344, n315, n52 }; + assign n86 = 32'd32768 >> { n70, n88, n89, n87, n90 }; + assign n464 = 32'd8 >> { i_3_, i_22_, i_13_, i_12_, i_11_ }; + assign n465 = 64'h2222222222222220 >> { n466, n467, n395, n397, i_24_, n54 }; + assign n466 = 64'h2222200020002000 >> { n142, n141, n225, n121, i_32_, n396 }; + assign n467 = 4'h8 >> { n393, n375 }; + assign n468 = 64'h153f153f153f1515 >> { n333, n55, i_23_, n469, n441, n470 }; + assign n469 = 8'h02 >> { i_24_, i_33_, i_38_ }; + assign n470 = 8'h02 >> { i_28_, i_24_, i_22_ }; + assign n471 = 64'h0777077705550777 >> { n473, n373, n472, n348, n474, n73 }; + assign n472 = 8'h02 >> { i_28_, i_29_, i_31_ }; + assign n473 = 64'hfdf5fdf5fdf5ddd5 >> { i_31_, i_35_, i_32_, i_7_, i_8_, i_38_ }; + assign n87 = 8'h01 >> { i_16_, i_14_, i_17_ }; + assign n474 = 64'h0000000000000008 >> { i_32_, i_23_, i_24_, i_31_, i_33_, i_14_ }; + assign n475 = 64'hfe00fe00ff00fe00 >> { i_30_, n408, n373, n476, n477, n478 }; + assign n476 = 32'd2290122880 >> { n329, i_38_, n408, n363, n89 }; + assign n477 = 16'ha888 >> { n88, n133, n132, n383 }; + assign n478 = 8'h08 >> { n308, n319, n366 }; + assign n479 = 64'h0a2a0a2a2a2a0a2a >> { i_31_, n480, n434, n432, i_33_, n314 }; + assign n480 = 32'd1430274112 >> { n141, n240, n225, n179, i_24_ }; + assign n481 = 64'hf0d0f0d0d0d0f0d0 >> { n463, n482, i_12_, i_9_, n483, n486 }; + assign n482 = 32'd1431655701 >> { i_28_, i_7_, n435, n330, n370 }; + assign n483 = 64'haa08aa08aa08aa00 >> { n403, n401, n484, i_24_, n433, n307 }; + assign n88 = 8'h01 >> { i_4_, i_5_, i_2_ }; + assign n484 = 32'd2290122880 >> { n376, n373, n375, n374, n485 }; + assign n485 = 8'h01 >> { i_3_, i_2_, i_8_ }; + assign n486 = 64'h0004000544445555 >> { n492, n489, n403, n401, n490, n487 }; + assign n487 = 32'd2860548224 >> { n366, n310, n315, n316, n488 }; + assign n488 = 16'h1011 >> { i_2_, i_12_, i_30_, i_10_ }; + assign n489 = 16'h0008 >> { n209, i_24_, n386, n322 }; + assign n490 = 16'h1011 >> { i_12_, n462, n491, n464 }; + assign n491 = 64'h0002000200020000 >> { i_19_, i_11_, i_2_, i_22_, i_13_, i_18_ }; + assign n492 = 32'd16843008 >> { i_19_, i_11_, i_13_, i_3_, i_24_ }; + assign n493 = 32'd2829626024 >> { i_30_, n52, n353, n352, n469 }; + assign n89 = 4'h1 >> { i_6_, i_9_ }; + assign o_0_ = 64'hfffffffffffffff7 >> { n652, n640, n511, n554, n535, n564 }; + assign n495 = 8'h01 >> { i_4_, i_5_, i_6_ }; + assign n496 = 32'd2827520136 >> { i_34_, n160, n75, n497, i_21_ }; + assign n497 = 64'h0000000000000008 >> { i_28_, i_27_, i_23_, i_34_, i_35_, i_31_ }; + assign n498 = 16'h0080 >> { i_28_, n414, n499, n74 }; + assign n499 = 4'h2 >> { i_35_, i_36_ }; + assign n500 = 64'haa80aa80aa00aa80 >> { i_34_, i_26_, n501, n435, n119, i_36_ }; + assign n501 = 32'd128 >> { i_32_, i_27_, n73, n177, n72 }; + assign n502 = 64'h0008000000080008 >> { n50, n268, i_29_, i_30_, n102, i_36_ }; + assign n503 = 4'h8 >> { i_14_, i_13_ }; + assign n90 = 64'h0000000000000001 >> { i_28_, i_29_, i_27_, i_23_, i_24_, i_26_ }; + assign n504 = 32'd2728567456 >> { n508, n505, n510, i_9_, i_29_ }; + assign n505 = 8'h02 >> { n506, n70, n227 }; + assign n506 = 8'h51 >> { n507, n495, i_2_ }; + assign n507 = 32'd4261281109 >> { i_35_, i_8_, i_32_, i_7_, i_36_ }; + assign n508 = 32'd128 >> { n509, i_32_, n495, n499, n193 }; + assign n509 = 8'h51 >> { i_18_, i_3_, n225 }; + assign n510 = 32'd8 >> { n200, i_32_, i_31_, n495, n499 }; + assign n511 = 64'haaaaaaaaaaaaaaa2 >> { n531, n532, n525, n528, n512, i_36_ }; + assign n512 = 64'h0000000200020002 >> { n135, n233, n643, n524, n521, n513 }; + assign n513 = 64'h0202020202020002 >> { i_21_, n514, n213, n518, n520, n517 }; + assign n91 = 64'h5540404040404040 >> { n93, n71, n69, n94, n92, i_14_ }; + assign n514 = 32'd2139062271 >> { n515, n62, n52, n516, n214 }; + assign n515 = 16'h0002 >> { i_4_, i_5_, i_18_, i_3_ }; + assign n516 = 16'h0001 >> { i_4_, i_5_, i_6_, i_9_ }; + assign n517 = 32'd2004289399 >> { n200, n47, n90, n77, n65 }; + assign n518 = 32'd32768 >> { i_32_, n73, n334, n519, n72 }; + assign n519 = 16'h0111 >> { i_13_, i_14_, i_12_, i_7_ }; + assign n520 = 32'd32768 >> { i_7_, n73, n74, i_34_, n75 }; + assign n521 = 32'd128 >> { i_17_, n439, n522, n72, n126 }; + assign n522 = 16'h0213 >> { i_10_, i_14_, i_16_, i_13_ }; + assign n523 = 64'h0000000080000000 >> { i_21_, n177, n253, n522, n516, n52 }; + assign n92 = 8'h01 >> { i_29_, i_30_, i_31_ }; + assign n524 = 32'd67392772 >> { n200, n47, n59, n193, n63 }; + assign n525 = 64'ha222222222222222 >> { n65, n148, n227, n64, n526, n329 }; + assign n526 = 64'hdfdfdfdfdfdf55df >> { i_2_, i_21_, n187, n148, n527, n227 }; + assign n527 = 16'h5515 >> { i_21_, n117, n75, n90 }; + assign n528 = 64'haa00aa08aa08aa08 >> { n529, n439, n283, n530, n119, i_34_ }; + assign n529 = 32'd3149642507 >> { i_32_, n70, n121, n194, i_7_ }; + assign n530 = 8'hea >> { i_14_, i_13_, i_16_ }; + assign n531 = 32'd2861206154 >> { n140, n149, n143, n296, n295 }; + assign n532 = 64'h5510101010101010 >> { n75, n92, n136, n533, n534, i_28_ }; + assign n533 = 8'h02 >> { n530, i_7_, n194 }; + assign n93 = 32'd1 >> { i_4_, i_0_, i_1_, i_5_, i_6_ }; + assign n534 = 64'hffdfffdfddddffdf >> { i_29_, n72, i_21_, n268, i_27_, n177 }; + assign n535 = 32'd572531234 >> { n258, n503, n552, n646, n541 }; + assign n536 = 4'h8 >> { n155, n519 }; + assign n537 = 64'ha2a0a2a0a2a0a2a2 >> { n540, i_31_, n233, n538, i_32_, n499 }; + assign n538 = 64'h1111111011101110 >> { n155, n539, n156, n231, i_30_, i_31_ }; + assign n539 = 16'h0111 >> { i_13_, i_14_, i_12_, i_8_ }; + assign n540 = 16'h777f >> { n169, n83, n75, n137 }; + assign n541 = 64'h5151515151515551 >> { n551, n546, n549, i_32_, n499, n542 }; + assign n542 = 64'h5054505454545054 >> { n506, n62, n544, n543, n545, i_21_ }; + assign n543 = 16'h8880 >> { n127, n72, n202, i_20_ }; + assign n49 = 8'h01 >> { i_23_, i_16_, i_17_ }; + assign n94 = 16'h0001 >> { i_28_, i_24_, i_26_, i_34_ }; + assign n544 = 64'h7f7f7f7f007f7f7f >> { n507, n89, n515, n141, i_3_, i_2_ }; + assign n545 = 8'h80 >> { n268, n149, n99 }; + assign n546 = 32'd572530720 >> { n548, n148, n547, i_21_, n227 }; + assign n547 = 8'h08 >> { n70, n69, n516 }; + assign n548 = 8'h08 >> { i_31_, n75, n117 }; + assign n549 = 32'd2004289399 >> { n550, n267, n368, n94, n92 }; + assign n550 = 16'h7757 >> { i_23_, n87, n149, n148 }; + assign n551 = 64'h8880808080808080 >> { i_13_, n89, n87, n114, n88, n90 }; + assign n552 = 64'hffefffefffefddcd >> { i_9_, n553, i_8_, n502, i_12_, i_7_ }; + assign n553 = 16'h7757 >> { n336, n102, n165, i_31_ }; + assign n95 = 16'h8000 >> { n99, n100, n97, n96 }; + assign n554 = 64'hf0d0f0d0d0d0f0d0 >> { n563, n560, i_34_, n499, n555, n556 }; + assign n555 = 4'h2 >> { n526, n382 }; + assign n556 = 64'h1111313331333133 >> { n539, n559, n54, n557, n558, n267 }; + assign n557 = 32'd2863278762 >> { n503, n382, n258, n137, n244 }; + assign n558 = 16'h0080 >> { n540, n74, n51, i_34_ }; + assign n559 = 64'h2020202022202020 >> { i_31_, n495, n253, n183, i_21_, n258 }; + assign n560 = 64'h2222222222220222 >> { n550, i_24_, n356, n102, n562, n561 }; + assign n561 = 64'h7f7f7f7f557f7f7f >> { i_31_, n194, n227, n179, n522, n119 }; + assign n562 = 64'h8880808080808080 >> { i_13_, n89, n87, n114, n88, n282 }; + assign n563 = 16'h888a >> { n557, i_24_, n538, n51 }; + assign n96 = 8'h01 >> { i_23_, i_24_, i_26_ }; + assign n564 = 64'h0002000000020002 >> { i_34_, n576, n574, n565, n567, n649 }; + assign n565 = 16'h1101 >> { i_21_, i_29_, n181, n566 }; + assign n566 = 4'h1 >> { i_14_, i_25_ }; + assign n567 = 32'd2863311522 >> { n568, n571, n573, n572, n72 }; + assign n568 = 8'h08 >> { i_23_, n569, i_21_ }; + assign n569 = 16'h8000 >> { n83, n160, n570, i_13_ }; + assign n570 = 16'h0888 >> { i_17_, i_12_, i_10_, i_7_ }; + assign n571 = 32'd32768 >> { n509, n169, n64, n472, n570 }; + assign n572 = 64'h0707070f070f070f >> { n208, i_21_, n126, n201, n209, n104 }; + assign n573 = 32'd128 >> { i_23_, i_21_, n99, i_20_, n162 }; + assign n97 = 8'h01 >> { i_16_, i_14_, i_20_ }; + assign n574 = 16'h0002 >> { n575, n503, i_9_, i_7_ }; + assign n575 = 32'd4025479150 >> { n553, i_23_, n496, i_16_, i_17_ }; + assign n576 = 64'h8080808080808880 >> { n568, n573, n578, i_24_, n579, n577 }; + assign n577 = 16'h1555 >> { n171, n73, n151, n168 }; + assign n578 = 64'heeceffdfffdfffdf >> { n202, i_20_, n566, n182, i_23_, i_21_ }; + assign n579 = 64'h0777777777777777 >> { n123, n83, n570, i_13_, n73, n474 }; + assign n580 = 64'h0808080008000800 >> { n75, n161, n496, n509, n169, n570 }; + assign n581 = 32'd2290092032 >> { i_25_, n271, n104, n75, n211 }; + assign n582 = 64'h1555555555555555 >> { n435, i_34_, i_36_, n536, n51, n583 }; + assign n583 = 32'd32768 >> { i_29_, n497, n570, n83, i_13_ }; + assign n98 = 64'h0000000000000001 >> { i_0_, i_28_, i_27_, i_12_, i_30_, i_7_ }; + assign n584 = 16'h8000 >> { n64, n162, n204, i_22_ }; + assign n585 = 16'h5554 >> { n237, n238, n239, i_24_ }; + assign n586 = 64'h77077f0f7707ff0f >> { n585, n281, n603, n51, n56, i_34_ }; + assign o_1_ = 64'hffffffff7fffffff >> { n589, n586, n654, n78, n598, n605 }; + assign n588 = 64'hff02020202020202 >> { n54, n75, n77, i_23_, i_35_, n53 }; + assign n589 = 64'h5454505450545054 >> { i_34_, n588, n57, n45, i_37_, i_14_ }; + assign n590 = 64'h0000000100010001 >> { i_17_, i_12_, i_16_, i_14_, i_23_, i_8_ }; + assign n591 = 32'd4294967287 >> { i_12_, i_7_, n50, i_37_, n51 }; + assign n592 = 64'h5054505450545454 >> { i_24_, n154, n591, n150, n590, i_30_ }; + assign n593 = 64'h40006aaa6aaa6aaa >> { n75, n206, n72, n208, n209, i_20_ }; + assign n99 = 8'h02 >> { i_28_, i_27_, i_29_ }; + assign n594 = 64'h080affff0802ffff >> { i_29_, n162, i_20_, n207, n593, n210 }; + assign n595 = 64'h0008000000080008 >> { n217, n191, n203, n212, n195, n594 }; + assign n596 = 64'hf3f2fbfaf3f0fbfa >> { n125, n59, n270, n192, i_32_, n193 }; + assign n597 = 64'h222222222222f222 >> { i_32_, i_30_, i_31_, n104, i_33_, n596 }; + assign n598 = 64'h1111111101111111 >> { i_29_, n208, n597, n173, n235, n601 }; + assign n599 = 64'hffffffffffffff7f >> { i_17_, i_33_, i_10_, n75, n169, n179 }; + assign n600 = 64'hafabafabafababab >> { n232, n233, n164, i_29_, n599, n229 }; + assign n601 = 32'd2863179944 >> { n600, n56, n234, n219, n117 }; + assign n602 = 64'hf888f888faaaf888 >> { i_35_, n277, n262, n194, n270, n163 }; + assign n603 = 64'h0000000100010001 >> { n96, n602, n272, n273, n274, n275 }; + assign n100 = 64'h0000000000000001 >> { i_4_, i_0_, i_12_, i_5_, i_6_, i_7_ }; + assign n604 = 64'haa20202020202020 >> { n96, n103, n164, n69, n292, i_37_ }; + assign n605 = 32'd352654613 >> { n604, i_13_, n71, n293, n608 }; + assign n606 = 64'h7f7f7fffff7fffff >> { n119, i_35_, i_34_, n121, n169, n299 }; + assign n607 = 64'heefefefefefefefe >> { n46, n149, n165, n606, i_10_, i_33_ }; + assign n608 = 32'd2863311402 >> { n294, n300, n297, n607, i_37_ }; + assign n609 = 32'd2324171272 >> { n463, i_11_, n460, i_19_, n404 }; + assign n610 = 64'h75f577ff75f577f7 >> { n462, n464, n609, n461, i_12_, i_10_ }; + assign o_2_ = 32'd4294934527 >> { n427, n614, n622, n610, n633 }; + assign n612 = 32'd2139051391 >> { n369, n307, i_9_, n323, i_12_ }; + assign n613 = 64'h0000000000000008 >> { n317, n327, n337, n657, n341, n339 }; + assign n101 = 64'h8000800080808000 >> { i_20_, n103, n105, n102, n96, n104 }; + assign n614 = 64'h0000000080000000 >> { n302, n612, n613, n350, n379, n660 }; + assign n615 = 32'd4008636128 >> { i_32_, i_30_, i_31_, i_16_, i_27_ }; + assign n616 = 32'd1574789087 >> { i_23_, i_22_, n615, i_29_, i_34_ }; + assign n617 = 64'h5051505151515051 >> { n355, n358, n616, n359, i_28_, i_24_ }; + assign n618 = 64'h0000000000000002 >> { i_28_, i_29_, i_24_, i_31_, i_35_, i_38_ }; + assign n619 = 64'h222222222222f222 >> { i_31_, i_33_, n314, n250, i_32_, n364 }; + assign n620 = 64'hf7f7f7fff7fff7ff >> { n322, n619, n407, i_10_, n315, n88 }; + assign n621 = 64'hffff555455545554 >> { n351, n421, i_26_, i_33_, i_28_, n362 }; + assign n622 = 32'd4008504556 >> { n621, n625, i_24_, i_22_, n627 }; + assign n623 = 64'h0100010001010100 >> { i_33_, n322, n362, i_35_, i_31_, i_32_ }; + assign n102 = 4'h1 >> { i_28_, i_27_ }; + assign n624 = 64'h5555577757775777 >> { n362, n414, n133, n88, n132, n623 }; + assign n625 = 64'h0002000202020002 >> { n411, n624, i_38_, n415, n417, n418 }; + assign n626 = 64'h0000000000000080 >> { i_24_, i_2_, n209, n322, n386, n426 }; + assign n627 = 64'h4444c4ccc4ccc4cc >> { n423, i_12_, n626, i_3_, n424, i_9_ }; + assign n628 = 64'h0f7f0f7f07770f7f >> { i_25_, n74, n402, n419, i_34_, n54 }; + assign n629 = 64'h7f7f7f7f007f7f7f >> { n308, n382, n367, n286, n338, n393 }; + assign n630 = 64'h2220222022222220 >> { n428, n628, n308, i_24_, n429, n629 }; + assign n631 = 64'hffffeeeceeeceeec >> { n319, n386, n353, n352, n354, i_38_ }; + assign n632 = 64'h7575757555757575 >> { i_24_, n438, n631, n636, n465, i_34_ }; + assign n633 = 64'h0202020202020222 >> { n475, n479, n493, n402, n481, n632 }; + assign n103 = 32'd1 >> { i_0_, i_28_, i_27_, i_30_, i_7_ }; + assign n634 = 64'h0000000200020002 >> { i_25_, i_33_, i_24_, i_28_, i_29_, i_38_ }; + assign n635 = 64'h1010101010101055 >> { i_8_, n308, i_31_, n393, i_30_, i_35_ }; + assign n636 = 64'h8088808800888088 >> { i_25_, n635, n634, n439, n468, n471 }; + assign n637 = 64'h0808080008000800 >> { n69, n495, n187, i_21_, i_36_, n52 }; + assign n638 = 32'd3149638587 >> { i_9_, i_7_, n496, n637, i_12_ }; + assign n639 = 64'h7f7f7f7f7f7f557f >> { n200, i_35_, n55, n331, n227, i_36_ }; + assign n640 = 32'd134742024 >> { n504, n639, i_21_, n117, n75 }; + assign n641 = 64'h1111111111111151 >> { i_4_, i_5_, i_6_, i_29_, i_30_, i_21_ }; + assign n642 = 64'h808080808080aa80 >> { n503, i_29_, n147, n519, n641, n258 }; + assign n643 = 32'd2290649256 >> { i_32_, i_28_, n642, n523, n267 }; + assign n50 = 8'h8d >> { i_35_, i_24_, i_34_ }; + assign n104 = 16'h0111 >> { i_17_, i_12_, i_14_, i_16_ }; + assign n644 = 64'h15151515bf151515 >> { i_12_, n170, n83, n536, n435, i_29_ }; + assign n645 = 64'hdfdfdfdfdddfdfdf >> { i_35_, n179, n522, n533, i_17_, n75 }; + assign n646 = 64'h8a8a82808a8a8a80 >> { n645, n537, i_36_, i_29_, n644, n117 }; + assign n647 = 64'hff80808080808080 >> { n208, n271, n335, n75, n104, n206 }; + assign n648 = 64'h0001010100111111 >> { i_21_, n96, n569, n647, n581, n584 }; + assign n649 = 32'd32768 >> { n580, n195, n339, n648, n582 }; + assign n650 = 64'hf080f080f080f888 >> { i_23_, i_12_, n498, n177, n253, i_0_ }; + assign n651 = 64'h5d5d5d5dff5d5d5d >> { i_21_, n267, n650, i_7_, n500, n638 }; + assign n652 = 64'h5510101010101010 >> { n49, n52, n502, n651, i_16_, n503 }; + assign n653 = 64'h2323232322232323 >> { i_8_, n119, n125, n283, n285, n247 }; + assign n105 = 8'h02 >> { i_29_, i_30_, i_31_ }; + assign n654 = 64'h0040004450505555 >> { n76, n56, n284, n287, n653, n278 }; + assign n655 = 32'd4294967287 >> { i_32_, i_28_, i_29_, n268, n364 }; + assign n656 = 64'h02220aaa03330bbb >> { i_26_, i_25_, i_8_, i_32_, i_33_, i_34_ }; + assign n657 = 64'h8a8a8a0a8a0a8a0a >> { n656, n618, n365, n655, n89, n363 }; + assign n658 = 64'h0000000000000002 >> { i_28_, i_29_, i_24_, i_30_, i_35_, i_38_ }; + assign n659 = 64'h0088008088888080 >> { i_33_, i_34_, i_25_, n402, n658, n406 }; + assign n660 = 64'h0000000800080008 >> { n509, n659, n400, n409, n394, n620 }; + assign n106 = 64'h0000000000000080 >> { i_17_, i_20_, i_18_, n107, n69, n108 }; + assign n107 = 64'h0000000000000002 >> { i_4_, i_0_, i_5_, i_6_, i_7_, i_3_ }; + assign n108 = 8'h01 >> { i_16_, i_14_, i_9_ }; + assign n109 = 64'h08080008aaaa00aa >> { n116, n118, n76, n110, n111, n124 }; + assign n110 = 32'd32768 >> { n70, n56, n82, n89, n87 }; + assign n111 = 32'd125269879 >> { n87, n112, n113, n115, n114 }; + assign n112 = 8'h01 >> { i_5_, i_6_, i_7_ }; + assign n113 = 16'h0002 >> { i_4_, i_0_, i_1_, i_37_ }; + assign n51 = 8'h01 >> { i_28_, i_29_, i_27_ }; + assign n114 = 64'h0000000000000001 >> { i_16_, i_17_, i_13_, i_6_, i_9_, i_10_ }; + assign n115 = 64'h0000000000000002 >> { i_4_, i_0_, i_33_, i_5_, i_35_, i_37_ }; + assign n116 = 16'h0080 >> { i_20_, n75, i_29_, n117 }; + assign n117 = 8'h01 >> { i_28_, i_27_, i_26_ }; + assign n118 = 64'h7f7f7f7f007f7f7f >> { i_30_, n123, n122, n119, n120, n121 }; + assign n119 = 64'h0000000000000001 >> { i_28_, i_29_, i_27_, i_23_, i_24_, i_17_ }; + assign n120 = 16'h1011 >> { i_10_, i_13_, i_16_, i_14_ }; + assign n121 = 64'h0000000000000001 >> { i_4_, i_5_, i_6_, i_9_, i_2_, i_7_ }; + assign n122 = 64'h0001010100555555 >> { i_14_, i_12_, i_17_, i_13_, i_33_, i_16_ }; + assign n123 = 64'h0000000000000002 >> { i_28_, i_29_, i_27_, i_23_, i_24_, i_31_ }; + assign n52 = 4'h1 >> { i_7_, i_8_ }; + assign n124 = 32'd125269879 >> { n126, n129, n125, n128, n127 }; + assign n125 = 64'h0000000000000001 >> { i_4_, i_1_, i_5_, i_6_, i_2_, i_7_ }; + assign n126 = 16'h0001 >> { i_28_, i_29_, i_27_, i_23_ }; + assign n127 = 8'h01 >> { i_24_, i_26_, i_34_ }; + assign n128 = 32'd8 >> { i_28_, i_30_, i_31_, i_29_, i_21_ }; + assign n129 = 64'h0000000000000008 >> { i_16_, i_14_, i_17_, i_34_, i_35_, i_37_ }; + assign n130 = 32'd1413760068 >> { n137, n75, n83, n131, n134 }; + assign n131 = 32'd2290122880 >> { n88, n133, n132, n75, n87 }; + assign n132 = 4'h8 >> { n60, n61 }; + assign n133 = 16'h0001 >> { i_6_, i_9_, i_11_, i_19_ }; + assign n53 = 8'h08 >> { i_24_, n55, n54 }; + assign n134 = 32'd4261281279 >> { n117, n135, i_32_, i_29_, n56 }; + assign n135 = 4'h8 >> { n51, n136 }; + assign n136 = 8'h02 >> { i_32_, i_35_, i_34_ }; + assign n137 = 32'd1 >> { i_4_, i_12_, i_5_, i_6_, i_2_ }; + assign n138 = 32'd269553937 >> { n165, n163, n139, n592, n157 }; + assign n139 = 32'd707398186 >> { i_35_, n148, n149, n140, n143 }; + assign n140 = 4'h8 >> { n141, n142 }; + assign n141 = 4'h1 >> { i_9_, i_18_ }; + assign n142 = 64'h0000000000000002 >> { i_4_, i_5_, i_6_, i_2_, i_7_, i_3_ }; + assign n143 = 32'd125269879 >> { n146, n121, n145, n147, n144 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act b/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act new file mode 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b/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif new file mode 100644 index 000000000..a5c5a5258 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif @@ -0,0 +1,1595 @@ +# Benchmark "apex4" written by ABC on Tue Mar 12 09:25:04 2019 +.model apex4 +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ \ + o_12_ o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ +.names n28 + 0 +.names n516 n85 n73 n57 n514 o_1_ +11111 0 +.names i_0_ i_2_ i_1_ n32 +100 1 +.names i_3_ i_4_ n33 +10 1 +.names i_6_ i_7_ i_8_ n34 +110 1 +.names i_8_ i_6_ i_7_ n35 +100 1 +.names i_5_ i_3_ i_4_ n36 +110 1 +.names i_7_ i_8_ i_6_ n37 +110 1 +.names i_7_ i_0_ i_6_ i_8_ i_2_ i_1_ n38 +110000 1 +.names i_1_ i_3_ i_4_ i_5_ i_2_ i_0_ n39 +111000 1 +.names n41 n47 n44 n45 n36 n46 n40 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n42 n43 i_6_ i_8_ i_7_ n41 +11000 1 +.names i_0_ i_1_ n42 +10 1 +.names i_4_ i_3_ i_5_ n43 +110 1 +.names i_5_ i_0_ i_1_ i_2_ i_3_ i_4_ n44 +111100 1 +.names i_6_ i_8_ i_7_ i_2_ i_0_ i_1_ n45 +111110 1 +.names i_6_ i_8_ i_7_ n46 +000 1 +.names i_0_ i_1_ i_4_ i_2_ i_5_ i_3_ n47 +111100 1 +.names n44 n49 n36 n50 n48 +11-- 0 +--11 0 +.names i_6_ i_8_ i_7_ n49 +110 1 +.names i_6_ i_8_ i_7_ i_0_ i_2_ i_1_ n50 +111100 1 +.names n52 n35 n51 +11 1 +.names i_5_ i_0_ i_3_ i_4_ i_2_ n52 +11000 1 +.names i_1_ i_0_ i_2_ n53 +110 1 +.names i_6_ i_7_ n54 +11 1 +.names i_2_ i_0_ i_1_ n55 +110 1 +.names i_5_ i_3_ i_4_ n56 +111 1 +.names n64 n58 n69 n67 n36 n72 n57 +11000- 1 +1100-0 1 +.names n59 n63 n44 n58 +10- 1 +1-0 1 +.names n61 n62 n32 n60 n46 n59 +11--- 0 +--111 0 +.names i_3_ i_5_ i_4_ n60 +100 1 +.names i_6_ i_7_ n61 +00 1 +.names i_5_ i_1_ i_4_ i_2_ i_0_ i_3_ n62 +111110 1 +.names i_6_ i_8_ i_7_ n63 +100 1 +.names n66 n63 n65 n38 n64 +11-- 0 +--11 0 +.names i_5_ i_4_ n65 +10 1 +.names i_5_ i_3_ i_1_ i_2_ i_4_ i_0_ n66 +111100 1 +.names n68 n35 n67 +11 1 +.names i_0_ i_1_ i_5_ i_3_ i_4_ i_2_ n68 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i_5_ i_4_ n76 i_3_ n175 i_6_ n520 +0010-- 0 +00--11 0 +.names n181 n179 n520 n172 n171 n177 n521 +111110 1 +.names n521 n168 n165 n176 n107 n35 n522 +1110-- 1 +111-00 1 +.names n193 n192 n191 n187 n36 n190 n523 +00000- 1 +0000-0 1 +.names n63 n98 n162 n189 n55 n46 n524 +11---- 0 +1-1--- 0 +---111 0 +.names n523 n184 n524 n32 n194 n525 +1110- 1 +111-1 1 +.names n96 n39 n49 n94 n210 n526 +1--1- 0 +1---1 0 +-11-- 0 +.names n214 n213 n212 n211 n526 n527 +11111 1 +.names i_2_ i_0_ n114 n112 i_8_ i_3_ n528 +001--- 1 +1--100 1 +.names n239 n236 n235 n234 i_1_ n528 n529 +11100- 1 +1110-0 1 +.names n231 n227 n222 n221 n529 n192 n530 +111110 1 +.names n190 n50 n101 n103 n60 n43 n531 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names i_1_ n71 n78 n130 i_0_ n49 n532 +011--- 0 +1--111 0 +.names n532 n248 n252 n35 n87 n533 +1100- 1 +110-0 1 +.names i_6_ i_8_ i_7_ n182 n99 n534 +000-1 0 +11-1- 0 +1-1-- 0 +-11-- 0 +.names n258 n256 n534 i_7_ n257 n201 n535 +1101-- 1 +1110-- 1 +11-100 1 +.names n308 n305 n188 n34 n53 n82 n536 +100-0- 1 +100--0 1 +10-0-- 1 +.names n103 n43 n49 n68 n306 n75 n537 +11---- 0 +--11-- 0 +----11 0 +.names n309 n307 n536 n303 n537 n304 n538 +111110 1 +.names i_5_ i_4_ n190 n287 n134 i_6_ n539 +011--- 1 +1--110 1 +.names n527 n358 n159 n350 n546 n357 n540 +111110 1 +.names n530 n578 n540 n73 n539 i_3_ o_5_ +11110- 0 +1111-1 0 +.names i_7_ i_6_ i_8_ n180 n333 n238 n542 +100-11 0 +1111-- 0 +.names n542 n334 n335 n332 n254 n543 +11000 1 +.names i_3_ i_4_ i_8_ i_1_ i_2_ i_5_ n544 +1000-- 1 +10--11 1 +.names i_6_ i_7_ i_0_ n544 n94 i_8_ n545 +1011-- 0 +10--11 0 +.names n349 n348 n347 n345 n344 n545 n546 +111111 1 +.names n378 n377 i_6_ n170 i_8_ i_7_ n547 +100--- 1 +10-0-- 1 +10--10 1 +.names n538 n583 n581 n551 n361 n547 o_6_ +111111 0 +.names n155 n50 n146 n152 n107 n43 n549 +1000-- 1 +100-0- 1 +1--0-0 1 +1---00 1 +.names n363 n362 n272 n245 n243 n242 n550 +111111 1 +.names n372 n368 n365 n550 n549 n551 +11111 1 +.names n274 n257 n76 n130 n34 n134 n552 +100--0 1 +10-0-- 1 +1-0-0- 1 +1--00- 1 +.names n387 n384 n210 n161 n46 n35 n553 +1000-- 1 +100-0- 1 +10-0-0 1 +10--00 1 +.names i_7_ n147 n37 n167 n244 i_8_ n554 +01---- 0 +1---10 0 +--11-- 0 +.names n413 n412 n339 n172 n338 n207 n555 +111100 1 +.names n551 n533 n405 n391 n555 n554 o_7_ +111111 0 +.names i_8_ i_6_ n108 i_7_ n43 n42 n557 +10--11 0 +1110-- 0 +.names n437 n435 n434 n433 n387 n304 n558 +111110 1 +.names n392 n558 n557 n64 n60 n84 n559 +11110- 1 +1111-0 1 +.names i_8_ n439 n438 i_6_ n436 n244 n560 +0--11- 1 +1001-- 1 +100--0 1 +.names i_2_ i_3_ n148 n54 i_5_ i_4_ n561 +001--- 1 +10-111 1 +.names n450 n449 i_1_ i_0_ n561 n138 n562 +100--0 1 +101-0- 1 +10-0-- 1 +.names n543 n350 n562 n446 n448 n447 n563 +111100 1 +.names i_7_ i_6_ n447 n62 n240 i_8_ n564 +00--00 0 +11-1-- 0 +--1--- 0 +.names n458 n456 n446 n419 n263 n564 n565 +111111 1 +.names n464 n183 n93 n149 n76 n37 n566 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n400 n151 n566 n399 n398 n567 +11100 1 +.names n188 n161 n68 n76 n36 n49 n568 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names i_6_ i_7_ i_8_ n127 n182 n97 n569 +010--- 1 +100--- 1 +10--0- 1 +1110-- 1 +-10000 1 +.names n475 n474 n437 i_6_ n569 n87 n570 +11100- 1 +11111- 1 +111-10 1 +.names n207 n152 n170 n215 n36 n34 n571 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n490 n489 n488 n487 n313 n389 n572 +111110 1 +.names n241 n87 n89 n170 n54 n63 n573 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n531 n242 n253 n245 n243 n254 n574 +111110 1 +.names n533 n574 n171 n573 n37 n66 n575 +11110- 1 +1111-0 1 +.names i_7_ i_6_ i_8_ n210 n39 n152 n576 +111--1 0 +11--1- 0 +1-01-- 0 +.names n343 n342 n331 n330 n328 n576 n577 +111111 1 +.names n543 n336 n270 n577 n32 n114 n578 +11110- 1 +1111-0 1 +.names i_7_ n162 n137 n189 n36 n32 n579 +0---11 1 +11---- 1 +1-11-- 1 +.names i_7_ i_6_ n579 i_8_ n376 n115 n580 +0011-- 0 +01---1 0 +1010-- 0 +----1- 0 +.names n388 n379 n375 n580 n56 n76 n581 +11110- 1 +1111-0 1 +.names n36 n72 n82 n83 n134 n35 n582 +11---- 0 +1---11 0 +--11-- 0 +.names n553 n552 n385 n582 n75 n154 n583 +11110- 1 +1111-0 1 +.names n190 i_1_ n126 i_3_ i_4_ i_2_ n584 +1----- 0 +-11110 0 +.names n560 i_8_ i_5_ n396 n584 i_7_ n585 +01---- 0 +100--1 0 +--0-0- 0 +---1-- 0 +.names n441 n440 n314 n286 n261 n585 n586 +111111 1 +.names n66 n34 n87 n49 n153 n54 n587 +11---- 0 +--11-- 0 +----11 0 +.names n411 n265 n88 n63 n37 n188 n588 +1100-- 1 +110--0 1 +11-00- 1 +.names n567 n467 n465 n58 n588 n587 n589 +111111 1 +.names i_4_ i_5_ i_3_ n103 n137 n107 n590 +000-11 0 +1001-- 0 +.names n568 n469 n590 n185 n35 n127 n591 +11100- 1 +1110-0 1 +.names n35 n47 n107 n182 n134 n36 n592 +11---- 0 +1---11 0 +--11-- 0 +.names n491 n450 n410 n63 n82 n137 n593 +1100-- 1 +110-0- 1 +110--0 1 +.names n572 n571 n592 n259 n593 n304 n594 +111110 1 +.names n28 o_0_ +1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v b/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v new file mode 100644 index 000000000..2b192b740 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v @@ -0,0 +1,1145 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module apex4(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_); + input i_0_; + input i_1_; + input i_2_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + wire n100; + wire n101; + wire n102; + wire n103; + wire n105; + wire n106; + wire n107; + wire n108; + wire n109; + wire n110; + wire n111; + wire n112; + wire n113; + wire n114; + wire n115; + wire n116; + wire n117; + wire n118; + wire n119; + wire n120; + wire n121; + wire n122; + wire n123; + wire n124; + wire n125; + wire n126; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n278; + wire n279; + wire n28; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n32; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n33; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n34; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n35; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n36; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n37; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n377; + wire n378; + wire n379; + wire n38; + wire n380; + wire n381; + wire n382; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n39; + wire n390; + wire n391; + wire n392; + wire n393; + wire n394; + wire n395; + wire n396; + wire n397; + wire n398; + wire n399; + wire n40; + wire n400; + wire n401; + wire n402; + wire n403; + wire n404; + wire n405; + wire n406; + wire n407; + wire n408; + wire n409; + wire n41; + wire n410; + wire n411; + wire n412; + wire n413; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n42; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n427; + wire n428; + wire n429; + wire n43; + wire n430; + wire n431; + wire n433; + wire n434; + wire n435; + wire n436; + wire n437; + wire n438; + wire n439; + wire n44; + wire n440; + wire n441; + wire n442; + wire n443; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n45; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n456; + wire n457; + wire n458; + wire n459; + wire n46; + wire n460; + wire n461; + wire n462; + wire n463; + wire n464; + wire n465; + wire n466; + wire n467; + wire n468; + wire n469; + wire n47; + wire n470; + wire n472; + wire n473; + wire n474; + wire n475; + wire n476; + wire n477; + wire n478; + wire n479; + wire n48; + wire n480; + wire n481; + wire n482; + wire n483; + wire n484; + wire n485; + wire n487; + wire n488; + wire n489; + wire n49; + wire n490; + wire n491; + wire n492; + wire n494; + wire n496; + wire n497; + wire n498; + wire n499; + wire n50; + wire n500; + wire n501; + wire n502; + wire n503; + wire n505; + wire n506; + wire n507; + wire n509; + wire n51; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n52; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n53; + wire n530; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n54; + wire n540; + wire n542; + wire n543; + wire n544; + wire n545; + wire n546; + wire n547; + wire n549; + wire n55; + wire n550; + wire n551; + wire n552; + wire n553; + wire n554; + wire n555; + wire n557; + wire n558; + wire n559; + wire n56; + wire n560; + wire n561; + wire n562; + wire n563; + wire n564; + wire n565; + wire n566; + wire n567; + wire n568; + wire n569; + wire n57; + wire n570; + wire n571; + wire n572; + wire n573; + wire n574; + wire n575; + wire n576; + wire n577; + wire n578; + wire n579; + wire n58; + wire n580; + wire n581; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n587; + wire n588; + wire n589; + wire n59; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n60; + wire n61; + wire n62; + wire n63; + wire n64; + wire n65; + wire n66; + wire n67; + wire n68; + wire n69; + wire n70; + wire n71; + wire n72; + wire n73; + wire n74; + wire n75; + wire n76; + wire n77; + wire n78; + wire n79; + wire n80; + wire n81; + wire n82; + wire n83; + wire n84; + wire n85; + wire n86; + wire n87; + wire n88; + wire n89; + wire n90; + wire n91; + wire n92; + wire n93; + wire n94; + wire n95; + wire n96; + wire n97; + wire n98; + wire n99; + output o_0_; + output o_10_; + output o_11_; + output o_12_; + output o_13_; + output o_14_; + output o_15_; + output o_16_; + output o_17_; + output o_18_; + output o_1_; + output o_2_; + output o_3_; + output o_4_; + output o_5_; + output o_6_; + output o_7_; + output o_8_; + output o_9_; + assign o_1_ = 32'd2147483647 >> { n514, n57, n73, n85, n516 }; + assign n40 = 64'h0001010100555555 >> { n46, n36, n45, n44, n47, n41 }; + assign n130 = 4'h2 >> { i_3_, i_4_ }; + assign n131 = 8'h02 >> { i_1_, i_0_, i_2_ }; + assign n132 = 64'h0002000000028000 >> { i_5_, i_0_, i_1_, i_4_, i_3_, n63 }; + assign n133 = 64'h7d7ffdfffdfffdff >> { n130, i_8_, n135, i_7_, i_6_, n134 }; + assign n134 = 8'h80 >> { i_1_, i_0_, i_2_ }; + assign n135 = 4'h8 >> { i_3_, i_5_ }; + assign n136 = 16'h0777 >> { n61, n139, n137, n138 }; + assign n137 = 8'h02 >> { i_0_, i_2_, i_1_ }; + assign n138 = 32'd8 >> { i_4_, i_3_, i_7_, i_5_, i_8_ }; + assign n139 = 64'h0000000000000008 >> { i_1_, i_4_, i_3_, i_5_, i_2_, i_0_ }; + assign n41 = 32'd8 >> { i_7_, i_8_, i_6_, n43, n42 }; + assign n140 = 64'hfff6ffffdff6dfff >> { i_6_, i_3_, i_8_, i_4_, i_7_, i_5_ }; + assign n141 = 64'h76f67efe77f77fff >> { n127, n111, n108, i_6_, i_8_, i_7_ }; + assign n142 = 64'h0000077707770777 >> { n146, n56, n144, n147, n143, n145 }; + assign n143 = 4'h8 >> { i_1_, i_0_ }; + assign n144 = 4'h2 >> { i_7_, i_8_ }; + assign n145 = 32'd8 >> { i_4_, i_8_, i_6_, i_3_, i_7_ }; + assign n146 = 64'h0000000080000000 >> { i_0_, i_1_, i_2_, i_7_, i_8_, i_6_ }; + assign n147 = 64'h0000000000008000 >> { i_2_, i_6_, i_1_, i_3_, i_5_, i_0_ }; + assign n148 = 4'h1 >> { i_8_, i_6_ }; + assign n149 = 8'h01 >> { i_4_, i_3_, i_5_ }; + assign n42 = 4'h2 >> { i_1_, i_0_ }; + assign n150 = 16'h8000 >> { n151, n155, n159, n163 }; + assign n151 = 64'h0000077707770777 >> { n35, n152, n153, n49, n75, n154 }; + assign n152 = 64'h0000000080000000 >> { i_5_, i_0_, i_2_, i_4_, i_3_, i_1_ }; + assign n153 = 64'h8000000000000000 >> { i_1_, i_0_, i_2_, i_4_, i_3_, i_5_ }; + assign n154 = 64'h0000000080000000 >> { i_2_, i_0_, i_1_, i_7_, i_8_, i_6_ }; + assign n155 = 64'h0000077707770777 >> { n118, n158, n49, n157, n156, n146 }; + assign n156 = 4'h2 >> { i_3_, i_5_ }; + assign n157 = 64'h0000000000008000 >> { i_4_, i_5_, i_2_, i_1_, i_3_, i_0_ }; + assign n158 = 8'h02 >> { i_0_, i_3_, i_1_ }; + assign n159 = 64'h0000077707770777 >> { n71, n160, n107, n162, n63, n161 }; + assign n43 = 8'h08 >> { i_5_, i_3_, i_4_ }; + assign n160 = 64'h0000000000008000 >> { i_4_, i_6_, i_5_, i_7_, i_8_, i_0_ }; + assign n161 = 64'h0000000000000080 >> { i_1_, i_0_, i_4_, i_2_, i_3_, i_5_ }; + assign n162 = 64'h0000000000008000 >> { i_0_, i_3_, i_2_, i_4_, i_1_, i_5_ }; + assign n163 = 64'h0000077707770777 >> { n72, n56, n36, n164, n96, n88 }; + assign n164 = 64'h0000000000000080 >> { i_1_, i_8_, i_6_, i_7_, i_0_, i_2_ }; + assign n165 = 64'h0001010100555555 >> { n35, n37, n93, n162, n167, n166 }; + assign n166 = 4'h8 >> { n43, n45 }; + assign n167 = 64'h0000000000000080 >> { i_2_, i_4_, i_5_, i_0_, i_3_, i_1_ }; + assign n168 = 64'h0001010100555555 >> { n46, n96, n127, n152, n170, n169 }; + assign n169 = 4'h8 >> { n34, n89 }; + assign n44 = 64'h0000000000008000 >> { i_4_, i_3_, i_2_, i_1_, i_0_, i_5_ }; + assign n170 = 64'h0000000000000080 >> { i_0_, i_4_, i_5_, i_1_, i_3_, i_2_ }; + assign n171 = 16'h0777 >> { n66, n61, n37, n94 }; + assign n172 = 64'h7777777777770777 >> { i_7_, i_8_, n173, n174, n81, n82 }; + assign n173 = 8'h02 >> { i_4_, i_5_, i_6_ }; + assign n174 = 8'h80 >> { i_0_, i_2_, i_3_ }; + assign n175 = 32'd8 >> { i_1_, i_3_, i_7_, i_0_, i_8_ }; + assign n176 = 64'h0000000000000080 >> { i_0_, i_2_, i_4_, i_1_, i_3_, i_5_ }; + assign n177 = 4'h8 >> { n178, n115 }; + assign n178 = 4'h2 >> { i_7_, i_6_ }; + assign n179 = 64'hcdedddfdcdefddff >> { n180, n108, n170, i_8_, i_6_, i_7_ }; + assign n45 = 64'h0000000080000000 >> { i_1_, i_0_, i_2_, i_7_, i_8_, i_6_ }; + assign n180 = 64'h0000000000000080 >> { i_1_, i_3_, i_5_, i_4_, i_0_, i_2_ }; + assign n181 = 64'h0000077707770777 >> { n182, n34, n49, n183, n80, n50 }; + assign n182 = 64'h0000000000000080 >> { i_1_, i_4_, i_5_, i_0_, i_3_, i_2_ }; + assign n183 = 64'h0000000000008000 >> { i_2_, i_5_, i_1_, i_4_, i_3_, i_0_ }; + assign n184 = 64'h0001010100111111 >> { n144, n111, n118, n93, n186, n185 }; + assign n185 = 4'h8 >> { n96, n44 }; + assign n186 = 4'h8 >> { n83, n60 }; + assign n187 = 4'h8 >> { n46, n188 }; + assign n188 = 64'h0000000000000008 >> { i_1_, i_0_, i_3_, i_5_, i_2_, i_4_ }; + assign n189 = 4'h2 >> { i_5_, i_3_ }; + assign n46 = 8'h01 >> { i_7_, i_8_, i_6_ }; + assign n190 = 64'h0000000000000080 >> { i_1_, i_0_, i_7_, i_2_, i_8_, i_6_ }; + assign n191 = 4'h8 >> { n144, n99 }; + assign n192 = 4'h8 >> { n107, n93 }; + assign n193 = 16'h8000 >> { n70, n34, n131, i_3_ }; + assign n194 = 64'hfdfff9fbfffff9fb >> { i_4_, i_7_, i_3_, i_6_, i_5_, i_8_ }; + assign n195 = 32'd526344 >> { n47, n34, n202, n196, n203 }; + assign n196 = 64'h0080008000808080 >> { n63, n96, n201, n198, n200, n197 }; + assign n197 = 16'h0777 >> { n46, n88, n107, n66 }; + assign n198 = 32'd125269879 >> { i_0_, i_2_, n199, n93, n46 }; + assign n199 = 32'd8 >> { i_4_, i_5_, i_6_, i_8_, i_7_ }; + assign n47 = 64'h0000000000008000 >> { i_3_, i_5_, i_2_, i_4_, i_1_, i_0_ }; + assign n200 = 32'd1467447159 >> { i_7_, i_0_, i_2_, n103, n82 }; + assign n201 = 64'h0000000000000080 >> { i_1_, i_0_, i_5_, i_4_, i_3_, i_2_ }; + assign n202 = 32'd286265360 >> { n143, n56, n52, i_7_, i_8_ }; + assign n203 = 16'h7707 >> { i_5_, n72, n54, n153 }; + assign n204 = 32'd2147483648 >> { n205, n527, n216, n218, n219 }; + assign n205 = 32'd526344 >> { n209, n96, n207, n206, n208 }; + assign n206 = 32'd125269879 >> { n35, n36, n55, n38, n82 }; + assign n207 = 4'h8 >> { n84, n56 }; + assign n208 = 64'h4c6e5d7f5d7f5d7f >> { n92, i_6_, n183, n182, i_8_, i_7_ }; + assign n209 = 64'h0000000000000008 >> { i_1_, i_0_, i_4_, i_3_, i_2_, i_5_ }; + assign n48 = 16'h0777 >> { n50, n36, n49, n44 }; + assign n210 = 64'h0000000000008000 >> { i_1_, i_0_, i_2_, i_4_, i_3_, i_5_ }; + assign n211 = 16'h0777 >> { n56, n83, n63, n176 }; + assign n212 = 32'd5723991 >> { n75, n50, n167, n183, n37 }; + assign n213 = 64'h1515153f153f153f >> { n189, n137, n152, n75, n81, n107 }; + assign n214 = 64'hd4dcf4fed5ddf5ff >> { n154, n215, n101, i_4_, i_3_, i_5_ }; + assign n215 = 64'h0000000000000080 >> { i_2_, i_7_, i_8_, i_0_, i_1_, i_6_ }; + assign n216 = 16'h1555 >> { n135, n143, n96, n217 }; + assign n217 = 8'h08 >> { i_3_, i_1_, n160 }; + assign n218 = 64'h0000077707770777 >> { n127, n35, n114, n53, n63, n210 }; + assign n219 = 32'd353703231 >> { n34, n37, n80, n83, n201 }; + assign n49 = 8'h08 >> { i_7_, i_8_, i_6_ }; + assign o_3_ = 32'd2147483647 >> { n530, n575, n255, n264, n270 }; + assign n221 = 16'h222a >> { n97, n209, n34, n48 }; + assign n222 = 32'd526344 >> { n99, n63, n223, n225, n224 }; + assign n223 = 4'h8 >> { n82, n50 }; + assign n224 = 32'd125269879 >> { n49, n53, n70, n90, n65 }; + assign n225 = 32'd2004289399 >> { i_1_, n71, n226, n127, n34 }; + assign n226 = 32'd2 >> { i_4_, i_5_, i_7_, i_6_, i_8_ }; + assign n227 = 64'h0080008000808080 >> { n47, n162, n34, n228, n229, n230 }; + assign n228 = 64'hf5fdf7fff7fff7ff >> { n60, i_0_, n82, i_2_, i_1_, n46 }; + assign n229 = 32'd125269879 >> { n56, n53, n34, n157, n96 }; + assign n32 = 8'h02 >> { i_1_, i_2_, i_0_ }; + assign n50 = 64'h0000000000008000 >> { i_1_, i_2_, i_0_, i_7_, i_8_, i_6_ }; + assign n230 = 32'd125269879 >> { n55, n61, n156, n45, n36 }; + assign n231 = 32'd17895697 >> { n56, n46, n32, n233, n232 }; + assign n232 = 16'h0080 >> { i_1_, n112, n71, i_8_ }; + assign n233 = 4'h8 >> { n63, n93 }; + assign n234 = 4'h8 >> { n96, n93 }; + assign n235 = 16'h0777 >> { n127, n35, n63, n210 }; + assign n236 = 64'hb1f5b9fdb3f7bbff >> { n237, n175, n154, i_6_, i_4_, i_5_ }; + assign n237 = 32'd8 >> { i_1_, i_7_, i_8_, i_0_, i_2_ }; + assign n238 = 8'h08 >> { i_3_, i_2_, i_1_ }; + assign n239 = 64'h0777077700000777 >> { n240, n46, n115, n35, n149, n164 }; + assign n51 = 4'h8 >> { n35, n52 }; + assign n240 = 64'hfffffffdffff7ffd >> { i_5_, i_4_, i_2_, i_3_, i_1_, i_0_ }; + assign n241 = 4'h8 >> { n46, n127 }; + assign n242 = 16'h0777 >> { n46, n180, n82, n154 }; + assign n243 = 32'd2004289399 >> { i_6_, i_8_, n244, n176, n37 }; + assign n244 = 64'h0000000000000008 >> { i_0_, i_2_, i_4_, i_5_, i_3_, i_1_ }; + assign n245 = 64'h1515153f153f153f >> { n63, n246, n247, n108, n34, n149 }; + assign n246 = 8'h08 >> { i_0_, i_1_, i_2_ }; + assign n247 = 32'd2 >> { i_2_, i_7_, i_8_, i_6_, i_0_ }; + assign n248 = 32'd125269879 >> { n134, n33, n249, n251, n250 }; + assign n249 = 4'h2 >> { i_8_, i_6_ }; + assign n52 = 32'd8 >> { i_2_, i_4_, i_3_, i_0_, i_5_ }; + assign n250 = 4'h2 >> { i_0_, i_1_ }; + assign n251 = 64'h0000000000000008 >> { i_3_, i_7_, i_8_, i_6_, i_5_, i_4_ }; + assign n252 = 4'h8 >> { n96, n152 }; + assign n253 = 16'h0777 >> { n199, n238, n96, n98 }; + assign n254 = 4'h8 >> { n96, n188 }; + assign n255 = 32'd2147483648 >> { n184, n535, n259, n261, n263 }; + assign n256 = 32'd125269879 >> { n34, n75, n53, n183, n63 }; + assign n257 = 32'd128 >> { i_0_, i_2_, i_1_, i_4_, i_3_ }; + assign n258 = 16'h0777 >> { n56, n50, n80, n103 }; + assign n259 = 8'h2a >> { n99, n49, n260 }; + assign n53 = 8'h08 >> { i_2_, i_0_, i_1_ }; + assign n260 = 64'h56de76fe57df77ff >> { n176, n98, n68, i_8_, i_6_, i_7_ }; + assign n261 = 16'h0777 >> { n262, n81, n80, n38 }; + assign n262 = 4'h1 >> { i_4_, i_3_ }; + assign n263 = 64'h0000077707770777 >> { n34, n257, n36, n84, n37, n162 }; + assign n264 = 64'h0000800080008000 >> { n127, n49, n267, n269, n265, n266 }; + assign n265 = 16'h0777 >> { n35, n39, n82, n101 }; + assign n266 = 16'h0777 >> { n43, n72, n96, n88 }; + assign n267 = 16'h0ddd >> { n170, n46, n268, n37 }; + assign n268 = 64'h7ffffff7fffffff7 >> { i_4_, i_0_, i_3_, i_5_, i_2_, i_1_ }; + assign n269 = 16'h0777 >> { n36, n215, n32, n109 }; + assign n54 = 4'h8 >> { i_7_, i_6_ }; + assign n270 = 64'h8000800000008000 >> { i_4_, n273, n271, n274, n276, n272 }; + assign n271 = 16'h0777 >> { n152, n34, n96, n167 }; + assign n272 = 32'd125269879 >> { i_8_, i_6_, n162, n92, n46 }; + assign n273 = 8'h80 >> { n53, n135, n46 }; + assign n274 = 64'he4f5e6f7ecfdeeff >> { n275, n182, n183, i_8_, i_6_, i_7_ }; + assign n275 = 32'd8 >> { i_1_, i_4_, i_3_, i_0_, i_5_ }; + assign n276 = 64'h05550ddd07770fff >> { n84, n76, n98, n34, i_3_, n70 }; + assign o_4_ = 32'd2147483647 >> { n278, n538, n310, n316, n324 }; + assign n278 = 32'd2147483648 >> { n205, n279, n281, n290, n297 }; + assign n279 = 16'h0222 >> { n209, n49, n252, n280 }; + assign n55 = 8'h08 >> { i_1_, i_0_, i_2_ }; + assign n280 = 32'd125269879 >> { n46, n53, n135, n167, n34 }; + assign n281 = 64'h8000000000000000 >> { n282, n283, n284, n285, n286, n289 }; + assign n282 = 32'd2004289399 >> { i_3_, n199, n42, n62, n35 }; + assign n283 = 16'h0777 >> { n226, n174, n39, n46 }; + assign n284 = 16'h0777 >> { n149, n154, n75, n76 }; + assign n285 = 16'h0777 >> { n96, n180, n49, n98 }; + assign n286 = 32'd125269879 >> { n134, n288, n60, n115, n287 }; + assign n287 = 4'h8 >> { i_7_, i_8_ }; + assign n288 = 4'h2 >> { i_8_, i_7_ }; + assign n289 = 32'd125269879 >> { n56, n32, n46, n210, n37 }; + assign n56 = 8'h80 >> { i_4_, i_3_, i_5_ }; + assign n290 = 16'h8000 >> { n291, n292, n294, n295 }; + assign n291 = 16'h0777 >> { n96, n244, n107, n210 }; + assign n292 = 32'd1474289631 >> { n293, i_0_, n160, i_2_, i_1_ }; + assign n293 = 32'd128 >> { i_8_, i_6_, i_7_, i_4_, i_5_ }; + assign n294 = 16'h0777 >> { n34, n127, n96, n44 }; + assign n295 = 64'h0555077707770777 >> { n63, n75, n148, n296, n114, n137 }; + assign n296 = 64'h0000000000000002 >> { i_1_, i_2_, i_4_, i_3_, i_5_, i_0_ }; + assign n297 = 64'h8000000000000000 >> { n242, n298, n299, n300, n301, n302 }; + assign n298 = 16'h0777 >> { n152, n49, n32, n251 }; + assign n299 = 16'h0777 >> { n98, n34, n43, n146 }; + assign n57 = 64'h0000000800080008 >> { n72, n36, n67, n69, n58, n64 }; + assign n300 = 64'h0000077707770777 >> { n201, n35, n149, n247, n82, n72 }; + assign n301 = 64'hffdfffdfddddffdf >> { i_3_, n46, i_4_, n96, i_5_, n246 }; + assign n302 = 64'h0777777777777777 >> { n33, n134, n249, i_5_, n37, n244 }; + assign n303 = 16'h0222 >> { n99, n63, n223, n224 }; + assign n304 = 4'h8 >> { n56, n164 }; + assign n305 = 8'h80 >> { n60, n46, n131 }; + assign n306 = 32'd32768 >> { i_1_, i_0_, i_2_, i_7_, i_6_ }; + assign n307 = 32'd16843025 >> { n44, n162, n35, n234, n186 }; + assign n308 = 16'h5777 >> { n63, n80, n114, n134 }; + assign n309 = 64'h002a2a2a2a2a2a2a >> { n126, n246, n262, n37, n94, n271 }; + assign n58 = 8'h2a >> { n44, n63, n59 }; + assign n310 = 64'h8000000000000000 >> { n227, n264, n311, n313, n314, n315 }; + assign n311 = 64'h0001010100111111 >> { n49, n61, n296, n162, n312, n51 }; + assign n312 = 16'h88a8 >> { i_0_, n145, n251, i_2_ }; + assign n313 = 16'h0777 >> { n35, n92, n81, n75 }; + assign n314 = 64'h0000077707770777 >> { n34, n170, n114, n55, n178, n139 }; + assign n315 = 64'h1b5f3b7f9bdfbbff >> { n215, n103, n146, i_5_, i_3_, i_4_ }; + assign n316 = 64'h0000000080000000 >> { n233, n317, n319, n321, n322, n323 }; + assign n317 = 64'h0000077707770777 >> { n173, n175, n56, n318, n63, n44 }; + assign n318 = 64'h0000000000000080 >> { i_1_, i_0_, i_8_, i_7_, i_2_, i_6_ }; + assign n319 = 64'h0777077700000777 >> { n320, n56, n103, n36, n49, n99 }; + assign n59 = 32'd125269879 >> { n46, n60, n32, n62, n61 }; + assign n320 = 64'hfffffd7ffffffdff >> { i_6_, i_1_, i_7_, i_2_, i_8_, i_0_ }; + assign n321 = 16'h0777 >> { n183, n46, n80, n215 }; + assign n322 = 32'd2004317959 >> { i_7_, i_8_, n62, n138, n53 }; + assign n323 = 32'd5723991 >> { n244, n46, n170, n108, n49 }; + assign n324 = 64'h8000800000008000 >> { n327, n107, n325, n326, n198, n181 }; + assign n325 = 64'h0000077707770777 >> { n35, n94, n83, n75, n249, n39 }; + assign n326 = 32'd125269879 >> { n149, n107, n137, n135, n81 }; + assign n327 = 64'hfffff77ffffff7ff >> { i_3_, i_2_, i_0_, i_5_, i_1_, i_4_ }; + assign n328 = 64'h575757df57df57df >> { n137, n35, n318, n83, i_3_, n329 }; + assign n329 = 4'h2 >> { i_5_, i_4_ }; + assign n33 = 4'h2 >> { i_4_, i_3_ }; + assign n60 = 8'h02 >> { i_4_, i_5_, i_3_ }; + assign n330 = 32'd125269879 >> { n137, n82, n96, n170, n63 }; + assign n331 = 32'd125269879 >> { n37, n71, n42, n46, n88 }; + assign n332 = 4'h8 >> { n34, n167 }; + assign n333 = 4'h1 >> { i_4_, i_5_ }; + assign n334 = 64'hf8fcf9fdfafefbff >> { n210, n201, n108, i_7_, i_6_, i_8_ }; + assign n335 = 4'h8 >> { n46, n94 }; + assign n336 = 64'h0000000000008000 >> { n337, n338, n315, n163, n339, n340 }; + assign n337 = 4'h8 >> { n144, n147 }; + assign n338 = 4'h8 >> { n46, n153 }; + assign n339 = 16'h0777 >> { n98, n63, n37, n157 }; + assign n61 = 4'h1 >> { i_7_, i_6_ }; + assign n340 = 64'h0000077707770777 >> { n341, n238, n43, n83, n63, n68 }; + assign n341 = 32'd128 >> { i_5_, i_6_, i_7_, i_8_, i_4_ }; + assign n342 = 64'h1515153f153f153f >> { n149, n32, n108, n127, n49, n96 }; + assign n343 = 64'hb5f5b7f7bdfdbfff >> { n167, n152, n88, i_7_, i_8_, i_6_ }; + assign n344 = 16'h0777 >> { n148, n296, n34, n157 }; + assign n345 = 16'h0777 >> { n137, n346, n250, n251 }; + assign n346 = 32'd2 >> { i_3_, i_5_, i_7_, i_6_, i_8_ }; + assign n347 = 16'h0777 >> { n66, n34, n49, n139 }; + assign n348 = 16'h0777 >> { n115, n63, n37, n244 }; + assign n349 = 16'h7707 >> { n327, n107, n249, n39 }; + assign n62 = 64'h0000000080000000 >> { i_3_, i_0_, i_2_, i_4_, i_1_, i_5_ }; + assign n350 = 64'h8000000000000000 >> { n282, n351, n352, n353, n354, n355 }; + assign n351 = 16'h0777 >> { n49, n152, n63, n88 }; + assign n352 = 16'h0777 >> { n49, n170, n75, n306 }; + assign n353 = 32'd125269879 >> { n53, n82, n34, n94, n35 }; + assign n354 = 16'h0777 >> { n288, n244, n81, n70 }; + assign n355 = 64'h5d7f7f7f7f7f7f7f >> { i_8_, n262, n246, n176, i_6_, i_7_ }; + assign n356 = 8'h02 >> { i_3_, i_6_, i_5_ }; + assign n357 = 4'h8 >> { n63, n209 }; + assign n358 = 32'd526344 >> { n180, n249, n359, n283, n360 }; + assign n359 = 4'h8 >> { n35, n161 }; + assign n63 = 8'h02 >> { i_7_, i_8_, i_6_ }; + assign n360 = 16'h0777 >> { n122, n96, n82, n164 }; + assign n361 = 4'h8 >> { n279, n281 }; + assign n362 = 16'h0777 >> { n94, n46, n88, n148 }; + assign n363 = 16'h0777 >> { n72, n82, n287, n364 }; + assign n364 = 64'h0000000000000008 >> { i_0_, i_4_, i_3_, i_6_, i_5_, i_2_ }; + assign n365 = 64'h8000000000000000 >> { n117, n218, n219, n239, n366, n367 }; + assign n366 = 64'h97d7b7f79fdfbfff >> { n183, n94, n93, i_6_, i_7_, i_8_ }; + assign n367 = 16'h0777 >> { n35, n108, n65, n38 }; + assign n368 = 64'h8000000000000000 >> { n181, n325, n342, n343, n369, n370 }; + assign n369 = 64'h1515373f373f373f >> { n131, n49, n32, n176, n35, n43 }; + assign n64 = 16'h0777 >> { n38, n65, n63, n66 }; + assign n370 = 64'h0001010100ffffff >> { n96, n44, n46, n98, n139, n371 }; + assign n371 = 32'd8 >> { i_0_, i_2_, i_4_, i_1_, i_5_ }; + assign n372 = 32'd526344 >> { n111, n34, n373, n206, n374 }; + assign n373 = 4'h8 >> { n246, n341 }; + assign n374 = 32'd125269879 >> { n63, n134, n135, n210, n46 }; + assign n375 = 32'd1426894510 >> { n288, n143, n77, n95, n80 }; + assign n376 = 32'd2621472 >> { i_0_, i_4_, i_1_, i_5_, n37 }; + assign n377 = 4'h8 >> { n287, n147 }; + assign n378 = 32'd125269879 >> { n46, n55, n333, n161, n107 }; + assign n379 = 64'h8000000000000000 >> { n203, n347, n380, n381, n382, n383 }; + assign n65 = 4'h2 >> { i_4_, i_5_ }; + assign n380 = 32'd125269879 >> { n35, n82, n55, n153, n107 }; + assign n381 = 16'h0777 >> { n36, n154, n84, n43 }; + assign n382 = 16'h0777 >> { n49, n47, n82, n84 }; + assign n383 = 64'h7ffd7ffffffdffff >> { n131, n246, i_7_, i_8_, i_6_, n135 }; + assign n384 = 4'h8 >> { n49, n66 }; + assign n385 = 64'h0001010100111111 >> { n63, n49, n39, n176, n191, n386 }; + assign n386 = 4'h8 >> { n70, n318 }; + assign n387 = 64'hdddddddfddfdddff >> { n244, n188, n93, i_8_, i_7_, i_6_ }; + assign n388 = 32'd32768 >> { n389, n294, n295, n248, n390 }; + assign n389 = 4'h8 >> { n49, n152 }; + assign n66 = 64'h0000000000008000 >> { i_0_, i_4_, i_2_, i_1_, i_3_, i_5_ }; + assign n390 = 64'h0000077707770777 >> { n237, n356, n46, n176, n63, n161 }; + assign n391 = 64'h8000000000000000 >> { n535, n392, n394, n397, n401, n404 }; + assign n392 = 32'd2763306 >> { n164, n43, n81, n60, n393 }; + assign n393 = 16'h0777 >> { n35, n89, n37, n108 }; + assign n394 = 64'h0002020202020202 >> { n137, n34, n82, n395, n396, n236 }; + assign n395 = 16'h8000 >> { n42, n70, n35, n71 }; + assign n396 = 4'h8 >> { n288, n364 }; + assign n397 = 8'h02 >> { n398, n399, n400 }; + assign n398 = 4'h8 >> { n80, n81 }; + assign n399 = 4'h8 >> { n63, n161 }; + assign n67 = 4'h8 >> { n35, n68 }; + assign n400 = 64'h1515153f153f153f >> { n36, n55, n93, n244, n63, n107 }; + assign n401 = 64'h0001010101010101 >> { n35, n60, n53, n402, n403, n357 }; + assign n402 = 4'h8 >> { n46, n152 }; + assign n403 = 4'h8 >> { n107, n180 }; + assign n404 = 32'd2763306 >> { n94, n96, n63, n97, n113 }; + assign n405 = 32'd2147483648 >> { n290, n316, n406, n407, n411 }; + assign n406 = 16'h0222 >> { n180, n249, n359, n360 }; + assign n407 = 64'h0001010100111111 >> { n409, n84, n36, n287, n408, n410 }; + assign n408 = 4'h8 >> { n112, n238 }; + assign n409 = 8'h08 >> { i_0_, n173, n71 }; + assign n68 = 64'h0000000000000008 >> { i_2_, i_4_, i_3_, i_5_, i_1_, i_0_ }; + assign n410 = 8'h80 >> { n42, n71, n226 }; + assign n411 = 64'h1b5f3b7f9bdfbbff >> { n210, n87, n364, i_6_, i_8_, i_7_ }; + assign n412 = 16'h0777 >> { n188, n126, n130, n190 }; + assign n413 = 32'd125269879 >> { n333, n107, n250, n161, n34 }; + assign o_8_ = 32'd2147483647 >> { n278, n583, n391, n415, n426 }; + assign n415 = 64'h8000000000000000 >> { n416, n417, n419, n423, n424, n345 }; + assign n416 = 4'h8 >> { n369, n370 }; + assign n417 = 32'd707406506 >> { n287, i_6_, n131, n149, n418 }; + assign n418 = 32'd125269879 >> { n36, n148, n32, n87, n63 }; + assign n419 = 64'h0000008000800080 >> { n162, n63, n335, n422, n421, n420 }; + assign n69 = 16'h0080 >> { i_1_, n49, n71, n70 }; + assign n420 = 16'h0777 >> { n45, n43, n49, n157 }; + assign n421 = 32'd125269879 >> { n61, n82, n137, n296, n96 }; + assign n422 = 64'hbb9bbfdfbfdfbfdf >> { n53, n56, i_7_, n122, i_8_, i_6_ }; + assign n423 = 64'h0001010100555555 >> { n34, n63, n66, n88, n89, n241 }; + assign n424 = 64'h0015151515151515 >> { i_1_, n49, n82, n37, n98, n425 }; + assign n425 = 16'h0008 >> { i_7_, i_8_, n333, n111 }; + assign n426 = 64'h0000000080000000 >> { n431, n427, n428, n340, n430, n221 }; + assign n427 = 32'd3216971199 >> { i_6_, n188, n409, i_7_, i_8_ }; + assign n428 = 32'd35791394 >> { n137, n156, n126, n187, n429 }; + assign n429 = 16'h0777 >> { n49, n87, n75, n50 }; + assign n34 = 8'h08 >> { i_8_, i_7_, i_6_ }; + assign n70 = 4'h8 >> { i_4_, i_5_ }; + assign n430 = 16'h0777 >> { n46, n209, n81, n70 }; + assign n431 = 8'h08 >> { i_3_, i_2_, n160 }; + assign o_9_ = 64'h7fffffffffffffff >> { n522, n578, n559, n586, n442, n300 }; + assign n433 = 16'h0777 >> { n35, n44, n130, n190 }; + assign n434 = 32'd353703231 >> { n180, n210, n34, n108, n46 }; + assign n435 = 16'h0777 >> { n293, n436, n46, n209 }; + assign n436 = 8'h02 >> { i_1_, i_3_, i_2_ }; + assign n437 = 64'h7c7e7d7ffcfefdff >> { n98, n44, n87, i_7_, i_6_, i_8_ }; + assign n438 = 64'h0000000000000080 >> { i_2_, i_4_, i_6_, i_3_, i_5_, i_0_ }; + assign n439 = 64'h0000000000008000 >> { i_2_, i_3_, i_1_, i_4_, i_0_, i_6_ }; + assign n71 = 4'h8 >> { i_2_, i_3_ }; + assign n440 = 64'h0002002202020222 >> { n122, n46, n63, n244, n373, n380 }; + assign n441 = 32'd353703253 >> { n34, n63, n137, n82, n384 }; + assign n442 = 32'd2147483648 >> { n516, n443, n388, n407, n417 }; + assign n443 = 16'h8000 >> { n117, n119, n120, n121 }; + assign o_10_ = 64'h7fffffffffffffff >> { n519, n559, n445, n563, n451, n222 }; + assign n445 = 32'd8421504 >> { n114, n134, n383, n427, n326 }; + assign n446 = 16'h0777 >> { n61, n296, n34, n188 }; + assign n447 = 4'h8 >> { n82, n215 }; + assign n448 = 64'h0080800000800000 >> { i_6_, i_1_, i_4_, i_2_, i_5_, n287 }; + assign n449 = 4'h8 >> { n43, n247 }; + assign n72 = 64'h0000000000000080 >> { i_1_, i_7_, i_8_, i_0_, i_2_, i_6_ }; + assign n450 = 32'd125269879 >> { n131, n63, n60, n154, n82 }; + assign n451 = 64'h0000000000000080 >> { n305, n395, n454, n85, n452, n362 }; + assign n452 = 16'h76f6 >> { i_5_, n453, n33, n134 }; + assign n453 = 16'h0777 >> { n157, n96, n70, n318 }; + assign n454 = 4'h8 >> { n144, n364 }; + assign o_11_ = 8'h7f >> { n565, n589, n468 }; + assign n456 = 64'h8000000000000000 >> { n106, n110, n113, n344, n393, n457 }; + assign n457 = 64'h1515153f153f153f >> { n54, n137, n90, n60, n50, n43 }; + assign n458 = 32'd32768 >> { n177, n179, n459, n460, n462 }; + assign n459 = 64'hb4f6b5f7bcfebdff >> { n162, n89, n201, i_7_, i_8_, i_6_ }; + assign n73 = 8'h02 >> { n74, n77, n79 }; + assign n460 = 64'h0545054505451555 >> { n83, n103, n45, n33, i_5_, n461 }; + assign n461 = 8'h01 >> { i_1_, i_0_, i_2_ }; + assign n462 = 64'h0000077707770777 >> { n436, n463, n34, n161, n53, n78 }; + assign n463 = 32'd8 >> { i_4_, i_7_, i_8_, i_5_, i_6_ }; + assign n464 = 32'd1 >> { i_1_, i_0_, i_4_, i_3_, i_6_ }; + assign n465 = 16'h2aaa >> { n56, n32, n46, n466 }; + assign n466 = 16'h0777 >> { n96, n167, n82, n50 }; + assign n467 = 64'h002a2a2a2a2a2a2a >> { n55, n35, n36, n39, n46, n256 }; + assign n468 = 32'd134752776 >> { n77, n470, n149, n131, n591 }; + assign n469 = 32'd5723991 >> { n244, n96, n152, n99, n63 }; + assign n74 = 4'h8 >> { n75, n76 }; + assign n470 = 32'd125269879 >> { n46, n189, n55, n139, n178 }; + assign o_12_ = 64'hffff7fff7fff7fff >> { n101, n149, n480, n485, n589, n472 }; + assign n472 = 64'h8000000000000000 >> { n473, n570, n476, n478, n197, n308 }; + assign n473 = 8'h80 >> { n380, n381, n382 }; + assign n474 = 16'h0777 >> { n153, n35, n37, n210 }; + assign n475 = 64'h0d0f0d0f0c0e0d0f >> { i_8_, n244, n176, n461, i_7_, i_6_ }; + assign n476 = 32'd131586 >> { n161, n46, n91, n187, n477 }; + assign n477 = 32'd125269879 >> { n149, i_6_, n131, n209, n63 }; + assign n478 = 16'h0222 >> { n139, n61, n74, n479 }; + assign n479 = 16'h0777 >> { n50, n75, n37, n167 }; + assign n75 = 8'h02 >> { i_4_, i_3_, i_5_ }; + assign n480 = 16'h0008 >> { n67, n193, n481, n482 }; + assign n481 = 32'd1381653 >> { n46, n99, n82, n72, n359 }; + assign n482 = 32'd2 >> { n402, n332, n384, n483, n484 }; + assign n483 = 8'h02 >> { i_1_, i_0_, n346 }; + assign n484 = 64'h0000077707770777 >> { n50, n43, n37, n244, n80, n38 }; + assign n485 = 64'h0001010100111111 >> { n81, n46, n183, n82, n425, n217 }; + assign o_13_ = 64'hffffffff7fffffff >> { n449, n594, n591, n430, n472, n492 }; + assign n487 = 64'h1515153f153f153f >> { n32, n82, n47, n99, n34, n46 }; + assign n488 = 16'h0777 >> { n126, n127, n80, n101 }; + assign n489 = 16'h0777 >> { n35, n176, n63, n98 }; + assign n76 = 64'h0000000000000080 >> { i_2_, i_8_, i_6_, i_7_, i_0_, i_1_ }; + assign n490 = 64'h0777077700000777 >> { i_5_, n464, n83, n56, n63, n89 }; + assign n491 = 16'h0777 >> { n96, n201, n80, n50 }; + assign n492 = 64'h9dbfbfbfbfbfbfbf >> { i_0_, n46, n333, n160, i_1_, i_2_ }; + assign o_14_ = 64'hffffffffffff7fff >> { n377, n431, n594, n494, n565, n480 }; + assign n494 = 64'h5555555555555551 >> { i_7_, i_8_, i_1_, i_0_, n149, n41 }; + assign o_15_ = 32'd2147483647 >> { n496, n499, n501, n502, n503 }; + assign n496 = 32'd3629156416 >> { n476, i_6_, n497, i_7_, n188 }; + assign n497 = 32'd663691914 >> { n498, n137, n209, n82, n34 }; + assign n498 = 8'h15 >> { n190, n75, n464 }; + assign n499 = 64'h0008080800888888 >> { n107, n61, n210, n161, n500, n475 }; + assign n77 = 16'h0080 >> { i_2_, i_0_, n78, i_3_ }; + assign n500 = 16'h0777 >> { n46, n39, n54, n176 }; + assign n501 = 16'h1555 >> { n137, n82, n96, n359 }; + assign n502 = 16'h0777 >> { n34, n188, n107, n210 }; + assign n503 = 32'd712998783 >> { n176, i_7_, n43, n131, i_6_ }; + assign o_16_ = 8'h7f >> { n496, n505, n506 }; + assign n505 = 8'h15 >> { n108, n34, n305 }; + assign n506 = 16'h0222 >> { n94, n63, n461, n507 }; + assign n507 = 64'h0000077707770777 >> { n34, n188, n96, n122, n49, n108 }; + assign o_17_ = 32'd2147483647 >> { n501, n506, n477, n498, n509 }; + assign n509 = 16'h0777 >> { n88, n63, n37, n39 }; + assign n78 = 32'd32768 >> { i_6_, i_5_, i_7_, i_8_, i_4_ }; + assign o_18_ = 64'h7fffffffffffffff >> { n499, n505, n502, n503, n509, n511 }; + assign n511 = 64'hfffdfffdfffdfdfd >> { i_7_, i_8_, i_6_, i_1_, i_0_, n149 }; + assign n512 = 64'hfa8afa8afa8afa0a >> { n55, n53, n38, i_4_, n54, i_5_ }; + assign n513 = 64'h5f775f7f5f775fff >> { n34, n35, i_4_, n512, n32, i_3_ }; + assign n514 = 64'h0000008000800080 >> { n39, n37, n51, n40, n48, n513 }; + assign n515 = 64'h00011111000fffff >> { n34, n49, n92, n98, n93, n99 }; + assign n516 = 64'h0000800080008000 >> { n94, n63, n515, n95, n100, n102 }; + assign n517 = 64'h88888888f8888888 >> { i_1_, n35, i_3_, i_4_, n80, n148 }; + assign n518 = 64'h2a2a2a2a002a2a2a >> { i_2_, n517, i_0_, n45, n149, n142 }; + assign n519 = 64'h8000000000000000 >> { n518, n105, n116, n128, n141, n150 }; + assign n79 = 32'd5723991 >> { n83, n82, n84, n81, n80 }; + assign n520 = 64'heeeeffefffefffef >> { i_6_, n175, i_3_, n76, i_4_, i_5_ }; + assign n521 = 64'h0000000080000000 >> { n177, n171, n172, n520, n179, n181 }; + assign n522 = 64'h0080008000808080 >> { n35, n107, n176, n165, n168, n521 }; + assign n523 = 64'h0000000100010001 >> { n190, n36, n187, n191, n192, n193 }; + assign n524 = 64'h0057575757575757 >> { n46, n55, n189, n162, n98, n63 }; + assign n525 = 32'd2155872384 >> { n194, n32, n524, n184, n523 }; + assign n526 = 32'd353703231 >> { n210, n94, n49, n39, n96 }; + assign n527 = 32'd2147483648 >> { n526, n211, n212, n213, n214 }; + assign n528 = 64'h101010101010ba10 >> { i_3_, i_8_, n112, n114, i_0_, i_2_ }; + assign n529 = 64'h0000008000800080 >> { n528, i_1_, n234, n235, n236, n239 }; + assign n35 = 8'h02 >> { i_7_, i_6_, i_8_ }; + assign n80 = 8'h02 >> { i_3_, i_5_, i_4_ }; + assign n530 = 64'h0000000080000000 >> { n192, n529, n221, n222, n227, n231 }; + assign n531 = 64'h0001010100ffffff >> { n43, n60, n103, n101, n50, n190 }; + assign n532 = 64'h15bfbfbfbfbfbfbf >> { n49, i_0_, n130, n78, n71, i_1_ }; + assign n533 = 32'd526344 >> { n87, n35, n252, n248, n532 }; + assign n534 = 32'd371070751 >> { n99, n182, i_7_, i_8_, i_6_ }; + assign n535 = 64'h0880088008808880 >> { n201, n257, i_7_, n534, n256, n258 }; + assign n536 = 64'h0022022202220222 >> { n82, n53, n34, n188, n305, n308 }; + assign n537 = 64'h0000077707770777 >> { n75, n306, n68, n49, n43, n103 }; + assign n538 = 64'h0000000080000000 >> { n304, n537, n303, n536, n307, n309 }; + assign n539 = 64'h40404040ea404040 >> { i_6_, n134, n287, n190, i_4_, i_5_ }; + assign n81 = 64'h0000000000000080 >> { i_1_, i_2_, i_6_, i_7_, i_8_, i_0_ }; + assign n540 = 64'h0000000080000000 >> { n357, n546, n350, n159, n358, n527 }; + assign o_5_ = 64'h7fff7fffffff7fff >> { i_3_, n539, n73, n540, n578, n530 }; + assign n542 = 64'h7dfd7fff7fff7fff >> { n238, n333, n180, i_8_, i_6_, i_7_ }; + assign n543 = 32'd8 >> { n254, n332, n335, n334, n542 }; + assign n544 = 64'h2222000200020002 >> { i_5_, i_2_, i_1_, i_8_, i_4_, i_3_ }; + assign n545 = 64'hdddddfffdfffdfff >> { i_8_, n94, n544, i_0_, i_7_, i_6_ }; + assign n546 = 64'h8000000000000000 >> { n545, n344, n345, n347, n348, n349 }; + assign n547 = 64'h0222022222220222 >> { i_7_, i_8_, n170, i_6_, n377, n378 }; + assign o_6_ = 64'h7fffffffffffffff >> { n547, n361, n551, n581, n583, n538 }; + assign n549 = 64'h0002020200aaaaaa >> { n43, n107, n152, n146, n50, n155 }; + assign n82 = 8'h08 >> { i_3_, i_4_, i_5_ }; + assign n550 = 64'h8000000000000000 >> { n242, n243, n245, n272, n362, n363 }; + assign n551 = 32'd2147483648 >> { n549, n550, n365, n368, n372 }; + assign n552 = 64'h00220aaa02220aaa >> { n134, n34, n130, n76, n257, n274 }; + assign n553 = 64'h0002020200222222 >> { n35, n46, n161, n210, n384, n387 }; + assign n554 = 64'h0bbb0bbb01110bbb >> { i_8_, n244, n167, n37, n147, i_7_ }; + assign n555 = 64'h0000000000008000 >> { n207, n338, n172, n339, n412, n413 }; + assign o_7_ = 64'h7fffffffffffffff >> { n554, n555, n391, n405, n533, n551 }; + assign n557 = 64'hdd5dff7fff7fff7f >> { n42, n43, i_7_, n108, i_6_, i_8_ }; + assign n558 = 64'h0000000080000000 >> { n304, n387, n433, n434, n435, n437 }; + assign n559 = 64'h0000800080008000 >> { n84, n60, n64, n557, n558, n392 }; + assign n83 = 64'h0000000000000080 >> { i_1_, i_2_, i_7_, i_0_, i_8_, i_6_ }; + assign n560 = 64'h5700020057020202 >> { n244, n436, i_6_, n438, n439, i_8_ }; + assign n561 = 64'h3210101010101010 >> { i_4_, i_5_, n54, n148, i_3_, i_2_ }; + assign n562 = 64'h0022202202222222 >> { n138, n561, i_0_, i_1_, n449, n450 }; + assign n563 = 64'h0000000000008000 >> { n447, n448, n446, n562, n350, n543 }; + assign n564 = 64'h070f070f070f060e >> { i_8_, n240, n62, n447, i_6_, i_7_ }; + assign n565 = 64'h8000000000000000 >> { n564, n263, n419, n446, n456, n458 }; + assign n566 = 64'h0001010100555555 >> { n37, n76, n149, n93, n183, n464 }; + assign n567 = 32'd128 >> { n398, n399, n566, n151, n400 }; + assign n568 = 64'h0001010100ffffff >> { n49, n36, n76, n68, n161, n188 }; + assign n569 = 64'h068626a6068626ae >> { n97, n182, n127, i_8_, i_7_, i_6_ }; + assign n84 = 64'h0000000000000008 >> { i_1_, i_2_, i_7_, i_8_, i_0_, i_6_ }; + assign n570 = 64'h8000008080800080 >> { n87, n569, i_6_, n437, n474, n475 }; + assign n571 = 64'h0001010100555555 >> { n34, n36, n215, n170, n152, n207 }; + assign n572 = 64'h0000000080000000 >> { n389, n313, n487, n488, n489, n490 }; + assign n573 = 64'h0001010100555555 >> { n63, n54, n170, n89, n87, n241 }; + assign n574 = 64'h0000000080000000 >> { n254, n243, n245, n253, n242, n531 }; + assign n575 = 64'h0000800080008000 >> { n66, n37, n573, n171, n574, n533 }; + assign n576 = 64'h7577757f7577f5ff >> { n152, n39, n210, i_8_, i_6_, i_7_ }; + assign n577 = 64'h8000000000000000 >> { n576, n328, n330, n331, n342, n343 }; + assign n578 = 64'h0000800080008000 >> { n114, n32, n577, n270, n336, n543 }; + assign n579 = 64'hfddda888a888a888 >> { n32, n36, n189, n137, n162, i_7_ }; + assign n85 = 32'd2763306 >> { n90, n43, n50, n60, n86 }; + assign n580 = 64'h0000ab9b0000efdf >> { n115, n376, i_8_, n579, i_6_, i_7_ }; + assign n581 = 64'h0000800080008000 >> { n76, n56, n580, n375, n379, n388 }; + assign n582 = 64'h0555077707770777 >> { n35, n134, n83, n82, n72, n36 }; + assign n583 = 64'h0000800080008000 >> { n154, n75, n582, n385, n552, n553 }; + assign n584 = 64'h5555555515555555 >> { i_2_, i_4_, i_3_, n126, i_1_, n190 }; + assign n585 = 64'h00b900b000bb00b0 >> { i_7_, n584, n396, i_5_, i_8_, n560 }; + assign n586 = 64'h8000000000000000 >> { n585, n261, n286, n314, n440, n441 }; + assign n587 = 64'h0000077707770777 >> { n54, n153, n49, n87, n34, n66 }; + assign n588 = 64'h0008008808080888 >> { n188, n37, n63, n88, n265, n411 }; + assign n589 = 64'h8000000000000000 >> { n587, n588, n58, n465, n467, n567 }; + assign n86 = 64'h0001010100ffffff >> { n34, n49, n89, n88, n87, n44 }; + assign n590 = 64'hfcfefdfffdfffdff >> { n107, n137, n103, i_3_, i_5_, i_4_ }; + assign n591 = 64'h0000008000800080 >> { n127, n35, n185, n590, n469, n568 }; + assign n592 = 64'h0555077707770777 >> { n36, n134, n182, n107, n47, n35 }; + assign n593 = 64'h0008080808080808 >> { n137, n82, n63, n410, n450, n491 }; + assign n594 = 64'h0000000080000000 >> { n304, n593, n259, n592, n571, n572 }; + assign n87 = 64'h0000000000000080 >> { i_0_, i_3_, i_5_, i_4_, i_1_, i_2_ }; + assign n88 = 64'h0000000000000008 >> { i_0_, i_2_, i_4_, i_3_, i_1_, i_5_ }; + assign n89 = 64'h0000000000000080 >> { i_4_, i_3_, i_5_, i_1_, i_0_, i_2_ }; + assign n36 = 8'h08 >> { i_4_, i_3_, i_5_ }; + assign n90 = 64'h0000000000008000 >> { i_1_, i_8_, i_2_, i_7_, i_0_, i_6_ }; + assign n91 = 4'h8 >> { n49, n92 }; + assign n92 = 64'h0000000000000008 >> { i_0_, i_4_, i_3_, i_5_, i_2_, i_1_ }; + assign n93 = 64'h0000000080000000 >> { i_0_, i_1_, i_2_, i_4_, i_3_, i_5_ }; + assign n94 = 64'h0000000000008000 >> { i_0_, i_2_, i_1_, i_4_, i_3_, i_5_ }; + assign n95 = 32'd5723991 >> { n97, n61, n89, n87, n96 }; + assign n96 = 8'h80 >> { i_7_, i_8_, i_6_ }; + assign n97 = 64'h0000000080000000 >> { i_1_, i_0_, i_2_, i_4_, i_3_, i_5_ }; + assign n98 = 64'h0000000000000002 >> { i_0_, i_2_, i_4_, i_3_, i_5_, i_1_ }; + assign n99 = 64'h0000000000000080 >> { i_0_, i_4_, i_3_, i_1_, i_2_, i_5_ }; + assign n37 = 8'h08 >> { i_6_, i_8_, i_7_ }; + assign n100 = 16'h0777 >> { n101, n43, n37, n66 }; + assign n101 = 64'h0000000000008000 >> { i_1_, i_7_, i_2_, i_0_, i_8_, i_6_ }; + assign n102 = 16'h0777 >> { n60, n103, n63, n89 }; + assign n103 = 64'h0000000000000080 >> { i_1_, i_2_, i_8_, i_7_, i_0_, i_6_ }; + assign o_2_ = 32'd2147483647 >> { n519, n522, n525, n195, n204 }; + assign n105 = 8'h80 >> { n106, n110, n113 }; + assign n106 = 64'h0000077707770777 >> { n55, n109, n94, n49, n107, n108 }; + assign n107 = 8'h02 >> { i_8_, i_6_, i_7_ }; + assign n108 = 64'h0000000000000008 >> { i_0_, i_2_, i_3_, i_5_, i_1_, i_4_ }; + assign n109 = 32'd8 >> { i_5_, i_7_, i_6_, i_8_, i_4_ }; + assign n38 = 64'h0000000000000008 >> { i_1_, i_2_, i_8_, i_6_, i_0_, i_7_ }; + assign n110 = 16'h0777 >> { n111, n112, n76, n56 }; + assign n111 = 16'h0008 >> { i_1_, i_3_, i_2_, i_0_ }; + assign n112 = 16'h0008 >> { i_4_, i_6_, i_7_, i_5_ }; + assign n113 = 16'h0777 >> { n34, n115, n32, n114 }; + assign n114 = 64'h0000000000008000 >> { i_4_, i_7_, i_5_, i_3_, i_8_, i_6_ }; + assign n115 = 64'h0000000000000080 >> { i_2_, i_3_, i_5_, i_4_, i_0_, i_1_ }; + assign n116 = 64'h8000000000000000 >> { n117, n119, n120, n121, n123, n125 }; + assign n117 = 64'h7777777777770777 >> { i_2_, i_3_, n118, i_0_, n107, n87 }; + assign n118 = 32'd8 >> { i_4_, i_5_, i_8_, i_7_, i_6_ }; + assign n119 = 16'h0777 >> { n35, n47, n49, n87 }; + assign n39 = 64'h0000000000000080 >> { i_0_, i_2_, i_5_, i_4_, i_3_, i_1_ }; + assign n120 = 16'h0777 >> { n46, n89, n49, n47 }; + assign n121 = 64'h0000077707770777 >> { n61, n122, n60, n38, n50, n43 }; + assign n122 = 64'h0000000000000080 >> { i_1_, i_0_, i_3_, i_4_, i_2_, i_5_ }; + assign n123 = 64'hff7fff7ffd7dff7f >> { i_5_, n46, n124, i_2_, i_3_, i_1_ }; + assign n124 = 32'd4294967165 >> { i_5_, i_6_, i_7_, i_4_, i_8_ }; + assign n125 = 64'h0000077707770777 >> { n82, n84, n126, n127, n80, n101 }; + assign n126 = 4'h2 >> { i_6_, i_7_ }; + assign n127 = 64'h0000000000008000 >> { i_0_, i_5_, i_2_, i_4_, i_3_, i_1_ }; + assign n128 = 64'h0008000800000008 >> { n140, n53, n129, n132, n133, n136 }; + assign n129 = 32'd2860548224 >> { n60, n131, n130, n53, n126 }; + assign n28 = 1'h0; + assign o_0_ = n28; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act b/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act new file mode 100644 index 000000000..11b64eb3e --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act @@ -0,0 +1,1160 @@ +clock 0.487000 0.495600 +Pstart_0_ 0.501200 0.480800 +Pkey_255_ 0.495000 0.502000 +Pkey_254_ 0.504600 0.502200 +Pkey_253_ 0.504200 0.509600 +Pkey_252_ 0.503600 0.498600 +Pkey_251_ 0.503000 0.494600 +Pkey_250_ 0.501400 0.502600 +Pkey_249_ 0.481800 0.504400 +Pkey_248_ 0.493400 0.499800 +Pkey_247_ 0.494400 0.489200 +Pkey_246_ 0.513200 0.504400 +Pkey_245_ 0.514200 0.495600 +Pkey_244_ 0.509200 0.504600 +Pkey_243_ 0.510200 0.498400 +Pkey_242_ 0.507600 0.492800 +Pkey_241_ 0.495400 0.509400 +Pkey_240_ 0.492000 0.498400 +Pkey_239_ 0.498800 0.492400 +Pkey_238_ 0.510000 0.511000 +Pkey_237_ 0.499600 0.497000 +Pkey_236_ 0.502000 0.499400 +Pkey_235_ 0.506400 0.505000 +Pkey_234_ 0.504800 0.502000 +Pkey_233_ 0.489600 0.495600 +Pkey_232_ 0.493200 0.501400 +Pkey_231_ 0.501000 0.488600 +Pkey_230_ 0.501200 0.487200 +Pkey_229_ 0.499200 0.494000 +Pkey_228_ 0.491800 0.501600 +Pkey_227_ 0.493800 0.494400 +Pkey_226_ 0.500000 0.496600 +Pkey_225_ 0.501000 0.505400 +Pkey_224_ 0.499200 0.497000 +Pkey_223_ 0.496400 0.518200 +Pkey_222_ 0.489400 0.490600 +Pkey_221_ 0.504200 0.503400 +Pkey_220_ 0.492600 0.497400 +Pkey_219_ 0.521400 0.490800 +Pkey_218_ 0.496600 0.491800 +Pkey_217_ 0.504400 0.501200 +Pkey_216_ 0.507200 0.503000 +Pkey_215_ 0.495000 0.491600 +Pkey_214_ 0.507800 0.483200 +Pkey_213_ 0.511200 0.502200 +Pkey_212_ 0.491600 0.495600 +Pkey_211_ 0.516400 0.499000 +Pkey_210_ 0.494800 0.499000 +Pkey_209_ 0.513600 0.507000 +Pkey_208_ 0.503800 0.490000 +Pkey_207_ 0.506200 0.499600 +Pkey_206_ 0.515600 0.503200 +Pkey_205_ 0.496400 0.506400 +Pkey_204_ 0.515200 0.500200 +Pkey_203_ 0.489600 0.500200 +Pkey_202_ 0.510400 0.500200 +Pkey_201_ 0.499600 0.500600 +Pkey_200_ 0.500000 0.494200 +Pkey_199_ 0.498600 0.507200 +Pkey_198_ 0.504400 0.486600 +Pkey_197_ 0.496600 0.512200 +Pkey_196_ 0.501800 0.514600 +Pkey_195_ 0.499400 0.507400 +Pkey_194_ 0.494800 0.512800 +Pkey_193_ 0.490800 0.495000 +Pkey_192_ 0.513400 0.487000 +Pkey_191_ 0.509400 0.489400 +Pkey_190_ 0.500600 0.494400 +Pkey_189_ 0.507000 0.491200 +Pkey_188_ 0.494400 0.511400 +Pkey_187_ 0.497400 0.500600 +Pkey_186_ 0.494200 0.506200 +Pkey_185_ 0.499800 0.505600 +Pkey_184_ 0.490600 0.499200 +Pkey_183_ 0.495600 0.509800 +Pkey_182_ 0.502000 0.499200 +Pkey_181_ 0.491600 0.506000 +Pkey_180_ 0.494400 0.504400 +Pkey_179_ 0.501800 0.499200 +Pkey_178_ 0.501400 0.497200 +Pkey_177_ 0.511400 0.503400 +Pkey_176_ 0.496800 0.494600 +Pkey_175_ 0.497600 0.514600 +Pkey_174_ 0.512600 0.491600 +Pkey_173_ 0.500000 0.494000 +Pkey_172_ 0.493200 0.496000 +Pkey_171_ 0.505000 0.504000 +Pkey_170_ 0.494400 0.503200 +Pkey_169_ 0.510200 0.495000 +Pkey_168_ 0.497800 0.497400 +Pkey_167_ 0.492600 0.499000 +Pkey_166_ 0.498400 0.500600 +Pkey_165_ 0.504800 0.499600 +Pkey_164_ 0.501000 0.499400 +Pkey_163_ 0.509000 0.497000 +Pkey_162_ 0.513200 0.506800 +Pkey_161_ 0.494400 0.507600 +Pkey_160_ 0.491800 0.490000 +Pkey_159_ 0.509400 0.498200 +Pkey_158_ 0.485000 0.498200 +Pkey_157_ 0.496600 0.487800 +Pkey_156_ 0.506600 0.505600 +Pkey_155_ 0.506600 0.504000 +Pkey_154_ 0.494800 0.501400 +Pkey_153_ 0.503000 0.504400 +Pkey_152_ 0.494800 0.496000 +Pkey_151_ 0.502200 0.490800 +Pkey_150_ 0.493400 0.504000 +Pkey_149_ 0.513600 0.503400 +Pkey_148_ 0.502600 0.491400 +Pkey_147_ 0.505000 0.505200 +Pkey_146_ 0.505800 0.486400 +Pkey_145_ 0.497200 0.494800 +Pkey_144_ 0.506400 0.498200 +Pkey_143_ 0.492000 0.507400 +Pkey_142_ 0.498000 0.508400 +Pkey_141_ 0.491600 0.516800 +Pkey_140_ 0.511600 0.505400 +Pkey_139_ 0.507600 0.501800 +Pkey_138_ 0.485200 0.501800 +Pkey_137_ 0.504200 0.498200 +Pkey_136_ 0.499800 0.505200 +Pkey_135_ 0.510000 0.502400 +Pkey_134_ 0.498800 0.504000 +Pkey_133_ 0.502600 0.503400 +Pkey_132_ 0.500400 0.493400 +Pkey_131_ 0.519400 0.498400 +Pkey_130_ 0.498600 0.496000 +Pkey_129_ 0.504000 0.491000 +Pkey_128_ 0.510400 0.500000 +Pkey_127_ 0.487400 0.505800 +Pkey_126_ 0.496000 0.500600 +Pkey_125_ 0.501200 0.507200 +Pkey_124_ 0.498600 0.510800 +Pkey_123_ 0.506200 0.495600 +Pkey_122_ 0.497600 0.499400 +Pkey_121_ 0.492600 0.495000 +Pkey_120_ 0.505200 0.506200 +Pkey_119_ 0.502600 0.484600 +Pkey_118_ 0.502600 0.487600 +Pkey_117_ 0.494200 0.496600 +Pkey_116_ 0.508200 0.510400 +Pkey_115_ 0.495800 0.501800 +Pkey_114_ 0.494800 0.511800 +Pkey_113_ 0.496400 0.496000 +Pkey_112_ 0.503000 0.498600 +Pkey_111_ 0.509400 0.501200 +Pkey_110_ 0.504200 0.506200 +Pkey_109_ 0.505200 0.500800 +Pkey_108_ 0.508200 0.489200 +Pkey_107_ 0.495600 0.498800 +Pkey_106_ 0.498000 0.501000 +Pkey_105_ 0.510400 0.497000 +Pkey_104_ 0.500200 0.510200 +Pkey_103_ 0.517200 0.504000 +Pkey_102_ 0.492600 0.503000 +Pkey_101_ 0.493200 0.495000 +Pkey_100_ 0.498600 0.489400 +Pkey_99_ 0.496600 0.506800 +Pkey_98_ 0.496200 0.505000 +Pkey_97_ 0.497200 0.503800 +Pkey_96_ 0.490000 0.505000 +Pkey_95_ 0.504400 0.499600 +Pkey_94_ 0.504600 0.500400 +Pkey_93_ 0.499000 0.497200 +Pkey_92_ 0.493600 0.499000 +Pkey_91_ 0.513000 0.490600 +Pkey_90_ 0.492400 0.497600 +Pkey_89_ 0.500200 0.486400 +Pkey_88_ 0.502800 0.499000 +Pkey_87_ 0.504600 0.498600 +Pkey_86_ 0.505200 0.502000 +Pkey_85_ 0.494600 0.503200 +Pkey_84_ 0.482600 0.491200 +Pkey_83_ 0.504000 0.492000 +Pkey_82_ 0.494000 0.513200 +Pkey_81_ 0.517800 0.507400 +Pkey_80_ 0.509000 0.496200 +Pkey_79_ 0.497000 0.509800 +Pkey_78_ 0.498000 0.488200 +Pkey_77_ 0.490400 0.508000 +Pkey_76_ 0.493800 0.508600 +Pkey_75_ 0.505400 0.484400 +Pkey_74_ 0.491800 0.494800 +Pkey_73_ 0.504000 0.492000 +Pkey_72_ 0.499400 0.513200 +Pkey_71_ 0.496400 0.507000 +Pkey_70_ 0.507200 0.516600 +Pkey_69_ 0.499200 0.494400 +Pkey_68_ 0.503000 0.511400 +Pkey_67_ 0.505000 0.503000 +Pkey_66_ 0.500200 0.494400 +Pkey_65_ 0.507000 0.496200 +Pkey_64_ 0.499800 0.506600 +Pkey_63_ 0.500400 0.497000 +Pkey_62_ 0.501800 0.495800 +Pkey_61_ 0.499600 0.499200 +Pkey_60_ 0.501400 0.499200 +Pkey_59_ 0.503000 0.485200 +Pkey_58_ 0.504400 0.512200 +Pkey_57_ 0.504800 0.507200 +Pkey_56_ 0.500400 0.502400 +Pkey_55_ 0.491200 0.484600 +Pkey_54_ 0.506800 0.509400 +Pkey_53_ 0.496000 0.499000 +Pkey_52_ 0.506600 0.482600 +Pkey_51_ 0.505800 0.501800 +Pkey_50_ 0.489600 0.501400 +Pkey_49_ 0.498400 0.490200 +Pkey_48_ 0.488400 0.501600 +Pkey_47_ 0.493400 0.493200 +Pkey_46_ 0.500600 0.499800 +Pkey_45_ 0.505000 0.499400 +Pkey_44_ 0.510200 0.495400 +Pkey_43_ 0.490200 0.499800 +Pkey_42_ 0.511000 0.501800 +Pkey_41_ 0.512000 0.497200 +Pkey_40_ 0.501000 0.503400 +Pkey_39_ 0.502400 0.495600 +Pkey_38_ 0.492400 0.497200 +Pkey_37_ 0.490400 0.492600 +Pkey_36_ 0.492800 0.504200 +Pkey_35_ 0.501600 0.510000 +Pkey_34_ 0.496600 0.503600 +Pkey_33_ 0.499200 0.509200 +Pkey_32_ 0.493800 0.497200 +Pkey_31_ 0.500000 0.504200 +Pkey_30_ 0.488600 0.490600 +Pkey_29_ 0.493600 0.496200 +Pkey_28_ 0.500000 0.509400 +Pkey_27_ 0.507600 0.489400 +Pkey_26_ 0.488600 0.487200 +Pkey_25_ 0.497600 0.497800 +Pkey_24_ 0.505600 0.491600 +Pkey_23_ 0.505200 0.496200 +Pkey_22_ 0.499600 0.511200 +Pkey_21_ 0.495200 0.488000 +Pkey_20_ 0.493000 0.509400 +Pkey_19_ 0.502800 0.497200 +Pkey_18_ 0.490400 0.496800 +Pkey_17_ 0.495400 0.502600 +Pkey_16_ 0.488000 0.494400 +Pkey_15_ 0.492200 0.509800 +Pkey_14_ 0.495000 0.499200 +Pkey_13_ 0.490800 0.499400 +Pkey_12_ 0.502400 0.494200 +Pkey_11_ 0.485800 0.495400 +Pkey_10_ 0.491800 0.507600 +Pkey_9_ 0.495400 0.505200 +Pkey_8_ 0.494800 0.516200 +Pkey_7_ 0.506000 0.515400 +Pkey_6_ 0.481000 0.501000 +Pkey_5_ 0.497600 0.498800 +Pkey_4_ 0.498600 0.498800 +Pkey_3_ 0.511600 0.497600 +Pkey_2_ 0.503200 0.496200 +Pkey_1_ 0.503000 0.505800 +Pkey_0_ 0.508400 0.496800 +Pencrypt_0_ 0.501600 0.493200 +Pcount_3_ 0.494800 0.492200 +Pcount_2_ 0.500200 0.514000 +Pcount_1_ 0.491600 0.495000 +Pcount_0_ 0.518200 0.498200 +PKSi_190_ 0.420600 0.443600 +PKSi_189_ 0.433200 0.436200 +PKSi_188_ 0.440000 0.439400 +PKSi_186_ 0.438800 0.436800 +PKSi_185_ 0.437000 0.432200 +PKSi_184_ 0.448200 0.429000 +PKSi_183_ 0.436400 0.439200 +PKSi_182_ 0.431000 0.446400 +PKSi_180_ 0.427800 0.434200 +PKSi_179_ 0.425800 0.446800 +PKSi_178_ 0.436800 0.433800 +PKSi_177_ 0.435600 0.444400 +PKSi_176_ 0.435600 0.424800 +PKSi_175_ 0.427400 0.432600 +PKSi_174_ 0.442600 0.448400 +PKSi_173_ 0.431600 0.442600 +PKSi_172_ 0.419400 0.429000 +PKSi_171_ 0.433000 0.438800 +PKSi_170_ 0.418200 0.445400 +PKSi_169_ 0.434200 0.439600 +PKSi_167_ 0.422600 0.427000 +PKSi_166_ 0.435600 0.439800 +PKSi_165_ 0.427000 0.440400 +PKSi_164_ 0.432400 0.437600 +PKSi_163_ 0.426600 0.428800 +PKSi_162_ 0.435600 0.437800 +PKSi_161_ 0.430400 0.425200 +PKSi_160_ 0.425600 0.433800 +PKSi_159_ 0.436600 0.428800 +PKSi_158_ 0.425200 0.431800 +PKSi_157_ 0.445200 0.448800 +PKSi_156_ 0.428800 0.427400 +PKSi_155_ 0.433800 0.436800 +PKSi_154_ 0.416000 0.425000 +PKSi_153_ 0.439600 0.436000 +PKSi_152_ 0.430400 0.441400 +PKSi_151_ 0.425800 0.446200 +PKSi_150_ 0.437000 0.431400 +PKSi_149_ 0.436600 0.434200 +PKSi_148_ 0.424800 0.432800 +PKSi_147_ 0.419600 0.435800 +PKSi_146_ 0.426800 0.439200 +PKSi_145_ 0.429800 0.444000 +PKSi_144_ 0.434000 0.430200 +PKSi_142_ 0.436000 0.437200 +PKSi_141_ 0.433000 0.444000 +PKSi_140_ 0.433200 0.430400 +PKSi_138_ 0.425400 0.432600 +PKSi_137_ 0.447800 0.443600 +PKSi_136_ 0.441000 0.432600 +PKSi_135_ 0.439800 0.433400 +PKSi_134_ 0.435200 0.434600 +PKSi_133_ 0.420000 0.424600 +PKSi_132_ 0.433000 0.440000 +PKSi_131_ 0.419200 0.432200 +PKSi_130_ 0.431200 0.430600 +PKSi_129_ 0.433600 0.436200 +PKSi_128_ 0.430800 0.447000 +PKSi_127_ 0.428600 0.431800 +PKSi_126_ 0.431800 0.442600 +PKSi_125_ 0.435200 0.423000 +PKSi_124_ 0.429600 0.436000 +PKSi_123_ 0.429400 0.437200 +PKSi_122_ 0.429200 0.445200 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0.192770 +n1549_1 0.437400 0.015429 +n1550 0.747400 0.046221 +n1545 0.575000 0.192744 +n1552 0.444400 0.015274 +n1553_1 0.749600 0.046500 +n1509 0.562200 0.191717 +n1555 0.454400 0.014373 +n1556 0.755000 0.045403 +n1711 0.558000 0.192969 +n1558 0.457000 0.015093 +n1559 0.748600 0.045076 +n1517 0.579600 0.188320 +n1561_1 0.437800 0.016528 +n1562 0.740600 0.045149 +n1473 0.582600 0.186797 +n1564 0.435000 0.015735 +n1565_1 0.746200 0.045245 +n1505 0.573400 0.196092 +n1567 0.444000 0.014825 +n1568 0.752800 0.045697 +n1716 0.576000 0.192953 +n1570 0.443200 0.014801 +n1571 0.753400 0.045648 +n1553 0.582400 0.185004 +n1573_1 0.436800 0.015362 +n1574 0.746600 0.045603 +n1485 0.573000 0.187091 +n1576 0.446400 0.015177 +n1577_1 0.747400 0.046404 +n1557 0.574200 0.191526 +n1579 0.448200 0.015564 +n1580 0.745400 0.047756 +n1469 0.578200 0.190722 +n1582 0.437400 0.015528 +n1583 0.745600 0.047445 +n1501 0.570200 0.189482 +n1585_1 0.446600 0.014774 +n1586 0.751400 0.045812 +n1549 0.579600 0.188935 +n1588 0.436000 0.015926 +n1589_1 0.741400 0.046678 +n1513 0.569600 0.193088 +n1591 0.446800 0.014899 +n1592 0.752800 0.046569 +n1721 0.560400 0.196319 +n1594 0.454200 0.014437 +n1595 0.756000 0.045186 +n1489 0.574200 0.198215 +n1597_1 0.445000 0.015145 +n1598 0.750600 0.045524 +n1481 0.561400 0.196910 +n1600 0.455800 0.014597 +n1601_1 0.753400 0.046190 +n1521 0.582600 0.185871 +n1603 0.432800 0.015916 +n1604 0.740400 0.046807 +n1537 0.576400 0.189757 +n1606 0.442200 0.015323 +n1607 0.747400 0.046956 +n1533 0.563800 0.198171 +n1609_1 0.452400 0.014724 +n1610 0.754400 0.045469 +n1465 0.576200 0.192527 +n1612 0.442800 0.015485 +n1613_1 0.748000 0.046405 +n1541 0.577400 0.187637 +n1615 0.439000 0.015612 +n1616 0.743400 0.046753 +n1625 0.574000 0.192581 +n1618 0.445600 0.015247 +n1619 0.747800 0.046743 +n1573 0.569000 0.189695 +n1621_1 0.446600 0.015004 +n1622 0.748400 0.045562 +n1589 0.571000 0.190254 +n1624 0.449200 0.015421 +n1625_1 0.747000 0.045804 +n1726 0.574800 0.189119 +n1627 0.441800 0.015244 +n1628 0.747000 0.046657 +n1641 0.564600 0.191134 +n1630 0.453000 0.015390 +n1631 0.749400 0.046408 +n1605 0.573800 0.191015 +n1633_1 0.446000 0.014951 +n1634 0.754200 0.045752 +n1731 0.567400 0.070265 +n1636 0.742600 0.122569 +n1613 0.561400 0.197374 +n1638 0.456000 0.014972 +n1639 0.753000 0.044376 +n1569 0.565400 0.193717 +n1641_1 0.453000 0.014713 +n1642 0.756000 0.044894 +n1601 0.583800 0.184810 +n1644 0.434800 0.015695 +n1645_1 0.742400 0.046717 +n1736 0.566200 0.190550 +n1647 0.448600 0.015081 +n1648 0.747800 0.046198 +n1649 0.575200 0.192069 +n1650 0.445600 0.015098 +n1651 0.748000 0.045749 +n1581 0.564000 0.195130 +n1653_1 0.451400 0.014960 +n1654 0.751600 0.046803 +n1621 0.564200 0.189512 +n1656 0.450600 0.015152 +n1657_1 0.750800 0.046065 +n1653 0.569600 0.193921 +n1659 0.449800 0.015091 +n1660 0.752000 0.045455 +n1565 0.572600 0.187717 +n1662 0.445800 0.015293 +n1663 0.748800 0.045561 +n1597 0.567200 0.187144 +n1665 0.447200 0.014713 +n1666_1 0.754400 0.045902 +n1609 0.566000 0.194170 +n1668 0.451800 0.015140 +n1669 0.750200 0.046798 +n1741 0.569200 0.190104 +n1671_1 0.447800 0.015517 +n1672 0.747000 0.046310 +n1585 0.570800 0.193205 +n1674 0.445000 0.015495 +n1675 0.747800 0.047130 +n1577 0.567200 0.201173 +n1677 0.451800 0.014990 +n1678 0.753200 0.046453 +n1617 0.572400 0.190365 +n1680 0.446200 0.015115 +n1681_1 0.751200 0.044882 +n1633 0.574000 0.189398 +n1683 0.444400 0.015596 +n1684 0.745200 0.045497 +n1593 0.569000 0.189838 +n1686_1 0.448800 0.014796 +n1687 0.754800 0.045965 +n1629 0.560800 0.198271 +n1689 0.456600 0.015133 +n1690 0.751800 0.045698 +n1561 0.575400 0.191646 +n1692 0.441200 0.015430 +n1693 0.746800 0.045342 +n1637 0.569600 0.190796 +n1695 0.444400 0.015420 +n1696_1 0.745000 0.045274 +Pnew_count_3_ 0.497800 0.026111 +Pnew_count_2_ 0.498600 0.017359 +Pnew_count_1_ 0.490200 0.023081 +Pnew_count_0_ 0.486800 0.126955 +Pdata_ready_0_ 0.033800 0.000941 +n945 0.436400 0.163743 +n1703 0.627400 0.020733 +n1704 0.744800 0.046208 +n981 0.431600 0.162757 +n1706_1 0.634600 0.019661 +n1707 0.751600 0.045328 +n1746 0.430200 0.161762 +n1709 0.633600 0.019311 +n1710 0.749400 0.046564 +n937 0.437000 0.077527 +n1712 0.714200 0.104202 +n997 0.434200 0.163575 +n1714 0.630000 0.020886 +n1715 0.744600 0.047937 +n969_1 0.435600 0.158856 +n1717 0.636600 0.019559 +n1718 0.751400 0.047514 +n929 0.440000 0.165647 +n1720 0.627600 0.020283 +n1721_1 0.745600 0.046617 +n1751 0.425400 0.161603 +n1723 0.636400 0.019271 +n1724 0.753600 0.044836 +n957 0.425800 0.162871 +n1726_1 0.635800 0.019002 +n1727 0.753000 0.044900 +n985 0.419400 0.155726 +n1729 0.643200 0.018286 +n1730 0.758200 0.044934 +n933 0.438800 0.043785 +n1732 0.750000 0.055396 +n965 0.435600 0.163886 +n1734 0.629400 0.020710 +n1735 0.744200 0.047099 +n953 0.427800 0.157995 +n1737 0.640000 0.018903 +n1738 0.755400 0.046198 +n1755 0.433800 0.162280 +n1740 0.634000 0.018856 +n1741_1 0.754000 0.045710 +n1760 0.437000 0.165210 +n1743 0.627000 0.019768 +n1744 0.746600 0.046743 +n1765 0.431800 0.163141 +n1746_1 0.632200 0.020944 +n1747 0.743800 0.047319 +n973_1 0.427400 0.157658 +n1749 0.636600 0.019785 +n1750 0.749800 0.046332 +n949 0.431000 0.164113 +n1752 0.631000 0.020305 +n1753 0.748400 0.045925 +n1770 0.425600 0.160907 +n1755_1 0.632800 0.019475 +n1756 0.751400 0.047086 +n989 0.433000 0.165461 +n1758 0.629600 0.020318 +n1759 0.746800 0.047548 +n925 0.433200 0.161067 +n1761 0.631600 0.020100 +n1762 0.745600 0.046716 +n1775 0.441800 0.162973 +n1764 0.626600 0.020543 +n1765_1 0.743600 0.047536 +n941 0.448200 0.163837 +n1767 0.623800 0.020702 +n1768 0.740000 0.047778 +n961 0.436800 0.161474 +n1770_1 0.634200 0.020410 +n1771 0.747600 0.045690 +n1780 0.432200 0.161932 +n1773 0.631400 0.019885 +n1774 0.746800 0.045198 +n993 0.418200 0.159561 +n1776 0.638600 0.018903 +n1777 0.755200 0.046929 +n977 0.442600 0.168997 +n1779 0.621400 0.021791 +n1780_1 0.736800 0.047994 +n921_1 0.420600 0.160928 +n1782 0.638600 0.019015 +n1783 0.755000 0.047514 +n1784_1 0.819000 0.070408 +n1013 0.432400 0.059205 +n1786 0.820000 0.071062 +n1009 0.427000 0.140990 +n1788 0.821000 0.070845 +n1829 0.423000 0.142023 +n1790 0.682400 0.080926 +n1365 0.568000 0.105618 +n1792 0.674000 0.073421 +n1341 0.565200 0.109296 +n1794_1 0.676600 0.073510 +n1393 0.581600 0.119128 +n1796 0.675200 0.081805 +n1493 0.575600 0.107518 +n1798 0.677400 0.081034 +n1525 0.576200 0.107603 +n1800 0.678400 0.073385 +n1497 0.573000 0.117752 +n1802 0.680200 0.073167 +n1645 0.570000 0.105107 +PKSi_143_ 0.423000 0.182651 +PKSi_181_ 0.425200 0.190154 +PKSi_191_ 0.432200 0.186797 +PKSi_90_ 0.564200 0.245514 diff --git a/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif b/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif new file mode 100644 index 000000000..e702c04ae --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif @@ -0,0 +1,2803 @@ +# Benchmark "bigkey" written by ABC on Tue Mar 12 09:35:16 2019 +.model bigkey +.inputs clock Pstart_0_ Pkey_255_ Pkey_254_ Pkey_253_ Pkey_252_ Pkey_251_ \ + Pkey_250_ Pkey_249_ Pkey_248_ Pkey_247_ Pkey_246_ Pkey_245_ Pkey_244_ \ + Pkey_243_ Pkey_242_ Pkey_241_ Pkey_240_ Pkey_239_ Pkey_238_ Pkey_237_ \ + Pkey_236_ Pkey_235_ Pkey_234_ Pkey_233_ Pkey_232_ Pkey_231_ Pkey_230_ \ + Pkey_229_ Pkey_228_ Pkey_227_ Pkey_226_ Pkey_225_ Pkey_224_ Pkey_223_ \ + Pkey_222_ Pkey_221_ Pkey_220_ Pkey_219_ Pkey_218_ Pkey_217_ Pkey_216_ \ + Pkey_215_ Pkey_214_ Pkey_213_ Pkey_212_ Pkey_211_ Pkey_210_ Pkey_209_ \ + Pkey_208_ Pkey_207_ Pkey_206_ Pkey_205_ Pkey_204_ Pkey_203_ Pkey_202_ \ + Pkey_201_ Pkey_200_ Pkey_199_ Pkey_198_ Pkey_197_ Pkey_196_ Pkey_195_ \ + Pkey_194_ Pkey_193_ Pkey_192_ Pkey_191_ Pkey_190_ Pkey_189_ Pkey_188_ \ + Pkey_187_ Pkey_186_ Pkey_185_ Pkey_184_ Pkey_183_ Pkey_182_ Pkey_181_ \ + Pkey_180_ Pkey_179_ Pkey_178_ Pkey_177_ Pkey_176_ Pkey_175_ Pkey_174_ \ + Pkey_173_ Pkey_172_ Pkey_171_ Pkey_170_ Pkey_169_ Pkey_168_ Pkey_167_ \ + Pkey_166_ Pkey_165_ Pkey_164_ Pkey_163_ Pkey_162_ Pkey_161_ Pkey_160_ \ + Pkey_159_ Pkey_158_ Pkey_157_ Pkey_156_ Pkey_155_ Pkey_154_ Pkey_153_ \ + Pkey_152_ Pkey_151_ Pkey_150_ Pkey_149_ Pkey_148_ Pkey_147_ Pkey_146_ \ + Pkey_145_ Pkey_144_ Pkey_143_ Pkey_142_ Pkey_141_ Pkey_140_ Pkey_139_ \ + Pkey_138_ Pkey_137_ Pkey_136_ Pkey_135_ Pkey_134_ Pkey_133_ Pkey_132_ \ + Pkey_131_ Pkey_130_ Pkey_129_ Pkey_128_ Pkey_127_ Pkey_126_ Pkey_125_ \ + Pkey_124_ Pkey_123_ Pkey_122_ Pkey_121_ Pkey_120_ Pkey_119_ Pkey_118_ \ + Pkey_117_ Pkey_116_ Pkey_115_ Pkey_114_ Pkey_113_ Pkey_112_ Pkey_111_ \ + Pkey_110_ Pkey_109_ Pkey_108_ Pkey_107_ Pkey_106_ Pkey_105_ Pkey_104_ \ + Pkey_103_ Pkey_102_ Pkey_101_ Pkey_100_ Pkey_99_ Pkey_98_ Pkey_97_ \ + Pkey_96_ Pkey_95_ Pkey_94_ Pkey_93_ Pkey_92_ Pkey_91_ Pkey_90_ Pkey_89_ \ + Pkey_88_ Pkey_87_ Pkey_86_ Pkey_85_ Pkey_84_ Pkey_83_ Pkey_82_ Pkey_81_ \ + Pkey_80_ Pkey_79_ Pkey_78_ Pkey_77_ Pkey_76_ Pkey_75_ Pkey_74_ Pkey_73_ \ + Pkey_72_ Pkey_71_ Pkey_70_ Pkey_69_ Pkey_68_ Pkey_67_ Pkey_66_ Pkey_65_ \ + Pkey_64_ Pkey_63_ Pkey_62_ Pkey_61_ Pkey_60_ Pkey_59_ Pkey_58_ Pkey_57_ \ + Pkey_56_ Pkey_55_ Pkey_54_ Pkey_53_ Pkey_52_ Pkey_51_ Pkey_50_ Pkey_49_ \ + Pkey_48_ Pkey_47_ Pkey_46_ Pkey_45_ Pkey_44_ Pkey_43_ Pkey_42_ Pkey_41_ \ + Pkey_40_ Pkey_39_ Pkey_38_ Pkey_37_ Pkey_36_ Pkey_35_ Pkey_34_ Pkey_33_ \ + Pkey_32_ Pkey_31_ Pkey_30_ Pkey_29_ Pkey_28_ Pkey_27_ Pkey_26_ Pkey_25_ \ + Pkey_24_ Pkey_23_ Pkey_22_ Pkey_21_ Pkey_20_ Pkey_19_ Pkey_18_ Pkey_17_ \ + Pkey_16_ Pkey_15_ Pkey_14_ Pkey_13_ Pkey_12_ Pkey_11_ Pkey_10_ Pkey_9_ \ + Pkey_8_ Pkey_7_ Pkey_6_ Pkey_5_ Pkey_4_ Pkey_3_ Pkey_2_ Pkey_1_ Pkey_0_ \ + Pencrypt_0_ Pcount_3_ Pcount_2_ Pcount_1_ Pcount_0_ +.outputs Pnew_count_3_ Pnew_count_2_ Pnew_count_1_ Pnew_count_0_ \ + Pdata_ready_0_ PKSi_191_ PKSi_190_ PKSi_189_ PKSi_188_ PKSi_187_ PKSi_186_ \ + PKSi_185_ PKSi_184_ PKSi_183_ PKSi_182_ PKSi_181_ PKSi_180_ PKSi_179_ \ + PKSi_178_ PKSi_177_ PKSi_176_ PKSi_175_ PKSi_174_ PKSi_173_ PKSi_172_ \ + PKSi_171_ PKSi_170_ PKSi_169_ PKSi_168_ PKSi_167_ PKSi_166_ PKSi_165_ \ + PKSi_164_ PKSi_163_ PKSi_162_ PKSi_161_ PKSi_160_ PKSi_159_ PKSi_158_ \ + PKSi_157_ PKSi_156_ PKSi_155_ PKSi_154_ PKSi_153_ PKSi_152_ PKSi_151_ \ + PKSi_150_ PKSi_149_ PKSi_148_ PKSi_147_ PKSi_146_ PKSi_145_ PKSi_144_ \ + PKSi_143_ PKSi_142_ PKSi_141_ PKSi_140_ PKSi_139_ PKSi_138_ PKSi_137_ \ + PKSi_136_ PKSi_135_ PKSi_134_ PKSi_133_ PKSi_132_ PKSi_131_ PKSi_130_ \ + PKSi_129_ PKSi_128_ PKSi_127_ PKSi_126_ PKSi_125_ PKSi_124_ PKSi_123_ \ + PKSi_122_ PKSi_121_ PKSi_120_ PKSi_119_ PKSi_118_ PKSi_117_ PKSi_116_ \ + PKSi_115_ PKSi_114_ PKSi_113_ PKSi_112_ PKSi_111_ PKSi_110_ PKSi_109_ \ + PKSi_108_ PKSi_107_ PKSi_106_ PKSi_105_ PKSi_104_ PKSi_103_ PKSi_102_ \ + PKSi_101_ PKSi_100_ PKSi_99_ PKSi_98_ PKSi_97_ PKSi_96_ PKSi_95_ PKSi_94_ \ + PKSi_93_ PKSi_92_ PKSi_91_ PKSi_90_ PKSi_89_ PKSi_88_ PKSi_87_ PKSi_86_ \ + PKSi_85_ PKSi_84_ PKSi_83_ PKSi_82_ PKSi_81_ PKSi_80_ PKSi_79_ PKSi_78_ \ + PKSi_77_ PKSi_76_ PKSi_75_ PKSi_74_ PKSi_73_ PKSi_72_ PKSi_71_ PKSi_70_ \ + PKSi_69_ PKSi_68_ PKSi_67_ PKSi_66_ PKSi_65_ PKSi_64_ PKSi_63_ PKSi_62_ \ + PKSi_61_ PKSi_60_ PKSi_59_ PKSi_58_ PKSi_57_ PKSi_56_ PKSi_55_ PKSi_54_ \ + PKSi_53_ PKSi_52_ PKSi_51_ PKSi_50_ PKSi_49_ PKSi_48_ PKSi_47_ PKSi_46_ \ + PKSi_45_ PKSi_44_ PKSi_43_ PKSi_42_ PKSi_41_ PKSi_40_ PKSi_39_ PKSi_38_ \ + PKSi_37_ PKSi_36_ PKSi_35_ PKSi_34_ PKSi_33_ PKSi_32_ PKSi_31_ PKSi_30_ \ + PKSi_29_ PKSi_28_ PKSi_27_ PKSi_26_ PKSi_25_ PKSi_24_ PKSi_23_ PKSi_22_ \ + PKSi_21_ PKSi_20_ PKSi_19_ PKSi_18_ PKSi_17_ PKSi_16_ PKSi_15_ PKSi_14_ \ + PKSi_13_ PKSi_12_ PKSi_11_ PKSi_10_ PKSi_9_ PKSi_8_ PKSi_7_ PKSi_6_ \ + PKSi_5_ PKSi_4_ PKSi_3_ PKSi_2_ PKSi_1_ PKSi_0_ + +.latch n921_1 PKSi_190_ re clock 0 +.latch n925 PKSi_189_ re clock 0 +.latch n929 PKSi_188_ re clock 0 +.latch n933 PKSi_186_ re clock 0 +.latch n937 PKSi_185_ re clock 0 +.latch n941 PKSi_184_ re clock 0 +.latch n945 PKSi_183_ re clock 0 +.latch n949 PKSi_182_ re clock 0 +.latch n953 PKSi_180_ re clock 0 +.latch n957 PKSi_179_ re clock 0 +.latch n961 PKSi_178_ re clock 0 +.latch n965 PKSi_177_ re clock 0 +.latch n969_1 PKSi_176_ re clock 0 +.latch n973_1 PKSi_175_ re clock 0 +.latch n977 PKSi_174_ re clock 0 +.latch n981 PKSi_173_ re clock 0 +.latch n985 PKSi_172_ re clock 0 +.latch n989 PKSi_171_ re clock 0 +.latch n993 PKSi_170_ re clock 0 +.latch n997 PKSi_169_ re clock 0 +.latch n1001 PKSi_167_ re clock 0 +.latch n1005 PKSi_166_ re clock 0 +.latch n1009 PKSi_165_ re clock 0 +.latch n1013 PKSi_164_ re clock 0 +.latch n1017 PKSi_163_ re clock 0 +.latch n1021 PKSi_162_ re clock 0 +.latch n1025 PKSi_161_ re clock 0 +.latch n1029 PKSi_160_ re clock 0 +.latch n1033 PKSi_159_ re clock 0 +.latch n1037 PKSi_158_ re clock 0 +.latch n1041 PKSi_157_ re clock 0 +.latch n1045 PKSi_156_ re clock 0 +.latch n1049 PKSi_155_ re clock 0 +.latch n1053 PKSi_154_ re clock 0 +.latch n1057 PKSi_153_ re clock 0 +.latch n1061 PKSi_152_ re clock 0 +.latch n1065 PKSi_151_ re clock 0 +.latch n1069_1 PKSi_150_ re clock 0 +.latch n1073_1 PKSi_149_ re clock 0 +.latch n1077_1 PKSi_148_ re clock 0 +.latch n1081_1 PKSi_147_ re clock 0 +.latch n1085 PKSi_146_ re clock 0 +.latch n1089 PKSi_145_ re clock 0 +.latch n1093 PKSi_144_ re clock 0 +.latch n1097 PKSi_142_ re clock 0 +.latch n1101 PKSi_141_ re clock 0 +.latch n1105 PKSi_140_ re clock 0 +.latch n1109 PKSi_138_ re clock 0 +.latch n1113 PKSi_137_ re clock 0 +.latch n1117 PKSi_136_ re clock 0 +.latch n1121 PKSi_135_ re clock 0 +.latch n1125 PKSi_134_ re clock 0 +.latch n1129 PKSi_133_ re clock 0 +.latch n1133 PKSi_132_ re clock 0 +.latch n1137 PKSi_131_ re clock 0 +.latch n1141 PKSi_130_ re clock 0 +.latch n1145 PKSi_129_ re clock 0 +.latch n1149 PKSi_128_ re clock 0 +.latch n1153 PKSi_127_ re clock 0 +.latch n1157 PKSi_126_ re clock 0 +.latch n1161 PKSi_125_ re clock 0 +.latch n1165 PKSi_124_ re clock 0 +.latch n1169 PKSi_123_ re clock 0 +.latch n1173 PKSi_122_ re clock 0 +.latch n1177 PKSi_121_ re clock 0 +.latch n1181 PKSi_120_ re clock 0 +.latch n1185_1 PKSi_119_ re clock 0 +.latch n1189_1 PKSi_118_ re clock 0 +.latch n1193_1 PKSi_117_ re clock 0 +.latch n1197_1 PKSi_116_ re clock 0 +.latch n1201 PKSi_115_ re clock 0 +.latch n1205 PKSi_114_ re clock 0 +.latch n1209 PKSi_113_ re clock 0 +.latch n1213 PKSi_112_ re clock 0 +.latch n1217 PKSi_111_ re clock 0 +.latch n1221 PKSi_110_ re clock 0 +.latch n1225 PKSi_109_ re clock 0 +.latch n1229 PKSi_108_ re clock 0 +.latch n1233 PKSi_107_ re clock 0 +.latch n1237 PKSi_106_ re clock 0 +.latch n1241 PKSi_105_ re clock 0 +.latch n1245 PKSi_104_ re clock 0 +.latch n1249 PKSi_103_ re clock 0 +.latch n1253 PKSi_102_ re clock 0 +.latch n1257 PKSi_101_ re clock 0 +.latch n1261 PKSi_100_ re clock 0 +.latch n1265 PKSi_99_ re clock 0 +.latch n1269 PKSi_98_ re clock 0 +.latch n1273 PKSi_97_ re clock 0 +.latch n1277 PKSi_96_ re clock 0 +.latch n1281 PKSi_95_ re clock 0 +.latch n1285 PKSi_94_ re clock 0 +.latch n1289 PKSi_93_ re clock 0 +.latch n1293 PKSi_92_ re clock 0 +.latch n1297 PKSi_91_ re clock 0 +.latch n1301 PKSi_89_ re clock 0 +.latch n1305 PKSi_87_ re clock 0 +.latch n1309 PKSi_86_ re clock 0 +.latch n1313 PKSi_85_ re clock 0 +.latch n1317 PKSi_84_ re clock 0 +.latch n1321 PKSi_83_ re clock 0 +.latch n1325 PKSi_82_ re clock 0 +.latch n1329 PKSi_81_ re clock 0 +.latch n1333 PKSi_80_ re clock 0 +.latch n1337 PKSi_79_ re clock 0 +.latch n1341 PKSi_78_ re clock 0 +.latch n1345 PKSi_77_ re clock 0 +.latch n1349 PKSi_76_ re clock 0 +.latch n1353 PKSi_75_ re clock 0 +.latch n1357 PKSi_74_ re clock 0 +.latch n1361 PKSi_73_ re clock 0 +.latch n1365 PKSi_72_ re clock 0 +.latch n1369 PKSi_71_ re clock 0 +.latch n1373 PKSi_70_ re clock 0 +.latch n1377 PKSi_69_ re clock 0 +.latch n1381 PKSi_68_ re clock 0 +.latch n1385 PKSi_67_ re clock 0 +.latch n1389 PKSi_66_ re clock 0 +.latch n1393 PKSi_65_ re clock 0 +.latch n1397 PKSi_64_ re clock 0 +.latch n1401 PKSi_63_ re clock 0 +.latch n1405 PKSi_62_ re clock 0 +.latch n1409 PKSi_61_ re clock 0 +.latch n1413 PKSi_60_ re clock 0 +.latch n1417 PKSi_59_ re clock 0 +.latch n1421 PKSi_58_ re clock 0 +.latch n1425 PKSi_57_ re clock 0 +.latch n1429 PKSi_56_ re clock 0 +.latch n1433 PKSi_55_ re clock 0 +.latch n1437 PKSi_54_ re clock 0 +.latch n1441 PKSi_53_ re clock 0 +.latch n1445 PKSi_52_ re clock 0 +.latch n1449 PKSi_51_ re clock 0 +.latch n1453 PKSi_50_ re clock 0 +.latch n1457 PKSi_49_ re clock 0 +.latch n1461 PKSi_48_ re clock 0 +.latch n1465 PKSi_47_ re clock 0 +.latch n1469 PKSi_46_ re clock 0 +.latch n1473 PKSi_45_ re clock 0 +.latch n1477 PKSi_44_ re clock 0 +.latch n1481 PKSi_43_ re clock 0 +.latch n1485 PKSi_42_ re clock 0 +.latch n1489 PKSi_41_ re clock 0 +.latch n1493 PKSi_40_ re clock 0 +.latch n1497 PKSi_39_ re clock 0 +.latch n1501 PKSi_38_ re clock 0 +.latch n1505 PKSi_37_ re clock 0 +.latch n1509 PKSi_36_ re clock 0 +.latch n1513 PKSi_35_ re clock 0 +.latch n1517 PKSi_34_ re clock 0 +.latch n1521 PKSi_33_ re clock 0 +.latch n1525 PKSi_32_ re clock 0 +.latch n1529 PKSi_31_ re clock 0 +.latch n1533 PKSi_30_ re clock 0 +.latch n1537 PKSi_29_ re clock 0 +.latch n1541 PKSi_28_ re clock 0 +.latch n1545 PKSi_27_ re clock 0 +.latch n1549 PKSi_26_ re clock 0 +.latch n1553 PKSi_25_ re clock 0 +.latch n1557 PKSi_24_ re clock 0 +.latch n1561 PKSi_23_ re clock 0 +.latch n1565 PKSi_22_ re clock 0 +.latch n1569 PKSi_21_ re clock 0 +.latch n1573 PKSi_20_ re clock 0 +.latch n1577 PKSi_19_ re clock 0 +.latch n1581 PKSi_18_ re clock 0 +.latch n1585 PKSi_17_ re clock 0 +.latch n1589 PKSi_16_ re clock 0 +.latch n1593 PKSi_15_ re clock 0 +.latch n1597 PKSi_14_ re clock 0 +.latch n1601 PKSi_13_ re clock 0 +.latch n1605 PKSi_12_ re clock 0 +.latch n1609 PKSi_11_ re clock 0 +.latch n1613 PKSi_10_ re clock 0 +.latch n1617 PKSi_9_ re clock 0 +.latch n1621 PKSi_8_ re clock 0 +.latch n1625 PKSi_7_ re clock 0 +.latch n1629 PKSi_6_ re clock 0 +.latch n1633 PKSi_5_ re clock 0 +.latch n1637 PKSi_4_ re clock 0 +.latch n1641 PKSi_3_ re clock 0 +.latch n1645 PKSi_2_ re clock 0 +.latch n1649 PKSi_1_ re clock 0 +.latch n1653 PKSi_0_ re clock 0 +.latch n1657 PKSi_88_ re clock 0 +.latch n1661 N_N2737 re clock 0 +.latch n1666 N_N2741 re clock 0 +.latch n1671 N_N2746 re clock 0 +.latch n1676 N_N2749 re clock 0 +.latch n1681 N_N2757 re clock 0 +.latch n1686 N_N2770 re clock 0 +.latch n1691 N_N2774 re clock 0 +.latch n1696 N_N2779 re clock 0 +.latch n1701 N_N2789 re clock 0 +.latch n1706 N_N2802 re clock 0 +.latch n1711 N_N2806 re clock 0 +.latch n1716 N_N2811 re clock 0 +.latch n1721 N_N2821 re clock 0 +.latch n1726 N_N2834 re clock 0 +.latch n1731 N_N2838 re clock 0 +.latch n1736 N_N2843 re clock 0 +.latch n1741 N_N2853 re clock 0 +.latch n1746 N_N2865 re clock 0 +.latch n1751 PKSi_168_ re clock 0 +.latch n1755 N_N2877 re clock 0 +.latch n1760 N_N2879 re clock 0 +.latch n1765 N_N2881 re clock 0 +.latch n1770 N_N2885 re clock 0 +.latch n1775 N_N2889 re clock 0 +.latch n1780 PKSi_187_ re clock 0 +.latch n1784 N_N2899 re clock 0 +.latch n1789 N_N2909 re clock 0 +.latch n1794 N_N2917 re clock 0 +.latch n1799_1 N_N2921 re clock 0 +.latch n1804 N_N2931 re clock 0 +.latch n1809 N_N2943 re clock 0 +.latch n1814 N_N2945 re clock 0 +.latch n1819 N_N2950 re clock 0 +.latch n1824 N_N2954 re clock 0 +.latch n1829 PKSi_139_ re clock 0 +.latch n1833_1 N_N2964 re clock 0 +.latch n1838 N_N2976 re clock 0 +.latch n1843 N_N2982 re clock 0 +.latch n1848 N_N2986 re clock 0 + +.names n1136 PKSi_55_ n1141_1 PKSi_159_ n1033 +0--- 1 +-111 1 +.names n1140 PKSi_159_ PKSi_55_ n1139 n1137_1 n1138 n1136 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pencrypt_0_ Pcount_1_ Pcount_2_ Pcount_3_ Pcount_0_ Pstart_0_ \ + n1137_1 +100000 1 +111010 1 +111100 1 +.names Pcount_1_ Pstart_0_ Pencrypt_0_ Pcount_3_ Pcount_0_ Pcount_2_ n1138 +000--1 1 +100--0 1 +-000-1 1 +-00110 1 +-00-01 1 +.names Pcount_2_ Pcount_1_ Pstart_0_ Pencrypt_0_ Pcount_3_ Pcount_0_ n1139 +00000- 1 +0000-0 1 +110011 1 +.names Pstart_0_ Pencrypt_0_ Pkey_131_ Pkey_254_ n1140 +101- 0 +11-1 0 +.names Pencrypt_0_ Pcount_1_ Pcount_2_ Pcount_3_ Pcount_0_ Pstart_0_ \ + n1141_1 +10000- 0 +11101- 0 +11110- 0 +-----1 0 +.names n1143 PKSi_68_ n1141_1 PKSi_149_ n1073_1 +0--- 1 +-111 1 +.names n1144 PKSi_149_ PKSi_68_ n1139 n1137_1 n1138 n1143 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_131_ Pkey_139_ n1144 +10-1 0 +111- 0 +.names n1146 N_N2899 n1141_1 PKSi_64_ n1784 +0--- 1 +-111 1 +.names n1147 PKSi_64_ N_N2899 n1139 n1137_1 n1138 n1146 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_139_ Pkey_147_ n1147 +10-1 0 +111- 0 +.names n1149_1 N_N2770 n1141_1 PKSi_161_ n1025 +0--- 1 +-111 1 +.names n1150 PKSi_161_ N_N2770 n1139 n1137_1 n1138 n1149_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_147_ Pkey_155_ n1150 +10-1 0 +111- 0 +.names n1152 PKSi_51_ n1141_1 PKSi_145_ n1089 +0--- 1 +-111 1 +.names n1153_1 PKSi_145_ PKSi_51_ n1139 n1137_1 n1138 n1152 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_155_ Pkey_132_ n1153_1 +10-1 0 +111- 0 +.names n1155 PKSi_60_ n1141_1 PKSi_152_ n1061 +0--- 1 +-111 1 +.names n1156 PKSi_152_ PKSi_60_ n1139 n1137_1 n1138 n1155 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_132_ Pkey_140_ n1156 +10-1 0 +111- 0 +.names Pstart_0_ Pencrypt_0_ n1157_1 +10 1 +.names Pstart_0_ Pencrypt_0_ n1158 +11 1 +.names n1160 PKSi_58_ n1141_1 PKSi_157_ n1041 +0--- 1 +-111 1 +.names n1161_1 PKSi_157_ PKSi_58_ n1139 n1137_1 n1138 n1160 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_148_ Pkey_156_ n1161_1 +10-1 0 +111- 0 +.names n1163 PKSi_69_ n1141_1 PKSi_155_ n1049 +0--- 1 +-111 1 +.names n1164 PKSi_155_ PKSi_69_ n1139 n1137_1 n1138 n1163 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_156_ Pkey_164_ n1164 +10-1 0 +111- 0 +.names n1166 PKSi_148_ PKSi_61_ n1139 n1137_1 n1141_1 n1077_1 +100--- 0 +10-00- 0 +1110-0 0 +1-000- 0 +.names Pstart_0_ Pencrypt_0_ n1138 n1167 Pkey_164_ Pkey_172_ n1166 +10---1 0 +11--1- 0 +--11-- 0 +.names PKSi_148_ PKSi_61_ n1167 +00 1 +.names n1169_1 Pkey_180_ n1157_1 PKSi_162_ N_N2779 n1141_1 n1021 +0----- 1 +-11--- 1 +---111 1 +.names n1170 PKSi_162_ N_N2779 n1139 n1137_1 n1138 n1169_1 +000--0 1 +0110-- 1 +01-00- 1 +0-100- 1 +.names Pkey_172_ Pstart_0_ Pencrypt_0_ n1170 +111 1 +.names n1172 N_N2909 n1141_1 PKSi_49_ n1789 +0--- 1 +-111 1 +.names n1173_1 PKSi_49_ N_N2909 n1139 n1137_1 n1138 n1172 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_180_ Pkey_188_ n1173_1 +10-1 0 +111- 0 +.names n1175 PKSi_66_ n1141_1 PKSi_156_ n1045 +0--- 1 +-111 1 +.names n1176 PKSi_156_ PKSi_66_ n1139 n1137_1 n1138 n1175 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_188_ Pkey_133_ n1176 +10-1 0 +111- 0 +.names n1178 PKSi_56_ n1141_1 PKSi_153_ n1057 +0--- 1 +-111 1 +.names n1179 PKSi_153_ PKSi_56_ n1139 n1137_1 n1138 n1178 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_133_ Pkey_141_ n1179 +10-1 0 +111- 0 +.names n1181_1 PKSi_48_ n1141_1 PKSi_163_ n1017 +0--- 1 +-111 1 +.names n1182 PKSi_163_ PKSi_48_ n1139 n1137_1 n1138 n1181_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_141_ Pkey_149_ n1182 +10-1 0 +111- 0 +.names n1184 PKSi_70_ n1141_1 PKSi_144_ n1093 +0--- 1 +-111 1 +.names n1185 PKSi_144_ PKSi_70_ n1139 n1137_1 n1138 n1184 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_149_ Pkey_157_ n1185 +10-1 0 +111- 0 +.names n1187 PKSi_62_ n1141_1 PKSi_151_ n1065 +0--- 1 +-111 1 +.names n1188 PKSi_151_ PKSi_62_ n1139 n1137_1 n1138 n1187 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_157_ Pkey_165_ n1188 +10-1 0 +111- 0 +.names n1190 PKSi_50_ n1141_1 PKSi_158_ n1037 +0--- 1 +-111 1 +.names n1191 PKSi_158_ PKSi_50_ n1139 n1137_1 n1138 n1190 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_165_ Pkey_173_ n1191 +10-1 0 +111- 0 +.names n1193 N_N2917 n1141_1 PKSi_59_ n1794 +0--- 1 +-111 1 +.names n1194 PKSi_59_ N_N2917 n1139 n1137_1 n1138 n1193 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_173_ Pkey_181_ n1194 +10-1 0 +111- 0 +.names n1196 N_N2789 n1141_1 PKSi_147_ n1081_1 +0--- 1 +-111 1 +.names n1197 PKSi_147_ N_N2789 n1139 n1137_1 n1138 n1196 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_181_ Pkey_189_ n1197 +10-1 0 +111- 0 +.names n1199 N_N2921 n1141_1 PKSi_67_ n1799_1 +0--- 1 +-111 1 +.names n1200 PKSi_67_ N_N2921 n1139 n1137_1 n1138 n1199 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_134_ Pkey_142_ n1200 +10-1 0 +111- 0 +.names n1202 PKSi_57_ n1141_1 PKSi_160_ n1029 +0--- 1 +-111 1 +.names n1203 PKSi_160_ PKSi_57_ n1139 n1137_1 n1138 n1202 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_142_ Pkey_150_ n1203 +10-1 0 +111- 0 +.names n1205_1 PKSi_53_ n1141_1 PKSi_154_ n1053 +0--- 1 +-111 1 +.names n1206 PKSi_154_ PKSi_53_ n1139 n1137_1 n1138 n1205_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_150_ Pkey_158_ n1206 +10-1 0 +111- 0 +.names n1208 PKSi_63_ n1141_1 PKSi_167_ n1001 +0--- 1 +-111 1 +.names n1209_1 PKSi_167_ PKSi_63_ n1139 n1137_1 n1138 n1208 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_158_ Pkey_166_ n1209_1 +10-1 0 +111- 0 +.names n1211 PKSi_54_ n1141_1 PKSi_146_ n1085 +0--- 1 +-111 1 +.names n1212 PKSi_146_ PKSi_54_ n1139 n1137_1 n1138 n1211 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_166_ Pkey_174_ n1212 +10-1 0 +111- 0 +.names n1214 PKSi_71_ n1141_1 PKSi_150_ n1069_1 +0--- 1 +-111 1 +.names n1215 PKSi_150_ PKSi_71_ n1139 n1137_1 n1138 n1214 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_174_ Pkey_182_ n1215 +10-1 0 +111- 0 +.names n1217_1 PKSi_52_ n1141_1 PKSi_166_ n1005 +0--- 1 +-111 1 +.names n1218 PKSi_166_ PKSi_52_ n1139 n1137_1 n1138 n1217_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_182_ Pkey_190_ n1218 +10-1 0 +111- 0 +.names n1220 PKSi_31_ n1141_1 PKSi_135_ n1121 +0--- 1 +-111 1 +.names n1221_1 PKSi_135_ PKSi_31_ n1139 n1137_1 n1138 n1220 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_190_ Pkey_67_ n1221_1 +10-1 0 +111- 0 +.names n1223 PKSi_44_ n1141_1 PKSi_125_ n1161 +0--- 1 +-111 1 +.names n1224 PKSi_125_ PKSi_44_ n1139 n1137_1 n1138 n1223 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_67_ Pkey_75_ n1224 +10-1 0 +111- 0 +.names n1226 N_N2931 n1141_1 PKSi_40_ n1804 +0--- 1 +-111 1 +.names n1227 PKSi_40_ N_N2931 n1139 n1137_1 n1138 n1226 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_75_ Pkey_83_ n1227 +10-1 0 +111- 0 +.names n1229_1 N_N2802 n1141_1 PKSi_137_ n1113 +0--- 1 +-111 1 +.names n1230 PKSi_137_ N_N2802 n1139 n1137_1 n1138 n1229_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_83_ Pkey_91_ n1230 +10-1 0 +111- 0 +.names n1232 PKSi_27_ n1141_1 PKSi_121_ n1177 +0--- 1 +-111 1 +.names n1233_1 PKSi_121_ PKSi_27_ n1139 n1137_1 n1138 n1232 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_91_ Pkey_68_ n1233_1 +10-1 0 +111- 0 +.names n1235 PKSi_36_ n1141_1 PKSi_128_ n1149 +0--- 1 +-111 1 +.names n1236 PKSi_128_ PKSi_36_ n1139 n1137_1 n1138 n1235 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_68_ Pkey_76_ n1236 +10-1 0 +111- 0 +.names n1238 N_N2806 n1141_1 PKSi_140_ n1105 +0--- 1 +-111 1 +.names n1239 PKSi_140_ N_N2806 n1139 n1137_1 n1138 n1238 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_76_ Pkey_84_ n1239 +10-1 0 +111- 0 +.names n1241_1 PKSi_34_ n1141_1 PKSi_133_ n1129 +0--- 1 +-111 1 +.names n1242 PKSi_133_ PKSi_34_ n1139 n1137_1 n1138 n1241_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_84_ Pkey_92_ n1242 +10-1 0 +111- 0 +.names n1244 PKSi_45_ n1141_1 PKSi_131_ n1137 +0--- 1 +-111 1 +.names n1245_1 PKSi_131_ PKSi_45_ n1139 n1137_1 n1138 n1244 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_92_ Pkey_100_ n1245_1 +10-1 0 +111- 0 +.names n1248 n1247 PKSi_124_ PKSi_37_ n1137_1 n1141_1 n1165 +1000-- 0 +100-0- 0 +1011-0 0 +10-00- 0 +.names Pkey_44_ n1157_1 n1247 +11 1 +.names PKSi_124_ PKSi_37_ n1139 n1158 Pkey_100_ n1138 n1248 +00---1 0 +1-1--- 0 +-11--- 0 +---11- 0 +.names n1250 Pkey_116_ n1157_1 PKSi_138_ N_N2811 n1141_1 n1109 +0----- 1 +-11--- 1 +---111 1 +.names n1251 PKSi_138_ N_N2811 n1139 n1137_1 n1138 n1250 +000--0 1 +0110-- 1 +01-00- 1 +0-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_44_ n1251 +111 1 +.names n1253_1 PKSi_25_ n1141_1 PKSi_129_ n1145 +0--- 1 +-111 1 +.names n1254 PKSi_129_ PKSi_25_ n1139 n1137_1 n1138 n1253_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_116_ Pkey_124_ n1254 +10-1 0 +111- 0 +.names n1256 PKSi_42_ n1141_1 PKSi_132_ n1133 +0--- 1 +-111 1 +.names n1257_1 PKSi_132_ PKSi_42_ n1139 n1137_1 n1138 n1256 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_124_ Pkey_69_ n1257_1 +10-1 0 +111- 0 +.names n1259 N_N2943 n1141_1 PKSi_32_ n1809 +0--- 1 +-111 1 +.names n1260 PKSi_32_ N_N2943 n1139 n1137_1 n1138 n1259 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_69_ Pkey_77_ n1260 +10-1 0 +111- 0 +.names n1262 N_N2945 n1141_1 PKSi_24_ n1814 +0--- 1 +-111 1 +.names n1263 PKSi_24_ N_N2945 n1139 n1137_1 n1138 n1262 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_77_ Pkey_85_ n1263 +10-1 0 +111- 0 +.names n1265_1 PKSi_46_ n1141_1 PKSi_120_ n1181 +0--- 1 +-111 1 +.names n1266 PKSi_120_ PKSi_46_ n1139 n1137_1 n1138 n1265_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_85_ Pkey_93_ n1266 +10-1 0 +111- 0 +.names n1268 PKSi_38_ n1141_1 PKSi_127_ n1153 +0--- 1 +-111 1 +.names n1269_1 PKSi_127_ PKSi_38_ n1139 n1137_1 n1138 n1268 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_93_ Pkey_101_ n1269_1 +10-1 0 +111- 0 +.names n1271 PKSi_26_ n1141_1 PKSi_134_ n1125 +0--- 1 +-111 1 +.names n1272 PKSi_134_ PKSi_26_ n1139 n1137_1 n1138 n1271 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_101_ Pkey_109_ n1272 +10-1 0 +111- 0 +.names n1274 N_N2950 n1141_1 PKSi_35_ n1819 +0--- 1 +-111 1 +.names n1275 PKSi_35_ N_N2950 n1139 n1137_1 n1138 n1274 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_109_ Pkey_117_ n1275 +10-1 0 +111- 0 +.names n1277_1 N_N2821 n1141_1 PKSi_123_ n1169 +0--- 1 +-111 1 +.names n1278 PKSi_123_ N_N2821 n1139 n1137_1 n1138 n1277_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_117_ Pkey_125_ n1278 +10-1 0 +111- 0 +.names n1280 PKSi_41_ n1141_1 PKSi_141_ n1101 +0--- 1 +-111 1 +.names n1281_1 PKSi_141_ PKSi_41_ n1139 n1137_1 n1138 n1280 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_125_ Pkey_70_ n1281_1 +10-1 0 +111- 0 +.names n1283 N_N2954 n1141_1 PKSi_43_ n1824 +0--- 1 +-111 1 +.names n1284 PKSi_43_ N_N2954 n1139 n1137_1 n1138 n1283 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_70_ Pkey_78_ n1284 +10-1 0 +111- 0 +.names n1286 PKSi_33_ n1141_1 PKSi_136_ n1117 +0--- 1 +-111 1 +.names n1287 PKSi_136_ PKSi_33_ n1139 n1137_1 n1138 n1286 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_78_ Pkey_86_ n1287 +10-1 0 +111- 0 +.names n1289_1 PKSi_29_ n1141_1 PKSi_130_ n1141 +0--- 1 +-111 1 +.names n1290 PKSi_130_ PKSi_29_ n1139 n1137_1 n1138 n1289_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_86_ Pkey_94_ n1290 +10-1 0 +111- 0 +.names n1292 PKSi_30_ n1141_1 PKSi_122_ n1173 +0--- 1 +-111 1 +.names n1293_1 PKSi_122_ PKSi_30_ n1139 n1137_1 n1138 n1292 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_102_ Pkey_110_ n1293_1 +10-1 0 +111- 0 +.names n1295 PKSi_47_ n1141_1 PKSi_126_ n1157 +0--- 1 +-111 1 +.names n1296 PKSi_126_ PKSi_47_ n1139 n1137_1 n1138 n1295 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_110_ Pkey_118_ n1296 +10-1 0 +111- 0 +.names n1298 PKSi_28_ n1141_1 PKSi_142_ n1097 +0--- 1 +-111 1 +.names n1299 PKSi_142_ PKSi_28_ n1139 n1137_1 n1138 n1298 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_118_ Pkey_126_ n1299 +10-1 0 +111- 0 +.names n1301_1 PKSi_7_ n1141_1 PKSi_111_ n1217 +0--- 1 +-111 1 +.names n1302 PKSi_111_ PKSi_7_ n1139 n1137_1 n1138 n1301_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_126_ Pkey_3_ n1302 +10-1 0 +111- 0 +.names n1304 PKSi_20_ n1141_1 PKSi_101_ n1257 +0--- 1 +-111 1 +.names n1305_1 PKSi_101_ PKSi_20_ n1139 n1137_1 n1138 n1304 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_3_ Pkey_11_ n1305_1 +10-1 0 +111- 0 +.names n1307 N_N2964 n1141_1 PKSi_16_ n1833_1 +0--- 1 +-111 1 +.names n1308 PKSi_16_ N_N2964 n1139 n1137_1 n1138 n1307 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_11_ Pkey_19_ n1308 +10-1 0 +111- 0 +.names n1310 N_N2834 n1141_1 PKSi_113_ n1209 +0--- 1 +-111 1 +.names n1311 PKSi_113_ N_N2834 n1139 n1137_1 n1138 n1310 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_19_ Pkey_27_ n1311 +10-1 0 +111- 0 +.names n1313_1 PKSi_3_ n1141_1 PKSi_97_ n1273 +0--- 1 +-111 1 +.names n1314 PKSi_97_ PKSi_3_ n1139 n1137_1 n1138 n1313_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_27_ Pkey_4_ n1314 +10-1 0 +111- 0 +.names n1316 PKSi_12_ n1141_1 PKSi_104_ n1245 +0--- 1 +-111 1 +.names n1317_1 PKSi_104_ PKSi_12_ n1139 n1137_1 n1138 n1316 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_4_ Pkey_12_ n1317_1 +10-1 0 +111- 0 +.names n1319 PKSi_116_ N_N2838 n1139 n1137_1 n1141_1 n1197_1 +100--- 0 +10-00- 0 +1110-0 0 +1-000- 0 +.names Pstart_0_ Pencrypt_0_ n1138 n1320 Pkey_12_ Pkey_20_ n1319 +10---1 0 +11--1- 0 +--11-- 0 +.names PKSi_116_ N_N2838 n1320 +00 1 +.names n1322 PKSi_10_ n1141_1 PKSi_109_ n1225 +0--- 1 +-111 1 +.names n1323 PKSi_109_ PKSi_10_ n1139 n1137_1 n1138 n1322 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_20_ Pkey_28_ n1323 +10-1 0 +111- 0 +.names n1325_1 PKSi_21_ n1141_1 PKSi_107_ n1233 +0--- 1 +-111 1 +.names n1326 PKSi_107_ PKSi_21_ n1139 n1137_1 n1138 n1325_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_28_ Pkey_36_ n1326 +10-1 0 +111- 0 +.names n1328 n1247 PKSi_100_ PKSi_13_ n1137_1 n1141_1 n1261 +1000-- 0 +100-0- 0 +1011-0 0 +10-00- 0 +.names PKSi_100_ PKSi_13_ n1139 n1158 Pkey_36_ n1138 n1328 +00---1 0 +1-1--- 0 +-11--- 0 +---11- 0 +.names n1330 n1251 PKSi_114_ N_N2843 n1137_1 n1138 n1205 +1000-0 0 +1011-- 0 +101-0- 0 +10-10- 0 +.names PKSi_114_ N_N2843 n1139 n1157_1 Pkey_52_ n1141_1 n1330 +11---1 0 +1-1--- 0 +-11--- 0 +---11- 0 +.names n1332 PKSi_1_ n1141_1 PKSi_105_ n1241 +0--- 1 +-111 1 +.names n1333_1 PKSi_105_ PKSi_1_ n1139 n1137_1 n1138 n1332 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_52_ Pkey_60_ n1333_1 +10-1 0 +111- 0 +.names n1335 PKSi_18_ n1141_1 PKSi_108_ n1229 +0--- 1 +-111 1 +.names n1336 PKSi_108_ PKSi_18_ n1139 n1137_1 n1138 n1335 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_60_ Pkey_5_ n1336 +10-1 0 +111- 0 +.names n1338 N_N2976 n1141_1 PKSi_8_ n1838 +0--- 1 +-111 1 +.names n1339 PKSi_8_ N_N2976 n1139 n1137_1 n1138 n1338 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_5_ Pkey_13_ n1339 +10-1 0 +111- 0 +.names n1341_1 PKSi_0_ n1141_1 PKSi_115_ n1201 +0--- 1 +-111 1 +.names n1342 PKSi_115_ PKSi_0_ n1139 n1137_1 n1138 n1341_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_13_ Pkey_21_ n1342 +10-1 0 +111- 0 +.names n1344 PKSi_22_ n1141_1 PKSi_96_ n1277 +0--- 1 +-111 1 +.names n1345_1 PKSi_96_ PKSi_22_ n1139 n1137_1 n1138 n1344 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_21_ Pkey_29_ n1345_1 +10-1 0 +111- 0 +.names n1347 PKSi_14_ n1141_1 PKSi_103_ n1249 +0--- 1 +-111 1 +.names n1348 PKSi_103_ PKSi_14_ n1139 n1137_1 n1138 n1347 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_29_ Pkey_37_ n1348 +10-1 0 +111- 0 +.names n1350 PKSi_2_ n1141_1 PKSi_110_ n1221 +0--- 1 +-111 1 +.names n1351 PKSi_110_ PKSi_2_ n1139 n1137_1 n1138 n1350 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_37_ Pkey_45_ n1351 +10-1 0 +111- 0 +.names n1353_1 N_N2982 n1141_1 PKSi_11_ n1843 +0--- 1 +-111 1 +.names n1354 PKSi_11_ N_N2982 n1139 n1137_1 n1138 n1353_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_45_ Pkey_53_ n1354 +10-1 0 +111- 0 +.names n1356 N_N2853 n1141_1 PKSi_99_ n1265 +0--- 1 +-111 1 +.names n1357_1 PKSi_99_ N_N2853 n1139 n1137_1 n1138 n1356 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_53_ Pkey_61_ n1357_1 +10-1 0 +111- 0 +.names n1359 PKSi_17_ n1141_1 PKSi_117_ n1193_1 +0--- 1 +-111 1 +.names n1360 PKSi_117_ PKSi_17_ n1139 n1137_1 n1138 n1359 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_61_ Pkey_6_ n1360 +10-1 0 +111- 0 +.names n1362 N_N2986 n1141_1 PKSi_19_ n1848 +0--- 1 +-111 1 +.names n1363 PKSi_19_ N_N2986 n1139 n1137_1 n1138 n1362 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_6_ Pkey_14_ n1363 +10-1 0 +111- 0 +.names n1365_1 PKSi_9_ n1141_1 PKSi_112_ n1213 +0--- 1 +-111 1 +.names n1366 PKSi_112_ PKSi_9_ n1139 n1137_1 n1138 n1365_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_14_ Pkey_22_ n1366 +10-1 0 +111- 0 +.names n1368 PKSi_5_ n1141_1 PKSi_106_ n1237 +0--- 1 +-111 1 +.names n1369_1 PKSi_106_ PKSi_5_ n1139 n1137_1 n1138 n1368 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_22_ Pkey_30_ n1369_1 +10-1 0 +111- 0 +.names n1371 PKSi_15_ n1141_1 PKSi_119_ n1185_1 +0--- 1 +-111 1 +.names n1372 PKSi_119_ PKSi_15_ n1139 n1137_1 n1138 n1371 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_30_ Pkey_38_ n1372 +10-1 0 +111- 0 +.names n1374 PKSi_6_ n1141_1 PKSi_98_ n1269 +0--- 1 +-111 1 +.names n1375 PKSi_98_ PKSi_6_ n1139 n1137_1 n1138 n1374 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_38_ Pkey_46_ n1375 +10-1 0 +111- 0 +.names n1377_1 PKSi_23_ n1141_1 PKSi_102_ n1253 +0--- 1 +-111 1 +.names n1378 PKSi_102_ PKSi_23_ n1139 n1137_1 n1138 n1377_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_46_ Pkey_54_ n1378 +10-1 0 +111- 0 +.names n1380 PKSi_4_ n1141_1 PKSi_118_ n1189_1 +0--- 1 +-111 1 +.names n1381_1 PKSi_118_ PKSi_4_ n1139 n1137_1 n1138 n1380 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_54_ Pkey_62_ n1381_1 +10-1 0 +111- 0 +.names n1383 PKSi_183_ PKSi_79_ n1386 n1337 +0--- 1 +-110 1 +.names n1385_1 PKSi_183_ PKSi_79_ n1138 n1384 n1139 n1383 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pcount_2_ Pcount_1_ Pcount_3_ Pcount_0_ Pencrypt_0_ Pstart_0_ n1384 +0000-- 0 +1101-- 0 +1110-- 0 +----0- 0 +-----1 0 +.names Pstart_0_ Pencrypt_0_ Pkey_56_ Pkey_227_ n1385_1 +10-1 0 +111- 0 +.names Pstart_0_ Pcount_1_ Pcount_2_ Pcount_3_ Pcount_0_ Pencrypt_0_ n1386 +00000- 0 +01101- 0 +01110- 0 +0----0 0 +.names n1388 PKSi_173_ PKSi_92_ n1386 n1293 +0--- 1 +-110 1 +.names n1389_1 PKSi_173_ PKSi_92_ n1138 n1384 n1139 n1388 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_227_ Pkey_235_ n1389_1 +10-1 0 +111- 0 +.names n1391 PKSi_88_ N_N2865 n1386 n1657 +0--- 1 +-110 1 +.names n1392 PKSi_88_ N_N2865 n1138 n1384 n1139 n1391 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_235_ Pkey_243_ n1392 +10-1 0 +111- 0 +.names n1394 PKSi_185_ N_N2737 n1138 n1384 n1386 n1661 +100--- 0 +10-00- 0 +1110-1 0 +1-000- 0 +.names Pstart_0_ Pencrypt_0_ n1139 n1395 Pkey_243_ Pkey_251_ n1394 +10---1 0 +11--1- 0 +--11-- 0 +.names PKSi_185_ N_N2737 n1395 +00 1 +.names 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0 +111- 0 +.names n1706_1 PKSi_92_ n1141_1 PKSi_173_ n981 +0--- 1 +-111 1 +.names n1707 PKSi_173_ PKSi_92_ n1139 n1137_1 n1138 n1706_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_195_ Pkey_203_ n1707 +10-1 0 +111- 0 +.names n1709 N_N2865 n1141_1 PKSi_88_ n1746 +0--- 1 +-111 1 +.names n1710 PKSi_88_ N_N2865 n1139 n1137_1 n1138 n1709 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_203_ Pkey_211_ n1710 +10-1 0 +111- 0 +.names n1712 PKSi_185_ N_N2737 n1139 n1137_1 n1141_1 n937 +100--- 0 +10-00- 0 +1110-0 0 +1-000- 0 +.names Pstart_0_ Pencrypt_0_ n1138 n1395 Pkey_211_ Pkey_219_ n1712 +10---1 0 +11--1- 0 +--11-- 0 +.names n1714 PKSi_75_ n1141_1 PKSi_169_ n997 +0--- 1 +-111 1 +.names n1715 PKSi_169_ PKSi_75_ n1139 n1137_1 n1138 n1714 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_219_ Pkey_196_ n1715 +10-1 0 +111- 0 +.names n1717 PKSi_84_ n1141_1 PKSi_176_ n969_1 +0--- 1 +-111 1 +.names n1718 PKSi_176_ PKSi_84_ n1139 n1137_1 n1138 n1717 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_196_ Pkey_204_ n1718 +10-1 0 +111- 0 +.names n1720 N_N2741 n1141_1 PKSi_188_ n929 +0--- 1 +-111 1 +.names n1721_1 PKSi_188_ N_N2741 n1139 n1137_1 n1138 n1720 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_204_ Pkey_212_ n1721_1 +10-1 0 +111- 0 +.names n1723 PKSi_82_ n1141_1 PKSi_168_ n1751 +0--- 1 +-111 1 +.names n1724 PKSi_168_ PKSi_82_ n1139 n1137_1 n1138 n1723 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_212_ Pkey_220_ n1724 +10-1 0 +111- 0 +.names n1726_1 PKSi_93_ n1141_1 PKSi_179_ n957 +0--- 1 +-111 1 +.names n1727 PKSi_179_ PKSi_93_ n1139 n1137_1 n1138 n1726_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_220_ Pkey_228_ n1727 +10-1 0 +111- 0 +.names n1729 PKSi_85_ n1141_1 PKSi_172_ n985 +0--- 1 +-111 1 +.names n1730 PKSi_172_ PKSi_85_ n1139 n1137_1 n1138 n1729 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_228_ Pkey_172_ n1730 +10-1 0 +111- 0 +.names n1732 n1170 PKSi_186_ N_N2746 n1137_1 n1138 n933 +1000-0 0 +1011-- 0 +101-0- 0 +10-10- 0 +.names PKSi_186_ N_N2746 n1139 n1157_1 Pkey_244_ n1141_1 n1732 +11---1 0 +1-1--- 0 +-11--- 0 +---11- 0 +.names n1734 PKSi_73_ n1141_1 PKSi_177_ n965 +0--- 1 +-111 1 +.names n1735 PKSi_177_ PKSi_73_ n1139 n1137_1 n1138 n1734 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_244_ Pkey_252_ n1735 +10-1 0 +111- 0 +.names n1737 N_N2749 n1141_1 PKSi_180_ n953 +0--- 1 +-111 1 +.names n1738 PKSi_180_ N_N2749 n1139 n1137_1 n1138 n1737 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_252_ Pkey_197_ n1738 +10-1 0 +111- 0 +.names n1740 N_N2877 n1141_1 PKSi_80_ n1755 +0--- 1 +-111 1 +.names n1741_1 PKSi_80_ N_N2877 n1139 n1137_1 n1138 n1740 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_197_ Pkey_205_ n1741_1 +10-1 0 +111- 0 +.names n1743 N_N2879 n1141_1 PKSi_72_ n1760 +0--- 1 +-111 1 +.names n1744 PKSi_72_ N_N2879 n1139 n1137_1 n1138 n1743 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_205_ Pkey_213_ n1744 +10-1 0 +111- 0 +.names n1746_1 N_N2881 n1141_1 PKSi_94_ n1765 +0--- 1 +-111 1 +.names n1747 PKSi_94_ N_N2881 n1139 n1137_1 n1138 n1746_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_213_ Pkey_221_ n1747 +10-1 0 +111- 0 +.names n1749 PKSi_86_ n1141_1 PKSi_175_ n973_1 +0--- 1 +-111 1 +.names n1750 PKSi_175_ PKSi_86_ n1139 n1137_1 n1138 n1749 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_221_ Pkey_229_ n1750 +10-1 0 +111- 0 +.names n1752 PKSi_74_ n1141_1 PKSi_182_ n949 +0--- 1 +-111 1 +.names n1753 PKSi_182_ PKSi_74_ n1139 n1137_1 n1138 n1752 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_229_ Pkey_237_ n1753 +10-1 0 +111- 0 +.names n1755_1 N_N2885 n1141_1 PKSi_83_ n1770 +0--- 1 +-111 1 +.names n1756 PKSi_83_ N_N2885 n1139 n1137_1 n1138 n1755_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_237_ Pkey_245_ n1756 +10-1 0 +111- 0 +.names n1758 N_N2757 n1141_1 PKSi_171_ n989 +0--- 1 +-111 1 +.names n1759 PKSi_171_ N_N2757 n1139 n1137_1 n1138 n1758 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_245_ Pkey_253_ n1759 +10-1 0 +111- 0 +.names n1761 PKSi_89_ n1141_1 PKSi_189_ n925 +0--- 1 +-111 1 +.names n1762 PKSi_189_ PKSi_89_ n1139 n1137_1 n1138 n1761 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_253_ Pkey_198_ n1762 +10-1 0 +111- 0 +.names n1764 N_N2889 n1141_1 PKSi_91_ n1775 +0--- 1 +-111 1 +.names n1765_1 PKSi_91_ N_N2889 n1139 n1137_1 n1138 n1764 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_198_ Pkey_206_ n1765_1 +10-1 0 +111- 0 +.names n1767 PKSi_81_ n1141_1 PKSi_184_ n941 +0--- 1 +-111 1 +.names n1768 PKSi_184_ PKSi_81_ n1139 n1137_1 n1138 n1767 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_206_ Pkey_214_ n1768 +10-1 0 +111- 0 +.names n1770_1 PKSi_77_ n1141_1 PKSi_178_ n961 +0--- 1 +-111 1 +.names n1771 PKSi_178_ PKSi_77_ n1139 n1137_1 n1138 n1770_1 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_214_ Pkey_222_ n1771 +10-1 0 +111- 0 +.names n1773 PKSi_87_ n1141_1 PKSi_187_ n1780 +0--- 1 +-111 1 +.names n1774 PKSi_187_ PKSi_87_ n1139 n1137_1 n1138 n1773 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_222_ Pkey_230_ n1774 +10-1 0 +111- 0 +.names n1776 PKSi_78_ n1141_1 PKSi_170_ n993 +0--- 1 +-111 1 +.names n1777 PKSi_170_ PKSi_78_ n1139 n1137_1 n1138 n1776 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_230_ Pkey_238_ n1777 +10-1 0 +111- 0 +.names n1779 PKSi_95_ n1141_1 PKSi_174_ n977 +0--- 1 +-111 1 +.names n1780_1 PKSi_174_ PKSi_95_ n1139 n1137_1 n1138 n1779 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_238_ Pkey_246_ n1780_1 +10-1 0 +111- 0 +.names n1782 PKSi_76_ n1141_1 PKSi_190_ n921_1 +0--- 1 +-111 1 +.names n1783 PKSi_190_ PKSi_76_ n1139 n1137_1 n1138 n1782 +100--0 1 +1110-- 1 +11-00- 1 +1-100- 1 +.names Pstart_0_ Pencrypt_0_ Pkey_246_ Pkey_254_ n1783 +10-1 0 +111- 0 +.names PKSi_164_ N_N2774 n1139 n1137_1 n1138 n1141_1 n1784_1 +00--0- 1 +0100-- 1 +1000-- 1 +110--0 1 +.names n1784_1 Pkey_140_ n1158 Pkey_148_ n1157_1 n1013 +0---- 1 +-11-- 1 +---11 1 +.names PKSi_165_ PKSi_65_ n1139 n1137_1 n1138 n1141_1 n1786 +00--0- 1 +0100-- 1 +1000-- 1 +110--0 1 +.names Pstart_0_ Pencrypt_0_ n1786 Pkey_189_ Pkey_134_ n1009 +10--1 1 +11-1- 1 +--0-- 1 +.names PKSi_139_ PKSi_39_ n1139 n1137_1 n1138 n1141_1 n1788 +00--0- 1 +0100-- 1 +1000-- 1 +110--0 1 +.names Pstart_0_ Pencrypt_0_ n1788 Pkey_94_ Pkey_102_ n1829 +10--1 1 +11-1- 1 +--0-- 1 +.names PKSi_72_ N_N2879 n1138 n1384 n1139 n1386 n1790 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names n1790 Pkey_201_ n1158 Pkey_209_ n1157_1 n1365 +0---- 1 +-11-- 1 +---11 1 +.names PKSi_170_ PKSi_78_ n1138 n1384 n1139 n1386 n1792 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names n1792 Pkey_224_ n1158 Pkey_232_ n1157_1 n1341 +0---- 1 +-11-- 1 +---11 1 +.names PKSi_165_ PKSi_65_ n1138 n1384 n1139 n1386 n1794_1 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names Pstart_0_ Pencrypt_0_ n1794_1 Pkey_185_ Pkey_128_ n1393 +10--1 1 +11-1- 1 +--0-- 1 +.names PKSi_40_ N_N2931 n1138 n1384 n1139 n1386 n1796 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names n1796 Pkey_107_ n1158 Pkey_115_ n1157_1 n1493 +0---- 1 +-11-- 1 +---11 1 +.names PKSi_32_ N_N2943 n1138 n1384 n1139 n1386 n1798 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names n1798 Pkey_65_ n1158 Pkey_73_ n1157_1 n1525 +0---- 1 +-11-- 1 +---11 1 +.names PKSi_139_ PKSi_39_ n1138 n1384 n1139 n1386 n1800 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names Pstart_0_ Pencrypt_0_ n1800 Pkey_88_ Pkey_96_ n1497 +10--1 1 +11-1- 1 +--0-- 1 +.names PKSi_110_ PKSi_2_ n1138 n1384 n1139 n1386 n1802 +00--0- 1 +0100-- 1 +1000-- 1 +110--1 1 +.names n1802 Pkey_33_ n1158 Pkey_41_ n1157_1 n1645 +0---- 1 +-11-- 1 +---11 1 +.names PKSi_139_ PKSi_143_ +1 1 +.names PKSi_168_ PKSi_181_ +1 1 +.names PKSi_187_ PKSi_191_ +1 1 +.names PKSi_88_ PKSi_90_ +1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v b/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v new file mode 100644 index 000000000..7267cd5aa --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v @@ -0,0 +1,2697 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module bigkey(clock, Pstart_0_, Pkey_255_, Pkey_254_, Pkey_253_, Pkey_252_, Pkey_251_, Pkey_250_, Pkey_249_, Pkey_248_, Pkey_247_, Pkey_246_, Pkey_245_, Pkey_244_, Pkey_243_, Pkey_242_, Pkey_241_, Pkey_240_, Pkey_239_, Pkey_238_, Pkey_237_, Pkey_236_, Pkey_235_, Pkey_234_, Pkey_233_, Pkey_232_, Pkey_231_, Pkey_230_, Pkey_229_, Pkey_228_, Pkey_227_, Pkey_226_, Pkey_225_, Pkey_224_, Pkey_223_, Pkey_222_, Pkey_221_, Pkey_220_, Pkey_219_, Pkey_218_, Pkey_217_, Pkey_216_, Pkey_215_, Pkey_214_, Pkey_213_, Pkey_212_, Pkey_211_, Pkey_210_, Pkey_209_, Pkey_208_, Pkey_207_, Pkey_206_, Pkey_205_, Pkey_204_, Pkey_203_, Pkey_202_, Pkey_201_, Pkey_200_, Pkey_199_, Pkey_198_, Pkey_197_, Pkey_196_, Pkey_195_, Pkey_194_, Pkey_193_, Pkey_192_, Pkey_191_, Pkey_190_, Pkey_189_, Pkey_188_, Pkey_187_, Pkey_186_, Pkey_185_, Pkey_184_, Pkey_183_, Pkey_182_, Pkey_181_, Pkey_180_, Pkey_179_, Pkey_178_, Pkey_177_, Pkey_176_, Pkey_175_, Pkey_174_, Pkey_173_, Pkey_172_, Pkey_171_, Pkey_170_, Pkey_169_, Pkey_168_, Pkey_167_, Pkey_166_, Pkey_165_, Pkey_164_, Pkey_163_, Pkey_162_, Pkey_161_, Pkey_160_, Pkey_159_, Pkey_158_, Pkey_157_, Pkey_156_, Pkey_155_, Pkey_154_, Pkey_153_, Pkey_152_, Pkey_151_, Pkey_150_, Pkey_149_, Pkey_148_, Pkey_147_, Pkey_146_, Pkey_145_, Pkey_144_, Pkey_143_, Pkey_142_, Pkey_141_, Pkey_140_, Pkey_139_, Pkey_138_, Pkey_137_, Pkey_136_, Pkey_135_, Pkey_134_, Pkey_133_, Pkey_132_, Pkey_131_, Pkey_130_, Pkey_129_, Pkey_128_, Pkey_127_, Pkey_126_, Pkey_125_, Pkey_124_, Pkey_123_, Pkey_122_, Pkey_121_, Pkey_120_, Pkey_119_, Pkey_118_, Pkey_117_, Pkey_116_, Pkey_115_, Pkey_114_, Pkey_113_, Pkey_112_, Pkey_111_, Pkey_110_, Pkey_109_, Pkey_108_, Pkey_107_, Pkey_106_, Pkey_105_, Pkey_104_, Pkey_103_, Pkey_102_, Pkey_101_, Pkey_100_, Pkey_99_, Pkey_98_, Pkey_97_, Pkey_96_, Pkey_95_, Pkey_94_, Pkey_93_, Pkey_92_, Pkey_91_, Pkey_90_, Pkey_89_, Pkey_88_, Pkey_87_, Pkey_86_, Pkey_85_, Pkey_84_, Pkey_83_, Pkey_82_, Pkey_81_, Pkey_80_, Pkey_79_, Pkey_78_, Pkey_77_, Pkey_76_, Pkey_75_, Pkey_74_, Pkey_73_, Pkey_72_, Pkey_71_, Pkey_70_, Pkey_69_, Pkey_68_, Pkey_67_, Pkey_66_, Pkey_65_, Pkey_64_, Pkey_63_, Pkey_62_, Pkey_61_, Pkey_60_, Pkey_59_, Pkey_58_, Pkey_57_, Pkey_56_, Pkey_55_, Pkey_54_, Pkey_53_, Pkey_52_, Pkey_51_, Pkey_50_, Pkey_49_, Pkey_48_, Pkey_47_, Pkey_46_, Pkey_45_, Pkey_44_, Pkey_43_, Pkey_42_, Pkey_41_, Pkey_40_, Pkey_39_, Pkey_38_, Pkey_37_, Pkey_36_, Pkey_35_, Pkey_34_, Pkey_33_, Pkey_32_, Pkey_31_, Pkey_30_, Pkey_29_, Pkey_28_, Pkey_27_, Pkey_26_, Pkey_25_, Pkey_24_, Pkey_23_, Pkey_22_, Pkey_21_, Pkey_20_, Pkey_19_, Pkey_18_, Pkey_17_, Pkey_16_, Pkey_15_, Pkey_14_, Pkey_13_, Pkey_12_, Pkey_11_, Pkey_10_, Pkey_9_, Pkey_8_, Pkey_7_, Pkey_6_, Pkey_5_, Pkey_4_, Pkey_3_, Pkey_2_, Pkey_1_, Pkey_0_, Pencrypt_0_, Pcount_3_, Pcount_2_, Pcount_1_, Pcount_0_, Pnew_count_3_, Pnew_count_2_, Pnew_count_1_, Pnew_count_0_, Pdata_ready_0_, PKSi_191_, PKSi_190_, PKSi_189_, PKSi_188_, PKSi_187_, PKSi_186_, PKSi_185_, PKSi_184_, PKSi_183_, PKSi_182_, PKSi_181_, PKSi_180_, PKSi_179_, PKSi_178_, PKSi_177_, PKSi_176_, PKSi_175_, PKSi_174_, PKSi_173_, PKSi_172_, PKSi_171_, PKSi_170_, PKSi_169_, PKSi_168_, PKSi_167_, PKSi_166_, PKSi_165_, PKSi_164_, PKSi_163_, PKSi_162_, PKSi_161_, PKSi_160_, PKSi_159_, PKSi_158_, PKSi_157_, PKSi_156_, PKSi_155_, PKSi_154_, PKSi_153_, PKSi_152_, PKSi_151_, PKSi_150_, PKSi_149_, PKSi_148_, PKSi_147_, PKSi_146_, PKSi_145_, PKSi_144_, PKSi_143_, PKSi_142_, PKSi_141_, PKSi_140_, PKSi_139_, PKSi_138_, PKSi_137_, PKSi_136_, PKSi_135_, PKSi_134_, PKSi_133_, PKSi_132_, PKSi_131_, PKSi_130_, PKSi_129_, PKSi_128_, PKSi_127_, PKSi_126_, PKSi_125_, PKSi_124_, PKSi_123_, PKSi_122_, PKSi_121_, PKSi_120_, PKSi_119_, PKSi_118_, PKSi_117_, PKSi_116_, PKSi_115_, PKSi_114_, PKSi_113_, PKSi_112_, PKSi_111_, PKSi_110_, PKSi_109_, PKSi_108_, PKSi_107_, PKSi_106_, PKSi_105_, PKSi_104_, PKSi_103_, PKSi_102_, PKSi_101_, PKSi_100_, PKSi_99_, PKSi_98_, PKSi_97_, PKSi_96_, PKSi_95_, PKSi_94_, PKSi_93_, PKSi_92_, PKSi_91_, PKSi_90_, PKSi_89_, PKSi_88_, PKSi_87_, PKSi_86_, PKSi_85_, PKSi_84_, PKSi_83_, PKSi_82_, PKSi_81_, PKSi_80_, PKSi_79_, PKSi_78_, PKSi_77_, PKSi_76_, PKSi_75_, PKSi_74_, PKSi_73_, PKSi_72_, PKSi_71_, PKSi_70_, PKSi_69_, PKSi_68_, PKSi_67_, PKSi_66_, PKSi_65_, PKSi_64_, PKSi_63_, PKSi_62_, PKSi_61_, PKSi_60_, PKSi_59_, PKSi_58_, PKSi_57_, PKSi_56_, PKSi_55_, PKSi_54_, PKSi_53_, PKSi_52_, PKSi_51_, PKSi_50_, PKSi_49_, PKSi_48_, PKSi_47_, PKSi_46_, PKSi_45_, PKSi_44_, PKSi_43_, PKSi_42_, PKSi_41_, PKSi_40_, PKSi_39_, PKSi_38_, PKSi_37_, PKSi_36_, PKSi_35_, PKSi_34_, PKSi_33_, PKSi_32_, PKSi_31_, PKSi_30_, PKSi_29_, PKSi_28_, PKSi_27_, PKSi_26_, PKSi_25_, PKSi_24_, PKSi_23_, PKSi_22_, PKSi_21_, PKSi_20_, PKSi_19_, PKSi_18_, PKSi_17_, PKSi_16_, PKSi_15_, PKSi_14_, PKSi_13_, PKSi_12_, PKSi_11_, PKSi_10_, PKSi_9_, PKSi_8_, PKSi_7_, PKSi_6_, PKSi_5_, PKSi_4_, PKSi_3_, PKSi_2_, PKSi_1_, PKSi_0_); + (* init = 1'h0 *) + reg N_N2737 = 1'h0; + (* init = 1'h0 *) + reg N_N2741 = 1'h0; + (* init = 1'h0 *) + reg N_N2746 = 1'h0; + (* init = 1'h0 *) + reg N_N2749 = 1'h0; + (* init = 1'h0 *) + reg N_N2757 = 1'h0; + (* init = 1'h0 *) + reg N_N2770 = 1'h0; + (* init = 1'h0 *) + reg N_N2774 = 1'h0; + (* init = 1'h0 *) + reg N_N2779 = 1'h0; + (* init = 1'h0 *) + reg N_N2789 = 1'h0; + (* init = 1'h0 *) + reg N_N2802 = 1'h0; + (* init = 1'h0 *) + reg N_N2806 = 1'h0; + (* init = 1'h0 *) + reg N_N2811 = 1'h0; + (* init = 1'h0 *) + reg N_N2821 = 1'h0; + (* init = 1'h0 *) + reg N_N2834 = 1'h0; + (* init = 1'h0 *) + reg N_N2838 = 1'h0; + (* init = 1'h0 *) + reg N_N2843 = 1'h0; + (* init = 1'h0 *) + reg N_N2853 = 1'h0; + (* init = 1'h0 *) + reg N_N2865 = 1'h0; + (* init = 1'h0 *) + reg N_N2877 = 1'h0; + (* init = 1'h0 *) + reg N_N2879 = 1'h0; + (* init = 1'h0 *) + reg N_N2881 = 1'h0; + (* init = 1'h0 *) + reg N_N2885 = 1'h0; + (* init = 1'h0 *) + reg N_N2889 = 1'h0; + (* init = 1'h0 *) + reg N_N2899 = 1'h0; + (* init = 1'h0 *) + reg N_N2909 = 1'h0; + (* init = 1'h0 *) + reg N_N2917 = 1'h0; + (* init = 1'h0 *) + reg N_N2921 = 1'h0; + (* init = 1'h0 *) + reg N_N2931 = 1'h0; + (* init = 1'h0 *) + reg N_N2943 = 1'h0; + (* init = 1'h0 *) + reg N_N2945 = 1'h0; + (* init = 1'h0 *) + reg N_N2950 = 1'h0; + (* init = 1'h0 *) + reg N_N2954 = 1'h0; + (* init = 1'h0 *) + reg N_N2964 = 1'h0; + (* init = 1'h0 *) + reg N_N2976 = 1'h0; + (* init = 1'h0 *) + reg N_N2982 = 1'h0; + (* init = 1'h0 *) + reg N_N2986 = 1'h0; + (* init = 1'h0 *) + output PKSi_0_; + reg PKSi_0_ = 1'h0; + (* init = 1'h0 *) + output PKSi_100_; + reg PKSi_100_ = 1'h0; + (* init = 1'h0 *) + output PKSi_101_; + reg PKSi_101_ = 1'h0; + (* init = 1'h0 *) + output PKSi_102_; + reg PKSi_102_ = 1'h0; + (* init = 1'h0 *) + output PKSi_103_; + reg PKSi_103_ = 1'h0; + (* init = 1'h0 *) + output PKSi_104_; + reg PKSi_104_ = 1'h0; + (* init = 1'h0 *) + output PKSi_105_; + reg PKSi_105_ = 1'h0; + (* init = 1'h0 *) + output PKSi_106_; + reg PKSi_106_ = 1'h0; + (* init = 1'h0 *) + output PKSi_107_; + reg PKSi_107_ = 1'h0; + (* init = 1'h0 *) + output PKSi_108_; + reg PKSi_108_ = 1'h0; + (* init = 1'h0 *) + output PKSi_109_; + reg PKSi_109_ = 1'h0; + (* init = 1'h0 *) + output PKSi_10_; + reg PKSi_10_ = 1'h0; + (* init = 1'h0 *) + output PKSi_110_; + reg PKSi_110_ = 1'h0; + (* init = 1'h0 *) + output PKSi_111_; + reg PKSi_111_ = 1'h0; + (* init = 1'h0 *) + output PKSi_112_; + reg PKSi_112_ = 1'h0; + (* init = 1'h0 *) + output PKSi_113_; + reg PKSi_113_ = 1'h0; + (* init = 1'h0 *) + output PKSi_114_; + reg PKSi_114_ = 1'h0; + (* init = 1'h0 *) + output PKSi_115_; + reg PKSi_115_ = 1'h0; + (* init = 1'h0 *) + output PKSi_116_; + reg PKSi_116_ = 1'h0; + (* init = 1'h0 *) + output PKSi_117_; + reg PKSi_117_ = 1'h0; + (* init = 1'h0 *) + output PKSi_118_; + reg PKSi_118_ = 1'h0; + (* init = 1'h0 *) + output PKSi_119_; + reg PKSi_119_ = 1'h0; + (* init = 1'h0 *) + output PKSi_11_; + reg PKSi_11_ = 1'h0; + (* init = 1'h0 *) + output PKSi_120_; + reg PKSi_120_ = 1'h0; + (* init = 1'h0 *) + output PKSi_121_; + reg PKSi_121_ = 1'h0; + (* init = 1'h0 *) + output PKSi_122_; + reg PKSi_122_ = 1'h0; + (* init = 1'h0 *) + output PKSi_123_; + reg PKSi_123_ = 1'h0; + (* init = 1'h0 *) + output PKSi_124_; + reg PKSi_124_ = 1'h0; + (* init = 1'h0 *) + output PKSi_125_; + reg PKSi_125_ = 1'h0; + (* init = 1'h0 *) + output PKSi_126_; + reg PKSi_126_ = 1'h0; + (* init = 1'h0 *) + output PKSi_127_; + reg PKSi_127_ = 1'h0; + (* init = 1'h0 *) + output PKSi_128_; + reg PKSi_128_ = 1'h0; + (* init = 1'h0 *) + output PKSi_129_; + reg PKSi_129_ = 1'h0; + (* init = 1'h0 *) + output PKSi_12_; + reg PKSi_12_ = 1'h0; + (* init = 1'h0 *) + output PKSi_130_; + reg PKSi_130_ = 1'h0; + (* init = 1'h0 *) + output PKSi_131_; + reg PKSi_131_ = 1'h0; + (* init = 1'h0 *) + output PKSi_132_; + reg PKSi_132_ = 1'h0; + (* init = 1'h0 *) + output PKSi_133_; + reg PKSi_133_ = 1'h0; + (* init = 1'h0 *) + output PKSi_134_; + reg PKSi_134_ = 1'h0; + (* init = 1'h0 *) + output PKSi_135_; + reg PKSi_135_ = 1'h0; + (* init = 1'h0 *) + output PKSi_136_; + reg PKSi_136_ = 1'h0; + (* init = 1'h0 *) + output PKSi_137_; + reg PKSi_137_ = 1'h0; + (* init = 1'h0 *) + output PKSi_138_; + reg PKSi_138_ = 1'h0; + (* init = 1'h0 *) + output PKSi_139_; + reg PKSi_139_ = 1'h0; + (* init = 1'h0 *) + output PKSi_13_; + reg PKSi_13_ = 1'h0; + (* init = 1'h0 *) + output PKSi_140_; + reg PKSi_140_ = 1'h0; + (* init = 1'h0 *) + output PKSi_141_; + reg PKSi_141_ = 1'h0; + (* init = 1'h0 *) + output PKSi_142_; + reg PKSi_142_ = 1'h0; + output PKSi_143_; + (* init = 1'h0 *) + output PKSi_144_; + reg PKSi_144_ = 1'h0; + (* init = 1'h0 *) + output PKSi_145_; + reg PKSi_145_ = 1'h0; + (* init = 1'h0 *) + output PKSi_146_; + reg PKSi_146_ = 1'h0; + (* init = 1'h0 *) + output PKSi_147_; + reg PKSi_147_ = 1'h0; + (* init = 1'h0 *) + output PKSi_148_; + reg PKSi_148_ = 1'h0; + (* init = 1'h0 *) + output PKSi_149_; + reg PKSi_149_ = 1'h0; + (* init = 1'h0 *) + output PKSi_14_; + reg PKSi_14_ = 1'h0; + (* init = 1'h0 *) + output PKSi_150_; + reg PKSi_150_ = 1'h0; + (* init = 1'h0 *) + output PKSi_151_; + reg PKSi_151_ = 1'h0; + (* init = 1'h0 *) + output PKSi_152_; + reg PKSi_152_ = 1'h0; + (* init = 1'h0 *) + output PKSi_153_; + reg PKSi_153_ = 1'h0; + (* init = 1'h0 *) + output PKSi_154_; + reg PKSi_154_ = 1'h0; + (* init = 1'h0 *) + output PKSi_155_; + reg PKSi_155_ = 1'h0; + (* init = 1'h0 *) + output PKSi_156_; + reg PKSi_156_ = 1'h0; + (* init = 1'h0 *) + output PKSi_157_; + reg PKSi_157_ = 1'h0; + (* init = 1'h0 *) + output PKSi_158_; + reg PKSi_158_ = 1'h0; + (* init = 1'h0 *) + output PKSi_159_; + reg PKSi_159_ = 1'h0; + (* init = 1'h0 *) + output PKSi_15_; + reg PKSi_15_ = 1'h0; + (* init = 1'h0 *) + output PKSi_160_; + reg PKSi_160_ = 1'h0; + (* init = 1'h0 *) + output PKSi_161_; + reg PKSi_161_ = 1'h0; + (* init = 1'h0 *) + output PKSi_162_; + reg PKSi_162_ = 1'h0; + (* init = 1'h0 *) + output PKSi_163_; + reg PKSi_163_ = 1'h0; + (* init = 1'h0 *) + output PKSi_164_; + reg PKSi_164_ = 1'h0; + (* init = 1'h0 *) + output PKSi_165_; + reg PKSi_165_ = 1'h0; + (* init = 1'h0 *) + output PKSi_166_; + reg PKSi_166_ = 1'h0; + (* init = 1'h0 *) + output PKSi_167_; + reg PKSi_167_ = 1'h0; + (* init = 1'h0 *) + output PKSi_168_; + reg PKSi_168_ = 1'h0; + (* init = 1'h0 *) + output PKSi_169_; + reg PKSi_169_ = 1'h0; + (* init = 1'h0 *) + output PKSi_16_; + reg PKSi_16_ = 1'h0; + (* init = 1'h0 *) + output PKSi_170_; + reg PKSi_170_ = 1'h0; + (* init = 1'h0 *) + output PKSi_171_; + reg PKSi_171_ = 1'h0; + (* init = 1'h0 *) + output PKSi_172_; + reg PKSi_172_ = 1'h0; + (* init = 1'h0 *) + output PKSi_173_; + reg PKSi_173_ = 1'h0; + (* init = 1'h0 *) + output PKSi_174_; + reg PKSi_174_ = 1'h0; + (* init = 1'h0 *) + output PKSi_175_; + reg PKSi_175_ = 1'h0; + (* init = 1'h0 *) + output PKSi_176_; + reg PKSi_176_ = 1'h0; + (* init = 1'h0 *) + output PKSi_177_; + reg PKSi_177_ = 1'h0; + (* init = 1'h0 *) + output PKSi_178_; + reg PKSi_178_ = 1'h0; + (* init = 1'h0 *) + output PKSi_179_; + reg PKSi_179_ = 1'h0; + (* init = 1'h0 *) + output PKSi_17_; + reg PKSi_17_ = 1'h0; + (* init = 1'h0 *) + output PKSi_180_; + reg PKSi_180_ = 1'h0; + output PKSi_181_; + (* init = 1'h0 *) + output PKSi_182_; + reg PKSi_182_ = 1'h0; + (* init = 1'h0 *) + output PKSi_183_; + reg PKSi_183_ = 1'h0; + (* init = 1'h0 *) + output PKSi_184_; + reg PKSi_184_ = 1'h0; + (* init = 1'h0 *) + output PKSi_185_; + reg PKSi_185_ = 1'h0; + (* init = 1'h0 *) + output PKSi_186_; + reg PKSi_186_ = 1'h0; + (* init = 1'h0 *) + output PKSi_187_; + reg PKSi_187_ = 1'h0; + (* init = 1'h0 *) + output PKSi_188_; + reg PKSi_188_ = 1'h0; + (* init = 1'h0 *) + output PKSi_189_; + reg PKSi_189_ = 1'h0; + (* init = 1'h0 *) + output PKSi_18_; + reg PKSi_18_ = 1'h0; + (* init = 1'h0 *) + output PKSi_190_; + reg PKSi_190_ = 1'h0; + output PKSi_191_; + (* init = 1'h0 *) + output PKSi_19_; + reg PKSi_19_ = 1'h0; + (* init = 1'h0 *) + output PKSi_1_; + reg PKSi_1_ = 1'h0; + (* init = 1'h0 *) + output PKSi_20_; + reg PKSi_20_ = 1'h0; + (* init = 1'h0 *) + output PKSi_21_; + reg PKSi_21_ = 1'h0; + (* init = 1'h0 *) + output PKSi_22_; + reg PKSi_22_ = 1'h0; + (* init = 1'h0 *) + output PKSi_23_; + reg PKSi_23_ = 1'h0; + (* init = 1'h0 *) + output PKSi_24_; + reg PKSi_24_ = 1'h0; + (* init = 1'h0 *) + output PKSi_25_; + reg PKSi_25_ = 1'h0; + (* init = 1'h0 *) + output PKSi_26_; + reg PKSi_26_ = 1'h0; + (* init = 1'h0 *) + output PKSi_27_; + reg PKSi_27_ = 1'h0; + (* init = 1'h0 *) + output PKSi_28_; + reg PKSi_28_ = 1'h0; + (* init = 1'h0 *) + output PKSi_29_; + reg PKSi_29_ = 1'h0; + (* init = 1'h0 *) + output PKSi_2_; + reg PKSi_2_ = 1'h0; + (* init = 1'h0 *) + output PKSi_30_; + reg PKSi_30_ = 1'h0; + (* init = 1'h0 *) + output PKSi_31_; + reg PKSi_31_ = 1'h0; + (* init = 1'h0 *) + output PKSi_32_; + reg PKSi_32_ = 1'h0; + (* init = 1'h0 *) + output PKSi_33_; + reg PKSi_33_ = 1'h0; + (* init = 1'h0 *) + output PKSi_34_; + reg PKSi_34_ = 1'h0; + (* init = 1'h0 *) + output PKSi_35_; + reg PKSi_35_ = 1'h0; + (* init = 1'h0 *) + output PKSi_36_; + reg PKSi_36_ = 1'h0; + (* init = 1'h0 *) + output PKSi_37_; + reg PKSi_37_ = 1'h0; + (* init = 1'h0 *) + output PKSi_38_; + reg PKSi_38_ = 1'h0; + (* init = 1'h0 *) + output PKSi_39_; + reg PKSi_39_ = 1'h0; + (* init = 1'h0 *) + output PKSi_3_; + reg PKSi_3_ = 1'h0; + (* init = 1'h0 *) + output PKSi_40_; + reg PKSi_40_ = 1'h0; + (* init = 1'h0 *) + output PKSi_41_; + reg PKSi_41_ = 1'h0; + (* init = 1'h0 *) + output PKSi_42_; + reg PKSi_42_ = 1'h0; + (* init = 1'h0 *) + output PKSi_43_; + reg PKSi_43_ = 1'h0; + (* init = 1'h0 *) + output PKSi_44_; + reg PKSi_44_ = 1'h0; + (* init = 1'h0 *) + output PKSi_45_; + reg PKSi_45_ = 1'h0; + (* init = 1'h0 *) + output PKSi_46_; + reg PKSi_46_ = 1'h0; + (* init = 1'h0 *) + output PKSi_47_; + reg PKSi_47_ = 1'h0; + (* init = 1'h0 *) + output PKSi_48_; + reg PKSi_48_ = 1'h0; + (* init = 1'h0 *) + output PKSi_49_; + reg PKSi_49_ = 1'h0; + (* init = 1'h0 *) + output PKSi_4_; + reg PKSi_4_ = 1'h0; + (* init = 1'h0 *) + output PKSi_50_; + reg PKSi_50_ = 1'h0; + (* init = 1'h0 *) + output PKSi_51_; + reg PKSi_51_ = 1'h0; + (* init = 1'h0 *) + output PKSi_52_; + reg PKSi_52_ = 1'h0; + (* init = 1'h0 *) + output PKSi_53_; + reg PKSi_53_ = 1'h0; + (* init = 1'h0 *) + output PKSi_54_; + reg PKSi_54_ = 1'h0; + (* init = 1'h0 *) + output PKSi_55_; + reg PKSi_55_ = 1'h0; + (* init = 1'h0 *) + output PKSi_56_; + reg PKSi_56_ = 1'h0; + (* init = 1'h0 *) + output PKSi_57_; + reg PKSi_57_ = 1'h0; + (* init = 1'h0 *) + output PKSi_58_; + reg PKSi_58_ = 1'h0; + (* init = 1'h0 *) + output PKSi_59_; + reg PKSi_59_ = 1'h0; + (* init = 1'h0 *) + output PKSi_5_; + reg PKSi_5_ = 1'h0; + (* init = 1'h0 *) + output PKSi_60_; + reg PKSi_60_ = 1'h0; + (* init = 1'h0 *) + output PKSi_61_; + reg PKSi_61_ = 1'h0; + (* init = 1'h0 *) + output PKSi_62_; + reg PKSi_62_ = 1'h0; + (* init = 1'h0 *) + output PKSi_63_; + reg PKSi_63_ = 1'h0; + (* init = 1'h0 *) + output PKSi_64_; + reg PKSi_64_ = 1'h0; + (* init = 1'h0 *) + output PKSi_65_; + reg PKSi_65_ = 1'h0; + (* init = 1'h0 *) + output PKSi_66_; + reg PKSi_66_ = 1'h0; + (* init = 1'h0 *) + output PKSi_67_; + reg PKSi_67_ = 1'h0; + (* init = 1'h0 *) + output PKSi_68_; + reg PKSi_68_ = 1'h0; + (* init = 1'h0 *) + output PKSi_69_; + reg PKSi_69_ = 1'h0; + (* init = 1'h0 *) + output PKSi_6_; + reg PKSi_6_ = 1'h0; + (* init = 1'h0 *) + output PKSi_70_; + reg PKSi_70_ = 1'h0; + (* init = 1'h0 *) + output PKSi_71_; + reg PKSi_71_ = 1'h0; + (* init = 1'h0 *) + output PKSi_72_; + reg PKSi_72_ = 1'h0; + (* init = 1'h0 *) + output PKSi_73_; + reg PKSi_73_ = 1'h0; + (* init = 1'h0 *) + output PKSi_74_; + reg PKSi_74_ = 1'h0; + (* init = 1'h0 *) + output PKSi_75_; + reg PKSi_75_ = 1'h0; + (* init = 1'h0 *) + output PKSi_76_; + reg PKSi_76_ = 1'h0; + (* init = 1'h0 *) + output PKSi_77_; + reg PKSi_77_ = 1'h0; + (* init = 1'h0 *) + output PKSi_78_; + reg PKSi_78_ = 1'h0; + (* init = 1'h0 *) + output PKSi_79_; + reg PKSi_79_ = 1'h0; + (* init = 1'h0 *) + output PKSi_7_; + reg PKSi_7_ = 1'h0; + (* init = 1'h0 *) + output PKSi_80_; + reg PKSi_80_ = 1'h0; + (* init = 1'h0 *) + output PKSi_81_; + reg PKSi_81_ = 1'h0; + (* init = 1'h0 *) + output PKSi_82_; + reg PKSi_82_ = 1'h0; + (* init = 1'h0 *) + output PKSi_83_; + reg PKSi_83_ = 1'h0; + (* init = 1'h0 *) + output PKSi_84_; + reg PKSi_84_ = 1'h0; + (* init = 1'h0 *) + output PKSi_85_; + reg PKSi_85_ = 1'h0; + (* init = 1'h0 *) + output PKSi_86_; + reg PKSi_86_ = 1'h0; + (* init = 1'h0 *) + output PKSi_87_; + reg PKSi_87_ = 1'h0; + (* init = 1'h0 *) + output PKSi_88_; + reg PKSi_88_ = 1'h0; + (* init = 1'h0 *) + output PKSi_89_; + reg PKSi_89_ = 1'h0; + (* init = 1'h0 *) + output PKSi_8_; + reg PKSi_8_ = 1'h0; + output PKSi_90_; + (* init = 1'h0 *) + output PKSi_91_; + reg PKSi_91_ = 1'h0; + (* init = 1'h0 *) + output PKSi_92_; + reg PKSi_92_ = 1'h0; + (* init = 1'h0 *) + output PKSi_93_; + reg PKSi_93_ = 1'h0; + (* init = 1'h0 *) + output PKSi_94_; + reg PKSi_94_ = 1'h0; + (* init = 1'h0 *) + output PKSi_95_; + reg PKSi_95_ = 1'h0; + (* init = 1'h0 *) + output PKSi_96_; + reg PKSi_96_ = 1'h0; + (* init = 1'h0 *) + output PKSi_97_; + reg PKSi_97_ = 1'h0; + (* init = 1'h0 *) + output PKSi_98_; + reg PKSi_98_ = 1'h0; + (* init = 1'h0 *) + output PKSi_99_; + reg PKSi_99_ = 1'h0; + (* init = 1'h0 *) + output PKSi_9_; + reg PKSi_9_ = 1'h0; + input Pcount_0_; + input Pcount_1_; + input Pcount_2_; + input Pcount_3_; + output Pdata_ready_0_; + input Pencrypt_0_; + input Pkey_0_; + input Pkey_100_; + input Pkey_101_; + input Pkey_102_; + input Pkey_103_; + input Pkey_104_; + input Pkey_105_; + input Pkey_106_; + input Pkey_107_; + input Pkey_108_; + input Pkey_109_; + input Pkey_10_; + input Pkey_110_; + input Pkey_111_; + input Pkey_112_; + input Pkey_113_; + input Pkey_114_; + input Pkey_115_; + input Pkey_116_; + input Pkey_117_; + input Pkey_118_; + input Pkey_119_; + input Pkey_11_; + input Pkey_120_; + input Pkey_121_; + input Pkey_122_; + input Pkey_123_; + input Pkey_124_; + input Pkey_125_; + input Pkey_126_; + input Pkey_127_; + input Pkey_128_; + input Pkey_129_; + input Pkey_12_; + input Pkey_130_; + input Pkey_131_; + input Pkey_132_; + input Pkey_133_; + input Pkey_134_; + input Pkey_135_; + input Pkey_136_; + input Pkey_137_; + input Pkey_138_; + input Pkey_139_; + input Pkey_13_; + input Pkey_140_; + input Pkey_141_; + input Pkey_142_; + input Pkey_143_; + input Pkey_144_; + input Pkey_145_; + input Pkey_146_; + input Pkey_147_; + input Pkey_148_; + input Pkey_149_; + input Pkey_14_; + input Pkey_150_; + input Pkey_151_; + input Pkey_152_; + input Pkey_153_; + input Pkey_154_; + input Pkey_155_; + input Pkey_156_; + input Pkey_157_; + input Pkey_158_; + input Pkey_159_; + input Pkey_15_; + input Pkey_160_; + input Pkey_161_; + input Pkey_162_; + input Pkey_163_; + input Pkey_164_; + input Pkey_165_; + input Pkey_166_; + input Pkey_167_; + input Pkey_168_; + input Pkey_169_; + input Pkey_16_; + input Pkey_170_; + input Pkey_171_; + input Pkey_172_; + input Pkey_173_; + input Pkey_174_; + input Pkey_175_; + input Pkey_176_; + input Pkey_177_; + input Pkey_178_; + input Pkey_179_; + input Pkey_17_; + input Pkey_180_; + input Pkey_181_; + input Pkey_182_; + input Pkey_183_; + input Pkey_184_; + input Pkey_185_; + input Pkey_186_; + input Pkey_187_; + input Pkey_188_; + input Pkey_189_; + input Pkey_18_; + input Pkey_190_; + input Pkey_191_; + input Pkey_192_; + input Pkey_193_; + input Pkey_194_; + input Pkey_195_; + input Pkey_196_; + input Pkey_197_; + input Pkey_198_; + input Pkey_199_; + input Pkey_19_; + input Pkey_1_; + input Pkey_200_; + input Pkey_201_; + input Pkey_202_; + input Pkey_203_; + input Pkey_204_; + input Pkey_205_; + input Pkey_206_; + input Pkey_207_; + input Pkey_208_; + input Pkey_209_; + input Pkey_20_; + input Pkey_210_; + input Pkey_211_; + input Pkey_212_; + input Pkey_213_; + input Pkey_214_; + input Pkey_215_; + input Pkey_216_; + input Pkey_217_; + input Pkey_218_; + input Pkey_219_; + input Pkey_21_; + input Pkey_220_; + input Pkey_221_; + input Pkey_222_; + input Pkey_223_; + input Pkey_224_; + input Pkey_225_; + input Pkey_226_; + input Pkey_227_; + input Pkey_228_; + input Pkey_229_; + input Pkey_22_; + input Pkey_230_; + input Pkey_231_; + input Pkey_232_; + input Pkey_233_; + input Pkey_234_; + input Pkey_235_; + input Pkey_236_; + input Pkey_237_; + input Pkey_238_; + input Pkey_239_; + input Pkey_23_; + input Pkey_240_; + input Pkey_241_; + input Pkey_242_; + input Pkey_243_; + input Pkey_244_; + input Pkey_245_; + input Pkey_246_; + input Pkey_247_; + input Pkey_248_; + input Pkey_249_; + input Pkey_24_; + input Pkey_250_; + input Pkey_251_; + input Pkey_252_; + input Pkey_253_; + input Pkey_254_; + input Pkey_255_; + input Pkey_25_; + input Pkey_26_; + input Pkey_27_; + input Pkey_28_; + input Pkey_29_; + input Pkey_2_; + input Pkey_30_; + input Pkey_31_; + input Pkey_32_; + input Pkey_33_; + input Pkey_34_; + input Pkey_35_; + input Pkey_36_; + input Pkey_37_; + input Pkey_38_; + input Pkey_39_; + input Pkey_3_; + input Pkey_40_; + input Pkey_41_; + input Pkey_42_; + input Pkey_43_; + input Pkey_44_; + input Pkey_45_; + input Pkey_46_; + input Pkey_47_; + input Pkey_48_; + input Pkey_49_; + input Pkey_4_; + input Pkey_50_; + input Pkey_51_; + input Pkey_52_; + input Pkey_53_; + input Pkey_54_; + input Pkey_55_; + input Pkey_56_; + input Pkey_57_; + input Pkey_58_; + input Pkey_59_; + input Pkey_5_; + input Pkey_60_; + input Pkey_61_; + input Pkey_62_; + input Pkey_63_; + input Pkey_64_; + input Pkey_65_; + input Pkey_66_; + input Pkey_67_; + input Pkey_68_; + input Pkey_69_; + input Pkey_6_; + input Pkey_70_; + input Pkey_71_; + input Pkey_72_; + input Pkey_73_; + input Pkey_74_; + input Pkey_75_; + input Pkey_76_; + input Pkey_77_; + input Pkey_78_; + input Pkey_79_; + input Pkey_7_; + input Pkey_80_; + input Pkey_81_; + input Pkey_82_; + input Pkey_83_; + input Pkey_84_; + input Pkey_85_; + input Pkey_86_; + input Pkey_87_; + input Pkey_88_; + input Pkey_89_; + input Pkey_8_; + input Pkey_90_; + input Pkey_91_; + input Pkey_92_; + input Pkey_93_; + input Pkey_94_; + input Pkey_95_; + input Pkey_96_; + input Pkey_97_; + input Pkey_98_; + input Pkey_99_; + input Pkey_9_; + output Pnew_count_0_; + output Pnew_count_1_; + output Pnew_count_2_; + output Pnew_count_3_; + input Pstart_0_; + input clock; + wire n1001; + wire n1005; + wire n1009; + wire n1013; + wire n1017; + wire n1021; + wire n1025; + wire n1029; + wire n1033; + wire n1037; + wire n1041; + wire n1045; + wire n1049; + wire n1053; + wire n1057; + wire n1061; + wire n1065; + wire n1069_1; + wire n1073_1; + wire n1077_1; + wire n1081_1; + wire n1085; + wire n1089; + wire n1093; + wire n1097; + wire n1101; + wire n1105; + wire n1109; + wire n1113; + wire n1117; + wire n1121; + wire n1125; + wire n1129; + wire n1133; + wire n1136; + wire n1137; + wire n1137_1; + wire n1138; + wire n1139; + wire n1140; + wire n1141; + wire n1141_1; + wire n1143; + wire n1144; + wire n1145; + wire n1146; + wire n1147; + wire n1149; + wire n1149_1; + wire n1150; + wire n1152; + wire n1153; + wire n1153_1; + wire n1155; + wire n1156; + wire n1157; + wire n1157_1; + wire n1158; + wire n1160; + wire n1161; + wire n1161_1; + wire n1163; + wire n1164; + wire n1165; + wire n1166; + wire n1167; + wire n1169; + wire n1169_1; + wire n1170; + wire n1172; + wire n1173; + wire n1173_1; + wire n1175; + wire n1176; + wire n1177; + wire n1178; + wire n1179; + wire n1181; + wire n1181_1; + wire n1182; + wire n1184; + wire n1185; + wire n1185_1; + wire n1187; + wire n1188; + wire n1189_1; + wire n1190; + wire n1191; + wire n1193; + wire n1193_1; + wire n1194; + wire n1196; + wire n1197; + wire n1197_1; + wire n1199; + wire n1200; + wire n1201; + wire n1202; + wire n1203; + wire n1205; + wire n1205_1; + wire n1206; + wire n1208; + wire n1209; + wire n1209_1; + wire n1211; + wire n1212; + wire n1213; + wire n1214; + wire n1215; + wire n1217; + wire n1217_1; + wire n1218; + wire n1220; + wire n1221; + wire n1221_1; + wire n1223; + wire n1224; + wire n1225; + wire n1226; + wire n1227; + wire n1229; + wire n1229_1; + wire n1230; + wire n1232; + wire n1233; + wire n1233_1; + wire n1235; + wire n1236; + wire n1237; + wire n1238; + wire n1239; + wire n1241; + wire n1241_1; + wire n1242; + wire n1244; + wire n1245; + wire n1245_1; + wire n1247; + wire n1248; + wire n1249; + wire n1250; + wire n1251; + wire n1253; + wire n1253_1; + wire n1254; + wire n1256; + wire n1257; + wire n1257_1; + wire n1259; + wire n1260; + wire n1261; + wire n1262; + wire n1263; + wire n1265; + wire n1265_1; + wire n1266; + wire n1268; + wire n1269; + wire n1269_1; + wire n1271; + wire n1272; + wire n1273; + wire n1274; + wire n1275; + wire n1277; + wire n1277_1; + wire n1278; + wire n1280; + wire n1281; + wire n1281_1; + wire n1283; + wire n1284; + wire n1285; + wire n1286; + wire n1287; + wire n1289; + wire n1289_1; + wire n1290; + wire n1292; + wire n1293; + wire n1293_1; + wire n1295; + wire n1296; + wire n1297; + wire n1298; + wire n1299; + wire n1301; + wire n1301_1; + wire n1302; + wire n1304; + wire n1305; + wire n1305_1; + wire n1307; + wire n1308; + wire n1309; + wire n1310; + wire n1311; + wire n1313; + wire n1313_1; + wire n1314; + wire n1316; + wire n1317; + wire n1317_1; + wire n1319; + wire n1320; + wire n1321; + wire n1322; + wire n1323; + wire n1325; + wire n1325_1; + wire n1326; + wire n1328; + wire n1329; + wire n1330; + wire n1332; + wire n1333; + wire n1333_1; + wire n1335; + wire n1336; + wire n1337; + wire n1338; + wire n1339; + wire n1341; + wire n1341_1; + wire n1342; + wire n1344; + wire n1345; + wire n1345_1; + wire n1347; + wire n1348; + wire n1349; + wire n1350; + wire n1351; + wire n1353; + wire n1353_1; + wire n1354; + wire n1356; + wire n1357; + wire n1357_1; + wire n1359; + wire n1360; + wire n1361; + wire n1362; + wire n1363; + wire n1365; + wire n1365_1; + wire n1366; + wire n1368; + wire n1369; + wire n1369_1; + wire n1371; + wire n1372; + wire n1373; + wire n1374; + wire n1375; + wire n1377; + wire n1377_1; + wire n1378; + wire n1380; + wire n1381; + wire n1381_1; + wire n1383; + wire n1384; + wire n1385; + wire n1385_1; + wire n1386; + wire n1388; + wire n1389; + wire n1389_1; + wire n1391; + wire n1392; + wire n1393; + wire n1394; + wire n1395; + wire n1397; + wire n1397_1; + wire n1398; + wire n1400; + wire n1401; + wire n1401_1; + wire n1403; + wire n1404; + wire n1405; + wire n1406; + wire n1407; + wire n1409; + wire n1409_1; + wire n1410; + wire n1412; + wire n1413; + wire n1413_1; + wire n1415; + wire n1416; + wire n1417; + wire n1418; + wire n1419; + wire n1421; + wire n1421_1; + wire n1422; + wire n1424; + wire n1425; + wire n1425_1; + wire n1427; + wire n1428; + wire n1429; + wire n1430; + wire n1431; + wire n1433; + wire n1433_1; + wire n1434; + wire n1436; + wire n1437; + wire n1437_1; + wire n1439; + wire n1440; + wire n1441; + wire n1442; + wire n1443; + wire n1445; + wire n1445_1; + wire n1446; + wire n1448; + wire n1449; + wire n1449_1; + wire n1451; + wire n1452; + wire n1453; + wire n1454; + wire n1455; + wire n1457; + wire n1457_1; + wire n1458; + wire n1460; + wire n1461; + wire n1461_1; + wire n1463; + wire n1464; + wire n1465; + wire n1466; + wire n1467; + wire n1469; + wire n1469_1; + wire n1470; + wire n1472; + wire n1473; + wire n1473_1; + wire n1475; + wire n1476; + wire n1477; + wire n1478; + wire n1479; + wire n1481; + wire n1481_1; + wire n1482; + wire n1484; + wire n1485; + wire n1485_1; + wire n1487; + wire n1488; + wire n1489; + wire n1490; + wire n1492; + wire n1493; + wire n1493_1; + wire n1495; + wire n1496; + wire n1497; + wire n1498; + wire n1499; + wire n1501; + wire n1501_1; + wire n1502; + wire n1504; + wire n1505; + wire n1505_1; + wire n1507; + wire n1508; + wire n1509; + wire n1510; + wire n1511; + wire n1513; + wire n1513_1; + wire n1514; + wire n1516; + wire n1517; + wire n1517_1; + wire n1519; + wire n1520; + wire n1521; + wire n1522; + wire n1523; + wire n1525; + wire n1525_1; + wire n1526; + wire n1528; + wire n1529; + wire n1529_1; + wire n1531; + wire n1532; + wire n1533; + wire n1534; + wire n1535; + wire n1537; + wire n1537_1; + wire n1538; + wire n1540; + wire n1541; + wire n1541_1; + wire n1543; + wire n1544; + wire n1545; + wire n1546; + wire n1547; + wire n1549; + wire n1549_1; + wire n1550; + wire n1552; + wire n1553; + wire n1553_1; + wire n1555; + wire n1556; + wire n1557; + wire n1558; + wire n1559; + wire n1561; + wire n1561_1; + wire n1562; + wire n1564; + wire n1565; + wire n1565_1; + wire n1567; + wire n1568; + wire n1569; + wire n1570; + wire n1571; + wire n1573; + wire n1573_1; + wire n1574; + wire n1576; + wire n1577; + wire n1577_1; + wire n1579; + wire n1580; + wire n1581; + wire n1582; + wire n1583; + wire n1585; + wire n1585_1; + wire n1586; + wire n1588; + wire n1589; + wire n1589_1; + wire n1591; + wire n1592; + wire n1593; + wire n1594; + wire n1595; + wire n1597; + wire n1597_1; + wire n1598; + wire n1600; + wire n1601; + wire n1601_1; + wire n1603; + wire n1604; + wire n1605; + wire n1606; + wire n1607; + wire n1609; + wire n1609_1; + wire n1610; + wire n1612; + wire n1613; + wire n1613_1; + wire n1615; + wire n1616; + wire n1617; + wire n1618; + wire n1619; + wire n1621; + wire n1621_1; + wire n1622; + wire n1624; + wire n1625; + wire n1625_1; + wire n1627; + wire n1628; + wire n1629; + wire n1630; + wire n1631; + wire n1633; + wire n1633_1; + wire n1634; + wire n1636; + wire n1637; + wire n1638; + wire n1639; + wire n1641; + wire n1641_1; + wire n1642; + wire n1644; + wire n1645; + wire n1645_1; + wire n1647; + wire n1648; + wire n1649; + wire n1650; + wire n1651; + wire n1653; + wire n1653_1; + wire n1654; + wire n1656; + wire n1657; + wire n1657_1; + wire n1659; + wire n1660; + wire n1661; + wire n1662; + wire n1663; + wire n1665; + wire n1666; + wire n1666_1; + wire n1668; + wire n1669; + wire n1671; + wire n1671_1; + wire n1672; + wire n1674; + wire n1675; + wire n1676; + wire n1677; + wire n1678; + wire n1680; + wire n1681; + wire n1681_1; + wire n1683; + wire n1684; + wire n1686; + wire n1686_1; + wire n1687; + wire n1689; + wire n1690; + wire n1691; + wire n1692; + wire n1693; + wire n1695; + wire n1696; + wire n1696_1; + wire n1701; + wire n1703; + wire n1704; + wire n1706; + wire n1706_1; + wire n1707; + wire n1709; + wire n1710; + wire n1711; + wire n1712; + wire n1714; + wire n1715; + wire n1716; + wire n1717; + wire n1718; + wire n1720; + wire n1721; + wire n1721_1; + wire n1723; + wire n1724; + wire n1726; + wire n1726_1; + wire n1727; + wire n1729; + wire n1730; + wire n1731; + wire n1732; + wire n1734; + wire n1735; + wire n1736; + wire n1737; + wire n1738; + wire n1740; + wire n1741; + wire n1741_1; + wire n1743; + wire n1744; + wire n1746; + wire n1746_1; + wire n1747; + wire n1749; + wire n1750; + wire n1751; + wire n1752; + wire n1753; + wire n1755; + wire n1755_1; + wire n1756; + wire n1758; + wire n1759; + wire n1760; + wire n1761; + wire n1762; + wire n1764; + wire n1765; + wire n1765_1; + wire n1767; + wire n1768; + wire n1770; + wire n1770_1; + wire n1771; + wire n1773; + wire n1774; + wire n1775; + wire n1776; + wire n1777; + wire n1779; + wire n1780; + wire n1780_1; + wire n1782; + wire n1783; + wire n1784; + wire n1784_1; + wire n1786; + wire n1788; + wire n1789; + wire n1790; + wire n1792; + wire n1794; + wire n1794_1; + wire n1796; + wire n1798; + wire n1799_1; + wire n1800; + wire n1802; + wire n1804; + wire n1809; + wire n1814; + wire n1819; + wire n1824; + wire n1829; + wire n1833_1; + wire n1838; + wire n1843; + wire n1848; + wire n921_1; + wire n925; + wire n929; + wire n933; + wire n937; + wire n941; + wire n945; + wire n949; + wire n953; + wire n957; + wire n961; + wire n965; + wire n969_1; + wire n973_1; + wire n977; + wire n981; + wire n985; + wire n989; + wire n993; + wire n997; + always @(posedge clock) + PKSi_190_ <= n921_1; + always @(posedge clock) + PKSi_179_ <= n957; + always @(posedge clock) + PKSi_84_ <= n1317; + always @(posedge clock) + PKSi_83_ <= n1321; + always @(posedge clock) + PKSi_82_ <= n1325; + always @(posedge clock) + PKSi_81_ <= n1329; + always @(posedge clock) + PKSi_80_ <= n1333; + always @(posedge clock) + PKSi_79_ <= n1337; + always @(posedge clock) + PKSi_78_ <= n1341; + always @(posedge clock) + PKSi_77_ <= n1345; + always @(posedge clock) + PKSi_76_ <= n1349; + always @(posedge clock) + PKSi_75_ <= n1353; + always @(posedge clock) + PKSi_178_ <= n961; + always @(posedge clock) + PKSi_74_ <= n1357; + always @(posedge clock) + PKSi_73_ <= n1361; + always @(posedge clock) + PKSi_72_ <= n1365; + always @(posedge clock) + PKSi_71_ <= n1369; + always @(posedge clock) + PKSi_70_ <= n1373; + always @(posedge clock) + PKSi_69_ <= n1377; + always @(posedge clock) + PKSi_68_ <= n1381; + always @(posedge clock) + PKSi_67_ <= n1385; + always @(posedge clock) + PKSi_66_ <= n1389; + always @(posedge clock) + PKSi_65_ <= n1393; + always @(posedge clock) + PKSi_177_ <= n965; + always @(posedge clock) + PKSi_64_ <= n1397; + always @(posedge clock) + PKSi_63_ <= n1401; + always @(posedge clock) + PKSi_62_ <= n1405; + always @(posedge clock) + PKSi_61_ <= n1409; + always @(posedge clock) + PKSi_60_ <= n1413; + always @(posedge clock) + PKSi_59_ <= n1417; + always @(posedge clock) + PKSi_58_ <= n1421; + always @(posedge clock) + PKSi_57_ <= n1425; + always @(posedge clock) + PKSi_56_ <= n1429; + always @(posedge clock) + PKSi_55_ <= n1433; + always @(posedge clock) + PKSi_176_ <= n969_1; + always @(posedge clock) + PKSi_54_ <= n1437; + always @(posedge clock) + PKSi_53_ <= n1441; + always @(posedge clock) + PKSi_52_ <= n1445; + always @(posedge clock) + PKSi_51_ <= n1449; + always @(posedge clock) + PKSi_50_ <= n1453; + always @(posedge clock) + PKSi_49_ <= n1457; + always @(posedge clock) + PKSi_48_ <= n1461; + always @(posedge clock) + PKSi_47_ <= n1465; + always @(posedge clock) + PKSi_46_ <= n1469; + always @(posedge clock) + PKSi_45_ <= n1473; + always @(posedge clock) + PKSi_175_ <= n973_1; + always @(posedge clock) + PKSi_44_ <= n1477; + always @(posedge clock) + PKSi_43_ <= n1481; + always @(posedge clock) + PKSi_42_ <= n1485; + always @(posedge clock) + PKSi_41_ <= n1489; + always @(posedge clock) + PKSi_40_ <= n1493; + always @(posedge clock) + PKSi_39_ <= n1497; + always @(posedge clock) + PKSi_38_ <= n1501; + always @(posedge clock) + PKSi_37_ <= n1505; + always @(posedge clock) + PKSi_36_ <= n1509; + always @(posedge clock) + PKSi_35_ <= n1513; + always @(posedge clock) + PKSi_174_ <= n977; + always @(posedge clock) + PKSi_34_ <= n1517; + always @(posedge clock) + PKSi_33_ <= n1521; + always @(posedge clock) + PKSi_32_ <= n1525; + always @(posedge clock) + PKSi_31_ <= n1529; + always @(posedge clock) + PKSi_30_ <= n1533; + always @(posedge clock) + PKSi_29_ <= n1537; + always @(posedge clock) + PKSi_28_ <= n1541; + always @(posedge clock) + PKSi_27_ <= n1545; + always @(posedge clock) + PKSi_26_ <= n1549; + always @(posedge clock) + PKSi_25_ <= n1553; + always @(posedge clock) + PKSi_173_ <= n981; + always @(posedge clock) + PKSi_24_ <= n1557; + always @(posedge clock) + PKSi_23_ <= n1561; + always @(posedge clock) + PKSi_22_ <= n1565; + always @(posedge clock) + PKSi_21_ <= n1569; + always @(posedge clock) + PKSi_20_ <= n1573; + always @(posedge clock) + PKSi_19_ <= n1577; + always @(posedge clock) + PKSi_18_ <= n1581; + always @(posedge clock) + PKSi_17_ <= n1585; + always @(posedge clock) + PKSi_16_ <= n1589; + always @(posedge clock) + PKSi_15_ <= n1593; + always @(posedge clock) + PKSi_172_ <= n985; + always @(posedge clock) + PKSi_14_ <= n1597; + always @(posedge clock) + PKSi_13_ <= n1601; + always @(posedge clock) + PKSi_12_ <= n1605; + always @(posedge clock) + PKSi_11_ <= n1609; + always @(posedge clock) + PKSi_10_ <= n1613; + always @(posedge clock) + PKSi_9_ <= n1617; + always @(posedge clock) + PKSi_8_ <= n1621; + always @(posedge clock) + PKSi_7_ <= n1625; + always @(posedge clock) + PKSi_6_ <= n1629; + always @(posedge clock) + PKSi_5_ <= n1633; + always @(posedge clock) + PKSi_171_ <= n989; + always @(posedge clock) + PKSi_4_ <= n1637; + always @(posedge clock) + PKSi_3_ <= n1641; + always @(posedge clock) + PKSi_2_ <= n1645; + always @(posedge clock) + PKSi_1_ <= n1649; + always @(posedge clock) + PKSi_0_ <= n1653; + always @(posedge clock) + PKSi_88_ <= n1657; + always @(posedge clock) + N_N2737 <= n1661; + always @(posedge clock) + N_N2741 <= n1666; + always @(posedge clock) + N_N2746 <= n1671; + always @(posedge clock) + N_N2749 <= n1676; + always @(posedge clock) + PKSi_170_ <= n993; + always @(posedge clock) + N_N2757 <= n1681; + always @(posedge clock) + N_N2770 <= n1686; + always @(posedge clock) + N_N2774 <= n1691; + always @(posedge clock) + N_N2779 <= n1696; + always @(posedge clock) + N_N2789 <= n1701; + always @(posedge clock) + N_N2802 <= n1706; + always @(posedge clock) + N_N2806 <= n1711; + always @(posedge clock) + N_N2811 <= n1716; + always @(posedge clock) + N_N2821 <= n1721; + always @(posedge clock) + N_N2834 <= n1726; + always @(posedge clock) + PKSi_189_ <= n925; + always @(posedge clock) + PKSi_169_ <= n997; + always @(posedge clock) + N_N2838 <= n1731; + always @(posedge clock) + N_N2843 <= n1736; + always @(posedge clock) + N_N2853 <= n1741; + always @(posedge clock) + N_N2865 <= n1746; + always @(posedge clock) + PKSi_168_ <= n1751; + always @(posedge clock) + N_N2877 <= n1755; + always @(posedge clock) + N_N2879 <= n1760; + always @(posedge clock) + N_N2881 <= n1765; + always @(posedge clock) + N_N2885 <= n1770; + always @(posedge clock) + N_N2889 <= n1775; + always @(posedge clock) + PKSi_167_ <= n1001; + always @(posedge clock) + PKSi_187_ <= n1780; + always @(posedge clock) + N_N2899 <= n1784; + always @(posedge clock) + N_N2909 <= n1789; + always @(posedge clock) + N_N2917 <= n1794; + always @(posedge clock) + N_N2921 <= n1799_1; + always @(posedge clock) + N_N2931 <= n1804; + always @(posedge clock) + N_N2943 <= n1809; + always @(posedge clock) + N_N2945 <= n1814; + always @(posedge clock) + N_N2950 <= n1819; + always @(posedge clock) + N_N2954 <= n1824; + always @(posedge clock) + PKSi_166_ <= n1005; + always @(posedge clock) + PKSi_139_ <= n1829; + always @(posedge clock) + N_N2964 <= n1833_1; + always @(posedge clock) + N_N2976 <= n1838; + always @(posedge clock) + N_N2982 <= n1843; + always @(posedge clock) + N_N2986 <= n1848; + always @(posedge clock) + PKSi_165_ <= n1009; + always @(posedge clock) + PKSi_164_ <= n1013; + always @(posedge clock) + PKSi_163_ <= n1017; + always @(posedge clock) + PKSi_162_ <= n1021; + always @(posedge clock) + PKSi_161_ <= n1025; + always @(posedge clock) + PKSi_160_ <= n1029; + always @(posedge clock) + PKSi_159_ <= n1033; + always @(posedge clock) + PKSi_188_ <= n929; + always @(posedge clock) + PKSi_158_ <= n1037; + always @(posedge clock) + PKSi_157_ <= n1041; + always @(posedge clock) + PKSi_156_ <= n1045; + always @(posedge clock) + PKSi_155_ <= n1049; + always @(posedge clock) + PKSi_154_ <= n1053; + always @(posedge clock) + PKSi_153_ <= n1057; + always @(posedge clock) + PKSi_152_ <= n1061; + always @(posedge clock) + PKSi_151_ <= n1065; + always @(posedge clock) + PKSi_150_ <= n1069_1; + always @(posedge clock) + PKSi_149_ <= n1073_1; + always @(posedge clock) + PKSi_186_ <= n933; + always @(posedge clock) + PKSi_148_ <= n1077_1; + always @(posedge clock) + PKSi_147_ <= n1081_1; + always @(posedge clock) + PKSi_146_ <= n1085; + always @(posedge clock) + PKSi_145_ <= n1089; + always @(posedge clock) + PKSi_144_ <= n1093; + always @(posedge clock) + PKSi_142_ <= n1097; + always @(posedge clock) + PKSi_141_ <= n1101; + always @(posedge clock) + PKSi_140_ <= n1105; + always @(posedge clock) + PKSi_138_ <= n1109; + always @(posedge clock) + PKSi_137_ <= n1113; + always @(posedge clock) + PKSi_185_ <= n937; + always @(posedge clock) + PKSi_136_ <= n1117; + always @(posedge clock) + PKSi_135_ <= n1121; + always @(posedge clock) + PKSi_134_ <= n1125; + always @(posedge clock) + PKSi_133_ <= n1129; + always @(posedge clock) + PKSi_132_ <= n1133; + always @(posedge clock) + PKSi_131_ <= n1137; + always @(posedge clock) + PKSi_130_ <= n1141; + always @(posedge clock) + PKSi_129_ <= n1145; + always @(posedge clock) + PKSi_128_ <= n1149; + always @(posedge clock) + PKSi_127_ <= n1153; + always @(posedge clock) + PKSi_184_ <= n941; + always @(posedge clock) + PKSi_126_ <= n1157; + always @(posedge clock) + PKSi_125_ <= n1161; + always @(posedge clock) + PKSi_124_ <= n1165; + always @(posedge clock) + PKSi_123_ <= n1169; + always @(posedge clock) + PKSi_122_ <= n1173; + always @(posedge clock) + PKSi_121_ <= n1177; + always @(posedge clock) + PKSi_120_ <= n1181; + always @(posedge clock) + PKSi_119_ <= n1185_1; + always @(posedge clock) + PKSi_118_ <= n1189_1; + always @(posedge clock) + PKSi_117_ <= n1193_1; + always @(posedge clock) + PKSi_183_ <= n945; + always @(posedge clock) + PKSi_116_ <= n1197_1; + always @(posedge clock) + PKSi_115_ <= n1201; + always @(posedge clock) + PKSi_114_ <= n1205; + always @(posedge clock) + PKSi_113_ <= n1209; + always @(posedge clock) + PKSi_112_ <= n1213; + always @(posedge clock) + PKSi_111_ <= n1217; + always @(posedge clock) + PKSi_110_ <= n1221; + always @(posedge clock) + PKSi_109_ <= n1225; + always @(posedge clock) + PKSi_108_ <= n1229; + always @(posedge clock) + PKSi_107_ <= n1233; + always @(posedge clock) + PKSi_182_ <= n949; + always @(posedge clock) + PKSi_106_ <= n1237; + always @(posedge clock) + PKSi_105_ <= n1241; + always @(posedge clock) + PKSi_104_ <= n1245; + always @(posedge clock) + PKSi_103_ <= n1249; + always @(posedge clock) + PKSi_102_ <= n1253; + always @(posedge clock) + PKSi_101_ <= n1257; + always @(posedge clock) + PKSi_100_ <= n1261; + always @(posedge clock) + PKSi_99_ <= n1265; + always @(posedge clock) + PKSi_98_ <= n1269; + always @(posedge clock) + PKSi_97_ <= n1273; + always @(posedge clock) + PKSi_180_ <= n953; + always @(posedge clock) + PKSi_96_ <= n1277; + always @(posedge clock) + PKSi_95_ <= n1281; + always @(posedge clock) + PKSi_94_ <= n1285; + always @(posedge clock) + PKSi_93_ <= n1289; + always @(posedge clock) + PKSi_92_ <= n1293; + always @(posedge clock) + PKSi_91_ <= n1297; + always @(posedge clock) + PKSi_89_ <= n1301; + always @(posedge clock) + PKSi_87_ <= n1305; + always @(posedge clock) + PKSi_86_ <= n1309; + always @(posedge clock) + PKSi_85_ <= n1313; + assign n1033 = 16'hd555 >> { PKSi_159_, n1141_1, PKSi_55_, n1136 }; + assign n1136 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_55_, PKSi_159_, n1140 }; + assign n1137_1 = 64'h0000000000808002 >> { Pstart_0_, Pcount_0_, Pcount_3_, Pcount_2_, Pcount_1_, Pencrypt_0_ }; + assign n1138 = 64'h0103030303020202 >> { Pcount_2_, Pcount_0_, Pcount_3_, Pencrypt_0_, Pstart_0_, Pcount_1_ }; + assign n1139 = 64'h0008000100010001 >> { Pcount_0_, Pcount_3_, Pencrypt_0_, Pstart_0_, Pcount_1_, Pcount_2_ }; + assign n1140 = 16'h57df >> { Pkey_254_, Pkey_131_, Pencrypt_0_, Pstart_0_ }; + assign n1141_1 = 64'h00000000ff7f7ffd >> { Pstart_0_, Pcount_0_, Pcount_3_, Pcount_2_, Pcount_1_, Pencrypt_0_ }; + assign n1073_1 = 16'hd555 >> { PKSi_149_, n1141_1, PKSi_68_, n1143 }; + assign n1143 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_68_, PKSi_149_, n1144 }; + assign n1144 = 16'h5d7f >> { Pkey_139_, Pkey_131_, Pencrypt_0_, Pstart_0_ }; + assign n1784 = 16'hd555 >> { PKSi_64_, n1141_1, N_N2899, n1146 }; + assign n1146 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2899, PKSi_64_, n1147 }; + assign n1147 = 16'h5d7f >> { Pkey_147_, Pkey_139_, Pencrypt_0_, Pstart_0_ }; + assign n1025 = 16'hd555 >> { PKSi_161_, n1141_1, N_N2770, n1149_1 }; + assign n1149_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2770, PKSi_161_, n1150 }; + assign n1150 = 16'h5d7f >> { Pkey_155_, Pkey_147_, Pencrypt_0_, Pstart_0_ }; + assign n1089 = 16'hd555 >> { PKSi_145_, n1141_1, PKSi_51_, n1152 }; + assign n1152 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_51_, PKSi_145_, n1153_1 }; + assign n1153_1 = 16'h5d7f >> { Pkey_132_, Pkey_155_, Pencrypt_0_, Pstart_0_ }; + assign n1061 = 16'hd555 >> { PKSi_152_, n1141_1, PKSi_60_, n1155 }; + assign n1155 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_60_, PKSi_152_, n1156 }; + assign n1156 = 16'h5d7f >> { Pkey_140_, Pkey_132_, Pencrypt_0_, Pstart_0_ }; + assign n1157_1 = 4'h2 >> { Pencrypt_0_, Pstart_0_ }; + assign n1158 = 4'h8 >> { Pencrypt_0_, Pstart_0_ }; + assign n1041 = 16'hd555 >> { PKSi_157_, n1141_1, PKSi_58_, n1160 }; + assign n1160 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_58_, PKSi_157_, n1161_1 }; + assign n1161_1 = 16'h5d7f >> { Pkey_156_, Pkey_148_, Pencrypt_0_, Pstart_0_ }; + assign n1049 = 16'hd555 >> { PKSi_155_, n1141_1, PKSi_69_, n1163 }; + assign n1163 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_69_, PKSi_155_, n1164 }; + assign n1164 = 16'h5d7f >> { Pkey_164_, Pkey_156_, Pencrypt_0_, Pstart_0_ }; + assign n1077_1 = 64'hfdfdfdd5fd7dfd55 >> { n1141_1, n1137_1, n1139, PKSi_61_, PKSi_148_, n1166 }; + assign n1166 = 64'h05550ddd07770fff >> { Pkey_172_, Pkey_164_, n1167, n1138, Pencrypt_0_, Pstart_0_ }; + assign n1167 = 4'h1 >> { PKSi_61_, PKSi_148_ }; + assign n1021 = 64'hffd5d5d5d5d5d5d5 >> { n1141_1, N_N2779, PKSi_162_, n1157_1, Pkey_180_, n1169_1 }; + assign n1169_1 = 64'h0040005401410155 >> { n1138, n1137_1, n1139, N_N2779, PKSi_162_, n1170 }; + assign n1170 = 8'h80 >> { Pencrypt_0_, Pstart_0_, Pkey_172_ }; + assign n1789 = 16'hd555 >> { PKSi_49_, n1141_1, N_N2909, n1172 }; + assign n1172 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2909, PKSi_49_, n1173_1 }; + assign n1173_1 = 16'h5d7f >> { Pkey_188_, Pkey_180_, Pencrypt_0_, Pstart_0_ }; + assign n1045 = 16'hd555 >> { PKSi_156_, n1141_1, PKSi_66_, n1175 }; + assign n1175 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_66_, PKSi_156_, n1176 }; + assign n1176 = 16'h5d7f >> { Pkey_133_, Pkey_188_, Pencrypt_0_, Pstart_0_ }; + assign n1057 = 16'hd555 >> { PKSi_153_, n1141_1, PKSi_56_, n1178 }; + assign n1178 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_56_, PKSi_153_, n1179 }; + assign n1179 = 16'h5d7f >> { Pkey_141_, Pkey_133_, Pencrypt_0_, Pstart_0_ }; + assign n1017 = 16'hd555 >> { PKSi_163_, n1141_1, PKSi_48_, n1181_1 }; + assign n1181_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_48_, PKSi_163_, n1182 }; + assign n1182 = 16'h5d7f >> { Pkey_149_, Pkey_141_, Pencrypt_0_, Pstart_0_ }; + assign n1093 = 16'hd555 >> { PKSi_144_, n1141_1, PKSi_70_, n1184 }; + assign n1184 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_70_, PKSi_144_, n1185 }; + assign n1185 = 16'h5d7f >> { Pkey_157_, Pkey_149_, Pencrypt_0_, Pstart_0_ }; + assign n1065 = 16'hd555 >> { PKSi_151_, n1141_1, PKSi_62_, n1187 }; + assign n1187 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_62_, PKSi_151_, n1188 }; + assign n1188 = 16'h5d7f >> { Pkey_165_, Pkey_157_, Pencrypt_0_, Pstart_0_ }; + assign n1037 = 16'hd555 >> { PKSi_158_, n1141_1, PKSi_50_, n1190 }; + assign n1190 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_50_, PKSi_158_, n1191 }; + assign n1191 = 16'h5d7f >> { Pkey_173_, Pkey_165_, Pencrypt_0_, Pstart_0_ }; + assign n1794 = 16'hd555 >> { PKSi_59_, n1141_1, N_N2917, n1193 }; + assign n1193 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2917, PKSi_59_, n1194 }; + assign n1194 = 16'h5d7f >> { Pkey_181_, Pkey_173_, Pencrypt_0_, Pstart_0_ }; + assign n1081_1 = 16'hd555 >> { PKSi_147_, n1141_1, N_N2789, n1196 }; + assign n1196 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2789, PKSi_147_, n1197 }; + assign n1197 = 16'h5d7f >> { Pkey_189_, Pkey_181_, Pencrypt_0_, Pstart_0_ }; + assign n1799_1 = 16'hd555 >> { PKSi_67_, n1141_1, N_N2921, n1199 }; + assign n1199 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2921, PKSi_67_, n1200 }; + assign n1200 = 16'h5d7f >> { Pkey_142_, Pkey_134_, Pencrypt_0_, Pstart_0_ }; + assign n1029 = 16'hd555 >> { PKSi_160_, n1141_1, PKSi_57_, n1202 }; + assign n1202 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_57_, PKSi_160_, n1203 }; + assign n1203 = 16'h5d7f >> { Pkey_150_, Pkey_142_, Pencrypt_0_, Pstart_0_ }; + assign n1053 = 16'hd555 >> { PKSi_154_, n1141_1, PKSi_53_, n1205_1 }; + assign n1205_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_53_, PKSi_154_, n1206 }; + assign n1206 = 16'h5d7f >> { Pkey_158_, Pkey_150_, Pencrypt_0_, Pstart_0_ }; + assign n1001 = 16'hd555 >> { PKSi_167_, n1141_1, PKSi_63_, n1208 }; + assign n1208 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_63_, PKSi_167_, n1209_1 }; + assign n1209_1 = 16'h5d7f >> { Pkey_166_, Pkey_158_, Pencrypt_0_, Pstart_0_ }; + assign n1085 = 16'hd555 >> { PKSi_146_, n1141_1, PKSi_54_, n1211 }; + assign n1211 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_54_, PKSi_146_, n1212 }; + assign n1212 = 16'h5d7f >> { Pkey_174_, Pkey_166_, Pencrypt_0_, Pstart_0_ }; + assign n1069_1 = 16'hd555 >> { PKSi_150_, n1141_1, PKSi_71_, n1214 }; + assign n1214 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_71_, PKSi_150_, n1215 }; + assign n1215 = 16'h5d7f >> { Pkey_182_, Pkey_174_, Pencrypt_0_, Pstart_0_ }; + assign n1005 = 16'hd555 >> { PKSi_166_, n1141_1, PKSi_52_, n1217_1 }; + assign n1217_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_52_, PKSi_166_, n1218 }; + assign n1218 = 16'h5d7f >> { Pkey_190_, Pkey_182_, Pencrypt_0_, Pstart_0_ }; + assign n1121 = 16'hd555 >> { PKSi_135_, n1141_1, PKSi_31_, n1220 }; + assign n1220 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_31_, PKSi_135_, n1221_1 }; + assign n1221_1 = 16'h5d7f >> { Pkey_67_, Pkey_190_, Pencrypt_0_, Pstart_0_ }; + assign n1161 = 16'hd555 >> { PKSi_125_, n1141_1, PKSi_44_, n1223 }; + assign n1223 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_44_, PKSi_125_, n1224 }; + assign n1224 = 16'h5d7f >> { Pkey_75_, Pkey_67_, Pencrypt_0_, Pstart_0_ }; + assign n1804 = 16'hd555 >> { PKSi_40_, n1141_1, N_N2931, n1226 }; + assign n1226 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2931, PKSi_40_, n1227 }; + assign n1227 = 16'h5d7f >> { Pkey_83_, Pkey_75_, Pencrypt_0_, Pstart_0_ }; + assign n1113 = 16'hd555 >> { PKSi_137_, n1141_1, N_N2802, n1229_1 }; + assign n1229_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2802, PKSi_137_, n1230 }; + assign n1230 = 16'h5d7f >> { Pkey_91_, Pkey_83_, Pencrypt_0_, Pstart_0_ }; + assign n1177 = 16'hd555 >> { PKSi_121_, n1141_1, PKSi_27_, n1232 }; + assign n1232 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_27_, PKSi_121_, n1233_1 }; + assign n1233_1 = 16'h5d7f >> { Pkey_68_, Pkey_91_, Pencrypt_0_, Pstart_0_ }; + assign n1149 = 16'hd555 >> { PKSi_128_, n1141_1, PKSi_36_, n1235 }; + assign n1235 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_36_, PKSi_128_, n1236 }; + assign n1236 = 16'h5d7f >> { Pkey_76_, Pkey_68_, Pencrypt_0_, Pstart_0_ }; + assign n1105 = 16'hd555 >> { PKSi_140_, n1141_1, N_N2806, n1238 }; + assign n1238 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2806, PKSi_140_, n1239 }; + assign n1239 = 16'h5d7f >> { Pkey_84_, Pkey_76_, Pencrypt_0_, Pstart_0_ }; + assign n1129 = 16'hd555 >> { PKSi_133_, n1141_1, PKSi_34_, n1241_1 }; + assign n1241_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_34_, PKSi_133_, n1242 }; + assign n1242 = 16'h5d7f >> { Pkey_92_, Pkey_84_, Pencrypt_0_, Pstart_0_ }; + assign n1137 = 16'hd555 >> { PKSi_131_, n1141_1, PKSi_45_, n1244 }; + assign n1244 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_45_, PKSi_131_, n1245_1 }; + assign n1245_1 = 16'h5d7f >> { Pkey_100_, Pkey_92_, Pencrypt_0_, Pstart_0_ }; + assign n1165 = 64'hfffdfddddffddddd >> { n1141_1, n1137_1, PKSi_37_, PKSi_124_, n1247, n1248 }; + assign n1247 = 4'h8 >> { n1157_1, Pkey_44_ }; + assign n1248 = 64'h000e0e0e001f1f1f >> { n1138, Pkey_100_, n1158, n1139, PKSi_37_, PKSi_124_ }; + assign n1109 = 64'hffd5d5d5d5d5d5d5 >> { n1141_1, N_N2811, PKSi_138_, n1157_1, Pkey_116_, n1250 }; + assign n1250 = 64'h0040005401410155 >> { n1138, n1137_1, n1139, N_N2811, PKSi_138_, n1251 }; + assign n1251 = 8'h80 >> { Pkey_44_, Pencrypt_0_, Pstart_0_ }; + assign n1145 = 16'hd555 >> { PKSi_129_, n1141_1, PKSi_25_, n1253_1 }; + assign n1253_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_25_, PKSi_129_, n1254 }; + assign n1254 = 16'h5d7f >> { Pkey_124_, Pkey_116_, Pencrypt_0_, Pstart_0_ }; + assign n1133 = 16'hd555 >> { PKSi_132_, n1141_1, PKSi_42_, n1256 }; + assign n1256 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_42_, PKSi_132_, n1257_1 }; + assign n1257_1 = 16'h5d7f >> { Pkey_69_, Pkey_124_, Pencrypt_0_, Pstart_0_ }; + assign n1809 = 16'hd555 >> { PKSi_32_, n1141_1, N_N2943, n1259 }; + assign n1259 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2943, PKSi_32_, n1260 }; + assign n1260 = 16'h5d7f >> { Pkey_77_, Pkey_69_, Pencrypt_0_, Pstart_0_ }; + assign n1814 = 16'hd555 >> { PKSi_24_, n1141_1, N_N2945, n1262 }; + assign n1262 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2945, PKSi_24_, n1263 }; + assign n1263 = 16'h5d7f >> { Pkey_85_, Pkey_77_, Pencrypt_0_, Pstart_0_ }; + assign n1181 = 16'hd555 >> { PKSi_120_, n1141_1, PKSi_46_, n1265_1 }; + assign n1265_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_46_, PKSi_120_, n1266 }; + assign n1266 = 16'h5d7f >> { Pkey_93_, Pkey_85_, Pencrypt_0_, Pstart_0_ }; + assign n1153 = 16'hd555 >> { PKSi_127_, n1141_1, PKSi_38_, n1268 }; + assign n1268 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_38_, PKSi_127_, n1269_1 }; + assign n1269_1 = 16'h5d7f >> { Pkey_101_, Pkey_93_, Pencrypt_0_, Pstart_0_ }; + assign n1125 = 16'hd555 >> { PKSi_134_, n1141_1, PKSi_26_, n1271 }; + assign n1271 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_26_, PKSi_134_, n1272 }; + assign n1272 = 16'h5d7f >> { Pkey_109_, Pkey_101_, Pencrypt_0_, Pstart_0_ }; + assign n1819 = 16'hd555 >> { PKSi_35_, n1141_1, N_N2950, n1274 }; + assign n1274 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2950, PKSi_35_, n1275 }; + assign n1275 = 16'h5d7f >> { Pkey_117_, Pkey_109_, Pencrypt_0_, Pstart_0_ }; + assign n1169 = 16'hd555 >> { PKSi_123_, n1141_1, N_N2821, n1277_1 }; + assign n1277_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2821, PKSi_123_, n1278 }; + assign n1278 = 16'h5d7f >> { Pkey_125_, Pkey_117_, Pencrypt_0_, Pstart_0_ }; + assign n1101 = 16'hd555 >> { PKSi_141_, n1141_1, PKSi_41_, n1280 }; + assign n1280 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_41_, PKSi_141_, n1281_1 }; + assign n1281_1 = 16'h5d7f >> { Pkey_70_, Pkey_125_, Pencrypt_0_, Pstart_0_ }; + assign n1824 = 16'hd555 >> { PKSi_43_, n1141_1, N_N2954, n1283 }; + assign n1283 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2954, PKSi_43_, n1284 }; + assign n1284 = 16'h5d7f >> { Pkey_78_, Pkey_70_, Pencrypt_0_, Pstart_0_ }; + assign n1117 = 16'hd555 >> { PKSi_136_, n1141_1, PKSi_33_, n1286 }; + assign n1286 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_33_, PKSi_136_, n1287 }; + assign n1287 = 16'h5d7f >> { Pkey_86_, Pkey_78_, Pencrypt_0_, Pstart_0_ }; + assign n1141 = 16'hd555 >> { PKSi_130_, n1141_1, PKSi_29_, n1289_1 }; + assign n1289_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_29_, PKSi_130_, n1290 }; + assign n1290 = 16'h5d7f >> { Pkey_94_, Pkey_86_, Pencrypt_0_, Pstart_0_ }; + assign n1173 = 16'hd555 >> { PKSi_122_, n1141_1, PKSi_30_, n1292 }; + assign n1292 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_30_, PKSi_122_, n1293_1 }; + assign n1293_1 = 16'h5d7f >> { Pkey_110_, Pkey_102_, Pencrypt_0_, Pstart_0_ }; + assign n1157 = 16'hd555 >> { PKSi_126_, n1141_1, PKSi_47_, n1295 }; + assign n1295 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_47_, PKSi_126_, n1296 }; + assign n1296 = 16'h5d7f >> { Pkey_118_, Pkey_110_, Pencrypt_0_, Pstart_0_ }; + assign n1097 = 16'hd555 >> { PKSi_142_, n1141_1, PKSi_28_, n1298 }; + assign n1298 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_28_, PKSi_142_, n1299 }; + assign n1299 = 16'h5d7f >> { Pkey_126_, Pkey_118_, Pencrypt_0_, Pstart_0_ }; + assign n1217 = 16'hd555 >> { PKSi_111_, n1141_1, PKSi_7_, n1301_1 }; + assign n1301_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_7_, PKSi_111_, n1302 }; + assign n1302 = 16'h5d7f >> { Pkey_3_, Pkey_126_, Pencrypt_0_, Pstart_0_ }; + assign n1257 = 16'hd555 >> { PKSi_101_, n1141_1, PKSi_20_, n1304 }; + assign n1304 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_20_, PKSi_101_, n1305_1 }; + assign n1305_1 = 16'h5d7f >> { Pkey_11_, Pkey_3_, Pencrypt_0_, Pstart_0_ }; + assign n1833_1 = 16'hd555 >> { PKSi_16_, n1141_1, N_N2964, n1307 }; + assign n1307 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2964, PKSi_16_, n1308 }; + assign n1308 = 16'h5d7f >> { Pkey_19_, Pkey_11_, Pencrypt_0_, Pstart_0_ }; + assign n1209 = 16'hd555 >> { PKSi_113_, n1141_1, N_N2834, n1310 }; + assign n1310 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2834, PKSi_113_, n1311 }; + assign n1311 = 16'h5d7f >> { Pkey_27_, Pkey_19_, Pencrypt_0_, Pstart_0_ }; + assign n1273 = 16'hd555 >> { PKSi_97_, n1141_1, PKSi_3_, n1313_1 }; + assign n1313_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_3_, PKSi_97_, n1314 }; + assign n1314 = 16'h5d7f >> { Pkey_4_, Pkey_27_, Pencrypt_0_, Pstart_0_ }; + assign n1245 = 16'hd555 >> { PKSi_104_, n1141_1, PKSi_12_, n1316 }; + assign n1316 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_12_, PKSi_104_, n1317_1 }; + assign n1317_1 = 16'h5d7f >> { Pkey_12_, Pkey_4_, Pencrypt_0_, Pstart_0_ }; + assign n1197_1 = 64'hfdfdfdd5fd7dfd55 >> { n1141_1, n1137_1, n1139, N_N2838, PKSi_116_, n1319 }; + assign n1319 = 64'h05550ddd07770fff >> { Pkey_20_, Pkey_12_, n1320, n1138, Pencrypt_0_, Pstart_0_ }; + assign n1320 = 4'h1 >> { N_N2838, PKSi_116_ }; + assign n1225 = 16'hd555 >> { PKSi_109_, n1141_1, PKSi_10_, n1322 }; + assign n1322 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_10_, PKSi_109_, n1323 }; + assign n1323 = 16'h5d7f >> { Pkey_28_, Pkey_20_, Pencrypt_0_, Pstart_0_ }; + assign n1233 = 16'hd555 >> { PKSi_107_, n1141_1, PKSi_21_, n1325_1 }; + assign n1325_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_21_, PKSi_107_, n1326 }; + assign n1326 = 16'h5d7f >> { Pkey_36_, Pkey_28_, Pencrypt_0_, Pstart_0_ }; + assign n1261 = 64'hfffdfddddffddddd >> { n1141_1, n1137_1, PKSi_13_, PKSi_100_, n1247, n1328 }; + assign n1328 = 64'h000e0e0e001f1f1f >> { n1138, Pkey_36_, n1158, n1139, PKSi_13_, PKSi_100_ }; + assign n1205 = 64'hdfffdddfdffddddd >> { n1138, n1137_1, N_N2843, PKSi_114_, n1251, n1330 }; + assign n1330 = 64'h00171717001f1f1f >> { n1141_1, Pkey_52_, n1157_1, n1139, N_N2843, PKSi_114_ }; + assign n1241 = 16'hd555 >> { PKSi_105_, n1141_1, PKSi_1_, n1332 }; + assign n1332 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_1_, PKSi_105_, n1333_1 }; + assign n1333_1 = 16'h5d7f >> { Pkey_60_, Pkey_52_, Pencrypt_0_, Pstart_0_ }; + assign n1229 = 16'hd555 >> { PKSi_108_, n1141_1, PKSi_18_, n1335 }; + assign n1335 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_18_, PKSi_108_, n1336 }; + assign n1336 = 16'h5d7f >> { Pkey_5_, Pkey_60_, Pencrypt_0_, Pstart_0_ }; + assign n1838 = 16'hd555 >> { PKSi_8_, n1141_1, N_N2976, n1338 }; + assign n1338 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2976, PKSi_8_, n1339 }; + assign n1339 = 16'h5d7f >> { Pkey_13_, Pkey_5_, Pencrypt_0_, Pstart_0_ }; + assign n1201 = 16'hd555 >> { PKSi_115_, n1141_1, PKSi_0_, n1341_1 }; + assign n1341_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_0_, PKSi_115_, n1342 }; + assign n1342 = 16'h5d7f >> { Pkey_21_, Pkey_13_, Pencrypt_0_, Pstart_0_ }; + assign n1277 = 16'hd555 >> { PKSi_96_, n1141_1, PKSi_22_, n1344 }; + assign n1344 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_22_, PKSi_96_, n1345_1 }; + assign n1345_1 = 16'h5d7f >> { Pkey_29_, Pkey_21_, Pencrypt_0_, Pstart_0_ }; + assign n1249 = 16'hd555 >> { PKSi_103_, n1141_1, PKSi_14_, n1347 }; + assign n1347 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_14_, PKSi_103_, n1348 }; + assign n1348 = 16'h5d7f >> { Pkey_37_, Pkey_29_, Pencrypt_0_, Pstart_0_ }; + assign n1221 = 16'hd555 >> { PKSi_110_, n1141_1, PKSi_2_, n1350 }; + assign n1350 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_2_, PKSi_110_, n1351 }; + assign n1351 = 16'h5d7f >> { Pkey_45_, Pkey_37_, Pencrypt_0_, Pstart_0_ }; + assign n1843 = 16'hd555 >> { PKSi_11_, n1141_1, N_N2982, n1353_1 }; + assign n1353_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2982, PKSi_11_, n1354 }; + assign n1354 = 16'h5d7f >> { Pkey_53_, Pkey_45_, Pencrypt_0_, Pstart_0_ }; + assign n1265 = 16'hd555 >> { PKSi_99_, n1141_1, N_N2853, n1356 }; + assign n1356 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2853, PKSi_99_, n1357_1 }; + assign n1357_1 = 16'h5d7f >> { Pkey_61_, Pkey_53_, Pencrypt_0_, Pstart_0_ }; + assign n1193_1 = 16'hd555 >> { PKSi_117_, n1141_1, PKSi_17_, n1359 }; + assign n1359 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_17_, PKSi_117_, n1360 }; + assign n1360 = 16'h5d7f >> { Pkey_6_, Pkey_61_, Pencrypt_0_, Pstart_0_ }; + assign n1848 = 16'hd555 >> { PKSi_19_, n1141_1, N_N2986, n1362 }; + assign n1362 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2986, PKSi_19_, n1363 }; + assign n1363 = 16'h5d7f >> { Pkey_14_, Pkey_6_, Pencrypt_0_, Pstart_0_ }; + assign n1213 = 16'hd555 >> { PKSi_112_, n1141_1, PKSi_9_, n1365_1 }; + assign n1365_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_9_, PKSi_112_, n1366 }; + assign n1366 = 16'h5d7f >> { Pkey_22_, Pkey_14_, Pencrypt_0_, Pstart_0_ }; + assign n1237 = 16'hd555 >> { PKSi_106_, n1141_1, PKSi_5_, n1368 }; + assign n1368 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_5_, PKSi_106_, n1369_1 }; + assign n1369_1 = 16'h5d7f >> { Pkey_30_, Pkey_22_, Pencrypt_0_, Pstart_0_ }; + assign n1185_1 = 16'hd555 >> { PKSi_119_, n1141_1, PKSi_15_, n1371 }; + assign n1371 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_15_, PKSi_119_, n1372 }; + assign n1372 = 16'h5d7f >> { Pkey_38_, Pkey_30_, Pencrypt_0_, Pstart_0_ }; + assign n1269 = 16'hd555 >> { PKSi_98_, n1141_1, PKSi_6_, n1374 }; + assign n1374 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_6_, PKSi_98_, n1375 }; + assign n1375 = 16'h5d7f >> { Pkey_46_, Pkey_38_, Pencrypt_0_, Pstart_0_ }; + assign n1253 = 16'hd555 >> { PKSi_102_, n1141_1, PKSi_23_, n1377_1 }; + assign n1377_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_23_, PKSi_102_, n1378 }; + assign n1378 = 16'h5d7f >> { Pkey_54_, Pkey_46_, Pencrypt_0_, Pstart_0_ }; + assign n1189_1 = 16'hd555 >> { PKSi_118_, n1141_1, PKSi_4_, n1380 }; + assign n1380 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_4_, PKSi_118_, n1381_1 }; + assign n1381_1 = 16'h5d7f >> { Pkey_62_, Pkey_54_, Pencrypt_0_, Pstart_0_ }; + assign n1337 = 16'h55d5 >> { n1386, PKSi_79_, PKSi_183_, n1383 }; + assign n1383 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_79_, PKSi_183_, n1385_1 }; + assign n1384 = 64'h00000000f77e0000 >> { Pstart_0_, Pencrypt_0_, Pcount_0_, Pcount_3_, Pcount_1_, Pcount_2_ }; + assign n1385_1 = 16'h5d7f >> { Pkey_227_, Pkey_56_, Pencrypt_0_, Pstart_0_ }; + assign n1386 = 64'hffbfbffeaaaaaaaa >> { Pencrypt_0_, Pcount_0_, Pcount_3_, Pcount_2_, Pcount_1_, Pstart_0_ }; + assign n1293 = 16'h55d5 >> { n1386, PKSi_92_, PKSi_173_, n1388 }; + assign n1388 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_92_, PKSi_173_, n1389_1 }; + assign n1389_1 = 16'h5d7f >> { Pkey_235_, Pkey_227_, Pencrypt_0_, Pstart_0_ }; + assign n1657 = 16'h55d5 >> { n1386, N_N2865, PKSi_88_, n1391 }; + assign n1391 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2865, PKSi_88_, n1392 }; + assign n1392 = 16'h5d7f >> { Pkey_243_, Pkey_235_, Pencrypt_0_, Pstart_0_ }; + assign n1661 = 64'hfd7dfd55fdfdfdd5 >> { n1386, n1384, n1138, N_N2737, PKSi_185_, n1394 }; + assign n1394 = 64'h05550ddd07770fff >> { Pkey_251_, Pkey_243_, n1395, n1139, Pencrypt_0_, Pstart_0_ }; + assign n1395 = 4'h1 >> { N_N2737, PKSi_185_ }; + assign n1353 = 16'h55d5 >> { n1386, PKSi_75_, PKSi_169_, n1397_1 }; + assign n1397_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_75_, PKSi_169_, n1398 }; + assign n1398 = 16'h5d7f >> { Pkey_194_, Pkey_251_, Pencrypt_0_, Pstart_0_ }; + assign n1317 = 16'h55d5 >> { n1386, PKSi_84_, PKSi_176_, n1400 }; + assign n1400 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_84_, PKSi_176_, n1401_1 }; + assign n1401_1 = 16'h5d7f >> { Pkey_202_, Pkey_194_, Pencrypt_0_, Pstart_0_ }; + assign n1666 = 16'h55d5 >> { n1386, N_N2741, PKSi_188_, n1403 }; + assign n1403 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2741, PKSi_188_, n1404 }; + assign n1404 = 16'h5d7f >> { Pkey_210_, Pkey_202_, Pencrypt_0_, Pstart_0_ }; + assign n1325 = 16'h55d5 >> { n1386, PKSi_82_, PKSi_168_, n1406 }; + assign n1406 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_82_, PKSi_168_, n1407 }; + assign n1407 = 16'h5d7f >> { Pkey_218_, Pkey_210_, Pencrypt_0_, Pstart_0_ }; + assign n1289 = 16'h55d5 >> { n1386, PKSi_93_, PKSi_179_, n1409_1 }; + assign n1409_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_93_, PKSi_179_, n1410 }; + assign n1410 = 16'h5d7f >> { Pkey_226_, Pkey_218_, Pencrypt_0_, Pstart_0_ }; + assign n1313 = 16'h55d5 >> { n1386, PKSi_85_, PKSi_172_, n1412 }; + assign n1412 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_85_, PKSi_172_, n1413_1 }; + assign n1413_1 = 16'h5d7f >> { Pkey_234_, Pkey_226_, Pencrypt_0_, Pstart_0_ }; + assign n1671 = 16'h55d5 >> { n1386, N_N2746, PKSi_186_, n1415 }; + assign n1415 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2746, PKSi_186_, n1416 }; + assign n1416 = 16'h5d7f >> { Pkey_242_, Pkey_234_, Pencrypt_0_, Pstart_0_ }; + assign n1361 = 16'h55d5 >> { n1386, PKSi_73_, PKSi_177_, n1418 }; + assign n1418 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_73_, PKSi_177_, n1419 }; + assign n1419 = 16'h5d7f >> { Pkey_250_, Pkey_242_, Pencrypt_0_, Pstart_0_ }; + assign n1676 = 16'h55d5 >> { n1386, N_N2749, PKSi_180_, n1421_1 }; + assign n1421_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2749, PKSi_180_, n1422 }; + assign n1422 = 16'h5d7f >> { Pkey_193_, Pkey_250_, Pencrypt_0_, Pstart_0_ }; + assign n1333 = 16'h55d5 >> { n1386, N_N2877, PKSi_80_, n1424 }; + assign n1424 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2877, PKSi_80_, n1425_1 }; + assign n1425_1 = 16'h5d7f >> { Pkey_201_, Pkey_193_, Pencrypt_0_, Pstart_0_ }; + assign n1285 = 16'h55d5 >> { n1386, N_N2881, PKSi_94_, n1427 }; + assign n1427 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2881, PKSi_94_, n1428 }; + assign n1428 = 16'h5d7f >> { Pkey_217_, Pkey_209_, Pencrypt_0_, Pstart_0_ }; + assign n1309 = 16'h55d5 >> { n1386, PKSi_86_, PKSi_175_, n1430 }; + assign n1430 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_86_, PKSi_175_, n1431 }; + assign n1431 = 16'h5d7f >> { Pkey_225_, Pkey_217_, Pencrypt_0_, Pstart_0_ }; + assign n1357 = 16'h55d5 >> { n1386, PKSi_74_, PKSi_182_, n1433_1 }; + assign n1433_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_74_, PKSi_182_, n1434 }; + assign n1434 = 16'h5d7f >> { Pkey_233_, Pkey_225_, Pencrypt_0_, Pstart_0_ }; + assign n1321 = 16'h55d5 >> { n1386, N_N2885, PKSi_83_, n1436 }; + assign n1436 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2885, PKSi_83_, n1437_1 }; + assign n1437_1 = 16'h5d7f >> { Pkey_241_, Pkey_233_, Pencrypt_0_, Pstart_0_ }; + assign n1681 = 16'h55d5 >> { n1386, N_N2757, PKSi_171_, n1439 }; + assign n1439 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2757, PKSi_171_, n1440 }; + assign n1440 = 16'h5d7f >> { Pkey_249_, Pkey_241_, Pencrypt_0_, Pstart_0_ }; + assign n1301 = 16'h55d5 >> { n1386, PKSi_89_, PKSi_189_, n1442 }; + assign n1442 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_89_, PKSi_189_, n1443 }; + assign n1443 = 16'h5d7f >> { Pkey_192_, Pkey_249_, Pencrypt_0_, Pstart_0_ }; + assign n1297 = 16'h55d5 >> { n1386, N_N2889, PKSi_91_, n1445_1 }; + assign n1445_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2889, PKSi_91_, n1446 }; + assign n1446 = 16'h5d7f >> { Pkey_200_, Pkey_192_, Pencrypt_0_, Pstart_0_ }; + assign n1329 = 16'h55d5 >> { n1386, PKSi_81_, PKSi_184_, n1448 }; + assign n1448 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_81_, PKSi_184_, n1449_1 }; + assign n1449_1 = 16'h5d7f >> { Pkey_208_, Pkey_200_, Pencrypt_0_, Pstart_0_ }; + assign n1345 = 16'h55d5 >> { n1386, PKSi_77_, PKSi_178_, n1451 }; + assign n1451 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_77_, PKSi_178_, n1452 }; + assign n1452 = 16'h5d7f >> { Pkey_216_, Pkey_208_, Pencrypt_0_, Pstart_0_ }; + assign n1305 = 16'h55d5 >> { n1386, PKSi_87_, PKSi_187_, n1454 }; + assign n1454 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_87_, PKSi_187_, n1455 }; + assign n1455 = 16'h5d7f >> { Pkey_224_, Pkey_216_, Pencrypt_0_, Pstart_0_ }; + assign n1281 = 16'h55d5 >> { n1386, PKSi_95_, PKSi_174_, n1457_1 }; + assign n1457_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_95_, PKSi_174_, n1458 }; + assign n1458 = 16'h5d7f >> { Pkey_240_, Pkey_232_, Pencrypt_0_, Pstart_0_ }; + assign n1349 = 16'h55d5 >> { n1386, PKSi_76_, PKSi_190_, n1460 }; + assign n1460 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_76_, PKSi_190_, n1461_1 }; + assign n1461_1 = 16'h5d7f >> { Pkey_248_, Pkey_240_, Pencrypt_0_, Pstart_0_ }; + assign n1433 = 16'h55d5 >> { n1386, PKSi_55_, PKSi_159_, n1463 }; + assign n1463 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_55_, PKSi_159_, n1464 }; + assign n1464 = 16'h5d7f >> { Pkey_163_, Pkey_248_, Pencrypt_0_, Pstart_0_ }; + assign n1381 = 16'h55d5 >> { n1386, PKSi_68_, PKSi_149_, n1466 }; + assign n1466 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_68_, PKSi_149_, n1467 }; + assign n1467 = 16'h5d7f >> { Pkey_171_, Pkey_163_, Pencrypt_0_, Pstart_0_ }; + assign n1397 = 16'h55d5 >> { n1386, N_N2899, PKSi_64_, n1469_1 }; + assign n1469_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2899, PKSi_64_, n1470 }; + assign n1470 = 16'h5d7f >> { Pkey_179_, Pkey_171_, Pencrypt_0_, Pstart_0_ }; + assign n1686 = 16'h55d5 >> { n1386, N_N2770, PKSi_161_, n1472 }; + assign n1472 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2770, PKSi_161_, n1473_1 }; + assign n1473_1 = 16'h5d7f >> { Pkey_187_, Pkey_179_, Pencrypt_0_, Pstart_0_ }; + assign n1449 = 16'h55d5 >> { n1386, PKSi_51_, PKSi_145_, n1475 }; + assign n1475 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_51_, PKSi_145_, n1476 }; + assign n1476 = 16'h5d7f >> { Pkey_130_, Pkey_187_, Pencrypt_0_, Pstart_0_ }; + assign n1413 = 16'h55d5 >> { n1386, PKSi_60_, PKSi_152_, n1478 }; + assign n1478 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_60_, PKSi_152_, n1479 }; + assign n1479 = 16'h5d7f >> { Pkey_138_, Pkey_130_, Pencrypt_0_, Pstart_0_ }; + assign n1691 = 16'h55d5 >> { n1386, N_N2774, PKSi_164_, n1481_1 }; + assign n1481_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2774, PKSi_164_, n1482 }; + assign n1482 = 16'h5d7f >> { Pkey_146_, Pkey_138_, Pencrypt_0_, Pstart_0_ }; + assign n1421 = 16'h55d5 >> { n1386, PKSi_58_, PKSi_157_, n1484 }; + assign n1484 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_58_, PKSi_157_, n1485_1 }; + assign n1485_1 = 16'h5d7f >> { Pkey_154_, Pkey_146_, Pencrypt_0_, Pstart_0_ }; + assign n1377 = 16'h55d5 >> { n1386, PKSi_69_, PKSi_155_, n1487 }; + assign n1487 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_69_, PKSi_155_, n1488 }; + assign n1488 = 16'h5d7f >> { Pkey_162_, Pkey_154_, Pencrypt_0_, Pstart_0_ }; + assign n1409 = 64'hfd7dfd55fdfdfdd5 >> { n1386, n1384, n1138, PKSi_61_, PKSi_148_, n1490 }; + assign n1490 = 64'h05550ddd07770fff >> { Pkey_170_, Pkey_162_, n1167, n1139, Pencrypt_0_, Pstart_0_ }; + assign n1696 = 16'h55d5 >> { n1386, N_N2779, PKSi_162_, n1492 }; + assign n1492 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2779, PKSi_162_, n1493_1 }; + assign n1493_1 = 16'h5d7f >> { Pkey_178_, Pkey_170_, Pencrypt_0_, Pstart_0_ }; + assign n1457 = 16'h55d5 >> { n1386, N_N2909, PKSi_49_, n1495 }; + assign n1495 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2909, PKSi_49_, n1496 }; + assign n1496 = 16'h5d7f >> { Pkey_186_, Pkey_178_, Pencrypt_0_, Pstart_0_ }; + assign n1389 = 16'h55d5 >> { n1386, PKSi_66_, PKSi_156_, n1498 }; + assign n1498 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_66_, PKSi_156_, n1499 }; + assign n1499 = 16'h5d7f >> { Pkey_129_, Pkey_186_, Pencrypt_0_, Pstart_0_ }; + assign n1429 = 16'h55d5 >> { n1386, PKSi_56_, PKSi_153_, n1501_1 }; + assign n1501_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_56_, PKSi_153_, n1502 }; + assign n1502 = 16'h5d7f >> { Pkey_137_, Pkey_129_, Pencrypt_0_, Pstart_0_ }; + assign n1461 = 16'h55d5 >> { n1386, PKSi_48_, PKSi_163_, n1504 }; + assign n1504 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_48_, PKSi_163_, n1505_1 }; + assign n1505_1 = 16'h5d7f >> { Pkey_145_, Pkey_137_, Pencrypt_0_, Pstart_0_ }; + assign n1373 = 16'h55d5 >> { n1386, PKSi_70_, PKSi_144_, n1507 }; + assign n1507 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_70_, PKSi_144_, n1508 }; + assign n1508 = 16'h5d7f >> { Pkey_153_, Pkey_145_, Pencrypt_0_, Pstart_0_ }; + assign n1405 = 16'h55d5 >> { n1386, PKSi_62_, PKSi_151_, n1510 }; + assign n1510 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_62_, PKSi_151_, n1511 }; + assign n1511 = 16'h5d7f >> { Pkey_161_, Pkey_153_, Pencrypt_0_, Pstart_0_ }; + assign n1453 = 16'h55d5 >> { n1386, PKSi_50_, PKSi_158_, n1513_1 }; + assign n1513_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_50_, PKSi_158_, n1514 }; + assign n1514 = 16'h5d7f >> { Pkey_169_, Pkey_161_, Pencrypt_0_, Pstart_0_ }; + assign n1417 = 16'h55d5 >> { n1386, N_N2917, PKSi_59_, n1516 }; + assign n1516 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2917, PKSi_59_, n1517_1 }; + assign n1517_1 = 16'h5d7f >> { Pkey_177_, Pkey_169_, Pencrypt_0_, Pstart_0_ }; + assign n1701 = 16'h55d5 >> { n1386, N_N2789, PKSi_147_, n1519 }; + assign n1519 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2789, PKSi_147_, n1520 }; + assign n1520 = 16'h5d7f >> { Pkey_185_, Pkey_177_, Pencrypt_0_, Pstart_0_ }; + assign n1385 = 16'h55d5 >> { n1386, N_N2921, PKSi_67_, n1522 }; + assign n1522 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2921, PKSi_67_, n1523 }; + assign n1523 = 16'h5d7f >> { Pkey_136_, Pkey_128_, Pencrypt_0_, Pstart_0_ }; + assign n1425 = 16'h55d5 >> { n1386, PKSi_57_, PKSi_160_, n1525_1 }; + assign n1525_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_57_, PKSi_160_, n1526 }; + assign n1526 = 16'h5d7f >> { Pkey_144_, Pkey_136_, Pencrypt_0_, Pstart_0_ }; + assign n1441 = 16'h55d5 >> { n1386, PKSi_53_, PKSi_154_, n1528 }; + assign n1528 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_53_, PKSi_154_, n1529_1 }; + assign n1529_1 = 16'h5d7f >> { Pkey_152_, Pkey_144_, Pencrypt_0_, Pstart_0_ }; + assign n1401 = 16'h55d5 >> { n1386, PKSi_63_, PKSi_167_, n1531 }; + assign n1531 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_63_, PKSi_167_, n1532 }; + assign n1532 = 16'h5d7f >> { Pkey_160_, Pkey_152_, Pencrypt_0_, Pstart_0_ }; + assign n1437 = 16'h55d5 >> { n1386, PKSi_54_, PKSi_146_, n1534 }; + assign n1534 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_54_, PKSi_146_, n1535 }; + assign n1535 = 16'h5d7f >> { Pkey_168_, Pkey_160_, Pencrypt_0_, Pstart_0_ }; + assign n1369 = 16'h55d5 >> { n1386, PKSi_71_, PKSi_150_, n1537_1 }; + assign n1537_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_71_, PKSi_150_, n1538 }; + assign n1538 = 16'h5d7f >> { Pkey_176_, Pkey_168_, Pencrypt_0_, Pstart_0_ }; + assign n1445 = 16'h55d5 >> { n1386, PKSi_52_, PKSi_166_, n1540 }; + assign n1540 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_52_, PKSi_166_, n1541_1 }; + assign n1541_1 = 16'h5d7f >> { Pkey_184_, Pkey_176_, Pencrypt_0_, Pstart_0_ }; + assign n1529 = 16'h55d5 >> { n1386, PKSi_31_, PKSi_135_, n1543 }; + assign n1543 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_31_, PKSi_135_, n1544 }; + assign n1544 = 16'h5d7f >> { Pkey_99_, Pkey_184_, Pencrypt_0_, Pstart_0_ }; + assign n1477 = 16'h55d5 >> { n1386, PKSi_44_, PKSi_125_, n1546 }; + assign n1546 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_44_, PKSi_125_, n1547 }; + assign n1547 = 16'h5d7f >> { Pkey_107_, Pkey_99_, Pencrypt_0_, Pstart_0_ }; + assign n1706 = 16'h55d5 >> { n1386, N_N2802, PKSi_137_, n1549_1 }; + assign n1549_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2802, PKSi_137_, n1550 }; + assign n1550 = 16'h5d7f >> { Pkey_123_, Pkey_115_, Pencrypt_0_, Pstart_0_ }; + assign n1545 = 16'h55d5 >> { n1386, PKSi_27_, PKSi_121_, n1552 }; + assign n1552 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_27_, PKSi_121_, n1553_1 }; + assign n1553_1 = 16'h5d7f >> { Pkey_66_, Pkey_123_, Pencrypt_0_, Pstart_0_ }; + assign n1509 = 16'h55d5 >> { n1386, PKSi_36_, PKSi_128_, n1555 }; + assign n1555 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_36_, PKSi_128_, n1556 }; + assign n1556 = 16'h5d7f >> { Pkey_74_, Pkey_66_, Pencrypt_0_, Pstart_0_ }; + assign n1711 = 16'h55d5 >> { n1386, N_N2806, PKSi_140_, n1558 }; + assign n1558 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2806, PKSi_140_, n1559 }; + assign n1559 = 16'h5d7f >> { Pkey_82_, Pkey_74_, Pencrypt_0_, Pstart_0_ }; + assign n1517 = 16'h55d5 >> { n1386, PKSi_34_, PKSi_133_, n1561_1 }; + assign n1561_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_34_, PKSi_133_, n1562 }; + assign n1562 = 16'h5d7f >> { Pkey_90_, Pkey_82_, Pencrypt_0_, Pstart_0_ }; + assign n1473 = 16'h55d5 >> { n1386, PKSi_45_, PKSi_131_, n1564 }; + assign n1564 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_45_, PKSi_131_, n1565_1 }; + assign n1565_1 = 16'h5d7f >> { Pkey_98_, Pkey_90_, Pencrypt_0_, Pstart_0_ }; + assign n1505 = 16'h55d5 >> { n1386, PKSi_37_, PKSi_124_, n1567 }; + assign n1567 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_37_, PKSi_124_, n1568 }; + assign n1568 = 16'h5d7f >> { Pkey_106_, Pkey_98_, Pencrypt_0_, Pstart_0_ }; + assign n1716 = 16'h55d5 >> { n1386, N_N2811, PKSi_138_, n1570 }; + assign n1570 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2811, PKSi_138_, n1571 }; + assign n1571 = 16'h5d7f >> { Pkey_114_, Pkey_106_, Pencrypt_0_, Pstart_0_ }; + assign n1553 = 16'h55d5 >> { n1386, PKSi_25_, PKSi_129_, n1573_1 }; + assign n1573_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_25_, PKSi_129_, n1574 }; + assign n1574 = 16'h5d7f >> { Pkey_122_, Pkey_114_, Pencrypt_0_, Pstart_0_ }; + assign n1485 = 16'h55d5 >> { n1386, PKSi_42_, PKSi_132_, n1576 }; + assign n1576 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_42_, PKSi_132_, n1577_1 }; + assign n1577_1 = 16'h5d7f >> { Pkey_65_, Pkey_122_, Pencrypt_0_, Pstart_0_ }; + assign n1557 = 16'h55d5 >> { n1386, N_N2945, PKSi_24_, n1579 }; + assign n1579 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2945, PKSi_24_, n1580 }; + assign n1580 = 16'h5d7f >> { Pkey_81_, Pkey_73_, Pencrypt_0_, Pstart_0_ }; + assign n1469 = 16'h55d5 >> { n1386, PKSi_46_, PKSi_120_, n1582 }; + assign n1582 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_46_, PKSi_120_, n1583 }; + assign n1583 = 16'h5d7f >> { Pkey_89_, Pkey_81_, Pencrypt_0_, Pstart_0_ }; + assign n1501 = 16'h55d5 >> { n1386, PKSi_38_, PKSi_127_, n1585_1 }; + assign n1585_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_38_, PKSi_127_, n1586 }; + assign n1586 = 16'h5d7f >> { Pkey_97_, Pkey_89_, Pencrypt_0_, Pstart_0_ }; + assign n1549 = 16'h55d5 >> { n1386, PKSi_26_, PKSi_134_, n1588 }; + assign n1588 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_26_, PKSi_134_, n1589_1 }; + assign n1589_1 = 16'h5d7f >> { Pkey_105_, Pkey_97_, Pencrypt_0_, Pstart_0_ }; + assign n1513 = 16'h55d5 >> { n1386, N_N2950, PKSi_35_, n1591 }; + assign n1591 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2950, PKSi_35_, n1592 }; + assign n1592 = 16'h5d7f >> { Pkey_113_, Pkey_105_, Pencrypt_0_, Pstart_0_ }; + assign n1721 = 16'h55d5 >> { n1386, N_N2821, PKSi_123_, n1594 }; + assign n1594 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2821, PKSi_123_, n1595 }; + assign n1595 = 16'h5d7f >> { Pkey_121_, Pkey_113_, Pencrypt_0_, Pstart_0_ }; + assign n1489 = 16'h55d5 >> { n1386, PKSi_41_, PKSi_141_, n1597_1 }; + assign n1597_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_41_, PKSi_141_, n1598 }; + assign n1598 = 16'h5d7f >> { Pkey_64_, Pkey_121_, Pencrypt_0_, Pstart_0_ }; + assign n1481 = 16'h55d5 >> { n1386, N_N2954, PKSi_43_, n1600 }; + assign n1600 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2954, PKSi_43_, n1601_1 }; + assign n1601_1 = 16'h5d7f >> { Pkey_72_, Pkey_64_, Pencrypt_0_, Pstart_0_ }; + assign n1521 = 16'h55d5 >> { n1386, PKSi_33_, PKSi_136_, n1603 }; + assign n1603 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_33_, PKSi_136_, n1604 }; + assign n1604 = 16'h5d7f >> { Pkey_80_, Pkey_72_, Pencrypt_0_, Pstart_0_ }; + assign n1537 = 16'h55d5 >> { n1386, PKSi_29_, PKSi_130_, n1606 }; + assign n1606 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_29_, PKSi_130_, n1607 }; + assign n1607 = 16'h5d7f >> { Pkey_88_, Pkey_80_, Pencrypt_0_, Pstart_0_ }; + assign n1533 = 16'h55d5 >> { n1386, PKSi_30_, PKSi_122_, n1609_1 }; + assign n1609_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_30_, PKSi_122_, n1610 }; + assign n1610 = 16'h5d7f >> { Pkey_104_, Pkey_96_, Pencrypt_0_, Pstart_0_ }; + assign n1465 = 16'h55d5 >> { n1386, PKSi_47_, PKSi_126_, n1612 }; + assign n1612 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_47_, PKSi_126_, n1613_1 }; + assign n1613_1 = 16'h5d7f >> { Pkey_112_, Pkey_104_, Pencrypt_0_, Pstart_0_ }; + assign n1541 = 16'h55d5 >> { n1386, PKSi_28_, PKSi_142_, n1615 }; + assign n1615 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_28_, PKSi_142_, n1616 }; + assign n1616 = 16'h5d7f >> { Pkey_120_, Pkey_112_, Pencrypt_0_, Pstart_0_ }; + assign n1625 = 16'h55d5 >> { n1386, PKSi_7_, PKSi_111_, n1618 }; + assign n1618 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_7_, PKSi_111_, n1619 }; + assign n1619 = 16'h5d7f >> { Pkey_35_, Pkey_120_, Pencrypt_0_, Pstart_0_ }; + assign n1573 = 16'h55d5 >> { n1386, PKSi_20_, PKSi_101_, n1621_1 }; + assign n1621_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_20_, PKSi_101_, n1622 }; + assign n1622 = 16'h5d7f >> { Pkey_43_, Pkey_35_, Pencrypt_0_, Pstart_0_ }; + assign n1589 = 16'h55d5 >> { n1386, N_N2964, PKSi_16_, n1624 }; + assign n1624 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2964, PKSi_16_, n1625_1 }; + assign n1625_1 = 16'h5d7f >> { Pkey_51_, Pkey_43_, Pencrypt_0_, Pstart_0_ }; + assign n1726 = 16'h55d5 >> { n1386, N_N2834, PKSi_113_, n1627 }; + assign n1627 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2834, PKSi_113_, n1628 }; + assign n1628 = 16'h5d7f >> { Pkey_59_, Pkey_51_, Pencrypt_0_, Pstart_0_ }; + assign n1641 = 16'h55d5 >> { n1386, PKSi_3_, PKSi_97_, n1630 }; + assign n1630 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_3_, PKSi_97_, n1631 }; + assign n1631 = 16'h5d7f >> { Pkey_2_, Pkey_59_, Pencrypt_0_, Pstart_0_ }; + assign n1605 = 16'h55d5 >> { n1386, PKSi_12_, PKSi_104_, n1633_1 }; + assign n1633_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_12_, PKSi_104_, n1634 }; + assign n1634 = 16'h5d7f >> { Pkey_10_, Pkey_2_, Pencrypt_0_, Pstart_0_ }; + assign n1731 = 64'hfd7dfd55fdfdfdd5 >> { n1386, n1384, n1138, N_N2838, PKSi_116_, n1636 }; + assign n1636 = 64'h05550ddd07770fff >> { Pkey_18_, Pkey_10_, n1320, n1139, Pencrypt_0_, Pstart_0_ }; + assign n1613 = 16'h55d5 >> { n1386, PKSi_10_, PKSi_109_, n1638 }; + assign n1638 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_10_, PKSi_109_, n1639 }; + assign n1639 = 16'h5d7f >> { Pkey_26_, Pkey_18_, Pencrypt_0_, Pstart_0_ }; + assign n1569 = 16'h55d5 >> { n1386, PKSi_21_, PKSi_107_, n1641_1 }; + assign n1641_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_21_, PKSi_107_, n1642 }; + assign n1642 = 16'h5d7f >> { Pkey_34_, Pkey_26_, Pencrypt_0_, Pstart_0_ }; + assign n1601 = 16'h55d5 >> { n1386, PKSi_13_, PKSi_100_, n1644 }; + assign n1644 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_13_, PKSi_100_, n1645_1 }; + assign n1645_1 = 16'h5d7f >> { Pkey_42_, Pkey_34_, Pencrypt_0_, Pstart_0_ }; + assign n1736 = 16'h55d5 >> { n1386, N_N2843, PKSi_114_, n1647 }; + assign n1647 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2843, PKSi_114_, n1648 }; + assign n1648 = 16'h5d7f >> { Pkey_50_, Pkey_42_, Pencrypt_0_, Pstart_0_ }; + assign n1649 = 16'h55d5 >> { n1386, PKSi_1_, PKSi_105_, n1650 }; + assign n1650 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_1_, PKSi_105_, n1651 }; + assign n1651 = 16'h5d7f >> { Pkey_58_, Pkey_50_, Pencrypt_0_, Pstart_0_ }; + assign n1581 = 16'h55d5 >> { n1386, PKSi_18_, PKSi_108_, n1653_1 }; + assign n1653_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_18_, PKSi_108_, n1654 }; + assign n1654 = 16'h5d7f >> { Pkey_1_, Pkey_58_, Pencrypt_0_, Pstart_0_ }; + assign n1621 = 16'h55d5 >> { n1386, N_N2976, PKSi_8_, n1656 }; + assign n1656 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2976, PKSi_8_, n1657_1 }; + assign n1657_1 = 16'h5d7f >> { Pkey_9_, Pkey_1_, Pencrypt_0_, Pstart_0_ }; + assign n1653 = 16'h55d5 >> { n1386, PKSi_0_, PKSi_115_, n1659 }; + assign n1659 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_0_, PKSi_115_, n1660 }; + assign n1660 = 16'h5d7f >> { Pkey_17_, Pkey_9_, Pencrypt_0_, Pstart_0_ }; + assign n1565 = 16'h55d5 >> { n1386, PKSi_22_, PKSi_96_, n1662 }; + assign n1662 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_22_, PKSi_96_, n1663 }; + assign n1663 = 16'h5d7f >> { Pkey_25_, Pkey_17_, Pencrypt_0_, Pstart_0_ }; + assign n1597 = 16'h55d5 >> { n1386, PKSi_14_, PKSi_103_, n1665 }; + assign n1665 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_14_, PKSi_103_, n1666_1 }; + assign n1666_1 = 16'h5d7f >> { Pkey_33_, Pkey_25_, Pencrypt_0_, Pstart_0_ }; + assign n1609 = 16'h55d5 >> { n1386, N_N2982, PKSi_11_, n1668 }; + assign n1668 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2982, PKSi_11_, n1669 }; + assign n1669 = 16'h5d7f >> { Pkey_49_, Pkey_41_, Pencrypt_0_, Pstart_0_ }; + assign n1741 = 16'h55d5 >> { n1386, N_N2853, PKSi_99_, n1671_1 }; + assign n1671_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2853, PKSi_99_, n1672 }; + assign n1672 = 16'h5d7f >> { Pkey_57_, Pkey_49_, Pencrypt_0_, Pstart_0_ }; + assign n1585 = 16'h55d5 >> { n1386, PKSi_17_, PKSi_117_, n1674 }; + assign n1674 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_17_, PKSi_117_, n1675 }; + assign n1675 = 16'h5d7f >> { Pkey_0_, Pkey_57_, Pencrypt_0_, Pstart_0_ }; + assign n1577 = 16'h55d5 >> { n1386, N_N2986, PKSi_19_, n1677 }; + assign n1677 = 64'h008000a8028202aa >> { n1139, n1384, n1138, N_N2986, PKSi_19_, n1678 }; + assign n1678 = 16'h5d7f >> { Pkey_8_, Pkey_0_, Pencrypt_0_, Pstart_0_ }; + assign n1617 = 16'h55d5 >> { n1386, PKSi_9_, PKSi_112_, n1680 }; + assign n1680 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_9_, PKSi_112_, n1681_1 }; + assign n1681_1 = 16'h5d7f >> { Pkey_16_, Pkey_8_, Pencrypt_0_, Pstart_0_ }; + assign n1633 = 16'h55d5 >> { n1386, PKSi_5_, PKSi_106_, n1683 }; + assign n1683 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_5_, PKSi_106_, n1684 }; + assign n1684 = 16'h5d7f >> { Pkey_24_, Pkey_16_, Pencrypt_0_, Pstart_0_ }; + assign n1593 = 16'h55d5 >> { n1386, PKSi_15_, PKSi_119_, n1686_1 }; + assign n1686_1 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_15_, PKSi_119_, n1687 }; + assign n1687 = 16'h5d7f >> { Pkey_32_, Pkey_24_, Pencrypt_0_, Pstart_0_ }; + assign n1629 = 16'h55d5 >> { n1386, PKSi_6_, PKSi_98_, n1689 }; + assign n1689 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_6_, PKSi_98_, n1690 }; + assign n1690 = 16'h5d7f >> { Pkey_40_, Pkey_32_, Pencrypt_0_, Pstart_0_ }; + assign n1561 = 16'h55d5 >> { n1386, PKSi_23_, PKSi_102_, n1692 }; + assign n1692 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_23_, PKSi_102_, n1693 }; + assign n1693 = 16'h5d7f >> { Pkey_48_, Pkey_40_, Pencrypt_0_, Pstart_0_ }; + assign n1637 = 16'h55d5 >> { n1386, PKSi_4_, PKSi_118_, n1695 }; + assign n1695 = 64'h008000a8028202aa >> { n1139, n1384, n1138, PKSi_4_, PKSi_118_, n1696_1 }; + assign n1696_1 = 16'h57df >> { Pkey_48_, Pkey_56_, Pencrypt_0_, Pstart_0_ }; + assign Pnew_count_3_ = 64'h06fc0cfc0cfc0cf9 >> { Pcount_0_, Pcount_2_, Pencrypt_0_, Pstart_0_, Pcount_3_, Pcount_1_ }; + assign Pnew_count_2_ = 32'd1431661769 >> { Pstart_0_, Pcount_0_, Pcount_1_, Pcount_2_, Pencrypt_0_ }; + assign Pnew_count_1_ = 16'h5569 >> { Pstart_0_, Pcount_0_, Pcount_1_, Pencrypt_0_ }; + assign Pnew_count_0_ = 8'h27 >> { Pcount_0_, Pencrypt_0_, Pstart_0_ }; + assign Pdata_ready_0_ = 64'h0000000080000001 >> { Pstart_0_, Pencrypt_0_, Pcount_0_, Pcount_2_, Pcount_1_, Pcount_3_ }; + assign n945 = 16'hd555 >> { PKSi_183_, n1141_1, PKSi_79_, n1703 }; + assign n1703 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_79_, PKSi_183_, n1704 }; + assign n1704 = 16'h5d7f >> { Pkey_195_, Pkey_62_, Pencrypt_0_, Pstart_0_ }; + assign n981 = 16'hd555 >> { PKSi_173_, n1141_1, PKSi_92_, n1706_1 }; + assign n1706_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_92_, PKSi_173_, n1707 }; + assign n1707 = 16'h5d7f >> { Pkey_203_, Pkey_195_, Pencrypt_0_, Pstart_0_ }; + assign n1746 = 16'hd555 >> { PKSi_88_, n1141_1, N_N2865, n1709 }; + assign n1709 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2865, PKSi_88_, n1710 }; + assign n1710 = 16'h5d7f >> { Pkey_211_, Pkey_203_, Pencrypt_0_, Pstart_0_ }; + assign n937 = 64'hfdfdfdd5fd7dfd55 >> { n1141_1, n1137_1, n1139, N_N2737, PKSi_185_, n1712 }; + assign n1712 = 64'h05550ddd07770fff >> { Pkey_219_, Pkey_211_, n1395, n1138, Pencrypt_0_, Pstart_0_ }; + assign n997 = 16'hd555 >> { PKSi_169_, n1141_1, PKSi_75_, n1714 }; + assign n1714 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_75_, PKSi_169_, n1715 }; + assign n1715 = 16'h5d7f >> { Pkey_196_, Pkey_219_, Pencrypt_0_, Pstart_0_ }; + assign n969_1 = 16'hd555 >> { PKSi_176_, n1141_1, PKSi_84_, n1717 }; + assign n1717 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_84_, PKSi_176_, n1718 }; + assign n1718 = 16'h5d7f >> { Pkey_204_, Pkey_196_, Pencrypt_0_, Pstart_0_ }; + assign n929 = 16'hd555 >> { PKSi_188_, n1141_1, N_N2741, n1720 }; + assign n1720 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2741, PKSi_188_, n1721_1 }; + assign n1721_1 = 16'h5d7f >> { Pkey_212_, Pkey_204_, Pencrypt_0_, Pstart_0_ }; + assign n1751 = 16'hd555 >> { PKSi_168_, n1141_1, PKSi_82_, n1723 }; + assign n1723 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_82_, PKSi_168_, n1724 }; + assign n1724 = 16'h5d7f >> { Pkey_220_, Pkey_212_, Pencrypt_0_, Pstart_0_ }; + assign n957 = 16'hd555 >> { PKSi_179_, n1141_1, PKSi_93_, n1726_1 }; + assign n1726_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_93_, PKSi_179_, n1727 }; + assign n1727 = 16'h5d7f >> { Pkey_228_, Pkey_220_, Pencrypt_0_, Pstart_0_ }; + assign n985 = 16'hd555 >> { PKSi_172_, n1141_1, PKSi_85_, n1729 }; + assign n1729 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_85_, PKSi_172_, n1730 }; + assign n1730 = 16'h5d7f >> { Pkey_172_, Pkey_228_, Pencrypt_0_, Pstart_0_ }; + assign n933 = 64'hdfffdddfdffddddd >> { n1138, n1137_1, N_N2746, PKSi_186_, n1170, n1732 }; + assign n1732 = 64'h00171717001f1f1f >> { n1141_1, Pkey_244_, n1157_1, n1139, N_N2746, PKSi_186_ }; + assign n965 = 16'hd555 >> { PKSi_177_, n1141_1, PKSi_73_, n1734 }; + assign n1734 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_73_, PKSi_177_, n1735 }; + assign n1735 = 16'h5d7f >> { Pkey_252_, Pkey_244_, Pencrypt_0_, Pstart_0_ }; + assign n953 = 16'hd555 >> { PKSi_180_, n1141_1, N_N2749, n1737 }; + assign n1737 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2749, PKSi_180_, n1738 }; + assign n1738 = 16'h5d7f >> { Pkey_197_, Pkey_252_, Pencrypt_0_, Pstart_0_ }; + assign n1755 = 16'hd555 >> { PKSi_80_, n1141_1, N_N2877, n1740 }; + assign n1740 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2877, PKSi_80_, n1741_1 }; + assign n1741_1 = 16'h5d7f >> { Pkey_205_, Pkey_197_, Pencrypt_0_, Pstart_0_ }; + assign n1760 = 16'hd555 >> { PKSi_72_, n1141_1, N_N2879, n1743 }; + assign n1743 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2879, PKSi_72_, n1744 }; + assign n1744 = 16'h5d7f >> { Pkey_213_, Pkey_205_, Pencrypt_0_, Pstart_0_ }; + assign n1765 = 16'hd555 >> { PKSi_94_, n1141_1, N_N2881, n1746_1 }; + assign n1746_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2881, PKSi_94_, n1747 }; + assign n1747 = 16'h5d7f >> { Pkey_221_, Pkey_213_, Pencrypt_0_, Pstart_0_ }; + assign n973_1 = 16'hd555 >> { PKSi_175_, n1141_1, PKSi_86_, n1749 }; + assign n1749 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_86_, PKSi_175_, n1750 }; + assign n1750 = 16'h5d7f >> { Pkey_229_, Pkey_221_, Pencrypt_0_, Pstart_0_ }; + assign n949 = 16'hd555 >> { PKSi_182_, n1141_1, PKSi_74_, n1752 }; + assign n1752 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_74_, PKSi_182_, n1753 }; + assign n1753 = 16'h5d7f >> { Pkey_237_, Pkey_229_, Pencrypt_0_, Pstart_0_ }; + assign n1770 = 16'hd555 >> { PKSi_83_, n1141_1, N_N2885, n1755_1 }; + assign n1755_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2885, PKSi_83_, n1756 }; + assign n1756 = 16'h5d7f >> { Pkey_245_, Pkey_237_, Pencrypt_0_, Pstart_0_ }; + assign n989 = 16'hd555 >> { PKSi_171_, n1141_1, N_N2757, n1758 }; + assign n1758 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2757, PKSi_171_, n1759 }; + assign n1759 = 16'h5d7f >> { Pkey_253_, Pkey_245_, Pencrypt_0_, Pstart_0_ }; + assign n925 = 16'hd555 >> { PKSi_189_, n1141_1, PKSi_89_, n1761 }; + assign n1761 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_89_, PKSi_189_, n1762 }; + assign n1762 = 16'h5d7f >> { Pkey_198_, Pkey_253_, Pencrypt_0_, Pstart_0_ }; + assign n1775 = 16'hd555 >> { PKSi_91_, n1141_1, N_N2889, n1764 }; + assign n1764 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, N_N2889, PKSi_91_, n1765_1 }; + assign n1765_1 = 16'h5d7f >> { Pkey_206_, Pkey_198_, Pencrypt_0_, Pstart_0_ }; + assign n941 = 16'hd555 >> { PKSi_184_, n1141_1, PKSi_81_, n1767 }; + assign n1767 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_81_, PKSi_184_, n1768 }; + assign n1768 = 16'h5d7f >> { Pkey_214_, Pkey_206_, Pencrypt_0_, Pstart_0_ }; + assign n961 = 16'hd555 >> { PKSi_178_, n1141_1, PKSi_77_, n1770_1 }; + assign n1770_1 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_77_, PKSi_178_, n1771 }; + assign n1771 = 16'h5d7f >> { Pkey_222_, Pkey_214_, Pencrypt_0_, Pstart_0_ }; + assign n1780 = 16'hd555 >> { PKSi_187_, n1141_1, PKSi_87_, n1773 }; + assign n1773 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_87_, PKSi_187_, n1774 }; + assign n1774 = 16'h5d7f >> { Pkey_230_, Pkey_222_, Pencrypt_0_, Pstart_0_ }; + assign n993 = 16'hd555 >> { PKSi_170_, n1141_1, PKSi_78_, n1776 }; + assign n1776 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_78_, PKSi_170_, n1777 }; + assign n1777 = 16'h5d7f >> { Pkey_238_, Pkey_230_, Pencrypt_0_, Pstart_0_ }; + assign n977 = 16'hd555 >> { PKSi_174_, n1141_1, PKSi_95_, n1779 }; + assign n1779 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_95_, PKSi_174_, n1780_1 }; + assign n1780_1 = 16'h5d7f >> { Pkey_246_, Pkey_238_, Pencrypt_0_, Pstart_0_ }; + assign n921_1 = 16'hd555 >> { PKSi_190_, n1141_1, PKSi_76_, n1782 }; + assign n1782 = 64'h008000a8028202aa >> { n1138, n1137_1, n1139, PKSi_76_, PKSi_190_, n1783 }; + assign n1783 = 16'h5d7f >> { Pkey_254_, Pkey_246_, Pencrypt_0_, Pstart_0_ }; + assign n1784_1 = 64'h00061117080e191f >> { n1141_1, n1138, n1137_1, n1139, N_N2774, PKSi_164_ }; + assign n1013 = 32'd4292203989 >> { n1157_1, Pkey_148_, n1158, Pkey_140_, n1784_1 }; + assign n1786 = 64'h00061117080e191f >> { n1141_1, n1138, n1137_1, n1139, PKSi_65_, PKSi_165_ }; + assign n1009 = 32'd2939129615 >> { Pkey_134_, Pkey_189_, n1786, Pencrypt_0_, Pstart_0_ }; + assign n1788 = 64'h00061117080e191f >> { n1141_1, n1138, n1137_1, n1139, PKSi_39_, PKSi_139_ }; + assign n1829 = 32'd2939129615 >> { Pkey_102_, Pkey_94_, n1788, Pencrypt_0_, Pstart_0_ }; + assign n1790 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, N_N2879, PKSi_72_ }; + assign n1365 = 32'd4292203989 >> { n1157_1, Pkey_209_, n1158, Pkey_201_, n1790 }; + assign n1792 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, PKSi_78_, PKSi_170_ }; + assign n1341 = 32'd4292203989 >> { n1157_1, Pkey_232_, n1158, Pkey_224_, n1792 }; + assign n1794_1 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, PKSi_65_, PKSi_165_ }; + assign n1393 = 32'd2939129615 >> { Pkey_128_, Pkey_185_, n1794_1, Pencrypt_0_, Pstart_0_ }; + assign n1796 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, N_N2931, PKSi_40_ }; + assign n1493 = 32'd4292203989 >> { n1157_1, Pkey_115_, n1158, Pkey_107_, n1796 }; + assign n1798 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, N_N2943, PKSi_32_ }; + assign n1525 = 32'd4292203989 >> { n1157_1, Pkey_73_, n1158, Pkey_65_, n1798 }; + assign n1800 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, PKSi_39_, PKSi_139_ }; + assign n1497 = 32'd2939129615 >> { Pkey_96_, Pkey_88_, n1800, Pencrypt_0_, Pstart_0_ }; + assign n1802 = 64'h080e191f00061117 >> { n1386, n1139, n1384, n1138, PKSi_2_, PKSi_110_ }; + assign n1645 = 32'd4292203989 >> { n1157_1, Pkey_41_, n1158, Pkey_33_, n1802 }; + assign PKSi_90_ = PKSi_88_; + assign PKSi_191_ = PKSi_187_; + assign PKSi_181_ = PKSi_168_; + assign PKSi_143_ = PKSi_139_; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act b/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act new file mode 100644 index 000000000..1a2158ff5 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act @@ -0,0 +1,2928 @@ +clock 0.491800 0.504600 +Pi416 0.492400 0.492200 +Pi415 0.493200 0.503800 +Pi414 0.506800 0.509000 +Pi413 0.508600 0.490200 +Pi412 0.509800 0.509400 +Pi411 0.495400 0.503400 +Pi410 0.502200 0.492000 +Pi409 0.501200 0.505200 +Pi408 0.511200 0.502000 +Pi407 0.504400 0.495600 +Pi406 0.497200 0.495000 +Pi405 0.512000 0.489800 +Pi404 0.498400 0.509600 +Pi403 0.489600 0.488000 +Pi402 0.501600 0.496200 +Pi401 0.494600 0.503000 +Pi400 0.499600 0.511000 +Pi399 0.502200 0.503600 +Pi398 0.508000 0.482200 +Pi397 0.490400 0.505400 +Pi396 0.491600 0.496200 +Pi395 0.496800 0.495600 +Pi394 0.502000 0.492000 +Pi393 0.489400 0.497000 +Pi392 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written by ABC on Tue Mar 12 09:36:31 2019 +.model clma +.inputs clock Pi416 Pi415 Pi414 Pi413 Pi412 Pi411 Pi410 Pi409 Pi408 Pi407 \ + Pi406 Pi405 Pi404 Pi403 Pi402 Pi401 Pi400 Pi399 Pi398 Pi397 Pi396 Pi395 \ + Pi394 Pi393 Pi392 Pi391 Pi390 Pi389 Pi388 Pi387 Pi386 Pi385 Pi384 Pi383 \ + Pi382 Pi381 Pi380 Pi379 Pi378 Pi377 Pi376 Pi375 Pi374 Pi373 Pi372 Pi371 \ + Pi370 Pi369 Pi368 Pi367 Pi366 Pi365 Pi364 Pi363 Pi362 Pi361 Pi360 Pi359 \ + Pi358 Pi357 Pi356 Pi355 Pi354 Pi353 Pi352 Pi351 Pi350 Pi349 Pi348 Pi347 \ + Pi346 Pi345 Pi344 Pi343 Pi342 Pi341 Pi340 Pi339 Pi338 Pi337 Pi336 Pi335 \ + Pi334 Pi333 Pi332 Pi331 Pi330 Pi329 Pi328 Pi327 Pi326 Pi325 Pi324 Pi323 \ + Pi322 Pi321 Pi320 Pi319 Pi318 Pi317 Pi316 Pi315 Pi314 Pi313 Pi312 Pi311 \ + Pi310 Pi309 Pi308 Pi307 Pi306 Pi305 Pi304 Pi303 Pi302 Pi301 Pi300 Pi299 \ + Pi298 Pi297 Pi296 Pi295 Pi294 Pi293 Pi292 Pi291 Pi290 Pi289 Pi288 Pi287 \ + Pi286 Pi285 Pi284 Pi283 Pi282 Pi281 Pi280 Pi279 Pi278 Pi277 Pi276 Pi275 \ + Pi274 Pi273 Pi272 Pi271 Pi270 Pi269 Pi268 Pi267 Pi266 Pi265 Pi264 Pi263 \ + Pi262 Pi261 Pi260 Pi259 Pi258 Pi257 Pi256 Pi255 Pi254 Pi253 Pi252 Pi251 \ + Pi250 Pi249 Pi248 Pi247 Pi246 Pi245 Pi244 Pi243 Pi242 Pi241 Pi240 Pi239 \ + Pi238 Pi237 Pi236 Pi235 Pi234 Pi233 Pi232 Pi231 Pi230 Pi229 Pi228 Pi227 \ + Pi226 Pi225 Pi224 Pi223 Pi222 Pi221 Pi220 Pi219 Pi218 Pi217 Pi216 Pi215 \ + Pi214 Pi213 Pi212 Pi211 Pi210 Pi209 Pi208 Pi207 Pi206 Pi205 Pi204 Pi203 \ + Pi202 Pi201 Pi200 Pi199 Pi198 Pi197 Pi196 Pi195 Pi194 Pi193 Pi192 Pi191 \ + Pi190 Pi189 Pi188 Pi187 Pi186 Pi185 Pi184 Pi183 Pi182 Pi181 Pi180 Pi179 \ + Pi178 Pi177 Pi176 Pi175 Pi174 Pi173 Pi172 Pi171 Pi170 Pi169 Pi168 Pi167 \ + Pi166 Pi165 Pi164 Pi163 Pi162 Pi161 Pi160 Pi159 Pi158 Pi157 Pi156 Pi155 \ + Pi154 Pi153 Pi152 Pi151 Pi150 Pi149 Pi148 Pi147 Pi146 Pi145 Pi144 Pi143 \ + Pi142 Pi141 Pi140 Pi139 Pi138 Pi137 Pi136 Pi135 Pi134 Pi133 Pi132 Pi131 \ + Pi130 Pi129 Pi128 Pi127 Pi126 Pi125 Pi124 Pi123 Pi122 Pi121 Pi120 Pi119 \ + Pi118 Pi117 Pi116 Pi115 Pi114 Pi113 Pi112 Pi111 Pi110 Pi109 Pi108 Pi107 \ + Pi106 Pi105 Pi104 Pi103 Pi102 Pi101 Pi100 Pi99 Pi98 Pi97 Pi96 Pi95 Pi94 \ + Pi93 Pi92 Pi91 Pi90 Pi89 Pi88 Pi87 Pi86 Pi85 Pi84 Pi83 Pi82 Pi81 Pi80 Pi79 \ + Pi78 Pi77 Pi76 Pi75 Pi74 Pi73 Pi72 Pi71 Pi70 Pi69 Pi68 Pi67 Pi66 Pi65 Pi64 \ + Pi63 Pi62 Pi61 Pi60 Pi59 Pi58 Pi57 Pi56 Pi55 Pi54 Pi53 Pi52 Pi51 Pi50 Pi49 \ + Pi28 Pi27 Pi26 Pi25 Pi24 Pi23 Pi22 Pi21 Pi20 Pi19 Pi18 Pi17 Pi16 Pi15 +.outputs P__cmxir_1 P__cmxir_0 P__cmxig_1 P__cmxig_0 P__cmxcl_1 P__cmxcl_0 \ + P__cmx1ad_35 P__cmx1ad_34 P__cmx1ad_33 P__cmx1ad_32 P__cmx1ad_31 \ + P__cmx1ad_30 P__cmx1ad_29 P__cmx1ad_28 P__cmx1ad_27 P__cmx1ad_26 \ + P__cmx1ad_25 P__cmx1ad_24 P__cmx1ad_23 P__cmx1ad_22 P__cmx1ad_21 \ + P__cmx1ad_20 P__cmx1ad_19 P__cmx1ad_18 P__cmx1ad_17 P__cmx1ad_16 \ + P__cmx1ad_15 P__cmx1ad_14 P__cmx1ad_13 P__cmx1ad_12 P__cmx1ad_11 \ + P__cmx1ad_10 P__cmx1ad_9 P__cmx1ad_8 P__cmx1ad_7 P__cmx1ad_6 P__cmx1ad_5 \ + P__cmx1ad_4 P__cmx1ad_3 P__cmx1ad_2 P__cmx1ad_1 P__cmx1ad_0 P__cmx0ad_35 \ + P__cmx0ad_34 P__cmx0ad_33 P__cmx0ad_32 P__cmx0ad_31 P__cmx0ad_30 \ + P__cmx0ad_29 P__cmx0ad_28 P__cmx0ad_27 P__cmx0ad_26 P__cmx0ad_25 \ + P__cmx0ad_24 P__cmx0ad_23 P__cmx0ad_22 P__cmx0ad_21 P__cmx0ad_20 \ + P__cmx0ad_19 P__cmx0ad_18 P__cmx0ad_17 P__cmx0ad_16 P__cmx0ad_15 \ + P__cmx0ad_14 P__cmx0ad_13 P__cmx0ad_12 P__cmx0ad_11 P__cmx0ad_10 \ + P__cmx0ad_9 P__cmx0ad_8 P__cmx0ad_7 P__cmx0ad_6 P__cmx0ad_5 P__cmx0ad_4 \ + P__cmx0ad_3 P__cmx0ad_2 P__cmx0ad_1 P__cmx0ad_0 P__cmnxcp_1 P__cmnxcp_0 \ + P__cmndst1p0 P__cmndst0p0 + +.latch n931 Ni48 re clock 0 +.latch n936_1 Ni47 re clock 0 +.latch n941 Ni46 re clock 0 +.latch n946 Ni45 re clock 0 +.latch n951 Ni44 re clock 0 +.latch n956 Ni43 re clock 0 +.latch n961 Ni42 re clock 0 +.latch n966 Ni41 re clock 0 +.latch n971_1 Ni40 re clock 0 +.latch n976 Ni39 re clock 0 +.latch n981 Ni38 re clock 0 +.latch n986_1 Ni37 re clock 0 +.latch n991 Ni36 re clock 0 +.latch n996 Ni35 re clock 0 +.latch n1001_1 Ni34 re clock 0 +.latch n1006 Ni33 re clock 0 +.latch n1011 Ni32 re clock 0 +.latch n1016 Ni31 re clock 0 +.latch n1021_1 Ni30 re clock 0 +.latch n1026 n18 re clock 0 +.latch n1031 Ni14 re clock 0 +.latch n1036_1 Ni13 re clock 0 +.latch n1041 Ni12 re clock 0 +.latch n1046 Ni11 re clock 0 +.latch n1051_1 Ni10 re clock 0 +.latch n1056 Ni9 re clock 0 +.latch n1061_1 Ni8 re clock 0 +.latch n1066 Ni7 re clock 0 +.latch n1071 Ni6 re clock 0 +.latch n1076_1 Ni5 re clock 0 +.latch n1081_1 Ni4 re clock 0 +.latch n1085 Ni3 re clock 0 +.latch n1090 Ni2 re clock 0 + +.names n564 + 0 +.names n18 Ni33 P__cmxig_1 +11 1 +.names n18 Ni33 P__cmxig_0 +10 1 +.names Ni2 Ni3 P__cmxcl_0 +00 1 +.names P__cmxcl_0 n571 P__cmx1ad_9 +11 1 +.names Ni13 Ni14 n572 n571 +111 1 +.names Ni12 Ni11 n572 +00 1 +.names P__cmx1ad_9 Pi27 P__cmx1ad_12 +10 1 +.names P__cmx1ad_9 Pi27 Pi26 P__cmx1ad_14 +101 1 +110 1 +.names n576 P__cmxcl_0 P__cmx0ad_9 +11 1 +.names Ni10 Ni9 Ni8 Ni7 n576 +1100 1 +.names P__cmx0ad_9 Pi24 P__cmx0ad_12 +10 1 +.names P__cmx0ad_9 Pi24 Pi23 P__cmx0ad_14 +101 1 +110 1 +.names Ni3 Ni2 n1090 +10 1 +.names Ni33 P__cmxcl_0 n581 n587 Ni30 n589 P__cmnxcp_1 +1--1-- 1 +1---10 1 +-10--- 1 +.names n585 n582 Ni12 n586 n581 +11-- 0 +--11 0 +.names Ni11 n583 n582 +11 1 +.names n584 Ni12 n583 +10 1 +.names Ni14 Ni13 n584 +10 1 +.names Pi26 Pi27 n585 +10 1 +.names Pi27 Ni14 Ni11 Ni13 Pi26 n586 +00000 1 +1100- 1 +.names Ni31 n588 Ni30 n587 +110 1 +.names n1090 Ni6 Ni5 Ni4 n588 +1100 1 +.names Ni31 n1090 Ni5 Ni6 Ni4 n590 n589 +110111 0 +111000 0 +.names Ni32 Ni41 Ni36 n590 +0-1 1 +11- 1 +.names Ni33 n592 n587 Ni30 n589 P__cmnxcp_0 +0-1-- 1 +0--10 1 +-1--- 1 +.names P__cmxcl_0 n593 n597 n595 n592 +11-- 1 +1-11 1 +.names Ni8 n594 Pi24 Ni10 Pi23 n593 +11000 1 +1111- 1 +.names Ni9 Ni7 n594 +00 1 +.names Ni7 n596 n595 +11 1 +.names Ni10 Ni8 Ni9 n596 +100 1 +.names Pi23 Pi24 n597 +10 1 +.names Ni47 Pi22 Ni48 Pi20 Ni31 n599 n931 +00-10- 1 +00-1-0 1 +1-1--- 1 +-11--- 1 +--1-11 1 +.names Ni32 Ni30 n599 +10 1 +.names n601 Ni33 Ni44 n951 +0-1 1 +11- 1 +.names Ni32 n602 n601 +11 1 +.names Ni30 Ni31 n602 +10 1 +.names Ni33 n604 Ni41 n613 n571 n576 n966 +01-1-1 1 +0-1--0 1 +11-11- 1 +1-1-0- 1 +-01--- 1 +.names n605 n601 n604 +11 1 +.names P__cmxcl_0 Ni5 Ni6 Ni4 n605 +1000 1 +.names n607 n604 Ni33 Ni40 n571 n576 n971_1 +110--1 1 +111-1- 1 +1--1-- 1 +-0-1-- 1 +.names Ni33 n571 Pi26 n576 Pi23 n607 +0--10 0 +110-- 0 +.names n609 Ni33 Ni39 n976 +0-1 1 +11- 1 +.names n602 Ni32 n609 +10 1 +.names n611 Ni36 n613 n991 +01- 1 +1-1 1 +.names n609 n605 Ni33 n576 n571 n611 +1101- 1 +111-1 1 +.names Ni33 Ni30 Ni31 n612 +110 1 +.names n602 Ni33 Pi27 n571 Pi24 n576 n613 +10--11 1 +1111-- 1 +.names n622 n615 n614 +10 1 +.names n620 n616 n615 +00 1 +.names n617 n618 Ni38 n616 +110 1 +.names Ni45 Ni47 Ni38 Ni42 Ni43 Ni37 n617 +0010-- 1 +001-1- 1 +00-0-0 1 +00--10 1 +.names Ni37 Ni36 Ni39 Ni38 n618 +01-- 1 +0-10 1 +.names Ni42 Ni45 Ni43 Ni47 n619 +0000 1 +.names n617 n619 n621 n618 Ni41 Ni44 n620 +11--1- 1 +11---1 1 +1-01-- 1 +.names Ni36 Ni37 n621 +10 1 +.names Ni31 Ni32 Ni30 n622 +000 1 +.names n625 n624 n623 +11 1 +.names Pi21 Pi22 n624 +11 1 +.names Pi19 Pi20 n625 +00 1 +.names n629 n627 n626 +11 1 +.names n617 Ni38 n619 n628 n627 +10-- 1 +1-10 1 +.names Ni40 Ni44 Ni41 n628 +100 1 +.names n630 n631 n619 n628 n629 +00-- 1 +0-10 1 +.names Ni47 Ni45 Ni42 Ni43 n630 +000- 0 +00-1 0 +.names Ni35 Ni36 Ni39 Ni38 n631 +100- 1 +10-1 1 +.names Pi19 n624 Pi20 n632 +110 1 +.names n636 n634 n633 +11 1 +.names n617 Ni38 n619 n635 n634 +10-- 1 +1-10 1 +.names Ni40 Ni44 Ni41 n635 +110 1 +.names n630 n637 n619 n635 n636 +00-- 1 +0-10 1 +.names Ni35 Ni36 Ni39 Ni38 n637 +101- 1 +10-1 1 +.names Pi19 Pi20 n624 n638 +111 1 +.names Ni34 P__cmxig_1 n622 n642 n640 n639 +11--- 1 +1-0-- 1 +1--00 1 +.names n617 n619 Ni41 Ni44 n641 n621 n640 +111--- 1 +11-0-- 1 +1---10 1 +.names Ni37 Ni36 Ni38 Ni39 n641 +01-- 1 +0-00 1 +.names n617 n641 Ni38 n642 +110 1 +.names n644 n624 n643 +11 1 +.names Pi20 Pi19 n644 +10 1 +.names Pi16 Pi15 n645 +11 1 +.names n622 n647 n646 +10 1 +.names n650 n648 n647 +00 1 +.names n617 n649 Ni44 n641 n621 n648 +110-- 1 +1--10 1 +.names Ni42 Ni45 Ni43 Ni47 Ni41 n649 +00000 1 +.names n617 n641 Ni38 n650 +110 1 +.names n654 n652 n651 +11 1 +.names n617 Ni38 n653 n652 +10- 1 +1-1 1 +.names Ni42 Ni45 Ni43 Ni41 Ni44 Ni40 n653 +00000- 1 +0000-0 1 +.names n630 n637 n653 n654 +00- 1 +0-1 1 +.names n657 n617 n656 Ni38 n655 +111- 1 +11-0 1 +.names Ni42 Ni45 Ni43 Ni41 Ni44 Ni40 n656 +00001- 1 +0000-0 1 +.names n631 n656 n657 +10 0 +.names n617 n618 Ni38 Ni44 n649 n658 +110-- 0 +1--11 0 +.names Pi15 Pi16 n659 +10 1 +.names n654 n663 n661 n660 +100 1 +.names Ni38 n653 n661 +10 1 +.names Ni35 Ni36 n662 +00 1 +.names n664 n653 n665 n663 +1-- 1 +-00 1 +.names Ni37 Ni38 n664 +10 1 +.names Ni37 Ni36 n665 +00 1 +.names n670 n632 Ni34 n622 n667 P__cmxig_1 n666 +10---- 1 +1-0--- 1 +1--110 1 +.names n669 n657 n668 n667 +110 1 +.names n617 Ni38 n656 n668 +0-- 1 +-10 1 +.names n665 n656 n669 +00 0 +.names n624 Ni34 n644 n648 n622 P__cmxig_1 n670 +1-0--- 1 +1--110 1 +-0---- 1 +.names n617 n618 n621 Ni44 n649 n671 +110-- 1 +1--11 1 +.names Pi16 Pi15 n672 +00 1 +.names n627 n674 n665 n629 n673 +11-- 1 +1-11 1 +.names n619 n628 n674 +10 1 +.names n636 n676 n634 n675 +111 1 +.names n664 n665 n619 n635 n676 +01-- 1 +0-10 1 +.names Pi16 Pi15 n677 +10 1 +.names n622 n679 n678 +11 1 +.names n684 n683 n680 n679 +100 1 +.names n617 Ni38 n682 n680 +0-- 1 +-10 1 +.names Ni35 Ni36 n681 +10 1 +.names Ni42 Ni45 Ni43 Ni41 Ni44 Ni40 n682 +00001- 1 +0000-1 1 +.names n665 n682 n683 +00 1 +.names n686 n682 n684 +10 0 +.names Ni47 Ni45 Ni42 Ni43 n685 +000- 0 +00-1 0 +.names Ni36 Ni35 Ni39 Ni38 n686 +000- 1 +00-1 1 +.names n690 n691 n688 n687 +111 1 +.names n617 Ni38 n689 n688 +10- 1 +1-1 1 +.names Ni42 Ni45 Ni43 Ni41 Ni44 Ni40 n689 +00000- 1 +0000-1 1 +.names n665 n689 n664 n690 +1-- 1 +-10 1 +.names n685 n692 n689 n691 +00- 1 +0-1 1 +.names Ni36 Ni35 Ni39 Ni38 n692 +001- 1 +00-1 1 +.names n694 n649 Ni36 n693 +11- 1 +1-0 1 +.names n617 n649 Ni38 n694 +11- 1 +1-0 1 +.names Ni40 Ni44 Ni41 n695 +000 1 +.names n617 Ni38 n619 n695 n696 +10-- 1 +1-10 1 +.names n685 n686 n619 n695 n697 +00-- 1 +0-10 1 +.names Ni34 n700 Ni36 n619 n698 +10-- 0 +1-10 0 +.names Pi19 n624 n699 +11 1 +.names n624 Ni34 Pi19 n622 n701 P__cmxig_1 n700 +1-0--- 1 +1--110 1 +-0---- 1 +.names Ni38 Ni47 Ni45 Ni42 Ni43 Ni37 n701 +000-10 1 +10000- 1 +-00000 1 +.names n705 n706 n703 n702 +111 1 +.names n617 Ni38 n619 n704 n703 +10-- 1 +1-10 1 +.names Ni44 Ni40 Ni41 n704 +100 1 +.names n664 n665 n619 n704 n705 +01-- 1 +0-10 1 +.names n685 n692 n619 n704 n706 +00-- 1 +0-10 1 +.names n709 n623 Ni34 n622 n708 P__cmxig_1 n707 +10---- 1 +1-0--- 1 +1--110 1 +.names n617 n682 n684 Ni38 n708 +11-- 1 +1-10 1 +.names n624 Ni34 Pi19 n694 n622 P__cmxig_1 n709 +1-0--- 1 +1--110 1 +-0---- 1 +.names n622 n711 n710 +11 1 +.names n691 n688 n711 +11 1 +.names Ni34 n623 n713 P__cmxig_1 n622 n712 +110-- 1 +11-1- 1 +11--0 1 +.names n697 n696 n713 +11 1 +.names Ni34 n643 n715 P__cmxig_1 n622 n714 +110-- 1 +11-1- 1 +11--0 1 +.names n706 n703 n715 +11 1 +.names n584 n572 n716 +11 1 +.names P__cmxcl_0 n718 n717 +11 1 +.names n594 Ni8 n718 +10 1 +.names n642 n640 n719 +00 1 +.names n18 n622 n720 +11 1 +.names Pi25 P__cmxig_0 n622 Ni34 n721 +1110 1 +.names Ni34 n622 n615 Pi25 n18 Ni33 n722 +01010- 0 +0101-0 0 +10---- 0 +1-1--- 0 +1---11 0 +.names Ni33 n616 n620 Ni34 n723 +0--- 0 +-000 0 +.names Ni34 n624 n724 +10 1 +.names n643 n729 Pi25 n726 n725 +10-- 1 +1-10 1 +.names Ni34 n647 n18 n727 n622 n726 +000-1 0 +110-- 0 +---1- 0 +.names n728 n648 n650 Ni34 n727 +0--- 0 +-000 0 +.names n622 P__cmxig_1 n728 +11 1 +.names n721 n647 Ni34 n622 P__cmxig_1 n729 +00-10 1 +0-0-- 1 +-10-- 1 +.names n623 n733 Pi25 n731 n730 +10-- 1 +1-10 1 +.names Ni34 n18 n732 n671 n622 Ni33 n731 +001-1- 0 +00-11- 0 +1000-- 0 +1-0011 0 +-11-11 0 +-1-111 0 +.names n617 n618 Ni38 n732 +110 1 +.names n721 n658 Ni34 n622 P__cmxig_1 n733 +00-10 1 +0-0-- 1 +-10-- 1 +.names Ni34 n622 n671 Ni33 n18 Pi25 n734 +011--1 0 +10---- 0 +1-0--- 0 +1--11- 0 +.names Ni34 n622 n693 Ni33 n18 Pi25 n735 +011--1 0 +10---- 0 +1-0--- 0 +1--11- 0 +.names n659 n737 n739 n643 n741 n736 +11--- 1 +1-0-- 1 +1--10 1 +.names n623 Pi25 n738 n708 n721 n737 +110-- 1 +1--11 1 +.names Ni34 n622 n708 n18 Ni33 n738 +0110- 0 +11-11 0 +1-00- 0 +-1111 0 +.names n699 n707 n740 Pi25 n694 n721 n739 +1-01-- 0 +1---11 0 +-0---- 0 +.names Ni34 n622 n694 n18 Ni33 n740 +0110- 0 +11-11 0 +1-00- 0 +-1111 0 +.names Ni34 n622 n711 Ni33 n18 Pi25 n741 +011--1 0 +10---- 0 +1-0--- 0 +1--11- 0 +.names n701 n619 Ni36 n742 +11- 1 +1-0 1 +.names Ni34 n622 n2562 Ni33 n18 Pi25 n743 +011--1 0 +10---- 0 +1-0--- 0 +1--11- 0 +.names n622 n747 n745 Ni34 n655 n708 n744 +11---1 0 +1-1-1- 0 +-1-1-- 0 +--11-- 0 +.names n746 Pi16 n745 +10 1 +.names Pi19 Pi17 n746 +10 1 +.names n748 Pi16 n747 +10 1 +.names Pi17 Pi19 n748 +10 1 +.names Pi25 n750 n749 +11 1 +.names n624 Pi20 n750 +10 1 +.names Pi16 n748 n751 +11 1 +.names Pi25 Pi20 n624 n752 +111 1 +.names n622 n719 n753 +10 1 +.names Pi25 n624 n754 +11 1 +.names Pi25 Pi21 Pi19 Pi17 Pi22 n755 +11111 1 +.names Pi16 n746 n756 +11 1 +.names Pi16 n758 n757 +11 1 +.names Pi19 Pi17 n758 +00 1 +.names n758 Pi16 n759 +10 1 +.names n761 n757 n745 n765 n766 n746 n760 +100--0 1 +1011-- 1 +11--1- 1 +1--11- 1 +.names n748 Pi20 n764 n762 n766 Pi16 n761 +00-0-- 1 +101-1- 1 +101--0 1 +.names n759 n763 n762 +10 1 +.names n671 n622 n624 Ni34 Ni33 n18 n763 +111-1- 0 +111--0 0 +---1-- 0 +.names n624 n622 Ni33 Ni34 n679 n18 n764 +1111-- 0 +111-1- 0 +11--10 0 +1--1-0 0 +.names n624 n622 Ni33 Ni34 n667 n18 n765 +1111-- 0 +111-1- 0 +11--10 0 +1--1-0 0 +.names n620 n622 n624 Ni34 Ni33 n18 n766 +111-1- 0 +111--0 0 +---1-- 0 +.names n624 n720 n723 n767 +111 1 +.names n624 n622 Ni34 Ni33 n18 n768 +11-1- 1 +11--0 1 +--0-- 1 +.names n624 n18 n769 +10 1 +.names n728 n624 n747 n708 Ni34 n770 +1111- 1 +111-1 1 +.names n772 n728 n655 Ni34 n771 +111- 1 +11-1 1 +.names n624 n745 n772 +11 1 +.names n759 n774 n622 n769 n658 n773 +10--- 1 +1-110 1 +.names Ni34 n728 n624 n732 n671 n774 +00--- 1 +0-0-- 1 +0--00 1 +.names Ni34 n624 n646 n18 n727 n775 +00--- 1 +0-0-- 1 +0--10 1 +.names Pi19 Pi17 n776 +11 1 +.names n778 n738 n624 Ni34 n708 n777 +0---- 0 +-01-- 0 +---10 0 +.names Ni34 n624 n622 n778 +0-- 1 +-11 1 +.names Ni34 n622 n624 n615 n18 n779 +01100 0 +10--- 0 +1-0-- 0 +1--1- 0 +.names Ni34 n622 n624 n713 n18 Ni33 n780 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names n782 n771 n745 n768 n778 n655 n781 +000--- 1 +00-1-- 1 +00--11 1 +.names n759 n778 n731 n624 Ni34 n658 n782 +10---- 1 +1-01-- 1 +1---11 1 +.names Ni34 n622 n624 n626 n18 Ni33 n783 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names n772 n655 Ni34 n18 n622 n784 +1010- 1 +11001 1 +.names n772 Ni34 n622 n651 n18 Ni33 n785 +10110- 1 +111-11 1 +11-00- 1 +1-1111 1 +.names Pi20 n745 n768 n651 n778 n786 +10--- 1 +1-1-- 1 +1--11 1 +.names Ni34 n622 n624 n633 n18 Ni33 n787 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names n759 n768 n726 n624 n647 n778 n788 +10--1- 1 +10---0 1 +1-01-- 1 +.names n757 n768 n790 n719 n778 n789 +10-1- 1 +10--0 1 +1-0-- 1 +.names n624 Ni34 n622 n719 n18 Ni33 n790 +10100- 0 +111-11 0 +11-10- 0 +1-1011 0 +.names Ni34 n622 n624 n715 n18 Ni33 n791 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names Pi15 n716 n792 +11 1 +.names Pi16 n776 n793 +11 1 +.names n797 n795 n776 n805 Pi16 n794 +11-1- 1 +11--0 1 +1-0-- 1 +.names n693 n622 n624 Ni34 Ni33 n18 n795 +111-1- 0 +111--0 0 +---1-- 0 +.names n622 n742 n796 +11 1 +.names Pi15 n768 n745 n747 n797 +01-- 1 +0-00 1 +.names Pi16 n776 n624 n798 +111 1 +.names Pi20 n800 n751 n759 n801 n799 +0---- 0 +-01-- 0 +---10 0 +.names Ni34 n622 n624 n702 n18 Ni33 n800 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names Ni34 n622 n624 n648 n18 Ni33 n801 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names Ni34 n622 n624 n687 n18 Ni33 n802 +00---- 1 +0-0--- 1 +0--0-- 1 +11110- 1 +-11110 1 +.names Ni34 n622 n624 n640 n18 Ni33 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n3034 +000--- 1 +011--1 1 +1--11- 1 +.names Pi17 Ni34 n3032 n3034 n716 P__cmxcl_0 n3035 +0-0--- 0 +10---- 0 +1--111 0 +.names n784 n779 n783 n767 n756 n757 n3036 +0110-- 1 +01-00- 1 +0-1--0 1 +0---00 1 +.names n781 n3036 Pi16 n748 n780 n777 n3037 +110--1 1 +111-1- 1 +11-0-- 1 +.names Ni10 n2891 n792 n2892 n3037 Pi20 n3038 +11-0-- 1 +11--10 1 +1-0--- 1 +.names Ni34 n624 n751 n759 n648 n702 n3039 +011--1 1 +01-11- 1 +1-00-- 1 +.names Pi20 n3039 Ni34 n622 n18 Ni33 n3040 +100--- 1 +111--- 1 +1-00-- 1 +1-0-10 1 +.names n624 n622 Ni33 n18 n3041 +111- 1 +11-0 1 +.names Ni34 n713 n756 n626 n751 n3041 n3042 +000--- 1 +00-0-- 1 +0--00- 1 +0----0 1 +--0-01 1 +.names n3042 n773 n771 n770 n3043 +1000 1 +.names Pi16 Pi17 n2562 n679 n620 n671 n3044 +00---1 1 +01-1-- 1 +10--1- 1 +111--- 1 +.names n747 n752 n1057 n749 n922 n1060 n3045 +110--- 0 +11---0 0 +1-01-- 0 +1--11- 0 +.names n1058 n3045 Pi20 n754 n1072 n1074 n3046 +110--1 1 +111-1- 1 +11-0-- 1 +.names n2900 Pi15 n3046 n1070 n745 n2603 n3047 +11100- 0 +1110-0 0 +.names Pi16 n932 n1076 n2607 n2608 n1077 n3048 +01--11 1 +10---- 1 +1-0--- 1 +1--0-- 1 +.names Pi17 n2610 Pi16 Pi15 n3048 n2901 n3049 +00001- 0 +0011-- 0 +001-0- 0 +00-1-0 0 +.names n2739 n745 n624 n1133 n751 n1717 n3050 +111--- 1 +---100 1 +.names n2740 n751 n1803 n1793 n1800 n1799 n3051 +1000-- 1 +110-11 1 +.names n2979 n3051 n1801 Ni14 n3050 n1686 n3052 +110-0- 0 +110--1 0 +---0-- 0 +.names n1323 Pi16 n1162 n1197 n1202 n3053 +0---- 1 +-01-- 1 +---00 1 +.names n1325 n1198 n1333 n1277 n1278 n3054 +1--1- 0 +1---0 0 +-01-- 0 +.names n2933 n3011 n3053 n758 Pi16 n3054 n3055 +011-0- 1 +011--1 1 +0--0-- 1 +.names Pi16 Pi20 n1735 n1770 n1737 n1859 n3056 +00---0 1 +01-1-- 1 +10--1- 1 +111--- 1 +.names n624 n1296 n746 Pi16 n3056 n1838 n3057 +1011-0 1 +111-1- 1 +11-01- 1 +.names Pi16 n3017 Pi25 n3057 n2751 n2748 n3058 +0----0 1 +1---0- 1 +-0---- 1 +--11-- 1 +.names n624 n622 Pi16 Pi19 n673 n667 n3059 +110--1 1 +111-1- 1 +11-0-- 1 +.names Pi19 n3059 Ni34 n18 n3044 Ni33 n3060 +000--- 1 +01101- 1 +01-110 1 +0-0-0- 1 +101--- 1 +1100-- 1 +11-1-1 1 +.names n2584 Pi19 n3060 Pi20 Pi17 n3061 +000-- 0 +011-0 0 +0--1- 0 +.names n564 P__cmx0ad_10 +1 1 +.names n564 P__cmx0ad_11 +1 1 +.names n564 P__cmx0ad_32 +1 1 +.names n564 P__cmx0ad_33 +1 1 +.names n564 P__cmx0ad_34 +1 1 +.names n564 P__cmx0ad_35 +1 1 +.names n564 P__cmx0ad_8 +1 1 +.names n564 P__cmx1ad_10 +1 1 +.names n564 P__cmx1ad_11 +1 1 +.names n564 P__cmx1ad_32 +1 1 +.names n564 P__cmx1ad_33 +1 1 +.names n564 P__cmx1ad_34 +1 1 +.names n564 P__cmx1ad_35 +1 1 +.names n564 P__cmx1ad_8 +1 1 +.names P__cmxcl_0 P__cmxcl_1 +1 1 +.names P__cmxcl_0 n1085 +1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v b/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v new file mode 100644 index 000000000..d11a4f515 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v @@ -0,0 +1,5543 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module clma(clock, Pi416, Pi415, Pi414, Pi413, Pi412, Pi411, Pi410, Pi409, Pi408, Pi407, Pi406, Pi405, Pi404, Pi403, Pi402, Pi401, Pi400, Pi399, Pi398, Pi397, Pi396, Pi395, Pi394, Pi393, Pi392, Pi391, Pi390, Pi389, Pi388, Pi387, Pi386, Pi385, Pi384, Pi383, Pi382, Pi381, Pi380, Pi379, Pi378, Pi377, Pi376, Pi375, Pi374, Pi373, Pi372, Pi371, Pi370, Pi369, Pi368, Pi367, Pi366, Pi365, Pi364, Pi363, Pi362, Pi361, Pi360, Pi359, Pi358, Pi357, Pi356, Pi355, Pi354, Pi353, Pi352, Pi351, Pi350, Pi349, Pi348, Pi347, Pi346, Pi345, Pi344, Pi343, Pi342, Pi341, Pi340, Pi339, Pi338, Pi337, Pi336, Pi335, Pi334, Pi333, Pi332, Pi331, Pi330, Pi329, Pi328, Pi327, Pi326, Pi325, Pi324, Pi323, Pi322, Pi321, Pi320, Pi319, Pi318, Pi317, Pi316, Pi315, Pi314, Pi313, Pi312, Pi311, Pi310, Pi309, Pi308, Pi307, Pi306, Pi305, Pi304, Pi303, Pi302, Pi301, Pi300, Pi299, Pi298, Pi297, Pi296, Pi295, Pi294, Pi293, Pi292, Pi291, Pi290, Pi289, Pi288, Pi287, Pi286, Pi285, Pi284, Pi283, Pi282, Pi281, Pi280, Pi279, Pi278, Pi277, Pi276, Pi275, Pi274, Pi273, Pi272, Pi271, Pi270, Pi269, Pi268, Pi267, Pi266, Pi265, Pi264, Pi263, Pi262, Pi261, Pi260, Pi259, Pi258, Pi257, Pi256, Pi255, Pi254, Pi253, Pi252, Pi251, Pi250, Pi249, Pi248, Pi247, Pi246, Pi245, Pi244, Pi243, Pi242, Pi241, Pi240, Pi239, Pi238, Pi237, Pi236, Pi235, Pi234, Pi233, Pi232, Pi231, Pi230, Pi229, Pi228, Pi227, Pi226, Pi225, Pi224, Pi223, Pi222, Pi221, Pi220, Pi219, Pi218, Pi217, Pi216, Pi215, Pi214, Pi213, Pi212, Pi211, Pi210, Pi209, Pi208, Pi207, Pi206, Pi205, Pi204, Pi203, Pi202, Pi201, Pi200, Pi199, Pi198, Pi197, Pi196, Pi195, Pi194, Pi193, Pi192, Pi191, Pi190, Pi189, Pi188, Pi187, Pi186, Pi185, Pi184, Pi183, Pi182, Pi181, Pi180, Pi179, Pi178, Pi177, Pi176, Pi175, Pi174, Pi173, Pi172, Pi171, Pi170, Pi169, Pi168, Pi167, Pi166, Pi165, Pi164, Pi163, Pi162, Pi161, Pi160, Pi159, Pi158, Pi157, Pi156, Pi155, Pi154, Pi153, Pi152, Pi151, Pi150, Pi149, Pi148, Pi147, Pi146, Pi145, Pi144, Pi143, Pi142, Pi141, Pi140, Pi139, Pi138, Pi137, Pi136, Pi135, Pi134, Pi133, Pi132, Pi131, Pi130, Pi129, Pi128, Pi127, Pi126, Pi125, Pi124, Pi123, Pi122, Pi121, Pi120, Pi119, Pi118, Pi117, Pi116, Pi115, Pi114, Pi113, Pi112, Pi111, Pi110, Pi109, Pi108, Pi107, Pi106, Pi105, Pi104, Pi103, Pi102, Pi101, Pi100, Pi99, Pi98, Pi97, Pi96, Pi95, Pi94, Pi93, Pi92, Pi91, Pi90, Pi89, Pi88, Pi87, Pi86, Pi85, Pi84, Pi83, Pi82, Pi81, Pi80, Pi79, Pi78, Pi77, Pi76, Pi75, Pi74, Pi73, Pi72, Pi71, Pi70, Pi69, Pi68, Pi67, Pi66, Pi65, Pi64, Pi63, Pi62, Pi61, Pi60, Pi59, Pi58, Pi57, Pi56, Pi55, Pi54, Pi53, Pi52, Pi51, Pi50, Pi49, Pi28, Pi27, Pi26, Pi25, Pi24, Pi23, Pi22, Pi21, Pi20, Pi19, Pi18, Pi17, Pi16, Pi15, P__cmxir_1, P__cmxir_0, P__cmxig_1, P__cmxig_0, P__cmxcl_1, P__cmxcl_0, P__cmx1ad_35, P__cmx1ad_34, P__cmx1ad_33, P__cmx1ad_32, P__cmx1ad_31, P__cmx1ad_30, P__cmx1ad_29, P__cmx1ad_28, P__cmx1ad_27, P__cmx1ad_26, P__cmx1ad_25, P__cmx1ad_24, P__cmx1ad_23, P__cmx1ad_22, P__cmx1ad_21, P__cmx1ad_20, P__cmx1ad_19, P__cmx1ad_18, P__cmx1ad_17, P__cmx1ad_16, P__cmx1ad_15, P__cmx1ad_14, P__cmx1ad_13, P__cmx1ad_12, P__cmx1ad_11, P__cmx1ad_10, P__cmx1ad_9, P__cmx1ad_8, P__cmx1ad_7, P__cmx1ad_6, P__cmx1ad_5, P__cmx1ad_4, P__cmx1ad_3, P__cmx1ad_2, P__cmx1ad_1, P__cmx1ad_0, P__cmx0ad_35, P__cmx0ad_34, P__cmx0ad_33, P__cmx0ad_32, P__cmx0ad_31, P__cmx0ad_30, P__cmx0ad_29, P__cmx0ad_28, P__cmx0ad_27, P__cmx0ad_26, P__cmx0ad_25, P__cmx0ad_24, P__cmx0ad_23, P__cmx0ad_22, P__cmx0ad_21, P__cmx0ad_20, P__cmx0ad_19, P__cmx0ad_18, P__cmx0ad_17, P__cmx0ad_16, P__cmx0ad_15, P__cmx0ad_14, P__cmx0ad_13, P__cmx0ad_12, P__cmx0ad_11, P__cmx0ad_10, P__cmx0ad_9, P__cmx0ad_8, P__cmx0ad_7, P__cmx0ad_6, P__cmx0ad_5, P__cmx0ad_4, P__cmx0ad_3, P__cmx0ad_2, P__cmx0ad_1, P__cmx0ad_0, P__cmnxcp_1, P__cmnxcp_0, P__cmndst1p0, P__cmndst0p0); + (* init = 1'h0 *) + reg Ni10 = 1'h0; + (* init = 1'h0 *) + reg Ni11 = 1'h0; + (* init = 1'h0 *) + reg Ni12 = 1'h0; + (* init = 1'h0 *) + reg Ni13 = 1'h0; + (* init = 1'h0 *) + reg Ni14 = 1'h0; + (* init = 1'h0 *) + reg Ni2 = 1'h0; + (* init = 1'h0 *) + reg Ni3 = 1'h0; + (* init = 1'h0 *) + reg Ni30 = 1'h0; + (* init = 1'h0 *) + reg Ni31 = 1'h0; + (* init = 1'h0 *) + reg Ni32 = 1'h0; + (* init = 1'h0 *) + reg Ni33 = 1'h0; + (* init = 1'h0 *) + reg Ni34 = 1'h0; + (* init = 1'h0 *) + reg Ni35 = 1'h0; + (* init = 1'h0 *) + reg Ni36 = 1'h0; + (* init = 1'h0 *) + reg Ni37 = 1'h0; + (* init = 1'h0 *) + reg Ni38 = 1'h0; + (* init = 1'h0 *) + reg Ni39 = 1'h0; + (* init = 1'h0 *) + reg Ni4 = 1'h0; + (* init = 1'h0 *) + reg Ni40 = 1'h0; + (* init = 1'h0 *) + reg Ni41 = 1'h0; + (* init = 1'h0 *) + reg Ni42 = 1'h0; + (* init = 1'h0 *) + reg Ni43 = 1'h0; + (* init = 1'h0 *) + reg Ni44 = 1'h0; + (* init = 1'h0 *) + reg Ni45 = 1'h0; + (* init = 1'h0 *) + reg Ni46 = 1'h0; + (* init = 1'h0 *) + reg Ni47 = 1'h0; + (* init = 1'h0 *) + reg Ni48 = 1'h0; + (* init = 1'h0 *) + reg Ni5 = 1'h0; + (* init = 1'h0 *) + reg Ni6 = 1'h0; + (* init = 1'h0 *) + reg Ni7 = 1'h0; + (* init = 1'h0 *) + reg Ni8 = 1'h0; + (* init = 1'h0 *) + reg Ni9 = 1'h0; + output P__cmndst0p0; + output P__cmndst1p0; + output P__cmnxcp_0; + output P__cmnxcp_1; + output P__cmx0ad_0; + output P__cmx0ad_1; + output P__cmx0ad_10; + output P__cmx0ad_11; + output P__cmx0ad_12; + output P__cmx0ad_13; + output P__cmx0ad_14; + output P__cmx0ad_15; + output P__cmx0ad_16; + output P__cmx0ad_17; + output P__cmx0ad_18; + output P__cmx0ad_19; + output P__cmx0ad_2; + output P__cmx0ad_20; + output P__cmx0ad_21; + output P__cmx0ad_22; + output P__cmx0ad_23; + output P__cmx0ad_24; + output P__cmx0ad_25; + output P__cmx0ad_26; + output P__cmx0ad_27; + output P__cmx0ad_28; + output P__cmx0ad_29; + output P__cmx0ad_3; + output P__cmx0ad_30; + output P__cmx0ad_31; + output P__cmx0ad_32; + output P__cmx0ad_33; + output P__cmx0ad_34; + output P__cmx0ad_35; + output P__cmx0ad_4; + output P__cmx0ad_5; + output P__cmx0ad_6; + output P__cmx0ad_7; + output P__cmx0ad_8; + output P__cmx0ad_9; + output P__cmx1ad_0; + output P__cmx1ad_1; + output P__cmx1ad_10; + output P__cmx1ad_11; + output P__cmx1ad_12; + output P__cmx1ad_13; + output P__cmx1ad_14; + output P__cmx1ad_15; + output P__cmx1ad_16; + output P__cmx1ad_17; + output P__cmx1ad_18; + output P__cmx1ad_19; + output P__cmx1ad_2; + output P__cmx1ad_20; + output P__cmx1ad_21; + output P__cmx1ad_22; + output P__cmx1ad_23; + output P__cmx1ad_24; + output P__cmx1ad_25; + output P__cmx1ad_26; + output P__cmx1ad_27; + output P__cmx1ad_28; + output P__cmx1ad_29; + output P__cmx1ad_3; + output P__cmx1ad_30; + output P__cmx1ad_31; + output P__cmx1ad_32; + output P__cmx1ad_33; + output P__cmx1ad_34; + output P__cmx1ad_35; + output P__cmx1ad_4; + output P__cmx1ad_5; + output P__cmx1ad_6; + output P__cmx1ad_7; + output P__cmx1ad_8; + output P__cmx1ad_9; + output P__cmxcl_0; + output P__cmxcl_1; + output P__cmxig_0; + output P__cmxig_1; + output P__cmxir_0; + output P__cmxir_1; + input Pi100; + input Pi101; + input Pi102; + input Pi103; + input Pi104; + input Pi105; + input Pi106; + input Pi107; + input Pi108; + input Pi109; + input Pi110; + input Pi111; + input Pi112; + input Pi113; + input Pi114; + input Pi115; + input Pi116; + input Pi117; + input Pi118; + input Pi119; + input Pi120; + input Pi121; + input Pi122; + input Pi123; + input Pi124; + input Pi125; + input Pi126; + input Pi127; + input Pi128; + input Pi129; + input Pi130; + input Pi131; + input Pi132; + input Pi133; + input Pi134; + input Pi135; + input Pi136; + input Pi137; + input Pi138; + input Pi139; + input Pi140; + input Pi141; + input Pi142; + input Pi143; + input Pi144; + input Pi145; + input Pi146; + input Pi147; + input Pi148; + input Pi149; + input Pi15; + input Pi150; + input Pi151; + input Pi152; + input Pi153; + input Pi154; + input Pi155; + input Pi156; + input Pi157; + input Pi158; + input Pi159; + input Pi16; + input Pi160; + input Pi161; + input Pi162; + input Pi163; + input Pi164; + input Pi165; + input Pi166; + input Pi167; + input Pi168; + input Pi169; + input Pi17; + input Pi170; + input Pi171; + input Pi172; + input Pi173; + input Pi174; + input Pi175; + input Pi176; + input Pi177; + input Pi178; + input Pi179; + input Pi18; + input Pi180; + input Pi181; + input Pi182; + input Pi183; + input Pi184; + input Pi185; + input Pi186; + input Pi187; + input Pi188; + input Pi189; + input Pi19; + input Pi190; + input Pi191; + input Pi192; + input Pi193; + input Pi194; + input Pi195; + input Pi196; + input Pi197; + input Pi198; + input Pi199; + input Pi20; + input Pi200; + input Pi201; + input Pi202; + input Pi203; + input Pi204; + input Pi205; + input Pi206; + input Pi207; + input Pi208; + input Pi209; + input Pi21; + input Pi210; + input Pi211; + input Pi212; + input Pi213; + input Pi214; + input Pi215; + input Pi216; + input Pi217; + input Pi218; + input Pi219; + input Pi22; + input Pi220; + input Pi221; + input Pi222; + input Pi223; + input Pi224; + input Pi225; + input Pi226; + input Pi227; + input Pi228; + input Pi229; + input Pi23; + input Pi230; + input Pi231; + input Pi232; + input Pi233; + input Pi234; + input Pi235; + input Pi236; + input Pi237; + input Pi238; + input Pi239; + input Pi24; + input Pi240; + input Pi241; + input Pi242; + input Pi243; + input Pi244; + input Pi245; + input Pi246; + input Pi247; + input Pi248; + input Pi249; + input Pi25; + input Pi250; + input Pi251; + input Pi252; + input Pi253; + input Pi254; + input Pi255; + input Pi256; + input Pi257; + input Pi258; + input Pi259; + input Pi26; + input Pi260; + input Pi261; + input Pi262; + input Pi263; + input Pi264; + input Pi265; + input Pi266; + input Pi267; + input Pi268; + input Pi269; + input Pi27; + input Pi270; + input Pi271; + input Pi272; + input Pi273; + input Pi274; + input Pi275; + input Pi276; + input Pi277; + input Pi278; + input Pi279; + input Pi28; + input Pi280; + input Pi281; + input Pi282; + input Pi283; + input Pi284; + input Pi285; + input Pi286; + input Pi287; + input Pi288; + input Pi289; + input Pi290; + input Pi291; + input Pi292; + input Pi293; + input Pi294; + input Pi295; + input Pi296; + input Pi297; + input Pi298; + input Pi299; + input Pi300; + input Pi301; + input Pi302; + input Pi303; + input Pi304; + input Pi305; + input Pi306; + input Pi307; + input Pi308; + input Pi309; + input Pi310; + input Pi311; + input Pi312; + input Pi313; + input Pi314; + input Pi315; + input Pi316; + input Pi317; + input Pi318; + input Pi319; + input Pi320; + input Pi321; + input Pi322; + input Pi323; + input Pi324; + input Pi325; + input Pi326; + input Pi327; + input Pi328; + input Pi329; + input Pi330; + input Pi331; + input Pi332; + input Pi333; + input Pi334; + input Pi335; + input Pi336; + input Pi337; + input Pi338; + input Pi339; + input Pi340; + input Pi341; + input Pi342; + input Pi343; + input Pi344; + input Pi345; + input Pi346; + input Pi347; + input Pi348; + input Pi349; + input Pi350; + input Pi351; + input Pi352; + input Pi353; + input Pi354; + input Pi355; + input Pi356; + input Pi357; + input Pi358; + input Pi359; + input Pi360; + input Pi361; + input Pi362; + input Pi363; + input Pi364; + input Pi365; + input Pi366; + input Pi367; + input Pi368; + input Pi369; + input Pi370; + input Pi371; + input Pi372; + input Pi373; + input Pi374; + input Pi375; + input Pi376; + input Pi377; + input Pi378; + input Pi379; + input Pi380; + input Pi381; + input Pi382; + input Pi383; + input Pi384; + input Pi385; + input Pi386; + input Pi387; + input Pi388; + input Pi389; + input Pi390; + input Pi391; + input Pi392; + input Pi393; + input Pi394; + input Pi395; + input Pi396; + input Pi397; + input Pi398; + input Pi399; + input Pi400; + input Pi401; + input Pi402; + input Pi403; + input Pi404; + input Pi405; + input Pi406; + input Pi407; + input Pi408; + input Pi409; + input Pi410; + input Pi411; + input Pi412; + input Pi413; + input Pi414; + input Pi415; + input Pi416; + input Pi49; + input Pi50; + input Pi51; + input Pi52; + input Pi53; + input Pi54; + input Pi55; + input Pi56; + input Pi57; + input Pi58; + input Pi59; + input Pi60; + input Pi61; + input Pi62; + input Pi63; + input Pi64; + input Pi65; + input Pi66; + input Pi67; + input Pi68; + input Pi69; + input Pi70; + input Pi71; + input Pi72; + input Pi73; + input Pi74; + input Pi75; + input Pi76; + input Pi77; + input Pi78; + input Pi79; + input Pi80; + input Pi81; + input Pi82; + input Pi83; + input Pi84; + input Pi85; + input Pi86; + input Pi87; + input Pi88; + input Pi89; + input Pi90; + input Pi91; + input Pi92; + input Pi93; + input Pi94; + input Pi95; + input Pi96; + input Pi97; + input Pi98; + input Pi99; + input clock; + wire n1000; + wire n1001; + wire n1001_1; + wire n1002; + wire n1003; + wire n1004; + wire n1005; + wire n1006; + wire n1006_1; + wire n1007; + wire n1008; + wire n1009; + wire n1010; + wire n1011; + wire n1011_1; + wire n1012; + wire n1013; + wire n1014; + wire n1015; + wire n1016; + wire n1016_1; + wire n1017; + wire n1018; + wire n1019; + wire n1020; + wire n1021; + wire n1021_1; + wire n1022; + wire n1023; + wire n1024; + wire n1025; + wire n1026; + wire n1026_1; + wire n1027; + wire n1028; + wire n1029; + wire n1030; + wire n1031; + wire n1031_1; + wire n1032; + wire n1033; + wire n1034; + wire n1035; + wire n1036; + wire n1036_1; + wire n1037; + wire n1038; + wire n1039; + wire n1040; + wire n1041; + wire n1041_1; + wire n1042; + wire n1043; + wire n1044; + wire n1045; + wire n1046; + wire n1046_1; + wire n1047; + wire n1048; + wire n1049; + wire n1050; + wire n1051; + wire n1051_1; + wire n1052; + wire n1053; + wire n1054; + wire n1055; + wire n1056; + wire n1056_1; + wire n1057; + wire n1058; + wire n1059; + wire n1060; + wire n1061; + wire n1061_1; + wire n1062; + wire n1063; + wire n1064; + wire n1065; + wire n1066; + wire n1066_1; + wire n1067; + wire n1068; + wire n1069; + wire n1070; + wire n1071; + wire n1071_1; + wire n1072; + wire n1073; + wire n1074; + wire n1075; + wire n1076; + wire n1076_1; + wire n1077; + wire n1078; + wire n1079; + wire n1080; + wire n1081; + wire n1081_1; + wire n1082; + wire n1083; + wire n1084; + wire n1085; + wire n1085_1; + wire n1086; + wire n1087; + wire n1088; + wire n1089; + wire n1090; + wire n1090_1; + wire n1091; + wire n1092; + wire n1093; + wire n1094; + wire n1095; + wire n1096; + wire n1097; + wire n1098; + wire n1099; + wire n1100; + wire n1101; + wire n1102; + wire n1103; + wire n1104; + wire n1105; + wire n1106; + wire n1107; + wire n1108; + wire n1109; + wire n1110; + wire n1111; + wire n1112; + wire n1113; + wire n1114; + wire n1115; + wire n1116; + wire n1117; + wire n1118; + wire n1119; + wire n1120; + wire n1121; + wire n1122; + wire n1123; + wire n1124; + wire n1125; + wire n1126; + wire n1127; + wire n1128; + wire n1129; + wire n1130; + wire n1131; + wire n1132; + wire n1133; + wire n1134; + wire n1135; + wire n1137; + wire n1138; + wire n1139; + wire n1140; + wire n1141; + wire n1142; + wire n1143; + wire n1144; + wire n1145; + wire n1146; + wire n1147; + wire n1148; + wire n1149; + wire n1150; + wire n1151; + wire n1152; + wire n1153; + wire n1154; + wire n1155; + wire n1156; + wire n1157; + wire n1158; + wire n1159; + wire n1160; + wire n1161; + wire n1162; + wire n1163; + wire n1164; + wire n1165; + wire n1166; + wire n1167; + wire n1168; + wire n1169; + wire n1170; + wire n1171; + wire n1172; + wire n1173; + wire n1174; + wire n1175; + wire n1176; + wire n1177; + wire n1178; + wire n1179; + wire n1180; + wire n1181; + wire n1182; + wire n1183; + wire n1184; + wire n1185; + wire n1186; + wire n1187; + wire n1188; + wire n1189; + wire n1190; + wire n1191; + wire n1192; + wire n1193; + wire n1194; + wire n1195; + wire n1196; + wire n1197; + wire n1198; + wire n1199; + wire n1200; + wire n1201; + wire n1202; + wire n1203; + wire n1204; + wire n1205; + wire n1206; + wire n1207; + wire n1208; + wire n1209; + wire n1210; + wire n1211; + wire n1212; + wire n1213; + wire n1214; + wire n1215; + wire n1216; + wire n1217; + wire n1218; + wire n1219; + wire n1220; + wire n1221; + wire n1222; + wire n1223; + wire n1224; + wire n1225; + wire n1226; + wire n1227; + wire n1228; + wire n1229; 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n1301; + wire n1302; + wire n1303; + wire n1304; + wire n1305; + wire n1306; + wire n1307; + wire n1308; + wire n1309; + wire n1310; + wire n1311; + wire n1312; + wire n1313; + wire n1314; + wire n1315; + wire n1316; + wire n1317; + wire n1318; + wire n1319; + wire n1320; + wire n1321; + wire n1322; + wire n1323; + wire n1324; + wire n1325; + wire n1326; + wire n1327; + wire n1328; + wire n1329; + wire n1330; + wire n1331; + wire n1332; + wire n1333; + wire n1334; + wire n1335; + wire n1336; + wire n1337; + wire n1338; + wire n1339; + wire n1340; + wire n1341; + wire n1342; + wire n1343; + wire n1344; + wire n1345; + wire n1346; + wire n1347; + wire n1348; + wire n1349; + wire n1350; + wire n1351; + wire n1352; + wire n1353; + wire n1354; + wire n1355; + wire n1356; + wire n1357; + wire n1358; + wire n1359; + wire n1360; + wire n1361; + wire n1362; + wire n1363; + wire n1364; + wire n1365; + wire n1366; + wire n1367; + wire n1368; + wire n1369; + wire n1370; + wire n1371; + wire n1372; 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n1444; + wire n1445; + wire n1446; + wire n1447; + wire n1448; + wire n1449; + wire n1450; + wire n1451; + wire n1452; + wire n1453; + wire n1454; + wire n1455; + wire n1456; + wire n1457; + wire n1458; + wire n1459; + wire n1460; + wire n1461; + wire n1462; + wire n1463; + wire n1464; + wire n1465; + wire n1466; + wire n1467; + wire n1468; + wire n1469; + wire n1470; + wire n1471; + wire n1472; + wire n1473; + wire n1474; + wire n1475; + wire n1476; + wire n1477; + wire n1478; + wire n1479; + wire n1480; + wire n1481; + wire n1482; + wire n1483; + wire n1484; + wire n1485; + wire n1486; + wire n1487; + wire n1488; + wire n1489; + wire n1490; + wire n1491; + wire n1492; + wire n1493; + wire n1494; + wire n1495; + wire n1496; + wire n1497; + wire n1498; + wire n1499; + wire n1500; + wire n1501; + wire n1502; + wire n1503; + wire n1504; + wire n1505; + wire n1506; + wire n1507; + wire n1508; + wire n1509; + wire n1510; + wire n1511; + wire n1512; + wire n1513; + wire n1514; + wire n1515; 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n1587; + wire n1588; + wire n1589; + wire n1590; + wire n1591; + wire n1592; + wire n1593; + wire n1594; + wire n1595; + wire n1596; + wire n1597; + wire n1598; + wire n1599; + wire n1600; + wire n1601; + wire n1602; + wire n1603; + wire n1604; + wire n1605; + wire n1606; + wire n1607; + wire n1608; + wire n1609; + wire n1610; + wire n1611; + wire n1612; + wire n1613; + wire n1614; + wire n1615; + wire n1616; + wire n1617; + wire n1618; + wire n1619; + wire n1620; + wire n1621; + wire n1622; + wire n1623; + wire n1624; + wire n1625; + wire n1626; + wire n1627; + wire n1628; + wire n1629; + wire n1630; + wire n1631; + wire n1632; + wire n1633; + wire n1634; + wire n1635; + wire n1636; + wire n1637; + wire n1638; + wire n1639; + wire n1640; + wire n1641; + wire n1642; + wire n1643; + wire n1644; + wire n1645; + wire n1646; + wire n1647; + wire n1648; + wire n1649; + wire n1650; + wire n1651; + wire n1652; + wire n1653; + wire n1654; + wire n1655; + wire n1656; + wire n1657; + wire n1658; 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n1731; + wire n1732; + wire n1733; + wire n1734; + wire n1735; + wire n1736; + wire n1737; + wire n1738; + wire n1739; + wire n1740; + wire n1741; + wire n1742; + wire n1743; + wire n1744; + wire n1745; + wire n1746; + wire n1747; + wire n1748; + wire n1749; + wire n1750; + wire n1751; + wire n1752; + wire n1753; + wire n1754; + wire n1755; + wire n1756; + wire n1757; + wire n1758; + wire n1759; + wire n1760; + wire n1761; + wire n1762; + wire n1763; + wire n1764; + wire n1765; + wire n1766; + wire n1767; + wire n1768; + wire n1769; + wire n1770; + wire n1771; + wire n1772; + wire n1773; + wire n1774; + wire n1775; + wire n1776; + wire n1777; + wire n1778; + wire n1779; + wire n1780; + wire n1781; + wire n1782; + wire n1783; + wire n1784; + wire n1785; + wire n1786; + wire n1787; + wire n1788; + wire n1789; + wire n1790; + wire n1791; + wire n1792; + wire n1793; + wire n1794; + wire n1795; + wire n1796; + wire n1797; + wire n1798; + wire n1799; + (* init = 1'h0 *) + reg n18 = 1'h0; + wire n1800; + wire n1801; + wire n1802; + wire n1803; + wire n1804; + wire n1805; + wire n1806; + wire n1807; + wire n1808; + wire n1809; + wire n1810; + wire n1811; + wire n1812; + wire n1813; + wire n1814; + wire n1815; + wire n1816; + wire n1817; + wire n1818; + wire n1819; + wire n1820; + wire n1821; + wire n1822; + wire n1823; + wire n1824; + wire n1825; + wire n1826; + wire n1827; + wire n1828; + wire n1829; + wire n1830; + wire n1831; + wire n1832; + wire n1833; + wire n1834; + wire n1835; + wire n1836; + wire n1837; + wire n1838; + wire n1839; + wire n1840; + wire n1841; + wire n1842; + wire n1843; + wire n1844; + wire n1845; + wire n1846; + wire n1847; + wire n1848; + wire n1849; + wire n1850; + wire n1851; + wire n1852; + wire n1853; + wire n1854; + wire n1855; + wire n1856; + wire n1857; + wire n1858; + wire n1859; + wire n1860; + wire n1861; + wire n1862; + wire n1863; + wire n1864; + wire n1865; + wire n1866; + wire n1867; + wire n1868; + wire n1869; + wire n1870; + wire n1871; + wire n1872; + wire n1873; + wire n1874; + wire n1875; + wire n1876; + wire n1877; + wire n1878; + wire n1879; + wire n1880; + wire n1881; + wire n1882; + wire n1883; + wire n1884; + wire n1885; + wire n1886; + wire n1887; + wire n1888; + wire n1889; + wire n1890; + wire n1891; + wire n1892; + wire n1893; + wire n1894; + wire n1895; + wire n1896; + wire n1897; + wire n1898; + wire n1899; + wire n1900; + wire n1901; + wire n1902; + wire n1903; + wire n1904; + wire n1905; + wire n1906; + wire n1907; + wire n1908; + wire n1909; + wire n1910; + wire n1911; + wire n1912; + wire n1913; + wire n1914; + wire n1915; + wire n1916; + wire n1917; + wire n1918; + wire n1919; + wire n1920; + wire n1921; + wire n1922; + wire n1923; + wire n1924; + wire n1925; + wire n1926; + wire n1927; + wire n1928; + wire n1929; + wire n1930; + wire n1931; + wire n1932; + wire n1933; + wire n1934; + wire n1935; + wire n1936; + wire n1937; + wire n1938; + wire n1939; + wire n1940; + wire n1941; + wire n1942; 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n2014; + wire n2015; + wire n2016; + wire n2017; + wire n2018; + wire n2019; + wire n2020; + wire n2021; + wire n2022; + wire n2023; + wire n2024; + wire n2025; + wire n2026; + wire n2027; + wire n2028; + wire n2029; + wire n2030; + wire n2031; + wire n2032; + wire n2033; + wire n2034; + wire n2035; + wire n2036; + wire n2037; + wire n2038; + wire n2039; + wire n2040; + wire n2041; + wire n2042; + wire n2043; + wire n2044; + wire n2045; + wire n2046; + wire n2047; + wire n2048; + wire n2049; + wire n2050; + wire n2051; + wire n2052; + wire n2053; + wire n2054; + wire n2055; + wire n2056; + wire n2057; + wire n2058; + wire n2059; + wire n2060; + wire n2061; + wire n2062; + wire n2063; + wire n2064; + wire n2065; + wire n2066; + wire n2067; + wire n2068; + wire n2069; + wire n2070; + wire n2071; + wire n2072; + wire n2073; + wire n2074; + wire n2075; + wire n2076; + wire n2077; + wire n2078; + wire n2079; + wire n2080; + wire n2081; + wire n2082; + wire n2083; + wire n2084; + wire n2085; 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n2164; + wire n2165; + wire n2166; + wire n2167; + wire n2168; + wire n2169; + wire n2170; + wire n2171; + wire n2172; + wire n2173; + wire n2174; + wire n2175; + wire n2176; + wire n2177; + wire n2178; + wire n2179; + wire n2180; + wire n2181; + wire n2182; + wire n2183; + wire n2184; + wire n2185; + wire n2186; + wire n2187; + wire n2188; + wire n2189; + wire n2190; + wire n2191; + wire n2192; + wire n2193; + wire n2194; + wire n2195; + wire n2196; + wire n2197; + wire n2198; + wire n2199; + wire n2200; + wire n2201; + wire n2202; + wire n2203; + wire n2204; + wire n2205; + wire n2206; + wire n2207; + wire n2208; + wire n2209; + wire n2210; + wire n2211; + wire n2212; + wire n2213; + wire n2214; + wire n2215; + wire n2216; + wire n2217; + wire n2218; + wire n2219; + wire n2220; + wire n2221; + wire n2222; + wire n2223; + wire n2224; + wire n2225; + wire n2226; + wire n2227; + wire n2228; + wire n2229; + wire n2230; + wire n2231; + wire n2232; + wire n2233; + wire n2234; + wire n2235; + wire n2236; + wire n2237; + wire n2238; + wire n2239; + wire n2240; + wire n2241; + wire n2242; + wire n2243; + wire n2244; + wire n2245; + wire n2246; + wire n2247; + wire n2248; + wire n2249; + wire n2250; + wire n2251; + wire n2252; + wire n2253; + wire n2254; + wire n2255; + wire n2256; + wire n2257; + wire n2258; + wire n2259; + wire n2260; + wire n2261; + wire n2262; + wire n2263; + wire n2264; + wire n2265; + wire n2266; + wire n2267; + wire n2268; + wire n2269; + wire n2270; + wire n2271; + wire n2272; + wire n2273; + wire n2274; + wire n2275; + wire n2276; + wire n2277; + wire n2278; + wire n2279; + wire n2280; + wire n2281; + wire n2282; + wire n2283; + wire n2284; + wire n2285; + wire n2286; + wire n2287; + wire n2288; + wire n2289; + wire n2290; + wire n2291; + wire n2292; + wire n2293; + wire n2294; + wire n2295; + wire n2296; + wire n2297; + wire n2298; + wire n2299; + wire n2300; + wire n2301; + wire n2302; + wire n2303; + wire n2304; + wire n2305; + wire n2306; + wire n2307; + wire n2308; + wire n2309; + wire n2310; + wire n2311; + wire n2312; + wire n2313; + wire n2314; + wire n2315; + wire n2316; + wire n2317; + wire n2318; + wire n2319; + wire n2320; + wire n2321; + wire n2322; + wire n2323; + wire n2324; + wire n2325; + wire n2326; + wire n2327; + wire n2328; + wire n2329; + wire n2330; + wire n2331; + wire n2332; + wire n2333; + wire n2334; + wire n2335; + wire n2336; + wire n2337; + wire n2338; + wire n2339; + wire n2340; + wire n2341; + wire n2342; + wire n2343; + wire n2344; + wire n2345; + wire n2346; + wire n2347; + wire n2348; + wire n2349; + wire n2350; + wire n2351; + wire n2352; + wire n2353; + wire n2354; + wire n2355; + wire n2356; + wire n2357; + wire n2358; + wire n2359; + wire n2360; + wire n2361; + wire n2362; + wire n2363; + wire n2364; + wire n2365; + wire n2366; + wire n2367; + wire n2368; + wire n2369; + wire n2370; + wire n2371; + wire n2372; + wire n2373; + wire n2374; + wire n2375; + wire n2376; + wire n2377; + wire n2378; + wire n2379; + wire n2380; + wire n2381; + wire n2382; + wire n2383; + wire n2384; + wire n2385; + wire n2386; + wire n2387; + wire n2388; + wire n2389; + wire n2390; + wire n2391; + wire n2392; + wire n2393; + wire n2394; + wire n2395; + wire n2396; + wire n2397; + wire n2398; + wire n2399; + wire n2400; + wire n2401; + wire n2402; + wire n2403; + wire n2404; + wire n2405; + wire n2406; + wire n2407; + wire n2408; + wire n2409; + wire n2410; + wire n2411; + wire n2412; + wire n2413; + wire n2414; + wire n2415; + wire n2416; + wire n2417; + wire n2418; + wire n2419; + wire n2420; + wire n2421; + wire n2422; + wire n2423; + wire n2424; + wire n2425; + wire n2426; + wire n2427; + wire n2428; + wire n2429; + wire n2430; + wire n2431; + wire n2432; + wire n2433; + wire n2434; + wire n2435; + wire n2436; + wire n2437; + wire n2438; + wire n2439; + wire n2440; + wire n2441; + wire n2442; + wire n2443; + wire n2444; + wire n2445; + wire n2446; + wire n2447; + wire n2448; + wire n2449; + wire n2450; + wire n2451; + wire n2452; + wire n2453; + wire n2454; + wire n2455; + wire n2456; + wire n2457; + wire n2458; + wire n2459; + wire n2460; + wire n2461; + wire n2462; + wire n2463; + wire n2464; + wire n2465; + wire n2466; + wire n2467; + wire n2468; + wire n2469; + wire n2470; + wire n2471; + wire n2472; + wire n2473; + wire n2474; + wire n2475; + wire n2476; + wire n2477; + wire n2478; + wire n2479; + wire n2540; + wire n2542; + wire n2543; + wire n2545; + wire n2546; + wire n2547; + wire n2549; + wire n2550; + wire n2551; + wire n2552; + wire n2555; + wire n2556; + wire n2557; + wire n2558; + wire n2559; + wire n2560; + wire n2561; + wire n2562; + wire n2563; + wire n2564; + wire n2565; + wire n2566; + wire n2567; + wire n2568; + wire n2569; + wire n2570; + wire n2571; + wire n2572; + wire n2573; + wire n2574; + wire n2575; + wire n2576; + wire n2577; + wire n2578; + wire n2579; + wire n2580; + wire n2581; + wire n2582; + wire n2583; + wire n2584; + wire n2585; + wire n2586; + wire n2588; + wire n2589; + wire n2590; + wire n2591; + wire n2592; + wire n2593; + wire n2594; + wire n2595; + wire n2596; + wire n2597; + wire n2598; + wire n2599; + wire n2600; + wire n2601; + wire n2602; + wire n2603; + wire n2604; + wire n2605; + wire n2606; + wire n2607; + wire n2608; + wire n2609; + wire n2610; + wire n2611; + wire n2612; + wire n2613; + wire n2614; + wire n2615; + wire n2616; + wire n2617; + wire n2618; + wire n2619; + wire n2620; + wire n2621; + wire n2622; + wire n2623; + wire n2624; + wire n2625; + wire n2626; + wire n2627; + wire n2628; + wire n2629; + wire n2630; + wire n2631; + wire n2632; + wire n2633; + wire n2634; + wire n2635; + wire n2636; + wire n2637; + wire n2638; + wire n2639; + wire n2640; + wire n2641; + wire n2642; + wire n2643; + wire n2644; + wire n2645; + wire n2646; + wire n2647; + wire n2648; + wire n2649; + wire n2650; + wire n2651; + wire n2652; + wire n2653; + wire n2654; + wire n2655; + wire n2656; + wire n2657; + wire n2658; + wire n2659; + wire n2660; + wire n2661; + wire n2662; + wire n2663; + wire n2664; + wire n2665; + wire n2666; + wire n2667; + wire n2668; + wire n2669; + wire n2670; + wire n2671; + wire n2672; + wire n2673; + wire n2674; + wire n2675; + wire n2676; + wire n2677; + wire n2678; + wire n2679; + wire n2680; + wire n2681; + wire n2682; + wire n2683; + wire n2684; + wire n2685; + wire n2686; + wire n2687; + wire n2688; + wire n2689; + wire n2690; + wire n2691; + wire n2692; + wire n2693; + wire n2694; + wire n2695; + wire n2696; + wire n2697; + wire n2698; + wire n2699; + wire n2700; + wire n2701; + wire n2702; + wire n2703; + wire n2704; + wire n2705; + wire n2706; + wire n2707; + wire n2708; + wire n2709; + wire n2710; + wire n2711; + wire n2712; + wire n2713; + wire n2714; + wire n2715; + wire n2716; + wire n2717; + wire n2718; + wire n2719; + wire n2720; + wire n2721; + wire n2722; + wire n2723; + wire n2724; + wire n2725; + wire n2726; + wire n2727; + wire n2728; + wire n2729; + wire n2730; + wire n2731; + wire n2732; + wire n2733; + wire n2734; + wire n2735; + wire n2736; + wire n2737; + wire n2738; + wire n2739; + wire n2740; + wire n2741; + wire n2742; + wire n2743; + wire n2744; + wire n2745; + wire n2746; + wire n2747; + wire n2748; + wire n2749; + wire n2750; + wire n2751; + wire n2752; + wire n2753; + wire n2754; + wire n2755; + wire n2756; + wire n2757; + wire n2758; + wire n2759; + wire n2760; + wire n2761; + wire n2762; + wire n2763; + wire n2764; + wire n2765; + wire n2766; + wire n2767; + wire n2768; + wire n2769; + wire n2770; + wire n2771; + wire n2772; + wire n2773; + wire n2774; + wire n2775; + wire n2776; + wire n2777; + wire n2778; + wire n2779; + wire n2780; + wire n2781; + wire n2782; + wire n2783; + wire n2784; + wire n2785; + wire n2786; + wire n2787; + wire n2788; + wire n2789; + wire n2790; + wire n2791; + wire n2792; + wire n2793; + wire n2794; + wire n2795; + wire n2796; + wire n2797; + wire n2798; + wire n2799; + wire n2800; + wire n2801; + wire n2802; + wire n2803; + wire n2805; + wire n2806; + wire n2807; + wire n2809; + wire n2810; + wire n2811; + wire n2812; + wire n2813; + wire n2814; + wire n2815; + wire n2816; + wire n2817; + wire n2818; + wire n2819; + wire n2820; + wire n2821; + wire n2822; + wire n2823; + wire n2824; + wire n2825; + wire n2826; + wire n2827; + wire n2828; + wire n2829; + wire n2830; + wire n2831; + wire n2832; + wire n2833; + wire n2834; + wire n2835; + wire n2836; + wire n2837; + wire n2838; + wire n2839; + wire n2840; + wire n2841; + wire n2842; + wire n2843; + wire n2844; + wire n2845; + wire n2846; + wire n2847; + wire n2848; + wire n2849; + wire n2850; + wire n2851; + wire n2852; + wire n2853; + wire n2854; + wire n2855; + wire n2856; + wire n2857; + wire n2858; + wire n2860; + wire n2862; + wire n2864; + wire n2865; + wire n2866; + wire n2867; + wire n2868; + wire n2869; + wire n2870; + wire n2871; + wire n2872; + wire n2873; + wire n2874; + wire n2875; + wire n2876; + wire n2877; + wire n2878; + wire n2880; + wire n2881; + wire n2882; + wire n2883; + wire n2884; + wire n2885; + wire n2886; + wire n2887; + wire n2888; + wire n2889; + wire n2890; + wire n2891; + wire n2892; + wire n2893; + wire n2894; + wire n2895; + wire n2896; + wire n2897; + wire n2898; + wire n2899; + wire n2900; + wire n2901; + wire n2902; + wire n2903; + wire n2904; + wire n2905; + wire n2906; + wire n2907; + wire n2908; + wire n2909; + wire n2910; + wire n2911; + wire n2912; + wire n2913; + wire n2914; + wire n2915; + wire n2916; + wire n2917; + wire n2918; + wire n2919; + wire n2920; + wire n2921; + wire n2922; + wire n2923; + wire n2924; + wire n2925; + wire n2926; + wire n2927; + wire n2928; + wire n2929; + wire n2930; + wire n2931; + wire n2932; + wire n2933; + wire n2934; + wire n2935; + wire n2936; + wire n2937; + wire n2938; + wire n2939; + wire n2940; + wire n2941; + wire n2942; + wire n2943; + wire n2944; + wire n2945; + wire n2946; + wire n2947; + wire n2948; + wire n2949; + wire n2950; + wire n2951; + wire n2952; + wire n2953; + wire n2954; + wire n2955; + wire n2956; + wire n2957; + wire n2958; + wire n2959; + wire n2960; + wire n2961; + wire n2962; + wire n2963; + wire n2964; + wire n2965; + wire n2966; + wire n2967; + wire n2968; + wire n2969; + wire n2970; + wire n2971; + wire n2972; + wire n2973; + wire n2974; + wire n2975; + wire n2976; + wire n2977; + wire n2978; + wire n2979; + wire n2980; + wire n2981; + wire n2982; + wire n2983; + wire n2984; + wire n2985; + wire n2986; + wire n2987; + wire n2988; + wire n2989; + wire n2990; + wire n2991; + wire n2992; + wire n2993; + wire n2994; + wire n2995; + wire n2996; + wire n2997; + wire n2998; + wire n2999; + wire n3000; + wire n3001; + wire n3002; + wire n3003; + wire n3004; + wire n3005; + wire n3006; + wire n3007; + wire n3008; + wire n3009; + wire n3010; + wire n3011; + wire n3012; + wire n3013; + wire n3014; + wire n3015; + wire n3016; + wire n3017; + wire n3018; + wire n3019; + wire n3020; + wire n3021; + wire n3022; + wire n3023; + wire n3024; + wire n3025; + wire n3026; + wire n3027; + wire n3028; + wire n3029; + wire n3030; + wire n3031; + wire n3032; + wire n3033; + wire n3034; + wire n3035; + wire n3036; + wire n3037; + wire n3038; + wire n3039; + wire n3040; + wire n3041; + wire n3042; + wire n3043; + wire n3044; + wire n3045; + wire n3046; + wire n3047; + wire n3048; + wire n3049; + wire n3050; + wire n3051; + wire n3052; + wire n3053; + wire n3054; + wire n3055; + wire n3056; + wire n3057; + wire n3058; + wire n3059; + wire n3060; + wire n3061; + wire n564; + wire n571; + wire n572; + wire n576; + wire n581; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n587; + wire n588; + wire n589; + wire n590; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n599; + wire n601; + wire n602; + wire n604; + wire n605; + wire n607; + wire n609; + wire n611; + wire n612; + wire n613; + wire n614; + wire n615; + wire n616; + wire n617; + wire n618; + wire n619; + wire n620; + wire n621; + wire n622; + wire n623; + wire n624; + wire n625; + wire n626; + wire n627; + wire n628; + wire n629; + wire n630; + wire n631; + wire n632; + wire n633; + wire n634; + wire n635; + wire n636; + wire n637; + wire n638; + wire n639; + wire n640; + wire n641; + wire n642; + wire n643; + wire n644; + wire n645; + wire n646; + wire n647; + wire n648; + wire n649; + wire n650; + wire n651; + wire n652; + wire n653; + wire n654; + wire n655; + wire n656; + wire n657; + wire n658; + wire n659; + wire n660; + wire n661; + wire n662; + wire n663; + wire n664; + wire n665; + wire n666; + wire n667; + wire n668; + wire n669; + wire n670; + wire n671; + wire n672; + wire n673; + wire n674; + wire n675; + wire n676; + wire n677; + wire n678; + wire n679; + wire n680; + wire n681; + wire n682; + wire n683; + wire n684; + wire n685; + wire n686; + wire n687; + wire n688; + wire n689; + wire n690; + wire n691; + wire n692; + wire n693; + wire n694; + wire n695; + wire n696; + wire n697; + wire n698; + wire n699; + wire n700; + wire n701; + wire n702; + wire n703; + wire n704; + wire n705; + wire n706; + wire n707; + wire n708; + wire n709; + wire n710; + wire n711; + wire n712; + wire n713; + wire n714; + wire n715; + wire n716; + wire n717; + wire n718; + wire n719; + wire n720; + wire n721; + wire n722; + wire n723; + wire n724; + wire n725; + wire n726; + wire n727; + wire n728; + wire n729; + wire n730; + wire n731; + wire n732; + wire n733; + wire n734; + wire n735; + wire n736; + wire n737; + wire n738; + wire n739; + wire n740; + wire n741; + wire n742; + wire n743; + wire n744; + wire n745; + wire n746; + wire n747; + wire n748; + wire n749; + wire n750; + wire n751; + wire n752; + wire n753; + wire n754; + wire n755; + wire n756; + wire n757; + wire n758; + wire n759; + wire n760; + wire n761; + wire n762; + wire n763; + wire n764; + wire n765; + wire n766; + wire n767; + wire n768; + wire n769; + wire n770; + wire n771; + wire n772; + wire n773; + wire n774; + wire n775; + wire n776; + wire n777; + wire n778; + wire n779; + wire n780; + wire n781; + wire n782; + wire n783; + wire n784; + wire n785; + wire n786; + wire n787; + wire n788; + wire n789; + wire n790; + wire n791; + wire n792; + wire n793; + wire n794; + wire n795; + wire n796; + wire n797; + wire n798; + wire n799; + wire n800; + wire n801; + wire n802; + wire n803; + wire n804; + wire n805; + wire n806; + wire n807; + wire n808; + wire n809; + wire n810; + wire n811; + wire n812; + wire n813; + wire n814; + wire n815; + wire n816; + wire n817; + wire n818; + wire n819; + wire n820; + wire n821; + wire n822; + wire n823; + wire n824; + wire n825; + wire n826; + wire n827; + wire n828; + wire n829; + wire n830; + wire n831; + wire n832; + wire n833; + wire n834; + wire n835; + wire n836; + wire n837; + wire n838; + wire n839; + wire n840; + wire n841; + wire n842; + wire n843; + wire n844; + wire n845; + wire n846; + wire n847; + wire n848; + wire n849; + wire n850; + wire n851; + wire n852; + wire n853; + wire n854; + wire n855; + wire n856; + wire n857; + wire n858; + wire n859; + wire n860; + wire n861; + wire n862; + wire n863; + wire n864; + wire n865; + wire n866; + wire n867; + wire n868; + wire n869; + wire n870; + wire n871; + wire n872; + wire n873; + wire n874; + wire n875; + wire n876; + wire n877; + wire n878; + wire n879; + wire n880; + wire n881; + wire n882; + wire n883; + wire n884; + wire n885; + wire n886; + wire n887; + wire n888; + wire n889; + wire n890; + wire n891; + wire n892; + wire n893; + wire n894; + wire n895; + wire n896; + wire n897; + wire n898; + wire n899; + wire n900; + wire n901; + wire n902; + wire n903; + wire n904; + wire n905; + wire n906; + wire n907; + wire n908; + wire n909; + wire n910; + wire n911; + wire n912; + wire n913; + wire n914; + wire n915; + wire n916; + wire n917; + wire n918; + wire n919; + wire n920; + wire n921; + wire n922; + wire n923; + wire n924; + wire n925; + wire n926; + wire n927; + wire n928; + wire n929; + wire n930; + wire n931; + wire n931_1; + wire n932; + wire n933; + wire n934; + wire n935; + wire n936; + wire n936_1; + wire n937; + wire n938; + wire n939; + wire n940; + wire n941; + wire n941_1; + wire n942; + wire n943; + wire n944; + wire n945; + wire n946; + wire n946_1; + wire n947; + wire n948; + wire n949; + wire n950; + wire n951; + wire n951_1; + wire n952; + wire n953; + wire n954; + wire n955; + wire n956; + wire n956_1; + wire n957; + wire n958; + wire n959; + wire n960; + wire n961; + wire n961_1; + wire n962; + wire n963; + wire n964; + wire n965; + wire n966; + wire n966_1; + wire n967; + wire n968; + wire n969; + wire n970; + wire n971; + wire n971_1; + wire n972; + wire n973; + wire n974; + wire n975; + wire n976; + wire n976_1; + wire n977; + wire n978; + wire n979; + wire n980; + wire n981; + wire n981_1; + wire n982; + wire n983; + wire n984; + wire n985; + wire n986; + wire n986_1; + wire n987; + wire n988; + wire n989; + wire n990; + wire n991; + wire n991_1; + wire n992; + wire n993; + wire n994; + wire n995; + wire n996; + wire n996_1; + wire n997; + wire n998; + wire n999; + always @(posedge clock) + Ni48 <= n931; + always @(posedge clock) + Ni39 <= n976; + always @(posedge clock) + Ni38 <= n981; + always @(posedge clock) + Ni37 <= n986_1; + always @(posedge clock) + Ni36 <= n991; + always @(posedge clock) + Ni35 <= n996; + always @(posedge clock) + Ni34 <= n1001_1; + always @(posedge clock) + Ni33 <= n1006; + always @(posedge clock) + Ni32 <= n1011; + always @(posedge clock) + Ni31 <= n1016; + always @(posedge clock) + Ni30 <= n1021_1; + always @(posedge clock) + Ni47 <= n936_1; + always @(posedge clock) + n18 <= n1026; + always @(posedge clock) + Ni14 <= n1031; + always @(posedge clock) + Ni13 <= n1036_1; + always @(posedge clock) + Ni12 <= n1041; + always @(posedge clock) + Ni11 <= n1046; + always @(posedge clock) + Ni10 <= n1051_1; + always @(posedge clock) + Ni9 <= n1056; + always @(posedge clock) + Ni8 <= n1061_1; + always @(posedge clock) + Ni7 <= n1066; + always @(posedge clock) + Ni6 <= n1071; + always @(posedge clock) + Ni46 <= n941; + always @(posedge clock) + Ni5 <= n1076_1; + always @(posedge clock) + Ni4 <= n1081_1; + always @(posedge clock) + Ni3 <= n1085; + always @(posedge clock) + Ni2 <= n1090; + always @(posedge clock) + Ni45 <= n946; + always @(posedge clock) + Ni44 <= n951; + always @(posedge clock) + Ni43 <= n956; + always @(posedge clock) + Ni42 <= n961; + always @(posedge clock) + Ni41 <= n966; + always @(posedge clock) + Ni40 <= n971_1; + assign n633 = 4'h8 >> { n634, n636 }; + assign n1533 = 32'd2863311522 >> { n1534, n1543, n1548, n1554, n677 }; + assign n1534 = 64'h0a2a0a2a2a2a0a2a >> { n1541, n1542, n1535, n1539, Pi19, Pi17 }; + assign n1535 = 64'hfffdf7f57f7d7775 >> { n1536, n1527, n1526, n597, Pi20, n624 }; + assign n1536 = 32'd1157973317 >> { n1147, n18, n1178, n1472, n1537 }; + assign n1537 = 4'hd >> { n599, n1538 }; + assign n1538 = 16'h5777 >> { Ni30, Ni33, Ni31, Ni32 }; + assign n1539 = 8'ha8 >> { n1163, n597, n1540 }; + assign n1540 = 64'haeaeffff040c55ff >> { Pi22, Ni32, n1150, Ni33, n602, Pi21 }; + assign n1541 = 32'd1157973317 >> { n1147, n18, n1180, n1472, n1537 }; + assign n1542 = 8'h08 >> { Pi20, n624, n597 }; + assign n634 = 16'h22a2 >> { n635, n619, Ni38, n617 }; + assign n1543 = 32'd707439146 >> { n1546, n1547, n1539, n1544, n746 }; + assign n1544 = 64'hfffddfddf7f5d7d5 >> { n1545, n1512, n1511, Pi20, n597, n624 }; + assign n1545 = 32'd1157973317 >> { n1147, n18, n1219, n1472, n1537 }; + assign n1546 = 32'd1157973317 >> { n1147, n18, n1221, n1472, n1537 }; + assign n1547 = 8'h80 >> { n597, n624, Pi20 }; + assign n1548 = 64'h2a222a22aaaa2a22 >> { n1520, n1553, n1552, n1491, n1549, n758 }; + assign n1549 = 32'd2324299914 >> { n1551, n1547, n1542, n1550, n1539 }; + assign n1550 = 16'h5444 >> { n1472, n18, n1199, n1537 }; + assign n1551 = 64'h2022202200222022 >> { n18, n1147, n1195, n1472, n599, n1538 }; + assign n1552 = 4'h2 >> { n597, n1332 }; + assign n635 = 8'h08 >> { Ni41, Ni44, Ni40 }; + assign n1553 = 8'h02 >> { n597, Pi20, n624 }; + assign n1554 = 16'hfd75 >> { n1555, n1522, n597, n1263 }; + assign n1555 = 16'h1101 >> { n1472, n1433, n1261, n1537 }; + assign n1556 = 64'hfd00ff00fd00fd00 >> { n1553, n1557, n758, n1560, n1558, n1539 }; + assign n1557 = 4'h1 >> { n1232, n1516 }; + assign n1558 = 32'd67392772 >> { n1551, n1547, n1550, n1542, n1559 }; + assign n1559 = 4'h8 >> { n1159, n1538 }; + assign n1560 = 8'ha8 >> { n1517, n1234, n1552 }; + assign n1561 = 64'h0001010100ff11ff >> { n1552, n1537, n1547, Ni32, n1257, n1509 }; + assign n1562 = 32'd1364283473 >> { n1472, n1433, n1143, n1261, n1537 }; + assign n636 = 16'h1151 >> { n635, n619, n637, n630 }; + assign n1563 = 64'hddd55555fff57775 >> { n1201, n1538, n1480, n1193, n597, n750 }; + assign n1564 = 8'ha2 >> { n1537, n1484, n1542 }; + assign n1565 = 64'h0001010100ff11ff >> { n1552, n1537, n1547, Ni32, n1210, n1486 }; + assign n1566 = 32'd35786671 >> { n1552, n1537, n1547, Ni32, n1471 }; + assign n1567 = 4'h2 >> { n1568, n1263 }; + assign n1568 = 8'h08 >> { n1272, n1496, n1538 }; + assign n1569 = 8'hea >> { n1496, n1160, n1162 }; + assign n1570 = 4'h2 >> { n597, n1263 }; + assign n1571 = 32'd1157973317 >> { n1147, n18, n1225, n1472, n1537 }; + assign n1572 = 32'd1157973317 >> { n1147, n18, n1223, n1472, n1537 }; + assign n637 = 16'h2220 >> { Ni38, Ni39, Ni36, Ni35 }; + assign n1573 = 32'd1157973317 >> { n1147, n18, n1186, n1472, n1537 }; + assign n1574 = 32'd1157973317 >> { n1147, n18, n1184, n1472, n1537 }; + assign n1575 = 32'd539107874 >> { n1142, n621, n1537, n1551, n1547 }; + assign n1576 = 8'h02 >> { n1491, n1198, n1552 }; + assign n1577 = 64'h0f1f0f1f2f3f0f1f >> { n1267, n1538, n1197, n750, n1490, n597 }; + assign n1578 = 4'h8 >> { n1160, n1496 }; + assign n1579 = 32'd4070764672 >> { n1582, n597, n1581, n1435, n1657 }; + assign n1580 = 8'h8a >> { n624, n1403, n1331 }; + assign n1581 = 64'h0a2a0a2a2a2a0a2a >> { Ni33, n602, Ni32, n624, n1436, n1540 }; + assign n1582 = 16'h2e0e >> { n1583, Ni11, Ni12, n584 }; + assign n638 = 8'h80 >> { n624, Pi20, Pi19 }; + assign n1583 = 8'h8a >> { n624, n1438, n1252 }; + assign n1584 = 8'h08 >> { Pi20, n624, n1585 }; + assign n1585 = 4'h1 >> { Pi23, Pi24 }; + assign n1586 = 8'h08 >> { n1585, n624, Pi20 }; + assign n1587 = 8'h02 >> { n1585, Pi20, n624 }; + assign n1588 = 8'h80 >> { n1585, n624, Pi20 }; + assign n1589 = 8'ha8 >> { n1163, n1585, n1540 }; + assign n1590 = 16'haaa8 >> { n1140, n1475, n1537, n1584 }; + assign n1591 = 32'd35786671 >> { n1586, n1537, n1588, Ni32, n1471 }; + assign n1592 = 16'hfddd >> { n1568, n1585, n1569, n1263 }; + assign n639 = 32'd2324335274 >> { n640, n642, n622, P__cmxig_1, Ni34 }; + assign n1593 = 64'h0101000155ff00ff >> { n1586, n1484, n1587, n1210, n1486, Ni32 }; + assign n1594 = 64'h0a2a0a2a2a2a0a2a >> { n1526, n1587, n1595, n1589, Pi19, Pi17 }; + assign n1595 = 64'hffdff7d77f5f7757 >> { n1536, n1541, n1527, Pi20, n1585, n624 }; + assign n1596 = 64'hffdf7f5ff7d77757 >> { n1545, n1546, n1512, Pi20, n1585, n624 }; + assign n1597 = 16'hdd0d >> { n1551, n1588, n1550, n1584 }; + assign n1598 = 64'hffdf7f5ff7d77757 >> { n1571, n1572, n1494, Pi20, n1585, n624 }; + assign n1599 = 64'hffdf7f5ff7d77757 >> { n1574, n1573, n1499, Pi20, n1585, n624 }; + assign n1600 = 64'h8a8a8a8aaa8a8a8a >> { n1537, n621, n1142, n1588, n1551, n1589 }; + assign n1601 = 16'haaa8 >> { n1166, n1507, n1537, n1584 }; + assign n1602 = 64'h00ff02ff01ff03ff >> { Ni32, n1537, n1332, n1509, n1257, n1585 }; + assign n640 = 64'h80888088aaaa8088 >> { n621, n641, Ni44, Ni41, n619, n617 }; + assign n1603 = 32'd4070764672 >> { n1582, n1585, n1581, n1435, n1657 }; + assign n1604 = 64'haaaaaaaaaaaaaa2a >> { n1605, n1610, n1617, n2707, n1614, n792 }; + assign n1605 = 64'h8a8a8a8a8a8aaa8a >> { n1491, n1198, n1609, n1608, n1606, n757 }; + assign n1606 = 32'd539107874 >> { n1142, n621, n1537, n1551, n1607 }; + assign n1607 = 8'h80 >> { n624, Pi24, Pi20 }; + assign n1608 = 64'h0f1f0f1f2f3f0f1f >> { n1267, n1538, n1197, n750, n1490, Pi24 }; + assign n1609 = 8'h08 >> { Pi24, n624, Pi20 }; + assign n1610 = 64'h2a222a22aaaa2a22 >> { n1485, n1609, n1613, n1483, n1611, n745 }; + assign n1611 = 64'h0101000155ff00ff >> { n1607, n1484, n1612, n1210, n1486, n1537 }; + assign n1612 = 8'h08 >> { Pi20, Pi24, n624 }; + assign n641 = 16'h4445 >> { Ni39, Ni38, Ni36, Ni37 }; + assign n1613 = 8'h02 >> { Pi24, Pi20, n624 }; + assign n1614 = 64'hd5d5d5d5d5d5ffd5 >> { Ni30, Pi16, n1559, n1615, n1616, n748 }; + assign n1615 = 16'hdd0d >> { n1574, n1612, n1573, n1607 }; + assign n1616 = 16'hdd0d >> { n1499, n1609, n1498, n1613 }; + assign n1617 = 8'h2a >> { n1619, n1618, n759 }; + assign n1618 = 64'h0f1f0f1f2f3f0f1f >> { n1265, n1538, n1190, n1332, n1481, Pi24 }; + assign n1619 = 64'hddd5fff555557775 >> { n1538, n1201, n1480, n1193, Pi24, n750 }; + assign n1620 = 16'hdd0d >> { n1571, n1612, n1572, n1607 }; + assign n1621 = 8'ha8 >> { Pi24, n1163, n1540 }; + assign n1622 = 64'h8000000000000000 >> { Pi24, Pi22, Pi17, Pi19, Pi16, Pi21 }; + assign n642 = 8'h08 >> { Ni38, n641, n617 }; + assign n1623 = 64'h0000000080000000 >> { Pi16, Pi22, Pi17, Pi19, Pi24, Pi21 }; + assign n1624 = 64'h0002000000020002 >> { n757, n1625, n1629, n1630, n1628, n1621 }; + assign n1625 = 64'h1111101101110011 >> { n1551, n1491, n1332, Pi24, n1626, n1627 }; + assign n1626 = 32'd2695013026 >> { n18, n1472, Ni32, n1199, n1613 }; + assign n1627 = 32'd2695013026 >> { n18, n1472, n1537, n1199, n1612 }; + assign n1628 = 32'd67392772 >> { n1523, n1133, n1522, n798, Pi24 }; + assign n1629 = 4'h2 >> { n1555, n1622 }; + assign n1630 = 4'h2 >> { n1562, n1623 }; + assign n1631 = 64'h2a222a22aaaa2a22 >> { n1527, n1609, n1613, n1526, n1632, n751 }; + assign n1632 = 16'hdd0d >> { n1536, n1607, n1541, n1612 }; + assign n643 = 4'h8 >> { n624, n644 }; + assign n1633 = 64'h008000aac0c0ffff >> { n759, n745, n1636, n1635, n1634, n1637 }; + assign n1634 = 64'h0101000155ff00ff >> { n1607, n1504, n1612, n1228, n1503, n1537 }; + assign n1635 = 64'h0101000155ff00ff >> { n1609, n1504, n1613, n1503, n1228, Ni32 }; + assign n1636 = 16'h4454 >> { n1551, n1607, n1627, n1559 }; + assign n1637 = 64'h00011111000fffff >> { n1613, n1609, n1517, n1234, n1516, n1232 }; + assign n1638 = 64'h2a222a22aaaa2a22 >> { n1545, n1612, n1607, n1546, n1639, n756 }; + assign n1639 = 16'hdd0d >> { n1512, n1609, n1511, n1613 }; + assign n1640 = 64'h00ff02ff01ff03ff >> { Ni32, n1537, n750, n1507, n1166, Pi24 }; + assign n1641 = 8'h80 >> { n594, Ni10, Ni8 }; + assign n1642 = 64'h2a0a2a0a2a2a2a0a >> { n2970, n2713, n1658, n1657, Ni11, n1659 }; + assign n644 = 4'h2 >> { Pi19, Pi20 }; + assign n1643 = 64'h00aa08aa80aa88aa >> { n1512, n1511, n1644, Pi20, n699, n677 }; + assign n1644 = 32'd2324299914 >> { n1520, n623, n643, n1491, n1163 }; + assign n1645 = 64'hf070f0707070f070 >> { Ni32, n1504, n632, n672, n1646, n1647 }; + assign n1646 = 32'd572662314 >> { Ni32, n1503, n1228, n638, n1163 }; + assign n1647 = 64'h00011111000fffff >> { n623, n643, n1517, n1234, n1516, n1232 }; + assign n1648 = 16'h888a >> { n1193, n1480, n1201, n623 }; + assign n1649 = 8'ha8 >> { n1481, n1190, n643 }; + assign n1650 = 64'h5757575757570057 >> { n1491, n1198, n643, n1490, n1197, n623 }; + assign n1651 = 16'haaa8 >> { Ni32, n1507, n1166, n623 }; + assign n1652 = 8'h02 >> { n1653, n1655, Pi17 }; + assign n645 = 4'h8 >> { Pi15, Pi16 }; + assign n1653 = 64'h2a222a22aaaa2a22 >> { n1527, n643, n623, n1526, n1654, n677 }; + assign n1654 = 64'h02aa02aa00aa02aa >> { n1472, n1433, n699, n1261, Ni32, n1163 }; + assign n1655 = 64'h2a222a22aaaa2a22 >> { n1499, n643, n623, n1498, n1656, n645 }; + assign n1656 = 16'ha222 >> { n1160, n1496, n699, n1163 }; + assign n1657 = 64'hee0eee0e0000ee0e >> { n1583, n582, n2708, Ni12, n1468, n1435 }; + assign n1658 = 4'h2 >> { n1435, n1529 }; + assign n1659 = 4'h1 >> { n594, n596 }; + assign n1660 = 8'h08 >> { Ni10, n594, Ni8 }; + assign n1661 = 64'h0101010101010111 >> { n1469, n1662, n1663, n1667, n1665, n1668 }; + assign n1662 = 64'h000800080008020a >> { n1347, n1346, n2653, Ni12, n584, n1531 }; + assign n646 = 4'h2 >> { n647, n622 }; + assign n1663 = 16'h1101 >> { Ni10, n1424, n572, n1664 }; + assign n1664 = 64'h20202020aa202020 >> { n1188, n1213, n1226, n1164, n1138, Ni10 }; + assign n1665 = 32'd10619050 >> { n2970, n1435, Ni11, n2713, n1666 }; + assign n1666 = 4'h2 >> { n718, n605 }; + assign n1667 = 4'h8 >> { n605, n718 }; + assign n1668 = 4'h2 >> { P__cmxcl_0, Ni32 }; + assign n1669 = 16'haaa8 >> { Ni5, Ni4, Ni6, P__cmxcl_0 }; + assign n1021_1 = 64'hdfddffdddfdddfdd >> { n3021, n2715, n1669, n1978, n2116, n2802 }; + assign n1671 = 8'h51 >> { n1677, n1672, Ni30 }; + assign n1672 = 4'h8 >> { n1673, n1676 }; + assign n647 = 4'h1 >> { n648, n650 }; + assign n1673 = 16'h4445 >> { n878, Ni38, n1675, n1674 }; + assign n1674 = 4'he >> { Ni45, Ni47 }; + assign n1675 = 16'h4445 >> { Ni44, Ni41, Ni42, Ni43 }; + assign n1676 = 8'ha2 >> { n1675, n937, n622 }; + assign n1677 = 4'h2 >> { n1678, P__cmxig_0 }; + assign n1678 = 64'h0010001011110010 >> { Ni43, Ni42, Ni38, Ni37, Ni45, Ni47 }; + assign n1679 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1299, n1677, n1305, n1680 }; + assign n1680 = 4'h8 >> { n1681, n1683 }; + assign n1681 = 16'haaab >> { n827, n1674, Ni38, n1682 }; + assign n1682 = 64'h0100010001010100 >> { Ni41, Ni44, Ni42, Ni43, Ni45, Ni47 }; + assign n648 = 32'd134785544 >> { n621, n641, Ni44, n649, n617 }; + assign n1683 = 8'ha2 >> { n1682, n937, n622 }; + assign n1684 = 8'ha2 >> { Ni31, Ni33, Ni30 }; + assign n1685 = 16'h5444 >> { n1676, n1673, n1684, n1686 }; + assign n1686 = 8'h02 >> { n1678, n1684, P__cmxig_0 }; + assign n1687 = 4'h2 >> { n624, n1688 }; + assign n1688 = 32'd2863311522 >> { Ni31, Pi26, Pi27, Ni33, Ni30 }; + assign n1689 = 64'hd0f0d0f0d0f0d0d0 >> { n1736, n1299, n1697, n746, n1687, n1690 }; + assign n1690 = 64'h0033313300f7f5f7 >> { Ni30, n1684, n1301, n1677, n1303, n1691 }; + assign n1691 = 4'h2 >> { n1696, n1692 }; + assign n1692 = 64'ha8a0a8a0a8a0a8a8 >> { Ni41, n635, Ni42, n1694, n1693, n1695 }; + assign n649 = 32'd1 >> { Ni41, Ni47, Ni43, Ni45, Ni42 }; + assign n1693 = 8'h01 >> { Ni47, Ni43, Ni45 }; + assign n1694 = 32'd1431655701 >> { Ni37, Ni36, Ni39, Ni35, Ni38 }; + assign n1695 = 32'd1 >> { Ni47, Ni45, Ni32, Ni31, Ni30 }; + assign n1696 = 32'd707406346 >> { Ni41, n635, n1693, Ni42, n621 }; + assign n1697 = 16'h5551 >> { n1702, n1677, n1698, Ni30 }; + assign n1698 = 32'd2695407784 >> { n1700, n1699, n896, n1701, n1695 }; + assign n1699 = 4'h1 >> { Ni41, Ni42 }; + assign n1700 = 4'h2 >> { Ni44, Ni40 }; + assign n1701 = 32'd16842753 >> { Ni42, Ni41, Ni43, Ni45, Ni47 }; + assign n1702 = 16'ha222 >> { n1700, n1699, n1701, n621 }; + assign n650 = 8'h08 >> { Ni38, n641, n617 }; + assign n1703 = 64'h8c8c8c8c8c8c888c >> { n1713, n1704, n1709, Pi19, Pi17, n1687 }; + assign n1704 = 4'h2 >> { n1705, n1303 }; + assign n1705 = 16'h5551 >> { n1708, n1677, n1706, Ni30 }; + assign n1706 = 32'd2829623464 >> { Ni42, n704, n1707, n1701, n1695 }; + assign n1707 = 32'd1431655761 >> { Ni36, Ni35, Ni37, Ni39, Ni38 }; + assign n1708 = 16'h22a2 >> { Ni42, n704, n1701, n621 }; + assign n1709 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1299, n1677, n1305, n1710 }; + assign n1710 = 4'h2 >> { n1712, n1711 }; + assign n1711 = 32'd2829623464 >> { Ni42, n695, n926, n1701, n1695 }; + assign n1712 = 16'h22a2 >> { Ni42, n695, n1701, n621 }; + assign n651 = 4'h8 >> { n652, n654 }; + assign n1713 = 32'd2290649256 >> { n1708, n1677, n1706, n1684, n1301 }; + assign n1714 = 8'hab >> { n1715, n1718, n1721 }; + assign n1715 = 8'h02 >> { n1717, n1686, n1716 }; + assign n1716 = 4'h8 >> { n1263, n1296 }; + assign n1717 = 16'h1151 >> { n1701, Ni38, n1695, n1684 }; + assign n1718 = 16'h0002 >> { n1719, n1686, n1296, n1263 }; + assign n1719 = 16'h1151 >> { n1701, Ni38, n1695, Ni30 }; + assign n1720 = 8'h02 >> { n1701, Ni30, n621 }; + assign n1721 = 8'h02 >> { n1701, n1684, n621 }; + assign n1722 = 32'd2829623464 >> { Ni42, n695, n926, n1693, n1695 }; + assign n652 = 8'ha2 >> { n653, Ni38, n617 }; + assign n1723 = 8'h51 >> { n1677, n1724, Ni30 }; + assign n1724 = 32'd2829623464 >> { Ni42, n704, n1707, n1693, n1695 }; + assign n1725 = 16'h2220 >> { Ni30, n1722, n1686, n1299 }; + assign n1726 = 64'h1111001101010001 >> { n1730, n1733, n1303, n1299, n1727, n1687 }; + assign n1727 = 16'h2220 >> { n1684, n1728, n1686, n1301 }; + assign n1728 = 16'h888a >> { n878, Ni38, n1729, n1695 }; + assign n1729 = 16'h5551 >> { Ni42, Ni41, Ni44, Ni43 }; + assign n1730 = 8'h51 >> { n1677, n1731, Ni30 }; + assign n1731 = 16'h888a >> { n827, Ni38, n1732, n1695 }; + assign n1732 = 16'h5554 >> { Ni41, Ni42, Ni44, Ni43 }; + assign n653 = 64'h0000000100010001 >> { Ni40, Ni44, Ni41, Ni43, Ni45, Ni42 }; + assign n1733 = 8'h51 >> { n1677, n1728, Ni30 }; + assign n1734 = 8'h8a >> { Ni38, n1693, n1695 }; + assign n1735 = 32'd2829623464 >> { Ni42, n635, n1694, n1693, n1695 }; + assign n1736 = 16'h2220 >> { n1684, n1737, n1686, n1305 }; + assign n1737 = 32'd2695407784 >> { n1700, n1699, n896, n1693, n1695 }; + assign n1738 = 4'h1 >> { n1734, n1684 }; + assign n1739 = 4'h2 >> { n1740, n1735 }; + assign n1740 = 16'h22a2 >> { Ni42, n635, n1693, n621 }; + assign n1741 = 4'h2 >> { n1742, n1737 }; + assign n1742 = 16'ha222 >> { n1699, n1700, n1693, n621 }; + assign n654 = 8'h51 >> { n653, n637, n630 }; + assign n1743 = 16'h5551 >> { n1740, n1677, n1735, Ni30 }; + assign n1744 = 64'h8c8c8c8c8c8c888c >> { n1745, n1748, n1750, Pi19, Pi17, n1687 }; + assign n1745 = 16'h88a8 >> { n1677, n1746, n1684, n1305 }; + assign n1746 = 4'h2 >> { n1747, n1722 }; + assign n1747 = 16'h22a2 >> { Ni42, n695, n1693, n621 }; + assign n1748 = 4'h2 >> { n1749, n1725 }; + assign n1749 = 32'd33694210 >> { Ni42, n695, n1693, Ni30, n621 }; + assign n1750 = 64'h0033313300f7f5f7 >> { Ni30, n1684, n1301, n1677, n1303, n1751 }; + assign n1751 = 4'h2 >> { n1752, n1724 }; + assign n1752 = 16'h22a2 >> { Ni42, n704, n1693, n621 }; + assign n655 = 16'h8088 >> { Ni38, n656, n617, n657 }; + assign n1753 = 32'd3832930421 >> { n1762, n1754, Ni30, n1299, n1677 }; + assign n1754 = 32'd16777473 >> { n1303, n1761, n1755, n1758, n1687 }; + assign n1755 = 32'd572530720 >> { n1756, n1757, n1684, n1686, n1301 }; + assign n1756 = 16'h4445 >> { n878, Ni38, n1729, n1674 }; + assign n1757 = 8'ha2 >> { n1729, n937, n622 }; + assign n1758 = 32'd572530720 >> { n1759, n1760, n1684, n1686, n1305 }; + assign n1759 = 16'h4445 >> { n827, Ni38, n1732, n1674 }; + assign n1760 = 8'ha2 >> { n1732, n937, n622 }; + assign n1761 = 16'h5515 >> { n1677, n1757, n1756, Ni30 }; + assign n1762 = 4'h8 >> { n1759, n1760 }; + assign n656 = 64'h0001000000010001 >> { Ni40, Ni44, Ni41, Ni43, Ni45, Ni42 }; + assign n1763 = 8'h02 >> { n1693, n1684, n621 }; + assign n1764 = 32'd353703173 >> { Ni38, n621, n1695, n1693, Ni30 }; + assign n1765 = 16'h2220 >> { n1684, n1706, n1686, n1301 }; + assign n1766 = 8'h51 >> { n1677, n1706, Ni30 }; + assign n1767 = 64'haaafabafaabfbbbf >> { n1684, Ni30, n1299, n1305, n1711, n1686 }; + assign n1768 = 64'haaafabafaabfbbbf >> { Ni30, n1684, n1301, n1303, n1692, n1686 }; + assign n1769 = 8'h51 >> { n1677, n1770, Ni30 }; + assign n1770 = 16'h888a >> { n878, Ni38, n1675, n1695 }; + assign n1771 = 64'haaafabafaabfbbbf >> { n1772, n1770, n1301, n1305, n1684, n1686 }; + assign n1772 = 16'h888a >> { n827, Ni38, n1682, n1695 }; + assign n657 = 4'hd >> { n656, n631 }; + assign n1773 = 8'h51 >> { n1677, n1772, Ni30 }; + assign n1774 = 16'h5515 >> { n1677, n1683, n1681, Ni30 }; + assign n1775 = 16'h2220 >> { n1684, n1680, n1686, n1326 }; + assign n1776 = 64'hfe00ff00fe00fe00 >> { n1324, n1777, n751, n1781, n1778, n1780 }; + assign n1777 = 16'h5551 >> { n1752, n1677, n1724, Ni30 }; + assign n1778 = 32'd33686016 >> { n1684, n1722, n1779, n1686, n1326 }; + assign n1779 = 32'd33694210 >> { Ni42, n695, n1693, n1684, n621 }; + assign n1780 = 32'd2290649256 >> { n1752, n1677, n1724, n1684, n1325 }; + assign n1781 = 32'd33686016 >> { Ni30, n1722, n1749, n1686, n1323 }; + assign n1782 = 16'h5551 >> { n1742, n1677, n1737, Ni30 }; + assign n658 = 32'd1442314231 >> { n649, Ni44, Ni38, n618, n617 }; + assign n1783 = 16'h2220 >> { n1684, n1735, n1686, n1325 }; + assign n1784 = 8'h08 >> { n1677, n1741, n1326 }; + assign n1785 = 64'h8a0a8a0a8a8a8a0a >> { n1677, n1691, Ni30, n2734, n1324, n745 }; + assign n1786 = 32'd570556930 >> { n1700, n1699, n1701, Ni30, n621 }; + assign n1787 = 32'd2290649256 >> { n1708, n1677, n1706, n1684, n1325 }; + assign n1788 = 8'h54 >> { n1684, n1789, n1686 }; + assign n1789 = 4'h8 >> { n1756, n1757 }; + assign n1790 = 16'h7707 >> { n1761, n1324, n1791, n1326 }; + assign n1791 = 16'h5444 >> { n1760, n1759, n1684, n1686 }; + assign n1792 = 8'h08 >> { n1677, n1762, n1323 }; + assign n659 = 4'h2 >> { Pi16, Pi15 }; + assign n1793 = 8'h02 >> { n1738, n1686, n798 }; + assign n1794 = 8'h45 >> { Ni30, Pi27, n1684 }; + assign n1795 = 8'h01 >> { n1719, n1720, n1686 }; + assign n1796 = 64'h2202220222022222 >> { n1737, n1684, n1686, n1326, n1783, n1797 }; + assign n1797 = 64'haaafabafaabfbbbf >> { n1735, n1737, n1323, n1324, Ni30, n1686 }; + assign n1798 = 64'h05cd05dd05cf05ff >> { n1706, n1711, Ni30, n1323, n1677, n1324 }; + assign n1799 = 64'hddddddfddddfddff >> { Ni30, n1684, n1722, Pi27, n1686, n750 }; + assign n1800 = 64'h5555d5dd7577f5ff >> { Ni30, n1684, n1724, n1677, Pi27, n1332 }; + assign n1801 = 64'h2a222a22aaaa2a22 >> { n1733, n1324, n1323, n1730, n1802, n757 }; + assign n1802 = 64'haaafabafaabfbbbf >> { n1731, n1728, n1325, n1326, n1684, n1686 }; + assign n660 = 8'h02 >> { n661, n663, n654 }; + assign n1803 = 32'd1059010325 >> { n1324, n1323, n1769, n1773, n1804 }; + assign n1804 = 64'haaafabafaabfbbbf >> { n1772, n1770, n1325, n1326, n1684, n1686 }; + assign n1805 = 4'h1 >> { n1806, n2982 }; + assign n1806 = 64'h0001000000010001 >> { n677, n1812, n1815, n1819, n1807, Pi17 }; + assign n1807 = 32'd4278189822 >> { n623, n1774, n1811, n1809, n1808 }; + assign n1808 = 32'd2290649256 >> { n1696, n1677, n1692, Ni30, n638 }; + assign n1809 = 32'd1145328708 >> { n1677, n1676, n1673, Ni30, n1810 }; + assign n1810 = 8'h27 >> { Ni30, n644, n624 }; + assign n1811 = 32'd33686016 >> { Ni30, n1698, n1786, n1686, n632 }; + assign n1812 = 64'h1111011110110011 >> { n1782, n1743, n699, Pi20, n1813, n1814 }; + assign n661 = 4'h2 >> { n653, Ni38 }; + assign n1813 = 32'd2290657416 >> { n1677, n1760, n1759, Ni30, n623 }; + assign n1814 = 32'd1145328708 >> { n1677, n1757, n1756, Ni30, n1810 }; + assign n1815 = 32'd2728569506 >> { n1769, n643, n1817, n1816, n659 }; + assign n1816 = 64'hdddddddfddfdddff >> { n1692, n1698, Ni30, Pi20, n1686, n699 }; + assign n1817 = 16'h4454 >> { n1677, n1772, Ni30, n1818 }; + assign n1818 = 8'h27 >> { Ni30, n625, n624 }; + assign n1819 = 32'd2324335274 >> { n1730, n1818, n1821, n1820, n645 }; + assign n1820 = 16'h88a8 >> { n1677, n1728, Ni30, n643 }; + assign n1821 = 64'hddddddfddddfddff >> { n1737, n1735, Ni30, Pi20, n1686, n699 }; + assign n1822 = 32'd2829626024 >> { n1777, n643, n1824, n1823, n677 }; + assign n662 = 4'h1 >> { Ni36, Ni35 }; + assign n1823 = 32'd33686016 >> { Ni30, n1722, n1749, n1686, n623 }; + assign n1824 = 16'h1110 >> { n1825, n699, n1764, n1686 }; + assign n1825 = 4'h2 >> { n624, Ni30 }; + assign n1826 = 32'd2728569506 >> { n1723, n643, n1825, n1827, n645 }; + assign n1827 = 64'haaafabafaabfbbbf >> { n1734, n1722, n623, n699, Ni30, n1686 }; + assign n1828 = 32'd1145324628 >> { n1712, n1677, n1711, Ni30, n1818 }; + assign n1829 = 4'h1 >> { n2985, n1843 }; + assign n1830 = 32'd2324299914 >> { n1833, Pi16, Pi15, n1831, n1834 }; + assign n1831 = 16'h0213 >> { n1711, n1706, Ni30, Pi20 }; + assign n1832 = 16'h0123 >> { n1724, n1722, Ni30, Pi20 }; + assign n663 = 8'hab >> { n665, n653, n664 }; + assign n1833 = 64'hcecfcecf4445cecf >> { n1752, n1724, n1722, Ni30, n1749, Pi20 }; + assign n1834 = 64'h3133313320223133 >> { n1712, n1711, n1706, n1708, Ni30, Pi20 }; + assign n1835 = 16'h0213 >> { n1772, n1770, Ni30, Pi20 }; + assign n1836 = 64'h0222133313331333 >> { n1681, n1683, n1676, n1673, Ni30, Pi20 }; + assign n1837 = 16'h0213 >> { n1731, n1728, Ni30, Pi20 }; + assign n1838 = 16'h0213 >> { n1737, n1735, Ni30, Pi20 }; + assign n1839 = 16'h0123 >> { n1692, n1698, Ni30, Pi20 }; + assign n1840 = 64'hcecfcecf4445cecf >> { n1696, n1692, n1698, Ni30, n1786, Pi20 }; + assign n1841 = 64'h3133313320223133 >> { n1742, n1737, n1735, n1740, Ni30, Pi20 }; + assign n1842 = 64'h0222133313331333 >> { n1759, n1760, n1757, n1756, Ni30, Pi20 }; + assign n664 = 4'h2 >> { Ni38, Ni37 }; + assign n1843 = 8'h02 >> { n1806, n2982, n1529 }; + assign n1844 = 16'haa2a >> { Ni31, Ni33, n585, n1825 }; + assign n1845 = 32'd33686016 >> { Ni30, n1722, n1686, n585, n750 }; + assign n1846 = 32'd3708411137 >> { n1728, n1684, n1686, n1847, n1251 }; + assign n1847 = 64'h1010001011110011 >> { n1248, n1733, n1241, n1730, n1848, n1844 }; + assign n1848 = 16'h2220 >> { n1684, n1731, n1686, n1244 }; + assign n1849 = 32'd2863311402 >> { n1855, n1852, n1858, n1850, n672 }; + assign n1850 = 64'h0022222200020202 >> { n1671, n1685, n1251, n1241, n1844, n1851 }; + assign n1851 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1248, n1677, n1244, n1680 }; + assign n1852 = 64'hfd00fd00ff00fd00 >> { n1697, n1248, n746, n1844, n1854, n1853 }; + assign n665 = 4'h1 >> { Ni36, Ni37 }; + assign n1853 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1241, n1677, n1251, n1691 }; + assign n1854 = 32'd538976800 >> { n1702, n1698, n1684, n1686, n1244 }; + assign n1855 = 64'hfd00ff00fd00fd00 >> { n1241, n1705, Pi17, n1857, n1844, n1856 }; + assign n1856 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1248, n1677, n1244, n1710 }; + assign n1857 = 32'd2290649256 >> { n1708, n1677, n1706, n1684, n1251 }; + assign n1858 = 8'hf7 >> { n1717, n1795, n1263 }; + assign n1859 = 4'h1 >> { n1772, n1684 }; + assign n1860 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1241, n1677, n1251, n1770 }; + assign n1861 = 16'h2220 >> { n1684, n1698, n1686, n1244 }; + assign n1862 = 64'h8808880888088888 >> { n1711, Ni30, n1686, n1248, n1864, n1863 }; + assign n666 = 64'h2a2a2a2aaa2a2a2a >> { P__cmxig_1, n667, n622, Ni34, n632, n670 }; + assign n1863 = 32'd1364283733 >> { n1706, n1684, n1686, n1251, n1844 }; + assign n1864 = 64'hd0ddd0ddd0ddf0ff >> { n1684, n1711, n1241, n1766, n1686, n1244 }; + assign n1865 = 64'hfd00ff00fd00fd00 >> { n1241, n1743, n746, n1844, n1866, n1867 }; + assign n1866 = 16'h88a8 >> { n1677, n1739, n1684, n1251 }; + assign n1867 = 64'h0033313300f7f5f7 >> { n1684, Ni30, n1248, n1677, n1244, n1741 }; + assign n1868 = 64'h05cd05dd05cf05ff >> { n1789, n1762, Ni30, n1248, n1677, n1241 }; + assign n1869 = 16'h0002 >> { n1738, n1763, n1686, n1263 }; + assign n1870 = 32'd1414550612 >> { n1898, n1871, n1922, n583, Ni11 }; + assign n1871 = 64'h5555555555551555 >> { n1896, n1872, n1881, n1892, n1876, Pi15 }; + assign n1872 = 64'h8a888a88aaaa8a88 >> { n1841, n754, n1476, n1875, n1873, n756 }; + assign n667 = 8'h08 >> { n668, n657, n669 }; + assign n1873 = 16'h88a8 >> { n1874, n1739, Ni30, n1477 }; + assign n1874 = 4'h2 >> { n1678, P__cmxig_1 }; + assign n1875 = 16'h5551 >> { n1874, n1742, n1737, Ni30 }; + assign n1876 = 64'h7077707750557077 >> { n1880, n1477, n754, n1879, n1877, n745 }; + assign n1877 = 8'h02 >> { n1878, n1786, n1476 }; + assign n1878 = 8'h51 >> { n1874, n1698, Ni30 }; + assign n1879 = 64'hffdffbdbfdddf9d9 >> { n1834, n1840, n1833, Pi16, Pi19, Pi17 }; + assign n1880 = 16'h5551 >> { n1874, n1696, n1692, Ni30 }; + assign n1881 = 32'd4043436288 >> { n1836, n1889, n757, n1883, n1886 }; + assign n1882 = 16'h5515 >> { n1874, n1683, n1681, Ni30 }; + assign n668 = 8'h5d >> { n656, Ni38, n617 }; + assign n1883 = 32'd134785544 >> { n1885, n1477, n1884, n1476, n747 }; + assign n1884 = 16'h5551 >> { n1874, n1712, n1711, Ni30 }; + assign n1885 = 16'h5551 >> { n1874, n1708, n1706, Ni30 }; + assign n1886 = 16'h88a8 >> { n1888, n1477, n1887, n751 }; + assign n1887 = 64'h0200020002020200 >> { n1874, n1722, Ni30, n1749, Pi25, n750 }; + assign n1888 = 16'h5551 >> { n1874, n1752, n1724, Ni30 }; + assign n1889 = 32'd3774867711 >> { Pi25, n624, n1842, n1891, n1890 }; + assign n1890 = 16'h5515 >> { n1874, n1760, n1759, Ni30 }; + assign n1891 = 16'h5515 >> { n1874, n1757, n1756, Ni30 }; + assign n1892 = 32'd2004317959 >> { n1895, n1720, n1133, n973, n1893 }; + assign n669 = 4'he >> { n656, n665 }; + assign n1893 = 32'd572661794 >> { Ni30, n621, n1693, n1894, n699 }; + assign n1894 = 64'h1511151155551511 >> { n1693, Ni38, P__cmxig_1, n1678, n1695, Ni30 }; + assign n1895 = 64'h1511151155551511 >> { n1701, Ni38, P__cmxig_1, n1678, n1695, Ni30 }; + assign n1896 = 32'd2155905194 >> { n1720, n1719, n1897, Pi16, n755 }; + assign n1897 = 8'h8a >> { n621, n1693, n1734 }; + assign n1898 = 64'h1111111151111111 >> { n1899, n1912, n1901, n1904, Pi15, n1825 }; + assign n1899 = 64'h2a222a22aaaa2a22 >> { n1837, n757, n745, n1839, n1900, n754 }; + assign n1900 = 64'hffefdfcff7e7d7c7 >> { n1838, n1832, n1831, Pi17, Pi19, Pi16 }; + assign n1901 = 32'd3774867711 >> { Pi25, n624, n1835, n1903, n1902 }; + assign n1902 = 8'h51 >> { n1874, n1772, Ni30 }; + assign n670 = 64'h3b3b3b3bbb3b3b3b >> { P__cmxig_1, n622, n648, n644, Ni34, n624 }; + assign n1903 = 8'h51 >> { n1874, n1770, Ni30 }; + assign n1904 = 32'd33554946 >> { n745, n1908, n1911, n1905, n1910 }; + assign n1905 = 32'd134785544 >> { n1906, n1477, n1907, n1476, n757 }; + assign n1906 = 8'h51 >> { n1874, n1728, Ni30 }; + assign n1907 = 8'h51 >> { n1874, n1731, Ni30 }; + assign n1908 = 16'hdd0d >> { n1909, n1477, n1878, n1476 }; + assign n1909 = 8'h51 >> { n1874, n1692, Ni30 }; + assign n1910 = 16'hdd0d >> { n1895, n1133, n1894, n798 }; + assign n1911 = 16'ha222 >> { n1734, Pi16, n1719, n755 }; + assign n1912 = 8'h01 >> { n1913, n1916, n1919 }; + assign n671 = 32'd2852653064 >> { n649, Ni44, n621, n618, n617 }; + assign n1913 = 32'd134785544 >> { n1914, n1477, n1915, n1476, n747 }; + assign n1914 = 8'h51 >> { n1874, n1706, Ni30 }; + assign n1915 = 8'h51 >> { n1874, n1711, Ni30 }; + assign n1916 = 32'd134785544 >> { n1917, n1477, n1918, n1476, n756 }; + assign n1917 = 8'h51 >> { n1874, n1735, Ni30 }; + assign n1918 = 8'h51 >> { n1874, n1737, Ni30 }; + assign n1919 = 32'd134785544 >> { n1921, n1477, n1920, n1476, n751 }; + assign n1920 = 8'h51 >> { n1874, n1722, Ni30 }; + assign n1921 = 8'h51 >> { n1874, n1724, Ni30 }; + assign n1922 = 32'd2728436386 >> { n1923, n1899, n1924, n2747, n1529 }; + assign n672 = 4'h1 >> { Pi15, Pi16 }; + assign n1923 = 8'h45 >> { n754, n1835, n1911 }; + assign n1924 = 8'h54 >> { Ni30, n1925, n754 }; + assign n1925 = 8'h80 >> { n624, n622, n1678 }; + assign n1926 = 4'he >> { n1688, n1925 }; + assign n1927 = 16'h2777 >> { n1698, n1370, n1692, n1369 }; + assign n1928 = 32'd2829626024 >> { n1831, n1371, n1930, n1929, n748 }; + assign n1929 = 4'h8 >> { n1711, n1370 }; + assign n1930 = 8'ha8 >> { n1684, n1706, n1369 }; + assign n1931 = 32'd17900339 >> { n1680, n1672, n1369, n1926, n1370 }; + assign n1932 = 8'hfd >> { n1717, n1721, n755 }; + assign n673 = 16'ha888 >> { n629, n665, n674, n627 }; + assign n1933 = 32'd2969678595 >> { n1370, n1708, n1930, n1926, n1710 }; + assign n1934 = 32'd2728569506 >> { n1840, n1371, n1926, n1935, n746 }; + assign n1935 = 16'h2777 >> { n1369, n1691, n1936, n1370 }; + assign n1936 = 4'h2 >> { n1702, n1698 }; + assign n1937 = 16'h2777 >> { n1369, n1751, n1746, n1370 }; + assign n1938 = 32'd2728569506 >> { n1841, n1371, n1926, n1939, n746 }; + assign n1939 = 16'h2777 >> { n1369, n1739, n1741, n1370 }; + assign n1940 = 16'h2777 >> { n1369, n1789, n1762, n1370 }; + assign n1941 = 16'hbbab >> { n1738, n755, n1926, n1764 }; + assign n1942 = 16'h2777 >> { n1731, n1370, n1728, n1369 }; + assign n674 = 4'h2 >> { n628, n619 }; + assign n1943 = 16'h2777 >> { n1722, n1370, n1724, n1369 }; + assign n1944 = 4'hd >> { n1925, n1794 }; + assign n1945 = 32'd2728566946 >> { n1399, n1962, n1944, n1841, n746 }; + assign n1946 = 8'h80 >> { n1756, n1757, n1401 }; + assign n1947 = 8'h80 >> { n1759, n1760, n1400 }; + assign n1948 = 4'hd >> { n1763, n1949 }; + assign n1949 = 4'h8 >> { n1734, n755 }; + assign n1950 = 16'h2777 >> { n1770, n1401, n1772, n1400 }; + assign n1951 = 32'd17892863 >> { n1400, n1401, n1692, n1698, n1684 }; + assign n1952 = 64'hfe00fe00ff00fe00 >> { n1831, n1399, n748, n1953, n1954, n1944 }; + assign n675 = 8'h80 >> { n634, n676, n636 }; + assign n1953 = 4'h8 >> { n1711, n1400 }; + assign n1954 = 4'h8 >> { n1706, n1401 }; + assign n1955 = 4'hd >> { n1717, n755 }; + assign n1956 = 64'h8c8c8c8c8c8c8c88 >> { n1954, n1953, n1399, n1834, n748, n1944 }; + assign n1957 = 8'h80 >> { n1673, n1676, n1401 }; + assign n1958 = 8'h80 >> { n1681, n1683, n1400 }; + assign n1959 = 16'h2777 >> { n1724, n1401, n1722, n1400 }; + assign n1960 = 16'h2777 >> { n1728, n1401, n1731, n1400 }; + assign n1961 = 16'h22a2 >> { n1838, n1399, n1962, n746 }; + assign n1962 = 16'h2777 >> { n1735, n1401, n1737, n1400 }; + assign n676 = 16'h4454 >> { n635, n619, n665, n664 }; + assign n1963 = 8'hae >> { n2762, n840, n1844 }; + assign n1964 = 64'h8c8c8c8c8c8c8c88 >> { n1976, n1965, n1443, n1834, n748, n1963 }; + assign n1965 = 8'ha8 >> { n1684, n1706, n1442 }; + assign n1966 = 64'h8c8c8c8c8c8c8c88 >> { n1967, n1974, n1443, n1840, n746, n1963 }; + assign n1967 = 8'ha8 >> { n1684, n1698, n1440 }; + assign n1968 = 32'd17892863 >> { n1440, n1442, n1724, n1722, n1684 }; + assign n1969 = 32'd17892863 >> { n1440, n1442, n1728, n1731, n1684 }; + assign n1970 = 16'h22a2 >> { n1838, n1443, n1971, n746 }; + assign n1971 = 32'd17892863 >> { n1440, n1442, n1735, n1737, n1684 }; + assign n1972 = 4'h2 >> { n1738, n755 }; + assign n677 = 4'h2 >> { Pi15, Pi16 }; + assign n1973 = 64'hfe00ff00fe00fe00 >> { n1443, n1839, n746, n1974, n1967, n1963 }; + assign n1974 = 8'ha8 >> { n1684, n1692, n1442 }; + assign n1975 = 64'hfe00ff00fe00fe00 >> { n1443, n1831, n748, n1976, n1965, n1963 }; + assign n1976 = 8'ha8 >> { n1684, n1711, n1440 }; + assign n1977 = 64'h5150515051515150 >> { n1899, n1923, n2747, n1468, n1924, Ni10 }; + assign n1978 = 64'h0001000101010001 >> { n2783, n2113, n595, n2091, n2791, n1979 }; + assign n1979 = 64'h0a2a0a2a0a2a8aaa >> { n2019, n583, n2876, n2020, Ni11, n1660 }; + assign n1980 = 4'h2 >> { n1981, n1263 }; + assign n1981 = 64'h2a222a22aaaa2a22 >> { n1693, Ni38, P__cmxig_1, n1678, n1695, n1982 }; + assign n1982 = 8'h57 >> { Ni33, Ni31, Ni30 }; + assign n678 = 4'h8 >> { n679, n622 }; + assign n1983 = 16'h0222 >> { n1982, n1585, n624, Ni30 }; + assign n1984 = 64'hcd05dd05cf05ff05 >> { n1728, n1731, n1982, n1584, n1874, n1588 }; + assign n1985 = 32'd3722436575 >> { n1588, n1735, n1584, n1874, n1737 }; + assign n1986 = 32'd572662434 >> { n1874, n1747, n1722, n1982, n1584 }; + assign n1987 = 64'h0d0f0d0f0d0d0d0f >> { n1874, n1722, Ni30, n1983, n1749, n1587 }; + assign n1988 = 64'haaaaaaaaaaaaaaa8 >> { n1992, n1989, n1983, n1990, n1991, Pi19 }; + assign n1989 = 32'd572662434 >> { n1874, n1740, n1735, n1982, n1588 }; + assign n1990 = 32'd572662434 >> { n1874, n1742, n1737, n1982, n1584 }; + assign n1991 = 32'd2290649256 >> { n1874, n1742, n1737, Ni30, n1587 }; + assign n1992 = 32'd2290649256 >> { n1874, n1740, n1735, Ni30, n1586 }; + assign n679 = 8'h02 >> { n680, n683, n684 }; + assign n1993 = 64'h0001000000010001 >> { n1586, n1891, n1995, n1996, n1994, n1983 }; + assign n1994 = 32'd2290657416 >> { n1874, n1759, n1760, Ni30, n1587 }; + assign n1995 = 32'd572695074 >> { n1874, n1756, n1757, n1982, n1588 }; + assign n1996 = 32'd572695074 >> { n1874, n1759, n1760, n1982, n1584 }; + assign n1997 = 8'h5d >> { n1693, n621, n1980 }; + assign n1998 = 64'hcd05dd05cf05ff05 >> { n1770, n1772, n1982, n1584, n1874, n1588 }; + assign n1999 = 64'hd5dd5555f5ff7577 >> { Ni30, n1982, n1692, n1874, n1585, n1332 }; + assign n2000 = 64'hcd05dd05cf05ff05 >> { n1706, n1711, n1982, n1584, n1874, n1588 }; + assign n2001 = 16'h22a2 >> { n1874, n2002, n1982, n1263 }; + assign n2002 = 8'h8a >> { Ni38, n1701, n1695 }; + assign n680 = 8'h5d >> { n682, Ni38, n617 }; + assign n2003 = 8'h02 >> { n1895, n1585, n1263 }; + assign n2004 = 64'hfd00ff00fd00fd00 >> { n1586, n1880, n746, n2006, n2005, n2007 }; + assign n2005 = 32'd572662434 >> { n1874, n1696, n1692, n1982, n1588 }; + assign n2006 = 32'd538976800 >> { n1874, n1698, Ni30, n1786, n1587 }; + assign n2007 = 64'h3131313131311131 >> { n1874, n1702, n1698, n1982, n1983, n1584 }; + assign n2008 = 32'd572662434 >> { n1874, n1708, n1706, n1982, n1588 }; + assign n2009 = 32'd2290649256 >> { n1874, n1708, n1706, Ni30, n1586 }; + assign n2010 = 32'd2290649256 >> { n1874, n1712, n1711, Ni30, n1587 }; + assign n2011 = 32'd572662434 >> { n1874, n1712, n1711, n1982, n1584 }; + assign n2012 = 32'd2290657416 >> { n1874, n1673, n1676, Ni30, n1586 }; + assign n681 = 4'h2 >> { Ni36, Ni35 }; + assign n2013 = 32'd572695074 >> { n1874, n1673, n1676, n1982, n1588 }; + assign n2014 = 32'd572695074 >> { n1874, n1681, n1683, n1982, n1584 }; + assign n2015 = 16'h88a8 >> { Ni13, Ni12, n2019, n2016 }; + assign n2016 = 32'd143133322 >> { Pi24, n2017, Pi23, n2018, n2780 }; + assign n2017 = 4'h2 >> { n1794, Ni14 }; + assign n2018 = 4'hd >> { Ni14, n1688 }; + assign n2019 = 16'hb111 >> { n1585, n1982, n1925, Ni30 }; + assign n2020 = 16'h5111 >> { n1585, n1982, n2021, n1925 }; + assign n2021 = 32'd2290616456 >> { Ni31, Ni33, n585, Ni30, n582 }; + assign n2022 = 32'd3470778335 >> { n1542, n1746, n1751, n1874, n1547 }; + assign n682 = 64'h0001000100010000 >> { Ni40, Ni44, Ni41, Ni43, Ni45, Ni42 }; + assign n2023 = 4'hd >> { n1749, n2024 }; + assign n2024 = 16'h88a8 >> { n1874, n1722, Ni30, n1553 }; + assign n2025 = 16'h0222 >> { n1982, n597, n624, Ni30 }; + assign n2026 = 32'd707439146 >> { n1875, n1553, n2028, n2027, n746 }; + assign n2027 = 32'd353699093 >> { n1874, n1739, n1552, Ni30, n2025 }; + assign n2028 = 64'hcd05dd05cf05ff05 >> { n1741, n1739, n1982, n1547, n1874, n1542 }; + assign n2029 = 8'ha2 >> { n1693, n621, n2030 }; + assign n2030 = 4'h2 >> { n1981, n1263 }; + assign n2031 = 32'd1162151237 >> { n1874, n1762, n1542, n1982, n2025 }; + assign n2032 = 64'hf351f3515151f351 >> { n1874, n1789, n1982, n1890, n1553, n1547 }; + assign n683 = 4'h1 >> { n682, n665 }; + assign n2033 = 64'h2a222a22aaaa2a22 >> { n1884, n1553, n1552, n1885, n2034, n748 }; + assign n2034 = 64'h1011101100111011 >> { n1874, n1710, n1542, n1982, n2025, n2035 }; + assign n2035 = 32'd572662434 >> { n1874, n1708, n1706, n1982, n1547 }; + assign n2036 = 32'd707439146 >> { n1786, n2038, n2039, n2037, n746 }; + assign n2037 = 64'h00f7f5f700333133 >> { n1982, Ni30, n1552, n1874, n1547, n1691 }; + assign n2038 = 4'h2 >> { n1878, n1553 }; + assign n2039 = 16'h5111 >> { n1702, n1982, n2040, n2025 }; + assign n2040 = 16'h22a2 >> { n1874, n1698, n1982, n1542 }; + assign n2041 = 16'h22a2 >> { n1874, n1672, n1982, n1547 }; + assign n2042 = 64'hf351f3515151f351 >> { n1874, n1680, n1982, n2043, n1552, n1542 }; + assign n684 = 4'hd >> { n682, n686 }; + assign n2043 = 16'h5515 >> { n1874, n1676, n1673, Ni30 }; + assign n2044 = 4'h2 >> { n1895, n1570 }; + assign n2045 = 16'h22a2 >> { n1874, n2002, n1982, n1263 }; + assign n2046 = 64'hcd05dd05cf05ff05 >> { n1770, n1772, n1982, n1542, n1874, n1547 }; + assign n2047 = 32'd2863311522 >> { n2038, n2040, n2025, n2048, n746 }; + assign n2048 = 64'h00f7f5f700333133 >> { n1982, Ni30, n1552, n1874, n1547, n1692 }; + assign n2049 = 64'hcd05dd05cf05ff05 >> { n1724, n1722, n1982, n1542, n1874, n1547 }; + assign n2050 = 64'hfd00fd00ff00fd00 >> { n1917, n1552, n746, n2025, n2051, n2052 }; + assign n2051 = 16'h88a8 >> { n1874, n1737, Ni30, n1553 }; + assign n2052 = 64'hcd05dd05cf05ff05 >> { n1735, n1737, n1982, n1542, n1874, n1547 }; + assign n685 = 16'heefe >> { Ni43, Ni42, Ni45, Ni47 }; + assign n2053 = 16'h88a8 >> { Ni13, Ni12, n2055, n2054 }; + assign n2054 = 32'd2158004392 >> { Pi24, n2017, n2018, Pi23, n2780 }; + assign n2055 = 16'hb111 >> { n597, n1982, n1925, Ni30 }; + assign n2056 = 64'h0202000200020002 >> { n2064, n2065, n759, n2059, n2057, n2061 }; + assign n2057 = 64'h2a222a22aaaa2a22 >> { n1907, n1613, n1609, n1906, n2058, n757 }; + assign n2058 = 64'hcd05dd05cf05ff05 >> { n1731, n1728, n1982, n1607, n1874, n1612 }; + assign n2059 = 64'h2a222a22aaaa2a22 >> { n1909, n1609, n1613, n1878, n2060, n745 }; + assign n2060 = 64'hcd05dd05cf05ff05 >> { n1698, n1692, n1982, n1607, n1874, n1612 }; + assign n2061 = 16'h2220 >> { Pi24, n1910, n2063, n2062 }; + assign n2062 = 32'd3448762287 >> { n793, Pi24, Ni30, n1981, n624 }; + assign n686 = 16'h1101 >> { Ni38, Ni39, Ni35, Ni36 }; + assign n2063 = 16'h22a2 >> { n1874, n2002, n1982, n1623 }; + assign n2064 = 64'hd5dd5555f5ff7577 >> { Ni30, n1982, n1770, n1874, Pi24, n1332 }; + assign n2065 = 64'hd5dd5555f5ff7577 >> { Ni30, n1982, n1772, n1874, Pi24, n750 }; + assign n2066 = 64'hd5dd5555f5ff7577 >> { Ni30, n1982, n1706, n1874, Pi24, n1332 }; + assign n2067 = 64'h2a222a22aaaa2a22 >> { n1921, n1609, n1613, n1920, n2068, n751 }; + assign n2068 = 64'hcd05dd05cf05ff05 >> { n1722, n1724, n1982, n1607, n1874, n1612 }; + assign n2069 = 64'h2a222a22aaaa2a22 >> { n1918, n1613, n1609, n1917, n2070, n756 }; + assign n2070 = 64'hcd05dd05cf05ff05 >> { n1737, n1735, n1982, n1607, n1874, n1612 }; + assign n2071 = 32'd4160223231 >> { n1607, n1612, n1874, n1746, n1751 }; + assign n2072 = 64'hfe00ff00fe00fe00 >> { n1613, n1884, n747, n2075, n2073, n2074 }; + assign n687 = 8'h80 >> { n688, n691, n690 }; + assign n2073 = 32'd572662434 >> { n1874, n1708, n1706, n1982, n1607 }; + assign n2074 = 32'd2290649256 >> { n1874, n1708, n1706, Ni30, n1609 }; + assign n2075 = 32'd572662434 >> { n1874, n1712, n1711, n1982, n1612 }; + assign n2076 = 64'hfe00ff00fe00fe00 >> { n1613, n1875, n756, n2079, n2077, n2078 }; + assign n2077 = 32'd2290649256 >> { n1874, n1740, n1735, Ni30, n1609 }; + assign n2078 = 32'd572662434 >> { n1874, n1740, n1735, n1982, n1607 }; + assign n2079 = 32'd572662434 >> { n1874, n1742, n1737, n1982, n1612 }; + assign n2080 = 32'd2324343434 >> { n1880, n1609, n2082, n2081, n745 }; + assign n2081 = 16'h22a2 >> { n1874, n1691, n1982, n1607 }; + assign n2082 = 64'hd5dd5555f5ff7577 >> { Ni30, n1982, n1936, n1874, Pi24, n750 }; + assign n688 = 8'ha2 >> { n689, Ni38, n617 }; + assign n2083 = 32'd1059010325 >> { n1609, n1613, n2043, n1882, n2084 }; + assign n2084 = 64'hcd05dd05cf05ff05 >> { n1680, n1672, n1982, n1607, n1874, n1612 }; + assign n2085 = 64'ha820f87028207870 >> { n1982, n757, Pi24, n1892, Ni30, n2086 }; + assign n2086 = 64'h1111001101010001 >> { n1890, n1891, n1609, n1613, n2088, n2087 }; + assign n2087 = 32'd572695074 >> { n1874, n1756, n1757, n1982, n1607 }; + assign n2088 = 32'd572695074 >> { n1874, n1759, n1760, n1982, n1612 }; + assign n2089 = 64'h5540555055515551 >> { Ni14, n2762, Ni13, Ni11, Ni12, n2090 }; + assign n2090 = 16'h2022 >> { Ni30, Pi24, n1925, n1982 }; + assign n2091 = 32'd2861206154 >> { n582, n1844, n2111, n2799, n1659 }; + assign n2092 = 32'd1060059946 >> { n643, n623, n1885, n1884, n2093 }; + assign n689 = 64'h0001000100000001 >> { Ni40, Ni44, Ni41, Ni43, Ni45, Ni42 }; + assign n2093 = 16'h1110 >> { n1825, n699, n1895, n1720 }; + assign n2094 = 32'd2829626024 >> { n1888, n643, n2095, n1893, n677 }; + assign n2095 = 16'h0008 >> { n1874, n1749, n1722, n623 }; + assign n2096 = 16'hdddf >> { n699, n643, n1874, n1724 }; + assign n2097 = 64'haaaaaaaaaaaaaaa8 >> { n2108, n2098, Pi17, n2102, n2104, n583 }; + assign n2098 = 32'd4278189822 >> { n643, n2043, n2101, n2100, n2099 }; + assign n2099 = 32'd2290649256 >> { n1874, n1696, n1692, Ni30, n638 }; + assign n2100 = 32'd1145328708 >> { n1874, n1683, n1681, Ni30, n1818 }; + assign n2101 = 32'd538976800 >> { n1874, n1698, Ni30, n1786, n632 }; + assign n2102 = 64'h2a222a22aaaa2a22 >> { n1878, n632, n623, n1902, n2103, n659 }; + assign n690 = 8'hae >> { n664, n689, n665 }; + assign n2103 = 64'h0cae0cee0caf0cff >> { n1770, n1692, Ni30, n638, n1810, n1874 }; + assign n2104 = 64'hfe00ff00fe00fe00 >> { n623, n1890, n677, n2107, n2106, n2105 }; + assign n2105 = 32'd2290649256 >> { n1874, n1740, n1735, Ni30, n638 }; + assign n2106 = 32'd2290649256 >> { n1874, n1742, n1737, Ni30, n632 }; + assign n2107 = 32'd1145328708 >> { n1874, n1757, n1756, Ni30, n1810 }; + assign n2108 = 32'd2728567466 >> { n1906, n1810, n2110, n2109, n645 }; + assign n2109 = 64'h05cd05dd05cf05ff >> { n1737, n1731, Ni30, n623, n1874, n632 }; + assign n2110 = 16'h88a8 >> { n1874, n1735, Ni30, n638 }; + assign n2111 = 16'haa2a >> { n2762, n624, Ni11, n2112 }; + assign n2112 = 64'h88dd80d5085d0055 >> { n1794, n2018, n1925, n1344, n1468, Ni30 }; + assign n691 = 8'h51 >> { n689, n692, n685 }; + assign n2113 = 8'ha2 >> { n2055, n1238, n2114 }; + assign n2114 = 32'd14013909 >> { n582, n1925, n1982, n597, n2021 }; + assign n2115 = 16'h1151 >> { n1871, n1898, n583, n1922 }; + assign n2116 = 16'haaa8 >> { n2799, Ni30, n1925, n1666 }; + assign n1031 = 32'd1329885030 >> { n2118, n716, P__cmxig_1, Ni14, P__cmxcl_0 }; + assign n2118 = 16'h1011 >> { Ni12, n1296, Ni11, Ni13 }; + assign n1036_1 = 16'h2a6a >> { n2120, P__cmxcl_0, Ni14, Ni13 }; + assign n2120 = 32'd1112752209 >> { Pi26, P__cmxig_1, Pi27, Ni12, Ni11 }; + assign n1056 = 16'h2a6a >> { n2122, P__cmxcl_0, Ni10, Ni9 }; + assign n2122 = 32'd1112752209 >> { Pi23, P__cmxig_0, Pi24, Ni8, Ni7 }; + assign n692 = 16'h1110 >> { Ni38, Ni39, Ni35, Ni36 }; + assign n1061_1 = 32'd304261802 >> { P__cmxcl_0, Ni10, Ni9, n593, Ni8 }; + assign n2124 = 8'h15 >> { Ni13, Ni14, Ni12 }; + assign n2125 = 32'd143165576 >> { Ni33, n585, n582, n602, P__cmxcl_0 }; + assign n2126 = 64'hfdfff8d8fdfef8f8 >> { Pi23, Ni8, Pi24, Ni7, Ni9, Ni10 }; + assign n2127 = 32'd33720834 >> { Ni11, n2124, n2128, n612, Ni6 }; + assign n2128 = 32'd2863179944 >> { Ni10, Ni9, Ni8, Ni7, n602 }; + assign n2129 = 32'd858919184 >> { Ni31, Ni6, n2130, Ni2, Ni3 }; + assign n2130 = 32'd570556930 >> { n2809, n2138, n1641, n2137, n2131 }; + assign n2131 = 64'h80d5005588dd085d >> { Pi23, n2136, n2135, n2133, n2132, n1660 }; + assign n2132 = 32'd2290649336 >> { Ni33, Pi24, n602, n2133, n2809 }; + assign n693 = 8'h8a >> { Ni36, n649, n694 }; + assign n2133 = 4'h8 >> { n612, n2134 }; + assign n2134 = 16'h0604 >> { Ni14, Ni13, Ni12, Ni11 }; + assign n2135 = 32'd16318715 >> { Ni10, n2136, Ni9, Ni8, Ni7 }; + assign n2136 = 64'h8000080080000080 >> { Pi26, Pi27, Ni14, Ni12, n612, n2134 }; + assign n2137 = 32'd2326399530 >> { n581, Pi23, n2132, n2133, n595 }; + assign n2138 = 32'd1162151237 >> { Pi27, Ni33, n1344, n602, n2139 }; + assign n2139 = 32'd353699093 >> { Ni33, n602, Pi24, n2134, n2136 }; + assign n2140 = 4'h8 >> { n2127, P__cmxcl_0 }; + assign n956 = 32'd1313737294 >> { Ni42, n2142, Ni31, Ni43, n1201 }; + assign n2142 = 64'h00aa40ea04ae44ee >> { Pi19, Pi17, Pi16, Ni40, n2143, Ni41 }; + assign n694 = 8'h8a >> { Ni38, n649, n617 }; + assign n2143 = 4'h9 >> { Pi20, Ni44 }; + assign n946 = 64'hfd00fdfdff00fffd >> { n588, Pi21, Ni45, Ni30, Ni32, Ni31 }; + assign n936_1 = 32'd1886908663 >> { n588, Pi22, Ni47, n599, Ni31 }; + assign n2146 = 64'h0002020200222222 >> { n2200, n2201, n973, n948, n2147, n2186 }; + assign n2147 = 16'haaa2 >> { n2172, n2182, n2148, n756 }; + assign n2148 = 8'h02 >> { n2149, n2160, n2171 }; + assign n2149 = 16'h0213 >> { n2817, n2814, Pi21, Pi20 }; + assign n2150 = 16'h0002 >> { Ni47, Ni43, Ni42, Ni38 }; + assign n2151 = 64'h0a3bffff0a08ffff >> { n2152, n665, Ni39, n635, Ni38, n2153 }; + assign n2152 = 8'h45 >> { Ni42, Ni43, Ni47 }; + assign n695 = 8'h01 >> { Ni41, Ni44, Ni40 }; + assign n2153 = 8'h01 >> { Ni47, Ni43, Ni42 }; + assign n2154 = 4'h1 >> { Ni32, Ni35 }; + assign n2155 = 32'd16777473 >> { Ni42, Ni43, Ni47, Ni37, Ni38 }; + assign n2156 = 4'h2 >> { Ni32, Ni36 }; + assign n2157 = 4'h2 >> { Ni32, Ni35 }; + assign n2158 = 8'h8a >> { n2153, n628, n2159 }; + assign n2159 = 8'h51 >> { Ni38, Ni39, Ni36 }; + assign n2160 = 16'h0123 >> { n2820, n2819, Pi22, Pi20 }; + assign n2161 = 8'hae >> { Ni43, Ni42, Ni45 }; + assign n2162 = 32'd1141137167 >> { n2159, n2164, Ni37, n2163, n628 }; + assign n696 = 16'h22a2 >> { n695, n619, Ni38, n617 }; + assign n2163 = 8'h01 >> { Ni43, Ni45, Ni42 }; + assign n2164 = 16'h0002 >> { Ni43, Ni45, Ni42, Ni38 }; + assign n2165 = 32'd16777473 >> { Ni42, Ni43, Ni45, Ni37, Ni38 }; + assign n2166 = 4'h8 >> { Ni32, Ni36 }; + assign n2167 = 4'h8 >> { Ni32, Ni35 }; + assign n2168 = 8'ha2 >> { n635, n2163, n2169 }; + assign n2169 = 8'h54 >> { Ni38, Ni39, Ni36 }; + assign n2170 = 16'h2022 >> { n2164, n635, n2165, Ni32 }; + assign n2171 = 64'hf0f0f8f000000080 >> { Pi21, Ni30, Ni32, Pi22, Ni31, n18 }; + assign n2172 = 4'h2 >> { n2173, n1332 }; + assign n697 = 16'h1151 >> { n695, n619, n686, n685 }; + assign n2173 = 64'h0202000200020002 >> { n2820, n2814, n2181, n2176, n2174, n2178 }; + assign n2174 = 16'h2aaa >> { n636, n634, n676, n2175 }; + assign n2175 = 8'h02 >> { Ni30, Ni31, n18 }; + assign n2176 = 8'ha2 >> { n635, n619, n2177 }; + assign n2177 = 8'h08 >> { Ni32, Ni30, n18 }; + assign n2178 = 16'h5ddd >> { Ni39, Ni35, n2180, n2179 }; + assign n2179 = 8'h80 >> { n18, Ni30, Ni32 }; + assign n2180 = 32'd1 >> { Ni36, Ni47, Ni37, Ni45, Ni38 }; + assign n2181 = 8'h08 >> { Ni30, n18, Ni31 }; + assign n2182 = 4'h2 >> { n2183, n750 }; + assign n698 = 16'hdd5d >> { n619, Ni36, n700, Ni34 }; + assign n2183 = 64'h80800080aaaa00aa >> { n2181, n673, n2175, n2819, n2817, n2184 }; + assign n2184 = 8'h8a >> { n2177, n674, n2185 }; + assign n2185 = 16'hdd5d >> { Ni39, Ni35, n2180, n2179 }; + assign n2186 = 64'h2222002202020002 >> { n2187, n2195, n798, n1133, Pi15, n18 }; + assign n2187 = 64'h1111001101010001 >> { n693, n649, n2177, n2175, n2188, n2194 }; + assign n2188 = 8'h2a >> { n2191, n2189, n2181 }; + assign n2189 = 32'd3452820941 >> { Ni41, n2153, Ni36, Ni32, n2190 }; + assign n2190 = 64'hffffeefefffdeefc >> { Ni41, Ni37, Ni43, Ni42, Ni47, Ni38 }; + assign n2191 = 16'h0ddd >> { n2193, Ni32, n2192, n2166 }; + assign n2192 = 16'h0001 >> { Ni41, Ni43, Ni45, Ni42 }; + assign n699 = 4'h8 >> { n624, Pi19 }; + assign n2193 = 64'hffffeefefffdeefc >> { Ni41, Ni37, Ni43, Ni42, Ni45, Ni38 }; + assign n2194 = 4'h2 >> { n2180, n2179 }; + assign n2195 = 64'h0001000101010001 >> { n2198, n2197, n2181, n2194, n2199, n2196 }; + assign n2196 = 4'h2 >> { n619, n2177 }; + assign n2197 = 32'd4211010286 >> { Ni38, Ni36, n2153, n2155, Ni32 }; + assign n2198 = 32'd167914018 >> { Ni38, Ni36, n2163, n2165, Ni32 }; + assign n2199 = 16'h22a2 >> { n619, Ni36, n701, n2175 }; + assign n2200 = 64'h222a222a222aaaaa >> { n2191, Pi22, n2189, Pi21, n2171, Pi19 }; + assign n2201 = 32'd2324335274 >> { n2197, Pi21, n2171, n2202, Pi19 }; + assign n2202 = 32'd84153621 >> { n2165, Ni36, n2163, Ni38, Pi22 }; + assign n700 = 64'h3b3b3b3bbb3b3b3b >> { P__cmxig_1, n701, n622, Pi19, Ni34, n624 }; + assign n2203 = 64'h2a222a22aaaa2a22 >> { n2225, n750, n1332, n2222, n2204, n757 }; + assign n2204 = 8'h02 >> { n2205, n2214, n2171 }; + assign n2205 = 32'd573775921 >> { n2213, n2209, n2206, Pi21, Pi20 }; + assign n2206 = 8'h51 >> { n2208, n2207, Ni32 }; + assign n2207 = 8'hae >> { Ni37, n2152, Ni38 }; + assign n2208 = 16'h1151 >> { Ni41, Ni44, n2153, n641 }; + assign n2209 = 16'h4454 >> { n2211, n2210, Ni32, n2212 }; + assign n2210 = 8'hae >> { Ni37, n2152, Ni38 }; + assign n2211 = 16'h1115 >> { Ni41, Ni44, n2153, n618 }; + assign n2212 = 32'd33686050 >> { Ni41, Ni44, n2153, Ni32, n621 }; + assign n701 = 64'h0000000201010003 >> { Ni37, Ni43, Ni42, Ni45, Ni47, Ni38 }; + assign n2213 = 32'd33694210 >> { Ni41, Ni44, n2153, Ni32, n621 }; + assign n2214 = 32'd288559154 >> { n2221, n2217, n2215, Pi22, Pi20 }; + assign n2215 = 64'h0a2a0a2a0a2a2a2a >> { Ni41, Ni44, n2163, n2216, n618, Ni32 }; + assign n2216 = 4'h1 >> { n2161, n664 }; + assign n2217 = 16'h1151 >> { n2219, n2218, Ni32, n2220 }; + assign n2218 = 4'h1 >> { n2161, n664 }; + assign n2219 = 16'h1151 >> { Ni41, Ni44, n2163, n641 }; + assign n2220 = 16'h22a2 >> { Ni41, Ni44, n2163, n2166 }; + assign n2221 = 16'h222a >> { Ni41, Ni44, n2163, n2166 }; + assign n2222 = 64'h0202020202022202 >> { n2213, n2206, n2217, n2181, n2224, n2223 }; + assign n702 = 8'h80 >> { n703, n706, n705 }; + assign n2223 = 64'hf351f3515151f351 >> { Ni41, Ni44, n619, n640, n2175, n2177 }; + assign n2224 = 8'ha2 >> { Ni39, n2180, n2179 }; + assign n2225 = 32'd572662434 >> { n2221, n2215, n2209, n2181, n2226 }; + assign n2226 = 16'h1011 >> { n2175, n620, n2228, n2227 }; + assign n2227 = 16'h222a >> { Ni41, Ni44, n619, n2177 }; + assign n2228 = 8'h2a >> { Ni39, n2180, n2179 }; + assign n2229 = 64'h2a222a22aaaa2a22 >> { n2246, n750, n1332, n2241, n2230, n751 }; + assign n2230 = 8'h02 >> { n2231, n2237, n2171 }; + assign n2231 = 16'h0213 >> { n2822, n2232, Pi21, Pi20 }; + assign n2232 = 16'h2031 >> { n2154, n2235, n2234, n2233 }; + assign n703 = 16'h22a2 >> { n704, n619, Ni38, n617 }; + assign n2233 = 64'h0a3bffff0a08ffff >> { n2152, n665, Ni39, n704, Ni38, n2153 }; + assign n2234 = 16'h2301 >> { n704, n2155, Ni32, n2150 }; + assign n2235 = 8'h5d >> { n704, n2153, n2156 }; + assign n2236 = 32'd1141137167 >> { n2159, n2150, Ni37, n2153, n695 }; + assign n2237 = 16'h0213 >> { n2826, n2824, Pi22, Pi20 }; + assign n2238 = 32'd1141137167 >> { Ni37, n2163, n2169, n2164, n704 }; + assign n2239 = 4'h2 >> { Ni35, Ni32 }; + assign n2240 = 32'd1141137167 >> { n2159, n2164, Ni37, n2163, n695 }; + assign n2241 = 64'h0202000200020002 >> { n2232, n2824, n2181, n2244, n2242, n2245 }; + assign n2242 = 4'h2 >> { n2243, n2177 }; + assign n704 = 8'h02 >> { Ni41, Ni40, Ni44 }; + assign n2243 = 4'h2 >> { n704, n619 }; + assign n2244 = 16'h2aaa >> { n705, n703, n706, n2175 }; + assign n2245 = 16'hdd5d >> { Ni35, Ni39, n2180, n2179 }; + assign n2246 = 64'h80800080aaaa00aa >> { n2181, n2562, n2175, n2822, n2826, n2247 }; + assign n2247 = 4'h2 >> { n2248, n2249 }; + assign n2248 = 8'ha2 >> { n695, n619, n2177 }; + assign n2249 = 16'hddd5 >> { Ni39, Ni35, n2180, n2179 }; + assign n2250 = 64'h0002000000020002 >> { n1332, n2263, n2251, n2265, n2257, n2171 }; + assign n2251 = 64'h3331333133312220 >> { n2254, n2256, n2255, n2252, Pi21, Pi20 }; + assign n2252 = 8'h51 >> { n2253, n2207, Ni32 }; + assign n705 = 16'h4454 >> { n704, n619, n665, n664 }; + assign n2253 = 16'h5551 >> { Ni41, Ni44, n2153, n641 }; + assign n2254 = 64'h1313131311131313 >> { Ni41, n2153, Ni44, n618, Ni32, n2210 }; + assign n2255 = 32'd572662274 >> { Ni44, Ni41, n2153, Ni32, n621 }; + assign n2256 = 32'd570565154 >> { Ni44, Ni41, n2153, Ni32, n621 }; + assign n2257 = 32'd573775921 >> { n2262, n2259, n2258, Pi22, Pi20 }; + assign n2258 = 32'd707398186 >> { Ni44, n2192, n2218, n641, Ni32 }; + assign n2259 = 16'h1151 >> { n2260, n2216, Ni32, n2261 }; + assign n2260 = 8'h15 >> { Ni44, n2192, n618 }; + assign n2261 = 8'h2a >> { Ni44, n2192, n2166 }; + assign n2262 = 8'ha2 >> { Ni44, n2192, n2166 }; + assign n706 = 16'h1151 >> { n704, n619, n692, n685 }; + assign n2263 = 64'h222222222222222a >> { n2255, n2258, n2252, n2262, n2181, n2264 }; + assign n2264 = 64'h0404000455550055 >> { n2177, n648, n2175, Ni44, n649, n2224 }; + assign n2265 = 64'hc4c4c4c4c4c444c4 >> { n2254, n2256, n2259, n2181, n750, n2266 }; + assign n2266 = 64'h4040004055550055 >> { n2177, n671, n2175, n649, Ni44, n2228 }; + assign n2267 = 64'h2a222a22aaaa2a22 >> { n2286, n1332, n750, n2283, n2828, n747 }; + assign n2268 = 8'h8a >> { n2239, n2269, n2270 }; + assign n2269 = 64'hdd55dd558c04cc54 >> { Ni36, n2161, Ni38, Ni39, n682, Ni37 }; + assign n2270 = 32'd3721788917 >> { n2166, Ni38, n2165, n682, Ni32 }; + assign n2271 = 8'h2a >> { n2272, n2239, n2273 }; + assign n2272 = 4'h2 >> { n689, n2169 }; + assign n707 = 64'h2a2a2a2aaa2a2a2a >> { P__cmxig_1, n708, n622, Ni34, n623, n709 }; + assign n2273 = 32'd3721788917 >> { n2166, Ni38, n2165, n689, Ni32 }; + assign n2274 = 16'haaa2 >> { n2275, n2277, n2152, n2154 }; + assign n2275 = 16'h222a >> { Ni44, Ni40, n2276, Ni37 }; + assign n2276 = 32'd2 >> { Ni41, Ni47, Ni43, Ni42, Ni38 }; + assign n2277 = 32'd2728567466 >> { Ni44, Ni40, Ni41, n2153, n2159 }; + assign n2278 = 16'h2022 >> { n2154, n2279, n2281, n2282 }; + assign n2279 = 64'hf555f501f555f400 >> { n2152, Ni36, n2280, Ni38, Ni39, Ni37 }; + assign n2280 = 64'h0001000100000001 >> { Ni40, Ni44, Ni41, Ni47, Ni43, Ni42 }; + assign n2281 = 16'h0123 >> { n2280, n2155, Ni32, Ni38 }; + assign n2282 = 32'd791613231 >> { Ni40, Ni44, n2156, Ni41, n2153 }; + assign n708 = 16'h88a8 >> { Ni38, n684, n682, n617 }; + assign n2283 = 32'd572695074 >> { n2274, n2830, n2268, n2181, n2284 }; + assign n2284 = 64'h0202020202022202 >> { n683, n680, n684, n2175, n2285, n2249 }; + assign n2285 = 8'ha2 >> { Ni47, n682, n2177 }; + assign n2286 = 64'h0202000200020002 >> { n2278, n2271, n2181, n2288, n2287, n2245 }; + assign n2287 = 16'h2aaa >> { n690, n688, n691, n2175 }; + assign n2288 = 8'ha2 >> { Ni47, n689, n2177 }; + assign n2289 = 4'h2 >> { n2290, n2300 }; + assign n2290 = 32'd539111731 >> { n2296, n2294, n2291, Pi21, Pi20 }; + assign n2291 = 16'haaa2 >> { n2292, n2293, n2152, n2157 }; + assign n2292 = 4'h2 >> { n2276, Ni37 }; + assign n709 = 64'h3b3b3b3bbb3b3b3b >> { P__cmxig_1, n622, n694, Pi19, Ni34, n624 }; + assign n2293 = 32'd2862785186 >> { Ni44, Ni40, Ni41, n2153, n2169 }; + assign n2294 = 32'd4092769186 >> { Ni38, Ni32, n2295, n2156, n2155 }; + assign n2295 = 16'h0222 >> { Ni40, Ni44, Ni41, n2153 }; + assign n2296 = 32'd3423128845 >> { n2299, n2298, n2156, n2297, n2157 }; + assign n2297 = 64'hf555f504f555f100 >> { n2152, Ni36, n2298, Ni38, Ni39, Ni37 }; + assign n2298 = 64'h0001000000010001 >> { Ni40, Ni44, Ni41, Ni47, Ni43, Ni42 }; + assign n2299 = 16'h028a >> { n2298, n2155, Ni38, n2154 }; + assign n2300 = 32'd2862786720 >> { n2304, n2301, Pi22, Pi20, n2171 }; + assign n2301 = 8'h8a >> { n2167, n2302, n2303 }; + assign n2302 = 64'hd5d5d5d5c480c4c5 >> { Ni36, n2161, Ni39, Ni38, n653, Ni37 }; + assign n710 = 4'h8 >> { n711, n622 }; + assign n2303 = 32'd3721788917 >> { n2166, Ni38, n2165, n653, Ni32 }; + assign n2304 = 8'h8a >> { n2167, n2305, n2306 }; + assign n2305 = 64'hdd55dd558c04cc54 >> { Ni36, n2161, Ni38, Ni39, n656, Ni37 }; + assign n2306 = 32'd3721788917 >> { n2166, Ni38, n2165, n656, Ni32 }; + assign n2307 = 64'hc4c4c4c444c4c4c4 >> { n2291, n2294, n2301, n2181, n1332, n2308 }; + assign n2308 = 64'h0202020202022202 >> { n663, n661, n654, n2175, n2309, n2178 }; + assign n2309 = 8'ha2 >> { Ni47, n653, n2177 }; + assign n2310 = 32'd176851594 >> { n2296, n2304, n2311, n2181, n750 }; + assign n2311 = 64'h0202020222020202 >> { n668, n669, n657, n2175, n2312, n2185 }; + assign n2312 = 8'ha2 >> { Ni47, n656, n2177 }; + assign n711 = 4'h8 >> { n688, n691 }; + assign n2313 = 32'd572662434 >> { n2322, n2323, n2324, n1332, n2314 }; + assign n2314 = 8'h02 >> { n2315, n2318, n2171 }; + assign n2315 = 32'd320017154 >> { n2317, n2254, n2316, Pi21, Pi20 }; + assign n2316 = 32'd4042455290 >> { Ni38, n2253, Ni32, n2255, n2207 }; + assign n2317 = 4'h8 >> { n2256, Ni38 }; + assign n2318 = 16'h0213 >> { n2321, n2319, Pi22, Pi20 }; + assign n2319 = 32'd254750511 >> { n2262, Ni38, Ni32, n2320, n2218 }; + assign n2320 = 8'h51 >> { Ni44, n2192, n641 }; + assign n2321 = 32'd521092911 >> { n2261, n2216, Ni32, n2260, Ni38 }; + assign n2322 = 8'h2a >> { n2316, n2319, n2181 }; + assign n712 = 32'd2282260616 >> { n622, P__cmxig_1, n713, n623, Ni34 }; + assign n2323 = 4'h8 >> { n647, n2175 }; + assign n2324 = 16'h1151 >> { Ni44, n649, n2177, n2325 }; + assign n2325 = 8'ha2 >> { n2327, n2326, n2179 }; + assign n2326 = 16'h0001 >> { Ni47, Ni37, Ni45, Ni38 }; + assign n2327 = 4'h2 >> { Ni36, Ni39 }; + assign n2328 = 4'h2 >> { n2329, n750 }; + assign n2329 = 32'd1145324772 >> { n2317, n2254, n2321, n2330, n2181 }; + assign n2330 = 64'h0040404000555555 >> { n2177, n658, n2175, n649, Ni44, n2331 }; + assign n2331 = 8'ha2 >> { n2332, n2326, n2179 }; + assign n2332 = 4'h1 >> { Ni39, Ni36 }; + assign n713 = 4'h8 >> { n696, n697 }; + assign n2333 = 32'd1157973317 >> { n1332, n2361, n756, n2350, n2334 }; + assign n2334 = 64'h2a222a22aaaa2a22 >> { n2347, n1332, n750, n2344, n2335, n745 }; + assign n2335 = 32'd2863178400 >> { n2342, n2341, Pi21, Pi20, n2336 }; + assign n2336 = 32'd2863178400 >> { n2339, n2337, Pi22, Pi20, n2171 }; + assign n2337 = 16'h7757 >> { n2305, Ni35, n2338, Ni32 }; + assign n2338 = 8'h15 >> { Ni38, n656, n2165 }; + assign n2339 = 8'h45 >> { n2167, n2302, n2340 }; + assign n2340 = 32'd353703168 >> { n2239, n2166, n653, Ni38, n2165 }; + assign n2341 = 32'd3486420874 >> { n2298, Ni32, n2157, n2297, n2155 }; + assign n2342 = 8'h15 >> { n2293, n2157, n2343 }; + assign n714 = 32'd2282260616 >> { n622, P__cmxig_1, n715, n643, Ni34 }; + assign n2343 = 32'd587268353 >> { Ni44, Ni40, n2155, Ni32, n2276 }; + assign n2344 = 64'h0202000200020002 >> { n2337, n2341, n2181, n2312, n2345, n2346 }; + assign n2345 = 32'd707439146 >> { n656, Ni38, n617, n657, n2175 }; + assign n2346 = 16'h5ddd >> { n2332, Ni35, n2326, n2179 }; + assign n2347 = 16'ha222 >> { n2342, n2339, n2181, n2348 }; + assign n2348 = 32'd570556930 >> { n654, n652, n2175, n2309, n2349 }; + assign n2349 = 16'h5ddd >> { n2327, Ni35, n2326, n2179 }; + assign n2350 = 16'h2022 >> { n750, n2359, n2351, n2354 }; + assign n2351 = 16'h0123 >> { n2833, n2352, Pi21, Pi20 }; + assign n2352 = 16'h5713 >> { Ni32, n2158, n2353, n2157 }; + assign n715 = 4'h8 >> { n703, n706 }; + assign n2353 = 8'h45 >> { n2150, n628, n2155 }; + assign n2354 = 32'd2862786720 >> { n2357, n2355, Pi22, Pi20, n2171 }; + assign n2355 = 32'd286331157 >> { n2168, n664, n2161, n2167, n2356 }; + assign n2356 = 32'd1162167552 >> { n2166, n2239, n2164, n635, n2165 }; + assign n2357 = 16'h7757 >> { n2162, Ni35, n2358, Ni32 }; + assign n2358 = 8'h45 >> { n2164, n628, n2165 }; + assign n2359 = 64'h80800080aaaa00aa >> { n2181, n626, n2175, n2357, n2352, n2360 }; + assign n2360 = 8'h8a >> { n2177, n674, n2346 }; + assign n2361 = 16'ha222 >> { n2833, n2355, n2181, n2362 }; + assign n2362 = 16'h2022 >> { n2175, n633, n2176, n2349 }; + assign n716 = 4'h8 >> { n572, n584 }; + assign n2363 = 64'h2a222a22aaaa2a22 >> { n2376, n750, n1332, n2372, n2364, n751 }; + assign n2364 = 64'h2222220222202200 >> { n2370, n2834, Pi21, Pi20, n2365, n2171 }; + assign n2365 = 16'h0213 >> { n2368, n2366, Pi22, Pi20 }; + assign n2366 = 16'h7775 >> { n2238, Ni35, n2367, Ni32 }; + assign n2367 = 8'h45 >> { n2164, n704, n2165 }; + assign n2368 = 16'h7775 >> { n2240, Ni35, n2369, Ni32 }; + assign n2369 = 8'h45 >> { n2164, n695, n2165 }; + assign n2370 = 16'hbbba >> { n2236, Ni35, n2371, Ni32 }; + assign n2371 = 8'h45 >> { n2150, n695, n2155 }; + assign n2372 = 32'd570556930 >> { n2834, n2366, n2181, n2373, n2374 }; + assign n717 = 4'h8 >> { n718, P__cmxcl_0 }; + assign n2373 = 8'h2a >> { n706, n703, n2175 }; + assign n2374 = 8'h8a >> { n2177, n2243, n2375 }; + assign n2375 = 16'hdd5d >> { Ni35, n2327, n2326, n2179 }; + assign n2376 = 64'h0202000200020002 >> { n2370, n2368, n2181, n2248, n2377, n2378 }; + assign n2377 = 8'h2a >> { n697, n696, n2175 }; + assign n2378 = 16'hdd5d >> { Ni35, n2332, n2326, n2179 }; + assign n2379 = 32'd1145324772 >> { n2383, n2380, n2388, n2384, Pi20 }; + assign n2380 = 8'h2a >> { n2382, n2381, n2181 }; + assign n2381 = 32'd254750511 >> { n2220, Ni38, Ni32, n2219, n2218 }; + assign n2382 = 32'd4042455290 >> { Ni38, n2208, Ni32, n2213, n2207 }; + assign n718 = 4'h2 >> { Ni8, n594 }; + assign n2383 = 4'h8 >> { n719, n2175 }; + assign n2384 = 32'd1145324772 >> { n2385, n2215, n2386, n2387, n2181 }; + assign n2385 = 4'h8 >> { n2221, Ni38 }; + assign n2386 = 32'd4042455290 >> { Ni38, n2211, Ni32, n2212, n2210 }; + assign n2387 = 32'd286265617 >> { n2175, n620, n616, n2331, n2227 }; + assign n2388 = 32'd1157973317 >> { Ni44, Ni41, n2177, n619, n2325 }; + assign n2389 = 64'ha8a8a8a8a8a8a800 >> { Pi21, n2391, n2392, n2390, Pi22, n2171 }; + assign n2390 = 16'h888d >> { n2385, n2215, n2381, Pi20 }; + assign n2391 = 4'h8 >> { n2382, Pi20 }; + assign n2392 = 4'h2 >> { Pi20, n2386 }; + assign n719 = 4'h1 >> { n640, n642 }; + assign n2393 = 32'd2282227720 >> { n2394, n2396, n793, n18, Pi15 }; + assign n2394 = 64'ha2a2a2a2a2a2a200 >> { Pi21, n2155, n2150, Pi22, n2395, n2171 }; + assign n2395 = 4'h1 >> { n2164, n2165 }; + assign n2396 = 64'h0002020202020202 >> { Ni31, n599, n2395, n2397, n2196, n2398 }; + assign n2397 = 4'h2 >> { n2326, n2179 }; + assign n2398 = 64'hdddddddddddddd0d >> { n2155, Ni32, n2150, n2181, n701, n2175 }; + assign n2399 = 64'h2222002202020002 >> { n694, n649, n2177, n2175, n2397, n2400 }; + assign n2400 = 64'hf5fdf7fff7fff7ff >> { n2190, n18, n2193, Ni30, Ni32, Ni31 }; + assign n2401 = 32'd2324299914 >> { Pi22, n2193, n2190, Pi21, n2171 }; + assign n2402 = 32'd2862786720 >> { n2410, n2408, Pi21, Pi20, n2403 }; + assign n720 = 4'h8 >> { n622, n18 }; + assign n2403 = 32'd2862786720 >> { n2406, n2404, Pi22, Pi20, n2171 }; + assign n2404 = 32'd286331157 >> { n2272, n664, n2161, n2239, n2405 }; + assign n2405 = 32'd353703168 >> { n2166, n2167, n689, Ni38, n2165 }; + assign n2406 = 8'h45 >> { n2239, n2269, n2407 }; + assign n2407 = 32'd353703168 >> { n2166, n2167, n682, Ni38, n2165 }; + assign n2408 = 16'hbbab >> { n2279, n2154, n2409, Ni32 }; + assign n2409 = 8'h15 >> { Ni38, n2280, n2155 }; + assign n2410 = 8'h15 >> { n2277, n2154, n2411 }; + assign n2411 = 32'd16843043 >> { Ni44, Ni40, n2155, Ni32, n2276 }; + assign n2412 = 64'h0202000200020002 >> { n2404, n2408, n2181, n2288, n2413, n2375 }; + assign n721 = 16'h0080 >> { Ni34, n622, P__cmxig_0, Pi25 }; + assign n2413 = 8'h2a >> { n691, n688, n2175 }; + assign n2414 = 64'h80800080aaaa00aa >> { n2181, n708, n2175, n2406, n2410, n2415 }; + assign n2415 = 4'h2 >> { n2285, n2378 }; + assign n2416 = 16'h22f2 >> { n2286, n1332, n2283, n750 }; + assign n2417 = 64'h0202000200020002 >> { n2422, n2250, n758, n2418, n2420, n2421 }; + assign n2418 = 64'haaaaaaaaaaaaaa2a >> { n2307, n2310, n2290, n2419, n2300, n746 }; + assign n2419 = 32'd4210227440 >> { n667, n660, n18, Pi20, n622 }; + assign n2420 = 16'h0222 >> { n622, n693, n18, n755 }; + assign n2421 = 16'h8a02 >> { Pi25, n2200, n769, n2187 }; + assign n2422 = 64'hffddfddddfdddddd >> { n648, n671, n622, Pi20, n18, n754 }; + assign n722 = 64'h5555595d595d595d >> { Ni33, n18, Pi25, n615, n622, Ni34 }; + assign n2423 = 64'hff00fd00fd00fd00 >> { n752, n2426, n746, n2425, n2424, n2335 }; + assign n2424 = 16'h22f2 >> { n2347, n1332, n2344, n750 }; + assign n2425 = 16'h0222 >> { n622, n655, n18, n749 }; + assign n2426 = 16'h1555 >> { n652, n654, n622, n18 }; + assign n2427 = 64'hf700ff00f700f700 >> { n1476, n2414, n748, n2428, n2429, n2402 }; + assign n2428 = 32'd170535466 >> { n622, n708, n2414, n18, n749 }; + assign n2429 = 32'd3452816709 >> { n710, n18, n1477, n2412, n752 }; + assign n2430 = 64'h0202000200020002 >> { n2834, n2366, n2181, n2431, n2373, n2374 }; + assign n2431 = 16'h1555 >> { n703, n706, n622, n18 }; + assign n2432 = 32'd2863311402 >> { n2433, n2434, n2389, n2379, n758 }; + assign n723 = 16'haaa8 >> { Ni34, n620, n616, Ni33 }; + assign n2433 = 16'h222a >> { n614, n18, n2384, n749 }; + assign n2434 = 64'hfd00fd00fd00ff00 >> { n18, n753, n752, n2380, n2383, n2388 }; + assign n2435 = 8'h15 >> { n622, n633, n18 }; + assign n2436 = 16'h0222 >> { n622, n626, n18, n749 }; + assign n2437 = 16'ha888 >> { n622, n701, n18, n2396 }; + assign n2438 = 32'd3014898449 >> { n18, Pi25, n2396, n776, n2394 }; + assign n2439 = 32'd2863311402 >> { n2172, n2182, n2440, n2148, n746 }; + assign n2440 = 64'hffddfddddfdddddd >> { n675, n673, n622, Pi20, n18, n754 }; + assign n2441 = 64'hf700ff00f700f700 >> { n1476, n2225, n758, n2443, n2442, n2204 }; + assign n2442 = 32'd4292203989 >> { n640, n622, n18, n2222, n1332 }; + assign n724 = 4'h2 >> { n624, Ni34 }; + assign n2443 = 32'd170535466 >> { n622, n620, n2225, n18, n749 }; + assign n2444 = 64'hf500f700fd00ff00 >> { n2394, n2364, n645, n2445, Pi19, n2446 }; + assign n2445 = 32'd170535466 >> { n622, n713, n2376, n18, n623 }; + assign n2446 = 16'hdd0d >> { n2437, n699, n2430, n643 }; + assign n2447 = 16'h5551 >> { n2237, n2231, n2171, Pi19 }; + assign n2448 = 32'd170535466 >> { n622, n702, n2241, n18, n643 }; + assign n2449 = 32'd1162167557 >> { n18, n678, n623, n2283, n2200 }; + assign n2450 = 64'h5555555555555554 >> { n2472, n2451, Pi17, n2457, n2463, n2478 }; + assign n2451 = 64'haaaaaaaaaaaaaaa2 >> { n2455, n2456, n2453, n2454, n2452, n645 }; + assign n2452 = 64'h2022202220220022 >> { n18, n614, n623, n2384, n2351, n2354 }; + assign n725 = 16'h22a2 >> { n726, Pi25, n729, n643 }; + assign n2453 = 64'hfd00fd00fd00ff00 >> { n18, n753, n643, n2380, n2383, n2388 }; + assign n2454 = 64'h0101010101010155 >> { n2391, Pi21, n2392, Pi22, n2390, Pi19 }; + assign n2455 = 64'hd0d0f0d0f0d0f0d0 >> { n2833, n2355, n2181, n638, n2435, n2362 }; + assign n2456 = 32'd170535466 >> { n622, n626, n2359, n18, n632 }; + assign n2457 = 64'haaaaaaaaaaaaaaa2 >> { n2461, n2458, n2459, n2460, n2462, n677 }; + assign n2458 = 32'd170535466 >> { n622, n675, n2173, n18, n638 }; + assign n2459 = 32'd170535466 >> { n622, n620, n2225, n18, n623 }; + assign n2460 = 32'd170535466 >> { n622, n640, n2222, n18, n643 }; + assign n2461 = 32'd170535466 >> { n622, n673, n2183, n18, n632 }; + assign n2462 = 64'h0200020002000202 >> { n2205, n2214, Pi19, n2160, n2149, n2171 }; + assign n726 = 32'd16122103 >> { n622, n727, n18, n647, Ni34 }; + assign n2463 = 64'haaaaaaaaaaaaaa2a >> { n2466, n2464, n2465, n2468, n2289, n672 }; + assign n2464 = 16'h5551 >> { n2257, n2251, n2171, Pi19 }; + assign n2465 = 32'd170535466 >> { n622, n648, n2263, n18, n643 }; + assign n2466 = 32'd170535466 >> { n622, n671, n2467, n18, n623 }; + assign n2467 = 32'd572662434 >> { n2256, n2254, n2259, n2181, n2266 }; + assign n2468 = 64'h4545450545054505 >> { n660, n622, n18, n638, n2469, n2470 }; + assign n2469 = 32'd572695074 >> { n2291, n2294, n2301, n2181, n2308 }; + assign n2470 = 64'hd0d0f0d0f0d0f0d0 >> { n2304, n2296, n2181, n632, n2471, n2311 }; + assign n2471 = 32'd1431639381 >> { n668, n657, n669, n622, n18 }; + assign n2472 = 64'haaaaaaaaaaaaaa2a >> { n2475, n2473, n2474, n2476, n2335, n659 }; + assign n727 = 16'haaa8 >> { Ni34, n650, n648, n728 }; + assign n2473 = 32'd705309226 >> { n622, n658, n2329, n18, n623 }; + assign n2474 = 64'hfd00fd00fd00ff00 >> { n18, n646, n643, n2322, n2323, n2324 }; + assign n2475 = 32'd170535466 >> { n622, n655, n2344, n18, n632 }; + assign n2476 = 32'd1145324628 >> { n2318, n2315, n2171, Pi19, n2477 }; + assign n2477 = 64'hd0d0f0d0f0d0f0d0 >> { n2339, n2342, n2181, n638, n2426, n2348 }; + assign n2478 = 8'h51 >> { Ni7, n596, n716 }; + assign n2479 = 4'h8 >> { Ni6, Ni5 }; + assign n1066 = 64'h68aaaaaa6aaaaaaa >> { n597, P__cmxcl_0, Ni10, Ni9, Ni8, Ni7 }; + assign n1046 = 64'h68aaaaaa6aaaaaaa >> { n585, P__cmxcl_0, Ni14, Ni12, Ni13, Ni11 }; + assign n1041 = 32'd1084910250 >> { n586, P__cmxcl_0, Ni14, Ni13, Ni12 }; + assign n728 = 4'h8 >> { P__cmxig_1, n622 }; + assign P__cmxir_1 = 8'h08 >> { P__cmxig_1, n716, P__cmxcl_0 }; + assign P__cmxir_0 = 16'h2a08 >> { Pi25, P__cmxig_0, Ni10, n717 }; + assign P__cmx1ad_31 = 4'h8 >> { P__cmx1ad_9, Pi255 }; + assign P__cmx1ad_30 = 4'h8 >> { P__cmx1ad_9, Pi254 }; + assign P__cmx1ad_29 = 4'h8 >> { P__cmx1ad_9, Pi253 }; + assign P__cmx1ad_28 = 4'h8 >> { P__cmx1ad_9, Pi252 }; + assign P__cmx1ad_27 = 4'h8 >> { P__cmx1ad_9, Pi251 }; + assign P__cmx1ad_26 = 4'h8 >> { P__cmx1ad_9, Pi250 }; + assign P__cmx1ad_25 = 4'h8 >> { P__cmx1ad_9, Pi249 }; + assign P__cmx1ad_24 = 4'h8 >> { P__cmx1ad_9, Pi248 }; + assign n729 = 32'd218963213 >> { P__cmxig_1, n622, Ni34, n647, n721 }; + assign P__cmx1ad_23 = 4'h8 >> { P__cmx1ad_9, Pi247 }; + assign P__cmx1ad_22 = 4'h8 >> { P__cmx1ad_9, Pi246 }; + assign P__cmx1ad_21 = 4'h8 >> { P__cmx1ad_9, Pi245 }; + assign P__cmx1ad_20 = 4'h8 >> { P__cmx1ad_9, Pi244 }; + assign P__cmx1ad_19 = 4'h8 >> { P__cmx1ad_9, Pi243 }; + assign P__cmx1ad_18 = 4'h8 >> { P__cmx1ad_9, Pi242 }; + assign P__cmx1ad_17 = 4'h8 >> { P__cmx1ad_9, Pi241 }; + assign P__cmx1ad_16 = 4'h8 >> { P__cmx1ad_9, Pi240 }; + assign P__cmx1ad_15 = 8'h80 >> { P__cmx1ad_9, Pi26, Pi27 }; + assign P__cmx1ad_13 = 4'h2 >> { n1296, P__cmx1ad_9 }; + assign n730 = 16'h22a2 >> { n731, Pi25, n733, n623 }; + assign P__cmx1ad_7 = 4'h8 >> { P__cmx1ad_9, Pi239 }; + assign P__cmx1ad_6 = 4'h8 >> { P__cmx1ad_9, Pi238 }; + assign P__cmx1ad_5 = 4'h8 >> { P__cmx1ad_9, Pi237 }; + assign P__cmx1ad_4 = 4'h8 >> { P__cmx1ad_9, Pi236 }; + assign P__cmx1ad_3 = 4'h8 >> { P__cmx1ad_9, Pi235 }; + assign P__cmx1ad_2 = 4'h8 >> { P__cmx1ad_9, Pi234 }; + assign P__cmx1ad_1 = 4'h8 >> { P__cmx1ad_9, Pi233 }; + assign P__cmx1ad_0 = 4'h8 >> { P__cmx1ad_9, Pi232 }; + assign P__cmx0ad_31 = 4'h8 >> { P__cmx0ad_9, Pi72 }; + assign P__cmx0ad_30 = 4'h8 >> { P__cmx0ad_9, Pi71 }; + assign n731 = 64'h2225fffdeeedfffd >> { Ni33, n622, n671, n732, n18, Ni34 }; + assign P__cmx0ad_29 = 4'h8 >> { P__cmx0ad_9, Pi70 }; + assign P__cmx0ad_28 = 4'h8 >> { P__cmx0ad_9, Pi69 }; + assign P__cmx0ad_27 = 4'h8 >> { P__cmx0ad_9, Pi68 }; + assign P__cmx0ad_26 = 4'h8 >> { P__cmx0ad_9, Pi67 }; + assign P__cmx0ad_25 = 4'h8 >> { P__cmx0ad_9, Pi66 }; + assign P__cmx0ad_24 = 4'h8 >> { P__cmx0ad_9, Pi65 }; + assign P__cmx0ad_23 = 4'h8 >> { P__cmx0ad_9, Pi64 }; + assign P__cmx0ad_22 = 4'h8 >> { P__cmx0ad_9, Pi63 }; + assign P__cmx0ad_21 = 4'h8 >> { P__cmx0ad_9, Pi62 }; + assign P__cmx0ad_20 = 4'h8 >> { P__cmx0ad_9, Pi61 }; + assign n732 = 8'h08 >> { Ni38, n618, n617 }; + assign P__cmx0ad_19 = 4'h8 >> { P__cmx0ad_9, Pi60 }; + assign P__cmx0ad_18 = 4'h8 >> { P__cmx0ad_9, Pi59 }; + assign P__cmx0ad_17 = 4'h8 >> { P__cmx0ad_9, Pi58 }; + assign P__cmx0ad_16 = 4'h8 >> { P__cmx0ad_9, Pi57 }; + assign P__cmx0ad_15 = 8'h80 >> { P__cmx0ad_9, Pi23, Pi24 }; + assign P__cmx0ad_13 = 4'h2 >> { n1585, P__cmx0ad_9 }; + assign P__cmx0ad_7 = 4'h8 >> { P__cmx0ad_9, Pi56 }; + assign P__cmx0ad_6 = 4'h8 >> { P__cmx0ad_9, Pi55 }; + assign P__cmx0ad_5 = 4'h8 >> { P__cmx0ad_9, Pi54 }; + assign P__cmx0ad_4 = 4'h8 >> { P__cmx0ad_9, Pi53 }; + assign n733 = 32'd218963213 >> { P__cmxig_1, n622, Ni34, n658, n721 }; + assign P__cmx0ad_3 = 4'h8 >> { P__cmx0ad_9, Pi52 }; + assign P__cmx0ad_2 = 4'h8 >> { P__cmx0ad_9, Pi51 }; + assign P__cmx0ad_1 = 4'h8 >> { P__cmx0ad_9, Pi50 }; + assign P__cmx0ad_0 = 4'h8 >> { P__cmx0ad_9, Pi49 }; + assign P__cmndst1p0 = 8'h02 >> { n1201, Ni42, Ni43 }; + assign P__cmndst0p0 = 8'ha2 >> { Ni32, Ni30, n823 }; + assign n941 = 8'hd8 >> { Ni46, Pi20, n2540 }; + assign n2540 = 32'd286265617 >> { Ni31, Ni32, Ni30, Pi21, Ni45 }; + assign n981 = 64'hbbbbb000fffff444 >> { Ni31, n2542, Ni37, Ni38, Ni30, Ni32 }; + assign n2542 = 16'h8a02 >> { Pi15, n2543, Ni36, Ni38 }; + assign n734 = 64'h1595959555d5d5d5 >> { Pi25, n18, Ni33, n671, n622, Ni34 }; + assign n2543 = 32'd626841 >> { Pi17, Pi19, Ni35, Ni39, Pi20 }; + assign n1016 = 64'hff00ff02ff02ff02 >> { n617, n624, Ni31, Ni30, Ni32, P__cmxcl_0 }; + assign n2545 = 8'h82 >> { Pi20, Ni39, n2546 }; + assign n2546 = 4'h2 >> { Pi17, Pi18 }; + assign n2547 = 64'h4447ffff0007bbbf >> { Ni31, Ni37, Ni43, Ni42, Ni30, Ni32 }; + assign n961 = 16'h09ff >> { n2549, n2551, Ni44, Ni39 }; + assign n2549 = 16'hfbf9 >> { n2550, n1201, Ni42, Ni43 }; + assign n2550 = 32'd2380127709 >> { n2143, n2546, Ni40, Pi16, Ni41 }; + assign n2551 = 64'h888bffff000b777f >> { Ni31, Ni42, Ni37, Ni38, Ni30, Ni32 }; + assign n2552 = 32'd2282258432 >> { n576, n571, Ni33, n605, n609 }; + assign n735 = 64'h1595959555d5d5d5 >> { Pi25, n18, Ni33, n693, n622, Ni34 }; + assign n996 = 32'd4201830480 >> { Pi23, Pi26, Ni35, Ni33, n2552 }; + assign n1001_1 = 64'he4eee4ee4444e4ee >> { n2581, n2895, n3029, Ni10, n3035, n717 }; + assign n2555 = 64'h2020002022ff00ff >> { n638, n626, n632, n633, P__cmxig_1, n622 }; + assign n2556 = 64'h002000222020ffff >> { n623, n632, n658, n655, P__cmxig_1, n622 }; + assign n2557 = 64'hdfffdfdfddff0000 >> { n623, n638, n660, n671, P__cmxig_1, n622 }; + assign n2558 = 64'h2020002022ff00ff >> { n632, n640, n643, n673, P__cmxig_1, n622 }; + assign n2559 = 64'hc0e0d0f0d0f0d0f0 >> { n622, n687, n710, n643, P__cmxig_1, Pi15 }; + assign n2560 = 64'h15bbaaaa55fbaaaa >> { n678, Ni34, n2559, n623, n804, Pi15 }; + assign n2561 = 64'hdfffdfdfddff0000 >> { n623, n643, n702, n2562, P__cmxig_1, n622 }; + assign n2562 = 64'h20202020aa202020 >> { Ni38, n665, n697, n619, n695, n617 }; + assign n736 = 32'd2324343434 >> { n741, n643, n739, n737, n659 }; + assign n2563 = 32'd715786376 >> { Pi25, n18, Ni33, Ni34, n622 }; + assign n2564 = 64'h999f195f159f555f >> { n626, n633, n632, n638, n2563, Ni34 }; + assign n2565 = 64'h00d8d8d8d8d8d8d8 >> { Ni34, Ni33, n18, n655, n651, Pi20 }; + assign n2566 = 64'h0000d7770000f777 >> { Pi25, n730, n2565, n622, Ni34, n699 }; + assign n2567 = 32'd712998783 >> { n643, n648, Ni33, n18, Ni34 }; + assign n2568 = 64'hb7f7777727772777 >> { n2567, n660, Pi25, n622, n699, Ni34 }; + assign n2569 = 64'hdf7fff7fdd5dff7f >> { n2567, n622, n667, n699, Ni34, Pi25 }; + assign n2570 = 32'd715786376 >> { Pi25, n18, Ni33, Ni34, n622 }; + assign n2571 = 64'h999f195f159f555f >> { n679, n687, n623, n643, n2570, Ni34 }; + assign n2572 = 16'h2202 >> { n735, n699, n724, n2571 }; + assign n737 = 32'd2852653064 >> { n721, n708, n738, Pi25, n623 }; + assign n2573 = 64'h44e440a0eaaa40a0 >> { n713, n623, n715, n643, n622, Ni34 }; + assign n2574 = 32'd715786376 >> { Pi25, n18, Ni33, Ni34, n622 }; + assign n2575 = 64'h9b1b9f5f9f5f9f5f >> { n699, n742, n702, n643, n2574, Ni34 }; + assign n2576 = 32'd707439146 >> { n743, n623, n698, n2575, n677 }; + assign n2577 = 64'ha8a8202000a80020 >> { Ni33, n701, n18, n694, Pi16, n624 }; + assign n2578 = 32'd170535466 >> { n622, n2577, n776, Ni34, Pi15 }; + assign n2579 = 64'heaaa6aaa2aaa6aaa >> { Ni33, n18, n622, n624, n711, Ni34 }; + assign n2580 = 64'h0020002220202222 >> { n2579, n751, n747, n791, n785, n786 }; + assign n2581 = 64'h00aa80aa08aa88aa >> { n804, n805, n3061, Pi16, n776, n806 }; + assign n2582 = 64'hc0aa40aa80aa00aa >> { n660, n675, Pi19, n624, n622, Pi16 }; + assign n738 = 32'd934674357 >> { Ni33, n18, n708, n622, Ni34 }; + assign n2583 = 32'd3932834410 >> { Ni33, n18, Pi19, Ni34, n2582 }; + assign n2584 = 64'hbf00bb00bd00b900 >> { n802, n803, n799, Pi19, n2583, Pi17 }; + assign n2585 = 64'hdfdfdfdf55dfdfdf >> { n1117, n973, n1119, n776, n1124, Pi21 }; + assign n2586 = 64'h1111111111111151 >> { n1120, n1122, n1125, n2585, n792, n1135 }; + assign n1006 = 64'hdcfedcfedcdcdcfe >> { n1127, n2586, n718, Ni33, n807, P__cmxcl_0 }; + assign n2588 = 64'h5d7f5d7f55555d7f >> { n621, n828, n816, n831, Pi16, n825 }; + assign n2589 = 64'h0002020200ffffff >> { n756, n2588, n758, n829, n833, n832 }; + assign n2590 = 64'h55ff040c55ff0008 >> { Ni45, n843, Pi22, n817, n622, Pi21 }; + assign n2591 = 64'h3f3f153f37371537 >> { n930, n946_1, n624, n947, n699, n835 }; + assign n2592 = 32'd2863311402 >> { n916, n938, n928, n2591, n948 }; + assign n739 = 64'h4444c4ccc4ccc4cc >> { n721, n694, Pi25, n740, n707, n699 }; + assign n2593 = 64'hf0d0f0d0d0d0f0d0 >> { n949, n754, n839, n966_1, Pi19, Pi20 }; + assign n2594 = 64'heaeaeac0eaeaeac8 >> { n970, n972, n971, n947, Pi19, n835 }; + assign n2595 = 64'h0055045504550455 >> { n2594, n624, n973, n957, n2593, Pi15 }; + assign n2596 = 64'hf575f575f5757575 >> { n681, n982, n832, n871, n851, n873 }; + assign n2597 = 64'h08aa08aa00aa08aa >> { n980, n851, n860, n978, n852, n2596 }; + assign n2598 = 32'd125269879 >> { n983, n2597, n974, n2600, n991_1 }; + assign n2599 = 64'h2202220222027757 >> { n1003, n1004, n993, n851, n894, Pi19 }; + assign n2600 = 64'hffaafbaafbaafbaa >> { n852, n2599, n897, Pi16, n754, Pi17 }; + assign n2601 = 64'h0a5f8adf4e5fcedf >> { n1005, n1007, n897, n839, n754, Pi20 }; + assign n2602 = 64'h2022202200222022 >> { Pi19, n2601, n973, n1009, n1016_1, Pi15 }; + assign n740 = 32'd934674357 >> { Ni33, n18, n694, n622, Ni34 }; + assign n2603 = 64'hff557f55f7557755 >> { n894, n1068, n754, Pi20, n1057, n1058 }; + assign n2604 = 64'h3737373737377737 >> { n922, n927, n1057, n749, n747, n1059 }; + assign n2605 = 64'h0000000000000008 >> { Pi15, n1055, n1061, n1065, n2905, n2604 }; + assign n2606 = 64'h000808080088aaaa >> { n638, n643, n985, n1068, n1057, n932 }; + assign n2607 = 64'h0008080800aaffff >> { n638, n623, n876, n870, n1067, n1057 }; + assign n2608 = 64'h0002020200aaffff >> { n632, n623, n911, n894, n891, n1057 }; + assign n2609 = 64'h31f131f1115131f1 >> { n1000, Ni33, n978, n1057, n643, n623 }; + assign n2610 = 64'h7070f070f070f070 >> { n1057, n1067, n638, n645, n2609, n1078 }; + assign n2611 = 64'h0008000a8888ffff >> { n699, n643, n936, n1064, n1060, n1057 }; + assign n2612 = 64'h02ff0aff00ff08ff >> { n932, n942, n672, n1082, n643, n2611 }; + assign n741 = 64'h1595959555d5d5d5 >> { Pi25, n18, Ni33, n711, n622, Ni34 }; + assign n2613 = 64'h0002020200aaffff >> { n643, n699, n967, n953, n1063, n1057 }; + assign n2614 = 64'hf131f1315111f131 >> { n1000, Ni33, n1075, n1091, n632, n623 }; + assign n2615 = 64'h00800088a0a0aaaa >> { n643, n638, n1102, n1103, n1091, n932 }; + assign n2616 = 64'hff007f00f7007700 >> { n1095, n1094, n932, Pi20, Pi19, n624 }; + assign n2617 = 64'h2a222a22aaaa2a22 >> { n1097, n643, n623, n1096, n2616, n677 }; + assign n2618 = 64'hf777f7775555f777 >> { n1104, n644, n1091, n963, n625, n624 }; + assign n2619 = 32'd707439146 >> { n1105, n699, n932, n2618, n645 }; + assign n2620 = 64'hc4c4c4c444c4c4c4 >> { n923, Ni33, n937, n1108, n932, n699 }; + assign n2621 = 64'hf575f575f5757575 >> { n814, Ni40, n923, n1109, n864, n643 }; + assign n2622 = 64'h0001010100ff11ff >> { n1244, Ni32, n1248, n1246, n1166, n1168 }; + assign n742 = 8'h8a >> { Ni36, n619, n701 }; + assign n2623 = 64'h0001010100ff11ff >> { n1251, Ni32, n1241, n1246, n1230, n1228 }; + assign n2624 = 64'h0004040400ff55ff >> { n1251, n1190, n1241, n1265, n1262, n1194 }; + assign n2625 = 32'd2728569506 >> { n1162, n1264, n1266, n2624, n758 }; + assign n2626 = 64'h0001010100ff11ff >> { n1251, Ni32, n1241, n1246, n1157, n1154 }; + assign n2627 = 64'h0001010100ff11ff >> { n1251, Ni32, n1241, n1246, n1212, n1210 }; + assign n2628 = 64'hc4ccc4cc8088c4cc >> { n1267, n1268, n1278, n1277, n624, Pi20 }; + assign n2629 = 32'd2854890026 >> { n2628, n585, n1279, n1252, n758 }; + assign n2630 = 64'h084c2a6e195d3b7f >> { n1218, n1286, n1220, n1285, Pi20, n585 }; + assign n2631 = 64'h00aa80aa08aa88aa >> { n1292, n1260, n2923, n585, n1263, n677 }; + assign n2632 = 64'h0f2f0f2f2f2f0f2f >> { n1236, n1237, n1299, n746, n1306, n1307 }; + assign n743 = 64'h1595959555d5d5d5 >> { Pi25, n18, Ni33, n2562, n622, Ni34 }; + assign n2633 = 64'h222222222222222a >> { n1298, n1300, n1302, n1304, n758, n1308 }; + assign n2634 = 64'h0001010100ff11ff >> { n1305, Ni32, n1299, n1246, n1168, n1166 }; + assign n2635 = 64'h0001010100ff11ff >> { n1301, Ni32, n1303, n1246, n1210, n1212 }; + assign n2636 = 64'h0004040400ff55ff >> { n1301, n1190, n1303, n1265, n1262, n1194 }; + assign n2637 = 32'd707439146 >> { n1162, n1309, n1310, n2636, n758 }; + assign n2638 = 64'hc4ccc4cc8088c4cc >> { n1267, n1268, n1278, n1277, n1296, Pi20 }; + assign n2639 = 64'hff00fd00fd00fd00 >> { n624, n2638, n758, n1309, n1317, n1295 }; + assign n2640 = 64'hfff77f77fdf57d75 >> { n1183, n1275, n1185, n1296, Pi20, n624 }; + assign n2641 = 32'd707439146 >> { n1276, n1305, n1295, n2640, n748 }; + assign n2642 = 64'h0004040400ff55ff >> { n1325, n1190, n1324, n1265, n1262, n1194 }; + assign n744 = 64'h03570377035f03ff >> { n708, n655, Ni34, n745, n747, n622 }; + assign n2643 = 64'h084c2a6e195d3b7f >> { n1183, n1185, n1276, n1275, Pi27, Pi20 }; + assign n2644 = 64'h2a227f777f777f77 >> { n1337, n1338, n1323, n1218, n1334, Pi16 }; + assign n2645 = 32'd4227574523 >> { n1162, n1329, Pi27, n798, n1173 }; + assign n2646 = 64'hff7ff777fd7df575 >> { n1217, n1291, n1290, Pi20, Pi27, n624 }; + assign n2647 = 16'h2220 >> { n1330, n1260, Pi15, n1331 }; + assign n2648 = 32'd134776840 >> { n1333, n2646, n757, n2645, n2647 }; + assign n2649 = 64'h0001010100ff11ff >> { n1326, Ni32, n1323, n1246, n1168, n1166 }; + assign n2650 = 16'hf7d5 >> { n1361, n1362, Pi19, n645 }; + assign n2651 = 64'hbb111b11ab010b01 >> { n1363, n1364, n1359, n677, n1356, Pi19 }; + assign n2652 = 32'd2315954730 >> { n1358, n1360, n672, Pi19, n2651 }; + assign n745 = 4'h2 >> { Pi16, n746 }; + assign n2653 = 64'ha2a2a0a2a0a2a0a2 >> { n2650, n2652, n624, n2655, Pi17, n1163 }; + assign n2654 = 64'h5d5d085d19190819 >> { n1350, n1349, n672, n1351, n677, Pi19 }; + assign n2655 = 64'h0220222202002222 >> { n1348, n624, Pi19, n2654, n1352, n1355 }; + assign n2656 = 64'h03570377035f03ff >> { n1221, n1219, n1246, n1370, n1369, n1147 }; + assign n2657 = 64'h03570377035f03ff >> { n1186, n1184, n1246, n1370, n1369, n1147 }; + assign n2658 = 64'h03570377035f03ff >> { n1225, n1223, n1246, n1369, n1370, n1147 }; + assign n2659 = 64'h7f777f777f773f33 >> { n1416, n1415, n1414, n1162, n1402, n1245 }; + assign n2660 = 64'h00ff02ff02ff02ff >> { n2659, n758, n672, n1408, n1411, n1417 }; + assign n2661 = 64'haaaaaaaaaaaaaa2a >> { n2664, n2944, n2947, n2660, Ni14, n1423 }; + assign n2662 = 64'h03570377035f03ff >> { n1186, n1184, n1246, n1400, n1401, n1147 }; + assign n746 = 4'h2 >> { Pi17, Pi19 }; + assign n2663 = 32'd2400161679 >> { n1399, n1353, n748, n2662, n1402 }; + assign n2664 = 32'd2863311402 >> { n1404, n2666, n2663, n1407, n645 }; + assign n2665 = 64'h03570377035f03ff >> { n1225, n1223, n1246, n1401, n1400, n1147 }; + assign n2666 = 32'd707439146 >> { n1362, n1399, n1402, n2665, n746 }; + assign n2667 = 64'h03570377035f03ff >> { n1180, n1178, n1246, n1401, n1400, n1147 }; + assign n2668 = 64'hfca8fc88fca0fc00 >> { n1155, n1141, n1246, n1400, n1401, n1147 }; + assign n2669 = 16'h77f7 >> { n1246, n1146, n748, n2668 }; + assign n2670 = 64'h4444c4ccc4ccc4cc >> { n1356, n758, n748, n1348, n1421, n1399 }; + assign n2671 = 64'h2a2a2a2a2a2a2aaa >> { n1439, n1441, n1443, n1356, n758, n1437 }; + assign n2672 = 64'h02ff02ff02ff00ff >> { n1452, n1162, n659, n1444, n1447, n2671 }; + assign n747 = 4'h2 >> { Pi16, n748 }; + assign n2673 = 64'h03570377035f03ff >> { n1186, n1184, n1246, n1440, n1442, n1147 }; + assign n2674 = 64'h03570377035f03ff >> { n1225, n1223, n1246, n1442, n1440, n1147 }; + assign n2675 = 64'h7f777f772a227f77 >> { n1455, n1454, n1443, n1350, n1453, Pi17 }; + assign n2676 = 64'hf700f700ff00f700 >> { Pi19, n2675, n677, n2678, n1437, n1456 }; + assign n2677 = 64'h03570377035f03ff >> { n1221, n1219, n1246, n1440, n1442, n1147 }; + assign n2678 = 16'h22a2 >> { n1364, n1443, n2677, n746 }; + assign n2679 = 64'hd5ddd5dd5555d5dd >> { n1353, n751, n747, n1348, n1426, n754 }; + assign n2680 = 64'h3133313311113133 >> { n1474, n1476, n1477, n1470, n1497, n747 }; + assign n2681 = 32'd128 >> { n1478, n1482, n2679, n2680, n1488 }; + assign n2682 = 64'h0001010100ff11ff >> { n1542, Ni32, n1553, n1537, n1166, n1507 }; + assign n748 = 4'h2 >> { Pi19, Pi17 }; + assign n2683 = 32'd2324335114 >> { n1523, n597, n1263, n1562, n1539 }; + assign n2684 = 16'ha222 >> { n2682, n1561, n748, n2683 }; + assign n2685 = 64'h0004040400ff55ff >> { n1547, n1190, n1552, n1265, n1538, n1481 }; + assign n2686 = 64'h88880008ffff000f >> { n758, n1569, n1567, n1570, n2685, n1563 }; + assign n2687 = 64'h0001010100ff11ff >> { n1542, Ni32, n1553, n1537, n1140, n1475 }; + assign n2688 = 64'h084c2a6e195d3b7f >> { n1493, n1571, n1494, n1572, Pi20, n597 }; + assign n2689 = 64'h00ababababababab >> { n746, n2688, n624, n1570, n1567, n1578 }; + assign n2690 = 64'hfdfdfdfdfdfdfddd >> { n1140, n1475, Ni32, n1587, n1590, n1591 }; + assign n2691 = 64'h22222222222222a2 >> { n2695, n2698, n2965, n2959, n716, n1603 }; + assign n2692 = 64'h5455fcfd005500fd >> { n1538, n1201, n1584, n1193, n1480, n1587 }; + assign n749 = 4'h8 >> { n750, Pi25 }; + assign n2693 = 64'h0101000155ff00ff >> { n1588, n1484, n1584, n1486, n1210, n1537 }; + assign n2694 = 64'hf373f3735151f373 >> { n1520, n758, n1511, n1596, n746, n1587 }; + assign n2695 = 16'haa2a >> { n1594, n2961, n2694, n677 }; + assign n2696 = 64'hf3f351f373735173 >> { n1498, n1493, n746, n1599, n748, n1587 }; + assign n2697 = 32'd2324335114 >> { n1585, n1578, n1263, n1568, n1589 }; + assign n2698 = 64'hf700f700ff00f700 >> { n1598, n746, n645, n2700, n2696, n2697 }; + assign n2699 = 64'h0004040400ff55ff >> { n1584, n1197, n1587, n1267, n1538, n1490 }; + assign n2700 = 64'h2a2a2a2a2a2aaa2a >> { n1198, n1491, n1586, n1600, n2699, n758 }; + assign n2701 = 64'h0101000155ff00ff >> { n1588, n1504, n1584, n1503, n1228, n1537 }; + assign n2702 = 64'h3331333133312220 >> { n1516, n1232, n1517, n1234, n1585, Pi20 }; + assign n750 = 4'h2 >> { Pi20, n624 }; + assign n2703 = 64'ha222a222a222aaaa >> { n1559, n1597, n2702, n624, n1589, n758 }; + assign n2704 = 32'd353703359 >> { Ni13, Ni11, n1583, n583, Ni12 }; + assign n2705 = 64'heeaabbbbec20b333 >> { Pi24, n2704, n2708, n1435, Ni12, n1581 }; + assign n2706 = 64'h55ff15bf51fb11bb >> { n1493, n1494, n1568, Pi20, n624, Pi24 }; + assign n2707 = 64'ha0208000aa22aa00 >> { n756, Pi24, n1495, n1620, n2706, n1621 }; + assign n2708 = 64'hfdecfdecececfdec >> { n1367, n624, n1295, n1580, Ni13, Ni14 }; + assign n2709 = 64'h000400054444ffff >> { n638, n632, n1210, n1486, n1484, Ni32 }; + assign n2710 = 64'h1111111111115111 >> { n1648, n1649, n1163, n2709, n659, Pi17 }; + assign n2711 = 32'd993770299 >> { n1509, n1170, n672, n643, n1470 }; + assign n2712 = 64'h080a88aa000a88aa >> { n1523, n672, n699, n1651, n1569, n1163 }; + assign n751 = 4'h8 >> { n748, Pi16 }; + assign n2713 = 64'h7f007f00ff007f00 >> { n1474, n623, n583, n2712, n2711, n1652 }; + assign n2714 = 64'h111111111111111b >> { n2988, n1849, n2993, n2995, n1805, n583 }; + assign n2715 = 64'h80808080a2808080 >> { n2975, n2727, n1829, n2714, Ni11, Ni10 }; + assign n2716 = 64'h1505150500041504 >> { n1686, n1731, n1305, n1684, n1726, n2977 }; + assign n2717 = 64'haabfaabfaaffaabf >> { n1685, n1296, n1687, n624, Pi20, n1671 }; + assign n2718 = 64'haaaaaaaaaaaa2aaa >> { n1689, n1703, n2717, n1679, n1714, n672 }; + assign n2719 = 64'hff22f222ff20f020 >> { n1722, n1724, n1301, n1684, n1303, n1305 }; + assign n2720 = 64'h2a22aaaa0a008a88 >> { n1725, n1723, n2719, n1686, n1303, n748 }; + assign n2721 = 64'hfffdfffdfffdf7f5 >> { n1738, n1763, n1764, n1686, n1296, n1263 }; + assign n2722 = 32'd2863311522 >> { n2724, n1744, n1753, n2721, n677 }; + assign n752 = 8'h80 >> { n624, Pi20, Pi25 }; + assign n2723 = 64'haabbbbbbaabfbfbf >> { n1305, n1301, n1739, n1299, n1741, n1677 }; + assign n2724 = 32'd2728569506 >> { n1743, n1303, n1687, n2723, n746 }; + assign n2725 = 64'h080accff000accff >> { n1766, n748, n1303, n1765, n1769, n1767 }; + assign n2726 = 64'haabbabbbaabfafbf >> { n1684, Ni30, n1299, n1698, n1305, n1686 }; + assign n2727 = 32'd2139053439 >> { n2730, n3052, n1805, Ni13, Ni12 }; + assign n2728 = 64'h00220fff02220fff >> { n1788, n757, n1325, n1685, n1792, n1790 }; + assign n2729 = 32'd1162149957 >> { n1671, n1324, n1323, n1774, n1775 }; + assign n2730 = 64'h0000000000008000 >> { n1785, n2736, n2732, n2728, n2729, n2738 }; + assign n2731 = 64'h4c5f4c5f4c5d4c5f >> { n1677, n1735, n1783, Ni30, n1740, n1324 }; + assign n2732 = 64'h0455045500550455 >> { n1782, n1323, n756, n1784, n2731, n1776 }; + assign n753 = 4'h2 >> { n719, n622 }; + assign n2733 = 64'h05af052704ae0426 >> { Ni30, n1702, n1684, n1786, n1698, Pi27 }; + assign n2734 = 64'hff7dff77fffdfff7 >> { n1691, n2733, n1686, Pi20, Pi27, n624 }; + assign n2735 = 64'ha999a999a899a999 >> { n1708, n1706, n1324, Ni30, n1787, n1677 }; + assign n2736 = 64'ha822a822a8228822 >> { n1326, n1323, n2735, n1710, n1677, n747 }; + assign n2737 = 32'd8 >> { Pi16, n1686, n1717, n776, n1795 }; + assign n2738 = 64'h1010001032320032 >> { n2737, n1763, n1793, n1794, Pi15, n624 }; + assign n2739 = 64'hfffff7d5fbeaf3c0 >> { n1698, n1692, Ni30, n1684, Pi27, Pi20 }; + assign n2740 = 64'ha2a2a2a2aaa2a2a2 >> { Ni31, Ni33, Pi27, n624, Ni30, Pi15 }; + assign n2741 = 32'd17895263 >> { n1251, Ni30, n1241, n1684, n1735 }; + assign n2742 = 64'haabbabbbaabfafbf >> { n1724, n1722, n1244, n1684, n1251, n1686 }; + assign n754 = 4'h8 >> { n624, Pi25 }; + assign n2743 = 64'hfd00fd00ff00fd00 >> { n1723, n1241, n748, n1844, n1845, n2742 }; + assign n2744 = 64'haabbbbbbaabfbfbf >> { n1251, n1244, n1746, n1241, n1751, n1677 }; + assign n2745 = 16'hdd5d >> { n1749, n1845, n2744, Pi17 }; + assign n2746 = 64'hc4ccc4cc4444c4cc >> { n1842, n758, n746, n1841, n1836, Pi16 }; + assign n2747 = 32'd285278465 >> { n2746, n1879, n754, Pi15, n1896 }; + assign n2748 = 64'h4044505500445055 >> { n1839, n746, n1371, n1835, n1927, n1928 }; + assign n2749 = 64'hf531f03075317030 >> { n1834, n1931, n1933, n1836, n748, n1371 }; + assign n2750 = 64'h080accff000accff >> { n1833, n748, n1371, n1926, n1842, n1937 }; + assign n2751 = 64'hf531f03075317030 >> { n1832, n1942, n1943, n1837, n748, n1371 }; + assign n2752 = 64'hdf00df0fdd00dd0d >> { n1959, n1946, n1842, n1399, n1833, n748 }; + assign n755 = 32'd2147483648 >> { Pi22, Pi17, Pi19, Pi21, Pi25 }; + assign n2753 = 64'h55555555555555d5 >> { n1944, n1945, n1947, n2752, n1948, n677 }; + assign n2754 = 32'd2863311402 >> { n2756, n2758, n2753, n2760, n1423 }; + assign n2755 = 64'hf531f03075317030 >> { n1839, n1950, n1951, n1835, n746, n1399 }; + assign n2756 = 32'd2863311402 >> { n1944, n1952, n2755, n1955, n659 }; + assign n2757 = 64'h00df000f00dd000d >> { n1951, n1836, n1958, n1399, n1840, n746 }; + assign n2758 = 64'haaaaaaaaaaaaaa2a >> { n1944, n1956, n1957, n1932, n2757, n672 }; + assign n2759 = 64'hf531f03075317030 >> { n1832, n1960, n1959, n1837, n748, n1399 }; + assign n2760 = 64'h22222222222222a2 >> { n1944, n1949, n1961, n2759, n645, Ni14 }; + assign n2761 = 64'hfffefefeffeeaaaa >> { n1440, n1442, n1672, n1680, n1684, n1443 }; + assign n2762 = 64'h7677545554555455 >> { Ni33, n585, n1678, Ni32, Ni31, Ni30 }; + assign n756 = 4'h8 >> { n746, Pi16 }; + assign n2763 = 64'hf531f03075317030 >> { n1832, n1969, n1968, n1837, n748, n1443 }; + assign n2764 = 32'd2863311522 >> { n1963, n1970, n1972, n2763, n645 }; + assign n2765 = 64'h5544544455405040 >> { n1789, n1762, n1440, n1684, n1442, n1443 }; + assign n2766 = 64'hfffefefeffeeaaaa >> { n1440, n1442, n1770, n1772, n1684, n1443 }; + assign n2767 = 16'hdd5d >> { n1917, n746, n1906, n1586 }; + assign n2768 = 64'hf531f733f531ff33 >> { n1737, n1731, n1985, n1874, n746, n1587 }; + assign n2769 = 64'hdddfdddfdddfddff >> { n1588, n1584, n1586, n1722, n1874, n1724 }; + assign n2770 = 64'h4e4e4e4e4e4eff4e >> { n1752, n1874, n1724, n1982, Ni30, n1585 }; + assign n2771 = 64'h5575757575757575 >> { n624, n2770, Pi20, n1987, n1986, n748 }; + assign n2772 = 32'd2863278762 >> { n1988, n2771, n1993, n1997, n677 }; + assign n757 = 4'h8 >> { n758, Pi16 }; + assign n2773 = 16'hdd5d >> { n1915, n748, n1902, n1587 }; + assign n2774 = 64'hf531f733f531ff33 >> { n1706, n1770, n2000, n1874, n748, n1586 }; + assign n2775 = 64'h3133f5f7003300f7 >> { n1982, Ni30, n1584, n1874, n1587, n1698 }; + assign n2776 = 64'h1111111111111115 >> { n2008, n2009, n2010, n2011, n748, n1983 }; + assign n2777 = 64'h0100010001000101 >> { n2001, n2003, n1720, n2012, n2013, n2014 }; + assign n2778 = 64'hf700f700ff00f700 >> { n1882, n1587, n672, n2004, n2776, n2777 }; + assign n2779 = 64'hf6c4f2c0feccfac8 >> { Pi27, Pi24, n1688, Ni31, Ni14, Ni33 }; + assign n2780 = 8'h15 >> { Ni30, n2779, n1925 }; + assign n2781 = 64'h8088f0ff0088f0ff >> { n1888, n748, n1552, n1891, n2022, n2023 }; + assign n2782 = 64'h555555555555d555 >> { n2026, n2029, n2781, n2031, n2032, n677 }; + assign n758 = 4'h1 >> { Pi17, Pi19 }; + assign n2783 = 64'h3131313111313131 >> { n2785, n2782, n2786, n583, Ni11, n2053 }; + assign n2784 = 64'h00080000000a0002 >> { n2044, n1720, n2041, n2025, n2045, n2042 }; + assign n2785 = 64'hfd00fd00ff00fd00 >> { n1882, n1553, n672, n2033, n2036, n2784 }; + assign n2786 = 32'd286331313 >> { n2045, n2047, n3005, n3008, n659 }; + assign n2787 = 64'hcd05dd05cf05ff05 >> { n1706, n1711, n1982, n1542, n1874, n1547 }; + assign n2788 = 64'h3133f5f7003300f7 >> { n1982, Ni30, n1542, n1874, n1553, n1731 }; + assign n2789 = 64'haa8aaa8affffaa8a >> { n1874, n1711, Ni31, Pi24, Ni33, Ni30 }; + assign n2790 = 64'h0011101110111011 >> { n750, n2789, n747, n2066, n2067, n2069 }; + assign n2791 = 64'hd0d0f0d0f0d0f0d0 >> { n2790, n2056, n792, n1641, n2089, n2794 }; + assign n2792 = 64'hfff7fff7fff7fdf5 >> { n1749, n1920, n1888, Pi24, Pi20, n624 }; + assign n759 = 4'h2 >> { Pi16, n758 }; + assign n2793 = 32'd285278465 >> { n2792, n2071, n751, n2072, n2076 }; + assign n2794 = 64'h1111111111115111 >> { n2080, n2083, n2793, n2085, n806, n2796 }; + assign n2795 = 64'hccddecfdcedfeeff >> { n1296, Pi27, Pi24, Ni14, Ni31, Ni33 }; + assign n2796 = 16'ha888 >> { Ni30, n2795, n1925, n1423 }; + assign n2797 = 64'h2a222a222a227f77 >> { n1915, n1914, n623, n1920, n2096, Pi16 }; + assign n2798 = 64'hfeeefeeefeeeeeee >> { Pi16, n624, n2797, Pi15, n2092, n2094 }; + assign n2799 = 64'h5544444455404040 >> { n1925, n2798, n2097, Ni30, n1529, Ni11 }; + assign n2800 = 64'h444e444e555f444e >> { n1899, n1923, n2982, n1806, n2747, Ni10 }; + assign n2801 = 64'h04f444f426f666f6 >> { n1924, n2985, n1531, n572, Ni10, n2800 }; + assign n2802 = 64'hd0ddd0dd5055d0dd >> { n2115, n1530, Ni30, P__cmxcl_0, n2801, n1667 }; + assign n760 = 64'haa882000aa8a2202 >> { n746, n766, n765, n745, n757, n761 }; + assign n2803 = 64'haaaaaaaaaaaaaa2a >> { Ni4, Ni6, n590, Ni30, Ni5, Ni31 }; + assign n1071 = 64'hff7faa6aff7daa68 >> { n2127, n2806, Ni2, Ni3, n2803, Ni6 }; + assign n2805 = 64'hf7f75ff780800a80 >> { n2124, Pi26, n1116, Pi27, n584, Ni12 }; + assign n2806 = 64'ha8a8a8a800a8a8a8 >> { Ni11, Ni33, n2805, n612, n2126, n2125 }; + assign n2807 = 64'h2a606a226a406a22 >> { n590, Ni30, Ni4, Ni31, Ni6, Ni5 }; + assign n1076_1 = 64'hfeeef666faaaf222 >> { n2806, n2140, n1090, n2807, n2129, Ni5 }; + assign n2809 = 64'h0082aaaa33b3bbbb >> { n1322, Ni33, Pi27, Pi26, n582, n602 }; + assign n2810 = 64'haaa2aaa2ffffaaa2 >> { n2250, n758, n2310, n2307, n2289, n746 }; + assign n2811 = 64'h0002000000020002 >> { n2810, Pi16, n2203, n2229, n2267, n2146 }; + assign n2812 = 32'd1078219007 >> { Ni36, Ni37, n2150, n2153, n635 }; + assign n761 = 64'h2031001120312031 >> { Pi16, n766, n762, n764, Pi20, n748 }; + assign n2813 = 64'hafefaaefaeeeaaee >> { n2150, n2153, Ni36, n635, n2155, Ni32 }; + assign n2814 = 32'd4208515288 >> { n2151, n2812, n2813, Ni32, Ni35 }; + assign n2815 = 64'h00800088a0a0aaaa >> { Ni36, Ni37, n628, n2150, n2153, n2152 }; + assign n2816 = 64'hafbfaabfaeaeaaae >> { n2155, n2153, Ni36, n628, n2150, Ni32 }; + assign n2817 = 32'd3638098648 >> { n2158, n2815, n2816, Ni32, Ni35 }; + assign n2818 = 64'h0fdf00df0ddd00dd >> { n2164, n2163, n2166, n628, n2165, Ni32 }; + assign n2819 = 8'h8a >> { n2167, n2162, n2818 }; + assign n2820 = 64'h0500151115111511 >> { n2169, n2167, n2163, n635, n2166, n2170 }; + assign n2821 = 64'h0fef00ef0eee00ee >> { n2150, n2153, n2156, n695, n2155, Ni32 }; + assign n2822 = 8'ha2 >> { n2236, n2154, n2821 }; + assign n762 = 4'h2 >> { n763, n759 }; + assign n2823 = 64'h0fdf00df0ddd00dd >> { n2164, n2163, n2166, n704, n2165, Ni32 }; + assign n2824 = 8'h8a >> { n2239, n2238, n2823 }; + assign n2825 = 64'h0fdf00df0ddd00dd >> { n2164, n2163, n2166, n695, n2165, Ni32 }; + assign n2826 = 8'ha2 >> { n2240, n2239, n2825 }; + assign n2827 = 64'ha8a0a8a0aaa2a8a0 >> { n2274, n2830, n2278, Pi21, Pi20, n2171 }; + assign n2828 = 32'd2862786720 >> { n2268, n2271, Pi22, Pi20, n2827 }; + assign n2829 = 64'ha0a0a04491919155 >> { n2155, Ni44, Ni40, n2153, n2276, Ni36 }; + assign n2830 = 16'hf1f9 >> { Ni41, Ni32, Ni36, n2829 }; + assign n2831 = 64'hb333b333f777b333 >> { n2328, n2313, n2389, n2379, n758, Pi16 }; + assign n2832 = 32'd1431639381 >> { n2363, n2333, n2831, n2836, n718 }; + assign n763 = 64'h007f00ff007f007f >> { n18, Ni33, Ni34, n624, n622, n671 }; + assign n2833 = 64'hbabbfaffaaaaeaee >> { n2155, n635, Ni35, n2151, n2150, Ni32 }; + assign n2834 = 64'hbbbafffaaaaaeeea >> { n2155, n704, n2233, Ni35, n2150, Ni32 }; + assign n2835 = 64'hff557f55f7557755 >> { n2414, n2412, n2402, Pi20, n624, n748 }; + assign n2836 = 64'ha8a8a0a8a0a8a0a8 >> { n2399, n2401, n776, Pi16, n2835, n2393 }; + assign n2837 = 64'hfbfbaafbbbbbaabb >> { n687, n678, n749, n622, n752, n18 }; + assign n2838 = 64'h3b3b3b3bbb3b3b3b >> { n2416, n2837, n2828, n748, n672, n2417 }; + assign n2839 = 64'h4444444444444404 >> { n2841, n2847, n2852, n2838, n718, Ni10 }; + assign n2840 = 64'haaff80c0aaff0040 >> { Pi25, n18, n776, n694, n622, n2401 }; + assign n2841 = 64'haaaaaaaaaaaaaa2a >> { n2423, n2427, n2844, n2399, n2840, n659 }; + assign n2842 = 64'hbbbbaabbfbfbaafb >> { n658, n646, n752, n622, n749, n18 }; + assign n764 = 64'h7f7f7fff557755ff >> { n18, n679, Ni34, Ni33, n622, n624 }; + assign n2843 = 32'd286331377 >> { n2322, n2323, n2324, n1477, n752 }; + assign n2844 = 32'd2863278762 >> { n2328, n2842, n2314, n2843, n758 }; + assign n2845 = 64'h058d058d058d45cd >> { n713, n18, n2430, n2376, Pi25, Pi20 }; + assign n2846 = 64'h5ddd5ddd55555ddd >> { n2372, n1332, n2845, n624, n2364, n748 }; + assign n2847 = 64'haaaaaaaaaaaa2aaa >> { n2432, n2849, n2846, n2437, n2438, n645 }; + assign n2848 = 64'h1151515199595959 >> { n2435, n2355, n2833, n2181, n2362, n752 }; + assign n2849 = 64'haaaa28aaaaaa20aa >> { n1477, n2436, n2350, n752, n2848, n746 }; + assign n2850 = 64'hffabafabbbababab >> { n2562, n702, n622, n752, n749, n18 }; + assign n2851 = 64'h8888aaaa0008000a >> { n2246, n1332, n750, n749, n2241, n2850 }; + assign n2852 = 16'haaa2 >> { n2439, n2441, n3010, n677 }; + assign n765 = 64'h7f7f7fff557755ff >> { n18, n667, Ni34, Ni33, n622, n624 }; + assign n2853 = 64'hd515d111c505c101 >> { n2195, n2562, n2246, n18, n623, n2201 }; + assign n2854 = 64'hf0ff8088f0ff0088 >> { n708, n18, n623, n2414, n622, n694 }; + assign n2855 = 64'h8088808880880088 >> { n710, n18, n643, n2412, n2401, n2399 }; + assign n2856 = 32'd707406506 >> { Pi19, n2402, n2855, n2854, n659 }; + assign n2857 = 32'd2970685713 >> { Ni30, Ni6, n590, n2127, Ni3 }; + assign n2858 = 64'h406a526a88aa9aaa >> { Ni31, n2130, n2857, n2479, Ni3, Ni4 }; + assign n1081_1 = 8'he4 >> { Ni4, n2858, Ni2 }; + assign n2860 = 64'h0206000403070105 >> { Pi25, n1585, P__cmxig_0, Ni9, Ni10, Ni8 }; + assign n1051_1 = 16'h66a6 >> { Ni7, n2860, P__cmxcl_0, Ni10 }; + assign n2862 = 64'h4666446444644464 >> { Ni35, n2545, Pi15, Ni36, Ni37, Ni38 }; + assign n766 = 64'h007f00ff007f007f >> { n18, Ni33, Ni34, n624, n622, n620 }; + assign n986_1 = 64'hff09ff090909ff09 >> { Ni32, Ni30, n2862, n2547, Ni39, Ni44 }; + assign n2864 = 64'h00030002ffffaaaa >> { Pi17, Ni10, n1111, n2619, n2910, n1058 }; + assign n2865 = 64'h0101000100010001 >> { n2614, n2615, n645, n1084, n1098, n2617 }; + assign n2866 = 64'h8088008888880888 >> { n2865, n1106, n2864, Pi17, n572, n1116 }; + assign n2867 = 64'h0101000155ff00ff >> { n1301, n1170, n1303, n1257, n1246, n1171 }; + assign n2868 = 64'h7f7fff7fff7fff7f >> { n2867, n2634, n748, n2632, n2633, n1295 }; + assign n2869 = 64'hff00fe00fe00fe00 >> { n2868, n672, n1322, n3015, n1314, n2926 }; + assign n2870 = 64'h08aa00aa08aa08aa >> { n1553, n1483, n746, n1564, n1565, n1539 }; + assign n2871 = 64'h8f8f0f8f0f8f0f8f >> { n1566, n2687, n748, n659, n2686, n2870 }; + assign n2872 = 64'h22222222222222a2 >> { n1533, n2953, n2956, n2871, n716, n1579 }; + assign n767 = 8'h80 >> { n723, n720, n624 }; + assign n2873 = 64'heeeeeeee4eeeeeee >> { n1938, n1940, n1941, n2750, n2749, Pi16 }; + assign n2874 = 64'h08880aaa00880aaa >> { n1920, n748, n1587, Ni30, n2769, n1984 }; + assign n2875 = 64'h555555555555d555 >> { n1980, n1983, n2874, n2767, n2768, n645 }; + assign n2876 = 64'h22222222222222a2 >> { n2772, n3003, n2778, n2875, n583, n2015 }; + assign n2877 = 64'hfff7aaa2fff7aaaa >> { n796, n18, n2447, n2448, n2853, P__cmxcl_0 }; + assign n2878 = 32'd2054355570 >> { n677, n3024, n2877, n2450, P__cmxcl_0 }; + assign n1026 = 64'hd0f0d0f0d0d0d0f0 >> { n2811, n2832, n2839, n2878, n716, P__cmxcl_0 }; + assign n2880 = 64'h7777777777775777 >> { Ni34, n719, Pi25, n622, n639, n643 }; + assign n2881 = 64'h44c4c4c4c4c4c4c4 >> { n720, n723, Pi25, n722, n2564, n623 }; + assign n2882 = 64'h3b7f3b7fffff3b7f >> { n734, n623, n2569, n2568, n666, Pi20 }; + assign n768 = 32'd2400161679 >> { n18, Ni33, Ni34, n622, n624 }; + assign n2883 = 64'h0002020200ffffff >> { n659, n2882, n672, n724, n725, n2566 }; + assign n2884 = 64'h0f7f007f07770077 >> { n646, n614, n623, P__cmxig_1, n643, n659 }; + assign n2885 = 64'h2020002022ff00ff >> { n638, n620, n623, n675, P__cmxig_1, n622 }; + assign n2886 = 64'h15153f153f153f15 >> { Ni34, n2557, n666, n639, n643, n672 }; + assign n2887 = 64'h8888880888808800 >> { n620, n640, Pi19, Pi20, n624, n622 }; + assign n2888 = 64'h5f7fff7fdd7fdd7f >> { n18, Ni33, Ni34, n622, n701, n699 }; + assign n2889 = 64'hfffdfffdfdfdfffd >> { n2573, n2888, Pi25, n712, n714, n700 }; + assign n2890 = 32'd2282258432 >> { n694, n701, Pi16, n622, n624 }; + assign n2891 = 32'd1568136695 >> { Ni33, Ni34, n18, n2890, n776 }; + assign n2892 = 64'hfdfdfdfdfffdfdfd >> { n787, n746, Pi16, n788, n789, n2580 }; + assign n769 = 4'h2 >> { n18, n624 }; + assign n2893 = 64'h444a404a440a000a >> { n675, n640, n757, n756, n624, Ni34 }; + assign n2894 = 64'h64ff44ff64ff64ff >> { n18, Ni33, n2897, n622, Ni34, n2893 }; + assign n2895 = 64'hf0e0f0e0e0e0f0e0 >> { n760, n2894, n794, n3038, n2899, n716 }; + assign n2896 = 64'hfca8fc88fca0fc00 >> { n687, n660, Ni34, n745, n747, n622 }; + assign n2897 = 64'h7070f070f070f070 >> { Ni33, n622, n18, n3040, n2896, n624 }; + assign n2898 = 64'h0003aaff0203aaff >> { n614, n757, n769, Ni34, n767, n744 }; + assign n2899 = 64'h80808080aa808080 >> { Pi20, n3043, n2898, n2584, n775, n2578 }; + assign n2900 = 64'h0515051515150515 >> { n985, n1057, n752, n759, n1069, n1073 }; + assign n2901 = 64'hfff7f7f7ff775555 >> { n623, n632, n894, n1003, n1057, n2606 }; + assign n2902 = 64'h4040404040405540 >> { n2605, Ni10, n3047, n2908, n3049, n1083 }; + assign n770 = 32'd2155905024 >> { Ni34, n708, n747, n624, n728 }; + assign n2903 = 64'h0011101101111111 >> { n911, n846, n758, Pi20, n936, n1064 }; + assign n2904 = 64'h0a2a0a2a2a2a0a2a >> { n1086, n1087, n749, n745, n1115, n1058 }; + assign n2905 = 64'h08aa00aa88aa80aa >> { n967, n2903, n754, Pi16, n1057, n2904 }; + assign n2906 = 64'h5fdf5fdf1b9b5fdf >> { n965, n963, n1063, n643, n1057, Pi15 }; + assign n2907 = 64'h77dfffdf57dfdfdf >> { n623, n1079, n2906, n2613, Pi15, n932 }; + assign n2908 = 64'hff00f700f700f700 >> { Pi16, n2907, Ni10, n1080, Pi17, n2612 }; + assign n2909 = 64'h4444445540404055 >> { n924, n864, n925, Ni40, n923, n866 }; + assign n2910 = 64'h7070f070f070f070 >> { n2909, n1091, n623, n672, n2620, n2621 }; + assign n2911 = 64'haae6eee6a2e6e6e6 >> { n1271, n1260, n585, n1158, n1263, Pi15 }; + assign n2912 = 64'hf0f7707770777077 >> { n2626, n1269, n776, n1252, n748, Pi15 }; + assign n771 = 16'h8880 >> { Ni34, n655, n728, n772 }; + assign n2913 = 64'h0101ab010001aa01 >> { n1172, n2625, n2911, n2920, n1239, Pi15 }; + assign n2914 = 64'h5ddd7fff7fff7fff >> { n1258, n2623, n1270, n2627, Pi15, n1252 }; + assign n2915 = 32'd4042848504 >> { n2914, n746, Pi16, n2913, n2912 }; + assign n2916 = 64'hff557f55f7557755 >> { n1284, n1271, n1252, n585, n624, n776 }; + assign n2917 = 32'd1431655773 >> { n1273, n1280, n2629, n2916, n645 }; + assign n2918 = 64'hc8c8c8c888c8c8c8 >> { n2631, n2917, n2915, n582, Ni10, n1137 }; + assign n2919 = 64'h0101000155ff00ff >> { n1251, n1170, n1241, n1246, n1257, n1171 }; + assign n2920 = 16'h2aaa >> { n2919, n1252, n2622, n748 }; + assign n2921 = 64'hdd0ddd0d0000dd0d >> { n1290, n1251, n1291, n1244, n1215, n1241 }; + assign n2922 = 64'h44eee4ee04aea4ae >> { n1217, n1179, n1287, n1248, n2921, Pi17 }; + assign n772 = 4'h8 >> { n745, n624 }; + assign n2923 = 64'h0a208aa88aa88aa8 >> { n2630, n624, Pi17, n2922, Pi19, n1252 }; + assign n2924 = 64'h0001010100ff11ff >> { n1305, Ni32, n1299, n1246, n1208, n1205 }; + assign n2925 = 64'h5ddd7fff7fff7fff >> { n2635, n2924, n1311, n1312, Pi17, n1295 }; + assign n2926 = 64'haaaaaaaa0880aaaa >> { n2637, n1313, Pi17, Pi19, n2925, n659 }; + assign n2927 = 64'h084c2a6e195d3b7f >> { n1224, n1222, n1282, n1283, Pi27, Pi20 }; + assign n2928 = 64'h1111133313331333 >> { n2643, n751, n2927, n756, n2931, n624 }; + assign n2929 = 32'd35791394 >> { n3055, n1327, n2928, n2935, n1344 }; + assign n2930 = 32'd33686103 >> { n1148, n1140, n1154, n1157, Pi20 }; + assign n2931 = 64'h8888088880880088 >> { Ni32, n1246, n2930, Pi27, n747, n624 }; + assign n2932 = 32'd33686103 >> { n1208, n1205, n1210, n1212, Pi20 }; + assign n773 = 32'd572695074 >> { n658, n769, n622, n774, n759 }; + assign n2933 = 64'h8888088880880088 >> { Ni32, n1246, n2932, Pi27, n745, n624 }; + assign n2934 = 64'h2a227f777f777f77 >> { n1336, n2649, n1326, n1288, n1335, Pi16 }; + assign n2935 = 64'h0002020200222222 >> { n2934, n746, n2644, n748, n1339, n2648 }; + assign n2936 = 64'h44eee4ee04aea4ae >> { n1364, n1350, n1368, n1371, n2656, Pi17 }; + assign n2937 = 64'haaaa2222888800a0 >> { Pi17, Pi19, n1372, n1373, n2936, n1374 }; + assign n2938 = 64'h0202000200020002 >> { n2937, n1366, n677, n1389, n2941, n1376 }; + assign n2939 = 64'hf3f351f373735173 >> { n1353, n1362, n746, n2657, n748, n1371 }; + assign n2940 = 32'd2324335114 >> { n1354, n1296, n755, n1385, n1366 }; + assign n2941 = 64'hf700f700ff00f700 >> { n2658, n746, n645, n1386, n2940, n2939 }; + assign n2942 = 32'd2324335114 >> { n1351, Pi27, n755, n1375, n1402 }; + assign n774 = 32'd353703253 >> { n671, n732, n624, n728, Ni34 }; + assign n2943 = 64'hf3f351f373735173 >> { n1350, n1364, n746, n2667, n748, n1399 }; + assign n2944 = 64'hf700f700ff00f700 >> { n1418, n746, n677, n1419, n2942, n2943 }; + assign n2945 = 64'h0526042605220022 >> { n1211, n1207, n1400, n1206, n1401, n1246 }; + assign n2946 = 64'h6f6fff6f4f4fff4f >> { n1147, n1359, n1399, n1402, n1246, n2945 }; + assign n2947 = 64'hff00f700f700f700 >> { n2946, n746, n659, n1420, n2669, n2670 }; + assign n2948 = 64'hf3f351f373735173 >> { n1353, n1362, n746, n2673, n748, n1443 }; + assign n2949 = 64'hff7fff7fffffff7f >> { n2674, n746, n1451, n1437, n1452, n2948 }; + assign n2950 = 64'hff00fd00fd00fd00 >> { n2949, n645, n582, n1458, n2676, n2672 }; + assign n2951 = 64'h0008080800aa88aa >> { n1542, Ni32, n1553, n1537, n1504, n1539 }; + assign n2952 = 64'h01010001ffff00ff >> { n1547, n1502, n1552, n1537, n1228, n1503 }; + assign n775 = 32'd353719573 >> { n727, n18, n646, n624, Ni34 }; + assign n2953 = 64'hd0d0f0d0f0d0f0d0 >> { n2951, n2952, n746, n672, n1556, n2684 }; + assign n2954 = 64'h084c2a6e195d3b7f >> { n1498, n1574, n1499, n1573, Pi20, n597 }; + assign n2955 = 32'd572662434 >> { n1575, n1576, n1577, n758, n1539 }; + assign n2956 = 64'haa2a2a2a2a2a2a2a >> { n748, n2954, n624, n2689, n2955, n645 }; + assign n2957 = 64'h0004040400ff55ff >> { n1588, n1190, n1586, n1265, n1538, n1481 }; + assign n2958 = 64'h80008888f000ffff >> { n746, n758, n2957, n2692, n1593, n2693 }; + assign n2959 = 64'h00ff80ff80ff80ff >> { n2690, n748, n659, n1589, n1592, n2958 }; + assign n2960 = 64'hfc54fc54fc545454 >> { n1522, n1585, n1555, Pi17, n1589, n1263 }; + assign n2961 = 64'hf0e0f0e0e0e0f0e0 >> { n1491, n1586, n1597, n2960, Pi17, Pi19 }; + assign n2962 = 64'h0101000155ff00ff >> { n1586, n1504, n1587, n1228, n1503, Ni32 }; + assign n776 = 4'h8 >> { Pi17, Pi19 }; + assign n2963 = 64'h8880aaa08800aaa0 >> { n1523, n1263, n1585, n1163, n1562, n1540 }; + assign n2964 = 64'h08aa00aa08aa08aa >> { n1587, n1506, n748, n1601, n1602, n2963 }; + assign n2965 = 64'hd0d0f0d0f0d0f0d0 >> { n2701, n2962, n746, n672, n2703, n2964 }; + assign n2966 = 64'h0101000155ff00ff >> { n1607, n1170, n1609, n1537, n1257, n1509 }; + assign n2967 = 64'h0202000200020002 >> { n2966, n1640, n747, n1638, n1631, n1633 }; + assign n2968 = 64'hd0d0f0d0f0d0f0d0 >> { n1624, n2967, n806, n1641, n1604, n2705 }; + assign n2969 = 64'hff007f00f7007700 >> { n1493, n1494, n1163, Pi20, n624, Pi19 }; + assign n2970 = 64'h0202000200020002 >> { n2969, n1650, n645, n1645, n1643, n2710 }; + assign n2971 = 64'hdddddddfddfdddff >> { n1684, Ni30, n1734, n1296, n1686, n1263 }; + assign n2972 = 8'hf7 >> { n2720, n2716, n2971 }; + assign n777 = 32'd2324299914 >> { n708, Ni34, n624, n738, n778 }; + assign n2973 = 64'h0202000200020002 >> { n1768, n2726, n746, n1687, n1718, n1771 }; + assign n2974 = 64'h08ff08ff00ff08ff >> { n1773, n1299, n659, n1715, n2973, n2725 }; + assign n2975 = 64'hff00fd00fd00fd00 >> { n2972, n645, n1322, n2718, n2722, n2974 }; + assign n2976 = 64'hbbb9bb31bab8ba30 >> { n1737, n1684, n1735, Ni30, n1296, Pi20 }; + assign n2977 = 32'd2290657416 >> { n1686, n624, n2976, n1736, n746 }; + assign n2978 = 64'haabbabbbaabfafbf >> { n1711, n1706, n1325, n1684, n1326, n1686 }; + assign n2979 = 64'hf5ffb1bbb1bbb1bb >> { n1798, n2978, n746, n1796, n748, Pi16 }; + assign n2980 = 64'hf0202020f2222222 >> { n1720, n1711, n623, n659, n1719, n699 }; + assign n2981 = 64'h3131313111313131 >> { n1677, n659, n1706, n1705, n1828, n643 }; + assign n2982 = 64'h0008000800000008 >> { n1686, n2980, n1822, n1826, n2981, Pi17 }; + assign n778 = 8'hd5 >> { n622, n624, Ni34 }; + assign n2983 = 64'h5050555500400044 >> { n1835, n677, n659, n1842, n1836, Pi17 }; + assign n2984 = 64'h1f111f115f551f11 >> { n1837, n645, Pi19, n1840, n2983, n1830 }; + assign n2985 = 16'ha888 >> { n624, n2984, n1825, n583 }; + assign n2986 = 32'd34218538 >> { n1684, n1248, n1244, n1737, n2741 }; + assign n2987 = 64'h3f3b3f3b2a2a3f3b >> { n1738, n1263, n2986, n1844, n746, n1686 }; + assign n2988 = 16'haaa2 >> { n1846, n2743, n2987, n645 }; + assign n2989 = 32'd17895263 >> { n1251, Ni30, n1241, n1684, n1692 }; + assign n2990 = 64'hafabafabafababab >> { Ni30, n1698, n1248, n1686, n2989, n1861 }; + assign n2991 = 64'h0f008f882f22afaa >> { n1719, n1717, n1244, n1859, n585, n1263 }; + assign n2992 = 64'h0020002220202222 >> { n746, n1248, n2990, n1773, n1844, n1860 }; + assign n779 = 32'd1440044437 >> { n18, n615, n624, n622, Ni34 }; + assign n2993 = 64'h2a222a22aaaa2a22 >> { n1686, n2991, Pi17, n1862, n2992, n659 }; + assign n2994 = 64'h007700f7007f00ff >> { n1791, n1788, n1869, Pi20, n624, n585 }; + assign n2995 = 64'haaaaaaaaaaaa2aaa >> { n1844, n1865, n2994, n1868, n2745, n677 }; + assign n2996 = 64'h4544050445444544 >> { n2766, n1835, n1720, n659, n1955, n1963 }; + assign n2997 = 64'h02ff00ff02ff02ff >> { n2761, n1836, n672, n1964, n1966, n2996 }; + assign n2998 = 64'h88aa082a80a20022 >> { n1741, n1739, n1841, Pi20, n585, n746 }; + assign n2999 = 32'd35791394 >> { n2998, n624, Pi25, n1963, n1948 }; + assign n3000 = 64'h555a565a556a666a >> { n1751, n1746, n1440, n1442, n1684, n1443 }; + assign n3001 = 64'h9091f0f51011f0f5 >> { n1833, n748, n2765, n1842, n3000, n1443 }; + assign n3002 = 64'h0202000200020002 >> { n1999, n2775, n746, n1983, n2001, n1998 }; + assign n780 = 64'h15559555d5559555 >> { Ni33, n18, n713, n624, n622, Ni34 }; + assign n3003 = 64'hff007f007f007f00 >> { n1586, Ni30, n659, n3002, n2773, n2774 }; + assign n3004 = 64'h8088a0aa0088a0aa >> { n1915, n748, n1553, n1902, n2787, n2046 }; + assign n3005 = 64'h2022202200222022 >> { n1914, n748, n1552, n1903, n2025, n3004 }; + assign n3006 = 64'h3133f5f70033f5f7 >> { n1982, Ni30, n1547, n1874, n1552, n1728 }; + assign n3007 = 64'h08aa08aa00aa08aa >> { n1921, n1552, n748, n2024, n2049, n2788 }; + assign n3008 = 64'haaaaaaaaaaaaaa2a >> { n2025, n2030, n2050, n3007, n3006, n645 }; + assign n3009 = 64'hfff7f7f7ff775555 >> { n18, Pi25, n796, n2195, n776, n624 }; + assign n3010 = 32'd570556930 >> { n2230, n2851, n748, n2201, n3009 }; + assign n3011 = 64'h22e2eeee00e0eeee >> { n1245, n1326, n1267, n1268, Pi16, n2642 }; + assign n3012 = 64'h048c159d26ae37bf >> { n1288, n1179, n1289, n1177, Pi20, n1296 }; + assign n781 = 64'h1111110111011101 >> { n655, n778, n768, n745, n771, n782 }; + assign n3013 = 64'hfb73ea62d951c840 >> { n1286, n1218, n1285, n1220, Pi20, n1296 }; + assign n3014 = 64'ha8a90001aaa9aa01 >> { n3013, n3012, n746, n748, n1294, n1295 }; + assign n3015 = 64'haa82aaaaaa02aaaa >> { n624, n1321, n1319, n1295, n3014, n677 }; + assign n3016 = 16'h5551 >> { n1717, n1721, n755, n1934 }; + assign n3017 = 64'h1111011110110011 >> { n1717, n1738, n755, Pi16, Ni14, n1926 }; + assign n3018 = 64'hffeb5541ffef5545 >> { n3016, n3058, Ni14, Pi16, n2873, Pi15 }; + assign n3019 = 64'hbfbfbfbfbfbf15bf >> { n1975, n1973, n2996, n3001, n2999, Pi15 }; + assign n3020 = 64'h2002ffff2222ffff >> { n3019, n582, Pi15, Pi16, n2764, n2997 }; + assign n3021 = 64'hff00f700f700f700 >> { n3018, n2754, n718, n1870, n3020, n1977 }; + assign n3022 = 64'hfc0c5404dc0c5404 >> { n687, n2286, n693, n622, n18, n643 }; + assign n782 = 64'haaaa2a222a222a22 >> { n658, Ni34, n624, n731, n778, n759 }; + assign n3023 = 64'h777f777f777fffff >> { n622, n2187, Pi19, n2828, n2449, n3022 }; + assign n3024 = 32'd131586 >> { n672, n3023, n2444, n2856, Pi17 }; + assign n3025 = 32'd2854914570 >> { n673, n675, Pi19, Pi20, n2887 }; + assign n3026 = 32'd429481437 >> { Pi25, n18, Ni33, n3025, Ni34 }; + assign n3027 = 64'h73737373fb737373 >> { n724, n2880, n2881, n3026, Pi16, Pi15 }; + assign n3028 = 64'h5500570257025702 >> { n2889, n645, n3027, n2576, n736, Pi17 }; + assign n3029 = 64'haaa20a0288000800 >> { n2883, n716, n2572, Ni34, Pi17, n3028 }; + assign n3030 = 64'h3b3b3b3bbb3b3b3b >> { P__cmxig_1, n651, n622, n638, n659, n2556 }; + assign n3031 = 64'h8080008000800080 >> { n2558, n2885, n677, n2555, n624, n716 }; + assign n3032 = 64'h2aaaaaaaaaaaaaaa >> { n3030, P__cmxcl_0, n3031, n2884, n2886, Ni34 }; + assign n783 = 64'h15559555d5559555 >> { Ni33, n18, n626, n624, n622, Ni34 }; + assign n3033 = 64'h111111bb010101ab >> { n619, n712, n714, Ni36, n2561, Pi15 }; + assign n3034 = 64'heb414141ab010101 >> { n707, n700, n3033, Pi15, n2560, Pi16 }; + assign n3035 = 64'h50d8d8d8d8d8d8d8 >> { P__cmxcl_0, n716, n3034, n3032, Ni34, Pi17 }; + assign n3036 = 64'h0040004450505555 >> { n757, n756, n767, n783, n779, n784 }; + assign n3037 = 64'h8888088880880088 >> { n777, n780, n748, Pi16, n3036, n781 }; + assign n3038 = 64'h0a8a0a8a8a8a0a8a >> { Pi20, n3037, n2892, n792, n2891, Ni10 }; + assign n3039 = 64'h444a404a440a000a >> { n702, n648, n759, n751, n624, Ni34 }; + assign n3040 = 64'h828a828a8a8a828a >> { Ni33, n18, n622, Ni34, n3039, Pi20 }; + assign n3041 = 16'h8088 >> { n18, Ni33, n622, n624 }; + assign n3042 = 64'h01110f5f55555555 >> { n3041, n751, n626, n756, n713, Ni34 }; + assign n784 = 32'd2621472 >> { n622, n18, Ni34, n655, n772 }; + assign n3043 = 16'h0002 >> { n770, n771, n773, n3042 }; + assign n3044 = 64'hf7b3d591e6a2c480 >> { n671, n620, n679, n2562, Pi17, Pi16 }; + assign n3045 = 64'h55f7f5f755777577 >> { n1060, n922, n749, n1057, n752, n747 }; + assign n3046 = 64'h8888088880880088 >> { n1074, n1072, n754, Pi20, n3045, n1058 }; + assign n3047 = 64'hffffff7fff7fff7f >> { n2603, n745, n1070, n3046, Pi15, n2900 }; + assign n3048 = 64'h6eee2aaa2aaa2aaa >> { n1077, n2608, n2607, n1076, n932, Pi16 }; + assign n3049 = 64'heffeefefeefeeeef >> { n2901, n3048, Pi15, Pi16, n2610, Pi17 }; + assign n3050 = 64'h808080808080ff80 >> { n1717, n751, n1133, n624, n745, n2739 }; + assign n3051 = 64'h080a000200020002 >> { n1799, n1800, n1793, n1803, n751, n2740 }; + assign n3052 = 64'hf700f700ff00f700 >> { n1686, n3050, Ni14, n1801, n3051, n2979 }; + assign n785 = 64'ha080208800002088 >> { Ni33, n18, n651, n622, Ni34, n772 }; + assign n3053 = 32'd1970632191 >> { n1202, n1197, n1162, Pi16, n1323 }; + assign n3054 = 32'd1171211589 >> { n1278, n1277, n1333, n1198, n1325 }; + assign n3055 = 64'h4055405500554055 >> { n3054, Pi16, n758, n3053, n3011, n2933 }; + assign n3056 = 64'he6a2c480f7b3d591 >> { n1859, n1737, n1770, n1735, Pi20, Pi16 }; + assign n3057 = 64'h80880000a0882000 >> { n1838, n3056, Pi16, n746, n1296, n624 }; + assign n3058 = 64'hf333fbbbf777ffff >> { n2748, n2751, n3057, Pi25, n3017, Pi16 }; + assign n3059 = 64'h8888088880880088 >> { n667, n673, Pi19, Pi16, n622, n624 }; + assign n3060 = 64'ha969ad2d6569252d >> { Ni33, n3044, n18, Ni34, n3059, Pi19 }; + assign n3061 = 32'd2868816574 >> { Pi17, Pi20, n3060, Pi19, n2584 }; + assign n786 = 32'd2862785186 >> { n778, n651, n768, n745, Pi20 }; + assign n787 = 64'h15559555d5559555 >> { Ni33, n18, n633, n624, n622, Ni34 }; + assign n788 = 64'h2a220a002a222a22 >> { n778, n647, n624, n726, n768, n759 }; + assign n789 = 32'd705309226 >> { n778, n719, n790, n768, n757 }; + assign n790 = 64'h7f5f77dfffff77df >> { Ni33, n18, n719, n622, Ni34, n624 }; + assign n791 = 64'h15559555d5559555 >> { Ni33, n18, n715, n624, n622, Ni34 }; + assign n792 = 4'h8 >> { n716, Pi15 }; + assign n793 = 4'h8 >> { n776, Pi16 }; + assign n794 = 32'd2315946634 >> { Pi16, n805, n776, n795, n797 }; + assign n795 = 64'h007f00ff007f007f >> { n18, Ni33, Ni34, n624, n622, n693 }; + assign n796 = 4'h8 >> { n742, n622 }; + assign n797 = 16'h4445 >> { n747, n745, n768, Pi15 }; + assign n798 = 8'h80 >> { n624, n776, Pi16 }; + assign n799 = 32'd2324299914 >> { n801, n759, n751, n800, Pi20 }; + assign n800 = 64'h15559555d5559555 >> { Ni33, n18, n702, n624, n622, Ni34 }; + assign n801 = 64'h15559555d5559555 >> { Ni33, n18, n648, n624, n622, Ni34 }; + assign n802 = 64'h15559555d5559555 >> { Ni33, n18, n687, n624, n622, Ni34 }; + assign n803 = 64'h15559555d5559555 >> { Ni33, n18, n640, n624, n622, Ni34 }; + assign n804 = 64'h15559555d5559555 >> { Ni33, n18, n693, n624, n622, Ni34 }; + assign n805 = 64'h15559555d5559555 >> { Ni33, n18, n742, n624, n622, Ni34 }; + assign n806 = 4'h2 >> { Pi15, n716 }; + assign n807 = 64'hf0e0f0e0f0e0e0e0 >> { n808, n1027, n716, n717, n2902, n2866 }; + assign n808 = 64'h5151515151510051 >> { n2592, n809, n2595, n2598, n2602, Ni10 }; + assign n809 = 32'd3149642507 >> { n874, n898, n908, n837, n810 }; + assign n810 = 8'h8a >> { n2589, n811, n834 }; + assign n811 = 8'h8a >> { n824, n812, n745 }; + assign n812 = 4'h8 >> { n813, n662 }; + assign n813 = 16'h1101 >> { n815, n814, Ni37, Ni38 }; + assign n814 = 64'h0a4e0a4e0a4e1b5f >> { Ni44, Ni43, Ni48, Ni46, Ni47, Ni45 }; + assign n815 = 8'h01 >> { Ni47, Ni42, Ni45 }; + assign n816 = 64'hff7f0000ff7d0000 >> { Ni41, n817, Ni43, Ni44, Ni42, n818 }; + assign n817 = 16'h2777 >> { Ni47, Ni48, Ni46, Ni45 }; + assign n818 = 16'hdd8d >> { Ni48, Ni47, Ni46, Ni45 }; + assign n819 = 8'h1b >> { Ni41, n820, n822 }; + assign n820 = 64'h1b5f1b5f0a4e1b5f >> { Ni43, Ni44, Ni48, Ni46, Ni47, Ni45 }; + assign n821 = 8'h01 >> { Ni47, Ni42, Ni45 }; + assign n822 = 16'h0001 >> { Ni47, Ni42, Ni43, Ni45 }; + assign n823 = 4'h2 >> { Ni37, Ni38 }; + assign n824 = 64'h88088808aaaa8808 >> { n621, n828, Ni40, n819, n816, n825 }; + assign n825 = 64'hd0ddd0ddf0ffd0dd >> { n815, n814, Ni37, n826, Ni38, n827 }; + assign n826 = 64'hcceedcfecdefddff >> { Ni39, Ni48, Ni46, Ni47, Ni38, Ni45 }; + assign n827 = 8'h01 >> { Ni36, Ni39, Ni37 }; + assign n828 = 16'h7273 >> { Ni39, Ni36, Ni38, Ni37 }; + assign n829 = 4'h8 >> { n813, n662 }; + assign n830 = 4'h2 >> { n822, n820 }; + assign n831 = 64'haaaaaabb0828aabb >> { Ni43, n818, Ni41, Ni44, Ni42, n817 }; + assign n832 = 32'd2829625504 >> { Ni40, n830, n828, n831, n825 }; + assign n833 = 16'h222a >> { n830, Ni40, n831, n621 }; + assign n834 = 4'h8 >> { n835, n624 }; + assign n835 = 4'h2 >> { Pi25, n836 }; + assign n836 = 16'h0001 >> { Ni33, Ni30, Ni32, Ni31 }; + assign n837 = 64'h0002000000020002 >> { n873, n869, n862, n838, n854, n861 }; + assign n838 = 32'd2863311402 >> { n846, n850, n852, n839, n759 }; + assign n839 = 16'h1115 >> { n845, n843, n840, n841 }; + assign n840 = 4'h2 >> { Pi25, n624 }; + assign n841 = 32'd1423725820 >> { n842, Pi22, n844, n843, Pi21 }; + assign n842 = 8'h02 >> { Ni48, Ni45, Ni47 }; + assign n843 = 16'haaa8 >> { Ni31, Ni30, Ni32, Ni33 }; + assign n844 = 32'd16842753 >> { Ni46, Ni45, Ni31, Ni30, Ni32 }; + assign n845 = 64'hddfd00000dfd0000 >> { Ni38, Ni33, n826, Ni37, n815, n814 }; + assign n846 = 16'haaa2 >> { n849, n848, n847, Ni33 }; + assign n847 = 16'hddd8 >> { n820, n821, n826, Ni37 }; + assign n848 = 16'h5111 >> { n815, Ni41, n814, n828 }; + assign n849 = 16'ha222 >> { n815, Ni41, n814, n621 }; + assign n850 = 32'd705309226 >> { n828, n621, n825, n816, n851 }; + assign n851 = 4'h8 >> { n836, Ni34 }; + assign n852 = 16'h0213 >> { n853, n845, n843, Ni34 }; + assign n853 = 64'h0202aa020002aa02 >> { Ni38, n826, Ni37, n820, n821, n836 }; + assign n854 = 32'd2728569506 >> { n855, n851, n856, n852, n860 }; + assign n855 = 16'h88a8 >> { n621, n828, n831, n825 }; + assign n856 = 16'haaa2 >> { n859, n857, n847, Ni33 }; + assign n857 = 16'h0111 >> { Ni41, n858, n814, n828 }; + assign n858 = 16'h0001 >> { Ni47, Ni42, Ni43, Ni45 }; + assign n859 = 16'h0222 >> { Ni41, n858, n814, n621 }; + assign n860 = 4'h8 >> { n754, n757 }; + assign n861 = 8'hea >> { Pi20, n839, Pi17 }; + assign n862 = 64'hf0d0f0d0d0d0f0d0 >> { n812, n824, n851, n745, n863, n865 }; + assign n863 = 32'd2720178690 >> { Ni40, Ni41, n858, n814, n864 }; + assign n864 = 8'h08 >> { Ni37, Ni36, Ni33 }; + assign n865 = 64'h0202020202020213 >> { n867, n853, n866, n845, n843, Ni34 }; + assign n866 = 32'd134744106 >> { n821, n820, n826, Ni37, Ni33 }; + assign n867 = 32'd2720178690 >> { Ni40, Ni41, n858, n814, n868 }; + assign n868 = 32'd2290657416 >> { Ni36, Ni35, Ni39, Ni38, Ni33 }; + assign n869 = 64'h0202020202022202 >> { n833, n829, n832, n851, n870, n871 }; + assign n870 = 32'd33694210 >> { Ni41, Ni40, n858, n814, n864 }; + assign n871 = 64'h0202020202020213 >> { n872, n853, n866, n845, n843, Ni34 }; + assign n872 = 32'd33694210 >> { Ni41, Ni40, n858, n814, n868 }; + assign P__cmxig_1 = 4'h8 >> { Ni33, n18 }; + assign n873 = 4'h8 >> { n754, n756 }; + assign n874 = 64'h4505450545454505 >> { n887, n745, n875, n897, n754, Pi17 }; + assign n875 = 16'haaa2 >> { n876, n884, n852, n757 }; + assign n876 = 16'haaa2 >> { n883, n879, n877, Ni33 }; + assign n877 = 16'hddd8 >> { n820, n821, n826, Ni37 }; + assign n878 = 8'h02 >> { Ni36, Ni37, Ni39 }; + assign n879 = 16'h0901 >> { n880, n881, n814, n858 }; + assign n880 = 64'h0302030301000101 >> { Ni46, Ni47, Ni48, Ni42, Ni41, Ni45 }; + assign n881 = 16'h7372 >> { Ni39, Ni36, Ni38, Ni37 }; + assign n882 = 16'h0002 >> { Ni47, Ni43, Ni45, Ni44 }; + assign P__cmxig_0 = 4'h2 >> { Ni33, n18 }; + assign n883 = 16'h8202 >> { n880, n858, n814, n621 }; + assign n884 = 32'd705309226 >> { n881, n621, n885, n886, n851 }; + assign n885 = 32'd3452820941 >> { n815, n814, n878, n826, Ni37 }; + assign n886 = 8'h2a >> { Ni41, n822, n820 }; + assign n887 = 64'h0002000202020002 >> { n888, n890, n851, n891, n894, n852 }; + assign n888 = 4'h8 >> { n813, n662 }; + assign n889 = 16'heae2 >> { Ni40, Ni41, n822, n820 }; + assign n890 = 16'h88a8 >> { n621, n881, n889, n885 }; + assign n891 = 8'ha8 >> { n893, n892, n864 }; + assign n892 = 4'h8 >> { n815, Ni41 }; + assign P__cmxcl_0 = 4'h1 >> { Ni3, Ni2 }; + assign n893 = 16'h9111 >> { n880, Ni40, n814, n858 }; + assign n894 = 16'heeea >> { n893, n892, n895, n866 }; + assign n895 = 4'h2 >> { n896, Ni33 }; + assign n896 = 32'd1431655761 >> { Ni36, Ni39, Ni37, Ni35, Ni38 }; + assign n897 = 16'h1115 >> { n845, n843, n840, n2590 }; + assign n898 = 32'd2324343434 >> { n899, n745, n904, n900, n834 }; + assign n899 = 4'h2 >> { n888, n890 }; + assign n900 = 4'h2 >> { n901, n756 }; + assign n901 = 32'd133130 >> { n813, n903, n902, n662, n885 }; + assign n902 = 32'd1157973317 >> { Ni40, Ni41, n820, n822, n881 }; + assign P__cmx1ad_9 = 4'h8 >> { n571, P__cmxcl_0 }; + assign n903 = 32'd2315946634 >> { Ni40, Ni41, n820, n822, n621 }; + assign n904 = 64'h0055045504550455 >> { n621, n906, n759, n907, n885, n905 }; + assign n905 = 32'd705309226 >> { n881, n621, n885, n886, n757 }; + assign n906 = 16'h5515 >> { Ni42, Ni41, n817, n820 }; + assign n907 = 32'd286327057 >> { Ni42, Ni41, n817, n820, n881 }; + assign n908 = 64'h8a0a8a0a8a0aaa2a >> { n1002, n915, n901, n873, n851, n910 }; + assign n909 = 8'hea >> { n893, n895, n866 }; + assign n910 = 64'h1515151515155515 >> { n914, n911, n852, n759, n754, Pi20 }; + assign n911 = 16'haaa2 >> { n913, n912, n877, Ni33 }; + assign n912 = 64'h1000554410105554 >> { n882, n814, Ni41, n818, Ni42, n881 }; + assign n571 = 8'h80 >> { n572, Ni14, Ni13 }; + assign n913 = 64'h2000aa882020aaa8 >> { n882, n814, Ni41, n818, Ni42, n621 }; + assign n914 = 32'd2862785186 >> { n906, n621, n907, n885, n851 }; + assign n915 = 4'h8 >> { n864, n893 }; + assign n916 = 64'hc4c4c4c4c4c444c4 >> { n927, n917, n921, n754, n625, n897 }; + assign n917 = 8'h8a >> { n920, n918, n851 }; + assign n918 = 4'h8 >> { n813, n681 }; + assign n919 = 16'he2ea >> { Ni40, Ni41, n822, n820 }; + assign n920 = 16'h88a8 >> { n621, n881, n919, n885 }; + assign n921 = 4'h2 >> { n922, n852 }; + assign n922 = 32'd3469659886 >> { n924, Ni40, n923, n866, n925 }; + assign n572 = 4'h1 >> { Ni11, Ni12 }; + assign n923 = 8'h4e >> { Ni41, n814, n858 }; + assign n924 = 4'h7 >> { n880, n814 }; + assign n925 = 4'h2 >> { n926, Ni33 }; + assign n926 = 32'd1431655764 >> { Ni37, Ni36, Ni39, Ni35, Ni38 }; + assign n927 = 16'h222a >> { n924, Ni40, n923, n864 }; + assign n928 = 32'd572662434 >> { n936, n929, n934, n699, n932 }; + assign n929 = 4'h2 >> { n930, n851 }; + assign n930 = 32'd236913685 >> { Ni36, n931_1, n819, Ni38, n813 }; + assign n931_1 = 4'h2 >> { n826, Ni37 }; + assign n932 = 4'h1 >> { n2590, n933 }; + assign P__cmx1ad_12 = 4'h2 >> { Pi27, P__cmx1ad_9 }; + assign n933 = 32'd134744200 >> { Pi22, n842, Pi21, n844, Pi20 }; + assign n934 = 64'h0202020202020213 >> { n935, n853, n866, n845, n843, Ni34 }; + assign n935 = 32'd2156396552 >> { Ni41, n814, n858, Ni33, Ni38 }; + assign n936 = 8'h08 >> { n923, Ni33, n937 }; + assign n937 = 8'ha2 >> { Ni38, Ni37, Ni36 }; + assign n938 = 8'h2a >> { n839, n939, n644 }; + assign n939 = 32'd33694210 >> { n940, n941_1, n851, n942, n943 }; + assign n940 = 4'h8 >> { n813, n681 }; + assign n941_1 = 64'h08880888aaaa0888 >> { n621, n828, Ni40, n819, n816, n825 }; + assign n942 = 16'h222a >> { n814, Ni40, n923, n864 }; + assign P__cmx1ad_14 = 8'h28 >> { Pi26, Pi27, P__cmx1ad_9 }; + assign n943 = 64'h0202020202020213 >> { n944, n853, n866, n845, n843, Ni34 }; + assign n944 = 32'd2718081570 >> { Ni40, Ni41, n858, n814, n945 }; + assign n945 = 32'd2290649256 >> { Ni36, Ni35, Ni39, Ni38, Ni33 }; + assign n946_1 = 16'h3210 >> { n941_1, n920, n918, Pi20 }; + assign n947 = 8'h54 >> { n843, n845, Pi25 }; + assign n948 = 4'h2 >> { Pi16, Pi17 }; + assign n949 = 64'h0202020202022202 >> { n952, n950, n951_1, n851, n953, n955 }; + assign n950 = 4'h8 >> { n813, n681 }; + assign n951_1 = 32'd2829101224 >> { Ni40, n830, n828, n831, n825 }; + assign n952 = 16'h22a2 >> { n830, Ni40, n831, n621 }; + assign P__cmx0ad_9 = 4'h8 >> { P__cmxcl_0, n576 }; + assign n953 = 4'h2 >> { n954, n864 }; + assign n954 = 16'heeea >> { Ni41, Ni40, n858, n814 }; + assign n955 = 64'h0202020202020213 >> { n956_1, n853, n866, n845, n843, Ni34 }; + assign n956_1 = 32'd33686050 >> { Ni41, Ni40, n858, n814, n945 }; + assign n957 = 64'hc4c4c4c4c4c444c4 >> { n965, n958, n962, n754, n625, n897 }; + assign n958 = 32'd2324343434 >> { n960, n621, n961_1, n959, n851 }; + assign n959 = 4'h8 >> { n813, n681 }; + assign n960 = 16'h222a >> { Ni41, Ni40, n822, n820 }; + assign n961_1 = 8'ha8 >> { n881, n960, n885 }; + assign n962 = 4'h8 >> { n963, n852 }; + assign n576 = 16'h0008 >> { Ni7, Ni8, Ni9, Ni10 }; + assign n963 = 32'd353703173 >> { Ni40, n924, n925, n964, n866 }; + assign n964 = 4'h1 >> { n814, n858 }; + assign n965 = 16'h888a >> { n924, Ni40, n964, n864 }; + assign n966_1 = 64'h08aa00aa08aa08aa >> { n851, n970, n699, n967, n852, n932 }; + assign n967 = 8'hfe >> { n968, n969, n866 }; + assign n968 = 16'h0008 >> { n814, n858, Ni33, Ni38 }; + assign n969 = 16'h0008 >> { n814, n858, n937, Ni33 }; + assign n970 = 32'd2358051845 >> { Ni36, Ni38, n931_1, n830, n813 }; + assign n971 = 32'd2324343434 >> { n960, n621, n961_1, n959, n625 }; + assign n972 = 16'haaa2 >> { n952, n950, n951_1, n644 }; + assign P__cmx0ad_12 = 4'h2 >> { Pi24, P__cmx0ad_9 }; + assign n973 = 4'h8 >> { Pi17, Pi16 }; + assign n974 = 8'h8a >> { n745, n975, n861 }; + assign n975 = 32'd2324335114 >> { n681, n976_1, n851, n977, n865 }; + assign n976_1 = 32'd1162151237 >> { Ni40, n819, n823, n816, n813 }; + assign n977 = 32'd2829623464 >> { Ni40, n819, n828, n816, n825 }; + assign n978 = 16'haaa2 >> { n979, n857, n847, Ni33 }; + assign n979 = 16'h0222 >> { Ni41, n858, n814, Ni38 }; + assign n980 = 32'd1346427080 >> { n981_1, n828, n825, n831, n621 }; + assign n981_1 = 16'h2202 >> { n815, n814, Ni38, n621 }; + assign n982 = 32'd1162167557 >> { Ni40, n830, n823, n831, n813 }; + assign P__cmx0ad_14 = 8'h28 >> { Pi23, Pi24, P__cmx0ad_9 }; + assign n983 = 32'd286331217 >> { n988, n989, n990, n834, n984 }; + assign n984 = 32'd2728569506 >> { n987, n851, n985, n852, n759 }; + assign n985 = 16'haaa2 >> { n986, n848, n847, Ni33 }; + assign n986 = 16'ha222 >> { n815, Ni41, n814, Ni38 }; + assign n987 = 32'd1346427080 >> { n981_1, n828, n825, n816, n621 }; + assign n988 = 16'h222a >> { n976_1, n681, n977, n745 }; + assign n989 = 4'h2 >> { n980, n757 }; + assign n990 = 64'hd0ddd0ddd0dd5055 >> { n681, n982, n759, n987, n832, n756 }; + assign n991_1 = 32'd16777473 >> { n834, n992, n1002, n999, Pi20 }; + assign n992 = 64'h1111101101110011 >> { n994, n993, n746, Pi16, n995, n997 }; + assign n1090 = 4'h2 >> { Ni2, Ni3 }; + assign n993 = 64'haa0a8800aa0a8808 >> { n823, n889, n681, n813, n881, n885 }; + assign n994 = 32'd538976290 >> { n903, n813, n681, n902, n885 }; + assign n995 = 64'hfd00fd00fd00ff00 >> { n881, n886, n757, n981_1, n996_1, n885 }; + assign n996_1 = 16'ha222 >> { n822, Ni41, n820, Ni38 }; + assign n997 = 32'd2863311522 >> { n998, n907, n981_1, n885, n759 }; + assign n998 = 32'd572654114 >> { Ni42, Ni41, n817, n820, Ni38 }; + assign n999 = 32'd2728569506 >> { n1000, Ni33, n1001, n852, n860 }; + assign n1000 = 16'h028a >> { Ni38, n879, n883, n877 }; + assign n1001 = 64'hfd00fd00fd00ff00 >> { n881, n886, n851, n981_1, n996_1, n885 }; + assign n1002 = 32'd2728569506 >> { n994, n851, n909, n852, n873 }; + assign P__cmnxcp_1 = 64'hae0cae0caeaeae0c >> { n589, Ni30, n587, n581, P__cmxcl_0, Ni33 }; + assign n1003 = 32'd2862785186 >> { Ni38, n913, n912, n877, Ni33 }; + assign n1004 = 32'd2863311522 >> { n998, n907, n981_1, n885, n851 }; + assign n1005 = 16'hd888 >> { n852, n963, n1006_1, n851 }; + assign n1006_1 = 64'haa0a8800aa0a8808 >> { n823, n960, n662, n813, n881, n885 }; + assign n1007 = 16'h22a2 >> { n1008, n951_1, n851, n955 }; + assign n1008 = 64'h5054505454545054 >> { n830, Ni40, n831, n813, n823, n662 }; + assign n1009 = 64'h0222002202220222 >> { n835, n1015, n699, n947, n1010, n1011_1 }; + assign n1010 = 32'd2292844586 >> { n1008, n1006_1, n951_1, Pi20, n834 }; + assign n1011_1 = 32'd572662434 >> { n1012, n1013, n852, n699, n932 }; + assign n1012 = 4'he >> { n968, n866 }; + assign n581 = 16'h0777 >> { n586, Ni12, n582, n585 }; + assign n1013 = 16'h22a2 >> { n830, Ni38, n1014, n851 }; + assign n1014 = 32'd3638091224 >> { n815, n814, Ni38, n826, Ni37 }; + assign n1015 = 8'h8a >> { Ni38, n830, n1014 }; + assign n1016_1 = 64'hfd00ff00fd00fd00 >> { n625, n1017, n948, n1022, n1019, n1023 }; + assign n1017 = 64'h08aa00aa08aa08aa >> { n851, n1018, n754, n922, n852, n897 }; + assign n1018 = 64'haa0a8800aa0a8808 >> { n823, n919, n662, n813, n881, n885 }; + assign n1019 = 64'hf070f0707070f070 >> { n1021, n1020, n851, n644, n943, n839 }; + assign n1020 = 32'd2695407784 >> { Ni40, n819, n828, n816, n825 }; + assign n1021 = 64'h5454505450545054 >> { n819, Ni40, n816, n813, n823, n662 }; + assign n1022 = 32'd2292844586 >> { n1021, n1018, n1020, Pi20, n834 }; + assign n582 = 4'h8 >> { n583, Ni11 }; + assign n1023 = 32'd572695074 >> { n1024, n934, n1026_1, n699, n932 }; + assign n1024 = 8'ha2 >> { n1025, n1014, n851 }; + assign n1025 = 16'h028a >> { Ni41, n820, n822, Ni38 }; + assign n1026_1 = 32'd1364327249 >> { n1025, n1014, Pi25, n845, n835 }; + assign n1027 = 64'hc8c8c8c8c8c888c8 >> { n1035, n1033, n1028, Pi17, Ni10, n1037 }; + assign n1028 = 64'h0455005504550455 >> { n643, n1031_1, n659, n1029, n1032, n1030 }; + assign n1029 = 16'h22a2 >> { n1018, n851, n921, n623 }; + assign n1030 = 64'h2a222a22aaaa2a22 >> { n1007, n643, n623, n1005, n1011_1, n645 }; + assign n1031_1 = 16'h22a2 >> { n1021, n1020, n851, n943 }; + assign n1032 = 16'h22a2 >> { n1024, n934, n699, n932 }; + assign n583 = 4'h2 >> { Ni12, n584 }; + assign n1033 = 64'h2a222a22aaaa2a22 >> { n939, n643, n623, n1034, n928, n672 }; + assign n1034 = 8'h02 >> { n917, n927, n921 }; + assign n1035 = 32'd2324343434 >> { n949, n643, n966_1, n1036, n677 }; + assign n1036 = 16'haaa2 >> { n965, n958, n962, n623 }; + assign n1037 = 32'd1431655764 >> { n1051, n1038, n1043, n1047, Pi17 }; + assign n1038 = 64'haaaaaaaaaaaaaaa2 >> { n1042, n1039, n1040, n1041_1, n932, n645 }; + assign n1039 = 32'd2728569506 >> { n994, n851, n909, n852, n632 }; + assign n1040 = 64'h0a8a0a8a0a8a8a8a >> { n982, n681, n832, n871, n851, n638 }; + assign n1041_1 = 32'd2728569506 >> { n980, n851, n978, n852, n643 }; + assign n1042 = 32'd2728569506 >> { n1000, Ni33, n1001, n852, n623 }; + assign n584 = 4'h2 >> { Ni13, Ni14 }; + assign n1043 = 64'hfd00ff00fd00fd00 >> { n632, n887, n672, n1045, n1044, n1046_1 }; + assign n1044 = 64'hf0d0f0d0d0d0f0d0 >> { n812, n824, n851, n638, n863, n865 }; + assign n1045 = 16'haaa2 >> { n850, n846, n852, n643 }; + assign n1046_1 = 32'd572662434 >> { n911, n914, n852, n623, n932 }; + assign n1047 = 64'hfd00ff00fd00fd00 >> { n638, n869, n677, n1050, n1048, n1049 }; + assign n1048 = 16'haaa2 >> { n876, n884, n852, n623 }; + assign n1049 = 64'h08aa00aa08aa08aa >> { n851, n855, n643, n856, n852, n932 }; + assign n1050 = 64'hfd00ff00fd00fd00 >> { n851, n901, n632, n909, n915, n852 }; + assign n1051 = 64'hfd00ff00fd00fd00 >> { n638, n975, n659, n1053, n1052, n1054 }; + assign n1052 = 16'haaa2 >> { n1003, n1004, n852, n623 }; + assign n585 = 4'h2 >> { Pi27, Pi26 }; + assign n1053 = 32'd2728569506 >> { n993, n851, n894, n852, n632 }; + assign n1054 = 64'h08aa00aa08aa08aa >> { n851, n987, n643, n985, n852, n932 }; + assign n1055 = 4'h2 >> { n1056_1, n757 }; + assign n1056_1 = 64'h00aa80aa08aa88aa >> { n876, n856, n754, Pi20, n1057, n1058 }; + assign n1057 = 16'h0111 >> { Ni34, n845, n843, n853 }; + assign n1058 = 64'h0101010101010111 >> { n843, n845, n853, n840, n933, n2590 }; + assign n1059 = 16'haa2a >> { n942, n1060, n1057, n752 }; + assign n1060 = 4'h1 >> { n866, n944 }; + assign n1061 = 64'hc4c4c4c4c4c444c4 >> { n1063, n953, n1057, n752, n751, n1062 }; + assign n1062 = 32'd1145365572 >> { n965, n963, n1057, n1058, n749 }; + assign n586 = 32'd524297 >> { Pi26, Ni13, Ni11, Ni14, Pi27 }; + assign n1063 = 4'he >> { n956_1, n866 }; + assign n1064 = 4'he >> { n935, n866 }; + assign n1065 = 64'hc4c4c4c4c4c444c4 >> { n915, n909, n1057, n749, n756, n1066_1 }; + assign n1066_1 = 32'd1145365572 >> { n870, n1067, n1057, n1058, n752 }; + assign n1067 = 4'h1 >> { n866, n872 }; + assign n1068 = 4'he >> { n867, n866 }; + assign n1069 = 8'ha2 >> { n1003, n1057, n749 }; + assign n1070 = 32'd2315946634 >> { n1057, n978, n1071_1, n752, n757 }; + assign n1071_1 = 32'd2324302474 >> { n1000, Ni33, n749, n1057, n1058 }; + assign n1072 = 32'd1171064205 >> { n1067, n1063, n756, n1057, n751 }; + assign n587 = 8'h08 >> { Ni30, n588, Ni31 }; + assign n1073 = 32'd2861181450 >> { n1012, n1064, n1057, Pi16, n754 }; + assign n1074 = 32'd2728558752 >> { n963, n751, n1075, n756, n1057 }; + assign n1075 = 8'h15 >> { n895, n893, n866 }; + assign n1076 = 64'h0002020200ffaaff >> { n632, n856, n643, n915, n909, n1057 }; + assign n1077 = 64'h0002020200ffaaff >> { n638, n846, n643, n863, n1068, n1057 }; + assign n1078 = 16'h22a2 >> { n909, n1057, n632, n932 }; + assign n1079 = 32'd171640891 >> { n963, n623, n1012, n699, n1057 }; + assign n1080 = 64'hf070f0707070f070 >> { n922, n1057, n623, n659, n932, n1081 }; + assign n1081 = 32'd171640891 >> { n1060, n643, n1064, n699, n1057 }; + assign n1082 = 16'haaa2 >> { n922, n927, n1057, n623 }; + assign n588 = 16'h0008 >> { Ni4, Ni5, Ni6, n1090 }; + assign n1083 = 4'h2 >> { Ni13, n572 }; + assign n1084 = 64'hfd00ff00fd00fd00 >> { n623, n1093, n672, n1090_1, n1085_1, n1088 }; + assign n1085_1 = 8'h8a >> { n1087, n1086, n632 }; + assign n1086 = 8'ha8 >> { n893, n892, n864 }; + assign n1087 = 64'h0001000100010101 >> { n893, n892, n895, n853, n866, n843 }; + assign n1088 = 8'h8a >> { n643, n1089, n932 }; + assign n1089 = 64'h1111111111115111 >> { n848, n849, n622, n847, Ni33, n853 }; + assign n1090_1 = 16'haa2a >> { n863, n1091, n1092, n638 }; + assign n1091 = 4'h1 >> { n853, n843 }; + assign n1092 = 4'h1 >> { n866, n867 }; + assign n589 = 64'hf7ffffffffffff7f >> { n590, Ni4, Ni6, Ni5, n1090, Ni31 }; + assign n1093 = 64'h1111111111115111 >> { n912, n913, n877, n622, Ni33, n853 }; + assign n1094 = 32'd1 >> { n853, n866, n870, n872, n843 }; + assign n1095 = 64'h0001000100010101 >> { n895, n864, n893, n866, n843, n853 }; + assign n1096 = 64'h1111111111115111 >> { n879, n883, n877, n622, Ni33, n853 }; + assign n1097 = 64'h1111111111115111 >> { n857, n859, n622, n847, Ni33, n853 }; + assign n1098 = 64'hf0d0f0d0d0d0f0d0 >> { n1003, n1091, n623, n659, n1099, n1101 }; + assign n1099 = 32'd2324302474 >> { n986, n1100, n1091, Ni33, n643 }; + assign n1100 = 4'h2 >> { n848, n847 }; + assign n1101 = 64'haa8a2a0a2a0a2a0a >> { n1092, n1091, n1087, n699, Pi20, n932 }; + assign n1102 = 16'haaa2 >> { n857, n979, n847, Ni33 }; + assign n590 = 8'hd8 >> { Ni36, Ni41, Ni32 }; + assign n1103 = 16'h0001 >> { n853, n866, n872, n843 }; + assign n1104 = 16'h0001 >> { n853, n866, n956_1, n843 }; + assign n1105 = 16'h0001 >> { n853, n866, n968, n843 }; + assign n1106 = 64'h7070f070f070f070 >> { n1110, n1091, n623, n659, n932, n1107 }; + assign n1107 = 16'hdd0d >> { n1109, n643, n1108, n699 }; + assign n1108 = 16'h0001 >> { n853, n866, n935, n843 }; + assign n1109 = 16'h0001 >> { n853, n866, n944, n843 }; + assign n1110 = 32'd1162167557 >> { Ni40, n924, n925, n923, n866 }; + assign n1111 = 64'hfd00ff00fd00fd00 >> { n623, n1112, n677, n1114, n1113, n932 }; + assign n1112 = 64'h0888088808880088 >> { Ni40, n924, n864, n964, n1091, n963 }; + assign P__cmnxcp_0 = 32'd3705462236 >> { n589, Ni30, n587, n592, Ni33 }; + assign n1113 = 16'h22a2 >> { n954, n864, n1104, n643 }; + assign n1114 = 8'ha2 >> { n969, n1105, n699 }; + assign n1115 = 64'haaaaaaaaaaaaaaa8 >> { n866, n867, n843, n853, n863, n752 }; + assign n1116 = 4'h1 >> { Ni14, Ni13 }; + assign n1117 = 16'h44e4 >> { n1008, n951_1, n1006_1, Pi20 }; + assign n1118 = 32'd2829626024 >> { Ni34, n853, n843, n845, Pi22 }; + assign n1119 = 4'h8 >> { n851, Pi22 }; + assign n1120 = 64'h5555454445444544 >> { Pi21, n1118, n1121, n992, n2590, Pi20 }; + assign n1121 = 4'h8 >> { n851, n624 }; + assign n1122 = 64'hc4c4c4c4c4c444c4 >> { n989, n988, n990, n1121, Pi20, n1123 }; + assign n592 = 16'ha888 >> { n595, n597, n593, P__cmxcl_0 }; + assign n1123 = 4'h1 >> { n1118, n841 }; + assign n1124 = 16'h1151 >> { n1025, n1014, n1119, n1118 }; + assign n1125 = 8'h08 >> { n1126, n1121, n948 }; + assign n1126 = 32'd3705470684 >> { n1021, n1020, n1018, Pi19, Pi20 }; + assign n1127 = 64'hf500f700fd00ff00 >> { n1134, n1128, n806, n1130, Pi20, n1132 }; + assign n1128 = 32'd4539717 >> { Pi21, n1118, n1121, n1129, n2590 }; + assign n1129 = 16'h2022 >> { n745, n899, n900, n904 }; + assign n1130 = 32'd2829625504 >> { n972, n971, n1131, n1121, n973 }; + assign n1131 = 32'd2155907200 >> { n970, n1119, n1118, Pi19, Pi21 }; + assign n1132 = 32'd2004289399 >> { n946_1, n1121, n948, n1133, n929 }; + assign n593 = 32'd2147516424 >> { Pi23, Ni10, Pi24, n594, Ni8 }; + assign n1133 = 8'h08 >> { Pi16, n776, n624 }; + assign n1134 = 16'h22a2 >> { n811, n2589, n1121, n1123 }; + assign n1135 = 32'd1162151237 >> { n845, n1091, n932, n624, n716 }; + assign n1011 = 64'hf575f5757575f575 >> { n2918, n1293, n718, n1669, n1532, n1661 }; + assign n1137 = 64'ha2a2a2a200a2a2a2 >> { n1188, n1226, n1213, n1138, n1164, n1238 }; + assign n1138 = 64'hfd00ff00fd00fd00 >> { n699, n1158, n659, n1153, n1139, n1163 }; + assign n1139 = 16'haaa8 >> { Ni32, n1148, n1140, n623 }; + assign n1140 = 16'h0008 >> { n1146, n18, n1147, n1141 }; + assign n1141 = 64'h0022002022222020 >> { n878, n1145, n1142, Ni40, n1143, n1144 }; + assign n1142 = 32'd1364218193 >> { Ni42, Ni43, Ni45, Ni47, Ni38 }; + assign n594 = 4'h1 >> { Ni7, Ni9 }; + assign n1143 = 32'd2728436386 >> { Ni42, Ni43, Ni45, Ni47, Ni41 }; + assign n1144 = 32'd1364283473 >> { Ni38, Ni37, Ni47, Ni43, Ni45 }; + assign n1145 = 16'hfffe >> { Ni44, Ni41, Ni42, Ni47 }; + assign n1146 = 4'h2 >> { n662, n1142 }; + assign n1147 = 4'h1 >> { Ni30, Ni31 }; + assign n1148 = 8'h02 >> { n1149, n1146, n1141 }; + assign n1149 = 8'h15 >> { n1151, n1150, n1152 }; + assign n1150 = 8'h01 >> { Ni30, Ni31, Ni45 }; + assign n1151 = 32'd4076007666 >> { Ni38, Ni37, Ni47, Ni43, Ni42 }; + assign n1152 = 8'h02 >> { Ni30, Ni31, Ni33 }; + assign n595 = 4'h8 >> { n596, Ni7 }; + assign n1153 = 16'haaa8 >> { Ni32, n1157, n1154, n643 }; + assign n1154 = 16'h0008 >> { n1146, n18, n1147, n1155 }; + assign n1155 = 64'h0022002022222020 >> { n827, n1156, n1142, Ni40, n1143, n1144 }; + assign n1156 = 16'hfffd >> { Ni41, Ni42, Ni47, Ni44 }; + assign n1157 = 8'h02 >> { n1149, n1146, n1155 }; + assign n1158 = 32'd4062376450 >> { n1149, n1162, n1161, n599, n1160 }; + assign n1159 = 4'h2 >> { n599, n1143 }; + assign n1160 = 32'd1330597455 >> { Ni31, n1161, Ni32, n18, Ni30 }; + assign n1161 = 64'h5150515051515150 >> { Ni37, Ni42, Ni38, Ni47, Ni43, Ni45 }; + assign n1162 = 64'h2202220022022202 >> { Ni42, Ni43, Ni45, Ni47, Ni32, Ni41 }; + assign n596 = 8'h02 >> { Ni9, Ni8, Ni10 }; + assign n1163 = 64'h8f8f8f8f8f8f8f8d >> { Ni30, Ni31, Ni45, Ni32, Pi22, Pi21 }; + assign n1164 = 64'h0002000202020002 >> { n1165, n1169, n672, n1182, n1176, Pi17 }; + assign n1165 = 16'haaa8 >> { Ni32, n1168, n1166, n623 }; + assign n1166 = 16'h0008 >> { n1167, n18, n1147, n1141 }; + assign n1167 = 4'h8 >> { n681, n1142 }; + assign n1168 = 8'h02 >> { n1167, n1149, n1141 }; + assign n1169 = 64'h08080008aaaa00aa >> { n643, n1172, n699, n1171, n1170, n1163 }; + assign n1170 = 64'h5555555555555551 >> { Ni30, Ni31, n1167, n18, n1155, Ni32 }; + assign n1171 = 8'h02 >> { n1167, n1149, n1155 }; + assign n1172 = 8'hea >> { n1175, n1173, n1162 }; + assign n597 = 4'h2 >> { Pi24, Pi23 }; + assign n1173 = 64'h4f4f4f4f4f4f4e4f >> { n1174, Ni31, n1144, Ni32, n18, Ni30 }; + assign n1174 = 16'h0001 >> { Ni42, Ni47, Ni36, Ni38 }; + assign n1175 = 64'h0d0d0d0f0d0f0d0f >> { n1150, n1151, n1152, n599, n1174, n1144 }; + assign n1176 = 64'h2a222a22aaaa2a22 >> { n1179, n623, n643, n1177, n1181, n677 }; + assign n1177 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1178 }; + assign n1178 = 64'h000a0008aaaa8888 >> { n1142, n1156, n681, n827, Ni40, n1144 }; + assign n1179 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1180 }; + assign n1180 = 64'h000a0008aaaa8888 >> { n1142, n1145, n681, n878, Ni40, n1144 }; + assign n1181 = 16'ha222 >> { n1173, n1175, n699, n1163 }; + assign n1182 = 64'h2a222a22aaaa2a22 >> { n1185, n643, n623, n1183, n1187, n645 }; + assign n931 = 64'hf0f0f1e0f1e0f1e0 >> { n599, Ni31, Pi20, Ni48, Pi22, Ni47 }; + assign n1183 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1184 }; + assign n1184 = 64'h00880080aaaaa0a0 >> { n1142, n1145, n878, Ni40, n662, n1144 }; + assign n1185 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1186 }; + assign n1186 = 64'h00880080aaaaa0a0 >> { n1142, n1156, n827, Ni40, n662, n1144 }; + assign n1187 = 64'h08aa00aa08aa08aa >> { n1161, n1149, n699, n599, n1160, n1163 }; + assign n1188 = 32'd2863311522 >> { n1189, n1196, n1204, n1209, n659 }; + assign n1189 = 8'ha8 >> { n1194, n1190, n643 }; + assign n1190 = 32'd2863311534 >> { n1193, n1162, n18, n1191, Ni32 }; + assign n1191 = 32'd526344 >> { n1142, n827, n1192, n1144, n1147 }; + assign n1192 = 16'h0002 >> { Ni41, Ni47, Ni42, Ni44 }; + assign n599 = 4'h2 >> { Ni30, Ni32 }; + assign n1193 = 8'h08 >> { n599, n621, n1142 }; + assign n1194 = 32'd1145324628 >> { n1149, n1143, n1195, n599, n1193 }; + assign n1195 = 16'h0222 >> { n1142, n827, n1192, n1144 }; + assign n1196 = 16'h2220 >> { n1202, n1197, n1162, n623 }; + assign n1197 = 16'h4445 >> { n1199, n18, n1201, n1198 }; + assign n1198 = 8'h08 >> { Ni32, n1142, n621 }; + assign n1199 = 64'h00ff00f700f700f7 >> { n1142, n878, n599, n1200, n1144, n1147 }; + assign n1200 = 16'h0001 >> { Ni44, Ni41, Ni47, Ni42 }; + assign n1201 = 4'h8 >> { Ni30, Ni32 }; + assign n1202 = 16'h4454 >> { n1149, n1203, n599, n1193 }; + assign n951 = 8'hd8 >> { Ni44, Ni33, n601 }; + assign n1203 = 16'h0222 >> { n1142, n878, n1200, n1144 }; + assign n1204 = 16'haaa8 >> { Ni32, n1208, n1205, n632 }; + assign n1205 = 16'h0008 >> { n1206, n18, n1147, n1207 }; + assign n1206 = 4'h2 >> { n681, n1142 }; + assign n1207 = 64'h0202000222220022 >> { n878, n1145, Ni40, n1142, n1143, n1144 }; + assign n1208 = 8'h02 >> { n1149, n1206, n1207 }; + assign n1209 = 32'd572662314 >> { Ni32, n1212, n1210, n638, n1163 }; + assign n1210 = 16'h0008 >> { n1206, n18, n1147, n1211 }; + assign n1211 = 64'h0202000222220022 >> { n827, n1156, Ni40, n1142, n1143, n1144 }; + assign n1212 = 8'h02 >> { n1149, n1206, n1211 }; + assign n601 = 4'h8 >> { n602, Ni32 }; + assign n1213 = 64'hffd5d5d5d5d5d5d5 >> { n1198, Pi22, Pi15, n1216, n1214, Pi16 }; + assign n1214 = 8'h8a >> { n643, n1215, n1163 }; + assign n1215 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1195 }; + assign n1216 = 64'hfffdf7f57f7d7775 >> { n1220, n1218, n1217, Pi20, Pi19, n624 }; + assign n1217 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1203 }; + assign n1218 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1219 }; + assign n1219 = 64'h02020002aaaa00aa >> { n1142, n1145, Ni40, n878, n662, n1144 }; + assign n1220 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1221 }; + assign n1221 = 64'h02020002aaaa00aa >> { n1142, n1156, Ni40, n827, n662, n1144 }; + assign n1222 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1223 }; + assign n602 = 4'h2 >> { Ni31, Ni30 }; + assign n1223 = 64'h08080008aaaa00aa >> { n1142, n1156, Ni40, n827, n681, n1144 }; + assign n1224 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1149, Ni32, n1225 }; + assign n1225 = 64'h08080008aaaa00aa >> { n1142, n1145, Ni40, n878, n681, n1144 }; + assign n1226 = 64'h1111111111115111 >> { n1231, n1227, n1233, n1163, n672, Pi17 }; + assign n1227 = 16'haaa8 >> { Ni32, n1230, n1228, n638 }; + assign n1228 = 16'h0008 >> { n1229, n18, n1147, n1211 }; + assign n1229 = 4'h8 >> { n662, n1142 }; + assign n1230 = 8'h02 >> { n1149, n1229, n1211 }; + assign n1231 = 64'ha2a0a2a0a2a2a2a0 >> { n1149, n1203, n599, n1232, n1159, n623 }; + assign n1232 = 16'h4445 >> { n1199, n18, n1201, n1162 }; + assign n966 = 64'hfc30f4b0f870f0f0 >> { n576, n571, n613, Ni41, n604, Ni33 }; + assign n1233 = 64'h00022222000fffff >> { n632, n643, n1234, n1235, n1236, n1237 }; + assign n1234 = 16'haaae >> { n1162, n18, n1191, Ni32 }; + assign n1235 = 16'haaae >> { n1149, n1143, n1195, n599 }; + assign n1236 = 8'h02 >> { n1149, n1229, n1207 }; + assign n1237 = 64'h5555555555555551 >> { Ni30, Ni31, n1229, n18, n1207, Ni32 }; + assign n1238 = 4'h2 >> { n583, Ni11 }; + assign n1239 = 64'haaaaaaaaaaaaaaa2 >> { n1249, n1240, n1242, n1247, n1252, n758 }; + assign n1240 = 8'ha8 >> { n1235, n1234, n1241 }; + assign n1241 = 8'h08 >> { n585, n624, Pi20 }; + assign n1242 = 64'h2220222022222220 >> { n1149, n1203, n1246, n1243, n1245, n1244 }; + assign n604 = 4'h8 >> { n601, n605 }; + assign n1243 = 4'h1 >> { n1199, n18 }; + assign n1244 = 8'h08 >> { Pi20, n624, n585 }; + assign n1245 = 4'h2 >> { n1246, n1143 }; + assign n1246 = 16'haa2a >> { Ni31, Ni33, Ni30, Ni32 }; + assign n1247 = 64'ha2a0a2a0a2a2a2a0 >> { n1149, n1203, n599, n1232, n1159, n1248 }; + assign n1248 = 4'h2 >> { n585, n750 }; + assign n1249 = 64'h2220222022222220 >> { n1149, n1195, n1246, n1250, n1245, n1251 }; + assign n1250 = 4'h2 >> { n18, n1191 }; + assign n1251 = 8'h80 >> { n585, n624, Pi20 }; + assign n1252 = 32'd570556930 >> { n585, n1256, n1253, n1255, n1254 }; + assign n605 = 16'h0002 >> { Ni4, Ni6, Ni5, P__cmxcl_0 }; + assign n1253 = 64'h2020202020202022 >> { Ni45, Ni30, Ni31, Ni32, Pi22, Pi21 }; + assign n1254 = 64'hddddddddddddfddd >> { Ni31, Pi27, Ni30, Ni33, Pi21, Ni32 }; + assign n1255 = 8'h02 >> { Pi26, Pi21, Ni32 }; + assign n1256 = 32'd1566332244 >> { Ni33, Ni45, Ni31, Ni30, Ni32 }; + assign n1257 = 16'h0008 >> { n1167, n18, n1147, n1155 }; + assign n1258 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n750, n1236, n1259, n585 }; + assign n1259 = 16'h0008 >> { n1229, n18, n1147, n1207 }; + assign n1260 = 8'h08 >> { n1261, n1175, n1262 }; + assign n1261 = 16'h0008 >> { n1174, n18, n1147, n1144 }; + assign n1262 = 16'h7757 >> { Ni33, Ni30, Ni31, Ni32 }; + assign n971_1 = 64'hbb88bb08bb80bb00 >> { n576, n571, Ni40, Ni33, n604, n607 }; + assign n1263 = 4'h8 >> { n624, n776 }; + assign n1264 = 8'ha8 >> { n1202, n1197, n1248 }; + assign n1265 = 16'h0002 >> { n1143, n1193, n18, n1191 }; + assign n1266 = 32'd789524271 >> { n1268, n1267, n1252, n1245, n1244 }; + assign n1267 = 8'h01 >> { n1193, n1199, n18 }; + assign n1268 = 32'd2728436386 >> { n1203, n1149, n1193, n599, n1262 }; + assign n1269 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n750, n1148, n1140, n585 }; + assign n1270 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n750, n1208, n1205, n585 }; + assign n1271 = 32'd33554946 >> { n1161, n1149, n599, n1272, n1262 }; + assign n1272 = 8'h08 >> { n18, n1161, n1147 }; + assign n607 = 32'd4160201463 >> { Pi23, n576, Pi26, n571, Ni33 }; + assign n1273 = 32'd707439146 >> { n1276, n1244, n1252, n1274, n748 }; + assign n1274 = 64'hfffdf7f57f7d7775 >> { n1275, n1185, n1183, n585, Pi20, n624 }; + assign n1275 = 32'd1157973317 >> { n1147, n18, n1186, n1149, n1246 }; + assign n1276 = 32'd1157973317 >> { n1147, n18, n1184, n1149, n1246 }; + assign n1277 = 8'h02 >> { n1193, n18, n1191 }; + assign n1278 = 32'd2728436386 >> { n1195, n1149, n1193, n599, n1262 }; + assign n1279 = 64'h5757575757570057 >> { n1215, n1198, n1241, n1202, n1197, n1248 }; + assign n1280 = 32'd707439146 >> { n1283, n1251, n1252, n1281, n746 }; + assign n1281 = 64'hffdffdddf7d7f5d5 >> { n1282, n1224, n1222, Pi20, n585, n624 }; + assign n1282 = 32'd1141134420 >> { n1225, n18, n1147, n1149, n1246 }; + assign n976 = 8'hd8 >> { Ni39, Ni33, n609 }; + assign n1283 = 32'd1141134420 >> { n1223, n18, n1147, n1149, n1246 }; + assign n1284 = 16'h2022 >> { n1161, n1149, n599, n1160 }; + assign n1285 = 32'd1141134420 >> { n1221, n18, n1147, n1149, n1246 }; + assign n1286 = 32'd1157973317 >> { n1147, n18, n1219, n1149, n1246 }; + assign n1287 = 64'hffdff7d77f5f7757 >> { n1289, n1288, n1177, Pi20, n585, n624 }; + assign n1288 = 32'd1157973317 >> { n1147, n18, n1180, n1149, n1246 }; + assign n1289 = 32'd1141134420 >> { n1178, n18, n1147, n1149, n1246 }; + assign n1290 = 32'd1141134420 >> { n1195, n18, n1147, n1149, n1246 }; + assign n1291 = 16'h5444 >> { n1149, n18, n1199, n1246 }; + assign n1292 = 4'h8 >> { n1173, n1175 }; + assign n609 = 4'h2 >> { Ni32, n602 }; + assign n1293 = 64'h0101010101011101 >> { n2929, n2869, n1345, n1531, n1469, n1365 }; + assign n1294 = 4'h2 >> { n1295, n776 }; + assign n1295 = 32'd570556930 >> { n1296, n1256, n1253, n1297, n1254 }; + assign n1296 = 4'h1 >> { Pi26, Pi27 }; + assign n1297 = 8'h08 >> { Pi21, Ni32, Pi26 }; + assign n1298 = 64'ha2a0a2a0a2a2a2a0 >> { n1149, n1203, n599, n1232, n1159, n1299 }; + assign n1299 = 8'h02 >> { n1296, Pi20, n624 }; + assign n1300 = 64'h2220222022222220 >> { n1149, n1195, n1246, n1250, n1245, n1301 }; + assign n1301 = 8'h80 >> { n1296, n624, Pi20 }; + assign n1302 = 8'ha8 >> { n1235, n1234, n1303 }; + assign n991 = 8'he4 >> { n613, Ni36, n611 }; + assign n1303 = 8'h08 >> { n1296, n624, Pi20 }; + assign n1304 = 64'h2220222022222220 >> { n1149, n1203, n1246, n1243, n1245, n1305 }; + assign n1305 = 8'h08 >> { Pi20, n624, n1296 }; + assign n1306 = 16'haaa8 >> { n1246, n1236, n1259, n1305 }; + assign n1307 = 64'h000101010011ffff >> { n1301, n1303, Ni32, n1246, n1230, n1228 }; + assign n1308 = 16'hfddd >> { n1260, n1296, n1172, n1263 }; + assign n1309 = 8'ha8 >> { n1202, n1197, n1299 }; + assign n1310 = 32'd2324343434 >> { n1267, n1268, n1305, n1245, n1295 }; + assign n1311 = 64'h000101010011ffff >> { n1301, n1303, Ni32, n1246, n1157, n1154 }; + assign n1312 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n750, n1148, n1140, n1296 }; + assign n611 = 32'd2290092032 >> { n571, n576, Ni33, n605, n609 }; + assign n1313 = 32'd1431392593 >> { n1296, n1271, n1158, n1263, n1294 }; + assign n1314 = 64'haaaaaaaaaaaaaaa2 >> { n1294, n1315, n2639, n2641, n1318, n645 }; + assign n1315 = 32'd707439146 >> { n1283, n1301, n1295, n1316, n746 }; + assign n1316 = 64'hffdffdddf7d7f5d5 >> { n1282, n1224, n1222, Pi20, n1296, n624 }; + assign n1317 = 8'h02 >> { n1215, n1198, n1303 }; + assign n1318 = 16'hfd75 >> { n1271, n1284, n1296, n1263 }; + assign n1319 = 64'h2a222a22aaaa2a22 >> { n1290, n1301, n1303, n1215, n1320, n758 }; + assign n1320 = 32'd2324299914 >> { n1291, n1305, n1299, n1217, n1295 }; + assign n1321 = 16'hfd75 >> { n1260, n1292, n1296, n1263 }; + assign n1322 = 4'h8 >> { n1116, Ni12 }; + assign n612 = 8'h08 >> { Ni31, Ni30, Ni33 }; + assign n1323 = 8'h02 >> { Pi27, Pi20, n624 }; + assign n1324 = 8'h08 >> { Pi27, n624, Pi20 }; + assign n1325 = 8'h80 >> { n624, Pi27, Pi20 }; + assign n1326 = 8'h08 >> { Pi20, Pi27, n624 }; + assign n1327 = 32'd2155905024 >> { n1330, n1271, n1328, n1331, Pi15 }; + assign n1328 = 16'heeef >> { n798, n1329, Pi27, n1158 }; + assign n1329 = 16'h0008 >> { Pi27, Pi16, n624, n776 }; + assign n1330 = 8'hb1 >> { n1245, n798, n1133 }; + assign n1331 = 8'hea >> { Pi27, n1256, n1163 }; + assign n1332 = 4'h8 >> { n624, Pi20 }; + assign n613 = 64'ha222800080008000 >> { n576, Pi24, n571, Pi27, Ni33, n602 }; + assign n1333 = 4'h2 >> { n1215, n1324 }; + assign n1334 = 64'hffdf7f5ff7d77757 >> { n1286, n1285, n1220, Pi20, Pi27, n624 }; + assign n1335 = 64'hfff7fdf57f777d75 >> { n1289, n1179, n1177, Pi27, Pi20, n624 }; + assign n1336 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n1332, n1171, n1257, Pi27 }; + assign n1337 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n1332, n1230, n1228, Pi27 }; + assign n1338 = 64'h00ff02ff01ff03ff >> { Ni32, n1246, n750, n1236, n1259, Pi27 }; + assign n1339 = 32'd2863311528 >> { n1343, n1340, n1341, n1342, n759 }; + assign n1340 = 64'h2220222022222220 >> { n1149, n1195, n1246, n1250, n1245, n1325 }; + assign n1341 = 64'ha2a0a2a0a2a2a2a0 >> { n1149, n1203, n599, n1232, n1159, n1323 }; + assign n1342 = 8'ha8 >> { n1235, n1234, n1324 }; + assign n614 = 4'h2 >> { n615, n622 }; + assign n1343 = 64'h2220222022222220 >> { n1149, n1203, n1246, n1243, n1245, n1326 }; + assign n1344 = 4'h8 >> { n584, Ni12 }; + assign n1345 = 64'hfff0fffefff0dddc >> { n2653, Ni13, n1346, n1347, Ni12, Ni14 }; + assign n1346 = 4'h2 >> { n1138, n1164 }; + assign n1347 = 8'h08 >> { n1188, n1213, n1226 }; + assign n1348 = 64'h00f500fd00f700ff >> { n1141, n1155, Ni32, n1146, Pi20, n1147 }; + assign n1349 = 64'h00f500fd00f700ff >> { n1141, n1155, Ni32, n1167, Pi20, n1147 }; + assign n1350 = 64'h00fc00fe00fd00ff >> { n1180, n1178, Ni32, Ni30, Ni31, Pi20 }; + assign n1351 = 16'h5515 >> { n1174, n1144, n1147, Ni32 }; + assign n1352 = 32'd557192 >> { n1354, n1353, Pi19, n645, n624 }; + assign n615 = 4'h1 >> { n616, n620 }; + assign n1353 = 64'h00fc00fd00fe00ff >> { n1186, n1184, Ni32, Ni30, Ni31, Pi20 }; + assign n1354 = 8'h15 >> { n1161, n1147, Ni32 }; + assign n1355 = 64'hf0d0f0d0d0d0f0d0 >> { n1351, n672, n1354, Pi17, n1162, n699 }; + assign n1356 = 64'h1111110111101100 >> { n1357, n1191, Ni32, Pi20, n1198, n1162 }; + assign n1357 = 32'd526344 >> { n1142, n878, n1200, n1144, n1147 }; + assign n1358 = 32'd1431393360 >> { n1357, n1191, Ni32, Pi20, n1162 }; + assign n1359 = 64'h00f500f700fd00ff >> { n1211, n1207, Ni32, n1206, Pi20, n1147 }; + assign n1360 = 64'h00f500f700fd00ff >> { n1211, n1207, Ni32, n1229, Pi20, n1147 }; + assign n1361 = 32'd4042453491 >> { n1357, n1191, n1198, Ni32, Pi20 }; + assign n1362 = 32'd88413525 >> { n1225, n1223, n1147, Pi20, Ni32 }; + assign n616 = 8'h08 >> { Ni38, n618, n617 }; + assign n1363 = 16'h0213 >> { n1357, n1191, Ni32, Pi20 }; + assign n1364 = 32'd85280085 >> { n1221, n1219, n1147, Pi20, Ni32 }; + assign n1365 = 64'h4544454445445555 >> { n1468, n1424, n2661, n2938, n2950, Ni10 }; + assign n1366 = 8'ha2 >> { n1367, n840, n1295 }; + assign n1367 = 64'h0080808000ffffff >> { Ni32, n1150, n1151, n602, Ni33, n1296 }; + assign n1368 = 64'h03570377035f03ff >> { n1180, n1178, n1246, n1369, n1370, n1147 }; + assign n1369 = 16'h8000 >> { n1296, n624, Pi20, Pi25 }; + assign n1370 = 16'h0080 >> { Pi20, n624, n1296, Pi25 }; + assign n1371 = 8'h08 >> { n1296, n624, Pi25 }; + assign n1372 = 32'd2862786720 >> { n1357, n1191, Ni32, Pi20, n1371 }; + assign n617 = 64'h1010001011110011 >> { Ni37, Ni43, Ni42, Ni38, Ni47, Ni45 }; + assign n1373 = 32'd17895263 >> { n1370, n1191, n1369, n1357, n1246 }; + assign n1374 = 16'hfd75 >> { n1375, n1351, n1296, n755 }; + assign n1375 = 16'h5515 >> { n1174, n1144, n1147, n1246 }; + assign n1376 = 64'h1111111111111151 >> { n1377, n1380, n1383, n1384, n672, Ni14 }; + assign n1377 = 64'hfd55ff55fd55fd55 >> { n1371, n1349, n748, n1379, n1378, n1366 }; + assign n1378 = 32'd2290657416 >> { n1167, n1147, n1141, n1246, n1370 }; + assign n1379 = 32'd2290657416 >> { n1167, n1147, n1155, n1246, n1369 }; + assign n1380 = 64'hfd00ff00fd00fd00 >> { n1371, n1360, n746, n1382, n1381, n1366 }; + assign n1381 = 32'd2290657416 >> { n1229, n1147, n1211, n1246, n1369 }; + assign n1382 = 32'd2290657416 >> { n1229, n1147, n1207, n1246, n1370 }; + assign n618 = 16'h4454 >> { Ni38, Ni39, Ni36, Ni37 }; + assign n1383 = 32'd2315946634 >> { n1373, n1371, n1366, n1358, n758 }; + assign n1384 = 32'd4294442485 >> { n1245, n1296, n1351, n1375, n755 }; + assign n1385 = 8'h15 >> { n1161, n1147, n1246 }; + assign n1386 = 64'hfd00ff00fd00fd00 >> { n1371, n1361, n758, n1388, n1387, n1366 }; + assign n1387 = 32'd707406346 >> { n599, n1191, n1262, n1193, n1369 }; + assign n1388 = 16'h222a >> { n1199, n1193, n1262, n1370 }; + assign n1389 = 64'haaaaaaaaaaaaaaa2 >> { n1398, n1390, n1391, n1394, n1397, n659 }; + assign n1390 = 32'd2324335114 >> { n1387, n1371, n1366, n1356, n758 }; + assign n1391 = 64'hfd00ff00fd00fd00 >> { n1371, n1359, n746, n1393, n1392, n1366 }; + assign n1392 = 32'd2290657416 >> { n1206, n1147, n1211, n1246, n1369 }; + assign n619 = 16'h0001 >> { Ni47, Ni43, Ni45, Ni42 }; + assign n1393 = 32'd2290657416 >> { n1206, n1147, n1207, n1246, n1370 }; + assign n1394 = 64'hfd00ff00fd00fd00 >> { n1371, n1348, n748, n1396, n1395, n1366 }; + assign n1395 = 32'd2290657416 >> { n1146, n1147, n1155, n1246, n1369 }; + assign n1396 = 32'd2290657416 >> { n1146, n1147, n1141, n1246, n1370 }; + assign n1397 = 32'd3722304861 >> { n1354, n1162, n1371, n1366, n776 }; + assign n1398 = 32'd1077957952 >> { n1385, n755, n758, n1388, n1245 }; + assign n1399 = 4'h2 >> { Pi27, n754 }; + assign n1400 = 16'h0080 >> { Pi20, Pi27, n624, Pi25 }; + assign n1401 = 16'h8000 >> { n624, Pi27, Pi20, Pi25 }; + assign n1402 = 8'ha2 >> { n1403, n840, n1331 }; + assign n620 = 64'h8a888a888a880a00 >> { Ni44, Ni41, n618, n621, n619, n617 }; + assign n1403 = 64'h0080808000ffffff >> { Ni32, n1150, n1151, Ni33, Pi27, n602 }; + assign n1404 = 64'hfd00ff00fd00fd00 >> { n1399, n1361, n758, n1405, n1406, n1402 }; + assign n1405 = 16'h222a >> { n1199, n1193, n1262, n1400 }; + assign n1406 = 32'd707406346 >> { n599, n1191, n1262, n1193, n1401 }; + assign n1407 = 64'hff55f7557f557755 >> { n1385, n1354, n1402, Pi27, n754, n776 }; + assign n1408 = 64'hfd55ff55fd55fd55 >> { n1399, n1349, n748, n1410, n1409, n1402 }; + assign n1409 = 32'd2290657416 >> { n1167, n1147, n1155, n1246, n1401 }; + assign n1410 = 32'd2290657416 >> { n1167, n1147, n1141, n1246, n1400 }; + assign n1411 = 64'hfd00ff00fd00fd00 >> { n1399, n1360, n746, n1412, n1413, n1402 }; + assign n1412 = 32'd2290657416 >> { n1229, n1147, n1211, n1246, n1401 }; + assign n621 = 4'h2 >> { Ni37, Ni36 }; + assign n1413 = 32'd2290657416 >> { n1229, n1147, n1207, n1246, n1400 }; + assign n1414 = 64'h2222220222202200 >> { n1357, n1191, Ni32, Pi20, Pi27, n754 }; + assign n1415 = 8'ha8 >> { n1246, n1191, n1401 }; + assign n1416 = 8'ha8 >> { n1246, n1357, n1400 }; + assign n1417 = 32'd4294442485 >> { n1245, Pi27, n1351, n1375, n755 }; + assign n1418 = 64'h03570377035f03ff >> { n1221, n1219, n1246, n1400, n1401, n1147 }; + assign n1419 = 32'd2863311522 >> { n1416, n1414, n1415, n1402, n758 }; + assign n1420 = 32'd707406346 >> { n1406, n1405, n1402, n1245, n758 }; + assign n1421 = 32'd538976290 >> { Ni32, n840, n1403, n1422, n1331 }; + assign n1422 = 32'd2290657416 >> { n1143, n1161, n1147, n1246, n755 }; + assign n622 = 8'h01 >> { Ni30, Ni32, Ni31 }; + assign n1423 = 8'h02 >> { Ni11, Ni13, Ni12 }; + assign n1424 = 32'd2290649256 >> { n1429, n1434, n1431, n1425, n1435 }; + assign n1425 = 16'h5111 >> { n1427, n1426, n754, n1428 }; + assign n1426 = 64'hffefffeedfcfdfce >> { n1362, n1162, n1361, Pi16, Pi17, Pi19 }; + assign n1427 = 64'hffeffdedf7e7f5e5 >> { n1353, n1348, n1359, Pi19, Pi16, Pi17 }; + assign n1428 = 32'd125240661 >> { n755, n659, n1162, n1354, Pi15 }; + assign n1429 = 16'h22a2 >> { n1350, n751, n1430, n754 }; + assign n1430 = 64'hffefffeefdedfdec >> { n1360, n1162, n1363, Pi16, Pi17, Pi19 }; + assign n1431 = 64'h0455055544554555 >> { Pi16, Ni32, n755, n1432, n1162, Pi15 }; + assign n1432 = 4'h8 >> { n1433, n1147 }; + assign n623 = 4'h8 >> { n624, n625 }; + assign n1433 = 4'h2 >> { n1174, n1144 }; + assign n1434 = 32'd134785544 >> { n1349, n747, n1364, n756, n754 }; + assign n1435 = 16'h222a >> { n1436, Ni32, n624, n1163 }; + assign n1436 = 4'h8 >> { n1150, n1151 }; + assign n1437 = 8'ha2 >> { n1438, n840, n1252 }; + assign n1438 = 64'h0080808000ffffff >> { Ni32, n1150, n1151, n602, Ni33, n585 }; + assign n1439 = 16'h222a >> { n1199, n1193, n1262, n1440 }; + assign n1440 = 16'h0080 >> { Pi20, n624, n585, Pi25 }; + assign n1441 = 32'd707406346 >> { n599, n1191, n1262, n1193, n1442 }; + assign n1442 = 16'h8000 >> { n585, n624, Pi20, Pi25 }; + assign n624 = 4'h8 >> { Pi22, Pi21 }; + assign n1443 = 8'h08 >> { n585, n624, Pi25 }; + assign n1444 = 64'hfd00ff00fd00fd00 >> { n1443, n1348, n748, n1446, n1445, n1437 }; + assign n1445 = 32'd2290657416 >> { n1146, n1147, n1155, n1246, n1442 }; + assign n1446 = 32'd2290657416 >> { n1146, n1147, n1141, n1246, n1440 }; + assign n1447 = 64'hfd00ff00fd00fd00 >> { n1443, n1359, n746, n1449, n1448, n1437 }; + assign n1448 = 32'd2290657416 >> { n1206, n1147, n1211, n1246, n1442 }; + assign n1449 = 32'd2290657416 >> { n1206, n1147, n1207, n1246, n1440 }; + assign n1450 = 4'h2 >> { n585, n755 }; + assign n1451 = 64'hfd00ff00fd00fd00 >> { n1443, n1361, n758, n1441, n1439, n1437 }; + assign n1452 = 16'hfd75 >> { n1385, n1354, n585, n755 }; + assign n625 = 4'h1 >> { Pi20, Pi19 }; + assign n1453 = 64'h03570377035f03ff >> { n1180, n1178, n1246, n1442, n1440, n1147 }; + assign n1454 = 32'd17895263 >> { n1440, n1191, n1442, n1357, n1246 }; + assign n1455 = 32'd2862786720 >> { n1357, n1191, Ni32, Pi20, n1443 }; + assign n1456 = 8'h45 >> { n1450, n1351, n1457 }; + assign n1457 = 4'h2 >> { n1375, n755 }; + assign n1458 = 64'haaaaaaaaaaaaaaa2 >> { n1467, n1459, n1463, n1466, n1462, n672 }; + assign n1459 = 64'hfd00ff00fd00fd00 >> { n1443, n1349, n748, n1461, n1460, n1437 }; + assign n1460 = 32'd2290657416 >> { n1167, n1147, n1141, n1246, n1440 }; + assign n1461 = 32'd2290657416 >> { n1167, n1147, n1155, n1246, n1442 }; + assign n1462 = 8'he4 >> { n1245, n1437, n1457 }; + assign n626 = 4'h8 >> { n627, n629 }; + assign n1463 = 64'hfd00ff00fd00fd00 >> { n1443, n1360, n746, n1465, n1464, n1437 }; + assign n1464 = 32'd2290657416 >> { n1229, n1147, n1207, n1246, n1440 }; + assign n1465 = 32'd2290657416 >> { n1229, n1147, n1211, n1246, n1442 }; + assign n1466 = 32'd2315946634 >> { n1454, n1443, n1437, n1358, n758 }; + assign n1467 = 8'h02 >> { n1351, n1162, n1450 }; + assign n1468 = 8'h15 >> { Ni13, Ni12, n1238 }; + assign n1469 = 64'ha0a8a0a8a0a8a8a8 >> { n2681, n1500, n1163, n1528, n583, n1530 }; + assign n1470 = 4'h2 >> { Ni32, n1471 }; + assign n1471 = 32'd4261273085 >> { n18, n1147, n1472, n1146, n1155 }; + assign n1472 = 8'h15 >> { n1151, n1150, n1473 }; + assign n627 = 16'h22a2 >> { n628, n619, Ni38, n617 }; + assign n1473 = 8'h01 >> { Ni33, Ni30, Ni31 }; + assign n1474 = 8'h01 >> { n1140, n1475, Ni32 }; + assign n1475 = 8'h02 >> { n1146, n1472, n1141 }; + assign n1476 = 4'h2 >> { Pi25, n750 }; + assign n1477 = 8'h08 >> { Pi25, Pi20, n624 }; + assign n1478 = 32'd2829625504 >> { n1481, n1190, n1479, n1477, n759 }; + assign n1479 = 16'h888a >> { n1480, n1193, n1201, n1476 }; + assign n1480 = 32'd3721252301 >> { n18, n1472, n1357, n1159, n599 }; + assign n1481 = 32'd1145324628 >> { n1472, n1143, n1195, n599, n1193 }; + assign n1482 = 64'h8a888a88aaaa8a88 >> { n1485, n1477, n1476, n1483, n1487, n745 }; + assign n628 = 8'h02 >> { Ni41, Ni44, Ni40 }; + assign n1483 = 4'h2 >> { Ni32, n1484 }; + assign n1484 = 32'd4260756596 >> { n18, n1206, n1472, n1147, n1207 }; + assign n1485 = 8'h01 >> { n1210, n1486, Ni32 }; + assign n1486 = 8'h02 >> { n1206, n1472, n1211 }; + assign n1487 = 4'h2 >> { n1359, n754 }; + assign n1488 = 32'd33554946 >> { n757, n1489, n1428, n1492, n1495 }; + assign n1489 = 64'h5757575757570057 >> { n1491, n1198, n1477, n1490, n1197, n1476 }; + assign n1490 = 16'h4454 >> { n1472, n1203, n599, n1193 }; + assign n1491 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1195 }; + assign n1492 = 32'd134785544 >> { n1494, n1477, n1493, n1476, n756 }; + assign n629 = 16'h1151 >> { n628, n619, n631, n630 }; + assign n1493 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1225 }; + assign n1494 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1223 }; + assign n1495 = 32'd3587555541 >> { n1162, n1133, n1160, n1496, n798 }; + assign n1496 = 32'd85267733 >> { n1151, n1150, n1161, n1473, n599 }; + assign n1497 = 32'd134785544 >> { n1499, n1477, n1498, n1476, n751 }; + assign n1498 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1184 }; + assign n1499 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1186 }; + assign n1500 = 64'h0008000000080008 >> { n751, n1525, n1513, n1501, n1518, n1505 }; + assign n1501 = 64'h8a888a880a008a88 >> { Ni32, n1504, n1477, n1502, n1476, n745 }; + assign n1502 = 8'h01 >> { n1228, n1503, Ni32 }; + assign n630 = 16'heefe >> { Ni43, Ni42, Ni45, Ni47 }; + assign n1503 = 8'h02 >> { n1229, n1472, n1211 }; + assign n1504 = 32'd4261273085 >> { n18, n1147, n1472, n1229, n1207 }; + assign n1505 = 64'h3133313311113133 >> { n1508, n1477, n1476, n1506, n1510, n747 }; + assign n1506 = 8'h01 >> { n1166, n1507, Ni32 }; + assign n1507 = 8'h02 >> { n1167, n1472, n1141 }; + assign n1508 = 4'h2 >> { n1509, n1170 }; + assign n1509 = 8'h02 >> { n1167, n1472, n1155 }; + assign n1510 = 32'd134785544 >> { n1512, n1477, n1511, n1476, n756 }; + assign n1511 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1219 }; + assign n1512 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1221 }; + assign n631 = 16'h2202 >> { Ni38, Ni39, Ni36, Ni35 }; + assign n1513 = 32'd2324335114 >> { n1517, n1234, n1514, n1477, n759 }; + assign n1514 = 32'd1426421511 >> { n1516, n1162, n1515, n1232, n1476 }; + assign n1515 = 32'd2862786720 >> { n1357, n1191, Ni32, Pi20, n754 }; + assign n1516 = 16'haaae >> { n1472, n1143, n1203, n599 }; + assign n1517 = 8'h02 >> { n1472, n1143, n1195 }; + assign n1518 = 32'd8 >> { n1434, n1519, n1524, n1521, n1431 }; + assign n1519 = 64'h8a888a88aaaa8a88 >> { n1491, n1477, n1476, n1520, n1515, n757 }; + assign n1520 = 16'h5444 >> { n1472, n18, n1199, Ni32 }; + assign n1521 = 16'hdd0d >> { n1523, n1133, n1522, n798 }; + assign n1522 = 16'h1101 >> { n1472, n1433, n1261, Ni32 }; + assign n632 = 8'h08 >> { Pi20, n624, Pi19 }; + assign n1523 = 32'd1364283473 >> { n1472, n1433, n1143, n1261, Ni32 }; + assign n1524 = 8'h08 >> { n1360, n754, n745 }; + assign n1525 = 32'd3774867711 >> { Pi25, n624, n1350, n1527, n1526 }; + assign n1526 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1180 }; + assign n1527 = 64'h3131313131313111 >> { n18, Ni30, Ni31, n1472, Ni32, n1178 }; + assign n1528 = 64'h4c4c4c4c4c4c444c >> { n1434, n1429, n1431, n1425, n1529, n1435 }; + assign n1529 = 4'h1 >> { n584, Ni12 }; + assign n1530 = 4'h1 >> { Ni11, Ni10 }; + assign n1531 = 4'h2 >> { Ni11, Ni10 }; + assign n1532 = 64'h1111001101010001 >> { n2872, n2691, n1660, n595, n1642, n2968 }; + assign n564 = 1'h0; + assign n1085 = P__cmxcl_0; + assign P__cmxcl_1 = P__cmxcl_0; + assign P__cmx1ad_8 = n564; + assign P__cmx1ad_35 = n564; + assign P__cmx1ad_34 = n564; + assign P__cmx1ad_33 = n564; + assign P__cmx1ad_32 = n564; + assign P__cmx1ad_11 = n564; + assign P__cmx1ad_10 = n564; + assign P__cmx0ad_8 = n564; + assign P__cmx0ad_35 = n564; + assign P__cmx0ad_34 = n564; + assign P__cmx0ad_33 = n564; + assign P__cmx0ad_32 = n564; + assign P__cmx0ad_11 = n564; + assign P__cmx0ad_10 = n564; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/des/des.act b/openfpga_flow/benchmarks/mcnc_big20/des/des.act new file mode 100644 index 000000000..dd94119ce --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/des/des.act @@ -0,0 +1,1061 @@ +Preset_0_ 0.496400 0.513800 +Poutreg_63_ 0.501600 0.500800 +Poutreg_62_ 0.500600 0.501400 +Poutreg_61_ 0.490600 0.510400 +Poutreg_60_ 0.494200 0.507400 +Poutreg_59_ 0.490600 0.491600 +Poutreg_58_ 0.501000 0.500400 +Poutreg_57_ 0.508600 0.501600 +Poutreg_56_ 0.515000 0.512000 +Poutreg_55_ 0.493800 0.508200 +Poutreg_54_ 0.493400 0.502800 +Poutreg_53_ 0.509800 0.505200 +Poutreg_52_ 0.507600 0.503200 +Poutreg_51_ 0.491400 0.502000 +Poutreg_50_ 0.519000 0.500400 +Poutreg_49_ 0.488400 0.495000 +Poutreg_48_ 0.494000 0.496000 +Poutreg_47_ 0.482600 0.492800 +Poutreg_46_ 0.497000 0.497200 +Poutreg_45_ 0.499000 0.504200 +Poutreg_44_ 0.499800 0.502600 +Poutreg_43_ 0.493600 0.490400 +Poutreg_42_ 0.500800 0.501600 +Poutreg_41_ 0.502200 0.503400 +Poutreg_40_ 0.495800 0.503200 +Poutreg_39_ 0.496600 0.504400 +Poutreg_38_ 0.497000 0.492200 +Poutreg_37_ 0.501000 0.498000 +Poutreg_36_ 0.490400 0.507000 +Poutreg_35_ 0.495200 0.491200 +Poutreg_34_ 0.506400 0.516200 +Poutreg_33_ 0.497000 0.499000 +Poutreg_32_ 0.496400 0.499000 +Poutreg_31_ 0.498200 0.506200 +Poutreg_30_ 0.497400 0.500800 +Poutreg_29_ 0.502400 0.496600 +Poutreg_28_ 0.505800 0.510800 +Poutreg_27_ 0.509600 0.503400 +Poutreg_26_ 0.493800 0.501600 +Poutreg_25_ 0.494600 0.485800 +Poutreg_24_ 0.481000 0.499000 +Poutreg_23_ 0.506400 0.507000 +Poutreg_22_ 0.499400 0.503200 +Poutreg_21_ 0.496000 0.497600 +Poutreg_20_ 0.508400 0.502600 +Poutreg_19_ 0.491400 0.494200 +Poutreg_18_ 0.493600 0.501600 +Poutreg_17_ 0.495400 0.498400 +Poutreg_16_ 0.508200 0.503000 +Poutreg_15_ 0.501000 0.510400 +Poutreg_14_ 0.502600 0.495000 +Poutreg_13_ 0.514000 0.494200 +Poutreg_12_ 0.502200 0.500000 +Poutreg_11_ 0.503200 0.501400 +Poutreg_10_ 0.492400 0.485400 +Poutreg_9_ 0.490000 0.490200 +Poutreg_8_ 0.499600 0.493000 +Poutreg_7_ 0.498200 0.508400 +Poutreg_6_ 0.492400 0.500000 +Poutreg_5_ 0.502400 0.507000 +Poutreg_4_ 0.506000 0.499600 +Poutreg_3_ 0.494200 0.495000 +Poutreg_2_ 0.507800 0.507800 +Poutreg_1_ 0.502800 0.504000 +Poutreg_0_ 0.506200 0.502400 +Pload_key_0_ 0.499600 0.493200 +Pinreg_55_ 0.485200 0.504200 +Pinreg_54_ 0.502400 0.506000 +Pinreg_53_ 0.494000 0.503400 +Pinreg_52_ 0.495600 0.510600 +Pinreg_51_ 0.512800 0.493400 +Pinreg_50_ 0.501000 0.512000 +Pinreg_49_ 0.493400 0.508400 +Pinreg_48_ 0.500400 0.499000 +Pinreg_47_ 0.501200 0.508800 +Pinreg_46_ 0.492800 0.497800 +Pinreg_45_ 0.514000 0.488400 +Pinreg_44_ 0.496400 0.512200 +Pinreg_43_ 0.499200 0.497800 +Pinreg_42_ 0.488800 0.499800 +Pinreg_41_ 0.502600 0.504000 +Pinreg_40_ 0.488200 0.502000 +Pinreg_39_ 0.505200 0.489000 +Pinreg_38_ 0.501200 0.500400 +Pinreg_37_ 0.490400 0.484400 +Pinreg_36_ 0.497800 0.507000 +Pinreg_35_ 0.503400 0.507400 +Pinreg_34_ 0.491600 0.490200 +Pinreg_33_ 0.503000 0.506600 +Pinreg_32_ 0.499200 0.486800 +Pinreg_31_ 0.511000 0.500800 +Pinreg_30_ 0.510400 0.493400 +Pinreg_29_ 0.511000 0.499200 +Pinreg_28_ 0.499200 0.505000 +Pinreg_27_ 0.505000 0.502600 +Pinreg_26_ 0.506800 0.489400 +Pinreg_25_ 0.503400 0.482600 +Pinreg_24_ 0.511000 0.496600 +Pinreg_23_ 0.508600 0.493800 +Pinreg_22_ 0.487200 0.492200 +Pinreg_21_ 0.500800 0.503200 +Pinreg_20_ 0.488200 0.499600 +Pinreg_19_ 0.505400 0.497400 +Pinreg_18_ 0.501400 0.488800 +Pinreg_17_ 0.489000 0.499000 +Pinreg_16_ 0.500200 0.495600 +Pinreg_15_ 0.501800 0.504400 +Pinreg_14_ 0.499800 0.506400 +Pinreg_13_ 0.499000 0.496800 +Pinreg_12_ 0.506600 0.492200 +Pinreg_11_ 0.499400 0.493600 +Pinreg_10_ 0.504200 0.492200 +Pinreg_9_ 0.500200 0.489400 +Pinreg_8_ 0.498600 0.497800 +Pinreg_7_ 0.500000 0.492800 +Pinreg_6_ 0.498400 0.507200 +Pinreg_5_ 0.502200 0.496400 +Pinreg_4_ 0.505000 0.504400 +Pinreg_3_ 0.493600 0.506800 +Pinreg_2_ 0.507800 0.498600 +Pinreg_1_ 0.506000 0.493600 +Pinreg_0_ 0.504600 0.499200 +Pencrypt_mode_0_ 0.486200 0.493400 +Pencrypt_0_ 0.485800 0.496400 +Pdata_in_7_ 0.499200 0.489400 +Pdata_in_6_ 0.498200 0.511400 +Pdata_in_5_ 0.502200 0.490400 +Pdata_in_4_ 0.498600 0.502600 +Pdata_in_3_ 0.492400 0.501800 +Pdata_in_2_ 0.499200 0.495000 +Pdata_in_1_ 0.513400 0.491800 +Pdata_in_0_ 0.494600 0.499600 +Pdata_63_ 0.503600 0.509000 +Pdata_62_ 0.494400 0.495200 +Pdata_61_ 0.500000 0.516600 +Pdata_60_ 0.504600 0.487600 +Pdata_59_ 0.501800 0.501600 +Pdata_58_ 0.499800 0.493200 +Pdata_57_ 0.496000 0.492200 +Pdata_56_ 0.497000 0.496200 +Pdata_55_ 0.506000 0.493200 +Pdata_54_ 0.516400 0.504400 +Pdata_53_ 0.496400 0.500000 +Pdata_52_ 0.495400 0.496400 +Pdata_51_ 0.508600 0.509200 +Pdata_50_ 0.503000 0.496400 +Pdata_49_ 0.504000 0.491400 +Pdata_48_ 0.499800 0.501800 +Pdata_47_ 0.499000 0.501800 +Pdata_46_ 0.497600 0.496800 +Pdata_45_ 0.493800 0.498400 +Pdata_44_ 0.487400 0.495400 +Pdata_43_ 0.502800 0.509800 +Pdata_42_ 0.506800 0.491000 +Pdata_41_ 0.499400 0.493400 +Pdata_40_ 0.510000 0.515400 +Pdata_39_ 0.499600 0.494000 +Pdata_38_ 0.503800 0.488000 +Pdata_37_ 0.507600 0.504600 +Pdata_36_ 0.498400 0.496800 +Pdata_35_ 0.511000 0.496400 +Pdata_34_ 0.498200 0.506200 +Pdata_33_ 0.493800 0.501200 +Pdata_32_ 0.504600 0.494200 +Pdata_31_ 0.503600 0.517800 +Pdata_30_ 0.502000 0.496600 +Pdata_29_ 0.504400 0.501600 +Pdata_28_ 0.515000 0.500200 +Pdata_27_ 0.502400 0.497000 +Pdata_26_ 0.503400 0.504800 +Pdata_25_ 0.501000 0.503800 +Pdata_24_ 0.492600 0.500000 +Pdata_23_ 0.490200 0.491600 +Pdata_22_ 0.502600 0.487000 +Pdata_21_ 0.495600 0.496200 +Pdata_20_ 0.491400 0.493200 +Pdata_19_ 0.491000 0.502400 +Pdata_18_ 0.508000 0.506600 +Pdata_17_ 0.498200 0.490000 +Pdata_16_ 0.499600 0.489200 +Pdata_15_ 0.507000 0.496400 +Pdata_14_ 0.503400 0.498200 +Pdata_13_ 0.504600 0.510800 +Pdata_12_ 0.493400 0.500400 +Pdata_11_ 0.499200 0.497000 +Pdata_10_ 0.505800 0.495000 +Pdata_9_ 0.502800 0.511600 +Pdata_8_ 0.504200 0.499200 +Pdata_7_ 0.502000 0.495000 +Pdata_6_ 0.490200 0.503400 +Pdata_5_ 0.501000 0.490600 +Pdata_4_ 0.501200 0.494400 +Pdata_3_ 0.503000 0.496400 +Pdata_2_ 0.488600 0.509000 +Pdata_1_ 0.493800 0.498400 +Pdata_0_ 0.494800 0.502000 +Pcount_3_ 0.494800 0.502000 +Pcount_2_ 0.496200 0.481200 +Pcount_1_ 0.506800 0.510600 +Pcount_0_ 0.498000 0.494600 +PD_27_ 0.498600 0.503800 +PD_26_ 0.499800 0.507000 +PD_25_ 0.502200 0.493600 +PD_24_ 0.504800 0.512800 +PD_23_ 0.496400 0.491400 +PD_22_ 0.509000 0.502800 +PD_21_ 0.507800 0.492800 +PD_20_ 0.502600 0.494600 +PD_19_ 0.505000 0.488400 +PD_18_ 0.505400 0.505800 +PD_17_ 0.493000 0.495000 +PD_16_ 0.490400 0.501000 +PD_15_ 0.495800 0.499800 +PD_14_ 0.490400 0.505600 +PD_13_ 0.492000 0.501800 +PD_12_ 0.507400 0.501800 +PD_11_ 0.499200 0.507800 +PD_10_ 0.495000 0.501200 +PD_9_ 0.498000 0.503000 +PD_8_ 0.491600 0.511400 +PD_7_ 0.497600 0.510400 +PD_6_ 0.508800 0.497200 +PD_5_ 0.505400 0.501200 +PD_4_ 0.498800 0.503000 +PD_3_ 0.494200 0.515000 +PD_2_ 0.490000 0.493400 +PD_1_ 0.503400 0.500000 +PD_0_ 0.498200 0.508000 +PC_27_ 0.510200 0.503400 +PC_26_ 0.485400 0.504000 +PC_25_ 0.516800 0.492000 +PC_24_ 0.505400 0.493600 +PC_23_ 0.496200 0.520800 +PC_22_ 0.505800 0.503600 +PC_21_ 0.509600 0.490800 +PC_20_ 0.504000 0.498600 +PC_19_ 0.498000 0.494800 +PC_18_ 0.498600 0.495400 +PC_17_ 0.495200 0.493200 +PC_16_ 0.493200 0.491600 +PC_15_ 0.494400 0.506400 +PC_14_ 0.507200 0.510800 +PC_13_ 0.519000 0.493000 +PC_12_ 0.501800 0.502800 +PC_11_ 0.504000 0.490400 +PC_10_ 0.500600 0.489400 +PC_9_ 0.508200 0.499400 +PC_8_ 0.499400 0.504000 +PC_7_ 0.496600 0.490600 +PC_6_ 0.507200 0.511400 +PC_5_ 0.502000 0.501400 +PC_4_ 0.490200 0.498800 +PC_3_ 0.502200 0.501000 +PC_2_ 0.496600 0.502400 +PC_1_ 0.510400 0.505000 +PC_0_ 0.501400 0.523800 +Poutreg_new_7_ 0.507000 0.144232 +n505 0.510600 0.017764 +n506 0.941000 0.047883 +n507 0.026200 0.037189 +n508 0.237200 0.076794 +n509 0.249600 0.038382 +n510 0.502200 0.125068 +n511 0.241600 0.077611 +n512 0.065800 0.057485 +n513 0.508800 0.125030 +n514 0.505800 0.125064 +n515 0.252400 0.078305 +n516 0.258800 0.077897 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0.000923 +n558 0.503400 0.124980 +n559 0.248800 0.079106 +n560 0.248600 0.039212 +n561 0.503000 0.125065 +n562 0.125200 0.003420 +n563 0.058400 0.055365 +n564 0.249800 0.076255 +n565 0.034000 0.015229 +n566 0.499800 0.031278 +n567 0.253200 0.039115 +n568 0.014600 0.000526 +n569 0.131000 0.015175 +n570 0.032800 0.000932 +n571 0.246400 0.079989 +n572 0.066200 0.001886 +n573 0.130800 0.015184 +Poutreg_new_4_ 0.493400 0.111316 +Poutreg_new_3_ 0.502000 0.142745 +n576 0.923400 0.001908 +n577 0.013600 0.002102 +n578 0.970000 0.002026 +n579 0.048200 0.012843 +n580 0.061800 0.001659 +n581 0.124400 0.003424 +n582 0.621600 0.008753 +Poutreg_new_2_ 0.499800 0.111919 +Poutreg_new_1_ 0.501800 0.143278 +n585 0.879400 0.009025 +n586 0.870400 0.162254 +n587 0.509400 0.125013 +n588 0.505200 0.125025 +n589 0.495600 0.125037 +n590 0.503000 0.125022 +n591 0.031200 0.000959 +n592 0.494000 0.124969 +n593 0.127200 0.074977 +n594 0.246800 0.040066 +n595 0.252200 0.078245 +n596 0.488000 0.031270 +n597 0.238400 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0.222257 +n1042 0.988200 0.000077 +n1043 0.860200 0.016381 +PD_new_10_ 0.257200 0.263437 +n1045 0.986000 0.000077 +n1046 0.779000 0.020749 +PD_new_9_ 0.252600 0.223401 +n1048 0.986600 0.000077 +n1049 0.857000 0.008900 +PD_new_8_ 0.256200 0.266939 +n1051 0.985800 0.000078 +n1052 0.779400 0.019665 +PD_new_7_ 0.253000 0.269460 +n1054 0.988000 0.000076 +n1055 0.782000 0.019899 +PD_new_6_ 0.244800 0.131238 +n1057 0.992600 0.000052 +n1058 0.789200 0.020116 +PD_new_5_ 0.247400 0.223024 +n1060 0.987200 0.000075 +n1061 0.858200 0.016648 +PD_new_4_ 0.251800 0.224895 +n1063 0.986800 0.000076 +n1064 0.856400 0.016812 +PD_new_3_ 0.250600 0.221019 +n1066 0.988000 0.000077 +n1067 0.857800 0.009071 +PD_new_2_ 0.246800 0.264066 +n1069 0.987000 0.000079 +n1070 0.791000 0.020640 +PD_new_1_ 0.252200 0.070343 +n1072 0.991800 0.000053 +n1073 0.851400 0.008651 +PD_new_0_ 0.248000 0.222809 +n1075 0.988200 0.000076 +n1076 0.853600 0.016293 +PC_new_27_ 0.250600 0.224533 +n1078 0.985600 0.000075 +n1079 0.860600 0.009130 +PC_new_26_ 0.251800 0.222747 +n1081 0.988000 0.000079 +n1082 0.856400 0.008945 +PC_new_25_ 0.247400 0.224232 +n1084 0.985400 0.000074 +n1085 0.859200 0.016546 +PC_new_24_ 0.249400 0.220133 +n1087 0.987800 0.000076 +n1088 0.855600 0.015944 +PC_new_23_ 0.256800 0.267632 +n1090 0.987600 0.000078 +n1091 0.779000 0.020490 +PC_new_22_ 0.255400 0.271879 +n1093 0.986600 0.000076 +n1094 0.780600 0.020077 +PC_new_21_ 0.250000 0.135259 +n1096 0.991600 0.000052 +n1097 0.785600 0.020219 +PC_new_20_ 0.256200 0.223356 +n1099 0.986200 0.000076 +n1100 0.851200 0.009071 +PC_new_19_ 0.250200 0.264084 +n1102 0.986400 0.000077 +n1103 0.785800 0.020545 +PC_new_18_ 0.257200 0.222011 +n1105 0.986200 0.000077 +n1106 0.852600 0.009011 +PC_new_17_ 0.251800 0.110993 +n1108 0.992800 0.000053 +n1109 0.856800 0.016595 +PC_new_16_ 0.244600 0.221260 +n1111 0.987600 0.000077 +n1112 0.866200 0.008855 +PC_new_15_ 0.250200 0.269648 +n1114 0.987000 0.000078 +n1115 0.785400 0.019186 +PC_new_14_ 0.250800 0.269271 +n1117 0.987200 0.000077 +n1118 0.789800 0.020410 +PC_new_13_ 0.258600 0.224227 +n1120 0.984800 0.000074 +n1121 0.850600 0.016001 +PC_new_12_ 0.252200 0.222506 +n1123 0.989800 0.000075 +n1124 0.854800 0.016201 +PC_new_11_ 0.270800 0.140755 +n1126 0.990800 0.000050 +n1127 0.842000 0.009420 +PC_new_10_ 0.249800 0.267117 +n1129 0.988000 0.000077 +n1130 0.784800 0.020258 +PC_new_9_ 0.248400 0.223109 +n1132 0.986000 0.000075 +n1133 0.857800 0.008989 +PC_new_8_ 0.246600 0.221941 +n1135 0.985400 0.000076 +n1136 0.859400 0.015885 +PC_new_7_ 0.261000 0.273058 +n1138 0.985600 0.000076 +n1139 0.778200 0.020236 +PC_new_6_ 0.247600 0.266047 +n1141 0.985800 0.000075 +n1142 0.789000 0.020646 +PC_new_5_ 0.245400 0.222222 +n1144 0.987600 0.000076 +n1145 0.857400 0.008813 +PC_new_4_ 0.255400 0.270712 +n1147 0.986400 0.000078 +n1148 0.780000 0.020489 +PC_new_3_ 0.247800 0.222515 +n1150 0.988400 0.000077 +n1151 0.860000 0.008951 +PC_new_2_ 0.253400 0.219661 +n1153 0.985800 0.000078 +n1154 0.856200 0.016113 +PC_new_1_ 0.257200 0.069495 +n1156 0.992200 0.000053 +n1157 0.854600 0.015532 +PC_new_0_ 0.246400 0.219550 +n1159 0.988200 0.000075 +n1160 0.860800 0.017139 +Poutreg_new_63_ 0.281200 0.098269 +Poutreg_new_62_ 0.284200 0.044692 +Poutreg_new_61_ 0.280200 0.101875 +Poutreg_new_60_ 0.279000 0.045801 +Poutreg_new_59_ 0.280400 0.100909 +Poutreg_new_58_ 0.285200 0.044487 +Poutreg_new_57_ 0.285400 0.095578 +Poutreg_new_56_ 0.290400 0.042788 +Poutreg_new_55_ 0.502000 0.144080 +Poutreg_new_54_ 0.493000 0.113166 +Poutreg_new_53_ 0.497800 0.212019 +n1172 0.534400 0.122476 +Poutreg_new_52_ 0.501800 0.112671 +Poutreg_new_51_ 0.484800 0.144772 +Poutreg_new_50_ 0.507200 0.109963 +Poutreg_new_49_ 0.499400 0.207289 +n1177 0.529600 0.120441 +Poutreg_new_48_ 0.489600 0.111585 +Poutreg_new_47_ 0.492400 0.146298 +Poutreg_new_46_ 0.491000 0.113384 +Poutreg_new_45_ 0.493400 0.141990 +Poutreg_new_44_ 0.501000 0.111720 +Poutreg_new_43_ 0.491000 0.144251 +Poutreg_new_42_ 0.516200 0.110111 +Poutreg_new_41_ 0.500800 0.143923 +Poutreg_new_40_ 0.499800 0.113413 +Poutreg_new_39_ 0.488000 0.205314 +n1188 0.542400 0.118688 +Poutreg_new_38_ 0.492000 0.112407 +Poutreg_new_37_ 0.505000 0.110046 +Poutreg_new_36_ 0.498200 0.114030 +Poutreg_new_35_ 0.499400 0.142831 +Poutreg_new_34_ 0.504800 0.112392 +Poutreg_new_33_ 0.491800 0.141815 +Poutreg_new_32_ 0.501400 0.113389 +Poutreg_new_31_ 0.494200 0.144240 +Poutreg_new_30_ 0.508800 0.112598 +Poutreg_new_29_ 0.501200 0.215799 +n1199 0.529000 0.121376 +Poutreg_new_28_ 0.494000 0.113662 +Poutreg_new_27_ 0.501000 0.214508 +n1202 0.528200 0.121852 +Poutreg_new_26_ 0.499000 0.113065 +Poutreg_new_25_ 0.494400 0.209315 +n1205 0.536200 0.119183 +Poutreg_new_24_ 0.487600 0.114823 +Poutreg_new_23_ 0.508200 0.142942 +Poutreg_new_22_ 0.488800 0.112855 +Poutreg_new_21_ 0.508400 0.142457 +Poutreg_new_20_ 0.512000 0.111232 +Poutreg_new_19_ 0.498200 0.142368 +Poutreg_new_18_ 0.495800 0.113859 +Poutreg_new_17_ 0.491800 0.142902 +Poutreg_new_16_ 0.493000 0.113832 +Poutreg_new_15_ 0.497600 0.142827 +Poutreg_new_14_ 0.504000 0.111868 +Poutreg_new_13_ 0.503000 0.139416 +Poutreg_new_12_ 0.508800 0.111276 +Poutreg_new_11_ 0.493800 0.142991 +Poutreg_new_10_ 0.492000 0.113157 +Poutreg_new_9_ 0.487400 0.206707 +n1222 0.542200 0.118600 +Poutreg_new_8_ 0.507800 0.111144 +n1224 0.904400 0.003702 +n1225 0.495400 0.002798 +n1226 0.499800 0.003537 +n1227 0.942000 0.081267 +n1228 0.691600 0.046174 +n1229 0.763200 0.033775 +n1230 0.504400 0.002256 +n1231 0.133200 0.007268 +n1232 0.938800 0.019923 +n1233 0.190200 0.030376 +n1234 0.755600 0.094384 +n1235 0.935400 0.001781 +n1236 0.126000 0.006869 +n1237 0.941800 0.007368 +n1238 0.953000 0.006075 +n1239 0.936600 0.086698 +n1240 0.060400 0.073006 +n1241 0.955000 0.077420 +n1242 0.268800 0.089618 +n1243 0.845400 0.099781 +n1244 0.953800 0.002083 +n1245 0.556400 0.036004 +n1246 0.914600 0.031390 +n1247 0.813400 0.090201 +n1248 0.495000 0.115827 +n1249 0.953400 0.005657 +n1250 0.153400 0.043216 +n1251 0.969400 0.000867 +n1252 0.938400 0.056054 +n1253 0.114600 0.006233 +n1254 0.828000 0.021776 +n1255 0.948400 0.002603 +n1256 0.488200 0.278311 +n1257 0.094200 0.003898 +n1258 0.868200 0.000473 +n1259 0.058400 0.108583 +n1260 0.937400 0.025970 +n1261 0.911200 0.004316 +n1262 0.638800 0.000152 +n1263 0.503800 0.265277 +n1264 0.839800 0.031692 +n1265 0.636600 0.013147 +n1266 0.491200 0.260715 +n1267 0.243800 0.053268 +n1268 0.893000 0.006759 +n1269 0.503600 0.275932 +n1270 0.918800 0.072270 +n1271 0.872600 0.004353 +n1272 0.824600 0.026962 +n1273 0.496200 0.276708 +n1274 0.700000 0.014547 +n1275 0.920200 0.003806 +n1276 0.891800 0.129968 +n1277 0.514200 0.287805 +n1278 0.768800 0.017531 +n1279 0.493400 0.103330 +n1280 0.798800 0.096082 +n1281 0.626600 0.003384 +n1282 0.096600 0.027205 +n1283 0.714200 0.002592 +n1284 0.492400 0.131278 +n1285 0.905600 0.074173 +n1286 0.791400 0.008354 +n1287 0.444400 0.089888 +n1288 0.793800 0.021495 +n1289 0.517600 0.139500 +n1290 0.843800 0.005932 +n1291 0.505200 0.272961 +n1292 0.544000 0.048086 +n1293 0.942200 0.047635 +n1294 0.857400 0.051323 +n1295 0.662400 0.068173 +n1296 0.507400 0.093122 +n1297 0.871600 0.007992 +n1298 0.507000 0.286710 +n1299 0.660600 0.074918 +n1300 0.828200 0.049001 +n1301 0.705400 0.092419 +n1302 0.786600 0.095315 +n1303 0.505400 0.005168 +n1304 0.844600 0.128066 +n1305 0.901000 0.107092 +n1306 0.623600 0.001055 +n1307 0.935600 0.105121 +n1308 0.836200 0.039314 diff --git a/openfpga_flow/benchmarks/mcnc_big20/des/des.blif b/openfpga_flow/benchmarks/mcnc_big20/des/des.blif new file mode 100644 index 000000000..e64cd5e3f --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/des/des.blif @@ -0,0 +1,3276 @@ +# Benchmark "des" written by ABC on Tue Mar 12 09:37:51 2019 +.model des +.inputs Preset_0_ Poutreg_63_ Poutreg_62_ Poutreg_61_ Poutreg_60_ \ + Poutreg_59_ Poutreg_58_ Poutreg_57_ Poutreg_56_ Poutreg_55_ Poutreg_54_ \ + Poutreg_53_ Poutreg_52_ Poutreg_51_ Poutreg_50_ Poutreg_49_ Poutreg_48_ \ + Poutreg_47_ Poutreg_46_ Poutreg_45_ Poutreg_44_ Poutreg_43_ Poutreg_42_ \ + Poutreg_41_ Poutreg_40_ Poutreg_39_ Poutreg_38_ Poutreg_37_ Poutreg_36_ \ + Poutreg_35_ Poutreg_34_ Poutreg_33_ Poutreg_32_ Poutreg_31_ Poutreg_30_ \ + Poutreg_29_ Poutreg_28_ Poutreg_27_ Poutreg_26_ Poutreg_25_ Poutreg_24_ \ + Poutreg_23_ Poutreg_22_ Poutreg_21_ Poutreg_20_ Poutreg_19_ Poutreg_18_ \ + Poutreg_17_ Poutreg_16_ Poutreg_15_ Poutreg_14_ Poutreg_13_ Poutreg_12_ \ + Poutreg_11_ Poutreg_10_ Poutreg_9_ Poutreg_8_ Poutreg_7_ Poutreg_6_ \ + Poutreg_5_ Poutreg_4_ Poutreg_3_ Poutreg_2_ Poutreg_1_ Poutreg_0_ \ + Pload_key_0_ Pinreg_55_ Pinreg_54_ Pinreg_53_ Pinreg_52_ Pinreg_51_ \ + Pinreg_50_ Pinreg_49_ Pinreg_48_ Pinreg_47_ Pinreg_46_ Pinreg_45_ \ + Pinreg_44_ Pinreg_43_ Pinreg_42_ Pinreg_41_ Pinreg_40_ Pinreg_39_ \ + Pinreg_38_ Pinreg_37_ Pinreg_36_ Pinreg_35_ Pinreg_34_ Pinreg_33_ \ + Pinreg_32_ Pinreg_31_ Pinreg_30_ Pinreg_29_ Pinreg_28_ Pinreg_27_ \ + Pinreg_26_ Pinreg_25_ Pinreg_24_ Pinreg_23_ Pinreg_22_ Pinreg_21_ \ + Pinreg_20_ Pinreg_19_ Pinreg_18_ Pinreg_17_ Pinreg_16_ Pinreg_15_ \ + Pinreg_14_ Pinreg_13_ Pinreg_12_ Pinreg_11_ Pinreg_10_ Pinreg_9_ Pinreg_8_ \ + Pinreg_7_ Pinreg_6_ Pinreg_5_ Pinreg_4_ Pinreg_3_ Pinreg_2_ Pinreg_1_ \ + Pinreg_0_ Pencrypt_mode_0_ Pencrypt_0_ Pdata_in_7_ Pdata_in_6_ Pdata_in_5_ \ + Pdata_in_4_ Pdata_in_3_ Pdata_in_2_ Pdata_in_1_ Pdata_in_0_ Pdata_63_ \ + Pdata_62_ Pdata_61_ Pdata_60_ Pdata_59_ Pdata_58_ Pdata_57_ Pdata_56_ \ + Pdata_55_ Pdata_54_ Pdata_53_ Pdata_52_ Pdata_51_ Pdata_50_ Pdata_49_ \ + Pdata_48_ Pdata_47_ Pdata_46_ Pdata_45_ Pdata_44_ Pdata_43_ Pdata_42_ \ + Pdata_41_ Pdata_40_ Pdata_39_ Pdata_38_ Pdata_37_ Pdata_36_ Pdata_35_ \ + Pdata_34_ Pdata_33_ Pdata_32_ Pdata_31_ Pdata_30_ Pdata_29_ Pdata_28_ \ + Pdata_27_ Pdata_26_ Pdata_25_ Pdata_24_ Pdata_23_ Pdata_22_ Pdata_21_ \ + Pdata_20_ Pdata_19_ Pdata_18_ Pdata_17_ Pdata_16_ Pdata_15_ Pdata_14_ \ + Pdata_13_ Pdata_12_ Pdata_11_ Pdata_10_ Pdata_9_ Pdata_8_ Pdata_7_ \ + Pdata_6_ Pdata_5_ Pdata_4_ Pdata_3_ Pdata_2_ Pdata_1_ Pdata_0_ Pcount_3_ \ + Pcount_2_ Pcount_1_ Pcount_0_ PD_27_ PD_26_ PD_25_ PD_24_ PD_23_ PD_22_ \ + PD_21_ PD_20_ PD_19_ PD_18_ PD_17_ PD_16_ PD_15_ PD_14_ PD_13_ PD_12_ \ + PD_11_ PD_10_ PD_9_ PD_8_ PD_7_ PD_6_ PD_5_ PD_4_ PD_3_ PD_2_ PD_1_ PD_0_ \ + PC_27_ PC_26_ PC_25_ PC_24_ PC_23_ PC_22_ PC_21_ PC_20_ PC_19_ PC_18_ \ + PC_17_ PC_16_ PC_15_ PC_14_ PC_13_ PC_12_ PC_11_ PC_10_ PC_9_ PC_8_ PC_7_ \ + PC_6_ PC_5_ PC_4_ PC_3_ PC_2_ PC_1_ PC_0_ +.outputs Poutreg_new_63_ Poutreg_new_62_ Poutreg_new_61_ Poutreg_new_60_ \ + Poutreg_new_59_ Poutreg_new_58_ Poutreg_new_57_ Poutreg_new_56_ \ + Poutreg_new_55_ Poutreg_new_54_ Poutreg_new_53_ Poutreg_new_52_ \ + Poutreg_new_51_ Poutreg_new_50_ Poutreg_new_49_ Poutreg_new_48_ \ + Poutreg_new_47_ Poutreg_new_46_ Poutreg_new_45_ Poutreg_new_44_ \ + Poutreg_new_43_ Poutreg_new_42_ Poutreg_new_41_ Poutreg_new_40_ \ + Poutreg_new_39_ Poutreg_new_38_ Poutreg_new_37_ Poutreg_new_36_ \ + Poutreg_new_35_ Poutreg_new_34_ Poutreg_new_33_ Poutreg_new_32_ \ + Poutreg_new_31_ Poutreg_new_30_ Poutreg_new_29_ Poutreg_new_28_ \ + Poutreg_new_27_ Poutreg_new_26_ Poutreg_new_25_ Poutreg_new_24_ \ + Poutreg_new_23_ Poutreg_new_22_ Poutreg_new_21_ Poutreg_new_20_ \ + Poutreg_new_19_ Poutreg_new_18_ Poutreg_new_17_ Poutreg_new_16_ \ + Poutreg_new_15_ Poutreg_new_14_ Poutreg_new_13_ Poutreg_new_12_ \ + Poutreg_new_11_ Poutreg_new_10_ Poutreg_new_9_ Poutreg_new_8_ \ + Poutreg_new_7_ Poutreg_new_6_ Poutreg_new_5_ Poutreg_new_4_ Poutreg_new_3_ \ + Poutreg_new_2_ Poutreg_new_1_ Poutreg_new_0_ Pinreg_new_55_ Pinreg_new_54_ \ + Pinreg_new_53_ Pinreg_new_52_ Pinreg_new_51_ Pinreg_new_50_ Pinreg_new_49_ \ + Pinreg_new_48_ Pinreg_new_47_ Pinreg_new_46_ Pinreg_new_45_ Pinreg_new_44_ \ + Pinreg_new_43_ Pinreg_new_42_ Pinreg_new_41_ Pinreg_new_40_ Pinreg_new_39_ \ + Pinreg_new_38_ Pinreg_new_37_ Pinreg_new_36_ Pinreg_new_35_ Pinreg_new_34_ \ + Pinreg_new_33_ Pinreg_new_32_ Pinreg_new_31_ Pinreg_new_30_ Pinreg_new_29_ \ + Pinreg_new_28_ Pinreg_new_27_ Pinreg_new_26_ Pinreg_new_25_ Pinreg_new_24_ \ + Pinreg_new_23_ Pinreg_new_22_ Pinreg_new_21_ Pinreg_new_20_ Pinreg_new_19_ \ + Pinreg_new_18_ Pinreg_new_17_ Pinreg_new_16_ Pinreg_new_15_ Pinreg_new_14_ \ + Pinreg_new_13_ Pinreg_new_12_ Pinreg_new_11_ Pinreg_new_10_ Pinreg_new_9_ \ + Pinreg_new_8_ Pinreg_new_7_ Pinreg_new_6_ Pinreg_new_5_ Pinreg_new_4_ \ + Pinreg_new_3_ Pinreg_new_2_ Pinreg_new_1_ Pinreg_new_0_ \ + Pencrypt_mode_new_0_ Pdata_new_63_ Pdata_new_62_ Pdata_new_61_ \ + Pdata_new_60_ Pdata_new_59_ Pdata_new_58_ Pdata_new_57_ Pdata_new_56_ \ + Pdata_new_55_ Pdata_new_54_ Pdata_new_53_ Pdata_new_52_ Pdata_new_51_ \ + Pdata_new_50_ Pdata_new_49_ Pdata_new_48_ Pdata_new_47_ Pdata_new_46_ \ + Pdata_new_45_ Pdata_new_44_ Pdata_new_43_ Pdata_new_42_ Pdata_new_41_ \ + Pdata_new_40_ Pdata_new_39_ Pdata_new_38_ Pdata_new_37_ Pdata_new_36_ \ + Pdata_new_35_ Pdata_new_34_ Pdata_new_33_ Pdata_new_32_ Pdata_new_31_ \ + Pdata_new_30_ Pdata_new_29_ Pdata_new_28_ Pdata_new_27_ Pdata_new_26_ \ + Pdata_new_25_ Pdata_new_24_ Pdata_new_23_ Pdata_new_22_ Pdata_new_21_ \ + Pdata_new_20_ Pdata_new_19_ Pdata_new_18_ Pdata_new_17_ Pdata_new_16_ \ + Pdata_new_15_ Pdata_new_14_ Pdata_new_13_ Pdata_new_12_ Pdata_new_11_ \ + Pdata_new_10_ Pdata_new_9_ Pdata_new_8_ Pdata_new_7_ Pdata_new_6_ \ + Pdata_new_5_ Pdata_new_4_ Pdata_new_3_ Pdata_new_2_ Pdata_new_1_ \ + Pdata_new_0_ Pcount_new_3_ Pcount_new_2_ Pcount_new_1_ Pcount_new_0_ \ + PD_new_27_ PD_new_26_ PD_new_25_ PD_new_24_ PD_new_23_ PD_new_22_ \ + PD_new_21_ PD_new_20_ PD_new_19_ PD_new_18_ PD_new_17_ PD_new_16_ \ + PD_new_15_ PD_new_14_ PD_new_13_ PD_new_12_ PD_new_11_ PD_new_10_ \ + PD_new_9_ PD_new_8_ PD_new_7_ PD_new_6_ PD_new_5_ PD_new_4_ PD_new_3_ \ + PD_new_2_ PD_new_1_ PD_new_0_ PC_new_27_ PC_new_26_ PC_new_25_ PC_new_24_ \ + PC_new_23_ PC_new_22_ PC_new_21_ PC_new_20_ PC_new_19_ PC_new_18_ \ + PC_new_17_ PC_new_16_ PC_new_15_ PC_new_14_ PC_new_13_ PC_new_12_ \ + PC_new_11_ PC_new_10_ PC_new_9_ PC_new_8_ PC_new_7_ PC_new_6_ PC_new_5_ \ + PC_new_4_ PC_new_3_ PC_new_2_ PC_new_1_ PC_new_0_ +.names n544 Pdata_31_ n505 Pcount_0_ Poutreg_7_ Poutreg_15_ Poutreg_new_7_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names n539 n532 n527 n525 n506 n519 n505 +111110 1 +.names n507 n516 n512 n517 n509 n518 n506 +1----- 0 +-11--- 0 +---111 0 +.names n508 n510 PD_10_ Pdata_57_ n511 n509 n507 +1000-1 1 +1011-1 1 +11011- 1 +11101- 1 +.names PD_20_ Pdata_56_ PD_27_ Pdata_58_ n508 +0100 1 +0111 1 +1000 1 +1011 1 +.names PD_15_ PD_5_ Pdata_59_ Pdata_55_ n509 +0011 1 +0101 1 +1010 1 +1100 1 +.names PD_24_ Pdata_60_ n510 +01 1 +10 1 +.names PD_5_ Pdata_59_ PD_15_ Pdata_55_ n511 +0100 1 +0111 1 +1000 1 +1011 1 +.names n515 n513 n514 n512 +110 1 +.names PD_5_ Pdata_59_ n513 +00 1 +11 1 +.names PD_15_ Pdata_55_ n514 +01 1 +10 1 +.names PD_10_ Pdata_57_ PD_24_ Pdata_60_ n515 +0100 1 +0111 1 +1000 1 +1011 1 +.names PD_20_ Pdata_56_ PD_27_ Pdata_58_ n516 +0000 1 +0011 1 +1100 1 +1111 1 +.names PD_27_ PD_20_ Pdata_56_ Pdata_58_ n517 +0011 1 +0101 1 +1010 1 +1100 1 +.names PD_24_ PD_10_ Pdata_57_ Pdata_60_ n518 +0001 1 +0111 1 +1000 1 +1110 1 +.names n520 n522 n516 n511 n519 +11-- 1 +1-11 1 +.names n521 n510 n520 +00 1 +.names PD_10_ Pdata_57_ n521 +01 1 +10 1 +.names n524 n523 n522 +11 1 +.names PD_27_ PD_20_ Pdata_56_ Pdata_58_ n523 +0001 1 +0111 1 +1000 1 +1110 1 +.names PD_15_ PD_5_ Pdata_59_ Pdata_55_ n524 +0001 1 +0111 1 +1000 1 +1110 1 +.names n518 n509 n516 n526 n513 n525 +10-11 0 +111-- 0 +.names n523 n521 n514 n526 +100 1 +.names n513 n530 n528 n508 n510 n514 n527 +0-1--- 0 +0--100 0 +-1---- 0 +.names n510 n514 n529 n521 PD_27_ Pdata_58_ n528 +1001-- 1 +101001 1 +101010 1 +110001 1 +110010 1 +.names PD_20_ Pdata_56_ n529 +01 1 +10 1 +.names n523 n524 n515 n530 +101 1 +110 1 +.names PD_24_ PD_10_ Pdata_57_ Pdata_60_ n531 +0011 1 +0101 1 +1010 1 +1100 1 +.names n533 n538 n536 n532 +000 1 +.names n517 n534 n535 n533 +110 1 +.names PD_10_ PD_24_ Pdata_57_ Pdata_60_ n534 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names PD_5_ PD_15_ Pdata_59_ Pdata_55_ n535 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names n518 n516 n513 n514 n536 +1110 1 +.names n523 n515 n511 n537 +111 1 +.names n523 n509 n521 n510 n538 +1100 1 +.names n543 n541 n540 n508 n539 +101- 1 +10-0 1 +.names n524 n531 n513 n518 n540 +0-11 0 +11-- 0 +.names n523 n521 n510 n514 n513 n541 +10000 1 +.names n523 n515 n509 n542 +111 1 +.names n524 n515 n516 n517 n543 +1000 0 +111- 0 +11-1 0 +.names Pcount_1_ Pcount_2_ Pcount_3_ Pcount_0_ n544 +1111 1 +.names Pcount_0_ n544 Pdata_63_ Poutreg_6_ Poutreg_14_ Poutreg_new_6_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1225 Pdata_23_ Pcount_0_ Poutreg_5_ Poutreg_13_ Poutreg_new_5_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names n551 n553 n555 n548 n554 n547 +00011 0 +101-1 0 +1101- 0 +.names n549 PC_3_ Pdata_42_ n550 n548 +1000 1 +1110 1 +.names PC_25_ Pdata_43_ n549 +00 1 +11 1 +.names PC_7_ Pdata_44_ n550 +01 1 +10 1 +.names n552 n549 n551 +01 1 +10 1 +.names PC_22_ Pdata_39_ n552 +00 1 +11 1 +.names PC_18_ Pdata_40_ PC_11_ Pdata_41_ n553 +0100 1 +0111 1 +1000 1 +1011 1 +.names PC_11_ PC_18_ Pdata_40_ Pdata_41_ n554 +0011 1 +0101 1 +1010 1 +1100 1 +.names PC_7_ PC_3_ Pdata_42_ Pdata_44_ n555 +0001 1 +0111 1 +1000 1 +1110 1 +.names n557 n553 n551 n560 n556 +0--- 0 +-111 0 +.names n559 n549 n558 PC_18_ Pdata_40_ n552 n557 +100001 0 +100111 0 +111010 0 +111100 0 +.names PC_11_ Pdata_41_ n558 +01 1 +10 1 +.names PC_3_ Pdata_42_ PC_7_ Pdata_44_ n559 +0100 1 +0111 1 +1000 1 +1011 1 +.names PC_7_ PC_3_ Pdata_42_ Pdata_44_ n560 +0011 1 +0101 1 +1010 1 +1100 1 +.names PC_18_ Pdata_40_ n561 +00 1 +11 1 +.names PC_3_ Pdata_42_ Pdata_43_ PC_25_ PC_22_ Pdata_39_ n562 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names n564 n549 n558 n563 +110 1 +.names PC_18_ Pdata_40_ PC_22_ Pdata_39_ n564 +0000 1 +0011 1 +1100 1 +1111 1 +.names n567 n566 n549 n558 n565 +1110 1 +.names PC_3_ PC_7_ Pdata_42_ Pdata_44_ n566 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names PC_22_ PC_18_ Pdata_40_ Pdata_39_ n567 +0001 1 +0111 1 +1000 1 +1110 1 +.names n569 n553 n552 n568 +111 1 +.names PC_3_ Pdata_42_ Pdata_43_ PC_25_ PC_7_ Pdata_44_ n569 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names n558 n571 PC_3_ Pdata_42_ n549 n570 +11010 1 +11100 1 +.names PC_18_ Pdata_40_ PC_22_ Pdata_39_ n571 +0100 1 +0111 1 +1000 1 +1011 1 +.names n566 n558 PC_18_ Pdata_40_ n549 n552 n572 +110010 1 +110100 1 +111000 1 +111110 1 +.names PC_18_ Pdata_40_ Pdata_43_ PC_25_ PC_22_ Pdata_39_ n573 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names Pcount_0_ n544 Pdata_55_ Poutreg_4_ Poutreg_12_ Poutreg_new_4_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1230 Pdata_15_ Pcount_0_ Poutreg_3_ Poutreg_11_ Poutreg_new_3_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names n565 n577 n568 n563 n555 n576 +0000- 1 +000-0 1 +.names n554 n549 PC_3_ Pdata_42_ n550 n552 n577 +110000 1 +111100 1 +.names n558 n555 n573 n559 n571 n549 n578 +011--- 0 +0--110 0 +.names n549 n552 n554 n550 n553 n559 n579 +0011-- 1 +00--11 1 +.names n567 n558 n569 n571 n559 n549 n580 +10--11 1 +1-1--- 1 +-111-- 1 +.names PC_3_ Pdata_42_ PC_25_ Pdata_43_ PC_7_ Pdata_44_ n581 +01---- 0 +10---- 0 +--01-- 0 +--10-- 0 +----00 0 +----11 0 +.names PC_22_ PC_11_ PC_18_ Pdata_40_ Pdata_41_ Pdata_39_ n582 +000111 1 +001011 1 +00--00 1 +010101 1 +011001 1 +01--10 1 +0-00-0 1 +0-11-0 1 +100110 1 +101010 1 +10--01 1 +110100 1 +111000 1 +11--11 1 +1-00-1 1 +1-11-1 1 +-0000- 1 +-0110- 1 +-1001- 1 +-1111- 1 +.names Pcount_0_ n544 Pdata_47_ Poutreg_2_ Poutreg_10_ Poutreg_new_2_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1289 Pdata_7_ Pcount_0_ Poutreg_1_ Poutreg_9_ Poutreg_new_1_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names n592 n591 n586 n597 n596 n590 n585 +1-0--- 0 +1--111 0 +-1---- 0 +.names n587 PD_18_ Pdata_51_ n590 n589 n588 n586 +100000 0 +100111 0 +101001 0 +101110 0 +110001 0 +110110 0 +111000 0 +111111 0 +.names PD_23_ Pdata_48_ n587 +01 1 +10 1 +.names PD_26_ Pdata_52_ n588 +00 1 +11 1 +.names PD_12_ Pdata_47_ n589 +01 1 +10 1 +.names PD_8_ Pdata_50_ n590 +00 1 +11 1 +.names n595 n592 n593 n594 n589 n591 +101-- 1 +11-11 1 +.names PD_2_ Pdata_49_ n592 +00 1 +11 1 +.names PD_8_ Pdata_50_ PD_18_ Pdata_51_ PD_12_ Pdata_47_ n593 +00---- 0 +11---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PD_18_ PD_8_ Pdata_50_ Pdata_51_ n594 +0011 1 +0101 1 +1010 1 +1100 1 +.names PD_23_ Pdata_48_ PD_26_ Pdata_52_ n595 +0000 1 +0011 1 +1100 1 +1111 1 +.names PD_12_ PD_18_ Pdata_51_ Pdata_47_ n596 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names PD_26_ PD_23_ Pdata_48_ Pdata_52_ n597 +0001 1 +0111 1 +1000 1 +1110 1 +.names n597 n592 n589 n600 n599 n602 n598 +101-1- 0 +110--1 0 +---1-- 0 +.names n590 PD_18_ Pdata_51_ n599 +101 1 +110 1 +.names n601 n596 n590 n592 n600 +1000 1 +.names PD_23_ Pdata_48_ PD_26_ Pdata_52_ n601 +0100 1 +0111 1 +1000 1 +1011 1 +.names PD_8_ Pdata_50_ PD_18_ Pdata_51_ n602 +0000 1 +0011 1 +1100 1 +1111 1 +.names n604 n605 n599 n602 n601 n606 n603 +1----- 0 +-11--- 0 +---111 0 +.names n597 n596 n590 n592 n604 +1000 1 +.names n595 n589 n592 n605 +110 1 +.names PD_2_ Pdata_49_ PD_12_ Pdata_47_ n606 +0100 1 +0111 1 +1000 1 +1011 1 +.names PD_26_ PD_23_ Pdata_48_ Pdata_52_ n607 +0011 1 +0101 1 +1010 1 +1100 1 +.names Pcount_0_ n544 Pdata_39_ Poutreg_0_ Poutreg_8_ Poutreg_new_0_ +0--1- 1 +10--1 1 +-11-- 1 +.names Pcount_0_ Pinreg_55_ Pinreg_47_ n544 Pinreg_new_55_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_54_ Pinreg_46_ n544 Pinreg_new_54_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_53_ Pinreg_45_ n544 Pinreg_new_53_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_52_ Pinreg_44_ n544 Pinreg_new_52_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_51_ Pinreg_43_ n544 Pinreg_new_51_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_50_ Pinreg_42_ n544 Pinreg_new_50_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_49_ Pinreg_41_ n544 Pinreg_new_49_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_48_ Pinreg_40_ n544 Pinreg_new_48_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_47_ Pinreg_39_ n544 Pinreg_new_47_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_46_ Pinreg_38_ n544 Pinreg_new_46_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_45_ Pinreg_37_ n544 Pinreg_new_45_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_44_ Pinreg_36_ n544 Pinreg_new_44_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_43_ Pinreg_35_ n544 Pinreg_new_43_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_42_ Pinreg_34_ n544 Pinreg_new_42_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_41_ Pinreg_33_ n544 Pinreg_new_41_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_40_ Pinreg_32_ n544 Pinreg_new_40_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_39_ Pinreg_31_ n544 Pinreg_new_39_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_38_ Pinreg_30_ n544 Pinreg_new_38_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_37_ Pinreg_29_ n544 Pinreg_new_37_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_36_ Pinreg_28_ n544 Pinreg_new_36_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_35_ Pinreg_27_ n544 Pinreg_new_35_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_34_ Pinreg_26_ n544 Pinreg_new_34_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_33_ Pinreg_25_ n544 Pinreg_new_33_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_32_ Pinreg_24_ n544 Pinreg_new_32_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_31_ Pinreg_23_ n544 Pinreg_new_31_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_30_ Pinreg_22_ n544 Pinreg_new_30_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_29_ Pinreg_21_ n544 Pinreg_new_29_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_28_ Pinreg_20_ n544 Pinreg_new_28_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_27_ Pinreg_19_ n544 Pinreg_new_27_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_26_ Pinreg_18_ n544 Pinreg_new_26_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_25_ Pinreg_17_ n544 Pinreg_new_25_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_24_ Pinreg_16_ n544 Pinreg_new_24_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_23_ Pinreg_15_ n544 Pinreg_new_23_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_22_ Pinreg_14_ n544 Pinreg_new_22_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_21_ Pinreg_13_ n544 Pinreg_new_21_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_20_ Pinreg_12_ n544 Pinreg_new_20_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_19_ Pinreg_11_ n544 Pinreg_new_19_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_18_ Pinreg_10_ n544 Pinreg_new_18_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_17_ Pinreg_9_ n544 Pinreg_new_17_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_16_ Pinreg_8_ n544 Pinreg_new_16_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_15_ Pinreg_7_ n544 Pinreg_new_15_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_14_ Pinreg_6_ n544 Pinreg_new_14_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_13_ Pinreg_5_ n544 Pinreg_new_13_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_12_ Pinreg_4_ n544 Pinreg_new_12_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_11_ Pinreg_3_ n544 Pinreg_new_11_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_10_ Pinreg_2_ n544 Pinreg_new_10_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_9_ Pinreg_1_ n544 Pinreg_new_9_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_8_ Pinreg_0_ n544 Pinreg_new_8_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_7_ Pdata_in_7_ n544 Pinreg_new_7_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_6_ Pdata_in_6_ n544 Pinreg_new_6_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_5_ Pdata_in_5_ n544 Pinreg_new_5_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_4_ Pdata_in_4_ n544 Pinreg_new_4_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_3_ Pdata_in_3_ n544 Pinreg_new_3_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_2_ Pdata_in_2_ n544 Pinreg_new_2_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_1_ Pdata_in_1_ n544 Pinreg_new_1_ +01-- 1 +1-10 1 +.names Pcount_0_ Pinreg_0_ Pdata_in_0_ n544 Pinreg_new_0_ +01-- 1 +1-10 1 +.names n544 Pencrypt_0_ Pencrypt_mode_0_ Pencrypt_mode_new_0_ +0-1 1 +11- 1 +.names n544 n505 Pdata_31_ Pdata_in_6_ Pdata_new_63_ +000- 1 +011- 1 +1--1 1 +.names n544 Pdata_30_ n668 Pinreg_6_ Pdata_new_62_ +000- 1 +011- 1 +1--1 1 +.names n1235 n1237 n686 n680 n677 n690 n668 +111110 1 +.names n671 n670 n669 +10 1 +.names PC_16_ Pdata_32_ n670 +01 1 +10 1 +.names PC_0_ Pdata_35_ n671 +01 1 +10 1 +.names PC_10_ Pdata_33_ n672 +01 1 +10 1 +.names PC_4_ Pdata_36_ n673 +01 1 +10 1 +.names Pdata_32_ PC_16_ PC_0_ Pdata_35_ PC_4_ Pdata_36_ n674 +00---- 0 +11---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PC_23_ Pdata_34_ n675 +01 1 +10 1 +.names PC_13_ Pdata_63_ n676 +01 1 +10 1 +.names n673 n676 n678 n679 n671 n677 +001-- 0 +10-10 0 +.names n675 n671 n670 n672 n678 +1000 1 +.names PC_16_ Pdata_32_ PC_10_ Pdata_33_ PC_23_ Pdata_34_ n679 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names n673 n669 n672 n683 n682 n681 n680 +0100-- 0 +1110-- 0 +1----0 0 +----0- 0 +.names n672 n670 n676 PC_0_ Pdata_35_ n675 n681 +00---- 1 +0-0--- 1 +111--- 1 +-0---0 1 +---01- 1 +---10- 1 +.names n685 n674 n684 n683 n682 +00-- 1 +0--0 1 +-00- 1 +.names PC_13_ PC_23_ Pdata_34_ Pdata_63_ n683 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names Pdata_32_ PC_16_ PC_23_ Pdata_34_ PC_13_ Pdata_63_ n684 +00---- 0 +11---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PC_10_ Pdata_33_ PC_23_ Pdata_34_ n685 +0100 1 +0111 1 +1000 1 +1011 1 +.names n687 n688 n672 n686 +01- 1 +0-1 1 +.names n679 n671 n676 n673 n687 +1000 1 +1110 1 +.names n671 n670 n673 n676 n675 n688 +11101 0 +11110 0 +.names PC_13_ PC_10_ Pdata_33_ Pdata_63_ n689 +0011 1 +0101 1 +1010 1 +1100 1 +.names n676 n672 n671 n670 n675 n673 n690 +110000 1 +111111 1 +.names n544 Pdata_29_ n692 Pinreg_14_ Pdata_new_61_ +000- 1 +011- 1 +1--1 1 +.names n547 n693 n1232 n1227 n556 n697 n692 +111110 1 +.names n696 n694 n695 n552 n693 +101- 1 +10-1 1 +.names n549 PC_3_ Pdata_42_ n550 n582 n564 n694 +1000-1 1 +10100- 1 +11000- 1 +1110-1 1 +.names n550 n558 n549 n561 n695 +0100 0 +1000 0 +1110 0 +.names PC_18_ Pdata_40_ n558 n552 n581 n566 n696 +0011-1 0 +001-1- 0 +01011- 0 +10011- 0 +1111-1 0 +111-1- 0 +.names n562 n561 n558 n697 +110 1 +.names n544 Pdata_28_ n699 Pinreg_22_ Pdata_new_60_ +000- 1 +011- 1 +1--1 1 +.names n730 n726 n724 n720 n712 n700 n699 +111110 1 +.names n710 n701 n705 n711 n703 n702 n700 +11---- 1 +1-0--- 1 +1--110 1 +.names n704 n702 PD_1_ Pdata_51_ n703 n701 +1100- 1 +1111- 1 +11--0 1 +.names PD_4_ Pdata_55_ n702 +01 1 +10 1 +.names PD_16_ Pdata_54_ n703 +01 1 +10 1 +.names PD_19_ PD_11_ Pdata_52_ Pdata_56_ n704 +0001 1 +0111 1 +1000 1 +1110 1 +.names PD_19_ Pdata_56_ n706 n709 n707 n708 n705 +0011-- 0 +00---1 0 +011-1- 0 +101-1- 0 +1111-- 0 +11---1 0 +.names PD_11_ Pdata_52_ n706 +01 1 +10 1 +.names Pdata_51_ PD_1_ PD_16_ Pdata_54_ PD_4_ Pdata_55_ n707 +00---- 0 +11---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PD_1_ Pdata_51_ Pdata_54_ PD_16_ PD_4_ Pdata_55_ n708 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names PD_1_ Pdata_51_ Pdata_54_ PD_16_ PD_4_ Pdata_55_ n709 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names PD_22_ Pdata_53_ n710 +01 1 +10 1 +.names PD_11_ Pdata_52_ PD_19_ Pdata_56_ n711 +0000 1 +0011 1 +1100 1 +1111 1 +.names n713 n718 n702 n719 n712 +0--- 0 +-111 0 +.names n710 n716 n714 n717 n715 n713 +0--11 0 +111-- 0 +.names PD_11_ Pdata_52_ PD_19_ Pdata_56_ n714 +0100 1 +0111 1 +1000 1 +1011 1 +.names PD_4_ PD_1_ Pdata_51_ Pdata_55_ n715 +0011 1 +0101 1 +1010 1 +1100 1 +.names PD_1_ Pdata_51_ PD_16_ Pdata_54_ PD_4_ Pdata_55_ n716 +01---- 0 +10---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PD_11_ Pdata_52_ PD_16_ Pdata_54_ PD_19_ Pdata_56_ n717 +01---- 0 +10---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PD_16_ PD_1_ Pdata_51_ Pdata_54_ n718 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names PD_11_ Pdata_52_ PD_22_ Pdata_53_ PD_19_ Pdata_56_ n719 +00---- 0 +11---- 0 +--01-- 0 +--10-- 0 +----00 0 +----11 0 +.names n710 n704 n721 n723 n711 n722 n720 +01---1 0 +0--11- 0 +111--- 0 +.names n703 PD_1_ Pdata_51_ n702 n721 +1010 1 +1100 1 +.names PD_1_ Pdata_51_ PD_16_ Pdata_54_ PD_4_ Pdata_55_ n722 +01---- 0 +10---- 0 +--01-- 0 +--10-- 0 +----00 0 +----11 0 +.names PD_4_ PD_1_ Pdata_51_ Pdata_55_ PD_16_ Pdata_54_ n723 +0000-- 0 +0011-- 0 +0101-- 0 +0110-- 0 +1001-- 0 +1010-- 0 +1100-- 0 +1111-- 0 +----00 0 +----11 0 +.names n725 n709 n719 n724 +10- 1 +1-0 1 +.names n710 n714 n716 n704 n722 n707 n725 +01---1 0 +11--1- 0 +1-11-- 0 +.names n728 n727 n729 n716 n719 n726 +0000- 1 +000-0 1 +.names n714 n710 n722 n715 n703 n727 +101-- 1 +11-10 1 +.names n719 n708 n728 +11 1 +.names n706 n710 n709 PD_19_ Pdata_56_ n729 +11101 1 +11110 1 +.names n710 n731 n718 n704 n702 n730 +00--- 0 +0-110 0 +.names n715 n732 n717 n714 n703 n731 +00-0- 1 +0-00- 1 +10-1- 1 +-101- 1 +--0-0 1 +.names Pdata_51_ PD_1_ PD_4_ Pdata_55_ n732 +0000 1 +0011 1 +1100 1 +1111 1 +.names n544 Pdata_27_ n758 n751 n734 Pinreg_30_ Pdata_new_59_ +000--- 1 +00-0-- 1 +00--0- 1 +01111- 1 +1----1 1 +.names n1239 n1241 n749 n734 +110 1 +.names PC_2_ Pdata_35_ PC_27_ Pdata_36_ n735 +0000 1 +0011 1 +1100 1 +1111 1 +.names Pdata_37_ PC_14_ PC_9_ Pdata_40_ n736 +0000 1 +0011 1 +1100 1 +1111 1 +.names PC_9_ PC_14_ Pdata_37_ Pdata_40_ n737 +0011 1 +0101 1 +1010 1 +1100 1 +.names PC_5_ Pdata_38_ PC_20_ Pdata_39_ n738 +0000 1 +0011 1 +1100 1 +1111 1 +.names PC_20_ PC_5_ Pdata_38_ Pdata_39_ n739 +0001 1 +0111 1 +1000 1 +1110 1 +.names PC_2_ Pdata_35_ PC_27_ Pdata_36_ n740 +0100 1 +0111 1 +1000 1 +1011 1 +.names PC_20_ PC_5_ Pdata_38_ Pdata_39_ n741 +0011 1 +0101 1 +1010 1 +1100 1 +.names PC_27_ PC_2_ Pdata_35_ Pdata_36_ n742 +0011 1 +0101 1 +1010 1 +1100 1 +.names PC_14_ Pdata_37_ PC_9_ Pdata_40_ n743 +0100 1 +0111 1 +1000 1 +1011 1 +.names PC_14_ Pdata_37_ n744 +01 1 +10 1 +.names PC_5_ Pdata_38_ PC_9_ Pdata_40_ PC_20_ Pdata_39_ n745 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names PC_27_ Pdata_36_ n746 +00 1 +11 1 +.names PC_2_ Pdata_35_ n747 +01 1 +10 1 +.names PC_5_ Pdata_38_ PC_20_ Pdata_39_ n748 +0100 1 +0111 1 +1000 1 +1011 1 +.names n738 n750 n746 n747 n744 n749 +11110 1 +.names PC_9_ Pdata_40_ n750 +01 1 +10 1 +.names n754 n752 n751 +11 1 +.names n753 n739 n736 n740 n752 +0--- 0 +-111 0 +.names n737 n741 n735 n736 n742 n748 n753 +111--- 0 +1---11 0 +-111-- 0 +.names n756 n755 n735 n744 n757 n754 +100-- 1 +10-1- 1 +10--0 1 +.names n748 n742 n750 n744 n755 +1110 1 +.names n736 n746 n747 n739 n748 n756 +1001- 0 +111-1 0 +.names PC_5_ Pdata_38_ PC_9_ Pdata_40_ PC_20_ Pdata_39_ n757 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names n759 n764 n763 n737 n740 n748 n758 +1000-- 1 +100-0- 1 +100--0 1 +.names n744 n747 n746 n760 n762 n759 +0100- 0 +1000- 0 +----1 0 +.names n761 n750 n741 n743 n760 +10-- 0 +--10 0 +.names PC_20_ Pdata_39_ n761 +00 1 +11 1 +.names n743 n738 n747 n740 n739 n762 +110-- 1 +1--11 1 +.names n735 PC_14_ Pdata_37_ n750 n741 n748 n763 +1001-1 1 +10101- 1 +11001- 1 +1111-1 1 +.names n750 n747 n746 n739 n738 n764 +100-1 1 +1101- 1 +.names n544 Pdata_26_ n1291 Pinreg_38_ Pdata_new_58_ +000- 1 +011- 1 +1--1 1 +.names n777 n774 n767 n772 n768 n766 +001-- 1 +10-0- 1 +10--0 1 +.names n769 n771 PD_13_ Pdata_60_ n768 n770 n767 +100010 0 +101110 0 +110100 0 +111000 0 +.names PD_17_ Pdata_59_ n768 +00 1 +11 1 +.names PD_7_ Pdata_62_ n769 +00 1 +11 1 +.names PD_21_ Pdata_61_ n770 +01 1 +10 1 +.names PD_0_ Pdata_63_ n771 +00 1 +11 1 +.names n769 n773 n770 n771 n772 +1110 1 +.names PD_13_ Pdata_60_ n773 +00 1 +11 1 +.names n776 n775 n773 n774 +110 1 +.names PD_17_ Pdata_59_ PD_7_ Pdata_62_ n775 +0100 1 +0111 1 +1000 1 +1011 1 +.names PD_3_ Pdata_32_ PD_21_ Pdata_61_ PD_0_ Pdata_63_ n776 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names PD_3_ Pdata_32_ n777 +00 1 +11 1 +.names PD_13_ Pdata_60_ PD_21_ Pdata_61_ PD_0_ Pdata_63_ n778 +01---- 0 +10---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PD_21_ PD_13_ Pdata_60_ Pdata_61_ n779 +0011 1 +0101 1 +1010 1 +1100 1 +.names Pdata_59_ PD_17_ Pdata_61_ PD_21_ PD_7_ Pdata_62_ n780 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names n787 n789 n788 n786 n784 n782 n781 +100000 1 +.names n780 n783 n777 n782 +110 1 +.names PD_0_ PD_13_ Pdata_60_ Pdata_63_ n783 +0001 1 +0111 1 +1000 1 +1110 1 +.names n785 n778 n768 n784 +111 1 +.names PD_3_ PD_7_ Pdata_32_ Pdata_62_ n785 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names n777 n771 n773 n770 n769 n768 n786 +100000 1 +.names n773 n771 n770 n768 n769 n777 n787 +100000 0 +111100 0 +.names n779 n768 n777 n771 n769 n788 +11100 1 +.names n778 n775 n777 n789 +111 1 +.names n773 n771 n770 PD_7_ Pdata_62_ n777 n790 +110011 0 +110101 0 +111000 0 +111110 0 +.names n544 Pdata_25_ n792 Pinreg_46_ Pdata_new_57_ +000- 1 +011- 1 +1--1 1 +.names n808 n793 n822 n818 n825 n823 n792 +111100 1 +.names n806 n799 n794 n793 +110 1 +.names n798 n797 n796 n795 n794 +1111 1 +.names Pdata_45_ PC_26_ PC_19_ Pdata_46_ n795 +0000 1 +0011 1 +1100 1 +1111 1 +.names PC_6_ Pdata_44_ n796 +01 1 +10 1 +.names PC_15_ Pdata_43_ n797 +01 1 +10 1 +.names Pdata_48_ PC_1_ PC_12_ Pdata_47_ n798 +0000 1 +0011 1 +1100 1 +1111 1 +.names n804 n800 n801 n802 n805 n803 n799 +10---1 0 +11--1- 0 +--11-- 0 +.names PC_1_ Pdata_48_ n800 +01 1 +10 1 +.names Pdata_43_ PC_15_ Pdata_48_ PC_1_ PC_12_ Pdata_47_ n801 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names PC_6_ Pdata_44_ PC_26_ Pdata_45_ PC_19_ Pdata_46_ n802 +01---- 0 +10---- 0 +--01-- 0 +--10-- 0 +----01 0 +----10 0 +.names PC_6_ Pdata_44_ Pdata_45_ PC_26_ PC_19_ Pdata_46_ n803 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names PC_12_ PC_15_ Pdata_43_ Pdata_47_ n804 +0001 1 +0111 1 +1000 1 +1110 1 +.names PC_6_ Pdata_44_ Pdata_45_ PC_26_ PC_19_ Pdata_46_ n805 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names PC_12_ Pdata_47_ n800 n797 n807 n802 n806 +000--- 1 +011--- 1 +101--- 1 +110--- 1 +---0-0 1 +---10- 1 +.names PC_6_ Pdata_44_ Pdata_45_ PC_26_ PC_19_ Pdata_46_ n807 +01---- 0 +10---- 0 +--00-- 0 +--11-- 0 +----00 0 +----11 0 +.names n813 n809 n796 n801 n817 n808 +100-- 1 +10-0- 1 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+01---- 1 +100--- 1 +-1---1 1 +--1--1 1 +---01- 1 +---10- 1 +.names n810 n826 n800 n796 n804 n825 +10--- 1 +1-111 1 +.names n796 n811 n798 n797 n801 n826 +01--1 0 +1010- 0 +1111- 0 +.names n544 n1296 Pinreg_54_ Pdata_new_56_ +01- 1 +1-1 1 +.names PD_8_ Pdata_50_ PD_18_ Pdata_51_ n828 +0100 1 +0111 1 +1000 1 +1011 1 +.names n831 n830 n829 +10 1 +.names n597 n590 PD_18_ Pdata_51_ n589 n592 n830 +100111 1 +101011 1 +110100 1 +111000 1 +.names n595 n828 n606 n602 n592 n831 +1011- 0 +110-0 0 +.names n544 n1225 Pdata_23_ Pdata_in_4_ Pdata_new_55_ +000- 1 +011- 1 +1--1 1 +.names n544 n1248 Pinreg_4_ Pdata_new_54_ +01- 1 +1-1 1 +.names n687 n838 n836 n672 n688 n835 n834 +0001-- 1 +000-10 1 +.names n671 n670 n676 n675 n673 n835 +11111 1 +.names n837 n671 n670 n675 n836 +1000 1 +.names Pdata_33_ PC_10_ PC_4_ Pdata_36_ PC_13_ Pdata_63_ n837 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names n683 n671 n670 n673 n672 n838 +10000 1 +.names n685 n670 n671 n839 +110 1 +.names n675 n673 n671 n672 n670 n840 +110-1 1 +1110- 1 +.names n544 Pdata_21_ n1298 Pinreg_12_ Pdata_new_53_ +000- 1 +011- 1 +1--1 1 +.names n844 n510 n513 n526 n843 n842 +10--0 1 +11-0- 1 +1-1-- 1 +.names n517 n521 n514 n843 +100 1 +.names n523 n531 n509 n524 n515 n844 +111-- 0 +1--11 0 +.names n544 Pdata_20_ n856 n851 n846 Pinreg_20_ Pdata_new_52_ +000--- 1 +00-0-- 1 +00--0- 1 +01111- 1 +1----1 1 +.names n849 n847 n846 +11 1 +.names n773 n771 n848 n776 n768 n769 n847 +001--- 0 +1--110 0 +.names n780 n777 n848 +10 1 +.names n777 n783 n770 n850 n775 n849 +0001- 0 +110-1 0 +.names n768 n771 n769 n777 n850 +1000 1 +.names n781 n855 n766 n852 n854 n777 n851 +11111- 1 +1111-1 1 +.names n853 n770 n768 n783 n785 n852 +001-- 1 +010-- 1 +0--0- 1 +---11 1 +.names n775 n773 n770 n777 n853 +1111 1 +.names PD_7_ Pdata_62_ n770 n768 n773 n771 n854 +00100- 0 +010001 0 +011101 0 +100001 0 +101101 0 +11100- 0 +.names n769 n768 n773 n770 n771 n776 n855 +10010- 0 +11000- 0 +110--1 0 +.names n778 n777 n857 n768 n856 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+000001 0 +00011- 0 +01010- 0 +0110-0 0 +011-10 0 +10010- 0 +1010-0 0 +101-10 0 +110001 0 +11011- 0 +.names n544 Pdata_13_ n1269 Pinreg_10_ Pdata_new_45_ +000- 1 +011- 1 +1--1 1 +.names n831 n830 n586 n592 n589 n886 +101-- 1 +10-00 1 +.names n544 Pdata_12_ n890 n888 n734 Pinreg_18_ Pdata_new_44_ +000--- 1 +00-0-- 1 +00--0- 1 +01111- 1 +1----1 1 +.names n1260 n889 n744 n888 +11- 1 +1-1 1 +.names n746 n750 n738 n747 n741 n889 +00010 0 +011-- 0 +01--1 0 +0-10- 0 +11010 0 +.names n752 n891 n893 n747 n744 n890 +111-- 1 +11-1- 1 +11--0 1 +.names n892 n736 n735 n748 n891 +0--- 0 +-111 0 +.names n742 n757 n738 n743 n735 n892 +11--- 0 +--110 0 +.names n750 n746 n748 n739 n741 n893 +00--1 0 +10-1- 0 +1-1-- 0 +.names n544 Pdata_11_ n895 Pinreg_26_ Pdata_new_43_ +000- 1 +011- 1 +1--1 1 +.names n506 n898 n842 n897 n896 n901 n895 +111110 1 +.names n536 n538 n537 n522 n518 n896 +0000- 1 +000-0 1 +.names n541 n542 n540 n508 n897 +001- 1 +00-0 1 +.names n900 n899 n512 n529 n528 n898 +100-0 1 +10-0- 1 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0 +100001 0 +100111 0 +111001 0 +111111 0 +.names n676 n671 n670 n673 n672 n675 n912 +00110- 0 +01100- 0 +100101 0 +101001 0 +110001 0 +.names n544 n1289 Pdata_7_ Pdata_in_0_ Pdata_new_39_ +000- 1 +011- 1 +1--1 1 +.names n544 Pdata_6_ n1306 n915 Pinreg_0_ Pdata_new_38_ +000-- 1 +00-0- 1 +0111- 1 +1---1 1 +.names n842 n896 n915 +11 1 +.names n513 n514 n508 n510 n517 n521 n916 +1010-- 1 +10--10 1 +.names n531 PD_27_ Pdata_58_ n513 n514 n529 n917 +100000 1 +100110 1 +101100 1 +110100 1 +111000 1 +111110 1 +.names n544 Pdata_5_ n1277 Pinreg_8_ Pdata_new_37_ +000- 1 +011- 1 +1--1 1 +.names n559 n567 n920 n921 n563 n570 n919 +000--1 0 +111--- 0 +1---1- 0 +---1-- 0 +.names n549 n558 n920 +00 1 +11 1 +.names n566 n553 n552 n549 n921 +1100 1 +1111 1 +.names n544 Pdata_4_ n929 n924 n923 Pinreg_16_ Pdata_new_36_ +000--- 1 +00-0-- 1 +00--0- 1 +01111- 1 +1----1 1 +.names n1293 n766 n923 +11 1 +.names n925 n926 n777 n768 n928 n790 n924 +1010-- 1 +101--1 1 +10-01- 1 +10--11 1 +.names n786 n784 n782 n925 +000 1 +.names n777 n927 n780 n771 n773 n926 +11--- 1 +1-100 1 +.names n769 n768 n773 n770 n927 +1100 1 +.names n769 n773 n768 n771 n770 n928 +01100 0 +10000 0 +.names n930 n849 n847 n929 +111 1 +.names n848 n772 n931 n768 n853 n773 n930 +001-0- 1 +01-1-- 1 +101--0 1 +.names n771 n768 n770 n769 n773 n931 +10000 0 +11010 0 +11100 0 +.names n544 n1279 Pinreg_24_ Pdata_new_35_ +01- 1 +1-1 1 +.names PD_19_ Pdata_56_ n710 n703 n732 n715 n933 +000-1- 0 +001100 0 +011000 0 +01111- 0 +01-1-1 0 +101000 0 +10111- 0 +10-1-1 0 +110-1- 0 +111100 0 +--001- 0 +.names n717 n732 n715 n702 n710 n934 +11--- 1 +1-1-- 1 +1--00 1 +.names n544 Pdata_2_ n936 Pinreg_32_ Pdata_new_34_ +000- 1 +011- 1 +1--1 1 +.names n585 n937 n829 n603 n939 n936 +11110 1 +.names n589 n938 n594 n592 n607 n602 n937 +0---11 0 +1-11-- 0 +-1---- 0 +.names n590 n601 PD_18_ Pdata_51_ n606 n938 +11010 1 +11100 1 +.names n592 n607 n590 n589 n940 n941 n939 +0101-- 1 +0110-- 1 +0----0 1 +1---1- 1 +.names n588 PD_18_ Pdata_51_ n589 n587 n590 n940 +100010 1 +100100 1 +101000 1 +110000 1 +111010 1 +111100 1 +.names PD_23_ Pdata_48_ n588 n589 n594 n602 n941 +00001- 0 +0001-1 0 +01101- 0 +10101- 0 +11001- 0 +1101-1 0 +.names n544 Pdata_1_ n1281 n870 Pinreg_40_ Pdata_new_33_ +000-- 1 +00-0- 1 +0111- 1 +1---1 1 +.names n737 n736 n748 n738 n741 n943 +00--1 0 +1--1- 0 +-11-- 0 +.names n746 n744 n738 n757 n745 n944 +111-- 1 +11-1- 1 +11--1 1 +.names n743 n742 n735 n761 n738 n945 +111-- 0 +11--0 0 +1-11- 0 +.names n544 Pdata_0_ n1284 Pinreg_48_ Pdata_new_32_ +000- 1 +011- 1 +1--1 1 +.names n797 n796 n810 n800 n812 n947 +01--- 1 +1-1-- 1 +-0-00 1 +--010 1 +.names n817 PC_12_ Pdata_47_ n797 n800 n796 n948 +10010- 1 +1001-1 1 +10100- 1 +11000- 1 +11110- 1 +1111-1 1 +.names n544 Pdata_in_7_ Pdata_63_ Pdata_new_31_ +0-1 1 +11- 1 +.names n544 Pinreg_7_ Pdata_62_ Pdata_new_30_ +0-1 1 +11- 1 +.names n544 Pinreg_15_ Pdata_61_ Pdata_new_29_ +0-1 1 +11- 1 +.names n544 Pinreg_23_ Pdata_60_ Pdata_new_28_ +0-1 1 +11- 1 +.names n544 Pinreg_31_ Pdata_59_ Pdata_new_27_ +0-1 1 +11- 1 +.names n544 Pinreg_39_ Pdata_58_ Pdata_new_26_ +0-1 1 +11- 1 +.names n544 Pinreg_47_ Pdata_57_ Pdata_new_25_ +0-1 1 +11- 1 +.names n544 Pinreg_55_ Pdata_56_ Pdata_new_24_ +0-1 1 +11- 1 +.names n544 Pdata_in_5_ Pdata_55_ Pdata_new_23_ +0-1 1 +11- 1 +.names n544 Pinreg_5_ Pdata_54_ Pdata_new_22_ +0-1 1 +11- 1 +.names n544 Pinreg_13_ Pdata_53_ Pdata_new_21_ +0-1 1 +11- 1 +.names n544 Pinreg_21_ Pdata_52_ Pdata_new_20_ +0-1 1 +11- 1 +.names n544 Pinreg_29_ Pdata_51_ Pdata_new_19_ +0-1 1 +11- 1 +.names n544 Pinreg_37_ Pdata_50_ Pdata_new_18_ +0-1 1 +11- 1 +.names n544 Pinreg_45_ Pdata_49_ Pdata_new_17_ +0-1 1 +11- 1 +.names n544 Pinreg_53_ Pdata_48_ Pdata_new_16_ +0-1 1 +11- 1 +.names n544 Pdata_in_3_ Pdata_47_ Pdata_new_15_ +0-1 1 +11- 1 +.names n544 Pinreg_3_ Pdata_46_ Pdata_new_14_ +0-1 1 +11- 1 +.names n544 Pinreg_11_ Pdata_45_ Pdata_new_13_ +0-1 1 +11- 1 +.names n544 Pinreg_19_ Pdata_44_ Pdata_new_12_ +0-1 1 +11- 1 +.names n544 Pinreg_27_ Pdata_43_ Pdata_new_11_ +0-1 1 +11- 1 +.names n544 Pinreg_35_ Pdata_42_ Pdata_new_10_ +0-1 1 +11- 1 +.names n544 Pinreg_43_ Pdata_41_ Pdata_new_9_ +0-1 1 +11- 1 +.names n544 Pinreg_51_ Pdata_40_ Pdata_new_8_ +0-1 1 +11- 1 +.names n544 Pdata_in_1_ Pdata_39_ Pdata_new_7_ +0-1 1 +11- 1 +.names n544 Pinreg_1_ Pdata_38_ Pdata_new_6_ +0-1 1 +11- 1 +.names n544 Pinreg_9_ Pdata_37_ Pdata_new_5_ +0-1 1 +11- 1 +.names n544 Pinreg_17_ Pdata_36_ Pdata_new_4_ +0-1 1 +11- 1 +.names n544 Pinreg_25_ Pdata_35_ Pdata_new_3_ +0-1 1 +11- 1 +.names n544 Pinreg_33_ Pdata_34_ Pdata_new_2_ +0-1 1 +11- 1 +.names n544 Pinreg_41_ Pdata_33_ Pdata_new_1_ +0-1 1 +11- 1 +.names n544 Pinreg_49_ Pdata_32_ Pdata_new_0_ +0-1 1 +11- 1 +.names Preset_0_ Pcount_0_ Pcount_new_0_ +00 1 +.names Pcount_3_ Preset_0_ Pcount_1_ Pcount_2_ Pcount_0_ Pcount_new_3_ +00111 1 +100-- 1 +10-0- 1 +10--0 1 +.names Pcount_2_ Preset_0_ Pcount_1_ Pcount_0_ Pcount_new_2_ +0011 1 +100- 1 +10-0 1 +.names Pcount_1_ Pcount_0_ Preset_0_ Pcount_new_1_ +010 1 +100 1 +.names n990 n986 n995 PD_25_ PD_new_27_ +110- 0 +11-0 0 +.names PD_27_ n987 n988 Pdata_in_3_ Pinreg_54_ n989 n986 +11---- 0 +--11-- 0 +----11 0 +.names n544 Pencrypt_0_ Pencrypt_mode_0_ Preset_0_ Pload_key_0_ n987 +10100 1 +11000 1 +.names n544 Pload_key_0_ Preset_0_ Pencrypt_0_ n988 +1100 1 +.names n544 Pload_key_0_ Pencrypt_0_ Preset_0_ n989 +1110 1 +.names PD_26_ n991 PD_1_ n993 n994 PD_0_ n990 +11---- 0 +--11-- 0 +----11 0 +.names n992 Preset_0_ Pencrypt_mode_0_ n544 Pload_key_0_ Pencrypt_0_ n991 +1000-- 1 +100-00 1 +.names Pcount_1_ Pcount_2_ Pcount_3_ Pcount_0_ n992 +0000 1 +111- 1 +11-1 1 +.names Pencrypt_mode_0_ Preset_0_ n992 n993 +100 1 +.names Pencrypt_mode_0_ n992 Preset_0_ n544 Pencrypt_0_ Pload_key_0_ n994 +1100-- 1 +110-10 1 +.names Preset_0_ Pencrypt_mode_0_ n992 n995 +000 1 +.names n998 n997 n994 PD_27_ PD_new_26_ +110- 0 +11-0 0 +.names PD_26_ n987 n988 Pinreg_3_ n989 Pdata_in_3_ n997 +11---- 0 +--11-- 0 +----11 0 +.names PD_24_ n995 n991 PD_25_ PD_0_ n993 n998 +11---- 0 +--11-- 0 +----11 0 +.names n1000 n1001 PD_25_ n987 n994 PD_26_ PD_new_25_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_11_ n988 Pinreg_3_ n989 n1000 +11-- 0 +--11 0 +.names PD_23_ n995 n991 PD_24_ PD_27_ n993 n1001 +11---- 0 +--11-- 0 +----11 0 +.names n1003 n1004 PD_24_ n987 PD_23_ n991 PD_new_24_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_19_ n988 Pinreg_11_ n989 n1003 +11-- 0 +--11 0 +.names PD_22_ n995 n993 PD_26_ n994 PD_25_ n1004 +11---- 0 +--11-- 0 +----11 0 +.names n1007 n1006 n991 PD_22_ PD_new_23_ +110- 0 +11-0 0 +.names PD_23_ n987 n988 Pdata_in_4_ Pinreg_19_ n989 n1006 +11---- 0 +--11-- 0 +----11 0 +.names PD_21_ n995 n993 PD_25_ n994 PD_24_ n1007 +11---- 0 +--11-- 0 +----11 0 +.names n1010 n1009 n994 PD_23_ PD_new_22_ +110- 0 +11-0 0 +.names PD_22_ n987 n988 Pinreg_4_ n989 Pdata_in_4_ n1009 +11---- 0 +--11-- 0 +----11 0 +.names PD_20_ n995 n991 PD_21_ PD_24_ n993 n1010 +11---- 0 +--11-- 0 +----11 0 +.names n1013 n1012 n995 PD_19_ PD_new_21_ +110- 0 +11-0 0 +.names PD_21_ n987 n988 Pinreg_12_ n989 Pinreg_4_ n1012 +11---- 0 +--11-- 0 +----11 0 +.names PD_20_ n991 n993 PD_23_ n994 PD_22_ n1013 +11---- 0 +--11-- 0 +----11 0 +.names n1016 n1015 n991 PD_19_ PD_new_20_ +110- 0 +11-0 0 +.names PD_20_ n987 n988 Pinreg_20_ n989 Pinreg_12_ n1015 +11---- 0 +--11-- 0 +----11 0 +.names PD_18_ n995 n993 PD_22_ n994 PD_21_ n1016 +11---- 0 +--11-- 0 +----11 0 +.names n1019 n1018 n994 PD_20_ PD_new_19_ +110- 0 +11-0 0 +.names PD_19_ n987 n988 Pinreg_28_ n989 Pinreg_20_ n1018 +11---- 0 +--11-- 0 +----11 0 +.names PD_17_ n995 n991 PD_18_ PD_21_ n993 n1019 +11---- 0 +--11-- 0 +----11 0 +.names n1022 n1021 n995 PD_16_ PD_new_18_ +110- 0 +11-0 0 +.names PD_18_ n987 n988 Pinreg_36_ n989 Pinreg_28_ n1021 +11---- 0 +--11-- 0 +----11 0 +.names PD_17_ n991 n993 PD_20_ n994 PD_19_ n1022 +11---- 0 +--11-- 0 +----11 0 +.names n1025 n1024 n993 PD_19_ PD_new_17_ +110- 0 +11-0 0 +.names PD_17_ n987 n988 Pinreg_44_ n989 Pinreg_36_ n1024 +11---- 0 +--11-- 0 +----11 0 +.names PD_15_ n995 n991 PD_16_ PD_18_ n994 n1025 +11---- 0 +--11-- 0 +----11 0 +.names n1028 n1027 n993 PD_18_ PD_new_16_ +110- 0 +11-0 0 +.names PD_16_ n987 n988 Pinreg_52_ Pinreg_44_ n989 n1027 +11---- 0 +--11-- 0 +----11 0 +.names PD_14_ n995 n991 PD_15_ PD_17_ n994 n1028 +11---- 0 +--11-- 0 +----11 0 +.names n1030 n1031 PD_13_ n995 n987 PD_15_ PD_new_15_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pdata_in_5_ n988 n989 Pinreg_52_ n1030 +11-- 0 +--11 0 +.names PD_14_ n991 n993 PD_17_ n994 PD_16_ n1031 +11---- 0 +--11-- 0 +----11 0 +.names n1034 n1033 n993 PD_16_ PD_new_14_ +110- 0 +11-0 0 +.names PD_14_ n987 n988 Pinreg_5_ n989 Pdata_in_5_ n1033 +11---- 0 +--11-- 0 +----11 0 +.names PD_12_ n995 n991 PD_13_ PD_15_ n994 n1034 +11---- 0 +--11-- 0 +----11 0 +.names n1037 n1036 n993 PD_15_ PD_new_13_ +110- 0 +11-0 0 +.names PD_13_ n987 n988 Pinreg_13_ n989 Pinreg_5_ n1036 +11---- 0 +--11-- 0 +----11 0 +.names PD_11_ n995 n991 PD_12_ PD_14_ n994 n1037 +11---- 0 +--11-- 0 +----11 0 +.names n1040 n1039 n993 PD_14_ PD_new_12_ +110- 0 +11-0 0 +.names PD_12_ n987 n988 Pinreg_21_ n989 Pinreg_13_ n1039 +11---- 0 +--11-- 0 +----11 0 +.names PD_10_ n995 n991 PD_11_ PD_13_ n994 n1040 +11---- 0 +--11-- 0 +----11 0 +.names n1043 n1042 n993 PD_13_ PD_new_11_ +110- 0 +11-0 0 +.names PD_11_ n987 n988 Pinreg_29_ n989 Pinreg_21_ n1042 +11---- 0 +--11-- 0 +----11 0 +.names PD_9_ n995 n991 PD_10_ PD_12_ n994 n1043 +11---- 0 +--11-- 0 +----11 0 +.names n1046 n1045 n994 PD_11_ PD_new_10_ +110- 0 +11-0 0 +.names PD_10_ n987 n988 Pinreg_37_ n989 Pinreg_29_ n1045 +11---- 0 +--11-- 0 +----11 0 +.names PD_8_ n995 n991 PD_9_ PD_12_ n993 n1046 +11---- 0 +--11-- 0 +----11 0 +.names n1049 n1048 n995 PD_7_ PD_new_9_ +110- 0 +11-0 0 +.names PD_9_ n987 n988 Pinreg_45_ n989 Pinreg_37_ n1048 +11---- 0 +--11-- 0 +----11 0 +.names PD_8_ n991 n993 PD_11_ n994 PD_10_ n1049 +11---- 0 +--11-- 0 +----11 0 +.names n1052 n1051 n994 PD_9_ PD_new_8_ +110- 0 +11-0 0 +.names PD_8_ n987 n988 Pinreg_53_ Pinreg_45_ n989 n1051 +11---- 0 +--11-- 0 +----11 0 +.names PD_6_ n995 n991 PD_7_ PD_10_ n993 n1052 +11---- 0 +--11-- 0 +----11 0 +.names n1055 n1054 n994 PD_8_ PD_new_7_ +110- 0 +11-0 0 +.names PD_7_ n987 n988 Pdata_in_6_ Pinreg_53_ n989 n1054 +11---- 0 +--11-- 0 +----11 0 +.names PD_5_ n995 n991 PD_6_ PD_9_ n993 n1055 +11---- 0 +--11-- 0 +----11 0 +.names n1057 n1058 PD_6_ n987 n994 PD_7_ PD_new_6_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_6_ n988 Pdata_in_6_ n989 n1057 +11-- 0 +--11 0 +.names PD_4_ n995 n991 PD_5_ PD_8_ n993 n1058 +11---- 0 +--11-- 0 +----11 0 +.names n1061 n1060 n993 PD_7_ PD_new_5_ +110- 0 +11-0 0 +.names PD_5_ n987 n988 Pinreg_14_ n989 Pinreg_6_ n1060 +11---- 0 +--11-- 0 +----11 0 +.names PD_3_ n995 n991 PD_4_ PD_6_ n994 n1061 +11---- 0 +--11-- 0 +----11 0 +.names n1064 n1063 n993 PD_6_ PD_new_4_ +110- 0 +11-0 0 +.names PD_4_ n987 n988 Pinreg_22_ n989 Pinreg_14_ n1063 +11---- 0 +--11-- 0 +----11 0 +.names PD_2_ n995 n991 PD_3_ PD_5_ n994 n1064 +11---- 0 +--11-- 0 +----11 0 +.names n1067 n1066 n995 PD_1_ PD_new_3_ +110- 0 +11-0 0 +.names PD_3_ n987 n988 Pinreg_30_ n989 Pinreg_22_ n1066 +11---- 0 +--11-- 0 +----11 0 +.names PD_2_ n991 n993 PD_5_ n994 PD_4_ n1067 +11---- 0 +--11-- 0 +----11 0 +.names n1070 n1069 n991 PD_1_ PD_new_2_ +110- 0 +11-0 0 +.names PD_2_ n987 n988 Pinreg_38_ n989 Pinreg_30_ n1069 +11---- 0 +--11-- 0 +----11 0 +.names PD_0_ n995 PD_4_ n993 PD_3_ n994 n1070 +11---- 0 +--11-- 0 +----11 0 +.names n1072 n1073 PD_27_ n995 PD_1_ n987 PD_new_1_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_46_ n988 Pinreg_38_ n989 n1072 +11-- 0 +--11 0 +.names PD_0_ n991 PD_3_ n993 PD_2_ n994 n1073 +11---- 0 +--11-- 0 +----11 0 +.names n1076 n1075 n993 PD_2_ PD_new_0_ +110- 0 +11-0 0 +.names PD_0_ n987 n988 Pinreg_54_ Pinreg_46_ n989 n1075 +11---- 0 +--11-- 0 +----11 0 +.names PD_26_ n995 n991 PD_27_ PD_1_ n994 n1076 +11---- 0 +--11-- 0 +----11 0 +.names n1079 n1078 n995 PC_25_ PC_new_27_ +110- 0 +11-0 0 +.names PC_27_ n987 n988 Pinreg_27_ Pinreg_48_ n989 n1078 +11---- 0 +--11-- 0 +----11 0 +.names PC_26_ n991 PC_1_ n993 n994 PC_0_ n1079 +11---- 0 +--11-- 0 +----11 0 +.names n1082 n1081 n995 PC_24_ PC_new_26_ +110- 0 +11-0 0 +.names PC_26_ n987 n988 Pinreg_35_ n989 Pinreg_27_ n1081 +11---- 0 +--11-- 0 +----11 0 +.names PC_25_ n991 n993 PC_0_ PC_27_ n994 n1082 +11---- 0 +--11-- 0 +----11 0 +.names n1085 n1084 n993 PC_27_ PC_new_25_ +110- 0 +11-0 0 +.names PC_25_ n987 n988 Pinreg_43_ n989 Pinreg_35_ n1084 +11---- 0 +--11-- 0 +----11 0 +.names PC_23_ n995 n991 PC_24_ PC_26_ n994 n1085 +11---- 0 +--11-- 0 +----11 0 +.names n1088 n1087 n993 PC_26_ PC_new_24_ +110- 0 +11-0 0 +.names PC_24_ n987 n988 Pinreg_51_ Pinreg_43_ n989 n1087 +11---- 0 +--11-- 0 +----11 0 +.names PC_22_ n995 n991 PC_23_ PC_25_ n994 n1088 +11---- 0 +--11-- 0 +----11 0 +.names n1091 n1090 n991 PC_22_ PC_new_23_ +110- 0 +11-0 0 +.names PC_23_ n987 n988 Pdata_in_2_ Pinreg_51_ n989 n1090 +11---- 0 +--11-- 0 +----11 0 +.names PC_21_ n995 n993 PC_25_ n994 PC_24_ n1091 +11---- 0 +--11-- 0 +----11 0 +.names n1094 n1093 n994 PC_23_ PC_new_22_ +110- 0 +11-0 0 +.names PC_22_ n987 n988 Pinreg_2_ n989 Pdata_in_2_ n1093 +11---- 0 +--11-- 0 +----11 0 +.names PC_20_ n995 n991 PC_21_ PC_24_ n993 n1094 +11---- 0 +--11-- 0 +----11 0 +.names n1096 n1097 PC_21_ n987 n994 PC_22_ PC_new_21_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_10_ n988 Pinreg_2_ n989 n1096 +11-- 0 +--11 0 +.names PC_19_ n995 n991 PC_20_ PC_23_ n993 n1097 +11---- 0 +--11-- 0 +----11 0 +.names n1100 n1099 n995 PC_18_ PC_new_20_ +110- 0 +11-0 0 +.names PC_20_ n987 n988 Pinreg_18_ n989 Pinreg_10_ n1099 +11---- 0 +--11-- 0 +----11 0 +.names PC_19_ n991 n993 PC_22_ n994 PC_21_ n1100 +11---- 0 +--11-- 0 +----11 0 +.names n1103 n1102 n994 PC_20_ PC_new_19_ +110- 0 +11-0 0 +.names PC_19_ n987 n988 Pinreg_26_ n989 Pinreg_18_ n1102 +11---- 0 +--11-- 0 +----11 0 +.names PC_17_ n995 n991 PC_18_ PC_21_ n993 n1103 +11---- 0 +--11-- 0 +----11 0 +.names n1106 n1105 n995 PC_16_ PC_new_18_ +110- 0 +11-0 0 +.names PC_18_ n987 n988 Pinreg_34_ n989 Pinreg_26_ n1105 +11---- 0 +--11-- 0 +----11 0 +.names PC_17_ n991 n993 PC_20_ n994 PC_19_ n1106 +11---- 0 +--11-- 0 +----11 0 +.names n1108 n1109 PC_17_ n987 n993 PC_19_ PC_new_17_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_42_ n988 Pinreg_34_ n989 n1108 +11-- 0 +--11 0 +.names PC_15_ n995 n991 PC_16_ PC_18_ n994 n1109 +11---- 0 +--11-- 0 +----11 0 +.names n1112 n1111 n995 PC_14_ PC_new_16_ +110- 0 +11-0 0 +.names PC_16_ n987 n988 Pinreg_50_ Pinreg_42_ n989 n1111 +11---- 0 +--11-- 0 +----11 0 +.names PC_15_ n991 n993 PC_18_ n994 PC_17_ n1112 +11---- 0 +--11-- 0 +----11 0 +.names n1115 n1114 n994 PC_16_ PC_new_15_ +110- 0 +11-0 0 +.names PC_15_ n987 n988 Pdata_in_1_ Pinreg_50_ n989 n1114 +11---- 0 +--11-- 0 +----11 0 +.names PC_13_ n995 n991 PC_14_ PC_17_ n993 n1115 +11---- 0 +--11-- 0 +----11 0 +.names n1118 n1117 n991 PC_13_ PC_new_14_ +110- 0 +11-0 0 +.names PC_14_ n987 n988 Pinreg_1_ n989 Pdata_in_1_ n1117 +11---- 0 +--11-- 0 +----11 0 +.names PC_12_ n995 n993 PC_16_ n994 PC_15_ n1118 +11---- 0 +--11-- 0 +----11 0 +.names n1121 n1120 n993 PC_15_ PC_new_13_ +110- 0 +11-0 0 +.names PC_13_ n987 n988 Pinreg_9_ n989 Pinreg_1_ n1120 +11---- 0 +--11-- 0 +----11 0 +.names PC_11_ n995 n991 PC_12_ PC_14_ n994 n1121 +11---- 0 +--11-- 0 +----11 0 +.names n1124 n1123 n993 PC_14_ PC_new_12_ +110- 0 +11-0 0 +.names PC_12_ n987 n988 Pinreg_17_ n989 Pinreg_9_ n1123 +11---- 0 +--11-- 0 +----11 0 +.names PC_10_ n995 n991 PC_11_ PC_13_ n994 n1124 +11---- 0 +--11-- 0 +----11 0 +.names n1126 n1127 PC_9_ n995 n987 PC_11_ PC_new_11_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_25_ n988 Pinreg_17_ n989 n1126 +11-- 0 +--11 0 +.names PC_10_ n991 n993 PC_13_ n994 PC_12_ n1127 +11---- 0 +--11-- 0 +----11 0 +.names n1130 n1129 n994 PC_11_ PC_new_10_ +110- 0 +11-0 0 +.names PC_10_ n987 n988 Pinreg_33_ n989 Pinreg_25_ n1129 +11---- 0 +--11-- 0 +----11 0 +.names PC_8_ n995 n991 PC_9_ PC_12_ n993 n1130 +11---- 0 +--11-- 0 +----11 0 +.names n1133 n1132 n995 PC_7_ PC_new_9_ +110- 0 +11-0 0 +.names PC_9_ n987 n988 Pinreg_41_ n989 Pinreg_33_ n1132 +11---- 0 +--11-- 0 +----11 0 +.names PC_8_ n991 n993 PC_11_ n994 PC_10_ n1133 +11---- 0 +--11-- 0 +----11 0 +.names n1136 n1135 n993 PC_10_ PC_new_8_ +110- 0 +11-0 0 +.names PC_8_ n987 n988 Pinreg_49_ Pinreg_41_ n989 n1135 +11---- 0 +--11-- 0 +----11 0 +.names PC_6_ n995 n991 PC_7_ PC_9_ n994 n1136 +11---- 0 +--11-- 0 +----11 0 +.names n1139 n1138 n994 PC_8_ PC_new_7_ +110- 0 +11-0 0 +.names PC_7_ n987 n988 Pdata_in_0_ Pinreg_49_ n989 n1138 +11---- 0 +--11-- 0 +----11 0 +.names PC_5_ n995 n991 PC_6_ PC_9_ n993 n1139 +11---- 0 +--11-- 0 +----11 0 +.names n1142 n1141 n994 PC_7_ PC_new_6_ +110- 0 +11-0 0 +.names PC_6_ n987 n988 Pinreg_0_ n989 Pdata_in_0_ n1141 +11---- 0 +--11-- 0 +----11 0 +.names PC_4_ n995 n991 PC_5_ PC_8_ n993 n1142 +11---- 0 +--11-- 0 +----11 0 +.names n1145 n1144 n995 PC_3_ PC_new_5_ +110- 0 +11-0 0 +.names PC_5_ n987 n988 Pinreg_8_ n989 Pinreg_0_ n1144 +11---- 0 +--11-- 0 +----11 0 +.names PC_4_ n991 n993 PC_7_ n994 PC_6_ n1145 +11---- 0 +--11-- 0 +----11 0 +.names n1148 n1147 n994 PC_5_ PC_new_4_ +110- 0 +11-0 0 +.names PC_4_ n987 n988 Pinreg_16_ n989 Pinreg_8_ n1147 +11---- 0 +--11-- 0 +----11 0 +.names PC_2_ n995 n991 PC_3_ PC_6_ n993 n1148 +11---- 0 +--11-- 0 +----11 0 +.names n1151 n1150 n995 PC_1_ PC_new_3_ +110- 0 +11-0 0 +.names PC_3_ n987 n988 Pinreg_24_ n989 Pinreg_16_ n1150 +11---- 0 +--11-- 0 +----11 0 +.names PC_2_ n991 n993 PC_5_ n994 PC_4_ n1151 +11---- 0 +--11-- 0 +----11 0 +.names n1154 n1153 n993 PC_4_ PC_new_2_ +110- 0 +11-0 0 +.names PC_2_ n987 n988 Pinreg_32_ n989 Pinreg_24_ n1153 +11---- 0 +--11-- 0 +----11 0 +.names PC_0_ n995 PC_1_ n991 PC_3_ n994 n1154 +11---- 0 +--11-- 0 +----11 0 +.names n1156 n1157 PC_1_ n987 PC_3_ n993 PC_new_1_ +0----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names Pinreg_40_ n988 Pinreg_32_ n989 n1156 +11-- 0 +--11 0 +.names PC_27_ n995 PC_0_ n991 PC_2_ n994 n1157 +11---- 0 +--11-- 0 +----11 0 +.names n1160 n1159 n993 PC_2_ PC_new_0_ +110- 0 +11-0 0 +.names PC_0_ n987 n988 Pinreg_48_ Pinreg_40_ n989 n1159 +11---- 0 +--11-- 0 +----11 0 +.names PC_26_ n995 n991 PC_27_ PC_1_ n994 n1160 +11---- 0 +--11-- 0 +----11 0 +.names n544 n1296 Poutreg_63_ Pcount_0_ Poutreg_new_63_ +11-- 1 +--10 1 +.names Pdata_56_ n544 Poutreg_62_ Pcount_0_ Poutreg_new_62_ +11-- 1 +--10 1 +.names n544 Pdata_16_ n1263 Poutreg_61_ Pcount_0_ Poutreg_new_61_ +100-- 1 +111-- 1 +---10 1 +.names Pdata_48_ n544 Poutreg_60_ Pcount_0_ Poutreg_new_60_ +11-- 1 +--10 1 +.names n544 n909 Poutreg_59_ Pcount_0_ Poutreg_new_59_ +11-- 1 +--10 1 +.names Pdata_40_ n544 Poutreg_58_ Pcount_0_ Poutreg_new_58_ +11-- 1 +--10 1 +.names n544 Pdata_0_ n1284 Poutreg_57_ Pcount_0_ Poutreg_new_57_ +100-- 1 +111-- 1 +---10 1 +.names Pdata_32_ n544 Poutreg_56_ Pcount_0_ Poutreg_new_56_ +11-- 1 +--10 1 +.names n544 n792 Pdata_25_ Pcount_0_ Poutreg_55_ Poutreg_63_ \ + Poutreg_new_55_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_57_ Poutreg_54_ Poutreg_62_ Poutreg_new_54_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_17_ n872 n870 n1172 Poutreg_new_53_ +100-- 1 +10-0- 1 +1111- 1 +----0 1 +.names Pcount_0_ Poutreg_53_ Poutreg_61_ n544 n1172 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_49_ Poutreg_52_ Poutreg_60_ Poutreg_new_52_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1273 Pdata_9_ Pcount_0_ Poutreg_51_ Poutreg_59_ \ + Poutreg_new_51_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_41_ Poutreg_50_ Poutreg_58_ Poutreg_new_50_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_1_ n1281 n870 n1177 Poutreg_new_49_ +100-- 1 +10-0- 1 +1111- 1 +----0 1 +.names Pcount_0_ Poutreg_49_ Poutreg_57_ n544 n1177 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_33_ Poutreg_48_ Poutreg_56_ Poutreg_new_48_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1291 Pdata_26_ Pcount_0_ Poutreg_47_ Poutreg_55_ \ + Poutreg_new_47_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_58_ Poutreg_46_ Poutreg_54_ Poutreg_new_46_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1256 Pdata_18_ Pcount_0_ Poutreg_45_ Poutreg_53_ \ + Poutreg_new_45_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_50_ Poutreg_44_ Poutreg_52_ Poutreg_new_44_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1303 Pdata_10_ Pcount_0_ Poutreg_43_ Poutreg_51_ \ + Poutreg_new_43_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_42_ Poutreg_42_ Poutreg_50_ Poutreg_new_42_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n936 Pdata_2_ Pcount_0_ Poutreg_41_ Poutreg_49_ Poutreg_new_41_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_34_ Poutreg_40_ Poutreg_48_ Poutreg_new_40_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_27_ n758 n751 n734 n1188 Poutreg_new_39_ +100--- 1 +10-0-- 1 +10--0- 1 +11111- 1 +-----0 1 +.names Pcount_0_ Poutreg_39_ Poutreg_47_ n544 n1188 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_59_ Poutreg_38_ Poutreg_46_ Poutreg_new_38_ +0--1- 1 +10--1 1 +-11-- 1 +.names Pcount_0_ n544 n859 Poutreg_37_ Poutreg_45_ Poutreg_new_37_ +0--1- 1 +10--1 1 +-10-- 1 +.names Pcount_0_ n544 Pdata_51_ Poutreg_36_ Poutreg_44_ Poutreg_new_36_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n895 Pdata_11_ Pcount_0_ Poutreg_35_ Poutreg_43_ \ + Poutreg_new_35_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_43_ Poutreg_34_ Poutreg_42_ Poutreg_new_34_ +0--1- 1 +10--1 1 +-11-- 1 +.names Pcount_0_ n544 n1279 Poutreg_33_ Poutreg_41_ Poutreg_new_33_ +0--1- 1 +10--1 1 +-11-- 1 +.names Pcount_0_ n544 Pdata_35_ Poutreg_32_ Poutreg_40_ Poutreg_new_32_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n699 Pdata_28_ Pcount_0_ Poutreg_31_ Poutreg_39_ \ + Poutreg_new_31_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_60_ Poutreg_30_ Poutreg_38_ Poutreg_new_30_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_20_ n856 n851 n846 n1199 Poutreg_new_29_ +100--- 1 +10-0-- 1 +10--0- 1 +11111- 1 +-----0 1 +.names Pcount_0_ Poutreg_29_ Poutreg_37_ n544 n1199 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_52_ Poutreg_28_ Poutreg_36_ Poutreg_new_28_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_12_ n890 n888 n734 n1202 Poutreg_new_27_ +100--- 1 +10-0-- 1 +10--0- 1 +11111- 1 +-----0 1 +.names Pcount_0_ Poutreg_27_ Poutreg_35_ n544 n1202 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_44_ Poutreg_26_ Poutreg_34_ Poutreg_new_26_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_4_ n929 n924 n923 n1205 Poutreg_new_25_ +100--- 1 +10-0-- 1 +10--0- 1 +11111- 1 +-----0 1 +.names Pcount_0_ Poutreg_25_ Poutreg_33_ n544 n1205 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_36_ Poutreg_24_ Poutreg_32_ Poutreg_new_24_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n692 Pdata_29_ Pcount_0_ Poutreg_23_ Poutreg_31_ \ + Poutreg_new_23_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_61_ Poutreg_22_ Poutreg_30_ Poutreg_new_22_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1298 Pdata_21_ Pcount_0_ Poutreg_21_ Poutreg_29_ \ + Poutreg_new_21_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_53_ Poutreg_20_ Poutreg_28_ Poutreg_new_20_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1269 Pdata_13_ Pcount_0_ Poutreg_19_ Poutreg_27_ \ + Poutreg_new_19_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_45_ Poutreg_18_ Poutreg_26_ Poutreg_new_18_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1277 Pdata_5_ Pcount_0_ Poutreg_17_ Poutreg_25_ \ + Poutreg_new_17_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_37_ Poutreg_16_ Poutreg_24_ Poutreg_new_16_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n668 Pdata_30_ Pcount_0_ Poutreg_15_ Poutreg_23_ \ + Poutreg_new_15_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_62_ Poutreg_14_ Poutreg_22_ Poutreg_new_14_ +0--1- 1 +10--1 1 +-11-- 1 +.names Pcount_0_ n544 n1248 Poutreg_13_ Poutreg_21_ Poutreg_new_13_ +0--1- 1 +10--1 1 +-11-- 1 +.names Pcount_0_ n544 Pdata_54_ Poutreg_12_ Poutreg_20_ Poutreg_new_12_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 n1266 Pdata_14_ Pcount_0_ Poutreg_11_ Poutreg_19_ \ + Poutreg_new_11_ +0--1-1 1 +100--- 1 +111--- 1 +---01- 1 +.names Pcount_0_ n544 Pdata_46_ Poutreg_10_ Poutreg_18_ Poutreg_new_10_ +0--1- 1 +10--1 1 +-11-- 1 +.names n544 Pdata_6_ n1306 n915 n1222 Poutreg_new_9_ +100-- 1 +10-0- 1 +1111- 1 +----0 1 +.names Pcount_0_ Poutreg_9_ Poutreg_17_ n544 n1222 +01-- 0 +1-10 0 +.names Pcount_0_ n544 Pdata_38_ Poutreg_8_ Poutreg_16_ Poutreg_new_8_ +0--1- 1 +10--1 1 +-11-- 1 +.names n550 n563 n570 n555 n562 n561 n1224 +01---- 0 +0-1--- 0 +1---11 0 +-1-1-- 0 +.names n547 n1227 n1286 n556 n1224 n565 n1225 +111110 1 +.names n561 n552 n549 n559 n560 n1226 +011-1 1 +10--- 1 +1-0-- 1 +1--0- 1 +.names n558 n561 n562 n550 n1226 n1227 +0011- 0 +10--1 0 +11--0 0 +1-101 0 +.names n558 n564 n566 n549 PC_3_ Pdata_42_ n1228 +0---00 0 +0---11 0 +1100-- 0 +1111-- 0 +.names n1228 n558 n580 n581 n582 n571 n1229 +01---- 0 +10---1 0 +--1--- 0 +---10- 0 +.names n1227 n1229 n1232 n576 n556 n579 n1230 +111110 1 +.names n560 n558 PC_18_ Pdata_40_ n559 n554 n1231 +1100-- 1 +1111-- 1 +----11 1 +.names n578 Pdata_43_ PC_25_ PC_22_ Pdata_39_ n1231 n1232 +100--- 1 +111--- 1 +1--00- 1 +1--11- 1 +1----0 1 +.names n588 n590 n587 PD_18_ Pdata_51_ n1233 +10101 1 +10110 1 +11001 1 +11010 1 +11100 1 +11111 1 +.names n592 n595 n594 n602 n607 n1234 +011-- 0 +01-1- 0 +100-0 0 +.names n673 n676 n671 n672 n670 n675 n1235 +001100 0 +010010 0 +101000 0 +110000 0 +.names n673 n671 n670 n676 n672 n689 n1236 +01101- 1 +01110- 1 +10000- 1 +110--1 1 +.names n675 n1236 n1237 +11 0 +.names n737 n735 n738 n736 n740 n739 n1238 +111--- 0 +1---11 0 +-111-- 0 +.names n1238 n743 n742 n741 n1239 +0--- 0 +-111 0 +.names PC_2_ Pdata_35_ n745 n744 n748 n743 n1240 +0010-- 1 +01--11 1 +10--11 1 +1110-- 1 +.names PC_27_ Pdata_36_ n741 n736 n747 n1240 n1241 +00---1 0 +01110- 0 +10110- 0 +11---1 0 +.names n768 n769 n777 n775 n770 n771 n1242 +0-1110 1 +10---- 1 +.names n773 n768 n928 n790 n1242 n776 n1243 +0-11-0 1 +10110- 1 +11--1- 1 +-1---0 1 +.names n768 n777 n769 n778 n773 n770 n1244 +0001-- 0 +110-00 0 +.names n595 PD_12_ Pdata_47_ n592 n828 n597 n1245 +0--1-- 0 +1000-- 0 +1110-- 0 +-01011 0 +-10011 0 +.names n671 n673 n685 n676 n670 n679 n1246 +00100- 0 +00---1 0 +1011-- 0 +11100- 0 +.names n676 n840 n672 n684 n839 n674 n1247 +001--- 1 +0-00-0 1 +10-00- 1 +-01-0- 1 +.names Pdata_22_ n1237 n1235 n834 n1247 n1246 n1248 +00---- 1 +0-0--- 1 +0--0-- 1 +0---0- 1 +0----0 1 +111111 1 +.names n516 n520 n522 n511 n524 n518 n1249 +11-1-- 0 +1---11 0 +-11--- 0 +.names n521 n514 n513 n508 n523 n529 n1250 +00--1- 1 +011--1 1 +0-11-- 1 +.names n796 n801 n815 n804 n795 n800 n1251 +111--- 0 +1--111 0 +.names n1251 n797 n798 n807 n802 n1252 +10--0 1 +11-0- 1 +1-0-- 1 +.names n715 n703 PD_19_ Pdata_56_ n1253 +1001 1 +1010 1 +1100 1 +1111 1 +.names n710 n718 n706 n732 n1253 n704 n1254 +1001-- 0 +1111-- 0 +11---1 0 +--0-1- 0 +.names n710 n867 n707 n714 n1255 +01-- 0 +1-11 0 +.names n868 n1258 n724 n720 n1255 n1254 n1256 +111111 1 +.names n706 n722 PD_19_ Pdata_56_ n723 n714 n1257 +1101-- 1 +1110-- 1 +----11 1 +.names n866 n729 n728 n727 n1257 n710 n1258 +00000- 1 +0000-0 1 +.names n747 n737 n748 n750 n738 n744 n1259 +011--- 1 +1--110 1 +.names n871 n1259 n746 n736 n740 n741 n1260 +1----- 0 +-10--- 0 +---111 0 +.names n671 n689 n673 n670 n675 n684 n1261 +01100- 0 +01-11- 0 +11000- 0 +1-1--1 0 +.names n1235 n1261 n879 n690 n672 n880 n1262 +11001- 1 +1100-1 1 +.names n1237 n878 n677 n1262 n1263 +1111 1 +.names n773 n768 n770 n769 n771 n777 n1264 +0100-- 0 +100000 0 +1111-- 0 +111-10 0 +.names n1264 n777 n789 n788 n884 n883 n1265 +1000-1 1 +11001- 1 +.names n1293 n849 n847 n1265 n766 n1266 +11111 1 +.names n590 n592 n589 PD_18_ Pdata_51_ n597 n1267 +00001- 1 +00010- 1 +00100- 1 +00111- 1 +01---1 1 +10101- 1 +10110- 1 +.names n592 n607 n1267 n596 n602 n1268 +011-- 0 +11--1 0 +1-11- 0 +.names n886 n603 n598 n1300 n1268 n1269 +11111 1 +.names n732 n703 PD_19_ Pdata_56_ n710 n711 n1270 +10010- 0 +10100- 0 +11000- 0 +11110- 0 +11---1 0 +.names n800 n906 n905 n804 n795 n796 n1271 +0-1--- 0 +0--100 0 +10---- 0 +.names n817 n907 n801 n796 n797 n798 n1272 +1-1--- 0 +1--111 0 +-0---- 0 +.names n1252 n904 n818 n808 n1272 n1271 n1273 +111111 1 +.names n514 n515 PD_27_ Pdata_58_ n513 n529 n1274 +0101-1 0 +0110-1 0 +0---1- 0 +11000- 0 +11110- 0 +.names n558 n573 n550 n562 n560 n1275 +01--1 0 +110-- 0 +1-11- 0 +.names n1275 n558 n581 n564 n567 n1276 +10--0 1 +11-0- 1 +1-0-- 1 +.names n1232 n1227 n919 n576 n1276 n547 n1277 +111111 1 +.names n710 n709 n723 n714 n706 n933 n1278 +01-1-- 0 +1011-- 0 +101-1- 0 +----00 0 +.names Pdata_3_ n1258 n720 n712 n1278 n934 n1279 +00---- 1 +0-0--- 1 +0--0-- 1 +0---0- 1 +0----1 1 +111110 1 +.names n747 n945 n893 n744 n943 n746 n1280 +0---00 0 +1-00-- 0 +-0---- 0 +.names n1239 n1280 n752 n944 n1281 +1110 1 +.names n800 n810 n804 n814 n797 n1282 +10-10 1 +111-- 1 +.names n948 n947 n811 n807 n798 n1282 n1283 +0100-- 1 +010-0- 1 +01-0-0 1 +0-1-00 1 +.names n1252 n1283 n793 n808 n810 n826 n1284 +11111- 1 +1111-1 1 +.names n549 n558 n571 n555 n559 n552 n1285 +0011-- 0 +00--10 0 +10--11 0 +1111-- 0 +.names n1285 n572 n568 n560 n573 n1286 +1000- 1 +100-0 1 +.names n592 n588 n593 n596 n590 n1287 +0-1-- 1 +0--11 1 +11--- 1 +.names n592 n594 n1287 n589 n607 n1234 n1288 +0-1-1- 0 +1100-- 0 +11--1- 0 +---1-0 0 +.names n1288 n603 n598 n585 n589 n1233 n1289 +11111- 1 +1111-0 1 +.names n771 n770 n773 n768 n769 n777 n1290 +00-101 0 +011100 0 +0-0010 0 +1001-0 0 +11000- 0 +-00110 0 +.names n1293 n1243 n781 n1290 n766 n1291 +11111 1 +.names PD_3_ Pdata_32_ n771 n780 n773 n779 n1292 +000--- 0 +00-11- 0 +110--- 0 +11-11- 0 +--0--0 0 +.names n771 n768 n1292 Pdata_62_ PD_7_ n1244 n1293 +0-0--1 1 +111--- 1 +-01--1 1 +--1011 1 +--1101 1 +.names n592 n602 n589 n607 n588 n594 n1294 +011-1- 0 +01-1-- 0 +0--1-1 0 +111-0- 0 +--01-1 0 +.names n1294 n1245 n592 n593 n596 n938 n1295 +1010-- 1 +110--0 1 +1111-- 1 +1-101- 1 +.names Pdata_24_ n829 n598 n1295 n585 n1296 +00--- 1 +0-0-- 1 +0--0- 1 +0---0 1 +11111 1 +.names n508 n540 n510 n1250 n511 n534 n1297 +10---- 0 +1---10 0 +--01-- 0 +.names n1249 n842 n525 n1308 n1297 n506 n1298 +111111 1 +.names n588 n590 n592 n589 n587 n596 n1299 +10-11- 0 +111--1 0 +--01-- 0 +.names n592 n1299 n594 n595 n593 n597 n1300 +010--1 0 +0111-- 0 +10---- 0 +1--11- 0 +.names n710 n704 n706 n723 n715 n703 n1301 +01-1-- 0 +01--10 0 +1-0--- 0 +.names n710 n709 n1301 n867 n714 n933 n1302 +001--- 1 +0-1-0- 1 +1000-- 1 +-010-1 1 +-1100- 1 +.names n1270 n1302 n724 n720 n712 n866 n1303 +111110 1 +.names n1274 n916 n508 n513 n518 n1304 +00-1- 1 +100-- 1 +10--0 1 +.names n524 n521 n917 n517 n516 n510 n1305 +10--10 0 +11-1-- 0 +--1--- 0 +.names n525 n506 n1305 n1304 n519 n1306 +11110 1 +.names n515 n509 n523 n529 n517 n535 n1307 +111--- 0 +11-0-- 0 +1---10 0 +.names n1307 n535 Pdata_58_ PD_27_ n531 n508 n1308 +10---0 1 +1100-- 1 +1111-- 1 +1---0- 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/des/des.v b/openfpga_flow/benchmarks/mcnc_big20/des/des.v new file mode 100644 index 000000000..3128c9d26 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/des/des.v @@ -0,0 +1,1870 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module des(Preset_0_, Poutreg_63_, Poutreg_62_, Poutreg_61_, Poutreg_60_, Poutreg_59_, Poutreg_58_, Poutreg_57_, Poutreg_56_, Poutreg_55_, Poutreg_54_, Poutreg_53_, Poutreg_52_, Poutreg_51_, Poutreg_50_, Poutreg_49_, Poutreg_48_, Poutreg_47_, Poutreg_46_, Poutreg_45_, Poutreg_44_, Poutreg_43_, Poutreg_42_, Poutreg_41_, Poutreg_40_, Poutreg_39_, Poutreg_38_, Poutreg_37_, Poutreg_36_, Poutreg_35_, Poutreg_34_, Poutreg_33_, Poutreg_32_, Poutreg_31_, Poutreg_30_, Poutreg_29_, Poutreg_28_, Poutreg_27_, Poutreg_26_, Poutreg_25_, Poutreg_24_, Poutreg_23_, Poutreg_22_, Poutreg_21_, Poutreg_20_, Poutreg_19_, Poutreg_18_, Poutreg_17_, Poutreg_16_, Poutreg_15_, Poutreg_14_, Poutreg_13_, Poutreg_12_, Poutreg_11_, Poutreg_10_, Poutreg_9_, Poutreg_8_, Poutreg_7_, Poutreg_6_, Poutreg_5_, Poutreg_4_, Poutreg_3_, Poutreg_2_, Poutreg_1_, Poutreg_0_, Pload_key_0_, Pinreg_55_, Pinreg_54_, Pinreg_53_, Pinreg_52_, Pinreg_51_, Pinreg_50_, Pinreg_49_, Pinreg_48_, Pinreg_47_, Pinreg_46_, Pinreg_45_, Pinreg_44_, Pinreg_43_, Pinreg_42_, Pinreg_41_, Pinreg_40_, Pinreg_39_, Pinreg_38_, Pinreg_37_, Pinreg_36_, Pinreg_35_, Pinreg_34_, Pinreg_33_, Pinreg_32_, Pinreg_31_, Pinreg_30_, Pinreg_29_, Pinreg_28_, Pinreg_27_, Pinreg_26_, Pinreg_25_, Pinreg_24_, Pinreg_23_, Pinreg_22_, Pinreg_21_, Pinreg_20_, Pinreg_19_, Pinreg_18_, Pinreg_17_, Pinreg_16_, Pinreg_15_, Pinreg_14_, Pinreg_13_, Pinreg_12_, Pinreg_11_, Pinreg_10_, Pinreg_9_, Pinreg_8_, Pinreg_7_, Pinreg_6_, Pinreg_5_, Pinreg_4_, Pinreg_3_, Pinreg_2_, Pinreg_1_, Pinreg_0_, Pencrypt_mode_0_, Pencrypt_0_, Pdata_in_7_, Pdata_in_6_, Pdata_in_5_, Pdata_in_4_, Pdata_in_3_, Pdata_in_2_, Pdata_in_1_, Pdata_in_0_, Pdata_63_, Pdata_62_, Pdata_61_, Pdata_60_, Pdata_59_, Pdata_58_, Pdata_57_, Pdata_56_, Pdata_55_, Pdata_54_, Pdata_53_, Pdata_52_, Pdata_51_, Pdata_50_, Pdata_49_, Pdata_48_, Pdata_47_, Pdata_46_, Pdata_45_, Pdata_44_, Pdata_43_, Pdata_42_, Pdata_41_, Pdata_40_, Pdata_39_, Pdata_38_, Pdata_37_, Pdata_36_, Pdata_35_, Pdata_34_, Pdata_33_, Pdata_32_, Pdata_31_, Pdata_30_, Pdata_29_, Pdata_28_, Pdata_27_, Pdata_26_, Pdata_25_, Pdata_24_, Pdata_23_, Pdata_22_, Pdata_21_, Pdata_20_, Pdata_19_, Pdata_18_, Pdata_17_, Pdata_16_, Pdata_15_, Pdata_14_, Pdata_13_, Pdata_12_, Pdata_11_, Pdata_10_, Pdata_9_, Pdata_8_, Pdata_7_, Pdata_6_, Pdata_5_, Pdata_4_, Pdata_3_, Pdata_2_, Pdata_1_, Pdata_0_, Pcount_3_, Pcount_2_, Pcount_1_, Pcount_0_, PD_27_, PD_26_, PD_25_, PD_24_, PD_23_, PD_22_, PD_21_, PD_20_, PD_19_, PD_18_, PD_17_, PD_16_, PD_15_, PD_14_, PD_13_, PD_12_, PD_11_, PD_10_, PD_9_, PD_8_, PD_7_, PD_6_, PD_5_, PD_4_, PD_3_, PD_2_, PD_1_, PD_0_, PC_27_, PC_26_, PC_25_, PC_24_, PC_23_, PC_22_, PC_21_, PC_20_, PC_19_, PC_18_, PC_17_, PC_16_, PC_15_, PC_14_, PC_13_, PC_12_, PC_11_, PC_10_, PC_9_, PC_8_, PC_7_, PC_6_, PC_5_, PC_4_, PC_3_, PC_2_, PC_1_, PC_0_, Poutreg_new_63_, Poutreg_new_62_, Poutreg_new_61_, Poutreg_new_60_, Poutreg_new_59_, Poutreg_new_58_, Poutreg_new_57_, Poutreg_new_56_, Poutreg_new_55_, Poutreg_new_54_, Poutreg_new_53_, Poutreg_new_52_, Poutreg_new_51_, Poutreg_new_50_, Poutreg_new_49_, Poutreg_new_48_, Poutreg_new_47_, Poutreg_new_46_, Poutreg_new_45_, Poutreg_new_44_, Poutreg_new_43_, Poutreg_new_42_, Poutreg_new_41_, Poutreg_new_40_, Poutreg_new_39_, Poutreg_new_38_, Poutreg_new_37_, Poutreg_new_36_, Poutreg_new_35_, Poutreg_new_34_, Poutreg_new_33_, Poutreg_new_32_, Poutreg_new_31_, Poutreg_new_30_, Poutreg_new_29_, Poutreg_new_28_, Poutreg_new_27_, Poutreg_new_26_, Poutreg_new_25_, Poutreg_new_24_, Poutreg_new_23_, Poutreg_new_22_, Poutreg_new_21_, Poutreg_new_20_, Poutreg_new_19_, Poutreg_new_18_, Poutreg_new_17_, Poutreg_new_16_, Poutreg_new_15_, Poutreg_new_14_, Poutreg_new_13_, Poutreg_new_12_, Poutreg_new_11_, Poutreg_new_10_, Poutreg_new_9_, Poutreg_new_8_, Poutreg_new_7_, Poutreg_new_6_, Poutreg_new_5_, Poutreg_new_4_, Poutreg_new_3_, Poutreg_new_2_, Poutreg_new_1_, Poutreg_new_0_, Pinreg_new_55_, Pinreg_new_54_, Pinreg_new_53_, Pinreg_new_52_, Pinreg_new_51_, Pinreg_new_50_, Pinreg_new_49_, Pinreg_new_48_, Pinreg_new_47_, Pinreg_new_46_, Pinreg_new_45_, Pinreg_new_44_, Pinreg_new_43_, Pinreg_new_42_, Pinreg_new_41_, Pinreg_new_40_, Pinreg_new_39_, Pinreg_new_38_, Pinreg_new_37_, Pinreg_new_36_, Pinreg_new_35_, Pinreg_new_34_, Pinreg_new_33_, Pinreg_new_32_, Pinreg_new_31_, Pinreg_new_30_, Pinreg_new_29_, Pinreg_new_28_, Pinreg_new_27_, Pinreg_new_26_, Pinreg_new_25_, Pinreg_new_24_, Pinreg_new_23_, Pinreg_new_22_, Pinreg_new_21_, Pinreg_new_20_, Pinreg_new_19_, Pinreg_new_18_, Pinreg_new_17_, Pinreg_new_16_, Pinreg_new_15_, Pinreg_new_14_, Pinreg_new_13_, Pinreg_new_12_, Pinreg_new_11_, Pinreg_new_10_, Pinreg_new_9_, Pinreg_new_8_, Pinreg_new_7_, Pinreg_new_6_, Pinreg_new_5_, Pinreg_new_4_, Pinreg_new_3_, Pinreg_new_2_, Pinreg_new_1_, Pinreg_new_0_, Pencrypt_mode_new_0_, Pdata_new_63_, Pdata_new_62_, Pdata_new_61_, Pdata_new_60_, Pdata_new_59_, Pdata_new_58_, Pdata_new_57_, Pdata_new_56_, Pdata_new_55_, Pdata_new_54_, Pdata_new_53_, Pdata_new_52_, Pdata_new_51_, Pdata_new_50_, Pdata_new_49_, Pdata_new_48_, Pdata_new_47_, Pdata_new_46_, Pdata_new_45_, Pdata_new_44_, Pdata_new_43_, Pdata_new_42_, Pdata_new_41_, Pdata_new_40_, Pdata_new_39_, Pdata_new_38_, Pdata_new_37_, Pdata_new_36_, Pdata_new_35_, Pdata_new_34_, Pdata_new_33_, Pdata_new_32_, Pdata_new_31_, Pdata_new_30_, Pdata_new_29_, Pdata_new_28_, Pdata_new_27_, Pdata_new_26_, Pdata_new_25_, Pdata_new_24_, Pdata_new_23_, Pdata_new_22_, Pdata_new_21_, Pdata_new_20_, Pdata_new_19_, Pdata_new_18_, Pdata_new_17_, Pdata_new_16_, Pdata_new_15_, Pdata_new_14_, Pdata_new_13_, Pdata_new_12_, Pdata_new_11_, Pdata_new_10_, Pdata_new_9_, Pdata_new_8_, Pdata_new_7_, Pdata_new_6_, Pdata_new_5_, Pdata_new_4_, Pdata_new_3_, Pdata_new_2_, Pdata_new_1_, Pdata_new_0_, Pcount_new_3_, Pcount_new_2_, Pcount_new_1_, Pcount_new_0_, PD_new_27_, PD_new_26_, PD_new_25_, PD_new_24_, PD_new_23_, PD_new_22_, PD_new_21_, PD_new_20_, PD_new_19_, PD_new_18_, PD_new_17_, PD_new_16_, PD_new_15_, PD_new_14_, PD_new_13_, PD_new_12_, PD_new_11_, PD_new_10_, PD_new_9_, PD_new_8_, PD_new_7_, PD_new_6_, PD_new_5_, PD_new_4_, PD_new_3_, PD_new_2_, PD_new_1_, PD_new_0_, PC_new_27_, PC_new_26_, PC_new_25_, PC_new_24_, PC_new_23_, PC_new_22_, PC_new_21_, PC_new_20_, PC_new_19_, PC_new_18_, PC_new_17_, PC_new_16_, PC_new_15_, PC_new_14_, PC_new_13_, PC_new_12_, PC_new_11_, PC_new_10_, PC_new_9_, PC_new_8_, PC_new_7_, PC_new_6_, PC_new_5_, PC_new_4_, PC_new_3_, PC_new_2_, PC_new_1_, PC_new_0_); + input PC_0_; + input PC_10_; + input PC_11_; + input PC_12_; + input PC_13_; + input PC_14_; + input PC_15_; + input PC_16_; + input PC_17_; + input PC_18_; + input PC_19_; + input PC_1_; + input PC_20_; + input PC_21_; + input PC_22_; + input PC_23_; + input PC_24_; + input PC_25_; + input PC_26_; + input PC_27_; + input PC_2_; + input PC_3_; + input PC_4_; + input PC_5_; + input PC_6_; + input PC_7_; + input PC_8_; + input PC_9_; + output PC_new_0_; + output PC_new_10_; + output PC_new_11_; + output PC_new_12_; + output PC_new_13_; + output PC_new_14_; + output PC_new_15_; + output PC_new_16_; + output PC_new_17_; + output PC_new_18_; + output PC_new_19_; + output PC_new_1_; + output PC_new_20_; + output PC_new_21_; + output PC_new_22_; + output PC_new_23_; + output PC_new_24_; + output PC_new_25_; + output PC_new_26_; + output PC_new_27_; + output PC_new_2_; + output PC_new_3_; + output PC_new_4_; + output PC_new_5_; + output PC_new_6_; + output PC_new_7_; + output PC_new_8_; + output PC_new_9_; + input PD_0_; + input PD_10_; + input PD_11_; + input PD_12_; + input PD_13_; + input PD_14_; + input PD_15_; + input PD_16_; + input PD_17_; + input PD_18_; + input PD_19_; + input PD_1_; + input PD_20_; + input PD_21_; + input PD_22_; + input PD_23_; + input PD_24_; + input PD_25_; + input PD_26_; + input PD_27_; + input PD_2_; + input PD_3_; + input PD_4_; + input PD_5_; + input PD_6_; + input PD_7_; + input PD_8_; + input PD_9_; + output PD_new_0_; + output PD_new_10_; + output PD_new_11_; + output PD_new_12_; + output PD_new_13_; + output PD_new_14_; + output PD_new_15_; + output PD_new_16_; + output PD_new_17_; + output PD_new_18_; + output PD_new_19_; + output PD_new_1_; + output PD_new_20_; + output PD_new_21_; + output PD_new_22_; + output PD_new_23_; + output PD_new_24_; + output PD_new_25_; + output PD_new_26_; + output PD_new_27_; + output PD_new_2_; + output PD_new_3_; + output PD_new_4_; + output PD_new_5_; + output PD_new_6_; + output PD_new_7_; + output PD_new_8_; + output PD_new_9_; + input Pcount_0_; + input Pcount_1_; + input Pcount_2_; + input Pcount_3_; + output Pcount_new_0_; + output Pcount_new_1_; + output Pcount_new_2_; + output Pcount_new_3_; + input Pdata_0_; + input Pdata_10_; + input Pdata_11_; + input Pdata_12_; + input Pdata_13_; + input Pdata_14_; + input Pdata_15_; + input Pdata_16_; + input Pdata_17_; + input Pdata_18_; + input Pdata_19_; + input Pdata_1_; + input Pdata_20_; + input Pdata_21_; + input Pdata_22_; + input Pdata_23_; + input Pdata_24_; + input Pdata_25_; + input Pdata_26_; + input Pdata_27_; + input Pdata_28_; + input Pdata_29_; + input Pdata_2_; + input Pdata_30_; + input Pdata_31_; + input Pdata_32_; + input Pdata_33_; + input Pdata_34_; + input Pdata_35_; + input Pdata_36_; + input Pdata_37_; + input Pdata_38_; + input Pdata_39_; + input Pdata_3_; + input Pdata_40_; + input Pdata_41_; + input Pdata_42_; + input Pdata_43_; + input Pdata_44_; + input Pdata_45_; + input Pdata_46_; + input Pdata_47_; + input Pdata_48_; + input Pdata_49_; + input Pdata_4_; + input Pdata_50_; + input Pdata_51_; + input Pdata_52_; + input Pdata_53_; + input Pdata_54_; + input Pdata_55_; + input Pdata_56_; + input Pdata_57_; + input Pdata_58_; + input Pdata_59_; + input Pdata_5_; + input Pdata_60_; + input Pdata_61_; + input Pdata_62_; + input Pdata_63_; + input Pdata_6_; + input Pdata_7_; + input Pdata_8_; + input Pdata_9_; + input Pdata_in_0_; + input Pdata_in_1_; + input Pdata_in_2_; + input Pdata_in_3_; + input Pdata_in_4_; + input Pdata_in_5_; + input Pdata_in_6_; + input Pdata_in_7_; + output Pdata_new_0_; + output Pdata_new_10_; + output Pdata_new_11_; + output Pdata_new_12_; + output Pdata_new_13_; + output Pdata_new_14_; + output Pdata_new_15_; + output Pdata_new_16_; + output Pdata_new_17_; + output Pdata_new_18_; + output Pdata_new_19_; + output Pdata_new_1_; + output Pdata_new_20_; + output Pdata_new_21_; + output Pdata_new_22_; + output Pdata_new_23_; + output Pdata_new_24_; + output Pdata_new_25_; + output Pdata_new_26_; + output Pdata_new_27_; + output Pdata_new_28_; + output Pdata_new_29_; + output Pdata_new_2_; + output Pdata_new_30_; + output Pdata_new_31_; + output Pdata_new_32_; + output Pdata_new_33_; + output Pdata_new_34_; + output Pdata_new_35_; + output Pdata_new_36_; + output Pdata_new_37_; + output Pdata_new_38_; + output Pdata_new_39_; + output Pdata_new_3_; + output Pdata_new_40_; + output Pdata_new_41_; + output Pdata_new_42_; + output Pdata_new_43_; + output Pdata_new_44_; + output Pdata_new_45_; + output Pdata_new_46_; + output Pdata_new_47_; + output Pdata_new_48_; + output Pdata_new_49_; + output Pdata_new_4_; + output Pdata_new_50_; + output Pdata_new_51_; + output Pdata_new_52_; + output Pdata_new_53_; + output Pdata_new_54_; + output Pdata_new_55_; + output Pdata_new_56_; + output Pdata_new_57_; + output Pdata_new_58_; + output Pdata_new_59_; + output Pdata_new_5_; + output Pdata_new_60_; + output Pdata_new_61_; + output Pdata_new_62_; + output Pdata_new_63_; + output Pdata_new_6_; + output Pdata_new_7_; + output Pdata_new_8_; + output Pdata_new_9_; + input Pencrypt_0_; + input Pencrypt_mode_0_; + output Pencrypt_mode_new_0_; + input Pinreg_0_; + input Pinreg_10_; + input Pinreg_11_; + input Pinreg_12_; + input Pinreg_13_; + input Pinreg_14_; + input Pinreg_15_; + input Pinreg_16_; + input Pinreg_17_; + input Pinreg_18_; + input Pinreg_19_; + input Pinreg_1_; + input Pinreg_20_; + input Pinreg_21_; + input Pinreg_22_; + input Pinreg_23_; + input Pinreg_24_; + input Pinreg_25_; + input Pinreg_26_; + input Pinreg_27_; + input Pinreg_28_; + input Pinreg_29_; + input Pinreg_2_; + input Pinreg_30_; + input Pinreg_31_; + input Pinreg_32_; + input Pinreg_33_; + input Pinreg_34_; + input Pinreg_35_; + input Pinreg_36_; + input Pinreg_37_; + input Pinreg_38_; + input Pinreg_39_; + input Pinreg_3_; + input Pinreg_40_; + input Pinreg_41_; + input Pinreg_42_; + input Pinreg_43_; + input Pinreg_44_; + input Pinreg_45_; + input Pinreg_46_; + input Pinreg_47_; + input Pinreg_48_; + input Pinreg_49_; + input Pinreg_4_; + input Pinreg_50_; + input Pinreg_51_; + input Pinreg_52_; + input Pinreg_53_; + input Pinreg_54_; + input Pinreg_55_; + input Pinreg_5_; + input Pinreg_6_; + input Pinreg_7_; + input Pinreg_8_; + input Pinreg_9_; + output Pinreg_new_0_; + output Pinreg_new_10_; + output Pinreg_new_11_; + output Pinreg_new_12_; + output Pinreg_new_13_; + output Pinreg_new_14_; + output Pinreg_new_15_; + output Pinreg_new_16_; + output Pinreg_new_17_; + output Pinreg_new_18_; + output Pinreg_new_19_; + output Pinreg_new_1_; + output Pinreg_new_20_; + output Pinreg_new_21_; + output Pinreg_new_22_; + output Pinreg_new_23_; + output Pinreg_new_24_; + output Pinreg_new_25_; + output Pinreg_new_26_; + output Pinreg_new_27_; + output Pinreg_new_28_; + output Pinreg_new_29_; + output Pinreg_new_2_; + output Pinreg_new_30_; + output Pinreg_new_31_; + output Pinreg_new_32_; + output Pinreg_new_33_; + output Pinreg_new_34_; + output Pinreg_new_35_; + output Pinreg_new_36_; + output Pinreg_new_37_; + output Pinreg_new_38_; + output Pinreg_new_39_; + output Pinreg_new_3_; + output Pinreg_new_40_; + output Pinreg_new_41_; + output Pinreg_new_42_; + output Pinreg_new_43_; + output Pinreg_new_44_; + output Pinreg_new_45_; + output Pinreg_new_46_; + output Pinreg_new_47_; + output Pinreg_new_48_; + output Pinreg_new_49_; + output Pinreg_new_4_; + output Pinreg_new_50_; + output Pinreg_new_51_; + output Pinreg_new_52_; + output Pinreg_new_53_; + output Pinreg_new_54_; + output Pinreg_new_55_; + output Pinreg_new_5_; + output Pinreg_new_6_; + output Pinreg_new_7_; + output Pinreg_new_8_; + output Pinreg_new_9_; + input Pload_key_0_; + input Poutreg_0_; + input Poutreg_10_; + input Poutreg_11_; + input Poutreg_12_; + input Poutreg_13_; + input Poutreg_14_; + input Poutreg_15_; + input Poutreg_16_; + input Poutreg_17_; + input Poutreg_18_; + input Poutreg_19_; + input Poutreg_1_; + input Poutreg_20_; + input Poutreg_21_; + input Poutreg_22_; + input Poutreg_23_; + input Poutreg_24_; + input Poutreg_25_; + input Poutreg_26_; + input Poutreg_27_; + input Poutreg_28_; + input Poutreg_29_; + input Poutreg_2_; + input Poutreg_30_; + input Poutreg_31_; + input Poutreg_32_; + input Poutreg_33_; + input Poutreg_34_; + input Poutreg_35_; + input Poutreg_36_; + input Poutreg_37_; + input Poutreg_38_; + input Poutreg_39_; + input Poutreg_3_; + input Poutreg_40_; + input Poutreg_41_; + input Poutreg_42_; + input Poutreg_43_; + input Poutreg_44_; + input Poutreg_45_; + input Poutreg_46_; + input Poutreg_47_; + input Poutreg_48_; + input Poutreg_49_; + input Poutreg_4_; + input Poutreg_50_; + input Poutreg_51_; + input Poutreg_52_; + input Poutreg_53_; + input Poutreg_54_; + input Poutreg_55_; + input Poutreg_56_; + input Poutreg_57_; + input Poutreg_58_; + input Poutreg_59_; + input Poutreg_5_; + input Poutreg_60_; + input Poutreg_61_; + input Poutreg_62_; + input Poutreg_63_; + input Poutreg_6_; + input Poutreg_7_; + input Poutreg_8_; + input Poutreg_9_; + output Poutreg_new_0_; + output Poutreg_new_10_; + output Poutreg_new_11_; + output Poutreg_new_12_; + output Poutreg_new_13_; + output Poutreg_new_14_; + output Poutreg_new_15_; + output Poutreg_new_16_; + output Poutreg_new_17_; + output Poutreg_new_18_; + output Poutreg_new_19_; + output Poutreg_new_1_; + output Poutreg_new_20_; + output Poutreg_new_21_; + output Poutreg_new_22_; + output Poutreg_new_23_; + output Poutreg_new_24_; + output Poutreg_new_25_; + output Poutreg_new_26_; + output Poutreg_new_27_; + output Poutreg_new_28_; + output Poutreg_new_29_; + output Poutreg_new_2_; + output Poutreg_new_30_; + output Poutreg_new_31_; + output Poutreg_new_32_; + output Poutreg_new_33_; + output Poutreg_new_34_; + output Poutreg_new_35_; + output Poutreg_new_36_; + output Poutreg_new_37_; + output Poutreg_new_38_; + output Poutreg_new_39_; + output Poutreg_new_3_; + output Poutreg_new_40_; + output Poutreg_new_41_; + output Poutreg_new_42_; + output Poutreg_new_43_; + output Poutreg_new_44_; + output Poutreg_new_45_; + output Poutreg_new_46_; + output Poutreg_new_47_; + output Poutreg_new_48_; + output Poutreg_new_49_; + output Poutreg_new_4_; + output Poutreg_new_50_; + output Poutreg_new_51_; + output Poutreg_new_52_; + output Poutreg_new_53_; + output Poutreg_new_54_; + output Poutreg_new_55_; + output Poutreg_new_56_; + output Poutreg_new_57_; + output Poutreg_new_58_; + output Poutreg_new_59_; + output Poutreg_new_5_; + output Poutreg_new_60_; + output Poutreg_new_61_; + output Poutreg_new_62_; + output Poutreg_new_63_; + output Poutreg_new_6_; + output Poutreg_new_7_; + output Poutreg_new_8_; + output Poutreg_new_9_; + input Preset_0_; + wire n1000; + wire n1001; + wire n1003; + wire n1004; + wire n1006; + wire n1007; + wire n1009; + wire n1010; + wire n1012; + wire n1013; + wire n1015; + wire n1016; + wire n1018; + wire n1019; + wire n1021; + wire n1022; + wire n1024; + wire n1025; + wire n1027; + wire n1028; + wire n1030; + wire n1031; + wire n1033; + wire n1034; + wire n1036; + wire n1037; + wire n1039; + wire n1040; + wire n1042; + wire n1043; + wire n1045; + wire n1046; + wire n1048; + wire n1049; + wire n1051; + wire n1052; + wire n1054; + wire n1055; + wire n1057; + wire n1058; + wire n1060; + wire n1061; + wire n1063; + wire n1064; + wire n1066; + wire n1067; + wire n1069; + wire n1070; + wire n1072; + wire n1073; + wire n1075; + wire n1076; + wire n1078; + wire n1079; + wire n1081; + wire n1082; + wire n1084; + wire n1085; + wire n1087; + wire n1088; + wire n1090; + wire n1091; + wire n1093; + wire n1094; + wire n1096; + wire n1097; + wire n1099; + wire n1100; + wire n1102; + wire n1103; + wire n1105; + wire n1106; + wire n1108; + wire n1109; + wire n1111; + wire n1112; + wire n1114; + wire n1115; + wire n1117; + wire n1118; + wire n1120; + wire n1121; + wire n1123; + wire n1124; + wire n1126; + wire n1127; + wire n1129; + wire n1130; + wire n1132; + wire n1133; + wire n1135; + wire n1136; + wire n1138; + wire n1139; + wire n1141; + wire n1142; + wire n1144; + wire n1145; + wire n1147; + wire n1148; + wire n1150; + wire n1151; + wire n1153; + wire n1154; + wire n1156; + wire n1157; + wire n1159; + wire n1160; + wire n1172; + wire n1177; + wire n1188; + wire n1199; + wire n1202; + wire n1205; + wire n1222; + wire n1224; + wire n1225; + wire n1226; + wire n1227; + wire n1228; + wire n1229; + wire n1230; + wire n1231; + wire n1232; + wire n1233; + wire n1234; + wire n1235; + wire n1236; + wire n1237; + wire n1238; + wire n1239; + wire n1240; + wire n1241; + wire n1242; + wire n1243; + wire n1244; + wire n1245; + wire n1246; + wire n1247; + wire n1248; + wire n1249; + wire n1250; + wire n1251; + wire n1252; + wire n1253; + wire n1254; + wire n1255; + wire n1256; + wire n1257; + wire n1258; + wire n1259; + wire n1260; + wire n1261; + wire n1262; + wire n1263; + wire n1264; + wire n1265; + wire n1266; + wire n1267; + wire n1268; + wire n1269; + wire n1270; + wire n1271; + wire n1272; + wire n1273; + wire n1274; + wire n1275; + wire n1276; + wire n1277; + wire n1278; + wire n1279; + wire n1280; + wire n1281; + wire n1282; + wire n1283; + wire n1284; + wire n1285; + wire n1286; + wire n1287; + wire n1288; + wire n1289; + wire n1290; + wire n1291; + wire n1292; + wire n1293; + wire n1294; + wire n1295; + wire n1296; + wire n1297; + wire n1298; + wire n1299; + wire n1300; + wire n1301; + wire n1302; + wire n1303; + wire n1304; + wire n1305; + wire n1306; + wire n1307; + wire n1308; + wire n505; + wire n506; + wire n507; + wire n508; + wire n509; + wire n510; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n530; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n540; + wire n541; + wire n542; + wire n543; + wire n544; + wire n547; + wire n548; + wire n549; + wire n550; + wire n551; + wire n552; + wire n553; + wire n554; + wire n555; + wire n556; + wire n557; + wire n558; + wire n559; + wire n560; + wire n561; + wire n562; + wire n563; + wire n564; + wire n565; + wire n566; + wire n567; + wire n568; + wire n569; + wire n570; + wire n571; + wire n572; + wire n573; + wire n576; + wire n577; + wire n578; + wire n579; + wire n580; + wire n581; + wire n582; + wire n585; + wire n586; + wire n587; + wire n588; + wire n589; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n598; + wire n599; + wire n600; + wire n601; + wire n602; + wire n603; + wire n604; + wire n605; + wire n606; + wire n607; + wire n668; + wire n669; + wire n670; + wire n671; + wire n672; + wire n673; + wire n674; + wire n675; + wire n676; + wire n677; + wire n678; + wire n679; + wire n680; + wire n681; + wire n682; + wire n683; + wire n684; + wire n685; + wire n686; + wire n687; + wire n688; + wire n689; + wire n690; + wire n692; + wire n693; + wire n694; + wire n695; + wire n696; + wire n697; + wire n699; + wire n700; + wire n701; + wire n702; + wire n703; + wire n704; + wire n705; + wire n706; + wire n707; + wire n708; + wire n709; + wire n710; + wire n711; + wire n712; + wire n713; + wire n714; + wire n715; + wire n716; + wire n717; + wire n718; + wire n719; + wire n720; + wire n721; + wire n722; + wire n723; + wire n724; + wire n725; + wire n726; + wire n727; + wire n728; + wire n729; + wire n730; + wire n731; + wire n732; + wire n734; + wire n735; + wire n736; + wire n737; + wire n738; + wire n739; + wire n740; + wire n741; + wire n742; + wire n743; + wire n744; + wire n745; + wire n746; + wire n747; + wire n748; + wire n749; + wire n750; + wire n751; + wire n752; + wire n753; + wire n754; + wire n755; + wire n756; + wire n757; + wire n758; + wire n759; + wire n760; + wire n761; + wire n762; + wire n763; + wire n764; + wire n766; + wire n767; + wire n768; + wire n769; + wire n770; + wire n771; + wire n772; + wire n773; + wire n774; + wire n775; + wire n776; + wire n777; + wire n778; + wire n779; + wire n780; + wire n781; + wire n782; + wire n783; + wire n784; + wire n785; + wire n786; + wire n787; + wire n788; + wire n789; + wire n790; + wire n792; + wire n793; + wire n794; + wire n795; + wire n796; + wire n797; + wire n798; + wire n799; + wire n800; + wire n801; + wire n802; + wire n803; + wire n804; + wire n805; + wire n806; + wire n807; + wire n808; + wire n809; + wire n810; + wire n811; + wire n812; + wire n813; + wire n814; + wire n815; + wire n816; + wire n817; + wire n818; + wire n819; + wire n820; + wire n821; + wire n822; + wire n823; + wire n824; + wire n825; + wire n826; + wire n828; + wire n829; + wire n830; + wire n831; + wire n834; + wire n835; + wire n836; + wire n837; + wire n838; + wire n839; + wire n840; + wire n842; + wire n843; + wire n844; + wire n846; + wire n847; + wire n848; + wire n849; + wire n850; + wire n851; + wire n852; + wire n853; + wire n854; + wire n855; + wire n856; + wire n857; + wire n859; + wire n860; + wire n861; + wire n862; + wire n863; + wire n864; + wire n866; + wire n867; + wire n868; + wire n870; + wire n871; + wire n872; + wire n873; + wire n874; + wire n875; + wire n876; + wire n878; + wire n879; + wire n880; + wire n883; + wire n884; + wire n886; + wire n888; + wire n889; + wire n890; + wire n891; + wire n892; + wire n893; + wire n895; + wire n896; + wire n897; + wire n898; + wire n899; + wire n900; + wire n901; + wire n904; + wire n905; + wire n906; + wire n907; + wire n909; + wire n910; + wire n911; + wire n912; + wire n915; + wire n916; + wire n917; + wire n919; + wire n920; + wire n921; + wire n923; + wire n924; + wire n925; + wire n926; + wire n927; + wire n928; + wire n929; + wire n930; + wire n931; + wire n933; + wire n934; + wire n936; + wire n937; + wire n938; + wire n939; + wire n940; + wire n941; + wire n943; + wire n944; + wire n945; + wire n947; + wire n948; + wire n986; + wire n987; + wire n988; + wire n989; + wire n990; + wire n991; + wire n992; + wire n993; + wire n994; + wire n995; + wire n997; + wire n998; + assign Poutreg_new_7_ = 64'hd7ffd78282ff8282 >> { Poutreg_15_, Poutreg_7_, Pcount_0_, n505, Pdata_31_, n544 }; + assign n513 = 4'h9 >> { Pdata_59_, PD_5_ }; + assign n603 = 64'h0015151515151515 >> { n606, n601, n602, n599, n605, n604 }; + assign n604 = 16'h0002 >> { n592, n590, n596, n597 }; + assign n605 = 8'h08 >> { n592, n589, n595 }; + assign n606 = 16'h6006 >> { Pdata_47_, PD_12_, Pdata_49_, PD_2_ }; + assign n607 = 16'h1428 >> { Pdata_52_, Pdata_48_, PD_23_, PD_26_ }; + assign Poutreg_new_0_ = 32'd4158838208 >> { Poutreg_8_, Poutreg_0_, Pdata_39_, n544, Pcount_0_ }; + assign Pinreg_new_55_ = 16'h44e4 >> { n544, Pinreg_47_, Pinreg_55_, Pcount_0_ }; + assign Pinreg_new_54_ = 16'h44e4 >> { n544, Pinreg_46_, Pinreg_54_, Pcount_0_ }; + assign Pinreg_new_53_ = 16'h44e4 >> { n544, Pinreg_45_, Pinreg_53_, Pcount_0_ }; + assign Pinreg_new_52_ = 16'h44e4 >> { n544, Pinreg_44_, Pinreg_52_, Pcount_0_ }; + assign n514 = 4'h6 >> { Pdata_55_, PD_15_ }; + assign Pinreg_new_51_ = 16'h44e4 >> { n544, Pinreg_43_, Pinreg_51_, Pcount_0_ }; + assign Pinreg_new_50_ = 16'h44e4 >> { n544, Pinreg_42_, Pinreg_50_, Pcount_0_ }; + assign Pinreg_new_49_ = 16'h44e4 >> { n544, Pinreg_41_, Pinreg_49_, Pcount_0_ }; + assign Pinreg_new_48_ = 16'h44e4 >> { n544, Pinreg_40_, Pinreg_48_, Pcount_0_ }; + assign Pinreg_new_47_ = 16'h44e4 >> { n544, Pinreg_39_, Pinreg_47_, Pcount_0_ }; + assign Pinreg_new_46_ = 16'h44e4 >> { n544, Pinreg_38_, Pinreg_46_, Pcount_0_ }; + assign Pinreg_new_45_ = 16'h44e4 >> { n544, Pinreg_37_, Pinreg_45_, Pcount_0_ }; + assign Pinreg_new_44_ = 16'h44e4 >> { n544, Pinreg_36_, Pinreg_44_, Pcount_0_ }; + assign Pinreg_new_43_ = 16'h44e4 >> { n544, Pinreg_35_, Pinreg_43_, Pcount_0_ }; + assign Pinreg_new_42_ = 16'h44e4 >> { n544, Pinreg_34_, Pinreg_42_, Pcount_0_ }; + assign n515 = 16'h6006 >> { Pdata_60_, PD_24_, Pdata_57_, PD_10_ }; + assign Pinreg_new_41_ = 16'h44e4 >> { n544, Pinreg_33_, Pinreg_41_, Pcount_0_ }; + assign Pinreg_new_40_ = 16'h44e4 >> { n544, Pinreg_32_, Pinreg_40_, Pcount_0_ }; + assign Pinreg_new_39_ = 16'h44e4 >> { n544, Pinreg_31_, Pinreg_39_, Pcount_0_ }; + assign Pinreg_new_38_ = 16'h44e4 >> { n544, Pinreg_30_, Pinreg_38_, Pcount_0_ }; + assign Pinreg_new_37_ = 16'h44e4 >> { n544, Pinreg_29_, Pinreg_37_, Pcount_0_ }; + assign Pinreg_new_36_ = 16'h44e4 >> { n544, Pinreg_28_, Pinreg_36_, Pcount_0_ }; + assign Pinreg_new_35_ = 16'h44e4 >> { n544, Pinreg_27_, Pinreg_35_, Pcount_0_ }; + assign Pinreg_new_34_ = 16'h44e4 >> { n544, Pinreg_26_, Pinreg_34_, Pcount_0_ }; + assign Pinreg_new_33_ = 16'h44e4 >> { n544, Pinreg_25_, Pinreg_33_, Pcount_0_ }; + assign Pinreg_new_32_ = 16'h44e4 >> { n544, Pinreg_24_, Pinreg_32_, Pcount_0_ }; + assign n516 = 16'h9009 >> { Pdata_58_, PD_27_, Pdata_56_, PD_20_ }; + assign Pinreg_new_31_ = 16'h44e4 >> { n544, Pinreg_23_, Pinreg_31_, Pcount_0_ }; + assign Pinreg_new_30_ = 16'h44e4 >> { n544, Pinreg_22_, Pinreg_30_, Pcount_0_ }; + assign Pinreg_new_29_ = 16'h44e4 >> { n544, Pinreg_21_, Pinreg_29_, Pcount_0_ }; + assign Pinreg_new_28_ = 16'h44e4 >> { n544, Pinreg_20_, Pinreg_28_, Pcount_0_ }; + assign Pinreg_new_27_ = 16'h44e4 >> { n544, Pinreg_19_, Pinreg_27_, Pcount_0_ }; + assign Pinreg_new_26_ = 16'h44e4 >> { n544, Pinreg_18_, Pinreg_26_, Pcount_0_ }; + assign Pinreg_new_25_ = 16'h44e4 >> { n544, Pinreg_17_, Pinreg_25_, Pcount_0_ }; + assign Pinreg_new_24_ = 16'h44e4 >> { n544, Pinreg_16_, Pinreg_24_, Pcount_0_ }; + assign Pinreg_new_23_ = 16'h44e4 >> { n544, Pinreg_15_, Pinreg_23_, Pcount_0_ }; + assign Pinreg_new_22_ = 16'h44e4 >> { n544, Pinreg_14_, Pinreg_22_, Pcount_0_ }; + assign n517 = 16'h1428 >> { Pdata_58_, Pdata_56_, PD_20_, PD_27_ }; + assign Pinreg_new_21_ = 16'h44e4 >> { n544, Pinreg_13_, Pinreg_21_, Pcount_0_ }; + assign Pinreg_new_20_ = 16'h44e4 >> { n544, Pinreg_12_, Pinreg_20_, Pcount_0_ }; + assign Pinreg_new_19_ = 16'h44e4 >> { n544, Pinreg_11_, Pinreg_19_, Pcount_0_ }; + assign Pinreg_new_18_ = 16'h44e4 >> { n544, Pinreg_10_, Pinreg_18_, Pcount_0_ }; + assign Pinreg_new_17_ = 16'h44e4 >> { n544, Pinreg_9_, Pinreg_17_, Pcount_0_ }; + assign Pinreg_new_16_ = 16'h44e4 >> { n544, Pinreg_8_, Pinreg_16_, Pcount_0_ }; + assign Pinreg_new_15_ = 16'h44e4 >> { n544, Pinreg_7_, Pinreg_15_, Pcount_0_ }; + assign Pinreg_new_14_ = 16'h44e4 >> { n544, Pinreg_6_, Pinreg_14_, Pcount_0_ }; + assign Pinreg_new_13_ = 16'h44e4 >> { n544, Pinreg_5_, Pinreg_13_, Pcount_0_ }; + assign Pinreg_new_12_ = 16'h44e4 >> { n544, Pinreg_4_, Pinreg_12_, Pcount_0_ }; + assign n518 = 16'h4182 >> { Pdata_60_, Pdata_57_, PD_10_, PD_24_ }; + assign Pinreg_new_11_ = 16'h44e4 >> { n544, Pinreg_3_, Pinreg_11_, Pcount_0_ }; + assign Pinreg_new_10_ = 16'h44e4 >> { n544, Pinreg_2_, Pinreg_10_, Pcount_0_ }; + assign Pinreg_new_9_ = 16'h44e4 >> { n544, Pinreg_1_, Pinreg_9_, Pcount_0_ }; + assign Pinreg_new_8_ = 16'h44e4 >> { n544, Pinreg_0_, Pinreg_8_, Pcount_0_ }; + assign Pinreg_new_7_ = 16'h44e4 >> { n544, Pdata_in_7_, Pinreg_7_, Pcount_0_ }; + assign Pinreg_new_6_ = 16'h44e4 >> { n544, Pdata_in_6_, Pinreg_6_, Pcount_0_ }; + assign Pinreg_new_5_ = 16'h44e4 >> { n544, Pdata_in_5_, Pinreg_5_, Pcount_0_ }; + assign Pinreg_new_4_ = 16'h44e4 >> { n544, Pdata_in_4_, Pinreg_4_, Pcount_0_ }; + assign Pinreg_new_3_ = 16'h44e4 >> { n544, Pdata_in_3_, Pinreg_3_, Pcount_0_ }; + assign Pinreg_new_2_ = 16'h44e4 >> { n544, Pdata_in_2_, Pinreg_2_, Pcount_0_ }; + assign n519 = 16'ha888 >> { n511, n516, n522, n520 }; + assign Pinreg_new_1_ = 16'h44e4 >> { n544, Pdata_in_1_, Pinreg_1_, Pcount_0_ }; + assign Pinreg_new_0_ = 16'h44e4 >> { n544, Pdata_in_0_, Pinreg_0_, Pcount_0_ }; + assign Pencrypt_mode_new_0_ = 8'hd8 >> { Pencrypt_mode_0_, Pencrypt_0_, n544 }; + assign Pdata_new_63_ = 16'heb41 >> { Pdata_in_6_, Pdata_31_, n505, n544 }; + assign Pdata_new_62_ = 16'heb41 >> { Pinreg_6_, n668, Pdata_30_, n544 }; + assign n668 = 64'h0000000080000000 >> { n690, n677, n680, n686, n1237, n1235 }; + assign n669 = 4'h2 >> { n670, n671 }; + assign n670 = 4'h6 >> { Pdata_32_, PC_16_ }; + assign n671 = 4'h6 >> { Pdata_35_, PC_0_ }; + assign n672 = 4'h6 >> { Pdata_33_, PC_10_ }; + assign n520 = 4'h1 >> { n510, n521 }; + assign n673 = 4'h6 >> { Pdata_36_, PC_4_ }; + assign n674 = 64'h6006000000006006 >> { Pdata_36_, PC_4_, Pdata_35_, PC_0_, PC_16_, Pdata_32_ }; + assign n675 = 4'h6 >> { Pdata_34_, PC_23_ }; + assign n676 = 4'h6 >> { Pdata_63_, PC_13_ }; + assign n677 = 32'd4025470447 >> { n671, n679, n678, n676, n673 }; + assign n678 = 16'h0002 >> { n672, n670, n671, n675 }; + assign n679 = 64'h0000099009900000 >> { Pdata_34_, PC_23_, Pdata_33_, PC_10_, Pdata_32_, PC_16_ }; + assign n680 = 64'hff7b000055510000 >> { n681, n682, n683, n672, n669, n673 }; + assign n681 = 64'h95ffff95b7ffffb7 >> { n675, Pdata_35_, PC_0_, n676, n670, n672 }; + assign n682 = 16'h1357 >> { n683, n684, n674, n685 }; + assign n521 = 4'h6 >> { Pdata_57_, PD_10_ }; + assign n683 = 16'h9669 >> { Pdata_63_, Pdata_34_, PC_23_, PC_13_ }; + assign n684 = 64'h6006000000006006 >> { Pdata_63_, PC_13_, Pdata_34_, PC_23_, PC_16_, Pdata_32_ }; + assign n685 = 16'h6006 >> { Pdata_34_, PC_23_, Pdata_33_, PC_10_ }; + assign n686 = 8'h54 >> { n672, n688, n687 }; + assign n687 = 16'h0082 >> { n673, n676, n671, n679 }; + assign n688 = 32'd4286545919 >> { n675, n676, n673, n670, n671 }; + assign n689 = 16'h1428 >> { Pdata_63_, Pdata_33_, PC_10_, PC_13_ }; + assign n690 = 64'h8000000000000008 >> { n673, n675, n670, n671, n672, n676 }; + assign Pdata_new_61_ = 16'heb41 >> { Pinreg_14_, n692, Pdata_29_, n544 }; + assign n692 = 64'h0000000080000000 >> { n697, n556, n1227, n1232, n693, n547 }; + assign n522 = 4'h8 >> { n523, n524 }; + assign n693 = 16'h2220 >> { n552, n695, n694, n696 }; + assign n694 = 64'h008200aa00000028 >> { n564, n582, n550, Pdata_42_, PC_3_, n549 }; + assign n695 = 16'hff79 >> { n561, n549, n558, n550 }; + assign n696 = 64'h696f6fff696fffff >> { n566, n581, n552, n558, Pdata_40_, PC_18_ }; + assign n697 = 8'h08 >> { n558, n561, n562 }; + assign Pdata_new_60_ = 16'heb41 >> { Pinreg_22_, n699, Pdata_28_, n544 }; + assign n699 = 64'h0000000080000000 >> { n700, n712, n720, n724, n726, n730 }; + assign n700 = 64'h8a8a8a8aaa8a8a8a >> { n702, n703, n711, n705, n701, n710 }; + assign n701 = 32'd2148042888 >> { n703, Pdata_51_, PD_1_, n702, n704 }; + assign n702 = 4'h6 >> { Pdata_55_, PD_4_ }; + assign n505 = 64'h0000000080000000 >> { n519, n506, n525, n527, n532, n539 }; + assign n523 = 16'h4182 >> { Pdata_58_, Pdata_56_, PD_20_, PD_27_ }; + assign n703 = 4'h6 >> { Pdata_54_, PD_16_ }; + assign n704 = 16'h4182 >> { Pdata_56_, Pdata_52_, PD_11_, PD_19_ }; + assign n705 = 64'h060666660f9f6fff >> { n708, n707, n709, n706, Pdata_56_, PD_19_ }; + assign n706 = 4'h6 >> { Pdata_52_, PD_11_ }; + assign n707 = 64'h6006000000006006 >> { Pdata_55_, PD_4_, Pdata_54_, PD_16_, PD_1_, Pdata_51_ }; + assign n708 = 64'h0990000000000990 >> { Pdata_55_, PD_4_, PD_16_, Pdata_54_, Pdata_51_, PD_1_ }; + assign n709 = 64'h0000066006600000 >> { Pdata_55_, PD_4_, PD_16_, Pdata_54_, Pdata_51_, PD_1_ }; + assign n710 = 4'h6 >> { Pdata_53_, PD_22_ }; + assign n711 = 16'h9009 >> { Pdata_56_, PD_19_, Pdata_52_, PD_11_ }; + assign n712 = 16'h2aaa >> { n719, n702, n718, n713 }; + assign n524 = 16'h4182 >> { Pdata_55_, Pdata_59_, PD_5_, PD_15_ }; + assign n713 = 32'd712998783 >> { n715, n717, n714, n716, n710 }; + assign n714 = 16'h6006 >> { Pdata_56_, PD_19_, Pdata_52_, PD_11_ }; + assign n715 = 16'h1428 >> { Pdata_55_, Pdata_51_, PD_1_, PD_4_ }; + assign n716 = 64'h9009000000009009 >> { Pdata_55_, PD_4_, Pdata_54_, PD_16_, Pdata_51_, PD_1_ }; + assign n717 = 64'h9009000000009009 >> { Pdata_56_, PD_19_, Pdata_54_, PD_16_, Pdata_52_, PD_11_ }; + assign n718 = 16'h6996 >> { Pdata_54_, Pdata_51_, PD_1_, PD_16_ }; + assign n719 = 64'h0000600660060000 >> { Pdata_56_, PD_19_, Pdata_53_, PD_22_, Pdata_52_, PD_11_ }; + assign n720 = 64'h2a3b3b3b2a7f7f7f >> { n722, n711, n723, n721, n704, n710 }; + assign n721 = 16'h0028 >> { n702, Pdata_51_, PD_1_, n703 }; + assign n722 = 64'h0000900990090000 >> { Pdata_55_, PD_4_, Pdata_54_, PD_16_, Pdata_51_, PD_1_ }; + assign n525 = 32'd1568636799 >> { n513, n526, n516, n509, n518 }; + assign n723 = 64'h0000699669960000 >> { Pdata_54_, PD_16_, Pdata_55_, Pdata_51_, PD_1_, PD_4_ }; + assign n724 = 8'h2a >> { n719, n709, n725 }; + assign n725 = 64'h13331bbb57775fff >> { n707, n722, n704, n716, n714, n710 }; + assign n726 = 32'd65793 >> { n719, n716, n729, n727, n728 }; + assign n727 = 32'd539011104 >> { n703, n715, n722, n710, n714 }; + assign n728 = 4'h8 >> { n708, n719 }; + assign n729 = 32'd8421376 >> { Pdata_56_, PD_19_, n709, n710, n706 }; + assign n730 = 32'd4008619758 >> { n702, n704, n718, n731, n710 }; + assign n731 = 32'd773140255 >> { n703, n714, n717, n732, n715 }; + assign n732 = 16'h9009 >> { Pdata_55_, PD_4_, PD_1_, Pdata_51_ }; + assign n526 = 8'h02 >> { n514, n521, n523 }; + assign Pdata_new_59_ = 64'hebbbbbbb41111111 >> { Pinreg_30_, n734, n751, n758, Pdata_27_, n544 }; + assign n734 = 8'h08 >> { n749, n1241, n1239 }; + assign n735 = 16'h9009 >> { Pdata_36_, PC_27_, Pdata_35_, PC_2_ }; + assign n736 = 16'h9009 >> { Pdata_40_, PC_9_, PC_14_, Pdata_37_ }; + assign n737 = 16'h1428 >> { Pdata_40_, Pdata_37_, PC_14_, PC_9_ }; + assign n738 = 16'h9009 >> { Pdata_39_, PC_20_, Pdata_38_, PC_5_ }; + assign n739 = 16'h4182 >> { Pdata_39_, Pdata_38_, PC_5_, PC_20_ }; + assign n740 = 16'h6006 >> { Pdata_36_, PC_27_, Pdata_35_, PC_2_ }; + assign n741 = 16'h1428 >> { Pdata_39_, Pdata_38_, PC_5_, PC_20_ }; + assign n742 = 16'h1428 >> { Pdata_36_, Pdata_35_, PC_2_, PC_27_ }; + assign n527 = 64'h2323232323232223 >> { n514, n510, n508, n528, n530, n513 }; + assign n743 = 16'h6006 >> { Pdata_40_, PC_9_, Pdata_37_, PC_14_ }; + assign n744 = 4'h6 >> { Pdata_37_, PC_14_ }; + assign n745 = 64'h0000099009900000 >> { Pdata_39_, PC_20_, Pdata_40_, PC_9_, Pdata_38_, PC_5_ }; + assign n746 = 4'h9 >> { Pdata_36_, PC_27_ }; + assign n747 = 4'h6 >> { Pdata_35_, PC_2_ }; + assign n748 = 16'h6006 >> { Pdata_39_, PC_20_, Pdata_38_, PC_5_ }; + assign n749 = 32'd32768 >> { n744, n747, n746, n750, n738 }; + assign n750 = 4'h6 >> { Pdata_40_, PC_9_ }; + assign n751 = 4'h8 >> { n752, n754 }; + assign n752 = 16'h2aaa >> { n740, n736, n739, n753 }; + assign n528 = 64'h0200022802280200 >> { Pdata_58_, PD_27_, n521, n529, n514, n510 }; + assign n753 = 64'h15553f7f3f7f3f7f >> { n748, n742, n736, n735, n741, n737 }; + assign n754 = 32'd570565154 >> { n757, n744, n735, n755, n756 }; + assign n755 = 16'h0080 >> { n744, n750, n742, n748 }; + assign n756 = 32'd2105540095 >> { n748, n739, n747, n746, n736 }; + assign n757 = 64'h0000066006600000 >> { Pdata_39_, PC_20_, Pdata_40_, PC_9_, Pdata_38_, PC_5_ }; + assign n758 = 64'h0002020202020202 >> { n748, n740, n737, n763, n764, n759 }; + assign n759 = 32'd65529 >> { n762, n760, n746, n747, n744 }; + assign n760 = 16'hdd0d >> { n743, n741, n750, n761 }; + assign n761 = 4'h9 >> { Pdata_39_, PC_20_ }; + assign n762 = 32'd2852653064 >> { n739, n740, n747, n738, n743 }; + assign n529 = 4'h6 >> { Pdata_56_, PD_20_ }; + assign n763 = 64'h8228820000280000 >> { n748, n741, n750, Pdata_37_, PC_14_, n735 }; + assign n764 = 32'd167905280 >> { n738, n739, n746, n747, n750 }; + assign Pdata_new_58_ = 16'heb41 >> { Pinreg_38_, n1291, Pdata_26_, n544 }; + assign n766 = 32'd271725106 >> { n768, n772, n767, n774, n777 }; + assign n767 = 64'hffffffffdffdf77f >> { n770, n768, Pdata_60_, PD_13_, n771, n769 }; + assign n768 = 4'h9 >> { Pdata_59_, PD_17_ }; + assign n769 = 4'h9 >> { Pdata_62_, PD_7_ }; + assign n770 = 4'h6 >> { Pdata_61_, PD_21_ }; + assign n771 = 4'h9 >> { Pdata_63_, PD_0_ }; + assign n772 = 16'h0080 >> { n771, n770, n773, n769 }; + assign n530 = 8'h28 >> { n515, n524, n523 }; + assign n773 = 4'h9 >> { Pdata_60_, PD_13_ }; + assign n774 = 8'h08 >> { n773, n775, n776 }; + assign n775 = 16'h6006 >> { Pdata_62_, PD_7_, Pdata_59_, PD_17_ }; + assign n776 = 64'h0990000000000990 >> { Pdata_63_, PD_0_, Pdata_61_, PD_21_, Pdata_32_, PD_3_ }; + assign n777 = 4'h9 >> { Pdata_32_, PD_3_ }; + assign n778 = 64'h9009000000009009 >> { Pdata_63_, PD_0_, Pdata_61_, PD_21_, Pdata_60_, PD_13_ }; + assign n779 = 16'h1428 >> { Pdata_61_, Pdata_60_, PD_13_, PD_21_ }; + assign n780 = 64'h0000066006600000 >> { Pdata_62_, PD_7_, PD_21_, Pdata_61_, PD_17_, Pdata_59_ }; + assign n781 = 64'h0000000000000002 >> { n782, n784, n786, n788, n789, n787 }; + assign n782 = 8'h08 >> { n777, n783, n780 }; + assign n531 = 16'h1428 >> { Pdata_60_, Pdata_57_, PD_10_, PD_24_ }; + assign n783 = 16'h4182 >> { Pdata_63_, Pdata_60_, PD_13_, PD_0_ }; + assign n784 = 8'h80 >> { n768, n778, n785 }; + assign n785 = 16'h9669 >> { Pdata_62_, Pdata_32_, PD_7_, PD_3_ }; + assign n786 = 64'h0000000000000002 >> { n768, n769, n770, n773, n771, n777 }; + assign n787 = 64'hffffffffffff7ffd >> { n777, n769, n768, n770, n771, n773 }; + assign n788 = 32'd128 >> { n769, n771, n777, n768, n779 }; + assign n789 = 8'h80 >> { n777, n775, n778 }; + assign n790 = 64'hfff7f7ff7fffff7f >> { n777, Pdata_62_, PD_7_, n770, n771, n773 }; + assign Pdata_new_57_ = 16'heb41 >> { Pinreg_46_, n792, Pdata_25_, n544 }; + assign n792 = 64'h0000000000008000 >> { n823, n825, n818, n822, n793, n808 }; + assign n532 = 8'h01 >> { n536, n538, n533 }; + assign n793 = 8'h08 >> { n794, n799, n806 }; + assign n794 = 16'h8000 >> { n795, n796, n797, n798 }; + assign n795 = 16'h9009 >> { Pdata_46_, PC_19_, PC_26_, Pdata_45_ }; + assign n796 = 4'h6 >> { Pdata_44_, PC_6_ }; + assign n797 = 4'h6 >> { Pdata_43_, PC_15_ }; + assign n798 = 16'h9009 >> { Pdata_47_, PC_12_, PC_1_, Pdata_48_ }; + assign n799 = 64'h05550ddd07770fff >> { n803, n805, n802, n801, n800, n804 }; + assign n800 = 4'h6 >> { Pdata_48_, PC_1_ }; + assign n801 = 64'h0000066006600000 >> { Pdata_47_, PC_12_, PC_1_, Pdata_48_, PC_15_, Pdata_43_ }; + assign n802 = 64'h9009000000009009 >> { Pdata_46_, PC_19_, Pdata_45_, PC_26_, Pdata_44_, PC_6_ }; + assign n506 = 64'h0015151515151515 >> { n518, n509, n517, n512, n516, n507 }; + assign n533 = 8'h08 >> { n535, n534, n517 }; + assign n803 = 64'h0000066006600000 >> { Pdata_46_, PC_19_, PC_26_, Pdata_45_, Pdata_44_, PC_6_ }; + assign n804 = 16'h4182 >> { Pdata_47_, Pdata_43_, PC_15_, PC_12_ }; + assign n805 = 64'h0990000000000990 >> { Pdata_46_, PC_19_, PC_26_, Pdata_45_, Pdata_44_, PC_6_ }; + assign n806 = 64'h6969ff6969ffffff >> { n802, n807, n797, n800, Pdata_47_, PC_12_ }; + assign n807 = 64'h0000099009900000 >> { Pdata_46_, PC_19_, PC_26_, Pdata_45_, Pdata_44_, PC_6_ }; + assign n808 = 32'd35791394 >> { n817, n801, n796, n809, n813 }; + assign n809 = 32'd8 >> { n811, n796, n797, n810, n812 }; + assign n810 = 4'h6 >> { Pdata_46_, PC_19_ }; + assign n811 = 4'h6 >> { Pdata_45_, PC_26_ }; + assign n812 = 16'h6006 >> { Pdata_47_, PC_12_, Pdata_48_, PC_1_ }; + assign n534 = 16'h9669 >> { Pdata_60_, Pdata_57_, PD_24_, PD_10_ }; + assign n813 = 64'h7777777777770777 >> { n797, n800, n814, n815, n805, n816 }; + assign n814 = 16'h6006 >> { Pdata_47_, PC_12_, Pdata_44_, PC_6_ }; + assign n815 = 16'h6006 >> { Pdata_46_, PC_19_, Pdata_45_, PC_26_ }; + assign n816 = 64'h0000600660060000 >> { Pdata_47_, PC_12_, Pdata_48_, PC_1_, PC_15_, Pdata_43_ }; + assign n817 = 16'h4182 >> { Pdata_46_, Pdata_45_, PC_26_, PC_19_ }; + assign n818 = 16'h0222 >> { n800, n819, n820, n821 }; + assign n819 = 16'h0080 >> { n797, n811, n810, n814 }; + assign n820 = 32'd8 >> { n811, n796, n797, n810, n798 }; + assign n821 = 32'd125269879 >> { n816, n817, n796, n803, n801 }; + assign n822 = 64'habbbffbbababefab >> { n906, n802, n800, n804, n807, n797 }; + assign n535 = 16'h6996 >> { Pdata_55_, Pdata_59_, PD_15_, PD_5_ }; + assign n823 = 4'h2 >> { n824, n797 }; + assign n824 = 64'hfefffffe46ffff46 >> { n810, Pdata_47_, PC_12_, n811, n796, n800 }; + assign n825 = 32'd2720145954 >> { n804, n796, n800, n826, n810 }; + assign n826 = 32'd1000046559 >> { n801, n797, n798, n811, n796 }; + assign Pdata_new_56_ = 8'he4 >> { Pinreg_54_, n1296, n544 }; + assign n828 = 16'h6006 >> { Pdata_51_, PD_18_, Pdata_50_, PD_8_ }; + assign n829 = 4'h2 >> { n830, n831 }; + assign n830 = 64'h0220000000000880 >> { n592, n589, Pdata_51_, PD_18_, n590, n597 }; + assign n831 = 32'd3758086135 >> { n592, n602, n606, n828, n595 }; + assign Pdata_new_55_ = 16'heb41 >> { Pdata_in_4_, Pdata_23_, n1225, n544 }; + assign n536 = 16'h0080 >> { n514, n513, n516, n518 }; + assign Pdata_new_54_ = 8'he4 >> { Pinreg_4_, n1248, n544 }; + assign n834 = 64'h0100010001010100 >> { n835, n688, n672, n836, n838, n687 }; + assign n835 = 32'd2147483648 >> { n673, n675, n676, n670, n671 }; + assign n836 = 16'h0002 >> { n675, n670, n671, n837 }; + assign n837 = 64'h0660000000000660 >> { Pdata_63_, PC_13_, Pdata_36_, PC_4_, PC_10_, Pdata_33_ }; + assign n838 = 32'd2 >> { n672, n673, n670, n671, n683 }; + assign n839 = 8'h08 >> { n671, n670, n685 }; + assign n840 = 32'd143130752 >> { n670, n672, n671, n673, n675 }; + assign Pdata_new_53_ = 16'heb41 >> { Pinreg_12_, n1298, Pdata_21_, n544 }; + assign n842 = 32'd2695406250 >> { n843, n526, n513, n510, n844 }; + assign n537 = 8'h80 >> { n511, n515, n523 }; + assign n843 = 8'h02 >> { n514, n521, n517 }; + assign n844 = 32'd1434419071 >> { n515, n524, n509, n531, n523 }; + assign Pdata_new_52_ = 64'hebbbbbbb41111111 >> { Pinreg_20_, n846, n851, n856, Pdata_20_, n544 }; + assign n846 = 4'h8 >> { n847, n849 }; + assign n847 = 64'hefefefef45efefef >> { n769, n768, n776, n848, n771, n773 }; + assign n848 = 4'h2 >> { n777, n780 }; + assign n849 = 32'd4143447807 >> { n775, n850, n770, n783, n777 }; + assign n850 = 16'h0002 >> { n777, n769, n771, n768 }; + assign n851 = 64'h8000800080000000 >> { n777, n854, n852, n766, n855, n781 }; + assign n852 = 32'd4283765845 >> { n785, n783, n768, n770, n853 }; + assign n538 = 16'h0008 >> { n510, n521, n509, n523 }; + assign n853 = 16'h8000 >> { n777, n770, n773, n775 }; + assign n854 = 64'hffff9f69ffffff6f >> { n771, n773, n768, n770, Pdata_62_, PD_7_ }; + assign n855 = 64'hf7f7f5f7fffffdf7 >> { n776, n771, n770, n773, n768, n769 }; + assign n856 = 16'hd9fb >> { n768, n857, n777, n778 }; + assign n857 = 32'd4294967255 >> { n769, n773, n768, n770, n771 }; + assign Pdata_new_51_ = 8'hb1 >> { Pinreg_28_, n859, n544 }; + assign n859 = 64'haaaaaaaa6aaaaaaa >> { n860, n793, n818, n1252, n862, Pdata_19_ }; + assign n860 = 4'h1 >> { n861, n811 }; + assign n861 = 64'h69d7ffffc37dd7ff >> { n797, n800, n810, Pdata_47_, PC_12_, n796 }; + assign n862 = 64'h0100010101010101 >> { n812, n805, n797, n819, n863, n864 }; + assign n539 = 16'h2022 >> { n508, n540, n541, n543 }; + assign n863 = 64'h8200822800008228 >> { n796, n800, n797, Pdata_47_, PC_12_, n815 }; + assign n864 = 8'ha8 >> { n803, n802, n816 }; + assign Pdata_new_50_ = 16'heb41 >> { Pinreg_36_, n1256, Pdata_18_, n544 }; + assign n866 = 4'h8 >> { n707, n719 }; + assign n867 = 8'h02 >> { n732, n715, n717 }; + assign n868 = 32'd89458551 >> { n722, n708, n714, n721, n719 }; + assign Pdata_new_49_ = 32'd3954917649 >> { Pinreg_44_, n870, n872, Pdata_17_, n544 }; + assign n870 = 32'd143165576 >> { n735, n750, n738, n1260, n754 }; + assign n871 = 8'h80 >> { n735, n743, n739 }; + assign n872 = 32'd128 >> { n749, n876, n873, n1239, n1241 }; + assign n540 = 16'h2777 >> { n518, n513, n531, n524 }; + assign n873 = 32'd17895697 >> { n739, n736, n735, n875, n874 }; + assign n874 = 64'h0232120202101200 >> { n747, n738, n750, n761, n746, n744 }; + assign n875 = 16'h0008 >> { n747, n750, n744, n748 }; + assign n876 = 32'd2155913856 >> { n736, n741, n738, n737, n740 }; + assign Pdata_new_48_ = 16'heb41 >> { Pinreg_52_, n1263, Pdata_16_, n544 }; + assign n878 = 8'h01 >> { n835, n838, n836 }; + assign n879 = 8'h08 >> { n676, n674, n685 }; + assign n880 = 64'hffff59956996eeee >> { n675, n676, Pdata_35_, PC_0_, n673, n670 }; + assign Pdata_new_47_ = 16'heb41 >> { Pdata_in_2_, Pdata_15_, n1230, n544 }; + assign Pdata_new_46_ = 16'heb41 >> { Pinreg_2_, n1266, Pdata_14_, n544 }; + assign n541 = 32'd2 >> { n513, n514, n510, n521, n523 }; + assign n883 = 64'hbeffebff967dd7ff >> { n768, n769, n770, Pdata_60_, PD_13_, n771 }; + assign n884 = 64'hf6fff9f6969ff99f >> { n770, n768, n769, n771, Pdata_60_, PD_13_ }; + assign Pdata_new_45_ = 16'heb41 >> { Pinreg_10_, n1269, Pdata_13_, n544 }; + assign n886 = 32'd538976290 >> { n589, n592, n586, n830, n831 }; + assign Pdata_new_44_ = 64'hebbbbbbb41111111 >> { Pinreg_18_, n734, n888, n890, Pdata_12_, n544 }; + assign n888 = 8'ha8 >> { n744, n889, n1260 }; + assign n889 = 32'd3148592815 >> { n741, n747, n738, n750, n746 }; + assign n890 = 32'd2290124936 >> { n744, n747, n893, n891, n752 }; + assign n891 = 16'h2aaa >> { n748, n735, n736, n892 }; + assign n892 = 32'd2004289399 >> { n735, n743, n738, n757, n742 }; + assign n542 = 8'h80 >> { n509, n515, n523 }; + assign n893 = 32'd1280204127 >> { n741, n739, n748, n746, n750 }; + assign Pdata_new_43_ = 16'heb41 >> { Pinreg_26_, n895, Pdata_11_, n544 }; + assign n895 = 64'h0000000080000000 >> { n901, n896, n897, n842, n898, n506 }; + assign n896 = 32'd65793 >> { n518, n522, n537, n538, n536 }; + assign n897 = 16'h1011 >> { n508, n540, n542, n541 }; + assign n898 = 32'd15860466 >> { n528, n529, n512, n899, n900 }; + assign n899 = 16'h0008 >> { n510, n521, n517, n524 }; + assign n900 = 64'h69c3ffeb69d7ffff >> { n508, n516, n513, Pdata_55_, PD_15_, n534 }; + assign n901 = 32'd1430274112 >> { n520, n508, n517, n531, n513 }; + assign Pdata_new_42_ = 16'heb41 >> { Pinreg_34_, n1303, Pdata_10_, n544 }; + assign n507 = 64'h2882200208800000 >> { n509, n511, Pdata_57_, PD_10_, n510, n508 }; + assign n543 = 16'h777d >> { n517, n516, n515, n524 }; + assign Pdata_new_41_ = 16'heb41 >> { Pinreg_42_, n1273, Pdata_9_, n544 }; + assign n904 = 4'h2 >> { n794, n799 }; + assign n905 = 64'h0000000028000028 >> { n810, n811, n797, Pdata_47_, PC_12_, n796 }; + assign n906 = 64'h7ff7ffffdffdf77f >> { n797, n810, Pdata_47_, PC_12_, n811, n796 }; + assign n907 = 64'h0000077707770777 >> { n805, n812, n804, n807, n797, n802 }; + assign Pdata_new_40_ = 8'he4 >> { Pinreg_50_, n909, n544 }; + assign n909 = 64'h5555555595555555 >> { n690, n1235, n677, n834, n910, Pdata_8_ }; + assign n910 = 16'h8c54 >> { n911, n839, n912, n671 }; + assign n911 = 64'h6debeb6defebebef >> { n672, Pdata_63_, PC_13_, n670, n673, n675 }; + assign n912 = 64'hffffed97ffffefbf >> { n675, n672, n673, n670, n671, n676 }; + assign n544 = 16'h8000 >> { Pcount_0_, Pcount_3_, Pcount_2_, Pcount_1_ }; + assign Pdata_new_39_ = 16'heb41 >> { Pdata_in_0_, Pdata_7_, n1289, n544 }; + assign Pdata_new_38_ = 32'd3954917649 >> { Pinreg_0_, n915, n1306, Pdata_6_, n544 }; + assign n915 = 4'h8 >> { n896, n842 }; + assign n916 = 64'h0020002022220020 >> { n521, n517, n510, n508, n514, n513 }; + assign n917 = 64'h0000000082002882 >> { n529, n514, n513, Pdata_58_, PD_27_, n531 }; + assign Pdata_new_37_ = 16'heb41 >> { Pinreg_8_, n1277, Pdata_5_, n544 }; + assign n919 = 64'h0054007e0055007f >> { n570, n563, n921, n920, n567, n559 }; + assign n920 = 4'h9 >> { n558, n549 }; + assign n921 = 16'h8008 >> { n549, n552, n553, n566 }; + assign Pdata_new_36_ = 64'hebbbbbbb41111111 >> { Pinreg_16_, n923, n924, n929, Pdata_4_, n544 }; + assign Poutreg_new_6_ = 32'd4158838208 >> { Poutreg_14_, Poutreg_6_, Pdata_63_, n544, Pcount_0_ }; + assign n923 = 4'h8 >> { n766, n1293 }; + assign n924 = 64'h2222202000220020 >> { n790, n928, n768, n777, n926, n925 }; + assign n925 = 8'h01 >> { n782, n784, n786 }; + assign n926 = 32'd2290649256 >> { n773, n771, n780, n927, n777 }; + assign n927 = 16'h0008 >> { n770, n773, n768, n769 }; + assign n928 = 32'd4294967229 >> { n770, n771, n768, n773, n769 }; + assign n929 = 8'h80 >> { n847, n849, n930 }; + assign n930 = 64'h4400541064207430 >> { n773, n853, n768, n931, n772, n848 }; + assign n931 = 32'd4294965117 >> { n773, n769, n770, n768, n771 }; + assign Pdata_new_35_ = 8'he4 >> { Pinreg_24_, n1279, n544 }; + assign Poutreg_new_5_ = 64'hd7ffd78282ff8282 >> { Poutreg_13_, Poutreg_5_, Pcount_0_, Pdata_23_, n1225, n544 }; + assign n933 = 64'h90f099ff96f06f9f >> { n715, n732, n703, n710, Pdata_56_, PD_19_ }; + assign n934 = 32'd2829625514 >> { n710, n702, n715, n732, n717 }; + assign Pdata_new_34_ = 16'heb41 >> { Pinreg_32_, n936, Pdata_2_, n544 }; + assign n936 = 32'd32768 >> { n939, n603, n829, n937, n585 }; + assign n937 = 64'h0222133313331333 >> { n602, n607, n592, n594, n938, n589 }; + assign n938 = 32'd2176 >> { n606, Pdata_51_, PD_18_, n601, n590 }; + assign n939 = 64'haeea0440ffff5555 >> { n941, n940, n589, n590, n607, n592 }; + assign n940 = 64'h0000000000828228 >> { n590, n587, n589, Pdata_51_, PD_18_, n588 }; + assign n941 = 64'hf696f6ffff96ffff >> { n602, n594, n589, n588, Pdata_48_, PD_23_ }; + assign Pdata_new_33_ = 32'd3954917649 >> { Pinreg_40_, n870, n1281, Pdata_1_, n544 }; + assign n547 = 32'd3605002239 >> { n554, n548, n555, n553, n551 }; + assign n943 = 32'd70128959 >> { n741, n738, n748, n736, n737 }; + assign n944 = 32'd2290649216 >> { n745, n757, n738, n744, n746 }; + assign n945 = 32'd1602180983 >> { n738, n761, n735, n742, n743 }; + assign Pdata_new_32_ = 16'heb41 >> { Pinreg_48_, n1284, Pdata_0_, n544 }; + assign n947 = 32'd3840208887 >> { n812, n800, n810, n796, n797 }; + assign n948 = 64'h8200822800008228 >> { n796, n800, n797, Pdata_47_, PC_12_, n817 }; + assign Pdata_new_31_ = 8'hd8 >> { Pdata_63_, Pdata_in_7_, n544 }; + assign Pdata_new_30_ = 8'hd8 >> { Pdata_62_, Pinreg_7_, n544 }; + assign Pdata_new_29_ = 8'hd8 >> { Pdata_61_, Pinreg_15_, n544 }; + assign Pdata_new_28_ = 8'hd8 >> { Pdata_60_, Pinreg_23_, n544 }; + assign n548 = 16'h0082 >> { n550, Pdata_42_, PC_3_, n549 }; + assign Pdata_new_27_ = 8'hd8 >> { Pdata_59_, Pinreg_31_, n544 }; + assign Pdata_new_26_ = 8'hd8 >> { Pdata_58_, Pinreg_39_, n544 }; + assign Pdata_new_25_ = 8'hd8 >> { Pdata_57_, Pinreg_47_, n544 }; + assign Pdata_new_24_ = 8'hd8 >> { Pdata_56_, Pinreg_55_, n544 }; + assign Pdata_new_23_ = 8'hd8 >> { Pdata_55_, Pdata_in_5_, n544 }; + assign Pdata_new_22_ = 8'hd8 >> { Pdata_54_, Pinreg_5_, n544 }; + assign Pdata_new_21_ = 8'hd8 >> { Pdata_53_, Pinreg_13_, n544 }; + assign Pdata_new_20_ = 8'hd8 >> { Pdata_52_, Pinreg_21_, n544 }; + assign Pdata_new_19_ = 8'hd8 >> { Pdata_51_, Pinreg_29_, n544 }; + assign Pdata_new_18_ = 8'hd8 >> { Pdata_50_, Pinreg_37_, n544 }; + assign n549 = 4'h9 >> { Pdata_43_, PC_25_ }; + assign Pdata_new_17_ = 8'hd8 >> { Pdata_49_, Pinreg_45_, n544 }; + assign Pdata_new_16_ = 8'hd8 >> { Pdata_48_, Pinreg_53_, n544 }; + assign Pdata_new_15_ = 8'hd8 >> { Pdata_47_, Pdata_in_3_, n544 }; + assign Pdata_new_14_ = 8'hd8 >> { Pdata_46_, Pinreg_3_, n544 }; + assign Pdata_new_13_ = 8'hd8 >> { Pdata_45_, Pinreg_11_, n544 }; + assign Pdata_new_12_ = 8'hd8 >> { Pdata_44_, Pinreg_19_, n544 }; + assign Pdata_new_11_ = 8'hd8 >> { Pdata_43_, Pinreg_27_, n544 }; + assign Pdata_new_10_ = 8'hd8 >> { Pdata_42_, Pinreg_35_, n544 }; + assign Pdata_new_9_ = 8'hd8 >> { Pdata_41_, Pinreg_43_, n544 }; + assign Pdata_new_8_ = 8'hd8 >> { Pdata_40_, Pinreg_51_, n544 }; + assign n550 = 4'h6 >> { Pdata_44_, PC_7_ }; + assign Pdata_new_7_ = 8'hd8 >> { Pdata_39_, Pdata_in_1_, n544 }; + assign Pdata_new_6_ = 8'hd8 >> { Pdata_38_, Pinreg_1_, n544 }; + assign Pdata_new_5_ = 8'hd8 >> { Pdata_37_, Pinreg_9_, n544 }; + assign Pdata_new_4_ = 8'hd8 >> { Pdata_36_, Pinreg_17_, n544 }; + assign Pdata_new_3_ = 8'hd8 >> { Pdata_35_, Pinreg_25_, n544 }; + assign Pdata_new_2_ = 8'hd8 >> { Pdata_34_, Pinreg_33_, n544 }; + assign Pdata_new_1_ = 8'hd8 >> { Pdata_33_, Pinreg_41_, n544 }; + assign Pdata_new_0_ = 8'hd8 >> { Pdata_32_, Pinreg_49_, n544 }; + assign Pcount_new_0_ = 4'h1 >> { Pcount_0_, Preset_0_ }; + assign Pcount_new_3_ = 32'd304226850 >> { Pcount_0_, Pcount_2_, Pcount_1_, Preset_0_, Pcount_3_ }; + assign n551 = 4'h6 >> { n549, n552 }; + assign Pcount_new_2_ = 16'h1222 >> { Pcount_0_, Pcount_1_, Preset_0_, Pcount_2_ }; + assign Pcount_new_1_ = 8'h06 >> { Preset_0_, Pcount_0_, Pcount_1_ }; + assign PD_new_27_ = 16'hf777 >> { PD_25_, n995, n986, n990 }; + assign n986 = 64'h0000077707770777 >> { n989, Pinreg_54_, Pdata_in_3_, n988, n987, PD_27_ }; + assign n987 = 32'd40 >> { Pload_key_0_, Preset_0_, Pencrypt_mode_0_, Pencrypt_0_, n544 }; + assign n988 = 16'h0008 >> { Pencrypt_0_, Preset_0_, Pload_key_0_, n544 }; + assign n989 = 16'h0080 >> { Preset_0_, Pencrypt_0_, Pload_key_0_, n544 }; + assign n990 = 64'h0000077707770777 >> { PD_0_, n994, n993, PD_1_, n991, PD_26_ }; + assign n991 = 64'h0002000200020202 >> { Pencrypt_0_, Pload_key_0_, n544, Pencrypt_mode_0_, Preset_0_, n992 }; + assign n992 = 16'h8881 >> { Pcount_0_, Pcount_3_, Pcount_2_, Pcount_1_ }; + assign n552 = 4'h9 >> { Pdata_39_, PC_22_ }; + assign n993 = 8'h02 >> { n992, Preset_0_, Pencrypt_mode_0_ }; + assign n994 = 64'h0008000808080008 >> { Pload_key_0_, Pencrypt_0_, n544, Preset_0_, n992, Pencrypt_mode_0_ }; + assign n995 = 8'h01 >> { n992, Pencrypt_mode_0_, Preset_0_ }; + assign PD_new_26_ = 16'hf777 >> { PD_27_, n994, n997, n998 }; + assign n997 = 64'h0000077707770777 >> { Pdata_in_3_, n989, Pinreg_3_, n988, n987, PD_26_ }; + assign n998 = 64'h0000077707770777 >> { n993, PD_0_, PD_25_, n991, n995, PD_24_ }; + assign PD_new_25_ = 64'hfffff777f777f777 >> { PD_26_, n994, n987, PD_25_, n1001, n1000 }; + assign n1000 = 16'h0777 >> { n989, Pinreg_3_, n988, Pinreg_11_ }; + assign n1001 = 64'h0000077707770777 >> { n993, PD_27_, PD_24_, n991, n995, PD_23_ }; + assign PD_new_24_ = 64'hfffff777f777f777 >> { n991, PD_23_, n987, PD_24_, n1004, n1003 }; + assign n508 = 16'h6006 >> { Pdata_58_, PD_27_, Pdata_56_, PD_20_ }; + assign n553 = 16'h6006 >> { Pdata_41_, PC_11_, Pdata_40_, PC_18_ }; + assign n1003 = 16'h0777 >> { n989, Pinreg_11_, n988, Pinreg_19_ }; + assign n1004 = 64'h0000077707770777 >> { PD_25_, n994, PD_26_, n993, n995, PD_22_ }; + assign PD_new_23_ = 16'hf777 >> { PD_22_, n991, n1006, n1007 }; + assign n1006 = 64'h0000077707770777 >> { n989, Pinreg_19_, Pdata_in_4_, n988, n987, PD_23_ }; + assign n1007 = 64'h0000077707770777 >> { PD_24_, n994, PD_25_, n993, n995, PD_21_ }; + assign PD_new_22_ = 16'hf777 >> { PD_23_, n994, n1009, n1010 }; + assign n1009 = 64'h0000077707770777 >> { Pdata_in_4_, n989, Pinreg_4_, n988, n987, PD_22_ }; + assign n1010 = 64'h0000077707770777 >> { n993, PD_24_, PD_21_, n991, n995, PD_20_ }; + assign PD_new_21_ = 16'hf777 >> { PD_19_, n995, n1012, n1013 }; + assign n1012 = 64'h0000077707770777 >> { Pinreg_4_, n989, Pinreg_12_, n988, n987, PD_21_ }; + assign n554 = 16'h1428 >> { Pdata_41_, Pdata_40_, PC_18_, PC_11_ }; + assign n1013 = 64'h0000077707770777 >> { PD_22_, n994, PD_23_, n993, n991, PD_20_ }; + assign PD_new_20_ = 16'hf777 >> { PD_19_, n991, n1015, n1016 }; + assign n1015 = 64'h0000077707770777 >> { Pinreg_12_, n989, Pinreg_20_, n988, n987, PD_20_ }; + assign n1016 = 64'h0000077707770777 >> { PD_21_, n994, PD_22_, n993, n995, PD_18_ }; + assign PD_new_19_ = 16'hf777 >> { PD_20_, n994, n1018, n1019 }; + assign n1018 = 64'h0000077707770777 >> { Pinreg_20_, n989, Pinreg_28_, n988, n987, PD_19_ }; + assign n1019 = 64'h0000077707770777 >> { n993, PD_21_, PD_18_, n991, n995, PD_17_ }; + assign PD_new_18_ = 16'hf777 >> { PD_16_, n995, n1021, n1022 }; + assign n1021 = 64'h0000077707770777 >> { Pinreg_28_, n989, Pinreg_36_, n988, n987, PD_18_ }; + assign n1022 = 64'h0000077707770777 >> { PD_19_, n994, PD_20_, n993, n991, PD_17_ }; + assign n555 = 16'h4182 >> { Pdata_44_, Pdata_42_, PC_3_, PC_7_ }; + assign PD_new_17_ = 16'hf777 >> { PD_19_, n993, n1024, n1025 }; + assign n1024 = 64'h0000077707770777 >> { Pinreg_36_, n989, Pinreg_44_, n988, n987, PD_17_ }; + assign n1025 = 64'h0000077707770777 >> { n994, PD_18_, PD_16_, n991, n995, PD_15_ }; + assign PD_new_16_ = 16'hf777 >> { PD_18_, n993, n1027, n1028 }; + assign n1027 = 64'h0000077707770777 >> { n989, Pinreg_44_, Pinreg_52_, n988, n987, PD_16_ }; + assign n1028 = 64'h0000077707770777 >> { n994, PD_17_, PD_15_, n991, n995, PD_14_ }; + assign PD_new_15_ = 64'hfffff777f777f777 >> { PD_15_, n987, n995, PD_13_, n1031, n1030 }; + assign n1030 = 16'h0777 >> { Pinreg_52_, n989, n988, Pdata_in_5_ }; + assign n1031 = 64'h0000077707770777 >> { PD_16_, n994, PD_17_, n993, n991, PD_14_ }; + assign PD_new_14_ = 16'hf777 >> { PD_16_, n993, n1033, n1034 }; + assign n556 = 16'h2aaa >> { n560, n551, n553, n557 }; + assign n1033 = 64'h0000077707770777 >> { Pdata_in_5_, n989, Pinreg_5_, n988, n987, PD_14_ }; + assign n1034 = 64'h0000077707770777 >> { n994, PD_15_, PD_13_, n991, n995, PD_12_ }; + assign PD_new_13_ = 16'hf777 >> { PD_15_, n993, n1036, n1037 }; + assign n1036 = 64'h0000077707770777 >> { Pinreg_5_, n989, Pinreg_13_, n988, n987, PD_13_ }; + assign n1037 = 64'h0000077707770777 >> { n994, PD_14_, PD_12_, n991, n995, PD_11_ }; + assign PD_new_12_ = 16'hf777 >> { PD_14_, n993, n1039, n1040 }; + assign n1039 = 64'h0000077707770777 >> { Pinreg_13_, n989, Pinreg_21_, n988, n987, PD_12_ }; + assign n1040 = 64'h0000077707770777 >> { n994, PD_13_, PD_11_, n991, n995, PD_10_ }; + assign PD_new_11_ = 16'hf777 >> { PD_13_, n993, n1042, n1043 }; + assign n1042 = 64'h0000077707770777 >> { Pinreg_21_, n989, Pinreg_29_, n988, n987, PD_11_ }; + assign n557 = 64'hfdfffffdff7f7fff >> { n552, Pdata_40_, PC_18_, n558, n549, n559 }; + assign n1043 = 64'h0000077707770777 >> { n994, PD_12_, PD_10_, n991, n995, PD_9_ }; + assign PD_new_10_ = 16'hf777 >> { PD_11_, n994, n1045, n1046 }; + assign n1045 = 64'h0000077707770777 >> { Pinreg_29_, n989, Pinreg_37_, n988, n987, PD_10_ }; + assign n1046 = 64'h0000077707770777 >> { n993, PD_12_, PD_9_, n991, n995, PD_8_ }; + assign PD_new_9_ = 16'hf777 >> { PD_7_, n995, n1048, n1049 }; + assign n1048 = 64'h0000077707770777 >> { Pinreg_37_, n989, Pinreg_45_, n988, n987, PD_9_ }; + assign n1049 = 64'h0000077707770777 >> { PD_10_, n994, PD_11_, n993, n991, PD_8_ }; + assign PD_new_8_ = 16'hf777 >> { PD_9_, n994, n1051, n1052 }; + assign n1051 = 64'h0000077707770777 >> { n989, Pinreg_45_, Pinreg_53_, n988, n987, PD_8_ }; + assign n1052 = 64'h0000077707770777 >> { n993, PD_10_, PD_7_, n991, n995, PD_6_ }; + assign n558 = 4'h6 >> { Pdata_41_, PC_11_ }; + assign PD_new_7_ = 16'hf777 >> { PD_8_, n994, n1054, n1055 }; + assign n1054 = 64'h0000077707770777 >> { n989, Pinreg_53_, Pdata_in_6_, n988, n987, PD_7_ }; + assign n1055 = 64'h0000077707770777 >> { n993, PD_9_, PD_6_, n991, n995, PD_5_ }; + assign PD_new_6_ = 64'hfffff777f777f777 >> { PD_7_, n994, n987, PD_6_, n1058, n1057 }; + assign n1057 = 16'h0777 >> { n989, Pdata_in_6_, n988, Pinreg_6_ }; + assign n1058 = 64'h0000077707770777 >> { n993, PD_8_, PD_5_, n991, n995, PD_4_ }; + assign PD_new_5_ = 16'hf777 >> { PD_7_, n993, n1060, n1061 }; + assign n1060 = 64'h0000077707770777 >> { Pinreg_6_, n989, Pinreg_14_, n988, n987, PD_5_ }; + assign n1061 = 64'h0000077707770777 >> { n994, PD_6_, PD_4_, n991, n995, PD_3_ }; + assign PD_new_4_ = 16'hf777 >> { PD_6_, n993, n1063, n1064 }; + assign n559 = 16'h6006 >> { Pdata_44_, PC_7_, Pdata_42_, PC_3_ }; + assign n1063 = 64'h0000077707770777 >> { Pinreg_14_, n989, Pinreg_22_, n988, n987, PD_4_ }; + assign n1064 = 64'h0000077707770777 >> { n994, PD_5_, PD_3_, n991, n995, PD_2_ }; + assign PD_new_3_ = 16'hf777 >> { PD_1_, n995, n1066, n1067 }; + assign n1066 = 64'h0000077707770777 >> { Pinreg_22_, n989, Pinreg_30_, n988, n987, PD_3_ }; + assign n1067 = 64'h0000077707770777 >> { PD_4_, n994, PD_5_, n993, n991, PD_2_ }; + assign PD_new_2_ = 16'hf777 >> { PD_1_, n991, n1069, n1070 }; + assign n1069 = 64'h0000077707770777 >> { Pinreg_30_, n989, Pinreg_38_, n988, n987, PD_2_ }; + assign n1070 = 64'h0000077707770777 >> { n994, PD_3_, n993, PD_4_, n995, PD_0_ }; + assign PD_new_1_ = 64'hfffff777f777f777 >> { n987, PD_1_, n995, PD_27_, n1073, n1072 }; + assign n1072 = 16'h0777 >> { n989, Pinreg_38_, n988, Pinreg_46_ }; + assign n560 = 16'h1428 >> { Pdata_44_, Pdata_42_, PC_3_, PC_7_ }; + assign n1073 = 64'h0000077707770777 >> { n994, PD_2_, n993, PD_3_, n991, PD_0_ }; + assign PD_new_0_ = 16'hf777 >> { PD_2_, n993, n1075, n1076 }; + assign n1075 = 64'h0000077707770777 >> { n989, Pinreg_46_, Pinreg_54_, n988, n987, PD_0_ }; + assign n1076 = 64'h0000077707770777 >> { n994, PD_1_, PD_27_, n991, n995, PD_26_ }; + assign PC_new_27_ = 16'hf777 >> { PC_25_, n995, n1078, n1079 }; + assign n1078 = 64'h0000077707770777 >> { n989, Pinreg_48_, Pinreg_27_, n988, n987, PC_27_ }; + assign n1079 = 64'h0000077707770777 >> { PC_0_, n994, n993, PC_1_, n991, PC_26_ }; + assign PC_new_26_ = 16'hf777 >> { PC_24_, n995, n1081, n1082 }; + assign n1081 = 64'h0000077707770777 >> { Pinreg_27_, n989, Pinreg_35_, n988, n987, PC_26_ }; + assign n1082 = 64'h0000077707770777 >> { n994, PC_27_, PC_0_, n993, n991, PC_25_ }; + assign n561 = 4'h9 >> { Pdata_40_, PC_18_ }; + assign PC_new_25_ = 16'hf777 >> { PC_27_, n993, n1084, n1085 }; + assign n1084 = 64'h0000077707770777 >> { Pinreg_35_, n989, Pinreg_43_, n988, n987, PC_25_ }; + assign n1085 = 64'h0000077707770777 >> { n994, PC_26_, PC_24_, n991, n995, PC_23_ }; + assign PC_new_24_ = 16'hf777 >> { PC_26_, n993, n1087, n1088 }; + assign n1087 = 64'h0000077707770777 >> { n989, Pinreg_43_, Pinreg_51_, n988, n987, PC_24_ }; + assign n1088 = 64'h0000077707770777 >> { n994, PC_25_, PC_23_, n991, n995, PC_22_ }; + assign PC_new_23_ = 16'hf777 >> { PC_22_, n991, n1090, n1091 }; + assign n1090 = 64'h0000077707770777 >> { n989, Pinreg_51_, Pdata_in_2_, n988, n987, PC_23_ }; + assign n1091 = 64'h0000077707770777 >> { PC_24_, n994, PC_25_, n993, n995, PC_21_ }; + assign PC_new_22_ = 16'hf777 >> { PC_23_, n994, n1093, n1094 }; + assign n562 = 64'h0000099009900000 >> { Pdata_39_, PC_22_, PC_25_, Pdata_43_, Pdata_42_, PC_3_ }; + assign n1093 = 64'h0000077707770777 >> { Pdata_in_2_, n989, Pinreg_2_, n988, n987, PC_22_ }; + assign n1094 = 64'h0000077707770777 >> { n993, PC_24_, PC_21_, n991, n995, PC_20_ }; + assign PC_new_21_ = 64'hfffff777f777f777 >> { PC_22_, n994, n987, PC_21_, n1097, n1096 }; + assign n1096 = 16'h0777 >> { n989, Pinreg_2_, n988, Pinreg_10_ }; + assign n1097 = 64'h0000077707770777 >> { n993, PC_23_, PC_20_, n991, n995, PC_19_ }; + assign PC_new_20_ = 16'hf777 >> { PC_18_, n995, n1099, n1100 }; + assign n1099 = 64'h0000077707770777 >> { Pinreg_10_, n989, Pinreg_18_, n988, n987, PC_20_ }; + assign n1100 = 64'h0000077707770777 >> { PC_21_, n994, PC_22_, n993, n991, PC_19_ }; + assign PC_new_19_ = 16'hf777 >> { PC_20_, n994, n1102, n1103 }; + assign n1102 = 64'h0000077707770777 >> { Pinreg_18_, n989, Pinreg_26_, n988, n987, PC_19_ }; + assign n509 = 16'h1428 >> { Pdata_55_, Pdata_59_, PD_5_, PD_15_ }; + assign n563 = 8'h08 >> { n558, n549, n564 }; + assign n1103 = 64'h0000077707770777 >> { n993, PC_21_, PC_18_, n991, n995, PC_17_ }; + assign PC_new_18_ = 16'hf777 >> { PC_16_, n995, n1105, n1106 }; + assign n1105 = 64'h0000077707770777 >> { Pinreg_26_, n989, Pinreg_34_, n988, n987, PC_18_ }; + assign n1106 = 64'h0000077707770777 >> { PC_19_, n994, PC_20_, n993, n991, PC_17_ }; + assign PC_new_17_ = 64'hfffff777f777f777 >> { PC_19_, n993, n987, PC_17_, n1109, n1108 }; + assign n1108 = 16'h0777 >> { n989, Pinreg_34_, n988, Pinreg_42_ }; + assign n1109 = 64'h0000077707770777 >> { n994, PC_18_, PC_16_, n991, n995, PC_15_ }; + assign PC_new_16_ = 16'hf777 >> { PC_14_, n995, n1111, n1112 }; + assign n1111 = 64'h0000077707770777 >> { n989, Pinreg_42_, Pinreg_50_, n988, n987, PC_16_ }; + assign n1112 = 64'h0000077707770777 >> { PC_17_, n994, PC_18_, n993, n991, PC_15_ }; + assign n564 = 16'h9009 >> { Pdata_39_, PC_22_, Pdata_40_, PC_18_ }; + assign PC_new_15_ = 16'hf777 >> { PC_16_, n994, n1114, n1115 }; + assign n1114 = 64'h0000077707770777 >> { n989, Pinreg_50_, Pdata_in_1_, n988, n987, PC_15_ }; + assign n1115 = 64'h0000077707770777 >> { n993, PC_17_, PC_14_, n991, n995, PC_13_ }; + assign PC_new_14_ = 16'hf777 >> { PC_13_, n991, n1117, n1118 }; + assign n1117 = 64'h0000077707770777 >> { Pdata_in_1_, n989, Pinreg_1_, n988, n987, PC_14_ }; + assign n1118 = 64'h0000077707770777 >> { PC_15_, n994, PC_16_, n993, n995, PC_12_ }; + assign PC_new_13_ = 16'hf777 >> { PC_15_, n993, n1120, n1121 }; + assign n1120 = 64'h0000077707770777 >> { Pinreg_1_, n989, Pinreg_9_, n988, n987, PC_13_ }; + assign n1121 = 64'h0000077707770777 >> { n994, PC_14_, PC_12_, n991, n995, PC_11_ }; + assign PC_new_12_ = 16'hf777 >> { PC_14_, n993, n1123, n1124 }; + assign n565 = 16'h0080 >> { n558, n549, n566, n567 }; + assign n1123 = 64'h0000077707770777 >> { Pinreg_9_, n989, Pinreg_17_, n988, n987, PC_12_ }; + assign n1124 = 64'h0000077707770777 >> { n994, PC_13_, PC_11_, n991, n995, PC_10_ }; + assign PC_new_11_ = 64'hfffff777f777f777 >> { PC_11_, n987, n995, PC_9_, n1127, n1126 }; + assign n1126 = 16'h0777 >> { n989, Pinreg_17_, n988, Pinreg_25_ }; + assign n1127 = 64'h0000077707770777 >> { PC_12_, n994, PC_13_, n993, n991, PC_10_ }; + assign PC_new_10_ = 16'hf777 >> { PC_11_, n994, n1129, n1130 }; + assign n1129 = 64'h0000077707770777 >> { Pinreg_25_, n989, Pinreg_33_, n988, n987, PC_10_ }; + assign n1130 = 64'h0000077707770777 >> { n993, PC_12_, PC_9_, n991, n995, PC_8_ }; + assign PC_new_9_ = 16'hf777 >> { PC_7_, n995, n1132, n1133 }; + assign n1132 = 64'h0000077707770777 >> { Pinreg_33_, n989, Pinreg_41_, n988, n987, PC_9_ }; + assign n566 = 16'h9669 >> { Pdata_44_, Pdata_42_, PC_7_, PC_3_ }; + assign n1133 = 64'h0000077707770777 >> { PC_10_, n994, PC_11_, n993, n991, PC_8_ }; + assign PC_new_8_ = 16'hf777 >> { PC_10_, n993, n1135, n1136 }; + assign n1135 = 64'h0000077707770777 >> { n989, Pinreg_41_, Pinreg_49_, n988, n987, PC_8_ }; + assign n1136 = 64'h0000077707770777 >> { n994, PC_9_, PC_7_, n991, n995, PC_6_ }; + assign PC_new_7_ = 16'hf777 >> { PC_8_, n994, n1138, n1139 }; + assign n1138 = 64'h0000077707770777 >> { n989, Pinreg_49_, Pdata_in_0_, n988, n987, PC_7_ }; + assign n1139 = 64'h0000077707770777 >> { n993, PC_9_, PC_6_, n991, n995, PC_5_ }; + assign PC_new_6_ = 16'hf777 >> { PC_7_, n994, n1141, n1142 }; + assign n1141 = 64'h0000077707770777 >> { Pdata_in_0_, n989, Pinreg_0_, n988, n987, PC_6_ }; + assign n1142 = 64'h0000077707770777 >> { n993, PC_8_, PC_5_, n991, n995, PC_4_ }; + assign n567 = 16'h4182 >> { Pdata_39_, Pdata_40_, PC_18_, PC_22_ }; + assign PC_new_5_ = 16'hf777 >> { PC_3_, n995, n1144, n1145 }; + assign n1144 = 64'h0000077707770777 >> { Pinreg_0_, n989, Pinreg_8_, n988, n987, PC_5_ }; + assign n1145 = 64'h0000077707770777 >> { PC_6_, n994, PC_7_, n993, n991, PC_4_ }; + assign PC_new_4_ = 16'hf777 >> { PC_5_, n994, n1147, n1148 }; + assign n1147 = 64'h0000077707770777 >> { Pinreg_8_, n989, Pinreg_16_, n988, n987, PC_4_ }; + assign n1148 = 64'h0000077707770777 >> { n993, PC_6_, PC_3_, n991, n995, PC_2_ }; + assign PC_new_3_ = 16'hf777 >> { PC_1_, n995, n1150, n1151 }; + assign n1150 = 64'h0000077707770777 >> { Pinreg_16_, n989, Pinreg_24_, n988, n987, PC_3_ }; + assign n1151 = 64'h0000077707770777 >> { PC_4_, n994, PC_5_, n993, n991, PC_2_ }; + assign PC_new_2_ = 16'hf777 >> { PC_4_, n993, n1153, n1154 }; + assign n568 = 8'h80 >> { n552, n553, n569 }; + assign n1153 = 64'h0000077707770777 >> { Pinreg_24_, n989, Pinreg_32_, n988, n987, PC_2_ }; + assign n1154 = 64'h0000077707770777 >> { n994, PC_3_, n991, PC_1_, n995, PC_0_ }; + assign PC_new_1_ = 64'hfffff777f777f777 >> { n993, PC_3_, n987, PC_1_, n1157, n1156 }; + assign n1156 = 16'h0777 >> { n989, Pinreg_32_, n988, Pinreg_40_ }; + assign n1157 = 64'h0000077707770777 >> { n994, PC_2_, n991, PC_0_, n995, PC_27_ }; + assign PC_new_0_ = 16'hf777 >> { PC_2_, n993, n1159, n1160 }; + assign n1159 = 64'h0000077707770777 >> { n989, Pinreg_40_, Pinreg_48_, n988, n987, PC_0_ }; + assign n1160 = 64'h0000077707770777 >> { n994, PC_1_, PC_27_, n991, n995, PC_26_ }; + assign Poutreg_new_63_ = 16'h88f8 >> { Pcount_0_, Poutreg_63_, n1296, n544 }; + assign Poutreg_new_62_ = 16'h88f8 >> { Pcount_0_, Poutreg_62_, n544, Pdata_56_ }; + assign n569 = 64'h0990000000000990 >> { Pdata_44_, PC_7_, PC_25_, Pdata_43_, Pdata_42_, PC_3_ }; + assign Poutreg_new_61_ = 32'd2189623170 >> { Pcount_0_, Poutreg_61_, n1263, Pdata_16_, n544 }; + assign Poutreg_new_60_ = 16'h88f8 >> { Pcount_0_, Poutreg_60_, n544, Pdata_48_ }; + assign Poutreg_new_59_ = 16'h88f8 >> { Pcount_0_, Poutreg_59_, n909, n544 }; + assign Poutreg_new_58_ = 16'h88f8 >> { Pcount_0_, Poutreg_58_, n544, Pdata_40_ }; + assign Poutreg_new_57_ = 32'd2189623170 >> { Pcount_0_, Poutreg_57_, n1284, Pdata_0_, n544 }; + assign Poutreg_new_56_ = 16'h88f8 >> { Pcount_0_, Poutreg_56_, n544, Pdata_32_ }; + assign Poutreg_new_55_ = 64'hd7ffd78282ff8282 >> { Poutreg_63_, Poutreg_55_, Pcount_0_, Pdata_25_, n792, n544 }; + assign Poutreg_new_54_ = 32'd4158838208 >> { Poutreg_62_, Poutreg_54_, Pdata_57_, n544, Pcount_0_ }; + assign Poutreg_new_53_ = 32'd2183331839 >> { n1172, n870, n872, Pdata_17_, n544 }; + assign n1172 = 16'hbb1b >> { n544, Poutreg_61_, Poutreg_53_, Pcount_0_ }; + assign n570 = 32'd2176 >> { n549, Pdata_42_, PC_3_, n571, n558 }; + assign Poutreg_new_52_ = 32'd4158838208 >> { Poutreg_60_, Poutreg_52_, Pdata_49_, n544, Pcount_0_ }; + assign Poutreg_new_51_ = 64'hd7ffd78282ff8282 >> { Poutreg_59_, Poutreg_51_, Pcount_0_, Pdata_9_, n1273, n544 }; + assign Poutreg_new_50_ = 32'd4158838208 >> { Poutreg_58_, Poutreg_50_, Pdata_41_, n544, Pcount_0_ }; + assign Poutreg_new_49_ = 32'd2183331839 >> { n1177, n870, n1281, Pdata_1_, n544 }; + assign n1177 = 16'hbb1b >> { n544, Poutreg_57_, Poutreg_49_, Pcount_0_ }; + assign Poutreg_new_48_ = 32'd4158838208 >> { Poutreg_56_, Poutreg_48_, Pdata_33_, n544, Pcount_0_ }; + assign Poutreg_new_47_ = 64'hd7ffd78282ff8282 >> { Poutreg_55_, Poutreg_47_, Pcount_0_, Pdata_26_, n1291, n544 }; + assign Poutreg_new_46_ = 32'd4158838208 >> { Poutreg_54_, Poutreg_46_, Pdata_58_, n544, Pcount_0_ }; + assign Poutreg_new_45_ = 64'hd7ffd78282ff8282 >> { Poutreg_53_, Poutreg_45_, Pcount_0_, Pdata_18_, n1256, n544 }; + assign Poutreg_new_44_ = 32'd4158838208 >> { Poutreg_52_, Poutreg_44_, Pdata_50_, n544, Pcount_0_ }; + assign n571 = 16'h6006 >> { Pdata_39_, PC_22_, Pdata_40_, PC_18_ }; + assign Poutreg_new_43_ = 64'hd7ffd78282ff8282 >> { Poutreg_51_, Poutreg_43_, Pcount_0_, Pdata_10_, n1303, n544 }; + assign Poutreg_new_42_ = 32'd4158838208 >> { Poutreg_50_, Poutreg_42_, Pdata_42_, n544, Pcount_0_ }; + assign Poutreg_new_41_ = 64'hd7ffd78282ff8282 >> { Poutreg_49_, Poutreg_41_, Pcount_0_, Pdata_2_, n936, n544 }; + assign Poutreg_new_40_ = 32'd4158838208 >> { Poutreg_48_, Poutreg_40_, Pdata_34_, n544, Pcount_0_ }; + assign Poutreg_new_39_ = 64'h82222222ffffffff >> { n1188, n734, n751, n758, Pdata_27_, n544 }; + assign n1188 = 16'hbb1b >> { n544, Poutreg_47_, Poutreg_39_, Pcount_0_ }; + assign Poutreg_new_38_ = 32'd4158838208 >> { Poutreg_46_, Poutreg_38_, Pdata_59_, n544, Pcount_0_ }; + assign Poutreg_new_37_ = 32'd2133744908 >> { Poutreg_45_, Poutreg_37_, n859, n544, Pcount_0_ }; + assign Poutreg_new_36_ = 32'd4158838208 >> { Poutreg_44_, Poutreg_36_, Pdata_51_, n544, Pcount_0_ }; + assign Poutreg_new_35_ = 64'hd7ffd78282ff8282 >> { Poutreg_43_, Poutreg_35_, Pcount_0_, Pdata_11_, n895, n544 }; + assign n572 = 64'h0000000080080880 >> { n552, n549, Pdata_40_, PC_18_, n558, n566 }; + assign Poutreg_new_34_ = 32'd4158838208 >> { Poutreg_42_, Poutreg_34_, Pdata_43_, n544, Pcount_0_ }; + assign Poutreg_new_33_ = 32'd4158838208 >> { Poutreg_41_, Poutreg_33_, n1279, n544, Pcount_0_ }; + assign Poutreg_new_32_ = 32'd4158838208 >> { Poutreg_40_, Poutreg_32_, Pdata_35_, n544, Pcount_0_ }; + assign Poutreg_new_31_ = 64'hd7ffd78282ff8282 >> { Poutreg_39_, Poutreg_31_, Pcount_0_, Pdata_28_, n699, n544 }; + assign Poutreg_new_30_ = 32'd4158838208 >> { Poutreg_38_, Poutreg_30_, Pdata_60_, n544, Pcount_0_ }; + assign Poutreg_new_29_ = 64'h82222222ffffffff >> { n1199, n846, n851, n856, Pdata_20_, n544 }; + assign n1199 = 16'hbb1b >> { n544, Poutreg_37_, Poutreg_29_, Pcount_0_ }; + assign Poutreg_new_28_ = 32'd4158838208 >> { Poutreg_36_, Poutreg_28_, Pdata_52_, n544, Pcount_0_ }; + assign Poutreg_new_27_ = 64'h82222222ffffffff >> { n1202, n734, n888, n890, Pdata_12_, n544 }; + assign n1202 = 16'hbb1b >> { n544, Poutreg_35_, Poutreg_27_, Pcount_0_ }; + assign n510 = 4'h6 >> { Pdata_60_, PD_24_ }; + assign n573 = 64'h0990000000000990 >> { Pdata_39_, PC_22_, PC_25_, Pdata_43_, Pdata_40_, PC_18_ }; + assign Poutreg_new_26_ = 32'd4158838208 >> { Poutreg_34_, Poutreg_26_, Pdata_44_, n544, Pcount_0_ }; + assign Poutreg_new_25_ = 64'h82222222ffffffff >> { n1205, n923, n924, n929, Pdata_4_, n544 }; + assign n1205 = 16'hbb1b >> { n544, Poutreg_33_, Poutreg_25_, Pcount_0_ }; + assign Poutreg_new_24_ = 32'd4158838208 >> { Poutreg_32_, Poutreg_24_, Pdata_36_, n544, Pcount_0_ }; + assign Poutreg_new_23_ = 64'hd7ffd78282ff8282 >> { Poutreg_31_, Poutreg_23_, Pcount_0_, Pdata_29_, n692, n544 }; + assign Poutreg_new_22_ = 32'd4158838208 >> { Poutreg_30_, Poutreg_22_, Pdata_61_, n544, Pcount_0_ }; + assign Poutreg_new_21_ = 64'hd7ffd78282ff8282 >> { Poutreg_29_, Poutreg_21_, Pcount_0_, Pdata_21_, n1298, n544 }; + assign Poutreg_new_20_ = 32'd4158838208 >> { Poutreg_28_, Poutreg_20_, Pdata_53_, n544, Pcount_0_ }; + assign Poutreg_new_19_ = 64'hd7ffd78282ff8282 >> { Poutreg_27_, Poutreg_19_, Pcount_0_, Pdata_13_, n1269, n544 }; + assign Poutreg_new_18_ = 32'd4158838208 >> { Poutreg_26_, Poutreg_18_, Pdata_45_, n544, Pcount_0_ }; + assign Poutreg_new_4_ = 32'd4158838208 >> { Poutreg_12_, Poutreg_4_, Pdata_55_, n544, Pcount_0_ }; + assign Poutreg_new_17_ = 64'hd7ffd78282ff8282 >> { Poutreg_25_, Poutreg_17_, Pcount_0_, Pdata_5_, n1277, n544 }; + assign Poutreg_new_16_ = 32'd4158838208 >> { Poutreg_24_, Poutreg_16_, Pdata_37_, n544, Pcount_0_ }; + assign Poutreg_new_15_ = 64'hd7ffd78282ff8282 >> { Poutreg_23_, Poutreg_15_, Pcount_0_, Pdata_30_, n668, n544 }; + assign Poutreg_new_14_ = 32'd4158838208 >> { Poutreg_22_, Poutreg_14_, Pdata_62_, n544, Pcount_0_ }; + assign Poutreg_new_13_ = 32'd4158838208 >> { Poutreg_21_, Poutreg_13_, n1248, n544, Pcount_0_ }; + assign Poutreg_new_12_ = 32'd4158838208 >> { Poutreg_20_, Poutreg_12_, Pdata_54_, n544, Pcount_0_ }; + assign Poutreg_new_11_ = 64'hd7ffd78282ff8282 >> { Poutreg_19_, Poutreg_11_, Pcount_0_, Pdata_14_, n1266, n544 }; + assign Poutreg_new_10_ = 32'd4158838208 >> { Poutreg_18_, Poutreg_10_, Pdata_46_, n544, Pcount_0_ }; + assign Poutreg_new_9_ = 32'd2183331839 >> { n1222, n915, n1306, Pdata_6_, n544 }; + assign n1222 = 16'hbb1b >> { n544, Poutreg_17_, Poutreg_9_, Pcount_0_ }; + assign Poutreg_new_3_ = 64'hd7ffd78282ff8282 >> { Poutreg_11_, Poutreg_3_, Pcount_0_, Pdata_15_, n1230, n544 }; + assign Poutreg_new_8_ = 32'd4158838208 >> { Poutreg_16_, Poutreg_8_, Pdata_38_, n544, Pcount_0_ }; + assign n1224 = 64'h010123ab23ab23ab >> { n561, n562, n555, n570, n563, n550 }; + assign n1225 = 64'h0000000080000000 >> { n565, n1224, n556, n1286, n1227, n547 }; + assign n1226 = 32'd1793731242 >> { n560, n559, n549, n552, n561 }; + assign n1227 = 32'd3445450615 >> { n1226, n550, n562, n561, n558 }; + assign n1228 = 64'h2aa27ff77ff72aa2 >> { Pdata_42_, PC_3_, n549, n566, n564, n558 }; + assign n1229 = 64'h090900090b0b000b >> { n571, n582, n581, n580, n558, n1228 }; + assign n1230 = 64'h0000000080000000 >> { n579, n556, n576, n1232, n1229, n1227 }; + assign n1231 = 64'hffff800880088008 >> { n554, n559, Pdata_40_, PC_18_, n558, n560 }; + assign n1232 = 64'haa8282aaaaaaaaaa >> { n1231, Pdata_39_, PC_22_, PC_25_, Pdata_43_, n578 }; + assign n576 = 32'd65793 >> { n555, n563, n568, n577, n565 }; + assign n1233 = 32'd2150115456 >> { Pdata_51_, PD_18_, n587, n590, n588 }; + assign n1234 = 32'd3149904317 >> { n607, n602, n594, n595, n592 }; + assign n1235 = 64'hfffffffffffbefd7 >> { n675, n670, n672, n671, n676, n673 }; + assign n1236 = 64'h0848480a00404002 >> { n689, n672, n676, n670, n671, n673 }; + assign n1237 = 4'h7 >> { n1236, n675 }; + assign n1238 = 64'h15553f7f3f7f3f7f >> { n739, n740, n736, n738, n735, n737 }; + assign n1239 = 16'h2aaa >> { n741, n742, n743, n1238 }; + assign n1240 = 64'h66f6009000900090 >> { n743, n748, n744, n745, Pdata_35_, PC_2_ }; + assign n1241 = 64'h66660666ffff9fff >> { n1240, n747, n736, n741, Pdata_36_, PC_27_ }; + assign n1242 = 64'h2222222272222222 >> { n771, n770, n775, n777, n769, n768 }; + assign n577 = 64'h0000000000008008 >> { n552, n550, Pdata_42_, PC_3_, n549, n554 }; + assign n1243 = 64'h88882000dcccfccc >> { n776, n1242, n790, n928, n768, n773 }; + assign n1244 = 64'hfefffefffefff6f7 >> { n770, n773, n778, n769, n777, n768 }; + assign n1245 = 64'haa41aa7daa7daa7d >> { n597, n828, n592, Pdata_47_, PD_12_, n595 }; + assign n1246 = 64'hceeece6edfffdf6f >> { n679, n670, n676, n685, n673, n671 }; + assign n1247 = 64'h1010303210153037 >> { n674, n839, n684, n672, n840, n676 }; + assign n1248 = 64'h9555555555555555 >> { n1246, n1247, n834, n1235, n1237, Pdata_22_ }; + assign n1249 = 64'h1515373f373f373f >> { n518, n524, n511, n522, n520, n516 }; + assign n1250 = 64'h5151504051115000 >> { n529, n523, n508, n513, n514, n521 }; + assign n1251 = 64'h557f7f7f7f7f7f7f >> { n800, n795, n804, n815, n801, n796 }; + assign n1252 = 32'd176827050 >> { n802, n807, n798, n797, n1251 }; + assign n578 = 64'hbfbfbfbfaabfbfbf >> { n549, n571, n559, n573, n555, n558 }; + assign n1253 = 16'h8228 >> { Pdata_56_, PD_19_, n703, n715 }; + assign n1254 = 64'h7070757770f07dff >> { n704, n1253, n732, n706, n718, n710 }; + assign n1255 = 16'h1bbb >> { n714, n707, n867, n710 }; + assign n1256 = 64'h8000000000000000 >> { n1254, n1255, n720, n724, n1258, n868 }; + assign n1257 = 64'hffff088008800880 >> { n714, n723, Pdata_56_, PD_19_, n722, n706 }; + assign n1258 = 64'h0000000100010001 >> { n710, n1257, n727, n728, n729, n866 }; + assign n1259 = 64'h40404040ea404040 >> { n744, n738, n750, n748, n737, n747 }; + assign n1260 = 64'h0051515151515151 >> { n741, n740, n736, n746, n1259, n871 }; + assign n1261 = 64'h1b5f5f17bbffffb7 >> { n684, n675, n670, n673, n689, n671 }; + assign n1262 = 64'h0008000800080000 >> { n880, n672, n690, n879, n1261, n1235 }; + assign n579 = 64'h1111100010001000 >> { n559, n553, n550, n554, n552, n549 }; + assign n1263 = 16'h8000 >> { n1262, n677, n878, n1237 }; + assign n1264 = 64'h7ffb7ffb7f7b7ff9 >> { n777, n771, n769, n770, n768, n773 }; + assign n1265 = 64'h000a000200080000 >> { n883, n884, n788, n789, n777, n1264 }; + assign n1266 = 32'd2147483648 >> { n766, n1265, n847, n849, n1293 }; + assign n1267 = 64'h5465655410212110 >> { n597, Pdata_51_, PD_18_, n589, n592, n590 }; + assign n1268 = 32'd389488575 >> { n602, n596, n1267, n607, n592 }; + assign n1269 = 32'd2147483648 >> { n1268, n1300, n598, n603, n886 }; + assign n1270 = 64'h77777557ffff7dd7 >> { n711, n710, Pdata_56_, PD_19_, n703, n732 }; + assign n1271 = 64'h8d8d8d8d8d8d888d >> { n796, n795, n804, n905, n906, n800 }; + assign n1272 = 64'h444c4c4c4c4c4c4c >> { n798, n797, n796, n801, n907, n817 }; + assign n580 = 64'he2a2e0a0e0a0e0a0 >> { n549, n559, n571, n569, n558, n567 }; + assign n1273 = 64'h8000000000000000 >> { n1271, n1272, n808, n818, n904, n1252 }; + assign n1274 = 64'haaaa7bb7aaaa7ff7 >> { n529, n513, Pdata_58_, PD_27_, n515, n514 }; + assign n1275 = 32'd330520567 >> { n560, n562, n550, n573, n558 }; + assign n1276 = 32'd176827050 >> { n567, n564, n581, n558, n1275 }; + assign n1277 = 64'h8000000000000000 >> { n547, n1276, n576, n919, n1227, n1232 }; + assign n1278 = 64'h9bdf9bff9bdf0000 >> { n933, n706, n714, n723, n709, n710 }; + assign n1279 = 64'h5555555595555555 >> { n934, n1278, n712, n720, n1258, Pdata_3_ }; + assign n1280 = 64'hccc4ccc4ccc48880 >> { n746, n943, n744, n893, n945, n747 }; + assign n1281 = 16'h0080 >> { n944, n752, n1280, n1239 }; + assign n1282 = 32'd2155913856 >> { n797, n814, n804, n810, n800 }; + assign n581 = 64'h0000900990090000 >> { Pdata_44_, PC_7_, Pdata_43_, PC_25_, Pdata_42_, PC_3_ }; + assign n1283 = 64'h0004040400445454 >> { n1282, n798, n807, n811, n947, n948 }; + assign n1284 = 64'h8000800080000000 >> { n826, n810, n808, n793, n1283, n1252 }; + assign n1285 = 64'h4ddd6fff6eee6fff >> { n552, n559, n555, n571, n558, n549 }; + assign n1286 = 32'd131586 >> { n573, n560, n568, n572, n1285 }; + assign n1287 = 32'd3721976024 >> { n590, n596, n593, n588, n592 }; + assign n1288 = 64'h2727fff7002700f7 >> { n1234, n607, n589, n1287, n594, n592 }; + assign n1289 = 64'h8000000080008000 >> { n1233, n589, n585, n598, n603, n1288 }; + assign n1290 = 64'hffffeef7fcfabdf7 >> { n777, n769, n768, n773, n770, n771 }; + assign n1291 = 32'd2147483648 >> { n766, n1290, n781, n1243, n1293 }; + assign n1292 = 64'h66f6f6f660f0f0f0 >> { n779, n773, n780, n771, Pdata_32_, PD_3_ }; + assign n582 = 64'he99eb66bd66d7997 >> { Pdata_39_, Pdata_41_, Pdata_40_, PC_18_, PC_11_, PC_22_ }; + assign n1293 = 64'hb5f5f5b580808080 >> { n1244, PD_7_, Pdata_62_, n1292, n768, n771 }; + assign n1294 = 64'ha0bf207fbbbf3b7f >> { n594, n588, n607, n589, n602, n592 }; + assign n1295 = 64'h80a0802088a88828 >> { n938, n596, n593, n592, n1245, n1294 }; + assign n1296 = 32'd2505397589 >> { n585, n1295, n598, n829, Pdata_24_ }; + assign n1297 = 64'hd0ddd0dd5055d0dd >> { n534, n511, n1250, n510, n540, n508 }; + assign n1298 = 64'h8000000000000000 >> { n506, n1297, n1308, n525, n842, n1249 }; + assign n1299 = 64'h507f707fd0fff0ff >> { n596, n587, n589, n592, n590, n588 }; + assign n1300 = 64'h11d999d915dd9ddd >> { n597, n593, n595, n594, n1299, n592 }; + assign n1301 = 64'hb1f5b1f5b1b1b1f5 >> { n703, n715, n723, n706, n704, n710 }; + assign n1302 = 64'h103250f2101250d2 >> { n933, n714, n867, n1301, n709, n710 }; + assign n511 = 16'h6006 >> { Pdata_55_, PD_15_, Pdata_59_, PD_5_ }; + assign Poutreg_new_2_ = 32'd4158838208 >> { Poutreg_10_, Poutreg_2_, Pdata_47_, n544, Pcount_0_ }; + assign n1303 = 64'h0000000080000000 >> { n866, n712, n720, n724, n1302, n1270 }; + assign n1304 = 32'd318911266 >> { n518, n513, n508, n916, n1274 }; + assign n1305 = 64'h070f070f050d070f >> { n510, n516, n517, n917, n521, n524 }; + assign n1306 = 32'd32768 >> { n519, n1304, n1305, n506, n525 }; + assign n1307 = 64'h7f777f7755557f77 >> { n535, n517, n529, n523, n509, n515 }; + assign n1308 = 64'h8008aaaaa22aaaaa >> { n508, n531, PD_27_, Pdata_58_, n535, n1307 }; + assign Poutreg_new_1_ = 64'hd7ffd78282ff8282 >> { Poutreg_9_, Poutreg_1_, Pcount_0_, Pdata_7_, n1289, n544 }; + assign n585 = 64'h1131313131313131 >> { n590, n596, n597, n586, n591, n592 }; + assign n586 = 64'h7dffffd7d7ffff7d >> { n588, n589, n590, Pdata_51_, PD_18_, n587 }; + assign n587 = 4'h6 >> { Pdata_48_, PD_23_ }; + assign n588 = 4'h9 >> { Pdata_52_, PD_26_ }; + assign n589 = 4'h6 >> { Pdata_47_, PD_12_ }; + assign n590 = 4'h9 >> { Pdata_50_, PD_8_ }; + assign n591 = 32'd2820677664 >> { n589, n594, n593, n592, n595 }; + assign n592 = 4'h9 >> { Pdata_49_, PD_2_ }; + assign n512 = 8'h08 >> { n514, n513, n515 }; + assign n593 = 64'h6006000000006006 >> { Pdata_47_, PD_12_, Pdata_51_, PD_18_, Pdata_50_, PD_8_ }; + assign n594 = 16'h1428 >> { Pdata_51_, Pdata_50_, PD_8_, PD_18_ }; + assign n595 = 16'h9009 >> { Pdata_52_, PD_26_, Pdata_48_, PD_23_ }; + assign n596 = 16'h6996 >> { Pdata_47_, Pdata_51_, PD_18_, PD_12_ }; + assign n597 = 16'h4182 >> { Pdata_52_, Pdata_48_, PD_23_, PD_26_ }; + assign n598 = 64'h00d700f700df00ff >> { n602, n599, n600, n589, n592, n597 }; + assign n599 = 8'h28 >> { Pdata_51_, PD_18_, n590 }; + assign n600 = 16'h0002 >> { n592, n590, n596, n601 }; + assign n601 = 16'h6006 >> { Pdata_52_, PD_26_, Pdata_48_, PD_23_ }; + assign n602 = 16'h9009 >> { Pdata_51_, PD_18_, Pdata_50_, PD_8_ }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act b/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act new file mode 100644 index 000000000..968c4e882 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act @@ -0,0 +1,870 @@ +clock 0.497600 0.501000 +PRESET 0.503600 0.501400 +Pdxport_0_0_ 0.496800 0.499200 +Pdxport_1_1_ 0.502600 0.501800 +Pdxport_2_2_ 0.500600 0.496000 +Pdxport_3_3_ 0.507000 0.498600 +Pdxport_4_4_ 0.500800 0.499000 +Pdxport_5_5_ 0.504200 0.506200 +Pdxport_6_6_ 0.506000 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0.000002 +n1076 1.000000 0.000000 +n1077 0.989800 0.000002 +n315 0.000000 0.252505 +n1079 0.000000 0.000000 +n1230 0.000000 0.252505 +n515 0.000000 0.252505 +n1082 0.000000 0.000000 +n530 0.000000 0.252505 +n1084 0.000000 0.000000 +n580 0.042200 0.061077 +n980 0.000000 0.252505 +n1087 0.000000 0.000000 +n240 0.007200 0.000067 +n1089 0.000000 0.000000 +n460 0.000000 0.252505 +n1091 0.000000 0.000000 +n1165_1 0.000000 0.252505 +n1400_1 0.046800 0.060711 +n1280_1 0.000000 0.252505 +n1305_1 0.000000 0.252505 +n1096 0.000000 0.000000 +n760 0.000000 0.000000 +n1098 1.000000 0.000000 +n1380_1 0.039600 0.060142 +n645 0.043800 0.060831 +n705 0.043800 0.060207 +n720 0.047200 0.060636 +n750 0.000000 0.252505 +n1104 0.000000 0.000000 +n1370_1 0.044400 0.060882 +n145 0.000000 0.000000 +n1107 1.000000 0.000000 +n1108 1.000000 0.000000 +n1109 1.000000 0.000000 +n1110_1 1.000000 0.000000 +n1111 1.000000 0.000000 +n1112 0.000000 0.000000 +n1113 1.000000 0.000000 +n1114 1.000000 0.000000 +n1115_1 1.000000 0.000000 +n1116 1.000000 0.000000 +n1117 1.000000 0.000000 +n1118 1.000000 0.000000 +n1119 0.000000 0.000000 +n1120_1 1.000000 0.000000 +n1121 1.000000 0.000000 +n1122 1.000000 0.000000 +n1123 1.000000 0.000000 +n1124 1.000000 0.000000 +n1125_1 1.000000 0.000000 +n1126 1.000000 0.000000 +n1127 1.000000 0.000000 +n1128 1.000000 0.000000 +n1129 1.000000 0.000000 +n1130_1 1.000000 0.000000 +n1131 1.000000 0.000000 +n1132 1.000000 0.000000 +n1133 1.000000 0.000000 +n1134 0.479600 0.000000 +n1135_1 0.959400 0.001933 +n1136 0.016800 0.021237 +n1137 1.000000 0.000000 +n1138 1.000000 0.000000 +n1139 0.006000 0.243193 +n1520_1 0.000000 0.000000 +n1141 0.000000 0.000000 +n90 0.000000 0.000000 +n1143 1.000000 0.000000 +n1360_1 0.000000 0.252505 +n95 0.042200 0.060482 +n110 0.000000 0.000000 +n1147 0.000000 0.000000 +n520 0.000000 0.000114 +n345 0.000000 0.000000 +n425 0.000000 0.252505 +n685 0.000000 0.000000 +n1152 0.000000 0.000000 +n130 0.000000 0.000000 +n1154 0.000000 0.000000 +n410 0.000000 0.000114 +n510 0.000000 0.252505 +n80 0.245000 0.001729 +n1105 0.000000 0.000114 +n365 0.000000 0.000000 +n1160 0.000000 0.000000 +n1265_1 0.000000 0.252505 +n340 0.000000 0.000000 +n1163 1.000000 0.000000 +n1515_1 0.000000 0.248895 +n1165 0.000000 0.000000 +n1166 0.012000 0.023712 +n1167 0.000000 0.248895 +n1075 0.000000 0.252505 +n830 0.047800 0.060593 +n770 0.000000 0.252505 +n1505_1 0.000000 0.000000 +n1172 0.000000 0.000000 +n1040 0.000000 0.000000 +n150 0.000000 0.000000 +n650 0.000000 0.000064 +n1176 1.000000 0.000000 +n1177 0.010200 0.020192 +n670 0.000000 0.000098 +n1179 1.000000 0.000000 +n1180_1 0.012600 0.024882 +n955 0.000000 0.252505 +n260 0.000000 0.252505 +n1035 0.000000 0.252505 +n695 0.000000 0.000092 +n300 0.000000 0.252505 +n270 0.009400 0.000106 +n1187 1.000000 0.000000 +n1188 0.013400 0.026441 +n1025 0.000000 0.000114 +n1485_1 0.000000 0.248895 +n1500_1 0.000000 0.000000 +n615 0.000000 0.000080 +n1193 0.011400 0.000002 +n280 0.000000 0.252505 +n810 0.000000 0.252505 +n930 0.000000 0.252505 +n1065 0.000000 0.000000 +n380 0.008400 0.000222 +n1199 0.479600 0.229783 +n1200_1 0.000200 0.000000 +n1201 0.040600 0.001734 +n1202 0.490400 0.225434 +n1203 0.983200 0.000305 +n1204 0.984600 0.000051 +n415 0.006000 0.000139 +n1206 0.983800 0.000300 +n1207 0.985000 0.000143 +n665 0.042200 0.059985 +n855 0.000000 0.000000 +n805 0.000000 0.000000 +n1211 1.000000 0.000000 +n1140_1 0.000000 0.000000 +n1213 1.000000 0.000000 +n1345_1 0.000000 0.252505 +n1215 0.000000 0.000000 +n165 0.000000 0.000114 +n395 0.000000 0.000000 +n950 0.009200 0.000077 +n495 0.000000 0.252505 +n490 0.000000 0.252505 +n690 0.044000 0.062023 +n890 0.047400 0.060513 +n160 0.000000 0.000000 +n1224 1.000000 0.000000 +n1355_1 0.000000 0.000000 +n1120 0.000000 0.000000 +n310 0.009600 0.000111 +n1228 1.000000 0.000000 +n1229 0.013200 0.026052 +n325 0.009600 0.243638 +n1231 0.006000 0.000224 +n1232 0.010800 0.242856 +n195 0.000000 0.252505 +n620 0.044200 0.060607 +n1005 0.000000 0.252505 +n1340_1 0.000000 0.000000 +n1405_1 0.000000 0.000069 +n885 0.000000 0.252505 +n1440_1 0.000000 0.000000 +n1495_1 0.000000 0.000000 +n505 0.000000 0.252505 +n210 0.009600 0.000070 +n1243 0.012200 0.000002 +n1045 0.000000 0.000000 +n860 0.000000 0.000000 +n1246 1.000000 0.000000 +n1247 0.988600 0.000002 +n1248 0.000000 0.248895 +n1090 0.000000 0.252505 +n335 0.000000 0.252505 +n1275 0.000000 0.252505 +n850 0.000000 0.000114 +n245 0.000000 0.000000 +n105 0.000000 0.000000 +n85 0.000000 0.000000 +n1256 1.000000 0.000000 +n1310_1 0.000000 0.000114 +n445 0.000000 0.000114 +n480 0.000000 0.000114 +n610 0.000000 0.000114 +n1240_1 0.000000 0.252505 +n1205 0.000000 0.000114 +n180 0.000000 0.000000 +n455 0.007400 0.000179 +n1265 0.983000 0.000359 +n1266 0.983000 0.000361 +n1267 0.983200 0.000361 +n1210 0.007400 0.002980 +n1269 0.001800 0.240536 +n225 0.000000 0.252505 +n1070 0.007600 0.000088 +n1235 0.006800 0.000066 +n925 0.000000 0.252505 +n1285 0.000000 0.000114 +n465 0.000000 0.000000 +n430 0.000000 0.000000 +n230 0.000000 0.252505 +n1455_1 0.042000 0.061916 +n440 0.009000 0.025450 +n1280 0.005800 0.000200 +n355 0.007600 0.000200 +n880 0.000000 0.000000 +n1283 0.000000 0.000000 +n700 0.000000 0.000000 +n1285_1 0.000000 0.000000 +n1286 0.000000 0.000000 +n710 0.000000 0.000000 +n1288 1.000000 0.000000 +n550 0.000000 0.252505 +n190 0.000000 0.000114 +n220 0.000000 0.000114 +n1080 0.000000 0.000000 +n715 0.000000 0.000000 +n1294 1.000000 0.000000 +n740 0.000000 0.000000 +n1296 1.000000 0.000000 +n1297 0.000000 0.000000 +n1480_1 0.000000 0.248895 +n405 0.000000 0.000000 +n185 0.000000 0.000000 +n1301 1.000000 0.000000 +n295 0.000000 0.000000 +n1303 1.000000 0.000000 +n205 0.000000 0.000000 +n235 0.000000 0.000000 +n1425_1 0.000000 0.000111 +n1465_1 0.000000 0.000115 +n1015 0.000000 0.252505 +n1055 0.000000 0.252505 +n1190_1 0.000000 0.252505 +n1225_1 0.000000 0.252505 +n840 0.000000 0.000000 +n1125 0.000000 0.000000 +n1410_1 0.046800 0.062464 +n1430_1 0.046400 0.059201 +n845 0.044000 0.060895 +n1195 0.000000 0.000000 +n1170_1 0.000000 0.000000 +n535 0.000000 0.000114 +n1395_1 0.000000 0.000073 +n1030 0.000000 0.252505 +n170 0.000000 0.252505 +n360 0.000000 0.252505 +n985 0.000000 0.252505 +n1110 0.009600 0.000226 +n1326 0.983000 0.000367 +n1420_1 0.051400 0.059867 +n385 0.000000 0.252505 +n780 0.000000 0.000000 +n435 0.000000 0.000114 +n1135 0.009600 0.000257 +n600 0.038800 0.061196 +n815 0.000000 0.252505 +n1115 0.000000 0.252505 +n140 0.000000 0.252505 +n525 0.000000 0.252505 +n545 0.000000 0.252505 +n1365_1 0.000000 0.000000 +n290 0.000000 0.000000 +n125 0.000000 0.000000 +n1050 0.008400 0.000094 +n500 0.000000 0.000114 +n1060 0.000000 0.000000 +n390 0.000000 0.000000 +n1345 0.000000 0.000000 +n250 0.000000 0.000114 +n870 0.000000 0.252505 +n940 0.000000 0.252505 +n1200 0.000000 0.252505 +n1160_1 0.009400 0.000284 +n1351 0.007600 0.000248 +n1185 0.007000 0.000159 +n1330_1 0.000000 0.000000 +n1010 0.006200 0.000062 +n1295 0.000000 0.252505 +n175 0.000000 0.252505 +n200 0.000000 0.252505 +n635 0.000000 0.000114 +n1220_1 0.000000 0.000114 +n475 0.006800 0.000000 +n1361 1.000000 0.230654 +n1362 0.983200 0.028775 +n655 0.043200 0.060443 +n820 0.039800 0.061673 +n320 0.000000 0.000000 +n450 0.000000 0.252505 +n485 0.000000 0.252505 +n1020 0.000000 0.000000 +n590 0.245000 0.001729 +n1270_1 0.000000 0.000000 +n1260_1 0.000000 0.252505 +n1095 0.000000 0.000000 +n555 0.000000 0.252505 +n825 0.000000 0.000000 +n605 0.000000 0.000114 +n275 0.000000 0.000114 +n900 0.000000 0.000000 +n960 0.000000 0.000000 +n775 0.000000 0.000114 +n570 0.046200 0.061752 +n595 0.000000 0.000081 +n255 0.000000 0.252505 +n305 0.000000 0.000000 +n725 0.245000 0.001729 +n910 0.000000 0.000114 +n970 0.000000 0.000114 +n1145_1 0.000000 0.000000 +n1130 0.000000 0.000114 +n1155_1 0.000000 0.000114 +n1320_1 0.000000 0.252505 +n865 0.000000 0.252505 +n920 0.000000 0.252505 +n470 0.000000 0.000114 +n265 0.000000 0.000000 +n120 0.000000 0.252505 +n585 0.000000 0.000114 +n1215_1 0.008400 0.000231 +n330 0.000000 0.000000 +n1399 1.000000 0.000000 +n1325_1 0.000000 0.000114 +n795 0.000000 0.000114 +n755 0.000000 0.000000 +n730 0.000000 0.000000 +n575 0.245000 0.001729 +n215 0.000000 0.000000 +n540 0.426800 0.217622 +n1530_1 0.817400 0.036302 +n1408 0.235000 0.044763 +n1535_1 1.000000 0.000000 +n1540_1 1.000000 0.000000 +n1545_1 1.000000 0.000000 +n1412 0.999800 0.000000 +n1413 0.496400 0.000000 +n1414 0.999800 0.041592 +n1550_1 1.000000 0.000000 +n1555_1 1.000000 0.000000 +n1560_1 1.000000 0.000000 +n1418 0.000000 0.117501 +n1419 0.080600 0.139841 +n1420 0.076800 0.000025 +n1421 0.920800 0.007595 +n1422 0.923000 0.000000 +n1423 0.920400 0.000061 +n1424 0.069800 0.088762 +n1565_1 1.000000 0.000000 +n1570_1 1.000000 0.000000 +n1575_1 1.000000 0.000000 +n1580_1 0.791200 0.028502 +n285 0.000000 0.000759 +n1430 1.000000 0.000000 +n1431 1.000000 0.000000 +n1432 1.000000 0.000000 +n1433 0.040600 0.000000 +n1385_1 0.016800 0.000932 +n745 0.000000 0.027967 +n1100 0.000000 0.027967 +n1350_1 0.040600 0.000000 +n1460_1 0.000000 0.248895 +n1375_1 0.000000 0.027967 +n115 0.000000 0.027967 +n640 0.000000 0.000000 +n63 0.139200 0.242794 +n1335_1 0.088200 0.000000 +n1250 0.000000 0.000796 +n565 0.000000 0.248895 +n905 0.016800 0.000763 +n155 0.000000 0.027967 +n765 0.000000 0.027967 +n735 0.000000 0.000000 +n135 0.000000 0.027967 +n1470_1 0.000000 0.248895 +n1490_1 0.000000 0.027967 +n675 0.016800 0.000000 +n630 0.000000 0.248895 +n1390_1 0.000000 0.027967 +n1150_1 0.000000 0.000000 +n400 0.000000 0.248895 +n875 0.000000 0.027967 +n1445_1 0.000000 0.248895 +n790 0.000000 0.027967 +n945 0.000000 0.027967 +n625 0.000000 0.027967 +n100 0.000000 0.027967 +n420 0.000000 0.000000 +n1450_1 0.000000 0.248895 +n995 0.000000 0.027967 +n1475_1 0.016800 0.022028 +n1085 0.000000 0.027967 +n560 0.094400 0.000870 +n660 0.000000 0.027967 +n680 0.000000 0.027967 +n1415_1 0.000000 0.027967 +n1435_1 0.000000 0.027967 +n1525_1 0.991400 0.000155 +n1175_1 0.000000 0.000000 +n71 0.000000 0.000000 +n67 0.000000 0.000000 +n1478 0.980200 0.000005 +n1479 0.980200 0.023917 +n1480 0.978400 0.000006 +n1481 0.978400 0.023482 +n1482 1.000000 0.001933 +n1483 1.000000 0.000000 +n1484 0.983200 0.000058 +n1485 0.000000 0.000000 diff --git a/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif b/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif new file mode 100644 index 000000000..abb235065 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif @@ -0,0 +1,2376 @@ +# Benchmark "diffeq" written by ABC on Tue Mar 12 09:38:45 2019 +.model diffeq +.inputs clock PRESET Pdxport_0_0_ Pdxport_1_1_ Pdxport_2_2_ Pdxport_3_3_ \ + Pdxport_4_4_ Pdxport_5_5_ Pdxport_6_6_ Pdxport_7_7_ Pdxport_8_8_ \ + Pdxport_9_9_ Pdxport_10_10_ Pdxport_11_11_ Paport_0_0_ Paport_1_1_ \ + Paport_2_2_ Paport_3_3_ Paport_4_4_ Paport_5_5_ Paport_6_6_ Paport_7_7_ \ + Paport_8_8_ Paport_9_9_ Paport_10_10_ Paport_11_11_ Preset_0_0_ \ + Pready_0_0_ +.outputs PDN Pnext_0_0_ Pover_0_0_ + +.latch n63 PDN re clock 0 +.latch n67 Pnext_0_0_ re clock 0 +.latch n71 Pover_0_0_ re clock 0 +.latch n75 N_N4054 re clock 0 +.latch n80 N_N3745 re clock 0 +.latch n85 N_N4119 re clock 0 +.latch n90 N_N3826 re clock 0 +.latch n95 N_N3818 re clock 0 +.latch n100 N_N3345 re clock 0 +.latch n105 N_N3924 re clock 0 +.latch n110 N_N3815 re clock 0 +.latch n115 N_N3691 re clock 0 +.latch n120 N_N3157 re clock 0 +.latch n125 N_N3872 re clock 0 +.latch n130 N_N3788 re clock 0 +.latch n135 N_N3375 re clock 0 +.latch n140 N_N3143 re clock 0 +.latch n145 N_N4197 re clock 0 +.latch n150 N_N3843 re clock 0 +.latch n155 N_N3426 re clock 0 +.latch n160 N_N4118 re clock 0 +.latch n165 N_N3580 re clock 0 +.latch n170 N_N3175 re clock 0 +.latch n175 N_N3071 re clock 0 +.latch n180 N_N3808 re clock 0 +.latch n185 N_N3923 re clock 0 +.latch n190 N_N3250 re clock 0 +.latch n195 N_N4221 re clock 0 +.latch n200 N_N3069 re clock 0 +.latch n205 N_N3464 re clock 0 +.latch n210 N_N3535 re clock 0 +.latch n215 N_N3871 re clock 0 +.latch n220 N_N3248 re clock 0 +.latch n225 N_N4180 re clock 0 +.latch n230 N_N3311 re clock 0 +.latch n235 N_N3442 re clock 0 +.latch n240 N_N3981 re clock 0 +.latch n245 N_N3842 re clock 0 +.latch n250 N_N3105 re clock 0 +.latch n255 N_N4133 re clock 0 +.latch n260 N_N4117 re clock 0 +.latch n265 N_N3420 re clock 0 +.latch n270 N_N3761 re clock 0 +.latch n275 N_N3062 re clock 0 +.latch n280 N_N4071 re clock 0 +.latch n285 N_N4227 re clock 0 +.latch n290 N_N3807 re clock 0 +.latch n295 N_N4145 re clock 0 +.latch n300 N_N3922 re clock 0 +.latch n305 N_N3516 re clock 0 +.latch n310 N_N3489 re clock 0 +.latch n315 N_N4030 re clock 0 +.latch n320 N_N3540 re clock 0 +.latch n325 N_N3513 re clock 0 +.latch n330 N_N4083 re clock 0 +.latch n335 N_N3841 re clock 0 +.latch n340 N_N4018 re clock 0 +.latch n345 N_N3971 re clock 0 +.latch n350 N_N4232 re clock 0 +.latch n355 N_N4246 re clock 0 +.latch n360 N_N3806 re clock 0 +.latch n365 N_N3992 re clock 0 +.latch n370 N_N4086 re clock 0 +.latch n375 N_N4230 re clock 0 +.latch n380 N_N4212 re clock 0 +.latch n385 N_N3626 re clock 0 +.latch n390 N_N3965 re clock 0 +.latch n395 N_N3890 re clock 0 +.latch n400 NDN3_11 re clock 0 +.latch n405 NDN5_10 re clock 0 +.latch n410 N_N3786 re clock 0 +.latch n415 N_N4171 re clock 0 +.latch n420 NDN5_16 re clock 0 +.latch n425 N_N3799 re clock 0 +.latch n430 N_N3844 re clock 0 +.latch n435 N_N3196 re clock 0 +.latch n440 N_N4126 re clock 0 +.latch n445 N_N3681 re clock 0 +.latch n450 N_N3679 re clock 0 +.latch n455 N_N3340 re clock 0 +.latch n460 N_N4116 re clock 0 +.latch n465 N_N3810 re clock 0 +.latch n470 N_N3235 re clock 0 +.latch n475 N_N3283 re clock 0 +.latch n480 N_N3716 re clock 0 +.latch n485 N_N3701 re clock 0 +.latch n490 N_N3921 re clock 0 +.latch n495 N_N3625 re clock 0 +.latch n500 N_N3751 re clock 0 +.latch n505 N_N3736 re clock 0 +.latch n510 N_N3870 re clock 0 +.latch n515 N_N4024 re clock 0 +.latch n520 N_N3876 re clock 0 +.latch n525 N_N3840 re clock 0 +.latch n530 N_N4021 re clock 0 +.latch n535 N_N3932 re clock 0 +.latch n540 NLC1_2 re clock 0 +.latch n545 N_N3805 re clock 0 +.latch n550 N_N3700 re clock 0 +.latch n555 N_N3735 re clock 0 +.latch n560 NLak3_2 re clock 0 +.latch n565 NLak3_9 re clock 0 +.latch n570 N_N3906 re clock 0 +.latch n575 N_N3388 re clock 0 +.latch n580 N_N4057 re clock 0 +.latch n585 N_N3011 re clock 0 +.latch n590 N_N3346 re clock 0 +.latch n595 N_N3677 re clock 0 +.latch n600 N_N4165 re clock 0 +.latch n605 N_N4080 re clock 0 +.latch n610 N_N3373 re clock 0 +.latch n615 N_N3709 re clock 0 +.latch n620 N_N4206 re clock 0 +.latch n625 N_N3324 re clock 0 +.latch n630 N_N3575 re clock 0 +.latch n635 N_N4159 re clock 0 +.latch n640 NAK5_2 re clock 0 +.latch n645 N_N3916 re clock 0 +.latch n650 N_N3743 re clock 0 +.latch n655 N_N4242 re clock 0 +.latch n660 N_N3312 re clock 0 +.latch n665 N_N3733 re clock 0 +.latch n670 N_N3774 re clock 0 +.latch n675 N_N4214 re clock 0 +.latch n680 N_N3294 re clock 0 +.latch n685 N_N3796 re clock 0 +.latch n690 N_N3574 re clock 0 +.latch n695 N_N3791 re clock 0 +.latch n700 N_N3480 re clock 0 +.latch n705 N_N4243 re clock 0 +.latch n710 N_N3940 re clock 0 +.latch n715 N_N3509 re clock 0 +.latch n720 N_N4015 re clock 0 +.latch n725 N_N2989 re clock 0 +.latch n730 N_N3919 re clock 0 +.latch n735 N_N3578 re clock 0 +.latch n740 N_N3529 re clock 0 +.latch n745 N_N4222 re clock 0 +.latch n750 N_N3910 re clock 0 +.latch n755 N_N3868 re clock 0 +.latch n760 N_N3947 re clock 0 +.latch n765 N_N4181 re clock 0 +.latch n770 N_N3793 re clock 0 +.latch n775 N_N3822 re clock 0 +.latch n780 N_N3813 re clock 0 +.latch n785 N_N4114 re clock 0 +.latch n790 N_N4134 re clock 0 +.latch n795 N_N3866 re clock 0 +.latch n800 N_N4218 re clock 0 +.latch n805 N_N3939 re clock 0 +.latch n810 N_N3776 re clock 0 +.latch n815 N_N3387 re clock 0 +.latch n820 N_N4194 re clock 0 +.latch n825 N_N3821 re clock 0 +.latch n830 N_N3882 re clock 0 +.latch n835 N_N4167 re clock 0 +.latch n840 N_N3800 re clock 0 +.latch n845 N_N4237 re clock 0 +.latch n850 N_N3417 re clock 0 +.latch n855 N_N3918 re clock 0 +.latch n860 N_N4158 re clock 0 +.latch n865 N_N3630 re clock 0 +.latch n870 N_N3344 re clock 0 +.latch n875 N_N4072 re clock 0 +.latch n880 N_N3274 re clock 0 +.latch n885 N_N3473 re clock 0 +.latch n890 N_N4205 re clock 0 +.latch n895 N_N4111 re clock 0 +.latch n900 N_N3680 re clock 0 +.latch n905 N_N3838 re clock 0 +.latch n910 N_N3262 re clock 0 +.latch n915 N_N4099 re clock 0 +.latch n920 N_N3607 re clock 0 +.latch n925 N_N3323 re clock 0 +.latch n930 N_N3612 re clock 0 +.latch n935 N_N4079 re clock 0 +.latch n940 N_N3457 re clock 0 +.latch n945 N_N3445 re clock 0 +.latch n950 N_N3794 re clock 0 +.latch n955 N_N3663 re clock 0 +.latch n960 N_N3715 re clock 0 +.latch n965 N_N4039 re clock 0 +.latch n970 N_N3280 re clock 0 +.latch n975 N_N4239 re clock 0 +.latch n980 N_N3988 re clock 0 +.latch n985 N_N3433 re clock 0 +.latch n990 N_N4075 re clock 0 +.latch n995 N_N3468 re clock 0 +.latch n1000 N_N4045 re clock 0 +.latch n1005 N_N3482 re clock 0 +.latch n1010 N_N3832 re clock 0 +.latch n1015 N_N3304 re clock 0 +.latch n1020 N_N3750 re clock 0 +.latch n1025 N_N3634 re clock 0 +.latch n1030 N_N3293 re clock 0 +.latch n1035 N_N3659 re clock 0 +.latch n1040 N_N4252 re clock 0 +.latch n1045 N_N3912 re clock 0 +.latch n1050 N_N3862 re clock 0 +.latch n1055 N_N3221 re clock 0 +.latch n1060 N_N3875 re clock 0 +.latch n1065 N_N3949 re clock 0 +.latch n1070 N_N3908 re clock 0 +.latch n1075 N_N3711 re clock 0 +.latch n1080 N_N3931 re clock 0 +.latch n1085 N_N3469 re clock 0 +.latch n1090 N_N3436 re clock 0 +.latch n1095 N_N3974 re clock 0 +.latch n1100 N_N3905 re clock 0 +.latch n1105 N_N3741 re clock 0 +.latch n1110 N_N3369 re clock 0 +.latch n1115 N_N3164 re clock 0 +.latch n1120 N_N3500 re clock 0 +.latch n1125 N_N3996 re clock 0 +.latch n1130 N_N3356 re clock 0 +.latch n1135 N_N4093 re clock 0 +.latch n1140_1 N_N4224 re clock 0 +.latch n1145_1 N_N4027 re clock 0 +.latch n1150_1 NDN1_4 re clock 0 +.latch n1155_1 N_N3384 re clock 0 +.latch n1160_1 N_N4036 re clock 0 +.latch n1165_1 N_N3968 re clock 0 +.latch n1170_1 N_N4183 re clock 0 +.latch n1175_1 NGFDN_3 re clock 0 +.latch n1180 N_N4090 re clock 0 +.latch n1185 N_N4004 re clock 0 +.latch n1190_1 N_N3205 re clock 0 +.latch n1195 N_N4136 re clock 0 +.latch n1200 N_N3303 re clock 0 +.latch n1205 N_N3533 re clock 0 +.latch n1210 N_N3336 re clock 0 +.latch n1215_1 N_N3961 re clock 0 +.latch n1220_1 N_N3331 re clock 0 +.latch n1225_1 N_N3203 re clock 0 +.latch n1230 N_N4236 re clock 0 +.latch n1235 N_N3884 re clock 0 +.latch n1240_1 N_N3367 re clock 0 +.latch n1245 N_N4140 re clock 0 +.latch n1250 NDN2_2 re clock 0 +.latch n1255_1 N_N4106 re clock 0 +.latch n1260_1 N_N3100 re clock 0 +.latch n1265_1 N_N4193 re clock 0 +.latch n1270_1 N_N3470 re clock 0 +.latch n1275 N_N3424 re clock 0 +.latch n1280_1 N_N3959 re clock 0 +.latch n1285 N_N3393 re clock 0 +.latch n1290 N_N4042 re clock 0 +.latch n1295 N_N3188 re clock 0 +.latch n1300_1 N_N4095 re clock 0 +.latch n1305_1 N_N3957 re clock 0 +.latch n1310_1 N_N3517 re clock 0 +.latch n1315_1 N_N4047 re clock 0 +.latch n1320_1 N_N3081 re clock 0 +.latch n1325_1 N_N3541 re clock 0 +.latch n1330_1 N_N4177 re clock 0 +.latch n1335_1 NDN3_3 re clock 0 +.latch n1340_1 N_N4176 re clock 0 +.latch n1345_1 N_N3585 re clock 0 +.latch n1350_1 NDN3_8 re clock 0 +.latch n1355_1 N_N4209 re clock 0 +.latch n1360_1 N_N3824 re clock 0 +.latch n1365_1 N_N4208 re clock 0 +.latch n1370_1 N_N4120 re clock 0 +.latch n1375_1 N_N3708 re clock 0 +.latch n1380_1 N_N4220 re clock 0 +.latch n1385_1 N_N3999 re clock 0 +.latch n1390_1 N_N4223 re clock 0 +.latch n1395_1 N_N3179 re clock 0 +.latch n1400_1 N_N4179 re clock 0 +.latch n1405_1 N_N3475 re clock 0 +.latch n1410_1 N_N4132 re clock 0 +.latch n1415_1 N_N4182 re clock 0 +.latch n1420_1 N_N3797 re clock 0 +.latch n1425_1 N_N3214 re clock 0 +.latch n1430_1 N_N4070 re clock 0 +.latch n1435_1 N_N4135 re clock 0 +.latch n1440_1 NLD3_9 re clock 0 +.latch n1445_1 NDN5_2 re clock 0 +.latch n1450_1 NDN5_3 re clock 0 +.latch n1455_1 N_N3778 re clock 0 +.latch n1460_1 NDN5_4 re clock 0 +.latch n1465_1 N_N3212 re clock 0 +.latch n1470_1 NDN5_5 re clock 0 +.latch n1475_1 NDN5_6 re clock 0 +.latch n1480_1 NDN5_7 re clock 0 +.latch n1485_1 NDN5_8 re clock 0 +.latch n1490_1 N_N4073 re clock 0 +.latch n1495_1 NDN5_9 re clock 0 +.latch n1500_1 NEN5_9 re clock 0 +.latch n1505_1 N_N3684 re clock 0 +.latch n1510_1 N_N4056 re clock 0 +.latch n1515_1 N_N3713 re clock 0 +.latch n1520_1 N_N3829 re clock 0 +.latch n1525_1 N_N4060 re clock 0 +.latch n1530_1 NSr3_2 re clock 0 +.latch n1535_1 NSr5_2 re clock 0 +.latch n1540_1 NSr5_3 re clock 0 +.latch n1545_1 N_N3462 re clock 0 +.latch n1550_1 N_N3460 re clock 0 +.latch n1555_1 NSr5_4 re clock 0 +.latch n1560_1 NSr3_9 re clock 0 +.latch n1565_1 NSr5_5 re clock 0 +.latch n1570_1 NSr5_7 re clock 0 +.latch n1575_1 NSr5_8 re clock 0 +.latch n1580_1 N_N3998 re clock 0 + +.names N_N4239 n950_1 N_N4090 n953 n954 N_N3774 n975 +10---- 1 +--11-- 1 +----11 1 +.names n952 n951 NDN3_8 NDN3_3 PDN NDN1_4 n950_1 +00---- 1 +0-01-- 1 +0---10 1 +.names PRESET NLD3_9 n951 +00 1 +.names PDN NLC1_2 NDN1_4 PRESET N_N3998 Preset_0_0_ n952 +1000-0 1 +11001- 1 +.names NDN3_3 PRESET NDN3_8 n953 +100 1 +.names NLD3_9 PRESET n954 +10 1 +.names N_N4232 PRESET NDN3_3 NSr3_2 n350 +101- 1 +10-1 1 +.names N_N4230 PRESET NDN3_3 NSr3_2 n375 +101- 1 +10-1 1 +.names N_N4218 PRESET NDN3_3 NSr3_2 n800 +101- 1 +10-1 1 +.names n969 PRESET n999 n959 N_N4167 n835 +00--1 1 +1001- 1 +1010- 1 +.names n998 n997 n996 n993 n960_1 n959 +110-- 1 +11--0 1 +1-00- 1 +1--00 1 +-10-0 1 +-1-0- 1 +--000 1 +.names n992 n990_1 n975_1 n974 n961 n960_1 +01--- 1 +0-00- 1 +0---1 1 +-100- 1 +-1--1 1 +.names n972 n973 n971 n962 n961 +0011 1 +100- 1 +10-0 1 +.names n963 N_N3203 n969 N_N3081 n970_1 n962 +0---- 0 +-11-- 0 +---11 0 +.names n964 N_N3679 n969 N_N4021 n970_1 n963 +0---- 0 +-11-- 0 +---11 0 +.names n968 n967 n966 n965_1 n964 +1111 1 +.names N_N3205 NDN5_10 NSr5_7 NEN5_9 N_N3957 NDN5_9 n965_1 +100--- 0 +---110 0 +.names N_N3799 NDN5_10 NSr5_7 NEN5_9 N_N4024 NDN5_9 n966 +100--- 0 +---110 0 +.names N_N3968 NDN5_10 NSr5_7 NEN5_9 N_N3959 NDN5_9 n967 +100--- 0 +---110 0 +.names N_N3626 NDN5_10 NSr5_7 NEN5_9 N_N3625 NDN5_9 n968 +100--- 0 +---110 0 +.names NDN5_10 NSr5_7 n969 +00 1 +.names NEN5_9 NDN5_9 n970_1 +10 1 +.names N_N3701 n969 n970_1 N_N3700 n971 +11-- 0 +--11 0 +.names N_N3100 n969 n970_1 N_N3585 n972 +11-- 0 +--11 0 +.names N_N4136 n969 n970_1 N_N3815 n973 +11-- 0 +--11 0 +.names n973 n972 n971 n962 n974 +100- 1 +10-0 1 +1111 1 +.names n971 n962 n989 n977 n976 n988 n975_1 +0011-- 1 +001-0- 1 +00-10- 1 +00---1 1 +1111-- 1 +111-0- 1 +11-10- 1 +11---1 1 +--11-1 1 +--1-01 1 +---101 1 +.names n963 N_N3203 N_N3081 n970_1 n969 n976 +000-- 1 +00-0- 1 +0-0-0 1 +0--00 1 +11--1 1 +1-11- 1 +.names n985_1 n986 n987 n979 n978 n977 +110-- 1 +11-1- 1 +1-01- 1 +1---0 1 +-10-0 1 +-1-10 1 +--010 1 +.names n964 N_N3679 N_N4021 n970_1 n969 n978 +000-- 1 +00-0- 1 +0-0-0 1 +0--00 1 +11--1 1 +1-11- 1 +.names n966 n980_1 n984 n983 n982 n981 n979 +0000-- 1 +000-1- 1 +00-01- 1 +00---1 1 +1100-- 1 +110-1- 1 +11-01- 1 +11---1 1 +--00-1 1 +--0-11 1 +---011 1 +.names n968 n967 n980_1 +11 1 +.names N_N4086 n969 n970_1 N_N3480 n981 +11-- 0 +--11 0 +.names N_N3500 n969 n970_1 N_N3684 n982 +11-- 0 +--11 0 +.names n968 N_N3971 n969 n970_1 N_N3796 n983 +011-- 1 +0--11 1 +.names n968 n967 n984 +01 1 +10 1 +.names N_N3890 n969 n970_1 N_N3509 n985_1 +11-- 0 +--11 0 +.names N_N4224 n969 n970_1 N_N3829 n986 +11-- 0 +--11 0 +.names n965_1 n968 n967 n966 n987 +0111 1 +10-- 1 +1-0- 1 +1--0 1 +.names N_N3844 n969 n970_1 N_N3529 n988 +11-- 0 +--11 0 +.names N_N4183 n969 n970_1 N_N3826 n989 +11-- 0 +--11 0 +.names n991 n972 n971 n962 n990_1 +0111 1 +10-- 1 +1-0- 1 +1--0 1 +.names N_N3736 n969 n970_1 N_N3735 n991 +11-- 0 +--11 0 +.names N_N3810 n969 n970_1 N_N3947 n992 +11-- 0 +--11 0 +.names n994 N_N3482 N_N4075 n970_1 n969 n993 +000-- 1 +00-0- 1 +0-0-0 1 +0--00 1 +11--1 1 +1-11- 1 +.names n995_1 n991 n972 n971 n962 n994 +11111 1 +.names N_N4042 n969 n970_1 N_N3824 n995_1 +11-- 0 +--11 0 +.names n995_1 n991 n972 n971 n962 n996 +01111 1 +10--- 1 +1-0-- 1 +1--0- 1 +1---0 1 +.names N_N3470 n969 n970_1 N_N3274 n997 +11-- 0 +--11 0 +.names N_N4140 n969 n970_1 N_N3788 n998 +11-- 0 +--11 0 +.names n1000_1 n994 N_N3482 N_N4075 n970_1 n969 n999 +0100-- 1 +010-0- 1 +01-0-0 1 +01--00 1 +10---- 1 +1-1--1 1 +1--11- 1 +.names n970_1 n969 N_N3612 N_N4167 N_N4095 N_N4039 n1000_1 +01--01 1 +01--10 1 +1001-- 1 +1010-- 1 +1-01-0 1 +1-100- 1 +-10-10 1 +-1-001 1 +.names N_N4140 n950_1 N_N3541 n953 n954 N_N3540 n1245 +10---- 1 +--11-- 1 +----11 1 +.names n970_1 PRESET n999 n959 N_N4114 n785 +00--1 1 +1001- 1 +1010- 1 +.names n1005_1 PRESET n1004 N_N4111 n895 +00-1 1 +101- 1 +.names n1005_1 n970_1 N_N3906 N_N3940 N_N3939 N_N3910 n1004 +01--01 1 +01--10 1 +1001-- 1 +1010-- 1 +1-01-0 1 +1-100- 1 +-10-10 1 +-1-001 1 +.names NDN3_8 NSr3_9 NLak3_9 NDN5_6 n1005_1 +1100 1 +.names N_N4106 PRESET NDN3_3 NSr3_2 n1255_1 +101- 1 +10-1 1 +.names N_N4099 n950_1 N_N3384 n953 N_N3743 n954 n915 +10---- 1 +--11-- 1 +----11 1 +.names N_N4095 n950_1 N_N3866 n953 n954 N_N4114 n1300_1 +10---- 1 +--11-- 1 +----11 1 +.names N_N4090 PRESET NDN3_3 NSr3_2 n1180 +101- 1 +10-1 1 +.names N_N4086 n950_1 N_N3716 n953 n954 N_N3715 n370 +10---- 1 +--11-- 1 +----11 1 +.names PRESET NSr5_8 NDN5_8 N_N4075 n1012 n990 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4197 n1013 n1012 +11 1 +.names N_N3999 N_N3838 n1479 n1019 n1042 n1032 n1013 +10---- 0 +--1111 0 +.names NSr5_4 NSr5_3 n1014 +10 1 +.names NSr5_3 NSr5_2 n1015_1 +10 1 +.names NSr5_7 NSr5_5 n1016 +10 1 +.names NSr5_8 NSr5_7 n1017 +10 1 +.names NSr5_5 NSr5_4 NDN3_8 NSr5_2 NSr3_9 NLak3_9 n1018 +10---- 0 +--1110 0 +.names n1030_1 n1027 n1024 n1022 n1020_1 n1019 +11111 1 +.names n1021 n1018 N_N4194 n1015_1 N_N4177 n1020_1 +0---- 0 +-01-- 0 +---11 0 +.names N_N4176 n1014 n1016 N_N3457 N_N4045 n1017 n1021 +11---- 0 +--11-- 0 +----11 0 +.names n1023 n1018 N_N4206 N_N4239 n1014 n1022 +0---- 0 +-01-- 0 +---11 0 +.names N_N3813 n1015_1 n1016 N_N3436 n1017 N_N3188 n1023 +11---- 0 +--11-- 0 +----11 0 +.names n1025_1 n1018 N_N4120 n1024 +11- 1 +1-0 1 +.names n1026 N_N4117 n1016 n1017 N_N4116 n1025_1 +0---- 0 +-11-- 0 +---11 0 +.names NSr5_3 N_N4119 NSr5_2 NSr5_4 N_N4118 n1026 +0--11 0 +110-- 0 +.names n1028 n1018 N_N4057 n1027 +11- 1 +1-0 1 +.names n1029 N_N3918 n1014 N_N3221 n1016 n1028 +0---- 0 +-11-- 0 +---11 0 +.names N_N3367 NSr5_8 NSr5_7 N_N3919 NSr5_3 NSr5_2 n1029 +110--- 0 +---110 0 +.names n1031 n1018 N_N4132 n1017 N_N3840 n1030_1 +0---- 0 +-01-- 0 +---11 0 +.names N_N3842 n1014 n1015_1 N_N3843 N_N3841 n1016 n1031 +11---- 0 +--11-- 0 +----11 0 +.names n1033 n1481 n1039 n1037 n1035_1 N_N3999 n1032 +111110 1 +.names n1034 n1018 N_N4165 N_N3711 n1016 n1033 +0---- 0 +-01-- 0 +---11 0 +.names N_N4099 n1014 N_N3868 n1015_1 n1017 N_N3424 n1034 +11---- 0 +--11-- 0 +----11 0 +.names n1036 n1018 N_N4220 n1015_1 N_N3924 n1035_1 +0---- 0 +-01-- 0 +---11 0 +.names N_N3923 n1014 n1016 N_N3922 n1017 N_N3921 n1036 +11---- 0 +--11-- 0 +----11 0 +.names n1038 n1018 N_N4237 n1014 N_N4208 n1037 +0---- 0 +-01-- 0 +---11 0 +.names N_N4209 n1015_1 n1016 N_N3433 N_N3659 n1017 n1038 +11---- 0 +--11-- 0 +----11 0 +.names n1040_1 n1018 N_N3906 n1039 +11- 1 +1-0 1 +.names n1041 N_N3304 n1016 n1017 N_N3303 n1040_1 +0---- 0 +-11-- 0 +---11 0 +.names NSr5_3 N_N3940 NSr5_2 NSr5_4 N_N3939 n1041 +0--11 0 +110-- 0 +.names n1043 n1018 N_N4179 N_N3871 n1014 n1042 +0---- 0 +-01-- 0 +---11 0 +.names N_N3872 n1015_1 n1016 N_N4030 N_N3870 n1017 n1043 +11---- 0 +--11-- 0 +----11 0 +.names PRESET NSr3_2 NDN3_3 N_N4056 Paport_5_5_ n1510_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4054 Paport_7_7_ n75 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N4047 n1047 n1315_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4145 n1013 n1047 +11 1 +.names PRESET NDN5_4 NSr5_4 N_N4045 n1012 n1000 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_7 NSr5_7 N_N4042 n1050_1 n1290 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3912 n1013 n1050_1 +11 1 +.names PRESET NDN5_7 NSr5_7 N_N4039 n1052 n965 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4227 n1013 n1052 +11 1 +.names n970_1 PRESET n1054 n1077 N_N4079 n935 +00--1 1 +1000- 1 +1011- 1 +.names n1072 n1073 n1076 n1075_1 n1074 n1055_1 n1054 +0011-- 1 +001--1 1 +00-1-1 1 +00--1- 1 +11---- 1 +1-000- 1 +1-0-00 1 +1--000 1 +.names n1067 n1069 n1068 n1070_1 n1071 n1056 n1055_1 +00-1-- 1 +00--00 1 +0-1--- 1 +.names n1062 n1064 n1066 n1065_1 n1057 n1063 n1056 +0000-- 1 +000-0- 1 +00-00- 1 +0----1 1 +.names n1061 n1058 N_N4057 n1005_1 N_N3793 n970_1 n1057 +00---- 0 +0-11-- 0 +0---11 0 +-011-- 0 +-0--11 0 +.names n1060_1 n1059 N_N4120 n1005_1 N_N3157 n970_1 n1058 +01---- 0 +0-11-- 0 +0---11 0 +-111-- 0 +-1--11 0 +.names n1005_1 n970_1 N_N3906 N_N3939 N_N3940 N_N3910 n1059 +1111-- 1 +11--11 1 +1-1-1- 1 +-1-1-1 1 +.names N_N4118 n970_1 N_N4119 n1005_1 n1060_1 +11-- 0 +--11 0 +.names N_N3918 n970_1 N_N3919 n1005_1 n1061 +11-- 0 +--11 0 +.names N_N3071 N_N3871 N_N3872 N_N4179 n1005_1 n970_1 n1062 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n1005_1 n970_1 N_N3868 N_N3776 N_N4165 N_N4099 n1063 +1111-- 1 +11--11 1 +1-1-1- 1 +-1-1-1 1 +.names N_N3776 N_N4099 N_N3868 N_N4165 n1005_1 n970_1 n1064 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names N_N3923 n970_1 n1005_1 N_N3924 n1065_1 +11-- 0 +--11 0 +.names N_N3143 n970_1 n1005_1 N_N4220 n1066 +11-- 0 +--11 0 +.names n1005_1 n970_1 N_N3843 N_N3069 N_N4132 N_N3842 n1067 +1111-- 1 +11--11 1 +1-1-1- 1 +-1-1-1 1 +.names N_N3069 N_N3842 N_N3843 N_N4132 n1005_1 n970_1 n1068 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n1005_1 n970_1 N_N3813 N_N3630 N_N4206 N_N4239 n1069 +1111-- 1 +11--11 1 +1-1-1- 1 +-1-1-1 1 +.names N_N3630 N_N4239 N_N3813 N_N4206 n1005_1 n970_1 n1070_1 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n1005_1 n970_1 N_N3872 N_N3071 N_N4179 N_N3871 n1071 +1111-- 1 +11--11 1 +1-1-1- 1 +-1-1-1 1 +.names N_N4176 n970_1 N_N4177 n1005_1 n1072 +11-- 0 +--11 0 +.names n1005_1 n970_1 N_N3808 N_N3311 N_N4070 N_N3807 n1073 +1111-- 1 +11--11 1 +1-1-1- 1 +-1-1-1 1 +.names N_N3311 N_N3807 N_N3808 N_N4070 n1005_1 n970_1 n1074 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names N_N3607 n970_1 n1005_1 N_N4242 n1075_1 +11-- 0 +--11 0 +.names N_N4252 n970_1 n1005_1 N_N3800 n1076 +11-- 0 +--11 0 +.names N_N4193 n970_1 n1005_1 N_N4194 n1077 +11-- 0 +--11 0 +.names PRESET NDN5_3 NSr5_3 N_N4030 n1079 n315 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3974 n1013 n1079 +11 1 +.names PRESET NDN5_5 NSr5_5 N_N4236 n1052 n1230 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr5_8 NDN5_8 N_N4024 n1082 n515 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3992 n1013 n1082 +11 1 +.names PRESET NSr5_8 NDN5_8 N_N4021 n1084 n530 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4018 n1013 n1084 +11 1 +.names PRESET NSr3_2 NDN3_3 N_N4057 Pdxport_2_2_ n580 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_2 NSr5_2 N_N3988 n1087 n980 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4083 n1013 n1087 +11 1 +.names n1005_1 PRESET n1089 n1066 N_N3981 n240 +00--1 1 +1000- 1 +1011- 1 +.names n1065_1 n1057 n1089 +01 1 +10 1 +.names PRESET NDN5_4 NSr5_4 N_N4116 n1091 n460 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4027 n1013 n1091 +11 1 +.names PRESET NDN5_7 NSr5_7 N_N3968 n1091 n1165_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4179 Pdxport_5_5_ n1400_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr5_8 NDN5_8 N_N3959 n1091 n1280_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr5_8 NDN5_8 N_N3957 n1096 n1305_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3996 n1013 n1096 +11 1 +.names n969 PRESET n992 n990_1 n1098 N_N3947 n760 +00---1 1 +10001- 1 +10010- 1 +10100- 1 +10111- 1 +.names n961 n974 n975_1 n1098 +01- 1 +0-1 1 +.names PRESET NSr3_2 NDN3_3 N_N4220 Pdxport_3_3_ n1380_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N3916 Paport_0_0_ n645 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4243 Paport_6_6_ n705 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4015 Paport_8_8_ n720 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3910 n1104 n750 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3965 n1013 n1104 +11 1 +.names PRESET NSr3_2 NDN3_3 N_N4120 Pdxport_1_1_ n1370_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4197 n1139 n1137 n1107 n1134 n145 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n1132 N_N3912 n1108 n1107 +10- 1 +1-1 1 +-01 1 +.names n1128 N_N3949 N_N4145 n1130_1 n1109 n1108 +100-- 1 +10-1- 1 +1-0-1 1 +1--11 1 +-00-1 1 +-0-11 1 +--01- 1 +.names n1126 N_N3974 N_N4083 n1483 n1110_1 n1109 +100-- 1 +10-1- 1 +1-0-1 1 +1--11 1 +-00-1 1 +-0-11 1 +--01- 1 +.names n1121 N_N3996 N_N4018 n1124 n1111 n1110_1 +100-- 1 +10-1- 1 +1-0-1 1 +1--11 1 +-00-1 1 +-0-11 1 +--01- 1 +.names n1115_1 N_N4027 N_N3992 n1118 n1112 n1111 +100-- 1 +10-1- 1 +1-0-0 1 +1--10 1 +-00-0 1 +-0-10 1 +--01- 1 +.names N_N3965 n1113 n1114 N_N3971 n1018 n1112 +10--- 1 +1-0-- 1 +1--10 1 +.names N_N3387 NSr5_7 NSr5_5 N_N3745 NSr5_4 NSr5_3 n1113 +110--- 0 +---110 0 +.names NSr5_8 N_N3906 NSr5_7 N_N3388 NSr5_3 NSr5_2 n1114 +110--- 0 +---110 0 +.names n1116 n1117 n1018 N_N3500 n1115_1 +111- 1 +11-0 1 +.names N_N4120 NSr5_8 NSr5_7 N_N3708 NSr5_3 NSr5_2 n1116 +110--- 0 +---110 0 +.names N_N3175 NSr5_7 NSr5_5 NSr5_4 N_N2989 NSr5_3 n1117 +110--- 0 +---110 0 +.names n1120_1 n1119 N_N4086 N_N3344 n1016 n1018 n1118 +1000-- 1 +100-0- 1 +10-0-1 1 +10--01 1 +.names N_N3346 NSr5_3 NSr5_2 n1119 +110 1 +.names N_N4057 NSr5_8 NSr5_7 N_N3345 NSr5_4 NSr5_3 n1120_1 +110--- 0 +---110 0 +.names n1122 n1018 N_N4224 n1121 +11- 1 +1-0 1 +.names n1123 N_N4223 n1015_1 N_N4220 n1017 n1122 +0---- 0 +-11-- 0 +---11 0 +.names N_N4221 NSr5_7 NSr5_5 NSr5_4 N_N4222 NSr5_3 n1123 +110--- 0 +---110 0 +.names n1125_1 n1018 N_N3890 n1016 N_N3323 n1124 +0---- 0 +-01-- 0 +---11 0 +.names N_N3691 n1014 n1015_1 N_N3324 N_N4165 n1017 n1125_1 +11---- 0 +--11-- 0 +----11 0 +.names n1127 n1018 N_N4183 n1014 N_N4181 n1126 +0---- 0 +-01-- 0 +---11 0 +.names N_N4182 n1015_1 n1016 N_N4180 N_N4179 n1017 n1127 +11---- 0 +--11-- 0 +----11 0 +.names n1129 n1018 N_N4136 n1017 N_N4132 n1128 +0---- 0 +-01-- 0 +---11 0 +.names N_N4134 n1014 N_N4135 n1015_1 N_N4133 n1016 n1129 +11---- 0 +--11-- 0 +----11 0 +.names n1131 n1018 N_N3810 n1014 N_N3426 n1130_1 +0---- 0 +-01-- 0 +---11 0 +.names N_N3294 n1015_1 n1016 N_N3293 N_N4242 n1017 n1131 +11---- 0 +--11-- 0 +----11 0 +.names n1133 n1018 N_N4140 n1017 N_N4070 n1132 +0---- 0 +-01-- 0 +---11 0 +.names N_N4072 n1014 N_N4073 n1015_1 N_N4071 n1016 n1133 +11---- 0 +--11-- 0 +----11 0 +.names n1136 PRESET N_N3460 n1013 N_N4214 n1135_1 n1134 +1----- 0 +-1---- 0 +--1100 0 +.names n1018 n1017 n1016 n1015_1 n1014 n1135_1 +10000 1 +.names N_N4214 N_N3462 N_N3575 n1136 +110 1 +.names n1138 n1018 N_N3470 n1014 N_N3468 n1137 +0---- 0 +-01-- 0 +---11 0 +.names N_N3469 n1015_1 N_N3473 n1016 N_N4194 n1017 n1138 +11---- 0 +--11-- 0 +----11 0 +.names n1136 PRESET n1139 +10 1 +.names n969 PRESET n1141 N_N3829 n1520_1 +00-1 1 +101- 1 +.names n987 n986 n979 n1141 +001 1 +010 1 +100 1 +111 1 +.names n969 PRESET n1143 N_N3826 n90 +00-1 1 +100- 1 +.names n989 n977 n976 n1143 +000 1 +011 1 +101 1 +110 1 +.names PRESET NSr5_8 NDN5_8 N_N3824 n1050_1 n1360_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N3818 Paport_9_9_ n95 +000-1 1 +01-1- 1 +0-11- 1 +.names n969 PRESET n1147 n975_1 N_N3815 n110 +00--1 1 +1000- 1 +1011- 1 +.names n974 n961 n1147 +00 1 +.names N_N3876 PRESET NDN3_3 NSr3_2 n520 +101- 1 +10-1 1 +.names N_N3971 n950_1 N_N3681 n953 n954 N_N3680 n345 +10---- 1 +--11-- 1 +----11 1 +.names PRESET NDN5_7 NSr5_7 N_N3799 n1082 n425 +000-1 1 +01-1- 1 +0-11- 1 +.names n969 PRESET n1152 N_N3796 n685 +00-1 1 +101- 1 +.names n968 N_N3971 N_N3796 n970_1 n969 n1152 +000-- 1 +00-0- 1 +0-0-0 1 +0--00 1 +11--1 1 +1-11- 1 +.names n969 PRESET n996 n1154 N_N3788 n130 +00--1 1 +1001- 1 +1010- 1 +.names n998 n960_1 n1154 +00 1 +11 1 +.names N_N3786 PRESET NDN3_3 NSr3_2 n410 +101- 1 +10-1 1 +.names PRESET NDN5_4 NSr5_4 N_N3870 n1079 n510 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET N_N3745 Preset_0_0_ PDN NLC1_2 NDN2_2 n80 +01---- 1 +0-1000 1 +.names N_N3741 PRESET NDN3_3 NSr3_2 n1105 +101- 1 +10-1 1 +.names N_N3992 n1139 n1118 n1160 n1134 n365 +0100- 1 +0111- 1 +1101- 1 +1110- 1 +1---1 1 +.names N_N4027 n1115_1 n1112 n1160 +10- 1 +1-1 1 +-01 1 +.names PRESET NDN5_5 NSr5_5 N_N4193 n1012 n1265_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4018 n1139 n1124 n1163 n1134 n340 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n1121 N_N3996 n1111 n1163 +10- 1 +1-1 1 +-01 1 +.names n1165 N_N3713 PRESET n970_1 n1515_1 +1--- 1 +-100 1 +.names n1167 n1166 n1076 n1075_1 n1055_1 n1165 +1000- 1 +100-0 1 +10-00 1 +1111- 1 +111-1 1 +11-11 1 +.names n1074 n1073 n1166 +00 1 +.names n970_1 PRESET n1167 +10 1 +.names PRESET NDN5_3 NSr5_3 N_N3711 n1084 n1075 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N3882 Paport_10_10_ n830 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3793 n1082 n770 +000-1 1 +01-1- 1 +0-11- 1 +.names n969 PRESET n984 n1172 N_N3684 n1505_1 +00--1 1 +1001- 1 +1010- 1 +.names n983 n982 n1172 +00 1 +11 1 +.names N_N4252 n950_1 N_N3533 n953 N_N3791 n954 n1040 +10---- 1 +--11-- 1 +----11 1 +.names N_N3843 n950_1 N_N3105 n953 N_N3489 n954 n150 +10---- 1 +--11-- 1 +----11 1 +.names n970_1 PRESET n1176 n1177 N_N3743 n650 +00--1 1 +1000- 1 +1011- 1 +.names n1066 n1065_1 n1057 n1176 +11- 1 +1-1 1 +-11 1 +.names n1064 n1063 n1177 +00 1 +.names n970_1 PRESET n1179 n1180_1 N_N3774 n670 +00--1 1 +1000- 1 +1011- 1 +.names n1071 n1056 n1179 +00 1 +.names n1070_1 n1069 n1180_1 +00 1 +.names PRESET NDN5_2 NSr5_2 N_N3663 n1052 n955 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N4117 n1091 n260 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N3659 n1052 n1035 +000-1 1 +01-1- 1 +0-11- 1 +.names n970_1 PRESET n1076 n1075_1 n1055_1 N_N3791 n695 +00---1 1 +10000- 1 +10011- 1 +10101- 1 +10110- 1 +.names PRESET NDN5_3 NSr5_3 N_N3922 n1096 n300 +000-1 1 +01-1- 1 +0-11- 1 +.names n1005_1 PRESET n1187 n1188 N_N3761 n270 +00--1 1 +1000- 1 +1011- 1 +.names n1063 n1176 n1064 n1187 +01- 1 +0-1 1 +.names n1062 n1071 n1188 +00 1 +.names N_N3634 PRESET NDN3_3 NSr3_2 n1025 +101- 1 +10-1 1 +.names NSr5_8 PRESET n1485_1 +00 1 +.names n951 NEN5_9 NSr5_8 n1500_1 +11- 1 +1-0 1 +.names n970_1 PRESET n1193 n1061 N_N3709 n615 +00--1 1 +1000- 1 +1011- 1 +.names n1058 N_N3793 N_N4057 n1005_1 n970_1 n1193 +000-- 1 +00-0- 1 +0-0-0 1 +0--00 1 +11--1 1 +1-11- 1 +.names PRESET NDN5_2 NSr5_2 N_N4071 n1050_1 n280 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3776 n1084 n810 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr5_8 NDN5_8 N_N3612 n1052 n930 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3949 n1139 n1128 n1109 n1134 n1065 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names N_N4212 n1139 n1203 n1199 n1202 n1022 n380 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names PRESET n1201 n1200_1 n1013 n1199 +000- 1 +00-1 1 +.names N_N3578 N_N3460 n1013 n1135_1 n1200_1 +00-- 1 +0-00 1 +.names N_N3460 n1136 n1013 n1135_1 N_N3578 N_N4214 n1201 +111--- 1 +11-1-- 1 +1-10-0 1 +-1--1- 1 +.names n1013 PRESET N_N3578 N_N3460 N_N4214 n1202 +000-- 1 +10-10 1 +.names n1204 N_N4060 N_N4036 n1203 +110 1 +.names N_N4171 N_N4004 N_N4126 N_N3961 n1204 +0000 1 +.names N_N4171 n1139 n1206 n1199 n1202 n1033 n415 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names n1207 N_N4004 n1206 +10 1 +.names N_N4060 N_N4126 N_N3961 n1207 +100 1 +.names PRESET NSr3_2 NDN3_3 N_N3733 Paport_2_2_ n665 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3918 n950_1 N_N3356 n953 n954 N_N3709 n855 +10---- 1 +--11-- 1 +----11 1 +.names n1211 N_N3939 n950_1 n805 +0-- 1 +-10 1 +.names PRESET NLD3_9 N_N3677 NDN3_3 N_N3741 NDN3_8 n1211 +011--- 0 +0--110 0 +.names n1213 N_N4224 n950_1 n1140_1 +0-- 1 +-10 1 +.names PRESET NLD3_9 N_N3442 NDN3_3 N_N4106 NDN3_8 n1213 +011--- 0 +0--110 0 +.names PRESET NSr5_8 NDN5_8 N_N3585 n1215 n1345_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3949 n1013 n1215 +11 1 +.names N_N3580 PRESET NDN3_3 NSr3_2 n165 +101- 1 +10-1 1 +.names N_N3890 n950_1 N_N3751 n953 n954 N_N3750 n395 +10---- 1 +--11-- 1 +----11 1 +.names n1005_1 PRESET n1193 n1061 N_N3794 n950 +00--1 1 +1000- 1 +1011- 1 +.names PRESET NSr5_8 NDN5_8 N_N3625 n1104 n495 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N3921 n1096 n490 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N3574 Paport_4_4_ n690 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4205 Paport_11_11_ n890 +000-1 1 +01-1- 1 +0-11- 1 +.names n1224 N_N4118 n950_1 n160 +0-- 1 +-10 1 +.names PRESET NLD3_9 N_N3179 NDN3_3 N_N4232 NDN3_8 n1224 +011--- 0 +0--110 0 +.names N_N4209 n950_1 N_N3373 n953 n954 N_N3336 n1355_1 +10---- 1 +--11-- 1 +----11 1 +.names N_N3500 n950_1 N_N3331 n953 N_N3464 n954 n1120 +10---- 1 +--11-- 1 +----11 1 +.names n1005_1 PRESET n1228 n1229 N_N3489 n310 +00--1 1 +1000- 1 +1011- 1 +.names n1069 n1179 n1070_1 n1228 +01- 1 +0-1 1 +.names n1068 n1067 n1229 +00 1 +.names n1231 N_N3513 PRESET n1005_1 n325 +1--- 1 +-100 1 +.names n1232 n1166 n1076 n1075_1 n1055_1 n1231 +1000- 1 +100-0 1 +10-00 1 +1111- 1 +111-1 1 +11-11 1 +.names n1005_1 PRESET n1232 +10 1 +.names PRESET NDN5_2 NSr5_2 N_N4221 n1096 n195 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4206 Pdxport_6_6_ n620 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_7 NSr5_7 N_N3482 n1012 n1005 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4176 n950_1 N_N4080 n953 n954 N_N4079 n1340_1 +10---- 1 +--11-- 1 +----11 1 +.names n970_1 PRESET n1089 n1066 N_N3475 n1405_1 +00--1 1 +1000- 1 +1011- 1 +.names PRESET NDN5_2 NSr5_2 N_N3473 n1012 n885 +000-1 1 +01-1- 1 +0-11- 1 +.names NDN5_9 n951 n1440_1 +11 1 +.names n951 NEN5_9 NDN5_9 n1495_1 +11- 1 +1-1 1 +.names PRESET NDN5_7 NSr5_7 N_N3736 n1047 n505 +000-1 1 +01-1- 1 +0-11- 1 +.names n1005_1 PRESET n1059 n1243 N_N3535 n210 +00--1 1 +1001- 1 +1010- 1 +.names n1060_1 N_N3157 N_N4120 n1005_1 n970_1 n1243 +000-- 1 +00-0- 1 +0-0-0 1 +0--00 1 +11--1 1 +1-11- 1 +.names N_N3912 n1139 n1132 n1108 n1134 n1045 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n1167 n1247 n1072 n1077 n1246 n1248 n860 +1011-- 1 +101-1- 1 +10-11- 1 +1100-- 1 +110-0- 1 +11-00- 1 +-----1 1 +.names n1073 n1076 n1075_1 n1055_1 n1074 n1246 +011-- 1 +01-1- 1 +0-11- 1 +0---1 1 +.names n970_1 n1005_1 N_N4209 N_N4236 N_N4237 N_N4208 n1247 +010-1- 0 +011-0- 0 +10-0-1 0 +10-1-0 0 +1-01-0 0 +1--001 0 +-10-10 0 +-1100- 0 +.names N_N4158 PRESET n970_1 n1248 +100 1 +.names PRESET NDN5_3 NSr5_3 N_N3436 n1087 n1090 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N3841 n1215 n335 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N3424 n1084 n1275 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3417 PRESET NDN3_3 NSr3_2 n850 +101- 1 +10-1 1 +.names N_N3842 n950_1 N_N3196 n953 N_N3212 n954 n245 +10---- 1 +--11-- 1 +----11 1 +.names N_N3924 n950_1 N_N3250 n953 n954 N_N3981 n105 +10---- 1 +--11-- 1 +----11 1 +.names n1256 N_N4119 n950_1 n85 +0-- 1 +-10 1 +.names PRESET NLD3_9 N_N3535 NDN3_3 N_N3580 NDN3_8 n1256 +011--- 0 +0--110 0 +.names N_N3517 PRESET NDN3_3 NSr3_2 n1310_1 +101- 1 +10-1 1 +.names N_N3681 PRESET NDN3_3 NSr3_2 n445 +101- 1 +10-1 1 +.names N_N3716 PRESET NDN3_3 NSr3_2 n480 +101- 1 +10-1 1 +.names N_N3373 PRESET NDN3_3 NSr3_2 n610 +101- 1 +10-1 1 +.names PRESET NDN5_4 NSr5_4 N_N3367 n1082 n1240_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3533 PRESET NDN3_3 NSr3_2 n1205 +101- 1 +10-1 1 +.names N_N3808 n950_1 N_N3062 n953 n954 N_N3513 n180 +10---- 1 +--11-- 1 +----11 1 +.names N_N3340 n1139 n1265 n1199 n1202 n1037 n455 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names n1266 N_N3283 N_N3369 N_N4246 n1265 +1000 1 +.names n1267 N_N4093 n1266 +10 1 +.names n1203 N_N4212 n1267 +10 1 +.names n1232 n1247 n1072 n1077 n1246 n1269 n1210 +1011-- 1 +101-1- 1 +10-11- 1 +1100-- 1 +110-0- 1 +11-00- 1 +-----1 1 +.names N_N3336 PRESET n1005_1 n1269 +100 1 +.names PRESET NDN5_2 NSr5_2 N_N4180 n1079 n225 +000-1 1 +01-1- 1 +0-11- 1 +.names n1005_1 PRESET n1076 n1075_1 n1055_1 N_N3908 n1070 +00---1 1 +10000- 1 +10011- 1 +10101- 1 +10110- 1 +.names n1005_1 PRESET n1054 n1077 N_N3884 n1235 +00--1 1 +1000- 1 +1011- 1 +.names PRESET NDN5_2 NSr5_2 N_N3323 n1084 n925 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3393 PRESET NDN3_3 NSr3_2 n1285 +101- 1 +10-1 1 +.names N_N3810 n950_1 N_N3932 n953 n954 N_N3931 n465 +10---- 1 +--11-- 1 +----11 1 +.names N_N3844 n950_1 N_N3876 n953 N_N3875 n954 n430 +10---- 1 +--11-- 1 +----11 1 +.names PRESET NDN5_5 NSr5_5 N_N3311 n1050_1 n230 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N3778 Paport_3_3_ n1455_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4126 n1139 N_N4060 N_N3961 n1280 n1199 n440 +0110-- 1 +110--- 1 +11-1-- 1 +1----1 1 +----1- 1 +.names n1202 n1027 n1280 +10 1 +.names N_N4246 n1139 n1266 n1199 n1202 n1479 n355 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names n969 PRESET n993 n1283 N_N3274 n880 +00--1 1 +1001- 1 +1010- 1 +.names n997 n998 n996 n960_1 n1283 +010- 1 +01-0 1 +0-00 1 +101- 1 +10-1 1 +1-11 1 +.names n969 PRESET n1286 n1285_1 N_N3480 n700 +00--1 1 +1001- 1 +1010- 1 +.names n984 n983 n982 n1285_1 +11- 1 +1-0 1 +-10 1 +.names n966 n981 n980_1 n1286 +000 1 +011 1 +101 1 +110 1 +.names n1288 N_N3940 n950_1 n710 +0-- 1 +-10 1 +.names PRESET NLD3_9 N_N4111 NDN3_3 N_N4218 NDN3_8 n1288 +011--- 0 +0--110 0 +.names PRESET NSr5_8 NDN5_8 N_N3700 n1087 n550 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3250 PRESET NDN3_3 NSr3_2 n190 +101- 1 +10-1 1 +.names N_N3248 PRESET NDN3_3 NSr3_2 n220 +101- 1 +10-1 1 +.names n970_1 PRESET n992 n990_1 n1098 N_N3931 n1080 +00---1 1 +10001- 1 +10010- 1 +10100- 1 +10111- 1 +.names n969 PRESET n985_1 n978 n1294 N_N3509 n715 +00---1 1 +10001- 1 +10010- 1 +10100- 1 +10111- 1 +.names n986 n987 n979 n1294 +10- 1 +1-1 1 +-01 1 +.names n969 PRESET n1296 n1297 N_N3529 n740 +00--1 1 +1000- 1 +1011- 1 +.names n989 n977 n976 n1296 +11- 1 +1-0 1 +-10 1 +.names n988 n971 n962 n1297 +000 1 +011 1 +101 1 +110 1 +.names NSr5_7 PRESET n1480_1 +00 1 +.names n951 NSr5_7 NDN5_10 n405 +10- 1 +1-1 1 +.names n1301 N_N3923 n950_1 n185 +0-- 1 +-10 1 +.names PRESET NLD3_9 N_N3475 NDN3_3 N_N4230 NDN3_8 n1301 +011--- 0 +0--110 0 +.names N_N4145 n1139 n1130_1 n1303 n1134 n295 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n1128 N_N3949 n1109 n1303 +10- 1 +1-1 1 +-01 1 +.names n970_1 PRESET n984 n1172 N_N3464 n205 +00--1 1 +1001- 1 +1010- 1 +.names n970_1 PRESET n1141 N_N3442 n235 +00-1 1 +101- 1 +.names n970_1 PRESET n1187 n1188 N_N3214 n1425_1 +00--1 1 +1000- 1 +1011- 1 +.names n970_1 PRESET n1228 n1229 N_N3212 n1465_1 +00--1 1 +1000- 1 +1011- 1 +.names PRESET NDN5_3 NSr5_3 N_N3304 n1104 n1015 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N3221 n1082 n1055 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_7 NSr5_7 N_N3205 n1096 n1190_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_7 NSr5_7 N_N3203 n1079 n1225_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3800 n950_1 N_N3634 n953 N_N3908 n954 n840 +10---- 1 +--11-- 1 +----11 1 +.names N_N3996 n1139 n1121 n1111 n1134 n1125 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names PRESET NSr3_2 NDN3_3 N_N4132 Pdxport_7_7_ n1410_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4070 Pdxport_9_9_ n1430_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4237 Pdxport_11_11_ n845 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4136 n950_1 N_N3517 n953 N_N3516 n954 n1195 +10---- 1 +--11-- 1 +----11 1 +.names N_N4183 n950_1 N_N3393 n953 N_N3420 n954 n1170_1 +10---- 1 +--11-- 1 +----11 1 +.names N_N3932 PRESET NDN3_3 NSr3_2 n535 +101- 1 +10-1 1 +.names n970_1 PRESET n1059 n1243 N_N3179 n1395_1 +00--1 1 +1001- 1 +1010- 1 +.names PRESET NDN5_2 NSr5_2 N_N3293 n1047 n1030 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_2 NSr5_2 N_N3175 n1091 n170 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N3806 n1050_1 n360 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N3433 n1052 n985 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3369 n1139 n1326 n1199 n1202 n1481 n1110 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names n1266 N_N4246 n1326 +10 1 +.names PRESET NSr3_2 NDN3_3 N_N3797 Paport_1_1_ n1420_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_7 NSr5_7 N_N3626 n1104 n385 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3813 n950_1 N_N3280 n953 n954 N_N3862 n780 +10---- 1 +--11-- 1 +----11 1 +.names N_N3196 PRESET NDN3_3 NSr3_2 n435 +101- 1 +10-1 1 +.names N_N4093 n1139 n1267 n1199 n1202 n1030_1 n1135 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names PRESET NSr3_2 NDN3_3 N_N4165 Pdxport_4_4_ n600 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_2 NSr5_2 N_N3387 n1104 n815 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N3164 n1047 n1115 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3143 n1096 n140 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N3840 n1215 n525 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N3805 n1050_1 n545 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4208 n950_1 N_N4159 n953 n954 N_N4158 n1365_1 +10---- 1 +--11-- 1 +----11 1 +.names N_N3807 n950_1 N_N3235 n953 n954 N_N3713 n290 +10---- 1 +--11-- 1 +----11 1 +.names N_N3872 n950_1 N_N3248 n953 n954 N_N3761 n125 +10---- 1 +--11-- 1 +----11 1 +.names n1005_1 PRESET n1179 n1180_1 N_N3862 n1050 +00--1 1 +1000- 1 +1011- 1 +.names N_N3751 PRESET NDN3_3 NSr3_2 n500 +101- 1 +10-1 1 +.names n970_1 PRESET n1296 n1297 N_N3875 n1060 +00--1 1 +1000- 1 +1011- 1 +.names n1345 N_N3965 n1134 n390 +1-- 1 +-11 1 +.names n1139 N_N3965 n1114 n1113 N_N3971 n1018 n1345 +100--- 1 +10-0-- 1 +10--10 1 +11110- 1 +1111-1 1 +.names N_N3105 PRESET NDN3_3 NSr3_2 n250 +101- 1 +10-1 1 +.names PRESET NDN5_2 NSr5_2 N_N3344 n1082 n870 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_3 NSr5_3 N_N3457 n1012 n940 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_4 NSr5_4 N_N3303 n1104 n1200 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4036 n1199 n1202 n1042 n1139 n1351 n1160_1 +11---- 1 +--10-- 1 +----10 1 +.names N_N4036 N_N4060 n1204 n1351 +00- 1 +0-0 1 +111 1 +.names N_N4004 n1139 n1207 n1199 n1202 n1035_1 n1185 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names N_N4177 n950_1 N_N3011 n953 n954 N_N3884 n1330_1 +10---- 1 +--11-- 1 +----11 1 +.names n1005_1 PRESET n1176 n1177 N_N3832 n1010 +00--1 1 +1000- 1 +1011- 1 +.names PRESET NDN5_4 NSr5_4 N_N3188 n1087 n1295 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3071 n1079 n175 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3069 n1215 n200 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N4159 PRESET NDN3_3 NSr3_2 n635 +101- 1 +10-1 1 +.names N_N3331 PRESET NDN3_3 NSr3_2 n1220_1 +101- 1 +10-1 1 +.names n1361 n1202 n1020_1 N_N3283 PRESET n1362 n475 +0----- 1 +-10--- 1 +---100 1 +.names n1265 n1139 N_N3283 n1134 n1200_1 n1361 +11--- 0 +--110 0 +.names n1136 n1013 n1200_1 n1326 N_N3369 n1362 +1--0- 0 +1---1 0 +-11-- 0 +.names PRESET NSr3_2 NDN3_3 N_N4242 Pdxport_8_8_ n655 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NSr3_2 NDN3_3 N_N4194 Pdxport_10_10_ n820 +000-1 1 +01-1- 1 +0-11- 1 +.names n970_1 PRESET n996 n1154 N_N3540 n320 +00--1 1 +1001- 1 +1010- 1 +.names PRESET NDN5_7 NSr5_7 N_N3679 n1084 n450 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_7 NSr5_7 N_N3701 n1087 n485 +000-1 1 +01-1- 1 +0-11- 1 +.names n970_1 PRESET n985_1 n978 n1294 N_N3750 n1020 +00---1 1 +10001- 1 +10010- 1 +10100- 1 +10111- 1 +.names PRESET N_N3346 Preset_0_0_ PDN NLC1_2 NDN2_2 n590 +01---- 1 +0-1000 1 +.names N_N3470 n950_1 N_N3822 n953 n954 N_N3821 n1270_1 +10---- 1 +--11-- 1 +----11 1 +.names PRESET NDN5_7 NSr5_7 N_N3100 n1215 n1260_1 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3974 n1139 n1126 n1110_1 n1134 n1095 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names PRESET NSr5_8 NDN5_8 N_N3735 n1047 n555 +000-1 1 +01-1- 1 +0-11- 1 +.names n970_1 PRESET n993 n1283 N_N3821 n825 +00--1 1 +1001- 1 +1010- 1 +.names N_N4080 PRESET NDN3_3 NSr3_2 n605 +101- 1 +10-1 1 +.names N_N3062 PRESET NDN3_3 NSr3_2 n275 +101- 1 +10-1 1 +.names n970_1 PRESET n1152 N_N3680 n900 +00-1 1 +101- 1 +.names n970_1 PRESET n1286 n1285_1 N_N3715 n960 +00--1 1 +1001- 1 +1010- 1 +.names N_N3822 PRESET NDN3_3 NSr3_2 n775 +101- 1 +10-1 1 +.names PRESET NSr3_2 NDN3_3 N_N3906 Pdxport_0_0_ n570 +000-1 1 +01-1- 1 +0-11- 1 +.names n970_1 PRESET n1004 N_N3677 n595 +00-1 1 +101- 1 +.names PRESET NDN5_2 NSr5_2 N_N4133 n1215 n255 +000-1 1 +01-1- 1 +0-11- 1 +.names n970_1 PRESET n1147 n975_1 N_N3516 n305 +00--1 1 +1000- 1 +1011- 1 +.names PRESET N_N2989 Preset_0_0_ PDN NLC1_2 NDN2_2 n725 +01---- 1 +0-1000 1 +.names N_N3262 PRESET NDN3_3 NSr3_2 n910 +101- 1 +10-1 1 +.names N_N3280 PRESET NDN3_3 NSr3_2 n970 +101- 1 +10-1 1 +.names N_N4027 n1139 n1115_1 n1112 n1134 n1145_1 +0100- 1 +0111- 1 +1101- 1 +1110- 1 +1---1 1 +.names N_N3356 PRESET NDN3_3 NSr3_2 n1130 +101- 1 +10-1 1 +.names N_N3384 PRESET NDN3_3 NSr3_2 n1155_1 +101- 1 +10-1 1 +.names PRESET NSr5_8 NDN5_8 N_N3081 n1079 n1320_1 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3630 n1087 n865 +000-1 1 +01-1- 1 +0-11- 1 +.names PRESET NDN5_5 NSr5_5 N_N3607 n1047 n920 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3235 PRESET NDN3_3 NSr3_2 n470 +101- 1 +10-1 1 +.names n970_1 PRESET n1143 N_N3420 n265 +00-1 1 +100- 1 +.names PRESET NDN5_5 NSr5_5 N_N3157 n1091 n120 +000-1 1 +01-1- 1 +0-11- 1 +.names N_N3011 PRESET NDN3_3 NSr3_2 n585 +101- 1 +10-1 1 +.names N_N3961 n1139 N_N4060 n1199 n1202 n1024 n1215_1 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names N_N4083 n1139 n1483 n1399 n1134 n330 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n1126 N_N3974 n1110_1 n1399 +10- 1 +1-1 1 +-01 1 +.names N_N3541 PRESET NDN3_3 NSr3_2 n1325_1 +101- 1 +10-1 1 +.names N_N3866 PRESET NDN3_3 NSr3_2 n795 +101- 1 +10-1 1 +.names N_N3868 n950_1 N_N3262 n953 n954 N_N3832 n755 +10---- 1 +--11-- 1 +----11 1 +.names N_N3919 n950_1 N_N3417 n953 n954 N_N3794 n730 +10---- 1 +--11-- 1 +----11 1 +.names PRESET N_N3388 Preset_0_0_ PDN NLC1_2 NDN2_2 n575 +01---- 1 +0-1000 1 +.names N_N3871 n950_1 N_N3786 n953 N_N3214 n954 n215 +10---- 1 +--11-- 1 +----11 1 +.names PRESET PDN n540 +00 1 +.names n540 NSr3_2 n1408 n1530_1 +0-- 1 +-10 1 +.names Pready_0_0_ NLC1_2 NLak3_2 PDN N_N3998 Preset_0_0_ n1408 +1000-0 1 +11001- 1 +.names n951 NSr5_2 NDN3_8 NSr3_9 NAK5_2 NLak3_9 n1535_1 +10---- 0 +1-1110 0 +.names n951 NSr5_3 NAK5_2 NSr5_2 n1540_1 +10-- 0 +1-10 0 +.names n1413 n1412 n1545_1 +10 0 +.names N_N3462 n1485 n1412 +10 1 +.names n1414 PRESET n1413 +10 1 +.names N_N3460 n1013 n1135_1 n1414 +11- 1 +1-1 1 +.names n1413 n1135_1 n1412 n1550_1 +100 0 +.names n951 NSr5_4 NAK5_2 NSr5_3 n1555_1 +10-- 0 +1-10 0 +.names n540 NSr3_9 n1418 NDN3_8 n1560_1 +10-- 0 +1-11 0 +.names NLD3_9 N_N3336 N_N4205 n1419 n1418 +110- 1 +11-0 1 +1-00 1 +.names N_N3884 N_N3882 N_N3818 N_N3513 n1420 n1419 +01--- 1 +0-10- 1 +0---1 1 +-110- 1 +-1--1 1 +.names N_N3908 N_N4015 n1421 N_N3513 N_N3818 n1420 +10--- 0 +1-1-- 0 +-01-- 0 +---10 0 +.names N_N3862 N_N3489 N_N4243 N_N4054 n1422 n1421 +110-- 1 +11--1 1 +1-00- 1 +1--01 1 +-10-1 1 +-1-0- 1 +--001 1 +.names N_N3761 N_N4056 N_N3832 N_N3574 n1423 n1422 +10--- 1 +1-10- 1 +1---1 1 +-010- 1 +-0--1 1 +.names N_N3778 N_N3981 n1424 N_N3574 N_N3832 n1423 +10--- 0 +1-1-- 0 +-01-- 0 +---10 0 +.names N_N3916 N_N3797 N_N4111 N_N3794 N_N3535 N_N3733 n1424 +1100-- 1 +110--1 1 +1-000- 1 +1-0-01 1 +-1-00- 1 +-1--01 1 +---0-1 1 +.names n951 NSr5_5 NAK5_2 NSr5_4 n1565_1 +10-- 0 +1-10 0 +.names n951 NSr5_7 NAK5_2 NSr5_5 n1570_1 +10-- 0 +1-10 0 +.names NLD3_9 n1485_1 NAK5_2 n1480_1 n1575_1 +01-- 0 +0-11 0 +.names PRESET NLC1_2 PDN N_N3998 Preset_0_0_ n1580_1 +000-1 0 +01-0- 0 +0-10- 0 +.names N_N4227 PRESET n1136 n1430 N_N4214 n1433 n285 +0010-- 1 +100-1- 1 +100--0 1 +10-11- 1 +10-1-0 1 +.names n1431 N_N3912 N_N4197 n1132 n1137 n1108 n1430 +0110-- 1 +011--0 1 +01-00- 1 +01--00 1 +0-10-0 1 +0-1-0- 1 +0--000 1 +1001-- 1 +100--1 1 +10-11- 1 +10--11 1 +1-01-1 1 +1-0-1- 1 +1--111 1 +.names n1432 n1018 N_N4095 n1016 N_N3663 n1431 +0---- 0 +-01-- 0 +---11 0 +.names N_N3445 n1014 N_N3905 n1015_1 N_N4237 n1017 n1432 +11---- 0 +--11-- 0 +----11 0 +.names N_N3460 n1013 n1135_1 n1433 +110 1 +.names n1413 n1433 N_N3999 n1385_1 +11- 1 +1-1 1 +.names PRESET N_N4222 Preset_0_0_ NLC1_2 NDN2_2 PDN n745 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N3905 Preset_0_0_ NLC1_2 PDN NDN2_2 n1100 +1----- 0 +-0---- 0 +--1000 0 +.names NGFDN_3 PRESET NDN3_3 NDN3_8 n1350_1 +001- 1 +00-1 1 +.names NSr5_4 PRESET n1460_1 +00 1 +.names PRESET N_N3708 Preset_0_0_ NLC1_2 NDN2_2 PDN n1375_1 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N3691 Preset_0_0_ NLC1_2 NDN2_2 PDN n115 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET n1414 n640 +00 1 +.names n540 NGFDN_3 Preset_0_0_ NLC1_2 n63 +11-- 1 +1-10 1 +.names NGFDN_3 PRESET NDN3_3 NSr3_2 n1335_1 +001- 1 +00-0 1 +.names NDN2_2 PRESET PDN Preset_0_0_ NLC1_2 n1250 +101-- 1 +10-0- 1 +10--1 1 +.names n1418 PRESET n565 +10 1 +.names PRESET n1433 N_N3838 n905 +01- 1 +0-1 1 +.names PRESET N_N3426 Preset_0_0_ NLC1_2 NDN2_2 PDN n155 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N4181 Preset_0_0_ NLC1_2 NDN2_2 PDN n765 +1----- 0 +-0---- 0 +--1000 0 +.names N_N3578 n1413 n735 +11 1 +.names PRESET N_N3375 Preset_0_0_ NLC1_2 NDN2_2 PDN n135 +1----- 0 +-0---- 0 +--1000 0 +.names NSr5_5 PRESET n1470_1 +00 1 +.names PRESET N_N4073 Preset_0_0_ NLC1_2 NDN2_2 PDN n1490_1 +1----- 0 +-0---- 0 +--1000 0 +.names n1412 PRESET n1433 N_N4214 n675 +101- 1 +10-1 1 +.names n1485 PRESET n630 +10 1 +.names PRESET N_N4223 Preset_0_0_ NLC1_2 NDN2_2 PDN n1390_1 +1----- 0 +-0---- 0 +--1000 0 +.names NDN1_4 n540 n1150_1 +11 1 +.names NDN3_11 NGFDN_3 PRESET n400 +100 1 +.names PRESET N_N4072 Preset_0_0_ NLC1_2 NDN2_2 PDN n875 +1----- 0 +-0---- 0 +--1000 0 +.names NSr5_2 PRESET n1445_1 +00 1 +.names PRESET N_N4134 Preset_0_0_ NLC1_2 NDN2_2 PDN n790 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N3445 Preset_0_0_ NLC1_2 PDN NDN2_2 n945 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N3324 Preset_0_0_ NLC1_2 NDN2_2 PDN n625 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N3345 Preset_0_0_ NLC1_2 NDN2_2 PDN n100 +1----- 0 +-0---- 0 +--1000 0 +.names NDN5_16 n951 n420 +11 1 +.names NSr5_3 PRESET n1450_1 +00 1 +.names PRESET N_N3468 Preset_0_0_ NLC1_2 NDN2_2 PDN n995 +1----- 0 +-0---- 0 +--1000 0 +.names n951 NDN5_6 NDN3_8 NSr3_9 NLak3_9 n1475_1 +11--- 1 +1-110 1 +.names PRESET N_N3469 Preset_0_0_ NLC1_2 NDN2_2 PDN n1085 +1----- 0 +-0---- 0 +--1000 0 +.names NSr3_2 n1408 PRESET n560 +110 1 +.names PRESET N_N3312 Preset_0_0_ NLC1_2 NDN2_2 PDN n660 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N3294 Preset_0_0_ NLC1_2 NDN2_2 PDN n680 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N4182 Preset_0_0_ NLC1_2 NDN2_2 PDN n1415_1 +1----- 0 +-0---- 0 +--1000 0 +.names PRESET N_N4135 Preset_0_0_ NLC1_2 NDN2_2 PDN n1435_1 +1----- 0 +-0---- 0 +--1000 0 +.names N_N4060 n1199 n1202 n1039 n1139 n1525_1 +01--- 0 +1---1 0 +--10- 0 +.names NGFDN_3 NSr3_9 PRESET n1175_1 +000 1 +.names PRESET Pover_0_0_ NGFDN_3 NSr3_9 NDN3_11 n71 +010-- 1 +01--1 1 +0-00- 1 +.names PRESET Pnext_0_0_ NLD3_9 NDN5_9 NDN5_16 n67 +010-- 1 +01--1 1 +0-01- 1 +.names n1016 N_N3164 N_N4242 n1018 N_N4047 n1017 n1478 +11---- 0 +--10-- 0 +----11 0 +.names NSr5_3 n1478 NSr5_2 N_N3800 N_N4252 NSr5_4 n1479 +0---11 0 +1-01-- 0 +-0---- 0 +.names n1016 N_N3806 N_N4070 n1018 N_N3805 n1017 n1480 +11---- 0 +--10-- 0 +----11 0 +.names NSr5_3 n1480 NSr5_2 N_N3808 N_N3807 NSr5_4 n1481 +0---11 0 +1-01-- 0 +-0---- 0 +.names N_N3844 n1018 N_N4206 n1017 n1016 N_N3988 n1482 +10---- 0 +--11-- 0 +----11 0 +.names NSr5_3 n1482 NSr5_2 N_N3312 N_N3375 NSr5_4 n1483 +0---11 0 +1-01-- 0 +-0---- 0 +.names N_N3283 N_N3369 N_N4246 N_N4093 N_N3340 N_N4036 n1484 +000000 1 +.names n1204 n1136 n1484 N_N4060 N_N4212 n1485 +11100 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v b/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v new file mode 100644 index 000000000..b576b8fb5 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v @@ -0,0 +1,2329 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module diffeq(clock, PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_, Pdxport_3_3_, Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_, Pdxport_8_8_, Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_, Paport_0_0_, Paport_1_1_, Paport_2_2_, Paport_3_3_, Paport_4_4_, Paport_5_5_, Paport_6_6_, Paport_7_7_, Paport_8_8_, Paport_9_9_, Paport_10_10_, Paport_11_11_, Preset_0_0_, Pready_0_0_, PDN, Pnext_0_0_, Pover_0_0_); + (* init = 1'h0 *) + reg NAK5_2 = 1'h0; + (* init = 1'h0 *) + reg NDN1_4 = 1'h0; + (* init = 1'h0 *) + reg NDN2_2 = 1'h0; + (* init = 1'h0 *) + reg NDN3_11 = 1'h0; + (* init = 1'h0 *) + reg NDN3_3 = 1'h0; + (* init = 1'h0 *) + reg NDN3_8 = 1'h0; + (* init = 1'h0 *) + reg NDN5_10 = 1'h0; + (* init = 1'h0 *) + reg NDN5_16 = 1'h0; + (* init = 1'h0 *) + reg NDN5_2 = 1'h0; + (* init = 1'h0 *) + reg NDN5_3 = 1'h0; + (* init = 1'h0 *) + reg NDN5_4 = 1'h0; + (* init = 1'h0 *) + reg NDN5_5 = 1'h0; + (* init = 1'h0 *) + reg NDN5_6 = 1'h0; + (* init = 1'h0 *) + reg NDN5_7 = 1'h0; + (* init = 1'h0 *) + reg NDN5_8 = 1'h0; + (* init = 1'h0 *) + reg NDN5_9 = 1'h0; + (* init = 1'h0 *) + reg NEN5_9 = 1'h0; + (* init = 1'h0 *) + reg NGFDN_3 = 1'h0; + (* init = 1'h0 *) + reg NLC1_2 = 1'h0; + (* init = 1'h0 *) + reg NLD3_9 = 1'h0; + (* init = 1'h0 *) + reg NLak3_2 = 1'h0; + (* init = 1'h0 *) + reg NLak3_9 = 1'h0; + (* init = 1'h0 *) + reg NSr3_2 = 1'h0; + (* init = 1'h0 *) + reg NSr3_9 = 1'h0; + (* init = 1'h0 *) + reg NSr5_2 = 1'h0; + (* init = 1'h0 *) + reg NSr5_3 = 1'h0; + (* init = 1'h0 *) + reg NSr5_4 = 1'h0; + (* init = 1'h0 *) + reg NSr5_5 = 1'h0; + (* init = 1'h0 *) + reg NSr5_7 = 1'h0; + (* init = 1'h0 *) + reg NSr5_8 = 1'h0; + (* init = 1'h0 *) + reg N_N2989 = 1'h0; + (* init = 1'h0 *) + reg N_N3011 = 1'h0; + (* init = 1'h0 *) + reg N_N3062 = 1'h0; + (* init = 1'h0 *) + reg N_N3069 = 1'h0; + (* init = 1'h0 *) + reg N_N3071 = 1'h0; + (* init = 1'h0 *) + reg N_N3081 = 1'h0; + (* init = 1'h0 *) + reg N_N3100 = 1'h0; + (* init = 1'h0 *) + reg N_N3105 = 1'h0; + (* init = 1'h0 *) + reg N_N3143 = 1'h0; + (* init = 1'h0 *) + reg N_N3157 = 1'h0; + (* init = 1'h0 *) + reg N_N3164 = 1'h0; + (* init = 1'h0 *) + reg N_N3175 = 1'h0; + (* init = 1'h0 *) + reg N_N3179 = 1'h0; + (* init = 1'h0 *) + reg N_N3188 = 1'h0; + (* init = 1'h0 *) + reg N_N3196 = 1'h0; + (* init = 1'h0 *) + reg N_N3203 = 1'h0; + (* init = 1'h0 *) + reg N_N3205 = 1'h0; + (* init = 1'h0 *) + reg N_N3212 = 1'h0; + (* init = 1'h0 *) + reg N_N3214 = 1'h0; + (* init = 1'h0 *) + reg N_N3221 = 1'h0; + (* init = 1'h0 *) + reg N_N3235 = 1'h0; + (* init = 1'h0 *) + reg N_N3248 = 1'h0; + (* init = 1'h0 *) + reg N_N3250 = 1'h0; + (* init = 1'h0 *) + reg N_N3262 = 1'h0; + (* init = 1'h0 *) + reg N_N3274 = 1'h0; + (* init = 1'h0 *) + reg N_N3280 = 1'h0; + (* init = 1'h0 *) + reg N_N3283 = 1'h0; + (* init = 1'h0 *) + reg N_N3293 = 1'h0; + (* init = 1'h0 *) + reg N_N3294 = 1'h0; + (* init = 1'h0 *) + reg N_N3303 = 1'h0; + (* init = 1'h0 *) + reg N_N3304 = 1'h0; + (* init = 1'h0 *) + reg N_N3311 = 1'h0; + (* init = 1'h0 *) + reg N_N3312 = 1'h0; + (* init = 1'h0 *) + reg N_N3323 = 1'h0; + (* init = 1'h0 *) + reg N_N3324 = 1'h0; + (* init = 1'h0 *) + reg N_N3331 = 1'h0; + (* init = 1'h0 *) + reg N_N3336 = 1'h0; + (* init = 1'h0 *) + reg N_N3340 = 1'h0; + (* init = 1'h0 *) + reg N_N3344 = 1'h0; + (* init = 1'h0 *) + reg N_N3345 = 1'h0; + (* init = 1'h0 *) + reg N_N3346 = 1'h0; + (* init = 1'h0 *) + reg N_N3356 = 1'h0; + (* init = 1'h0 *) + reg N_N3367 = 1'h0; + (* init = 1'h0 *) + reg N_N3369 = 1'h0; + (* init = 1'h0 *) + reg N_N3373 = 1'h0; + (* init = 1'h0 *) + reg N_N3375 = 1'h0; + (* init = 1'h0 *) + reg N_N3384 = 1'h0; + (* init = 1'h0 *) + reg N_N3387 = 1'h0; + (* init = 1'h0 *) + reg N_N3388 = 1'h0; + (* init = 1'h0 *) + reg N_N3393 = 1'h0; + (* init = 1'h0 *) + reg N_N3417 = 1'h0; + (* init = 1'h0 *) + reg N_N3420 = 1'h0; + (* init = 1'h0 *) + reg N_N3424 = 1'h0; + (* init = 1'h0 *) + reg N_N3426 = 1'h0; + (* init = 1'h0 *) + reg N_N3433 = 1'h0; + (* init = 1'h0 *) + reg N_N3436 = 1'h0; + (* init = 1'h0 *) + reg N_N3442 = 1'h0; + (* init = 1'h0 *) + reg N_N3445 = 1'h0; + (* init = 1'h0 *) + reg N_N3457 = 1'h0; + (* init = 1'h0 *) + reg N_N3460 = 1'h0; + (* init = 1'h0 *) + reg N_N3462 = 1'h0; + (* init = 1'h0 *) + reg N_N3464 = 1'h0; + (* init = 1'h0 *) + reg N_N3468 = 1'h0; + (* init = 1'h0 *) + reg N_N3469 = 1'h0; + (* init = 1'h0 *) + reg N_N3470 = 1'h0; + (* init = 1'h0 *) + reg N_N3473 = 1'h0; + (* init = 1'h0 *) + reg N_N3475 = 1'h0; + (* init = 1'h0 *) + reg N_N3480 = 1'h0; + (* init = 1'h0 *) + reg N_N3482 = 1'h0; + (* init = 1'h0 *) + reg N_N3489 = 1'h0; + (* init = 1'h0 *) + reg N_N3500 = 1'h0; + (* init = 1'h0 *) + reg N_N3509 = 1'h0; + (* init = 1'h0 *) + reg N_N3513 = 1'h0; + (* init = 1'h0 *) + reg N_N3516 = 1'h0; + (* init = 1'h0 *) + reg N_N3517 = 1'h0; + (* init = 1'h0 *) + reg N_N3529 = 1'h0; + (* init = 1'h0 *) + reg N_N3533 = 1'h0; + (* init = 1'h0 *) + reg N_N3535 = 1'h0; + (* init = 1'h0 *) + reg N_N3540 = 1'h0; + (* init = 1'h0 *) + reg N_N3541 = 1'h0; + (* init = 1'h0 *) + reg N_N3574 = 1'h0; + (* init = 1'h0 *) + reg N_N3575 = 1'h0; + (* init = 1'h0 *) + reg N_N3578 = 1'h0; + (* init = 1'h0 *) + reg N_N3580 = 1'h0; + (* init = 1'h0 *) + reg N_N3585 = 1'h0; + (* init = 1'h0 *) + reg N_N3607 = 1'h0; + (* init = 1'h0 *) + reg N_N3612 = 1'h0; + (* init = 1'h0 *) + reg N_N3625 = 1'h0; + (* init = 1'h0 *) + reg N_N3626 = 1'h0; + (* init = 1'h0 *) + reg N_N3630 = 1'h0; + (* init = 1'h0 *) + reg N_N3634 = 1'h0; + (* init = 1'h0 *) + reg N_N3659 = 1'h0; + (* init = 1'h0 *) + reg N_N3663 = 1'h0; + (* init = 1'h0 *) + reg N_N3677 = 1'h0; + (* init = 1'h0 *) + reg N_N3679 = 1'h0; + (* init = 1'h0 *) + reg N_N3680 = 1'h0; + (* init = 1'h0 *) + reg N_N3681 = 1'h0; + (* init = 1'h0 *) + reg N_N3684 = 1'h0; + (* init = 1'h0 *) + reg N_N3691 = 1'h0; + (* init = 1'h0 *) + reg N_N3700 = 1'h0; + (* init = 1'h0 *) + reg N_N3701 = 1'h0; + (* init = 1'h0 *) + reg N_N3708 = 1'h0; + (* init = 1'h0 *) + reg N_N3709 = 1'h0; + (* init = 1'h0 *) + reg N_N3711 = 1'h0; + (* init = 1'h0 *) + reg N_N3713 = 1'h0; + (* init = 1'h0 *) + reg N_N3715 = 1'h0; + (* init = 1'h0 *) + reg N_N3716 = 1'h0; + (* init = 1'h0 *) + reg N_N3733 = 1'h0; + (* init = 1'h0 *) + reg N_N3735 = 1'h0; + (* init = 1'h0 *) + reg N_N3736 = 1'h0; + (* init = 1'h0 *) + reg N_N3741 = 1'h0; + (* init = 1'h0 *) + reg N_N3743 = 1'h0; + (* init = 1'h0 *) + reg N_N3745 = 1'h0; + (* init = 1'h0 *) + reg N_N3750 = 1'h0; + (* init = 1'h0 *) + reg N_N3751 = 1'h0; + (* init = 1'h0 *) + reg N_N3761 = 1'h0; + (* init = 1'h0 *) + reg N_N3774 = 1'h0; + (* init = 1'h0 *) + reg N_N3776 = 1'h0; + (* init = 1'h0 *) + reg N_N3778 = 1'h0; + (* init = 1'h0 *) + reg N_N3786 = 1'h0; + (* init = 1'h0 *) + reg N_N3788 = 1'h0; + (* init = 1'h0 *) + reg N_N3791 = 1'h0; + (* init = 1'h0 *) + reg N_N3793 = 1'h0; + (* init = 1'h0 *) + reg N_N3794 = 1'h0; + (* init = 1'h0 *) + reg N_N3796 = 1'h0; + (* init = 1'h0 *) + reg N_N3797 = 1'h0; + (* init = 1'h0 *) + reg N_N3799 = 1'h0; + (* init = 1'h0 *) + reg N_N3800 = 1'h0; + (* init = 1'h0 *) + reg N_N3805 = 1'h0; + (* init = 1'h0 *) + reg N_N3806 = 1'h0; + (* init = 1'h0 *) + reg N_N3807 = 1'h0; + (* init = 1'h0 *) + reg N_N3808 = 1'h0; + (* init = 1'h0 *) + reg N_N3810 = 1'h0; + (* init = 1'h0 *) + reg N_N3813 = 1'h0; + (* init = 1'h0 *) + reg N_N3815 = 1'h0; + (* init = 1'h0 *) + reg N_N3818 = 1'h0; + (* init = 1'h0 *) + reg N_N3821 = 1'h0; + (* init = 1'h0 *) + reg N_N3822 = 1'h0; + (* init = 1'h0 *) + reg N_N3824 = 1'h0; + (* init = 1'h0 *) + reg N_N3826 = 1'h0; + (* init = 1'h0 *) + reg N_N3829 = 1'h0; + (* init = 1'h0 *) + reg N_N3832 = 1'h0; + (* init = 1'h0 *) + reg N_N3838 = 1'h0; + (* init = 1'h0 *) + reg N_N3840 = 1'h0; + (* init = 1'h0 *) + reg N_N3841 = 1'h0; + (* init = 1'h0 *) + reg N_N3842 = 1'h0; + (* init = 1'h0 *) + reg N_N3843 = 1'h0; + (* init = 1'h0 *) + reg N_N3844 = 1'h0; + (* init = 1'h0 *) + reg N_N3862 = 1'h0; + (* init = 1'h0 *) + reg N_N3866 = 1'h0; + (* init = 1'h0 *) + reg N_N3868 = 1'h0; + (* init = 1'h0 *) + reg N_N3870 = 1'h0; + (* init = 1'h0 *) + reg N_N3871 = 1'h0; + (* init = 1'h0 *) + reg N_N3872 = 1'h0; + (* init = 1'h0 *) + reg N_N3875 = 1'h0; + (* init = 1'h0 *) + reg N_N3876 = 1'h0; + (* init = 1'h0 *) + reg N_N3882 = 1'h0; + (* init = 1'h0 *) + reg N_N3884 = 1'h0; + (* init = 1'h0 *) + reg N_N3890 = 1'h0; + (* init = 1'h0 *) + reg N_N3905 = 1'h0; + (* init = 1'h0 *) + reg N_N3906 = 1'h0; + (* init = 1'h0 *) + reg N_N3908 = 1'h0; + (* init = 1'h0 *) + reg N_N3910 = 1'h0; + (* init = 1'h0 *) + reg N_N3912 = 1'h0; + (* init = 1'h0 *) + reg N_N3916 = 1'h0; + (* init = 1'h0 *) + reg N_N3918 = 1'h0; + (* init = 1'h0 *) + reg N_N3919 = 1'h0; + (* init = 1'h0 *) + reg N_N3921 = 1'h0; + (* init = 1'h0 *) + reg N_N3922 = 1'h0; + (* init = 1'h0 *) + reg N_N3923 = 1'h0; + (* init = 1'h0 *) + reg N_N3924 = 1'h0; + (* init = 1'h0 *) + reg N_N3931 = 1'h0; + (* init = 1'h0 *) + reg N_N3932 = 1'h0; + (* init = 1'h0 *) + reg N_N3939 = 1'h0; + (* init = 1'h0 *) + reg N_N3940 = 1'h0; + (* init = 1'h0 *) + reg N_N3947 = 1'h0; + (* init = 1'h0 *) + reg N_N3949 = 1'h0; + (* init = 1'h0 *) + reg N_N3957 = 1'h0; + (* init = 1'h0 *) + reg N_N3959 = 1'h0; + (* init = 1'h0 *) + reg N_N3961 = 1'h0; + (* init = 1'h0 *) + reg N_N3965 = 1'h0; + (* init = 1'h0 *) + reg N_N3968 = 1'h0; + (* init = 1'h0 *) + reg N_N3971 = 1'h0; + (* init = 1'h0 *) + reg N_N3974 = 1'h0; + (* init = 1'h0 *) + reg N_N3981 = 1'h0; + (* init = 1'h0 *) + reg N_N3988 = 1'h0; + (* init = 1'h0 *) + reg N_N3992 = 1'h0; + (* init = 1'h0 *) + reg N_N3996 = 1'h0; + (* init = 1'h0 *) + reg N_N3998 = 1'h0; + (* init = 1'h0 *) + reg N_N3999 = 1'h0; + (* init = 1'h0 *) + reg N_N4004 = 1'h0; + (* init = 1'h0 *) + reg N_N4015 = 1'h0; + (* init = 1'h0 *) + reg N_N4018 = 1'h0; + (* init = 1'h0 *) + reg N_N4021 = 1'h0; + (* init = 1'h0 *) + reg N_N4024 = 1'h0; + (* init = 1'h0 *) + reg N_N4027 = 1'h0; + (* init = 1'h0 *) + reg N_N4030 = 1'h0; + (* init = 1'h0 *) + reg N_N4036 = 1'h0; + (* init = 1'h0 *) + reg N_N4039 = 1'h0; + (* init = 1'h0 *) + reg N_N4042 = 1'h0; + (* init = 1'h0 *) + reg N_N4045 = 1'h0; + (* init = 1'h0 *) + reg N_N4047 = 1'h0; + (* init = 1'h0 *) + reg N_N4054 = 1'h0; + (* init = 1'h0 *) + reg N_N4056 = 1'h0; + (* init = 1'h0 *) + reg N_N4057 = 1'h0; + (* init = 1'h0 *) + reg N_N4060 = 1'h0; + (* init = 1'h0 *) + reg N_N4070 = 1'h0; + (* init = 1'h0 *) + reg N_N4071 = 1'h0; + (* init = 1'h0 *) + reg N_N4072 = 1'h0; + (* init = 1'h0 *) + reg N_N4073 = 1'h0; + (* init = 1'h0 *) + reg N_N4075 = 1'h0; + (* init = 1'h0 *) + reg N_N4079 = 1'h0; + (* init = 1'h0 *) + reg N_N4080 = 1'h0; + (* init = 1'h0 *) + reg N_N4083 = 1'h0; + (* init = 1'h0 *) + reg N_N4086 = 1'h0; + (* init = 1'h0 *) + reg N_N4090 = 1'h0; + (* init = 1'h0 *) + reg N_N4093 = 1'h0; + (* init = 1'h0 *) + reg N_N4095 = 1'h0; + (* init = 1'h0 *) + reg N_N4099 = 1'h0; + (* init = 1'h0 *) + reg N_N4106 = 1'h0; + (* init = 1'h0 *) + reg N_N4111 = 1'h0; + (* init = 1'h0 *) + reg N_N4114 = 1'h0; + (* init = 1'h0 *) + reg N_N4116 = 1'h0; + (* init = 1'h0 *) + reg N_N4117 = 1'h0; + (* init = 1'h0 *) + reg N_N4118 = 1'h0; + (* init = 1'h0 *) + reg N_N4119 = 1'h0; + (* init = 1'h0 *) + reg N_N4120 = 1'h0; + (* init = 1'h0 *) + reg N_N4126 = 1'h0; + (* init = 1'h0 *) + reg N_N4132 = 1'h0; + (* init = 1'h0 *) + reg N_N4133 = 1'h0; + (* init = 1'h0 *) + reg N_N4134 = 1'h0; + (* init = 1'h0 *) + reg N_N4135 = 1'h0; + (* init = 1'h0 *) + reg N_N4136 = 1'h0; + (* init = 1'h0 *) + reg N_N4140 = 1'h0; + (* init = 1'h0 *) + reg N_N4145 = 1'h0; + (* init = 1'h0 *) + reg N_N4158 = 1'h0; + (* init = 1'h0 *) + reg N_N4159 = 1'h0; + (* init = 1'h0 *) + reg N_N4165 = 1'h0; + (* init = 1'h0 *) + reg N_N4167 = 1'h0; + (* init = 1'h0 *) + reg N_N4171 = 1'h0; + (* init = 1'h0 *) + reg N_N4176 = 1'h0; + (* init = 1'h0 *) + reg N_N4177 = 1'h0; + (* init = 1'h0 *) + reg N_N4179 = 1'h0; + (* init = 1'h0 *) + reg N_N4180 = 1'h0; + (* init = 1'h0 *) + reg N_N4181 = 1'h0; + (* init = 1'h0 *) + reg N_N4182 = 1'h0; + (* init = 1'h0 *) + reg N_N4183 = 1'h0; + (* init = 1'h0 *) + reg N_N4193 = 1'h0; + (* init = 1'h0 *) + reg N_N4194 = 1'h0; + (* init = 1'h0 *) + reg N_N4197 = 1'h0; + (* init = 1'h0 *) + reg N_N4205 = 1'h0; + (* init = 1'h0 *) + reg N_N4206 = 1'h0; + (* init = 1'h0 *) + reg N_N4208 = 1'h0; + (* init = 1'h0 *) + reg N_N4209 = 1'h0; + (* init = 1'h0 *) + reg N_N4212 = 1'h0; + (* init = 1'h0 *) + reg N_N4214 = 1'h0; + (* init = 1'h0 *) + reg N_N4218 = 1'h0; + (* init = 1'h0 *) + reg N_N4220 = 1'h0; + (* init = 1'h0 *) + reg N_N4221 = 1'h0; + (* init = 1'h0 *) + reg N_N4222 = 1'h0; + (* init = 1'h0 *) + reg N_N4223 = 1'h0; + (* init = 1'h0 *) + reg N_N4224 = 1'h0; + (* init = 1'h0 *) + reg N_N4227 = 1'h0; + (* init = 1'h0 *) + reg N_N4230 = 1'h0; + (* init = 1'h0 *) + reg N_N4232 = 1'h0; + (* init = 1'h0 *) + reg N_N4236 = 1'h0; + (* init = 1'h0 *) + reg N_N4237 = 1'h0; + (* init = 1'h0 *) + reg N_N4239 = 1'h0; + (* init = 1'h0 *) + reg N_N4242 = 1'h0; + (* init = 1'h0 *) + reg N_N4243 = 1'h0; + (* init = 1'h0 *) + reg N_N4246 = 1'h0; + (* init = 1'h0 *) + reg N_N4252 = 1'h0; + (* init = 1'h0 *) + output PDN; + reg PDN = 1'h0; + input PRESET; + input Paport_0_0_; + input Paport_10_10_; + input Paport_11_11_; + input Paport_1_1_; + input Paport_2_2_; + input Paport_3_3_; + input Paport_4_4_; + input Paport_5_5_; + input Paport_6_6_; + input Paport_7_7_; + input Paport_8_8_; + input Paport_9_9_; + input Pdxport_0_0_; + input Pdxport_10_10_; + input Pdxport_11_11_; + input Pdxport_1_1_; + input Pdxport_2_2_; + input Pdxport_3_3_; + input Pdxport_4_4_; + input Pdxport_5_5_; + input Pdxport_6_6_; + input Pdxport_7_7_; + input Pdxport_8_8_; + input Pdxport_9_9_; + (* init = 1'h0 *) + output Pnext_0_0_; + reg Pnext_0_0_ = 1'h0; + (* init = 1'h0 *) + output Pover_0_0_; + reg Pover_0_0_ = 1'h0; + input Pready_0_0_; + input Preset_0_0_; + input clock; + wire n100; + wire n1000; + wire n1000_1; + wire n1004; + wire n1005; + wire n1005_1; + wire n1010; + wire n1012; + wire n1013; + wire n1014; + wire n1015; + wire n1015_1; + wire n1016; + wire n1017; + wire n1018; + wire n1019; + wire n1020; + wire n1020_1; + wire n1021; + wire n1022; + wire n1023; + wire n1024; + wire n1025; + wire n1025_1; + wire n1026; + wire n1027; + wire n1028; + wire n1029; + wire n1030; + wire n1030_1; + wire n1031; + wire n1032; + wire n1033; + wire n1034; + wire n1035; + wire n1035_1; + wire n1036; + wire n1037; + wire n1038; + wire n1039; + wire n1040; + wire n1040_1; + wire n1041; + wire n1042; + wire n1043; + wire n1045; + wire n1047; + wire n105; + wire n1050; + wire n1050_1; + wire n1052; + wire n1054; + wire n1055; + wire n1055_1; + wire n1056; + wire n1057; + wire n1058; + wire n1059; + wire n1060; + wire n1060_1; + wire n1061; + wire n1062; + wire n1063; + wire n1064; + wire n1065; + wire n1065_1; + wire n1066; + wire n1067; + wire n1068; + wire n1069; + wire n1070; + wire n1070_1; + wire n1071; + wire n1072; + wire n1073; + wire n1074; + wire n1075; + wire n1075_1; + wire n1076; + wire n1077; + wire n1079; + wire n1080; + wire n1082; + wire n1084; + wire n1085; + wire n1087; + wire n1089; + wire n1090; + wire n1091; + wire n1095; + wire n1096; + wire n1098; + wire n110; + wire n1100; + wire n1104; + wire n1105; + wire n1107; + wire n1108; + wire n1109; + wire n1110; + wire n1110_1; + wire n1111; + wire n1112; + wire n1113; + wire n1114; + wire n1115; + wire n1115_1; + wire n1116; + wire n1117; + wire n1118; + wire n1119; + wire n1120; + wire n1120_1; + wire n1121; + wire n1122; + wire n1123; + wire n1124; + wire n1125; + wire n1125_1; + wire n1126; + wire n1127; + wire n1128; + wire n1129; + wire n1130; + wire n1130_1; + wire n1131; + wire n1132; + wire n1133; + wire n1134; + wire n1135; + wire n1135_1; + wire n1136; + wire n1137; + wire n1138; + wire n1139; + wire n1140_1; + wire n1141; + wire n1143; + wire n1145_1; + wire n1147; + wire n115; + wire n1150_1; + wire n1152; + wire n1154; + wire n1155_1; + wire n1160; + wire n1160_1; + wire n1163; + wire n1165; + wire n1165_1; + wire n1166; + wire n1167; + wire n1170_1; + wire n1172; + wire n1175_1; + wire n1176; + wire n1177; + wire n1179; + wire n1180; + wire n1180_1; + wire n1185; + wire n1187; + wire n1188; + wire n1190_1; + wire n1193; + wire n1195; + wire n1199; + wire n120; + wire n1200; + wire n1200_1; + wire n1201; + wire n1202; + wire n1203; + wire n1204; + wire n1205; + wire n1206; + wire n1207; + wire n1210; + wire n1211; + wire n1213; + wire n1215; + wire n1215_1; + wire n1220_1; + wire n1224; + wire n1225_1; + wire n1228; + wire n1229; + wire n1230; + wire n1231; + wire n1232; + wire n1235; + wire n1240_1; + wire n1243; + wire n1245; + wire n1246; + wire n1247; + wire n1248; + wire n125; + wire n1250; + wire n1255_1; + wire n1256; + wire n1260_1; + wire n1265; + wire n1265_1; + wire n1266; + wire n1267; + wire n1269; + wire n1270_1; + wire n1275; + wire n1280; + wire n1280_1; + wire n1283; + wire n1285; + wire n1285_1; + wire n1286; + wire n1288; + wire n1290; + wire n1294; + wire n1295; + wire n1296; + wire n1297; + wire n130; + wire n1300_1; + wire n1301; + wire n1303; + wire n1305_1; + wire n1310_1; + wire n1315_1; + wire n1320_1; + wire n1325_1; + wire n1326; + wire n1330_1; + wire n1335_1; + wire n1340_1; + wire n1345; + wire n1345_1; + wire n135; + wire n1350_1; + wire n1351; + wire n1355_1; + wire n1360_1; + wire n1361; + wire n1362; + wire n1365_1; + wire n1370_1; + wire n1375_1; + wire n1380_1; + wire n1385_1; + wire n1390_1; + wire n1395_1; + wire n1399; + wire n140; + wire n1400_1; + wire n1405_1; + wire n1408; + wire n1410_1; + wire n1412; + wire n1413; + wire n1414; + wire n1415_1; + wire n1418; + wire n1419; + wire n1420; + wire n1420_1; + wire n1421; + wire n1422; + wire n1423; + wire n1424; + wire n1425_1; + wire n1430; + wire n1430_1; + wire n1431; + wire n1432; + wire n1433; + wire n1435_1; + wire n1440_1; + wire n1445_1; + wire n145; + wire n1450_1; + wire n1455_1; + wire n1460_1; + wire n1465_1; + wire n1470_1; + wire n1475_1; + wire n1478; + wire n1479; + wire n1480; + wire n1480_1; + wire n1481; + wire n1482; + wire n1483; + wire n1484; + wire n1485; + wire n1485_1; + wire n1490_1; + wire n1495_1; + wire n150; + wire n1500_1; + wire n1505_1; + wire n1510_1; + wire n1515_1; + wire n1520_1; + wire n1525_1; + wire n1530_1; + wire n1535_1; + wire n1540_1; + wire n1545_1; + wire n155; + wire n1550_1; + wire n1555_1; + wire n1560_1; + wire n1565_1; + wire n1570_1; + wire n1575_1; + wire n1580_1; + wire n160; + wire n165; + wire n170; + wire n175; + wire n180; + wire n185; + wire n190; + wire n195; + wire n200; + wire n205; + wire n210; + wire n215; + wire n220; + wire n225; + wire n230; + wire n235; + wire n240; + wire n245; + wire n250; + wire n255; + wire n260; + wire n265; + wire n270; + wire n275; + wire n280; + wire n285; + wire n290; + wire n295; + wire n300; + wire n305; + wire n310; + wire n315; + wire n320; + wire n325; + wire n330; + wire n335; + wire n340; + wire n345; + wire n350; + wire n355; + wire n360; + wire n365; + wire n370; + wire n375; + wire n380; + wire n385; + wire n390; + wire n395; + wire n400; + wire n405; + wire n410; + wire n415; + wire n420; + wire n425; + wire n430; + wire n435; + wire n440; + wire n445; + wire n450; + wire n455; + wire n460; + wire n465; + wire n470; + wire n475; + wire n480; + wire n485; + wire n490; + wire n495; + wire n500; + wire n505; + wire n510; + wire n515; + wire n520; + wire n525; + wire n530; + wire n535; + wire n540; + wire n545; + wire n550; + wire n555; + wire n560; + wire n565; + wire n570; + wire n575; + wire n580; + wire n585; + wire n590; + wire n595; + wire n600; + wire n605; + wire n610; + wire n615; + wire n620; + wire n625; + wire n63; + wire n630; + wire n635; + wire n640; + wire n645; + wire n650; + wire n655; + wire n660; + wire n665; + wire n67; + wire n670; + wire n675; + wire n680; + wire n685; + wire n690; + wire n695; + wire n700; + wire n705; + wire n71; + wire n710; + wire n715; + wire n720; + wire n725; + wire n730; + wire n735; + wire n740; + wire n745; + wire n75; + wire n750; + wire n755; + wire n760; + wire n765; + wire n770; + wire n775; + wire n780; + wire n785; + wire n790; + wire n795; + wire n80; + wire n800; + wire n805; + wire n810; + wire n815; + wire n820; + wire n825; + wire n830; + wire n835; + wire n840; + wire n845; + wire n85; + wire n850; + wire n855; + wire n860; + wire n865; + wire n870; + wire n875; + wire n880; + wire n885; + wire n890; + wire n895; + wire n90; + wire n900; + wire n905; + wire n910; + wire n915; + wire n920; + wire n925; + wire n930; + wire n935; + wire n940; + wire n945; + wire n95; + wire n950; + wire n950_1; + wire n951; + wire n952; + wire n953; + wire n954; + wire n955; + wire n959; + wire n960; + wire n960_1; + wire n961; + wire n962; + wire n963; + wire n964; + wire n965; + wire n965_1; + wire n966; + wire n967; + wire n968; + wire n969; + wire n970; + wire n970_1; + wire n971; + wire n972; + wire n973; + wire n974; + wire n975; + wire n975_1; + wire n976; + wire n977; + wire n978; + wire n979; + wire n980; + wire n980_1; + wire n981; + wire n982; + wire n983; + wire n984; + wire n985; + wire n985_1; + wire n986; + wire n987; + wire n988; + wire n989; + wire n990; + wire n990_1; + wire n991; + wire n992; + wire n993; + wire n994; + wire n995; + wire n995_1; + wire n996; + wire n997; + wire n998; + wire n999; + always @(posedge clock) + PDN <= n63; + always @(posedge clock) + N_N3924 <= n105; + always @(posedge clock) + N_N3735 <= n555; + always @(posedge clock) + NLak3_2 <= n560; + always @(posedge clock) + NLak3_9 <= n565; + always @(posedge clock) + N_N3906 <= n570; + always @(posedge clock) + N_N3388 <= n575; + always @(posedge clock) + N_N4057 <= n580; + always @(posedge clock) + N_N3011 <= n585; + always @(posedge clock) + N_N3346 <= n590; + always @(posedge clock) + N_N3677 <= n595; + always @(posedge clock) + N_N4165 <= n600; + always @(posedge clock) + N_N3815 <= n110; + always @(posedge clock) + N_N4080 <= n605; + always @(posedge clock) + N_N3373 <= n610; + always @(posedge clock) + N_N3709 <= n615; + always @(posedge clock) + N_N4206 <= n620; + always @(posedge clock) + N_N3324 <= n625; + always @(posedge clock) + N_N3575 <= n630; + always @(posedge clock) + N_N4159 <= n635; + always @(posedge clock) + NAK5_2 <= n640; + always @(posedge clock) + N_N3916 <= n645; + always @(posedge clock) + N_N3743 <= n650; + always @(posedge clock) + N_N3691 <= n115; + always @(posedge clock) + N_N4242 <= n655; + always @(posedge clock) + N_N3312 <= n660; + always @(posedge clock) + N_N3733 <= n665; + always @(posedge clock) + N_N3774 <= n670; + always @(posedge clock) + N_N4214 <= n675; + always @(posedge clock) + N_N3294 <= n680; + always @(posedge clock) + N_N3796 <= n685; + always @(posedge clock) + N_N3574 <= n690; + always @(posedge clock) + N_N3791 <= n695; + always @(posedge clock) + N_N3480 <= n700; + always @(posedge clock) + N_N3157 <= n120; + always @(posedge clock) + N_N4243 <= n705; + always @(posedge clock) + N_N3940 <= n710; + always @(posedge clock) + N_N3509 <= n715; + always @(posedge clock) + N_N4015 <= n720; + always @(posedge clock) + N_N2989 <= n725; + always @(posedge clock) + N_N3919 <= n730; + always @(posedge clock) + N_N3578 <= n735; + always @(posedge clock) + N_N3529 <= n740; + always @(posedge clock) + N_N4222 <= n745; + always @(posedge clock) + N_N3910 <= n750; + always @(posedge clock) + N_N3872 <= n125; + always @(posedge clock) + N_N3868 <= n755; + always @(posedge clock) + N_N3947 <= n760; + always @(posedge clock) + N_N4181 <= n765; + always @(posedge clock) + N_N3793 <= n770; + always @(posedge clock) + N_N3822 <= n775; + always @(posedge clock) + N_N3813 <= n780; + always @(posedge clock) + N_N4114 <= n785; + always @(posedge clock) + N_N4134 <= n790; + always @(posedge clock) + N_N3866 <= n795; + always @(posedge clock) + N_N4218 <= n800; + always @(posedge clock) + N_N3788 <= n130; + always @(posedge clock) + N_N3939 <= n805; + always @(posedge clock) + N_N3776 <= n810; + always @(posedge clock) + N_N3387 <= n815; + always @(posedge clock) + N_N4194 <= n820; + always @(posedge clock) + N_N3821 <= n825; + always @(posedge clock) + N_N3882 <= n830; + always @(posedge clock) + N_N4167 <= n835; + always @(posedge clock) + N_N3800 <= n840; + always @(posedge clock) + N_N4237 <= n845; + always @(posedge clock) + N_N3417 <= n850; + always @(posedge clock) + N_N3375 <= n135; + always @(posedge clock) + N_N3918 <= n855; + always @(posedge clock) + N_N4158 <= n860; + always @(posedge clock) + N_N3630 <= n865; + always @(posedge clock) + N_N3344 <= n870; + always @(posedge clock) + N_N4072 <= n875; + always @(posedge clock) + N_N3274 <= n880; + always @(posedge clock) + N_N3473 <= n885; + always @(posedge clock) + N_N4205 <= n890; + always @(posedge clock) + N_N4111 <= n895; + always @(posedge clock) + N_N3680 <= n900; + always @(posedge clock) + N_N3143 <= n140; + always @(posedge clock) + N_N3838 <= n905; + always @(posedge clock) + N_N3262 <= n910; + always @(posedge clock) + N_N4099 <= n915; + always @(posedge clock) + N_N3607 <= n920; + always @(posedge clock) + N_N3323 <= n925; + always @(posedge clock) + N_N3612 <= n930; + always @(posedge clock) + N_N4079 <= n935; + always @(posedge clock) + N_N3457 <= n940; + always @(posedge clock) + N_N3445 <= n945; + always @(posedge clock) + N_N3794 <= n950; + always @(posedge clock) + N_N4197 <= n145; + always @(posedge clock) + N_N3663 <= n955; + always @(posedge clock) + N_N3715 <= n960; + always @(posedge clock) + N_N4039 <= n965; + always @(posedge clock) + N_N3280 <= n970; + always @(posedge clock) + N_N4239 <= n975; + always @(posedge clock) + N_N3988 <= n980; + always @(posedge clock) + N_N3433 <= n985; + always @(posedge clock) + N_N4075 <= n990; + always @(posedge clock) + N_N3468 <= n995; + always @(posedge clock) + N_N4045 <= n1000; + always @(posedge clock) + N_N3843 <= n150; + always @(posedge clock) + N_N3482 <= n1005; + always @(posedge clock) + N_N3832 <= n1010; + always @(posedge clock) + N_N3304 <= n1015; + always @(posedge clock) + N_N3750 <= n1020; + always @(posedge clock) + N_N3634 <= n1025; + always @(posedge clock) + N_N3293 <= n1030; + always @(posedge clock) + N_N3659 <= n1035; + always @(posedge clock) + N_N4252 <= n1040; + always @(posedge clock) + N_N3912 <= n1045; + always @(posedge clock) + N_N3862 <= n1050; + always @(posedge clock) + Pnext_0_0_ <= n67; + always @(posedge clock) + N_N3426 <= n155; + always @(posedge clock) + N_N3221 <= n1055; + always @(posedge clock) + N_N3875 <= n1060; + always @(posedge clock) + N_N3949 <= n1065; + always @(posedge clock) + N_N3908 <= n1070; + always @(posedge clock) + N_N3711 <= n1075; + always @(posedge clock) + N_N3931 <= n1080; + always @(posedge clock) + N_N3469 <= n1085; + always @(posedge clock) + N_N3436 <= n1090; + always @(posedge clock) + N_N3974 <= n1095; + always @(posedge clock) + N_N3905 <= n1100; + always @(posedge clock) + N_N4118 <= n160; + always @(posedge clock) + N_N3741 <= n1105; + always @(posedge clock) + N_N3369 <= n1110; + always @(posedge clock) + N_N3164 <= n1115; + always @(posedge clock) + N_N3500 <= n1120; + always @(posedge clock) + N_N3996 <= n1125; + always @(posedge clock) + N_N3356 <= n1130; + always @(posedge clock) + N_N4093 <= n1135; + always @(posedge clock) + N_N4224 <= n1140_1; + always @(posedge clock) + N_N4027 <= n1145_1; + always @(posedge clock) + NDN1_4 <= n1150_1; + always @(posedge clock) + N_N3580 <= n165; + always @(posedge clock) + N_N3384 <= n1155_1; + always @(posedge clock) + N_N4036 <= n1160_1; + always @(posedge clock) + N_N3968 <= n1165_1; + always @(posedge clock) + N_N4183 <= n1170_1; + always @(posedge clock) + NGFDN_3 <= n1175_1; + always @(posedge clock) + N_N4090 <= n1180; + always @(posedge clock) + N_N4004 <= n1185; + always @(posedge clock) + N_N3205 <= n1190_1; + always @(posedge clock) + N_N4136 <= n1195; + always @(posedge clock) + N_N3303 <= n1200; + always @(posedge clock) + N_N3175 <= n170; + always @(posedge clock) + N_N3533 <= n1205; + always @(posedge clock) + N_N3336 <= n1210; + always @(posedge clock) + N_N3961 <= n1215_1; + always @(posedge clock) + N_N3331 <= n1220_1; + always @(posedge clock) + N_N3203 <= n1225_1; + always @(posedge clock) + N_N4236 <= n1230; + always @(posedge clock) + N_N3884 <= n1235; + always @(posedge clock) + N_N3367 <= n1240_1; + always @(posedge clock) + N_N4140 <= n1245; + always @(posedge clock) + NDN2_2 <= n1250; + always @(posedge clock) + N_N3071 <= n175; + always @(posedge clock) + N_N4106 <= n1255_1; + always @(posedge clock) + N_N3100 <= n1260_1; + always @(posedge clock) + N_N4193 <= n1265_1; + always @(posedge clock) + N_N3470 <= n1270_1; + always @(posedge clock) + N_N3424 <= n1275; + always @(posedge clock) + N_N3959 <= n1280_1; + always @(posedge clock) + N_N3393 <= n1285; + always @(posedge clock) + N_N4042 <= n1290; + always @(posedge clock) + N_N3188 <= n1295; + always @(posedge clock) + N_N4095 <= n1300_1; + always @(posedge clock) + N_N3808 <= n180; + always @(posedge clock) + N_N3957 <= n1305_1; + always @(posedge clock) + N_N3517 <= n1310_1; + always @(posedge clock) + N_N4047 <= n1315_1; + always @(posedge clock) + N_N3081 <= n1320_1; + always @(posedge clock) + N_N3541 <= n1325_1; + always @(posedge clock) + N_N4177 <= n1330_1; + always @(posedge clock) + NDN3_3 <= n1335_1; + always @(posedge clock) + N_N4176 <= n1340_1; + always @(posedge clock) + N_N3585 <= n1345_1; + always @(posedge clock) + NDN3_8 <= n1350_1; + always @(posedge clock) + N_N3923 <= n185; + always @(posedge clock) + N_N4209 <= n1355_1; + always @(posedge clock) + N_N3824 <= n1360_1; + always @(posedge clock) + N_N4208 <= n1365_1; + always @(posedge clock) + N_N4120 <= n1370_1; + always @(posedge clock) + N_N3708 <= n1375_1; + always @(posedge clock) + N_N4220 <= n1380_1; + always @(posedge clock) + N_N3999 <= n1385_1; + always @(posedge clock) + N_N4223 <= n1390_1; + always @(posedge clock) + N_N3179 <= n1395_1; + always @(posedge clock) + N_N4179 <= n1400_1; + always @(posedge clock) + N_N3250 <= n190; + always @(posedge clock) + N_N3475 <= n1405_1; + always @(posedge clock) + N_N4132 <= n1410_1; + always @(posedge clock) + N_N4182 <= n1415_1; + always @(posedge clock) + N_N3797 <= n1420_1; + always @(posedge clock) + N_N3214 <= n1425_1; + always @(posedge clock) + N_N4070 <= n1430_1; + always @(posedge clock) + N_N4135 <= n1435_1; + always @(posedge clock) + NLD3_9 <= n1440_1; + always @(posedge clock) + NDN5_2 <= n1445_1; + always @(posedge clock) + NDN5_3 <= n1450_1; + always @(posedge clock) + N_N4221 <= n195; + always @(posedge clock) + N_N3778 <= n1455_1; + always @(posedge clock) + NDN5_4 <= n1460_1; + always @(posedge clock) + N_N3212 <= n1465_1; + always @(posedge clock) + NDN5_5 <= n1470_1; + always @(posedge clock) + NDN5_6 <= n1475_1; + always @(posedge clock) + NDN5_7 <= n1480_1; + always @(posedge clock) + NDN5_8 <= n1485_1; + always @(posedge clock) + N_N4073 <= n1490_1; + always @(posedge clock) + NDN5_9 <= n1495_1; + always @(posedge clock) + NEN5_9 <= n1500_1; + always @(posedge clock) + N_N3069 <= n200; + always @(posedge clock) + N_N3684 <= n1505_1; + always @(posedge clock) + N_N4056 <= n1510_1; + always @(posedge clock) + N_N3713 <= n1515_1; + always @(posedge clock) + N_N3829 <= n1520_1; + always @(posedge clock) + N_N4060 <= n1525_1; + always @(posedge clock) + NSr3_2 <= n1530_1; + always @(posedge clock) + NSr5_2 <= n1535_1; + always @(posedge clock) + NSr5_3 <= n1540_1; + always @(posedge clock) + N_N3462 <= n1545_1; + always @(posedge clock) + N_N3460 <= n1550_1; + always @(posedge clock) + Pover_0_0_ <= n71; + always @(posedge clock) + N_N3464 <= n205; + always @(posedge clock) + NSr5_4 <= n1555_1; + always @(posedge clock) + NSr3_9 <= n1560_1; + always @(posedge clock) + NSr5_5 <= n1565_1; + always @(posedge clock) + NSr5_7 <= n1570_1; + always @(posedge clock) + NSr5_8 <= n1575_1; + always @(posedge clock) + N_N3998 <= n1580_1; + always @(posedge clock) + N_N3535 <= n210; + always @(posedge clock) + N_N3871 <= n215; + always @(posedge clock) + N_N3248 <= n220; + always @(posedge clock) + N_N4180 <= n225; + always @(posedge clock) + N_N3311 <= n230; + always @(posedge clock) + N_N3442 <= n235; + always @(posedge clock) + N_N3981 <= n240; + always @(posedge clock) + N_N3842 <= n245; + always @(posedge clock) + N_N3105 <= n250; + always @(posedge clock) + N_N4054 <= n75; + always @(posedge clock) + N_N4133 <= n255; + always @(posedge clock) + N_N4117 <= n260; + always @(posedge clock) + N_N3420 <= n265; + always @(posedge clock) + N_N3761 <= n270; + always @(posedge clock) + N_N3062 <= n275; + always @(posedge clock) + N_N4071 <= n280; + always @(posedge clock) + N_N4227 <= n285; + always @(posedge clock) + N_N3807 <= n290; + always @(posedge clock) + N_N4145 <= n295; + always @(posedge clock) + N_N3922 <= n300; + always @(posedge clock) + N_N3745 <= n80; + always @(posedge clock) + N_N3516 <= n305; + always @(posedge clock) + N_N3489 <= n310; + always @(posedge clock) + N_N4030 <= n315; + always @(posedge clock) + N_N3540 <= n320; + always @(posedge clock) + N_N3513 <= n325; + always @(posedge clock) + N_N4083 <= n330; + always @(posedge clock) + N_N3841 <= n335; + always @(posedge clock) + N_N4018 <= n340; + always @(posedge clock) + N_N3971 <= n345; + always @(posedge clock) + N_N4232 <= n350; + always @(posedge clock) + N_N4119 <= n85; + always @(posedge clock) + N_N4246 <= n355; + always @(posedge clock) + N_N3806 <= n360; + always @(posedge clock) + N_N3992 <= n365; + always @(posedge clock) + N_N4086 <= n370; + always @(posedge clock) + N_N4230 <= n375; + always @(posedge clock) + N_N4212 <= n380; + always @(posedge clock) + N_N3626 <= n385; + always @(posedge clock) + N_N3965 <= n390; + always @(posedge clock) + N_N3890 <= n395; + always @(posedge clock) + NDN3_11 <= n400; + always @(posedge clock) + N_N3826 <= n90; + always @(posedge clock) + NDN5_10 <= n405; + always @(posedge clock) + N_N3786 <= n410; + always @(posedge clock) + N_N4171 <= n415; + always @(posedge clock) + NDN5_16 <= n420; + always @(posedge clock) + N_N3799 <= n425; + always @(posedge clock) + N_N3844 <= n430; + always @(posedge clock) + N_N3196 <= n435; + always @(posedge clock) + N_N4126 <= n440; + always @(posedge clock) + N_N3681 <= n445; + always @(posedge clock) + N_N3679 <= n450; + always @(posedge clock) + N_N3818 <= n95; + always @(posedge clock) + N_N3340 <= n455; + always @(posedge clock) + N_N4116 <= n460; + always @(posedge clock) + N_N3810 <= n465; + always @(posedge clock) + N_N3235 <= n470; + always @(posedge clock) + N_N3283 <= n475; + always @(posedge clock) + N_N3716 <= n480; + always @(posedge clock) + N_N3701 <= n485; + always @(posedge clock) + N_N3921 <= n490; + always @(posedge clock) + N_N3625 <= n495; + always @(posedge clock) + N_N3751 <= n500; + always @(posedge clock) + N_N3345 <= n100; + always @(posedge clock) + N_N3736 <= n505; + always @(posedge clock) + N_N3870 <= n510; + always @(posedge clock) + N_N4024 <= n515; + always @(posedge clock) + N_N3876 <= n520; + always @(posedge clock) + N_N3840 <= n525; + always @(posedge clock) + N_N4021 <= n530; + always @(posedge clock) + N_N3932 <= n535; + always @(posedge clock) + NLC1_2 <= n540; + always @(posedge clock) + N_N3805 <= n545; + always @(posedge clock) + N_N3700 <= n550; + assign n975 = 64'hfffff222f222f222 >> { N_N3774, n954, n953, N_N4090, n950_1, N_N4239 }; + assign n950_1 = 64'h1511151155551511 >> { NDN1_4, PDN, NDN3_3, NDN3_8, n951, n952 }; + assign n951 = 4'h1 >> { NLD3_9, PRESET }; + assign n952 = 64'h00080000000a0002 >> { Preset_0_0_, N_N3998, PRESET, NDN1_4, NLC1_2, PDN }; + assign n953 = 8'h02 >> { NDN3_8, PRESET, NDN3_3 }; + assign n954 = 4'h2 >> { PRESET, NLD3_9 }; + assign n350 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4232 }; + assign n375 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4230 }; + assign n800 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4218 }; + assign n835 = 32'd321978912 >> { N_N4167, n959, n999, PRESET, n969 }; + assign n959 = 32'd147754223 >> { n960_1, n993, n996, n997, n998 }; + assign n960_1 = 32'd3722265677 >> { n961, n974, n975_1, n990_1, n992 }; + assign n961 = 16'h1222 >> { n962, n971, n973, n972 }; + assign n962 = 32'd2763306 >> { n970_1, N_N3081, n969, N_N3203, n963 }; + assign n963 = 32'd2763306 >> { n970_1, N_N4021, n969, N_N3679, n964 }; + assign n964 = 16'h8000 >> { n965_1, n966, n967, n968 }; + assign n965_1 = 64'hfdfdfdfd00fdfdfd >> { NDN5_9, N_N3957, NEN5_9, NSr5_7, NDN5_10, N_N3205 }; + assign n966 = 64'hfdfdfdfd00fdfdfd >> { NDN5_9, N_N4024, NEN5_9, NSr5_7, NDN5_10, N_N3799 }; + assign n967 = 64'hfdfdfdfd00fdfdfd >> { NDN5_9, N_N3959, NEN5_9, NSr5_7, NDN5_10, N_N3968 }; + assign n968 = 64'hfdfdfdfd00fdfdfd >> { NDN5_9, N_N3625, NEN5_9, NSr5_7, NDN5_10, N_N3626 }; + assign n969 = 4'h1 >> { NSr5_7, NDN5_10 }; + assign n970_1 = 4'h2 >> { NDN5_9, NEN5_9 }; + assign n971 = 16'h0777 >> { N_N3700, n970_1, n969, N_N3701 }; + assign n972 = 16'h0777 >> { N_N3585, n970_1, n969, N_N3100 }; + assign n973 = 16'h0777 >> { N_N3815, n970_1, n969, N_N4136 }; + assign n974 = 16'h8222 >> { n962, n971, n972, n973 }; + assign n975_1 = 64'hf999fff990009990 >> { n988, n976, n977, n989, n962, n971 }; + assign n976 = 32'd2845418837 >> { n969, n970_1, N_N3081, N_N3203, n963 }; + assign n977 = 32'd2315841454 >> { n978, n979, n987, n986, n985_1 }; + assign n978 = 32'd2845418837 >> { n969, n970_1, N_N4021, N_N3679, n964 }; + assign n979 = 64'h9fff999f09990009 >> { n981, n982, n983, n984, n980_1, n966 }; + assign n980_1 = 4'h8 >> { n967, n968 }; + assign n981 = 16'h0777 >> { N_N3480, n970_1, n969, N_N4086 }; + assign n982 = 16'h0777 >> { N_N3684, n970_1, n969, N_N3500 }; + assign n983 = 32'd1430274112 >> { N_N3796, n970_1, n969, N_N3971, n968 }; + assign n984 = 4'h6 >> { n967, n968 }; + assign n985_1 = 16'h0777 >> { N_N3509, n970_1, n969, N_N3890 }; + assign n986 = 16'h0777 >> { N_N3829, n970_1, n969, N_N4224 }; + assign n987 = 16'h6aaa >> { n966, n967, n968, n965_1 }; + assign n988 = 16'h0777 >> { N_N3529, n970_1, n969, N_N3844 }; + assign n989 = 16'h0777 >> { N_N3826, n970_1, n969, N_N4183 }; + assign n990_1 = 16'h6aaa >> { n962, n971, n972, n991 }; + assign n991 = 16'h0777 >> { N_N3735, n970_1, n969, N_N3736 }; + assign n992 = 16'h0777 >> { N_N3947, n970_1, n969, N_N3810 }; + assign n993 = 32'd2845418837 >> { n969, n970_1, N_N4075, N_N3482, n994 }; + assign n994 = 32'd2147483648 >> { n962, n971, n972, n991, n995_1 }; + assign n995_1 = 16'h0777 >> { N_N3824, n970_1, n969, N_N4042 }; + assign n996 = 32'd1789569706 >> { n962, n971, n972, n991, n995_1 }; + assign n997 = 16'h0777 >> { N_N3274, n970_1, n969, N_N3470 }; + assign n998 = 16'h0777 >> { N_N3788, n970_1, n969, N_N4140 }; + assign n999 = 64'haaa6a6a6aa666666 >> { n969, n970_1, N_N4075, N_N3482, n994, n1000_1 }; + assign n1000_1 = 64'h022046ec4e6c0aa0 >> { N_N4039, N_N4095, N_N4167, N_N3612, n969, n970_1 }; + assign n1245 = 64'hfffff222f222f222 >> { N_N3540, n954, n953, N_N3541, n950_1, N_N4140 }; + assign n785 = 32'd321978912 >> { N_N4114, n959, n999, PRESET, n970_1 }; + assign n895 = 16'h3120 >> { N_N4111, n1004, PRESET, n1005_1 }; + assign n1004 = 64'h022046ec4e6c0aa0 >> { N_N3910, N_N3939, N_N3940, N_N3906, n970_1, n1005_1 }; + assign n1005_1 = 16'h0008 >> { NDN5_6, NLak3_9, NSr3_9, NDN3_8 }; + assign n1255_1 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4106 }; + assign n915 = 64'hfffff222f222f222 >> { n954, N_N3743, n953, N_N3384, n950_1, N_N4099 }; + assign n1300_1 = 64'hfffff222f222f222 >> { N_N4114, n954, n953, N_N3866, n950_1, N_N4095 }; + assign n1180 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4090 }; + assign n370 = 64'hfffff222f222f222 >> { N_N3715, n954, n953, N_N3716, n950_1, N_N4086 }; + assign n990 = 32'd1426150400 >> { n1012, N_N4075, NDN5_8, NSr5_8, PRESET }; + assign n1012 = 4'h8 >> { n1013, N_N4197 }; + assign n1013 = 64'h0ddddddddddddddd >> { n1032, n1042, n1019, n1479, N_N3838, N_N3999 }; + assign n1014 = 4'h2 >> { NSr5_3, NSr5_4 }; + assign n1015_1 = 4'h2 >> { NSr5_2, NSr5_3 }; + assign n1016 = 4'h2 >> { NSr5_5, NSr5_7 }; + assign n1017 = 4'h2 >> { NSr5_7, NSr5_8 }; + assign n1018 = 64'hdddddddd0ddddddd >> { NLak3_9, NSr3_9, NSr5_2, NDN3_8, NSr5_4, NSr5_5 }; + assign n1019 = 32'd2147483648 >> { n1020_1, n1022, n1024, n1027, n1030_1 }; + assign n1020_1 = 32'd9079434 >> { N_N4177, n1015_1, N_N4194, n1018, n1021 }; + assign n1021 = 64'h0000077707770777 >> { n1017, N_N4045, N_N3457, n1016, n1014, N_N4176 }; + assign n1022 = 32'd9079434 >> { n1014, N_N4239, N_N4206, n1018, n1023 }; + assign n1023 = 64'h0000077707770777 >> { N_N3188, n1017, N_N3436, n1016, n1015_1, N_N3813 }; + assign n1024 = 8'h8a >> { N_N4120, n1018, n1025_1 }; + assign n1025_1 = 32'd2763306 >> { N_N4116, n1017, n1016, N_N4117, n1026 }; + assign n1026 = 32'd2734159863 >> { N_N4118, NSr5_4, NSr5_2, N_N4119, NSr5_3 }; + assign n1027 = 8'h8a >> { N_N4057, n1018, n1028 }; + assign n1028 = 32'd2763306 >> { n1016, N_N3221, n1014, N_N3918, n1029 }; + assign n1029 = 64'hf7f7f7f700f7f7f7 >> { NSr5_2, NSr5_3, N_N3919, NSr5_7, NSr5_8, N_N3367 }; + assign n1030_1 = 32'd9079434 >> { N_N3840, n1017, N_N4132, n1018, n1031 }; + assign n1031 = 64'h0000077707770777 >> { n1016, N_N3841, N_N3843, n1015_1, n1014, N_N3842 }; + assign n1032 = 64'h0000000080000000 >> { N_N3999, n1035_1, n1037, n1039, n1481, n1033 }; + assign n1033 = 32'd9079434 >> { n1016, N_N3711, N_N4165, n1018, n1034 }; + assign n1034 = 64'h0000077707770777 >> { N_N3424, n1017, n1015_1, N_N3868, n1014, N_N4099 }; + assign n1035_1 = 32'd9079434 >> { N_N3924, n1015_1, N_N4220, n1018, n1036 }; + assign n1036 = 64'h0000077707770777 >> { N_N3921, n1017, N_N3922, n1016, n1014, N_N3923 }; + assign n1037 = 32'd9079434 >> { N_N4208, n1014, N_N4237, n1018, n1038 }; + assign n1038 = 64'h0000077707770777 >> { n1017, N_N3659, N_N3433, n1016, n1015_1, N_N4209 }; + assign n1039 = 8'h8a >> { N_N3906, n1018, n1040_1 }; + assign n1040_1 = 32'd2763306 >> { N_N3303, n1017, n1016, N_N3304, n1041 }; + assign n1041 = 32'd2734159863 >> { N_N3939, NSr5_4, NSr5_2, N_N3940, NSr5_3 }; + assign n1042 = 32'd9079434 >> { n1014, N_N3871, N_N4179, n1018, n1043 }; + assign n1043 = 64'h0000077707770777 >> { n1017, N_N3870, N_N4030, n1016, n1015_1, N_N3872 }; + assign n1510_1 = 32'd1426150400 >> { Paport_5_5_, N_N4056, NDN3_3, NSr3_2, PRESET }; + assign n75 = 32'd1426150400 >> { Paport_7_7_, N_N4054, NDN3_3, NSr3_2, PRESET }; + assign n1315_1 = 32'd1426150400 >> { n1047, N_N4047, NSr5_4, NDN5_4, PRESET }; + assign n1047 = 4'h8 >> { n1013, N_N4145 }; + assign n1000 = 32'd1426150400 >> { n1012, N_N4045, NSr5_4, NDN5_4, PRESET }; + assign n1290 = 32'd1426150400 >> { n1050_1, N_N4042, NSr5_7, NDN5_7, PRESET }; + assign n1050_1 = 4'h8 >> { n1013, N_N3912 }; + assign n965 = 32'd1426150400 >> { n1052, N_N4039, NSr5_7, NDN5_7, PRESET }; + assign n1052 = 4'h8 >> { n1013, N_N4227 }; + assign n935 = 32'd823336962 >> { N_N4079, n1077, n1054, PRESET, n970_1 }; + assign n1054 = 64'h9999999a99999aaa >> { n1055_1, n1074, n1075_1, n1076, n1073, n1072 }; + assign n1055_1 = 64'h5150515051505151 >> { n1056, n1071, n1070_1, n1068, n1069, n1067 }; + assign n1056 = 64'h5555555500010111 >> { n1063, n1057, n1065_1, n1066, n1064, n1062 }; + assign n1057 = 64'h88888eee8eee8eee >> { n970_1, N_N3793, n1005_1, N_N4057, n1058, n1061 }; + assign n1058 = 64'h22222bbb2bbb2bbb >> { n970_1, N_N3157, n1005_1, N_N4120, n1059, n1060_1 }; + assign n1059 = 64'heca8cc00a0a08000 >> { N_N3910, N_N3940, N_N3939, N_N3906, n970_1, n1005_1 }; + assign n1060_1 = 16'h0777 >> { n1005_1, N_N4119, n970_1, N_N4118 }; + assign n1061 = 16'h0777 >> { n1005_1, N_N3919, n970_1, N_N3918 }; + assign n1062 = 64'h00011111000fffff >> { n970_1, n1005_1, N_N4179, N_N3872, N_N3871, N_N3071 }; + assign n1063 = 64'heca8cc00a0a08000 >> { N_N4099, N_N4165, N_N3776, N_N3868, n970_1, n1005_1 }; + assign n1064 = 64'h00011111000fffff >> { n970_1, n1005_1, N_N4165, N_N3868, N_N4099, N_N3776 }; + assign n1065_1 = 16'h0777 >> { N_N3924, n1005_1, n970_1, N_N3923 }; + assign n1066 = 16'h0777 >> { N_N4220, n1005_1, n970_1, N_N3143 }; + assign n1067 = 64'heca8cc00a0a08000 >> { N_N3842, N_N4132, N_N3069, N_N3843, n970_1, n1005_1 }; + assign n1068 = 64'h00011111000fffff >> { n970_1, n1005_1, N_N4132, N_N3843, N_N3842, N_N3069 }; + assign n1069 = 64'heca8cc00a0a08000 >> { N_N4239, N_N4206, N_N3630, N_N3813, n970_1, n1005_1 }; + assign n1070_1 = 64'h00011111000fffff >> { n970_1, n1005_1, N_N4206, N_N3813, N_N4239, N_N3630 }; + assign n1071 = 64'heca8cc00a0a08000 >> { N_N3871, N_N4179, N_N3071, N_N3872, n970_1, n1005_1 }; + assign n1072 = 16'h0777 >> { n1005_1, N_N4177, n970_1, N_N4176 }; + assign n1073 = 64'heca8cc00a0a08000 >> { N_N3807, N_N4070, N_N3311, N_N3808, n970_1, n1005_1 }; + assign n1074 = 64'h00011111000fffff >> { n970_1, n1005_1, N_N4070, N_N3808, N_N3807, N_N3311 }; + assign n1075_1 = 16'h0777 >> { N_N4242, n1005_1, n970_1, N_N3607 }; + assign n1076 = 16'h0777 >> { N_N3800, n1005_1, n970_1, N_N4252 }; + assign n1077 = 16'h0777 >> { N_N4194, n1005_1, n970_1, N_N4193 }; + assign n315 = 32'd1426150400 >> { n1079, N_N4030, NSr5_3, NDN5_3, PRESET }; + assign n1079 = 4'h8 >> { n1013, N_N3974 }; + assign n1230 = 32'd1426150400 >> { n1052, N_N4236, NSr5_5, NDN5_5, PRESET }; + assign n515 = 32'd1426150400 >> { n1082, N_N4024, NDN5_8, NSr5_8, PRESET }; + assign n1082 = 4'h8 >> { n1013, N_N3992 }; + assign n530 = 32'd1426150400 >> { n1084, N_N4021, NDN5_8, NSr5_8, PRESET }; + assign n1084 = 4'h8 >> { n1013, N_N4018 }; + assign n580 = 32'd1426150400 >> { Pdxport_2_2_, N_N4057, NDN3_3, NSr3_2, PRESET }; + assign n980 = 32'd1426150400 >> { n1087, N_N3988, NSr5_2, NDN5_2, PRESET }; + assign n1087 = 4'h8 >> { n1013, N_N4083 }; + assign n240 = 32'd823336962 >> { N_N3981, n1066, n1089, PRESET, n1005_1 }; + assign n1089 = 4'h6 >> { n1057, n1065_1 }; + assign n460 = 32'd1426150400 >> { n1091, N_N4116, NSr5_4, NDN5_4, PRESET }; + assign n1091 = 4'h8 >> { n1013, N_N4027 }; + assign n1165_1 = 32'd1426150400 >> { n1091, N_N3968, NSr5_7, NDN5_7, PRESET }; + assign n1400_1 = 32'd1426150400 >> { Pdxport_5_5_, N_N4179, NDN3_3, NSr3_2, PRESET }; + assign n1280_1 = 32'd1426150400 >> { n1091, N_N3959, NDN5_8, NSr5_8, PRESET }; + assign n1305_1 = 32'd1426150400 >> { n1096, N_N3957, NDN5_8, NSr5_8, PRESET }; + assign n1096 = 4'h8 >> { n1013, N_N3996 }; + assign n760 = 64'h3113133120020220 >> { N_N3947, n1098, n990_1, n992, PRESET, n969 }; + assign n1098 = 8'h54 >> { n975_1, n974, n961 }; + assign n1380_1 = 32'd1426150400 >> { Pdxport_3_3_, N_N4220, NDN3_3, NSr3_2, PRESET }; + assign n645 = 32'd1426150400 >> { Paport_0_0_, N_N3916, NDN3_3, NSr3_2, PRESET }; + assign n705 = 32'd1426150400 >> { Paport_6_6_, N_N4243, NDN3_3, NSr3_2, PRESET }; + assign n720 = 32'd1426150400 >> { Paport_8_8_, N_N4015, NDN3_3, NSr3_2, PRESET }; + assign n750 = 32'd1426150400 >> { n1104, N_N3910, NSr5_5, NDN5_5, PRESET }; + assign n1104 = 4'h8 >> { n1013, N_N3965 }; + assign n1370_1 = 32'd1426150400 >> { Pdxport_1_1_, N_N4120, NDN3_3, NSr3_2, PRESET }; + assign n145 = 32'd2934604872 >> { n1134, n1107, n1137, n1139, N_N4197 }; + assign n1107 = 8'hb2 >> { n1108, N_N3912, n1132 }; + assign n1108 = 32'd3205181186 >> { n1109, n1130_1, N_N4145, N_N3949, n1128 }; + assign n1109 = 32'd3205181186 >> { n1110_1, n1483, N_N4083, N_N3974, n1126 }; + assign n1110_1 = 32'd3205181186 >> { n1111, n1124, N_N4018, N_N3996, n1121 }; + assign n1111 = 32'd788709131 >> { n1112, n1118, N_N3992, N_N4027, n1115_1 }; + assign n1112 = 32'd707439146 >> { n1018, N_N3971, n1114, n1113, N_N3965 }; + assign n1113 = 64'hf7f7f7f700f7f7f7 >> { NSr5_3, NSr5_4, N_N3745, NSr5_5, NSr5_7, N_N3387 }; + assign n1114 = 64'hf7f7f7f700f7f7f7 >> { NSr5_2, NSr5_3, N_N3388, NSr5_7, N_N3906, NSr5_8 }; + assign n1115_1 = 16'h8088 >> { N_N3500, n1018, n1117, n1116 }; + assign n1116 = 64'hf7f7f7f700f7f7f7 >> { NSr5_2, NSr5_3, N_N3708, NSr5_7, NSr5_8, N_N4120 }; + assign n1117 = 64'hf7f7f7f700f7f7f7 >> { NSr5_3, N_N2989, NSr5_4, NSr5_5, NSr5_7, N_N3175 }; + assign n1118 = 64'h0022222200020202 >> { n1018, n1016, N_N3344, N_N4086, n1119, n1120_1 }; + assign n1119 = 8'h08 >> { NSr5_2, NSr5_3, N_N3346 }; + assign n1120_1 = 64'hf7f7f7f700f7f7f7 >> { NSr5_3, NSr5_4, N_N3345, NSr5_7, NSr5_8, N_N4057 }; + assign n1121 = 8'h8a >> { N_N4224, n1018, n1122 }; + assign n1122 = 32'd2763306 >> { n1017, N_N4220, n1015_1, N_N4223, n1123 }; + assign n1123 = 64'hf7f7f7f700f7f7f7 >> { NSr5_3, N_N4222, NSr5_4, NSr5_5, NSr5_7, N_N4221 }; + assign n1124 = 32'd9079434 >> { N_N3323, n1016, N_N3890, n1018, n1125_1 }; + assign n1125_1 = 64'h0000077707770777 >> { n1017, N_N4165, N_N3324, n1015_1, n1014, N_N3691 }; + assign n1126 = 32'd9079434 >> { N_N4181, n1014, N_N4183, n1018, n1127 }; + assign n1127 = 64'h0000077707770777 >> { n1017, N_N4179, N_N4180, n1016, n1015_1, N_N4182 }; + assign n1128 = 32'd9079434 >> { N_N4132, n1017, N_N4136, n1018, n1129 }; + assign n1129 = 64'h0000077707770777 >> { n1016, N_N4133, n1015_1, N_N4135, n1014, N_N4134 }; + assign n1130_1 = 32'd9079434 >> { N_N3426, n1014, N_N3810, n1018, n1131 }; + assign n1131 = 64'h0000077707770777 >> { n1017, N_N4242, N_N3293, n1016, n1015_1, N_N3294 }; + assign n1132 = 32'd9079434 >> { N_N4070, n1017, N_N4140, n1018, n1133 }; + assign n1133 = 64'h0000077707770777 >> { n1016, N_N4071, n1015_1, N_N4073, n1014, N_N4072 }; + assign n1134 = 64'h1111111111110111 >> { n1135_1, N_N4214, n1013, N_N3460, PRESET, n1136 }; + assign n1135_1 = 32'd2 >> { n1014, n1015_1, n1016, n1017, n1018 }; + assign n1136 = 8'h08 >> { N_N3575, N_N3462, N_N4214 }; + assign n1137 = 32'd9079434 >> { N_N3468, n1014, N_N3470, n1018, n1138 }; + assign n1138 = 64'h0000077707770777 >> { n1017, N_N4194, n1016, N_N3473, n1015_1, N_N3469 }; + assign n1139 = 4'h2 >> { PRESET, n1136 }; + assign n1520_1 = 16'h3120 >> { N_N3829, n1141, PRESET, n969 }; + assign n1141 = 8'h96 >> { n979, n986, n987 }; + assign n90 = 16'h1302 >> { N_N3826, n1143, PRESET, n969 }; + assign n1143 = 8'h69 >> { n976, n977, n989 }; + assign n1360_1 = 32'd1426150400 >> { n1050_1, N_N3824, NDN5_8, NSr5_8, PRESET }; + assign n95 = 32'd1426150400 >> { Paport_9_9_, N_N3818, NDN3_3, NSr3_2, PRESET }; + assign n110 = 32'd823336962 >> { N_N3815, n975_1, n1147, PRESET, n969 }; + assign n1147 = 4'h1 >> { n961, n974 }; + assign n520 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3876 }; + assign n345 = 64'hfffff222f222f222 >> { N_N3680, n954, n953, N_N3681, n950_1, N_N3971 }; + assign n425 = 32'd1426150400 >> { n1082, N_N3799, NSr5_7, NDN5_7, PRESET }; + assign n685 = 16'h3120 >> { N_N3796, n1152, PRESET, n969 }; + assign n1152 = 32'd2845418837 >> { n969, n970_1, N_N3796, N_N3971, n968 }; + assign n130 = 32'd321978912 >> { N_N3788, n1154, n996, PRESET, n969 }; + assign n1154 = 4'h9 >> { n960_1, n998 }; + assign n410 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3786 }; + assign n510 = 32'd1426150400 >> { n1079, N_N3870, NSr5_4, NDN5_4, PRESET }; + assign n80 = 64'h4444444444444454 >> { NDN2_2, NLC1_2, PDN, Preset_0_0_, N_N3745, PRESET }; + assign n1105 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3741 }; + assign n365 = 32'd3937290372 >> { n1134, n1160, n1118, n1139, N_N3992 }; + assign n1160 = 8'hb2 >> { n1112, n1115_1, N_N4027 }; + assign n1265_1 = 32'd1426150400 >> { n1012, N_N4193, NSr5_5, NDN5_5, PRESET }; + assign n340 = 32'd2934604872 >> { n1134, n1163, n1124, n1139, N_N4018 }; + assign n1163 = 8'hb2 >> { n1111, N_N3996, n1121 }; + assign n1515_1 = 16'haaae >> { n970_1, PRESET, N_N3713, n1165 }; + assign n1165 = 32'd2290254370 >> { n1055_1, n1075_1, n1076, n1166, n1167 }; + assign n1166 = 4'h1 >> { n1073, n1074 }; + assign n1167 = 4'h2 >> { PRESET, n970_1 }; + assign n1075 = 32'd1426150400 >> { n1084, N_N3711, NSr5_3, NDN5_3, PRESET }; + assign n830 = 32'd1426150400 >> { Paport_10_10_, N_N3882, NDN3_3, NSr3_2, PRESET }; + assign n770 = 32'd1426150400 >> { n1082, N_N3793, NSr5_5, NDN5_5, PRESET }; + assign n1505_1 = 32'd321978912 >> { N_N3684, n1172, n984, PRESET, n969 }; + assign n1172 = 4'h9 >> { n982, n983 }; + assign n1040 = 64'hfffff222f222f222 >> { n954, N_N3791, n953, N_N3533, n950_1, N_N4252 }; + assign n150 = 64'hfffff222f222f222 >> { n954, N_N3489, n953, N_N3105, n950_1, N_N3843 }; + assign n650 = 32'd823336962 >> { N_N3743, n1177, n1176, PRESET, n970_1 }; + assign n1176 = 8'he8 >> { n1057, n1065_1, n1066 }; + assign n1177 = 4'h1 >> { n1063, n1064 }; + assign n670 = 32'd823336962 >> { N_N3774, n1180_1, n1179, PRESET, n970_1 }; + assign n1179 = 4'h1 >> { n1056, n1071 }; + assign n1180_1 = 4'h1 >> { n1069, n1070_1 }; + assign n955 = 32'd1426150400 >> { n1052, N_N3663, NSr5_2, NDN5_2, PRESET }; + assign n260 = 32'd1426150400 >> { n1091, N_N4117, NSr5_3, NDN5_3, PRESET }; + assign n1035 = 32'd1426150400 >> { n1052, N_N3659, NSr5_4, NDN5_4, PRESET }; + assign n695 = 64'h1331311302202002 >> { N_N3791, n1055_1, n1075_1, n1076, PRESET, n970_1 }; + assign n300 = 32'd1426150400 >> { n1096, N_N3922, NSr5_3, NDN5_3, PRESET }; + assign n270 = 32'd823336962 >> { N_N3761, n1188, n1187, PRESET, n1005_1 }; + assign n1187 = 8'h54 >> { n1064, n1176, n1063 }; + assign n1188 = 4'h1 >> { n1071, n1062 }; + assign n1025 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3634 }; + assign n1485_1 = 4'h1 >> { PRESET, NSr5_8 }; + assign n1500_1 = 8'h8a >> { NSr5_8, NEN5_9, n951 }; + assign n615 = 32'd823336962 >> { N_N3709, n1061, n1193, PRESET, n970_1 }; + assign n1193 = 32'd2845418837 >> { n970_1, n1005_1, N_N4057, N_N3793, n1058 }; + assign n280 = 32'd1426150400 >> { n1050_1, N_N4071, NSr5_2, NDN5_2, PRESET }; + assign n810 = 32'd1426150400 >> { n1084, N_N3776, NSr5_5, NDN5_5, PRESET }; + assign n930 = 32'd1426150400 >> { n1052, N_N3612, NDN5_8, NSr5_8, PRESET }; + assign n1065 = 32'd2934604872 >> { n1134, n1109, n1128, n1139, N_N3949 }; + assign n380 = 64'hea48ea48ffffea48 >> { n1022, n1202, n1199, n1203, n1139, N_N4212 }; + assign n1199 = 16'h1101 >> { n1013, n1200_1, n1201, PRESET }; + assign n1200_1 = 16'h1115 >> { n1135_1, n1013, N_N3460, N_N3578 }; + assign n1201 = 64'hcccc8880ccec88a0 >> { N_N4214, N_N3578, n1135_1, n1013, n1136, N_N3460 }; + assign n1202 = 32'd16851713 >> { N_N4214, N_N3460, N_N3578, PRESET, n1013 }; + assign n1203 = 8'h08 >> { N_N4036, N_N4060, n1204 }; + assign n1204 = 16'h0001 >> { N_N3961, N_N4126, N_N4004, N_N4171 }; + assign n415 = 64'hea48ea48ffffea48 >> { n1033, n1202, n1199, n1206, n1139, N_N4171 }; + assign n1206 = 4'h2 >> { N_N4004, n1207 }; + assign n1207 = 8'h02 >> { N_N3961, N_N4126, N_N4060 }; + assign n665 = 32'd1426150400 >> { Paport_2_2_, N_N3733, NDN3_3, NSr3_2, PRESET }; + assign n855 = 64'hfffff222f222f222 >> { N_N3709, n954, n953, N_N3356, n950_1, N_N3918 }; + assign n805 = 8'h5d >> { n950_1, N_N3939, n1211 }; + assign n1211 = 64'hbfbfbfbfaabfbfbf >> { NDN3_8, N_N3741, NDN3_3, N_N3677, NLD3_9, PRESET }; + assign n1140_1 = 8'h5d >> { n950_1, N_N4224, n1213 }; + assign n1213 = 64'hbfbfbfbfaabfbfbf >> { NDN3_8, N_N4106, NDN3_3, N_N3442, NLD3_9, PRESET }; + assign n1345_1 = 32'd1426150400 >> { n1215, N_N3585, NDN5_8, NSr5_8, PRESET }; + assign n1215 = 4'h8 >> { n1013, N_N3949 }; + assign n165 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3580 }; + assign n395 = 64'hfffff222f222f222 >> { N_N3750, n954, n953, N_N3751, n950_1, N_N3890 }; + assign n950 = 32'd823336962 >> { N_N3794, n1061, n1193, PRESET, n1005_1 }; + assign n495 = 32'd1426150400 >> { n1104, N_N3625, NDN5_8, NSr5_8, PRESET }; + assign n490 = 32'd1426150400 >> { n1096, N_N3921, NSr5_4, NDN5_4, PRESET }; + assign n690 = 32'd1426150400 >> { Paport_4_4_, N_N3574, NDN3_3, NSr3_2, PRESET }; + assign n890 = 32'd1426150400 >> { Paport_11_11_, N_N4205, NDN3_3, NSr3_2, PRESET }; + assign n160 = 8'h5d >> { n950_1, N_N4118, n1224 }; + assign n1224 = 64'hbfbfbfbfaabfbfbf >> { NDN3_8, N_N4232, NDN3_3, N_N3179, NLD3_9, PRESET }; + assign n1355_1 = 64'hfffff222f222f222 >> { N_N3336, n954, n953, N_N3373, n950_1, N_N4209 }; + assign n1120 = 64'hfffff222f222f222 >> { n954, N_N3464, n953, N_N3331, n950_1, N_N3500 }; + assign n310 = 32'd823336962 >> { N_N3489, n1229, n1228, PRESET, n1005_1 }; + assign n1228 = 8'h54 >> { n1070_1, n1179, n1069 }; + assign n1229 = 4'h1 >> { n1067, n1068 }; + assign n325 = 16'haaae >> { n1005_1, PRESET, N_N3513, n1231 }; + assign n1231 = 32'd2290254370 >> { n1055_1, n1075_1, n1076, n1166, n1232 }; + assign n1232 = 4'h2 >> { PRESET, n1005_1 }; + assign n195 = 32'd1426150400 >> { n1096, N_N4221, NSr5_2, NDN5_2, PRESET }; + assign n620 = 32'd1426150400 >> { Pdxport_6_6_, N_N4206, NDN3_3, NSr3_2, PRESET }; + assign n1005 = 32'd1426150400 >> { n1012, N_N3482, NSr5_7, NDN5_7, PRESET }; + assign n1340_1 = 64'hfffff222f222f222 >> { N_N4079, n954, n953, N_N4080, n950_1, N_N4176 }; + assign n1405_1 = 32'd823336962 >> { N_N3475, n1066, n1089, PRESET, n970_1 }; + assign n885 = 32'd1426150400 >> { n1012, N_N3473, NSr5_2, NDN5_2, PRESET }; + assign n1440_1 = 4'h8 >> { n951, NDN5_9 }; + assign n1495_1 = 8'ha8 >> { NDN5_9, NEN5_9, n951 }; + assign n505 = 32'd1426150400 >> { n1047, N_N3736, NSr5_7, NDN5_7, PRESET }; + assign n210 = 32'd321978912 >> { N_N3535, n1243, n1059, PRESET, n1005_1 }; + assign n1243 = 32'd2845418837 >> { n970_1, n1005_1, N_N4120, N_N3157, n1060_1 }; + assign n1045 = 32'd2934604872 >> { n1134, n1108, n1132, n1139, N_N3912 }; + assign n860 = 64'hffffffff22282888 >> { n1248, n1246, n1077, n1072, n1247, n1167 }; + assign n1246 = 32'd1431655488 >> { n1074, n1055_1, n1075_1, n1076, n1073 }; + assign n1247 = 64'hfbd9bf15d1f3953f >> { N_N4208, N_N4237, N_N4236, N_N4209, n1005_1, n970_1 }; + assign n1248 = 8'h02 >> { n970_1, PRESET, N_N4158 }; + assign n1090 = 32'd1426150400 >> { n1087, N_N3436, NSr5_3, NDN5_3, PRESET }; + assign n335 = 32'd1426150400 >> { n1215, N_N3841, NSr5_3, NDN5_3, PRESET }; + assign n1275 = 32'd1426150400 >> { n1084, N_N3424, NSr5_4, NDN5_4, PRESET }; + assign n850 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3417 }; + assign n245 = 64'hfffff222f222f222 >> { n954, N_N3212, n953, N_N3196, n950_1, N_N3842 }; + assign n105 = 64'hfffff222f222f222 >> { N_N3981, n954, n953, N_N3250, n950_1, N_N3924 }; + assign n85 = 8'h5d >> { n950_1, N_N4119, n1256 }; + assign n1256 = 64'hbfbfbfbfaabfbfbf >> { NDN3_8, N_N3580, NDN3_3, N_N3535, NLD3_9, PRESET }; + assign n1310_1 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3517 }; + assign n445 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3681 }; + assign n480 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3716 }; + assign n610 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3373 }; + assign n1240_1 = 32'd1426150400 >> { n1082, N_N3367, NSr5_4, NDN5_4, PRESET }; + assign n1205 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3533 }; + assign n180 = 64'hfffff222f222f222 >> { N_N3513, n954, n953, N_N3062, n950_1, N_N3808 }; + assign n455 = 64'hea48ea48ffffea48 >> { n1037, n1202, n1199, n1265, n1139, N_N3340 }; + assign n1265 = 16'h0002 >> { N_N4246, N_N3369, N_N3283, n1266 }; + assign n1266 = 4'h2 >> { N_N4093, n1267 }; + assign n1267 = 4'h2 >> { N_N4212, n1203 }; + assign n1210 = 64'hffffffff22282888 >> { n1269, n1246, n1077, n1072, n1247, n1232 }; + assign n1269 = 8'h02 >> { n1005_1, PRESET, N_N3336 }; + assign n225 = 32'd1426150400 >> { n1079, N_N4180, NSr5_2, NDN5_2, PRESET }; + assign n1070 = 64'h1331311302202002 >> { N_N3908, n1055_1, n1075_1, n1076, PRESET, n1005_1 }; + assign n1235 = 32'd823336962 >> { N_N3884, n1077, n1054, PRESET, n1005_1 }; + assign n925 = 32'd1426150400 >> { n1084, N_N3323, NSr5_2, NDN5_2, PRESET }; + assign n1285 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3393 }; + assign n465 = 64'hfffff222f222f222 >> { N_N3931, n954, n953, N_N3932, n950_1, N_N3810 }; + assign n430 = 64'hfffff222f222f222 >> { n954, N_N3875, n953, N_N3876, n950_1, N_N3844 }; + assign n230 = 32'd1426150400 >> { n1050_1, N_N3311, NSr5_5, NDN5_5, PRESET }; + assign n1455_1 = 32'd1426150400 >> { Paport_3_3_, N_N3778, NDN3_3, NSr3_2, PRESET }; + assign n440 = 64'hffffaaeaffff8848 >> { n1199, n1280, N_N3961, N_N4060, n1139, N_N4126 }; + assign n1280 = 4'h2 >> { n1027, n1202 }; + assign n355 = 64'hea48ea48ffffea48 >> { n1479, n1202, n1199, n1266, n1139, N_N4246 }; + assign n880 = 32'd321978912 >> { N_N3274, n1283, n993, PRESET, n969 }; + assign n1283 = 16'ha665 >> { n960_1, n996, n998, n997 }; + assign n700 = 32'd321978912 >> { N_N3480, n1285_1, n1286, PRESET, n969 }; + assign n1285_1 = 8'h8e >> { n982, n983, n984 }; + assign n1286 = 8'h69 >> { n980_1, n981, n966 }; + assign n710 = 8'h5d >> { n950_1, N_N3940, n1288 }; + assign n1288 = 64'hbfbfbfbfaabfbfbf >> { NDN3_8, N_N4218, NDN3_3, N_N4111, NLD3_9, PRESET }; + assign n550 = 32'd1426150400 >> { n1087, N_N3700, NDN5_8, NSr5_8, PRESET }; + assign n190 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3250 }; + assign n220 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3248 }; + assign n1080 = 64'h3113133120020220 >> { N_N3931, n1098, n990_1, n992, PRESET, n970_1 }; + assign n715 = 64'h3113133120020220 >> { N_N3509, n1294, n978, n985_1, PRESET, n969 }; + assign n1294 = 8'hb2 >> { n979, n987, n986 }; + assign n740 = 32'd823336962 >> { N_N3529, n1297, n1296, PRESET, n969 }; + assign n1296 = 8'h8e >> { n976, n977, n989 }; + assign n1297 = 8'h69 >> { n962, n971, n988 }; + assign n1480_1 = 4'h1 >> { PRESET, NSr5_7 }; + assign n405 = 8'ha2 >> { NDN5_10, NSr5_7, n951 }; + assign n185 = 8'h5d >> { n950_1, N_N3923, n1301 }; + assign n1301 = 64'hbfbfbfbfaabfbfbf >> { NDN3_8, N_N4230, NDN3_3, N_N3475, NLD3_9, PRESET }; + assign n295 = 32'd2934604872 >> { n1134, n1303, n1130_1, n1139, N_N4145 }; + assign n1303 = 8'hb2 >> { n1109, N_N3949, n1128 }; + assign n205 = 32'd321978912 >> { N_N3464, n1172, n984, PRESET, n970_1 }; + assign n235 = 16'h3120 >> { N_N3442, n1141, PRESET, n970_1 }; + assign n1425_1 = 32'd823336962 >> { N_N3214, n1188, n1187, PRESET, n970_1 }; + assign n1465_1 = 32'd823336962 >> { N_N3212, n1229, n1228, PRESET, n970_1 }; + assign n1015 = 32'd1426150400 >> { n1104, N_N3304, NSr5_3, NDN5_3, PRESET }; + assign n1055 = 32'd1426150400 >> { n1082, N_N3221, NSr5_3, NDN5_3, PRESET }; + assign n1190_1 = 32'd1426150400 >> { n1096, N_N3205, NSr5_7, NDN5_7, PRESET }; + assign n1225_1 = 32'd1426150400 >> { n1079, N_N3203, NSr5_7, NDN5_7, PRESET }; + assign n840 = 64'hfffff222f222f222 >> { n954, N_N3908, n953, N_N3634, n950_1, N_N3800 }; + assign n1125 = 32'd2934604872 >> { n1134, n1111, n1121, n1139, N_N3996 }; + assign n1410_1 = 32'd1426150400 >> { Pdxport_7_7_, N_N4132, NDN3_3, NSr3_2, PRESET }; + assign n1430_1 = 32'd1426150400 >> { Pdxport_9_9_, N_N4070, NDN3_3, NSr3_2, PRESET }; + assign n845 = 32'd1426150400 >> { Pdxport_11_11_, N_N4237, NDN3_3, NSr3_2, PRESET }; + assign n1195 = 64'hfffff222f222f222 >> { n954, N_N3516, n953, N_N3517, n950_1, N_N4136 }; + assign n1170_1 = 64'hfffff222f222f222 >> { n954, N_N3420, n953, N_N3393, n950_1, N_N4183 }; + assign n535 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3932 }; + assign n1395_1 = 32'd321978912 >> { N_N3179, n1243, n1059, PRESET, n970_1 }; + assign n1030 = 32'd1426150400 >> { n1047, N_N3293, NSr5_2, NDN5_2, PRESET }; + assign n170 = 32'd1426150400 >> { n1091, N_N3175, NSr5_2, NDN5_2, PRESET }; + assign n360 = 32'd1426150400 >> { n1050_1, N_N3806, NSr5_3, NDN5_3, PRESET }; + assign n985 = 32'd1426150400 >> { n1052, N_N3433, NSr5_3, NDN5_3, PRESET }; + assign n1110 = 64'hea48ea48ffffea48 >> { n1481, n1202, n1199, n1326, n1139, N_N3369 }; + assign n1326 = 4'h2 >> { N_N4246, n1266 }; + assign n1420_1 = 32'd1426150400 >> { Paport_1_1_, N_N3797, NDN3_3, NSr3_2, PRESET }; + assign n385 = 32'd1426150400 >> { n1104, N_N3626, NSr5_7, NDN5_7, PRESET }; + assign n780 = 64'hfffff222f222f222 >> { N_N3862, n954, n953, N_N3280, n950_1, N_N3813 }; + assign n435 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3196 }; + assign n1135 = 64'hea48ea48ffffea48 >> { n1030_1, n1202, n1199, n1267, n1139, N_N4093 }; + assign n600 = 32'd1426150400 >> { Pdxport_4_4_, N_N4165, NDN3_3, NSr3_2, PRESET }; + assign n815 = 32'd1426150400 >> { n1104, N_N3387, NSr5_2, NDN5_2, PRESET }; + assign n1115 = 32'd1426150400 >> { n1047, N_N3164, NSr5_3, NDN5_3, PRESET }; + assign n140 = 32'd1426150400 >> { n1096, N_N3143, NSr5_5, NDN5_5, PRESET }; + assign n525 = 32'd1426150400 >> { n1215, N_N3840, NSr5_4, NDN5_4, PRESET }; + assign n545 = 32'd1426150400 >> { n1050_1, N_N3805, NSr5_4, NDN5_4, PRESET }; + assign n1365_1 = 64'hfffff222f222f222 >> { N_N4158, n954, n953, N_N4159, n950_1, N_N4208 }; + assign n290 = 64'hfffff222f222f222 >> { N_N3713, n954, n953, N_N3235, n950_1, N_N3807 }; + assign n125 = 64'hfffff222f222f222 >> { N_N3761, n954, n953, N_N3248, n950_1, N_N3872 }; + assign n1050 = 32'd823336962 >> { N_N3862, n1180_1, n1179, PRESET, n1005_1 }; + assign n500 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3751 }; + assign n1060 = 32'd823336962 >> { N_N3875, n1297, n1296, PRESET, n970_1 }; + assign n390 = 8'hea >> { n1134, N_N3965, n1345 }; + assign n1345 = 64'h8222822222228222 >> { n1018, N_N3971, n1113, n1114, N_N3965, n1139 }; + assign n250 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3105 }; + assign n870 = 32'd1426150400 >> { n1082, N_N3344, NSr5_2, NDN5_2, PRESET }; + assign n940 = 32'd1426150400 >> { n1012, N_N3457, NSr5_3, NDN5_3, PRESET }; + assign n1200 = 32'd1426150400 >> { n1104, N_N3303, NSr5_4, NDN5_4, PRESET }; + assign n1160_1 = 64'h88f888f8ffff88f8 >> { n1351, n1139, n1042, n1202, n1199, N_N4036 }; + assign n1351 = 8'h95 >> { n1204, N_N4060, N_N4036 }; + assign n1185 = 64'hea48ea48ffffea48 >> { n1035_1, n1202, n1199, n1207, n1139, N_N4004 }; + assign n1330_1 = 64'hfffff222f222f222 >> { N_N3884, n954, n953, N_N3011, n950_1, N_N4177 }; + assign n1010 = 32'd823336962 >> { N_N3832, n1177, n1176, PRESET, n1005_1 }; + assign n1295 = 32'd1426150400 >> { n1087, N_N3188, NSr5_4, NDN5_4, PRESET }; + assign n175 = 32'd1426150400 >> { n1079, N_N3071, NSr5_5, NDN5_5, PRESET }; + assign n200 = 32'd1426150400 >> { n1215, N_N3069, NSr5_5, NDN5_5, PRESET }; + assign n635 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4159 }; + assign n1220_1 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3331 }; + assign n475 = 64'h5d5d5d5d5d5dff5d >> { n1362, PRESET, N_N3283, n1020_1, n1202, n1361 }; + assign n1361 = 32'd2004289399 >> { n1200_1, n1134, N_N3283, n1139, n1265 }; + assign n1362 = 32'd353713941 >> { N_N3369, n1326, n1200_1, n1013, n1136 }; + assign n655 = 32'd1426150400 >> { Pdxport_8_8_, N_N4242, NDN3_3, NSr3_2, PRESET }; + assign n820 = 32'd1426150400 >> { Pdxport_10_10_, N_N4194, NDN3_3, NSr3_2, PRESET }; + assign n320 = 32'd321978912 >> { N_N3540, n1154, n996, PRESET, n970_1 }; + assign n450 = 32'd1426150400 >> { n1084, N_N3679, NSr5_7, NDN5_7, PRESET }; + assign n485 = 32'd1426150400 >> { n1087, N_N3701, NSr5_7, NDN5_7, PRESET }; + assign n1020 = 64'h3113133120020220 >> { N_N3750, n1294, n978, n985_1, PRESET, n970_1 }; + assign n590 = 64'h4444444444444454 >> { NDN2_2, NLC1_2, PDN, Preset_0_0_, N_N3346, PRESET }; + assign n1270_1 = 64'hfffff222f222f222 >> { N_N3821, n954, n953, N_N3822, n950_1, N_N3470 }; + assign n1260_1 = 32'd1426150400 >> { n1215, N_N3100, NSr5_7, NDN5_7, PRESET }; + assign n1095 = 32'd2934604872 >> { n1134, n1110_1, n1126, n1139, N_N3974 }; + assign n555 = 32'd1426150400 >> { n1047, N_N3735, NDN5_8, NSr5_8, PRESET }; + assign n825 = 32'd321978912 >> { N_N3821, n1283, n993, PRESET, n970_1 }; + assign n605 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N4080 }; + assign n275 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3062 }; + assign n900 = 16'h3120 >> { N_N3680, n1152, PRESET, n970_1 }; + assign n960 = 32'd321978912 >> { N_N3715, n1285_1, n1286, PRESET, n970_1 }; + assign n775 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3822 }; + assign n570 = 32'd1426150400 >> { Pdxport_0_0_, N_N3906, NDN3_3, NSr3_2, PRESET }; + assign n595 = 16'h3120 >> { N_N3677, n1004, PRESET, n970_1 }; + assign n255 = 32'd1426150400 >> { n1215, N_N4133, NSr5_2, NDN5_2, PRESET }; + assign n305 = 32'd823336962 >> { N_N3516, n975_1, n1147, PRESET, n970_1 }; + assign n725 = 64'h4444444444444454 >> { NDN2_2, NLC1_2, PDN, Preset_0_0_, N_N2989, PRESET }; + assign n910 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3262 }; + assign n970 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3280 }; + assign n1145_1 = 32'd3937290372 >> { n1134, n1112, n1115_1, n1139, N_N4027 }; + assign n1130 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3356 }; + assign n1155_1 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3384 }; + assign n1320_1 = 32'd1426150400 >> { n1079, N_N3081, NDN5_8, NSr5_8, PRESET }; + assign n865 = 32'd1426150400 >> { n1087, N_N3630, NSr5_5, NDN5_5, PRESET }; + assign n920 = 32'd1426150400 >> { n1047, N_N3607, NSr5_5, NDN5_5, PRESET }; + assign n470 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3235 }; + assign n265 = 16'h1302 >> { N_N3420, n1143, PRESET, n970_1 }; + assign n120 = 32'd1426150400 >> { n1091, N_N3157, NSr5_5, NDN5_5, PRESET }; + assign n585 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3011 }; + assign n1215_1 = 64'hea48ea48ffffea48 >> { n1024, n1202, n1199, N_N4060, n1139, N_N3961 }; + assign n330 = 32'd2934604872 >> { n1134, n1399, n1483, n1139, N_N4083 }; + assign n1399 = 8'hb2 >> { n1110_1, N_N3974, n1126 }; + assign n1325_1 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3541 }; + assign n795 = 16'h2220 >> { NSr3_2, NDN3_3, PRESET, N_N3866 }; + assign n755 = 64'hfffff222f222f222 >> { N_N3832, n954, n953, N_N3262, n950_1, N_N3868 }; + assign n730 = 64'hfffff222f222f222 >> { N_N3794, n954, n953, N_N3417, n950_1, N_N3919 }; + assign n575 = 64'h4444444444444454 >> { NDN2_2, NLC1_2, PDN, Preset_0_0_, N_N3388, PRESET }; + assign n215 = 64'hfffff222f222f222 >> { n954, N_N3214, n953, N_N3786, n950_1, N_N3871 }; + assign n540 = 4'h1 >> { PDN, PRESET }; + assign n1530_1 = 8'h5d >> { n1408, NSr3_2, n540 }; + assign n1408 = 64'h00080000000a0002 >> { Preset_0_0_, N_N3998, PDN, NLak3_2, NLC1_2, Pready_0_0_ }; + assign n1535_1 = 64'hdddddddd5ddddddd >> { NLak3_9, NAK5_2, NSr3_9, NDN3_8, NSr5_2, n951 }; + assign n1540_1 = 16'hdd5d >> { NSr5_2, NAK5_2, NSr5_3, n951 }; + assign n1545_1 = 4'hd >> { n1412, n1413 }; + assign n1412 = 4'h2 >> { n1485, N_N3462 }; + assign n1413 = 4'h2 >> { PRESET, n1414 }; + assign n1414 = 8'ha8 >> { n1135_1, n1013, N_N3460 }; + assign n1550_1 = 8'hfd >> { n1412, n1135_1, n1413 }; + assign n1555_1 = 16'hdd5d >> { NSr5_3, NAK5_2, NSr5_4, n951 }; + assign n1560_1 = 16'h5ddd >> { NDN3_8, n1418, NSr3_9, n540 }; + assign n1418 = 16'h088a >> { n1419, N_N4205, N_N3336, NLD3_9 }; + assign n1419 = 32'd3722265812 >> { n1420, N_N3513, N_N3818, N_N3882, N_N3884 }; + assign n1420 = 32'd1296891981 >> { N_N3818, N_N3513, n1421, N_N4015, N_N3908 }; + assign n1421 = 32'd2364475598 >> { n1422, N_N4054, N_N4243, N_N3489, N_N3862 }; + assign n1422 = 32'd3149603506 >> { n1423, N_N3574, N_N3832, N_N4056, N_N3761 }; + assign n1423 = 32'd1296891981 >> { N_N3832, N_N3574, n1424, N_N3981, N_N3778 }; + assign n1424 = 64'h08ffceff000800ce >> { N_N3733, N_N3535, N_N3794, N_N4111, N_N3797, N_N3916 }; + assign n1565_1 = 16'hdd5d >> { NSr5_4, NAK5_2, NSr5_5, n951 }; + assign n1570_1 = 16'hdd5d >> { NSr5_5, NAK5_2, NSr5_7, n951 }; + assign n1575_1 = 16'habbb >> { n1480_1, NAK5_2, n1485_1, NLD3_9 }; + assign n1580_1 = 32'd4272619435 >> { Preset_0_0_, N_N3998, PDN, NLC1_2, PRESET }; + assign n285 = 64'h2212001022122212 >> { n1433, N_N4214, n1430, n1136, PRESET, N_N4227 }; + assign n1430 = 64'haa6a5a566a5a5655 >> { n1108, n1137, n1132, N_N4197, N_N3912, n1431 }; + assign n1431 = 32'd9079434 >> { N_N3663, n1016, N_N4095, n1018, n1432 }; + assign n1432 = 64'h0000077707770777 >> { n1017, N_N4237, n1015_1, N_N3905, n1014, N_N3445 }; + assign n1433 = 8'h08 >> { n1135_1, n1013, N_N3460 }; + assign n1385_1 = 8'ha8 >> { N_N3999, n1433, n1413 }; + assign n745 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4222, PRESET }; + assign n1100 = 64'h4444444444444404 >> { NDN2_2, PDN, NLC1_2, Preset_0_0_, N_N3905, PRESET }; + assign n1350_1 = 16'h1110 >> { NDN3_8, NDN3_3, PRESET, NGFDN_3 }; + assign n1460_1 = 4'h1 >> { PRESET, NSr5_4 }; + assign n1375_1 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3708, PRESET }; + assign n115 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3691, PRESET }; + assign n640 = 4'h1 >> { n1414, PRESET }; + assign n63 = 16'h88a8 >> { NLC1_2, Preset_0_0_, NGFDN_3, n540 }; + assign n1335_1 = 16'h1011 >> { NSr3_2, NDN3_3, PRESET, NGFDN_3 }; + assign n1250 = 32'd572661794 >> { NLC1_2, Preset_0_0_, PDN, PRESET, NDN2_2 }; + assign n565 = 4'h2 >> { PRESET, n1418 }; + assign n905 = 8'h54 >> { N_N3838, n1433, PRESET }; + assign n155 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3426, PRESET }; + assign n765 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4181, PRESET }; + assign n735 = 4'h8 >> { n1413, N_N3578 }; + assign n135 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3375, PRESET }; + assign n1470_1 = 4'h1 >> { PRESET, NSr5_5 }; + assign n1490_1 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4073, PRESET }; + assign n675 = 16'h2220 >> { N_N4214, n1433, PRESET, n1412 }; + assign n630 = 4'h2 >> { PRESET, n1485 }; + assign n1390_1 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4223, PRESET }; + assign n1150_1 = 4'h8 >> { n540, NDN1_4 }; + assign n400 = 8'h02 >> { PRESET, NGFDN_3, NDN3_11 }; + assign n875 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4072, PRESET }; + assign n1445_1 = 4'h1 >> { PRESET, NSr5_2 }; + assign n790 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4134, PRESET }; + assign n945 = 64'h4444444444444404 >> { NDN2_2, PDN, NLC1_2, Preset_0_0_, N_N3445, PRESET }; + assign n625 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3324, PRESET }; + assign n100 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3345, PRESET }; + assign n420 = 4'h8 >> { n951, NDN5_16 }; + assign n1450_1 = 4'h1 >> { PRESET, NSr5_3 }; + assign n995 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3468, PRESET }; + assign n1475_1 = 32'd2290657416 >> { NLak3_9, NSr3_9, NDN3_8, NDN5_6, n951 }; + assign n1085 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3469, PRESET }; + assign n560 = 8'h08 >> { PRESET, n1408, NSr3_2 }; + assign n660 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3312, PRESET }; + assign n680 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N3294, PRESET }; + assign n1415_1 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4182, PRESET }; + assign n1435_1 = 64'h4444444444444404 >> { PDN, NDN2_2, NLC1_2, Preset_0_0_, N_N4135, PRESET }; + assign n1525_1 = 32'd285326091 >> { n1139, n1039, n1202, n1199, N_N4060 }; + assign n1175_1 = 8'h01 >> { PRESET, NSr3_9, NGFDN_3 }; + assign n71 = 32'd1145373701 >> { NDN3_11, NSr3_9, NGFDN_3, Pover_0_0_, PRESET }; + assign n67 = 32'd1162085636 >> { NDN5_16, NDN5_9, NLD3_9, Pnext_0_0_, PRESET }; + assign n1478 = 64'h0000770777077707 >> { n1017, N_N4047, n1018, N_N4242, N_N3164, n1016 }; + assign n1479 = 64'h8088c4ccc4ccc4cc >> { NSr5_4, N_N4252, N_N3800, NSr5_2, n1478, NSr5_3 }; + assign n1480 = 64'h0000770777077707 >> { n1017, N_N3805, n1018, N_N4070, N_N3806, n1016 }; + assign n1481 = 64'h8088c4ccc4ccc4cc >> { NSr5_4, N_N3807, N_N3808, NSr5_2, n1480, NSr5_3 }; + assign n1482 = 64'h00000ddd0ddd0ddd >> { N_N3988, n1016, n1017, N_N4206, n1018, N_N3844 }; + assign n1483 = 64'h8088c4ccc4ccc4cc >> { NSr5_4, N_N3375, N_N3312, NSr5_2, n1482, NSr5_3 }; + assign n1484 = 64'h0000000000000001 >> { N_N4036, N_N3340, N_N4093, N_N4246, N_N3369, N_N3283 }; + assign n1485 = 32'd128 >> { N_N4212, N_N4060, n1484, n1136, n1204 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act b/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act new file mode 100644 index 000000000..0f519b264 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act @@ -0,0 +1,1115 @@ +clock 0.491200 0.491000 +pcount_3_ 0.501000 0.506000 +pkey_5_ 0.517400 0.502800 +pkey_131_ 0.494400 0.501400 +pkey_144_ 0.488000 0.493800 +pkey_157_ 0.490800 0.504000 +pkey_230_ 0.497200 0.496800 +pkey_243_ 0.507200 0.501200 +pcount_2_ 0.505600 0.504800 +pkey_4_ 0.507400 0.490600 +pkey_132_ 0.493400 0.508600 +pkey_158_ 0.501200 0.506400 +pkey_169_ 0.513400 0.497800 +pkey_242_ 0.499400 0.504200 +pcount_1_ 0.488800 0.493400 +pkey_146_ 0.502400 0.498200 +pkey_168_ 0.498200 0.490200 +pkey_245_ 0.493800 0.493000 +pcount_0_ 0.510600 0.495400 +pkey_6_ 0.498600 0.487800 +pkey_130_ 0.499400 0.503000 +pkey_145_ 0.504000 0.507600 +pkey_244_ 0.506600 0.507200 +pkey_9_ 0.493000 0.512200 +pkey_16_ 0.497000 0.497800 +pkey_27_ 0.501800 0.509000 +pkey_38_ 0.500800 0.496600 +pkey_49_ 0.488000 0.499400 +pkey_122_ 0.501000 0.485200 +pkey_148_ 0.507800 0.498400 +pkey_153_ 0.495600 0.493600 +pkey_166_ 0.499800 0.513800 +pkey_221_ 0.495800 0.490400 +pkey_252_ 0.489800 0.499000 +pkey_8_ 0.497000 0.497600 +pkey_17_ 0.499800 0.499400 +pkey_26_ 0.505400 0.508200 +pkey_48_ 0.497200 0.500800 +pkey_110_ 0.508600 0.495200 +pkey_121_ 0.499600 0.493400 +pkey_147_ 0.498000 0.496400 +pkey_154_ 0.490600 0.500000 +pkey_165_ 0.509000 0.496000 +pkey_220_ 0.485000 0.500200 +pkey_246_ 0.497400 0.503200 +pkey_253_ 0.501200 0.503200 +pkey_18_ 0.502600 0.504400 +pkey_29_ 0.502200 0.507600 +pkey_36_ 0.500400 0.504200 +pkey_120_ 0.486800 0.510800 +pkey_155_ 0.506600 0.485600 +pkey_164_ 0.495800 0.503000 +pkey_210_ 0.508800 0.514600 +pkey_249_ 0.492600 0.502000 +pkey_254_ 0.511600 0.511200 +pkey_19_ 0.509200 0.507600 +pkey_28_ 0.505200 0.506000 +pkey_37_ 0.503000 0.506000 +pkey_46_ 0.494000 0.503400 +pkey_112_ 0.490200 0.508800 +pkey_149_ 0.495600 0.490200 +pkey_156_ 0.501600 0.503600 +pkey_163_ 0.503400 0.486600 +pkey_211_ 0.493600 0.491000 +pkey_248_ 0.493600 0.488200 +pkey_56_ 0.506400 0.484800 +pkey_67_ 0.505600 0.509600 +pkey_78_ 0.502600 0.497200 +pkey_89_ 0.488600 0.503000 +pkey_113_ 0.500600 0.502800 +pkey_126_ 0.515800 0.495600 +pkey_139_ 0.509200 0.504600 +pkey_162_ 0.499200 0.499400 +pkey_212_ 0.494000 0.503000 +pkey_225_ 0.507800 0.502600 +pkey_238_ 0.496000 0.500200 +pkey_57_ 0.498800 0.494000 +pkey_66_ 0.497400 0.506800 +pkey_88_ 0.496800 0.507400 +pkey_114_ 0.496000 0.491800 +pkey_125_ 0.508000 0.500200 +pkey_150_ 0.509600 0.499200 +pkey_161_ 0.503800 0.501800 +pkey_213_ 0.508000 0.502800 +pkey_224_ 0.501200 0.495800 +pkey_58_ 0.497000 0.498800 +pkey_69_ 0.501000 0.488400 +pkey_76_ 0.496800 0.502000 +pkey_115_ 0.505400 0.487000 +pkey_124_ 0.496400 0.498000 +pkey_137_ 0.495800 0.507200 +pkey_160_ 0.499200 0.491400 +pkey_214_ 0.511600 0.489800 +pkey_250_ 0.500400 0.497800 +pkey_59_ 0.498800 0.503400 +pkey_68_ 0.505200 0.506000 +pkey_77_ 0.504800 0.511000 +pkey_86_ 0.511800 0.499600 +pkey_116_ 0.499600 0.510200 +pkey_123_ 0.507600 0.495200 +pkey_138_ 0.502000 0.501400 +pkey_152_ 0.500200 0.505600 +pkey_222_ 0.504200 0.503000 +pkey_237_ 0.490400 0.491200 +pkey_251_ 0.500600 0.504600 +pkey_1_ 0.497200 0.502000 +pkey_96_ 0.512200 0.486200 +pkey_117_ 0.488200 0.502600 +pkey_140_ 0.490200 0.493000 +pkey_216_ 0.508000 0.510200 +pkey_229_ 0.488000 0.497600 +pkey_234_ 0.491000 0.500200 +pkey_0_ 0.486800 0.491600 +pkey_97_ 0.497800 0.496200 +pkey_118_ 0.499600 0.506200 +pkey_129_ 0.499800 0.504200 +pkey_136_ 0.502600 0.506000 +pkey_217_ 0.496200 0.509000 +pkey_228_ 0.489600 0.497200 +pkey_235_ 0.499000 0.500600 +pkey_3_ 0.502400 0.503200 +pkey_98_ 0.494000 0.511400 +pkey_128_ 0.505400 0.497000 +pkey_133_ 0.499800 0.491000 +pkey_142_ 0.500000 0.498800 +pkey_218_ 0.506600 0.507600 +pkey_227_ 0.507800 0.496400 +pkey_232_ 0.490200 0.503400 +pkey_241_ 0.499200 0.507000 +pkey_2_ 0.492400 0.491800 +pkey_99_ 0.494000 0.507200 +pkey_134_ 0.489200 0.484000 +pkey_141_ 0.497600 0.497000 +pkey_219_ 0.498400 0.501800 +pkey_226_ 0.488400 0.490400 +pkey_233_ 0.495600 0.510200 +pkey_240_ 0.496200 0.498600 +pkey_70_ 0.495400 0.505800 +pkey_81_ 0.497800 0.481400 +pkey_92_ 0.486400 0.500800 +pkey_180_ 0.508600 0.505400 +pkey_193_ 0.504800 0.489000 +pkey_80_ 0.524400 0.498800 +pkey_93_ 0.494600 0.495800 +pkey_107_ 0.502000 0.503000 +pkey_194_ 0.504800 0.503400 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0.129000 0.020345 +n861_1 0.501000 0.076583 +n1546 0.492800 0.151716 +n1547 0.127800 0.019831 +n1469 0.505200 0.076365 +n1549_1 0.497400 0.154437 +n1550 0.132800 0.020905 +n1425 0.497200 0.076316 +n1552 0.503400 0.154336 +n1553_1 0.131600 0.020604 +n1740 0.506200 0.076363 +n1555 0.498000 0.153718 +n1556 0.131000 0.020769 +n1249 0.507000 0.076391 +n1558 0.493000 0.156693 +n1559 0.127600 0.019734 +n1177 0.498800 0.076658 +n1561_1 0.501000 0.148012 +n1562 0.125800 0.019935 +n869 0.493800 0.076689 +n1564 0.500600 0.156477 +n1565_1 0.129400 0.020079 +n985 0.500400 0.076561 +n1567 0.501200 0.155087 +n1568 0.129000 0.020768 +n857_1 0.503400 0.076504 +n1570 0.506800 0.155821 +n1571 0.131400 0.020353 +n1445 0.514200 0.076331 +n1573_1 0.500200 0.156463 +n1574 0.133600 0.020853 +n1745 0.511000 0.076290 +n1576 0.484400 0.154762 +n1577_1 0.128600 0.020669 +n1205_1 0.482200 0.077084 +n1579 0.512200 0.154771 +n1580 0.122600 0.020069 +n1009 0.504200 0.076767 +n1582 0.515200 0.153536 +n1583 0.127800 0.020290 +n981 0.498600 0.076612 +n1585_1 0.493800 0.155271 +n1586 0.130800 0.020605 +n1750 0.504200 0.076469 +n1588 0.500200 0.153000 +n1589 0.130200 0.021326 +n853_1 0.506200 0.076309 +n1591 0.497800 0.161234 +n1592 0.130600 0.019838 +n1201_1 0.510400 0.076293 +n1594_1 0.507200 0.156625 +n1595 0.133600 0.020305 +n1217_1 0.499000 0.076423 +n1597 0.494400 0.156456 +n1598 0.130800 0.020085 +n1029_1 0.498800 0.076703 +n1600 0.493800 0.150973 +n1601 0.126400 0.019814 +n901_1 0.496200 0.076778 +n1603 0.493800 0.154675 +n1604_1 0.123000 0.020292 +n1421 0.502000 0.076192 +n1606 0.498800 0.154449 +n1607 0.131200 0.021236 +n949 0.507400 0.076520 +n1609 0.481600 0.156884 +n1610 0.128000 0.019709 +n1329 0.503400 0.076488 +n1612 0.498000 0.151102 +n1613 0.130000 0.020686 +n1261 0.492000 0.077159 +n1615 0.492000 0.154663 +n1616 0.118600 0.019331 +n865 0.492000 0.077059 +n1618 0.504600 0.157164 +n1619 0.126600 0.020578 +n1449 0.504600 0.076392 +n1621 0.482400 0.155914 +n1622 0.127600 0.020219 +n953 0.504000 0.076386 +n1624 0.501600 0.157047 +n1625 0.132600 0.020826 +n1109_1 0.505800 0.076583 +n1627 0.503800 0.154548 +n1628_1 0.135400 0.020922 +n1229 0.500600 0.076628 +n1630 0.489200 0.156674 +n1631 0.129400 0.020733 +n1755_1 0.497800 0.076628 +n1633_1 0.509200 0.149046 +n1634 0.129200 0.019899 +n1760 0.500400 0.076808 +n1636 0.517600 0.156835 +n1637 0.127800 0.019624 +n1765 0.509000 0.076186 +n1639 0.498200 0.152007 +n1640 0.137200 0.020139 +n997 0.512400 0.076288 +n1642 0.499000 0.153508 +n1643 0.130600 0.020009 +n917 0.502800 0.076399 +n1645 0.499200 0.152743 +n1646 0.130000 0.019632 +n1133 0.488200 0.076885 +n1648_1 0.508000 0.158710 +n1649 0.126000 0.020634 +n1181 0.505200 0.076372 +n1651 0.493400 0.159408 +n1652 0.134600 0.020651 +n1121_1 0.486600 0.076411 +n1654 0.511200 0.154029 +n1655 0.129800 0.020073 +n1169 0.504200 0.076438 +n1657 0.497800 0.149712 +n1658_1 0.127800 0.020202 +n1770 0.501200 0.076398 +n1660 0.500400 0.151744 +n1661 0.133400 0.020092 +n1025_1 0.503200 0.076402 +n1663 0.508200 0.150885 +n1664 0.131800 0.020697 +n1085 0.496200 0.076526 +n1666 0.509200 0.148920 +n1667 0.129800 0.020725 +n1197 0.495400 0.077242 +n1669 0.503200 0.151717 +n1670 0.125200 0.019109 +n1173 0.482800 0.076958 +n1672 0.492000 0.155766 +n1673_1 0.123600 0.020345 +n1377 0.492200 0.076765 +n1675 0.516600 0.152243 +n1676 0.126400 0.020487 +n977 0.495000 0.076429 +n1678_1 0.517200 0.155137 +n1679 0.135600 0.021371 +n1157 0.504800 0.076347 +n1681 0.493600 0.156957 +n1682_1 0.134000 0.020475 +n1775 0.497200 0.076946 +n1684 0.510200 0.153436 +n1685 0.125600 0.019361 +n1780 0.504600 0.076875 +n1687 0.503200 0.153787 +n1688 0.126000 0.019982 +n1517 0.497600 0.076939 +n1690 0.509400 0.153579 +n1691 0.126000 0.020036 +n1237 0.504800 0.077241 +n1693 0.509400 0.156818 +n1694 0.126200 0.020533 +pnew_count_0_ 0.492600 0.128148 +pdata_ready_0_ 0.031600 0.000929 +pnew_count_3_ 0.499600 0.026961 +pnew_count_2_ 0.495400 0.017405 +pnew_count_1_ 0.504200 0.022907 +n1145 0.487800 0.076283 +n1701 0.503800 0.152688 +n1702 0.129800 0.019792 +n1369 0.497000 0.076775 +n1704 0.496600 0.150484 +n1705 0.127800 0.019381 +n1589_1 0.502400 0.076684 +n1707 0.496400 0.162358 +n1708 0.130000 0.019313 +n1461 0.503400 0.076095 +n1710 0.492000 0.154682 +n1711_1 0.133000 0.020551 +n1529 0.491000 0.076764 +n1713 0.508000 0.155039 +n1714 0.126200 0.019973 +n1715_1 0.509800 0.088342 +n1577 0.501600 0.037376 +n1717 0.511000 0.088142 +n1117_1 0.516400 0.037404 +n1719 0.515600 0.088637 +n1594 0.504800 0.036761 +n1721 0.500000 0.088121 +n1345 0.490600 0.037676 +n1723 0.511000 0.088191 +n1599 0.495400 0.038270 +n1725_1 0.515200 0.088648 +n1604 0.512600 0.038109 +n1727 0.505800 0.088558 +n1609_1 0.500600 0.037605 +n1729 0.508000 0.088339 +n1561 0.502800 0.038372 +n1731 0.507000 0.088498 +n937 0.501400 0.036850 +n1733 0.509800 0.088479 +n1545 0.497400 0.038193 +n1735 0.514000 0.088491 +n965 0.513800 0.037196 +n1737 0.517200 0.088345 +n1341 0.508800 0.037783 +n1739 0.506000 0.088004 +n1513 0.499600 0.037375 +n1741 0.498200 0.088116 +n913 0.486800 0.037081 +n1743 0.509600 0.088400 +n1333 0.503400 0.036207 +n1745_1 0.507400 0.088285 +n1569 0.487800 0.036963 +n1747 0.513800 0.088334 +n1565 0.508000 0.037974 +n1749 0.507600 0.088492 +n993 0.489600 0.037625 +n1751 0.503800 0.088488 +n1701_1 0.483000 0.038087 +n1753 0.507400 0.088303 +n1097 0.494400 0.038543 +n1755 0.505800 0.088481 +n1245 0.492200 0.037859 +n1757 0.509400 0.088255 +n1153 0.506200 0.037458 +pksi_143_ 0.502800 0.254619 +pksi_181_ 0.487400 0.240581 +pksi_191_ 0.500600 0.250100 +pksi_90_ 0.508200 0.250644 diff --git a/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif b/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif new file mode 100644 index 000000000..d52878176 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif @@ -0,0 +1,2780 @@ +# Benchmark "dsip" written by ABC on Tue Mar 12 09:39:42 2019 +.model dsip +.inputs clock pcount_3_ pkey_5_ pkey_131_ pkey_144_ pkey_157_ pkey_230_ \ + pkey_243_ pcount_2_ pkey_4_ pkey_132_ pkey_158_ pkey_169_ pkey_242_ \ + pcount_1_ pkey_146_ pkey_168_ pkey_245_ pcount_0_ pkey_6_ pkey_130_ \ + pkey_145_ pkey_244_ pkey_9_ pkey_16_ pkey_27_ pkey_38_ pkey_49_ pkey_122_ \ + pkey_148_ pkey_153_ pkey_166_ pkey_221_ pkey_252_ pkey_8_ pkey_17_ \ + pkey_26_ pkey_48_ pkey_110_ pkey_121_ pkey_147_ pkey_154_ pkey_165_ \ + pkey_220_ pkey_246_ pkey_253_ pkey_18_ pkey_29_ pkey_36_ pkey_120_ \ + pkey_155_ pkey_164_ pkey_210_ pkey_249_ pkey_254_ pkey_19_ pkey_28_ \ + pkey_37_ pkey_46_ pkey_112_ pkey_149_ pkey_156_ pkey_163_ pkey_211_ \ + pkey_248_ pkey_56_ pkey_67_ pkey_78_ pkey_89_ pkey_113_ pkey_126_ \ + pkey_139_ pkey_162_ pkey_212_ pkey_225_ pkey_238_ pkey_57_ pkey_66_ \ + pkey_88_ pkey_114_ pkey_125_ pkey_150_ pkey_161_ pkey_213_ pkey_224_ \ + pkey_58_ pkey_69_ pkey_76_ pkey_115_ pkey_124_ pkey_137_ pkey_160_ \ + pkey_214_ pkey_250_ pkey_59_ pkey_68_ pkey_77_ pkey_86_ pkey_116_ \ + pkey_123_ pkey_138_ pkey_152_ pkey_222_ pkey_237_ pkey_251_ pkey_1_ \ + pkey_96_ pkey_117_ pkey_140_ pkey_216_ pkey_229_ pkey_234_ pkey_0_ \ + pkey_97_ pkey_118_ pkey_129_ pkey_136_ pkey_217_ pkey_228_ pkey_235_ \ + pkey_3_ pkey_98_ pkey_128_ pkey_133_ pkey_142_ pkey_218_ pkey_227_ \ + pkey_232_ pkey_241_ pkey_2_ pkey_99_ pkey_134_ pkey_141_ pkey_219_ \ + pkey_226_ pkey_233_ pkey_240_ pkey_70_ pkey_81_ pkey_92_ pkey_180_ \ + pkey_193_ pkey_80_ pkey_93_ pkey_107_ pkey_194_ pkey_206_ pkey_50_ \ + pkey_61_ pkey_94_ pkey_182_ pkey_195_ pkey_209_ pstart_0_ pkey_51_ \ + pkey_60_ pkey_109_ pkey_181_ pkey_196_ pkey_208_ pkey_52_ pkey_74_ \ + pkey_85_ pkey_104_ pkey_171_ pkey_197_ pkey_203_ pencrypt_0_ pkey_53_ \ + pkey_62_ pkey_75_ pkey_84_ pkey_172_ pkey_198_ pkey_202_ pkey_54_ pkey_65_ \ + pkey_72_ pkey_83_ pkey_90_ pkey_106_ pkey_205_ pkey_64_ pkey_73_ pkey_82_ \ + pkey_91_ pkey_105_ pkey_170_ pkey_204_ pkey_12_ pkey_34_ pkey_45_ \ + pkey_100_ pkey_188_ pkey_13_ pkey_22_ pkey_35_ pkey_44_ pkey_176_ \ + pkey_187_ pkey_14_ pkey_25_ pkey_32_ pkey_43_ pkey_102_ pkey_173_ \ + pkey_201_ pkey_24_ pkey_33_ pkey_42_ pkey_101_ pkey_174_ pkey_189_ \ + pkey_200_ pkey_30_ pkey_41_ pkey_179_ pkey_184_ pkey_40_ pkey_190_ \ + pkey_10_ pkey_21_ pkey_177_ pkey_186_ pkey_11_ pkey_20_ pkey_178_ \ + pkey_185_ pkey_192_ +.outputs pksi_50_ pksi_61_ pksi_72_ pksi_83_ pksi_94_ pksi_102_ pksi_115_ \ + pksi_128_ pdata_ready_0_ pksi_51_ pksi_60_ pksi_73_ pksi_82_ pksi_95_ \ + pksi_101_ pksi_116_ pksi_127_ pksi_52_ pksi_63_ pksi_70_ pksi_81_ pksi_96_ \ + pksi_100_ pksi_113_ pksi_53_ pksi_62_ pksi_71_ pksi_80_ pksi_97_ pksi_114_ \ + pksi_129_ pksi_54_ pksi_65_ pksi_76_ pksi_87_ pksi_90_ pksi_119_ pksi_124_ \ + pksi_191_ pksi_55_ pksi_64_ pksi_77_ pksi_86_ pksi_91_ pksi_123_ pksi_56_ \ + pksi_67_ pksi_74_ pksi_85_ pksi_92_ pksi_117_ pksi_126_ pksi_57_ pksi_66_ \ + pksi_75_ pksi_84_ pksi_93_ pksi_118_ pksi_125_ pksi_190_ pksi_14_ pksi_25_ \ + pksi_36_ pksi_47_ pksi_120_ pksi_15_ pksi_24_ pksi_37_ pksi_46_ pksi_109_ \ + pnew_count_3_ pksi_16_ pksi_27_ pksi_34_ pksi_45_ pksi_108_ pksi_122_ \ + pksi_17_ pksi_26_ pksi_35_ pksi_44_ pksi_107_ pksi_121_ pksi_10_ pksi_21_ \ + pksi_32_ pksi_43_ pksi_106_ pksi_111_ pnew_count_0_ pksi_11_ pksi_20_ \ + pksi_33_ pksi_42_ pksi_105_ pksi_112_ pksi_12_ pksi_23_ pksi_30_ pksi_41_ \ + pksi_104_ pnew_count_2_ pksi_13_ pksi_22_ pksi_31_ pksi_40_ pksi_103_ \ + pksi_110_ pnew_count_1_ pksi_3_ pksi_151_ pksi_164_ pksi_177_ pksi_2_ \ + pksi_152_ pksi_163_ pksi_178_ pksi_189_ pksi_1_ pksi_166_ pksi_179_ \ + pksi_188_ pksi_0_ pksi_150_ pksi_165_ pksi_187_ pksi_18_ pksi_29_ \ + pksi_142_ pksi_168_ pksi_173_ pksi_186_ pksi_19_ pksi_28_ pksi_130_ \ + pksi_141_ pksi_167_ pksi_174_ pksi_185_ pksi_38_ pksi_49_ pksi_131_ \ + pksi_140_ pksi_175_ pksi_184_ pksi_39_ pksi_48_ pksi_132_ pksi_169_ \ + pksi_176_ pksi_183_ pksi_58_ pksi_69_ pksi_133_ pksi_146_ pksi_159_ \ + pksi_182_ pksi_59_ pksi_68_ pksi_134_ pksi_145_ pksi_170_ pksi_181_ \ + pksi_9_ pksi_78_ pksi_89_ pksi_135_ pksi_144_ pksi_157_ pksi_171_ \ + pksi_180_ pksi_8_ pksi_79_ pksi_88_ pksi_136_ pksi_143_ pksi_158_ \ + pksi_172_ pksi_7_ pksi_98_ pksi_137_ pksi_155_ pksi_160_ pksi_6_ pksi_99_ \ + pksi_138_ pksi_149_ pksi_156_ pksi_5_ pksi_139_ pksi_148_ pksi_153_ \ + pksi_162_ pksi_4_ pksi_147_ pksi_154_ pksi_161_ + +.latch n853_1 pksi_50_ re clock 0 +.latch n857_1 pksi_61_ re clock 0 +.latch n861_1 pksi_72_ re clock 0 +.latch n865 pksi_83_ re clock 0 +.latch n869 pksi_94_ re clock 0 +.latch n873 pksi_102_ re clock 0 +.latch n877 pksi_115_ re clock 0 +.latch n881 pksi_128_ re clock 0 +.latch n885 pksi_51_ re clock 0 +.latch n889 pksi_60_ re clock 0 +.latch n893 pksi_73_ re clock 0 +.latch n897 pksi_82_ re clock 0 +.latch n901_1 pksi_95_ re clock 0 +.latch n905 pksi_101_ re clock 0 +.latch n909 pksi_116_ re clock 0 +.latch n913 pksi_127_ re clock 0 +.latch n917 pksi_52_ re clock 0 +.latch n921 pksi_63_ re clock 0 +.latch n925 pksi_70_ re clock 0 +.latch n929 pksi_81_ re clock 0 +.latch n933 pksi_96_ re clock 0 +.latch n937 pksi_100_ re clock 0 +.latch n941 pksi_113_ re clock 0 +.latch n945 pksi_53_ re clock 0 +.latch n949 pksi_62_ re clock 0 +.latch n953 pksi_71_ re clock 0 +.latch n957 pksi_80_ re clock 0 +.latch n961 pksi_97_ re clock 0 +.latch n965 pksi_114_ re clock 0 +.latch n969 pksi_129_ re clock 0 +.latch n973 pksi_54_ re clock 0 +.latch n977 pksi_65_ re clock 0 +.latch n981 pksi_76_ re clock 0 +.latch n985 pksi_87_ re clock 0 +.latch n989 pksi_119_ re clock 0 +.latch n993 pksi_124_ re clock 0 +.latch n997 pksi_55_ re clock 0 +.latch n1001 pksi_64_ re clock 0 +.latch n1005 pksi_77_ re clock 0 +.latch n1009 pksi_86_ re clock 0 +.latch n1013_1 pksi_91_ re clock 0 +.latch n1017_1 pksi_123_ re clock 0 +.latch n1021_1 pksi_56_ re clock 0 +.latch n1025_1 pksi_67_ re clock 0 +.latch n1029_1 pksi_74_ re clock 0 +.latch n1033_1 pksi_85_ re clock 0 +.latch n1037_1 pksi_92_ re clock 0 +.latch n1041_1 pksi_117_ re clock 0 +.latch n1045_1 pksi_126_ re clock 0 +.latch n1049 pksi_57_ re clock 0 +.latch n1053 pksi_66_ re clock 0 +.latch n1057 pksi_75_ re clock 0 +.latch n1061 pksi_84_ re clock 0 +.latch n1065 pksi_93_ re clock 0 +.latch n1069 pksi_118_ re clock 0 +.latch n1073 pksi_125_ re clock 0 +.latch n1077 pksi_190_ re clock 0 +.latch n1081 pksi_14_ re clock 0 +.latch n1085 pksi_25_ re clock 0 +.latch n1089 pksi_36_ re clock 0 +.latch n1093 pksi_47_ re clock 0 +.latch n1097 pksi_120_ re clock 0 +.latch n1101 pksi_15_ re clock 0 +.latch n1105_1 pksi_24_ re clock 0 +.latch n1109_1 pksi_37_ re clock 0 +.latch n1113_1 pksi_46_ re clock 0 +.latch n1117_1 pksi_109_ re clock 0 +.latch n1121_1 pksi_16_ re clock 0 +.latch n1125_1 pksi_27_ re clock 0 +.latch n1129 pksi_34_ re clock 0 +.latch n1133 pksi_45_ re clock 0 +.latch n1137 pksi_108_ re clock 0 +.latch n1141 pksi_122_ re clock 0 +.latch n1145 pksi_17_ re clock 0 +.latch n1149 pksi_26_ re clock 0 +.latch n1153 pksi_35_ re clock 0 +.latch n1157 pksi_44_ re clock 0 +.latch n1161 pksi_107_ re clock 0 +.latch n1165 pksi_121_ re clock 0 +.latch n1169 pksi_10_ re clock 0 +.latch n1173 pksi_21_ re clock 0 +.latch n1177 pksi_32_ re clock 0 +.latch n1181 pksi_43_ re clock 0 +.latch n1185 pksi_106_ re clock 0 +.latch n1189 pksi_111_ re clock 0 +.latch n1193 pksi_11_ re clock 0 +.latch n1197 pksi_20_ re clock 0 +.latch n1201_1 pksi_33_ re clock 0 +.latch n1205_1 pksi_42_ re clock 0 +.latch n1209_1 pksi_105_ re clock 0 +.latch n1213_1 pksi_112_ re clock 0 +.latch n1217_1 pksi_12_ re clock 0 +.latch n1221 pksi_23_ re clock 0 +.latch n1225 pksi_30_ re clock 0 +.latch n1229 pksi_41_ re clock 0 +.latch n1233 pksi_104_ re clock 0 +.latch n1237 pksi_13_ re clock 0 +.latch n1241 pksi_22_ re clock 0 +.latch n1245 pksi_31_ re clock 0 +.latch n1249 pksi_40_ re clock 0 +.latch n1253 pksi_103_ re clock 0 +.latch n1257 pksi_110_ re clock 0 +.latch n1261 pksi_3_ re clock 0 +.latch n1265 pksi_151_ re clock 0 +.latch n1269 pksi_164_ re clock 0 +.latch n1273 pksi_177_ re clock 0 +.latch n1277 pksi_2_ re clock 0 +.latch n1281 pksi_152_ re clock 0 +.latch n1285_1 pksi_163_ re clock 0 +.latch n1289_1 pksi_178_ re clock 0 +.latch n1293_1 pksi_189_ re clock 0 +.latch n1297_1 pksi_1_ re clock 0 +.latch n1301_1 pksi_166_ re clock 0 +.latch n1305_1 pksi_179_ re clock 0 +.latch n1309_1 pksi_188_ re clock 0 +.latch n1313 pksi_0_ re clock 0 +.latch n1317 pksi_150_ re clock 0 +.latch n1321 pksi_165_ re clock 0 +.latch n1325 pksi_18_ re clock 0 +.latch n1329 pksi_29_ re clock 0 +.latch n1333 pksi_142_ re clock 0 +.latch n1337 pksi_173_ re clock 0 +.latch n1341 pksi_186_ re clock 0 +.latch n1345 pksi_19_ re clock 0 +.latch n1349 pksi_28_ re clock 0 +.latch n1353 pksi_130_ re clock 0 +.latch n1357 pksi_141_ re clock 0 +.latch n1361_1 pksi_167_ re clock 0 +.latch n1365_1 pksi_174_ re clock 0 +.latch n1369 pksi_185_ re clock 0 +.latch n1373 pksi_38_ re clock 0 +.latch n1377 pksi_49_ re clock 0 +.latch n1381 pksi_131_ re clock 0 +.latch n1385 pksi_140_ re clock 0 +.latch n1389 pksi_175_ re clock 0 +.latch n1393 pksi_184_ re clock 0 +.latch n1397 pksi_39_ re clock 0 +.latch n1401 pksi_48_ re clock 0 +.latch n1405 pksi_132_ re clock 0 +.latch n1409 pksi_169_ re clock 0 +.latch n1413 pksi_176_ re clock 0 +.latch n1417 pksi_183_ re clock 0 +.latch n1421 pksi_58_ re clock 0 +.latch n1425 pksi_69_ re clock 0 +.latch n1429 pksi_133_ re clock 0 +.latch n1433 pksi_146_ re clock 0 +.latch n1437 pksi_159_ re clock 0 +.latch n1441 pksi_182_ re clock 0 +.latch n1445 pksi_59_ re clock 0 +.latch n1449 pksi_68_ re clock 0 +.latch n1453 pksi_134_ re clock 0 +.latch n1457 pksi_145_ re clock 0 +.latch n1461 pksi_170_ re clock 0 +.latch n1465 pksi_9_ re clock 0 +.latch n1469 pksi_78_ re clock 0 +.latch n1473 pksi_89_ re clock 0 +.latch n1477 pksi_135_ re clock 0 +.latch n1481 pksi_144_ re clock 0 +.latch n1485_1 pksi_157_ re clock 0 +.latch n1489_1 pksi_171_ re clock 0 +.latch n1493_1 pksi_180_ re clock 0 +.latch n1497_1 pksi_8_ re clock 0 +.latch n1501 pksi_79_ re clock 0 +.latch n1505 pksi_136_ re clock 0 +.latch n1509 pksi_158_ re clock 0 +.latch n1513 pksi_172_ re clock 0 +.latch n1517 pksi_7_ re clock 0 +.latch n1521 pksi_98_ re clock 0 +.latch n1525 pksi_137_ re clock 0 +.latch n1529 pksi_155_ re clock 0 +.latch n1533 pksi_160_ re clock 0 +.latch n1537 pksi_6_ re clock 0 +.latch n1541 pksi_99_ re clock 0 +.latch n1545 pksi_138_ re clock 0 +.latch n1549 pksi_149_ re clock 0 +.latch n1553 pksi_156_ re clock 0 +.latch n1557 pksi_5_ re clock 0 +.latch n1561 pksi_148_ re clock 0 +.latch n1565 pksi_153_ re clock 0 +.latch n1569 pksi_162_ re clock 0 +.latch n1573 pksi_4_ re clock 0 +.latch n1577 pksi_147_ re clock 0 +.latch n1581 pksi_154_ re clock 0 +.latch n1585 pksi_161_ re clock 0 +.latch n1589_1 n_n2410 re clock 0 +.latch n1594 n_n2513 re clock 0 +.latch n1599 n_n2396 re clock 0 +.latch n1604 n_n2412 re clock 0 +.latch n1609_1 pksi_187_ re clock 0 +.latch n1613_1 n_n2448 re clock 0 +.latch n1618_1 n_n2408 re clock 0 +.latch n1623 n_n2420 re clock 0 +.latch n1628 n_n2485 re clock 0 +.latch n1633 n_n2495 re clock 0 +.latch n1638 n_n2384 re clock 0 +.latch n1643_1 n_n2416 re clock 0 +.latch n1648 n_n2440 re clock 0 +.latch n1653 n_n2272 re clock 0 +.latch n1658 n_n2430 re clock 0 +.latch n1663_1 n_n2481 re clock 0 +.latch n1668 n_n2452 re clock 0 +.latch n1673 n_n2462 re clock 0 +.latch n1678 pksi_168_ re clock 0 +.latch n1682 pksi_88_ re clock 0 +.latch n1686 n_n2474 re clock 0 +.latch n1691_1 n_n2517 re clock 0 +.latch n1696_1 n_n2268 re clock 0 +.latch n1701_1 n_n2476 re clock 0 +.latch n1706_1 n_n2507 re clock 0 +.latch n1711 pksi_139_ re clock 0 +.latch n1715 n_n2374 re clock 0 +.latch n1720 n_n2337 re clock 0 +.latch n1725 n_n2277 re clock 0 +.latch n1730_1 n_n2280 re clock 0 +.latch n1735_1 n_n2301 re clock 0 +.latch n1740 n_n2320 re clock 0 +.latch n1745 n_n2333 re clock 0 +.latch n1750 n_n2305 re clock 0 +.latch n1755_1 n_n2365 re clock 0 +.latch n1760 n_n2369 re clock 0 +.latch n1765 n_n2288 re clock 0 +.latch n1770 n_n2310 re clock 0 +.latch n1775 n_n2342 re clock 0 +.latch n1780 n_n2352 re clock 0 + +.names pcount_1_ pcount_2_ pcount_3_ pcount_0_ n1101_1 +0000 1 +1101 1 +1110 1 +.names pencrypt_0_ pstart_0_ n1102 +10 1 +.names pcount_1_ pcount_2_ pcount_3_ pcount_0_ n1103 +000- 1 +00-0 1 +1111 1 +.names pstart_0_ pencrypt_0_ n1106 n1105 pkey_181_ pkey_173_ n1613_1 +00-0-- 1 +10--1- 1 +11---1 1 +--1--- 1 +.names n1103 pksi_147_ pksi_165_ n1105 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_158_ pksi_151_ n1106 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1109 n1108 pkey_28_ pkey_36_ n1161 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_100_ pksi_114_ n1108 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_109_ pksi_116_ n1109 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1112 n1111 pkey_37_ pkey_45_ n1257 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2513 pksi_99_ n1111 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_103_ pksi_96_ n1112 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1115 n1114 pkey_8_ pkey_16_ n1465 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_5_ pksi_15_ n1114 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_19_ pksi_17_ n1115 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1118 n1117 pkey_196_ pkey_204_ n1413 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_188_ pksi_168_ n1117 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_169_ pksi_185_ n1118 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1121 n1120 pkey_252_ pkey_197_ n1493_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2408 n_n2410 n1120 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_177_ pksi_186_ n1121 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1124 n1123 pkey_214_ pkey_222_ n1289_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_187_ pksi_170_ n1123 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_184_ n_n2420 n1124 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1127 n1126 pkey_190_ pkey_67_ n1477 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_125_ n_n2462 n1126 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_166_ pksi_150_ n1127 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1130 n1129_1 pkey_116_ pkey_124_ n969 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_132_ n_n2474 n1129_1 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_138_ pksi_124_ n1130 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1133_1 n1132 pkey_61_ pkey_6_ n1041_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2517 pksi_112_ n1132 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_99_ n_n2513 n1133_1 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1136 n1135 pkey_54_ pkey_62_ n1069 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_183_ pksi_173_ n1135 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_102_ pksi_98_ n1136 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1139 n1138 pkey_16_ pkey_24_ n1557 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_15_ pksi_6_ n1138 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_9_ pksi_19_ n1139 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1142 n1141_1 pkey_219_ pkey_196_ n1409 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_176_ pksi_188_ n1141_1 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_185_ n_n2396 n1142 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1145_1 n1144 pkey_197_ pkey_205_ n1618_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2410 n_n2412 n1144 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_180_ pksi_177_ n1145_1 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1148 n1147 pkey_206_ pkey_214_ n1393 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_178_ pksi_187_ n1147 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2420 pksi_189_ n1148 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1151 n1150 pkey_67_ pkey_75_ n1073 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2462 pksi_137_ n1150 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_135_ pksi_166_ n1151 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1154 n1153_1 pkey_53_ pkey_61_ n1541 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_117_ n_n2517 n1153_1 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2513 pksi_110_ n1154 +10-1 1 +111- 1 +.names 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pstart_0_ pencrypt_0_ n1652 n1651 pkey_64_ pkey_72_ n1181 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_33_ pksi_29_ n1651 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_41_ n_n2352 n1652 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1655 n1654 pkey_43_ pkey_51_ n1121_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2365 pksi_3_ n1654 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_20_ pksi_7_ n1655 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1658_1 n1657 pkey_18_ pkey_26_ n1169 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_21_ pksi_13_ n1657 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2369 pksi_12_ n1658_1 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1661 n1660 pkey_170_ pkey_178_ n1770 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_49_ pksi_66_ n1660 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_61_ pksi_69_ n1661 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1664 n1663 pkey_128_ pkey_136_ n1025_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_57_ pksi_53_ n1663 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_65_ n_n2320 n1664 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1667 n1666 pkey_114_ pkey_122_ n1085 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_42_ pksi_32_ n1666 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2342 pksi_37_ n1667 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1670 n1669 pkey_35_ pkey_43_ n1197 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_16_ n_n2365 n1669 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_7_ pksi_28_ n1670 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1673_1 n1672 pkey_26_ pkey_34_ n1173 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_13_ n_n2374 n1672 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_10_ n_n2369 n1673_1 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1676 n1675 pkey_178_ pkey_186_ n1377 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_66_ pksi_56_ n1675 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2310 pksi_61_ n1676 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1679 n1678_1 pkey_185_ pkey_128_ n977 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_67_ pksi_57_ n1678_1 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2320 pksi_59_ n1679 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1682_1 n1681 pkey_99_ pkey_107_ n1157 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_40_ n_n2333 n1681 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_31_ pksi_52_ n1682_1 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1685 n1684 pkey_106_ pkey_114_ n1775 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_25_ pksi_42_ n1684 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_37_ pksi_45_ n1685 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1688 n1687 pkey_113_ pkey_121_ n1780 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_41_ pksi_43_ n1687 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_35_ pksi_26_ n1688 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1691 n1690 pkey_120_ pkey_35_ n1517 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_20_ pksi_16_ n1690 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_28_ pksi_47_ n1691 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1694 n1693 pkey_34_ pkey_42_ n1237 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2374 pksi_1_ n1693 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_21_ pksi_10_ n1694 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ pcount_0_ pnew_count_0_ +0-0 1 +10- 1 +.names pcount_1_ pcount_2_ pcount_3_ pcount_0_ pencrypt_0_ pstart_0_ \ + pdata_ready_0_ +000000 1 +111110 1 +.names pcount_1_ pcount_3_ pstart_0_ pencrypt_0_ pcount_2_ pcount_0_ \ + pnew_count_3_ +00-000 1 +010--1 1 +100111 1 +11-0-- 1 +-101-0 1 +-10-01 1 +-1-01- 1 +--10-- 1 +.names pencrypt_0_ pcount_2_ pcount_1_ pcount_0_ pstart_0_ pnew_count_2_ +0000- 1 +01-1- 1 +0---1 1 +10110 1 +11-00 1 +-1010 1 +-1100 1 +.names pencrypt_0_ pcount_1_ pcount_0_ pstart_0_ pnew_count_1_ +000- 1 +011- 1 +0--1 1 +1010 1 +1100 1 +.names pstart_0_ pencrypt_0_ n1702 n1701 pkey_57_ pkey_0_ n1145 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_19_ pksi_9_ n1701 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2384 pksi_11_ n1702 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1705 n1704 pkey_211_ pkey_219_ n1369 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_169_ pksi_176_ n1704 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2396 pksi_173_ n1705 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1708 n1707 pkey_205_ pkey_213_ n1589_1 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 n_n2412 pksi_175_ n1707 +0-0 1 +10- 1 +.names n1102 n1101_1 n_n2408 pksi_180_ n1708 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1711_1 n1710 pkey_230_ pkey_238_ n1461 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_174_ pksi_190_ n1710 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_187_ pksi_178_ n1711_1 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1714 n1713 pkey_156_ pkey_164_ n1529 +00-0-- 1 +10---1 1 +11--1- 1 +--1--- 1 +.names n1103 pksi_148_ pksi_162_ n1713 +0-0 1 +10- 1 +.names n1102 n1101_1 pksi_157_ pksi_164_ n1714 +10-1 1 +111- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_181_ n_n2448 pksi_158_ n1715_1 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1715_1 pencrypt_0_ n1103 pkey_189_ n_n2452 pksi_165_ n1577 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_20_ pksi_104_ pksi_116_ n1717 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1717 pencrypt_0_ n1103 pkey_28_ pksi_100_ pksi_107_ n1117_1 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_45_ pksi_103_ pksi_110_ n1719 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1719 pencrypt_0_ n1103 pkey_53_ pksi_117_ pksi_99_ n1594 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_0_ pksi_17_ n_n2384 n1721 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1721 pencrypt_0_ n1103 pkey_8_ pksi_5_ pksi_9_ n1345 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_203_ pksi_183_ pksi_173_ n1723 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1723 pencrypt_0_ n1103 pkey_211_ pksi_185_ pksi_169_ n1599 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_213_ n_n2410 n_n2408 n1725_1 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1725_1 pencrypt_0_ n1103 pkey_221_ pksi_182_ pksi_175_ n1604 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_222_ pksi_184_ pksi_178_ n1727 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1727 pencrypt_0_ n1103 pkey_230_ pksi_170_ pksi_174_ n1609_1 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_164_ pksi_155_ pksi_157_ n1729 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1729 pencrypt_0_ n1103 pkey_172_ n_n2440 pksi_162_ n1561 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_36_ pksi_107_ pksi_109_ n1731 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1731 pencrypt_0_ n1103 pkey_44_ pksi_114_ pksi_105_ n937 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_44_ pksi_124_ pksi_131_ n1733 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1733 pencrypt_0_ n1103 pkey_116_ pksi_132_ pksi_129_ n1545 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_44_ pksi_100_ pksi_107_ n1735 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1735 pencrypt_0_ n1103 pkey_52_ pksi_105_ pksi_108_ n965 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_172_ pksi_179_ pksi_172_ n1737 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1737 pencrypt_0_ n1103 pkey_244_ pksi_177_ pksi_180_ n1341 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_228_ pksi_168_ pksi_179_ n1739 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1739 pencrypt_0_ n1103 pkey_172_ pksi_186_ pksi_177_ n1513 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_93_ pksi_120_ n_n2476 n1741 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1741 pencrypt_0_ n1103 pkey_101_ n_n2481 pksi_134_ n913 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_118_ pksi_122_ pksi_126_ n1743 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1743 pencrypt_0_ n1103 pkey_126_ pksi_101_ pksi_111_ n1333 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_172_ pksi_155_ pksi_148_ n1745_1 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1745_1 pencrypt_0_ n1103 pkey_180_ n_n2440 pksi_156_ n1569 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_133_ n_n2440 pksi_156_ n1747 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1747 pencrypt_0_ n1103 pkey_141_ pksi_144_ pksi_163_ n1565 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_100_ pksi_131_ pksi_133_ n1749 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1749 pencrypt_0_ n1103 pkey_44_ pksi_138_ pksi_129_ n993 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_77_ n_n2474 pksi_132_ n1751 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1751 pencrypt_0_ n1103 pkey_85_ pksi_120_ pksi_127_ n1701_1 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_85_ n_n2474 n_n2476 n1753 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1753 pencrypt_0_ n1103 pkey_93_ pksi_134_ pksi_127_ n1097 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_184_ pksi_71_ pksi_52_ n1755 +010-1- 1 +011--1 1 +10---- 1 +1--1-- 1 +.names n1755 pencrypt_0_ n1103 pkey_99_ pksi_40_ pksi_44_ n1245 +000-1- 1 +001--1 1 +11---- 1 +1--1-- 1 +.names pstart_0_ pencrypt_0_ n1101_1 pkey_105_ pksi_26_ pksi_38_ n1757 +010--1 1 +011-1- 1 +10---- 1 +1--1-- 1 +.names n1757 pencrypt_0_ n1103 pkey_113_ n_n2352 pksi_41_ n1153 +000--1 1 +001-1- 1 +11---- 1 +1--1-- 1 +.names pksi_139_ pksi_143_ +1 1 +.names pksi_168_ pksi_181_ +1 1 +.names pksi_187_ pksi_191_ +1 1 +.names pksi_88_ pksi_90_ +1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v b/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v new file mode 100644 index 000000000..311110cd8 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v @@ -0,0 +1,2641 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module dsip(clock, pcount_3_, pkey_5_, pkey_131_, pkey_144_, pkey_157_, pkey_230_, pkey_243_, pcount_2_, pkey_4_, pkey_132_, pkey_158_, pkey_169_, pkey_242_, pcount_1_, pkey_146_, pkey_168_, pkey_245_, pcount_0_, pkey_6_, pkey_130_, pkey_145_, pkey_244_, pkey_9_, pkey_16_, pkey_27_, pkey_38_, pkey_49_, pkey_122_, pkey_148_, pkey_153_, pkey_166_, pkey_221_, pkey_252_, pkey_8_, pkey_17_, pkey_26_, pkey_48_, pkey_110_, pkey_121_, pkey_147_, pkey_154_, pkey_165_, pkey_220_, pkey_246_, pkey_253_, pkey_18_, pkey_29_, pkey_36_, pkey_120_, pkey_155_, pkey_164_, pkey_210_, pkey_249_, pkey_254_, pkey_19_, pkey_28_, pkey_37_, pkey_46_, pkey_112_, pkey_149_, pkey_156_, pkey_163_, pkey_211_, pkey_248_, pkey_56_, pkey_67_, pkey_78_, pkey_89_, pkey_113_, pkey_126_, pkey_139_, pkey_162_, pkey_212_, pkey_225_, pkey_238_, pkey_57_, pkey_66_, pkey_88_, pkey_114_, pkey_125_, pkey_150_, pkey_161_, pkey_213_, pkey_224_, pkey_58_, pkey_69_, pkey_76_, pkey_115_, pkey_124_, pkey_137_, pkey_160_, pkey_214_, pkey_250_, pkey_59_, pkey_68_, pkey_77_, pkey_86_, pkey_116_, pkey_123_, pkey_138_, pkey_152_, pkey_222_, pkey_237_, pkey_251_, pkey_1_, pkey_96_, pkey_117_, pkey_140_, pkey_216_, pkey_229_, pkey_234_, pkey_0_, pkey_97_, pkey_118_, pkey_129_, pkey_136_, pkey_217_, pkey_228_, pkey_235_, pkey_3_, pkey_98_, pkey_128_, pkey_133_, pkey_142_, pkey_218_, pkey_227_, pkey_232_, pkey_241_, pkey_2_, pkey_99_, pkey_134_, pkey_141_, pkey_219_, pkey_226_, pkey_233_, pkey_240_, pkey_70_, pkey_81_, pkey_92_, pkey_180_, pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, pkey_50_, pkey_61_, pkey_94_, pkey_182_, pkey_195_, pkey_209_, pstart_0_, pkey_51_, pkey_60_, pkey_109_, pkey_181_, pkey_196_, pkey_208_, pkey_52_, pkey_74_, pkey_85_, pkey_104_, pkey_171_, pkey_197_, pkey_203_, pencrypt_0_, pkey_53_, pkey_62_, pkey_75_, pkey_84_, pkey_172_, pkey_198_, pkey_202_, pkey_54_, pkey_65_, pkey_72_, pkey_83_, pkey_90_, pkey_106_, pkey_205_, pkey_64_, pkey_73_, pkey_82_, pkey_91_, pkey_105_, pkey_170_, pkey_204_, pkey_12_, pkey_34_, pkey_45_, pkey_100_, pkey_188_, pkey_13_, pkey_22_, pkey_35_, pkey_44_, pkey_176_, pkey_187_, pkey_14_, pkey_25_, pkey_32_, pkey_43_, pkey_102_, pkey_173_, pkey_201_, pkey_24_, pkey_33_, pkey_42_, pkey_101_, pkey_174_, pkey_189_, pkey_200_, pkey_30_, pkey_41_, pkey_179_, pkey_184_, pkey_40_, pkey_190_, pkey_10_, pkey_21_, pkey_177_, pkey_186_, pkey_11_, pkey_20_, pkey_178_, pkey_185_, pkey_192_, pksi_50_, pksi_61_, pksi_72_, pksi_83_, pksi_94_, pksi_102_, pksi_115_, pksi_128_, pdata_ready_0_, pksi_51_, pksi_60_, pksi_73_, pksi_82_, pksi_95_, pksi_101_, pksi_116_, pksi_127_, pksi_52_, pksi_63_, pksi_70_, pksi_81_, pksi_96_, pksi_100_, pksi_113_, pksi_53_, pksi_62_, pksi_71_, pksi_80_, pksi_97_, pksi_114_, pksi_129_, pksi_54_, pksi_65_, pksi_76_, pksi_87_, pksi_90_, pksi_119_, pksi_124_, pksi_191_, pksi_55_, pksi_64_, pksi_77_, pksi_86_, pksi_91_, pksi_123_, pksi_56_, pksi_67_, pksi_74_, pksi_85_, pksi_92_, pksi_117_, pksi_126_, pksi_57_, pksi_66_, pksi_75_, pksi_84_, pksi_93_, pksi_118_, pksi_125_, pksi_190_, pksi_14_, pksi_25_, pksi_36_, pksi_47_, pksi_120_, pksi_15_, pksi_24_, pksi_37_, pksi_46_, pksi_109_, pnew_count_3_, pksi_16_, pksi_27_, pksi_34_, pksi_45_, pksi_108_, pksi_122_, pksi_17_, pksi_26_, pksi_35_, pksi_44_, pksi_107_, pksi_121_, pksi_10_, pksi_21_, pksi_32_, pksi_43_, pksi_106_, pksi_111_, pnew_count_0_, pksi_11_, pksi_20_, pksi_33_, pksi_42_, pksi_105_, pksi_112_, pksi_12_, pksi_23_, pksi_30_, pksi_41_, pksi_104_, pnew_count_2_, pksi_13_, pksi_22_, pksi_31_, pksi_40_, pksi_103_, pksi_110_, pnew_count_1_, pksi_3_, pksi_151_, pksi_164_, pksi_177_, pksi_2_, pksi_152_, pksi_163_, pksi_178_, pksi_189_, pksi_1_, pksi_166_, pksi_179_, pksi_188_, pksi_0_, pksi_150_, pksi_165_, pksi_187_, pksi_18_, pksi_29_, pksi_142_, pksi_168_, pksi_173_, pksi_186_, pksi_19_, pksi_28_, pksi_130_, pksi_141_, pksi_167_, pksi_174_, pksi_185_, pksi_38_, pksi_49_, pksi_131_, pksi_140_, pksi_175_, pksi_184_, pksi_39_, pksi_48_, pksi_132_, pksi_169_, pksi_176_, pksi_183_, pksi_58_, pksi_69_, pksi_133_, pksi_146_, pksi_159_, pksi_182_, pksi_59_, pksi_68_, pksi_134_, pksi_145_, pksi_170_, pksi_181_, pksi_9_, pksi_78_, pksi_89_, pksi_135_, pksi_144_, pksi_157_, pksi_171_, pksi_180_, pksi_8_, pksi_79_, pksi_88_, pksi_136_, pksi_143_, pksi_158_, pksi_172_, pksi_7_, pksi_98_, pksi_137_, pksi_155_, pksi_160_, pksi_6_, pksi_99_, pksi_138_, pksi_149_, pksi_156_, pksi_5_, pksi_139_, pksi_148_, pksi_153_, pksi_162_, pksi_4_, pksi_147_, pksi_154_, pksi_161_); + input clock; + wire n1001; + wire n1005; + wire n1009; + wire n1013_1; + wire n1017_1; + wire n1021_1; + wire n1025_1; + wire n1029_1; + wire n1033_1; + wire n1037_1; + wire n1041_1; + wire n1045_1; + wire n1049; + wire n1053; + wire n1057; + wire n1061; + wire n1065; + wire n1069; + wire n1073; + wire n1077; + wire n1081; + wire n1085; + wire n1089; + wire n1093; + wire n1097; + wire n1101; + wire n1101_1; + wire n1102; + wire n1103; + wire n1105; + wire n1105_1; + wire n1106; + wire n1108; + wire n1109; + wire n1109_1; + wire n1111; + wire n1112; + wire n1113_1; + wire n1114; + wire n1115; + wire n1117; + wire n1117_1; + wire n1118; + wire n1120; + wire n1121; + wire n1121_1; + wire n1123; + wire n1124; + wire n1125_1; + wire n1126; + wire n1127; + wire n1129; + wire n1129_1; + wire n1130; + wire n1132; + wire n1133; + wire n1133_1; + wire n1135; + wire n1136; + wire n1137; + wire n1138; + wire n1139; + wire n1141; + wire n1141_1; + wire n1142; + wire n1144; + wire n1145; + wire n1145_1; + wire n1147; + wire n1148; + wire n1149; + wire n1150; + wire n1151; + wire n1153; + wire n1153_1; + wire n1154; + wire n1156; + wire n1157; + wire n1157_1; + wire n1159; + wire n1160; + wire n1161; + wire n1162; + wire n1163; + wire n1165; + wire n1165_1; + wire n1166; + wire n1168; + wire n1169; + wire n1169_1; + wire n1171; + wire n1172; + wire n1173; + wire n1174; + wire n1175; + wire n1177; + wire n1177_1; + wire n1178; + wire n1180; + wire n1181; + wire n1181_1; + wire n1183; + wire n1184; + wire n1185; + wire n1186; + wire n1187; + wire n1189; + wire n1189_1; + wire n1190; + wire n1192; + wire n1193; + wire n1193_1; + wire n1195; + wire n1196; + wire n1197; + wire n1198; + wire n1199; + wire n1201; + wire n1201_1; + wire n1202; + wire n1204; + wire n1205; + wire n1205_1; + wire n1207; + wire n1208; + wire n1209_1; + wire n1210; + wire n1211; + wire n1213; + wire n1213_1; + wire n1214; + wire n1216; + wire n1217; + wire n1217_1; + wire n1219; + wire n1220; + wire n1221; + wire n1222; + wire n1223; + wire n1225; + wire n1225_1; + wire n1226; + wire n1228; + wire n1229; + wire n1229_1; + wire n1231; + wire n1232; + wire n1233; + wire n1234; + wire n1235; + wire n1237; + wire n1237_1; + wire n1238; + wire n1240; + wire n1241; + wire n1241_1; + wire n1243; + wire n1244; + wire n1245; + wire n1246; + wire n1247; + wire n1249; + wire n1249_1; + wire n1250; + wire n1252; + wire n1253; + wire n1253_1; + wire n1255; + wire n1256; + wire n1257; + wire n1258; + wire n1259; + wire n1261; + wire n1261_1; + wire n1262; + wire n1264; + wire n1265; + wire n1265_1; + wire n1267; + wire n1268; + wire n1269; + wire n1270; + wire n1271; + wire n1273; + wire n1273_1; + wire n1274; + wire n1276; + wire n1277; + wire n1277_1; + wire n1279; + wire n1280; + wire n1281; + wire n1282; + wire n1283; + wire n1285; + wire n1285_1; + wire n1286; + wire n1288; + wire n1289; + wire n1289_1; + wire n1291; + wire n1292; + wire n1293_1; + wire n1294; + wire n1295; + wire n1297; + wire n1297_1; + wire n1298; + wire n1300; + wire n1301; + wire n1301_1; + wire n1303; + wire n1304; + wire n1305_1; + wire n1306; + wire n1307; + wire n1309; + wire n1309_1; + wire n1310; + wire n1312; + wire n1313; + wire n1313_1; + wire n1315; + wire n1316; + wire n1317; + wire n1318; + wire n1319; + wire n1321; + wire n1321_1; + wire n1322; + wire n1324; + wire n1325; + wire n1325_1; + wire n1327; + wire n1328; + wire n1329; + wire n1330; + wire n1331; + wire n1333; + wire n1333_1; + wire n1334; + wire n1336; + wire n1337; + wire n1337_1; + wire n1339; + wire n1340; + wire n1341; + wire n1342; + wire n1343; + wire n1345; + wire n1345_1; + wire n1346; + wire n1348; + wire n1349; + wire n1349_1; + wire n1351; + wire n1352; + wire n1353; + wire n1354; + wire n1355; + wire n1357; + wire n1357_1; + wire n1358; + wire n1360; + wire n1361; + wire n1361_1; + wire n1363; + wire n1364; + wire n1365_1; + wire n1366; + wire n1367; + wire n1369; + wire n1369_1; + wire n1370; + wire n1372; + wire n1373; + wire n1373_1; + wire n1375; + wire n1376; + wire n1377; + wire n1378; + wire n1379; + wire n1381; + wire n1381_1; + wire n1382; + wire n1384; + wire n1385; + wire n1385_1; + wire n1387; + wire n1388; + wire n1389; + wire n1390; + wire n1391; + wire n1393; + wire n1393_1; + wire n1394; + wire n1396; + wire n1397; + wire n1397_1; + wire n1399; + wire n1400; + wire n1401; + wire n1402; + wire n1403; + wire n1405; + wire n1405_1; + wire n1406; + wire n1408; + wire n1409; + wire n1409_1; + wire n1411; + wire n1412; + wire n1413; + wire n1414; + wire n1415; + wire n1417; + wire n1417_1; + wire n1418; + wire n1420; + wire n1421; + wire n1421_1; + wire n1423; + wire n1424; + wire n1425; + wire n1426; + wire n1427; + wire n1429; + wire n1429_1; + wire n1430; + wire n1432; + wire n1433; + wire n1433_1; + wire n1435; + wire n1436; + wire n1437; + wire n1438; + wire n1439; + wire n1441; + wire n1441_1; + wire n1442; + wire n1444; + wire n1445; + wire n1445_1; + wire n1447; + wire n1448; + wire n1449; + wire n1450; + wire n1451; + wire n1453; + wire n1453_1; + wire n1454; + wire n1456; + wire n1457; + wire n1457_1; + wire n1459; + wire n1460; + wire n1461; + wire n1462; + wire n1463; + wire n1465; + wire n1465_1; + wire n1466; + wire n1468; + wire n1469; + wire n1469_1; + wire n1471; + wire n1472; + wire n1473; + wire n1474; + wire n1475; + wire n1477; + wire n1477_1; + wire n1478; + wire n1480; + wire n1481; + wire n1481_1; + wire n1483; + wire n1484; + wire n1485_1; + wire n1486; + wire n1487; + wire n1489; + wire n1489_1; + wire n1490; + wire n1492; + wire n1493; + wire n1493_1; + wire n1495; + wire n1496; + wire n1497_1; + wire n1498; + wire n1499; + wire n1501; + wire n1501_1; + wire n1502; + wire n1504; + wire n1505; + wire n1505_1; + wire n1507; + wire n1508; + wire n1509; + wire n1510; + wire n1511; + wire n1513; + wire n1513_1; + wire n1514; + wire n1516; + wire n1517; + wire n1517_1; + wire n1519; + wire n1520; + wire n1521; + wire n1522; + wire n1523; + wire n1525; + wire n1525_1; + wire n1526; + wire n1528; + wire n1529; + wire n1529_1; + wire n1531; + wire n1532; + wire n1533; + wire n1534; + wire n1535; + wire n1537; + wire n1537_1; + wire n1538; + wire n1540; + wire n1541; + wire n1541_1; + wire n1543; + wire n1544; + wire n1545; + wire n1546; + wire n1547; + wire n1549; + wire n1549_1; + wire n1550; + wire n1552; + wire n1553; + wire n1553_1; + wire n1555; + wire n1556; + wire n1557; + wire n1558; + wire n1559; + wire n1561; + wire n1561_1; + wire n1562; + wire n1564; + wire n1565; + wire n1565_1; + wire n1567; + wire n1568; + wire n1569; + wire n1570; + wire n1571; + wire n1573; + wire n1573_1; + wire n1574; + wire n1576; + wire n1577; + wire n1577_1; + wire n1579; + wire n1580; + wire n1581; + wire n1582; + wire n1583; + wire n1585; + wire n1585_1; + wire n1586; + wire n1588; + wire n1589; + wire n1589_1; + wire n1591; + wire n1592; + wire n1594; + wire n1594_1; + wire n1595; + wire n1597; + wire n1598; + wire n1599; + wire n1600; + wire n1601; + wire n1603; + wire n1604; + wire n1604_1; + wire n1606; + wire n1607; + wire n1609; + wire n1609_1; + wire n1610; + wire n1612; + wire n1613; + wire n1613_1; + wire n1615; + wire n1616; + wire n1618; + wire n1618_1; + wire n1619; + wire n1621; + wire n1622; + wire n1623; + wire n1624; + wire n1625; + wire n1627; + wire n1628; + wire n1628_1; + wire n1630; + wire n1631; + wire n1633; + wire n1633_1; + wire n1634; + wire n1636; + wire n1637; + wire n1638; + wire n1639; + wire n1640; + wire n1642; + wire n1643; + wire n1643_1; + wire n1645; + wire n1646; + wire n1648; + wire n1648_1; + wire n1649; + wire n1651; + wire n1652; + wire n1653; + wire n1654; + wire n1655; + wire n1657; + wire n1658; + wire n1658_1; + wire n1660; + wire n1661; + wire n1663; + wire n1663_1; + wire n1664; + wire n1666; + wire n1667; + wire n1668; + wire n1669; + wire n1670; + wire n1672; + wire n1673; + wire n1673_1; + wire n1675; + wire n1676; + wire n1678; + wire n1678_1; + wire n1679; + wire n1681; + wire n1682; + wire n1682_1; + wire n1684; + wire n1685; + wire n1686; + wire n1687; + wire n1688; + wire n1690; + wire n1691; + wire n1691_1; + wire n1693; + wire n1694; + wire n1696_1; + wire n1701; + wire n1701_1; + wire n1702; + wire n1704; + wire n1705; + wire n1706_1; + wire n1707; + wire n1708; + wire n1710; + wire n1711; + wire n1711_1; + wire n1713; + wire n1714; + wire n1715; + wire n1715_1; + wire n1717; + wire n1719; + wire n1720; + wire n1721; + wire n1723; + wire n1725; + wire n1725_1; + wire n1727; + wire n1729; + wire n1730_1; + wire n1731; + wire n1733; + wire n1735; + wire n1735_1; + wire n1737; + wire n1739; + wire n1740; + wire n1741; + wire n1743; + wire n1745; + wire n1745_1; + wire n1747; + wire n1749; + wire n1750; + wire n1751; + wire n1753; + wire n1755; + wire n1755_1; + wire n1757; + wire n1760; + wire n1765; + wire n1770; + wire n1775; + wire n1780; + wire n853_1; + wire n857_1; + wire n861_1; + wire n865; + wire n869; + wire n873; + wire n877; + wire n881; + wire n885; + wire n889; + wire n893; + wire n897; + wire n901_1; + wire n905; + wire n909; + wire n913; + wire n917; + wire n921; + wire n925; + wire n929; + wire n933; + wire n937; + wire n941; + wire n945; + wire n949; + wire n953; + wire n957; + wire n961; + wire n965; + wire n969; + wire n973; + wire n977; + wire n981; + wire n985; + wire n989; + wire n993; + wire n997; + (* init = 1'h0 *) + reg n_n2268 = 1'h0; + (* init = 1'h0 *) + reg n_n2272 = 1'h0; + (* init = 1'h0 *) + reg n_n2277 = 1'h0; + (* init = 1'h0 *) + reg n_n2280 = 1'h0; + (* init = 1'h0 *) + reg n_n2288 = 1'h0; + (* init = 1'h0 *) + reg n_n2301 = 1'h0; + (* init = 1'h0 *) + reg n_n2305 = 1'h0; + (* init = 1'h0 *) + reg n_n2310 = 1'h0; + (* init = 1'h0 *) + reg n_n2320 = 1'h0; + (* init = 1'h0 *) + reg n_n2333 = 1'h0; + (* init = 1'h0 *) + reg n_n2337 = 1'h0; + (* init = 1'h0 *) + reg n_n2342 = 1'h0; + (* init = 1'h0 *) + reg n_n2352 = 1'h0; + (* init = 1'h0 *) + reg n_n2365 = 1'h0; + (* init = 1'h0 *) + reg n_n2369 = 1'h0; + (* init = 1'h0 *) + reg n_n2374 = 1'h0; + (* init = 1'h0 *) + reg n_n2384 = 1'h0; + (* init = 1'h0 *) + reg n_n2396 = 1'h0; + (* init = 1'h0 *) + reg n_n2408 = 1'h0; + (* init = 1'h0 *) + reg n_n2410 = 1'h0; + (* init = 1'h0 *) + reg n_n2412 = 1'h0; + (* init = 1'h0 *) + reg n_n2416 = 1'h0; + (* init = 1'h0 *) + reg n_n2420 = 1'h0; + (* init = 1'h0 *) + reg n_n2430 = 1'h0; + (* init = 1'h0 *) + reg n_n2440 = 1'h0; + (* init = 1'h0 *) + reg n_n2448 = 1'h0; + (* init = 1'h0 *) + reg n_n2452 = 1'h0; + (* init = 1'h0 *) + reg n_n2462 = 1'h0; + (* init = 1'h0 *) + reg n_n2474 = 1'h0; + (* init = 1'h0 *) + reg n_n2476 = 1'h0; + (* init = 1'h0 *) + reg n_n2481 = 1'h0; + (* init = 1'h0 *) + reg n_n2485 = 1'h0; + (* init = 1'h0 *) + reg n_n2495 = 1'h0; + (* init = 1'h0 *) + reg n_n2507 = 1'h0; + (* init = 1'h0 *) + reg n_n2513 = 1'h0; + (* init = 1'h0 *) + reg n_n2517 = 1'h0; + input pcount_0_; + input pcount_1_; + input pcount_2_; + input pcount_3_; + output pdata_ready_0_; + input pencrypt_0_; + input pkey_0_; + input pkey_100_; + input pkey_101_; + input pkey_102_; + input pkey_104_; + input pkey_105_; + input pkey_106_; + input pkey_107_; + input pkey_109_; + input pkey_10_; + input pkey_110_; + input pkey_112_; + input pkey_113_; + input pkey_114_; + input pkey_115_; + input pkey_116_; + input pkey_117_; + input pkey_118_; + input pkey_11_; + input pkey_120_; + input pkey_121_; + input pkey_122_; + input pkey_123_; + input pkey_124_; + input pkey_125_; + input pkey_126_; + input pkey_128_; + input pkey_129_; + input pkey_12_; + input pkey_130_; + input pkey_131_; + input pkey_132_; + input pkey_133_; + input pkey_134_; + input pkey_136_; + input pkey_137_; + input pkey_138_; + input pkey_139_; + input pkey_13_; + input pkey_140_; + input pkey_141_; + input pkey_142_; + input pkey_144_; + input pkey_145_; + input pkey_146_; + input pkey_147_; + input pkey_148_; + input pkey_149_; + input pkey_14_; + input pkey_150_; + input pkey_152_; + input pkey_153_; + input pkey_154_; + input pkey_155_; + input pkey_156_; + input pkey_157_; + input pkey_158_; + input pkey_160_; + input pkey_161_; + input pkey_162_; + input pkey_163_; + input pkey_164_; + input pkey_165_; + input pkey_166_; + input pkey_168_; + input pkey_169_; + input pkey_16_; + input pkey_170_; + input pkey_171_; + input pkey_172_; + input pkey_173_; + input pkey_174_; + input pkey_176_; + input pkey_177_; + input pkey_178_; + input pkey_179_; + input pkey_17_; + input pkey_180_; + input pkey_181_; + input pkey_182_; + input pkey_184_; + input pkey_185_; + input pkey_186_; + input pkey_187_; + input pkey_188_; + input pkey_189_; + input pkey_18_; + input pkey_190_; + input pkey_192_; + input pkey_193_; + input pkey_194_; + input pkey_195_; + input pkey_196_; + input pkey_197_; + input pkey_198_; + input pkey_19_; + input pkey_1_; + input pkey_200_; + input pkey_201_; + input pkey_202_; + input pkey_203_; + input pkey_204_; + input pkey_205_; + input pkey_206_; + input pkey_208_; + input pkey_209_; + input pkey_20_; + input pkey_210_; + input pkey_211_; + input pkey_212_; + input pkey_213_; + input pkey_214_; + input pkey_216_; + input pkey_217_; + input pkey_218_; + input pkey_219_; + input pkey_21_; + input pkey_220_; + input pkey_221_; + input pkey_222_; + input pkey_224_; + input pkey_225_; + input pkey_226_; + input pkey_227_; + input pkey_228_; + input pkey_229_; + input pkey_22_; + input pkey_230_; + input pkey_232_; + input pkey_233_; + input pkey_234_; + input pkey_235_; + input pkey_237_; + input pkey_238_; + input pkey_240_; + input pkey_241_; + input pkey_242_; + input pkey_243_; + input pkey_244_; + input pkey_245_; + input pkey_246_; + input pkey_248_; + input pkey_249_; + input pkey_24_; + input pkey_250_; + input pkey_251_; + input pkey_252_; + input pkey_253_; + input pkey_254_; + input pkey_25_; + input pkey_26_; + input pkey_27_; + input pkey_28_; + input pkey_29_; + input pkey_2_; + input pkey_30_; + input pkey_32_; + input pkey_33_; + input pkey_34_; + input pkey_35_; + input pkey_36_; + input pkey_37_; + input pkey_38_; + input pkey_3_; + input pkey_40_; + input pkey_41_; + input pkey_42_; + input pkey_43_; + input pkey_44_; + input pkey_45_; + input pkey_46_; + input pkey_48_; + input pkey_49_; + input pkey_4_; + input pkey_50_; + input pkey_51_; + input pkey_52_; + input pkey_53_; + input pkey_54_; + input pkey_56_; + input pkey_57_; + input pkey_58_; + input pkey_59_; + input pkey_5_; + input pkey_60_; + input pkey_61_; + input pkey_62_; + input pkey_64_; + input pkey_65_; + input pkey_66_; + input pkey_67_; + input pkey_68_; + input pkey_69_; + input pkey_6_; + input pkey_70_; + input pkey_72_; + input pkey_73_; + input pkey_74_; + input pkey_75_; + input pkey_76_; + input pkey_77_; + input pkey_78_; + input pkey_80_; + input pkey_81_; + input pkey_82_; + input pkey_83_; + input pkey_84_; + input pkey_85_; + input pkey_86_; + input pkey_88_; + input pkey_89_; + input pkey_8_; + input pkey_90_; + input pkey_91_; + input pkey_92_; + input pkey_93_; + input pkey_94_; + input pkey_96_; + input pkey_97_; + input pkey_98_; + input pkey_99_; + input pkey_9_; + (* init = 1'h0 *) + output pksi_0_; + reg pksi_0_ = 1'h0; + (* init = 1'h0 *) + output pksi_100_; + reg pksi_100_ = 1'h0; + (* init = 1'h0 *) + output pksi_101_; + reg pksi_101_ = 1'h0; + (* init = 1'h0 *) + output pksi_102_; + reg pksi_102_ = 1'h0; + (* init = 1'h0 *) + output pksi_103_; + reg pksi_103_ = 1'h0; + (* init = 1'h0 *) + output pksi_104_; + reg pksi_104_ = 1'h0; + (* init = 1'h0 *) + output pksi_105_; + reg pksi_105_ = 1'h0; + (* init = 1'h0 *) + output pksi_106_; + reg pksi_106_ = 1'h0; + (* init = 1'h0 *) + output pksi_107_; + reg pksi_107_ = 1'h0; + (* init = 1'h0 *) + output pksi_108_; + reg pksi_108_ = 1'h0; + (* init = 1'h0 *) + output pksi_109_; + reg pksi_109_ = 1'h0; + (* init = 1'h0 *) + output pksi_10_; + reg pksi_10_ = 1'h0; + (* init = 1'h0 *) + output pksi_110_; + reg pksi_110_ = 1'h0; + (* init = 1'h0 *) + output pksi_111_; + reg pksi_111_ = 1'h0; + (* init = 1'h0 *) + output pksi_112_; + reg pksi_112_ = 1'h0; + (* init = 1'h0 *) + output pksi_113_; + reg pksi_113_ = 1'h0; + (* init = 1'h0 *) + output pksi_114_; + reg pksi_114_ = 1'h0; + (* init = 1'h0 *) + output pksi_115_; + reg pksi_115_ = 1'h0; + (* init = 1'h0 *) + output pksi_116_; + reg pksi_116_ = 1'h0; + (* init = 1'h0 *) + output pksi_117_; + reg pksi_117_ = 1'h0; + (* init = 1'h0 *) + output pksi_118_; + reg pksi_118_ = 1'h0; + (* init = 1'h0 *) + output pksi_119_; + reg pksi_119_ = 1'h0; + (* init = 1'h0 *) + output pksi_11_; + reg pksi_11_ = 1'h0; + (* init = 1'h0 *) + output pksi_120_; + reg pksi_120_ = 1'h0; + (* init = 1'h0 *) + output pksi_121_; + reg pksi_121_ = 1'h0; + (* init = 1'h0 *) + output pksi_122_; + reg pksi_122_ = 1'h0; + (* init = 1'h0 *) + output pksi_123_; + reg pksi_123_ = 1'h0; + (* init = 1'h0 *) + output pksi_124_; + reg pksi_124_ = 1'h0; + (* init = 1'h0 *) + output pksi_125_; + reg pksi_125_ = 1'h0; + (* init = 1'h0 *) + output pksi_126_; + reg pksi_126_ = 1'h0; + (* init = 1'h0 *) + output pksi_127_; + reg pksi_127_ = 1'h0; + (* init = 1'h0 *) + output pksi_128_; + reg pksi_128_ = 1'h0; + (* init = 1'h0 *) + output pksi_129_; + reg pksi_129_ = 1'h0; + (* init = 1'h0 *) + output pksi_12_; + reg pksi_12_ = 1'h0; + (* init = 1'h0 *) + output pksi_130_; + reg pksi_130_ = 1'h0; + (* init = 1'h0 *) + output pksi_131_; + reg pksi_131_ = 1'h0; + (* init = 1'h0 *) + output pksi_132_; + reg pksi_132_ = 1'h0; + (* init = 1'h0 *) + output pksi_133_; + reg pksi_133_ = 1'h0; + (* init = 1'h0 *) + output pksi_134_; + reg pksi_134_ = 1'h0; + (* init = 1'h0 *) + output pksi_135_; + reg pksi_135_ = 1'h0; + (* init = 1'h0 *) + output pksi_136_; + reg pksi_136_ = 1'h0; + (* init = 1'h0 *) + output pksi_137_; + reg pksi_137_ = 1'h0; + (* init = 1'h0 *) + output pksi_138_; + reg pksi_138_ = 1'h0; + (* init = 1'h0 *) + output pksi_139_; + reg pksi_139_ = 1'h0; + (* init = 1'h0 *) + output pksi_13_; + reg pksi_13_ = 1'h0; + (* init = 1'h0 *) + output pksi_140_; + reg pksi_140_ = 1'h0; + (* init = 1'h0 *) + output pksi_141_; + reg pksi_141_ = 1'h0; + (* init = 1'h0 *) + output pksi_142_; + reg pksi_142_ = 1'h0; + output pksi_143_; + (* init = 1'h0 *) + output pksi_144_; + reg pksi_144_ = 1'h0; + (* init = 1'h0 *) + output pksi_145_; + reg pksi_145_ = 1'h0; + (* init = 1'h0 *) + output pksi_146_; + reg pksi_146_ = 1'h0; + (* init = 1'h0 *) + output pksi_147_; + reg pksi_147_ = 1'h0; + (* init = 1'h0 *) + output pksi_148_; + reg pksi_148_ = 1'h0; + (* init = 1'h0 *) + output pksi_149_; + reg pksi_149_ = 1'h0; + (* init = 1'h0 *) + output pksi_14_; + reg pksi_14_ = 1'h0; + (* init = 1'h0 *) + output pksi_150_; + reg pksi_150_ = 1'h0; + (* init = 1'h0 *) + output pksi_151_; + reg pksi_151_ = 1'h0; + (* init = 1'h0 *) + output pksi_152_; + reg pksi_152_ = 1'h0; + (* init = 1'h0 *) + output pksi_153_; + reg pksi_153_ = 1'h0; + (* init = 1'h0 *) + output pksi_154_; + reg pksi_154_ = 1'h0; + (* init = 1'h0 *) + output pksi_155_; + reg pksi_155_ = 1'h0; + (* init = 1'h0 *) + output pksi_156_; + reg pksi_156_ = 1'h0; + (* init = 1'h0 *) + output pksi_157_; + reg pksi_157_ = 1'h0; + (* init = 1'h0 *) + output pksi_158_; + reg pksi_158_ = 1'h0; + (* init = 1'h0 *) + output pksi_159_; + reg pksi_159_ = 1'h0; + (* init = 1'h0 *) + output pksi_15_; + reg pksi_15_ = 1'h0; + (* init = 1'h0 *) + output pksi_160_; + reg pksi_160_ = 1'h0; + (* init = 1'h0 *) + output pksi_161_; + reg pksi_161_ = 1'h0; + (* init = 1'h0 *) + output pksi_162_; + reg pksi_162_ = 1'h0; + (* init = 1'h0 *) + output pksi_163_; + reg pksi_163_ = 1'h0; + (* init = 1'h0 *) + output pksi_164_; + reg pksi_164_ = 1'h0; + (* init = 1'h0 *) + output pksi_165_; + reg pksi_165_ = 1'h0; + (* init = 1'h0 *) + output pksi_166_; + reg pksi_166_ = 1'h0; + (* init = 1'h0 *) + output pksi_167_; + reg pksi_167_ = 1'h0; + (* init = 1'h0 *) + output pksi_168_; + reg pksi_168_ = 1'h0; + (* init = 1'h0 *) + output pksi_169_; + reg pksi_169_ = 1'h0; + (* init = 1'h0 *) + output pksi_16_; + reg pksi_16_ = 1'h0; + (* init = 1'h0 *) + output pksi_170_; + reg pksi_170_ = 1'h0; + (* init = 1'h0 *) + output pksi_171_; + reg pksi_171_ = 1'h0; + (* init = 1'h0 *) + output pksi_172_; + reg pksi_172_ = 1'h0; + (* init = 1'h0 *) + output pksi_173_; + reg pksi_173_ = 1'h0; + (* init = 1'h0 *) + output pksi_174_; + reg pksi_174_ = 1'h0; + (* init = 1'h0 *) + output pksi_175_; + reg pksi_175_ = 1'h0; + (* init = 1'h0 *) + output pksi_176_; + reg pksi_176_ = 1'h0; + (* init = 1'h0 *) + output pksi_177_; + reg pksi_177_ = 1'h0; + (* init = 1'h0 *) + output pksi_178_; + reg pksi_178_ = 1'h0; + (* init = 1'h0 *) + output pksi_179_; + reg pksi_179_ = 1'h0; + (* init = 1'h0 *) + output pksi_17_; + reg pksi_17_ = 1'h0; + (* init = 1'h0 *) + output pksi_180_; + reg pksi_180_ = 1'h0; + output pksi_181_; + (* init = 1'h0 *) + output pksi_182_; + reg pksi_182_ = 1'h0; + (* init = 1'h0 *) + output pksi_183_; + reg pksi_183_ = 1'h0; + (* init = 1'h0 *) + output pksi_184_; + reg pksi_184_ = 1'h0; + (* init = 1'h0 *) + output pksi_185_; + reg pksi_185_ = 1'h0; + (* init = 1'h0 *) + output pksi_186_; + reg pksi_186_ = 1'h0; + (* init = 1'h0 *) + output pksi_187_; + reg pksi_187_ = 1'h0; + (* init = 1'h0 *) + output pksi_188_; + reg pksi_188_ = 1'h0; + (* init = 1'h0 *) + output pksi_189_; + reg pksi_189_ = 1'h0; + (* init = 1'h0 *) + output pksi_18_; + reg pksi_18_ = 1'h0; + (* init = 1'h0 *) + output pksi_190_; + reg pksi_190_ = 1'h0; + output pksi_191_; + (* init = 1'h0 *) + output pksi_19_; + reg pksi_19_ = 1'h0; + (* init = 1'h0 *) + output pksi_1_; + reg pksi_1_ = 1'h0; + (* init = 1'h0 *) + output pksi_20_; + reg pksi_20_ = 1'h0; + (* init = 1'h0 *) + output pksi_21_; + reg pksi_21_ = 1'h0; + (* init = 1'h0 *) + output pksi_22_; + reg pksi_22_ = 1'h0; + (* init = 1'h0 *) + output pksi_23_; + reg pksi_23_ = 1'h0; + (* init = 1'h0 *) + output pksi_24_; + reg pksi_24_ = 1'h0; + (* init = 1'h0 *) + output pksi_25_; + reg pksi_25_ = 1'h0; + (* init = 1'h0 *) + output pksi_26_; + reg pksi_26_ = 1'h0; + (* init = 1'h0 *) + output pksi_27_; + reg pksi_27_ = 1'h0; + (* init = 1'h0 *) + output pksi_28_; + reg pksi_28_ = 1'h0; + (* init = 1'h0 *) + output pksi_29_; + reg pksi_29_ = 1'h0; + (* init = 1'h0 *) + output pksi_2_; + reg pksi_2_ = 1'h0; + (* init = 1'h0 *) + output pksi_30_; + reg pksi_30_ = 1'h0; + (* init = 1'h0 *) + output pksi_31_; + reg pksi_31_ = 1'h0; + (* init = 1'h0 *) + output pksi_32_; + reg pksi_32_ = 1'h0; + (* init = 1'h0 *) + output pksi_33_; + reg pksi_33_ = 1'h0; + (* init = 1'h0 *) + output pksi_34_; + reg pksi_34_ = 1'h0; + (* init = 1'h0 *) + output pksi_35_; + reg pksi_35_ = 1'h0; + (* init = 1'h0 *) + output pksi_36_; + reg pksi_36_ = 1'h0; + (* init = 1'h0 *) + output pksi_37_; + reg pksi_37_ = 1'h0; + (* init = 1'h0 *) + output pksi_38_; + reg pksi_38_ = 1'h0; + (* init = 1'h0 *) + output pksi_39_; + reg pksi_39_ = 1'h0; + (* init = 1'h0 *) + output pksi_3_; + reg pksi_3_ = 1'h0; + (* init = 1'h0 *) + output pksi_40_; + reg pksi_40_ = 1'h0; + (* init = 1'h0 *) + output pksi_41_; + reg pksi_41_ = 1'h0; + (* init = 1'h0 *) + output pksi_42_; + reg pksi_42_ = 1'h0; + (* init = 1'h0 *) + output pksi_43_; + reg pksi_43_ = 1'h0; + (* init = 1'h0 *) + output pksi_44_; + reg pksi_44_ = 1'h0; + (* init = 1'h0 *) + output pksi_45_; + reg pksi_45_ = 1'h0; + (* init = 1'h0 *) + output pksi_46_; + reg pksi_46_ = 1'h0; + (* init = 1'h0 *) + output pksi_47_; + reg pksi_47_ = 1'h0; + (* init = 1'h0 *) + output pksi_48_; + reg pksi_48_ = 1'h0; + (* init = 1'h0 *) + output pksi_49_; + reg pksi_49_ = 1'h0; + (* init = 1'h0 *) + output pksi_4_; + reg pksi_4_ = 1'h0; + (* init = 1'h0 *) + output pksi_50_; + reg pksi_50_ = 1'h0; + (* init = 1'h0 *) + output pksi_51_; + reg pksi_51_ = 1'h0; + (* init = 1'h0 *) + output pksi_52_; + reg pksi_52_ = 1'h0; + (* init = 1'h0 *) + output pksi_53_; + reg pksi_53_ = 1'h0; + (* init = 1'h0 *) + output pksi_54_; + reg pksi_54_ = 1'h0; + (* init = 1'h0 *) + output pksi_55_; + reg pksi_55_ = 1'h0; + (* init = 1'h0 *) + output pksi_56_; + reg pksi_56_ = 1'h0; + (* init = 1'h0 *) + output pksi_57_; + reg pksi_57_ = 1'h0; + (* init = 1'h0 *) + output pksi_58_; + reg pksi_58_ = 1'h0; + (* init = 1'h0 *) + output pksi_59_; + reg pksi_59_ = 1'h0; + (* init = 1'h0 *) + output pksi_5_; + reg pksi_5_ = 1'h0; + (* init = 1'h0 *) + output pksi_60_; + reg pksi_60_ = 1'h0; + (* init = 1'h0 *) + output pksi_61_; + reg pksi_61_ = 1'h0; + (* init = 1'h0 *) + output pksi_62_; + reg pksi_62_ = 1'h0; + (* init = 1'h0 *) + output pksi_63_; + reg pksi_63_ = 1'h0; + (* init = 1'h0 *) + output pksi_64_; + reg pksi_64_ = 1'h0; + (* init = 1'h0 *) + output pksi_65_; + reg pksi_65_ = 1'h0; + (* init = 1'h0 *) + output pksi_66_; + reg pksi_66_ = 1'h0; + (* init = 1'h0 *) + output pksi_67_; + reg pksi_67_ = 1'h0; + (* init = 1'h0 *) + output pksi_68_; + reg pksi_68_ = 1'h0; + (* init = 1'h0 *) + output pksi_69_; + reg pksi_69_ = 1'h0; + (* init = 1'h0 *) + output pksi_6_; + reg pksi_6_ = 1'h0; + (* init = 1'h0 *) + output pksi_70_; + reg pksi_70_ = 1'h0; + (* init = 1'h0 *) + output pksi_71_; + reg pksi_71_ = 1'h0; + (* init = 1'h0 *) + output pksi_72_; + reg pksi_72_ = 1'h0; + (* init = 1'h0 *) + output pksi_73_; + reg pksi_73_ = 1'h0; + (* init = 1'h0 *) + output pksi_74_; + reg pksi_74_ = 1'h0; + (* init = 1'h0 *) + output pksi_75_; + reg pksi_75_ = 1'h0; + (* init = 1'h0 *) + output pksi_76_; + reg pksi_76_ = 1'h0; + (* init = 1'h0 *) + output pksi_77_; + reg pksi_77_ = 1'h0; + (* init = 1'h0 *) + output pksi_78_; + reg pksi_78_ = 1'h0; + (* init = 1'h0 *) + output pksi_79_; + reg pksi_79_ = 1'h0; + (* init = 1'h0 *) + output pksi_7_; + reg pksi_7_ = 1'h0; + (* init = 1'h0 *) + output pksi_80_; + reg pksi_80_ = 1'h0; + (* init = 1'h0 *) + output pksi_81_; + reg pksi_81_ = 1'h0; + (* init = 1'h0 *) + output pksi_82_; + reg pksi_82_ = 1'h0; + (* init = 1'h0 *) + output pksi_83_; + reg pksi_83_ = 1'h0; + (* init = 1'h0 *) + output pksi_84_; + reg pksi_84_ = 1'h0; + (* init = 1'h0 *) + output pksi_85_; + reg pksi_85_ = 1'h0; + (* init = 1'h0 *) + output pksi_86_; + reg pksi_86_ = 1'h0; + (* init = 1'h0 *) + output pksi_87_; + reg pksi_87_ = 1'h0; + (* init = 1'h0 *) + output pksi_88_; + reg pksi_88_ = 1'h0; + (* init = 1'h0 *) + output pksi_89_; + reg pksi_89_ = 1'h0; + (* init = 1'h0 *) + output pksi_8_; + reg pksi_8_ = 1'h0; + output pksi_90_; + (* init = 1'h0 *) + output pksi_91_; + reg pksi_91_ = 1'h0; + (* init = 1'h0 *) + output pksi_92_; + reg pksi_92_ = 1'h0; + (* init = 1'h0 *) + output pksi_93_; + reg pksi_93_ = 1'h0; + (* init = 1'h0 *) + output pksi_94_; + reg pksi_94_ = 1'h0; + (* init = 1'h0 *) + output pksi_95_; + reg pksi_95_ = 1'h0; + (* init = 1'h0 *) + output pksi_96_; + reg pksi_96_ = 1'h0; + (* init = 1'h0 *) + output pksi_97_; + reg pksi_97_ = 1'h0; + (* init = 1'h0 *) + output pksi_98_; + reg pksi_98_ = 1'h0; + (* init = 1'h0 *) + output pksi_99_; + reg pksi_99_ = 1'h0; + (* init = 1'h0 *) + output pksi_9_; + reg pksi_9_ = 1'h0; + output pnew_count_0_; + output pnew_count_1_; + output pnew_count_2_; + output pnew_count_3_; + input pstart_0_; + always @(posedge clock) + pksi_50_ <= n853_1; + always @(posedge clock) + pksi_60_ <= n889; + always @(posedge clock) + pksi_40_ <= n1249; + always @(posedge clock) + pksi_103_ <= n1253; + always @(posedge clock) + pksi_110_ <= n1257; + always @(posedge clock) + pksi_3_ <= n1261; + always @(posedge clock) + pksi_151_ <= n1265; + always @(posedge clock) + pksi_164_ <= n1269; + always @(posedge clock) + pksi_177_ <= n1273; + always @(posedge clock) + pksi_2_ <= n1277; + always @(posedge clock) + pksi_152_ <= n1281; + always @(posedge clock) + pksi_163_ <= n1285_1; + always @(posedge clock) + pksi_73_ <= n893; + always @(posedge clock) + pksi_178_ <= n1289_1; + always @(posedge clock) + pksi_189_ <= n1293_1; + always @(posedge clock) + pksi_1_ <= n1297_1; + always @(posedge clock) + pksi_166_ <= n1301_1; + always @(posedge clock) + pksi_179_ <= n1305_1; + always @(posedge clock) + pksi_188_ <= n1309_1; + always @(posedge clock) + pksi_0_ <= n1313; + always @(posedge clock) + pksi_150_ <= n1317; + always @(posedge clock) + pksi_165_ <= n1321; + always @(posedge clock) + pksi_18_ <= n1325; + always @(posedge clock) + pksi_82_ <= n897; + always @(posedge clock) + pksi_29_ <= n1329; + always @(posedge clock) + pksi_142_ <= n1333; + always @(posedge clock) + pksi_173_ <= n1337; + always @(posedge clock) + pksi_186_ <= n1341; + always @(posedge clock) + pksi_19_ <= n1345; + always @(posedge clock) + pksi_28_ <= n1349; + always @(posedge clock) + pksi_130_ <= n1353; + always @(posedge clock) + pksi_141_ <= n1357; + always @(posedge clock) + pksi_167_ <= n1361_1; + always @(posedge clock) + pksi_174_ <= n1365_1; + always @(posedge clock) + pksi_95_ <= n901_1; + always @(posedge clock) + pksi_185_ <= n1369; + always @(posedge clock) + pksi_38_ <= n1373; + always @(posedge clock) + pksi_49_ <= n1377; + always @(posedge clock) + pksi_131_ <= n1381; + always @(posedge clock) + pksi_140_ <= n1385; + always @(posedge clock) + pksi_175_ <= n1389; + always @(posedge clock) + pksi_184_ <= n1393; + always @(posedge clock) + pksi_39_ <= n1397; + always @(posedge clock) + pksi_48_ <= n1401; + always @(posedge clock) + pksi_132_ <= n1405; + always @(posedge clock) + pksi_101_ <= n905; + always @(posedge clock) + pksi_169_ <= n1409; + always @(posedge clock) + pksi_176_ <= n1413; + always @(posedge clock) + pksi_183_ <= n1417; + always @(posedge clock) + pksi_58_ <= n1421; + always @(posedge clock) + pksi_69_ <= n1425; + always @(posedge clock) + pksi_133_ <= n1429; + always @(posedge clock) + pksi_146_ <= n1433; + always @(posedge clock) + pksi_159_ <= n1437; + always @(posedge clock) + pksi_182_ <= n1441; + always @(posedge clock) + pksi_59_ <= n1445; + always @(posedge clock) + pksi_116_ <= n909; + always @(posedge clock) + pksi_68_ <= n1449; + always @(posedge clock) + pksi_134_ <= n1453; + always @(posedge clock) + pksi_145_ <= n1457; + always @(posedge clock) + pksi_170_ <= n1461; + always @(posedge clock) + pksi_9_ <= n1465; + always @(posedge clock) + pksi_78_ <= n1469; + always @(posedge clock) + pksi_89_ <= n1473; + always @(posedge clock) + pksi_135_ <= n1477; + always @(posedge clock) + pksi_144_ <= n1481; + always @(posedge clock) + pksi_157_ <= n1485_1; + always @(posedge clock) + pksi_127_ <= n913; + always @(posedge clock) + pksi_171_ <= n1489_1; + always @(posedge clock) + pksi_180_ <= n1493_1; + always @(posedge clock) + pksi_8_ <= n1497_1; + always @(posedge clock) + pksi_79_ <= n1501; + always @(posedge clock) + pksi_136_ <= n1505; + always @(posedge clock) + pksi_158_ <= n1509; + always @(posedge clock) + pksi_172_ <= n1513; + always @(posedge clock) + pksi_7_ <= n1517; + always @(posedge clock) + pksi_98_ <= n1521; + always @(posedge clock) + pksi_137_ <= n1525; + always @(posedge clock) + pksi_52_ <= n917; + always @(posedge clock) + pksi_155_ <= n1529; + always @(posedge clock) + pksi_160_ <= n1533; + always @(posedge clock) + pksi_6_ <= n1537; + always @(posedge clock) + pksi_99_ <= n1541; + always @(posedge clock) + pksi_138_ <= n1545; + always @(posedge clock) + pksi_149_ <= n1549; + always @(posedge clock) + pksi_156_ <= n1553; + always @(posedge clock) + pksi_5_ <= n1557; + always @(posedge clock) + pksi_148_ <= n1561; + always @(posedge clock) + pksi_153_ <= n1565; + always @(posedge clock) + pksi_63_ <= n921; + always @(posedge clock) + pksi_162_ <= n1569; + always @(posedge clock) + pksi_4_ <= n1573; + always @(posedge clock) + pksi_147_ <= n1577; + always @(posedge clock) + pksi_154_ <= n1581; + always @(posedge clock) + pksi_161_ <= n1585; + always @(posedge clock) + n_n2410 <= n1589_1; + always @(posedge clock) + n_n2513 <= n1594; + always @(posedge clock) + n_n2396 <= n1599; + always @(posedge clock) + n_n2412 <= n1604; + always @(posedge clock) + pksi_187_ <= n1609_1; + always @(posedge clock) + pksi_70_ <= n925; + always @(posedge clock) + n_n2448 <= n1613_1; + always @(posedge clock) + n_n2408 <= n1618_1; + always @(posedge clock) + n_n2420 <= n1623; + always @(posedge clock) + n_n2485 <= n1628; + always @(posedge clock) + n_n2495 <= n1633; + always @(posedge clock) + n_n2384 <= n1638; + always @(posedge clock) + n_n2416 <= n1643_1; + always @(posedge clock) + n_n2440 <= n1648; + always @(posedge clock) + n_n2272 <= n1653; + always @(posedge clock) + n_n2430 <= n1658; + always @(posedge clock) + pksi_61_ <= n857_1; + always @(posedge clock) + pksi_81_ <= n929; + always @(posedge clock) + n_n2481 <= n1663_1; + always @(posedge clock) + n_n2452 <= n1668; + always @(posedge clock) + n_n2462 <= n1673; + always @(posedge clock) + pksi_168_ <= n1678; + always @(posedge clock) + pksi_88_ <= n1682; + always @(posedge clock) + n_n2474 <= n1686; + always @(posedge clock) + n_n2517 <= n1691_1; + always @(posedge clock) + n_n2268 <= n1696_1; + always @(posedge clock) + n_n2476 <= n1701_1; + always @(posedge clock) + n_n2507 <= n1706_1; + always @(posedge clock) + pksi_96_ <= n933; + always @(posedge clock) + pksi_139_ <= n1711; + always @(posedge clock) + n_n2374 <= n1715; + always @(posedge clock) + n_n2337 <= n1720; + always @(posedge clock) + n_n2277 <= n1725; + always @(posedge clock) + n_n2280 <= n1730_1; + always @(posedge clock) + n_n2301 <= n1735_1; + always @(posedge clock) + n_n2320 <= n1740; + always @(posedge clock) + n_n2333 <= n1745; + always @(posedge clock) + n_n2305 <= n1750; + always @(posedge clock) + n_n2365 <= n1755_1; + always @(posedge clock) + pksi_100_ <= n937; + always @(posedge clock) + n_n2369 <= n1760; + always @(posedge clock) + n_n2288 <= n1765; + always @(posedge clock) + n_n2310 <= n1770; + always @(posedge clock) + n_n2342 <= n1775; + always @(posedge clock) + n_n2352 <= n1780; + always @(posedge clock) + pksi_113_ <= n941; + always @(posedge clock) + pksi_53_ <= n945; + always @(posedge clock) + pksi_62_ <= n949; + always @(posedge clock) + pksi_71_ <= n953; + always @(posedge clock) + pksi_80_ <= n957; + always @(posedge clock) + pksi_97_ <= n961; + always @(posedge clock) + pksi_114_ <= n965; + always @(posedge clock) + pksi_72_ <= n861_1; + always @(posedge clock) + pksi_129_ <= n969; + always @(posedge clock) + pksi_54_ <= n973; + always @(posedge clock) + pksi_65_ <= n977; + always @(posedge clock) + pksi_76_ <= n981; + always @(posedge clock) + pksi_87_ <= n985; + always @(posedge clock) + pksi_119_ <= n989; + always @(posedge clock) + pksi_124_ <= n993; + always @(posedge clock) + pksi_55_ <= n997; + always @(posedge clock) + pksi_64_ <= n1001; + always @(posedge clock) + pksi_77_ <= n1005; + always @(posedge clock) + pksi_83_ <= n865; + always @(posedge clock) + pksi_86_ <= n1009; + always @(posedge clock) + pksi_91_ <= n1013_1; + always @(posedge clock) + pksi_123_ <= n1017_1; + always @(posedge clock) + pksi_56_ <= n1021_1; + always @(posedge clock) + pksi_67_ <= n1025_1; + always @(posedge clock) + pksi_74_ <= n1029_1; + always @(posedge clock) + pksi_85_ <= n1033_1; + always @(posedge clock) + pksi_92_ <= n1037_1; + always @(posedge clock) + pksi_117_ <= n1041_1; + always @(posedge clock) + pksi_126_ <= n1045_1; + always @(posedge clock) + pksi_94_ <= n869; + always @(posedge clock) + pksi_57_ <= n1049; + always @(posedge clock) + pksi_66_ <= n1053; + always @(posedge clock) + pksi_75_ <= n1057; + always @(posedge clock) + pksi_84_ <= n1061; + always @(posedge clock) + pksi_93_ <= n1065; + always @(posedge clock) + pksi_118_ <= n1069; + always @(posedge clock) + pksi_125_ <= n1073; + always @(posedge clock) + pksi_190_ <= n1077; + always @(posedge clock) + pksi_14_ <= n1081; + always @(posedge clock) + pksi_25_ <= n1085; + always @(posedge clock) + pksi_102_ <= n873; + always @(posedge clock) + pksi_36_ <= n1089; + always @(posedge clock) + pksi_47_ <= n1093; + always @(posedge clock) + pksi_120_ <= n1097; + always @(posedge clock) + pksi_15_ <= n1101; + always @(posedge clock) + pksi_24_ <= n1105_1; + always @(posedge clock) + pksi_37_ <= n1109_1; + always @(posedge clock) + pksi_46_ <= n1113_1; + always @(posedge clock) + pksi_109_ <= n1117_1; + always @(posedge clock) + pksi_16_ <= n1121_1; + always @(posedge clock) + pksi_27_ <= n1125_1; + always @(posedge clock) + pksi_115_ <= n877; + always @(posedge clock) + pksi_34_ <= n1129; + always @(posedge clock) + pksi_45_ <= n1133; + always @(posedge clock) + pksi_108_ <= n1137; + always @(posedge clock) + pksi_122_ <= n1141; + always @(posedge clock) + pksi_17_ <= n1145; + always @(posedge clock) + pksi_26_ <= n1149; + always @(posedge clock) + pksi_35_ <= n1153; + always @(posedge clock) + pksi_44_ <= n1157; + always @(posedge clock) + pksi_107_ <= n1161; + always @(posedge clock) + pksi_121_ <= n1165; + always @(posedge clock) + pksi_128_ <= n881; + always @(posedge clock) + pksi_10_ <= n1169; + always @(posedge clock) + pksi_21_ <= n1173; + always @(posedge clock) + pksi_32_ <= n1177; + always @(posedge clock) + pksi_43_ <= n1181; + always @(posedge clock) + pksi_106_ <= n1185; + always @(posedge clock) + pksi_111_ <= n1189; + always @(posedge clock) + pksi_11_ <= n1193; + always @(posedge clock) + pksi_20_ <= n1197; + always @(posedge clock) + pksi_33_ <= n1201_1; + always @(posedge clock) + pksi_42_ <= n1205_1; + always @(posedge clock) + pksi_51_ <= n885; + always @(posedge clock) + pksi_105_ <= n1209_1; + always @(posedge clock) + pksi_112_ <= n1213_1; + always @(posedge clock) + pksi_12_ <= n1217_1; + always @(posedge clock) + pksi_23_ <= n1221; + always @(posedge clock) + pksi_30_ <= n1225; + always @(posedge clock) + pksi_41_ <= n1229; + always @(posedge clock) + pksi_104_ <= n1233; + always @(posedge clock) + pksi_13_ <= n1237; + always @(posedge clock) + pksi_22_ <= n1241; + always @(posedge clock) + pksi_31_ <= n1245; + assign n1101_1 = 16'h0881 >> { pcount_0_, pcount_3_, pcount_2_, pcount_1_ }; + assign n1102 = 4'h2 >> { pstart_0_, pencrypt_0_ }; + assign n1103 = 16'h8111 >> { pcount_0_, pcount_3_, pcount_2_, pcount_1_ }; + assign n1613_1 = 64'hfafbf8f9f2f3f0f1 >> { pkey_173_, pkey_181_, n1105, n1106, pencrypt_0_, pstart_0_ }; + assign n1105 = 8'h27 >> { pksi_165_, pksi_147_, n1103 }; + assign n1106 = 16'ha280 >> { pksi_151_, pksi_158_, n1101_1, n1102 }; + assign n1161 = 64'hfafbf2f3f8f9f0f1 >> { pkey_36_, pkey_28_, n1108, n1109, pencrypt_0_, pstart_0_ }; + assign n1108 = 8'h27 >> { pksi_114_, pksi_100_, n1103 }; + assign n1109 = 16'ha280 >> { pksi_116_, pksi_109_, n1101_1, n1102 }; + assign n1257 = 64'hfafbf2f3f8f9f0f1 >> { pkey_45_, pkey_37_, n1111, n1112, pencrypt_0_, pstart_0_ }; + assign n1111 = 8'h27 >> { pksi_99_, n_n2513, n1103 }; + assign n1112 = 16'ha280 >> { pksi_96_, pksi_103_, n1101_1, n1102 }; + assign n1465 = 64'hfafbf2f3f8f9f0f1 >> { pkey_16_, pkey_8_, n1114, n1115, pencrypt_0_, pstart_0_ }; + assign n1114 = 8'h27 >> { pksi_15_, pksi_5_, n1103 }; + assign n1115 = 16'ha280 >> { pksi_17_, pksi_19_, n1101_1, n1102 }; + assign n1413 = 64'hfafbf2f3f8f9f0f1 >> { pkey_204_, pkey_196_, n1117, n1118, pencrypt_0_, pstart_0_ }; + assign n1117 = 8'h27 >> { pksi_168_, pksi_188_, n1103 }; + assign n1118 = 16'ha280 >> { pksi_185_, pksi_169_, n1101_1, n1102 }; + assign n1493_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_197_, pkey_252_, n1120, n1121, pencrypt_0_, pstart_0_ }; + assign n1120 = 8'h27 >> { n_n2410, n_n2408, n1103 }; + assign n1121 = 16'ha280 >> { pksi_186_, pksi_177_, n1101_1, n1102 }; + assign n1289_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_222_, pkey_214_, n1123, n1124, pencrypt_0_, pstart_0_ }; + assign n1123 = 8'h27 >> { pksi_170_, pksi_187_, n1103 }; + assign n1124 = 16'ha280 >> { n_n2420, pksi_184_, n1101_1, n1102 }; + assign n1477 = 64'hfafbf2f3f8f9f0f1 >> { pkey_67_, pkey_190_, n1126, n1127, pencrypt_0_, pstart_0_ }; + assign n1126 = 8'h27 >> { n_n2462, pksi_125_, n1103 }; + assign n1127 = 16'ha280 >> { pksi_150_, pksi_166_, n1101_1, n1102 }; + assign n969 = 64'hfafbf2f3f8f9f0f1 >> { pkey_124_, pkey_116_, n1129_1, n1130, pencrypt_0_, pstart_0_ }; + assign n1129_1 = 8'h27 >> { n_n2474, pksi_132_, n1103 }; + assign n1130 = 16'ha280 >> { pksi_124_, pksi_138_, n1101_1, n1102 }; + assign n1041_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_6_, pkey_61_, n1132, n1133_1, pencrypt_0_, pstart_0_ }; + assign n1132 = 8'h27 >> { pksi_112_, n_n2517, n1103 }; + assign n1133_1 = 16'ha280 >> { n_n2513, pksi_99_, n1101_1, n1102 }; + assign n1069 = 64'hfafbf2f3f8f9f0f1 >> { pkey_62_, pkey_54_, n1135, n1136, pencrypt_0_, pstart_0_ }; + assign n1135 = 8'h27 >> { pksi_173_, pksi_183_, n1103 }; + assign n1136 = 16'ha280 >> { pksi_98_, pksi_102_, n1101_1, n1102 }; + assign n1557 = 64'hfafbf2f3f8f9f0f1 >> { pkey_24_, pkey_16_, n1138, n1139, pencrypt_0_, pstart_0_ }; + assign n1138 = 8'h27 >> { pksi_6_, pksi_15_, n1103 }; + assign n1139 = 16'ha280 >> { pksi_19_, pksi_9_, n1101_1, n1102 }; + assign n1409 = 64'hfafbf2f3f8f9f0f1 >> { pkey_196_, pkey_219_, n1141_1, n1142, pencrypt_0_, pstart_0_ }; + assign n1141_1 = 8'h27 >> { pksi_188_, pksi_176_, n1103 }; + assign n1142 = 16'ha280 >> { n_n2396, pksi_185_, n1101_1, n1102 }; + assign n1618_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_205_, pkey_197_, n1144, n1145_1, pencrypt_0_, pstart_0_ }; + assign n1144 = 8'h27 >> { n_n2412, n_n2410, n1103 }; + assign n1145_1 = 16'ha280 >> { pksi_177_, pksi_180_, n1101_1, n1102 }; + assign n1393 = 64'hfafbf2f3f8f9f0f1 >> { pkey_214_, pkey_206_, n1147, n1148, pencrypt_0_, pstart_0_ }; + assign n1147 = 8'h27 >> { pksi_187_, pksi_178_, n1103 }; + assign n1148 = 16'ha280 >> { pksi_189_, n_n2420, n1101_1, n1102 }; + assign n1073 = 64'hfafbf2f3f8f9f0f1 >> { pkey_75_, pkey_67_, n1150, n1151, pencrypt_0_, pstart_0_ }; + assign n1150 = 8'h27 >> { pksi_137_, n_n2462, n1103 }; + assign n1151 = 16'ha280 >> { pksi_166_, pksi_135_, n1101_1, n1102 }; + assign n1541 = 64'hfafbf2f3f8f9f0f1 >> { pkey_61_, pkey_53_, n1153_1, n1154, pencrypt_0_, pstart_0_ }; + assign n1153_1 = 8'h27 >> { n_n2517, pksi_117_, n1103 }; + assign n1154 = 16'ha280 >> { pksi_110_, n_n2513, n1101_1, n1102 }; + assign n1033_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_234_, pkey_226_, n1156, n1157_1, pencrypt_0_, pstart_0_ }; + assign n1156 = 8'h27 >> { pksi_73_, n_n2277, n1103 }; + assign n1157_1 = 16'ha280 >> { pksi_82_, pksi_93_, n1101_1, n1102 }; + assign n1081 = 64'hfafbf2f3f8f9f0f1 >> { pkey_33_, pkey_25_, n1159, n1160, pencrypt_0_, pstart_0_ }; + assign n1159 = 8'h27 >> { pksi_11_, pksi_2_, n1103 }; + assign n1160 = 16'ha280 >> { pksi_0_, pksi_22_, n1101_1, n1102 }; + assign n1573 = 64'hfafbf2f3f8f9f0f1 >> { pkey_56_, pkey_48_, n1162, n1163, pencrypt_0_, pstart_0_ }; + assign n1162 = 8'h27 >> { pksi_92_, pksi_79_, n1103 }; + assign n1163 = 16'ha280 >> { pksi_6_, pksi_23_, n1101_1, n1102 }; + assign n1623 = 64'hfafbf2f3f8f9f0f1 >> { pkey_206_, pkey_198_, n1165_1, n1166, pencrypt_0_, pstart_0_ }; + assign n1165_1 = 8'h27 >> { pksi_178_, pksi_184_, n1103 }; + assign n1166 = 16'ha280 >> { pksi_171_, pksi_189_, n1101_1, n1102 }; + assign n1357 = 64'hfafbf2f3f8f9f0f1 >> { pkey_70_, pkey_125_, n1168, n1169_1, pencrypt_0_, pstart_0_ }; + assign n1168 = 8'h27 >> { pksi_136_, n_n2485, n1103 }; + assign n1169_1 = 16'ha280 >> { n_n2481, pksi_123_, n1101_1, n1102 }; + assign n941 = 64'hfafbf2f3f8f9f0f1 >> { pkey_27_, pkey_19_, n1171, n1172, pencrypt_0_, pstart_0_ }; + assign n1171 = 8'h27 >> { pksi_104_, pksi_97_, n1103 }; + assign n1172 = 16'ha280 >> { pksi_101_, n_n2495, n1101_1, n1102 }; + assign n877 = 64'hfafbf2f3f8f9f0f1 >> { pkey_21_, pkey_13_, n1174, n1175, pencrypt_0_, pstart_0_ }; + assign n1174 = 8'h27 >> { pksi_103_, pksi_96_, n1103 }; + assign n1175 = 16'ha280 >> { pksi_108_, n_n2507, n1101_1, n1102 }; + assign n1521 = 64'hfafbf2f3f8f9f0f1 >> { pkey_46_, pkey_38_, n1177_1, n1178, pencrypt_0_, pstart_0_ }; + assign n1177_1 = 8'h27 >> { pksi_118_, pksi_102_, n1103 }; + assign n1178 = 16'ha280 >> { pksi_106_, pksi_119_, n1101_1, n1102 }; + assign n1277 = 64'hfafbf2f3f8f9f0f1 >> { pkey_41_, pkey_33_, n1180, n1181_1, pencrypt_0_, pstart_0_ }; + assign n1180 = 8'h27 >> { n_n2384, pksi_11_, n1103 }; + assign n1181_1 = 16'ha280 >> { pksi_22_, pksi_14_, n1101_1, n1102 }; + assign n1221 = 64'hfafbf2f3f8f9f0f1 >> { pkey_48_, pkey_40_, n1183, n1184, pencrypt_0_, pstart_0_ }; + assign n1183 = 8'h27 >> { pksi_79_, pksi_4_, n1103 }; + assign n1184 = 16'ha280 >> { pksi_15_, pksi_6_, n1101_1, n1102 }; + assign n1273 = 64'hfafbf2f3f8f9f0f1 >> { pkey_252_, pkey_244_, n1186, n1187, pencrypt_0_, pstart_0_ }; + assign n1186 = 8'h27 >> { n_n2408, pksi_180_, n1103 }; + assign n1187 = 16'ha280 >> { pksi_172_, pksi_186_, n1101_1, n1102 }; + assign n1293_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_198_, pkey_253_, n1189_1, n1190, pencrypt_0_, pstart_0_ }; + assign n1189_1 = 8'h27 >> { pksi_184_, n_n2420, n1103 }; + assign n1190 = 16'ha280 >> { n_n2416, pksi_171_, n1101_1, n1102 }; + assign n1628 = 64'hfafbf2f3f8f9f0f1 >> { pkey_78_, pkey_70_, n1192, n1193_1, pencrypt_0_, pstart_0_ }; + assign n1192 = 8'h27 >> { pksi_130_, pksi_136_, n1103 }; + assign n1193_1 = 16'ha280 >> { pksi_123_, pksi_141_, n1101_1, n1102 }; + assign n1633 = 64'hfafbf2f3f8f9f0f1 >> { pkey_19_, pkey_11_, n1195, n1196, pencrypt_0_, pstart_0_ }; + assign n1195 = 8'h27 >> { pksi_97_, pksi_113_, n1103 }; + assign n1196 = 16'ha280 >> { pksi_111_, pksi_101_, n1101_1, n1102 }; + assign n961 = 64'hfafbf2f3f8f9f0f1 >> { pkey_4_, pkey_27_, n1198, n1199, pencrypt_0_, pstart_0_ }; + assign n1198 = 8'h27 >> { pksi_116_, pksi_104_, n1103 }; + assign n1199 = 16'ha280 >> { n_n2495, pksi_113_, n1101_1, n1102 }; + assign n873 = 64'hfafbf2f3f8f9f0f1 >> { pkey_54_, pkey_46_, n1201, n1202, pencrypt_0_, pstart_0_ }; + assign n1201 = 8'h27 >> { pksi_183_, pksi_118_, n1103 }; + assign n1202 = 16'ha280 >> { pksi_119_, pksi_98_, n1101_1, n1102 }; + assign n1193 = 64'hfafbf2f3f8f9f0f1 >> { pkey_49_, pkey_41_, n1204, n1205, pencrypt_0_, pstart_0_ }; + assign n1204 = 8'h27 >> { pksi_17_, n_n2384, n1103 }; + assign n1205 = 16'ha280 >> { pksi_14_, pksi_2_, n1101_1, n1102 }; + assign n1337 = 64'hfafbf2f3f8f9f0f1 >> { pkey_203_, pkey_195_, n1207, n1208, pencrypt_0_, pstart_0_ }; + assign n1207 = 8'h27 >> { pksi_185_, n_n2396, n1103 }; + assign n1208 = 16'ha280 >> { pksi_118_, pksi_183_, n1101_1, n1102 }; + assign n1305_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_228_, pkey_220_, n1210, n1211, pencrypt_0_, pstart_0_ }; + assign n1210 = 8'h27 >> { pksi_186_, pksi_172_, n1103 }; + assign n1211 = 16'ha280 >> { pksi_188_, pksi_168_, n1101_1, n1102 }; + assign n1489_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_253_, pkey_245_, n1213, n1214, pencrypt_0_, pstart_0_ }; + assign n1213 = 8'h27 >> { n_n2420, pksi_189_, n1103 }; + assign n1214 = 16'ha280 >> { pksi_182_, n_n2416, n1101_1, n1102 }; + assign n1233 = 64'hfafbf2f3f8f9f0f1 >> { pkey_12_, pkey_4_, n1216, n1217, pencrypt_0_, pstart_0_ }; + assign n1216 = 8'h27 >> { pksi_109_, pksi_116_, n1103 }; + assign n1217 = 16'ha280 >> { pksi_113_, pksi_97_, n1101_1, n1102 }; + assign n1253 = 64'hfafbf2f3f8f9f0f1 >> { pkey_37_, pkey_29_, n1219, n1220, pencrypt_0_, pstart_0_ }; + assign n1219 = 8'h27 >> { n_n2513, pksi_110_, n1103 }; + assign n1220 = 16'ha280 >> { pksi_115_, pksi_96_, n1101_1, n1102 }; + assign n1638 = 64'hfafbf2f3f8f9f0f1 >> { pkey_57_, pkey_49_, n1222, n1223, pencrypt_0_, pstart_0_ }; + assign n1222 = 8'h27 >> { pksi_19_, pksi_17_, n1103 }; + assign n1223 = 16'ha280 >> { pksi_2_, pksi_11_, n1101_1, n1102 }; + assign n1417 = 64'hfafbf2f3f8f9f0f1 >> { pkey_195_, pkey_62_, n1225_1, n1226, pencrypt_0_, pstart_0_ }; + assign n1225_1 = 8'h27 >> { n_n2396, pksi_173_, n1103 }; + assign n1226 = 16'ha280 >> { pksi_102_, pksi_118_, n1101_1, n1102 }; + assign n1643_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_245_, pkey_237_, n1228, n1229_1, pencrypt_0_, pstart_0_ }; + assign n1228 = 8'h27 >> { pksi_189_, pksi_171_, n1103 }; + assign n1229_1 = 16'ha280 >> { pksi_175_, pksi_182_, n1101_1, n1102 }; + assign n909 = 64'hfafbf2f3f8f9f0f1 >> { pkey_20_, pkey_12_, n1231, n1232, pencrypt_0_, pstart_0_ }; + assign n1231 = 8'h27 >> { pksi_107_, pksi_109_, n1103 }; + assign n1232 = 16'ha280 >> { pksi_97_, pksi_104_, n1101_1, n1102 }; + assign n933 = 64'hfafbf2f3f8f9f0f1 >> { pkey_29_, pkey_21_, n1234, n1235, pencrypt_0_, pstart_0_ }; + assign n1234 = 8'h27 >> { pksi_110_, pksi_103_, n1103 }; + assign n1235 = 16'ha280 >> { n_n2507, pksi_115_, n1101_1, n1102 }; + assign n989 = 64'hfafbf2f3f8f9f0f1 >> { pkey_38_, pkey_30_, n1237_1, n1238, pencrypt_0_, pstart_0_ }; + assign n1237_1 = 8'h27 >> { pksi_102_, pksi_98_, n1103 }; + assign n1238 = 16'ha280 >> { pksi_112_, pksi_106_, n1101_1, n1102 }; + assign n1061 = 64'hfafbf2f3f8f9f0f1 >> { pkey_202_, pkey_194_, n1240, n1241_1, pencrypt_0_, pstart_0_ }; + assign n1240 = 8'h27 >> { pksi_82_, n_n2272, n1103 }; + assign n1241_1 = 16'ha280 >> { n_n2268, pksi_75_, n1101_1, n1102 }; + assign n1437 = 64'hfafbf2f3f8f9f0f1 >> { pkey_131_, pkey_254_, n1243, n1244, pencrypt_0_, pstart_0_ }; + assign n1243 = 8'h27 >> { n_n2430, pksi_149_, n1103 }; + assign n1244 = 16'ha280 >> { pksi_174_, pksi_190_, n1101_1, n1102 }; + assign n1648 = 64'hfafbf2f3f8f9f0f1 >> { pkey_188_, pkey_180_, n1246, n1247, pencrypt_0_, pstart_0_ }; + assign n1246 = 8'h27 >> { pksi_153_, pksi_156_, n1103 }; + assign n1247 = 16'ha280 >> { pksi_148_, pksi_162_, n1101_1, n1102 }; + assign n1533 = 64'hfafbf2f3f8f9f0f1 >> { pkey_150_, pkey_142_, n1249_1, n1250, pencrypt_0_, pstart_0_ }; + assign n1249_1 = 8'h27 >> { pksi_167_, pksi_154_, n1103 }; + assign n1250 = 16'ha280 >> { pksi_165_, n_n2452, n1101_1, n1102 }; + assign n881 = 64'hfafbf2f3f8f9f0f1 >> { pkey_76_, pkey_68_, n1252, n1253_1, pencrypt_0_, pstart_0_ }; + assign n1252 = 8'h27 >> { pksi_133_, pksi_140_, n1103 }; + assign n1253_1 = 16'ha280 >> { pksi_137_, pksi_121_, n1101_1, n1102 }; + assign n1653 = 64'hfafbf2f3f8f9f0f1 >> { pkey_210_, pkey_202_, n1255, n1256, pencrypt_0_, pstart_0_ }; + assign n1255 = 8'h27 >> { pksi_93_, pksi_82_, n1103 }; + assign n1256 = 16'ha280 >> { pksi_75_, pksi_84_, n1101_1, n1102 }; + assign n1549 = 64'hfafbf2f3f8f9f0f1 >> { pkey_139_, pkey_131_, n1258, n1259, pencrypt_0_, pstart_0_ }; + assign n1258 = 8'h27 >> { pksi_161_, n_n2430, n1103 }; + assign n1259 = 16'ha280 >> { pksi_190_, pksi_159_, n1101_1, n1102 }; + assign n1581 = 64'hfafbf2f3f8f9f0f1 >> { pkey_158_, pkey_150_, n1261_1, n1262, pencrypt_0_, pstart_0_ }; + assign n1261_1 = 8'h27 >> { pksi_146_, pksi_167_, n1103 }; + assign n1262 = 16'ha280 >> { n_n2452, pksi_160_, n1101_1, n1102 }; + assign n1165 = 64'hfafbf2f3f8f9f0f1 >> { pkey_68_, pkey_91_, n1264, n1265_1, pencrypt_0_, pstart_0_ }; + assign n1264 = 8'h27 >> { pksi_140_, pksi_128_, n1103 }; + assign n1265_1 = 16'ha280 >> { n_n2462, pksi_137_, n1101_1, n1102 }; + assign n1453 = 64'hfafbf2f3f8f9f0f1 >> { pkey_109_, pkey_101_, n1267, n1268, pencrypt_0_, pstart_0_ }; + assign n1267 = 8'h27 >> { pksi_123_, n_n2481, n1103 }; + assign n1268 = 16'ha280 >> { pksi_120_, pksi_127_, n1101_1, n1102 }; + assign n1045_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_118_, pkey_110_, n1270, n1271, pencrypt_0_, pstart_0_ }; + assign n1270 = 8'h27 >> { pksi_111_, pksi_142_, n1103 }; + assign n1271 = 16'ha280 >> { pksi_139_, pksi_122_, n1101_1, n1102 }; + assign n897 = 64'hfafbf2f3f8f9f0f1 >> { pkey_218_, pkey_210_, n1273_1, n1274, pencrypt_0_, pstart_0_ }; + assign n1273_1 = 8'h27 >> { pksi_85_, pksi_93_, n1103 }; + assign n1274 = 16'ha280 >> { pksi_84_, n_n2272, n1101_1, n1102 }; + assign n1658 = 64'hfafbf2f3f8f9f0f1 >> { pkey_147_, pkey_139_, n1276, n1277_1, pencrypt_0_, pstart_0_ }; + assign n1276 = 8'h27 >> { pksi_145_, pksi_161_, n1103 }; + assign n1277_1 = 16'ha280 >> { pksi_159_, pksi_149_, n1101_1, n1102 }; + assign n1321 = 64'hfafbf2f3f8f9f0f1 >> { pkey_134_, pkey_189_, n1279, n1280, pencrypt_0_, pstart_0_ }; + assign n1279 = 8'h27 >> { pksi_160_, n_n2452, n1103 }; + assign n1280 = 16'ha280 >> { n_n2448, pksi_147_, n1101_1, n1102 }; + assign n1525 = 64'hfafbf2f3f8f9f0f1 >> { pkey_91_, pkey_83_, n1282, n1283, pencrypt_0_, pstart_0_ }; + assign n1282 = 8'h27 >> { pksi_128_, pksi_121_, n1103 }; + assign n1283 = 16'ha280 >> { pksi_125_, n_n2462, n1101_1, n1102 }; + assign n1663_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_117_, pkey_109_, n1285, n1286, pencrypt_0_, pstart_0_ }; + assign n1285 = 8'h27 >> { pksi_141_, pksi_123_, n1103 }; + assign n1286 = 16'ha280 >> { pksi_127_, pksi_134_, n1101_1, n1102 }; + assign n905 = 64'hfafbf2f3f8f9f0f1 >> { pkey_11_, pkey_3_, n1288, n1289, pencrypt_0_, pstart_0_ }; + assign n1288 = 8'h27 >> { pksi_113_, n_n2495, n1103 }; + assign n1289 = 16'ha280 >> { pksi_142_, pksi_111_, n1101_1, n1102 }; + assign n1065 = 64'hfafbf2f3f8f9f0f1 >> { pkey_226_, pkey_218_, n1291, n1292, pencrypt_0_, pstart_0_ }; + assign n1291 = 8'h27 >> { n_n2277, pksi_85_, n1103 }; + assign n1292 = 16'ha280 >> { n_n2272, pksi_82_, n1101_1, n1102 }; + assign n1585 = 64'hfafbf2f3f8f9f0f1 >> { pkey_155_, pkey_147_, n1294, n1295, pencrypt_0_, pstart_0_ }; + assign n1294 = 8'h27 >> { pksi_152_, pksi_145_, n1103 }; + assign n1295 = 16'ha280 >> { pksi_149_, n_n2430, n1101_1, n1102 }; + assign n1553 = 64'hfafbf2f3f8f9f0f1 >> { pkey_133_, pkey_188_, n1297, n1298, pencrypt_0_, pstart_0_ }; + assign n1297 = 8'h27 >> { pksi_163_, pksi_153_, n1103 }; + assign n1298 = 16'ha280 >> { pksi_162_, n_n2440, n1101_1, n1102 }; + assign n1668 = 64'hfafbf2f3f8f9f0f1 >> { pkey_142_, pkey_134_, n1300, n1301, pencrypt_0_, pstart_0_ }; + assign n1300 = 8'h27 >> { pksi_154_, pksi_160_, n1103 }; + assign n1301 = 16'ha280 >> { pksi_147_, pksi_165_, n1101_1, n1102 }; + assign n1673 = 64'hfafbf2f3f8f9f0f1 >> { pkey_83_, pkey_75_, n1303, n1304, pencrypt_0_, pstart_0_ }; + assign n1303 = 8'h27 >> { pksi_121_, pksi_137_, n1103 }; + assign n1304 = 16'ha280 >> { pksi_135_, pksi_125_, n1101_1, n1102 }; + assign n1017_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_125_, pkey_117_, n1306, n1307, pencrypt_0_, pstart_0_ }; + assign n1306 = 8'h27 >> { n_n2485, pksi_141_, n1103 }; + assign n1307 = 16'ha280 >> { pksi_134_, n_n2481, n1101_1, n1102 }; + assign n1189 = 64'hfafbf2f3f8f9f0f1 >> { pkey_3_, pkey_126_, n1309, n1310, pencrypt_0_, pstart_0_ }; + assign n1309 = 8'h27 >> { n_n2495, pksi_101_, n1103 }; + assign n1310 = 16'ha280 >> { pksi_126_, pksi_142_, n1101_1, n1102 }; + assign n1037_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_235_, pkey_227_, n1312, n1313_1, pencrypt_0_, pstart_0_ }; + assign n1312 = 8'h27 >> { n_n2268, pksi_88_, n1103 }; + assign n1313_1 = 16'ha280 >> { pksi_4_, pksi_79_, n1101_1, n1102 }; + assign n1101 = 64'hfafbf2f3f8f9f0f1 >> { pkey_32_, pkey_24_, n1315, n1316, pencrypt_0_, pstart_0_ }; + assign n1315 = 8'h27 >> { pksi_23_, pksi_6_, n1103 }; + assign n1316 = 16'ha280 >> { pksi_9_, pksi_5_, n1101_1, n1102 }; + assign n1678 = 64'hfafbf2f3f8f9f0f1 >> { pkey_220_, pkey_212_, n1318, n1319, pencrypt_0_, pstart_0_ }; + assign n1318 = 8'h27 >> { pksi_172_, pksi_179_, n1103 }; + assign n1319 = 16'ha280 >> { pksi_176_, pksi_188_, n1101_1, n1102 }; + assign n1457 = 64'hfafbf2f3f8f9f0f1 >> { pkey_132_, pkey_155_, n1321_1, n1322, pencrypt_0_, pstart_0_ }; + assign n1321_1 = 8'h27 >> { pksi_164_, pksi_152_, n1103 }; + assign n1322 = 16'ha280 >> { n_n2430, pksi_161_, n1101_1, n1102 }; + assign n1481 = 64'hfafbf2f3f8f9f0f1 >> { pkey_157_, pkey_149_, n1324, n1325_1, pencrypt_0_, pstart_0_ }; + assign n1324 = 8'h27 >> { pksi_158_, pksi_151_, n1103 }; + assign n1325_1 = 16'ha280 >> { pksi_153_, pksi_163_, n1101_1, n1102 }; + assign n1317 = 64'hfafbf2f3f8f9f0f1 >> { pkey_182_, pkey_174_, n1327, n1328, pencrypt_0_, pstart_0_ }; + assign n1327 = 8'h27 >> { pksi_135_, pksi_166_, n1103 }; + assign n1328 = 16'ha280 >> { pksi_167_, pksi_146_, n1101_1, n1102 }; + assign n1405 = 64'hfafbf2f3f8f9f0f1 >> { pkey_69_, pkey_124_, n1330, n1331, pencrypt_0_, pstart_0_ }; + assign n1330 = 8'h27 >> { n_n2476, n_n2474, n1103 }; + assign n1331 = 16'ha280 >> { pksi_138_, pksi_129_, n1101_1, n1102 }; + assign n1353 = 64'hfafbf2f3f8f9f0f1 >> { pkey_94_, pkey_86_, n1333_1, n1334, pencrypt_0_, pstart_0_ }; + assign n1333_1 = 8'h27 >> { pksi_122_, pksi_139_, n1103 }; + assign n1334 = 16'ha280 >> { n_n2485, pksi_136_, n1101_1, n1102 }; + assign n1209_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_60_, pkey_52_, n1336, n1337_1, pencrypt_0_, pstart_0_ }; + assign n1336 = 8'h27 >> { n_n2507, pksi_108_, n1103 }; + assign n1337_1 = 16'ha280 >> { pksi_100_, pksi_114_, n1101_1, n1102 }; + assign n1213_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_22_, pkey_14_, n1339, n1340, pencrypt_0_, pstart_0_ }; + assign n1339 = 8'h27 >> { pksi_119_, pksi_106_, n1103 }; + assign n1340 = 16'ha280 >> { pksi_117_, n_n2517, n1101_1, n1102 }; + assign n1682 = 64'hfafbf2f3f8f9f0f1 >> { pkey_243_, pkey_235_, n1342, n1343, pencrypt_0_, pstart_0_ }; + assign n1342 = 8'h27 >> { pksi_75_, n_n2268, n1103 }; + assign n1343 = 16'ha280 >> { pksi_79_, pksi_92_, n1101_1, n1102 }; + assign n1537 = 64'hfafbf2f3f8f9f0f1 >> { pkey_40_, pkey_32_, n1345_1, n1346, pencrypt_0_, pstart_0_ }; + assign n1345_1 = 8'h27 >> { pksi_4_, pksi_23_, n1103 }; + assign n1346 = 16'ha280 >> { pksi_5_, pksi_15_, n1101_1, n1102 }; + assign n1309_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_212_, pkey_204_, n1348, n1349_1, pencrypt_0_, pstart_0_ }; + assign n1348 = 8'h27 >> { pksi_179_, pksi_168_, n1103 }; + assign n1349_1 = 16'ha280 >> { pksi_169_, pksi_176_, n1101_1, n1102 }; + assign n1281 = 64'hfafbf2f3f8f9f0f1 >> { pkey_140_, pkey_132_, n1351, n1352, pencrypt_0_, pstart_0_ }; + assign n1351 = 8'h27 >> { pksi_157_, pksi_164_, n1103 }; + assign n1352 = 16'ha280 >> { pksi_161_, pksi_145_, n1101_1, n1102 }; + assign n1285_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_149_, pkey_141_, n1354, n1355, pencrypt_0_, pstart_0_ }; + assign n1354 = 8'h27 >> { pksi_151_, pksi_144_, n1103 }; + assign n1355 = 16'ha280 >> { pksi_156_, pksi_153_, n1101_1, n1102 }; + assign n1301_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_190_, pkey_182_, n1357_1, n1358, pencrypt_0_, pstart_0_ }; + assign n1357_1 = 8'h27 >> { pksi_125_, pksi_135_, n1103 }; + assign n1358 = 16'ha280 >> { pksi_146_, pksi_150_, n1101_1, n1102 }; + assign n1381 = 64'hfafbf2f3f8f9f0f1 >> { pkey_100_, pkey_92_, n1360, n1361, pencrypt_0_, pstart_0_ }; + assign n1360 = 8'h27 >> { pksi_138_, pksi_124_, n1103 }; + assign n1361 = 16'ha280 >> { pksi_140_, pksi_133_, n1101_1, n1102 }; + assign n1686 = 64'hfafbf2f3f8f9f0f1 >> { pkey_77_, pkey_69_, n1363, n1364, pencrypt_0_, pstart_0_ }; + assign n1363 = 8'h27 >> { pksi_120_, n_n2476, n1103 }; + assign n1364 = 16'ha280 >> { pksi_129_, pksi_132_, n1101_1, n1102 }; + assign n1505 = 64'hfafbf2f3f8f9f0f1 >> { pkey_86_, pkey_78_, n1366, n1367, pencrypt_0_, pstart_0_ }; + assign n1366 = 8'h27 >> { pksi_139_, pksi_130_, n1103 }; + assign n1367 = 16'ha280 >> { pksi_141_, n_n2485, n1101_1, n1102 }; + assign n1137 = 64'hfafbf2f3f8f9f0f1 >> { pkey_5_, pkey_60_, n1369_1, n1370, pencrypt_0_, pstart_0_ }; + assign n1369_1 = 8'h27 >> { pksi_115_, n_n2507, n1103 }; + assign n1370 = 16'ha280 >> { pksi_114_, pksi_105_, n1101_1, n1102 }; + assign n1691_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_14_, pkey_6_, n1372, n1373_1, pencrypt_0_, pstart_0_ }; + assign n1372 = 8'h27 >> { pksi_106_, pksi_112_, n1103 }; + assign n1373_1 = 16'ha280 >> { pksi_99_, pksi_117_, n1101_1, n1102 }; + assign n1696_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_251_, pkey_243_, n1375, n1376, pencrypt_0_, pstart_0_ }; + assign n1375 = 8'h27 >> { pksi_84_, pksi_75_, n1103 }; + assign n1376 = 16'ha280 >> { pksi_92_, pksi_88_, n1101_1, n1102 }; + assign n1389 = 64'hfafbf2f3f8f9f0f1 >> { pkey_229_, pkey_221_, n1378, n1379, pencrypt_0_, pstart_0_ }; + assign n1378 = 8'h27 >> { n_n2416, pksi_182_, n1103 }; + assign n1379 = 16'ha280 >> { n_n2410, n_n2412, n1101_1, n1102 }; + assign n1077 = 64'hfafbf2f3f8f9f0f1 >> { pkey_254_, pkey_246_, n1381_1, n1382, pencrypt_0_, pstart_0_ }; + assign n1381_1 = 8'h27 >> { pksi_149_, pksi_159_, n1103 }; + assign n1382 = 16'ha280 >> { pksi_170_, pksi_174_, n1101_1, n1102 }; + assign n1269 = 64'hfafbf2f3f8f9f0f1 >> { pkey_148_, pkey_140_, n1384, n1385_1, pencrypt_0_, pstart_0_ }; + assign n1384 = 8'h27 >> { pksi_155_, pksi_157_, n1103 }; + assign n1385_1 = 16'ha280 >> { pksi_145_, pksi_152_, n1101_1, n1102 }; + assign n1509 = 64'hfafbf2f3f8f9f0f1 >> { pkey_173_, pkey_165_, n1387, n1388, pencrypt_0_, pstart_0_ }; + assign n1387 = 8'h27 >> { pksi_147_, n_n2448, n1103 }; + assign n1388 = 16'ha280 >> { pksi_144_, pksi_151_, n1101_1, n1102 }; + assign n1361_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_166_, pkey_158_, n1390, n1391, pencrypt_0_, pstart_0_ }; + assign n1390 = 8'h27 >> { pksi_150_, pksi_146_, n1103 }; + assign n1391 = 16'ha280 >> { pksi_160_, pksi_154_, n1101_1, n1102 }; + assign n1429 = 64'hfafbf2f3f8f9f0f1 >> { pkey_92_, pkey_84_, n1393_1, n1394, pencrypt_0_, pstart_0_ }; + assign n1393_1 = 8'h27 >> { pksi_124_, pksi_131_, n1103 }; + assign n1394 = 16'ha280 >> { pksi_128_, pksi_140_, n1101_1, n1102 }; + assign n1141 = 64'hfafbf2f3f8f9f0f1 >> { pkey_110_, pkey_102_, n1396, n1397_1, pencrypt_0_, pstart_0_ }; + assign n1396 = 8'h27 >> { pksi_142_, pksi_126_, n1103 }; + assign n1397_1 = 16'ha280 >> { pksi_130_, pksi_139_, n1101_1, n1102 }; + assign n1706_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_13_, pkey_5_, n1399, n1400, pencrypt_0_, pstart_0_ }; + assign n1399 = 8'h27 >> { pksi_96_, pksi_115_, n1103 }; + assign n1400 = 16'ha280 >> { pksi_105_, pksi_108_, n1101_1, n1102 }; + assign n1057 = 64'hfafbf2f3f8f9f0f1 >> { pkey_194_, pkey_251_, n1402, n1403, pencrypt_0_, pstart_0_ }; + assign n1402 = 8'h27 >> { n_n2272, pksi_84_, n1103 }; + assign n1403 = 16'ha280 >> { pksi_88_, n_n2268, n1101_1, n1102 }; + assign n1441 = 64'hfafbf2f3f8f9f0f1 >> { pkey_237_, pkey_229_, n1405_1, n1406, pencrypt_0_, pstart_0_ }; + assign n1405_1 = 8'h27 >> { pksi_171_, n_n2416, n1103 }; + assign n1406 = 16'ha280 >> { n_n2412, pksi_175_, n1101_1, n1102 }; + assign n1365_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_246_, pkey_238_, n1408, n1409_1, pencrypt_0_, pstart_0_ }; + assign n1408 = 8'h27 >> { pksi_159_, pksi_190_, n1103 }; + assign n1409_1 = 16'ha280 >> { pksi_187_, pksi_170_, n1101_1, n1102 }; + assign n1485_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_156_, pkey_148_, n1411, n1412, pencrypt_0_, pstart_0_ }; + assign n1411 = 8'h27 >> { pksi_148_, pksi_155_, n1103 }; + assign n1412 = 16'ha280 >> { pksi_152_, pksi_164_, n1101_1, n1102 }; + assign n1265 = 64'hfafbf2f3f8f9f0f1 >> { pkey_165_, pkey_157_, n1414, n1415, pencrypt_0_, pstart_0_ }; + assign n1414 = 8'h27 >> { n_n2448, pksi_158_, n1103 }; + assign n1415 = 16'ha280 >> { pksi_163_, pksi_144_, n1101_1, n1102 }; + assign n1433 = 64'hfafbf2f3f8f9f0f1 >> { pkey_174_, pkey_166_, n1417_1, n1418, pencrypt_0_, pstart_0_ }; + assign n1417_1 = 8'h27 >> { pksi_166_, pksi_150_, n1103 }; + assign n1418 = 16'ha280 >> { pksi_154_, pksi_167_, n1101_1, n1102 }; + assign n1385 = 64'hfafbf2f3f8f9f0f1 >> { pkey_84_, pkey_76_, n1420, n1421_1, pencrypt_0_, pstart_0_ }; + assign n1420 = 8'h27 >> { pksi_131_, pksi_133_, n1103 }; + assign n1421_1 = 16'ha280 >> { pksi_121_, pksi_128_, n1101_1, n1102 }; + assign n1711 = 64'hfafbf2f3f8f9f0f1 >> { pkey_102_, pkey_94_, n1423, n1424, pencrypt_0_, pstart_0_ }; + assign n1423 = 8'h27 >> { pksi_126_, pksi_122_, n1103 }; + assign n1424 = 16'ha280 >> { pksi_136_, pksi_130_, n1101_1, n1102 }; + assign n1185 = 64'hfafbf2f3f8f9f0f1 >> { pkey_30_, pkey_22_, n1426, n1427, pencrypt_0_, pstart_0_ }; + assign n1426 = 8'h27 >> { pksi_98_, pksi_119_, n1103 }; + assign n1427 = 16'ha280 >> { n_n2517, pksi_112_, n1101_1, n1102 }; + assign n1049 = 64'hfafbf2f3f8f9f0f1 >> { pkey_144_, pkey_136_, n1429_1, n1430, pencrypt_0_, pstart_0_ }; + assign n1429_1 = 8'h27 >> { pksi_63_, pksi_53_, n1103 }; + assign n1430 = 16'ha280 >> { pksi_65_, pksi_67_, n1101_1, n1102 }; + assign n1089 = 64'hfafbf2f3f8f9f0f1 >> { pkey_74_, pkey_66_, n1432, n1433_1, pencrypt_0_, pstart_0_ }; + assign n1432 = 8'h27 >> { pksi_34_, n_n2337, n1103 }; + assign n1433_1 = 16'ha280 >> { n_n2333, pksi_27_, n1101_1, n1102 }; + assign n1373 = 64'hfafbf2f3f8f9f0f1 >> { pkey_97_, pkey_89_, n1435, n1436, pencrypt_0_, pstart_0_ }; + assign n1435 = 8'h27 >> { pksi_35_, pksi_26_, n1103 }; + assign n1436 = 16'ha280 >> { pksi_24_, pksi_46_, n1101_1, n1102 }; + assign n1349 = 64'hfafbf2f3f8f9f0f1 >> { pkey_120_, pkey_112_, n1438, n1439, pencrypt_0_, pstart_0_ }; + assign n1438 = 8'h27 >> { pksi_20_, pksi_7_, n1103 }; + assign n1439 = 16'ha280 >> { pksi_30_, pksi_47_, n1101_1, n1102 }; + assign n1715 = 64'hfafbf2f3f8f9f0f1 >> { pkey_50_, pkey_42_, n1441_1, n1442, pencrypt_0_, pstart_0_ }; + assign n1441_1 = 8'h27 >> { pksi_18_, pksi_1_, n1103 }; + assign n1442 = 16'ha280 >> { pksi_21_, pksi_13_, n1101_1, n1102 }; + assign n945 = 64'hfafbf2f3f8f9f0f1 >> { pkey_152_, pkey_144_, n1444, n1445_1, pencrypt_0_, pstart_0_ }; + assign n1444 = 8'h27 >> { pksi_54_, pksi_63_, n1103 }; + assign n1445_1 = 16'ha280 >> { pksi_67_, pksi_57_, n1101_1, n1102 }; + assign n1125_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_66_, pkey_123_, n1447, n1448, pencrypt_0_, pstart_0_ }; + assign n1447 = 8'h27 >> { n_n2337, pksi_36_, n1103 }; + assign n1448 = 16'ha280 >> { pksi_40_, n_n2333, n1101_1, n1102 }; + assign n1149 = 64'hfafbf2f3f8f9f0f1 >> { pkey_105_, pkey_97_, n1450, n1451, pencrypt_0_, pstart_0_ }; + assign n1450 = 8'h27 >> { n_n2352, pksi_35_, n1103 }; + assign n1451 = 16'ha280 >> { pksi_46_, pksi_38_, n1101_1, n1102 }; + assign n1093 = 64'hfafbf2f3f8f9f0f1 >> { pkey_112_, pkey_104_, n1453_1, n1454, pencrypt_0_, pstart_0_ }; + assign n1453_1 = 8'h27 >> { pksi_7_, pksi_28_, n1103 }; + assign n1454 = 16'ha280 >> { pksi_39_, pksi_30_, n1101_1, n1102 }; + assign n1297_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_58_, pkey_50_, n1456, n1457_1, pencrypt_0_, pstart_0_ }; + assign n1456 = 8'h27 >> { pksi_8_, pksi_18_, n1103 }; + assign n1457_1 = 16'ha280 >> { pksi_13_, n_n2374, n1101_1, n1102 }; + assign n921 = 64'hfafbf2f3f8f9f0f1 >> { pkey_160_, pkey_152_, n1459, n1460, pencrypt_0_, pstart_0_ }; + assign n1459 = 8'h27 >> { pksi_71_, pksi_54_, n1103 }; + assign n1460 = 16'ha280 >> { pksi_57_, pksi_53_, n1101_1, n1102 }; + assign n1129 = 64'hfafbf2f3f8f9f0f1 >> { pkey_90_, pkey_82_, n1462, n1463, pencrypt_0_, pstart_0_ }; + assign n1462 = 8'h27 >> { pksi_37_, pksi_45_, n1103 }; + assign n1463 = 16'ha280 >> { pksi_36_, n_n2337, n1101_1, n1102 }; + assign n1105_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_81_, pkey_73_, n1465_1, n1466, pencrypt_0_, pstart_0_ }; + assign n1465_1 = 8'h27 >> { pksi_38_, pksi_46_, n1103 }; + assign n1466 = 16'ha280 >> { pksi_42_, pksi_32_, n1101_1, n1102 }; + assign n1225 = 64'hfafbf2f3f8f9f0f1 >> { pkey_104_, pkey_96_, n1468, n1469_1, pencrypt_0_, pstart_0_ }; + assign n1468 = 8'h27 >> { pksi_28_, pksi_47_, n1103 }; + assign n1469_1 = 16'ha280 >> { pksi_29_, pksi_39_, n1101_1, n1102 }; + assign n1325 = 64'hfafbf2f3f8f9f0f1 >> { pkey_1_, pkey_58_, n1471, n1472, pencrypt_0_, pstart_0_ }; + assign n1471 = 8'h27 >> { pksi_0_, pksi_8_, n1103 }; + assign n1472 = 16'ha280 >> { n_n2374, pksi_1_, n1101_1, n1102 }; + assign n1501 = 64'hfafbf2f3f8f9f0f1 >> { pkey_227_, pkey_56_, n1474, n1475, pencrypt_0_, pstart_0_ }; + assign n1474 = 8'h27 >> { pksi_88_, pksi_92_, n1103 }; + assign n1475 = 16'ha280 >> { pksi_23_, pksi_4_, n1101_1, n1102 }; + assign n973 = 64'hfafbf2f3f8f9f0f1 >> { pkey_168_, pkey_160_, n1477_1, n1478, pencrypt_0_, pstart_0_ }; + assign n1477_1 = 8'h27 >> { pksi_52_, pksi_71_, n1103 }; + assign n1478 = 16'ha280 >> { pksi_53_, pksi_63_, n1101_1, n1102 }; + assign n1720 = 64'hfafbf2f3f8f9f0f1 >> { pkey_82_, pkey_74_, n1480, n1481_1, pencrypt_0_, pstart_0_ }; + assign n1480 = 8'h27 >> { pksi_45_, pksi_34_, n1103 }; + assign n1481_1 = 16'ha280 >> { pksi_27_, pksi_36_, n1101_1, n1102 }; + assign n1113_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_89_, pkey_81_, n1483, n1484, pencrypt_0_, pstart_0_ }; + assign n1483 = 8'h27 >> { pksi_26_, pksi_38_, n1103 }; + assign n1484 = 16'ha280 >> { pksi_32_, pksi_24_, n1101_1, n1102 }; + assign n1397 = 64'hfafbf2f3f8f9f0f1 >> { pkey_96_, pkey_88_, n1486, n1487, pencrypt_0_, pstart_0_ }; + assign n1486 = 8'h27 >> { pksi_47_, pksi_30_, n1103 }; + assign n1487 = 16'ha280 >> { pksi_33_, pksi_29_, n1101_1, n1102 }; + assign n1497_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_9_, pkey_1_, n1489, n1490, pencrypt_0_, pstart_0_ }; + assign n1489 = 8'h27 >> { pksi_22_, pksi_0_, n1103 }; + assign n1490 = 16'ha280 >> { pksi_1_, pksi_18_, n1101_1, n1102 }; + assign n1725 = 64'hfafbf2f3f8f9f0f1 >> { pkey_242_, pkey_234_, n1492, n1493, pencrypt_0_, pstart_0_ }; + assign n1492 = 8'h27 >> { n_n2280, pksi_73_, n1103 }; + assign n1493 = 16'ha280 >> { pksi_93_, pksi_85_, n1101_1, n1102 }; + assign n1013_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_200_, pkey_192_, n1495, n1496, pencrypt_0_, pstart_0_ }; + assign n1495 = 8'h27 >> { pksi_77_, pksi_81_, n1103 }; + assign n1496 = 16'ha280 >> { n_n2288, pksi_89_, n1101_1, n1102 }; + assign n885 = 64'hfafbf2f3f8f9f0f1 >> { pkey_130_, pkey_187_, n1498, n1499, pencrypt_0_, pstart_0_ }; + assign n1498 = 8'h27 >> { n_n2305, pksi_60_, n1103 }; + assign n1499 = 16'ha280 >> { pksi_64_, n_n2301, n1101_1, n1102 }; + assign n925 = 64'hfafbf2f3f8f9f0f1 >> { pkey_153_, pkey_145_, n1501_1, n1502, pencrypt_0_, pstart_0_ }; + assign n1501_1 = 8'h27 >> { pksi_50_, pksi_62_, n1103 }; + assign n1502 = 16'ha280 >> { pksi_56_, pksi_48_, n1101_1, n1102 }; + assign n1313 = 64'hfafbf2f3f8f9f0f1 >> { pkey_17_, pkey_9_, n1504, n1505_1, pencrypt_0_, pstart_0_ }; + assign n1504 = 8'h27 >> { pksi_14_, pksi_22_, n1103 }; + assign n1505_1 = 16'ha280 >> { pksi_18_, pksi_8_, n1101_1, n1102 }; + assign n893 = 64'hfafbf2f3f8f9f0f1 >> { pkey_250_, pkey_242_, n1507, n1508, pencrypt_0_, pstart_0_ }; + assign n1507 = 8'h27 >> { pksi_80_, n_n2280, n1103 }; + assign n1508 = 16'ha280 >> { pksi_85_, n_n2277, n1101_1, n1102 }; + assign n1473 = 64'hfafbf2f3f8f9f0f1 >> { pkey_192_, pkey_249_, n1510, n1511, pencrypt_0_, pstart_0_ }; + assign n1510 = 8'h27 >> { pksi_81_, pksi_91_, n1103 }; + assign n1511 = 16'ha280 >> { pksi_83_, n_n2288, n1101_1, n1102 }; + assign n889 = 64'hfafbf2f3f8f9f0f1 >> { pkey_138_, pkey_130_, n1513_1, n1514, pencrypt_0_, pstart_0_ }; + assign n1513_1 = 8'h27 >> { pksi_58_, n_n2305, n1103 }; + assign n1514 = 16'ha280 >> { n_n2301, pksi_51_, n1101_1, n1102 }; + assign n1401 = 64'hfafbf2f3f8f9f0f1 >> { pkey_145_, pkey_137_, n1516, n1517_1, pencrypt_0_, pstart_0_ }; + assign n1516 = 8'h27 >> { pksi_62_, pksi_70_, n1103 }; + assign n1517_1 = 16'ha280 >> { pksi_66_, pksi_56_, n1101_1, n1102 }; + assign n1241 = 64'hfafbf2f3f8f9f0f1 >> { pkey_25_, pkey_17_, n1519, n1520, pencrypt_0_, pstart_0_ }; + assign n1519 = 8'h27 >> { pksi_2_, pksi_14_, n1103 }; + assign n1520 = 16'ha280 >> { pksi_8_, pksi_0_, n1101_1, n1102 }; + assign n1730_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_193_, pkey_250_, n1522, n1523, pencrypt_0_, pstart_0_ }; + assign n1522 = 8'h27 >> { pksi_72_, pksi_80_, n1103 }; + assign n1523 = 16'ha280 >> { n_n2277, pksi_73_, n1101_1, n1102 }; + assign n1005 = 64'hfafbf2f3f8f9f0f1 >> { pkey_216_, pkey_208_, n1525_1, n1526, pencrypt_0_, pstart_0_ }; + assign n1525_1 = 8'h27 >> { pksi_78_, pksi_87_, n1103 }; + assign n1526 = 16'ha280 >> { pksi_91_, pksi_81_, n1101_1, n1102 }; + assign n1001 = 64'hfafbf2f3f8f9f0f1 >> { pkey_179_, pkey_171_, n1528, n1529_1, pencrypt_0_, pstart_0_ }; + assign n1528 = 8'h27 >> { pksi_51_, n_n2301, n1103 }; + assign n1529_1 = 16'ha280 >> { pksi_55_, pksi_68_, n1101_1, n1102 }; + assign n1021_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_137_, pkey_129_, n1531, n1532, pencrypt_0_, pstart_0_ }; + assign n1531 = 8'h27 >> { pksi_70_, pksi_48_, n1103 }; + assign n1532 = 16'ha280 >> { pksi_49_, pksi_66_, n1101_1, n1102 }; + assign n957 = 64'hfafbf2f3f8f9f0f1 >> { pkey_201_, pkey_193_, n1534, n1535, pencrypt_0_, pstart_0_ }; + assign n1534 = 8'h27 >> { pksi_94_, pksi_72_, n1103 }; + assign n1535 = 16'ha280 >> { pksi_73_, n_n2280, n1101_1, n1102 }; + assign n929 = 64'hfafbf2f3f8f9f0f1 >> { pkey_208_, pkey_200_, n1537_1, n1538, pencrypt_0_, pstart_0_ }; + assign n1537_1 = 8'h27 >> { pksi_87_, pksi_77_, n1103 }; + assign n1538 = 16'ha280 >> { pksi_89_, pksi_91_, n1101_1, n1102 }; + assign n1735_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_187_, pkey_179_, n1540, n1541_1, pencrypt_0_, pstart_0_ }; + assign n1540 = 8'h27 >> { pksi_60_, pksi_51_, n1103 }; + assign n1541_1 = 16'ha280 >> { pksi_68_, pksi_64_, n1101_1, n1102 }; + assign n1053 = 64'hfafbf2f3f8f9f0f1 >> { pkey_129_, pkey_186_, n1543, n1544, pencrypt_0_, pstart_0_ }; + assign n1543 = 8'h27 >> { pksi_48_, pksi_56_, n1103 }; + assign n1544 = 16'ha280 >> { n_n2310, pksi_49_, n1101_1, n1102 }; + assign n861_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_209_, pkey_201_, n1546, n1547, pencrypt_0_, pstart_0_ }; + assign n1546 = 8'h27 >> { pksi_86_, pksi_94_, n1103 }; + assign n1547 = 16'ha280 >> { n_n2280, pksi_80_, n1101_1, n1102 }; + assign n1469 = 64'hfafbf2f3f8f9f0f1 >> { pkey_232_, pkey_224_, n1549_1, n1550, pencrypt_0_, pstart_0_ }; + assign n1549_1 = 8'h27 >> { pksi_76_, pksi_95_, n1103 }; + assign n1550 = 16'ha280 >> { pksi_77_, pksi_87_, n1101_1, n1102 }; + assign n1425 = 64'hfafbf2f3f8f9f0f1 >> { pkey_162_, pkey_154_, n1552, n1553_1, pencrypt_0_, pstart_0_ }; + assign n1552 = 8'h27 >> { n_n2310, pksi_61_, n1103 }; + assign n1553_1 = 16'ha280 >> { n_n2305, pksi_58_, n1101_1, n1102 }; + assign n1740 = 64'hfafbf2f3f8f9f0f1 >> { pkey_185_, pkey_177_, n1555, n1556, pencrypt_0_, pstart_0_ }; + assign n1555 = 8'h27 >> { pksi_67_, pksi_65_, n1103 }; + assign n1556 = 16'ha280 >> { pksi_50_, pksi_59_, n1101_1, n1102 }; + assign n1249 = 64'hfafbf2f3f8f9f0f1 >> { pkey_115_, pkey_107_, n1558, n1559, pencrypt_0_, pstart_0_ }; + assign n1558 = 8'h27 >> { pksi_27_, n_n2333, n1103 }; + assign n1559 = 16'ha280 >> { pksi_31_, pksi_44_, n1101_1, n1102 }; + assign n1177 = 64'hfafbf2f3f8f9f0f1 >> { pkey_73_, pkey_65_, n1561_1, n1562, pencrypt_0_, pstart_0_ }; + assign n1561_1 = 8'h27 >> { pksi_46_, pksi_24_, n1103 }; + assign n1562 = 16'ha280 >> { pksi_25_, pksi_42_, n1101_1, n1102 }; + assign n869 = 64'hfafbf2f3f8f9f0f1 >> { pkey_217_, pkey_209_, n1564, n1565_1, pencrypt_0_, pstart_0_ }; + assign n1564 = 8'h27 >> { pksi_74_, pksi_86_, n1103 }; + assign n1565_1 = 16'ha280 >> { pksi_80_, pksi_72_, n1101_1, n1102 }; + assign n985 = 64'hfafbf2f3f8f9f0f1 >> { pkey_224_, pkey_216_, n1567, n1568, pencrypt_0_, pstart_0_ }; + assign n1567 = 8'h27 >> { pksi_95_, pksi_78_, n1103 }; + assign n1568 = 16'ha280 >> { pksi_81_, pksi_77_, n1101_1, n1102 }; + assign n857_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_170_, pkey_162_, n1570, n1571, pencrypt_0_, pstart_0_ }; + assign n1570 = 8'h27 >> { pksi_49_, n_n2310, n1103 }; + assign n1571 = 16'ha280 >> { pksi_58_, pksi_69_, n1101_1, n1102 }; + assign n1445 = 64'hfafbf2f3f8f9f0f1 >> { pkey_177_, pkey_169_, n1573_1, n1574, pencrypt_0_, pstart_0_ }; + assign n1573_1 = 8'h27 >> { pksi_65_, n_n2320, n1103 }; + assign n1574 = 16'ha280 >> { pksi_62_, pksi_50_, n1101_1, n1102 }; + assign n1745 = 64'hfafbf2f3f8f9f0f1 >> { pkey_123_, pkey_115_, n1576, n1577_1, pencrypt_0_, pstart_0_ }; + assign n1576 = 8'h27 >> { pksi_36_, pksi_27_, n1103 }; + assign n1577_1 = 16'ha280 >> { pksi_44_, pksi_40_, n1101_1, n1102 }; + assign n1205_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_65_, pkey_122_, n1579, n1580, pencrypt_0_, pstart_0_ }; + assign n1579 = 8'h27 >> { pksi_24_, pksi_32_, n1103 }; + assign n1580 = 16'ha280 >> { n_n2342, pksi_25_, n1101_1, n1102 }; + assign n1009 = 64'hfafbf2f3f8f9f0f1 >> { pkey_225_, pkey_217_, n1582, n1583, pencrypt_0_, pstart_0_ }; + assign n1582 = 8'h27 >> { pksi_83_, pksi_74_, n1103 }; + assign n1583 = 16'ha280 >> { pksi_72_, pksi_94_, n1101_1, n1102 }; + assign n981 = 64'hfafbf2f3f8f9f0f1 >> { pkey_248_, pkey_240_, n1585_1, n1586, pencrypt_0_, pstart_0_ }; + assign n1585_1 = 8'h27 >> { pksi_68_, pksi_55_, n1103 }; + assign n1586 = 16'ha280 >> { pksi_78_, pksi_95_, n1101_1, n1102 }; + assign n1750 = 64'hfafbf2f3f8f9f0f1 >> { pkey_146_, pkey_138_, n1588, n1589, pencrypt_0_, pstart_0_ }; + assign n1588 = 8'h27 >> { pksi_69_, pksi_58_, n1103 }; + assign n1589 = 16'ha280 >> { pksi_51_, pksi_60_, n1101_1, n1102 }; + assign n853_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_169_, pkey_161_, n1591, n1592, pencrypt_0_, pstart_0_ }; + assign n1591 = 8'h27 >> { n_n2320, pksi_59_, n1103 }; + assign n1592 = 16'ha280 >> { pksi_70_, pksi_62_, n1101_1, n1102 }; + assign n1201_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_80_, pkey_72_, n1594_1, n1595, pencrypt_0_, pstart_0_ }; + assign n1594_1 = 8'h27 >> { pksi_39_, pksi_29_, n1103 }; + assign n1595 = 16'ha280 >> { pksi_41_, pksi_43_, n1101_1, n1102 }; + assign n1217_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_10_, pkey_2_, n1597, n1598, pencrypt_0_, pstart_0_ }; + assign n1597 = 8'h27 >> { pksi_10_, n_n2369, n1103 }; + assign n1598 = 16'ha280 >> { n_n2365, pksi_3_, n1101_1, n1102 }; + assign n1029_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_233_, pkey_225_, n1600, n1601, pencrypt_0_, pstart_0_ }; + assign n1600 = 8'h27 >> { n_n2288, pksi_83_, n1103 }; + assign n1601 = 16'ha280 >> { pksi_94_, pksi_86_, n1101_1, n1102 }; + assign n901_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_240_, pkey_232_, n1603, n1604_1, pencrypt_0_, pstart_0_ }; + assign n1603 = 8'h27 >> { pksi_55_, pksi_76_, n1103 }; + assign n1604_1 = 16'ha280 >> { pksi_87_, pksi_78_, n1101_1, n1102 }; + assign n1421 = 64'hfafbf2f3f8f9f0f1 >> { pkey_154_, pkey_146_, n1606, n1607, pencrypt_0_, pstart_0_ }; + assign n1606 = 8'h27 >> { pksi_61_, pksi_69_, n1103 }; + assign n1607 = 16'ha280 >> { pksi_60_, n_n2305, n1101_1, n1102 }; + assign n949 = 64'hfafbf2f3f8f9f0f1 >> { pkey_161_, pkey_153_, n1609, n1610, pencrypt_0_, pstart_0_ }; + assign n1609 = 8'h27 >> { pksi_59_, pksi_50_, n1103 }; + assign n1610 = 16'ha280 >> { pksi_48_, pksi_70_, n1101_1, n1102 }; + assign n1329 = 64'hfafbf2f3f8f9f0f1 >> { pkey_88_, pkey_80_, n1612, n1613, pencrypt_0_, pstart_0_ }; + assign n1612 = 8'h27 >> { pksi_30_, pksi_39_, n1103 }; + assign n1613 = 16'ha280 >> { pksi_43_, pksi_33_, n1101_1, n1102 }; + assign n1261 = 64'hfafbf2f3f8f9f0f1 >> { pkey_2_, pkey_59_, n1615, n1616, pencrypt_0_, pstart_0_ }; + assign n1615 = 8'h27 >> { n_n2369, pksi_12_, n1103 }; + assign n1616 = 16'ha280 >> { pksi_16_, n_n2365, n1101_1, n1102 }; + assign n865 = 64'hfafbf2f3f8f9f0f1 >> { pkey_241_, pkey_233_, n1618, n1619, pencrypt_0_, pstart_0_ }; + assign n1618 = 8'h27 >> { pksi_89_, n_n2288, n1103 }; + assign n1619 = 16'ha280 >> { pksi_86_, pksi_74_, n1101_1, n1102 }; + assign n1449 = 64'hfafbf2f3f8f9f0f1 >> { pkey_171_, pkey_163_, n1621, n1622, pencrypt_0_, pstart_0_ }; + assign n1621 = 8'h27 >> { n_n2301, pksi_64_, n1103 }; + assign n1622 = 16'ha280 >> { pksi_76_, pksi_55_, n1101_1, n1102 }; + assign n953 = 64'hfafbf2f3f8f9f0f1 >> { pkey_176_, pkey_168_, n1624, n1625, pencrypt_0_, pstart_0_ }; + assign n1624 = 8'h27 >> { pksi_31_, pksi_52_, n1103 }; + assign n1625 = 16'ha280 >> { pksi_63_, pksi_54_, n1101_1, n1102 }; + assign n1109_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_106_, pkey_98_, n1627, n1628_1, pencrypt_0_, pstart_0_ }; + assign n1627 = 8'h27 >> { pksi_25_, n_n2342, n1103 }; + assign n1628_1 = 16'ha280 >> { pksi_34_, pksi_45_, n1101_1, n1102 }; + assign n1229 = 64'hfafbf2f3f8f9f0f1 >> { pkey_64_, pkey_121_, n1630, n1631, pencrypt_0_, pstart_0_ }; + assign n1630 = 8'h27 >> { pksi_33_, pksi_43_, n1103 }; + assign n1631 = 16'ha280 >> { pksi_35_, n_n2352, n1101_1, n1102 }; + assign n1755_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_59_, pkey_51_, n1633_1, n1634, pencrypt_0_, pstart_0_ }; + assign n1633_1 = 8'h27 >> { pksi_12_, pksi_3_, n1103 }; + assign n1634 = 16'ha280 >> { pksi_20_, pksi_16_, n1101_1, n1102 }; + assign n1760 = 64'hfafbf2f3f8f9f0f1 >> { pkey_18_, pkey_10_, n1636, n1637, pencrypt_0_, pstart_0_ }; + assign n1636 = 8'h27 >> { pksi_21_, pksi_10_, n1103 }; + assign n1637 = 16'ha280 >> { pksi_3_, pksi_12_, n1101_1, n1102 }; + assign n1765 = 64'hfafbf2f3f8f9f0f1 >> { pkey_249_, pkey_241_, n1639, n1640, pencrypt_0_, pstart_0_ }; + assign n1639 = 8'h27 >> { pksi_91_, pksi_89_, n1103 }; + assign n1640 = 16'ha280 >> { pksi_74_, pksi_83_, n1101_1, n1102 }; + assign n997 = 64'hfafbf2f3f8f9f0f1 >> { pkey_163_, pkey_248_, n1642, n1643, pencrypt_0_, pstart_0_ }; + assign n1642 = 8'h27 >> { pksi_64_, pksi_68_, n1103 }; + assign n1643 = 16'ha280 >> { pksi_95_, pksi_76_, n1101_1, n1102 }; + assign n917 = 64'hfafbf2f3f8f9f0f1 >> { pkey_184_, pkey_176_, n1645, n1646, pencrypt_0_, pstart_0_ }; + assign n1645 = 8'h27 >> { pksi_44_, pksi_31_, n1103 }; + assign n1646 = 16'ha280 >> { pksi_54_, pksi_71_, n1101_1, n1102 }; + assign n1133 = 64'hfafbf2f3f8f9f0f1 >> { pkey_98_, pkey_90_, n1648_1, n1649, pencrypt_0_, pstart_0_ }; + assign n1648_1 = 8'h27 >> { n_n2342, pksi_37_, n1103 }; + assign n1649 = 16'ha280 >> { n_n2337, pksi_34_, n1101_1, n1102 }; + assign n1181 = 64'hfafbf2f3f8f9f0f1 >> { pkey_72_, pkey_64_, n1651, n1652, pencrypt_0_, pstart_0_ }; + assign n1651 = 8'h27 >> { pksi_29_, pksi_33_, n1103 }; + assign n1652 = 16'ha280 >> { n_n2352, pksi_41_, n1101_1, n1102 }; + assign n1121_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_51_, pkey_43_, n1654, n1655, pencrypt_0_, pstart_0_ }; + assign n1654 = 8'h27 >> { pksi_3_, n_n2365, n1103 }; + assign n1655 = 16'ha280 >> { pksi_7_, pksi_20_, n1101_1, n1102 }; + assign n1169 = 64'hfafbf2f3f8f9f0f1 >> { pkey_26_, pkey_18_, n1657, n1658_1, pencrypt_0_, pstart_0_ }; + assign n1657 = 8'h27 >> { pksi_13_, pksi_21_, n1103 }; + assign n1658_1 = 16'ha280 >> { pksi_12_, n_n2369, n1101_1, n1102 }; + assign n1770 = 64'hfafbf2f3f8f9f0f1 >> { pkey_178_, pkey_170_, n1660, n1661, pencrypt_0_, pstart_0_ }; + assign n1660 = 8'h27 >> { pksi_66_, pksi_49_, n1103 }; + assign n1661 = 16'ha280 >> { pksi_69_, pksi_61_, n1101_1, n1102 }; + assign n1025_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_136_, pkey_128_, n1663, n1664, pencrypt_0_, pstart_0_ }; + assign n1663 = 8'h27 >> { pksi_53_, pksi_57_, n1103 }; + assign n1664 = 16'ha280 >> { n_n2320, pksi_65_, n1101_1, n1102 }; + assign n1085 = 64'hfafbf2f3f8f9f0f1 >> { pkey_122_, pkey_114_, n1666, n1667, pencrypt_0_, pstart_0_ }; + assign n1666 = 8'h27 >> { pksi_32_, pksi_42_, n1103 }; + assign n1667 = 16'ha280 >> { pksi_37_, n_n2342, n1101_1, n1102 }; + assign n1197 = 64'hfafbf2f3f8f9f0f1 >> { pkey_43_, pkey_35_, n1669, n1670, pencrypt_0_, pstart_0_ }; + assign n1669 = 8'h27 >> { n_n2365, pksi_16_, n1103 }; + assign n1670 = 16'ha280 >> { pksi_28_, pksi_7_, n1101_1, n1102 }; + assign n1173 = 64'hfafbf2f3f8f9f0f1 >> { pkey_34_, pkey_26_, n1672, n1673_1, pencrypt_0_, pstart_0_ }; + assign n1672 = 8'h27 >> { n_n2374, pksi_13_, n1103 }; + assign n1673_1 = 16'ha280 >> { n_n2369, pksi_10_, n1101_1, n1102 }; + assign n1377 = 64'hfafbf2f3f8f9f0f1 >> { pkey_186_, pkey_178_, n1675, n1676, pencrypt_0_, pstart_0_ }; + assign n1675 = 8'h27 >> { pksi_56_, pksi_66_, n1103 }; + assign n1676 = 16'ha280 >> { pksi_61_, n_n2310, n1101_1, n1102 }; + assign n977 = 64'hfafbf2f3f8f9f0f1 >> { pkey_128_, pkey_185_, n1678_1, n1679, pencrypt_0_, pstart_0_ }; + assign n1678_1 = 8'h27 >> { pksi_57_, pksi_67_, n1103 }; + assign n1679 = 16'ha280 >> { pksi_59_, n_n2320, n1101_1, n1102 }; + assign n1157 = 64'hfafbf2f3f8f9f0f1 >> { pkey_107_, pkey_99_, n1681, n1682_1, pencrypt_0_, pstart_0_ }; + assign n1681 = 8'h27 >> { n_n2333, pksi_40_, n1103 }; + assign n1682_1 = 16'ha280 >> { pksi_52_, pksi_31_, n1101_1, n1102 }; + assign n1775 = 64'hfafbf2f3f8f9f0f1 >> { pkey_114_, pkey_106_, n1684, n1685, pencrypt_0_, pstart_0_ }; + assign n1684 = 8'h27 >> { pksi_42_, pksi_25_, n1103 }; + assign n1685 = 16'ha280 >> { pksi_45_, pksi_37_, n1101_1, n1102 }; + assign n1780 = 64'hfafbf2f3f8f9f0f1 >> { pkey_121_, pkey_113_, n1687, n1688, pencrypt_0_, pstart_0_ }; + assign n1687 = 8'h27 >> { pksi_43_, pksi_41_, n1103 }; + assign n1688 = 16'ha280 >> { pksi_26_, pksi_35_, n1101_1, n1102 }; + assign n1517 = 64'hfafbf2f3f8f9f0f1 >> { pkey_35_, pkey_120_, n1690, n1691, pencrypt_0_, pstart_0_ }; + assign n1690 = 8'h27 >> { pksi_16_, pksi_20_, n1103 }; + assign n1691 = 16'ha280 >> { pksi_47_, pksi_28_, n1101_1, n1102 }; + assign n1237 = 64'hfafbf2f3f8f9f0f1 >> { pkey_42_, pkey_34_, n1693, n1694, pencrypt_0_, pstart_0_ }; + assign n1693 = 8'h27 >> { pksi_1_, n_n2374, n1103 }; + assign n1694 = 16'ha280 >> { pksi_10_, pksi_21_, n1101_1, n1102 }; + assign pnew_count_0_ = 8'h27 >> { pcount_0_, pencrypt_0_, pstart_0_ }; + assign pdata_ready_0_ = 64'h0000000080000001 >> { pstart_0_, pencrypt_0_, pcount_0_, pcount_3_, pcount_2_, pcount_1_ }; + assign pnew_count_3_ = 64'h06fc0cfc0cfc0cf9 >> { pcount_0_, pcount_2_, pencrypt_0_, pstart_0_, pcount_3_, pcount_1_ }; + assign pnew_count_2_ = 32'd1431661769 >> { pstart_0_, pcount_0_, pcount_1_, pcount_2_, pencrypt_0_ }; + assign pnew_count_1_ = 16'h5569 >> { pstart_0_, pcount_0_, pcount_1_, pencrypt_0_ }; + assign n1145 = 64'hfafbf2f3f8f9f0f1 >> { pkey_0_, pkey_57_, n1701, n1702, pencrypt_0_, pstart_0_ }; + assign n1701 = 8'h27 >> { pksi_9_, pksi_19_, n1103 }; + assign n1702 = 16'ha280 >> { pksi_11_, n_n2384, n1101_1, n1102 }; + assign n1369 = 64'hfafbf2f3f8f9f0f1 >> { pkey_219_, pkey_211_, n1704, n1705, pencrypt_0_, pstart_0_ }; + assign n1704 = 8'h27 >> { pksi_176_, pksi_169_, n1103 }; + assign n1705 = 16'ha280 >> { pksi_173_, n_n2396, n1101_1, n1102 }; + assign n1589_1 = 64'hfafbf2f3f8f9f0f1 >> { pkey_213_, pkey_205_, n1707, n1708, pencrypt_0_, pstart_0_ }; + assign n1707 = 8'h27 >> { pksi_175_, n_n2412, n1103 }; + assign n1708 = 16'ha280 >> { pksi_180_, n_n2408, n1101_1, n1102 }; + assign n1461 = 64'hfafbf2f3f8f9f0f1 >> { pkey_238_, pkey_230_, n1710, n1711_1, pencrypt_0_, pstart_0_ }; + assign n1710 = 8'h27 >> { pksi_190_, pksi_174_, n1103 }; + assign n1711_1 = 16'ha280 >> { pksi_178_, pksi_187_, n1101_1, n1102 }; + assign n1529 = 64'hfafbf2f3f8f9f0f1 >> { pkey_164_, pkey_156_, n1713, n1714, pencrypt_0_, pstart_0_ }; + assign n1713 = 8'h27 >> { pksi_162_, pksi_148_, n1103 }; + assign n1714 = 16'ha280 >> { pksi_164_, pksi_157_, n1101_1, n1102 }; + assign n1715_1 = 64'hee66ae26ea62aa22 >> { pksi_158_, n_n2448, pkey_181_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1577 = 64'hbb99ba98ab89aa88 >> { pksi_165_, n_n2452, pkey_189_, n1103, pencrypt_0_, n1715_1 }; + assign n1717 = 64'hee66ea62ae26aa22 >> { pksi_116_, pksi_104_, pkey_20_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1117_1 = 64'hbb99ba98ab89aa88 >> { pksi_107_, pksi_100_, pkey_28_, n1103, pencrypt_0_, n1717 }; + assign n1719 = 64'hee66ea62ae26aa22 >> { pksi_110_, pksi_103_, pkey_45_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1594 = 64'hbb99ba98ab89aa88 >> { pksi_99_, pksi_117_, pkey_53_, n1103, pencrypt_0_, n1719 }; + assign n1721 = 64'hee66ae26ea62aa22 >> { n_n2384, pksi_17_, pkey_0_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1345 = 64'hbb99ba98ab89aa88 >> { pksi_9_, pksi_5_, pkey_8_, n1103, pencrypt_0_, n1721 }; + assign n1723 = 64'hee66ea62ae26aa22 >> { pksi_173_, pksi_183_, pkey_203_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1599 = 64'hbb99ab89ba98aa88 >> { pksi_169_, pksi_185_, pkey_211_, n1103, pencrypt_0_, n1723 }; + assign n1725_1 = 64'hee66ae26ea62aa22 >> { n_n2408, n_n2410, pkey_213_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1604 = 64'hbb99ba98ab89aa88 >> { pksi_175_, pksi_182_, pkey_221_, n1103, pencrypt_0_, n1725_1 }; + assign n1727 = 64'hee66ea62ae26aa22 >> { pksi_178_, pksi_184_, pkey_222_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1609_1 = 64'hbb99ab89ba98aa88 >> { pksi_174_, pksi_170_, pkey_230_, n1103, pencrypt_0_, n1727 }; + assign n1729 = 64'hee66ae26ea62aa22 >> { pksi_157_, pksi_155_, pkey_164_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1561 = 64'hbb99ba98ab89aa88 >> { pksi_162_, n_n2440, pkey_172_, n1103, pencrypt_0_, n1729 }; + assign n1731 = 64'hee66ae26ea62aa22 >> { pksi_109_, pksi_107_, pkey_36_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n937 = 64'hbb99ab89ba98aa88 >> { pksi_105_, pksi_114_, pkey_44_, n1103, pencrypt_0_, n1731 }; + assign n1733 = 64'hee66ae26ea62aa22 >> { pksi_131_, pksi_124_, pkey_44_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1545 = 64'hbb99ba98ab89aa88 >> { pksi_129_, pksi_132_, pkey_116_, n1103, pencrypt_0_, n1733 }; + assign n1735 = 64'hee66ae26ea62aa22 >> { pksi_107_, pksi_100_, pkey_44_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n965 = 64'hbb99ab89ba98aa88 >> { pksi_108_, pksi_105_, pkey_52_, n1103, pencrypt_0_, n1735 }; + assign n1737 = 64'hee66ea62ae26aa22 >> { pksi_172_, pksi_179_, pkey_172_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1341 = 64'hbb99ab89ba98aa88 >> { pksi_180_, pksi_177_, pkey_244_, n1103, pencrypt_0_, n1737 }; + assign n1739 = 64'hee66ea62ae26aa22 >> { pksi_179_, pksi_168_, pkey_228_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1513 = 64'hbb99ab89ba98aa88 >> { pksi_177_, pksi_186_, pkey_172_, n1103, pencrypt_0_, n1739 }; + assign n1741 = 64'hee66ae26ea62aa22 >> { n_n2476, pksi_120_, pkey_93_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n913 = 64'hbb99ba98ab89aa88 >> { pksi_134_, n_n2481, pkey_101_, n1103, pencrypt_0_, n1741 }; + assign n1743 = 64'hee66ea62ae26aa22 >> { pksi_126_, pksi_122_, pkey_118_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1333 = 64'hbb99ba98ab89aa88 >> { pksi_111_, pksi_101_, pkey_126_, n1103, pencrypt_0_, n1743 }; + assign n1745_1 = 64'hee66ea62ae26aa22 >> { pksi_148_, pksi_155_, pkey_172_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1569 = 64'hbb99ab89ba98aa88 >> { pksi_156_, n_n2440, pkey_180_, n1103, pencrypt_0_, n1745_1 }; + assign n1747 = 64'hee66ea62ae26aa22 >> { pksi_156_, n_n2440, pkey_133_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1565 = 64'hbb99ba98ab89aa88 >> { pksi_163_, pksi_144_, pkey_141_, n1103, pencrypt_0_, n1747 }; + assign n1749 = 64'hee66ae26ea62aa22 >> { pksi_133_, pksi_131_, pkey_100_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n993 = 64'hbb99ab89ba98aa88 >> { pksi_129_, pksi_138_, pkey_44_, n1103, pencrypt_0_, n1749 }; + assign n1751 = 64'hee66ae26ea62aa22 >> { pksi_132_, n_n2474, pkey_77_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1701_1 = 64'hbb99ab89ba98aa88 >> { pksi_127_, pksi_120_, pkey_85_, n1103, pencrypt_0_, n1751 }; + assign n1753 = 64'hee66ea62ae26aa22 >> { n_n2476, n_n2474, pkey_85_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1097 = 64'hbb99ba98ab89aa88 >> { pksi_127_, pksi_134_, pkey_93_, n1103, pencrypt_0_, n1753 }; + assign n1755 = 64'hee66ea62ae26aa22 >> { pksi_52_, pksi_71_, pkey_184_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1245 = 64'hbb99ba98ab89aa88 >> { pksi_44_, pksi_40_, pkey_99_, n1103, pencrypt_0_, n1755 }; + assign n1757 = 64'hee66ae26ea62aa22 >> { pksi_38_, pksi_26_, pkey_105_, n1101_1, pencrypt_0_, pstart_0_ }; + assign n1153 = 64'hbb99ab89ba98aa88 >> { pksi_41_, n_n2352, pkey_113_, n1103, pencrypt_0_, n1757 }; + assign pksi_90_ = pksi_88_; + assign pksi_191_ = pksi_187_; + assign pksi_181_ = pksi_168_; + assign pksi_143_ = pksi_139_; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act b/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act new file mode 100644 index 000000000..7064c2d66 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act @@ -0,0 +1,3040 @@ +clock 0.505600 0.511600 +tin_psv39_8_8_ 0.494800 0.495000 +tin_psv39_0_0_ 0.493000 0.507600 +tin_psv13_5_5_ 0.513200 0.499800 +tin_psv2_13_13_ 0.497800 0.497200 +tin_psv2_8_8_ 0.495400 0.489400 +pinp_2_2_ 0.500200 0.501200 +tin_psv38_2_2_ 0.508800 0.513400 +tin_psv33_5_5_ 0.502400 0.498000 +tin_psv26_6_6_ 0.494000 0.508800 +tin_psv2_9_9_ 0.501000 0.506800 +pinp_3_3_ 0.495400 0.505800 +tin_psv18_2_2_ 0.506200 0.498800 +tin_psv39_9_9_ 0.497600 0.503200 +tin_psv39_1_1_ 0.507600 0.501400 +tin_psv13_6_6_ 0.478200 0.501400 +tin_psv2_6_6_ 0.504000 0.505200 +pinp_0_0_ 0.483800 0.493800 +tin_psv38_3_3_ 0.493800 0.499600 +tin_psv33_6_6_ 0.483200 0.489200 +tin_psv26_13_13_ 0.485600 0.502000 +tin_psv26_12_12_ 0.498000 0.481800 +tin_psv26_7_7_ 0.511600 0.505200 +tin_psv2_7_7_ 0.503000 0.499000 +pinp_1_1_ 0.491400 0.497200 +preset_0_0_ 0.498800 0.498600 +tin_psv18_3_3_ 0.502000 0.504000 +tin_psv39_2_2_ 0.516600 0.499000 +tin_psv33_12_12_ 0.504600 0.508400 +tin_psv33_11_11_ 0.488600 0.496800 +tin_psv33_10_10_ 0.504800 0.503200 +tin_psv13_7_7_ 0.507200 0.487800 +tin_psv2_10_10_ 0.494000 0.503600 +tin_psv38_4_4_ 0.497200 0.498800 +tin_psv39_10_10_ 0.502200 0.499200 +tin_psv33_7_7_ 0.498600 0.495400 +tin_psv26_15_15_ 0.473800 0.500400 +tin_psv26_14_14_ 0.487600 0.500600 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0.238600 0.001340 +n5876 0.000000 0.008679 +n5881 0.000000 0.000000 +n5886 0.000000 0.000000 +n5891 0.000000 0.009556 +n5896 0.000000 0.000000 +n5901 0.000000 0.021954 +n5906 0.000000 0.000000 +n5911 0.000000 0.255926 +n5916 0.000000 0.000000 +n5921 0.000000 0.007738 +n5926 0.125800 0.050924 +n5931 0.000000 0.021954 +n5936 0.000000 0.000000 +n5941 0.000000 0.255926 +n5946 0.000000 0.255926 +n5951 0.135200 0.050606 +n5956 0.000000 0.021954 +n5966 0.000000 0.009974 +n5971 0.000000 0.021954 +n5976 0.000000 0.255926 +n5981 0.000000 0.255926 +n5986 0.000000 0.015019 +n5991 0.000000 0.021954 +n5996 0.000000 0.255911 +n6001 0.000000 0.006978 +n6006 0.000000 0.021954 +n6011 0.005400 0.007557 +n6016 0.000000 0.021954 +n6021 0.000000 0.000000 +n6026 0.000000 0.021954 +n6031 0.000000 0.000000 +n6036 0.000000 0.255926 +n6041 0.000000 0.021954 +n6046 0.127800 0.049978 +n6051 0.000000 0.008854 +n6056 0.000000 0.008959 +n6061 0.000000 0.000000 +n6066 0.000000 0.008248 +n6071 0.000000 0.009556 +n6076 0.000000 0.008956 +n6081 0.000000 0.000000 +n6086 0.000000 0.000000 +n6091 0.000000 0.008248 +n6096 0.000000 0.009094 diff --git a/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif b/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif new file mode 100644 index 000000000..3fb6c5f8e --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif @@ -0,0 +1,7378 @@ +# Benchmark "elliptic" written by ABC on Tue Mar 12 09:26:11 2019 +.model elliptic +.inputs clock tin_psv39_8_8_ tin_psv39_0_0_ tin_psv13_5_5_ tin_psv2_13_13_ \ + tin_psv2_8_8_ pinp_2_2_ tin_psv38_2_2_ tin_psv33_5_5_ tin_psv26_6_6_ \ + tin_psv2_9_9_ pinp_3_3_ tin_psv18_2_2_ tin_psv39_9_9_ tin_psv39_1_1_ \ + tin_psv13_6_6_ tin_psv2_6_6_ pinp_0_0_ tin_psv38_3_3_ tin_psv33_6_6_ \ + tin_psv26_13_13_ tin_psv26_12_12_ tin_psv26_7_7_ tin_psv2_7_7_ pinp_1_1_ \ + preset_0_0_ tin_psv18_3_3_ tin_psv39_2_2_ tin_psv33_12_12_ \ + tin_psv33_11_11_ tin_psv33_10_10_ tin_psv13_7_7_ tin_psv2_10_10_ \ + tin_psv38_4_4_ tin_psv39_10_10_ tin_psv33_7_7_ tin_psv26_15_15_ \ + tin_psv26_14_14_ tin_psv26_8_8_ tin_psv26_0_0_ tin_psv13_12_12_ \ + tin_psv13_11_11_ tin_psv18_4_4_ tin_psv39_3_3_ tin_psv13_8_8_ \ + tin_psv13_0_0_ pinp_15_15_ pinp_12_12_ tin_psv38_5_5_ tin_psv33_8_8_ \ + tin_psv33_0_0_ tin_psv26_9_9_ tin_psv26_1_1_ tin_psv13_10_10_ \ + tin_psv18_5_5_ tin_psv39_4_4_ tin_psv13_9_9_ tin_psv13_1_1_ \ + tin_psv2_15_15_ tin_psv2_11_11_ tin_psv2_0_0_ tin_psv38_14_14_ \ + tin_psv38_12_12_ tin_psv38_10_10_ tin_psv38_6_6_ tin_psv18_15_15_ \ + tin_psv18_13_13_ tin_psv18_11_11_ tin_psv33_9_9_ tin_psv33_1_1_ \ + tin_psv26_2_2_ tin_psv2_1_1_ pclk tin_psv38_15_15_ tin_psv38_11_11_ \ + tin_psv18_12_12_ tin_psv18_6_6_ tin_psv39_5_5_ tin_psv13_2_2_ pinp_14_14_ \ + pinp_11_11_ pinp_8_8_ tin_psv38_7_7_ tin_psv39_12_12_ tin_psv39_11_11_ \ + tin_psv33_2_2_ tin_psv26_3_3_ tin_psv13_14_14_ tin_psv13_13_13_ pinp_9_9_ \ + tin_psv18_10_10_ tin_psv18_7_7_ tin_psv39_6_6_ tin_psv33_15_15_ \ + tin_psv33_14_14_ tin_psv33_13_13_ tin_psv13_3_3_ tin_psv2_14_14_ \ + tin_psv2_12_12_ tin_psv2_4_4_ pinp_6_6_ tin_psv38_8_8_ tin_psv38_0_0_ \ + tin_psv39_14_14_ tin_psv39_13_13_ tin_psv33_3_3_ tin_psv26_11_11_ \ + tin_psv26_10_10_ tin_psv26_4_4_ tin_psv13_15_15_ tin_psv2_5_5_ pinp_7_7_ \ + tin_psv18_8_8_ tin_psv18_0_0_ tin_psv39_7_7_ tin_psv13_4_4_ tin_psv2_2_2_ \ + pinp_13_13_ pinp_10_10_ pinp_4_4_ tin_psv38_9_9_ tin_psv38_1_1_ preset \ + tin_psv39_15_15_ tin_psv33_4_4_ tin_psv26_5_5_ tin_psv2_3_3_ pinp_5_5_ \ + tin_psv38_13_13_ tin_psv18_14_14_ tin_psv18_9_9_ tin_psv18_1_1_ +.outputs psv39_8_8_ psv39_0_0_ psv13_5_5_ psv2_13_13_ psv2_8_8_ psv38_2_2_ \ + psv33_5_5_ psv26_6_6_ psv2_9_9_ psv18_2_2_ psv39_9_9_ psv39_1_1_ \ + psv13_6_6_ psv2_6_6_ psv38_3_3_ psv33_6_6_ psv26_13_13_ psv26_12_12_ \ + psv26_7_7_ psv2_7_7_ psv18_3_3_ psv39_2_2_ psv33_12_12_ psv33_11_11_ \ + psv33_10_10_ psv13_7_7_ psv2_10_10_ psv38_4_4_ psv39_10_10_ psv33_7_7_ \ + psv26_15_15_ psv26_14_14_ psv26_8_8_ psv26_0_0_ psv13_12_12_ psv13_11_11_ \ + psv18_4_4_ psv39_3_3_ psv13_8_8_ psv13_0_0_ psv38_5_5_ psv33_8_8_ \ + psv33_0_0_ psv26_9_9_ psv26_1_1_ psv13_10_10_ psv18_5_5_ psv39_4_4_ \ + psv13_9_9_ psv13_1_1_ psv2_15_15_ psv2_11_11_ psv2_0_0_ psv38_14_14_ \ + psv38_12_12_ psv38_10_10_ psv38_6_6_ psv18_15_15_ psv18_13_13_ \ + psv18_11_11_ psv33_9_9_ psv33_1_1_ psv26_2_2_ psv2_1_1_ psv38_15_15_ \ + psv38_11_11_ psv18_12_12_ psv18_6_6_ psv39_5_5_ psv13_2_2_ pover_0_0_ \ + psv38_7_7_ psv39_12_12_ psv39_11_11_ psv33_2_2_ psv26_3_3_ psv13_14_14_ \ + psv13_13_13_ psv18_10_10_ psv18_7_7_ psv39_6_6_ psv33_15_15_ psv33_14_14_ \ + psv33_13_13_ psv13_3_3_ psv2_14_14_ psv2_12_12_ psv2_4_4_ psv38_8_8_ \ + psv38_0_0_ pdn psv39_14_14_ psv39_13_13_ psv33_3_3_ psv26_11_11_ \ + psv26_10_10_ psv26_4_4_ psv13_15_15_ psv2_5_5_ psv18_8_8_ psv18_0_0_ \ + psv39_7_7_ psv13_4_4_ psv2_2_2_ psv38_9_9_ psv38_1_1_ psv39_15_15_ \ + psv33_4_4_ psv26_5_5_ psv2_3_3_ psv38_13_13_ psv18_14_14_ psv18_9_9_ \ + psv18_1_1_ + +.latch n493 pdn re clock 0 +.latch n497 pover_0_0_ re clock 0 +.latch n501_1 n_n9280 re clock 0 +.latch n506_1 n_n9172 re clock 0 +.latch n511_1 n_n9260 re clock 0 +.latch n516_1 n_n7726 re clock 0 +.latch n521_1 n_n8270 re clock 0 +.latch n526_1 n_n8196 re clock 0 +.latch n531_1 n_n9150 re clock 0 +.latch n536_1 n_n9267 re clock 0 +.latch n541_1 n_n7779 re clock 0 +.latch n546_1 n_n9503 re clock 0 +.latch n551_1 n_n8150 re clock 0 +.latch n556_1 n_n9401 re clock 0 +.latch n561_1 n_n7341 re clock 0 +.latch n566_1 n_n9180 re clock 0 +.latch n571_1 n_n8592 re clock 0 +.latch n576_1 n_n8871 re clock 0 +.latch n581_1 n_n7252 re clock 0 +.latch n586_1 n_n7271 re clock 0 +.latch n591_1 n_n6991 re clock 0 +.latch n596_1 n_n8557 re clock 0 +.latch n601_1 n_n7707 re clock 0 +.latch n606_1 n_n7552 re clock 0 +.latch n611_1 ndn3_23 re clock 0 +.latch n616_1 n_n9548 re clock 0 +.latch n621_1 n_n9467 re clock 0 +.latch n626_1 n_n8002 re clock 0 +.latch n631_1 n_n6950 re clock 0 +.latch n636_1 n_n8930 re clock 0 +.latch n641_1 n_n7244 re clock 0 +.latch n646_1 n_n7819 re clock 0 +.latch n651_1 n_n8883 re clock 0 +.latch n656_1 n_n7709 re clock 0 +.latch n661_1 n_n9580 re clock 0 +.latch n666_1 n_n9130 re clock 0 +.latch n671_1 n_n9486 re clock 0 +.latch n676_1 n_n9235 re clock 0 +.latch n681_1 n_n7522 re clock 0 +.latch n686_1 n_n7373 re clock 0 +.latch n691_1 n_n9085 re clock 0 +.latch n696_1 n_n9638 re clock 0 +.latch n701_1 n_n7452 re clock 0 +.latch n706_1 n_n8775 re clock 0 +.latch n711_1 n_n7654 re clock 0 +.latch n716_1 n_n8410 re clock 0 +.latch n721_1 n_n8208 re clock 0 +.latch n726_1 n_n8377 re clock 0 +.latch n731_1 n_n7558 re clock 0 +.latch n736_1 n_n7599 re clock 0 +.latch n741_1 n_n8225 re clock 0 +.latch n746_1 n_n8202 re clock 0 +.latch n751_1 n_n7670 re clock 0 +.latch n756_1 n_n7888 re clock 0 +.latch n761_1 n_n7889 re clock 0 +.latch n766_1 n_n8597 re clock 0 +.latch n771_1 n_n8152 re clock 0 +.latch n776_1 n_n8394 re clock 0 +.latch n781_1 n_n7812 re clock 0 +.latch n786_1 n_n7816 re clock 0 +.latch n791_1 n_n9141 re clock 0 +.latch n796_1 n_n7332 re clock 0 +.latch n801_1 n_n8758 re clock 0 +.latch n806_1 n_n7765 re clock 0 +.latch n811_1 n_n7877 re clock 0 +.latch n816_1 n_n7814 re clock 0 +.latch n821_1 n_n9008 re clock 0 +.latch n826_1 n_n7581 re clock 0 +.latch n831_1 n_n7376 re clock 0 +.latch n836 n_n7970 re clock 0 +.latch n841 n_n8599 re clock 0 +.latch n846 n_n8227 re clock 0 +.latch n851 n_n9442 re clock 0 +.latch n856 n_n9485 re clock 0 +.latch n861 n_n7148 re clock 0 +.latch n866 n_n9311 re clock 0 +.latch n871 n_n9273 re clock 0 +.latch n876 ndn3_9 re clock 0 +.latch n881 n_n8613 re clock 0 +.latch n886 n_n8533 re clock 0 +.latch n891 n_n8699 re clock 0 +.latch n896 n_n8609 re clock 0 +.latch n901 n_n8308 re clock 0 +.latch n906 n_n8655 re clock 0 +.latch n911 n_n8981 re clock 0 +.latch n916 n_n7583 re clock 0 +.latch n921 n_n9198 re clock 0 +.latch n926 n_n9602 re clock 0 +.latch n931 n_n8786 re clock 0 +.latch n936 n_n9598 re clock 0 +.latch n941 n_n7738 re clock 0 +.latch n946 n_n8573 re clock 0 +.latch n951 n_n9473 re clock 0 +.latch n956 n_n9000 re clock 0 +.latch n961 n_n8001 re clock 0 +.latch n966 n_n9554 re clock 0 +.latch n971 n_n8508 re clock 0 +.latch n976 n_n9635 re clock 0 +.latch n981 n_n7190 re clock 0 +.latch n986 n_n8702 re clock 0 +.latch n991 n_n9106 re clock 0 +.latch n996 n_n7409 re clock 0 +.latch n1001 n_n9437 re clock 0 +.latch n1006 n_n9052 re clock 0 +.latch n1011 n_n8647 re clock 0 +.latch n1016 n_n9265 re clock 0 +.latch n1021 n_n7179 re clock 0 +.latch n1026 ndn3_13 re clock 0 +.latch n1031 ndn3_17 re clock 0 +.latch n1036 ndn3_25 re clock 0 +.latch n1041 ndn3_29 re clock 0 +.latch n1046 n_n9539 re clock 0 +.latch n1051 n_n7953 re clock 0 +.latch n1056 n_n8488 re clock 0 +.latch n1061 nen3_22 re clock 0 +.latch n1066 n_n9438 re clock 0 +.latch n1071 n_n8132 re clock 0 +.latch n1076 n_n8661 re clock 0 +.latch n1081 n_n7759 re clock 0 +.latch n1086 n_n8333 re clock 0 +.latch n1091 n_n9399 re clock 0 +.latch n1096 n_n7798 re clock 0 +.latch n1101 n_n9434 re clock 0 +.latch n1106 n_n7910 re clock 0 +.latch n1111 n_n9528 re clock 0 +.latch n1116 n_n7850 re clock 0 +.latch n1121 n_n8251 re clock 0 +.latch n1126 n_n7937 re clock 0 +.latch n1131 n_n8482 re clock 0 +.latch n1136 n_n9290 re clock 0 +.latch n1141 n_n8007 re clock 0 +.latch n1146 n_n7556 re clock 0 +.latch n1151 n_n9064 re clock 0 +.latch n1156 n_n9398 re clock 0 +.latch n1161 n_n9412 re clock 0 +.latch n1166 n_n9361 re clock 0 +.latch n1171 n_n9304 re clock 0 +.latch n1176 n_n7651 re clock 0 +.latch n1181 n_n7712 re clock 0 +.latch n1186 n_n7735 re clock 0 +.latch n1191 n_n7934 re clock 0 +.latch n1196 n_n7811 re clock 0 +.latch n1201 n_n8053 re clock 0 +.latch n1206 n_n9015 re clock 0 +.latch n1211 n_n8066 re clock 0 +.latch n1216 n_n9518 re clock 0 +.latch n1221 n_n8091 re clock 0 +.latch n1226 n_n9257 re clock 0 +.latch n1231 n_n8175 re clock 0 +.latch n1236 n_n8491 re clock 0 +.latch n1241 n_n8114 re clock 0 +.latch n1246 n_n7951 re clock 0 +.latch n1251 n_n8913 re clock 0 +.latch n1256 n_n8035 re clock 0 +.latch n1261 n_n8631 re clock 0 +.latch n1266 n_n8243 re clock 0 +.latch n1271 n_n7857 re clock 0 +.latch n1276 ngfdn_3 re clock 0 +.latch n1281 n_n7791 re clock 0 +.latch n1286 n_n9175 re clock 0 +.latch n1291 n_n9588 re clock 0 +.latch n1296 n_n9049 re clock 0 +.latch n1301 n_n9483 re clock 0 +.latch n1306 n_n9410 re clock 0 +.latch n1311 n_n7691 re clock 0 +.latch n1316 n_n7740 re clock 0 +.latch n1321 n_n7602 re clock 0 +.latch n1326 n_n7783 re clock 0 +.latch n1331 n_n7948 re clock 0 +.latch n1336 n_n7054 re clock 0 +.latch n1341 n_n9343 re clock 0 +.latch n1346 n_n9400 re clock 0 +.latch n1351 nsr1_2 re clock 0 +.latch n1356 n_n9127 re clock 0 +.latch n1361 n_n8531 re clock 0 +.latch n1366 n_n9335 re clock 0 +.latch n1371 n_n7324 re clock 0 +.latch n1376 n_n9611 re clock 0 +.latch n1381 n_n8112 re clock 0 +.latch n1386 n_n9406 re clock 0 +.latch n1391 n_n9618 re clock 0 +.latch n1396 n_n9613 re clock 0 +.latch n1401 n_n9242 re clock 0 +.latch n1406 n_n7384 re clock 0 +.latch n1411 n_n8884 re clock 0 +.latch n1416 n_n7462 re clock 0 +.latch n1421 n_n7908 re clock 0 +.latch n1426 n_n8765 re clock 0 +.latch n1431 n_n7909 re clock 0 +.latch n1436 n_n7898 re clock 0 +.latch n1441 n_n9135 re clock 0 +.latch n1446 n_n8862 re clock 0 +.latch n1451 n_n8037 re clock 0 +.latch n1456 ndn3_18 re clock 0 +.latch n1461 ndn3_22 re clock 0 +.latch n1466 n_n8974 re clock 0 +.latch n1471 n_n7286 re clock 0 +.latch n1476 n_n9223 re clock 0 +.latch n1481 n_n7306 re clock 0 +.latch n1486 n_n9169 re clock 0 +.latch n1491 n_n9125 re clock 0 +.latch n1496 nen3_39 re clock 0 +.latch n1501 n_n8278 re clock 0 +.latch n1506 n_n9557 re clock 0 +.latch n1511 n_n7758 re clock 0 +.latch n1516 n_n9391 re clock 0 +.latch n1521 n_n8110 re clock 0 +.latch n1526 n_n9597 re clock 0 +.latch n1531 n_n8568 re clock 0 +.latch n1536 n_n7428 re clock 0 +.latch n1541 n_n7931 re clock 0 +.latch n1546 n_n7742 re clock 0 +.latch n1551 n_n7236 re clock 0 +.latch n1556 n_n8219 re clock 0 +.latch n1561 n_n9568 re clock 0 +.latch n1566 n_n9200 re clock 0 +.latch n1571 n_n8545 re clock 0 +.latch n1576 n_n7823 re clock 0 +.latch n1581 n_n8005 re clock 0 +.latch n1586 n_n8736 re clock 0 +.latch n1591 n_n9339 re clock 0 +.latch n1596 n_n8499 re clock 0 +.latch n1601 n_n8086 re clock 0 +.latch n1606 n_n7803 re clock 0 +.latch n1611 n_n7640 re clock 0 +.latch n1616 n_n9098 re clock 0 +.latch n1621 n_n7160 re clock 0 +.latch n1626 n_n7713 re clock 0 +.latch n1631 n_n9566 re clock 0 +.latch n1636 n_n7955 re clock 0 +.latch n1641 n_n8414 re clock 0 +.latch n1646 n_n8006 re clock 0 +.latch n1651 n_n9560 re clock 0 +.latch n1656 n_n8742 re clock 0 +.latch n1661 n_n7174 re clock 0 +.latch n1666 n_n8882 re clock 0 +.latch n1671 n_n7546 re clock 0 +.latch n1676 n_n8282 re clock 0 +.latch n1681 n_n8998 re clock 0 +.latch n1686 n_n7656 re clock 0 +.latch n1691 n_n9465 re clock 0 +.latch n1696 n_n9601 re clock 0 +.latch n1701 n_n8875 re clock 0 +.latch n1706 n_n7954 re clock 0 +.latch n1711 n_n8959 re clock 0 +.latch n1716 n_n8957 re clock 0 +.latch n1721 n_n8247 re clock 0 +.latch n1726 n_n8258 re clock 0 +.latch n1731 n_n7641 re clock 0 +.latch n1736 n_n8843 re clock 0 +.latch n1741 n_n9321 re clock 0 +.latch n1746 n_n7702 re clock 0 +.latch n1751 nsr3_23 re clock 0 +.latch n1756 n_n8199 re clock 0 +.latch n1761 n_n7983 re clock 0 +.latch n1766 n_n7217 re clock 0 +.latch n1771 n_n7821 re clock 0 +.latch n1776 n_n9489 re clock 0 +.latch n1781 n_n8348 re clock 0 +.latch n1786 n_n9408 re clock 0 +.latch n1791 n_n8445 re clock 0 +.latch n1796 n_n9501 re clock 0 +.latch n1801 n_n7831 re clock 0 +.latch n1806 n_n7757 re clock 0 +.latch n1811 n_n9174 re clock 0 +.latch n1816 n_n9432 re clock 0 +.latch n1821 n_n8678 re clock 0 +.latch n1826 n_n8024 re clock 0 +.latch n1831 n_n7806 re clock 0 +.latch n1836 n_n8996 re clock 0 +.latch n1841 n_n7918 re clock 0 +.latch n1846 n_n8260 re clock 0 +.latch n1851 n_n9341 re clock 0 +.latch n1856 n_n9189 re clock 0 +.latch n1861 n_n9096 re clock 0 +.latch n1866 ndn3_30 re clock 0 +.latch n1871 n_n7775 re clock 0 +.latch n1876 n_n7693 re clock 0 +.latch n1881 nen3_16 re clock 0 +.latch n1886 n_n7643 re clock 0 +.latch n1891 n_n8941 re clock 0 +.latch n1896 n_n8042 re clock 0 +.latch n1901 n_n8681 re clock 0 +.latch n1906 n_n8659 re clock 0 +.latch n1911 n_n9110 re clock 0 +.latch n1916 n_n9573 re clock 0 +.latch n1921 n_n8951 re clock 0 +.latch n1926 n_n9589 re clock 0 +.latch n1931 n_n9387 re clock 0 +.latch n1936 n_n8279 re clock 0 +.latch n1941 n_n7790 re clock 0 +.latch n1946 n_n8406 re clock 0 +.latch n1951 n_n8582 re clock 0 +.latch n1956 n_n7911 re clock 0 +.latch n1961 n_n7474 re clock 0 +.latch n1966 n_n8466 re clock 0 +.latch n1971 n_n6984 re clock 0 +.latch n1976 n_n7760 re clock 0 +.latch n1981 n_n7847 re clock 0 +.latch n1986 n_n9559 re clock 0 +.latch n1991 n_n7362 re clock 0 +.latch n1996 n_n9300 re clock 0 +.latch n2001 n_n9550 re clock 0 +.latch n2006 n_n9492 re clock 0 +.latch n2011 n_n8777 re clock 0 +.latch n2016 n_n7764 re clock 0 +.latch n2021 n_n7826 re clock 0 +.latch n2026 n_n7777 re clock 0 +.latch n2031 n_n7824 re clock 0 +.latch n2036 n_n8173 re clock 0 +.latch n2041 n_n7498 re clock 0 +.latch n2046 n_n9148 re clock 0 +.latch n2051 n_n8753 re clock 0 +.latch n2056 n_n8772 re clock 0 +.latch n2061 n_n8049 re clock 0 +.latch n2066 n_n9362 re clock 0 +.latch n2071 ndn1_4 re clock 0 +.latch n2076 n_n9561 re clock 0 +.latch n2081 n_n9004 re clock 0 +.latch n2086 n_n8203 re clock 0 +.latch n2091 n_n8153 re clock 0 +.latch n2096 n_n9263 re clock 0 +.latch n2101 n_n8369 re clock 0 +.latch n2106 n_n9331 re clock 0 +.latch n2111 n_n7454 re clock 0 +.latch n2116 ndn3_7 re clock 0 +.latch n2121 n_n7527 re clock 0 +.latch n2126 n_n9036 re clock 0 +.latch n2131 n_n7875 re clock 0 +.latch n2136 n_n8697 re clock 0 +.latch n2141 n_n9497 re clock 0 +.latch n2146 n_n7291 re clock 0 +.latch n2151 nsr3_13 re clock 0 +.latch n2156 nsr3_38 re clock 0 +.latch n2161 n_n8240 re clock 0 +.latch n2166 n_n7703 re clock 0 +.latch n2171 n_n9282 re clock 0 +.latch n2176 n_n8237 re clock 0 +.latch n2181 n_n8935 re clock 0 +.latch n2186 n_n9244 re clock 0 +.latch n2191 n_n8648 re clock 0 +.latch n2196 n_n8235 re clock 0 +.latch n2201 n_n8611 re clock 0 +.latch n2206 n_n9045 re clock 0 +.latch n2211 n_n9334 re clock 0 +.latch n2216 n_n8572 re clock 0 +.latch n2221 n_n9491 re clock 0 +.latch n2226 n_n9134 re clock 0 +.latch n2231 n_n9555 re clock 0 +.latch n2236 n_n9336 re clock 0 +.latch n2241 n_n7050 re clock 0 +.latch n2246 n_n9346 re clock 0 +.latch n2251 n_n7140 re clock 0 +.latch n2256 n_n7681 re clock 0 +.latch n2261 n_n6948 re clock 0 +.latch n2266 n_n8549 re clock 0 +.latch n2271 ndn3_19 re clock 0 +.latch n2276 ndn3_28 re clock 0 +.latch n2281 n_n7102 re clock 0 +.latch n2286 n_n8093 re clock 0 +.latch n2291 n_n9041 re clock 0 +.latch n2296 n_n8381 re clock 0 +.latch n2301 n_n8810 re clock 0 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n2456 n_n8808 re clock 0 +.latch n2461 nsr3_30 re clock 0 +.latch n2466 n_n8274 re clock 0 +.latch n2471 n_n8615 re clock 0 +.latch n2476 n_n8238 re clock 0 +.latch n2481 n_n7854 re clock 0 +.latch n2486 n_n8649 re clock 0 +.latch n2491 n_n8236 re clock 0 +.latch n2496 n_n8269 re clock 0 +.latch n2501 n_n9592 re clock 0 +.latch n2506 n_n8022 re clock 0 +.latch n2511 n_n8744 re clock 0 +.latch n2516 n_n8529 re clock 0 +.latch n2521 n_n7967 re clock 0 +.latch n2526 n_n9487 re clock 0 +.latch n2531 n_n8685 re clock 0 +.latch n2536 n_n9531 re clock 0 +.latch n2541 n_n9510 re clock 0 +.latch n2546 n_n7771 re clock 0 +.latch n2551 n_n8480 re clock 0 +.latch n2556 n_n8543 re clock 0 +.latch n2561 n_n7789 re clock 0 +.latch n2566 ndn3_11 re clock 0 +.latch n2571 ndn3_15 re clock 0 +.latch n2576 ndn3_21 re clock 0 +.latch n2581 n_n7584 re clock 0 +.latch n2586 n_n8354 re clock 0 +.latch n2591 n_n6952 re clock 0 +.latch n2596 n_n8864 re clock 0 +.latch n2601 n_n7930 re clock 0 +.latch n2606 n_n7962 re clock 0 +.latch n2611 n_n7929 re clock 0 +.latch n2616 n_n9316 re clock 0 +.latch n2621 n_n9102 re clock 0 +.latch n2626 n_n7308 re clock 0 +.latch n2631 n_n7657 re clock 0 +.latch n2636 n_n9264 re clock 0 +.latch n2641 n_n8760 re clock 0 +.latch n2646 n_n6912 re clock 0 +.latch n2651 n_n7887 re clock 0 +.latch n2656 n_n8911 re clock 0 +.latch n2661 n_n7952 re clock 0 +.latch n2666 n_n8704 re clock 0 +.latch n2671 n_n7876 re clock 0 +.latch n2676 n_n9596 re clock 0 +.latch n2681 n_n8430 re clock 0 +.latch n2686 n_n9019 re clock 0 +.latch n2691 n_n7699 re clock 0 +.latch n2696 n_n7375 re clock 0 +.latch n2701 n_n7936 re clock 0 +.latch n2706 n_n8340 re clock 0 +.latch n2711 n_n8809 re clock 0 +.latch n2716 n_n6961 re clock 0 +.latch n2721 n_n9429 re clock 0 +.latch n2726 n_n7743 re clock 0 +.latch n2731 n_n8980 re clock 0 +.latch n2736 n_n7582 re clock 0 +.latch n2741 n_n8968 re clock 0 +.latch n2746 n_n9371 re clock 0 +.latch n2751 n_n8741 re clock 0 +.latch n2756 n_n9502 re clock 0 +.latch n2761 n_n9373 re clock 0 +.latch n2766 n_n9248 re clock 0 +.latch n2771 n_n7822 re clock 0 +.latch n2776 n_n9054 re clock 0 +.latch n2781 n_n8273 re clock 0 +.latch n2786 n_n6937 re clock 0 +.latch n2791 n_n9342 re clock 0 +.latch n2796 n_n9325 re clock 0 +.latch n2801 n_n9609 re clock 0 +.latch n2806 n_n9623 re clock 0 +.latch n2811 n_n9470 re clock 0 +.latch n2816 n_n7570 re clock 0 +.latch n2821 n_n9310 re clock 0 +.latch n2826 n_n9366 re clock 0 +.latch n2831 n_n7181 re clock 0 +.latch n2836 n_n8739 re clock 0 +.latch n2841 n_n8939 re clock 0 +.latch n2846 n_n7256 re clock 0 +.latch n2851 n_n8983 re clock 0 +.latch n2856 n_n7487 re clock 0 +.latch n2861 n_n9268 re clock 0 +.latch n2866 n_n8906 re clock 0 +.latch n2871 n_n7988 re clock 0 +.latch n2876 n_n9181 re clock 0 +.latch n2881 n_n8725 re clock 0 +.latch n2886 n_n8626 re clock 0 +.latch n2891 ndn3_27 re clock 0 +.latch n2896 n_n8210 re clock 0 +.latch n2901 n_n7415 re clock 0 +.latch n2906 n_n8900 re clock 0 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n3061 nsr3_35 re clock 0 +.latch n3066 n_n7154 re clock 0 +.latch n3071 n_n9495 re clock 0 +.latch n3076 n_n9137 re clock 0 +.latch n3081 n_n8854 re clock 0 +.latch n3086 n_n9183 re clock 0 +.latch n3091 n_n9323 re clock 0 +.latch n3096 n_n9349 re clock 0 +.latch n3101 n_n7896 re clock 0 +.latch n3106 n_n8073 re clock 0 +.latch n3111 n_n8970 re clock 0 +.latch n3116 n_n9314 re clock 0 +.latch n3121 n_n8486 re clock 0 +.latch n3126 n_n7246 re clock 0 +.latch n3131 n_n7866 re clock 0 +.latch n3136 n_n9599 re clock 0 +.latch n3141 n_n7635 re clock 0 +.latch n3146 n_n8984 re clock 0 +.latch n3151 n_n7360 re clock 0 +.latch n3156 n_n8794 re clock 0 +.latch n3161 n_n9108 re clock 0 +.latch n3166 n_n9286 re clock 0 +.latch n3171 ndn3_12 re clock 0 +.latch n3176 ndn3_16 re clock 0 +.latch n3181 n_n7708 re clock 0 +.latch n3186 n_n7807 re clock 0 +.latch n3191 n_n7650 re clock 0 +.latch n3196 n_n7947 re clock 0 +.latch n3201 n_n9500 re clock 0 +.latch n3206 n_n7734 re clock 0 +.latch n3211 n_n8464 re clock 0 +.latch n3216 n_n7659 re clock 0 +.latch n3221 n_n7630 re clock 0 +.latch n3226 n_n7756 re clock 0 +.latch n3231 n_n8691 re clock 0 +.latch n3236 n_n9176 re clock 0 +.latch n3241 n_n9327 re clock 0 +.latch n3246 n_n7995 re clock 0 +.latch n3251 n_n7395 re clock 0 +.latch n3256 n_n7878 re clock 0 +.latch n3261 n_n7507 re clock 0 +.latch n3266 n_n7959 re clock 0 +.latch n3271 n_n7825 re clock 0 +.latch n3276 n_n8009 re clock 0 +.latch n3281 n_n8281 re clock 0 +.latch n3286 n_n7685 re clock 0 +.latch n3291 n_n8106 re clock 0 +.latch n3296 n_n7687 re clock 0 +.latch n3301 n_n7766 re clock 0 +.latch n3306 n_n7880 re clock 0 +.latch n3311 n_n8961 re clock 0 +.latch n3316 n_n8014 re clock 0 +.latch n3321 n_n9278 re clock 0 +.latch n3326 n_n9087 re clock 0 +.latch n3331 n_n9182 re clock 0 +.latch n3336 n_n7852 re clock 0 +.latch n3341 n_n9324 re clock 0 +.latch n3346 nak3_13 re clock 0 +.latch n3351 n_n9416 re clock 0 +.latch n3356 nsr3_14 re clock 0 +.latch n3361 n_n8603 re clock 0 +.latch n3366 n_n7026 re clock 0 +.latch n3371 n_n8856 re clock 0 +.latch n3376 n_n8272 re clock 0 +.latch n3381 n_n9312 re clock 0 +.latch n3386 n_n7985 re clock 0 +.latch n3391 n_n8312 re clock 0 +.latch n3396 n_n7231 re clock 0 +.latch n3401 n_n9396 re clock 0 +.latch n3406 n_n8801 re clock 0 +.latch n3411 n_n8683 re clock 0 +.latch n3416 ndn3_39 re clock 0 +.latch n3421 n_n8245 re clock 0 +.latch n3426 n_n9458 re clock 0 +.latch n3431 n_n9302 re clock 0 +.latch n3436 n_n7392 re clock 0 +.latch n3441 n_n6963 re clock 0 +.latch n3446 n_n7808 re clock 0 +.latch n3451 n_n7225 re clock 0 +.latch n3456 n_n7817 re clock 0 +.latch n3461 n_n8201 re clock 0 +.latch n3466 n_n7793 re clock 0 +.latch n3471 n_n8177 re clock 0 +.latch n3476 n_n8389 re clock 0 +.latch n3481 n_n9440 re clock 0 +.latch n3486 n_n7683 re clock 0 +.latch n3491 n_n7761 re clock 0 +.latch n3496 n_n7667 re clock 0 +.latch n3501 n_n7980 re clock 0 +.latch n3506 n_n7509 re clock 0 +.latch n3511 n_n7813 re clock 0 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n3666 n_n7879 re clock 0 +.latch n3671 n_n7019 re clock 0 +.latch n3676 n_n9171 re clock 0 +.latch n3681 n_n7261 re clock 0 +.latch n3686 n_n8223 re clock 0 +.latch n3691 n_n8989 re clock 0 +.latch n3696 n_n7993 re clock 0 +.latch n3701 n_n7845 re clock 0 +.latch n3706 n_n8253 re clock 0 +.latch n3711 n_n8889 re clock 0 +.latch n3716 n_n7809 re clock 0 +.latch n3721 n_n8918 re clock 0 +.latch n3726 n_n8515 re clock 0 +.latch n3731 n_n7933 re clock 0 +.latch n3736 n_n8075 re clock 0 +.latch n3741 n_n7338 re clock 0 +.latch n3746 n_n8104 re clock 0 +.latch n3751 n_n8171 re clock 0 +.latch n3756 n_n9059 re clock 0 +.latch n3761 n_n9023 re clock 0 +.latch n3766 n_n7692 re clock 0 +.latch n3771 n_n9441 re clock 0 +.latch n3776 n_n6920 re clock 0 +.latch n3781 n_n8831 re clock 0 +.latch n3786 n_n8441 re clock 0 +.latch n3791 n_n9576 re clock 0 +.latch n3796 n_n9252 re clock 0 +.latch n3801 n_n9363 re clock 0 +.latch n3806 ndn3_4 re clock 0 +.latch n3811 n_n9247 re clock 0 +.latch n3816 n_n7561 re clock 0 +.latch n3821 n_n8923 re clock 0 +.latch n3826 n_n7978 re clock 0 +.latch n3831 n_n8978 re clock 0 +.latch n3836 n_n9499 re clock 0 +.latch n3841 n_n8713 re clock 0 +.latch n3846 n_n8944 re clock 0 +.latch n3851 n_n8239 re clock 0 +.latch n3856 n_n7652 re clock 0 +.latch n3861 n_n9042 re clock 0 +.latch n3866 n_n8530 re clock 0 +.latch n3871 n_n9271 re clock 0 +.latch n3876 n_n9318 re clock 0 +.latch n3881 n_n7706 re clock 0 +.latch n3886 n_n7964 re clock 0 +.latch n3891 n_n8222 re clock 0 +.latch n3896 n_n8898 re clock 0 +.latch n3901 n_n7976 re clock 0 +.latch n3906 n_n7649 re clock 0 +.latch n3911 n_n7604 re clock 0 +.latch n3916 n_n7961 re clock 0 +.latch n3921 n_n7424 re clock 0 +.latch n3926 n_n7476 re clock 0 +.latch n3931 n_n9259 re clock 0 +.latch n3936 n_n9309 re clock 0 +.latch n3941 n_n9161 re clock 0 +.latch n3946 n_n8436 re clock 0 +.latch n3951 n_n9121 re clock 0 +.latch n3956 n_n8061 re clock 0 +.latch n3961 n_n8004 re clock 0 +.latch n3966 n_n9360 re clock 0 +.latch n3971 n_n9205 re clock 0 +.latch n3976 n_n8392 re clock 0 +.latch n3981 n_n9034 re clock 0 +.latch n3986 n_n8375 re clock 0 +.latch n3991 n_n8328 re clock 0 +.latch n3996 n_n9298 re clock 0 +.latch n4001 n_n7598 re clock 0 +.latch n4006 n_n8506 re clock 0 +.latch n4011 n_n7737 re clock 0 +.latch n4016 n_n7420 re clock 0 +.latch n4021 n_n9291 re clock 0 +.latch n4026 n_n7946 re clock 0 +.latch n4031 n_n8584 re clock 0 +.latch n4036 n_n9308 re clock 0 +.latch n4041 n_n9403 re clock 0 +.latch n4046 n_n7284 re clock 0 +.latch n4051 n_n9270 re clock 0 +.latch n4056 n_n7390 re clock 0 +.latch n4061 n_n9351 re clock 0 +.latch n4066 n_n6968 re clock 0 +.latch n4071 n_n8668 re clock 0 +.latch n4076 n_n9605 re clock 0 +.latch n4081 n_n7013 re clock 0 +.latch n4086 n_n9626 re clock 0 +.latch n4091 n_n8200 re clock 0 +.latch n4096 n_n9028 re clock 0 +.latch n4101 n_n8803 re clock 0 +.latch n4106 n_n9570 re clock 0 +.latch n4111 n_n8366 re clock 0 +.latch n4116 n_n9050 re clock 0 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n4271 n_n7914 re clock 0 +.latch n4276 n_n7873 re clock 0 +.latch n4281 n_n7849 re clock 0 +.latch n4286 n_n9421 re clock 0 +.latch n4291 n_n7626 re clock 0 +.latch n4296 n_n7848 re clock 0 +.latch n4301 n_n8263 re clock 0 +.latch n4306 n_n9100 re clock 0 +.latch n4311 n_n9393 re clock 0 +.latch n4316 n_n9591 re clock 0 +.latch n4321 n_n7588 re clock 0 +.latch n4326 n_n9123 re clock 0 +.latch n4331 n_n9159 re clock 0 +.latch n4336 n_n9128 re clock 0 +.latch n4341 n_n8045 re clock 0 +.latch n4346 n_n7728 re clock 0 +.latch n4351 n_n8929 re clock 0 +.latch n4356 n_n7739 re clock 0 +.latch n4361 n_n9355 re clock 0 +.latch n4366 n_n9394 re clock 0 +.latch n4371 n_n8470 re clock 0 +.latch n4376 n_n8571 re clock 0 +.latch n4381 n_n8796 re clock 0 +.latch n4386 ndn3_36 re clock 0 +.latch n4391 n_n7990 re clock 0 +.latch n4396 n_n8781 re clock 0 +.latch n4401 n_n8817 re clock 0 +.latch n4406 n_n9160 re clock 0 +.latch n4411 n_n9092 re clock 0 +.latch n4416 n_n8513 re clock 0 +.latch n4421 n_n8213 re clock 0 +.latch n4426 n_n8581 re clock 0 +.latch n4431 n_n9284 re clock 0 +.latch n4436 n_n7837 re clock 0 +.latch n4441 n_n8224 re clock 0 +.latch n4446 n_n9203 re clock 0 +.latch n4451 n_n7655 re clock 0 +.latch n4456 n_n8946 re clock 0 +.latch n4461 n_n7052 re clock 0 +.latch n4466 n_n9615 re clock 0 +.latch n4471 n_n8473 re clock 0 +.latch n4476 n_n7741 re clock 0 +.latch n4481 n_n9460 re clock 0 +.latch n4486 n_n7912 re clock 0 +.latch n4491 n_n7606 re clock 0 +.latch n4496 n_n9021 re clock 0 +.latch n4501 n_n7781 re clock 0 +.latch n4506 n_n7810 re clock 0 +.latch n4511 n_n7108 re clock 0 +.latch n4516 n_n7697 re clock 0 +.latch n4521 n_n7642 re clock 0 +.latch n4526 n_n9595 re clock 0 +.latch n4531 n_n7694 re clock 0 +.latch n4536 n_n8221 re clock 0 +.latch n4541 n_n7600 re clock 0 +.latch n4546 n_n7935 re clock 0 +.latch n4551 n_n9230 re clock 0 +.latch n4556 n_n7701 re clock 0 +.latch n4561 n_n7510 re clock 0 +.latch n4566 n_n7627 re clock 0 +.latch n4571 n_n8502 re clock 0 +.latch n4576 n_n8516 re clock 0 +.latch n4581 n_n7913 re clock 0 +.latch n4586 n_n9320 re clock 0 +.latch n4591 n_n7411 re clock 0 +.latch n4596 n_n9129 re clock 0 +.latch n4601 n_n9053 re clock 0 +.latch n4606 n_n7069 re clock 0 +.latch n4611 n_n8617 re clock 0 +.latch n4616 n_n7242 re clock 0 +.latch n4621 n_n8230 re clock 0 +.latch n4626 n_n9294 re clock 0 +.latch n4631 n_n8249 re clock 0 +.latch n4636 n_n8972 re clock 0 +.latch n4641 n_n7074 re clock 0 +.latch n4646 n_n7493 re clock 0 +.latch n4651 n_n8290 re clock 0 +.latch n4656 n_n8821 re clock 0 +.latch n4661 n_n7769 re clock 0 +.latch n4666 n_n7491 re clock 0 +.latch n4671 n_n9600 re clock 0 +.latch n4676 n_n9317 re clock 0 +.latch n4681 n_n8047 re clock 0 +.latch n4686 n_n9629 re clock 0 +.latch n4691 n_n9126 re clock 0 +.latch n4696 n_n9508 re clock 0 +.latch n4701 n_n9155 re clock 0 +.latch n4706 n_n8528 re clock 0 +.latch n4711 ndn3_37 re clock 0 +.latch n4716 ndn3_42 re clock 0 +.latch n4721 n_n9358 re clock 0 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n4876 n_n8779 re clock 0 +.latch n4881 n_n6980 re clock 0 +.latch n4886 n_n7715 re clock 0 +.latch n4891 n_n9067 re clock 0 +.latch n4896 n_n9164 re clock 0 +.latch n4901 n_n7402 re clock 0 +.latch n4906 n_n8938 re clock 0 +.latch n4911 n_n9046 re clock 0 +.latch n4916 n_n8789 re clock 0 +.latch n4921 n_n9390 re clock 0 +.latch n4926 n_n7768 re clock 0 +.latch n4931 n_n9136 re clock 0 +.latch n4936 n_n8670 re clock 0 +.latch n4941 n_n8644 re clock 0 +.latch n4946 n_n9178 re clock 0 +.latch n4951 n_n8188 re clock 0 +.latch n4956 n_n7083 re clock 0 +.latch n4961 n_n9344 re clock 0 +.latch n4966 n_n7366 re clock 0 +.latch n4971 n_n8361 re clock 0 +.latch n4976 n_n9228 re clock 0 +.latch n4981 n_n9402 re clock 0 +.latch n4986 n_n8510 re clock 0 +.latch n4991 n_n8881 re clock 0 +.latch n4996 n_n9404 re clock 0 +.latch n5001 n_n9424 re clock 0 +.latch n5006 n_n9031 re clock 0 +.latch n5011 nsr3_37 re clock 0 +.latch n5016 n_n8197 re clock 0 +.latch n5021 n_n8468 re clock 0 +.latch n5026 n_n7121 re clock 0 +.latch n5031 n_n7511 re clock 0 +.latch n5036 ndn3_44 re clock 0 +.latch n5041 n_n9322 re clock 0 +.latch n5046 n_n7682 re clock 0 +.latch n5051 n_n9603 re clock 0 +.latch n5056 nlc1_2 re clock 0 +.latch n5061 n_n8408 re clock 0 +.latch n5066 n_n8577 re clock 0 +.latch n5071 n_n7079 re clock 0 +.latch n5076 n_n8828 re clock 0 +.latch n5081 n_n9340 re clock 0 +.latch n5086 n_n8586 re clock 0 +.latch n5091 n_n7901 re clock 0 +.latch n5096 n_n8628 re clock 0 +.latch n5101 n_n8869 re clock 0 +.latch n5106 n_n7710 re clock 0 +.latch n5111 n_n8993 re clock 0 +.latch n5116 n_n9586 re clock 0 +.latch n5121 n_n8852 re clock 0 +.latch n5126 n_n8583 re clock 0 +.latch n5131 n_n8011 re clock 0 +.latch n5136 n_n7717 re clock 0 +.latch n5141 n_n8326 re clock 0 +.latch n5146 n_n9163 re clock 0 +.latch n5151 n_n8344 re clock 0 +.latch n5156 n_n8296 re clock 0 +.latch n5161 n_n8116 re clock 0 +.latch n5166 n_n8267 re clock 0 +.latch n5171 n_n7686 re clock 0 +.latch n5176 n_n9061 re clock 0 +.latch n5181 n_n9338 re clock 0 +.latch n5186 n_n7688 re clock 0 +.latch n5191 n_n9081 re clock 0 +.latch n5196 n_n6910 re clock 0 +.latch n5201 n_n8727 re clock 0 +.latch n5206 n_n7674 re clock 0 +.latch n5211 n_n7330 re clock 0 +.latch n5216 n_n8966 re clock 0 +.latch n5221 n_n7843 re clock 0 +.latch n5226 n_n8847 re clock 0 +.latch n5231 n_n9376 re clock 0 +.latch n5236 n_n7553 re clock 0 +.latch n5241 n_n9292 re clock 0 +.latch n5246 n_n7464 re clock 0 +.latch n5251 n_n8146 re clock 0 +.latch n5256 n_n8439 re clock 0 +.latch n5261 n_n9498 re clock 0 +.latch n5266 n_n8118 re clock 0 +.latch n5271 n_n9452 re clock 0 +.latch n5276 n_n9239 re clock 0 +.latch n5281 n_n9237 re clock 0 +.latch n5286 n_n9488 re clock 0 +.latch n5291 ndn3_2 re clock 0 +.latch n5296 n_n9522 re clock 0 +.latch n5301 n_n9313 re clock 0 +.latch n5306 n_n7435 re clock 0 +.latch n5311 n_n8665 re clock 0 +.latch n5316 n_n9593 re clock 0 +.latch n5321 n_n8303 re clock 0 +.latch n5326 n_n7022 re clock 0 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n5481 n_n7336 re clock 0 +.latch n5486 n_n8226 re clock 0 +.latch n5491 n_n8151 re clock 0 +.latch n5496 n_n7644 re clock 0 +.latch n5501 n_n8770 re clock 0 +.latch n5506 n_n8423 re clock 0 +.latch n5511 n_n7763 re clock 0 +.latch n5516 n_n9525 re clock 0 +.latch n5521 n_n8033 re clock 0 +.latch n5526 n_n7881 re clock 0 +.latch n5531 n_n7815 re clock 0 +.latch n5536 n_n9232 re clock 0 +.latch n5541 n_n7792 re clock 0 +.latch n5546 n_n9563 re clock 0 +.latch n5551 n_n8672 re clock 0 +.latch n5556 n_n7346 re clock 0 +.latch n5561 n_n7949 re clock 0 +.latch n5566 n_n8756 re clock 0 +.latch n5571 n_n8641 re clock 0 +.latch n5576 n_n8192 re clock 0 +.latch n5581 n_n8058 re clock 0 +.latch n5586 n_n8561 re clock 0 +.latch n5591 n_n9306 re clock 0 +.latch n5596 n_n9165 re clock 0 +.latch n5601 n_n8850 re clock 0 +.latch n5606 n_n9210 re clock 0 +.latch n5611 ndn2_2 re clock 0 +.latch n5616 n_n7342 re clock 0 +.latch n5621 n_n8051 re clock 0 +.latch n5626 n_n7136 re clock 0 +.latch n5631 n_n9348 re clock 0 +.latch n5636 n_n9006 re clock 0 +.latch n5641 n_n7653 re clock 0 +.latch n5646 n_n7905 re clock 0 +.latch n5651 n_n9166 re clock 0 +.latch n5656 n_n7065 re clock 0 +.latch n5661 n_n9490 re clock 0 +.latch n5666 n_n7024 re clock 0 +.latch n5671 n_n7586 re clock 0 +.latch n5676 n_n8416 re clock 0 +.latch n5681 n_n8937 re clock 0 +.latch n5686 n_n8141 re clock 0 +.latch n5691 n_n7853 re clock 0 +.latch n5696 n_n8121 re clock 0 +.latch n5701 n_n9604 re clock 0 +.latch n5706 n_n9496 re clock 0 +.latch n5711 n_n8195 re clock 0 +.latch n5716 n_n9516 re clock 0 +.latch n5721 n_n9077 re clock 0 +.latch n5726 n_n9436 re clock 0 +.latch n5731 n_n9051 re clock 0 +.latch n5736 n_n7664 re clock 0 +.latch n5741 n_n8419 re clock 0 +.latch n5746 n_n7874 re clock 0 +.latch n5751 n_n9133 re clock 0 +.latch n5756 n_n9392 re clock 0 +.latch n5761 n_n7770 re clock 0 +.latch n5766 ndn3_32 re clock 0 +.latch n5771 n_n7601 re clock 0 +.latch n5776 n_n8206 re clock 0 +.latch n5781 n_n7927 re clock 0 +.latch n5786 n_n9606 re clock 0 +.latch n5791 n_n7111 re clock 0 +.latch n5796 n_n9269 re clock 0 +.latch n5801 ndn3_38 re clock 0 +.latch n5806 n_n7886 re clock 0 +.latch n5811 n_n9179 re clock 0 +.latch n5816 n_n9357 re clock 0 +.latch n5821 n_n9594 re clock 0 +.latch n5826 n_n7628 re clock 0 +.latch n5831 n_n8454 re clock 0 +.latch n5836 ndn3_20 re clock 0 +.latch n5841 n_n9505 re clock 0 +.latch n5846 nen3_34 re clock 0 +.latch n5851 n_n9632 re clock 0 +.latch n5856 n_n7076 re clock 0 +.latch n5861 n_n9262 re clock 0 +.latch n5866 n_n9048 re clock 0 +.latch n5871 n_n9578 re clock 0 +.latch n5876 n_n8135 re clock 0 +.latch n5881 ndn3_26 re clock 0 +.latch n5886 n_n7500 re clock 0 +.latch n5891 n_n6974 re clock 0 +.latch n5896 n_n8605 re clock 0 +.latch n5901 n_n9296 re clock 0 +.latch n5906 n_n7156 re clock 0 +.latch n5911 n_n7920 re clock 0 +.latch n5916 n_n8895 re clock 0 +.latch n5921 n_n8991 re clock 0 +.latch n5926 n_n8139 re clock 0 +.latch n5931 n_n9275 re clock 0 +.latch n5936 n_n7203 re clock 0 +.latch n5941 n_n9590 re clock 0 +.latch n5946 n_n7344 re clock 0 +.latch n5951 n_n6976 re clock 0 +.latch n5956 n_n7629 re clock 0 +.latch n5961 ndn3_14 re clock 0 +.latch n5966 n_n7862 re clock 0 +.latch n5971 n_n9013 re clock 0 +.latch n5976 n_n7288 re clock 0 +.latch n5981 n_n8078 re clock 0 +.latch n5986 n_n7334 re clock 0 +.latch n5991 n_n7704 re clock 0 +.latch n5996 n_n7788 re clock 0 +.latch n6001 n_n8526 re clock 0 +.latch n6006 n_n9556 re clock 0 +.latch n6011 n_n9345 re clock 0 +.latch n6016 n_n8447 re clock 0 +.latch n6021 n_n7485 re clock 0 +.latch n6026 n_n8570 re clock 0 +.latch n6031 n_n7453 re clock 0 +.latch n6036 n_n7928 re clock 0 +.latch n6041 n_n8646 re clock 0 +.latch n6046 n_n9405 re clock 0 +.latch n6051 n_n8948 re clock 0 +.latch n6056 n_n9131 re clock 0 +.latch n6061 n_n8216 re clock 0 +.latch n6066 n_n9177 re clock 0 +.latch n6071 n_n7844 re clock 0 +.latch n6076 n_n8811 re clock 0 +.latch n6081 n_n9145 re clock 0 +.latch n6086 n_n8428 re clock 0 +.latch n6091 n_n8858 re clock 0 +.latch n6096 n_n8580 re clock 0 + +.names n_n7154 tin_psv39_8_8_ n_n9366 psv39_8_8_ +01- 1 +1-1 1 +.names n_n6986 tin_psv39_0_0_ n_n9424 psv39_0_0_ +01- 1 +1-1 1 +.names n_n7561 tin_psv13_5_5_ n_n9004 psv13_5_5_ +01- 1 +1-1 1 +.names n_n8245 tin_psv2_13_13_ n_n9169 psv2_13_13_ +01- 1 +1-1 1 +.names n_n8121 tin_psv2_8_8_ n_n8303 psv2_8_8_ +01- 1 +1-1 1 +.names n_n7146 tin_psv38_2_2_ n_n6910 psv38_2_2_ +01- 1 +1-1 1 +.names n_n7050 tin_psv33_5_5_ n_n9148 psv33_5_5_ +01- 1 +1-1 1 +.names n_n7622 tin_psv26_6_6_ n_n6980 psv26_6_6_ +01- 1 +1-1 1 +.names n_n8918 tin_psv2_9_9_ n_n7522 psv2_9_9_ +01- 1 +1-1 1 +.names n_n7905 tin_psv18_2_2_ n_n8801 psv18_2_2_ +01- 1 +1-1 1 +.names n_n7717 tin_psv39_9_9_ n_n7332 psv39_9_9_ +01- 1 +1-1 1 +.names n_n8946 tin_psv39_1_1_ n_n8430 psv39_1_1_ +01- 1 +1-1 1 +.names n_n8568 tin_psv13_6_6_ n_n7179 psv13_6_6_ +01- 1 +1-1 1 +.names n_n7150 tin_psv2_6_6_ n_n7022 psv2_6_6_ +01- 1 +1-1 1 +.names n_n7491 tin_psv38_3_3_ n_n7203 psv38_3_3_ +01- 1 +1-1 1 +.names n_n8243 tin_psv33_6_6_ n_n7344 psv33_6_6_ +01- 1 +1-1 1 +.names n_n7381 tin_psv26_13_13_ n_n7500 psv26_13_13_ +01- 1 +1-1 1 +.names n_n7798 tin_psv26_12_12_ n_n8488 psv26_12_12_ +01- 1 +1-1 1 +.names n_n7362 tin_psv26_7_7_ n_n8702 psv26_7_7_ +01- 1 +1-1 1 +.names n_n8392 tin_psv2_7_7_ n_n8061 psv2_7_7_ +01- 1 +1-1 1 +.names n_n7079 tin_psv18_3_3_ n_n7498 psv18_3_3_ +01- 1 +1-1 1 +.names n_n7978 tin_psv39_2_2_ n_n7726 psv39_2_2_ +01- 1 +1-1 1 +.names n_n7493 tin_psv33_12_12_ n_n8369 psv33_12_12_ +01- 1 +1-1 1 +.names n_n8665 tin_psv33_11_11_ n_n7923 psv33_11_11_ +01- 1 +1-1 1 +.names n_n9123 tin_psv33_10_10_ n_n9483 psv33_10_10_ +01- 1 +1-1 1 +.names n_n9228 tin_psv13_7_7_ n_n7546 psv13_7_7_ +01- 1 +1-1 1 +.names n_n7244 tin_psv2_10_10_ n_n8681 psv2_10_10_ +01- 1 +1-1 1 +.names n_n7052 tin_psv38_4_4_ n_n7674 psv38_4_4_ +01- 1 +1-1 1 +.names n_n7330 tin_psv39_10_10_ n_n8644 psv39_10_10_ +01- 1 +1-1 1 +.names n_n7140 tin_psv33_7_7_ n_n7843 psv33_7_7_ +01- 1 +1-1 1 +.names n_n8389 tin_psv26_15_15_ n_n9026 psv26_15_15_ +01- 1 +1-1 1 +.names n_n9200 tin_psv26_14_14_ n_n7392 psv26_14_14_ +01- 1 +1-1 1 +.names n_n6937 tin_psv26_8_8_ n_n7581 psv26_8_8_ +01- 1 +1-1 1 +.names n_n7246 tin_psv26_0_0_ n_n7017 psv26_0_0_ +01- 1 +1-1 1 +.names n_n8055 tin_psv13_12_12_ n_n8895 psv13_12_12_ +01- 1 +1-1 1 +.names n_n7336 tin_psv13_11_11_ n_n9548 psv13_11_11_ +01- 1 +1-1 1 +.names n_n9006 tin_psv18_4_4_ n_n9432 psv18_4_4_ +01- 1 +1-1 1 +.names n_n7507 tin_psv39_3_3_ n_n7108 psv39_3_3_ +01- 1 +1-1 1 +.names n_n7261 tin_psv13_8_8_ n_n7271 psv13_8_8_ +01- 1 +1-1 1 +.names n_n7176 tin_psv13_0_0_ n_n7775 psv13_0_0_ +01- 1 +1-1 1 +.names n_n8655 tin_psv38_5_5_ n_n7256 psv38_5_5_ +01- 1 +1-1 1 +.names n_n9306 tin_psv33_8_8_ n_n7288 psv33_8_8_ +01- 1 +1-1 1 +.names n_n8672 tin_psv33_0_0_ n_n8486 psv33_0_0_ +01- 1 +1-1 1 +.names n_n7310 tin_psv26_9_9_ n_n7360 psv26_9_9_ +01- 1 +1-1 1 +.names n_n7699 tin_psv26_1_1_ n_n7231 psv26_1_1_ +01- 1 +1-1 1 +.names n_n6956 tin_psv13_10_10_ n_n7976 psv13_10_10_ +01- 1 +1-1 1 +.names n_n7903 tin_psv18_5_5_ n_n7715 psv18_5_5_ +01- 1 +1-1 1 +.names n_n7117 tin_psv39_4_4_ n_n7121 psv39_4_4_ +01- 1 +1-1 1 +.names n_n7944 tin_psv13_9_9_ n_n9376 psv13_9_9_ +01- 1 +1-1 1 +.names n_n7013 tin_psv13_1_1_ n_n8589 psv13_1_1_ +01- 1 +1-1 1 +.names n_n6948 tin_psv2_15_15_ n_n8102 psv2_15_15_ +01- 1 +1-1 1 +.names n_n6952 tin_psv2_11_11_ n_n6963 psv2_11_11_ +01- 1 +1-1 1 +.names n_n7024 tin_psv2_0_0_ n_n8371 psv2_0_0_ +01- 1 +1-1 1 +.names n_n8454 tin_psv38_14_14_ n_n7174 psv38_14_14_ +01- 1 +1-1 1 +.names n_n8605 tin_psv38_12_12_ n_n7402 psv38_12_12_ +01- 1 +1-1 1 +.names n_n7181 tin_psv38_10_10_ n_n7284 psv38_10_10_ +01- 1 +1-1 1 +.names n_n7556 tin_psv38_6_6_ n_n7514 psv38_6_6_ +01- 1 +1-1 1 +.names n_n7019 tin_psv18_15_15_ n_n7074 psv18_15_15_ +01- 1 +1-1 1 +.names n_n7415 tin_psv18_13_13_ n_n7148 psv18_13_13_ +01- 1 +1-1 1 +.names n_n8195 tin_psv18_11_11_ n_n8439 psv18_11_11_ +01- 1 +1-1 1 +.names n_n8725 tin_psv33_9_9_ n_n9278 psv33_9_9_ +01- 1 +1-1 1 +.names n_n7635 tin_psv33_1_1_ n_n8091 psv33_1_1_ +01- 1 +1-1 1 +.names n_n7276 tin_psv26_2_2_ n_n7777 psv26_2_2_ +01- 1 +1-1 1 +.names n_n7467 tin_psv2_1_1_ n_n7678 psv2_1_1_ +01- 1 +1-1 1 +.names n_n8216 tin_psv38_15_15_ n_n8340 psv38_15_15_ +01- 1 +1-1 1 +.names n_n7033 tin_psv38_11_11_ n_n7857 psv38_11_11_ +01- 1 +1-1 1 +.names n_n8817 tin_psv18_12_12_ n_n9465 psv18_12_12_ +01- 1 +1-1 1 +.names n_n8230 tin_psv18_6_6_ n_n7156 psv18_6_6_ +01- 1 +1-1 1 +.names n_n8633 tin_psv39_5_5_ n_n8777 psv39_5_5_ +01- 1 +1-1 1 +.names n_n8251 tin_psv13_2_2_ n_n7130 psv13_2_2_ +01- 1 +1-1 1 +.names n_n8713 tin_psv38_7_7_ n_n8592 psv38_7_7_ +01- 1 +1-1 1 +.names n_n9476 tin_psv39_12_12_ n_n8100 psv39_12_12_ +01- 1 +1-1 1 +.names n_n7315 tin_psv39_11_11_ n_n7390 psv39_11_11_ +01- 1 +1-1 1 +.names n_n7209 tin_psv33_2_2_ n_n7111 psv33_2_2_ +01- 1 +1-1 1 +.names n_n7338 tin_psv26_3_3_ n_n8384 psv26_3_3_ +01- 1 +1-1 1 +.names n_n7959 tin_psv13_14_14_ n_n7252 psv13_14_14_ +01- 1 +1-1 1 +.names n_n8704 tin_psv13_13_13_ n_n6991 psv13_13_13_ +01- 1 +1-1 1 +.names n_n8974 tin_psv18_10_10_ n_n8146 psv18_10_10_ +01- 1 +1-1 1 +.names n_n7659 tin_psv18_7_7_ n_n8049 psv18_7_7_ +01- 1 +1-1 1 +.names n_n8047 tin_psv39_6_6_ n_n8073 psv39_6_6_ +01- 1 +1-1 1 +.names n_n7026 tin_psv33_15_15_ n_n8263 psv33_15_15_ +01- 1 +1-1 1 +.names n_n6988 tin_psv33_14_14_ n_n9429 psv33_14_14_ +01- 1 +1-1 1 +.names n_n8290 tin_psv33_13_13_ n_n7069 psv33_13_13_ +01- 1 +1-1 1 +.names n_n7586 tin_psv13_3_3_ n_n8850 psv13_3_3_ +01- 1 +1-1 1 +.names n_n8683 tin_psv2_14_14_ n_n7102 psv2_14_14_ +01- 1 +1-1 1 +.names n_n7286 tin_psv2_12_12_ n_n8132 psv2_12_12_ +01- 1 +1-1 1 +.names n_n7291 tin_psv2_4_4_ n_n8045 psv2_4_4_ +01- 1 +1-1 1 +.names n_n6984 tin_psv38_8_8_ n_n9421 psv38_8_8_ +01- 1 +1-1 1 +.names n_n8921 tin_psv38_0_0_ n_n8916 psv38_0_0_ +01- 1 +1-1 1 +.names n_n8441 tin_psv39_14_14_ n_n9371 psv39_14_14_ +01- 1 +1-1 1 +.names n_n8831 tin_psv39_13_13_ n_n7366 psv39_13_13_ +01- 1 +1-1 1 +.names n_n7409 tin_psv33_3_3_ n_n7420 psv33_3_3_ +01- 1 +1-1 1 +.names n_n7308 tin_psv26_11_11_ n_n8185 psv26_11_11_ +01- 1 +1-1 1 +.names n_n9580 tin_psv26_10_10_ n_n8781 psv26_10_10_ +01- 1 +1-1 1 +.names n_n8112 tin_psv26_4_4_ n_n8175 psv26_4_4_ +01- 1 +1-1 1 +.names n_n8406 tin_psv13_15_15_ n_n9145 psv13_15_15_ +01- 1 +1-1 1 +.names n_n9446 tin_psv2_5_5_ n_n7395 psv2_5_5_ +01- 1 +1-1 1 +.names n_n7242 tin_psv18_8_8_ n_n8678 psv18_8_8_ +01- 1 +1-1 1 +.names n_n7065 tin_psv18_0_0_ n_n7190 psv18_0_0_ +01- 1 +1-1 1 +.names n_n7183 tin_psv39_7_7_ n_n7160 psv39_7_7_ +01- 1 +1-1 1 +.names n_n9085 tin_psv13_4_4_ n_n9096 psv13_4_4_ +01- 1 +1-1 1 +.names n_n8510 tin_psv2_2_2_ n_n7054 psv2_2_2_ +01- 1 +1-1 1 +.names n_n8944 tin_psv38_9_9_ n_n8428 psv38_9_9_ +01- 1 +1-1 1 +.names n_n9373 tin_psv38_1_1_ n_n7964 psv38_1_1_ +01- 1 +1-1 1 +.names n_n7411 tin_psv39_15_15_ n_n8361 psv39_15_15_ +01- 1 +1-1 1 +.names n_n7003 tin_psv33_4_4_ n_n7462 psv33_4_4_ +01- 1 +1-1 1 +.names n_n8423 tin_psv26_5_5_ n_n7076 psv26_5_5_ +01- 1 +1-1 1 +.names n_n6912 tin_psv2_3_3_ n_n8750 psv2_3_3_ +01- 1 +1-1 1 +.names n_n9531 tin_psv38_13_13_ n_n6920 psv38_13_13_ +01- 1 +1-1 1 +.names n_n8762 tin_psv18_14_14_ n_n7435 psv18_14_14_ +01- 1 +1-1 1 +.names n_n6950 tin_psv18_9_9_ n_n6961 psv18_9_9_ +01- 1 +1-1 1 +.names n_n7387 tin_psv18_1_1_ n_n9535 psv18_1_1_ +01- 1 +1-1 1 +.names preset n_n9280 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n501_1 +1----- 0 +-0---- 0 +--1100 0 +.names nsr3_37 preset n4711 +00 1 +.names preset nsr3_37 ndn3_37 n_n9172 n3730 n506_1 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n9434 n3731_1 n3730 +10 1 +.names n3732 n_n8929 n_n8930 n3731_1 +00- 1 +0-0 1 +.names n_n8930 n3767 n3754 n3733 n3781_1 n3732 +1---- 0 +-1111 0 +.names n3751_1 n3748 n3745 n3734 n3733 +1111 1 +.names n3739 n3735 n_n9557 n_n9561 n3744 n3743 n3734 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n_n9554 n3736_1 n_n9558 n3737 n_n9556 n3738 n3735 +11---- 0 +--11-- 0 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n_n7583 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n916 +1----- 0 +-0---- 0 +--1100 0 +.names n4176_1 preset n4327 n921 +100 0 +.names n_n9248 n4328 n4327 +10 1 +.names n4337 n4336_1 n4335 n4334 n4329 n4328 +11111 1 +.names n_n8561 n4330 n_n8978 n_n9034 n_n9031 n_n8993 n4329 +00---- 1 +0-1--- 1 +0--1-- 1 +0---1- 1 +0----1 1 +110000 1 +.names n4331_1 n_n8911 n4330 +10 1 +.names n4332 n_n8933 n4331_1 +10 1 +.names n4333 n_n8869 n4332 +10 1 +.names n_n8603 n_n8798 n_n8923 n4333 +100 1 +.names n_n9034 n4330 n_n8978 n_n9031 n_n8993 n4334 +00--- 1 +0-1-- 1 +0--1- 1 +0---1 1 +11000 1 +.names n_n9031 n4330 n_n8978 n_n8993 n4335 +00-- 1 +0-1- 1 +0--1 1 +1100 1 +.names n_n8993 n4330 n_n8978 n4336_1 +00- 1 +0-1 1 +110 1 +.names n4340 n4339 n4338 n_n8798 n_n8603 n_n8923 n4337 +111000 1 +.names n_n8847 n_n8631 n4338 +00 1 +.names n_n8869 n_n8978 n_n8911 n_n8933 n4339 +0000 1 +.names n_n9248 n_n9247 n_n9011 n_n8964 n_n8913 n_n7306 n4340 +110000 1 +.names n3850 preset n3803 n_n9602 n926 +00-1 1 +101- 1 +.names n3850 preset n4324 n4052 n4027 n_n8786 n931 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3838 preset n3803 n_n9598 n936 +00-1 1 +101- 1 +.names n3843 preset n4187 n_n7738 n941 +00-1 1 +101- 1 +.names preset n_n8573 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n946 +1----- 0 +-0---- 0 +--1100 0 +.names n3836_1 preset n4106_1 n_n9473 n951 +00-1 1 +101- 1 +.names n3843 preset n4217 n3853 n_n9000 n956 +00--1 1 +1000- 1 +1011- 1 +.names preset ndn3_38 nsr3_38 n_n8001 n4349 n961 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n8557 n3731_1 n4349 +10 1 +.names preset n_n9554 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n966 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8508 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n971 +1----- 0 +-0---- 0 +--1100 0 +.names n3819 preset n4081_1 n_n9635 n976 +00-1 1 +101- 1 +.names n3819 preset n_n8249 n_n7190 n981 +00-1 1 +101- 1 +.names n3827 preset n_n8213 n_n8702 n986 +00-1 1 +101- 1 +.names n3813 preset n4356_1 n_n9106 n991 +00-1 1 +101- 1 +.names n3962 n3949 n3935 n4356_1 +001 1 +010 1 +100 1 +111 1 +.names preset n_n7409 ngfdn_3 ndn3_50 n996 +01-- 1 +0-10 1 +.names preset n_n9437 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1001 +1----- 0 +-0---- 0 +--1100 0 +.names n3808 preset n4356_1 n_n9052 n1006 +00-1 1 +101- 1 +.names preset n_n8647 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1011 +1----- 0 +-0---- 0 +--1100 0 +.names n3826_1 preset n3803 n_n9265 n1016 +00-1 1 +101- 1 +.names n3818 preset n_n7783 n_n7179 n1021 +00-1 1 +101- 1 +.names ngfdn_3 preset ndn3_17 ndn3_16 n1031 +001- 1 +00-1 1 +.names ngfdn_3 preset ndn3_22 ndn3_25 n1036 +001- 1 +00-1 1 +.names ngfdn_3 preset ndn3_29 ndn3_28 n1041 +001- 1 +00-1 1 +.names preset n_n9539 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1046 +1----- 0 +-0---- 0 +--1100 0 +.names preset ndn3_13 nsr3_13 n_n7953 n4368 n1051 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n8821 n3731_1 n4368 +10 1 +.names n3827 preset n_n9412 n_n8488 n1056 +00-1 1 +101- 1 +.names ngfdn_3 preset nsr3_23 nen3_22 n1061 +000- 1 +00-1 1 +.names preset n_n9438 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1066 +1----- 0 +-0---- 0 +--1100 0 +.names n3835 preset n_n8150 n_n8132 n1071 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n8661 n4374 n1076 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n9416 n3731_1 n4374 +10 1 +.names n4079 preset psv18_11_11_ n_n7759 n1081 +00-1 1 +101- 1 +.names n3822 preset n4219 n_n8333 n1086 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n9399 n4207 n1091 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3827 n_n7798 n1096 +01- 1 +0-1 1 +.names n_n9434 n4183 n4147 n4118 n4174 n1101 +0100- 1 +0111- 1 +1101- 1 +1110- 1 +1---1 1 +.names n3851_1 preset n4381_1 n4244 n4243 n_n7910 n1106 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4261_1 n4245 n4381_1 +01 1 +10 1 +.names n3828 preset n4187 n_n9528 n1111 +00-1 1 +101- 1 +.names n4079 preset pinp_13_13_ n_n7850 n1116 +00-1 1 +101- 1 +.names preset n3818 n_n8251 n1121 +01- 1 +0-1 1 +.names n4079 preset psv2_14_14_ n_n7937 n1126 +00-1 1 +101- 1 +.names n4079 preset pinp_15_15_ n_n8482 n1131 +00-1 1 +101- 1 +.names preset n_n9290 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1136 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv2_15_15_ n_n8007 n1141 +00-1 1 +101- 1 +.names preset n3824 n_n7556 n1146 +01- 1 +0-1 1 +.names preset ndn3_20 nsr3_20 n_n9064 n4290 n1151 +000-1 1 +01-1- 1 +0-11- 1 +.names n3827 preset n4099 n_n9398 n1156 +00-1 1 +101- 1 +.names n3816_1 preset n4081_1 n_n9412 n1161 +00-1 1 +101- 1 +.names preset n_n9361 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1166 +1----- 0 +-0---- 0 +--1100 0 +.names n3816_1 preset n4061_1 n4007 n_n9304 n1171 +00--1 1 +1001- 1 +1010- 1 +.names nsr3_30 preset n1866 +00 1 +.names preset ndn3_30 nsr3_30 n_n7651 n4397 n1176 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n8652 n3731_1 n4397 +10 1 +.names n3826_1 preset n4061_1 n4007 n_n7712 n1181 +00--1 1 +1001- 1 +1010- 1 +.names preset ndn3_30 nsr3_30 n_n7735 n4318 n1186 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_13 nsr3_13 n_n7934 n4401_1 n1191 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n8549 n3731_1 n4401_1 +10 1 +.names n3828 preset n4081_1 n_n7811 n1196 +00-1 1 +101- 1 +.names n4079 preset psv13_2_2_ n_n8053 n1201 +00-1 1 +101- 1 +.names n3837 preset n4102 n_n9015 n1206 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n8066 n4185 n1211 +000-1 1 +01-1- 1 +0-11- 1 +.names n3836_1 preset n4240 n_n9518 n1216 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n8091 n_n8466 n1221 +00-1- 1 +010-1 1 +0-11- 1 +.names preset ndn3_13 nsr3_13 n_n9257 n4409 n1226 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n9448 n3731_1 n4409 +10 1 +.names n3827 preset n_n9252 n_n8175 n1231 +00-1 1 +101- 1 +.names n4079 preset psv39_15_15_ n_n8491 n1236 +00-1 1 +101- 1 +.names n4079 preset psv13_14_14_ n_n8114 n1241 +00-1 1 +101- 1 +.names n3837 preset n4240 n_n7951 n1246 +00-1 1 +101- 1 +.names n_n8913 n4183 n4417 n4415 n4416_1 n3785 n1251 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names preset n_n8668 n4196_1 n4175 n3731_1 n4415 +000-0 1 +01-1- 1 +0-11- 1 +.names n3731_1 preset n_n9198 n4178 n_n8668 n_n9247 n4416_1 +0010-0 1 +100-0- 1 +10-00- 1 +.names n4338 n4418 n4417 +11 1 +.names n4330 n_n8561 n_n8978 n_n9034 n_n9031 n_n8993 n4418 +100000 1 +.names n3826_1 preset n4187 n_n8035 n1256 +00-1 1 +101- 1 +.names n_n8631 n4183 n4418 n4415 n4416_1 n3764 n1261 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names preset n_n8243 ngfdn_3 ndn3_50 n1266 +01-- 1 +0-10 1 +.names n3824 preset n_n7706 n_n7857 n1271 +00-1 1 +101- 1 +.names n3812 preset n4081_1 n_n7791 n1281 +00-1 1 +101- 1 +.names n3851_1 preset n4106_1 n_n9175 n1286 +00-1 1 +101- 1 +.names n3810 preset n3803 n_n9588 n1291 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n9049 n4313 n1296 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ngfdn_3 ndn3_50 n_n9483 n_n8948 n1301 +00-1- 1 +010-1 1 +0-11- 1 +.names preset n_n9410 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1306 +1----- 0 +-0---- 0 +--1100 0 +.names n3819 preset n4240 n_n7691 n1311 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n7740 n4318 n1316 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_23 nsr3_23 n_n7602 n4200 n1321 +000-1 1 +01-1- 1 +0-11- 1 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n3819 n_n8974 n1466 +01- 1 +0-1 1 +.names preset n3835 n_n7286 n1471 +01- 1 +0-1 1 +.names n4079 preset psv38_15_15_ n_n9223 n1476 +00-1 1 +101- 1 +.names n4328 preset n1481 +10 1 +.names n3835 preset n_n6974 n_n9169 n1486 +00-1 1 +101- 1 +.names n3819 preset n4099 n_n9125 n1491 +00-1 1 +101- 1 +.names ngfdn_3 preset nsr3_38 nen3_39 n1496 +000- 1 +00-1 1 +.names n4213 n4219 n_n8278 n4212 n1501 +11-- 1 +--11 1 +.names preset n_n9557 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1506 +1----- 0 +-0---- 0 +--1100 0 +.names preset ndn3_30 nsr3_30 n_n7758 n4185 n1511 +000-1 1 +01-1- 1 +0-11- 1 +.names n3835 preset n4099 n_n9391 n1516 +00-1 1 +101- 1 +.names n4079 preset pinp_10_10_ n_n8110 n1521 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n9597 n3796_1 n1526 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3818 n_n8568 n1531 +01- 1 +0-1 1 +.names n4213 n4301_1 n_n7428 n4212 n1536 +11-- 1 +--11 1 +.names n3843 preset n4381_1 n4244 n4243 n_n7931 n1541 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3850 preset n4187 n_n7742 n1546 +00-1 1 +101- 1 +.names n3816_1 preset n4242 n_n7236 n1551 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n8219 n4401_1 n1556 +000-1 1 +01-1- 1 +0-11- 1 +.names n3808 preset n4381_1 n4244 n4243 n_n9568 n1561 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset n3827 n_n9200 n1566 +01- 1 +0-1 1 +.names n4104 n4191_1 n_n8545 n4103 n1571 +11-- 1 +--11 1 +.names n3838 preset n4301_1 n_n7823 n1576 +00-1 1 +101- 1 +.names n3838 preset n4242 n_n8005 n1581 +00-1 1 +101- 1 +.names n4079 preset pinp_4_4_ n_n8736 n1586 +00-1 1 +101- 1 +.names n3827 preset n4324 n4052 n4027 n_n9339 n1591 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3836_1 preset n4187 n_n8499 n1596 +00-1 1 +101- 1 +.names n4079 preset psv33_11_11_ n_n8086 n1601 +00-1 1 +101- 1 +.names n3850 preset n4191_1 n_n7803 n1606 +00-1 1 +101- 1 +.names n3836_1 preset n4217 n3853 n_n7640 n1611 +00--1 1 +1000- 1 +1011- 1 +.names n4079 preset psv33_13_13_ n_n9098 n1616 +00-1 1 +101- 1 +.names n3798 preset n_n8906 n_n7160 n1621 +00-1 1 +101- 1 +.names n3814 preset n4061_1 n4007 n_n7713 n1626 +00--1 1 +1001- 1 +1010- 1 +.names n3814 preset n4102 n_n9566 n1631 +00-1 1 +101- 1 +.names n4079 preset psv13_8_8_ n_n7955 n1636 +00-1 1 +101- 1 +.names n4079 preset psv13_13_13_ n_n8414 n1641 +00-1 1 +101- 1 +.names n3850 preset n4242 n_n8006 n1646 +00-1 1 +101- 1 +.names preset n_n9560 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1651 +1----- 0 +-0---- 0 +--1100 0 +.names n4104 n4356_1 n_n8742 n4103 n1656 +11-- 1 +--11 1 +.names n3824 preset n_n9632 n_n7174 n1661 +00-1 1 +101- 1 +.names n4104 n4106_1 n_n8882 n4103 n1666 +11-- 1 +--11 1 +.names n3818 preset n_n9235 n_n7546 n1671 +00-1 1 +101- 1 +.names n3837 preset n4219 n_n8282 n1676 +00-1 1 +101- 1 +.names n4104 n4324 n4052 n4027 n_n8998 n4103 n1681 +101--- 1 +10-1-- 1 +1100-- 1 +----11 1 +.names n4079 preset psv26_0_0_ n_n7656 n1686 +00-1 1 +101- 1 +.names n3819 preset n_n8022 n_n9465 n1691 +00-1 1 +101- 1 +.names preset ndn3_13 nsr3_13 n_n9601 n3796_1 n1696 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n8875 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1701 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv26_8_8_ n_n7954 n1706 +00-1 1 +101- 1 +.names n3798 preset n4217 n3853 n_n8959 n1711 +00--1 1 +1000- 1 +1011- 1 +.names n3798 preset n4240 n_n8957 n1716 +00-1 1 +101- 1 +.names n3835 preset n4187 n_n8247 n1721 +00-1 1 +101- 1 +.names n3824 preset n4301_1 n_n8258 n1726 +00-1 1 +101- 1 +.names preset ndn3_23 nsr3_23 n_n7641 n4374 n1731 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_20 nsr3_20 n_n8843 n4368 n1736 +000-1 1 +01-1- 1 +0-11- 1 +.names n3850 preset n4356_1 n_n9321 n1741 +00-1 1 +101- 1 +.names preset n_n7702 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1746 +1----- 0 +-0---- 0 +--1100 0 +.names preset pdn nsr3_23 nak3_13 ndn3_19 n1751 +000-- 0 +00-11 0 +.names preset n_n8199 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1756 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n7983 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1761 +1----- 0 +-0---- 0 +--1100 0 +.names n3818 preset n4381_1 n4244 n4243 n_n7217 n1766 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3843 preset n4301_1 n_n7821 n1771 +00-1 1 +101- 1 +.names preset ndn3_30 nsr3_30 n_n9489 n3730 n1776 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n8348 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1781 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv2_3_3_ n_n9408 n1786 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n8445 n4401_1 n1791 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv13_5_5_ n_n9501 n1796 +00-1 1 +101- 1 +.names preset ndn3_30 nsr3_30 n_n7831 n4441_1 n1801 +000-1 1 +01-1- 1 +0-11- 1 +.names n3835 preset n4061_1 n4007 n_n7757 n1806 +00--1 1 +1001- 1 +1010- 1 +.names n4079 preset psv38_5_5_ n_n9174 n1811 +00-1 1 +101- 1 +.names n3819 preset n_n9036 n_n9432 n1816 +00-1 1 +101- 1 +.names n3819 preset n_n7948 n_n8678 n1821 +00-1 1 +101- 1 +.names n3835 preset n4191_1 n_n8024 n1826 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n7806 n4292 n1831 +000-1 1 +01-1- 1 +0-11- 1 +.names n3798 preset n4191_1 n_n8996 n1836 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n7918 n4185 n1841 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_13 nsr3_13 n_n8260 n4397 n1846 +000-1 1 +01-1- 1 +0-11- 1 +.names n3826_1 preset n4324 n4052 n4027 n_n9341 n1851 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset ndn3_13 nsr3_13 n_n9189 n4318 n1856 +000-1 1 +01-1- 1 +0-11- 1 +.names n3818 preset n_n8258 n_n9096 n1861 +00-1 1 +101- 1 +.names n3818 preset n_n7083 n_n7775 n1871 +00-1 1 +101- 1 +.names n3851_1 preset n4240 n_n7693 n1876 +00-1 1 +101- 1 +.names ngfdn_3 preset nsr3_14 nen3_16 n1881 +000- 1 +00-1 1 +.names n4079 preset psv33_6_6_ n_n7643 n1886 +00-1 1 +101- 1 +.names n4213 n4242 n_n8941 n4212 n1891 +11-- 1 +--11 1 +.names preset ndn3_14 nsr3_14 n_n8042 n4200 n1896 +000-1 1 +01-1- 1 +0-11- 1 +.names n3835 preset n_n8996 n_n8681 n1901 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n8659 n4368 n1906 +000-1 1 +01-1- 1 +0-11- 1 +.names n3836_1 preset n4061_1 n4007 n_n9110 n1911 +00--1 1 +1001- 1 +1010- 1 +.names n3824 preset n4099 n_n9573 n1916 +00-1 1 +101- 1 +.names n3824 preset n4106_1 n_n8951 n1921 +00-1 1 +101- 1 +.names n3835 preset n3803 n_n9589 n1926 +00-1 1 +101- 1 +.names n4079 preset psv2_11_11_ n_n9387 n1931 +00-1 1 +101- 1 +.names n4104 n4219 n_n8279 n4103 n1936 +11-- 1 +--11 1 +.names n3851_1 preset n4081_1 n_n7790 n1941 +00-1 1 +101- 1 +.names preset n3818 n_n8406 n1946 +01- 1 +0-1 1 +.names n4203 n4242 n_n8582 n4202 n1951 +11-- 1 +--11 1 +.names preset ndn3_23 nsr3_23 n_n7911 n4401_1 n1956 +000-1 1 +01-1- 1 +0-11- 1 +.names n4213 n4240 n_n7474 n4212 n1961 +11-- 1 +--11 1 +.names n3818 preset n4356_1 n_n8466 n1966 +00-1 1 +101- 1 +.names preset n3824 n_n6984 n1971 +01- 1 +0-1 1 +.names n3827 preset n4061_1 n4007 n_n7760 n1976 +00--1 1 +1001- 1 +1010- 1 +.names n3826_1 preset n4219 n_n7847 n1981 +00-1 1 +101- 1 +.names preset n_n9559 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n1986 +1----- 0 +-0---- 0 +--1100 0 +.names preset n3827 n_n7362 n1991 +01- 1 +0-1 1 +.names n4079 preset psv33_10_10_ n_n9300 n1996 +00-1 1 +101- 1 +.names preset n_n9550 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2001 +1----- 0 +-0---- 0 +--1100 0 +.names n3843 preset n4106_1 n_n9492 n2006 +00-1 1 +101- 1 +.names n3798 preset n_n8858 n_n8777 n2011 +00-1 1 +101- 1 +.names n3850 preset n4061_1 n4007 n_n7764 n2016 +00--1 1 +1001- 1 +1010- 1 +.names n4079 preset psv13_4_4_ n_n7826 n2021 +00-1 1 +101- 1 +.names n3827 preset n_n9100 n_n7777 n2026 +00-1 1 +101- 1 +.names n3837 preset n4301_1 n_n7824 n2031 +00-1 1 +101- 1 +.names preset n_n8173 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2036 +1----- 0 +-0---- 0 +--1100 0 +.names n3819 preset n_n9391 n_n7498 n2041 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n9148 n_n7606 n2046 +00-1- 1 +010-1 1 +0-11- 1 +.names n4287 preset n4240 n_n8753 n2051 +00-1 1 +101- 1 +.names n3814 preset n4381_1 n4244 n4243 n_n8772 n2056 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3819 preset n_n9589 n_n8049 n2061 +00-1 1 +101- 1 +.names preset n_n9362 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2066 +1----- 0 +-0---- 0 +--1100 0 +.names ndn1_4 pdn preset n2071 +100 1 +.names preset n_n9561 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2076 +1----- 0 +-0---- 0 +--1100 0 +.names n3818 preset n_n8951 n_n9004 n2081 +00-1 1 +101- 1 +.names n3837 preset n4061_1 n4007 n_n8203 n2086 +00--1 1 +1001- 1 +1010- 1 +.names n3837 preset n4191_1 n_n8153 n2091 +00-1 1 +101- 1 +.names n3851_1 preset n3803 n_n9263 n2096 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n8369 n_n9508 n2101 +00-1- 1 +010-1 1 +0-11- 1 +.names preset n_n9331 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2106 +1----- 0 +-0---- 0 +--1100 0 +.names n4203 n3853 n4217 n_n7454 n4202 n2111 +100-- 1 +111-- 1 +---11 1 +.names ngfdn_3 preset ndn3_7 ndn3_4 n2116 +001- 1 +00-1 1 +.names n3824 preset n4187 n_n7527 n2121 +00-1 1 +101- 1 +.names n3835 preset n4301_1 n_n9036 n2126 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n7875 n4374 n2131 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_23 nsr3_23 n_n8697 n4368 n2136 +000-1 1 +01-1- 1 +0-11- 1 +.names n3828 preset n4106_1 n_n9497 n2141 +00-1 1 +101- 1 +.names preset n3835 n_n7291 n2146 +01- 1 +0-1 1 +.names preset pdn nsr3_13 nak3_13 ndn3_12 n2151 +000-- 0 +00-11 0 +.names preset pdn nsr3_38 nak3_13 nen3_36 n2156 +000-- 0 +00-11 0 +.names preset n_n8240 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2161 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n7703 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2166 +1----- 0 +-0---- 0 +--1100 0 +.names n3818 preset n4240 n_n9282 n2171 +00-1 1 +101- 1 +.names preset n_n8237 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2176 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8935 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2181 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n9244 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2186 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8648 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2191 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8235 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2196 +1----- 0 +-0---- 0 +--1100 0 +.names n3813 preset n4381_1 n4244 n4243 n_n8611 n2201 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4079 preset psv38_1_1_ n_n9045 n2206 +00-1 1 +101- 1 +.names n3836_1 preset n4324 n4052 n4027 n_n9334 n2211 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset n_n8572 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2216 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv18_5_5_ n_n9491 n2221 +00-1 1 +101- 1 +.names n3814 preset n4099 n_n9134 n2226 +00-1 1 +101- 1 +.names preset n_n9555 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2231 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv38_9_9_ n_n9336 n2236 +00-1 1 +101- 1 +.names preset n_n7050 ngfdn_3 ndn3_50 n2241 +01-- 1 +0-10 1 +.names n3814 preset n4324 n4052 n4027 n_n9346 n2246 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset n_n7140 ngfdn_3 ndn3_50 n2251 +01-- 1 +0-10 1 +.names preset ndn3_38 nsr3_38 n_n7681 n4409 n2256 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3835 n_n6948 n2261 +01- 1 +0-1 1 +.names n_n8549 n4183 n4621_1 n4174 n2266 +011- 1 +110- 1 +1--1 1 +.names n4171_1 n4114 n_n8449 n4170 n4621_1 +000- 1 +00-1 1 +11-- 1 +1-10 1 +.names ngfdn_3 preset ndn3_19 nen3_19 n2271 +001- 1 +00-1 1 +.names ngfdn_3 preset nen3_28 ndn3_28 n2276 +001- 1 +00-1 1 +.names n3835 preset n_n9609 n_n7102 n2281 +00-1 1 +101- 1 +.names n3816_1 preset n4356_1 n_n8093 n2286 +00-1 1 +101- 1 +.names n3819 preset n4356_1 n_n9041 n2291 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n8381 n4318 n2296 +000-1 1 +01-1- 1 +0-11- 1 +.names n4203 n4099 n_n8810 n4202 n2301 +11-- 1 +--11 1 +.names ngfdn_3 preset nsr3_37 nen3_36 n2306 +000- 1 +00-1 1 +.names preset ndn3_23 nsr3_23 n_n9047 n4313 n2311 +000-1 1 +01-1- 1 +0-11- 1 +.names n3819 preset n4324 n4052 n4027 n_n9333 n2316 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3822 preset n4187 n_n7736 n2321 +00-1 1 +101- 1 +.names n3822 preset n4301_1 n_n7820 n2326 +00-1 1 +101- 1 +.names n4079 preset pinp_11_11_ n_n8986 n2331 +00-1 1 +101- 1 +.names n3822 preset n4240 n_n8891 n2336 +00-1 1 +101- 1 +.names n4079 preset pinp_14_14_ n_n8000 n2341 +00-1 1 +101- 1 +.names preset ndn3_23 nsr3_23 n_n7968 n4349 n2346 +000-1 1 +01-1- 1 +0-11- 1 +.names n3835 preset n_n7962 n_n8750 n2351 +00-1 1 +101- 1 +.names preset n_n9558 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2356 +1----- 0 +-0---- 0 +--1100 0 +.names n3827 preset n4356_1 n_n9368 n2361 +00-1 1 +101- 1 +.names n3828 preset n4242 n_n8519 n2366 +00-1 1 +101- 1 +.names preset n3818 n_n6956 n2371 +01- 1 +0-1 1 +.names n3812 preset n4187 n_n8298 n2376 +00-1 1 +101- 1 +.names n3843 preset n4099 n_n9397 n2381 +00-1 1 +101- 1 +.names n3827 preset n_n9087 n_n7017 n2386 +00-1 1 +101- 1 +.names n4079 preset psv38_2_2_ n_n8638 n2391 +00-1 1 +101- 1 +.names preset n_n9552 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2396 +1----- 0 +-0---- 0 +--1100 0 +.names n_n8964 n4649 n4416_1 n3761_1 n4651_1 n2401 +0---1 1 +10--- 1 +--10- 1 +.names n4650 n_n8668 n4196_1 n4175 preset n3731_1 n4649 +000--1 1 +01-0-- 1 +0-10-- 1 +0---1- 1 +.names n4183 n4417 n_n8913 n4650 +10- 1 +1-1 1 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1 +.names n3838 preset n4217 n3853 n_n7876 n2671 +00--1 1 +1000- 1 +1011- 1 +.names n3827 preset n3803 n_n9596 n2676 +00-1 1 +101- 1 +.names n3798 preset n_n9106 n_n8430 n2681 +00-1 1 +101- 1 +.names n4287 preset n4061_1 n4007 n_n9019 n2686 +00--1 1 +1001- 1 +1010- 1 +.names preset n3827 n_n7699 n2691 +01- 1 +0-1 1 +.names n4287 preset n4187 n_n7375 n2696 +00-1 1 +101- 1 +.names n4079 preset psv39_14_14_ n_n7936 n2701 +00-1 1 +101- 1 +.names n3824 preset n_n8468 n_n8340 n2706 +00-1 1 +101- 1 +.names n4104 n4099 n_n8809 n4103 n2711 +11-- 1 +--11 1 +.names n3819 preset n_n8989 n_n6961 n2716 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n9429 n_n7217 n2721 +00-1- 1 +010-1 1 +0-11- 1 +.names n4079 preset psv26_2_2_ n_n7743 n2726 +00-1 1 +101- 1 +.names n3810 preset n4324 n4052 n4027 n_n8980 n2731 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset n_n7582 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2736 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8968 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n2741 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nsr3_38 n_n9310 n4313 n2821 +000-1 1 +01-1- 1 +0-11- 1 +.names n3798 preset n_n7464 n_n9366 n2826 +00-1 1 +101- 1 +.names preset n3824 n_n7181 n2831 +01- 1 +0-1 1 +.names n4079 preset psv2_9_9_ n_n8739 n2836 +00-1 1 +101- 1 +.names n4287 preset n3803 n_n8939 n2841 +00-1 1 +101- 1 +.names n3824 preset n_n9171 n_n7256 n2846 +00-1 1 +101- 1 +.names n4287 preset n4324 n4052 n4027 n_n8983 n2851 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4104 n4187 n_n7487 n4103 n2856 +11-- 1 +--11 1 +.names n3814 preset n3803 n_n9268 n2861 +00-1 1 +101- 1 +.names n3813 preset n3803 n_n8906 n2866 +00-1 1 +101- 1 +.names preset ndn3_35 nsr3_35 n_n7988 n4290 n2871 +000-1 1 +01-1- 1 +0-11- 1 +.names n3808 preset n4106_1 n_n9181 n2876 +00-1 1 +101- 1 +.names preset n_n8725 ngfdn_3 ndn3_50 n2881 +01-- 1 +0-10 1 +.names n3810 preset n4219 n_n8626 n2886 +00-1 1 +101- 1 +.names ngfdn_3 preset ndn3_26 ndn3_27 n2891 +001- 1 +00-1 1 +.names preset ndn3_14 nsr3_14 n_n8210 n4397 n2896 +000-1 1 +01-1- 1 +0-11- 1 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1 +0-1 1 +.names n4079 preset psv13_9_9_ n_n7866 n3131 +00-1 1 +101- 1 +.names n3837 preset n3803 n_n9599 n3136 +00-1 1 +101- 1 +.names preset n_n7635 ngfdn_3 ndn3_50 n3141 +01-- 1 +0-10 1 +.names n3837 preset n4324 n4052 n4027 n_n8984 n3146 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3827 preset n_n7756 n_n7360 n3151 +00-1 1 +101- 1 +.names n3813 preset n4099 n_n8794 n3156 +00-1 1 +101- 1 +.names n3810 preset n4381_1 n4244 n4243 n_n9108 n3161 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4104 n4240 n_n9286 n4103 n3166 +11-- 1 +--11 1 +.names ngfdn_3 preset ndn3_12 ndn3_11 n3171 +001- 1 +00-1 1 +.names ngfdn_3 preset ndn3_16 nen3_16 n3176 +001- 1 +00-1 1 +.names n3809 preset n4061_1 n4007 n_n7708 n3181 +00--1 1 +1001- 1 +1010- 1 +.names preset ndn3_35 nsr3_35 n_n7807 n4292 n3186 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_35 nsr3_35 n_n7650 n4397 n3191 +000-1 1 +01-1- 1 +0-11- 1 +.names n3810 preset n4240 n_n7947 n3196 +00-1 1 +101- 1 +.names n4079 preset psv26_5_5_ n_n9500 n3201 +00-1 1 +101- 1 +.names preset ndn3_35 nsr3_35 n_n7734 n4318 n3206 +000-1 1 +01-1- 1 +0-11- 1 +.names n3816_1 preset n4099 n_n8464 n3211 +00-1 1 +101- 1 +.names preset n3819 n_n7659 n3216 +01- 1 +0-1 1 +.names preset n_n7630 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3221 +1----- 0 +-0---- 0 +--1100 0 +.names n3816_1 preset n4324 n4052 n4027 n_n7756 n3226 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset n_n8691 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3231 +1----- 0 +-0---- 0 +--1100 0 +.names preset ndn3_23 nsr3_23 n_n9176 n3730 n3236 +000-1 1 +01-1- 1 +0-11- 1 +.names n3822 preset n4217 n3853 n_n9327 n3241 +00--1 1 +1000- 1 +1011- 1 +.names n3809 preset n4102 n_n7995 n3246 +00-1 1 +101- 1 +.names n3835 preset n_n8206 n_n7395 n3251 +00-1 1 +101- 1 +.names n3828 preset n4217 n3853 n_n7878 n3256 +00--1 1 +1000- 1 +1011- 1 +.names preset n3798 n_n7507 n3261 +01- 1 +0-1 1 +.names preset n3818 n_n7959 n3266 +01- 1 +0-1 1 +.names n3850 preset n4301_1 n_n7825 n3271 +00-1 1 +101- 1 +.names n4079 preset pinp_2_2_ n_n8009 n3276 +00-1 1 +101- 1 +.names n4287 preset n4219 n_n8281 n3281 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n7685 n4409 n3286 +000-1 1 +01-1- 1 +0-11- 1 +.names n3828 preset n4381_1 n4244 n4243 n_n8106 n3291 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3828 preset n4191_1 n_n7687 n3296 +00-1 1 +101- 1 +.names n4079 preset psv13_11_11_ n_n7766 n3301 +00-1 1 +101- 1 +.names n4079 preset psv13_6_6_ n_n7880 n3306 +00-1 1 +101- 1 +.names n3814 preset n4217 n3853 n_n8961 n3311 +00--1 1 +1000- 1 +1011- 1 +.names n3814 preset n4242 n_n8014 n3316 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n9278 n_n7781 n3321 +00-1- 1 +010-1 1 +0-11- 1 +.names n3816_1 preset n4102 n_n9087 n3326 +00-1 1 +101- 1 +.names n4079 preset psv33_5_5_ n_n9182 n3331 +00-1 1 +101- 1 +.names preset n_n7852 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3336 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv39_1_1_ n_n9324 n3341 +00-1 1 +101- 1 +.names preset n4196_1 n3346 +00 1 +.names n_n9416 n4183 n4144 n4845 n4174 n3351 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n4147 n_n9434 n4118 n4845 +10- 1 +1-0 1 +-00 1 +.names nsr3_14 preset n5961 +00 1 +.names preset pdn nsr3_14 nak3_13 nsr3_13 n3356 +000-- 0 +00-10 0 +.names n_n8603 n4415 n4416_1 n3771_1 n4183 n3361 +01--- 0 +1---1 0 +--10- 0 +.names preset n_n7026 ngfdn_3 ndn3_50 n3366 +01-- 1 +0-10 1 +.names n3827 preset n4217 n3853 n_n8856 n3371 +00--1 1 +1000- 1 +1011- 1 +.names preset n_n8272 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3376 +1----- 0 +-0---- 0 +--1100 0 +.names preset ndn3_30 nsr3_30 n_n9312 n4313 n3381 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n7985 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3386 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8312 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3391 +1----- 0 +-0---- 0 +--1100 0 +.names n3827 preset n_n8093 n_n7231 n3396 +00-1 1 +101- 1 +.names n4079 preset psv18_3_3_ n_n9396 n3401 +00-1 1 +101- 1 +.names n3819 preset n_n8247 n_n8801 n3406 +00-1 1 +101- 1 +.names preset n3835 n_n8683 n3411 +01- 1 +0-1 1 +.names ngfdn_3 preset ndn3_39 nen3_39 n3416 +001- 1 +00-1 1 +.names preset n3835 n_n8245 n3421 +01- 1 +0-1 1 +.names n3810 preset n4217 n3853 n_n9458 n3426 +00--1 1 +1000- 1 +1011- 1 +.names n4079 preset psv33_8_8_ n_n9302 n3431 +00-1 1 +101- 1 +.names n3827 preset n_n9586 n_n7392 n3436 +00-1 1 +101- 1 +.names n3835 preset n_n9155 n_n6963 n3441 +00-1 1 +101- 1 +.names preset ndn3_30 nsr3_30 n_n7808 n4292 n3446 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_20 nsr3_20 n_n7225 n4441_1 n3451 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv2_12_12_ n_n7817 n3456 +00-1 1 +101- 1 +.names n4213 n4061_1 n4007 n_n8201 n4212 n3461 +101-- 1 +110-- 1 +---11 1 +.names n3808 preset n4081_1 n_n7793 n3466 +00-1 1 +101- 1 +.names n4213 n4191_1 n_n8177 n4212 n3471 +11-- 1 +--11 1 +.names preset n3827 n_n8389 n3476 +01- 1 +0-1 1 +.names preset n_n9440 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3481 +1----- 0 +-0---- 0 +--1100 0 +.names n3843 preset n4191_1 n_n7683 n3486 +00-1 1 +101- 1 +.names preset ndn3_20 nsr3_20 n_n7761 n4185 n3491 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_23 nsr3_23 n_n7667 n4409 n3496 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_30 nsr3_30 n_n7980 n4374 n3501 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv38_0_0_ n_n7509 n3506 +00-1 1 +101- 1 +.names n3850 preset n4081_1 n_n7813 n3511 +00-1 1 +101- 1 +.names preset ndn3_13 nsr3_13 n_n8396 n4185 n3516 +000-1 1 +01-1- 1 +0-11- 1 +.names n3819 preset n_n9309 n_n9535 n3521 +00-1 1 +101- 1 +.names preset n_n7209 ngfdn_3 ndn3_50 n3526 +01-- 1 +0-10 1 +.names preset n_n7003 ngfdn_3 ndn3_50 n3531 +01-- 1 +0-10 1 +.names n3814 preset n4240 n_n7695 n3536 +00-1 1 +101- 1 +.names n3813 preset n4217 n3853 n_n7624 n3541 +00--1 1 +1000- 1 +1011- 1 +.names n3808 preset n4301_1 n_n8791 n3546 +00-1 1 +101- 1 +.names n4203 n4187 n_n7374 n4202 n3551 +11-- 1 +--11 1 +.names n4203 n4301_1 n_n7429 n4202 n3556 +11-- 1 +--11 1 +.names preset n3818 n_n7944 n3561 +01- 1 +0-1 1 +.names preset ndn3_14 nsr3_14 n_n9266 n3796_1 n3566 +000-1 1 +01-1- 1 +0-11- 1 +.names n3798 preset n_n8871 n_n8100 n3571 +00-1 1 +101- 1 +.names preset n_n6988 ngfdn_3 ndn3_50 n3576 +01-- 1 +0-10 1 +.names preset n3798 n_n6986 n3581 +01- 1 +0-1 1 +.names n_n8933 n4183 n4332 n4415 n4416_1 n3791_1 n3586 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names preset n3798 n_n7117 n3591 +01- 1 +0-1 1 +.names preset nsr3_37 ndn3_37 n_n9043 n4313 n3596 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n8241 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3601 +1----- 0 +-0---- 0 +--1100 0 +.names n3818 preset n4301_1 n_n9219 n3606 +00-1 1 +101- 1 +.names preset n_n8198 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3611 +1----- 0 +-0---- 0 +--1100 0 +.names n3818 preset n4242 n_n8081 n3616 +00-1 1 +101- 1 +.names preset n_n8575 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3621 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n8710 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3626 +1----- 0 +-0---- 0 +--1100 0 +.names preset n3827 n_n7622 n3631 +01- 1 +0-1 1 +.names preset nsr3_37 ndn3_37 n_n7966 n4349 n3636 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_38 nsr3_38 n_n7885 n4290 n3641 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3824 n_n7033 n3646 +01- 1 +0-1 1 +.names ngfdn_3 preset nen3_34 ndn3_34 n3651 +001- 1 +00-1 1 +.names preset ndn3_13 nsr3_13 n_n9186 n4200 n3656 +000-1 1 +01-1- 1 +0-11- 1 +.names ndn3_50 ngfdn_3 preset n3661 +100 1 +.names preset ndn3_13 nsr3_13 n_n7879 n4374 n3666 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3819 n_n7019 n3671 +01- 1 +0-1 1 +.names n3819 preset n4106_1 n_n9171 n3676 +00-1 1 +101- 1 +.names preset n3818 n_n7261 n3681 +01- 1 +0-1 1 +.names n3836_1 preset n4081_1 n_n8223 n3686 +00-1 1 +101- 1 +.names n3835 preset n4324 n4052 n4027 n_n8989 n3691 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3809 preset n4187 n_n7993 n3696 +00-1 1 +101- 1 +.names n3851_1 preset n4219 n_n7845 n3701 +00-1 1 +101- 1 +.names n3809 preset n4301_1 n_n8253 n3706 +00-1 1 +101- 1 +.names n3822 preset n4191_1 n_n8889 n3711 +00-1 1 +101- 1 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1 +.names n3798 preset n4187 n_n9576 n3791 +00-1 1 +101- 1 +.names n3816_1 preset n4301_1 n_n9252 n3796 +00-1 1 +101- 1 +.names preset n_n9363 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3801 +1----- 0 +-0---- 0 +--1100 0 +.names ngfdn_3 preset ndn3_2 ndn3_4 n3806 +001- 1 +00-1 1 +.names n4327 preset n4176_1 n_n9247 n3811 +101- 1 +10-1 1 +.names preset n3818 n_n7561 n3816 +01- 1 +0-1 1 +.names n_n8923 n4183 n_n8603 n_n8798 n4941_1 n4415 n3821 +0110-- 1 +110--- 1 +11-1-- 1 +1----1 1 +----1- 1 +.names n4416_1 n3788 n4941_1 +10 1 +.names preset n3798 n_n7978 n3826 +01- 1 +0-1 1 +.names n_n8978 n4183 n4330 n4415 n4416_1 n3778 n3831 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names n3850 preset n4106_1 n_n9499 n3836 +00-1 1 +101- 1 +.names preset n3824 n_n8713 n3841 +01- 1 +0-1 1 +.names preset n3824 n_n8944 n3846 +01- 1 +0-1 1 +.names preset n_n8239 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3851 +1----- 0 +-0---- 0 +--1100 0 +.names n3843 preset n4102 n_n7652 n3856 +00-1 1 +101- 1 +.names n3836_1 preset n4356_1 n_n9042 n3861 +00-1 1 +101- 1 +.names preset n_n8530 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3866 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset pinp_7_7_ n_n9271 n3871 +00-1 1 +101- 1 +.names n3837 preset n4356_1 n_n9318 n3876 +00-1 1 +101- 1 +.names n3819 preset n4061_1 n4007 n_n7706 n3881 +00--1 1 +1001- 1 +1010- 1 +.names n3824 preset n_n9041 n_n7964 n3886 +00-1 1 +101- 1 +.names n3810 preset n4081_1 n_n8222 n3891 +00-1 1 +101- 1 +.names n3810 preset n4301_1 n_n8898 n3896 +00-1 1 +101- 1 +.names n3818 preset n_n8765 n_n7976 n3901 +00-1 1 +101- 1 +.names n3851_1 preset n4217 n3853 n_n7649 n3906 +00--1 1 +1000- 1 +1011- 1 +.names n4079 preset psv33_4_4_ n_n7604 n3911 +00-1 1 +101- 1 +.names preset n_n7961 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3916 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv26_9_9_ n_n7424 n3921 +00-1 1 +101- 1 +.names preset nsr1_2 nlc1_2 n_n7476 preset_0_0_ n3926 +00-1- 1 +010-0 1 +0-11- 1 +.names n3819 preset n3803 n_n9259 n3931 +00-1 1 +101- 1 +.names n3835 preset n4356_1 n_n9309 n3936 +00-1 1 +101- 1 +.names preset n_n9161 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n3941 +01---- 1 +0-1100 1 +.names n3824 preset n4324 n4052 n4027 n_n8436 n3946 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4079 preset psv39_6_6_ n_n9121 n3951 +00-1 1 +101- 1 +.names n3835 preset n_n9104 n_n8061 n3956 +00-1 1 +101- 1 +.names n3827 preset n4242 n_n8004 n3961 +00-1 1 +101- 1 +.names preset n_n9360 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3966 +1----- 0 +-0---- 0 +--1100 0 +.names n4104 n4081_1 n_n9205 n4103 n3971 +11-- 1 +--11 1 +.names preset n3835 n_n8392 n3976 +01- 1 +0-1 1 +.names n_n9034 n4415 n4416_1 n3734 n4183 n4334 n3981 +11---- 1 +--10-- 1 +----10 1 +.names n3850 preset n4240 n_n8375 n3986 +00-1 1 +101- 1 +.names preset nsr3_37 ndn3_37 n_n8328 n4374 n3991 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n9298 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n3996 +1----- 0 +-0---- 0 +--1100 0 +.names n3836_1 preset n4301_1 n_n7598 n4001 +00-1 1 +101- 1 +.names n4079 preset psv39_11_11_ n_n8506 n4006 +00-1 1 +101- 1 +.names n4079 preset psv18_2_2_ n_n7737 n4011 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n7420 n_n7558 n4016 +00-1- 1 +010-1 1 +0-11- 1 +.names preset n_n9291 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4021 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv26_14_14_ n_n7946 n4026 +00-1 1 +101- 1 +.names n3837 preset n4242 n_n8584 n4031 +00-1 1 +101- 1 +.names n3810 preset n4356_1 n_n9308 n4036 +00-1 1 +101- 1 +.names preset ndn3_13 nsr3_13 n_n9403 n4207 n4041 +000-1 1 +01-1- 1 +0-11- 1 +.names n3824 preset n_n7898 n_n7284 n4046 +00-1 1 +101- 1 +.names n4079 preset psv33_7_7_ n_n9270 n4051 +00-1 1 +101- 1 +.names n3798 preset n_n7334 n_n7390 n4056 +00-1 1 +101- 1 +.names n3816_1 preset n4240 n_n9351 n4061 +00-1 1 +101- 1 +.names preset ndn3_35 nsr3_35 n_n6968 n4441_1 n4066 +000-1 1 +01-1- 1 +0-11- 1 +.names n_n8668 n4195 n4071 +11 1 +.names n4079 preset psv39_7_7_ n_n9605 n4076 +00-1 1 +101- 1 +.names preset n3818 n_n7013 n4081 +01- 1 +0-1 1 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1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset ndn3_20 nsr3_20 n_n8064 n4349 n4226 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n9162 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n4231 +01---- 1 +0-1100 1 +.names n3808 preset n4242 n_n7971 n4236 +00-1 1 +101- 1 +.names preset n3818 n_n8055 n4241 +01- 1 +0-1 1 +.names preset ndn3_23 nsr3_23 n_n7711 n4185 n4246 +000-1 1 +01-1- 1 +0-11- 1 +.names n3818 preset n3803 n_n8256 n4251 +00-1 1 +101- 1 +.names preset ndn3_30 nsr3_30 n_n7925 n4200 n4256 +000-1 1 +01-1- 1 +0-11- 1 +.names n3838 preset n4061_1 n4007 n_n7762 n4261 +00--1 1 +1001- 1 +1010- 1 +.names n3814 preset n4191_1 n_n7668 n4266 +00-1 1 +101- 1 +.names n4079 preset psv33_14_14_ n_n7914 n4271 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n7873 n4374 n4276 +000-1 1 +01-1- 1 +0-11- 1 +.names n3814 preset n4219 n_n7849 n4281 +00-1 1 +101- 1 +.names n3824 preset n_n7691 n_n9421 n4286 +00-1 1 +101- 1 +.names n3813 preset n4301_1 n_n7626 n4291 +00-1 1 +101- 1 +.names n3812 preset n4219 n_n7848 n4296 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n8263 n_n8081 n4301 +00-1- 1 +010-1 1 +0-11- 1 +.names n3816_1 preset n4187 n_n9100 n4306 +00-1 1 +101- 1 +.names preset ndn3_35 nsr3_35 n_n9393 n4207 n4311 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ndn3_35 nsr3_35 n_n9591 n3796_1 n4316 +000-1 1 +01-1- 1 +0-11- 1 +.names n4203 n4240 n_n7588 n4202 n4321 +11-- 1 +--11 1 +.names preset n_n9123 ngfdn_3 ndn3_50 n4326 +01-- 1 +0-10 1 +.names n3822 preset n4324 n4052 n4027 n_n9159 n4331 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3809 preset n4099 n_n9128 n4336 +00-1 1 +101- 1 +.names n3835 preset n_n7136 n_n8045 n4341 +00-1 1 +101- 1 +.names n3827 preset n4102 n_n7728 n4346 +00-1 1 +101- 1 +.names preset n4197 n_n8929 n4351 +01- 1 +0-1 1 +.names n3827 preset n4187 n_n7739 n4356 +00-1 1 +101- 1 +.names n3835 preset n4242 n_n9355 n4361 +00-1 1 +101- 1 +.names preset ndn3_30 nsr3_30 n_n9394 n4207 n4366 +000-1 1 +01-1- 1 +0-11- 1 +.names n3819 preset n4219 n_n8470 n4371 +00-1 1 +101- 1 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1 +--11 1 +.names n4104 n4381_1 n4244 n4243 n_n9203 n4103 n4446 +101--- 1 +10-1-- 1 +1100-- 1 +----11 1 +.names n3850 preset n4102 n_n7655 n4451 +00-1 1 +101- 1 +.names preset n3798 n_n8946 n4456 +01- 1 +0-1 1 +.names preset n3824 n_n7052 n4461 +01- 1 +0-1 1 +.names n4104 n4061_1 n4007 n_n9615 n4103 n4466 +101-- 1 +110-- 1 +---11 1 +.names n3843 preset n4081_1 n_n8473 n4471 +00-1 1 +101- 1 +.names n3838 preset n4187 n_n7741 n4476 +00-1 1 +101- 1 +.names n3816_1 preset n4219 n_n9460 n4481 +00-1 1 +101- 1 +.names n3826_1 preset n4381_1 n4244 n4243 n_n7912 n4486 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3818 preset n4106_1 n_n7606 n4491 +00-1 1 +101- 1 +.names n3838 preset n4240 n_n9021 n4496 +00-1 1 +101- 1 +.names n3818 preset n4324 n4052 n4027 n_n7781 n4501 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3838 preset n4081_1 n_n7810 n4506 +00-1 1 +101- 1 +.names n3798 preset n_n8794 n_n7108 n4511 +00-1 1 +101- 1 +.names n4079 preset pinp_8_8_ n_n7697 n4516 +00-1 1 +101- 1 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ndn3_13 nsr3_13 n_n9320 n4313 n4586 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3798 n_n7411 n4591 +01- 1 +0-1 1 +.names n3851_1 preset n4099 n_n9129 n4596 +00-1 1 +101- 1 +.names n4079 preset psv33_1_1_ n_n9053 n4601 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n7069 n_n7324 n4606 +00-1- 1 +010-1 1 +0-11- 1 +.names n4079 preset psv26_4_4_ n_n8617 n4611 +00-1 1 +101- 1 +.names preset n3819 n_n7242 n4616 +01- 1 +0-1 1 +.names preset n3819 n_n8230 n4621 +01- 1 +0-1 1 +.names preset n_n9294 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4626 +1----- 0 +-0---- 0 +--1100 0 +.names n3835 preset n4102 n_n8249 n4631 +00-1 1 +101- 1 +.names preset n_n8972 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4636 +1----- 0 +-0---- 0 +--1100 0 +.names n3819 preset n_n9355 n_n7074 n4641 +00-1 1 +101- 1 +.names preset n_n7493 ngfdn_3 ndn3_50 n4646 +01-- 1 +0-10 1 +.names preset n_n8290 ngfdn_3 ndn3_50 n4651 +01-- 1 +0-10 1 +.names n_n8821 n4183 n5110 n4174 n4656 +011- 1 +110- 1 +1--1 1 +.names n4151_1 n4117 n_n9537 n4150 n5110 +000- 1 +00-1 1 +11-- 1 +1-10 1 +.names preset n_n7769 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4661 +1----- 0 +-0---- 0 +--1100 0 +.names preset n3824 n_n7491 n4666 +01- 1 +0-1 1 +.names n3828 preset n3803 n_n9600 n4671 +00-1 1 +101- 1 +.names n3838 preset n4356_1 n_n9317 n4676 +00-1 1 +101- 1 +.names preset n3798 n_n8047 n4681 +01- 1 +0-1 1 +.names n3824 preset n4242 n_n9629 n4686 +00-1 1 +101- 1 +.names n3836_1 preset n4099 n_n9126 n4691 +00-1 1 +101- 1 +.names n3818 preset n4081_1 n_n9508 n4696 +00-1 1 +101- 1 +.names n3798 preset n4061_1 n4007 n_n9155 n4701 +00--1 1 +1001- 1 +1010- 1 +.names preset n_n8528 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4706 +1----- 0 +-0---- 0 +--1100 0 +.names ngfdn_3 preset ndn3_40 ndn3_42 n4716 +001- 1 +00-1 1 +.names preset n_n9358 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4721 +1----- 0 +-0---- 0 +--1100 0 +.names n3827 preset n_n9304 n_n8185 n4726 +00-1 1 +101- 1 +.names ngfdn_3 preset nsr3_30 nen3_28 n4731 +000- 1 +00-1 1 +.names n3822 preset n4242 n_n8839 n4736 +00-1 1 +101- 1 +.names preset n3819 n_n7903 n4741 +01- 1 +0-1 1 +.names n4203 n3803 n_n9139 n4202 n4746 +11-- 1 +--11 1 +.names n3822 preset n4102 n_n9075 n4751 +00-1 1 +101- 1 +.names preset n_n9439 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4756 +1----- 0 +-0---- 0 +--1100 0 +.names n_n9353 n4183 n4126_1 n4123 n4174 n4761 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n4079 preset psv38_10_10_ n_n7665 n4766 +00-1 1 +101- 1 +.names n_n8798 n4183 n_n8603 n4415 n4416_1 n3748 n4771 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names preset n3824 n_n7146 n4776 +01- 1 +0-1 1 +.names n4079 preset psv2_13_13_ n_n7890 n4781 +00-1 1 +101- 1 +.names preset n3818 n_n7176 n4786 +01- 1 +0-1 1 +.names preset nsr3_37 ndn3_37 n_n8477 n4397 n4791 +000-1 1 +01-1- 1 +0-11- 1 +.names n4203 n4381_1 n4244 n4243 n_n8514 n4202 n4796 +101--- 1 +10-1-- 1 +1100-- 1 +----11 1 +.names preset nsr3_37 ndn3_37 n_n8636 n4318 n4801 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3798 n_n7183 n4806 +01- 1 +0-1 1 +.names preset ndn3_20 nsr3_20 n_n8657 n4292 n4811 +000-1 1 +01-1- 1 +0-11- 1 +.names n3827 preset n4106_1 n_n9493 n4816 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n7969 n4349 n4821 +000-1 1 +01-1- 1 +0-11- 1 +.names n3816_1 preset n4191_1 n_n9255 n4826 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n8535 n4401_1 n4831 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv13_0_0_ n_n8619 n4836 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n8909 n4290 n4841 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv2_2_2_ n_n7744 n4846 +00-1 1 +101- 1 +.names n4079 preset psv13_10_10_ n_n9119 n4851 +00-1 1 +101- 1 +.names n4079 preset psv2_4_4_ n_n7827 n4856 +00-1 1 +101- 1 +.names n3824 preset n_n8670 n_n8916 n4861 +00-1 1 +101- 1 +.names n4287 preset n4301_1 n_n8729 n4866 +00-1 1 +101- 1 +.names n_n9011 n4651_1 n_n8964 n5153 n4649 n4871 +010-- 1 +111-- 1 +1---0 1 +---1- 1 +.names n4416_1 n3755 n5153 +10 1 +.names n4079 preset psv38_6_6_ n_n8779 n4876 +00-1 1 +101- 1 +.names n3827 preset n_n9273 n_n6980 n4881 +00-1 1 +101- 1 +.names n3819 preset n_n9486 n_n7715 n4886 +00-1 1 +101- 1 +.names n4079 preset psv26_13_13_ n_n9067 n4891 +00-1 1 +101- 1 +.names preset n_n9164 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n4896 +01---- 1 +0-1100 1 +.names n3824 preset n_n9635 n_n7402 n4901 +00-1 1 +101- 1 +.names n4104 n3803 n_n8938 n4103 n4906 +11-- 1 +--11 1 +.names n3851_1 preset n4356_1 n_n9046 n4911 +00-1 1 +101- 1 +.names n3808 preset n4217 n3853 n_n8789 n4916 +00--1 1 +1000- 1 +1011- 1 +.names n3810 preset n4099 n_n9390 n4921 +00-1 1 +101- 1 +.names preset n_n7768 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n4926 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv33_3_3_ n_n9136 n4931 +00-1 1 +101- 1 +.names n3819 preset n4102 n_n8670 n4936 +00-1 1 +101- 1 +.names n3798 preset n_n8543 n_n8644 n4941 +00-1 1 +101- 1 +.names preset ndn3_14 nsr3_14 n_n9178 n3730 n4946 +000-1 1 +01-1- 1 +0-11- 1 +.names n3819 preset n4217 n3853 n_n8188 n4951 +00--1 1 +1000- 1 +1011- 1 +.names n3824 preset n4102 n_n7083 n4956 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ndn3_42 n5036 +001- 1 +00-1 1 +.names n4079 preset psv26_1_1_ n_n9322 n5041 +00-1 1 +101- 1 +.names preset ndn3_35 nsr3_35 n_n7682 n4409 n5046 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv26_7_7_ n_n9603 n5051 +00-1 1 +101- 1 +.names pdn preset nsr1_2 nlc1_2 n5056 +001- 1 +00-1 1 +.names n4079 preset psv18_12_12_ n_n8408 n5061 +00-1 1 +101- 1 +.names preset n_n8577 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5066 +1----- 0 +-0---- 0 +--1100 0 +.names preset n3819 n_n7079 n5071 +01- 1 +0-1 1 +.names n4213 n4102 n_n8828 n4212 n5076 +11-- 1 +--11 1 +.names preset ndn3_23 nsr3_23 n_n9340 n4441_1 n5081 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv18_10_10_ n_n8586 n5086 +00-1 1 +101- 1 +.names n3808 preset n4061_1 n4007 n_n7901 n5091 +00--1 1 +1001- 1 +1010- 1 +.names n3836_1 preset n4191_1 n_n8628 n5096 +00-1 1 +101- 1 +.names n_n8869 n4183 n4333 n4415 n4416_1 n3751_1 n5101 +011--- 1 +110--- 1 +1--1-- 1 +----10 1 +.names n3851_1 preset n4061_1 n4007 n_n7710 n5106 +00--1 1 +1001- 1 +1010- 1 +.names n_n8993 n4415 n4416_1 n3775 n4183 n4336_1 n5111 +11---- 1 +--10-- 1 +----10 1 +.names n3816_1 preset n4381_1 n4244 n4243 n_n9586 n5116 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3843 preset n4061_1 n4007 n_n8852 n5121 +00--1 1 +1001- 1 +1010- 1 +.names n4287 preset n4242 n_n8583 n5126 +00-1 1 +101- 1 +.names n4079 preset pinp_0_0_ n_n8011 n5131 +00-1 1 +101- 1 +.names preset n3798 n_n7717 n5136 +01- 1 +0-1 1 +.names preset nsr3_37 ndn3_37 n_n8326 n4368 n5141 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n9163 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n5146 +01---- 1 +0-1100 1 +.names preset ndn3_13 nsr3_13 n_n8344 n4349 n5151 +000-1 1 +01-1- 1 +0-11- 1 +.names n3812 preset n4301_1 n_n8296 n5156 +00-1 1 +101- 1 +.names n4079 preset psv39_10_10_ n_n8116 n5161 +00-1 1 +101- 1 +.names n4079 preset psv33_12_12_ n_n8267 n5166 +00-1 1 +101- 1 +.names n3838 preset n4191_1 n_n7686 n5171 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n9061 n4397 n5176 +000-1 1 +01-1- 1 +0-11- 1 +.names n3843 preset n4324 n4052 n4027 n_n9338 n5181 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4079 preset psv26_10_10_ n_n7688 n5186 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n9081 n4200 n5191 +000-1 1 +01-1- 1 +0-11- 1 +.names n3824 preset n_n9239 n_n6910 n5196 +00-1 1 +101- 1 +.names n4287 preset n4217 n3853 n_n8727 n5201 +00--1 1 +1000- 1 +1011- 1 +.names n3824 preset n_n9237 n_n7674 n5206 +00-1 1 +101- 1 +.names preset n3798 n_n7330 n5211 +01- 1 +0-1 1 +.names n4079 preset psv18_8_8_ n_n8966 n5216 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n7843 n_n8256 n5221 +00-1- 1 +010-1 1 +0-11- 1 +.names n_n8847 n4183 n4418 n_n8631 n5225 n4415 n5226 +0110-- 1 +110--- 1 +11-1-- 1 +1----1 1 +----1- 1 +.names n4416_1 n3782 n5225 +10 1 +.names n3818 preset n_n8436 n_n9376 n5231 +00-1 1 +101- 1 +.names n3808 preset n4187 n_n7553 n5236 +00-1 1 +101- 1 +.names preset n_n9292 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5241 +1----- 0 +-0---- 0 +--1100 0 +.names n3813 preset n4240 n_n7464 n5246 +00-1 1 +101- 1 +.names n3819 preset n_n8024 n_n8146 n5251 +00-1 1 +101- 1 +.names n3819 preset n_n7757 n_n8439 n5256 +00-1 1 +101- 1 +.names preset ndn3_13 nsr3_13 n_n9498 n3730 n5261 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n8118 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5266 +1----- 0 +-0---- 0 +--1100 0 +.names n3798 preset n4102 n_n9452 n5271 +00-1 1 +101- 1 +.names n3819 preset n4187 n_n9239 n5276 +00-1 1 +101- 1 +.names n3819 preset n4301_1 n_n9237 n5281 +00-1 1 +101- 1 +.names preset ndn3_35 nsr3_35 n_n9488 n3730 n5286 +000-1 1 +01-1- 1 +0-11- 1 +.names ngfdn_3 preset n5239 n5291 +000 1 +.names ndn3_2 nlc1_2 nsr1_2 n_n7476 preset_0_0_ n5239 +00--1 1 +01-0- 1 +0-0-- 1 +.names preset ndn3_23 nsr3_23 n_n9522 n4397 n5296 +000-1 1 +01-1- 1 +0-11- 1 +.names n3822 preset n4356_1 n_n9313 n5301 +00-1 1 +101- 1 +.names n3819 preset n_n7927 n_n7435 n5306 +00-1 1 +101- 1 +.names preset n_n8665 ngfdn_3 ndn3_50 n5311 +01-- 1 +0-10 1 +.names n3822 preset n3803 n_n9593 n5316 +00-1 1 +101- 1 +.names n3835 preset n_n8957 n_n8303 n5321 +00-1 1 +101- 1 +.names n3835 preset n_n8959 n_n7022 n5326 +00-1 1 +101- 1 +.names n3809 preset n4106_1 n_n9173 n5331 +00-1 1 +101- 1 +.names n3809 preset n3803 n_n9261 n5336 +00-1 1 +101- 1 +.names preset n3835 n_n7150 n5341 +01- 1 +0-1 1 +.names n3809 preset n4324 n4052 n4027 n_n9455 n5346 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3835 preset n_n9452 n_n8371 n5351 +00-1 1 +101- 1 +.names preset pdn nsr3_20 nak3_13 ndn3_17 n5356 +000-- 0 +00-11 0 +.names preset n_n8271 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5361 +1----- 0 +-0---- 0 +--1100 0 +.names n3798 preset n4242 n_n9542 n5366 +00-1 1 +101- 1 +.names n3824 preset n4381_1 n4244 n4243 n_n7444 n5371 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names ngfdn_3 preset ndn3_39 ndn3_40 n5376 +001- 1 +00-1 1 +.names n3818 preset n_n7527 n_n7130 n5381 +00-1 1 +101- 1 +.names n3808 preset n4324 n4052 n4027 n_n9347 n5386 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3835 preset n_n9542 n_n8102 n5391 +00-1 1 +101- 1 +.names n4079 preset psv38_13_13_ n_n9225 n5396 +00-1 1 +101- 1 +.names n3816_1 preset n4106_1 n_n8462 n5401 +00-1 1 +101- 1 +.names n4079 preset psv38_12_12_ n_n8088 n5406 +00-1 1 +101- 1 +.names n3827 preset n_n7236 n_n9026 n5411 +00-1 1 +101- 1 +.names preset n_n9289 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5416 +1----- 0 +-0---- 0 +--1100 0 +.names n3828 preset n4102 n_n7661 n5421 +00-1 1 +101- 1 +.names n4079 preset pinp_12_12_ n_n8108 n5426 +00-1 1 +101- 1 +.names preset n3824 n_n8921 n5431 +01- 1 +0-1 1 +.names n3822 preset n4081_1 n_n7859 n5436 +00-1 1 +101- 1 +.names preset ndn3_30 nsr3_30 n_n7732 n4409 n5441 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv39_8_8_ n_n7956 n5446 +00-1 1 +101- 1 +.names n3827 preset n4219 n_n9520 n5451 +00-1 1 +101- 1 +.names n3851_1 preset n4191_1 n_n7666 n5456 +00-1 1 +101- 1 +.names n3835 preset n_n7862 n_n7678 n5461 +00-1 1 +101- 1 +.names preset ndn3_23 nsr3_23 n_n7846 n4290 n5466 +000-1 1 +01-1- 1 +0-11- 1 +.names n4203 n4219 n_n8280 n4202 n5471 +11-- 1 +--11 1 +.names preset ndn3_23 nsr3_23 n_n8841 n4292 n5476 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3818 n_n7336 n5481 +01- 1 +0-1 1 +.names n4287 preset n4081_1 n_n8226 n5486 +00-1 1 +101- 1 +.names n4203 n4191_1 n_n8151 n4202 n5491 +11-- 1 +--11 1 +.names n4079 preset pinp_6_6_ n_n7644 n5496 +00-1 1 +101- 1 +.names n4079 preset psv2_0_0_ n_n8770 n5501 +00-1 1 +101- 1 +.names preset n3827 n_n8423 n5506 +01- 1 +0-1 1 +.names n3828 preset n4061_1 n4007 n_n7763 n5511 +00--1 1 +1001- 1 +1010- 1 +.names preset ndn3_14 nsr3_14 n_n9525 n4292 n5516 +000-1 1 +01-1- 1 +0-11- 1 +.names n4079 preset psv18_0_0_ n_n8033 n5521 +00-1 1 +101- 1 +.names n4079 preset psv2_6_6_ n_n7881 n5526 +00-1 1 +101- 1 +.names n4079 preset psv13_12_12_ n_n7815 n5531 +00-1 1 +101- 1 +.names n4079 preset psv18_4_4_ n_n9232 n5536 +00-1 1 +101- 1 +.names n3814 preset n4081_1 n_n7792 n5541 +00-1 1 +101- 1 +.names n3814 preset n4187 n_n9563 n5546 +00-1 1 +101- 1 +.names preset n_n8672 ngfdn_3 ndn3_50 n5551 +01-- 1 +0-10 1 +.names n3813 preset n4102 n_n7346 n5556 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n7949 n4368 n5561 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n8756 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5566 +1----- 0 +-0---- 0 +--1100 0 +.names n3808 preset n4102 n_n8641 n5571 +00-1 1 +101- 1 +.names n4079 preset psv26_15_15_ n_n8192 n5576 +00-1 1 +101- 1 +.names n3826_1 preset n4217 n3853 n_n8058 n5581 +00--1 1 +1000- 1 +1011- 1 +.names n_n8561 n4415 n4416_1 n3745 n4183 n4329 n5586 +11---- 1 +--10-- 1 +----10 1 +.names preset n_n9306 ngfdn_3 ndn3_50 n5591 +01-- 1 +0-10 1 +.names preset n_n9165 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n5596 +01---- 1 +0-1100 1 +.names n3818 preset n_n9573 n_n8850 n5601 +00-1 1 +101- 1 +.names n3812 preset n4061_1 n4007 n_n9210 n5606 +00--1 1 +1001- 1 +1010- 1 +.names ndn2_2 preset nsr1_2 nlc1_2 preset_0_0_ n5611 +100-- 1 +10-1- 1 +10--0 1 +.names n4203 n4102 n_n7342 n4202 n5616 +11-- 1 +--11 1 +.names n4079 preset psv26_6_6_ n_n8051 n5621 +00-1 1 +101- 1 +.names n3798 preset n4301_1 n_n7136 n5626 +00-1 1 +101- 1 +.names n4079 preset psv33_9_9_ n_n9348 n5631 +00-1 1 +101- 1 +.names preset n3819 n_n9006 n5636 +01- 1 +0-1 1 +.names preset ndn3_20 nsr3_20 n_n7653 n4397 n5641 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n3819 n_n7905 n5646 +01- 1 +0-1 1 +.names preset n_n9166 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n5651 +01---- 1 +0-1100 1 +.names preset n3819 n_n7065 n5656 +01- 1 +0-1 1 +.names n3822 preset n4106_1 n_n9490 n5661 +00-1 1 +101- 1 +.names preset n3835 n_n7024 n5666 +01- 1 +0-1 1 +.names preset n3818 n_n7586 n5671 +01- 1 +0-1 1 +.names n4079 preset psv39_9_9_ n_n8416 n5676 +00-1 1 +101- 1 +.names n4213 n3803 n_n8937 n4212 n5681 +11-- 1 +--11 1 +.names preset n_n8141 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5686 +1----- 0 +-0---- 0 +--1100 0 +.names preset n_n7853 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5691 +1----- 0 +-0---- 0 +--1100 0 +.names preset n3835 n_n8121 n5696 +01- 1 +0-1 1 +.names n4079 preset psv13_7_7_ n_n9604 n5701 +00-1 1 +101- 1 +.names n3837 preset n4106_1 n_n9496 n5706 +00-1 1 +101- 1 +.names preset n3819 n_n8195 n5711 +01- 1 +0-1 1 +.names n3810 preset n4061_1 n4007 n_n9516 n5716 +00--1 1 +1001- 1 +1010- 1 +.names n3851_1 preset n4242 n_n9077 n5721 +00-1 1 +101- 1 +.names preset n_n9436 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5726 +1----- 0 +-0---- 0 +--1100 0 +.names n3814 preset n4356_1 n_n9051 n5731 +00-1 1 +101- 1 +.names n3809 preset n4191_1 n_n7664 n5736 +00-1 1 +101- 1 +.names n_n8419 n4183 n5330 n4174 n5741 +011- 1 +110- 1 +1--1 1 +.names n4167 n4115 n_n8354 n4163 n5330 +000- 1 +00-1 1 +11-- 1 +1-10 1 +.names preset ndn3_35 nsr3_35 n_n7874 n4374 n5746 +000-1 1 +01-1- 1 +0-11- 1 +.names n3812 preset n4099 n_n9133 n5751 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n9392 n4207 n5756 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n7770 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5761 +1----- 0 +-0---- 0 +--1100 0 +.names preset ngfdn_3 ndn3_29 ndn3_32 n5766 +001- 1 +00-1 1 +.names n3851_1 preset n4301_1 n_n7601 n5771 +00-1 1 +101- 1 +.names n3798 preset n4106_1 n_n8206 n5776 +00-1 1 +101- 1 +.names n3835 preset n4381_1 n4244 n4243 n_n7927 n5781 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4079 preset psv2_7_7_ n_n9606 n5786 +00-1 1 +101- 1 +.names preset ngfdn_3 ndn3_50 n_n7111 n_n9028 n5791 +00-1- 1 +010-1 1 +0-11- 1 +.names n3808 preset n3803 n_n9269 n5796 +00-1 1 +101- 1 +.names nsr3_38 preset n5801 +00 1 +.names n4079 preset psv18_13_13_ n_n7886 n5806 +00-1 1 +101- 1 +.names n3812 preset n4106_1 n_n9179 n5811 +00-1 1 +101- 1 +.names preset n_n9357 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5816 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv18_7_7_ n_n9594 n5821 +00-1 1 +101- 1 +.names preset n_n7628 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5826 +1----- 0 +-0---- 0 +--1100 0 +.names preset n3824 n_n8454 n5831 +01- 1 +0-1 1 +.names nsr3_20 preset n5836 +00 1 +.names preset nsr3_37 ndn3_37 n_n9505 n4409 n5841 +000-1 1 +01-1- 1 +0-11- 1 +.names ngfdn_3 preset nsr3_35 nen3_34 n5846 +000- 1 +00-1 1 +.names n3819 preset n4381_1 n4244 n4243 n_n9632 n5851 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n3827 preset n_n8462 n_n7076 n5856 +00-1 1 +101- 1 +.names n4079 preset psv38_7_7_ n_n9262 n5861 +00-1 1 +101- 1 +.names n3826_1 preset n4356_1 n_n9048 n5866 +00-1 1 +101- 1 +.names preset n_n9578 preset_0_0_ nsr1_2 nlc1_2 ndn2_2 n5871 +01---- 1 +0-1100 1 +.names n3810 preset n4187 n_n8135 n5876 +00-1 1 +101- 1 +.names ngfdn_3 preset ndn3_26 ndn3_25 n5881 +001- 1 +00-1 1 +.names n3827 preset n_n9460 n_n7500 n5886 +00-1 1 +101- 1 +.names n3798 preset n4219 n_n6974 n5891 +00-1 1 +101- 1 +.names preset n3824 n_n8605 n5896 +01- 1 +0-1 1 +.names preset n_n9296 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5901 +1----- 0 +-0---- 0 +--1100 0 +.names n3819 preset n_n8609 n_n7156 n5906 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n7920 n4441_1 n5911 +000-1 1 +01-1- 1 +0-11- 1 +.names n3818 preset n_n7570 n_n8895 n5916 +00-1 1 +101- 1 +.names n3813 preset n4324 n4052 n4027 n_n8991 n5921 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names n4079 preset psv38_14_14_ n_n8139 n5926 +00-1 1 +101- 1 +.names preset n_n9275 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5931 +1----- 0 +-0---- 0 +--1100 0 +.names n3824 preset n_n9125 n_n7203 n5936 +00-1 1 +101- 1 +.names preset ndn3_38 nsr3_38 n_n9590 n3796_1 n5941 +000-1 1 +01-1- 1 +0-11- 1 +.names preset ngfdn_3 ndn3_50 n_n7344 n_n9570 n5946 +00-1- 1 +010-1 1 +0-11- 1 +.names n4079 preset psv18_9_9_ n_n6976 n5951 +00-1 1 +101- 1 +.names preset n_n7629 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5956 +1----- 0 +-0---- 0 +--1100 0 +.names n3798 preset n4356_1 n_n7862 n5966 +00-1 1 +101- 1 +.names preset n_n9013 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5971 +1----- 0 +-0---- 0 +--1100 0 +.names preset ngfdn_3 ndn3_50 n_n7288 n_n9282 n5976 +00-1- 1 +010-1 1 +0-11- 1 +.names preset ndn3_35 nsr3_35 n_n8078 n4349 n5981 +000-1 1 +01-1- 1 +0-11- 1 +.names n3813 preset n4061_1 n4007 n_n7334 n5986 +00--1 1 +1001- 1 +1010- 1 +.names preset n_n7704 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n5991 +1----- 0 +-0---- 0 +--1100 0 +.names preset nsr3_37 ndn3_37 n_n7788 n4292 n5996 +000-1 1 +01-1- 1 +0-11- 1 +.names n3851_1 preset n4102 n_n8526 n6001 +00-1 1 +101- 1 +.names preset n_n9556 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n6006 +1----- 0 +-0---- 0 +--1100 0 +.names n3812 preset n4324 n4052 n4027 n_n9345 n6011 +00---1 1 +1001-- 1 +100-1- 1 +10100- 1 +.names preset n_n8447 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n6016 +1----- 0 +-0---- 0 +--1100 0 +.names n4104 n4301_1 n_n7485 n4103 n6021 +11-- 1 +--11 1 +.names preset n_n8570 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n6026 +1----- 0 +-0---- 0 +--1100 0 +.names n4104 n3853 n4217 n_n7453 n4103 n6031 +100-- 1 +111-- 1 +---11 1 +.names preset ndn3_35 nsr3_35 n_n7928 n4401_1 n6036 +000-1 1 +01-1- 1 +0-11- 1 +.names preset n_n8646 nsr1_2 preset_0_0_ nlc1_2 ndn2_2 n6041 +1----- 0 +-0---- 0 +--1100 0 +.names n4079 preset psv26_3_3_ n_n9405 n6046 +00-1 1 +101- 1 +.names n3818 preset n4191_1 n_n8948 n6051 +00-1 1 +101- 1 +.names n3826_1 preset n4099 n_n9131 n6056 +00-1 1 +101- 1 +.names preset n3824 n_n8216 n6061 +01- 1 +0-1 1 +.names n3826_1 preset n4106_1 n_n9177 n6066 +00-1 1 +101- 1 +.names n3809 preset n4219 n_n7844 n6071 +00-1 1 +101- 1 +.names n4287 preset n4099 n_n8811 n6076 +00-1 1 +101- 1 +.names n3818 preset n_n9629 n_n9145 n6081 +00-1 1 +101- 1 +.names n3824 preset n_n9333 n_n8428 n6086 +00-1 1 +101- 1 +.names n3813 preset n4106_1 n_n8858 n6091 +00-1 1 +101- 1 +.names n3810 preset n4242 n_n8580 n6096 +00-1 1 +101- 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v b/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v new file mode 100644 index 000000000..35b630cab --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v @@ -0,0 +1,8198 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module elliptic(clock, tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_, tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_, tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_, tin_psv39_9_9_, tin_psv39_1_1_, tin_psv13_6_6_, tin_psv2_6_6_, pinp_0_0_, tin_psv38_3_3_, tin_psv33_6_6_, tin_psv26_13_13_, tin_psv26_12_12_, tin_psv26_7_7_, tin_psv2_7_7_, pinp_1_1_, preset_0_0_, tin_psv18_3_3_, tin_psv39_2_2_, tin_psv33_12_12_, tin_psv33_11_11_, tin_psv33_10_10_, tin_psv13_7_7_, tin_psv2_10_10_, tin_psv38_4_4_, tin_psv39_10_10_, tin_psv33_7_7_, tin_psv26_15_15_, tin_psv26_14_14_, tin_psv26_8_8_, tin_psv26_0_0_, tin_psv13_12_12_, tin_psv13_11_11_, tin_psv18_4_4_, tin_psv39_3_3_, tin_psv13_8_8_, tin_psv13_0_0_, pinp_15_15_, pinp_12_12_, tin_psv38_5_5_, tin_psv33_8_8_, tin_psv33_0_0_, tin_psv26_9_9_, tin_psv26_1_1_, tin_psv13_10_10_, tin_psv18_5_5_, tin_psv39_4_4_, tin_psv13_9_9_, tin_psv13_1_1_, tin_psv2_15_15_, tin_psv2_11_11_, tin_psv2_0_0_, tin_psv38_14_14_, tin_psv38_12_12_, tin_psv38_10_10_, tin_psv38_6_6_, tin_psv18_15_15_, tin_psv18_13_13_, tin_psv18_11_11_, tin_psv33_9_9_, tin_psv33_1_1_, tin_psv26_2_2_, tin_psv2_1_1_, /*pclk,*/ tin_psv38_15_15_, tin_psv38_11_11_, tin_psv18_12_12_, tin_psv18_6_6_, tin_psv39_5_5_, tin_psv13_2_2_, pinp_14_14_, pinp_11_11_, pinp_8_8_, tin_psv38_7_7_, tin_psv39_12_12_, tin_psv39_11_11_, tin_psv33_2_2_, tin_psv26_3_3_, tin_psv13_14_14_, tin_psv13_13_13_, pinp_9_9_, tin_psv18_10_10_, tin_psv18_7_7_, tin_psv39_6_6_, tin_psv33_15_15_, tin_psv33_14_14_, tin_psv33_13_13_, tin_psv13_3_3_, tin_psv2_14_14_, tin_psv2_12_12_, tin_psv2_4_4_, pinp_6_6_, tin_psv38_8_8_, tin_psv38_0_0_, tin_psv39_14_14_, tin_psv39_13_13_, tin_psv33_3_3_, tin_psv26_11_11_, tin_psv26_10_10_, tin_psv26_4_4_, tin_psv13_15_15_, tin_psv2_5_5_, pinp_7_7_, tin_psv18_8_8_, tin_psv18_0_0_, tin_psv39_7_7_, tin_psv13_4_4_, tin_psv2_2_2_, pinp_13_13_, pinp_10_10_, pinp_4_4_, tin_psv38_9_9_, tin_psv38_1_1_, preset, tin_psv39_15_15_, tin_psv33_4_4_, tin_psv26_5_5_, tin_psv2_3_3_, pinp_5_5_, tin_psv38_13_13_, tin_psv18_14_14_, tin_psv18_9_9_, tin_psv18_1_1_, psv39_8_8_, psv39_0_0_, psv13_5_5_, psv2_13_13_, psv2_8_8_, psv38_2_2_, psv33_5_5_, psv26_6_6_, psv2_9_9_, psv18_2_2_, psv39_9_9_, psv39_1_1_, psv13_6_6_, psv2_6_6_, psv38_3_3_, psv33_6_6_, psv26_13_13_, psv26_12_12_, psv26_7_7_, psv2_7_7_, psv18_3_3_, psv39_2_2_, psv33_12_12_, psv33_11_11_, psv33_10_10_, psv13_7_7_, psv2_10_10_, psv38_4_4_, psv39_10_10_, psv33_7_7_, psv26_15_15_, psv26_14_14_, psv26_8_8_, psv26_0_0_, psv13_12_12_, psv13_11_11_, psv18_4_4_, psv39_3_3_, psv13_8_8_, psv13_0_0_, psv38_5_5_, psv33_8_8_, psv33_0_0_, psv26_9_9_, psv26_1_1_, psv13_10_10_, psv18_5_5_, psv39_4_4_, psv13_9_9_, psv13_1_1_, psv2_15_15_, psv2_11_11_, psv2_0_0_, psv38_14_14_, psv38_12_12_, psv38_10_10_, psv38_6_6_, psv18_15_15_, psv18_13_13_, psv18_11_11_, psv33_9_9_, psv33_1_1_, psv26_2_2_, psv2_1_1_, psv38_15_15_, psv38_11_11_, psv18_12_12_, psv18_6_6_, psv39_5_5_, psv13_2_2_, pover_0_0_, psv38_7_7_, psv39_12_12_, psv39_11_11_, psv33_2_2_, psv26_3_3_, psv13_14_14_, psv13_13_13_, psv18_10_10_, psv18_7_7_, psv39_6_6_, psv33_15_15_, psv33_14_14_, psv33_13_13_, psv13_3_3_, psv2_14_14_, psv2_12_12_, psv2_4_4_, psv38_8_8_, psv38_0_0_, pdn, psv39_14_14_, psv39_13_13_, psv33_3_3_, psv26_11_11_, psv26_10_10_, psv26_4_4_, psv13_15_15_, psv2_5_5_, psv18_8_8_, psv18_0_0_, psv39_7_7_, psv13_4_4_, psv2_2_2_, psv38_9_9_, psv38_1_1_, psv39_15_15_, psv33_4_4_, psv26_5_5_, psv2_3_3_, psv38_13_13_, psv18_14_14_, psv18_9_9_, psv18_1_1_); + input clock; + wire n1001; + wire n1006; + wire n1011; + wire n1016; + wire n1021; + wire n1026; + wire n1031; + wire n1036; + wire n1041; + wire n1046; + wire n1051; + wire n1056; + wire n1061; + wire n1066; + wire n1071; + wire n1076; + wire n1081; + wire n1086; + wire n1091; + wire n1096; + wire n1101; + wire n1106; + wire n1111; + wire n1116; + wire n1121; + wire n1126; + wire n1131; + wire n1136; + wire n1141; + wire n1146; + wire n1151; + wire n1156; + wire n1161; + wire n1166; + wire n1171; + wire n1176; + wire n1181; + wire n1186; + wire n1191; + wire n1196; + wire n1201; + wire n1206; + wire n1211; + wire n1216; + wire n1221; + wire n1226; + wire n1231; + wire n1236; + wire n1241; + wire n1246; + wire n1251; + wire n1256; + wire n1261; + wire n1266; + wire n1271; + wire n1276; + wire n1281; + wire n1286; + wire n1291; + wire n1296; + wire n1301; + wire n1306; + wire n1311; + wire n1316; + wire n1321; + wire n1326; + wire n1331; + wire n1336; + wire n1341; + wire n1346; + wire n1351; + wire n1356; + wire n1361; + wire n1366; + wire n1371; + wire n1376; + wire n1381; + wire n1386; + wire n1391; + wire n1396; + wire n1401; + wire n1406; + wire n1411; + wire n1416; + wire n1421; + wire n1426; + wire n1431; + wire n1436; + wire n1441; + wire n1446; + wire n1451; + wire n1456; + wire n1461; + wire n1466; + wire n1471; + wire n1476; + wire n1481; + wire n1486; + wire n1491; + wire n1496; + wire n1501; + wire n1506; + wire n1511; + wire n1516; + wire n1521; + wire n1526; + wire n1531; + wire n1536; + wire n1541; + wire n1546; + wire n1551; + wire n1556; + wire n1561; + wire n1566; + wire n1571; + wire n1576; + wire n1581; + wire n1586; + wire n1591; + wire n1596; + wire n1601; + wire n1606; + wire n1611; + wire n1616; + wire n1621; + wire n1626; + wire n1631; + wire n1636; + wire n1641; + wire n1646; + wire n1651; + wire n1656; + wire n1661; + wire n1666; + wire n1671; + wire n1676; + wire n1681; + wire n1686; + wire n1691; + wire n1696; + wire n1701; + wire n1706; + wire n1711; + wire n1716; + wire n1721; + wire n1726; + wire n1731; + wire n1736; + wire n1741; + wire n1746; + wire n1751; + wire n1756; + wire n1761; + wire n1766; + wire n1771; + wire n1776; + wire n1781; + wire n1786; + wire n1791; + wire n1796; + wire n1801; + wire n1806; + wire n1811; + wire n1816; + wire n1821; + wire n1826; + wire n1831; + wire n1836; + wire n1841; + wire n1846; + wire n1851; + wire n1856; + wire n1861; + wire n1866; + wire n1871; + wire n1876; + wire n1881; + wire n1886; + wire n1891; + wire n1896; + wire n1901; + wire n1906; + wire n1911; + wire n1916; + wire n1921; + wire n1926; + wire n1931; + wire n1936; + wire n1941; + wire n1946; + wire n1951; + wire n1956; + wire n1961; + wire n1966; + wire n1971; + wire n1976; + wire n1981; + wire n1986; + wire n1991; + wire n1996; + wire n2001; + wire n2006; + wire n2011; + wire n2016; + wire n2021; + wire n2026; + wire n2031; + wire n2036; + wire n2041; + wire n2046; + wire n2051; + wire n2056; + wire n2061; + wire n2066; + wire n2071; + wire n2076; + wire n2081; + wire n2086; + wire n2091; + wire n2096; + wire n2101; + wire n2106; + wire n2111; + wire n2116; + wire n2121; + wire n2126; + wire n2131; + wire n2136; + wire n2141; + wire n2146; + wire n2151; + wire n2156; + wire n2161; + wire n2166; + wire n2171; + wire n2176; + wire n2181; + wire n2186; + wire n2191; + wire n2196; + wire n2201; + wire n2206; + wire n2211; + wire n2216; + wire n2221; + wire n2226; + wire n2231; + wire n2236; + wire n2241; + wire n2246; + wire n2251; + wire n2256; + wire n2261; + wire n2266; + wire n2271; + wire n2276; + wire n2281; + wire n2286; + wire n2291; + wire n2296; + wire n2301; + wire n2306; + wire n2311; + wire n2316; + wire n2321; + wire n2326; + wire n2331; + wire n2336; + wire n2341; + wire n2346; + wire n2351; + wire n2356; + wire n2361; + wire n2366; + wire n2371; + wire n2376; + wire n2381; + wire n2386; + wire n2391; + wire n2396; + wire n2401; + wire n2406; + wire n2411; + wire n2416; + wire n2421; + wire n2426; + wire n2431; + wire n2436; + wire n2441; + wire n2446; + wire n2451; + wire n2456; + wire n2461; + wire n2466; + wire n2471; + wire n2476; + wire n2481; + wire n2486; + wire n2491; + wire n2496; + wire n2501; + wire n2506; + wire n2511; + wire n2516; + wire n2521; + wire n2526; + wire n2531; + wire n2536; + wire n2541; + wire n2546; + wire n2551; + wire n2556; + wire n2561; + wire n2566; + wire n2571; + wire n2576; + wire n2581; + wire n2586; + wire n2591; + wire n2596; + wire n2601; + wire n2606; + wire n2611; + wire n2616; + wire n2621; + wire n2626; + wire n2631; + wire n2636; + wire n2641; + wire n2646; + wire n2651; + wire n2656; + wire n2661; + wire n2666; + wire n2671; + wire n2676; + wire n2681; + wire n2686; + wire n2691; + wire n2696; + wire n2701; + wire n2706; + wire n2711; + wire n2716; + wire n2721; + wire n2726; + wire n2731; + wire n2736; + wire n2741; + wire n2746; + wire n2751; + wire n2756; + wire n2761; + wire n2766; + wire n2771; + wire n2776; + wire n2781; + wire n2786; + wire n2791; + wire n2796; + wire n2801; + wire n2806; + wire n2811; + wire n2816; + wire n2821; + wire n2826; + wire n2831; + wire n2836; + wire n2841; + wire n2846; + wire n2851; + wire n2856; + wire n2861; + wire n2866; + wire n2871; + wire n2876; + wire n2881; + wire n2886; + wire n2891; + wire n2896; + wire n2901; + wire n2906; + wire n2911; + wire n2916; + wire n2921; + wire n2926; + wire n2931; + wire n2936; + wire n2941; + wire n2946; + wire n2951; + wire n2956; + wire n2961; + wire n2966; + wire n2971; + wire n2976; + wire n2981; + wire n2986; + wire n2991; + wire n2996; + wire n3001; + wire n3006; + wire n3011; + wire n3016; + wire n3021; + wire n3026; + wire n3031; + wire n3036; + wire n3041; + wire n3046; + wire n3051; + wire n3056; + wire n3061; + wire n3066; + wire n3071; + wire n3076; + wire n3081; + wire n3086; + wire n3091; + wire n3096; + wire n3101; + wire n3106; + wire n3111; + wire n3116; + wire n3121; + wire n3126; + wire n3131; + wire n3136; + wire n3141; + wire n3146; + wire n3151; + wire n3156; + wire n3161; + wire n3166; + wire n3171; + wire n3176; + wire n3181; + wire n3186; + wire n3191; + wire n3196; + wire n3201; + wire n3206; + wire n3211; + wire n3216; + wire n3221; + wire n3226; + wire n3231; + wire n3236; + wire n3241; + wire n3246; + wire n3251; + wire n3256; + wire n3261; + wire n3266; + wire n3271; + wire n3276; + wire n3281; + wire n3286; + wire n3291; + wire n3296; + wire n3301; + wire n3306; + wire n3311; + wire n3316; + wire n3321; + wire n3326; + wire n3331; + wire n3336; + wire n3341; + wire n3346; + wire n3351; + wire n3356; + wire n3361; + wire n3366; + wire n3371; + wire n3376; + wire n3381; + wire n3386; + wire n3391; + wire n3396; + wire n3401; + wire n3406; + wire n3411; + wire n3416; + wire n3421; + wire n3426; + wire n3431; + wire n3436; + wire n3441; + wire n3446; + wire n3451; + wire n3456; + wire n3461; + wire n3466; + wire n3471; + wire n3476; + wire n3481; + wire n3486; + wire n3491; + wire n3496; + wire n3501; + wire n3506; + wire n3511; + wire n3516; + wire n3521; + wire n3526; + wire n3531; + wire n3536; + wire n3541; + wire n3546; + wire n3551; + wire n3556; + wire n3561; + wire n3566; + wire n3571; + wire n3576; + wire n3581; + wire n3586; + wire n3591; + wire n3596; + wire n3601; + wire n3606; + wire n3611; + wire n3616; + wire n3621; + wire n3626; + wire n3631; + wire n3636; + wire n3641; + wire n3646; + wire n3651; + wire n3656; + wire n3661; + wire n3666; + wire n3671; + wire n3676; + wire n3681; + wire n3686; + wire n3691; + wire n3696; + wire n3701; + wire n3706; + wire n3711; + wire n3716; + wire n3721; + wire n3726; + wire n3730; + wire n3731; + wire n3731_1; + wire n3732; + wire n3733; + wire n3734; + wire n3735; + wire n3736; + wire n3736_1; + wire n3737; + wire n3738; + wire n3739; + wire n3740; + wire n3741; + wire n3741_1; + wire n3742; + wire n3743; + wire n3744; + wire n3745; + wire n3746; + wire n3746_1; + wire n3747; + wire n3748; + wire n3749; + wire n3750; + wire n3751; + wire n3751_1; + wire n3752; + wire n3753; + wire n3754; + wire n3755; + wire n3756; + wire n3756_1; + wire n3757; + wire n3758; + wire n3759; + wire n3760; + wire n3761; + wire n3761_1; + wire n3762; + wire n3763; + wire n3764; + wire n3765; + wire n3766; + wire n3766_1; + wire n3767; + wire n3768; + wire n3769; + wire n3770; + wire n3771; + wire n3771_1; + wire n3772; + wire n3773; + wire n3774; + wire n3775; + wire n3776; + wire n3776_1; + wire n3777; + wire n3778; + wire n3779; + wire n3780; + wire n3781; + wire n3781_1; + wire n3782; + wire n3783; + wire n3784; + wire n3785; + wire n3786; + wire n3786_1; + wire n3787; + wire n3788; + wire n3789; + wire n3790; + wire n3791; + wire n3791_1; + wire n3792; + wire n3793; + wire n3794; + wire n3796; + wire n3796_1; + wire n3798; + wire n3801; + wire n3803; + wire n3804; + wire n3805; + wire n3806; + wire n3806_1; + wire n3807; + wire n3808; + wire n3809; + wire n3810; + wire n3811; + wire n3811_1; + wire n3812; + wire n3813; + wire n3814; + wire n3815; + wire n3816; + wire n3816_1; + wire n3817; + wire n3818; + wire n3819; + wire n3820; + wire n3821; + wire n3821_1; + wire n3822; + wire n3823; + wire n3824; + wire n3825; + wire n3826; + wire n3826_1; + wire n3827; + wire n3828; + wire n3829; + wire n3830; + wire n3831; + wire n3831_1; + wire n3832; + wire n3833; + wire n3834; + wire n3835; + wire n3836; + wire n3836_1; + wire n3837; + wire n3838; + wire n3839; + wire n3840; + wire n3841; + wire n3841_1; + wire n3842; + wire n3843; + wire n3844; + wire n3845; + wire n3846; + wire n3846_1; + wire n3847; + wire n3848; + wire n3849; + wire n3850; + wire n3851; + wire n3851_1; + wire n3852; + wire n3853; + wire n3854; + wire n3855; + wire n3856; + wire n3856_1; + wire n3857; + wire n3858; + wire n3859; + wire n3860; + wire n3861; + wire n3861_1; + wire n3862; + wire n3863; + wire n3864; + wire n3865; + wire n3866; + wire n3866_1; + wire n3867; + wire n3868; + wire n3869; + wire n3870; + wire n3871; + wire n3871_1; + wire n3872; + wire n3873; + wire n3874; + wire n3875; + wire n3876; + wire n3876_1; + wire n3877; + wire n3878; + wire n3879; + wire n3880; + wire n3881; + wire n3881_1; + wire n3882; + wire n3883; + wire n3884; + wire n3885; + wire n3886; + wire n3886_1; + wire n3887; + wire n3888; + wire n3889; + wire n3890; + wire n3891; + wire n3891_1; + wire n3892; + wire n3893; + wire n3894; + wire n3895; + wire n3896; + wire n3896_1; + wire n3897; + wire n3898; + wire n3899; + wire n3900; + wire n3901; + wire n3901_1; + wire n3902; + wire n3903; + wire n3904; + wire n3905; + wire n3906; + wire n3906_1; + wire n3907; + wire n3908; + wire n3909; + wire n3910; + wire n3911; + wire n3911_1; + wire n3912; + wire n3913; + wire n3914; + wire n3915; + wire n3916; + wire n3916_1; + wire n3917; + wire n3918; + wire n3919; + wire n3920; + wire n3921; + wire n3921_1; + wire n3922; + wire n3923; + wire n3924; + wire n3925; + wire n3926; + wire n3926_1; + wire n3927; + wire n3928; + wire n3929; + wire n3930; + wire n3931; + wire n3931_1; + wire n3932; + wire n3933; + wire n3934; + wire n3935; + wire n3936; + wire n3936_1; + wire n3937; + wire n3938; + wire n3939; + wire n3940; + wire n3941; + wire n3941_1; + wire n3942; + wire n3943; + wire n3944; + wire n3945; + wire n3946; + wire n3946_1; + wire n3947; + wire n3948; + wire n3949; + wire n3950; + wire n3951; + wire n3951_1; + wire n3952; + wire n3953; + wire n3954; + wire n3955; + wire n3956; + wire n3956_1; + wire n3957; + wire n3958; + wire n3959; + wire n3960; + wire n3961; + wire n3961_1; + wire n3962; + wire n3963; + wire n3964; + wire n3965; + wire n3966; + wire n3966_1; + wire n3967; + wire n3968; + wire n3969; + wire n3970; + wire n3971; + wire n3971_1; + wire n3972; + wire n3973; + wire n3974; + wire n3975; + wire n3976; + wire n3976_1; + wire n3977; + wire n3978; + wire n3979; + wire n3980; + wire n3981; + wire n3981_1; + wire n3982; + wire n3983; + wire n3984; + wire n3985; + wire n3986; + wire n3986_1; + wire n3987; + wire n3988; + wire n3989; + wire n3990; + wire n3991; + wire n3991_1; + wire n3992; + wire n3993; + wire n3994; + wire n3995; + wire n3996; + wire n3996_1; + wire n3997; + wire n3998; + wire n3999; + wire n4000; + wire n4001; + wire n4001_1; + wire n4002; + wire n4003; + wire n4004; + wire n4006; + wire n4007; + wire n4008; + wire n4009; + wire n4010; + wire n4011; + wire n4011_1; + wire n4012; + wire n4013; + wire n4014; + wire n4015; + wire n4016; + wire n4016_1; + wire n4017; + wire n4018; + wire n4019; + wire n4020; + wire n4021; + wire n4021_1; + wire n4022; + wire n4023; + wire n4024; + wire n4025; + wire n4026; + wire n4026_1; + wire n4027; + wire n4028; + wire n4029; + wire n4030; + wire n4031; + wire n4031_1; + wire n4032; + wire n4033; + wire n4034; + wire n4035; + wire n4036; + wire n4036_1; + wire n4037; + wire n4038; + wire n4039; + wire n4040; + wire n4041; + wire n4041_1; + wire n4042; + wire n4043; + wire n4044; + wire n4045; + wire n4046; + wire n4046_1; + wire n4047; + wire n4048; + wire n4049; + wire n4050; + wire n4051; + wire n4051_1; + wire n4052; + wire n4053; + wire n4054; + wire n4055; + wire n4056; + wire n4056_1; + wire n4057; + wire n4058; + wire n4059; + wire n4060; + wire n4061; + wire n4061_1; + wire n4062; + wire n4063; + wire n4064; + wire n4065; + wire n4066; + wire n4066_1; + wire n4067; + wire n4068; + wire n4069; + wire n4070; + wire n4071; + wire n4071_1; + wire n4072; + wire n4073; + wire n4074; + wire n4075; + wire n4076; + wire n4076_1; + wire n4077; + wire n4079; + wire n4081; + wire n4081_1; + wire n4082; + wire n4083; + wire n4084; + wire n4085; + wire n4086; + wire n4086_1; + wire n4087; + wire n4088; + wire n4089; + wire n4090; + wire n4091; + wire n4091_1; + wire n4092; + wire n4093; + wire n4094; + wire n4095; + wire n4096; + wire n4096_1; + wire n4097; + wire n4099; + wire n4100; + wire n4101; + wire n4102; + wire n4103; + wire n4104; + wire n4106; + wire n4106_1; + wire n4111; + wire n4113; + wire n4114; + wire n4115; + wire n4116; + wire n4116_1; + wire n4117; + wire n4118; + wire n4119; + wire n4120; + wire n4121; + wire n4121_1; + wire n4122; + wire n4123; + wire n4124; + wire n4125; + wire n4126; + wire n4126_1; + wire n4127; + wire n4128; + wire n4129; + wire n4130; + wire n4131; + wire n4131_1; + wire n4132; + wire n4133; + wire n4134; + wire n4135; + wire n4136; + wire n4136_1; + wire n4137; + wire n4138; + wire n4139; + wire n4140; + wire n4141; + wire n4141_1; + wire n4142; + wire n4143; + wire n4144; + wire n4145; + wire n4146; + wire n4146_1; + wire n4147; + wire n4148; + wire n4149; + wire n4150; + wire n4151; + wire n4151_1; + wire n4152; + wire n4153; + wire n4154; + wire n4155; + wire n4156; + wire n4156_1; + wire n4157; + wire n4158; + wire n4159; + wire n4160; + wire n4161; + wire n4161_1; + wire n4162; + wire n4163; + wire n4164; + wire n4165; + wire n4166; + wire n4166_1; + wire n4167; + wire n4168; + wire n4169; + wire n4170; + wire n4171; + wire n4171_1; + wire n4172; + wire n4173; + wire n4174; + wire n4175; + wire n4176; + wire n4176_1; + wire n4177; + wire n4178; + wire n4179; + wire n4180; + wire n4181; + wire n4181_1; + wire n4182; + wire n4183; + wire n4185; + wire n4186; + wire n4187; + wire n4191; + wire n4191_1; + wire n4195; + wire n4196; + wire n4196_1; + wire n4197; + wire n4200; + wire n4201; + wire n4202; + wire n4203; + wire n4206; + wire n4207; + wire n4211; + wire n4212; + wire n4213; + wire n4216; + wire n4217; + wire n4219; + wire n4220; + wire n4221; + wire n4221_1; + wire n4222; + wire n4223; + wire n4224; + wire n4225; + wire n4226; + wire n4226_1; + wire n4227; + wire n4228; + wire n4229; + wire n4230; + wire n4231; + wire n4231_1; + wire n4232; + wire n4233; + wire n4234; + wire n4235; + wire n4236; + wire n4236_1; + wire n4237; + wire n4240; + wire n4241; + wire n4242; + wire n4243; + wire n4244; + wire n4245; + wire n4246; + wire n4246_1; + wire n4247; + wire n4248; + wire n4249; + wire n4250; + wire n4251; + wire n4251_1; + wire n4252; + wire n4253; + wire n4254; + wire n4255; + wire n4256; + wire n4256_1; + wire n4257; + wire n4258; + wire n4259; + wire n4260; + wire n4261; + wire n4261_1; + wire n4262; + wire n4263; + wire n4264; + wire n4265; + wire n4266; + wire n4266_1; + wire n4267; + wire n4268; + wire n4269; + wire n4270; + wire n4271; + wire n4271_1; + wire n4272; + wire n4273; + wire n4274; + wire n4275; + wire n4276; + wire n4276_1; + wire n4281; + wire n4286; + wire n4287; + wire n4290; + wire n4291; + wire n4292; + wire n4296; + wire n4301; + wire n4301_1; + wire n4306; + wire n4311; + wire n4313; + wire n4316; + wire n4318; + wire n4321; + wire n4324; + wire n4326; + wire n4327; + wire n4328; + wire n4329; + wire n4330; + wire n4331; + wire n4331_1; + wire n4332; + wire n4333; + wire n4334; + wire n4335; + wire n4336; + wire n4336_1; + wire n4337; + wire n4338; + wire n4339; + wire n4340; + wire n4341; + wire n4346; + wire n4349; + wire n4351; + wire n4356; + wire n4356_1; + wire n4361; + wire n4366; + wire n4368; + wire n4371; + wire n4374; + wire n4376; + wire n4381; + wire n4381_1; + wire n4386; + wire n4391; + wire n4396; + wire n4397; + wire n4401; + wire n4401_1; + wire n4406; + wire n4409; + wire n4411; + wire n4415; + wire n4416; + wire n4416_1; + wire n4417; + wire n4418; + wire n4421; + wire n4426; + wire n4431; + wire n4436; + wire n4441; + wire n4441_1; + wire n4446; + wire n4451; + wire n4456; + wire n4461; + wire n4466; + wire n4471; + wire n4476; + wire n4481; + wire n4486; + wire n4491; + wire n4496; + wire n4501; + wire n4506; + wire n4511; + wire n4516; + wire n4521; + wire n4526; + wire n4531; + wire n4536; + wire n4541; + wire n4546; + wire n4551; + wire n4556; + wire n4561; + wire n4566; + wire n4571; + wire n4576; + wire n4581; + wire n4586; + wire n4591; + wire n4596; + wire n4601; + wire n4606; + wire n4611; + wire n4616; + wire n4621; + wire n4621_1; + wire n4626; + wire n4631; + wire n4636; + wire n4641; + wire n4646; + wire n4649; + wire n4650; + wire n4651; + wire n4651_1; + wire n4656; + wire n4659; + wire n4661; + wire n4661_1; + wire n4666; + wire n4671; + wire n4676; + wire n4681; + wire n4686; + wire n4691; + wire n4696; + wire n4701; + wire n4706; + wire n4711; + wire n4716; + wire n4721; + wire n4726; + wire n4731; + wire n4736; + wire n4741; + wire n4746; + wire n4751; + wire n4756; + wire n4761; + wire n4766; + wire n4771; + wire n4776; + wire n4781; + wire n4784; + wire n4786; + wire n4791; + wire n4796; + wire n4801; + wire n4806; + wire n4811; + wire n4816; + wire n4821; + wire n4826; + wire n4831; + wire n4836; + wire n4841; + wire n4845; + wire n4846; + wire n4851; + wire n4856; + wire n4861; + wire n4866; + wire n4871; + wire n4876; + wire n4881; + wire n4886; + wire n4891; + wire n4896; + wire n4901; + wire n4906; + wire n4911; + wire n4916; + wire n4921; + wire n4926; + wire n493; + wire n4931; + wire n4936; + wire n4941; + wire n4941_1; + wire n4946; + wire n4951; + wire n4956; + wire n4961; + wire n4966; + wire n497; + wire n4971; + wire n4976; + wire n4981; + wire n4986; + wire n4991; + wire n4996; + wire n5001; + wire n5006; + wire n5011; + wire n5016; + wire n5017; + wire n501_1; + wire n5021; + wire n5026; + wire n5031; + wire n5036; + wire n5041; + wire n5046; + wire n5051; + wire n5056; + wire n5061; + wire n5066; + wire n506_1; + wire n5071; + wire n5076; + wire n5081; + wire n5086; + wire n5091; + wire n5096; + wire n5101; + wire n5106; + wire n5110; + wire n5111; + wire n5116; + wire n511_1; + wire n5121; + wire n5126; + wire n5131; + wire n5136; + wire n5141; + wire n5146; + wire n5151; + wire n5153; + wire n5156; + wire n5161; + wire n5166; + wire n516_1; + wire n5171; + wire n5176; + wire n5181; + wire n5186; + wire n5191; + wire n5196; + wire n5201; + wire n5206; + wire n5211; + wire n5216; + wire n521_1; + wire n5221; + wire n5225; + wire n5226; + wire n5231; + wire n5236; + wire n5239; + wire n5241; + wire n5246; + wire n5251; + wire n5256; + wire n5261; + wire n5266; + wire n526_1; + wire n5271; + wire n5276; + wire n5281; + wire n5286; + wire n5291; + wire n5296; + wire n5301; + wire n5306; + wire n5311; + wire n5316; + wire n531_1; + wire n5321; + wire n5326; + wire n5330; + wire n5331; + wire n5336; + wire n5341; + wire n5346; + wire n5351; + wire n5356; + wire n5361; + wire n5366; + wire n536_1; + wire n5371; + wire n5376; + wire n5381; + wire n5386; + wire n5391; + wire n5396; + wire n5401; + wire n5406; + wire n5411; + wire n5416; + wire n541_1; + wire n5421; + wire n5426; + wire n5431; + wire n5436; + wire n5441; + wire n5446; + wire n5451; + wire n5456; + wire n5461; + wire n5466; + wire n546_1; + wire n5471; + wire n5476; + wire n5481; + wire n5486; + wire n5491; + wire n5496; + wire n5501; + wire n5506; + wire n5511; + wire n5516; + wire n551_1; + wire n5521; + wire n5526; + wire n5531; + wire n5536; + wire n5541; + wire n5546; + wire n5551; + wire n5556; + wire n5561; + wire n5566; + wire n556_1; + wire n5571; + wire n5576; + wire n5581; + wire n5586; + wire n5591; + wire n5596; + wire n5601; + wire n5606; + wire n5611; + wire n5616; + wire n561_1; + wire n5621; + wire n5626; + wire n5631; + wire n5636; + wire n5641; + wire n5646; + wire n5651; + wire n5656; + wire n5661; + wire n5666; + wire n566_1; + wire n5671; + wire n5676; + wire n5681; + wire n5686; + wire n5691; + wire n5696; + wire n5701; + wire n5706; + wire n5711; + wire n5716; + wire n571_1; + wire n5721; + wire n5726; + wire n5731; + wire n5736; + wire n5741; + wire n5746; + wire n5751; + wire n5756; + wire n5761; + wire n5766; + wire n576_1; + wire n5771; + wire n5776; + wire n5781; + wire n5786; + wire n5791; + wire n5796; + wire n5801; + wire n5806; + wire n5811; + wire n5816; + wire n581_1; + wire n5821; + wire n5826; + wire n5831; + wire n5836; + wire n5841; + wire n5846; + wire n5851; + wire n5856; + wire n5861; + wire n5866; + wire n586_1; + wire n5871; + wire n5876; + wire n5881; + wire n5886; + wire n5891; + wire n5896; + wire n5901; + wire n5906; + wire n5911; + wire n5916; + wire n591_1; + wire n5921; + wire n5926; + wire n5931; + wire n5936; + wire n5941; + wire n5946; + wire n5951; + wire n5956; + wire n5961; + wire n5966; + wire n596_1; + wire n5971; + wire n5976; + wire n5981; + wire n5986; + wire n5991; + wire n5996; + wire n6001; + wire n6006; + wire n6011; + wire n6016; + wire n601_1; + wire n6021; + wire n6026; + wire n6031; + wire n6036; + wire n6041; + wire n6046; + wire n6051; + wire n6056; + wire n6061; + wire n6066; + wire n606_1; + wire n6071; + wire n6076; + wire n6081; + wire n6086; + wire n6091; + wire n6096; + wire n611_1; + wire n616_1; + wire n621_1; + wire n626_1; + wire n631_1; + wire n636_1; + wire n641_1; + wire n646_1; + wire n651_1; + wire n656_1; + wire n661_1; + wire n666_1; + wire n671_1; + wire n676_1; + wire n681_1; + wire n686_1; + wire n691_1; + wire n696_1; + wire n701_1; + wire n706_1; + wire n711_1; + wire n716_1; + wire n721_1; + wire n726_1; + wire n731_1; + wire n736_1; + wire n741_1; + wire n746_1; + wire n751_1; + wire n756_1; + wire n761_1; + wire n766_1; + wire n771_1; + wire n776_1; + wire n781_1; + wire n786_1; + wire n791_1; + wire n796_1; + wire n801_1; + wire n806_1; + wire n811_1; + wire n816_1; + wire n821_1; + wire n826_1; + wire n831_1; + wire n836; + wire n841; + wire n846; + wire n851; + wire n856; + wire n861; + wire n866; + wire n871; + wire n876; + wire n881; + wire n886; + wire n891; + wire n896; + wire n901; + wire n906; + wire n911; + wire n916; + wire n921; + wire n926; + wire n931; + wire n936; + wire n941; + wire n946; + wire n951; + wire n956; + wire n961; + wire n966; + wire n971; + wire n976; + wire n981; + wire n986; + wire n991; + wire n996; + (* init = 1'h0 *) + reg n_n6910 = 1'h0; + (* init = 1'h0 *) + reg n_n6912 = 1'h0; + (* init = 1'h0 *) + reg n_n6920 = 1'h0; + (* init = 1'h0 *) + reg n_n6937 = 1'h0; + (* init = 1'h0 *) + reg n_n6948 = 1'h0; + (* init = 1'h0 *) + reg n_n6950 = 1'h0; + (* init = 1'h0 *) + reg n_n6952 = 1'h0; + (* init = 1'h0 *) + reg n_n6956 = 1'h0; + (* init = 1'h0 *) + reg n_n6961 = 1'h0; + (* init = 1'h0 *) + reg n_n6963 = 1'h0; + (* init = 1'h0 *) + reg n_n6968 = 1'h0; + (* init = 1'h0 *) + reg n_n6974 = 1'h0; + (* init = 1'h0 *) + reg n_n6976 = 1'h0; + (* init = 1'h0 *) + reg n_n6980 = 1'h0; + (* init = 1'h0 *) + reg n_n6984 = 1'h0; + (* init = 1'h0 *) + reg n_n6986 = 1'h0; + (* init = 1'h0 *) + reg n_n6988 = 1'h0; + (* init = 1'h0 *) + reg n_n6991 = 1'h0; + (* init = 1'h0 *) + reg n_n7003 = 1'h0; + (* init = 1'h0 *) + reg n_n7013 = 1'h0; + (* init = 1'h0 *) + reg n_n7017 = 1'h0; + (* init = 1'h0 *) + reg n_n7019 = 1'h0; + (* init = 1'h0 *) + reg n_n7022 = 1'h0; + (* init = 1'h0 *) + reg n_n7024 = 1'h0; + (* init = 1'h0 *) + reg n_n7026 = 1'h0; + (* init = 1'h0 *) + reg n_n7033 = 1'h0; + (* init = 1'h0 *) + reg n_n7050 = 1'h0; + (* init = 1'h0 *) + reg n_n7052 = 1'h0; + (* init = 1'h0 *) + reg n_n7054 = 1'h0; + (* init = 1'h0 *) + reg n_n7065 = 1'h0; + (* init = 1'h0 *) + reg n_n7069 = 1'h0; + (* init = 1'h0 *) + reg n_n7074 = 1'h0; + (* init = 1'h0 *) + reg n_n7076 = 1'h0; + (* init = 1'h0 *) + reg n_n7079 = 1'h0; + (* init = 1'h0 *) + reg n_n7083 = 1'h0; + (* init = 1'h0 *) + reg n_n7102 = 1'h0; + (* init = 1'h0 *) + reg n_n7108 = 1'h0; + (* init = 1'h0 *) + reg n_n7111 = 1'h0; + (* init = 1'h0 *) + reg n_n7117 = 1'h0; + (* init = 1'h0 *) + reg n_n7121 = 1'h0; + (* init = 1'h0 *) + reg n_n7130 = 1'h0; + (* init = 1'h0 *) + reg n_n7136 = 1'h0; + (* init = 1'h0 *) + reg n_n7140 = 1'h0; + (* init = 1'h0 *) + reg n_n7146 = 1'h0; + (* init = 1'h0 *) + reg n_n7148 = 1'h0; + (* init = 1'h0 *) + reg n_n7150 = 1'h0; + (* init = 1'h0 *) + reg n_n7154 = 1'h0; + (* init = 1'h0 *) + reg n_n7156 = 1'h0; + (* init = 1'h0 *) + reg n_n7160 = 1'h0; + (* init = 1'h0 *) + reg n_n7174 = 1'h0; + (* init = 1'h0 *) + reg n_n7176 = 1'h0; + (* init = 1'h0 *) + reg n_n7179 = 1'h0; + (* init = 1'h0 *) + reg n_n7181 = 1'h0; + (* init = 1'h0 *) + reg n_n7183 = 1'h0; + (* init = 1'h0 *) + reg n_n7190 = 1'h0; + (* init = 1'h0 *) + reg n_n7203 = 1'h0; + (* init = 1'h0 *) + reg n_n7209 = 1'h0; + (* init = 1'h0 *) + reg n_n7217 = 1'h0; + (* init = 1'h0 *) + reg n_n7225 = 1'h0; + (* init = 1'h0 *) + reg n_n7231 = 1'h0; + (* init = 1'h0 *) + reg n_n7236 = 1'h0; + (* init = 1'h0 *) + reg n_n7242 = 1'h0; + (* init = 1'h0 *) + reg n_n7244 = 1'h0; + (* init = 1'h0 *) + reg n_n7246 = 1'h0; + (* init = 1'h0 *) + reg n_n7252 = 1'h0; + (* init = 1'h0 *) + reg n_n7256 = 1'h0; + (* init = 1'h0 *) + reg n_n7261 = 1'h0; + (* init = 1'h0 *) + reg n_n7271 = 1'h0; + (* init = 1'h0 *) + reg n_n7276 = 1'h0; + (* init = 1'h0 *) + reg n_n7284 = 1'h0; + (* init = 1'h0 *) + reg n_n7286 = 1'h0; + (* init = 1'h0 *) + reg n_n7288 = 1'h0; + (* init = 1'h0 *) + reg n_n7291 = 1'h0; + (* init = 1'h0 *) + reg n_n7306 = 1'h0; + (* init = 1'h0 *) + reg n_n7308 = 1'h0; + (* init = 1'h0 *) + reg n_n7310 = 1'h0; + (* init = 1'h0 *) + reg n_n7315 = 1'h0; + (* init = 1'h0 *) + reg n_n7324 = 1'h0; + (* init = 1'h0 *) + reg n_n7330 = 1'h0; + (* init = 1'h0 *) + reg n_n7332 = 1'h0; + (* init = 1'h0 *) + reg n_n7334 = 1'h0; + (* init = 1'h0 *) + reg n_n7336 = 1'h0; + (* init = 1'h0 *) + reg n_n7338 = 1'h0; + (* init = 1'h0 *) + reg n_n7341 = 1'h0; + (* init = 1'h0 *) + reg n_n7342 = 1'h0; + (* init = 1'h0 *) + reg n_n7344 = 1'h0; + (* init = 1'h0 *) + reg n_n7346 = 1'h0; + (* init = 1'h0 *) + reg n_n7360 = 1'h0; + (* init = 1'h0 *) + reg n_n7362 = 1'h0; + (* init = 1'h0 *) + reg n_n7366 = 1'h0; + (* init = 1'h0 *) + reg n_n7373 = 1'h0; + (* init = 1'h0 *) + reg n_n7374 = 1'h0; + (* init = 1'h0 *) + reg n_n7375 = 1'h0; + (* init = 1'h0 *) + reg n_n7376 = 1'h0; + (* init = 1'h0 *) + reg n_n7381 = 1'h0; + (* init = 1'h0 *) + reg n_n7384 = 1'h0; + (* init = 1'h0 *) + reg n_n7387 = 1'h0; + (* init = 1'h0 *) + reg n_n7390 = 1'h0; + (* init = 1'h0 *) + reg n_n7392 = 1'h0; + (* init = 1'h0 *) + reg n_n7395 = 1'h0; + (* init = 1'h0 *) + reg n_n7402 = 1'h0; + (* init = 1'h0 *) + reg n_n7409 = 1'h0; + (* init = 1'h0 *) + reg n_n7411 = 1'h0; + (* init = 1'h0 *) + reg n_n7415 = 1'h0; + (* init = 1'h0 *) + reg n_n7420 = 1'h0; + (* init = 1'h0 *) + reg n_n7424 = 1'h0; + (* init = 1'h0 *) + reg n_n7428 = 1'h0; + (* init = 1'h0 *) + reg n_n7429 = 1'h0; + (* init = 1'h0 *) + reg n_n7435 = 1'h0; + (* init = 1'h0 *) + reg n_n7444 = 1'h0; + (* init = 1'h0 *) + reg n_n7452 = 1'h0; + (* init = 1'h0 *) + reg n_n7453 = 1'h0; + (* init = 1'h0 *) + reg n_n7454 = 1'h0; + (* init = 1'h0 *) + reg n_n7462 = 1'h0; + (* init = 1'h0 *) + reg n_n7464 = 1'h0; + (* init = 1'h0 *) + reg n_n7467 = 1'h0; + (* init = 1'h0 *) + reg n_n7474 = 1'h0; + (* init = 1'h0 *) + reg n_n7476 = 1'h0; + (* init = 1'h0 *) + reg n_n7485 = 1'h0; + (* init = 1'h0 *) + reg n_n7487 = 1'h0; + (* init = 1'h0 *) + reg n_n7491 = 1'h0; + (* init = 1'h0 *) + reg n_n7493 = 1'h0; + (* init = 1'h0 *) + reg n_n7498 = 1'h0; + (* init = 1'h0 *) + reg n_n7500 = 1'h0; + (* init = 1'h0 *) + reg n_n7507 = 1'h0; + (* init = 1'h0 *) + reg n_n7509 = 1'h0; + (* init = 1'h0 *) + reg n_n7510 = 1'h0; + (* init = 1'h0 *) + reg n_n7511 = 1'h0; + (* init = 1'h0 *) + reg n_n7514 = 1'h0; + (* init = 1'h0 *) + reg n_n7522 = 1'h0; + (* init = 1'h0 *) + reg n_n7527 = 1'h0; + (* init = 1'h0 *) + reg n_n7546 = 1'h0; + (* init = 1'h0 *) + reg n_n7552 = 1'h0; + (* init = 1'h0 *) + reg n_n7553 = 1'h0; + (* init = 1'h0 *) + reg n_n7554 = 1'h0; + (* init = 1'h0 *) + reg n_n7556 = 1'h0; + (* init = 1'h0 *) + reg n_n7558 = 1'h0; + (* init = 1'h0 *) + reg n_n7561 = 1'h0; + (* init = 1'h0 *) + reg n_n7570 = 1'h0; + (* init = 1'h0 *) + reg n_n7581 = 1'h0; + (* init = 1'h0 *) + reg n_n7582 = 1'h0; + (* init = 1'h0 *) + reg n_n7583 = 1'h0; + (* init = 1'h0 *) + reg n_n7584 = 1'h0; + (* init = 1'h0 *) + reg n_n7586 = 1'h0; + (* init = 1'h0 *) + reg n_n7588 = 1'h0; + (* init = 1'h0 *) + reg n_n7598 = 1'h0; + (* init = 1'h0 *) + reg n_n7599 = 1'h0; + (* init = 1'h0 *) + reg n_n7600 = 1'h0; + (* init = 1'h0 *) + reg n_n7601 = 1'h0; + (* init = 1'h0 *) + reg n_n7602 = 1'h0; + (* init = 1'h0 *) + reg n_n7603 = 1'h0; + (* init = 1'h0 *) + reg n_n7604 = 1'h0; + (* init = 1'h0 *) + reg n_n7606 = 1'h0; + (* init = 1'h0 *) + reg n_n7622 = 1'h0; + (* init = 1'h0 *) + reg n_n7624 = 1'h0; + (* init = 1'h0 *) + reg n_n7626 = 1'h0; + (* init = 1'h0 *) + reg n_n7627 = 1'h0; + (* init = 1'h0 *) + reg n_n7628 = 1'h0; + (* init = 1'h0 *) + reg n_n7629 = 1'h0; + (* init = 1'h0 *) + reg n_n7630 = 1'h0; + (* init = 1'h0 *) + reg n_n7635 = 1'h0; + (* init = 1'h0 *) + reg n_n7640 = 1'h0; + (* init = 1'h0 *) + reg n_n7641 = 1'h0; + (* init = 1'h0 *) + reg n_n7642 = 1'h0; + (* init = 1'h0 *) + reg n_n7643 = 1'h0; + (* init = 1'h0 *) + reg n_n7644 = 1'h0; + (* init = 1'h0 *) + reg n_n7649 = 1'h0; + (* init = 1'h0 *) + reg n_n7650 = 1'h0; + (* init = 1'h0 *) + reg n_n7651 = 1'h0; + (* init = 1'h0 *) + reg n_n7652 = 1'h0; + (* init = 1'h0 *) + reg n_n7653 = 1'h0; + (* init = 1'h0 *) + reg n_n7654 = 1'h0; + (* init = 1'h0 *) + reg n_n7655 = 1'h0; + (* init = 1'h0 *) + reg n_n7656 = 1'h0; + (* init = 1'h0 *) + reg n_n7657 = 1'h0; + (* init = 1'h0 *) + reg n_n7659 = 1'h0; + (* init = 1'h0 *) + reg n_n7661 = 1'h0; + (* init = 1'h0 *) + reg n_n7664 = 1'h0; + (* init = 1'h0 *) + reg n_n7665 = 1'h0; + (* init = 1'h0 *) + reg n_n7666 = 1'h0; + (* init = 1'h0 *) + reg n_n7667 = 1'h0; + (* init = 1'h0 *) + reg n_n7668 = 1'h0; + (* init = 1'h0 *) + reg n_n7670 = 1'h0; + (* init = 1'h0 *) + reg n_n7674 = 1'h0; + (* init = 1'h0 *) + reg n_n7678 = 1'h0; + (* init = 1'h0 *) + reg n_n7681 = 1'h0; + (* init = 1'h0 *) + reg n_n7682 = 1'h0; + (* init = 1'h0 *) + reg n_n7683 = 1'h0; + (* init = 1'h0 *) + reg n_n7684 = 1'h0; + (* init = 1'h0 *) + reg n_n7685 = 1'h0; + (* init = 1'h0 *) + reg n_n7686 = 1'h0; + (* init = 1'h0 *) + reg n_n7687 = 1'h0; + (* init = 1'h0 *) + reg n_n7688 = 1'h0; + (* init = 1'h0 *) + reg n_n7689 = 1'h0; + (* init = 1'h0 *) + reg n_n7691 = 1'h0; + (* init = 1'h0 *) + reg n_n7692 = 1'h0; + (* init = 1'h0 *) + reg n_n7693 = 1'h0; + (* init = 1'h0 *) + reg n_n7694 = 1'h0; + (* init = 1'h0 *) + reg n_n7695 = 1'h0; + (* init = 1'h0 *) + reg n_n7696 = 1'h0; + (* init = 1'h0 *) + reg n_n7697 = 1'h0; + (* init = 1'h0 *) + reg n_n7699 = 1'h0; + (* init = 1'h0 *) + reg n_n7701 = 1'h0; + (* init = 1'h0 *) + reg n_n7702 = 1'h0; + (* init = 1'h0 *) + reg n_n7703 = 1'h0; + (* init = 1'h0 *) + reg n_n7704 = 1'h0; + (* init = 1'h0 *) + reg n_n7706 = 1'h0; + (* init = 1'h0 *) + reg n_n7707 = 1'h0; + (* init = 1'h0 *) + reg n_n7708 = 1'h0; + (* init = 1'h0 *) + reg n_n7709 = 1'h0; + (* init = 1'h0 *) + reg n_n7710 = 1'h0; + (* init = 1'h0 *) + reg n_n7711 = 1'h0; + (* init = 1'h0 *) + reg n_n7712 = 1'h0; + (* init = 1'h0 *) + reg n_n7713 = 1'h0; + (* init = 1'h0 *) + reg n_n7715 = 1'h0; + (* init = 1'h0 *) + reg n_n7717 = 1'h0; + (* init = 1'h0 *) + reg n_n7726 = 1'h0; + (* init = 1'h0 *) + reg n_n7728 = 1'h0; + (* init = 1'h0 *) + reg n_n7732 = 1'h0; + (* init = 1'h0 *) + reg n_n7734 = 1'h0; + (* init = 1'h0 *) + reg n_n7735 = 1'h0; + (* init = 1'h0 *) + reg n_n7736 = 1'h0; + (* init = 1'h0 *) + reg n_n7737 = 1'h0; + (* init = 1'h0 *) + reg n_n7738 = 1'h0; + (* init = 1'h0 *) + reg n_n7739 = 1'h0; + (* init = 1'h0 *) + reg n_n7740 = 1'h0; + (* init = 1'h0 *) + reg n_n7741 = 1'h0; + (* init = 1'h0 *) + reg n_n7742 = 1'h0; + (* init = 1'h0 *) + reg n_n7743 = 1'h0; + (* init = 1'h0 *) + reg n_n7744 = 1'h0; + (* init = 1'h0 *) + reg n_n7756 = 1'h0; + (* init = 1'h0 *) + reg n_n7757 = 1'h0; + (* init = 1'h0 *) + reg n_n7758 = 1'h0; + (* init = 1'h0 *) + reg n_n7759 = 1'h0; + (* init = 1'h0 *) + reg n_n7760 = 1'h0; + (* init = 1'h0 *) + reg n_n7761 = 1'h0; + (* init = 1'h0 *) + reg n_n7762 = 1'h0; + (* init = 1'h0 *) + reg n_n7763 = 1'h0; + (* init = 1'h0 *) + reg n_n7764 = 1'h0; + (* init = 1'h0 *) + reg n_n7765 = 1'h0; + (* init = 1'h0 *) + reg n_n7766 = 1'h0; + (* init = 1'h0 *) + reg n_n7768 = 1'h0; + (* init = 1'h0 *) + reg n_n7769 = 1'h0; + (* init = 1'h0 *) + reg n_n7770 = 1'h0; + (* init = 1'h0 *) + reg n_n7771 = 1'h0; + (* init = 1'h0 *) + reg n_n7775 = 1'h0; + (* init = 1'h0 *) + reg n_n7777 = 1'h0; + (* init = 1'h0 *) + reg n_n7779 = 1'h0; + (* init = 1'h0 *) + reg n_n7781 = 1'h0; + (* init = 1'h0 *) + reg n_n7783 = 1'h0; + (* init = 1'h0 *) + reg n_n7788 = 1'h0; + (* init = 1'h0 *) + reg n_n7789 = 1'h0; + (* init = 1'h0 *) + reg n_n7790 = 1'h0; + (* init = 1'h0 *) + reg n_n7791 = 1'h0; + (* init = 1'h0 *) + reg n_n7792 = 1'h0; + (* init = 1'h0 *) + reg n_n7793 = 1'h0; + (* init = 1'h0 *) + reg n_n7798 = 1'h0; + (* init = 1'h0 *) + reg n_n7803 = 1'h0; + (* init = 1'h0 *) + reg n_n7806 = 1'h0; + (* init = 1'h0 *) + reg n_n7807 = 1'h0; + (* init = 1'h0 *) + reg n_n7808 = 1'h0; + (* init = 1'h0 *) + reg n_n7809 = 1'h0; + (* init = 1'h0 *) + reg n_n7810 = 1'h0; + (* init = 1'h0 *) + reg n_n7811 = 1'h0; + (* init = 1'h0 *) + reg n_n7812 = 1'h0; + (* init = 1'h0 *) + reg n_n7813 = 1'h0; + (* init = 1'h0 *) + reg n_n7814 = 1'h0; + (* init = 1'h0 *) + reg n_n7815 = 1'h0; + (* init = 1'h0 *) + reg n_n7816 = 1'h0; + (* init = 1'h0 *) + reg n_n7817 = 1'h0; + (* init = 1'h0 *) + reg n_n7819 = 1'h0; + (* init = 1'h0 *) + reg n_n7820 = 1'h0; + (* init = 1'h0 *) + reg n_n7821 = 1'h0; + (* init = 1'h0 *) + reg n_n7822 = 1'h0; + (* init = 1'h0 *) + reg n_n7823 = 1'h0; + (* init = 1'h0 *) + reg n_n7824 = 1'h0; + (* init = 1'h0 *) + reg n_n7825 = 1'h0; + (* init = 1'h0 *) + reg n_n7826 = 1'h0; + (* init = 1'h0 *) + reg n_n7827 = 1'h0; + (* init = 1'h0 *) + reg n_n7831 = 1'h0; + (* init = 1'h0 *) + reg n_n7835 = 1'h0; + (* init = 1'h0 *) + reg n_n7837 = 1'h0; + (* init = 1'h0 *) + reg n_n7843 = 1'h0; + (* init = 1'h0 *) + reg n_n7844 = 1'h0; + (* init = 1'h0 *) + reg n_n7845 = 1'h0; + (* init = 1'h0 *) + reg n_n7846 = 1'h0; + (* init = 1'h0 *) + reg n_n7847 = 1'h0; + (* init = 1'h0 *) + reg n_n7848 = 1'h0; + (* init = 1'h0 *) + reg n_n7849 = 1'h0; + (* init = 1'h0 *) + reg n_n7850 = 1'h0; + (* init = 1'h0 *) + reg n_n7852 = 1'h0; + (* init = 1'h0 *) + reg n_n7853 = 1'h0; + (* init = 1'h0 *) + reg n_n7854 = 1'h0; + (* init = 1'h0 *) + reg n_n7857 = 1'h0; + (* init = 1'h0 *) + reg n_n7859 = 1'h0; + (* init = 1'h0 *) + reg n_n7862 = 1'h0; + (* init = 1'h0 *) + reg n_n7866 = 1'h0; + (* init = 1'h0 *) + reg n_n7873 = 1'h0; + (* init = 1'h0 *) + reg n_n7874 = 1'h0; + (* init = 1'h0 *) + reg n_n7875 = 1'h0; + (* init = 1'h0 *) + reg n_n7876 = 1'h0; + (* init = 1'h0 *) + reg n_n7877 = 1'h0; + (* init = 1'h0 *) + reg n_n7878 = 1'h0; + (* init = 1'h0 *) + reg n_n7879 = 1'h0; + (* init = 1'h0 *) + reg n_n7880 = 1'h0; + (* init = 1'h0 *) + reg n_n7881 = 1'h0; + (* init = 1'h0 *) + reg n_n7885 = 1'h0; + (* init = 1'h0 *) + reg n_n7886 = 1'h0; + (* init = 1'h0 *) + reg n_n7887 = 1'h0; + (* init = 1'h0 *) + reg n_n7888 = 1'h0; + (* init = 1'h0 *) + reg n_n7889 = 1'h0; + (* init = 1'h0 *) + reg n_n7890 = 1'h0; + (* init = 1'h0 *) + reg n_n7896 = 1'h0; + (* init = 1'h0 *) + reg n_n7898 = 1'h0; + (* init = 1'h0 *) + reg n_n7901 = 1'h0; + (* init = 1'h0 *) + reg n_n7903 = 1'h0; + (* init = 1'h0 *) + reg n_n7905 = 1'h0; + (* init = 1'h0 *) + reg n_n7908 = 1'h0; + (* init = 1'h0 *) + reg n_n7909 = 1'h0; + (* init = 1'h0 *) + reg n_n7910 = 1'h0; + (* init = 1'h0 *) + reg n_n7911 = 1'h0; + (* init = 1'h0 *) + reg n_n7912 = 1'h0; + (* init = 1'h0 *) + reg n_n7913 = 1'h0; + (* init = 1'h0 *) + reg n_n7914 = 1'h0; + (* init = 1'h0 *) + reg n_n7918 = 1'h0; + (* init = 1'h0 *) + reg n_n7920 = 1'h0; + (* init = 1'h0 *) + reg n_n7923 = 1'h0; + (* init = 1'h0 *) + reg n_n7925 = 1'h0; + (* init = 1'h0 *) + reg n_n7927 = 1'h0; + (* init = 1'h0 *) + reg n_n7928 = 1'h0; + (* init = 1'h0 *) + reg n_n7929 = 1'h0; + (* init = 1'h0 *) + reg n_n7930 = 1'h0; + (* init = 1'h0 *) + reg n_n7931 = 1'h0; + (* init = 1'h0 *) + reg n_n7932 = 1'h0; + (* init = 1'h0 *) + reg n_n7933 = 1'h0; + (* init = 1'h0 *) + reg n_n7934 = 1'h0; + (* init = 1'h0 *) + reg n_n7935 = 1'h0; + (* init = 1'h0 *) + reg n_n7936 = 1'h0; + (* init = 1'h0 *) + reg n_n7937 = 1'h0; + (* init = 1'h0 *) + reg n_n7944 = 1'h0; + (* init = 1'h0 *) + reg n_n7946 = 1'h0; + (* init = 1'h0 *) + reg n_n7947 = 1'h0; + (* init = 1'h0 *) + reg n_n7948 = 1'h0; + (* init = 1'h0 *) + reg n_n7949 = 1'h0; + (* init = 1'h0 *) + reg n_n7950 = 1'h0; + (* init = 1'h0 *) + reg n_n7951 = 1'h0; + (* init = 1'h0 *) + reg n_n7952 = 1'h0; + (* init = 1'h0 *) + reg n_n7953 = 1'h0; + (* init = 1'h0 *) + reg n_n7954 = 1'h0; + (* init = 1'h0 *) + reg n_n7955 = 1'h0; + (* init = 1'h0 *) + reg n_n7956 = 1'h0; + (* init = 1'h0 *) + reg n_n7959 = 1'h0; + (* init = 1'h0 *) + reg n_n7961 = 1'h0; + (* init = 1'h0 *) + reg n_n7962 = 1'h0; + (* init = 1'h0 *) + reg n_n7964 = 1'h0; + (* init = 1'h0 *) + reg n_n7966 = 1'h0; + (* init = 1'h0 *) + reg n_n7967 = 1'h0; + (* init = 1'h0 *) + reg n_n7968 = 1'h0; + (* init = 1'h0 *) + reg n_n7969 = 1'h0; + (* init = 1'h0 *) + reg n_n7970 = 1'h0; + (* init = 1'h0 *) + reg n_n7971 = 1'h0; + (* init = 1'h0 *) + reg n_n7976 = 1'h0; + (* init = 1'h0 *) + reg n_n7978 = 1'h0; + (* init = 1'h0 *) + reg n_n7980 = 1'h0; + (* init = 1'h0 *) + reg n_n7983 = 1'h0; + (* init = 1'h0 *) + reg n_n7985 = 1'h0; + (* init = 1'h0 *) + reg n_n7988 = 1'h0; + (* init = 1'h0 *) + reg n_n7990 = 1'h0; + (* init = 1'h0 *) + reg n_n7993 = 1'h0; + (* init = 1'h0 *) + reg n_n7995 = 1'h0; + (* init = 1'h0 *) + reg n_n8000 = 1'h0; + (* init = 1'h0 *) + reg n_n8001 = 1'h0; + (* init = 1'h0 *) + reg n_n8002 = 1'h0; + (* init = 1'h0 *) + reg n_n8003 = 1'h0; + (* init = 1'h0 *) + reg n_n8004 = 1'h0; + (* init = 1'h0 *) + reg n_n8005 = 1'h0; + (* init = 1'h0 *) + reg n_n8006 = 1'h0; + (* init = 1'h0 *) + reg n_n8007 = 1'h0; + (* init = 1'h0 *) + reg n_n8009 = 1'h0; + (* init = 1'h0 *) + reg n_n8011 = 1'h0; + (* init = 1'h0 *) + reg n_n8014 = 1'h0; + (* init = 1'h0 *) + reg n_n8016 = 1'h0; + (* init = 1'h0 *) + reg n_n8022 = 1'h0; + (* init = 1'h0 *) + reg n_n8024 = 1'h0; + (* init = 1'h0 *) + reg n_n8033 = 1'h0; + (* init = 1'h0 *) + reg n_n8035 = 1'h0; + (* init = 1'h0 *) + reg n_n8037 = 1'h0; + (* init = 1'h0 *) + reg n_n8042 = 1'h0; + (* init = 1'h0 *) + reg n_n8045 = 1'h0; + (* init = 1'h0 *) + reg n_n8047 = 1'h0; + (* init = 1'h0 *) + reg n_n8049 = 1'h0; + (* init = 1'h0 *) + reg n_n8051 = 1'h0; + (* init = 1'h0 *) + reg n_n8053 = 1'h0; + (* init = 1'h0 *) + reg n_n8055 = 1'h0; + (* init = 1'h0 *) + reg n_n8058 = 1'h0; + (* init = 1'h0 *) + reg n_n8061 = 1'h0; + (* init = 1'h0 *) + reg n_n8064 = 1'h0; + (* init = 1'h0 *) + reg n_n8066 = 1'h0; + (* init = 1'h0 *) + reg n_n8073 = 1'h0; + (* init = 1'h0 *) + reg n_n8075 = 1'h0; + (* init = 1'h0 *) + reg n_n8078 = 1'h0; + (* init = 1'h0 *) + reg n_n8081 = 1'h0; + (* init = 1'h0 *) + reg n_n8086 = 1'h0; + (* init = 1'h0 *) + reg n_n8088 = 1'h0; + (* init = 1'h0 *) + reg n_n8091 = 1'h0; + (* init = 1'h0 *) + reg n_n8093 = 1'h0; + (* init = 1'h0 *) + reg n_n8095 = 1'h0; + (* init = 1'h0 *) + reg n_n8100 = 1'h0; + (* init = 1'h0 *) + reg n_n8102 = 1'h0; + (* init = 1'h0 *) + reg n_n8104 = 1'h0; + (* init = 1'h0 *) + reg n_n8106 = 1'h0; + (* init = 1'h0 *) + reg n_n8108 = 1'h0; + (* init = 1'h0 *) + reg n_n8110 = 1'h0; + (* init = 1'h0 *) + reg n_n8112 = 1'h0; + (* init = 1'h0 *) + reg n_n8114 = 1'h0; + (* init = 1'h0 *) + reg n_n8116 = 1'h0; + (* init = 1'h0 *) + reg n_n8118 = 1'h0; + (* init = 1'h0 *) + reg n_n8121 = 1'h0; + (* init = 1'h0 *) + reg n_n8132 = 1'h0; + (* init = 1'h0 *) + reg n_n8135 = 1'h0; + (* init = 1'h0 *) + reg n_n8139 = 1'h0; + (* init = 1'h0 *) + reg n_n8141 = 1'h0; + (* init = 1'h0 *) + reg n_n8146 = 1'h0; + (* init = 1'h0 *) + reg n_n8150 = 1'h0; + (* init = 1'h0 *) + reg n_n8151 = 1'h0; + (* init = 1'h0 *) + reg n_n8152 = 1'h0; + (* init = 1'h0 *) + reg n_n8153 = 1'h0; + (* init = 1'h0 *) + reg n_n8171 = 1'h0; + (* init = 1'h0 *) + reg n_n8173 = 1'h0; + (* init = 1'h0 *) + reg n_n8175 = 1'h0; + (* init = 1'h0 *) + reg n_n8177 = 1'h0; + (* init = 1'h0 *) + reg n_n8185 = 1'h0; + (* init = 1'h0 *) + reg n_n8188 = 1'h0; + (* init = 1'h0 *) + reg n_n8192 = 1'h0; + (* init = 1'h0 *) + reg n_n8195 = 1'h0; + (* init = 1'h0 *) + reg n_n8196 = 1'h0; + (* init = 1'h0 *) + reg n_n8197 = 1'h0; + (* init = 1'h0 *) + reg n_n8198 = 1'h0; + (* init = 1'h0 *) + reg n_n8199 = 1'h0; + (* init = 1'h0 *) + reg n_n8200 = 1'h0; + (* init = 1'h0 *) + reg n_n8201 = 1'h0; + (* init = 1'h0 *) + reg n_n8202 = 1'h0; + (* init = 1'h0 *) + reg n_n8203 = 1'h0; + (* init = 1'h0 *) + reg n_n8206 = 1'h0; + (* init = 1'h0 *) + reg n_n8208 = 1'h0; + (* init = 1'h0 *) + reg n_n8210 = 1'h0; + (* init = 1'h0 *) + reg n_n8213 = 1'h0; + (* init = 1'h0 *) + reg n_n8216 = 1'h0; + (* init = 1'h0 *) + reg n_n8219 = 1'h0; + (* init = 1'h0 *) + reg n_n8221 = 1'h0; + (* init = 1'h0 *) + reg n_n8222 = 1'h0; + (* init = 1'h0 *) + reg n_n8223 = 1'h0; + (* init = 1'h0 *) + reg n_n8224 = 1'h0; + (* init = 1'h0 *) + reg n_n8225 = 1'h0; + (* init = 1'h0 *) + reg n_n8226 = 1'h0; + (* init = 1'h0 *) + reg n_n8227 = 1'h0; + (* init = 1'h0 *) + reg n_n8230 = 1'h0; + (* init = 1'h0 *) + reg n_n8233 = 1'h0; + (* init = 1'h0 *) + reg n_n8235 = 1'h0; + (* init = 1'h0 *) + reg n_n8236 = 1'h0; + (* init = 1'h0 *) + reg n_n8237 = 1'h0; + (* init = 1'h0 *) + reg n_n8238 = 1'h0; + (* init = 1'h0 *) + reg n_n8239 = 1'h0; + (* init = 1'h0 *) + reg n_n8240 = 1'h0; + (* init = 1'h0 *) + reg n_n8241 = 1'h0; + (* init = 1'h0 *) + reg n_n8243 = 1'h0; + (* init = 1'h0 *) + reg n_n8245 = 1'h0; + (* init = 1'h0 *) + reg n_n8247 = 1'h0; + (* init = 1'h0 *) + reg n_n8249 = 1'h0; + (* init = 1'h0 *) + reg n_n8251 = 1'h0; + (* init = 1'h0 *) + reg n_n8253 = 1'h0; + (* init = 1'h0 *) + reg n_n8256 = 1'h0; + (* init = 1'h0 *) + reg n_n8258 = 1'h0; + (* init = 1'h0 *) + reg n_n8260 = 1'h0; + (* init = 1'h0 *) + reg n_n8263 = 1'h0; + (* init = 1'h0 *) + reg n_n8267 = 1'h0; + (* init = 1'h0 *) + reg n_n8269 = 1'h0; + (* init = 1'h0 *) + reg n_n8270 = 1'h0; + (* init = 1'h0 *) + reg n_n8271 = 1'h0; + (* init = 1'h0 *) + reg n_n8272 = 1'h0; + (* init = 1'h0 *) + reg n_n8273 = 1'h0; + (* init = 1'h0 *) + reg n_n8274 = 1'h0; + (* init = 1'h0 *) + reg n_n8276 = 1'h0; + (* init = 1'h0 *) + reg n_n8277 = 1'h0; + (* init = 1'h0 *) + reg n_n8278 = 1'h0; + (* init = 1'h0 *) + reg n_n8279 = 1'h0; + (* init = 1'h0 *) + reg n_n8280 = 1'h0; + (* init = 1'h0 *) + reg n_n8281 = 1'h0; + (* init = 1'h0 *) + reg n_n8282 = 1'h0; + (* init = 1'h0 *) + reg n_n8290 = 1'h0; + (* init = 1'h0 *) + reg n_n8296 = 1'h0; + (* init = 1'h0 *) + reg n_n8298 = 1'h0; + (* init = 1'h0 *) + reg n_n8303 = 1'h0; + (* init = 1'h0 *) + reg n_n8308 = 1'h0; + (* init = 1'h0 *) + reg n_n8312 = 1'h0; + (* init = 1'h0 *) + reg n_n8326 = 1'h0; + (* init = 1'h0 *) + reg n_n8328 = 1'h0; + (* init = 1'h0 *) + reg n_n8333 = 1'h0; + (* init = 1'h0 *) + reg n_n8340 = 1'h0; + (* init = 1'h0 *) + reg n_n8344 = 1'h0; + (* init = 1'h0 *) + reg n_n8348 = 1'h0; + (* init = 1'h0 *) + reg n_n8354 = 1'h0; + (* init = 1'h0 *) + reg n_n8361 = 1'h0; + (* init = 1'h0 *) + reg n_n8366 = 1'h0; + (* init = 1'h0 *) + reg n_n8369 = 1'h0; + (* init = 1'h0 *) + reg n_n8371 = 1'h0; + (* init = 1'h0 *) + reg n_n8375 = 1'h0; + (* init = 1'h0 *) + reg n_n8377 = 1'h0; + (* init = 1'h0 *) + reg n_n8381 = 1'h0; + (* init = 1'h0 *) + reg n_n8384 = 1'h0; + (* init = 1'h0 *) + reg n_n8389 = 1'h0; + (* init = 1'h0 *) + reg n_n8392 = 1'h0; + (* init = 1'h0 *) + reg n_n8394 = 1'h0; + (* init = 1'h0 *) + reg n_n8396 = 1'h0; + (* init = 1'h0 *) + reg n_n8402 = 1'h0; + (* init = 1'h0 *) + reg n_n8406 = 1'h0; + (* init = 1'h0 *) + reg n_n8408 = 1'h0; + (* init = 1'h0 *) + reg n_n8410 = 1'h0; + (* init = 1'h0 *) + reg n_n8414 = 1'h0; + (* init = 1'h0 *) + reg n_n8416 = 1'h0; + (* init = 1'h0 *) + reg n_n8419 = 1'h0; + (* init = 1'h0 *) + reg n_n8423 = 1'h0; + (* init = 1'h0 *) + reg n_n8425 = 1'h0; + (* init = 1'h0 *) + reg n_n8428 = 1'h0; + (* init = 1'h0 *) + reg n_n8430 = 1'h0; + (* init = 1'h0 *) + reg n_n8436 = 1'h0; + (* init = 1'h0 *) + reg n_n8439 = 1'h0; + (* init = 1'h0 *) + reg n_n8441 = 1'h0; + (* init = 1'h0 *) + reg n_n8445 = 1'h0; + (* init = 1'h0 *) + reg n_n8447 = 1'h0; + (* init = 1'h0 *) + reg n_n8449 = 1'h0; + (* init = 1'h0 *) + reg n_n8454 = 1'h0; + (* init = 1'h0 *) + reg n_n8456 = 1'h0; + (* init = 1'h0 *) + reg n_n8462 = 1'h0; + (* init = 1'h0 *) + reg n_n8464 = 1'h0; + (* init = 1'h0 *) + reg n_n8466 = 1'h0; + (* init = 1'h0 *) + reg n_n8468 = 1'h0; + (* init = 1'h0 *) + reg n_n8470 = 1'h0; + (* init = 1'h0 *) + reg n_n8473 = 1'h0; + (* init = 1'h0 *) + reg n_n8477 = 1'h0; + (* init = 1'h0 *) + reg n_n8480 = 1'h0; + (* init = 1'h0 *) + reg n_n8482 = 1'h0; + (* init = 1'h0 *) + reg n_n8486 = 1'h0; + (* init = 1'h0 *) + reg n_n8488 = 1'h0; + (* init = 1'h0 *) + reg n_n8491 = 1'h0; + (* init = 1'h0 *) + reg n_n8499 = 1'h0; + (* init = 1'h0 *) + reg n_n8502 = 1'h0; + (* init = 1'h0 *) + reg n_n8504 = 1'h0; + (* init = 1'h0 *) + reg n_n8506 = 1'h0; + (* init = 1'h0 *) + reg n_n8508 = 1'h0; + (* init = 1'h0 *) + reg n_n8510 = 1'h0; + (* init = 1'h0 *) + reg n_n8512 = 1'h0; + (* init = 1'h0 *) + reg n_n8513 = 1'h0; + (* init = 1'h0 *) + reg n_n8514 = 1'h0; + (* init = 1'h0 *) + reg n_n8515 = 1'h0; + (* init = 1'h0 *) + reg n_n8516 = 1'h0; + (* init = 1'h0 *) + reg n_n8519 = 1'h0; + (* init = 1'h0 *) + reg n_n8526 = 1'h0; + (* init = 1'h0 *) + reg n_n8528 = 1'h0; + (* init = 1'h0 *) + reg n_n8529 = 1'h0; + (* init = 1'h0 *) + reg n_n8530 = 1'h0; + (* init = 1'h0 *) + reg n_n8531 = 1'h0; + (* init = 1'h0 *) + reg n_n8533 = 1'h0; + (* init = 1'h0 *) + reg n_n8535 = 1'h0; + (* init = 1'h0 *) + reg n_n8543 = 1'h0; + (* init = 1'h0 *) + reg n_n8545 = 1'h0; + (* init = 1'h0 *) + reg n_n8549 = 1'h0; + (* init = 1'h0 *) + reg n_n8552 = 1'h0; + (* init = 1'h0 *) + reg n_n8557 = 1'h0; + (* init = 1'h0 *) + reg n_n8561 = 1'h0; + (* init = 1'h0 *) + reg n_n8568 = 1'h0; + (* init = 1'h0 *) + reg n_n8570 = 1'h0; + (* init = 1'h0 *) + reg n_n8571 = 1'h0; + (* init = 1'h0 *) + reg n_n8572 = 1'h0; + (* init = 1'h0 *) + reg n_n8573 = 1'h0; + (* init = 1'h0 *) + reg n_n8574 = 1'h0; + (* init = 1'h0 *) + reg n_n8575 = 1'h0; + (* init = 1'h0 *) + reg n_n8577 = 1'h0; + (* init = 1'h0 *) + reg n_n8580 = 1'h0; + (* init = 1'h0 *) + reg n_n8581 = 1'h0; + (* init = 1'h0 *) + reg n_n8582 = 1'h0; + (* init = 1'h0 *) + reg n_n8583 = 1'h0; + (* init = 1'h0 *) + reg n_n8584 = 1'h0; + (* init = 1'h0 *) + reg n_n8586 = 1'h0; + (* init = 1'h0 *) + reg n_n8589 = 1'h0; + (* init = 1'h0 *) + reg n_n8592 = 1'h0; + (* init = 1'h0 *) + reg n_n8597 = 1'h0; + (* init = 1'h0 *) + reg n_n8599 = 1'h0; + (* init = 1'h0 *) + reg n_n8603 = 1'h0; + (* init = 1'h0 *) + reg n_n8605 = 1'h0; + (* init = 1'h0 *) + reg n_n8609 = 1'h0; + (* init = 1'h0 *) + reg n_n8611 = 1'h0; + (* init = 1'h0 *) + reg n_n8613 = 1'h0; + (* init = 1'h0 *) + reg n_n8615 = 1'h0; + (* init = 1'h0 *) + reg n_n8617 = 1'h0; + (* init = 1'h0 *) + reg n_n8619 = 1'h0; + (* init = 1'h0 *) + reg n_n8626 = 1'h0; + (* init = 1'h0 *) + reg n_n8628 = 1'h0; + (* init = 1'h0 *) + reg n_n8631 = 1'h0; + (* init = 1'h0 *) + reg n_n8633 = 1'h0; + (* init = 1'h0 *) + reg n_n8636 = 1'h0; + (* init = 1'h0 *) + reg n_n8638 = 1'h0; + (* init = 1'h0 *) + reg n_n8641 = 1'h0; + (* init = 1'h0 *) + reg n_n8644 = 1'h0; + (* init = 1'h0 *) + reg n_n8646 = 1'h0; + (* init = 1'h0 *) + reg n_n8647 = 1'h0; + (* init = 1'h0 *) + reg n_n8648 = 1'h0; + (* init = 1'h0 *) + reg n_n8649 = 1'h0; + (* init = 1'h0 *) + reg n_n8650 = 1'h0; + (* init = 1'h0 *) + reg n_n8652 = 1'h0; + (* init = 1'h0 *) + reg n_n8655 = 1'h0; + (* init = 1'h0 *) + reg n_n8657 = 1'h0; + (* init = 1'h0 *) + reg n_n8659 = 1'h0; + (* init = 1'h0 *) + reg n_n8661 = 1'h0; + (* init = 1'h0 *) + reg n_n8665 = 1'h0; + (* init = 1'h0 *) + reg n_n8668 = 1'h0; + (* init = 1'h0 *) + reg n_n8670 = 1'h0; + (* init = 1'h0 *) + reg n_n8672 = 1'h0; + (* init = 1'h0 *) + reg n_n8678 = 1'h0; + (* init = 1'h0 *) + reg n_n8681 = 1'h0; + (* init = 1'h0 *) + reg n_n8683 = 1'h0; + (* init = 1'h0 *) + reg n_n8685 = 1'h0; + (* init = 1'h0 *) + reg n_n8691 = 1'h0; + (* init = 1'h0 *) + reg n_n8697 = 1'h0; + (* init = 1'h0 *) + reg n_n8699 = 1'h0; + (* init = 1'h0 *) + reg n_n8702 = 1'h0; + (* init = 1'h0 *) + reg n_n8704 = 1'h0; + (* init = 1'h0 *) + reg n_n8707 = 1'h0; + (* init = 1'h0 *) + reg n_n8710 = 1'h0; + (* init = 1'h0 *) + reg n_n8713 = 1'h0; + (* init = 1'h0 *) + reg n_n8725 = 1'h0; + (* init = 1'h0 *) + reg n_n8727 = 1'h0; + (* init = 1'h0 *) + reg n_n8729 = 1'h0; + (* init = 1'h0 *) + reg n_n8736 = 1'h0; + (* init = 1'h0 *) + reg n_n8739 = 1'h0; + (* init = 1'h0 *) + reg n_n8741 = 1'h0; + (* init = 1'h0 *) + reg n_n8742 = 1'h0; + (* init = 1'h0 *) + reg n_n8743 = 1'h0; + (* init = 1'h0 *) + reg n_n8744 = 1'h0; + (* init = 1'h0 *) + reg n_n8750 = 1'h0; + (* init = 1'h0 *) + reg n_n8753 = 1'h0; + (* init = 1'h0 *) + reg n_n8756 = 1'h0; + (* init = 1'h0 *) + reg n_n8758 = 1'h0; + (* init = 1'h0 *) + reg n_n8760 = 1'h0; + (* init = 1'h0 *) + reg n_n8762 = 1'h0; + (* init = 1'h0 *) + reg n_n8765 = 1'h0; + (* init = 1'h0 *) + reg n_n8770 = 1'h0; + (* init = 1'h0 *) + reg n_n8772 = 1'h0; + (* init = 1'h0 *) + reg n_n8775 = 1'h0; + (* init = 1'h0 *) + reg n_n8777 = 1'h0; + (* init = 1'h0 *) + reg n_n8779 = 1'h0; + (* init = 1'h0 *) + reg n_n8781 = 1'h0; + (* init = 1'h0 *) + reg n_n8786 = 1'h0; + (* init = 1'h0 *) + reg n_n8789 = 1'h0; + (* init = 1'h0 *) + reg n_n8791 = 1'h0; + (* init = 1'h0 *) + reg n_n8794 = 1'h0; + (* init = 1'h0 *) + reg n_n8796 = 1'h0; + (* init = 1'h0 *) + reg n_n8798 = 1'h0; + (* init = 1'h0 *) + reg n_n8801 = 1'h0; + (* init = 1'h0 *) + reg n_n8803 = 1'h0; + (* init = 1'h0 *) + reg n_n8808 = 1'h0; + (* init = 1'h0 *) + reg n_n8809 = 1'h0; + (* init = 1'h0 *) + reg n_n8810 = 1'h0; + (* init = 1'h0 *) + reg n_n8811 = 1'h0; + (* init = 1'h0 *) + reg n_n8817 = 1'h0; + (* init = 1'h0 *) + reg n_n8821 = 1'h0; + (* init = 1'h0 *) + reg n_n8828 = 1'h0; + (* init = 1'h0 *) + reg n_n8831 = 1'h0; + (* init = 1'h0 *) + reg n_n8833 = 1'h0; + (* init = 1'h0 *) + reg n_n8839 = 1'h0; + (* init = 1'h0 *) + reg n_n8841 = 1'h0; + (* init = 1'h0 *) + reg n_n8843 = 1'h0; + (* init = 1'h0 *) + reg n_n8847 = 1'h0; + (* init = 1'h0 *) + reg n_n8850 = 1'h0; + (* init = 1'h0 *) + reg n_n8852 = 1'h0; + (* init = 1'h0 *) + reg n_n8854 = 1'h0; + (* init = 1'h0 *) + reg n_n8856 = 1'h0; + (* init = 1'h0 *) + reg n_n8858 = 1'h0; + (* init = 1'h0 *) + reg n_n8862 = 1'h0; + (* init = 1'h0 *) + reg n_n8864 = 1'h0; + (* init = 1'h0 *) + reg n_n8869 = 1'h0; + (* init = 1'h0 *) + reg n_n8871 = 1'h0; + (* init = 1'h0 *) + reg n_n8875 = 1'h0; + (* init = 1'h0 *) + reg n_n8881 = 1'h0; + (* init = 1'h0 *) + reg n_n8882 = 1'h0; + (* init = 1'h0 *) + reg n_n8883 = 1'h0; + (* init = 1'h0 *) + reg n_n8884 = 1'h0; + (* init = 1'h0 *) + reg n_n8889 = 1'h0; + (* init = 1'h0 *) + reg n_n8891 = 1'h0; + (* init = 1'h0 *) + reg n_n8895 = 1'h0; + (* init = 1'h0 *) + reg n_n8898 = 1'h0; + (* init = 1'h0 *) + reg n_n8900 = 1'h0; + (* init = 1'h0 *) + reg n_n8906 = 1'h0; + (* init = 1'h0 *) + reg n_n8909 = 1'h0; + (* init = 1'h0 *) + reg n_n8911 = 1'h0; + (* init = 1'h0 *) + reg n_n8913 = 1'h0; + (* init = 1'h0 *) + reg n_n8916 = 1'h0; + (* init = 1'h0 *) + reg n_n8918 = 1'h0; + (* init = 1'h0 *) + reg n_n8921 = 1'h0; + (* init = 1'h0 *) + reg n_n8923 = 1'h0; + (* init = 1'h0 *) + reg n_n8929 = 1'h0; + (* init = 1'h0 *) + reg n_n8930 = 1'h0; + (* init = 1'h0 *) + reg n_n8933 = 1'h0; + (* init = 1'h0 *) + reg n_n8935 = 1'h0; + (* init = 1'h0 *) + reg n_n8937 = 1'h0; + (* init = 1'h0 *) + reg n_n8938 = 1'h0; + (* init = 1'h0 *) + reg n_n8939 = 1'h0; + (* init = 1'h0 *) + reg n_n8941 = 1'h0; + (* init = 1'h0 *) + reg n_n8944 = 1'h0; + (* init = 1'h0 *) + reg n_n8946 = 1'h0; + (* init = 1'h0 *) + reg n_n8948 = 1'h0; + (* init = 1'h0 *) + reg n_n8951 = 1'h0; + (* init = 1'h0 *) + reg n_n8957 = 1'h0; + (* init = 1'h0 *) + reg n_n8959 = 1'h0; + (* init = 1'h0 *) + reg n_n8961 = 1'h0; + (* init = 1'h0 *) + reg n_n8964 = 1'h0; + (* init = 1'h0 *) + reg n_n8966 = 1'h0; + (* init = 1'h0 *) + reg n_n8968 = 1'h0; + (* init = 1'h0 *) + reg n_n8970 = 1'h0; + (* init = 1'h0 *) + reg n_n8972 = 1'h0; + (* init = 1'h0 *) + reg n_n8974 = 1'h0; + (* init = 1'h0 *) + reg n_n8978 = 1'h0; + (* init = 1'h0 *) + reg n_n8980 = 1'h0; + (* init = 1'h0 *) + reg n_n8981 = 1'h0; + (* init = 1'h0 *) + reg n_n8982 = 1'h0; + (* init = 1'h0 *) + reg n_n8983 = 1'h0; + (* init = 1'h0 *) + reg n_n8984 = 1'h0; + (* init = 1'h0 *) + reg n_n8986 = 1'h0; + (* init = 1'h0 *) + reg n_n8989 = 1'h0; + (* init = 1'h0 *) + reg n_n8991 = 1'h0; + (* init = 1'h0 *) + reg n_n8993 = 1'h0; + (* init = 1'h0 *) + reg n_n8996 = 1'h0; + (* init = 1'h0 *) + reg n_n8998 = 1'h0; + (* init = 1'h0 *) + reg n_n9000 = 1'h0; + (* init = 1'h0 *) + reg n_n9004 = 1'h0; + (* init = 1'h0 *) + reg n_n9006 = 1'h0; + (* init = 1'h0 *) + reg n_n9008 = 1'h0; + (* init = 1'h0 *) + reg n_n9011 = 1'h0; + (* init = 1'h0 *) + reg n_n9013 = 1'h0; + (* init = 1'h0 *) + reg n_n9015 = 1'h0; + (* init = 1'h0 *) + reg n_n9019 = 1'h0; + (* init = 1'h0 *) + reg n_n9021 = 1'h0; + (* init = 1'h0 *) + reg n_n9023 = 1'h0; + (* init = 1'h0 *) + reg n_n9026 = 1'h0; + (* init = 1'h0 *) + reg n_n9028 = 1'h0; + (* init = 1'h0 *) + reg n_n9031 = 1'h0; + (* init = 1'h0 *) + reg n_n9034 = 1'h0; + (* init = 1'h0 *) + reg n_n9036 = 1'h0; + (* init = 1'h0 *) + reg n_n9041 = 1'h0; + (* init = 1'h0 *) + reg n_n9042 = 1'h0; + (* init = 1'h0 *) + reg n_n9043 = 1'h0; + (* init = 1'h0 *) + reg n_n9044 = 1'h0; + (* init = 1'h0 *) + reg n_n9045 = 1'h0; + (* init = 1'h0 *) + reg n_n9046 = 1'h0; + (* init = 1'h0 *) + reg n_n9047 = 1'h0; + (* init = 1'h0 *) + reg n_n9048 = 1'h0; + (* init = 1'h0 *) + reg n_n9049 = 1'h0; + (* init = 1'h0 *) + reg n_n9050 = 1'h0; + (* init = 1'h0 *) + reg n_n9051 = 1'h0; + (* init = 1'h0 *) + reg n_n9052 = 1'h0; + (* init = 1'h0 *) + reg n_n9053 = 1'h0; + (* init = 1'h0 *) + reg n_n9054 = 1'h0; + (* init = 1'h0 *) + reg n_n9059 = 1'h0; + (* init = 1'h0 *) + reg n_n9061 = 1'h0; + (* init = 1'h0 *) + reg n_n9064 = 1'h0; + (* init = 1'h0 *) + reg n_n9067 = 1'h0; + (* init = 1'h0 *) + reg n_n9075 = 1'h0; + (* init = 1'h0 *) + reg n_n9077 = 1'h0; + (* init = 1'h0 *) + reg n_n9081 = 1'h0; + (* init = 1'h0 *) + reg n_n9085 = 1'h0; + (* init = 1'h0 *) + reg n_n9087 = 1'h0; + (* init = 1'h0 *) + reg n_n9092 = 1'h0; + (* init = 1'h0 *) + reg n_n9096 = 1'h0; + (* init = 1'h0 *) + reg n_n9098 = 1'h0; + (* init = 1'h0 *) + reg n_n9100 = 1'h0; + (* init = 1'h0 *) + reg n_n9102 = 1'h0; + (* init = 1'h0 *) + reg n_n9104 = 1'h0; + (* init = 1'h0 *) + reg n_n9106 = 1'h0; + (* init = 1'h0 *) + reg n_n9108 = 1'h0; + (* init = 1'h0 *) + reg n_n9110 = 1'h0; + (* init = 1'h0 *) + reg n_n9119 = 1'h0; + (* init = 1'h0 *) + reg n_n9121 = 1'h0; + (* init = 1'h0 *) + reg n_n9123 = 1'h0; + (* init = 1'h0 *) + reg n_n9125 = 1'h0; + (* init = 1'h0 *) + reg n_n9126 = 1'h0; + (* init = 1'h0 *) + reg n_n9127 = 1'h0; + (* init = 1'h0 *) + reg n_n9128 = 1'h0; + (* init = 1'h0 *) + reg n_n9129 = 1'h0; + (* init = 1'h0 *) + reg n_n9130 = 1'h0; + (* init = 1'h0 *) + reg n_n9131 = 1'h0; + (* init = 1'h0 *) + reg n_n9132 = 1'h0; + (* init = 1'h0 *) + reg n_n9133 = 1'h0; + (* init = 1'h0 *) + reg n_n9134 = 1'h0; + (* init = 1'h0 *) + reg n_n9135 = 1'h0; + (* init = 1'h0 *) + reg n_n9136 = 1'h0; + (* init = 1'h0 *) + reg n_n9137 = 1'h0; + (* init = 1'h0 *) + reg n_n9139 = 1'h0; + (* init = 1'h0 *) + reg n_n9141 = 1'h0; + (* init = 1'h0 *) + reg n_n9145 = 1'h0; + (* init = 1'h0 *) + reg n_n9148 = 1'h0; + (* init = 1'h0 *) + reg n_n9150 = 1'h0; + (* init = 1'h0 *) + reg n_n9155 = 1'h0; + (* init = 1'h0 *) + reg n_n9157 = 1'h0; + (* init = 1'h0 *) + reg n_n9159 = 1'h0; + (* init = 1'h0 *) + reg n_n9160 = 1'h0; + (* init = 1'h0 *) + reg n_n9161 = 1'h0; + (* init = 1'h0 *) + reg n_n9162 = 1'h0; + (* init = 1'h0 *) + reg n_n9163 = 1'h0; + (* init = 1'h0 *) + reg n_n9164 = 1'h0; + (* init = 1'h0 *) + reg n_n9165 = 1'h0; + (* init = 1'h0 *) + reg n_n9166 = 1'h0; + (* init = 1'h0 *) + reg n_n9169 = 1'h0; + (* init = 1'h0 *) + reg n_n9171 = 1'h0; + (* init = 1'h0 *) + reg n_n9172 = 1'h0; + (* init = 1'h0 *) + reg n_n9173 = 1'h0; + (* init = 1'h0 *) + reg n_n9174 = 1'h0; + (* init = 1'h0 *) + reg n_n9175 = 1'h0; + (* init = 1'h0 *) + reg n_n9176 = 1'h0; + (* init = 1'h0 *) + reg n_n9177 = 1'h0; + (* init = 1'h0 *) + reg n_n9178 = 1'h0; + (* init = 1'h0 *) + reg n_n9179 = 1'h0; + (* init = 1'h0 *) + reg n_n9180 = 1'h0; + (* init = 1'h0 *) + reg n_n9181 = 1'h0; + (* init = 1'h0 *) + reg n_n9182 = 1'h0; + (* init = 1'h0 *) + reg n_n9183 = 1'h0; + (* init = 1'h0 *) + reg n_n9186 = 1'h0; + (* init = 1'h0 *) + reg n_n9189 = 1'h0; + (* init = 1'h0 *) + reg n_n9198 = 1'h0; + (* init = 1'h0 *) + reg n_n9200 = 1'h0; + (* init = 1'h0 *) + reg n_n9203 = 1'h0; + (* init = 1'h0 *) + reg n_n9205 = 1'h0; + (* init = 1'h0 *) + reg n_n9210 = 1'h0; + (* init = 1'h0 *) + reg n_n9212 = 1'h0; + (* init = 1'h0 *) + reg n_n9219 = 1'h0; + (* init = 1'h0 *) + reg n_n9221 = 1'h0; + (* init = 1'h0 *) + reg n_n9223 = 1'h0; + (* init = 1'h0 *) + reg n_n9225 = 1'h0; + (* init = 1'h0 *) + reg n_n9228 = 1'h0; + (* init = 1'h0 *) + reg n_n9230 = 1'h0; + (* init = 1'h0 *) + reg n_n9232 = 1'h0; + (* init = 1'h0 *) + reg n_n9235 = 1'h0; + (* init = 1'h0 *) + reg n_n9237 = 1'h0; + (* init = 1'h0 *) + reg n_n9239 = 1'h0; + (* init = 1'h0 *) + reg n_n9242 = 1'h0; + (* init = 1'h0 *) + reg n_n9244 = 1'h0; + (* init = 1'h0 *) + reg n_n9247 = 1'h0; + (* init = 1'h0 *) + reg n_n9248 = 1'h0; + (* init = 1'h0 *) + reg n_n9252 = 1'h0; + (* init = 1'h0 *) + reg n_n9255 = 1'h0; + (* init = 1'h0 *) + reg n_n9257 = 1'h0; + (* init = 1'h0 *) + reg n_n9259 = 1'h0; + (* init = 1'h0 *) + reg n_n9260 = 1'h0; + (* init = 1'h0 *) + reg n_n9261 = 1'h0; + (* init = 1'h0 *) + reg n_n9262 = 1'h0; + (* init = 1'h0 *) + reg n_n9263 = 1'h0; + (* init = 1'h0 *) + reg n_n9264 = 1'h0; + (* init = 1'h0 *) + reg n_n9265 = 1'h0; + (* init = 1'h0 *) + reg n_n9266 = 1'h0; + (* init = 1'h0 *) + reg n_n9267 = 1'h0; + (* init = 1'h0 *) + reg n_n9268 = 1'h0; + (* init = 1'h0 *) + reg n_n9269 = 1'h0; + (* init = 1'h0 *) + reg n_n9270 = 1'h0; + (* init = 1'h0 *) + reg n_n9271 = 1'h0; + (* init = 1'h0 *) + reg n_n9273 = 1'h0; + (* init = 1'h0 *) + reg n_n9275 = 1'h0; + (* init = 1'h0 *) + reg n_n9278 = 1'h0; + (* init = 1'h0 *) + reg n_n9280 = 1'h0; + (* init = 1'h0 *) + reg n_n9282 = 1'h0; + (* init = 1'h0 *) + reg n_n9284 = 1'h0; + (* init = 1'h0 *) + reg n_n9286 = 1'h0; + (* init = 1'h0 *) + reg n_n9289 = 1'h0; + (* init = 1'h0 *) + reg n_n9290 = 1'h0; + (* init = 1'h0 *) + reg n_n9291 = 1'h0; + (* init = 1'h0 *) + reg n_n9292 = 1'h0; + (* init = 1'h0 *) + reg n_n9294 = 1'h0; + (* init = 1'h0 *) + reg n_n9296 = 1'h0; + (* init = 1'h0 *) + reg n_n9298 = 1'h0; + (* init = 1'h0 *) + reg n_n9300 = 1'h0; + (* init = 1'h0 *) + reg n_n9302 = 1'h0; + (* init = 1'h0 *) + reg n_n9304 = 1'h0; + (* init = 1'h0 *) + reg n_n9306 = 1'h0; + (* init = 1'h0 *) + reg n_n9308 = 1'h0; + (* init = 1'h0 *) + reg n_n9309 = 1'h0; + (* init = 1'h0 *) + reg n_n9310 = 1'h0; + (* init = 1'h0 *) + reg n_n9311 = 1'h0; + (* init = 1'h0 *) + reg n_n9312 = 1'h0; + (* init = 1'h0 *) + reg n_n9313 = 1'h0; + (* init = 1'h0 *) + reg n_n9314 = 1'h0; + (* init = 1'h0 *) + reg n_n9315 = 1'h0; + (* init = 1'h0 *) + reg n_n9316 = 1'h0; + (* init = 1'h0 *) + reg n_n9317 = 1'h0; + (* init = 1'h0 *) + reg n_n9318 = 1'h0; + (* init = 1'h0 *) + reg n_n9319 = 1'h0; + (* init = 1'h0 *) + reg n_n9320 = 1'h0; + (* init = 1'h0 *) + reg n_n9321 = 1'h0; + (* init = 1'h0 *) + reg n_n9322 = 1'h0; + (* init = 1'h0 *) + reg n_n9323 = 1'h0; + (* init = 1'h0 *) + reg n_n9324 = 1'h0; + (* init = 1'h0 *) + reg n_n9325 = 1'h0; + (* init = 1'h0 *) + reg n_n9327 = 1'h0; + (* init = 1'h0 *) + reg n_n9331 = 1'h0; + (* init = 1'h0 *) + reg n_n9333 = 1'h0; + (* init = 1'h0 *) + reg n_n9334 = 1'h0; + (* init = 1'h0 *) + reg n_n9335 = 1'h0; + (* init = 1'h0 *) + reg n_n9336 = 1'h0; + (* init = 1'h0 *) + reg n_n9337 = 1'h0; + (* init = 1'h0 *) + reg n_n9338 = 1'h0; + (* init = 1'h0 *) + reg n_n9339 = 1'h0; + (* init = 1'h0 *) + reg n_n9340 = 1'h0; + (* init = 1'h0 *) + reg n_n9341 = 1'h0; + (* init = 1'h0 *) + reg n_n9342 = 1'h0; + (* init = 1'h0 *) + reg n_n9343 = 1'h0; + (* init = 1'h0 *) + reg n_n9344 = 1'h0; + (* init = 1'h0 *) + reg n_n9345 = 1'h0; + (* init = 1'h0 *) + reg n_n9346 = 1'h0; + (* init = 1'h0 *) + reg n_n9347 = 1'h0; + (* init = 1'h0 *) + reg n_n9348 = 1'h0; + (* init = 1'h0 *) + reg n_n9349 = 1'h0; + (* init = 1'h0 *) + reg n_n9351 = 1'h0; + (* init = 1'h0 *) + reg n_n9353 = 1'h0; + (* init = 1'h0 *) + reg n_n9355 = 1'h0; + (* init = 1'h0 *) + reg n_n9357 = 1'h0; + (* init = 1'h0 *) + reg n_n9358 = 1'h0; + (* init = 1'h0 *) + reg n_n9359 = 1'h0; + (* init = 1'h0 *) + reg n_n9360 = 1'h0; + (* init = 1'h0 *) + reg n_n9361 = 1'h0; + (* init = 1'h0 *) + reg n_n9362 = 1'h0; + (* init = 1'h0 *) + reg n_n9363 = 1'h0; + (* init = 1'h0 *) + reg n_n9366 = 1'h0; + (* init = 1'h0 *) + reg n_n9368 = 1'h0; + (* init = 1'h0 *) + reg n_n9371 = 1'h0; + (* init = 1'h0 *) + reg n_n9373 = 1'h0; + (* init = 1'h0 *) + reg n_n9376 = 1'h0; + (* init = 1'h0 *) + reg n_n9387 = 1'h0; + (* init = 1'h0 *) + reg n_n9390 = 1'h0; + (* init = 1'h0 *) + reg n_n9391 = 1'h0; + (* init = 1'h0 *) + reg n_n9392 = 1'h0; + (* init = 1'h0 *) + reg n_n9393 = 1'h0; + (* init = 1'h0 *) + reg n_n9394 = 1'h0; + (* init = 1'h0 *) + reg n_n9395 = 1'h0; + (* init = 1'h0 *) + reg n_n9396 = 1'h0; + (* init = 1'h0 *) + reg n_n9397 = 1'h0; + (* init = 1'h0 *) + reg n_n9398 = 1'h0; + (* init = 1'h0 *) + reg n_n9399 = 1'h0; + (* init = 1'h0 *) + reg n_n9400 = 1'h0; + (* init = 1'h0 *) + reg n_n9401 = 1'h0; + (* init = 1'h0 *) + reg n_n9402 = 1'h0; + (* init = 1'h0 *) + reg n_n9403 = 1'h0; + (* init = 1'h0 *) + reg n_n9404 = 1'h0; + (* init = 1'h0 *) + reg n_n9405 = 1'h0; + (* init = 1'h0 *) + reg n_n9406 = 1'h0; + (* init = 1'h0 *) + reg n_n9407 = 1'h0; + (* init = 1'h0 *) + reg n_n9408 = 1'h0; + (* init = 1'h0 *) + reg n_n9410 = 1'h0; + (* init = 1'h0 *) + reg n_n9412 = 1'h0; + (* init = 1'h0 *) + reg n_n9416 = 1'h0; + (* init = 1'h0 *) + reg n_n9421 = 1'h0; + (* init = 1'h0 *) + reg n_n9424 = 1'h0; + (* init = 1'h0 *) + reg n_n9429 = 1'h0; + (* init = 1'h0 *) + reg n_n9432 = 1'h0; + (* init = 1'h0 *) + reg n_n9434 = 1'h0; + (* init = 1'h0 *) + reg n_n9436 = 1'h0; + (* init = 1'h0 *) + reg n_n9437 = 1'h0; + (* init = 1'h0 *) + reg n_n9438 = 1'h0; + (* init = 1'h0 *) + reg n_n9439 = 1'h0; + (* init = 1'h0 *) + reg n_n9440 = 1'h0; + (* init = 1'h0 *) + reg n_n9441 = 1'h0; + (* init = 1'h0 *) + reg n_n9442 = 1'h0; + (* init = 1'h0 *) + reg n_n9446 = 1'h0; + (* init = 1'h0 *) + reg n_n9448 = 1'h0; + (* init = 1'h0 *) + reg n_n9452 = 1'h0; + (* init = 1'h0 *) + reg n_n9455 = 1'h0; + (* init = 1'h0 *) + reg n_n9458 = 1'h0; + (* init = 1'h0 *) + reg n_n9460 = 1'h0; + (* init = 1'h0 *) + reg n_n9465 = 1'h0; + (* init = 1'h0 *) + reg n_n9467 = 1'h0; + (* init = 1'h0 *) + reg n_n9470 = 1'h0; + (* init = 1'h0 *) + reg n_n9473 = 1'h0; + (* init = 1'h0 *) + reg n_n9476 = 1'h0; + (* init = 1'h0 *) + reg n_n9483 = 1'h0; + (* init = 1'h0 *) + reg n_n9485 = 1'h0; + (* init = 1'h0 *) + reg n_n9486 = 1'h0; + (* init = 1'h0 *) + reg n_n9487 = 1'h0; + (* init = 1'h0 *) + reg n_n9488 = 1'h0; + (* init = 1'h0 *) + reg n_n9489 = 1'h0; + (* init = 1'h0 *) + reg n_n9490 = 1'h0; + (* init = 1'h0 *) + reg n_n9491 = 1'h0; + (* init = 1'h0 *) + reg n_n9492 = 1'h0; + (* init = 1'h0 *) + reg n_n9493 = 1'h0; + (* init = 1'h0 *) + reg n_n9494 = 1'h0; + (* init = 1'h0 *) + reg n_n9495 = 1'h0; + (* init = 1'h0 *) + reg n_n9496 = 1'h0; + (* init = 1'h0 *) + reg n_n9497 = 1'h0; + (* init = 1'h0 *) + reg n_n9498 = 1'h0; + (* init = 1'h0 *) + reg n_n9499 = 1'h0; + (* init = 1'h0 *) + reg n_n9500 = 1'h0; + (* init = 1'h0 *) + reg n_n9501 = 1'h0; + (* init = 1'h0 *) + reg n_n9502 = 1'h0; + (* init = 1'h0 *) + reg n_n9503 = 1'h0; + (* init = 1'h0 *) + reg n_n9505 = 1'h0; + (* init = 1'h0 *) + reg n_n9508 = 1'h0; + (* init = 1'h0 *) + reg n_n9510 = 1'h0; + (* init = 1'h0 *) + reg n_n9512 = 1'h0; + (* init = 1'h0 *) + reg n_n9516 = 1'h0; + (* init = 1'h0 *) + reg n_n9518 = 1'h0; + (* init = 1'h0 *) + reg n_n9520 = 1'h0; + (* init = 1'h0 *) + reg n_n9522 = 1'h0; + (* init = 1'h0 *) + reg n_n9525 = 1'h0; + (* init = 1'h0 *) + reg n_n9528 = 1'h0; + (* init = 1'h0 *) + reg n_n9531 = 1'h0; + (* init = 1'h0 *) + reg n_n9535 = 1'h0; + (* init = 1'h0 *) + reg n_n9537 = 1'h0; + (* init = 1'h0 *) + reg n_n9539 = 1'h0; + (* init = 1'h0 *) + reg n_n9542 = 1'h0; + (* init = 1'h0 *) + reg n_n9548 = 1'h0; + (* init = 1'h0 *) + reg n_n9550 = 1'h0; + (* init = 1'h0 *) + reg n_n9552 = 1'h0; + (* init = 1'h0 *) + reg n_n9554 = 1'h0; + (* init = 1'h0 *) + reg n_n9555 = 1'h0; + (* init = 1'h0 *) + reg n_n9556 = 1'h0; + (* init = 1'h0 *) + reg n_n9557 = 1'h0; + (* init = 1'h0 *) + reg n_n9558 = 1'h0; + (* init = 1'h0 *) + reg n_n9559 = 1'h0; + (* init = 1'h0 *) + reg n_n9560 = 1'h0; + (* init = 1'h0 *) + reg n_n9561 = 1'h0; + (* init = 1'h0 *) + reg n_n9563 = 1'h0; + (* init = 1'h0 *) + reg n_n9566 = 1'h0; + (* init = 1'h0 *) + reg n_n9568 = 1'h0; + (* init = 1'h0 *) + reg n_n9570 = 1'h0; + (* init = 1'h0 *) + reg n_n9573 = 1'h0; + (* init = 1'h0 *) + reg n_n9576 = 1'h0; + (* init = 1'h0 *) + reg n_n9578 = 1'h0; + (* init = 1'h0 *) + reg n_n9580 = 1'h0; + (* init = 1'h0 *) + reg n_n9586 = 1'h0; + (* init = 1'h0 *) + reg n_n9588 = 1'h0; + (* init = 1'h0 *) + reg n_n9589 = 1'h0; + (* init = 1'h0 *) + reg n_n9590 = 1'h0; + (* init = 1'h0 *) + reg n_n9591 = 1'h0; + (* init = 1'h0 *) + reg n_n9592 = 1'h0; + (* init = 1'h0 *) + reg n_n9593 = 1'h0; + (* init = 1'h0 *) + reg n_n9594 = 1'h0; + (* init = 1'h0 *) + reg n_n9595 = 1'h0; + (* init = 1'h0 *) + reg n_n9596 = 1'h0; + (* init = 1'h0 *) + reg n_n9597 = 1'h0; + (* init = 1'h0 *) + reg n_n9598 = 1'h0; + (* init = 1'h0 *) + reg n_n9599 = 1'h0; + (* init = 1'h0 *) + reg n_n9600 = 1'h0; + (* init = 1'h0 *) + reg n_n9601 = 1'h0; + (* init = 1'h0 *) + reg n_n9602 = 1'h0; + (* init = 1'h0 *) + reg n_n9603 = 1'h0; + (* init = 1'h0 *) + reg n_n9604 = 1'h0; + (* init = 1'h0 *) + reg n_n9605 = 1'h0; + (* init = 1'h0 *) + reg n_n9606 = 1'h0; + (* init = 1'h0 *) + reg n_n9609 = 1'h0; + (* init = 1'h0 *) + reg n_n9611 = 1'h0; + (* init = 1'h0 *) + reg n_n9613 = 1'h0; + (* init = 1'h0 *) + reg n_n9615 = 1'h0; + (* init = 1'h0 *) + reg n_n9618 = 1'h0; + (* init = 1'h0 *) + reg n_n9623 = 1'h0; + (* init = 1'h0 *) + reg n_n9626 = 1'h0; + (* init = 1'h0 *) + reg n_n9629 = 1'h0; + (* init = 1'h0 *) + reg n_n9632 = 1'h0; + (* init = 1'h0 *) + reg n_n9635 = 1'h0; + (* init = 1'h0 *) + reg n_n9638 = 1'h0; + (* init = 1'h0 *) + reg nak3_13 = 1'h0; + (* init = 1'h0 *) + reg ndn1_4 = 1'h0; + (* init = 1'h0 *) + reg ndn2_2 = 1'h0; + (* init = 1'h0 *) + reg ndn3_11 = 1'h0; + (* init = 1'h0 *) + reg ndn3_12 = 1'h0; + (* init = 1'h0 *) + reg ndn3_13 = 1'h0; + (* init = 1'h0 *) + reg ndn3_14 = 1'h0; + (* init = 1'h0 *) + reg ndn3_15 = 1'h0; + (* init = 1'h0 *) + reg ndn3_16 = 1'h0; + (* init = 1'h0 *) + reg ndn3_17 = 1'h0; + (* init = 1'h0 *) + reg ndn3_18 = 1'h0; + (* init = 1'h0 *) + reg ndn3_19 = 1'h0; + (* init = 1'h0 *) + reg ndn3_2 = 1'h0; + (* init = 1'h0 *) + reg ndn3_20 = 1'h0; + (* init = 1'h0 *) + reg ndn3_21 = 1'h0; + (* init = 1'h0 *) + reg ndn3_22 = 1'h0; + (* init = 1'h0 *) + reg ndn3_23 = 1'h0; + (* init = 1'h0 *) + reg ndn3_25 = 1'h0; + (* init = 1'h0 *) + reg ndn3_26 = 1'h0; + (* init = 1'h0 *) + reg ndn3_27 = 1'h0; + (* init = 1'h0 *) + reg ndn3_28 = 1'h0; + (* init = 1'h0 *) + reg ndn3_29 = 1'h0; + (* init = 1'h0 *) + reg ndn3_30 = 1'h0; + (* init = 1'h0 *) + reg ndn3_32 = 1'h0; + (* init = 1'h0 *) + reg ndn3_34 = 1'h0; + (* init = 1'h0 *) + reg ndn3_35 = 1'h0; + (* init = 1'h0 *) + reg ndn3_36 = 1'h0; + (* init = 1'h0 *) + reg ndn3_37 = 1'h0; + (* init = 1'h0 *) + reg ndn3_38 = 1'h0; + (* init = 1'h0 *) + reg ndn3_39 = 1'h0; + (* init = 1'h0 *) + reg ndn3_4 = 1'h0; + (* init = 1'h0 *) + reg ndn3_40 = 1'h0; + (* init = 1'h0 *) + reg ndn3_42 = 1'h0; + (* init = 1'h0 *) + reg ndn3_44 = 1'h0; + (* init = 1'h0 *) + reg ndn3_46 = 1'h0; + (* init = 1'h0 *) + reg ndn3_50 = 1'h0; + (* init = 1'h0 *) + reg ndn3_7 = 1'h0; + (* init = 1'h0 *) + reg ndn3_9 = 1'h0; + (* init = 1'h0 *) + reg nen3_16 = 1'h0; + (* init = 1'h0 *) + reg nen3_19 = 1'h0; + (* init = 1'h0 *) + reg nen3_22 = 1'h0; + (* init = 1'h0 *) + reg nen3_28 = 1'h0; + (* init = 1'h0 *) + reg nen3_34 = 1'h0; + (* init = 1'h0 *) + reg nen3_36 = 1'h0; + (* init = 1'h0 *) + reg nen3_39 = 1'h0; + (* init = 1'h0 *) + reg ngfdn_3 = 1'h0; + (* init = 1'h0 *) + reg nlc1_2 = 1'h0; + (* init = 1'h0 *) + reg nsr1_2 = 1'h0; + (* init = 1'h0 *) + reg nsr3_13 = 1'h0; + (* init = 1'h0 *) + reg nsr3_14 = 1'h0; + (* init = 1'h0 *) + reg nsr3_20 = 1'h0; + (* init = 1'h0 *) + reg nsr3_23 = 1'h0; + (* init = 1'h0 *) + reg nsr3_30 = 1'h0; + (* init = 1'h0 *) + reg nsr3_35 = 1'h0; + (* init = 1'h0 *) + reg nsr3_37 = 1'h0; + (* init = 1'h0 *) + reg nsr3_38 = 1'h0; + /* input pclk; + (* init = 1'h0 *) */ + output pdn; + reg pdn = 1'h0; + input pinp_0_0_; + input pinp_10_10_; + input pinp_11_11_; + input pinp_12_12_; + input pinp_13_13_; + input pinp_14_14_; + input pinp_15_15_; + input pinp_1_1_; + input pinp_2_2_; + input pinp_3_3_; + input pinp_4_4_; + input pinp_5_5_; + input pinp_6_6_; + input pinp_7_7_; + input pinp_8_8_; + input pinp_9_9_; + (* init = 1'h0 *) + output pover_0_0_; + reg pover_0_0_ = 1'h0; + input preset; + input preset_0_0_; + output psv13_0_0_; + output psv13_10_10_; + output psv13_11_11_; + output psv13_12_12_; + output psv13_13_13_; + output psv13_14_14_; + output psv13_15_15_; + output psv13_1_1_; + output psv13_2_2_; + output psv13_3_3_; + output psv13_4_4_; + output psv13_5_5_; + output psv13_6_6_; + output psv13_7_7_; + output psv13_8_8_; + output psv13_9_9_; + output psv18_0_0_; + output psv18_10_10_; + output psv18_11_11_; + output psv18_12_12_; + output psv18_13_13_; + output psv18_14_14_; + output psv18_15_15_; + output psv18_1_1_; + output psv18_2_2_; + output psv18_3_3_; + output psv18_4_4_; + output psv18_5_5_; + output psv18_6_6_; + output psv18_7_7_; + output psv18_8_8_; + output psv18_9_9_; + output psv26_0_0_; + output psv26_10_10_; + output psv26_11_11_; + output psv26_12_12_; + output psv26_13_13_; + output psv26_14_14_; + output psv26_15_15_; + output psv26_1_1_; + output psv26_2_2_; + output psv26_3_3_; + output psv26_4_4_; + output psv26_5_5_; + output psv26_6_6_; + output psv26_7_7_; + output psv26_8_8_; + output psv26_9_9_; + output psv2_0_0_; + output psv2_10_10_; + output psv2_11_11_; + output psv2_12_12_; + output psv2_13_13_; + output psv2_14_14_; + output psv2_15_15_; + output psv2_1_1_; + output psv2_2_2_; + output psv2_3_3_; + output psv2_4_4_; + output psv2_5_5_; + output psv2_6_6_; + output psv2_7_7_; + output psv2_8_8_; + output psv2_9_9_; + output psv33_0_0_; + output psv33_10_10_; + output psv33_11_11_; + output psv33_12_12_; + output psv33_13_13_; + output psv33_14_14_; + output psv33_15_15_; + output psv33_1_1_; + output psv33_2_2_; + output psv33_3_3_; + output psv33_4_4_; + output psv33_5_5_; + output psv33_6_6_; + output psv33_7_7_; + output psv33_8_8_; + output psv33_9_9_; + output psv38_0_0_; + output psv38_10_10_; + output psv38_11_11_; + output psv38_12_12_; + output psv38_13_13_; + output psv38_14_14_; + output psv38_15_15_; + output psv38_1_1_; + output psv38_2_2_; + output psv38_3_3_; + output psv38_4_4_; + output psv38_5_5_; + output psv38_6_6_; + output psv38_7_7_; + output psv38_8_8_; + output psv38_9_9_; + output psv39_0_0_; + output psv39_10_10_; + output psv39_11_11_; + output psv39_12_12_; + output psv39_13_13_; + output psv39_14_14_; + output psv39_15_15_; + output psv39_1_1_; + output psv39_2_2_; + output psv39_3_3_; + output psv39_4_4_; + output psv39_5_5_; + output psv39_6_6_; + output psv39_7_7_; + output psv39_8_8_; + output psv39_9_9_; + input tin_psv13_0_0_; + input tin_psv13_10_10_; + input tin_psv13_11_11_; + input tin_psv13_12_12_; + input tin_psv13_13_13_; + input tin_psv13_14_14_; + input tin_psv13_15_15_; + input tin_psv13_1_1_; + input tin_psv13_2_2_; + input tin_psv13_3_3_; + input tin_psv13_4_4_; + input tin_psv13_5_5_; + input tin_psv13_6_6_; + input tin_psv13_7_7_; + input tin_psv13_8_8_; + input tin_psv13_9_9_; + input tin_psv18_0_0_; + input tin_psv18_10_10_; + input tin_psv18_11_11_; + input tin_psv18_12_12_; + input tin_psv18_13_13_; + input tin_psv18_14_14_; + input tin_psv18_15_15_; + input tin_psv18_1_1_; + input tin_psv18_2_2_; + input tin_psv18_3_3_; + input tin_psv18_4_4_; + input tin_psv18_5_5_; + input tin_psv18_6_6_; + input tin_psv18_7_7_; + input tin_psv18_8_8_; + input tin_psv18_9_9_; + input tin_psv26_0_0_; + input tin_psv26_10_10_; + input tin_psv26_11_11_; + input tin_psv26_12_12_; + input tin_psv26_13_13_; + input tin_psv26_14_14_; + input tin_psv26_15_15_; + input tin_psv26_1_1_; + input tin_psv26_2_2_; + input tin_psv26_3_3_; + input tin_psv26_4_4_; + input tin_psv26_5_5_; + input tin_psv26_6_6_; + input tin_psv26_7_7_; + input tin_psv26_8_8_; + input tin_psv26_9_9_; + input tin_psv2_0_0_; + input tin_psv2_10_10_; + input tin_psv2_11_11_; + input tin_psv2_12_12_; + input tin_psv2_13_13_; + input tin_psv2_14_14_; + input tin_psv2_15_15_; + input tin_psv2_1_1_; + input tin_psv2_2_2_; + input tin_psv2_3_3_; + input tin_psv2_4_4_; + input tin_psv2_5_5_; + input tin_psv2_6_6_; + input tin_psv2_7_7_; + input tin_psv2_8_8_; + input tin_psv2_9_9_; + input tin_psv33_0_0_; + input tin_psv33_10_10_; + input tin_psv33_11_11_; + input tin_psv33_12_12_; + input tin_psv33_13_13_; + input tin_psv33_14_14_; + input tin_psv33_15_15_; + input tin_psv33_1_1_; + input tin_psv33_2_2_; + input tin_psv33_3_3_; + input tin_psv33_4_4_; + input tin_psv33_5_5_; + input tin_psv33_6_6_; + input tin_psv33_7_7_; + input tin_psv33_8_8_; + input tin_psv33_9_9_; + input tin_psv38_0_0_; + input tin_psv38_10_10_; + input tin_psv38_11_11_; + input tin_psv38_12_12_; + input tin_psv38_13_13_; + input tin_psv38_14_14_; + input tin_psv38_15_15_; + input tin_psv38_1_1_; + input tin_psv38_2_2_; + input tin_psv38_3_3_; + input tin_psv38_4_4_; + input tin_psv38_5_5_; + input tin_psv38_6_6_; + input tin_psv38_7_7_; + input tin_psv38_8_8_; + input tin_psv38_9_9_; + input tin_psv39_0_0_; + input tin_psv39_10_10_; + input tin_psv39_11_11_; + input tin_psv39_12_12_; + input tin_psv39_13_13_; + input tin_psv39_14_14_; + input tin_psv39_15_15_; + input tin_psv39_1_1_; + input tin_psv39_2_2_; + input tin_psv39_3_3_; + input tin_psv39_4_4_; + input tin_psv39_5_5_; + input tin_psv39_6_6_; + input tin_psv39_7_7_; + input tin_psv39_8_8_; + input tin_psv39_9_9_; + always @(posedge clock) + pdn <= n493; + always @(posedge clock) + n_n9267 <= n536_1; + always @(posedge clock) + n_n8702 <= n986; + always @(posedge clock) + n_n8226 <= n5486; + always @(posedge clock) + n_n8151 <= n5491; + always @(posedge clock) + n_n7644 <= n5496; + always @(posedge clock) + n_n8770 <= n5501; + always @(posedge clock) + n_n8423 <= n5506; + always @(posedge clock) + n_n7763 <= n5511; + always @(posedge clock) + n_n9525 <= n5516; + always @(posedge clock) + n_n8033 <= n5521; + always @(posedge clock) + n_n7881 <= n5526; + always @(posedge clock) + n_n7815 <= n5531; + always @(posedge clock) + n_n9106 <= n991; + always @(posedge clock) + n_n9232 <= n5536; + always @(posedge clock) + n_n7792 <= n5541; + always @(posedge clock) + n_n9563 <= n5546; + always @(posedge clock) + n_n8672 <= n5551; + always @(posedge clock) + n_n7346 <= n5556; + always @(posedge clock) + n_n7949 <= n5561; + always @(posedge clock) + n_n8756 <= n5566; + always @(posedge clock) + n_n8641 <= n5571; + always @(posedge clock) + n_n8192 <= n5576; + always @(posedge clock) + n_n8058 <= n5581; + always @(posedge clock) + n_n7409 <= n996; + always @(posedge clock) + n_n8561 <= n5586; + always @(posedge clock) + n_n9306 <= n5591; + always @(posedge clock) + n_n9165 <= n5596; + always @(posedge clock) + n_n8850 <= n5601; + always @(posedge clock) + n_n9210 <= n5606; + always @(posedge clock) + ndn2_2 <= n5611; + always @(posedge clock) + n_n7342 <= n5616; + always @(posedge clock) + n_n8051 <= n5621; + always @(posedge clock) + n_n7136 <= n5626; + always @(posedge clock) + n_n9348 <= n5631; + always @(posedge clock) + n_n9437 <= n1001; + always @(posedge clock) + n_n9006 <= n5636; + always @(posedge clock) + n_n7653 <= n5641; + always @(posedge clock) + n_n7905 <= n5646; + always @(posedge clock) + n_n9166 <= n5651; + always @(posedge clock) + n_n7065 <= n5656; + always @(posedge clock) + n_n9490 <= n5661; + always @(posedge clock) + n_n7024 <= n5666; + always @(posedge clock) + n_n7586 <= n5671; + always @(posedge clock) + n_n8416 <= n5676; + always @(posedge clock) + n_n8937 <= n5681; + always @(posedge clock) + n_n9052 <= n1006; + always @(posedge clock) + n_n8141 <= n5686; + always @(posedge clock) + n_n7853 <= n5691; + always @(posedge clock) + n_n8121 <= n5696; + always @(posedge clock) + n_n9604 <= n5701; + always @(posedge clock) + n_n9496 <= n5706; + always @(posedge clock) + n_n8195 <= n5711; + always @(posedge clock) + n_n9516 <= n5716; + always @(posedge clock) + n_n9077 <= n5721; + always @(posedge clock) + n_n9436 <= n5726; + always @(posedge clock) + n_n9051 <= n5731; + always @(posedge clock) + n_n8647 <= n1011; + always @(posedge clock) + n_n7664 <= n5736; + always @(posedge clock) + n_n8419 <= n5741; + always @(posedge clock) + n_n7874 <= n5746; + always @(posedge clock) + n_n9133 <= n5751; + always @(posedge clock) + n_n9392 <= n5756; + always @(posedge clock) + n_n7770 <= n5761; + always @(posedge clock) + ndn3_32 <= n5766; + always @(posedge clock) + n_n7601 <= n5771; + always @(posedge clock) + n_n8206 <= n5776; + always @(posedge clock) + n_n7927 <= n5781; + always @(posedge clock) + n_n9265 <= n1016; + always @(posedge clock) + n_n9606 <= n5786; + always @(posedge clock) + n_n7111 <= n5791; + always @(posedge clock) + n_n9269 <= n5796; + always @(posedge clock) + ndn3_38 <= n5801; + always @(posedge clock) + n_n7886 <= n5806; + always @(posedge clock) + n_n9179 <= n5811; + always @(posedge clock) + n_n9357 <= n5816; + always @(posedge clock) + n_n9594 <= n5821; + always @(posedge clock) + n_n7628 <= n5826; + always @(posedge clock) + n_n8454 <= n5831; + always @(posedge clock) + n_n7179 <= n1021; + always @(posedge clock) + ndn3_20 <= n5836; + always @(posedge clock) + n_n9505 <= n5841; + always @(posedge clock) + nen3_34 <= n5846; + always @(posedge clock) + n_n9632 <= n5851; + always @(posedge clock) + n_n7076 <= n5856; + always @(posedge clock) + n_n9262 <= n5861; + always @(posedge clock) + n_n9048 <= n5866; + always @(posedge clock) + n_n9578 <= n5871; + always @(posedge clock) + n_n8135 <= n5876; + always @(posedge clock) + ndn3_26 <= n5881; + always @(posedge clock) + ndn3_13 <= n1026; + always @(posedge clock) + n_n7500 <= n5886; + always @(posedge clock) + n_n6974 <= n5891; + always @(posedge clock) + n_n8605 <= n5896; + always @(posedge clock) + n_n9296 <= n5901; + always @(posedge clock) + n_n7156 <= n5906; + always @(posedge clock) + n_n7920 <= n5911; + always @(posedge clock) + n_n8895 <= n5916; + always @(posedge clock) + n_n8991 <= n5921; + always @(posedge clock) + n_n8139 <= n5926; + always @(posedge clock) + n_n9275 <= n5931; + always @(posedge clock) + ndn3_17 <= n1031; + always @(posedge clock) + n_n7203 <= n5936; + always @(posedge clock) + n_n9590 <= n5941; + always @(posedge clock) + n_n7344 <= n5946; + always @(posedge clock) + n_n6976 <= n5951; + always @(posedge clock) + n_n7629 <= n5956; + always @(posedge clock) + ndn3_14 <= n5961; + always @(posedge clock) + n_n7862 <= n5966; + always @(posedge clock) + n_n9013 <= n5971; + always @(posedge clock) + n_n7288 <= n5976; + always @(posedge clock) + n_n8078 <= n5981; + always @(posedge clock) + n_n7779 <= n541_1; + always @(posedge clock) + ndn3_25 <= n1036; + always @(posedge clock) + n_n7334 <= n5986; + always @(posedge clock) + n_n7704 <= n5991; + always @(posedge clock) + n_n7788 <= n5996; + always @(posedge clock) + n_n8526 <= n6001; + always @(posedge clock) + n_n9556 <= n6006; + always @(posedge clock) + n_n9345 <= n6011; + always @(posedge clock) + n_n8447 <= n6016; + always @(posedge clock) + n_n7485 <= n6021; + always @(posedge clock) + n_n8570 <= n6026; + always @(posedge clock) + n_n7453 <= n6031; + always @(posedge clock) + ndn3_29 <= n1041; + always @(posedge clock) + n_n7928 <= n6036; + always @(posedge clock) + n_n8646 <= n6041; + always @(posedge clock) + n_n9405 <= n6046; + always @(posedge clock) + n_n8948 <= n6051; + always @(posedge clock) + n_n9131 <= n6056; + always @(posedge clock) + n_n8216 <= n6061; + always @(posedge clock) + n_n9177 <= n6066; + always @(posedge clock) + n_n7844 <= n6071; + always @(posedge clock) + n_n8811 <= n6076; + always @(posedge clock) + n_n9145 <= n6081; + always @(posedge clock) + n_n9539 <= n1046; + always @(posedge clock) + n_n8428 <= n6086; + always @(posedge clock) + n_n8858 <= n6091; + always @(posedge clock) + n_n8580 <= n6096; + always @(posedge clock) + n_n7953 <= n1051; + always @(posedge clock) + n_n8488 <= n1056; + always @(posedge clock) + nen3_22 <= n1061; + always @(posedge clock) + n_n9438 <= n1066; + always @(posedge clock) + n_n8132 <= n1071; + always @(posedge clock) + n_n8661 <= n1076; + always @(posedge clock) + n_n7759 <= n1081; + always @(posedge clock) + n_n9503 <= n546_1; + always @(posedge clock) + n_n8333 <= n1086; + always @(posedge clock) + n_n9399 <= n1091; + always @(posedge clock) + n_n7798 <= n1096; + always @(posedge clock) + n_n9434 <= n1101; + always @(posedge clock) + n_n7910 <= n1106; + always @(posedge clock) + n_n9528 <= n1111; + always @(posedge clock) + n_n7850 <= n1116; + always @(posedge clock) + n_n8251 <= n1121; + always @(posedge clock) + n_n7937 <= n1126; + always @(posedge clock) + n_n8482 <= n1131; + always @(posedge clock) + n_n8150 <= n551_1; + always @(posedge clock) + n_n9290 <= n1136; + always @(posedge clock) + n_n8007 <= n1141; + always @(posedge clock) + n_n7556 <= n1146; + always @(posedge clock) + n_n9064 <= n1151; + always @(posedge clock) + n_n9398 <= n1156; + always @(posedge clock) + n_n9412 <= n1161; + always @(posedge clock) + n_n9361 <= n1166; + always @(posedge clock) + n_n9304 <= n1171; + always @(posedge clock) + n_n7651 <= n1176; + always @(posedge clock) + n_n7712 <= n1181; + always @(posedge clock) + n_n9401 <= n556_1; + always @(posedge clock) + n_n7735 <= n1186; + always @(posedge clock) + n_n7934 <= n1191; + always @(posedge clock) + n_n7811 <= n1196; + always @(posedge clock) + n_n8053 <= n1201; + always @(posedge clock) + n_n9015 <= n1206; + always @(posedge clock) + n_n8066 <= n1211; + always @(posedge clock) + n_n9518 <= n1216; + always @(posedge clock) + n_n8091 <= n1221; + always @(posedge clock) + n_n9257 <= n1226; + always @(posedge clock) + n_n8175 <= n1231; + always @(posedge clock) + n_n7341 <= n561_1; + always @(posedge clock) + n_n8491 <= n1236; + always @(posedge clock) + n_n8114 <= n1241; + always @(posedge clock) + n_n7951 <= n1246; + always @(posedge clock) + n_n8913 <= n1251; + always @(posedge clock) + n_n8035 <= n1256; + always @(posedge clock) + n_n8631 <= n1261; + always @(posedge clock) + n_n8243 <= n1266; + always @(posedge clock) + n_n7857 <= n1271; + always @(posedge clock) + ngfdn_3 <= n1276; + always @(posedge clock) + n_n7791 <= n1281; + always @(posedge clock) + n_n9180 <= n566_1; + always @(posedge clock) + n_n9175 <= n1286; + always @(posedge clock) + n_n9588 <= n1291; + always @(posedge clock) + n_n9049 <= n1296; + always @(posedge clock) + n_n9483 <= n1301; + always @(posedge clock) + n_n9410 <= n1306; + always @(posedge clock) + n_n7691 <= n1311; + always @(posedge clock) + n_n7740 <= n1316; + always @(posedge clock) + n_n7602 <= n1321; + always @(posedge clock) + n_n7783 <= n1326; + always @(posedge clock) + n_n7948 <= n1331; + always @(posedge clock) + n_n8592 <= n571_1; + always @(posedge clock) + n_n7054 <= n1336; + always @(posedge clock) + n_n9343 <= n1341; + always @(posedge clock) + n_n9400 <= n1346; + always @(posedge clock) + nsr1_2 <= n1351; + always @(posedge clock) + n_n9127 <= n1356; + always @(posedge clock) + n_n8531 <= n1361; + always @(posedge clock) + n_n9335 <= n1366; + always @(posedge clock) + n_n7324 <= n1371; + always @(posedge clock) + n_n9611 <= n1376; + always @(posedge clock) + n_n8112 <= n1381; + always @(posedge clock) + n_n8871 <= n576_1; + always @(posedge clock) + n_n9406 <= n1386; + always @(posedge clock) + n_n9618 <= n1391; + always @(posedge clock) + n_n9613 <= n1396; + always @(posedge clock) + n_n9242 <= n1401; + always @(posedge clock) + n_n7384 <= n1406; + always @(posedge clock) + n_n8884 <= n1411; + always @(posedge clock) + n_n7462 <= n1416; + always @(posedge clock) + n_n7908 <= n1421; + always @(posedge clock) + n_n8765 <= n1426; + always @(posedge clock) + n_n7909 <= n1431; + always @(posedge clock) + n_n7252 <= n581_1; + always @(posedge clock) + n_n7898 <= n1436; + always @(posedge clock) + n_n9135 <= n1441; + always @(posedge clock) + n_n8862 <= n1446; + always @(posedge clock) + n_n8037 <= n1451; + always @(posedge clock) + ndn3_18 <= n1456; + always @(posedge clock) + ndn3_22 <= n1461; + always @(posedge clock) + n_n8974 <= n1466; + always @(posedge clock) + n_n7286 <= n1471; + always @(posedge clock) + n_n9223 <= n1476; + always @(posedge clock) + n_n7306 <= n1481; + always @(posedge clock) + pover_0_0_ <= n497; + always @(posedge clock) + n_n7271 <= n586_1; + always @(posedge clock) + n_n9169 <= n1486; + always @(posedge clock) + n_n9125 <= n1491; + always @(posedge clock) + nen3_39 <= n1496; + always @(posedge clock) + n_n8278 <= n1501; + always @(posedge clock) + n_n9557 <= n1506; + always @(posedge clock) + n_n7758 <= n1511; + always @(posedge clock) + n_n9391 <= n1516; + always @(posedge clock) + n_n8110 <= n1521; + always @(posedge clock) + n_n9597 <= n1526; + always @(posedge clock) + n_n8568 <= n1531; + always @(posedge clock) + n_n6991 <= n591_1; + always @(posedge clock) + n_n7428 <= n1536; + always @(posedge clock) + n_n7931 <= n1541; + always @(posedge clock) + n_n7742 <= n1546; + always @(posedge clock) + n_n7236 <= n1551; + always @(posedge clock) + n_n8219 <= n1556; + always @(posedge clock) + n_n9568 <= n1561; + always @(posedge clock) + n_n9200 <= n1566; + always @(posedge clock) + n_n8545 <= n1571; + always @(posedge clock) + n_n7823 <= n1576; + always @(posedge clock) + n_n8005 <= n1581; + always @(posedge clock) + n_n8557 <= n596_1; + always @(posedge clock) + n_n8736 <= n1586; + always @(posedge clock) + n_n9339 <= n1591; + always @(posedge clock) + n_n8499 <= n1596; + always @(posedge clock) + n_n8086 <= n1601; + always @(posedge clock) + n_n7803 <= n1606; + always @(posedge clock) + n_n7640 <= n1611; + always @(posedge clock) + n_n9098 <= n1616; + always @(posedge clock) + n_n7160 <= n1621; + always @(posedge clock) + n_n7713 <= n1626; + always @(posedge clock) + n_n9566 <= n1631; + always @(posedge clock) + n_n7707 <= n601_1; + always @(posedge clock) + n_n7955 <= n1636; + always @(posedge clock) + n_n8414 <= n1641; + always @(posedge clock) + n_n8006 <= n1646; + always @(posedge clock) + n_n9560 <= n1651; + always @(posedge clock) + n_n8742 <= n1656; + always @(posedge clock) + n_n7174 <= n1661; + always @(posedge clock) + n_n8882 <= n1666; + always @(posedge clock) + n_n7546 <= n1671; + always @(posedge clock) + n_n8282 <= n1676; + always @(posedge clock) + n_n8998 <= n1681; + always @(posedge clock) + n_n7552 <= n606_1; + always @(posedge clock) + n_n7656 <= n1686; + always @(posedge clock) + n_n9465 <= n1691; + always @(posedge clock) + n_n9601 <= n1696; + always @(posedge clock) + n_n8875 <= n1701; + always @(posedge clock) + n_n7954 <= n1706; + always @(posedge clock) + n_n8959 <= n1711; + always @(posedge clock) + n_n8957 <= n1716; + always @(posedge clock) + n_n8247 <= n1721; + always @(posedge clock) + n_n8258 <= n1726; + always @(posedge clock) + n_n7641 <= n1731; + always @(posedge clock) + ndn3_23 <= n611_1; + always @(posedge clock) + n_n8843 <= n1736; + always @(posedge clock) + n_n9321 <= n1741; + always @(posedge clock) + n_n7702 <= n1746; + always @(posedge clock) + nsr3_23 <= n1751; + always @(posedge clock) + n_n8199 <= n1756; + always @(posedge clock) + n_n7983 <= n1761; + always @(posedge clock) + n_n7217 <= n1766; + always @(posedge clock) + n_n7821 <= n1771; + always @(posedge clock) + n_n9489 <= n1776; + always @(posedge clock) + n_n8348 <= n1781; + always @(posedge clock) + n_n9548 <= n616_1; + always @(posedge clock) + n_n9408 <= n1786; + always @(posedge clock) + n_n8445 <= n1791; + always @(posedge clock) + n_n9501 <= n1796; + always @(posedge clock) + n_n7831 <= n1801; + always @(posedge clock) + n_n7757 <= n1806; + always @(posedge clock) + n_n9174 <= n1811; + always @(posedge clock) + n_n9432 <= n1816; + always @(posedge clock) + n_n8678 <= n1821; + always @(posedge clock) + n_n8024 <= n1826; + always @(posedge clock) + n_n7806 <= n1831; + always @(posedge clock) + n_n9467 <= n621_1; + always @(posedge clock) + n_n8996 <= n1836; + always @(posedge clock) + n_n7918 <= n1841; + always @(posedge clock) + n_n8260 <= n1846; + always @(posedge clock) + n_n9341 <= n1851; + always @(posedge clock) + n_n9189 <= n1856; + always @(posedge clock) + n_n9096 <= n1861; + always @(posedge clock) + ndn3_30 <= n1866; + always @(posedge clock) + n_n7775 <= n1871; + always @(posedge clock) + n_n7693 <= n1876; + always @(posedge clock) + nen3_16 <= n1881; + always @(posedge clock) + n_n8002 <= n626_1; + always @(posedge clock) + n_n7643 <= n1886; + always @(posedge clock) + n_n8941 <= n1891; + always @(posedge clock) + n_n8042 <= n1896; + always @(posedge clock) + n_n8681 <= n1901; + always @(posedge clock) + n_n8659 <= n1906; + always @(posedge clock) + n_n9110 <= n1911; + always @(posedge clock) + n_n9573 <= n1916; + always @(posedge clock) + n_n8951 <= n1921; + always @(posedge clock) + n_n9589 <= n1926; + always @(posedge clock) + n_n9387 <= n1931; + always @(posedge clock) + n_n6950 <= n631_1; + always @(posedge clock) + n_n8279 <= n1936; + always @(posedge clock) + n_n7790 <= n1941; + always @(posedge clock) + n_n8406 <= n1946; + always @(posedge clock) + n_n8582 <= n1951; + always @(posedge clock) + n_n7911 <= n1956; + always @(posedge clock) + n_n7474 <= n1961; + always @(posedge clock) + n_n8466 <= n1966; + always @(posedge clock) + n_n6984 <= n1971; + always @(posedge clock) + n_n7760 <= n1976; + always @(posedge clock) + n_n7847 <= n1981; + always @(posedge clock) + n_n9280 <= n501_1; + always @(posedge clock) + n_n8930 <= n636_1; + always @(posedge clock) + n_n9559 <= n1986; + always @(posedge clock) + n_n7362 <= n1991; + always @(posedge clock) + n_n9300 <= n1996; + always @(posedge clock) + n_n9550 <= n2001; + always @(posedge clock) + n_n9492 <= n2006; + always @(posedge clock) + n_n8777 <= n2011; + always @(posedge clock) + n_n7764 <= n2016; + always @(posedge clock) + n_n7826 <= n2021; + always @(posedge clock) + n_n7777 <= n2026; + always @(posedge clock) + n_n7824 <= n2031; + always @(posedge clock) + n_n7244 <= n641_1; + always @(posedge clock) + n_n8173 <= n2036; + always @(posedge clock) + n_n7498 <= n2041; + always @(posedge clock) + n_n9148 <= n2046; + always @(posedge clock) + n_n8753 <= n2051; + always @(posedge clock) + n_n8772 <= n2056; + always @(posedge clock) + n_n8049 <= n2061; + always @(posedge clock) + n_n9362 <= n2066; + always @(posedge clock) + ndn1_4 <= n2071; + always @(posedge clock) + n_n9561 <= n2076; + always @(posedge clock) + n_n9004 <= n2081; + always @(posedge clock) + n_n7819 <= n646_1; + always @(posedge clock) + n_n8203 <= n2086; + always @(posedge clock) + n_n8153 <= n2091; + always @(posedge clock) + n_n9263 <= n2096; + always @(posedge clock) + n_n8369 <= n2101; + always @(posedge clock) + n_n9331 <= n2106; + always @(posedge clock) + n_n7454 <= n2111; + always @(posedge clock) + ndn3_7 <= n2116; + always @(posedge clock) + n_n7527 <= n2121; + always @(posedge clock) + n_n9036 <= n2126; + always @(posedge clock) + n_n7875 <= n2131; + always @(posedge clock) + n_n8883 <= n651_1; + always @(posedge clock) + n_n8697 <= n2136; + always @(posedge clock) + n_n9497 <= n2141; + always @(posedge clock) + n_n7291 <= n2146; + always @(posedge clock) + nsr3_13 <= n2151; + always @(posedge clock) + nsr3_38 <= n2156; + always @(posedge clock) + n_n8240 <= n2161; + always @(posedge clock) + n_n7703 <= n2166; + always @(posedge clock) + n_n9282 <= n2171; + always @(posedge clock) + n_n8237 <= n2176; + always @(posedge clock) + n_n8935 <= n2181; + always @(posedge clock) + n_n7709 <= n656_1; + always @(posedge clock) + n_n9244 <= n2186; + always @(posedge clock) + n_n8648 <= n2191; + always @(posedge clock) + n_n8235 <= n2196; + always @(posedge clock) + n_n8611 <= n2201; + always @(posedge clock) + n_n9045 <= n2206; + always @(posedge clock) + n_n9334 <= n2211; + always @(posedge clock) + n_n8572 <= n2216; + always @(posedge clock) + n_n9491 <= n2221; + always @(posedge clock) + n_n9134 <= n2226; + always @(posedge clock) + n_n9555 <= n2231; + always @(posedge clock) + n_n9580 <= n661_1; + always @(posedge clock) + n_n9336 <= n2236; + always @(posedge clock) + n_n7050 <= n2241; + always @(posedge clock) + n_n9346 <= n2246; + always @(posedge clock) + n_n7140 <= n2251; + always @(posedge clock) + n_n7681 <= n2256; + always @(posedge clock) + n_n6948 <= n2261; + always @(posedge clock) + n_n8549 <= n2266; + always @(posedge clock) + ndn3_19 <= n2271; + always @(posedge clock) + ndn3_28 <= n2276; + always @(posedge clock) + n_n7102 <= n2281; + always @(posedge clock) + n_n9130 <= n666_1; + always @(posedge clock) + n_n8093 <= n2286; + always @(posedge clock) + n_n9041 <= n2291; + always @(posedge clock) + n_n8381 <= n2296; + always @(posedge clock) + n_n8810 <= n2301; + always @(posedge clock) + nen3_36 <= n2306; + always @(posedge clock) + n_n9047 <= n2311; + always @(posedge clock) + n_n9333 <= n2316; + always @(posedge clock) + n_n7736 <= n2321; + always @(posedge clock) + n_n7820 <= n2326; + always @(posedge clock) + n_n8986 <= n2331; + always @(posedge clock) + n_n9486 <= n671_1; + always @(posedge clock) + n_n8891 <= n2336; + always @(posedge clock) + n_n8000 <= n2341; + always @(posedge clock) + n_n7968 <= n2346; + always @(posedge clock) + n_n8750 <= n2351; + always @(posedge clock) + n_n9558 <= n2356; + always @(posedge clock) + n_n9368 <= n2361; + always @(posedge clock) + n_n8519 <= n2366; + always @(posedge clock) + n_n6956 <= n2371; + always @(posedge clock) + n_n8298 <= n2376; + always @(posedge clock) + n_n9397 <= n2381; + always @(posedge clock) + n_n9235 <= n676_1; + always @(posedge clock) + n_n7017 <= n2386; + always @(posedge clock) + n_n8638 <= n2391; + always @(posedge clock) + n_n9552 <= n2396; + always @(posedge clock) + n_n8964 <= n2401; + always @(posedge clock) + n_n8016 <= n2406; + always @(posedge clock) + n_n7603 <= n2411; + always @(posedge clock) + n_n7696 <= n2416; + always @(posedge clock) + n_n8589 <= n2421; + always @(posedge clock) + n_n9337 <= n2426; + always @(posedge clock) + n_n9132 <= n2431; + always @(posedge clock) + n_n7522 <= n681_1; + always @(posedge clock) + n_n8652 <= n2436; + always @(posedge clock) + n_n8707 <= n2441; + always @(posedge clock) + n_n9407 <= n2446; + always @(posedge clock) + n_n9044 <= n2451; + always @(posedge clock) + n_n8808 <= n2456; + always @(posedge clock) + nsr3_30 <= n2461; + always @(posedge clock) + n_n8274 <= n2466; + always @(posedge clock) + n_n8615 <= n2471; + always @(posedge clock) + n_n8238 <= n2476; + always @(posedge clock) + n_n7854 <= n2481; + always @(posedge clock) + n_n9172 <= n506_1; + always @(posedge clock) + n_n7373 <= n686_1; + always @(posedge clock) + n_n8649 <= n2486; + always @(posedge clock) + n_n8236 <= n2491; + always @(posedge clock) + n_n8269 <= n2496; + always @(posedge clock) + n_n9592 <= n2501; + always @(posedge clock) + n_n8022 <= n2506; + always @(posedge clock) + n_n8744 <= n2511; + always @(posedge clock) + n_n8529 <= n2516; + always @(posedge clock) + n_n7967 <= n2521; + always @(posedge clock) + n_n9487 <= n2526; + always @(posedge clock) + n_n8685 <= n2531; + always @(posedge clock) + n_n9085 <= n691_1; + always @(posedge clock) + n_n9531 <= n2536; + always @(posedge clock) + n_n9510 <= n2541; + always @(posedge clock) + n_n7771 <= n2546; + always @(posedge clock) + n_n8480 <= n2551; + always @(posedge clock) + n_n8543 <= n2556; + always @(posedge clock) + n_n7789 <= n2561; + always @(posedge clock) + ndn3_11 <= n2566; + always @(posedge clock) + ndn3_15 <= n2571; + always @(posedge clock) + ndn3_21 <= n2576; + always @(posedge clock) + n_n7584 <= n2581; + always @(posedge clock) + n_n9638 <= n696_1; + always @(posedge clock) + n_n8354 <= n2586; + always @(posedge clock) + n_n6952 <= n2591; + always @(posedge clock) + n_n8864 <= n2596; + always @(posedge clock) + n_n7930 <= n2601; + always @(posedge clock) + n_n7962 <= n2606; + always @(posedge clock) + n_n7929 <= n2611; + always @(posedge clock) + n_n9316 <= n2616; + always @(posedge clock) + n_n9102 <= n2621; + always @(posedge clock) + n_n7308 <= n2626; + always @(posedge clock) + n_n7657 <= n2631; + always @(posedge clock) + n_n7452 <= n701_1; + always @(posedge clock) + n_n9264 <= n2636; + always @(posedge clock) + n_n8760 <= n2641; + always @(posedge clock) + n_n6912 <= n2646; + always @(posedge clock) + n_n7887 <= n2651; + always @(posedge clock) + n_n8911 <= n2656; + always @(posedge clock) + n_n7952 <= n2661; + always @(posedge clock) + n_n8704 <= n2666; + always @(posedge clock) + n_n7876 <= n2671; + always @(posedge clock) + n_n9596 <= n2676; + always @(posedge clock) + n_n8430 <= n2681; + always @(posedge clock) + n_n8775 <= n706_1; + always @(posedge clock) + n_n9019 <= n2686; + always @(posedge clock) + n_n7699 <= n2691; + always @(posedge clock) + n_n7375 <= n2696; + always @(posedge clock) + n_n7936 <= n2701; + always @(posedge clock) + n_n8340 <= n2706; + always @(posedge clock) + n_n8809 <= n2711; + always @(posedge clock) + n_n6961 <= n2716; + always @(posedge clock) + n_n9429 <= n2721; + always @(posedge clock) + n_n7743 <= n2726; + always @(posedge clock) + n_n8980 <= n2731; + always @(posedge clock) + n_n7654 <= n711_1; + always @(posedge clock) + n_n7582 <= n2736; + always @(posedge clock) + n_n8968 <= n2741; + always @(posedge clock) + n_n9371 <= n2746; + always @(posedge clock) + n_n8741 <= n2751; + always @(posedge clock) + n_n9502 <= n2756; + always @(posedge clock) + n_n9373 <= n2761; + always @(posedge clock) + n_n9248 <= n2766; + always @(posedge clock) + n_n7822 <= n2771; + always @(posedge clock) + n_n9054 <= n2776; + always @(posedge clock) + n_n8273 <= n2781; + always @(posedge clock) + n_n8410 <= n716_1; + always @(posedge clock) + n_n6937 <= n2786; + always @(posedge clock) + n_n9342 <= n2791; + always @(posedge clock) + n_n9325 <= n2796; + always @(posedge clock) + n_n9609 <= n2801; + always @(posedge clock) + n_n9623 <= n2806; + always @(posedge clock) + n_n9470 <= n2811; + always @(posedge clock) + n_n7570 <= n2816; + always @(posedge clock) + n_n9310 <= n2821; + always @(posedge clock) + n_n9366 <= n2826; + always @(posedge clock) + n_n7181 <= n2831; + always @(posedge clock) + n_n8208 <= n721_1; + always @(posedge clock) + n_n8739 <= n2836; + always @(posedge clock) + n_n8939 <= n2841; + always @(posedge clock) + n_n7256 <= n2846; + always @(posedge clock) + n_n8983 <= n2851; + always @(posedge clock) + n_n7487 <= n2856; + always @(posedge clock) + n_n9268 <= n2861; + always @(posedge clock) + n_n8906 <= n2866; + always @(posedge clock) + n_n7988 <= n2871; + always @(posedge clock) + n_n9181 <= n2876; + always @(posedge clock) + n_n8725 <= n2881; + always @(posedge clock) + n_n8377 <= n726_1; + always @(posedge clock) + n_n8626 <= n2886; + always @(posedge clock) + ndn3_27 <= n2891; + always @(posedge clock) + n_n8210 <= n2896; + always @(posedge clock) + n_n7415 <= n2901; + always @(posedge clock) + n_n8900 <= n2906; + always @(posedge clock) + nen3_19 <= n2911; + always @(posedge clock) + n_n8762 <= n2916; + always @(posedge clock) + n_n8512 <= n2921; + always @(posedge clock) + n_n8095 <= n2926; + always @(posedge clock) + n_n8982 <= n2931; + always @(posedge clock) + n_n7558 <= n731_1; + always @(posedge clock) + n_n7387 <= n2936; + always @(posedge clock) + n_n9494 <= n2941; + always @(posedge clock) + n_n7689 <= n2946; + always @(posedge clock) + n_n7835 <= n2951; + always @(posedge clock) + n_n9157 <= n2956; + always @(posedge clock) + n_n8552 <= n2961; + always @(posedge clock) + n_n7381 <= n2966; + always @(posedge clock) + n_n9446 <= n2971; + always @(posedge clock) + n_n8633 <= n2976; + always @(posedge clock) + n_n7684 <= n2981; + always @(posedge clock) + n_n9260 <= n511_1; + always @(posedge clock) + n_n7599 <= n736_1; + always @(posedge clock) + n_n7310 <= n2986; + always @(posedge clock) + n_n8402 <= n2991; + always @(posedge clock) + n_n9315 <= n2996; + always @(posedge clock) + n_n7950 <= n3001; + always @(posedge clock) + n_n8504 <= n3006; + always @(posedge clock) + n_n8456 <= n3011; + always @(posedge clock) + n_n7514 <= n3016; + always @(posedge clock) + n_n7315 <= n3021; + always @(posedge clock) + n_n9476 <= n3026; + always @(posedge clock) + n_n8276 <= n3031; + always @(posedge clock) + n_n8225 <= n741_1; + always @(posedge clock) + n_n8833 <= n3036; + always @(posedge clock) + n_n7923 <= n3041; + always @(posedge clock) + n_n9395 <= n3046; + always @(posedge clock) + n_n9512 <= n3051; + always @(posedge clock) + n_n9319 <= n3056; + always @(posedge clock) + nsr3_35 <= n3061; + always @(posedge clock) + n_n7154 <= n3066; + always @(posedge clock) + n_n9495 <= n3071; + always @(posedge clock) + n_n9137 <= n3076; + always @(posedge clock) + n_n8854 <= n3081; + always @(posedge clock) + n_n8202 <= n746_1; + always @(posedge clock) + n_n9183 <= n3086; + always @(posedge clock) + n_n9323 <= n3091; + always @(posedge clock) + n_n9349 <= n3096; + always @(posedge clock) + n_n7896 <= n3101; + always @(posedge clock) + n_n8073 <= n3106; + always @(posedge clock) + n_n8970 <= n3111; + always @(posedge clock) + n_n9314 <= n3116; + always @(posedge clock) + n_n8486 <= n3121; + always @(posedge clock) + n_n7246 <= n3126; + always @(posedge clock) + n_n7866 <= n3131; + always @(posedge clock) + n_n7670 <= n751_1; + always @(posedge clock) + n_n9599 <= n3136; + always @(posedge clock) + n_n7635 <= n3141; + always @(posedge clock) + n_n8984 <= n3146; + always @(posedge clock) + n_n7360 <= n3151; + always @(posedge clock) + n_n8794 <= n3156; + always @(posedge clock) + n_n9108 <= n3161; + always @(posedge clock) + n_n9286 <= n3166; + always @(posedge clock) + ndn3_12 <= n3171; + always @(posedge clock) + ndn3_16 <= n3176; + always @(posedge clock) + n_n7708 <= n3181; + always @(posedge clock) + n_n7888 <= n756_1; + always @(posedge clock) + n_n7807 <= n3186; + always @(posedge clock) + n_n7650 <= n3191; + always @(posedge clock) + n_n7947 <= n3196; + always @(posedge clock) + n_n9500 <= n3201; + always @(posedge clock) + n_n7734 <= n3206; + always @(posedge clock) + n_n8464 <= n3211; + always @(posedge clock) + n_n7659 <= n3216; + always @(posedge clock) + n_n7630 <= n3221; + always @(posedge clock) + n_n7756 <= n3226; + always @(posedge clock) + n_n8691 <= n3231; + always @(posedge clock) + n_n7889 <= n761_1; + always @(posedge clock) + n_n9176 <= n3236; + always @(posedge clock) + n_n9327 <= n3241; + always @(posedge clock) + n_n7995 <= n3246; + always @(posedge clock) + n_n7395 <= n3251; + always @(posedge clock) + n_n7878 <= n3256; + always @(posedge clock) + n_n7507 <= n3261; + always @(posedge clock) + n_n7959 <= n3266; + always @(posedge clock) + n_n7825 <= n3271; + always @(posedge clock) + n_n8009 <= n3276; + always @(posedge clock) + n_n8281 <= n3281; + always @(posedge clock) + n_n8597 <= n766_1; + always @(posedge clock) + n_n7685 <= n3286; + always @(posedge clock) + n_n8106 <= n3291; + always @(posedge clock) + n_n7687 <= n3296; + always @(posedge clock) + n_n7766 <= n3301; + always @(posedge clock) + n_n7880 <= n3306; + always @(posedge clock) + n_n8961 <= n3311; + always @(posedge clock) + n_n8014 <= n3316; + always @(posedge clock) + n_n9278 <= n3321; + always @(posedge clock) + n_n9087 <= n3326; + always @(posedge clock) + n_n9182 <= n3331; + always @(posedge clock) + n_n8152 <= n771_1; + always @(posedge clock) + n_n7852 <= n3336; + always @(posedge clock) + n_n9324 <= n3341; + always @(posedge clock) + nak3_13 <= n3346; + always @(posedge clock) + n_n9416 <= n3351; + always @(posedge clock) + nsr3_14 <= n3356; + always @(posedge clock) + n_n8603 <= n3361; + always @(posedge clock) + n_n7026 <= n3366; + always @(posedge clock) + n_n8856 <= n3371; + always @(posedge clock) + n_n8272 <= n3376; + always @(posedge clock) + n_n9312 <= n3381; + always @(posedge clock) + n_n8394 <= n776_1; + always @(posedge clock) + n_n7985 <= n3386; + always @(posedge clock) + n_n8312 <= n3391; + always @(posedge clock) + n_n7231 <= n3396; + always @(posedge clock) + n_n9396 <= n3401; + always @(posedge clock) + n_n8801 <= n3406; + always @(posedge clock) + n_n8683 <= n3411; + always @(posedge clock) + ndn3_39 <= n3416; + always @(posedge clock) + n_n8245 <= n3421; + always @(posedge clock) + n_n9458 <= n3426; + always @(posedge clock) + n_n9302 <= n3431; + always @(posedge clock) + n_n7812 <= n781_1; + always @(posedge clock) + n_n7392 <= n3436; + always @(posedge clock) + n_n6963 <= n3441; + always @(posedge clock) + n_n7808 <= n3446; + always @(posedge clock) + n_n7225 <= n3451; + always @(posedge clock) + n_n7817 <= n3456; + always @(posedge clock) + n_n8201 <= n3461; + always @(posedge clock) + n_n7793 <= n3466; + always @(posedge clock) + n_n8177 <= n3471; + always @(posedge clock) + n_n8389 <= n3476; + always @(posedge clock) + n_n9440 <= n3481; + always @(posedge clock) + n_n7726 <= n516_1; + always @(posedge clock) + n_n7816 <= n786_1; + always @(posedge clock) + n_n7683 <= n3486; + always @(posedge clock) + n_n7761 <= n3491; + always @(posedge clock) + n_n7667 <= n3496; + always @(posedge clock) + n_n7980 <= n3501; + always @(posedge clock) + n_n7509 <= n3506; + always @(posedge clock) + n_n7813 <= n3511; + always @(posedge clock) + n_n8396 <= n3516; + always @(posedge clock) + n_n9535 <= n3521; + always @(posedge clock) + n_n7209 <= n3526; + always @(posedge clock) + n_n7003 <= n3531; + always @(posedge clock) + n_n9141 <= n791_1; + always @(posedge clock) + n_n7695 <= n3536; + always @(posedge clock) + n_n7624 <= n3541; + always @(posedge clock) + n_n8791 <= n3546; + always @(posedge clock) + n_n7374 <= n3551; + always @(posedge clock) + n_n7429 <= n3556; + always @(posedge clock) + n_n7944 <= n3561; + always @(posedge clock) + n_n9266 <= n3566; + always @(posedge clock) + n_n8100 <= n3571; + always @(posedge clock) + n_n6988 <= n3576; + always @(posedge clock) + n_n6986 <= n3581; + always @(posedge clock) + n_n7332 <= n796_1; + always @(posedge clock) + n_n8933 <= n3586; + always @(posedge clock) + n_n7117 <= n3591; + always @(posedge clock) + n_n9043 <= n3596; + always @(posedge clock) + n_n8241 <= n3601; + always @(posedge clock) + n_n9219 <= n3606; + always @(posedge clock) + n_n8198 <= n3611; + always @(posedge clock) + n_n8081 <= n3616; + always @(posedge clock) + n_n8575 <= n3621; + always @(posedge clock) + n_n8710 <= n3626; + always @(posedge clock) + n_n7622 <= n3631; + always @(posedge clock) + n_n8758 <= n801_1; + always @(posedge clock) + n_n7966 <= n3636; + always @(posedge clock) + n_n7885 <= n3641; + always @(posedge clock) + n_n7033 <= n3646; + always @(posedge clock) + ndn3_34 <= n3651; + always @(posedge clock) + n_n9186 <= n3656; + always @(posedge clock) + ndn3_50 <= n3661; + always @(posedge clock) + n_n7879 <= n3666; + always @(posedge clock) + n_n7019 <= n3671; + always @(posedge clock) + n_n9171 <= n3676; + always @(posedge clock) + n_n7261 <= n3681; + always @(posedge clock) + n_n7765 <= n806_1; + always @(posedge clock) + n_n8223 <= n3686; + always @(posedge clock) + n_n8989 <= n3691; + always @(posedge clock) + n_n7993 <= n3696; + always @(posedge clock) + n_n7845 <= n3701; + always @(posedge clock) + n_n8253 <= n3706; + always @(posedge clock) + n_n8889 <= n3711; + always @(posedge clock) + n_n7809 <= n3716; + always @(posedge clock) + n_n8918 <= n3721; + always @(posedge clock) + n_n8515 <= n3726; + always @(posedge clock) + n_n7933 <= n3731; + always @(posedge clock) + n_n7877 <= n811_1; + always @(posedge clock) + n_n8075 <= n3736; + always @(posedge clock) + n_n7338 <= n3741; + always @(posedge clock) + n_n8104 <= n3746; + always @(posedge clock) + n_n8171 <= n3751; + always @(posedge clock) + n_n9059 <= n3756; + always @(posedge clock) + n_n9023 <= n3761; + always @(posedge clock) + n_n7692 <= n3766; + always @(posedge clock) + n_n9441 <= n3771; + always @(posedge clock) + n_n6920 <= n3776; + always @(posedge clock) + n_n8831 <= n3781; + always @(posedge clock) + n_n7814 <= n816_1; + always @(posedge clock) + n_n8441 <= n3786; + always @(posedge clock) + n_n9576 <= n3791; + always @(posedge clock) + n_n9252 <= n3796; + always @(posedge clock) + n_n9363 <= n3801; + always @(posedge clock) + ndn3_4 <= n3806; + always @(posedge clock) + n_n9247 <= n3811; + always @(posedge clock) + n_n7561 <= n3816; + always @(posedge clock) + n_n8923 <= n3821; + always @(posedge clock) + n_n7978 <= n3826; + always @(posedge clock) + n_n8978 <= n3831; + always @(posedge clock) + n_n9008 <= n821_1; + always @(posedge clock) + n_n9499 <= n3836; + always @(posedge clock) + n_n8713 <= n3841; + always @(posedge clock) + n_n8944 <= n3846; + always @(posedge clock) + n_n8239 <= n3851; + always @(posedge clock) + n_n7652 <= n3856; + always @(posedge clock) + n_n9042 <= n3861; + always @(posedge clock) + n_n8530 <= n3866; + always @(posedge clock) + n_n9271 <= n3871; + always @(posedge clock) + n_n9318 <= n3876; + always @(posedge clock) + n_n7706 <= n3881; + always @(posedge clock) + n_n7581 <= n826_1; + always @(posedge clock) + n_n7964 <= n3886; + always @(posedge clock) + n_n8222 <= n3891; + always @(posedge clock) + n_n8898 <= n3896; + always @(posedge clock) + n_n7976 <= n3901; + always @(posedge clock) + n_n7649 <= n3906; + always @(posedge clock) + n_n7604 <= n3911; + always @(posedge clock) + n_n7961 <= n3916; + always @(posedge clock) + n_n7424 <= n3921; + always @(posedge clock) + n_n7476 <= n3926; + always @(posedge clock) + n_n9259 <= n3931; + always @(posedge clock) + n_n7376 <= n831_1; + always @(posedge clock) + n_n9309 <= n3936; + always @(posedge clock) + n_n9161 <= n3941; + always @(posedge clock) + n_n8436 <= n3946; + always @(posedge clock) + n_n9121 <= n3951; + always @(posedge clock) + n_n8061 <= n3956; + always @(posedge clock) + n_n8004 <= n3961; + always @(posedge clock) + n_n9360 <= n3966; + always @(posedge clock) + n_n9205 <= n3971; + always @(posedge clock) + n_n8392 <= n3976; + always @(posedge clock) + n_n9034 <= n3981; + always @(posedge clock) + n_n8270 <= n521_1; + always @(posedge clock) + n_n7970 <= n836; + always @(posedge clock) + n_n8375 <= n3986; + always @(posedge clock) + n_n8328 <= n3991; + always @(posedge clock) + n_n9298 <= n3996; + always @(posedge clock) + n_n7598 <= n4001; + always @(posedge clock) + n_n8506 <= n4006; + always @(posedge clock) + n_n7737 <= n4011; + always @(posedge clock) + n_n7420 <= n4016; + always @(posedge clock) + n_n9291 <= n4021; + always @(posedge clock) + n_n7946 <= n4026; + always @(posedge clock) + n_n8584 <= n4031; + always @(posedge clock) + n_n8599 <= n841; + always @(posedge clock) + n_n9308 <= n4036; + always @(posedge clock) + n_n9403 <= n4041; + always @(posedge clock) + n_n7284 <= n4046; + always @(posedge clock) + n_n9270 <= n4051; + always @(posedge clock) + n_n7390 <= n4056; + always @(posedge clock) + n_n9351 <= n4061; + always @(posedge clock) + n_n6968 <= n4066; + always @(posedge clock) + n_n8668 <= n4071; + always @(posedge clock) + n_n9605 <= n4076; + always @(posedge clock) + n_n7013 <= n4081; + always @(posedge clock) + n_n8227 <= n846; + always @(posedge clock) + n_n9626 <= n4086; + always @(posedge clock) + n_n8200 <= n4091; + always @(posedge clock) + n_n9028 <= n4096; + always @(posedge clock) + n_n8803 <= n4101; + always @(posedge clock) + n_n9570 <= n4106; + always @(posedge clock) + n_n8366 <= n4111; + always @(posedge clock) + n_n9050 <= n4116; + always @(posedge clock) + n_n8650 <= n4121; + always @(posedge clock) + n_n8574 <= n4126; + always @(posedge clock) + n_n7276 <= n4131; + always @(posedge clock) + n_n9442 <= n851; + always @(posedge clock) + n_n9212 <= n4136; + always @(posedge clock) + n_n8384 <= n4141; + always @(posedge clock) + ndn3_35 <= n4146; + always @(posedge clock) + n_n8449 <= n4151; + always @(posedge clock) + ndn3_46 <= n4156; + always @(posedge clock) + n_n7554 <= n4161; + always @(posedge clock) + n_n8743 <= n4166; + always @(posedge clock) + n_n8277 <= n4171; + always @(posedge clock) + n_n9359 <= n4176; + always @(posedge clock) + n_n8425 <= n4181; + always @(posedge clock) + n_n9485 <= n856; + always @(posedge clock) + n_n9104 <= n4186; + always @(posedge clock) + n_n9221 <= n4191; + always @(posedge clock) + n_n9448 <= n4196; + always @(posedge clock) + n_n9537 <= n4201; + always @(posedge clock) + n_n8003 <= n4206; + always @(posedge clock) + n_n7467 <= n4211; + always @(posedge clock) + n_n8233 <= n4216; + always @(posedge clock) + n_n7932 <= n4221; + always @(posedge clock) + n_n8064 <= n4226; + always @(posedge clock) + n_n9162 <= n4231; + always @(posedge clock) + n_n7148 <= n861; + always @(posedge clock) + n_n7971 <= n4236; + always @(posedge clock) + n_n8055 <= n4241; + always @(posedge clock) + n_n7711 <= n4246; + always @(posedge clock) + n_n8256 <= n4251; + always @(posedge clock) + n_n7925 <= n4256; + always @(posedge clock) + n_n7762 <= n4261; + always @(posedge clock) + n_n7668 <= n4266; + always @(posedge clock) + n_n7914 <= n4271; + always @(posedge clock) + n_n7873 <= n4276; + always @(posedge clock) + n_n7849 <= n4281; + always @(posedge clock) + n_n9311 <= n866; + always @(posedge clock) + n_n9421 <= n4286; + always @(posedge clock) + n_n7626 <= n4291; + always @(posedge clock) + n_n7848 <= n4296; + always @(posedge clock) + n_n8263 <= n4301; + always @(posedge clock) + n_n9100 <= n4306; + always @(posedge clock) + n_n9393 <= n4311; + always @(posedge clock) + n_n9591 <= n4316; + always @(posedge clock) + n_n7588 <= n4321; + always @(posedge clock) + n_n9123 <= n4326; + always @(posedge clock) + n_n9159 <= n4331; + always @(posedge clock) + n_n9273 <= n871; + always @(posedge clock) + n_n9128 <= n4336; + always @(posedge clock) + n_n8045 <= n4341; + always @(posedge clock) + n_n7728 <= n4346; + always @(posedge clock) + n_n8929 <= n4351; + always @(posedge clock) + n_n7739 <= n4356; + always @(posedge clock) + n_n9355 <= n4361; + always @(posedge clock) + n_n9394 <= n4366; + always @(posedge clock) + n_n8470 <= n4371; + always @(posedge clock) + n_n8571 <= n4376; + always @(posedge clock) + n_n8796 <= n4381; + always @(posedge clock) + ndn3_9 <= n876; + always @(posedge clock) + ndn3_36 <= n4386; + always @(posedge clock) + n_n7990 <= n4391; + always @(posedge clock) + n_n8781 <= n4396; + always @(posedge clock) + n_n8817 <= n4401; + always @(posedge clock) + n_n9160 <= n4406; + always @(posedge clock) + n_n9092 <= n4411; + always @(posedge clock) + n_n8513 <= n4416; + always @(posedge clock) + n_n8213 <= n4421; + always @(posedge clock) + n_n8581 <= n4426; + always @(posedge clock) + n_n9284 <= n4431; + always @(posedge clock) + n_n8613 <= n881; + always @(posedge clock) + n_n7837 <= n4436; + always @(posedge clock) + n_n8224 <= n4441; + always @(posedge clock) + n_n9203 <= n4446; + always @(posedge clock) + n_n7655 <= n4451; + always @(posedge clock) + n_n8946 <= n4456; + always @(posedge clock) + n_n7052 <= n4461; + always @(posedge clock) + n_n9615 <= n4466; + always @(posedge clock) + n_n8473 <= n4471; + always @(posedge clock) + n_n7741 <= n4476; + always @(posedge clock) + n_n9460 <= n4481; + always @(posedge clock) + n_n8196 <= n526_1; + always @(posedge clock) + n_n8533 <= n886; + always @(posedge clock) + n_n7912 <= n4486; + always @(posedge clock) + n_n7606 <= n4491; + always @(posedge clock) + n_n9021 <= n4496; + always @(posedge clock) + n_n7781 <= n4501; + always @(posedge clock) + n_n7810 <= n4506; + always @(posedge clock) + n_n7108 <= n4511; + always @(posedge clock) + n_n7697 <= n4516; + always @(posedge clock) + n_n7642 <= n4521; + always @(posedge clock) + n_n9595 <= n4526; + always @(posedge clock) + n_n7694 <= n4531; + always @(posedge clock) + n_n8699 <= n891; + always @(posedge clock) + n_n8221 <= n4536; + always @(posedge clock) + n_n7600 <= n4541; + always @(posedge clock) + n_n7935 <= n4546; + always @(posedge clock) + n_n9230 <= n4551; + always @(posedge clock) + n_n7701 <= n4556; + always @(posedge clock) + n_n7510 <= n4561; + always @(posedge clock) + n_n7627 <= n4566; + always @(posedge clock) + n_n8502 <= n4571; + always @(posedge clock) + n_n8516 <= n4576; + always @(posedge clock) + n_n7913 <= n4581; + always @(posedge clock) + n_n8609 <= n896; + always @(posedge clock) + n_n9320 <= n4586; + always @(posedge clock) + n_n7411 <= n4591; + always @(posedge clock) + n_n9129 <= n4596; + always @(posedge clock) + n_n9053 <= n4601; + always @(posedge clock) + n_n7069 <= n4606; + always @(posedge clock) + n_n8617 <= n4611; + always @(posedge clock) + n_n7242 <= n4616; + always @(posedge clock) + n_n8230 <= n4621; + always @(posedge clock) + n_n9294 <= n4626; + always @(posedge clock) + n_n8249 <= n4631; + always @(posedge clock) + n_n8308 <= n901; + always @(posedge clock) + n_n8972 <= n4636; + always @(posedge clock) + n_n7074 <= n4641; + always @(posedge clock) + n_n7493 <= n4646; + always @(posedge clock) + n_n8290 <= n4651; + always @(posedge clock) + n_n8821 <= n4656; + always @(posedge clock) + n_n7769 <= n4661; + always @(posedge clock) + n_n7491 <= n4666; + always @(posedge clock) + n_n9600 <= n4671; + always @(posedge clock) + n_n9317 <= n4676; + always @(posedge clock) + n_n8047 <= n4681; + always @(posedge clock) + n_n8655 <= n906; + always @(posedge clock) + n_n9629 <= n4686; + always @(posedge clock) + n_n9126 <= n4691; + always @(posedge clock) + n_n9508 <= n4696; + always @(posedge clock) + n_n9155 <= n4701; + always @(posedge clock) + n_n8528 <= n4706; + always @(posedge clock) + ndn3_37 <= n4711; + always @(posedge clock) + ndn3_42 <= n4716; + always @(posedge clock) + n_n9358 <= n4721; + always @(posedge clock) + n_n8185 <= n4726; + always @(posedge clock) + nen3_28 <= n4731; + always @(posedge clock) + n_n8981 <= n911; + always @(posedge clock) + n_n8839 <= n4736; + always @(posedge clock) + n_n7903 <= n4741; + always @(posedge clock) + n_n9139 <= n4746; + always @(posedge clock) + n_n9075 <= n4751; + always @(posedge clock) + n_n9439 <= n4756; + always @(posedge clock) + n_n9353 <= n4761; + always @(posedge clock) + n_n7665 <= n4766; + always @(posedge clock) + n_n8798 <= n4771; + always @(posedge clock) + n_n7146 <= n4776; + always @(posedge clock) + n_n7890 <= n4781; + always @(posedge clock) + n_n7583 <= n916; + always @(posedge clock) + n_n7176 <= n4786; + always @(posedge clock) + n_n8477 <= n4791; + always @(posedge clock) + n_n8514 <= n4796; + always @(posedge clock) + n_n8636 <= n4801; + always @(posedge clock) + n_n7183 <= n4806; + always @(posedge clock) + n_n8657 <= n4811; + always @(posedge clock) + n_n9493 <= n4816; + always @(posedge clock) + n_n7969 <= n4821; + always @(posedge clock) + n_n9255 <= n4826; + always @(posedge clock) + n_n8535 <= n4831; + always @(posedge clock) + n_n9198 <= n921; + always @(posedge clock) + n_n8619 <= n4836; + always @(posedge clock) + n_n8909 <= n4841; + always @(posedge clock) + n_n7744 <= n4846; + always @(posedge clock) + n_n9119 <= n4851; + always @(posedge clock) + n_n7827 <= n4856; + always @(posedge clock) + n_n8916 <= n4861; + always @(posedge clock) + n_n8729 <= n4866; + always @(posedge clock) + n_n9011 <= n4871; + always @(posedge clock) + n_n8779 <= n4876; + always @(posedge clock) + n_n6980 <= n4881; + always @(posedge clock) + n_n9602 <= n926; + always @(posedge clock) + n_n7715 <= n4886; + always @(posedge clock) + n_n9067 <= n4891; + always @(posedge clock) + n_n9164 <= n4896; + always @(posedge clock) + n_n7402 <= n4901; + always @(posedge clock) + n_n8938 <= n4906; + always @(posedge clock) + n_n9046 <= n4911; + always @(posedge clock) + n_n8789 <= n4916; + always @(posedge clock) + n_n9390 <= n4921; + always @(posedge clock) + n_n7768 <= n4926; + always @(posedge clock) + n_n9136 <= n4931; + always @(posedge clock) + n_n8786 <= n931; + always @(posedge clock) + n_n8670 <= n4936; + always @(posedge clock) + n_n8644 <= n4941; + always @(posedge clock) + n_n9178 <= n4946; + always @(posedge clock) + n_n8188 <= n4951; + always @(posedge clock) + n_n7083 <= n4956; + always @(posedge clock) + n_n9344 <= n4961; + always @(posedge clock) + n_n7366 <= n4966; + always @(posedge clock) + n_n8361 <= n4971; + always @(posedge clock) + n_n9228 <= n4976; + always @(posedge clock) + n_n9402 <= n4981; + always @(posedge clock) + n_n9150 <= n531_1; + always @(posedge clock) + n_n9598 <= n936; + always @(posedge clock) + n_n8510 <= n4986; + always @(posedge clock) + n_n8881 <= n4991; + always @(posedge clock) + n_n9404 <= n4996; + always @(posedge clock) + n_n9424 <= n5001; + always @(posedge clock) + n_n9031 <= n5006; + always @(posedge clock) + nsr3_37 <= n5011; + always @(posedge clock) + n_n8197 <= n5016; + always @(posedge clock) + n_n8468 <= n5021; + always @(posedge clock) + n_n7121 <= n5026; + always @(posedge clock) + n_n7511 <= n5031; + always @(posedge clock) + n_n7738 <= n941; + always @(posedge clock) + ndn3_44 <= n5036; + always @(posedge clock) + n_n9322 <= n5041; + always @(posedge clock) + n_n7682 <= n5046; + always @(posedge clock) + n_n9603 <= n5051; + always @(posedge clock) + nlc1_2 <= n5056; + always @(posedge clock) + n_n8408 <= n5061; + always @(posedge clock) + n_n8577 <= n5066; + always @(posedge clock) + n_n7079 <= n5071; + always @(posedge clock) + n_n8828 <= n5076; + always @(posedge clock) + n_n9340 <= n5081; + always @(posedge clock) + n_n8573 <= n946; + always @(posedge clock) + n_n8586 <= n5086; + always @(posedge clock) + n_n7901 <= n5091; + always @(posedge clock) + n_n8628 <= n5096; + always @(posedge clock) + n_n8869 <= n5101; + always @(posedge clock) + n_n7710 <= n5106; + always @(posedge clock) + n_n8993 <= n5111; + always @(posedge clock) + n_n9586 <= n5116; + always @(posedge clock) + n_n8852 <= n5121; + always @(posedge clock) + n_n8583 <= n5126; + always @(posedge clock) + n_n8011 <= n5131; + always @(posedge clock) + n_n9473 <= n951; + always @(posedge clock) + n_n7717 <= n5136; + always @(posedge clock) + n_n8326 <= n5141; + always @(posedge clock) + n_n9163 <= n5146; + always @(posedge clock) + n_n8344 <= n5151; + always @(posedge clock) + n_n8296 <= n5156; + always @(posedge clock) + n_n8116 <= n5161; + always @(posedge clock) + n_n8267 <= n5166; + always @(posedge clock) + n_n7686 <= n5171; + always @(posedge clock) + n_n9061 <= n5176; + always @(posedge clock) + n_n9338 <= n5181; + always @(posedge clock) + n_n9000 <= n956; + always @(posedge clock) + n_n7688 <= n5186; + always @(posedge clock) + n_n9081 <= n5191; + always @(posedge clock) + n_n6910 <= n5196; + always @(posedge clock) + n_n8727 <= n5201; + always @(posedge clock) + n_n7674 <= n5206; + always @(posedge clock) + n_n7330 <= n5211; + always @(posedge clock) + n_n8966 <= n5216; + always @(posedge clock) + n_n7843 <= n5221; + always @(posedge clock) + n_n8847 <= n5226; + always @(posedge clock) + n_n9376 <= n5231; + always @(posedge clock) + n_n8001 <= n961; + always @(posedge clock) + n_n7553 <= n5236; + always @(posedge clock) + n_n9292 <= n5241; + always @(posedge clock) + n_n7464 <= n5246; + always @(posedge clock) + n_n8146 <= n5251; + always @(posedge clock) + n_n8439 <= n5256; + always @(posedge clock) + n_n9498 <= n5261; + always @(posedge clock) + n_n8118 <= n5266; + always @(posedge clock) + n_n9452 <= n5271; + always @(posedge clock) + n_n9239 <= n5276; + always @(posedge clock) + n_n9237 <= n5281; + always @(posedge clock) + n_n9554 <= n966; + always @(posedge clock) + n_n9488 <= n5286; + always @(posedge clock) + ndn3_2 <= n5291; + always @(posedge clock) + n_n9522 <= n5296; + always @(posedge clock) + n_n9313 <= n5301; + always @(posedge clock) + n_n7435 <= n5306; + always @(posedge clock) + n_n8665 <= n5311; + always @(posedge clock) + n_n9593 <= n5316; + always @(posedge clock) + n_n8303 <= n5321; + always @(posedge clock) + n_n7022 <= n5326; + always @(posedge clock) + n_n9173 <= n5331; + always @(posedge clock) + n_n8508 <= n971; + always @(posedge clock) + n_n9261 <= n5336; + always @(posedge clock) + n_n7150 <= n5341; + always @(posedge clock) + n_n9455 <= n5346; + always @(posedge clock) + n_n8371 <= n5351; + always @(posedge clock) + nsr3_20 <= n5356; + always @(posedge clock) + n_n8271 <= n5361; + always @(posedge clock) + n_n9542 <= n5366; + always @(posedge clock) + n_n7444 <= n5371; + always @(posedge clock) + ndn3_40 <= n5376; + always @(posedge clock) + n_n7130 <= n5381; + always @(posedge clock) + n_n9635 <= n976; + always @(posedge clock) + n_n9347 <= n5386; + always @(posedge clock) + n_n8102 <= n5391; + always @(posedge clock) + n_n9225 <= n5396; + always @(posedge clock) + n_n8462 <= n5401; + always @(posedge clock) + n_n8088 <= n5406; + always @(posedge clock) + n_n9026 <= n5411; + always @(posedge clock) + n_n9289 <= n5416; + always @(posedge clock) + n_n7661 <= n5421; + always @(posedge clock) + n_n8108 <= n5426; + always @(posedge clock) + n_n8921 <= n5431; + always @(posedge clock) + n_n7190 <= n981; + always @(posedge clock) + n_n7859 <= n5436; + always @(posedge clock) + n_n7732 <= n5441; + always @(posedge clock) + n_n7956 <= n5446; + always @(posedge clock) + n_n9520 <= n5451; + always @(posedge clock) + n_n7666 <= n5456; + always @(posedge clock) + n_n7678 <= n5461; + always @(posedge clock) + n_n7846 <= n5466; + always @(posedge clock) + n_n8280 <= n5471; + always @(posedge clock) + n_n8841 <= n5476; + always @(posedge clock) + n_n7336 <= n5481; + assign psv39_8_8_ = 8'he4 >> { n_n9366, tin_psv39_8_8_, n_n7154 }; + assign psv39_0_0_ = 8'he4 >> { n_n9424, tin_psv39_0_0_, n_n6986 }; + assign psv13_5_5_ = 8'he4 >> { n_n9004, tin_psv13_5_5_, n_n7561 }; + assign psv2_13_13_ = 8'he4 >> { n_n9169, tin_psv2_13_13_, n_n8245 }; + assign psv2_8_8_ = 8'he4 >> { n_n8303, tin_psv2_8_8_, n_n8121 }; + assign psv38_2_2_ = 8'he4 >> { n_n6910, tin_psv38_2_2_, n_n7146 }; + assign psv33_5_5_ = 8'he4 >> { n_n9148, tin_psv33_5_5_, n_n7050 }; + assign psv26_6_6_ = 8'he4 >> { n_n6980, tin_psv26_6_6_, n_n7622 }; + assign psv2_9_9_ = 8'he4 >> { n_n7522, tin_psv2_9_9_, n_n8918 }; + assign psv18_2_2_ = 8'he4 >> { n_n8801, tin_psv18_2_2_, n_n7905 }; + assign psv39_9_9_ = 8'he4 >> { n_n7332, tin_psv39_9_9_, n_n7717 }; + assign psv39_1_1_ = 8'he4 >> { n_n8430, tin_psv39_1_1_, n_n8946 }; + assign psv13_6_6_ = 8'he4 >> { n_n7179, tin_psv13_6_6_, n_n8568 }; + assign psv2_6_6_ = 8'he4 >> { n_n7022, tin_psv2_6_6_, n_n7150 }; + assign psv38_3_3_ = 8'he4 >> { n_n7203, tin_psv38_3_3_, n_n7491 }; + assign psv33_6_6_ = 8'he4 >> { n_n7344, tin_psv33_6_6_, n_n8243 }; + assign psv26_13_13_ = 8'he4 >> { n_n7500, tin_psv26_13_13_, n_n7381 }; + assign psv26_12_12_ = 8'he4 >> { n_n8488, tin_psv26_12_12_, n_n7798 }; + assign psv26_7_7_ = 8'he4 >> { n_n8702, tin_psv26_7_7_, n_n7362 }; + assign psv2_7_7_ = 8'he4 >> { n_n8061, tin_psv2_7_7_, n_n8392 }; + assign psv18_3_3_ = 8'he4 >> { n_n7498, tin_psv18_3_3_, n_n7079 }; + assign psv39_2_2_ = 8'he4 >> { n_n7726, tin_psv39_2_2_, n_n7978 }; + assign psv33_12_12_ = 8'he4 >> { n_n8369, tin_psv33_12_12_, n_n7493 }; + assign psv33_11_11_ = 8'he4 >> { n_n7923, tin_psv33_11_11_, n_n8665 }; + assign psv33_10_10_ = 8'he4 >> { n_n9483, tin_psv33_10_10_, n_n9123 }; + assign psv13_7_7_ = 8'he4 >> { n_n7546, tin_psv13_7_7_, n_n9228 }; + assign psv2_10_10_ = 8'he4 >> { n_n8681, tin_psv2_10_10_, n_n7244 }; + assign psv38_4_4_ = 8'he4 >> { n_n7674, tin_psv38_4_4_, n_n7052 }; + assign psv39_10_10_ = 8'he4 >> { n_n8644, tin_psv39_10_10_, n_n7330 }; + assign psv33_7_7_ = 8'he4 >> { n_n7843, tin_psv33_7_7_, n_n7140 }; + assign psv26_15_15_ = 8'he4 >> { n_n9026, tin_psv26_15_15_, n_n8389 }; + assign psv26_14_14_ = 8'he4 >> { n_n7392, tin_psv26_14_14_, n_n9200 }; + assign psv26_8_8_ = 8'he4 >> { n_n7581, tin_psv26_8_8_, n_n6937 }; + assign psv26_0_0_ = 8'he4 >> { n_n7017, tin_psv26_0_0_, n_n7246 }; + assign psv13_12_12_ = 8'he4 >> { n_n8895, tin_psv13_12_12_, n_n8055 }; + assign psv13_11_11_ = 8'he4 >> { n_n9548, tin_psv13_11_11_, n_n7336 }; + assign psv18_4_4_ = 8'he4 >> { n_n9432, tin_psv18_4_4_, n_n9006 }; + assign psv39_3_3_ = 8'he4 >> { n_n7108, tin_psv39_3_3_, n_n7507 }; + assign psv13_8_8_ = 8'he4 >> { n_n7271, tin_psv13_8_8_, n_n7261 }; + assign psv13_0_0_ = 8'he4 >> { n_n7775, tin_psv13_0_0_, n_n7176 }; + assign psv38_5_5_ = 8'he4 >> { n_n7256, tin_psv38_5_5_, n_n8655 }; + assign psv33_8_8_ = 8'he4 >> { n_n7288, tin_psv33_8_8_, n_n9306 }; + assign psv33_0_0_ = 8'he4 >> { n_n8486, tin_psv33_0_0_, n_n8672 }; + assign psv26_9_9_ = 8'he4 >> { n_n7360, tin_psv26_9_9_, n_n7310 }; + assign psv26_1_1_ = 8'he4 >> { n_n7231, tin_psv26_1_1_, n_n7699 }; + assign psv13_10_10_ = 8'he4 >> { n_n7976, tin_psv13_10_10_, n_n6956 }; + assign psv18_5_5_ = 8'he4 >> { n_n7715, tin_psv18_5_5_, n_n7903 }; + assign psv39_4_4_ = 8'he4 >> { n_n7121, tin_psv39_4_4_, n_n7117 }; + assign psv13_9_9_ = 8'he4 >> { n_n9376, tin_psv13_9_9_, n_n7944 }; + assign psv13_1_1_ = 8'he4 >> { n_n8589, tin_psv13_1_1_, n_n7013 }; + assign psv2_15_15_ = 8'he4 >> { n_n8102, tin_psv2_15_15_, n_n6948 }; + assign psv2_11_11_ = 8'he4 >> { n_n6963, tin_psv2_11_11_, n_n6952 }; + assign psv2_0_0_ = 8'he4 >> { n_n8371, tin_psv2_0_0_, n_n7024 }; + assign psv38_14_14_ = 8'he4 >> { n_n7174, tin_psv38_14_14_, n_n8454 }; + assign psv38_12_12_ = 8'he4 >> { n_n7402, tin_psv38_12_12_, n_n8605 }; + assign psv38_10_10_ = 8'he4 >> { n_n7284, tin_psv38_10_10_, n_n7181 }; + assign psv38_6_6_ = 8'he4 >> { n_n7514, tin_psv38_6_6_, n_n7556 }; + assign psv18_15_15_ = 8'he4 >> { n_n7074, tin_psv18_15_15_, n_n7019 }; + assign psv18_13_13_ = 8'he4 >> { n_n7148, tin_psv18_13_13_, n_n7415 }; + assign psv18_11_11_ = 8'he4 >> { n_n8439, tin_psv18_11_11_, n_n8195 }; + assign psv33_9_9_ = 8'he4 >> { n_n9278, tin_psv33_9_9_, n_n8725 }; + assign psv33_1_1_ = 8'he4 >> { n_n8091, tin_psv33_1_1_, n_n7635 }; + assign psv26_2_2_ = 8'he4 >> { n_n7777, tin_psv26_2_2_, n_n7276 }; + assign psv2_1_1_ = 8'he4 >> { n_n7678, tin_psv2_1_1_, n_n7467 }; + assign psv38_15_15_ = 8'he4 >> { n_n8340, tin_psv38_15_15_, n_n8216 }; + assign psv38_11_11_ = 8'he4 >> { n_n7857, tin_psv38_11_11_, n_n7033 }; + assign psv18_12_12_ = 8'he4 >> { n_n9465, tin_psv18_12_12_, n_n8817 }; + assign psv18_6_6_ = 8'he4 >> { n_n7156, tin_psv18_6_6_, n_n8230 }; + assign psv39_5_5_ = 8'he4 >> { n_n8777, tin_psv39_5_5_, n_n8633 }; + assign psv13_2_2_ = 8'he4 >> { n_n7130, tin_psv13_2_2_, n_n8251 }; + assign psv38_7_7_ = 8'he4 >> { n_n8592, tin_psv38_7_7_, n_n8713 }; + assign psv39_12_12_ = 8'he4 >> { n_n8100, tin_psv39_12_12_, n_n9476 }; + assign psv39_11_11_ = 8'he4 >> { n_n7390, tin_psv39_11_11_, n_n7315 }; + assign psv33_2_2_ = 8'he4 >> { n_n7111, tin_psv33_2_2_, n_n7209 }; + assign psv26_3_3_ = 8'he4 >> { n_n8384, tin_psv26_3_3_, n_n7338 }; + assign psv13_14_14_ = 8'he4 >> { n_n7252, tin_psv13_14_14_, n_n7959 }; + assign psv13_13_13_ = 8'he4 >> { n_n6991, tin_psv13_13_13_, n_n8704 }; + assign psv18_10_10_ = 8'he4 >> { n_n8146, tin_psv18_10_10_, n_n8974 }; + assign psv18_7_7_ = 8'he4 >> { n_n8049, tin_psv18_7_7_, n_n7659 }; + assign psv39_6_6_ = 8'he4 >> { n_n8073, tin_psv39_6_6_, n_n8047 }; + assign psv33_15_15_ = 8'he4 >> { n_n8263, tin_psv33_15_15_, n_n7026 }; + assign psv33_14_14_ = 8'he4 >> { n_n9429, tin_psv33_14_14_, n_n6988 }; + assign psv33_13_13_ = 8'he4 >> { n_n7069, tin_psv33_13_13_, n_n8290 }; + assign psv13_3_3_ = 8'he4 >> { n_n8850, tin_psv13_3_3_, n_n7586 }; + assign psv2_14_14_ = 8'he4 >> { n_n7102, tin_psv2_14_14_, n_n8683 }; + assign psv2_12_12_ = 8'he4 >> { n_n8132, tin_psv2_12_12_, n_n7286 }; + assign psv2_4_4_ = 8'he4 >> { n_n8045, tin_psv2_4_4_, n_n7291 }; + assign psv38_8_8_ = 8'he4 >> { n_n9421, tin_psv38_8_8_, n_n6984 }; + assign psv38_0_0_ = 8'he4 >> { n_n8916, tin_psv38_0_0_, n_n8921 }; + assign psv39_14_14_ = 8'he4 >> { n_n9371, tin_psv39_14_14_, n_n8441 }; + assign psv39_13_13_ = 8'he4 >> { n_n7366, tin_psv39_13_13_, n_n8831 }; + assign psv33_3_3_ = 8'he4 >> { n_n7420, tin_psv33_3_3_, n_n7409 }; + assign psv26_11_11_ = 8'he4 >> { n_n8185, tin_psv26_11_11_, n_n7308 }; + assign psv26_10_10_ = 8'he4 >> { n_n8781, tin_psv26_10_10_, n_n9580 }; + assign psv26_4_4_ = 8'he4 >> { n_n8175, tin_psv26_4_4_, n_n8112 }; + assign psv13_15_15_ = 8'he4 >> { n_n9145, tin_psv13_15_15_, n_n8406 }; + assign psv2_5_5_ = 8'he4 >> { n_n7395, tin_psv2_5_5_, n_n9446 }; + assign psv18_8_8_ = 8'he4 >> { n_n8678, tin_psv18_8_8_, n_n7242 }; + assign psv18_0_0_ = 8'he4 >> { n_n7190, tin_psv18_0_0_, n_n7065 }; + assign psv39_7_7_ = 8'he4 >> { n_n7160, tin_psv39_7_7_, n_n7183 }; + assign psv13_4_4_ = 8'he4 >> { n_n9096, tin_psv13_4_4_, n_n9085 }; + assign psv2_2_2_ = 8'he4 >> { n_n7054, tin_psv2_2_2_, n_n8510 }; + assign psv38_9_9_ = 8'he4 >> { n_n8428, tin_psv38_9_9_, n_n8944 }; + assign psv38_1_1_ = 8'he4 >> { n_n7964, tin_psv38_1_1_, n_n9373 }; + assign psv39_15_15_ = 8'he4 >> { n_n8361, tin_psv39_15_15_, n_n7411 }; + assign psv33_4_4_ = 8'he4 >> { n_n7462, tin_psv33_4_4_, n_n7003 }; + assign psv26_5_5_ = 8'he4 >> { n_n7076, tin_psv26_5_5_, n_n8423 }; + assign psv2_3_3_ = 8'he4 >> { n_n8750, tin_psv2_3_3_, n_n6912 }; + assign psv38_13_13_ = 8'he4 >> { n_n6920, tin_psv38_13_13_, n_n9531 }; + assign psv18_14_14_ = 8'he4 >> { n_n7435, tin_psv18_14_14_, n_n8762 }; + assign psv18_9_9_ = 8'he4 >> { n_n6961, tin_psv18_9_9_, n_n6950 }; + assign psv18_1_1_ = 8'he4 >> { n_n9535, tin_psv18_1_1_, n_n7387 }; + assign n501_1 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9280, preset }; + assign n4711 = 4'h1 >> { preset, nsr3_37 }; + assign n506_1 = 32'd1426150400 >> { n3730, n_n9172, ndn3_37, nsr3_37, preset }; + assign n3730 = 4'h2 >> { n3731_1, n_n9434 }; + assign n3731_1 = 8'h15 >> { n_n8930, n_n8929, n3732 }; + assign n3732 = 32'd357913941 >> { n3781_1, n3733, n3754, n3767, n_n8930 }; + assign n3733 = 16'h8000 >> { n3734, n3745, n3748, n3751_1 }; + assign n3734 = 64'h0008080800888888 >> { n3743, n3744, n_n9561, n_n9557, n3735, n3739 }; + assign n3735 = 64'h0000077707770777 >> { n3738, n_n9556, n3737, n_n9558, n3736_1, n_n9554 }; + assign n3736_1 = 4'h8 >> { nsr3_38, nen3_36 }; + assign n3737 = 4'h8 >> { nsr3_23, ndn3_19 }; + assign n3738 = 4'h8 >> { nsr3_35, ndn3_29 }; + assign n3739 = 64'h0000077707770777 >> { n_n9560, n3742, n3741_1, n_n9555, n3740, n_n9559 }; + assign n3740 = 4'h8 >> { nsr3_20, ndn3_17 }; + assign n3741_1 = 4'h8 >> { nsr3_37, nen3_34 }; + assign n3742 = 4'h2 >> { nsr3_13, nsr3_14 }; + assign n3743 = 4'h8 >> { nsr3_30, ndn3_26 }; + assign n3744 = 4'h8 >> { nsr3_13, ndn3_12 }; + assign n3745 = 64'h0008080800888888 >> { n3738, n3742, n_n8199, n_n8197, n3746_1, n3747 }; + assign n3746_1 = 64'h0000077707770777 >> { n3744, n_n8200, n3737, n_n8198, n3743, n_n8366 }; + assign n3747 = 64'h0000077707770777 >> { n_n8710, n3741_1, n3736_1, n_n8196, n3740, n_n9280 }; + assign n3748 = 64'h0008080800888888 >> { n3736_1, n3742, n_n9165, n_n9578, n3749, n3750 }; + assign n3749 = 64'h0000077707770777 >> { n3741_1, n_n9160, n_n9164, n3740, n3743, n_n9162 }; + assign n3750 = 64'h0000077707770777 >> { n3744, n_n9166, n_n9161, n3738, n3737, n_n9163 }; + assign n3751_1 = 64'h0008080800888888 >> { n3736_1, n3744, n_n9410, n_n9296, n3752, n3753 }; + assign n3752 = 64'h0000077707770777 >> { n_n9539, n3741_1, n_n9289, n3738, n3737, n_n9298 }; + assign n3753 = 64'h0000077707770777 >> { n_n9292, n3742, n_n9291, n3740, n3743, n_n9290 }; + assign n3754 = 16'h8000 >> { n3755, n3758, n3761_1, n3764 }; + assign n3755 = 64'h0008080800888888 >> { n3738, n3744, n_n8650, n_n8796, n3756_1, n3757 }; + assign n3756_1 = 64'h0000077707770777 >> { n3736_1, n_n8646, n_n8648, n3740, n3743, n_n9242 }; + assign n3757 = 64'h0000077707770777 >> { n3742, n_n8649, n_n8647, n3741_1, n3737, n_n9013 }; + assign n3758 = 64'h0008080800888888 >> { n3737, n3744, n_n8037, n_n7853, n3759, n3760 }; + assign n3759 = 64'h0000077707770777 >> { n_n8756, n3741_1, n_n7854, n3740, n3743, n_n8972 }; + assign n3760 = 64'h0000077707770777 >> { n3742, n_n9510, n_n7852, n3738, n3736_1, n_n8171 }; + assign n3761_1 = 64'h0008080800888888 >> { n3743, n3742, n_n8574, n_n8970, n3762, n3763 }; + assign n3762 = 64'h0000077707770777 >> { n3744, n_n8575, n3737, n_n9150, n3736_1, n_n8570 }; + assign n3763 = 64'h0000077707770777 >> { n3741_1, n_n8571, n3738, n_n8572, n3740, n_n8573 }; + assign n3764 = 64'h0008080800888888 >> { n3743, n3736_1, n_n8235, n_n8237, n3766_1, n3765 }; + assign n3765 = 64'h0000077707770777 >> { n3744, n_n8241, n_n8312, n3738, n3737, n_n8238 }; + assign n3766_1 = 64'h0000077707770777 >> { n3742, n_n8240, n3741_1, n_n8236, n3740, n_n8239 }; + assign n3767 = 16'h8000 >> { n3768, n3771_1, n3775, n3778 }; + assign n3768 = 64'h0008080800888888 >> { n3744, n3741_1, n_n9358, n_n9363, n3770, n3769 }; + assign n3769 = 64'h0000077707770777 >> { n3738, n_n9359, n3737, n_n9361, n3743, n_n9360 }; + assign n3770 = 64'h0000077707770777 >> { n_n9362, n3742, n3736_1, n_n9357, n3740, n_n9552 }; + assign n3771_1 = 64'h0008080800888888 >> { n3743, n3736_1, n_n8016, n_n7583, n3773, n3772 }; + assign n3772 = 16'h0777 >> { n3738, n_n8968, n3740, n_n8447 }; + assign n3773 = 32'd2763306 >> { n3742, n_n7584, n3744, n_n8691, n3774 }; + assign n3774 = 64'h007f7f7f7f7f7f7f >> { ndn3_19, nsr3_23, n_n7985, nsr3_37, nen3_34, n_n7582 }; + assign n3775 = 64'h0008080800888888 >> { n3744, n3741_1, n_n9437, n_n9442, n3777, n3776_1 }; + assign n3776_1 = 64'h0000077707770777 >> { n3737, n_n9440, n_n9550, n3740, n3743, n_n9439 }; + assign n3777 = 64'h0000077707770777 >> { n3742, n_n9441, n_n9438, n3738, n3736_1, n_n9436 }; + assign n3778 = 64'h0008080800888888 >> { n3744, n3742, n_n7771, n_n7961, n3779, n3780 }; + assign n3779 = 64'h0000077707770777 >> { n_n7768, n3741_1, n3736_1, n_n8173, n3740, n_n7770 }; + assign n3780 = 64'h0000077707770777 >> { n3738, n_n9331, n3737, n_n8803, n3743, n_n7769 }; + assign n3781_1 = 16'h8000 >> { n3782, n3785, n3788, n3791_1 }; + assign n3782 = 64'h0008080800888888 >> { n3743, n3740, n_n8272, n_n8270, n3783, n3784 }; + assign n3783 = 64'h0000077707770777 >> { n_n8269, n3741_1, n_n8274, n3744, n3736_1, n_n8508 }; + assign n3784 = 64'h0000077707770777 >> { n3742, n_n8273, n_n8348, n3738, n3737, n_n8271 }; + assign n3785 = 64'h0008080800888888 >> { n3743, n3744, n_n8615, n_n9244, n3786_1, n3787 }; + assign n3786_1 = 64'h0000077707770777 >> { n3742, n_n8531, n3737, n_n8935, n3736_1, n_n8528 }; + assign n3787 = 64'h0000077707770777 >> { n3741_1, n_n8529, n3738, n_n9275, n3740, n_n8530 }; + assign n3788 = 64'h0008080800888888 >> { n3744, n3741_1, n_n8875, n_n7630, n3790, n3789 }; + assign n3789 = 64'h0000077707770777 >> { n3738, n_n8613, n3736_1, n_n7627, n3743, n_n8141 }; + assign n3790 = 64'h0000077707770777 >> { n3742, n_n7629, n3737, n_n7983, n3740, n_n7628 }; + assign n3791_1 = 64'h0008080800888888 >> { n3740, n3741_1, n_n8118, n_n8685, n3793, n3792 }; + assign n3792 = 16'h0777 >> { n_n7704, n3742, n3737, n_n7703 }; + assign n3793 = 32'd2763306 >> { n3744, n_n8577, n3736_1, n_n7701, n3794 }; + assign n3794 = 64'h007f7f7f7f7f7f7f >> { ndn3_26, nsr3_30, n_n7702, nsr3_35, ndn3_29, n_n9294 }; + assign n511_1 = 32'd1426150400 >> { n3796_1, n_n9260, ndn3_37, nsr3_37, preset }; + assign n3796_1 = 4'h2 >> { n3731_1, n_n9537 }; + assign n516_1 = 16'h3120 >> { n_n7726, n_n7376, preset, n3798 }; + assign n3798 = 4'h2 >> { ndn3_40, ndn3_39 }; + assign n521_1 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8270, preset }; + assign n526_1 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8196, preset }; + assign n531_1 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9150, preset }; + assign n536_1 = 16'h3120 >> { n_n9267, n3803, preset, n3812 }; + assign n3803 = 32'd1718184345 >> { n3804, n3831_1, n3853, n3989, n3997 }; + assign n3804 = 64'h8888008808080008 >> { n3829, n3830, n_n9230, n_n9121, n3825, n3805 }; + assign n3805 = 64'h0088888800080808 >> { n3823, n3824, n_n8609, n_n8377, n3820, n3806_1 }; + assign n3806_1 = 32'd8421504 >> { n_n7873, n3819, n3815, n3807, n3811_1 }; + assign n3807 = 64'h0000077707770777 >> { n3810, n_n9327, n_n7980, n3809, n3808, n_n7881 }; + assign n3808 = 4'h2 >> { ndn3_4, ndn3_2 }; + assign n3809 = 4'h2 >> { ndn3_36, nen3_36 }; + assign n3810 = 4'h2 >> { ndn3_34, nen3_34 }; + assign n3811_1 = 64'h0000077707770777 >> { n_n7880, n3814, n_n7874, n3813, n3812, n_n8051 }; + assign n3812 = 4'h2 >> { ndn3_11, ndn3_9 }; + assign n3813 = 4'h2 >> { ndn3_39, nen3_39 }; + assign n3814 = 4'h2 >> { ndn3_9, ndn3_7 }; + assign n3815 = 64'h0000770777077707 >> { n3818, n_n9458, n3817, n_n7878, n3816_1, n_n7876 }; + assign n3816_1 = 4'h2 >> { ndn3_21, ndn3_19 }; + assign n3817 = 16'hdd0d >> { ndn3_27, ndn3_26, ndn3_17, ndn3_16 }; + assign n3818 = 4'h2 >> { ngfdn_3, ndn3_46 }; + assign n3819 = 4'h2 >> { ndn3_44, ndn3_42 }; + assign n3820 = 16'h0ddd >> { n_n9000, n3822, n3821_1, n_n8856 }; + assign n3821_1 = 16'hdd0d >> { ndn3_40, ndn3_39, ndn3_26, ndn3_25 }; + assign n3822 = 4'h2 >> { ndn3_28, nen3_28 }; + assign n3823 = 64'hdd0ddd0d0000dd0d >> { ndn3_16, nen3_16, ndn3_19, nen3_19, ndn3_12, ndn3_11 }; + assign n3824 = 4'h2 >> { ndn3_46, ndn3_44 }; + assign n3825 = 64'h0000077707770777 >> { n3828, n_n7879, n3827, n_n7875, n3826_1, n_n7877 }; + assign n3826_1 = 4'h2 >> { ndn3_18, ndn3_17 }; + assign n3827 = 4'h2 >> { ndn3_22, nen3_22 }; + assign n3828 = 4'h1 >> { nsr3_13, ndn3_15 }; + assign n3829 = 64'hdd0ddd0d0000dd0d >> { ndn3_7, ndn3_4, ndn3_25, ndn3_22, ndn3_29, ndn3_28 }; + assign n3830 = 16'hdd0d >> { ndn3_42, ndn3_40, ndn3_32, ndn3_29 }; + assign n3831_1 = 32'd2147516544 >> { n_n7876, n3852, n3848, n3832, n3841_1 }; + assign n3832 = 32'd2324299914 >> { n3840, n_n8961, n_n8789, n3839, n3833 }; + assign n3833 = 32'd2763306 >> { n_n8661, n3838, n3837, n_n7642, n3834 }; + assign n3834 = 16'h0777 >> { n3836_1, n_n7649, n3835, n_n8328 }; + assign n3835 = 4'h2 >> { ndn3_42, ndn3_40 }; + assign n3836_1 = 4'h2 >> { ndn3_32, ndn3_29 }; + assign n3837 = 4'h2 >> { ndn3_12, ndn3_11 }; + assign n3838 = 4'h2 >> { ndn3_16, nen3_16 }; + assign n3839 = 64'hdd0ddd0d0000dd0d >> { ndn3_22, nen3_22, ndn3_9, ndn3_7, ndn3_26, ndn3_25 }; + assign n3840 = 64'hddd0ddd00000ddd0 >> { ndn3_11, ndn3_9, ndn3_15, nsr3_13, ndn3_17, ndn3_16 }; + assign n3841_1 = 16'h0888 >> { n_n8552, n3798, n3842, n3844 }; + assign n3842 = 16'h0777 >> { n3824, n_n7640, n3843, n_n7641 }; + assign n3843 = 4'h2 >> { ndn3_25, ndn3_22 }; + assign n3844 = 64'hdd0ddd0d0000dd0d >> { n3847, n_n7644, n3846_1, n_n9000, n3845, n_n8779 }; + assign n3845 = 16'hdd0d >> { ndn3_44, ndn3_42, ndn3_34, nen3_34 }; + assign n3846_1 = 16'hdd0d >> { ndn3_39, nen3_39, ndn3_29, ndn3_28 }; + assign n3847 = 16'hdd0d >> { ndn3_4, ndn3_2, ndn3_36, nen3_36 }; + assign n3848 = 32'd2763306 >> { n_n8856, n3851_1, n3816_1, n_n8058, n3849 }; + assign n3849 = 64'h0000077707770777 >> { n3818, n_n8188, n_n7878, n3826_1, n3850, n_n7643 }; + assign n3850 = 4'h2 >> { ndn3_7, ndn3_4 }; + assign n3851_1 = 4'h2 >> { ndn3_27, ndn3_26 }; + assign n3852 = 16'hdd0d >> { ndn3_28, nen3_28, ndn3_19, nen3_19 }; + assign n3853 = 64'heeefaaae888a0008 >> { n3854, n3870, n3886_1, n3988, n3878, n3862 }; + assign n3854 = 64'h8888008808080008 >> { n3846_1, n3847, n_n9183, n_n9492, n3860, n3855 }; + assign n3855 = 64'h8000000080008000 >> { n_n9181, n3839, n3858, n3859, n3856_1, n3857 }; + assign n3856_1 = 16'h0777 >> { n3818, n_n9171, n3851_1, n_n9493 }; + assign n3857 = 64'h0000077707770777 >> { n3835, n_n9172, n_n9179, n3837, n3798, n_n9173 }; + assign n3858 = 16'h0777 >> { n_n9473, n3824, n3836_1, n_n9175 }; + assign n3859 = 64'h0777077700000777 >> { n3852, n_n9495, n_n9497, n3826_1, n3843, n_n9176 }; + assign n3860 = 32'd707395626 >> { n3840, n_n9180, n3850, n_n9182, n3861_1 }; + assign n3861_1 = 64'h0777077700000777 >> { n3845, n_n9174, n_n9177, n3816_1, n3838, n_n9178 }; + assign n3862 = 32'd2147516544 >> { n_n9499, n3823, n3869, n3863, n3866_1 }; + assign n3863 = 64'h8888008808080008 >> { n3829, n3830, n_n9491, n_n9502, n3865, n3864 }; + assign n3864 = 16'h0ddd >> { n3822, n_n9492, n3821_1, n_n9493 }; + assign n3865 = 64'h0000077707770777 >> { n_n9501, n3814, n3810, n_n9490, n3813, n_n9488 }; + assign n3866_1 = 64'h0008080800888888 >> { n3826_1, n3827, n_n9494, n_n9496, n3868, n3867 }; + assign n3867 = 64'h0000770777077707 >> { n_n9489, n3809, n3817, n_n9497, n3824, n_n9486 }; + assign n3868 = 64'h0000077707770777 >> { n3828, n_n9498, n3816_1, n_n9495, n3812, n_n9500 }; + assign n3869 = 64'h0000077707770777 >> { n_n9485, n3818, n3819, n_n9487, n3808, n_n9503 }; + assign n3870 = 32'd8421504 >> { n_n8042, n3838, n3877, n3871_1, n3874 }; + assign n3871_1 = 16'h8088 >> { n_n9008, n3840, n3872, n3873 }; + assign n3872 = 64'h0000077707770777 >> { n3824, n_n7598, n3816_1, n_n7603, n3826_1, n_n8233 }; + assign n3873 = 64'h0000077707770777 >> { n3837, n_n8296, n_n7602, n3843, n3850, n_n7604 }; + assign n3874 = 64'h8888008808080008 >> { n3845, n3846_1, n_n7821, n_n7600, n3875, n3876_1 }; + assign n3875 = 64'h0000077707770777 >> { n3851_1, n_n7822, n_n7599, n3835, n3798, n_n8253 }; + assign n3876_1 = 16'h7707 >> { n3852, n_n7823, n3836_1, n_n7601 }; + assign n3877 = 64'h7707770700007707 >> { n3847, n_n8736, n3839, n_n8791, n3818, n_n9237 }; + assign n3878 = 64'h8000000080008000 >> { n_n7825, n3823, n3884, n3885, n3879, n3882 }; + assign n3879 = 64'h0008080800888888 >> { n3824, n3814, n_n7826, n_n9036, n3880, n3881_1 }; + assign n3880 = 64'h7707770700007707 >> { n3821_1, n_n7822, n3830, n_n9232, n3819, n_n9081 }; + assign n3881_1 = 64'h0000077707770777 >> { n3813, n_n7819, n_n7827, n3808, n3812, n_n8617 }; + assign n3882 = 32'd9079434 >> { n_n8898, n3818, n_n8233, n3817, n3883 }; + assign n3883 = 64'h0000077707770777 >> { n3810, n_n7820, n_n8699, n3827, n3816_1, n_n7823 }; + assign n3884 = 64'h0000077707770777 >> { n3822, n_n7821, n_n7925, n3809, n3826_1, n_n7824 }; + assign n3885 = 16'h0ddd >> { n3828, n_n9186, n3829, n_n7835 }; + assign n3886_1 = 64'h0008080a0a8a8aaa >> { n3914, n3935, n3949, n3926_1, n3962, n3887 }; + assign n3887 = 64'h7f80808080808080 >> { n3888, n3891_1, n3896_1, n3901_1, n3904, n3909 }; + assign n3888 = 64'h8888008808080008 >> { n3829, n3823, n_n9404, n_n9407, n3890, n3889 }; + assign n3889 = 64'hf7f7f7f700f7f7f7 >> { ndn3_28, n_n9397, nen3_28, ndn3_11, ndn3_9, n_n9405 }; + assign n3890 = 64'hf7f7f7f700f7f7f7 >> { ndn3_44, ndn3_42, n_n9392, ngfdn_3, ndn3_46, n_n9390 }; + assign n3891_1 = 16'h0002 >> { n3892, n3894, n3895, n3893 }; + assign n3892 = 32'd134785544 >> { ndn3_42, ndn3_40, ndn3_32, ndn3_29, n_n9396 }; + assign n3893 = 64'hf7f7f7f700f7f7f7 >> { ndn3_9, ndn3_7, n_n9406, ndn3_18, ndn3_17, n_n9401 }; + assign n3894 = 32'd134785544 >> { ndn3_27, ndn3_26, ndn3_17, ndn3_16, n_n9402 }; + assign n3895 = 32'd134785544 >> { ndn3_40, ndn3_39, ndn3_26, ndn3_25, n_n9398 }; + assign n3896_1 = 16'h8000 >> { n3897, n3898, n3899, n3900 }; + assign n3897 = 64'hfdfdfdfd00fdfdfd >> { ndn3_39, nen3_39, n_n9393, nsr3_13, ndn3_15, n_n9403 }; + assign n3898 = 64'hf7f7f7f700f7f7f7 >> { ndn3_21, n_n9400, ndn3_19, ndn3_36, nen3_36, n_n9394 }; + assign n3899 = 64'hf7f7f7f700f7f7f7 >> { ndn3_4, n_n9408, ndn3_2, ndn3_34, nen3_34, n_n9395 }; + assign n3900 = 64'hf7f7f7f700f7f7f7 >> { ndn3_46, ndn3_44, n_n9391, ndn3_22, nen3_22, n_n9399 }; + assign n3901_1 = 64'h8888008808080008 >> { n3839, n3840, n_n9134, n_n9135, n3902, n3903 }; + assign n3902 = 64'hf7f7f7f700f7f7f7 >> { ndn3_32, ndn3_29, n_n9129, ndn3_12, ndn3_11, n_n9133 }; + assign n3903 = 32'd3216971199 >> { ndn3_42, n_n9127, ndn3_39, n_n9128, ndn3_40 }; + assign n3904 = 16'h0001 >> { n3905, n3906_1, n3907, n3908 }; + assign n3905 = 32'd134785544 >> { ndn3_39, nen3_39, ndn3_29, ndn3_28, n_n9397 }; + assign n3906_1 = 32'd134785544 >> { ndn3_4, ndn3_2, ndn3_36, nen3_36, n_n9137 }; + assign n3907 = 32'd134785544 >> { ndn3_28, nen3_28, ndn3_19, nen3_19, n_n9400 }; + assign n3908 = 32'd134785544 >> { ndn3_44, ndn3_42, ndn3_34, nen3_34, n_n9212 }; + assign n3909 = 16'h8000 >> { n3910, n3911_1, n3912, n3913 }; + assign n3910 = 64'hf7f7f7f700f7f7f7 >> { ndn3_16, nen3_16, n_n9132, ndn3_27, ndn3_26, n_n9398 }; + assign n3911_1 = 64'hf7f7f7f700f7f7f7 >> { ndn3_21, n_n9131, ndn3_19, ndn3_18, ndn3_17, n_n9402 }; + assign n3912 = 64'hf7f7f7f700f7f7f7 >> { ndn3_46, ndn3_44, n_n9126, ndn3_25, ndn3_22, n_n9130 }; + assign n3913 = 64'hf7f7f7f700f7f7f7 >> { ngfdn_3, ndn3_46, n_n9125, ndn3_7, ndn3_4, n_n9136 }; + assign n3914 = 64'h0000000000008000 >> { n3915, n3916_1, n3917, n3919, n3920, n3921_1 }; + assign n3915 = 4'h2 >> { n3829, n_n7837 }; + assign n3916_1 = 4'h2 >> { n3823, n_n7742 }; + assign n3917 = 32'd2763306 >> { n3809, n_n7735, n3812, n_n7743, n3918 }; + assign n3918 = 64'hf7f7f7f700f7f7f7 >> { ndn3_28, n_n7738, nen3_28, ndn3_39, nen3_39, n_n7734 }; + assign n3919 = 64'h00000ddd0ddd0ddd >> { n_n8053, n3814, n3818, n_n8135, n3830, n_n7737 }; + assign n3920 = 16'hdd0d >> { n3817, n_n9528, n3821_1, n_n7739 }; + assign n3921_1 = 16'h8000 >> { n3922, n3923, n3924, n3925 }; + assign n3922 = 64'hf7f7f7f700f7f7f7 >> { ndn3_21, n_n7741, ndn3_19, ndn3_18, ndn3_17, n_n9141 }; + assign n3923 = 64'hf7f7f7f700f7f7f7 >> { ndn3_4, ndn3_2, n_n7744, ndn3_22, nen3_22, n_n7740 }; + assign n3924 = 64'hf7f7f7f700f7f7f7 >> { ndn3_44, n_n9059, ndn3_42, ndn3_34, nen3_34, n_n7736 }; + assign n3925 = 64'hfdfdfdfd00fdfdfd >> { ndn3_46, ndn3_44, n_n8247, nsr3_13, ndn3_15, n_n9189 }; + assign n3926_1 = 64'h0000000080000000 >> { n3927, n3928, n3929, n3930, n3931_1, n3934 }; + assign n3927 = 4'h2 >> { n3845, n_n8638 }; + assign n3928 = 16'h0777 >> { n3836_1, n_n7552, n3850, n_n7554 }; + assign n3929 = 64'h0000077707770777 >> { n3835, n_n8636, n3816_1, n_n8035, n3826_1, n_n9528 }; + assign n3930 = 64'hdd0ddd0d0000dd0d >> { n3847, n_n8009, n3852, n_n7741, n3846_1, n_n7738 }; + assign n3931_1 = 64'h8888008808080008 >> { n3839, n3840, n_n9563, n_n7553, n3932, n3933 }; + assign n3932 = 64'hf7f7f7f700f7f7f7 >> { ndn3_46, ndn3_44, n_n8499, ndn3_25, ndn3_22, n_n8533 }; + assign n3933 = 64'hf7f7f7f700f7f7f7 >> { ndn3_27, n_n7739, ndn3_26, ndn3_12, ndn3_11, n_n8298 }; + assign n3934 = 64'h0000077707770777 >> { n_n9239, n3818, n3838, n_n8381, n3798, n_n7993 }; + assign n3935 = 64'h0000000000008000 >> { n3936_1, n3937, n3938, n3940, n3945, n3947 }; + assign n3936_1 = 4'h2 >> { n3829, n_n9324 }; + assign n3937 = 4'h2 >> { n3823, n_n9321 }; + assign n3938 = 32'd2763306 >> { n_n9313, n3810, n3824, n_n9309, n3939 }; + assign n3939 = 64'hf7f7f7f700f7f7f7 >> { ndn3_28, n_n9315, nen3_28, ngfdn_3, ndn3_46, n_n9308 }; + assign n3940 = 16'h0002 >> { n3941_1, n3943, n3944, n3942 }; + assign n3941_1 = 32'd134785544 >> { ndn3_27, ndn3_26, ndn3_17, ndn3_16, n_n9319 }; + assign n3942 = 64'hf7f7f7f700f7f7f7 >> { ndn3_4, ndn3_2, n_n9325, ndn3_22, nen3_22, n_n9316 }; + assign n3943 = 32'd134785544 >> { ndn3_42, ndn3_40, ndn3_32, ndn3_29, n_n9314 }; + assign n3944 = 32'd134785544 >> { ndn3_40, ndn3_39, ndn3_26, ndn3_25, n_n9368 }; + assign n3945 = 32'd2763306 >> { n3809, n_n9312, n3819, n_n9310, n3946_1 }; + assign n3946_1 = 64'hf7f7f7f700f7f7f7 >> { ndn3_39, nen3_39, n_n9311, ndn3_18, ndn3_17, n_n9318 }; + assign n3947 = 32'd2763306 >> { n_n9323, n3814, n3816_1, n_n9317, n3948 }; + assign n3948 = 64'hfdfdfdfd00fdfdfd >> { ndn3_11, ndn3_9, n_n9322, nsr3_13, ndn3_15, n_n9320 }; + assign n3949 = 64'h8000000080008000 >> { n_n9051, n3840, n3958, n3960, n3950, n3953 }; + assign n3950 = 16'h8088 >> { n_n9052, n3839, n3952, n3951_1 }; + assign n3951_1 = 64'hf7f7f7f700f7f7f7 >> { ndn3_46, n_n9042, ndn3_44, ndn3_18, ndn3_17, n_n9319 }; + assign n3952 = 64'hf7f7f7f700f7f7f7 >> { ndn3_16, nen3_16, n_n9049, ndn3_7, ndn3_4, n_n9053 }; + assign n3953 = 16'h0001 >> { n3954, n3955, n3956_1, n3957 }; + assign n3954 = 32'd134785544 >> { ndn3_28, nen3_28, ndn3_19, nen3_19, n_n9317 }; + assign n3955 = 32'd134785544 >> { ndn3_4, ndn3_2, ndn3_36, nen3_36, n_n9054 }; + assign n3956_1 = 32'd134785544 >> { ndn3_39, nen3_39, ndn3_29, ndn3_28, n_n9315 }; + assign n3957 = 32'd134785544 >> { ndn3_44, ndn3_42, ndn3_34, nen3_34, n_n9045 }; + assign n3958 = 32'd2763306 >> { n_n9041, n3818, n3835, n_n9043, n3959 }; + assign n3959 = 64'hf7f7f7f700f7f7f7 >> { ndn3_25, ndn3_22, n_n9047, ndn3_21, ndn3_19, n_n9048 }; + assign n3960 = 32'd2763306 >> { n3851_1, n_n9368, n3798, n_n9044, n3961_1 }; + assign n3961_1 = 64'hf7f7f7f700f7f7f7 >> { ndn3_32, ndn3_29, n_n9046, ndn3_12, ndn3_11, n_n9050 }; + assign n3962 = 64'h007f7f7f7f7f7f7f >> { n3975, n3978, n3983, n3963, n3966_1, n3972 }; + assign n3963 = 64'h1111001101010001 >> { n3846_1, n3852, n_n7654, n_n7652, n3964, n3965 }; + assign n3964 = 32'd134785544 >> { ndn3_44, ndn3_42, ndn3_34, nen3_34, n_n7509 }; + assign n3965 = 32'd134785544 >> { ndn3_4, ndn3_2, ndn3_36, nen3_36, n_n8011 }; + assign n3966_1 = 32'd128 >> { n3967, n3968, n3969, n3970, n3971_1 }; + assign n3967 = 8'h08 >> { ndn3_40, ndn3_39, n_n7995 }; + assign n3968 = 8'h08 >> { ndn3_12, ndn3_11, n_n8075 }; + assign n3969 = 64'hf7f7f7f700f7f7f7 >> { ndn3_25, n_n9522, ndn3_22, ndn3_18, ndn3_17, n_n7661 }; + assign n3970 = 64'hf7f7f7f700f7f7f7 >> { ndn3_42, ndn3_40, n_n8477, ndn3_27, ndn3_26, n_n7728 }; + assign n3971_1 = 64'hf7f7f7f700f7f7f7 >> { ndn3_46, ndn3_44, n_n7670, ndn3_21, ndn3_19, n_n7510 }; + assign n3972 = 64'h8888008808080008 >> { n3839, n3840, n_n9566, n_n8641, n3973, n3974 }; + assign n3973 = 64'hf7f7f7f700f7f7f7 >> { ndn3_16, n_n8210, nen3_16, ndn3_32, ndn3_29, n_n8526 }; + assign n3974 = 64'hf7f7f7f700f7f7f7 >> { ngfdn_3, ndn3_46, n_n8670, ndn3_7, ndn3_4, n_n7511 }; + assign n3975 = 64'h8888008808080008 >> { n3829, n3823, n_n7655, n_n7657, n3976_1, n3977 }; + assign n3976_1 = 64'hfdfdfdfd00fdfdfd >> { ndn3_44, ndn3_42, n_n9061, nsr3_13, ndn3_15, n_n8260 }; + assign n3977 = 64'hf7f7f7f700f7f7f7 >> { ngfdn_3, n_n8862, ndn3_46, ndn3_34, nen3_34, n_n9075 }; + assign n3978 = 16'h0002 >> { n3979, n3981_1, n3982, n3980 }; + assign n3979 = 32'd134785544 >> { ndn3_42, ndn3_40, ndn3_32, ndn3_29, n_n8033 }; + assign n3980 = 64'hf7f7f7f700f7f7f7 >> { ndn3_22, n_n7653, nen3_22, ndn3_9, ndn3_7, n_n8619 }; + assign n3981_1 = 32'd134785544 >> { ndn3_40, ndn3_39, ndn3_26, ndn3_25, n_n7728 }; + assign n3982 = 32'd134785544 >> { ndn3_27, ndn3_26, ndn3_17, ndn3_16, n_n7661 }; + assign n3983 = 16'h8000 >> { n3984, n3985, n3986_1, n3987 }; + assign n3984 = 64'hf7f7f7f700f7f7f7 >> { ndn3_11, ndn3_9, n_n7656, ndn3_39, nen3_39, n_n7650 }; + assign n3985 = 64'hf7f7f7f700f7f7f7 >> { ndn3_4, ndn3_2, n_n8770, ndn3_18, ndn3_17, n_n9015 }; + assign n3986_1 = 64'hf7f7f7f700f7f7f7 >> { ndn3_46, ndn3_44, n_n8249, ndn3_36, nen3_36, n_n7651 }; + assign n3987 = 64'hf7f7f7f700f7f7f7 >> { ndn3_28, nen3_28, n_n7652, ndn3_21, ndn3_19, n_n7654 }; + assign n3988 = 64'h007f7f7f7f7f7f7f >> { n3901_1, n3904, n3909, n3888, n3891_1, n3896_1 }; + assign n3989 = 64'h8000000080008000 >> { n_n9605, n3829, n3995, n3996_1, n3990, n3992 }; + assign n3990 = 32'd9079434 >> { n_n9593, n3810, n_n9602, n3823, n3991_1 }; + assign n3991_1 = 16'h0777 >> { n_n9601, n3828, n3824, n_n9589 }; + assign n3992 = 64'h0008080800888888 >> { n3812, n3808, n_n9606, n_n9603, n3993, n3994 }; + assign n3993 = 64'h0777077700000777 >> { n3817, n_n9600, n_n9598, n3816_1, n3826_1, n_n9599 }; + assign n3994 = 64'h0000077707770777 >> { n3822, n_n9595, n_n9591, n3813, n3819, n_n9590 }; + assign n3995 = 64'h0000dd0ddd0ddd0d >> { n_n9592, n3809, n3821_1, n_n9596, n3830, n_n9594 }; + assign n3996_1 = 64'h0000077707770777 >> { n_n9604, n3814, n3818, n_n9588, n3827, n_n9597 }; + assign n3997 = 32'd8421504 >> { n_n9259, n3818, n4004, n3998, n4001_1 }; + assign n3998 = 64'h0808000888880088 >> { n3843, n3839, n_n9269, n_n9264, n4000, n3999 }; + assign n3999 = 64'h0000077707770777 >> { n_n9470, n3824, n_n9265, n3816_1, n3826_1, n_n9600 }; + assign n4000 = 16'h0777 >> { n_n9267, n3837, n3850, n_n9270 }; + assign n4001_1 = 64'h0008080800888888 >> { n3798, n3835, n_n9260, n_n9261, n4002, n4003 }; + assign n4002 = 16'h0777 >> { n_n9596, n3851_1, n3836_1, n_n9263 }; + assign n4003 = 64'hdd0ddd0d0000dd0d >> { n3852, n_n9598, n3846_1, n_n9595, n3845, n_n9262 }; + assign n4004 = 64'h7707770700007707 >> { n3847, n_n9271, n3840, n_n9268, n3838, n_n9266 }; + assign n1276 = 4'h2 >> { preset, n3818 }; + assign n541_1 = 32'd321978912 >> { n_n7779, n4007, n4061_1, preset, n3818 }; + assign n4007 = 64'h00000000bbbafffb >> { n4008, n4044, n4027, n4052, n4053, n4026_1 }; + assign n4008 = 4'h8 >> { n4009, n4018 }; + assign n4009 = 16'h8088 >> { n_n7803, n3823, n4010, n4015 }; + assign n4010 = 32'd2147516544 >> { n_n8116, n3829, n4014, n4011_1, n4013 }; + assign n4011_1 = 32'd2763306 >> { n3816_1, n_n7686, n3812, n_n7688, n4012 }; + assign n4012 = 16'h0777 >> { n3828, n_n9257, n3827, n_n7685 }; + assign n4013 = 16'h7707 >> { n3830, n_n8586, n3808, n_n7689 }; + assign n4014 = 64'h0000dd0ddd0ddd0d >> { n3809, n_n7732, n3817, n_n7687, n3821_1, n_n7684 }; + assign n4015 = 64'h0008080800888888 >> { n3813, n3810, n_n8889, n_n7682, n4017, n4016_1 }; + assign n4016_1 = 64'h0000077707770777 >> { n_n9467, n3818, n3819, n_n7681, n3826_1, n_n8153 }; + assign n4017 = 64'h0000077707770777 >> { n_n9119, n3814, n_n7683, n3822, n3824, n_n8024 }; + assign n4018 = 64'h8888008808080008 >> { n3846_1, n3847, n_n8110, n_n7683, n4024, n4019 }; + assign n4019 = 64'h8000000080008000 >> { n_n7668, n3840, n4022, n4023, n4020, n4021_1 }; + assign n4020 = 64'h0000077707770777 >> { n3851_1, n_n7684, n3824, n_n8628, n3816_1, n_n8597 }; + assign n4021_1 = 16'h0777 >> { n_n7687, n3826_1, n3850, n_n9300 }; + assign n4022 = 16'h0777 >> { n3836_1, n_n7666, n3835, n_n9505 }; + assign n4023 = 64'h0777077700000777 >> { n3852, n_n7686, n_n8221, n3838, n3798, n_n7664 }; + assign n4024 = 32'd707395626 >> { n3839, n_n8760, n3837, n_n8276, n4025 }; + assign n4025 = 64'h0777077700000777 >> { n3845, n_n7665, n3818, n_n7898, n3843, n_n7667 }; + assign n4026_1 = 4'h1 >> { n4009, n4018 }; + assign n4027 = 64'h000202aa002a2aaa >> { n3804, n3989, n3997, n3831_1, n3853, n4028 }; + assign n4028 = 4'h6 >> { n4029, n4037 }; + assign n4029 = 64'h0000800080008000 >> { n_n7955, n3814, n4035, n4036_1, n4030, n4033 }; + assign n4030 = 64'h8888008808080008 >> { n3829, n3830, n_n8966, n_n7956, n4032, n4031_1 }; + assign n4031_1 = 64'h0000770777077707 >> { n_n9618, n3822, n3821_1, n_n8854, n3812, n_n7954 }; + assign n4032 = 64'h0000770777077707 >> { n3827, n_n8843, n3817, n_n7952, n3826_1, n_n7951 }; + assign n4033 = 32'd2763306 >> { n_n8891, n3810, n3819, n_n7949, n4034 }; + assign n4034 = 16'h0777 >> { n3818, n_n7947, n3809, n_n7950 }; + assign n4035 = 64'h00000ddd0ddd0ddd >> { n3813, n_n8095, n3808, n_n9023, n3823, n_n8375 }; + assign n4036_1 = 64'h0000077707770777 >> { n_n7953, n3828, n3824, n_n7948, n3816_1, n_n9021 }; + assign n4037 = 64'h0000800080008000 >> { n_n8854, n3851_1, n4042, n4043, n4038, n4041_1 }; + assign n4038 = 64'h8888008808080008 >> { n3839, n3845, n_n7692, n_n7696, n4040, n4039 }; + assign n4039 = 64'h0777077700000777 >> { n3847, n_n7697, n3837, n_n7694, n3843, n_n8697 }; + assign n4040 = 64'h0000077707770777 >> { n3818, n_n7691, n3836_1, n_n7693, n3838, n_n8659 }; + assign n4041_1 = 64'h7707770700007707 >> { n3852, n_n9021, n3846_1, n_n9618, n3835, n_n8326 }; + assign n4042 = 64'h0000077707770777 >> { n3824, n_n9518, n_n9302, n3850, n3798, n_n8410 }; + assign n4043 = 64'h0777077700000777 >> { n3840, n_n7695, n_n8599, n3816_1, n3826_1, n_n7952 }; + assign n4044 = 64'h8000000080008000 >> { n_n8786, n3823, n4050, n4051_1, n4045, n4049 }; + assign n4045 = 64'h8888008808080008 >> { n3821_1, n3817, n_n9343, n_n9339, n4046_1, n4048 }; + assign n4046_1 = 32'd2763306 >> { n3828, n_n8833, n3810, n_n9159, n4047 }; + assign n4047 = 64'h00000ddd0ddd0ddd >> { n_n7225, n3827, n3824, n_n8989, n3829, n_n8416 }; + assign n4048 = 64'h00000ddd0ddd0ddd >> { n3822, n_n9338, n_n7831, n3809, n3830, n_n6976 }; + assign n4049 = 16'h0777 >> { n3814, n_n7866, n3826_1, n_n8984 }; + assign n4050 = 64'h0000077707770777 >> { n_n8980, n3818, n_n6968, n3813, n3812, n_n7424 }; + assign n4051_1 = 64'h0000077707770777 >> { n3819, n_n7920, n_n9342, n3816_1, n3808, n_n8739 }; + assign n4052 = 4'h1 >> { n4029, n4037 }; + assign n4053 = 64'h8000000080008000 >> { n_n9338, n3846_1, n4059, n4060, n4054, n4057 }; + assign n4054 = 64'h8888008808080008 >> { n3839, n3840, n_n9346, n_n9347, n4055, n4056_1 }; + assign n4055 = 16'h0777 >> { n_n9334, n3824, n3826_1, n_n9343 }; + assign n4056_1 = 16'h0777 >> { n_n9335, n3835, n3798, n_n9455 }; + assign n4057 = 32'd2763306 >> { n_n9344, n3838, n3850, n_n9348, n4058 }; + assign n4058 = 64'h0000077707770777 >> { n_n9333, n3818, n3836_1, n_n9337, n3843, n_n9340 }; + assign n4059 = 64'h0000077707770777 >> { n3851_1, n_n9339, n_n9341, n3816_1, n3837, n_n9345 }; + assign n4060 = 64'hdd0ddd0d0000dd0d >> { n3847, n_n9349, n3852, n_n9342, n3845, n_n9336 }; + assign n4061_1 = 4'h6 >> { n4062, n4070 }; + assign n4062 = 64'h8000000080008000 >> { n_n7709, n3845, n4068, n4069, n4063, n4066_1 }; + assign n4063 = 32'd707395626 >> { n3840, n_n7713, n3851_1, n_n7760, n4064 }; + assign n4064 = 32'd707395626 >> { n3839, n_n7901, n3837, n_n9210, n4065 }; + assign n4065 = 16'h0777 >> { n3824, n_n9110, n3843, n_n7711 }; + assign n4066_1 = 32'd2763306 >> { n_n7706, n3818, n3850, n_n8086, n4067 }; + assign n4067 = 64'h0000077707770777 >> { n_n7707, n3835, n_n7712, n3816_1, n3838, n_n8066 }; + assign n4068 = 64'h0000077707770777 >> { n_n7710, n3836_1, n_n7763, n3826_1, n3798, n_n7708 }; + assign n4069 = 64'hdd0ddd0d0000dd0d >> { n3847, n_n8986, n3852, n_n7762, n3846_1, n_n8852 }; + assign n4070 = 64'h0000800080008000 >> { n_n7761, n3827, n4076_1, n4077, n4071_1, n4073 }; + assign n4071_1 = 32'd707395626 >> { n3817, n_n7763, n3816_1, n_n7762, n4072 }; + assign n4072 = 64'h0000077707770777 >> { n3814, n_n7766, n3810, n_n9157, n3819, n_n7918 }; + assign n4073 = 64'h0008080800888888 >> { n3812, n3808, n_n9387, n_n7765, n4074, n4075 }; + assign n4074 = 64'h0000077707770777 >> { n3828, n_n8396, n_n7990, n3813, n3824, n_n7757 }; + assign n4075 = 64'h00000ddd0ddd0ddd >> { n3818, n_n9516, n_n8852, n3822, n3823, n_n7764 }; + assign n4076_1 = 16'h0ddd >> { n3809, n_n7758, n3821_1, n_n7760 }; + assign n4077 = 64'h0ddd0ddd00000ddd >> { n3830, n_n7759, n_n8203, n3826_1, n3829, n_n8506 }; + assign n546_1 = 16'h3120 >> { n_n9503, psv2_5_5_, preset, n4079 }; + assign n4079 = 32'd134220290 >> { preset_0_0_, n_n7476, ndn3_2, nlc1_2, nsr1_2 }; + assign n551_1 = 16'h3120 >> { n_n8150, n4081_1, preset, n3798 }; + assign n4081_1 = 32'd1771660905 >> { n4007, n4062, n4070, n4082, n4090 }; + assign n4082 = 64'h8888008808080008 >> { n3845, n3852, n_n7810, n_n8088, n4083, n4088 }; + assign n4083 = 32'd2147516544 >> { n_n7792, n3840, n4087, n4084, n4086_1 }; + assign n4084 = 32'd2763306 >> { n_n7790, n3836_1, n3826_1, n_n7811, n4085 }; + assign n4085 = 16'h0777 >> { n3818, n_n9635, n3835, n_n7788 }; + assign n4086_1 = 64'h0000077707770777 >> { n_n8223, n3824, n_n8402, n3816_1, n3798, n_n7789 }; + assign n4087 = 64'h0777077700000777 >> { n3847, n_n8108, n_n7809, n3851_1, n3837, n_n7791 }; + assign n4088 = 32'd707395626 >> { n3839, n_n7793, n3843, n_n8841, n4089 }; + assign n4089 = 64'h0777077700000777 >> { n3846_1, n_n8473, n3838, n_n9525, n3850, n_n8267 }; + assign n4090 = 32'd2147483648 >> { n4091_1, n4093, n4095, n4096_1, n4097 }; + assign n4091_1 = 32'd2763306 >> { n_n8657, n3827, n3826_1, n_n8227, n4092 }; + assign n4092 = 64'h0000dd0ddd0ddd0d >> { n3828, n_n7812, n3830, n_n8408, n3829, n_n7816 }; + assign n4093 = 32'd2324299914 >> { n3817, n_n7811, n_n7813, n3823, n4094 }; + assign n4094 = 64'h0000077707770777 >> { n_n7807, n3813, n3816_1, n_n7810, n3808, n_n7817 }; + assign n4095 = 64'h0000077707770777 >> { n_n8473, n3822, n_n7808, n3809, n3819, n_n7806 }; + assign n4096_1 = 64'h0000770777077707 >> { n_n8222, n3818, n3821_1, n_n7809, n3824, n_n8022 }; + assign n4097 = 64'h0000077707770777 >> { n3814, n_n7815, n3810, n_n7859, n3812, n_n7814 }; + assign n556_1 = 16'h3120 >> { n_n9401, n4099, preset, n3837 }; + assign n4099 = 16'ha995 >> { n4100, n3914, n3926_1, n3887 }; + assign n4100 = 8'hb2 >> { n3935, n3962, n3949 }; + assign n561_1 = 16'hf888 >> { n4103, n_n7341, n4102, n4104 }; + assign n4102 = 64'h7f80808080808080 >> { n3963, n3966_1, n3972, n3975, n3978, n3983 }; + assign n4103 = 8'h45 >> { ndn3_25, ndn3_26, preset }; + assign n4104 = 8'h02 >> { preset, ndn3_26, ndn3_25 }; + assign n566_1 = 16'h3120 >> { n_n9180, n4106_1, preset, n3814 }; + assign n4106_1 = 64'h6999699969996669 >> { n3886_1, n3988, n3870, n3878, n3854, n3862 }; + assign n571_1 = 16'h3120 >> { n_n8592, n_n9259, preset, n3824 }; + assign n576_1 = 16'h3120 >> { n_n8871, n4081_1, preset, n3813 }; + assign n581_1 = 16'h3120 >> { n_n7252, n_n7444, preset, n3818 }; + assign n586_1 = 16'h3120 >> { n_n7271, n_n8308, preset, n3818 }; + assign n591_1 = 16'h3120 >> { n_n6991, n_n7896, preset, n3818 }; + assign n596_1 = 32'd2934604872 >> { n4174, n4113, n4180, n4183, n_n8557 }; + assign n4113 = 32'd1903243377 >> { n4170, n_n8449, n4171_1, n_n8549, n4114 }; + assign n4114 = 64'h4545454504044504 >> { n4115, n4163, n_n8354, n4167, n_n8419, n4164 }; + assign n4115 = 64'h4050545500405054 >> { n4116_1, n4157, n4160, n_n9448, n_n9638, n4154 }; + assign n4116_1 = 32'd3149603506 >> { n4117, n4150, n_n9537, n4151_1, n_n8821 }; + assign n4117 = 64'h4050545500405054 >> { n4118, n4144, n4147, n_n9416, n_n9434, n4141_1 }; + assign n4118 = 32'd143306479 >> { n4119, n4123, n4126_1, n_n9353, n_n9512 }; + assign n4119 = 64'h0008080800888888 >> { n3743, n3740, n_n8729, n_n7485, n4120, n4122 }; + assign n4120 = 64'h0777077700000777 >> { n4121_1, n_n7824, n_n7598, n3741_1, n3738, n_n7428 }; + assign n4121_1 = 8'h1b >> { ndn3_12, nsr3_14, nsr3_13 }; + assign n4122 = 16'h0777 >> { n3737, n_n7429, n3736_1, n_n8898 }; + assign n4123 = 64'h0008080800888888 >> { n3740, n3736_1, n_n9390, n_n8811, n4124, n4125 }; + assign n4124 = 64'h0777077700000777 >> { n4121_1, n_n9401, n_n9126, n3741_1, n3737, n_n8810 }; + assign n4125 = 16'h0777 >> { n_n8808, n3738, n3743, n_n8809 }; + assign n4126_1 = 32'd2136413441 >> { n4127, n4132, n4137, n_n9284, n_n8707 }; + assign n4127 = 16'h0080 >> { n4130, n4129, n4128, n4131_1 }; + assign n4128 = 64'h007f7f7f7f7f7f7f >> { nen3_36, n_n8135, nsr3_38, nsr3_20, ndn3_17, n_n7375 }; + assign n4129 = 64'h007f7f7f7f7f7f7f >> { ndn3_19, nsr3_23, n_n7374, nsr3_35, ndn3_29, n_n7373 }; + assign n4130 = 16'ha820 >> { ndn3_12, nsr3_14, nsr3_13, n_n9141 }; + assign n4131_1 = 64'h007f7f7f7f7f7f7f >> { ndn3_26, nsr3_30, n_n7487, nsr3_37, nen3_34, n_n8499 }; + assign n4132 = 16'h0080 >> { n4135, n4134, n4133, n4136_1 }; + assign n4133 = 64'h007f7f7f7f7f7f7f >> { nen3_36, nsr3_38, n_n9308, nsr3_37, nen3_34, n_n9042 }; + assign n4134 = 64'h007f7f7f7f7f7f7f >> { ndn3_26, nsr3_30, n_n8742, nsr3_20, ndn3_17, n_n8744 }; + assign n4135 = 16'ha820 >> { ndn3_12, nsr3_14, nsr3_13, n_n9318 }; + assign n4136_1 = 64'h007f7f7f7f7f7f7f >> { ndn3_19, nsr3_23, n_n8743, nsr3_35, ndn3_29, n_n8741 }; + assign n4137 = 64'h7f00ff007f007f00 >> { n_n9015, n4121_1, n_n8652, n4140, n4139, n4138 }; + assign n4138 = 64'h007f7f7f7f7f7f7f >> { nsr3_20, ndn3_17, n_n8104, nsr3_35, ndn3_29, n_n8828 }; + assign n4139 = 64'h007f7f7f7f7f7f7f >> { nen3_36, n_n8862, nsr3_38, nsr3_30, ndn3_26, n_n7341 }; + assign n4140 = 64'h007f7f7f7f7f7f7f >> { ndn3_19, nsr3_23, n_n7342, nsr3_37, nen3_34, n_n7670 }; + assign n4141_1 = 64'h0008080800888888 >> { n3738, n3741_1, n_n9470, n_n8937, n4142, n4143 }; + assign n4142 = 16'h0777 >> { n_n8939, n3740, n3743, n_n8938 }; + assign n4143 = 64'h0777077700000777 >> { n4121_1, n_n9599, n3737, n_n9139, n3736_1, n_n9588 }; + assign n4144 = 64'h0008080800888888 >> { n3738, n3741_1, n_n7640, n_n7452, n4145, n4146_1 }; + assign n4145 = 64'h0777077700000777 >> { n4121_1, n_n7877, n_n9458, n3736_1, n3743, n_n7453 }; + assign n4146_1 = 16'h0777 >> { n3737, n_n7454, n3740, n_n8727 }; + assign n4147 = 64'h0008080800888888 >> { n3738, n3741_1, n_n9473, n_n8881, n4148, n4149 }; + assign n4148 = 64'h0777077700000777 >> { n4121_1, n_n9496, n3737, n_n8883, n3736_1, n_n9485 }; + assign n4149 = 16'h0777 >> { n_n8884, n3740, n3743, n_n8882 }; + assign n4150 = 64'h08aa00088aaa008a >> { n4118, n4144, n_n9416, n_n9434, n4147, n4141_1 }; + assign n4151_1 = 64'h0008080800888888 >> { n3737, n3741_1, n_n9518, n_n7588, n4152, n4153 }; + assign n4152 = 16'h0777 >> { n_n8753, n3740, n3743, n_n9286 }; + assign n4153 = 64'h0777077700000777 >> { n4121_1, n_n7951, n3738, n_n7474, n3736_1, n_n7947 }; + assign n4154 = 64'h0008080800888888 >> { n3743, n3738, n_n8201, n_n9615, n4155, n4156_1 }; + assign n4155 = 16'h0777 >> { n_n9110, n3741_1, n3737, n_n8202 }; + assign n4156_1 = 64'h0777077700000777 >> { n4121_1, n_n8203, n_n9516, n3736_1, n3740, n_n9019 }; + assign n4157 = 64'h0008080800888888 >> { n3743, n3736_1, n_n9467, n_n8545, n4158, n4159 }; + assign n4158 = 64'h0777077700000777 >> { n4121_1, n_n8153, n_n8628, n3741_1, n3737, n_n8151 }; + assign n4159 = 16'h0777 >> { n_n8177, n3738, n3740, n_n8152 }; + assign n4160 = 16'h8088 >> { n_n8984, n4121_1, n4161_1, n4162 }; + assign n4161_1 = 64'h0000077707770777 >> { n3741_1, n_n9334, n3737, n_n8982, n3736_1, n_n8980 }; + assign n4162 = 64'h0000077707770777 >> { n3738, n_n8981, n_n8983, n3740, n3743, n_n8998 }; + assign n4163 = 64'h08aa00088aaa008a >> { n4116_1, n4157, n_n9448, n_n9638, n4160, n4154 }; + assign n4164 = 16'h8088 >> { n_n8282, n4121_1, n4165, n4166_1 }; + assign n4165 = 64'h0000077707770777 >> { n3737, n_n8280, n3736_1, n_n8626, n3743, n_n8279 }; + assign n4166_1 = 64'h0000077707770777 >> { n3741_1, n_n8277, n_n8278, n3738, n3740, n_n8281 }; + assign n4167 = 64'h0008080800888888 >> { n3743, n3741_1, n_n8223, n_n9205, n4168, n4169 }; + assign n4168 = 16'h0777 >> { n_n8222, n3736_1, n3740, n_n8226 }; + assign n4169 = 64'h0777077700000777 >> { n4121_1, n_n8227, n_n8224, n3738, n3737, n_n8225 }; + assign n4170 = 64'h2a022a020a002a02 >> { n4163, n_n8354, n4167, n_n8419, n4115, n4164 }; + assign n4171_1 = 16'h8088 >> { n_n8516, n4121_1, n4172, n4173 }; + assign n4172 = 64'h0000077707770777 >> { n3737, n_n8514, n3736_1, n_n9108, n3743, n_n9203 }; + assign n4173 = 64'h0000077707770777 >> { n3741_1, n_n8512, n3738, n_n8513, n3740, n_n8515 }; + assign n4174 = 4'h2 >> { preset, n4175 }; + assign n4175 = 16'hbb1b >> { n_n7306, n_n9248, n4176_1, n_n9247 }; + assign n4176_1 = 4'h2 >> { n3731_1, n4177 }; + assign n4177 = 4'h2 >> { n4178, n_n9198 }; + assign n4178 = 16'h0008 >> { n3743, n3738, n4179, n4121_1 }; + assign n4179 = 16'h0001 >> { n3740, n3736_1, n3737, n3741_1 }; + assign n4180 = 64'h0008080800888888 >> { n3737, n3741_1, n_n8864, n_n8582, n4181_1, n4182 }; + assign n4181_1 = 16'h0777 >> { n_n8583, n3740, n3743, n_n8581 }; + assign n4182 = 64'h0777077700000777 >> { n4121_1, n_n8584, n_n8941, n3738, n3736_1, n_n8580 }; + assign n4183 = 16'h0008 >> { preset, n_n7306, n_n9248, n_n9247 }; + assign n601_1 = 32'd1426150400 >> { n4185, n_n7707, ndn3_37, nsr3_37, preset }; + assign n4185 = 4'h2 >> { n3731_1, n_n8354 }; + assign n606_1 = 16'h3120 >> { n_n7552, n4187, preset, n3851_1 }; + assign n4187 = 8'h69 >> { n4100, n3914, n3926_1 }; + assign n611_1 = 4'h1 >> { preset, nsr3_23 }; + assign n616_1 = 16'h3120 >> { n_n9548, n_n7384, preset, n3818 }; + assign n621_1 = 16'h3120 >> { n_n9467, n4191_1, preset, n3810 }; + assign n4191_1 = 64'h1eee1eee1eee111e >> { n4027, n4052, n4044, n4053, n4008, n4026_1 }; + assign n626_1 = 16'h3120 >> { n_n8002, psv18_15_15_, preset, n4079 }; + assign n631_1 = 8'h54 >> { n_n6950, n3819, preset }; + assign n636_1 = 8'ha8 >> { n_n8930, n4197, n4195 }; + assign n4195 = 4'h2 >> { preset, n4196_1 }; + assign n4196_1 = 8'ha2 >> { n4178, n3731_1, n_n9198 }; + assign n4197 = 4'h8 >> { n3732, n4177 }; + assign n641_1 = 8'h54 >> { n_n7244, n3835, preset }; + assign n646_1 = 32'd1426150400 >> { n4200, n_n7819, nsr3_35, ndn3_35, preset }; + assign n4200 = 4'h2 >> { n3731_1, n_n9512 }; + assign n651_1 = 16'hf888 >> { n4202, n_n8883, n4106_1, n4203 }; + assign n4202 = 8'h45 >> { nen3_19, ndn3_19, preset }; + assign n4203 = 8'h02 >> { preset, ndn3_19, nen3_19 }; + assign n656_1 = 16'h3120 >> { n_n7709, psv38_11_11_, preset, n4079 }; + assign n661_1 = 8'h54 >> { n_n9580, n3827, preset }; + assign n666_1 = 32'd1426150400 >> { n4207, n_n9130, nsr3_23, ndn3_23, preset }; + assign n4207 = 4'h2 >> { n3731_1, n_n9353 }; + assign n671_1 = 16'h3120 >> { n_n9486, n4106_1, preset, n3835 }; + assign n676_1 = 16'h3120 >> { n_n9235, n3803, preset, n3824 }; + assign n681_1 = 16'h3120 >> { n_n7522, n_n9102, preset, n3835 }; + assign n686_1 = 16'hf888 >> { n4212, n_n7373, n4187, n4213 }; + assign n4212 = 8'h45 >> { ndn3_28, ndn3_29, preset }; + assign n4213 = 8'h02 >> { preset, ndn3_29, ndn3_28 }; + assign n691_1 = 8'h54 >> { n_n9085, n3818, preset }; + assign n696_1 = 32'd3937290372 >> { n4174, n4116_1, n4160, n4183, n_n9638 }; + assign n701_1 = 32'd4286743170 >> { n4212, n_n7452, n4217, n3853, n4213 }; + assign n4217 = 4'h6 >> { n3804, n3831_1 }; + assign n706_1 = 16'h3120 >> { n_n8775, n4219, preset, n3808 }; + assign n4219 = 64'haa959555aaa9a955 >> { n4007, n4082, n4090, n4062, n4070, n4220 }; + assign n4220 = 4'h6 >> { n4221_1, n4229 }; + assign n4221_1 = 16'h8088 >> { n_n7889, n3817, n4222, n4226_1 }; + assign n4222 = 32'd8421504 >> { n_n8626, n3818, n4225, n4223, n4224 }; + assign n4223 = 64'h0000077707770777 >> { n_n8414, n3814, n_n9064, n3827, n3812, n_n9067 }; + assign n4224 = 64'h0000077707770777 >> { n_n8394, n3828, n3824, n_n9623, n3826_1, n_n8282 }; + assign n4225 = 64'h00000ddd0ddd0ddd >> { n3822, n_n7887, n3809, n_n9092, n3821_1, n_n9520 }; + assign n4226_1 = 64'h0088888800080808 >> { n3829, n3819, n_n7885, n_n8504, n4228, n4227 }; + assign n4227 = 64'h0000077707770777 >> { n_n7988, n3813, n_n7888, n3816_1, n3808, n_n7890 }; + assign n4228 = 64'h0000dd0ddd0ddd0d >> { n3810, n_n8333, n3830, n_n7886, n3823, n_n8758 }; + assign n4229 = 64'h8000000080008000 >> { n_n7849, n3840, n4236_1, n4237, n4230, n4233 }; + assign n4230 = 64'h2222002202020002 >> { n3845, n3847, n_n7850, n_n9225, n4231_1, n4232 }; + assign n4231_1 = 4'h2 >> { n3852, n_n7888 }; + assign n4232 = 64'h0000077707770777 >> { n_n8480, n3835, n_n7889, n3826_1, n3838, n_n8909 }; + assign n4233 = 64'h0202000222220022 >> { n3836_1, n3846_1, n_n7887, n_n7845, n4234, n4235 }; + assign n4234 = 4'h8 >> { n3851_1, n_n9520 }; + assign n4235 = 64'h0000077707770777 >> { n_n8470, n3818, n_n7846, n3843, n3798, n_n7844 }; + assign n4236_1 = 64'h0000077707770777 >> { n3816_1, n_n7847, n3837, n_n7848, n3850, n_n9098 }; + assign n4237 = 16'h7707 >> { n3839, n_n8775, n3824, n_n8277 }; + assign n711_1 = 16'h3120 >> { n_n7654, n4102, preset, n3838 }; + assign n716_1 = 16'h3120 >> { n_n8410, n4240, preset, n3809 }; + assign n4240 = 64'haaa9a955aa959555 >> { n3804, n3989, n3997, n3831_1, n3853, n4028 }; + assign n721_1 = 16'h3120 >> { n_n8208, n4242, preset, n3826_1 }; + assign n4242 = 64'h6999699969996669 >> { n4243, n4244, n4245, n4261_1, n4253, n4269 }; + assign n4243 = 64'h002a2aaa000202aa >> { n4007, n4082, n4090, n4062, n4070, n4220 }; + assign n4244 = 4'h1 >> { n4221_1, n4229 }; + assign n4245 = 32'd2147516544 >> { n_n9568, n3839, n4252, n4246_1, n4249 }; + assign n4246_1 = 32'd707395626 >> { n3845, n_n8139, n3836_1, n_n7910, n4247 }; + assign n4247 = 32'd2763306 >> { n3851_1, n_n7932, n3835, n_n7908, n4248 }; + assign n4248 = 16'h0777 >> { n3838, n_n8535, n3837, n_n7913 }; + assign n4249 = 64'h8888008808080008 >> { n3840, n3846_1, n_n7931, n_n8772, n4251_1, n4250 }; + assign n4250 = 64'h0000077707770777 >> { n3824, n_n8512, n_n7912, n3816_1, n3843, n_n7911 }; + assign n4251_1 = 64'h0777077700000777 >> { n3847, n_n8000, n_n7914, n3850, n3798, n_n7909 }; + assign n4252 = 64'h0777077700000777 >> { n3852, n_n7933, n3818, n_n9632, n3826_1, n_n8106 }; + assign n4253 = 64'h8888008808080008 >> { n3840, n3845, n_n9223, n_n8014, n4258, n4254 }; + assign n4254 = 32'd707395626 >> { n3839, n_n7971, n3850, n_n8456, n4255 }; + assign n4255 = 64'h0008080800888888 >> { n3837, n3824, n_n8864, n_n7970, n4256_1, n4257 }; + assign n4256_1 = 16'h0777 >> { n_n8004, n3851_1, n3835, n_n7966 }; + assign n4257 = 64'h0000077707770777 >> { n3826_1, n_n8519, n3838, n_n7969, n3843, n_n7968 }; + assign n4258 = 16'h0888 >> { n_n9077, n3836_1, n4259, n4260 }; + assign n4259 = 64'h0777077700000777 >> { n3852, n_n8005, n3818, n_n8468, n3816_1, n_n8208 }; + assign n4260 = 64'h7707770700007707 >> { n3847, n_n8482, n3846_1, n_n8003, n3798, n_n7967 }; + assign n4261_1 = 64'h8000000080008000 >> { n_n7935, n3823, n4267, n4268, n4262, n4265 }; + assign n4262 = 64'h0008080800888888 >> { n3809, n3827, n_n8219, n_n7929, n4264, n4263 }; + assign n4263 = 64'hdd0ddd0d0000dd0d >> { n3817, n_n8106, n3830, n_n7930, n3829, n_n7936 }; + assign n4264 = 64'h0777077700000777 >> { n3821_1, n_n7932, n3824, n_n7927, n3812, n_n7946 }; + assign n4265 = 32'd2763306 >> { n3814, n_n8114, n3819, n_n8445, n4266_1 }; + assign n4266_1 = 64'h0000077707770777 >> { n3810, n_n8425, n3818, n_n9108, n3826_1, n_n8516 }; + assign n4267 = 64'h0000077707770777 >> { n_n7934, n3828, n_n7931, n3822, n3808, n_n7937 }; + assign n4268 = 16'h0777 >> { n3813, n_n7928, n3816_1, n_n7933 }; + assign n4269 = 64'h8000000080008000 >> { n_n8002, n3830, n4275, n4276_1, n4270, n4272 }; + assign n4270 = 32'd9079434 >> { n_n8839, n3810, n_n8491, n3829, n4271_1 }; + assign n4271_1 = 16'h0777 >> { n_n8580, n3818, n3827, n_n8064 }; + assign n4272 = 64'h0008080800888888 >> { n3812, n3813, n_n8078, n_n8192, n4273, n4274 }; + assign n4273 = 64'h0777077700000777 >> { n3817, n_n8519, n3816_1, n_n8005, n3826_1, n_n8584 }; + assign n4274 = 64'h0000077707770777 >> { n_n8003, n3822, n3819, n_n8001, n3808, n_n8007 }; + assign n4275 = 64'h0000dd0ddd0ddd0d >> { n3809, n_n8900, n3821_1, n_n8004, n3823, n_n8006 }; + assign n4276_1 = 64'h0000077707770777 >> { n_n8502, n3814, n_n8344, n3828, n3824, n_n9355 }; + assign n726_1 = 32'd823336962 >> { n_n8377, n3853, n4217, preset, n3850 }; + assign n731_1 = 16'h3120 >> { n_n7558, n4099, preset, n3818 }; + assign n736_1 = 32'd1426150400 >> { n4200, n_n7599, ndn3_37, nsr3_37, preset }; + assign n741_1 = 16'hf888 >> { n4202, n_n8225, n4081_1, n4203 }; + assign n746_1 = 32'd4280821800 >> { n4202, n_n8202, n4007, n4061_1, n4203 }; + assign n751_1 = 16'h3120 >> { n_n7670, n4102, preset, n3836_1 }; + assign n756_1 = 16'h3120 >> { n_n7888, n4219, preset, n3838 }; + assign n761_1 = 16'h3120 >> { n_n7889, n4219, preset, n3828 }; + assign n766_1 = 16'h3120 >> { n_n8597, n4191_1, preset, n3826_1 }; + assign n771_1 = 16'h3120 >> { n_n8152, n4191_1, preset, n4287 }; + assign n4287 = 4'h2 >> { ndn3_17, ndn3_16 }; + assign n1026 = 4'h1 >> { preset, nsr3_13 }; + assign n776_1 = 32'd1426150400 >> { n4290, n_n8394, nsr3_13, ndn3_13, preset }; + assign n4290 = 4'h2 >> { n3731_1, n_n8449 }; + assign n781_1 = 32'd1426150400 >> { n4292, n_n7812, nsr3_13, ndn3_13, preset }; + assign n4292 = 4'h2 >> { n3731_1, n_n8419 }; + assign n786_1 = 16'h3120 >> { n_n7816, psv39_12_12_, preset, n4079 }; + assign n791_1 = 16'h3120 >> { n_n9141, n4187, preset, n3837 }; + assign n796_1 = 16'h3120 >> { n_n7332, n_n8991, preset, n3798 }; + assign n801_1 = 16'h3120 >> { n_n8758, n4219, preset, n3850 }; + assign n806_1 = 16'h3120 >> { n_n7765, psv26_11_11_, preset, n4079 }; + assign n811_1 = 32'd823336962 >> { n_n7877, n3853, n4217, preset, n3837 }; + assign n816_1 = 16'h3120 >> { n_n7814, psv26_12_12_, preset, n4079 }; + assign n821_1 = 16'h3120 >> { n_n9008, n4301_1, preset, n3814 }; + assign n4301_1 = 16'h9996 >> { n3886_1, n3988, n3870, n3878 }; + assign n826_1 = 16'h3120 >> { n_n7581, n_n9351, preset, n3827 }; + assign n831_1 = 16'h3120 >> { n_n7376, n4187, preset, n3813 }; + assign n836 = 16'h3120 >> { n_n7970, n4242, preset, n3812 }; + assign n493 = 8'h01 >> { preset, nsr1_2, pdn }; + assign n497 = 32'd1145373701 >> { ndn1_4, nsr1_2, pdn, pover_0_0_, preset }; + assign n841 = 16'h3120 >> { n_n8599, n4240, preset, n3826_1 }; + assign n846 = 16'h3120 >> { n_n8227, n4081_1, preset, n3837 }; + assign n851 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9442, preset }; + assign n856 = 16'h3120 >> { n_n9485, n4106_1, preset, n3810 }; + assign n861 = 16'h3120 >> { n_n7148, n_n9623, preset, n3819 }; + assign n866 = 32'd1426150400 >> { n4313, n_n9311, nsr3_35, ndn3_35, preset }; + assign n4313 = 4'h2 >> { n3731_1, n_n9284 }; + assign n871 = 32'd823336962 >> { n_n9273, n3853, n4217, preset, n3816_1 }; + assign n876 = 16'h1110 >> { ndn3_7, ndn3_9, preset, ngfdn_3 }; + assign n881 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8613, preset }; + assign n886 = 32'd1426150400 >> { n4318, n_n8533, nsr3_23, ndn3_23, preset }; + assign n4318 = 4'h2 >> { n3731_1, n_n8707 }; + assign n891 = 32'd1426150400 >> { n4200, n_n8699, nsr3_20, ndn3_20, preset }; + assign n896 = 32'd823336962 >> { n_n8609, n3853, n4217, preset, n3835 }; + assign n901 = 16'h3120 >> { n_n8308, n4240, preset, n3824 }; + assign n906 = 8'h54 >> { n_n8655, n3824, preset }; + assign n911 = 64'hffff222822282228 >> { n4212, n_n8981, n4027, n4052, n4324, n4213 }; + assign n4324 = 4'h6 >> { n4044, n4053 }; + assign n916 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7583, preset }; + assign n921 = 8'hfd >> { n4327, preset, n4176_1 }; + assign n4327 = 4'h2 >> { n4328, n_n9248 }; + assign n4328 = 32'd2147483648 >> { n4329, n4334, n4335, n4336_1, n4337 }; + assign n4329 = 64'h5555555555555559 >> { n_n8993, n_n9031, n_n9034, n_n8978, n4330, n_n8561 }; + assign n4330 = 4'h2 >> { n_n8911, n4331_1 }; + assign n4331_1 = 4'h2 >> { n_n8933, n4332 }; + assign n4332 = 4'h2 >> { n_n8869, n4333 }; + assign n4333 = 8'h02 >> { n_n8923, n_n8798, n_n8603 }; + assign n4334 = 32'd1431655769 >> { n_n8993, n_n9031, n_n8978, n4330, n_n9034 }; + assign n4335 = 16'h5559 >> { n_n8993, n_n8978, n4330, n_n9031 }; + assign n4336_1 = 8'h59 >> { n_n8978, n4330, n_n8993 }; + assign n4337 = 64'h0000000000000080 >> { n_n8923, n_n8603, n_n8798, n4338, n4339, n4340 }; + assign n4338 = 4'h1 >> { n_n8631, n_n8847 }; + assign n4339 = 16'h0001 >> { n_n8933, n_n8911, n_n8978, n_n8869 }; + assign n4340 = 64'h0000000000000008 >> { n_n7306, n_n8913, n_n8964, n_n9011, n_n9247, n_n9248 }; + assign n926 = 16'h3120 >> { n_n9602, n3803, preset, n3850 }; + assign n931 = 64'h1313133102020220 >> { n_n8786, n4027, n4052, n4324, preset, n3850 }; + assign n936 = 16'h3120 >> { n_n9598, n3803, preset, n3838 }; + assign n941 = 16'h3120 >> { n_n7738, n4187, preset, n3843 }; + assign n946 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8573, preset }; + assign n951 = 16'h3120 >> { n_n9473, n4106_1, preset, n3836_1 }; + assign n956 = 32'd823336962 >> { n_n9000, n3853, n4217, preset, n3843 }; + assign n961 = 32'd1426150400 >> { n4349, n_n8001, nsr3_38, ndn3_38, preset }; + assign n4349 = 4'h2 >> { n3731_1, n_n8557 }; + assign n966 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9554, preset }; + assign n971 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8508, preset }; + assign n976 = 16'h3120 >> { n_n9635, n4081_1, preset, n3819 }; + assign n981 = 16'h3120 >> { n_n7190, n_n8249, preset, n3819 }; + assign n986 = 16'h3120 >> { n_n8702, n_n8213, preset, n3827 }; + assign n991 = 16'h3120 >> { n_n9106, n4356_1, preset, n3813 }; + assign n4356_1 = 8'h96 >> { n3935, n3949, n3962 }; + assign n996 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7409, preset }; + assign n1001 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9437, preset }; + assign n1006 = 16'h3120 >> { n_n9052, n4356_1, preset, n3808 }; + assign n1011 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8647, preset }; + assign n1016 = 16'h3120 >> { n_n9265, n3803, preset, n3826_1 }; + assign n1021 = 16'h3120 >> { n_n7179, n_n7783, preset, n3818 }; + assign n1031 = 16'h1110 >> { ndn3_16, ndn3_17, preset, ngfdn_3 }; + assign n1036 = 16'h1110 >> { ndn3_25, ndn3_22, preset, ngfdn_3 }; + assign n1041 = 16'h1110 >> { ndn3_28, ndn3_29, preset, ngfdn_3 }; + assign n1046 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9539, preset }; + assign n1051 = 32'd1426150400 >> { n4368, n_n7953, nsr3_13, ndn3_13, preset }; + assign n4368 = 4'h2 >> { n3731_1, n_n8821 }; + assign n1056 = 16'h3120 >> { n_n8488, n_n9412, preset, n3827 }; + assign n1061 = 16'h1101 >> { nen3_22, nsr3_23, preset, ngfdn_3 }; + assign n1066 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9438, preset }; + assign n1071 = 16'h3120 >> { n_n8132, n_n8150, preset, n3835 }; + assign n1076 = 32'd1426150400 >> { n4374, n_n8661, nsr3_14, ndn3_14, preset }; + assign n4374 = 4'h2 >> { n3731_1, n_n9416 }; + assign n1081 = 16'h3120 >> { n_n7759, psv18_11_11_, preset, n4079 }; + assign n1086 = 16'h3120 >> { n_n8333, n4219, preset, n3822 }; + assign n1091 = 32'd1426150400 >> { n4207, n_n9399, nsr3_20, ndn3_20, preset }; + assign n1096 = 8'h54 >> { n_n7798, n3827, preset }; + assign n1101 = 32'd3937290372 >> { n4174, n4118, n4147, n4183, n_n9434 }; + assign n1106 = 64'h1313133102020220 >> { n_n7910, n4243, n4244, n4381_1, preset, n3851_1 }; + assign n4381_1 = 4'h6 >> { n4245, n4261_1 }; + assign n1111 = 16'h3120 >> { n_n9528, n4187, preset, n3828 }; + assign n1116 = 16'h3120 >> { n_n7850, pinp_13_13_, preset, n4079 }; + assign n1121 = 8'h54 >> { n_n8251, n3818, preset }; + assign n1126 = 16'h3120 >> { n_n7937, psv2_14_14_, preset, n4079 }; + assign n1131 = 16'h3120 >> { n_n8482, pinp_15_15_, preset, n4079 }; + assign n1136 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9290, preset }; + assign n1141 = 16'h3120 >> { n_n8007, psv2_15_15_, preset, n4079 }; + assign n1146 = 8'h54 >> { n_n7556, n3824, preset }; + assign n1151 = 32'd1426150400 >> { n4290, n_n9064, nsr3_20, ndn3_20, preset }; + assign n1156 = 16'h3120 >> { n_n9398, n4099, preset, n3827 }; + assign n1161 = 16'h3120 >> { n_n9412, n4081_1, preset, n3816_1 }; + assign n1166 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9361, preset }; + assign n1171 = 32'd321978912 >> { n_n9304, n4007, n4061_1, preset, n3816_1 }; + assign n1866 = 4'h1 >> { preset, nsr3_30 }; + assign n1176 = 32'd1426150400 >> { n4397, n_n7651, nsr3_30, ndn3_30, preset }; + assign n4397 = 4'h2 >> { n3731_1, n_n8652 }; + assign n1181 = 32'd321978912 >> { n_n7712, n4007, n4061_1, preset, n3826_1 }; + assign n1186 = 32'd1426150400 >> { n4318, n_n7735, nsr3_30, ndn3_30, preset }; + assign n1191 = 32'd1426150400 >> { n4401_1, n_n7934, nsr3_13, ndn3_13, preset }; + assign n4401_1 = 4'h2 >> { n3731_1, n_n8549 }; + assign n1196 = 16'h3120 >> { n_n7811, n4081_1, preset, n3828 }; + assign n1201 = 16'h3120 >> { n_n8053, psv13_2_2_, preset, n4079 }; + assign n1206 = 16'h3120 >> { n_n9015, n4102, preset, n3837 }; + assign n1211 = 32'd1426150400 >> { n4185, n_n8066, nsr3_14, ndn3_14, preset }; + assign n1216 = 16'h3120 >> { n_n9518, n4240, preset, n3836_1 }; + assign n1221 = 32'd1426346240 >> { n_n8466, n_n8091, ndn3_50, ngfdn_3, preset }; + assign n1226 = 32'd1426150400 >> { n4409, n_n9257, nsr3_13, ndn3_13, preset }; + assign n4409 = 4'h2 >> { n3731_1, n_n9448 }; + assign n1231 = 16'h3120 >> { n_n8175, n_n9252, preset, n3827 }; + assign n1236 = 16'h3120 >> { n_n8491, psv39_15_15_, preset, n4079 }; + assign n1241 = 16'h3120 >> { n_n8114, psv13_14_14_, preset, n4079 }; + assign n1246 = 16'h3120 >> { n_n7951, n4240, preset, n3837 }; + assign n1251 = 64'hea48ea48ffffea48 >> { n3785, n4416_1, n4415, n4417, n4183, n_n8913 }; + assign n4415 = 32'd1409307905 >> { n3731_1, n4175, n4196_1, n_n8668, preset }; + assign n4416_1 = 64'h0000022200100232 >> { n_n9247, n_n8668, n4178, n_n9198, preset, n3731_1 }; + assign n4417 = 4'h8 >> { n4418, n4338 }; + assign n4418 = 64'h0000000000000002 >> { n_n8993, n_n9031, n_n9034, n_n8978, n_n8561, n4330 }; + assign n1256 = 16'h3120 >> { n_n8035, n4187, preset, n3826_1 }; + assign n1261 = 64'hea48ea48ffffea48 >> { n3764, n4416_1, n4415, n4418, n4183, n_n8631 }; + assign n1266 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n8243, preset }; + assign n1271 = 16'h3120 >> { n_n7857, n_n7706, preset, n3824 }; + assign n1281 = 16'h3120 >> { n_n7791, n4081_1, preset, n3812 }; + assign n1286 = 16'h3120 >> { n_n9175, n4106_1, preset, n3851_1 }; + assign n1291 = 16'h3120 >> { n_n9588, n3803, preset, n3810 }; + assign n1296 = 32'd1426150400 >> { n4313, n_n9049, nsr3_14, ndn3_14, preset }; + assign n1301 = 32'd1426346240 >> { n_n8948, n_n9483, ndn3_50, ngfdn_3, preset }; + assign n1306 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9410, preset }; + assign n1311 = 16'h3120 >> { n_n7691, n4240, preset, n3819 }; + assign n1316 = 32'd1426150400 >> { n4318, n_n7740, nsr3_20, ndn3_20, preset }; + assign n1321 = 32'd1426150400 >> { n4200, n_n7602, nsr3_23, ndn3_23, preset }; + assign n1326 = 32'd823336962 >> { n_n7783, n3853, n4217, preset, n3824 }; + assign n1331 = 16'h3120 >> { n_n7948, n4240, preset, n3835 }; + assign n1336 = 16'h3120 >> { n_n7054, n_n9576, preset, n3835 }; + assign n1341 = 64'h1313133102020220 >> { n_n9343, n4027, n4052, n4324, preset, n3828 }; + assign n1346 = 16'h3120 >> { n_n9400, n4099, preset, n3838 }; + assign n1351 = 64'heefeeefeeeeeeefe >> { nlc1_2, preset_0_0_, ngfdn_3, nsr1_2, preset, pdn }; + assign n1356 = 32'd1426150400 >> { n4207, n_n9127, ndn3_37, nsr3_37, preset }; + assign n1361 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8531, preset }; + assign n1366 = 32'd1426150400 >> { n4441_1, n_n9335, ndn3_37, nsr3_37, preset }; + assign n4441_1 = 4'h2 >> { n3731_1, n_n9638 }; + assign n1371 = 16'h3120 >> { n_n7324, n4219, preset, n3818 }; + assign n1376 = 16'h3120 >> { n_n9611, n4242, preset, n3813 }; + assign n1381 = 8'h54 >> { n_n8112, n3827, preset }; + assign n1386 = 16'h3120 >> { n_n9406, psv13_3_3_, preset, n4079 }; + assign n1391 = 16'h3120 >> { n_n9618, n4240, preset, n3843 }; + assign n1396 = 16'h3120 >> { n_n9613, n4219, preset, n3813 }; + assign n1401 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9242, preset }; + assign n1406 = 32'd321978912 >> { n_n7384, n4007, n4061_1, preset, n3824 }; + assign n1411 = 16'h3120 >> { n_n8884, n4106_1, preset, n4287 }; + assign n1416 = 32'd1426346240 >> { n_n9219, n_n7462, ndn3_50, ngfdn_3, preset }; + assign n1421 = 32'd1426150400 >> { n4401_1, n_n7908, ndn3_37, nsr3_37, preset }; + assign n1426 = 16'h3120 >> { n_n8765, n4191_1, preset, n3824 }; + assign n1431 = 64'h1313133102020220 >> { n_n7909, n4243, n4244, n4381_1, preset, n3809 }; + assign n1436 = 16'h3120 >> { n_n7898, n4191_1, preset, n3819 }; + assign n1441 = 16'h3120 >> { n_n9135, n4099, preset, n3808 }; + assign n1446 = 16'h3120 >> { n_n8862, n4102, preset, n3810 }; + assign n1451 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8037, preset }; + assign n1456 = 16'h1110 >> { ndn3_18, ndn3_17, preset, ngfdn_3 }; + assign n1461 = 16'h1110 >> { ndn3_22, nen3_22, preset, ngfdn_3 }; + assign n1466 = 8'h54 >> { n_n8974, n3819, preset }; + assign n1471 = 8'h54 >> { n_n7286, n3835, preset }; + assign n1476 = 16'h3120 >> { n_n9223, psv38_15_15_, preset, n4079 }; + assign n1481 = 4'h2 >> { preset, n4328 }; + assign n1486 = 16'h3120 >> { n_n9169, n_n6974, preset, n3835 }; + assign n1491 = 16'h3120 >> { n_n9125, n4099, preset, n3819 }; + assign n1496 = 16'h1101 >> { nen3_39, nsr3_38, preset, ngfdn_3 }; + assign n1501 = 16'hf888 >> { n4212, n_n8278, n4219, n4213 }; + assign n1506 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9557, preset }; + assign n1511 = 32'd1426150400 >> { n4185, n_n7758, nsr3_30, ndn3_30, preset }; + assign n1516 = 16'h3120 >> { n_n9391, n4099, preset, n3835 }; + assign n1521 = 16'h3120 >> { n_n8110, pinp_10_10_, preset, n4079 }; + assign n1526 = 32'd1426150400 >> { n3796_1, n_n9597, nsr3_20, ndn3_20, preset }; + assign n1531 = 8'h54 >> { n_n8568, n3818, preset }; + assign n1536 = 16'hf888 >> { n4212, n_n7428, n4301_1, n4213 }; + assign n1541 = 64'h1313133102020220 >> { n_n7931, n4243, n4244, n4381_1, preset, n3843 }; + assign n1546 = 16'h3120 >> { n_n7742, n4187, preset, n3850 }; + assign n1551 = 16'h3120 >> { n_n7236, n4242, preset, n3816_1 }; + assign n1556 = 32'd1426150400 >> { n4401_1, n_n8219, nsr3_20, ndn3_20, preset }; + assign n1561 = 64'h1313133102020220 >> { n_n9568, n4243, n4244, n4381_1, preset, n3808 }; + assign n1566 = 8'h54 >> { n_n9200, n3827, preset }; + assign n1571 = 16'hf888 >> { n4103, n_n8545, n4191_1, n4104 }; + assign n1576 = 16'h3120 >> { n_n7823, n4301_1, preset, n3838 }; + assign n1581 = 16'h3120 >> { n_n8005, n4242, preset, n3838 }; + assign n1586 = 16'h3120 >> { n_n8736, pinp_4_4_, preset, n4079 }; + assign n1591 = 64'h1313133102020220 >> { n_n9339, n4027, n4052, n4324, preset, n3827 }; + assign n1596 = 16'h3120 >> { n_n8499, n4187, preset, n3836_1 }; + assign n1601 = 16'h3120 >> { n_n8086, psv33_11_11_, preset, n4079 }; + assign n1606 = 16'h3120 >> { n_n7803, n4191_1, preset, n3850 }; + assign n1611 = 32'd823336962 >> { n_n7640, n3853, n4217, preset, n3836_1 }; + assign n1616 = 16'h3120 >> { n_n9098, psv33_13_13_, preset, n4079 }; + assign n1621 = 16'h3120 >> { n_n7160, n_n8906, preset, n3798 }; + assign n1626 = 32'd321978912 >> { n_n7713, n4007, n4061_1, preset, n3814 }; + assign n1631 = 16'h3120 >> { n_n9566, n4102, preset, n3814 }; + assign n1636 = 16'h3120 >> { n_n7955, psv13_8_8_, preset, n4079 }; + assign n1641 = 16'h3120 >> { n_n8414, psv13_13_13_, preset, n4079 }; + assign n1646 = 16'h3120 >> { n_n8006, n4242, preset, n3850 }; + assign n1651 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9560, preset }; + assign n1656 = 16'hf888 >> { n4103, n_n8742, n4356_1, n4104 }; + assign n1661 = 16'h3120 >> { n_n7174, n_n9632, preset, n3824 }; + assign n1666 = 16'hf888 >> { n4103, n_n8882, n4106_1, n4104 }; + assign n1671 = 16'h3120 >> { n_n7546, n_n9235, preset, n3818 }; + assign n1676 = 16'h3120 >> { n_n8282, n4219, preset, n3837 }; + assign n1681 = 64'hffff222822282228 >> { n4103, n_n8998, n4027, n4052, n4324, n4104 }; + assign n1686 = 16'h3120 >> { n_n7656, psv26_0_0_, preset, n4079 }; + assign n1691 = 16'h3120 >> { n_n9465, n_n8022, preset, n3819 }; + assign n1696 = 32'd1426150400 >> { n3796_1, n_n9601, nsr3_13, ndn3_13, preset }; + assign n1701 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8875, preset }; + assign n1706 = 16'h3120 >> { n_n7954, psv26_8_8_, preset, n4079 }; + assign n1711 = 32'd823336962 >> { n_n8959, n3853, n4217, preset, n3798 }; + assign n1716 = 16'h3120 >> { n_n8957, n4240, preset, n3798 }; + assign n1721 = 16'h3120 >> { n_n8247, n4187, preset, n3835 }; + assign n1726 = 16'h3120 >> { n_n8258, n4301_1, preset, n3824 }; + assign n1731 = 32'd1426150400 >> { n4374, n_n7641, nsr3_23, ndn3_23, preset }; + assign n1736 = 32'd1426150400 >> { n4368, n_n8843, nsr3_20, ndn3_20, preset }; + assign n1741 = 16'h3120 >> { n_n9321, n4356_1, preset, n3850 }; + assign n1746 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7702, preset }; + assign n1751 = 32'd4009688830 >> { ndn3_19, nak3_13, nsr3_23, pdn, preset }; + assign n1756 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8199, preset }; + assign n1761 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7983, preset }; + assign n1766 = 64'h1313133102020220 >> { n_n7217, n4243, n4244, n4381_1, preset, n3818 }; + assign n1771 = 16'h3120 >> { n_n7821, n4301_1, preset, n3843 }; + assign n1776 = 32'd1426150400 >> { n3730, n_n9489, nsr3_30, ndn3_30, preset }; + assign n1781 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8348, preset }; + assign n1786 = 16'h3120 >> { n_n9408, psv2_3_3_, preset, n4079 }; + assign n1791 = 32'd1426150400 >> { n4401_1, n_n8445, nsr3_38, ndn3_38, preset }; + assign n1796 = 16'h3120 >> { n_n9501, psv13_5_5_, preset, n4079 }; + assign n1801 = 32'd1426150400 >> { n4441_1, n_n7831, nsr3_30, ndn3_30, preset }; + assign n1806 = 32'd321978912 >> { n_n7757, n4007, n4061_1, preset, n3835 }; + assign n1811 = 16'h3120 >> { n_n9174, psv38_5_5_, preset, n4079 }; + assign n1816 = 16'h3120 >> { n_n9432, n_n9036, preset, n3819 }; + assign n1821 = 16'h3120 >> { n_n8678, n_n7948, preset, n3819 }; + assign n1826 = 16'h3120 >> { n_n8024, n4191_1, preset, n3835 }; + assign n1831 = 32'd1426150400 >> { n4292, n_n7806, nsr3_38, ndn3_38, preset }; + assign n1836 = 16'h3120 >> { n_n8996, n4191_1, preset, n3798 }; + assign n1841 = 32'd1426150400 >> { n4185, n_n7918, nsr3_38, ndn3_38, preset }; + assign n1846 = 32'd1426150400 >> { n4397, n_n8260, nsr3_13, ndn3_13, preset }; + assign n1851 = 64'h1313133102020220 >> { n_n9341, n4027, n4052, n4324, preset, n3826_1 }; + assign n1856 = 32'd1426150400 >> { n4318, n_n9189, nsr3_13, ndn3_13, preset }; + assign n1861 = 16'h3120 >> { n_n9096, n_n8258, preset, n3818 }; + assign n1871 = 16'h3120 >> { n_n7775, n_n7083, preset, n3818 }; + assign n1876 = 16'h3120 >> { n_n7693, n4240, preset, n3851_1 }; + assign n1881 = 16'h1101 >> { nen3_16, nsr3_14, preset, ngfdn_3 }; + assign n1886 = 16'h3120 >> { n_n7643, psv33_6_6_, preset, n4079 }; + assign n1891 = 16'hf888 >> { n4212, n_n8941, n4242, n4213 }; + assign n1896 = 32'd1426150400 >> { n4200, n_n8042, nsr3_14, ndn3_14, preset }; + assign n1901 = 16'h3120 >> { n_n8681, n_n8996, preset, n3835 }; + assign n1906 = 32'd1426150400 >> { n4368, n_n8659, nsr3_14, ndn3_14, preset }; + assign n1911 = 32'd321978912 >> { n_n9110, n4007, n4061_1, preset, n3836_1 }; + assign n1916 = 16'h3120 >> { n_n9573, n4099, preset, n3824 }; + assign n1921 = 16'h3120 >> { n_n8951, n4106_1, preset, n3824 }; + assign n1926 = 16'h3120 >> { n_n9589, n3803, preset, n3835 }; + assign n1931 = 16'h3120 >> { n_n9387, psv2_11_11_, preset, n4079 }; + assign n1936 = 16'hf888 >> { n4103, n_n8279, n4219, n4104 }; + assign n1941 = 16'h3120 >> { n_n7790, n4081_1, preset, n3851_1 }; + assign n1946 = 8'h54 >> { n_n8406, n3818, preset }; + assign n1951 = 16'hf888 >> { n4202, n_n8582, n4242, n4203 }; + assign n1956 = 32'd1426150400 >> { n4401_1, n_n7911, nsr3_23, ndn3_23, preset }; + assign n1961 = 16'hf888 >> { n4212, n_n7474, n4240, n4213 }; + assign n1966 = 16'h3120 >> { n_n8466, n4356_1, preset, n3818 }; + assign n1971 = 8'h54 >> { n_n6984, n3824, preset }; + assign n1976 = 32'd321978912 >> { n_n7760, n4007, n4061_1, preset, n3827 }; + assign n1981 = 16'h3120 >> { n_n7847, n4219, preset, n3826_1 }; + assign n1986 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9559, preset }; + assign n1991 = 8'h54 >> { n_n7362, n3827, preset }; + assign n1996 = 16'h3120 >> { n_n9300, psv33_10_10_, preset, n4079 }; + assign n2001 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9550, preset }; + assign n2006 = 16'h3120 >> { n_n9492, n4106_1, preset, n3843 }; + assign n2011 = 16'h3120 >> { n_n8777, n_n8858, preset, n3798 }; + assign n2016 = 32'd321978912 >> { n_n7764, n4007, n4061_1, preset, n3850 }; + assign n2021 = 16'h3120 >> { n_n7826, psv13_4_4_, preset, n4079 }; + assign n2026 = 16'h3120 >> { n_n7777, n_n9100, preset, n3827 }; + assign n2031 = 16'h3120 >> { n_n7824, n4301_1, preset, n3837 }; + assign n2036 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8173, preset }; + assign n2041 = 16'h3120 >> { n_n7498, n_n9391, preset, n3819 }; + assign n2046 = 32'd1426346240 >> { n_n7606, n_n9148, ndn3_50, ngfdn_3, preset }; + assign n2051 = 16'h3120 >> { n_n8753, n4240, preset, n4287 }; + assign n2056 = 64'h1313133102020220 >> { n_n8772, n4243, n4244, n4381_1, preset, n3814 }; + assign n2061 = 16'h3120 >> { n_n8049, n_n9589, preset, n3819 }; + assign n2066 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9362, preset }; + assign n2071 = 8'h02 >> { preset, pdn, ndn1_4 }; + assign n2076 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9561, preset }; + assign n2081 = 16'h3120 >> { n_n9004, n_n8951, preset, n3818 }; + assign n2086 = 32'd321978912 >> { n_n8203, n4007, n4061_1, preset, n3837 }; + assign n2091 = 16'h3120 >> { n_n8153, n4191_1, preset, n3837 }; + assign n2096 = 16'h3120 >> { n_n9263, n3803, preset, n3851_1 }; + assign n2101 = 32'd1426346240 >> { n_n9508, n_n8369, ndn3_50, ngfdn_3, preset }; + assign n2106 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9331, preset }; + assign n2111 = 32'd4286743170 >> { n4202, n_n7454, n4217, n3853, n4203 }; + assign n2116 = 16'h1110 >> { ndn3_4, ndn3_7, preset, ngfdn_3 }; + assign n2121 = 16'h3120 >> { n_n7527, n4187, preset, n3824 }; + assign n2126 = 16'h3120 >> { n_n9036, n4301_1, preset, n3835 }; + assign n2131 = 32'd1426150400 >> { n4374, n_n7875, nsr3_20, ndn3_20, preset }; + assign n2136 = 32'd1426150400 >> { n4368, n_n8697, nsr3_23, ndn3_23, preset }; + assign n2141 = 16'h3120 >> { n_n9497, n4106_1, preset, n3828 }; + assign n2146 = 8'h54 >> { n_n7291, n3835, preset }; + assign n2151 = 32'd4009688830 >> { ndn3_12, nak3_13, nsr3_13, pdn, preset }; + assign n2156 = 32'd4009688830 >> { nen3_36, nak3_13, nsr3_38, pdn, preset }; + assign n2161 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8240, preset }; + assign n2166 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7703, preset }; + assign n2171 = 16'h3120 >> { n_n9282, n4240, preset, n3818 }; + assign n2176 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8237, preset }; + assign n2181 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8935, preset }; + assign n2186 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9244, preset }; + assign n2191 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8648, preset }; + assign n2196 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8235, preset }; + assign n2201 = 64'h1313133102020220 >> { n_n8611, n4243, n4244, n4381_1, preset, n3813 }; + assign n2206 = 16'h3120 >> { n_n9045, psv38_1_1_, preset, n4079 }; + assign n2211 = 64'h1313133102020220 >> { n_n9334, n4027, n4052, n4324, preset, n3836_1 }; + assign n2216 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8572, preset }; + assign n2221 = 16'h3120 >> { n_n9491, psv18_5_5_, preset, n4079 }; + assign n2226 = 16'h3120 >> { n_n9134, n4099, preset, n3814 }; + assign n2231 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9555, preset }; + assign n2236 = 16'h3120 >> { n_n9336, psv38_9_9_, preset, n4079 }; + assign n2241 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7050, preset }; + assign n2246 = 64'h1313133102020220 >> { n_n9346, n4027, n4052, n4324, preset, n3814 }; + assign n2251 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7140, preset }; + assign n2256 = 32'd1426150400 >> { n4409, n_n7681, nsr3_38, ndn3_38, preset }; + assign n2261 = 8'h54 >> { n_n6948, n3835, preset }; + assign n2266 = 16'hea48 >> { n4174, n4621_1, n4183, n_n8549 }; + assign n4621_1 = 16'h99a9 >> { n4170, n_n8449, n4114, n4171_1 }; + assign n2271 = 16'h1110 >> { nen3_19, ndn3_19, preset, ngfdn_3 }; + assign n2276 = 16'h1110 >> { ndn3_28, nen3_28, preset, ngfdn_3 }; + assign n2281 = 16'h3120 >> { n_n7102, n_n9609, preset, n3835 }; + assign n2286 = 16'h3120 >> { n_n8093, n4356_1, preset, n3816_1 }; + assign n2291 = 16'h3120 >> { n_n9041, n4356_1, preset, n3819 }; + assign n2296 = 32'd1426150400 >> { n4318, n_n8381, nsr3_14, ndn3_14, preset }; + assign n2301 = 16'hf888 >> { n4202, n_n8810, n4099, n4203 }; + assign n2306 = 16'h1101 >> { nen3_36, nsr3_37, preset, ngfdn_3 }; + assign n2311 = 32'd1426150400 >> { n4313, n_n9047, nsr3_23, ndn3_23, preset }; + assign n2316 = 64'h1313133102020220 >> { n_n9333, n4027, n4052, n4324, preset, n3819 }; + assign n2321 = 16'h3120 >> { n_n7736, n4187, preset, n3822 }; + assign n2326 = 16'h3120 >> { n_n7820, n4301_1, preset, n3822 }; + assign n2331 = 16'h3120 >> { n_n8986, pinp_11_11_, preset, n4079 }; + assign n2336 = 16'h3120 >> { n_n8891, n4240, preset, n3822 }; + assign n2341 = 16'h3120 >> { n_n8000, pinp_14_14_, preset, n4079 }; + assign n2346 = 32'd1426150400 >> { n4349, n_n7968, nsr3_23, ndn3_23, preset }; + assign n2351 = 16'h3120 >> { n_n8750, n_n7962, preset, n3835 }; + assign n2356 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9558, preset }; + assign n2361 = 16'h3120 >> { n_n9368, n4356_1, preset, n3827 }; + assign n2366 = 16'h3120 >> { n_n8519, n4242, preset, n3828 }; + assign n2371 = 8'h54 >> { n_n6956, n3818, preset }; + assign n2376 = 16'h3120 >> { n_n8298, n4187, preset, n3812 }; + assign n2381 = 16'h3120 >> { n_n9397, n4099, preset, n3843 }; + assign n2386 = 16'h3120 >> { n_n7017, n_n9087, preset, n3827 }; + assign n2391 = 16'h3120 >> { n_n8638, psv38_2_2_, preset, n4079 }; + assign n2396 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9552, preset }; + assign n2401 = 32'd2012685042 >> { n4651_1, n3761_1, n4416_1, n4649, n_n8964 }; + assign n4649 = 64'h5555015555550054 >> { n3731_1, preset, n4175, n4196_1, n_n8668, n4650 }; + assign n4650 = 8'ha2 >> { n_n8913, n4417, n4183 }; + assign n4651_1 = 8'h08 >> { n_n8913, n4183, n4417 }; + assign n2406 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8016, preset }; + assign n2411 = 16'h3120 >> { n_n7603, n4301_1, preset, n3826_1 }; + assign n2416 = 16'h3120 >> { n_n7696, n4240, preset, n3808 }; + assign n2421 = 16'h3120 >> { n_n8589, n_n9221, preset, n3818 }; + assign n2426 = 64'h1313133102020220 >> { n_n9337, n4027, n4052, n4324, preset, n3851_1 }; + assign n2431 = 32'd1426150400 >> { n4207, n_n9132, nsr3_14, ndn3_14, preset }; + assign n2436 = 16'hae84 >> { n4174, n4659, n4183, n_n8652 }; + assign n4659 = 32'd2147516544 >> { n_n9015, n4121_1, n4139, n4140, n4138 }; + assign n2441 = 16'hea48 >> { n4174, n4661_1, n4183, n_n8707 }; + assign n4661_1 = 16'h95a9 >> { n4132, n4137, n_n9284, n4127 }; + assign n2446 = 16'h3120 >> { n_n9407, psv39_3_3_, preset, n4079 }; + assign n2451 = 16'h3120 >> { n_n9044, n4356_1, preset, n3809 }; + assign n2456 = 16'hf888 >> { n4212, n_n8808, n4099, n4213 }; + assign n2461 = 32'd4009688830 >> { ndn3_26, nak3_13, nsr3_30, pdn, preset }; + assign n2466 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8274, preset }; + assign n2471 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8615, preset }; + assign n2476 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8238, preset }; + assign n2481 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7854, preset }; + assign n2486 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8649, preset }; + assign n2491 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8236, preset }; + assign n2496 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8269, preset }; + assign n2501 = 32'd1426150400 >> { n3796_1, n_n9592, nsr3_30, ndn3_30, preset }; + assign n2506 = 16'h3120 >> { n_n8022, n4081_1, preset, n3835 }; + assign n2511 = 16'h3120 >> { n_n8744, n4356_1, preset, n4287 }; + assign n2516 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8529, preset }; + assign n2521 = 16'h3120 >> { n_n7967, n4242, preset, n3809 }; + assign n2526 = 32'd1426150400 >> { n3730, n_n9487, nsr3_38, ndn3_38, preset }; + assign n2531 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8685, preset }; + assign n2536 = 8'h54 >> { n_n9531, n3824, preset }; + assign n2541 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9510, preset }; + assign n2546 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7771, preset }; + assign n2551 = 32'd1426150400 >> { n4290, n_n8480, ndn3_37, nsr3_37, preset }; + assign n2556 = 16'h3120 >> { n_n8543, n4191_1, preset, n3813 }; + assign n2561 = 16'h3120 >> { n_n7789, n4081_1, preset, n3809 }; + assign n2566 = 16'h1110 >> { ndn3_11, ndn3_9, preset, ngfdn_3 }; + assign n2571 = 16'h1101 >> { ndn3_15, nsr3_13, preset, ngfdn_3 }; + assign n2576 = 16'h1110 >> { ndn3_21, ndn3_19, preset, ngfdn_3 }; + assign n2581 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7584, preset }; + assign n2586 = 32'd2863564932 >> { n4174, n4115, n4163, n4183, n_n8354 }; + assign n2591 = 8'h54 >> { n_n6952, n3835, preset }; + assign n2596 = 16'h3120 >> { n_n8864, n4242, preset, n3836_1 }; + assign n2601 = 16'h3120 >> { n_n7930, psv18_14_14_, preset, n4079 }; + assign n2606 = 16'h3120 >> { n_n7962, n4099, preset, n3798 }; + assign n2611 = 32'd1426150400 >> { n4401_1, n_n7929, nsr3_30, ndn3_30, preset }; + assign n2616 = 32'd1426150400 >> { n4313, n_n9316, nsr3_20, ndn3_20, preset }; + assign n2621 = 64'h1313133102020220 >> { n_n9102, n4027, n4052, n4324, preset, n3798 }; + assign n2626 = 8'h54 >> { n_n7308, n3827, preset }; + assign n2631 = 16'h3120 >> { n_n7657, psv39_0_0_, preset, n4079 }; + assign n2636 = 32'd1426150400 >> { n3796_1, n_n9264, nsr3_23, ndn3_23, preset }; + assign n2641 = 16'h3120 >> { n_n8760, n4191_1, preset, n3808 }; + assign n2646 = 8'h54 >> { n_n6912, n3835, preset }; + assign n2651 = 16'h3120 >> { n_n7887, n4219, preset, n3843 }; + assign n2656 = 64'hea48ea48ffffea48 >> { n3768, n4416_1, n4415, n4331_1, n4183, n_n8911 }; + assign n2661 = 16'h3120 >> { n_n7952, n4240, preset, n3828 }; + assign n2666 = 8'h54 >> { n_n8704, n3818, preset }; + assign n2671 = 32'd823336962 >> { n_n7876, n3853, n4217, preset, n3838 }; + assign n2676 = 16'h3120 >> { n_n9596, n3803, preset, n3827 }; + assign n2681 = 16'h3120 >> { n_n8430, n_n9106, preset, n3798 }; + assign n2686 = 32'd321978912 >> { n_n9019, n4007, n4061_1, preset, n4287 }; + assign n2691 = 8'h54 >> { n_n7699, n3827, preset }; + assign n2696 = 16'h3120 >> { n_n7375, n4187, preset, n4287 }; + assign n2701 = 16'h3120 >> { n_n7936, psv39_14_14_, preset, n4079 }; + assign n2706 = 16'h3120 >> { n_n8340, n_n8468, preset, n3824 }; + assign n2711 = 16'hf888 >> { n4103, n_n8809, n4099, n4104 }; + assign n2716 = 16'h3120 >> { n_n6961, n_n8989, preset, n3819 }; + assign n2721 = 32'd1426346240 >> { n_n7217, n_n9429, ndn3_50, ngfdn_3, preset }; + assign n2726 = 16'h3120 >> { n_n7743, psv26_2_2_, preset, n4079 }; + assign n2731 = 64'h1313133102020220 >> { n_n8980, n4027, n4052, n4324, preset, n3810 }; + assign n2736 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7582, preset }; + assign n2741 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8968, preset }; + assign n2746 = 16'h3120 >> { n_n9371, n_n8611, preset, n3798 }; + assign n2751 = 16'hf888 >> { n4212, n_n8741, n4356_1, n4213 }; + assign n2756 = 16'h3120 >> { n_n9502, psv39_5_5_, preset, n4079 }; + assign n2761 = 8'h54 >> { n_n9373, n3824, preset }; + assign n2766 = 4'hd >> { n4327, n4195 }; + assign n2771 = 16'h3120 >> { n_n7822, n4301_1, preset, n3827 }; + assign n2776 = 16'h3120 >> { n_n9054, pinp_1_1_, preset, n4079 }; + assign n2781 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8273, preset }; + assign n2786 = 8'h54 >> { n_n6937, n3827, preset }; + assign n2791 = 64'h1313133102020220 >> { n_n9342, n4027, n4052, n4324, preset, n3838 }; + assign n2796 = 16'h3120 >> { n_n9325, psv2_1_1_, preset, n4079 }; + assign n2801 = 64'h1313133102020220 >> { n_n9609, n4243, n4244, n4381_1, preset, n3798 }; + assign n2806 = 16'h3120 >> { n_n9623, n4219, preset, n3835 }; + assign n2811 = 16'h3120 >> { n_n9470, n3803, preset, n3836_1 }; + assign n2816 = 16'h3120 >> { n_n7570, n4081_1, preset, n3824 }; + assign n2821 = 32'd1426150400 >> { n4313, n_n9310, nsr3_38, ndn3_38, preset }; + assign n2826 = 16'h3120 >> { n_n9366, n_n7464, preset, n3798 }; + assign n2831 = 8'h54 >> { n_n7181, n3824, preset }; + assign n2836 = 16'h3120 >> { n_n8739, psv2_9_9_, preset, n4079 }; + assign n2841 = 16'h3120 >> { n_n8939, n3803, preset, n4287 }; + assign n2846 = 16'h3120 >> { n_n7256, n_n9171, preset, n3824 }; + assign n2851 = 64'h1313133102020220 >> { n_n8983, n4027, n4052, n4324, preset, n4287 }; + assign n2856 = 16'hf888 >> { n4103, n_n7487, n4187, n4104 }; + assign n2861 = 16'h3120 >> { n_n9268, n3803, preset, n3814 }; + assign n2866 = 16'h3120 >> { n_n8906, n3803, preset, n3813 }; + assign n2871 = 32'd1426150400 >> { n4290, n_n7988, nsr3_35, ndn3_35, preset }; + assign n2876 = 16'h3120 >> { n_n9181, n4106_1, preset, n3808 }; + assign n2881 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n8725, preset }; + assign n2886 = 16'h3120 >> { n_n8626, n4219, preset, n3810 }; + assign n2891 = 16'h1110 >> { ndn3_27, ndn3_26, preset, ngfdn_3 }; + assign n2896 = 32'd1426150400 >> { n4397, n_n8210, nsr3_14, ndn3_14, preset }; + assign n2901 = 8'h54 >> { n_n7415, n3819, preset }; + assign n2906 = 32'd1426150400 >> { n4349, n_n8900, nsr3_30, ndn3_30, preset }; + assign n2911 = 16'h1101 >> { nen3_19, nsr3_20, preset, ngfdn_3 }; + assign n2916 = 8'h54 >> { n_n8762, n3819, preset }; + assign n2921 = 64'h1313133102020220 >> { n_n8512, n4243, n4244, n4381_1, preset, n3836_1 }; + assign n2926 = 32'd1426150400 >> { n4368, n_n8095, nsr3_35, ndn3_35, preset }; + assign n2931 = 64'hffff222822282228 >> { n4202, n_n8982, n4027, n4052, n4324, n4203 }; + assign n2936 = 8'h54 >> { n_n7387, n3819, preset }; + assign n2941 = 32'd1426150400 >> { n3730, n_n9494, nsr3_20, ndn3_20, preset }; + assign n2946 = 16'h3120 >> { n_n7689, psv2_10_10_, preset, n4079 }; + assign n2951 = 16'h3120 >> { n_n7835, psv39_4_4_, preset, n4079 }; + assign n2956 = 32'd321978912 >> { n_n9157, n4007, n4061_1, preset, n3822 }; + assign n2961 = 32'd823336962 >> { n_n8552, n3853, n4217, preset, n3809 }; + assign n2966 = 8'h54 >> { n_n7381, n3827, preset }; + assign n2971 = 8'h54 >> { n_n9446, n3835, preset }; + assign n2976 = 8'h54 >> { n_n8633, n3798, preset }; + assign n2981 = 16'h3120 >> { n_n7684, n4191_1, preset, n3827 }; + assign n2986 = 8'h54 >> { n_n7310, n3827, preset }; + assign n2991 = 16'h3120 >> { n_n8402, n4081_1, preset, n3826_1 }; + assign n2996 = 16'h3120 >> { n_n9315, n4356_1, preset, n3843 }; + assign n3001 = 32'd1426150400 >> { n4368, n_n7950, nsr3_30, ndn3_30, preset }; + assign n3006 = 16'h3120 >> { n_n8504, psv39_13_13_, preset, n4079 }; + assign n3011 = 16'h3120 >> { n_n8456, psv33_15_15_, preset, n4079 }; + assign n3016 = 16'h3120 >> { n_n7514, n_n8188, preset, n3824 }; + assign n3021 = 8'h54 >> { n_n7315, n3798, preset }; + assign n3026 = 8'h54 >> { n_n9476, n3798, preset }; + assign n3031 = 16'h3120 >> { n_n8276, n4191_1, preset, n3812 }; + assign n3036 = 32'd1426150400 >> { n4441_1, n_n8833, nsr3_13, ndn3_13, preset }; + assign n3041 = 32'd1426346240 >> { n_n7779, n_n7923, ndn3_50, ngfdn_3, preset }; + assign n3046 = 16'h3120 >> { n_n9395, n4099, preset, n3822 }; + assign n3051 = 32'd3937290372 >> { n4174, n4119, n4784, n4183, n_n9512 }; + assign n4784 = 8'h2b >> { n4123, n4126_1, n_n9353 }; + assign n3056 = 16'h3120 >> { n_n9319, n4356_1, preset, n3828 }; + assign n3061 = 32'd4009688830 >> { ndn3_29, nak3_13, nsr3_35, pdn, preset }; + assign n3066 = 8'h54 >> { n_n7154, n3798, preset }; + assign n3071 = 16'h3120 >> { n_n9495, n4106_1, preset, n3838 }; + assign n3076 = 16'h3120 >> { n_n9137, pinp_3_3_, preset, n4079 }; + assign n3081 = 16'h3120 >> { n_n8854, n4240, preset, n3827 }; + assign n3086 = 16'h3120 >> { n_n9183, pinp_5_5_, preset, n4079 }; + assign n3091 = 16'h3120 >> { n_n9323, psv13_1_1_, preset, n4079 }; + assign n3096 = 16'h3120 >> { n_n9349, pinp_9_9_, preset, n4079 }; + assign n3101 = 16'h3120 >> { n_n7896, n4219, preset, n3824 }; + assign n3106 = 16'h3120 >> { n_n8073, n_n7624, preset, n3798 }; + assign n3111 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8970, preset }; + assign n3116 = 16'h3120 >> { n_n9314, psv18_1_1_, preset, n4079 }; + assign n3121 = 32'd1426346240 >> { n_n9626, n_n8486, ndn3_50, ngfdn_3, preset }; + assign n3126 = 8'h54 >> { n_n7246, n3827, preset }; + assign n3131 = 16'h3120 >> { n_n7866, psv13_9_9_, preset, n4079 }; + assign n3136 = 16'h3120 >> { n_n9599, n3803, preset, n3837 }; + assign n3141 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7635, preset }; + assign n3146 = 64'h1313133102020220 >> { n_n8984, n4027, n4052, n4324, preset, n3837 }; + assign n3151 = 16'h3120 >> { n_n7360, n_n7756, preset, n3827 }; + assign n3156 = 16'h3120 >> { n_n8794, n4099, preset, n3813 }; + assign n3161 = 64'h1313133102020220 >> { n_n9108, n4243, n4244, n4381_1, preset, n3810 }; + assign n3166 = 16'hf888 >> { n4103, n_n9286, n4240, n4104 }; + assign n3171 = 16'h1110 >> { ndn3_11, ndn3_12, preset, ngfdn_3 }; + assign n3176 = 16'h1110 >> { nen3_16, ndn3_16, preset, ngfdn_3 }; + assign n3181 = 32'd321978912 >> { n_n7708, n4007, n4061_1, preset, n3809 }; + assign n3186 = 32'd1426150400 >> { n4292, n_n7807, nsr3_35, ndn3_35, preset }; + assign n3191 = 32'd1426150400 >> { n4397, n_n7650, nsr3_35, ndn3_35, preset }; + assign n3196 = 16'h3120 >> { n_n7947, n4240, preset, n3810 }; + assign n3201 = 16'h3120 >> { n_n9500, psv26_5_5_, preset, n4079 }; + assign n3206 = 32'd1426150400 >> { n4318, n_n7734, nsr3_35, ndn3_35, preset }; + assign n3211 = 16'h3120 >> { n_n8464, n4099, preset, n3816_1 }; + assign n3216 = 8'h54 >> { n_n7659, n3819, preset }; + assign n3221 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7630, preset }; + assign n3226 = 64'h1313133102020220 >> { n_n7756, n4027, n4052, n4324, preset, n3816_1 }; + assign n3231 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8691, preset }; + assign n3236 = 32'd1426150400 >> { n3730, n_n9176, nsr3_23, ndn3_23, preset }; + assign n3241 = 32'd823336962 >> { n_n9327, n3853, n4217, preset, n3822 }; + assign n3246 = 16'h3120 >> { n_n7995, n4102, preset, n3809 }; + assign n3251 = 16'h3120 >> { n_n7395, n_n8206, preset, n3835 }; + assign n3256 = 32'd823336962 >> { n_n7878, n3853, n4217, preset, n3828 }; + assign n3261 = 8'h54 >> { n_n7507, n3798, preset }; + assign n3266 = 8'h54 >> { n_n7959, n3818, preset }; + assign n3271 = 16'h3120 >> { n_n7825, n4301_1, preset, n3850 }; + assign n3276 = 16'h3120 >> { n_n8009, pinp_2_2_, preset, n4079 }; + assign n3281 = 16'h3120 >> { n_n8281, n4219, preset, n4287 }; + assign n3286 = 32'd1426150400 >> { n4409, n_n7685, nsr3_20, ndn3_20, preset }; + assign n3291 = 64'h1313133102020220 >> { n_n8106, n4243, n4244, n4381_1, preset, n3828 }; + assign n3296 = 16'h3120 >> { n_n7687, n4191_1, preset, n3828 }; + assign n3301 = 16'h3120 >> { n_n7766, psv13_11_11_, preset, n4079 }; + assign n3306 = 16'h3120 >> { n_n7880, psv13_6_6_, preset, n4079 }; + assign n3311 = 32'd823336962 >> { n_n8961, n3853, n4217, preset, n3814 }; + assign n3316 = 16'h3120 >> { n_n8014, n4242, preset, n3814 }; + assign n3321 = 32'd1426346240 >> { n_n7781, n_n9278, ndn3_50, ngfdn_3, preset }; + assign n3326 = 16'h3120 >> { n_n9087, n4102, preset, n3816_1 }; + assign n3331 = 16'h3120 >> { n_n9182, psv33_5_5_, preset, n4079 }; + assign n3336 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7852, preset }; + assign n3341 = 16'h3120 >> { n_n9324, psv39_1_1_, preset, n4079 }; + assign n3346 = 4'h1 >> { n4196_1, preset }; + assign n3351 = 32'd2934604872 >> { n4174, n4845, n4144, n4183, n_n9416 }; + assign n4845 = 8'h2b >> { n4118, n_n9434, n4147 }; + assign n5961 = 4'h1 >> { preset, nsr3_14 }; + assign n3356 = 32'd4278120190 >> { nsr3_13, nak3_13, nsr3_14, pdn, preset }; + assign n3361 = 32'd285326091 >> { n4183, n3771_1, n4416_1, n4415, n_n8603 }; + assign n3366 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7026, preset }; + assign n3371 = 32'd823336962 >> { n_n8856, n3853, n4217, preset, n3827 }; + assign n3376 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8272, preset }; + assign n3381 = 32'd1426150400 >> { n4313, n_n9312, nsr3_30, ndn3_30, preset }; + assign n3386 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7985, preset }; + assign n3391 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8312, preset }; + assign n3396 = 16'h3120 >> { n_n7231, n_n8093, preset, n3827 }; + assign n3401 = 16'h3120 >> { n_n9396, psv18_3_3_, preset, n4079 }; + assign n3406 = 16'h3120 >> { n_n8801, n_n8247, preset, n3819 }; + assign n3411 = 8'h54 >> { n_n8683, n3835, preset }; + assign n3416 = 16'h1110 >> { nen3_39, ndn3_39, preset, ngfdn_3 }; + assign n3421 = 8'h54 >> { n_n8245, n3835, preset }; + assign n3426 = 32'd823336962 >> { n_n9458, n3853, n4217, preset, n3810 }; + assign n3431 = 16'h3120 >> { n_n9302, psv33_8_8_, preset, n4079 }; + assign n3436 = 16'h3120 >> { n_n7392, n_n9586, preset, n3827 }; + assign n3441 = 16'h3120 >> { n_n6963, n_n9155, preset, n3835 }; + assign n3446 = 32'd1426150400 >> { n4292, n_n7808, nsr3_30, ndn3_30, preset }; + assign n3451 = 32'd1426150400 >> { n4441_1, n_n7225, nsr3_20, ndn3_20, preset }; + assign n3456 = 16'h3120 >> { n_n7817, psv2_12_12_, preset, n4079 }; + assign n3461 = 32'd4280821800 >> { n4212, n_n8201, n4007, n4061_1, n4213 }; + assign n3466 = 16'h3120 >> { n_n7793, n4081_1, preset, n3808 }; + assign n3471 = 16'hf888 >> { n4212, n_n8177, n4191_1, n4213 }; + assign n3476 = 8'h54 >> { n_n8389, n3827, preset }; + assign n3481 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9440, preset }; + assign n3486 = 16'h3120 >> { n_n7683, n4191_1, preset, n3843 }; + assign n3491 = 32'd1426150400 >> { n4185, n_n7761, nsr3_20, ndn3_20, preset }; + assign n3496 = 32'd1426150400 >> { n4409, n_n7667, nsr3_23, ndn3_23, preset }; + assign n3501 = 32'd1426150400 >> { n4374, n_n7980, nsr3_30, ndn3_30, preset }; + assign n3506 = 16'h3120 >> { n_n7509, psv38_0_0_, preset, n4079 }; + assign n3511 = 16'h3120 >> { n_n7813, n4081_1, preset, n3850 }; + assign n3516 = 32'd1426150400 >> { n4185, n_n8396, nsr3_13, ndn3_13, preset }; + assign n3521 = 16'h3120 >> { n_n9535, n_n9309, preset, n3819 }; + assign n3526 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7209, preset }; + assign n3531 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7003, preset }; + assign n3536 = 16'h3120 >> { n_n7695, n4240, preset, n3814 }; + assign n3541 = 32'd823336962 >> { n_n7624, n3853, n4217, preset, n3813 }; + assign n3546 = 16'h3120 >> { n_n8791, n4301_1, preset, n3808 }; + assign n3551 = 16'hf888 >> { n4202, n_n7374, n4187, n4203 }; + assign n3556 = 16'hf888 >> { n4202, n_n7429, n4301_1, n4203 }; + assign n3561 = 8'h54 >> { n_n7944, n3818, preset }; + assign n3566 = 32'd1426150400 >> { n3796_1, n_n9266, nsr3_14, ndn3_14, preset }; + assign n3571 = 16'h3120 >> { n_n8100, n_n8871, preset, n3798 }; + assign n3576 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n6988, preset }; + assign n3581 = 8'h54 >> { n_n6986, n3798, preset }; + assign n3586 = 64'hea48ea48ffffea48 >> { n3791_1, n4416_1, n4415, n4332, n4183, n_n8933 }; + assign n3591 = 8'h54 >> { n_n7117, n3798, preset }; + assign n3596 = 32'd1426150400 >> { n4313, n_n9043, ndn3_37, nsr3_37, preset }; + assign n3601 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8241, preset }; + assign n3606 = 16'h3120 >> { n_n9219, n4301_1, preset, n3818 }; + assign n3611 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8198, preset }; + assign n3616 = 16'h3120 >> { n_n8081, n4242, preset, n3818 }; + assign n3621 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8575, preset }; + assign n3626 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8710, preset }; + assign n3631 = 8'h54 >> { n_n7622, n3827, preset }; + assign n3636 = 32'd1426150400 >> { n4349, n_n7966, ndn3_37, nsr3_37, preset }; + assign n3641 = 32'd1426150400 >> { n4290, n_n7885, nsr3_38, ndn3_38, preset }; + assign n3646 = 8'h54 >> { n_n7033, n3824, preset }; + assign n3651 = 16'h1110 >> { ndn3_34, nen3_34, preset, ngfdn_3 }; + assign n3656 = 32'd1426150400 >> { n4200, n_n9186, nsr3_13, ndn3_13, preset }; + assign n3661 = 8'h02 >> { preset, ngfdn_3, ndn3_50 }; + assign n3666 = 32'd1426150400 >> { n4374, n_n7879, nsr3_13, ndn3_13, preset }; + assign n3671 = 8'h54 >> { n_n7019, n3819, preset }; + assign n3676 = 16'h3120 >> { n_n9171, n4106_1, preset, n3819 }; + assign n3681 = 8'h54 >> { n_n7261, n3818, preset }; + assign n3686 = 16'h3120 >> { n_n8223, n4081_1, preset, n3836_1 }; + assign n3691 = 64'h1313133102020220 >> { n_n8989, n4027, n4052, n4324, preset, n3835 }; + assign n3696 = 16'h3120 >> { n_n7993, n4187, preset, n3809 }; + assign n3701 = 16'h3120 >> { n_n7845, n4219, preset, n3851_1 }; + assign n3706 = 16'h3120 >> { n_n8253, n4301_1, preset, n3809 }; + assign n3711 = 16'h3120 >> { n_n8889, n4191_1, preset, n3822 }; + assign n3716 = 16'h3120 >> { n_n7809, n4081_1, preset, n3827 }; + assign n3721 = 8'h54 >> { n_n8918, n3835, preset }; + assign n3726 = 64'h1313133102020220 >> { n_n8515, n4243, n4244, n4381_1, preset, n4287 }; + assign n3731 = 64'h1313133102020220 >> { n_n7933, n4243, n4244, n4381_1, preset, n3838 }; + assign n3736 = 16'h3120 >> { n_n8075, n4102, preset, n3812 }; + assign n3741 = 8'h54 >> { n_n7338, n3827, preset }; + assign n3746 = 16'h3120 >> { n_n8104, n4102, preset, n4287 }; + assign n3751 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8171, preset }; + assign n3756 = 32'd1426150400 >> { n4318, n_n9059, nsr3_38, ndn3_38, preset }; + assign n3761 = 16'h3120 >> { n_n9023, psv2_8_8_, preset, n4079 }; + assign n3766 = 16'h3120 >> { n_n7692, psv38_8_8_, preset, n4079 }; + assign n3771 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9441, preset }; + assign n3776 = 16'h3120 >> { n_n6920, n_n8470, preset, n3824 }; + assign n3781 = 8'h54 >> { n_n8831, n3798, preset }; + assign n3786 = 8'h54 >> { n_n8441, n3798, preset }; + assign n3791 = 16'h3120 >> { n_n9576, n4187, preset, n3798 }; + assign n3796 = 16'h3120 >> { n_n9252, n4301_1, preset, n3816_1 }; + assign n3801 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9363, preset }; + assign n3806 = 16'h1110 >> { ndn3_4, ndn3_2, preset, ngfdn_3 }; + assign n3811 = 16'h2220 >> { n_n9247, n4176_1, preset, n4327 }; + assign n3816 = 8'h54 >> { n_n7561, n3818, preset }; + assign n3821 = 64'hffffaaeaffff8848 >> { n4415, n4941_1, n_n8798, n_n8603, n4183, n_n8923 }; + assign n4941_1 = 4'h2 >> { n3788, n4416_1 }; + assign n3826 = 8'h54 >> { n_n7978, n3798, preset }; + assign n3831 = 64'hea48ea48ffffea48 >> { n3778, n4416_1, n4415, n4330, n4183, n_n8978 }; + assign n3836 = 16'h3120 >> { n_n9499, n4106_1, preset, n3850 }; + assign n3841 = 8'h54 >> { n_n8713, n3824, preset }; + assign n3846 = 8'h54 >> { n_n8944, n3824, preset }; + assign n3851 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8239, preset }; + assign n3856 = 16'h3120 >> { n_n7652, n4102, preset, n3843 }; + assign n3861 = 16'h3120 >> { n_n9042, n4356_1, preset, n3836_1 }; + assign n3866 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8530, preset }; + assign n3871 = 16'h3120 >> { n_n9271, pinp_7_7_, preset, n4079 }; + assign n3876 = 16'h3120 >> { n_n9318, n4356_1, preset, n3837 }; + assign n3881 = 32'd321978912 >> { n_n7706, n4007, n4061_1, preset, n3819 }; + assign n3886 = 16'h3120 >> { n_n7964, n_n9041, preset, n3824 }; + assign n3891 = 16'h3120 >> { n_n8222, n4081_1, preset, n3810 }; + assign n3896 = 16'h3120 >> { n_n8898, n4301_1, preset, n3810 }; + assign n3901 = 16'h3120 >> { n_n7976, n_n8765, preset, n3818 }; + assign n3906 = 32'd823336962 >> { n_n7649, n3853, n4217, preset, n3851_1 }; + assign n3911 = 16'h3120 >> { n_n7604, psv33_4_4_, preset, n4079 }; + assign n3916 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7961, preset }; + assign n3921 = 16'h3120 >> { n_n7424, psv26_9_9_, preset, n4079 }; + assign n3926 = 32'd1358976260 >> { preset_0_0_, n_n7476, nlc1_2, nsr1_2, preset }; + assign n3931 = 16'h3120 >> { n_n9259, n3803, preset, n3819 }; + assign n3936 = 16'h3120 >> { n_n9309, n4356_1, preset, n3835 }; + assign n3941 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9161, preset }; + assign n3946 = 64'h1313133102020220 >> { n_n8436, n4027, n4052, n4324, preset, n3824 }; + assign n3951 = 16'h3120 >> { n_n9121, psv39_6_6_, preset, n4079 }; + assign n3956 = 16'h3120 >> { n_n8061, n_n9104, preset, n3835 }; + assign n3961 = 16'h3120 >> { n_n8004, n4242, preset, n3827 }; + assign n3966 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9360, preset }; + assign n3971 = 16'hf888 >> { n4103, n_n9205, n4081_1, n4104 }; + assign n3976 = 8'h54 >> { n_n8392, n3835, preset }; + assign n3981 = 64'h88f888f8ffff88f8 >> { n4334, n4183, n3734, n4416_1, n4415, n_n9034 }; + assign n3986 = 16'h3120 >> { n_n8375, n4240, preset, n3850 }; + assign n3991 = 32'd1426150400 >> { n4374, n_n8328, ndn3_37, nsr3_37, preset }; + assign n3996 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9298, preset }; + assign n4001 = 16'h3120 >> { n_n7598, n4301_1, preset, n3836_1 }; + assign n4006 = 16'h3120 >> { n_n8506, psv39_11_11_, preset, n4079 }; + assign n4011 = 16'h3120 >> { n_n7737, psv18_2_2_, preset, n4079 }; + assign n4016 = 32'd1426346240 >> { n_n7558, n_n7420, ndn3_50, ngfdn_3, preset }; + assign n4021 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9291, preset }; + assign n4026 = 16'h3120 >> { n_n7946, psv26_14_14_, preset, n4079 }; + assign n4031 = 16'h3120 >> { n_n8584, n4242, preset, n3837 }; + assign n4036 = 16'h3120 >> { n_n9308, n4356_1, preset, n3810 }; + assign n4041 = 32'd1426150400 >> { n4207, n_n9403, nsr3_13, ndn3_13, preset }; + assign n4046 = 16'h3120 >> { n_n7284, n_n7898, preset, n3824 }; + assign n4051 = 16'h3120 >> { n_n9270, psv33_7_7_, preset, n4079 }; + assign n4056 = 16'h3120 >> { n_n7390, n_n7334, preset, n3798 }; + assign n4061 = 16'h3120 >> { n_n9351, n4240, preset, n3816_1 }; + assign n4066 = 32'd1426150400 >> { n4441_1, n_n6968, nsr3_35, ndn3_35, preset }; + assign n4071 = 4'h8 >> { n4195, n_n8668 }; + assign n4076 = 16'h3120 >> { n_n9605, psv39_7_7_, preset, n4079 }; + assign n4081 = 8'h54 >> { n_n7013, n3818, preset }; + assign n4086 = 16'h3120 >> { n_n9626, n4102, preset, n3818 }; + assign n4091 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8200, preset }; + assign n4096 = 16'h3120 >> { n_n9028, n4187, preset, n3818 }; + assign n4101 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8803, preset }; + assign n4106 = 32'd823336962 >> { n_n9570, n3853, n4217, preset, n3818 }; + assign n4111 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8366, preset }; + assign n4116 = 16'h3120 >> { n_n9050, n4356_1, preset, n3812 }; + assign n4121 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8650, preset }; + assign n4126 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8574, preset }; + assign n4131 = 8'h54 >> { n_n7276, n3827, preset }; + assign n4136 = 16'h3120 >> { n_n9212, psv38_3_3_, preset, n4079 }; + assign n4141 = 16'h3120 >> { n_n8384, n_n8464, preset, n3827 }; + assign n4146 = 4'h1 >> { preset, nsr3_35 }; + assign n4151 = 32'd2863564932 >> { n4174, n4114, n4170, n4183, n_n8449 }; + assign n4156 = 16'h1110 >> { ndn3_44, ndn3_46, preset, ngfdn_3 }; + assign n4161 = 16'h3120 >> { n_n7554, psv33_2_2_, preset, n4079 }; + assign n4166 = 16'hf888 >> { n4202, n_n8743, n4356_1, n4203 }; + assign n4171 = 16'h3120 >> { n_n8277, n4219, preset, n3836_1 }; + assign n4176 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9359, preset }; + assign n4181 = 64'h1313133102020220 >> { n_n8425, n4243, n4244, n4381_1, preset, n3822 }; + assign n4186 = 16'h3120 >> { n_n9104, n3803, preset, n3798 }; + assign n4191 = 16'h3120 >> { n_n9221, n4356_1, preset, n3824 }; + assign n4196 = 32'd3937290372 >> { n4174, n5017, n4157, n4183, n_n9448 }; + assign n5017 = 8'hb2 >> { n4116_1, n4160, n_n9638 }; + assign n4201 = 32'd2863564932 >> { n4174, n4117, n4150, n4183, n_n9537 }; + assign n4206 = 16'h3120 >> { n_n8003, n4242, preset, n3843 }; + assign n4211 = 8'h54 >> { n_n7467, n3835, preset }; + assign n4216 = 16'h3120 >> { n_n8233, n4301_1, preset, n3828 }; + assign n4221 = 64'h1313133102020220 >> { n_n7932, n4243, n4244, n4381_1, preset, n3827 }; + assign n4226 = 32'd1426150400 >> { n4349, n_n8064, nsr3_20, ndn3_20, preset }; + assign n4231 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9162, preset }; + assign n4236 = 16'h3120 >> { n_n7971, n4242, preset, n3808 }; + assign n4241 = 8'h54 >> { n_n8055, n3818, preset }; + assign n4246 = 32'd1426150400 >> { n4185, n_n7711, nsr3_23, ndn3_23, preset }; + assign n4251 = 16'h3120 >> { n_n8256, n3803, preset, n3818 }; + assign n4256 = 32'd1426150400 >> { n4200, n_n7925, nsr3_30, ndn3_30, preset }; + assign n4261 = 32'd321978912 >> { n_n7762, n4007, n4061_1, preset, n3838 }; + assign n4266 = 16'h3120 >> { n_n7668, n4191_1, preset, n3814 }; + assign n4271 = 16'h3120 >> { n_n7914, psv33_14_14_, preset, n4079 }; + assign n4276 = 32'd1426150400 >> { n4374, n_n7873, nsr3_38, ndn3_38, preset }; + assign n4281 = 16'h3120 >> { n_n7849, n4219, preset, n3814 }; + assign n4286 = 16'h3120 >> { n_n9421, n_n7691, preset, n3824 }; + assign n4291 = 16'h3120 >> { n_n7626, n4301_1, preset, n3813 }; + assign n4296 = 16'h3120 >> { n_n7848, n4219, preset, n3812 }; + assign n4301 = 32'd1426346240 >> { n_n8081, n_n8263, ndn3_50, ngfdn_3, preset }; + assign n4306 = 16'h3120 >> { n_n9100, n4187, preset, n3816_1 }; + assign n4311 = 32'd1426150400 >> { n4207, n_n9393, nsr3_35, ndn3_35, preset }; + assign n4316 = 32'd1426150400 >> { n3796_1, n_n9591, nsr3_35, ndn3_35, preset }; + assign n4321 = 16'hf888 >> { n4202, n_n7588, n4240, n4203 }; + assign n4326 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n9123, preset }; + assign n4331 = 64'h1313133102020220 >> { n_n9159, n4027, n4052, n4324, preset, n3822 }; + assign n4336 = 16'h3120 >> { n_n9128, n4099, preset, n3809 }; + assign n4341 = 16'h3120 >> { n_n8045, n_n7136, preset, n3835 }; + assign n4346 = 16'h3120 >> { n_n7728, n4102, preset, n3827 }; + assign n4351 = 8'h54 >> { n_n8929, n4197, preset }; + assign n4356 = 16'h3120 >> { n_n7739, n4187, preset, n3827 }; + assign n4361 = 16'h3120 >> { n_n9355, n4242, preset, n3835 }; + assign n4366 = 32'd1426150400 >> { n4207, n_n9394, nsr3_30, ndn3_30, preset }; + assign n4371 = 16'h3120 >> { n_n8470, n4219, preset, n3819 }; + assign n4376 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8571, preset }; + assign n4381 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8796, preset }; + assign n4386 = 16'h1110 >> { ndn3_36, nen3_36, preset, ngfdn_3 }; + assign n4391 = 32'd1426150400 >> { n4185, n_n7990, nsr3_35, ndn3_35, preset }; + assign n4396 = 16'h3120 >> { n_n8781, n_n9255, preset, n3827 }; + assign n4401 = 8'h54 >> { n_n8817, n3819, preset }; + assign n4406 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9160, preset }; + assign n4411 = 32'd1426150400 >> { n4290, n_n9092, nsr3_30, ndn3_30, preset }; + assign n4416 = 64'hffff222822282228 >> { n4212, n_n8513, n4243, n4244, n4381_1, n4213 }; + assign n4421 = 16'h3120 >> { n_n8213, n3803, preset, n3816_1 }; + assign n4426 = 16'hf888 >> { n4103, n_n8581, n4242, n4104 }; + assign n4431 = 32'd3937290372 >> { n4174, n4132, n4137, n4183, n_n9284 }; + assign n4436 = 16'h3120 >> { n_n7837, psv39_2_2_, preset, n4079 }; + assign n4441 = 16'hf888 >> { n4212, n_n8224, n4081_1, n4213 }; + assign n4446 = 64'hffff222822282228 >> { n4103, n_n9203, n4243, n4244, n4381_1, n4104 }; + assign n4451 = 16'h3120 >> { n_n7655, n4102, preset, n3850 }; + assign n4456 = 8'h54 >> { n_n8946, n3798, preset }; + assign n4461 = 8'h54 >> { n_n7052, n3824, preset }; + assign n4466 = 32'd4280821800 >> { n4103, n_n9615, n4007, n4061_1, n4104 }; + assign n4471 = 16'h3120 >> { n_n8473, n4081_1, preset, n3843 }; + assign n4476 = 16'h3120 >> { n_n7741, n4187, preset, n3838 }; + assign n4481 = 16'h3120 >> { n_n9460, n4219, preset, n3816_1 }; + assign n4486 = 64'h1313133102020220 >> { n_n7912, n4243, n4244, n4381_1, preset, n3826_1 }; + assign n4491 = 16'h3120 >> { n_n7606, n4106_1, preset, n3818 }; + assign n4496 = 16'h3120 >> { n_n9021, n4240, preset, n3838 }; + assign n4501 = 64'h1313133102020220 >> { n_n7781, n4027, n4052, n4324, preset, n3818 }; + assign n4506 = 16'h3120 >> { n_n7810, n4081_1, preset, n3838 }; + assign n4511 = 16'h3120 >> { n_n7108, n_n8794, preset, n3798 }; + assign n4516 = 16'h3120 >> { n_n7697, pinp_8_8_, preset, n4079 }; + assign n4521 = 32'd823336962 >> { n_n7642, n3853, n4217, preset, n3812 }; + assign n4526 = 16'h3120 >> { n_n9595, n3803, preset, n3843 }; + assign n4531 = 16'h3120 >> { n_n7694, n4240, preset, n3812 }; + assign n4536 = 32'd1426150400 >> { n4409, n_n8221, nsr3_14, ndn3_14, preset }; + assign n4541 = 16'h3120 >> { n_n7600, psv38_4_4_, preset, n4079 }; + assign n4546 = 64'h1313133102020220 >> { n_n7935, n4243, n4244, n4381_1, preset, n3850 }; + assign n4551 = 16'h3120 >> { n_n9230, psv18_6_6_, preset, n4079 }; + assign n4556 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7701, preset }; + assign n4561 = 16'h3120 >> { n_n7510, n4102, preset, n3826_1 }; + assign n4566 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7627, preset }; + assign n4571 = 16'h3120 >> { n_n8502, psv13_15_15_, preset, n4079 }; + assign n4576 = 64'h1313133102020220 >> { n_n8516, n4243, n4244, n4381_1, preset, n3837 }; + assign n4581 = 64'h1313133102020220 >> { n_n7913, n4243, n4244, n4381_1, preset, n3812 }; + assign n4586 = 32'd1426150400 >> { n4313, n_n9320, nsr3_13, ndn3_13, preset }; + assign n4591 = 8'h54 >> { n_n7411, n3798, preset }; + assign n4596 = 16'h3120 >> { n_n9129, n4099, preset, n3851_1 }; + assign n4601 = 16'h3120 >> { n_n9053, psv33_1_1_, preset, n4079 }; + assign n4606 = 32'd1426346240 >> { n_n7324, n_n7069, ndn3_50, ngfdn_3, preset }; + assign n4611 = 16'h3120 >> { n_n8617, psv26_4_4_, preset, n4079 }; + assign n4616 = 8'h54 >> { n_n7242, n3819, preset }; + assign n4621 = 8'h54 >> { n_n8230, n3819, preset }; + assign n4626 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9294, preset }; + assign n4631 = 16'h3120 >> { n_n8249, n4102, preset, n3835 }; + assign n4636 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8972, preset }; + assign n4641 = 16'h3120 >> { n_n7074, n_n9355, preset, n3819 }; + assign n4646 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n7493, preset }; + assign n4651 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n8290, preset }; + assign n4656 = 16'hea48 >> { n4174, n5110, n4183, n_n8821 }; + assign n5110 = 16'h99a9 >> { n4150, n_n9537, n4117, n4151_1 }; + assign n4661 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7769, preset }; + assign n4666 = 8'h54 >> { n_n7491, n3824, preset }; + assign n4671 = 16'h3120 >> { n_n9600, n3803, preset, n3828 }; + assign n4676 = 16'h3120 >> { n_n9317, n4356_1, preset, n3838 }; + assign n4681 = 8'h54 >> { n_n8047, n3798, preset }; + assign n4686 = 16'h3120 >> { n_n9629, n4242, preset, n3824 }; + assign n4691 = 16'h3120 >> { n_n9126, n4099, preset, n3836_1 }; + assign n4696 = 16'h3120 >> { n_n9508, n4081_1, preset, n3818 }; + assign n4701 = 32'd321978912 >> { n_n9155, n4007, n4061_1, preset, n3798 }; + assign n4706 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8528, preset }; + assign n4716 = 16'h1110 >> { ndn3_42, ndn3_40, preset, ngfdn_3 }; + assign n4721 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9358, preset }; + assign n4726 = 16'h3120 >> { n_n8185, n_n9304, preset, n3827 }; + assign n4731 = 16'h1101 >> { nen3_28, nsr3_30, preset, ngfdn_3 }; + assign n4736 = 16'h3120 >> { n_n8839, n4242, preset, n3822 }; + assign n4741 = 8'h54 >> { n_n7903, n3819, preset }; + assign n4746 = 16'hf888 >> { n4202, n_n9139, n3803, n4203 }; + assign n4751 = 16'h3120 >> { n_n9075, n4102, preset, n3822 }; + assign n4756 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9439, preset }; + assign n4761 = 32'd2934604872 >> { n4174, n4123, n4126_1, n4183, n_n9353 }; + assign n4766 = 16'h3120 >> { n_n7665, psv38_10_10_, preset, n4079 }; + assign n4771 = 64'hea48ea48ffffea48 >> { n3748, n4416_1, n4415, n_n8603, n4183, n_n8798 }; + assign n4776 = 8'h54 >> { n_n7146, n3824, preset }; + assign n4781 = 16'h3120 >> { n_n7890, psv2_13_13_, preset, n4079 }; + assign n4786 = 8'h54 >> { n_n7176, n3818, preset }; + assign n4791 = 32'd1426150400 >> { n4397, n_n8477, ndn3_37, nsr3_37, preset }; + assign n4796 = 64'hffff222822282228 >> { n4202, n_n8514, n4243, n4244, n4381_1, n4203 }; + assign n4801 = 32'd1426150400 >> { n4318, n_n8636, ndn3_37, nsr3_37, preset }; + assign n4806 = 8'h54 >> { n_n7183, n3798, preset }; + assign n4811 = 32'd1426150400 >> { n4292, n_n8657, nsr3_20, ndn3_20, preset }; + assign n4816 = 16'h3120 >> { n_n9493, n4106_1, preset, n3827 }; + assign n4821 = 32'd1426150400 >> { n4349, n_n7969, nsr3_14, ndn3_14, preset }; + assign n4826 = 16'h3120 >> { n_n9255, n4191_1, preset, n3816_1 }; + assign n4831 = 32'd1426150400 >> { n4401_1, n_n8535, nsr3_14, ndn3_14, preset }; + assign n4836 = 16'h3120 >> { n_n8619, psv13_0_0_, preset, n4079 }; + assign n4841 = 32'd1426150400 >> { n4290, n_n8909, nsr3_14, ndn3_14, preset }; + assign n4846 = 16'h3120 >> { n_n7744, psv2_2_2_, preset, n4079 }; + assign n4851 = 16'h3120 >> { n_n9119, psv13_10_10_, preset, n4079 }; + assign n4856 = 16'h3120 >> { n_n7827, psv2_4_4_, preset, n4079 }; + assign n4861 = 16'h3120 >> { n_n8916, n_n8670, preset, n3824 }; + assign n4866 = 16'h3120 >> { n_n8729, n4301_1, preset, n4287 }; + assign n4871 = 32'd4286906286 >> { n4649, n5153, n_n8964, n4651_1, n_n9011 }; + assign n5153 = 4'h2 >> { n3755, n4416_1 }; + assign n4876 = 16'h3120 >> { n_n8779, psv38_6_6_, preset, n4079 }; + assign n4881 = 16'h3120 >> { n_n6980, n_n9273, preset, n3827 }; + assign n4886 = 16'h3120 >> { n_n7715, n_n9486, preset, n3819 }; + assign n4891 = 16'h3120 >> { n_n9067, psv26_13_13_, preset, n4079 }; + assign n4896 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9164, preset }; + assign n4901 = 16'h3120 >> { n_n7402, n_n9635, preset, n3824 }; + assign n4906 = 16'hf888 >> { n4103, n_n8938, n3803, n4104 }; + assign n4911 = 16'h3120 >> { n_n9046, n4356_1, preset, n3851_1 }; + assign n4916 = 32'd823336962 >> { n_n8789, n3853, n4217, preset, n3808 }; + assign n4921 = 16'h3120 >> { n_n9390, n4099, preset, n3810 }; + assign n4926 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7768, preset }; + assign n4931 = 16'h3120 >> { n_n9136, psv33_3_3_, preset, n4079 }; + assign n4936 = 16'h3120 >> { n_n8670, n4102, preset, n3819 }; + assign n4941 = 16'h3120 >> { n_n8644, n_n8543, preset, n3798 }; + assign n4946 = 32'd1426150400 >> { n3730, n_n9178, nsr3_14, ndn3_14, preset }; + assign n4951 = 32'd823336962 >> { n_n8188, n3853, n4217, preset, n3819 }; + assign n4956 = 16'h3120 >> { n_n7083, n4102, preset, n3824 }; + assign n4961 = 32'd1426150400 >> { n4441_1, n_n9344, nsr3_14, ndn3_14, preset }; + assign n4966 = 16'h3120 >> { n_n7366, n_n9613, preset, n3798 }; + assign n4971 = 16'h3120 >> { n_n8361, n_n9611, preset, n3798 }; + assign n4976 = 8'h54 >> { n_n9228, n3818, preset }; + assign n4981 = 16'h3120 >> { n_n9402, n4099, preset, n3828 }; + assign n4986 = 8'h54 >> { n_n8510, n3835, preset }; + assign n4991 = 16'hf888 >> { n4212, n_n8881, n4106_1, n4213 }; + assign n4996 = 16'h3120 >> { n_n9404, n4099, preset, n3850 }; + assign n5001 = 16'h3120 >> { n_n9424, n_n7346, preset, n3798 }; + assign n5006 = 64'h88f888f8ffff88f8 >> { n4335, n4183, n3758, n4416_1, n4415, n_n9031 }; + assign n5011 = 32'd4009688830 >> { nen3_34, nak3_13, nsr3_37, pdn, preset }; + assign n5016 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8197, preset }; + assign n5021 = 16'h3120 >> { n_n8468, n4242, preset, n3819 }; + assign n5026 = 16'h3120 >> { n_n7121, n_n7626, preset, n3798 }; + assign n5031 = 16'h3120 >> { n_n7511, psv33_0_0_, preset, n4079 }; + assign n5036 = 16'h1110 >> { ndn3_42, ndn3_44, preset, ngfdn_3 }; + assign n5041 = 16'h3120 >> { n_n9322, psv26_1_1_, preset, n4079 }; + assign n5046 = 32'd1426150400 >> { n4409, n_n7682, nsr3_35, ndn3_35, preset }; + assign n5051 = 16'h3120 >> { n_n9603, psv26_7_7_, preset, n4079 }; + assign n5056 = 16'h1110 >> { nlc1_2, nsr1_2, preset, pdn }; + assign n5061 = 16'h3120 >> { n_n8408, psv18_12_12_, preset, n4079 }; + assign n5066 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8577, preset }; + assign n5071 = 8'h54 >> { n_n7079, n3819, preset }; + assign n5076 = 16'hf888 >> { n4212, n_n8828, n4102, n4213 }; + assign n5081 = 32'd1426150400 >> { n4441_1, n_n9340, nsr3_23, ndn3_23, preset }; + assign n5086 = 16'h3120 >> { n_n8586, psv18_10_10_, preset, n4079 }; + assign n5091 = 32'd321978912 >> { n_n7901, n4007, n4061_1, preset, n3808 }; + assign n5096 = 16'h3120 >> { n_n8628, n4191_1, preset, n3836_1 }; + assign n5101 = 64'hea48ea48ffffea48 >> { n3751_1, n4416_1, n4415, n4333, n4183, n_n8869 }; + assign n5106 = 32'd321978912 >> { n_n7710, n4007, n4061_1, preset, n3851_1 }; + assign n5111 = 64'h88f888f8ffff88f8 >> { n4336_1, n4183, n3775, n4416_1, n4415, n_n8993 }; + assign n5116 = 64'h1313133102020220 >> { n_n9586, n4243, n4244, n4381_1, preset, n3816_1 }; + assign n5121 = 32'd321978912 >> { n_n8852, n4007, n4061_1, preset, n3843 }; + assign n5126 = 16'h3120 >> { n_n8583, n4242, preset, n4287 }; + assign n5131 = 16'h3120 >> { n_n8011, pinp_0_0_, preset, n4079 }; + assign n5136 = 8'h54 >> { n_n7717, n3798, preset }; + assign n5141 = 32'd1426150400 >> { n4368, n_n8326, ndn3_37, nsr3_37, preset }; + assign n5146 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9163, preset }; + assign n5151 = 32'd1426150400 >> { n4349, n_n8344, nsr3_13, ndn3_13, preset }; + assign n5156 = 16'h3120 >> { n_n8296, n4301_1, preset, n3812 }; + assign n5161 = 16'h3120 >> { n_n8116, psv39_10_10_, preset, n4079 }; + assign n5166 = 16'h3120 >> { n_n8267, psv33_12_12_, preset, n4079 }; + assign n5171 = 16'h3120 >> { n_n7686, n4191_1, preset, n3838 }; + assign n5176 = 32'd1426150400 >> { n4397, n_n9061, nsr3_38, ndn3_38, preset }; + assign n5181 = 64'h1313133102020220 >> { n_n9338, n4027, n4052, n4324, preset, n3843 }; + assign n5186 = 16'h3120 >> { n_n7688, psv26_10_10_, preset, n4079 }; + assign n5191 = 32'd1426150400 >> { n4200, n_n9081, nsr3_38, ndn3_38, preset }; + assign n5196 = 16'h3120 >> { n_n6910, n_n9239, preset, n3824 }; + assign n5201 = 32'd823336962 >> { n_n8727, n3853, n4217, preset, n4287 }; + assign n5206 = 16'h3120 >> { n_n7674, n_n9237, preset, n3824 }; + assign n5211 = 8'h54 >> { n_n7330, n3798, preset }; + assign n5216 = 16'h3120 >> { n_n8966, psv18_8_8_, preset, n4079 }; + assign n5221 = 32'd1426346240 >> { n_n8256, n_n7843, ndn3_50, ngfdn_3, preset }; + assign n5226 = 64'hffffaaeaffff8848 >> { n4415, n5225, n_n8631, n4418, n4183, n_n8847 }; + assign n5225 = 4'h2 >> { n3782, n4416_1 }; + assign n5231 = 16'h3120 >> { n_n9376, n_n8436, preset, n3818 }; + assign n5236 = 16'h3120 >> { n_n7553, n4187, preset, n3808 }; + assign n5241 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9292, preset }; + assign n5246 = 16'h3120 >> { n_n7464, n4240, preset, n3813 }; + assign n5251 = 16'h3120 >> { n_n8146, n_n8024, preset, n3819 }; + assign n5256 = 16'h3120 >> { n_n8439, n_n7757, preset, n3819 }; + assign n5261 = 32'd1426150400 >> { n3730, n_n9498, nsr3_13, ndn3_13, preset }; + assign n5266 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8118, preset }; + assign n5271 = 16'h3120 >> { n_n9452, n4102, preset, n3798 }; + assign n5276 = 16'h3120 >> { n_n9239, n4187, preset, n3819 }; + assign n5281 = 16'h3120 >> { n_n9237, n4301_1, preset, n3819 }; + assign n5286 = 32'd1426150400 >> { n3730, n_n9488, nsr3_35, ndn3_35, preset }; + assign n5291 = 8'h01 >> { n5239, preset, ngfdn_3 }; + assign n5239 = 32'd357893445 >> { preset_0_0_, n_n7476, nsr1_2, nlc1_2, ndn3_2 }; + assign n5296 = 32'd1426150400 >> { n4397, n_n9522, nsr3_23, ndn3_23, preset }; + assign n5301 = 16'h3120 >> { n_n9313, n4356_1, preset, n3822 }; + assign n5306 = 16'h3120 >> { n_n7435, n_n7927, preset, n3819 }; + assign n5311 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n8665, preset }; + assign n5316 = 16'h3120 >> { n_n9593, n3803, preset, n3822 }; + assign n5321 = 16'h3120 >> { n_n8303, n_n8957, preset, n3835 }; + assign n5326 = 16'h3120 >> { n_n7022, n_n8959, preset, n3835 }; + assign n5331 = 16'h3120 >> { n_n9173, n4106_1, preset, n3809 }; + assign n5336 = 16'h3120 >> { n_n9261, n3803, preset, n3809 }; + assign n5341 = 8'h54 >> { n_n7150, n3835, preset }; + assign n5346 = 64'h1313133102020220 >> { n_n9455, n4027, n4052, n4324, preset, n3809 }; + assign n5351 = 16'h3120 >> { n_n8371, n_n9452, preset, n3835 }; + assign n5356 = 32'd4009688830 >> { ndn3_17, nak3_13, nsr3_20, pdn, preset }; + assign n5361 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8271, preset }; + assign n5366 = 16'h3120 >> { n_n9542, n4242, preset, n3798 }; + assign n5371 = 64'h1313133102020220 >> { n_n7444, n4243, n4244, n4381_1, preset, n3824 }; + assign n5376 = 16'h1110 >> { ndn3_40, ndn3_39, preset, ngfdn_3 }; + assign n5381 = 16'h3120 >> { n_n7130, n_n7527, preset, n3818 }; + assign n5386 = 64'h1313133102020220 >> { n_n9347, n4027, n4052, n4324, preset, n3808 }; + assign n5391 = 16'h3120 >> { n_n8102, n_n9542, preset, n3835 }; + assign n5396 = 16'h3120 >> { n_n9225, psv38_13_13_, preset, n4079 }; + assign n5401 = 16'h3120 >> { n_n8462, n4106_1, preset, n3816_1 }; + assign n5406 = 16'h3120 >> { n_n8088, psv38_12_12_, preset, n4079 }; + assign n5411 = 16'h3120 >> { n_n9026, n_n7236, preset, n3827 }; + assign n5416 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9289, preset }; + assign n5421 = 16'h3120 >> { n_n7661, n4102, preset, n3828 }; + assign n5426 = 16'h3120 >> { n_n8108, pinp_12_12_, preset, n4079 }; + assign n5431 = 8'h54 >> { n_n8921, n3824, preset }; + assign n5436 = 16'h3120 >> { n_n7859, n4081_1, preset, n3822 }; + assign n5441 = 32'd1426150400 >> { n4409, n_n7732, nsr3_30, ndn3_30, preset }; + assign n5446 = 16'h3120 >> { n_n7956, psv39_8_8_, preset, n4079 }; + assign n5451 = 16'h3120 >> { n_n9520, n4219, preset, n3827 }; + assign n5456 = 16'h3120 >> { n_n7666, n4191_1, preset, n3851_1 }; + assign n5461 = 16'h3120 >> { n_n7678, n_n7862, preset, n3835 }; + assign n5466 = 32'd1426150400 >> { n4290, n_n7846, nsr3_23, ndn3_23, preset }; + assign n5471 = 16'hf888 >> { n4202, n_n8280, n4219, n4203 }; + assign n5476 = 32'd1426150400 >> { n4292, n_n8841, nsr3_23, ndn3_23, preset }; + assign n5481 = 8'h54 >> { n_n7336, n3818, preset }; + assign n5486 = 16'h3120 >> { n_n8226, n4081_1, preset, n4287 }; + assign n5491 = 16'hf888 >> { n4202, n_n8151, n4191_1, n4203 }; + assign n5496 = 16'h3120 >> { n_n7644, pinp_6_6_, preset, n4079 }; + assign n5501 = 16'h3120 >> { n_n8770, psv2_0_0_, preset, n4079 }; + assign n5506 = 8'h54 >> { n_n8423, n3827, preset }; + assign n5511 = 32'd321978912 >> { n_n7763, n4007, n4061_1, preset, n3828 }; + assign n5516 = 32'd1426150400 >> { n4292, n_n9525, nsr3_14, ndn3_14, preset }; + assign n5521 = 16'h3120 >> { n_n8033, psv18_0_0_, preset, n4079 }; + assign n5526 = 16'h3120 >> { n_n7881, psv2_6_6_, preset, n4079 }; + assign n5531 = 16'h3120 >> { n_n7815, psv13_12_12_, preset, n4079 }; + assign n5536 = 16'h3120 >> { n_n9232, psv18_4_4_, preset, n4079 }; + assign n5541 = 16'h3120 >> { n_n7792, n4081_1, preset, n3814 }; + assign n5546 = 16'h3120 >> { n_n9563, n4187, preset, n3814 }; + assign n5551 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n8672, preset }; + assign n5556 = 16'h3120 >> { n_n7346, n4102, preset, n3813 }; + assign n5561 = 32'd1426150400 >> { n4368, n_n7949, nsr3_38, ndn3_38, preset }; + assign n5566 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8756, preset }; + assign n5571 = 16'h3120 >> { n_n8641, n4102, preset, n3808 }; + assign n5576 = 16'h3120 >> { n_n8192, psv26_15_15_, preset, n4079 }; + assign n5581 = 32'd823336962 >> { n_n8058, n3853, n4217, preset, n3826_1 }; + assign n5586 = 64'h88f888f8ffff88f8 >> { n4329, n4183, n3745, n4416_1, n4415, n_n8561 }; + assign n5591 = 16'h4454 >> { ndn3_50, ngfdn_3, n_n9306, preset }; + assign n5596 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9165, preset }; + assign n5601 = 16'h3120 >> { n_n8850, n_n9573, preset, n3818 }; + assign n5606 = 32'd321978912 >> { n_n9210, n4007, n4061_1, preset, n3812 }; + assign n5611 = 32'd570565154 >> { preset_0_0_, nlc1_2, nsr1_2, preset, ndn2_2 }; + assign n5616 = 16'hf888 >> { n4202, n_n7342, n4102, n4203 }; + assign n5621 = 16'h3120 >> { n_n8051, psv26_6_6_, preset, n4079 }; + assign n5626 = 16'h3120 >> { n_n7136, n4301_1, preset, n3798 }; + assign n5631 = 16'h3120 >> { n_n9348, psv33_9_9_, preset, n4079 }; + assign n5636 = 8'h54 >> { n_n9006, n3819, preset }; + assign n5641 = 32'd1426150400 >> { n4397, n_n7653, nsr3_20, ndn3_20, preset }; + assign n5646 = 8'h54 >> { n_n7905, n3819, preset }; + assign n5651 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9166, preset }; + assign n5656 = 8'h54 >> { n_n7065, n3819, preset }; + assign n5661 = 16'h3120 >> { n_n9490, n4106_1, preset, n3822 }; + assign n5666 = 8'h54 >> { n_n7024, n3835, preset }; + assign n5671 = 8'h54 >> { n_n7586, n3818, preset }; + assign n5676 = 16'h3120 >> { n_n8416, psv39_9_9_, preset, n4079 }; + assign n5681 = 16'hf888 >> { n4212, n_n8937, n3803, n4213 }; + assign n5686 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8141, preset }; + assign n5691 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7853, preset }; + assign n5696 = 8'h54 >> { n_n8121, n3835, preset }; + assign n5701 = 16'h3120 >> { n_n9604, psv13_7_7_, preset, n4079 }; + assign n5706 = 16'h3120 >> { n_n9496, n4106_1, preset, n3837 }; + assign n5711 = 8'h54 >> { n_n8195, n3819, preset }; + assign n5716 = 32'd321978912 >> { n_n9516, n4007, n4061_1, preset, n3810 }; + assign n5721 = 16'h3120 >> { n_n9077, n4242, preset, n3851_1 }; + assign n5726 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9436, preset }; + assign n5731 = 16'h3120 >> { n_n9051, n4356_1, preset, n3814 }; + assign n5736 = 16'h3120 >> { n_n7664, n4191_1, preset, n3809 }; + assign n5741 = 16'hea48 >> { n4174, n5330, n4183, n_n8419 }; + assign n5330 = 16'h99a9 >> { n4163, n_n8354, n4115, n4167 }; + assign n5746 = 32'd1426150400 >> { n4374, n_n7874, nsr3_35, ndn3_35, preset }; + assign n5751 = 16'h3120 >> { n_n9133, n4099, preset, n3812 }; + assign n5756 = 32'd1426150400 >> { n4207, n_n9392, nsr3_38, ndn3_38, preset }; + assign n5761 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7770, preset }; + assign n5766 = 16'h1110 >> { ndn3_32, ndn3_29, ngfdn_3, preset }; + assign n5771 = 16'h3120 >> { n_n7601, n4301_1, preset, n3851_1 }; + assign n5776 = 16'h3120 >> { n_n8206, n4106_1, preset, n3798 }; + assign n5781 = 64'h1313133102020220 >> { n_n7927, n4243, n4244, n4381_1, preset, n3835 }; + assign n5786 = 16'h3120 >> { n_n9606, psv2_7_7_, preset, n4079 }; + assign n5791 = 32'd1426346240 >> { n_n9028, n_n7111, ndn3_50, ngfdn_3, preset }; + assign n5796 = 16'h3120 >> { n_n9269, n3803, preset, n3808 }; + assign n5801 = 4'h1 >> { preset, nsr3_38 }; + assign n5806 = 16'h3120 >> { n_n7886, psv18_13_13_, preset, n4079 }; + assign n5811 = 16'h3120 >> { n_n9179, n4106_1, preset, n3812 }; + assign n5816 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9357, preset }; + assign n5821 = 16'h3120 >> { n_n9594, psv18_7_7_, preset, n4079 }; + assign n5826 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7628, preset }; + assign n5831 = 8'h54 >> { n_n8454, n3824, preset }; + assign n5836 = 4'h1 >> { preset, nsr3_20 }; + assign n5841 = 32'd1426150400 >> { n4409, n_n9505, ndn3_37, nsr3_37, preset }; + assign n5846 = 16'h1101 >> { nen3_34, nsr3_35, preset, ngfdn_3 }; + assign n5851 = 64'h1313133102020220 >> { n_n9632, n4243, n4244, n4381_1, preset, n3819 }; + assign n5856 = 16'h3120 >> { n_n7076, n_n8462, preset, n3827 }; + assign n5861 = 16'h3120 >> { n_n9262, psv38_7_7_, preset, n4079 }; + assign n5866 = 16'h3120 >> { n_n9048, n4356_1, preset, n3826_1 }; + assign n5871 = 64'h4444444444445444 >> { ndn2_2, nlc1_2, nsr1_2, preset_0_0_, n_n9578, preset }; + assign n5876 = 16'h3120 >> { n_n8135, n4187, preset, n3810 }; + assign n5881 = 16'h1110 >> { ndn3_25, ndn3_26, preset, ngfdn_3 }; + assign n5886 = 16'h3120 >> { n_n7500, n_n9460, preset, n3827 }; + assign n5891 = 16'h3120 >> { n_n6974, n4219, preset, n3798 }; + assign n5896 = 8'h54 >> { n_n8605, n3824, preset }; + assign n5901 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9296, preset }; + assign n5906 = 16'h3120 >> { n_n7156, n_n8609, preset, n3819 }; + assign n5911 = 32'd1426150400 >> { n4441_1, n_n7920, nsr3_38, ndn3_38, preset }; + assign n5916 = 16'h3120 >> { n_n8895, n_n7570, preset, n3818 }; + assign n5921 = 64'h1313133102020220 >> { n_n8991, n4027, n4052, n4324, preset, n3813 }; + assign n5926 = 16'h3120 >> { n_n8139, psv38_14_14_, preset, n4079 }; + assign n5931 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9275, preset }; + assign n5936 = 16'h3120 >> { n_n7203, n_n9125, preset, n3824 }; + assign n5941 = 32'd1426150400 >> { n3796_1, n_n9590, nsr3_38, ndn3_38, preset }; + assign n5946 = 32'd1426346240 >> { n_n9570, n_n7344, ndn3_50, ngfdn_3, preset }; + assign n5951 = 16'h3120 >> { n_n6976, psv18_9_9_, preset, n4079 }; + assign n5956 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7629, preset }; + assign n5966 = 16'h3120 >> { n_n7862, n4356_1, preset, n3798 }; + assign n5971 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9013, preset }; + assign n5976 = 32'd1426346240 >> { n_n9282, n_n7288, ndn3_50, ngfdn_3, preset }; + assign n5981 = 32'd1426150400 >> { n4349, n_n8078, nsr3_35, ndn3_35, preset }; + assign n5986 = 32'd321978912 >> { n_n7334, n4007, n4061_1, preset, n3813 }; + assign n5991 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n7704, preset }; + assign n5996 = 32'd1426150400 >> { n4292, n_n7788, ndn3_37, nsr3_37, preset }; + assign n6001 = 16'h3120 >> { n_n8526, n4102, preset, n3851_1 }; + assign n6006 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n9556, preset }; + assign n6011 = 64'h1313133102020220 >> { n_n9345, n4027, n4052, n4324, preset, n3812 }; + assign n6016 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8447, preset }; + assign n6021 = 16'hf888 >> { n4103, n_n7485, n4301_1, n4104 }; + assign n6026 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8570, preset }; + assign n6031 = 32'd4286743170 >> { n4103, n_n7453, n4217, n3853, n4104 }; + assign n6036 = 32'd1426150400 >> { n4401_1, n_n7928, nsr3_35, ndn3_35, preset }; + assign n6041 = 64'h4444444444440444 >> { ndn2_2, nlc1_2, preset_0_0_, nsr1_2, n_n8646, preset }; + assign n6046 = 16'h3120 >> { n_n9405, psv26_3_3_, preset, n4079 }; + assign n6051 = 16'h3120 >> { n_n8948, n4191_1, preset, n3818 }; + assign n6056 = 16'h3120 >> { n_n9131, n4099, preset, n3826_1 }; + assign n6061 = 8'h54 >> { n_n8216, n3824, preset }; + assign n6066 = 16'h3120 >> { n_n9177, n4106_1, preset, n3826_1 }; + assign n6071 = 16'h3120 >> { n_n7844, n4219, preset, n3809 }; + assign n6076 = 16'h3120 >> { n_n8811, n4099, preset, n4287 }; + assign n6081 = 16'h3120 >> { n_n9145, n_n9629, preset, n3818 }; + assign n6086 = 16'h3120 >> { n_n8428, n_n9333, preset, n3824 }; + assign n6091 = 16'h3120 >> { n_n8858, n4106_1, preset, n3813 }; + assign n6096 = 16'h3120 >> { n_n8580, n4242, preset, n3810 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act b/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act new file mode 100644 index 000000000..ceec874ae --- /dev/null +++ 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0.997600 0.007522 +n595 0.988600 0.000011 +n596 0.996400 0.000017 +n597 0.988600 0.000020 +n598 0.989600 0.000022 +n599 0.953800 0.082248 +o_9_ 0.124600 0.001838 +n601 0.957600 0.000275 +n602 0.990000 0.000025 +o_1_ 0.141200 0.001714 diff --git a/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif b/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif new file mode 100644 index 000000000..8a3055407 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif @@ -0,0 +1,1775 @@ +# Benchmark "ex1010" written by ABC on Tue Mar 12 09:27:59 2019 +.model ex1010 +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ +.names n24 n31 n30 n28 n27 n29 n23 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n26 n25 n24 +11 1 +.names i_7_ i_6_ i_4_ i_3_ i_5_ i_8_ n25 +110000 1 +.names i_0_ i_1_ i_9_ i_2_ n26 +1100 1 +.names i_2_ i_1_ i_0_ i_9_ n27 +1110 1 +.names i_4_ i_3_ i_7_ i_6_ i_5_ i_8_ n28 +111100 1 +.names i_8_ i_9_ i_6_ i_7_ n29 +1110 1 +.names i_4_ i_0_ i_5_ i_3_ i_1_ i_2_ n30 +111000 1 +.names i_4_ i_3_ i_5_ i_1_ i_0_ i_2_ n31 +111000 1 +.names n36 n37 n35 n34 n33 n32 +11--- 0 +--111 0 +.names i_6_ i_7_ i_8_ n33 +110 1 +.names i_1_ i_9_ i_0_ i_2_ n34 +1000 1 +.names i_5_ i_3_ i_4_ n35 +110 1 +.names i_2_ i_9_ i_1_ i_0_ n36 +1000 1 +.names i_4_ i_3_ i_5_ i_8_ i_7_ i_6_ n37 +111110 1 +.names i_8_ i_7_ i_9_ i_6_ n38 +1110 1 +.names i_4_ i_0_ i_5_ i_1_ i_3_ i_2_ n39 +111100 1 +.names i_4_ i_7_ i_5_ i_6_ i_3_ i_8_ n40 +111100 1 +.names i_0_ i_2_ i_9_ i_1_ n41 +1100 1 +.names n51 n50 n49 n47 n43 n48 n42 +0000-- 1 +000-1- 1 +---0-0 1 +----10 1 +.names n46 n45 n44 n43 +000 1 +.names i_4_ i_3_ i_5_ i_1_ i_0_ i_2_ n44 +111111 1 +.names i_5_ i_0_ i_4_ i_3_ i_1_ i_2_ n45 +110000 1 +.names i_2_ i_1_ i_4_ i_3_ i_5_ i_0_ n46 +110000 1 +.names i_9_ i_8_ i_7_ i_6_ n47 +1000 1 +.names i_8_ i_9_ i_7_ i_6_ n48 +1100 1 +.names i_2_ i_4_ i_3_ i_5_ i_1_ i_0_ n49 +100000 1 +.names i_0_ i_3_ i_4_ i_5_ i_1_ i_2_ n50 +110000 1 +.names i_4_ i_0_ i_2_ i_1_ i_3_ i_5_ n51 +111100 1 +.names i_3_ i_4_ i_5_ i_1_ i_0_ i_2_ n52 +100000 1 +.names i_4_ i_3_ i_1_ i_5_ i_0_ i_2_ n53 +111000 1 +.names n58 n38 n40 n57 n56 n55 n54 +11---- 0 +--11-- 0 +----11 0 +.names i_6_ i_9_ i_8_ i_7_ n55 +1100 1 +.names i_2_ i_3_ i_5_ i_1_ i_0_ i_4_ n56 +111110 1 +.names i_0_ i_9_ i_1_ i_2_ n57 +1000 1 +.names i_4_ i_3_ i_0_ i_2_ i_5_ i_1_ n58 +111100 1 +.names i_9_ i_7_ i_6_ i_8_ n59 +1110 1 +.names n61 n65 n66 n60 +10- 1 +1-0 1 +.names n62 n29 n63 n38 n64 n57 n61 +11---- 0 +--11-- 0 +----11 0 +.names i_4_ i_3_ i_5_ i_2_ i_0_ i_1_ n62 +111110 1 +.names i_4_ i_2_ i_3_ i_5_ i_1_ i_0_ n63 +110000 1 +.names i_6_ i_4_ i_3_ i_5_ i_8_ i_7_ n64 +100000 1 +.names i_2_ i_1_ i_9_ i_0_ n65 +1100 1 +.names i_5_ i_7_ i_4_ i_3_ i_8_ i_6_ n66 +110000 1 +.names i_8_ i_7_ i_6_ n67 +100 1 +.names i_8_ i_7_ i_6_ i_9_ n68 +1111 1 +.names i_4_ i_3_ i_0_ i_1_ i_5_ i_2_ n69 +111100 1 +.names i_4_ i_3_ i_2_ i_5_ i_1_ i_0_ n70 +111000 1 +.names n72 n27 n73 n59 n74 n57 n71 +11---- 0 +--11-- 0 +----11 0 +.names i_7_ i_3_ i_4_ i_5_ i_8_ i_6_ n72 +110000 1 +.names i_4_ i_3_ i_5_ i_1_ i_0_ i_2_ n73 +111100 1 +.names i_6_ i_3_ i_5_ i_8_ i_4_ i_7_ n74 +111100 1 +.names n76 n55 n77 n47 n75 +11-- 0 +--11 0 +.names i_0_ i_2_ i_4_ i_3_ i_5_ i_1_ n76 +110000 1 +.names i_1_ i_4_ i_3_ i_5_ i_0_ i_2_ n77 +100000 1 +.names n80 n27 n38 n79 n78 +11-- 0 +--11 0 +.names i_0_ i_3_ i_5_ i_4_ i_1_ i_2_ n79 +111000 1 +.names i_4_ i_3_ i_5_ i_6_ i_7_ i_8_ n80 +111110 1 +.names i_4_ i_8_ i_6_ i_3_ i_5_ i_7_ n81 +111000 1 +.names i_1_ i_3_ i_0_ i_4_ i_5_ i_2_ n82 +111000 1 +.names n90 n84 n88 n34 n37 n83 +1100- 1 +110-0 1 +.names n87 n36 n46 n48 n85 n86 n84 +11---- 0 +--11-- 0 +----11 0 +.names i_9_ i_1_ i_0_ i_2_ n85 +0000 1 +.names i_4_ i_3_ i_8_ i_5_ i_7_ i_6_ n86 +111000 1 +.names i_6_ i_3_ i_4_ i_5_ i_8_ i_7_ n87 +110000 1 +.names n89 n38 n88 +11 1 +.names i_4_ i_2_ i_5_ i_1_ i_0_ i_3_ n89 +111110 1 +.names n93 n27 n91 n92 n90 +11-- 0 +--11 0 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n425 n240 n203 n48 n26 n423 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n98 n29 n91 n191 n424 +11-- 0 +--11 0 +.names n28 n65 n57 n167 n67 n425 +11--- 0 +--111 0 +.names n434 n432 n431 n430 n428 n427 n426 +111110 1 +.names n240 n34 n427 +11 1 +.names n36 n429 n59 n182 n428 +10-- 0 +--11 0 +.names i_4_ i_7_ i_5_ i_8_ i_6_ i_3_ n429 +11011- 0 +1101-0 0 +111010 0 +.names n195 n131 n55 n81 i_9_ n430 +111-- 0 +1--10 0 +.names n91 n39 n105 n47 n92 n48 n431 +11---- 0 +--11-- 0 +----11 0 +.names n27 n433 n65 n140 n68 n259 n432 +10---- 0 +--11-- 0 +----11 0 +.names i_5_ i_3_ i_7_ i_4_ i_6_ i_8_ n433 +110110 0 +111000 0 +.names n56 n29 n203 n59 n55 n53 n434 +11---- 0 +--11-- 0 +----11 0 +.names n436 n342 n269 n435 +111 1 +.names n440 n439 n438 n437 n352 n257 n436 +111111 1 +.names n50 n38 n70 n47 n437 +11-- 0 +--11 0 +.names n145 n36 n40 n65 n438 +11-- 0 +--11 0 +.names n57 n119 n233 n34 n159 n439 +11--- 0 +--111 0 +.names n72 n26 n112 n48 n440 +11-- 0 +--11 0 +.names n442 n182 n29 n34 n173 n441 +0---- 0 +-11-- 0 +---11 0 +.names n85 n179 n167 n59 n166 n442 +11--- 0 +--111 0 +.names n41 n25 n48 n195 i_3_ i_5_ n443 +11---- 0 +--1100 0 +.names n48 n52 n45 n444 +11- 1 +1-1 1 +.names n137 n446 n449 n447 n448 n27 n445 +10001- 1 +1000-0 1 +.names n34 n239 n119 n213 n446 +0--- 0 +-000 0 +.names n26 n147 n93 n151 n447 +0--- 0 +-000 0 +.names n96 n135 n134 n448 +000 1 +.names n36 n96 n81 n299 n154 n449 +0---- 0 +-0000 0 +.names n456 n454 n451 n450 +111 1 +.names n453 n300 n452 n366 n168 n68 n451 +10000- 1 +1000-0 1 +.names n153 n48 n452 +11 1 +.names n36 n136 n35 n34 n33 n453 +11--- 0 +--111 0 +.names n331 n455 n40 n230 n68 n26 n454 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n62 n59 n85 n81 n455 +11-- 0 +--11 0 +.names n105 n38 n59 n89 n181 n48 n456 +11---- 0 +--11-- 0 +----11 0 +.names n315 n314 n458 n398 n217 n457 +11111 1 +.names n459 n461 n460 n69 n55 n59 n458 +0000-- 1 +000-00 1 +.names n91 n182 n101 n233 n459 +11-- 1 +1-11 1 +.names n38 n191 n35 n116 n460 +11-- 1 +1-11 1 +.names n47 n155 i_2_ n167 i_1_ n461 +11--- 1 +1-110 1 +.names n468 n466 n465 n560 n436 n234 n462 +111111 1 +.names n91 n230 n38 n82 n205 n463 +1--1- 0 +1---1 0 +-11-- 0 +.names n188 n27 n73 n55 n65 n198 n464 +11---- 0 +--11-- 0 +----11 0 +.names n231 n248 n150 n109 n85 n29 n465 +1000-- 1 +100-0- 1 +1--0-0 1 +1---00 1 +.names n467 n84 n64 n190 n48 n34 n466 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n147 n36 n240 n41 n467 +11-- 0 +--11 0 +.names n469 n471 n470 n215 n91 n29 n468 +1110-- 1 +111-00 1 +.names n103 n38 n59 n110 n469 +11-- 0 +--11 0 +.names n48 n205 n67 n131 n34 n470 +11--- 0 +--111 0 +.names n37 n27 n72 n65 n471 +11-- 0 +--11 0 +.names n29 n203 n38 n195 n131 n472 +11--- 0 +--111 0 +.names n389 n474 n91 n268 n132 n346 n473 +100--- 1 +10-000 1 +.names n68 n62 n52 n143 n63 n474 +0---- 0 +-0000 0 +.names n67 i_5_ n65 i_4_ n475 +1110 1 +.names n477 n153 n38 n62 n47 n476 +0---- 0 +-11-- 0 +---11 0 +.names n273 n179 n27 n233 n159 n477 +11--- 0 +--111 0 +.names n479 n480 n124 n68 n50 n36 n478 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n41 n96 n239 n91 n155 n479 +11--- 0 +1-1-- 0 +---11 0 +.names n215 n47 n85 n146 n480 +11-- 0 +--11 0 +.names n456 n485 n482 n454 n451 n481 +11111 1 +.names n483 n373 n225 n68 n484 n55 n482 +1000-- 1 +100-1- 1 +10--10 1 +1--0-0 1 +.names n48 n89 n131 n195 n29 n483 +11--- 0 +--111 0 +.names n110 n101 n233 n484 +00- 1 +0-0 1 +.names n487 n486 n427 n488 n38 n215 n485 +10000- 1 +1000-0 1 +.names n91 n51 n45 n56 n486 +0--- 0 +-000 0 +.names n76 n55 n213 n85 n487 +11-- 0 +--11 0 +.names n41 n118 n219 n488 +11- 1 +1-1 1 +.names n208 n136 n68 n29 n185 n65 n489 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n85 n25 n169 n47 n226 n68 n490 +11---- 0 +--11-- 0 +----11 0 +.names i_5_ i_7_ i_3_ i_6_ i_4_ i_8_ n491 +011110 0 +100000 0 +111101 0 +.names n237 n140 n72 n492 +000 1 +.names n52 n29 n248 n38 n208 n85 n493 +11---- 0 +--11-- 0 +----11 0 +.names n182 n181 n132 n30 n55 n47 n494 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n180 n170 n162 n494 n45 n68 n495 +11110- 1 +1111-0 1 +.names n567 n126 n505 n501 n495 n498 o_0_ +111111 0 +.names n54 n39 n59 n38 n53 n52 n497 +100--- 1 +10--00 1 +1-00-- 1 +.names n42 n32 n23 n497 n40 n41 n498 +11110- 1 +1111-0 1 +.names n503 n71 n81 n69 n59 n36 n499 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n78 n75 n111 n68 n82 n70 n500 +1100-- 1 +110-00 1 +.names n106 n94 n83 n500 n60 n499 n501 +111111 1 +.names i_4_ i_5_ i_3_ i_2_ i_1_ i_0_ n502 +00-110 1 +100--- 1 +.names n502 i_4_ n68 n67 n65 n503 +101-- 0 +11-11 0 +.names i_1_ i_0_ i_2_ n97 n113 n25 n504 +010-1- 1 +0111-- 1 +100--1 1 +.names n120 n114 i_9_ n91 n52 n504 n505 +1110-- 1 +111-0- 1 +11-0-0 1 +11--00 1 +.names n154 n151 n152 n136 n36 n26 n506 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n155 n45 n150 n153 n91 n38 n507 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n156 n148 n507 n506 n52 n55 n508 +11110- 1 +1111-0 1 +.names n59 n195 n194 n79 n155 n91 n509 +111--- 0 +1--1-- 0 +1---1- 0 +-11--1 0 +.names n192 n50 n59 n29 n191 n55 n510 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n39 n192 n209 n37 n65 n47 n511 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n511 n128 n206 n204 n55 n143 n512 +11000- 1 +1100-0 1 +.names n286 n211 n512 n199 n41 n208 n513 +11110- 1 +1111-0 1 +.names n185 n117 n145 n37 n41 n48 n514 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n241 n142 n197 n113 n57 n34 n515 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n234 n227 n515 n569 n34 n140 n516 +11110- 1 +1111-0 1 +.names i_0_ i_1_ i_2_ n202 n241 n183 n517 +001-1- 1 +110--1 1 +1111-- 1 +.names n41 n151 n179 n65 n108 n518 +11--- 0 +1-1-- 0 +---11 0 +.names n254 n518 n256 n255 n517 i_9_ n519 +11000- 1 +1100-1 1 +.names n125 n36 n38 n103 n155 n91 n520 +11---- 0 +--11-- 0 +----11 0 +.names n259 n117 n57 n85 n239 n55 n521 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n260 n258 n520 n521 n27 n140 n522 +11110- 1 +1111-0 1 +.names n207 n48 n55 n132 n69 n59 n523 +11---- 0 +--11-- 0 +----11 0 +.names n523 n283 n284 n47 n203 n31 n524 +1100-- 1 +110-00 1 +.names n145 n118 n93 n73 n59 n27 n525 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n45 n205 n241 n152 n57 n29 n526 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n298 n297 n91 n195 n233 n131 n527 +100--- 1 +10-0-- 1 +10--00 1 +.names n527 n526 n153 n47 n101 n233 n528 +110-0- 1 +110--0 1 +11-0-- 1 +.names n340 n335 n336 n85 n339 n142 n529 +1110-- 1 +111-10 1 +.names n572 n321 n536 n307 n533 n578 o_3_ +111111 0 +.names n215 n185 n44 n175 n57 n59 n531 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n306 n531 n301 n305 n300 n247 n532 +111000 1 +.names n303 n532 n36 n239 n113 n533 +110-- 1 +11-00 1 +.names n315 n314 n29 n268 n207 n62 n534 +110--- 1 +11-000 1 +.names n143 n48 n55 n70 n192 n91 n535 +11---- 0 +--11-- 0 +----11 0 +.names n519 n318 n316 n157 n535 n534 n536 +111111 1 +.names n59 n182 n29 n46 n55 n346 n537 +11---- 0 +1----1 0 +-1--1- 0 +--11-- 0 +.names i_8_ i_7_ i_6_ n46 n346 n225 n538 +000--1 1 +0111-- 1 +100-1- 1 +.names n27 n125 n65 n152 n35 n67 n539 +11---- 0 +1---11 0 +--11-- 0 +.names n348 n539 n347 n538 n41 i_9_ n540 +1110-- 1 +111--0 1 +11-00- 1 +11--00 1 +.names n30 n89 n97 n66 n41 n29 n541 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n375 n56 n38 n68 n143 n92 n542 +000--- 1 +00--00 1 +0-00-- 1 +.names n290 n162 n589 n542 n543 +1111 1 +.names n299 n93 n63 n50 n47 n41 n544 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n419 n48 n225 n192 n73 n53 n545 +10---- 1 +1-0000 1 +.names n426 n423 n420 n418 n411 n322 n546 +111111 1 +.names n501 n550 n407 n546 n243 n545 o_6_ +111111 0 +.names n209 n27 n36 n108 n57 n125 n548 +11---- 0 +--11-- 0 +----11 0 +.names n415 n229 n548 n59 n117 n98 n549 +1110-- 1 +111-00 1 +.names n416 n412 n404 n549 n26 n208 n550 +11110- 1 +1111-0 1 +.names n443 n57 n208 n154 n118 n72 n551 +10---- 1 +1-0000 1 +.names n441 n408 n551 n65 n183 n552 +1110- 1 +111-0 1 +.names n457 n450 n445 n595 n435 n552 o_7_ +111111 0 +.names n259 n225 n63 n31 n55 n29 n554 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n299 n140 n57 n34 n35 n67 n555 +00--0- 1 +00---0 1 +0-0--- 1 +--00-- 1 +.names n472 n426 n402 n365 n47 n51 n556 +11110- 1 +1111-0 1 +.names n533 n505 n563 n462 n556 n555 o_8_ +111111 0 +.names i_6_ i_7_ i_5_ i_3_ i_4_ i_9_ n558 +001100 1 +101010 1 +11010- 1 +11---1 1 +.names i_9_ i_8_ n558 n207 n346 i_1_ n559 +011--0 1 +10--0- 1 +11-0-- 1 +1-0--- 1 +.names n464 n463 i_9_ n559 i_2_ i_0_ n560 +1100-- 1 +1111-- 1 +11-10- 1 +11-1-0 1 +.names i_0_ n147 n202 n193 n96 n37 n561 +01---- 1 +1-0000 1 +.names i_1_ i_0_ i_2_ i_9_ n561 n173 n562 +0100-1 0 +10001- 0 +11000- 0 +.names n478 n476 n562 n473 n287 n475 n563 +111110 1 +.names n176 n492 n145 n135 n36 n34 n564 +0100-- 1 +01---0 1 +0-000- 1 +----00 1 +.names n33 n167 n85 n27 n81 n35 n565 +111--- 0 +11-1-- 0 +1--1-1 0 +--1-1- 0 +.names n510 n509 n196 n189 n184 n186 n566 +111110 1 +.names n565 n566 n183 n193 n57 n27 n567 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n55 n74 n65 n41 n125 n56 n568 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n568 n236 n238 n88 n41 n164 n569 +11000- 1 +1100-0 1 +.names n27 n125 n139 n26 n67 n35 n570 +11---- 0 +1-1--- 0 +---111 0 +.names n226 n29 n36 n119 n91 n168 n571 +11---- 0 +--11-- 0 +----11 0 +.names n524 n570 n281 n280 n571 n282 n572 +111110 1 +.names n213 n209 n119 n87 n57 n41 n573 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n525 n296 n295 n48 n215 n132 n574 +1000-- 1 +100-00 1 +.names n573 n574 n34 n117 n29 n28 n575 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n68 n53 n122 n35 n116 n29 n576 +11---- 0 +1-1--- 0 +---111 0 +.names n30 n182 n76 n185 n47 n38 n577 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n529 n576 n337 n332 n577 n338 n578 +111110 1 +.names n27 n86 n57 n213 n67 n131 n579 +11---- 0 +1---11 0 +--11-- 0 +.names n537 n356 n283 n60 n41 n146 n580 +11110- 1 +1111-0 1 +.names n587 n513 n360 n341 n580 n579 o_4_ +111111 0 +.names i_2_ i_1_ i_0_ n80 n135 n198 n582 +100--1 1 +1101-- 1 +110-1- 1 +.names i_7_ i_6_ i_8_ i_9_ n101 n232 n583 +011-1- 1 +01-11- 1 +1011-1 1 +.names n349 n305 i_9_ n233 n583 n582 n584 +0010-- 1 +001-0- 1 +00-0-0 1 +00--00 1 +.names n80 n179 n173 n346 n29 n26 n585 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n541 n355 n354 n91 n226 n122 n586 +1000-- 1 +100-00 1 +.names n584 n585 n350 n586 n353 n587 +11110 1 +.names i_4_ i_1_ i_5_ i_0_ i_2_ i_3_ n588 +010101 1 +100001 1 +111001 1 +11111- 1 +.names n377 n376 i_0_ n588 n55 n91 n589 +000--0 1 +001-0- 1 +00-0-- 1 +.names n154 n34 n183 n36 n268 n68 n590 +11---- 0 +--11-- 0 +----11 0 +.names n544 n386 n590 n65 n239 n152 n591 +1110-- 1 +111-00 1 +.names n382 n380 n378 n591 n29 n51 n592 +11110- 1 +1111-0 1 +.names n44 n92 n183 n40 n41 n59 n593 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names n86 n65 n104 n68 n203 n91 n594 +11---- 0 +--11-- 0 +----11 0 +.names n554 n594 n393 n593 n444 n204 n595 +111100 1 +.names i_1_ i_0_ i_2_ i_9_ n491 n81 n596 +1000-1 0 +11000- 0 +.names n493 n490 n411 n258 n49 n59 n597 +11110- 1 +1111-0 1 +.names n596 n489 n188 n57 n85 n240 n598 +1100-- 1 +110--0 1 +11-00- 1 +.names n597 n564 n560 n367 n332 n293 n599 +111111 1 +.names n481 n387 n599 n216 n127 n598 o_9_ +111111 0 +.names n522 n519 n222 n217 n55 n77 n601 +11110- 1 +1111-0 1 +.names n514 n221 n216 n85 n188 n119 n602 +1110-- 1 +111-00 1 +.names n516 n513 n242 n602 n601 o_1_ +11111 0 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v b/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v new file mode 100644 index 000000000..9531854b4 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v @@ -0,0 +1,1176 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module ex1010(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_); + input i_0_; + input i_1_; + input i_2_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + input i_9_; + wire n100; + wire n101; + wire n102; + wire n103; + wire n104; + wire n105; + wire n106; + wire n107; + wire n108; + wire n109; + wire n110; + wire n111; + wire n112; + wire n113; + wire n114; + wire n115; + wire n116; + wire n117; + wire n118; + wire n119; + wire n120; + wire n121; + wire n122; + wire n123; + wire n124; + wire n125; + wire n126; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n23; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n24; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n25; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n26; + wire n260; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n27; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n28; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n29; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n30; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n31; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n32; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n33; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n34; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n35; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n36; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n37; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n377; + wire n378; + wire n379; + wire n38; + wire n380; + wire n381; + wire n382; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n39; + wire n390; + wire n391; + wire n392; + wire n393; + wire n394; + wire n395; + wire n396; + wire n397; + wire n398; + wire n399; + wire n40; + wire n400; + wire n401; + wire n402; + wire n403; + wire n404; + wire n405; + wire n406; + wire n407; + wire n408; + wire n409; + wire n41; + wire n410; + wire n411; + wire n412; + wire n413; + wire n414; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n42; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n427; + wire n428; + wire n429; + wire n43; + wire n430; + wire n431; + wire n432; + wire n433; + wire n434; + wire n435; + wire n436; + wire n437; + wire n438; + wire n439; + wire n44; + wire n440; + wire n441; + wire n442; + wire n443; + wire n444; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n45; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n455; + wire n456; + wire n457; + wire n458; + wire n459; + wire n46; + wire n460; + wire n461; + wire n462; + wire n463; + wire n464; + wire n465; + wire n466; + wire n467; + wire n468; + wire n469; + wire n47; + wire n470; + wire n471; + wire n472; + wire n473; + wire n474; + wire n475; + wire n476; + wire n477; + wire n478; + wire n479; + wire n48; + wire n480; + wire n481; + wire n482; + wire n483; + wire n484; + wire n485; + wire n486; + wire n487; + wire n488; + wire n489; + wire n49; + wire n490; + wire n491; + wire n492; + wire n493; + wire n494; + wire n495; + wire n497; + wire n498; + wire n499; + wire n50; + wire n500; + wire n501; + wire n502; + wire n503; + wire n504; + wire n505; + wire n506; + wire n507; + wire n508; + wire n509; + wire n51; + wire n510; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n52; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n53; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n54; + wire n540; + wire n541; + wire n542; + wire n543; + wire n544; + wire n545; + wire n546; + wire n548; + wire n549; + wire n55; + wire n550; + wire n551; + wire n552; + wire n554; + wire n555; + wire n556; + wire n558; + wire n559; + wire n56; + wire n560; + wire n561; + wire n562; + wire n563; + wire n564; + wire n565; + wire n566; + wire n567; + wire n568; + wire n569; + wire n57; + wire n570; + wire n571; + wire n572; + wire n573; + wire n574; + wire n575; + wire n576; + wire n577; + wire n578; + wire n579; + wire n58; + wire n580; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n587; + wire n588; + wire n589; + wire n59; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n598; + wire n599; + wire n60; + wire n601; + wire n602; + wire n61; + wire n62; + wire n63; + wire n64; + wire n65; + wire n66; + wire n67; + wire n68; + wire n69; + wire n70; + wire n71; + wire n72; + wire n73; + wire n74; + wire n75; + wire n76; + wire n77; + wire n78; + wire n79; + wire n80; + wire n81; + wire n82; + wire n83; + wire n84; + wire n85; + wire n86; + wire n87; + wire n88; + wire n89; + wire n90; + wire n91; + wire n92; + wire n93; + wire n94; + wire n95; + wire n96; + wire n97; + wire n98; + wire n99; + output o_0_; + output o_1_; + output o_2_; + output o_3_; + output o_4_; + output o_5_; + output o_6_; + output o_7_; + output o_8_; + output o_9_; + assign n23 = 64'h0001010100555555 >> { n29, n27, n28, n30, n31, n24 }; + assign n32 = 32'd125269879 >> { n33, n34, n35, n37, n36 }; + assign n122 = 64'h0000000000000080 >> { i_1_, i_3_, i_4_, i_5_, i_0_, i_2_ }; + assign n123 = 16'h0777 >> { n36, n74, n27, n124 }; + assign n124 = 64'h0000000000000008 >> { i_7_, i_8_, i_5_, i_3_, i_6_, i_4_ }; + assign n125 = 64'h0000000080000000 >> { i_4_, i_7_, i_8_, i_5_, i_3_, i_6_ }; + assign n126 = 16'h8000 >> { n127, n137, n508, n157 }; + assign n127 = 32'd8421504 >> { n136, n41, n133, n128, n130 }; + assign n128 = 16'h0777 >> { n129, n41, n38, n122 }; + assign n129 = 64'h0000000000000008 >> { i_6_, i_7_, i_8_, i_3_, i_5_, i_4_ }; + assign n130 = 32'd125269879 >> { n67, n26, n131, n132, n29 }; + assign n131 = 8'h02 >> { i_3_, i_4_, i_5_ }; + assign n33 = 8'h08 >> { i_8_, i_7_, i_6_ }; + assign n132 = 64'h0000000000000080 >> { i_2_, i_0_, i_3_, i_5_, i_1_, i_4_ }; + assign n133 = 64'h0000077707770777 >> { n65, n129, n134, n85, n57, n135 }; + assign n134 = 64'h0000000000000080 >> { i_6_, i_5_, i_3_, i_7_, i_8_, i_4_ }; + assign n135 = 64'h0000000000008000 >> { i_7_, i_3_, i_8_, i_5_, i_6_, i_4_ }; + assign n136 = 64'h0000000000000080 >> { i_6_, i_8_, i_4_, i_5_, i_3_, i_7_ }; + assign n137 = 64'h0008000800080808 >> { n40, n147, n27, n138, n141, n144 }; + assign n138 = 8'ha8 >> { n140, n139, n85 }; + assign n139 = 64'h0000000000000008 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n140 = 64'h0000000000008000 >> { i_3_, i_4_, i_8_, i_5_, i_6_, i_7_ }; + assign n141 = 64'h0000077707770777 >> { n55, n143, n38, n77, n34, n142 }; + assign n34 = 16'h0002 >> { i_2_, i_0_, i_9_, i_1_ }; + assign n142 = 64'h0000000000000002 >> { i_6_, i_8_, i_5_, i_3_, i_4_, i_7_ }; + assign n143 = 64'h0000000000000008 >> { i_0_, i_1_, i_3_, i_4_, i_2_, i_5_ }; + assign n144 = 64'h0000077707770777 >> { n91, n62, n145, n41, n36, n146 }; + assign n145 = 64'h0000000080000000 >> { i_3_, i_7_, i_8_, i_5_, i_6_, i_4_ }; + assign n146 = 64'h0000000000000008 >> { i_6_, i_7_, i_5_, i_3_, i_8_, i_4_ }; + assign n147 = 64'h0000000000000002 >> { i_6_, i_7_, i_5_, i_3_, i_4_, i_8_ }; + assign n148 = 16'h0777 >> { n70, n38, n26, n149 }; + assign n149 = 64'h0000000000000008 >> { i_7_, i_5_, i_3_, i_4_, i_8_, i_6_ }; + assign n150 = 64'h0000000000000080 >> { i_2_, i_0_, i_4_, i_5_, i_3_, i_1_ }; + assign n151 = 64'h0000000000000080 >> { i_8_, i_3_, i_4_, i_5_, i_7_, i_6_ }; + assign n35 = 8'h08 >> { i_4_, i_3_, i_5_ }; + assign n152 = 64'h0000000000008000 >> { i_6_, i_4_, i_8_, i_5_, i_3_, i_7_ }; + assign n153 = 64'h0000000080000000 >> { i_5_, i_0_, i_1_, i_2_, i_3_, i_4_ }; + assign n154 = 64'h0000000000000080 >> { i_8_, i_5_, i_3_, i_7_, i_6_, i_4_ }; + assign n155 = 64'h0000000000000080 >> { i_1_, i_5_, i_3_, i_0_, i_2_, i_4_ }; + assign n156 = 16'h0777 >> { n48, n79, n34, n40 }; + assign n157 = 64'h0008000800080808 >> { n86, n154, n41, n158, n160, n161 }; + assign n158 = 16'h8000 >> { n26, n159, i_5_, i_3_ }; + assign n159 = 8'h80 >> { i_6_, i_7_, i_8_ }; + assign n160 = 64'h0000077707770777 >> { n68, n155, n122, n48, n59, n143 }; + assign n161 = 64'hfbfffbfff9fdfbff >> { i_1_, n151, n139, i_9_, i_0_, i_2_ }; + assign n36 = 16'h0002 >> { i_0_, i_1_, i_9_, i_2_ }; + assign n162 = 64'h0002020200222222 >> { n38, n48, n169, n168, n163, n165 }; + assign n163 = 16'ha888 >> { n131, n67, n164, n57 }; + assign n164 = 64'h0000000000000080 >> { i_7_, i_8_, i_4_, i_5_, i_3_, i_6_ }; + assign n165 = 32'd125269879 >> { n91, n166, n167, n69, n29 }; + assign n166 = 8'h02 >> { i_2_, i_0_, i_1_ }; + assign n167 = 8'h02 >> { i_5_, i_4_, i_3_ }; + assign n168 = 64'h0000000000000080 >> { i_0_, i_3_, i_4_, i_5_, i_2_, i_1_ }; + assign n169 = 64'h0000000000000008 >> { i_2_, i_0_, i_1_, i_3_, i_5_, i_4_ }; + assign n170 = 64'h0000000200020002 >> { n142, n57, n177, n171, n174, n178 }; + assign n171 = 64'haaaa0880aaaa0800 >> { i_4_, n173, i_5_, i_3_, n172, n36 }; + assign n37 = 64'h0000000080000000 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n172 = 8'h02 >> { i_7_, i_8_, i_6_ }; + assign n173 = 64'h0000000000008000 >> { i_6_, i_5_, i_8_, i_7_, i_3_, i_4_ }; + assign n174 = 16'haaa8 >> { n176, n175, n134, n57 }; + assign n175 = 64'h0000000000000008 >> { i_6_, i_8_, i_5_, i_3_, i_7_, i_4_ }; + assign n176 = 64'h0000000000000080 >> { i_6_, i_5_, i_4_, i_7_, i_3_, i_8_ }; + assign n177 = 4'h8 >> { n48, n76 }; + assign n178 = 16'h0777 >> { n70, n59, n41, n179 }; + assign n179 = 64'h0000000000008000 >> { i_6_, i_3_, i_8_, i_5_, i_7_, i_4_ }; + assign n180 = 64'h77f77fff7fff7fff >> { n38, i_3_, n47, i_5_, n166, i_4_ }; + assign n181 = 64'h0000000000000080 >> { i_0_, i_1_, i_3_, i_5_, i_2_, i_4_ }; + assign n38 = 16'h0080 >> { i_6_, i_9_, i_7_, i_8_ }; + assign n182 = 64'h0000000000000080 >> { i_0_, i_5_, i_3_, i_2_, i_1_, i_4_ }; + assign n183 = 64'h0000000000000080 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n184 = 16'h0777 >> { n185, n91, n26, n175 }; + assign n185 = 64'h0000000000000008 >> { i_2_, i_0_, i_5_, i_3_, i_1_, i_4_ }; + assign n186 = 64'hff00fe00fe00fe00 >> { n67, n167, n65, n124, n187, n188 }; + assign n187 = 64'h0000000000008000 >> { i_5_, i_4_, i_8_, i_6_, i_3_, i_7_ }; + assign n188 = 64'h0000000080000000 >> { i_7_, i_6_, i_8_, i_5_, i_3_, i_4_ }; + assign n189 = 64'h0000077707770777 >> { n55, n190, n109, n36, n34, n72 }; + assign n190 = 64'h0000000080000000 >> { i_0_, i_2_, i_1_, i_5_, i_3_, i_4_ }; + assign n191 = 64'h0000000000008000 >> { i_0_, i_3_, i_1_, i_5_, i_2_, i_4_ }; + assign n39 = 64'h0000000000008000 >> { i_2_, i_3_, i_1_, i_5_, i_0_, i_4_ }; + assign n192 = 64'h0000000000000008 >> { i_0_, i_1_, i_5_, i_4_, i_3_, i_2_ }; + assign n193 = 64'h0000000000000080 >> { i_7_, i_5_, i_4_, i_6_, i_3_, i_8_ }; + assign n194 = 8'h80 >> { i_5_, i_3_, i_4_ }; + assign n195 = 8'h08 >> { i_2_, i_0_, i_1_ }; + assign n196 = 64'h0001010100ffffff >> { n41, n29, n73, n197, n198, n109 }; + assign n197 = 64'h0000000000000080 >> { i_6_, i_7_, i_3_, i_5_, i_8_, i_4_ }; + assign n198 = 64'h0000000080000000 >> { i_5_, i_7_, i_8_, i_6_, i_3_, i_4_ }; + assign n199 = 64'h0001010100111111 >> { n27, n59, n203, n149, n201, n200 }; + assign n200 = 4'h8 >> { n48, n104 }; + assign n201 = 4'h8 >> { n57, n202 }; + assign n40 = 64'h0000000000008000 >> { i_8_, i_3_, i_6_, i_5_, i_7_, i_4_ }; + assign n202 = 64'h0000000000000008 >> { i_6_, i_5_, i_3_, i_4_, i_8_, i_7_ }; + assign n203 = 64'h0000000000000008 >> { i_2_, i_1_, i_5_, i_3_, i_0_, i_4_ }; + assign n204 = 4'h8 >> { n47, n205 }; + assign n205 = 64'h0000000000000008 >> { i_2_, i_0_, i_1_, i_4_, i_3_, i_5_ }; + assign n206 = 4'h8 >> { n48, n207 }; + assign n207 = 64'h0000000000008000 >> { i_3_, i_4_, i_1_, i_5_, i_2_, i_0_ }; + assign n208 = 64'h0000000000000008 >> { i_7_, i_8_, i_3_, i_4_, i_6_, i_5_ }; + assign n209 = 64'h0000000000000080 >> { i_7_, i_8_, i_5_, i_6_, i_3_, i_4_ }; + assign n210 = 8'ha8 >> { n82, n31, n38 }; + assign n211 = 64'h0008080800888888 >> { n47, n91, n70, n215, n212, n214 }; + assign n41 = 16'h0008 >> { i_1_, i_9_, i_2_, i_0_ }; + assign n212 = 16'h0777 >> { n85, n213, n26, n164 }; + assign n213 = 64'h0000000000008000 >> { i_5_, i_3_, i_8_, i_6_, i_7_, i_4_ }; + assign n214 = 64'h0000077707770777 >> { n57, n81, n55, n62, n41, n80 }; + assign n215 = 64'h0000000000008000 >> { i_5_, i_4_, i_1_, i_2_, i_3_, i_0_ }; + assign n216 = 64'h0001010100ffffff >> { n47, n36, n164, n79, n31, n117 }; + assign n217 = 64'h0008080800888888 >> { n59, n57, n96, n192, n220, n218 }; + assign n218 = 16'h0777 >> { n112, n47, n34, n219 }; + assign n219 = 64'h0000000000000002 >> { i_6_, i_7_, i_8_, i_3_, i_4_, i_5_ }; + assign n220 = 16'h0777 >> { n188, n36, n34, n151 }; + assign n221 = 16'h0777 >> { n65, n175, n59, n82 }; + assign n24 = 4'h8 >> { n25, n26 }; + assign n42 = 64'h01010001ffff00ff >> { n48, n43, n47, n49, n50, n51 }; + assign n222 = 32'd33686050 >> { n105, n226, n55, n223, n224 }; + assign n223 = 16'ha888 >> { n131, n195, n150, n47 }; + assign n224 = 64'h00011111000fffff >> { n36, n91, n190, n225, n97, n213 }; + assign n225 = 64'h0000000000008000 >> { i_0_, i_5_, i_1_, i_2_, i_3_, i_4_ }; + assign n226 = 64'h0000000000000080 >> { i_0_, i_1_, i_4_, i_5_, i_3_, i_2_ }; + assign n227 = 64'h0080008000808080 >> { n185, n205, n38, n228, n229, n231 }; + assign n228 = 64'h0000077707770777 >> { n113, n36, n29, n225, n28, n41 }; + assign n229 = 64'h0000077707770777 >> { n150, n59, n124, n26, n29, n230 }; + assign n230 = 64'h0000000000008000 >> { i_2_, i_4_, i_1_, i_5_, i_3_, i_0_ }; + assign n231 = 64'h1515153f153f153f >> { n233, n232, n117, n63, n48, n68 }; + assign n43 = 8'h01 >> { n44, n45, n46 }; + assign n232 = 8'h01 >> { i_2_, i_0_, i_1_ }; + assign n233 = 8'h01 >> { i_5_, i_3_, i_4_ }; + assign n234 = 32'd2763306 >> { n65, n87, n85, n151, n235 }; + assign n235 = 64'h0000077707770777 >> { n44, n48, n81, n41, n36, n149 }; + assign n236 = 16'h0777 >> { n34, n237, n28, n85 }; + assign n237 = 64'h0000000000000002 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n238 = 8'ha8 >> { n240, n239, n27 }; + assign n239 = 64'h0000000000000001 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n240 = 64'h0000000000008000 >> { i_6_, i_8_, i_7_, i_5_, i_3_, i_4_ }; + assign n241 = 64'h0000000000000008 >> { i_6_, i_7_, i_8_, i_4_, i_3_, i_5_ }; + assign n44 = 64'h8000000000000000 >> { i_2_, i_0_, i_1_, i_5_, i_3_, i_4_ }; + assign n242 = 64'h0080000000800080 >> { n68, n253, n252, n249, n243, n246 }; + assign n243 = 32'd2763306 >> { n202, n85, n29, n77, n244 }; + assign n244 = 32'd125269879 >> { n131, n245, n57, n183, n34 }; + assign n245 = 8'h08 >> { i_7_, i_6_, i_8_ }; + assign n246 = 64'h0002020200222222 >> { n26, n47, n248, n145, n247, n189 }; + assign n247 = 4'h8 >> { n31, n91 }; + assign n248 = 64'h0000000000000002 >> { i_2_, i_0_, i_1_, i_3_, i_4_, i_5_ }; + assign n249 = 64'h0008080800888888 >> { n47, n91, n143, n89, n251, n250 }; + assign n250 = 64'h0000077707770777 >> { n65, n113, n41, n74, n36, n64 }; + assign n251 = 64'h0000077707770777 >> { n48, n82, n26, n74, n29, n76 }; + assign n45 = 64'h0000000000000008 >> { i_2_, i_1_, i_3_, i_4_, i_0_, i_5_ }; + assign n252 = 8'ha8 >> { n190, n132, n38 }; + assign n253 = 16'h0001 >> { n58, n46, n49, n248 }; + assign n254 = 16'h0777 >> { n59, n51, n31, n55 }; + assign n255 = 8'ha8 >> { n70, n69, n48 }; + assign n256 = 8'ha8 >> { n149, n93, n57 }; + assign n257 = 16'h0777 >> { n55, n117, n27, n140 }; + assign n258 = 64'h0000077707770777 >> { n207, n59, n62, n38, n36, n219 }; + assign n259 = 64'h0000000000000080 >> { i_5_, i_3_, i_4_, i_2_, i_0_, i_1_ }; + assign n260 = 16'h0777 >> { n48, n153, n34, n179 }; + assign o_2_ = 64'h7fffffffffffffff >> { n498, n262, n572, n285, n575, n528 }; + assign n46 = 64'h0000000000000008 >> { i_0_, i_5_, i_3_, i_4_, i_1_, i_2_ }; + assign n262 = 64'h8000000000000000 >> { n522, n263, n266, n269, n274, n279 }; + assign n263 = 32'd2763306 >> { n230, n265, n30, n47, n264 }; + assign n264 = 16'h5777 >> { n101, n100, n168, n68 }; + assign n265 = 8'h02 >> { i_6_, i_8_, i_7_ }; + assign n266 = 64'h0001010100555555 >> { n59, n38, n230, n122, n268, n267 }; + assign n267 = 8'h80 >> { n33, n26, n167 }; + assign n268 = 64'h0000000000000080 >> { i_1_, i_5_, i_4_, i_0_, i_3_, i_2_ }; + assign n269 = 32'd8421504 >> { n187, n36, n272, n270, n271 }; + assign n270 = 32'd353703231 >> { n48, n29, n27, n176, n53 }; + assign n271 = 32'd125269879 >> { n131, n34, n245, n169, n59 }; + assign n47 = 16'h0002 >> { i_6_, i_7_, i_8_, i_9_ }; + assign n272 = 64'h1515373f373f373f >> { n273, n68, n101, n191, n48, n100 }; + assign n273 = 8'h02 >> { i_0_, i_1_, i_2_ }; + assign n274 = 16'h8000 >> { n275, n276, n277, n278 }; + assign n275 = 32'd353703231 >> { n47, n55, n29, n82, n191 }; + assign n276 = 16'h0777 >> { n41, n187, n34, n193 }; + assign n277 = 64'h0000077707770777 >> { n181, n59, n51, n38, n36, n176 }; + assign n278 = 64'h0000077707770777 >> { n104, n91, n47, n259, n27, n25 }; + assign n279 = 64'h0000077707770777 >> { n48, n259, n79, n29, n27, n81 }; + assign n280 = 16'h222a >> { n89, n215, n68, n218 }; + assign n281 = 16'h0777 >> { n49, n38, n34, n176 }; + assign n48 = 16'h0008 >> { i_6_, i_7_, i_9_, i_8_ }; + assign n282 = 8'h80 >> { n33, n36, n167 }; + assign n283 = 32'd353703231 >> { n259, n230, n27, n237, n59 }; + assign n284 = 4'h8 >> { n41, n124 }; + assign n285 = 16'h8000 >> { n286, n287, n290, n293 }; + assign n286 = 64'h0001010100555555 >> { n65, n47, n49, n142, n154, n210 }; + assign n287 = 64'h0022222200020202 >> { n288, n34, n93, n48, n200, n289 }; + assign n288 = 4'h1 >> { n182, n226 }; + assign n289 = 16'h0777 >> { n85, n241, n57, n108 }; + assign n290 = 32'd33686050 >> { n164, n108, n27, n291, n292 }; + assign n291 = 8'h80 >> { n100, n101, n59 }; + assign n49 = 64'h0000000000000002 >> { i_0_, i_1_, i_5_, i_3_, i_4_, i_2_ }; + assign n292 = 16'h0777 >> { n105, n68, n34, n146 }; + assign n293 = 64'h0002020200aaaaaa >> { n48, n53, n55, n62, n203, n294 }; + assign n294 = 64'h0000077707770777 >> { n44, n68, n192, n38, n26, n237 }; + assign n295 = 32'd2290649256 >> { i_5_, i_3_, n232, n110, n55 }; + assign n296 = 16'ha888 >> { n159, n233, n72, n85 }; + assign n297 = 8'ha8 >> { n198, n175, n34 }; + assign n298 = 64'h00011111000fffff >> { n59, n65, n240, n299, n226, n77 }; + assign n299 = 64'h0000000000008000 >> { i_7_, i_5_, i_8_, i_6_, i_3_, i_4_ }; + assign n300 = 4'h8 >> { n91, n150 }; + assign n301 = 64'h0777077700000777 >> { n302, n85, n38, n259, n27, n142 }; + assign n50 = 64'h0000000000000008 >> { i_2_, i_1_, i_5_, i_4_, i_3_, i_0_ }; + assign n302 = 64'hffffffffdfffffd7 >> { i_5_, i_7_, i_3_, i_8_, i_4_, i_6_ }; + assign n303 = 64'h0002020200aaaaaa >> { n38, n41, n64, n69, n203, n304 }; + assign n304 = 64'h0000077707770777 >> { n122, n47, n58, n55, n41, n72 }; + assign n305 = 4'h8 >> { n47, n230 }; + assign n306 = 16'h0777 >> { n79, n38, n26, n240 }; + assign n307 = 64'h8000000000000000 >> { n308, n107, n310, n311, n312, n313 }; + assign n308 = 32'd170535466 >> { n116, n35, n48, n30, n309 }; + assign n309 = 64'h0000077707770777 >> { n109, n65, n132, n59, n34, n66 }; + assign n310 = 16'h0777 >> { n59, n70, n30, n55 }; + assign n311 = 32'd125269879 >> { n67, n27, n167, n183, n34 }; + assign n51 = 64'h0000000000008000 >> { i_5_, i_3_, i_1_, i_2_, i_0_, i_4_ }; + assign n312 = 64'h0000077707770777 >> { n65, n93, n85, n74, n41, n173 }; + assign n313 = 16'h0777 >> { n91, n76, n38, n155 }; + assign n314 = 32'd125269879 >> { n166, n167, n55, n103, n47 }; + assign n315 = 64'h0000077707770777 >> { n173, n65, n85, n237, n58, n91 }; + assign n316 = 32'd2763306 >> { n41, n134, n38, n169, n317 }; + assign n317 = 16'h0777 >> { n85, n154, n36, n193 }; + assign n318 = 64'h0008080800aaaaaa >> { n34, n59, n56, n136, n319, n320 }; + assign n319 = 16'h5515 >> { i_6_, n35, i_8_, n87 }; + assign n320 = 32'd353703231 >> { n59, n29, n27, n66, n105 }; + assign n321 = 64'h0008000800080808 >> { n109, n179, n26, n330, n322, n331 }; + assign n25 = 64'h0000000000000008 >> { i_8_, i_5_, i_3_, i_4_, i_6_, i_7_ }; + assign n52 = 64'h0000000000000002 >> { i_2_, i_0_, i_1_, i_5_, i_4_, i_3_ }; + assign n322 = 64'h0000000000008000 >> { n323, n324, n325, n326, n328, n329 }; + assign n323 = 16'ha888 >> { n195, n233, n92, n68 }; + assign n324 = 8'ha8 >> { n268, n230, n55 }; + assign n325 = 16'h0777 >> { n139, n36, n26, n118 }; + assign n326 = 64'h0000770777077707 >> { n205, n47, n327, n57, n34, n187 }; + assign n327 = 64'hfffffffff7ffff7f >> { i_6_, i_7_, i_8_, i_3_, i_5_, i_4_ }; + assign n328 = 16'h0777 >> { n34, n213, n29, n104 }; + assign n329 = 16'h0777 >> { n175, n65, n79, n91 }; + assign n330 = 16'haaa8 >> { n82, n39, n77, n47 }; + assign n331 = 64'h0000077707770777 >> { n57, n81, n225, n59, n41, n237 }; + assign n53 = 64'h0000000000000080 >> { i_2_, i_0_, i_5_, i_1_, i_3_, i_4_ }; + assign n332 = 32'd134744200 >> { n147, n240, n85, n334, n333 }; + assign n333 = 64'h0000077707770777 >> { n51, n68, n26, n135, n29, n50 }; + assign n334 = 16'h0777 >> { n47, n143, n34, n37 }; + assign n335 = 8'h57 >> { n86, n147, n57 }; + assign n336 = 16'h0777 >> { n26, n176, n27, n173 }; + assign n337 = 16'h0777 >> { n57, n74, n27, n72 }; + assign n338 = 16'ha888 >> { n233, n101, n58, n48 }; + assign n339 = 16'h0111 >> { n67, n35, n97, n299 }; + assign n340 = 64'h00011111000fffff >> { n36, n91, n50, n53, n142, n135 }; + assign n341 = 16'h8000 >> { n508, n274, n342, n540 }; + assign n54 = 64'h0000077707770777 >> { n55, n56, n57, n40, n38, n58 }; + assign n342 = 64'h0022222200020202 >> { n343, n28, n36, n38, n344, n345 }; + assign n343 = 16'h0111 >> { n233, n101, n182, n117 }; + assign n344 = 8'ha8 >> { n66, n80, n57 }; + assign n345 = 64'h0000077707770777 >> { n48, n230, n41, n149, n27, n197 }; + assign n346 = 64'h0000000000008000 >> { i_1_, i_4_, i_2_, i_5_, i_3_, i_0_ }; + assign n347 = 8'h01 >> { n175, n64, n87 }; + assign n348 = 64'h0000077707770777 >> { n169, n55, n85, n37, n34, n188 }; + assign n349 = 32'd2860548224 >> { n167, n67, n233, n159, n36 }; + assign n350 = 32'd134744200 >> { n164, n86, n34, n352, n351 }; + assign n351 = 64'h00011111000fffff >> { n47, n85, n183, n173, n190, n104 }; + assign n55 = 16'h0008 >> { i_7_, i_8_, i_9_, i_6_ }; + assign n352 = 16'h0777 >> { n48, n150, n25, n57 }; + assign n353 = 32'd2860548224 >> { n35, n116, n166, n167, n68 }; + assign n354 = 8'ha8 >> { n209, n124, n57 }; + assign n355 = 8'ha8 >> { n146, n87, n27 }; + assign n356 = 32'd1162149957 >> { n359, n38, n48, n358, n357 }; + assign n357 = 16'haaa8 >> { n299, n66, n152, n26 }; + assign n358 = 8'h01 >> { n30, n51, n168 }; + assign n359 = 16'h0111 >> { n195, n233, n46, n259 }; + assign n360 = 8'h80 >> { n361, n363, n367 }; + assign n361 = 16'h0222 >> { n185, n59, n282, n362 }; + assign n56 = 64'h0000000080000000 >> { i_4_, i_0_, i_1_, i_5_, i_3_, i_2_ }; + assign n362 = 64'h0000077707770777 >> { n47, n168, n207, n38, n34, n209 }; + assign n363 = 32'd526344 >> { n51, n47, n366, n364, n365 }; + assign n364 = 16'h0777 >> { n34, n299, n29, n203 }; + assign n365 = 16'h0777 >> { n85, n152, n59, n112 }; + assign n366 = 8'h80 >> { n195, n38, n131 }; + assign n367 = 64'h0088088808880888 >> { n131, n245, n27, n97, n368, n369 }; + assign n368 = 64'h0000077707770777 >> { n48, n103, n47, n56, n36, n74 }; + assign n369 = 64'hfdfdfdfffdfffdff >> { n65, i_4_, n26, i_5_, i_3_, n159 }; + assign o_5_ = 64'h7fffffffffffffff >> { n307, n371, n543, n592, n387, n397 }; + assign n371 = 64'h0808080808080888 >> { n208, n175, n119, n27, n227, n372 }; + assign n57 = 16'h0002 >> { i_2_, i_1_, i_9_, i_0_ }; + assign n372 = 64'h1111111111111115 >> { n192, n112, n373, n181, n29, n374 }; + assign n373 = 4'h8 >> { n233, n195 }; + assign n374 = 32'd2863179944 >> { n245, n131, n241, n179, n65 }; + assign n375 = 8'ha8 >> { n125, n134, n34 }; + assign n376 = 16'ha888 >> { n233, n159, n193, n41 }; + assign n377 = 16'ha888 >> { n35, n33, n209, n26 }; + assign n378 = 64'h0001010100555555 >> { n26, n30, n91, n81, n113, n379 }; + assign n379 = 8'h80 >> { n29, n232, n233 }; + assign n380 = 64'h0008080800888888 >> { n59, n57, n119, n153, n381, n95 }; + assign n381 = 32'd125269879 >> { n194, n195, n38, n268, n48 }; + assign n58 = 64'h0000000000008000 >> { i_1_, i_5_, i_2_, i_0_, i_3_, i_4_ }; + assign n382 = 64'h0008000800080808 >> { n58, n45, n38, n385, n384, n383 }; + assign n383 = 16'h0777 >> { n47, n203, n36, n119 }; + assign n384 = 16'h0777 >> { n85, n239, n48, n104 }; + assign n385 = 16'h8880 >> { n68, n29, n195, n194 }; + assign n386 = 64'h7777777707777777 >> { i_3_, n57, i_5_, n265, n34, n139 }; + assign n387 = 32'd2147483648 >> { n388, n391, n394, n395, n396 }; + assign n388 = 64'h0008080800888888 >> { n34, n47, n69, n108, n389, n390 }; + assign n389 = 64'h0000077707770777 >> { n182, n68, n140, n41, n38, n346 }; + assign n390 = 16'h0777 >> { n57, n86, n39, n68 }; + assign n391 = 64'h0000008000800080 >> { n124, n27, n177, n393, n392, n337 }; + assign n59 = 16'h0080 >> { i_8_, i_6_, i_7_, i_9_ }; + assign n392 = 32'd125269879 >> { n48, n100, n101, n237, n27 }; + assign n393 = 16'h0777 >> { n68, n205, n134, n65 }; + assign n394 = 64'h0000000800080008 >> { n215, n59, n206, n111, n236, n148 }; + assign n395 = 64'h0000077707770777 >> { n91, n63, n26, n198, n27, n129 }; + assign n396 = 64'h0000077707770777 >> { n197, n65, n169, n55, n27, n86 }; + assign n397 = 16'h8000 >> { n361, n398, n402, n404 }; + assign n398 = 64'h0008000800080808 >> { n193, n129, n85, n401, n399, n400 }; + assign n399 = 16'h0777 >> { n168, n59, n26, n146 }; + assign n400 = 16'h0777 >> { n65, n209, n29, n190 }; + assign n401 = 16'ha888 >> { n167, n67, n80, n41 }; + assign n60 = 8'h2a >> { n66, n65, n61 }; + assign n402 = 32'd707406506 >> { n41, n57, n167, n33, n403 }; + assign n403 = 64'h0000077707770777 >> { n155, n48, n59, n103, n29, n31 }; + assign n404 = 64'h0008080800888888 >> { n30, n55, n346, n68, n406, n405 }; + assign n405 = 64'h0000077707770777 >> { n65, n154, n59, n190, n29, n44 }; + assign n406 = 16'h0777 >> { n187, n57, n36, n125 }; + assign n407 = 32'd2147483648 >> { n540, n408, n279, n395, n410 }; + assign n408 = 8'h2a >> { n103, n55, n409 }; + assign n409 = 64'h0000077707770777 >> { n69, n68, n113, n34, n26, n241 }; + assign n410 = 64'h00011111000fffff >> { n38, n47, n58, n110, n73, n268 }; + assign n411 = 64'h0000077707770777 >> { n91, n112, n181, n68, n36, n175 }; + assign n61 = 64'h0000077707770777 >> { n57, n64, n38, n63, n29, n62 }; + assign n412 = 64'h8888888808888888 >> { i_7_, n85, i_6_, n233, n414, n413 }; + assign n413 = 16'h0777 >> { n73, n68, n41, n152 }; + assign n414 = 64'h00011111000fffff >> { n29, n65, n193, n164, n63, n92 }; + assign n415 = 32'd1434419071 >> { n273, n38, n33, n57, n35 }; + assign n416 = 32'd2763306 >> { n65, n109, n47, n112, n417 }; + assign n417 = 16'h5777 >> { n131, n245, n149, n34 }; + assign n418 = 32'd17892863 >> { n41, n57, n239, n142, n202 }; + assign n419 = 64'h00011111000fffff >> { n27, n68, n77, n346, n241, n64 }; + assign n420 = 32'd134744200 >> { n45, n62, n59, n422, n421 }; + assign n421 = 64'h0000077707770777 >> { n91, n169, n145, n85, n55, n150 }; + assign n26 = 16'h0008 >> { i_2_, i_9_, i_1_, i_0_ }; + assign n62 = 64'h0000000080000000 >> { i_1_, i_0_, i_2_, i_5_, i_3_, i_4_ }; + assign n422 = 16'h0777 >> { n85, n219, n34, n74 }; + assign n423 = 64'h0008080800888888 >> { n26, n48, n203, n240, n425, n424 }; + assign n424 = 16'h0777 >> { n191, n91, n29, n98 }; + assign n425 = 32'd125269879 >> { n67, n167, n57, n65, n28 }; + assign n426 = 64'h0000000080000000 >> { n427, n428, n430, n431, n432, n434 }; + assign n427 = 4'h8 >> { n34, n240 }; + assign n428 = 16'h0ddd >> { n182, n59, n429, n36 }; + assign n429 = 64'hf7fffffff77ff7ff >> { i_3_, i_6_, i_8_, i_5_, i_7_, i_4_ }; + assign n430 = 32'd2139051391 >> { i_9_, n81, n55, n131, n195 }; + assign n431 = 64'h0000077707770777 >> { n48, n92, n47, n105, n39, n91 }; + assign n63 = 64'h0000000000000008 >> { i_0_, i_1_, i_5_, i_3_, i_2_, i_4_ }; + assign n432 = 64'h00000ddd0ddd0ddd >> { n259, n68, n140, n65, n433, n27 }; + assign n433 = 64'hfffffffff7ffff7f >> { i_8_, i_6_, i_4_, i_7_, i_3_, i_5_ }; + assign n434 = 64'h0000077707770777 >> { n53, n55, n59, n203, n29, n56 }; + assign n435 = 8'h80 >> { n269, n342, n436 }; + assign n436 = 64'h8000000000000000 >> { n257, n352, n437, n438, n439, n440 }; + assign n437 = 16'h0777 >> { n47, n70, n38, n50 }; + assign n438 = 16'h0777 >> { n65, n40, n36, n145 }; + assign n439 = 32'd125269879 >> { n159, n34, n233, n119, n57 }; + assign n440 = 16'h0777 >> { n48, n112, n26, n72 }; + assign n441 = 32'd2763306 >> { n173, n34, n29, n182, n442 }; + assign n64 = 64'h0000000000000002 >> { i_7_, i_8_, i_5_, i_3_, i_4_, i_6_ }; + assign n442 = 32'd125269879 >> { n166, n59, n167, n179, n85 }; + assign n443 = 64'h7777777777770777 >> { i_5_, i_3_, n195, n48, n25, n41 }; + assign n444 = 8'ha8 >> { n45, n52, n48 }; + assign n445 = 64'h0002000000020002 >> { n27, n448, n447, n449, n446, n137 }; + assign n446 = 16'haaa8 >> { n213, n119, n239, n34 }; + assign n447 = 16'haaa8 >> { n151, n93, n147, n26 }; + assign n448 = 8'h01 >> { n134, n135, n96 }; + assign n449 = 32'd2863311528 >> { n154, n299, n81, n96, n36 }; + assign n450 = 8'h80 >> { n451, n454, n456 }; + assign n451 = 64'h0000000200020002 >> { n68, n168, n366, n452, n300, n453 }; + assign n65 = 16'h0008 >> { i_0_, i_9_, i_1_, i_2_ }; + assign n452 = 4'h8 >> { n48, n153 }; + assign n453 = 32'd125269879 >> { n33, n34, n35, n136, n36 }; + assign n454 = 64'h0008080800888888 >> { n26, n68, n230, n40, n455, n331 }; + assign n455 = 16'h0777 >> { n81, n85, n59, n62 }; + assign n456 = 64'h0000077707770777 >> { n48, n181, n89, n59, n38, n105 }; + assign n457 = 32'd2147483648 >> { n217, n398, n458, n314, n315 }; + assign n458 = 64'h0001000100010101 >> { n59, n55, n69, n460, n461, n459 }; + assign n459 = 16'ha888 >> { n233, n101, n182, n91 }; + assign n460 = 16'ha888 >> { n116, n35, n191, n38 }; + assign n461 = 32'd2290657416 >> { i_1_, n167, i_2_, n155, n47 }; + assign n66 = 64'h0000000000000008 >> { i_6_, i_8_, i_3_, i_4_, i_7_, i_5_ }; + assign n462 = 64'h8000000000000000 >> { n234, n436, n560, n465, n466, n468 }; + assign n463 = 32'd353703231 >> { n205, n82, n38, n230, n91 }; + assign n464 = 64'h0000077707770777 >> { n198, n65, n55, n73, n27, n188 }; + assign n465 = 64'h0002020200aaaaaa >> { n29, n85, n109, n150, n248, n231 }; + assign n466 = 64'h0008080800888888 >> { n34, n48, n190, n64, n84, n467 }; + assign n467 = 16'h0777 >> { n41, n240, n36, n147 }; + assign n468 = 64'h0080008000808080 >> { n29, n91, n215, n470, n471, n469 }; + assign n469 = 16'h0777 >> { n110, n59, n38, n103 }; + assign n470 = 32'd125269879 >> { n34, n131, n67, n205, n48 }; + assign n471 = 16'h0777 >> { n65, n72, n27, n37 }; + assign n67 = 8'h02 >> { i_6_, i_7_, i_8_ }; + assign n472 = 32'd125269879 >> { n131, n195, n38, n203, n29 }; + assign n473 = 64'h0202020202020222 >> { n346, n132, n268, n91, n474, n389 }; + assign n474 = 32'd2863311528 >> { n63, n143, n52, n62, n68 }; + assign n475 = 16'h0080 >> { i_4_, n65, i_5_, n67 }; + assign n476 = 32'd2763306 >> { n47, n62, n38, n153, n477 }; + assign n477 = 32'd125269879 >> { n159, n233, n27, n179, n273 }; + assign n478 = 64'h0008080800888888 >> { n36, n50, n68, n124, n480, n479 }; + assign n479 = 32'd5723991 >> { n155, n91, n239, n96, n41 }; + assign n480 = 16'h0777 >> { n146, n85, n47, n215 }; + assign n481 = 32'd2147483648 >> { n451, n454, n482, n485, n456 }; + assign n68 = 16'h8000 >> { i_9_, i_6_, i_7_, i_8_ }; + assign n482 = 64'h0202000222aa00aa >> { n55, n484, n68, n225, n373, n483 }; + assign n483 = 32'd125269879 >> { n29, n195, n131, n89, n48 }; + assign n484 = 8'h15 >> { n233, n101, n110 }; + assign n485 = 64'h0000000200020002 >> { n215, n38, n488, n427, n486, n487 }; + assign n486 = 16'haaa8 >> { n56, n45, n51, n91 }; + assign n487 = 16'h0777 >> { n85, n213, n55, n76 }; + assign n488 = 8'ha8 >> { n219, n118, n41 }; + assign n489 = 64'h00011111000fffff >> { n65, n185, n29, n68, n136, n208 }; + assign n490 = 64'h0000077707770777 >> { n68, n226, n47, n169, n25, n85 }; + assign n491 = 64'hffff7fffbffffffd >> { i_8_, i_4_, i_6_, i_3_, i_7_, i_5_ }; + assign n69 = 64'h0000000000008000 >> { i_2_, i_5_, i_1_, i_0_, i_3_, i_4_ }; + assign n492 = 8'h01 >> { n72, n140, n237 }; + assign n493 = 64'h0000077707770777 >> { n85, n208, n38, n248, n29, n52 }; + assign n494 = 64'h00011111000fffff >> { n47, n55, n30, n132, n181, n182 }; + assign n495 = 64'h0000800080008000 >> { n68, n45, n494, n162, n170, n180 }; + assign o_0_ = 64'h7fffffffffffffff >> { n498, n495, n501, n505, n126, n567 }; + assign n497 = 64'h020a020a020a222a >> { n52, n53, n38, n59, n39, n54 }; + assign n498 = 64'h0000800080008000 >> { n41, n40, n497, n23, n32, n42 }; + assign n499 = 64'h0008080800888888 >> { n36, n59, n69, n81, n71, n503 }; + assign n500 = 64'h0008000800080808 >> { n70, n82, n68, n111, n75, n78 }; + assign n501 = 64'h8000000000000000 >> { n499, n60, n500, n83, n94, n106 }; + assign n70 = 64'h0000000000000080 >> { i_0_, i_1_, i_5_, i_2_, i_3_, i_4_ }; + assign n502 = 64'h0202020213020202 >> { i_0_, i_1_, i_2_, i_3_, i_5_, i_4_ }; + assign n503 = 32'd1474289631 >> { n65, n67, n68, i_4_, n502 }; + assign n504 = 64'h4606420244044000 >> { n25, n113, n97, i_2_, i_0_, i_1_ }; + assign n505 = 64'h0080808000888888 >> { n504, n52, n91, i_9_, n114, n120 }; + assign n506 = 64'h00011111000fffff >> { n26, n36, n136, n152, n151, n154 }; + assign n507 = 64'h0001010100ffffff >> { n38, n91, n153, n150, n45, n155 }; + assign n508 = 64'h0000800080008000 >> { n55, n52, n506, n507, n148, n156 }; + assign n509 = 64'h1515153f5555557f >> { n91, n155, n79, n194, n195, n59 }; + assign n510 = 64'h00011111000fffff >> { n55, n191, n29, n59, n50, n192 }; + assign n511 = 64'h00011111000fffff >> { n47, n65, n37, n209, n192, n39 }; + assign n71 = 64'h0000077707770777 >> { n57, n74, n59, n73, n27, n72 }; + assign n512 = 64'h0000000800080008 >> { n143, n55, n204, n206, n128, n511 }; + assign n513 = 64'h0000800080008000 >> { n208, n41, n199, n512, n211, n286 }; + assign n514 = 64'h00011111000fffff >> { n48, n41, n37, n145, n117, n185 }; + assign n515 = 64'h00011111000fffff >> { n34, n57, n113, n197, n142, n241 }; + assign n516 = 64'h0000800080008000 >> { n140, n34, n569, n515, n227, n234 }; + assign n517 = 64'h9818880890108000 >> { n183, n241, n202, i_2_, i_1_, i_0_ }; + assign n518 = 32'd5723991 >> { n108, n65, n179, n151, n41 }; + assign n519 = 64'h0008000800000008 >> { i_9_, n517, n255, n256, n518, n254 }; + assign n520 = 64'h0000077707770777 >> { n91, n155, n103, n38, n36, n125 }; + assign n521 = 64'h00011111000fffff >> { n55, n239, n85, n57, n117, n259 }; + assign n27 = 16'h0080 >> { i_9_, i_0_, i_1_, i_2_ }; + assign n72 = 64'h0000000000000008 >> { i_6_, i_8_, i_5_, i_4_, i_3_, i_7_ }; + assign n522 = 64'h0000800080008000 >> { n140, n27, n521, n520, n258, n260 }; + assign n523 = 64'h0000077707770777 >> { n59, n69, n132, n55, n48, n207 }; + assign n524 = 64'h0008000800080808 >> { n31, n203, n47, n284, n283, n523 }; + assign n525 = 64'h0001010100ffffff >> { n27, n59, n73, n93, n118, n145 }; + assign n526 = 64'h00011111000fffff >> { n29, n57, n152, n241, n205, n45 }; + assign n527 = 64'h0222022202222222 >> { n131, n233, n195, n91, n297, n298 }; + assign n528 = 64'h0088088808880888 >> { n233, n101, n47, n153, n526, n527 }; + assign n529 = 64'h0080008080800080 >> { n142, n339, n85, n336, n335, n340 }; + assign o_3_ = 64'h7fffffffffffffff >> { n578, n533, n307, n536, n321, n572 }; + assign n531 = 64'h0001010100ffffff >> { n59, n57, n175, n44, n185, n215 }; + assign n73 = 64'h0000000000008000 >> { i_2_, i_0_, i_1_, i_5_, i_3_, i_4_ }; + assign n532 = 64'h0000000000000080 >> { n247, n300, n305, n301, n531, n306 }; + assign n533 = 32'd134744200 >> { n113, n239, n36, n532, n303 }; + assign n534 = 64'h0808080808080888 >> { n62, n207, n268, n29, n314, n315 }; + assign n535 = 64'h0000077707770777 >> { n91, n192, n70, n55, n48, n143 }; + assign n536 = 64'h8000000000000000 >> { n534, n535, n157, n316, n318, n519 }; + assign n537 = 64'h0111055503330777 >> { n346, n55, n46, n29, n182, n59 }; + assign n538 = 64'h4303410142024000 >> { n225, n346, n46, i_6_, i_7_, i_8_ }; + assign n539 = 64'h0555077707770777 >> { n67, n35, n152, n65, n125, n27 }; + assign n540 = 64'h0080008880808888 >> { i_9_, n41, n538, n347, n539, n348 }; + assign n541 = 64'h00011111000fffff >> { n29, n41, n66, n97, n89, n30 }; + assign n74 = 64'h0000000000008000 >> { i_7_, i_4_, i_8_, i_5_, i_3_, i_6_ }; + assign n542 = 64'h0105010501051115 >> { n92, n143, n68, n38, n56, n375 }; + assign n543 = 16'h8000 >> { n542, n589, n162, n290 }; + assign n544 = 64'h00011111000fffff >> { n41, n47, n50, n63, n93, n299 }; + assign n545 = 64'h222222222222222a >> { n53, n73, n192, n225, n48, n419 }; + assign n546 = 64'h8000000000000000 >> { n322, n411, n418, n420, n423, n426 }; + assign o_6_ = 64'h7fffffffffffffff >> { n545, n243, n546, n407, n550, n501 }; + assign n548 = 64'h0000077707770777 >> { n125, n57, n108, n36, n27, n209 }; + assign n549 = 64'h0080008000808080 >> { n98, n117, n59, n548, n229, n415 }; + assign n550 = 64'h0000800080008000 >> { n208, n26, n549, n404, n412, n416 }; + assign n551 = 64'h222222222222222a >> { n72, n118, n154, n208, n57, n443 }; + assign n75 = 16'h0777 >> { n47, n77, n55, n76 }; + assign n552 = 32'd8421504 >> { n183, n65, n551, n408, n441 }; + assign o_7_ = 64'h7fffffffffffffff >> { n552, n435, n595, n445, n450, n457 }; + assign n554 = 64'h00011111000fffff >> { n29, n55, n31, n63, n225, n259 }; + assign n555 = 64'h050f151f151f151f >> { n67, n35, n34, n57, n140, n299 }; + assign n556 = 64'h0000800080008000 >> { n51, n47, n365, n402, n426, n472 }; + assign o_8_ = 64'h7fffffffffffffff >> { n555, n556, n462, n563, n505, n533 }; + assign n558 = 64'h8888888800201800 >> { i_9_, i_4_, i_3_, i_5_, i_7_, i_6_ }; + assign n559 = 64'h0a8a2aaa4aca6aea >> { i_1_, n346, n207, n558, i_8_, i_9_ }; + assign n560 = 64'h8008880888088808 >> { i_0_, i_2_, n559, i_9_, n463, n464 }; + assign n561 = 64'h444444444444444e >> { n37, n96, n193, n202, n147, i_0_ }; + assign n76 = 64'h0000000000000008 >> { i_1_, i_5_, i_3_, i_4_, i_2_, i_0_ }; + assign n562 = 64'hfff9fff3fffdfff7 >> { n173, n561, i_9_, i_2_, i_0_, i_1_ }; + assign n563 = 64'h0000000080000000 >> { n475, n287, n473, n562, n476, n478 }; + assign n564 = 64'h000400054444ffff >> { n34, n36, n135, n145, n492, n176 }; + assign n565 = 64'h050f557f070f777f >> { n35, n81, n27, n85, n167, n33 }; + assign n566 = 64'h0000000080000000 >> { n186, n184, n189, n196, n509, n510 }; + assign n567 = 64'h0008080800888888 >> { n27, n57, n193, n183, n566, n565 }; + assign n568 = 64'h00011111000fffff >> { n56, n125, n41, n65, n74, n55 }; + assign n569 = 64'h0000000800080008 >> { n164, n41, n88, n238, n236, n568 }; + assign n570 = 64'h0057575757575757 >> { n35, n67, n26, n139, n125, n27 }; + assign n571 = 64'h0000077707770777 >> { n168, n91, n119, n36, n29, n226 }; + assign n77 = 64'h0000000000000002 >> { i_2_, i_0_, i_5_, i_3_, i_4_, i_1_ }; + assign n572 = 64'h0000000080000000 >> { n282, n571, n280, n281, n570, n524 }; + assign n573 = 64'h0001010100ffffff >> { n41, n57, n87, n119, n209, n213 }; + assign n574 = 64'h0002000200020202 >> { n132, n215, n48, n295, n296, n525 }; + assign n575 = 64'h0008080800888888 >> { n28, n29, n117, n34, n574, n573 }; + assign n576 = 64'h0057575757575757 >> { n29, n116, n35, n122, n53, n68 }; + assign n577 = 64'h0001010100ffffff >> { n38, n47, n185, n76, n182, n30 }; + assign n578 = 64'h0000000080000000 >> { n338, n577, n332, n337, n576, n529 }; + assign n579 = 64'h0555077707770777 >> { n131, n67, n213, n57, n86, n27 }; + assign n580 = 64'h0000800080008000 >> { n146, n41, n60, n283, n356, n537 }; + assign o_4_ = 64'h7fffffffffffffff >> { n579, n580, n341, n360, n513, n587 }; + assign n78 = 16'h0777 >> { n79, n38, n27, n80 }; + assign n582 = 64'h0a0a0a0208080800 >> { n198, n135, n80, i_0_, i_1_, i_2_ }; + assign n583 = 64'h6440200044400000 >> { n232, n101, i_9_, i_8_, i_6_, i_7_ }; + assign n584 = 64'h0010101000111111 >> { n582, n583, n233, i_9_, n305, n349 }; + assign n585 = 64'h0001010100ffffff >> { n26, n29, n346, n173, n179, n80 }; + assign n586 = 64'h0002000200020202 >> { n122, n226, n91, n354, n355, n541 }; + assign n587 = 32'd32768 >> { n353, n586, n350, n585, n584 }; + assign n588 = 64'h8000048280000000 >> { i_3_, i_2_, i_0_, i_5_, i_1_, i_4_ }; + assign n589 = 64'h0011101101111111 >> { n91, n55, n588, i_0_, n376, n377 }; + assign n590 = 64'h0000077707770777 >> { n68, n268, n36, n183, n34, n154 }; + assign n591 = 64'h0080008000808080 >> { n152, n239, n65, n590, n386, n544 }; + assign n79 = 64'h0000000000000080 >> { i_2_, i_1_, i_4_, i_5_, i_3_, i_0_ }; + assign n592 = 64'h0000800080008000 >> { n51, n29, n591, n378, n380, n382 }; + assign n593 = 64'h00011111000fffff >> { n59, n41, n40, n183, n92, n44 }; + assign n594 = 64'h0000077707770777 >> { n91, n203, n68, n104, n65, n86 }; + assign n595 = 64'h0000000000008000 >> { n204, n444, n593, n393, n594, n554 }; + assign n596 = 64'hfffdfff5fffffff7 >> { n81, n491, i_9_, i_2_, i_0_, i_1_ }; + assign n597 = 64'h0000800080008000 >> { n59, n49, n258, n411, n490, n493 }; + assign n598 = 64'h0008008808080888 >> { n240, n85, n57, n188, n489, n596 }; + assign n599 = 64'h8000000000000000 >> { n293, n332, n367, n560, n564, n597 }; + assign o_9_ = 64'h7fffffffffffffff >> { n598, n127, n216, n599, n387, n481 }; + assign n601 = 64'h0000800080008000 >> { n77, n55, n217, n222, n519, n522 }; + assign n80 = 64'h0000000080000000 >> { i_8_, i_7_, i_6_, i_5_, i_3_, i_4_ }; + assign n602 = 64'h0080008000808080 >> { n119, n188, n85, n216, n221, n514 }; + assign o_1_ = 32'd2147483647 >> { n601, n602, n242, n513, n516 }; + assign n81 = 64'h0000000000000080 >> { i_7_, i_5_, i_3_, i_6_, i_8_, i_4_ }; + assign n28 = 64'h0000000000008000 >> { i_8_, i_5_, i_6_, i_7_, i_3_, i_4_ }; + assign n82 = 64'h0000000000000080 >> { i_2_, i_5_, i_4_, i_0_, i_3_, i_1_ }; + assign n83 = 32'd526344 >> { n37, n34, n88, n84, n90 }; + assign n84 = 64'h0000077707770777 >> { n86, n85, n48, n46, n36, n87 }; + assign n85 = 16'h0001 >> { i_2_, i_0_, i_1_, i_9_ }; + assign n86 = 64'h0000000000000080 >> { i_6_, i_7_, i_5_, i_8_, i_3_, i_4_ }; + assign n87 = 64'h0000000000000008 >> { i_7_, i_8_, i_5_, i_4_, i_3_, i_6_ }; + assign n88 = 4'h8 >> { n38, n89 }; + assign n89 = 64'h0000000080000000 >> { i_3_, i_0_, i_1_, i_5_, i_2_, i_4_ }; + assign n90 = 16'h0777 >> { n92, n91, n27, n93 }; + assign n91 = 16'h0008 >> { i_6_, i_8_, i_7_, i_9_ }; + assign n29 = 16'h0080 >> { i_7_, i_6_, i_9_, i_8_ }; + assign n92 = 64'h0000000000008000 >> { i_0_, i_1_, i_2_, i_5_, i_3_, i_4_ }; + assign n93 = 64'h0000000000000080 >> { i_6_, i_3_, i_4_, i_5_, i_7_, i_8_ }; + assign n94 = 32'd526344 >> { n105, n68, n99, n95, n102 }; + assign n95 = 64'h0000077707770777 >> { n85, n96, n47, n98, n26, n97 }; + assign n96 = 64'h0000000000000080 >> { i_6_, i_8_, i_5_, i_7_, i_3_, i_4_ }; + assign n97 = 64'h0000000000008000 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n98 = 64'h0000000000000080 >> { i_0_, i_5_, i_4_, i_2_, i_3_, i_1_ }; + assign n99 = 8'h80 >> { n100, n101, n55 }; + assign n100 = 8'h08 >> { i_5_, i_3_, i_4_ }; + assign n101 = 8'h02 >> { i_2_, i_1_, i_0_ }; + assign n30 = 64'h0000000000000080 >> { i_2_, i_1_, i_3_, i_5_, i_0_, i_4_ }; + assign n102 = 16'h0777 >> { n103, n48, n59, n104 }; + assign n103 = 64'h0000000000000008 >> { i_2_, i_0_, i_1_, i_5_, i_3_, i_4_ }; + assign n104 = 64'h0000000000008000 >> { i_2_, i_1_, i_0_, i_5_, i_3_, i_4_ }; + assign n105 = 64'h0000000000000008 >> { i_2_, i_0_, i_3_, i_4_, i_1_, i_5_ }; + assign n106 = 32'd2763306 >> { n110, n38, n34, n109, n107 }; + assign n107 = 16'h0777 >> { n41, n108, n38, n44 }; + assign n108 = 64'h0000000000000002 >> { i_6_, i_7_, i_8_, i_5_, i_4_, i_3_ }; + assign n109 = 64'h0000000000000080 >> { i_6_, i_8_, i_3_, i_5_, i_7_, i_4_ }; + assign n110 = 64'h0000000000000080 >> { i_2_, i_5_, i_3_, i_0_, i_1_, i_4_ }; + assign n111 = 4'h8 >> { n38, n112 }; + assign n31 = 64'h0000000000000080 >> { i_2_, i_0_, i_1_, i_5_, i_3_, i_4_ }; + assign n112 = 64'h0000000000000002 >> { i_2_, i_0_, i_1_, i_5_, i_3_, i_4_ }; + assign n113 = 64'h0000000000008000 >> { i_7_, i_8_, i_6_, i_5_, i_3_, i_4_ }; + assign n114 = 64'h0002020200aaaaaa >> { n65, n55, n63, n118, n119, n115 }; + assign n115 = 64'h0555077707770777 >> { n116, n35, n85, n80, n117, n47 }; + assign n116 = 8'h08 >> { i_0_, i_2_, i_1_ }; + assign n117 = 64'h0000000000008000 >> { i_1_, i_3_, i_2_, i_5_, i_0_, i_4_ }; + assign n118 = 64'h0000000000000080 >> { i_7_, i_8_, i_3_, i_5_, i_6_, i_4_ }; + assign n119 = 64'h8000000000000000 >> { i_6_, i_7_, i_8_, i_5_, i_3_, i_4_ }; + assign n120 = 64'h0002020200222222 >> { n26, n41, n125, n64, n121, n123 }; + assign n121 = 64'h0808080008000800 >> { n70, i_8_, n122, i_7_, i_6_, i_9_ }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act b/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act new file mode 100644 index 000000000..ad3592652 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act @@ -0,0 +1,283 @@ +i_0_ 0.506400 0.495000 +i_1_ 0.504000 0.508200 +i_2_ 0.504400 0.507600 +i_3_ 0.494200 0.497400 +i_4_ 0.496000 0.504000 +i_5_ 0.503800 0.517000 +i_6_ 0.495200 0.509400 +i_7_ 0.494600 0.498000 +o_6_ 0.008200 0.000128 +n75 0.126400 0.025951 +n76 0.063600 0.007663 +o_21_ 0.008800 0.000121 +n78 0.122800 0.025951 +o_20_ 0.009200 0.000109 +n80 0.060200 0.007383 +o_0_ 0.123800 0.185931 +o_1_ 0.126000 0.175576 +n83 0.257600 0.094002 +o_2_ 0.030200 0.002061 +o_3_ 0.033600 0.235205 +n86 0.063400 0.007326 +o_4_ 0.032800 0.001944 +o_5_ 0.063400 0.007373 +o_7_ 0.003800 0.000030 +n90 0.119800 0.025951 +o_8_ 0.003400 0.000036 +n92 0.033000 0.002003 +n93 0.128200 0.028971 +o_9_ 0.004600 0.000039 +n95 0.034800 0.001944 +o_15_ 0.003000 0.000021 +n97 0.125200 0.026735 +n98 0.026200 0.001914 +o_10_ 0.008200 0.000054 +o_11_ 0.005200 0.000037 +n101 0.130800 0.026735 +o_12_ 0.003800 0.000034 +n103 0.124600 0.026815 +o_13_ 0.003400 0.000020 +o_14_ 0.003800 0.000021 +o_16_ 0.004000 0.000023 +o_17_ 0.031400 0.058288 +n108 0.014800 0.000473 +n109 0.016600 0.000450 +o_18_ 0.015000 0.000466 +o_19_ 0.031600 0.001856 +o_22_ 0.006800 0.000063 +n113 0.030800 0.001857 +o_23_ 0.029400 0.001791 +n115 0.122200 0.027221 +o_24_ 0.005000 0.000027 +n117 0.030400 0.002019 +o_25_ 0.004200 0.000026 +o_30_ 0.004200 0.000030 +n120 0.007800 0.000139 +n121 0.065200 0.007663 +o_26_ 0.007800 0.000157 +o_27_ 0.003400 0.000029 +o_28_ 0.003400 0.000029 +o_29_ 0.002600 0.000026 +o_31_ 0.924400 0.025810 +n127 0.479600 0.010240 +n128 0.861800 0.022353 +n129 0.247800 0.090804 +n130 0.701400 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0.146965 +n214 0.906400 0.140468 +n215 0.689400 0.001352 +n216 0.964600 0.000387 +n217 0.848600 0.214975 +n218 0.945400 0.000000 +n219 0.992400 0.024035 +n220 0.755000 0.019995 +n221 0.943000 0.001754 +n222 0.936800 0.109851 +n223 0.958200 0.001505 +n224 0.916800 0.008002 +o_39_ 0.959600 0.032109 +n226 0.206000 0.002013 +n227 0.972800 0.001376 +n228 0.974400 0.092711 +o_40_ 0.882800 0.091109 +n230 0.789200 0.035999 +n231 0.847000 0.000323 +n232 0.739200 0.000148 +n233 0.987400 0.006852 +n234 0.735800 0.009752 +n235 0.008400 0.000138 +n236 0.983600 0.010836 +n237 0.912400 0.232854 +n238 0.877800 0.186728 +n239 0.941000 0.003540 +n240 0.102000 0.001944 +n241 0.777000 0.023887 +n242 0.987600 0.006081 +n243 0.959200 0.061786 +n244 0.872400 0.056329 +n245 0.966200 0.000226 +n246 0.933600 0.000124 +n247 0.486000 0.001779 +n248 0.892400 0.168235 +n249 0.988400 0.006136 +o_46_ 0.961800 0.009121 +n251 0.910800 0.000194 +n252 0.989200 0.006899 +n253 0.789600 0.264434 +o_47_ 0.912000 0.004102 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0.737000 0.082957 +n297 0.432000 0.000003 +n298 0.848200 0.000022 +o_37_ 0.873200 0.081469 +n300 0.532000 0.004741 +o_38_ 0.900000 0.077332 +n302 0.936200 0.029078 +n303 0.203600 0.017053 +o_41_ 0.906000 0.000668 +n305 0.691800 0.047162 +n306 0.382000 0.000049 +o_42_ 0.926000 0.003817 +n308 0.979400 0.039350 +n309 0.865000 0.072014 +n310 0.896800 0.001090 +o_43_ 0.777400 0.010934 +n312 0.884000 0.045014 +o_44_ 0.959200 0.015012 +n314 0.689400 0.000127 +n315 0.854600 0.163096 +o_45_ 0.914400 0.113221 +n317 0.763800 0.004065 +n318 0.897000 0.000561 +n319 0.729400 0.183352 +n320 0.631000 0.084224 +o_53_ 0.823600 0.010097 +n322 0.904200 0.270395 +n323 0.640000 0.005386 +o_55_ 0.800400 0.006571 +n325 0.890200 0.018287 +n326 0.727800 0.002452 +o_56_ 0.944000 0.001791 +n328 0.917800 0.000580 +n329 0.762000 0.003399 +o_59_ 0.900800 0.020333 +n331 0.784200 0.001895 +n332 0.845000 0.003179 +o_34_ 0.925000 0.092354 +n334 0.853800 0.030338 +n335 0.759200 0.006476 +o_35_ 0.928600 0.061765 +n337 0.745200 0.077389 +n338 0.455800 0.017221 +n339 0.924200 0.029968 +n340 0.758200 0.022460 +n341 0.042600 0.073633 +o_50_ 0.981200 0.000068 +n343 0.633800 0.015754 +n344 0.777200 0.032845 +o_54_ 0.897400 0.077441 +n346 0.903800 0.000319 +n347 0.754800 0.002660 +o_57_ 0.905800 0.101237 diff --git a/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif b/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif new file mode 100644 index 000000000..e035825a5 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif @@ -0,0 +1,732 @@ +# Benchmark "ex5p" written by ABC on Tue Mar 12 09:27:13 2019 +.model ex5p +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ \ + o_12_ o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ \ + o_24_ o_25_ o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ o_35_ \ + o_36_ o_37_ o_38_ o_39_ o_40_ o_41_ o_42_ o_43_ o_44_ o_45_ o_46_ o_47_ \ + o_48_ o_49_ o_50_ o_51_ o_52_ o_53_ o_54_ o_55_ o_56_ o_57_ o_58_ o_59_ \ + o_60_ o_61_ o_62_ +.names n76 n75 o_6_ +11 1 +.names i_2_ i_0_ i_1_ n75 +100 1 +.names i_3_ i_6_ i_4_ i_5_ n76 +1000 1 +.names n78 n76 o_21_ +11 1 +.names i_0_ i_1_ i_2_ n78 +100 1 +.names n80 n78 o_20_ +11 1 +.names i_6_ i_3_ i_4_ i_5_ n80 +0000 1 +.names n80 n76 o_0_ +00 0 +.names n83 i_5_ o_1_ +10 1 +.names i_7_ i_6_ n83 +00 1 +.names i_5_ n83 i_3_ i_4_ o_2_ +1100 1 +.names n86 i_7_ o_3_ +10 1 +.names i_5_ i_3_ i_6_ i_4_ n86 +1100 1 +.names i_3_ i_6_ i_7_ i_4_ i_5_ o_4_ +11000 1 +.names i_5_ i_6_ i_7_ i_4_ o_5_ +1100 1 +.names i_7_ i_6_ i_5_ n90 i_3_ i_4_ o_7_ +111100 1 +.names i_1_ i_0_ i_2_ n90 +100 1 +.names n93 n92 o_8_ +11 1 +.names i_7_ i_6_ i_5_ i_3_ i_4_ n92 +11100 1 +.names i_0_ i_1_ i_2_ n93 +111 1 +.names n95 n75 o_9_ +11 1 +.names i_7_ i_6_ i_3_ i_4_ i_5_ n95 +11000 1 +.names n98 n97 o_15_ +11 1 +.names i_2_ i_1_ i_0_ n97 +110 1 +.names i_7_ i_6_ i_3_ i_5_ i_4_ n98 +11110 1 +.names n97 n92 n98 o_10_ +11- 1 +1-1 1 +.names n101 n92 o_11_ +11 1 +.names i_0_ i_1_ i_2_ n101 +110 1 +.names n92 n103 o_12_ +11 1 +.names i_0_ i_2_ i_1_ n103 +110 1 +.names n98 n90 o_13_ +11 1 +.names n98 n78 o_14_ +11 1 +.names n101 n98 o_16_ +11 1 +.names n109 n108 o_17_ +00 0 +.names i_3_ i_4_ i_0_ i_5_ i_1_ i_2_ n108 +111000 1 +.names i_0_ i_4_ i_3_ i_5_ i_1_ i_2_ n109 +110000 1 +.names i_3_ i_4_ i_2_ i_5_ i_0_ i_1_ o_18_ +111000 1 +.names i_4_ i_3_ i_0_ i_1_ i_2_ o_19_ +10000 1 +.names n78 n95 n113 o_22_ +11- 1 +1-1 1 +.names i_7_ i_6_ i_3_ i_4_ i_5_ n113 +11100 1 +.names i_3_ i_5_ n115 o_23_ +111 1 +.names i_0_ i_1_ i_2_ n115 +000 1 +.names n117 n115 o_24_ +11 1 +.names i_6_ i_7_ i_3_ i_4_ i_5_ n117 +10000 1 +.names n117 n90 o_25_ +11 1 +.names i_7_ n120 o_30_ +11 1 +.names n121 n93 n120 +11 1 +.names i_6_ i_3_ i_4_ i_5_ n121 +1000 1 +.names i_0_ i_2_ n95 o_26_ +111 1 +.names n117 n97 o_27_ +11 1 +.names n113 n103 o_28_ +11 1 +.names i_7_ n115 n80 o_29_ +111 1 +.names n136 n127 n142 n139 n210 i_1_ o_31_ +111100 0 +.names n128 n130 n103 n93 n127 +1100 1 +.names n93 i_5_ i_6_ i_3_ i_7_ i_4_ n128 +111--- 0 +11--1- 0 +1--1-- 0 +1----1 0 +-01100 0 +.names i_3_ i_4_ n129 +11 1 +.names n101 i_4_ i_5_ i_7_ i_6_ n130 +01--- 1 +0-0-- 1 +0--11 1 +.names n90 n97 n80 n132 n133 n131 +1--1- 0 +1---1 0 +-11-- 0 +.names i_3_ i_4_ i_5_ n132 +111 1 +.names i_3_ i_5_ i_4_ i_6_ i_7_ n133 +1101- 1 +110-1 1 +.names n135 n97 n121 n134 +00- 1 +0-0 1 +.names i_3_ i_4_ i_1_ i_5_ i_0_ i_2_ n135 +111000 1 +.names n138 n137 n113 n136 +100 1 +.names n115 n129 n133 n137 +11- 1 +1-1 1 +.names n75 i_3_ n138 +10 0 +.names n141 o_17_ n139 +10 1 +.names i_5_ i_4_ i_3_ i_7_ i_6_ n140 +010-- 0 +10011 0 +.names i_4_ i_5_ i_6_ i_7_ n78 n141 +010-- 0 +01-0- 0 +0-1-1 0 +.names n145 n144 n143 n142 +111 1 +.names n115 i_3_ i_4_ i_5_ n143 +100- 0 +10-0 0 +.names n90 i_3_ i_6_ n144 +0-- 1 +-11 1 +.names i_4_ i_3_ n75 i_5_ n145 +00-- 1 +11-1 1 +--0- 1 +.names i_3_ i_7_ i_6_ i_5_ i_4_ n146 +10010 0 +11100 0 +.names n162 n156 n150 n148 n139 o_32_ +11111 0 +.names n128 n130 n103 n93 n149 n148 +11000 1 +.names n115 n86 n113 n149 +11- 1 +1-1 1 +.names n153 n154 n151 n97 n150 +1110 1 +.names n152 n90 n113 n76 n151 +00-- 1 +0-00 1 +.names i_1_ i_4_ i_3_ i_0_ i_2_ n152 +11000 1 +.names n78 i_3_ i_5_ i_4_ n153 +100- 0 +10-0 0 +.names n98 n129 n117 n80 n97 n90 n154 +0000-- 1 +00--0- 1 +--00-0 1 +----00 1 +.names i_1_ i_4_ i_2_ i_3_ i_0_ n155 +11100 1 +.names n159 n157 n98 o_7_ n156 +1100 1 +.names n158 n115 n95 n80 n157 +00-- 1 +0-00 1 +.names i_1_ i_3_ i_4_ i_5_ i_0_ i_2_ n158 +100000 1 +.names n115 i_6_ i_5_ i_4_ n159 +0--- 1 +-100 1 +.names n161 o_5_ n115 n80 n75 n160 +0-1-- 0 +10-11 0 +-11-- 0 +.names i_3_ i_4_ i_6_ i_5_ i_7_ n161 +11--- 0 +1-111 0 +.names n75 i_3_ i_5_ i_4_ n162 +10-- 0 +1-00 0 +.names n187 n296 n176 n174 n168 n164 o_33_ +111111 0 +.names n165 n167 n164 +10 1 +.names n166 o_4_ n165 +00 1 +.names i_3_ i_1_ i_2_ i_0_ i_4_ i_5_ n166 +111100 1 +.names i_4_ i_0_ i_1_ i_2_ n167 +1111 1 +.names n170 n172 n97 n169 n168 +1100 1 +.names n115 n161 n169 +10 1 +.names n158 n171 n90 n140 n170 +000- 1 +00-1 1 +.names i_3_ i_4_ i_2_ i_0_ i_1_ n171 +11100 1 +.names n115 n113 n76 n172 +0-- 1 +-00 1 +.names i_3_ i_7_ i_6_ i_4_ i_5_ n173 +10000 1 +.names n141 n175 n78 n76 n174 +1100 1 +.names n103 n117 n80 n175 +0-- 1 +-00 1 +.names n177 n103 n133 n129 n176 +10-- 1 +1-00 1 +.names i_3_ i_5_ i_4_ n101 i_6_ i_7_ n177 +010-0- 0 +010--0 0 +0--1-- 0 +.names n180 n97 n181 n179 n80 n178 +00--- 1 +0-100 1 +.names i_5_ i_7_ i_6_ i_3_ i_4_ n179 +10100 1 +11000 1 +.names i_3_ i_4_ i_5_ i_1_ i_0_ i_2_ n180 +111100 1 +.names i_5_ i_6_ i_3_ i_4_ i_7_ n181 +0100- 0 +10000 0 +.names n90 n133 n146 n184 n183 n182 +11--- 0 +1-0-- 0 +---10 0 +.names i_7_ i_6_ n183 +11 1 +.names i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ n184 +111000 1 +.names i_5_ i_4_ i_3_ n185 +110 1 +.names i_4_ i_3_ i_5_ i_7_ i_6_ n186 +0-0-- 1 +0--00 1 +-1--- 1 +.names n188 n75 o_19_ n187 +100 1 +.names n115 i_3_ i_4_ n188 +100 0 +.names n192 n160 n190 n191 n189 +1110 1 +.names i_4_ i_3_ i_5_ n101 i_6_ i_7_ n190 +001-0- 0 +001--0 0 +00-1-- 0 +.names n103 n95 n140 n191 +11- 1 +1-0 1 +.names n115 n76 n80 n185 n117 n192 +0---- 1 +-0000 1 +.names i_3_ n93 i_4_ n101 n193 +01-- 0 +1-11 0 +.names n93 n161 n101 n113 n194 +10-- 0 +--11 0 +.names n196 n101 n133 n195 +00- 1 +0-0 1 +.names i_1_ i_4_ i_0_ i_3_ i_2_ n196 +11100 1 +.names n131 n198 n151 n134 o_18_ n197 +11110 1 +.names n199 i_7_ i_6_ n200 n103 n198 +000-- 1 +0--0- 1 +111-- 1 +1---0 1 +.names i_3_ i_4_ i_5_ n199 +000 1 +.names i_3_ i_5_ i_4_ n200 +110 1 +.names i_0_ i_4_ i_5_ i_3_ i_1_ i_2_ n201 +111000 1 +.names n206 n205 n204 n202 +111 1 +.names i_4_ n75 i_3_ i_5_ i_6_ n203 +0-0-- 1 +0--10 1 +-0--- 1 +.names n183 i_4_ n78 i_5_ n204 +00-- 1 +--10 1 +.names n78 n80 n117 n205 +0-- 1 +-00 1 +.names n207 n158 n90 n92 n206 +000- 1 +00-0 1 +.names i_3_ i_4_ i_5_ i_2_ i_0_ i_1_ n207 +111100 1 +.names o_4_ n103 n113 n76 n185 n208 +00--- 1 +0-000 1 +.names n86 n78 n113 n76 n209 +00-- 1 +0-00 1 +.names n115 n76 n210 +11 1 +.names o_5_ n78 n98 n108 n211 +00-- 1 +0-00 1 +.names n213 n297 n148 o_36_ +111 0 +.names n214 n204 n160 n203 n213 +1111 1 +.names n115 i_3_ i_6_ n214 +0-- 1 +-11 1 +.names n216 n194 n193 n138 n188 n137 n215 +111110 1 +.names n135 n90 n146 n133 n216 +00-- 1 +0-10 1 +.names n219 n218 n144 n217 +111 1 +.names n108 n161 n75 n103 n181 n218 +1---- 0 +-01-- 0 +---10 0 +.names n76 n103 n219 +11 0 +.names n90 n97 n220 +00 1 +.names n113 n98 n221 +00 1 +.names i_3_ i_4_ n78 n97 n222 +001- 0 +11-1 0 +.names o_19_ n115 n113 n76 n223 +00-- 1 +0-00 1 +.names n75 i_3_ i_6_ i_4_ n224 +10-- 0 +1-00 0 +.names n189 n208 n226 n133 o_39_ +1110 0 +.names n140 n227 n141 n226 +110 1 +.names n78 n98 n117 n227 +00- 1 +1-0 1 +.names n103 n132 n78 n80 n117 n228 +1--1- 0 +1---1 0 +-11-- 0 +.names n296 n141 n234 n232 n230 n108 o_40_ +111110 0 +.names n231 n175 n157 n98 n230 +1110 1 +.names n109 n97 n115 n92 n76 n231 +000-- 1 +00-00 1 +.names n233 n128 n138 n137 n115 n113 n232 +11100- 1 +1110-0 1 +.names n75 n76 n113 n233 +0-- 1 +-00 1 +.names n237 n236 n177 n235 n234 +1110 1 +.names n101 n76 n235 +11 1 +.names n101 n133 n113 n236 +0-- 1 +-00 1 +.names i_3_ n103 i_6_ i_4_ i_5_ i_7_ n237 +11---- 0 +1-1000 0 +.names n239 n222 n238 +11 1 +.names n78 i_3_ i_4_ i_5_ n239 +101- 0 +11-0 0 +.names i_5_ i_4_ i_3_ i_6_ i_7_ n240 +1001- 1 +100-1 1 +.names n244 n243 n242 n169 n210 n241 +11100 1 +.names n75 n117 n80 n242 +0-- 1 +-00 1 +.names n101 n80 n93 n161 n243 +11-- 0 +--10 0 +.names n186 i_0_ i_2_ n113 n95 n244 +011-- 0 +10-1- 0 +10--1 0 +.names n201 n109 n78 n173 n245 +000- 1 +00-0 1 +.names n92 n103 n161 n246 +00- 1 +0-1 1 +.names n198 n76 i_1_ n103 n186 n161 n247 +10--11 1 +1-00-- 1 +-100-- 1 +.names n211 n228 n248 +11 1 +.names n115 n117 n80 n249 +0-- 1 +-00 1 +.names n187 n127 n253 n251 i_3_ i_2_ o_46_ +111100 0 +.names n252 n172 n169 n92 n251 +1100 1 +.names n90 n76 n117 n252 +0-- 1 +-00 1 +.names n211 n239 n228 n222 n253 +1111 1 +.names n259 n317 n257 n255 n234 o_47_ +11111 0 +.names n193 n97 n146 n256 n153 n255 +10-11 1 +111-- 1 +.names n129 n166 n93 n256 +00- 1 +1-0 1 +.names n228 n211 n258 n209 n201 n257 +11110 1 +.names n103 n186 n181 n258 +0-- 1 +-11 1 +.names n90 n260 o_10_ n259 +000 1 +.names n121 n97 n260 +11 1 +.names n169 n210 o_48_ +00 1 +.names n263 n214 n253 n220 n148 o_49_ +11111 0 +.names i_4_ i_6_ i_3_ n263 +00- 1 +1-0 1 +.names i_6_ i_7_ i_5_ i_4_ n264 +1100 1 +.names n237 n268 n266 n257 n150 o_51_ +11111 0 +.names n267 n101 n161 n113 n76 n266 +10--- 1 +1-100 1 +.names i_5_ i_4_ i_3_ i_6_ i_7_ n267 +0001- 0 +1000- 0 +-0010 0 +.names n206 n221 n138 n269 o_8_ o_18_ n268 +111100 1 +.names n115 i_3_ i_5_ i_4_ n269 +10-- 0 +1-10 0 +.names n217 n269 n275 n319 n271 n113 o_52_ +111110 0 +.names n272 n131 n134 n97 n271 +1110 1 +.names i_3_ i_4_ i_5_ i_7_ n78 i_6_ n272 +1010-- 0 +101--0 0 +10-11- 0 +110-1- 0 +.names n103 n113 n273 +11 0 +.names n166 o_4_ n92 n93 n274 +000- 1 +00-0 1 +.names n246 n236 n267 n235 n275 +1110 1 +.names n245 n236 n228 n182 n208 n260 n276 +111110 1 +.names n272 n95 n103 n277 +100 1 +.names n249 n279 n224 n223 n169 n278 +11110 1 +.names n158 n171 n113 n279 +000 1 +.names n141 n281 n103 n78 n280 +1100 1 +.names n90 i_3_ i_5_ i_4_ n281 +1010 0 +1100 0 +.names i_3_ i_4_ n93 i_6_ i_5_ n282 +10-10 0 +1-1-- 0 +-11-- 0 +.names n284 n214 n203 n283 +111 1 +.names n199 n75 n155 n284 +001 0 +11- 0 +.names n138 n115 n285 +10 1 +.names n145 n188 n286 +11 1 +.names n234 n288 n257 n255 n314 n169 o_58_ +111110 0 +.names n214 o_15_ n288 +10 1 +.names n92 n103 n185 n98 n289 +00-- 1 +0-00 1 +.names n237 n291 n278 n266 n257 n150 o_60_ +111111 0 +.names n274 n243 o_11_ o_7_ n184 n291 +11000 1 +.names n294 n286 n285 n257 n150 n293 o_61_ +111111 0 +.names n130 n128 n93 n293 +110 1 +.names n289 n273 n207 n158 n294 +1100 1 +.names n314 i_1_ n275 i_3_ o_62_ +1110 0 +.names i_2_ i_1_ i_0_ n186 n182 n296 +010-- 0 +01-1- 0 +1010- 0 +----0 0 +.names n209 i_1_ n121 i_0_ i_2_ n80 n297 +100-1- 1 +100--0 1 +10-0-- 1 +.names n201 n76 n173 n155 n103 n186 n298 +00000- 1 +0000-1 1 +.names n217 n215 n338 n97 n146 n92 o_37_ +1110-- 0 +111-10 0 +.names n224 n223 n222 n221 n220 n80 n300 +111110 1 +.names n300 n127 n115 n161 i_5_ n95 o_38_ +110--- 0 +11-100 0 +.names n113 n101 i_3_ i_6_ i_5_ i_4_ n302 +0-0--- 1 +0--100 1 +-0---- 1 +.names n220 n218 n214 n302 i_2_ n303 +11110 1 +.names n238 n232 n303 o_41_ +111 0 +.names i_3_ i_5_ i_7_ i_6_ n103 n93 n305 +01---- 1 +0---00 1 +10-1-- 1 +-10--- 1 +.names n249 n211 n205 n154 n158 i_4_ n306 +111100 1 +.names n241 n340 n306 n305 o_42_ +1111 0 +.names n113 n75 n95 n90 n121 n101 n308 +11---- 0 +1--1-- 0 +-11--- 0 +----11 0 +.names n101 n184 n183 n240 n309 +011- 1 +0-10 1 +1-0- 1 +-000 1 +.names n227 n97 n117 i_4_ n92 n76 n310 +10---- 1 +1-0000 1 +.names n340 n247 n241 n157 n131 n310 o_43_ +111111 0 +.names n188 i_3_ i_6_ i_4_ i_5_ n78 n312 +1000-- 1 +11-11- 1 +1-001- 1 +1----0 1 +.names n314 n248 n168 n127 n312 o_44_ +11111 0 +.names n178 n155 i_1_ i_2_ i_0_ n92 n314 +1000-- 1 +1011-0 1 +10--1- 1 +.names n97 n78 n121 n113 n98 n92 n315 +00---- 1 +1-0000 1 +.names n249 n159 n127 n315 n90 n75 o_45_ +111100 0 +.names n192 i_1_ i_0_ i_4_ i_5_ i_2_ n317 +11---- 1 +1-1--- 1 +1--000 1 +.names n117 n161 n121 n129 n101 n93 n318 +0100-- 1 +010-0- 1 +0--0-0 1 +0---00 1 +.names n274 n318 i_1_ i_0_ i_2_ n113 n319 +111--- 1 +11-0-- 1 +11--10 1 +.names i_1_ i_2_ n92 i_0_ i_3_ i_4_ n320 +000--- 0 +111--- 0 +11-01- 0 +11-101 0 +1-1001 0 +-00001 0 +.names n278 n277 n276 n176 n320 o_53_ +11111 0 +.names n92 n90 n167 n166 n113 n97 n322 +01--0- 1 +01---0 1 +0-000- 1 +-000-0 1 +.names n203 n322 n97 n121 n78 n98 n323 +11000- 1 +1110-0 1 +.names n285 n277 n276 n176 n323 o_55_ +11111 0 +.names n98 n181 n97 n113 n76 n80 n325 +0-0--0 1 +11100- 1 +-11000 1 +.names n284 n223 n206 n325 n169 n152 n326 +111100 1 +.names n286 n248 n238 n127 n326 o_56_ +11111 0 +.names i_1_ i_0_ i_2_ n76 n152 i_6_ n328 +100--0 0 +1101-- 0 +---01- 0 +.names n289 n228 n203 n195 o_19_ n92 n329 +111100 1 +.names n319 n271 n189 n329 n328 o_59_ +11111 0 +.names n165 n143 n161 n76 n103 n93 n331 +110-00 1 +1110-- 1 +.names n195 n193 n113 n115 n97 n101 n332 +110--- 1 +11-000 1 +.names n202 n197 n189 n332 n331 o_34_ +11111 0 +.names i_5_ i_4_ i_3_ n78 i_7_ i_6_ n334 +0101-- 0 +100111 0 +111--- 0 +.names n211 n188 n334 n210 n75 i_3_ n335 +1100-1 1 +11100- 1 +.names n297 n160 n148 n335 o_35_ +1111 0 +.names i_3_ n200 i_2_ i_1_ i_4_ i_0_ n337 +001--- 1 +1-0-1- 1 +-001-- 1 +-0--0- 1 +--00-1 1 +.names n298 n178 n175 n153 n337 n113 n338 +111110 1 +.names i_3_ n75 i_6_ i_5_ i_4_ i_7_ n339 +0111-1 0 +01--1- 0 +11000- 0 +1-1000 0 +.names n309 n308 n339 n179 n166 n340 +11100 1 +.names n264 n237 i_2_ i_1_ i_0_ n76 n341 +110-0- 1 +110--0 1 +11-0-- 1 +.names n317 n257 n177 n154 n153 n341 o_50_ +111111 0 +.names n282 n184 n129 n97 n80 n101 n343 +1000-0 1 +100-0- 1 +1--10- 1 +.names n267 n196 n101 n133 n113 n76 n344 +100--- 1 +10-000 1 +.names n343 n283 n280 n344 n135 o_54_ +11110 0 +.names n184 n97 n121 n113 i_4_ n76 n346 +00---- 1 +0-0000 1 +.names n195 n190 n154 n171 n135 o_25_ n347 +111000 1 +.names n280 n232 n347 n346 n115 o_57_ +11110 0 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v b/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v new file mode 100644 index 000000000..2bd5bc474 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v @@ -0,0 +1,562 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module ex5p(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_, o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_, o_61_, o_62_); + input i_0_; + input i_1_; + input i_2_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + wire n101; + wire n103; + wire n108; + wire n109; + wire n113; + wire n115; + wire n117; + wire n120; + wire n121; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n226; + wire n227; + wire n228; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n251; + wire n252; + wire n253; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n260; + wire n263; + wire n264; + wire n266; + wire n267; + wire n268; + wire n269; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n288; + wire n289; + wire n291; + wire n293; + wire n294; + wire n296; + wire n297; + wire n298; + wire n300; + wire n302; + wire n303; + wire n305; + wire n306; + wire n308; + wire n309; + wire n310; + wire n312; + wire n314; + wire n315; + wire n317; + wire n318; + wire n319; + wire n320; + wire n322; + wire n323; + wire n325; + wire n326; + wire n328; + wire n329; + wire n331; + wire n332; + wire n334; + wire n335; + wire n337; + wire n338; + wire n339; + wire n340; + wire n341; + wire n343; + wire n344; + wire n346; + wire n347; + wire n75; + wire n76; + wire n78; + wire n80; + wire n83; + wire n86; + wire n90; + wire n92; + wire n93; + wire n95; + wire n97; + wire n98; + output o_0_; + output o_10_; + output o_11_; + output o_12_; + output o_13_; + output o_14_; + output o_15_; + output o_16_; + output o_17_; + output o_18_; + output o_19_; + output o_1_; + output o_20_; + output o_21_; + output o_22_; + output o_23_; + output o_24_; + output o_25_; + output o_26_; + output o_27_; + output o_28_; + output o_29_; + output o_2_; + output o_30_; + output o_31_; + output o_32_; + output o_33_; + output o_34_; + output o_35_; + output o_36_; + output o_37_; + output o_38_; + output o_39_; + output o_3_; + output o_40_; + output o_41_; + output o_42_; + output o_43_; + output o_44_; + output o_45_; + output o_46_; + output o_47_; + output o_48_; + output o_49_; + output o_4_; + output o_50_; + output o_51_; + output o_52_; + output o_53_; + output o_54_; + output o_55_; + output o_56_; + output o_57_; + output o_58_; + output o_59_; + output o_5_; + output o_60_; + output o_61_; + output o_62_; + output o_6_; + output o_7_; + output o_8_; + output o_9_; + assign o_6_ = 4'h8 >> { n75, n76 }; + assign n83 = 4'h1 >> { i_6_, i_7_ }; + assign n173 = 32'd2 >> { i_5_, i_4_, i_6_, i_7_, i_3_ }; + assign n174 = 16'h0008 >> { n76, n78, n175, n141 }; + assign n175 = 8'h57 >> { n80, n117, n103 }; + assign n176 = 16'h222a >> { n129, n133, n103, n177 }; + assign n177 = 64'haaffaafbaafbaafb >> { i_7_, i_6_, n101, i_4_, i_5_, i_3_ }; + assign n178 = 32'd286331217 >> { n80, n179, n181, n97, n180 }; + assign n179 = 32'd40 >> { i_4_, i_3_, i_6_, i_7_, i_5_ }; + assign n180 = 64'h0000000000008000 >> { i_2_, i_0_, i_1_, i_5_, i_4_, i_3_ }; + assign n181 = 32'd4294705145 >> { i_7_, i_4_, i_3_, i_6_, i_5_ }; + assign n182 = 32'd1970602101 >> { n183, n184, n146, n133, n90 }; + assign o_2_ = 16'h0008 >> { i_4_, i_3_, n83, i_5_ }; + assign n183 = 4'h8 >> { i_6_, i_7_ }; + assign n184 = 64'h0000000000000080 >> { i_5_, i_4_, i_3_, i_2_, i_1_, i_0_ }; + assign n185 = 8'h08 >> { i_3_, i_4_, i_5_ }; + assign n186 = 32'd3452816861 >> { i_6_, i_7_, i_5_, i_3_, i_4_ }; + assign n187 = 8'h02 >> { o_19_, n75, n188 }; + assign n188 = 8'hfd >> { i_4_, i_3_, n115 }; + assign n189 = 16'h0080 >> { n191, n190, n160, n192 }; + assign n190 = 64'heeffeeefeeefeeef >> { i_7_, i_6_, n101, i_5_, i_3_, i_4_ }; + assign n191 = 8'h8a >> { n140, n95, n103 }; + assign n192 = 32'd1431655767 >> { n117, n185, n80, n76, n115 }; + assign o_3_ = 4'h2 >> { i_7_, n86 }; + assign n193 = 16'h1bbb >> { n101, i_4_, n93, i_3_ }; + assign n194 = 16'h0ddd >> { n113, n101, n161, n93 }; + assign n195 = 8'h15 >> { n133, n101, n196 }; + assign n196 = 32'd128 >> { i_2_, i_3_, i_0_, i_4_, i_1_ }; + assign n197 = 32'd32768 >> { o_18_, n134, n151, n198, n131 }; + assign n198 = 32'd2178264063 >> { n103, n200, i_6_, i_7_, n199 }; + assign n199 = 8'h01 >> { i_5_, i_4_, i_3_ }; + assign n200 = 8'h08 >> { i_4_, i_5_, i_3_ }; + assign n201 = 64'h0000000000000080 >> { i_2_, i_1_, i_3_, i_5_, i_4_, i_0_ }; + assign n202 = 8'h80 >> { n204, n205, n206 }; + assign n86 = 16'h0008 >> { i_4_, i_6_, i_3_, i_5_ }; + assign n203 = 32'd926381879 >> { i_6_, i_5_, i_3_, n75, i_4_ }; + assign n204 = 16'h11f1 >> { i_5_, n78, i_4_, n183 }; + assign n205 = 8'h57 >> { n117, n80, n78 }; + assign n206 = 16'h0111 >> { n92, n90, n158, n207 }; + assign n207 = 64'h0000000000008000 >> { i_1_, i_0_, i_2_, i_5_, i_4_, i_3_ }; + assign n208 = 32'd286331157 >> { n185, n76, n113, n103, o_4_ }; + assign n209 = 16'h1115 >> { n76, n113, n78, n86 }; + assign n210 = 4'h8 >> { n76, n115 }; + assign n211 = 16'h1115 >> { n108, n98, n78, o_5_ }; + assign o_36_ = 8'h7f >> { n148, n297, n213 }; + assign o_4_ = 32'd8 >> { i_5_, i_4_, i_7_, i_6_, i_3_ }; + assign n213 = 16'h8000 >> { n203, n160, n204, n214 }; + assign n214 = 8'hd5 >> { i_6_, i_3_, n115 }; + assign n215 = 64'h0000000080000000 >> { n137, n188, n138, n193, n194, n216 }; + assign n216 = 16'h1151 >> { n133, n146, n90, n135 }; + assign n217 = 8'h80 >> { n144, n218, n219 }; + assign n218 = 32'd1162149957 >> { n181, n103, n75, n161, n108 }; + assign n219 = 4'h7 >> { n103, n76 }; + assign n220 = 4'h1 >> { n97, n90 }; + assign n221 = 4'h1 >> { n98, n113 }; + assign n222 = 16'h67ef >> { n97, n78, i_4_, i_3_ }; + assign o_5_ = 16'h0008 >> { i_4_, i_7_, i_6_, i_5_ }; + assign n223 = 16'h1115 >> { n76, n113, n115, o_19_ }; + assign n224 = 16'hddd5 >> { i_4_, i_6_, i_3_, n75 }; + assign o_39_ = 16'hff7f >> { n133, n226, n208, n189 }; + assign n226 = 8'h08 >> { n141, n227, n140 }; + assign n227 = 8'h1b >> { n117, n98, n78 }; + assign n228 = 32'd353703231 >> { n117, n80, n78, n132, n103 }; + assign o_40_ = 64'hffffffff7fffffff >> { n108, n230, n232, n234, n141, n296 }; + assign n230 = 16'h0080 >> { n98, n157, n175, n231 }; + assign n231 = 32'd16843025 >> { n76, n92, n115, n97, n109 }; + assign n232 = 64'h0000008000800080 >> { n113, n115, n137, n138, n128, n233 }; + assign o_7_ = 64'h0000000000008000 >> { i_4_, i_3_, n90, i_5_, i_6_, i_7_ }; + assign n233 = 8'h57 >> { n113, n76, n75 }; + assign n234 = 16'h0080 >> { n235, n177, n236, n237 }; + assign n235 = 4'h8 >> { n76, n101 }; + assign n236 = 8'h57 >> { n113, n133, n101 }; + assign n237 = 64'h7777777777777757 >> { i_7_, i_5_, i_4_, i_6_, n103, i_3_ }; + assign n238 = 4'h8 >> { n222, n239 }; + assign n239 = 16'hdf57 >> { i_5_, i_4_, i_3_, n78 }; + assign n240 = 32'd33686016 >> { i_7_, i_6_, i_3_, i_4_, i_5_ }; + assign n241 = 32'd128 >> { n210, n169, n242, n243, n244 }; + assign n242 = 8'h57 >> { n80, n117, n75 }; + assign n90 = 8'h02 >> { i_2_, i_0_, i_1_ }; + assign n243 = 16'h7707 >> { n161, n93, n80, n101 }; + assign n244 = 32'd2644352447 >> { n95, n113, i_2_, i_0_, n186 }; + assign n245 = 16'h0111 >> { n173, n78, n109, n201 }; + assign n246 = 8'h51 >> { n161, n103, n92 }; + assign n247 = 64'h222e000e000e000e >> { n161, n186, n103, i_1_, n76, n198 }; + assign n248 = 4'h8 >> { n228, n211 }; + assign n249 = 8'h57 >> { n80, n117, n115 }; + assign o_46_ = 64'hffffffffffff7fff >> { i_2_, i_3_, n251, n253, n127, n187 }; + assign n251 = 16'h0008 >> { n92, n169, n172, n252 }; + assign n252 = 8'h57 >> { n117, n76, n90 }; + assign o_8_ = 4'h8 >> { n92, n93 }; + assign n253 = 16'h8000 >> { n222, n228, n239, n211 }; + assign o_47_ = 32'd2147483647 >> { n234, n255, n257, n317, n259 }; + assign n255 = 32'd2726330496 >> { n153, n256, n146, n97, n193 }; + assign n256 = 8'h1b >> { n93, n166, n129 }; + assign n257 = 32'd32768 >> { n201, n209, n258, n211, n228 }; + assign n258 = 8'hd5 >> { n181, n186, n103 }; + assign n259 = 8'h01 >> { o_10_, n260, n90 }; + assign n260 = 4'h8 >> { n97, n121 }; + assign o_48_ = 4'h1 >> { n210, n169 }; + assign o_49_ = 32'd2147483647 >> { n148, n220, n253, n214, n263 }; + assign n92 = 32'd128 >> { i_4_, i_3_, i_5_, i_6_, i_7_ }; + assign n263 = 8'h1b >> { i_3_, i_6_, i_4_ }; + assign n264 = 16'h0008 >> { i_4_, i_5_, i_7_, i_6_ }; + assign o_51_ = 32'd2147483647 >> { n150, n257, n266, n268, n237 }; + assign n266 = 32'd572662434 >> { n76, n113, n161, n101, n267 }; + assign n267 = 32'd4278058237 >> { i_7_, i_6_, i_3_, i_4_, i_5_ }; + assign n268 = 64'h0000000000008000 >> { o_18_, o_8_, n269, n138, n221, n206 }; + assign n269 = 16'hdd5d >> { i_4_, i_5_, i_3_, n115 }; + assign o_52_ = 64'hffffffff7fffffff >> { n113, n271, n319, n275, n269, n217 }; + assign n271 = 16'h0080 >> { n97, n134, n131, n272 }; + assign n272 = 64'hd5d7ffdfd5d7dfdf >> { i_6_, n78, i_7_, i_5_, i_4_, i_3_ }; + assign n75 = 8'h02 >> { i_1_, i_0_, i_2_ }; + assign n93 = 8'h80 >> { i_2_, i_1_, i_0_ }; + assign n273 = 4'h7 >> { n113, n103 }; + assign n274 = 16'h0111 >> { n93, n92, o_4_, n166 }; + assign n275 = 16'h0080 >> { n235, n267, n236, n246 }; + assign n276 = 64'h0000000080000000 >> { n260, n208, n182, n228, n236, n245 }; + assign n277 = 8'h02 >> { n103, n95, n272 }; + assign n278 = 32'd32768 >> { n169, n223, n224, n279, n249 }; + assign n279 = 8'h01 >> { n113, n171, n158 }; + assign n280 = 16'h0008 >> { n78, n103, n281, n141 }; + assign n281 = 16'hffd7 >> { i_4_, i_5_, i_3_, n90 }; + assign n282 = 32'd522132767 >> { i_5_, i_6_, n93, i_4_, i_3_ }; + assign o_9_ = 4'h8 >> { n75, n95 }; + assign n283 = 8'h80 >> { n203, n214, n284 }; + assign n284 = 8'h67 >> { n155, n75, n199 }; + assign n285 = 4'h2 >> { n115, n138 }; + assign n286 = 4'h8 >> { n188, n145 }; + assign o_58_ = 64'hffffffff7fffffff >> { n169, n314, n255, n257, n288, n234 }; + assign n288 = 4'h2 >> { o_15_, n214 }; + assign n289 = 16'h1115 >> { n98, n185, n103, n92 }; + assign o_60_ = 64'h7fffffffffffffff >> { n150, n257, n266, n278, n291, n237 }; + assign n291 = 32'd8 >> { n184, o_7_, o_11_, n243, n274 }; + assign o_61_ = 64'h7fffffffffffffff >> { n293, n150, n257, n285, n286, n294 }; + assign n95 = 32'd8 >> { i_5_, i_4_, i_3_, i_6_, i_7_ }; + assign n293 = 8'h08 >> { n93, n128, n130 }; + assign n294 = 16'h0008 >> { n158, n207, n273, n289 }; + assign o_62_ = 16'hff7f >> { i_3_, n275, i_1_, n314 }; + assign n296 = 32'd3151691776 >> { n182, n186, i_0_, i_1_, i_2_ }; + assign n297 = 64'h0222002202220222 >> { n80, i_2_, i_0_, n121, i_1_, n209 }; + assign n298 = 64'h0001000100000001 >> { n186, n103, n155, n173, n76, n201 }; + assign o_37_ = 64'hff7fff7f7f7fff7f >> { n92, n146, n97, n338, n215, n217 }; + assign n300 = 64'h0000000080000000 >> { n80, n220, n221, n222, n223, n224 }; + assign o_38_ = 64'hf7f7f7f7f7f777f7 >> { n95, i_5_, n161, n115, n127, n300 }; + assign n302 = 64'h3737373737377737 >> { i_4_, i_5_, i_6_, i_3_, n101, n113 }; + assign o_15_ = 4'h8 >> { n97, n98 }; + assign n303 = 32'd32768 >> { i_2_, n302, n214, n218, n220 }; + assign o_41_ = 8'h7f >> { n303, n232, n238 }; + assign n305 = 64'h6e4c6e4c6e4c7f5d >> { n93, n103, i_6_, i_7_, i_5_, i_3_ }; + assign n306 = 64'h0000000000008000 >> { i_4_, n158, n154, n205, n211, n249 }; + assign o_42_ = 16'h7fff >> { n305, n306, n340, n241 }; + assign n308 = 64'h0000153715371537 >> { n101, n121, n90, n95, n75, n113 }; + assign n309 = 16'h4a5b >> { n240, n183, n184, n101 }; + assign n310 = 64'h222222222222222a >> { n76, n92, i_4_, n117, n97, n227 }; + assign o_43_ = 64'h7fffffffffffffff >> { n310, n131, n157, n241, n247, n340 }; + assign n312 = 64'h880a0002aaaaaaaa >> { n78, i_5_, i_4_, i_6_, i_3_, n188 }; + assign n97 = 8'h08 >> { i_0_, i_1_, i_2_ }; + assign o_44_ = 32'd2147483647 >> { n312, n127, n168, n248, n314 }; + assign n314 = 64'h2222000222222002 >> { n92, i_0_, i_2_, i_1_, n155, n178 }; + assign n315 = 64'h111111111111111b >> { n92, n98, n113, n121, n78, n97 }; + assign o_45_ = 64'hffffffffffff7fff >> { n75, n90, n315, n127, n159, n249 }; + assign n317 = 64'ha8a8a8a8a8a8a8aa >> { i_2_, i_5_, i_4_, i_0_, i_1_, n192 }; + assign n318 = 64'h0004040400555555 >> { n93, n101, n129, n121, n161, n117 }; + assign n319 = 64'h8088808888888088 >> { n113, i_2_, i_0_, i_1_, n318, n274 }; + assign n320 = 64'h7e76765c7e767e7e >> { i_4_, i_3_, i_0_, n92, i_2_, i_1_ }; + assign o_53_ = 32'd2147483647 >> { n320, n176, n276, n277, n278 }; + assign n322 = 64'h0000444544474447 >> { n97, n113, n166, n167, n90, n92 }; + assign n98 = 32'd32768 >> { i_4_, i_5_, i_3_, i_6_, i_7_ }; + assign n323 = 64'h0000000800800088 >> { n98, n78, n121, n97, n322, n203 }; + assign o_55_ = 32'd2147483647 >> { n323, n176, n276, n277, n285 }; + assign n325 = 64'h00000080050505c5 >> { n80, n76, n113, n97, n181, n98 }; + assign n326 = 64'h0000000000008000 >> { n152, n169, n325, n206, n223, n284 }; + assign o_56_ = 32'd2147483647 >> { n326, n127, n238, n248, n286 }; + assign n328 = 64'hf700f7fff500f5fd >> { i_6_, n152, n76, i_2_, i_0_, i_1_ }; + assign n329 = 64'h0000000000008000 >> { n92, o_19_, n195, n203, n228, n289 }; + assign o_59_ = 32'd2147483647 >> { n328, n329, n189, n271, n319 }; + assign n331 = 64'h0080008000800888 >> { n93, n103, n76, n161, n143, n165 }; + assign n332 = 64'h0808080808080888 >> { n101, n97, n115, n113, n193, n195 }; + assign o_10_ = 8'ha8 >> { n98, n92, n97 }; + assign o_34_ = 32'd2147483647 >> { n331, n332, n189, n197, n202 }; + assign n334 = 64'h797f7b7f7b7f7b7f >> { i_6_, i_7_, n78, i_3_, i_4_, i_5_ }; + assign n335 = 64'h0008008800000080 >> { i_3_, n75, n210, n334, n188, n211 }; + assign o_35_ = 16'h7fff >> { n335, n148, n160, n297 }; + assign n337 = 64'h1b1f333f1b1a3333 >> { i_0_, i_4_, i_1_, i_2_, n200, i_3_ }; + assign n338 = 64'h0000000080000000 >> { n113, n337, n153, n175, n178, n298 }; + assign n339 = 64'hbbbbbff7bbbbff57 >> { i_7_, i_4_, i_5_, i_6_, n75, i_3_ }; + assign n340 = 32'd128 >> { n166, n179, n339, n308, n309 }; + assign n341 = 64'h0088088808880888 >> { n76, i_0_, i_1_, i_2_, n237, n264 }; + assign o_50_ = 64'h7fffffffffffffff >> { n341, n153, n154, n177, n257, n317 }; + assign o_11_ = 4'h8 >> { n92, n101 }; + assign n343 = 64'h0000aa020002aa02 >> { n101, n80, n97, n129, n184, n282 }; + assign n344 = 64'h0202020202020222 >> { n76, n113, n133, n101, n196, n267 }; + assign o_54_ = 32'd4294934527 >> { n135, n344, n280, n283, n343 }; + assign n346 = 64'h1111111111111115 >> { n76, i_4_, n113, n121, n97, n184 }; + assign n347 = 64'h0000000000000080 >> { o_25_, n135, n171, n154, n190, n195 }; + assign o_57_ = 32'd4294934527 >> { n115, n346, n347, n232, n280 }; + assign n101 = 8'h08 >> { i_2_, i_1_, i_0_ }; + assign o_12_ = 4'h8 >> { n103, n92 }; + assign n76 = 16'h0002 >> { i_5_, i_4_, i_6_, i_3_ }; + assign n103 = 8'h08 >> { i_1_, i_2_, i_0_ }; + assign o_13_ = 4'h8 >> { n90, n98 }; + assign o_14_ = 4'h8 >> { n78, n98 }; + assign o_16_ = 4'h8 >> { n98, n101 }; + assign o_17_ = 4'he >> { n108, n109 }; + assign n108 = 64'h0000000000000080 >> { i_2_, i_1_, i_5_, i_0_, i_4_, i_3_ }; + assign n109 = 64'h0000000000000008 >> { i_2_, i_1_, i_5_, i_3_, i_4_, i_0_ }; + assign o_18_ = 64'h0000000000000080 >> { i_1_, i_0_, i_5_, i_2_, i_4_, i_3_ }; + assign o_19_ = 32'd2 >> { i_2_, i_1_, i_0_, i_3_, i_4_ }; + assign o_22_ = 8'ha8 >> { n113, n95, n78 }; + assign o_21_ = 4'h8 >> { n76, n78 }; + assign n113 = 32'd128 >> { i_5_, i_4_, i_3_, i_6_, i_7_ }; + assign o_23_ = 8'h80 >> { n115, i_5_, i_3_ }; + assign n115 = 8'h01 >> { i_2_, i_1_, i_0_ }; + assign o_24_ = 4'h8 >> { n115, n117 }; + assign n117 = 32'd2 >> { i_5_, i_4_, i_3_, i_7_, i_6_ }; + assign o_25_ = 4'h8 >> { n90, n117 }; + assign o_30_ = 4'h8 >> { n120, i_7_ }; + assign n120 = 4'h8 >> { n93, n121 }; + assign n121 = 16'h0002 >> { i_5_, i_4_, i_3_, i_6_ }; + assign o_26_ = 8'h80 >> { n95, i_2_, i_0_ }; + assign n78 = 8'h02 >> { i_2_, i_1_, i_0_ }; + assign o_27_ = 4'h8 >> { n97, n117 }; + assign o_28_ = 4'h8 >> { n103, n113 }; + assign o_29_ = 8'h80 >> { n80, n115, i_7_ }; + assign o_31_ = 64'hffffffffffff7fff >> { i_1_, n210, n139, n142, n127, n136 }; + assign n127 = 16'h0008 >> { n93, n103, n130, n128 }; + assign n128 = 64'h555555555577457f >> { i_4_, i_7_, i_3_, i_6_, i_5_, n93 }; + assign n129 = 4'h8 >> { i_4_, i_3_ }; + assign n130 = 32'd1430603077 >> { i_6_, i_7_, i_5_, i_4_, n101 }; + assign n131 = 32'd353703231 >> { n133, n132, n80, n97, n90 }; + assign n132 = 8'h80 >> { i_5_, i_4_, i_3_ }; + assign o_20_ = 4'h8 >> { n78, n80 }; + assign n133 = 32'd134744064 >> { i_7_, i_6_, i_4_, i_5_, i_3_ }; + assign n134 = 8'h15 >> { n121, n97, n135 }; + assign n135 = 64'h0000000000000080 >> { i_2_, i_0_, i_5_, i_1_, i_4_, i_3_ }; + assign n136 = 8'h02 >> { n113, n137, n138 }; + assign n137 = 8'ha8 >> { n133, n129, n115 }; + assign n138 = 4'hd >> { i_3_, n75 }; + assign n139 = 4'h2 >> { o_17_, n141 }; + assign n140 = 32'd4194040827 >> { i_6_, i_7_, i_3_, i_4_, i_5_ }; + assign n141 = 32'd2880175035 >> { n78, i_7_, i_6_, i_5_, i_4_ }; + assign n142 = 8'h80 >> { n143, n144, n145 }; + assign n80 = 16'h0001 >> { i_5_, i_4_, i_3_, i_6_ }; + assign n143 = 16'hfddd >> { i_5_, i_4_, i_3_, n115 }; + assign n144 = 8'hd5 >> { i_6_, i_3_, n90 }; + assign n145 = 16'h9f1f >> { i_5_, n75, i_3_, i_4_ }; + assign n146 = 32'd4294966655 >> { i_4_, i_5_, i_6_, i_7_, i_3_ }; + assign o_32_ = 32'd2147483647 >> { n139, n148, n150, n156, n162 }; + assign n148 = 32'd8 >> { n149, n93, n103, n130, n128 }; + assign n149 = 8'ha8 >> { n113, n86, n115 }; + assign n150 = 16'h0080 >> { n97, n151, n154, n153 }; + assign n151 = 16'h1115 >> { n76, n113, n90, n152 }; + assign n152 = 32'd8 >> { i_2_, i_0_, i_3_, i_4_, i_1_ }; + assign o_0_ = 4'he >> { n76, n80 }; + assign n153 = 16'hfddd >> { i_4_, i_5_, i_3_, n78 }; + assign n154 = 64'h00011111000fffff >> { n90, n97, n80, n117, n129, n98 }; + assign n155 = 32'd128 >> { i_0_, i_3_, i_2_, i_4_, i_1_ }; + assign n156 = 16'h0008 >> { o_7_, n98, n157, n159 }; + assign n157 = 16'h1115 >> { n80, n95, n115, n158 }; + assign n158 = 64'h0000000000000002 >> { i_2_, i_0_, i_5_, i_4_, i_3_, i_1_ }; + assign n159 = 16'h555d >> { i_4_, i_5_, i_6_, n115 }; + assign n160 = 32'd221196079 >> { n75, n80, n115, o_5_, n161 }; + assign n161 = 32'd1467447159 >> { i_7_, i_5_, i_6_, i_4_, i_3_ }; + assign n162 = 16'hddd5 >> { i_4_, i_5_, i_3_, n75 }; + assign o_1_ = 4'h2 >> { i_5_, n83 }; + assign o_33_ = 64'h7fffffffffffffff >> { n164, n168, n174, n176, n296, n187 }; + assign n164 = 4'h2 >> { n167, n165 }; + assign n165 = 4'h1 >> { o_4_, n166 }; + assign n166 = 64'h0000000000008000 >> { i_5_, i_4_, i_0_, i_2_, i_1_, i_3_ }; + assign n167 = 16'h8000 >> { i_2_, i_1_, i_0_, i_4_ }; + assign n168 = 16'h0008 >> { n169, n97, n172, n170 }; + assign n169 = 4'h2 >> { n161, n115 }; + assign n170 = 16'h1101 >> { n140, n90, n171, n158 }; + assign n171 = 32'd128 >> { i_1_, i_0_, i_2_, i_4_, i_3_ }; + assign n172 = 8'h57 >> { n76, n113, n115 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act b/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act new file mode 100644 index 000000000..da4d0d675 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act @@ -0,0 +1,2622 @@ +tin_pdata_8_8_ 0.494400 0.496000 +tin_pdata_0_0_ 0.498000 0.497600 +tin_pdata_7_7_ 0.498200 0.502400 +preset_0_0_ 0.501000 0.495800 +tin_pdata_2_2_ 0.502000 0.496000 +tin_pdata_9_9_ 0.504400 0.504200 +tin_pdata_1_1_ 0.504400 0.490400 +tin_pdata_4_4_ 0.514000 0.494800 +pclk 0.513800 0.492400 +pirq_0_0_ 0.484800 0.506800 +tin_pdata_10_10_ 0.494000 0.502800 +tin_pdata_3_3_ 0.507600 0.509000 +tin_pdata_6_6_ 0.504200 0.500200 +tin_pdata_15_15_ 0.490200 0.491600 +tin_pdata_11_11_ 0.513000 0.498800 +tin_pdata_14_14_ 0.498200 0.505600 +tin_pdata_12_12_ 0.502400 0.497000 +tin_pdata_5_5_ 0.503000 0.498200 +preset 0.499800 0.500000 +tin_pdata_13_13_ 0.501200 0.502000 +ppeakb_7_7_ 0.000000 0.000000 +ppeakp_12_12_ 0.012000 0.012400 +ppeakp_0_0_ 0.020600 0.022800 +ppeaka_7_7_ 0.000000 0.000000 +ppeaki_15_15_ 0.004600 0.006000 +ppeaki_11_11_ 0.005600 0.006800 +ppeaki_3_3_ 0.005600 0.006800 +paddress_3_3_ 0.001400 0.001600 +ppeakb_14_14_ 0.000000 0.000000 +ppeakb_10_10_ 0.000000 0.000000 +ppeakb_8_8_ 0.000000 0.000000 +ppeakp_1_1_ 0.012600 0.012400 +ppeaka_14_14_ 0.000000 0.000000 +ppeaka_10_10_ 0.000400 0.000400 +ppeaka_8_8_ 0.000000 0.000000 +ppeaki_4_4_ 0.006600 0.008400 +paddress_15_15_ 0.001600 0.002400 +paddress_11_11_ 0.003200 0.003600 +paddress_2_2_ 0.000600 0.001200 +ppeakb_9_9_ 0.000000 0.000000 +ppeakp_2_2_ 0.012000 0.012000 +ppeaka_9_9_ 0.000000 0.000000 +ppeaks_12_12_ 0.008800 0.009200 +ppeaks_0_0_ 0.011000 0.012000 +ppeaki_5_5_ 0.006000 0.007200 +paddress_5_5_ 0.002400 0.002400 +ppeakb_15_15_ 0.000000 0.000000 +ppeakp_3_3_ 0.009400 0.009600 +pwr_0_0_ 0.037000 0.074000 +ppeaks_1_1_ 0.013200 0.012800 +ppeaki_6_6_ 0.005000 0.005600 +paddress_4_4_ 0.002800 0.002400 +piack_0_0_ 0.000000 0.000000 +ppeakp_13_13_ 0.010000 0.009600 +ppeakp_4_4_ 0.012200 0.011200 +ppeaka_15_15_ 0.000000 0.000000 +ppeaka_11_11_ 0.000400 0.000400 +ppeaks_2_2_ 0.010800 0.012000 +ppeaki_7_7_ 0.006000 0.006800 +paddress_10_10_ 0.002200 0.002000 +paddress_7_7_ 0.001200 0.001600 +ppeakp_5_5_ 0.009600 0.008400 +ppeaks_13_13_ 0.010200 0.010800 +ppeaks_3_3_ 0.010600 0.010400 +ppeaki_14_14_ 0.005000 0.006000 +ppeaki_10_10_ 0.004000 0.005200 +ppeaki_8_8_ 0.005400 0.006800 +paddress_6_6_ 0.002600 0.002400 +ppeakp_6_6_ 0.009200 0.008800 +ppeaks_4_4_ 0.010600 0.010400 +ppeaki_9_9_ 0.006800 0.006800 +paddress_9_9_ 0.001200 0.001600 +ppeakb_11_11_ 0.000000 0.000000 +ppeakp_7_7_ 0.010200 0.011600 +ppeaks_5_5_ 0.013000 0.012000 +paddress_13_13_ 0.002800 0.002400 +paddress_8_8_ 0.001400 0.001600 +ppeakp_14_14_ 0.009400 0.010000 +ppeakp_10_10_ 0.011800 0.012400 +ppeakp_8_8_ 0.007200 0.007200 +ppeaks_6_6_ 0.011800 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+n4278 0.000000 0.250100 +n601 0.001600 0.000002 +n4291 0.998400 0.000000 +n4292 0.999400 0.000000 +n4293_1 0.999400 0.000001 +n4294 1.000000 0.000000 +n4295 1.000000 0.000000 +n4296 1.000000 0.000000 +n4283 0.054600 0.007201 +n4288 0.015200 0.000000 +n4293 0.000400 0.250000 +n4298 0.000000 0.250100 +n337 0.001600 0.000003 +n4302 0.998800 0.000003 +n4303_1 0.998800 0.001199 +n4304 0.998800 0.000001 +n4305 0.999800 0.000000 +n4306 1.000000 0.000000 +n4307 0.999800 0.000000 +n4303 0.000000 0.250050 +n4308 0.000000 0.248175 +n4310 0.999800 0.000000 +n4311 1.000000 0.000000 +n4312 1.000000 0.000000 +n4313_1 1.000000 0.000000 +n4313 0.000000 0.250100 +n4318 0.000000 0.000000 +n4323 0.000000 0.216726 +n4328_1 0.000000 0.216726 +n4333_1 0.229600 0.000000 +n4338_1 0.000400 0.000001 +n4343_1 0.123600 0.000000 +n4321 0.243400 0.067009 +n385 0.037000 0.241580 +n4323_1 0.000000 0.002540 +n4324 0.968400 0.003715 +n4325 0.995400 0.000070 +n4348_1 0.098600 0.000024 +n4353_1 0.011800 0.000275 +n4358_1 0.064600 0.002816 +n4363_1 0.064600 0.002816 +n625 0.229200 0.130695 +n4331 0.542200 0.305549 +n4332 0.000200 0.000000 +n4333 0.902600 0.172248 +n4334 0.966400 0.002201 +n4335 1.000000 0.000000 +n4336 0.999600 0.000000 +n4337 0.097800 0.005493 +n4338 0.228800 0.353386 +n4339 0.999800 0.000000 +n4340 0.542200 0.283223 +n4368_1 0.064600 0.002816 +n4373_1 0.000000 0.216727 +n4378_1 0.064600 0.002816 +n4383_1 0.064600 0.002816 +n4388 0.064600 0.002816 +n4393 0.000000 0.216727 +n4398 0.024800 0.001635 +n4403 0.001400 0.000000 +n4408 0.002400 0.241350 +n4413 0.000600 0.000000 +n4418 0.064600 0.002816 +n613 0.018200 0.000665 +n4423 0.123600 0.022271 +n4428 0.003000 0.000000 +n4433 0.002200 0.241105 +n4438 0.000000 0.250100 +n4443 0.064600 0.002816 +n4448 0.123600 0.016054 +n4453 0.000200 0.000000 +n4458 0.003000 0.240817 +n4468 0.064600 0.002816 +n4473 0.000000 0.216727 +n4478 0.011600 0.000330 +n4483 0.000600 0.000000 +n4488 0.004000 0.239994 +n4493 0.000000 0.250100 +n669_1 0.119800 0.000001 +n4368 0.934000 0.123239 +n4369 0.934000 0.000000 +n4370 0.934000 0.008443 +n4371 0.935000 0.001842 +n4372 0.999600 0.000400 +n4373 0.000200 0.000000 +n4374 0.968600 0.000030 +n401 0.000000 0.000000 +n4498 0.000400 0.000000 +n4503 0.000000 0.250000 +n4508 0.000000 0.000000 +n645 0.008600 0.000001 +n4380 0.999400 0.000000 +n4381 0.999400 0.000002 +n4382 0.995000 0.248824 +n4383 0.999000 0.001998 +n4384 0.999000 0.000000 +n4385 0.999800 0.000000 +n4386 0.995400 0.000000 +n4513 0.000000 0.216728 +n4518_1 0.064600 0.002816 +n4523_1 0.000200 0.000000 +n345 0.000600 0.000001 +n4391 0.999400 0.001198 +n4392 0.999400 0.000002 +n4393_1 0.999800 0.000000 +n4394 1.000000 0.000000 +n4395 0.999800 0.000000 +n4396 1.000000 0.002913 +n4543 0.000000 0.250100 +n4548 0.000000 0.250050 +n301 0.001400 0.000002 +n4400 0.998600 0.000000 +n4401 0.999200 0.000000 +n4402 0.999200 0.000001 +n4403_1 0.999800 0.000000 +n4404 1.000000 0.000000 +n4405 0.999800 0.000000 +n4553 0.118400 0.074596 +n4558 0.000000 0.250100 +n4568 0.000200 0.000000 +n397 0.002800 0.000004 +n4410 0.998800 0.000003 +n4411 0.998800 0.001199 +n4412 0.998800 0.000002 +n4413_1 0.999800 0.000000 +n4414 1.000000 0.000000 +n4415 1.000000 0.000000 +n4416 0.999800 0.000000 +n373_1 0.002400 0.000001 +n4418_1 0.998800 0.000003 +n4419 0.998800 0.000000 +n4420 0.999800 0.000000 +n4421 0.999800 0.000000 +n4422 1.000000 0.000000 +n4423_1 1.000000 0.000000 +n4573 0.258000 0.024033 +n461 0.002600 0.000001 +n4426 0.998800 0.002396 +n4427 0.998800 0.000000 +n4428_1 0.998800 0.000001 +n4429 0.999600 0.000000 +n4430 1.000000 0.000000 +n4431 1.000000 0.000000 +n4578 0.064600 0.002816 +n4583 0.064600 0.002816 +n4588 0.000400 0.000000 +n4593 0.000000 0.249900 +n433_1 0.001200 0.000002 +n4437 0.998800 0.000000 +n4438_1 0.999200 0.000000 +n4439 0.999200 0.000001 +n4440 0.999800 0.000000 +n4441 1.000000 0.000000 +n4442 0.999800 0.000000 +n4598_1 0.000600 0.000007 +n4444 0.999200 0.000001 +n4445 0.999200 0.000000 +n4446 0.999600 0.000000 +n4447 1.000000 0.000000 +n4448_1 1.000000 0.000000 +n537 0.000000 0.000000 +n4450 1.000000 0.000000 +n4451 0.000000 0.000000 +n808 0.001200 0.000008 +n4453_1 0.999600 0.000000 +n4454 0.999600 0.000000 +n4455 0.003400 0.000026 +n4456 0.999800 0.000000 +n4457 0.830800 0.003436 +n4458_1 1.000000 0.000001 +n4459 1.000000 0.000000 +n521_1 0.000000 0.000000 +n4461 1.000000 0.000000 +n285 0.000000 0.000000 +n4463_1 1.000000 0.000000 +n309 0.000000 0.000000 +n1288 0.000000 0.000000 +n1303 0.000000 0.000000 +n4467 1.000000 0.000000 +n4468_1 0.999800 0.000374 +n481 0.000000 0.000139 +n4470 1.000000 0.000000 +n4471 1.000000 0.000000 +n557 0.000000 0.000000 +n1408_1 0.000400 0.000008 +n1583_1 0.000000 0.000008 +n2008 0.000200 0.000008 +n2708 0.000200 0.000008 +n4477 1.000000 0.000000 +n4478_1 1.000000 0.000000 +n305 0.000000 0.000000 +n3023 0.000000 0.000008 +n3043 0.000000 0.000000 +n4482 1.000000 0.000000 +n629_1 0.000000 0.000000 +n3433 0.000000 0.000000 +n4485 0.000000 0.000000 +n4486 1.000000 0.002138 +n417 0.000400 0.000597 +n4488_1 1.000000 0.000000 +n4489 0.000000 0.000000 +n589_1 0.000400 0.249752 +n4491 0.999800 0.000374 +n4492 1.000000 0.000001 +n649_1 0.000000 0.000000 +n3928_1 0.000000 0.000008 +n4495 1.000000 0.000000 +n4496 1.000000 0.000000 +n273_1 0.000000 0.000000 +n4498_1 0.999800 0.000374 +n4499 1.000000 0.000000 +n545 0.011200 0.016037 +n4501 0.999800 0.000000 +n4502 0.989400 0.000000 +n4503_1 0.988800 0.000037 +n4504 0.000800 0.016288 +n4505 0.999400 0.000000 +n4506 0.999200 0.036795 +n597 0.001600 0.000000 +n4508_1 0.991200 0.000000 +n4509 0.009600 0.011679 +n4510 1.000000 0.000000 +n4511 0.999800 0.000000 +n573 0.010200 0.000102 diff --git a/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif b/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif new file mode 100644 index 000000000..258a36af1 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif @@ -0,0 +1,7023 @@ +# Benchmark "frisc" written by ABC on Tue Mar 12 09:29:07 2019 +.model frisc +.inputs tin_pdata_8_8_ tin_pdata_0_0_ tin_pdata_7_7_ preset_0_0_ \ + tin_pdata_2_2_ tin_pdata_9_9_ tin_pdata_1_1_ tin_pdata_4_4_ pclk pirq_0_0_ \ + tin_pdata_10_10_ tin_pdata_3_3_ tin_pdata_6_6_ tin_pdata_15_15_ \ + tin_pdata_11_11_ tin_pdata_14_14_ tin_pdata_12_12_ tin_pdata_5_5_ preset \ + tin_pdata_13_13_ +.outputs ppeakb_7_7_ ppeakp_12_12_ ppeakp_0_0_ ppeaka_7_7_ ppeaki_15_15_ \ + ppeaki_11_11_ ppeaki_3_3_ paddress_3_3_ pdata_8_8_ pdata_0_0_ \ + ppeakb_14_14_ ppeakb_10_10_ ppeakb_8_8_ ppeakp_1_1_ ppeaka_14_14_ \ + ppeaka_10_10_ ppeaka_8_8_ ppeaki_4_4_ paddress_15_15_ paddress_11_11_ \ + paddress_2_2_ ppeakb_9_9_ ppeakp_2_2_ ppeaka_9_9_ ppeaks_12_12_ \ + ppeaks_0_0_ ppeaki_5_5_ paddress_5_5_ pdata_7_7_ ppeakb_15_15_ ppeakp_3_3_ \ + pwr_0_0_ ppeaks_1_1_ ppeaki_6_6_ paddress_4_4_ piack_0_0_ ppeakp_13_13_ \ + ppeakp_4_4_ ppeaka_15_15_ ppeaka_11_11_ ppeaks_2_2_ ppeaki_7_7_ \ + paddress_10_10_ paddress_7_7_ pdata_2_2_ ppeakp_5_5_ ppeaks_13_13_ \ + ppeaks_3_3_ ppeaki_14_14_ ppeaki_10_10_ ppeaki_8_8_ paddress_6_6_ \ + ppeakp_6_6_ ppeaks_4_4_ ppeaki_9_9_ paddress_9_9_ pdata_9_9_ pdata_1_1_ \ + ppeakb_11_11_ ppeakp_7_7_ ppeaks_5_5_ paddress_13_13_ paddress_8_8_ \ + ppeakp_14_14_ ppeakp_10_10_ ppeakp_8_8_ ppeaks_6_6_ ppeaki_13_13_ \ + pdata_4_4_ ppeakb_0_0_ ppeakp_9_9_ ppeaka_0_0_ ppeaks_7_7_ ppeakb_1_1_ \ + ppeaka_1_1_ ppeaks_10_10_ ppeaks_8_8_ pdata_10_10_ pdata_3_3_ \ + ppeakb_12_12_ ppeakb_2_2_ ppeaka_12_12_ ppeaka_2_2_ ppeaks_15_15_ \ + ppeaks_9_9_ ppeakb_3_3_ ppeakp_15_15_ ppeakp_11_11_ ppeaka_13_13_ \ + ppeaka_3_3_ paddress_14_14_ paddress_12_12_ pdata_6_6_ ppeakb_13_13_ \ + ppeakb_4_4_ pdn ppeaka_4_4_ ppeaki_0_0_ prd_0_0_ pdata_15_15_ pdata_11_11_ \ + ppeakb_5_5_ ppeaka_5_5_ ppeaks_14_14_ ppeaki_1_1_ paddress_1_1_ \ + pdata_14_14_ pdata_12_12_ pdata_5_5_ ppeakb_6_6_ ppeaka_6_6_ ppeaks_11_11_ \ + ppeaki_12_12_ ppeaki_2_2_ paddress_0_0_ pdata_13_13_ + +.latch n273_1 ppeakb_7_7_ re pclk 0 +.latch n277 ppeakp_12_12_ re pclk 0 +.latch n281 ppeakp_0_0_ re pclk 0 +.latch n285 ppeaka_7_7_ re pclk 0 +.latch n289 ppeaki_15_15_ re pclk 0 +.latch n293 ppeaki_11_11_ re pclk 0 +.latch n297 ppeaki_3_3_ re pclk 0 +.latch n301 paddress_3_3_ re pclk 0 +.latch n305 ppeakb_14_14_ re pclk 0 +.latch n309 ppeakb_10_10_ re pclk 0 +.latch n313_1 ppeakb_8_8_ re pclk 0 +.latch n317 ppeakp_1_1_ re pclk 0 +.latch n321 ppeaka_14_14_ re pclk 0 +.latch n325 ppeaka_10_10_ re pclk 0 +.latch n329 ppeaka_8_8_ re pclk 0 +.latch n333_1 ppeaki_4_4_ re pclk 0 +.latch n337 paddress_15_15_ re pclk 0 +.latch n341 paddress_11_11_ re pclk 0 +.latch n345 paddress_2_2_ re pclk 0 +.latch n349 ppeakb_9_9_ re pclk 0 +.latch n353_1 ppeakp_2_2_ re pclk 0 +.latch n357 ppeaka_9_9_ re pclk 0 +.latch n361 ppeaks_12_12_ re pclk 0 +.latch n365 ppeaks_0_0_ re pclk 0 +.latch n369 ppeaki_5_5_ re pclk 0 +.latch n373_1 paddress_5_5_ re pclk 0 +.latch n377 ppeakb_15_15_ re pclk 0 +.latch n381 ppeakp_3_3_ re pclk 0 +.latch n385 pwr_0_0_ re pclk 0 +.latch n389 ppeaks_1_1_ re pclk 0 +.latch n393_1 ppeaki_6_6_ re pclk 0 +.latch n397 paddress_4_4_ re pclk 0 +.latch n401 piack_0_0_ re pclk 0 +.latch n405 ppeakp_13_13_ re pclk 0 +.latch n409 ppeakp_4_4_ re pclk 0 +.latch n413_1 ppeaka_15_15_ re pclk 0 +.latch n417 ppeaka_11_11_ re pclk 0 +.latch n421 ppeaks_2_2_ re pclk 0 +.latch n425 ppeaki_7_7_ re pclk 0 +.latch n429 paddress_10_10_ re pclk 0 +.latch n433_1 paddress_7_7_ re pclk 0 +.latch n437 ppeakp_5_5_ re pclk 0 +.latch n441 ppeaks_13_13_ re pclk 0 +.latch n445 ppeaks_3_3_ re pclk 0 +.latch n449 ppeaki_14_14_ re pclk 0 +.latch n453_1 ppeaki_10_10_ re pclk 0 +.latch n457 ppeaki_8_8_ re pclk 0 +.latch n461 paddress_6_6_ re pclk 0 +.latch n465 ppeakp_6_6_ re pclk 0 +.latch n469 ppeaks_4_4_ re pclk 0 +.latch n473_1 ppeaki_9_9_ re pclk 0 +.latch n477 paddress_9_9_ re pclk 0 +.latch n481 ppeakb_11_11_ re pclk 0 +.latch n485 ppeakp_7_7_ re pclk 0 +.latch n489 ppeaks_5_5_ re pclk 0 +.latch n493_1 paddress_13_13_ re pclk 0 +.latch n497 paddress_8_8_ re pclk 0 +.latch n501 ppeakp_14_14_ re pclk 0 +.latch n505 ppeakp_10_10_ re pclk 0 +.latch n509 ppeakp_8_8_ re pclk 0 +.latch n513_1 ppeaks_6_6_ re pclk 0 +.latch n517_1 ppeaki_13_13_ re pclk 0 +.latch n521_1 ppeakb_0_0_ re pclk 0 +.latch n525 ppeakp_9_9_ re pclk 0 +.latch n529 ppeaka_0_0_ re pclk 0 +.latch n533 ppeaks_7_7_ re pclk 0 +.latch n537 ppeakb_1_1_ re pclk 0 +.latch n541 ppeaka_1_1_ re pclk 0 +.latch n545 ppeaks_10_10_ re pclk 0 +.latch n549_1 ppeaks_8_8_ re pclk 0 +.latch n553 ppeakb_12_12_ re pclk 0 +.latch n557 ppeakb_2_2_ re pclk 0 +.latch n561 ppeaka_12_12_ re pclk 0 +.latch n565 ppeaka_2_2_ re pclk 0 +.latch n569_1 ppeaks_15_15_ re pclk 0 +.latch n573 ppeaks_9_9_ re pclk 0 +.latch n577 ppeakb_3_3_ re pclk 0 +.latch n581 ppeakp_15_15_ re pclk 0 +.latch n585 ppeakp_11_11_ re pclk 0 +.latch n589_1 ppeaka_13_13_ re pclk 0 +.latch n593 ppeaka_3_3_ re pclk 0 +.latch n597 paddress_14_14_ re pclk 0 +.latch n601 paddress_12_12_ re pclk 0 +.latch n605 ppeakb_13_13_ re pclk 0 +.latch n609_1 ppeakb_4_4_ re pclk 0 +.latch n613 pdn re pclk 0 +.latch n617 ppeaka_4_4_ re pclk 0 +.latch n621 ppeaki_0_0_ re pclk 0 +.latch n625 prd_0_0_ re pclk 0 +.latch n629_1 ppeakb_5_5_ re pclk 0 +.latch n633 ppeaka_5_5_ re pclk 0 +.latch n637 ppeaks_14_14_ re pclk 0 +.latch n641 ppeaki_1_1_ re pclk 0 +.latch n645 paddress_1_1_ re pclk 0 +.latch n649_1 ppeakb_6_6_ re pclk 0 +.latch n653 ppeaka_6_6_ re pclk 0 +.latch n657 ppeaks_11_11_ re pclk 0 +.latch n661 ppeaki_12_12_ re pclk 0 +.latch n665 ppeaki_2_2_ re pclk 0 +.latch n669_1 paddress_0_0_ re pclk 0 +.latch n673 ndout re pclk 0 +.latch n678 [4295] re pclk 0 +.latch n683 [4310] re pclk 0 +.latch n688 [4355] re pclk 0 +.latch n693 [4370] re pclk 0 +.latch n698 [4385] re pclk 0 +.latch n703 [4400] re pclk 0 +.latch n708 [4415] re pclk 0 +.latch n713 [4430] re pclk 0 +.latch n718 [4445] re pclk 0 +.latch n723 [4460] re pclk 0 +.latch n728 [4475] re pclk 0 +.latch n733 [4490] re pclk 0 +.latch n738 [4505] re pclk 0 +.latch n743_1 [4520] re pclk 0 +.latch n748 [4535] re pclk 0 +.latch n753 [4550] re pclk 0 +.latch n758 [4565] re pclk 0 +.latch n763 [4580] re pclk 0 +.latch n768 [4595] re pclk 0 +.latch n773 [4610] re pclk 0 +.latch n778 [4625] re pclk 0 +.latch n783 [4640] re pclk 0 +.latch n788 [4655] re pclk 0 +.latch n793 [4670] re pclk 0 +.latch n798 [4700] re pclk 0 +.latch n803 [4715] re pclk 0 +.latch n808 [4730] re pclk 0 +.latch n813 [4745] re pclk 0 +.latch n818 [4760] re pclk 0 +.latch n823 [4775] re pclk 0 +.latch n828 [4790] re pclk 0 +.latch n833 [4805] re pclk 0 +.latch n838 [4820] re pclk 0 +.latch n843 [4835] re pclk 0 +.latch n848 [4850] re pclk 0 +.latch n853 [4865] re pclk 0 +.latch n858 [4880] re pclk 0 +.latch n863 [4895] re pclk 0 +.latch n868 [4910] re pclk 0 +.latch n873 [4925] re pclk 0 +.latch n878 [4940] re pclk 0 +.latch n883 [4955] re pclk 0 +.latch n888 [4970] re pclk 0 +.latch n893 [5015] re pclk 0 +.latch n898 [5030] re pclk 0 +.latch n903 [5075] re pclk 0 +.latch n908 [5090] re pclk 0 +.latch n913 [5105] re pclk 0 +.latch n918 [5120] re pclk 0 +.latch n923 [5135] re pclk 0 +.latch n928 [5150] re pclk 0 +.latch n933 [5165] re pclk 0 +.latch n938 [5180] re pclk 0 +.latch n943 [5195] re pclk 0 +.latch n948 [5210] re pclk 0 +.latch n953 [5225] re pclk 0 +.latch n958 [5240] re pclk 0 +.latch n963 [5255] re pclk 0 +.latch n968_1 [5270] re pclk 0 +.latch n973 [5285] re pclk 0 +.latch n978 [5300] re pclk 0 +.latch n983 [5315] re pclk 0 +.latch n988 [5330] re pclk 0 +.latch n993 [5345] re pclk 0 +.latch n998 [5360] re pclk 0 +.latch n1003 [5375] re pclk 0 +.latch n1008 [5390] re pclk 0 +.latch n1013 [5405] re pclk 0 +.latch n1018 [5420] re pclk 0 +.latch n1023 [5435] re pclk 0 +.latch n1028 [5450] re pclk 0 +.latch n1033 [5465] re pclk 0 +.latch n1038 [5480] re pclk 0 +.latch n1043 [5495] re pclk 0 +.latch n1048 [5510] re pclk 0 +.latch n1053 [5525] re pclk 0 +.latch n1058 [5540] re pclk 0 +.latch n1063 [5555] re pclk 0 +.latch n1068 [5570] re pclk 0 +.latch n1073 [5600] re pclk 0 +.latch n1078 [5615] re pclk 0 +.latch n1083 [5630] re pclk 0 +.latch n1088 [5645] re pclk 0 +.latch n1093 [5660] re pclk 0 +.latch n1098 [5675] re pclk 0 +.latch n1103 [5720] re pclk 0 +.latch n1108 [5780] re pclk 0 +.latch n1113 [5795] re pclk 0 +.latch n1118 [5810] re pclk 0 +.latch n1123 [5825] re pclk 0 +.latch n1128 [5840] re pclk 0 +.latch n1133 [5855] re pclk 0 +.latch n1138 [5870] re pclk 0 +.latch n1143 [5885] re pclk 0 +.latch n1148 [5900] re pclk 0 +.latch n1153 [5915] re pclk 0 +.latch n1158 [5930] re pclk 0 +.latch n1163 [5945] re pclk 0 +.latch n1168 [5960] re pclk 0 +.latch n1173 [5975] re pclk 0 +.latch n1178 [5990] re pclk 0 +.latch n1183_1 [6005] re pclk 0 +.latch n1188 [6020] re pclk 0 +.latch n1193 [6035] re pclk 0 +.latch n1198 [6050] re pclk 0 +.latch n1203 [6065] re pclk 0 +.latch n1208 [6080] re pclk 0 +.latch n1213 [6095] re pclk 0 +.latch n1218 [6110] re pclk 0 +.latch n1223 [6125] re pclk 0 +.latch n1228 [6140] re pclk 0 +.latch n1233 [6155] re pclk 0 +.latch n1238 [6170] re pclk 0 +.latch n1243 [6185] re pclk 0 +.latch n1248 [6200] re pclk 0 +.latch n1253 [6215] re pclk 0 +.latch n1258 [6230] re pclk 0 +.latch n1263 [6245] re pclk 0 +.latch n1268 [6260] re pclk 0 +.latch n1273 [6275] re pclk 0 +.latch n1278 [6290] re pclk 0 +.latch n1283 [6305] re pclk 0 +.latch n1288 [6320] re pclk 0 +.latch n1293 [6335] re pclk 0 +.latch n1298 [6350] re pclk 0 +.latch n1303 [6365] re pclk 0 +.latch n1308 [6410] re pclk 0 +.latch n1313 [6470] re pclk 0 +.latch n1318 [6485] re pclk 0 +.latch n1323 [6500] re pclk 0 +.latch n1328 [6515] re pclk 0 +.latch n1333 [6530] re pclk 0 +.latch n1338 [6545] re pclk 0 +.latch n1343 [6560] re pclk 0 +.latch n1348 [6575] re pclk 0 +.latch n1353 [6590] re pclk 0 +.latch n1358 [6605] re pclk 0 +.latch n1363 [6620] re pclk 0 +.latch n1368 [6635] re pclk 0 +.latch n1373 [6650] re pclk 0 +.latch n1378 [6665] re pclk 0 +.latch n1383 [6680] re pclk 0 +.latch n1388 [6695] re pclk 0 +.latch n1393_1 [6710] re pclk 0 +.latch n1398_1 [6725] re pclk 0 +.latch n1403_1 [6740] re pclk 0 +.latch n1408_1 [6755] re pclk 0 +.latch n1413_1 [6770] re pclk 0 +.latch n1418_1 [6785] re pclk 0 +.latch n1423_1 [6815] re pclk 0 +.latch n1428_1 [6830] re pclk 0 +.latch n1433_1 [6845] re pclk 0 +.latch n1438_1 [6860] re pclk 0 +.latch n1443_1 [6875] re pclk 0 +.latch n1448_1 [6890] re pclk 0 +.latch n1453_1 [6905] re pclk 0 +.latch n1458_1 [6920] re pclk 0 +.latch n1463_1 [6935] re pclk 0 +.latch n1468_1 [6950] re pclk 0 +.latch n1473_1 [6965] re pclk 0 +.latch n1478_1 [6980] re pclk 0 +.latch n1483_1 [6995] re pclk 0 +.latch n1488_1 [7010] re pclk 0 +.latch n1493_1 [7025] re pclk 0 +.latch n1498_1 [7055] re pclk 0 +.latch n1503_1 [7115] re pclk 0 +.latch n1508_1 [7130] re pclk 0 +.latch n1513_1 [7145] re pclk 0 +.latch n1518_1 [7160] re pclk 0 +.latch n1523_1 [7175] re pclk 0 +.latch n1528_1 [7190] re pclk 0 +.latch n1533_1 [7205] re pclk 0 +.latch n1538_1 [7220] re pclk 0 +.latch n1543_1 [7235] re pclk 0 +.latch n1548_1 [7250] re pclk 0 +.latch n1553_1 [7265] re pclk 0 +.latch n1558_1 [7280] re pclk 0 +.latch n1563_1 [7295] re pclk 0 +.latch n1568_1 [7310] re pclk 0 +.latch n1573_1 [7325] re pclk 0 +.latch n1578_1 [7340] re pclk 0 +.latch n1583_1 [7355] re pclk 0 +.latch n1588 [7370] re pclk 0 +.latch n1593 [7385] re pclk 0 +.latch n1598 [7400] re pclk 0 +.latch n1603 [7415] re pclk 0 +.latch n1608 [7430] re pclk 0 +.latch n1613 [7445] re pclk 0 +.latch n1618 [7460] re pclk 0 +.latch n1623 [7475] re pclk 0 +.latch n1628 [7490] re pclk 0 +.latch n1633 [7505] re pclk 0 +.latch n1638 [7520] re pclk 0 +.latch n1643 [7535] re pclk 0 +.latch n1648 [7550] re pclk 0 +.latch n1653 [7565] re pclk 0 +.latch n1658 [7580] re pclk 0 +.latch n1663 [7595] re pclk 0 +.latch n1668 [7625] re pclk 0 +.latch n1673 [7640] re pclk 0 +.latch n1678 [7655] re pclk 0 +.latch n1683 [7670] re pclk 0 +.latch n1688 [7685] re pclk 0 +.latch n1693 [7745] re pclk 0 +.latch n1698 [7760] re pclk 0 +.latch n1703 [7775] re pclk 0 +.latch n1708 [7790] re pclk 0 +.latch n1713 [7805] re pclk 0 +.latch n1718 [7820] re pclk 0 +.latch n1723 [7835] re pclk 0 +.latch n1728 [7850] re pclk 0 +.latch n1733 [7865] re pclk 0 +.latch n1738 [7880] re pclk 0 +.latch n1743 [7895] re pclk 0 +.latch n1748 [7910] re pclk 0 +.latch n1753 [7925] re pclk 0 +.latch n1758 [7940] re pclk 0 +.latch n1763 [7955] re pclk 0 +.latch n1768 [7970] re pclk 0 +.latch n1773 [8000] re pclk 0 +.latch n1778 [8015] re pclk 0 +.latch n1783 [8030] re pclk 0 +.latch n1788 [8045] re pclk 0 +.latch n1793 [8060] re pclk 0 +.latch n1798_1 [8075] re pclk 0 +.latch n1803 [8090] re pclk 0 +.latch n1808 [8105] re pclk 0 +.latch n1813 [8120] re pclk 0 +.latch n1818 [8135] re pclk 0 +.latch n1823 [8150] re pclk 0 +.latch n1828 [8165] re pclk 0 +.latch n1833 [8180] re pclk 0 +.latch n1838 [8195] re pclk 0 +.latch n1843 [8210] re pclk 0 +.latch n1848 [8225] re pclk 0 +.latch n1853 [8240] re pclk 0 +.latch n1858 [8255] re pclk 0 +.latch n1863 [8285] re pclk 0 +.latch n1868 [8300] re pclk 0 +.latch n1873 [8315] re pclk 0 +.latch n1878 [8330] re pclk 0 +.latch n1883 [8390] re pclk 0 +.latch n1888 [8405] re pclk 0 +.latch n1893 [8420] re pclk 0 +.latch n1898 [8435] re pclk 0 +.latch n1903 [8450] re pclk 0 +.latch n1908 [8465] re pclk 0 +.latch n1913 [8480] re pclk 0 +.latch n1918 [8495] re pclk 0 +.latch n1923 [8510] re pclk 0 +.latch n1928 [8525] re pclk 0 +.latch n1933 [8540] re pclk 0 +.latch n1938 [8555] re pclk 0 +.latch n1943 [8570] re pclk 0 +.latch n1948 [8585] re pclk 0 +.latch n1953 [8600] re pclk 0 +.latch n1958 [8615] re pclk 0 +.latch n1963 [8630] re pclk 0 +.latch n1968 [8645] re pclk 0 +.latch n1973 [8660] re pclk 0 +.latch n1978 [8675] re pclk 0 +.latch n1983 [8690] re pclk 0 +.latch n1988 [8705] re pclk 0 +.latch n1993 [8720] re pclk 0 +.latch n1998 [8735] re pclk 0 +.latch n2003 [8750] re pclk 0 +.latch n2008 [8765] re pclk 0 +.latch n2013 [8780] re pclk 0 +.latch n2018 [8810] re pclk 0 +.latch n2023 [8825] re pclk 0 +.latch n2028 [8840] re pclk 0 +.latch n2033 [8855] re pclk 0 +.latch n2038 [8870] re pclk 0 +.latch n2043 [8885] re pclk 0 +.latch n2048 [8900] re pclk 0 +.latch n2053 [8915] re pclk 0 +.latch n2058 [8930] re pclk 0 +.latch n2063 [8945] re pclk 0 +.latch n2068 [8960] re pclk 0 +.latch n2073 [8975] re pclk 0 +.latch n2078 [9050] re pclk 0 +.latch n2083 [9065] re pclk 0 +.latch n2088 [9080] re pclk 0 +.latch n2093 [9095] re pclk 0 +.latch n2098 [9110] re pclk 0 +.latch n2103 [9125] re pclk 0 +.latch n2108 [9140] re pclk 0 +.latch n2113 [9155] re pclk 0 +.latch n2118 [9170] re pclk 0 +.latch n2123 [9185] re pclk 0 +.latch n2128 [9200] re pclk 0 +.latch n2133 [9215] re pclk 0 +.latch n2138 [9230] re pclk 0 +.latch n2143 [9245] re pclk 0 +.latch n2148 [9260] re pclk 0 +.latch n2153 [9275] re pclk 0 +.latch n2158 [9290] re pclk 0 +.latch n2163 [9305] re pclk 0 +.latch n2168 [9320] re pclk 0 +.latch n2173 [9335] re pclk 0 +.latch n2178 [9350] re pclk 0 +.latch n2183 [9365] re pclk 0 +.latch n2188_1 [9380] re pclk 0 +.latch n2193_1 [9395] re pclk 0 +.latch n2198_1 [9410] re pclk 0 +.latch n2203_1 [9440] re pclk 0 +.latch n2208_1 [9455] re pclk 0 +.latch n2213_1 [9470] re pclk 0 +.latch n2218_1 [9485] re pclk 0 +.latch n2223_1 [9500] re pclk 0 +.latch n2228_1 [9515] re pclk 0 +.latch n2233_1 [9530] re pclk 0 +.latch n2238_1 [9545] re pclk 0 +.latch n2243_1 [9560] re pclk 0 +.latch n2248_1 [9575] re pclk 0 +.latch n2253_1 [9590] re pclk 0 +.latch n2258_1 [9605] re pclk 0 +.latch n2263_1 [9620] re pclk 0 +.latch n2268 [9635] re pclk 0 +.latch n2273 [9650] re pclk 0 +.latch n2278 [9665] re pclk 0 +.latch n2283 [9680] re pclk 0 +.latch n2288 [9710] re pclk 0 +.latch n2293 [9725] re pclk 0 +.latch n2298 [9740] re pclk 0 +.latch n2303 [9770] re pclk 0 +.latch n2308 [9785] re pclk 0 +.latch n2313 [9800] re pclk 0 +.latch n2318 [9815] re pclk 0 +.latch n2323 [9830] re pclk 0 +.latch n2328 [9845] re pclk 0 +.latch n2333 [9860] re pclk 0 +.latch n2338 [9875] re pclk 0 +.latch n2343 [9890] re pclk 0 +.latch n2348 [9905] re pclk 0 +.latch n2353 [9920] re pclk 0 +.latch n2358 [9935] re pclk 0 +.latch n2363 [9950] re pclk 0 +.latch n2368 [9980] re pclk 0 +.latch n2373 [9995] re pclk 0 +.latch n2378 [10010] re pclk 0 +.latch n2383 [10025] re pclk 0 +.latch n2388 [10040] re pclk 0 +.latch n2393 [10055] re pclk 0 +.latch n2398 [10070] re pclk 0 +.latch n2403 [10085] re pclk 0 +.latch n2408 [10100] re pclk 0 +.latch n2413 [10115] re pclk 0 +.latch n2418 [10130] re pclk 0 +.latch n2423 [10145] re pclk 0 +.latch n2428 [10175] re pclk 0 +.latch n2433 [10190] re pclk 0 +.latch n2438 [10205] re pclk 0 +.latch n2443 [10220] re pclk 0 +.latch n2448 [10265] re pclk 0 +.latch n2453 [10280] re pclk 0 +.latch n2458 [10310] re pclk 0 +.latch n2463 [10325] re pclk 0 +.latch n2468 [10340] re pclk 0 +.latch n2473 [10355] re pclk 0 +.latch n2478 [10370] re pclk 0 +.latch n2483 [10400] re pclk 0 +.latch n2488 [10415] re pclk 0 +.latch n2493 [10430] re pclk 0 +.latch n2498 [10445] re pclk 0 +.latch n2503 [10460] re pclk 0 +.latch n2508 [10475] re pclk 0 +.latch n2513 [10490] re pclk 0 +.latch n2518 [10505] re pclk 0 +.latch n2523 [10550] re pclk 0 +.latch n2528 [10565] re pclk 0 +.latch n2533 [10580] re pclk 0 +.latch n2538 [10595] re pclk 0 +.latch n2543 [10610] re pclk 0 +.latch n2548 [10625] re pclk 0 +.latch n2553 [10655] re pclk 0 +.latch n2558 [10670] re pclk 0 +.latch n2563 [10685] re pclk 0 +.latch n2568 [10700] re pclk 0 +.latch n2573 [10715] re pclk 0 +.latch n2578 [10730] re pclk 0 +.latch n2583 [10745] re pclk 0 +.latch n2588 [10760] re pclk 0 +.latch n2593 [10775] re pclk 0 +.latch n2598 [10790] re pclk 0 +.latch n2603 [10805] re pclk 0 +.latch n2608 [10820] re pclk 0 +.latch n2613 [10850] re pclk 0 +.latch n2618 [10865] re pclk 0 +.latch n2623 [10880] re pclk 0 +.latch n2628 [10895] re pclk 0 +.latch n2633 [10925] re pclk 0 +.latch n2638 [10940] re pclk 0 +.latch n2643 [10955] re pclk 0 +.latch n2648 [10970] re pclk 0 +.latch n2653 [10985] re pclk 0 +.latch n2658 [11015] re pclk 0 +.latch n2663 [11030] re pclk 0 +.latch n2668 [11045] re pclk 0 +.latch n2673 [11060] re pclk 0 +.latch n2678 [11075] re pclk 0 +.latch n2683 [11090] re pclk 0 +.latch n2688 [11120] re pclk 0 +.latch n2693 [11135] re pclk 0 +.latch n2698_1 [11150] re pclk 0 +.latch n2703 [11165] re pclk 0 +.latch n2708 [11180] re pclk 0 +.latch n2713 [11195] re pclk 0 +.latch n2718 [11210] re pclk 0 +.latch n2723 [11225] re pclk 0 +.latch n2728 [11240] re pclk 0 +.latch n2733 [11255] re pclk 0 +.latch n2738 [11270] re pclk 0 +.latch n2743 [11285] re pclk 0 +.latch n2748 [11300] re pclk 0 +.latch n2753 [11315] re pclk 0 +.latch n2758 [11330] re pclk 0 +.latch n2763 [11345] re pclk 0 +.latch n2768 [11375] re pclk 0 +.latch n2773 [11390] re pclk 0 +.latch n2778 [11405] re pclk 0 +.latch n2783 [11420] re pclk 0 +.latch n2788 [11435] re pclk 0 +.latch n2793_1 [11450] re pclk 0 +.latch n2798_1 [11465] re pclk 0 +.latch n2803_1 [11480] re pclk 0 +.latch n2808_1 [11495] re pclk 0 +.latch n2813_1 [11510] re pclk 0 +.latch n2818_1 [11525] re pclk 0 +.latch n2823_1 [11540] re pclk 0 +.latch n2828_1 [11555] re pclk 0 +.latch n2833_1 [11570] re pclk 0 +.latch n2838_1 [11585] re pclk 0 +.latch n2843_1 [11600] re pclk 0 +.latch n2848_1 [11615] re pclk 0 +.latch n2853 [11630] re pclk 0 +.latch n2858 [11645] re pclk 0 +.latch n2863 [11660] re pclk 0 +.latch n2868 [11675] re pclk 0 +.latch n2873 [11690] re pclk 0 +.latch n2878 [11705] re pclk 0 +.latch n2883 [11720] re pclk 0 +.latch n2888 [11735] re pclk 0 +.latch n2893 [11750] re pclk 0 +.latch n2898 [11765] re pclk 0 +.latch n2903 [11780] re pclk 0 +.latch n2908 [11795] re pclk 0 +.latch n2913 [11810] re pclk 0 +.latch n2918 [11885] re pclk 0 +.latch n2923 [11900] re pclk 0 +.latch n2928 [11915] re pclk 0 +.latch n2933 [11930] re pclk 0 +.latch n2938 [12005] re pclk 0 +.latch n2943 [12020] re pclk 0 +.latch n2948 [12035] re pclk 0 +.latch n2953 [12050] re pclk 0 +.latch n2958 [12065] re pclk 0 +.latch n2963 [12080] re pclk 0 +.latch n2968 [12125] re pclk 0 +.latch n2973 [12140] re pclk 0 +.latch n2978_1 [12155] re pclk 0 +.latch n2983 [12170] re pclk 0 +.latch n2988 [12185] re pclk 0 +.latch n2993 [12200] re pclk 0 +.latch n2998 [12245] re pclk 0 +.latch n3003 [12260] re pclk 0 +.latch n3008 [12275] re pclk 0 +.latch n3013 [12335] re pclk 0 +.latch n3018 [12350] re pclk 0 +.latch n3023 [12365] re pclk 0 +.latch n3028 [12380] re pclk 0 +.latch n3033 [12395] re pclk 0 +.latch n3038 [12410] re pclk 0 +.latch n3043 [12425] re pclk 0 +.latch n3048 [12440] re pclk 0 +.latch n3053 [12455] re pclk 0 +.latch n3058 [12470] re pclk 0 +.latch n3063 [12485] re pclk 0 +.latch n3068 [12545] re pclk 0 +.latch n3073 [12560] re pclk 0 +.latch n3078 [12575] re pclk 0 +.latch n3083 [12590] re pclk 0 +.latch n3088 [12605] re pclk 0 +.latch n3093 [12620] re pclk 0 +.latch n3098 [12635] re pclk 0 +.latch n3103 [12650] re pclk 0 +.latch n3108 [12665] re pclk 0 +.latch n3113 [12680] re pclk 0 +.latch n3118 [12695] re pclk 0 +.latch n3123 [12770] re pclk 0 +.latch n3128 [12800] re pclk 0 +.latch n3133 [12815] re pclk 0 +.latch n3138 [12830] re pclk 0 +.latch n3143 [12845] re pclk 0 +.latch n3148 [12860] re pclk 0 +.latch n3153 [12875] re pclk 0 +.latch n3158_1 [12890] re pclk 0 +.latch n3163_1 [12905] re pclk 0 +.latch n3168_1 [12920] re pclk 0 +.latch n3173_1 [12935] re pclk 0 +.latch n3178_1 [13010] re pclk 0 +.latch n3183_1 [13025] re pclk 0 +.latch n3188_1 [13040] re pclk 0 +.latch n3193_1 [13055] re pclk 0 +.latch n3198_1 [13070] re pclk 0 +.latch n3203_1 [13085] re pclk 0 +.latch n3208_1 [13100] re pclk 0 +.latch n3213_1 [13115] re pclk 0 +.latch n3218_1 [13130] re pclk 0 +.latch n3223_1 [13160] re pclk 0 +.latch n3228_1 [13175] re pclk 0 +.latch n3233_1 [13220] re pclk 0 +.latch n3238_1 [13235] re pclk 0 +.latch n3243_1 [13250] re pclk 0 +.latch n3248_1 [13265] re pclk 0 +.latch n3253_1 [13280] re pclk 0 +.latch n3258_1 [13295] re pclk 0 +.latch n3263_1 [13310] re pclk 0 +.latch n3268 [13325] re pclk 0 +.latch n3273 [13340] re pclk 0 +.latch n3278 [13355] re pclk 0 +.latch n3283 [13370] re pclk 0 +.latch n3288 [13385] re pclk 0 +.latch n3293 [13400] re pclk 0 +.latch n3298 [13415] re pclk 0 +.latch n3303 [13430] re pclk 0 +.latch n3308 [13445] re pclk 0 +.latch n3313 [13460] re pclk 0 +.latch n3318 [13475] re pclk 0 +.latch n3323 [13490] re pclk 0 +.latch n3328 [13505] re pclk 0 +.latch n3333 [13550] re pclk 0 +.latch n3338 [13580] re pclk 0 +.latch n3343 [13595] re pclk 0 +.latch n3348 [13610] re pclk 0 +.latch n3353 [13625] re pclk 0 +.latch n3358 [13640] re pclk 0 +.latch n3363 [13655] re pclk 0 +.latch n3368 [13670] re pclk 0 +.latch n3373 [13685] re pclk 0 +.latch n3378 [13700] re pclk 0 +.latch n3383 [13715] re pclk 0 +.latch n3388 [13730] re pclk 0 +.latch n3393_1 [13745] re pclk 0 +.latch n3398 [13775] re pclk 0 +.latch n3403 [13790] re pclk 0 +.latch n3408 [13805] re pclk 0 +.latch n3413 [13820] re pclk 0 +.latch n3418 [13835] re pclk 0 +.latch n3423 [13850] re pclk 0 +.latch n3428 [13865] re pclk 0 +.latch n3433 [13880] re pclk 0 +.latch n3438 [13895] re pclk 0 +.latch n3443 [13955] re pclk 0 +.latch n3448 [13970] re pclk 0 +.latch n3453 [13985] re pclk 0 +.latch n3458 [14000] re pclk 0 +.latch n3463 [14015] re pclk 0 +.latch n3468 [14030] re pclk 0 +.latch n3473 [14045] re pclk 0 +.latch n3478 [14060] re pclk 0 +.latch n3483 [14075] re pclk 0 +.latch n3488 [14090] re pclk 0 +.latch n3493 [14105] re pclk 0 +.latch n3498 [14120] re pclk 0 +.latch n3503 [14135] re pclk 0 +.latch n3508 [14150] re pclk 0 +.latch n3513 [14165] re pclk 0 +.latch n3518 [14180] re pclk 0 +.latch n3523 [14210] re pclk 0 +.latch n3528_1 [14225] re pclk 0 +.latch n3533_1 [14240] re pclk 0 +.latch n3538 [14255] re pclk 0 +.latch n3543 [14270] re pclk 0 +.latch n3548 [14285] re pclk 0 +.latch n3553 [14360] re pclk 0 +.latch n3558 [14375] re pclk 0 +.latch n3563 [14390] re pclk 0 +.latch n3568 [14405] re pclk 0 +.latch n3573 [14420] re pclk 0 +.latch n3578 [14435] re pclk 0 +.latch n3583 [14450] re pclk 0 +.latch n3588 [14465] re pclk 0 +.latch n3593 [14480] re pclk 0 +.latch n3598 [14495] re pclk 0 +.latch n3603 [14510] re pclk 0 +.latch n3608 [14525] re pclk 0 +.latch n3613 [14540] re pclk 0 +.latch n3618 [14555] re pclk 0 +.latch n3623 [14570] re pclk 0 +.latch n3628 [14585] re pclk 0 +.latch n3633 [14600] re pclk 0 +.latch n3638 [14615] re pclk 0 +.latch n3643_1 [14630] re pclk 0 +.latch n3648_1 [14660] re pclk 0 +.latch n3653 [14675] re pclk 0 +.latch n3658 [14690] re pclk 0 +.latch n3663 [14705] re pclk 0 +.latch n3668 [14765] re pclk 0 +.latch n3673 [14810] re pclk 0 +.latch n3678 [14825] re pclk 0 +.latch n3683 [14840] re pclk 0 +.latch n3688 [14855] re pclk 0 +.latch n3693 [14870] re pclk 0 +.latch n3698 [14885] re pclk 0 +.latch n3703 [14900] re pclk 0 +.latch n3708 [14915] re pclk 0 +.latch n3713 [14930] re pclk 0 +.latch n3718 [14960] re pclk 0 +.latch n3723 [14975] re pclk 0 +.latch n3728 [14990] re pclk 0 +.latch n3733 [15005] re pclk 0 +.latch n3738 [15020] re pclk 0 +.latch n3743 [15035] re pclk 0 +.latch n3748 [15050] re pclk 0 +.latch n3753 [15065] re pclk 0 +.latch n3758_1 [15080] re pclk 0 +.latch n3763_1 [15140] re pclk 0 +.latch n3768_1 [15185] re pclk 0 +.latch n3773 [15200] re pclk 0 +.latch n3778 [15215] re pclk 0 +.latch n3783 [15230] re pclk 0 +.latch n3788 [15245] re pclk 0 +.latch n3793 [15260] re pclk 0 +.latch n3798 [15275] re pclk 0 +.latch n3803 [15290] re pclk 0 +.latch n3808 [15305] re pclk 0 +.latch n3813 [15320] re pclk 0 +.latch n3818 [15335] re pclk 0 +.latch n3823 [15350] re pclk 0 +.latch n3828 [15365] re pclk 0 +.latch n3833 [15380] re pclk 0 +.latch n3838 [15395] re pclk 0 +.latch n3843 [15410] re pclk 0 +.latch n3848 [15425] re pclk 0 +.latch n3853 [15440] re pclk 0 +.latch n3858 [15500] re pclk 0 +.latch n3863 [15515] re pclk 0 +.latch n3868 [15545] re pclk 0 +.latch n3873 [15560] re pclk 0 +.latch n3878_1 [15575] re pclk 0 +.latch n3883_1 [15590] re pclk 0 +.latch n3888_1 [15605] re pclk 0 +.latch n3893_1 [15620] re pclk 0 +.latch n3898_1 [15635] re pclk 0 +.latch n3903_1 [15650] re pclk 0 +.latch n3908_1 [15665] re pclk 0 +.latch n3913_1 [15680] re pclk 0 +.latch n3918_1 [15695] re pclk 0 +.latch n3923_1 [15710] re pclk 0 +.latch n3928_1 [15725] re pclk 0 +.latch n3933_1 [15755] re pclk 0 +.latch n3938_1 [15770] re pclk 0 +.latch n3943_1 [15785] re pclk 0 +.latch n3948_1 [15845] re pclk 0 +.latch n3953_1 [15860] re pclk 0 +.latch n3958 [15890] re pclk 0 +.latch n3963 [15905] re pclk 0 +.latch n3968 [15920] re pclk 0 +.latch n3973 [15935] re pclk 0 +.latch n3978 [15950] re pclk 0 +.latch n3983 [15965] re pclk 0 +.latch n3988 [15980] re pclk 0 +.latch n3993 [15995] re pclk 0 +.latch n3998 [16010] re pclk 0 +.latch n4003 [16025] re pclk 0 +.latch n4008 [16040] re pclk 0 +.latch n4013 [16055] re pclk 0 +.latch n4018 [16070] re pclk 0 +.latch n4023 [16085] re pclk 0 +.latch n4028 [16100] re pclk 0 +.latch n4033 [16907] re pclk 0 +.latch n4038 [16920] re pclk 0 +.latch n4043 [16933] re pclk 0 +.latch n4048 [16959] re pclk 0 +.latch n4053 [16972] re pclk 0 +.latch n4058 [16985] re pclk 0 +.latch n4063 [16998] re pclk 0 +.latch n4068 [17011] re pclk 0 +.latch n4073 [17024] re pclk 0 +.latch n4078 [17037] re pclk 0 +.latch n4083 [17050] re pclk 0 +.latch n4088 [17063] re pclk 0 +.latch n4093 [17076] re pclk 0 +.latch n4098 [17089] re pclk 0 +.latch n4103 [17102] re pclk 0 +.latch n4108 [17115] re pclk 0 +.latch n4113 [17128] re pclk 0 +.latch n4118 [17141] re pclk 0 +.latch n4123 [17154] re pclk 0 +.latch n4128 [17167] re pclk 0 +.latch n4133 [17180] re pclk 0 +.latch n4138 [17193] re pclk 0 +.latch n4143 [17206] re pclk 0 +.latch n4148 [17219] re pclk 0 +.latch n4153 [17232] re pclk 0 +.latch n4158 [17245] re pclk 0 +.latch n4163 [17258] re pclk 0 +.latch n4168 [17271] re pclk 0 +.latch n4173 [17284] re pclk 0 +.latch n4178 [17297] re pclk 0 +.latch n4183 [17310] re pclk 0 +.latch n4188 [17323] re pclk 0 +.latch n4193 [17336] re pclk 0 +.latch n4198 [17349] re pclk 0 +.latch n4203_1 [17362] re pclk 0 +.latch n4208_1 [17375] re pclk 0 +.latch n4213_1 [17388] re pclk 0 +.latch n4218_1 [17414] re pclk 0 +.latch n4223_1 [17427] re pclk 0 +.latch n4228 [17453] re pclk 0 +.latch n4233 [17479] re pclk 0 +.latch n4238 [17492] re pclk 0 +.latch n4243 [17505] re pclk 0 +.latch n4248 [17518] re pclk 0 +.latch n4253 [17531] re pclk 0 +.latch n4258 [17544] re pclk 0 +.latch n4263 [17570] re pclk 0 +.latch n4268 [17583] re pclk 0 +.latch n4273 [17596] re pclk 0 +.latch n4278 [17609] re pclk 0 +.latch n4283 [17635] re pclk 0 +.latch n4288 [17648] re pclk 0 +.latch n4293 [17661] re pclk 0 +.latch n4298 [17674] re pclk 0 +.latch n4303 [17700] re pclk 0 +.latch n4308 [17713] re pclk 0 +.latch n4313 [17739] re pclk 0 +.latch n4318 [17752] re pclk 0 +.latch n4323 [17765] re pclk 0 +.latch n4328_1 [17778] re pclk 0 +.latch n4333_1 [17791] re pclk 0 +.latch n4338_1 [17804] re pclk 0 +.latch n4343_1 [17817] re pclk 0 +.latch n4348_1 [17843] re pclk 0 +.latch n4353_1 [17856] re pclk 0 +.latch n4358_1 [17869] re pclk 0 +.latch n4363_1 [17882] re pclk 0 +.latch n4368_1 [17908] re pclk 0 +.latch n4373_1 [17921] re pclk 0 +.latch n4378_1 [17934] re pclk 0 +.latch n4383_1 [17947] re pclk 0 +.latch n4388 [17960] re pclk 0 +.latch n4393 [17973] re pclk 0 +.latch n4398 [17986] re pclk 0 +.latch n4403 [17999] re pclk 0 +.latch n4408 [18012] re pclk 0 +.latch n4413 [18025] re pclk 0 +.latch n4418 [18038] re pclk 0 +.latch n4423 [18064] re pclk 0 +.latch n4428 [18077] re pclk 0 +.latch n4433 [18090] re pclk 0 +.latch n4438 [18103] re pclk 0 +.latch n4443 [18116] re pclk 0 +.latch n4448 [18129] re pclk 0 +.latch n4453 [18142] re pclk 0 +.latch n4458 [18155] re pclk 0 +.latch n4463 [18168] re pclk 0 +.latch n4468 [18181] re pclk 0 +.latch n4473 [18194] re pclk 0 +.latch n4478 [18207] re pclk 0 +.latch n4483 [18220] re pclk 0 +.latch n4488 [18233] re pclk 0 +.latch n4493 [18246] re pclk 0 +.latch n4498 [18285] re pclk 0 +.latch n4503 [18298] re pclk 0 +.latch n4508 [18311] re pclk 0 +.latch n4513 [18337] re pclk 0 +.latch n4518_1 [18350] re pclk 0 +.latch n4523_1 [18363] re pclk 0 +.latch n4528_1 [18376] re pclk 0 +.latch n4533_1 [18389] re pclk 0 +.latch n4538 [18415] re pclk 0 +.latch n4543 [18428] re pclk 0 +.latch n4548 [18441] re pclk 0 +.latch n4553 [18467] re pclk 0 +.latch n4558 [18480] re pclk 0 +.latch n4563 [18493] re pclk 0 +.latch n4568 [18506] re pclk 0 +.latch n4573 [18545] re pclk 0 +.latch n4578 [18571] re pclk 0 +.latch n4583 [18584] re pclk 0 +.latch n4588 [18597] re pclk 0 +.latch n4593 [18610] re pclk 0 +.latch n4598_1 [18636] re pclk 0 + +.names [17882] tin_pdata_8_8_ [16959] pdata_8_8_ +01- 1 +1-1 1 +.names [17479] tin_pdata_0_0_ [18337] pdata_0_0_ +01- 1 +1-1 1 +.names [17869] tin_pdata_7_7_ [16907] pdata_7_7_ +01- 1 +1-1 1 +.names [18181] tin_pdata_2_2_ [17323] pdata_2_2_ +01- 1 +1-1 1 +.names [18571] tin_pdata_9_9_ [17765] pdata_9_9_ +01- 1 +1-1 1 +.names [18116] tin_pdata_1_1_ [17258] pdata_1_1_ +01- 1 +1-1 1 +.names [18038] tin_pdata_4_4_ [17193] pdata_4_4_ +01- 1 +1-1 1 +.names [17011] tin_pdata_10_10_ [17921] pdata_10_10_ +01- 1 +1-1 1 +.names [17960] tin_pdata_3_3_ [17128] pdata_3_3_ +01- 1 +1-1 1 +.names [17934] tin_pdata_6_6_ [17063] pdata_6_6_ +01- 1 +1-1 1 +.names [17947] tin_pdata_15_15_ [17076] pdata_15_15_ +01- 1 +1-1 1 +.names [17336] tin_pdata_11_11_ [18194] pdata_11_11_ +01- 1 +1-1 1 +.names [18584] tin_pdata_14_14_ [17778] pdata_14_14_ +01- 1 +1-1 1 +.names [17141] tin_pdata_12_12_ [17973] pdata_12_12_ +01- 1 +1-1 1 +.names [17908] tin_pdata_5_5_ [16998] pdata_5_5_ +01- 1 +1-1 1 +.names [18350] tin_pdata_13_13_ [17492] pdata_13_13_ +01- 1 +1-1 1 +.names preset [17791] [17843] ndout pdata_2_2_ n673 +00-1- 1 +010-1 1 +0-11- 1 +.names n2866 n2815 n2862 ppeakb_12_12_ n2855 n553 +0---- 1 +-01-- 1 +---10 1 +.names n2843 n2816 [15260] [9230] n2853_1 n2851 n2815 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names [13325] n2817 n2838 [5945] [8495] n2840 n2816 +11---- 0 +--11-- 0 +----11 0 +.names n2836 n2818 n2817 +10 1 +.names n2825 n2819 n2818 +11 1 +.names n2820 [17596] pdn [17089] n2819 +10-- 0 +--10 0 +.names [17986] n2821 [17804] n2820 +110 1 +.names [18207] [17856] n2822 n2824 [12695] [10820] n2821 +0-1100 0 +10---- 0 +.names n2823 [12185] [12935] [11600] [11345] n2822 +10000 1 +.names [10805] [12485] [12200] [12275] n2823 +0000 1 +.names [11585] [11090] [11930] [12065] [11810] [12080] n2824 +000000 1 +.names [18636] n4509 n2834 n2825 +01- 1 +0-0 1 +.names n2829 n2828 n2827 n2826 +111 1 +.names [17531] [18090] [18155] ppeaki_3_3_ ppeaki_0_0_ n2827 +0--10 1 +110-- 1 +.names [17531] [18012] ppeaki_2_2_ n2828 +0-1 1 +11- 1 +.names [17531] ppeaki_1_1_ [18233] n2829 +00- 1 +1-0 1 +.names ppeaki_5_5_ ppeaki_7_7_ ppeaki_6_6_ [17752] n2830 +1000 1 +.names [17531] [18090] [18012] ppeaki_2_2_ ppeaki_3_3_ n2831 +0--00 1 +100-- 1 +.names [17531] ppeaki_0_0_ ppeaki_1_1_ [18155] [18233] n2832 +010-- 1 +1--10 1 +.names n2834 [18636] n2835 n2829 n2831 n2833 +100-- 1 +10-0- 1 +10--0 1 +.names [17596] [18597] [17661] n2834 +100 1 +.names [17531] [18155] ppeaki_0_0_ n2835 +0-0 1 +10- 1 +.names n2832 n2837 n2828 n2836 +110 1 +.names [17531] [18090] ppeaki_3_3_ n2837 +0-1 1 +11- 1 +.names n2839 n2818 n2838 +10 1 +.names n2827 n2829 n2828 n2839 +100 1 +.names n2841 n2818 n2840 +10 1 +.names n2842 n2828 n2837 n2841 +110 1 +.names [17531] ppeaki_0_0_ ppeaki_1_1_ [18155] [18233] n2842 +011-- 1 +1--11 1 +.names ppeaka_12_12_ n2844 n2847 [6545] [7955] n2849 n2843 +11---- 0 +--11-- 0 +----11 0 +.names n2845 n2818 n2844 +00 1 +.names n2846 n2828 n2827 n2829 n2845 +1--- 0 +-000 0 +.names n2832 n2828 n2837 n2846 +110 1 +.names n2848 n2818 n2847 +10 1 +.names n2829 n2828 n2835 n2837 n2848 +1110 1 +.names n2850 n2818 n2849 +10 1 +.names n2827 n2828 n2829 n2850 +110 1 +.names n2852 n2818 n2851 +10 1 +.names n2829 n2827 n2828 n2852 +110 1 +.names n2854 n2818 n2853_1 +10 1 +.names n2832 n2828 n2837 n2854 +111 1 +.names n2861 n2856 n2855 +00 1 +.names preset n2857 n2860 n2819 n2856 +00-- 1 +0-10 1 +.names n2818 pdn [17089] n2858_1 n2857 +1--- 0 +-100 0 +.names n2859 n2821 n2858_1 +10 1 +.names [17024] preset_0_0_ [18545] n2859 +00- 1 +1-0 1 +.names [18064] pirq_0_0_ [18129] n2860 +00- 1 +1-0 1 +.names n2862 n2828 n2835 n2837 n2829 n2863_1 n2861 +11010- 1 +11100- 1 +11111- 1 +1----1 1 +.names preset n2825 n2862 +00 1 +.names n2864 ppeaki_4_4_ n2830 [17674] n2865 [17609] n2863_1 +101--- 1 +1--110 1 +.names n2832 n2831 n2864 +11 1 +.names [17752] [17544] [17713] n2865 +100 1 +.names [15545] n2867 [15845] n2872 n2874 [6470] n2866 +11---- 0 +--11-- 0 +----11 0 +.names n2868_1 n2862 n2867 +11 1 +.names n2864 n2869 n2868_1 +10 1 +.names n2871 [17713] n2870 [17674] [17609] n2869 +1---- 0 +-1100 0 +.names [17752] [17544] n2870 +10 1 +.names ppeaki_4_4_ ppeaki_7_7_ ppeaki_6_6_ [17752] ppeaki_5_5_ n2871 +10000 1 +.names n2860 n2873_1 n2872 +00 1 +.names preset [17596] n2820 pdn n2858_1 [17089] n2873_1 +001--- 0 +0--110 0 +.names n2875 n2862 n2874 +11 1 +.names n2864 n2876 n2875 +10 1 +.names ppeaki_4_4_ n2877 n2865 [17674] [17609] n2876 +01--- 0 +--100 0 +.names ppeaki_7_7_ ppeaki_6_6_ [17752] ppeaki_5_5_ n2877 +0000 1 +.names [13295] n2851 [5150] n2847 [14510] n2849 n2878_1 +11---- 0 +--11-- 0 +----11 0 +.names [9065] n2867 [5030] n2872 n2874 [5075] n2879 +11---- 0 +--11-- 0 +----11 0 +.names n2899 n2881 n2897 ppeaka_6_6_ n653 +101- 0 +10-0 0 +.names n2889 n2882 n2887 n2862 n2894 [7685] n2881 +111-1- 0 +111--0 0 +---0-- 0 +.names [10745] n2849 [11690] n2883_1 n2885 [4955] n2882 +11---- 0 +--11-- 0 +----11 0 +.names n2884 n2818 n2883_1 +10 1 +.names n2842 n2831 n2884 +11 1 +.names n2886 n2818 n2885 +10 1 +.names n2842 n2828 n2837 n2886 +111 1 +.names n2875 ppeakb_6_6_ [15935] n2847 ppeaka_6_6_ n2888_1 n2887 +10---- 0 +1---0- 0 +-1---0 0 +--11-- 0 +.names n2842 n2828 n2837 n2888_1 +001 0 +110 0 +.names [15200] n2890 n2892 [5870] n2889 +11-- 0 +--11 0 +.names n2891 n2818 n2890 +10 1 +.names n2831 n2835 n2829 n2891 +110 1 +.names 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n2862 n2910 +1110-- 1 +111-1- 1 +1--0-0 1 +1---10 1 +.names n2914 n2912 [13430] [10895] n2849 n2838 n2911 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names [6185] n2853_1 n2913_1 [13505] n2890 [9545] n2912 +11---- 0 +--11-- 0 +----11 0 +.names n2846 n2818 n2913_1 +10 1 +.names [13055] n2817 [7445] n2851 [5420] n2840 n2914 +11---- 0 +--11-- 0 +----11 0 +.names [10280] n2847 [11465] n2883_1 n2916 [6995] n2915 +11---- 0 +--11-- 0 +----11 0 +.names n2896 n2818 n2916 +10 1 +.names n2918_1 n2861 n2873_1 n2860 n2917 +101- 1 +10-0 1 +.names preset n2818 n2821 n2859 pdn [17089] n2918_1 +01---- 0 +0-1110 0 +.names [15395] n2872 [13700] n2874 [11885] n2920 n2919 +11---- 0 +--11-- 0 +----11 0 +.names pdn [17089] preset n2859 n2920 +1000 1 +.names n2929 n2922 n505 +11 0 +.names ppeakp_10_10_ n2923_1 ppeaka_10_10_ n2928_1 [12140] n2920 n2922 +10---- 0 +--11-- 0 +----11 0 +.names n2918_1 n2927 n2862 n2836 n2924 n2923_1 +11-0- 1 +11--0 1 +1-0-- 1 +.names n2926 n2925 ppeakb_4_4_ ppeakb_13_13_ ppeakb_1_1_ ppeakb_12_12_ \ + n2924 +110000 1 +.names ppeakb_5_5_ ppeakb_3_3_ ppeakb_2_2_ ppeakb_0_0_ ppeakb_11_11_ \ + ppeakb_15_15_ n2925 +000000 1 +.names ppeakb_9_9_ ppeakb_10_10_ ppeakb_7_7_ ppeakb_14_14_ ppeakb_8_8_ \ + ppeakb_6_6_ n2926 +000000 1 +.names n2837 n2829 n2835 n2828 n2927 +0-10 1 +11-- 1 +.names n2862 n2836 n2924 n2829 n2827 n2928_1 +110-- 1 +1--11 1 +.names ppeakb_10_10_ n2898_1 [6965] n2930 [4850] n2873_1 n2929 +11---- 0 +--11-- 0 +----10 0 +.names n2891 n2862 n2930 +11 1 +.names preset [17453] [18246] [4355] pdata_0_0_ n688 +00-1- 1 +010-1 1 +0-11- 1 +.names preset [17453] [18246] [4370] pdata_11_11_ n693 +00-1- 1 +010-1 1 +0-11- 1 +.names n4451 preset pdata_6_6_ [4385] n698 +00-1 1 +101- 1 +.names [18168] n2871 [17713] n2870 n2934 +01-- 1 +0-11 1 +.names preset [17102] [17154] [4400] pdata_1_1_ n703 +00-1- 1 +010-1 1 +0-11- 1 +.names preset [17102] [17154] [4415] pdata_12_12_ n708 +00-1- 1 +010-1 1 +0-11- 1 +.names n2938_1 preset pdata_7_7_ [4430] n713 +00-1 1 +101- 1 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[4595] n768 +00-1 1 +101- 1 +.names preset [17388] [17310] [4610] pdata_6_6_ n773 +00-1- 1 +010-1 1 +0-11- 1 +.names n2959 preset n4228 +10 1 +.names n2960 n2833 n2864 [18610] n2959 +1110 1 +.names [17453] ppeaki_4_4_ n2877 n2865 [17674] [17609] n2960 +001--- 1 +0--100 1 +.names n2983_1 n2962 [4625] n2986 n778 +10-- 1 +--11 1 +.names n2963_1 n2981 n2977 n2962 +000 1 +11- 1 +1-1 1 +.names n2974 n2964 n2971 ppeaks_0_0_ n2963_1 +10-0 1 +110- 1 +.names n2965 n2970 n2969 n2968_1 n2959 n2964 +10000 1 +.names n2833 n2966 n2967 n2948_1 n2965 +0--- 1 +-000 1 +.names n2837 n2832 [16920] n2828 n2966 +1100 1 +.names n2827 [17297] n2829 n2828 n2967 +1000 1 +.names n2833 n2850 [16933] n2968_1 +110 1 +.names n2833 n2841 [17284] n2969 +110 1 +.names [18168] [18103] n2970 +10 1 +.names n2938_1 n2973_1 n2972 n2954 n4451 ppeaka_0_0_ n2971 +00000- 1 +0000-0 1 +.names [18506] [18311] n2972 +10 1 +.names [18285] [18363] n2973_1 +10 1 +.names n2976 n2975 ppeakb_0_0_ [4310] n2954 n4451 n2974 +1000-- 1 +100-0- 1 +10-0-0 1 +10--00 1 +.names ppeaka_0_0_ n2833 n2848 [18285] n2975 +1110 1 +.names [10025] n2972 n2973_1 [8630] n2976 +11-- 0 +--11 0 +.names ppeaka_1_1_ n2978 ppeaks_1_1_ n2964 n2979 ppeakb_1_1_ n2977 +01---1 1 +0-10-- 1 +0---0- 1 +-010-- 1 +-0--0- 1 +.names n4509 n2934 n2864 [18610] n2978 +1110 1 +.names n2980 ppeaka_1_1_ n2938_1 n2954 [5030] n2979 +0---- 0 +-11-- 0 +---11 0 +.names [10310] n2972 n2973_1 [9290] n2980 +11-- 0 +--11 0 +.names n2979 n2982 ppeakb_1_1_ n2981 +110 1 +.names ppeaka_1_1_ n4451 n2982 +11 1 +.names n2984 n2960 preset n2983_1 +110 1 +.names n2985 [18610] n2984 +10 1 +.names n2864 n4509 n2985 +11 1 +.names preset n2959 n2986 +00 1 +.names n2983_1 n3000 n2988_1 [4640] n2986 n783 +100-- 1 +111-- 1 +---11 1 +.names n2997 n2989 n2988_1 +01 1 +10 1 +.names n2996 ppeaka_12_12_ n2990 ppeaka_11_11_ n2993_1 n2989 +0010- 1 +010-- 1 +01-1- 1 +0---1 1 +.names n2991 n2995 ppeaka_10_10_ ppeaka_9_9_ ppeaka_8_8_ n2990 +10--- 1 +1-000 1 +.names n2992 n2995 ppeaka_7_7_ n2991 +00- 1 +0-0 1 +.names n2993_1 ppeaka_4_4_ n2994 ppeaka_5_5_ ppeaka_6_6_ n2992 +1---- 0 +-0000 0 +.names n2971 n2964 n2978 n2993_1 +110 1 +.names n2964 n2971 n2995 ppeaka_2_2_ ppeaka_1_1_ ppeaka_3_3_ n2994 +110--- 0 +11-000 0 +.names n4509 n2864 [18168] [18610] n2869 n2995 +11000 1 +.names n2992 n2995 n2996 +10 1 +.names n2998_1 ppeakb_12_12_ n2978 ppeaks_12_12_ n2964 n2997 +0---- 0 +-11-- 0 +---10 0 +.names n2999 ppeaka_12_12_ n2938_1 n2954 [15845] n2998_1 +0---- 0 +-11-- 0 +---11 0 +.names [6860] n2972 n2973_1 [10010] n2999 +11-- 0 +--11 0 +.names n3048_1 n3045 n3044 n3001 n3043_1 n3042 n3000 +1100-- 1 +11--0- 1 +1-000- 1 +1----1 1 +-100-1 1 +-1--01 1 +--0001 1 +.names n3002 n3010 n3038_1 n3039 n3011 n3006 n3001 +0010-- 1 +001-0- 1 +00-00- 1 +0----1 1 +.names n3003_1 n2996 ppeaka_9_9_ n2991 ppeaka_8_8_ n2993_1 n3002 +10010- 1 +1010-- 1 +101-1- 1 +10---1 1 +.names n3004 n2964 ppeaks_9_9_ n3003_1 +11- 1 +1-0 1 +.names n3005 ppeakb_9_9_ n2978 n2938_1 ppeaka_9_9_ n3004 +0---- 0 +-11-- 0 +---11 0 +.names [5720] n2954 [10040] n2972 n2973_1 [7370] n3005 +11---- 0 +--11-- 0 +----11 0 +.names n2991 n3007 ppeaka_8_8_ n2995 n3006 +000- 1 +00-0 1 +1011 1 +.names n3008_1 n2964 ppeaks_8_8_ n3007 +11- 1 +1-0 1 +.names n3009 ppeakb_8_8_ n2995 n2938_1 ppeaka_8_8_ n3008_1 +0---- 0 +-11-- 0 +---11 0 +.names [6410] n2954 [8750] n2972 n2973_1 [8000] n3009 +11---- 0 +--11-- 0 +----11 0 +.names n3007 n2991 ppeaka_8_8_ n2995 n3010 +1011 1 +110- 1 +11-0 1 +.names n3012 n3035 n3034 n3018_1 n3017 n3011 +010-- 1 +01-1- 1 +0-01- 1 +0---1 1 +.names n3014 n2995 ppeaka_6_6_ n3013_1 ppeaka_5_5_ n3012 +00-0- 1 +010-1 1 +01110 1 +0-00- 1 +.names n2994 n2978 ppeaka_4_4_ n3013_1 +00- 1 +0-0 1 +.names n3015 n2964 ppeaks_6_6_ n3014 +11- 1 +1-0 1 +.names n3016 ppeakb_6_6_ n2978 n2954 [7685] n3015 +0---- 0 +-11-- 0 +---11 0 +.names ppeaka_6_6_ n2938_1 [7475] n2972 n2973_1 [6740] n3016 +11---- 0 +--11-- 0 +----11 0 +.names n3014 n2995 ppeaka_6_6_ n3013_1 ppeaka_5_5_ n3017 +11010 1 +1110- 1 +111-1 1 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+11---- 0 +--11-- 0 +----11 0 +.names n3032 ppeakb_3_3_ n2978 ppeaks_3_3_ n2964 n3031 +0---- 0 +-11-- 0 +---10 0 +.names n3033_1 ppeaka_3_3_ n2938_1 n2954 [15860] n3032 +0---- 0 +-11-- 0 +---11 0 +.names [6845] n2972 n2973_1 [9995] n3033_1 +11-- 0 +--11 0 +.names n3013_1 ppeaka_5_5_ n2995 n3034 +00- 1 +0-0 1 +111 1 +.names n3036 ppeakb_5_5_ n2978 ppeaks_5_5_ n2964 n3035 +0---- 0 +-11-- 0 +---10 0 +.names n3037 ppeaka_5_5_ n2938_1 n2954 [8330] n3036 +0---- 0 +-11-- 0 +---11 0 +.names [8105] n2972 n2973_1 [4670] n3037 +11-- 0 +--11 0 +.names n2992 ppeaka_7_7_ n2978 n3038_1 +011 1 +10- 1 +1-0 1 +.names n3040 n3041 n2964 ppeaks_7_7_ n3039 +111- 1 +11-0 1 +.names ppeakb_7_7_ n4451 n2938_1 ppeaka_7_7_ [7055] n2954 n3040 +11---- 0 +--11-- 0 +----11 0 +.names [9410] n2972 n2973_1 [6065] n3041 +11-- 0 +--11 0 +.names n2990 ppeaka_11_11_ n2995 n3042 +011 1 +10- 1 +1-0 1 +.names n2978 ppeaka_10_10_ n2991 ppeaka_9_9_ ppeaka_8_8_ n3043_1 +0-0-- 1 +10-1- 1 +10--1 1 +11100 1 +-00-- 1 +.names n3003_1 ppeaka_9_9_ n2991 ppeaka_8_8_ n2996 n3044 +000-- 1 +00-1- 1 +0110- 1 +0---1 1 +.names n3046 n2964 ppeaks_10_10_ n3045 +11- 1 +1-0 1 +.names n3047 ppeakb_10_10_ n4451 n2954 [5015] n3046 +0---- 0 +-11-- 0 +---11 0 +.names ppeaka_10_10_ n2938_1 [9770] n2972 n2973_1 [9305] n3047 +11---- 0 +--11-- 0 +----11 0 +.names n3049 ppeakb_11_11_ n2978 ppeaks_11_11_ n2964 n3048_1 +0---- 0 +-11-- 0 +---10 0 +.names n3050 ppeaka_11_11_ n2938_1 [4295] n2954 n3049 +0---- 0 +-11-- 0 +---11 0 +.names [10595] n2972 n2973_1 [8645] n3050 +11-- 0 +--11 0 +.names n2970 preset n3052 [4655] n788 +00-1 1 +101- 1 +.names n3048_1 n3042 n3045 n3043_1 n3044 n3001 n3052 +0001-- 1 +000-1- 1 +000--1 1 +00-11- 1 +00-1-1 1 +0110-- 1 +011-00 1 +01-000 1 +1010-- 1 +101-00 1 +10-000 1 +1101-- 1 +110-1- 1 +110--1 1 +11-11- 1 +11-1-1 1 +.names n2938_1 preset n3054 [4670] n793 +00-1 1 +101- 1 +.names n3035 n3034 n3018_1 n3054 +001 1 +010 1 +100 1 +111 1 +.names n2973_1 preset n3056 [4700] n798 +00-1 1 +101- 1 +.names n3045 n3043_1 n3044 n3001 n3056 +0000 1 +011- 1 +01-1 1 +101- 1 +10-1 1 +1100 1 +.names n2969 preset n3058_1 [4715] n803 +00-1 1 +101- 1 +.names n3028_1 n3019 n3031 n3027 n3021 n3058_1 +0010- 1 +001-0 1 +00-00 1 +0101- 1 +010-1 1 +01-11 1 +1001- 1 +100-1 1 +10-11 1 +1110- 1 +111-0 1 +11-00 1 +.names n2997 n2989 n3063_1 n3060 n3000 n3059 +111-- 1 +11-0- 1 +1-1-1 1 +1--01 1 +-11-1 1 +-1-01 1 +--10- 1 +.names n3062 ppeaka_13_13_ n2978 n3061 n3060 +1--- 0 +-110 0 +.names n2990 ppeaka_11_11_ ppeaka_12_12_ n3061 +100 1 +.names n2990 n2995 ppeaka_13_13_ ppeaka_11_11_ ppeaka_12_12_ n3062 +10--- 1 +1-000 1 +.names n3064 ppeakb_13_13_ n2978 ppeaks_13_13_ n2964 n3063_1 +0---- 0 +-11-- 0 +---10 0 +.names n3065 ppeaka_13_13_ n2938_1 n2954 [15500] n3064 +0---- 0 +-11-- 0 +---11 0 +.names [4775] n2972 n2973_1 [9740] n3065 +11-- 0 +--11 0 +.names n3067 ppeaka_14_14_ n3061 ppeaka_13_13_ n2995 n3066 +000-- 1 +00-1- 1 +0110- 1 +0---0 1 +.names n3068_1 n2964 ppeaks_14_14_ n3067 +11- 1 +1-0 1 +.names n3069 [5480] n2972 [6080] n2973_1 n3068_1 +0---- 0 +-11-- 0 +---11 0 +.names n3070 ppeakb_14_14_ n4451 n2938_1 ppeaka_14_14_ n3069 +1---- 0 +-11-- 0 +---11 0 +.names [15140] n2954 n3070 +11 1 +.names n3067 n2995 ppeaka_14_14_ ppeaka_13_13_ n3061 n2993_1 n3071 +10---1 1 +11001- 1 +1111-- 1 +111-0- 1 +1--0-1 1 +.names n2947 preset n4563 +10 1 +.names n2947 preset n3074 [4745] n813 +00-1 1 +101- 1 +.names n3075 n3002 n3044 n3074 +01- 1 +0-1 1 +100 1 +.names n3006 n3039 n3038_1 n3011 n3010 n3075 +010-- 1 +01-1- 1 +0-01- 1 +0---1 1 +.names n2954 preset n3077 [4760] n818 +00-1 1 +100- 1 +.names n3024 n3023_1 n2977 n2981 n2963_1 n3077 +0001- 1 +000-1 1 +011-- 1 +01-00 1 +101-- 1 +10-00 1 +1101- 1 +110-1 1 +.names n2954 preset n3079 [4775] n823 +00-1 1 +101- 1 +.names n3063_1 n3060 n2997 n2989 n3000 n3079 +0011- 1 +001-1 1 +00-11 1 +0100- 1 +010-0 1 +01-00 1 +1000- 1 +100-0 1 +10-00 1 +1111- 1 +111-1 1 +11-11 1 +.names n2972 preset n3081 [4790] n828 +00-1 1 +101- 1 +.names n3039 n3038_1 n3011 n3081 +001 1 +010 1 +100 1 +111 1 +.names n2968_1 preset n2962 [4805] n833 +00-1 1 +100- 1 +.names n2968_1 preset n2988_1 n3000 [4820] n838 +00--1 1 +1000- 1 +1011- 1 +.names n3137 n3085 [4835] n3136 n843 +11-- 1 +--11 1 +.names n3132 n3086 ppeaka_6_6_ n2968_1 n3085 +000- 1 +00-0 1 +0111 1 +1011 1 +110- 1 +11-0 1 +.names n2968_1 ppeaka_5_5_ n3128_1 ppeaka_4_4_ n3127 n3087 n3086 +110--- 1 +11-10- 1 +11---1 1 +1-010- 1 +--0--1 1 +.names n3088_1 n3126 n3125 n3113_1 n3109 n3104 n3087 +0110-- 1 +011-0- 1 +01-00- 1 +01---0 1 +0-10-0 1 +0-1-00 1 +0--000 1 +.names n3095 n3089 ppeaks_4_4_ n3088_1 +11- 1 +1-0 1 +.names n3093_1 n3092 n3091 n3090 n3089 +1000 1 +.names n2833 n2846 [17115] n3090 +110 1 +.names n2833 n2896 [17180] n3091 +110 1 +.names n2833 n2884 [17206] n3092 +110 1 +.names n3094 n2891 n2833 [18025] n3093_1 +1--- 0 +-110 0 +.names n2859 [17817] [18467] pdn n2860 n3094 +10000 1 +.names n3097 ppeakb_4_4_ n2968_1 n3096 ppeaka_4_4_ n3095 +0---- 0 +-11-- 0 +---11 0 +.names n2833 n2886 [17245] n3096 +110 1 +.names n3103_1 n2860 ppeakp_4_4_ n3098_1 n3102 [10505] n3097 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [6230] n3099 n3100 [15035] [12245] n3101 n3098_1 +11---- 0 +--11-- 0 +----11 0 +.names [17427] [17648] n3099 +10 1 +.names [18077] [17999] n3100 +10 1 +.names [17180] [17232] n3101 +10 1 +.names [18025] [17037] n3102 +10 1 +.names [17635] [17986] n3103_1 +10 1 +.names n3105 n3089 ppeaks_3_3_ ppeaka_3_3_ n3096 n3104 +0---- 0 +-01-- 0 +---11 0 +.names n3106 ppeakb_3_3_ n2968_1 ppeakp_3_3_ n3108_1 n3105 +0---- 0 +-11-- 0 +---10 0 +.names n3107 [10790] n3103_1 n2860 n3106 +0--- 0 +-110 0 +.names [8165] n3099 n3100 [12845] [12455] n3101 n3107 +11---- 0 +--11-- 0 +----11 0 +.names n3102 n2860 n3103_1 n3108_1 +00- 1 +0-0 1 +.names n3110 n3089 ppeaks_2_2_ ppeakb_2_2_ n2968_1 n3109 +0---- 0 +-01-- 0 +---11 0 +.names n3111 ppeaka_2_2_ n3096 ppeakp_2_2_ n3108_1 n3110 +0---- 0 +-11-- 0 +---10 0 +.names n3112 [11060] n3103_1 n2860 n3111 +0--- 0 +-110 0 +.names [7535] n3099 n3100 [13100] [12680] n3101 n3112 +11---- 0 +--11-- 0 +----11 0 +.names n3118_1 n3115 n3114 n3124 n4457 n3119 n3113_1 +010-1- 1 +010--1 1 +0--11- 1 +0--1-1 1 +-101-- 1 +.names ppeaks_1_1_ n3093_1 n3092 n3091 n3090 n3114 +0---- 0 +-1000 0 +.names n3116 ppeakb_1_1_ n2968_1 n3096 ppeaka_1_1_ n3115 +0---- 0 +-11-- 0 +---11 0 +.names n3103_1 n2860 ppeakp_1_1_ n3117 n3102 [11315] n3116 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [9485] n3099 n3100 [12380] [12920] n3101 n3117 +11---- 0 +--11-- 0 +----11 0 +.names ppeaks_0_0_ n3093_1 n3092 n3091 n3090 n3118_1 +0---- 0 +-1000 0 +.names n3120 ppeakb_0_0_ n2968_1 n3096 ppeaka_0_0_ n3119 +0---- 0 +-11-- 0 +---11 0 +.names n3122 n3121 ppeakp_0_0_ [11630] n3099 n3108_1 n3120 +1000-- 1 +100-0- 1 +10-0-1 1 +10--01 1 +.names [11555] n3103_1 n2860 n3121 +110 1 +.names [12605] n3100 [13175] n3101 n3122 +11-- 0 +--11 0 +.names n3100 n3099 n3103_1 n3102 n3123_1 +0000 1 +.names n3101 n2968_1 ppeaka_1_1_ n3124 +00- 1 +0-0 1 +.names ppeaka_2_2_ n2968_1 n3125 +11 1 +.names ppeaka_3_3_ n2968_1 n3126 +11 1 +.names n3088_1 n3113_1 n3126 n3125 n3109 n3104 n3127 +1100-- 1 +110-1- 1 +11-0-1 1 +11--11 1 +1-001- 1 +1-0--1 1 +1--011 1 +.names n3129 n3089 ppeaks_5_5_ n3128_1 +11- 1 +1-0 1 +.names n3130 ppeakb_5_5_ n2968_1 n3096 ppeaka_5_5_ n3129 +0---- 0 +-11-- 0 +---11 0 +.names n3103_1 n2860 ppeakp_5_5_ n3131 n3102 [10220] n3130 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [6905] n3099 n3100 [15395] n3101 [6995] n3131 +11---- 0 +--11-- 0 +----11 0 +.names n3133_1 n3089 ppeaks_6_6_ ppeaka_6_6_ n3096 n3132 +0---- 0 +-01-- 0 +---11 0 +.names n3134 n2968_1 ppeakb_6_6_ n3133_1 +10- 1 +1-0 1 +.names n3103_1 n2860 ppeakp_6_6_ n3135 n3102 [9950] n3134 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [4835] n3099 [14210] n3100 [7625] n3101 n3135 +11---- 0 +--11-- 0 +----11 0 +.names preset n3094 n3136 +00 1 +.names n3094 preset n3137 +10 1 +.names n3103_1 preset n3139 [4850] n848 +00-1 1 +101- 1 +.names n3158 n3154 n3140 n3139 +000 1 +011 1 +101 1 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n2968_1 n3096 ppeaka_8_8_ n3151 +0---- 0 +-11-- 0 +---11 0 +.names n3103_1 n2860 ppeakp_8_8_ n3153_1 n3102 [11330] n3152 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [11420] n3099 n3100 [13460] [8915] n3101 n3153_1 +11---- 0 +--11-- 0 +----11 0 +.names n3155 n3089 ppeaks_10_10_ ppeaka_10_10_ n3096 n3154 +0---- 0 +-01-- 0 +---11 0 +.names n3156 n3157 ppeakb_10_10_ ppeakp_10_10_ n3108_1 n2968_1 n3155 +1000-- 1 +100-1- 1 +10-0-0 1 +10--10 1 +.names [10925] n3099 n3100 [12860] [9860] n3101 n3156 +11---- 0 +--11-- 0 +----11 0 +.names [11795] n3103_1 n2860 n3157 +110 1 +.names ppeaka_10_10_ n2968_1 n3158 +11 1 +.names n3162 n3160 [4865] n3161 n853 +11-- 1 +--11 1 +.names n3127 n3087 n3160 +00 1 +.names preset n2891 n4509 [18025] n3161 +1--- 0 +-110 0 +.names n2891 n4509 [18025] preset n3162 +1100 1 +.names n3162 n3181 n3185 n3190 n3164 n3189 n858 +1010-- 1 +101-0- 1 +10-00- 1 +1101-- 1 +110-1- 1 +11-11- 1 +-----1 1 +.names n3179 n3180 n3175 n3171 n3165 n3164 +110-- 1 +11--1 1 +1-00- 1 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n2860 ppeakp_12_12_ n3178 n3102 [12050] n3177 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [15755] n3099 n3100 [12395] [10415] n3101 n3178 +11---- 0 +--11-- 0 +----11 0 +.names ppeaka_12_12_ n2968_1 n3179 +11 1 +.names ppeaka_13_13_ n2968_1 n3180 +11 1 +.names ppeaka_15_15_ n2968_1 n3183 n3182 ppeakb_15_15_ n3096 n3181 +0010-- 1 +0-100- 1 +110--- 1 +11-1-- 1 +11---1 1 +1-1010 1 +-010-0 1 +.names ppeaks_15_15_ n3089 n3182 +10 1 +.names n3103_1 n2860 ppeakp_15_15_ n3184 n3102 [12470] n3183 +10---1 0 +111--- 0 +--1-1- 0 +---0-- 0 +.names [14615] n3099 n3100 [15050] [6320] n3101 n3184 +11---- 0 +--11-- 0 +----11 0 +.names n3186 n3089 ppeaks_14_14_ ppeaka_14_14_ n3096 n3185 +0---- 0 +-01-- 0 +---11 0 +.names n3187 n3188 ppeakb_14_14_ ppeakp_14_14_ n3108_1 n2968_1 n3186 +1000-- 1 +100-1- 1 +10-0-0 1 +10--10 1 +.names [13445] n3099 n3100 [15410] [10985] n3101 n3187 +11---- 0 +--11-- 0 +----11 0 +.names [12260] n3103_1 n2860 n3188 +110 1 +.names [4880] n3161 n3189 +11 1 +.names ppeaka_14_14_ n2968_1 n3190 +11 1 +.names n3102 preset n3192 [4895] n863 +00-1 1 +100- 1 +.names n3146 ppeaka_9_9_ n2968_1 n3150 n3141 ppeaka_8_8_ n3192 +0010-1 1 +001-11 1 +00-01- 1 +01110- 1 +0111-0 1 +011-00 1 +0-001- 1 +10-10- 1 +10-1-0 1 +10--00 1 +11101- 1 +11-001 1 +11-111 1 +1-01-- 1 +1-0-0- 1 +.names n3196 n3194 [4910] n3195 n868 +11-- 1 +--11 1 +.names n3126 n3104 n3125 n3113_1 n3109 n3194 +0001- 1 +000-1 1 +00-11 1 +0110- 1 +011-0 1 +01-00 1 +1010- 1 +101-0 1 +10-00 1 +1101- 1 +110-1 1 +11-11 1 +.names preset n3092 n3195 +00 1 +.names n3092 preset n3196 +10 1 +.names n2968_1 preset n3198 [4925] n873 +00-1 1 +100- 1 +.names n3124 n3199 n3198 +01 1 +10 1 +.names n3118_1 n3115 n3114 n4457 n3119 n3199 +00-1- 1 +00--1 1 +0-11- 1 +0-1-1 1 +110-- 1 +-1000 1 +.names n2968_1 preset n3201 [4940] n878 +00-1 1 +100- 1 +.names n3179 n3202 n3201 +00 1 +11 1 +.names n3175 n3158 n3170 n3154 n3166 n3140 n3202 +0001-- 1 +000--0 1 +00-11- 1 +00--10 1 +0-01-0 1 +0-0-1- 1 +0--110 1 +1110-- 1 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n3221 [14975] n2867 n2872 [15035] n469 +1----- 1 +-0---- 1 +--11-- 1 +----11 1 +.names n2862 n3217 [6875] n2849 [4865] n2890 n3216 +10---- 1 +1-11-- 1 +1---11 1 +.names n3218 n3220 [12350] [9380] n2851 n2817 n3217 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n3219 [8015] n2847 [12245] n2916 n3218 +0---- 0 +-11-- 0 +---11 0 +.names [4715] n2840 [5615] n2883_1 n3219 +11-- 0 +--11 0 +.names [13790] n2838 [9785] n2853_1 [14675] n2913_1 n3220 +11---- 0 +--11-- 0 +----11 0 +.names ppeaks_4_4_ n2917 [11120] n2874 n2920 [11765] n3221 +10---- 0 +--11-- 0 +----11 0 +.names n3224 n3223 n585 +11 0 +.names ppeakp_11_11_ n2923_1 n2928_1 ppeaka_11_11_ [5555] n2873_1 n3223 +10---- 0 +--11-- 0 +----10 0 +.names ppeakb_11_11_ n2898_1 [6290] n2930 n2920 [12020] n3224 +11---- 0 +--11-- 0 +----11 0 +.names preset [17453] [18246] [5075] pdata_1_1_ n903 +00-1- 1 +010-1 1 +0-11- 1 +.names preset [17453] [18246] [5090] pdata_10_10_ n908 +00-1- 1 +010-1 1 +0-11- 1 +.names preset [17102] [17154] [5105] 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n4413_1 ppeakp_4_4_ n4209 [10505] n4210 n2860 n4412 +0----- 0 +-10--- 0 +---110 0 +.names n4415 n4414 n4416 n4215 [15035] n4413_1 +1110- 1 +111-0 1 +.names [4865] n4214 n4533_1 [6170] n4414 +11-- 0 +--11 0 +.names [12245] n4153 n4538 [5375] n4415 +11-- 0 +--11 0 +.names [14675] n4083 [5615] n4168 [6230] n4216 n4416 +11---- 0 +--11-- 0 +----11 0 +.names n4418_1 paddress_5_5_ n4193_1 ppeaks_5_5_ n4204 n373_1 +0---- 1 +-11-- 1 +---10 1 +.names n4419 ppeaka_5_5_ n4501 n2969 ppeakb_5_5_ preset n4418_1 +0----- 0 +-10--- 0 +---110 0 +.names n4420 n4422 [8330] ppeakp_5_5_ n4209 n3562 n4419 +1100-- 1 +110-1- 1 +11-0-0 1 +11--10 1 +.names n4421 [13505] n4083 [10220] n4210 n2860 n4420 +0----- 0 +-11--- 0 +---110 0 +.names [4670] n4538 n4168 [11465] [6905] n4216 n4421 +11---- 0 +--11-- 0 +----11 0 +.names n4423_1 [6995] n4153 [15395] n4215 n4422 +0---- 0 +-11-- 0 +---11 0 +.names [9545] n4214 [8105] n4533_1 n4423_1 +11-- 0 +--11 0 +.names pdn preset n2859 [18545] n4573 +000- 1 +10-1 1 +.names n4426 paddress_6_6_ n4193_1 ppeaks_6_6_ n4204 n461 +0---- 1 +-11-- 1 +---10 1 +.names n4427 n4501 ppeaka_6_6_ n4426 +11- 1 +1-0 1 +.names n4428_1 [7685] n3562 n2969 ppeakb_6_6_ preset n4427 +0----- 0 +-11--- 0 +---110 0 +.names n4429 ppeakp_6_6_ n4209 [9950] n4210 n2860 n4428_1 +0----- 0 +-10--- 0 +---110 0 +.names n4430 n4431 [7475] [4835] n4216 n4533_1 n4429 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names [8870] n4214 n4083 [13865] [14210] n4215 n4430 +11---- 0 +--11-- 0 +----11 0 +.names [7625] n4153 n4538 [6740] [11690] n4168 n4431 +11---- 0 +--11-- 0 +----11 0 +.names preset n4232 [18571] n4578 +00- 1 +0-1 1 +.names preset n4232 [18584] n4583 +00- 1 +0-1 1 +.names n4073 [18597] n4504 [17596] n4588 +11-- 1 +1-11 1 +.names preset n2985 [18610] n2825 [17453] [18168] n4593 +011--- 1 +01--1- 1 +01---1 1 +0-11-- 1 +.names n4437 ppeaks_7_7_ n4204 n433_1 +0-- 1 +-10 1 +.names n4438_1 paddress_7_7_ n4193_1 ppeaka_7_7_ n4501 n4437 +0---- 0 +-11-- 0 +---10 0 +.names n4439 [7055] n3562 n2969 ppeakb_7_7_ preset n4438_1 +0----- 0 +-11--- 0 +---110 0 +.names n4440 ppeakp_7_7_ n4209 [11075] n4210 n2860 n4439 +0----- 0 +-10--- 0 +---110 0 +.names n4442 n4441 [8255] [12905] n4083 n4153 n4440 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names [8225] n4214 n4538 [6065] n4168 [10970] n4441 +11---- 0 +--11-- 0 +----11 0 +.names [9410] n4533_1 [14630] n4215 [5540] n4216 n4442 +11---- 0 +--11-- 0 +----11 0 +.names n4509 preset n4593 n4444 n2886 n4598_1 +10-0- 1 +10--1 1 +1-1-- 1 +.names n4445 [17050] [18415] [17271] [18389] n4444 +10000 1 +.names n4446 [18493] [18376] [17167] [17102] n4445 +10000 1 +.names [17232] [17388] [17297] [16920] n4446 +0000 1 +.names n2840 [8480] n2853_1 [5285] ppeaka_1_1_ n2844 n4447 +11---- 0 +--11-- 0 +----11 0 +.names n2818 n2878_1 n2839 [15650] [13310] n2836 n4448_1 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2862 n2879 n2855 ppeakb_1_1_ n4447 n4448_1 n537 +1---0- 1 +1----0 1 +-0---- 1 +--01-- 1 +.names [18610] [17752] [17544] [17674] [17609] n4450 +00--- 1 +0-000 1 +.names n2934 n2864 n2833 n4450 n4451 +1111 1 +.names n2969 preset n4455 n3059 n3066 [4730] n808 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2954 [13550] n2973_1 [6755] [8765] n2972 n4453_1 +11---- 0 +--11-- 0 +----11 0 +.names n4453_1 ppeakb_15_15_ n2978 ppeaks_15_15_ n2964 n4454 +0---- 0 +-11-- 0 +---10 0 +.names n3062 ppeaka_15_15_ n4454 n2995 n2938_1 ppeaka_14_14_ n4455 +001--- 1 +0101-- 1 +0-100- 1 +0-111- 1 +100--0 1 +111100 1 +11-01- 1 +1-00-- 1 +-011-1 1 +-101-1 1 +--1111 1 +.names n2833 [17245] n2886 ppeaka_0_0_ n2850 [16933] n4456 +101--- 0 +1--110 0 +.names n3123_1 n3093_1 n4456 n3092 n3091 n3090 n4457 +111000 1 +.names n2844 ppeaka_0_0_ n2849 [10550] n2851 [5900] n4458_1 +11---- 0 +--11-- 0 +----11 0 +.names n2818 n3205 n2841 [7835] n2848 [15605] n4459 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2862 n3206 n2855 ppeakb_0_0_ n4458_1 n4459 n521_1 +1---0- 1 +1----0 1 +-0---- 1 +--01-- 1 +.names n2862 ppeakp_7_7_ n2872 ppeaka_8_8_ n2863_1 n2826 n4461 +11---1 0 +1--11- 0 +-11--- 0 +.names n4461 n3207 ppeaka_7_7_ n2897 n2867 [12335] n285 +0----- 1 +-1---- 1 +--10-- 1 +----11 1 +.names n2862 n2874 [5090] n3276 [14810] n2868_1 n4463_1 +1--0-- 0 +1---11 0 +-11--- 0 +.names n4463_1 n2855 ppeakb_10_10_ n2872 [5015] n309 +0---- 1 +-01-- 1 +---11 1 +.names n3091 preset n3181 n3164 n3185 [6320] n1288 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n3096 preset n3181 n3164 n3185 [6365] n1303 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2853_1 [4595] ppeaka_11_11_ n2844 [5930] n2851 n4467 +11---- 0 +--11-- 0 +----11 0 +.names n2818 n3347 n2841 [9155] n2850 [14090] n4468_1 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2862 n3348_1 n2855 ppeakb_11_11_ n4467 n4468_1 n481 +1---0- 1 +1----0 1 +-0---- 1 +--01-- 1 +.names n2818 n3349 n2848 [4445] n2852 [13640] n4470 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2844 ppeaka_2_2_ n2849 [7310] n2853_1 [8555] n4471 +11---- 0 +--11-- 0 +----11 0 +.names n2862 n3350 n2855 ppeakb_2_2_ n4470 n4471 n557 +1---0- 1 +1----0 1 +-0---- 1 +--01-- 1 +.names n2938_1 preset n4455 n3059 n3066 [6755] n1408_1 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2970 preset n4455 n3059 n3066 [7355] n1583_1 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2954 preset n4455 n3059 n3066 [8765] n2008 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2968_1 preset n4455 n3059 n3066 [11180] n2708 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2818 n3780 n2845 ppeaka_14_14_ [12770] n2836 n4477 +0-01-- 0 +0---11 0 +-0---- 0 +.names n2838 [7250] n2853_1 [7925] [15965] n2851 n4478_1 +11---- 0 +--11-- 0 +----11 0 +.names n2862 n3781 n2855 ppeakb_14_14_ n4477 n4478_1 n305 +1---0- 1 +1----0 1 +-0---- 1 +--01-- 1 +.names n2950 preset n4455 n3059 n3066 [12365] n3023 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n3092 preset n3181 n3164 n3185 [12425] n3043 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2862 n2874 [13955] n3907 [6485] n2868_1 n4482 +1--0-- 0 +1---11 0 +-11--- 0 +.names n4482 n2855 ppeakb_5_5_ n2872 [8330] n629_1 +0---- 1 +-01-- 1 +---11 1 +.names n3090 preset n3181 n3164 n3185 [13880] n3433 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names ppeakb_11_11_ n2888_1 n2893_1 [7820] n2850 [9650] n4485 +10---- 1 +--11-- 1 +----11 1 +.names n4485 n2818 n2890 [5120] [11735] n2885 n4486 +10---- 0 +--11-- 0 +----11 0 +.names n2862 n3938 n4486 ppeaka_11_11_ n2897 n3936 n417 +1-0--- 1 +1----0 1 +-0---- 1 +---10- 1 +.names n4022 n4021 n2885 n2892 [14015] [10190] n4488_1 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n2818 n4488_1 n2888_1 ppeakb_13_13_ [5645] n2850 n4489 +0-01-- 1 +0---11 1 +-0---- 1 +.names n4023_1 n2862 n4489 ppeaka_13_13_ n2897 n589_1 +0---- 1 +-11-- 1 +---10 1 +.names n2818 n4032 n2891 [10685] [14165] n2836 n4491 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2862 n4107 n2875 [7745] n2854 [10265] n4492 +10---- 0 +1-11-- 0 +1---11 0 +.names n4492 n2855 ppeakb_6_6_ n2872 [7685] n649_1 +0---- 1 +-01-- 1 +---11 1 +.names n2947 preset n4455 n3059 n3066 [15725] n3928_1 +00---1 1 +1000-- 1 +100-1- 1 +10110- 1 +.names n2844 ppeaka_7_7_ n2851 [5915] n2853_1 [14930] n4495 +11---- 0 +--11-- 0 +----11 0 +.names n2818 n4147 n2841 [14450] [15980] n2836 n4496 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2862 n4148_1 n4495 ppeakb_7_7_ n2855 n4496 n273_1 +1-0--- 1 +1----0 1 +-0---- 1 +---10- 1 +.names n2818 n4165 n2848 [4700] [14585] n2836 n4498_1 +0-11-- 0 +0---11 0 +-0---- 0 +.names n2862 n4498_1 [8060] n2840 n2853_1 [8135] n4499 +10---- 0 +1-11-- 0 +1---11 0 +.names n4499 n4168_1 ppeaks_10_10_ n2917 n2874 [6035] n545 +0----- 1 +-0---- 1 +--10-- 1 +----11 1 +.names preset n4185 n2938_1 n4501 +1-- 1 +-00 1 +.names ppeaki_14_14_ ppeaki_10_10_ n3641 ppeaki_5_5_ ppeaki_7_7_ \ + ppeaki_6_6_ n4502 +001--- 1 +00-000 1 +.names ppeaki_11_11_ ppeaki_9_9_ ppeaki_13_13_ ppeaki_8_8_ ppeaki_12_12_ \ + ppeaki_15_15_ n4503_1 +000000 1 +.names n2825 n4503_1 n4502 n3641 n2835 ppeaki_4_4_ n4504 +0111-- 1 +011--0 1 +0--11- 1 +.names ppeaka_14_14_ n4501 ppeaks_14_14_ n4204 n4193_1 paddress_14_14_ \ + n4505 +10---- 0 +--10-- 0 +----11 0 +.names ppeakp_14_14_ preset n3070 n4103 n4198_1 n2860 n4506 +10--11 0 +1--1-- 0 +-01--- 0 +.names n4310 n4505 n4506 preset ppeakb_14_14_ n2969 n597 +1111-- 0 +111-0- 0 +111--0 0 +.names [17752] ppeaki_6_6_ ppeaki_7_7_ [17544] [17674] [17609] n4508_1 +000--- 1 +1--000 1 +.names n2833 n2826 n2831 n2832 n4508_1 n2830 n4509 +100--- 1 +10-0-- 1 +10--10 1 +.names n2916 [9590] [5405] n2847 [15770] n2883_1 n4510 +11---- 0 +--11-- 0 +----11 0 +.names n2818 n4510 [5465] n2839 n2850 [9470] n4511 +0-11-- 0 +0---11 0 +-0---- 0 +.names n4033_1 n4491 n4511 n2862 [4745] n2851 n573 +111-0- 0 +111--0 0 +1--0-- 0 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v b/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v new file mode 100644 index 000000000..c6c12fb24 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v @@ -0,0 +1,7100 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module frisc(tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_, tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk, pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_, tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_, tin_pdata_5_5_, preset, tin_pdata_13_13_, ppeakb_7_7_, ppeakp_12_12_, ppeakp_0_0_, ppeaka_7_7_, ppeaki_15_15_, ppeaki_11_11_, ppeaki_3_3_, paddress_3_3_, pdata_8_8_, pdata_0_0_, ppeakb_14_14_, ppeakb_10_10_, ppeakb_8_8_, ppeakp_1_1_, ppeaka_14_14_, ppeaka_10_10_, ppeaka_8_8_, ppeaki_4_4_, paddress_15_15_, paddress_11_11_, paddress_2_2_, ppeakb_9_9_, ppeakp_2_2_, ppeaka_9_9_, ppeaks_12_12_, ppeaks_0_0_, ppeaki_5_5_, paddress_5_5_, pdata_7_7_, ppeakb_15_15_, ppeakp_3_3_, pwr_0_0_, ppeaks_1_1_, ppeaki_6_6_, paddress_4_4_, piack_0_0_, ppeakp_13_13_, ppeakp_4_4_, ppeaka_15_15_, ppeaka_11_11_, ppeaks_2_2_, ppeaki_7_7_, paddress_10_10_, paddress_7_7_, pdata_2_2_, ppeakp_5_5_, ppeaks_13_13_, ppeaks_3_3_, ppeaki_14_14_, ppeaki_10_10_, ppeaki_8_8_, paddress_6_6_, ppeakp_6_6_, ppeaks_4_4_, ppeaki_9_9_, paddress_9_9_, pdata_9_9_, pdata_1_1_, ppeakb_11_11_, ppeakp_7_7_, ppeaks_5_5_, paddress_13_13_, paddress_8_8_, ppeakp_14_14_, ppeakp_10_10_, ppeakp_8_8_, ppeaks_6_6_, ppeaki_13_13_, pdata_4_4_, ppeakb_0_0_, ppeakp_9_9_, ppeaka_0_0_, ppeaks_7_7_, ppeakb_1_1_, ppeaka_1_1_, ppeaks_10_10_, ppeaks_8_8_, pdata_10_10_, pdata_3_3_, ppeakb_12_12_, ppeakb_2_2_, ppeaka_12_12_, ppeaka_2_2_, ppeaks_15_15_, ppeaks_9_9_, ppeakb_3_3_, ppeakp_15_15_, ppeakp_11_11_, ppeaka_13_13_, ppeaka_3_3_, paddress_14_14_, paddress_12_12_, pdata_6_6_, ppeakb_13_13_, ppeakb_4_4_, pdn, ppeaka_4_4_, ppeaki_0_0_, prd_0_0_, pdata_15_15_, pdata_11_11_, ppeakb_5_5_, ppeaka_5_5_, ppeaks_14_14_, ppeaki_1_1_, paddress_1_1_, pdata_14_14_, pdata_12_12_, pdata_5_5_, ppeakb_6_6_, ppeaka_6_6_, ppeaks_11_11_, ppeaki_12_12_, ppeaki_2_2_, paddress_0_0_, pdata_13_13_); + (* init = 1'h0 *) + reg \[10010] = 1'h0; + (* init = 1'h0 *) + reg \[10025] = 1'h0; + (* init = 1'h0 *) + reg \[10040] = 1'h0; + (* init = 1'h0 *) + reg \[10055] = 1'h0; + (* init = 1'h0 *) + reg \[10070] = 1'h0; + (* init = 1'h0 *) + reg \[10085] = 1'h0; + (* init = 1'h0 *) + reg \[10100] = 1'h0; + (* init = 1'h0 *) + reg \[10115] = 1'h0; + (* init = 1'h0 *) + reg \[10130] = 1'h0; + (* init = 1'h0 *) + reg \[10145] = 1'h0; + (* init = 1'h0 *) + reg \[10175] = 1'h0; + (* init = 1'h0 *) + reg \[10190] = 1'h0; + (* init = 1'h0 *) + reg \[10205] = 1'h0; + (* init = 1'h0 *) + reg \[10220] = 1'h0; + (* init = 1'h0 *) + reg \[10265] = 1'h0; + (* init = 1'h0 *) + reg \[10280] = 1'h0; + (* init = 1'h0 *) + reg \[10310] = 1'h0; + (* init = 1'h0 *) + reg \[10325] = 1'h0; + (* init = 1'h0 *) + reg \[10340] = 1'h0; + (* init = 1'h0 *) + reg \[10355] = 1'h0; + (* init = 1'h0 *) + reg \[10370] = 1'h0; + (* init = 1'h0 *) + reg \[10400] = 1'h0; + (* init = 1'h0 *) + reg \[10415] = 1'h0; + (* init = 1'h0 *) + reg \[10430] = 1'h0; + (* init = 1'h0 *) + reg \[10445] = 1'h0; + (* init = 1'h0 *) + reg \[10460] = 1'h0; + (* init = 1'h0 *) + reg \[10475] = 1'h0; + (* init = 1'h0 *) + reg \[10490] = 1'h0; + (* init = 1'h0 *) + reg \[10505] = 1'h0; + (* init = 1'h0 *) + reg \[10550] = 1'h0; + (* init = 1'h0 *) + reg \[10565] = 1'h0; + (* init = 1'h0 *) + reg \[10580] = 1'h0; + (* init = 1'h0 *) + reg \[10595] = 1'h0; + (* init = 1'h0 *) + reg \[10610] = 1'h0; + (* init = 1'h0 *) + reg \[10625] = 1'h0; + (* init = 1'h0 *) + reg \[10655] = 1'h0; + (* init = 1'h0 *) + reg \[10670] = 1'h0; + (* init = 1'h0 *) + reg \[10685] = 1'h0; + (* init = 1'h0 *) + reg \[10700] = 1'h0; + (* init = 1'h0 *) + reg \[10715] = 1'h0; + (* init = 1'h0 *) + reg \[10730] = 1'h0; + (* init = 1'h0 *) + reg \[10745] = 1'h0; + (* init = 1'h0 *) + reg \[10760] = 1'h0; + (* init = 1'h0 *) + reg \[10775] = 1'h0; + (* init = 1'h0 *) + reg \[10790] = 1'h0; + (* init = 1'h0 *) + reg \[10805] = 1'h0; + (* init = 1'h0 *) + reg \[10820] = 1'h0; + (* init = 1'h0 *) + reg \[10850] = 1'h0; + (* init = 1'h0 *) + reg \[10865] = 1'h0; + (* init = 1'h0 *) + reg \[10880] = 1'h0; + (* init = 1'h0 *) + reg \[10895] = 1'h0; + (* init = 1'h0 *) + reg \[10925] = 1'h0; + (* init = 1'h0 *) + reg \[10940] = 1'h0; + (* init = 1'h0 *) + reg \[10955] = 1'h0; + (* init = 1'h0 *) + reg \[10970] = 1'h0; + (* init = 1'h0 *) + reg \[10985] = 1'h0; + (* init = 1'h0 *) + reg \[11015] = 1'h0; + (* init = 1'h0 *) + reg \[11030] = 1'h0; + (* init = 1'h0 *) + reg \[11045] = 1'h0; + (* init = 1'h0 *) + reg \[11060] = 1'h0; + (* init = 1'h0 *) + reg \[11075] = 1'h0; + (* init = 1'h0 *) + reg \[11090] = 1'h0; + (* init = 1'h0 *) + reg \[11120] = 1'h0; + (* init = 1'h0 *) + reg \[11135] = 1'h0; + (* init = 1'h0 *) + reg \[11150] = 1'h0; + (* init = 1'h0 *) + reg \[11165] = 1'h0; + (* init = 1'h0 *) + reg \[11180] = 1'h0; + (* init = 1'h0 *) + reg \[11195] = 1'h0; + (* init = 1'h0 *) + reg \[11210] = 1'h0; + (* init = 1'h0 *) + reg \[11225] = 1'h0; + (* init = 1'h0 *) + reg \[11240] = 1'h0; + (* init = 1'h0 *) + reg \[11255] = 1'h0; + (* init = 1'h0 *) + reg \[11270] = 1'h0; + (* init = 1'h0 *) + reg \[11285] = 1'h0; + (* init = 1'h0 *) + reg \[11300] = 1'h0; + (* init = 1'h0 *) + reg \[11315] = 1'h0; + (* init = 1'h0 *) + reg \[11330] = 1'h0; + (* init = 1'h0 *) + reg \[11345] = 1'h0; + (* init = 1'h0 *) + reg \[11375] = 1'h0; + (* init = 1'h0 *) + reg \[11390] = 1'h0; + (* init = 1'h0 *) + reg \[11405] = 1'h0; + (* init = 1'h0 *) + reg \[11420] = 1'h0; + (* init = 1'h0 *) + reg \[11435] = 1'h0; + (* init = 1'h0 *) + reg \[11450] = 1'h0; + (* init = 1'h0 *) + reg \[11465] = 1'h0; + (* init = 1'h0 *) + reg \[11480] = 1'h0; + (* init = 1'h0 *) + reg \[11495] = 1'h0; + (* init = 1'h0 *) + reg \[11510] = 1'h0; + (* init = 1'h0 *) + reg \[11525] = 1'h0; + (* init = 1'h0 *) + reg \[11540] = 1'h0; + (* init = 1'h0 *) + reg \[11555] = 1'h0; + (* init = 1'h0 *) + reg \[11570] = 1'h0; + (* init = 1'h0 *) + reg \[11585] = 1'h0; + (* init = 1'h0 *) + reg \[11600] = 1'h0; + (* init = 1'h0 *) + reg \[11615] = 1'h0; + (* init = 1'h0 *) + reg \[11630] = 1'h0; + (* init = 1'h0 *) + reg \[11645] = 1'h0; + (* init = 1'h0 *) + reg \[11660] = 1'h0; + (* init = 1'h0 *) + reg \[11675] = 1'h0; + (* init = 1'h0 *) + reg \[11690] = 1'h0; + (* init = 1'h0 *) + reg \[11705] = 1'h0; + (* init = 1'h0 *) + reg \[11720] = 1'h0; + (* init = 1'h0 *) + reg \[11735] = 1'h0; + (* init = 1'h0 *) + reg \[11750] = 1'h0; + (* init = 1'h0 *) + reg \[11765] = 1'h0; + (* init = 1'h0 *) + reg \[11780] = 1'h0; + (* init = 1'h0 *) + reg \[11795] = 1'h0; + (* init = 1'h0 *) + reg \[11810] = 1'h0; + (* init = 1'h0 *) + reg \[11885] = 1'h0; + (* init = 1'h0 *) + reg \[11900] = 1'h0; + (* init = 1'h0 *) + reg \[11915] = 1'h0; + (* init = 1'h0 *) + reg \[11930] = 1'h0; + (* init = 1'h0 *) + reg \[12005] = 1'h0; + (* init = 1'h0 *) + reg \[12020] = 1'h0; + (* init = 1'h0 *) + reg \[12035] = 1'h0; + (* init = 1'h0 *) + reg \[12050] = 1'h0; + (* init = 1'h0 *) + reg \[12065] = 1'h0; + (* init = 1'h0 *) + reg \[12080] = 1'h0; + (* init = 1'h0 *) + reg \[12125] = 1'h0; + (* init = 1'h0 *) + reg \[12140] = 1'h0; + (* init = 1'h0 *) + reg \[12155] = 1'h0; + (* init = 1'h0 *) + reg \[12170] = 1'h0; + (* init = 1'h0 *) + reg \[12185] = 1'h0; + (* init = 1'h0 *) + reg \[12200] = 1'h0; + (* init = 1'h0 *) + reg \[12245] = 1'h0; + (* init = 1'h0 *) + reg \[12260] = 1'h0; + (* init = 1'h0 *) + reg \[12275] = 1'h0; + (* init = 1'h0 *) + reg \[12335] = 1'h0; + (* init = 1'h0 *) + reg \[12350] = 1'h0; + (* init = 1'h0 *) + reg \[12365] = 1'h0; + (* init = 1'h0 *) + reg \[12380] = 1'h0; + (* init = 1'h0 *) + reg \[12395] = 1'h0; + (* init = 1'h0 *) + reg \[12410] = 1'h0; + (* init = 1'h0 *) + reg \[12425] = 1'h0; + (* init = 1'h0 *) + reg \[12440] = 1'h0; + (* init = 1'h0 *) + reg \[12455] = 1'h0; + (* init = 1'h0 *) + reg \[12470] = 1'h0; + (* init = 1'h0 *) + reg \[12485] = 1'h0; + (* init = 1'h0 *) + reg \[12545] = 1'h0; + (* init = 1'h0 *) + reg \[12560] = 1'h0; + (* init = 1'h0 *) + reg \[12575] = 1'h0; + (* init = 1'h0 *) + reg \[12590] = 1'h0; + (* init = 1'h0 *) + reg \[12605] = 1'h0; + (* init = 1'h0 *) + reg \[12620] = 1'h0; + (* init = 1'h0 *) + reg \[12635] = 1'h0; + (* init = 1'h0 *) + reg \[12650] = 1'h0; + (* init = 1'h0 *) + reg \[12665] = 1'h0; + (* init = 1'h0 *) + reg \[12680] = 1'h0; + (* init = 1'h0 *) + reg \[12695] = 1'h0; + (* init = 1'h0 *) + reg \[12770] = 1'h0; + (* init = 1'h0 *) + reg \[12800] = 1'h0; + (* init = 1'h0 *) + reg \[12815] = 1'h0; + (* init = 1'h0 *) + reg \[12830] = 1'h0; + (* init = 1'h0 *) + reg \[12845] = 1'h0; + (* init = 1'h0 *) + reg \[12860] = 1'h0; + (* init = 1'h0 *) + reg \[12875] = 1'h0; + (* init = 1'h0 *) + reg \[12890] = 1'h0; + (* init = 1'h0 *) + reg \[12905] = 1'h0; + (* init = 1'h0 *) + reg \[12920] = 1'h0; + (* init = 1'h0 *) + reg \[12935] = 1'h0; + (* init = 1'h0 *) + reg \[13010] = 1'h0; + (* init = 1'h0 *) + reg \[13025] = 1'h0; + (* init = 1'h0 *) + reg \[13040] = 1'h0; + (* init = 1'h0 *) + reg \[13055] = 1'h0; + (* init = 1'h0 *) + reg \[13070] = 1'h0; + (* init = 1'h0 *) + reg \[13085] = 1'h0; + (* init = 1'h0 *) + reg \[13100] = 1'h0; + (* init = 1'h0 *) + reg \[13115] = 1'h0; + (* init = 1'h0 *) + reg \[13130] = 1'h0; + (* init = 1'h0 *) + reg \[13160] = 1'h0; + (* init = 1'h0 *) + reg \[13175] = 1'h0; + (* init = 1'h0 *) + reg \[13220] = 1'h0; + (* init = 1'h0 *) + reg \[13235] = 1'h0; + (* init = 1'h0 *) + reg \[13250] = 1'h0; + (* init = 1'h0 *) + reg \[13265] = 1'h0; + (* init = 1'h0 *) + reg \[13280] = 1'h0; + (* init = 1'h0 *) + reg \[13295] = 1'h0; + (* init = 1'h0 *) + reg \[13310] = 1'h0; + (* init = 1'h0 *) + reg \[13325] = 1'h0; + (* init = 1'h0 *) + reg \[13340] = 1'h0; + (* init = 1'h0 *) + reg \[13355] = 1'h0; + (* init = 1'h0 *) + reg \[13370] = 1'h0; + (* init = 1'h0 *) + reg \[13385] = 1'h0; + (* init = 1'h0 *) + reg \[13400] = 1'h0; + (* init = 1'h0 *) + reg \[13415] = 1'h0; + (* init = 1'h0 *) + reg \[13430] = 1'h0; + (* init = 1'h0 *) + reg \[13445] = 1'h0; + (* init = 1'h0 *) + reg \[13460] = 1'h0; + (* init = 1'h0 *) + reg \[13475] = 1'h0; + (* init = 1'h0 *) + reg \[13490] = 1'h0; + (* init = 1'h0 *) + reg \[13505] = 1'h0; + (* init = 1'h0 *) + reg \[13550] = 1'h0; + (* init = 1'h0 *) + reg \[13580] = 1'h0; + (* init = 1'h0 *) + reg \[13595] = 1'h0; + (* init = 1'h0 *) + reg \[13610] = 1'h0; + (* init = 1'h0 *) + reg \[13625] = 1'h0; + (* init = 1'h0 *) + reg \[13640] = 1'h0; + (* init = 1'h0 *) + reg \[13655] = 1'h0; + (* init = 1'h0 *) + reg \[13670] = 1'h0; + (* init = 1'h0 *) + reg \[13685] = 1'h0; + (* init = 1'h0 *) + reg \[13700] = 1'h0; + (* init = 1'h0 *) + reg \[13715] = 1'h0; + (* init = 1'h0 *) + reg \[13730] = 1'h0; + (* init = 1'h0 *) + reg \[13745] = 1'h0; + (* init = 1'h0 *) + reg \[13775] = 1'h0; + (* init = 1'h0 *) + reg \[13790] = 1'h0; + (* init = 1'h0 *) + reg \[13805] = 1'h0; + (* init = 1'h0 *) + reg \[13820] = 1'h0; + (* init = 1'h0 *) + reg \[13835] = 1'h0; + (* init = 1'h0 *) + reg \[13850] = 1'h0; + (* init = 1'h0 *) + reg \[13865] = 1'h0; + (* init = 1'h0 *) + reg \[13880] = 1'h0; + (* init = 1'h0 *) + reg \[13895] = 1'h0; + (* init = 1'h0 *) + reg \[13955] = 1'h0; + (* init = 1'h0 *) + reg \[13970] = 1'h0; + (* init = 1'h0 *) + reg \[13985] = 1'h0; + (* init = 1'h0 *) + reg \[14000] = 1'h0; + (* init = 1'h0 *) + reg \[14015] = 1'h0; + (* init = 1'h0 *) + reg \[14030] = 1'h0; + (* init = 1'h0 *) + reg \[14045] = 1'h0; + (* init = 1'h0 *) + reg \[14060] = 1'h0; + (* init = 1'h0 *) + reg \[14075] = 1'h0; + (* init = 1'h0 *) + reg \[14090] = 1'h0; + (* init = 1'h0 *) + reg \[14105] = 1'h0; + (* init = 1'h0 *) + reg \[14120] = 1'h0; + (* init = 1'h0 *) + reg \[14135] = 1'h0; + (* init = 1'h0 *) + reg \[14150] = 1'h0; + (* init = 1'h0 *) + reg \[14165] = 1'h0; + (* init = 1'h0 *) + reg \[14180] = 1'h0; + (* init = 1'h0 *) + reg \[14210] = 1'h0; + (* init = 1'h0 *) + reg \[14225] = 1'h0; + (* init = 1'h0 *) + reg \[14240] = 1'h0; + (* init = 1'h0 *) + reg \[14255] = 1'h0; + (* init = 1'h0 *) + reg \[14270] = 1'h0; + (* init = 1'h0 *) + reg \[14285] = 1'h0; + (* init = 1'h0 *) + reg \[14360] = 1'h0; + (* init = 1'h0 *) + reg \[14375] = 1'h0; + (* init = 1'h0 *) + reg \[14390] = 1'h0; + (* init = 1'h0 *) + reg \[14405] = 1'h0; + (* init = 1'h0 *) + reg \[14420] = 1'h0; + (* init = 1'h0 *) + reg \[14435] = 1'h0; + (* init = 1'h0 *) + reg \[14450] = 1'h0; + (* init = 1'h0 *) + reg \[14465] = 1'h0; + (* init = 1'h0 *) + reg \[14480] = 1'h0; + (* init = 1'h0 *) + reg \[14495] = 1'h0; + (* init = 1'h0 *) + reg \[14510] = 1'h0; + (* init = 1'h0 *) + reg \[14525] = 1'h0; + (* init = 1'h0 *) + reg \[14540] = 1'h0; + (* init = 1'h0 *) + reg \[14555] = 1'h0; + (* init = 1'h0 *) + reg \[14570] = 1'h0; + (* init = 1'h0 *) + reg \[14585] = 1'h0; + (* init = 1'h0 *) + reg \[14600] = 1'h0; + (* init = 1'h0 *) + reg \[14615] = 1'h0; + (* init = 1'h0 *) + reg \[14630] = 1'h0; + (* init = 1'h0 *) + reg \[14660] = 1'h0; + (* init = 1'h0 *) + reg \[14675] = 1'h0; + (* init = 1'h0 *) + reg \[14690] = 1'h0; + (* init = 1'h0 *) + reg \[14705] = 1'h0; + (* init = 1'h0 *) + reg \[14765] = 1'h0; + (* init = 1'h0 *) + reg \[14810] = 1'h0; + (* init = 1'h0 *) + reg \[14825] = 1'h0; + (* init = 1'h0 *) + reg \[14840] = 1'h0; + (* init = 1'h0 *) + reg \[14855] = 1'h0; + (* init = 1'h0 *) + reg \[14870] = 1'h0; + (* init = 1'h0 *) + reg \[14885] = 1'h0; + (* init = 1'h0 *) + reg \[14900] = 1'h0; + (* init = 1'h0 *) + reg \[14915] = 1'h0; + (* init = 1'h0 *) + reg \[14930] = 1'h0; + (* init = 1'h0 *) + reg \[14960] = 1'h0; + (* init = 1'h0 *) + reg \[14975] = 1'h0; + (* init = 1'h0 *) + reg \[14990] = 1'h0; + (* init = 1'h0 *) + reg \[15005] = 1'h0; + (* init = 1'h0 *) + reg \[15020] = 1'h0; + (* init = 1'h0 *) + reg \[15035] = 1'h0; + (* init = 1'h0 *) + reg \[15050] = 1'h0; + (* init = 1'h0 *) + reg \[15065] = 1'h0; + (* init = 1'h0 *) + reg \[15080] = 1'h0; + (* init = 1'h0 *) + reg \[15140] = 1'h0; + (* init = 1'h0 *) + reg \[15185] = 1'h0; + (* init = 1'h0 *) + reg \[15200] = 1'h0; + (* init = 1'h0 *) + reg \[15215] = 1'h0; + (* init = 1'h0 *) + reg \[15230] = 1'h0; + (* init = 1'h0 *) + reg \[15245] = 1'h0; + (* init = 1'h0 *) + reg \[15260] = 1'h0; + (* init = 1'h0 *) + reg \[15275] = 1'h0; + (* init = 1'h0 *) + reg \[15290] = 1'h0; + (* init = 1'h0 *) + reg \[15305] = 1'h0; + (* init = 1'h0 *) + reg \[15320] = 1'h0; + (* init = 1'h0 *) + reg \[15335] = 1'h0; + (* init = 1'h0 *) + reg \[15350] = 1'h0; + (* init = 1'h0 *) + reg \[15365] = 1'h0; + (* init = 1'h0 *) + reg \[15380] = 1'h0; + (* init = 1'h0 *) + reg \[15395] = 1'h0; + (* init = 1'h0 *) + reg \[15410] = 1'h0; + (* init = 1'h0 *) + reg \[15425] = 1'h0; + (* init = 1'h0 *) + reg \[15440] = 1'h0; + (* init = 1'h0 *) + reg \[15500] = 1'h0; + (* init = 1'h0 *) + reg \[15515] = 1'h0; + (* init = 1'h0 *) + reg \[15545] = 1'h0; + (* init = 1'h0 *) + reg \[15560] = 1'h0; + (* init = 1'h0 *) + reg \[15575] = 1'h0; + (* init = 1'h0 *) + reg \[15590] = 1'h0; + (* init = 1'h0 *) + reg \[15605] = 1'h0; + (* init = 1'h0 *) + reg \[15620] = 1'h0; + (* init = 1'h0 *) + reg \[15635] = 1'h0; + (* init = 1'h0 *) + reg \[15650] = 1'h0; + (* init = 1'h0 *) + reg \[15665] = 1'h0; + (* init = 1'h0 *) + reg \[15680] = 1'h0; + (* init = 1'h0 *) + reg \[15695] = 1'h0; + (* init = 1'h0 *) + reg \[15710] = 1'h0; + (* init = 1'h0 *) + reg \[15725] = 1'h0; + (* init = 1'h0 *) + reg \[15755] = 1'h0; + (* init = 1'h0 *) + reg \[15770] = 1'h0; + (* init = 1'h0 *) + reg \[15785] = 1'h0; + (* init = 1'h0 *) + reg \[15845] = 1'h0; + (* init = 1'h0 *) + reg \[15860] = 1'h0; + (* init = 1'h0 *) + reg \[15890] = 1'h0; + (* init = 1'h0 *) + reg \[15905] = 1'h0; + (* init = 1'h0 *) + reg \[15920] = 1'h0; + (* init = 1'h0 *) + reg \[15935] = 1'h0; + (* init = 1'h0 *) + reg \[15950] = 1'h0; + (* init = 1'h0 *) + reg \[15965] = 1'h0; + (* init = 1'h0 *) + reg \[15980] = 1'h0; + (* init = 1'h0 *) + reg \[15995] = 1'h0; + (* init = 1'h0 *) + reg \[16010] = 1'h0; + (* init = 1'h0 *) + reg \[16025] = 1'h0; + (* init = 1'h0 *) + reg \[16040] = 1'h0; + (* init = 1'h0 *) + reg \[16055] = 1'h0; + (* init = 1'h0 *) + reg \[16070] = 1'h0; + (* init = 1'h0 *) + reg \[16085] = 1'h0; + (* init = 1'h0 *) + reg \[16100] = 1'h0; + (* init = 1'h0 *) + reg \[16907] = 1'h0; + (* init = 1'h0 *) + reg \[16920] = 1'h0; + (* init = 1'h0 *) + reg \[16933] = 1'h0; + (* init = 1'h0 *) + reg \[16959] = 1'h0; + (* init = 1'h0 *) + reg \[16972] = 1'h0; + (* init = 1'h0 *) + reg \[16985] = 1'h0; + (* init = 1'h0 *) + reg \[16998] = 1'h0; + (* init = 1'h0 *) + reg \[17011] = 1'h0; + (* init = 1'h0 *) + reg \[17024] = 1'h0; + (* init = 1'h0 *) + reg \[17037] = 1'h0; + (* init = 1'h0 *) + reg \[17050] = 1'h0; + (* init = 1'h0 *) + reg \[17063] = 1'h0; + (* init = 1'h0 *) + reg \[17076] = 1'h0; + (* init = 1'h0 *) + reg \[17089] = 1'h0; + (* init = 1'h0 *) + reg \[17102] = 1'h0; + (* init = 1'h0 *) + reg \[17115] = 1'h0; + (* init = 1'h0 *) + reg \[17128] = 1'h0; + (* init = 1'h0 *) + reg \[17141] = 1'h0; + (* init = 1'h0 *) + reg \[17154] = 1'h0; + (* init = 1'h0 *) + reg \[17167] = 1'h0; + (* init = 1'h0 *) + reg \[17180] = 1'h0; + (* init = 1'h0 *) + reg \[17193] = 1'h0; + (* init = 1'h0 *) + reg \[17206] = 1'h0; + (* init = 1'h0 *) + reg \[17219] = 1'h0; + (* init = 1'h0 *) + reg \[17232] = 1'h0; + (* init = 1'h0 *) + reg \[17245] = 1'h0; + (* init = 1'h0 *) + reg \[17258] = 1'h0; + (* init = 1'h0 *) + reg \[17271] = 1'h0; + (* init = 1'h0 *) + reg \[17284] = 1'h0; + (* init = 1'h0 *) + reg \[17297] = 1'h0; + (* init = 1'h0 *) + reg \[17310] = 1'h0; + (* init = 1'h0 *) + reg \[17323] = 1'h0; + (* init = 1'h0 *) + reg \[17336] = 1'h0; + (* init = 1'h0 *) + reg \[17349] = 1'h0; + (* init = 1'h0 *) + reg \[17362] = 1'h0; + (* init = 1'h0 *) + reg \[17375] = 1'h0; + (* init = 1'h0 *) + reg \[17388] = 1'h0; + (* init = 1'h0 *) + reg \[17414] = 1'h0; + (* init = 1'h0 *) + reg \[17427] = 1'h0; + (* init = 1'h0 *) + reg \[17453] = 1'h0; + (* init = 1'h0 *) + reg \[17479] = 1'h0; + (* init = 1'h0 *) + reg \[17492] = 1'h0; + (* init = 1'h0 *) + reg \[17505] = 1'h0; + (* init = 1'h0 *) + reg \[17518] = 1'h0; + (* init = 1'h0 *) + reg \[17531] = 1'h0; + (* init = 1'h0 *) + reg \[17544] = 1'h0; + (* init = 1'h0 *) + reg \[17570] = 1'h0; + (* init = 1'h0 *) + reg \[17583] = 1'h0; + (* init = 1'h0 *) + reg \[17596] = 1'h0; + (* init = 1'h0 *) + reg \[17609] = 1'h0; + (* init = 1'h0 *) + reg \[17635] = 1'h0; + (* init = 1'h0 *) + reg \[17648] = 1'h0; + (* init = 1'h0 *) + reg \[17661] = 1'h0; + (* init = 1'h0 *) + reg \[17674] = 1'h0; + (* init = 1'h0 *) + reg \[17700] = 1'h0; + (* init = 1'h0 *) + reg \[17713] = 1'h0; + (* init = 1'h0 *) + reg \[17739] = 1'h0; + (* init = 1'h0 *) + reg \[17752] = 1'h0; + (* init = 1'h0 *) + reg \[17765] = 1'h0; + (* init = 1'h0 *) + reg \[17778] = 1'h0; + (* init = 1'h0 *) + reg \[17791] = 1'h0; + (* init = 1'h0 *) + reg \[17804] = 1'h0; + (* init = 1'h0 *) + reg \[17817] = 1'h0; + (* init = 1'h0 *) + reg \[17843] = 1'h0; + (* init = 1'h0 *) + reg \[17856] = 1'h0; + (* init = 1'h0 *) + reg \[17869] = 1'h0; + (* init = 1'h0 *) + reg \[17882] = 1'h0; + (* init = 1'h0 *) + reg \[17908] = 1'h0; + (* init = 1'h0 *) + reg \[17921] = 1'h0; + (* init = 1'h0 *) + reg \[17934] = 1'h0; + (* init = 1'h0 *) + reg \[17947] = 1'h0; + (* init = 1'h0 *) + reg \[17960] = 1'h0; + (* init = 1'h0 *) + reg \[17973] = 1'h0; + (* init = 1'h0 *) + reg \[17986] = 1'h0; + (* init = 1'h0 *) + reg \[17999] = 1'h0; + (* init = 1'h0 *) + reg \[18012] = 1'h0; + (* init = 1'h0 *) + reg \[18025] = 1'h0; + (* init = 1'h0 *) + reg \[18038] = 1'h0; + (* init = 1'h0 *) + reg \[18064] = 1'h0; + (* init = 1'h0 *) + reg \[18077] = 1'h0; + (* init = 1'h0 *) + reg \[18090] = 1'h0; + (* init = 1'h0 *) + reg \[18103] = 1'h0; + (* init = 1'h0 *) + reg \[18116] = 1'h0; + (* init = 1'h0 *) + reg \[18129] = 1'h0; + (* init = 1'h0 *) + reg \[18142] = 1'h0; + (* init = 1'h0 *) + reg \[18155] = 1'h0; + (* init = 1'h0 *) + reg \[18168] = 1'h0; + (* init = 1'h0 *) + reg \[18181] = 1'h0; + (* init = 1'h0 *) + reg \[18194] = 1'h0; + (* init = 1'h0 *) + reg \[18207] = 1'h0; + (* init = 1'h0 *) + reg \[18220] = 1'h0; + (* init = 1'h0 *) + reg \[18233] = 1'h0; + (* init = 1'h0 *) + reg \[18246] = 1'h0; + (* init = 1'h0 *) + reg \[18285] = 1'h0; + (* init = 1'h0 *) + reg \[18298] = 1'h0; + (* init = 1'h0 *) + reg \[18311] = 1'h0; + (* init = 1'h0 *) + reg \[18337] = 1'h0; + (* init = 1'h0 *) + reg \[18350] = 1'h0; + (* init = 1'h0 *) + reg \[18363] = 1'h0; + (* init = 1'h0 *) + reg \[18376] = 1'h0; + (* init = 1'h0 *) + reg \[18389] = 1'h0; + (* init = 1'h0 *) + reg \[18415] = 1'h0; + (* init = 1'h0 *) + reg \[18428] = 1'h0; + (* init = 1'h0 *) + reg \[18441] = 1'h0; + (* init = 1'h0 *) + reg \[18467] = 1'h0; + (* init = 1'h0 *) + reg \[18480] = 1'h0; + (* init = 1'h0 *) + reg \[18493] = 1'h0; + (* init = 1'h0 *) + reg \[18506] = 1'h0; + (* init = 1'h0 *) + reg \[18545] = 1'h0; + (* init = 1'h0 *) + reg \[18571] = 1'h0; + (* init = 1'h0 *) + reg \[18584] = 1'h0; + (* init = 1'h0 *) + reg \[18597] = 1'h0; + (* init = 1'h0 *) + reg \[18610] = 1'h0; + (* init = 1'h0 *) + reg \[18636] = 1'h0; + (* init = 1'h0 *) + reg \[4295] = 1'h0; + (* init = 1'h0 *) + reg \[4310] = 1'h0; + (* init = 1'h0 *) + reg \[4355] = 1'h0; + (* init = 1'h0 *) + reg \[4370] = 1'h0; + (* init = 1'h0 *) + reg \[4385] = 1'h0; + (* init = 1'h0 *) + reg \[4400] = 1'h0; + (* init = 1'h0 *) + reg \[4415] = 1'h0; + (* init = 1'h0 *) + reg \[4430] = 1'h0; + (* init = 1'h0 *) + reg \[4445] = 1'h0; + (* init = 1'h0 *) + reg \[4460] = 1'h0; + (* init = 1'h0 *) + reg \[4475] = 1'h0; + (* init = 1'h0 *) + reg \[4490] = 1'h0; + (* init = 1'h0 *) + reg \[4505] = 1'h0; + (* init = 1'h0 *) + reg \[4520] = 1'h0; + (* init = 1'h0 *) + reg \[4535] = 1'h0; + (* init = 1'h0 *) + reg \[4550] = 1'h0; + (* init = 1'h0 *) + reg \[4565] = 1'h0; + (* init = 1'h0 *) + reg \[4580] = 1'h0; + (* init = 1'h0 *) + reg \[4595] = 1'h0; + (* init = 1'h0 *) + reg \[4610] = 1'h0; + (* init = 1'h0 *) + reg \[4625] = 1'h0; + (* init = 1'h0 *) + reg \[4640] = 1'h0; + (* init = 1'h0 *) + reg \[4655] = 1'h0; + (* init = 1'h0 *) + reg \[4670] = 1'h0; + (* init = 1'h0 *) + reg \[4700] = 1'h0; + (* init = 1'h0 *) + reg \[4715] = 1'h0; + (* init = 1'h0 *) + reg \[4730] = 1'h0; + (* init = 1'h0 *) + reg \[4745] = 1'h0; + (* init = 1'h0 *) + reg \[4760] = 1'h0; + (* init = 1'h0 *) + reg \[4775] = 1'h0; + (* init = 1'h0 *) + reg \[4790] = 1'h0; + (* init = 1'h0 *) + reg \[4805] = 1'h0; + (* init = 1'h0 *) + reg \[4820] = 1'h0; + (* init = 1'h0 *) + reg \[4835] = 1'h0; + (* init = 1'h0 *) + reg \[4850] = 1'h0; + (* init = 1'h0 *) + reg \[4865] = 1'h0; + (* init = 1'h0 *) + reg \[4880] = 1'h0; + (* init = 1'h0 *) + reg \[4895] = 1'h0; + (* init = 1'h0 *) + reg \[4910] = 1'h0; + (* init = 1'h0 *) + reg \[4925] = 1'h0; + (* init = 1'h0 *) + reg \[4940] = 1'h0; + (* init = 1'h0 *) + reg \[4955] = 1'h0; + (* init = 1'h0 *) + reg \[4970] = 1'h0; + (* init = 1'h0 *) + reg \[5015] = 1'h0; + (* init = 1'h0 *) + reg \[5030] = 1'h0; + (* init = 1'h0 *) + reg \[5075] = 1'h0; + (* init = 1'h0 *) + reg \[5090] = 1'h0; + (* init = 1'h0 *) + reg \[5105] = 1'h0; + (* init = 1'h0 *) + reg \[5120] = 1'h0; + (* init = 1'h0 *) + reg \[5135] = 1'h0; + (* init = 1'h0 *) + reg \[5150] = 1'h0; + (* init = 1'h0 *) + reg \[5165] = 1'h0; + (* init = 1'h0 *) + reg \[5180] = 1'h0; + (* init = 1'h0 *) + reg \[5195] = 1'h0; + (* init = 1'h0 *) + reg \[5210] = 1'h0; + (* init = 1'h0 *) + reg \[5225] = 1'h0; + (* init = 1'h0 *) + reg \[5240] = 1'h0; + (* init = 1'h0 *) + reg \[5255] = 1'h0; + (* init = 1'h0 *) + reg \[5270] = 1'h0; + (* init = 1'h0 *) + reg \[5285] = 1'h0; + (* init = 1'h0 *) + reg \[5300] = 1'h0; + (* init = 1'h0 *) + reg \[5315] = 1'h0; + (* init = 1'h0 *) + reg \[5330] = 1'h0; + (* init = 1'h0 *) + reg \[5345] = 1'h0; + (* init = 1'h0 *) + reg \[5360] = 1'h0; + (* init = 1'h0 *) + reg \[5375] = 1'h0; + (* init = 1'h0 *) + reg \[5390] = 1'h0; + (* init = 1'h0 *) + reg \[5405] = 1'h0; + (* init = 1'h0 *) + reg \[5420] = 1'h0; + (* init = 1'h0 *) + reg \[5435] = 1'h0; + (* init = 1'h0 *) + reg \[5450] = 1'h0; + (* init = 1'h0 *) + reg \[5465] = 1'h0; + (* init = 1'h0 *) + reg \[5480] = 1'h0; + (* init = 1'h0 *) + reg \[5495] = 1'h0; + (* init = 1'h0 *) + reg \[5510] = 1'h0; + (* init = 1'h0 *) + reg \[5525] = 1'h0; + (* init = 1'h0 *) + reg \[5540] = 1'h0; + (* init = 1'h0 *) + reg \[5555] = 1'h0; + (* init = 1'h0 *) + reg \[5570] = 1'h0; + (* init = 1'h0 *) + reg \[5600] = 1'h0; + (* init = 1'h0 *) + reg \[5615] = 1'h0; + (* init = 1'h0 *) + reg \[5630] = 1'h0; + (* init = 1'h0 *) + reg \[5645] = 1'h0; + (* init = 1'h0 *) + reg \[5660] = 1'h0; + (* init = 1'h0 *) + reg \[5675] = 1'h0; + (* init = 1'h0 *) + reg \[5720] = 1'h0; + (* init = 1'h0 *) + reg \[5780] = 1'h0; + (* init = 1'h0 *) + reg \[5795] = 1'h0; + (* init = 1'h0 *) + reg \[5810] = 1'h0; + (* init = 1'h0 *) + reg \[5825] = 1'h0; + (* init = 1'h0 *) + reg \[5840] = 1'h0; + (* init = 1'h0 *) + reg \[5855] = 1'h0; + (* init = 1'h0 *) + reg \[5870] = 1'h0; + (* init = 1'h0 *) + reg \[5885] = 1'h0; + (* init = 1'h0 *) + reg \[5900] = 1'h0; + (* init = 1'h0 *) + reg \[5915] = 1'h0; + (* init = 1'h0 *) + reg \[5930] = 1'h0; + (* init = 1'h0 *) + reg \[5945] = 1'h0; + (* init = 1'h0 *) + reg \[5960] = 1'h0; + (* init = 1'h0 *) + reg \[5975] = 1'h0; + (* init = 1'h0 *) + reg \[5990] = 1'h0; + (* init = 1'h0 *) + reg \[6005] = 1'h0; + (* init = 1'h0 *) + reg \[6020] = 1'h0; + (* init = 1'h0 *) + reg \[6035] = 1'h0; + (* init = 1'h0 *) + reg \[6050] = 1'h0; + (* init = 1'h0 *) + reg \[6065] = 1'h0; + (* init = 1'h0 *) + reg \[6080] = 1'h0; + (* init = 1'h0 *) + reg \[6095] = 1'h0; + (* init = 1'h0 *) + reg \[6110] = 1'h0; + (* init = 1'h0 *) + reg \[6125] = 1'h0; + (* init = 1'h0 *) + reg \[6140] = 1'h0; + (* init = 1'h0 *) + reg \[6155] = 1'h0; + (* init = 1'h0 *) + reg \[6170] = 1'h0; + (* init = 1'h0 *) + reg \[6185] = 1'h0; + (* init = 1'h0 *) + reg \[6200] = 1'h0; + (* init = 1'h0 *) + reg \[6215] = 1'h0; + (* init = 1'h0 *) + reg \[6230] = 1'h0; + (* init = 1'h0 *) + reg \[6245] = 1'h0; + (* init = 1'h0 *) + reg \[6260] = 1'h0; + (* init = 1'h0 *) + reg \[6275] = 1'h0; + (* init = 1'h0 *) + reg \[6290] = 1'h0; + (* init = 1'h0 *) + reg \[6305] = 1'h0; + (* init = 1'h0 *) + reg \[6320] = 1'h0; + (* init = 1'h0 *) + reg \[6335] = 1'h0; + (* init = 1'h0 *) + reg \[6350] = 1'h0; + (* init = 1'h0 *) + reg \[6365] = 1'h0; + (* init = 1'h0 *) + reg \[6410] = 1'h0; + (* init = 1'h0 *) + reg \[6470] = 1'h0; + (* init = 1'h0 *) + reg \[6485] = 1'h0; + (* init = 1'h0 *) + reg \[6500] = 1'h0; + (* init = 1'h0 *) + reg \[6515] = 1'h0; + (* init = 1'h0 *) + reg \[6530] = 1'h0; + (* init = 1'h0 *) + reg \[6545] = 1'h0; + (* init = 1'h0 *) + reg \[6560] = 1'h0; + (* init = 1'h0 *) + reg \[6575] = 1'h0; + (* init = 1'h0 *) + reg \[6590] = 1'h0; + (* init = 1'h0 *) + reg \[6605] = 1'h0; + (* init = 1'h0 *) + reg \[6620] = 1'h0; + (* init = 1'h0 *) + reg \[6635] = 1'h0; + (* init = 1'h0 *) + reg \[6650] = 1'h0; + (* init = 1'h0 *) + reg \[6665] = 1'h0; + (* init = 1'h0 *) + reg \[6680] = 1'h0; + (* init = 1'h0 *) + reg \[6695] = 1'h0; + (* init = 1'h0 *) + reg \[6710] = 1'h0; + (* init = 1'h0 *) + reg \[6725] = 1'h0; + (* init = 1'h0 *) + reg \[6740] = 1'h0; + (* init = 1'h0 *) + reg \[6755] = 1'h0; + (* init = 1'h0 *) + reg \[6770] = 1'h0; + (* init = 1'h0 *) + reg \[6785] = 1'h0; + (* init = 1'h0 *) + reg \[6815] = 1'h0; + (* init = 1'h0 *) + reg \[6830] = 1'h0; + (* init = 1'h0 *) + reg \[6845] = 1'h0; + (* init = 1'h0 *) + reg \[6860] = 1'h0; + (* init = 1'h0 *) + reg \[6875] = 1'h0; + (* init = 1'h0 *) + reg \[6890] = 1'h0; + (* init = 1'h0 *) + reg \[6905] = 1'h0; + (* init = 1'h0 *) + reg \[6920] = 1'h0; + (* init = 1'h0 *) + reg \[6935] = 1'h0; + (* init = 1'h0 *) + reg \[6950] = 1'h0; + (* init = 1'h0 *) + reg \[6965] = 1'h0; + (* init = 1'h0 *) + reg \[6980] = 1'h0; + (* init = 1'h0 *) + reg \[6995] = 1'h0; + (* init = 1'h0 *) + reg \[7010] = 1'h0; + (* init = 1'h0 *) + reg \[7025] = 1'h0; + (* init = 1'h0 *) + reg \[7055] = 1'h0; + (* init = 1'h0 *) + reg \[7115] = 1'h0; + (* init = 1'h0 *) + reg \[7130] = 1'h0; + (* init = 1'h0 *) + reg \[7145] = 1'h0; + (* init = 1'h0 *) + reg \[7160] = 1'h0; + (* init = 1'h0 *) + reg \[7175] = 1'h0; + (* init = 1'h0 *) + reg \[7190] = 1'h0; + (* init = 1'h0 *) + reg \[7205] = 1'h0; + (* init = 1'h0 *) + reg \[7220] = 1'h0; + (* init = 1'h0 *) + reg \[7235] = 1'h0; + (* init = 1'h0 *) + reg \[7250] = 1'h0; + (* init = 1'h0 *) + reg \[7265] = 1'h0; + (* init = 1'h0 *) + reg \[7280] = 1'h0; + (* init = 1'h0 *) + reg \[7295] = 1'h0; + (* init = 1'h0 *) + reg \[7310] = 1'h0; + (* init = 1'h0 *) + reg \[7325] = 1'h0; + (* init = 1'h0 *) + reg \[7340] = 1'h0; + (* init = 1'h0 *) + reg \[7355] = 1'h0; + (* init = 1'h0 *) + reg \[7370] = 1'h0; + (* init = 1'h0 *) + reg \[7385] = 1'h0; + (* init = 1'h0 *) + reg \[7400] = 1'h0; + (* init = 1'h0 *) + reg \[7415] = 1'h0; + (* init = 1'h0 *) + reg \[7430] = 1'h0; + (* init = 1'h0 *) + reg \[7445] = 1'h0; + (* init = 1'h0 *) + reg \[7460] = 1'h0; + (* init = 1'h0 *) + reg \[7475] = 1'h0; + (* init = 1'h0 *) + reg \[7490] = 1'h0; + (* init = 1'h0 *) + reg \[7505] = 1'h0; + (* init = 1'h0 *) + reg \[7520] = 1'h0; + (* init = 1'h0 *) + reg \[7535] = 1'h0; + (* init = 1'h0 *) + reg \[7550] = 1'h0; + (* init = 1'h0 *) + reg \[7565] = 1'h0; + (* init = 1'h0 *) + reg \[7580] = 1'h0; + (* init = 1'h0 *) + reg \[7595] = 1'h0; + (* init = 1'h0 *) + reg \[7625] = 1'h0; + (* init = 1'h0 *) + reg \[7640] = 1'h0; + (* init = 1'h0 *) + reg \[7655] = 1'h0; + (* init = 1'h0 *) + reg \[7670] = 1'h0; + (* init = 1'h0 *) + reg \[7685] = 1'h0; + (* init = 1'h0 *) + reg \[7745] = 1'h0; + (* init = 1'h0 *) + reg \[7760] = 1'h0; + (* init = 1'h0 *) + reg \[7775] = 1'h0; + (* init = 1'h0 *) + reg \[7790] = 1'h0; + (* init = 1'h0 *) + reg \[7805] = 1'h0; + (* init = 1'h0 *) + reg \[7820] = 1'h0; + (* init = 1'h0 *) + reg \[7835] = 1'h0; + (* init = 1'h0 *) + reg \[7850] = 1'h0; + (* init = 1'h0 *) + reg \[7865] = 1'h0; + (* init = 1'h0 *) + reg \[7880] = 1'h0; + (* init = 1'h0 *) + reg \[7895] = 1'h0; + (* init = 1'h0 *) + reg \[7910] = 1'h0; + (* init = 1'h0 *) + reg \[7925] = 1'h0; + (* init = 1'h0 *) + reg \[7940] = 1'h0; + (* init = 1'h0 *) + reg \[7955] = 1'h0; + (* init = 1'h0 *) + reg \[7970] = 1'h0; + (* init = 1'h0 *) + reg \[8000] = 1'h0; + (* init = 1'h0 *) + reg \[8015] = 1'h0; + (* init = 1'h0 *) + reg \[8030] = 1'h0; + (* init = 1'h0 *) + reg \[8045] = 1'h0; + (* init = 1'h0 *) + reg \[8060] = 1'h0; + (* init = 1'h0 *) + reg \[8075] = 1'h0; + (* init = 1'h0 *) + reg \[8090] = 1'h0; + (* init = 1'h0 *) + reg \[8105] = 1'h0; + (* init = 1'h0 *) + reg \[8120] = 1'h0; + (* init = 1'h0 *) + reg \[8135] = 1'h0; + (* init = 1'h0 *) + reg \[8150] = 1'h0; + (* init = 1'h0 *) + reg \[8165] = 1'h0; + (* init = 1'h0 *) + reg \[8180] = 1'h0; + (* init = 1'h0 *) + reg \[8195] = 1'h0; + (* init = 1'h0 *) + reg \[8210] = 1'h0; + (* init = 1'h0 *) + reg \[8225] = 1'h0; + (* init = 1'h0 *) + reg \[8240] = 1'h0; + (* init = 1'h0 *) + reg \[8255] = 1'h0; + (* init = 1'h0 *) + reg \[8285] = 1'h0; + (* init = 1'h0 *) + reg \[8300] = 1'h0; + (* init = 1'h0 *) + reg \[8315] = 1'h0; + (* init = 1'h0 *) + reg \[8330] = 1'h0; + (* init = 1'h0 *) + reg \[8390] = 1'h0; + (* init = 1'h0 *) + reg \[8405] = 1'h0; + (* init = 1'h0 *) + reg \[8420] = 1'h0; + (* init = 1'h0 *) + reg \[8435] = 1'h0; + (* init = 1'h0 *) + reg \[8450] = 1'h0; + (* init = 1'h0 *) + reg \[8465] = 1'h0; + (* init = 1'h0 *) + reg \[8480] = 1'h0; + (* init = 1'h0 *) + reg \[8495] = 1'h0; + (* init = 1'h0 *) + reg \[8510] = 1'h0; + (* init = 1'h0 *) + reg \[8525] = 1'h0; + (* init = 1'h0 *) + reg \[8540] = 1'h0; + (* init = 1'h0 *) + reg \[8555] = 1'h0; + (* init = 1'h0 *) + reg \[8570] = 1'h0; + (* init = 1'h0 *) + reg \[8585] = 1'h0; + (* init = 1'h0 *) + reg \[8600] = 1'h0; + (* init = 1'h0 *) + reg \[8615] = 1'h0; + (* init = 1'h0 *) + reg \[8630] = 1'h0; + (* init = 1'h0 *) + reg \[8645] = 1'h0; + (* init = 1'h0 *) + reg \[8660] = 1'h0; + (* init = 1'h0 *) + reg \[8675] = 1'h0; + (* init = 1'h0 *) + reg \[8690] = 1'h0; + (* init = 1'h0 *) + reg \[8705] = 1'h0; + (* init = 1'h0 *) + reg \[8720] = 1'h0; + (* init = 1'h0 *) + reg \[8735] = 1'h0; + (* init = 1'h0 *) + reg \[8750] = 1'h0; + (* init = 1'h0 *) + reg \[8765] = 1'h0; + (* init = 1'h0 *) + reg \[8780] = 1'h0; + (* init = 1'h0 *) + reg \[8810] = 1'h0; + (* init = 1'h0 *) + reg \[8825] = 1'h0; + (* init = 1'h0 *) + reg \[8840] = 1'h0; + (* init = 1'h0 *) + reg \[8855] = 1'h0; + (* init = 1'h0 *) + reg \[8870] = 1'h0; + (* init = 1'h0 *) + reg \[8885] = 1'h0; + (* init = 1'h0 *) + reg \[8900] = 1'h0; + (* init = 1'h0 *) + reg \[8915] = 1'h0; + (* init = 1'h0 *) + reg \[8930] = 1'h0; + (* init = 1'h0 *) + reg \[8945] = 1'h0; + (* init = 1'h0 *) + reg \[8960] = 1'h0; + (* init = 1'h0 *) + reg \[8975] = 1'h0; + (* init = 1'h0 *) + reg \[9050] = 1'h0; + (* init = 1'h0 *) + reg \[9065] = 1'h0; + (* init = 1'h0 *) + reg \[9080] = 1'h0; + (* init = 1'h0 *) + reg \[9095] = 1'h0; + (* init = 1'h0 *) + reg \[9110] = 1'h0; + (* init = 1'h0 *) + reg \[9125] = 1'h0; + (* init = 1'h0 *) + reg \[9140] = 1'h0; + (* init = 1'h0 *) + reg \[9155] = 1'h0; + (* init = 1'h0 *) + reg \[9170] = 1'h0; + (* init = 1'h0 *) + reg \[9185] = 1'h0; + (* init = 1'h0 *) + reg \[9200] = 1'h0; + (* init = 1'h0 *) + reg \[9215] = 1'h0; + (* init = 1'h0 *) + reg \[9230] = 1'h0; + (* init = 1'h0 *) + reg \[9245] = 1'h0; + (* init = 1'h0 *) + reg \[9260] = 1'h0; + (* init = 1'h0 *) + reg \[9275] = 1'h0; + (* init = 1'h0 *) + reg \[9290] = 1'h0; + (* init = 1'h0 *) + reg \[9305] = 1'h0; + (* init = 1'h0 *) + reg \[9320] = 1'h0; + (* init = 1'h0 *) + reg \[9335] = 1'h0; + (* init = 1'h0 *) + reg \[9350] = 1'h0; + (* init = 1'h0 *) + reg \[9365] = 1'h0; + (* init = 1'h0 *) + reg \[9380] = 1'h0; + (* init = 1'h0 *) + reg \[9395] = 1'h0; + (* init = 1'h0 *) + reg \[9410] = 1'h0; + (* init = 1'h0 *) + reg \[9440] = 1'h0; + (* init = 1'h0 *) + reg \[9455] = 1'h0; + (* init = 1'h0 *) + reg \[9470] = 1'h0; + (* init = 1'h0 *) + reg \[9485] = 1'h0; + (* init = 1'h0 *) + reg \[9500] = 1'h0; + (* init = 1'h0 *) + reg \[9515] = 1'h0; + (* init = 1'h0 *) + reg \[9530] = 1'h0; + (* init = 1'h0 *) + reg \[9545] = 1'h0; + (* init = 1'h0 *) + reg \[9560] = 1'h0; + (* init = 1'h0 *) + reg \[9575] = 1'h0; + (* init = 1'h0 *) + reg \[9590] = 1'h0; + (* init = 1'h0 *) + reg \[9605] = 1'h0; + (* init = 1'h0 *) + reg \[9620] = 1'h0; + (* init = 1'h0 *) + reg \[9635] = 1'h0; + (* init = 1'h0 *) + reg \[9650] = 1'h0; + (* init = 1'h0 *) + reg \[9665] = 1'h0; + (* init = 1'h0 *) + reg \[9680] = 1'h0; + (* init = 1'h0 *) + reg \[9710] = 1'h0; + (* init = 1'h0 *) + reg \[9725] = 1'h0; + (* init = 1'h0 *) + reg \[9740] = 1'h0; + (* init = 1'h0 *) + reg \[9770] = 1'h0; + (* init = 1'h0 *) + reg \[9785] = 1'h0; + (* init = 1'h0 *) + reg \[9800] = 1'h0; + (* init = 1'h0 *) + reg \[9815] = 1'h0; + (* init = 1'h0 *) + reg \[9830] = 1'h0; + (* init = 1'h0 *) + reg \[9845] = 1'h0; + (* init = 1'h0 *) + reg \[9860] = 1'h0; + (* init = 1'h0 *) + reg \[9875] = 1'h0; + (* init = 1'h0 *) + reg \[9890] = 1'h0; + (* init = 1'h0 *) + reg \[9905] = 1'h0; + (* init = 1'h0 *) + reg \[9920] = 1'h0; + (* init = 1'h0 *) + reg \[9935] = 1'h0; + (* init = 1'h0 *) + reg \[9950] = 1'h0; + (* init = 1'h0 *) + reg \[9980] = 1'h0; + (* init = 1'h0 *) + reg \[9995] = 1'h0; + wire n1003; + wire n1008; + wire n1013; + wire n1018; + wire n1023; + wire n1028; + wire n1033; + wire n1038; + wire n1043; + wire n1048; + wire n1053; + wire n1058; + wire n1063; + wire n1068; + wire n1073; + wire n1078; + wire n1083; + wire n1088; + wire n1093; + wire n1098; + wire n1103; + wire n1108; + wire n1113; + wire n1118; + wire n1123; + wire n1128; + wire n1133; + wire n1138; + wire n1143; + wire n1148; + wire n1153; + wire n1158; + wire n1163; + wire n1168; + wire n1173; + wire n1178; + wire n1183_1; + wire n1188; + wire n1193; + wire n1198; + wire n1203; + wire n1208; + wire n1213; + wire n1218; + wire n1223; + wire n1228; + wire n1233; + wire n1238; + wire n1243; + wire n1248; + wire n1253; + wire n1258; + wire n1263; + wire n1268; + wire n1273; + wire n1278; + wire n1283; + wire n1288; + wire n1293; + wire n1298; + wire n1303; + wire n1308; + wire n1313; + wire n1318; + wire n1323; + wire n1328; + wire n1333; + wire n1338; + wire n1343; + wire n1348; + wire n1353; + wire n1358; + wire n1363; + wire n1368; + wire n1373; + wire n1378; + wire n1383; + wire n1388; + wire n1393_1; + wire n1398_1; + wire n1403_1; + wire n1408_1; + wire n1413_1; + wire n1418_1; + wire n1423_1; + wire n1428_1; + wire n1433_1; + wire n1438_1; + wire n1443_1; + wire n1448_1; + wire n1453_1; + wire n1458_1; + wire n1463_1; + wire n1468_1; + wire n1473_1; + wire n1478_1; + wire n1483_1; + wire n1488_1; + wire n1493_1; + wire n1498_1; + wire n1503_1; + wire n1508_1; + wire n1513_1; + wire n1518_1; + wire n1523_1; + wire n1528_1; + wire n1533_1; + wire n1538_1; + wire n1543_1; + wire n1548_1; + wire n1553_1; + wire n1558_1; + wire n1563_1; + wire n1568_1; + wire n1573_1; + wire n1578_1; + wire n1583_1; + wire n1588; + wire n1593; + wire n1598; + wire n1603; + wire n1608; + wire n1613; + wire n1618; + wire n1623; + wire n1628; + wire n1633; + wire n1638; + wire n1643; + wire n1648; + wire n1653; + wire n1658; + wire n1663; + wire n1668; + wire n1673; + wire n1678; + wire n1683; + wire n1688; + wire n1693; + wire n1698; + wire n1703; + wire n1708; + wire n1713; + wire n1718; + wire n1723; + wire n1728; + wire n1733; + wire n1738; + wire n1743; + wire n1748; + wire n1753; + wire n1758; + wire n1763; + wire n1768; + wire n1773; + wire n1778; + wire n1783; + wire n1788; + wire n1793; + wire n1798_1; + wire n1803; + wire n1808; + wire n1813; + wire n1818; + wire n1823; + wire n1828; + wire n1833; + wire n1838; + wire n1843; + wire n1848; + wire n1853; + wire n1858; + wire n1863; + wire n1868; + wire n1873; + wire n1878; + wire n1883; + wire n1888; + wire n1893; + wire n1898; + wire n1903; + wire n1908; + wire n1913; + wire n1918; + wire n1923; + wire n1928; + wire n1933; + wire n1938; + wire n1943; + wire n1948; + wire n1953; + wire n1958; + wire n1963; + wire n1968; + wire n1973; + wire n1978; + wire n1983; + wire n1988; + wire n1993; + wire n1998; + wire n2003; + wire n2008; + wire n2013; + wire n2018; + wire n2023; + wire n2028; + wire n2033; + wire n2038; + wire n2043; + wire n2048; + wire n2053; + wire n2058; + wire n2063; + wire n2068; + wire n2073; + wire n2078; + wire n2083; + wire n2088; + wire n2093; + wire n2098; + wire n2103; + wire n2108; + wire n2113; + wire n2118; + wire n2123; + wire n2128; + wire n2133; + wire n2138; + wire n2143; + wire n2148; + wire n2153; + wire n2158; + wire n2163; + wire n2168; + wire n2173; + wire n2178; + wire n2183; + wire n2188_1; + wire n2193_1; + wire n2198_1; + wire n2203_1; + wire n2208_1; + wire n2213_1; + wire n2218_1; + wire n2223_1; + wire n2228_1; + wire n2233_1; + wire n2238_1; + wire n2243_1; + wire n2248_1; + wire n2253_1; + wire n2258_1; + wire n2263_1; + wire n2268; + wire n2273; + wire n2278; + wire n2283; + wire n2288; + wire n2293; + wire n2298; + wire n2303; + wire n2308; + wire n2313; + wire n2318; + wire n2323; + wire n2328; + wire n2333; + wire n2338; + wire n2343; + wire n2348; + wire n2353; + wire n2358; + wire n2363; + wire n2368; + wire n2373; + wire n2378; + wire n2383; + wire n2388; + wire n2393; + wire n2398; + wire n2403; + wire n2408; + wire n2413; + wire n2418; + wire n2423; + wire n2428; + wire n2433; + wire n2438; + wire n2443; + wire n2448; + wire n2453; + wire n2458; + wire n2463; + wire n2468; + wire n2473; + wire n2478; + wire n2483; + wire n2488; + wire n2493; + wire n2498; + wire n2503; + wire n2508; + wire n2513; + wire n2518; + wire n2523; + wire n2528; + wire n2533; + wire n2538; + wire n2543; + wire n2548; + wire n2553; + wire n2558; + wire n2563; + wire n2568; + wire n2573; + wire n2578; + wire n2583; + wire n2588; + wire n2593; + wire n2598; + wire n2603; + wire n2608; + wire n2613; + wire n2618; + wire n2623; + wire n2628; + wire n2633; + wire n2638; + wire n2643; + wire n2648; + wire n2653; + wire n2658; + wire n2663; + wire n2668; + wire n2673; + wire n2678; + wire n2683; + wire n2688; + wire n2693; + wire n2698_1; + wire n2703; + wire n2708; + wire n2713; + wire n2718; + wire n2723; + wire n2728; + wire n2733; + wire n2738; + wire n273_1; + wire n2743; + wire n2748; + wire n2753; + wire n2758; + wire n2763; + wire n2768; + wire n277; + wire n2773; + wire n2778; + wire n2783; + wire n2788; + wire n2793_1; + wire n2798_1; + wire n2803_1; + wire n2808_1; + wire n281; + wire n2813_1; + wire n2815; + wire n2816; + wire n2817; + wire n2818; + wire n2818_1; + wire n2819; + wire n2820; + wire n2821; + wire n2822; + wire n2823; + wire n2823_1; + wire n2824; + wire n2825; + wire n2826; + wire n2827; + wire n2828; + wire n2828_1; + wire n2829; + wire n2830; + wire n2831; + wire n2832; + wire n2833; + wire n2833_1; + wire n2834; + wire n2835; + wire n2836; + wire n2837; + wire n2838; + wire n2838_1; + wire n2839; + wire n2840; + wire n2841; + wire n2842; + wire n2843; + wire n2843_1; + wire n2844; + wire n2845; + wire n2846; + wire n2847; + wire n2848; + wire n2848_1; + wire n2849; + wire n285; + wire n2850; + wire n2851; + wire n2852; + wire n2853; + wire n2853_1; + wire n2854; + wire n2855; + wire n2856; + wire n2857; + wire n2858; + wire n2858_1; + wire n2859; + wire n2860; + wire n2861; + wire n2862; + wire n2863; + wire n2863_1; + wire n2864; + wire n2865; + wire n2866; + wire n2867; + wire n2868; + wire n2868_1; + wire n2869; + wire n2870; + wire n2871; + wire n2872; + wire n2873; + wire n2873_1; + wire n2874; + wire n2875; + wire n2876; + wire n2877; + wire n2878; + wire n2878_1; + wire n2879; + wire n2881; + wire n2882; + wire n2883; + wire n2883_1; + wire n2884; + wire n2885; + wire n2886; + wire n2887; + wire n2888; + wire n2888_1; + wire n2889; + wire n289; + wire n2890; + wire n2891; + wire n2892; + wire n2893; + wire n2893_1; + wire n2894; + wire n2895; + wire n2896; + wire n2897; + wire n2898; + wire n2898_1; + wire n2899; + wire n2900; + wire n2901; + wire n2903; + wire n2903_1; + wire n2904; + wire n2905; + wire n2906; + wire n2908; + wire n2908_1; + wire n2910; + wire n2911; + wire n2912; + wire n2913; + wire n2913_1; + wire n2914; + wire n2915; + wire n2916; + wire n2917; + wire n2918; + wire n2918_1; + wire n2919; + wire n2920; + wire n2922; + wire n2923; + wire n2923_1; + wire n2924; + wire n2925; + wire n2926; + wire n2927; + wire n2928; + wire n2928_1; + wire n2929; + wire n293; + wire n2930; + wire n2933; + wire n2934; + wire n2938; + wire n2938_1; + wire n2943; + wire n2943_1; + wire n2947; + wire n2948; + wire n2948_1; + wire n2950; + wire n2952; + wire n2953; + wire n2954; + wire n2958; + wire n2959; + wire n2960; + wire n2962; + wire n2963; + wire n2963_1; + wire n2964; + wire n2965; + wire n2966; + wire n2967; + wire n2968; + wire n2968_1; + wire n2969; + wire n297; + wire n2970; + wire n2971; + wire n2972; + wire n2973; + wire n2973_1; + wire n2974; + wire n2975; + wire n2976; + wire n2977; + wire n2978; + wire n2978_1; + wire n2979; + wire n2980; + wire n2981; + wire n2982; + wire n2983; + wire n2983_1; + wire n2984; + wire n2985; + wire n2986; + wire n2988; + wire n2988_1; + wire n2989; + wire n2990; + wire n2991; + wire n2992; + wire n2993; + wire n2993_1; + wire n2994; + wire n2995; + wire n2996; + wire n2997; + wire n2998; + wire n2998_1; + wire n2999; + wire n3000; + wire n3001; + wire n3002; + wire n3003; + wire n3003_1; + wire n3004; + wire n3005; + wire n3006; + wire n3007; + wire n3008; + wire n3008_1; + wire n3009; + wire n301; + wire n3010; + wire n3011; + wire n3012; + wire n3013; + wire n3013_1; + wire n3014; + wire n3015; + wire n3016; + wire n3017; + wire n3018; + wire n3018_1; + wire n3019; + wire n3020; + wire n3021; + wire n3022; + wire n3023; + wire n3023_1; + wire n3024; + wire n3025; + wire n3026; + wire n3027; + wire n3028; + wire n3028_1; + wire n3029; + wire n3030; + wire n3031; + wire n3032; + wire n3033; + wire n3033_1; + wire n3034; + wire n3035; + wire n3036; + wire n3037; + wire n3038; + wire n3038_1; + wire n3039; + wire n3040; + wire n3041; + wire n3042; + wire n3043; + wire n3043_1; + wire n3044; + wire n3045; + wire n3046; + wire n3047; + wire n3048; + wire n3048_1; + wire n3049; + wire n305; + wire n3050; + wire n3052; + wire n3053; + wire n3054; + wire n3056; + wire n3058; + wire n3058_1; + wire n3059; + wire n3060; + wire n3061; + wire n3062; + wire n3063; + wire n3063_1; + wire n3064; + wire n3065; + wire n3066; + wire n3067; + wire n3068; + wire n3068_1; + wire n3069; + wire n3070; + wire n3071; + wire n3073; + wire n3074; + wire n3075; + wire n3077; + wire n3078; + wire n3079; + wire n3081; + wire n3083; + wire n3085; + wire n3086; + wire n3087; + wire n3088; + wire n3088_1; + wire n3089; + wire n309; + wire n3090; + wire n3091; + wire n3092; + wire n3093; + wire n3093_1; + wire n3094; + wire n3095; + wire n3096; + wire n3097; + wire n3098; + wire n3098_1; + wire n3099; + wire n3100; + wire n3101; + wire n3102; + wire n3103; + wire n3103_1; + wire n3104; + wire n3105; + wire n3106; + wire n3107; + wire n3108; + wire n3108_1; + wire n3109; + wire n3110; + wire n3111; + wire n3112; + wire n3113; + wire n3113_1; + wire n3114; + wire n3115; + wire n3116; + wire n3117; + wire n3118; + wire n3118_1; + wire n3119; + wire n3120; + wire n3121; + wire n3122; + wire n3123; + wire n3123_1; + wire n3124; + wire n3125; + wire n3126; + wire n3127; + wire n3128; + wire n3128_1; + wire n3129; + wire n3130; + wire n3131; + wire n3132; + wire n3133; + wire n3133_1; + wire n3134; + wire n3135; + wire n3136; + wire n3137; + wire n3138; + wire n3139; + wire n313_1; + wire n3140; + wire n3141; + wire n3142; + wire n3143; + wire n3143_1; + wire n3144; + wire n3145; + wire n3146; + wire n3147; + wire n3148; + wire n3148_1; + wire n3149; + wire n3150; + wire n3151; + wire n3152; + wire n3153; + wire n3153_1; + wire n3154; + wire n3155; + wire n3156; + wire n3157; + wire n3158; + wire n3158_1; + wire n3160; + wire n3161; + wire n3162; + wire n3163_1; + wire n3164; + wire n3165; + wire n3166; + wire n3167; + wire n3168; + wire n3168_1; + wire n3169; + wire n317; + wire n3170; + wire n3171; + wire n3172; + wire n3173; + wire n3173_1; + wire n3174; + wire n3175; + wire n3176; + wire n3177; + wire n3178; + wire n3178_1; + wire n3179; + wire n3180; + wire n3181; + wire n3182; + wire n3183; + wire n3183_1; + wire n3184; + wire n3185; + wire n3186; + wire n3187; + wire n3188; + wire n3188_1; + wire n3189; + wire n3190; + wire n3192; + wire n3193_1; + wire n3194; + wire n3195; + wire n3196; + wire n3198; + wire n3198_1; + wire n3199; + wire n3201; + wire n3202; + wire n3203_1; + wire n3205; + wire n3206; + wire n3207; + wire n3208; + wire n3208_1; + wire n3209; + wire n321; + wire n3210; + wire n3212; + wire n3213_1; + wire n3214; + wire n3216; + wire n3217; + wire n3218; + wire n3218_1; + wire n3219; + wire n3220; + wire n3221; + wire n3223; + wire n3223_1; + wire n3224; + wire n3228_1; + wire n3233_1; + wire n3238_1; + wire n3243; + wire n3243_1; + wire n3248_1; + wire n325; + wire n3251; + wire n3252; + wire n3253_1; + wire n3258; + wire n3258_1; + wire n3262; + wire n3263_1; + wire n3264; + wire n3267; + wire n3268; + wire n3272; + wire n3273; + wire n3274; + wire n3276; + wire n3277; + wire n3278; + wire n3278_1; + wire n3280; + wire n3281; + wire n3282; + wire n3283; + wire n3283_1; + wire n3284; + wire n3286; + wire n3288; + wire n3288_1; + wire n3289; + wire n329; + wire n3290; + wire n3291; + wire n3292; + wire n3293; + wire n3293_1; + wire n3295; + wire n3296; + wire n3297; + wire n3298; + wire n3298_1; + wire n3299; + wire n3300; + wire n3302; + wire n3303; + wire n3303_1; + wire n3308; + wire n3313; + wire n3318; + wire n3323; + wire n3326; + wire n3328; + wire n3333; + wire n3338; + wire n3339; + wire n333_1; + wire n3342; + wire n3343; + wire n3343_1; + wire n3345; + wire n3347; + wire n3348; + wire n3348_1; + wire n3349; + wire n3350; + wire n3352; + wire n3353; + wire n3354; + wire n3355; + wire n3356; + wire n3357; + wire n3358; + wire n3358_1; + wire n3359; + wire n3360; + wire n3362; + wire n3363; + wire n3363_1; + wire n3364; + wire n3365; + wire n3366; + wire n3367; + wire n3368; + wire n3369; + wire n337; + wire n3370; + wire n3373; + wire n3378; + wire n3383; + wire n3388; + wire n3393_1; + wire n3398; + wire n3403; + wire n3404; + wire n3407; + wire n3408; + wire n3408_1; + wire n3409; + wire n341; + wire n3412; + wire n3413; + wire n3414; + wire n3415; + wire n3416; + wire n3417; + wire n3418; + wire n3418_1; + wire n3419; + wire n3421; + wire n3422; + wire n3423; + wire n3423_1; + wire n3424; + wire n3425; + wire n3426; + wire n3428; + wire n3428_1; + wire n3429; + wire n3433; + wire n3438; + wire n3443; + wire n3448; + wire n345; + wire n3453; + wire n3458; + wire n3463; + wire n3467; + wire n3468; + wire n3469; + wire n3470; + wire n3471; + wire n3472; + wire n3473; + wire n3473_1; + wire n3474; + wire n3476; + wire n3477; + wire n3478; + wire n3479; + wire n3480; + wire n3483; + wire n3488; + wire n349; + wire n3493; + wire n3498; + wire n3503; + wire n3508; + wire n3508_1; + wire n3509; + wire n3513; + wire n3514; + wire n3515; + wire n3518; + wire n3523; + wire n3523_1; + wire n3525; + wire n3526; + wire n3527; + wire n3528; + wire n3528_1; + wire n3529; + wire n3530; + wire n3532; + wire n3533; + wire n3533_1; + wire n3535; + wire n3536; + wire n3538; + wire n353_1; + wire n3543; + wire n3548; + wire n3553; + wire n3558; + wire n3562; + wire n3563; + wire n3568; + wire n357; + wire n3573; + wire n3577; + wire n3578; + wire n3578_1; + wire n3579; + wire n3580; + wire n3581; + wire n3582; + wire n3583; + wire n3584; + wire n3585; + wire n3586; + wire n3587; + wire n3588; + wire n3588_1; + wire n3589; + wire n3591; + wire n3592; + wire n3593; + wire n3594; + wire n3595; + wire n3598; + wire n3603; + wire n3608; + wire n361; + wire n3613; + wire n3618; + wire n3620; + wire n3623; + wire n3628; + wire n3633; + wire n3638; + wire n3640; + wire n3641; + wire n3643_1; + wire n3648_1; + wire n365; + wire n3653; + wire n3654; + wire n3658; + wire n3663; + wire n3668; + wire n3673; + wire n3677; + wire n3678; + wire n3683; + wire n3684; + wire n3688; + wire n369; + wire n3693; + wire n3696; + wire n3698; + wire n3700; + wire n3701; + wire n3703; + wire n3708; + wire n3713; + wire n3718; + wire n3723; + wire n3728; + wire n3733; + wire n3738; + wire n373_1; + wire n3743; + wire n3748; + wire n3753; + wire n3753_1; + wire n3758_1; + wire n3763_1; + wire n3768_1; + wire n377; + wire n3773; + wire n3778; + wire n3779; + wire n3780; + wire n3781; + wire n3783; + wire n3787; + wire n3788; + wire n3789; + wire n3790; + wire n3791; + wire n3792; + wire n3793; + wire n3794; + wire n3795; + wire n3798; + wire n3802; + wire n3803; + wire n3808; + wire n381; + wire n3810; + wire n3811; + wire n3812; + wire n3813; + wire n3813_1; + wire n3818; + wire n3819; + wire n3822; + wire n3823; + wire n3828; + wire n3833; + wire n3834; + wire n3838; + wire n3843; + wire n3847; + wire n3848; + wire n3849; + wire n385; + wire n3853; + wire n3858; + wire n3862; + wire n3863; + wire n3864; + wire n3868; + wire n3873; + wire n3877; + wire n3878; + wire n3878_1; + wire n3879; + wire n3880; + wire n3882; + wire n3883; + wire n3883_1; + wire n3884; + wire n3885; + wire n3886; + wire n3888_1; + wire n389; + wire n3893_1; + wire n3898_1; + wire n3903_1; + wire n3907; + wire n3908; + wire n3908_1; + wire n3909; + wire n3911; + wire n3913; + wire n3913_1; + wire n3914; + wire n3918_1; + wire n3923_1; + wire n3926; + wire n3928_1; + wire n3933_1; + wire n3936; + wire n3937; + wire n3938; + wire n3938_1; + wire n393_1; + wire n3940; + wire n3941; + wire n3942; + wire n3943; + wire n3943_1; + wire n3944; + wire n3946; + wire n3947; + wire n3948_1; + wire n3953_1; + wire n3958; + wire n3963; + wire n3968; + wire n397; + wire n3971; + wire n3972; + wire n3973; + wire n3973_1; + wire n3974; + wire n3976; + wire n3977; + wire n3978; + wire n3978_1; + wire n3979; + wire n3980; + wire n3982; + wire n3983; + wire n3983_1; + wire n3984; + wire n3985; + wire n3986; + wire n3987; + wire n3988; + wire n3989; + wire n3990; + wire n3993; + wire n3998; + wire n4003; + wire n4008; + wire n4009; + wire n401; + wire n4013; + wire n4016; + wire n4017; + wire n4018; + wire n4018_1; + wire n4019; + wire n4020; + wire n4021; + wire n4022; + wire n4023; + wire n4023_1; + wire n4025; + wire n4026; + wire n4027; + wire n4028; + wire n4028_1; + wire n4029; + wire n4031; + wire n4032; + wire n4033; + wire n4033_1; + wire n4034; + wire n4036; + wire n4037; + wire n4038; + wire n4043; + wire n4048; + wire n405; + wire n4053; + wire n4054; + wire n4058; + wire n4058_1; + wire n4059; + wire n4060; + wire n4061; + wire n4062; + wire n4063; + wire n4064; + wire n4065; + wire n4066; + wire n4067; + wire n4068; + wire n4068_1; + wire n4070; + wire n4071; + wire n4072; + wire n4073; + wire n4073_1; + wire n4074; + wire n4076; + wire n4078; + wire n4078_1; + wire n4079; + wire n4080; + wire n4081; + wire n4082; + wire n4083; + wire n4083_1; + wire n4084; + wire n4086; + wire n4087; + wire n4088; + wire n409; + wire n4093; + wire n4098; + wire n4098_1; + wire n4103; + wire n4107; + wire n4108; + wire n4108_1; + wire n4109; + wire n4111; + wire n4112; + wire n4113; + wire n4113_1; + wire n4114; + wire n4116; + wire n4117; + wire n4118; + wire n4118_1; + wire n4119; + wire n4120; + wire n4122; + wire n4123; + wire n4124; + wire n4126; + wire n4127; + wire n4128; + wire n4128_1; + wire n4129; + wire n4130; + wire n4131; + wire n4133; + wire n4138; + wire n413_1; + wire n4143; + wire n4147; + wire n4148; + wire n4148_1; + wire n4150; + wire n4151; + wire n4152; + wire n4153; + wire n4153_1; + wire n4154; + wire n4156; + wire n4157; + wire n4158; + wire n4158_1; + wire n4159; + wire n4160; + wire n4162; + wire n4163; + wire n4164; + wire n4165; + wire n4166; + wire n4167; + wire n4168; + wire n4168_1; + wire n417; + wire n4173; + wire n4178; + wire n4183; + wire n4185; + wire n4188; + wire n4193; + wire n4193_1; + wire n4194; + wire n4195; + wire n4196; + wire n4197; + wire n4198; + wire n4198_1; + wire n4199; + wire n4200; + wire n4201; + wire n4202; + wire n4203; + wire n4203_1; + wire n4204; + wire n4205; + wire n4206; + wire n4207; + wire n4208; + wire n4208_1; + wire n4209; + wire n421; + wire n4210; + wire n4211; + wire n4212; + wire n4213; + wire n4213_1; + wire n4214; + wire n4215; + wire n4216; + wire n4218; + wire n4218_1; + wire n4221; + wire n4222; + wire n4223; + wire n4223_1; + wire n4224; + wire n4225; + wire n4226; + wire n4228; + wire n4232; + wire n4233; + wire n4238; + wire n4243; + wire n4248; + wire n425; + wire n4253; + wire n4256; + wire n4257; + wire n4258; + wire n4258_1; + wire n4259; + wire n4260; + wire n4261; + wire n4263; + wire n4265; + wire n4266; + wire n4267; + wire n4268; + wire n4268_1; + wire n4269; + wire n4270; + wire n4273; + wire n4278; + wire n4278_1; + wire n4279; + wire n4280; + wire n4281; + wire n4282; + wire n4283; + wire n4283_1; + wire n4285; + wire n4286; + wire n4288; + wire n429; + wire n4291; + wire n4292; + wire n4293; + wire n4293_1; + wire n4294; + wire n4295; + wire n4296; + wire n4298; + wire n4302; + wire n4303; + wire n4303_1; + wire n4304; + wire n4305; + wire n4306; + wire n4307; + wire n4308; + wire n4310; + wire n4311; + wire n4312; + wire n4313; + wire n4313_1; + wire n4318; + wire n4321; + wire n4323; + wire n4323_1; + wire n4324; + wire n4325; + wire n4328_1; + wire n4331; + wire n4332; + wire n4333; + wire n4333_1; + wire n4334; + wire n4335; + wire n4336; + wire n4337; + wire n4338; + wire n4338_1; + wire n4339; + wire n433_1; + wire n4340; + wire n4343_1; + wire n4348_1; + wire n4353_1; + wire n4358_1; + wire n4363_1; + wire n4368; + wire n4368_1; + wire n4369; + wire n437; + wire n4370; + wire n4371; + wire n4372; + wire n4373; + wire n4373_1; + wire n4374; + wire n4378_1; + wire n4380; + wire n4381; + wire n4382; + wire n4383; + wire n4383_1; + wire n4384; + wire n4385; + wire n4386; + wire n4388; + wire n4391; + wire n4392; + wire n4393; + wire n4393_1; + wire n4394; + wire n4395; + wire n4396; + wire n4398; + wire n4400; + wire n4401; + wire n4402; + wire n4403; + wire n4403_1; + wire n4404; + wire n4405; + wire n4408; + wire n441; + wire n4410; + wire n4411; + wire n4412; + wire n4413; + wire n4413_1; + wire n4414; + wire n4415; + wire n4416; + wire n4418; + wire n4418_1; + wire n4419; + wire n4420; + wire n4421; + wire n4422; + wire n4423; + wire n4423_1; + wire n4426; + wire n4427; + wire n4428; + wire n4428_1; + wire n4429; + wire n4430; + wire n4431; + wire n4433; + wire n4437; + wire n4438; + wire n4438_1; + wire n4439; + wire n4440; + wire n4441; + wire n4442; + wire n4443; + wire n4444; + wire n4445; + wire n4446; + wire n4447; + wire n4448; + wire n4448_1; + wire n445; + wire n4450; + wire n4451; + wire n4453; + wire n4453_1; + wire n4454; + wire n4455; + wire n4456; + wire n4457; + wire n4458; + wire n4458_1; + wire n4459; + wire n4461; + wire n4463; + wire n4463_1; + wire n4467; + wire n4468; + wire n4468_1; + wire n4470; + wire n4471; + wire n4473; + wire n4477; + wire n4478; + wire n4478_1; + wire n4482; + wire n4483; + wire n4485; + wire n4486; + wire n4488; + wire n4488_1; + wire n4489; + wire n449; + wire n4491; + wire n4492; + wire n4493; + wire n4495; + wire n4496; + wire n4498; + wire n4498_1; + wire n4499; + wire n4501; + wire n4502; + wire n4503; + wire n4503_1; + wire n4504; + wire n4505; + wire n4506; + wire n4508; + wire n4508_1; + wire n4509; + wire n4510; + wire n4511; + wire n4513; + wire n4518_1; + wire n4523_1; + wire n4528_1; + wire n4533_1; + wire n4538; + wire n453_1; + wire n4543; + wire n4548; + wire n4553; + wire n4558; + wire n4563; + wire n4568; + wire n457; + wire n4573; + wire n4578; + wire n4583; + wire n4588; + wire n4593; + wire n4598_1; + wire n461; + wire n465; + wire n469; + wire n473_1; + wire n477; + wire n481; + wire n485; + wire n489; + wire n493_1; + wire n497; + wire n501; + wire n505; + wire n509; + wire n513_1; + wire n517_1; + wire n521_1; + wire n525; + wire n529; + wire n533; + wire n537; + wire n541; + wire n545; + wire n549_1; + wire n553; + wire n557; + wire n561; + wire n565; + wire n569_1; + wire n573; + wire n577; + wire n581; + wire n585; + wire n589_1; + wire n593; + wire n597; + wire n601; + wire n605; + wire n609_1; + wire n613; + wire n617; + wire n621; + wire n625; + wire n629_1; + wire n633; + wire n637; + wire n641; + wire n645; + wire n649_1; + wire n653; + wire n657; + wire n661; + wire n665; + wire n669_1; + wire n673; + wire n678; + wire n683; + wire n688; + wire n693; + wire n698; + wire n703; + wire n708; + wire n713; + wire n718; + wire n723; + wire n728; + wire n733; + wire n738; + wire n743_1; + wire n748; + wire n753; + wire n758; + wire n763; + wire n768; + wire n773; + wire n778; + wire n783; + wire n788; + wire n793; + wire n798; + wire n803; + wire n808; + wire n813; + wire n818; + wire n823; + wire n828; + wire n833; + wire n838; + wire n843; + wire n848; + wire n853; + wire n858; + wire n863; + wire n868; + wire n873; + wire n878; + wire n883; + wire n888; + wire n893; + wire n898; + wire n903; + wire n908; + wire n913; + wire n918; + wire n923; + wire n928; + wire n933; + wire n938; + wire n943; + wire n948; + wire n953; + wire n958; + wire n963; + wire n968_1; + wire n973; + wire n978; + wire n983; + wire n988; + wire n993; + wire n998; + (* init = 1'h0 *) + reg ndout = 1'h0; + (* init = 1'h0 *) + output paddress_0_0_; + reg paddress_0_0_ = 1'h0; + (* init = 1'h0 *) + output paddress_10_10_; + reg paddress_10_10_ = 1'h0; + (* init = 1'h0 *) + output paddress_11_11_; + reg paddress_11_11_ = 1'h0; + (* init = 1'h0 *) + output paddress_12_12_; + reg paddress_12_12_ = 1'h0; + (* init = 1'h0 *) + output paddress_13_13_; + reg paddress_13_13_ = 1'h0; + (* init = 1'h0 *) + output paddress_14_14_; + reg paddress_14_14_ = 1'h0; + (* init = 1'h0 *) + output paddress_15_15_; + reg paddress_15_15_ = 1'h0; + (* init = 1'h0 *) + output paddress_1_1_; + reg paddress_1_1_ = 1'h0; + (* init = 1'h0 *) + output paddress_2_2_; + reg paddress_2_2_ = 1'h0; + (* init = 1'h0 *) + output paddress_3_3_; + reg paddress_3_3_ = 1'h0; + (* init = 1'h0 *) + output paddress_4_4_; + reg paddress_4_4_ = 1'h0; + (* init = 1'h0 *) + output paddress_5_5_; + reg paddress_5_5_ = 1'h0; + (* init = 1'h0 *) + output paddress_6_6_; + reg paddress_6_6_ = 1'h0; + (* init = 1'h0 *) + output paddress_7_7_; + reg paddress_7_7_ = 1'h0; + (* init = 1'h0 *) + output paddress_8_8_; + reg paddress_8_8_ = 1'h0; + (* init = 1'h0 *) + output paddress_9_9_; + reg paddress_9_9_ = 1'h0; + input pclk; + output pdata_0_0_; + output pdata_10_10_; + output pdata_11_11_; + output pdata_12_12_; + output pdata_13_13_; + output pdata_14_14_; + output pdata_15_15_; + output pdata_1_1_; + output pdata_2_2_; + output pdata_3_3_; + output pdata_4_4_; + output pdata_5_5_; + output pdata_6_6_; + output pdata_7_7_; + output pdata_8_8_; + output pdata_9_9_; + (* init = 1'h0 *) + output pdn; + reg pdn = 1'h0; + (* init = 1'h0 *) + output piack_0_0_; + reg piack_0_0_ = 1'h0; + input pirq_0_0_; + (* init = 1'h0 *) + output ppeaka_0_0_; + reg ppeaka_0_0_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_10_10_; + reg ppeaka_10_10_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_11_11_; + reg ppeaka_11_11_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_12_12_; + reg ppeaka_12_12_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_13_13_; + reg ppeaka_13_13_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_14_14_; + reg ppeaka_14_14_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_15_15_; + reg ppeaka_15_15_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_1_1_; + reg ppeaka_1_1_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_2_2_; + reg ppeaka_2_2_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_3_3_; + reg ppeaka_3_3_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_4_4_; + reg ppeaka_4_4_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_5_5_; + reg ppeaka_5_5_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_6_6_; + reg ppeaka_6_6_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_7_7_; + reg ppeaka_7_7_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_8_8_; + reg ppeaka_8_8_ = 1'h0; + (* init = 1'h0 *) + output ppeaka_9_9_; + reg ppeaka_9_9_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_0_0_; + reg ppeakb_0_0_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_10_10_; + reg ppeakb_10_10_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_11_11_; + reg ppeakb_11_11_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_12_12_; + reg ppeakb_12_12_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_13_13_; + reg ppeakb_13_13_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_14_14_; + reg ppeakb_14_14_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_15_15_; + reg ppeakb_15_15_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_1_1_; + reg ppeakb_1_1_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_2_2_; + reg ppeakb_2_2_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_3_3_; + reg ppeakb_3_3_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_4_4_; + reg ppeakb_4_4_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_5_5_; + reg ppeakb_5_5_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_6_6_; + reg ppeakb_6_6_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_7_7_; + reg ppeakb_7_7_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_8_8_; + reg ppeakb_8_8_ = 1'h0; + (* init = 1'h0 *) + output ppeakb_9_9_; + reg ppeakb_9_9_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_0_0_; + reg ppeaki_0_0_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_10_10_; + reg ppeaki_10_10_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_11_11_; + reg ppeaki_11_11_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_12_12_; + reg ppeaki_12_12_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_13_13_; + reg ppeaki_13_13_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_14_14_; + reg ppeaki_14_14_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_15_15_; + reg ppeaki_15_15_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_1_1_; + reg ppeaki_1_1_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_2_2_; + reg ppeaki_2_2_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_3_3_; + reg ppeaki_3_3_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_4_4_; + reg ppeaki_4_4_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_5_5_; + reg ppeaki_5_5_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_6_6_; + reg ppeaki_6_6_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_7_7_; + reg ppeaki_7_7_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_8_8_; + reg ppeaki_8_8_ = 1'h0; + (* init = 1'h0 *) + output ppeaki_9_9_; + reg ppeaki_9_9_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_0_0_; + reg ppeakp_0_0_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_10_10_; + reg ppeakp_10_10_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_11_11_; + reg ppeakp_11_11_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_12_12_; + reg ppeakp_12_12_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_13_13_; + reg ppeakp_13_13_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_14_14_; + reg ppeakp_14_14_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_15_15_; + reg ppeakp_15_15_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_1_1_; + reg ppeakp_1_1_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_2_2_; + reg ppeakp_2_2_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_3_3_; + reg ppeakp_3_3_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_4_4_; + reg ppeakp_4_4_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_5_5_; + reg ppeakp_5_5_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_6_6_; + reg ppeakp_6_6_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_7_7_; + reg ppeakp_7_7_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_8_8_; + reg ppeakp_8_8_ = 1'h0; + (* init = 1'h0 *) + output ppeakp_9_9_; + reg ppeakp_9_9_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_0_0_; + reg ppeaks_0_0_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_10_10_; + reg ppeaks_10_10_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_11_11_; + reg ppeaks_11_11_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_12_12_; + reg ppeaks_12_12_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_13_13_; + reg ppeaks_13_13_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_14_14_; + reg ppeaks_14_14_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_15_15_; + reg ppeaks_15_15_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_1_1_; + reg ppeaks_1_1_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_2_2_; + reg ppeaks_2_2_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_3_3_; + reg ppeaks_3_3_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_4_4_; + reg ppeaks_4_4_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_5_5_; + reg ppeaks_5_5_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_6_6_; + reg ppeaks_6_6_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_7_7_; + reg ppeaks_7_7_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_8_8_; + reg ppeaks_8_8_ = 1'h0; + (* init = 1'h0 *) + output ppeaks_9_9_; + reg ppeaks_9_9_ = 1'h0; + (* init = 1'h0 *) + output prd_0_0_; + reg prd_0_0_ = 1'h0; + input preset; + input preset_0_0_; + (* init = 1'h0 *) + output pwr_0_0_; + reg pwr_0_0_ = 1'h0; + input tin_pdata_0_0_; + input tin_pdata_10_10_; + input tin_pdata_11_11_; + input tin_pdata_12_12_; + input tin_pdata_13_13_; + input tin_pdata_14_14_; + input tin_pdata_15_15_; + input tin_pdata_1_1_; + input tin_pdata_2_2_; + input tin_pdata_3_3_; + input tin_pdata_4_4_; + input tin_pdata_5_5_; + input tin_pdata_6_6_; + input tin_pdata_7_7_; + input tin_pdata_8_8_; + input tin_pdata_9_9_; + always @(posedge pclk) + ppeakb_7_7_ <= n273_1; + always @(posedge pclk) + ppeakb_10_10_ <= n309; + always @(posedge pclk) + paddress_0_0_ <= n669_1; + always @(posedge pclk) + ndout <= n673; + always @(posedge pclk) + \[4295] <= n678; + always @(posedge pclk) + \[4310] <= n683; + always @(posedge pclk) + \[4355] <= n688; + always @(posedge pclk) + \[4370] <= n693; + always @(posedge pclk) + \[4385] <= n698; + always @(posedge pclk) + \[4400] <= n703; + always @(posedge pclk) + \[4415] <= n708; + always @(posedge pclk) + \[4430] <= n713; + always @(posedge pclk) + ppeakb_8_8_ <= n313_1; + always @(posedge pclk) + \[4445] <= n718; + always @(posedge pclk) + \[4460] <= n723; + always @(posedge pclk) + \[4475] <= n728; + always @(posedge pclk) + \[4490] <= n733; + always @(posedge pclk) + \[4505] <= n738; + always @(posedge pclk) + \[4520] <= n743_1; + always @(posedge pclk) + \[4535] <= n748; + always @(posedge pclk) + \[4550] <= n753; + always @(posedge pclk) + \[4565] <= n758; + always @(posedge pclk) + \[4580] <= n763; + always @(posedge pclk) + ppeakp_1_1_ <= n317; + always @(posedge pclk) + \[4595] <= n768; + always @(posedge pclk) + \[4610] <= n773; + always @(posedge pclk) + \[4625] <= n778; + always @(posedge pclk) + \[4640] <= n783; + always @(posedge pclk) + \[4655] <= n788; + always @(posedge pclk) + \[4670] <= n793; + always @(posedge pclk) + \[4700] <= n798; + always @(posedge pclk) + \[4715] <= n803; + always @(posedge pclk) + \[4730] <= n808; + always @(posedge pclk) + \[4745] <= n813; + always @(posedge pclk) + ppeaka_14_14_ <= n321; + always @(posedge pclk) + \[4760] <= n818; + always @(posedge pclk) + \[4775] <= n823; + always @(posedge pclk) + \[4790] <= n828; + always @(posedge pclk) + \[4805] <= n833; + always @(posedge pclk) + \[4820] <= n838; + always @(posedge pclk) + \[4835] <= n843; + always @(posedge pclk) + \[4850] <= n848; + always @(posedge pclk) + \[4865] <= n853; + always @(posedge pclk) + \[4880] <= n858; + always @(posedge pclk) + \[4895] <= n863; + always @(posedge pclk) + ppeaka_10_10_ <= n325; + always @(posedge pclk) + \[4910] <= n868; + always @(posedge pclk) + \[4925] <= n873; + always @(posedge pclk) + \[4940] <= n878; + always @(posedge pclk) + \[4955] <= n883; + always @(posedge pclk) + \[4970] <= n888; + always @(posedge pclk) + \[5015] <= n893; + always @(posedge pclk) + \[5030] <= n898; + always @(posedge pclk) + \[5075] <= n903; + always @(posedge pclk) + \[5090] <= n908; + always @(posedge pclk) + \[5105] <= n913; + always @(posedge pclk) + ppeaka_8_8_ <= n329; + always @(posedge pclk) + \[5120] <= n918; + always @(posedge pclk) + \[5135] <= n923; + always @(posedge pclk) + \[5150] <= n928; + always @(posedge pclk) + \[5165] <= n933; + always @(posedge pclk) + \[5180] <= n938; + always @(posedge pclk) + \[5195] <= n943; + always @(posedge pclk) + \[5210] <= n948; + always @(posedge pclk) + \[5225] <= n953; + always @(posedge pclk) + \[5240] <= n958; + always @(posedge pclk) + \[5255] <= n963; + always @(posedge pclk) + ppeaki_4_4_ <= n333_1; + always @(posedge pclk) + \[5270] <= n968_1; + always @(posedge pclk) + \[5285] <= n973; + always @(posedge pclk) + \[5300] <= n978; + always @(posedge pclk) + \[5315] <= n983; + always @(posedge pclk) + \[5330] <= n988; + always @(posedge pclk) + \[5345] <= n993; + always @(posedge pclk) + \[5360] <= n998; + always @(posedge pclk) + \[5375] <= n1003; + always @(posedge pclk) + \[5390] <= n1008; + always @(posedge pclk) + \[5405] <= n1013; + always @(posedge pclk) + paddress_15_15_ <= n337; + always @(posedge pclk) + \[5420] <= n1018; + always @(posedge pclk) + \[5435] <= n1023; + always @(posedge pclk) + \[5450] <= n1028; + always @(posedge pclk) + \[5465] <= n1033; + always @(posedge pclk) + \[5480] <= n1038; + always @(posedge pclk) + \[5495] <= n1043; + always @(posedge pclk) + \[5510] <= n1048; + always @(posedge pclk) + \[5525] <= n1053; + always @(posedge pclk) + \[5540] <= n1058; + always @(posedge pclk) + \[5555] <= n1063; + always @(posedge pclk) + paddress_11_11_ <= n341; + always @(posedge pclk) + \[5570] <= n1068; + always @(posedge pclk) + \[5600] <= n1073; + always @(posedge pclk) + \[5615] <= n1078; + always @(posedge pclk) + \[5630] <= n1083; + always @(posedge pclk) + \[5645] <= n1088; + always @(posedge pclk) + \[5660] <= n1093; + always @(posedge pclk) + \[5675] <= n1098; + always @(posedge pclk) + \[5720] <= n1103; + always @(posedge pclk) + \[5780] <= n1108; + always @(posedge pclk) + \[5795] <= n1113; + always @(posedge pclk) + paddress_2_2_ <= n345; + always @(posedge pclk) + \[5810] <= n1118; + always @(posedge pclk) + \[5825] <= n1123; + always @(posedge pclk) + \[5840] <= n1128; + always @(posedge pclk) + \[5855] <= n1133; + always @(posedge pclk) + \[5870] <= n1138; + always @(posedge pclk) + \[5885] <= n1143; + always @(posedge pclk) + \[5900] <= n1148; + always @(posedge pclk) + \[5915] <= n1153; + always @(posedge pclk) + \[5930] <= n1158; + always @(posedge pclk) + \[5945] <= n1163; + always @(posedge pclk) + ppeakp_12_12_ <= n277; + always @(posedge pclk) + ppeakb_9_9_ <= n349; + always @(posedge pclk) + \[5960] <= n1168; + always @(posedge pclk) + \[5975] <= n1173; + always @(posedge pclk) + \[5990] <= n1178; + always @(posedge pclk) + \[6005] <= n1183_1; + always @(posedge pclk) + \[6020] <= n1188; + always @(posedge pclk) + \[6035] <= n1193; + always @(posedge pclk) + \[6050] <= n1198; + always @(posedge pclk) + \[6065] <= n1203; + always @(posedge pclk) + \[6080] <= n1208; + always @(posedge pclk) + \[6095] <= n1213; + always @(posedge pclk) + ppeakp_2_2_ <= n353_1; + always @(posedge pclk) + \[6110] <= n1218; + always @(posedge pclk) + \[6125] <= n1223; + always @(posedge pclk) + \[6140] <= n1228; + always @(posedge pclk) + \[6155] <= n1233; + always @(posedge pclk) + \[6170] <= n1238; + always @(posedge pclk) + \[6185] <= n1243; + always @(posedge pclk) + \[6200] <= n1248; + always @(posedge pclk) + \[6215] <= n1253; + always @(posedge pclk) + \[6230] <= n1258; + always @(posedge pclk) + \[6245] <= n1263; + always @(posedge pclk) + ppeaka_9_9_ <= n357; + always @(posedge pclk) + \[6260] <= n1268; + always @(posedge pclk) + \[6275] <= n1273; + always @(posedge pclk) + \[6290] <= n1278; + always @(posedge pclk) + \[6305] <= n1283; + always @(posedge pclk) + \[6320] <= n1288; + always @(posedge pclk) + \[6335] <= n1293; + always @(posedge pclk) + \[6350] <= n1298; + always @(posedge pclk) + \[6365] <= n1303; + always @(posedge pclk) + \[6410] <= n1308; + always @(posedge pclk) + \[6470] <= n1313; + always @(posedge pclk) + ppeaks_12_12_ <= n361; + always @(posedge pclk) + \[6485] <= n1318; + always @(posedge pclk) + \[6500] <= n1323; + always @(posedge pclk) + \[6515] <= n1328; + always @(posedge pclk) + \[6530] <= n1333; + always @(posedge pclk) + \[6545] <= n1338; + always @(posedge pclk) + \[6560] <= n1343; + always @(posedge pclk) + \[6575] <= n1348; + always @(posedge pclk) + \[6590] <= n1353; + always @(posedge pclk) + \[6605] <= n1358; + always @(posedge pclk) + \[6620] <= n1363; + always @(posedge pclk) + ppeaks_0_0_ <= n365; + always @(posedge pclk) + \[6635] <= n1368; + always @(posedge pclk) + \[6650] <= n1373; + always @(posedge pclk) + \[6665] <= n1378; + always @(posedge pclk) + \[6680] <= n1383; + always @(posedge pclk) + \[6695] <= n1388; + always @(posedge pclk) + \[6710] <= n1393_1; + always @(posedge pclk) + \[6725] <= n1398_1; + always @(posedge pclk) + \[6740] <= n1403_1; + always @(posedge pclk) + \[6755] <= n1408_1; + always @(posedge pclk) + \[6770] <= n1413_1; + always @(posedge pclk) + ppeaki_5_5_ <= n369; + always @(posedge pclk) + \[6785] <= n1418_1; + always @(posedge pclk) + \[6815] <= n1423_1; + always @(posedge pclk) + \[6830] <= n1428_1; + always @(posedge pclk) + \[6845] <= n1433_1; + always @(posedge pclk) + \[6860] <= n1438_1; + always @(posedge pclk) + \[6875] <= n1443_1; + always @(posedge pclk) + \[6890] <= n1448_1; + always @(posedge pclk) + \[6905] <= n1453_1; + always @(posedge pclk) + \[6920] <= n1458_1; + always @(posedge pclk) + \[6935] <= n1463_1; + always @(posedge pclk) + paddress_5_5_ <= n373_1; + always @(posedge pclk) + \[6950] <= n1468_1; + always @(posedge pclk) + \[6965] <= n1473_1; + always @(posedge pclk) + \[6980] <= n1478_1; + always @(posedge pclk) + \[6995] <= n1483_1; + always @(posedge pclk) + \[7010] <= n1488_1; + always @(posedge pclk) + \[7025] <= n1493_1; + always @(posedge pclk) + \[7055] <= n1498_1; + always @(posedge pclk) + \[7115] <= n1503_1; + always @(posedge pclk) + \[7130] <= n1508_1; + always @(posedge pclk) + \[7145] <= n1513_1; + always @(posedge pclk) + ppeakb_15_15_ <= n377; + always @(posedge pclk) + \[7160] <= n1518_1; + always @(posedge pclk) + \[7175] <= n1523_1; + always @(posedge pclk) + \[7190] <= n1528_1; + always @(posedge pclk) + \[7205] <= n1533_1; + always @(posedge pclk) + \[7220] <= n1538_1; + always @(posedge pclk) + \[7235] <= n1543_1; + always @(posedge pclk) + \[7250] <= n1548_1; + always @(posedge pclk) + \[7265] <= n1553_1; + always @(posedge pclk) + \[7280] <= n1558_1; + always @(posedge pclk) + \[7295] <= n1563_1; + always @(posedge pclk) + ppeakp_3_3_ <= n381; + always @(posedge pclk) + \[7310] <= n1568_1; + always @(posedge pclk) + \[7325] <= n1573_1; + always @(posedge pclk) + \[7340] <= n1578_1; + always @(posedge pclk) + \[7355] <= n1583_1; + always @(posedge pclk) + \[7370] <= n1588; + always @(posedge pclk) + \[7385] <= n1593; + always @(posedge pclk) + \[7400] <= n1598; + always @(posedge pclk) + \[7415] <= n1603; + always @(posedge pclk) + \[7430] <= n1608; + always @(posedge pclk) + \[7445] <= n1613; + always @(posedge pclk) + pwr_0_0_ <= n385; + always @(posedge pclk) + \[7460] <= n1618; + always @(posedge pclk) + \[7475] <= n1623; + always @(posedge pclk) + \[7490] <= n1628; + always @(posedge pclk) + \[7505] <= n1633; + always @(posedge pclk) + \[7520] <= n1638; + always @(posedge pclk) + \[7535] <= n1643; + always @(posedge pclk) + \[7550] <= n1648; + always @(posedge pclk) + \[7565] <= n1653; + always @(posedge pclk) + \[7580] <= n1658; + always @(posedge pclk) + \[7595] <= n1663; + always @(posedge pclk) + ppeakp_0_0_ <= n281; + always @(posedge pclk) + ppeaks_1_1_ <= n389; + always @(posedge pclk) + \[7625] <= n1668; + always @(posedge pclk) + \[7640] <= n1673; + always @(posedge pclk) + \[7655] <= n1678; + always @(posedge pclk) + \[7670] <= n1683; + always @(posedge pclk) + \[7685] <= n1688; + always @(posedge pclk) + \[7745] <= n1693; + always @(posedge pclk) + \[7760] <= n1698; + always @(posedge pclk) + \[7775] <= n1703; + always @(posedge pclk) + \[7790] <= n1708; + always @(posedge pclk) + \[7805] <= n1713; + always @(posedge pclk) + ppeaki_6_6_ <= n393_1; + always @(posedge pclk) + \[7820] <= n1718; + always @(posedge pclk) + \[7835] <= n1723; + always @(posedge pclk) + \[7850] <= n1728; + always @(posedge pclk) + \[7865] <= n1733; + always @(posedge pclk) + \[7880] <= n1738; + always @(posedge pclk) + \[7895] <= n1743; + always @(posedge pclk) + \[7910] <= n1748; + always @(posedge pclk) + \[7925] <= n1753; + always @(posedge pclk) + \[7940] <= n1758; + always @(posedge pclk) + \[7955] <= n1763; + always @(posedge pclk) + paddress_4_4_ <= n397; + always @(posedge pclk) + \[7970] <= n1768; + always @(posedge pclk) + \[8000] <= n1773; + always @(posedge pclk) + \[8015] <= n1778; + always @(posedge pclk) + \[8030] <= n1783; + always @(posedge pclk) + \[8045] <= n1788; + always @(posedge pclk) + \[8060] <= n1793; + always @(posedge pclk) + \[8075] <= n1798_1; + always @(posedge pclk) + \[8090] <= n1803; + always @(posedge pclk) + \[8105] <= n1808; + always @(posedge pclk) + \[8120] <= n1813; + always @(posedge pclk) + piack_0_0_ <= n401; + always @(posedge pclk) + \[8135] <= n1818; + always @(posedge pclk) + \[8150] <= n1823; + always @(posedge pclk) + \[8165] <= n1828; + always @(posedge pclk) + \[8180] <= n1833; + always @(posedge pclk) + \[8195] <= n1838; + always @(posedge pclk) + \[8210] <= n1843; + always @(posedge pclk) + \[8225] <= n1848; + always @(posedge pclk) + \[8240] <= n1853; + always @(posedge pclk) + \[8255] <= n1858; + always @(posedge pclk) + \[8285] <= n1863; + always @(posedge pclk) + ppeakp_13_13_ <= n405; + always @(posedge pclk) + \[8300] <= n1868; + always @(posedge pclk) + \[8315] <= n1873; + always @(posedge pclk) + \[8330] <= n1878; + always @(posedge pclk) + \[8390] <= n1883; + always @(posedge pclk) + \[8405] <= n1888; + always @(posedge pclk) + \[8420] <= n1893; + always @(posedge pclk) + \[8435] <= n1898; + always @(posedge pclk) + \[8450] <= n1903; + always @(posedge pclk) + \[8465] <= n1908; + always @(posedge pclk) + \[8480] <= n1913; + always @(posedge pclk) + ppeakp_4_4_ <= n409; + always @(posedge pclk) + \[8495] <= n1918; + always @(posedge pclk) + \[8510] <= n1923; + always @(posedge pclk) + \[8525] <= n1928; + always @(posedge pclk) + \[8540] <= n1933; + always @(posedge pclk) + \[8555] <= n1938; + always @(posedge pclk) + \[8570] <= n1943; + always @(posedge pclk) + \[8585] <= n1948; + always @(posedge pclk) + \[8600] <= n1953; + always @(posedge pclk) + \[8615] <= n1958; + always @(posedge pclk) + \[8630] <= n1963; + always @(posedge pclk) + ppeaka_15_15_ <= n413_1; + always @(posedge pclk) + \[8645] <= n1968; + always @(posedge pclk) + \[8660] <= n1973; + always @(posedge pclk) + \[8675] <= n1978; + always @(posedge pclk) + \[8690] <= n1983; + always @(posedge pclk) + \[8705] <= n1988; + always @(posedge pclk) + \[8720] <= n1993; + always @(posedge pclk) + \[8735] <= n1998; + always @(posedge pclk) + \[8750] <= n2003; + always @(posedge pclk) + \[8765] <= n2008; + always @(posedge pclk) + \[8780] <= n2013; + always @(posedge pclk) + ppeaka_11_11_ <= n417; + always @(posedge pclk) + \[8810] <= n2018; + always @(posedge pclk) + \[8825] <= n2023; + always @(posedge pclk) + \[8840] <= n2028; + always @(posedge pclk) + \[8855] <= n2033; + always @(posedge pclk) + \[8870] <= n2038; + always @(posedge pclk) + \[8885] <= n2043; + always @(posedge pclk) + \[8900] <= n2048; + always @(posedge pclk) + \[8915] <= n2053; + always @(posedge pclk) + \[8930] <= n2058; + always @(posedge pclk) + \[8945] <= n2063; + always @(posedge pclk) + ppeaks_2_2_ <= n421; + always @(posedge pclk) + \[8960] <= n2068; + always @(posedge pclk) + \[8975] <= n2073; + always @(posedge pclk) + \[9050] <= n2078; + always @(posedge pclk) + \[9065] <= n2083; + always @(posedge pclk) + \[9080] <= n2088; + always @(posedge pclk) + \[9095] <= n2093; + always @(posedge pclk) + \[9110] <= n2098; + always @(posedge pclk) + \[9125] <= n2103; + always @(posedge pclk) + \[9140] <= n2108; + always @(posedge pclk) + \[9155] <= n2113; + always @(posedge pclk) + ppeaki_7_7_ <= n425; + always @(posedge pclk) + \[9170] <= n2118; + always @(posedge pclk) + \[9185] <= n2123; + always @(posedge pclk) + \[9200] <= n2128; + always @(posedge pclk) + \[9215] <= n2133; + always @(posedge pclk) + \[9230] <= n2138; + always @(posedge pclk) + \[9245] <= n2143; + always @(posedge pclk) + \[9260] <= n2148; + always @(posedge pclk) + \[9275] <= n2153; + always @(posedge pclk) + \[9290] <= n2158; + always @(posedge pclk) + \[9305] <= n2163; + always @(posedge pclk) + ppeaka_7_7_ <= n285; + always @(posedge pclk) + paddress_10_10_ <= n429; + always @(posedge pclk) + \[9320] <= n2168; + always @(posedge pclk) + \[9335] <= n2173; + always @(posedge pclk) + \[9350] <= n2178; + always @(posedge pclk) + \[9365] <= n2183; + always @(posedge pclk) + \[9380] <= n2188_1; + always @(posedge pclk) + \[9395] <= n2193_1; + always @(posedge pclk) + \[9410] <= n2198_1; + always @(posedge pclk) + \[9440] <= n2203_1; + always @(posedge pclk) + \[9455] <= n2208_1; + always @(posedge pclk) + \[9470] <= n2213_1; + always @(posedge pclk) + paddress_7_7_ <= n433_1; + always @(posedge pclk) + \[9485] <= n2218_1; + always @(posedge pclk) + \[9500] <= n2223_1; + always @(posedge pclk) + \[9515] <= n2228_1; + always @(posedge pclk) + \[9530] <= n2233_1; + always @(posedge pclk) + \[9545] <= n2238_1; + always @(posedge pclk) + \[9560] <= n2243_1; + always @(posedge pclk) + \[9575] <= n2248_1; + always @(posedge pclk) + \[9590] <= n2253_1; + always @(posedge pclk) + \[9605] <= n2258_1; + always @(posedge pclk) + \[9620] <= n2263_1; + always @(posedge pclk) + ppeakp_5_5_ <= n437; + always @(posedge pclk) + \[9635] <= n2268; + always @(posedge pclk) + \[9650] <= n2273; + always @(posedge pclk) + \[9665] <= n2278; + always @(posedge pclk) + \[9680] <= n2283; + always @(posedge pclk) + \[9710] <= n2288; + always @(posedge pclk) + \[9725] <= n2293; + always @(posedge pclk) + \[9740] <= n2298; + always @(posedge pclk) + \[9770] <= n2303; + always @(posedge pclk) + \[9785] <= n2308; + always @(posedge pclk) + \[9800] <= n2313; + always @(posedge pclk) + ppeaks_13_13_ <= n441; + always @(posedge pclk) + \[9815] <= n2318; + always @(posedge pclk) + \[9830] <= n2323; + always @(posedge pclk) + \[9845] <= n2328; + always @(posedge pclk) + \[9860] <= n2333; + always @(posedge pclk) + \[9875] <= n2338; + always @(posedge pclk) + \[9890] <= n2343; + always @(posedge pclk) + \[9905] <= n2348; + always @(posedge pclk) + \[9920] <= n2353; + always @(posedge pclk) + \[9935] <= n2358; + always @(posedge pclk) + \[9950] <= n2363; + always @(posedge pclk) + ppeaks_3_3_ <= n445; + always @(posedge pclk) + \[9980] <= n2368; + always @(posedge pclk) + \[9995] <= n2373; + always @(posedge pclk) + \[10010] <= n2378; + always @(posedge pclk) + \[10025] <= n2383; + always @(posedge pclk) + \[10040] <= n2388; + always @(posedge pclk) + \[10055] <= n2393; + always @(posedge pclk) + \[10070] <= n2398; + always @(posedge pclk) + \[10085] <= n2403; + always @(posedge pclk) + \[10100] <= n2408; + always @(posedge pclk) + \[10115] <= n2413; + always @(posedge pclk) + ppeaki_14_14_ <= n449; + always @(posedge pclk) + \[10130] <= n2418; + always @(posedge pclk) + \[10145] <= n2423; + always @(posedge pclk) + \[10175] <= n2428; + always @(posedge pclk) + \[10190] <= n2433; + always @(posedge pclk) + \[10205] <= n2438; + always @(posedge pclk) + \[10220] <= n2443; + always @(posedge pclk) + \[10265] <= n2448; + always @(posedge pclk) + \[10280] <= n2453; + always @(posedge pclk) + \[10310] <= n2458; + always @(posedge pclk) + \[10325] <= n2463; + always @(posedge pclk) + ppeaki_10_10_ <= n453_1; + always @(posedge pclk) + \[10340] <= n2468; + always @(posedge pclk) + \[10355] <= n2473; + always @(posedge pclk) + \[10370] <= n2478; + always @(posedge pclk) + \[10400] <= n2483; + always @(posedge pclk) + \[10415] <= n2488; + always @(posedge pclk) + \[10430] <= n2493; + always @(posedge pclk) + \[10445] <= n2498; + always @(posedge pclk) + \[10460] <= n2503; + always @(posedge pclk) + \[10475] <= n2508; + always @(posedge pclk) + \[10490] <= n2513; + always @(posedge pclk) + ppeaki_8_8_ <= n457; + always @(posedge pclk) + \[10505] <= n2518; + always @(posedge pclk) + \[10550] <= n2523; + always @(posedge pclk) + \[10565] <= n2528; + always @(posedge pclk) + \[10580] <= n2533; + always @(posedge pclk) + \[10595] <= n2538; + always @(posedge pclk) + \[10610] <= n2543; + always @(posedge pclk) + \[10625] <= n2548; + always @(posedge pclk) + \[10655] <= n2553; + always @(posedge pclk) + \[10670] <= n2558; + always @(posedge pclk) + \[10685] <= n2563; + always @(posedge pclk) + paddress_6_6_ <= n461; + always @(posedge pclk) + \[10700] <= n2568; + always @(posedge pclk) + \[10715] <= n2573; + always @(posedge pclk) + \[10730] <= n2578; + always @(posedge pclk) + \[10745] <= n2583; + always @(posedge pclk) + \[10760] <= n2588; + always @(posedge pclk) + \[10775] <= n2593; + always @(posedge pclk) + \[10790] <= n2598; + always @(posedge pclk) + \[10805] <= n2603; + always @(posedge pclk) + \[10820] <= n2608; + always @(posedge pclk) + \[10850] <= n2613; + always @(posedge pclk) + ppeakp_6_6_ <= n465; + always @(posedge pclk) + \[10865] <= n2618; + always @(posedge pclk) + \[10880] <= n2623; + always @(posedge pclk) + \[10895] <= n2628; + always @(posedge pclk) + \[10925] <= n2633; + always @(posedge pclk) + \[10940] <= n2638; + always @(posedge pclk) + \[10955] <= n2643; + always @(posedge pclk) + \[10970] <= n2648; + always @(posedge pclk) + \[10985] <= n2653; + always @(posedge pclk) + \[11015] <= n2658; + always @(posedge pclk) + \[11030] <= n2663; + always @(posedge pclk) + ppeaki_15_15_ <= n289; + always @(posedge pclk) + ppeaks_4_4_ <= n469; + always @(posedge pclk) + \[11045] <= n2668; + always @(posedge pclk) + \[11060] <= n2673; + always @(posedge pclk) + \[11075] <= n2678; + always @(posedge pclk) + \[11090] <= n2683; + always @(posedge pclk) + \[11120] <= n2688; + always @(posedge pclk) + \[11135] <= n2693; + always @(posedge pclk) + \[11150] <= n2698_1; + always @(posedge pclk) + \[11165] <= n2703; + always @(posedge pclk) + \[11180] <= n2708; + always @(posedge pclk) + \[11195] <= n2713; + always @(posedge pclk) + ppeaki_9_9_ <= n473_1; + always @(posedge pclk) + \[11210] <= n2718; + always @(posedge pclk) + \[11225] <= n2723; + always @(posedge pclk) + \[11240] <= n2728; + always @(posedge pclk) + \[11255] <= n2733; + always @(posedge pclk) + \[11270] <= n2738; + always @(posedge pclk) + \[11285] <= n2743; + always @(posedge pclk) + \[11300] <= n2748; + always @(posedge pclk) + \[11315] <= n2753; + always @(posedge pclk) + \[11330] <= n2758; + always @(posedge pclk) + \[11345] <= n2763; + always @(posedge pclk) + paddress_9_9_ <= n477; + always @(posedge pclk) + \[11375] <= n2768; + always @(posedge pclk) + \[11390] <= n2773; + always @(posedge pclk) + \[11405] <= n2778; + always @(posedge pclk) + \[11420] <= n2783; + always @(posedge pclk) + \[11435] <= n2788; + always @(posedge pclk) + \[11450] <= n2793_1; + always @(posedge pclk) + \[11465] <= n2798_1; + always @(posedge pclk) + \[11480] <= n2803_1; + always @(posedge pclk) + \[11495] <= n2808_1; + always @(posedge pclk) + \[11510] <= n2813_1; + always @(posedge pclk) + ppeakb_11_11_ <= n481; + always @(posedge pclk) + \[11525] <= n2818_1; + always @(posedge pclk) + \[11540] <= n2823_1; + always @(posedge pclk) + \[11555] <= n2828_1; + always @(posedge pclk) + \[11570] <= n2833_1; + always @(posedge pclk) + \[11585] <= n2838_1; + always @(posedge pclk) + \[11600] <= n2843_1; + always @(posedge pclk) + \[11615] <= n2848_1; + always @(posedge pclk) + \[11630] <= n2853; + always @(posedge pclk) + \[11645] <= n2858; + always @(posedge pclk) + \[11660] <= n2863; + always @(posedge pclk) + ppeakp_7_7_ <= n485; + always @(posedge pclk) + \[11675] <= n2868; + always @(posedge pclk) + \[11690] <= n2873; + always @(posedge pclk) + \[11705] <= n2878; + always @(posedge pclk) + \[11720] <= n2883; + always @(posedge pclk) + \[11735] <= n2888; + always @(posedge pclk) + \[11750] <= n2893; + always @(posedge pclk) + \[11765] <= n2898; + always @(posedge pclk) + \[11780] <= n2903; + always @(posedge pclk) + \[11795] <= n2908; + always @(posedge pclk) + \[11810] <= n2913; + always @(posedge pclk) + ppeaks_5_5_ <= n489; + always @(posedge pclk) + \[11885] <= n2918; + always @(posedge pclk) + \[11900] <= n2923; + always @(posedge pclk) + \[11915] <= n2928; + always @(posedge pclk) + \[11930] <= n2933; + always @(posedge pclk) + \[12005] <= n2938; + always @(posedge pclk) + \[12020] <= n2943; + always @(posedge pclk) + \[12035] <= n2948; + always @(posedge pclk) + \[12050] <= n2953; + always @(posedge pclk) + \[12065] <= n2958; + always @(posedge pclk) + \[12080] <= n2963; + always @(posedge pclk) + paddress_13_13_ <= n493_1; + always @(posedge pclk) + \[12125] <= n2968; + always @(posedge pclk) + \[12140] <= n2973; + always @(posedge pclk) + \[12155] <= n2978_1; + always @(posedge pclk) + \[12170] <= n2983; + always @(posedge pclk) + \[12185] <= n2988; + always @(posedge pclk) + \[12200] <= n2993; + always @(posedge pclk) + \[12245] <= n2998; + always @(posedge pclk) + \[12260] <= n3003; + always @(posedge pclk) + \[12275] <= n3008; + always @(posedge pclk) + \[12335] <= n3013; + always @(posedge pclk) + paddress_8_8_ <= n497; + always @(posedge pclk) + \[12350] <= n3018; + always @(posedge pclk) + \[12365] <= n3023; + always @(posedge pclk) + \[12380] <= n3028; + always @(posedge pclk) + \[12395] <= n3033; + always @(posedge pclk) + \[12410] <= n3038; + always @(posedge pclk) + \[12425] <= n3043; + always @(posedge pclk) + \[12440] <= n3048; + always @(posedge pclk) + \[12455] <= n3053; + always @(posedge pclk) + \[12470] <= n3058; + always @(posedge pclk) + \[12485] <= n3063; + always @(posedge pclk) + ppeakp_14_14_ <= n501; + always @(posedge pclk) + \[12545] <= n3068; + always @(posedge pclk) + \[12560] <= n3073; + always @(posedge pclk) + \[12575] <= n3078; + always @(posedge pclk) + \[12590] <= n3083; + always @(posedge pclk) + \[12605] <= n3088; + always @(posedge pclk) + \[12620] <= n3093; + always @(posedge pclk) + \[12635] <= n3098; + always @(posedge pclk) + \[12650] <= n3103; + always @(posedge pclk) + \[12665] <= n3108; + always @(posedge pclk) + \[12680] <= n3113; + always @(posedge pclk) + ppeakp_10_10_ <= n505; + always @(posedge pclk) + \[12695] <= n3118; + always @(posedge pclk) + \[12770] <= n3123; + always @(posedge pclk) + \[12800] <= n3128; + always @(posedge pclk) + \[12815] <= n3133; + always @(posedge pclk) + \[12830] <= n3138; + always @(posedge pclk) + \[12845] <= n3143; + always @(posedge pclk) + \[12860] <= n3148; + always @(posedge pclk) + \[12875] <= n3153; + always @(posedge pclk) + \[12890] <= n3158_1; + always @(posedge pclk) + \[12905] <= n3163_1; + always @(posedge pclk) + ppeaki_11_11_ <= n293; + always @(posedge pclk) + ppeakp_8_8_ <= n509; + always @(posedge pclk) + \[12920] <= n3168_1; + always @(posedge pclk) + \[12935] <= n3173_1; + always @(posedge pclk) + \[13010] <= n3178_1; + always @(posedge pclk) + \[13025] <= n3183_1; + always @(posedge pclk) + \[13040] <= n3188_1; + always @(posedge pclk) + \[13055] <= n3193_1; + always @(posedge pclk) + \[13070] <= n3198_1; + always @(posedge pclk) + \[13085] <= n3203_1; + always @(posedge pclk) + \[13100] <= n3208_1; + always @(posedge pclk) + \[13115] <= n3213_1; + always @(posedge pclk) + ppeaks_6_6_ <= n513_1; + always @(posedge pclk) + \[13130] <= n3218_1; + always @(posedge pclk) + \[13160] <= n3223_1; + always @(posedge pclk) + \[13175] <= n3228_1; + always @(posedge pclk) + \[13220] <= n3233_1; + always @(posedge pclk) + \[13235] <= n3238_1; + always @(posedge pclk) + \[13250] <= n3243_1; + always @(posedge pclk) + \[13265] <= n3248_1; + always @(posedge pclk) + \[13280] <= n3253_1; + always @(posedge pclk) + \[13295] <= n3258_1; + always @(posedge pclk) + \[13310] <= n3263_1; + always @(posedge pclk) + ppeaki_13_13_ <= n517_1; + always @(posedge pclk) + \[13325] <= n3268; + always @(posedge pclk) + \[13340] <= n3273; + always @(posedge pclk) + \[13355] <= n3278; + always @(posedge pclk) + \[13370] <= n3283; + always @(posedge pclk) + \[13385] <= n3288; + always @(posedge pclk) + \[13400] <= n3293; + always @(posedge pclk) + \[13415] <= n3298; + always @(posedge pclk) + \[13430] <= n3303; + always @(posedge pclk) + \[13445] <= n3308; + always @(posedge pclk) + \[13460] <= n3313; + always @(posedge pclk) + ppeakb_0_0_ <= n521_1; + always @(posedge pclk) + \[13475] <= n3318; + always @(posedge pclk) + \[13490] <= n3323; + always @(posedge pclk) + \[13505] <= n3328; + always @(posedge pclk) + \[13550] <= n3333; + always @(posedge pclk) + \[13580] <= n3338; + always @(posedge pclk) + \[13595] <= n3343; + always @(posedge pclk) + \[13610] <= n3348; + always @(posedge pclk) + \[13625] <= n3353; + always @(posedge pclk) + \[13640] <= n3358; + always @(posedge pclk) + \[13655] <= n3363; + always @(posedge pclk) + ppeakp_9_9_ <= n525; + always @(posedge pclk) + \[13670] <= n3368; + always @(posedge pclk) + \[13685] <= n3373; + always @(posedge pclk) + \[13700] <= n3378; + always @(posedge pclk) + \[13715] <= n3383; + always @(posedge pclk) + \[13730] <= n3388; + always @(posedge pclk) + \[13745] <= n3393_1; + always @(posedge pclk) + \[13775] <= n3398; + always @(posedge pclk) + \[13790] <= n3403; + always @(posedge pclk) + \[13805] <= n3408; + always @(posedge pclk) + \[13820] <= n3413; + always @(posedge pclk) + ppeaka_0_0_ <= n529; + always @(posedge pclk) + \[13835] <= n3418; + always @(posedge pclk) + \[13850] <= n3423; + always @(posedge pclk) + \[13865] <= n3428; + always @(posedge pclk) + \[13880] <= n3433; + always @(posedge pclk) + \[13895] <= n3438; + always @(posedge pclk) + \[13955] <= n3443; + always @(posedge pclk) + \[13970] <= n3448; + always @(posedge pclk) + \[13985] <= n3453; + always @(posedge pclk) + \[14000] <= n3458; + always @(posedge pclk) + \[14015] <= n3463; + always @(posedge pclk) + ppeaks_7_7_ <= n533; + always @(posedge pclk) + \[14030] <= n3468; + always @(posedge pclk) + \[14045] <= n3473; + always @(posedge pclk) + \[14060] <= n3478; + always @(posedge pclk) + \[14075] <= n3483; + always @(posedge pclk) + \[14090] <= n3488; + always @(posedge pclk) + \[14105] <= n3493; + always @(posedge pclk) + \[14120] <= n3498; + always @(posedge pclk) + \[14135] <= n3503; + always @(posedge pclk) + \[14150] <= n3508; + always @(posedge pclk) + \[14165] <= n3513; + always @(posedge pclk) + ppeakb_1_1_ <= n537; + always @(posedge pclk) + \[14180] <= n3518; + always @(posedge pclk) + \[14210] <= n3523; + always @(posedge pclk) + \[14225] <= n3528_1; + always @(posedge pclk) + \[14240] <= n3533_1; + always @(posedge pclk) + \[14255] <= n3538; + always @(posedge pclk) + \[14270] <= n3543; + always @(posedge pclk) + \[14285] <= n3548; + always @(posedge pclk) + \[14360] <= n3553; + always @(posedge pclk) + \[14375] <= n3558; + always @(posedge pclk) + \[14390] <= n3563; + always @(posedge pclk) + ppeaka_1_1_ <= n541; + always @(posedge pclk) + \[14405] <= n3568; + always @(posedge pclk) + \[14420] <= n3573; + always @(posedge pclk) + \[14435] <= n3578; + always @(posedge pclk) + \[14450] <= n3583; + always @(posedge pclk) + \[14465] <= n3588; + always @(posedge pclk) + \[14480] <= n3593; + always @(posedge pclk) + \[14495] <= n3598; + always @(posedge pclk) + \[14510] <= n3603; + always @(posedge pclk) + \[14525] <= n3608; + always @(posedge pclk) + \[14540] <= n3613; + always @(posedge pclk) + ppeaks_10_10_ <= n545; + always @(posedge pclk) + \[14555] <= n3618; + always @(posedge pclk) + \[14570] <= n3623; + always @(posedge pclk) + \[14585] <= n3628; + always @(posedge pclk) + \[14600] <= n3633; + always @(posedge pclk) + \[14615] <= n3638; + always @(posedge pclk) + \[14630] <= n3643_1; + always @(posedge pclk) + \[14660] <= n3648_1; + always @(posedge pclk) + \[14675] <= n3653; + always @(posedge pclk) + \[14690] <= n3658; + always @(posedge pclk) + \[14705] <= n3663; + always @(posedge pclk) + ppeaki_3_3_ <= n297; + always @(posedge pclk) + ppeaks_8_8_ <= n549_1; + always @(posedge pclk) + \[14765] <= n3668; + always @(posedge pclk) + \[14810] <= n3673; + always @(posedge pclk) + \[14825] <= n3678; + always @(posedge pclk) + \[14840] <= n3683; + always @(posedge pclk) + \[14855] <= n3688; + always @(posedge pclk) + \[14870] <= n3693; + always @(posedge pclk) + \[14885] <= n3698; + always @(posedge pclk) + \[14900] <= n3703; + always @(posedge pclk) + \[14915] <= n3708; + always @(posedge pclk) + \[14930] <= n3713; + always @(posedge pclk) + ppeakb_12_12_ <= n553; + always @(posedge pclk) + \[14960] <= n3718; + always @(posedge pclk) + \[14975] <= n3723; + always @(posedge pclk) + \[14990] <= n3728; + always @(posedge pclk) + \[15005] <= n3733; + always @(posedge pclk) + \[15020] <= n3738; + always @(posedge pclk) + \[15035] <= n3743; + always @(posedge pclk) + \[15050] <= n3748; + always @(posedge pclk) + \[15065] <= n3753; + always @(posedge pclk) + \[15080] <= n3758_1; + always @(posedge pclk) + \[15140] <= n3763_1; + always @(posedge pclk) + ppeakb_2_2_ <= n557; + always @(posedge pclk) + \[15185] <= n3768_1; + always @(posedge pclk) + \[15200] <= n3773; + always @(posedge pclk) + \[15215] <= n3778; + always @(posedge pclk) + \[15230] <= n3783; + always @(posedge pclk) + \[15245] <= n3788; + always @(posedge pclk) + \[15260] <= n3793; + always @(posedge pclk) + \[15275] <= n3798; + always @(posedge pclk) + \[15290] <= n3803; + always @(posedge pclk) + \[15305] <= n3808; + always @(posedge pclk) + \[15320] <= n3813; + always @(posedge pclk) + ppeaka_12_12_ <= n561; + always @(posedge pclk) + \[15335] <= n3818; + always @(posedge pclk) + \[15350] <= n3823; + always @(posedge pclk) + \[15365] <= n3828; + always @(posedge pclk) + \[15380] <= n3833; + always @(posedge pclk) + \[15395] <= n3838; + always @(posedge pclk) + \[15410] <= n3843; + always @(posedge pclk) + \[15425] <= n3848; + always @(posedge pclk) + \[15440] <= n3853; + always @(posedge pclk) + \[15500] <= n3858; + always @(posedge pclk) + \[15515] <= n3863; + always @(posedge pclk) + ppeaka_2_2_ <= n565; + always @(posedge pclk) + \[15545] <= n3868; + always @(posedge pclk) + \[15560] <= n3873; + always @(posedge pclk) + \[15575] <= n3878_1; + always @(posedge pclk) + \[15590] <= n3883_1; + always @(posedge pclk) + \[15605] <= n3888_1; + always @(posedge pclk) + \[15620] <= n3893_1; + always @(posedge pclk) + \[15635] <= n3898_1; + always @(posedge pclk) + \[15650] <= n3903_1; + always @(posedge pclk) + \[15665] <= n3908_1; + always @(posedge pclk) + \[15680] <= n3913_1; + always @(posedge pclk) + ppeaks_15_15_ <= n569_1; + always @(posedge pclk) + \[15695] <= n3918_1; + always @(posedge pclk) + \[15710] <= n3923_1; + always @(posedge pclk) + \[15725] <= n3928_1; + always @(posedge pclk) + \[15755] <= n3933_1; + always @(posedge pclk) + \[15770] <= n3938_1; + always @(posedge pclk) + \[15785] <= n3943_1; + always @(posedge pclk) + \[15845] <= n3948_1; + always @(posedge pclk) + \[15860] <= n3953_1; + always @(posedge pclk) + \[15890] <= n3958; + always @(posedge pclk) + \[15905] <= n3963; + always @(posedge pclk) + ppeaks_9_9_ <= n573; + always @(posedge pclk) + \[15920] <= n3968; + always @(posedge pclk) + \[15935] <= n3973; + always @(posedge pclk) + \[15950] <= n3978; + always @(posedge pclk) + \[15965] <= n3983; + always @(posedge pclk) + \[15980] <= n3988; + always @(posedge pclk) + \[15995] <= n3993; + always @(posedge pclk) + \[16010] <= n3998; + always @(posedge pclk) + \[16025] <= n4003; + always @(posedge pclk) + \[16040] <= n4008; + always @(posedge pclk) + \[16055] <= n4013; + always @(posedge pclk) + ppeakb_3_3_ <= n577; + always @(posedge pclk) + \[16070] <= n4018; + always @(posedge pclk) + \[16085] <= n4023; + always @(posedge pclk) + \[16100] <= n4028; + always @(posedge pclk) + \[16907] <= n4033; + always @(posedge pclk) + \[16920] <= n4038; + always @(posedge pclk) + \[16933] <= n4043; + always @(posedge pclk) + \[16959] <= n4048; + always @(posedge pclk) + \[16972] <= n4053; + always @(posedge pclk) + \[16985] <= n4058; + always @(posedge pclk) + \[16998] <= n4063; + always @(posedge pclk) + ppeakp_15_15_ <= n581; + always @(posedge pclk) + \[17011] <= n4068; + always @(posedge pclk) + \[17024] <= n4073; + always @(posedge pclk) + \[17037] <= n4078; + always @(posedge pclk) + \[17050] <= n4083; + always @(posedge pclk) + \[17063] <= n4088; + always @(posedge pclk) + \[17076] <= n4093; + always @(posedge pclk) + \[17089] <= n4098; + always @(posedge pclk) + \[17102] <= n4103; + always @(posedge pclk) + \[17115] <= n4108; + always @(posedge pclk) + \[17128] <= n4113; + always @(posedge pclk) + ppeakp_11_11_ <= n585; + always @(posedge pclk) + \[17141] <= n4118; + always @(posedge pclk) + \[17154] <= n4123; + always @(posedge pclk) + \[17167] <= n4128; + always @(posedge pclk) + \[17180] <= n4133; + always @(posedge pclk) + \[17193] <= n4138; + always @(posedge pclk) + \[17206] <= n4143; + always @(posedge pclk) + \[17219] <= n4148; + always @(posedge pclk) + \[17232] <= n4153; + always @(posedge pclk) + \[17245] <= n4158; + always @(posedge pclk) + \[17258] <= n4163; + always @(posedge pclk) + paddress_3_3_ <= n301; + always @(posedge pclk) + ppeaka_13_13_ <= n589_1; + always @(posedge pclk) + \[17271] <= n4168; + always @(posedge pclk) + \[17284] <= n4173; + always @(posedge pclk) + \[17297] <= n4178; + always @(posedge pclk) + \[17310] <= n4183; + always @(posedge pclk) + \[17323] <= n4188; + always @(posedge pclk) + \[17336] <= n4193; + always @(posedge pclk) + \[17349] <= n4198; + always @(posedge pclk) + \[17362] <= n4203_1; + always @(posedge pclk) + \[17375] <= n4208_1; + always @(posedge pclk) + \[17388] <= n4213_1; + always @(posedge pclk) + ppeaka_3_3_ <= n593; + always @(posedge pclk) + \[17414] <= n4218_1; + always @(posedge pclk) + \[17427] <= n4223_1; + always @(posedge pclk) + \[17453] <= n4228; + always @(posedge pclk) + \[17479] <= n4233; + always @(posedge pclk) + \[17492] <= n4238; + always @(posedge pclk) + \[17505] <= n4243; + always @(posedge pclk) + \[17518] <= n4248; + always @(posedge pclk) + \[17531] <= n4253; + always @(posedge pclk) + \[17544] <= n4258; + always @(posedge pclk) + \[17570] <= n4263; + always @(posedge pclk) + paddress_14_14_ <= n597; + always @(posedge pclk) + \[17583] <= n4268; + always @(posedge pclk) + \[17596] <= n4273; + always @(posedge pclk) + \[17609] <= n4278; + always @(posedge pclk) + \[17635] <= n4283; + always @(posedge pclk) + \[17648] <= n4288; + always @(posedge pclk) + \[17661] <= n4293; + always @(posedge pclk) + \[17674] <= n4298; + always @(posedge pclk) + \[17700] <= n4303; + always @(posedge pclk) + \[17713] <= n4308; + always @(posedge pclk) + \[17739] <= n4313; + always @(posedge pclk) + paddress_12_12_ <= n601; + always @(posedge pclk) + \[17752] <= n4318; + always @(posedge pclk) + \[17765] <= n4323; + always @(posedge pclk) + \[17778] <= n4328_1; + always @(posedge pclk) + \[17791] <= n4333_1; + always @(posedge pclk) + \[17804] <= n4338_1; + always @(posedge pclk) + \[17817] <= n4343_1; + always @(posedge pclk) + \[17843] <= n4348_1; + always @(posedge pclk) + \[17856] <= n4353_1; + always @(posedge pclk) + \[17869] <= n4358_1; + always @(posedge pclk) + \[17882] <= n4363_1; + always @(posedge pclk) + ppeakb_13_13_ <= n605; + always @(posedge pclk) + \[17908] <= n4368_1; + always @(posedge pclk) + \[17921] <= n4373_1; + always @(posedge pclk) + \[17934] <= n4378_1; + always @(posedge pclk) + \[17947] <= n4383_1; + always @(posedge pclk) + \[17960] <= n4388; + always @(posedge pclk) + \[17973] <= n4393; + always @(posedge pclk) + \[17986] <= n4398; + always @(posedge pclk) + \[17999] <= n4403; + always @(posedge pclk) + \[18012] <= n4408; + always @(posedge pclk) + \[18025] <= n4413; + always @(posedge pclk) + ppeakb_4_4_ <= n609_1; + always @(posedge pclk) + \[18038] <= n4418; + always @(posedge pclk) + \[18064] <= n4423; + always @(posedge pclk) + \[18077] <= n4428; + always @(posedge pclk) + \[18090] <= n4433; + always @(posedge pclk) + \[18103] <= n4438; + always @(posedge pclk) + \[18116] <= n4443; + always @(posedge pclk) + \[18129] <= n4448; + always @(posedge pclk) + \[18142] <= n4453; + always @(posedge pclk) + \[18155] <= n4458; + always @(posedge pclk) + \[18168] <= n4463; + always @(posedge pclk) + pdn <= n613; + always @(posedge pclk) + \[18181] <= n4468; + always @(posedge pclk) + \[18194] <= n4473; + always @(posedge pclk) + \[18207] <= n4478; + always @(posedge pclk) + \[18220] <= n4483; + always @(posedge pclk) + \[18233] <= n4488; + always @(posedge pclk) + \[18246] <= n4493; + always @(posedge pclk) + \[18285] <= n4498; + always @(posedge pclk) + \[18298] <= n4503; + always @(posedge pclk) + \[18311] <= n4508; + always @(posedge pclk) + \[18337] <= n4513; + always @(posedge pclk) + ppeaka_4_4_ <= n617; + always @(posedge pclk) + \[18350] <= n4518_1; + always @(posedge pclk) + \[18363] <= n4523_1; + always @(posedge pclk) + \[18376] <= n4528_1; + always @(posedge pclk) + \[18389] <= n4533_1; + always @(posedge pclk) + \[18415] <= n4538; + always @(posedge pclk) + \[18428] <= n4543; + always @(posedge pclk) + \[18441] <= n4548; + always @(posedge pclk) + \[18467] <= n4553; + always @(posedge pclk) + \[18480] <= n4558; + always @(posedge pclk) + \[18493] <= n4563; + always @(posedge pclk) + ppeaki_0_0_ <= n621; + always @(posedge pclk) + \[18506] <= n4568; + always @(posedge pclk) + \[18545] <= n4573; + always @(posedge pclk) + \[18571] <= n4578; + always @(posedge pclk) + \[18584] <= n4583; + always @(posedge pclk) + \[18597] <= n4588; + always @(posedge pclk) + \[18610] <= n4593; + always @(posedge pclk) + \[18636] <= n4598_1; + always @(posedge pclk) + prd_0_0_ <= n625; + always @(posedge pclk) + ppeakb_14_14_ <= n305; + always @(posedge pclk) + ppeakb_5_5_ <= n629_1; + always @(posedge pclk) + ppeaka_5_5_ <= n633; + always @(posedge pclk) + ppeaks_14_14_ <= n637; + always @(posedge pclk) + ppeaki_1_1_ <= n641; + always @(posedge pclk) + paddress_1_1_ <= n645; + always @(posedge pclk) + ppeakb_6_6_ <= n649_1; + always @(posedge pclk) + ppeaka_6_6_ <= n653; + always @(posedge pclk) + ppeaks_11_11_ <= n657; + always @(posedge pclk) + ppeaki_12_12_ <= n661; + always @(posedge pclk) + ppeaki_2_2_ <= n665; + assign n2910 = 64'h80800080aaaa00aa >> { n2862, n2917, ppeaks_5_5_, n2911, n2915, n2919 }; + assign n2911 = 64'h0008080800888888 >> { n2838, n2849, \[10895] , \[13430] , n2912, n2914 }; + assign n2912 = 64'h0000077707770777 >> { \[9545] , n2890, \[13505] , n2913_1, n2853_1, \[6185] }; + assign n2913_1 = 4'h2 >> { n2818, n2846 }; + assign n2914 = 64'h0000077707770777 >> { n2840, \[5420] , n2851, \[7445] , n2817, \[13055] }; + assign n2915 = 64'h0000077707770777 >> { \[6995] , n2916, n2883_1, \[11465] , n2847, \[10280] }; + assign n2916 = 4'h2 >> { n2818, n2896 }; + assign n2917 = 16'h2022 >> { n2860, n2873_1, n2861, n2918_1 }; + assign n2918_1 = 64'hbbbbbbbbabbbbbbb >> { \[17089] , pdn, n2859, n2821, n2818, preset }; + assign n2919 = 64'h0000077707770777 >> { n2920, \[11885] , n2874, \[13700] , n2872, \[15395] }; + assign n2920 = 16'h0002 >> { n2859, preset, \[17089] , pdn }; + assign n505 = 4'h7 >> { n2922, n2929 }; + assign n2922 = 64'h00000ddd0ddd0ddd >> { n2920, \[12140] , n2928_1, ppeaka_10_10_, n2923_1, ppeakp_10_10_ }; + assign n2923_1 = 32'd176851594 >> { n2924, n2836, n2862, n2927, n2918_1 }; + assign n2924 = 64'h0000000000000008 >> { ppeakb_12_12_, ppeakb_1_1_, ppeakb_13_13_, ppeakb_4_4_, n2925, n2926 }; + assign n2925 = 64'h0000000000000001 >> { ppeakb_15_15_, ppeakb_11_11_, ppeakb_0_0_, ppeakb_2_2_, ppeakb_3_3_, ppeakb_5_5_ }; + assign n2926 = 64'h0000000000000001 >> { ppeakb_6_6_, ppeakb_8_8_, ppeakb_14_14_, ppeakb_7_7_, ppeakb_10_10_, ppeakb_9_9_ }; + assign n2927 = 16'h88d8 >> { n2828, n2835, n2829, n2837 }; + assign n2928_1 = 32'd2852653064 >> { n2827, n2829, n2924, n2836, n2862 }; + assign n2929 = 64'h0777077700000777 >> { n2873_1, \[4850] , n2930, \[6965] , n2898_1, ppeakb_10_10_ }; + assign n2930 = 4'h8 >> { n2862, n2891 }; + assign n688 = 32'd1426346240 >> { pdata_0_0_, \[4355] , \[18246] , \[17453] , preset }; + assign n693 = 32'd1426346240 >> { pdata_11_11_, \[4370] , \[18246] , \[17453] , preset }; + assign n698 = 16'h3120 >> { \[4385] , pdata_6_6_, preset, n4451 }; + assign n2934 = 16'h5444 >> { n2870, \[17713] , n2871, \[18168] }; + assign n703 = 32'd1426346240 >> { pdata_1_1_, \[4400] , \[17154] , \[17102] , preset }; + assign n708 = 32'd1426346240 >> { pdata_12_12_, \[4415] , \[17154] , \[17102] , preset }; + assign n713 = 16'h3120 >> { \[4430] , pdata_7_7_, preset, n2938_1 }; + assign n2938_1 = 8'h08 >> { \[18285] , n2848, n2833 }; + assign n718 = 16'h3120 >> { \[4445] , pdata_2_2_, preset, n2938_1 }; + assign n723 = 16'h3120 >> { \[4460] , pdata_13_13_, preset, n2938_1 }; + assign n728 = 32'd1426346240 >> { pdata_8_8_, \[4475] , \[17362] , \[17167] , preset }; + assign n4528_1 = 4'h2 >> { preset, n2943_1 }; + assign n2943_1 = 4'h2 >> { \[18376] , \[17284] }; + assign n733 = 16'h3120 >> { \[4490] , pdata_3_3_, preset, n2943_1 }; + assign n738 = 16'h3120 >> { \[4505] , pdata_14_14_, preset, n2943_1 }; + assign n743_1 = 16'h3120 >> { \[4520] , pdata_9_9_, preset, n2947 }; + assign n2947 = 4'h8 >> { n2833, n2948_1 }; + assign n2948_1 = 16'h0008 >> { n2828, \[18493] , n2829, n2827 }; + assign n748 = 16'h3120 >> { \[4535] , pdata_15_15_, preset, n2950 }; + assign n2950 = 8'h08 >> { \[16920] , n2836, n4509 }; + assign n753 = 16'h3120 >> { \[4550] , pdata_10_10_, preset, n2952 }; + assign n2952 = 8'h08 >> { \[17297] , n2839, n4509 }; + assign n758 = 16'h3120 >> { \[4565] , pdata_5_5_, preset, n2954 }; + assign n2954 = 8'h08 >> { \[18506] , n2854, n2833 }; + assign n763 = 16'h3120 >> { \[4580] , pdata_0_0_, preset, n2954 }; + assign n768 = 16'h3120 >> { \[4595] , pdata_11_11_, preset, n2954 }; + assign n773 = 32'd1426346240 >> { pdata_6_6_, \[4610] , \[17310] , \[17388] , preset }; + assign n4228 = 4'h2 >> { preset, n2959 }; + assign n2959 = 16'h0080 >> { \[18610] , n2864, n2833, n2960 }; + assign n2960 = 64'h1010101010105510 >> { \[17609] , \[17674] , n2865, n2877, ppeaki_4_4_, \[17453] }; + assign n778 = 16'hf222 >> { n2986, \[4625] , n2962, n2983_1 }; + assign n2962 = 8'ha9 >> { n2977, n2981, n2963_1 }; + assign n2963_1 = 16'h082a >> { ppeaks_0_0_, n2971, n2964, n2974 }; + assign n2964 = 32'd2 >> { n2959, n2968_1, n2969, n2970, n2965 }; + assign n2965 = 16'h5557 >> { n2948_1, n2967, n2966, n2833 }; + assign n2966 = 16'h0008 >> { n2828, \[16920] , n2832, n2837 }; + assign n2967 = 16'h0002 >> { n2828, n2829, \[17297] , n2827 }; + assign n2968_1 = 8'h08 >> { \[16933] , n2850, n2833 }; + assign n2969 = 8'h08 >> { \[17284] , n2841, n2833 }; + assign n2970 = 4'h2 >> { \[18103] , \[18168] }; + assign n2971 = 64'h0000000100010001 >> { ppeaka_0_0_, n4451, n2954, n2972, n2973_1, n2938_1 }; + assign n2972 = 4'h2 >> { \[18311] , \[18506] }; + assign n2973_1 = 4'h2 >> { \[18363] , \[18285] }; + assign n2974 = 64'h0002020200222222 >> { n4451, n2954, \[4310] , ppeakb_0_0_, n2975, n2976 }; + assign n2975 = 16'h0080 >> { \[18285] , n2848, n2833, ppeaka_0_0_ }; + assign n2976 = 16'h0777 >> { \[8630] , n2973_1, n2972, \[10025] }; + assign n2977 = 64'h4474777700707777 >> { ppeakb_1_1_, n2979, n2964, ppeaks_1_1_, n2978, ppeaka_1_1_ }; + assign n2978 = 16'h0080 >> { \[18610] , n2864, n2934, n4509 }; + assign n2979 = 32'd2763306 >> { \[5030] , n2954, n2938_1, ppeaka_1_1_, n2980 }; + assign n2980 = 16'h0777 >> { \[9290] , n2973_1, n2972, \[10310] }; + assign n2981 = 8'h08 >> { ppeakb_1_1_, n2982, n2979 }; + assign n2982 = 4'h8 >> { n4451, ppeaka_1_1_ }; + assign n2983_1 = 8'h08 >> { preset, n2960, n2984 }; + assign n2984 = 4'h2 >> { \[18610] , n2985 }; + assign n2985 = 4'h8 >> { n4509, n2864 }; + assign n2986 = 4'h1 >> { n2959, preset }; + assign n783 = 32'd4286743170 >> { n2986, \[4640] , n2988_1, n3000, n2983_1 }; + assign n2988_1 = 4'h6 >> { n2989, n2997 }; + assign n2989 = 32'd1431651348 >> { n2993_1, ppeaka_11_11_, n2990, ppeaka_12_12_, n2996 }; + assign n2990 = 32'd572662314 >> { ppeaka_8_8_, ppeaka_9_9_, ppeaka_10_10_, n2995, n2991 }; + assign n2991 = 8'h15 >> { ppeaka_7_7_, n2995, n2992 }; + assign n2992 = 32'd1431655764 >> { ppeaka_6_6_, ppeaka_5_5_, n2994, ppeaka_4_4_, n2993_1 }; + assign n2993_1 = 8'h08 >> { n2978, n2964, n2971 }; + assign n2994 = 64'hf7f7f7f7f7f7f777 >> { ppeaka_3_3_, ppeaka_1_1_, ppeaka_2_2_, n2995, n2971, n2964 }; + assign n2995 = 32'd8 >> { n2869, \[18610] , \[18168] , n2864, n4509 }; + assign n2996 = 4'h2 >> { n2995, n2992 }; + assign n2997 = 32'd707395626 >> { n2964, ppeaks_12_12_, n2978, ppeakb_12_12_, n2998_1 }; + assign n2998_1 = 32'd2763306 >> { \[15845] , n2954, n2938_1, ppeaka_12_12_, n2999 }; + assign n2999 = 16'h0777 >> { \[10010] , n2973_1, n2972, \[6860] }; + assign n3000 = 64'haaaeeeef0008888a >> { n3042, n3043_1, n3001, n3044, n3045, n3048_1 }; + assign n3001 = 64'h5555555500101011 >> { n3006, n3011, n3039, n3038_1, n3010, n3002 }; + assign n3002 = 64'h2222222220200220 >> { n2993_1, ppeaka_8_8_, n2991, ppeaka_9_9_, n2996, n3003_1 }; + assign n3003_1 = 8'h8a >> { ppeaks_9_9_, n2964, n3004 }; + assign n3004 = 32'd2763306 >> { ppeaka_9_9_, n2938_1, n2978, ppeakb_9_9_, n3005 }; + assign n3005 = 64'h0000077707770777 >> { \[7370] , n2973_1, n2972, \[10040] , n2954, \[5720] }; + assign n3006 = 16'h2111 >> { n2995, ppeaka_8_8_, n3007, n2991 }; + assign n3007 = 8'h8a >> { ppeaks_8_8_, n2964, n3008_1 }; + assign n3008_1 = 32'd2763306 >> { ppeaka_8_8_, n2938_1, n2995, ppeakb_8_8_, n3009 }; + assign n3009 = 64'h0000077707770777 >> { \[8000] , n2973_1, n2972, \[8750] , n2954, \[6410] }; + assign n3010 = 16'h2888 >> { n2995, ppeaka_8_8_, n2991, n3007 }; + assign n3011 = 32'd1431651588 >> { n3017, n3018_1, n3034, n3035, n3012 }; + assign n3012 = 32'd68501525 >> { ppeaka_5_5_, n3013_1, ppeaka_6_6_, n2995, n3014 }; + assign n3013_1 = 8'h15 >> { ppeaka_4_4_, n2978, n2994 }; + assign n3014 = 8'h8a >> { ppeaks_6_6_, n2964, n3015 }; + assign n3015 = 32'd2763306 >> { \[7685] , n2954, n2978, ppeakb_6_6_, n3016 }; + assign n3016 = 64'h0000077707770777 >> { \[6740] , n2973_1, n2972, \[7475] , n2938_1, ppeaka_6_6_ }; + assign n3017 = 32'd2155874432 >> { ppeaka_5_5_, n3013_1, ppeaka_6_6_, n2995, n3014 }; + assign n3018_1 = 32'd143306479 >> { n3019, n3021, n3027, n3031, n3028_1 }; + assign n3019 = 64'h2727272727272787 >> { ppeaka_1_1_, ppeaka_2_2_, ppeaka_3_3_, n3020, ppeaka_4_4_, n2995 }; + assign n3020 = 4'h8 >> { n2964, n2971 }; + assign n3021 = 64'hdcdcdcdc444444dc >> { n2977, n2963_1, n2981, n3023_1, n3022, n3024 }; + assign n3022 = 16'h5515 >> { n2982, n2971, n2964, n3023_1 }; + assign n3023_1 = 4'h8 >> { n4451, ppeaka_2_2_ }; + assign n3024 = 32'd707395626 >> { n2964, ppeaks_2_2_, n2978, ppeakb_2_2_, n3025 }; + assign n3025 = 32'd2763306 >> { \[15515] , n2954, n2938_1, ppeaka_2_2_, n3026 }; + assign n3026 = 16'h0777 >> { \[9725] , n2973_1, n2972, \[4760] }; + assign n3027 = 32'd656877447 >> { ppeaka_1_1_, ppeaka_2_2_, n3020, ppeaka_3_3_, n2995 }; + assign n3028_1 = 8'h2a >> { ppeakb_4_4_, n2995, n3029 }; + assign n3029 = 32'd9079434 >> { n2954, \[14765] , ppeaks_4_4_, n2964, n3030 }; + assign n3030 = 64'h0000077707770777 >> { \[5375] , n2973_1, n2972, \[6170] , n2938_1, ppeaka_4_4_ }; + assign n3031 = 32'd707395626 >> { n2964, ppeaks_3_3_, n2978, ppeakb_3_3_, n3032 }; + assign n3032 = 32'd2763306 >> { \[15860] , n2954, n2938_1, ppeaka_3_3_, n3033_1 }; + assign n3033_1 = 16'h0777 >> { \[9995] , n2973_1, n2972, \[6845] }; + assign n3034 = 8'h95 >> { n2995, ppeaka_5_5_, n3013_1 }; + assign n3035 = 32'd707395626 >> { n2964, ppeaks_5_5_, n2978, ppeakb_5_5_, n3036 }; + assign n3036 = 32'd2763306 >> { \[8330] , n2954, n2938_1, ppeaka_5_5_, n3037 }; + assign n3037 = 16'h0777 >> { \[4670] , n2973_1, n2972, \[8105] }; + assign n3038_1 = 8'h6a >> { n2978, ppeaka_7_7_, n2992 }; + assign n3039 = 16'h8088 >> { ppeaks_7_7_, n2964, n3041, n3040 }; + assign n3040 = 64'h0000077707770777 >> { n2954, \[7055] , ppeaka_7_7_, n2938_1, n4451, ppeakb_7_7_ }; + assign n3041 = 16'h0777 >> { \[6065] , n2973_1, n2972, \[9410] }; + assign n3042 = 8'h6a >> { n2995, ppeaka_11_11_, n2990 }; + assign n3043_1 = 32'd656877447 >> { ppeaka_8_8_, ppeaka_9_9_, n2991, ppeaka_10_10_, n2978 }; + assign n3044 = 32'd1431638337 >> { n2996, ppeaka_8_8_, n2991, ppeaka_9_9_, n3003_1 }; + assign n3045 = 8'h8a >> { ppeaks_10_10_, n2964, n3046 }; + assign n3046 = 32'd2763306 >> { \[5015] , n2954, n4451, ppeakb_10_10_, n3047 }; + assign n3047 = 64'h0000077707770777 >> { \[9305] , n2973_1, n2972, \[9770] , n2938_1, ppeaka_10_10_ }; + assign n3048_1 = 32'd707395626 >> { n2964, ppeaks_11_11_, n2978, ppeakb_11_11_, n3049 }; + assign n3049 = 32'd2763306 >> { n2954, \[4295] , n2938_1, ppeaka_11_11_, n3050 }; + assign n3050 = 16'h0777 >> { \[8645] , n2973_1, n2972, \[10595] }; + assign n788 = 16'h3120 >> { \[4655] , n3052, preset, n2970 }; + assign n3052 = 64'h9969996999696966 >> { n3001, n3044, n3043_1, n3045, n3042, n3048_1 }; + assign n793 = 16'h3120 >> { \[4670] , n3054, preset, n2938_1 }; + assign n3054 = 8'h96 >> { n3018_1, n3034, n3035 }; + assign n798 = 16'h3120 >> { \[4700] , n3056, preset, n2973_1 }; + assign n3056 = 16'h6669 >> { n3001, n3044, n3043_1, n3045 }; + assign n803 = 16'h3120 >> { \[4715] , n3058_1, preset, n2969 }; + assign n3058_1 = 32'd1721144985 >> { n3021, n3027, n3031, n3019, n3028_1 }; + assign n3059 = 32'd3774775544 >> { n3000, n3060, n3063_1, n2989, n2997 }; + assign n3060 = 16'h5515 >> { n3061, n2978, ppeaka_13_13_, n3062 }; + assign n3061 = 8'h02 >> { ppeaka_12_12_, ppeaka_11_11_, n2990 }; + assign n3062 = 32'd572662314 >> { ppeaka_12_12_, ppeaka_11_11_, ppeaka_13_13_, n2995, n2990 }; + assign n3063_1 = 32'd707395626 >> { n2964, ppeaks_13_13_, n2978, ppeakb_13_13_, n3064 }; + assign n3064 = 32'd2763306 >> { \[15500] , n2954, n2938_1, ppeaka_13_13_, n3065 }; + assign n3065 = 16'h0777 >> { \[9740] , n2973_1, n2972, \[4775] }; + assign n3066 = 32'd289494357 >> { n2995, ppeaka_13_13_, n3061, ppeaka_14_14_, n3067 }; + assign n3067 = 8'h8a >> { ppeaks_14_14_, n2964, n3068_1 }; + assign n3068_1 = 32'd2763306 >> { n2973_1, \[6080] , n2972, \[5480] , n3069 }; + assign n3069 = 32'd1381653 >> { ppeaka_14_14_, n2938_1, n4451, ppeakb_14_14_, n3070 }; + assign n3070 = 4'h8 >> { n2954, \[15140] }; + assign n3071 = 64'ha2aaa2aa80088080 >> { n2993_1, n3061, ppeaka_13_13_, ppeaka_14_14_, n2995, n3067 }; + assign n4563 = 4'h2 >> { preset, n2947 }; + assign n813 = 16'h3120 >> { \[4745] , n3074, preset, n2947 }; + assign n3074 = 8'h56 >> { n3044, n3002, n3075 }; + assign n3075 = 32'd1431651588 >> { n3010, n3011, n3038_1, n3039, n3006 }; + assign n818 = 16'h1302 >> { \[4760] , n3077, preset, n2954 }; + assign n3077 = 32'd1768515942 >> { n2963_1, n2981, n2977, n3023_1, n3024 }; + assign n823 = 16'h3120 >> { \[4775] , n3079, preset, n2954 }; + assign n3079 = 32'd2576782950 >> { n3000, n2989, n2997, n3060, n3063_1 }; + assign n828 = 16'h3120 >> { \[4790] , n3081, preset, n2972 }; + assign n3081 = 8'h96 >> { n3011, n3038_1, n3039 }; + assign n833 = 16'h1302 >> { \[4805] , n2962, preset, n2968_1 }; + assign n838 = 32'd823336962 >> { \[4820] , n3000, n2988_1, preset, n2968_1 }; + assign n843 = 16'hf888 >> { n3136, \[4835] , n3085, n3137 }; + assign n3085 = 16'h6999 >> { n2968_1, ppeaka_6_6_, n3086, n3132 }; + assign n3086 = 64'h8f8f8f8f08088a08 >> { n3087, n3127, ppeaka_4_4_, n3128_1, ppeaka_5_5_, n2968_1 }; + assign n3087 = 64'h0040404444545455 >> { n3104, n3109, n3113_1, n3125, n3126, n3088_1 }; + assign n3088_1 = 8'h8a >> { ppeaks_4_4_, n3089, n3095 }; + assign n3089 = 16'h0002 >> { n3090, n3091, n3092, n3093_1 }; + assign n3090 = 8'h08 >> { \[17115] , n2846, n2833 }; + assign n3091 = 8'h08 >> { \[17180] , n2896, n2833 }; + assign n3092 = 8'h08 >> { \[17206] , n2884, n2833 }; + assign n3093_1 = 16'h5515 >> { \[18025] , n2833, n2891, n3094 }; + assign n3094 = 32'd2 >> { n2860, pdn, \[18467] , \[17817] , n2859 }; + assign n3095 = 32'd2763306 >> { ppeaka_4_4_, n3096, n2968_1, ppeakb_4_4_, n3097 }; + assign n3096 = 8'h08 >> { \[17245] , n2886, n2833 }; + assign n3097 = 64'h0d005d000f007f00 >> { \[10505] , n3102, n3098_1, ppeakp_4_4_, n2860, n3103_1 }; + assign n3098_1 = 64'h0000077707770777 >> { n3101, \[12245] , \[15035] , n3100, n3099, \[6230] }; + assign n3099 = 4'h2 >> { \[17648] , \[17427] }; + assign n3100 = 4'h2 >> { \[17999] , \[18077] }; + assign n3101 = 4'h2 >> { \[17232] , \[17180] }; + assign n3102 = 4'h2 >> { \[17037] , \[18025] }; + assign n3103_1 = 4'h2 >> { \[17986] , \[17635] }; + assign n3104 = 32'd9079434 >> { n3096, ppeaka_3_3_, ppeaks_3_3_, n3089, n3105 }; + assign n3105 = 32'd707395626 >> { n3108_1, ppeakp_3_3_, n2968_1, ppeakb_3_3_, n3106 }; + assign n3106 = 16'haa2a >> { n2860, n3103_1, \[10790] , n3107 }; + assign n3107 = 64'h0000077707770777 >> { n3101, \[12455] , \[12845] , n3100, n3099, \[8165] }; + assign n3108_1 = 8'h15 >> { n3103_1, n2860, n3102 }; + assign n3109 = 32'd9079434 >> { n2968_1, ppeakb_2_2_, ppeaks_2_2_, n3089, n3110 }; + assign n3110 = 32'd707395626 >> { n3108_1, ppeakp_2_2_, n3096, ppeaka_2_2_, n3111 }; + assign n3111 = 16'haa2a >> { n2860, n3103_1, \[11060] , n3112 }; + assign n3112 = 64'h0000077707770777 >> { n3101, \[12680] , \[13100] , n3100, n3099, \[7535] }; + assign n3113_1 = 64'h5d045d045d040c00 >> { n3119, n4457, n3124, n3114, n3115, n3118_1 }; + assign n3114 = 32'd2863311522 >> { n3090, n3091, n3092, n3093_1, ppeaks_1_1_ }; + assign n3115 = 32'd2763306 >> { ppeaka_1_1_, n3096, n2968_1, ppeakb_1_1_, n3116 }; + assign n3116 = 64'h0d005d000f007f00 >> { \[11315] , n3102, n3117, ppeakp_1_1_, n2860, n3103_1 }; + assign n3117 = 64'h0000077707770777 >> { n3101, \[12920] , \[12380] , n3100, n3099, \[9485] }; + assign n3118_1 = 32'd2863311522 >> { n3090, n3091, n3092, n3093_1, ppeaks_0_0_ }; + assign n3119 = 32'd2763306 >> { ppeaka_0_0_, n3096, n2968_1, ppeakb_0_0_, n3120 }; + assign n3120 = 64'h0022222200020202 >> { n3108_1, n3099, \[11630] , ppeakp_0_0_, n3121, n3122 }; + assign n3121 = 8'h08 >> { n2860, n3103_1, \[11555] }; + assign n3122 = 16'h0777 >> { n3101, \[13175] , n3100, \[12605] }; + assign n3123_1 = 16'h0001 >> { n3102, n3103_1, n3099, n3100 }; + assign n3124 = 8'h15 >> { ppeaka_1_1_, n2968_1, n3101 }; + assign n3125 = 4'h8 >> { n2968_1, ppeaka_2_2_ }; + assign n3126 = 4'h8 >> { n2968_1, ppeaka_3_3_ }; + assign n3127 = 64'h8aaa0a8a080a0008 >> { n3104, n3109, n3125, n3126, n3113_1, n3088_1 }; + assign n3128_1 = 8'h8a >> { ppeaks_5_5_, n3089, n3129 }; + assign n3129 = 32'd2763306 >> { ppeaka_5_5_, n3096, n2968_1, ppeakb_5_5_, n3130 }; + assign n3130 = 64'h0d005d000f007f00 >> { \[10220] , n3102, n3131, ppeakp_5_5_, n2860, n3103_1 }; + assign n3131 = 64'h0000077707770777 >> { \[6995] , n3101, \[15395] , n3100, n3099, \[6905] }; + assign n3132 = 32'd9079434 >> { n3096, ppeaka_6_6_, ppeaks_6_6_, n3089, n3133_1 }; + assign n3133_1 = 8'h2a >> { ppeakb_6_6_, n2968_1, n3134 }; + assign n3134 = 64'h0d005d000f007f00 >> { \[9950] , n3102, n3135, ppeakp_6_6_, n2860, n3103_1 }; + assign n3135 = 64'h0000077707770777 >> { n3101, \[7625] , n3100, \[14210] , n3099, \[4835] }; + assign n3136 = 4'h1 >> { n3094, preset }; + assign n3137 = 4'h2 >> { preset, n3094 }; + assign n848 = 16'h3120 >> { \[4850] , n3139, preset, n3103_1 }; + assign n3139 = 8'h69 >> { n3140, n3154, n3158 }; + assign n3140 = 64'h80a0a8ff0080a0a8 >> { n3141, n3146, n3150, ppeaka_9_9_, ppeaka_8_8_, n2968_1 }; + assign n3141 = 64'h80a0a8ff0080a0a8 >> { n3086, n3142, n3132, ppeaka_7_7_, ppeaka_6_6_, n2968_1 }; + assign n3142 = 64'ha2a2a2a200a2a2a2 >> { n2860, n3103_1, \[11075] , n3089, ppeaks_7_7_, n3143_1 }; + assign n3143_1 = 32'd2763306 >> { n3096, ppeaka_7_7_, n2968_1, ppeakb_7_7_, n3144 }; + assign n3144 = 8'h8a >> { ppeakp_7_7_, n3108_1, n3145 }; + assign n3145 = 64'h0000077707770777 >> { n3101, \[8255] , \[14630] , n3100, n3099, \[5540] }; + assign n3146 = 8'h8a >> { ppeaks_9_9_, n3089, n3147 }; + assign n3147 = 64'h0008080800888888 >> { n2968_1, n3096, ppeaka_9_9_, ppeakb_9_9_, n3149, n3148_1 }; + assign n3148_1 = 64'h0000077707770777 >> { n3101, \[9590] , \[13820] , n3100, n3099, \[11645] }; + assign n3149 = 32'd224202623 >> { \[11570] , n3102, ppeakp_9_9_, n2860, n3103_1 }; + assign n3150 = 8'h8a >> { ppeaks_8_8_, n3089, n3151 }; + assign n3151 = 32'd2763306 >> { ppeaka_8_8_, n3096, n2968_1, ppeakb_8_8_, n3152 }; + assign n3152 = 64'h0d005d000f007f00 >> { \[11330] , n3102, n3153_1, ppeakp_8_8_, n2860, n3103_1 }; + assign n3153_1 = 64'h0000077707770777 >> { n3101, \[8915] , \[13460] , n3100, n3099, \[11420] }; + assign n3154 = 32'd9079434 >> { n3096, ppeaka_10_10_, ppeaks_10_10_, n3089, n3155 }; + assign n3155 = 64'h0202000222220022 >> { n2968_1, n3108_1, ppeakp_10_10_, ppeakb_10_10_, n3157, n3156 }; + assign n3156 = 64'h0000077707770777 >> { n3101, \[9860] , \[12860] , n3100, n3099, \[10925] }; + assign n3157 = 8'h08 >> { n2860, n3103_1, \[11795] }; + assign n3158 = 4'h8 >> { n2968_1, ppeaka_10_10_ }; + assign n853 = 16'hf888 >> { n3161, \[4865] , n3160, n3162 }; + assign n3160 = 4'h1 >> { n3087, n3127 }; + assign n3161 = 16'h5515 >> { \[18025] , n4509, n2891, preset }; + assign n3162 = 16'h0008 >> { preset, \[18025] , n4509, n2891 }; + assign n858 = 64'hffffffff88282822 >> { n3189, n3164, n3190, n3185, n3181, n3162 }; + assign n3164 = 32'd2364475598 >> { n3165, n3171, n3175, n3180, n3179 }; + assign n3165 = 32'd2364475598 >> { n3140, n3166, n3154, n3170, n3158 }; + assign n3166 = 64'ha2a2a2a200a2a2a2 >> { n2860, n3103_1, \[11915] , n3089, ppeaks_11_11_, n3167 }; + assign n3167 = 32'd2763306 >> { ppeaka_11_11_, n3096, n2968_1, ppeakb_11_11_, n3168 }; + assign n3168 = 32'd9079434 >> { \[10130] , n3101, ppeakp_11_11_, n3108_1, n3169 }; + assign n3169 = 16'h0777 >> { \[13115] , n3100, n3099, \[16100] }; + assign n3170 = 4'h8 >> { n2968_1, ppeaka_11_11_ }; + assign n3171 = 8'h8a >> { ppeaks_13_13_, n3089, n3172 }; + assign n3172 = 32'd2763306 >> { ppeaka_13_13_, n3096, n2968_1, ppeakb_13_13_, n3173 }; + assign n3173 = 64'h0d005d000f007f00 >> { \[12170] , n3102, n3174, ppeakp_13_13_, n2860, n3103_1 }; + assign n3174 = 64'h0000077707770777 >> { n3101, \[10700] , \[12620] , n3100, n3099, \[13805] }; + assign n3175 = 8'h8a >> { ppeaks_12_12_, n3089, n3176 }; + assign n3176 = 32'd2763306 >> { ppeaka_12_12_, n3096, n2968_1, ppeakb_12_12_, n3177 }; + assign n3177 = 64'h0d005d000f007f00 >> { \[12050] , n3102, n3178, ppeakp_12_12_, n2860, n3103_1 }; + assign n3178 = 64'h0000077707770777 >> { n3101, \[10415] , \[12395] , n3100, n3099, \[15755] }; + assign n3179 = 4'h8 >> { n2968_1, ppeaka_12_12_ }; + assign n3180 = 4'h8 >> { n2968_1, ppeaka_13_13_ }; + assign n3181 = 64'h889888d888b88878 >> { n3096, ppeakb_15_15_, n3182, n3183, n2968_1, ppeaka_15_15_ }; + assign n3182 = 4'h2 >> { n3089, ppeaks_15_15_ }; + assign n3183 = 64'h0d005d000f007f00 >> { \[12470] , n3102, n3184, ppeakp_15_15_, n2860, n3103_1 }; + assign n3184 = 64'h0000077707770777 >> { n3101, \[6320] , \[15050] , n3100, n3099, \[14615] }; + assign n3185 = 32'd9079434 >> { n3096, ppeaka_14_14_, ppeaks_14_14_, n3089, n3186 }; + assign n3186 = 64'h0202000222220022 >> { n2968_1, n3108_1, ppeakp_14_14_, ppeakb_14_14_, n3188, n3187 }; + assign n3187 = 64'h0000077707770777 >> { n3101, \[10985] , \[15410] , n3100, n3099, \[13445] }; + assign n3188 = 8'h08 >> { n2860, n3103_1, \[12260] }; + assign n3189 = 4'h8 >> { n3161, \[4880] }; + assign n3190 = 4'h8 >> { n2968_1, ppeaka_14_14_ }; + assign n863 = 16'h1302 >> { \[4895] , n3192, preset, n3102 }; + assign n3192 = 64'h9a956a9a6a956a6a >> { ppeaka_8_8_, n3141, n3150, n2968_1, ppeaka_9_9_, n3146 }; + assign n868 = 16'hf888 >> { n3195, \[4910] , n3194, n3196 }; + assign n3194 = 32'd2573822310 >> { n3109, n3113_1, n3125, n3104, n3126 }; + assign n3195 = 4'h1 >> { n3092, preset }; + assign n3196 = 4'h2 >> { preset, n3092 }; + assign n873 = 16'h1302 >> { \[4925] , n3198, preset, n2968_1 }; + assign n3198 = 4'h6 >> { n3199, n3124 }; + assign n3199 = 32'd1499027724 >> { n3119, n4457, n3114, n3115, n3118_1 }; + assign n878 = 16'h1302 >> { \[4940] , n3201, preset, n2968_1 }; + assign n3201 = 4'h9 >> { n3202, n3179 }; + assign n3202 = 64'h95a5a9aa5595a5a9 >> { n3140, n3166, n3154, n3170, n3158, n3175 }; + assign n883 = 16'h3120 >> { \[4955] , n3085, preset, n3096 }; + assign n888 = 32'd1426346240 >> { pdata_1_1_, \[4970] , \[17843] , \[17791] , preset }; + assign n3205 = 64'h0000077707770777 >> { n2853_1, \[4580] , \[15995] , n2838, n2817, \[13655] }; + assign n3206 = 64'h0000077707770777 >> { \[4355] , n2874, \[4310] , n2872, n2867, \[8405] }; + assign n3207 = 32'd707439146 >> { n2894, \[7055] , n3210, n3208, n2862 }; + assign n3208 = 32'd2763306 >> { \[13985] , n2890, n2849, \[10460] , n3209 }; + assign n3209 = 64'h0ddd055501110111 >> { n2888_1, ppeaka_7_7_, n2892, \[5180] , ppeakb_7_7_, n2875 }; + assign n3210 = 64'h0000077707770777 >> { \[7025] , n2885, n2883_1, \[10970] , n2847, \[4430] }; + assign n893 = 16'h55d5 >> { preset, n2906, \[9620] , n3212 }; + assign n3212 = 64'h00000ddd0ddd0ddd >> { n2898_1, \[9200] , n2872, \[8180] , n2904, \[5015] }; + assign n898 = 32'd4285887861 >> { \[9185] , n2898_1, \[5030] , n2904, n3214 }; + assign n3214 = 32'd2004289399 >> { preset, n2906, \[9605] , \[13835] , n2872 }; + assign n469 = 64'hfffffbbbfbbbfbbb >> { \[15035] , n2872, n2867, \[14975] , n3221, n3216 }; + assign n3216 = 64'haaaaa222a222a222 >> { n2890, \[4865] , n2849, \[6875] , n3217, n2862 }; + assign n3217 = 64'h0008080800888888 >> { n2817, n2851, \[9380] , \[12350] , n3220, n3218 }; + assign n3218 = 32'd2763306 >> { n2916, \[12245] , n2847, \[8015] , n3219 }; + assign n3219 = 16'h0777 >> { n2883_1, \[5615] , n2840, \[4715] }; + assign n3220 = 64'h0000077707770777 >> { n2913_1, \[14675] , n2853_1, \[9785] , n2838, \[13790] }; + assign n3221 = 64'h00000ddd0ddd0ddd >> { \[11765] , n2920, n2874, \[11120] , n2917, ppeaks_4_4_ }; + assign n585 = 4'h7 >> { n3223, n3224 }; + assign n3223 = 64'h0ddd0ddd00000ddd >> { n2873_1, \[5555] , ppeaka_11_11_, n2928_1, n2923_1, ppeakp_11_11_ }; + assign n3224 = 64'h0000077707770777 >> { \[12020] , n2920, n2930, \[6290] , n2898_1, ppeakb_11_11_ }; + assign n903 = 32'd1426346240 >> { pdata_1_1_, \[5075] , \[18246] , \[17453] , preset }; + assign n908 = 32'd1426346240 >> { pdata_10_10_, \[5090] , \[18246] , \[17453] , preset }; + assign n913 = 32'd1426346240 >> { pdata_2_2_, \[5105] , \[17154] , \[17102] , preset }; + assign n918 = 32'd1426346240 >> { pdata_11_11_, \[5120] , \[17154] , \[17102] , preset }; + assign n923 = 16'h3120 >> { \[5135] , pdata_8_8_, preset, n2938_1 }; + assign n928 = 16'h3120 >> { \[5150] , pdata_1_1_, preset, n2938_1 }; + assign n933 = 16'h3120 >> { \[5165] , pdata_14_14_, preset, n2938_1 }; + assign n938 = 32'd1426346240 >> { pdata_7_7_, \[5180] , \[17362] , \[17167] , preset }; + assign n943 = 16'h3120 >> { \[5195] , pdata_4_4_, preset, n2943_1 }; + assign n948 = 16'h3120 >> { \[5210] , pdata_13_13_, preset, n2943_1 }; + assign n953 = 16'h3120 >> { \[5225] , pdata_10_10_, preset, n2947 }; + assign n958 = 16'h3120 >> { \[5240] , pdata_5_5_, preset, n2950 }; + assign n963 = 16'h3120 >> { \[5255] , pdata_11_11_, preset, n2952 }; + assign n968_1 = 16'h3120 >> { \[5270] , pdata_4_4_, preset, n2954 }; + assign n973 = 16'h3120 >> { \[5285] , pdata_1_1_, preset, n2954 }; + assign n978 = 16'h3120 >> { \[5300] , pdata_10_10_, preset, n2954 }; + assign n983 = 32'd1426346240 >> { pdata_7_7_, \[5315] , \[17310] , \[17388] , preset }; + assign n988 = 16'hf222 >> { n2986, \[5330] , n3243, n2983_1 }; + assign n3243 = 8'h51 >> { n2974, n3020, n2963_1 }; + assign n993 = 16'hf888 >> { n2986, \[5345] , n3079, n2983_1 }; + assign n998 = 32'd823336962 >> { \[5360] , n3000, n2988_1, preset, n2970 }; + assign n1003 = 16'h3120 >> { \[5375] , n3058_1, preset, n2938_1 }; + assign n1008 = 16'h1302 >> { \[5390] , n3243, preset, n2973_1 }; + assign n1013 = 16'h3120 >> { \[5405] , n3074, preset, n2973_1 }; + assign n1018 = 16'h3120 >> { \[5420] , n3054, preset, n2969 }; + assign n1023 = 16'h1302 >> { \[5435] , n3251, preset, n2969 }; + assign n3251 = 64'h56aa55566aaa556a >> { n3000, n3060, n3063_1, n2989, n2997, n3252 }; + assign n3252 = 64'h59556aa659556a6a >> { n3061, n2993_1, ppeaka_13_13_, ppeaka_14_14_, n2995, n3067 }; + assign n1028 = 16'h3120 >> { \[5450] , n3056, preset, n2947 }; + assign n4178 = 8'h08 >> { preset, n2967, n4509 }; + assign n1033 = 16'h3120 >> { \[5465] , n3074, preset, n2952 }; + assign n1038 = 16'h1302 >> { \[5480] , n3251, preset, n2954 }; + assign n1043 = 16'h1302 >> { \[5495] , n3258, preset, n2972 }; + assign n3258 = 32'd4233516547 >> { n3018_1, n3035, n3012, n3017, n3034 }; + assign n1048 = 16'h1302 >> { \[5510] , n3077, preset, n2968_1 }; + assign n1053 = 16'h3120 >> { \[5525] , n3052, preset, n2968_1 }; + assign n1058 = 16'hf888 >> { n3136, \[5540] , n3262, n3137 }; + assign n3262 = 64'h656a9565956a9595 >> { ppeaka_6_6_, n3086, n3132, n2968_1, ppeaka_7_7_, n3142 }; + assign n1063 = 16'h3120 >> { \[5555] , n3264, preset, n3103_1 }; + assign n3264 = 32'd1768331625 >> { n3140, n3154, n3158, n3166, n3170 }; + assign n1068 = 16'hf888 >> { n3161, \[5570] , n3194, n3162 }; + assign n1073 = 16'h1302 >> { \[5600] , n3267, preset, n3102 }; + assign n3267 = 16'h9666 >> { n2968_1, ppeaka_8_8_, n3141, n3150 }; + assign n1078 = 16'hf888 >> { n3195, \[5615] , n3160, n3196 }; + assign n4153 = 4'h2 >> { preset, n3101 }; + assign n1083 = 16'h1302 >> { \[5630] , n3267, preset, n3101 }; + assign n1088 = 16'h1302 >> { \[5645] , n3272, preset, n2968_1 }; + assign n3272 = 32'd2526635670 >> { n3165, n3175, n3179, n3171, n3180 }; + assign n1093 = 16'h1302 >> { \[5660] , n3274, preset, n3096 }; + assign n3274 = 64'h96669666a5669666 >> { n3127, ppeaka_4_4_, n2968_1, ppeaka_5_5_, n3087, n3128_1 }; + assign n1098 = 32'd1426346240 >> { pdata_0_0_, \[5675] , \[17843] , \[17791] , preset }; + assign n3276 = 64'h0008080800888888 >> { n2844, n2853_1, \[5300] , ppeaka_10_10_, n3278_1, n3277 }; + assign n3277 = 64'h0000077707770777 >> { n2840, \[7220] , \[4550] , n2838, n2851, \[5225] }; + assign n3278_1 = 64'h0000077707770777 >> { n2849, \[10850] , n2847, \[15230] , n2817, \[14060] }; + assign n329 = 8'hd5 >> { n2901, ppeaka_9_9_, n3280 }; + assign n3280 = 64'h80aa00aa80aa80aa >> { \[6410] , n2894, n2862, n3282, n3284, n3281 }; + assign n3281 = 64'h0000dd0ddd0ddd0d >> { n2867, \[15695] , n2900, ppeakp_8_8_, n2897, ppeaka_8_8_ }; + assign n3282 = 32'd2763306 >> { \[6350] , n2885, n2847, \[5135] , n3283_1 }; + assign n3283_1 = 64'h0ddd055501110111 >> { n2888_1, ppeaka_8_8_, n2890, \[14405] , ppeakb_8_8_, n2875 }; + assign n3284 = 64'h0000077707770777 >> { n2892, \[4475] , n2883_1, \[11225] , n2849, \[10175] }; + assign n1103 = 16'h55d5 >> { preset, n2906, \[8945] , n3286 }; + assign n3286 = 64'h00000ddd0ddd0ddd >> { n2898_1, \[7265] , n2872, \[7550] , n2904, \[5720] }; + assign n637 = 8'hd5 >> { n2874, \[11375] , n3288_1 }; + assign n3288_1 = 64'h80800080aaaa00aa >> { n2862, n2917, ppeaks_14_14_, n3289, n3292, n3293_1 }; + assign n3289 = 64'h0008080800888888 >> { n2853_1, n2849, \[6215] , \[10055] , n3290, n3291 }; + assign n3290 = 64'h0000077707770777 >> { \[9560] , n2890, \[14270] , n2913_1, n2838, \[8735] }; + assign n3291 = 64'h0000077707770777 >> { n2840, \[5435] , n2851, \[16070] , n2817, \[13070] }; + assign n3292 = 64'h0000077707770777 >> { n2916, \[10985] , n2883_1, \[12650] , n2847, \[7400] }; + assign n3293_1 = 64'h0000077707770777 >> { \[11900] , n2920, \[15410] , n2872, n2867, \[6725] }; + assign n533 = 64'hfffffbbbfbbbfbbb >> { \[14630] , n2872, n2867, \[13745] , n3300, n3295 }; + assign n3295 = 64'haaaaa222a222a222 >> { \[8225] , n2890, n2883_1, \[10970] , n3296, n2862 }; + assign n3296 = 64'h0008080800888888 >> { n2851, n2913_1, \[12905] , \[6140] , n3297, n3299 }; + assign n3297 = 32'd2763306 >> { n2853_1, \[4790] , n2847, \[6770] , n3298_1 }; + assign n3298_1 = 16'h0777 >> { \[11405] , n2849, n2817, \[15005] }; + assign n3299 = 64'h0000077707770777 >> { n2916, \[8255] , \[6785] , n2840, n2838, \[12830] }; + assign n3300 = 64'h00000ddd0ddd0ddd >> { \[11540] , n2920, n2874, \[9275] , n2917, ppeaks_7_7_ }; + assign n277 = 4'h7 >> { n3302, n3303_1 }; + assign n3302 = 64'h0ddd0ddd00000ddd >> { n2873_1, \[8855] , ppeaka_12_12_, n2928_1, n2923_1, ppeakp_12_12_ }; + assign n3303_1 = 64'h0000077707770777 >> { \[11030] , n2920, n2930, \[11210] , n2898_1, ppeakb_12_12_ }; + assign n1108 = 32'd1426346240 >> { pdata_2_2_, \[5780] , \[18246] , \[17453] , preset }; + assign n1113 = 16'h3120 >> { \[5795] , pdata_4_4_, preset, n4451 }; + assign n1118 = 16'h3120 >> { \[5810] , pdata_8_8_, preset, n4451 }; + assign n1123 = 16'h3120 >> { \[5825] , pdata_9_9_, preset, n2938_1 }; + assign n1128 = 16'h3120 >> { \[5840] , pdata_4_4_, preset, n2938_1 }; + assign n1133 = 16'h3120 >> { \[5855] , pdata_11_11_, preset, n2938_1 }; + assign n1138 = 32'd1426346240 >> { pdata_6_6_, \[5870] , \[17362] , \[17167] , preset }; + assign n1143 = 16'h3120 >> { \[5885] , pdata_5_5_, preset, n2943_1 }; + assign n1148 = 16'h3120 >> { \[5900] , pdata_0_0_, preset, n2947 }; + assign n1153 = 16'h3120 >> { \[5915] , pdata_7_7_, preset, n2947 }; + assign n1158 = 16'h3120 >> { \[5930] , pdata_11_11_, preset, n2947 }; + assign n1163 = 16'h3120 >> { \[5945] , pdata_12_12_, preset, n2952 }; + assign n1168 = 16'h3120 >> { \[5960] , pdata_7_7_, preset, n2954 }; + assign n1173 = 16'h3120 >> { \[5975] , pdata_14_14_, preset, n2954 }; + assign n1178 = 16'h3120 >> { \[5990] , pdata_9_9_, preset, n2954 }; + assign n1183_1 = 32'd1426346240 >> { pdata_8_8_, \[6005] , \[17310] , \[17388] , preset }; + assign n1188 = 32'd2934572096 >> { \[6020] , n3021, n3031, n2983_1, n2986 }; + assign n1193 = 16'hf888 >> { n2986, \[6035] , n3056, n2983_1 }; + assign n1198 = 16'h3120 >> { \[6050] , n3079, preset, n2970 }; + assign n1203 = 16'h3120 >> { \[6065] , n3081, preset, n2938_1 }; + assign n1208 = 16'h1302 >> { \[6080] , n3251, preset, n2938_1 }; + assign n1213 = 16'h3120 >> { \[6095] , n3326, preset, n2973_1 }; + assign n3326 = 32'd1443101782 >> { n3011, n3038_1, n3006, n3010, n3039 }; + assign n1218 = 16'h1302 >> { \[6110] , n3258, preset, n2969 }; + assign n1223 = 16'h1302 >> { \[6125] , n3243, preset, n2947 }; + assign n1228 = 16'h3120 >> { \[6140] , n3081, preset, n2947 }; + assign n1233 = 16'h3120 >> { \[6155] , n3056, preset, n2952 }; + assign n1238 = 16'h3120 >> { \[6170] , n3058_1, preset, n2954 }; + assign n1243 = 16'h3120 >> { \[6185] , n3054, preset, n2972 }; + assign n1248 = 32'd321978912 >> { \[6200] , n3021, n3031, preset, n2968_1 }; + assign n1253 = 16'h1302 >> { \[6215] , n3251, preset, n2968_1 }; + assign n1258 = 64'hffff288828882888 >> { n3136, \[6230] , n2968_1, ppeaka_4_4_, n3160, n3137 }; + assign n1263 = 16'h3120 >> { \[6245] , n3262, preset, n3100 }; + assign n1268 = 16'h1302 >> { \[6260] , n3198, preset, n3103_1 }; + assign n1273 = 16'h3120 >> { \[6275] , n3339, preset, n3102 }; + assign n3339 = 8'h46 >> { n3118_1, n4457, n3119 }; + assign n1278 = 16'h3120 >> { \[6290] , n3264, preset, n3102 }; + assign n1283 = 16'hf222 >> { n3195, \[6305] , n3198, n3196 }; + assign n3342 = 4'h1 >> { n3091, preset }; + assign n3343_1 = 4'h2 >> { preset, n3091 }; + assign n1293 = 32'd321978912 >> { \[6335] , n3345, ppeaka_14_14_, preset, n2968_1 }; + assign n3345 = 64'ha655aaa66555aa65 >> { n3165, n3171, n3180, n3179, n3175, n3185 }; + assign n1298 = 16'h1302 >> { \[6350] , n3267, preset, n3096 }; + assign n3347 = 64'h0000077707770777 >> { \[5855] , n2847, \[5255] , n2838, n2817, \[14480] }; + assign n3348_1 = 64'h0000077707770777 >> { \[4370] , n2874, \[4295] , n2872, n2867, \[15890] }; + assign n3349 = 64'h0000077707770777 >> { n2840, \[9140] , \[15290] , n2838, n2817, \[14465] }; + assign n3350 = 64'h0000077707770777 >> { \[5780] , n2874, \[15515] , n2872, n2867, \[7130] }; + assign n1308 = 32'd4285887861 >> { \[7895] , n2898_1, \[6410] , n2904, n3352 }; + assign n3352 = 32'd2004289399 >> { preset, \[5630] , n2906, \[6920] , n2872 }; + assign n569_1 = 64'hffffbbfbbbfbbbfb >> { n2872, \[15050] , n2917, ppeaks_15_15_, n3360, n3354 }; + assign n3354 = 64'hff00f700f700f700 >> { \[4730] , n2840, n2862, n3357, n3355, n3356 }; + assign n3355 = 16'h0777 >> { \[9395] , n2838, n2817, \[12365] }; + assign n3356 = 64'h0000077707770777 >> { n2916, \[6320] , \[11180] , n2849, n2847, \[10580] }; + assign n3357 = 32'd4292203989 >> { \[8150] , n2854, n2846, \[13880] , n3358_1 }; + assign n3358_1 = 32'd1381653 >> { n2891, \[4880] , n2852, \[15725] , n3359 }; + assign n3359 = 4'h8 >> { n2884, \[12425] }; + assign n3360 = 64'h0000077707770777 >> { n2920, \[11780] , \[15320] , n2874, n2867, \[7355] }; + assign n513_1 = 8'hd5 >> { n2867, \[14135] , n3362 }; + assign n3362 = 64'h80800080aaaa00aa >> { n2862, n2917, ppeaks_6_6_, n3363_1, n3366, n3367 }; + assign n3363_1 = 64'h0008080800888888 >> { n2883_1, n2890, \[8870] , \[11690] , n3365, n3364 }; + assign n3364 = 64'h0000077707770777 >> { \[13865] , n2913_1, \[11165] , n2849, n2851, \[8075] }; + assign n3365 = 64'h0000077707770777 >> { n2916, \[7625] , \[6110] , n2840, n2838, \[13085] }; + assign n3366 = 64'h0000077707770777 >> { n2853_1, \[5495] , \[10565] , n2847, n2817, \[16085] }; + assign n3367 = 64'h0000077707770777 >> { \[11300] , n2920, n2874, \[8615] , n2872, \[14210] }; + assign n405 = 4'h7 >> { n3369, n3370 }; + assign n3369 = 64'h00000ddd0ddd0ddd >> { n2930, \[10955] , ppeakb_13_13_, n2898_1, n2923_1, ppeakp_13_13_ }; + assign n3370 = 64'h0000770777077707 >> { \[10760] , n2920, n2873_1, \[9530] , n2928_1, ppeaka_13_13_ }; + assign n1313 = 32'd1426346240 >> { pdata_12_12_, \[6470] , \[18246] , \[17453] , preset }; + assign n1318 = 16'h3120 >> { \[6485] , pdata_5_5_, preset, n4451 }; + assign n1323 = 16'h3120 >> { \[6500] , pdata_7_7_, preset, n4451 }; + assign n1328 = 16'h3120 >> { \[6515] , pdata_10_10_, preset, n2938_1 }; + assign n1333 = 16'h3120 >> { \[6530] , pdata_3_3_, preset, n2938_1 }; + assign n1338 = 16'h3120 >> { \[6545] , pdata_12_12_, preset, n2938_1 }; + assign n1343 = 32'd1426346240 >> { pdata_5_5_, \[6560] , \[17362] , \[17167] , preset }; + assign n1348 = 16'h3120 >> { \[6575] , pdata_6_6_, preset, n2943_1 }; + assign n1353 = 16'h3120 >> { \[6590] , pdata_15_15_, preset, n2943_1 }; + assign n1358 = 16'h3120 >> { \[6605] , pdata_8_8_, preset, n2947 }; + assign n1363 = 16'h3120 >> { \[6620] , pdata_13_13_, preset, n2952 }; + assign n1368 = 16'h3120 >> { \[6635] , pdata_6_6_, preset, n2954 }; + assign n1373 = 16'h3120 >> { \[6650] , pdata_15_15_, preset, n2954 }; + assign n1378 = 16'h3120 >> { \[6665] , pdata_8_8_, preset, n2954 }; + assign n1383 = 32'd1426346240 >> { pdata_9_9_, \[6680] , \[17310] , \[17388] , preset }; + assign n1388 = 16'hf222 >> { n2986, \[6695] , n3077, n2983_1 }; + assign n1393_1 = 16'hf888 >> { n2986, \[6710] , n3052, n2983_1 }; + assign n1398_1 = 16'h1302 >> { \[6725] , n3251, preset, n2970 }; + assign n1403_1 = 16'h1302 >> { \[6740] , n3258, preset, n2938_1 }; + assign n1413_1 = 16'h3120 >> { \[6770] , n3081, preset, n2973_1 }; + assign n1418_1 = 16'h3120 >> { \[6785] , n3081, preset, n2969 }; + assign n1423_1 = 16'h3120 >> { \[6815] , n3326, preset, n2947 }; + assign n1428_1 = 16'h3120 >> { \[6830] , n3052, preset, n2952 }; + assign n1433_1 = 32'd321978912 >> { \[6845] , n3021, n3031, preset, n2954 }; + assign n1438_1 = 32'd823336962 >> { \[6860] , n3000, n2988_1, preset, n2954 }; + assign n1443_1 = 16'h3120 >> { \[6875] , n3058_1, preset, n2968_1 }; + assign n1448_1 = 16'h3120 >> { \[6890] , n3079, preset, n2968_1 }; + assign n1453_1 = 16'hf222 >> { n3136, \[6905] , n3274, n3137 }; + assign n1458_1 = 16'h1302 >> { \[6920] , n3267, preset, n3100 }; + assign n1463_1 = 16'h3120 >> { \[6935] , n3339, preset, n3103_1 }; + assign n1468_1 = 16'h1302 >> { \[6950] , n3198, preset, n3102 }; + assign n1473_1 = 16'h3120 >> { \[6965] , n3139, preset, n3102 }; + assign n1478_1 = 16'hf888 >> { n3195, \[6980] , n3404, n3196 }; + assign n3404 = 8'h96 >> { n3109, n3113_1, n3125 }; + assign n1483_1 = 16'hf222 >> { n3342, \[6995] , n3274, n3343_1 }; + assign n1488_1 = 64'hffffffff88282822 >> { n3407, n3164, n3190, n3185, n3181, n3409 }; + assign n3407 = 4'h8 >> { n3408_1, \[7010] }; + assign n3408_1 = 4'h1 >> { n2968_1, preset }; + assign n3409 = 4'h2 >> { preset, n2968_1 }; + assign n1493_1 = 16'h3120 >> { \[7025] , n3262, preset, n3096 }; + assign n1498_1 = 32'd4285887861 >> { \[5960] , n2898_1, \[7055] , n2904, n3412 }; + assign n3412 = 32'd2004289399 >> { preset, n2906, \[11240] , \[6245] , n2872 }; + assign n361 = 8'hd5 >> { n2874, \[4640] , n3414 }; + assign n3414 = 64'h80800080aaaa00aa >> { n2862, n2917, ppeaks_12_12_, n3415, n3418_1, n3419 }; + assign n3415 = 64'h0008080800888888 >> { n2849, n2890, \[9845] , \[4820] , n3417, n3416 }; + assign n3416 = 64'h0000077707770777 >> { n2913_1, \[15065] , n2853_1, \[10625] , n2838, \[7460] }; + assign n3417 = 64'h0000077707770777 >> { n2840, \[9365] , n2851, \[11615] , n2817, \[13775] }; + assign n3418_1 = 64'h0000077707770777 >> { n2916, \[10415] , n2883_1, \[14660] , n2847, \[8675] }; + assign n3419 = 64'h0000077707770777 >> { n2920, \[9680] , \[12395] , n2872, n2867, \[5360] }; + assign n389 = 64'hfffffbbbfbbbfbbb >> { \[12380] , n2872, n2867, \[16055] , n3426, n3421 }; + assign n3421 = 64'haaaaa222a222a222 >> { n2913_1, \[12005] , n2817, \[14570] , n3422, n2862 }; + assign n3422 = 64'h0008080800888888 >> { n2838, n2916, \[12920] , \[15020] , n3423_1, n3425 }; + assign n3423_1 = 32'd2763306 >> { n2849, \[4805] , n2853_1, \[8120] , n3424 }; + assign n3424 = 16'h0777 >> { \[6305] , n2883_1, n2840, \[8045] }; + assign n3425 = 64'h0000077707770777 >> { \[9830] , n2890, \[8660] , n2847, n2851, \[11150] }; + assign n3426 = 64'h00000ddd0ddd0ddd >> { n2920, \[9665] , \[4625] , n2874, n2917, ppeaks_1_1_ }; + assign n381 = 4'h7 >> { n3428_1, n3429 }; + assign n3428_1 = 64'h00000ddd0ddd0ddd >> { \[15785] , n2920, n2930, \[11195] , n2923_1, ppeakp_3_3_ }; + assign n3429 = 64'h0777077700000777 >> { n2873_1, \[7565] , n2928_1, ppeaka_3_3_, n2898_1, ppeakb_3_3_ }; + assign n1503_1 = 32'd1426346240 >> { pdata_7_7_, \[7115] , \[18246] , \[17453] , preset }; + assign n1508_1 = 16'h3120 >> { \[7130] , pdata_2_2_, preset, n4451 }; + assign n1513_1 = 16'h3120 >> { \[7145] , pdata_11_11_, preset, n2938_1 }; + assign n1518_1 = 16'h3120 >> { \[7160] , pdata_6_6_, preset, n2938_1 }; + assign n1523_1 = 32'd1426346240 >> { pdata_1_1_, \[7175] , \[17362] , \[17167] , preset }; + assign n1528_1 = 32'd1426346240 >> { pdata_12_12_, \[7190] , \[17362] , \[17167] , preset }; + assign n1533_1 = 32'd1426346240 >> { pdata_15_15_, \[7205] , \[17362] , \[17167] , preset }; + assign n1538_1 = 16'h3120 >> { \[7220] , pdata_10_10_, preset, n2943_1 }; + assign n1543_1 = 16'h3120 >> { \[7235] , pdata_5_5_, preset, n2947 }; + assign n1548_1 = 16'h3120 >> { \[7250] , pdata_14_14_, preset, n2952 }; + assign n1553_1 = 16'h3120 >> { \[7265] , pdata_9_9_, preset, n2954 }; + assign n1558_1 = 16'h3120 >> { \[7280] , pdata_4_4_, preset, n2954 }; + assign n1563_1 = 16'h3120 >> { \[7295] , pdata_15_15_, preset, n2954 }; + assign n1568_1 = 32'd1426346240 >> { pdata_2_2_, \[7310] , \[17310] , \[17388] , preset }; + assign n1573_1 = 32'd1426346240 >> { pdata_13_13_, \[7325] , \[17310] , \[17388] , preset }; + assign n1578_1 = 16'hf888 >> { n2986, \[7340] , n3326, n2983_1 }; + assign n1588 = 16'h3120 >> { \[7370] , n3074, preset, n2938_1 }; + assign n1593 = 64'h1331311302202002 >> { \[7385] , n3021, n3027, n3031, preset, n2973_1 }; + assign n1598 = 16'h1302 >> { \[7400] , n3251, preset, n2973_1 }; + assign n1603 = 16'h1302 >> { \[7415] , n3243, preset, n2969 }; + assign n1608 = 16'h3120 >> { \[7430] , n3052, preset, n2969 }; + assign n1613 = 16'h3120 >> { \[7445] , n3054, preset, n2947 }; + assign n1618 = 32'd823336962 >> { \[7460] , n3000, n2988_1, preset, n2952 }; + assign n1623 = 16'h1302 >> { \[7475] , n3258, preset, n2954 }; + assign n1628 = 16'h1302 >> { \[7490] , n3243, preset, n2972 }; + assign n1633 = 16'h3120 >> { \[7505] , n3052, preset, n2972 }; + assign n1638 = 16'h3120 >> { \[7520] , n3326, preset, n2968_1 }; + assign n1643 = 16'hf888 >> { n3136, \[7535] , n3404, n3137 }; + assign n1648 = 16'h1302 >> { \[7550] , n3192, preset, n3100 }; + assign n1653 = 16'h3120 >> { \[7565] , n3194, preset, n3103_1 }; + assign n1658 = 32'd321978912 >> { \[7580] , n3345, n3190, preset, n3103_1 }; + assign n1663 = 16'hf222 >> { n3161, \[7595] , n3267, n3162 }; + assign n1668 = 16'hf888 >> { n3342, \[7625] , n3085, n3343_1 }; + assign n1673 = 16'h3120 >> { \[7640] , n3339, preset, n3101 }; + assign n1678 = 16'h3120 >> { \[7655] , n3264, preset, n3101 }; + assign n1683 = 16'h1302 >> { \[7670] , n3274, preset, n2968_1 }; + assign n1688 = 32'd4285887861 >> { \[6635] , n2898_1, \[7685] , n2904, n3467 }; + assign n3467 = 32'd2004289399 >> { preset, n2906, \[10430] , \[12410] , n2872 }; + assign n441 = 64'hfffffbbbfbbbfbbb >> { \[12620] , n2872, n2867, \[6050] , n3474, n3469 }; + assign n3469 = 64'hff007f007f007f00 >> { \[8885] , n2890, n2862, n3472, n3470, n3473_1 }; + assign n3470 = 32'd2763306 >> { n2883_1, \[14240] , n2853_1, \[10340] , n3471 }; + assign n3471 = 16'h0777 >> { \[8705] , n2840, n2851, \[14990] }; + assign n3472 = 64'h0000077707770777 >> { n2916, \[10700] , \[8090] , n2838, n2817, \[12815] }; + assign n3473_1 = 64'h0000077707770777 >> { n2913_1, \[14690] , \[6890] , n2849, n2847, \[8030] }; + assign n3474 = 64'h00000ddd0ddd0ddd >> { n2920, \[12035] , n2874, \[5345] , n2917, ppeaks_13_13_ }; + assign n485 = 4'h7 >> { n3476, n3477 }; + assign n3476 = 64'h00000ddd0ddd0ddd >> { n2920, \[14285] , ppeaka_7_7_, n2928_1, n2923_1, ppeakp_7_7_ }; + assign n3477 = 64'h0777077700000777 >> { n2873_1, \[9815] , n2930, \[8900] , n2898_1, ppeakb_7_7_ }; + assign n353_1 = 4'h7 >> { n3479, n3480 }; + assign n3479 = 64'h00000ddd0ddd0ddd >> { n2920, ndout, ppeaka_2_2_, n2928_1, n2923_1, ppeakp_2_2_ }; + assign n3480 = 64'h0777077700000777 >> { n2873_1, \[8195] , n2930, \[10940] , n2898_1, ppeakb_2_2_ }; + assign n1693 = 32'd1426346240 >> { pdata_6_6_, \[7745] , \[18246] , \[17453] , preset }; + assign n1698 = 16'h3120 >> { \[7760] , pdata_3_3_, preset, n4451 }; + assign n1703 = 16'h3120 >> { \[7775] , pdata_12_12_, preset, n2938_1 }; + assign n1708 = 16'h3120 >> { \[7790] , pdata_5_5_, preset, n2938_1 }; + assign n1713 = 32'd1426346240 >> { pdata_2_2_, \[7805] , \[17362] , \[17167] , preset }; + assign n1718 = 32'd1426346240 >> { pdata_11_11_, \[7820] , \[17362] , \[17167] , preset }; + assign n1723 = 16'h3120 >> { \[7835] , pdata_0_0_, preset, n2943_1 }; + assign n1728 = 16'h3120 >> { \[7850] , pdata_9_9_, preset, n2943_1 }; + assign n1733 = 16'h3120 >> { \[7865] , pdata_6_6_, preset, n2947 }; + assign n1738 = 16'h3120 >> { \[7880] , pdata_15_15_, preset, n2952 }; + assign n1743 = 16'h3120 >> { \[7895] , pdata_8_8_, preset, n2954 }; + assign n1748 = 16'h3120 >> { \[7910] , pdata_5_5_, preset, n2954 }; + assign n1753 = 16'h3120 >> { \[7925] , pdata_14_14_, preset, n2954 }; + assign n1758 = 32'd1426346240 >> { pdata_3_3_, \[7940] , \[17310] , \[17388] , preset }; + assign n1763 = 32'd1426346240 >> { pdata_12_12_, \[7955] , \[17310] , \[17388] , preset }; + assign n1768 = 16'hf888 >> { n2986, \[7970] , n3074, n2983_1 }; + assign n1773 = 16'h3120 >> { \[8000] , n3326, preset, n2938_1 }; + assign n1778 = 16'h3120 >> { \[8015] , n3058_1, preset, n2973_1 }; + assign n1783 = 16'h3120 >> { \[8030] , n3079, preset, n2973_1 }; + assign n1788 = 16'h1302 >> { \[8045] , n2962, preset, n2969 }; + assign n1793 = 16'h3120 >> { \[8060] , n3056, preset, n2969 }; + assign n1798_1 = 16'h1302 >> { \[8075] , n3258, preset, n2947 }; + assign n1803 = 16'h3120 >> { \[8090] , n3079, preset, n2952 }; + assign n1808 = 16'h3120 >> { \[8105] , n3054, preset, n2954 }; + assign n1813 = 16'h1302 >> { \[8120] , n2962, preset, n2972 }; + assign n1818 = 16'h3120 >> { \[8135] , n3056, preset, n2972 }; + assign n1823 = 64'hffffffff28282822 >> { n3509, n3059, n3071, n3066, n4455, n3508_1 }; + assign n3508_1 = 4'h2 >> { preset, n2972 }; + assign n3509 = 8'h02 >> { n2972, preset, \[8150] }; + assign n1828 = 16'hf888 >> { n3136, \[8165] , n3194, n3137 }; + assign n1833 = 16'h3120 >> { \[8180] , n3139, preset, n3100 }; + assign n1838 = 16'h3120 >> { \[8195] , n3404, preset, n3103_1 }; + assign n1843 = 64'hffffffff88282822 >> { n3515, n3164, n3190, n3185, n3181, n3514 }; + assign n3514 = 4'h2 >> { preset, n3103_1 }; + assign n3515 = 8'h02 >> { n3103_1, preset, \[8210] }; + assign n1848 = 16'hf888 >> { n3161, \[8225] , n3262, n3162 }; + assign n1853 = 16'hf888 >> { n3195, \[8240] , n3339, n3196 }; + assign n1858 = 16'hf888 >> { n3342, \[8255] , n3262, n3343_1 }; + assign n1863 = 16'h1302 >> { \[8285] , n3201, preset, n3101 }; + assign n1868 = 32'd321978912 >> { \[8300] , n3160, ppeaka_4_4_, preset, n2968_1 }; + assign n1873 = 16'h3120 >> { \[8315] , n3345, preset, n3096 }; + assign n1878 = 16'h55d5 >> { preset, n2906, \[10715] , n3523_1 }; + assign n3523_1 = 64'h00000ddd0ddd0ddd >> { n2898_1, \[4565] , n2872, \[12635] , n2904, \[8330] }; + assign n445 = 8'hd5 >> { n2867, \[15350] , n3525 }; + assign n3525 = 64'h80800080aaaa00aa >> { n2862, n2917, ppeaks_3_3_, n3526, n3529, n3530 }; + assign n3526 = 64'h0008080800888888 >> { n2847, n2913_1, \[14255] , \[7385] , n3528, n3527 }; + assign n3527 = 64'h0000077707770777 >> { n2883_1, \[4910] , \[6200] , n2849, n2853_1, \[10610] }; + assign n3528 = 64'h0000077707770777 >> { n2890, \[5570] , n2851, \[8720] , n2817, \[12575] }; + assign n3529 = 64'h0000077707770777 >> { n2916, \[12455] , \[9350] , n2840, n2838, \[14180] }; + assign n3530 = 64'h0000077707770777 >> { n2920, \[12155] , n2874, \[6020] , n2872, \[12845] }; + assign n509 = 4'h7 >> { n3532, n3533 }; + assign n3532 = 64'h00000ddd0ddd0ddd >> { n2930, \[5600] , ppeakb_8_8_, n2898_1, n2923_1, ppeakp_8_8_ }; + assign n3533 = 64'h0000770777077707 >> { \[13895] , n2920, n2873_1, \[10655] , n2928_1, ppeaka_8_8_ }; + assign n317 = 4'h7 >> { n3535, n3536 }; + assign n3535 = 64'h00000ddd0ddd0ddd >> { n2920, \[4970] , ppeakb_1_1_, n2898_1, n2923_1, ppeakp_1_1_ }; + assign n3536 = 64'h0777077700000777 >> { n2873_1, \[6260] , ppeaka_1_1_, n2928_1, n2930, \[6950] }; + assign n1883 = 32'd1426346240 >> { pdata_9_9_, \[8390] , \[18246] , \[17453] , preset }; + assign n1888 = 16'h3120 >> { \[8405] , pdata_0_0_, preset, n4451 }; + assign n1893 = 16'h3120 >> { \[8420] , pdata_13_13_, preset, n2938_1 }; + assign n1898 = 16'h3120 >> { \[8435] , pdata_8_8_, preset, n2938_1 }; + assign n1903 = 16'h3120 >> { \[8450] , pdata_15_15_, preset, n2938_1 }; + assign n1908 = 32'd1426346240 >> { pdata_10_10_, \[8465] , \[17362] , \[17167] , preset }; + assign n1913 = 16'h3120 >> { \[8480] , pdata_1_1_, preset, n2943_1 }; + assign n1918 = 16'h3120 >> { \[8495] , pdata_12_12_, preset, n2943_1 }; + assign n1923 = 16'h3120 >> { \[8510] , pdata_3_3_, preset, n2947 }; + assign n1928 = 16'h3120 >> { \[8525] , pdata_0_0_, preset, n2954 }; + assign n1933 = 16'h3120 >> { \[8540] , pdata_11_11_, preset, n2954 }; + assign n1938 = 16'h3120 >> { \[8555] , pdata_2_2_, preset, n2954 }; + assign n1943 = 16'h3120 >> { \[8570] , pdata_13_13_, preset, n2954 }; + assign n1948 = 32'd1426346240 >> { pdata_4_4_, \[8585] , \[17310] , \[17388] , preset }; + assign n1953 = 32'd1426346240 >> { pdata_15_15_, \[8600] , \[17310] , \[17388] , preset }; + assign n1958 = 16'hf222 >> { n2986, \[8615] , n3258, n2983_1 }; + assign n1963 = 16'h1302 >> { \[8630] , n3243, preset, n2938_1 }; + assign n1968 = 16'h3120 >> { \[8645] , n3052, preset, n2938_1 }; + assign n1973 = 16'h1302 >> { \[8660] , n2962, preset, n2973_1 }; + assign n1978 = 32'd823336962 >> { \[8675] , n3000, n2988_1, preset, n2973_1 }; + assign n1983 = 16'h1302 >> { \[8690] , n3077, preset, n2969 }; + assign n1988 = 16'h3120 >> { \[8705] , n3079, preset, n2969 }; + assign n1993 = 32'd321978912 >> { \[8720] , n3021, n3031, preset, n2947 }; + assign n1998 = 16'h1302 >> { \[8735] , n3251, preset, n2952 }; + assign n2003 = 16'h3120 >> { \[8750] , n3326, preset, n2954 }; + assign n3562 = 4'h2 >> { preset, n2954 }; + assign n2013 = 16'h3120 >> { \[8780] , n3074, preset, n2972 }; + assign n2018 = 16'h3120 >> { \[8810] , n3056, preset, n2968_1 }; + assign n2023 = 16'h3120 >> { \[8825] , n3264, preset, n3100 }; + assign n2028 = 16'h1302 >> { \[8840] , n3274, preset, n3103_1 }; + assign n2033 = 16'h1302 >> { \[8855] , n3201, preset, n3103_1 }; + assign n2038 = 16'hf888 >> { n3161, \[8870] , n3085, n3162 }; + assign n2043 = 16'hf222 >> { n3161, \[8885] , n3272, n3162 }; + assign n2048 = 16'h3120 >> { \[8900] , n3262, preset, n3102 }; + assign n2053 = 16'hf222 >> { n3342, \[8915] , n3267, n3343_1 }; + assign n2058 = 16'h3120 >> { \[8930] , n3404, preset, n3101 }; + assign n2063 = 16'h1302 >> { \[8945] , n3192, preset, n3101 }; + assign n2068 = 16'h3120 >> { \[8960] , n3194, preset, n2968_1 }; + assign n2073 = 16'h3120 >> { \[8975] , n3160, preset, n3096 }; + assign n657 = 64'hfffffbbbfbbbfbbb >> { n2872, \[13115] , n2867, \[4655] , n3582, n3577 }; + assign n3577 = 64'haaaaa222a222a222 >> { n2849, \[5525] , n2853_1, \[7505] , n3578_1, n2862 }; + assign n3578_1 = 64'h0008080800888888 >> { n2817, n2851, \[11390] , \[13415] , n3581, n3579 }; + assign n3579 = 32'd2763306 >> { \[13490] , n2883_1, n2847, \[9335] , n3580 }; + assign n3580 = 16'h0777 >> { \[10130] , n2916, n2840, \[7430] }; + assign n3581 = 64'h0000077707770777 >> { n2890, \[10115] , n2913_1, \[12125] , n2838, \[6830] }; + assign n3582 = 64'h00000ddd0ddd0ddd >> { n2920, \[10490] , n2874, \[6710] , n2917, ppeaks_11_11_ }; + assign n421 = 64'hfffffbbbfbbbfbbb >> { \[13100] , n2872, n2867, \[15710] , n3589, n3584 }; + assign n3584 = 64'hff007f007f007f00 >> { \[10100] , n2890, n2862, n3587, n3585, n3588_1 }; + assign n3585 = 32'd2763306 >> { n2916, \[12680] , n2840, \[8690] , n3586 }; + assign n3586 = 16'h0777 >> { \[15425] , n2913_1, n2838, \[14600] }; + assign n3587 = 64'h0000077707770777 >> { n2883_1, \[6980] , n2851, \[10880] , n2817, \[14150] }; + assign n3588_1 = 64'h0000077707770777 >> { n2849, \[5510] , n2853_1, \[10325] , n2847, \[9320] }; + assign n3589 = 64'h00000ddd0ddd0ddd >> { n2920, \[10475] , n2874, \[6695] , n2917, ppeaks_2_2_ }; + assign n525 = 4'h7 >> { n3591, n3592 }; + assign n3591 = 64'h00000ddd0ddd0ddd >> { n2920, \[11750] , n2930, \[4895] , n2923_1, ppeakp_9_9_ }; + assign n3592 = 64'h0777077700000777 >> { n2873_1, \[10370] , n2928_1, ppeaka_9_9_, n2898_1, ppeakb_9_9_ }; + assign n281 = 4'h7 >> { n3594, n3595 }; + assign n3594 = 64'h00000ddd0ddd0ddd >> { n2930, \[6275] , ppeakb_0_0_, n2898_1, n2923_1, ppeakp_0_0_ }; + assign n3595 = 64'h0000770777077707 >> { \[5675] , n2920, n2873_1, \[6935] , n2928_1, ppeaka_0_0_ }; + assign n2078 = 32'd1426346240 >> { pdata_8_8_, \[9050] , \[18246] , \[17453] , preset }; + assign n2083 = 16'h3120 >> { \[9065] , pdata_1_1_, preset, n4451 }; + assign n2088 = 16'h3120 >> { \[9080] , pdata_14_14_, preset, n2938_1 }; + assign n2093 = 16'h3120 >> { \[9095] , pdata_7_7_, preset, n2938_1 }; + assign n2098 = 32'd1426346240 >> { pdata_0_0_, \[9110] , \[17362] , \[17167] , preset }; + assign n2103 = 32'd1426346240 >> { pdata_9_9_, \[9125] , \[17362] , \[17167] , preset }; + assign n2108 = 16'h3120 >> { \[9140] , pdata_2_2_, preset, n2943_1 }; + assign n2113 = 16'h3120 >> { \[9155] , pdata_11_11_, preset, n2943_1 }; + assign n2118 = 16'h3120 >> { \[9170] , pdata_4_4_, preset, n2947 }; + assign n2123 = 16'h3120 >> { \[9185] , pdata_1_1_, preset, n2954 }; + assign n2128 = 16'h3120 >> { \[9200] , pdata_10_10_, preset, n2954 }; + assign n2133 = 16'h3120 >> { \[9215] , pdata_3_3_, preset, n2954 }; + assign n2138 = 16'h3120 >> { \[9230] , pdata_12_12_, preset, n2954 }; + assign n2143 = 32'd1426346240 >> { pdata_5_5_, \[9245] , \[17310] , \[17388] , preset }; + assign n2148 = 32'd1426346240 >> { pdata_14_14_, \[9260] , \[17310] , \[17388] , preset }; + assign n2153 = 16'hf888 >> { n2986, \[9275] , n3081, n2983_1 }; + assign n2158 = 16'h1302 >> { \[9290] , n2962, preset, n2938_1 }; + assign n2163 = 16'h3120 >> { \[9305] , n3056, preset, n2938_1 }; + assign n2168 = 16'h1302 >> { \[9320] , n3077, preset, n2973_1 }; + assign n2173 = 16'h3120 >> { \[9335] , n3052, preset, n2973_1 }; + assign n2178 = 32'd321978912 >> { \[9350] , n3021, n3031, preset, n2969 }; + assign n2183 = 32'd823336962 >> { \[9365] , n3000, n2988_1, preset, n2969 }; + assign n2188_1 = 16'h3120 >> { \[9380] , n3058_1, preset, n2947 }; + assign n2193_1 = 32'd4294910594 >> { n3620, n3066, n3059, n4455, n4178 }; + assign n3620 = 8'h02 >> { n2952, preset, \[9395] }; + assign n2198_1 = 16'h3120 >> { \[9410] , n3081, preset, n2954 }; + assign n2203_1 = 16'h3120 >> { \[9440] , n3326, preset, n2972 }; + assign n2208_1 = 16'h1302 >> { \[9455] , n3243, preset, n2968_1 }; + assign n2213_1 = 16'h3120 >> { \[9470] , n3074, preset, n2968_1 }; + assign n2218_1 = 16'hf222 >> { n3136, \[9485] , n3198, n3137 }; + assign n2223_1 = 16'h1302 >> { \[9500] , n3201, preset, n3100 }; + assign n2228_1 = 64'h1331313102202020 >> { \[9515] , n2968_1, ppeaka_4_4_, n3160, preset, n3103_1 }; + assign n2233_1 = 16'h1302 >> { \[9530] , n3272, preset, n3103_1 }; + assign n2238_1 = 16'hf222 >> { n3161, \[9545] , n3274, n3162 }; + assign n2243_1 = 16'hf888 >> { n3161, \[9560] , n3345, n3162 }; + assign n2248_1 = 16'h3120 >> { \[9575] , n3085, preset, n3102 }; + assign n2253_1 = 16'hf222 >> { n3342, \[9590] , n3192, n3343_1 }; + assign n2258_1 = 16'h1302 >> { \[9605] , n3199, preset, n3101 }; + assign n2263_1 = 16'h3120 >> { \[9620] , n3139, preset, n3101 }; + assign n2268 = 16'h3120 >> { \[9635] , n3404, preset, n2968_1 }; + assign n2273 = 16'h3120 >> { \[9650] , n3264, preset, n2968_1 }; + assign n2278 = 32'd1426346240 >> { pdata_1_1_, \[9665] , \[17505] , \[17414] , preset }; + assign n2283 = 32'd1426346240 >> { pdata_12_12_, \[9680] , \[17505] , \[17414] , preset }; + assign n393_1 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_6_6_, n2873_1, \[12185] , n3640 }; + assign n3640 = 32'd539011104 >> { n2835, ppeaki_14_14_, ppeaki_10_10_, n3641, n2862 }; + assign n3641 = 4'h8 >> { n2829, n2831 }; + assign n2288 = 16'h3120 >> { \[9710] , pdata_2_2_, preset, n2954 }; + assign n2293 = 16'h1302 >> { \[9725] , n3077, preset, n2938_1 }; + assign n2298 = 16'h3120 >> { \[9740] , n3079, preset, n2938_1 }; + assign n2303 = 16'h3120 >> { \[9770] , n3056, preset, n2954 }; + assign n2308 = 16'h3120 >> { \[9785] , n3058_1, preset, n2972 }; + assign n2313 = 16'h1302 >> { \[9800] , n3272, preset, n3100 }; + assign n2318 = 16'h3120 >> { \[9815] , n3262, preset, n3103_1 }; + assign n2323 = 16'hf222 >> { n3161, \[9830] , n3198, n3162 }; + assign n2328 = 16'hf222 >> { n3161, \[9845] , n3201, n3162 }; + assign n2333 = 16'hf888 >> { n3342, \[9860] , n3139, n3343_1 }; + assign n2338 = 64'h1331313102202020 >> { \[9875] , n2968_1, ppeaka_4_4_, n3160, preset, n3101 }; + assign n2343 = 64'h4414141155555555 >> { n3101, n3164, n3190, n3185, n3181, n3654 }; + assign n3654 = 8'hab >> { n3101, \[9890] , preset }; + assign n2348 = 16'h1302 >> { \[9905] , n3192, preset, n2968_1 }; + assign n2353 = 16'h3120 >> { \[9920] , n3194, preset, n3096 }; + assign n2358 = 32'd1426346240 >> { pdata_0_0_, \[9935] , \[17505] , \[17414] , preset }; + assign n2363 = 32'd1426346240 >> { pdata_6_6_, \[9950] , \[18142] , \[18220] , preset }; + assign n2368 = 16'h3120 >> { \[9980] , pdata_12_12_, preset, n2954 }; + assign n2373 = 32'd321978912 >> { \[9995] , n3021, n3031, preset, n2938_1 }; + assign n2378 = 32'd823336962 >> { \[10010] , n3000, n2988_1, preset, n2938_1 }; + assign n2383 = 16'h1302 >> { \[10025] , n3243, preset, n2954 }; + assign n2388 = 16'h3120 >> { \[10040] , n3074, preset, n2954 }; + assign n2393 = 16'h1302 >> { \[10055] , n3251, preset, n2972 }; + assign n2398 = 32'd321978912 >> { \[10070] , n3345, n3190, preset, n3100 }; + assign n2403 = 16'h3120 >> { \[10085] , n3085, preset, n3103_1 }; + assign n2408 = 16'hf888 >> { n3161, \[10100] , n3404, n3162 }; + assign n2413 = 16'hf888 >> { n3161, \[10115] , n3264, n3162 }; + assign n2418 = 16'hf888 >> { n3342, \[10130] , n3264, n3343_1 }; + assign n2423 = 16'h3120 >> { \[10145] , n3194, preset, n3101 }; + assign n2428 = 16'h1302 >> { \[10175] , n3267, preset, n2968_1 }; + assign n2433 = 16'h1302 >> { \[10190] , n3272, preset, n3096 }; + assign n2438 = 32'd1426346240 >> { pdata_10_10_, \[10205] , \[17505] , \[17414] , preset }; + assign n2443 = 32'd1426346240 >> { pdata_5_5_, \[10220] , \[18142] , \[18220] , preset }; + assign n289 = 32'd1145324788 >> { preset, n2857, ppeaki_15_15_, \[12200] , n2873_1 }; + assign n333_1 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_4_4_, n2873_1, \[11930] , n3677 }; + assign n3677 = 32'd539011104 >> { n2835, ppeaki_12_12_, ppeaki_8_8_, n3641, n2862 }; + assign n2448 = 16'h3120 >> { \[10265] , pdata_6_6_, preset, n2954 }; + assign n2453 = 16'h3120 >> { \[10280] , n3054, preset, n2973_1 }; + assign n2458 = 16'h1302 >> { \[10310] , n2962, preset, n2954 }; + assign n2463 = 16'h1302 >> { \[10325] , n3077, preset, n2972 }; + assign n2468 = 16'h3120 >> { \[10340] , n3079, preset, n2972 }; + assign n2473 = 64'h88282822aaaaaaaa >> { n3100, n3164, n3190, n3185, n3181, n3684 }; + assign n3684 = 8'h54 >> { \[10355] , n3100, preset }; + assign n2478 = 16'h1302 >> { \[10370] , n3192, preset, n3103_1 }; + assign n2483 = 16'hf888 >> { n3161, \[10400] , n3139, n3162 }; + assign n2488 = 16'hf222 >> { n3342, \[10415] , n3201, n3343_1 }; + assign n2493 = 16'h3120 >> { \[10430] , n3085, preset, n3101 }; + assign n2498 = 16'h1302 >> { \[10445] , n3272, preset, n3101 }; + assign n2503 = 16'h3120 >> { \[10460] , n3262, preset, n2968_1 }; + assign n2508 = 32'd1426346240 >> { pdata_2_2_, \[10475] , \[17505] , \[17414] , preset }; + assign n2513 = 32'd1426346240 >> { pdata_11_11_, \[10490] , \[17505] , \[17414] , preset }; + assign n2518 = 32'd1426346240 >> { pdata_4_4_, \[10505] , \[18142] , \[18220] , preset }; + assign n449 = 32'd1145324788 >> { preset, n2857, ppeaki_14_14_, \[12080] , n2873_1 }; + assign n369 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_5_5_, n2873_1, \[11810] , n3696 }; + assign n3696 = 32'd539011104 >> { n2835, ppeaki_13_13_, ppeaki_9_9_, n3641, n2862 }; + assign n2523 = 32'd1426346240 >> { pdata_0_0_, \[10550] , \[17310] , \[17388] , preset }; + assign n2528 = 16'h1302 >> { \[10565] , n3258, preset, n2973_1 }; + assign n2533 = 64'hffffffff28282822 >> { n3701, n3059, n3071, n3066, n4455, n3700 }; + assign n3700 = 4'h2 >> { preset, n2973_1 }; + assign n3701 = 8'h02 >> { n2973_1, preset, \[10580] }; + assign n2538 = 16'h3120 >> { \[10595] , n3052, preset, n2954 }; + assign n2543 = 64'h1331311302202002 >> { \[10610] , n3021, n3027, n3031, preset, n2972 }; + assign n2548 = 32'd823336962 >> { \[10625] , n3000, n2988_1, preset, n2972 }; + assign n2553 = 16'h1302 >> { \[10655] , n3267, preset, n3103_1 }; + assign n2558 = 16'hf888 >> { n3161, \[10670] , n3339, n3162 }; + assign n2563 = 16'hf222 >> { n3161, \[10685] , n3192, n3162 }; + assign n2568 = 16'hf222 >> { n3342, \[10700] , n3272, n3343_1 }; + assign n2573 = 16'h1302 >> { \[10715] , n3274, preset, n3101 }; + assign n2578 = 32'd321978912 >> { \[10730] , n3345, n3190, preset, n3101 }; + assign n2583 = 16'h3120 >> { \[10745] , n3085, preset, n2968_1 }; + assign n2588 = 32'd1426346240 >> { pdata_13_13_, \[10760] , \[17843] , \[17791] , preset }; + assign n2593 = 32'd1426346240 >> { pdata_8_8_, \[10775] , \[17505] , \[17414] , preset }; + assign n2598 = 32'd1426346240 >> { pdata_3_3_, \[10790] , \[18142] , \[18220] , preset }; + assign n2603 = 32'd1426346240 >> { pdata_1_1_, \[10805] , \[17635] , \[17570] , preset }; + assign n2608 = 32'd1426346240 >> { pdata_12_12_, \[10820] , \[17635] , \[17570] , preset }; + assign n2613 = 32'd1426346240 >> { pdata_10_10_, \[10850] , \[17310] , \[17388] , preset }; + assign n2618 = 16'h3120 >> { \[10865] , n3326, preset, n2969 }; + assign n2623 = 16'h1302 >> { \[10880] , n3077, preset, n2947 }; + assign n2628 = 16'h3120 >> { \[10895] , n3054, preset, n2968_1 }; + assign n2633 = 16'hf888 >> { n3136, \[10925] , n3139, n3137 }; + assign n2638 = 16'h3120 >> { \[10940] , n3404, preset, n3102 }; + assign n2643 = 16'h1302 >> { \[10955] , n3272, preset, n3102 }; + assign n2648 = 16'hf888 >> { n3195, \[10970] , n3262, n3196 }; + assign n2653 = 16'hf888 >> { n3342, \[10985] , n3345, n3343_1 }; + assign n2658 = 16'h3120 >> { \[11015] , n3139, preset, n3096 }; + assign n2663 = 32'd1426346240 >> { pdata_12_12_, \[11030] , \[17843] , \[17791] , preset }; + assign n2668 = 32'd1426346240 >> { pdata_9_9_, \[11045] , \[17505] , \[17414] , preset }; + assign n2673 = 32'd1426346240 >> { pdata_2_2_, \[11060] , \[18142] , \[18220] , preset }; + assign n2678 = 32'd1426346240 >> { pdata_7_7_, \[11075] , \[18142] , \[18220] , preset }; + assign n2683 = 32'd1426346240 >> { pdata_13_13_, \[11090] , \[17635] , \[17570] , preset }; + assign n2688 = 16'hf888 >> { n2986, \[11120] , n3058_1, n2983_1 }; + assign n2693 = 16'h3120 >> { \[11135] , n3074, preset, n2969 }; + assign n2698_1 = 16'h1302 >> { \[11150] , n2962, preset, n2947 }; + assign n2703 = 16'h1302 >> { \[11165] , n3258, preset, n2968_1 }; + assign n2713 = 16'h3120 >> { \[11195] , n3194, preset, n3102 }; + assign n2718 = 16'h1302 >> { \[11210] , n3201, preset, n3102 }; + assign n2723 = 16'hf222 >> { n3195, \[11225] , n3267, n3196 }; + assign n2728 = 16'h3120 >> { \[11240] , n3262, preset, n3101 }; + assign n2733 = 16'h3120 >> { \[11255] , n3339, preset, n3096 }; + assign n2738 = 16'h1302 >> { \[11270] , n3192, preset, n3096 }; + assign n2743 = 32'd1426346240 >> { pdata_15_15_, \[11285] , \[17843] , \[17791] , preset }; + assign n2748 = 32'd1426346240 >> { pdata_6_6_, \[11300] , \[17505] , \[17414] , preset }; + assign n2753 = 32'd1426346240 >> { pdata_1_1_, \[11315] , \[18142] , \[18220] , preset }; + assign n2758 = 32'd1426346240 >> { pdata_8_8_, \[11330] , \[18142] , \[18220] , preset }; + assign n2763 = 32'd1426346240 >> { pdata_3_3_, \[11345] , \[17635] , \[17570] , preset }; + assign n2768 = 16'hf222 >> { n2986, \[11375] , n3251, n2983_1 }; + assign n2773 = 16'h3120 >> { \[11390] , n3052, preset, n2947 }; + assign n2778 = 16'h3120 >> { \[11405] , n3081, preset, n2968_1 }; + assign n2783 = 16'hf222 >> { n3136, \[11420] , n3267, n3137 }; + assign n2788 = 64'h1331313102202020 >> { \[11435] , n2968_1, ppeaka_4_4_, n3160, preset, n3102 }; + assign n2793_1 = 64'h88282822aaaaaaaa >> { n3102, n3164, n3190, n3185, n3181, n3753_1 }; + assign n3753_1 = 8'h54 >> { \[11450] , n3102, preset }; + assign n2798_1 = 16'hf222 >> { n3195, \[11465] , n3274, n3196 }; + assign n2803_1 = 16'h3120 >> { \[11480] , n3339, preset, n2968_1 }; + assign n2808_1 = 16'h1302 >> { \[11495] , n3198, preset, n3096 }; + assign n2813_1 = 16'h1302 >> { \[11510] , n3201, preset, n3096 }; + assign n2818_1 = 32'd1426346240 >> { pdata_14_14_, \[11525] , \[17843] , \[17791] , preset }; + assign n2823_1 = 32'd1426346240 >> { pdata_7_7_, \[11540] , \[17505] , \[17414] , preset }; + assign n2828_1 = 32'd1426346240 >> { pdata_0_0_, \[11555] , \[18142] , \[18220] , preset }; + assign n2833_1 = 32'd1426346240 >> { pdata_9_9_, \[11570] , \[18142] , \[18220] , preset }; + assign n2838_1 = 32'd1426346240 >> { pdata_2_2_, \[11585] , \[17635] , \[17570] , preset }; + assign n2843_1 = 32'd1426346240 >> { pdata_11_11_, \[11600] , \[17635] , \[17570] , preset }; + assign n2848_1 = 32'd823336962 >> { \[11615] , n3000, n2988_1, preset, n2947 }; + assign n2853 = 16'hf888 >> { n3136, \[11630] , n3339, n3137 }; + assign n2858 = 16'hf222 >> { n3136, \[11645] , n3192, n3137 }; + assign n2863 = 16'h1302 >> { \[11660] , n3274, preset, n3102 }; + assign n2868 = 32'd321978912 >> { \[11675] , n3345, n3190, preset, n3102 }; + assign n2873 = 16'hf888 >> { n3195, \[11690] , n3085, n3196 }; + assign n2878 = 16'h3120 >> { \[11705] , n3139, preset, n2968_1 }; + assign n2883 = 16'h3120 >> { \[11720] , n3404, preset, n3096 }; + assign n2888 = 16'h3120 >> { \[11735] , n3264, preset, n3096 }; + assign n2893 = 32'd1426346240 >> { pdata_9_9_, \[11750] , \[17843] , \[17791] , preset }; + assign n2898 = 32'd1426346240 >> { pdata_4_4_, \[11765] , \[17505] , \[17414] , preset }; + assign n2903 = 32'd1426346240 >> { pdata_15_15_, \[11780] , \[17505] , \[17414] , preset }; + assign n2908 = 32'd1426346240 >> { pdata_10_10_, \[11795] , \[18142] , \[18220] , preset }; + assign n2913 = 32'd1426346240 >> { pdata_5_5_, \[11810] , \[17635] , \[17570] , preset }; + assign n473_1 = 16'h555d >> { n2857, preset, ppeaki_9_9_, n3779 }; + assign n3779 = 32'd3149597627 >> { n3641, n2862, ppeaki_13_13_, \[12275] , n2873_1 }; + assign n3780 = 64'h0000077707770777 >> { n2849, \[9260] , n2847, \[5165] , n2840, \[4505] }; + assign n3781 = 64'h0000077707770777 >> { n2874, \[13235] , \[15140] , n2872, n2867, \[13250] }; + assign n2918 = 32'd1426346240 >> { pdata_5_5_, \[11885] , \[17505] , \[17414] , preset }; + assign n2923 = 32'd1426346240 >> { pdata_14_14_, \[11900] , \[17505] , \[17414] , preset }; + assign n2928 = 32'd1426346240 >> { pdata_11_11_, \[11915] , \[18142] , \[18220] , preset }; + assign n2933 = 32'd1426346240 >> { pdata_4_4_, \[11930] , \[17635] , \[17570] , preset }; + assign n457 = 16'h555d >> { n2857, preset, ppeaki_8_8_, n3787 }; + assign n3787 = 32'd3149597627 >> { n3641, n2862, ppeaki_12_12_, \[12485] , n2873_1 }; + assign n377 = 32'd4285887861 >> { \[13550] , n2872, ppeakb_15_15_, n2855, n3789 }; + assign n3789 = 64'h00ff80ff80ff80ff >> { \[7295] , n2854, n2862, n3792, n3790, n3791 }; + assign n3790 = 64'h00000ddd0ddd0ddd >> { \[13580] , n2875, n2868_1, \[14390] , n2845, ppeaka_15_15_ }; + assign n3791 = 64'h0000077707770777 >> { n2850, \[8600] , n2848, \[8450] , n2841, \[6590] }; + assign n3792 = 64'h0000077707770777 >> { \[7880] , n2839, n2852, \[15620] , n2836, \[4535] }; + assign n2938 = 16'hf222 >> { n3794, \[12005] , n3198, n3795 }; + assign n3794 = 4'h1 >> { n3090, preset }; + assign n3795 = 4'h2 >> { preset, n3090 }; + assign n2943 = 32'd1426346240 >> { pdata_11_11_, \[12020] , \[17843] , \[17791] , preset }; + assign n2948 = 32'd1426346240 >> { pdata_13_13_, \[12035] , \[17505] , \[17414] , preset }; + assign n2953 = 32'd1426346240 >> { pdata_12_12_, \[12050] , \[18142] , \[18220] , preset }; + assign n2958 = 32'd1426346240 >> { pdata_7_7_, \[12065] , \[17635] , \[17570] , preset }; + assign n2963 = 32'd1426346240 >> { pdata_14_14_, \[12080] , \[17635] , \[17570] , preset }; + assign n425 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_7_7_, n2873_1, \[12065] , n3802 }; + assign n3802 = 32'd539011104 >> { n2835, ppeaki_15_15_, ppeaki_11_11_, n3641, n2862 }; + assign n2968 = 16'hf888 >> { n3794, \[12125] , n3264, n3795 }; + assign n2973 = 32'd1426346240 >> { pdata_10_10_, \[12140] , \[17843] , \[17791] , preset }; + assign n2978_1 = 32'd1426346240 >> { pdata_3_3_, \[12155] , \[17505] , \[17414] , preset }; + assign n2983 = 32'd1426346240 >> { pdata_13_13_, \[12170] , \[18142] , \[18220] , preset }; + assign n2988 = 32'd1426346240 >> { pdata_6_6_, \[12185] , \[17635] , \[17570] , preset }; + assign n2993 = 32'd1426346240 >> { pdata_15_15_, \[12200] , \[17635] , \[17570] , preset }; + assign n605 = 32'd1970667381 >> { n3811, n2862, ppeakb_13_13_, n2855, n3810 }; + assign n3810 = 64'h0000077707770777 >> { \[8570] , n2898_1, n2874, \[14375] , n2872, \[15500] }; + assign n3811 = 64'h0088888800080808 >> { n2845, n2868_1, \[13595] , ppeaka_13_13_, n3813_1, n3812 }; + assign n3812 = 64'h0000077707770777 >> { \[7325] , n2850, \[4460] , n2848, n2852, \[14885] }; + assign n3813_1 = 64'h0000077707770777 >> { n2841, \[5210] , \[6620] , n2839, n2836, \[13670] }; + assign n2998 = 16'hf888 >> { n3342, \[12245] , n3160, n3343_1 }; + assign n3003 = 32'd1426346240 >> { pdata_14_14_, \[12260] , \[18142] , \[18220] , preset }; + assign n3008 = 32'd1426346240 >> { pdata_9_9_, \[12275] , \[17635] , \[17570] , preset }; + assign n517_1 = 32'd1145324788 >> { preset, n2857, ppeaki_13_13_, \[11090] , n2873_1 }; + assign n665 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_2_2_, n2873_1, \[11585] , n3819 }; + assign n3819 = 32'd539011104 >> { n2835, ppeaki_10_10_, ppeaki_6_6_, n3641, n2862 }; + assign n4463 = 4'h2 >> { preset, n2978 }; + assign n3013 = 16'hf888 >> { n3822, \[12335] , n3081, n4463 }; + assign n3822 = 4'h1 >> { n4451, preset }; + assign n4038 = 8'h08 >> { preset, n2966, n4509 }; + assign n3018 = 16'h3120 >> { \[12350] , n3058_1, preset, n2950 }; + assign n3028 = 16'h1302 >> { \[12380] , n3198, preset, n3099 }; + assign n3033 = 16'h1302 >> { \[12395] , n3201, preset, n3099 }; + assign n3038 = 16'h3120 >> { \[12410] , n3085, preset, n3100 }; + assign n3048 = 16'hf222 >> { n3794, \[12440] , n3192, n3795 }; + assign n3053 = 16'hf888 >> { n3342, \[12455] , n3194, n3343_1 }; + assign n3058 = 32'd1426346240 >> { pdata_15_15_, \[12470] , \[18142] , \[18220] , preset }; + assign n3063 = 32'd1426346240 >> { pdata_8_8_, \[12485] , \[17635] , \[17570] , preset }; + assign n661 = 32'd1145324788 >> { preset, n2857, ppeaki_12_12_, \[10820] , n2873_1 }; + assign n297 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_3_3_, n2873_1, \[11345] , n3834 }; + assign n3834 = 32'd539011104 >> { n2835, ppeaki_11_11_, ppeaki_7_7_, n3641, n2862 }; + assign n3068 = 16'h3120 >> { \[12545] , pdata_4_4_, preset, n2950 }; + assign n3073 = 16'hf222 >> { n3822, \[12560] , n3258, n4463 }; + assign n3078 = 32'd321978912 >> { \[12575] , n3021, n3031, preset, n2950 }; + assign n3083 = 16'h3120 >> { \[12590] , n3326, preset, n2952 }; + assign n3088 = 16'h3120 >> { \[12605] , n3339, preset, n3099 }; + assign n3093 = 16'h1302 >> { \[12620] , n3272, preset, n3099 }; + assign n3098 = 16'h1302 >> { \[12635] , n3274, preset, n3100 }; + assign n3103 = 16'hf888 >> { n3195, \[12650] , n3345, n3196 }; + assign n3108 = 16'hf888 >> { n3794, \[12665] , n3139, n3795 }; + assign n3113 = 16'hf888 >> { n3342, \[12680] , n3404, n3343_1 }; + assign n3118 = 32'd1426346240 >> { pdata_0_0_, \[12695] , \[17635] , \[17570] , preset }; + assign n293 = 16'h555d >> { n2857, preset, ppeaki_11_11_, n3847 }; + assign n3847 = 32'd3149597627 >> { n3641, n2862, ppeaki_15_15_, \[11600] , n2873_1 }; + assign n621 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_0_0_, n2873_1, \[12695] , n3849 }; + assign n3849 = 32'd539011104 >> { n2835, ppeaki_8_8_, ppeaki_4_4_, n3641, n2862 }; + assign n3123 = 16'h3120 >> { \[12770] , pdata_14_14_, preset, n2950 }; + assign n3128 = 16'h3120 >> { \[12800] , n3056, preset, n2970 }; + assign n3133 = 16'h3120 >> { \[12815] , n3079, preset, n2950 }; + assign n3138 = 16'h3120 >> { \[12830] , n3081, preset, n2952 }; + assign n3143 = 16'h3120 >> { \[12845] , n3194, preset, n3099 }; + assign n3148 = 16'h3120 >> { \[12860] , n3139, preset, n3099 }; + assign n3153 = 64'h1331313102202020 >> { \[12875] , n2968_1, ppeaka_4_4_, n3160, preset, n3100 }; + assign n3158_1 = 16'hf888 >> { n3794, \[12890] , n3339, n3795 }; + assign n3163_1 = 16'hf888 >> { n3794, \[12905] , n3262, n3795 }; + assign n3168_1 = 16'hf222 >> { n3342, \[12920] , n3198, n3343_1 }; + assign n3173_1 = 32'd1426346240 >> { pdata_10_10_, \[12935] , \[17635] , \[17570] , preset }; + assign n453_1 = 16'h555d >> { n2857, preset, ppeaki_10_10_, n3862 }; + assign n3862 = 32'd3149597627 >> { n3641, n2862, ppeaki_14_14_, \[12935] , n2873_1 }; + assign n641 = 64'haeaeaeaeaeaeffae >> { preset, n2857, ppeaki_1_1_, n2873_1, \[10805] , n3864 }; + assign n3864 = 32'd539011104 >> { n2835, ppeaki_9_9_, ppeaki_5_5_, n3641, n2862 }; + assign n3178_1 = 16'h3120 >> { \[13010] , pdata_8_8_, preset, n2952 }; + assign n3183_1 = 16'h1302 >> { \[13025] , n3243, preset, n2970 }; + assign n3188_1 = 16'h3120 >> { \[13040] , n3074, preset, n2970 }; + assign n3193_1 = 16'h3120 >> { \[13055] , n3054, preset, n2950 }; + assign n3198_1 = 16'h1302 >> { \[13070] , n3251, preset, n2950 }; + assign n3203_1 = 16'h1302 >> { \[13085] , n3258, preset, n2952 }; + assign n3208_1 = 16'h3120 >> { \[13100] , n3404, preset, n3099 }; + assign n3213_1 = 16'h3120 >> { \[13115] , n3264, preset, n3099 }; + assign n3218_1 = 16'h3120 >> { \[13130] , n3194, preset, n3100 }; + assign n3223_1 = 16'hf222 >> { n3794, \[13160] , n3267, n3795 }; + assign n3228_1 = 16'hf888 >> { n3342, \[13175] , n3339, n3343_1 }; + assign n609_1 = 32'd1970667381 >> { n3877, n2862, ppeakb_4_4_, n2855, n3880 }; + assign n3877 = 64'h0008080800888888 >> { n2844, n2840, \[5195] , ppeaka_4_4_, n3879, n3878 }; + assign n3878 = 64'h0000077707770777 >> { n2838, \[14495] , \[9170] , n2851, n2817, \[12545] }; + assign n3879 = 64'h0000077707770777 >> { n2849, \[8585] , n2853_1, \[7280] , n2847, \[5840] }; + assign n3880 = 64'h0000077707770777 >> { n2874, \[14360] , \[14765] , n2872, n2867, \[5795] }; + assign n357 = 8'hd5 >> { n2867, \[16040] , n3882 }; + assign n3882 = 64'h80aa00aa80aa80aa >> { \[5720] , n2894, n2862, n3884, n3886, n3883 }; + assign n3883 = 64'h0000dd0ddd0ddd0d >> { n2901, ppeaka_10_10_, n2900, ppeakp_9_9_, n2897, ppeaka_9_9_ }; + assign n3884 = 32'd2763306 >> { \[13265] , n2890, n2885, \[11270] , n3885 }; + assign n3885 = 64'h0ddd055501110111 >> { n2888_1, ppeaka_9_9_, n2847, \[5825] , ppeakb_9_9_, n2875 }; + assign n3886 = 64'h0000077707770777 >> { n2892, \[9125] , n2883_1, \[15770] , n2849, \[9905] }; + assign n3233_1 = 32'd1426346240 >> { pdata_3_3_, \[13220] , \[18246] , \[17453] , preset }; + assign n3238_1 = 32'd1426346240 >> { pdata_14_14_, \[13235] , \[18246] , \[17453] , preset }; + assign n3243_1 = 16'h3120 >> { \[13250] , pdata_14_14_, preset, n4451 }; + assign n3248_1 = 32'd1426346240 >> { pdata_9_9_, \[13265] , \[17154] , \[17102] , preset }; + assign n3253_1 = 16'h3120 >> { \[13280] , pdata_4_4_, preset, n2938_1 }; + assign n3258_1 = 16'h3120 >> { \[13295] , pdata_1_1_, preset, n2947 }; + assign n3263_1 = 16'h3120 >> { \[13310] , pdata_1_1_, preset, n2950 }; + assign n3268 = 16'h3120 >> { \[13325] , pdata_12_12_, preset, n2950 }; + assign n3273 = 16'h3120 >> { \[13340] , pdata_7_7_, preset, n2952 }; + assign n3278 = 64'hffff288228822882 >> { n3822, \[13355] , n3021, n3027, n3031, n4463 }; + assign n3283 = 16'hf222 >> { n3822, \[13370] , n3251, n4463 }; + assign n3288 = 16'h3120 >> { \[13385] , n3326, preset, n2970 }; + assign n3293 = 16'h1302 >> { \[13400] , n3243, preset, n2950 }; + assign n3298 = 16'h3120 >> { \[13415] , n3052, preset, n2950 }; + assign n3303 = 16'h3120 >> { \[13430] , n3054, preset, n2952 }; + assign n3308 = 32'd4280821800 >> { n3136, \[13445] , n3345, n3190, n3137 }; + assign n3313 = 16'h1302 >> { \[13460] , n3267, preset, n3099 }; + assign n3318 = 16'h3120 >> { \[13475] , n3404, preset, n3100 }; + assign n3323 = 16'hf888 >> { n3195, \[13490] , n3264, n3196 }; + assign n3328 = 16'hf222 >> { n3794, \[13505] , n3274, n3795 }; + assign n3907 = 64'h0008080800888888 >> { n2844, n2847, \[7790] , ppeaka_5_5_, n3909, n3908 }; + assign n3908 = 64'h0000077707770777 >> { \[7910] , n2853_1, n2838, \[14075] , n2851, \[7235] }; + assign n3909 = 64'h0000077707770777 >> { n2849, \[9245] , n2840, \[5885] , n2817, \[5240] }; + assign n3333 = 16'h55d5 >> { preset, n2906, \[9890] , n3911 }; + assign n3911 = 64'h00000ddd0ddd0ddd >> { \[6650] , n2898_1, n2872, \[10355] , n2904, \[13550] }; + assign n465 = 4'h7 >> { n3913, n3914 }; + assign n3913 = 64'h00000ddd0ddd0ddd >> { n2920, \[14705] , n2898_1, ppeakb_6_6_, n2923_1, ppeakp_6_6_ }; + assign n3914 = 64'h0777077700000777 >> { n2873_1, \[10085] , ppeaka_6_6_, n2928_1, n2930, \[9575] }; + assign n3338 = 32'd1426346240 >> { pdata_15_15_, \[13580] , \[18246] , \[17453] , preset }; + assign n3343 = 16'h3120 >> { \[13595] , pdata_13_13_, preset, n4451 }; + assign n3348 = 32'd1426346240 >> { pdata_10_10_, \[13610] , \[17154] , \[17102] , preset }; + assign n3353 = 16'h3120 >> { \[13625] , pdata_3_3_, preset, n2938_1 }; + assign n3358 = 16'h3120 >> { \[13640] , pdata_2_2_, preset, n2947 }; + assign n3363 = 16'h3120 >> { \[13655] , pdata_0_0_, preset, n2950 }; + assign n3368 = 16'h3120 >> { \[13670] , pdata_13_13_, preset, n2950 }; + assign n3373 = 16'h3120 >> { \[13685] , pdata_6_6_, preset, n2952 }; + assign n3378 = 16'hf888 >> { n2986, \[13700] , n3054, n2983_1 }; + assign n3383 = 16'hf222 >> { n3822, \[13715] , n3077, n4463 }; + assign n3388 = 64'hffffffff28282822 >> { n3926, n3059, n3071, n3066, n4455, n4463 }; + assign n3926 = 4'h8 >> { n3822, \[13730] }; + assign n3393_1 = 16'h3120 >> { \[13745] , n3081, preset, n2970 }; + assign n3398 = 32'd823336962 >> { \[13775] , n3000, n2988_1, preset, n2950 }; + assign n3403 = 16'h3120 >> { \[13790] , n3058_1, preset, n2952 }; + assign n3408 = 16'hf222 >> { n3136, \[13805] , n3272, n3137 }; + assign n3413 = 16'h1302 >> { \[13820] , n3192, preset, n3099 }; + assign n3418 = 16'h1302 >> { \[13835] , n3198, preset, n3100 }; + assign n3423 = 16'hf888 >> { n3195, \[13850] , n3139, n3196 }; + assign n3428 = 16'hf888 >> { n3794, \[13865] , n3085, n3795 }; + assign n3438 = 32'd1426346240 >> { pdata_8_8_, \[13895] , \[17843] , \[17791] , preset }; + assign n3936 = 32'd707395626 >> { n2894, \[4295] , n2847, \[7145] , n3937 }; + assign n3937 = 32'd1058346261 >> { ppeaka_11_11_, ppeakb_11_11_, n2883_1, \[13490] , n2875 }; + assign n3938 = 64'h00000ddd0ddd0ddd >> { n2867, \[15335] , ppeaka_12_12_, n2901, n2900, ppeakp_11_11_ }; + assign n529 = 8'h5d >> { n2897, ppeaka_0_0_, n3940 }; + assign n3940 = 64'h5151f351f351f351 >> { \[4310] , n2895, n3941, n2900, ppeakp_0_0_, n2862 }; + assign n3941 = 64'h0808000888880088 >> { n2850, n2888_1, ppeakb_0_0_, \[11480] , n3942, n3944 }; + assign n3942 = 64'h0080808000aaaaaa >> { n2875, n2868_1, \[16025] , ppeakb_0_0_, ppeaka_0_0_, n3943 }; + assign n3943 = 64'h0000077707770777 >> { \[11255] , n2886, n2848, \[14840] , n2863_1, ppeaka_1_1_ }; + assign n3944 = 64'h0000077707770777 >> { \[9110] , n2893_1, n2891, \[13970] , n2884, \[8240] }; + assign n437 = 4'h7 >> { n3946, n3947 }; + assign n3946 = 64'h00000ddd0ddd0ddd >> { ppeaka_5_5_, n2928_1, ppeakb_5_5_, n2898_1, n2923_1, ppeakp_5_5_ }; + assign n3947 = 64'h0000770777077707 >> { n2920, \[15080] , n2873_1, \[8840] , n2930, \[11660] }; + assign n3443 = 32'd1426346240 >> { pdata_5_5_, \[13955] , \[18246] , \[17453] , preset }; + assign n3448 = 32'd1426346240 >> { pdata_0_0_, \[13970] , \[17154] , \[17102] , preset }; + assign n3453 = 32'd1426346240 >> { pdata_7_7_, \[13985] , \[17154] , \[17102] , preset }; + assign n3458 = 16'h3120 >> { \[14000] , pdata_2_2_, preset, n2938_1 }; + assign n3463 = 32'd1426346240 >> { pdata_13_13_, \[14015] , \[17362] , \[17167] , preset }; + assign n3468 = 16'h3120 >> { \[14030] , pdata_8_8_, preset, n2943_1 }; + assign n3473 = 16'h3120 >> { \[14045] , pdata_3_3_, preset, n2950 }; + assign n3478 = 16'h3120 >> { \[14060] , pdata_10_10_, preset, n2950 }; + assign n3483 = 16'h3120 >> { \[14075] , pdata_5_5_, preset, n2952 }; + assign n3488 = 32'd1426346240 >> { pdata_11_11_, \[14090] , \[17310] , \[17388] , preset }; + assign n3493 = 16'hf888 >> { n3822, \[14105] , n3054, n4463 }; + assign n3498 = 32'd4286743170 >> { n3822, \[14120] , n2988_1, n3000, n4463 }; + assign n3503 = 16'h1302 >> { \[14135] , n3258, preset, n2970 }; + assign n3508 = 16'h1302 >> { \[14150] , n3077, preset, n2950 }; + assign n3513 = 16'h3120 >> { \[14165] , n3074, preset, n2950 }; + assign n3518 = 32'd321978912 >> { \[14180] , n3021, n3031, preset, n2952 }; + assign n3523 = 16'h3120 >> { \[14210] , n3085, preset, n3099 }; + assign n3528_1 = 16'h3120 >> { \[14225] , n3339, preset, n3100 }; + assign n3533_1 = 16'hf222 >> { n3195, \[14240] , n3272, n3196 }; + assign n3538 = 16'hf888 >> { n3794, \[14255] , n3194, n3795 }; + assign n3543 = 16'hf888 >> { n3794, \[14270] , n3345, n3795 }; + assign n3548 = 32'd1426346240 >> { pdata_7_7_, \[14285] , \[17843] , \[17791] , preset }; + assign n577 = 32'd4285887861 >> { \[9215] , n2898_1, ppeakb_3_3_, n2855, n3971 }; + assign n3971 = 64'h0777077700000777 >> { n3972, n2862, n2874, \[13220] , n2872, \[15860] }; + assign n3972 = 64'h0088888800080808 >> { n2845, n2868_1, \[7760] , ppeaka_3_3_, n3974, n3973_1 }; + assign n3973_1 = 64'h0000077707770777 >> { \[7940] , n2850, \[6530] , n2848, n2839, \[14915] }; + assign n3974 = 64'h0000077707770777 >> { n2841, \[4490] , \[8510] , n2852, n2836, \[14045] }; + assign n325 = 32'd3132817338 >> { n2900, ppeakp_10_10_, ppeaka_10_10_, n2897, n3976 }; + assign n3976 = 64'hff007f007f007f00 >> { \[14960] , n2868_1, n2862, n3980, n3977, n3979 }; + assign n3977 = 32'd707395626 >> { n2888_1, ppeakb_10_10_, n2886, \[11015] , n3978_1 }; + assign n3978_1 = 64'h0000077707770777 >> { n2893_1, \[8465] , \[13610] , n2891, n2884, \[13850] }; + assign n3979 = 32'd14013909 >> { \[5015] , n2895, ppeaka_10_10_, ppeakb_10_10_, n2875 }; + assign n3980 = 64'h0000077707770777 >> { n2850, \[11705] , n2848, \[6515] , n2863_1, ppeaka_11_11_ }; + assign n541 = 8'h5d >> { n2897, ppeaka_1_1_, n3982 }; + assign n3982 = 64'h5151f351f351f351 >> { \[6305] , n2883_1, n3983_1, n2900, ppeakp_1_1_, n2862 }; + assign n3983_1 = 8'h2a >> { ppeaka_2_2_, n2863_1, n3984 }; + assign n3984 = 64'h0808000888880088 >> { n2848, n2888_1, ppeakb_1_1_, \[14420] , n3985, n3987 }; + assign n3985 = 64'h0080808000aaaaaa >> { n2875, n2895, \[5030] , ppeakb_1_1_, ppeaka_1_1_, n3986 }; + assign n3986 = 64'h0000077707770777 >> { \[7175] , n2893_1, \[4925] , n2850, n2868_1, \[15680] }; + assign n3987 = 16'h0777 >> { \[4400] , n2891, n2886, \[11495] }; + assign n409 = 4'h7 >> { n3989, n3990 }; + assign n3989 = 64'h00000ddd0ddd0ddd >> { n2928_1, ppeaka_4_4_, n2930, \[11435] , n2923_1, ppeakp_4_4_ }; + assign n3990 = 64'h0000770777077707 >> { n2920, \[15440] , n2873_1, \[9515] , n2898_1, ppeakb_4_4_ }; + assign n3553 = 32'd1426346240 >> { pdata_4_4_, \[14360] , \[18246] , \[17453] , preset }; + assign n3558 = 32'd1426346240 >> { pdata_13_13_, \[14375] , \[18246] , \[17453] , preset }; + assign n3563 = 16'h3120 >> { \[14390] , pdata_15_15_, preset, n4451 }; + assign n3568 = 32'd1426346240 >> { pdata_8_8_, \[14405] , \[17154] , \[17102] , preset }; + assign n3573 = 16'h3120 >> { \[14420] , pdata_1_1_, preset, n2938_1 }; + assign n3578 = 32'd1426346240 >> { pdata_14_14_, \[14435] , \[17362] , \[17167] , preset }; + assign n3583 = 16'h3120 >> { \[14450] , pdata_7_7_, preset, n2943_1 }; + assign n3588 = 16'h3120 >> { \[14465] , pdata_2_2_, preset, n2950 }; + assign n3593 = 16'h3120 >> { \[14480] , pdata_11_11_, preset, n2950 }; + assign n3598 = 16'h3120 >> { \[14495] , pdata_4_4_, preset, n2952 }; + assign n3603 = 32'd1426346240 >> { pdata_1_1_, \[14510] , \[17310] , \[17388] , preset }; + assign n3608 = 16'hf888 >> { n3822, \[14525] , n3058_1, n4463 }; + assign n3613 = 16'hf888 >> { n3822, \[14540] , n3079, n4463 }; + assign n3618 = 16'h3120 >> { \[14555] , n3054, preset, n2970 }; + assign n3623 = 16'h1302 >> { \[14570] , n2962, preset, n2950 }; + assign n3628 = 16'h3120 >> { \[14585] , n3056, preset, n2950 }; + assign n3633 = 16'h1302 >> { \[14600] , n3077, preset, n2952 }; + assign n3638 = 64'hffffffff88282822 >> { n4009, n3164, n3190, n3185, n3181, n3137 }; + assign n4009 = 4'h8 >> { n3136, \[14615] }; + assign n3643_1 = 16'h3120 >> { \[14630] , n3262, preset, n3099 }; + assign n3648_1 = 16'hf222 >> { n3195, \[14660] , n3201, n3196 }; + assign n3653 = 16'hf888 >> { n3794, \[14675] , n3160, n3795 }; + assign n3658 = 16'hf222 >> { n3794, \[14690] , n3272, n3795 }; + assign n3663 = 32'd1426346240 >> { pdata_6_6_, \[14705] , \[17843] , \[17791] , preset }; + assign n313_1 = 8'h5d >> { n2855, ppeakb_8_8_, n4016 }; + assign n4016 = 32'd1381653 >> { \[9050] , n2874, n2872, \[6410] , n4017 }; + assign n4017 = 64'haaaa2a222a222a22 >> { \[5810] , n2868_1, ppeaka_8_8_, n2845, n4018_1, n2862 }; + assign n4018_1 = 64'h0008080800888888 >> { n2841, n2848, \[8435] , \[14030] , n4019, n4020 }; + assign n4019 = 16'h0777 >> { \[6665] , n2854, n2839, \[13010] }; + assign n4020 = 64'h0000077707770777 >> { n2850, \[6005] , \[6605] , n2852, n2836, \[14900] }; + assign n4021 = 32'd1058346261 >> { ppeaka_13_13_, ppeakb_13_13_, n2883_1, \[14240] , n2875 }; + assign n4022 = 64'h0000770777077707 >> { n2890, \[15920] , n2894, \[15500] , n2847, \[8420] }; + assign n4023_1 = 64'h00000ddd0ddd0ddd >> { n2867, \[14540] , ppeaka_14_14_, n2901, n2900, ppeakp_13_13_ }; + assign n565 = 32'd2136866653 >> { ppeakb_2_2_, n2874, n2897, ppeaka_2_2_, n4025 }; + assign n4025 = 64'h5151f351f351f351 >> { \[6980] , n2883_1, n4026, n2900, ppeakp_2_2_, n2862 }; + assign n4026 = 16'h0888 >> { \[15515] , n2895, n4029, n4027 }; + assign n4027 = 32'd2763306 >> { \[13715] , n2868_1, n2863_1, ppeaka_3_3_, n4028_1 }; + assign n4028_1 = 64'h0000077707770777 >> { \[11720] , n2886, \[9635] , n2850, n2848, \[14000] }; + assign n4029 = 64'h00000ddd0ddd0ddd >> { n2893_1, \[7805] , n2891, \[5105] , n2888_1, ppeakb_2_2_ }; + assign n3668 = 32'd4285887861 >> { \[5270] , n2898_1, \[14765] , n2904, n4031 }; + assign n4031 = 32'd2004289399 >> { preset, \[9875] , n2906, \[12875] , n2872 }; + assign n4032 = 64'h0000077707770777 >> { n2913_1, \[12440] , \[8780] , n2853_1, n2840, \[11135] }; + assign n4033_1 = 32'd2763306 >> { n2872, \[13820] , n2867, \[13040] , n4034 }; + assign n4034 = 64'h00000ddd0ddd0ddd >> { n2920, \[11045] , n2874, \[7970] , n2917, ppeaks_9_9_ }; + assign n501 = 4'h7 >> { n4036, n4037 }; + assign n4036 = 64'h0ddd0ddd00000ddd >> { n2873_1, \[7580] , n2930, \[11675] , n2923_1, ppeakp_14_14_ }; + assign n4037 = 64'h0000077707770777 >> { n2920, \[11525] , n2928_1, ppeaka_14_14_, n2898_1, ppeakb_14_14_ }; + assign n3673 = 16'h3120 >> { \[14810] , pdata_10_10_, preset, n4451 }; + assign n3678 = 32'd1426346240 >> { pdata_5_5_, \[14825] , \[17154] , \[17102] , preset }; + assign n3683 = 16'h3120 >> { \[14840] , pdata_0_0_, preset, n2938_1 }; + assign n3688 = 16'h3120 >> { \[14855] , pdata_9_9_, preset, n2938_1 }; + assign n3693 = 32'd1426346240 >> { pdata_4_4_, \[14870] , \[17362] , \[17167] , preset }; + assign n3698 = 16'h3120 >> { \[14885] , pdata_13_13_, preset, n2947 }; + assign n3703 = 16'h3120 >> { \[14900] , pdata_8_8_, preset, n2950 }; + assign n3708 = 16'h3120 >> { \[14915] , pdata_3_3_, preset, n2952 }; + assign n3713 = 16'h3120 >> { \[14930] , pdata_7_7_, preset, n2954 }; + assign n3718 = 16'hf888 >> { n3822, \[14960] , n3056, n4463 }; + assign n3723 = 16'h3120 >> { \[14975] , n3058_1, preset, n2970 }; + assign n3728 = 16'h3120 >> { \[14990] , n3079, preset, n2947 }; + assign n3733 = 16'h3120 >> { \[15005] , n3081, preset, n2950 }; + assign n3738 = 16'h1302 >> { \[15020] , n2962, preset, n2952 }; + assign n3743 = 64'h1331313102202020 >> { \[15035] , n2968_1, ppeaka_4_4_, n3160, preset, n3099 }; + assign n3748 = 64'h88282822aaaaaaaa >> { n3099, n3164, n3190, n3185, n3181, n4054 }; + assign n4054 = 8'h54 >> { \[15050] , n3099, preset }; + assign n3753 = 16'hf222 >> { n3794, \[15065] , n3201, n3795 }; + assign n3758_1 = 32'd1426346240 >> { pdata_5_5_, \[15080] , \[17843] , \[17791] , preset }; + assign n349 = 8'h5d >> { n2855, ppeakb_9_9_, n4058_1 }; + assign n4058_1 = 32'd1381653 >> { \[5990] , n2898_1, n2872, \[5720] , n4059 }; + assign n4059 = 64'haaaa2a222a222a22 >> { \[8390] , n2875, ppeaka_9_9_, n2845, n4060, n2862 }; + assign n4060 = 32'd2763306 >> { n2852, \[4520] , n2868_1, \[15185] , n4061 }; + assign n4061 = 32'd2763306 >> { n2848, \[14855] , n2836, \[15275] , n4062 }; + assign n4062 = 64'h0000077707770777 >> { n2850, \[6680] , \[7850] , n2841, n2839, \[16010] }; + assign n561 = 16'hdfdd >> { ppeaka_12_12_, n2897, n4064, n4068_1 }; + assign n4064 = 32'd707439146 >> { n2894, \[15845] , n4067, n4065, n2862 }; + assign n4065 = 32'd2763306 >> { n2890, \[4415] , n2849, \[4940] , n4066 }; + assign n4066 = 64'h0ddd055501110111 >> { n2888_1, ppeaka_12_12_, n2883_1, \[14660] , ppeakb_12_12_, n2875 }; + assign n4067 = 64'h0000077707770777 >> { n2892, \[7190] , n2885, \[11510] , n2847, \[7775] }; + assign n4068_1 = 64'h00000ddd0ddd0ddd >> { n2867, \[14120] , ppeaka_13_13_, n2901, n2900, ppeakp_12_12_ }; + assign n593 = 32'd2136866653 >> { ppeakb_3_3_, n2874, n2897, ppeaka_3_3_, n4070 }; + assign n4070 = 16'hdd0d >> { n2900, ppeakp_3_3_, n4071, n2862 }; + assign n4071 = 64'h0008080800888888 >> { n2883_1, n2868_1, \[13355] , \[4910] , n4074, n4072 }; + assign n4072 = 32'd2763306 >> { \[15860] , n2895, n2863_1, ppeaka_4_4_, n4073_1 }; + assign n4073_1 = 64'h0000770777077707 >> { n2891, \[15560] , n2888_1, ppeakb_3_3_, n2848, \[13625] }; + assign n4074 = 64'h0000077707770777 >> { n2893_1, \[15245] , n2886, \[9920] , n2850, \[8960] }; + assign n3763_1 = 16'h55d5 >> { preset, n2906, \[10730] , n4076 }; + assign n4076 = 64'h00000ddd0ddd0ddd >> { \[5975] , n2898_1, n2872, \[10070] , n2904, \[15140] }; + assign n549_1 = 8'hd5 >> { n2867, \[13385] , n4078_1 }; + assign n4078_1 = 64'h80800080aaaa00aa >> { n2862, n2917, ppeaks_8_8_, n4079, n4083_1, n4084 }; + assign n4079 = 64'h0008080800888888 >> { n2817, n2849, \[7520] , \[15365] , n4080, n4082 }; + assign n4080 = 32'd2763306 >> { \[13160] , n2913_1, n2883_1, \[11225] , n4081 }; + assign n4081 = 16'h0777 >> { n2853_1, \[9440] , n2847, \[6095] }; + assign n4082 = 16'h0777 >> { \[7595] , n2890, n2840, \[10865] }; + assign n4083_1 = 64'h0000077707770777 >> { n2916, \[8915] , n2838, \[12590] , n2851, \[6815] }; + assign n4084 = 64'h0000077707770777 >> { n2920, \[10775] , n2874, \[7340] , n2872, \[13460] }; + assign n581 = 4'h7 >> { n4086, n4087 }; + assign n4086 = 64'h00000ddd0ddd0ddd >> { n2928_1, ppeaka_15_15_, n2930, \[11450] , n2923_1, ppeakp_15_15_ }; + assign n4087 = 64'h0000770777077707 >> { n2920, \[11285] , n2873_1, \[8210] , n2898_1, ppeakb_15_15_ }; + assign n3768_1 = 16'h3120 >> { \[15185] , pdata_9_9_, preset, n4451 }; + assign n3773 = 32'd1426346240 >> { pdata_6_6_, \[15200] , \[17154] , \[17102] , preset }; + assign n3778 = 32'd1426346240 >> { pdata_15_15_, \[15215] , \[17154] , \[17102] , preset }; + assign n3783 = 16'h3120 >> { \[15230] , pdata_10_10_, preset, n2938_1 }; + assign n3788 = 32'd1426346240 >> { pdata_3_3_, \[15245] , \[17362] , \[17167] , preset }; + assign n3793 = 16'h3120 >> { \[15260] , pdata_12_12_, preset, n2947 }; + assign n3798 = 16'h3120 >> { \[15275] , pdata_9_9_, preset, n2950 }; + assign n3803 = 16'h3120 >> { \[15290] , pdata_2_2_, preset, n2952 }; + assign n3808 = 16'h3120 >> { \[15305] , pdata_13_13_, preset, n2954 }; + assign n3813 = 32'd4294910594 >> { n4098_1, n3066, n3059, n4455, n2983_1 }; + assign n4098_1 = 4'h8 >> { n2986, \[15320] }; + assign n3818 = 16'hf888 >> { n3822, \[15335] , n3052, n4463 }; + assign n3823 = 32'd321978912 >> { \[15350] , n3021, n3031, preset, n2970 }; + assign n3828 = 16'h3120 >> { \[15365] , n3326, preset, n2950 }; + assign n3833 = 16'h1302 >> { \[15380] , n3243, preset, n2952 }; + assign n3838 = 16'h1302 >> { \[15395] , n3274, preset, n3099 }; + assign n3843 = 32'd321978912 >> { \[15410] , n3345, n3190, preset, n3099 }; + assign n3848 = 16'hf888 >> { n3794, \[15425] , n3404, n3795 }; + assign n3853 = 32'd1426346240 >> { pdata_4_4_, \[15440] , \[17843] , \[17791] , preset }; + assign n4107 = 64'h0088888800080808 >> { n2845, n2868_1, \[4385] , ppeaka_6_6_, n4109, n4108_1 }; + assign n4108_1 = 64'h0000077707770777 >> { \[7160] , n2848, \[6575] , n2841, n2852, \[7865] }; + assign n4109 = 64'h0000077707770777 >> { n2850, \[4610] , \[13685] , n2839, n2836, \[15635] }; + assign n413_1 = 32'd3132817338 >> { n2900, ppeakp_15_15_, ppeaka_15_15_, n2897, n4111 }; + assign n4111 = 64'h7f00ff007f007f00 >> { ppeakb_15_15_, n2888_1, n2862, n4114, n4112, n4113_1 }; + assign n4112 = 64'h0040404000555555 >> { n2875, n2850, \[7010] , ppeakb_15_15_, ppeaka_15_15_, n3359 }; + assign n4113_1 = 64'h0000077707770777 >> { \[6365] , n2886, \[13550] , n2895, n2868_1, \[13730] }; + assign n4114 = 64'h0000077707770777 >> { n2893_1, \[7205] , \[15215] , n2891, n2848, \[15950] }; + assign n617 = 64'h22f222f2ffff22f2 >> { n2900, ppeakp_4_4_, n4116, n2862, n2897, ppeaka_4_4_ }; + assign n4116 = 64'h0808000888880088 >> { n2883_1, n2888_1, ppeakb_4_4_, \[5615] , n4120, n4117 }; + assign n4117 = 32'd2763306 >> { \[14525] , n2868_1, n2863_1, ppeaka_5_5_, n4118_1 }; + assign n4118_1 = 64'h0080808000aaaaaa >> { n2875, n2886, \[8975] , ppeakb_4_4_, ppeaka_4_4_, n4119 }; + assign n4119 = 16'h0777 >> { n2891, \[15905] , n2850, \[8300] }; + assign n4120 = 64'h0000077707770777 >> { n2893_1, \[14870] , n2848, \[13280] , n2895, \[14765] }; + assign n3858 = 32'd4285887861 >> { \[15305] , n2898_1, \[15500] , n2904, n4122 }; + assign n4122 = 32'd2004289399 >> { preset, n2906, \[10445] , \[9800] , n2872 }; + assign n3863 = 16'h55d5 >> { preset, n2906, \[8930] , n4124 }; + assign n4124 = 64'h00000ddd0ddd0ddd >> { \[9710] , n2898_1, n2872, \[13475] , n2904, \[15515] }; + assign n365 = 64'hffffbbfbbbfbbbfb >> { n2867, \[13025] , n2917, ppeaks_0_0_, n4131, n4126 }; + assign n4126 = 64'haaaaa222a222a222 >> { n2840, \[7415] , n2817, \[13400] , n4127, n2862 }; + assign n4127 = 64'h0008080800888888 >> { n2838, n2890, \[10670] , \[15380] , n4128_1, n4130 }; + assign n4128_1 = 32'd2763306 >> { \[12890] , n2913_1, n2916, \[13175] , n4129 }; + assign n4129 = 16'h0777 >> { n2849, \[9455] , n2853_1, \[7490] }; + assign n4130 = 64'h0000077707770777 >> { n2884, \[8240] , \[5390] , n2847, n2851, \[6125] }; + assign n4131 = 64'h0000077707770777 >> { n2920, \[9935] , n2874, \[5330] , n2872, \[12605] }; + assign n3868 = 16'h3120 >> { \[15545] , pdata_12_12_, preset, n4451 }; + assign n3873 = 32'd1426346240 >> { pdata_3_3_, \[15560] , \[17154] , \[17102] , preset }; + assign n3878_1 = 32'd1426346240 >> { pdata_14_14_, \[15575] , \[17154] , \[17102] , preset }; + assign n3883_1 = 16'h3120 >> { \[15590] , pdata_5_5_, preset, n2938_1 }; + assign n3888_1 = 16'h3120 >> { \[15605] , pdata_0_0_, preset, n2938_1 }; + assign n3893_1 = 16'h3120 >> { \[15620] , pdata_15_15_, preset, n2947 }; + assign n3898_1 = 16'h3120 >> { \[15635] , pdata_6_6_, preset, n2950 }; + assign n3903_1 = 16'h3120 >> { \[15650] , pdata_1_1_, preset, n2952 }; + assign n3908_1 = 16'h3120 >> { \[15665] , pdata_3_3_, preset, n2954 }; + assign n3913_1 = 16'hf222 >> { n3822, \[15680] , n2962, n4463 }; + assign n3918_1 = 16'hf888 >> { n3822, \[15695] , n3326, n4463 }; + assign n3923_1 = 16'h1302 >> { \[15710] , n3077, preset, n2970 }; + assign n3933_1 = 16'hf222 >> { n3136, \[15755] , n3201, n3137 }; + assign n3938_1 = 16'hf222 >> { n3195, \[15770] , n3192, n3196 }; + assign n3943_1 = 32'd1426346240 >> { pdata_3_3_, \[15785] , \[17843] , \[17791] , preset }; + assign n4147 = 64'h0000077707770777 >> { n2849, \[5315] , \[9095] , n2847, n2838, \[13340] }; + assign n4148_1 = 64'h0000077707770777 >> { n2874, \[7115] , \[7055] , n2872, n2867, \[6500] }; + assign n321 = 16'hdfdd >> { ppeaka_14_14_, n2897, n4150, n4154 }; + assign n4150 = 32'd707439146 >> { n2894, \[15140] , n4153_1, n4151, n2862 }; + assign n4151 = 32'd2763306 >> { \[15575] , n2890, n2885, \[8315] , n4152 }; + assign n4152 = 64'h0ddd055501110111 >> { n2888_1, ppeaka_14_14_, n2883_1, \[12650] , ppeakb_14_14_, n2875 }; + assign n4153_1 = 64'h0000077707770777 >> { n2892, \[14435] , \[6335] , n2849, n2847, \[9080] }; + assign n4154 = 64'h00000ddd0ddd0ddd >> { n2867, \[13370] , ppeaka_15_15_, n2901, n2900, ppeakp_14_14_ }; + assign n633 = 32'd3132817338 >> { n2900, ppeakp_5_5_, ppeaka_5_5_, n2897, n4156 }; + assign n4156 = 64'haaaaa222a222a222 >> { ppeaka_6_6_, n2863_1, n2883_1, \[11465] , n4157, n2862 }; + assign n4157 = 64'h0008080800888888 >> { n2848, n2893_1, \[6560] , \[15590] , n4158_1, n4160 }; + assign n4158_1 = 64'h0080808000aaaaaa >> { n2875, n2895, \[8330] , ppeakb_5_5_, ppeaka_5_5_, n4159 }; + assign n4159 = 64'h0000077707770777 >> { n2891, \[14825] , \[7670] , n2850, n2868_1, \[14105] }; + assign n4160 = 16'h7707 >> { n2888_1, ppeakb_5_5_, n2886, \[5660] }; + assign n3948_1 = 32'd4285887861 >> { \[9980] , n2898_1, \[15845] , n2904, n4162 }; + assign n4162 = 32'd2004289399 >> { preset, \[8285] , n2906, \[9500] , n2872 }; + assign n3953_1 = 32'd4285887861 >> { \[15665] , n2898_1, \[15860] , n2904, n4164 }; + assign n4164 = 32'd2004289399 >> { preset, \[10145] , n2906, \[13130] , n2872 }; + assign n4165 = 64'h0008080800888888 >> { n2890, n2884, \[13850] , \[10400] , n4167, n4166 }; + assign n4166 = 64'h0000077707770777 >> { n2913_1, \[12665] , n2849, \[8810] , n2851, \[5450] }; + assign n4167 = 16'h0777 >> { \[9860] , n2916, n2838, \[6155] }; + assign n4168_1 = 64'h0000077707770777 >> { \[10205] , n2920, \[12860] , n2872, n2867, \[12800] }; + assign n3958 = 16'h3120 >> { \[15890] , pdata_11_11_, preset, n4451 }; + assign n3963 = 32'd1426346240 >> { pdata_4_4_, \[15905] , \[17154] , \[17102] , preset }; + assign n3968 = 32'd1426346240 >> { pdata_13_13_, \[15920] , \[17154] , \[17102] , preset }; + assign n3973 = 16'h3120 >> { \[15935] , pdata_6_6_, preset, n2938_1 }; + assign n3978 = 16'h3120 >> { \[15950] , pdata_15_15_, preset, n2938_1 }; + assign n3983 = 16'h3120 >> { \[15965] , pdata_14_14_, preset, n2947 }; + assign n3988 = 16'h3120 >> { \[15980] , pdata_7_7_, preset, n2950 }; + assign n3993 = 16'h3120 >> { \[15995] , pdata_0_0_, preset, n2952 }; + assign n3998 = 16'h3120 >> { \[16010] , pdata_9_9_, preset, n2952 }; + assign n4003 = 16'hf222 >> { n3822, \[16025] , n3243, n4463 }; + assign n4008 = 16'hf888 >> { n3822, \[16040] , n3074, n4463 }; + assign n4013 = 16'h1302 >> { \[16055] , n2962, preset, n2970 }; + assign n4018 = 16'h1302 >> { \[16070] , n3251, preset, n2947 }; + assign n4023 = 16'h1302 >> { \[16085] , n3258, preset, n2950 }; + assign n4028 = 16'hf888 >> { n3136, \[16100] , n3264, n3137 }; + assign n4128 = 4'h2 >> { preset, n4185 }; + assign n4185 = 8'h08 >> { \[17167] , n2893_1, n4509 }; + assign n4213_1 = 8'h02 >> { preset, \[17388] , \[16933] }; + assign n4083 = 8'h02 >> { preset, \[17050] , \[17115] }; + assign n4103 = 8'h02 >> { preset, \[17102] , \[17037] }; + assign n4538 = 8'h02 >> { preset, \[18415] , \[18363] }; + assign n4533_1 = 8'h02 >> { preset, \[18389] , \[18311] }; + assign n4168 = 8'h02 >> { preset, \[17271] , \[17206] }; + assign n497 = 32'd3587571669 >> { n4204, ppeaks_8_8_, n4193_1, paddress_8_8_, n4206 }; + assign n4193_1 = 8'h80 >> { n4194, n4195, n4203 }; + assign n4194 = 64'h0101010101010001 >> { \[17453] , n2876, n2984, n2952, n2947, n2950 }; + assign n4195 = 32'd8 >> { n4185, n2938_1, n2954, n3822, n4196 }; + assign n4196 = 64'h8000800000008000 >> { \[17271] , \[17206] , n4201, n4202, n4197, n4199 }; + assign n4197 = 64'h5151515151515100 >> { n2859, pdn, \[17791] , \[18220] , \[17999] , n4198_1 }; + assign n4198_1 = 32'd1145328708 >> { pdn, n2860, n2859, \[18467] , \[17570] }; + assign n4199 = 32'd2324299914 >> { \[18415] , \[18363] , \[16933] , \[17388] , n4200 }; + assign n4200 = 16'hdd0d >> { \[18389] , \[18311] , \[17414] , \[17843] }; + assign n4201 = 8'h45 >> { \[17037] , \[17102] , n2943_1 }; + assign n4202 = 64'h1000101011001111 >> { \[17817] , \[17115] , \[17050] , \[17518] , n3101, n3102 }; + assign n4203 = 8'h51 >> { \[17583] , \[17648] , n2969 }; + assign n4204 = 8'h02 >> { n4463, n4228, n4205 }; + assign n4205 = 32'd1 >> { n4563, n4178, n4038, n4528_1, n4213_1 }; + assign n4206 = 8'h8a >> { ppeaka_8_8_, n4501, n4207 }; + assign n4207 = 64'h2a2a2a2a002a2a2a >> { preset, ppeakb_8_8_, n2969, n3562, \[6410] , n4208 }; + assign n4208 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[11330] , n4209, ppeakp_8_8_, n4211 }; + assign n4209 = 8'h15 >> { n2860, n4210, n4103 }; + assign n4210 = 4'h2 >> { preset, n4198_1 }; + assign n4211 = 64'h0008080800888888 >> { n4083, n4538, \[8000] , \[13160] , n4212, n4213 }; + assign n4212 = 64'h0000077707770777 >> { n4168, \[11225] , \[8750] , n4533_1, n4153, \[8915] }; + assign n4213 = 64'h0000077707770777 >> { \[11420] , n4216, \[13460] , n4215, n4214, \[7595] }; + assign n4214 = 4'h2 >> { preset, n3102 }; + assign n4215 = 8'h02 >> { preset, \[17583] , \[17648] }; + assign n4216 = 8'h02 >> { preset, \[17518] , \[17817] }; + assign n4033 = 64'h5551454015110500 >> { \[16907] , ppeakb_7_7_, ppeaka_7_7_, n4203, n4218, preset }; + assign n4218 = 64'h0001000100000001 >> { \[17518] , \[17817] , n3092, n3102, n3090, n3091 }; + assign n4043 = 32'd286265360 >> { n2850, n2833, \[16933] , \[17388] , preset }; + assign n477 = 32'd3587571669 >> { n4204, ppeaks_9_9_, n4193_1, paddress_9_9_, n4221 }; + assign n4221 = 8'h8a >> { ppeaka_9_9_, n4501, n4222 }; + assign n4222 = 64'h2a2a2a2a002a2a2a >> { preset, ppeakb_9_9_, n2969, n3562, \[5720] , n4223 }; + assign n4223 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[11570] , n4209, ppeakp_9_9_, n4224 }; + assign n4224 = 64'h0008080800888888 >> { n4153, n4168, \[15770] , \[9590] , n4225, n4226 }; + assign n4225 = 64'h0000077707770777 >> { \[10040] , n4533_1, \[7370] , n4538, n4214, \[10685] }; + assign n4226 = 64'h0000077707770777 >> { \[11645] , n4216, \[13820] , n4215, n4083, \[12440] }; + assign n4048 = 64'h5551454015110500 >> { \[16959] , ppeakb_8_8_, ppeaka_8_8_, n4203, n4218, preset }; + assign n4053 = 8'h02 >> { preset, \[16920] , \[16972] }; + assign n4058 = 8'h02 >> { preset, \[18389] , \[16985] }; + assign n4063 = 64'h5551454015110500 >> { \[16998] , ppeakb_5_5_, ppeaka_5_5_, n4203, n4218, preset }; + assign n4068 = 8'h51 >> { \[17011] , n4232, preset }; + assign n4232 = 4'h8 >> { n4203, n4218 }; + assign n4078 = 16'h1110 >> { \[17037] , \[18025] , preset, \[17102] }; + assign n4088 = 64'h5551454015110500 >> { \[17063] , ppeakb_6_6_, ppeaka_6_6_, n4203, n4218, preset }; + assign n4093 = 64'h5551454015110500 >> { \[17076] , ppeakb_15_15_, ppeaka_15_15_, n4203, n4218, preset }; + assign n4098 = 4'h8 >> { n4073, \[17089] }; + assign n4073 = 4'h1 >> { preset, pdn }; + assign n4108 = 32'd286265360 >> { n2846, n4509, \[17115] , preset, \[17050] }; + assign n4113 = 64'h5551454015110500 >> { \[17128] , ppeakb_3_3_, ppeaka_3_3_, n4203, n4218, preset }; + assign n4118 = 8'h51 >> { \[17141] , n4232, preset }; + assign n4123 = 8'h02 >> { preset, \[17102] , \[17154] }; + assign n4133 = 32'd286265360 >> { n2896, n4509, \[17180] , \[17232] , preset }; + assign n4138 = 64'h5551454015110500 >> { \[17193] , ppeakb_4_4_, ppeaka_4_4_, n4203, n4218, preset }; + assign n4143 = 32'd286265360 >> { n2884, n4509, \[17206] , preset, \[17271] }; + assign n4148 = 8'h02 >> { preset, \[17050] , \[17219] }; + assign n4158 = 16'h0222 >> { n2886, n2833, preset, \[17245] }; + assign n4163 = 64'h5551454015110500 >> { \[17258] , ppeakb_1_1_, ppeaka_1_1_, n4203, n4218, preset }; + assign n4173 = 32'd286265360 >> { n2841, n4509, \[17284] , \[18376] , preset }; + assign n4183 = 8'h02 >> { preset, \[17388] , \[17310] }; + assign n4188 = 64'h5551454015110500 >> { \[17323] , ppeakb_2_2_, ppeaka_2_2_, n4203, n4218, preset }; + assign n4193 = 8'h51 >> { \[17336] , n4232, preset }; + assign n4198 = 8'h02 >> { preset, \[17271] , \[17349] }; + assign n4203_1 = 8'h02 >> { preset, \[17167] , \[17362] }; + assign n4208_1 = 8'h02 >> { preset, \[17297] , \[17375] }; + assign n341 = 8'h5d >> { n4204, ppeaks_11_11_, n4256 }; + assign n4256 = 32'd707395626 >> { n4501, ppeaka_11_11_, n4193_1, paddress_11_11_, n4257 }; + assign n4257 = 64'h2a2a2a2a002a2a2a >> { preset, n2969, ppeakb_11_11_, n3562, \[4295] , n4258_1 }; + assign n4258_1 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[11915] , n4209, ppeakp_11_11_, n4259 }; + assign n4259 = 64'h0008080800888888 >> { n4214, n4538, \[8645] , \[10115] , n4261, n4260 }; + assign n4260 = 64'h0000077707770777 >> { n4168, \[13490] , n4083, \[12125] , n4153, \[10130] }; + assign n4261 = 64'h0000077707770777 >> { n4216, \[16100] , n4215, \[13115] , n4533_1, \[10595] }; + assign n4218_1 = 8'h02 >> { preset, \[17414] , \[17843] }; + assign n4223_1 = 16'h1110 >> { \[17518] , \[17427] , preset, \[17700] }; + assign n429 = 8'h5d >> { n4204, ppeaks_10_10_, n4265 }; + assign n4265 = 32'd707395626 >> { n4501, ppeaka_10_10_, n4193_1, paddress_10_10_, n4266 }; + assign n4266 = 64'h88888ccc8ccc8ccc >> { n2969, ppeakb_10_10_, n2954, \[5015] , n4267, preset }; + assign n4267 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[11795] , n4209, ppeakp_10_10_, n4268_1 }; + assign n4268_1 = 64'h0008080800888888 >> { n4168, n4216, \[10925] , \[13850] , n4269, n4270 }; + assign n4269 = 64'h0000077707770777 >> { n4215, \[12860] , n4083, \[12665] , n4214, \[10400] }; + assign n4270 = 64'h0000077707770777 >> { \[9770] , n4533_1, \[9305] , n4538, n4153, \[9860] }; + assign n4233 = 8'h51 >> { \[17479] , n4232, preset }; + assign n4238 = 64'h5551454015110500 >> { \[17492] , ppeakb_13_13_, ppeaka_13_13_, n4203, n4218, preset }; + assign n4243 = 8'h02 >> { preset, \[17414] , \[17505] }; + assign n4248 = 16'h1110 >> { \[17518] , \[17817] , preset, \[17700] }; + assign n4253 = 16'h5444 >> { n2825, \[17531] , n4509, preset }; + assign n4258 = 8'h02 >> { n2984, preset, \[17544] }; + assign n493_1 = 32'd3587571669 >> { n4204, ppeaks_13_13_, n4193_1, paddress_13_13_, n4278_1 }; + assign n4278_1 = 32'd2282260616 >> { ppeakb_13_13_, preset, n2969, n4283_1, n4279 }; + assign n4279 = 32'd2324299914 >> { n4209, ppeakp_13_13_, ppeaka_13_13_, n4501, n4280 }; + assign n4280 = 64'h0008080800888888 >> { n4153, n4533_1, \[4775] , \[10700] , n4282, n4281 }; + assign n4281 = 64'h0000077707770777 >> { \[14240] , n4168, \[9740] , n4538, n4214, \[8885] }; + assign n4282 = 64'h0000077707770777 >> { \[13805] , n4216, \[12620] , n4215, n4083, \[14690] }; + assign n4283_1 = 32'd2004289399 >> { n2860, n4210, \[12170] , \[15500] , n3562 }; + assign n4263 = 64'ha8a8a8a8aaa8a8a8 >> { pdn, n2860, n2859, \[17570] , \[18467] , n4285 }; + assign n4285 = 4'h2 >> { preset, n4286 }; + assign n4286 = 64'h0055045504550455 >> { \[17596] , n4504, \[17986] , \[18597] , n2821, \[17804] }; + assign n4268 = 16'h1110 >> { \[17583] , \[17648] , preset, \[17700] }; + assign n4273 = 32'd16777986 >> { n4504, n2820, \[18597] , preset, \[17596] }; + assign n4278 = 8'h02 >> { n2984, preset, \[17609] }; + assign n601 = 8'h5d >> { n4204, ppeaks_12_12_, n4291 }; + assign n4291 = 32'd707395626 >> { n4501, ppeaka_12_12_, n4193_1, paddress_12_12_, n4292 }; + assign n4292 = 64'h2a2a2a2a002a2a2a >> { preset, ppeakb_12_12_, n2969, n3562, \[15845] , n4293_1 }; + assign n4293_1 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[12050] , n4209, ppeakp_12_12_, n4294 }; + assign n4294 = 64'h0008080800888888 >> { n4083, n4538, \[10010] , \[15065] , n4295, n4296 }; + assign n4295 = 64'h0000077707770777 >> { \[14660] , n4168, \[10415] , n4153, n4214, \[9845] }; + assign n4296 = 64'h0000077707770777 >> { n4216, \[15755] , n4215, \[12395] , n4533_1, \[6860] }; + assign n4283 = 8'ha8 >> { \[17570] , \[17635] , n4285 }; + assign n4288 = 16'h1110 >> { \[17427] , \[17648] , preset, \[17700] }; + assign n4293 = 4'h2 >> { preset, n4504 }; + assign n4298 = 8'h02 >> { n2984, preset, \[17674] }; + assign n337 = 8'hd5 >> { n4193_1, paddress_15_15_, n4302 }; + assign n4302 = 32'd2324299914 >> { n4501, ppeaka_15_15_, ppeaks_15_15_, n4204, n4303_1 }; + assign n4303_1 = 64'h88888ccc8ccc8ccc >> { n2969, ppeakb_15_15_, n2954, \[13550] , n4304, preset }; + assign n4304 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[12470] , n4209, ppeakp_15_15_, n4305 }; + assign n4305 = 64'h0008080800888888 >> { n4538, n4533_1, \[8765] , \[6755] , n4307, n4306 }; + assign n4306 = 64'h0000077707770777 >> { n4168, \[12425] , n4083, \[13880] , n4153, \[6320] }; + assign n4307 = 64'h0000077707770777 >> { n4216, \[14615] , n4215, \[15050] , n4214, \[4880] }; + assign n4303 = 8'h02 >> { preset, \[17700] , \[18142] }; + assign n4308 = 32'd1426346240 >> { ppeaki_4_4_, \[17713] , \[17752] , n2984, preset }; + assign n4310 = 64'h0008080800888888 >> { n4215, n4216, \[13445] , \[15410] , n4313_1, n4311 }; + assign n4311 = 64'h2a2a2a2a002a2a2a >> { n2860, \[12260] , n4210, n4168, \[12650] , n4312 }; + assign n4312 = 64'h0000077707770777 >> { n4538, \[6080] , \[10985] , n4153, n4214, \[9560] }; + assign n4313_1 = 16'h0777 >> { \[5480] , n4533_1, n4083, \[14270] }; + assign n4313 = 8'h02 >> { preset, \[17700] , \[17739] }; + assign n4318 = 16'h2220 >> { \[17752] , n2984, preset, n2825 }; + assign n4323 = 64'h5551454015110500 >> { \[17765] , ppeakb_9_9_, ppeaka_9_9_, n4203, n4218, preset }; + assign n4328_1 = 64'h5551454015110500 >> { \[17778] , ppeakb_14_14_, ppeaka_14_14_, n4203, n4218, preset }; + assign n4333_1 = 32'd269488145 >> { n2859, pdn, \[17791] , preset, \[17414] }; + assign n4338_1 = 4'h2 >> { n4286, n4073 }; + assign n4343_1 = 16'h1110 >> { \[17817] , n4321, preset, \[17700] }; + assign n4321 = 16'h0002 >> { n2860, pdn, \[18467] , n2859 }; + assign n385 = 64'h00f700f700ff00f7 >> { \[17271] , \[17206] , preset, n4323_1, n4203, n4202 }; + assign n4323_1 = 16'h8000 >> { n4325, n4201, n4324, pwr_0_0_ }; + assign n4324 = 64'hdd0ddd0d0000dd0d >> { \[17349] , \[17271] , \[18441] , \[17232] , \[17427] , \[17518] }; + assign n4325 = 16'hdd0d >> { \[17219] , \[17050] , \[18077] , \[17583] }; + assign n4348_1 = 16'h1110 >> { \[17843] , \[17791] , preset, \[17414] }; + assign n4353_1 = 8'h54 >> { \[17856] , n2820, preset }; + assign n4358_1 = 8'h51 >> { \[17869] , n4232, preset }; + assign n4363_1 = 8'h51 >> { \[17882] , n4232, preset }; + assign n625 = 32'd4160223231 >> { preset, n4331, n3562, n4501, n4204 }; + assign n4331 = 8'ha2 >> { n2970, n4332, n4340 }; + assign n4332 = 64'h0000000000008000 >> { n2978, n4185, n4333, n4337, n4199, n4339 }; + assign n4333 = 64'h8080888800800088 >> { \[17635] , \[18389] , \[17570] , \[16985] , n4336, n4334 }; + assign n4334 = 32'd2324299914 >> { \[18142] , \[18220] , \[17414] , \[17505] , n4335 }; + assign n4335 = 16'hdd0d >> { \[17310] , \[17388] , \[17362] , \[17167] }; + assign n4336 = 16'hdd0d >> { \[16972] , \[16920] , \[18298] , \[18376] }; + assign n4337 = 64'h8000808088008888 >> { \[17791] , \[17453] , \[18246] , \[17843] , n4338, n4201 }; + assign n4338 = 32'd33685506 >> { \[17154] , \[17102] , n2972, n2973_1, prd_0_0_ }; + assign n4339 = 64'hdd0ddd0d0000dd0d >> { \[18480] , \[18415] , \[17375] , \[17297] , \[18428] , \[18493] }; + assign n4340 = 64'h8080888800800088 >> { \[17102] , \[18363] , \[17037] , \[18415] , n4197, n4200 }; + assign n4368_1 = 8'h51 >> { \[17908] , n4232, preset }; + assign n4373_1 = 64'h5551454015110500 >> { \[17921] , ppeakb_10_10_, ppeaka_10_10_, n4203, n4218, preset }; + assign n4378_1 = 8'h51 >> { \[17934] , n4232, preset }; + assign n4383_1 = 8'h51 >> { \[17947] , n4232, preset }; + assign n4388 = 8'h51 >> { \[17960] , n4232, preset }; + assign n4393 = 64'h5551454015110500 >> { \[17973] , ppeakb_12_12_, ppeaka_12_12_, n4203, n4218, preset }; + assign n4398 = 8'ha8 >> { \[17635] , \[17986] , n4285 }; + assign n4403 = 16'h1110 >> { \[18077] , \[17999] , preset, \[17700] }; + assign n4408 = 32'd1426346240 >> { ppeaki_2_2_, \[18012] , \[17531] , n4509, preset }; + assign n4413 = 32'd286265360 >> { n2891, n4509, \[18025] , \[17102] , preset }; + assign n4418 = 8'h51 >> { \[18038] , n4232, preset }; + assign n613 = 8'ha2 >> { \[17414] , n4286, n4073 }; + assign n4423 = 8'ha8 >> { \[18064] , n4321, n4073 }; + assign n4428 = 16'h1110 >> { \[17583] , \[18077] , preset, \[17700] }; + assign n4433 = 32'd1426346240 >> { ppeaki_3_3_, \[18090] , \[17531] , n4509, preset }; + assign n4438 = 8'h02 >> { preset, \[18168] , \[18103] }; + assign n4443 = 8'h51 >> { \[18116] , n4232, preset }; + assign n4448 = 8'h54 >> { \[18129] , n4321, preset }; + assign n4453 = 16'h1110 >> { \[18142] , \[18220] , preset, \[17700] }; + assign n4458 = 32'd1426346240 >> { ppeaki_0_0_, \[18155] , \[17531] , n4509, preset }; + assign n4468 = 8'h51 >> { \[18181] , n4232, preset }; + assign n4473 = 64'h5551454015110500 >> { \[18194] , ppeakb_11_11_, ppeaka_11_11_, n4203, n4218, preset }; + assign n4478 = 8'ha8 >> { \[18207] , n2820, n4073 }; + assign n4483 = 16'h1110 >> { \[18220] , \[17999] , preset, \[17700] }; + assign n4488 = 32'd1426346240 >> { ppeaki_1_1_, \[18233] , \[17531] , n4509, preset }; + assign n4493 = 8'h02 >> { preset, \[17453] , \[18246] }; + assign n669_1 = 32'd3587571669 >> { n4204, ppeaks_0_0_, n4193_1, paddress_0_0_, n4368 }; + assign n4368 = 8'h8a >> { ppeaka_0_0_, n4501, n4369 }; + assign n4369 = 64'h2a2a2a2a002a2a2a >> { preset, n2969, ppeakb_0_0_, n3562, \[4310] , n4370 }; + assign n4370 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[11555] , n4209, ppeakp_0_0_, n4371 }; + assign n4371 = 32'd526344 >> { \[8240] , n4168, n4218_1, n4372, n4374 }; + assign n4372 = 32'd1381653 >> { n4538, \[8630] , n4214, \[10670] , n4373 }; + assign n4373 = 64'h4040404055404040 >> { \[17050] , \[12890] , \[17115] , \[13175] , n3101, preset }; + assign n4374 = 64'h0000077707770777 >> { n4216, \[11630] , n4215, \[12605] , n4533_1, \[10025] }; + assign n401 = 32'd1162085636 >> { \[17739] , \[18142] , \[17700] , piack_0_0_, preset }; + assign n4498 = 32'd286265360 >> { n2848, n4509, \[18285] , preset, \[18415] }; + assign n4503 = 8'h02 >> { preset, \[18376] , \[18298] }; + assign n4508 = 16'h1110 >> { \[18311] , \[18506] , preset, \[18389] }; + assign n645 = 64'hf777f777fffff777 >> { n4204, ppeaks_1_1_, n4193_1, paddress_1_1_, n4382, n4380 }; + assign n4380 = 64'h2a2a2a2a002a2a2a >> { n2860, n4210, \[11315] , n4533_1, \[10310] , n4381 }; + assign n4381 = 64'h0000dd0ddd0ddd0d >> { n4083, \[12005] , n4209, ppeakp_1_1_, n4501, ppeaka_1_1_ }; + assign n4382 = 32'd2695407784 >> { ppeakb_1_1_, n2969, preset, n4383, n4386 }; + assign n4383 = 8'h2a >> { \[5030] , n2954, n4384 }; + assign n4384 = 32'd707395626 >> { \[18220] , \[17999] , n3101, \[12920] , n4385 }; + assign n4385 = 64'hf7f7f7f700f7f7f7 >> { \[17271] , \[6305] , \[17206] , \[18415] , \[9290] , \[18363] }; + assign n4386 = 64'h0000077707770777 >> { \[9485] , n4216, \[12380] , n4215, n4214, \[9830] }; + assign n4513 = 64'h5551454015110500 >> { \[18337] , ppeakb_0_0_, ppeaka_0_0_, n4203, n4218, preset }; + assign n4518_1 = 8'h51 >> { \[18350] , n4232, preset }; + assign n4523_1 = 16'h1110 >> { \[18363] , \[18285] , preset, \[18415] }; + assign n345 = 32'd3587571669 >> { n4204, ppeaks_2_2_, n4193_1, paddress_2_2_, n4391 }; + assign n4391 = 32'd2282260616 >> { ppeakb_2_2_, preset, n2969, n4396, n4392 }; + assign n4392 = 32'd2324299914 >> { n4209, ppeakp_2_2_, ppeaka_2_2_, n4501, n4393_1 }; + assign n4393_1 = 64'h0008080800888888 >> { n4153, n4533_1, \[4760] , \[12680] , n4395, n4394 }; + assign n4394 = 64'h0000077707770777 >> { \[6980] , n4168, \[9725] , n4538, n4214, \[10100] }; + assign n4395 = 64'h0000077707770777 >> { \[7535] , n4216, \[13100] , n4215, n4083, \[15425] }; + assign n4396 = 32'd2004289399 >> { n2860, n4210, \[11060] , \[15515] , n3562 }; + assign n4543 = 8'h02 >> { preset, \[18493] , \[18428] }; + assign n4548 = 8'h02 >> { preset, \[17232] , \[18441] }; + assign n301 = 8'h5d >> { n4204, ppeaks_3_3_, n4400 }; + assign n4400 = 32'd707395626 >> { n4501, ppeaka_3_3_, n4193_1, paddress_3_3_, n4401 }; + assign n4401 = 64'h2a2a2a2a002a2a2a >> { preset, ppeakb_3_3_, n2969, n3562, \[15860] , n4402 }; + assign n4402 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[10790] , n4209, ppeakp_3_3_, n4403_1 }; + assign n4403_1 = 64'h0008080800888888 >> { n4083, n4538, \[9995] , \[14255] , n4404, n4405 }; + assign n4404 = 64'h0000077707770777 >> { \[4910] , n4168, \[12455] , n4153, n4214, \[5570] }; + assign n4405 = 64'h0000077707770777 >> { n4216, \[8165] , n4215, \[12845] , n4533_1, \[6845] }; + assign n4553 = 64'h1110111011101100 >> { \[17700] , n2860, \[18467] , n2859, pdn, preset }; + assign n4558 = 8'h02 >> { preset, \[18415] , \[18480] }; + assign n4568 = 32'd286265360 >> { n2854, n2833, \[18506] , preset, \[18389] }; + assign n397 = 8'hd5 >> { n4193_1, paddress_4_4_, n4410 }; + assign n4410 = 32'd2324299914 >> { n4501, ppeaka_4_4_, ppeaks_4_4_, n4204, n4411 }; + assign n4411 = 64'h88888ccc8ccc8ccc >> { n2969, ppeakb_4_4_, n2954, \[14765] , n4412, preset }; + assign n4412 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[10505] , n4209, ppeakp_4_4_, n4413_1 }; + assign n4413_1 = 32'd8421504 >> { \[15035] , n4215, n4416, n4414, n4415 }; + assign n4414 = 16'h0777 >> { \[6170] , n4533_1, n4214, \[4865] }; + assign n4415 = 16'h0777 >> { \[5375] , n4538, n4153, \[12245] }; + assign n4416 = 64'h0000077707770777 >> { n4216, \[6230] , n4168, \[5615] , n4083, \[14675] }; + assign n373_1 = 32'd3587571669 >> { n4204, ppeaks_5_5_, n4193_1, paddress_5_5_, n4418_1 }; + assign n4418_1 = 64'ha2a2a2a200a2a2a2 >> { preset, ppeakb_5_5_, n2969, n4501, ppeaka_5_5_, n4419 }; + assign n4419 = 64'h0808000888880088 >> { n3562, n4209, ppeakp_5_5_, \[8330] , n4422, n4420 }; + assign n4420 = 64'h2a2a2a2a002a2a2a >> { n2860, n4210, \[10220] , n4083, \[13505] , n4421 }; + assign n4421 = 64'h0000077707770777 >> { n4216, \[6905] , \[11465] , n4168, n4538, \[4670] }; + assign n4422 = 32'd2763306 >> { n4215, \[15395] , n4153, \[6995] , n4423_1 }; + assign n4423_1 = 16'h0777 >> { n4533_1, \[8105] , n4214, \[9545] }; + assign n4573 = 16'h2301 >> { \[18545] , n2859, preset, pdn }; + assign n461 = 32'd3587571669 >> { n4204, ppeaks_6_6_, n4193_1, paddress_6_6_, n4426 }; + assign n4426 = 8'h8a >> { ppeaka_6_6_, n4501, n4427 }; + assign n4427 = 64'h2a2a2a2a002a2a2a >> { preset, ppeakb_6_6_, n2969, n3562, \[7685] , n4428_1 }; + assign n4428_1 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[9950] , n4209, ppeakp_6_6_, n4429 }; + assign n4429 = 64'h0008080800888888 >> { n4533_1, n4216, \[4835] , \[7475] , n4431, n4430 }; + assign n4430 = 64'h0000077707770777 >> { n4215, \[14210] , \[13865] , n4083, n4214, \[8870] }; + assign n4431 = 64'h0000077707770777 >> { n4168, \[11690] , \[6740] , n4538, n4153, \[7625] }; + assign n4578 = 8'h51 >> { \[18571] , n4232, preset }; + assign n4583 = 8'h51 >> { \[18584] , n4232, preset }; + assign n4588 = 16'ha888 >> { \[17596] , n4504, \[18597] , n4073 }; + assign n4593 = 64'h5444544454445040 >> { \[18168] , \[17453] , n2825, \[18610] , n2985, preset }; + assign n433_1 = 8'h5d >> { n4204, ppeaks_7_7_, n4437 }; + assign n4437 = 32'd707395626 >> { n4501, ppeaka_7_7_, n4193_1, paddress_7_7_, n4438_1 }; + assign n4438_1 = 64'h2a2a2a2a002a2a2a >> { preset, ppeakb_7_7_, n2969, n3562, \[7055] , n4439 }; + assign n4439 = 64'ha2a2a2a200a2a2a2 >> { n2860, n4210, \[11075] , n4209, ppeakp_7_7_, n4440 }; + assign n4440 = 64'h0008080800888888 >> { n4153, n4083, \[12905] , \[8255] , n4441, n4442 }; + assign n4441 = 64'h0000077707770777 >> { \[10970] , n4168, \[6065] , n4538, n4214, \[8225] }; + assign n4442 = 64'h0000077707770777 >> { n4216, \[5540] , n4215, \[14630] , n4533_1, \[9410] }; + assign n4598_1 = 32'd2728566946 >> { n2886, n4444, n4593, preset, n4509 }; + assign n4444 = 32'd2 >> { \[18389] , \[17271] , \[18415] , \[17050] , n4445 }; + assign n4445 = 32'd2 >> { \[17102] , \[17167] , \[18376] , \[18493] , n4446 }; + assign n4446 = 16'h0001 >> { \[16920] , \[17297] , \[17388] , \[17232] }; + assign n4447 = 64'h0000077707770777 >> { n2844, ppeaka_1_1_, \[5285] , n2853_1, \[8480] , n2840 }; + assign n4448_1 = 64'h88888ccc8ccc8ccc >> { n2836, \[13310] , \[15650] , n2839, n2878_1, n2818 }; + assign n537 = 64'h3f33bfbbbfbbbfbb >> { n4448_1, n4447, ppeakb_1_1_, n2855, n2879, n2862 }; + assign n4450 = 32'd286331157 >> { \[17609] , \[17674] , \[17544] , \[17752] , \[18610] }; + assign n4451 = 16'h8000 >> { n4450, n2833, n2864, n2934 }; + assign n808 = 64'h1313311302022002 >> { \[4730] , n3066, n3059, n4455, preset, n2969 }; + assign n4453_1 = 64'h0000077707770777 >> { n2972, \[8765] , \[6755] , n2973_1, \[13550] , n2954 }; + assign n4454 = 32'd707395626 >> { n2964, ppeaks_15_15_, n2978, ppeakb_15_15_, n4453_1 }; + assign n4455 = 64'hfc9a3c5a569a965a >> { ppeaka_14_14_, n2938_1, n2995, n4454, ppeaka_15_15_, n3062 }; + assign n4456 = 64'hdfdfdfdf55dfdfdf >> { \[16933] , n2850, ppeaka_0_0_, n2886, \[17245] , n2833 }; + assign n4457 = 64'h0000000000000080 >> { n3090, n3091, n3092, n4456, n3093_1, n3123_1 }; + assign n4458_1 = 64'h0000077707770777 >> { \[5900] , n2851, \[10550] , n2849, ppeaka_0_0_, n2844 }; + assign n4459 = 64'h88888ccc8ccc8ccc >> { \[15605] , n2848, \[7835] , n2841, n3205, n2818 }; + assign n521_1 = 64'h3f33bfbbbfbbbfbb >> { n4459, n4458_1, ppeakb_0_0_, n2855, n3206, n2862 }; + assign n4461 = 64'h15373737153f3f3f >> { n2826, n2863_1, ppeaka_8_8_, n2872, ppeakp_7_7_, n2862 }; + assign n285 = 64'hffffddfdddfdddfd >> { \[12335] , n2867, n2897, ppeaka_7_7_, n3207, n4461 }; + assign n4463_1 = 64'h15153f153f153f15 >> { n2868_1, \[14810] , n3276, \[5090] , n2874, n2862 }; + assign n309 = 32'd4285887861 >> { \[5015] , n2872, ppeakb_10_10_, n2855, n4463_1 }; + assign n1288 = 64'h1313311302022002 >> { \[6320] , n3185, n3164, n3181, preset, n3091 }; + assign n1303 = 64'h1313311302022002 >> { \[6365] , n3185, n3164, n3181, preset, n3096 }; + assign n4467 = 64'h0000077707770777 >> { n2851, \[5930] , n2844, ppeaka_11_11_, \[4595] , n2853_1 }; + assign n4468_1 = 64'h88888ccc8ccc8ccc >> { \[14090] , n2850, \[9155] , n2841, n3347, n2818 }; + assign n481 = 64'h3f33bfbbbfbbbfbb >> { n4468_1, n4467, ppeakb_11_11_, n2855, n3348_1, n2862 }; + assign n4470 = 64'h88888ccc8ccc8ccc >> { \[13640] , n2852, \[4445] , n2848, n3349, n2818 }; + assign n4471 = 64'h0000077707770777 >> { \[8555] , n2853_1, \[7310] , n2849, ppeaka_2_2_, n2844 }; + assign n557 = 64'h3f33bfbbbfbbbfbb >> { n4471, n4470, ppeakb_2_2_, n2855, n3350, n2862 }; + assign n1408_1 = 64'h1313311302022002 >> { \[6755] , n3066, n3059, n4455, preset, n2938_1 }; + assign n1583_1 = 64'h1313311302022002 >> { \[7355] , n3066, n3059, n4455, preset, n2970 }; + assign n2008 = 64'h1313311302022002 >> { \[8765] , n3066, n3059, n4455, preset, n2954 }; + assign n2708 = 64'h1313311302022002 >> { \[11180] , n3066, n3059, n4455, preset, n2968_1 }; + assign n4477 = 64'h8888c8ccc8ccc8cc >> { n2836, \[12770] , ppeaka_14_14_, n2845, n3780, n2818 }; + assign n4478_1 = 64'h0000077707770777 >> { n2851, \[15965] , \[7925] , n2853_1, \[7250] , n2838 }; + assign n305 = 64'h3f33bfbbbfbbbfbb >> { n4478_1, n4477, ppeakb_14_14_, n2855, n3781, n2862 }; + assign n3023 = 64'h1313311302022002 >> { \[12365] , n3066, n3059, n4455, preset, n2950 }; + assign n3043 = 64'h1313311302022002 >> { \[12425] , n3185, n3164, n3181, preset, n3092 }; + assign n4482 = 64'h15153f153f153f15 >> { n2868_1, \[6485] , n3907, \[13955] , n2874, n2862 }; + assign n629_1 = 32'd4285887861 >> { \[8330] , n2872, ppeakb_5_5_, n2855, n4482 }; + assign n3433 = 64'h1313311302022002 >> { \[13880] , n3185, n3164, n3181, preset, n3090 }; + assign n4485 = 64'hfffff222f222f222 >> { \[9650] , n2850, \[7820] , n2893_1, n2888_1, ppeakb_11_11_ }; + assign n4486 = 64'h00000ddd0ddd0ddd >> { n2885, \[11735] , \[5120] , n2890, n2818, n4485 }; + assign n417 = 64'h3b3bff3bbbbbffbb >> { n3936, n2897, ppeaka_11_11_, n4486, n3938, n2862 }; + assign n4488_1 = 64'h0008080800888888 >> { \[10190] , \[14015] , n2892, n2885, n4021, n4022 }; + assign n4489 = 64'h7777373337333733 >> { n2850, \[5645] , ppeakb_13_13_, n2888_1, n4488_1, n2818 }; + assign n589_1 = 32'd3587571669 >> { n2897, ppeaka_13_13_, n4489, n2862, n4023_1 }; + assign n4491 = 64'h88888ccc8ccc8ccc >> { n2836, \[14165] , \[10685] , n2891, n4032, n2818 }; + assign n4492 = 64'h55555ddd5ddd5ddd >> { \[10265] , n2854, \[7745] , n2875, n4107, n2862 }; + assign n649_1 = 32'd4285887861 >> { \[7685] , n2872, ppeakb_6_6_, n2855, n4492 }; + assign n3928_1 = 64'h1313311302022002 >> { \[15725] , n3066, n3059, n4455, preset, n2947 }; + assign n4495 = 64'h0000077707770777 >> { \[14930] , n2853_1, \[5915] , n2851, ppeaka_7_7_, n2844 }; + assign n4496 = 64'h88888ccc8ccc8ccc >> { n2836, \[15980] , \[14450] , n2841, n4147, n2818 }; + assign n273_1 = 64'h3b3bff3bbbbbffbb >> { n4496, n2855, ppeakb_7_7_, n4495, n4148_1, n2862 }; + assign n4498_1 = 64'h88888ccc8ccc8ccc >> { n2836, \[14585] , \[4700] , n2848, n4165, n2818 }; + assign n4499 = 64'h55555ddd5ddd5ddd >> { \[8135] , n2853_1, n2840, \[8060] , n4498_1, n2862 }; + assign n545 = 64'hffff77f777f777f7 >> { \[6035] , n2874, n2917, ppeaks_10_10_, n4168_1, n4499 }; + assign n4501 = 8'hab >> { n2938_1, n4185, preset }; + assign n4502 = 64'h1010101010101011 >> { ppeaki_6_6_, ppeaki_7_7_, ppeaki_5_5_, n3641, ppeaki_10_10_, ppeaki_14_14_ }; + assign n4503_1 = 64'h0000000000000001 >> { ppeaki_15_15_, ppeaki_12_12_, ppeaki_8_8_, ppeaki_13_13_, ppeaki_9_9_, ppeaki_11_11_ }; + assign n4504 = 64'h5500400055404040 >> { ppeaki_4_4_, n2835, n3641, n4502, n4503_1, n2825 }; + assign n4505 = 64'h0000dd0ddd0ddd0d >> { paddress_14_14_, n4193_1, n4204, ppeaks_14_14_, n4501, ppeaka_14_14_ }; + assign n4506 = 64'h45cd45cf45cf45cf >> { n2860, n4198_1, n4103, n3070, preset, ppeakp_14_14_ }; + assign n597 = 64'h7fff7f7f7f7f7f7f >> { n2969, ppeakb_14_14_, preset, n4506, n4505, n4310 }; + assign n4508_1 = 64'h01010101010101ab >> { \[17609] , \[17674] , \[17544] , ppeaki_7_7_, ppeaki_6_6_, \[17752] }; + assign n4509 = 64'h0222022222220222 >> { n2830, n4508_1, n2832, n2831, n2826, n2833 }; + assign n4510 = 64'h0000077707770777 >> { n2883_1, \[15770] , n2847, \[5405] , \[9590] , n2916 }; + assign n4511 = 64'h88888ccc8ccc8ccc >> { \[9470] , n2850, n2839, \[5465] , n4510, n2818 }; + assign n573 = 64'hff557f557f557f55 >> { n2851, \[4745] , n2862, n4511, n4491, n4033_1 }; + assign pdata_8_8_ = 8'he4 >> { \[16959] , tin_pdata_8_8_, \[17882] }; + assign pdata_0_0_ = 8'he4 >> { \[18337] , tin_pdata_0_0_, \[17479] }; + assign pdata_7_7_ = 8'he4 >> { \[16907] , tin_pdata_7_7_, \[17869] }; + assign pdata_2_2_ = 8'he4 >> { \[17323] , tin_pdata_2_2_, \[18181] }; + assign pdata_9_9_ = 8'he4 >> { \[17765] , tin_pdata_9_9_, \[18571] }; + assign pdata_1_1_ = 8'he4 >> { \[17258] , tin_pdata_1_1_, \[18116] }; + assign pdata_4_4_ = 8'he4 >> { \[17193] , tin_pdata_4_4_, \[18038] }; + assign pdata_10_10_ = 8'he4 >> { \[17921] , tin_pdata_10_10_, \[17011] }; + assign pdata_3_3_ = 8'he4 >> { \[17128] , tin_pdata_3_3_, \[17960] }; + assign pdata_6_6_ = 8'he4 >> { \[17063] , tin_pdata_6_6_, \[17934] }; + assign pdata_15_15_ = 8'he4 >> { \[17076] , tin_pdata_15_15_, \[17947] }; + assign pdata_11_11_ = 8'he4 >> { \[18194] , tin_pdata_11_11_, \[17336] }; + assign pdata_14_14_ = 8'he4 >> { \[17778] , tin_pdata_14_14_, \[18584] }; + assign pdata_12_12_ = 8'he4 >> { \[17973] , tin_pdata_12_12_, \[17141] }; + assign pdata_5_5_ = 8'he4 >> { \[16998] , tin_pdata_5_5_, \[17908] }; + assign pdata_13_13_ = 8'he4 >> { \[17492] , tin_pdata_13_13_, \[18350] }; + assign n673 = 32'd1426346240 >> { pdata_2_2_, ndout, \[17843] , \[17791] , preset }; + assign n553 = 32'd1970667381 >> { n2855, ppeakb_12_12_, n2862, n2815, n2866 }; + assign n2815 = 64'h0008080800888888 >> { n2851, n2853_1, \[9230] , \[15260] , n2816, n2843 }; + assign n2816 = 64'h0000077707770777 >> { n2840, \[8495] , \[5945] , n2838, n2817, \[13325] }; + assign n2817 = 4'h2 >> { n2818, n2836 }; + assign n2818 = 4'h8 >> { n2819, n2825 }; + assign n2819 = 16'hdd0d >> { \[17089] , pdn, \[17596] , n2820 }; + assign n2820 = 8'h08 >> { \[17804] , n2821, \[17986] }; + assign n2821 = 64'hdddddddddddd8ddd >> { \[10820] , \[12695] , n2824, n2822, \[17856] , \[18207] }; + assign n2822 = 32'd2 >> { \[11345] , \[11600] , \[12935] , \[12185] , n2823 }; + assign n2823 = 16'h0001 >> { \[12275] , \[12200] , \[12485] , \[10805] }; + assign n2824 = 64'h0000000000000001 >> { \[12080] , \[11810] , \[12065] , \[11930] , \[11090] , \[11585] }; + assign n2825 = 8'h45 >> { n2834, n4509, \[18636] }; + assign n2826 = 8'h80 >> { n2827, n2828, n2829 }; + assign n2827 = 32'd134765832 >> { ppeaki_0_0_, ppeaki_3_3_, \[18155] , \[18090] , \[17531] }; + assign n2828 = 8'hd8 >> { ppeaki_2_2_, \[18012] , \[17531] }; + assign n2829 = 8'h1b >> { \[18233] , ppeaki_1_1_, \[17531] }; + assign n2830 = 16'h0002 >> { \[17752] , ppeaki_6_6_, ppeaki_7_7_, ppeaki_5_5_ }; + assign n2831 = 32'd33686103 >> { ppeaki_3_3_, ppeaki_2_2_, \[18012] , \[18090] , \[17531] }; + assign n2832 = 32'd67415556 >> { \[18233] , \[18155] , ppeaki_1_1_, ppeaki_0_0_, \[17531] }; + assign n2833 = 32'd35791394 >> { n2831, n2829, n2835, \[18636] , n2834 }; + assign n2834 = 8'h02 >> { \[17661] , \[18597] , \[17596] }; + assign n2835 = 8'h27 >> { ppeaki_0_0_, \[18155] , \[17531] }; + assign n2836 = 8'h08 >> { n2828, n2837, n2832 }; + assign n2837 = 8'hd8 >> { ppeaki_3_3_, \[18090] , \[17531] }; + assign n2838 = 4'h2 >> { n2818, n2839 }; + assign n2839 = 8'h02 >> { n2828, n2829, n2827 }; + assign n2840 = 4'h2 >> { n2818, n2841 }; + assign n2841 = 8'h08 >> { n2837, n2828, n2842 }; + assign n2842 = 32'd3930079296 >> { \[18233] , \[18155] , ppeaki_1_1_, ppeaki_0_0_, \[17531] }; + assign n2843 = 64'h0000077707770777 >> { n2849, \[7955] , \[6545] , n2847, n2844, ppeaka_12_12_ }; + assign n2844 = 4'h1 >> { n2818, n2845 }; + assign n2845 = 16'h5554 >> { n2829, n2827, n2828, n2846 }; + assign n2846 = 8'h08 >> { n2837, n2828, n2832 }; + assign n2847 = 4'h2 >> { n2818, n2848 }; + assign n2848 = 16'h0080 >> { n2837, n2835, n2828, n2829 }; + assign n2849 = 4'h2 >> { n2818, n2850 }; + assign n2850 = 8'h08 >> { n2829, n2828, n2827 }; + assign n2851 = 4'h2 >> { n2818, n2852 }; + assign n2852 = 8'h08 >> { n2828, n2827, n2829 }; + assign n2853_1 = 4'h2 >> { n2818, n2854 }; + assign n2854 = 8'h80 >> { n2837, n2828, n2832 }; + assign n2855 = 4'h1 >> { n2856, n2861 }; + assign n2856 = 16'h1151 >> { n2819, n2860, n2857, preset }; + assign n2857 = 16'h5551 >> { n2858_1, \[17089] , pdn, n2818 }; + assign n2858_1 = 4'h2 >> { n2821, n2859 }; + assign n2859 = 8'h1b >> { \[18545] , preset_0_0_, \[17024] }; + assign n2860 = 8'h1b >> { \[18129] , pirq_0_0_, \[18064] }; + assign n2861 = 64'haaaaaaaa80000880 >> { n2863_1, n2829, n2837, n2835, n2828, n2862 }; + assign n2862 = 4'h1 >> { n2825, preset }; + assign n2863_1 = 64'h20202020aa202020 >> { \[17609] , n2865, \[17674] , n2830, ppeaki_4_4_, n2864 }; + assign n2864 = 4'h8 >> { n2831, n2832 }; + assign n2865 = 8'h02 >> { \[17713] , \[17544] , \[17752] }; + assign n2866 = 64'h0000077707770777 >> { \[6470] , n2874, n2872, \[15845] , n2867, \[15545] }; + assign n2867 = 4'h8 >> { n2862, n2868_1 }; + assign n2868_1 = 4'h2 >> { n2869, n2864 }; + assign n2869 = 32'd1431655701 >> { \[17609] , \[17674] , n2870, \[17713] , n2871 }; + assign n2870 = 4'h2 >> { \[17544] , \[17752] }; + assign n2871 = 32'd2 >> { ppeaki_5_5_, \[17752] , ppeaki_6_6_, ppeaki_7_7_, ppeaki_4_4_ }; + assign n2872 = 4'h1 >> { n2873_1, n2860 }; + assign n2873_1 = 64'hefefefefaaefefef >> { \[17089] , n2858_1, pdn, n2820, \[17596] , preset }; + assign n2874 = 4'h8 >> { n2862, n2875 }; + assign n2875 = 4'h2 >> { n2876, n2864 }; + assign n2876 = 32'd3149642507 >> { \[17609] , \[17674] , n2865, n2877, ppeaki_4_4_ }; + assign n2877 = 16'h0001 >> { ppeaki_5_5_, \[17752] , ppeaki_6_6_, ppeaki_7_7_ }; + assign n2878_1 = 64'h0000077707770777 >> { n2849, \[14510] , n2847, \[5150] , n2851, \[13295] }; + assign n2879 = 64'h0000077707770777 >> { \[5075] , n2874, n2872, \[5030] , n2867, \[9065] }; + assign n653 = 16'hdfdd >> { ppeaka_6_6_, n2897, n2881, n2899 }; + assign n2881 = 64'h7f00ff007f007f00 >> { \[7685] , n2894, n2862, n2887, n2882, n2889 }; + assign n2882 = 64'h0000077707770777 >> { \[4955] , n2885, n2883_1, \[11690] , n2849, \[10745] }; + assign n2883_1 = 4'h2 >> { n2818, n2884 }; + assign n2884 = 4'h8 >> { n2831, n2842 }; + assign n2885 = 4'h2 >> { n2818, n2886 }; + assign n2886 = 8'h80 >> { n2837, n2828, n2842 }; + assign n2887 = 64'h0ddd055501110111 >> { n2888_1, ppeaka_6_6_, n2847, \[15935] , ppeakb_6_6_, n2875 }; + assign n2888_1 = 8'he7 >> { n2837, n2828, n2842 }; + assign n2889 = 16'h0777 >> { \[5870] , n2892, n2890, \[15200] }; + assign n2890 = 4'h2 >> { n2818, n2891 }; + assign n2891 = 8'h08 >> { n2829, n2835, n2831 }; + assign n2892 = 4'h2 >> { n2818, n2893_1 }; + assign n2893_1 = 16'h0008 >> { n2837, n2829, n2828, n2835 }; + assign n2894 = 4'hd >> { n2818, n2895 }; + assign n2895 = 4'he >> { n2846, n2896 }; + assign n2896 = 8'h08 >> { n2828, n2837, n2842 }; + assign n2897 = 4'h1 >> { n2856, n2898_1 }; + assign n2898_1 = 4'h8 >> { n2862, n2854 }; + assign n2899 = 64'h00000ddd0ddd0ddd >> { n2867, \[12560] , ppeaka_7_7_, n2901, n2900, ppeakp_6_6_ }; + assign n2900 = 8'h15 >> { n2826, n2862, n2872 }; + assign n2901 = 4'h8 >> { n2862, n2863_1 }; + assign n678 = 16'h55d5 >> { preset, n2906, \[7655] , n2903_1 }; + assign n2903_1 = 64'h00000ddd0ddd0ddd >> { n2898_1, \[8540] , n2872, \[8825] , n2904, \[4295] }; + assign n2904 = 8'h51 >> { n2905, n2862, n2856 }; + assign n2905 = 64'h2121210808210808 >> { \[18090] , ppeaki_3_3_, \[17531] , n2828, n2835, n2829 }; + assign n2906 = 4'h2 >> { n2825, n2896 }; + assign n683 = 16'h55d5 >> { preset, n2906, \[7640] , n2908_1 }; + assign n2908_1 = 64'h00000ddd0ddd0ddd >> { n2898_1, \[8525] , n2872, \[14225] , n2904, \[4310] }; + assign n489 = 8'hd5 >> { n2867, \[14555] , n2910 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act b/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act new file mode 100644 index 000000000..bdd4aec59 --- /dev/null +++ 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n198 i n113 n48 h n339 +11---- 0 +1-1110 0 +.names n85 n144 h e n229 n92 n340 +1100-0 0 +11100- 0 +.names n237 n343 n339 n244 n243 n340 n341 +01---- 1 +0-1111 1 +.names n m f n246 n188 g n342 +01-0-- 0 +10--10 0 +--0--- 0 +.names n342 n250 n249 n248 n193 n247 n343 +10000- 1 +1000-1 1 +.names i k n53 h n200 g n344 +0010-- 0 +00--11 0 +.names m n255 n114 n344 j h n345 +000-0- 0 +000--0 0 +0--0-- 0 +.names c f h d g e n346 +001-0- 1 +001--1 1 +0101-- 1 +0-010- 1 +100--1 1 +.names j k n270 n144 n46 b n347 +000--- 0 +1--110 0 +.names n347 n264 n350 n263 d a n348 +11-0-- 0 +11--11 0 +--1--- 0 +.names n n269 n200 n114 g n92 n349 +0-0--- 0 +11-0-- 0 +11--11 0 +.names n267 n266 m n349 n136 n n350 +101--- 1 +10-0-- 1 +10--00 1 +.names i m h n45 n202 n232 n351 +0001-- 0 +00101- 0 +01---1 0 +10001- 0 +.names n n280 n279 n274 n276 n275 n352 +0--111 1 +101--- 1 +.names n355 n352 n m n351 n273 n353 +0111-- 1 +01-01- 1 +01--10 1 +0-00-- 1 +.names m n235 i n113 n226 n229 n354 +011--- 1 +01---0 1 +1--10- 1 +.names g n272 n n354 n198 n200 n355 +01---- 1 +0-01-- 1 +0---10 1 +.names l n79 n193 n171 n153 f n356 +00---- 0 +0-0--- 0 +1--110 0 +.names n290 n288 n257 n256 n203 n140 n357 +1110-- 1 +111-0- 1 +11-0-0 1 +11--00 1 +.names n357 n356 n287 n361 l j n358 +10000- 1 +11001- 1 +1-0000 1 +.names n l c j g e n359 +000-0- 1 +000--1 1 +11-1-- 1 +.names n359 m n161 l f n49 n360 +1011-0 0 +101-0- 0 +10-00- 0 +.names i n360 n285 n286 n284 n212 n361 +0----- 0 +-11000 0 +.names n161 n156 k n153 m n154 n362 +10---- 1 +--1100 1 +.names n147 n139 n145 n362 j i n363 +1100-- 1 +110-11 1 +.names n363 n151 n149 n138 k n301 n2 +11000- 0 +1100-0 0 +.names b d f c e a n365 +0010-- 0 +01001- 0 +0-010- 0 +0----0 0 +10-101 0 +11111- 0 +-00-0- 0 +-1---0 0 +--0--0 0 +.names h n105 n165 n365 n91 j n366 +100--- 0 +1--110 0 +.names i j n156 n84 n152 m n367 +100--- 1 +10--00 1 +--01-- 1 +.names n366 n302 n162 n151 n367 k o2 +11110- 0 +1111-0 0 +.names n136 n99 n53 a m n n369 +111110 1 +.names k n201 n369 n204 n203 n92 n370 +0--111 0 +1-1--- 0 +-1---- 0 +.names n56 n370 n223 n197 n37 n371 +11000 1 +.names k j n257 g m n232 n372 +10---1 0 +1-00-- 0 +1---0- 0 +-000-- 0 +-0--0- 0 +.names n258 n260 n259 i m n346 n373 +0001-- 1 +000-1- 1 +000--0 1 +.names n261 n373 m n372 n256 n374 +1100- 1 +1111- 1 +11-10 1 +.names e c f n253 n254 n161 n375 +0100-- 0 +010--1 0 +1000-- 0 +----1- 0 +.names n374 n345 n m n375 n252 n376 +11-1-- 1 +11--10 1 +--1--- 1 +.names n358 n353 n376 n341 n338 n348 l2 +111110 0 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v b/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v new file mode 100644 index 000000000..d74a2cd7a --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v @@ -0,0 +1,712 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module misex3(a, b, c, d, e, f, g, h, i, j, k, l, m, n, r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2); + input a; + input b; + input c; + input d; + input e; + input f; + input g; + input h; + output h2; + input i; + output i2; + input j; + output j2; + input k; + output k2; + input l; + output l2; + input m; + output m2; + input n; + wire n100; + wire n101; + wire n102; + wire n103; + wire n104; + wire n105; + wire n106; + wire n107; + wire n108; + wire n109; + wire n110; + wire n111; + wire n112; + wire n113; + wire n114; + wire n115; + wire n116; + wire n117; + wire n118; + wire n119; + wire n120; + wire n121; + wire n122; + wire n123; + wire n124; + wire n125; + wire n126; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + output n2; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n290; + wire n291; + wire n292; + wire n294; + wire n296; + wire n297; + wire n298; + wire n299; + wire n301; + wire n302; + wire n303; + wire n304; + wire n306; + wire n308; + wire n309; + wire n31; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n316; + wire n317; + wire n318; + wire n319; + wire n32; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n33; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n337; + wire n338; + wire n339; + wire n34; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n35; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n36; + wire n360; + wire n361; + wire n362; + wire n363; + wire n365; + wire n366; + wire n367; + wire n369; + wire n37; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n38; + wire n39; + wire n40; + wire n41; + wire n42; + wire n43; + wire n44; + wire n45; + wire n46; + wire n47; + wire n48; + wire n49; + wire n50; + wire n51; + wire n52; + wire n53; + wire n54; + wire n55; + wire n56; + wire n57; + wire n58; + wire n59; + wire n60; + wire n61; + wire n62; + wire n63; + wire n64; + wire n65; + wire n66; + wire n67; + wire n68; + wire n69; + wire n70; + wire n71; + wire n72; + wire n73; + wire n74; + wire n75; + wire n76; + wire n77; + wire n78; + wire n79; + wire n80; + wire n81; + wire n82; + wire n83; + wire n84; + wire n85; + wire n86; + wire n87; + wire n88; + wire n89; + wire n90; + wire n91; + wire n92; + wire n93; + wire n94; + wire n96; + wire n97; + wire n98; + wire n99; + output o2; + output p2; + output q2; + output r2; + output s2; + output t2; + output u2; + assign n31 = 64'hf5fdf7fff7fff7ff >> { n35, h, n32, d, g, e }; + assign n40 = 4'h8 >> { d, b }; + assign n130 = 32'd16843008 >> { n120, n131, n134, n135, n132 }; + assign n131 = 64'hf7ff7f7f77ff7fff >> { l, h, k, g, n33, i }; + assign n132 = 16'h8000 >> { n84, n75, n71, n133 }; + assign n133 = 16'h0008 >> { n, d, c, a }; + assign n134 = 32'd32768 >> { l, n109, n33, i, k }; + assign n135 = 32'd2147483648 >> { n136, n66, n99, n137, c }; + assign n136 = 4'h2 >> { j, i }; + assign n137 = 8'h02 >> { m, n, l }; + assign n138 = 32'd572530720 >> { n92, l, n84, n105, n79 }; + assign n139 = 16'h2202 >> { n108, n78, n125, n126 }; + assign n41 = 8'h08 >> { n42, n45, c }; + assign n140 = 4'h2 >> { l, n33 }; + assign n141 = 8'ha2 >> { n142, n52, n143 }; + assign n142 = 32'd1465350135 >> { c, d, e, f, b }; + assign n143 = 32'd4160749439 >> { f, d, e, h, b }; + assign n144 = 4'h2 >> { m, n }; + assign n145 = 64'h0000088000000800 >> { n32, n120, n140, j, k, g }; + assign n146 = 8'h08 >> { h, i, g }; + assign n147 = 64'h5555555555551555 >> { n120, h, g, i, n91, n148 }; + assign n148 = 32'd128 >> { l, j, n33, n109, k }; + assign n149 = 64'h0008000808080008 >> { n120, g, n105, i, h, n150 }; + assign n42 = 8'h27 >> { n44, n43, h }; + assign n150 = 16'h0008 >> { j, n, m, l }; + assign n151 = 64'h1111111111110111 >> { n152, m, i, n113, n158, n155 }; + assign n152 = 16'hdd0d >> { n154, n153, n141, n }; + assign n153 = 4'h8 >> { h, g }; + assign n154 = 64'hfd75727f7d75727f >> { f, c, d, e, b, n }; + assign n155 = 16'h0080 >> { n156, n113, i, h }; + assign n156 = 64'hfefefefedcfefefe >> { b, f, c, n157, m, n }; + assign n157 = 32'd2503415095 >> { g, e, d, f, c }; + assign n158 = 64'ha0a8a0a8a8a8a0a8 >> { f, n107, n159, n109, g, n160 }; + assign n159 = 64'ha7a777b7272f553f >> { c, e, d, b, f, a }; + assign n43 = 64'h02080a080a080a08 >> { i, l, j, m, k, n }; + assign n160 = 32'd128 >> { n, k, j, m, h }; + assign n161 = 4'h8 >> { k, h }; + assign n162 = 8'h45 >> { n79, n110, n163 }; + assign n163 = 32'd134785544 >> { n154, n146, n164, n, n117 }; + assign n164 = 64'h3133313331331111 >> { g, n142, n68, f, n59, n84 }; + assign n165 = 32'd3445485439 >> { n150, j, n33, i, k }; + assign n166 = 32'd1431589972 >> { n76, j, n168, n167, n120 }; + assign n167 = 8'h08 >> { n, n73, g }; + assign n168 = 32'd2290092032 >> { j, l, k, n146, n33 }; + assign n169 = 32'd1414813012 >> { n109, n106, h, n170, n158 }; + assign n44 = 64'h0800080008080800 >> { j, l, k, m, n, i }; + assign n170 = 32'd1431639381 >> { k, n33, l, i, n171 }; + assign n171 = 32'd32768 >> { n, i, m, j, k }; + assign n172 = 64'h00fd00ff00fd00fd >> { n72, n106, n, n175, n173, n174 }; + assign n173 = 64'h0808080888080808 >> { n120, n136, g, n110, k, n75 }; + assign n174 = 64'hffffdff7fff7dff7 >> { n110, n120, g, j, h, n75 }; + assign n175 = 4'h2 >> { n157, n176 }; + assign n176 = 64'h0000000000008000 >> { i, m, l, j, k, h }; + assign n177 = 64'h02080a0200080800 >> { i, j, k, n156, h, l }; + assign n178 = 64'h0000800800008000 >> { h, n120, n113, g, n33, l }; + assign n179 = 64'h0080008000000080 >> { n109, n106, h, l, j, n33 }; + assign n45 = 4'h8 >> { n46, b }; + assign n180 = 32'd4160223061 >> { n142, g, f, n68, n84 }; + assign n181 = 16'h0080 >> { b, f, c, n176 }; + assign n182 = 64'h0f0d0f0d0d0d0f0d >> { n184, n153, n141, n183, i, n144 }; + assign n183 = 64'h0000000000000080 >> { i, c, e, n48, n153, d }; + assign n184 = 32'd3012899733 >> { f, e, d, b, c }; + assign n185 = 32'd32768 >> { n50, c, d, b, a }; + assign n186 = 16'h0080 >> { j, n109, n79, i }; + assign n187 = 16'h8000 >> { n67, n137, n188, n189 }; + assign n188 = 8'h02 >> { c, d, e }; + assign n189 = 8'h02 >> { j, k, i }; + assign n46 = 4'h2 >> { f, e }; + assign n190 = 16'h2227 >> { n191, n195, n125, n94 }; + assign n191 = 64'h8080808088808080 >> { g, n114, n193, n192, n194, n48 }; + assign n192 = 64'h0000000080000000 >> { g, j, i, k, h, l }; + assign n193 = 4'h1 >> { i, h }; + assign n194 = 8'h01 >> { f, c, d }; + assign n195 = 8'h80 >> { n66, n188, n196 }; + assign n196 = 64'h0000000000000080 >> { i, m, n, j, l, k }; + assign n197 = 32'd8 >> { f, g, e, n200, n198 }; + assign n198 = 4'h8 >> { n199, h }; + assign n199 = 64'h0000000000008000 >> { m, n, i, l, j, k }; + assign n47 = 64'h92135757ffffffff >> { n48, i, l, j, k, h }; + assign n200 = 4'h1 >> { c, d }; + assign n201 = 32'd128 >> { m, h, n202, n114, n92 }; + assign n202 = 64'h8000000000000000 >> { f, g, c, e, d, b }; + assign n203 = 8'h01 >> { l, m, n }; + assign n204 = 64'h0000000080000000 >> { h, f, g, c, e, d }; + assign n205 = 64'h0000000000000008 >> { n211, n214, n218, n219, n206, n216 }; + assign n206 = 16'h7d7f >> { n208, n209, n207, n210 }; + assign n207 = 8'h80 >> { n53, n, e }; + assign n208 = 8'h08 >> { h, n100, n53 }; + assign n209 = 8'h08 >> { b, d, c }; + assign n48 = 4'h1 >> { m, n }; + assign n210 = 64'h0000000000000080 >> { i, m, h, j, k, l }; + assign n211 = 16'h0008 >> { e, d, n212, n213 }; + assign n212 = 32'd2 >> { k, f, g, c, n48 }; + assign n213 = 4'h2 >> { l, n193 }; + assign n214 = 64'h0000000080000000 >> { f, n48, n215, n189, l, n153 }; + assign n215 = 8'h08 >> { e, c, d }; + assign n216 = 32'd2139062271 >> { n196, n217, n53, n210, n215 }; + assign n217 = 64'h0000000000008000 >> { f, e, c, g, d, b }; + assign n218 = 16'h8000 >> { n43, n52, n85, e }; + assign n219 = 32'd128 >> { m, k, l, n217, n220 }; + assign n49 = 8'h80 >> { c, e, d }; + assign n220 = 8'h08 >> { j, i, h }; + assign n221 = 16'h0008 >> { n54, c, b, a }; + assign n222 = 16'h0080 >> { g, n84, n85, n58 }; + assign n223 = 16'h22a2 >> { n42, n63, n61, n209 }; + assign j2 = 16'hfff7 >> { n197, n228, n330, n327 }; + assign n225 = 8'h02 >> { m, k, l }; + assign n226 = 64'h0000000000008000 >> { e, a, f, d, b, c }; + assign n227 = 64'h8000000000000000 >> { n53, n225, n209, n220, n, e }; + assign n228 = 32'd32768 >> { g, n193, n194, n229, n203 }; + assign n229 = 4'h1 >> { j, k }; + assign n32 = 4'h2 >> { n34, n33 }; + assign n50 = 8'h15 >> { n53, n32, n51 }; + assign k2 = 64'hddddddddddddfddd >> { f, g, n198, n188, n211, n333 }; + assign n231 = 64'h8000000000000000 >> { l, j, i, m, k, h }; + assign n232 = 64'h8000000000000000 >> { f, c, e, d, b, a }; + assign n233 = 64'h0000000000008000 >> { i, f, n137, n229, n52, n215 }; + assign n234 = 32'd2 >> { j, i, f, e, n52 }; + assign n235 = 8'h02 >> { f, e, c }; + assign n236 = 64'h1111111101111111 >> { i, n203, n204, n113, n201, n191 }; + assign n237 = 32'd2863311522 >> { n238, n240, n241, n242, g }; + assign n238 = 64'h00ffffff00808080 >> { n239, c, b, h, n171, l }; + assign n239 = 64'h0001000000010001 >> { c, n, i, h, m, e }; + assign n51 = 8'h08 >> { f, n35, n52 }; + assign n240 = 64'h3120202020202020 >> { i, n48, n113, n199, d, h }; + assign n241 = 32'd134742024 >> { a, n85, k, n220, n33 }; + assign n242 = 64'hfff7fff7fff7fdf5 >> { i, f, e, m, n, n200 }; + assign n243 = 64'h1113131313131313 >> { n84, n113, b, n213, f, n144 }; + assign n244 = 32'd353703253 >> { d, a, n193, n150, n245 }; + assign n245 = 64'h0222020200220002 >> { b, d, c, e, g, n144 }; + assign n246 = 64'hfffabffafffa9dd8 >> { i, e, c, b, a, d }; + assign n247 = 64'hbbbfbbbb9b9f9b9b >> { j, b, k, l, n, m }; + assign n248 = 64'h0000008000080088 >> { c, b, m, n, n161, n118 }; + assign n249 = 32'd134752776 >> { k, n220, g, n200, n48 }; + assign n52 = 4'h2 >> { g, h }; + assign n250 = 32'd1145328708 >> { n, n231, g, n251, a }; + assign n251 = 64'h0008000000080008 >> { h, k, n, e, m, d }; + assign n252 = 64'h080a000200020002 >> { n49, f, h, j, i, g }; + assign n253 = 32'd368918013 >> { k, g, h, j, i }; + assign n254 = 8'h80 >> { n63, n113, n84 }; + assign n255 = 32'd4278120190 >> { d, n136, g, c, f }; + assign n256 = 16'h8000 >> { n49, i, f, g }; + assign n257 = 64'h7decfdecfdecfdec >> { c, b, f, a, e, d }; + assign n258 = 64'h0000000000000028 >> { j, m, k, i, g, h }; + assign n259 = 64'h0000000000000008 >> { l, j, m, k, i, h }; + assign n53 = 4'h2 >> { f, g }; + assign n260 = 64'h0000000000000080 >> { m, k, h, i, j, f }; + assign n261 = 64'h00ff007f007f007f >> { d, e, n262, g, n231, f }; + assign n262 = 64'h0000000000000008 >> { j, m, k, g, f, h }; + assign n263 = 16'h0002 >> { n, f, e, m }; + assign n264 = 32'd572654114 >> { i, n200, n48, n265, h }; + assign n265 = 32'd32768 >> { m, n229, n, e, b }; + assign n266 = 64'h0444044455550444 >> { k, n150, d, c, n144, i }; + assign n267 = 32'd2863311402 >> { i, d, c, n48, n268 }; + assign n268 = 32'd1431655761 >> { l, n, k, i, h }; + assign n269 = 64'hfffdfff0bbb9fff0 >> { k, g, f, b, j, e }; + assign n54 = 64'hdd5dff7fff7fff7f >> { n35, h, n34, n33, g, f }; + assign n270 = 64'h5555401155554051 >> { n46, m, n, d, c, n271 }; + assign n271 = 64'h000000080002000a >> { c, b, m, e, n, i }; + assign n272 = 32'd1145328708 >> { i, n48, c, n79, h }; + assign n273 = 32'd128 >> { e, a, n113, d, g }; + assign n274 = 32'd3149642507 >> { h, g, f, n229, l }; + assign n275 = 32'd4008619758 >> { c, d, n46, a, b }; + assign n276 = 64'h2031313131313131 >> { n193, n46, l, n277, n278, j }; + assign n277 = 64'hfffaeeeaeeeaeeea >> { a, d, h, g, e, f }; + assign n278 = 64'h0000000000008000 >> { j, k, i, h, g, e }; + assign n279 = 8'h01 >> { n258, n259, n260 }; + assign n55 = 32'd526344 >> { d, e, n47, c, f }; + assign n280 = 64'h000800020008000a >> { j, i, m, b, k, n46 }; + assign n281 = 32'd2004317959 >> { h, e, f, n49, n67 }; + assign n282 = 64'haa08aa00aa08aa08 >> { d, n193, n235, c, g, n203 }; + assign n283 = 64'hf3a2f3a2a2a2f3a2 >> { d, n46, c, j, n202, b }; + assign n284 = 64'h0000000000000002 >> { j, m, n, c, d, k }; + assign n285 = 64'hffbbdf9bdf9bdf9b >> { k, l, n277, n202, m, n }; + assign n286 = 64'ha8a8a8a0a8a0a8a0 >> { n200, g, n235, n204, j, n48 }; + assign n287 = 64'h0002000200000002 >> { k, n39, f, g, b, n144 }; + assign n288 = 32'd1427457285 >> { a, b, n263, c, n289 }; + assign n289 = 64'h0000000000000080 >> { j, m, k, n, h, f }; + assign n56 = 8'h15 >> { n59, n58, n57 }; + assign n290 = 64'h07f7f7f707777777 >> { k, n63, n199, h, n33, n232 }; + assign n291 = 64'h3131313131311131 >> { e, n60, f, n31, n55, b }; + assign n292 = 64'h0202020202000202 >> { n61, n40, c, n62, n64, n56 }; + assign r2 = 16'hff7f >> { n69, n292, n36, n291 }; + assign n294 = 64'hd5d5d5d580d5d5d5 >> { n47, d, f, n83, n56, c }; + assign s2 = 64'hffffffffffffff7f >> { n69, n86, n93, n77, n36, n294 }; + assign n296 = 64'h4c44dc5ca800a808 >> { h, j, i, l, k, g }; + assign n297 = 32'd2934894318 >> { m, e, n296, n70, n }; + assign n298 = 64'hf7a2f7f7ffa2fff7 >> { n109, l, n106, k, j, h }; + assign n299 = 64'hf7f7f7f7f7f7f777 >> { n110, n113, n114, n298, m, i }; + assign n57 = 32'd32768 >> { e, n40, h, f, n43 }; + assign u2 = 32'd2004318039 >> { n115, n119, n299, n, n122 }; + assign n301 = 64'h020f0202222f2222 >> { i, n140, n106, j, n141, n144 }; + assign n302 = 64'hbbbbbbbbabbbbbbb >> { j, h, n33, k, n76, n120 }; + assign n303 = 64'hff87ff87ff878880 >> { m, n152, n156, h, i, k }; + assign n304 = 64'h4444ccc4ccc4ccc4 >> { n71, n133, n, n106, n169, n73 }; + assign p2 = 32'd3724410365 >> { n303, n162, j, n166, n304 }; + assign n306 = 64'hdddddddddddd0ddd >> { n105, j, i, n79, n182, k }; + assign q2 = 64'hfffdfffdfdfdfffd >> { n163, n306, l, n149, n172, n309 }; + assign n308 = 64'hfffffdf7fdfdfdf5 >> { n180, n141, k, m, j, l }; + assign n309 = 64'h0002000202020002 >> { n181, n308, n, n179, n177, n313 }; + assign n58 = 32'd538976800 >> { j, l, k, m, n }; + assign n310 = 32'd2147516930 >> { n154, n71, n133, m, l }; + assign n311 = 64'h2725252526202020 >> { n146, h, g, n133, k, j }; + assign n312 = 16'hff7f >> { n133, n59, n39, n144 }; + assign n313 = 16'h0222 >> { n311, n310, n178, n312 }; + assign n314 = 64'h020666660a066e66 >> { e, n297, d, n54, b, a }; + assign h2 = 64'hfbbbfbbbfffffbbb >> { n190, n54, c, n314, n318, n185 }; + assign n316 = 64'h2020202022202020 >> { g, h, n150, n76, d, a }; + assign n317 = 64'h0001000000010001 >> { n133, n70, n134, n148, n186, n187 }; + assign n318 = 32'd35791394 >> { e, c, n316, n132, n317 }; + assign n319 = 64'hdfdfdfdfdfdf55df >> { c, n42, g, f, n60, n40 }; + assign n59 = 64'h0000000000008000 >> { h, e, f, i, d, b }; + assign i2 = 32'd2147483647 >> { n319, n371, n205, n322, n318 }; + assign n321 = 64'h0a0f2a2f2a2f2a2f >> { n53, n32, n82, n94, n51, n54 }; + assign n322 = 64'h0101010101011101 >> { n104, n222, n321, e, n221, n324 }; + assign n323 = 64'h0220222202002222 >> { n75, n87, h, n74, f, g }; + assign n324 = 32'd2155907200 >> { n, n323, n51, a, n99 }; + assign n325 = 64'hffffffffffff7fff >> { m, h, n, e, n53, n209 }; + assign n326 = 64'hffd5d5d5d5d5d5d5 >> { n52, n33, n226, n48, n208, n325 }; + assign n327 = 64'haaaaaaaa2aaaaaaa >> { k, i, n326, j, l, n216 }; + assign n328 = 64'h0000000000008000 >> { j, k, i, l, h, g }; + assign n329 = 64'h08080808ff080808 >> { f, n100, n48, n, m, n226 }; + assign n33 = 4'h2 >> { n, m }; + assign n60 = 32'd3470778335 >> { n58, i, n43, g, h }; + assign n330 = 64'h0000000100010001 >> { n329, n328, n195, n214, n219, n227 }; + assign n331 = 64'h8808800080008000 >> { f, n49, n232, m, k, g }; + assign n332 = 64'h8888008000800080 >> { n117, n202, n, n331, i, h }; + assign n333 = 32'd143165576 >> { n332, j, l, n206, n330 }; + assign n334 = 64'h0000000080000000 >> { a, g, n39, n79, n193, n235 }; + assign n335 = 64'h9dbfbfbfbfbfbfbf >> { c, n225, n234, n334, b, d }; + assign m2 = 64'hffffffffffff7fff >> { n187, n233, n335, n236, n327, n333 }; + assign n337 = 64'h22222222a2222222 >> { n114, n49, g, f, n281, n48 }; + assign n338 = 64'h0404000455550055 >> { n144, i, n337, n192, n283, n282 }; + assign n339 = 64'h7777777757777777 >> { h, n48, n113, i, n198, c }; + assign n61 = 16'h5d7f >> { n44, n43, h, f }; + assign n340 = 64'hffffff7ffff7ff77 >> { n92, n229, e, h, n144, n85 }; + assign n341 = 64'h5444444444444444 >> { n340, n243, n244, n339, n343, n237 }; + assign n342 = 64'hf0b0f0b0d090f0b0 >> { g, n188, n246, f, m, n }; + assign n343 = 64'h0002000200000002 >> { n247, n193, n248, n249, n250, n342 }; + assign n344 = 64'heeeeffefffefffef >> { g, n200, h, n53, k, i }; + assign n345 = 64'hffaafeaafeaafeaa >> { h, j, n344, n114, n255, m }; + assign n346 = 64'h1612171204001510 >> { e, g, d, h, f, c }; + assign n347 = 64'hfefefefe54fefefe >> { b, n46, n144, n270, k, j }; + assign n348 = 64'h07070f070f070f07 >> { a, d, n263, n350, n264, n347 }; + assign n349 = 64'h7272fa72fa72fa72 >> { n92, g, n114, n200, n269, n }; + assign n62 = 32'd128 >> { n42, d, c, n63, b }; + assign n350 = 64'h2022202220222222 >> { n, n136, n349, m, n266, n267 }; + assign n351 = 64'hbaa9babbfeedfeff >> { n232, n202, n45, h, m, i }; + assign n352 = 64'h7520202020202020 >> { n275, n276, n274, n279, n280, n }; + assign n353 = 64'h4045400544454005 >> { n273, n351, m, n, n352, n355 }; + assign n354 = 64'h4040ea404444ee44 >> { n229, n226, n113, i, n235, m }; + assign n355 = 64'h4544454455554544 >> { n200, n198, n354, n, n272, g }; + assign n356 = 64'heaeaeaea40eaeaea >> { f, n153, n171, n193, n79, l }; + assign n357 = 64'h0080808000888888 >> { n140, n203, n256, n257, n288, n290 }; + assign n358 = 64'h000800020008000a >> { j, l, n361, n287, n356, n357 }; + assign n359 = 64'h8901890188008901 >> { e, g, j, c, l, n }; + assign n63 = 4'h2 >> { e, g }; + assign n360 = 64'hffffdfdddfffdfdd >> { n49, f, l, n161, m, n359 }; + assign n361 = 64'haaaaaaaaaaaaaa2a >> { n212, n284, n286, n285, n360, i }; + assign n362 = 64'h222222222222f222 >> { n154, m, n153, k, n156, n161 }; + assign n363 = 64'h0808000800080008 >> { i, j, n362, n145, n139, n147 }; + assign n2 = 64'hfffffff7fff7fff7 >> { n301, k, n138, n149, n151, n363 }; + assign n365 = 64'h7febd8ec20202020 >> { a, e, c, f, d, b }; + assign n366 = 64'hfdfdfdfd55fdfdfd >> { j, n91, n365, n165, n105, h }; + assign n367 = 64'h0f020f020f022f22 >> { m, n152, n84, n156, j, i }; + assign o2 = 64'hffff7fff7fff7fff >> { k, n367, n151, n162, n302, n366 }; + assign n369 = 64'h0000000080000000 >> { n, m, a, n53, n99, n136 }; + assign n64 = 4'h2 >> { n65, n68 }; + assign n370 = 64'h0213131313131313 >> { n92, n203, n204, n369, n201, k }; + assign n371 = 32'd8 >> { n37, n197, n223, n370, n56 }; + assign n372 = 64'hddd44444fff44444 >> { n232, m, g, n257, j, k }; + assign n373 = 64'h0101010001010101 >> { n346, m, i, n259, n260, n258 }; + assign n374 = 32'd2148042760 >> { n256, n372, m, n373, n261 }; + assign n375 = 64'h0000fbf90000fff9 >> { n161, n254, n253, f, c, e }; + assign n376 = 64'hf8f0f8f0f8f8f8f0 >> { n252, n375, m, n, n345, n374 }; + assign l2 = 64'hffffffff7fffffff >> { n348, n338, n341, n376, n353, n358 }; + assign n65 = 16'h0777 >> { n66, n44, n43, n67 }; + assign n66 = 8'h08 >> { h, f, g }; + assign n67 = 8'h80 >> { h, f, g }; + assign n68 = 8'h08 >> { d, e, b }; + assign n69 = 8'h02 >> { n297, a, n40 }; + assign n34 = 32'd2416120153 >> { l, h, i, j, k }; + assign n70 = 32'd521084703 >> { h, n74, n71, n72, n73 }; + assign n71 = 4'h8 >> { g, e }; + assign n72 = 16'h0080 >> { k, j, m, l }; + assign n73 = 32'd134219784 >> { k, l, i, m, j }; + assign n74 = 16'hd5f7 >> { j, i, l, m }; + assign n75 = 4'h8 >> { l, m }; + assign n76 = 32'd128 >> { n, g, k, h, m }; + assign n77 = 32'd1423760604 >> { n82, n63, n81, n42, n80 }; + assign n78 = 32'd32768 >> { j, n79, i, f, g }; + assign n79 = 8'h08 >> { n, m, k }; + assign n35 = 32'd538976800 >> { j, l, k, n, m }; + assign n80 = 32'd128 >> { j, n, m, i, k }; + assign n81 = 64'hf7f7f7f7f7f777f7 >> { e, d, g, b, c, f }; + assign n82 = 8'h08 >> { c, d, a }; + assign n83 = 64'hfff7fff7f7f7fff7 >> { n47, d, n60, e, c, f }; + assign n84 = 4'h2 >> { h, i }; + assign n85 = 8'h80 >> { c, d, b }; + assign n86 = 16'haa2a >> { n88, n90, n54, n82 }; + assign n87 = 32'd3749142487 >> { i, l, j, k, m }; + assign n88 = 64'h0040404455555555 >> { n89, n74, n87, h, n63, n }; + assign n89 = 64'hfff7ffd7ffffffdf >> { i, j, e, h, g, n75 }; + assign n36 = 32'd286330897 >> { f, n49, n47, n41, n37 }; + assign n90 = 32'd3149597627 >> { n92, n63, n91, n76, e }; + assign n91 = 8'h08 >> { l, n33, k }; + assign n92 = 4'h2 >> { i, j }; + assign n93 = 32'd9076874 >> { n50, n54, e, d, n94 }; + assign n94 = 8'h08 >> { b, c, a }; + assign t2 = 64'hfffdfffdfffffffd >> { c, n104, n102, n103, n101, n96 }; + assign n96 = 64'h50d850d850d872fa >> { n100, n98, n64, n97, n47, f }; + assign n97 = 64'hdf57ffffdf57dfff >> { d, c, n47, b, n42, n46 }; + assign n98 = 4'h8 >> { n99, c }; + assign n99 = 4'h2 >> { d, e }; + assign n37 = 16'h0080 >> { n38, n40, n33, a }; + assign n100 = 8'h08 >> { c, e, d }; + assign n101 = 32'd17367048 >> { b, e, n54, d, a }; + assign n102 = 32'd2621472 >> { d, n61, c, b, e }; + assign n103 = 64'h1232100012221020 >> { c, e, d, a, n54, b }; + assign n104 = 64'h0088000800800000 >> { n44, n43, f, h, n40, g }; + assign n105 = 4'h2 >> { n109, n106 }; + assign n106 = 64'hd5ddf5ff55557577 >> { n108, n107, n82, e, f, g }; + assign n107 = 32'd2829617160 >> { b, c, d, e, a }; + assign n108 = 32'd3012899733 >> { e, d, c, a, b }; + assign n109 = 32'd32768 >> { d, c, e, g, a }; + assign n38 = 64'hefcdefcdefcdffdd >> { k, n39, n34, h, e, g }; + assign n110 = 64'h1011111100110111 >> { n108, n107, n52, f, n112, n111 }; + assign n111 = 64'h0000000000000080 >> { g, c, e, h, d, a }; + assign n112 = 64'h0000000000008000 >> { g, d, c, e, h, a }; + assign n113 = 4'h2 >> { k, j }; + assign n114 = 4'h1 >> { l, k }; + assign n115 = 64'h88888888a8888888 >> { m, k, n66, i, n116, n98 }; + assign n116 = 32'd134785544 >> { n118, n117, m, n113, n67 }; + assign n117 = 4'h2 >> { m, k }; + assign n118 = 8'h80 >> { l, j, i }; + assign n119 = 64'h5111111111111111 >> { i, g, n75, n113, n121, n120 }; + assign n39 = 4'h2 >> { j, l }; + assign n120 = 16'hf777 >> { a, f, b, e }; + assign n121 = 64'hffffff7f7fffffff >> { l, j, g, m, h, i }; + assign n122 = 64'h0000000000000080 >> { n62, n128, n129, n123, n124, n130 }; + assign n123 = 64'hfdfdfdfd00fdfdfd >> { n106, i, n91, n65, e, n40 }; + assign n124 = 32'd33685506 >> { n108, n78, n127, n125, n126 }; + assign n125 = 32'd2860548224 >> { n53, n107, n63, n82, n80 }; + assign n126 = 64'hf7fff7fff7f7f7ff >> { n120, g, n109, j, i, n79 }; + assign n127 = 64'h0088000800800000 >> { n44, n43, c, h, n71, b }; + assign n128 = 64'h0200020008080200 >> { f, e, c, n42, b, g }; + assign n129 = 64'h020a080200080800 >> { d, f, e, n47, c, g }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act b/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act new file mode 100644 index 000000000..f69feb9e5 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act @@ -0,0 +1,1422 @@ +i_0_ 0.492200 0.507800 +i_1_ 0.488800 0.509400 +i_2_ 0.494200 0.497800 +i_3_ 0.505200 0.489400 +i_4_ 0.496000 0.502600 +i_5_ 0.500600 0.502400 +i_6_ 0.510200 0.487000 +i_7_ 0.486600 0.508800 +i_8_ 0.505800 0.506800 +i_9_ 0.494400 0.501800 +i_10_ 0.508800 0.503600 +i_11_ 0.508600 0.499200 +i_12_ 0.504800 0.514600 +i_13_ 0.513600 0.510600 +i_14_ 0.505200 0.499800 +i_15_ 0.500200 0.502600 +o_6_ 0.131000 0.028811 +o_5_ 0.021200 0.000159 +n61 0.000000 0.000000 +n62 0.002800 0.000006 +n63 0.117800 0.024503 +n64 0.015200 0.000548 +n65 0.006800 0.000123 +n66 0.120400 0.026116 +n67 0.065400 0.007475 +n68 0.995400 0.039074 +n69 0.015200 0.000526 +n70 0.124000 0.027070 +n71 0.117200 0.028259 +n72 0.000000 0.003481 +n73 0.001800 0.000011 +n74 0.018600 0.000529 +n75 0.957600 0.021374 +n76 0.132800 0.030036 +n77 0.001800 0.025253 +n78 0.245800 0.094385 +n79 0.006400 0.000102 +n80 0.059600 0.007674 +n81 0.008400 0.000122 +n82 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0.000000 +n1436 1.000000 0.000000 +n1437 0.999400 0.014754 +n1438 0.998800 0.000000 +n1439 0.997400 0.005570 +n1440 0.999600 0.000000 +o_18_ 0.017000 0.000013 +n1442 0.986800 0.073988 +n1443 0.998000 0.001198 +n1444 0.931200 0.118732 +n1445 0.028400 0.000747 +n1446 1.000000 0.000000 +n1447 0.999600 0.000000 +n1448 1.000000 0.000000 +n1449 0.999400 0.001198 +n1450 0.999600 0.000013 +n1451 0.999600 0.000000 +n1452 0.999800 0.000000 +n1453 0.998000 0.003984 +n1454 0.999400 0.000000 +n1455 0.998800 0.000000 +n1456 0.998600 0.000000 +n1457 1.000000 0.006884 +n1458 0.999800 0.000000 +n1459 0.001200 0.095078 +n1460 0.999200 0.000000 +n1461 0.999200 0.000000 +n1462 0.999800 0.000000 +n1463 0.998600 0.000000 +n1464 0.998000 0.004085 diff --git a/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif b/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif new file mode 100644 index 000000000..4adca05ae --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif @@ -0,0 +1,4513 @@ +# Benchmark "pdc" written by ABC on Tue Mar 12 09:31:09 2019 +.model pdc +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ + i_13_ i_14_ i_15_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ \ + o_12_ o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ \ + o_24_ o_25_ o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ o_35_ \ + o_36_ o_37_ o_38_ o_39_ +.names i_3_ i_0_ i_1_ o_6_ +100 1 +.names n1248 n1246 n1243 n1240 n217 n1219 o_5_ +111111 0 +.names n65 n62 n68 n61 +11- 1 +1-0 1 +.names n64 n63 n62 +11 1 +.names i_6_ i_7_ i_8_ n63 +110 1 +.names i_3_ i_5_ i_4_ i_2_ i_0_ i_1_ n64 +000000 1 +.names n67 n66 n65 +11 1 +.names i_14_ i_12_ i_13_ n66 +110 1 +.names i_15_ i_11_ i_9_ i_10_ n67 +1100 1 +.names n69 n71 n70 n68 +0-- 1 +-00 1 +.names i_4_ i_3_ i_5_ i_2_ i_0_ i_1_ n69 +100000 1 +.names i_7_ i_8_ i_6_ n70 +100 1 +.names i_8_ i_7_ i_6_ n71 +000 1 +.names n73 n75 n72 +10 1 +.names n70 n74 n73 +11 1 +.names i_4_ i_5_ i_3_ i_2_ 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n1366 +111111 1 +.names n94 n630 n89 n744 n250 n787 n1367 +11---- 0 +1--0-- 0 +-11--- 0 +----10 0 +.names n660 n736 n146 n569 n500 n174 n1368 +0110-- 1 +011-1- 1 +0--0-0 1 +0---10 1 +.names n1367 n1118 n1117 n696 n1368 n1119 n1369 +111110 1 +.names n787 n328 n220 n87 n200 n207 n1370 +11000- 0 +1100-0 0 +.names n1123 n799 n1125 n1124 n1122 n1121 n1371 +110000 1 +.names n1371 n638 n621 n558 n1370 n164 n1372 +10000- 1 +1000-0 1 +.names n1170 n330 n159 n174 n719 n714 n1373 +110--- 1 +11--11 1 +1-00-- 1 +.names n1360 n1171 n1382 n819 n1373 n1374 +11111 1 +.names n1138 n1137 n174 n964 n645 n379 n1375 +110--- 1 +11-110 1 +.names n1375 n641 n643 n130 n980 n1376 +1100- 1 +110-1 1 +.names n1167 n68 n633 n151 n169 n237 n1377 +1110-- 1 +11-00- 1 +1-1--0 1 +1---00 1 +.names n311 n170 n289 n333 n259 n169 n1378 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n1165 n266 n1378 n250 n79 n97 n1379 +1110-- 1 +111-00 1 +.names n549 n689 n691 n279 n119 n62 n1380 +000--- 1 +0--100 1 +.names n824 n1168 n1169 n551 n146 n159 n1381 +11001- 1 +1100-0 1 +.names n1380 n1381 n141 n259 n62 n94 n1382 +110--- 1 +11-000 1 +.names n705 n1178 n65 n251 n169 n290 n1383 +1100-- 1 +1-000- 1 +-1---0 1 +----00 1 +.names n273 n785 n784 n1383 n1175 n401 n1384 +111100 1 +.names n1176 n663 n1384 n1174 n137 n684 n1385 +11100- 1 +1110-0 1 +.names n500 n68 n138 n666 o_13_ n167 n1386 +1100-- 1 +110-0- 1 +1---00 1 +---0-0 1 +.names n1193 n1124 n1121 n1116 n895 n324 n1387 +100000 1 +.names n74 n175 n70 n689 n195 n390 n1388 +11--1- 0 +11---1 0 +1-11-- 0 +.names n1209 n1208 n1206 n1444 n654 n1388 o_34_ +111111 0 +.names n1222 n1221 n99 n90 n72 n61 n1390 +111000 1 +.names n87 n113 n79 n97 n77 n94 n1391 +0000-- 1 +000-0- 1 +0--0-0 1 +----00 1 +.names n121 n107 n1391 n1390 n87 n89 n1392 +11110- 1 +1111-0 1 +.names n120 n74 n1190 n69 n208 n794 n1393 +11--1- 0 +11---0 0 +1-01-- 0 +.names n1387 n1386 n1191 n1189 n500 n685 n1394 +11111- 1 +1111-0 1 +.names n1385 n1357 n1179 n1133 n1394 n1393 o_19_ +111111 0 +.names n187 n159 n93 n118 n74 n175 n1396 +100--- 0 +10--0- 0 +10---0 0 +--00-- 0 +.names n261 n159 n66 n1396 n251 n288 n1397 +11---- 0 +1----0 0 +-1--1- 0 +--11-- 0 +.names n1238 n97 n250 n66 n181 n88 n1398 +00--00 1 +0-0--- 1 +-0-0-- 1 +--00-- 1 +.names n324 n320 n319 n318 n124 n174 n1399 +00001- 1 +0000-0 1 +.names n325 n321 n1398 n314 n1399 n317 n1400 +111110 1 +.names n155 n169 n334 n159 n177 n197 n1401 +10--00 1 +1-10-- 1 +1-1--0 1 +-010-- 1 +-0-00- 1 +.names n1401 n329 n326 n177 n199 n333 n1402 +1110-- 1 +111-10 1 +.names n328 n368 n412 n97 n164 n73 n1403 +1000-- 1 +10--0- 1 +--00-0 1 +----00 1 +.names n424 n421 n138 n169 n177 n409 n1404 +0100-- 1 +01---0 1 +0-000- 1 +0---00 1 +.names n1249 n394 n396 n259 n194 n73 n1405 +1110-- 1 +111-0- 1 +11-0-0 1 +11--00 1 +.names n393 n138 n143 n392 n391 n1406 +00--- 1 +0--00 1 +-00-- 1 +.names n250 n428 n433 n168 n167 n166 n1407 +01---- 1 +100000 1 +.names n1264 n1259 n609 n183 n608 n173 n1408 +111100 1 +.names n1408 n250 n158 n1407 n164 n1409 +1000- 1 +1101- 1 +1-010 1 +.names n363 n361 i_14_ i_12_ i_13_ i_11_ n1410 +000000 1 +.names n572 i_9_ i_10_ n576 n1410 n472 n1411 +100--- 1 +111--- 1 +1---0- 1 +-111-- 1 +---10- 1 +---1-1 1 +.names n580 n92 n106 n579 i_8_ n1411 n1412 +1000-- 1 +100-0- 1 +1--0-0 1 +1---00 1 +.names n596 n486 n279 n123 n451 n212 n1413 +101--- 1 +10--00 1 +1-10-- 1 +.names n604 n159 n259 n574 n573 n333 n1414 +1000-- 1 +100-0- 1 +1--0-0 1 +1---00 1 +.names n1263 n601 n1413 n1414 n599 n1415 +11110 1 +.names n474 n255 n71 n96 n120 n292 n1416 +000-0- 1 +000--0 1 +00-0-- 1 +.names n1278 n1276 n741 n725 n734 n735 n1417 +111110 1 +.names n1273 n1417 n1416 n223 o_21_ +1110 0 +.names n319 n73 n737 n408 n194 n193 n1419 +00---- 1 +0-1000 1 +.names n767 n164 n768 n569 n303 n195 n1420 +00---- 1 +0-1000 1 +.names n769 n766 n1420 n1419 n763 n226 n1421 +111100 1 +.names n669 n152 n527 n666 n251 n208 n1422 +111000 0 +.names n803 n667 n537 n295 n1422 n110 n1423 +1000-- 1 +100-0- 1 +10-0-0 1 +10--00 1 +.names n111 n94 n110 n221 n823 n73 n1424 +00--10 1 +0-00-- 1 +0-0-1- 1 +-000-- 1 +-0-0-0 1 +.names n115 n77 n113 n100 n97 n79 n1425 +00---- 1 +0-0000 1 +.names n868 n867 n1425 n1424 n102 n90 n1426 +111100 1 +.names n131 n720 n111 n748 n149 n174 n1427 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n921 n912 n1427 n742 n77 n733 n1428 +11100- 1 +1110-1 1 +.names n631 n639 n73 n434 n910 n706 n1429 +000--- 1 +00--10 1 +--00-- 1 +.names n1428 n922 n918 n913 n911 n1429 n1430 +111111 1 +.names n1456 n1430 n684 n917 n221 n1431 +110-- 1 +11-10 1 +.names n931 n565 n909 n634 n279 n500 n1432 +1110-- 1 +11-01- 1 +1-1--1 1 +----11 1 +.names n1322 n1321 n945 n944 n1432 n1433 +11111 1 +.names n745 n120 n74 n69 n948 n949 n1434 +00---- 1 +0-00-- 1 +0---10 1 +.names n783 n947 n76 n74 n175 n98 n1435 +1----- 0 +-1---- 0 +--1111 0 +.names n950 n794 n787 n164 n165 n768 n1436 +1110-- 1 +111--1 1 +---00- 1 +.names n171 n657 n130 n1092 n365 n133 n1437 +001-0- 1 +001--0 1 +00-10- 1 +--01-0 1 +.names n1082 n1081 n174 n623 n550 n171 n1438 +100--- 1 +10-110 1 +.names n1363 n1094 n1087 n1084 n1438 n1437 n1439 +111111 1 +.names n762 n376 n77 n493 n412 n333 n1440 +010--- 1 +01--00 1 +0-01-- 1 +.names n1439 n1374 n1464 n1133 n619 n1440 o_18_ +111111 0 +.names n164 n428 n948 i_6_ i_7_ n834 n1442 +11---- 0 +1-0--- 0 +---100 0 +.names n1205 n982 n571 n574 n85 n811 n1443 +100-0- 1 +100--0 1 +10-0-- 1 +.names n1203 n1171 n838 n828 n1443 n1442 n1444 +111111 1 +.names n120 n291 n292 n106 n66 n112 n1445 +11---- 1 +1-1--- 1 +---111 1 +.names n297 n296 n293 n260 n295 n164 n1446 +0000-- 1 +000-00 1 +.names n559 n334 n268 n472 n174 n138 n1447 +0100-- 1 +010-0- 1 +0--0-0 1 +0---00 1 +.names n1403 n560 n561 n259 n1247 n248 n1448 +1110-- 1 +111-10 1 +.names n557 n1448 n1447 n148 n169 n1449 +1111- 1 +111-0 1 +.names n74 n78 n416 n420 n212 n85 n1450 +111--- 0 +11-1-- 0 +1---11 0 +.names n1450 n1406 n420 n134 n165 n143 n1451 +110--- 1 +11-000 1 +.names n1404 n419 n416 n151 o_13_ n418 n1452 +1100-- 1 +110--0 1 +11-00- 1 +.names n1405 n422 n417 n397 n1452 n1451 n1453 +111111 1 +.names n951 n718 n174 n119 n690 n662 n1454 +000--- 1 +00--00 1 +0-00-- 1 +.names n1436 n1435 n1434 n1323 n1454 n712 n1455 +111110 1 +.names n952 n1455 n684 n493 n290 n1456 +110-- 1 +11-10 1 +.names n634 n220 n303 n395 n169 n164 n1457 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n1457 n1161 n1166 n77 n98 n235 n1458 +1100-- 1 +110-0- 1 +110--0 1 +.names i_15_ i_10_ n174 i_9_ i_11_ n290 n1459 +0110-- 1 +01--01 1 +1011-- 1 +1-111- 1 +-1101- 1 +.names n1446 n1233 n287 n1445 n250 n96 n1460 +1110-- 1 +111--0 1 +11-00- 1 +11--00 1 +.names n1397 n1231 n1460 n1459 n66 n1461 +1110- 1 +111-0 1 +.names n714 n546 n634 n259 n738 n500 n1462 +11--11 1 +1-00-- 1 +1-0-1- 1 +-100-- 1 +-1-0-1 1 +.names n1458 n1379 n1377 n1271 n1159 n1164 n1463 +111110 1 +.names n1162 n1463 n1158 n1462 n259 n376 n1464 +11110- 1 +1111-1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v b/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v new file mode 100644 index 000000000..356ebcbf6 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v @@ -0,0 +1,2832 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module pdc(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_); + input i_0_; + input i_10_; + input i_11_; + input i_12_; + input i_13_; + input i_14_; + input i_15_; + input i_1_; + input i_2_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + input i_9_; + wire n100; + wire n1000; + wire n1001; + wire n1002; + wire n1003; + wire n1004; + wire n1005; + wire n1006; + wire n1007; + wire n1008; + wire n1009; + wire n101; + wire n1010; + wire n1011; + wire n1012; + wire n1013; + wire n1014; + wire n1015; + wire n1016; + wire n1017; + wire n1018; + wire n1019; + wire n102; + wire n1020; + wire n1021; + wire n1022; + wire n1023; + wire n1024; + wire n1025; + wire n1026; + wire n1027; + wire n1028; + wire n1029; + wire n103; + wire n1030; + wire n1031; + wire n1032; + wire n1033; + wire n1034; + wire n1035; + wire n1036; + wire n1037; + wire n1038; + wire n1039; + wire n104; + wire n1040; + wire n1041; + wire n1042; + wire n1043; + wire n1044; + wire n1045; + wire n1046; + wire n1047; + wire n1048; + wire n1049; + wire n105; + wire n1050; + wire n1051; + wire n1052; + wire n1053; + wire n1054; + wire n1055; + wire n1056; + wire n1057; + wire n1058; + wire n1059; + wire n106; + wire n1060; + wire n1061; + wire n1062; + wire n1063; + wire n1064; + wire n1065; + wire n1066; + wire n1067; + wire n1068; + wire n1069; + wire n107; + wire n1070; + wire n1071; + wire n1072; + wire n1073; + wire n1074; + wire n1075; + wire n1076; + wire n1077; + wire n1078; + wire n1079; + wire n108; + wire n1080; + wire n1081; + wire n1082; + wire n1083; + wire n1084; + wire n1085; + wire n1086; + wire n1087; + wire n1088; + wire n1089; + wire n109; + wire n1090; + wire n1091; + wire n1092; + wire n1093; + wire n1094; + wire n1095; + wire n1096; + wire n1097; + wire n1098; + wire n1099; + wire n110; + wire n1100; + wire n1101; + wire n1102; + wire n1103; + wire n1104; + wire n1105; + wire n1106; + wire n1107; + wire n1108; + wire n1109; + wire n111; + wire n1110; + wire n1111; + wire n1112; + wire n1113; + wire n1114; + wire n1115; + wire n1116; + wire n1117; + wire n1118; + wire n1119; + wire n112; + wire n1120; + wire n1121; + wire n1122; + wire n1123; + wire n1124; + wire n1125; + wire n1126; + wire n1127; + wire n1128; + wire n1129; + wire n113; + wire n1130; + wire n1131; + wire n1132; + wire n1133; + wire n1134; + wire n1135; + wire n1136; + wire n1137; + wire n1138; + wire n1139; + wire n114; + wire n1140; + wire n1141; + wire n1142; + wire n1143; + wire n1144; + wire n1145; + wire n1146; + wire n1147; + wire n1148; + wire n1149; + wire n115; + wire n1150; + wire n1151; + wire n1152; + wire n1153; + wire n1154; + wire n1155; + wire n1156; + wire n1157; + wire n1158; + wire n1159; + wire n116; + wire n1160; + wire n1161; + wire n1162; + wire n1163; + wire n1164; + wire n1165; + wire n1166; + wire n1167; + wire n1168; + wire n1169; + wire n117; + wire n1170; + wire n1171; + wire n1172; + wire n1173; + wire n1174; + wire n1175; + wire n1176; + wire n1177; + wire n1178; + wire n1179; + wire n118; + wire n1180; + wire n1181; + wire n1182; + wire n1183; + wire n1184; + wire n1185; + wire n1186; + wire n1187; + wire n1188; + wire n1189; + wire n119; + wire n1190; + wire n1191; + wire n1192; + wire n1193; + wire n1196; + wire n1199; + wire n120; + wire n1200; + wire n1201; + wire n1203; + wire n1204; + wire n1205; + wire n1206; + wire n1207; + wire n1208; + wire n1209; + wire n121; + wire n1211; + wire n1213; + wire n1214; + wire n1217; + wire n1218; + wire n1219; + wire n122; + wire n1220; + wire n1221; + wire n1222; + wire n1223; + wire n1224; + wire n1225; + wire n1226; + wire n1227; + wire n1228; + wire n1229; + wire n123; + wire n1230; + wire n1231; + wire n1232; + wire n1233; + wire n1234; + wire n1235; + wire n1236; + wire n1237; + wire n1238; + wire n1239; + wire n124; + wire n1240; + wire n1241; + wire n1242; + wire n1243; + wire n1244; + wire n1245; + wire n1246; + wire n1247; + wire n1248; + wire n1249; + wire n125; + wire n1250; + wire n1251; + wire n1252; + wire n1253; + wire n1254; + wire n1255; + wire n1256; + wire n1257; + wire n1258; + wire n1259; + wire n126; + wire n1261; + wire n1262; + wire n1263; + wire n1264; + wire n1265; + wire n1266; + wire n1267; + wire n1268; + wire n1269; + wire n127; + wire n1270; + wire n1271; + wire n1272; + wire n1273; + wire n1274; + wire n1275; + wire n1276; + wire n1277; + wire n1278; + wire n1279; + wire n128; + wire n1280; + wire n1281; + wire n1282; + wire n1283; + wire n1284; + wire n1285; + wire n1286; + wire n1287; + wire n1288; + wire n1289; + wire n129; + wire n1290; + wire n1291; + wire n1292; + wire n1293; + wire n1294; + wire n1295; + wire n1296; + wire n1297; + wire n1298; + wire n1299; + wire n130; + wire n1300; + wire n1301; + wire n1303; + wire n1304; + wire n1306; + wire n1307; + wire n1308; + wire n1309; + wire n131; + wire n1310; + wire n1311; + wire n1312; + wire n1313; + wire n1314; + wire n1315; + wire n1317; + wire n1318; + wire n1319; + wire n132; + wire n1320; + wire n1321; + wire n1322; + wire n1323; + wire n1324; + wire n1325; + wire n1327; + wire n1328; + wire n1329; + wire n133; + wire n1330; + wire n1331; + wire n1332; + wire n1333; + wire n1334; + wire n1335; + wire n1336; + wire n1337; + wire n1339; + wire n134; + wire n1340; + wire n1341; + wire n1342; + wire n1343; + wire n1344; + wire n1345; + wire n1346; + wire n1347; + wire n1348; + wire n1349; + wire n135; + wire n1350; + wire n1351; + wire n1352; + wire n1353; + wire n1355; + wire n1356; + wire n1357; + wire n1358; + wire n1359; + wire n136; + wire n1360; + wire n1361; + wire n1362; + wire n1363; + wire n1364; + wire n1365; + wire n1366; + wire n1367; + wire n1368; + wire n1369; + wire n137; + wire n1370; + wire n1371; + wire n1372; + wire n1373; + wire n1374; + wire n1375; + wire n1376; + wire n1377; + wire n1378; + wire n1379; + wire n138; + wire n1380; + wire n1381; + wire n1382; + wire n1383; + wire n1384; + wire n1385; + wire n1386; + wire n1387; + wire n1388; + wire n139; + wire n1390; + wire n1391; + wire n1392; + wire n1393; + wire n1394; + wire n1396; + wire n1397; + wire n1398; + wire n1399; + wire n140; + wire n1400; + wire n1401; + wire n1402; + wire n1403; + wire n1404; + wire n1405; + wire n1406; + wire n1407; + wire n1408; + wire n1409; + wire n141; + wire n1410; + wire n1411; + wire n1412; + wire n1413; + wire n1414; + wire n1415; + wire n1416; + wire n1417; + wire n1419; + wire n142; + wire n1420; + wire n1421; + wire n1422; + wire n1423; + wire n1424; + wire n1425; + wire n1426; + wire n1427; + wire n1428; + wire n1429; + wire n143; + wire n1430; + wire n1431; + wire n1432; + wire n1433; + wire n1434; + wire n1435; + wire n1436; + wire n1437; + wire n1438; + wire n1439; + wire n144; + wire n1440; + wire n1442; + wire n1443; + wire n1444; + wire n1445; + wire n1446; + wire n1447; + wire n1448; + wire n1449; + wire n1450; + wire n1451; + wire n1452; + wire n1453; + wire n1454; + wire n1455; + wire n1456; + wire n1457; + wire n1458; + wire n1459; + wire n146; + wire n1460; + wire n1461; + wire n1462; + wire n1463; + wire n1464; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n376; + wire n377; + wire n378; + wire n379; + wire n380; + wire n381; + wire n382; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n390; + wire n391; + wire n392; + wire n393; + wire n394; + wire n395; + wire n396; + wire n397; + wire n398; + wire n399; + wire n400; + wire n401; + wire n402; + wire n403; + wire n404; + wire n405; + wire n406; + wire n407; + wire n408; + wire n409; + wire n410; + wire n411; + wire n412; + wire n413; + wire n414; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n427; + wire n428; + wire n429; + wire n430; + wire n431; + wire n432; + wire n433; + wire n434; + wire n435; + wire n436; + wire n437; + wire n438; + wire n439; + wire n440; + wire n441; + wire n442; + wire n443; + wire n444; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n455; + wire n456; + wire n457; + wire n458; + wire n459; + wire n460; + wire n461; + wire n462; + wire n463; + wire n464; + wire n465; + wire n466; + wire n467; + wire n468; + wire n469; + wire n470; + wire n471; + wire n472; + wire n473; + wire n474; + wire n475; + wire n476; + wire n477; + wire n478; + wire n479; + wire n480; + wire n481; + wire n482; + wire n483; + wire n484; + wire n485; + wire n486; + wire n487; + wire n488; + wire n489; + wire n490; + wire n491; + wire n492; + wire n493; + wire n494; + wire n495; + wire n496; + wire n497; + wire n498; + wire n499; + wire n500; + wire n501; + wire n502; + wire n503; + wire n504; + wire n505; + wire n506; + wire n507; + wire n508; + wire n509; + wire n510; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n530; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n540; + wire n541; + wire n542; + wire n543; + wire n544; + wire n545; + wire n546; + wire n547; + wire n548; + wire n549; + wire n550; + wire n551; + wire n552; + wire n553; + wire n554; + wire n555; + wire n556; + wire n557; + wire n558; + wire n559; + wire n560; + wire n561; + wire n563; + wire n564; + wire n565; + wire n566; + wire n567; + wire n568; + wire n569; + wire n570; + wire n571; + wire n572; + wire n573; + wire n574; + wire n575; + wire n576; + wire n577; + wire n578; + wire n579; + wire n580; + wire n581; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n587; + wire n588; + wire n589; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n598; + wire n599; + wire n600; + wire n601; + wire n602; + wire n603; + wire n604; + wire n605; + wire n606; + wire n607; + wire n608; + wire n609; + wire n61; + wire n610; + wire n611; + wire n612; + wire n613; + wire n614; + wire n615; + wire n616; + wire n617; + wire n619; + wire n62; + wire n620; + wire n621; + wire n622; + wire n623; + wire n624; + wire n625; + wire n626; + wire n627; + wire n628; + wire n629; + wire n63; + wire n630; + wire n631; + wire n632; + wire n633; + wire n634; + wire n635; + wire n636; + wire n637; + wire n638; + wire n639; + wire n64; + wire n640; + wire n641; + wire n642; + wire n643; + wire n644; + wire n645; + wire n646; + wire n647; + wire n648; + wire n649; + wire n65; + wire n650; + wire n651; + wire n652; + wire n653; + wire n654; + wire n655; + wire n656; + wire n657; + wire n658; + wire n659; + wire n66; + wire n660; + wire n661; + wire n662; + wire n663; + wire n664; + wire n665; + wire n666; + wire n667; + wire n668; + wire n669; + wire n67; + wire n670; + wire n671; + wire n672; + wire n673; + wire n674; + wire n675; + wire n676; + wire n677; + wire n678; + wire n679; + wire n68; + wire n680; + wire n681; + wire n682; + wire n683; + wire n684; + wire n685; + wire n686; + wire n687; + wire n688; + wire n689; + wire n69; + wire n690; + wire n691; + wire n692; + wire n693; + wire n694; + wire n695; + wire n696; + wire n697; + wire n698; + wire n699; + wire n70; + wire n701; + wire n702; + wire n703; + wire n704; + wire n705; + wire n706; + wire n707; + wire n708; + wire n709; + wire n71; + wire n710; + wire n712; + wire n713; + wire n714; + wire n715; + wire n716; + wire n717; + wire n718; + wire n719; + wire n72; + wire n720; + wire n721; + wire n722; + wire n723; + wire n724; + wire n725; + wire n726; + wire n727; + wire n728; + wire n729; + wire n73; + wire n730; + wire n731; + wire n732; + wire n733; + wire n734; + wire n735; + wire n736; + wire n737; + wire n738; + wire n739; + wire n74; + wire n740; + wire n741; + wire n742; + wire n743; + wire n744; + wire n745; + wire n746; + wire n747; + wire n748; + wire n749; + wire n75; + wire n750; + wire n752; + wire n753; + wire n754; + wire n755; + wire n756; + wire n757; + wire n758; + wire n759; + wire n76; + wire n760; + wire n761; + wire n762; + wire n763; + wire n764; + wire n765; + wire n766; + wire n767; + wire n768; + wire n769; + wire n77; + wire n770; + wire n771; + wire n772; + wire n773; + wire n774; + wire n775; + wire n776; + wire n777; + wire n778; + wire n779; + wire n78; + wire n780; + wire n781; + wire n782; + wire n783; + wire n784; + wire n785; + wire n786; + wire n787; + wire n788; + wire n789; + wire n79; + wire n790; + wire n791; + wire n792; + wire n793; + wire n794; + wire n795; + wire n796; + wire n797; + wire n798; + wire n799; + wire n80; + wire n800; + wire n801; + wire n802; + wire n803; + wire n804; + wire n805; + wire n806; + wire n807; + wire n808; + wire n809; + wire n81; + wire n810; + wire n811; + wire n812; + wire n814; + wire n816; + wire n817; + wire n818; + wire n819; + wire n82; + wire n820; + wire n821; + wire n822; + wire n823; + wire n824; + wire n825; + wire n827; + wire n828; + wire n829; + wire n83; + wire n830; + wire n831; + wire n832; + wire n833; + wire n834; + wire n835; + wire n836; + wire n837; + wire n838; + wire n839; + wire n84; + wire n840; + wire n843; + wire n844; + wire n846; + wire n847; + wire n848; + wire n849; + wire n85; + wire n851; + wire n852; + wire n854; + wire n856; + wire n858; + wire n859; + wire n86; + wire n860; + wire n861; + wire n862; + wire n863; + wire n864; + wire n865; + wire n866; + wire n867; + wire n868; + wire n869; + wire n87; + wire n870; + wire n871; + wire n872; + wire n873; + wire n874; + wire n875; + wire n876; + wire n877; + wire n878; + wire n879; + wire n88; + wire n880; + wire n881; + wire n882; + wire n883; + wire n884; + wire n885; + wire n886; + wire n887; + wire n888; + wire n889; + wire n89; + wire n890; + wire n891; + wire n892; + wire n893; + wire n894; + wire n895; + wire n896; + wire n897; + wire n898; + wire n899; + wire n90; + wire n900; + wire n901; + wire n902; + wire n903; + wire n904; + wire n905; + wire n906; + wire n907; + wire n908; + wire n909; + wire n91; + wire n910; + wire n911; + wire n912; + wire n913; + wire n914; + wire n915; + wire n916; + wire n917; + wire n918; + wire n919; + wire n92; + wire n920; + wire n921; + wire n922; + wire n923; + wire n924; + wire n925; + wire n926; + wire n927; + wire n928; + wire n929; + wire n93; + wire n930; + wire n931; + wire n932; + wire n933; + wire n934; + wire n935; + wire n936; + wire n937; + wire n938; + wire n939; + wire n94; + wire n940; + wire n941; + wire n942; + wire n943; + wire n944; + wire n945; + wire n946; + wire n947; + wire n948; + wire n949; + wire n95; + wire n950; + wire n951; + wire n952; + wire n953; + wire n954; + wire n955; + wire n956; + wire n957; + wire n959; + wire n96; + wire n960; + wire n961; + wire n962; + wire n963; + wire n964; + wire n965; + wire n966; + wire n967; + wire n968; + wire n969; + wire n97; + wire n970; + wire n971; + wire n972; + wire n973; + wire n974; + wire n975; + wire n976; + wire n977; + wire n978; + wire n979; + wire n98; + wire n980; + wire n981; + wire n982; + wire n983; + wire n984; + wire n985; + wire n986; + wire n987; + wire n988; + wire n989; + wire n99; + wire n990; + wire n991; + wire n992; + wire n993; + wire n994; + wire n995; + wire n996; + wire n997; + wire n998; + wire n999; + output o_0_; + output o_10_; + output o_11_; + output o_12_; + output o_13_; + output o_14_; + output o_15_; + output o_16_; + output o_17_; + output o_18_; + output o_19_; + output o_1_; + output o_20_; + output o_21_; + output o_22_; + output o_23_; + output o_24_; + output o_25_; + output o_26_; + output o_27_; + output o_28_; + output o_29_; + output o_2_; + output o_30_; + output o_31_; + output o_32_; + output o_33_; + output o_34_; + output o_35_; + output o_36_; + output o_37_; + output o_38_; + output o_39_; + output o_3_; + output o_4_; + output o_5_; + output o_6_; + output o_7_; + output o_8_; + output o_9_; + assign o_6_ = 8'h02 >> { i_1_, i_0_, i_3_ }; + assign n68 = 8'h57 >> { n70, n71, n69 }; + assign n158 = 8'ha8 >> { n162, n160, n159 }; + assign n1058 = 16'h0002 >> { n141, n194, n180, n1052 }; + assign n1059 = 64'h0808000800080008 >> { n334, n672, n174, n798, n941, n1060 }; + assign n1060 = 64'h153f153f1515153f >> { i_8_, n677, n81, n371, n174, n227 }; + assign n1061 = 16'h22a2 >> { n672, n177, n1062, n259 }; + assign n1062 = 64'hd7d7d5dff7f7d7ff >> { i_15_, i_14_, n134, i_13_, i_12_, n233 }; + assign n1063 = 16'h0080 >> { n451, n721, n724, n1017 }; + assign n1064 = 64'h0000000000008000 >> { n655, n1075, n1070, n1073, n1065, n1068 }; + assign n1065 = 64'h0008000800080808 >> { n232, n456, n94, n742, n1066, n1067 }; + assign n1066 = 16'hd555 >> { n653, n334, n387, n94 }; + assign n1067 = 64'h0040004450505555 >> { n674, n250, n290, n733, n956, n957 }; + assign n159 = 4'h8 >> { n96, n106 }; + assign n1068 = 64'h2020002022220022 >> { n77, n493, n677, n733, n728, n1069 }; + assign n1069 = 64'h0000077707770777 >> { n371, n133, n630, n174, o_13_, n81 }; + assign n1070 = 64'h0080008880808888 >> { n232, n434, n250, n1017, n1072, n1071 }; + assign n1071 = 16'h7707 >> { n653, n169, n94, n162 }; + assign n1072 = 64'h0000153715371537 >> { n371, n250, n212, n94, n246, n159 }; + assign n1073 = 32'd572662314 >> { n371, n176, n451, n159, n1074 }; + assign n1074 = 32'd2003850576 >> { n942, n68, n678, n111, n538 }; + assign n1075 = 32'd2863311402 >> { n456, n371, n334, n672, n77 }; + assign n1076 = 64'h0044055504440555 >> { n161, n94, n149, n748, n749, n747 }; + assign n1077 = 64'h8a8a8a0a8a0a8a0a >> { n773, n964, i_8_, n130, n148, n1078 }; + assign n160 = 4'h8 >> { n80, n161 }; + assign n1078 = 32'd2902303989 >> { n773, n130, n379, n191, n174 }; + assign n1079 = 16'hdff7 >> { i_15_, i_12_, i_14_, n149 }; + assign n1080 = 64'h4000404055005555 >> { n89, n73, n764, n773, n148, n516 }; + assign n1081 = 64'h0008880880888888 >> { i_13_, i_14_, i_15_, i_12_, n147, n434 }; + assign n1082 = 32'd1431655773 >> { n365, n225, n110, n1083, n164 }; + assign n1083 = 32'd3715456887 >> { i_15_, i_12_, i_13_, i_14_, n147 }; + assign n1084 = 32'd33554946 >> { n94, n739, n727, n223, n1085 }; + assign n1085 = 32'd572695074 >> { n365, n146, n623, n89, n1086 }; + assign n1086 = 64'hf7f77f7777ff7f7f >> { i_15_, i_12_, i_13_, i_14_, n147, n250 }; + assign n1087 = 32'd134742024 >> { n623, n133, n1039, n1088, n1091 }; + assign n161 = 8'h02 >> { i_12_, i_14_, i_13_ }; + assign n1088 = 32'd2763306 >> { n269, n274, n110, n119, n1089 }; + assign n1089 = 64'h4c5d4c5d00004c5d >> { n693, n169, n89, n631, n1090, n250 }; + assign n1090 = 16'h0777 >> { n84, n161, n66, n93 }; + assign n1091 = 32'd1162149957 >> { n624, n89, n73, n737, n767 }; + assign n1092 = 64'h0008080800aaaaaa >> { n94, n119, n365, n690, n1038, n1093 }; + assign n1093 = 64'h00020003aaaaffff >> { n538, n133, n135, n723, n716, n624 }; + assign n1094 = 64'h0000000000008000 >> { n778, n1102, n1098, n1100, n820, n1095 }; + assign n1095 = 64'h0000008000800080 >> { n123, n220, n318, n868, n1096, n1097 }; + assign n1096 = 32'd3623346175 >> { n77, n159, i_14_, i_12_, n84 }; + assign n1097 = 8'h15 >> { n395, n259, n698 }; + assign n162 = 4'h8 >> { n82, n161 }; + assign n1098 = 32'd4539717 >> { n225, n250, n690, n595, n1099 }; + assign n1099 = 8'ha8 >> { n79, n110, n222 }; + assign n1100 = 32'd2763306 >> { n365, n169, n94, n420, n1101 }; + assign n1101 = 32'd2004289399 >> { i_8_, n364, o_13_, n169, n220 }; + assign n1102 = 64'h0808808808008080 >> { i_13_, i_15_, i_14_, i_12_, n77, n147 }; + assign n1103 = 64'h0008000808080008 >> { n138, n68, n631, n998, n1104, n253 }; + assign n1104 = 64'h0111055503130757 >> { n89, n79, n391, n77, n250, n87 }; + assign n1105 = 32'd526344 >> { n443, n250, n1106, n1108, n1107 }; + assign n1106 = 8'ha8 >> { n674, n162, n73 }; + assign n1107 = 64'h5173517351735577 >> { n435, n361, o_12_, i_8_, o_13_, n218 }; + assign n163 = 64'h000101010055ffff >> { n165, n164, n160, n166, n168, n167 }; + assign n1108 = 64'h0004000544445555 >> { n79, n250, n94, n434, n328, n1109 }; + assign n1109 = 32'd32768 >> { i_8_, n69, n78, n76, n114 }; + assign n1110 = 64'h00022222000fffff >> { n250, n169, n87, n110, n166, n277 }; + assign n1111 = 64'h0001010100555555 >> { n166, n222, n81, o_12_, n123, n774 }; + assign n1112 = 64'h0000077707770777 >> { n123, n365, n79, n164, n94, n409 }; + assign n1113 = 32'd16842753 >> { n749, n169, n1116, n1114, n946 }; + assign n1114 = 64'haaaaaaaaaaaaaa2a >> { n361, n113, n435, n1115, n876, n89 }; + assign n1115 = 8'h08 >> { n456, n653, n724 }; + assign n1116 = 16'haa2a >> { n371, n334, n672, n89 }; + assign n1117 = 32'd356455701 >> { n206, n391, n77, n393, n89 }; + assign n164 = 4'h8 >> { n74, n120 }; + assign n1118 = 64'h01010001ffff00ff >> { n77, n380, n720, n197, n166, n443 }; + assign n1119 = 16'h5554 >> { n647, n349, n195, n68 }; + assign n1120 = 16'h5557 >> { n627, n218, n720, n164 }; + assign n1121 = 4'h2 >> { n653, n174 }; + assign n1122 = 64'h0808008888088080 >> { i_15_, i_12_, i_13_, i_14_, n207, n174 }; + assign n1123 = 16'hdd0d >> { n737, n164, n649, n174 }; + assign n1124 = 8'h8a >> { n724, n456, n174 }; + assign n1125 = 16'haaa8 >> { n361, n393, n443, n123 }; + assign n1126 = 64'h0000000080000000 >> { n1132, n922, n1335, n1127, n1129, n987 }; + assign n1127 = 64'h22222222a2222222 >> { n110, n733, n1128, n623, n133, n734 }; + assign n165 = 4'h8 >> { n69, n120 }; + assign n1128 = 64'h0000000000000002 >> { n268, n456, n395, n420, n371, n686 }; + assign n1129 = 64'h1111001101010001 >> { n906, n1131, n133, n259, n966, n1130 }; + assign n1130 = 32'd2863311402 >> { n349, n435, n594, n686, n434 }; + assign n1131 = 64'h4105514155555555 >> { n207, i_15_, i_13_, i_12_, i_14_, n740 }; + assign n1132 = 64'h0888880880808800 >> { i_15_, i_12_, i_14_, i_13_, n149, n77 }; + assign n1133 = 64'h0000000080000000 >> { n1132, n1134, n1376, n1139, n1154, n1276 }; + assign n1134 = 64'h0202000200020002 >> { n1136, n626, n164, n771, n772, n1135 }; + assign n1135 = 32'd65793 >> { n79, n164, n770, n347, n102 }; + assign n1136 = 16'h0001 >> { n340, n379, n628, n639 }; + assign n1137 = 8'h01 >> { n757, n636, n504 }; + assign n166 = 4'h8 >> { n88, n161 }; + assign n1138 = 16'h22a2 >> { n650, n155, n174, n284 }; + assign n1139 = 64'h0080000000800080 >> { n89, n1153, n1146, n1147, n1140, n1142 }; + assign n1140 = 64'h0002020200222222 >> { n227, n164, n644, n1141, n228, n799 }; + assign n1141 = 64'h08aa002800aa0028 >> { i_8_, i_12_, i_14_, i_13_, i_15_, n103 }; + assign n1142 = 64'h0000008000800080 >> { n627, n164, n1143, n1145, n190, n1144 }; + assign n1143 = 4'h8 >> { n169, n100 }; + assign n1144 = 64'h80008080aa00aaaa >> { o_12_, o_13_, n948, n626, n155, n1046 }; + assign n1145 = 64'h04440ccc05550ddd >> { n123, n160, n174, n628, n693, n164 }; + assign n1146 = 64'haaaaaaaaaaaaaaa2 >> { n627, n628, n403, n379, n1004, n169 }; + assign n1147 = 64'h04aa040c0caa0c0c >> { n631, n169, n77, n1151, n1148, n1152 }; + assign n167 = 4'h8 >> { n67, n161 }; + assign n1148 = 32'd1435850197 >> { n1150, n100, n1024, n1149, n250 }; + assign n1149 = 16'hffd7 >> { i_14_, i_13_, i_12_, n118 }; + assign n1150 = 32'd32768 >> { i_8_, n96, n76, n101, n95 }; + assign n1151 = 4'h8 >> { o_13_, n103 }; + assign n1152 = 64'h9bdf95d79bff95ff >> { n103, i_12_, n149, i_13_, i_15_, i_14_ }; + assign n1153 = 4'h2 >> { n103, n693 }; + assign n1154 = 64'h2233a2b32033a0b3 >> { i_9_, n379, n259, n1157, n434, n1155 }; + assign n1155 = 64'h2222002202020002 >> { n923, n1156, i_8_, n134, n192, n1079 }; + assign n1156 = 64'h1188db8835beffff >> { n149, n103, i_14_, i_13_, i_15_, i_12_ }; + assign n1157 = 4'h1 >> { n103, n79 }; + assign n69 = 64'h0000000000000002 >> { i_1_, i_0_, i_2_, i_5_, i_3_, i_4_ }; + assign n168 = 4'h8 >> { n101, n161 }; + assign n1158 = 64'h0777077707770fff >> { n153, n235, n690, n434, n133, n98 }; + assign n1159 = 32'd286331217 >> { n89, n274, n238, n706, n1160 }; + assign n1160 = 64'h0880880080808080 >> { i_12_, i_13_, i_15_, i_14_, n169, n291 }; + assign n1161 = 16'h0777 >> { n267, n144, o_13_, n141 }; + assign n1162 = 64'h8888008808080008 >> { n719, n501, n657, n538, n1163, n766 }; + assign n1163 = 32'd1426447629 >> { n363, n205, n250, n719, n89 }; + assign n1164 = 16'haaa2 >> { n62, n151, n501, n170 }; + assign n1165 = 16'h0ddd >> { n441, n434, n736, n174 }; + assign n1166 = 16'h8880 >> { n100, n97, n69, n175 }; + assign n1167 = 64'h0ddd0ddd00000ddd >> { n950, n250, n73, n689, n737, n164 }; + assign n169 = 4'h8 >> { n69, n106 }; + assign n1168 = 64'h0101010101010111 >> { n457, n268, n420, n133, n555, n553 }; + assign n1169 = 64'h0880808888088080 >> { i_15_, i_13_, i_14_, i_12_, n291, n62 }; + assign n1170 = 64'h0004000544445555 >> { n94, n151, n333, n441, n376, n731 }; + assign n1171 = 64'h0202020202022202 >> { n141, n333, n480, n164, n1172, n1173 }; + assign n1172 = 64'h0888800888088080 >> { i_15_, i_12_, i_13_, i_14_, n291, n73 }; + assign n1173 = 32'd7697781 >> { n73, n368, n950, n97, n164 }; + assign n1174 = 4'h2 >> { n708, n62 }; + assign n1175 = 8'h8a >> { n199, n208, o_12_ }; + assign n1176 = 16'h5515 >> { n238, n67, n142, n1177 }; + assign n1177 = 64'h0880808808080880 >> { i_15_, i_13_, i_14_, i_12_, n577, o_13_ }; + assign n170 = 4'h8 >> { n98, n161 }; + assign n1178 = 64'h84a581b5ceffc9ff >> { n577, i_13_, n233, i_12_, i_14_, i_15_ }; + assign n1179 = 64'h8000000080008000 >> { n684, n917, n1280, n1187, n1180, n1184 }; + assign n1180 = 64'h00800088a0a0aaaa >> { n685, n89, n123, n1183, n279, n1181 }; + assign n1181 = 16'ha222 >> { n152, n527, n134, n1182 }; + assign n1182 = 64'hf77f7f77f7f7f77f >> { i_15_, i_13_, i_14_, i_12_, n577, n177 }; + assign n1183 = 64'h8e378e778f3fffff >> { n577, n233, i_15_, i_14_, i_13_, i_12_ }; + assign n1184 = 32'd572662314 >> { n418, n65, n204, n134, n1185 }; + assign n1185 = 32'd33686050 >> { n94, n134, n208, n1186, n625 }; + assign n1186 = 16'haaa8 >> { n627, n630, n160, n165 }; + assign n1187 = 64'h0008080808080808 >> { n71, n74, n198, n698, n1188, n916 }; + assign n171 = 4'h8 >> { n84, n161 }; + assign n1188 = 64'h0001010100555555 >> { n267, n79, n165, n144, n305, n915 }; + assign n1189 = 32'd1158008205 >> { n65, n708, n73, n797, n164 }; + assign n1190 = 32'd1685483007 >> { n125, n67, i_13_, i_12_, i_14_ }; + assign n1191 = 16'h2202 >> { n931, n138, n1192, n687 }; + assign n1192 = 64'heeecaaa8aaa8aaa8 >> { n67, n142, n259, n151, n143, n251 }; + assign n1193 = 32'd707406399 >> { n949, n169, n123, n677, n693 }; + assign o_20_ = 8'hfe >> { o_21_, o_11_, n259 }; + assign o_22_ = 16'hfff7 >> { n1099, n915, n1196, n694 }; + assign n1196 = 16'h1115 >> { n87, n81, n222, n294 }; + assign o_27_ = 32'd32768 >> { i_2_, n116, i_1_, i_0_, n1262 }; + assign n172 = 64'h0004000544445555 >> { n180, n177, n179, n119, n182, n173 }; + assign o_29_ = 32'd2004318199 >> { n578, i_10_, i_9_, n1199, n837 }; + assign n1199 = 32'd526344 >> { n573, n361, n1201, n835, n1200 }; + assign n1200 = 64'h15153f153f153f15 >> { n598, i_5_, n834, n573, n197, n116 }; + assign n1201 = 32'd2290125040 >> { n834, i_6_, i_7_, n805, i_5_ }; + assign o_31_ = 32'd117381119 >> { n809, n835, n578, i_10_, i_9_ }; + assign n1203 = 32'd33685506 >> { n327, n174, n1204, n986, n1200 }; + assign n1204 = 8'ha2 >> { n573, n831, n141 }; + assign n1205 = 64'h0777077707770fff >> { n98, n67, n1141, n227, n142, n73 }; + assign n1206 = 32'd134776840 >> { n208, n794, n164, n1207, n1376 }; + assign n1207 = 32'd1158008205 >> { n65, n708, n73, n797, n164 }; + assign n173 = 16'heee0 >> { n176, n171, n174, n159 }; + assign n1208 = 32'd2147483648 >> { n688, n807, n1059, n1077, n1082 }; + assign n1209 = 4'h8 >> { n1288, n1372 }; + assign o_35_ = 8'h5d >> { n808, n365, n1211 }; + assign n1211 = 32'd251731729 >> { n574, n839, n573, n195, n368 }; + assign o_37_ = 64'h2aaaaaaaaaaaaaaa >> { n1213, n834, n1214, n851, n852, n1262 }; + assign n1213 = 16'h1151 >> { n574, n814, n810, n836 }; + assign n1214 = 64'hffd7fff7ffdfffff >> { n71, n63, i_4_, i_5_, i_3_, n568 }; + assign o_38_ = 4'h8 >> { n805, n78 }; + assign o_39_ = 4'h8 >> { n805, n178 }; + assign n1217 = 64'ha8a8a8a8a8a8ffa8 >> { n148, i_8_, n116, n194, n193, n70 }; + assign n174 = 4'h8 >> { n74, n175 }; + assign n1218 = 64'h0008080800888888 >> { n1217, n164, n195, n74, n190, n196 }; + assign n1219 = 64'h0000000080000000 >> { n202, n1392, n139, n150, n156, n1218 }; + assign n1220 = 64'hff80808080808080 >> { n66, n84, n85, n63, n76, n83 }; + assign n1221 = 64'h0002020200aaaaaa >> { n77, n1220, n64, n79, n81, n86 }; + assign n1222 = 64'h77777fff7fff7fff >> { n76, n93, n66, n84, n85, n74 }; + assign n1223 = 64'h0000008000800080 >> { n250, n79, n234, n236, n266, n270 }; + assign n1224 = 64'h00200022a0a0a2a2 >> { n164, n218, n251, n238, n113, n230 }; + assign n1225 = 64'h8000000000000000 >> { n1223, n1224, n1228, n239, n252, n272 }; + assign n1226 = 64'h88888888f8888888 >> { i_8_, n78, n112, n69, n84, n222 }; + assign n1227 = 64'h0001010100111111 >> { n94, n220, n221, n218, n219, n223 }; + assign n175 = 8'h80 >> { i_6_, i_7_, i_8_ }; + assign n1228 = 64'h0008080800888888 >> { n1226, n65, n130, n66, n1227, n224 }; + assign n1229 = 32'd19922943 >> { i_14_, n112, n216, i_13_, i_12_ }; + assign n1230 = 32'd2863278762 >> { n113, n1229, n276, n277, o_12_ }; + assign n1231 = 64'h7f7f7f7f7f7f7fff >> { n125, n114, n83, n106, n69, n66 }; + assign n1232 = 64'heaaac080c080c080 >> { n96, n106, n112, n92, n64, n91 }; + assign n1233 = 64'h0015151515151515 >> { n130, n261, i_8_, n1232, n66, n294 }; + assign n1234 = 32'd1465319511 >> { n304, n164, n303, n225, n133 }; + assign n1235 = 64'h00040c0c00555d5d >> { n159, n305, n174, n248, n244, n164 }; + assign n1236 = 32'd1431655773 >> { n225, n232, n204, n277, n250 }; + assign n1237 = 16'h8000 >> { n1234, n1235, n1236, n298 }; + assign n176 = 4'h8 >> { n153, n82 }; + assign n1238 = 64'hff80808080808080 >> { n84, n74, n120, n69, n82, n106 }; + assign n1239 = 64'ha0b000b0a2b300b3 >> { n165, n146, n174, n328, n164, n327 }; + assign n1240 = 32'd2290616456 >> { n148, n130, i_8_, n1239, n1402 }; + assign n1241 = 64'h0000000080000000 >> { n344, n346, n348, n355, n357, n358 }; + assign n1242 = 64'h0008000800080808 >> { n159, n138, n342, n341, n1241, n350 }; + assign n1243 = 64'h0808080808080888 >> { n343, n345, n349, n73, n335, n1242 }; + assign n1244 = 64'h0105010501051115 >> { n368, n371, n134, n123, n379, n369 }; + assign n1245 = 64'hdd0ddd0d0000dd0d >> { n380, n370, n377, n143, n389, n138 }; + assign n1246 = 64'h0000000080000000 >> { n359, n1245, n1244, n366, n372, n381 }; + assign n1247 = 64'h0001000100010101 >> { n118, n125, n76, n261, n289, n390 }; + assign n177 = 8'h80 >> { n64, n178, i_8_ }; + assign n1248 = 64'h0000000080000000 >> { n545, n1453, n425, n465, n1449, n548 }; + assign n1249 = 32'd17895263 >> { n176, n62, n391, n137, n89 }; + assign n1250 = 64'h5502020200020202 >> { n74, n98, n200, n435, n443, n94 }; + assign n1251 = 64'h0ddd0ddd00000ddd >> { n438, n434, n250, n442, n436, n77 }; + assign n1252 = 64'h0080000800880008 >> { n63, n1250, n437, n94, n1251, n439 }; + assign n1253 = 64'ha888a888a888a000 >> { n112, n93, n362, n67, n161, n78 }; + assign n1254 = 64'h0051515151515151 >> { n69, n1253, i_8_, n467, n374, n468 }; + assign n1255 = 64'h0000000080000000 >> { n466, n1254, n469, n471, n473, n476 }; + assign n1256 = 64'haaab222322232223 >> { n518, n531, n62, n174, n123, n527 }; + assign n1257 = 64'h1010001011110011 >> { n161, n380, n391, n519, n517, n528 }; + assign n70 = 8'h02 >> { i_6_, i_8_, i_7_ }; + assign n178 = 4'h2 >> { i_7_, i_6_ }; + assign n1258 = 64'h0000000080000000 >> { n516, n1257, n1256, n520, n522, n529 }; + assign n1259 = 64'h373f373f1515373f >> { n189, n74, n64, n119, n180, n175 }; + assign o_8_ = 64'h2aaaaaaaaaaaaaaa >> { n465, n1409, n581, n1267, n611, n1262 }; + assign n1261 = 64'h5444f6667666f666 >> { i_11_, n62, n567, n578, i_10_, i_9_ }; + assign n1262 = 64'h0800080008080800 >> { n569, n563, n567, n570, n1261, n1412 }; + assign n1263 = 64'h0333077701110555 >> { n595, n428, n457, n133, n174, n456 }; + assign n1264 = 64'h0001010100ff55ff >> { n169, n160, n164, n170, n171, n167 }; + assign n1265 = 64'h08080008aaaa00aa >> { n420, n331, n392, n133, n242, n610 }; + assign n1266 = 32'd572662434 >> { n164, n259, n380, n393, n1265 }; + assign n1267 = 64'h0808088800080088 >> { n210, n164, n434, n408, n1266, n1453 }; + assign n179 = 4'h8 >> { n64, n175 }; + assign n1268 = 64'hdd5fff7fdddfffff >> { n174, n123, i_12_, i_13_, i_14_, n216 }; + assign n1269 = 64'h0000000000000080 >> { n317, n655, n662, n656, n658, n1268 }; + assign n1270 = 64'h0001010100ff11ff >> { n123, n170, n174, n690, n689, n289 }; + assign n1271 = 16'h0222 >> { n691, n130, n526, n1270 }; + assign n1272 = 64'h8000000000000000 >> { n702, n713, n714, n719, n732, n750 }; + assign n1273 = 64'h8080008000800080 >> { n330, n1272, n159, n730, n1280, n746 }; + assign n1274 = 64'h3b6fdf7b93a313b3 >> { i_8_, i_15_, i_13_, i_14_, i_9_, i_12_ }; + assign n1275 = 64'h5557575757575757 >> { i_11_, n1274, i_10_, n650, n131, n151 }; + assign n1276 = 16'h0222 >> { n409, n138, n712, n1275 }; + assign n1277 = 32'd8 >> { n81, n180, n248, n721, n733 }; + assign n180 = 4'h8 >> { n181, n161 }; + assign n1278 = 64'h0101000155ff00ff >> { n94, n1277, n159, n246, n569, n162 }; + assign n1279 = 64'h000200ff020202ff >> { n208, n138, n159, n204, n65, n527 }; + assign n1280 = 32'd33694210 >> { n418, n152, n151, n745, n1279 }; + assign n1281 = 64'h0000000000000008 >> { n131, n144, n198, n428, n283, n653 }; + assign n1282 = 64'h0202000200020002 >> { n1281, n646, n295, n643, n285, n753 }; + assign n1283 = 64'h0000800080008000 >> { n652, n130, n1282, n754, n755, n1286 }; + assign n1284 = 64'h02ff02ff00ff02ff >> { n506, i_8_, n130, n345, n637, n503 }; + assign n1285 = 64'h0202020202022202 >> { n379, n435, n758, n295, n757, n641 }; + assign n1286 = 64'h0000000000000080 >> { n446, n504, n505, n1285, n1284, n756 }; + assign n1287 = 64'h0010001110105555 >> { n73, n164, n614, n765, n627, n762 }; + assign n181 = 16'h0002 >> { i_10_, i_9_, i_11_, i_15_ }; + assign n1288 = 64'h0000000080000000 >> { n760, n759, n1287, n1421, n1290, n777 }; + assign n1289 = 64'h0101010123010101 >> { n379, n626, n776, n347, n775, n164 }; + assign n1290 = 64'h0000000000000002 >> { n102, n770, n771, n772, n774, n1289 }; + assign n1291 = 64'h0000800080008000 >> { n295, n204, n790, n791, n793, n795 }; + assign n1292 = 64'h55555555555555d5 >> { n333, n442, n220, n787, n792, n537 }; + assign n1293 = 16'h8808 >> { n669, n123, n1292, n1291 }; + assign n1294 = 64'hffff377737773777 >> { n103, n800, i_13_, i_8_, n797, n709 }; + assign n1295 = 64'h0000008000800080 >> { n227, n1294, n798, n799, n801, n1269 }; + assign n1296 = 64'hffffffffffffff7f >> { n237, n364, n716, n146, n737, n802 }; + assign n1297 = 64'h0002020200222222 >> { n73, n1296, n537, n689, n664, n1423 }; + assign n182 = 16'h1357 >> { n153, n84, n82, n161 }; + assign n1298 = 64'h2200220222022202 >> { n362, n114, i_8_, n685, n684, n707 }; + assign n1299 = 64'h0002000202020002 >> { n816, n1298, n130, n676, n673, n819 }; + assign n1300 = 64'h8000800000008000 >> { n686, n123, n620, n1299, n688, n817 }; + assign n1301 = 64'h1111111111111151 >> { n251, n65, n674, n705, n290, n401 }; + assign o_26_ = 64'hffffff7fff7fff7f >> { n684, n221, n825, n820, n824, n1301 }; + assign n1303 = 64'h0080808080808080 >> { n598, n116, i_5_, n591, n827, n834 }; + assign n1304 = 64'h2626262626262604 >> { n368, n361, n197, n576, i_7_, n572 }; + assign o_30_ = 32'd2146926455 >> { n71, i_7_, n1304, n1303, n837 }; + assign n1306 = 64'h030f135f03071357 >> { i_8_, n441, n440, n174, n130, n430 }; + assign n1307 = 64'h000fffff00011111 >> { n68, n261, n73, n434, n218, n220 }; + assign n183 = 4'h1 >> { n184, n185 }; + assign n1308 = 64'h0000800080008000 >> { n315, n164, n1306, n1307, n859, n860 }; + assign n1309 = 64'h0001010100555555 >> { n434, n117, n119, n110, n79, n636 }; + assign n1310 = 64'h0008008808080888 >> { n123, n65, n81, n94, n1426, n1309 }; + assign n1311 = 64'h0008080800ffaaff >> { n268, n119, n154, n250, n242, n279 }; + assign n1312 = 64'h0008000a8888ffff >> { n144, n141, n134, n159, n500, n279 }; + assign n1313 = 64'h0000000080000000 >> { n890, n1312, n1315, n887, n1311, n891 }; + assign n1314 = 64'h0008000800080808 >> { n133, n123, n144, n635, n885, n886 }; + assign n1315 = 64'h0000000000008000 >> { n351, n353, n1314, n878, n882, n883 }; + assign o_4_ = 64'h7fffffffffffffff >> { n1431, n899, n900, n907, n927, n1267 }; + assign n1317 = 64'h0001010100555555 >> { i_8_, n201, n216, n81, n97, n718 }; + assign n184 = 64'h0080008000000080 >> { i_12_, i_13_, i_14_, n64, n175, n181 }; + assign n1318 = 64'h004000c85050fafa >> { n227, n553, n689, n941, n1317, i_8_ }; + assign n1319 = 64'h0008008808080888 >> { n409, n159, n165, n717, n642, n1318 }; + assign n1320 = 32'd1162167759 >> { n639, n637, n137, n942, n177 }; + assign n1321 = 64'h222222222222222a >> { n634, n637, n666, n717, n73, n1320 }; + assign n1322 = 64'h0002002202020222 >> { n723, n227, n159, n716, n946, n943 }; + assign n1323 = 64'h22220002aaaf000f >> { n177, n733, n159, n164, n718, n925 }; + assign n1324 = 64'h0040004450505454 >> { n723, n123, n134, n965, n279, n976 }; + assign n1325 = 64'h8000000000000000 >> { n961, n963, n1329, n967, n974, n1237 }; + assign o_9_ = 64'h7fffffffffffffff >> { n1324, n960, n1325, n977, n991, n1313 }; + assign n1327 = 64'hffff5440ffff5400 >> { n216, n657, n118, i_13_, i_12_, i_14_ }; + assign n185 = 64'h8888800080008000 >> { n64, n92, n96, n106, n101, n161 }; + assign n1328 = 64'h0004040400555555 >> { n434, n159, n648, n627, n909, n966 }; + assign n1329 = 16'h0222 >> { n73, n1327, n638, n1328 }; + assign n1330 = 32'd169548571 >> { n216, n201, n250, n628, n677 }; + assign n1331 = 64'h000004dd040504dd >> { n657, n159, n164, n627, n1330, n677 }; + assign n1332 = 32'd128 >> { n985, n986, n1331, n984, n1255 }; + assign n1333 = 32'd1145365572 >> { n627, n672, n971, n164, n169 }; + assign n1334 = 32'd1431655773 >> { n342, n364, n569, n964, n174 }; + assign n1335 = 64'h0008000800088088 >> { n569, n703, n169, n1333, n1334, n990 }; + assign n1336 = 64'h80008080aa00ffff >> { n133, n169, n199, n334, n1058, n206 }; + assign n1337 = 64'h8000000080008000 >> { n295, n148, n1346, n1351, n1051, n1056 }; + assign n186 = 16'h1151 >> { n174, n187, n160, n188 }; + assign o_16_ = 64'h7fffffffffffffff >> { n1336, n1337, n892, n977, n1007, n1020 }; + assign n1339 = 32'd17895263 >> { n250, n166, n537, n433, n428 }; + assign n1340 = 32'd32768 >> { n1011, n1009, n1343, n1010, n1008 }; + assign n1341 = 64'h0888080800880008 >> { n187, n189, n160, n295, n1339, n1340 }; + assign n1342 = 64'hddd5888088808880 >> { n69, n84, n80, n67, n74, i_7_ }; + assign n1343 = 64'h1111111101111111 >> { i_6_, n161, i_8_, n1342, n185, n184 }; + assign n1344 = 64'h1111111111111151 >> { n176, n395, n403, n211, n169, n400 }; + assign n1345 = 64'h0080008000000080 >> { n404, n250, n1048, n1047, n1348, n1049 }; + assign n1346 = 64'h0808080808088808 >> { n408, n409, n211, n133, n1344, n1345 }; + assign n1347 = 64'h77777fff7fff7fff >> { n96, n88, n69, n98, n106, n153 }; + assign n187 = 16'h0777 >> { n64, n92, n69, n106 }; + assign n1348 = 32'd131586 >> { n537, n333, n405, n410, n1347 }; + assign n1349 = 64'ha0b000b0a2b300b3 >> { n250, n146, n295, n328, n537, n327 }; + assign n1350 = 64'h00880080aaaaa0a0 >> { n159, n330, n197, n331, n155, n1050 }; + assign n1351 = 64'h8000808088008888 >> { n133, n250, n332, n199, n1349, n1350 }; + assign n1352 = 64'h0202000200020002 >> { n328, n782, n73, n763, n762, n1120 }; + assign n1353 = 64'h8000000000000000 >> { n1040, n1366, n1113, n1369, n1372, n1126 }; + assign o_17_ = 64'hffffffff7fffffff >> { n726, n710, n1352, n1353, n1357, n1439 }; + assign n1355 = 64'h444c444c555d444c >> { n274, n104, n81, n162, n721, n159 }; + assign n1356 = 64'h0002000200000002 >> { n1063, n133, n671, n825, n1019, n1355 }; + assign n1357 = 64'h0000000080000000 >> { n1061, n1014, n1059, n1356, n1064, n1360 }; + assign n71 = 8'h01 >> { i_6_, i_7_, i_8_ }; + assign n188 = 16'h8000 >> { n74, n120, n88, n161 }; + assign n1358 = 64'h7777777777777772 >> { n160, n340, n627, n630, n89, n379 }; + assign n1359 = 64'h020002022200a2a2 >> { n77, n434, n1079, n1358, n379, n1080 }; + assign n1360 = 64'h0000000080000000 >> { n1018, n963, n1359, n1076, n1077, n1362 }; + assign n1361 = 32'd4160181751 >> { n693, n178, n191, n92, n64 }; + assign n1362 = 32'd572662434 >> { n160, n627, n964, n434, n1361 }; + assign n1363 = 64'ha0b000b0a2b300b3 >> { n133, n622, n169, n736, n159, n737 }; + assign n1364 = 64'h0000000000000002 >> { n113, n391, n395, n435, n647, n334 }; + assign n1365 = 64'h8080008088aa00aa >> { n434, n1364, n169, n649, n206, n1112 }; + assign n1366 = 64'h8000000000000000 >> { n1365, n609, n1103, n1105, n1110, n1111 }; + assign n1367 = 64'h3715371500003715 >> { n787, n250, n744, n89, n630, n94 }; + assign n189 = 64'h75f5f57577ffff7f >> { n161, i_10_, i_11_, i_9_, n153, i_15_ }; + assign n1368 = 64'h4040004055550055 >> { n174, n500, n569, n146, n736, n660 }; + assign n1369 = 64'h0000000080000000 >> { n1119, n1368, n696, n1117, n1118, n1367 }; + assign n1370 = 64'hfffffff7fff7fff7 >> { n207, n200, n87, n220, n328, n787 }; + assign n1371 = 64'h0000000000000008 >> { n1121, n1122, n1124, n1125, n799, n1123 }; + assign n1372 = 64'h0000000200020002 >> { n164, n1370, n558, n621, n638, n1371 }; + assign n1373 = 64'h888a080a080a080a >> { n714, n719, n174, n159, n330, n1170 }; + assign n1374 = 32'd2147483648 >> { n1373, n819, n1382, n1171, n1360 }; + assign n1375 = 64'h0808080888080808 >> { n379, n645, n964, n174, n1137, n1138 }; + assign n1376 = 32'd134742024 >> { n980, n130, n643, n641, n1375 }; + assign n1377 = 64'h00800088a0a0aaaa >> { n237, n169, n151, n633, n68, n1167 }; + assign n190 = 16'h0ddd >> { n169, n192, n191, n89 }; + assign n1378 = 64'h0001010100555555 >> { n169, n259, n333, n289, n170, n311 }; + assign n1379 = 64'h0080008000808080 >> { n97, n79, n250, n1378, n266, n1165 }; + assign n1380 = 64'h0101010101015501 >> { n62, n119, n279, n691, n689, n549 }; + assign n1381 = 64'h0008000000080008 >> { n159, n146, n551, n1169, n1168, n824 }; + assign n1382 = 64'h0808080808080888 >> { n94, n62, n259, n141, n1381, n1380 }; + assign n1383 = 64'h0008000accccffff >> { n290, n169, n251, n65, n1178, n705 }; + assign n1384 = 64'h0000000000008000 >> { n401, n1175, n1383, n784, n785, n273 }; + assign n1385 = 64'h0000008000800080 >> { n684, n137, n1174, n1384, n663, n1176 }; + assign n1386 = 64'h0008080800ffaaff >> { n167, o_13_, n666, n138, n68, n500 }; + assign n1387 = 64'h0000000000000002 >> { n324, n895, n1116, n1121, n1124, n1193 }; + assign n191 = 8'h57 >> { n153, n66, n80 }; + assign n1388 = 64'h5777577757775fff >> { n390, n195, n689, n70, n175, n74 }; + assign o_34_ = 64'h7fffffffffffffff >> { n1388, n654, n1444, n1206, n1208, n1209 }; + assign n1390 = 64'h0000000000000080 >> { n61, n72, n90, n99, n1221, n1222 }; + assign n1391 = 64'h000101010055ffff >> { n94, n77, n97, n79, n113, n87 }; + assign n1392 = 64'h0000800080008000 >> { n89, n87, n1390, n1391, n107, n121 }; + assign n1393 = 64'h7577f5ff75777577 >> { n794, n208, n69, n1190, n74, n120 }; + assign n1394 = 64'h8000000080008000 >> { n685, n500, n1189, n1191, n1386, n1387 }; + assign o_19_ = 64'h7fffffffffffffff >> { n1393, n1394, n1133, n1179, n1357, n1385 }; + assign n1396 = 64'hfdf0ddd0ddd0ddd0 >> { n175, n74, n118, n93, n159, n187 }; + assign n1397 = 64'h0333077701110555 >> { n288, n251, n1396, n66, n159, n261 }; + assign n192 = 4'h8 >> { n91, n161 }; + assign n1398 = 64'h053f053f053f153f >> { n88, n181, n66, n250, n97, n1238 }; + assign n1399 = 64'h0001000000010001 >> { n174, n124, n318, n319, n320, n324 }; + assign n1400 = 64'h0000000080000000 >> { n317, n1399, n314, n1398, n321, n325 }; + assign n1401 = 64'h00b000b3a0b0a2b3 >> { n197, n177, n159, n334, n169, n155 }; + assign n1402 = 64'h0080008080800080 >> { n333, n199, n177, n326, n329, n1401 }; + assign n1403 = 64'h00022222000fffff >> { n73, n164, n97, n412, n368, n328 }; + assign n1404 = 64'h0004000544445555 >> { n409, n177, n169, n138, n421, n424 }; + assign n1405 = 64'h0080808000888888 >> { n73, n194, n259, n396, n394, n1249 }; + assign n1406 = 32'd320017239 >> { n391, n392, n143, n138, n393 }; + assign n1407 = 64'h4444444444444446 >> { n166, n167, n168, n433, n428, n250 }; + assign n193 = 4'h8 >> { n66, n181 }; + assign n1408 = 64'h0000000000008000 >> { n173, n608, n183, n609, n1259, n1264 }; + assign n1409 = 32'd134351362 >> { n164, n1407, n158, n250, n1408 }; + assign n1410 = 64'h0000000000000001 >> { i_11_, i_13_, i_12_, i_14_, n361, n363 }; + assign n1411 = 64'hff82ffaac282ffaa >> { n472, n1410, n576, i_10_, i_9_, n572 }; + assign n1412 = 64'h0002020200aaaaaa >> { n1411, i_8_, n579, n106, n92, n580 }; + assign n1413 = 64'h20a020a020a022a2 >> { n212, n451, n123, n279, n486, n596 }; + assign n1414 = 64'h0002020200aaaaaa >> { n333, n573, n574, n259, n159, n604 }; + assign n1415 = 32'd32768 >> { n599, n1414, n1413, n601, n1263 }; + assign n1416 = 64'h0011011101110111 >> { n292, n120, n96, n71, n255, n474 }; + assign n1417 = 64'h0000000080000000 >> { n735, n734, n725, n741, n1276, n1278 }; + assign n194 = 4'h8 >> { n181, n153 }; + assign o_21_ = 16'hff7f >> { n223, n1416, n1417, n1273 }; + assign n1419 = 64'h1111111111111151 >> { n193, n194, n408, n737, n73, n319 }; + assign n1420 = 64'h1111111111111151 >> { n195, n303, n569, n768, n164, n767 }; + assign n1421 = 64'h0000000000008000 >> { n226, n763, n1419, n1420, n766, n769 }; + assign n1422 = 64'hffffffffffffff7f >> { n208, n251, n666, n527, n152, n669 }; + assign n1423 = 64'h0002020200222222 >> { n110, n1422, n295, n537, n667, n803 }; + assign n1424 = 64'h0507000715370037 >> { n73, n823, n221, n110, n94, n111 }; + assign n1425 = 64'h1111111111111115 >> { n79, n97, n100, n113, n77, n115 }; + assign n1426 = 64'h0000000000008000 >> { n90, n102, n1424, n1425, n867, n868 }; + assign n1427 = 64'h0001010100ffffff >> { n174, n149, n748, n111, n720, n131 }; + assign n195 = 4'h8 >> { n114, n161 }; + assign n1428 = 64'h0080008000000080 >> { n733, n77, n742, n1427, n912, n921 }; + assign n1429 = 64'h010f010f111f010f >> { n706, n910, n434, n73, n639, n631 }; + assign n1430 = 64'h8000000000000000 >> { n1429, n911, n913, n918, n922, n1428 }; + assign n1431 = 32'd134776840 >> { n221, n917, n684, n1430, n1456 }; + assign n1432 = 64'hffffa0a000880080 >> { n500, n279, n634, n909, n565, n931 }; + assign n1433 = 32'd2147483648 >> { n1432, n944, n945, n1321, n1322 }; + assign n1434 = 64'h1115111555551115 >> { n949, n948, n69, n74, n120, n745 }; + assign n1435 = 64'h0111111111111111 >> { n98, n175, n74, n76, n947, n783 }; + assign n1436 = 64'h808080ff008000ff >> { n768, n165, n164, n787, n794, n950 }; + assign n1437 = 64'h000011101f101f10 >> { n133, n365, n1092, n130, n657, n171 }; + assign n196 = 64'h00022222000fffff >> { n89, n197, n62, n143, n198, n199 }; + assign n1438 = 64'h0202020222020202 >> { n171, n550, n623, n174, n1081, n1082 }; + assign n1439 = 64'h8000000000000000 >> { n1437, n1438, n1084, n1087, n1094, n1363 }; + assign n1440 = 64'h0504050405044544 >> { n333, n412, n493, n77, n376, n762 }; + assign o_18_ = 64'h7fffffffffffffff >> { n1440, n619, n1133, n1464, n1374, n1439 }; + assign n1442 = 64'h7575757575750075 >> { n834, i_7_, i_6_, n948, n428, n164 }; + assign n1443 = 64'h0022022202220222 >> { n811, n85, n574, n571, n982, n1205 }; + assign n1444 = 64'h8000000000000000 >> { n1442, n1443, n828, n838, n1171, n1203 }; + assign n1445 = 64'hffa8a8a8a8a8a8a8 >> { n112, n66, n106, n292, n291, n120 }; + assign n1446 = 64'h0001000100010101 >> { n164, n295, n260, n293, n296, n297 }; + assign n1447 = 64'h0004040400555555 >> { n138, n174, n472, n268, n334, n559 }; + assign n197 = 4'h8 >> { n114, n142 }; + assign n1448 = 64'h0080008080800080 >> { n248, n1247, n259, n561, n560, n1403 }; + assign n1449 = 32'd2147516544 >> { n169, n148, n1447, n1448, n557 }; + assign n1450 = 64'h5555777f777f777f >> { n85, n212, n420, n416, n78, n74 }; + assign n1451 = 64'h0808080808080888 >> { n143, n165, n134, n420, n1406, n1450 }; + assign n1452 = 64'h0008008808080888 >> { n418, o_13_, n151, n416, n419, n1404 }; + assign n1453 = 64'h8000000000000000 >> { n1451, n1452, n397, n417, n422, n1405 }; + assign n1454 = 64'h0105010501051115 >> { n662, n690, n119, n174, n718, n951 }; + assign n1455 = 64'h0000000080000000 >> { n712, n1454, n1323, n1434, n1435, n1436 }; + assign n1456 = 32'd134776840 >> { n290, n493, n684, n1455, n952 }; + assign n1457 = 64'h0001010100ffffff >> { n164, n169, n395, n303, n220, n634 }; + assign n72 = 4'h2 >> { n75, n73 }; + assign n198 = 4'h8 >> { n112, n142 }; + assign n1458 = 64'h0008080808080808 >> { n235, n98, n77, n1166, n1161, n1457 }; + assign n1459 = 64'ha0c06444a0c02040 >> { n290, i_11_, i_9_, n174, i_10_, i_15_ }; + assign n1460 = 64'h0080008880808888 >> { n96, n250, n1445, n287, n1233, n1446 }; + assign n1461 = 32'd8421504 >> { n66, n1459, n1460, n1231, n1397 }; + assign n1462 = 64'h8ace00ce0a0e000e >> { n500, n738, n259, n634, n546, n714 }; + assign n1463 = 64'h0000000080000000 >> { n1164, n1159, n1271, n1377, n1379, n1458 }; + assign n1464 = 64'h8000800000008000 >> { n376, n259, n1462, n1158, n1463, n1162 }; + assign n199 = 32'd5723991 >> { n142, n125, n201, n200, n67 }; + assign n200 = 8'h02 >> { i_13_, i_14_, i_12_ }; + assign n201 = 8'h08 >> { i_14_, i_12_, i_13_ }; + assign n202 = 32'd715827882 >> { n203, n215, n210, n214, n134 }; + assign n203 = 64'h0000000000000008 >> { n204, n193, n208, n209, n205, n206 }; + assign n204 = 4'h8 >> { n200, n125 }; + assign n205 = 8'h57 >> { n200, n201, n98 }; + assign n206 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n207 }; + assign n207 = 8'h02 >> { i_10_, i_11_, i_9_ }; + assign n73 = 4'h8 >> { n74, n70 }; + assign n208 = 4'h8 >> { n125, n161 }; + assign n209 = 64'h0000000000000080 >> { i_10_, i_15_, i_12_, i_9_, i_11_, i_14_ }; + assign n210 = 8'h08 >> { n212, n211, n213 }; + assign n211 = 8'h57 >> { n67, n88, n153 }; + assign n212 = 4'h8 >> { n82, n201 }; + assign n213 = 8'h57 >> { n84, n98, n153 }; + assign n214 = 32'd1 >> { n65, n111, n135, n87, n97 }; + assign n215 = 32'd414866943 >> { n181, n216, i_13_, i_12_, i_14_ }; + assign n216 = 16'h0001 >> { i_10_, i_9_, i_11_, i_15_ }; + assign n217 = 32'd2147483648 >> { n1225, n1461, n1237, n306, n1400 }; + assign n74 = 64'h0000000000000008 >> { i_1_, i_0_, i_2_, i_3_, i_5_, i_4_ }; + assign n218 = 4'h8 >> { n66, n114 }; + assign n219 = 16'h8000 >> { n66, n63, n64, n83 }; + assign n220 = 4'h8 >> { n66, n93 }; + assign n221 = 8'h08 >> { i_8_, n178, n74 }; + assign n222 = 4'h8 >> { n69, n63 }; + assign n223 = 8'h80 >> { n96, n147, n70 }; + assign n224 = 64'h0001010100111111 >> { n130, n111, n227, n225, n226, n228 }; + assign n225 = 8'h08 >> { i_15_, n200, n147 }; + assign n226 = 16'h8000 >> { n66, n114, n74, n175 }; + assign n227 = 4'h8 >> { n78, n74 }; + assign n75 = 64'h7dc3ffeb7dd7ffff >> { n76, n66, i_9_, i_10_, i_11_, i_15_ }; + assign n228 = 16'h8000 >> { n74, n91, n229, n120 }; + assign n229 = 8'h8a >> { i_12_, i_13_, i_14_ }; + assign n230 = 32'd1465319511 >> { n231, n77, n232, n111, n133 }; + assign n231 = 8'h57 >> { n112, n216, n229 }; + assign n232 = 8'h08 >> { i_15_, n200, n233 }; + assign n233 = 8'h08 >> { i_10_, i_9_, i_11_ }; + assign n234 = 8'h80 >> { n73, n235, n118 }; + assign n235 = 4'h2 >> { i_13_, i_12_ }; + assign n236 = 16'h0777 >> { n164, n237, n174, n204 }; + assign n237 = 4'h8 >> { n83, n76 }; + assign n76 = 8'h80 >> { i_13_, i_12_, i_14_ }; + assign n238 = 64'hc1ebd1fbc5efd5ff >> { n74, n96, n64, i_8_, i_7_, i_6_ }; + assign n239 = 64'h0008000808080008 >> { n251, n152, n62, n249, n245, n240 }; + assign n240 = 64'h1000101011001111 >> { n174, n232, n242, n244, n243, n241 }; + assign n241 = 32'd2155905024 >> { n85, n78, n83, n74, n66 }; + assign n242 = 16'h0777 >> { n74, n116, n96, n106 }; + assign n243 = 64'h8888800080008000 >> { n74, n63, n96, n71, n216, n229 }; + assign n244 = 8'h57 >> { n83, n91, n200 }; + assign n245 = 64'h00020003aaaaffff >> { n174, n227, n246, n193, n248, n247 }; + assign n246 = 4'h8 >> { n66, n112 }; + assign n247 = 32'd353703231 >> { n118, n93, n66, n91, n76 }; + assign n77 = 8'h08 >> { i_8_, n78, n69 }; + assign n248 = 4'h8 >> { n200, n216 }; + assign n249 = 32'd2863311528 >> { n246, n251, n113, n135, n250 }; + assign n250 = 8'h80 >> { n69, n78, i_8_ }; + assign n251 = 4'h8 >> { n76, n125 }; + assign n252 = 64'h2000202022002222 >> { n123, n250, n263, n264, n258, n253 }; + assign n253 = 64'h0000000100010001 >> { n87, n222, n254, n255, n256, n257 }; + assign n254 = 16'h8000 >> { n114, n74, n71, n142 }; + assign n255 = 8'h80 >> { n96, n207, n70 }; + assign n256 = 32'd2155905024 >> { n93, n112, n66, n74, n70 }; + assign n257 = 32'd2155905024 >> { n118, n114, n63, n74, n66 }; + assign o_5_ = 64'h7fffffffffffffff >> { n1219, n217, n1240, n1243, n1246, n1248 }; + assign n78 = 4'h2 >> { i_6_, i_7_ }; + assign n258 = 64'h4440444055554440 >> { n262, n259, n261, n260, n130, i_8_ }; + assign n259 = 4'h8 >> { n64, n178 }; + assign n260 = 4'h8 >> { n66, n125 }; + assign n261 = 4'h8 >> { n66, n216 }; + assign n262 = 16'h0777 >> { n91, n66, n235, n118 }; + assign n263 = 64'h5d5d5d5d5d5d5dff >> { n112, n83, n91, i_13_, i_12_, i_14_ }; + assign n264 = 64'h75fdfdfdfffd7fdf >> { i_10_, i_11_, i_14_, i_9_, i_15_, n235 }; + assign n265 = 8'h57 >> { n112, n93, n66 }; + assign n266 = 32'd125269879 >> { n74, n71, n268, n267, n141 }; + assign n267 = 4'h8 >> { n74, n106 }; + assign n79 = 4'h8 >> { n66, n80 }; + assign n268 = 4'h2 >> { i_13_, n269 }; + assign n269 = 64'h0000000000000080 >> { i_11_, i_15_, i_12_, i_9_, i_10_, i_14_ }; + assign n270 = 64'h4444444444444445 >> { n123, n94, n164, n134, n265, n271 }; + assign n271 = 64'h8880808088008000 >> { n78, n96, n71, n69, n118, n66 }; + assign n272 = 32'd8 >> { n1230, n278, n281, n273, n282 }; + assign n273 = 32'd572662434 >> { n89, n274, n238, n260, n275 }; + assign n274 = 32'd50462976 >> { n69, n96, i_6_, i_8_, i_7_ }; + assign n275 = 32'd2004844415 >> { n112, n76, n209, n106, n96 }; + assign n276 = 16'hdddf >> { n147, n233, i_15_, n200 }; + assign n277 = 8'h57 >> { n114, n118, n200 }; + assign n80 = 16'h8000 >> { i_10_, i_9_, i_11_, i_15_ }; + assign n278 = 64'h5555555555551555 >> { n251, n261, n280, n247, n244, n279 }; + assign n279 = 32'd3942574847 >> { n96, n69, i_7_, i_8_, i_6_ }; + assign n280 = 8'h57 >> { n83, n91, n76 }; + assign n281 = 16'hddd0 >> { n248, n193, n123, n279 }; + assign n282 = 32'd33685506 >> { n283, n174, n285, n286, n284 }; + assign n283 = 32'd1853849471 >> { n114, i_12_, n112, i_13_, i_14_ }; + assign n284 = 32'd2139062271 >> { n153, n76, n74, n91, n175 }; + assign n285 = 16'h8000 >> { n116, n74, n200, n118 }; + assign n286 = 32'd2155905024 >> { n91, n112, n175, n74, n142 }; + assign n287 = 32'd17895263 >> { n66, n83, n200, n125, n91 }; + assign n81 = 4'h8 >> { n66, n82 }; + assign n288 = 32'd2004875263 >> { n64, n69, i_6_, i_7_, i_8_ }; + assign n289 = 4'h8 >> { n66, n83 }; + assign n290 = 4'h8 >> { n74, n92 }; + assign n291 = 8'h02 >> { i_9_, i_11_, i_10_ }; + assign n292 = 8'h01 >> { i_10_, i_9_, i_11_ }; + assign n293 = 16'h8000 >> { n74, n106, n216, n142 }; + assign n294 = 32'd2155905024 >> { n98, n181, n175, n66, n69 }; + assign n295 = 8'h80 >> { n116, n74, i_8_ }; + assign n296 = 16'h8000 >> { n66, n114, n74, n120 }; + assign n297 = 32'd2155905024 >> { n120, n175, n66, n74, n118 }; + assign n82 = 16'h0080 >> { i_10_, i_9_, i_11_, i_15_ }; + assign n298 = 32'd1162167552 >> { n288, n300, n299, n302, n301 }; + assign n299 = 16'hf888 >> { n64, n92, n96, n106 }; + assign n300 = 8'h57 >> { n200, n142, n216 }; + assign n301 = 32'd2155905024 >> { n142, n200, n83, n92, n74 }; + assign n302 = 32'd5723991 >> { n142, n216, n125, n114, n200 }; + assign n303 = 4'h8 >> { n83, n200 }; + assign n304 = 64'haeabafabfebfffff >> { n200, n142, i_10_, i_9_, i_11_, i_15_ }; + assign n305 = 4'h8 >> { n125, n142 }; + assign n306 = 64'h888a080a080a080a >> { n280, n313, n133, n159, n307, n309 }; + assign n307 = 16'h0002 >> { n87, n79, n97, n308 }; + assign n83 = 16'h0002 >> { i_9_, i_11_, i_15_, i_10_ }; + assign n308 = 16'h0777 >> { n216, n76, n66, n181 }; + assign n309 = 64'h0010001110101111 >> { n250, n290, n81, n310, n311, n312 }; + assign n310 = 16'h0777 >> { n76, n83, n66, n98 }; + assign n311 = 16'h8000 >> { n66, n69, n84, n106 }; + assign n312 = 16'h8000 >> { n96, n66, n84, n106 }; + assign n313 = 16'h5557 >> { n82, n67, n101, n66 }; + assign n314 = 32'd1162149957 >> { n288, n315, n133, n313, n316 }; + assign n315 = 4'h8 >> { n76, n216 }; + assign n316 = 64'h8888800080008000 >> { n74, n175, n69, n106, n66, n98 }; + assign n317 = 16'h8000 >> { n74, n175, n76, n216 }; + assign n84 = 16'h0080 >> { i_11_, i_9_, i_10_, i_15_ }; + assign n318 = 16'h8000 >> { n66, n64, n84, n92 }; + assign n319 = 16'h8000 >> { n66, n74, n120, n181 }; + assign n320 = 32'd2147483648 >> { n66, n69, n78, n67, i_8_ }; + assign n321 = 64'h0010101000551155 >> { n164, n251, n290, n322, n65, n323 }; + assign n322 = 16'h5557 >> { n101, n88, n80, n66 }; + assign n323 = 16'h8000 >> { n66, n64, n175, n181 }; + assign n324 = 16'h8000 >> { n66, n69, n67, n106 }; + assign n325 = 32'd17895263 >> { n169, n110, n250, n87, n100 }; + assign n326 = 16'hab23 >> { n199, n133, n169, n206 }; + assign n327 = 32'd89458551 >> { n201, n216, n142, n200, n181 }; + assign n85 = 8'h02 >> { i_7_, i_8_, i_6_ }; + assign n328 = 32'd4253023743 >> { i_13_, i_14_, i_12_, i_15_, n207 }; + assign n329 = 16'hddd0 >> { n331, n330, n332, n165 }; + assign n330 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n291 }; + assign n331 = 8'h57 >> { n69, n96, n106 }; + assign n332 = 32'd353703231 >> { n153, n142, n67, n201, n125 }; + assign n333 = 4'h8 >> { n98, n201 }; + assign n334 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n233 }; + assign n335 = 64'h0002002202020222 >> { n204, n174, n138, n197, n339, n336 }; + assign n336 = 8'h45 >> { n134, n337, n338 }; + assign n337 = 8'h01 >> { n232, n303, n305 }; + assign n86 = 64'h77777fff7fff7fff >> { n74, n82, n64, n80, n66, n85 }; + assign n338 = 16'haaa8 >> { n197, n305, n141, n123 }; + assign n339 = 8'ha8 >> { n177, n143, n340 }; + assign n340 = 4'h8 >> { n200, n118 }; + assign n341 = 4'h8 >> { n123, n144 }; + assign n342 = 4'h8 >> { n93, n200 }; + assign n343 = 4'h8 >> { n216, n142 }; + assign n344 = 8'ha8 >> { n154, n345, n259 }; + assign n345 = 4'h8 >> { n200, n91 }; + assign n346 = 32'd353697813 >> { n277, n138, n154, n164, n347 }; + assign n347 = 16'h8000 >> { n74, n70, n91, n142 }; + assign n87 = 4'h8 >> { n66, n88 }; + assign n348 = 64'h0c0e1d1f1d1f1d1f >> { n73, n248, n232, n177, n144, n138 }; + assign n349 = 4'h8 >> { n114, n200 }; + assign n350 = 32'd269488145 >> { n62, n143, n354, n351, n353 }; + assign n351 = 4'h2 >> { n352, n73 }; + assign n352 = 64'hf9f9fbfff9f9f9ff >> { i_9_, n200, n142, i_15_, i_11_, i_10_ }; + assign n353 = 4'h8 >> { n73, n154 }; + assign n354 = 8'h57 >> { n114, n125, n200 }; + assign n355 = 16'h22a2 >> { n305, n276, n143, n356 }; + assign n356 = 64'h7f7f7fffff7fffff >> { n83, n112, i_8_, n74, n142, n116 }; + assign n357 = 64'h0111055503330777 >> { n137, n349, n62, n303, n134, n342 }; + assign n61 = 8'h8a >> { n68, n62, n65 }; + assign n88 = 16'h0008 >> { i_10_, i_11_, i_9_, i_15_ }; + assign n358 = 64'h0001010100ffffff >> { n268, n159, n340, n137, n227, n134 }; + assign n359 = 16'h2022 >> { i_8_, n364, n360, n151 }; + assign n360 = 16'h0001 >> { n361, n363, n364, n365 }; + assign n361 = 4'h8 >> { n88, n362 }; + assign n362 = 8'h01 >> { i_13_, i_12_, i_14_ }; + assign n363 = 4'h8 >> { n98, n362 }; + assign n364 = 4'h8 >> { n84, n362 }; + assign n365 = 4'h8 >> { n93, n161 }; + assign n366 = 64'h0a020a020a022a22 >> { n368, n195, n108, n62, n208, n367 }; + assign n367 = 32'd17895263 >> { n365, n164, n364, n123, n134 }; + assign n89 = 4'h8 >> { n69, n71 }; + assign n368 = 4'h8 >> { n83, n161 }; + assign n369 = 32'd3368610504 >> { i_8_, n195, n164, n370, n151 }; + assign n370 = 4'h8 >> { n80, n362 }; + assign n371 = 4'h8 >> { n112, n161 }; + assign n372 = 64'h00cdcdcd00454545 >> { n376, o_13_, n364, n177, n373, n143 }; + assign n373 = 4'h1 >> { n374, n370 }; + assign n374 = 4'h8 >> { n101, n362 }; + assign o_13_ = 4'h8 >> { n69, n78 }; + assign n376 = 16'h0777 >> { n98, n362, n83, n161 }; + assign n377 = 8'h01 >> { n208, n361, n378 }; + assign n90 = 16'h8000 >> { n64, n76, n91, n92 }; + assign n378 = 4'h8 >> { n67, n362 }; + assign n379 = 4'h8 >> { n118, n161 }; + assign n380 = 16'h5d7f >> { n74, n69, i_8_, n78 }; + assign n381 = 32'd33685506 >> { n388, n134, n382, n384, n386 }; + assign n382 = 4'h2 >> { n383, n73 }; + assign n383 = 64'hd014d555fabeffff >> { n362, n161, i_11_, i_10_, i_9_, i_15_ }; + assign n384 = 16'h5551 >> { n195, n379, n385, n68 }; + assign n385 = 8'h57 >> { n93, n112, n161 }; + assign n386 = 64'h00022222000fffff >> { n138, n192, n73, n123, n379, n387 }; + assign n387 = 16'h0777 >> { n82, n362, n112, n161 }; + assign n91 = 16'h0008 >> { i_9_, i_15_, i_11_, i_10_ }; + assign n388 = 64'h898ff9ff999ff9ff >> { i_11_, n362, n161, i_15_, i_10_, i_9_ }; + assign n389 = 16'h0001 >> { n368, n390, n378, n374 }; + assign n390 = 4'h8 >> { n216, n161 }; + assign n391 = 4'h8 >> { n153, n88 }; + assign n392 = 4'h8 >> { n101, n201 }; + assign n393 = 4'h8 >> { n88, n201 }; + assign n394 = 64'h0133053700320537 >> { n421, n134, n395, n94, n176, n123 }; + assign n395 = 4'h8 >> { n84, n153 }; + assign n396 = 64'hdddd5ddfddff5dff >> { n153, i_10_, n201, i_11_, i_9_, i_15_ }; + assign n397 = 64'h8000000080008000 >> { n159, n411, n407, n398, n414, n402 }; + assign n92 = 8'h08 >> { i_7_, i_6_, i_8_ }; + assign n398 = 64'h0100010001000101 >> { n177, n174, n213, n399, n400, n401 }; + assign n399 = 64'h8080808080808000 >> { n82, n101, n84, n153, n69, n106 }; + assign n400 = 64'h8888800080008000 >> { n120, n69, n96, n106, n181, n201 }; + assign n401 = 32'd2155905024 >> { n201, n153, n92, n74, n67 }; + assign n402 = 64'h0020002220202222 >> { n299, n165, n403, n404, n405, n406 }; + assign n403 = 4'h8 >> { n153, n101 }; + assign n404 = 16'h0777 >> { n98, n201, n181, n153 }; + assign n405 = 16'h8000 >> { n64, n175, n181, n153 }; + assign n406 = 64'h77777fff7fff7fff >> { n69, n98, n96, n88, n106, n153 }; + assign n407 = 64'h0001010100555555 >> { n177, n164, n333, n408, n409, n410 }; + assign n93 = 16'h0008 >> { i_11_, i_15_, i_10_, i_9_ }; + assign n408 = 4'h8 >> { n181, n201 }; + assign n409 = 4'h8 >> { n153, n80 }; + assign n410 = 16'h8000 >> { n96, n84, n106, n153 }; + assign n411 = 16'h0002 >> { n194, n412, n409, n413 }; + assign n412 = 4'h8 >> { n153, n98 }; + assign n413 = 8'h57 >> { n88, n67, n201 }; + assign n414 = 64'h00030002ffffaaaa >> { n164, n187, n392, n415, n212, n211 }; + assign n415 = 4'h8 >> { n67, n201 }; + assign n416 = 4'h8 >> { n80, n201 }; + assign n417 = 64'h0015151500373737 >> { n143, n138, n333, n418, n62, n412 }; + assign n94 = 8'h08 >> { i_8_, n96, n95 }; + assign n418 = 4'h8 >> { n67, n153 }; + assign n419 = 64'h00011111000fffff >> { n138, n143, n391, n333, n415, n420 }; + assign n420 = 4'h8 >> { n84, n201 }; + assign n421 = 8'h57 >> { n101, n80, n201 }; + assign n422 = 64'h0002020200aa22aa >> { n415, n94, n403, n143, n134, n423 }; + assign n423 = 32'd320017239 >> { n89, n94, n333, n412, n123 }; + assign n424 = 16'h8000 >> { n96, n106, n82, n201 }; + assign n425 = 16'h8000 >> { n426, n1252, n444, n454 }; + assign n426 = 4'h8 >> { n427, n431 }; + assign n427 = 64'h0015151500373737 >> { n119, n133, n428, n430, n73, n429 }; + assign n95 = 4'h1 >> { i_6_, i_7_ }; + assign n428 = 4'h8 >> { n91, n153 }; + assign n429 = 4'h8 >> { n118, n153 }; + assign n430 = 4'h8 >> { n200, n101 }; + assign n431 = 64'h0001030300555757 >> { n123, n433, n62, n432, n435, n434 }; + assign n432 = 4'h8 >> { n125, n153 }; + assign n433 = 4'h8 >> { n83, n153 }; + assign n434 = 8'h08 >> { i_8_, n178, n64 }; + assign n435 = 4'h8 >> { n114, n153 }; + assign n436 = 16'h0777 >> { n125, n153, n67, n200 }; + assign n437 = 64'h0080008000800000 >> { n101, n80, i_8_, n95, n96, n200 }; + assign n96 = 64'h0000000000000002 >> { i_1_, i_0_, i_2_, i_4_, i_3_, i_5_ }; + assign n438 = 8'h57 >> { n84, n80, n200 }; + assign n439 = 16'h0777 >> { n428, n73, o_13_, n440 }; + assign n440 = 4'h8 >> { n200, n80 }; + assign n441 = 4'h8 >> { n200, n98 }; + assign n442 = 4'h8 >> { n269, i_13_ }; + assign n443 = 4'h8 >> { n200, n88 }; + assign n444 = 64'h0008000800080808 >> { n62, n77, n435, n450, n452, n445 }; + assign n445 = 64'h2000202022002222 >> { n130, n434, n449, n448, n446, n447 }; + assign n446 = 16'h8000 >> { n116, n74, n118, n153 }; + assign n447 = 64'h7f7fff7f7fffffff >> { n91, n114, i_8_, n116, n153, n74 }; + assign n97 = 4'h8 >> { n66, n98 }; + assign n448 = 8'h57 >> { n93, n83, n153 }; + assign n449 = 64'hdd5dff7fff7fff7f >> { i_10_, n153, i_9_, n200, i_15_, i_11_ }; + assign n450 = 16'heee0 >> { n442, n451, n159, n134 }; + assign n451 = 4'h8 >> { n200, n82 }; + assign n452 = 32'd1465319511 >> { n453, n440, n443, n441, n77 }; + assign n453 = 16'h0777 >> { n120, n74, n96, n106 }; + assign n454 = 64'h0008000800000008 >> { n464, n73, n462, n463, n455, n459 }; + assign n455 = 64'h00011111000fffff >> { n94, n77, n457, n430, n456, n458 }; + assign n456 = 4'h8 >> { n209, i_13_ }; + assign n457 = 4'h8 >> { n84, n200 }; + assign n62 = 4'h8 >> { n63, n64 }; + assign n98 = 16'h0008 >> { i_9_, i_11_, i_10_, i_15_ }; + assign n458 = 4'h8 >> { n67, n200 }; + assign n459 = 64'h40045115e0a4f1b5 >> { n442, n460, n438, n461, n133, n164 }; + assign n460 = 16'h8000 >> { n63, n74, n209, i_13_ }; + assign n461 = 16'h0777 >> { n118, n153, n84, n200 }; + assign n462 = 32'd3974950056 >> { n250, n94, n442, n457, n221 }; + assign n463 = 16'haaa8 >> { n442, n456, n430, n133 }; + assign n464 = 64'h41c0ebea55d5ffff >> { n153, n200, i_9_, i_10_, i_11_, i_15_ }; + assign n465 = 64'h8000000000000000 >> { n1255, n478, n491, n508, n1258, n532 }; + assign n466 = 64'ha8a8a8a088888880 >> { n299, n82, n181, n67, n164, n362 }; + assign n467 = 32'd353703231 >> { n74, n69, n96, n106, n120 }; + assign n99 = 64'h0010001110101111 >> { n77, n81, n100, n104, n102, n105 }; + assign n468 = 32'd2155905024 >> { n93, n112, n96, n106, n161 }; + assign n469 = 32'd67488989 >> { n365, n174, n169, n470, n164 }; + assign n470 = 16'h5557 >> { n112, n91, n216, n161 }; + assign n471 = 64'h0303000157570055 >> { n133, n376, n164, n208, n472, n250 }; + assign n472 = 4'h8 >> { n181, n362 }; + assign n473 = 64'h0010101000111111 >> { n133, n179, n390, n385, n474, n475 }; + assign n474 = 64'h8080800000800000 >> { n362, n161, i_15_, n96, n106, n292 }; + assign n475 = 32'd2155905024 >> { n125, n216, n69, n106, n161 }; + assign n476 = 64'h0070507000735173 >> { n133, n368, n174, n477, n159, n208 }; + assign n477 = 32'd5723991 >> { n362, n98, n91, n83, n161 }; + assign n100 = 4'h8 >> { n66, n101 }; + assign n478 = 32'd2147516544 >> { n164, n484, n485, n489, n479 }; + assign n479 = 64'hddd0ddd0ddd00000 >> { n482, n480, n481, n453, n483, n159 }; + assign n480 = 16'h0777 >> { n200, n98, n83, n153 }; + assign n481 = 16'h0777 >> { n200, n67, n83, n153 }; + assign n482 = 8'h57 >> { n74, n64, n92 }; + assign n483 = 32'd4294834165 >> { i_9_, i_11_, i_15_, i_10_, n153 }; + assign n484 = 32'd1 >> { n456, n441, n443, n430, n451 }; + assign n485 = 64'h50f051f154f455f5 >> { n432, n133, n179, n488, n487, n486 }; + assign n486 = 4'h8 >> { n216, n153 }; + assign n487 = 16'h0777 >> { n181, n200, n114, n153 }; + assign n101 = 16'h0080 >> { i_9_, i_10_, i_11_, i_15_ }; + assign n488 = 32'd1568636799 >> { n64, i_6_, n74, i_7_, i_8_ }; + assign n489 = 64'h00020003aaaaffff >> { n250, n119, n441, n430, n486, n490 }; + assign n490 = 16'h5557 >> { n88, n181, n67, n200 }; + assign n491 = 64'h0000000000000080 >> { n496, n498, n499, n492, n502, n507 }; + assign n492 = 32'd3477423429 >> { n495, n493, n174, n494, n162 }; + assign n493 = 32'd4160223231 >> { n74, n69, i_6_, i_7_, i_8_ }; + assign n494 = 64'ha2f3aafba6f7aeff >> { n82, n67, n98, i_12_, i_13_, i_14_ }; + assign n495 = 64'hf8f9fcfdfafbfeff >> { n64, n69, n96, i_8_, i_7_, i_6_ }; + assign n496 = 16'haaa2 >> { n432, n435, n497, o_12_ }; + assign n497 = 64'h7777575f7777f77f >> { n161, i_10_, i_11_, i_9_, n362, i_15_ }; + assign n102 = 64'h8080008080000000 >> { n76, n66, i_15_, n74, n103, n70 }; + assign n498 = 16'haaa2 >> { n259, n227, n279, n180 }; + assign n499 = 32'd2863311402 >> { n227, n94, n501, n500, n170 }; + assign n500 = 32'd3522942463 >> { n96, n64, i_7_, i_8_, i_6_ }; + assign n501 = 8'h57 >> { n78, n71, n69 }; + assign n502 = 64'h1000101011001111 >> { n130, n174, n506, n503, n505, n504 }; + assign n503 = 16'h1357 >> { n201, n101, n88, n362 }; + assign n504 = 32'd2155905024 >> { n201, n200, n63, n101, n74 }; + assign n505 = 16'h8000 >> { n116, n74, n200, n88 }; + assign n506 = 32'd17764639 >> { n362, n101, n82, n201, n200 }; + assign n507 = 64'h00080a0a00ccffff >> { n166, n168, n134, n274, n279, n238 }; + assign n103 = 8'h08 >> { i_9_, i_10_, i_11_ }; + assign n508 = 32'd33685506 >> { n515, n509, n511, n510, n512 }; + assign n509 = 8'h8a >> { n187, n174, n161 }; + assign n510 = 16'haaa2 >> { n123, n164, n279, n194 }; + assign n511 = 16'haaa2 >> { n89, n274, n238, n167 }; + assign n512 = 64'h0ddd0ddd0ddd0000 >> { n513, n467, n195, n119, n514, n133 }; + assign n513 = 16'h0777 >> { n88, n362, n118, n161 }; + assign n514 = 32'd353703231 >> { n88, n84, n114, n161, n362 }; + assign n515 = 64'hddddddfddfdddfff >> { n169, n174, i_11_, i_10_, i_15_, i_9_ }; + assign n516 = 64'h8888800080008000 >> { n74, n63, n69, n71, n80, n161 }; + assign n517 = 64'h8888800080008000 >> { n82, n362, n112, n153, n106, n96 }; + assign n104 = 16'h0777 >> { n85, n64, n69, n71 }; + assign n518 = 32'd5723991 >> { n362, n98, n101, n67, n161 }; + assign n519 = 32'd1434419071 >> { n70, n118, n63, n82, n74 }; + assign n520 = 64'h0004000544445555 >> { n434, n164, n409, n370, n211, n521 }; + assign n521 = 32'd2155905024 >> { n70, n63, n84, n74, n161 }; + assign n522 = 64'h0000000200020002 >> { n364, n130, n523, n525, n526, n524 }; + assign n523 = 16'h8000 >> { n64, n92, n82, n362 }; + assign n524 = 64'h77777fff7fff7fff >> { n88, n161, n181, n153, n74, n175 }; + assign n525 = 64'h8888800080008000 >> { n80, n161, n153, n82, n78, n69 }; + assign n526 = 16'h8000 >> { n63, n74, n98, n161 }; + assign n527 = 16'h5557 >> { n362, n200, n201, n67 }; + assign n105 = 16'h8000 >> { n66, n69, n106, n80 }; + assign n528 = 64'h0080008000000080 >> { i_12_, i_13_, i_14_, n63, n64, n88 }; + assign n529 = 64'h1515001537370037 >> { n162, n530, n227, n94, n160, n73 }; + assign n530 = 32'd5723991 >> { n161, n101, n80, n84, n153 }; + assign n531 = 16'h5557 >> { n362, n200, n201, n181 }; + assign n532 = 64'h0000000000000080 >> { n533, n534, n540, n536, n541, n543 }; + assign n533 = 64'haaaaaaaaaaaaaaa2 >> { n390, n195, n403, n409, n211, n123 }; + assign n534 = 64'h08aa08aa00aa08aa >> { i_12_, i_13_, n535, i_14_, n82, n123 }; + assign n535 = 16'h5557 >> { n125, n181, n88, n161 }; + assign n536 = 32'd488512799 >> { n539, n538, n164, n403, n171 }; + assign n537 = 8'h80 >> { n78, n74, i_8_ }; + assign n106 = 8'h02 >> { i_6_, i_7_, i_8_ }; + assign n538 = 32'd50462976 >> { n64, n96, i_7_, i_8_, i_6_ }; + assign n539 = 64'h0080008000000080 >> { i_12_, i_13_, i_14_, n63, n64, n98 }; + assign n540 = 16'h5551 >> { n428, n429, n448, n279 }; + assign n541 = 32'd1381653 >> { n434, n160, n412, n250, n542 }; + assign n542 = 16'h0080 >> { i_6_, n82, n362, n69 }; + assign n543 = 16'heee0 >> { n531, n279, n501, n544 }; + assign n544 = 64'hd7dfdedff7fffeff >> { n153, i_10_, n161, i_11_, i_9_, i_15_ }; + assign n545 = 16'h4454 >> { n547, o_13_, n192, n546 }; + assign n546 = 4'h2 >> { n94, n501 }; + assign n547 = 32'd1 >> { n268, n395, n392, n409, n154 }; + assign n107 = 64'h0008080800aaaaaa >> { n97, n117, n119, n62, n108, n109 }; + assign n548 = 64'h0008000800000008 >> { n146, n159, n549, n551, n552, n554 }; + assign n549 = 16'haa2a >> { n368, n330, n550, n89 }; + assign n550 = 8'h57 >> { n66, n153, n84 }; + assign n551 = 8'h8a >> { n501, n151, n289 }; + assign n552 = 16'h1115 >> { n268, n420, n177, n553 }; + assign n553 = 16'h8000 >> { n64, n83, n178, n76 }; + assign n554 = 64'h0101010101010111 >> { n62, n259, n138, n141, n555, n556 }; + assign n555 = 16'h8000 >> { n69, n83, n106, n161 }; + assign n556 = 32'd2147483648 >> { n64, n178, n84, n200, i_8_ }; + assign n557 = 64'h0001010100555555 >> { n227, n164, n208, n176, n81, n558 }; + assign n63 = 8'h08 >> { i_8_, i_7_, i_6_ }; + assign n108 = 4'h1 >> { n94, n89 }; + assign n558 = 4'h8 >> { n73, n195 }; + assign n559 = 32'd1431655764 >> { n212, n451, n220, n218, n501 }; + assign n560 = 16'h0777 >> { o_12_, n204, n130, n370 }; + assign n561 = 32'd1465319511 >> { n206, n89, n315, n261, n227 }; + assign o_14_ = 4'h2 >> { i_1_, i_0_ }; + assign n563 = 8'h80 >> { n564, n565, n566 }; + assign n564 = 64'h4141414141414155 >> { n153, i_11_, i_12_, i_9_, i_10_, n166 }; + assign n565 = 8'h57 >> { n88, n98, n142 }; + assign n566 = 16'h0777 >> { n161, n98, n83, n362 }; + assign n567 = 16'hff7f >> { i_3_, n568, i_5_, n63 }; + assign n109 = 64'h0001010100555555 >> { n77, n94, n111, n113, n110, n115 }; + assign n568 = 8'h02 >> { i_0_, i_2_, i_1_ }; + assign n569 = 4'h8 >> { n114, n362 }; + assign n570 = 32'd3587560704 >> { n571, n573, i_12_, n147, n563 }; + assign n571 = 4'h8 >> { n85, n572 }; + assign n572 = 64'h0000000000000008 >> { i_0_, i_2_, i_5_, i_3_, i_1_, i_4_ }; + assign n573 = 4'h8 >> { n71, n572 }; + assign n574 = 4'h1 >> { i_10_, i_9_ }; + assign n575 = 8'h57 >> { n106, n92, n576 }; + assign n576 = 16'h0002 >> { i_4_, i_5_, i_3_, n568 }; + assign n577 = 8'h02 >> { i_10_, i_9_, i_11_ }; + assign n110 = 4'h8 >> { n66, n84 }; + assign n578 = 16'hff7f >> { i_5_, n568, n71, i_3_ }; + assign n579 = 16'h0080 >> { i_3_, i_6_, i_5_, n568 }; + assign n580 = 64'he6f7e6ffe6f7e6f7 >> { i_5_, i_4_, i_3_, i_2_, i_0_, i_1_ }; + assign n581 = 64'h0000000080000000 >> { n382, n590, n1415, n605, n606, n582 }; + assign n582 = 32'd32768 >> { n369, n586, n587, n588, n583 }; + assign n583 = 64'h020a020a020a222a >> { n368, n371, n134, n123, n379, n584 }; + assign n584 = 32'd825307509 >> { n62, n89, n585, n208, n94 }; + assign n585 = 64'hd6def7ff56de77ff >> { i_10_, n161, n362, i_9_, i_15_, i_11_ }; + assign n586 = 64'h0001010100555555 >> { n62, n123, n365, n368, n195, n384 }; + assign n587 = 64'hd0ddf0ffd0ddd0dd >> { i_8_, n364, n370, n380, n360, n151 }; + assign n111 = 4'h8 >> { n112, n76 }; + assign n588 = 64'h222a222a222a020a >> { i_8_, n376, n164, o_13_, n364, n589 }; + assign n589 = 64'h00011111000fffff >> { n434, n192, n73, n123, n364, n365 }; + assign n590 = 8'h8a >> { n573, n593, n591 }; + assign n591 = 16'h0ddd >> { n78, n572, n592, n573 }; + assign n592 = 4'h1 >> { n141, n363 }; + assign n593 = 64'h0000000000000002 >> { n197, n268, n368, n364, n365, n594 }; + assign n594 = 16'h0777 >> { n88, n362, n114, n161 }; + assign n595 = 4'h1 >> { o_13_, o_12_ }; + assign n596 = 64'h0002020200aaaaaa >> { n164, n227, n176, n412, n195, n597 }; + assign n597 = 16'h7707 >> { i_5_, n598, n106, n572 }; + assign n112 = 16'h0008 >> { i_10_, i_15_, i_11_, i_9_ }; + assign n598 = 16'h0008 >> { i_1_, i_3_, i_4_, i_0_ }; + assign n599 = 64'hccc4ccc4ccc44444 >> { n201, n200, n84, n80, o_12_, n600 }; + assign n600 = 64'h0000000000000008 >> { n443, n368, n430, n458, n413, n205 }; + assign n601 = 32'd33686050 >> { n62, n159, n432, n602, n603 }; + assign n602 = 16'h5554 >> { n409, n395, n392, n501 }; + assign n603 = 64'h0000077707770777 >> { n250, n192, n133, n390, n164, n208 }; + assign n604 = 64'h00020003aaaaffff >> { n130, n174, n416, n440, n370, n531 }; + assign n605 = 64'hc4d5c4d50000c4d5 >> { n388, n434, n133, n377, n373, n77 }; + assign n606 = 64'h0101000155550055 >> { n73, n279, n192, n368, n195, n607 }; + assign n607 = 16'haaa8 >> { n390, n208, n472, n434 }; + assign n113 = 4'h8 >> { n114, n76 }; + assign n608 = 4'h2 >> { n182, n133 }; + assign n609 = 32'd353719573 >> { n174, n187, n161, n80, n188 }; + assign n610 = 64'h01010155030303ff >> { n73, n133, n250, n415, n212, n194 }; + assign n611 = 64'h8000000000000000 >> { n426, n1252, n444, n454, n612, n615 }; + assign n612 = 16'h222a >> { n441, n430, n159, n613 }; + assign n613 = 64'h00011111000fffff >> { n432, n614, n164, n134, n165, n138 }; + assign n614 = 4'h8 >> { n200, n181 }; + assign n615 = 64'h0808080808080888 >> { n486, n456, n441, n134, n616, n617 }; + assign n616 = 32'd1426421511 >> { n250, n242, n457, n227, n435 }; + assign n617 = 64'h05075577050f557f >> { n458, n165, n443, n451, i_8_, n259 }; + assign n114 = 16'h0002 >> { i_10_, i_11_, i_15_, i_9_ }; + assign o_10_ = 4'hd >> { n130, n694 }; + assign n619 = 4'h2 >> { n632, n620 }; + assign n620 = 8'h08 >> { n621, n625, n629 }; + assign n621 = 8'h2a >> { n550, n622, n123 }; + assign n622 = 8'h80 >> { n146, n623, n624 }; + assign n623 = 32'd4160747391 >> { i_12_, i_13_, i_15_, n147, i_14_ }; + assign n624 = 32'd4292870103 >> { i_13_, i_14_, i_12_, i_15_, n147 }; + assign n625 = 64'h0002020200aaffff >> { n174, n123, n628, n627, n160, n626 }; + assign n626 = 32'd2113929087 >> { i_15_, i_13_, i_12_, i_14_, n103 }; + assign n627 = 4'h8 >> { n118, n362 }; + assign n115 = 32'd2155905024 >> { n93, n83, n116, n74, n76 }; + assign n628 = 4'h8 >> { n91, n362 }; + assign n629 = 64'h0001010100ffffff >> { n174, n123, n365, n368, n630, n631 }; + assign n630 = 4'h8 >> { n66, n118 }; + assign n631 = 4'h8 >> { n76, n80 }; + assign n632 = 4'h2 >> { n633, n174 }; + assign n633 = 8'h01 >> { n303, n363, n634 }; + assign n634 = 4'h8 >> { n83, n201 }; + assign n635 = 4'h8 >> { n174, n197 }; + assign n636 = 16'h8000 >> { n63, n74, n76, n91 }; + assign n637 = 4'h8 >> { n91, n201 }; + assign n116 = 4'h8 >> { i_6_, i_7_ }; + assign n638 = 32'd134744064 >> { i_12_, i_13_, i_14_, n114, n123 }; + assign n639 = 4'h8 >> { n118, n201 }; + assign n640 = 16'ha888 >> { n343, i_8_, n154, n130 }; + assign n641 = 64'h7fff7fff7f7f7fff >> { i_8_, n142, n161, n91, n116, n74 }; + assign n642 = 64'h2202020202020202 >> { n653, n645, n646, n174, n643, n651 }; + assign n643 = 8'ha8 >> { n100, n644, n123 }; + assign n644 = 8'h08 >> { i_12_, n101, i_14_ }; + assign n645 = 4'h1 >> { n403, n100 }; + assign n646 = 16'h0002 >> { n647, n648, n650, n649 }; + assign n647 = 4'h8 >> { n142, n88 }; + assign n117 = 4'h8 >> { n76, n118 }; + assign n648 = 4'h8 >> { n142, n82 }; + assign n649 = 8'h57 >> { n153, n66, n88 }; + assign n650 = 4'h8 >> { n142, n101 }; + assign n651 = 8'h5d >> { n652, n191, n130 }; + assign n652 = 4'h8 >> { n142, n80 }; + assign n653 = 8'h57 >> { n153, n66, n82 }; + assign n654 = 8'h80 >> { n1269, n663, n670 }; + assign n655 = 64'h8808880888008000 >> { i_13_, i_15_, i_14_, i_12_, n233, n123 }; + assign n656 = 64'h111f010f010f010f >> { n550, n623, n123, n174, n171, n657 }; + assign n657 = 4'h8 >> { n93, n362 }; + assign n64 = 64'h0000000000000001 >> { i_1_, i_0_, i_2_, i_4_, i_5_, i_3_ }; + assign n118 = 16'h0080 >> { i_15_, i_9_, i_11_, i_10_ }; + assign n658 = 32'd33685506 >> { n215, n123, n659, n660, n661 }; + assign n659 = 64'h0000800080008000 >> { i_12_, i_13_, n88, n63, n74, i_14_ }; + assign n660 = 64'h8888800080008000 >> { n112, n362, n114, n229, n63, n74 }; + assign n661 = 32'd2139062271 >> { n76, n66, n175, n147, n74 }; + assign n662 = 64'h0000800080008000 >> { i_12_, i_13_, n181, n116, n74, i_14_ }; + assign n663 = 64'h0002000200000002 >> { n669, n123, n667, n664, n665, n668 }; + assign n664 = 16'haa2a >> { n251, n152, n527, n123 }; + assign n665 = 16'haaa8 >> { n666, n204, n378, n174 }; + assign n666 = 4'h8 >> { n125, n201 }; + assign n667 = 16'haaa8 >> { n666, n204, n208, n123 }; + assign n119 = 16'hf888 >> { n120, n69, n96, n106 }; + assign n668 = 64'hf77f77ff7f777f7f >> { i_12_, i_13_, i_15_, i_14_, n174, n577 }; + assign n669 = 16'h5557 >> { n153, n66, n142, n67 }; + assign n670 = 64'h0000000000000080 >> { n671, n673, n676, n679, n683, n687 }; + assign n671 = 8'h2a >> { n672, n334, n123 }; + assign n672 = 32'd4292870103 >> { i_13_, i_14_, i_12_, i_15_, n233 }; + assign n673 = 16'haaa8 >> { n675, n180, n674, n174 }; + assign n674 = 4'h8 >> { n76, n82 }; + assign n675 = 4'h8 >> { n216, n362 }; + assign n676 = 8'h8a >> { n678, n677, n174 }; + assign n677 = 4'h8 >> { n112, n362 }; + assign n120 = 8'h08 >> { i_6_, i_7_, i_8_ }; + assign n678 = 16'h0777 >> { n82, n161, n66, n112 }; + assign n679 = 64'h4000404055005555 >> { n174, n123, n680, n330, n682, n681 }; + assign n680 = 32'd2418671615 >> { n291, i_13_, i_15_, i_12_, i_14_ }; + assign n681 = 16'h8000 >> { n116, n74, n142, n98 }; + assign n682 = 64'h82d76177aaffe9ff >> { n291, i_12_, n147, i_15_, i_13_, i_14_ }; + assign n683 = 64'h7373737373737773 >> { n685, n569, n686, i_8_, n130, n684 }; + assign n684 = 4'h8 >> { n67, n76 }; + assign n685 = 4'h8 >> { n125, n362 }; + assign n686 = 32'd2113929087 >> { i_15_, i_13_, i_12_, i_14_, n207 }; + assign n687 = 32'd253697823 >> { n685, n174, n130, n167, n260 }; + assign n121 = 32'd32768 >> { n122, n126, n129, n132, n136 }; + assign n688 = 64'h0808080808080888 >> { n627, n220, n160, n123, n692, n1271 }; + assign n689 = 4'h8 >> { n76, n98 }; + assign n690 = 4'h8 >> { n84, n76 }; + assign n691 = 4'h8 >> { n83, n362 }; + assign n692 = 16'h7707 >> { n693, n123, n174, n628 }; + assign n693 = 16'h0777 >> { n76, n80, n66, n118 }; + assign n694 = 64'h0000000000000002 >> { n695, n697, n254, n293, n698, n696 }; + assign n695 = 4'h8 >> { n141, n267 }; + assign n696 = 16'h777f >> { n198, n268, n74, n71 }; + assign n697 = 8'ha8 >> { n144, n305, n267 }; + assign n122 = 32'd2863311522 >> { n97, n113, n111, n124, n123 }; + assign n698 = 16'h8000 >> { n74, n118, n71, n142 }; + assign n699 = 4'h8 >> { n76, n181 }; + assign o_11_ = 64'hffff3bbb3bbb3bbb >> { n292, n179, n708, n701, n710, n62 }; + assign n701 = 16'h0080 >> { n291, n704, n707, n702 }; + assign n702 = 8'h01 >> { n569, n685, n703 }; + assign n703 = 4'h8 >> { n114, n201 }; + assign n704 = 8'h08 >> { n689, n566, n705 }; + assign n705 = 32'd5723991 >> { n201, n125, n142, n76, n67 }; + assign n706 = 4'h8 >> { n142, n98 }; + assign n707 = 16'h0777 >> { n67, n161, n66, n125 }; + assign n123 = 4'h8 >> { n63, n74 }; + assign n708 = 4'h8 >> { n436, n709 }; + assign n709 = 32'd9857535 >> { n67, n125, i_13_, i_12_, i_14_ }; + assign n710 = 64'h0009ffffffffffff >> { n207, n62, i_15_, i_14_, i_12_, i_13_ }; + assign o_15_ = 8'h46 >> { i_1_, i_2_, i_0_ }; + assign n712 = 8'h80 >> { n96, n103, n120 }; + assign n713 = 64'h0000000000000008 >> { n237, n251, n706, n634, n707, n705 }; + assign n714 = 4'h1 >> { n303, n433 }; + assign n715 = 4'h1 >> { n716, n717 }; + assign n716 = 4'h8 >> { n93, n201 }; + assign n717 = 4'h8 >> { n112, n201 }; + assign n124 = 16'h0777 >> { n76, n125, n66, n84 }; + assign n718 = 4'h8 >> { n76, n101 }; + assign n719 = 4'h1 >> { n412, n97 }; + assign n720 = 4'h8 >> { n76, n88 }; + assign n721 = 16'h0777 >> { n82, n76, n112, n362 }; + assign n722 = 16'h0002 >> { n135, n420, n723, n724 }; + assign n723 = 4'h8 >> { n84, n142 }; + assign n724 = 16'h0777 >> { n142, n82, n112, n76 }; + assign n725 = 64'h0000000000000002 >> { n726, n727, n728, n312, n468, n729 }; + assign n726 = 64'h8888880888808800 >> { i_12_, i_15_, i_14_, i_13_, n207, n159 }; + assign n727 = 16'haa2a >> { n442, n146, n624, n159 }; + assign n125 = 16'h0002 >> { i_10_, i_9_, i_15_, i_11_ }; + assign n728 = 4'h2 >> { n672, n159 }; + assign n729 = 64'h5555555555555557 >> { n395, n451, n723, n246, n135, n159 }; + assign n730 = 64'h0004000544445555 >> { n138, n151, n333, n441, n376, n731 }; + assign n731 = 8'h80 >> { n96, n291, n120 }; + assign n732 = 4'h1 >> { n675, n699 }; + assign n733 = 32'd4152358911 >> { i_13_, i_15_, i_12_, n233, i_14_ }; + assign n734 = 8'h15 >> { n209, n159, n424 }; + assign n735 = 16'h2aaa >> { n738, n736, n737, n151 }; + assign n736 = 16'h0777 >> { n84, n76, n66, n93 }; + assign n737 = 16'h0777 >> { n161, n84, n93, n362 }; + assign n126 = 64'h0202020202020222 >> { n81, n65, n110, n94, n127, n128 }; + assign n738 = 32'd2113929085 >> { i_15_, i_13_, i_12_, i_14_, n291 }; + assign n739 = 16'h0002 >> { n740, n364, n365, n550 }; + assign n740 = 4'h8 >> { n147, n200 }; + assign n741 = 64'h2202020202020202 >> { n653, n334, n387, n138, n742, n743 }; + assign n742 = 8'h80 >> { n96, n233, n70 }; + assign n743 = 32'd2139062271 >> { n153, n200, n96, n71, n112 }; + assign n744 = 32'd2147614719 >> { n207, i_15_, i_13_, i_12_, i_14_ }; + assign n745 = 8'h80 >> { n96, n577, n120 }; + assign n746 = 64'h0044055504440555 >> { n161, n138, n149, n748, n749, n747 }; + assign n747 = 32'd2863311402 >> { n160, n627, n191, n693, n159 }; + assign n127 = 16'h8000 >> { n96, n93, n76, n106 }; + assign n748 = 4'h8 >> { n96, n70 }; + assign n749 = 32'd3723844983 >> { i_15_, i_12_, i_13_, i_14_, n149 }; + assign n750 = 64'h80022222aaaaaaaa >> { n292, i_12_, i_15_, i_13_, i_14_, n594 }; + assign o_23_ = 4'h7 >> { n752, n806 }; + assign n752 = 64'h8000000000000000 >> { n1283, n1288, n1293, n1295, n1297, n804 }; + assign n753 = 32'd1162167759 >> { n100, n403, n130, n191, n295 }; + assign n754 = 64'h00f700f700f700ff >> { i_12_, i_13_, n640, i_14_, n114, n123 }; + assign n755 = 64'h00aa08aa02aa0aaa >> { n379, n197, n130, n639, i_8_, n129 }; + assign n756 = 64'h01ff00ff01ff01ff >> { i_8_, n531, n130, n440, n370, n416 }; + assign n757 = 16'h8000 >> { n63, n74, n91, n153 }; + assign n65 = 4'h8 >> { n66, n67 }; + assign n128 = 64'h77777fff7fff7fff >> { n84, n70, n63, n82, n74, n66 }; + assign n758 = 64'hff01ff0fff11ff1f >> { n114, i_12_, i_14_, i_13_, n112, n216 }; + assign n759 = 64'h0155005503570257 >> { n569, n761, n130, n699, n261, n174 }; + assign n760 = 32'd2324335114 >> { n216, n114, n761, n201, n227 }; + assign n761 = 16'h0001 >> { n261, n180, n675, n699 }; + assign n762 = 32'd2863311528 >> { n365, n716, n740, n364, n73 }; + assign n763 = 4'h2 >> { n764, n164 }; + assign n764 = 32'd2113929087 >> { i_15_, i_13_, i_12_, i_14_, n149 }; + assign n765 = 32'd1 >> { n368, n363, n677, n634, n292 }; + assign n766 = 64'h002000222020ffff >> { n164, n73, n689, n736, n289, n566 }; + assign n767 = 16'h8000 >> { n74, n84, n76, n120 }; + assign n129 = 32'd254746431 >> { n131, n113, n130, n117, i_8_ }; + assign n768 = 32'd353703231 >> { n153, n142, n76, n216, n181 }; + assign n769 = 64'h0000153715371537 >> { n343, n73, n361, n174, n166, n164 }; + assign n770 = 4'h8 >> { n73, n428 }; + assign n771 = 16'haaa2 >> { n644, n628, n626, n73 }; + assign n772 = 32'd2863311402 >> { n409, n370, n148, n773, n164 }; + assign n773 = 32'd4160747391 >> { i_12_, i_13_, i_15_, n149, i_14_ }; + assign n774 = 16'h8000 >> { n74, n200, n120, n118 }; + assign n775 = 16'h8000 >> { n74, n120, n118, n201 }; + assign n776 = 16'h0777 >> { n91, n362, n66, n80 }; + assign n777 = 64'h0000000000008000 >> { n778, n779, n781, n784, n785, n786 }; + assign n130 = 4'h8 >> { n116, n74 }; + assign n778 = 64'h0880800080808080 >> { i_12_, i_15_, i_13_, i_14_, n73, n147 }; + assign n779 = 32'd2863311522 >> { n684, n248, n260, n780, n73 }; + assign n780 = 32'd5723991 >> { n142, n181, n88, n216, n76 }; + assign n781 = 32'd285278465 >> { n328, n782, n73, n296, n783 }; + assign n782 = 32'd4250795869 >> { i_15_, i_13_, i_12_, i_14_, n207 }; + assign n783 = 16'h8000 >> { n74, n76, n120, n88 }; + assign n784 = 64'h0f1f0f1f0f1f2f3f >> { n260, n167, n246, n227, n685, i_8_ }; + assign n785 = 64'h005f777f575f777f >> { n164, n67, n76, n161, n82, n73 }; + assign n786 = 64'h80008080ff00ffff >> { n73, n164, n788, n764, n787, n789 }; + assign n787 = 32'd4152358911 >> { i_13_, i_15_, i_12_, n207, i_14_ }; + assign n131 = 4'h8 >> { n76, n91 }; + assign n788 = 32'd2113929087 >> { i_15_, i_13_, i_12_, i_14_, n233 }; + assign n789 = 32'd5723991 >> { n362, n181, n161, n153, n216 }; + assign n790 = 64'h3737373737373777 >> { n87, n365, n225, i_8_, n227, n706 }; + assign n791 = 64'h515151f351f351f3 >> { n142, n67, n677, n724, n227, n73 }; + assign n792 = 32'd4152358911 >> { i_13_, i_15_, i_12_, n147, i_14_ }; + assign n793 = 64'h0f2f0f2f8faf0f2f >> { n208, n794, n195, n227, i_8_, n653 }; + assign n794 = 32'd5723991 >> { n76, n125, n153, n142, n67 }; + assign n795 = 64'h3b333b337f773b33 >> { n363, n796, n480, n141, n227, i_8_ }; + assign n796 = 32'd2438594559 >> { n291, i_13_, i_15_, i_14_, i_12_ }; + assign n797 = 32'd2610924191 >> { i_13_, n67, n125, i_12_, i_14_ }; + assign n132 = 64'h0000077707770777 >> { n134, n131, n135, n133, n62, n87 }; + assign n798 = 32'd2863311402 >> { n456, n371, n334, n672, n227 }; + assign n799 = 64'hf77f77777777f77f >> { i_15_, i_13_, i_12_, i_14_, n73, n149 }; + assign n800 = 32'd788926214 >> { i_8_, i_12_, i_14_, i_13_, i_15_ }; + assign n801 = 16'h5777 >> { n91, n229, n644, n537 }; + assign n802 = 8'h2a >> { n200, n207, n328 }; + assign n803 = 32'd926365631 >> { n97, n412, n368, n227, i_8_ }; + assign n804 = 16'h2aaa >> { i_5_, n805, n95, n670 }; + assign n805 = 8'h80 >> { n568, i_4_, i_3_ }; + assign n806 = 64'h0800080008000808 >> { n364, n365, n808, n621, n807, n688 }; + assign n807 = 64'h0008000000080008 >> { n268, n808, n812, n632, n625, n629 }; + assign n133 = 4'h8 >> { n64, n92 }; + assign n808 = 32'd33686186 >> { n85, n71, n811, n572, n809 }; + assign n809 = 16'h1115 >> { n85, n71, n576, n810 }; + assign n810 = 32'd128 >> { i_4_, i_3_, n85, i_5_, n568 }; + assign n811 = 16'h0080 >> { i_3_, i_4_, i_5_, n568 }; + assign n812 = 4'h8 >> { n174, n720 }; + assign o_24_ = 32'd1145369668 >> { n814, n811, n71, n675, n575 }; + assign n814 = 4'h8 >> { n592, n593 }; + assign o_25_ = 64'h7fffffffffffffff >> { n1300, n1283, n1288, n1293, n1295, n1297 }; + assign n816 = 4'h8 >> { n174, n685 }; + assign n817 = 64'h0202020222020202 >> { n720, n633, n205, n174, n818, n356 }; + assign n134 = 4'h8 >> { n64, n85 }; + assign n818 = 64'h0800080008080800 >> { i_13_, i_15_, i_12_, i_14_, n123, n233 }; + assign n819 = 32'd1162149957 >> { n680, n123, n174, n682, n681 }; + assign n820 = 32'd707395626 >> { n823, n221, n220, n822, n821 }; + assign n821 = 16'h5557 >> { n269, n225, n457, n221 }; + assign n822 = 4'h8 >> { n74, n178 }; + assign n823 = 16'h0777 >> { n93, n76, n66, n84 }; + assign n824 = 64'h0040404000555555 >> { n290, n289, n822, n480, n310, n301 }; + assign n825 = 64'h8888800080008000 >> { i_13_, i_12_, i_15_, i_14_, n221, n233 }; + assign o_28_ = 64'h7f7f7f7f7fff7f7f >> { i_9_, i_10_, n578, n827, n832, n835 }; + assign n827 = 64'h8088808000880080 >> { n829, n592, n368, n831, n830, n828 }; + assign n135 = 4'h8 >> { n93, n76 }; + assign n828 = 16'h0ddd >> { n178, n598, n829, n141 }; + assign n829 = 16'h1115 >> { n811, n576, n71, n571 }; + assign n830 = 16'h0ddd >> { n95, n598, n829, n363 }; + assign n831 = 16'h7707 >> { i_8_, n579, n576, n85 }; + assign n832 = 64'h0044004055555050 >> { n573, n834, n368, i_7_, n592, n833 }; + assign n833 = 8'h02 >> { n95, i_5_, n805 }; + assign n834 = 8'hfd >> { i_4_, i_3_, o_14_ }; + assign n835 = 32'd1431639381 >> { i_5_, n805, n574, n106, n836 }; + assign n836 = 64'h0000000000008000 >> { i_4_, i_5_, n568, n574, n106, i_3_ }; + assign n837 = 32'd134776840 >> { n573, n839, n195, n838, n840 }; + assign n136 = 32'd356455701 >> { n104, n138, n111, n137, n100 }; + assign n838 = 32'd3149597627 >> { i_5_, n598, n116, n197, n839 }; + assign n839 = 4'h8 >> { n829, n831 }; + assign n840 = 16'h0ddd >> { n78, n598, n839, n361 }; + assign o_32_ = 64'h8000a02008002020 >> { i_6_, i_5_, i_4_, i_7_, i_3_, n568 }; + assign o_33_ = 8'h7f >> { n840, n843, n830 }; + assign n843 = 64'h08080008aaaa00aa >> { n363, n808, n364, n573, n831, n844 }; + assign n844 = 64'h1537153715370000 >> { i_6_, n834, n571, n361, n573, n574 }; + assign o_36_ = 64'h2aaaaaaaaaaaaaaa >> { n846, n688, n848, n619, n752, n1262 }; + assign n846 = 8'h08 >> { n598, n847, n590 }; + assign n847 = 16'h0ddd >> { n116, n572, n814, n571 }; + assign n137 = 4'h8 >> { n74, n85 }; + assign n848 = 64'hf700f500ff00fd00 >> { i_6_, n814, n849, i_8_, i_7_, n811 }; + assign n849 = 64'h0d0d0d0f0d0f0d0f >> { n574, n106, n71, n812, i_5_, n805 }; + assign o_0_ = 32'd715827882 >> { n575, n834, n851, n852, n1262 }; + assign n851 = 32'd926381879 >> { n574, n814, n71, n576, n78 }; + assign n852 = 64'h77f777f777ff77f7 >> { n574, n814, i_7_, i_8_, n576, i_6_ }; + assign o_1_ = 8'h2a >> { n854, n846, n1262 }; + assign n854 = 16'hdddf >> { i_8_, n574, i_7_, n572 }; + assign o_2_ = 8'h2a >> { n856, n852, n1262 }; + assign n856 = 64'hfcfefdfffdfffdff >> { n92, n568, o_14_, i_4_, i_3_, i_5_ }; + assign o_3_ = 64'h2aaaaaaaaaaaaaaa >> { n1313, n1225, n892, n858, n866, n1262 }; + assign n66 = 8'h08 >> { i_13_, i_12_, i_14_ }; + assign n138 = 4'h8 >> { n96, n71 }; + assign n858 = 64'h0080008080800080 >> { n130, n279, n451, n1308, n863, n847 }; + assign n859 = 64'h0103010301035557 >> { n443, n441, n123, o_12_, n62, n458 }; + assign n860 = 32'd134744200 >> { n204, n432, n89, n861, n862 }; + assign n861 = 32'd353703231 >> { n251, n117, n94, n198, n434 }; + assign n862 = 64'h0777077707770fff >> { i_8_, n574, i_5_, n598, n178, n572 }; + assign n863 = 32'd33694210 >> { n274, n104, n289, n865, n864 }; + assign n864 = 64'h1111111111111151 >> { n435, n198, n430, n438, o_12_, n540 }; + assign n865 = 32'd3974932716 >> { n179, n279, n443, n614, n130 }; + assign n866 = 64'h8000000000000000 >> { n1310, n869, n872, n611, n874, n877 }; + assign n867 = 32'd5723991 >> { n133, n135, n87, n237, n62 }; + assign n139 = 64'h888a888a888a080a >> { i_8_, n148, n123, o_12_, n146, n140 }; + assign n868 = 8'h15 >> { n77, n110, n127 }; + assign n869 = 32'd33694210 >> { n62, n108, n97, n61, n870 }; + assign n870 = 16'h1151 >> { n138, n104, n100, n871 }; + assign n871 = 32'd3974950056 >> { n77, n89, n113, n87, n94 }; + assign n872 = 32'd572662434 >> { n221, n77, n104, n81, n873 }; + assign n873 = 64'h535253525352dfde >> { n169, n94, n129, n434, n79, n131 }; + assign n874 = 64'h080a080a888a080a >> { n237, n214, n73, n434, n308, n875 }; + assign n875 = 64'h00000ddd0ddd0ddd >> { n133, n117, n73, n81, n876, n89 }; + assign n876 = 4'h1 >> { n110, n79 }; + assign n877 = 4'h1 >> { n72, n122 }; + assign n140 = 32'd320017239 >> { n134, n94, n141, n144, n143 }; + assign n878 = 64'h0080808000888888 >> { n94, n62, n303, n277, n879, n880 }; + assign n879 = 32'd353703231 >> { n349, n345, n94, n204, n73 }; + assign n880 = 64'h0002002202020222 >> { n340, n221, n159, n225, n881, n356 }; + assign n881 = 16'h0080 >> { i_13_, n74, n269, n78 }; + assign n882 = 32'd286331217 >> { n225, n349, n337, n434, n344 }; + assign n883 = 32'd33686050 >> { n221, n434, n268, n338, n884 }; + assign n884 = 64'h22220002ffff000f >> { n94, n354, n77, n62, n197, n276 }; + assign n885 = 64'h0001010100ffffff >> { n73, n164, n154, n144, n248, n343 }; + assign n886 = 32'd320034579 >> { n305, n276, n133, n77, n340 }; + assign n887 = 16'h1151 >> { n204, n889, n434, n888 }; + assign n141 = 4'h8 >> { n83, n142 }; + assign n888 = 32'd2863311528 >> { n94, o_12_, n133, n250, n305 }; + assign n889 = 4'h2 >> { n198, n300 }; + assign n890 = 16'haa2a >> { n227, n500, n595, n197 }; + assign n891 = 64'h0001010100555555 >> { n133, n164, n343, n268, n198, n640 }; + assign n892 = 64'h8000000000000000 >> { n1461, n1237, n306, n1400, n478, n893 }; + assign n893 = 64'h0002000200000002 >> { n152, n159, n897, n894, n896, n898 }; + assign n894 = 64'hf0e0f0e0f0e0e0e0 >> { n81, n97, n227, i_8_, n895, n553 }; + assign n895 = 32'd2155905024 >> { n153, n200, n95, n125, n69 }; + assign n896 = 32'd2863311528 >> { n251, n261, n289, n248, n133 }; + assign n897 = 32'd3974950056 >> { n220, n218, n159, n165, n289 }; + assign n142 = 8'h02 >> { i_13_, i_12_, i_14_ }; + assign n898 = 64'h0000077707770777 >> { n457, n133, n261, n164, n174, n458 }; + assign n899 = 32'd2147483648 >> { n1310, n869, n872, n874, n877 }; + assign n900 = 64'h0202020222020202 >> { n333, n905, n722, o_12_, n904, n901 }; + assign n901 = 32'd67372117 >> { n718, n689, n123, n279, n902 }; + assign n902 = 64'hdddddddddddddd0d >> { n634, n639, n212, n903, n130, n279 }; + assign n903 = 16'h5557 >> { n112, n93, n91, n201 }; + assign n904 = 64'haaaaaaaaaaaaaaa2 >> { n137, n123, n227, n134, n546, n674 }; + assign n905 = 16'h0002 >> { n117, n416, n652, n906 }; + assign n906 = 4'h1 >> { n113, n647 }; + assign n907 = 32'd2324299914 >> { n909, n259, n133, n715, n908 }; + assign n143 = 4'h8 >> { n69, n70 }; + assign n908 = 32'd178916283 >> { o_12_, n77, n647, n62, n413 }; + assign n909 = 16'h0777 >> { n142, n181, n216, n201 }; + assign n910 = 16'h5557 >> { n101, n181, n67, n142 }; + assign n911 = 32'd5723991 >> { n333, n174, n117, n135, n94 }; + assign n912 = 64'h00770777007f0f7f >> { o_13_, n133, n652, n151, n639, i_8_ }; + assign n913 = 64'h0888088808888888 >> { n198, n154, n71, n74, n914, n916 }; + assign n914 = 64'h0001010100555555 >> { n267, n250, n79, n305, n144, n915 }; + assign n915 = 32'd2155905024 >> { n101, n67, n66, n175, n69 }; + assign n916 = 8'h57 >> { n79, n81, n222 }; + assign n917 = 8'h08 >> { n130, n238, n279 }; + assign n144 = 4'h8 >> { n91, n142 }; + assign n918 = 32'd33686050 >> { n648, n723, n538, n919, n920 }; + assign n919 = 64'h5554545454545454 >> { i_13_, i_12_, n98, n251, n113, n500 }; + assign n920 = 32'd1426421511 >> { n169, n733, n133, n164, n703 }; + assign n921 = 32'd2324335311 >> { n403, n418, n392, n501, n68 }; + assign n922 = 64'h2020002022aa00aa >> { n73, n923, n434, n787, n690, n924 }; + assign n923 = 8'h01 >> { n117, n409, n652 }; + assign n924 = 64'h0111010100110001 >> { n925, n279, n123, n720, n659, n926 }; + assign n925 = 8'h57 >> { n84, n80, n76 }; + assign n926 = 32'd2155905024 >> { n80, n84, n71, n153, n69 }; + assign n927 = 64'h8000000000000000 >> { n928, n934, n1319, n1433, n306, n1400 }; + assign o_12_ = 4'h8 >> { n95, n69 }; + assign n928 = 64'h0202020202022202 >> { n130, n179, n279, n408, n933, n929 }; + assign n929 = 64'h8888808000880080 >> { n453, n288, n637, n909, n930, n932 }; + assign n930 = 32'd1465319511 >> { n931, n290, n717, n634, n164 }; + assign n931 = 16'h0777 >> { n125, n201, n67, n142 }; + assign n932 = 32'd1970602101 >> { n493, n666, n909, n650, n159 }; + assign n933 = 32'd2863311522 >> { n73, n134, n123, n279, n699 }; + assign n934 = 32'd1947231232 >> { n939, n940, n935, n662, n123 }; + assign n935 = 64'h0001000101010001 >> { n718, n903, n434, n936, n937, n938 }; + assign n936 = 8'h8a >> { n792, n716, n250 }; + assign n937 = 64'h5555555555551555 >> { n251, n194, n925, n280, n308, n279 }; + assign n146 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n147 }; + assign n938 = 64'h8000800000888808 >> { i_10_, i_9_, i_11_, i_15_, n130, n201 }; + assign n939 = 64'hff0f110111011101 >> { n923, n792, n238, n720, n77, n227 }; + assign n940 = 8'h02 >> { n315, n648, n669 }; + assign n941 = 8'h5d >> { n176, n724, n227 }; + assign n942 = 16'h0777 >> { n82, n142, n112, n201 }; + assign n943 = 32'd1381653 >> { n165, n652, n650, n177, n775 }; + assign n944 = 32'd35786671 >> { n650, n130, n706, n134, n279 }; + assign n945 = 64'h00011111000fffff >> { n138, n723, n130, n133, n647, n703 }; + assign n946 = 8'h2a >> { n501, n238, n703 }; + assign n947 = 64'h0000800080008000 >> { i_12_, i_13_, n175, n74, n67, i_14_ }; + assign n147 = 8'h08 >> { i_11_, i_9_, i_10_ }; + assign n948 = 32'd4152358911 >> { i_13_, i_15_, i_12_, n103, i_14_ }; + assign n949 = 16'h8000 >> { n69, n76, n120, n80 }; + assign n950 = 32'd4152358911 >> { i_13_, i_15_, i_12_, n291, i_14_ }; + assign n951 = 64'h8888800080008000 >> { n64, n92, n96, n106, n76, n82 }; + assign n952 = 64'h0202020202022202 >> { n634, n637, n953, n165, n954, n955 }; + assign n953 = 8'h01 >> { n690, n720, n689 }; + assign n954 = 16'haaa2 >> { n119, n179, n488, n699 }; + assign n955 = 64'h4044c0cc5055d0dd >> { n957, n290, n165, n733, n956, n674 }; + assign n956 = 16'h0777 >> { n175, n74, n69, n106 }; + assign n957 = 16'h8000 >> { n74, n175, n76, n80 }; + assign n67 = 16'h0008 >> { i_10_, i_9_, i_11_, i_15_ }; + assign n148 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n149 }; + assign o_7_ = 8'h2a >> { n959, n851, n1262 }; + assign n959 = 64'hfefefefffefffeff >> { n106, n568, o_14_, i_4_, i_5_, i_3_ }; + assign n960 = 16'h0080 >> { n382, n605, n606, n582 }; + assign n961 = 64'h0004040400555555 >> { n647, n198, n119, n130, n595, n962 }; + assign n962 = 64'h00ff00fe00fe00fe >> { n362, n82, n501, n637, n390, n717 }; + assign n963 = 64'h3131313131313175 >> { n94, n73, n123, n964, n627, n89 }; + assign n964 = 32'd4292870103 >> { i_13_, i_14_, i_12_, i_15_, n149 }; + assign n965 = 8'h57 >> { n125, n83, n362 }; + assign n966 = 4'h8 >> { n94, n569 }; + assign n967 = 64'h8000808088008888 >> { n89, n434, n964, n624, n972, n968 }; + assign n149 = 8'h80 >> { i_10_, i_9_, i_11_ }; + assign n968 = 32'd33694210 >> { n703, n971, n174, n969, n970 }; + assign n969 = 16'haaa8 >> { n62, n123, o_12_, n378 }; + assign n970 = 16'hdd0d >> { n903, n538, n910, n130 }; + assign n971 = 16'h0777 >> { n88, n362, n114, n200 }; + assign n972 = 64'h0002020200aaaaaa >> { n123, o_12_, n368, n361, n657, n973 }; + assign n973 = 32'd1381653 >> { n204, o_12_, n248, n133, n286 }; + assign n974 = 64'h0105010501051115 >> { n361, n363, n159, n62, n305, n975 }; + assign n975 = 32'd3974950056 >> { n716, n627, n151, o_13_, n639 }; + assign n976 = 32'd2863311402 >> { n259, n227, n279, n242, n652 }; + assign n977 = 64'h8000000000000000 >> { n978, n1332, n987, n929, n988, n1335 }; + assign n150 = 32'd1566376029 >> { n155, n89, n154, n152, n151 }; + assign n978 = 64'h0000000000000008 >> { n632, n979, n665, n728, n981, n603 }; + assign n979 = 8'h08 >> { n980, n130, i_8_ }; + assign n980 = 8'h01 >> { n345, n374, n637 }; + assign n981 = 64'h0001000101010001 >> { n677, n909, n133, n816, n982, n983 }; + assign n982 = 4'h8 >> { n164, n144 }; + assign n983 = 4'h8 >> { n174, n691 }; + assign n984 = 64'h8888ffff0008000f >> { n672, n169, n174, n133, n980, n633 }; + assign n985 = 16'haaa2 >> { n119, n179, n488, n675 }; + assign n986 = 32'd2829625504 >> { n201, n200, n472, n216, n174 }; + assign n987 = 8'ha2 >> { n515, n509, n512 }; + assign n151 = 4'h8 >> { n95, n96 }; + assign n988 = 64'h080a080a080a888a >> { n141, n144, n164, n250, n965, n989 }; + assign n989 = 64'h0001010100ff11ff >> { n628, n169, n657, n119, n177, n174 }; + assign n990 = 64'h0111011101110fff >> { n174, n133, n164, n195, n716, n627 }; + assign n991 = 64'h0000000000008000 >> { n1003, n1006, n995, n999, n1433, n992 }; + assign n992 = 64'h0101010101011101 >> { n123, n179, n279, n472, n994, n993 }; + assign n993 = 64'hcdcdcdcdcdcdcd45 >> { n434, n130, n73, n889, n677, n279 }; + assign n994 = 64'heeeeeeeeeeeeee0e >> { n73, n134, n123, n279, n675, n628 }; + assign n995 = 32'd538976800 >> { n569, n965, n238, n998, n996 }; + assign n996 = 16'h4454 >> { n634, n244, n546, n997 }; + assign n997 = 8'ha8 >> { n538, n164, n657 }; + assign n152 = 8'h57 >> { n142, n153, n125 }; + assign n998 = 16'hb3a2 >> { n657, n123, n501, n569 }; + assign n999 = 64'h0101000100010001 >> { n624, n964, n169, n1000, n1001, n1002 }; + assign n1000 = 32'd2863311522 >> { n374, n232, n363, n971, n89 }; + assign n1001 = 64'h0080800080808000 >> { i_9_, i_10_, i_11_, n250, n142, i_15_ }; + assign n1002 = 16'haa2a >> { n723, n565, n910, n227 }; + assign n1003 = 64'h2aaaaaaaaaaaaaaa >> { n624, n672, n1005, n1004, n633, n123 }; + assign n1004 = 16'h0002 >> { n345, n374, n637, n964 }; + assign n1005 = 32'd2846599679 >> { n125, n216, i_13_, i_12_, i_14_ }; + assign n1006 = 32'd2863311522 >> { n130, n227, n259, n279, n648 }; + assign n1007 = 32'd128 >> { n1018, n1019, n1014, n1341, n1012 }; + assign n153 = 8'h08 >> { i_12_, i_13_, i_14_ }; + assign n1008 = 64'h1113111311135557 >> { n167, n168, n159, n179, n250, n180 }; + assign n1009 = 64'h010f010f010f111f >> { n160, n162, n174, n159, n176, n171 }; + assign n1010 = 64'h00000ddd0ddd0ddd >> { n170, n169, n166, n250, n182, n133 }; + assign n1011 = 16'h8000 >> { n69, n67, n106, n161 }; + assign n1012 = 32'd2720145954 >> { n623, n1128, n733, n133, n1013 }; + assign n1013 = 4'h2 >> { n318, n734 }; + assign n1014 = 32'd33685506 >> { n788, n164, n676, n1015, n1016 }; + assign n1015 = 32'd2863311402 >> { n456, n677, n678, n724, n169 }; + assign n1016 = 32'd1465319511 >> { n1017, n250, n648, n111, n159 }; + assign n1017 = 8'h15 >> { n201, n82, n209 }; + assign n154 = 4'h8 >> { n118, n142 }; + assign n1018 = 64'h0808808888008080 >> { i_15_, i_12_, i_13_, i_14_, n149, n250 }; + assign n1019 = 64'h8008080008800800 >> { i_13_, i_12_, i_15_, i_14_, n233, n250 }; + assign n1020 = 64'h0000000080000000 >> { n1021, n1456, n1028, n1032, n1036, n1040 }; + assign n1021 = 64'h2aaaaaaaaaaaaaaa >> { n953, n1022, n215, n622, n761, n169 }; + assign n1022 = 64'h0000000000000080 >> { n166, n718, n628, n1023, n1025, n1027 }; + assign n1023 = 4'h2 >> { n631, n1024 }; + assign n1024 = 16'h0777 >> { n101, n161, n66, n91 }; + assign n1025 = 64'h0000000000000002 >> { n237, n248, n433, n706, n684, n1026 }; + assign n1026 = 64'hb9bdbdbdb9ffffff >> { n577, n207, i_14_, i_12_, i_13_, i_15_ }; + assign n1027 = 64'h0000000000000008 >> { n193, n194, n368, n192, n909, n965 }; + assign n155 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n103 }; + assign n1028 = 64'h2202020202020202 >> { n964, n148, n773, n169, n1031, n1029 }; + assign n1029 = 64'h1111111151111111 >> { n456, n724, n334, n773, n295, n1030 }; + assign n1030 = 16'haaa8 >> { n650, n131, n428, n169 }; + assign n1031 = 64'haaaaaaaaaaaaaa2a >> { n706, n433, n237, n330, n623, n295 }; + assign n1032 = 32'd572662434 >> { n569, n657, n1035, n250, n1033 }; + assign n1033 = 32'd33694210 >> { n180, n626, n537, n695, n1034 }; + assign n1034 = 64'h0ddddddddddddddd >> { n295, n67, i_13_, i_12_, n686, n159 }; + assign n1035 = 32'd1 >> { n392, n390, n170, n171, n703 }; + assign n1036 = 64'h0202020202020222 >> { n689, n289, n170, n537, n1039, n1037 }; + assign n1037 = 64'h0011111100010101 >> { n1038, n250, n79, n537, n697, n915 }; + assign n156 = 64'h8000800000008000 >> { n189, n174, n183, n186, n157, n172 }; + assign n1038 = 4'h2 >> { n220, n737 }; + assign n1039 = 16'haaa8 >> { n627, n630, n160, n250 }; + assign n1040 = 64'h0000000000008000 >> { n727, n772, n1041, n1044, n1045, n1046 }; + assign n1041 = 64'h8808080808080808 >> { n672, n385, n823, n159, n1042, n1043 }; + assign n1042 = 64'h77777fff7fff7fff >> { n200, n82, n84, n142, n96, n106 }; + assign n1043 = 64'h77777fff7fff7fff >> { n84, n153, n66, n112, n106, n96 }; + assign n1044 = 8'hab >> { n133, n159, n749 }; + assign n1045 = 8'h51 >> { n686, n174, n775 }; + assign n1046 = 32'd2139062271 >> { n153, n66, n106, n69, n80 }; + assign n1047 = 16'h4445 >> { n295, n133, n213, n401 }; + assign n157 = 64'h0202020202020222 >> { n171, n170, n167, n169, n158, n163 }; + assign n1048 = 64'hececececececa8ec >> { n194, n412, n413, n133, n159, n403 }; + assign n1049 = 64'h0001010100ffffff >> { n537, n159, n409, n415, n212, n392 }; + assign n1050 = 64'h00d5d5d5d5d5d5d5 >> { n259, i_8_, n333, n155, n334, n169 }; + assign n1051 = 64'h0008000808080008 >> { n418, n1052, n159, n1053, n1054, n1055 }; + assign n1052 = 64'h0000000000008000 >> { n706, n634, n906, n702, n704, n707 }; + assign n1053 = 64'h0808008888088080 >> { i_15_, i_12_, i_13_, i_14_, n207, n295 }; + assign n1054 = 64'h55555555555555d5 >> { n716, n442, n364, n146, n792, n537 }; + assign n1055 = 64'hf7f7ff7777f77f7f >> { i_15_, i_12_, i_13_, i_14_, n103, n133 }; + assign n1056 = 64'h22222222222222a2 >> { n650, n131, n428, n155, n295, n1057 }; + assign n1057 = 64'hf7f77f7777ff7f7f >> { i_15_, i_12_, i_13_, i_14_, n147, n250 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act b/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act new file mode 100644 index 000000000..d1b998a42 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act @@ -0,0 +1,36 @@ +clock 0.503600 0.509400 +G0 0.499400 0.497000 +G1 0.491000 0.490800 +G2 0.512600 0.511000 +G10 0.332600 0.665000 +G11 0.200200 0.265200 +G12 0.059400 0.066000 +G13 0.002600 0.003600 +G14 0.130200 0.194400 +G15 0.001200 0.000800 +G66 0.000400 0.000800 +G67 0.990600 0.009600 +G117 0.997600 0.002000 +G118 0.001600 0.002800 +G132 0.001200 0.002400 +G133 0.007000 0.009200 +G22 0.250000 0.378200 +G23 0.255600 0.380400 +n63 0.001600 0.000006 +n56 0.998200 0.000000 +n57 0.002200 0.015182 +n67 0.001200 0.000003 +n59_1 0.000800 0.015201 +n21 0.332600 0.166165 +n26 0.200200 0.002222 +n31 0.059400 0.205226 +n36 0.002600 0.077660 +n41 0.130200 0.137391 +n65 0.744000 0.000000 +n46 0.001200 0.000001 +n51 0.000400 0.000003 +n55 0.990600 0.003272 +n59 0.997600 0.128971 +n71 0.007000 0.216731 +n75 0.250000 0.056676 +n80 0.255600 0.059427 diff --git a/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif b/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif new file mode 100644 index 000000000..c588a6e0a --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif @@ -0,0 +1,90 @@ +# Benchmark "s298" written by ABC on Tue Mar 12 09:40:31 2019 +.model s298 +.inputs clock G0 G1 G2 +.outputs G117 G132 G66 G118 G133 G67 + +.latch n21 G10 re clock 0 +.latch n26 G11 re clock 0 +.latch n31 G12 re clock 0 +.latch n36 G13 re clock 0 +.latch n41 G14 re clock 0 +.latch n46 G15 re clock 0 +.latch n51 G66 re clock 0 +.latch n55 G67 re clock 0 +.latch n59 G117 re clock 0 +.latch n63 G118 re clock 0 +.latch n67 G132 re clock 0 +.latch n71 G133 re clock 0 +.latch n75 G22 re clock 0 +.latch n80 G23 re clock 0 + +.names n56 n57 G10 n63 +0-0 1 +11- 1 +.names G15 G11 G13 G22 G14 G12 n56 +01---- 1 +0-0--- 1 +0--0-- 1 +0---1- 1 +0----1 1 +-11000 1 +.names G14 G13 G12 G118 G11 n57 +01--- 1 +100-0 1 +1-11- 1 +-1-1- 1 +.names n56 n59_1 G10 n67 +0-0 1 +11- 1 +.names G14 G13 G12 G132 G11 n59_1 +100-0 1 +11-1- 1 +1-11- 1 +.names G0 G10 n21 +00 1 +.names G10 G11 G0 G12 G13 n26 +010-- 1 +1001- 1 +100-0 1 +.names G12 G0 G11 G10 n31 +0011 1 +100- 1 +10-0 1 +.names G13 G0 G11 G12 G10 n36 +00111 1 +1001- 1 +1010- 1 +10--0 1 +.names n65 G14 G0 n41 +000 1 +110 1 +.names G23 G10 G13 G11 G12 n65 +1---- 0 +-1100 0 +.names G0 n56 n46 +00 1 +.names n56 G66 G14 G13 G12 n51 +111-1 1 +11-1- 1 +1-01- 1 +.names n56 G13 G14 G11 G67 G12 n55 +1000-- 1 +10-1-0 1 +111-1- 1 +1-1-11 1 +.names n56 G13 G117 G14 G12 G11 n59 +10-0-- 1 +10--01 1 +1111-- 1 +1-111- 1 +.names n56 G14 G12 G13 G133 G11 n71 +1010-1 1 +111-1- 1 +11-11- 1 +.names G2 G22 G0 n75 +010 1 +100 1 +.names G1 G23 G0 n80 +010 1 +100 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v b/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v new file mode 100644 index 000000000..e780ec0a0 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v @@ -0,0 +1,106 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module s298(clock, G0, G1, G2, G117, G132, G66, G118, G133, G67); + input G0; + input G1; + (* init = 1'h0 *) + reg G10 = 1'h0; + (* init = 1'h0 *) + reg G11 = 1'h0; + (* init = 1'h0 *) + output G117; + reg G117 = 1'h0; + (* init = 1'h0 *) + output G118; + reg G118 = 1'h0; + (* init = 1'h0 *) + reg G12 = 1'h0; + (* init = 1'h0 *) + reg G13 = 1'h0; + (* init = 1'h0 *) + output G132; + reg G132 = 1'h0; + (* init = 1'h0 *) + output G133; + reg G133 = 1'h0; + (* init = 1'h0 *) + reg G14 = 1'h0; + (* init = 1'h0 *) + reg G15 = 1'h0; + input G2; + (* init = 1'h0 *) + reg G22 = 1'h0; + (* init = 1'h0 *) + reg G23 = 1'h0; + (* init = 1'h0 *) + output G66; + reg G66 = 1'h0; + (* init = 1'h0 *) + output G67; + reg G67 = 1'h0; + input clock; + wire n21; + wire n26; + wire n31; + wire n36; + wire n41; + wire n46; + wire n51; + wire n55; + wire n56; + wire n57; + wire n59; + wire n59_1; + wire n63; + wire n65; + wire n67; + wire n71; + wire n75; + wire n80; + always @(posedge clock) + G10 <= n21; + always @(posedge clock) + G118 <= n63; + always @(posedge clock) + G132 <= n67; + always @(posedge clock) + G133 <= n71; + always @(posedge clock) + G22 <= n75; + always @(posedge clock) + G23 <= n80; + always @(posedge clock) + G11 <= n26; + always @(posedge clock) + G12 <= n31; + always @(posedge clock) + G13 <= n36; + always @(posedge clock) + G14 <= n41; + always @(posedge clock) + G15 <= n46; + always @(posedge clock) + G66 <= n51; + always @(posedge clock) + G67 <= n55; + always @(posedge clock) + G117 <= n59; + assign n63 = 8'h8d >> { G10, n57, n56 }; + assign n56 = 64'h55555555555545d5 >> { G12, G14, G22, G13, G11, G15 }; + assign n57 = 32'd3963940422 >> { G11, G118, G12, G13, G14 }; + assign n67 = 8'h8d >> { G10, n59_1, n56 }; + assign n59_1 = 32'd2818615810 >> { G11, G132, G12, G13, G14 }; + assign n21 = 4'h1 >> { G10, G0 }; + assign n26 = 32'd100926982 >> { G13, G12, G0, G11, G10 }; + assign n31 = 16'h1222 >> { G10, G11, G0, G12 }; + assign n36 = 32'd304095778 >> { G10, G12, G11, G0, G13 }; + assign n41 = 8'h09 >> { G0, G14, n65 }; + assign n65 = 32'd1431655701 >> { G12, G11, G13, G10, G23 }; + assign n46 = 4'h1 >> { n56, G0 }; + assign n51 = 32'd2323679744 >> { G12, G13, G14, G66, n56 }; + assign n55 = 64'ha0a20002a2822202 >> { G12, G67, G11, G14, G13, n56 }; + assign n59 = 64'ha022a222a0228022 >> { G11, G12, G14, G117, G13, n56 }; + assign n71 = 64'h88a0002088800000 >> { G11, G133, G13, G12, G14, n56 }; + assign n75 = 8'h06 >> { G0, G22, G2 }; + assign n80 = 8'h06 >> { G0, G23, G1 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act b/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act new file mode 100644 index 000000000..a050b0a28 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act @@ -0,0 +1,4010 @@ +clock 0.502400 0.508600 +Pg3234 0.490800 0.491400 +Pg3233 0.502000 0.505200 +Pg3232 0.498600 0.497400 +Pg3231 0.497800 0.495000 +Pg3230 0.505800 0.497200 +Pg3229 0.491600 0.504800 +Pg3228 0.503000 0.497200 +Pg3227 0.501800 0.497400 +Pg3226 0.481000 0.499200 +Pg3225 0.502000 0.499800 +Pg3224 0.505000 0.498800 +Pg3223 0.509400 0.501200 +Pg3222 0.506800 0.498200 +Pg3221 0.508000 0.502000 +Pg3220 0.505200 0.499200 +Pg3219 0.503400 0.486400 +Pg3218 0.492800 0.508000 +Pg3217 0.496600 0.498800 +Pg3216 0.489800 0.498200 +Pg3215 0.486000 0.499200 +Pg3214 0.503000 0.511200 +Pg3213 0.490400 0.502600 +Pg3212 0.501600 0.498800 +Pg2637 0.496200 0.493000 +Pg1943 0.487000 0.497800 +Pg1249 0.475600 0.493800 +Pg563 0.493000 0.497800 +Pg51 0.490600 0.496000 +Pg16437 0.071400 0.066000 +Pg16399 0.071400 0.066000 +Pg16355 0.071400 0.066000 +Pg16297 0.071400 0.066000 +Pg8275 0.055600 0.066000 +Pg8274 0.054000 0.063600 +Pg8273 0.053400 0.067200 +Pg8272 0.054800 0.066400 +Pg8271 0.052400 0.066400 +Pg8270 0.053200 0.062800 +Pg8269 0.049400 0.062400 +Pg8268 0.054200 0.060800 +Pg8267 0.401800 0.494800 +Pg8266 0.051200 0.058800 +Pg8265 0.051800 0.060800 +Pg8264 0.050400 0.059200 +Pg8263 0.050800 0.060400 +Pg8262 0.052800 0.062000 +Pg8261 0.052800 0.063600 +Pg8260 0.053800 0.064800 +Pg8259 0.053800 0.061200 +Pg8258 0.399400 0.494400 +Pg8251 0.491600 0.227600 +Pg8249 0.513400 0.221400 +Pg8175 0.524000 0.220400 +Pg8096 0.497200 0.221800 +Pg8023 0.488600 0.220800 +Pg8021 0.490600 0.496000 +Pg7519 0.494600 0.220600 +Pg7334 0.511400 0.226400 +Pg6895 0.505600 0.217600 +Pg6442 0.495000 0.214600 +Pg6225 0.500800 0.223600 +Pg5388 0.490800 0.491400 +Pg4590 0.490000 0.219200 +Pg4450 0.497200 0.219000 +Pg4323 0.490200 0.233800 +Pg4321 0.500000 0.222800 +Pg4200 0.499600 0.224200 +Pg4090 0.503200 0.221400 +Pg4088 0.508200 0.223000 +Pg3993 0.489800 0.228600 +Ng2817 0.286400 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+n6676_1 0.000000 0.000062 +n6677 0.000800 0.131685 +n6678 0.000000 0.000000 +n6679 0.121000 0.016681 +n6680 0.491400 0.114876 +n6681_1 0.000000 0.000000 +n6682 0.000800 0.130762 +n6683 0.000000 0.000000 +n6684 1.000000 0.000000 +n6685 0.000000 0.000000 +n6686_1 1.000000 0.000200 +n6687 0.000000 0.000000 +n6688 0.131600 0.016172 +n6689 0.000000 0.000000 +n6690 0.460800 0.044258 +n6691_1 0.598400 0.000000 +n6692 0.165000 0.001649 +n6693 0.234600 0.071665 +n6694 0.969200 0.000001 +n6695 0.070600 0.000920 +n6696_1 0.368400 0.000081 +n6697 0.975400 0.000001 +n6698 1.000000 0.000000 +n6699 0.000800 0.000000 +n6216 0.998400 0.000000 +n6701_1 0.000800 0.000000 +n6702 1.000000 0.000000 +n1713 0.998400 0.000000 +n6704 0.207400 0.000000 +n6705 0.803400 0.072761 +n6706_1 0.242400 0.000000 +n944 0.242400 0.046798 +n6708 0.000000 0.000000 +n6709 0.857000 0.000000 +n6710 0.999800 0.000000 +n6711_1 0.974000 0.008879 +n7170 0.014400 0.247426 +n6713 0.224000 0.025746 +n7035 0.014000 0.000341 +n6715 0.000800 0.159122 +n6716_1 0.000000 0.000200 +Pg25442 0.756600 0.281455 +Pg5472 0.565400 0.323863 +Pg5511 0.565400 0.323863 +Pg5555 0.565400 0.323863 +Pg5595 0.000000 0.000000 +Pg5612 0.000000 0.000000 +Pg5637 0.000000 0.000000 +Pg5657 0.566800 0.323077 +Pg5686 0.566800 0.322849 +Pg5695 0.566800 0.323077 +Pg5738 0.566800 0.322849 +Pg5747 0.566800 0.323077 +Pg5796 0.566800 0.322849 +Pg6231 0.565400 0.323863 +Pg6368 0.565400 0.323863 +Pg6447 0.565400 0.323635 +Pg6485 0.566800 0.323077 +Pg6518 0.565400 0.323635 +Pg6573 0.565400 0.323863 +Pg6642 0.566800 0.322849 +Pg6677 0.566800 0.323077 +Pg6712 0.565400 0.323635 +Pg6750 0.566800 0.323077 +Pg6782 0.565400 0.323635 +Pg6837 0.565400 0.323863 +Pg6911 0.566800 0.322849 +Pg6944 0.566800 0.322849 +Pg6979 0.566800 0.323077 +Pg7014 0.565400 0.323635 +Pg7052 0.566800 0.323077 +Pg7084 0.565400 0.323635 +Pg7161 0.566800 0.322849 +Pg7194 0.566800 0.322849 +Pg7229 0.566800 0.323077 +Pg7264 0.565400 0.323635 +Pg7302 0.566800 0.323077 +Pg7357 0.566800 0.322849 +Pg7390 0.566800 0.322849 +Pg7425 0.566800 0.323077 +Pg7487 0.566800 0.322849 +Pg7909 0.565400 0.323863 +Pg7956 0.565400 0.323635 +Pg7961 0.565400 0.323863 +Pg8007 0.565400 0.323635 +Pg8012 0.565400 0.323863 +Pg8030 0.566800 0.322849 +Pg8082 0.565400 0.323635 +Pg8087 0.565400 0.323863 +Pg8106 0.566800 0.323077 +Pg8167 0.565400 0.323635 +n378 0.490600 0.243338 +n401 0.490800 0.241179 +n516 0.490600 0.243338 +n525 0.501600 0.250198 +n529 0.503000 0.250092 +n533 0.501800 0.249595 +n537 0.481000 0.240115 +n541 0.502000 0.250900 +n545 0.505000 0.251894 +n549 0.509400 0.255311 +n553 0.506800 0.252488 +n557 0.508000 0.255016 +n561 0.498600 0.248004 +n565 0.505200 0.252196 +n569 0.503400 0.244854 +n573 0.492800 0.250342 +n577 0.496600 0.247704 +n581 0.489800 0.244018 +n585 0.486000 0.242611 +n589 0.503000 0.257134 +n593 0.490400 0.246475 +n642 0.491600 0.111888 +n646 0.503000 0.111408 +n650 0.490000 0.114609 +n654 0.490000 0.107408 +n658 0.500800 0.111979 +n662 0.494800 0.106227 +n666 0.505600 0.110019 +n670 0.511400 0.115781 +n674_1 0.494600 0.109109 +n678 0.513200 0.113667 +n682 0.508000 0.113329 +n686 0.500000 0.111400 +n690 0.488600 0.107883 +n694_1 0.524000 0.115490 +n698 0.489600 0.111968 +n702 0.499400 0.112010 +n706 0.497000 0.108887 +n710 0.497200 0.110279 +n939 0.756600 0.281455 +n948 0.756600 0.281455 +n962 0.792800 0.307924 +n966 0.756600 0.281455 +n970 0.803600 0.315654 +n974 0.756600 0.281455 +n978 0.757600 0.282433 +n1627 0.487000 0.107822 +n1636 0.492200 0.109761 +n1645 0.499800 0.111400 +n1654 0.511200 0.112917 +n1663 0.476200 0.104859 +n1672 0.510600 0.116723 +n1681 0.500800 0.112279 +n1690 0.502800 0.110056 +n1694 0.497000 0.110279 +n1698 0.496800 0.110235 +n1717 0.000000 0.000000 +n1721 0.000000 0.000000 +n1725 0.000000 0.000000 +n1729 0.000000 0.000000 +n1733 0.445800 0.000089 +n1737 0.445600 0.000089 +n1741 0.026400 0.000011 +n1745 0.026400 0.000011 +n1749 0.000000 0.000000 +n1753 0.000000 0.000000 +n1757 0.000000 0.000000 +n1761 0.000000 0.000000 +n1765 0.546200 0.000546 +n1769 0.546000 0.000546 +n1773 0.357200 0.000143 +n1777 0.357200 0.000143 +n1781 0.803000 0.000161 +n1785 0.802800 0.000161 +n1789 0.889000 0.000178 +n1793 0.888800 0.000178 +n1797 0.803200 0.000161 +n1801 0.803000 0.000161 +n1805 0.803000 0.000161 +n1809 0.802800 0.000161 +n1833_1 0.999800 0.000000 +n1837 0.999600 0.000200 +n1842 0.000000 0.000000 +n1846 0.000000 0.000000 +n1851 0.000000 0.000000 +n1855 0.000000 0.000000 +n1860 0.000000 0.000000 +n1864 0.000000 0.000000 +n1869 0.000000 0.000000 +n1873 0.000000 0.000000 +n1878 0.000000 0.000000 +n1882 0.000000 0.000000 +n1887 0.000000 0.000000 +n1891 0.000000 0.000000 +n1969 0.999800 0.000000 +n1973 0.999600 0.000200 +n1982 0.000600 0.000000 +n1996 0.999000 0.000400 +n2005 0.000600 0.000000 +n2144 0.998800 0.000599 +n2153 0.071400 0.004712 +n2477 0.565600 0.323976 +n2480 0.565400 0.323863 +n2483 0.565400 0.323635 +n3127 0.508600 0.115656 +n3136 0.496800 0.109936 +n3145 0.509800 0.119136 +n3154 0.510200 0.111734 +n3163 0.499000 0.111621 +n3172 0.505400 0.108459 +n3181 0.494200 0.107581 +n3190 0.488400 0.110619 +n3194 0.494400 0.109109 +n3198 0.494200 0.109065 +n3217 0.000000 0.000000 +n3221 0.000000 0.000000 +n3225 0.000000 0.000000 +n3229 0.000000 0.000000 +n3233 0.445800 0.000089 +n3237 0.445600 0.000089 +n3241 0.026400 0.000011 +n3245 0.026400 0.000011 +n3249 0.000000 0.000000 +n3253 0.000000 0.000000 +n3257 0.000000 0.000000 +n3261 0.000000 0.000000 +n3265 0.546200 0.000546 +n3269 0.546000 0.000546 +n3273 0.357200 0.000143 +n3277 0.357200 0.000143 +n3281 0.803000 0.000161 +n3285 0.802800 0.000161 +n3289 0.889000 0.000178 +n3293 0.888800 0.000178 +n3297 0.803200 0.000161 +n3301 0.803000 0.000161 +n3305 0.803000 0.000161 +n3309 0.802800 0.000161 +n3333 0.999800 0.000000 +n3337 0.999600 0.000200 +n3342 0.000000 0.000000 +n3346 0.000000 0.000000 +n3351 0.000000 0.000000 +n3355 0.000000 0.000000 +n3360 0.000000 0.000000 +n3364 0.000000 0.000000 +n3369 0.000000 0.000000 +n3373 0.000000 0.000000 +n3378 0.000000 0.000000 +n3382 0.000000 0.000000 +n3387 0.000000 0.000000 +n3391 0.000000 0.000000 +n3469 0.999800 0.000000 +n3473 0.999600 0.000200 +n3482 0.000600 0.000000 +n3496 0.999000 0.000400 +n3505 0.000600 0.000000 +n3644 0.998800 0.000599 +n3653 0.071400 0.004712 +n3708 0.567000 0.323191 +n3711 0.566800 0.323077 +n3714 0.566800 0.322849 +n4628 0.488600 0.128697 +n4637 0.497600 0.139185 +n4646 0.483200 0.133418 +n4655 0.481600 0.133555 +n4664 0.511400 0.145340 +n4673 0.527600 0.141080 +n4682 0.498800 0.137724 +n4691 0.494000 0.139802 +n4695 0.505000 0.138728 +n4699 0.504800 0.138673 +n4718 0.000000 0.000000 +n4722 0.000000 0.000000 +n4726 0.000000 0.000000 +n4730 0.000000 0.000000 +n4734 0.445800 0.000089 +n4738 0.445600 0.000089 +n4742_1 0.026400 0.000011 +n4746 0.026400 0.000011 +n4750 0.000000 0.000000 +n4754 0.000000 0.000000 +n4758 0.000000 0.000000 +n4762 0.000000 0.000000 +n4766 0.546200 0.000546 +n4770 0.546000 0.000546 +n4774 0.357200 0.000143 +n4778 0.357200 0.000143 +n4782 0.803000 0.000161 +n4786 0.802800 0.000161 +n4790 0.889000 0.000178 +n4794 0.888800 0.000178 +n4798 0.803200 0.000161 +n4802 0.803000 0.000161 +n4806 0.803000 0.000161 +n4810 0.802800 0.000161 +n4834_1 0.999800 0.000000 +n4838_1 0.999600 0.000200 +n4843 0.000000 0.000000 +n4847 0.000000 0.000000 +n4852 0.000000 0.000000 +n4856_1 0.000000 0.000000 +n4861_1 0.000000 0.000000 +n4865 0.000000 0.000000 +n4870 0.000000 0.000000 +n4874 0.000000 0.000000 +n4879 0.000000 0.000000 +n4883 0.000000 0.000000 +n4888_1 0.000000 0.000000 +n4892 0.000000 0.000000 +n4970 0.999800 0.000000 +n4974 0.999600 0.000200 +n4983_1 0.000600 0.000000 +n4997 0.999000 0.000400 +n5006 0.000600 0.000000 +n5145_1 0.998800 0.000599 +n5154 0.071400 0.004712 +n5893_1 0.000000 0.000000 +n5896 0.000000 0.000000 +n6130 0.505200 0.146970 +n6139 0.497600 0.142015 +n6148 0.520200 0.140142 +n6157 0.512800 0.141430 +n6166 0.507000 0.137756 +n6175 0.511600 0.138848 +n6184 0.499200 0.135238 +n6193 0.501000 0.139378 +n6197 0.511400 0.140124 +n6201 0.511400 0.140124 +n6220 0.000000 0.000000 +n6224 0.000000 0.000000 +n6228 0.000000 0.000000 +n6232 0.000000 0.000000 +n6236 0.445800 0.000089 +n6240 0.445600 0.000089 +n6244_1 0.026400 0.000011 +n6248 0.026400 0.000011 +n6252 0.000000 0.000000 +n6256 0.000000 0.000000 +n6260 0.000000 0.000000 +n6264 0.000000 0.000000 +n6268 0.546200 0.000546 +n6272 0.546000 0.000546 +n6276 0.357200 0.000143 +n6280 0.357200 0.000143 +n6284 0.803000 0.000161 +n6288 0.802800 0.000161 +n6292 0.889000 0.000178 +n6296 0.888800 0.000178 +n6300 0.803200 0.000161 +n6304 0.803000 0.000161 +n6308 0.803000 0.000161 +n6312 0.802800 0.000161 +n6336_1 0.999800 0.000000 +n6340 0.999600 0.000200 +n6345_1 0.000000 0.000000 +n6349_1 0.000000 0.000000 +n6354 0.000000 0.000000 +n6358_1 0.000000 0.000000 +n6363_1 0.000000 0.000000 +n6367 0.000000 0.000000 +n6372 0.000000 0.000000 +n6376 0.000000 0.000000 +n6381 0.000000 0.000000 +n6385 0.000000 0.000000 +n6390 0.000000 0.000000 +n6394 0.000000 0.000000 +n6472 0.999800 0.000000 +n6476 0.999600 0.000200 +n6485_1 0.000600 0.000000 +n6499 0.999000 0.000400 +n6508 0.000600 0.000000 +n6647_1 0.998800 0.000599 +n6656 0.071400 0.004712 +n7229 0.490600 0.241179 +n7233 0.557400 0.493410 diff --git a/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif b/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif new file mode 100644 index 000000000..e29726108 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif @@ -0,0 +1,10494 @@ +# Benchmark "s38417" written by ABC on Tue Mar 12 09:41:41 2019 +.model s38417 +.inputs clock Pg3234 Pg3233 Pg3232 Pg3231 Pg3230 Pg3229 Pg3228 Pg3227 \ + Pg3226 Pg3225 Pg3224 Pg3223 Pg3222 Pg3221 Pg3220 Pg3219 Pg3218 Pg3217 \ + Pg3216 Pg3215 Pg3214 Pg3213 Pg3212 Pg2637 Pg1943 Pg1249 Pg563 Pg51 +.outputs Pg27380 Pg26149 Pg26135 Pg26104 Pg25489 Pg25442 Pg25435 Pg25420 \ + Pg24734 Pg16496 Pg16437 Pg16399 Pg16355 Pg16297 Pg8275 Pg8274 Pg8273 \ + Pg8272 Pg8271 Pg8270 Pg8269 Pg8268 Pg8267 Pg8266 Pg8265 Pg8264 Pg8263 \ + Pg8262 Pg8261 Pg8260 Pg8259 Pg8258 Pg8251 Pg8249 Pg8175 Pg8167 Pg8106 \ + Pg8096 Pg8087 Pg8082 Pg8030 Pg8023 Pg8021 Pg8012 Pg8007 Pg7961 Pg7956 \ + Pg7909 Pg7519 Pg7487 Pg7425 Pg7390 Pg7357 Pg7334 Pg7302 Pg7264 Pg7229 \ + Pg7194 Pg7161 Pg7084 Pg7052 Pg7014 Pg6979 Pg6944 Pg6911 Pg6895 Pg6837 \ + Pg6782 Pg6750 Pg6712 Pg6677 Pg6642 Pg6573 Pg6518 Pg6485 Pg6447 Pg6442 \ + Pg6368 Pg6313 Pg6231 Pg6225 Pg5796 Pg5747 Pg5738 Pg5695 Pg5686 Pg5657 \ + Pg5648 Pg5637 Pg5629 Pg5612 Pg5595 Pg5555 Pg5549 Pg5511 Pg5472 Pg5437 \ + Pg5388 Pg4590 Pg4450 Pg4323 Pg4321 Pg4200 Pg4090 Pg4088 Pg3993 + +.latch n271 Pg16437 re clock 0 +.latch n275 Pg16399 re clock 0 +.latch n279 Pg16355 re clock 0 +.latch n283 Pg16297 re clock 0 +.latch n287 Pg8275 re clock 0 +.latch n291 Pg8274 re clock 0 +.latch n295 Pg8273 re clock 0 +.latch n299 Pg8272 re clock 0 +.latch n303 Pg8271 re clock 0 +.latch n307 Pg8270 re clock 0 +.latch n311 Pg8269 re clock 0 +.latch n315 Pg8268 re clock 0 +.latch n319 Pg8267 re clock 0 +.latch n323 Pg8266 re clock 0 +.latch n327 Pg8265 re clock 0 +.latch n331 Pg8264 re clock 0 +.latch n335 Pg8263 re clock 0 +.latch n339_1 Pg8262 re clock 0 +.latch n343 Pg8261 re clock 0 +.latch n347 Pg8260 re clock 0 +.latch n351 Pg8259 re clock 0 +.latch n355 Pg8258 re clock 0 +.latch n359 Pg8251 re clock 0 +.latch n363 Pg8249 re clock 0 +.latch n367 Pg8175 re clock 0 +.latch n371 Pg8096 re clock 0 +.latch n375 Pg8023 re clock 0 +.latch n378 Pg8021 re clock 0 +.latch n382 Pg7519 re clock 0 +.latch n386 Pg7334 re clock 0 +.latch n390 Pg6895 re clock 0 +.latch n394 Pg6442 re clock 0 +.latch n398 Pg6225 re clock 0 +.latch n401 Pg5388 re clock 0 +.latch n405 Pg4590 re clock 0 +.latch n409 Pg4450 re clock 0 +.latch n413 Pg4323 re clock 0 +.latch n417 Pg4321 re clock 0 +.latch n421 Pg4200 re clock 0 +.latch n425 Pg4090 re clock 0 +.latch n429 Pg4088 re clock 0 +.latch n433 Pg3993 re clock 0 +.latch n437 Ng2817 re clock 0 +.latch n442 Ng2933 re clock 0 +.latch n447 Ng13457 re clock 0 +.latch n452 Ng2883 re clock 0 +.latch n457 Ng2888 re clock 0 +.latch n462 Ng2896 re clock 0 +.latch n467 Ng2892 re clock 0 +.latch n472 Ng2903 re clock 0 +.latch n477 Ng2900 re clock 0 +.latch n482 Ng2908 re clock 0 +.latch n487 Ng2912 re clock 0 +.latch n492 Ng2917 re clock 0 +.latch n497 Ng2924 re clock 0 +.latch n502 Ng2920 re clock 0 +.latch n507 Ng2984 re clock 0 +.latch n512 Ng2985 re clock 0 +.latch n516 Ng2929 re clock 0 +.latch n521 Ng2879 re clock 0 +.latch n525 Ng2934 re clock 0 +.latch n529 Ng2935 re clock 0 +.latch n533 Ng2938 re clock 0 +.latch n537 Ng2941 re clock 0 +.latch n541 Ng2944 re clock 0 +.latch n545 Ng2947 re clock 0 +.latch n549 Ng2953 re clock 0 +.latch n553 Ng2956 re clock 0 +.latch n557 Ng2959 re clock 0 +.latch n561 Ng2962 re clock 0 +.latch n565 Ng2963 re clock 0 +.latch n569 Ng2966 re clock 0 +.latch n573 Ng2969 re clock 0 +.latch n577 Ng2972 re clock 0 +.latch n581 Ng2975 re clock 0 +.latch n585 Ng2978 re clock 0 +.latch n589 Ng2981 re clock 0 +.latch n593 Ng2874 re clock 0 +.latch n598 Ng1506 re clock 0 +.latch n603 Ng1501 re clock 0 +.latch n608 Ng1496 re clock 0 +.latch n613 Ng1491 re clock 0 +.latch n618 Ng1486 re clock 0 +.latch n623 Ng1481 re clock 0 +.latch n628 Ng1476 re clock 0 +.latch n633 Ng1471 re clock 0 +.latch n638 Ng13439 re clock 0 +.latch n642 Ng813 re clock 0 +.latch n646 Ng809 re clock 0 +.latch n650 Ng805 re clock 0 +.latch n654 Ng801 re clock 0 +.latch n658 Ng797 re clock 0 +.latch n662 Ng793 re clock 0 +.latch n666 Ng789 re clock 0 +.latch n670 Ng785 re clock 0 +.latch n674_1 Ng13423 re clock 0 +.latch n678 Ng125 re clock 0 +.latch n682 Ng121 re clock 0 +.latch n686 Ng117 re clock 0 +.latch n690 Ng113 re clock 0 +.latch n694_1 Ng109 re clock 0 +.latch n698 Ng105 re clock 0 +.latch n702 Ng101 re clock 0 +.latch n706 Ng97 re clock 0 +.latch n710 Ng13407 re clock 0 +.latch n715 Ng2200 re clock 0 +.latch n720 Ng2195 re clock 0 +.latch n725 Ng2190 re clock 0 +.latch n730 Ng2185 re clock 0 +.latch n735 Ng2180 re clock 0 +.latch n740 Ng2175 re clock 0 +.latch n745 Ng2170 re clock 0 +.latch n750 Ng2165 re clock 0 +.latch n755 Ng13455 re clock 0 +.latch n760 Ng3210 re clock 0 +.latch n765 Ng3211 re clock 0 +.latch n770 Ng3084 re clock 0 +.latch n775 Ng3085 re clock 0 +.latch n780 Ng3086 re clock 0 +.latch n785 Ng3087 re clock 0 +.latch n790 Ng3091 re clock 0 +.latch n795 Ng3092 re clock 0 +.latch n800 Ng3093 re clock 0 +.latch n805 Ng3094 re clock 0 +.latch n810 Ng3095 re clock 0 +.latch n815 Ng3096 re clock 0 +.latch n820 Ng3097 re clock 0 +.latch n825 Ng3098 re clock 0 +.latch n830 Ng3099 re clock 0 +.latch n835 Ng3100 re clock 0 +.latch n840 Ng3101 re clock 0 +.latch n845 Ng3102 re clock 0 +.latch n850 Ng3103 re clock 0 +.latch n855 Ng3104 re clock 0 +.latch n860 Ng3105 re clock 0 +.latch n865 Ng3106 re clock 0 +.latch n870 Ng3107 re clock 0 +.latch n875 Ng3108 re clock 0 +.latch n880 Ng3155 re clock 0 +.latch n885 Ng3158 re clock 0 +.latch n890 Ng3161 re clock 0 +.latch n895 Ng3164 re clock 0 +.latch n900 Ng3167 re clock 0 +.latch n905 Ng3170 re clock 0 +.latch n910 Ng3173 re clock 0 +.latch n915 Ng3176 re clock 0 +.latch n920 Ng3179 re clock 0 +.latch n925 Ng3182 re clock 0 +.latch n930 Ng3185 re clock 0 +.latch n935 Ng3088 re clock 0 +.latch n939 Ng3191 re clock 0 +.latch n944 Ng3128 re clock 0 +.latch n948 Ng3126 re clock 0 +.latch n953 Ng3125 re clock 0 +.latch n958_1 Ng3123 re clock 0 +.latch n962 Ng3120 re clock 0 +.latch n966 Ng3110 re clock 0 +.latch n970 Ng3139 re clock 0 +.latch n974 Ng3135 re clock 0 +.latch n978 Ng3147 re clock 0 +.latch n983 Ng185 re clock 0 +.latch n988 Ng130 re clock 0 +.latch n993 Ng131 re clock 0 +.latch n998_1 Ng129 re clock 0 +.latch n1003_1 Ng133 re clock 0 +.latch n1008 Ng134 re clock 0 +.latch n1013 Ng132 re clock 0 +.latch n1018_1 Ng142 re clock 0 +.latch n1023 Ng143 re clock 0 +.latch n1028 Ng141 re clock 0 +.latch n1033_1 Ng145 re clock 0 +.latch n1038 Ng146 re clock 0 +.latch n1043 Ng144 re clock 0 +.latch n1048_1 Ng148 re clock 0 +.latch n1053_1 Ng149 re clock 0 +.latch n1058 Ng147 re clock 0 +.latch n1063_1 Ng151 re clock 0 +.latch n1068 Ng152 re clock 0 +.latch n1073 Ng150 re clock 0 +.latch n1078 Ng154 re clock 0 +.latch n1083 Ng155 re clock 0 +.latch n1088 Ng153 re clock 0 +.latch n1093 Ng157 re clock 0 +.latch n1098 Ng158 re clock 0 +.latch n1103 Ng156 re clock 0 +.latch n1108_1 Ng160 re clock 0 +.latch n1113 Ng161 re clock 0 +.latch n1118 Ng159 re clock 0 +.latch n1123 Ng163 re clock 0 +.latch n1128 Ng164 re clock 0 +.latch n1133 Ng162 re clock 0 +.latch n1138 Ng169 re clock 0 +.latch n1143 Ng170 re clock 0 +.latch n1148 Ng168 re clock 0 +.latch n1153 Ng172 re clock 0 +.latch n1158 Ng173 re clock 0 +.latch n1163 Ng171 re clock 0 +.latch n1168 Ng175 re clock 0 +.latch n1173 Ng176 re clock 0 +.latch n1178_1 Ng174 re clock 0 +.latch n1183 Ng178 re clock 0 +.latch n1188 Ng179 re clock 0 +.latch n1193 Ng177 re clock 0 +.latch n1198 Ng186 re clock 0 +.latch n1203 Ng189 re clock 0 +.latch n1208 Ng192 re clock 0 +.latch n1213 Ng231 re clock 0 +.latch n1218 Ng234 re clock 0 +.latch n1223 Ng237 re clock 0 +.latch n1228 Ng195 re clock 0 +.latch n1233 Ng198 re clock 0 +.latch n1238 Ng201 re clock 0 +.latch n1243 Ng240 re clock 0 +.latch n1248 Ng243 re clock 0 +.latch n1253 Ng246 re clock 0 +.latch n1258 Ng204 re clock 0 +.latch n1263 Ng207 re clock 0 +.latch n1268_1 Ng210 re clock 0 +.latch n1273 Ng249 re clock 0 +.latch n1278_1 Ng252 re clock 0 +.latch n1283 Ng255 re clock 0 +.latch n1288_1 Ng213 re clock 0 +.latch n1293 Ng216 re clock 0 +.latch n1298_1 Ng219 re clock 0 +.latch n1303_1 Ng258 re clock 0 +.latch n1308 Ng261 re clock 0 +.latch n1313_1 Ng264 re clock 0 +.latch n1318_1 Ng222 re clock 0 +.latch n1323 Ng225 re clock 0 +.latch n1328 Ng228 re clock 0 +.latch n1333 Ng267 re clock 0 +.latch n1338 Ng270 re clock 0 +.latch n1343 Ng273 re clock 0 +.latch n1348_1 Ng92 re clock 0 +.latch n1353_1 Ng88 re clock 0 +.latch n1358 Ng83 re clock 0 +.latch n1363 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Ng438 re clock 0 +.latch n1523 Ng441 re clock 0 +.latch n1528_1 Ng444 re clock 0 +.latch n1533 Ng448 re clock 0 +.latch n1538 Ng449 re clock 0 +.latch n1543 Ng447 re clock 0 +.latch n1548 Ng312 re clock 0 +.latch n1553 Ng313 re clock 0 +.latch n1558 Ng314 re clock 0 +.latch n1563 Ng315 re clock 0 +.latch n1568 Ng316 re clock 0 +.latch n1573 Ng317 re clock 0 +.latch n1578_1 Ng318 re clock 0 +.latch n1583 Ng319 re clock 0 +.latch n1588 Ng320 re clock 0 +.latch n1593 Ng322 re clock 0 +.latch n1598 Ng323 re clock 0 +.latch n1603 Ng321 re clock 0 +.latch n1608 Ng403 re clock 0 +.latch n1613_1 Ng404 re clock 0 +.latch n1618 Ng402 re clock 0 +.latch n1623 Ng450 re clock 0 +.latch n1627 Ng451 re clock 0 +.latch n1632 Ng452 re clock 0 +.latch n1636 Ng453 re clock 0 +.latch n1641 Ng454 re clock 0 +.latch n1645 Ng279 re clock 0 +.latch n1650 Ng280 re clock 0 +.latch n1654 Ng281 re clock 0 +.latch n1659 Ng282 re clock 0 +.latch n1663 Ng283 re clock 0 +.latch n1668 Ng284 re clock 0 +.latch n1672 Ng285 re clock 0 +.latch n1677 Ng286 re clock 0 +.latch n1681 Ng287 re clock 0 +.latch n1686 Ng288 re clock 0 +.latch n1690 Ng289 re clock 0 +.latch n1694 Ng290 re clock 0 +.latch n1698 Ng291 re clock 0 +.latch n1703 Ng299 re clock 0 +.latch n1708 Ng305 re clock 0 +.latch n1713 Ng298 re clock 0 +.latch n1717 Ng342 re clock 0 +.latch n1721 Ng349 re clock 0 +.latch n1725 Ng350 re clock 0 +.latch n1729 Ng351 re clock 0 +.latch n1733 Ng352 re clock 0 +.latch n1737 Ng353 re clock 0 +.latch n1741 Ng357 re clock 0 +.latch n1745 Ng364 re clock 0 +.latch n1749 Ng365 re clock 0 +.latch n1753 Ng366 re clock 0 +.latch n1757 Ng367 re clock 0 +.latch n1761 Ng368 re clock 0 +.latch n1765 Ng372 re clock 0 +.latch n1769 Ng379 re clock 0 +.latch n1773 Ng380 re clock 0 +.latch n1777 Ng381 re clock 0 +.latch n1781 Ng382 re clock 0 +.latch n1785 Ng383 re clock 0 +.latch n1789 Ng387 re clock 0 +.latch n1793 Ng394 re clock 0 +.latch n1797 Ng395 re clock 0 +.latch n1801 Ng396 re clock 0 +.latch n1805 Ng397 re clock 0 +.latch n1809 Ng324 re clock 0 +.latch n1814 Ng554 re clock 0 +.latch n1819 Ng557 re clock 0 +.latch n1824 Ng510 re clock 0 +.latch n1829_1 Ng513 re clock 0 +.latch n1833_1 Ng523 re clock 0 +.latch n1837 Ng524 re clock 0 +.latch n1842 Ng564 re clock 0 +.latch n1846 Ng569 re clock 0 +.latch n1851 Ng570 re clock 0 +.latch n1855 Ng571 re clock 0 +.latch n1860 Ng572 re clock 0 +.latch n1864 Ng573 re clock 0 +.latch n1869 Ng574 re clock 0 +.latch n1873 Ng565 re clock 0 +.latch n1878 Ng566 re clock 0 +.latch n1882 Ng567 re clock 0 +.latch n1887 Ng568 re clock 0 +.latch n1891 Ng489 re clock 0 +.latch n1896 Ng486 re clock 0 +.latch n1901 Ng487 re clock 0 +.latch n1906 Ng488 re clock 0 +.latch n1911 Ng11512 re clock 0 +.latch n1915 Ng11515 re clock 0 +.latch n1919 Ng11516 re clock 0 +.latch n1923 Ng477 re clock 0 +.latch n1928 Ng478 re clock 0 +.latch n1933 Ng479 re clock 0 +.latch n1938 Ng480 re clock 0 +.latch n1943 Ng484 re clock 0 +.latch n1948 Ng464 re clock 0 +.latch n1953 Ng11517 re clock 0 +.latch n1957 Ng11513 re clock 0 +.latch n1961 Ng11514 re clock 0 +.latch n1965_1 Ng528 re clock 0 +.latch n1969 Ng535 re clock 0 +.latch n1973 Ng542 re clock 0 +.latch n1978 Ng543 re clock 0 +.latch n1982 Ng544 re clock 0 +.latch n1987 Ng548 re clock 0 +.latch n1992 Ng549 re clock 0 +.latch n1996 Ng8284 re clock 0 +.latch n2001 Ng558 re clock 0 +.latch n2005 Ng559 re clock 0 +.latch n2010_1 Ng576 re clock 0 +.latch n2015 Ng577 re clock 0 +.latch n2020 Ng575 re clock 0 +.latch n2025 Ng579 re clock 0 +.latch n2030_1 Ng580 re clock 0 +.latch n2035 Ng578 re clock 0 +.latch n2040_1 Ng582 re clock 0 +.latch n2045 Ng583 re clock 0 +.latch n2050 Ng581 re clock 0 +.latch n2055 Ng585 re clock 0 +.latch n2060 Ng586 re clock 0 +.latch n2065 Ng584 re clock 0 +.latch n2070 Ng587 re clock 0 +.latch n2075 Ng590 re clock 0 +.latch n2080 Ng593 re clock 0 +.latch n2085 Ng596 re clock 0 +.latch n2090 Ng599 re clock 0 +.latch n2095 Ng602 re clock 0 +.latch n2100 Ng614 re clock 0 +.latch n2105 Ng617 re clock 0 +.latch n2110 Ng620 re clock 0 +.latch n2115 Ng605 re clock 0 +.latch n2120 Ng608 re clock 0 +.latch n2125 Ng611 re clock 0 +.latch n2130 Ng490 re clock 0 +.latch n2135 Ng493 re clock 0 +.latch n2140 Ng496 re clock 0 +.latch n2144 Ng506 re clock 0 +.latch n2149 Ng507 re clock 0 +.latch n2153 Ng525 re clock 0 +.latch n2158 Ng529 re clock 0 +.latch n2163 Ng530 re clock 0 +.latch n2168 Ng531 re clock 0 +.latch n2173 Ng532 re clock 0 +.latch n2178 Ng533 re clock 0 +.latch n2183 Ng534 re clock 0 +.latch n2188 Ng536 re clock 0 +.latch n2193 Ng537 re clock 0 +.latch n2198 Ng538 re clock 0 +.latch n2203 Ng541 re clock 0 +.latch n2208 Ng630 re clock 0 +.latch n2213 Ng659 re clock 0 +.latch n2218 Ng640 re clock 0 +.latch n2223 Ng633 re clock 0 +.latch n2228 Ng653 re clock 0 +.latch n2233 Ng646 re clock 0 +.latch n2238 Ng660 re clock 0 +.latch n2243 Ng672 re clock 0 +.latch n2248 Ng666 re clock 0 +.latch n2253 Ng679 re clock 0 +.latch n2258 Ng686 re clock 0 +.latch n2263 Ng692 re clock 0 +.latch n2268 Ng699 re clock 0 +.latch n2273 Ng700 re clock 0 +.latch n2278 Ng698 re clock 0 +.latch n2283 Ng702 re clock 0 +.latch n2288 Ng703 re clock 0 +.latch n2293 Ng701 re clock 0 +.latch n2298 Ng705 re clock 0 +.latch n2303 Ng706 re clock 0 +.latch n2308 Ng704 re clock 0 +.latch n2313 Ng708 re clock 0 +.latch n2318 Ng709 re clock 0 +.latch n2323 Ng707 re clock 0 +.latch n2328 Ng711 re clock 0 +.latch n2333 Ng712 re clock 0 +.latch n2338 Ng710 re clock 0 +.latch n2343 Ng714 re clock 0 +.latch n2348 Ng715 re clock 0 +.latch n2353 Ng713 re clock 0 +.latch n2358 Ng717 re clock 0 +.latch n2363 Ng718 re clock 0 +.latch n2368 Ng716 re clock 0 +.latch n2373 Ng720 re clock 0 +.latch n2378 Ng721 re clock 0 +.latch n2383 Ng719 re clock 0 +.latch n2388 Ng723 re clock 0 +.latch n2393 Ng724 re clock 0 +.latch n2398 Ng722 re clock 0 +.latch n2403 Ng726 re clock 0 +.latch n2408 Ng727 re clock 0 +.latch n2413 Ng725 re clock 0 +.latch n2418 Ng729 re clock 0 +.latch n2423 Ng730 re clock 0 +.latch n2428 Ng728 re clock 0 +.latch n2433 Ng732 re clock 0 +.latch n2438 Ng733 re clock 0 +.latch n2443 Ng731 re clock 0 +.latch n2448 Ng735 re clock 0 +.latch n2453 Ng736 re clock 0 +.latch n2458 Ng734 re clock 0 +.latch n2463 Ng738 re clock 0 +.latch n2468 Ng739 re clock 0 +.latch n2473 Ng737 re clock 0 +.latch n2477 Pg5437 re clock 0 +.latch n2480 Pg6313 re clock 0 +.latch n2483 Ng853 re clock 0 +.latch n2488 Ng818 re clock 0 +.latch n2493 Ng819 re clock 0 +.latch n2498 Ng817 re clock 0 +.latch n2503 Ng821 re clock 0 +.latch n2508 Ng822 re clock 0 +.latch n2513 Ng820 re clock 0 +.latch n2518 Ng830 re clock 0 +.latch n2523 Ng831 re clock 0 +.latch n2528 Ng829 re clock 0 +.latch n2533 Ng833 re clock 0 +.latch n2538 Ng834 re clock 0 +.latch n2543 Ng832 re clock 0 +.latch n2548 Ng836 re clock 0 +.latch n2553 Ng837 re clock 0 +.latch n2558 Ng835 re clock 0 +.latch n2563 Ng839 re clock 0 +.latch n2568 Ng840 re clock 0 +.latch n2573 Ng838 re clock 0 +.latch n2578 Ng842 re clock 0 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n2743 Ng927 re clock 0 +.latch n2748 Ng930 re clock 0 +.latch n2753 Ng933 re clock 0 +.latch n2758 Ng891 re clock 0 +.latch n2763 Ng894 re clock 0 +.latch n2768 Ng897 re clock 0 +.latch n2773 Ng936 re clock 0 +.latch n2778 Ng939 re clock 0 +.latch n2783 Ng942 re clock 0 +.latch n2788 Ng900 re clock 0 +.latch n2793 Ng903 re clock 0 +.latch n2798 Ng906 re clock 0 +.latch n2803 Ng945 re clock 0 +.latch n2808 Ng948 re clock 0 +.latch n2813 Ng951 re clock 0 +.latch n2818 Ng909 re clock 0 +.latch n2823 Ng912 re clock 0 +.latch n2828 Ng915 re clock 0 +.latch n2833 Ng954 re clock 0 +.latch n2838 Ng957 re clock 0 +.latch n2843 Ng960 re clock 0 +.latch n2848 Ng780 re clock 0 +.latch n2853 Ng776 re clock 0 +.latch n2858 Ng771 re clock 0 +.latch n2863 Ng767 re clock 0 +.latch n2868 Ng762 re clock 0 +.latch n2873 Ng758 re clock 0 +.latch n2878 Ng753 re clock 0 +.latch n2883 Ng749 re clock 0 +.latch n2888 Ng744 re clock 0 +.latch n2893 Ng740 re clock 0 +.latch n2898 Ng11524 re clock 0 +.latch n2903 Ng11525 re clock 0 +.latch n2908 Ng11526 re clock 0 +.latch n2913 Ng11527 re clock 0 +.latch n2918 Ng11528 re clock 0 +.latch n2923 Ng11529 re clock 0 +.latch n2928 Ng11530 re clock 0 +.latch n2933 Ng11531 re clock 0 +.latch n2938 Ng11532 re clock 0 +.latch n2943 Ng11533 re clock 0 +.latch n2948 Ng11534 re clock 0 +.latch n2953 Ng11535 re clock 0 +.latch n2958 Ng1095 re clock 0 +.latch n2963 Ng1098 re clock 0 +.latch n2968 Ng1101 re clock 0 +.latch n2973 Ng1104 re clock 0 +.latch n2978 Ng1107 re clock 0 +.latch n2983 Ng1110 re clock 0 +.latch n2988 Ng1114 re clock 0 +.latch n2993 Ng1115 re clock 0 +.latch n2998 Ng1113 re clock 0 +.latch n3003 Ng1116 re clock 0 +.latch n3008 Ng1119 re clock 0 +.latch n3013 Ng1122 re clock 0 +.latch n3018 Ng1125 re clock 0 +.latch n3023 Ng1128 re clock 0 +.latch n3028 Ng1131 re clock 0 +.latch n3033 Ng1135 re clock 0 +.latch n3038 Ng1136 re clock 0 +.latch n3043 Ng1134 re clock 0 +.latch n3048 Ng999 re clock 0 +.latch n3053 Ng1000 re clock 0 +.latch n3058 Ng1001 re clock 0 +.latch n3063 Ng1002 re clock 0 +.latch n3068 Ng1003 re clock 0 +.latch n3073 Ng1004 re clock 0 +.latch n3078 Ng1005 re clock 0 +.latch n3083 Ng1006 re clock 0 +.latch n3088 Ng1007 re clock 0 +.latch n3093 Ng1009 re clock 0 +.latch n3098 Ng1010 re clock 0 +.latch n3103 Ng1008 re clock 0 +.latch n3108 Ng1090 re clock 0 +.latch n3113 Ng1091 re clock 0 +.latch n3118 Ng1089 re clock 0 +.latch n3123 Ng1137 re clock 0 +.latch n3127 Ng1138 re clock 0 +.latch n3132 Ng1139 re clock 0 +.latch n3136 Ng1140 re clock 0 +.latch n3141 Ng1141 re clock 0 +.latch n3145 Ng966 re clock 0 +.latch n3150 Ng967 re clock 0 +.latch n3154 Ng968 re clock 0 +.latch n3159 Ng969 re clock 0 +.latch n3163 Ng970 re clock 0 +.latch n3168 Ng971 re clock 0 +.latch n3172 Ng972 re clock 0 +.latch n3177 Ng973 re clock 0 +.latch n3181 Ng974 re clock 0 +.latch n3186 Ng975 re clock 0 +.latch n3190 Ng976 re clock 0 +.latch n3194 Ng977 re clock 0 +.latch n3198 Ng978 re clock 0 +.latch n3203 Ng986 re clock 0 +.latch n3208 Ng992 re clock 0 +.latch n3213 Ng985 re clock 0 +.latch n3217 Ng1029 re clock 0 +.latch n3221 Ng1036 re clock 0 +.latch n3225 Ng1037 re clock 0 +.latch n3229 Ng1038 re clock 0 +.latch n3233 Ng1039 re clock 0 +.latch n3237 Ng1040 re clock 0 +.latch n3241 Ng1044 re clock 0 +.latch n3245 Ng1051 re clock 0 +.latch n3249 Ng1052 re clock 0 +.latch n3253 Ng1053 re clock 0 +.latch n3257 Ng1054 re clock 0 +.latch n3261 Ng1055 re clock 0 +.latch n3265 Ng1059 re clock 0 +.latch n3269 Ng1066 re clock 0 +.latch n3273 Ng1067 re clock 0 +.latch n3277 Ng1068 re clock 0 +.latch n3281 Ng1069 re clock 0 +.latch n3285 Ng1070 re clock 0 +.latch n3289 Ng1074 re clock 0 +.latch n3293 Ng1081 re clock 0 +.latch n3297 Ng1082 re clock 0 +.latch n3301 Ng1083 re clock 0 +.latch n3305 Ng1084 re clock 0 +.latch n3309 Ng1011 re clock 0 +.latch n3314 Ng1240 re clock 0 +.latch n3319 Ng1243 re clock 0 +.latch n3324 Ng1196 re clock 0 +.latch n3329 Ng1199 re clock 0 +.latch n3333 Ng1209 re clock 0 +.latch n3337 Ng1210 re clock 0 +.latch n3342 Ng1250 re clock 0 +.latch n3346 Ng1255 re clock 0 +.latch n3351 Ng1256 re clock 0 +.latch n3355 Ng1257 re clock 0 +.latch n3360 Ng1258 re clock 0 +.latch n3364 Ng1259 re clock 0 +.latch n3369 Ng1260 re clock 0 +.latch n3373 Ng1251 re clock 0 +.latch n3378 Ng1252 re clock 0 +.latch n3382 Ng1253 re clock 0 +.latch n3387 Ng1254 re clock 0 +.latch n3391 Ng1176 re clock 0 +.latch n3396 Ng1173 re clock 0 +.latch n3401 Ng1174 re clock 0 +.latch n3406 Ng1175 re clock 0 +.latch n3411 Ng11539 re clock 0 +.latch n3415 Ng11542 re clock 0 +.latch n3419 Ng11543 re clock 0 +.latch n3423 Ng1164 re clock 0 +.latch n3428 Ng1165 re clock 0 +.latch n3433 Ng1166 re clock 0 +.latch n3438 Ng1167 re clock 0 +.latch n3443 Ng1171 re clock 0 +.latch n3448 Ng1151 re clock 0 +.latch n3453 Ng11544 re clock 0 +.latch n3457 Ng11540 re clock 0 +.latch n3461 Ng11541 re clock 0 +.latch n3465 Ng1214 re clock 0 +.latch n3469 Ng1221 re clock 0 +.latch n3473 Ng1228 re clock 0 +.latch n3478 Ng1229 re clock 0 +.latch n3482 Ng1230 re clock 0 +.latch n3487 Ng1234 re clock 0 +.latch n3492 Ng1235 re clock 0 +.latch n3496 Ng8293 re clock 0 +.latch n3501 Ng1244 re clock 0 +.latch n3505 Ng1245 re clock 0 +.latch n3510 Ng1262 re clock 0 +.latch n3515 Ng1263 re clock 0 +.latch n3520 Ng1261 re clock 0 +.latch n3525 Ng1265 re clock 0 +.latch n3530 Ng1266 re clock 0 +.latch n3535 Ng1264 re clock 0 +.latch n3540 Ng1268 re clock 0 +.latch n3545 Ng1269 re clock 0 +.latch n3550 Ng1267 re clock 0 +.latch n3555 Ng1271 re clock 0 +.latch n3560 Ng1272 re clock 0 +.latch n3565 Ng1270 re clock 0 +.latch n3570 Ng1273 re clock 0 +.latch n3575 Ng1276 re clock 0 +.latch n3580 Ng1279 re clock 0 +.latch n3585 Ng1282 re clock 0 +.latch n3590 Ng1285 re clock 0 +.latch n3595 Ng1288 re clock 0 +.latch n3600 Ng1300 re clock 0 +.latch n3605 Ng1303 re clock 0 +.latch n3610 Ng1306 re clock 0 +.latch n3615 Ng1291 re clock 0 +.latch n3620 Ng1294 re clock 0 +.latch n3625 Ng1297 re clock 0 +.latch n3630 Ng1177 re clock 0 +.latch n3635 Ng1180 re clock 0 +.latch n3640 Ng1183 re clock 0 +.latch n3644 Ng1192 re clock 0 +.latch n3649 Ng1193 re clock 0 +.latch n3653 Ng1211 re clock 0 +.latch n3658 Ng1215 re clock 0 +.latch n3663 Ng1216 re clock 0 +.latch n3668 Ng1217 re clock 0 +.latch n3673 Ng1218 re clock 0 +.latch n3678 Ng1219 re clock 0 +.latch n3683 Ng1220 re clock 0 +.latch n3688 Ng1222 re clock 0 +.latch n3693 Ng1223 re clock 0 +.latch n3698 Ng1224 re clock 0 +.latch n3703 Ng1227 re clock 0 +.latch n3708 Pg5629 re clock 0 +.latch n3711 Pg5648 re clock 0 +.latch n3714 Ng1315 re clock 0 +.latch n3719 Ng1316 re clock 0 +.latch n3724 Ng1345 re clock 0 +.latch n3729 Ng1326 re clock 0 +.latch n3734 Ng1319 re clock 0 +.latch n3739 Ng1339 re clock 0 +.latch n3744 Ng1332 re clock 0 +.latch n3749 Ng1346 re clock 0 +.latch n3754 Ng1358 re clock 0 +.latch n3759 Ng1352 re clock 0 +.latch n3764 Ng1365 re clock 0 +.latch n3769 Ng1372 re clock 0 +.latch n3774 Ng1378 re clock 0 +.latch n3779 Ng1385 re clock 0 +.latch n3784 Ng1386 re clock 0 +.latch n3789 Ng1384 re clock 0 +.latch n3794 Ng1388 re clock 0 +.latch n3799 Ng1389 re clock 0 +.latch n3804 Ng1387 re clock 0 +.latch n3809 Ng1391 re clock 0 +.latch n3814 Ng1392 re clock 0 +.latch n3819 Ng1390 re clock 0 +.latch n3824 Ng1394 re clock 0 +.latch n3829 Ng1395 re clock 0 +.latch n3834 Ng1393 re clock 0 +.latch n3839 Ng1397 re clock 0 +.latch n3844 Ng1398 re clock 0 +.latch n3849 Ng1396 re clock 0 +.latch n3854 Ng1400 re clock 0 +.latch n3859 Ng1401 re clock 0 +.latch n3864 Ng1399 re clock 0 +.latch n3869 Ng1403 re clock 0 +.latch n3874 Ng1404 re clock 0 +.latch n3879 Ng1402 re clock 0 +.latch n3884 Ng1406 re clock 0 +.latch n3889 Ng1407 re clock 0 +.latch n3894 Ng1405 re clock 0 +.latch n3899 Ng1409 re clock 0 +.latch n3904 Ng1410 re clock 0 +.latch n3909 Ng1408 re clock 0 +.latch n3914 Ng1412 re clock 0 +.latch n3919 Ng1413 re clock 0 +.latch n3924 Ng1411 re clock 0 +.latch n3929 Ng1415 re clock 0 +.latch n3934 Ng1416 re clock 0 +.latch n3939 Ng1414 re clock 0 +.latch n3944 Ng1418 re clock 0 +.latch n3949 Ng1419 re clock 0 +.latch n3954 Ng1417 re clock 0 +.latch n3959 Ng1421 re clock 0 +.latch n3964 Ng1422 re clock 0 +.latch n3969 Ng1420 re clock 0 +.latch n3974 Ng1424 re clock 0 +.latch n3979 Ng1425 re clock 0 +.latch n3984 Ng1423 re clock 0 +.latch n3989 Ng1512 re clock 0 +.latch n3994 Ng1513 re clock 0 +.latch n3999 Ng1511 re clock 0 +.latch n4004 Ng1515 re clock 0 +.latch n4009 Ng1516 re clock 0 +.latch n4014 Ng1514 re clock 0 +.latch n4019 Ng1524 re clock 0 +.latch n4024 Ng1525 re clock 0 +.latch n4029 Ng1523 re clock 0 +.latch n4034 Ng1527 re clock 0 +.latch n4039 Ng1528 re clock 0 +.latch n4044 Ng1526 re clock 0 +.latch n4049 Ng1530 re clock 0 +.latch n4054 Ng1531 re clock 0 +.latch n4059 Ng1529 re clock 0 +.latch n4064 Ng1533 re clock 0 +.latch n4069 Ng1534 re clock 0 +.latch n4074 Ng1532 re clock 0 +.latch n4079 Ng1536 re clock 0 +.latch n4084 Ng1537 re clock 0 +.latch n4089 Ng1535 re clock 0 +.latch n4094 Ng1539 re clock 0 +.latch n4099 Ng1540 re clock 0 +.latch n4104 Ng1538 re clock 0 +.latch n4109 Ng1542 re clock 0 +.latch n4114 Ng1543 re clock 0 +.latch n4119 Ng1541 re clock 0 +.latch n4124 Ng1545 re clock 0 +.latch n4129 Ng1546 re clock 0 +.latch n4134 Ng1544 re clock 0 +.latch n4139 Ng1551 re clock 0 +.latch n4144 Ng1552 re clock 0 +.latch n4149 Ng1550 re clock 0 +.latch n4154 Ng1554 re clock 0 +.latch n4159 Ng1555 re clock 0 +.latch n4164 Ng1553 re clock 0 +.latch n4169 Ng1557 re clock 0 +.latch n4174 Ng1558 re clock 0 +.latch n4179 Ng1556 re clock 0 +.latch n4184 Ng1560 re clock 0 +.latch n4189 Ng1561 re clock 0 +.latch n4194 Ng1559 re clock 0 +.latch n4199 Ng1567 re clock 0 +.latch n4204 Ng1570 re clock 0 +.latch n4209 Ng1573 re clock 0 +.latch n4214 Ng1612 re clock 0 +.latch n4219 Ng1615 re clock 0 +.latch n4224 Ng1618 re clock 0 +.latch n4229 Ng1576 re clock 0 +.latch n4234 Ng1579 re clock 0 +.latch n4239 Ng1582 re clock 0 +.latch n4244 Ng1621 re clock 0 +.latch n4249 Ng1624 re clock 0 +.latch n4254 Ng1627 re clock 0 +.latch n4259 Ng1585 re clock 0 +.latch n4264 Ng1588 re clock 0 +.latch n4269 Ng1591 re clock 0 +.latch n4274 Ng1630 re clock 0 +.latch n4279 Ng1633 re clock 0 +.latch n4284 Ng1636 re clock 0 +.latch n4289 Ng1594 re clock 0 +.latch n4294 Ng1597 re clock 0 +.latch n4299 Ng1600 re clock 0 +.latch n4304 Ng1639 re clock 0 +.latch n4309 Ng1642 re clock 0 +.latch n4314 Ng1645 re clock 0 +.latch n4319 Ng1603 re clock 0 +.latch n4324 Ng1606 re clock 0 +.latch n4329 Ng1609 re clock 0 +.latch n4334 Ng1648 re clock 0 +.latch n4339 Ng1651 re clock 0 +.latch n4344 Ng1654 re clock 0 +.latch n4349 Ng1466 re clock 0 +.latch n4354 Ng1462 re clock 0 +.latch n4359 Ng1457 re clock 0 +.latch n4364 Ng1453 re clock 0 +.latch n4369 Ng1448 re clock 0 +.latch n4374 Ng1444 re clock 0 +.latch n4379 Ng1439 re clock 0 +.latch n4384 Ng1435 re clock 0 +.latch n4389 Ng1430 re clock 0 +.latch n4394 Ng1426 re clock 0 +.latch n4399 Ng11551 re clock 0 +.latch n4404 Ng11552 re clock 0 +.latch n4409 Ng11553 re clock 0 +.latch n4414 Ng11554 re clock 0 +.latch n4419 Ng11555 re clock 0 +.latch n4424 Ng11556 re clock 0 +.latch n4429 Ng11557 re clock 0 +.latch n4434 Ng11558 re clock 0 +.latch n4439 Ng11559 re clock 0 +.latch n4444 Ng11560 re clock 0 +.latch n4449 Ng11561 re clock 0 +.latch n4454 Ng11562 re clock 0 +.latch n4459 Ng1789 re clock 0 +.latch n4464 Ng1792 re clock 0 +.latch n4469 Ng1795 re clock 0 +.latch n4474 Ng1798 re clock 0 +.latch n4479 Ng1801 re clock 0 +.latch n4484 Ng1804 re clock 0 +.latch n4489 Ng1808 re clock 0 +.latch n4494 Ng1809 re clock 0 +.latch n4499 Ng1807 re clock 0 +.latch n4504 Ng1810 re clock 0 +.latch n4509 Ng1813 re clock 0 +.latch n4514 Ng1816 re clock 0 +.latch n4519 Ng1819 re clock 0 +.latch n4524 Ng1822 re clock 0 +.latch n4529 Ng1825 re clock 0 +.latch n4534 Ng1829 re clock 0 +.latch n4539 Ng1830 re clock 0 +.latch n4544 Ng1828 re clock 0 +.latch n4549 Ng1693 re clock 0 +.latch n4554 Ng1694 re clock 0 +.latch n4559 Ng1695 re clock 0 +.latch n4564_1 Ng1696 re clock 0 +.latch n4569 Ng1697 re clock 0 +.latch n4574 Ng1698 re clock 0 +.latch n4579 Ng1699 re clock 0 +.latch n4584 Ng1700 re clock 0 +.latch n4589 Ng1701 re clock 0 +.latch n4594 Ng1703 re clock 0 +.latch n4599 Ng1704 re clock 0 +.latch n4604 Ng1702 re clock 0 +.latch n4609_1 Ng1784 re clock 0 +.latch n4614 Ng1785 re clock 0 +.latch n4619 Ng1783 re clock 0 +.latch n4624 Ng1831 re clock 0 +.latch n4628 Ng1832 re clock 0 +.latch n4633 Ng1833 re clock 0 +.latch n4637 Ng1834 re clock 0 +.latch n4642 Ng1835 re clock 0 +.latch n4646 Ng1660 re clock 0 +.latch n4651 Ng1661 re clock 0 +.latch n4655 Ng1662 re clock 0 +.latch n4660 Ng1663 re clock 0 +.latch n4664 Ng1664 re clock 0 +.latch n4669 Ng1665 re clock 0 +.latch n4673 Ng1666 re clock 0 +.latch n4678 Ng1667 re clock 0 +.latch n4682 Ng1668 re clock 0 +.latch n4687 Ng1669 re clock 0 +.latch n4691 Ng1670 re clock 0 +.latch n4695 Ng1671 re clock 0 +.latch n4699 Ng1672 re clock 0 +.latch n4704 Ng1680 re clock 0 +.latch n4709 Ng1686 re clock 0 +.latch n4714 Ng1679 re clock 0 +.latch n4718 Ng1723 re clock 0 +.latch n4722 Ng1730 re clock 0 +.latch n4726 Ng1731 re clock 0 +.latch n4730 Ng1732 re clock 0 +.latch n4734 Ng1733 re clock 0 +.latch n4738 Ng1734 re clock 0 +.latch n4742_1 Ng1738 re clock 0 +.latch n4746 Ng1745 re clock 0 +.latch n4750 Ng1746 re clock 0 +.latch n4754 Ng1747 re clock 0 +.latch n4758 Ng1748 re clock 0 +.latch n4762 Ng1749 re clock 0 +.latch n4766 Ng1753 re clock 0 +.latch n4770 Ng1760 re clock 0 +.latch n4774 Ng1761 re clock 0 +.latch n4778 Ng1762 re clock 0 +.latch n4782 Ng1763 re clock 0 +.latch n4786 Ng1764 re clock 0 +.latch n4790 Ng1768 re clock 0 +.latch n4794 Ng1775 re clock 0 +.latch n4798 Ng1776 re clock 0 +.latch n4802 Ng1777 re clock 0 +.latch n4806 Ng1778 re clock 0 +.latch n4810 Ng1705 re clock 0 +.latch n4815 Ng1934 re clock 0 +.latch n4820 Ng1937 re clock 0 +.latch n4825 Ng1890 re clock 0 +.latch n4830 Ng1893 re clock 0 +.latch n4834_1 Ng1903 re clock 0 +.latch n4838_1 Ng1904 re clock 0 +.latch n4843 Ng1944 re clock 0 +.latch n4847 Ng1949 re clock 0 +.latch n4852 Ng1950 re clock 0 +.latch n4856_1 Ng1951 re clock 0 +.latch n4861_1 Ng1952 re clock 0 +.latch n4865 Ng1953 re clock 0 +.latch n4870 Ng1954 re clock 0 +.latch n4874 Ng1945 re clock 0 +.latch n4879 Ng1946 re clock 0 +.latch n4883 Ng1947 re clock 0 +.latch n4888_1 Ng1948 re clock 0 +.latch n4892 Ng1870 re clock 0 +.latch n4897 Ng1867 re clock 0 +.latch n4902 Ng1868 re clock 0 +.latch n4907 Ng1869 re clock 0 +.latch n4912 Ng11566 re clock 0 +.latch n4916 Ng11569 re clock 0 +.latch n4920 Ng11570 re clock 0 +.latch n4924_1 Ng1858 re clock 0 +.latch n4929 Ng1859 re clock 0 +.latch n4934 Ng1860 re clock 0 +.latch n4939 Ng1861 re clock 0 +.latch n4944 Ng1865 re clock 0 +.latch n4949 Ng1845 re clock 0 +.latch n4954 Ng11571 re clock 0 +.latch n4958_1 Ng11567 re clock 0 +.latch n4962 Ng11568 re clock 0 +.latch n4966 Ng1908 re clock 0 +.latch n4970 Ng1915 re clock 0 +.latch n4974 Ng1922 re clock 0 +.latch n4979 Ng1923 re clock 0 +.latch n4983_1 Ng1924 re clock 0 +.latch n4988_1 Ng1928 re clock 0 +.latch n4993_1 Ng1929 re clock 0 +.latch n4997 Ng8302 re clock 0 +.latch n5002 Ng1938 re clock 0 +.latch n5006 Ng1939 re clock 0 +.latch n5011 Ng1956 re clock 0 +.latch n5016 Ng1957 re clock 0 +.latch n5021 Ng1955 re clock 0 +.latch n5026 Ng1959 re clock 0 +.latch n5031 Ng1960 re clock 0 +.latch n5036 Ng1958 re clock 0 +.latch n5041 Ng1962 re clock 0 +.latch n5046 Ng1963 re clock 0 +.latch n5051 Ng1961 re clock 0 +.latch n5056 Ng1965 re clock 0 +.latch n5061 Ng1966 re clock 0 +.latch n5066 Ng1964 re clock 0 +.latch n5071 Ng1967 re clock 0 +.latch n5076 Ng1970 re clock 0 +.latch n5081 Ng1973 re clock 0 +.latch n5086 Ng1976 re clock 0 +.latch n5091 Ng1979 re clock 0 +.latch n5096 Ng1982 re clock 0 +.latch n5101 Ng1994 re clock 0 +.latch n5106 Ng1997 re clock 0 +.latch n5111 Ng2000 re clock 0 +.latch n5116 Ng1985 re clock 0 +.latch n5121 Ng1988 re clock 0 +.latch n5126 Ng1991 re clock 0 +.latch n5131 Ng1871 re clock 0 +.latch n5136 Ng1874 re clock 0 +.latch n5141 Ng1877 re clock 0 +.latch n5145_1 Ng1886 re clock 0 +.latch n5150_1 Ng1887 re clock 0 +.latch n5154 Ng1905 re clock 0 +.latch n5159 Ng1909 re clock 0 +.latch n5164 Ng1910 re clock 0 +.latch n5169 Ng1911 re clock 0 +.latch n5174 Ng1912 re clock 0 +.latch n5179 Ng1913 re clock 0 +.latch n5184 Ng1914 re clock 0 +.latch n5189 Ng1916 re clock 0 +.latch n5194 Ng1917 re clock 0 +.latch n5199 Ng1918 re clock 0 +.latch n5204 Ng1921 re clock 0 +.latch n5209 Ng2010 re clock 0 +.latch n5214 Ng2039 re clock 0 +.latch n5219 Ng2020 re clock 0 +.latch n5224 Ng2013 re clock 0 +.latch n5229 Ng2033 re clock 0 +.latch n5234 Ng2026 re clock 0 +.latch n5239 Ng2040 re clock 0 +.latch n5244 Ng2052 re clock 0 +.latch n5249 Ng2046 re clock 0 +.latch n5254 Ng2059 re clock 0 +.latch n5259 Ng2066 re clock 0 +.latch n5264 Ng2072 re clock 0 +.latch n5269 Ng2079 re clock 0 +.latch n5274 Ng2080 re clock 0 +.latch n5279 Ng2078 re clock 0 +.latch n5284 Ng2082 re clock 0 +.latch n5289 Ng2083 re clock 0 +.latch n5294 Ng2081 re clock 0 +.latch n5299 Ng2085 re clock 0 +.latch n5304 Ng2086 re clock 0 +.latch n5309 Ng2084 re clock 0 +.latch n5314 Ng2088 re clock 0 +.latch n5319 Ng2089 re clock 0 +.latch n5324 Ng2087 re clock 0 +.latch n5329 Ng2091 re clock 0 +.latch n5334 Ng2092 re clock 0 +.latch n5339 Ng2090 re clock 0 +.latch n5344 Ng2094 re clock 0 +.latch n5349 Ng2095 re clock 0 +.latch n5354 Ng2093 re clock 0 +.latch n5359 Ng2097 re clock 0 +.latch n5364 Ng2098 re clock 0 +.latch n5369 Ng2096 re clock 0 +.latch n5374 Ng2100 re clock 0 +.latch n5379 Ng2101 re clock 0 +.latch n5384 Ng2099 re clock 0 +.latch n5389 Ng2103 re clock 0 +.latch n5394 Ng2104 re clock 0 +.latch n5399 Ng2102 re clock 0 +.latch n5404 Ng2106 re clock 0 +.latch n5409 Ng2107 re clock 0 +.latch n5414 Ng2105 re clock 0 +.latch n5419 Ng2109 re clock 0 +.latch n5424 Ng2110 re clock 0 +.latch n5429 Ng2108 re clock 0 +.latch n5434 Ng2112 re clock 0 +.latch n5439 Ng2113 re clock 0 +.latch n5444 Ng2111 re clock 0 +.latch n5449 Ng2115 re clock 0 +.latch n5454 Ng2116 re clock 0 +.latch n5459 Ng2114 re clock 0 +.latch n5464 Ng2118 re clock 0 +.latch n5469 Ng2119 re clock 0 +.latch n5474 Ng2117 re clock 0 +.latch n5479 Ng2206 re clock 0 +.latch n5484 Ng2207 re clock 0 +.latch n5489 Ng2205 re clock 0 +.latch n5494 Ng2209 re clock 0 +.latch n5499 Ng2210 re clock 0 +.latch n5504 Ng2208 re clock 0 +.latch n5509 Ng2218 re clock 0 +.latch n5514 Ng2219 re clock 0 +.latch n5519 Ng2217 re clock 0 +.latch n5524 Ng2221 re clock 0 +.latch n5529 Ng2222 re clock 0 +.latch n5534 Ng2220 re clock 0 +.latch n5539 Ng2224 re clock 0 +.latch n5544 Ng2225 re clock 0 +.latch n5549 Ng2223 re clock 0 +.latch n5554 Ng2227 re clock 0 +.latch n5559 Ng2228 re clock 0 +.latch n5564 Ng2226 re clock 0 +.latch n5569 Ng2230 re clock 0 +.latch n5574 Ng2231 re clock 0 +.latch n5579 Ng2229 re clock 0 +.latch n5584 Ng2233 re clock 0 +.latch n5589 Ng2234 re clock 0 +.latch n5594 Ng2232 re clock 0 +.latch n5599 Ng2236 re clock 0 +.latch n5604 Ng2237 re clock 0 +.latch n5609 Ng2235 re clock 0 +.latch n5614 Ng2239 re clock 0 +.latch n5619 Ng2240 re clock 0 +.latch n5624 Ng2238 re clock 0 +.latch n5629 Ng2245 re clock 0 +.latch n5634 Ng2246 re clock 0 +.latch n5639 Ng2244 re clock 0 +.latch n5644 Ng2248 re clock 0 +.latch n5649 Ng2249 re clock 0 +.latch n5654 Ng2247 re clock 0 +.latch n5659 Ng2251 re clock 0 +.latch n5664 Ng2252 re clock 0 +.latch n5669 Ng2250 re clock 0 +.latch n5674 Ng2254 re clock 0 +.latch n5679 Ng2255 re clock 0 +.latch n5684 Ng2253 re clock 0 +.latch n5689 Ng2261 re clock 0 +.latch n5694 Ng2264 re clock 0 +.latch n5699 Ng2267 re clock 0 +.latch n5704 Ng2306 re clock 0 +.latch n5709 Ng2309 re clock 0 +.latch n5714 Ng2312 re clock 0 +.latch n5719 Ng2270 re clock 0 +.latch n5724 Ng2273 re clock 0 +.latch n5729 Ng2276 re clock 0 +.latch n5734 Ng2315 re clock 0 +.latch n5739 Ng2318 re clock 0 +.latch n5744 Ng2321 re clock 0 +.latch n5749 Ng2279 re clock 0 +.latch n5754 Ng2282 re clock 0 +.latch n5759 Ng2285 re clock 0 +.latch n5764 Ng2324 re clock 0 +.latch n5769 Ng2327 re clock 0 +.latch n5774 Ng2330 re clock 0 +.latch n5779 Ng2288 re clock 0 +.latch n5784 Ng2291 re clock 0 +.latch n5789 Ng2294 re clock 0 +.latch n5794 Ng2333 re clock 0 +.latch n5799 Ng2336 re clock 0 +.latch n5804 Ng2339 re clock 0 +.latch n5809 Ng2297 re clock 0 +.latch n5814 Ng2300 re clock 0 +.latch n5819 Ng2303 re clock 0 +.latch n5824 Ng2342 re clock 0 +.latch n5829 Ng2345 re clock 0 +.latch n5834 Ng2348 re clock 0 +.latch n5839 Ng2160 re clock 0 +.latch n5844 Ng2156 re clock 0 +.latch n5849 Ng2151 re clock 0 +.latch n5854 Ng2147 re clock 0 +.latch n5859 Ng2142 re clock 0 +.latch n5864 Ng2138 re clock 0 +.latch n5869 Ng2133 re clock 0 +.latch n5874 Ng2129 re clock 0 +.latch n5879 Ng2124 re clock 0 +.latch n5884 Ng2120 re clock 0 +.latch n5889 Ng2256 re clock 0 +.latch n5893_1 Pg5549 re clock 0 +.latch n5896 Ng2257 re clock 0 +.latch n5901 Ng11578 re clock 0 +.latch n5906 Ng11579 re clock 0 +.latch n5911 Ng11580 re clock 0 +.latch n5916 Ng11581 re clock 0 +.latch n5921 Ng11582 re clock 0 +.latch n5926 Ng11583 re clock 0 +.latch n5931 Ng11584 re clock 0 +.latch n5936 Ng11585 re clock 0 +.latch n5941 Ng11586 re clock 0 +.latch n5946 Ng11587 re clock 0 +.latch n5951 Ng11588 re clock 0 +.latch n5956 Ng11589 re clock 0 +.latch n5961 Ng2483 re clock 0 +.latch n5966 Ng2486 re clock 0 +.latch n5971 Ng2489 re clock 0 +.latch n5976 Ng2492 re clock 0 +.latch n5981 Ng2495 re clock 0 +.latch n5986 Ng2498 re clock 0 +.latch n5991 Ng2502 re clock 0 +.latch n5996 Ng2503 re clock 0 +.latch n6001 Ng2501 re clock 0 +.latch n6006 Ng2504 re clock 0 +.latch n6011 Ng2507 re clock 0 +.latch n6016 Ng2510 re clock 0 +.latch n6021 Ng2513 re clock 0 +.latch n6026 Ng2516 re clock 0 +.latch n6031 Ng2519 re clock 0 +.latch n6036 Ng2523 re clock 0 +.latch n6041 Ng2524 re clock 0 +.latch n6046 Ng2522 re clock 0 +.latch n6051 Ng2387 re clock 0 +.latch n6056 Ng2388 re clock 0 +.latch n6061 Ng2389 re clock 0 +.latch n6066 Ng2390 re clock 0 +.latch n6071_1 Ng2391 re clock 0 +.latch n6076 Ng2392 re clock 0 +.latch n6081 Ng2393 re clock 0 +.latch n6086 Ng2394 re clock 0 +.latch n6091 Ng2395 re clock 0 +.latch n6096 Ng2397 re clock 0 +.latch n6101 Ng2398 re clock 0 +.latch n6106 Ng2396 re clock 0 +.latch n6111 Ng2478 re clock 0 +.latch n6116_1 Ng2479 re clock 0 +.latch n6121 Ng2477 re clock 0 +.latch n6126 Ng2525 re clock 0 +.latch n6130 Ng2526 re clock 0 +.latch n6135 Ng2527 re clock 0 +.latch n6139 Ng2528 re clock 0 +.latch n6144 Ng2529 re clock 0 +.latch n6148 Ng2354 re clock 0 +.latch n6153 Ng2355 re clock 0 +.latch n6157 Ng2356 re clock 0 +.latch n6162 Ng2357 re clock 0 +.latch n6166 Ng2358 re clock 0 +.latch n6171 Ng2359 re clock 0 +.latch n6175 Ng2360 re clock 0 +.latch n6180 Ng2361 re clock 0 +.latch n6184 Ng2362 re clock 0 +.latch n6189 Ng2363 re clock 0 +.latch n6193 Ng2364 re clock 0 +.latch n6197 Ng2365 re clock 0 +.latch n6201 Ng2366 re clock 0 +.latch n6206 Ng2374 re clock 0 +.latch n6211 Ng2380 re clock 0 +.latch n6216 Ng2373 re clock 0 +.latch n6220 Ng2417 re clock 0 +.latch n6224 Ng2424 re clock 0 +.latch n6228 Ng2425 re clock 0 +.latch n6232 Ng2426 re clock 0 +.latch n6236 Ng2427 re clock 0 +.latch n6240 Ng2428 re clock 0 +.latch n6244_1 Ng2432 re clock 0 +.latch n6248 Ng2439 re clock 0 +.latch n6252 Ng2440 re clock 0 +.latch n6256 Ng2441 re clock 0 +.latch n6260 Ng2442 re clock 0 +.latch n6264 Ng2443 re clock 0 +.latch n6268 Ng2447 re clock 0 +.latch n6272 Ng2454 re clock 0 +.latch n6276 Ng2455 re clock 0 +.latch n6280 Ng2456 re clock 0 +.latch n6284 Ng2457 re clock 0 +.latch n6288 Ng2458 re clock 0 +.latch n6292 Ng2462 re clock 0 +.latch n6296 Ng2469 re clock 0 +.latch n6300 Ng2470 re clock 0 +.latch n6304 Ng2471 re clock 0 +.latch n6308 Ng2472 re clock 0 +.latch n6312 Ng2399 re clock 0 +.latch n6317 Ng2628 re clock 0 +.latch n6322 Ng2631 re clock 0 +.latch n6327 Ng2584 re clock 0 +.latch n6332 Ng2587 re clock 0 +.latch n6336_1 Ng2597 re clock 0 +.latch n6340 Ng2598 re clock 0 +.latch n6345_1 Ng2638 re clock 0 +.latch n6349_1 Ng2643 re clock 0 +.latch n6354 Ng2644 re clock 0 +.latch n6358_1 Ng2645 re clock 0 +.latch n6363_1 Ng2646 re clock 0 +.latch n6367 Ng2647 re clock 0 +.latch n6372 Ng2648 re clock 0 +.latch n6376 Ng2639 re clock 0 +.latch n6381 Ng2640 re clock 0 +.latch n6385 Ng2641 re clock 0 +.latch n6390 Ng2642 re clock 0 +.latch n6394 Ng2564 re clock 0 +.latch n6399 Ng2561 re clock 0 +.latch n6404 Ng2562 re clock 0 +.latch n6409 Ng2563 re clock 0 +.latch n6414 Ng11593 re clock 0 +.latch n6418 Ng11596 re clock 0 +.latch n6422_1 Ng11597 re clock 0 +.latch n6426 Ng2552 re clock 0 +.latch n6431_1 Ng2553 re clock 0 +.latch n6436 Ng2554 re clock 0 +.latch n6441 Ng2555 re clock 0 +.latch n6446 Ng2559 re clock 0 +.latch n6451 Ng2539 re clock 0 +.latch n6456 Ng11598 re clock 0 +.latch n6460_1 Ng11594 re clock 0 +.latch n6464 Ng11595 re clock 0 +.latch n6468 Ng2602 re clock 0 +.latch n6472 Ng2609 re clock 0 +.latch n6476 Ng2616 re clock 0 +.latch n6481 Ng2617 re clock 0 +.latch n6485_1 Ng2618 re clock 0 +.latch n6490_1 Ng2622 re clock 0 +.latch n6495_1 Ng2623 re clock 0 +.latch n6499 Ng8311 re clock 0 +.latch n6504 Ng2632 re clock 0 +.latch n6508 Ng2633 re clock 0 +.latch n6513 Ng2650 re clock 0 +.latch n6518 Ng2651 re clock 0 +.latch n6523 Ng2649 re clock 0 +.latch n6528 Ng2653 re clock 0 +.latch n6533 Ng2654 re clock 0 +.latch n6538 Ng2652 re clock 0 +.latch n6543 Ng2656 re clock 0 +.latch n6548 Ng2657 re clock 0 +.latch n6553 Ng2655 re clock 0 +.latch n6558 Ng2659 re clock 0 +.latch n6563 Ng2660 re clock 0 +.latch n6568 Ng2658 re clock 0 +.latch n6573 Ng2661 re clock 0 +.latch n6578 Ng2664 re clock 0 +.latch n6583 Ng2667 re clock 0 +.latch n6588 Ng2670 re clock 0 +.latch n6593 Ng2673 re clock 0 +.latch n6598 Ng2676 re clock 0 +.latch n6603 Ng2688 re clock 0 +.latch n6608 Ng2691 re clock 0 +.latch n6613 Ng2694 re clock 0 +.latch n6618 Ng2679 re clock 0 +.latch n6623 Ng2682 re clock 0 +.latch n6628 Ng2685 re clock 0 +.latch n6633 Ng2565 re clock 0 +.latch n6638 Ng2568 re clock 0 +.latch n6643 Ng2571 re clock 0 +.latch n6647_1 Ng2580 re clock 0 +.latch n6652_1 Ng2581 re clock 0 +.latch n6656 Ng2599 re clock 0 +.latch n6661 Ng2603 re clock 0 +.latch n6666 Ng2604 re clock 0 +.latch n6671 Ng2605 re clock 0 +.latch n6676 Ng2606 re clock 0 +.latch n6681 Ng2607 re clock 0 +.latch n6686 Ng2608 re clock 0 +.latch n6691 Ng2610 re clock 0 +.latch n6696 Ng2611 re clock 0 +.latch n6701 Ng2612 re clock 0 +.latch n6706 Ng2615 re clock 0 +.latch n6711 Ng2704 re clock 0 +.latch n6716 Ng2733 re clock 0 +.latch n6721 Ng2714 re clock 0 +.latch n6726 Ng2707 re clock 0 +.latch n6731 Ng2727 re clock 0 +.latch n6736 Ng2720 re clock 0 +.latch n6741 Ng2734 re clock 0 +.latch n6746 Ng2746 re clock 0 +.latch n6751 Ng2740 re clock 0 +.latch n6756 Ng2753 re clock 0 +.latch n6761 Ng2760 re clock 0 +.latch n6766 Ng2766 re clock 0 +.latch n6771 Ng2773 re clock 0 +.latch n6776 Ng2774 re clock 0 +.latch n6781 Ng2772 re clock 0 +.latch n6786 Ng2776 re clock 0 +.latch n6791 Ng2777 re clock 0 +.latch n6796 Ng2775 re clock 0 +.latch n6801 Ng2779 re clock 0 +.latch n6806 Ng2780 re clock 0 +.latch n6811 Ng2778 re clock 0 +.latch n6816 Ng2782 re clock 0 +.latch n6821 Ng2783 re clock 0 +.latch n6826 Ng2781 re clock 0 +.latch n6831 Ng2785 re clock 0 +.latch n6836 Ng2786 re clock 0 +.latch n6841 Ng2784 re clock 0 +.latch n6846 Ng2788 re clock 0 +.latch n6851 Ng2789 re clock 0 +.latch n6856 Ng2787 re clock 0 +.latch n6861 Ng2791 re clock 0 +.latch n6866 Ng2792 re clock 0 +.latch n6871 Ng2790 re clock 0 +.latch n6876 Ng2794 re clock 0 +.latch n6881 Ng2795 re clock 0 +.latch n6886 Ng2793 re clock 0 +.latch n6891 Ng2797 re clock 0 +.latch n6896 Ng2798 re clock 0 +.latch n6901 Ng2796 re clock 0 +.latch n6906 Ng2800 re clock 0 +.latch n6911 Ng2801 re clock 0 +.latch n6916 Ng2799 re clock 0 +.latch n6921 Ng2803 re clock 0 +.latch n6926_1 Ng2804 re clock 0 +.latch n6931_1 Ng2802 re clock 0 +.latch n6936_1 Ng2806 re clock 0 +.latch n6941_1 Ng2807 re clock 0 +.latch n6946_1 Ng2805 re clock 0 +.latch n6951_1 Ng2809 re clock 0 +.latch n6956_1 Ng2810 re clock 0 +.latch n6961_1 Ng2808 re clock 0 +.latch n6966_1 Ng2812 re clock 0 +.latch n6971_1 Ng2813 re clock 0 +.latch n6976_1 Ng2811 re clock 0 +.latch n6981_1 Ng3054 re clock 0 +.latch n6986_1 Ng3079 re clock 0 +.latch n6991_1 Ng13475 re clock 0 +.latch n6995 Ng3043 re clock 0 +.latch n7000 Ng3044 re clock 0 +.latch n7005 Ng3045 re clock 0 +.latch n7010 Ng3046 re clock 0 +.latch n7015 Ng3047 re clock 0 +.latch n7020 Ng3048 re clock 0 +.latch n7025 Ng3049 re clock 0 +.latch n7030 Ng3050 re clock 0 +.latch n7035 Ng3051 re clock 0 +.latch n7040 Ng3052 re clock 0 +.latch n7045 Ng3053 re clock 0 +.latch n7050 Ng3055 re clock 0 +.latch n7055 Ng3056 re clock 0 +.latch n7060 Ng3057 re clock 0 +.latch n7065 Ng3058 re clock 0 +.latch n7070 Ng3059 re clock 0 +.latch n7075 Ng3060 re clock 0 +.latch n7080 Ng3061 re clock 0 +.latch n7085 Ng3062 re clock 0 +.latch n7090 Ng3063 re clock 0 +.latch n7095 Ng3064 re clock 0 +.latch n7100 Ng3065 re clock 0 +.latch n7105 Ng3066 re clock 0 +.latch n7110 Ng3067 re clock 0 +.latch n7115 Ng3068 re clock 0 +.latch n7120 Ng3069 re clock 0 +.latch n7125 Ng3070 re clock 0 +.latch n7130 Ng3071 re clock 0 +.latch n7135 Ng3072 re clock 0 +.latch n7140 Ng3073 re clock 0 +.latch n7145 Ng3074 re clock 0 +.latch n7150 Ng3075 re clock 0 +.latch n7155 Ng3076 re clock 0 +.latch n7160 Ng3077 re clock 0 +.latch n7165 Ng3078 re clock 0 +.latch n7170 Ng2997 re clock 0 +.latch n7175 Ng2993 re clock 0 +.latch n7180_1 Ng2998 re clock 0 +.latch n7185 Ng3006 re clock 0 +.latch n7190 Ng3002 re clock 0 +.latch n7195 Ng3013 re clock 0 +.latch n7200_1 Ng3010 re clock 0 +.latch n7205 Ng3024 re clock 0 +.latch n7210 Ng3018 re clock 0 +.latch n7215 Ng3028 re clock 0 +.latch n7220 Ng3036 re clock 0 +.latch n7225 Ng3032 re clock 0 +.latch n7229 Ng2986 re clock 0 +.latch n7233 Ng2987 re clock 0 +.latch n7238_1 Ng3083 re clock 0 +.latch n7243 Ng2992 re clock 0 +.latch n7248 Ng2990 re clock 0 +.latch n7253 Ng2991 re clock 0 + +.names Pg3233 Pg3230 Pg25420 +10 0 +.names n4526 Ng3135 Ng3147 Ng3110 Ng3126 Ng3191 n4525 +110000 1 +.names Ng3120 Ng3139 n4526 +10 1 +.names n4528 Ng3120 Ng3139 n4527 +100 1 +.names Ng3147 Ng3135 Ng3110 Ng3126 Ng3191 n4528 +00000 1 +.names Ng3139 Ng185 Ng2991 Ng2992 n4529_1 +0-00 1 +10-- 1 +.names Ng3110 Ng3147 Ng3135 Ng3126 Ng3191 n4530 +10000 1 +.names Ng3110 Ng3135 Ng3147 Ng3126 Ng3191 n4531 +11000 1 +.names n4534_1 Ng3120 Ng3139 n4533 Ng3173 Ng3167 n4532 +100--1 0 +110-1- 0 +---0-- 0 +.names Ng3120 Ng3139 Ng3164 n4530 n4531 Ng3185 n4533 +10--11 0 +1111-- 0 +.names Ng3147 Ng3110 Ng3135 Ng3126 Ng3191 n4534_1 +11000 1 +.names Ng3139 n4534_1 Ng3120 Ng3176 Ng3170 n4535 +110-1 0 +1111- 0 +.names Ng3147 Ng3110 Ng3126 Ng3191 Ng3120 Ng3139 n4536 +100000 1 +.names Ng3147 Ng3135 n4526 Ng3110 Ng3126 Ng3191 n4537 +111000 1 +.names Ng3120 Ng3139 Ng3097 n4530 n4534_1 Ng3103 n4538 +0011-- 0 +10--11 0 +.names n4534_1 Ng3139 Ng3120 Ng3102 Ng3101 n4539_1 +100-1 0 +1101- 0 +.names n4531 Ng3120 Ng3139 Ng3108 Ng3107 Ng3105 n4540 +100--1 0 +110-1- 0 +1111-- 0 +.names Ng3120 n4531 Ng3139 n4542 Ng3094 Ng3093 n4541 +010--1 0 +011-1- 0 +1--0-- 0 +.names n4537 n4525 n4542 +00 1 +.names n4534_1 Ng3139 Ng3120 Ng3092 Ng3087 Ng3086 n4543 +100--1 0 +110-1- 0 +1111-- 0 +.names Ng3147 n4545 Ng3120 Ng3139 Ng3097 Pg25489 +00--- 1 +1-111 1 +.names Ng3120 Ng3139 Ng2985 Ng2984 Ng2991 Ng2992 n4545 +11---- 1 +1---00 1 +-100-- 1 +.names Pg25420 n4525 Ng3125 n953 +00- 1 +0-1 1 +.names Pg25420 n4525 Ng3123 n958_1 +00- 1 +0-1 1 +.names Ng2987 Pg5388 Ng2986 Pg16496 +0-- 1 +-10 1 +.names Ng2879 Pg8021 Ng2929 n521 +0-- 1 +-10 1 +.names Ng1315 n4551 Ng659 n2213 +0-1 1 +11- 1 +.names Ng3002 Ng3024 Ng3006 Ng3010 Ng3013 n4551 +00000 1 +.names Ng1315 n4551 Ng1345 n3724 +0-1 1 +11- 1 +.names Ng1315 n4551 Ng2039 n5214 +0-1 1 +11- 1 +.names Ng1315 n4551 Ng2733 n6716 +0-1 1 +11- 1 +.names Ng1315 n4556 Ng554 n1814 +0-1 1 +10- 1 +.names Ng3028 Ng3018 n4557 Ng3036 Ng3032 n4556 +11100 1 +.names n4558 Ng2998 Ng3002 Ng2993 n4557 +1110 1 +.names Ng3024 Ng3013 Ng3006 Ng3010 n4558 +1100 1 +.names Ng1315 n4556 Ng1240 n3314 +0-1 1 +10- 1 +.names Ng1315 n4556 Ng1934 n4815 +0-1 1 +10- 1 +.names Ng1315 n4556 Ng2628 n6317 +0-1 1 +10- 1 +.names n4563 n4551 n4564 Ng510 n4565 n2149 +10--- 1 +1--10 1 +-01-- 1 +.names Ng496 Ng1315 Ng490 Pg5629 Pg5648 Ng493 n4563 +11---- 0 +--11-- 0 +----11 0 +.names Ng611 Ng1315 Pg5629 Ng605 Ng608 Pg5648 n4564 +11---- 0 +--11-- 0 +----11 0 +.names Ng620 Ng1315 Pg5629 Ng614 Ng617 Pg5648 n4565 +11---- 0 +--11-- 0 +----11 0 +.names n4567 n4551 n4568 Ng1196 n4569_1 n3649 +10--- 1 +1--10 1 +-01-- 1 +.names Ng1183 Ng1315 Pg5629 Ng1177 Ng1180 Pg5648 n4567 +11---- 0 +--11-- 0 +----11 0 +.names Ng1297 Ng1315 Pg5629 Ng1291 Ng1294 Pg5648 n4568 +11---- 0 +--11-- 0 +----11 0 +.names Ng1306 Ng1315 Pg5629 Ng1300 Ng1303 Pg5648 n4569_1 +11---- 0 +--11-- 0 +----11 0 +.names n4571 n4551 n4572 Ng1890 n4573 n5150_1 +10--- 1 +1--10 1 +-01-- 1 +.names Ng1877 Ng1315 Pg5629 Ng1871 Ng1874 Pg5648 n4571 +11---- 0 +--11-- 0 +----11 0 +.names Ng1991 Ng1315 Pg5629 Ng1985 Ng1988 Pg5648 n4572 +11---- 0 +--11-- 0 +----11 0 +.names Ng2000 Ng1315 Pg5629 Ng1994 Ng1997 Pg5648 n4573 +11---- 0 +--11-- 0 +----11 0 +.names n4575 n4551 n4576 Ng2584 n4577 n6652_1 +10--- 1 +1--10 1 +-01-- 1 +.names Ng2571 Ng1315 Pg5629 Ng2565 Ng2568 Pg5648 n4575 +11---- 0 +--11-- 0 +----11 0 +.names Ng2685 Ng1315 Pg5629 Ng2679 Ng2682 Pg5648 n4576 +11---- 0 +--11-- 0 +----11 0 +.names Ng2694 Ng1315 Pg5629 Ng2688 Ng2691 Pg5648 n4577 +11---- 0 +--11-- 0 +----11 0 +.names Ng8284 Ng544 Ng548 Pg5629 n1987 +0-10 1 +11-- 1 +.names Ng8293 Pg5629 Ng1230 Ng1234 Ng544 Ng8284 n3487 +00-1-- 1 +01--11 1 +1-1--- 1 +.names Ng8302 Pg5629 Ng1924 n3487 Ng1928 n4988_1 +00--1 1 +01-1- 1 +1-1-- 1 +.names Ng8311 Pg5629 Ng2618 n4988_1 Ng2622 n6490_1 +00--1 1 +01-1- 1 +1-1-- 1 +.names Pg5437 Ng417 Ng853 Ng423 Pg6313 Ng420 n1703 +11---- 1 +--11-- 1 +----11 1 +.names Ng1104 Pg5437 Ng1110 Ng853 Ng1107 Pg6313 n3203 +11---- 1 +--11-- 1 +----11 1 +.names Ng1798 Pg5437 Ng1804 Ng853 Ng1801 Pg6313 n4704 +11---- 1 +--11-- 1 +----11 1 +.names Ng2492 Pg5437 Ng2498 Ng853 Ng2495 Pg6313 n6206 +11---- 1 +--11-- 1 +----11 1 +.names Ng8311 Ng2633 Pg2637 n6490_1 n4586 +1000 1 +.names n4595 n4588 n4587 +11 1 +.names n4590 n4594_1 n4593 n4592 n4591 n4589_1 n4588 +100000 1 +.names Ng1315 Ng2778 Pg5629 Ng2779 Pg5648 Ng2780 n4589_1 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2784 Pg5629 Ng2785 Pg5648 Ng2786 n4590 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2796 Pg5629 Ng2797 Pg5648 Ng2798 n4591 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2775 Pg5629 Ng2776 Pg5648 Ng2777 n4592 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2805 Pg5629 Ng2806 Pg5648 Ng2807 n4593 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2811 Pg5629 Ng2812 Pg5648 Ng2813 n4594_1 +10---- 0 +--10-- 0 +----10 0 +.names n4601 n4596 n4599_1 n4598 n4600 n4597 n4595 +111100 1 +.names Ng1315 Ng2772 Pg5629 Ng2773 Pg5648 Ng2774 n4596 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2781 Pg5629 Ng2782 Pg5648 Ng2783 n4597 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2790 Pg5629 Ng2791 Pg5648 Ng2792 n4598 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2787 Pg5629 Ng2788 Pg5648 Ng2789 n4599_1 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2799 Pg5629 Ng2800 Pg5648 Ng2801 n4600 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2793 Pg5629 Ng2794 Pg5648 Ng2795 n4601 +10---- 0 +--10-- 0 +----10 0 +.names n4592 n4587 n4602 +00 1 +.names n4596 n4577 n4603 +01 1 +10 1 +.names n4600 n4587 n4604_1 +00 1 +.names n4577 n4591 n4587 n4605 +000 1 +11- 1 +1-1 1 +.names Ng2584 Ng2631 Ng2599 n4606 +01- 1 +0-1 1 +.names Pg3229 Ng2615 Ng2612 n4607 +00- 1 +1-0 1 +.names Ng2631 Ng2584 n4609 n4586 n4605 n7165 +10-0- 1 +10--0 1 +--1-- 1 +.names n4610 n4611 Ng2611 n4586 n4603 n4609 +01-0- 1 +01--1 1 +111-- 1 +1-10- 1 +.names n4606 Ng2633 Pg2637 n6490_1 n4610 +1000 1 +.names Ng2631 Ng2584 Ng2599 n4611 +01- 1 +0-1 1 +.names Ng2584 Ng2631 Ng2599 n4614_1 n4613 Ng2608 n7155 +001--1 1 +01-0-- 1 +0-10-- 1 +10--0- 1 +.names n4586 n4577 n4589_1 n4587 n4613 +1000 1 +111- 1 +11-1 1 +.names Ng2633 Pg2637 n6490_1 n4614_1 +000 1 +.names Ng2584 Ng2631 Ng2599 n4614_1 n4616 Ng2607 n7150 +001--1 1 +01-0-- 1 +0-10-- 1 +10--0- 1 +.names n4586 n4576 n4597 n4587 n4616 +1000 1 +111- 1 +11-1 1 +.names n4618 n4621 n4610 Ng2606 n7145 +00-- 0 +0-10 0 +.names Ng2631 Ng2584 n4614_1 n4619_1 n4618 +100- 1 +10-0 1 +.names Ng8311 n4587 n4620 Ng1315 Ng2808 n4619_1 +11--- 1 +1-0-- 1 +1--10 1 +.names Pg5629 Ng2809 Pg5648 Ng2810 n4620 +10-- 0 +--10 0 +.names Ng2584 n4586 n4590 n4577 n4611 n4621 +1100- 0 +1111- 0 +----0 0 +.names n4611 n4624_1 n4623 n4610 Ng2605 n7140 +10-0- 1 +10--1 1 +--1-- 1 +.names Ng2631 Ng2584 n4614_1 n4619_1 n4623 +100- 1 +10-1 1 +.names Ng2584 n4586 n4599_1 n4576 n4624_1 +1100 1 +1111 1 +.names n4623 n4626 n4610 Ng2604 n7135 +00-- 0 +0-10 0 +.names Ng2584 n4586 n4598 n4577 n4611 n4626 +1100- 0 +1111- 0 +----0 0 +.names n4611 n4628_1 n4618 n4610 Ng2603 n7130 +10-0- 1 +10--1 1 +--1-- 1 +.names Ng2584 n4586 n4601 n4576 n4628_1 +1100 1 +1111 1 +.names Ng8302 n4630 n4629 +11 1 +.names Ng1939 Pg1943 n4988_1 n4630 +000 1 +.names n4645 n4632 n4631 +00 1 +.names n4640 n4643 n4642_1 n4633_1 n4644 n4641 n4632 +111100 1 +.names n4635 n4638 n4639 n4637_1 n4636 n4634 n4633_1 +110000 1 +.names Ng1315 Ng2087 Pg5629 Ng2088 Pg5648 Ng2089 n4634 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2090 Pg5629 Ng2091 Pg5648 Ng2092 n4635 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2105 Pg5629 Ng2106 Pg5648 Ng2107 n4636 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2117 Pg5629 Ng2118 Pg5648 Ng2119 n4637_1 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2078 Pg5629 Ng2079 Pg5648 Ng2080 n4638 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2081 Pg5629 Ng2082 Pg5648 Ng2083 n4639 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2099 Pg5629 Ng2100 Pg5648 Ng2101 n4640 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2111 Pg5629 Ng2112 Pg5648 Ng2113 n4641 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2093 Pg5629 Ng2094 Pg5648 Ng2095 n4642_1 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2096 Pg5629 Ng2097 Pg5648 Ng2098 n4643 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2102 Pg5629 Ng2103 Pg5648 Ng2104 n4644 +10---- 0 +--10-- 0 +----10 0 +.names Ng1315 Ng2084 Pg5629 Ng2085 Pg5648 Ng2086 n4645 +10---- 0 +--10-- 0 +----10 0 +.names n4632 n4645 n4646_1 +10 1 +.names Ng1937 n4629 n4573 n4649 n4648 n4650 n4647 +0----1 0 +11001- 0 +11010- 0 +11100- 0 +11111- 0 +.names n4644 n4632 n4645 n4648 +00- 1 +0-1 1 +.names n4572 n4636 n4645 n4632 n4649 +001- 1 +00-0 1 +11-- 1 +1-01 1 +.names n4651_1 Pg3229 Ng1918 Ng1921 n4650 +10-1 1 +111- 1 +.names Ng1890 n4988_1 Ng1939 Pg1943 Ng1937 Ng1905 n4651_1 +00001- 1 +0000-1 1 +.names Ng1937 Ng1890 Ng1905 n4652 +01- 1 +0-1 1 +.names Ng1890 Ng1937 Ng1905 n4630 n4654 Ng1914 n7110 +001--1 1 +01-0-- 1 +0-10-- 1 +10--0- 1 +.names n4629 n4573 n4631 n4654 +101 1 +110 1 +.names Ng1890 Ng1937 Ng1905 n4630 n4656 Ng1913 n7105 +001--1 1 +01-0-- 1 +0-10-- 1 +10--0- 1 +.names n4629 n4572 n4634 n4646_1 n4656 +1000 1 +111- 1 +11-1 1 +.names n4658 n4660_1 n4651_1 Ng1912 n7100 +00-- 0 +0-10 0 +.names Ng1937 Ng1890 n4629 n4659 n4646_1 n4658 +100-- 1 +10-10 1 +.names Ng1315 Ng2114 Pg5629 Ng2115 Pg5648 Ng2116 n4659 +10---- 0 +--10-- 0 +----10 0 +.names Ng1890 n4629 n4635 n4573 n4652 n4660_1 +1100- 0 +1111- 0 +----0 0 +.names n4662 n4663 n4651_1 Ng1911 n7095 +10-- 0 +1-10 0 +.names Ng1937 Ng1890 Ng8302 n4630 n4646_1 n4659 n4662 +101-1- 0 +101--0 0 +10-0-- 0 +.names Ng1890 n4629 n4642_1 n4572 n4652 n4663 +1100- 0 +1111- 0 +----0 0 +.names n4652 n4665 n4662 n4651_1 Ng1910 n7090 +10-0- 1 +10--1 1 +--0-- 1 +.names Ng1890 n4629 n4643 n4573 n4665 +1100 1 +1111 1 +.names n4652 n4667 n4658 n4651_1 Ng1909 n7085 +10-0- 1 +10--1 1 +--1-- 1 +.names Ng1890 n4629 n4640 n4572 n4667 +1100 1 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n4729 Ng525 Ng510 n4737 +110 1 +.names n4740 n4737 n4739 n4734_1 Ng537 n7030 +10-0- 1 +11--1 1 +--1-- 1 +.names Ng557 Ng510 n4565 n4725 n4713 n4728 n4739 +1001-- 1 +100-1- 1 +10100- 1 +10---0 1 +.names Ng557 Ng510 Ng525 n4740 +01- 1 +0-1 1 +.names Ng510 Ng557 Ng525 n4729 n4732 Ng534 n7020 +001--1 1 +01-0-- 1 +0-10-- 1 +10--0- 1 +.names Ng510 Ng557 Ng525 n4729 n4733 Ng533 n7015 +001--1 1 +01-0-- 1 +0-10-- 1 +10--0- 1 +.names n4744 n4746_1 n4737 Ng532 n7010 +00-- 0 +0-10 0 +.names Ng557 Ng510 n4728 n4745 n4713 n4744 +100-- 1 +10-10 1 +.names Ng1315 Ng734 Pg5629 Ng735 Pg5648 Ng736 n4745 +10---- 0 +--10-- 0 +----10 0 +.names Ng510 n4728 n4716 n4565 n4740 n4746_1 +1100- 0 +1111- 0 +----0 0 +.names n4740 n4737 n4748 n4731 Ng531 n7005 +10-0- 1 +11--1 1 +--0-- 1 +.names Ng557 Ng510 Ng8284 n4729 n4713 n4745 n4748 +101-1- 0 +101--0 0 +10-0-- 0 +.names n4740 n4737 n4748 n4730_1 Ng530 n7000 +10-0- 1 +11--1 1 +--0-- 1 +.names n4740 n4737 n4744 n4712 Ng529 n6995 +10-0- 1 +11--1 1 +--1-- 1 +.names Ng2998 Ng2993 Ng13475 n4557 Pg3234 n7180_1 +0110- 1 +10-0- 1 +1-0-- 1 +----1 1 +.names Ng1315 n6490_1 Ng3108 n875 +0-1 1 +11- 1 +.names Pg5648 n6490_1 Ng3107 n870 +0-1 1 +11- 1 +.names Pg5629 n6490_1 Ng3106 n865 +0-1 1 +11- 1 +.names Ng853 Ng2392 n4813 n4810_1 n6672 n4816 n6076 +01---- 1 +1-0000 1 +.names n4770_1 n4757 n4756 +10 1 +.names n4761 n4758_1 n4767 n4766_1 n4769 n4768 n4757 +10---- 0 +--10-- 0 +----10 0 +.names Ng2195 Ng2185 n4760 n4759 n4758_1 +0011 1 +0101 1 +1010 1 +1100 1 +.names Ng2288 Pg5437 Ng2294 Ng853 Ng2291 Pg6313 n4759 +11---- 0 +--11-- 0 +----11 0 +.names Ng2279 Pg5437 Ng2285 Ng853 Ng2282 Pg6313 n4760 +11---- 0 +--11-- 0 +----11 0 +.names Ng2175 Ng2165 n4764 n4763 n4765 n4762_1 n4761 +0011-- 0 +0101-- 0 +1010-- 0 +1100-- 0 +----00 0 +----11 0 +.names Pg5437 Ng2251 Ng853 Ng2250 Pg6313 Ng2252 n4762_1 +10---- 0 +--10-- 0 +----10 0 +.names Ng2270 Pg5437 Ng2276 Ng853 Ng2273 Pg6313 n4763 +11---- 0 +--11-- 0 +----11 0 +.names Ng2261 Pg5437 Ng2267 Ng853 Ng2264 Pg6313 n4764 +11---- 0 +--11-- 0 +----11 0 +.names Ng2297 Pg5437 Ng2303 Ng853 Ng2300 Pg6313 n4765 +11---- 0 +--11-- 0 +----11 0 +.names Ng2175 n4763 n4765 n4762_1 n4766_1 +0100 1 +0111 1 +1000 1 +1011 1 +.names Ng2165 Ng2195 n4759 n4764 Ng2185 n4760 n4767 +0011-- 0 +0101-- 0 +1010-- 0 +1100-- 0 +----01 0 +----10 0 +.names Ng2195 n4759 n4765 n4762_1 n4768 +0100 1 +0111 1 +1000 1 +1011 1 +.names Ng2175 Ng2185 n4760 n4763 Ng2165 n4764 n4769 +0011-- 0 +0101-- 0 +1010-- 0 +1100-- 0 +----01 0 +----10 0 +.names Ng2257 n4771 n4770_1 +10 1 +.names Pg5437 Ng2245 Ng853 Ng2244 Pg6313 Ng2246 n4771 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng2233 Ng853 Ng2232 Pg6313 Ng2234 n4772 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng2221 Ng853 Ng2220 Pg6313 Ng2222 n4773 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng2224 Ng853 Ng2223 Pg6313 Ng2225 n4774_1 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng2218 Ng853 Ng2217 Pg6313 Ng2219 n4775 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng2209 Ng853 Ng2208 Pg6313 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Ng2180 Ng2190 n4800 n4799 n4801 +0011 1 +0101 1 +1010 1 +1100 1 +.names Ng2333 Pg5437 Ng2339 Ng853 Ng2336 Pg6313 n4802_1 +11---- 0 +--11-- 0 +----11 0 +.names n4804 n4796 Ng2180 n4799 n4794_1 n4803 +0000- 1 +0011- 1 +00--0 1 +.names Ng2200 Ng2190 n4800 n4802_1 n4804 +0011 1 +0101 1 +1010 1 +1100 1 +.names n4771 n4766_1 n4801 n4806_1 n4808 n4807 n4805 +1----- 0 +-11111 0 +.names Ng2200 n4797 n4778_1 n4802_1 n4806_1 +0001 1 +0111 1 +1000 1 +1110 1 +.names Ng2165 Ng2195 n4759 n4764 n4807 +0011 1 +0101 1 +1010 1 +1100 1 +.names Ng2170 Ng2185 n4760 n4795 n4808 +0011 1 +0101 1 +1010 1 +1100 1 +.names Pg5437 Ng2390 Ng853 Ng2392 Pg6313 Ng2391 n4809 +10---- 0 +--10-- 0 +----10 0 +.names n4809 n4756 n4811 n4805 n4812 n4810_1 +001-- 1 +00-0- 1 +00--0 1 +.names n4770_1 n4793 n4803 n4811 +11- 1 +1-1 1 +.names Ng2257 n4791 n4812 +11 1 +.names n4814 n4815_1 n4813 +10 1 +.names n4789 n4788 n4787 n4786_1 n4785 n4814 +11111 1 +.names Pg5437 Ng2478 Ng853 Ng2477 Pg6313 Ng2479 n4815_1 +10---- 0 +--10-- 0 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n4835 n4760 n4800 n4799 n4802_1 n4825_1 n4834 +100001 1 +111110 1 +.names n4791 n4792 n4809 n4764 n4763 n4795 n4835 +110000 1 +111111 1 +.names Pg6313 n4820_1 Ng2345 n4828 n4833 n5829 +0-1-- 1 +10-0- 1 +10--1 1 +.names Pg5437 n4820_1 Ng2342 n4828 n4833 n5824 +0-1-- 1 +10-0- 1 +10--1 1 +.names Ng853 n4839 n4799 n4835 Ng2321 n4828 n5744 +0---1- 1 +1000-- 1 +1011-- 1 +10---0 1 +.names n4821 n4823 n6673 Ng2180 n4824 n4839 +0--0- 1 +10--1 1 +1-1-1 1 +-100- 1 +.names Pg6313 n4839 n4799 n4835 Ng2318 n4828 n5739 +0---1- 1 +1000-- 1 +1011-- 1 +10---0 1 +.names Pg5437 n4839 n4799 n4835 Ng2315 n4828 n5734 +0---1- 1 +1000-- 1 +1011-- 1 +10---0 1 +.names Ng853 n4843_1 n4795 n4844 Ng2312 n4828 n5714 +0---1- 1 +1001-- 1 +1010-- 1 +10---0 1 +.names n4821 n4823 n6673 Ng2170 n4824 n4843_1 +0--0- 1 +10--1 1 +1-1-1 1 +-100- 1 +.names n4764 n4825_1 n4831 n4844 +00- 1 +1-0 1 +.names Pg6313 n4843_1 n4795 n4844 Ng2309 n4828 n5709 +0---1- 1 +1001-- 1 +1010-- 1 +10---0 1 +.names Pg5437 n4843_1 n4795 n4844 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Ng1539 Ng853 Ng1538 Pg6313 Ng1540 n4895 +10---- 0 +--10-- 0 +----10 0 +.names Ng2257 Ng1481 n4897_1 n4882 Ng1471 n4898 n4896 +10100- 1 +1010-0 1 +11000- 1 +1100-0 1 +.names Pg5437 Ng1524 Ng853 Ng1523 Pg6313 Ng1525 n4897_1 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng1512 Ng853 Ng1511 Pg6313 Ng1513 n4898 +10---- 0 +--10-- 0 +----10 0 +.names Ng1496 n4901 n4900 n4875 Ng1471 n4898 n4899 +00---- 0 +11---- 0 +--01-- 0 +--10-- 0 +----00 0 +.names Pg5437 Ng1542 Ng853 Ng1541 Pg6313 Ng1543 n4900 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng1533 Ng853 Ng1532 Pg6313 Ng1534 n4901 +10---- 0 +--10-- 0 +----10 0 +.names Ng1491 n4903 n4902_1 +01 1 +10 1 +.names Pg5437 Ng1530 Ng853 Ng1529 Pg6313 Ng1531 n4903 +10---- 0 +--10-- 0 +----10 0 +.names Ng1501 n4906 Ng1476 n4905 n4907_1 n4864 n4904 +00---- 0 +11---- 0 +--00-- 0 +--11-- 0 +----01 0 +----10 0 +.names Pg5437 Ng1515 Ng853 Ng1514 Pg6313 Ng1516 n4905 +10---- 0 +--10-- 0 +----10 0 +.names Pg5437 Ng1536 Ng853 Ng1535 Pg6313 Ng1537 n4906 +10---- 0 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n5086_1 n5077 n5072 n5076_1 n5084 n5081_1 n5075 +1----- 0 +-11111 0 +.names Ng125 n5070 n5066_1 n5065 n5076_1 +0100 1 +0111 1 +1000 1 +1011 1 +.names Ng121 n5080 n5079 n5078 n5077 +0100 1 +0111 1 +1000 1 +1011 1 +.names Pg5437 Ng175 Ng853 Ng174 Pg6313 Ng176 n5078 +10---- 0 +--10-- 0 +----10 0 +.names Ng222 Pg5437 Ng228 Ng853 Pg6313 Ng225 n5079 +11---- 0 +--11-- 0 +----11 0 +.names Ng213 Pg5437 Ng853 Ng219 Ng216 Pg6313 n5080 +11---- 0 +--11-- 0 +----11 0 +.names Ng105 Ng113 n5083 n5082 n5081_1 +0011 1 +0101 1 +1010 1 +1100 1 +.names Ng195 Pg5437 Ng201 Ng853 Ng198 Pg6313 n5082 +11---- 0 +--11-- 0 +----11 0 +.names Ng204 Pg5437 Ng210 Ng853 Ng207 Pg6313 n5083 +11---- 0 +--11-- 0 +----11 0 +.names Ng101 Ng97 n5085 n5069 n5084 +0011 1 +0101 1 +1010 1 +1100 1 +.names Ng186 Pg5437 Ng192 Ng853 Ng189 Pg6313 n5085 +11---- 0 +--11-- 0 +----11 0 +.names Pg5437 Ng169 Ng853 Ng168 Pg6313 Ng170 n5086_1 +10---- 0 +--10-- 0 +----10 0 +.names Ng2257 n5088 n5087 +11 1 +.names Pg5437 Ng318 Ng853 Ng320 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n5352 n5351 n5348 n4986 n5347 +00---- 1 +0-1--0 1 +0--1-0 1 +0---0- 1 +-1000- 1 +.names n5349_1 n4984 n4968 n5348 +100 1 +.names Ng809 Ng805 Ng797 Ng793 n5350 n5349_1 +11111 1 +.names Ng813 Ng801 Ng789 Ng785 n5350 +1111 1 +.names Ng1095 Pg5437 Ng1101 Ng853 Ng1098 Pg6313 n5351 +11---- 0 +--11-- 0 +----11 0 +.names Pg5437 Ng1114 Ng853 Ng1113 Pg6313 Ng1115 n5352 +10---- 0 +--10-- 0 +----10 0 +.names Pg6313 n5347 Ng1107 n2978 +0-1 1 +10- 1 +.names Pg5437 n5347 Ng1104 n2973 +0-1 1 +10- 1 +.names Ng1008 Ng2257 Ng853 n5356 n5358 n5022 n3103 +00---- 0 +0-0--- 0 +0--1-- 0 +-11010 0 +.names n5357 n4976 n5356 +00 1 +.names n5011_1 n5009 n4988 n5357 +100 1 +.names n5015 n5014 n5013 n5000 n4996 n5358 +11111 1 +.names Ng1010 Ng2257 Pg6313 n5356 n5358 n5022 n3098 +00---- 0 +0-0--- 0 +0--1-- 0 +-11010 0 +.names Ng1009 Ng2257 Pg5437 n5356 n5358 n5022 n3093 +00---- 0 +0-0--- 0 +0--1-- 0 +-11010 0 +.names Ng853 n5362 Ng423 n1483 +0-1 1 +11- 1 +.names Ng2257 n1703 n5363 n5367 n5366 n5086_1 n5362 +01---- 1 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Ng1315 Ng2658 Pg5629 Ng2659 Pg5648 Ng2660 n5412 +10---- 0 +--10-- 0 +----10 0 +.names n5409_1 n5410 n5414_1 n5407 n5412 n5415 n5413 +11-0-- 1 +11--10 1 +1-1--- 1 +.names n5415 n5411 n5408 n5406 n5407 n5414_1 +000-0 1 +1001- 1 +.names Ng2428 Ng1315 Pg5629 Ng2424 Ng2426 Pg5648 n5415 +11---- 0 +--11-- 0 +----11 0 +.names n5406 n5407 n5408 n5411 n5410 n5416 +010-0 1 +01-1- 1 +0-01- 1 +.names n5408 n5415 n5411 n5407 n5406 n5412 n5417 +100--1 1 +10-0-- 1 +11--1- 1 +1-00-- 1 +.names n5419_1 Ng2616 Ng185 n6468 n5418 +0--- 0 +-110 0 +.names Ng2676 Ng1315 Pg5629 Ng2670 Ng2673 Pg5648 n5419_1 +11---- 0 +--11-- 0 +----11 0 +.names n4577 n4556 n5420 +00 1 +.names n5426 n5424_1 n5422 n5421 +000 1 +.names n5409_1 n5423 n5415 n5407 n5406 n5410 n5422 +001--- 1 +0--111 1 +.names n5406 n5408 n5411 n5410 n5407 n5412 n5423 +0-1--- 0 +100--1 0 +-0-00- 0 +.names n5415 n5425 n5409_1 n5412 n5411 n5408 n5424_1 +001--- 1 +0--000 1 +.names n5406 n5407 n5408 n5411 n5412 n5410 n5425 +110--0 0 +1--11- 0 +-01--- 0 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+1 1 +.names Ng1235 n3496 +1 1 +.names Ng1244 n3505 +1 1 +.names Ng8293 n3644 +1 1 +.names Pg16355 n3653 +1 1 +.names Ng13475 n3708 +1 1 +.names Pg5629 n3711 +1 1 +.names Pg5648 n3714 +1 1 +.names Ng1831 n4628 +1 1 +.names Ng1833 n4637 +1 1 +.names Ng1835 n4646 +1 1 +.names Ng1661 n4655 +1 1 +.names Ng1663 n4664 +1 1 +.names Ng1665 n4673 +1 1 +.names Ng1667 n4682 +1 1 +.names Ng1669 n4691 +1 1 +.names Ng13439 n4695 +1 1 +.names Ng1671 n4699 +1 1 +.names Ng11551 n4718 +1 1 +.names Ng1723 n4722 +1 1 +.names Ng11552 n4726 +1 1 +.names Ng1731 n4730 +1 1 +.names Ng11553 n4734 +1 1 +.names Ng1733 n4738 +1 1 +.names Ng11554 n4742_1 +1 1 +.names Ng1738 n4746 +1 1 +.names Ng11555 n4750 +1 1 +.names Ng1746 n4754 +1 1 +.names Ng11556 n4758 +1 1 +.names Ng1748 n4762 +1 1 +.names Ng11557 n4766 +1 1 +.names Ng1753 n4770 +1 1 +.names Ng11558 n4774 +1 1 +.names Ng1761 n4778 +1 1 +.names Ng11559 n4782 +1 1 +.names Ng1763 n4786 +1 1 +.names Ng11560 n4790 +1 1 +.names Ng1768 n4794 +1 1 +.names Ng11561 n4798 +1 1 +.names Ng1776 n4802 +1 1 +.names Ng11562 n4806 +1 1 +.names Ng1778 n4810 +1 1 +.names Ng1893 n4834_1 +1 1 +.names Ng1903 n4838_1 +1 1 +.names Ng11566 n4843 +1 1 +.names Ng1944 n4847 +1 1 +.names Ng11569 n4852 +1 1 +.names Ng1950 n4856_1 +1 1 +.names Ng11570 n4861_1 +1 1 +.names Ng1952 n4865 +1 1 +.names Ng11571 n4870 +1 1 +.names Ng1954 n4874 +1 1 +.names Ng11567 n4879 +1 1 +.names Ng1946 n4883 +1 1 +.names Ng11568 n4888_1 +1 1 +.names Ng1948 n4892 +1 1 +.names Ng1908 n4970 +1 1 +.names Ng1915 n4974 +1 1 +.names Ng1923 n4983_1 +1 1 +.names Ng1929 n4997 +1 1 +.names Ng1938 n5006 +1 1 +.names Ng8302 n5145_1 +1 1 +.names Pg16399 n5154 +1 1 +.names Ng2256 n5893_1 +1 1 +.names Pg5549 n5896 +1 1 +.names Ng2525 n6130 +1 1 +.names Ng2527 n6139 +1 1 +.names Ng2529 n6148 +1 1 +.names Ng2355 n6157 +1 1 +.names Ng2357 n6166 +1 1 +.names Ng2359 n6175 +1 1 +.names Ng2361 n6184 +1 1 +.names Ng2363 n6193 +1 1 +.names Ng13455 n6197 +1 1 +.names Ng2365 n6201 +1 1 +.names Ng11578 n6220 +1 1 +.names Ng2417 n6224 +1 1 +.names Ng11579 n6228 +1 1 +.names Ng2425 n6232 +1 1 +.names Ng11580 n6236 +1 1 +.names Ng2427 n6240 +1 1 +.names Ng11581 n6244_1 +1 1 +.names Ng2432 n6248 +1 1 +.names Ng11582 n6252 +1 1 +.names Ng2440 n6256 +1 1 +.names Ng11583 n6260 +1 1 +.names Ng2442 n6264 +1 1 +.names Ng11584 n6268 +1 1 +.names Ng2447 n6272 +1 1 +.names Ng11585 n6276 +1 1 +.names Ng2455 n6280 +1 1 +.names Ng11586 n6284 +1 1 +.names Ng2457 n6288 +1 1 +.names Ng11587 n6292 +1 1 +.names Ng2462 n6296 +1 1 +.names Ng11588 n6300 +1 1 +.names Ng2470 n6304 +1 1 +.names Ng11589 n6308 +1 1 +.names Ng2472 n6312 +1 1 +.names Ng2587 n6336_1 +1 1 +.names Ng2597 n6340 +1 1 +.names Ng11593 n6345_1 +1 1 +.names Ng2638 n6349_1 +1 1 +.names Ng11596 n6354 +1 1 +.names Ng2644 n6358_1 +1 1 +.names Ng11597 n6363_1 +1 1 +.names Ng2646 n6367 +1 1 +.names Ng11598 n6372 +1 1 +.names Ng2648 n6376 +1 1 +.names Ng11594 n6381 +1 1 +.names Ng2640 n6385 +1 1 +.names Ng11595 n6390 +1 1 +.names Ng2642 n6394 +1 1 +.names Ng2602 n6472 +1 1 +.names Ng2609 n6476 +1 1 +.names Ng2617 n6485_1 +1 1 +.names Ng2623 n6499 +1 1 +.names Ng2632 n6508 +1 1 +.names Ng8311 n6647_1 +1 1 +.names Pg16437 n6656 +1 1 +.names Pg5388 n7229 +1 1 +.names Pg16496 n7233 +1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v b/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v new file mode 100644 index 000000000..47183130b --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v @@ -0,0 +1,10966 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module s38417(clock, Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227, Pg3226, Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218, Pg3217, Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249, Pg563, Pg51, Pg27380, Pg26149, Pg26135, Pg26104, Pg25489, Pg25442, Pg25435, Pg25420, Pg24734, Pg16496, Pg16437, Pg16399, Pg16355, Pg16297, Pg8275, Pg8274, Pg8273, Pg8272, Pg8271, Pg8270, Pg8269, Pg8268, Pg8267, Pg8266, Pg8265, Pg8264, Pg8263, Pg8262, Pg8261, Pg8260, Pg8259, Pg8258, Pg8251, Pg8249, Pg8175, Pg8167, Pg8106, Pg8096, Pg8087, Pg8082, Pg8030, Pg8023, Pg8021, Pg8012, Pg8007, Pg7961, Pg7956, Pg7909, Pg7519, Pg7487, Pg7425, Pg7390, Pg7357, Pg7334, Pg7302, Pg7264, Pg7229, Pg7194, Pg7161, Pg7084, Pg7052, Pg7014, Pg6979, Pg6944, Pg6911, Pg6895, Pg6837, Pg6782, Pg6750, Pg6712, Pg6677, Pg6642, Pg6573, Pg6518, Pg6485, Pg6447, Pg6442, Pg6368, Pg6313, Pg6231, Pg6225, Pg5796, Pg5747, Pg5738, Pg5695, Pg5686, Pg5657, Pg5648, Pg5637, Pg5629, Pg5612, Pg5595, Pg5555, Pg5549, Pg5511, Pg5472, Pg5437, Pg5388, Pg4590, Pg4450, Pg4323, Pg4321, Pg4200, Pg4090, Pg4088, Pg3993); + (* init = 1'h0 *) + reg Ng1000 = 1'h0; + (* init = 1'h0 *) + reg Ng1001 = 1'h0; + (* init = 1'h0 *) + reg Ng1002 = 1'h0; + (* init = 1'h0 *) + reg Ng1003 = 1'h0; + (* init = 1'h0 *) + reg Ng1004 = 1'h0; + (* init = 1'h0 *) + reg Ng1005 = 1'h0; + (* init = 1'h0 *) + reg Ng1006 = 1'h0; + (* init = 1'h0 *) + reg Ng1007 = 1'h0; + (* init = 1'h0 *) + reg Ng1008 = 1'h0; + (* init = 1'h0 *) + reg Ng1009 = 1'h0; + (* init = 1'h0 *) + reg Ng101 = 1'h0; + (* init = 1'h0 *) + reg Ng1010 = 1'h0; + (* init = 1'h0 *) + reg Ng1011 = 1'h0; + (* init = 1'h0 *) + reg Ng1029 = 1'h0; + (* init = 1'h0 *) + reg Ng1036 = 1'h0; + (* init = 1'h0 *) + reg Ng1037 = 1'h0; + (* init = 1'h0 *) + reg Ng1038 = 1'h0; + (* init = 1'h0 *) + reg Ng1039 = 1'h0; + (* init = 1'h0 *) + reg Ng1040 = 1'h0; + (* init = 1'h0 *) + reg Ng1044 = 1'h0; + (* init = 1'h0 *) + reg Ng105 = 1'h0; + (* init = 1'h0 *) + reg Ng1051 = 1'h0; + (* init = 1'h0 *) + reg Ng1052 = 1'h0; + (* init = 1'h0 *) + reg Ng1053 = 1'h0; + (* init = 1'h0 *) + reg Ng1054 = 1'h0; + (* init = 1'h0 *) + reg Ng1055 = 1'h0; + (* init = 1'h0 *) + reg Ng1059 = 1'h0; + (* init = 1'h0 *) + reg Ng1066 = 1'h0; + (* init = 1'h0 *) + reg Ng1067 = 1'h0; + (* init = 1'h0 *) + reg Ng1068 = 1'h0; + (* init = 1'h0 *) + reg Ng1069 = 1'h0; + (* init = 1'h0 *) + reg Ng1070 = 1'h0; + (* init = 1'h0 *) + reg Ng1074 = 1'h0; + (* init = 1'h0 *) + reg Ng1081 = 1'h0; + (* init = 1'h0 *) + reg Ng1082 = 1'h0; + (* init = 1'h0 *) + reg Ng1083 = 1'h0; + (* init = 1'h0 *) + reg Ng1084 = 1'h0; + (* init = 1'h0 *) + reg Ng1089 = 1'h0; + (* init = 1'h0 *) + reg Ng109 = 1'h0; + (* init = 1'h0 *) + reg Ng1090 = 1'h0; + (* init = 1'h0 *) + reg Ng1091 = 1'h0; + (* init = 1'h0 *) + reg Ng1095 = 1'h0; + (* init = 1'h0 *) + reg Ng1098 = 1'h0; + (* init = 1'h0 *) + reg Ng1101 = 1'h0; + (* init = 1'h0 *) + reg Ng1104 = 1'h0; + (* init = 1'h0 *) + reg Ng1107 = 1'h0; + (* init = 1'h0 *) + reg Ng1110 = 1'h0; + (* init = 1'h0 *) + reg Ng1113 = 1'h0; + (* init = 1'h0 *) + reg Ng1114 = 1'h0; + (* init = 1'h0 *) + reg Ng1115 = 1'h0; + (* init = 1'h0 *) + reg Ng1116 = 1'h0; + (* init = 1'h0 *) + reg Ng1119 = 1'h0; + (* init = 1'h0 *) + reg Ng1122 = 1'h0; + (* init = 1'h0 *) + reg Ng1125 = 1'h0; + (* init = 1'h0 *) + reg Ng1128 = 1'h0; + (* init = 1'h0 *) + reg Ng113 = 1'h0; + (* init = 1'h0 *) + reg Ng1131 = 1'h0; + (* init = 1'h0 *) + reg Ng1134 = 1'h0; + (* init = 1'h0 *) + reg Ng1135 = 1'h0; + (* init = 1'h0 *) + reg Ng1136 = 1'h0; + (* init = 1'h0 *) + reg Ng1137 = 1'h0; + (* init = 1'h0 *) + reg Ng1138 = 1'h0; + (* init = 1'h0 *) + reg Ng1139 = 1'h0; + (* init = 1'h0 *) + reg Ng1140 = 1'h0; + (* init = 1'h0 *) + reg Ng1141 = 1'h0; + (* init = 1'h0 *) + reg Ng11497 = 1'h0; + (* init = 1'h0 *) + reg Ng11498 = 1'h0; + (* init = 1'h0 *) + reg Ng11499 = 1'h0; + (* init = 1'h0 *) + reg Ng11500 = 1'h0; + (* init = 1'h0 *) + reg Ng11501 = 1'h0; + (* init = 1'h0 *) + reg Ng11502 = 1'h0; + (* init = 1'h0 *) + reg Ng11503 = 1'h0; + (* init = 1'h0 *) + reg Ng11504 = 1'h0; + (* init = 1'h0 *) + reg Ng11505 = 1'h0; + (* init = 1'h0 *) + reg Ng11506 = 1'h0; + (* init = 1'h0 *) + reg Ng11507 = 1'h0; + (* init = 1'h0 *) + reg Ng11508 = 1'h0; + (* init = 1'h0 *) + reg Ng1151 = 1'h0; + (* init = 1'h0 *) + reg Ng11512 = 1'h0; + (* init = 1'h0 *) + reg Ng11513 = 1'h0; + (* init = 1'h0 *) + reg Ng11514 = 1'h0; + (* init = 1'h0 *) + reg Ng11515 = 1'h0; + (* init = 1'h0 *) + reg Ng11516 = 1'h0; + (* init = 1'h0 *) + reg Ng11517 = 1'h0; + (* init = 1'h0 *) + reg Ng11524 = 1'h0; + (* init = 1'h0 *) + reg Ng11525 = 1'h0; + (* init = 1'h0 *) + reg Ng11526 = 1'h0; + (* init = 1'h0 *) + reg Ng11527 = 1'h0; + (* init = 1'h0 *) + reg Ng11528 = 1'h0; + (* init = 1'h0 *) + reg Ng11529 = 1'h0; + (* init = 1'h0 *) + reg Ng11530 = 1'h0; + (* init = 1'h0 *) + reg Ng11531 = 1'h0; + (* init = 1'h0 *) + reg Ng11532 = 1'h0; + (* init = 1'h0 *) + reg Ng11533 = 1'h0; + (* init = 1'h0 *) + reg Ng11534 = 1'h0; + (* init = 1'h0 *) + reg Ng11535 = 1'h0; + (* init = 1'h0 *) + reg Ng11539 = 1'h0; + (* init = 1'h0 *) + reg Ng11540 = 1'h0; + (* init = 1'h0 *) + reg Ng11541 = 1'h0; + (* init = 1'h0 *) + reg Ng11542 = 1'h0; + (* init = 1'h0 *) + reg Ng11543 = 1'h0; + (* init = 1'h0 *) + reg Ng11544 = 1'h0; + (* init = 1'h0 *) + reg Ng11551 = 1'h0; + (* init = 1'h0 *) + reg Ng11552 = 1'h0; + (* init = 1'h0 *) + reg Ng11553 = 1'h0; + (* init = 1'h0 *) + reg Ng11554 = 1'h0; + (* init = 1'h0 *) + reg Ng11555 = 1'h0; + (* init = 1'h0 *) + reg Ng11556 = 1'h0; + (* init = 1'h0 *) + reg Ng11557 = 1'h0; + (* init = 1'h0 *) + reg Ng11558 = 1'h0; + (* init = 1'h0 *) + reg Ng11559 = 1'h0; + (* init = 1'h0 *) + reg Ng11560 = 1'h0; + (* init = 1'h0 *) + reg Ng11561 = 1'h0; + (* init = 1'h0 *) + reg Ng11562 = 1'h0; + (* init = 1'h0 *) + reg Ng11566 = 1'h0; + (* init = 1'h0 *) + reg Ng11567 = 1'h0; + (* init = 1'h0 *) + reg Ng11568 = 1'h0; + (* init = 1'h0 *) + reg Ng11569 = 1'h0; + (* init = 1'h0 *) + reg Ng11570 = 1'h0; + (* init = 1'h0 *) + reg Ng11571 = 1'h0; + (* init = 1'h0 *) + reg Ng11578 = 1'h0; + (* init = 1'h0 *) + reg Ng11579 = 1'h0; + (* init = 1'h0 *) + reg Ng11580 = 1'h0; + (* init = 1'h0 *) + reg Ng11581 = 1'h0; + (* init = 1'h0 *) + reg Ng11582 = 1'h0; + (* init = 1'h0 *) + reg Ng11583 = 1'h0; + (* init = 1'h0 *) + reg Ng11584 = 1'h0; + (* init = 1'h0 *) + reg Ng11585 = 1'h0; + (* init = 1'h0 *) + reg Ng11586 = 1'h0; + (* init = 1'h0 *) + reg Ng11587 = 1'h0; + (* init = 1'h0 *) + reg Ng11588 = 1'h0; + (* init = 1'h0 *) + reg Ng11589 = 1'h0; + (* init = 1'h0 *) + reg Ng11593 = 1'h0; + (* init = 1'h0 *) + reg Ng11594 = 1'h0; + (* init = 1'h0 *) + reg Ng11595 = 1'h0; + (* init = 1'h0 *) + reg Ng11596 = 1'h0; + (* init = 1'h0 *) + reg Ng11597 = 1'h0; + (* init = 1'h0 *) + reg Ng11598 = 1'h0; + (* init = 1'h0 *) + reg Ng1164 = 1'h0; + (* init = 1'h0 *) + reg Ng1165 = 1'h0; + (* init = 1'h0 *) + reg Ng1166 = 1'h0; + (* init = 1'h0 *) + reg Ng1167 = 1'h0; + (* init = 1'h0 *) + reg Ng117 = 1'h0; + (* init = 1'h0 *) + reg Ng1171 = 1'h0; + (* init = 1'h0 *) + reg Ng1173 = 1'h0; + (* init = 1'h0 *) + reg Ng1174 = 1'h0; + (* init = 1'h0 *) + reg Ng1175 = 1'h0; + (* init = 1'h0 *) + reg Ng1176 = 1'h0; + (* init = 1'h0 *) + reg Ng1177 = 1'h0; + (* init = 1'h0 *) + reg Ng1180 = 1'h0; + (* init = 1'h0 *) + reg Ng1183 = 1'h0; + (* init = 1'h0 *) + reg Ng1192 = 1'h0; + (* init = 1'h0 *) + reg Ng1193 = 1'h0; + (* init = 1'h0 *) + reg Ng1196 = 1'h0; + (* init = 1'h0 *) + reg Ng1199 = 1'h0; + (* init = 1'h0 *) + reg Ng1209 = 1'h0; + (* init = 1'h0 *) + reg Ng121 = 1'h0; + (* init = 1'h0 *) + reg Ng1210 = 1'h0; + (* init = 1'h0 *) + reg Ng1211 = 1'h0; + (* init = 1'h0 *) + reg Ng1214 = 1'h0; + (* init = 1'h0 *) + reg Ng1215 = 1'h0; + (* init = 1'h0 *) + reg Ng1216 = 1'h0; + (* init = 1'h0 *) + reg Ng1217 = 1'h0; + (* init = 1'h0 *) + reg Ng1218 = 1'h0; + (* init = 1'h0 *) + reg Ng1219 = 1'h0; + (* init = 1'h0 *) + reg Ng1220 = 1'h0; + (* init = 1'h0 *) + reg Ng1221 = 1'h0; + (* init = 1'h0 *) + reg Ng1222 = 1'h0; + (* init = 1'h0 *) + reg Ng1223 = 1'h0; + (* init = 1'h0 *) + reg Ng1224 = 1'h0; + (* init = 1'h0 *) + reg Ng1227 = 1'h0; + (* init = 1'h0 *) + reg Ng1228 = 1'h0; + (* init = 1'h0 *) + reg Ng1229 = 1'h0; + (* init = 1'h0 *) + reg Ng1230 = 1'h0; + (* init = 1'h0 *) + reg Ng1234 = 1'h0; + (* init = 1'h0 *) + reg Ng1235 = 1'h0; + (* init = 1'h0 *) + reg Ng1240 = 1'h0; + (* init = 1'h0 *) + reg Ng1243 = 1'h0; + (* init = 1'h0 *) + reg Ng1244 = 1'h0; + (* init = 1'h0 *) + reg Ng1245 = 1'h0; + (* init = 1'h0 *) + reg Ng125 = 1'h0; + (* init = 1'h0 *) + reg Ng1250 = 1'h0; + (* init = 1'h0 *) + reg Ng1251 = 1'h0; + (* init = 1'h0 *) + reg Ng1252 = 1'h0; + (* init = 1'h0 *) + reg Ng1253 = 1'h0; + (* init = 1'h0 *) + reg Ng1254 = 1'h0; + (* init = 1'h0 *) + reg Ng1255 = 1'h0; + (* init = 1'h0 *) + reg Ng1256 = 1'h0; + (* init = 1'h0 *) + reg Ng1257 = 1'h0; + (* init = 1'h0 *) + reg Ng1258 = 1'h0; + (* init = 1'h0 *) + reg Ng1259 = 1'h0; + (* init = 1'h0 *) + reg Ng1260 = 1'h0; + (* init = 1'h0 *) + reg Ng1261 = 1'h0; + (* init = 1'h0 *) + reg Ng1262 = 1'h0; + (* init = 1'h0 *) + reg Ng1263 = 1'h0; + (* init = 1'h0 *) + reg Ng1264 = 1'h0; + (* init = 1'h0 *) + reg Ng1265 = 1'h0; + (* init = 1'h0 *) + reg Ng1266 = 1'h0; + (* init = 1'h0 *) + reg Ng1267 = 1'h0; + (* init = 1'h0 *) + reg Ng1268 = 1'h0; + (* init = 1'h0 *) + reg Ng1269 = 1'h0; + (* init = 1'h0 *) + reg Ng1270 = 1'h0; + (* init = 1'h0 *) + reg Ng1271 = 1'h0; + (* init = 1'h0 *) + reg Ng1272 = 1'h0; + (* init = 1'h0 *) + reg Ng1273 = 1'h0; + (* init = 1'h0 *) + reg Ng1276 = 1'h0; + (* init = 1'h0 *) + reg Ng1279 = 1'h0; + (* init = 1'h0 *) + reg Ng1282 = 1'h0; + (* init = 1'h0 *) + reg Ng1285 = 1'h0; + (* init = 1'h0 *) + reg Ng1288 = 1'h0; + (* init = 1'h0 *) + reg Ng129 = 1'h0; + (* init = 1'h0 *) + reg Ng1291 = 1'h0; + (* init = 1'h0 *) + reg Ng1294 = 1'h0; + (* init = 1'h0 *) + reg Ng1297 = 1'h0; + (* init = 1'h0 *) + reg Ng130 = 1'h0; + (* init = 1'h0 *) + reg Ng1300 = 1'h0; + (* init = 1'h0 *) + reg Ng1303 = 1'h0; + (* init = 1'h0 *) + reg Ng1306 = 1'h0; + (* init = 1'h0 *) + reg Ng131 = 1'h0; + (* init = 1'h0 *) + reg Ng1315 = 1'h0; + (* init = 1'h0 *) + reg Ng1316 = 1'h0; + (* init = 1'h0 *) + reg Ng1319 = 1'h0; + (* init = 1'h0 *) + reg Ng132 = 1'h0; + (* init = 1'h0 *) + reg Ng1326 = 1'h0; + (* init = 1'h0 *) + reg Ng133 = 1'h0; + (* init = 1'h0 *) + reg Ng1332 = 1'h0; + (* init = 1'h0 *) + reg Ng1339 = 1'h0; + (* init = 1'h0 *) + reg Ng134 = 1'h0; + (* init = 1'h0 *) + reg Ng13407 = 1'h0; + (* init = 1'h0 *) + reg Ng13423 = 1'h0; + (* init = 1'h0 *) + reg Ng13439 = 1'h0; + (* init = 1'h0 *) + reg Ng1345 = 1'h0; + (* init = 1'h0 *) + reg Ng13455 = 1'h0; + (* init = 1'h0 *) + reg Ng13457 = 1'h0; + (* init = 1'h0 *) + reg Ng1346 = 1'h0; + (* init = 1'h0 *) + reg Ng13475 = 1'h0; + (* init = 1'h0 *) + reg Ng1352 = 1'h0; + (* init = 1'h0 *) + reg Ng1358 = 1'h0; + (* init = 1'h0 *) + reg Ng1365 = 1'h0; + (* init = 1'h0 *) + reg Ng1372 = 1'h0; + (* init = 1'h0 *) + reg Ng1378 = 1'h0; + (* init = 1'h0 *) + reg Ng1384 = 1'h0; + (* init = 1'h0 *) + reg Ng1385 = 1'h0; + (* init = 1'h0 *) + reg Ng1386 = 1'h0; + (* init = 1'h0 *) + reg Ng1387 = 1'h0; + (* init = 1'h0 *) + reg Ng1388 = 1'h0; + (* init = 1'h0 *) + reg Ng1389 = 1'h0; + (* init = 1'h0 *) + reg Ng1390 = 1'h0; + (* init = 1'h0 *) + reg Ng1391 = 1'h0; + (* init = 1'h0 *) + reg Ng1392 = 1'h0; + (* init = 1'h0 *) + reg Ng1393 = 1'h0; + (* init = 1'h0 *) + reg Ng1394 = 1'h0; + (* init = 1'h0 *) + reg Ng1395 = 1'h0; + (* init = 1'h0 *) + reg Ng1396 = 1'h0; + (* init = 1'h0 *) + reg Ng1397 = 1'h0; + (* init = 1'h0 *) + reg Ng1398 = 1'h0; + (* init = 1'h0 *) + reg Ng1399 = 1'h0; + (* init = 1'h0 *) + reg Ng1400 = 1'h0; + (* init = 1'h0 *) + reg Ng1401 = 1'h0; + (* init = 1'h0 *) + reg Ng1402 = 1'h0; + (* init = 1'h0 *) + reg Ng1403 = 1'h0; + (* init = 1'h0 *) + reg Ng1404 = 1'h0; + (* init = 1'h0 *) + reg Ng1405 = 1'h0; + (* init = 1'h0 *) + reg Ng1406 = 1'h0; + (* init = 1'h0 *) + reg Ng1407 = 1'h0; + (* init = 1'h0 *) + reg Ng1408 = 1'h0; + (* init = 1'h0 *) + reg Ng1409 = 1'h0; + (* init = 1'h0 *) + reg Ng141 = 1'h0; + (* init = 1'h0 *) + reg Ng1410 = 1'h0; + (* init = 1'h0 *) + reg Ng1411 = 1'h0; + (* init = 1'h0 *) + reg Ng1412 = 1'h0; + (* init = 1'h0 *) + reg Ng1413 = 1'h0; + (* init = 1'h0 *) + reg Ng1414 = 1'h0; + (* init = 1'h0 *) + reg Ng1415 = 1'h0; + (* init = 1'h0 *) + reg Ng1416 = 1'h0; + (* init = 1'h0 *) + reg Ng1417 = 1'h0; + (* init = 1'h0 *) + reg Ng1418 = 1'h0; + (* init = 1'h0 *) + reg Ng1419 = 1'h0; + (* init = 1'h0 *) + reg Ng142 = 1'h0; + (* init = 1'h0 *) + reg Ng1420 = 1'h0; + (* init = 1'h0 *) + reg Ng1421 = 1'h0; + (* init = 1'h0 *) + reg Ng1422 = 1'h0; + (* init = 1'h0 *) + reg Ng1423 = 1'h0; + (* init = 1'h0 *) + reg Ng1424 = 1'h0; + (* init = 1'h0 *) + reg Ng1425 = 1'h0; + (* init = 1'h0 *) + reg Ng1426 = 1'h0; + (* init = 1'h0 *) + reg Ng143 = 1'h0; + (* init = 1'h0 *) + reg Ng1430 = 1'h0; + (* init = 1'h0 *) + reg Ng1435 = 1'h0; + (* init = 1'h0 *) + reg Ng1439 = 1'h0; + (* init = 1'h0 *) + reg Ng144 = 1'h0; + (* init = 1'h0 *) + reg Ng1444 = 1'h0; + (* init = 1'h0 *) + reg Ng1448 = 1'h0; + (* init = 1'h0 *) + reg Ng145 = 1'h0; + (* init = 1'h0 *) + reg Ng1453 = 1'h0; + (* init = 1'h0 *) + reg Ng1457 = 1'h0; + (* init = 1'h0 *) + reg Ng146 = 1'h0; + (* init = 1'h0 *) + reg Ng1462 = 1'h0; + (* init = 1'h0 *) + reg Ng1466 = 1'h0; + (* init = 1'h0 *) + reg Ng147 = 1'h0; + (* init = 1'h0 *) + reg Ng1471 = 1'h0; + (* init = 1'h0 *) + reg Ng1476 = 1'h0; + (* init = 1'h0 *) + reg Ng148 = 1'h0; + (* init = 1'h0 *) + reg Ng1481 = 1'h0; + (* init = 1'h0 *) + reg Ng1486 = 1'h0; + (* init = 1'h0 *) + reg Ng149 = 1'h0; + (* init = 1'h0 *) + reg Ng1491 = 1'h0; + (* init = 1'h0 *) + reg Ng1496 = 1'h0; + (* init = 1'h0 *) + reg Ng150 = 1'h0; + (* init = 1'h0 *) + reg Ng1501 = 1'h0; + (* init = 1'h0 *) + reg Ng1506 = 1'h0; + (* init = 1'h0 *) + reg Ng151 = 1'h0; + (* init = 1'h0 *) + reg Ng1511 = 1'h0; + (* init = 1'h0 *) + reg Ng1512 = 1'h0; + (* init = 1'h0 *) + reg Ng1513 = 1'h0; + (* init = 1'h0 *) + reg Ng1514 = 1'h0; + (* init = 1'h0 *) + reg Ng1515 = 1'h0; + (* init = 1'h0 *) + reg Ng1516 = 1'h0; + (* init = 1'h0 *) + reg Ng152 = 1'h0; + (* init = 1'h0 *) + reg Ng1523 = 1'h0; + (* init = 1'h0 *) + reg Ng1524 = 1'h0; + (* init = 1'h0 *) + reg Ng1525 = 1'h0; + (* init = 1'h0 *) + reg Ng1526 = 1'h0; + (* init = 1'h0 *) + reg Ng1527 = 1'h0; + (* init = 1'h0 *) + reg Ng1528 = 1'h0; + (* init = 1'h0 *) + reg Ng1529 = 1'h0; + (* init = 1'h0 *) + reg Ng153 = 1'h0; + (* init = 1'h0 *) + reg Ng1530 = 1'h0; + (* init = 1'h0 *) + reg Ng1531 = 1'h0; + (* init = 1'h0 *) + reg Ng1532 = 1'h0; + (* init = 1'h0 *) + reg Ng1533 = 1'h0; + (* init = 1'h0 *) + reg Ng1534 = 1'h0; + (* init = 1'h0 *) + reg Ng1535 = 1'h0; + (* init = 1'h0 *) + reg Ng1536 = 1'h0; + (* init = 1'h0 *) + reg Ng1537 = 1'h0; + (* init = 1'h0 *) + reg Ng1538 = 1'h0; + (* init = 1'h0 *) + reg Ng1539 = 1'h0; + (* init = 1'h0 *) + reg Ng154 = 1'h0; + (* init = 1'h0 *) + reg Ng1540 = 1'h0; + (* init = 1'h0 *) + reg Ng1541 = 1'h0; + (* init = 1'h0 *) + reg Ng1542 = 1'h0; + (* init = 1'h0 *) + reg Ng1543 = 1'h0; + (* init = 1'h0 *) + reg Ng1544 = 1'h0; + (* init = 1'h0 *) + reg Ng1545 = 1'h0; + (* init = 1'h0 *) + reg Ng1546 = 1'h0; + (* init = 1'h0 *) + reg Ng155 = 1'h0; + (* init = 1'h0 *) + reg Ng1550 = 1'h0; + (* init = 1'h0 *) + reg Ng1551 = 1'h0; + (* init = 1'h0 *) + reg Ng1552 = 1'h0; + (* init = 1'h0 *) + reg Ng1553 = 1'h0; + (* init = 1'h0 *) + reg Ng1554 = 1'h0; + (* init = 1'h0 *) + reg Ng1555 = 1'h0; + (* init = 1'h0 *) + reg Ng1556 = 1'h0; + (* init = 1'h0 *) + reg Ng1557 = 1'h0; + (* init = 1'h0 *) + reg Ng1558 = 1'h0; + (* init = 1'h0 *) + reg Ng1559 = 1'h0; + (* init = 1'h0 *) + reg Ng156 = 1'h0; + (* init = 1'h0 *) + reg Ng1560 = 1'h0; + (* init = 1'h0 *) + reg Ng1561 = 1'h0; + (* init = 1'h0 *) + reg Ng1567 = 1'h0; + (* init = 1'h0 *) + reg Ng157 = 1'h0; + (* init = 1'h0 *) + reg Ng1570 = 1'h0; + (* init = 1'h0 *) + reg Ng1573 = 1'h0; + (* init = 1'h0 *) + reg Ng1576 = 1'h0; + (* init = 1'h0 *) + reg Ng1579 = 1'h0; + (* init = 1'h0 *) + reg Ng158 = 1'h0; + (* init = 1'h0 *) + reg Ng1582 = 1'h0; + (* init = 1'h0 *) + reg Ng1585 = 1'h0; + (* init = 1'h0 *) + reg Ng1588 = 1'h0; + (* init = 1'h0 *) + reg Ng159 = 1'h0; + (* init = 1'h0 *) + reg Ng1591 = 1'h0; + (* init = 1'h0 *) + reg Ng1594 = 1'h0; + (* init = 1'h0 *) + reg Ng1597 = 1'h0; + (* init = 1'h0 *) + reg Ng160 = 1'h0; + (* init = 1'h0 *) + reg Ng1600 = 1'h0; + (* init = 1'h0 *) + reg Ng1603 = 1'h0; + (* init = 1'h0 *) + reg Ng1606 = 1'h0; + (* init = 1'h0 *) + reg Ng1609 = 1'h0; + (* init = 1'h0 *) + reg Ng161 = 1'h0; + (* init = 1'h0 *) + reg Ng1612 = 1'h0; + (* init = 1'h0 *) + reg Ng1615 = 1'h0; + (* init = 1'h0 *) + reg Ng1618 = 1'h0; + (* init = 1'h0 *) + reg Ng162 = 1'h0; + (* init = 1'h0 *) + reg Ng1621 = 1'h0; + (* init = 1'h0 *) + reg Ng1624 = 1'h0; + (* init = 1'h0 *) + reg Ng1627 = 1'h0; + (* init = 1'h0 *) + reg Ng163 = 1'h0; + (* init = 1'h0 *) + reg Ng1630 = 1'h0; + (* init = 1'h0 *) + reg Ng1633 = 1'h0; + (* init = 1'h0 *) + reg Ng1636 = 1'h0; + (* init = 1'h0 *) + reg Ng1639 = 1'h0; + (* init = 1'h0 *) + reg Ng164 = 1'h0; + (* init = 1'h0 *) + reg Ng1642 = 1'h0; + (* init = 1'h0 *) + reg Ng1645 = 1'h0; + (* init = 1'h0 *) + reg Ng1648 = 1'h0; + (* init = 1'h0 *) + reg Ng1651 = 1'h0; + (* init = 1'h0 *) + reg Ng1654 = 1'h0; + (* init = 1'h0 *) + reg Ng1660 = 1'h0; + (* init = 1'h0 *) + reg Ng1661 = 1'h0; + (* init = 1'h0 *) + reg Ng1662 = 1'h0; + (* init = 1'h0 *) + reg Ng1663 = 1'h0; + (* init = 1'h0 *) + reg Ng1664 = 1'h0; + (* init = 1'h0 *) + reg Ng1665 = 1'h0; + (* init = 1'h0 *) + reg Ng1666 = 1'h0; + (* init = 1'h0 *) + reg Ng1667 = 1'h0; + (* init = 1'h0 *) + reg Ng1668 = 1'h0; + (* init = 1'h0 *) + reg Ng1669 = 1'h0; + (* init = 1'h0 *) + reg Ng1670 = 1'h0; + (* init = 1'h0 *) + reg Ng1671 = 1'h0; + (* init = 1'h0 *) + reg Ng1672 = 1'h0; + (* init = 1'h0 *) + reg Ng1679 = 1'h0; + (* init = 1'h0 *) + reg Ng168 = 1'h0; + (* init = 1'h0 *) + reg Ng1680 = 1'h0; + (* init = 1'h0 *) + reg Ng1686 = 1'h0; + (* init = 1'h0 *) + reg Ng169 = 1'h0; + (* init = 1'h0 *) + reg Ng1693 = 1'h0; + (* init = 1'h0 *) + reg Ng1694 = 1'h0; + (* init = 1'h0 *) + reg Ng1695 = 1'h0; + (* init = 1'h0 *) + reg Ng1696 = 1'h0; + (* init = 1'h0 *) + reg Ng1697 = 1'h0; + (* init = 1'h0 *) + reg Ng1698 = 1'h0; + (* init = 1'h0 *) + reg Ng1699 = 1'h0; + (* init = 1'h0 *) + reg Ng170 = 1'h0; + (* init = 1'h0 *) + reg Ng1700 = 1'h0; + (* init = 1'h0 *) + reg Ng1701 = 1'h0; + (* init = 1'h0 *) + reg Ng1702 = 1'h0; + (* init = 1'h0 *) + reg Ng1703 = 1'h0; + (* init = 1'h0 *) + reg Ng1704 = 1'h0; + (* init = 1'h0 *) + reg Ng1705 = 1'h0; + (* init = 1'h0 *) + reg Ng171 = 1'h0; + (* init = 1'h0 *) + reg Ng172 = 1'h0; + (* init = 1'h0 *) + reg Ng1723 = 1'h0; + (* init = 1'h0 *) + reg Ng173 = 1'h0; + (* init = 1'h0 *) + reg Ng1730 = 1'h0; + (* init = 1'h0 *) + reg Ng1731 = 1'h0; + (* init = 1'h0 *) + reg Ng1732 = 1'h0; + (* init = 1'h0 *) + reg Ng1733 = 1'h0; + (* init = 1'h0 *) + reg Ng1734 = 1'h0; + (* init = 1'h0 *) + reg Ng1738 = 1'h0; + (* init = 1'h0 *) + reg Ng174 = 1'h0; + (* init = 1'h0 *) + reg Ng1745 = 1'h0; + (* init = 1'h0 *) + reg Ng1746 = 1'h0; + (* init = 1'h0 *) + reg Ng1747 = 1'h0; + (* init = 1'h0 *) + reg Ng1748 = 1'h0; + (* init = 1'h0 *) + reg Ng1749 = 1'h0; + (* init = 1'h0 *) + reg Ng175 = 1'h0; + (* init = 1'h0 *) + reg Ng1753 = 1'h0; + (* init = 1'h0 *) + reg Ng176 = 1'h0; + (* init = 1'h0 *) + reg Ng1760 = 1'h0; + (* init = 1'h0 *) + reg Ng1761 = 1'h0; + (* init = 1'h0 *) + reg Ng1762 = 1'h0; + (* init = 1'h0 *) + reg Ng1763 = 1'h0; + (* init = 1'h0 *) + reg Ng1764 = 1'h0; + (* init = 1'h0 *) + reg Ng1768 = 1'h0; + (* init = 1'h0 *) + reg Ng177 = 1'h0; + (* init = 1'h0 *) + reg Ng1775 = 1'h0; + (* init = 1'h0 *) + reg Ng1776 = 1'h0; + (* init = 1'h0 *) + reg Ng1777 = 1'h0; + (* init = 1'h0 *) + reg Ng1778 = 1'h0; + (* init = 1'h0 *) + reg Ng178 = 1'h0; + (* init = 1'h0 *) + reg Ng1783 = 1'h0; + (* init = 1'h0 *) + reg Ng1784 = 1'h0; + (* init = 1'h0 *) + reg Ng1785 = 1'h0; + (* init = 1'h0 *) + reg Ng1789 = 1'h0; + (* init = 1'h0 *) + reg Ng179 = 1'h0; + (* init = 1'h0 *) + reg Ng1792 = 1'h0; + (* init = 1'h0 *) + reg Ng1795 = 1'h0; + (* init = 1'h0 *) + reg Ng1798 = 1'h0; + (* init = 1'h0 *) + reg Ng1801 = 1'h0; + (* init = 1'h0 *) + reg Ng1804 = 1'h0; + (* init = 1'h0 *) + reg Ng1807 = 1'h0; + (* init = 1'h0 *) + reg Ng1808 = 1'h0; + (* init = 1'h0 *) + reg Ng1809 = 1'h0; + (* init = 1'h0 *) + reg Ng1810 = 1'h0; + (* init = 1'h0 *) + reg Ng1813 = 1'h0; + (* init = 1'h0 *) + reg Ng1816 = 1'h0; + (* init = 1'h0 *) + reg Ng1819 = 1'h0; + (* init = 1'h0 *) + reg Ng1822 = 1'h0; + (* init = 1'h0 *) + reg Ng1825 = 1'h0; + (* init = 1'h0 *) + reg Ng1828 = 1'h0; + (* init = 1'h0 *) + reg Ng1829 = 1'h0; + (* init = 1'h0 *) + reg Ng1830 = 1'h0; + (* init = 1'h0 *) + reg Ng1831 = 1'h0; + (* init = 1'h0 *) + reg Ng1832 = 1'h0; + (* init = 1'h0 *) + reg Ng1833 = 1'h0; + (* init = 1'h0 *) + reg Ng1834 = 1'h0; + (* init = 1'h0 *) + reg Ng1835 = 1'h0; + (* init = 1'h0 *) + reg Ng1845 = 1'h0; + (* init = 1'h0 *) + reg Ng185 = 1'h0; + (* init = 1'h0 *) + reg Ng1858 = 1'h0; + (* init = 1'h0 *) + reg Ng1859 = 1'h0; + (* init = 1'h0 *) + reg Ng186 = 1'h0; + (* init = 1'h0 *) + reg Ng1860 = 1'h0; + (* init = 1'h0 *) + reg Ng1861 = 1'h0; + (* init = 1'h0 *) + reg Ng1865 = 1'h0; + (* init = 1'h0 *) + reg Ng1867 = 1'h0; + (* init = 1'h0 *) + reg Ng1868 = 1'h0; + (* init = 1'h0 *) + reg Ng1869 = 1'h0; + (* init = 1'h0 *) + reg Ng1870 = 1'h0; + (* init = 1'h0 *) + reg Ng1871 = 1'h0; + (* init = 1'h0 *) + reg Ng1874 = 1'h0; + (* init = 1'h0 *) + reg Ng1877 = 1'h0; + (* init = 1'h0 *) + reg Ng1886 = 1'h0; + (* init = 1'h0 *) + reg Ng1887 = 1'h0; + (* init = 1'h0 *) + reg Ng189 = 1'h0; + (* init = 1'h0 *) + reg Ng1890 = 1'h0; + (* init = 1'h0 *) + reg Ng1893 = 1'h0; + (* init = 1'h0 *) + reg Ng1903 = 1'h0; + (* init = 1'h0 *) + reg Ng1904 = 1'h0; + (* init = 1'h0 *) + reg Ng1905 = 1'h0; + (* init = 1'h0 *) + reg Ng1908 = 1'h0; + (* init = 1'h0 *) + reg Ng1909 = 1'h0; + (* init = 1'h0 *) + reg Ng1910 = 1'h0; + (* init = 1'h0 *) + reg Ng1911 = 1'h0; + (* init = 1'h0 *) + reg Ng1912 = 1'h0; + (* init = 1'h0 *) + reg Ng1913 = 1'h0; + (* init = 1'h0 *) + reg Ng1914 = 1'h0; + (* init = 1'h0 *) + reg Ng1915 = 1'h0; + (* init = 1'h0 *) + reg Ng1916 = 1'h0; + (* init = 1'h0 *) + reg Ng1917 = 1'h0; + (* init = 1'h0 *) + reg Ng1918 = 1'h0; + (* init = 1'h0 *) + reg Ng192 = 1'h0; + (* init = 1'h0 *) + reg Ng1921 = 1'h0; + (* init = 1'h0 *) + reg Ng1922 = 1'h0; + (* init = 1'h0 *) + reg Ng1923 = 1'h0; + (* init = 1'h0 *) + reg Ng1924 = 1'h0; + (* init = 1'h0 *) + reg Ng1928 = 1'h0; + (* init = 1'h0 *) + reg Ng1929 = 1'h0; + (* init = 1'h0 *) + reg Ng1934 = 1'h0; + (* init = 1'h0 *) + reg Ng1937 = 1'h0; + (* init = 1'h0 *) + reg Ng1938 = 1'h0; + (* init = 1'h0 *) + reg Ng1939 = 1'h0; + (* init = 1'h0 *) + reg Ng1944 = 1'h0; + (* init = 1'h0 *) + reg Ng1945 = 1'h0; + (* init = 1'h0 *) + reg Ng1946 = 1'h0; + (* init = 1'h0 *) + reg Ng1947 = 1'h0; + (* init = 1'h0 *) + reg Ng1948 = 1'h0; + (* init = 1'h0 *) + reg Ng1949 = 1'h0; + (* init = 1'h0 *) + reg Ng195 = 1'h0; + (* init = 1'h0 *) + reg Ng1950 = 1'h0; + (* init = 1'h0 *) + reg Ng1951 = 1'h0; + (* init = 1'h0 *) + reg Ng1952 = 1'h0; + (* init = 1'h0 *) + reg Ng1953 = 1'h0; + (* init = 1'h0 *) + reg Ng1954 = 1'h0; + (* init = 1'h0 *) + reg Ng1955 = 1'h0; + (* init = 1'h0 *) + reg Ng1956 = 1'h0; + (* init = 1'h0 *) + reg Ng1957 = 1'h0; + (* init = 1'h0 *) + reg Ng1958 = 1'h0; + (* init = 1'h0 *) + reg Ng1959 = 1'h0; + (* init = 1'h0 *) + reg Ng1960 = 1'h0; + (* init = 1'h0 *) + reg Ng1961 = 1'h0; + (* init = 1'h0 *) + reg Ng1962 = 1'h0; + (* init = 1'h0 *) + reg Ng1963 = 1'h0; + (* init = 1'h0 *) + reg Ng1964 = 1'h0; + (* init = 1'h0 *) + reg Ng1965 = 1'h0; + (* init = 1'h0 *) + reg Ng1966 = 1'h0; + (* init = 1'h0 *) + reg Ng1967 = 1'h0; + (* init = 1'h0 *) + reg Ng1970 = 1'h0; + (* init = 1'h0 *) + reg Ng1973 = 1'h0; + (* init = 1'h0 *) + reg Ng1976 = 1'h0; + (* init = 1'h0 *) + reg Ng1979 = 1'h0; + (* init = 1'h0 *) + reg Ng198 = 1'h0; + (* init = 1'h0 *) + reg Ng1982 = 1'h0; + (* init = 1'h0 *) + reg Ng1985 = 1'h0; + (* init = 1'h0 *) + reg Ng1988 = 1'h0; + (* init = 1'h0 *) + reg Ng1991 = 1'h0; + (* init = 1'h0 *) + reg Ng1994 = 1'h0; + (* init = 1'h0 *) + reg Ng1997 = 1'h0; + (* init = 1'h0 *) + reg Ng2000 = 1'h0; + (* init = 1'h0 *) + reg Ng201 = 1'h0; + (* init = 1'h0 *) + reg Ng2010 = 1'h0; + (* init = 1'h0 *) + reg Ng2013 = 1'h0; + (* init = 1'h0 *) + reg Ng2020 = 1'h0; + (* init = 1'h0 *) + reg Ng2026 = 1'h0; + (* init = 1'h0 *) + reg Ng2033 = 1'h0; + (* init = 1'h0 *) + reg Ng2039 = 1'h0; + (* init = 1'h0 *) + reg Ng204 = 1'h0; + (* init = 1'h0 *) + reg Ng2040 = 1'h0; + (* init = 1'h0 *) + reg Ng2046 = 1'h0; + (* init = 1'h0 *) + reg Ng2052 = 1'h0; + (* init = 1'h0 *) + reg Ng2059 = 1'h0; + (* init = 1'h0 *) + reg Ng2066 = 1'h0; + (* init = 1'h0 *) + reg Ng207 = 1'h0; + (* init = 1'h0 *) + reg Ng2072 = 1'h0; + (* init = 1'h0 *) + reg Ng2078 = 1'h0; + (* init = 1'h0 *) + reg Ng2079 = 1'h0; + (* init = 1'h0 *) + reg Ng2080 = 1'h0; + (* init = 1'h0 *) + reg Ng2081 = 1'h0; + (* init = 1'h0 *) + reg Ng2082 = 1'h0; + (* init = 1'h0 *) + reg Ng2083 = 1'h0; + (* init = 1'h0 *) + reg Ng2084 = 1'h0; + (* init = 1'h0 *) + reg Ng2085 = 1'h0; + (* init = 1'h0 *) + reg Ng2086 = 1'h0; + (* init = 1'h0 *) + reg Ng2087 = 1'h0; + (* init = 1'h0 *) + reg Ng2088 = 1'h0; + (* init = 1'h0 *) + reg Ng2089 = 1'h0; + (* init = 1'h0 *) + reg Ng2090 = 1'h0; + (* init = 1'h0 *) + reg Ng2091 = 1'h0; + (* init = 1'h0 *) + reg Ng2092 = 1'h0; + (* init = 1'h0 *) + reg Ng2093 = 1'h0; + (* init = 1'h0 *) + reg Ng2094 = 1'h0; + (* init = 1'h0 *) + reg Ng2095 = 1'h0; + (* init = 1'h0 *) + reg Ng2096 = 1'h0; + (* init = 1'h0 *) + reg Ng2097 = 1'h0; + (* init = 1'h0 *) + reg Ng2098 = 1'h0; + (* init = 1'h0 *) + reg Ng2099 = 1'h0; + (* init = 1'h0 *) + reg Ng210 = 1'h0; + (* init = 1'h0 *) + reg Ng2100 = 1'h0; + (* init = 1'h0 *) + reg Ng2101 = 1'h0; + (* init = 1'h0 *) + reg Ng2102 = 1'h0; + (* init = 1'h0 *) + reg Ng2103 = 1'h0; + (* init = 1'h0 *) + reg Ng2104 = 1'h0; + (* init = 1'h0 *) + reg Ng2105 = 1'h0; + (* init = 1'h0 *) + reg Ng2106 = 1'h0; + (* init = 1'h0 *) + reg Ng2107 = 1'h0; + (* init = 1'h0 *) + reg Ng2108 = 1'h0; + (* init = 1'h0 *) + reg Ng2109 = 1'h0; + (* init = 1'h0 *) + reg Ng2110 = 1'h0; + (* init = 1'h0 *) + reg Ng2111 = 1'h0; + (* init = 1'h0 *) + reg Ng2112 = 1'h0; + (* init = 1'h0 *) + reg Ng2113 = 1'h0; + (* init = 1'h0 *) + reg Ng2114 = 1'h0; + (* init = 1'h0 *) + reg Ng2115 = 1'h0; + (* init = 1'h0 *) + reg Ng2116 = 1'h0; + (* init = 1'h0 *) + reg Ng2117 = 1'h0; + (* init = 1'h0 *) + reg Ng2118 = 1'h0; + (* init = 1'h0 *) + reg Ng2119 = 1'h0; + (* init = 1'h0 *) + reg Ng2120 = 1'h0; + (* init = 1'h0 *) + reg Ng2124 = 1'h0; + (* init = 1'h0 *) + reg Ng2129 = 1'h0; + (* init = 1'h0 *) + reg Ng213 = 1'h0; + (* init = 1'h0 *) + reg Ng2133 = 1'h0; + (* init = 1'h0 *) + reg Ng2138 = 1'h0; + (* init = 1'h0 *) + reg Ng2142 = 1'h0; + (* init = 1'h0 *) + reg Ng2147 = 1'h0; + (* init = 1'h0 *) + reg Ng2151 = 1'h0; + (* init = 1'h0 *) + reg Ng2156 = 1'h0; + (* init = 1'h0 *) + reg Ng216 = 1'h0; + (* init = 1'h0 *) + reg Ng2160 = 1'h0; + (* init = 1'h0 *) + reg Ng2165 = 1'h0; + (* init = 1'h0 *) + reg Ng2170 = 1'h0; + (* init = 1'h0 *) + reg Ng2175 = 1'h0; + (* init = 1'h0 *) + reg Ng2180 = 1'h0; + (* init = 1'h0 *) + reg Ng2185 = 1'h0; + (* init = 1'h0 *) + reg Ng219 = 1'h0; + (* init = 1'h0 *) + reg Ng2190 = 1'h0; + (* init = 1'h0 *) + reg Ng2195 = 1'h0; + (* init = 1'h0 *) + reg Ng2200 = 1'h0; + (* init = 1'h0 *) + reg Ng2205 = 1'h0; + (* init = 1'h0 *) + reg Ng2206 = 1'h0; + (* init = 1'h0 *) + reg Ng2207 = 1'h0; + (* init = 1'h0 *) + reg Ng2208 = 1'h0; + (* init = 1'h0 *) + reg Ng2209 = 1'h0; + (* init = 1'h0 *) + reg Ng2210 = 1'h0; + (* init = 1'h0 *) + reg Ng2217 = 1'h0; + (* init = 1'h0 *) + reg Ng2218 = 1'h0; + (* init = 1'h0 *) + reg Ng2219 = 1'h0; + (* init = 1'h0 *) + reg Ng222 = 1'h0; + (* init = 1'h0 *) + reg Ng2220 = 1'h0; + (* init = 1'h0 *) + reg Ng2221 = 1'h0; + (* init = 1'h0 *) + reg Ng2222 = 1'h0; + (* init = 1'h0 *) + reg Ng2223 = 1'h0; + (* init = 1'h0 *) + reg Ng2224 = 1'h0; + (* init = 1'h0 *) + reg Ng2225 = 1'h0; + (* init = 1'h0 *) + reg Ng2226 = 1'h0; + (* init = 1'h0 *) + reg Ng2227 = 1'h0; + (* init = 1'h0 *) + reg Ng2228 = 1'h0; + (* init = 1'h0 *) + reg Ng2229 = 1'h0; + (* init = 1'h0 *) + reg Ng2230 = 1'h0; + (* init = 1'h0 *) + reg Ng2231 = 1'h0; + (* init = 1'h0 *) + reg Ng2232 = 1'h0; + (* init = 1'h0 *) + reg Ng2233 = 1'h0; + (* init = 1'h0 *) + reg Ng2234 = 1'h0; + (* init = 1'h0 *) + reg Ng2235 = 1'h0; + (* init = 1'h0 *) + reg Ng2236 = 1'h0; + (* init = 1'h0 *) + reg Ng2237 = 1'h0; + (* init = 1'h0 *) + reg Ng2238 = 1'h0; + (* init = 1'h0 *) + reg Ng2239 = 1'h0; + (* init = 1'h0 *) + reg Ng2240 = 1'h0; + (* init = 1'h0 *) + reg Ng2244 = 1'h0; + (* init = 1'h0 *) + reg Ng2245 = 1'h0; + (* init = 1'h0 *) + reg Ng2246 = 1'h0; + (* init = 1'h0 *) + reg Ng2247 = 1'h0; + (* init = 1'h0 *) + reg Ng2248 = 1'h0; + (* init = 1'h0 *) + reg Ng2249 = 1'h0; + (* init = 1'h0 *) + reg Ng225 = 1'h0; + (* init = 1'h0 *) + reg Ng2250 = 1'h0; + (* init = 1'h0 *) + reg Ng2251 = 1'h0; + (* init = 1'h0 *) + reg Ng2252 = 1'h0; + (* init = 1'h0 *) + reg Ng2253 = 1'h0; + (* init = 1'h0 *) + reg Ng2254 = 1'h0; + (* init = 1'h0 *) + reg Ng2255 = 1'h0; + (* init = 1'h0 *) + reg Ng2256 = 1'h0; + (* init = 1'h0 *) + reg Ng2257 = 1'h0; + (* init = 1'h0 *) + reg Ng2261 = 1'h0; + (* init = 1'h0 *) + reg Ng2264 = 1'h0; + (* init = 1'h0 *) + reg Ng2267 = 1'h0; + (* init = 1'h0 *) + reg Ng2270 = 1'h0; + (* init = 1'h0 *) + reg Ng2273 = 1'h0; + (* init = 1'h0 *) + reg Ng2276 = 1'h0; + (* init = 1'h0 *) + reg Ng2279 = 1'h0; + (* init = 1'h0 *) + reg Ng228 = 1'h0; + (* init = 1'h0 *) + reg Ng2282 = 1'h0; + (* init = 1'h0 *) + reg Ng2285 = 1'h0; + (* init = 1'h0 *) + reg Ng2288 = 1'h0; + (* init = 1'h0 *) + reg Ng2291 = 1'h0; + (* init = 1'h0 *) + reg Ng2294 = 1'h0; + (* init = 1'h0 *) + reg Ng2297 = 1'h0; + (* init = 1'h0 *) + reg Ng2300 = 1'h0; + (* init = 1'h0 *) + reg Ng2303 = 1'h0; + (* init = 1'h0 *) + reg Ng2306 = 1'h0; + (* init = 1'h0 *) + reg Ng2309 = 1'h0; + (* init = 1'h0 *) + reg Ng231 = 1'h0; + (* init = 1'h0 *) + reg Ng2312 = 1'h0; + (* init = 1'h0 *) + reg Ng2315 = 1'h0; + (* init = 1'h0 *) + reg Ng2318 = 1'h0; + (* init = 1'h0 *) + reg Ng2321 = 1'h0; + (* init = 1'h0 *) + reg Ng2324 = 1'h0; + (* init = 1'h0 *) + reg Ng2327 = 1'h0; + (* init = 1'h0 *) + reg Ng2330 = 1'h0; + (* init = 1'h0 *) + reg Ng2333 = 1'h0; + (* init = 1'h0 *) + reg Ng2336 = 1'h0; + (* init = 1'h0 *) + reg Ng2339 = 1'h0; + (* init = 1'h0 *) + reg Ng234 = 1'h0; + (* init = 1'h0 *) + reg Ng2342 = 1'h0; + (* init = 1'h0 *) + reg Ng2345 = 1'h0; + (* init = 1'h0 *) + reg Ng2348 = 1'h0; + (* init = 1'h0 *) + reg Ng2354 = 1'h0; + (* init = 1'h0 *) + reg Ng2355 = 1'h0; + (* init = 1'h0 *) + reg Ng2356 = 1'h0; + (* init = 1'h0 *) + reg Ng2357 = 1'h0; + (* init = 1'h0 *) + reg Ng2358 = 1'h0; + (* init = 1'h0 *) + reg Ng2359 = 1'h0; + (* init = 1'h0 *) + reg Ng2360 = 1'h0; + (* init = 1'h0 *) + reg Ng2361 = 1'h0; + (* init = 1'h0 *) + reg Ng2362 = 1'h0; + (* init = 1'h0 *) + reg Ng2363 = 1'h0; + (* init = 1'h0 *) + reg Ng2364 = 1'h0; + (* init = 1'h0 *) + reg Ng2365 = 1'h0; + (* init = 1'h0 *) + reg Ng2366 = 1'h0; + (* init = 1'h0 *) + reg Ng237 = 1'h0; + (* init = 1'h0 *) + reg Ng2373 = 1'h0; + (* init = 1'h0 *) + reg Ng2374 = 1'h0; + (* init = 1'h0 *) + reg Ng2380 = 1'h0; + (* init = 1'h0 *) + reg Ng2387 = 1'h0; + (* init = 1'h0 *) + reg Ng2388 = 1'h0; + (* init = 1'h0 *) + reg Ng2389 = 1'h0; + (* init = 1'h0 *) + reg Ng2390 = 1'h0; + (* init = 1'h0 *) + reg Ng2391 = 1'h0; + (* init = 1'h0 *) + reg Ng2392 = 1'h0; + (* init = 1'h0 *) + reg Ng2393 = 1'h0; + (* init = 1'h0 *) + reg Ng2394 = 1'h0; + (* init = 1'h0 *) + reg Ng2395 = 1'h0; + (* init = 1'h0 *) + reg Ng2396 = 1'h0; + (* init = 1'h0 *) + reg Ng2397 = 1'h0; + (* init = 1'h0 *) + reg Ng2398 = 1'h0; + (* init = 1'h0 *) + reg Ng2399 = 1'h0; + (* init = 1'h0 *) + reg Ng240 = 1'h0; + (* init = 1'h0 *) + reg Ng2417 = 1'h0; + (* init = 1'h0 *) + reg Ng2424 = 1'h0; + (* init = 1'h0 *) + reg Ng2425 = 1'h0; + (* init = 1'h0 *) + reg Ng2426 = 1'h0; + (* init = 1'h0 *) + reg Ng2427 = 1'h0; + (* init = 1'h0 *) + reg Ng2428 = 1'h0; + (* init = 1'h0 *) + reg Ng243 = 1'h0; + (* init = 1'h0 *) + reg Ng2432 = 1'h0; + (* init = 1'h0 *) + reg Ng2439 = 1'h0; + (* init = 1'h0 *) + reg Ng2440 = 1'h0; + (* init = 1'h0 *) + reg Ng2441 = 1'h0; + (* init = 1'h0 *) + reg Ng2442 = 1'h0; + (* init = 1'h0 *) + reg Ng2443 = 1'h0; + (* init = 1'h0 *) + reg Ng2447 = 1'h0; + (* init = 1'h0 *) + reg Ng2454 = 1'h0; + (* init = 1'h0 *) + reg Ng2455 = 1'h0; + (* init = 1'h0 *) + reg Ng2456 = 1'h0; + (* init = 1'h0 *) + reg Ng2457 = 1'h0; + (* init = 1'h0 *) + reg Ng2458 = 1'h0; + (* init = 1'h0 *) + reg Ng246 = 1'h0; + (* init = 1'h0 *) + reg Ng2462 = 1'h0; + (* init = 1'h0 *) + reg Ng2469 = 1'h0; + (* init = 1'h0 *) + reg Ng2470 = 1'h0; + (* init = 1'h0 *) + reg Ng2471 = 1'h0; + (* init = 1'h0 *) + reg Ng2472 = 1'h0; + (* init = 1'h0 *) + reg Ng2477 = 1'h0; + (* init = 1'h0 *) + reg Ng2478 = 1'h0; + (* init = 1'h0 *) + reg Ng2479 = 1'h0; + (* init = 1'h0 *) + reg Ng2483 = 1'h0; + (* init = 1'h0 *) + reg Ng2486 = 1'h0; + (* init = 1'h0 *) + reg Ng2489 = 1'h0; + (* init = 1'h0 *) + reg Ng249 = 1'h0; + (* init = 1'h0 *) + reg Ng2492 = 1'h0; + (* init = 1'h0 *) + reg Ng2495 = 1'h0; + (* init = 1'h0 *) + reg Ng2498 = 1'h0; + (* init = 1'h0 *) + reg Ng2501 = 1'h0; + (* init = 1'h0 *) + reg Ng2502 = 1'h0; + (* init = 1'h0 *) + reg Ng2503 = 1'h0; + (* init = 1'h0 *) + reg Ng2504 = 1'h0; + (* init = 1'h0 *) + reg Ng2507 = 1'h0; + (* init = 1'h0 *) + reg Ng2510 = 1'h0; + (* init = 1'h0 *) + reg Ng2513 = 1'h0; + (* init = 1'h0 *) + reg Ng2516 = 1'h0; + (* init = 1'h0 *) + reg Ng2519 = 1'h0; + (* init = 1'h0 *) + reg Ng252 = 1'h0; + (* init = 1'h0 *) + reg Ng2522 = 1'h0; + (* init = 1'h0 *) + reg Ng2523 = 1'h0; + (* init = 1'h0 *) + reg Ng2524 = 1'h0; + (* init = 1'h0 *) + reg Ng2525 = 1'h0; + (* init = 1'h0 *) + reg Ng2526 = 1'h0; + (* init = 1'h0 *) + reg Ng2527 = 1'h0; + (* init = 1'h0 *) + reg Ng2528 = 1'h0; + (* init = 1'h0 *) + reg Ng2529 = 1'h0; + (* init = 1'h0 *) + reg Ng2539 = 1'h0; + (* init = 1'h0 *) + reg Ng255 = 1'h0; + (* init = 1'h0 *) + reg Ng2552 = 1'h0; + (* init = 1'h0 *) + reg Ng2553 = 1'h0; + (* init = 1'h0 *) + reg Ng2554 = 1'h0; + (* init = 1'h0 *) + reg Ng2555 = 1'h0; + (* init = 1'h0 *) + reg Ng2559 = 1'h0; + (* init = 1'h0 *) + reg Ng2561 = 1'h0; + (* init = 1'h0 *) + reg Ng2562 = 1'h0; + (* init = 1'h0 *) + reg Ng2563 = 1'h0; + (* init = 1'h0 *) + reg Ng2564 = 1'h0; + (* init = 1'h0 *) + reg Ng2565 = 1'h0; + (* init = 1'h0 *) + reg Ng2568 = 1'h0; + (* init = 1'h0 *) + reg Ng2571 = 1'h0; + (* init = 1'h0 *) + reg Ng258 = 1'h0; + (* init = 1'h0 *) + reg Ng2580 = 1'h0; + (* init = 1'h0 *) + reg Ng2581 = 1'h0; + (* init = 1'h0 *) + reg Ng2584 = 1'h0; + (* init = 1'h0 *) + reg Ng2587 = 1'h0; + (* init = 1'h0 *) + reg Ng2597 = 1'h0; + (* init = 1'h0 *) + reg Ng2598 = 1'h0; + (* init = 1'h0 *) + reg Ng2599 = 1'h0; + (* init = 1'h0 *) + reg Ng2602 = 1'h0; + (* init = 1'h0 *) + reg Ng2603 = 1'h0; + (* init = 1'h0 *) + reg Ng2604 = 1'h0; + (* init = 1'h0 *) + reg Ng2605 = 1'h0; + (* init = 1'h0 *) + reg Ng2606 = 1'h0; + (* init = 1'h0 *) + reg Ng2607 = 1'h0; + (* init = 1'h0 *) + reg Ng2608 = 1'h0; + (* init = 1'h0 *) + reg Ng2609 = 1'h0; + (* init = 1'h0 *) + reg Ng261 = 1'h0; + (* init = 1'h0 *) + reg Ng2610 = 1'h0; + (* init = 1'h0 *) + reg Ng2611 = 1'h0; + (* init = 1'h0 *) + reg Ng2612 = 1'h0; + (* init = 1'h0 *) + reg Ng2615 = 1'h0; + (* init = 1'h0 *) + reg Ng2616 = 1'h0; + (* init = 1'h0 *) + reg Ng2617 = 1'h0; + (* init = 1'h0 *) + reg Ng2618 = 1'h0; + (* init = 1'h0 *) + reg Ng2622 = 1'h0; + (* init = 1'h0 *) + reg Ng2623 = 1'h0; + (* init = 1'h0 *) + reg Ng2628 = 1'h0; + (* init = 1'h0 *) + reg Ng2631 = 1'h0; + (* init = 1'h0 *) + reg Ng2632 = 1'h0; + (* init = 1'h0 *) + reg Ng2633 = 1'h0; + (* init = 1'h0 *) + reg Ng2638 = 1'h0; + (* init = 1'h0 *) + reg Ng2639 = 1'h0; + (* init = 1'h0 *) + reg Ng264 = 1'h0; + (* init = 1'h0 *) + reg Ng2640 = 1'h0; + (* init = 1'h0 *) + reg Ng2641 = 1'h0; + (* init = 1'h0 *) + reg Ng2642 = 1'h0; + (* init = 1'h0 *) + reg Ng2643 = 1'h0; + (* init = 1'h0 *) + reg Ng2644 = 1'h0; + (* init = 1'h0 *) + reg Ng2645 = 1'h0; + (* init = 1'h0 *) + reg Ng2646 = 1'h0; + (* init = 1'h0 *) + reg Ng2647 = 1'h0; + (* init = 1'h0 *) + reg Ng2648 = 1'h0; + (* init = 1'h0 *) + reg Ng2649 = 1'h0; + (* init = 1'h0 *) + reg Ng2650 = 1'h0; + (* init = 1'h0 *) + reg Ng2651 = 1'h0; + (* init = 1'h0 *) + reg Ng2652 = 1'h0; + (* init = 1'h0 *) + reg Ng2653 = 1'h0; + (* init = 1'h0 *) + reg Ng2654 = 1'h0; + (* init = 1'h0 *) + reg Ng2655 = 1'h0; + (* init = 1'h0 *) + reg Ng2656 = 1'h0; + (* init = 1'h0 *) + reg Ng2657 = 1'h0; + (* init = 1'h0 *) + reg Ng2658 = 1'h0; + (* init = 1'h0 *) + reg Ng2659 = 1'h0; + (* init = 1'h0 *) + reg Ng2660 = 1'h0; + (* init = 1'h0 *) + reg Ng2661 = 1'h0; + (* init = 1'h0 *) + reg Ng2664 = 1'h0; + (* init = 1'h0 *) + reg Ng2667 = 1'h0; + (* init = 1'h0 *) + reg Ng267 = 1'h0; + (* init = 1'h0 *) + reg Ng2670 = 1'h0; + (* init = 1'h0 *) + reg Ng2673 = 1'h0; + (* init = 1'h0 *) + reg Ng2676 = 1'h0; + (* init = 1'h0 *) + reg Ng2679 = 1'h0; + (* init = 1'h0 *) + reg Ng2682 = 1'h0; + (* init = 1'h0 *) + reg Ng2685 = 1'h0; + (* init = 1'h0 *) + reg Ng2688 = 1'h0; + (* init = 1'h0 *) + reg Ng2691 = 1'h0; + (* init = 1'h0 *) + reg Ng2694 = 1'h0; + (* init = 1'h0 *) + reg Ng270 = 1'h0; + (* init = 1'h0 *) + reg Ng2704 = 1'h0; + (* init = 1'h0 *) + reg Ng2707 = 1'h0; + (* init = 1'h0 *) + reg Ng2714 = 1'h0; + (* init = 1'h0 *) + reg Ng2720 = 1'h0; + (* init = 1'h0 *) + reg Ng2727 = 1'h0; + (* init = 1'h0 *) + reg Ng273 = 1'h0; + (* init = 1'h0 *) + reg Ng2733 = 1'h0; + (* init = 1'h0 *) + reg Ng2734 = 1'h0; + (* init = 1'h0 *) + reg Ng2740 = 1'h0; + (* init = 1'h0 *) + reg Ng2746 = 1'h0; + (* init = 1'h0 *) + reg Ng2753 = 1'h0; + (* init = 1'h0 *) + reg Ng2760 = 1'h0; + (* init = 1'h0 *) + reg Ng2766 = 1'h0; + (* init = 1'h0 *) + reg Ng2772 = 1'h0; + (* init = 1'h0 *) + reg Ng2773 = 1'h0; + (* init = 1'h0 *) + reg Ng2774 = 1'h0; + (* init = 1'h0 *) + reg Ng2775 = 1'h0; + (* init = 1'h0 *) + reg Ng2776 = 1'h0; + (* init = 1'h0 *) + reg Ng2777 = 1'h0; + (* init = 1'h0 *) + reg Ng2778 = 1'h0; + (* init = 1'h0 *) + reg Ng2779 = 1'h0; + (* init = 1'h0 *) + reg Ng2780 = 1'h0; + (* init = 1'h0 *) + reg Ng2781 = 1'h0; + (* init = 1'h0 *) + reg Ng2782 = 1'h0; + (* init = 1'h0 *) + reg Ng2783 = 1'h0; + (* init = 1'h0 *) + reg Ng2784 = 1'h0; + (* init = 1'h0 *) + reg Ng2785 = 1'h0; + (* init = 1'h0 *) + reg Ng2786 = 1'h0; + (* init = 1'h0 *) + reg Ng2787 = 1'h0; + (* init = 1'h0 *) + reg Ng2788 = 1'h0; + (* init = 1'h0 *) + reg Ng2789 = 1'h0; + (* init = 1'h0 *) + reg Ng279 = 1'h0; + (* init = 1'h0 *) + reg Ng2790 = 1'h0; + (* init = 1'h0 *) + reg Ng2791 = 1'h0; + (* init = 1'h0 *) + reg Ng2792 = 1'h0; + (* init = 1'h0 *) + reg Ng2793 = 1'h0; + (* init = 1'h0 *) + reg Ng2794 = 1'h0; + (* init = 1'h0 *) + reg Ng2795 = 1'h0; + (* init = 1'h0 *) + reg Ng2796 = 1'h0; + (* init = 1'h0 *) + reg Ng2797 = 1'h0; + (* init = 1'h0 *) + reg Ng2798 = 1'h0; + (* init = 1'h0 *) + reg Ng2799 = 1'h0; + (* init = 1'h0 *) + reg Ng280 = 1'h0; + (* init = 1'h0 *) + reg Ng2800 = 1'h0; + (* init = 1'h0 *) + reg Ng2801 = 1'h0; + (* init = 1'h0 *) + reg Ng2802 = 1'h0; + (* init = 1'h0 *) + reg Ng2803 = 1'h0; + (* init = 1'h0 *) + reg Ng2804 = 1'h0; + (* init = 1'h0 *) + reg Ng2805 = 1'h0; + (* init = 1'h0 *) + reg Ng2806 = 1'h0; + (* init = 1'h0 *) + reg Ng2807 = 1'h0; + (* init = 1'h0 *) + reg Ng2808 = 1'h0; + (* init = 1'h0 *) + reg Ng2809 = 1'h0; + (* init = 1'h0 *) + reg Ng281 = 1'h0; + (* init = 1'h0 *) + reg Ng2810 = 1'h0; + (* init = 1'h0 *) + reg Ng2811 = 1'h0; + (* init = 1'h0 *) + reg Ng2812 = 1'h0; + (* init = 1'h0 *) + reg Ng2813 = 1'h0; + (* init = 1'h0 *) + reg Ng2817 = 1'h0; + (* init = 1'h0 *) + reg Ng282 = 1'h0; + (* init = 1'h0 *) + reg Ng283 = 1'h0; + (* init = 1'h0 *) + reg Ng284 = 1'h0; + (* init = 1'h0 *) + reg Ng285 = 1'h0; + (* init = 1'h0 *) + reg Ng286 = 1'h0; + (* init = 1'h0 *) + reg Ng287 = 1'h0; + (* init = 1'h0 *) + reg Ng2874 = 1'h0; + (* init = 1'h0 *) + reg Ng2879 = 1'h0; + (* init = 1'h0 *) + reg Ng288 = 1'h0; + (* init = 1'h0 *) + reg Ng2883 = 1'h0; + (* init = 1'h0 *) + reg Ng2888 = 1'h0; + (* init = 1'h0 *) + reg Ng289 = 1'h0; + (* init = 1'h0 *) + reg Ng2892 = 1'h0; + (* init = 1'h0 *) + reg Ng2896 = 1'h0; + (* init = 1'h0 *) + reg Ng290 = 1'h0; + (* init = 1'h0 *) + reg Ng2900 = 1'h0; + (* init = 1'h0 *) + reg Ng2903 = 1'h0; + (* init = 1'h0 *) + reg Ng2908 = 1'h0; + (* init = 1'h0 *) + reg Ng291 = 1'h0; + (* init = 1'h0 *) + reg Ng2912 = 1'h0; + (* init = 1'h0 *) + reg Ng2917 = 1'h0; + (* init = 1'h0 *) + reg Ng2920 = 1'h0; + (* init = 1'h0 *) + reg Ng2924 = 1'h0; + (* init = 1'h0 *) + reg Ng2929 = 1'h0; + (* init = 1'h0 *) + reg Ng2933 = 1'h0; + (* init = 1'h0 *) + reg Ng2934 = 1'h0; + (* init = 1'h0 *) + reg Ng2935 = 1'h0; + (* init = 1'h0 *) + reg Ng2938 = 1'h0; + (* init = 1'h0 *) + reg Ng2941 = 1'h0; + (* init = 1'h0 *) + reg Ng2944 = 1'h0; + (* init = 1'h0 *) + reg Ng2947 = 1'h0; + (* init = 1'h0 *) + reg Ng2953 = 1'h0; + (* init = 1'h0 *) + reg Ng2956 = 1'h0; + (* init = 1'h0 *) + reg Ng2959 = 1'h0; + (* init = 1'h0 *) + reg Ng2962 = 1'h0; + (* init = 1'h0 *) + reg Ng2963 = 1'h0; + (* init = 1'h0 *) + reg Ng2966 = 1'h0; + (* init = 1'h0 *) + reg Ng2969 = 1'h0; + (* init = 1'h0 *) + reg Ng2972 = 1'h0; + (* init = 1'h0 *) + reg Ng2975 = 1'h0; + (* init = 1'h0 *) + reg Ng2978 = 1'h0; + (* init = 1'h0 *) + reg Ng298 = 1'h0; + (* init = 1'h0 *) + reg Ng2981 = 1'h0; + (* init = 1'h0 *) + reg Ng2984 = 1'h0; + (* init = 1'h0 *) + reg Ng2985 = 1'h0; + (* init = 1'h0 *) + reg Ng2986 = 1'h0; + (* init = 1'h0 *) + reg Ng2987 = 1'h0; + (* init = 1'h0 *) + reg Ng299 = 1'h0; + (* init = 1'h0 *) + reg Ng2990 = 1'h0; + (* init = 1'h0 *) + reg Ng2991 = 1'h0; + (* init = 1'h0 *) + reg Ng2992 = 1'h0; + (* init = 1'h0 *) + reg Ng2993 = 1'h0; + (* init = 1'h0 *) + reg Ng2997 = 1'h0; + (* init = 1'h0 *) + reg Ng2998 = 1'h0; + (* init = 1'h0 *) + reg Ng3002 = 1'h0; + (* init = 1'h0 *) + reg Ng3006 = 1'h0; + (* init = 1'h0 *) + reg Ng3010 = 1'h0; + (* init = 1'h0 *) + reg Ng3013 = 1'h0; + (* init = 1'h0 *) + reg Ng3018 = 1'h0; + (* init = 1'h0 *) + reg Ng3024 = 1'h0; + (* init = 1'h0 *) + reg Ng3028 = 1'h0; + (* init = 1'h0 *) + reg Ng3032 = 1'h0; + (* init = 1'h0 *) + reg Ng3036 = 1'h0; + (* init = 1'h0 *) + reg Ng3043 = 1'h0; + (* init = 1'h0 *) + reg Ng3044 = 1'h0; + (* init = 1'h0 *) + reg Ng3045 = 1'h0; + (* init = 1'h0 *) + reg Ng3046 = 1'h0; + (* init = 1'h0 *) + reg Ng3047 = 1'h0; + (* init = 1'h0 *) + reg Ng3048 = 1'h0; + (* init = 1'h0 *) + reg Ng3049 = 1'h0; + (* init = 1'h0 *) + reg Ng305 = 1'h0; + (* init = 1'h0 *) + reg Ng3050 = 1'h0; + (* init = 1'h0 *) + reg Ng3051 = 1'h0; + (* init = 1'h0 *) + reg Ng3052 = 1'h0; + (* init = 1'h0 *) + reg Ng3053 = 1'h0; + (* init = 1'h0 *) + reg Ng3054 = 1'h0; + (* init = 1'h0 *) + reg Ng3055 = 1'h0; + (* init = 1'h0 *) + reg Ng3056 = 1'h0; + (* init = 1'h0 *) + reg Ng3057 = 1'h0; + (* init = 1'h0 *) + reg Ng3058 = 1'h0; + (* init = 1'h0 *) + reg Ng3059 = 1'h0; + (* init = 1'h0 *) + reg Ng3060 = 1'h0; + (* init = 1'h0 *) + reg Ng3061 = 1'h0; + (* init = 1'h0 *) + reg Ng3062 = 1'h0; + (* init = 1'h0 *) + reg Ng3063 = 1'h0; + (* init = 1'h0 *) + reg Ng3064 = 1'h0; + (* init = 1'h0 *) + reg Ng3065 = 1'h0; + (* init = 1'h0 *) + reg Ng3066 = 1'h0; + (* init = 1'h0 *) + reg Ng3067 = 1'h0; + (* init = 1'h0 *) + reg Ng3068 = 1'h0; + (* init = 1'h0 *) + reg Ng3069 = 1'h0; + (* init = 1'h0 *) + reg Ng3070 = 1'h0; + (* init = 1'h0 *) + reg Ng3071 = 1'h0; + (* init = 1'h0 *) + reg Ng3072 = 1'h0; + (* init = 1'h0 *) + reg Ng3073 = 1'h0; + (* init = 1'h0 *) + reg Ng3074 = 1'h0; + (* init = 1'h0 *) + reg Ng3075 = 1'h0; + (* init = 1'h0 *) + reg Ng3076 = 1'h0; + (* init = 1'h0 *) + reg Ng3077 = 1'h0; + (* init = 1'h0 *) + reg Ng3078 = 1'h0; + (* init = 1'h0 *) + reg Ng3079 = 1'h0; + (* init = 1'h0 *) + reg Ng3083 = 1'h0; + (* init = 1'h0 *) + reg Ng3084 = 1'h0; + (* init = 1'h0 *) + reg Ng3085 = 1'h0; + (* init = 1'h0 *) + reg Ng3086 = 1'h0; + (* init = 1'h0 *) + reg Ng3087 = 1'h0; + (* init = 1'h0 *) + reg Ng3088 = 1'h0; + (* init = 1'h0 *) + reg Ng3091 = 1'h0; + (* init = 1'h0 *) + reg Ng3092 = 1'h0; + (* init = 1'h0 *) + reg Ng3093 = 1'h0; + (* init = 1'h0 *) + reg Ng3094 = 1'h0; + (* init = 1'h0 *) + reg Ng3095 = 1'h0; + (* init = 1'h0 *) + reg Ng3096 = 1'h0; + (* init = 1'h0 *) + reg Ng3097 = 1'h0; + (* init = 1'h0 *) + reg Ng3098 = 1'h0; + (* init = 1'h0 *) + reg Ng3099 = 1'h0; + (* init = 1'h0 *) + reg Ng3100 = 1'h0; + (* init = 1'h0 *) + reg Ng3101 = 1'h0; + (* init = 1'h0 *) + reg Ng3102 = 1'h0; + (* init = 1'h0 *) + reg Ng3103 = 1'h0; + (* init = 1'h0 *) + reg Ng3104 = 1'h0; + (* init = 1'h0 *) + reg Ng3105 = 1'h0; + (* init = 1'h0 *) + reg Ng3106 = 1'h0; + (* init = 1'h0 *) + reg Ng3107 = 1'h0; + (* init = 1'h0 *) + reg Ng3108 = 1'h0; + (* init = 1'h0 *) + reg Ng3110 = 1'h0; + (* init = 1'h0 *) + reg Ng312 = 1'h0; + (* init = 1'h0 *) + reg Ng3120 = 1'h0; + (* init = 1'h0 *) + reg Ng3123 = 1'h0; + (* init = 1'h0 *) + reg Ng3125 = 1'h0; + (* init = 1'h0 *) + reg Ng3126 = 1'h0; + (* init = 1'h0 *) + reg Ng3128 = 1'h0; + (* init = 1'h0 *) + reg Ng313 = 1'h0; + (* init = 1'h0 *) + reg Ng3135 = 1'h0; + (* init = 1'h0 *) + reg Ng3139 = 1'h0; + (* init = 1'h0 *) + reg Ng314 = 1'h0; + (* init = 1'h0 *) + reg Ng3147 = 1'h0; + (* init = 1'h0 *) + reg Ng315 = 1'h0; + (* init = 1'h0 *) + reg Ng3155 = 1'h0; + (* init = 1'h0 *) + reg Ng3158 = 1'h0; + (* init = 1'h0 *) + reg Ng316 = 1'h0; + (* init = 1'h0 *) + reg Ng3161 = 1'h0; + (* init = 1'h0 *) + reg Ng3164 = 1'h0; + (* init = 1'h0 *) + reg Ng3167 = 1'h0; + (* init = 1'h0 *) + reg Ng317 = 1'h0; + (* init = 1'h0 *) + reg Ng3170 = 1'h0; + (* init = 1'h0 *) + reg Ng3173 = 1'h0; + (* init = 1'h0 *) + reg Ng3176 = 1'h0; + (* init = 1'h0 *) + reg Ng3179 = 1'h0; + (* init = 1'h0 *) + reg Ng318 = 1'h0; + (* init = 1'h0 *) + reg Ng3182 = 1'h0; + (* init = 1'h0 *) + reg Ng3185 = 1'h0; + (* init = 1'h0 *) + reg Ng319 = 1'h0; + (* init = 1'h0 *) + reg Ng3191 = 1'h0; + (* init = 1'h0 *) + reg Ng320 = 1'h0; + (* init = 1'h0 *) + reg Ng321 = 1'h0; + (* init = 1'h0 *) + reg Ng3210 = 1'h0; + (* init = 1'h0 *) + reg Ng3211 = 1'h0; + (* init = 1'h0 *) + reg Ng322 = 1'h0; + (* init = 1'h0 *) + reg Ng323 = 1'h0; + (* init = 1'h0 *) + reg Ng324 = 1'h0; + (* init = 1'h0 *) + reg Ng342 = 1'h0; + (* init = 1'h0 *) + reg Ng349 = 1'h0; + (* init = 1'h0 *) + reg Ng350 = 1'h0; + (* init = 1'h0 *) + reg Ng351 = 1'h0; + (* init = 1'h0 *) + reg Ng352 = 1'h0; + (* init = 1'h0 *) + reg Ng353 = 1'h0; + (* init = 1'h0 *) + reg Ng357 = 1'h0; + (* init = 1'h0 *) + reg Ng364 = 1'h0; + (* init = 1'h0 *) + reg Ng365 = 1'h0; + (* init = 1'h0 *) + reg Ng366 = 1'h0; + (* init = 1'h0 *) + reg Ng367 = 1'h0; + (* init = 1'h0 *) + reg Ng368 = 1'h0; + (* init = 1'h0 *) + reg Ng372 = 1'h0; + (* init = 1'h0 *) + reg Ng379 = 1'h0; + (* init = 1'h0 *) + reg Ng380 = 1'h0; + (* init = 1'h0 *) + reg Ng381 = 1'h0; + (* init = 1'h0 *) + reg Ng382 = 1'h0; + (* init = 1'h0 *) + reg Ng383 = 1'h0; + (* init = 1'h0 *) + reg Ng387 = 1'h0; + (* init = 1'h0 *) + reg Ng394 = 1'h0; + (* init = 1'h0 *) + reg Ng395 = 1'h0; + (* init = 1'h0 *) + reg Ng396 = 1'h0; + (* init = 1'h0 *) + reg Ng397 = 1'h0; + (* init = 1'h0 *) + reg Ng402 = 1'h0; + (* init = 1'h0 *) + reg Ng403 = 1'h0; + (* init = 1'h0 *) + reg Ng404 = 1'h0; + (* init = 1'h0 *) + reg Ng408 = 1'h0; + (* init = 1'h0 *) + reg Ng411 = 1'h0; + (* init = 1'h0 *) + reg Ng414 = 1'h0; + (* init = 1'h0 *) + reg Ng417 = 1'h0; + (* init = 1'h0 *) + reg Ng420 = 1'h0; + (* init = 1'h0 *) + reg Ng423 = 1'h0; + (* init = 1'h0 *) + reg Ng426 = 1'h0; + (* init = 1'h0 *) + reg Ng427 = 1'h0; + (* init = 1'h0 *) + reg Ng428 = 1'h0; + (* init = 1'h0 *) + reg Ng429 = 1'h0; + (* init = 1'h0 *) + reg Ng432 = 1'h0; + (* init = 1'h0 *) + reg Ng435 = 1'h0; + (* init = 1'h0 *) + reg Ng438 = 1'h0; + (* init = 1'h0 *) + reg Ng441 = 1'h0; + (* init = 1'h0 *) + reg Ng444 = 1'h0; + (* init = 1'h0 *) + reg Ng447 = 1'h0; + (* init = 1'h0 *) + reg Ng448 = 1'h0; + (* init = 1'h0 *) + reg Ng449 = 1'h0; + (* init = 1'h0 *) + reg Ng450 = 1'h0; + (* init = 1'h0 *) + reg Ng451 = 1'h0; + (* init = 1'h0 *) + reg Ng452 = 1'h0; + (* init = 1'h0 *) + reg Ng453 = 1'h0; + (* init = 1'h0 *) + reg Ng454 = 1'h0; + (* init = 1'h0 *) + reg Ng464 = 1'h0; + (* init = 1'h0 *) + reg Ng477 = 1'h0; + (* init = 1'h0 *) + reg Ng478 = 1'h0; + (* init = 1'h0 *) + reg Ng479 = 1'h0; + (* init = 1'h0 *) + reg Ng480 = 1'h0; + (* init = 1'h0 *) + reg Ng484 = 1'h0; + (* init = 1'h0 *) + reg Ng486 = 1'h0; + (* init = 1'h0 *) + reg Ng487 = 1'h0; + (* init = 1'h0 *) + reg Ng488 = 1'h0; + (* init = 1'h0 *) + reg Ng489 = 1'h0; + (* init = 1'h0 *) + reg Ng490 = 1'h0; + (* init = 1'h0 *) + reg Ng493 = 1'h0; + (* init = 1'h0 *) + reg Ng496 = 1'h0; + (* init = 1'h0 *) + reg Ng506 = 1'h0; + (* init = 1'h0 *) + reg Ng507 = 1'h0; + (* init = 1'h0 *) + reg Ng510 = 1'h0; + (* init = 1'h0 *) + reg Ng513 = 1'h0; + (* init = 1'h0 *) + reg Ng52 = 1'h0; + (* init = 1'h0 *) + reg Ng523 = 1'h0; + (* init = 1'h0 *) + reg Ng524 = 1'h0; + (* init = 1'h0 *) + reg Ng525 = 1'h0; + (* init = 1'h0 *) + reg Ng528 = 1'h0; + (* init = 1'h0 *) + reg Ng529 = 1'h0; + (* init = 1'h0 *) + reg Ng530 = 1'h0; + (* init = 1'h0 *) + reg Ng531 = 1'h0; + (* init = 1'h0 *) + reg Ng532 = 1'h0; + (* init = 1'h0 *) + reg Ng533 = 1'h0; + (* init = 1'h0 *) + reg Ng534 = 1'h0; + (* init = 1'h0 *) + reg Ng535 = 1'h0; + (* init = 1'h0 *) + reg Ng536 = 1'h0; + (* init = 1'h0 *) + reg Ng537 = 1'h0; + (* init = 1'h0 *) + reg Ng538 = 1'h0; + (* init = 1'h0 *) + reg Ng541 = 1'h0; + (* init = 1'h0 *) + reg Ng542 = 1'h0; + (* init = 1'h0 *) + reg Ng543 = 1'h0; + (* init = 1'h0 *) + reg Ng544 = 1'h0; + (* init = 1'h0 *) + reg Ng548 = 1'h0; + (* init = 1'h0 *) + reg Ng549 = 1'h0; + (* init = 1'h0 *) + reg Ng554 = 1'h0; + (* init = 1'h0 *) + reg Ng557 = 1'h0; + (* init = 1'h0 *) + reg Ng558 = 1'h0; + (* init = 1'h0 *) + reg Ng559 = 1'h0; + (* init = 1'h0 *) + reg Ng56 = 1'h0; + (* init = 1'h0 *) + reg Ng564 = 1'h0; + (* init = 1'h0 *) + reg Ng565 = 1'h0; + (* init = 1'h0 *) + reg Ng566 = 1'h0; + (* init = 1'h0 *) + reg Ng567 = 1'h0; + (* init = 1'h0 *) + reg Ng568 = 1'h0; + (* init = 1'h0 *) + reg Ng569 = 1'h0; + (* init = 1'h0 *) + reg Ng570 = 1'h0; + (* init = 1'h0 *) + reg Ng571 = 1'h0; + (* init = 1'h0 *) + reg Ng572 = 1'h0; + (* init = 1'h0 *) + reg Ng573 = 1'h0; + (* init = 1'h0 *) + reg Ng574 = 1'h0; + (* init = 1'h0 *) + reg Ng575 = 1'h0; + (* init = 1'h0 *) + reg Ng576 = 1'h0; + (* init = 1'h0 *) + reg Ng577 = 1'h0; + (* init = 1'h0 *) + reg Ng578 = 1'h0; + (* init = 1'h0 *) + reg Ng579 = 1'h0; + (* init = 1'h0 *) + reg Ng580 = 1'h0; + (* init = 1'h0 *) + reg Ng581 = 1'h0; + (* init = 1'h0 *) + reg Ng582 = 1'h0; + (* init = 1'h0 *) + reg Ng583 = 1'h0; + (* init = 1'h0 *) + reg Ng584 = 1'h0; + (* init = 1'h0 *) + reg Ng585 = 1'h0; + (* init = 1'h0 *) + reg Ng586 = 1'h0; + (* init = 1'h0 *) + reg Ng587 = 1'h0; + (* init = 1'h0 *) + reg Ng590 = 1'h0; + (* init = 1'h0 *) + reg Ng593 = 1'h0; + (* init = 1'h0 *) + reg Ng596 = 1'h0; + (* init = 1'h0 *) + reg Ng599 = 1'h0; + (* init = 1'h0 *) + reg Ng602 = 1'h0; + (* init = 1'h0 *) + reg Ng605 = 1'h0; + (* init = 1'h0 *) + reg Ng608 = 1'h0; + (* init = 1'h0 *) + reg Ng61 = 1'h0; + (* init = 1'h0 *) + reg Ng611 = 1'h0; + (* init = 1'h0 *) + reg Ng614 = 1'h0; + (* init = 1'h0 *) + reg Ng617 = 1'h0; + (* init = 1'h0 *) + reg Ng620 = 1'h0; + (* init = 1'h0 *) + reg Ng630 = 1'h0; + (* init = 1'h0 *) + reg Ng633 = 1'h0; + (* init = 1'h0 *) + reg Ng640 = 1'h0; + (* init = 1'h0 *) + reg Ng646 = 1'h0; + (* init = 1'h0 *) + reg Ng65 = 1'h0; + (* init = 1'h0 *) + reg Ng653 = 1'h0; + (* init = 1'h0 *) + reg Ng659 = 1'h0; + (* init = 1'h0 *) + reg Ng660 = 1'h0; + (* init = 1'h0 *) + reg Ng666 = 1'h0; + (* init = 1'h0 *) + reg Ng672 = 1'h0; + (* init = 1'h0 *) + reg Ng679 = 1'h0; + (* init = 1'h0 *) + reg Ng686 = 1'h0; + (* init = 1'h0 *) + reg Ng692 = 1'h0; + (* init = 1'h0 *) + reg Ng698 = 1'h0; + (* init = 1'h0 *) + reg Ng699 = 1'h0; + (* init = 1'h0 *) + reg Ng70 = 1'h0; + (* init = 1'h0 *) + reg Ng700 = 1'h0; + (* init = 1'h0 *) + reg Ng701 = 1'h0; + (* init = 1'h0 *) + reg Ng702 = 1'h0; + (* init = 1'h0 *) + reg Ng703 = 1'h0; + (* init = 1'h0 *) + reg Ng704 = 1'h0; + (* init = 1'h0 *) + reg Ng705 = 1'h0; + (* init = 1'h0 *) + reg Ng706 = 1'h0; + (* init = 1'h0 *) + reg Ng707 = 1'h0; + (* init = 1'h0 *) + reg Ng708 = 1'h0; + (* init = 1'h0 *) + reg Ng709 = 1'h0; + (* init = 1'h0 *) + reg Ng710 = 1'h0; + (* init = 1'h0 *) + reg Ng711 = 1'h0; + (* init = 1'h0 *) + reg Ng712 = 1'h0; + (* init = 1'h0 *) + reg Ng713 = 1'h0; + (* init = 1'h0 *) + reg Ng714 = 1'h0; + (* init = 1'h0 *) + reg Ng715 = 1'h0; + (* init = 1'h0 *) + reg Ng716 = 1'h0; + (* init = 1'h0 *) + reg Ng717 = 1'h0; + (* init = 1'h0 *) + reg Ng718 = 1'h0; + (* init = 1'h0 *) + reg Ng719 = 1'h0; + (* init = 1'h0 *) + reg Ng720 = 1'h0; + (* init = 1'h0 *) + reg Ng721 = 1'h0; + (* init = 1'h0 *) + reg Ng722 = 1'h0; + (* init = 1'h0 *) + reg Ng723 = 1'h0; + (* init = 1'h0 *) + reg Ng724 = 1'h0; + (* init = 1'h0 *) + reg Ng725 = 1'h0; + (* init = 1'h0 *) + reg Ng726 = 1'h0; + (* init = 1'h0 *) + reg Ng727 = 1'h0; + (* init = 1'h0 *) + reg Ng728 = 1'h0; + (* init = 1'h0 *) + reg Ng729 = 1'h0; + (* init = 1'h0 *) + reg Ng730 = 1'h0; + (* init = 1'h0 *) + reg Ng731 = 1'h0; + (* init = 1'h0 *) + reg Ng732 = 1'h0; + (* init = 1'h0 *) + reg Ng733 = 1'h0; + (* init = 1'h0 *) + reg Ng734 = 1'h0; + (* init = 1'h0 *) + reg Ng735 = 1'h0; + (* init = 1'h0 *) + reg Ng736 = 1'h0; + (* init = 1'h0 *) + reg Ng737 = 1'h0; + (* init = 1'h0 *) + reg Ng738 = 1'h0; + (* init = 1'h0 *) + reg Ng739 = 1'h0; + (* init = 1'h0 *) + reg Ng74 = 1'h0; + (* init = 1'h0 *) + reg Ng740 = 1'h0; + (* init = 1'h0 *) + reg Ng744 = 1'h0; + (* init = 1'h0 *) + reg Ng749 = 1'h0; + (* init = 1'h0 *) + reg Ng753 = 1'h0; + (* init = 1'h0 *) + reg Ng758 = 1'h0; + (* init = 1'h0 *) + reg Ng762 = 1'h0; + (* init = 1'h0 *) + reg Ng767 = 1'h0; + (* init = 1'h0 *) + reg Ng771 = 1'h0; + (* init = 1'h0 *) + reg Ng776 = 1'h0; + (* init = 1'h0 *) + reg Ng780 = 1'h0; + (* init = 1'h0 *) + reg Ng785 = 1'h0; + (* init = 1'h0 *) + reg Ng789 = 1'h0; + (* init = 1'h0 *) + reg Ng79 = 1'h0; + (* init = 1'h0 *) + reg Ng793 = 1'h0; + (* init = 1'h0 *) + reg Ng797 = 1'h0; + (* init = 1'h0 *) + reg Ng801 = 1'h0; + (* init = 1'h0 *) + reg Ng805 = 1'h0; + (* init = 1'h0 *) + reg Ng809 = 1'h0; + (* init = 1'h0 *) + reg Ng813 = 1'h0; + (* init = 1'h0 *) + reg Ng817 = 1'h0; + (* init = 1'h0 *) + reg Ng818 = 1'h0; + (* init = 1'h0 *) + reg Ng819 = 1'h0; + (* init = 1'h0 *) + reg Ng820 = 1'h0; + (* init = 1'h0 *) + reg Ng821 = 1'h0; + (* init = 1'h0 *) + reg Ng822 = 1'h0; + (* init = 1'h0 *) + reg Ng8284 = 1'h0; + (* init = 1'h0 *) + reg Ng829 = 1'h0; + (* init = 1'h0 *) + reg Ng8293 = 1'h0; + (* init = 1'h0 *) + reg Ng83 = 1'h0; + (* init = 1'h0 *) + reg Ng830 = 1'h0; + (* init = 1'h0 *) + reg Ng8302 = 1'h0; + (* init = 1'h0 *) + reg Ng831 = 1'h0; + (* init = 1'h0 *) + reg Ng8311 = 1'h0; + (* init = 1'h0 *) + reg Ng832 = 1'h0; + (* init = 1'h0 *) + reg Ng833 = 1'h0; + (* init = 1'h0 *) + reg Ng834 = 1'h0; + (* init = 1'h0 *) + reg Ng835 = 1'h0; + (* init = 1'h0 *) + reg Ng836 = 1'h0; + (* init = 1'h0 *) + reg Ng837 = 1'h0; + (* init = 1'h0 *) + reg Ng838 = 1'h0; + (* init = 1'h0 *) + reg Ng839 = 1'h0; + (* init = 1'h0 *) + reg Ng840 = 1'h0; + (* init = 1'h0 *) + reg Ng841 = 1'h0; + (* init = 1'h0 *) + reg Ng842 = 1'h0; + (* init = 1'h0 *) + reg Ng843 = 1'h0; + (* init = 1'h0 *) + reg Ng844 = 1'h0; + (* init = 1'h0 *) + reg Ng845 = 1'h0; + (* init = 1'h0 *) + reg Ng846 = 1'h0; + (* init = 1'h0 *) + reg Ng847 = 1'h0; + (* init = 1'h0 *) + reg Ng848 = 1'h0; + (* init = 1'h0 *) + reg Ng849 = 1'h0; + (* init = 1'h0 *) + reg Ng850 = 1'h0; + (* init = 1'h0 *) + reg Ng851 = 1'h0; + (* init = 1'h0 *) + reg Ng852 = 1'h0; + (* init = 1'h0 *) + reg Ng853 = 1'h0; + (* init = 1'h0 *) + reg Ng856 = 1'h0; + (* init = 1'h0 *) + reg Ng857 = 1'h0; + (* init = 1'h0 *) + reg Ng858 = 1'h0; + (* init = 1'h0 *) + reg Ng859 = 1'h0; + (* init = 1'h0 *) + reg Ng860 = 1'h0; + (* init = 1'h0 *) + reg Ng861 = 1'h0; + (* init = 1'h0 *) + reg Ng862 = 1'h0; + (* init = 1'h0 *) + reg Ng863 = 1'h0; + (* init = 1'h0 *) + reg Ng864 = 1'h0; + (* init = 1'h0 *) + reg Ng865 = 1'h0; + (* init = 1'h0 *) + reg Ng866 = 1'h0; + (* init = 1'h0 *) + reg Ng867 = 1'h0; + (* init = 1'h0 *) + reg Ng873 = 1'h0; + (* init = 1'h0 *) + reg Ng876 = 1'h0; + (* init = 1'h0 *) + reg Ng879 = 1'h0; + (* init = 1'h0 *) + reg Ng88 = 1'h0; + (* init = 1'h0 *) + reg Ng882 = 1'h0; + (* init = 1'h0 *) + reg Ng885 = 1'h0; + (* init = 1'h0 *) + reg Ng888 = 1'h0; + (* init = 1'h0 *) + reg Ng891 = 1'h0; + (* init = 1'h0 *) + reg Ng894 = 1'h0; + (* init = 1'h0 *) + reg Ng897 = 1'h0; + (* init = 1'h0 *) + reg Ng900 = 1'h0; + (* init = 1'h0 *) + reg Ng903 = 1'h0; + (* init = 1'h0 *) + reg Ng906 = 1'h0; + (* init = 1'h0 *) + reg Ng909 = 1'h0; + (* init = 1'h0 *) + reg Ng912 = 1'h0; + (* init = 1'h0 *) + reg Ng915 = 1'h0; + (* init = 1'h0 *) + reg Ng918 = 1'h0; + (* init = 1'h0 *) + reg Ng92 = 1'h0; + (* init = 1'h0 *) + reg Ng921 = 1'h0; + (* init = 1'h0 *) + reg Ng924 = 1'h0; + (* init = 1'h0 *) + reg Ng927 = 1'h0; + (* init = 1'h0 *) + reg Ng930 = 1'h0; + (* init = 1'h0 *) + reg Ng933 = 1'h0; + (* init = 1'h0 *) + reg Ng936 = 1'h0; + (* init = 1'h0 *) + reg Ng939 = 1'h0; + (* init = 1'h0 *) + reg Ng942 = 1'h0; + (* init = 1'h0 *) + reg Ng945 = 1'h0; + (* init = 1'h0 *) + reg Ng948 = 1'h0; + (* init = 1'h0 *) + reg Ng951 = 1'h0; + (* init = 1'h0 *) + reg Ng954 = 1'h0; + (* init = 1'h0 *) + reg Ng957 = 1'h0; + (* init = 1'h0 *) + reg Ng960 = 1'h0; + (* init = 1'h0 *) + reg Ng966 = 1'h0; + (* init = 1'h0 *) + reg Ng967 = 1'h0; + (* init = 1'h0 *) + reg Ng968 = 1'h0; + (* init = 1'h0 *) + reg Ng969 = 1'h0; + (* init = 1'h0 *) + reg Ng97 = 1'h0; + (* init = 1'h0 *) + reg Ng970 = 1'h0; + (* init = 1'h0 *) + reg Ng971 = 1'h0; + (* init = 1'h0 *) + reg Ng972 = 1'h0; + (* init = 1'h0 *) + reg Ng973 = 1'h0; + (* init = 1'h0 *) + reg Ng974 = 1'h0; + (* init = 1'h0 *) + reg Ng975 = 1'h0; + (* init = 1'h0 *) + reg Ng976 = 1'h0; + (* init = 1'h0 *) + reg Ng977 = 1'h0; + (* init = 1'h0 *) + reg Ng978 = 1'h0; + (* init = 1'h0 *) + reg Ng985 = 1'h0; + (* init = 1'h0 *) + reg Ng986 = 1'h0; + (* init = 1'h0 *) + reg Ng992 = 1'h0; + (* init = 1'h0 *) + reg Ng999 = 1'h0; + input Pg1249; + (* init = 1'h0 *) + output Pg16297; + reg Pg16297 = 1'h0; + (* init = 1'h0 *) + output Pg16355; + reg Pg16355 = 1'h0; + (* init = 1'h0 *) + output Pg16399; + reg Pg16399 = 1'h0; + (* init = 1'h0 *) + output Pg16437; + reg Pg16437 = 1'h0; + output Pg16496; + input Pg1943; + output Pg24734; + output Pg25420; + output Pg25435; + output Pg25442; + output Pg25489; + output Pg26104; + output Pg26135; + output Pg26149; + input Pg2637; + output Pg27380; + input Pg3212; + input Pg3213; + input Pg3214; + input Pg3215; + input Pg3216; + input Pg3217; + input Pg3218; + input Pg3219; + input Pg3220; + input Pg3221; + input Pg3222; + input Pg3223; + input Pg3224; + input Pg3225; + input Pg3226; + input Pg3227; + input Pg3228; + input Pg3229; + input Pg3230; + input Pg3231; + input Pg3232; + input Pg3233; + input Pg3234; + (* init = 1'h0 *) + output Pg3993; + reg Pg3993 = 1'h0; + (* init = 1'h0 *) + output Pg4088; + reg Pg4088 = 1'h0; + (* init = 1'h0 *) + output Pg4090; + reg Pg4090 = 1'h0; + (* init = 1'h0 *) + output Pg4200; + reg Pg4200 = 1'h0; + (* init = 1'h0 *) + output Pg4321; + reg Pg4321 = 1'h0; + (* init = 1'h0 *) + output Pg4323; + reg Pg4323 = 1'h0; + (* init = 1'h0 *) + output Pg4450; + reg Pg4450 = 1'h0; + (* init = 1'h0 *) + output Pg4590; + reg Pg4590 = 1'h0; + input Pg51; + (* init = 1'h0 *) + output Pg5388; + reg Pg5388 = 1'h0; + (* init = 1'h0 *) + output Pg5437; + reg Pg5437 = 1'h0; + output Pg5472; + output Pg5511; + (* init = 1'h0 *) + output Pg5549; + reg Pg5549 = 1'h0; + output Pg5555; + output Pg5595; + output Pg5612; + (* init = 1'h0 *) + output Pg5629; + reg Pg5629 = 1'h0; + input Pg563; + output Pg5637; + (* init = 1'h0 *) + output Pg5648; + reg Pg5648 = 1'h0; + output Pg5657; + output Pg5686; + output Pg5695; + output Pg5738; + output Pg5747; + output Pg5796; + (* init = 1'h0 *) + output Pg6225; + reg Pg6225 = 1'h0; + output Pg6231; + (* init = 1'h0 *) + output Pg6313; + reg Pg6313 = 1'h0; + output Pg6368; + (* init = 1'h0 *) + output Pg6442; + reg Pg6442 = 1'h0; + output Pg6447; + output Pg6485; + output Pg6518; + output Pg6573; + output Pg6642; + output Pg6677; + output Pg6712; + output Pg6750; + output Pg6782; + output Pg6837; + (* init = 1'h0 *) + output Pg6895; + reg Pg6895 = 1'h0; + output Pg6911; + output Pg6944; + output Pg6979; + output Pg7014; + output Pg7052; + output Pg7084; + output Pg7161; + output Pg7194; + output Pg7229; + output Pg7264; + output Pg7302; + (* init = 1'h0 *) + output Pg7334; + reg Pg7334 = 1'h0; + output Pg7357; + output Pg7390; + output Pg7425; + output Pg7487; + (* init = 1'h0 *) + output Pg7519; + reg Pg7519 = 1'h0; + output Pg7909; + output Pg7956; + output Pg7961; + output Pg8007; + output Pg8012; + (* init = 1'h0 *) + output Pg8021; + reg Pg8021 = 1'h0; + (* init = 1'h0 *) + output Pg8023; + reg Pg8023 = 1'h0; + output Pg8030; + output Pg8082; + output Pg8087; + (* init = 1'h0 *) + output Pg8096; + reg Pg8096 = 1'h0; + output Pg8106; + output Pg8167; + (* init = 1'h0 *) + output Pg8175; + reg Pg8175 = 1'h0; + (* init = 1'h0 *) + output Pg8249; + reg Pg8249 = 1'h0; + (* init = 1'h0 *) + output Pg8251; + reg Pg8251 = 1'h0; + (* init = 1'h0 *) + output Pg8258; + reg Pg8258 = 1'h0; + (* init = 1'h0 *) + output Pg8259; + reg Pg8259 = 1'h0; + (* init = 1'h0 *) + output Pg8260; + reg Pg8260 = 1'h0; + (* init = 1'h0 *) + output Pg8261; + reg Pg8261 = 1'h0; + (* init = 1'h0 *) + output Pg8262; + reg Pg8262 = 1'h0; + (* init = 1'h0 *) + output Pg8263; + reg Pg8263 = 1'h0; + (* init = 1'h0 *) + output Pg8264; + reg Pg8264 = 1'h0; + (* init = 1'h0 *) + output Pg8265; + reg Pg8265 = 1'h0; + (* init = 1'h0 *) + output Pg8266; + reg Pg8266 = 1'h0; + (* init = 1'h0 *) + output Pg8267; + reg Pg8267 = 1'h0; + (* init = 1'h0 *) + output Pg8268; + reg Pg8268 = 1'h0; + (* init = 1'h0 *) + output Pg8269; + reg Pg8269 = 1'h0; + (* init = 1'h0 *) + output Pg8270; + reg Pg8270 = 1'h0; + (* init = 1'h0 *) + output Pg8271; + reg Pg8271 = 1'h0; + (* init = 1'h0 *) + output Pg8272; + reg Pg8272 = 1'h0; + (* init = 1'h0 *) + output Pg8273; + reg Pg8273 = 1'h0; + (* init = 1'h0 *) + output Pg8274; + reg Pg8274 = 1'h0; + (* init = 1'h0 *) + output Pg8275; + reg Pg8275 = 1'h0; + input clock; + wire n1003_1; + wire n1008; + wire n1013; + wire n1018_1; + wire n1023; + wire n1028; + wire n1033_1; + wire n1038; + wire n1043; + wire n1048_1; + wire n1053_1; + wire n1058; + wire n1063_1; + wire n1068; + wire n1073; + wire n1078; + wire n1083; + wire n1088; + wire n1093; + wire n1098; + wire n1103; + wire n1108_1; + wire n1113; + wire n1118; + wire n1123; + wire n1128; + wire n1133; + wire n1138; + wire n1143; + wire n1148; + wire n1153; + wire n1158; + wire n1163; + wire n1168; + wire n1173; + wire n1178_1; + wire n1183; + wire n1188; + wire n1193; + wire n1198; + wire n1203; + wire n1208; + wire n1213; + wire n1218; + wire n1223; + wire n1228; + wire n1233; + wire n1238; + wire n1243; + wire n1248; + wire n1253; + wire n1258; + wire n1263; + wire n1268_1; + wire n1273; + wire n1278_1; + wire n1283; + wire n1288_1; + wire n1293; + wire n1298_1; + wire n1303_1; + wire n1308; + wire n1313_1; + wire n1318_1; + wire n1323; + wire n1328; + wire n1333; + wire n1338; + wire n1343; + wire n1348_1; + wire n1353_1; + wire n1358; + wire n1363; + wire n1368_1; + wire n1373; + wire n1378; + wire n1383_1; + wire n1388_1; + wire n1393_1; + wire n1398; + wire n1403_1; + wire n1408; + wire n1413_1; + wire n1418; + wire n1423; + wire n1428; + wire n1433; + wire n1438; + wire n1443; + wire n1448; + wire n1453_1; + wire n1458; + wire n1463; + wire n1468; + wire n1473; + wire n1478; + wire n1483; + wire n1488; + wire n1493_1; + wire n1498_1; + wire n1503_1; + wire n1508_1; + wire n1513; + wire n1518; + wire n1523; + wire n1528_1; + wire n1533; + wire n1538; + wire n1543; + wire n1548; + wire n1553; + wire n1558; + wire n1563; + wire n1568; + wire n1573; + wire n1578_1; + wire n1583; + wire n1588; + wire n1593; + wire n1598; + wire n1603; + wire n1608; + wire n1613_1; + wire n1618; + wire n1623; + wire n1627; + wire n1632; + wire n1636; + wire n1641; + wire n1645; + wire n1650; + wire n1654; + wire n1659; + wire n1663; + wire n1668; + wire n1672; + wire n1677; + wire n1681; + wire n1686; + wire n1690; + wire n1694; + wire n1698; + wire n1703; + wire n1708; + wire n1713; + wire n1717; + wire n1721; + wire n1725; + wire n1729; + wire n1733; + wire n1737; + wire n1741; + wire n1745; + wire n1749; + wire n1753; + wire n1757; + wire n1761; + wire n1765; + wire n1769; + wire n1773; + wire n1777; + wire n1781; + wire n1785; + wire n1789; + wire n1793; + wire n1797; + wire n1801; + wire n1805; + wire n1809; + wire n1814; + wire n1819; + wire n1824; + wire n1829_1; + wire n1833_1; + wire n1837; + wire n1842; + wire n1846; + wire n1851; + wire n1855; + wire n1860; + wire n1864; + wire n1869; + wire n1873; + wire n1878; + wire n1882; + wire n1887; + wire n1891; + wire n1896; + wire n1901; + wire n1906; + wire n1911; + wire n1915; + wire n1919; + wire n1923; + wire n1928; + wire n1933; + wire n1938; + wire n1943; + wire n1948; + wire n1953; + wire n1957; + wire n1961; + wire n1965_1; + wire n1969; + wire n1973; + wire n1978; + wire n1982; + wire n1987; + wire n1992; + wire n1996; + wire n2001; + wire n2005; + wire n2010_1; + wire n2015; + wire n2020; + wire n2025; + wire n2030_1; + wire n2035; + wire n2040_1; + wire n2045; + wire n2050; + wire n2055; + wire n2060; + wire n2065; + wire n2070; + wire n2075; + wire n2080; + wire n2085; + wire n2090; + wire n2095; + wire n2100; + wire n2105; + wire n2110; + wire n2115; + wire n2120; + wire n2125; + wire n2130; + wire n2135; + wire n2140; + wire n2144; + wire n2149; + wire n2153; + wire n2158; + wire n2163; + wire n2168; + wire n2173; + wire n2178; + wire n2183; + wire n2188; + wire n2193; + wire n2198; + wire n2203; + wire n2208; + wire n2213; + wire n2218; + wire n2223; + wire n2228; + wire n2233; + wire n2238; + wire n2243; + wire n2248; + wire n2253; + wire n2258; + wire n2263; + wire n2268; + wire n2273; + wire n2278; + wire n2283; + wire n2288; + wire n2293; + wire n2298; + wire n2303; + wire n2308; + wire n2313; + wire n2318; + wire n2323; + wire n2328; + wire n2333; + wire n2338; + wire n2343; + wire n2348; + wire n2353; + wire n2358; + wire n2363; + wire n2368; + wire n2373; + wire n2378; + wire n2383; + wire n2388; + wire n2393; + wire n2398; + wire n2403; + wire n2408; + wire n2413; + wire n2418; + wire n2423; + wire n2428; + wire n2433; + wire n2438; + wire n2443; + wire n2448; + wire n2453; + wire n2458; + wire n2463; + wire n2468; + wire n2473; + wire n2477; + wire n2480; + wire n2483; + wire n2488; + wire n2493; + wire n2498; + wire n2503; + wire n2508; + wire n2513; + wire n2518; + wire n2523; + wire n2528; + wire n2533; + wire n2538; + wire n2543; + wire n2548; + wire n2553; + wire n2558; + wire n2563; + wire n2568; + wire n2573; + wire n2578; + wire n2583; + wire n2588; + wire n2593; + wire n2598; + wire n2603; + wire n2608; + wire n2613; + wire n2618; + wire n2623; + wire n2628; + wire n2633; + wire n2638; + wire n2643; + wire n2648; + wire n2653; + wire n2658; + wire n2663; + wire n2668; + wire n2673; + wire n2678; + wire n2683; + wire n2688; + wire n2693; + wire n2698; + wire n2703; + wire n2708; + wire n271; + wire n2713; + wire n2718; + wire n2723; + wire n2728; + wire n2733; + wire n2738; + wire n2743; + wire n2748; + wire n275; + wire n2753; + wire n2758; + wire n2763; + wire n2768; + wire n2773; + wire n2778; + wire n2783; + wire n2788; + wire n279; + wire n2793; + wire n2798; + wire n2803; + wire n2808; + wire n2813; + wire n2818; + wire n2823; + wire n2828; + wire n283; + wire n2833; + wire n2838; + wire n2843; + wire n2848; + wire n2853; + wire n2858; + wire n2863; + wire n2868; + wire n287; + wire n2873; + wire n2878; + wire n2883; + wire n2888; + wire n2893; + wire n2898; + wire n2903; + wire n2908; + wire n291; + wire n2913; + wire n2918; + wire n2923; + wire n2928; + wire n2933; + wire n2938; + wire n2943; + wire n2948; + wire n295; + wire n2953; + wire n2958; + wire n2963; + wire n2968; + wire n2973; + wire n2978; + wire n2983; + wire n2988; + wire n299; + wire n2993; + wire n2998; + wire n3003; + wire n3008; + wire n3013; + wire n3018; + wire n3023; + wire n3028; + wire n303; + wire n3033; + wire n3038; + wire n3043; + wire n3048; + wire n3053; + wire n3058; + wire n3063; + wire n3068; + wire n307; + wire n3073; + wire n3078; + wire n3083; + wire n3088; + wire n3093; + wire n3098; + wire n3103; + wire n3108; + wire n311; + wire n3113; + wire n3118; + wire n3123; + wire n3127; + wire n3132; + wire n3136; + wire n3141; + wire n3145; + wire n315; + wire n3150; + wire n3154; + wire n3159; + wire n3163; + wire n3168; + wire n3172; + wire n3177; + wire n3181; + wire n3186; + wire n319; + wire n3190; + wire n3194; + wire n3198; + wire n3203; + wire n3208; + wire n3213; + wire n3217; + wire n3221; + wire n3225; + wire n3229; + wire n323; + wire n3233; + wire n3237; + wire n3241; + wire n3245; + wire n3249; + wire n3253; + wire n3257; + wire n3261; + wire n3265; + wire n3269; + wire n327; + wire n3273; + wire n3277; + wire n3281; + wire n3285; + wire n3289; + wire n3293; + wire n3297; + wire n3301; + wire n3305; + wire n3309; + wire n331; + wire n3314; + wire n3319; + wire n3324; + wire n3329; + wire n3333; + wire n3337; + wire n3342; + wire n3346; + wire n335; + wire n3351; + wire n3355; + wire n3360; + wire n3364; + wire n3369; + wire n3373; + wire n3378; + wire n3382; + wire n3387; + wire n3391; + wire n3396; + wire n339_1; + wire n3401; + wire n3406; + wire n3411; + wire n3415; + wire n3419; + wire n3423; + wire n3428; + wire n343; + wire n3433; + wire n3438; + wire n3443; + wire n3448; + wire n3453; + wire n3457; + wire n3461; + wire n3465; + wire n3469; + wire n347; + wire n3473; + wire n3478; + wire n3482; + wire n3487; + wire n3492; + wire n3496; + wire n3501; + wire n3505; + wire n351; + wire n3510; + wire n3515; + wire n3520; + wire n3525; + wire n3530; + wire n3535; + wire n3540; + wire n3545; + wire n355; + wire n3550; + wire n3555; + wire n3560; + wire n3565; + wire n3570; + wire n3575; + wire n3580; + wire n3585; + wire n359; + wire n3590; + wire n3595; + wire n3600; + wire n3605; + wire n3610; + wire n3615; + wire n3620; + wire n3625; + wire n363; + wire n3630; + wire n3635; + wire n3640; + wire n3644; + wire n3649; + wire n3653; + wire n3658; + wire n3663; + wire n3668; + wire n367; + wire n3673; + wire n3678; + wire n3683; + wire n3688; + wire n3693; + wire n3698; + wire n3703; + wire n3708; + wire n371; + wire n3711; + wire n3714; + wire n3719; + wire n3724; + wire n3729; + wire n3734; + wire n3739; + wire n3744; + wire n3749; + wire n375; + wire n3754; + wire n3759; + wire n3764; + wire n3769; + wire n3774; + wire n3779; + wire n378; + wire n3784; + wire n3789; + wire n3794; + wire n3799; + wire n3804; + wire n3809; + wire n3814; + wire n3819; + wire n382; + wire n3824; + wire n3829; + wire n3834; + wire n3839; + wire n3844; + wire n3849; + wire n3854; + wire n3859; + wire n386; + wire n3864; + wire n3869; + wire n3874; + wire n3879; + wire n3884; + wire n3889; + wire n3894; + wire n3899; + wire n390; + wire n3904; + wire n3909; + wire n3914; + wire n3919; + wire n3924; + wire n3929; + wire n3934; + wire n3939; + wire n394; + wire n3944; + wire n3949; + wire n3954; + wire n3959; + wire n3964; + wire n3969; + wire n3974; + wire n3979; + wire n398; + wire n3984; + wire n3989; + wire n3994; + wire n3999; + wire n4004; + wire n4009; + wire n401; + wire n4014; + wire n4019; + wire n4024; + wire n4029; + wire n4034; + wire n4039; + wire n4044; + wire n4049; + wire n405; + wire n4054; + wire n4059; + wire n4064; + wire n4069; + wire n4074; + wire n4079; + wire n4084; + wire n4089; + wire n409; + wire n4094; + wire n4099; + wire n4104; + wire n4109; + wire n4114; + wire n4119; + wire n4124; + wire n4129; + wire n413; + wire n4134; + wire n4139; + wire n4144; + wire n4149; + wire n4154; + wire n4159; + wire n4164; + wire n4169; + wire n417; + wire n4174; + wire n4179; + wire n4184; + wire n4189; + wire n4194; + wire n4199; + wire n4204; + wire n4209; + wire n421; + wire n4214; + wire n4219; + wire n4224; + wire n4229; + wire n4234; + wire n4239; + wire n4244; + wire n4249; + wire n425; + wire n4254; + wire n4259; + wire n4264; + wire n4269; + wire n4274; + wire n4279; + wire n4284; + wire n4289; + wire n429; + wire n4294; + wire n4299; + wire n4304; + wire n4309; + wire n4314; + wire n4319; + wire n4324; + wire n4329; + wire n433; + wire n4334; + wire n4339; + wire n4344; + wire n4349; + wire n4354; + wire n4359; + wire n4364; + wire n4369; + wire n437; + wire n4374; + wire n4379; + wire n4384; + wire n4389; + wire n4394; + wire n4399; + wire n4404; + wire n4409; + wire n4414; + wire n4419; + wire n442; + wire n4424; + wire n4429; + wire n4434; + wire n4439; + wire n4444; + wire n4449; + wire n4454; + wire n4459; + wire n4464; + wire n4469; + wire n447; + wire n4474; + wire n4479; + wire n4484; + wire n4489; + wire n4494; + wire n4499; + wire n4504; + wire n4509; + wire n4514; + wire n4519; + wire n452; + wire n4524; + wire n4525; + wire n4526; + wire n4527; + wire n4528; + wire n4529; + wire n4529_1; + wire n4530; + wire n4531; + wire n4532; + wire n4533; + wire n4534; + wire n4534_1; + wire n4535; + wire n4536; + wire n4537; + wire n4538; + wire n4539; + wire n4539_1; + wire n4540; + wire n4541; + wire n4542; + wire n4543; + wire n4544; + wire n4545; + wire n4549; + wire n4551; + wire n4554; + wire n4556; + wire n4557; + wire n4558; + wire n4559; + wire n4563; + wire n4564; + wire n4564_1; + wire n4565; + wire n4567; + wire n4568; + wire n4569; + wire n4569_1; + wire n457; + wire n4571; + wire n4572; + wire n4573; + wire n4574; + wire n4575; + wire n4576; + wire n4577; + wire n4579; + wire n4584; + wire n4586; + wire n4587; + wire n4588; + wire n4589; + wire n4589_1; + wire n4590; + wire n4591; + wire n4592; + wire n4593; + wire n4594; + wire n4594_1; + wire n4595; + wire n4596; + wire n4597; + wire n4598; + wire n4599; + wire n4599_1; + wire n4600; + wire n4601; + wire n4602; + wire n4603; + wire n4604; + wire n4604_1; + wire n4605; + wire n4606; + wire n4607; + wire n4609; + wire n4609_1; + wire n4610; + wire n4611; + wire n4613; + wire n4614; + wire n4614_1; + wire n4616; + wire n4618; + wire n4619; + wire n4619_1; + wire n462; + wire n4620; + wire n4621; + wire n4623; + wire n4624; + wire n4624_1; + wire n4626; + wire n4628; + wire n4628_1; + wire n4629; + wire n4630; + wire n4631; + wire n4632; + wire n4633; + wire n4633_1; + wire n4634; + wire n4635; + wire n4636; + wire n4637; + wire n4637_1; + wire n4638; + wire n4639; + wire n4640; + wire n4641; + wire n4642; + wire n4642_1; + wire n4643; + wire n4644; + wire n4645; + wire n4646; + wire n4646_1; + wire n4647; + wire n4648; + wire n4649; + wire n4650; + wire n4651; + wire n4651_1; + wire n4652; + wire n4654; + wire n4655; + wire n4656; + wire n4658; + wire n4659; + wire n4660; + wire n4660_1; + wire n4662; + wire n4663; + wire n4664; + wire n4665; + wire n4667; + wire n4669; + wire n4669_1; + wire n467; + wire n4670; + wire n4671; + wire n4672; + wire n4673; + wire n4673_1; + wire n4674; + wire n4675; + wire n4676; + wire n4677; + wire n4678; + wire n4678_1; + wire n4679; + wire n4680; + wire n4681; + wire n4682; + wire n4682_1; + wire n4683; + wire n4684; + wire n4685; + wire n4686; + wire n4687; + wire n4687_1; + wire n4688; + wire n4689; + wire n4690; + wire n4691; + wire n4691_1; + wire n4692; + wire n4693; + wire n4694; + wire n4695; + wire n4695_1; + wire n4696; + wire n4697; + wire n4698; + wire n4699; + wire n4700; + wire n4701; + wire n4704; + wire n4704_1; + wire n4706; + wire n4707; + wire n4709; + wire n4709_1; + wire n4712; + wire n4713; + wire n4714; + wire n4714_1; + wire n4715; + wire n4716; + wire n4717; + wire n4718; + wire n4718_1; + wire n4719; + wire n472; + wire n4720; + wire n4721; + wire n4722; + wire n4722_1; + wire n4723; + wire n4724; + wire n4725; + wire n4726; + wire n4726_1; + wire n4727; + wire n4728; + wire n4729; + wire n4730; + wire n4730_1; + wire n4731; + wire n4732; + wire n4733; + wire n4734; + wire n4734_1; + wire n4735; + wire n4736; + wire n4737; + wire n4738; + wire n4739; + wire n4740; + wire n4742_1; + wire n4744; + wire n4745; + wire n4746; + wire n4746_1; + wire n4748; + wire n4750; + wire n4754; + wire n4756; + wire n4757; + wire n4758; + wire n4758_1; + wire n4759; + wire n4760; + wire n4761; + wire n4762; + wire n4762_1; + wire n4763; + wire n4764; + wire n4765; + wire n4766; + wire n4766_1; + wire n4767; + wire n4768; + wire n4769; + wire n477; + wire n4770; + wire n4770_1; + wire n4771; + wire n4772; + wire n4773; + wire n4774; + wire n4774_1; + wire n4775; + wire n4776; + wire n4777; + wire n4778; + wire n4778_1; + wire n4779; + wire n4780; + wire n4781; + wire n4782; + wire n4782_1; + wire n4783; + wire n4784; + wire n4785; + wire n4786; + wire n4786_1; + wire n4787; + wire n4788; + wire n4789; + wire n4790; + wire n4790_1; + wire n4791; + wire n4792; + wire n4793; + wire n4794; + wire n4794_1; + wire n4795; + wire n4796; + wire n4797; + wire n4798; + wire n4798_1; + wire n4799; + wire n4800; + wire n4801; + wire n4802; + wire n4802_1; + wire n4803; + wire n4804; + wire n4805; + wire n4806; + wire n4806_1; + wire n4807; + wire n4808; + wire n4809; + wire n4810; + wire n4810_1; + wire n4811; + wire n4812; + wire n4813; + wire n4814; + wire n4815; + wire n4815_1; + wire n4816; + wire n482; + wire n4820; + wire n4820_1; + wire n4821; + wire n4822; + wire n4823; + wire n4824; + wire n4825; + wire n4825_1; + wire n4826; + wire n4827; + wire n4828; + wire n4829; + wire n4830; + wire n4830_1; + wire n4831; + wire n4832; + wire n4833; + wire n4834; + wire n4834_1; + wire n4835; + wire n4838_1; + wire n4839; + wire n4843; + wire n4843_1; + wire n4844; + wire n4847; + wire n4848; + wire n4849; + wire n4852; + wire n4853; + wire n4854; + wire n4856_1; + wire n4858; + wire n4859; + wire n4860; + wire n4861; + wire n4861_1; + wire n4862; + wire n4863; + wire n4864; + wire n4865; + wire n4865_1; + wire n4866; + wire n4867; + wire n4868; + wire n4869; + wire n487; + wire n4870; + wire n4870_1; + wire n4871; + wire n4872; + wire n4873; + wire n4874; + wire n4874_1; + wire n4875; + wire n4876; + wire n4877; + wire n4878; + wire n4879; + wire n4879_1; + wire n4880; + wire n4881; + wire n4882; + wire n4883; + wire n4883_1; + wire n4884; + wire n4885; + wire n4886; + wire n4887; + wire n4888; + wire n4888_1; + wire n4889; + wire n4890; + wire n4891; + wire n4892; + wire n4892_1; + wire n4893; + wire n4894; + wire n4895; + wire n4896; + wire n4897; + wire n4897_1; + wire n4898; + wire n4899; + wire n4900; + wire n4901; + wire n4902; + wire n4902_1; + wire n4903; + wire n4904; + wire n4905; + wire n4906; + wire n4907; + wire n4907_1; + wire n4908; + wire n4909; + wire n4910; + wire n4911; + wire n4912; + wire n4912_1; + wire n4913; + wire n4914; + wire n4915; + wire n4916; + wire n4916_1; + wire n492; + wire n4920; + wire n4920_1; + wire n4921; + wire n4922; + wire n4923; + wire n4924; + wire n4924_1; + wire n4925; + wire n4926; + wire n4927; + wire n4928; + wire n4929; + wire n4929_1; + wire n4930; + wire n4931; + wire n4932; + wire n4933; + wire n4934; + wire n4934_1; + wire n4935; + wire n4936; + wire n4939; + wire n4940; + wire n4941; + wire n4942; + wire n4944; + wire n4946; + wire n4947; + wire n4948; + wire n4949; + wire n4952; + wire n4953; + wire n4954; + wire n4954_1; + wire n4958; + wire n4958_1; + wire n4959; + wire n4962; + wire n4963; + wire n4964; + wire n4965; + wire n4966; + wire n4966_1; + wire n4967; + wire n4968; + wire n4969; + wire n497; + wire n4970; + wire n4970_1; + wire n4971; + wire n4972; + wire n4973; + wire n4974; + wire n4974_1; + wire n4975; + wire n4976; + wire n4977; + wire n4978; + wire n4979; + wire n4979_1; + wire n4980; + wire n4981; + wire n4982; + wire n4983; + wire n4983_1; + wire n4984; + wire n4985; + wire n4986; + wire n4987; + wire n4988; + wire n4988_1; + wire n4989; + wire n4990; + wire n4991; + wire n4992; + wire n4993; + wire n4993_1; + wire n4994; + wire n4995; + wire n4996; + wire n4997; + wire n4997_1; + wire n4998; + wire n4999; + wire n5000; + wire n5001; + wire n5002; + wire n5002_1; + wire n5003; + wire n5004; + wire n5005; + wire n5006; + wire n5006_1; + wire n5007; + wire n5008; + wire n5009; + wire n5010; + wire n5011; + wire n5011_1; + wire n5012; + wire n5013; + wire n5014; + wire n5015; + wire n5016; + wire n5016_1; + wire n502; + wire n5020; + wire n5021; + wire n5021_1; + wire n5022; + wire n5023; + wire n5024; + wire n5025; + wire n5026; + wire n5026_1; + wire n5027; + wire n5028; + wire n5029; + wire n5030; + wire n5031; + wire n5031_1; + wire n5032; + wire n5033; + wire n5034; + wire n5035; + wire n5036; + wire n5039; + wire n5040; + wire n5041; + wire n5041_1; + wire n5045; + wire n5046; + wire n5046_1; + wire n5047; + wire n5051; + wire n5051_1; + wire n5052; + wire n5053; + wire n5056; + wire n5057; + wire n5058; + wire n5061; + wire n5062; + wire n5063; + wire n5064; + wire n5065; + wire n5066; + wire n5066_1; + wire n5067; + wire n5068; + wire n5069; + wire n507; + wire n5070; + wire n5071; + wire n5071_1; + wire n5072; + wire n5073; + wire n5074; + wire n5075; + wire n5076; + wire n5076_1; + wire n5077; + wire n5078; + wire n5079; + wire n5080; + wire n5081; + wire n5081_1; + wire n5082; + wire n5083; + wire n5084; + wire n5085; + wire n5086; + wire n5086_1; + wire n5087; + wire n5088; + wire n5089; + wire n5090; + wire n5091; + wire n5091_1; + wire n5092; + wire n5093; + wire n5094; + wire n5095; + wire n5096; + wire n5096_1; + wire n5097; + wire n5098; + wire n5099; + wire n5100; + wire n5101; + wire n5101_1; + wire n5102; + wire n5103; + wire n5104; + wire n5105; + wire n5106; + wire n5106_1; + wire n5107; + wire n5108; + wire n5109; + wire n5110; + wire n5111; + wire n5111_1; + wire n5112; + wire n5113; + wire n5114; + wire n5115; + wire n5116; + wire n5116_1; + wire n5117; + wire n512; + wire n5121; + wire n5121_1; + wire n5122; + wire n5123; + wire n5124; + wire n5125; + wire n5126; + wire n5126_1; + wire n5127; + wire n5128; + wire n5129; + wire n5130; + wire n5131; + wire n5131_1; + wire n5132; + wire n5133; + wire n5134; + wire n5135; + wire n5136; + wire n5136_1; + wire n5137; + wire n5138; + wire n5139; + wire n5140; + wire n5141; + wire n5141_1; + wire n5142; + wire n5145_1; + wire n5146; + wire n5150; + wire n5150_1; + wire n5151; + wire n5154; + wire n5155; + wire n5156; + wire n5159; + wire n516; + wire n5160; + wire n5161; + wire n5164; + wire n5168; + wire n5169; + wire n5169_1; + wire n5170; + wire n5174; + wire n5177; + wire n5178; + wire n5179; + wire n5179_1; + wire n5180; + wire n5181; + wire n5182; + wire n5183; + wire n5184; + wire n5187; + wire n5188; + wire n5189; + wire n5189_1; + wire n5193; + wire n5194; + wire n5194_1; + wire n5198; + wire n5199; + wire n5199_1; + wire n5203; + wire n5204; + wire n5204_1; + wire n5208; + wire n5209; + wire n5209_1; + wire n521; + wire n5213; + wire n5214; + wire n5214_1; + wire n5215; + wire n5219; + wire n5219_1; + wire n5220; + wire n5224; + wire n5224_1; + wire n5225; + wire n5229; + wire n5229_1; + wire n5230; + wire n5234; + wire n5234_1; + wire n5235; + wire n5239; + wire n5239_1; + wire n5240; + wire n5241; + wire n5244; + wire n5245; + wire n5246; + wire n5249; + wire n525; + wire n5250; + wire n5251; + wire n5254; + wire n5255; + wire n5256; + wire n5259; + wire n5260; + wire n5261; + wire n5264; + wire n5265; + wire n5266; + wire n5267; + wire n5269; + wire n5271; + wire n5272; + wire n5274; + wire n5276; + wire n5277; + wire n5279; + wire n5281; + wire n5282; + wire n5284; + wire n5286; + wire n5287; + wire n5289; + wire n529; + wire n5294; + wire n5299; + wire n5302; + wire n5304; + wire n5306; + wire n5307; + wire n5309; + wire n5311; + wire n5312; + wire n5314; + wire n5316; + wire n5319; + wire n5320; + wire n5321; + wire n5322; + wire n5323; + wire n5324; + wire n5324_1; + wire n5325; + wire n5329; + wire n5329_1; + wire n533; + wire n5333; + wire n5334; + wire n5334_1; + wire n5335; + wire n5336; + wire n5337; + wire n5338; + wire n5339; + wire n5342; + wire n5343; + wire n5344; + wire n5347; + wire n5348; + wire n5349; + wire n5349_1; + wire n5350; + wire n5351; + wire n5352; + wire n5354; + wire n5356; + wire n5357; + wire n5358; + wire n5359; + wire n5362; + wire n5363; + wire n5364; + wire n5364_1; + wire n5365; + wire n5366; + wire n5367; + wire n5369; + wire n537; + wire n5371; + wire n5372; + wire n5373; + wire n5374; + wire n5377; + wire n5378; + wire n5379; + wire n5382; + wire n5383; + wire n5384; + wire n5387; + wire n5388; + wire n5389; + wire n5392; + wire n5393; + wire n5394; + wire n5399; + wire n5402; + wire n5403; + wire n5404; + wire n5404_1; + wire n5405; + wire n5406; + wire n5407; + wire n5408; + wire n5409; + wire n5409_1; + wire n541; + wire n5410; + wire n5411; + wire n5412; + wire n5413; + wire n5414; + wire n5414_1; + wire n5415; + wire n5416; + wire n5417; + wire n5418; + wire n5419; + wire n5419_1; + wire n5420; + wire n5421; + wire n5422; + wire n5423; + wire n5424; + wire n5424_1; + wire n5425; + wire n5426; + wire n5427; + wire n5428; + wire n5429; + wire n5429_1; + wire n5433; + wire n5434; + wire n5439; + wire n5439_1; + wire n5440; + wire n5441; + wire n5442; + wire n5443; + wire n5444; + wire n5444_1; + wire n5445; + wire n5446; + wire n5447; + wire n5448; + wire n5449; + wire n5449_1; + wire n545; + wire n5450; + wire n5451; + wire n5452; + wire n5453; + wire n5454; + wire n5454_1; + wire n5455; + wire n5456; + wire n5457; + wire n5458; + wire n5459; + wire n5459_1; + wire n5460; + wire n5461; + wire n5462; + wire n5463; + wire n5464; + wire n5467; + wire n5468; + wire n5469; + wire n5474; + wire n5474_1; + wire n5475; + wire n5476; + wire n5477; + wire n5478; + wire n5479; + wire n5479_1; + wire n5480; + wire n5481; + wire n5482; + wire n5483; + wire n5484; + wire n5484_1; + wire n5485; + wire n5486; + wire n5487; + wire n5488; + wire n5489; + wire n5489_1; + wire n549; + wire n5490; + wire n5491; + wire n5492; + wire n5493; + wire n5494; + wire n5494_1; + wire n5495; + wire n5496; + wire n5497; + wire n5498; + wire n5499; + wire n5499_1; + wire n5500; + wire n5501; + wire n5504; + wire n5505; + wire n5506; + wire n5507; + wire n5509; + wire n5513; + wire n5514; + wire n5514_1; + wire n5515; + wire n5516; + wire n5517; + wire n5518; + wire n5519; + wire n5519_1; + wire n5520; + wire n5521; + wire n5522; + wire n5523; + wire n5524; + wire n5524_1; + wire n5525; + wire n5526; + wire n5527; + wire n5528; + wire n5529; + wire n5529_1; + wire n553; + wire n5530; + wire n5531; + wire n5532; + wire n5533; + wire n5534; + wire n5534_1; + wire n5535; + wire n5536; + wire n5537; + wire n5538; + wire n5539; + wire n5539_1; + wire n5540; + wire n5544; + wire n5544_1; + wire n5545; + wire n5546; + wire n5549; + wire n5550; + wire n5552; + wire n5554; + wire n5554_1; + wire n5556; + wire n5559; + wire n5563; + wire n5564; + wire n5567; + wire n5568; + wire n5569; + wire n5569_1; + wire n557; + wire n5570; + wire n5571; + wire n5572; + wire n5573; + wire n5574; + wire n5575; + wire n5577; + wire n5579; + wire n5579_1; + wire n5580; + wire n5584; + wire n5584_1; + wire n5588; + wire n5589; + wire n5592; + wire n5594; + wire n5594_1; + wire n5596; + wire n5598; + wire n5599; + wire n5604; + wire n5605; + wire n5609; + wire n5609_1; + wire n561; + wire n5610; + wire n5611; + wire n5612; + wire n5613; + wire n5614; + wire n5614_1; + wire n5616; + wire n5618; + wire n5619; + wire n5620; + wire n5621; + wire n5624; + wire n5625; + wire n5629; + wire n5629_1; + wire n5633; + wire n5634; + wire n5635; + wire n5637; + wire n5639; + wire n5639_1; + wire n5644; + wire n5646; + wire n5649; + wire n565; + wire n5650; + wire n5651; + wire n5652; + wire n5653; + wire n5654; + wire n5654_1; + wire n5655; + wire n5657; + wire n5659; + wire n5659_1; + wire n5661; + wire n5662; + wire n5664; + wire n5666; + wire n5669; + wire n5670; + wire n5674; + wire n5674_1; + wire n5676; + wire n5678; + wire n5679; + wire n5680; + wire n5684; + wire n5687; + wire n5689; + wire n569; + wire n5691; + wire n5692; + wire n5693; + wire n5694; + wire n5694_1; + wire n5695; + wire n5696; + wire n5698; + wire n5699; + wire n5700; + wire n5702; + wire n5703; + wire n5704; + wire n5707; + wire n5709; + wire n5711; + wire n5714; + wire n5715; + wire n5716; + wire n5717; + wire n5718; + wire n5719; + wire n5719_1; + wire n5720; + wire n5724; + wire n5724_1; + wire n5728; + wire n5729; + wire n5729_1; + wire n573; + wire n5730; + wire n5731; + wire n5732; + wire n5733; + wire n5734; + wire n5737; + wire n5739; + wire n5741; + wire n5742; + wire n5743; + wire n5744; + wire n5744_1; + wire n5745; + wire n5746; + wire n5749; + wire n5750; + wire n5754; + wire n5754_1; + wire n5755; + wire n5756; + wire n5757; + wire n5758; + wire n5759; + wire n5759_1; + wire n5763; + wire n5764; + wire n5767; + wire n5769; + wire n577; + wire n5771; + wire n5774; + wire n5775; + wire n5779; + wire n5782; + wire n5784; + wire n5786; + wire n5789; + wire n5790; + wire n5794; + wire n5794_1; + wire n5799; + wire n5802; + wire n5803; + wire n5804; + wire n5804_1; + wire n5808; + wire n5809; + wire n581; + wire n5810; + wire n5812; + wire n5814; + wire n5814_1; + wire n5819; + wire n5824; + wire n5825; + wire n5826; + wire n5827; + wire n5829; + wire n5834; + wire n5839; + wire n5843; + wire n5844; + wire n5844_1; + wire n5845; + wire n5846; + wire n5847; + wire n5848; + wire n5849; + wire n5849_1; + wire n585; + wire n5854; + wire n5859; + wire n5864; + wire n5865; + wire n5866; + wire n5867; + wire n5868; + wire n5869; + wire n5869_1; + wire n5870; + wire n5871; + wire n5874; + wire n5879; + wire n5884; + wire n5888; + wire n5889; + wire n589; + wire n5892; + wire n5893_1; + wire n5896; + wire n5898; + wire n5901; + wire n5902; + wire n5906; + wire n5908; + wire n5911; + wire n5912; + wire n5916; + wire n5918; + wire n5921; + wire n5922; + wire n5926; + wire n593; + wire n5931; + wire n5936; + wire n5941; + wire n5946; + wire n5951; + wire n5956; + wire n5961; + wire n5966; + wire n5971; + wire n5976; + wire n598; + wire n5981; + wire n5986; + wire n5991; + wire n5996; + wire n6001; + wire n6006; + wire n6011; + wire n6016; + wire n6021; + wire n6026; + wire n603; + wire n6031; + wire n6036; + wire n6041; + wire n6046; + wire n6051; + wire n6056; + wire n6061; + wire n6066; + wire n6071_1; + wire n6076; + wire n608; + wire n6081; + wire n6086; + wire n6091; + wire n6096; + wire n6101; + wire n6106; + wire n6107; + wire n6108; + wire n6110; + wire n6111; + wire n6111_1; + wire n6116; + wire n6116_1; + wire n6121; + wire n6126; + wire n613; + wire n6130; + wire n6135; + wire n6139; + wire n6144; + wire n6148; + wire n6153; + wire n6153_1; + wire n6157; + wire n6162; + wire n6166; + wire n6171; + wire n6175; + wire n618; + wire n6180; + wire n6184; + wire n6189; + wire n6190; + wire n6193; + wire n6197; + wire n6201; + wire n6206; + wire n6211; + wire n6216; + wire n6220; + wire n6224; + wire n6227; + wire n6228; + wire n623; + wire n6232; + wire n6236; + wire n6240; + wire n6244_1; + wire n6248; + wire n6252; + wire n6256; + wire n6260; + wire n6264; + wire n6268; + wire n6272; + wire n6276; + wire n628; + wire n6280; + wire n6284; + wire n6288; + wire n6292; + wire n6296; + wire n6300; + wire n6304; + wire n6308; + wire n6312; + wire n6317; + wire n6322; + wire n6327; + wire n633; + wire n6332; + wire n6336_1; + wire n6340; + wire n6345_1; + wire n6349_1; + wire n6354; + wire n6358_1; + wire n6363_1; + wire n6367; + wire n6369; + wire n6370; + wire n6371; + wire n6372; + wire n6376; + wire n638; + wire n6380; + wire n6381; + wire n6385; + wire n6390; + wire n6394; + wire n6397; + wire n6399; + wire n6401; + wire n6404; + wire n6404_1; + wire n6406; + wire n6408; + wire n6409; + wire n6410; + wire n6412; + wire n6414; + wire n6418; + wire n6418_1; + wire n6419; + wire n642; + wire n6422_1; + wire n6424; + wire n6426; + wire n6426_1; + wire n6428; + wire n6430; + wire n6431_1; + wire n6432; + wire n6435; + wire n6436; + wire n6438; + wire n6441; + wire n6446; + wire n6451; + wire n6456; + wire n646; + wire n6460; + wire n6460_1; + wire n6462; + wire n6464; + wire n6464_1; + wire n6468; + wire n6470; + wire n6472; + wire n6472_1; + wire n6474; + wire n6476; + wire n6476_1; + wire n6478; + wire n6480; + wire n6481; + wire n6482; + wire n6484; + wire n6485_1; + wire n6486; + wire n6487; + wire n6490; + wire n6490_1; + wire n6491; + wire n6495; + wire n6495_1; + wire n6496; + wire n6499; + wire n650; + wire n6500; + wire n6501; + wire n6504; + wire n6508; + wire n6513; + wire n6518; + wire n6518_1; + wire n6519; + wire n6522; + wire n6523; + wire n6523_1; + wire n6528; + wire n6530; + wire n6531; + wire n6533; + wire n6538; + wire n654; + wire n6540; + wire n6542; + wire n6543; + wire n6544; + wire n6546; + wire n6547; + wire n6548; + wire n6548_1; + wire n6550; + wire n6551; + wire n6552; + wire n6553; + wire n6553_1; + wire n6554; + wire n6556; + wire n6557; + wire n6558; + wire n6558_1; + wire n6559; + wire n6560; + wire n6561; + wire n6562; + wire n6563; + wire n6563_1; + wire n6565; + wire n6566; + wire n6568; + wire n6568_1; + wire n6569; + wire n6573; + wire n6578; + wire n658; + wire n6583; + wire n6588; + wire n6593; + wire n6598; + wire n6603; + wire n6608; + wire n6613; + wire n6618; + wire n662; + wire n6623; + wire n6628; + wire n6633; + wire n6638; + wire n6643; + wire n6646; + wire n6647_1; + wire n6648; + wire n6649; + wire n6650; + wire n6651; + wire n6652_1; + wire n6653; + wire n6654; + wire n6656; + wire n6656_1; + wire n6657; + wire n6659; + wire n666; + wire n6660; + wire n6661; + wire n6662; + wire n6664; + wire n6666; + wire n6666_1; + wire n6668; + wire n6669; + wire n6671; + wire n6671_1; + wire n6672; + wire n6673; + wire n6674; + wire n6675; + wire n6676; + wire n6676_1; + wire n6677; + wire n6678; + wire n6679; + wire n6680; + wire n6681; + wire n6681_1; + wire n6682; + wire n6683; + wire n6684; + wire n6685; + wire n6686; + wire n6686_1; + wire n6687; + wire n6688; + wire n6689; + wire n6690; + wire n6691; + wire n6691_1; + wire n6692; + wire n6693; + wire n6694; + wire n6695; + wire n6696; + wire n6696_1; + wire n6697; + wire n6698; + wire n6699; + wire n670; + wire n6701; + wire n6701_1; + wire n6702; + wire n6704; + wire n6705; + wire n6706; + wire n6706_1; + wire n6708; + wire n6709; + wire n6710; + wire n6711; + wire n6711_1; + wire n6713; + wire n6715; + wire n6716; + wire n6716_1; + wire n6721; + wire n6726; + wire n6731; + wire n6736; + wire n6741; + wire n6746; + wire n674_1; + wire n6751; + wire n6756; + wire n6761; + wire n6766; + wire n6771; + wire n6776; + wire n678; + wire n6781; + wire n6786; + wire n6791; + wire n6796; + wire n6801; + wire n6806; + wire n6811; + wire n6816; + wire n682; + wire n6821; + wire n6826; + wire n6831; + wire n6836; + wire n6841; + wire n6846; + wire n6851; + wire n6856; + wire n686; + wire n6861; + wire n6866; + wire n6871; + wire n6876; + wire n6881; + wire n6886; + wire n6891; + wire n6896; + wire n690; + wire n6901; + wire n6906; + wire n6911; + wire n6916; + wire n6921; + wire n6926_1; + wire n6931_1; + wire n6936_1; + wire n6941_1; + wire n6946_1; + wire n694_1; + wire n6951_1; + wire n6956_1; + wire n6961_1; + wire n6966_1; + wire n6971_1; + wire n6976_1; + wire n698; + wire n6981_1; + wire n6986_1; + wire n6991_1; + wire n6995; + wire n7000; + wire n7005; + wire n7010; + wire n7015; + wire n702; + wire n7020; + wire n7025; + wire n7030; + wire n7035; + wire n7040; + wire n7045; + wire n7050; + wire n7055; + wire n706; + wire n7060; + wire n7065; + wire n7070; + wire n7075; + wire n7080; + wire n7085; + wire n7090; + wire n7095; + wire n710; + wire n7100; + wire n7105; + wire n7110; + wire n7115; + wire n7120; + wire n7125; + wire n7130; + wire n7135; + wire n7140; + wire n7145; + wire n715; + wire n7150; + wire n7155; + wire n7160; + wire n7165; + wire n7170; + wire n7175; + wire n7180_1; + wire n7185; + wire n7190; + wire n7195; + wire n720; + wire n7200_1; + wire n7205; + wire n7210; + wire n7215; + wire n7220; + wire n7225; + wire n7229; + wire n7233; + wire n7238_1; + wire n7243; + wire n7248; + wire n725; + wire n7253; + wire n730; + wire n735; + wire n740; + wire n745; + wire n750; + wire n755; + wire n760; + wire n765; + wire n770; + wire n775; + wire n780; + wire n785; + wire n790; + wire n795; + wire n800; + wire n805; + wire n810; + wire n815; + wire n820; + wire n825; + wire n830; + wire n835; + wire n840; + wire n845; + wire n850; + wire n855; + wire n860; + wire n865; + wire n870; + wire n875; + wire n880; + wire n885; + wire n890; + wire n895; + wire n900; + wire n905; + wire n910; + wire n915; + wire n920; + wire n925; + wire n930; + wire n935; + wire n939; + wire n944; + wire n948; + wire n953; + wire n958_1; + wire n962; + wire n966; + wire n970; + wire n974; + wire n978; + wire n983; + wire n988; + wire n993; + wire n998_1; + always @(posedge clock) + Pg16437 <= n271; + always @(posedge clock) + Pg8270 <= n307; + always @(posedge clock) + Ng113 <= n690; + always @(posedge clock) + Ng1939 <= n5006; + always @(posedge clock) + Ng1956 <= n5011; + always @(posedge clock) + Ng1957 <= n5016; + always @(posedge clock) + Ng1955 <= n5021; + always @(posedge clock) + Ng1959 <= n5026; + always @(posedge clock) + Ng1960 <= n5031; + always @(posedge clock) + Ng1958 <= n5036; + always @(posedge clock) + Ng1962 <= n5041; + always @(posedge clock) + Ng1963 <= n5046; + always @(posedge clock) + Ng1961 <= n5051; + always @(posedge clock) + Ng109 <= n694_1; + always @(posedge clock) + Ng1965 <= n5056; + always @(posedge clock) + Ng1966 <= n5061; + always @(posedge clock) + Ng1964 <= n5066; + always @(posedge clock) + Ng1967 <= n5071; + always @(posedge clock) + Ng1970 <= n5076; + always @(posedge clock) + Ng1973 <= n5081; + always @(posedge clock) + Ng1976 <= n5086; + always @(posedge clock) + Ng1979 <= n5091; + always @(posedge clock) + Ng1982 <= n5096; + always @(posedge clock) + Ng1994 <= n5101; + always @(posedge clock) + Ng105 <= n698; + always @(posedge clock) + Ng1997 <= n5106; + always @(posedge clock) + Ng2000 <= n5111; + always @(posedge clock) + Ng1985 <= n5116; + always @(posedge clock) + Ng1988 <= n5121; + always @(posedge clock) + Ng1991 <= n5126; + always @(posedge clock) + Ng1871 <= n5131; + always @(posedge clock) + Ng1874 <= n5136; + always @(posedge clock) + Ng1877 <= n5141; + always @(posedge clock) + Ng1886 <= n5145_1; + always @(posedge clock) + Ng1887 <= n5150_1; + always @(posedge clock) + Ng101 <= n702; + always @(posedge clock) + Ng1905 <= n5154; + always @(posedge clock) + Ng1909 <= n5159; + always @(posedge clock) + Ng1910 <= n5164; + always @(posedge clock) + Ng1911 <= n5169; + always @(posedge clock) + Ng1912 <= n5174; + always @(posedge clock) + Ng1913 <= n5179; + always @(posedge clock) + Ng1914 <= n5184; + always @(posedge clock) + Ng1916 <= n5189; + always @(posedge clock) + Ng1917 <= n5194; + always @(posedge clock) + Ng1918 <= n5199; + always @(posedge clock) + Ng97 <= n706; + always @(posedge clock) + Ng1921 <= n5204; + always @(posedge clock) + Ng2010 <= n5209; + always @(posedge clock) + Ng2039 <= n5214; + always @(posedge clock) + Ng2020 <= n5219; + always @(posedge clock) + Ng2013 <= n5224; + always @(posedge clock) + Ng2033 <= n5229; + always @(posedge clock) + Ng2026 <= n5234; + always @(posedge clock) + Ng2040 <= n5239; + always @(posedge clock) + Ng2052 <= n5244; + always @(posedge clock) + Ng2046 <= n5249; + always @(posedge clock) + Ng13407 <= n710; + always @(posedge clock) + Ng2059 <= n5254; + always @(posedge clock) + Ng2066 <= n5259; + always @(posedge clock) + Ng2072 <= n5264; + always @(posedge clock) + Ng2079 <= n5269; + always @(posedge clock) + Ng2080 <= n5274; + always @(posedge clock) + Ng2078 <= n5279; + always @(posedge clock) + Ng2082 <= n5284; + always @(posedge clock) + Ng2083 <= n5289; + always @(posedge clock) + Ng2081 <= n5294; + always @(posedge clock) + Ng2085 <= n5299; + always @(posedge clock) + Ng2200 <= n715; + always @(posedge clock) + Ng2086 <= n5304; + always @(posedge clock) + Ng2084 <= n5309; + always @(posedge clock) + Ng2088 <= n5314; + always @(posedge clock) + Ng2089 <= n5319; + always @(posedge clock) + Ng2087 <= n5324; + always @(posedge clock) + Ng2091 <= n5329; + always @(posedge clock) + Ng2092 <= n5334; + always @(posedge clock) + Ng2090 <= n5339; + always @(posedge clock) + Ng2094 <= n5344; + always @(posedge clock) + Ng2095 <= n5349; + always @(posedge clock) + Ng2195 <= n720; + always @(posedge clock) + Ng2093 <= n5354; + always @(posedge clock) + Ng2097 <= n5359; + always @(posedge clock) + Ng2098 <= n5364; + always @(posedge clock) + Ng2096 <= n5369; + always @(posedge clock) + Ng2100 <= n5374; + always @(posedge clock) + Ng2101 <= n5379; + always @(posedge clock) + Ng2099 <= n5384; + always @(posedge clock) + Ng2103 <= n5389; + always @(posedge clock) + Ng2104 <= n5394; + always @(posedge clock) + Ng2102 <= n5399; + always @(posedge clock) + Ng2190 <= n725; + always @(posedge clock) + Ng2106 <= n5404; + always @(posedge clock) + Ng2107 <= n5409; + always @(posedge clock) + Ng2105 <= n5414; + always @(posedge clock) + Ng2109 <= n5419; + always @(posedge clock) + Ng2110 <= n5424; + always @(posedge clock) + Ng2108 <= n5429; + always @(posedge clock) + Ng2112 <= n5434; + always @(posedge clock) + Ng2113 <= n5439; + always @(posedge clock) + Ng2111 <= n5444; + always @(posedge clock) + Ng2115 <= n5449; + always @(posedge clock) + Ng2185 <= n730; + always @(posedge clock) + Ng2116 <= n5454; + always @(posedge clock) + Ng2114 <= n5459; + always @(posedge clock) + Ng2118 <= n5464; + always @(posedge clock) + Ng2119 <= n5469; + always @(posedge clock) + Ng2117 <= n5474; + always @(posedge clock) + Ng2206 <= n5479; + always @(posedge clock) + Ng2207 <= n5484; + always @(posedge clock) + Ng2205 <= n5489; + always @(posedge clock) + Ng2209 <= n5494; + always @(posedge clock) + Ng2210 <= n5499; + always @(posedge clock) + Pg8269 <= n311; + always @(posedge clock) + Ng2180 <= n735; + always @(posedge clock) + Ng2208 <= n5504; + always @(posedge clock) + Ng2218 <= n5509; + always @(posedge clock) + Ng2219 <= n5514; + always @(posedge clock) + Ng2217 <= n5519; + always @(posedge clock) + Ng2221 <= n5524; + always @(posedge clock) + Ng2222 <= n5529; + always @(posedge clock) + Ng2220 <= n5534; + always @(posedge clock) + Ng2224 <= n5539; + always @(posedge clock) + Ng2225 <= n5544; + always @(posedge clock) + Ng2223 <= n5549; + always @(posedge clock) + Ng2175 <= n740; + always @(posedge clock) + Ng2227 <= n5554; + always @(posedge clock) + Ng2228 <= n5559; + always @(posedge clock) + Ng2226 <= n5564; + always @(posedge clock) + Ng2230 <= n5569; + always @(posedge clock) + Ng2231 <= n5574; + always @(posedge clock) + Ng2229 <= n5579; + always @(posedge clock) + Ng2233 <= n5584; + always @(posedge clock) + Ng2234 <= n5589; + always @(posedge clock) + Ng2232 <= n5594; + always @(posedge clock) + Ng2236 <= n5599; + always @(posedge clock) + Ng2170 <= n745; + always @(posedge clock) + Ng2237 <= n5604; + always @(posedge clock) + Ng2235 <= n5609; + always @(posedge clock) + Ng2239 <= n5614; + always @(posedge clock) + Ng2240 <= n5619; + always @(posedge clock) + Ng2238 <= n5624; + always @(posedge clock) + Ng2245 <= n5629; + always @(posedge clock) + Ng2246 <= n5634; + always @(posedge clock) + Ng2244 <= n5639; + always @(posedge clock) + Ng2248 <= n5644; + always @(posedge clock) + Ng2249 <= n5649; + always @(posedge clock) + Ng2165 <= n750; + always @(posedge clock) + Ng2247 <= n5654; + always @(posedge clock) + Ng2251 <= n5659; + always @(posedge clock) + Ng2252 <= n5664; + always @(posedge clock) + Ng2250 <= n5669; + always @(posedge clock) + Ng2254 <= n5674; + always @(posedge clock) + Ng2255 <= n5679; + always @(posedge clock) + Ng2253 <= n5684; + always @(posedge clock) + Ng2261 <= n5689; + always @(posedge clock) + Ng2264 <= n5694; + always @(posedge clock) + Ng2267 <= n5699; + always @(posedge clock) + Ng13455 <= n755; + always @(posedge clock) + Ng2306 <= n5704; + always @(posedge clock) + Ng2309 <= n5709; + always @(posedge clock) + Ng2312 <= n5714; + always @(posedge clock) + Ng2270 <= n5719; + always @(posedge clock) + Ng2273 <= n5724; + always @(posedge clock) + Ng2276 <= n5729; + always @(posedge clock) + Ng2315 <= n5734; + always @(posedge clock) + Ng2318 <= n5739; + always @(posedge clock) + Ng2321 <= n5744; + always @(posedge clock) + Ng2279 <= n5749; + always @(posedge clock) + Ng3210 <= n760; + always @(posedge clock) + Ng2282 <= n5754; + always @(posedge clock) + Ng2285 <= n5759; + always @(posedge clock) + Ng2324 <= n5764; + always @(posedge clock) + Ng2327 <= n5769; + always @(posedge clock) + Ng2330 <= n5774; + always @(posedge clock) + Ng2288 <= n5779; + always @(posedge clock) + Ng2291 <= n5784; + always @(posedge clock) + Ng2294 <= n5789; + always @(posedge clock) + Ng2333 <= n5794; + always @(posedge clock) + Ng2336 <= n5799; + always @(posedge clock) + Ng3211 <= n765; + always @(posedge clock) + Ng2339 <= n5804; + always @(posedge clock) + Ng2297 <= n5809; + always @(posedge clock) + Ng2300 <= n5814; + always @(posedge clock) + Ng2303 <= n5819; + always @(posedge clock) + Ng2342 <= n5824; + always @(posedge clock) + Ng2345 <= n5829; + always @(posedge clock) + Ng2348 <= n5834; + always @(posedge clock) + Ng2160 <= n5839; + always @(posedge clock) + Ng2156 <= n5844; + always @(posedge clock) + Ng2151 <= n5849; + always @(posedge clock) + Ng3084 <= n770; + always @(posedge clock) + Ng2147 <= n5854; + always @(posedge clock) + Ng2142 <= n5859; + always @(posedge clock) + Ng2138 <= n5864; + always @(posedge clock) + Ng2133 <= n5869; + always @(posedge clock) + Ng2129 <= n5874; + always @(posedge clock) + Ng2124 <= n5879; + always @(posedge clock) + Ng2120 <= n5884; + always @(posedge clock) + Ng2256 <= n5889; + always @(posedge clock) + Pg5549 <= n5893_1; + always @(posedge clock) + Ng2257 <= n5896; + always @(posedge clock) + Ng3085 <= n775; + always @(posedge clock) + Ng11578 <= n5901; + always @(posedge clock) + Ng11579 <= n5906; + always @(posedge clock) + Ng11580 <= n5911; + always @(posedge clock) + Ng11581 <= n5916; + always @(posedge clock) + Ng11582 <= n5921; + always @(posedge clock) + Ng11583 <= n5926; + always @(posedge clock) + Ng11584 <= n5931; + always @(posedge clock) + Ng11585 <= n5936; + always @(posedge clock) + Ng11586 <= n5941; + always @(posedge clock) + Ng11587 <= n5946; + always @(posedge clock) + Ng3086 <= n780; + always @(posedge clock) + Ng11588 <= n5951; + always @(posedge clock) + Ng11589 <= n5956; + always @(posedge clock) + Ng2483 <= n5961; + always @(posedge clock) + Ng2486 <= n5966; + always @(posedge clock) + Ng2489 <= n5971; + always @(posedge clock) + Ng2492 <= n5976; + always @(posedge clock) + Ng2495 <= n5981; + always @(posedge clock) + Ng2498 <= n5986; + always @(posedge clock) + Ng2502 <= n5991; + always @(posedge clock) + Ng2503 <= n5996; + always @(posedge clock) + Pg8268 <= n315; + always @(posedge clock) + Ng3087 <= n785; + always @(posedge clock) + Ng2501 <= n6001; + always @(posedge clock) + Ng2504 <= n6006; + always @(posedge clock) + Ng2507 <= n6011; + always @(posedge clock) + Ng2510 <= n6016; + always @(posedge clock) + Ng2513 <= n6021; + always @(posedge clock) + Ng2516 <= n6026; + always @(posedge clock) + Ng2519 <= n6031; + always @(posedge clock) + Ng2523 <= n6036; + always @(posedge clock) + Ng2524 <= n6041; + always @(posedge clock) + Ng2522 <= n6046; + always @(posedge clock) + Ng3091 <= n790; + always @(posedge clock) + Ng2387 <= n6051; + always @(posedge clock) + Ng2388 <= n6056; + always @(posedge clock) + Ng2389 <= n6061; + always @(posedge clock) + Ng2390 <= n6066; + always @(posedge clock) + Ng2391 <= n6071_1; + always @(posedge clock) + Ng2392 <= n6076; + always @(posedge clock) + Ng2393 <= n6081; + always @(posedge clock) + Ng2394 <= n6086; + always @(posedge clock) + Ng2395 <= n6091; + always @(posedge clock) + Ng2397 <= n6096; + always @(posedge clock) + Ng3092 <= n795; + always @(posedge clock) + Ng2398 <= n6101; + always @(posedge clock) + Ng2396 <= n6106; + always @(posedge clock) + Ng2478 <= n6111; + always @(posedge clock) + Ng2479 <= n6116_1; + always @(posedge clock) + Ng2477 <= n6121; + always @(posedge clock) + Ng2525 <= n6126; + always @(posedge clock) + Ng2526 <= n6130; + always @(posedge clock) + Ng2527 <= n6135; + always @(posedge clock) + Ng2528 <= n6139; + always @(posedge clock) + Ng2529 <= n6144; + always @(posedge clock) + Ng3093 <= n800; + always @(posedge clock) + Ng2354 <= n6148; + always @(posedge clock) + Ng2355 <= n6153; + always @(posedge clock) + Ng2356 <= n6157; + always @(posedge clock) + Ng2357 <= n6162; + always @(posedge clock) + Ng2358 <= n6166; + always @(posedge clock) + Ng2359 <= n6171; + always @(posedge clock) + Ng2360 <= n6175; + always @(posedge clock) + Ng2361 <= n6180; + always @(posedge clock) + Ng2362 <= n6184; + always @(posedge clock) + Ng2363 <= n6189; + always @(posedge clock) + Ng3094 <= n805; + always @(posedge clock) + Ng2364 <= n6193; + always @(posedge clock) + Ng2365 <= n6197; + always @(posedge clock) + Ng2366 <= n6201; + always @(posedge clock) + Ng2374 <= n6206; + always @(posedge clock) + Ng2380 <= n6211; + always @(posedge clock) + Ng2373 <= n6216; + always @(posedge clock) + Ng2417 <= n6220; + always @(posedge clock) + Ng2424 <= n6224; + always @(posedge clock) + Ng2425 <= n6228; + always @(posedge clock) + Ng2426 <= n6232; + always @(posedge clock) + Ng3095 <= n810; + always @(posedge clock) + Ng2427 <= n6236; + always @(posedge clock) + Ng2428 <= n6240; + always @(posedge clock) + Ng2432 <= n6244_1; + always @(posedge clock) + Ng2439 <= n6248; + always @(posedge clock) + Ng2440 <= n6252; + always @(posedge clock) + Ng2441 <= n6256; + always @(posedge clock) + Ng2442 <= n6260; + always @(posedge clock) + Ng2443 <= n6264; + always @(posedge clock) + Ng2447 <= n6268; + always @(posedge clock) + Ng2454 <= n6272; + always @(posedge clock) + Ng3096 <= n815; + always @(posedge clock) + Ng2455 <= n6276; + always @(posedge clock) + Ng2456 <= n6280; + always @(posedge clock) + Ng2457 <= n6284; + always @(posedge clock) + Ng2458 <= n6288; + always @(posedge clock) + Ng2462 <= n6292; + always @(posedge clock) + Ng2469 <= n6296; + always @(posedge clock) + Ng2470 <= n6300; + always @(posedge clock) + Ng2471 <= n6304; + always @(posedge clock) + Ng2472 <= n6308; + always @(posedge clock) + Ng2399 <= n6312; + always @(posedge clock) + Ng3097 <= n820; + always @(posedge clock) + Ng2628 <= n6317; + always @(posedge clock) + Ng2631 <= n6322; + always @(posedge clock) + Ng2584 <= n6327; + always @(posedge clock) + Ng2587 <= n6332; + always @(posedge clock) + Ng2597 <= n6336_1; + always @(posedge clock) + Ng2598 <= n6340; + always @(posedge clock) + Ng2638 <= n6345_1; + always @(posedge clock) + Ng2643 <= n6349_1; + always @(posedge clock) + Ng2644 <= n6354; + always @(posedge clock) + Ng2645 <= n6358_1; + always @(posedge clock) + Ng3098 <= n825; + always @(posedge clock) + Ng2646 <= n6363_1; + always @(posedge clock) + Ng2647 <= n6367; + always @(posedge clock) + Ng2648 <= n6372; + always @(posedge clock) + Ng2639 <= n6376; + always @(posedge clock) + Ng2640 <= n6381; + always @(posedge clock) + Ng2641 <= n6385; + always @(posedge clock) + Ng2642 <= n6390; + always @(posedge clock) + Ng2564 <= n6394; + always @(posedge clock) + Ng2561 <= n6399; + always @(posedge clock) + Ng2562 <= n6404; + always @(posedge clock) + Ng3099 <= n830; + always @(posedge clock) + Ng2563 <= n6409; + always @(posedge clock) + Ng11593 <= n6414; + always @(posedge clock) + Ng11596 <= n6418; + always @(posedge clock) + Ng11597 <= n6422_1; + always @(posedge clock) + Ng2552 <= n6426; + always @(posedge clock) + Ng2553 <= n6431_1; + always @(posedge clock) + Ng2554 <= n6436; + always @(posedge clock) + Ng2555 <= n6441; + always @(posedge clock) + Ng2559 <= n6446; + always @(posedge clock) + Ng2539 <= n6451; + always @(posedge clock) + Pg8267 <= n319; + always @(posedge clock) + Ng3100 <= n835; + always @(posedge clock) + Ng11598 <= n6456; + always @(posedge clock) + Ng11594 <= n6460_1; + always @(posedge clock) + Ng11595 <= n6464; + always @(posedge clock) + Ng2602 <= n6468; + always @(posedge clock) + Ng2609 <= n6472; + always @(posedge clock) + Ng2616 <= n6476; + always @(posedge clock) + Ng2617 <= n6481; + always @(posedge clock) + Ng2618 <= n6485_1; + always @(posedge clock) + Ng2622 <= n6490_1; + always @(posedge clock) + Ng2623 <= n6495_1; + always @(posedge clock) + Ng3101 <= n840; + always @(posedge clock) + Ng8311 <= n6499; + always @(posedge clock) + Ng2632 <= n6504; + always @(posedge clock) + Ng2633 <= n6508; + always @(posedge clock) + Ng2650 <= n6513; + always @(posedge clock) + Ng2651 <= n6518; + always @(posedge clock) + Ng2649 <= n6523; + always @(posedge clock) + Ng2653 <= n6528; + always @(posedge clock) + Ng2654 <= n6533; + always @(posedge clock) + Ng2652 <= n6538; + always @(posedge clock) + Ng2656 <= n6543; + always @(posedge clock) + Ng3102 <= n845; + always @(posedge clock) + Ng2657 <= n6548; + always @(posedge clock) + Ng2655 <= n6553; + always @(posedge clock) + Ng2659 <= n6558; + always @(posedge clock) + Ng2660 <= n6563; + always @(posedge clock) + Ng2658 <= n6568; + always @(posedge clock) + Ng2661 <= n6573; + always @(posedge clock) + Ng2664 <= n6578; + always @(posedge clock) + Ng2667 <= n6583; + always @(posedge clock) + Ng2670 <= n6588; + always @(posedge clock) + Ng2673 <= n6593; + always @(posedge clock) + Ng3103 <= n850; + always @(posedge clock) + Ng2676 <= n6598; + always @(posedge clock) + Ng2688 <= n6603; + always @(posedge clock) + Ng2691 <= n6608; + always @(posedge clock) + Ng2694 <= n6613; + always @(posedge clock) + Ng2679 <= n6618; + always @(posedge clock) + Ng2682 <= n6623; + always @(posedge clock) + Ng2685 <= n6628; + always @(posedge clock) + Ng2565 <= n6633; + always @(posedge clock) + Ng2568 <= n6638; + always @(posedge clock) + Ng2571 <= n6643; + always @(posedge clock) + Ng3104 <= n855; + always @(posedge clock) + Ng2580 <= n6647_1; + always @(posedge clock) + Ng2581 <= n6652_1; + always @(posedge clock) + Ng2599 <= n6656; + always @(posedge clock) + Ng2603 <= n6661; + always @(posedge clock) + Ng2604 <= n6666; + always @(posedge clock) + Ng2605 <= n6671; + always @(posedge clock) + Ng2606 <= n6676; + always @(posedge clock) + Ng2607 <= n6681; + always @(posedge clock) + Ng2608 <= n6686; + always @(posedge clock) + Ng2610 <= n6691; + always @(posedge clock) + Ng3105 <= n860; + always @(posedge clock) + Ng2611 <= n6696; + always @(posedge clock) + Ng2612 <= n6701; + always @(posedge clock) + Ng2615 <= n6706; + always @(posedge clock) + Ng2704 <= n6711; + always @(posedge clock) + Ng2733 <= n6716; + always @(posedge clock) + Ng2714 <= n6721; + always @(posedge clock) + Ng2707 <= n6726; + always @(posedge clock) + Ng2727 <= n6731; + always @(posedge clock) + Ng2720 <= n6736; + always @(posedge clock) + Ng2734 <= n6741; + always @(posedge clock) + Ng3106 <= n865; + always @(posedge clock) + Ng2746 <= n6746; + always @(posedge clock) + Ng2740 <= n6751; + always @(posedge clock) + Ng2753 <= n6756; + always @(posedge clock) + Ng2760 <= n6761; + always @(posedge clock) + Ng2766 <= n6766; + always @(posedge clock) + Ng2773 <= n6771; + always @(posedge clock) + Ng2774 <= n6776; + always @(posedge clock) + Ng2772 <= n6781; + always @(posedge clock) + Ng2776 <= n6786; + always @(posedge clock) + Ng2777 <= n6791; + always @(posedge clock) + Ng3107 <= n870; + always @(posedge clock) + Ng2775 <= n6796; + always @(posedge clock) + Ng2779 <= n6801; + always @(posedge clock) + Ng2780 <= n6806; + always @(posedge clock) + Ng2778 <= n6811; + always @(posedge clock) + Ng2782 <= n6816; + always @(posedge clock) + Ng2783 <= n6821; + always @(posedge clock) + Ng2781 <= n6826; + always @(posedge clock) + Ng2785 <= n6831; + always @(posedge clock) + Ng2786 <= n6836; + always @(posedge clock) + Ng2784 <= n6841; + always @(posedge clock) + Ng3108 <= n875; + always @(posedge clock) + Ng2788 <= n6846; + always @(posedge clock) + Ng2789 <= n6851; + always @(posedge clock) + Ng2787 <= n6856; + always @(posedge clock) + Ng2791 <= n6861; + always @(posedge clock) + Ng2792 <= n6866; + always @(posedge clock) + Ng2790 <= n6871; + always @(posedge clock) + Ng2794 <= n6876; + always @(posedge clock) + Ng2795 <= n6881; + always @(posedge clock) + Ng2793 <= n6886; + always @(posedge clock) + Ng2797 <= n6891; + always @(posedge clock) + Ng3155 <= n880; + always @(posedge clock) + Ng2798 <= n6896; + always @(posedge clock) + Ng2796 <= n6901; + always @(posedge clock) + Ng2800 <= n6906; + always @(posedge clock) + Ng2801 <= n6911; + always @(posedge clock) + Ng2799 <= n6916; + always @(posedge clock) + Ng2803 <= n6921; + always @(posedge clock) + Ng2804 <= n6926_1; + always @(posedge clock) + Ng2802 <= n6931_1; + always @(posedge clock) + Ng2806 <= n6936_1; + always @(posedge clock) + Ng2807 <= n6941_1; + always @(posedge clock) + Pg8266 <= n323; + always @(posedge clock) + Ng3158 <= n885; + always @(posedge clock) + Ng2805 <= n6946_1; + always @(posedge clock) + Ng2809 <= n6951_1; + always @(posedge clock) + Ng2810 <= n6956_1; + always @(posedge clock) + Ng2808 <= n6961_1; + always @(posedge clock) + Ng2812 <= n6966_1; + always @(posedge clock) + Ng2813 <= n6971_1; + always @(posedge clock) + Ng2811 <= n6976_1; + always @(posedge clock) + Ng3054 <= n6981_1; + always @(posedge clock) + Ng3079 <= n6986_1; + always @(posedge clock) + Ng13475 <= n6991_1; + always @(posedge clock) + Ng3161 <= n890; + always @(posedge clock) + Ng3043 <= n6995; + always @(posedge clock) + Ng3044 <= n7000; + always @(posedge clock) + Ng3045 <= n7005; + always @(posedge clock) + Ng3046 <= n7010; + always @(posedge clock) + Ng3047 <= n7015; + always @(posedge clock) + Ng3048 <= n7020; + always @(posedge clock) + Ng3049 <= n7025; + always @(posedge clock) + Ng3050 <= n7030; + always @(posedge clock) + Ng3051 <= n7035; + always @(posedge clock) + Ng3052 <= n7040; + always @(posedge clock) + Ng3164 <= n895; + always @(posedge clock) + Ng3053 <= n7045; + always @(posedge clock) + Ng3055 <= n7050; + always @(posedge clock) + Ng3056 <= n7055; + always @(posedge clock) + Ng3057 <= n7060; + always @(posedge clock) + Ng3058 <= n7065; + always @(posedge clock) + Ng3059 <= n7070; + always @(posedge clock) + Ng3060 <= n7075; + always @(posedge clock) + Ng3061 <= n7080; + always @(posedge clock) + Ng3062 <= n7085; + always @(posedge clock) + Ng3063 <= n7090; + always @(posedge clock) + Ng3167 <= n900; + always @(posedge clock) + Ng3064 <= n7095; + always @(posedge clock) + Ng3065 <= n7100; + always @(posedge clock) + Ng3066 <= n7105; + always @(posedge clock) + Ng3067 <= n7110; + always @(posedge clock) + Ng3068 <= n7115; + always @(posedge clock) + Ng3069 <= n7120; + always @(posedge clock) + Ng3070 <= n7125; + always @(posedge clock) + Ng3071 <= n7130; + always @(posedge clock) + Ng3072 <= n7135; + always @(posedge clock) + Ng3073 <= n7140; + always @(posedge clock) + Ng3170 <= n905; + always @(posedge clock) + Ng3074 <= n7145; + always @(posedge clock) + Ng3075 <= n7150; + always @(posedge clock) + Ng3076 <= n7155; + always @(posedge clock) + Ng3077 <= n7160; + always @(posedge clock) + Ng3078 <= n7165; + always @(posedge clock) + Ng2997 <= n7170; + always @(posedge clock) + Ng2993 <= n7175; + always @(posedge clock) + Ng2998 <= n7180_1; + always @(posedge clock) + Ng3006 <= n7185; + always @(posedge clock) + Ng3002 <= n7190; + always @(posedge clock) + Ng3173 <= n910; + always @(posedge clock) + Ng3013 <= n7195; + always @(posedge clock) + Ng3010 <= n7200_1; + always @(posedge clock) + Ng3024 <= n7205; + always @(posedge clock) + Ng3018 <= n7210; + always @(posedge clock) + Ng3028 <= n7215; + always @(posedge clock) + Ng3036 <= n7220; + always @(posedge clock) + Ng3032 <= n7225; + always @(posedge clock) + Ng2986 <= n7229; + always @(posedge clock) + Ng2987 <= n7233; + always @(posedge clock) + Ng3083 <= n7238_1; + always @(posedge clock) + Ng3176 <= n915; + always @(posedge clock) + Ng2992 <= n7243; + always @(posedge clock) + Ng2990 <= n7248; + always @(posedge clock) + Ng2991 <= n7253; + always @(posedge clock) + Ng3179 <= n920; + always @(posedge clock) + Ng3182 <= n925; + always @(posedge clock) + Ng3185 <= n930; + always @(posedge clock) + Pg8265 <= n327; + always @(posedge clock) + Ng3088 <= n935; + always @(posedge clock) + Ng3191 <= n939; + always @(posedge clock) + Ng3128 <= n944; + always @(posedge clock) + Ng3126 <= n948; + always @(posedge clock) + Ng3125 <= n953; + always @(posedge clock) + Ng3123 <= n958_1; + always @(posedge clock) + Ng3120 <= n962; + always @(posedge clock) + Ng3110 <= n966; + always @(posedge clock) + Ng3139 <= n970; + always @(posedge clock) + Ng3135 <= n974; + always @(posedge clock) + Pg8264 <= n331; + always @(posedge clock) + Ng3147 <= n978; + always @(posedge clock) + Ng185 <= n983; + always @(posedge clock) + Ng130 <= n988; + always @(posedge clock) + Ng131 <= n993; + always @(posedge clock) + Ng129 <= n998_1; + always @(posedge clock) + Ng133 <= n1003_1; + always @(posedge clock) + Ng134 <= n1008; + always @(posedge clock) + Ng132 <= n1013; + always @(posedge clock) + Ng142 <= n1018_1; + always @(posedge clock) + Ng143 <= n1023; + always @(posedge clock) + Pg8263 <= n335; + always @(posedge clock) + Ng141 <= n1028; + always @(posedge clock) + Ng145 <= n1033_1; + always @(posedge clock) + Ng146 <= n1038; + always @(posedge clock) + Ng144 <= n1043; + always @(posedge clock) + Ng148 <= n1048_1; + always @(posedge clock) + Ng149 <= n1053_1; + always @(posedge clock) + Ng147 <= n1058; + always @(posedge clock) + Ng151 <= n1063_1; + always @(posedge clock) + Ng152 <= n1068; + always @(posedge clock) + Ng150 <= n1073; + always @(posedge clock) + Pg8262 <= n339_1; + always @(posedge clock) + Ng154 <= n1078; + always @(posedge clock) + Ng155 <= n1083; + always @(posedge clock) + Ng153 <= n1088; + always @(posedge clock) + Ng157 <= n1093; + always @(posedge clock) + Ng158 <= n1098; + always @(posedge clock) + Ng156 <= n1103; + always @(posedge clock) + Ng160 <= n1108_1; + always @(posedge clock) + Ng161 <= n1113; + always @(posedge clock) + Ng159 <= n1118; + always @(posedge clock) + Ng163 <= n1123; + always @(posedge clock) + Pg8261 <= n343; + always @(posedge clock) + Ng164 <= n1128; + always @(posedge clock) + Ng162 <= n1133; + always @(posedge clock) + Ng169 <= n1138; + always @(posedge clock) + Ng170 <= n1143; + always @(posedge clock) + Ng168 <= n1148; + always @(posedge clock) + Ng172 <= n1153; + always @(posedge clock) + Ng173 <= n1158; + always @(posedge clock) + Ng171 <= n1163; + always @(posedge clock) + Ng175 <= n1168; + always @(posedge clock) + Ng176 <= n1173; + always @(posedge clock) + Pg16399 <= n275; + always @(posedge clock) + Pg8260 <= n347; + always @(posedge clock) + Ng174 <= n1178_1; + always @(posedge clock) + Ng178 <= n1183; + always @(posedge clock) + Ng179 <= n1188; + always @(posedge clock) + Ng177 <= n1193; + always @(posedge clock) + Ng186 <= n1198; + always @(posedge clock) + Ng189 <= n1203; + always @(posedge clock) + Ng192 <= n1208; + always @(posedge clock) + Ng231 <= n1213; + always @(posedge clock) + Ng234 <= n1218; + always @(posedge clock) + Ng237 <= n1223; + always @(posedge clock) + Pg8259 <= n351; + always @(posedge clock) + Ng195 <= n1228; + always @(posedge clock) + Ng198 <= n1233; + always @(posedge clock) + Ng201 <= n1238; + always @(posedge clock) + Ng240 <= n1243; + always @(posedge clock) + Ng243 <= n1248; + always @(posedge clock) + Ng246 <= n1253; + always @(posedge clock) + Ng204 <= n1258; + always @(posedge clock) + Ng207 <= n1263; + always @(posedge clock) + Ng210 <= n1268_1; + always @(posedge clock) + Ng249 <= n1273; + always @(posedge clock) + Pg8258 <= n355; + always @(posedge clock) + Ng252 <= n1278_1; + always @(posedge clock) + Ng255 <= n1283; + always @(posedge clock) + Ng213 <= n1288_1; + always @(posedge clock) + Ng216 <= n1293; + always @(posedge clock) + Ng219 <= n1298_1; + always @(posedge clock) + Ng258 <= n1303_1; + always @(posedge clock) + Ng261 <= n1308; + always @(posedge clock) + Ng264 <= n1313_1; + always @(posedge clock) + Ng222 <= n1318_1; + always @(posedge clock) + Ng225 <= n1323; + always @(posedge clock) + Pg8251 <= n359; + always @(posedge clock) + Ng228 <= n1328; + always @(posedge clock) + Ng267 <= n1333; + always @(posedge clock) + Ng270 <= n1338; + always @(posedge clock) + Ng273 <= n1343; + always @(posedge clock) + Ng92 <= n1348_1; + always @(posedge clock) + Ng88 <= n1353_1; + always @(posedge clock) + Ng83 <= n1358; + always @(posedge clock) + Ng79 <= n1363; + always @(posedge clock) + Ng74 <= n1368_1; + always @(posedge clock) + Ng70 <= n1373; + always @(posedge clock) + Pg8249 <= n363; + always @(posedge clock) + Ng65 <= n1378; + always @(posedge clock) + Ng61 <= n1383_1; + always @(posedge clock) + Ng56 <= n1388_1; + always @(posedge clock) + Ng52 <= n1393_1; + always @(posedge clock) + Ng11497 <= n1398; + always @(posedge clock) + Ng11498 <= n1403_1; + always @(posedge clock) + Ng11499 <= n1408; + always @(posedge clock) + Ng11500 <= n1413_1; + always @(posedge clock) + Ng11501 <= n1418; + always @(posedge clock) + Ng11502 <= n1423; + always @(posedge clock) + Pg8175 <= n367; + always @(posedge clock) + Ng11503 <= n1428; + always @(posedge clock) + Ng11504 <= n1433; + always @(posedge clock) + Ng11505 <= n1438; + always @(posedge clock) + Ng11506 <= n1443; + always @(posedge clock) + Ng11507 <= n1448; + always @(posedge clock) + Ng11508 <= n1453_1; + always @(posedge clock) + Ng408 <= n1458; + always @(posedge clock) + Ng411 <= n1463; + always @(posedge clock) + Ng414 <= n1468; + always @(posedge clock) + Ng417 <= n1473; + always @(posedge clock) + Pg8096 <= n371; + always @(posedge clock) + Ng420 <= n1478; + always @(posedge clock) + Ng423 <= n1483; + always @(posedge clock) + Ng427 <= n1488; + always @(posedge clock) + Ng428 <= n1493_1; + always @(posedge clock) + Ng426 <= n1498_1; + always @(posedge clock) + Ng429 <= n1503_1; + always @(posedge clock) + Ng432 <= n1508_1; + always @(posedge clock) + Ng435 <= n1513; + always @(posedge clock) + Ng438 <= n1518; + always @(posedge clock) + Ng441 <= n1523; + always @(posedge clock) + Pg8023 <= n375; + always @(posedge clock) + Ng444 <= n1528_1; + always @(posedge clock) + Ng448 <= n1533; + always @(posedge clock) + Ng449 <= n1538; + always @(posedge clock) + Ng447 <= n1543; + always @(posedge clock) + Ng312 <= n1548; + always @(posedge clock) + Ng313 <= n1553; + always @(posedge clock) + Ng314 <= n1558; + always @(posedge clock) + Ng315 <= n1563; + always @(posedge clock) + Ng316 <= n1568; + always @(posedge clock) + Ng317 <= n1573; + always @(posedge clock) + Pg8021 <= n378; + always @(posedge clock) + Ng318 <= n1578_1; + always @(posedge clock) + Ng319 <= n1583; + always @(posedge clock) + Ng320 <= n1588; + always @(posedge clock) + Ng322 <= n1593; + always @(posedge clock) + Ng323 <= n1598; + always @(posedge clock) + Ng321 <= n1603; + always @(posedge clock) + Ng403 <= n1608; + always @(posedge clock) + Ng404 <= n1613_1; + always @(posedge clock) + Ng402 <= n1618; + always @(posedge clock) + Ng450 <= n1623; + always @(posedge clock) + Pg7519 <= n382; + always @(posedge clock) + Ng451 <= n1627; + always @(posedge clock) + Ng452 <= n1632; + always @(posedge clock) + Ng453 <= n1636; + always @(posedge clock) + Ng454 <= n1641; + always @(posedge clock) + Ng279 <= n1645; + always @(posedge clock) + Ng280 <= n1650; + always @(posedge clock) + Ng281 <= n1654; + always @(posedge clock) + Ng282 <= n1659; + always @(posedge clock) + Ng283 <= n1663; + always @(posedge clock) + Ng284 <= n1668; + always @(posedge clock) + Pg16355 <= n279; + always @(posedge clock) + Pg7334 <= n386; + always @(posedge clock) + Ng285 <= n1672; + always @(posedge clock) + Ng286 <= n1677; + always @(posedge clock) + Ng287 <= n1681; + always @(posedge clock) + Ng288 <= n1686; + always @(posedge clock) + Ng289 <= n1690; + always @(posedge clock) + Ng290 <= n1694; + always @(posedge clock) + Ng291 <= n1698; + always @(posedge clock) + Ng299 <= n1703; + always @(posedge clock) + Ng305 <= n1708; + always @(posedge clock) + Ng298 <= n1713; + always @(posedge clock) + Pg6895 <= n390; + always @(posedge clock) + Ng342 <= n1717; + always @(posedge clock) + Ng349 <= n1721; + always @(posedge clock) + Ng350 <= n1725; + always @(posedge clock) + Ng351 <= n1729; + always @(posedge clock) + Ng352 <= n1733; + always @(posedge clock) + Ng353 <= n1737; + always @(posedge clock) + Ng357 <= n1741; + always @(posedge clock) + Ng364 <= n1745; + always @(posedge clock) + Ng365 <= n1749; + always @(posedge clock) + Ng366 <= n1753; + always @(posedge clock) + Pg6442 <= n394; + always @(posedge clock) + Ng367 <= n1757; + always @(posedge clock) + Ng368 <= n1761; + always @(posedge clock) + Ng372 <= n1765; + always @(posedge clock) + Ng379 <= n1769; + always @(posedge clock) + Ng380 <= n1773; + always @(posedge clock) + Ng381 <= n1777; + always @(posedge clock) + Ng382 <= n1781; + always @(posedge clock) + Ng383 <= n1785; + always @(posedge clock) + Ng387 <= n1789; + always @(posedge clock) + Ng394 <= n1793; + always @(posedge clock) + Pg6225 <= n398; + always @(posedge clock) + Ng395 <= n1797; + always @(posedge clock) + Ng396 <= n1801; + always @(posedge clock) + Ng397 <= n1805; + always @(posedge clock) + Ng324 <= n1809; + always @(posedge clock) + Ng554 <= n1814; + always @(posedge clock) + Ng557 <= n1819; + always @(posedge clock) + Ng510 <= n1824; + always @(posedge clock) + Ng513 <= n1829_1; + always @(posedge clock) + Ng523 <= n1833_1; + always @(posedge clock) + Ng524 <= n1837; + always @(posedge clock) + Pg5388 <= n401; + always @(posedge clock) + Ng564 <= n1842; + always @(posedge clock) + Ng569 <= n1846; + always @(posedge clock) + Ng570 <= n1851; + always @(posedge clock) + Ng571 <= n1855; + always @(posedge clock) + Ng572 <= n1860; + always @(posedge clock) + Ng573 <= n1864; + always @(posedge clock) + Ng574 <= n1869; + always @(posedge clock) + Ng565 <= n1873; + always @(posedge clock) + Ng566 <= n1878; + always @(posedge clock) + Ng567 <= n1882; + always @(posedge clock) + Pg4590 <= n405; + always @(posedge clock) + Ng568 <= n1887; + always @(posedge clock) + Ng489 <= n1891; + always @(posedge clock) + Ng486 <= n1896; + always @(posedge clock) + Ng487 <= n1901; + always @(posedge clock) + Ng488 <= n1906; + always @(posedge clock) + Ng11512 <= n1911; + always @(posedge clock) + Ng11515 <= n1915; + always @(posedge clock) + Ng11516 <= n1919; + always @(posedge clock) + Ng477 <= n1923; + always @(posedge clock) + Ng478 <= n1928; + always @(posedge clock) + Pg4450 <= n409; + always @(posedge clock) + Ng479 <= n1933; + always @(posedge clock) + Ng480 <= n1938; + always @(posedge clock) + Ng484 <= n1943; + always @(posedge clock) + Ng464 <= n1948; + always @(posedge clock) + Ng11517 <= n1953; + always @(posedge clock) + Ng11513 <= n1957; + always @(posedge clock) + Ng11514 <= n1961; + always @(posedge clock) + Ng528 <= n1965_1; + always @(posedge clock) + Ng535 <= n1969; + always @(posedge clock) + Ng542 <= n1973; + always @(posedge clock) + Pg4323 <= n413; + always @(posedge clock) + Ng543 <= n1978; + always @(posedge clock) + Ng544 <= n1982; + always @(posedge clock) + Ng548 <= n1987; + always @(posedge clock) + Ng549 <= n1992; + always @(posedge clock) + Ng8284 <= n1996; + always @(posedge clock) + Ng558 <= n2001; + always @(posedge clock) + Ng559 <= n2005; + always @(posedge clock) + Ng576 <= n2010_1; + always @(posedge clock) + Ng577 <= n2015; + always @(posedge clock) + Ng575 <= n2020; + always @(posedge clock) + Pg4321 <= n417; + always @(posedge clock) + Ng579 <= n2025; + always @(posedge clock) + Ng580 <= n2030_1; + always @(posedge clock) + Ng578 <= n2035; + always @(posedge clock) + Ng582 <= n2040_1; + always @(posedge clock) + Ng583 <= n2045; + always @(posedge clock) + Ng581 <= n2050; + always @(posedge clock) + Ng585 <= n2055; + always @(posedge clock) + Ng586 <= n2060; + always @(posedge clock) + Ng584 <= n2065; + always @(posedge clock) + Ng587 <= n2070; + always @(posedge clock) + Pg4200 <= n421; + always @(posedge clock) + Ng590 <= n2075; + always @(posedge clock) + Ng593 <= n2080; + always @(posedge clock) + Ng596 <= n2085; + always @(posedge clock) + Ng599 <= n2090; + always @(posedge clock) + Ng602 <= n2095; + always @(posedge clock) + Ng614 <= n2100; + always @(posedge clock) + Ng617 <= n2105; + always @(posedge clock) + Ng620 <= n2110; + always @(posedge clock) + Ng605 <= n2115; + always @(posedge clock) + Ng608 <= n2120; + always @(posedge clock) + Pg16297 <= n283; + always @(posedge clock) + Pg4090 <= n425; + always @(posedge clock) + Ng611 <= n2125; + always @(posedge clock) + Ng490 <= n2130; + always @(posedge clock) + Ng493 <= n2135; + always @(posedge clock) + Ng496 <= n2140; + always @(posedge clock) + Ng506 <= n2144; + always @(posedge clock) + Ng507 <= n2149; + always @(posedge clock) + Ng525 <= n2153; + always @(posedge clock) + Ng529 <= n2158; + always @(posedge clock) + Ng530 <= n2163; + always @(posedge clock) + Ng531 <= n2168; + always @(posedge clock) + Pg4088 <= n429; + always @(posedge clock) + Ng532 <= n2173; + always @(posedge clock) + Ng533 <= n2178; + always @(posedge clock) + Ng534 <= n2183; + always @(posedge clock) + Ng536 <= n2188; + always @(posedge clock) + Ng537 <= n2193; + always @(posedge clock) + Ng538 <= n2198; + always @(posedge clock) + Ng541 <= n2203; + always @(posedge clock) + Ng630 <= n2208; + always @(posedge clock) + Ng659 <= n2213; + always @(posedge clock) + Ng640 <= n2218; + always @(posedge clock) + Pg3993 <= n433; + always @(posedge clock) + Ng633 <= n2223; + always @(posedge clock) + Ng653 <= n2228; + always @(posedge clock) + Ng646 <= n2233; + always @(posedge clock) + Ng660 <= n2238; + always @(posedge clock) + Ng672 <= n2243; + always @(posedge clock) + Ng666 <= n2248; + always @(posedge clock) + Ng679 <= n2253; + always @(posedge clock) + Ng686 <= n2258; + always @(posedge clock) + Ng692 <= n2263; + always @(posedge clock) + Ng699 <= n2268; + always @(posedge clock) + Ng2817 <= n437; + always @(posedge clock) + Ng700 <= n2273; + always @(posedge clock) + Ng698 <= n2278; + always @(posedge clock) + Ng702 <= n2283; + always @(posedge clock) + Ng703 <= n2288; + always @(posedge clock) + Ng701 <= n2293; + always @(posedge clock) + Ng705 <= n2298; + always @(posedge clock) + Ng706 <= n2303; + always @(posedge clock) + Ng704 <= n2308; + always @(posedge clock) + Ng708 <= n2313; + always @(posedge clock) + Ng709 <= n2318; + always @(posedge clock) + Ng2933 <= n442; + always @(posedge clock) + Ng707 <= n2323; + always @(posedge clock) + Ng711 <= n2328; + always @(posedge clock) + Ng712 <= n2333; + always @(posedge clock) + Ng710 <= n2338; + always @(posedge clock) + Ng714 <= n2343; + always @(posedge clock) + Ng715 <= n2348; + always @(posedge clock) + Ng713 <= n2353; + always @(posedge clock) + Ng717 <= n2358; + always @(posedge clock) + Ng718 <= n2363; + always @(posedge clock) + Ng716 <= n2368; + always @(posedge clock) + Ng13457 <= n447; + always @(posedge clock) + Ng720 <= n2373; + always @(posedge clock) + Ng721 <= n2378; + always @(posedge clock) + Ng719 <= n2383; + always @(posedge clock) + Ng723 <= n2388; + always @(posedge clock) + Ng724 <= n2393; + always @(posedge clock) + Ng722 <= n2398; + always @(posedge clock) + Ng726 <= n2403; + always @(posedge clock) + Ng727 <= n2408; + always @(posedge clock) + Ng725 <= n2413; + always @(posedge clock) + Ng729 <= n2418; + always @(posedge clock) + Ng2883 <= n452; + always @(posedge clock) + Ng730 <= n2423; + always @(posedge clock) + Ng728 <= n2428; + always @(posedge clock) + Ng732 <= n2433; + always @(posedge clock) + Ng733 <= n2438; + always @(posedge clock) + Ng731 <= n2443; + always @(posedge clock) + Ng735 <= n2448; + always @(posedge clock) + Ng736 <= n2453; + always @(posedge clock) + Ng734 <= n2458; + always @(posedge clock) + Ng738 <= n2463; + always @(posedge clock) + Ng739 <= n2468; + always @(posedge clock) + Ng2888 <= n457; + always @(posedge clock) + Ng737 <= n2473; + always @(posedge clock) + Pg5437 <= n2477; + always @(posedge clock) + Pg6313 <= n2480; + always @(posedge clock) + Ng853 <= n2483; + always @(posedge clock) + Ng818 <= n2488; + always @(posedge clock) + Ng819 <= n2493; + always @(posedge clock) + Ng817 <= n2498; + always @(posedge clock) + Ng821 <= n2503; + always @(posedge clock) + Ng822 <= n2508; + always @(posedge clock) + Ng820 <= n2513; + always @(posedge clock) + Ng2896 <= n462; + always @(posedge clock) + Ng830 <= n2518; + always @(posedge clock) + Ng831 <= n2523; + always @(posedge clock) + Ng829 <= n2528; + always @(posedge clock) + Ng833 <= n2533; + always @(posedge clock) + Ng834 <= n2538; + always @(posedge clock) + Ng832 <= n2543; + always @(posedge clock) + Ng836 <= n2548; + always @(posedge clock) + Ng837 <= n2553; + always @(posedge clock) + Ng835 <= n2558; + always @(posedge clock) + Ng839 <= n2563; + always @(posedge clock) + Ng2892 <= n467; + always @(posedge clock) + Ng840 <= n2568; + always @(posedge clock) + Ng838 <= n2573; + always @(posedge clock) + Ng842 <= n2578; + always @(posedge clock) + Ng843 <= n2583; + always @(posedge clock) + Ng841 <= n2588; + always @(posedge clock) + Ng845 <= n2593; + always @(posedge clock) + Ng846 <= n2598; + always @(posedge clock) + Ng844 <= n2603; + always @(posedge clock) + Ng848 <= n2608; + always @(posedge clock) + Ng849 <= n2613; + always @(posedge clock) + Pg8275 <= n287; + always @(posedge clock) + Ng2903 <= n472; + always @(posedge clock) + Ng847 <= n2618; + always @(posedge clock) + Ng851 <= n2623; + always @(posedge clock) + Ng852 <= n2628; + always @(posedge clock) + Ng850 <= n2633; + always @(posedge clock) + Ng857 <= n2638; + always @(posedge clock) + Ng858 <= n2643; + always @(posedge clock) + Ng856 <= n2648; + always @(posedge clock) + Ng860 <= n2653; + always @(posedge clock) + Ng861 <= n2658; + always @(posedge clock) + Ng859 <= n2663; + always @(posedge clock) + Ng2900 <= n477; + always @(posedge clock) + Ng863 <= n2668; + always @(posedge clock) + Ng864 <= n2673; + always @(posedge clock) + Ng862 <= n2678; + always @(posedge clock) + Ng866 <= n2683; + always @(posedge clock) + Ng867 <= n2688; + always @(posedge clock) + Ng865 <= n2693; + always @(posedge clock) + Ng873 <= n2698; + always @(posedge clock) + Ng876 <= n2703; + always @(posedge clock) + Ng879 <= n2708; + always @(posedge clock) + Ng918 <= n2713; + always @(posedge clock) + Ng2908 <= n482; + always @(posedge clock) + Ng921 <= n2718; + always @(posedge clock) + Ng924 <= n2723; + always @(posedge clock) + Ng882 <= n2728; + always @(posedge clock) + Ng885 <= n2733; + always @(posedge clock) + Ng888 <= n2738; + always @(posedge clock) + Ng927 <= n2743; + always @(posedge clock) + Ng930 <= n2748; + always @(posedge clock) + Ng933 <= n2753; + always @(posedge clock) + Ng891 <= n2758; + always @(posedge clock) + Ng894 <= n2763; + always @(posedge clock) + Ng2912 <= n487; + always @(posedge clock) + Ng897 <= n2768; + always @(posedge clock) + Ng936 <= n2773; + always @(posedge clock) + Ng939 <= n2778; + always @(posedge clock) + Ng942 <= n2783; + always @(posedge clock) + Ng900 <= n2788; + always @(posedge clock) + Ng903 <= n2793; + always @(posedge clock) + Ng906 <= n2798; + always @(posedge clock) + Ng945 <= n2803; + always @(posedge clock) + Ng948 <= n2808; + always @(posedge clock) + Ng951 <= n2813; + always @(posedge clock) + Ng2917 <= n492; + always @(posedge clock) + Ng909 <= n2818; + always @(posedge clock) + Ng912 <= n2823; + always @(posedge clock) + Ng915 <= n2828; + always @(posedge clock) + Ng954 <= n2833; + always @(posedge clock) + Ng957 <= n2838; + always @(posedge clock) + Ng960 <= n2843; + always @(posedge clock) + Ng780 <= n2848; + always @(posedge clock) + Ng776 <= n2853; + always @(posedge clock) + Ng771 <= n2858; + always @(posedge clock) + Ng767 <= n2863; + always @(posedge clock) + Ng2924 <= n497; + always @(posedge clock) + Ng762 <= n2868; + always @(posedge clock) + Ng758 <= n2873; + always @(posedge clock) + Ng753 <= n2878; + always @(posedge clock) + Ng749 <= n2883; + always @(posedge clock) + Ng744 <= n2888; + always @(posedge clock) + Ng740 <= n2893; + always @(posedge clock) + Ng11524 <= n2898; + always @(posedge clock) + Ng11525 <= n2903; + always @(posedge clock) + Ng11526 <= n2908; + always @(posedge clock) + Ng11527 <= n2913; + always @(posedge clock) + Ng2920 <= n502; + always @(posedge clock) + Ng11528 <= n2918; + always @(posedge clock) + Ng11529 <= n2923; + always @(posedge clock) + Ng11530 <= n2928; + always @(posedge clock) + Ng11531 <= n2933; + always @(posedge clock) + Ng11532 <= n2938; + always @(posedge clock) + Ng11533 <= n2943; + always @(posedge clock) + Ng11534 <= n2948; + always @(posedge clock) + Ng11535 <= n2953; + always @(posedge clock) + Ng1095 <= n2958; + always @(posedge clock) + Ng1098 <= n2963; + always @(posedge clock) + Ng2984 <= n507; + always @(posedge clock) + Ng1101 <= n2968; + always @(posedge clock) + Ng1104 <= n2973; + always @(posedge clock) + Ng1107 <= n2978; + always @(posedge clock) + Ng1110 <= n2983; + always @(posedge clock) + Ng1114 <= n2988; + always @(posedge clock) + Ng1115 <= n2993; + always @(posedge clock) + Ng1113 <= n2998; + always @(posedge clock) + Ng1116 <= n3003; + always @(posedge clock) + Ng1119 <= n3008; + always @(posedge clock) + Ng1122 <= n3013; + always @(posedge clock) + Ng2985 <= n512; + always @(posedge clock) + Ng1125 <= n3018; + always @(posedge clock) + Ng1128 <= n3023; + always @(posedge clock) + Ng1131 <= n3028; + always @(posedge clock) + Ng1135 <= n3033; + always @(posedge clock) + Ng1136 <= n3038; + always @(posedge clock) + Ng1134 <= n3043; + always @(posedge clock) + Ng999 <= n3048; + always @(posedge clock) + Ng1000 <= n3053; + always @(posedge clock) + Ng1001 <= n3058; + always @(posedge clock) + Ng1002 <= n3063; + always @(posedge clock) + Ng2929 <= n516; + always @(posedge clock) + Ng1003 <= n3068; + always @(posedge clock) + Ng1004 <= n3073; + always @(posedge clock) + Ng1005 <= n3078; + always @(posedge clock) + Ng1006 <= n3083; + always @(posedge clock) + Ng1007 <= n3088; + always @(posedge clock) + Ng1009 <= n3093; + always @(posedge clock) + Ng1010 <= n3098; + always @(posedge clock) + Ng1008 <= n3103; + always @(posedge clock) + Ng1090 <= n3108; + always @(posedge clock) + Ng1091 <= n3113; + always @(posedge clock) + Pg8274 <= n291; + always @(posedge clock) + Ng2879 <= n521; + always @(posedge clock) + Ng1089 <= n3118; + always @(posedge clock) + Ng1137 <= n3123; + always @(posedge clock) + Ng1138 <= n3127; + always @(posedge clock) + Ng1139 <= n3132; + always @(posedge clock) + Ng1140 <= n3136; + always @(posedge clock) + Ng1141 <= n3141; + always @(posedge clock) + Ng966 <= n3145; + always @(posedge clock) + Ng967 <= n3150; + always @(posedge clock) + Ng968 <= n3154; + always @(posedge clock) + Ng969 <= n3159; + always @(posedge clock) + Ng2934 <= n525; + always @(posedge clock) + Ng970 <= n3163; + always @(posedge clock) + Ng971 <= n3168; + always @(posedge clock) + Ng972 <= n3172; + always @(posedge clock) + Ng973 <= n3177; + always @(posedge clock) + Ng974 <= n3181; + always @(posedge clock) + Ng975 <= n3186; + always @(posedge clock) + Ng976 <= n3190; + always @(posedge clock) + Ng977 <= n3194; + always @(posedge clock) + Ng978 <= n3198; + always @(posedge clock) + Ng986 <= n3203; + always @(posedge clock) + Ng2935 <= n529; + always @(posedge clock) + Ng992 <= n3208; + always @(posedge clock) + Ng985 <= n3213; + always @(posedge clock) + Ng1029 <= n3217; + always @(posedge clock) + Ng1036 <= n3221; + always @(posedge clock) + Ng1037 <= n3225; + always @(posedge clock) + Ng1038 <= n3229; + always @(posedge clock) + Ng1039 <= n3233; + always @(posedge clock) + Ng1040 <= n3237; + always @(posedge clock) + Ng1044 <= n3241; + always @(posedge clock) + Ng1051 <= n3245; + always @(posedge clock) + Ng2938 <= n533; + always @(posedge clock) + Ng1052 <= n3249; + always @(posedge clock) + Ng1053 <= n3253; + always @(posedge clock) + Ng1054 <= n3257; + always @(posedge clock) + Ng1055 <= n3261; + always @(posedge clock) + Ng1059 <= n3265; + always @(posedge clock) + Ng1066 <= n3269; + always @(posedge clock) + Ng1067 <= n3273; + always @(posedge clock) + Ng1068 <= n3277; + always @(posedge clock) + Ng1069 <= n3281; + always @(posedge clock) + Ng1070 <= n3285; + always @(posedge clock) + Ng2941 <= n537; + always @(posedge clock) + Ng1074 <= n3289; + always @(posedge clock) + Ng1081 <= n3293; + always @(posedge clock) + Ng1082 <= n3297; + always @(posedge clock) + Ng1083 <= n3301; + always @(posedge clock) + Ng1084 <= n3305; + always @(posedge clock) + Ng1011 <= n3309; + always @(posedge clock) + Ng1240 <= n3314; + always @(posedge clock) + Ng1243 <= n3319; + always @(posedge clock) + Ng1196 <= n3324; + always @(posedge clock) + Ng1199 <= n3329; + always @(posedge clock) + Ng2944 <= n541; + always @(posedge clock) + Ng1209 <= n3333; + always @(posedge clock) + Ng1210 <= n3337; + always @(posedge clock) + Ng1250 <= n3342; + always @(posedge clock) + Ng1255 <= n3346; + always @(posedge clock) + Ng1256 <= n3351; + always @(posedge clock) + Ng1257 <= n3355; + always @(posedge clock) + Ng1258 <= n3360; + always @(posedge clock) + Ng1259 <= n3364; + always @(posedge clock) + Ng1260 <= n3369; + always @(posedge clock) + Ng1251 <= n3373; + always @(posedge clock) + Ng2947 <= n545; + always @(posedge clock) + Ng1252 <= n3378; + always @(posedge clock) + Ng1253 <= n3382; + always @(posedge clock) + Ng1254 <= n3387; + always @(posedge clock) + Ng1176 <= n3391; + always @(posedge clock) + Ng1173 <= n3396; + always @(posedge clock) + Ng1174 <= n3401; + always @(posedge clock) + Ng1175 <= n3406; + always @(posedge clock) + Ng11539 <= n3411; + always @(posedge clock) + Ng11542 <= n3415; + always @(posedge clock) + Ng11543 <= n3419; + always @(posedge clock) + Ng2953 <= n549; + always @(posedge clock) + Ng1164 <= n3423; + always @(posedge clock) + Ng1165 <= n3428; + always @(posedge clock) + Ng1166 <= n3433; + always @(posedge clock) + Ng1167 <= n3438; + always @(posedge clock) + Ng1171 <= n3443; + always @(posedge clock) + Ng1151 <= n3448; + always @(posedge clock) + Ng11544 <= n3453; + always @(posedge clock) + Ng11540 <= n3457; + always @(posedge clock) + Ng11541 <= n3461; + always @(posedge clock) + Ng1214 <= n3465; + always @(posedge clock) + Ng2956 <= n553; + always @(posedge clock) + Ng1221 <= n3469; + always @(posedge clock) + Ng1228 <= n3473; + always @(posedge clock) + Ng1229 <= n3478; + always @(posedge clock) + Ng1230 <= n3482; + always @(posedge clock) + Ng1234 <= n3487; + always @(posedge clock) + Ng1235 <= n3492; + always @(posedge clock) + Ng8293 <= n3496; + always @(posedge clock) + Ng1244 <= n3501; + always @(posedge clock) + Ng1245 <= n3505; + always @(posedge clock) + Ng1262 <= n3510; + always @(posedge clock) + Ng2959 <= n557; + always @(posedge clock) + Ng1263 <= n3515; + always @(posedge clock) + Ng1261 <= n3520; + always @(posedge clock) + Ng1265 <= n3525; + always @(posedge clock) + Ng1266 <= n3530; + always @(posedge clock) + Ng1264 <= n3535; + always @(posedge clock) + Ng1268 <= n3540; + always @(posedge clock) + Ng1269 <= n3545; + always @(posedge clock) + Ng1267 <= n3550; + always @(posedge clock) + Ng1271 <= n3555; + always @(posedge clock) + Ng1272 <= n3560; + always @(posedge clock) + Pg8273 <= n295; + always @(posedge clock) + Ng2962 <= n561; + always @(posedge clock) + Ng1270 <= n3565; + always @(posedge clock) + Ng1273 <= n3570; + always @(posedge clock) + Ng1276 <= n3575; + always @(posedge clock) + Ng1279 <= n3580; + always @(posedge clock) + Ng1282 <= n3585; + always @(posedge clock) + Ng1285 <= n3590; + always @(posedge clock) + Ng1288 <= n3595; + always @(posedge clock) + Ng1300 <= n3600; + always @(posedge clock) + Ng1303 <= n3605; + always @(posedge clock) + Ng1306 <= n3610; + always @(posedge clock) + Ng2963 <= n565; + always @(posedge clock) + Ng1291 <= n3615; + always @(posedge clock) + Ng1294 <= n3620; + always @(posedge clock) + Ng1297 <= n3625; + always @(posedge clock) + Ng1177 <= n3630; + always @(posedge clock) + Ng1180 <= n3635; + always @(posedge clock) + Ng1183 <= n3640; + always @(posedge clock) + Ng1192 <= n3644; + always @(posedge clock) + Ng1193 <= n3649; + always @(posedge clock) + Ng1211 <= n3653; + always @(posedge clock) + Ng1215 <= n3658; + always @(posedge clock) + Ng2966 <= n569; + always @(posedge clock) + Ng1216 <= n3663; + always @(posedge clock) + Ng1217 <= n3668; + always @(posedge clock) + Ng1218 <= n3673; + always @(posedge clock) + Ng1219 <= n3678; + always @(posedge clock) + Ng1220 <= n3683; + always @(posedge clock) + Ng1222 <= n3688; + always @(posedge clock) + Ng1223 <= n3693; + always @(posedge clock) + Ng1224 <= n3698; + always @(posedge clock) + Ng1227 <= n3703; + always @(posedge clock) + Pg5629 <= n3708; + always @(posedge clock) + Ng2969 <= n573; + always @(posedge clock) + Pg5648 <= n3711; + always @(posedge clock) + Ng1315 <= n3714; + always @(posedge clock) + Ng1316 <= n3719; + always @(posedge clock) + Ng1345 <= n3724; + always @(posedge clock) + Ng1326 <= n3729; + always @(posedge clock) + Ng1319 <= n3734; + always @(posedge clock) + Ng1339 <= n3739; + always @(posedge clock) + Ng1332 <= n3744; + always @(posedge clock) + Ng1346 <= n3749; + always @(posedge clock) + Ng1358 <= n3754; + always @(posedge clock) + Ng2972 <= n577; + always @(posedge clock) + Ng1352 <= n3759; + always @(posedge clock) + Ng1365 <= n3764; + always @(posedge clock) + Ng1372 <= n3769; + always @(posedge clock) + Ng1378 <= n3774; + always @(posedge clock) + Ng1385 <= n3779; + always @(posedge clock) + Ng1386 <= n3784; + always @(posedge clock) + Ng1384 <= n3789; + always @(posedge clock) + Ng1388 <= n3794; + always @(posedge clock) + Ng1389 <= n3799; + always @(posedge clock) + Ng1387 <= n3804; + always @(posedge clock) + Ng2975 <= n581; + always @(posedge clock) + Ng1391 <= n3809; + always @(posedge clock) + Ng1392 <= n3814; + always @(posedge clock) + Ng1390 <= n3819; + always @(posedge clock) + Ng1394 <= n3824; + always @(posedge clock) + Ng1395 <= n3829; + always @(posedge clock) + Ng1393 <= n3834; + always @(posedge clock) + Ng1397 <= n3839; + always @(posedge clock) + Ng1398 <= n3844; + always @(posedge clock) + Ng1396 <= n3849; + always @(posedge clock) + Ng1400 <= n3854; + always @(posedge clock) + Ng2978 <= n585; + always @(posedge clock) + Ng1401 <= n3859; + always @(posedge clock) + Ng1399 <= n3864; + always @(posedge clock) + Ng1403 <= n3869; + always @(posedge clock) + Ng1404 <= n3874; + always @(posedge clock) + Ng1402 <= n3879; + always @(posedge clock) + Ng1406 <= n3884; + always @(posedge clock) + Ng1407 <= n3889; + always @(posedge clock) + Ng1405 <= n3894; + always @(posedge clock) + Ng1409 <= n3899; + always @(posedge clock) + Ng1410 <= n3904; + always @(posedge clock) + Ng2981 <= n589; + always @(posedge clock) + Ng1408 <= n3909; + always @(posedge clock) + Ng1412 <= n3914; + always @(posedge clock) + Ng1413 <= n3919; + always @(posedge clock) + Ng1411 <= n3924; + always @(posedge clock) + Ng1415 <= n3929; + always @(posedge clock) + Ng1416 <= n3934; + always @(posedge clock) + Ng1414 <= n3939; + always @(posedge clock) + Ng1418 <= n3944; + always @(posedge clock) + Ng1419 <= n3949; + always @(posedge clock) + Ng1417 <= n3954; + always @(posedge clock) + Ng2874 <= n593; + always @(posedge clock) + Ng1421 <= n3959; + always @(posedge clock) + Ng1422 <= n3964; + always @(posedge clock) + Ng1420 <= n3969; + always @(posedge clock) + Ng1424 <= n3974; + always @(posedge clock) + Ng1425 <= n3979; + always @(posedge clock) + Ng1423 <= n3984; + always @(posedge clock) + Ng1512 <= n3989; + always @(posedge clock) + Ng1513 <= n3994; + always @(posedge clock) + Ng1511 <= n3999; + always @(posedge clock) + Ng1515 <= n4004; + always @(posedge clock) + Ng1506 <= n598; + always @(posedge clock) + Ng1516 <= n4009; + always @(posedge clock) + Ng1514 <= n4014; + always @(posedge clock) + Ng1524 <= n4019; + always @(posedge clock) + Ng1525 <= n4024; + always @(posedge clock) + Ng1523 <= n4029; + always @(posedge clock) + Ng1527 <= n4034; + always @(posedge clock) + Ng1528 <= n4039; + always @(posedge clock) + Ng1526 <= n4044; + always @(posedge clock) + Ng1530 <= n4049; + always @(posedge clock) + Ng1531 <= n4054; + always @(posedge clock) + Pg8272 <= n299; + always @(posedge clock) + Ng1501 <= n603; + always @(posedge clock) + Ng1529 <= n4059; + always @(posedge clock) + Ng1533 <= n4064; + always @(posedge clock) + Ng1534 <= n4069; + always @(posedge clock) + Ng1532 <= n4074; + always @(posedge clock) + Ng1536 <= n4079; + always @(posedge clock) + Ng1537 <= n4084; + always @(posedge clock) + Ng1535 <= n4089; + always @(posedge clock) + Ng1539 <= n4094; + always @(posedge clock) + Ng1540 <= n4099; + always @(posedge clock) + Ng1538 <= n4104; + always @(posedge clock) + Ng1496 <= n608; + always @(posedge clock) + Ng1542 <= n4109; + always @(posedge clock) + Ng1543 <= n4114; + always @(posedge clock) + Ng1541 <= n4119; + always @(posedge clock) + Ng1545 <= n4124; + always @(posedge clock) + Ng1546 <= n4129; + always @(posedge clock) + Ng1544 <= n4134; + always @(posedge clock) + Ng1551 <= n4139; + always @(posedge clock) + Ng1552 <= n4144; + always @(posedge clock) + Ng1550 <= n4149; + always @(posedge clock) + Ng1554 <= n4154; + always @(posedge clock) + Ng1491 <= n613; + always @(posedge clock) + Ng1555 <= n4159; + always @(posedge clock) + Ng1553 <= n4164; + always @(posedge clock) + Ng1557 <= n4169; + always @(posedge clock) + Ng1558 <= n4174; + always @(posedge clock) + Ng1556 <= n4179; + always @(posedge clock) + Ng1560 <= n4184; + always @(posedge clock) + Ng1561 <= n4189; + always @(posedge clock) + Ng1559 <= n4194; + always @(posedge clock) + Ng1567 <= n4199; + always @(posedge clock) + Ng1570 <= n4204; + always @(posedge clock) + Ng1486 <= n618; + always @(posedge clock) + Ng1573 <= n4209; + always @(posedge clock) + Ng1612 <= n4214; + always @(posedge clock) + Ng1615 <= n4219; + always @(posedge clock) + Ng1618 <= n4224; + always @(posedge clock) + Ng1576 <= n4229; + always @(posedge clock) + Ng1579 <= n4234; + always @(posedge clock) + Ng1582 <= n4239; + always @(posedge clock) + Ng1621 <= n4244; + always @(posedge clock) + Ng1624 <= n4249; + always @(posedge clock) + Ng1627 <= n4254; + always @(posedge clock) + Ng1481 <= n623; + always @(posedge clock) + Ng1585 <= n4259; + always @(posedge clock) + Ng1588 <= n4264; + always @(posedge clock) + Ng1591 <= n4269; + always @(posedge clock) + Ng1630 <= n4274; + always @(posedge clock) + Ng1633 <= n4279; + always @(posedge clock) + Ng1636 <= n4284; + always @(posedge clock) + Ng1594 <= n4289; + always @(posedge clock) + Ng1597 <= n4294; + always @(posedge clock) + Ng1600 <= n4299; + always @(posedge clock) + Ng1639 <= n4304; + always @(posedge clock) + Ng1476 <= n628; + always @(posedge clock) + Ng1642 <= n4309; + always @(posedge clock) + Ng1645 <= n4314; + always @(posedge clock) + Ng1603 <= n4319; + always @(posedge clock) + Ng1606 <= n4324; + always @(posedge clock) + Ng1609 <= n4329; + always @(posedge clock) + Ng1648 <= n4334; + always @(posedge clock) + Ng1651 <= n4339; + always @(posedge clock) + Ng1654 <= n4344; + always @(posedge clock) + Ng1466 <= n4349; + always @(posedge clock) + Ng1462 <= n4354; + always @(posedge clock) + Ng1471 <= n633; + always @(posedge clock) + Ng1457 <= n4359; + always @(posedge clock) + Ng1453 <= n4364; + always @(posedge clock) + Ng1448 <= n4369; + always @(posedge clock) + Ng1444 <= n4374; + always @(posedge clock) + Ng1439 <= n4379; + always @(posedge clock) + Ng1435 <= n4384; + always @(posedge clock) + Ng1430 <= n4389; + always @(posedge clock) + Ng1426 <= n4394; + always @(posedge clock) + Ng11551 <= n4399; + always @(posedge clock) + Ng11552 <= n4404; + always @(posedge clock) + Ng13439 <= n638; + always @(posedge clock) + Ng11553 <= n4409; + always @(posedge clock) + Ng11554 <= n4414; + always @(posedge clock) + Ng11555 <= n4419; + always @(posedge clock) + Ng11556 <= n4424; + always @(posedge clock) + Ng11557 <= n4429; + always @(posedge clock) + Ng11558 <= n4434; + always @(posedge clock) + Ng11559 <= n4439; + always @(posedge clock) + Ng11560 <= n4444; + always @(posedge clock) + Ng11561 <= n4449; + always @(posedge clock) + Ng11562 <= n4454; + always @(posedge clock) + Ng813 <= n642; + always @(posedge clock) + Ng1789 <= n4459; + always @(posedge clock) + Ng1792 <= n4464; + always @(posedge clock) + Ng1795 <= n4469; + always @(posedge clock) + Ng1798 <= n4474; + always @(posedge clock) + Ng1801 <= n4479; + always @(posedge clock) + Ng1804 <= n4484; + always @(posedge clock) + Ng1808 <= n4489; + always @(posedge clock) + Ng1809 <= n4494; + always @(posedge clock) + Ng1807 <= n4499; + always @(posedge clock) + Ng1810 <= n4504; + always @(posedge clock) + Ng809 <= n646; + always @(posedge clock) + Ng1813 <= n4509; + always @(posedge clock) + Ng1816 <= n4514; + always @(posedge clock) + Ng1819 <= n4519; + always @(posedge clock) + Ng1822 <= n4524; + always @(posedge clock) + Ng1825 <= n4529; + always @(posedge clock) + Ng1829 <= n4534; + always @(posedge clock) + Ng1830 <= n4539; + always @(posedge clock) + Ng1828 <= n4544; + always @(posedge clock) + Ng1693 <= n4549; + always @(posedge clock) + Ng1694 <= n4554; + always @(posedge clock) + Pg8271 <= n303; + always @(posedge clock) + Ng805 <= n650; + always @(posedge clock) + Ng1695 <= n4559; + always @(posedge clock) + Ng1696 <= n4564_1; + always @(posedge clock) + Ng1697 <= n4569; + always @(posedge clock) + Ng1698 <= n4574; + always @(posedge clock) + Ng1699 <= n4579; + always @(posedge clock) + Ng1700 <= n4584; + always @(posedge clock) + Ng1701 <= n4589; + always @(posedge clock) + Ng1703 <= n4594; + always @(posedge clock) + Ng1704 <= n4599; + always @(posedge clock) + Ng1702 <= n4604; + always @(posedge clock) + Ng801 <= n654; + always @(posedge clock) + Ng1784 <= n4609_1; + always @(posedge clock) + Ng1785 <= n4614; + always @(posedge clock) + Ng1783 <= n4619; + always @(posedge clock) + Ng1831 <= n4624; + always @(posedge clock) + Ng1832 <= n4628; + always @(posedge clock) + Ng1833 <= n4633; + always @(posedge clock) + Ng1834 <= n4637; + always @(posedge clock) + Ng1835 <= n4642; + always @(posedge clock) + Ng1660 <= n4646; + always @(posedge clock) + Ng1661 <= n4651; + always @(posedge clock) + Ng797 <= n658; + always @(posedge clock) + Ng1662 <= n4655; + always @(posedge clock) + Ng1663 <= n4660; + always @(posedge clock) + Ng1664 <= n4664; + always @(posedge clock) + Ng1665 <= n4669; + always @(posedge clock) + Ng1666 <= n4673; + always @(posedge clock) + Ng1667 <= n4678; + always @(posedge clock) + Ng1668 <= n4682; + always @(posedge clock) + Ng1669 <= n4687; + always @(posedge clock) + Ng1670 <= n4691; + always @(posedge clock) + Ng1671 <= n4695; + always @(posedge clock) + Ng793 <= n662; + always @(posedge clock) + Ng1672 <= n4699; + always @(posedge clock) + Ng1680 <= n4704; + always @(posedge clock) + Ng1686 <= n4709; + always @(posedge clock) + Ng1679 <= n4714; + always @(posedge clock) + Ng1723 <= n4718; + always @(posedge clock) + Ng1730 <= n4722; + always @(posedge clock) + Ng1731 <= n4726; + always @(posedge clock) + Ng1732 <= n4730; + always @(posedge clock) + Ng1733 <= n4734; + always @(posedge clock) + Ng1734 <= n4738; + always @(posedge clock) + Ng789 <= n666; + always @(posedge clock) + Ng1738 <= n4742_1; + always @(posedge clock) + Ng1745 <= n4746; + always @(posedge clock) + Ng1746 <= n4750; + always @(posedge clock) + Ng1747 <= n4754; + always @(posedge clock) + Ng1748 <= n4758; + always @(posedge clock) + Ng1749 <= n4762; + always @(posedge clock) + Ng1753 <= n4766; + always @(posedge clock) + Ng1760 <= n4770; + always @(posedge clock) + Ng1761 <= n4774; + always @(posedge clock) + Ng1762 <= n4778; + always @(posedge clock) + Ng785 <= n670; + always @(posedge clock) + Ng1763 <= n4782; + always @(posedge clock) + Ng1764 <= n4786; + always @(posedge clock) + Ng1768 <= n4790; + always @(posedge clock) + Ng1775 <= n4794; + always @(posedge clock) + Ng1776 <= n4798; + always @(posedge clock) + Ng1777 <= n4802; + always @(posedge clock) + Ng1778 <= n4806; + always @(posedge clock) + Ng1705 <= n4810; + always @(posedge clock) + Ng1934 <= n4815; + always @(posedge clock) + Ng1937 <= n4820; + always @(posedge clock) + Ng13423 <= n674_1; + always @(posedge clock) + Ng1890 <= n4825; + always @(posedge clock) + Ng1893 <= n4830; + always @(posedge clock) + Ng1903 <= n4834_1; + always @(posedge clock) + Ng1904 <= n4838_1; + always @(posedge clock) + Ng1944 <= n4843; + always @(posedge clock) + Ng1949 <= n4847; + always @(posedge clock) + Ng1950 <= n4852; + always @(posedge clock) + Ng1951 <= n4856_1; + always @(posedge clock) + Ng1952 <= n4861_1; + always @(posedge clock) + Ng1953 <= n4865; + always @(posedge clock) + Ng125 <= n678; + always @(posedge clock) + Ng1954 <= n4870; + always @(posedge clock) + Ng1945 <= n4874; + always @(posedge clock) + Ng1946 <= n4879; + always @(posedge clock) + Ng1947 <= n4883; + always @(posedge clock) + Ng1948 <= n4888_1; + always @(posedge clock) + Ng1870 <= n4892; + always @(posedge clock) + Ng1867 <= n4897; + always @(posedge clock) + Ng1868 <= n4902; + always @(posedge clock) + Ng1869 <= n4907; + always @(posedge clock) + Ng11566 <= n4912; + always @(posedge clock) + Ng121 <= n682; + always @(posedge clock) + Ng11569 <= n4916; + always @(posedge clock) + Ng11570 <= n4920; + always @(posedge clock) + Ng1858 <= n4924_1; + always @(posedge clock) + Ng1859 <= n4929; + always @(posedge clock) + Ng1860 <= n4934; + always @(posedge clock) + Ng1861 <= n4939; + always @(posedge clock) + Ng1865 <= n4944; + always @(posedge clock) + Ng1845 <= n4949; + always @(posedge clock) + Ng11571 <= n4954; + always @(posedge clock) + Ng11567 <= n4958_1; + always @(posedge clock) + Ng117 <= n686; + always @(posedge clock) + Ng11568 <= n4962; + always @(posedge clock) + Ng1908 <= n4966; + always @(posedge clock) + Ng1915 <= n4970; + always @(posedge clock) + Ng1922 <= n4974; + always @(posedge clock) + Ng1923 <= n4979; + always @(posedge clock) + Ng1924 <= n4983_1; + always @(posedge clock) + Ng1928 <= n4988_1; + always @(posedge clock) + Ng1929 <= n4993_1; + always @(posedge clock) + Ng8302 <= n4997; + always @(posedge clock) + Ng1938 <= n5002; + assign Pg25420 = 4'hd >> { Pg3230, Pg3233 }; + assign n4525 = 64'h0000000000000008 >> { Ng3191, Ng3126, Ng3110, Ng3147, Ng3135, n4526 }; + assign n4526 = 4'h2 >> { Ng3139, Ng3120 }; + assign n4527 = 8'h02 >> { Ng3139, Ng3120, n4528 }; + assign n4528 = 32'd1 >> { Ng3191, Ng3126, Ng3110, Ng3135, Ng3147 }; + assign n4529_1 = 16'h2227 >> { Ng2992, Ng2991, Ng185, Ng3139 }; + assign n4530 = 32'd2 >> { Ng3191, Ng3126, Ng3135, Ng3147, Ng3110 }; + assign n4531 = 32'd8 >> { Ng3191, Ng3126, Ng3147, Ng3135, Ng3110 }; + assign n4532 = 64'hf500fd00f700ff00 >> { Ng3167, Ng3173, n4533, Ng3139, Ng3120, n4534_1 }; + assign n4533 = 64'h5ddd7fff7fff7fff >> { Ng3185, n4531, n4530, Ng3164, Ng3139, Ng3120 }; + assign n4534_1 = 32'd8 >> { Ng3191, Ng3126, Ng3135, Ng3110, Ng3147 }; + assign n4535 = 32'd2012708863 >> { Ng3170, Ng3176, Ng3120, n4534_1, Ng3139 }; + assign n4536 = 64'h0000000000000002 >> { Ng3139, Ng3120, Ng3191, Ng3126, Ng3110, Ng3147 }; + assign n4537 = 64'h0000000000000080 >> { Ng3191, Ng3126, Ng3110, n4526, Ng3135, Ng3147 }; + assign n4538 = 64'hcdddefffefffefff >> { Ng3103, n4534_1, n4530, Ng3097, Ng3139, Ng3120 }; + assign n4539_1 = 32'd4127062015 >> { Ng3101, Ng3102, Ng3120, Ng3139, n4534_1 }; + assign n4540 = 64'h75f57dfd77f77fff >> { Ng3105, Ng3107, Ng3108, Ng3139, Ng3120, n4531 }; + assign n4541 = 64'hbb11fb51bf15ff55 >> { Ng3093, Ng3094, n4542, Ng3139, n4531, Ng3120 }; + assign n4542 = 4'h1 >> { n4525, n4537 }; + assign n4543 = 64'h75f57dfd77f77fff >> { Ng3086, Ng3087, Ng3092, Ng3120, Ng3139, n4534_1 }; + assign Pg25489 = 32'd2970685713 >> { Ng3097, Ng3139, Ng3120, n4545, Ng3147 }; + assign n4545 = 64'h888c888c888caaae >> { Ng2992, Ng2991, Ng2984, Ng2985, Ng3139, Ng3120 }; + assign n953 = 8'h51 >> { Ng3125, n4525, Pg25420 }; + assign n958_1 = 8'h51 >> { Ng3123, n4525, Pg25420 }; + assign Pg16496 = 8'h5d >> { Ng2986, Pg5388, Ng2987 }; + assign n521 = 8'h5d >> { Ng2929, Pg8021, Ng2879 }; + assign n2213 = 8'hd8 >> { Ng659, n4551, Ng1315 }; + assign n4551 = 32'd1 >> { Ng3013, Ng3010, Ng3006, Ng3024, Ng3002 }; + assign n3724 = 8'hd8 >> { Ng1345, n4551, Ng1315 }; + assign n5214 = 8'hd8 >> { Ng2039, n4551, Ng1315 }; + assign n6716 = 8'hd8 >> { Ng2733, n4551, Ng1315 }; + assign n1814 = 8'h72 >> { Ng554, n4556, Ng1315 }; + assign n4556 = 32'd128 >> { Ng3032, Ng3036, n4557, Ng3018, Ng3028 }; + assign n4557 = 16'h0080 >> { Ng2993, Ng3002, Ng2998, n4558 }; + assign n4558 = 16'h0008 >> { Ng3010, Ng3006, Ng3013, Ng3024 }; + assign n3314 = 8'h72 >> { Ng1240, n4556, Ng1315 }; + assign n4815 = 8'h72 >> { Ng1934, n4556, Ng1315 }; + assign n6317 = 8'h72 >> { Ng2628, n4556, Ng1315 }; + assign n2149 = 32'd842185266 >> { n4565, Ng510, n4564, n4551, n4563 }; + assign n4563 = 64'h0000077707770777 >> { Ng493, Pg5648, Pg5629, Ng490, Ng1315, Ng496 }; + assign n4564 = 64'h0000077707770777 >> { Pg5648, Ng608, Ng605, Pg5629, Ng1315, Ng611 }; + assign n4565 = 64'h0000077707770777 >> { Pg5648, Ng617, Ng614, Pg5629, Ng1315, Ng620 }; + assign n3649 = 32'd842185266 >> { n4569_1, Ng1196, n4568, n4551, n4567 }; + assign n4567 = 64'h0000077707770777 >> { Pg5648, Ng1180, Ng1177, Pg5629, Ng1315, Ng1183 }; + assign n4568 = 64'h0000077707770777 >> { Pg5648, Ng1294, Ng1291, Pg5629, Ng1315, Ng1297 }; + assign n4569_1 = 64'h0000077707770777 >> { Pg5648, Ng1303, Ng1300, Pg5629, Ng1315, Ng1306 }; + assign n5150_1 = 32'd842185266 >> { n4573, Ng1890, n4572, n4551, n4571 }; + assign n4571 = 64'h0000077707770777 >> { Pg5648, Ng1874, Ng1871, Pg5629, Ng1315, Ng1877 }; + assign n4572 = 64'h0000077707770777 >> { Pg5648, Ng1988, Ng1985, Pg5629, Ng1315, Ng1991 }; + assign n4573 = 64'h0000077707770777 >> { Pg5648, Ng1997, Ng1994, Pg5629, Ng1315, Ng2000 }; + assign n6652_1 = 32'd842185266 >> { n4577, Ng2584, n4576, n4551, n4575 }; + assign n4575 = 64'h0000077707770777 >> { Pg5648, Ng2568, Ng2565, Pg5629, Ng1315, Ng2571 }; + assign n4576 = 64'h0000077707770777 >> { Pg5648, Ng2682, Ng2679, Pg5629, Ng1315, Ng2685 }; + assign n4577 = 64'h0000077707770777 >> { Pg5648, Ng2691, Ng2688, Pg5629, Ng1315, Ng2694 }; + assign n1987 = 16'h88d8 >> { Pg5629, Ng548, Ng544, Ng8284 }; + assign n3487 = 64'hf5e4b1a0b1a0b1a0 >> { Ng8284, Ng544, Ng1234, Ng1230, Pg5629, Ng8293 }; + assign n4988_1 = 32'd4122076320 >> { Ng1928, n3487, Ng1924, Pg5629, Ng8302 }; + assign n6490_1 = 32'd4122076320 >> { Ng2622, n4988_1, Ng2618, Pg5629, Ng8311 }; + assign n1703 = 64'hfffff888f888f888 >> { Ng420, Pg6313, Ng423, Ng853, Ng417, Pg5437 }; + assign n3203 = 64'hfffff888f888f888 >> { Pg6313, Ng1107, Ng853, Ng1110, Pg5437, Ng1104 }; + assign n4704 = 64'hfffff888f888f888 >> { Pg6313, Ng1801, Ng853, Ng1804, Pg5437, Ng1798 }; + assign n6206 = 64'hfffff888f888f888 >> { Pg6313, Ng2495, Ng853, Ng2498, Pg5437, Ng2492 }; + assign n4586 = 16'h0002 >> { n6490_1, Pg2637, Ng2633, Ng8311 }; + assign n4587 = 4'h8 >> { n4588, n4595 }; + assign n4588 = 64'h0000000000000002 >> { n4589_1, n4591, n4592, n4593, n4594_1, n4590 }; + assign n4589_1 = 64'hdd0ddd0d0000dd0d >> { Ng2780, Pg5648, Ng2779, Pg5629, Ng2778, Ng1315 }; + assign n4590 = 64'hdd0ddd0d0000dd0d >> { Ng2786, Pg5648, Ng2785, Pg5629, Ng2784, Ng1315 }; + assign n4591 = 64'hdd0ddd0d0000dd0d >> { Ng2798, Pg5648, Ng2797, Pg5629, Ng2796, Ng1315 }; + assign n4592 = 64'hdd0ddd0d0000dd0d >> { Ng2777, Pg5648, Ng2776, Pg5629, Ng2775, Ng1315 }; + assign n4593 = 64'hdd0ddd0d0000dd0d >> { Ng2807, Pg5648, Ng2806, Pg5629, Ng2805, Ng1315 }; + assign n4594_1 = 64'hdd0ddd0d0000dd0d >> { Ng2813, Pg5648, Ng2812, Pg5629, Ng2811, Ng1315 }; + assign n4595 = 64'h0000000000008000 >> { n4597, n4600, n4598, n4599_1, n4596, n4601 }; + assign n4596 = 64'hdd0ddd0d0000dd0d >> { Ng2774, Pg5648, Ng2773, Pg5629, Ng2772, Ng1315 }; + assign n4597 = 64'hdd0ddd0d0000dd0d >> { Ng2783, Pg5648, Ng2782, Pg5629, Ng2781, Ng1315 }; + assign n4598 = 64'hdd0ddd0d0000dd0d >> { Ng2792, Pg5648, Ng2791, Pg5629, Ng2790, Ng1315 }; + assign n4599_1 = 64'hdd0ddd0d0000dd0d >> { Ng2789, Pg5648, Ng2788, Pg5629, Ng2787, Ng1315 }; + assign n4600 = 64'hdd0ddd0d0000dd0d >> { Ng2801, Pg5648, Ng2800, Pg5629, Ng2799, Ng1315 }; + assign n4601 = 64'hdd0ddd0d0000dd0d >> { Ng2795, Pg5648, Ng2794, Pg5629, Ng2793, Ng1315 }; + assign n4602 = 4'h1 >> { n4587, n4592 }; + assign n4603 = 4'h6 >> { n4577, n4596 }; + assign n4604_1 = 4'h1 >> { n4587, n4600 }; + assign n4605 = 8'ha9 >> { n4587, n4591, n4577 }; + assign n4606 = 8'h54 >> { Ng2599, Ng2631, Ng2584 }; + assign n4607 = 8'h1b >> { Ng2612, Ng2615, Pg3229 }; + assign n7165 = 32'd4042453746 >> { n4605, n4586, n4609, Ng2584, Ng2631 }; + assign n4609 = 32'd3303309540 >> { n4603, n4586, Ng2611, n4611, n4610 }; + assign n4610 = 16'h0002 >> { n6490_1, Pg2637, Ng2633, n4606 }; + assign n4611 = 8'h54 >> { Ng2599, Ng2584, Ng2631 }; + assign n7155 = 64'h1054327600542276 >> { Ng2608, n4613, n4614_1, Ng2599, Ng2631, Ng2584 }; + assign n4613 = 16'h8882 >> { n4587, n4589_1, n4577, n4586 }; + assign n4614_1 = 8'h01 >> { n6490_1, Pg2637, Ng2633 }; + assign n7150 = 64'h1054327600542276 >> { Ng2607, n4616, n4614_1, Ng2599, Ng2631, Ng2584 }; + assign n4616 = 16'h8882 >> { n4587, n4597, n4576, n4586 }; + assign n7145 = 16'heeae >> { Ng2606, n4610, n4621, n4618 }; + assign n4618 = 16'h0222 >> { n4619_1, n4614_1, Ng2584, Ng2631 }; + assign n4619_1 = 32'd2324343434 >> { Ng2808, Ng1315, n4620, n4587, Ng8311 }; + assign n4620 = 16'hdd0d >> { Ng2810, Pg5648, Ng2809, Pg5629 }; + assign n4621 = 32'd2146893824 >> { n4611, n4577, n4590, n4586, Ng2584 }; + assign n7140 = 32'd4076007666 >> { Ng2605, n4610, n4623, n4624_1, n4611 }; + assign n4623 = 16'h2202 >> { n4619_1, n4614_1, Ng2584, Ng2631 }; + assign n4624_1 = 16'h8008 >> { n4576, n4599_1, n4586, Ng2584 }; + assign n7135 = 16'heeae >> { Ng2604, n4610, n4626, n4623 }; + assign n4626 = 32'd2146893824 >> { n4611, n4577, n4598, n4586, Ng2584 }; + assign n7130 = 32'd4076007666 >> { Ng2603, n4610, n4618, n4628_1, n4611 }; + assign n4628_1 = 16'h8008 >> { n4576, n4601, n4586, Ng2584 }; + assign n4629 = 4'h8 >> { n4630, Ng8302 }; + assign n4630 = 8'h01 >> { n4988_1, Pg1943, Ng1939 }; + assign n4631 = 4'h1 >> { n4632, n4645 }; + assign n4632 = 64'h0000000000008000 >> { n4641, n4644, n4633_1, n4642_1, n4643, n4640 }; + assign n4633_1 = 64'h0000000000000008 >> { n4634, n4636, n4637_1, n4639, n4638, n4635 }; + assign n4634 = 64'hdd0ddd0d0000dd0d >> { Ng2089, Pg5648, Ng2088, Pg5629, Ng2087, Ng1315 }; + assign n4635 = 64'hdd0ddd0d0000dd0d >> { Ng2092, Pg5648, Ng2091, Pg5629, Ng2090, Ng1315 }; + assign n4636 = 64'hdd0ddd0d0000dd0d >> { Ng2107, Pg5648, Ng2106, Pg5629, Ng2105, Ng1315 }; + assign n4637_1 = 64'hdd0ddd0d0000dd0d >> { Ng2119, Pg5648, Ng2118, Pg5629, Ng2117, Ng1315 }; + assign n4638 = 64'hdd0ddd0d0000dd0d >> { Ng2080, Pg5648, Ng2079, Pg5629, Ng2078, Ng1315 }; + assign n4639 = 64'hdd0ddd0d0000dd0d >> { Ng2083, Pg5648, Ng2082, Pg5629, Ng2081, Ng1315 }; + assign n4640 = 64'hdd0ddd0d0000dd0d >> { Ng2101, Pg5648, Ng2100, Pg5629, Ng2099, Ng1315 }; + assign n4641 = 64'hdd0ddd0d0000dd0d >> { Ng2113, Pg5648, Ng2112, Pg5629, Ng2111, Ng1315 }; + assign n4642_1 = 64'hdd0ddd0d0000dd0d >> { Ng2095, Pg5648, Ng2094, Pg5629, Ng2093, Ng1315 }; + assign n4643 = 64'hdd0ddd0d0000dd0d >> { Ng2098, Pg5648, Ng2097, Pg5629, Ng2096, Ng1315 }; + assign n4644 = 64'hdd0ddd0d0000dd0d >> { Ng2104, Pg5648, Ng2103, Pg5629, Ng2102, Ng1315 }; + assign n4645 = 64'hdd0ddd0d0000dd0d >> { Ng2086, Pg5648, Ng2085, Pg5629, Ng2084, Ng1315 }; + assign n4646_1 = 4'h2 >> { n4645, n4632 }; + assign n4647 = 64'h2aa2a22a7ff7f77f >> { n4650, n4648, n4649, n4573, n4629, Ng1937 }; + assign n4648 = 8'h51 >> { n4645, n4632, n4644 }; + assign n4649 = 16'h9a99 >> { n4632, n4645, n4636, n4572 }; + assign n4650 = 16'ha280 >> { Ng1921, Ng1918, Pg3229, n4651_1 }; + assign n4651_1 = 64'h0001000100010000 >> { Ng1905, Ng1937, Pg1943, Ng1939, n4988_1, Ng1890 }; + assign n4652 = 8'h54 >> { Ng1905, Ng1890, Ng1937 }; + assign n7110 = 64'h1054327600542276 >> { Ng1914, n4654, n4630, Ng1905, Ng1937, Ng1890 }; + assign n4654 = 8'h28 >> { n4631, n4573, n4629 }; + assign n7105 = 64'h1054327600542276 >> { Ng1913, n4656, n4630, Ng1905, Ng1937, Ng1890 }; + assign n4656 = 16'h8882 >> { n4646_1, n4634, n4572, n4629 }; + assign n7100 = 16'heeae >> { Ng1912, n4651_1, n4660_1, n4658 }; + assign n4658 = 32'd33694210 >> { n4646_1, n4659, n4629, Ng1890, Ng1937 }; + assign n4659 = 64'hdd0ddd0d0000dd0d >> { Ng2116, Pg5648, Ng2115, Pg5629, Ng2114, Ng1315 }; + assign n4660_1 = 32'd2146893824 >> { n4652, n4573, n4635, n4629, Ng1890 }; + assign n7095 = 16'hdd5d >> { Ng1911, n4651_1, n4663, n4662 }; + assign n4662 = 64'hdfddffdddfdddfdd >> { n4659, n4646_1, n4630, Ng8302, Ng1890, Ng1937 }; + assign n4663 = 32'd2146893824 >> { n4652, n4572, n4642_1, n4629, Ng1890 }; + assign n7090 = 32'd791613231 >> { Ng1910, n4651_1, n4662, n4665, n4652 }; + assign n4665 = 16'h8008 >> { n4573, n4643, n4629, Ng1890 }; + assign n7085 = 32'd4076007666 >> { Ng1909, n4651_1, n4658, n4667, n4652 }; + assign n4667 = 16'h8008 >> { n4572, n4640, n4629, Ng1890 }; + assign n7080 = 64'h82282882ffffffff >> { n4694, n4669_1, n4691_1, n4697, n4698, Ng1196 }; + assign n4669_1 = 32'd1771465104 >> { n4671, n4670, n4689, n4690, n4688 }; + assign n4670 = 16'h8882 >> { n4673_1, n4675, n4569_1, n4671 }; + assign n4671 = 4'h8 >> { n4672, Ng8293 }; + assign n4672 = 8'h01 >> { n3487, Pg1249, Ng1245 }; + assign n4673_1 = 4'h8 >> { n4674, n4681 }; + assign n4674 = 64'h0000000000000080 >> { n4675, n4676, n4680, n4678_1, n4679, n4677 }; + assign n4675 = 64'hdd0ddd0d0000dd0d >> { Ng1392, Pg5648, Ng1391, Pg5629, Ng1390, Ng1315 }; + assign n4676 = 64'hdd0ddd0d0000dd0d >> { Ng1413, Pg5648, Ng1412, Pg5629, Ng1411, Ng1315 }; + assign n4677 = 64'hdd0ddd0d0000dd0d >> { Ng1404, Pg5648, Ng1403, Pg5629, Ng1402, Ng1315 }; + assign n4678_1 = 64'hdd0ddd0d0000dd0d >> { Ng1401, Pg5648, Ng1400, Pg5629, Ng1399, Ng1315 }; + assign n4679 = 64'hdd0ddd0d0000dd0d >> { Ng1386, Pg5648, Ng1385, Pg5629, Ng1384, Ng1315 }; + assign n4680 = 64'hdd0ddd0d0000dd0d >> { Ng1425, Pg5648, Ng1424, Pg5629, Ng1423, Ng1315 }; + assign n4681 = 64'h0000000000000008 >> { n4683, n4685, n4686, n4687_1, n4684, n4682_1 }; + assign n4682_1 = 64'hdd0ddd0d0000dd0d >> { Ng1398, Pg5648, Ng1397, Pg5629, Ng1396, Ng1315 }; + assign n4683 = 64'hdd0ddd0d0000dd0d >> { Ng1389, Pg5648, Ng1388, Pg5629, Ng1387, Ng1315 }; + assign n4684 = 64'hdd0ddd0d0000dd0d >> { Ng1407, Pg5648, Ng1406, Pg5629, Ng1405, Ng1315 }; + assign n4685 = 64'hdd0ddd0d0000dd0d >> { Ng1419, Pg5648, Ng1418, Pg5629, Ng1417, Ng1315 }; + assign n4686 = 64'hdd0ddd0d0000dd0d >> { Ng1410, Pg5648, Ng1409, Pg5629, Ng1408, Ng1315 }; + assign n4687_1 = 64'hdd0ddd0d0000dd0d >> { Ng1395, Pg5648, Ng1394, Pg5629, Ng1393, Ng1315 }; + assign n4688 = 4'h1 >> { n4673_1, n4687_1 }; + assign n4689 = 8'h82 >> { n4569_1, n4679, n4671 }; + assign n4690 = 4'h1 >> { n4673_1, n4683 }; + assign n4691_1 = 4'h9 >> { n4692, n4693 }; + assign n4692 = 8'h82 >> { n4569_1, n4682_1, n4671 }; + assign n4693 = 8'h82 >> { n4568, n4678_1, n4671 }; + assign n4694 = 64'hbb11fb51bf15ff55 >> { Ng1227, Ng1224, n4695_1, Pg3229, n4696, Ng1243 }; + assign n4695_1 = 32'd3615325655 >> { n4676, n4686, n4568, n4569_1, n4671 }; + assign n4696 = 16'h2220 >> { Ng1211, Ng1243, Ng1196, n4672 }; + assign n4697 = 8'h82 >> { n4569_1, n4677, n4671 }; + assign n4698 = 8'h82 >> { n4568, n4684, n4671 }; + assign n7075 = 32'd4177195250 >> { Ng1223, n4689, n4700, n4696, n4701 }; + assign n4700 = 64'h0202022022222222 >> { n4671, n4673_1, n4686, n4569_1, Ng1196, Ng1243 }; + assign n4701 = 8'h54 >> { Ng1211, Ng1196, Ng1243 }; + assign n7065 = 64'h1054327600542276 >> { Ng1220, n4670, n4672, Ng1211, Ng1243, Ng1196 }; + assign n7060 = 64'h1054327600542276 >> { Ng1219, n4704_1, n4672, Ng1211, Ng1243, Ng1196 }; + assign n4704_1 = 8'h28 >> { n4688, n4568, n4671 }; + assign n7055 = 32'd4177195250 >> { Ng1218, n4692, n4706, n4696, n4701 }; + assign n4706 = 32'd33694210 >> { n4673_1, n4707, n4671, Ng1196, Ng1243 }; + assign n4707 = 64'hdd0ddd0d0000dd0d >> { Ng1422, Pg5648, Ng1421, Pg5629, Ng1420, Ng1315 }; + assign n7050 = 32'd2410614575 >> { Ng1217, n4693, n4709_1, n4696, n4701 }; + assign n4709_1 = 64'hdfddffdddfdddfdd >> { n4707, n4673_1, n4672, Ng8293, Ng1196, Ng1243 }; + assign n7045 = 32'd2410614575 >> { Ng1216, n4697, n4709_1, n4696, n4701 }; + assign n7040 = 32'd4177195250 >> { Ng1215, n4698, n4706, n4696, n4701 }; + assign n4712 = 8'h82 >> { n4564, n4715, n4728 }; + assign n4713 = 4'h8 >> { n4714_1, n4721 }; + assign n4714_1 = 64'h0000000000008000 >> { n4718_1, n4720, n4717, n4715, n4719, n4716 }; + assign n4715 = 64'hdd0ddd0d0000dd0d >> { Ng721, Pg5648, Ng720, Pg5629, Ng719, Ng1315 }; + assign n4716 = 64'hdd0ddd0d0000dd0d >> { Ng712, Pg5648, Ng711, Pg5629, Ng710, Ng1315 }; + assign n4717 = 64'hdd0ddd0d0000dd0d >> { Ng700, Pg5648, Ng699, Pg5629, Ng698, Ng1315 }; + assign n4718_1 = 64'hdd0ddd0d0000dd0d >> { Ng739, Pg5648, Ng738, Pg5629, Ng737, Ng1315 }; + assign n4719 = 64'hdd0ddd0d0000dd0d >> { Ng715, Pg5648, Ng714, Pg5629, Ng713, Ng1315 }; + assign n4720 = 64'hdd0ddd0d0000dd0d >> { Ng733, Pg5648, Ng732, Pg5629, Ng731, Ng1315 }; + assign n4721 = 64'h0000000000000002 >> { n4722_1, n4724, n4725, n4726_1, n4727, n4723 }; + assign n4722_1 = 64'hdd0ddd0d0000dd0d >> { Ng706, Pg5648, Ng705, Pg5629, Ng704, Ng1315 }; + assign n4723 = 64'hdd0ddd0d0000dd0d >> { Ng718, Pg5648, Ng717, Pg5629, Ng716, Ng1315 }; + assign n4724 = 64'hdd0ddd0d0000dd0d >> { Ng703, Pg5648, Ng702, Pg5629, Ng701, Ng1315 }; + assign n4725 = 64'hdd0ddd0d0000dd0d >> { Ng724, Pg5648, Ng723, Pg5629, Ng722, Ng1315 }; + assign n4726_1 = 64'hdd0ddd0d0000dd0d >> { Ng709, Pg5648, Ng708, Pg5629, Ng707, Ng1315 }; + assign n4727 = 64'hdd0ddd0d0000dd0d >> { Ng727, Pg5648, Ng726, Pg5629, Ng725, Ng1315 }; + assign n4728 = 4'h8 >> { n4729, Ng8284 }; + assign n4729 = 32'd16842753 >> { Ng8284, Pg5629, n1987, Pg563, Ng559 }; + assign n4730_1 = 8'h82 >> { n4565, n4723, n4728 }; + assign n4731 = 8'h82 >> { n4564, n4719, n4728 }; + assign n4732 = 16'h8882 >> { n4713, n4722_1, n4565, n4728 }; + assign n4733 = 16'h8882 >> { n4713, n4726_1, n4564, n4728 }; + assign n4734_1 = 8'h82 >> { n4565, n4717, n4728 }; + assign n4735 = 64'hbb11fb51bf15ff55 >> { Ng541, Ng538, n4736, Pg3229, n4737, Ng557 }; + assign n4736 = 32'd3615325655 >> { n4725, n4727, n4564, n4565, n4728 }; + assign n4737 = 8'h08 >> { Ng510, Ng525, n4729 }; + assign n7030 = 32'd4177195250 >> { Ng537, n4734_1, n4739, n4737, n4740 }; + assign n4739 = 64'h0202022022222222 >> { n4728, n4713, n4725, n4565, Ng510, Ng557 }; + assign n4740 = 8'h54 >> { Ng525, Ng510, Ng557 }; + assign n7020 = 64'h1054327600542276 >> { Ng534, n4732, n4729, Ng525, Ng557, Ng510 }; + assign n7015 = 64'h1054327600542276 >> { Ng533, n4733, n4729, Ng525, Ng557, Ng510 }; + assign n7010 = 16'heeae >> { Ng532, n4737, n4746_1, n4744 }; + assign n4744 = 32'd33694210 >> { n4713, n4745, n4728, Ng510, Ng557 }; + assign n4745 = 64'hdd0ddd0d0000dd0d >> { Ng736, Pg5648, Ng735, Pg5629, Ng734, Ng1315 }; + assign n4746_1 = 32'd2146893824 >> { n4740, n4565, n4716, n4728, Ng510 }; + assign n7005 = 32'd2410614575 >> { Ng531, n4731, n4748, n4737, n4740 }; + assign n4748 = 64'hdfddffdddfdddfdd >> { n4745, n4713, n4729, Ng8284, Ng510, Ng557 }; + assign n7000 = 32'd2410614575 >> { Ng530, n4730_1, n4748, n4737, n4740 }; + assign n6995 = 32'd4177195250 >> { Ng529, n4712, n4744, n4737, n4740 }; + assign n7180_1 = 32'd4294904426 >> { Pg3234, n4557, Ng13475, Ng2993, Ng2998 }; + assign n875 = 8'hd8 >> { Ng3108, n6490_1, Ng1315 }; + assign n870 = 8'hd8 >> { Ng3107, n6490_1, Pg5648 }; + assign n865 = 8'hd8 >> { Ng3106, n6490_1, Pg5629 }; + assign n6076 = 64'h444444444444444e >> { n4816, n6672, n4810_1, n4813, Ng2392, Ng853 }; + assign n4756 = 4'h2 >> { n4757, n4770_1 }; + assign n4757 = 64'hdd0ddd0d0000dd0d >> { n4768, n4769, n4766_1, n4767, n4758_1, n4761 }; + assign n4758_1 = 16'h1428 >> { n4759, n4760, Ng2185, Ng2195 }; + assign n4759 = 64'h0000077707770777 >> { Pg6313, Ng2291, Ng853, Ng2294, Pg5437, Ng2288 }; + assign n4760 = 64'h0000077707770777 >> { Pg6313, Ng2282, Ng853, Ng2285, Pg5437, Ng2279 }; + assign n4761 = 64'h0000ebd7ebd70000 >> { n4762_1, n4765, n4763, n4764, Ng2165, Ng2175 }; + assign n4762_1 = 64'hdd0ddd0d0000dd0d >> { Ng2252, Pg6313, Ng2250, Ng853, Ng2251, Pg5437 }; + assign n4763 = 64'h0000077707770777 >> { Pg6313, Ng2273, Ng853, Ng2276, Pg5437, Ng2270 }; + assign n4764 = 64'h0000077707770777 >> { Pg6313, Ng2264, Ng853, Ng2267, Pg5437, Ng2261 }; + assign n4765 = 64'h0000077707770777 >> { Pg6313, Ng2300, Ng853, Ng2303, Pg5437, Ng2297 }; + assign n4766_1 = 16'h6006 >> { n4762_1, n4765, n4763, Ng2175 }; + assign n4767 = 64'hebd700000000ebd7 >> { n4760, Ng2185, n4764, n4759, Ng2195, Ng2165 }; + assign n4768 = 16'h6006 >> { n4762_1, n4765, n4759, Ng2195 }; + assign n4769 = 64'hebd700000000ebd7 >> { n4764, Ng2165, n4763, n4760, Ng2185, Ng2175 }; + assign n4770_1 = 4'h2 >> { n4771, Ng2257 }; + assign n4771 = 64'hdd0ddd0d0000dd0d >> { Ng2246, Pg6313, Ng2244, Ng853, Ng2245, Pg5437 }; + assign n4772 = 64'hdd0ddd0d0000dd0d >> { Ng2234, Pg6313, Ng2232, Ng853, Ng2233, Pg5437 }; + assign n4773 = 64'hdd0ddd0d0000dd0d >> { Ng2222, Pg6313, Ng2220, Ng853, Ng2221, Pg5437 }; + assign n4774_1 = 64'hdd0ddd0d0000dd0d >> { Ng2225, Pg6313, Ng2223, Ng853, Ng2224, Pg5437 }; + assign n4775 = 64'hdd0ddd0d0000dd0d >> { Ng2219, Pg6313, Ng2217, Ng853, Ng2218, Pg5437 }; + assign n4776 = 64'hdd0ddd0d0000dd0d >> { Ng2210, Pg6313, Ng2208, Ng853, Ng2209, Pg5437 }; + assign n4777 = 64'hdd0ddd0d0000dd0d >> { Ng2231, Pg6313, Ng2229, Ng853, Ng2230, Pg5437 }; + assign n4778_1 = 64'hdd0ddd0d0000dd0d >> { Ng2249, Pg6313, Ng2247, Ng853, Ng2248, Pg5437 }; + assign n4779 = 64'hdd0ddd0d0000dd0d >> { Ng2207, Pg6313, Ng2205, Ng853, Ng2206, Pg5437 }; + assign n4780 = 64'hdd0ddd0d0000dd0d >> { Ng2237, Pg6313, Ng2235, Ng853, Ng2236, Pg5437 }; + assign n4781 = 64'hdd0ddd0d0000dd0d >> { Ng2240, Pg6313, Ng2238, Ng853, Ng2239, Pg5437 }; + assign n4782_1 = 64'hdd0ddd0d0000dd0d >> { Ng2228, Pg6313, Ng2226, Ng853, Ng2227, Pg5437 }; + assign n4783 = 64'hdd0ddd0d0000dd0d >> { Ng2398, Pg6313, Ng2396, Ng853, Ng2397, Pg5437 }; + assign n4784 = 64'h0000000080000000 >> { n4783, n4786_1, n4787, n4788, n4789, n4785 }; + assign n4785 = 16'h1428 >> { n4776, n4774_1, Ng2185, Ng2170 }; + assign n4786_1 = 64'h0000002800280028 >> { n4773, Ng2180, n4771, n4777, Ng2195, Ng2257 }; + assign n4787 = 64'h6006600660060000 >> { n4773, Ng2180, n4762_1, n4780, n4782_1, Ng2190 }; + assign n4788 = 4'h6 >> { n4775, Ng2175 }; + assign n4789 = 64'h0660000000000660 >> { n4778_1, n4781, n4779, Ng2165, n4772, Ng2200 }; + assign n4790_1 = 4'h8 >> { n4771, Ng2257 }; + assign n4791 = 64'hdd0ddd0d0000dd0d >> { Ng2394, Pg6313, Ng2395, Ng853, Ng2393, Pg5437 }; + assign n4792 = 64'hdd0ddd0d0000dd0d >> { Ng2388, Pg6313, Ng2389, Ng853, Ng2387, Pg5437 }; + assign n4793 = 64'h9f9f00099f9f000f >> { n4796, n4798_1, n4801, n4794_1, n4802_1, Ng2200 }; + assign n4794_1 = 4'h6 >> { n4795, Ng2170 }; + assign n4795 = 64'h0000077707770777 >> { Pg6313, Ng2309, Ng853, Ng2312, Pg5437, Ng2306 }; + assign n4796 = 4'h9 >> { n4778_1, n4797 }; + assign n4797 = 64'h0000077707770777 >> { Pg6313, Ng2345, Ng853, Ng2348, Pg5437, Ng2342 }; + assign n4798_1 = 64'h9ff9000000009ff9 >> { n4800, Ng2190, n4778_1, n4797, n4799, Ng2180 }; + assign n4799 = 64'h0000077707770777 >> { Pg6313, Ng2318, Ng853, Ng2321, Pg5437, Ng2315 }; + assign n4800 = 64'h0000077707770777 >> { Pg6313, Ng2327, Ng853, Ng2330, Pg5437, Ng2324 }; + assign n4801 = 16'h1428 >> { n4799, n4800, Ng2190, Ng2180 }; + assign n4802_1 = 64'h0000077707770777 >> { Pg6313, Ng2336, Ng853, Ng2339, Pg5437, Ng2333 }; + assign n4803 = 32'd268505361 >> { n4794_1, n4799, Ng2180, n4796, n4804 }; + assign n4804 = 16'h1428 >> { n4802_1, n4800, Ng2190, Ng2200 }; + assign n4805 = 64'h1555555555555555 >> { n4807, n4808, n4806_1, n4801, n4766_1, n4771 }; + assign n4806_1 = 16'h4182 >> { n4802_1, n4778_1, n4797, Ng2200 }; + assign n4807 = 16'h1428 >> { n4764, n4759, Ng2195, Ng2165 }; + assign n4808 = 16'h1428 >> { n4795, n4760, Ng2185, Ng2170 }; + assign n4809 = 64'hdd0ddd0d0000dd0d >> { Ng2391, Pg6313, Ng2392, Ng853, Ng2390, Pg5437 }; + assign n4810_1 = 32'd269553937 >> { n4812, n4805, n4811, n4756, n4809 }; + assign n4811 = 8'ha8 >> { n4803, n4793, n4770_1 }; + assign n4812 = 4'h8 >> { n4791, Ng2257 }; + assign n4813 = 4'h2 >> { n4815_1, n4814 }; + assign n4814 = 32'd2147483648 >> { n4785, n4786_1, n4787, n4788, n4789 }; + assign n4815_1 = 64'hdd0ddd0d0000dd0d >> { Ng2479, Pg6313, Ng2477, Ng853, Ng2478, Pg5437 }; + assign n4816 = 4'h2 >> { n4809, n4792 }; + assign n6071_1 = 64'h444444444444444e >> { n4816, n6672, n4810_1, n4813, Ng2391, Pg6313 }; + assign n6066 = 64'h444444444444444e >> { n4816, n6672, n4810_1, n4813, Ng2390, Pg5437 }; + assign n5834 = 32'd1920094322 >> { n4833, n4828, Ng2348, n4820_1, Ng853 }; + assign n4820_1 = 32'd4210184400 >> { n4824, n6673, n4778_1, n4823, n4821 }; + assign n4821 = 16'hdd0d >> { n4792, n4790_1, n4815_1, n4814 }; + assign n4822 = 8'h02 >> { n4791, n4792, n4809 }; + assign n4823 = 4'h8 >> { n4784, n4809 }; + assign n4824 = 32'd128 >> { n4799, n4763, n4827, n4825_1, n4826 }; + assign n4825_1 = 8'h08 >> { n4809, n4792, n4791 }; + assign n4826 = 32'd2147483648 >> { n4802_1, n4800, n4764, n4759, n4760 }; + assign n4827 = 8'h01 >> { n4795, n4797, n4765 }; + assign n4828 = 8'h8a >> { n4823, n6673, n4821 }; + assign n4829 = 4'h1 >> { n4824, n4830_1 }; + assign n4830_1 = 8'h80 >> { n4826, n4831, n4832 }; + assign n4831 = 8'h80 >> { n4791, n4792, n4809 }; + assign n4832 = 32'd2147483648 >> { n4795, n4797, n4799, n4763, n4765 }; + assign n4833 = 32'd1452627285 >> { n4834, n4825_1, n4759, n4765, n4797 }; + assign n4834 = 64'h0000000280000000 >> { n4825_1, n4802_1, n4799, n4800, n4760, n4835 }; + assign n4835 = 64'h8000000000000008 >> { n4795, n4763, n4764, n4809, n4792, n4791 }; + assign n5829 = 32'd1920094322 >> { n4833, n4828, Ng2345, n4820_1, Pg6313 }; + assign n5824 = 32'd1920094322 >> { n4833, n4828, Ng2342, n4820_1, Pg5437 }; + assign n5744 = 64'h7557200277772222 >> { n4828, Ng2321, n4835, n4799, n4839, Ng853 }; + assign n4839 = 32'd2734620765 >> { n4824, Ng2180, n6673, n4823, n4821 }; + assign n5739 = 64'h7557200277772222 >> { n4828, Ng2318, n4835, n4799, n4839, Pg6313 }; + assign n5734 = 64'h7557200277772222 >> { n4828, Ng2315, n4835, n4799, n4839, Pg5437 }; + assign n5714 = 64'h5775022077772222 >> { n4828, Ng2312, n4844, n4795, n4843_1, Ng853 }; + assign n4843_1 = 32'd2734620765 >> { n4824, Ng2170, n6673, n4823, n4821 }; + assign n4844 = 8'h1b >> { n4831, n4825_1, n4764 }; + assign n5709 = 64'h5775022077772222 >> { n4828, Ng2309, n4844, n4795, n4843_1, Pg6313 }; + assign n5704 = 64'h5775022077772222 >> { n4828, Ng2306, n4844, n4795, n4843_1, Pg5437 }; + assign n5819 = 64'h7557200277772222 >> { n4828, Ng2303, n4849, n4765, n4848, Ng853 }; + assign n4848 = 32'd4210184400 >> { n4824, n6673, n4762_1, n4823, n4821 }; + assign n4849 = 8'h28 >> { n4825_1, n4759, n4834 }; + assign n5814 = 64'h7557200277772222 >> { n4828, Ng2300, n4849, n4765, n4848, Pg6313 }; + assign n5809 = 64'h7557200277772222 >> { n4828, Ng2297, n4849, n4765, n4848, Pg5437 }; + assign n5729 = 64'h7557200277772222 >> { n4828, Ng2276, n4854, n4763, n4853, Ng853 }; + assign n4853 = 32'd2734620765 >> { n4824, Ng2175, n6673, n4823, n4821 }; + assign n4854 = 8'h06 >> { n4844, n4825_1, n4795 }; + assign n5724 = 64'h7557200277772222 >> { n4828, Ng2273, n4854, n4763, n4853, Pg6313 }; + assign n5719 = 64'h7557200277772222 >> { n4828, Ng2270, n4854, n4763, n4853, Pg5437 }; + assign n4574 = 8'hd8 >> { Ng1698, n6716_1, Ng853 }; + assign n4858 = 64'ha2f3a2f3a2a2a2f3 >> { n4870_1, n4869, n4868, n4859, n4862, n4867 }; + assign n4859 = 16'h1428 >> { n4860, n4861, Ng1476, Ng1506 }; + assign n4860 = 64'h0000077707770777 >> { Pg6313, Ng1642, Ng853, Ng1645, Pg5437, Ng1639 }; + assign n4861 = 64'h0000077707770777 >> { Pg6313, Ng1615, Ng853, Ng1618, Pg5437, Ng1612 }; + assign n4862 = 64'h9ff9000000009ff9 >> { n4863, Ng1496, n4865_1, n4864, n4866, Ng1486 }; + assign n4863 = 64'h0000077707770777 >> { Pg6313, Ng1633, Ng853, Ng1636, Pg5437, Ng1630 }; + assign n4864 = 64'hdd0ddd0d0000dd0d >> { Ng1555, Pg6313, Ng1553, Ng853, Ng1554, Pg5437 }; + assign n4865_1 = 64'h0000077707770777 >> { Pg6313, Ng1651, Ng853, Ng1654, Pg5437, Ng1648 }; + assign n4866 = 64'h0000077707770777 >> { Pg6313, Ng1624, Ng853, Ng1627, Pg5437, Ng1621 }; + assign n4867 = 16'h1428 >> { n4861, n4866, Ng1486, Ng1476 }; + assign n4868 = 64'h0000ebd7ebd70000 >> { n4864, n4865_1, n4860, n4863, Ng1496, Ng1506 }; + assign n4869 = 64'hebd700000000ebd7 >> { n4861, Ng1476, n4863, n4866, Ng1486, Ng1496 }; + assign n4870_1 = 16'h4182 >> { n4860, n4864, n4865_1, Ng1506 }; + assign n4871 = 64'h1555555555555555 >> { n4877, n4880, n4867, n4872, n4873, n4882 }; + assign n4872 = 16'h1428 >> { n4860, n4863, Ng1496, Ng1506 }; + assign n4873 = 16'h4182 >> { n4874_1, n4875, n4876, Ng1481 }; + assign n4874_1 = 64'h0000077707770777 >> { Pg6313, Ng1579, Ng853, Ng1582, Pg5437, Ng1576 }; + assign n4875 = 64'hdd0ddd0d0000dd0d >> { Ng1558, Pg6313, Ng1556, Ng853, Ng1557, Pg5437 }; + assign n4876 = 64'h0000077707770777 >> { Pg6313, Ng1606, Ng853, Ng1609, Pg5437, Ng1603 }; + assign n4877 = 16'h1428 >> { n4878, n4879_1, Ng1501, Ng1491 }; + assign n4878 = 64'h0000077707770777 >> { Pg6313, Ng1588, Ng853, Ng1591, Pg5437, Ng1585 }; + assign n4879_1 = 64'h0000077707770777 >> { Pg6313, Ng1597, Ng853, Ng1600, Pg5437, Ng1594 }; + assign n4880 = 16'h6006 >> { n4864, n4865_1, n4881, Ng1471 }; + assign n4881 = 64'h0000077707770777 >> { Pg6313, Ng1570, Ng853, Ng1573, Pg5437, Ng1567 }; + assign n4882 = 64'hdd0ddd0d0000dd0d >> { Ng1552, Pg6313, Ng1550, Ng853, Ng1551, Pg5437 }; + assign n4883_1 = 4'h8 >> { n4884, Ng2257 }; + assign n4884 = 64'hdd0ddd0d0000dd0d >> { Ng1700, Pg6313, Ng1701, Ng853, Ng1699, Pg5437 }; + assign n4885 = 4'h2 >> { n4882, Ng2257 }; + assign n4886 = 64'he0eee0eee0eef0ff >> { n4890, n4889, n4891, n4877, n4888, n4887 }; + assign n4887 = 16'h1428 >> { n4879_1, n4881, Ng1471, Ng1501 }; + assign n4888 = 16'h1428 >> { n4874_1, n4878, Ng1491, Ng1481 }; + assign n4889 = 64'hbe7d00000000be7d >> { n4878, Ng1491, n4874_1, n4876, n4875, Ng1481 }; + assign n4890 = 64'h9ff9000000009ff9 >> { n4881, Ng1471, n4875, n4876, n4879_1, Ng1501 }; + assign n4891 = 64'h0000ebd7ebd70000 >> { n4875, n4876, n4874_1, n4881, Ng1471, Ng1481 }; + assign n4892_1 = 64'h0000000080000000 >> { n4908, n4896, n4899, n4902_1, n4904, n4893 }; + assign n4893 = 16'h1428 >> { n4894, n4895, Ng1506, Ng1486 }; + assign n4894 = 64'hdd0ddd0d0000dd0d >> { Ng1528, Pg6313, Ng1526, Ng853, Ng1527, Pg5437 }; + assign n4895 = 64'hdd0ddd0d0000dd0d >> { Ng1540, Pg6313, Ng1538, Ng853, Ng1539, Pg5437 }; + assign n4896 = 64'h0000002800280028 >> { n4898, Ng1471, n4882, n4897_1, Ng1481, Ng2257 }; + assign n4897_1 = 64'hdd0ddd0d0000dd0d >> { Ng1525, Pg6313, Ng1523, Ng853, Ng1524, Pg5437 }; + assign n4898 = 64'hdd0ddd0d0000dd0d >> { Ng1513, Pg6313, Ng1511, Ng853, Ng1512, Pg5437 }; + assign n4899 = 64'h6006600660060000 >> { n4898, Ng1471, n4875, n4900, n4901, Ng1496 }; + assign n4900 = 64'hdd0ddd0d0000dd0d >> { Ng1543, Pg6313, Ng1541, Ng853, Ng1542, Pg5437 }; + assign n4901 = 64'hdd0ddd0d0000dd0d >> { Ng1534, Pg6313, Ng1532, Ng853, Ng1533, Pg5437 }; + assign n4902_1 = 4'h6 >> { n4903, Ng1491 }; + assign n4903 = 64'hdd0ddd0d0000dd0d >> { Ng1531, Pg6313, Ng1529, Ng853, Ng1530, Pg5437 }; + assign n4904 = 64'h0660000000000660 >> { n4864, n4907_1, n4905, Ng1476, n4906, Ng1501 }; + assign n4905 = 64'hdd0ddd0d0000dd0d >> { Ng1516, Pg6313, Ng1514, Ng853, Ng1515, Pg5437 }; + assign n4906 = 64'hdd0ddd0d0000dd0d >> { Ng1537, Pg6313, Ng1535, Ng853, Ng1536, Pg5437 }; + assign n4907_1 = 64'hdd0ddd0d0000dd0d >> { Ng1546, Pg6313, Ng1544, Ng853, Ng1545, Pg5437 }; + assign n4908 = 64'hdd0ddd0d0000dd0d >> { Ng1704, Pg6313, Ng1702, Ng853, Ng1703, Pg5437 }; + assign n4909 = 4'h8 >> { n4882, Ng2257 }; + assign n4910 = 64'hdd0ddd0d0000dd0d >> { Ng1694, Pg6313, Ng1695, Ng853, Ng1693, Pg5437 }; + assign n4911 = 64'hdd0ddd0d0000dd0d >> { Ng1697, Pg6313, Ng1698, Ng853, Ng1696, Pg5437 }; + assign n4912_1 = 16'hdd0d >> { n4911, n4910, n4916_1, n6676_1 }; + assign n4913 = 64'h0660000000000660 >> { n4875, n4900, n4905, Ng1476, n4906, Ng1501 }; + assign n4914 = 64'h6660666066600000 >> { n4898, Ng1471, n4897_1, Ng1481, n4894, Ng1486 }; + assign n4915 = 64'h0000002800280028 >> { n4898, Ng1471, n4882, n4895, Ng1506, Ng2257 }; + assign n4916_1 = 64'hdd0ddd0d0000dd0d >> { Ng1785, Pg6313, Ng1783, Ng853, Ng1784, Pg5437 }; + assign n4569 = 8'hd8 >> { Ng1697, n6716_1, Pg6313 }; + assign n4564_1 = 8'hd8 >> { Ng1696, n6716_1, Pg5437 }; + assign n4344 = 16'h444e >> { n4929_1, n4920_1, Ng1654, Ng853 }; + assign n4920_1 = 32'd4210184400 >> { n4925, n4923, n4864, n4924, n4921 }; + assign n4921 = 16'hdd0d >> { n4910, n4909, n4916_1, n4922 }; + assign n4922 = 32'd2147483648 >> { n4893, n4896, n4899, n4902_1, n4904 }; + assign n4923 = 32'd3455053807 >> { n4858, n4886, n4911, n4910, n4884 }; + assign n4924 = 4'h8 >> { n4892_1, n4911 }; + assign n4925 = 32'd8 >> { n4861, n4865_1, n4876, n4928, n4926 }; + assign n4926 = 8'h02 >> { n4866, n4874_1, n4927 }; + assign n4927 = 8'h08 >> { n4911, n4910, n4884 }; + assign n4928 = 32'd2147483648 >> { n4860, n4863, n4878, n4879_1, n4881 }; + assign n4929_1 = 16'h2022 >> { n4924, n4923, n4933, n4921 }; + assign n4930 = 64'h7777777777777757 >> { n4876, n4861, n4865_1, n4926, n4931, n4928 }; + assign n4931 = 64'h8000000000000000 >> { n4932, n4861, n4865_1, n4866, n4874_1, n4876 }; + assign n4932 = 8'h80 >> { n4884, n4910, n4911 }; + assign n4933 = 32'd1452627285 >> { n4934_1, n4927, n4876, n4879_1, n4865_1 }; + assign n4934_1 = 64'h0000000000028000 >> { n4936, n4927, n4860, n4863, n4878, n4935 }; + assign n4935 = 32'd2147483656 >> { n4861, n4881, n4911, n4910, n4884 }; + assign n4936 = 8'h7e >> { n4911, n4874_1, n4866 }; + assign n4339 = 16'h444e >> { n4929_1, n4920_1, Ng1651, Pg6313 }; + assign n4334 = 16'h444e >> { n4929_1, n4920_1, Ng1648, Pg5437 }; + assign n4254 = 16'h444e >> { n4941, n4940, Ng1627, Ng853 }; + assign n4940 = 32'd2734620765 >> { n4925, Ng1486, n4923, n4924, n4921 }; + assign n4941 = 16'h2022 >> { n4924, n4923, n4942, n4921 }; + assign n4942 = 16'h6955 >> { n4935, n4927, n4874_1, n4866 }; + assign n4249 = 16'h444e >> { n4941, n4940, Ng1624, Pg6313 }; + assign n4244 = 16'h444e >> { n4941, n4940, Ng1621, Pg5437 }; + assign n4224 = 16'h444e >> { n4947, n4946, Ng1618, Ng853 }; + assign n4946 = 32'd2734620765 >> { n4925, Ng1476, n4923, n4924, n4921 }; + assign n4947 = 16'h2022 >> { n4924, n4923, n4948, n4921 }; + assign n4948 = 16'hc693 >> { n4927, n4932, n4861, n4881 }; + assign n4219 = 16'h444e >> { n4947, n4946, Ng1615, Pg6313 }; + assign n4214 = 16'h444e >> { n4947, n4946, Ng1612, Pg5437 }; + assign n4329 = 16'h444e >> { n4953, n4952, Ng1609, Ng853 }; + assign n4952 = 32'd4210184400 >> { n4925, n4923, n4875, n4924, n4921 }; + assign n4953 = 16'h2022 >> { n4924, n4923, n4954_1, n4921 }; + assign n4954_1 = 16'h6955 >> { n4934_1, n4927, n4879_1, n4876 }; + assign n4324 = 16'h444e >> { n4953, n4952, Ng1606, Pg6313 }; + assign n4319 = 16'h444e >> { n4953, n4952, Ng1603, Pg5437 }; + assign n4239 = 16'h444e >> { n4959, n4958, Ng1582, Ng853 }; + assign n4958 = 32'd2734620765 >> { n4925, Ng1481, n4923, n4924, n4921 }; + assign n4959 = 32'd142616736 >> { n4924, n4935, n4874_1, n4923, n4921 }; + assign n4234 = 16'h444e >> { n4959, n4958, Ng1579, Pg6313 }; + assign n4229 = 16'h444e >> { n4959, n4958, Ng1576, Pg5437 }; + assign n3073 = 8'hd8 >> { Ng1004, n6678, Ng853 }; + assign n4963 = 64'hb0bbb0bba0aab0bb >> { n4972, n4973, n4975, n4974_1, n4967, n4964 }; + assign n4964 = 16'h1428 >> { n4965, n4966_1, Ng813, Ng789 }; + assign n4965 = 64'h0000077707770777 >> { Pg6313, Ng921, Ng853, Ng924, Pg5437, Ng918 }; + assign n4966_1 = 64'h0000077707770777 >> { Pg6313, Ng948, Ng853, Ng951, Pg5437, Ng945 }; + assign n4967 = 64'h9ff9000000009ff9 >> { n4971, Ng805, n4968, n4969, n4970_1, Ng797 }; + assign n4968 = 64'hdd0ddd0d0000dd0d >> { Ng861, Pg6313, Ng859, Ng853, Ng860, Pg5437 }; + assign n4969 = 64'h0000077707770777 >> { Pg6313, Ng957, Ng853, Ng960, Pg5437, Ng954 }; + assign n4970_1 = 64'h0000077707770777 >> { Pg6313, Ng930, Ng853, Ng933, Pg5437, Ng927 }; + assign n4971 = 64'h0000077707770777 >> { Pg6313, Ng939, Ng853, Ng942, Pg5437, Ng936 }; + assign n4972 = 16'h1428 >> { n4970_1, n4971, Ng805, Ng797 }; + assign n4973 = 64'hbe7d00000000be7d >> { n4965, Ng789, n4966_1, n4969, n4968, Ng813 }; + assign n4974_1 = 16'h1428 >> { n4966_1, n4971, Ng805, Ng813 }; + assign n4975 = 64'h0000ebd7ebd70000 >> { n4968, n4969, n4965, n4970_1, Ng797, Ng789 }; + assign n4976 = 64'h1555555555555555 >> { n4979_1, n4982, n4964, n4972, n4977, n4986 }; + assign n4977 = 16'h6006 >> { n4968, n4969, n4978, Ng801 }; + assign n4978 = 64'h0000077707770777 >> { Pg6313, Ng894, Ng853, Ng897, Pg5437, Ng891 }; + assign n4979_1 = 16'h1428 >> { n4980, n4981, Ng809, Ng785 }; + assign n4980 = 64'h0000077707770777 >> { Pg6313, Ng876, Ng853, Ng879, Pg5437, Ng873 }; + assign n4981 = 64'h0000077707770777 >> { Ng903, Pg6313, Ng853, Ng906, Pg5437, Ng900 }; + assign n4982 = 16'h4182 >> { n4983, n4984, n4985, Ng793 }; + assign n4983 = 64'h0000077707770777 >> { Pg6313, Ng885, Ng853, Ng888, Pg5437, Ng882 }; + assign n4984 = 64'hdd0ddd0d0000dd0d >> { Ng864, Pg6313, Ng862, Ng853, Ng863, Pg5437 }; + assign n4985 = 64'h0000077707770777 >> { Pg6313, Ng912, Ng853, Ng915, Pg5437, Ng909 }; + assign n4986 = 64'hdd0ddd0d0000dd0d >> { Ng858, Pg6313, Ng856, Ng853, Ng857, Pg5437 }; + assign n4987 = 4'h8 >> { n4988, Ng2257 }; + assign n4988 = 64'hdd0ddd0d0000dd0d >> { Ng1006, Pg6313, Ng1007, Ng853, Ng1005, Pg5437 }; + assign n4989 = 64'heefeeeeeeefeaeee >> { n4990, n4986, n4988, Ng2257, n6681_1, n5009 }; + assign n4990 = 64'ha2f3a2f3a2a2a2f3 >> { n4982, n4994, n4995, n4991, n4992, n4993 }; + assign n4991 = 16'h1428 >> { n4978, n4983, Ng793, Ng801 }; + assign n4992 = 64'hbe7d00000000be7d >> { n4980, Ng785, n4981, n4985, n4984, Ng809 }; + assign n4993 = 16'h1428 >> { n4978, n4981, Ng809, Ng801 }; + assign n4994 = 64'hebd700000000ebd7 >> { n4978, Ng801, n4980, n4981, Ng809, Ng785 }; + assign n4995 = 64'h0000ebd7ebd70000 >> { n4984, n4985, n4980, n4983, Ng793, Ng785 }; + assign n4996 = 64'h0000066006600000 >> { n4997_1, Ng789, n4998, Ng793, n4999, Ng809 }; + assign n4997_1 = 64'hdd0ddd0d0000dd0d >> { Ng822, Pg6313, Ng820, Ng853, Ng821, Pg5437 }; + assign n4998 = 64'hdd0ddd0d0000dd0d >> { Ng831, Pg6313, Ng829, Ng853, Ng830, Pg5437 }; + assign n4999 = 64'hdd0ddd0d0000dd0d >> { Ng843, Pg6313, Ng841, Ng853, Ng842, Pg5437 }; + assign n5000 = 16'h6006 >> { n4984, n5002_1, n5001, Ng785 }; + assign n5001 = 64'hdd0ddd0d0000dd0d >> { Ng819, Pg6313, Ng817, Ng853, Ng818, Pg5437 }; + assign n5002_1 = 64'hdd0ddd0d0000dd0d >> { Ng849, Pg6313, Ng847, Ng853, Ng848, Pg5437 }; + assign n5003 = 64'hdd0ddd0d0000dd0d >> { Ng837, Pg6313, Ng835, Ng853, Ng836, Pg5437 }; + assign n5004 = 64'hdd0ddd0d0000dd0d >> { Ng852, Pg6313, Ng850, Ng853, Ng851, Pg5437 }; + assign n5005 = 64'hdd0ddd0d0000dd0d >> { Ng846, Pg6313, Ng844, Ng853, Ng845, Pg5437 }; + assign n5006_1 = 64'hdd0ddd0d0000dd0d >> { Ng840, Pg6313, Ng838, Ng853, Ng839, Pg5437 }; + assign n5007 = 64'hdd0ddd0d0000dd0d >> { Ng834, Pg6313, Ng832, Ng853, Ng833, Pg5437 }; + assign n5008 = 64'hdd0ddd0d0000dd0d >> { Ng1010, Pg6313, Ng1008, Ng853, Ng1009, Pg5437 }; + assign n5009 = 64'hdd0ddd0d0000dd0d >> { Ng1000, Pg6313, Ng1001, Ng853, Ng999, Pg5437 }; + assign n5010 = 4'h2 >> { n4986, Ng2257 }; + assign n5011_1 = 64'hdd0ddd0d0000dd0d >> { Ng1003, Pg6313, Ng1004, Ng853, Ng1002, Pg5437 }; + assign n5012 = 64'h0000000080000000 >> { n5016_1, n5000, n5013, n5014, n5015, n4996 }; + assign n5013 = 64'h0000002800280028 >> { n5003, Ng801, n4986, n5005, Ng813, Ng2257 }; + assign n5014 = 16'h6660 >> { n5007, Ng797, n5006_1, Ng805 }; + assign n5015 = 64'h0000999099909990 >> { n5007, Ng797, n5003, Ng801, n4968, n5004 }; + assign n5016_1 = 64'hdd0ddd0d0000dd0d >> { Ng1091, Pg6313, Ng1089, Ng853, Ng1090, Pg5437 }; + assign n3068 = 8'hd8 >> { Ng1003, n6678, Pg6313 }; + assign n3063 = 8'hd8 >> { Ng1002, n6678, Pg5437 }; + assign n2843 = 16'h444e >> { n5028, n5020, Ng960, Ng853 }; + assign n5020 = 32'd4210184400 >> { n5024, n5022, n4968, n5023, n5021_1 }; + assign n5021_1 = 16'h5515 >> { n5009, n4986, Ng2257, n5012 }; + assign n5022 = 32'd3455053807 >> { n4963, n4990, n5011_1, n5009, n4988 }; + assign n5023 = 4'h8 >> { n6681_1, n5011_1 }; + assign n5024 = 32'd8 >> { n4965, n4969, n4985, n5027, n5025 }; + assign n5025 = 8'h02 >> { n4970_1, n4983, n5026_1 }; + assign n5026_1 = 8'h08 >> { n5011_1, n5009, n4988 }; + assign n5027 = 32'd2147483648 >> { n4966_1, n4971, n4978, n4980, n4981 }; + assign n5028 = 16'h2022 >> { n5023, n5022, n5032, n5021_1 }; + assign n5029 = 64'h7777777777777757 >> { n4985, n4965, n4969, n5025, n5030, n5027 }; + assign n5030 = 64'h8000000000000000 >> { n5031_1, n4965, n4969, n4970_1, n4983, n4985 }; + assign n5031_1 = 8'h80 >> { n4988, n5009, n5011_1 }; + assign n5032 = 32'd1452627285 >> { n5033, n5026_1, n4981, n4985, n4969 }; + assign n5033 = 64'h0000000000028000 >> { n5035, n5026_1, n4966_1, n4971, n4978, n5034 }; + assign n5034 = 32'd2147483656 >> { n4965, n4980, n5011_1, n5009, n4988 }; + assign n5035 = 8'h7e >> { n5011_1, n4983, n4970_1 }; + assign n2838 = 16'h444e >> { n5028, n5020, Ng957, Pg6313 }; + assign n2833 = 16'h444e >> { n5028, n5020, Ng954, Pg5437 }; + assign n2753 = 16'h444e >> { n5040, n5039, Ng933, Ng853 }; + assign n5039 = 32'd2734620765 >> { n5024, Ng797, n5022, n5023, n5021_1 }; + assign n5040 = 16'h2022 >> { n5023, n5022, n5041_1, n5021_1 }; + assign n5041_1 = 16'h6955 >> { n5034, n5026_1, n4983, n4970_1 }; + assign n2748 = 16'h444e >> { n5040, n5039, Ng930, Pg6313 }; + assign n2743 = 16'h444e >> { n5040, n5039, Ng927, Pg5437 }; + assign n2723 = 16'h444e >> { n5046_1, n5045, Ng924, Ng853 }; + assign n5045 = 32'd2734620765 >> { n5024, Ng789, n5022, n5023, n5021_1 }; + assign n5046_1 = 16'h2022 >> { n5023, n5022, n5047, n5021_1 }; + assign n5047 = 16'hc693 >> { n5026_1, n5031_1, n4965, n4980 }; + assign n2718 = 16'h444e >> { n5046_1, n5045, Ng921, Pg6313 }; + assign n2713 = 16'h444e >> { n5046_1, n5045, Ng918, Pg5437 }; + assign n2828 = 16'h444e >> { n5052, n5051_1, Ng915, Ng853 }; + assign n5051_1 = 32'd4210184400 >> { n5024, n5022, n4984, n5023, n5021_1 }; + assign n5052 = 16'h2022 >> { n5023, n5022, n5053, n5021_1 }; + assign n5053 = 16'h6955 >> { n5033, n5026_1, n4981, n4985 }; + assign n2823 = 16'h444e >> { n5052, n5051_1, Ng912, Pg6313 }; + assign n2818 = 16'h444e >> { n5052, n5051_1, Ng909, Pg5437 }; + assign n2738 = 16'h444e >> { n5058, n5057, Ng888, Ng853 }; + assign n5057 = 32'd2734620765 >> { n5024, Ng793, n5022, n5023, n5021_1 }; + assign n5058 = 32'd545270408 >> { n5023, n5034, n5022, n4983, n5021_1 }; + assign n2733 = 16'h444e >> { n5058, n5057, Ng885, Pg6313 }; + assign n2728 = 16'h444e >> { n5058, n5057, Ng882, Pg5437 }; + assign n1573 = 8'hd8 >> { Ng317, n6683, Ng853 }; + assign n5062 = 64'he0eee0eee0eef0ff >> { n5068, n5063, n5074, n5073, n5071_1, n5072 }; + assign n5063 = 64'hbe7d00000000be7d >> { n5067, Ng117, n5064, n5066_1, n5065, Ng109 }; + assign n5064 = 64'h0000077707770777 >> { Pg6313, Ng243, Ng853, Ng246, Pg5437, Ng240 }; + assign n5065 = 64'hdd0ddd0d0000dd0d >> { Ng173, Pg6313, Ng171, Ng853, Ng172, Pg5437 }; + assign n5066_1 = 64'h0000077707770777 >> { Pg6313, Ng270, Ng853, Ng273, Pg5437, Ng267 }; + assign n5067 = 64'h0000077707770777 >> { Pg6313, Ng252, Ng853, Ng255, Pg5437, Ng249 }; + assign n5068 = 64'h9ff9000000009ff9 >> { n5069, Ng101, n5065, n5066_1, n5070, Ng125 }; + assign n5069 = 64'h0000077707770777 >> { Pg6313, Ng234, Ng853, Ng237, Pg5437, Ng231 }; + assign n5070 = 64'h0000077707770777 >> { Pg6313, Ng261, Ng853, Ng264, Pg5437, Ng258 }; + assign n5071_1 = 16'h1428 >> { n5069, n5070, Ng125, Ng101 }; + assign n5072 = 16'h1428 >> { n5064, n5067, Ng117, Ng109 }; + assign n5073 = 16'h1428 >> { n5064, n5069, Ng101, Ng109 }; + assign n5074 = 64'h0000ebd7ebd70000 >> { n5065, n5066_1, n5067, n5070, Ng125, Ng117 }; + assign n5075 = 64'h1555555555555555 >> { n5081_1, n5084, n5076_1, n5072, n5077, n5086_1 }; + assign n5076_1 = 16'h6006 >> { n5065, n5066_1, n5070, Ng125 }; + assign n5077 = 16'h6006 >> { n5078, n5079, n5080, Ng121 }; + assign n5078 = 64'hdd0ddd0d0000dd0d >> { Ng176, Pg6313, Ng174, Ng853, Ng175, Pg5437 }; + assign n5079 = 64'h0000077707770777 >> { Ng225, Pg6313, Ng853, Ng228, Pg5437, Ng222 }; + assign n5080 = 64'h0000077707770777 >> { Pg6313, Ng216, Ng219, Ng853, Pg5437, Ng213 }; + assign n5081_1 = 16'h1428 >> { n5082, n5083, Ng113, Ng105 }; + assign n5082 = 64'h0000077707770777 >> { Pg6313, Ng198, Ng853, Ng201, Pg5437, Ng195 }; + assign n5083 = 64'h0000077707770777 >> { Pg6313, Ng207, Ng853, Ng210, Pg5437, Ng204 }; + assign n5084 = 16'h1428 >> { n5069, n5085, Ng97, Ng101 }; + assign n5085 = 64'h0000077707770777 >> { Pg6313, Ng189, Ng853, Ng192, Pg5437, Ng186 }; + assign n5086_1 = 64'hdd0ddd0d0000dd0d >> { Ng170, Pg6313, Ng168, Ng853, Ng169, Pg5437 }; + assign n5087 = 4'h8 >> { n5088, Ng2257 }; + assign n5088 = 64'hdd0ddd0d0000dd0d >> { Ng319, Pg6313, Ng320, Ng853, Ng318, Pg5437 }; + assign n5089 = 64'hffff08a8ffff00a8 >> { n5106_1, n5112, n5088, n5086_1, n5125, Ng2257 }; + assign n5090 = 64'h0660000000000660 >> { n5065, n5092, n5091_1, Ng97, n5093, Ng125 }; + assign n5091_1 = 64'hdd0ddd0d0000dd0d >> { Ng131, Pg6313, Ng129, Ng853, Ng130, Pg5437 }; + assign n5092 = 64'hdd0ddd0d0000dd0d >> { Ng164, Pg6313, Ng162, Ng853, Ng163, Pg5437 }; + assign n5093 = 64'hdd0ddd0d0000dd0d >> { Ng158, Pg6313, Ng156, Ng853, Ng157, Pg5437 }; + assign n5094 = 16'h1428 >> { n5095, n5096_1, Ng105, Ng101 }; + assign n5095 = 64'hdd0ddd0d0000dd0d >> { Ng134, Pg6313, Ng132, Ng853, Ng133, Pg5437 }; + assign n5096_1 = 64'hdd0ddd0d0000dd0d >> { Ng143, Pg6313, Ng141, Ng853, Ng142, Pg5437 }; + assign n5097 = 64'h0000002800280028 >> { n5099, Ng117, n5086_1, n5098, Ng121, Ng2257 }; + assign n5098 = 64'hdd0ddd0d0000dd0d >> { Ng155, Pg6313, Ng153, Ng853, Ng154, Pg5437 }; + assign n5099 = 64'hdd0ddd0d0000dd0d >> { Ng152, Pg6313, Ng150, Ng853, Ng151, Pg5437 }; + assign n5100 = 16'h0999 >> { n5102, Ng113, n5078, n5101_1 }; + assign n5101_1 = 64'hdd0ddd0d0000dd0d >> { Ng161, Pg6313, Ng159, Ng853, Ng160, Pg5437 }; + assign n5102 = 64'hdd0ddd0d0000dd0d >> { Ng149, Pg6313, Ng147, Ng853, Ng148, Pg5437 }; + assign n5103 = 64'h6660666066600000 >> { Ng113, n5102, n5099, Ng117, n5104, Ng109 }; + assign n5104 = 64'hdd0ddd0d0000dd0d >> { Ng146, Pg6313, Ng144, Ng853, Ng145, Pg5437 }; + assign n5105 = 64'hdd0ddd0d0000dd0d >> { Ng323, Pg6313, Ng321, Ng853, Ng322, Pg5437 }; + assign n5106_1 = 64'hdd0ddd0d0000dd0d >> { n5110, n5111_1, n5107, n5108, n5077, n5109 }; + assign n5107 = 16'h1428 >> { n5080, n5083, Ng113, Ng121 }; + assign n5108 = 64'h0000ebd7ebd70000 >> { n5078, n5079, n5085, n5082, Ng105, Ng97 }; + assign n5109 = 64'hebd700000000ebd7 >> { n5085, Ng97, n5082, n5083, Ng113, Ng105 }; + assign n5110 = 16'h6006 >> { n5078, n5079, n5082, Ng105 }; + assign n5111_1 = 64'hebd700000000ebd7 >> { n5083, Ng113, n5080, n5085, Ng97, Ng121 }; + assign n5112 = 64'hdd0ddd0d0000dd0d >> { Ng313, Pg6313, Ng314, Ng853, Ng312, Pg5437 }; + assign n5113 = 4'h2 >> { n5086_1, Ng2257 }; + assign n5114 = 64'hdd0ddd0d0000dd0d >> { Ng316, Pg6313, Ng317, Ng853, Ng315, Pg5437 }; + assign n5115 = 64'h0000000080000000 >> { n5116_1, n5094, n5097, n5100, n5103, n5090 }; + assign n5116_1 = 64'hdd0ddd0d0000dd0d >> { Ng404, Pg6313, Ng402, Ng853, Ng403, Pg5437 }; + assign n5117 = 4'h2 >> { n5088, n5112 }; + assign n1568 = 8'hd8 >> { Ng316, n6683, Pg6313 }; + assign n1563 = 8'hd8 >> { Ng315, n6683, Pg5437 }; + assign n1343 = 32'd1920094322 >> { n5139, n5134, Ng273, n5121_1, Ng853 }; + assign n5121_1 = 32'd4210184400 >> { n5130, n5123, n5065, n5124, n5122 }; + assign n5122 = 16'h5515 >> { n5112, n5086_1, Ng2257, n5115 }; + assign n5123 = 32'd3455053807 >> { n5062, n5106_1, n5114, n5112, n5088 }; + assign n5124 = 4'h8 >> { n5125, n5114 }; + assign n5125 = 64'h0000000080000000 >> { n5105, n5127, n5128, n5129, n5126_1, n5103 }; + assign n5126_1 = 64'h0000002800280028 >> { n5093, Ng125, n5086_1, n5096_1, Ng105, Ng2257 }; + assign n5127 = 64'h0000999099909990 >> { n5099, Ng117, n5093, Ng125, n5078, n5101_1 }; + assign n5128 = 64'h0660000000000660 >> { n5065, n5092, n5091_1, Ng97, n5098, Ng121 }; + assign n5129 = 16'h1428 >> { n5095, n5102, Ng113, Ng101 }; + assign n5130 = 32'd128 >> { n5069, n5082, n5133, n5131_1, n5132 }; + assign n5131_1 = 8'h08 >> { n5114, n5112, n5088 }; + assign n5132 = 32'd2147483648 >> { n5067, n5070, n5080, n5085, n5083 }; + assign n5133 = 8'h01 >> { n5064, n5066_1, n5079 }; + assign n5134 = 8'h8a >> { n5124, n5123, n5122 }; + assign n5135 = 4'h1 >> { n5130, n5136_1 }; + assign n5136_1 = 8'h80 >> { n5132, n5137, n5138 }; + assign n5137 = 8'h80 >> { n5088, n5112, n5114 }; + assign n5138 = 32'd2147483648 >> { n5064, n5066_1, n5069, n5079, n5082 }; + assign n5139 = 32'd1452627285 >> { n5140, n5131_1, n5079, n5080, n5066_1 }; + assign n5140 = 32'd163840 >> { n5131_1, n5067, n5070, n5083, n5141_1 }; + assign n5141_1 = 8'h28 >> { n5131_1, n5064, n5142 }; + assign n5142 = 64'h8000000000000008 >> { n5069, n5085, n5082, n5114, n5112, n5088 }; + assign n1338 = 32'd1920094322 >> { n5139, n5134, Ng270, n5121_1, Pg6313 }; + assign n1333 = 32'd1920094322 >> { n5139, n5134, Ng267, n5121_1, Pg5437 }; + assign n1253 = 64'h7557200277772222 >> { n5134, Ng246, n5142, n5064, n5146, Ng853 }; + assign n5146 = 32'd2734620765 >> { n5130, Ng109, n5123, n5124, n5122 }; + assign n1248 = 64'h7557200277772222 >> { n5134, Ng243, n5142, n5064, n5146, Pg6313 }; + assign n1243 = 64'h7557200277772222 >> { n5134, Ng240, n5142, n5064, n5146, Pg5437 }; + assign n1223 = 64'h5775022077772222 >> { n5134, Ng237, n5151, n5069, n5150, Ng853 }; + assign n5150 = 32'd2734620765 >> { n5130, Ng101, n5123, n5124, n5122 }; + assign n5151 = 8'h1b >> { n5137, n5131_1, n5085 }; + assign n1218 = 64'h5775022077772222 >> { n5134, Ng234, n5151, n5069, n5150, Pg6313 }; + assign n1213 = 64'h5775022077772222 >> { n5134, Ng231, n5151, n5069, n5150, Pg5437 }; + assign n1328 = 64'h7557200277772222 >> { n5134, Ng228, n5156, n5079, n5155, Ng853 }; + assign n5155 = 32'd4210184400 >> { n5130, n5123, n5078, n5124, n5122 }; + assign n5156 = 8'h28 >> { n5131_1, n5080, n5140 }; + assign n1323 = 64'h7557200277772222 >> { n5134, Ng225, n5156, n5079, n5155, Pg6313 }; + assign n1318_1 = 64'h7557200277772222 >> { n5134, Ng222, n5156, n5079, n5155, Pg5437 }; + assign n1238 = 64'h7557200277772222 >> { n5134, Ng201, n5161, n5082, n5160, Ng853 }; + assign n5160 = 32'd2734620765 >> { n5130, Ng105, n5123, n5124, n5122 }; + assign n5161 = 8'h06 >> { n5151, n5131_1, n5069 }; + assign n1233 = 64'h7557200277772222 >> { n5134, Ng198, n5161, n5082, n5160, Pg6313 }; + assign n1228 = 64'h7557200277772222 >> { n5134, Ng195, n5161, n5082, n5160, Pg5437 }; + assign n6091 = 8'hd8 >> { Ng2395, n6685, Ng853 }; + assign n6086 = 8'hd8 >> { Ng2394, n6685, Pg6313 }; + assign n6081 = 8'hd8 >> { Ng2393, n6685, Pg5437 }; + assign n4589 = 8'hd8 >> { Ng1701, n5168, Ng853 }; + assign n5168 = 64'h00a900a9000000a9 >> { n4916_1, n6676_1, n4910, n5169_1, n5170, n4884 }; + assign n5169_1 = 32'd176851594 >> { n4886, n4858, n4883_1, n4885, n4911 }; + assign n5170 = 16'h1f9f >> { n4911, Ng2257, n4884, n4871 }; + assign n4584 = 8'hd8 >> { Ng1700, n5168, Pg6313 }; + assign n4579 = 8'hd8 >> { Ng1699, n5168, Pg5437 }; + assign n3088 = 8'hd8 >> { Ng1007, n6687, Ng853 }; + assign n3083 = 8'hd8 >> { Ng1006, n6687, Pg6313 }; + assign n3078 = 8'hd8 >> { Ng1005, n6687, Pg5437 }; + assign n1588 = 64'h55750020557d0028 >> { n5112, Ng320, n5177, n5180, n5088, Ng853 }; + assign n5177 = 4'h2 >> { n5116_1, n6689 }; + assign n5178 = 32'd35653760 >> { n5102, n5104, Ng109, Ng113, n5113 }; + assign n5179_1 = 64'h6006000000006006 >> { n5065, n5092, n5078, n5101_1, n5091_1, Ng97 }; + assign n5180 = 64'h1010101010103210 >> { n5182, n5181, n5087, n5183, n5112, n5114 }; + assign n5181 = 4'h2 >> { n5106_1, n5113 }; + assign n5182 = 4'h2 >> { n5062, n5113 }; + assign n5183 = 8'h28 >> { n5075, n5088, Ng2257 }; + assign n1583 = 64'h55750020557d0028 >> { n5112, Ng319, n5177, n5180, n5088, Pg6313 }; + assign n1578_1 = 64'h55750020557d0028 >> { n5112, Ng318, n5177, n5180, n5088, Pg5437 }; + assign n5804 = 8'h72 >> { Ng2339, n5187, Ng853 }; + assign n5187 = 64'ha2a200a2f7f7fff7 >> { Ng2200, n6673, n4823, n5188, n4829, n4821 }; + assign n5188 = 4'h6 >> { n5189_1, n4802_1 }; + assign n5189_1 = 64'h0000000280000000 >> { n4825_1, n4799, n4800, n4759, n4760, n4835 }; + assign n5799 = 8'h72 >> { Ng2336, n5187, Pg6313 }; + assign n5794 = 8'h72 >> { Ng2333, n5187, Pg5437 }; + assign n5774 = 8'h72 >> { Ng2330, n5193, Ng853 }; + assign n5193 = 64'ha2a200a2f7f7fff7 >> { Ng2190, n6673, n4823, n5194_1, n4829, n4821 }; + assign n5194_1 = 32'd2842340010 >> { n4835, n4825_1, n4799, n4760, n4800 }; + assign n5769 = 8'h72 >> { Ng2327, n5193, Pg6313 }; + assign n5764 = 8'h72 >> { Ng2324, n5193, Pg5437 }; + assign n5789 = 8'h72 >> { Ng2294, n5198, Ng853 }; + assign n5198 = 64'ha2a200a2f7f7fff7 >> { Ng2195, n6673, n4823, n5199_1, n4829, n4821 }; + assign n5199_1 = 64'haaa96aaaaaaaaaaa >> { n4835, n4825_1, n4799, n4800, n4760, n4759 }; + assign n5784 = 8'h72 >> { Ng2291, n5198, Pg6313 }; + assign n5779 = 8'h72 >> { Ng2288, n5198, Pg5437 }; + assign n5759 = 8'h72 >> { Ng2285, n5203, Ng853 }; + assign n5203 = 64'h2a2a002a7f7fff7f >> { Ng2185, n6673, n4823, n4829, n5204_1, n4821 }; + assign n5204_1 = 16'h6955 >> { n4835, n4825_1, n4799, n4760 }; + assign n5754 = 8'h72 >> { Ng2282, n5203, Pg6313 }; + assign n5749 = 8'h72 >> { Ng2279, n5203, Pg5437 }; + assign n5699 = 8'h72 >> { Ng2267, n5208, Ng853 }; + assign n5208 = 64'ha2a200a2f7f7fff7 >> { Ng2165, n6673, n4823, n5209_1, n4829, n4821 }; + assign n5209_1 = 8'h6a >> { n4791, n4792, n4764 }; + assign n5694 = 8'h72 >> { Ng2264, n5208, Pg6313 }; + assign n5689 = 8'h72 >> { Ng2261, n5208, Pg5437 }; + assign n4314 = 8'h72 >> { Ng1645, n5213, Ng853 }; + assign n5213 = 64'ha2a200a2f7f7fff7 >> { Ng1506, n4923, n4924, n5214_1, n4930, n4921 }; + assign n5214_1 = 16'h96aa >> { n5215, n4927, n4879_1, n4860 }; + assign n5215 = 32'd640 >> { n4936, n4927, n4863, n4878, n4935 }; + assign n4309 = 8'h72 >> { Ng1642, n5213, Pg6313 }; + assign n4304 = 8'h72 >> { Ng1639, n5213, Pg5437 }; + assign n4284 = 8'h72 >> { Ng1636, n5219_1, Ng853 }; + assign n5219_1 = 64'ha2a200a2f7f7fff7 >> { Ng1496, n4923, n4924, n5220, n4930, n4921 }; + assign n5220 = 32'd2863306410 >> { n4936, n4935, n4927, n4878, n4863 }; + assign n4279 = 8'h72 >> { Ng1633, n5219_1, Pg6313 }; + assign n4274 = 8'h72 >> { Ng1630, n5219_1, Pg5437 }; + assign n4299 = 8'h72 >> { Ng1600, n5224_1, Ng853 }; + assign n5224_1 = 64'ha2a200a2f7f7fff7 >> { Ng1501, n4923, n4924, n5225, n4930, n4921 }; + assign n5225 = 4'h6 >> { n5215, n4879_1 }; + assign n4294 = 8'h72 >> { Ng1597, n5224_1, Pg6313 }; + assign n4289 = 8'h72 >> { Ng1594, n5224_1, Pg5437 }; + assign n4269 = 8'h72 >> { Ng1591, n5229_1, Ng853 }; + assign n5229_1 = 64'h2a2a002a7f7fff7f >> { Ng1491, n4923, n4924, n4930, n5230, n4921 }; + assign n5230 = 8'h59 >> { n4936, n4935, n4878 }; + assign n4264 = 8'h72 >> { Ng1588, n5229_1, Pg6313 }; + assign n4259 = 8'h72 >> { Ng1585, n5229_1, Pg5437 }; + assign n4209 = 8'h72 >> { Ng1573, n5234_1, Ng853 }; + assign n5234_1 = 64'ha2a200a2f7f7fff7 >> { Ng1471, n4923, n4924, n5235, n4930, n4921 }; + assign n5235 = 8'h6a >> { n4884, n4910, n4881 }; + assign n4204 = 8'h72 >> { Ng1570, n5234_1, Pg6313 }; + assign n4199 = 8'h72 >> { Ng1567, n5234_1, Pg5437 }; + assign n2813 = 8'h72 >> { Ng951, n5239_1, Ng853 }; + assign n5239_1 = 64'ha2a200a2f7f7fff7 >> { Ng813, n5022, n5023, n5240, n5029, n5021_1 }; + assign n5240 = 16'h96aa >> { n5241, n5026_1, n4981, n4966_1 }; + assign n5241 = 32'd640 >> { n5035, n5026_1, n4971, n4978, n5034 }; + assign n2808 = 8'h72 >> { Ng948, n5239_1, Pg6313 }; + assign n2803 = 8'h72 >> { Ng945, n5239_1, Pg5437 }; + assign n2783 = 8'h72 >> { Ng942, n5245, Ng853 }; + assign n5245 = 64'ha2a200a2f7f7fff7 >> { Ng805, n5022, n5023, n5246, n5029, n5021_1 }; + assign n5246 = 32'd2863306410 >> { n5035, n5034, n5026_1, n4978, n4971 }; + assign n2778 = 8'h72 >> { Ng939, n5245, Pg6313 }; + assign n2773 = 8'h72 >> { Ng936, n5245, Pg5437 }; + assign n2798 = 8'h72 >> { Ng906, n5250, Ng853 }; + assign n5250 = 64'ha2a200a2f7f7fff7 >> { Ng809, n5022, n5023, n5251, n5029, n5021_1 }; + assign n5251 = 4'h6 >> { n5241, n4981 }; + assign n2793 = 8'h72 >> { Ng903, n5250, Pg6313 }; + assign n2788 = 8'h72 >> { Ng900, n5250, Pg5437 }; + assign n2768 = 8'h72 >> { Ng897, n5255, Ng853 }; + assign n5255 = 64'h2a2a002a7f7fff7f >> { Ng801, n5022, n5023, n5029, n5256, n5021_1 }; + assign n5256 = 8'h59 >> { n5035, n5034, n4978 }; + assign n2763 = 8'h72 >> { Ng894, n5255, Pg6313 }; + assign n2758 = 8'h72 >> { Ng891, n5255, Pg5437 }; + assign n2708 = 8'h72 >> { Ng879, n5260, Ng853 }; + assign n5260 = 64'ha2a200a2f7f7fff7 >> { Ng785, n5022, n5023, n5261, n5029, n5021_1 }; + assign n5261 = 8'h6a >> { n4988, n5009, n4980 }; + assign n2703 = 8'h72 >> { Ng876, n5260, Pg6313 }; + assign n2698 = 8'h72 >> { Ng873, n5260, Pg5437 }; + assign n1313_1 = 8'h72 >> { Ng264, n5265, Ng853 }; + assign n5265 = 64'ha2a200a2f7f7fff7 >> { Ng125, n5123, n5124, n5266, n5135, n5122 }; + assign n5266 = 4'h6 >> { n5267, n5070 }; + assign n5267 = 64'h0000000280000000 >> { n5131_1, n5064, n5067, n5080, n5083, n5142 }; + assign n1308 = 8'h72 >> { Ng261, n5265, Pg6313 }; + assign n1303_1 = 8'h72 >> { Ng258, n5265, Pg5437 }; + assign n1283 = 8'h72 >> { Ng255, n5271, Ng853 }; + assign n5271 = 64'ha2a200a2f7f7fff7 >> { Ng117, n5123, n5124, n5272, n5135, n5122 }; + assign n5272 = 16'h96aa >> { n5141_1, n5131_1, n5083, n5067 }; + assign n1278_1 = 8'h72 >> { Ng252, n5271, Pg6313 }; + assign n1273 = 8'h72 >> { Ng249, n5271, Pg5437 }; + assign n1298_1 = 8'h72 >> { Ng219, n5276, Ng853 }; + assign n5276 = 64'h2a2a002a7f7fff7f >> { Ng121, n5123, n5124, n5135, n5277, n5122 }; + assign n5277 = 32'd1452627285 >> { n5141_1, n5131_1, n5067, n5083, n5080 }; + assign n1293 = 8'h72 >> { Ng216, n5276, Pg6313 }; + assign n1288_1 = 8'h72 >> { Ng213, n5276, Pg5437 }; + assign n1268_1 = 8'h72 >> { Ng210, n5281, Ng853 }; + assign n5281 = 64'h2a2a002a7f7fff7f >> { Ng113, n5123, n5124, n5135, n5282, n5122 }; + assign n5282 = 4'h9 >> { n5141_1, n5083 }; + assign n1263 = 8'h72 >> { Ng207, n5281, Pg6313 }; + assign n1258 = 8'h72 >> { Ng204, n5281, Pg5437 }; + assign n1208 = 8'h72 >> { Ng192, n5286, Ng853 }; + assign n5286 = 64'ha2a200a2f7f7fff7 >> { Ng97, n5123, n5124, n5287, n5135, n5122 }; + assign n5287 = 8'h6a >> { n5088, n5112, n5085 }; + assign n1203 = 8'h72 >> { Ng189, n5286, Pg6313 }; + assign n1198 = 8'h72 >> { Ng186, n5286, Pg5437 }; + assign n283 = 16'hddd8 >> { Pg16297, Pg5648, Ng507, Ng506 }; + assign n279 = 64'hf5e4f5e4b1a0f5e4 >> { Ng507, Ng506, Pg16355, Ng1193, Pg5648, Ng1192 }; + assign n275 = 32'd4122076320 >> { Pg16399, n279, Ng1887, Pg5648, Ng1886 }; + assign n271 = 32'd4122076320 >> { Pg16437, n275, Ng2581, Pg5648, Ng2580 }; + assign n1708 = 16'h11b1 >> { Pg6313, Ng305, Ng298, Ng299 }; + assign n3208 = 64'h270527052705af8d >> { Ng299, Ng298, Ng992, Ng985, Pg6313, Ng986 }; + assign n4709 = 32'd2938604805 >> { Ng1686, n3208, Ng1679, Pg6313, Ng1680 }; + assign n6211 = 32'd2938604805 >> { Ng2380, n4709, Ng2373, Pg6313, Ng2374 }; + assign n860 = 8'hd8 >> { Ng3105, n4988_1, Ng1315 }; + assign n855 = 8'hd8 >> { Ng3104, n4988_1, Pg5648 }; + assign n850 = 8'hd8 >> { Ng3103, n4988_1, Pg5629 }; + assign n6061 = 8'hd8 >> { Ng2389, n5302, Ng853 }; + assign n5302 = 64'h1031103110310020 >> { n4811, n4756, n4809, n4791, n4813, n4792 }; + assign n6056 = 8'hd8 >> { Ng2388, n5302, Pg6313 }; + assign n6051 = 8'hd8 >> { Ng2387, n5302, Pg5437 }; + assign n4559 = 8'hd8 >> { Ng1695, n5306, Ng853 }; + assign n5306 = 8'h51 >> { n4916_1, n4922, n5307 }; + assign n5307 = 64'hdfdf8edf8edf8edf >> { n4886, n4858, n4885, n4884, n4911, n4910 }; + assign n4554 = 8'hd8 >> { Ng1694, n5306, Pg6313 }; + assign n4549 = 8'hd8 >> { Ng1693, n5306, Pg5437 }; + assign n3058 = 8'hd8 >> { Ng1001, n5311, Ng853 }; + assign n5311 = 32'd2101297 >> { n5312, n5011_1, n4988, n5012, n5009 }; + assign n5312 = 8'hd5 >> { n4990, n4963, n5010 }; + assign n3053 = 8'hd8 >> { Ng1000, n5311, Pg6313 }; + assign n3048 = 8'hd8 >> { Ng999, n5311, Pg5437 }; + assign n1558 = 16'h444e >> { n5316, n5177, Ng314, Ng853 }; + assign n5316 = 32'd2391707359 >> { n5181, n5182, n5088, n5114, n5112 }; + assign n1553 = 16'h444e >> { n5316, n5177, Ng313, Pg6313 }; + assign n1548 = 16'h444e >> { n5316, n5177, Ng312, Pg5437 }; + assign n5986 = 8'h72 >> { Ng2498, n5320, Ng853 }; + assign n5320 = 64'hccc4fff5ccc4fff7 >> { n4790_1, n6206, n4778_1, n4762_1, n5321, n5324_1 }; + assign n5321 = 8'h02 >> { n5322, n5323, Ng2257 }; + assign n5322 = 64'h0000077707770777 >> { Pg6313, Ng2486, Ng853, Ng2489, Pg5437, Ng2483 }; + assign n5323 = 64'hdd0ddd0d0000dd0d >> { Ng2503, Pg6313, Ng2501, Ng853, Ng2502, Pg5437 }; + assign n5324_1 = 32'd2147483648 >> { n5325, Ng2175, Ng2180, Ng2190, Ng2195 }; + assign n5325 = 16'h8000 >> { Ng2165, Ng2170, Ng2185, Ng2200 }; + assign n5981 = 8'h72 >> { Ng2495, n5320, Pg6313 }; + assign n5976 = 8'h72 >> { Ng2492, n5320, Pg5437 }; + assign n6106 = 64'haaeaaaeaaa2aaaea >> { n6673, n4814, n5329_1, Ng853, Ng2257, Ng2396 }; + assign n5329_1 = 4'h1 >> { n4805, n4822 }; + assign n6101 = 64'haaeaaaeaaa2aaaea >> { n6673, n4814, n5329_1, Pg6313, Ng2257, Ng2398 }; + assign n6096 = 64'haaeaaaeaaa2aaaea >> { n6673, n4814, n5329_1, Pg5437, Ng2257, Ng2397 }; + assign n4484 = 8'hd8 >> { Ng1804, n5333, Ng853 }; + assign n5333 = 64'hececece4cccccce4 >> { n4882, n5337, n5338, n5334_1, n4704, Ng2257 }; + assign n5334_1 = 8'h02 >> { n4864, n4875, n5335 }; + assign n5335 = 32'd2147483648 >> { n5336, Ng1481, Ng1486, Ng1496, Ng1501 }; + assign n5336 = 16'h8000 >> { Ng1471, Ng1476, Ng1491, Ng1506 }; + assign n5337 = 64'h0000077707770777 >> { Pg6313, Ng1792, Ng853, Ng1795, Pg5437, Ng1789 }; + assign n5338 = 64'hdd0ddd0d0000dd0d >> { Ng1809, Pg6313, Ng1807, Ng853, Ng1808, Pg5437 }; + assign n4479 = 8'hd8 >> { Ng1801, n5333, Pg6313 }; + assign n4474 = 8'hd8 >> { Ng1798, n5333, Pg5437 }; + assign n4604 = 64'haaeaaaeaaa2aaaea >> { n4923, n4922, n5342, Ng853, Ng2257, Ng1702 }; + assign n5342 = 4'h1 >> { n4871, n5343 }; + assign n5343 = 8'h02 >> { n4884, n4910, n4911 }; + assign n4599 = 64'haaeaaaeaaa2aaaea >> { n4923, n4922, n5342, Pg6313, Ng2257, Ng1704 }; + assign n4594 = 64'haaeaaaeaaa2aaaea >> { n4923, n4922, n5342, Pg5437, Ng2257, Ng1703 }; + assign n2983 = 8'h72 >> { Ng1110, n5347, Ng853 }; + assign n5347 = 64'h1111555d5551555d >> { n4986, n5348, n5351, n5352, Ng2257, n3203 }; + assign n5348 = 8'h02 >> { n4968, n4984, n5349_1 }; + assign n5349_1 = 32'd2147483648 >> { n5350, Ng793, Ng797, Ng805, Ng809 }; + assign n5350 = 16'h8000 >> { Ng785, Ng789, Ng801, Ng813 }; + assign n5351 = 64'h0000077707770777 >> { Pg6313, Ng1098, Ng853, Ng1101, Pg5437, Ng1095 }; + assign n5352 = 64'hdd0ddd0d0000dd0d >> { Ng1115, Pg6313, Ng1113, Ng853, Ng1114, Pg5437 }; + assign n2978 = 8'h72 >> { Ng1107, n5347, Pg6313 }; + assign n2973 = 8'h72 >> { Ng1104, n5347, Pg5437 }; + assign n3103 = 64'haaeaaaeaaa2aaaea >> { n5022, n5358, n5356, Ng853, Ng2257, Ng1008 }; + assign n5356 = 4'h1 >> { n4976, n5357 }; + assign n5357 = 8'h02 >> { n4988, n5009, n5011_1 }; + assign n5358 = 32'd2147483648 >> { n4996, n5000, n5013, n5014, n5015 }; + assign n3098 = 64'haaeaaaeaaa2aaaea >> { n5022, n5358, n5356, Pg6313, Ng2257, Ng1010 }; + assign n3093 = 64'haaeaaaeaaa2aaaea >> { n5022, n5358, n5356, Pg5437, Ng2257, Ng1009 }; + assign n1483 = 8'hd8 >> { Ng423, n5362, Ng853 }; + assign n5362 = 64'hececece4cccccce4 >> { n5086_1, n5366, n5367, n5363, n1703, Ng2257 }; + assign n5363 = 8'h02 >> { n5065, n5078, n5364_1 }; + assign n5364_1 = 32'd2147483648 >> { n5365, Ng105, Ng109, Ng117, Ng121 }; + assign n5365 = 16'h8000 >> { Ng97, Ng101, Ng113, Ng125 }; + assign n5366 = 64'h0000077707770777 >> { Pg6313, Ng411, Ng853, Ng414, Pg5437, Ng408 }; + assign n5367 = 64'hdd0ddd0d0000dd0d >> { Ng428, Pg6313, Ng426, Ng853, Ng427, Pg5437 }; + assign n1478 = 8'hd8 >> { Ng420, n5362, Pg6313 }; + assign n1473 = 8'hd8 >> { Ng417, n5362, Pg5437 }; + assign n1603 = 32'd2854922986 >> { n5371, n5372, Ng853, Ng2257, Ng321 }; + assign n5371 = 4'h2 >> { n5123, n6689 }; + assign n5372 = 4'h1 >> { n5075, n5373 }; + assign n5373 = 8'h02 >> { n5088, n5112, n5114 }; + assign n1598 = 32'd2854922986 >> { n5371, n5372, Pg6313, Ng2257, Ng323 }; + assign n1593 = 32'd2854922986 >> { n5371, n5372, Pg5437, Ng2257, Ng322 }; + assign n5971 = 8'h72 >> { Ng2489, n5377, Ng853 }; + assign n5377 = 16'h4e6e >> { n5323, n5378, n5322, Ng2257 }; + assign n5378 = 32'd2862787238 >> { n4790_1, n4778_1, n4762_1, n5324_1, n6206 }; + assign n5966 = 8'h72 >> { Ng2486, n5377, Pg6313 }; + assign n5961 = 8'h72 >> { Ng2483, n5377, Pg5437 }; + assign n4469 = 8'h72 >> { Ng1795, n5382, Ng853 }; + assign n5382 = 16'he4e6 >> { n5338, n5383, n5337, Ng2257 }; + assign n5383 = 8'hb9 >> { n4909, n4704, n5334_1 }; + assign n4464 = 8'h72 >> { Ng1792, n5382, Pg6313 }; + assign n4459 = 8'h72 >> { Ng1789, n5382, Pg5437 }; + assign n2968 = 8'h72 >> { Ng1101, n5387, Ng853 }; + assign n5387 = 16'h4e6e >> { n5352, n5388, n5351, Ng2257 }; + assign n5388 = 8'h46 >> { n4986, n3203, n5348 }; + assign n2963 = 8'h72 >> { Ng1098, n5387, Pg6313 }; + assign n2958 = 8'h72 >> { Ng1095, n5387, Pg5437 }; + assign n1468 = 8'h72 >> { Ng414, n5392, Ng853 }; + assign n5392 = 16'he4e6 >> { n5367, n5393, n5366, Ng2257 }; + assign n5393 = 8'hb9 >> { n5086_1, n1703, n5363 }; + assign n1463 = 8'h72 >> { Ng411, n5392, Pg6313 }; + assign n1458 = 8'h72 >> { Ng408, n5392, Pg5437 }; + assign n845 = 8'hd8 >> { Ng3102, n3487, Ng1315 }; + assign n840 = 8'hd8 >> { Ng3101, n3487, Pg5648 }; + assign n835 = 8'hd8 >> { Ng3100, n3487, Pg5629 }; + assign n6468 = 64'h0000077707770777 >> { Pg5648, Ng2641, Ng2639, Pg5629, Ng1315, Ng2564 }; + assign n6332 = 64'h0000077707770777 >> { Pg5648, Ng2645, Ng2643, Pg5629, Ng1315, Ng2647 }; + assign n6613 = 64'hd8d8d8d8fad8d8d8 >> { n5402, n5427, n5421, Ng2694, n5420, Ng1315 }; + assign n5402 = 4'h8 >> { n5403, n5418 }; + assign n5403 = 64'h0010001120302233 >> { n5404_1, n5417, n5416, n5409_1, n5413, n5415 }; + assign n5404_1 = 32'd3301229781 >> { n5409_1, n5410, n5405, n5411, n5412 }; + assign n5405 = 8'h08 >> { n5408, n5407, n5406 }; + assign n5406 = 64'hdd0ddd0d0000dd0d >> { Ng2654, Pg5648, Ng2653, Pg5629, Ng2652, Ng1315 }; + assign n5407 = 64'hdd0ddd0d0000dd0d >> { Ng2657, Pg5648, Ng2656, Pg5629, Ng2655, Ng1315 }; + assign n5408 = 64'h0000077707770777 >> { Pg5648, Ng2441, Ng2439, Pg5629, Ng1315, Ng2443 }; + assign n5409_1 = 64'hdd0ddd0d0000dd0d >> { Ng2651, Pg5648, Ng2650, Pg5629, Ng2649, Ng1315 }; + assign n5410 = 64'h0000077707770777 >> { Pg5648, Ng2471, Ng2469, Pg5629, Ng1315, Ng2399 }; + assign n5411 = 64'h0000077707770777 >> { Pg5648, Ng2456, Ng2454, Pg5629, Ng1315, Ng2458 }; + assign n5412 = 64'hdd0ddd0d0000dd0d >> { Ng2660, Pg5648, Ng2659, Pg5629, Ng2658, Ng1315 }; + assign n5413 = 64'ha0a8a0a8a8a8a0a8 >> { n5415, n5412, n5407, n5414_1, n5410, n5409_1 }; + assign n5414_1 = 32'd33555201 >> { n5407, n5406, n5408, n5411, n5415 }; + assign n5415 = 64'h0000077707770777 >> { Pg5648, Ng2426, Ng2424, Pg5629, Ng1315, Ng2428 }; + assign n5416 = 32'd1157645572 >> { n5410, n5411, n5408, n5407, n5406 }; + assign n5417 = 64'h8aaa022a88aa002a >> { n5412, n5406, n5407, n5411, n5415, n5408 }; + assign n5418 = 16'haa2a >> { n6468, Ng185, Ng2616, n5419_1 }; + assign n5419_1 = 64'h0000077707770777 >> { Pg5648, Ng2673, Ng2670, Pg5629, Ng1315, Ng2676 }; + assign n5420 = 4'h1 >> { n4556, n4577 }; + assign n5421 = 8'h01 >> { n5422, n5424_1, n5426 }; + assign n5422 = 64'h5510101010101010 >> { n5410, n5406, n5407, n5415, n5423, n5409_1 }; + assign n5423 = 64'hadadad8cafafaf8c >> { n5412, n5407, n5410, n5411, n5408, n5406 }; + assign n5424_1 = 64'h1010101010101055 >> { n5408, n5411, n5412, n5409_1, n5425, n5415 }; + assign n5425 = 64'h45cfcfcf45c7c7c7 >> { n5410, n5412, n5411, n5408, n5407, n5406 }; + assign n5426 = 64'h2222002000200020 >> { n5407, n5415, n5411, n5409_1, n5406, n5408 }; + assign n5427 = 8'ha8 >> { n5428, n5418, n4556 }; + assign n5428 = 16'haa2a >> { n6332, Ng185, Ng2598, n5429_1 }; + assign n5429_1 = 64'h0000077707770777 >> { Pg5648, Ng2664, Pg5629, Ng2661, Ng1315, Ng2667 }; + assign n6608 = 64'hd8d8d8d8fad8d8d8 >> { n5402, n5427, n5421, Ng2691, n5420, Pg5648 }; + assign n6603 = 64'hd8d8d8d8fad8d8d8 >> { n5402, n5427, n5421, Ng2688, n5420, Pg5629 }; + assign n6628 = 8'h72 >> { Ng2685, n5433, Ng1315 }; + assign n5433 = 64'hf7a27722ffaa7f2a >> { n5418, n5421, n4576, n5428, n5403, n4556 }; + assign n6623 = 8'h72 >> { Ng2682, n5433, Pg5648 }; + assign n6618 = 8'h72 >> { Ng2679, n5433, Pg5629 }; + assign n4966 = 64'h0000077707770777 >> { Pg5648, Ng1947, Ng1945, Pg5629, Ng1315, Ng1870 }; + assign n4830 = 64'h0000077707770777 >> { Pg5648, Ng1951, Ng1949, Pg5629, Ng1315, Ng1953 }; + assign n5111 = 64'hd8d8d8d8fad8d8d8 >> { n5439_1, n5458, n5455, Ng2000, n5454_1, Ng1315 }; + assign n5439_1 = 4'h8 >> { n6691_1, n5452 }; + assign n5440 = 64'ha020a020a020a222 >> { n5445, n5448, n5441, n5449_1, n5447, n5446 }; + assign n5441 = 8'h08 >> { n5444_1, n5443, n5442 }; + assign n5442 = 64'hdd0ddd0d0000dd0d >> { Ng1963, Pg5648, Ng1962, Pg5629, Ng1961, Ng1315 }; + assign n5443 = 64'hdd0ddd0d0000dd0d >> { Ng1960, Pg5648, Ng1959, Pg5629, Ng1958, Ng1315 }; + assign n5444_1 = 64'h0000077707770777 >> { Pg5648, Ng1747, Ng1745, Pg5629, Ng1315, Ng1749 }; + assign n5445 = 64'hdd0ddd0d0000dd0d >> { Ng1957, Pg5648, Ng1956, Pg5629, Ng1955, Ng1315 }; + assign n5446 = 64'h0000077707770777 >> { Pg5648, Ng1732, Ng1730, Pg5629, Ng1315, Ng1734 }; + assign n5447 = 64'hdd0ddd0d0000dd0d >> { Ng1966, Pg5648, Ng1965, Pg5629, Ng1964, Ng1315 }; + assign n5448 = 64'h0000077707770777 >> { Pg5648, Ng1777, Ng1775, Pg5629, Ng1315, Ng1705 }; + assign n5449_1 = 64'h0000077707770777 >> { Pg5648, Ng1762, Ng1760, Pg5629, Ng1315, Ng1764 }; + assign n5450 = 16'h22a2 >> { n5446, n5447, n5442, n5448 }; + assign n5451 = 64'h1011000010110010 >> { n5448, n5449_1, n5444_1, n5442, n5443, n5446 }; + assign n5452 = 16'haa2a >> { n4966, Ng185, Ng1922, n5453 }; + assign n5453 = 64'h0000077707770777 >> { Pg5648, Ng1979, Ng1976, Pg5629, Ng1315, Ng1982 }; + assign n5454_1 = 4'h1 >> { n4556, n4573 }; + assign n5455 = 8'ha8 >> { n5456, n5452, n4556 }; + assign n5456 = 16'haa2a >> { n4830, Ng185, Ng1904, n5457 }; + assign n5457 = 64'h0000077707770777 >> { Pg5648, Ng1970, Pg5629, Ng1967, Ng1315, Ng1973 }; + assign n5458 = 8'h01 >> { n5459_1, n5461, n5463 }; + assign n5459_1 = 64'h1010101010101055 >> { n5447, n5444_1, n5449_1, n5445, n5460, n5446 }; + assign n5460 = 64'h45cfcfcf45c7c7c7 >> { n5448, n5449_1, n5447, n5444_1, n5442, n5443 }; + assign n5461 = 64'h5510101010101010 >> { n5442, n5448, n5443, n5446, n5462, n5445 }; + assign n5462 = 64'hadadad8cafafaf8c >> { n5447, n5448, n5442, n5449_1, n5444_1, n5443 }; + assign n5463 = 64'h2222002000200020 >> { n5446, n5442, n5449_1, n5445, n5443, n5444_1 }; + assign n5106 = 64'hd8d8d8d8fad8d8d8 >> { n5439_1, n5458, n5455, Ng1997, n5454_1, Pg5648 }; + assign n5101 = 64'hd8d8d8d8fad8d8d8 >> { n5439_1, n5458, n5455, Ng1994, n5454_1, Pg5629 }; + assign n5126 = 64'hd8d8d8d8fad8d8d8 >> { n5467, n5455, n6691_1, Ng1991, n5468, Ng1315 }; + assign n5467 = 4'h8 >> { n5458, n5456 }; + assign n5468 = 4'h1 >> { n4556, n4572 }; + assign n5121 = 64'hd8d8d8d8fad8d8d8 >> { n5467, n5455, n6691_1, Ng1988, n5468, Pg5648 }; + assign n5116 = 64'hd8d8d8d8fad8d8d8 >> { n5467, n5455, n6691_1, Ng1985, n5468, Pg5629 }; + assign n3465 = 64'h0000077707770777 >> { Pg5648, Ng1253, Ng1251, Pg5629, Ng1315, Ng1176 }; + assign n3329 = 64'h0000077707770777 >> { Pg5648, Ng1257, Ng1255, Pg5629, Ng1315, Ng1259 }; + assign n3610 = 8'h72 >> { Ng1306, n5474_1, Ng1315 }; + assign n5474_1 = 32'd4008578798 >> { n5489_1, n5475, n5499_1, n4569_1, n4556 }; + assign n5475 = 8'h01 >> { n5476, n5486, n5488 }; + assign n5476 = 64'h5510101010101010 >> { n5478, n5479_1, n5480, n5485, n5477, n5484_1 }; + assign n5477 = 64'hadadad8cafafaf8c >> { n5483, n5479_1, n5478, n5482, n5481, n5480 }; + assign n5478 = 64'h0000077707770777 >> { Pg5648, Ng1083, Ng1081, Pg5629, Ng1315, Ng1011 }; + assign n5479_1 = 64'hdd0ddd0d0000dd0d >> { Ng1269, Pg5648, Ng1268, Pg5629, Ng1267, Ng1315 }; + assign n5480 = 64'hdd0ddd0d0000dd0d >> { Ng1266, Pg5648, Ng1265, Pg5629, Ng1264, Ng1315 }; + assign n5481 = 64'h0000077707770777 >> { Pg5648, Ng1053, Ng1051, Pg5629, Ng1315, Ng1055 }; + assign n5482 = 64'h0000077707770777 >> { Pg5648, Ng1068, Ng1066, Pg5629, Ng1315, Ng1070 }; + assign n5483 = 64'hdd0ddd0d0000dd0d >> { Ng1272, Pg5648, Ng1271, Pg5629, Ng1270, Ng1315 }; + assign n5484_1 = 64'hdd0ddd0d0000dd0d >> { Ng1263, Pg5648, Ng1262, Pg5629, Ng1261, Ng1315 }; + assign n5485 = 64'h0000077707770777 >> { Pg5648, Ng1038, Ng1036, Pg5629, Ng1315, Ng1040 }; + assign n5486 = 64'h1010101010101055 >> { n5481, n5482, n5483, n5484_1, n5487, n5485 }; + assign n5487 = 64'h45cfcfcf45c7c7c7 >> { n5478, n5483, n5482, n5481, n5479_1, n5480 }; + assign n5488 = 64'h2222002000200020 >> { n5485, n5479_1, n5482, n5484_1, n5480, n5481 }; + assign n5489_1 = 32'd2 >> { n5490, n5492, n5494_1, n5498, n5496 }; + assign n5490 = 64'ha0a8a0a8a8a8a0a8 >> { n5485, n5483, n5479_1, n5491, n5478, n5484_1 }; + assign n5491 = 32'd33751041 >> { n5480, n5479_1, n5481, n5482, n5485 }; + assign n5492 = 64'ha020a020a020a222 >> { n5484_1, n5478, n5493, n5482, n5483, n5485 }; + assign n5493 = 8'h08 >> { n5481, n5480, n5479_1 }; + assign n5494_1 = 4'h2 >> { n5484_1, n5495 }; + assign n5495 = 64'h8aaa022a88aa002a >> { n5483, n5480, n5479_1, n5482, n5485, n5481 }; + assign n5496 = 16'haa2a >> { n3465, Ng185, Ng1228, n5497 }; + assign n5497 = 64'h0000077707770777 >> { Pg5648, Ng1285, Ng1282, Pg5629, Ng1315, Ng1288 }; + assign n5498 = 64'h1011000010110010 >> { n5478, n5482, n5481, n5479_1, n5480, n5485 }; + assign n5499_1 = 8'ha8 >> { n5500, n5496, n4556 }; + assign n5500 = 16'haa2a >> { n3329, Ng185, Ng1210, n5501 }; + assign n5501 = 64'h0000077707770777 >> { Pg5648, Ng1276, Pg5629, Ng1273, Ng1315, Ng1279 }; + assign n3605 = 8'h72 >> { Ng1303, n5474_1, Pg5648 }; + assign n3600 = 8'h72 >> { Ng1300, n5474_1, Pg5629 }; + assign n3625 = 64'hd8d8d8d8fad8d8d8 >> { n5505, n5499_1, n5506, Ng1297, n5507, Ng1315 }; + assign n5505 = 4'h8 >> { n5475, n5500 }; + assign n5506 = 16'h0001 >> { n5490, n5492, n5494_1, n5498 }; + assign n5507 = 4'h1 >> { n4556, n4568 }; + assign n3620 = 64'hd8d8d8d8fad8d8d8 >> { n5505, n5499_1, n5506, Ng1294, n5507, Pg5648 }; + assign n3615 = 64'hd8d8d8d8fad8d8d8 >> { n5505, n5499_1, n5506, Ng1291, n5507, Pg5629 }; + assign n1965_1 = 64'h0000077707770777 >> { Pg5648, Ng567, Ng565, Pg5629, Ng1315, Ng489 }; + assign n1829_1 = 64'h0000077707770777 >> { Pg5648, Ng571, Ng569, Pg5629, Ng1315, Ng573 }; + assign n2110 = 8'h72 >> { Ng620, n5513, Ng1315 }; + assign n5513 = 32'd4008578798 >> { n5528, n5514_1, n5538, n4565, n4556 }; + assign n5514_1 = 8'h01 >> { n5515, n5525, n5527 }; + assign n5515 = 64'h5510101010101010 >> { n5517, n5518, n5519_1, n5524_1, n5516, n5523 }; + assign n5516 = 64'hadadad8cafafaf8c >> { n5522, n5518, n5517, n5521, n5520, n5519_1 }; + assign n5517 = 64'h0000077707770777 >> { Pg5648, Ng396, Ng394, Pg5629, Ng1315, Ng324 }; + assign n5518 = 64'hdd0ddd0d0000dd0d >> { Ng583, Pg5648, Ng582, Pg5629, Ng581, Ng1315 }; + assign n5519_1 = 64'hdd0ddd0d0000dd0d >> { Ng580, Pg5648, Ng579, Pg5629, Ng578, Ng1315 }; + assign n5520 = 64'h0000077707770777 >> { Pg5648, Ng366, Ng364, Pg5629, Ng1315, Ng368 }; + assign n5521 = 64'h0000077707770777 >> { Pg5648, Ng381, Ng379, Pg5629, Ng1315, Ng383 }; + assign n5522 = 64'hdd0ddd0d0000dd0d >> { Ng586, Pg5648, Ng585, Pg5629, Ng584, Ng1315 }; + assign n5523 = 64'hdd0ddd0d0000dd0d >> { Ng577, Pg5648, Ng576, Pg5629, Ng575, Ng1315 }; + assign n5524_1 = 64'h0000077707770777 >> { Pg5648, Ng351, Ng349, Pg5629, Ng1315, Ng353 }; + assign n5525 = 64'h1010101010101055 >> { n5520, n5521, n5522, n5523, n5526, n5524_1 }; + assign n5526 = 64'h45cfcfcf45c7c7c7 >> { n5517, n5522, n5521, n5520, n5518, n5519_1 }; + assign n5527 = 64'h2222002000200020 >> { n5524_1, n5518, n5521, n5523, n5519_1, n5520 }; + assign n5528 = 32'd2 >> { n5529_1, n5531, n5533, n5537, n5535 }; + assign n5529_1 = 64'ha0a8a0a8a8a8a0a8 >> { n5524_1, n5522, n5518, n5530, n5517, n5523 }; + assign n5530 = 32'd33751041 >> { n5519_1, n5518, n5520, n5521, n5524_1 }; + assign n5531 = 64'ha020a020a020a222 >> { n5523, n5517, n5532, n5521, n5522, n5524_1 }; + assign n5532 = 8'h08 >> { n5520, n5519_1, n5518 }; + assign n5533 = 4'h2 >> { n5523, n5534_1 }; + assign n5534_1 = 64'h8aaa022a88aa002a >> { n5522, n5519_1, n5518, n5521, n5524_1, n5520 }; + assign n5535 = 16'haa2a >> { n1965_1, Ng185, Ng542, n5536 }; + assign n5536 = 64'h0000077707770777 >> { Pg5648, Ng599, Ng596, Pg5629, Ng1315, Ng602 }; + assign n5537 = 64'h1011000010110010 >> { n5517, n5521, n5520, n5518, n5519_1, n5524_1 }; + assign n5538 = 8'ha8 >> { n5539_1, n5535, n4556 }; + assign n5539_1 = 16'haa2a >> { n1829_1, Ng185, Ng524, n5540 }; + assign n5540 = 64'h0000077707770777 >> { Pg5648, Ng590, Pg5629, Ng587, Ng1315, Ng593 }; + assign n2105 = 8'h72 >> { Ng617, n5513, Pg5648 }; + assign n2100 = 8'h72 >> { Ng614, n5513, Pg5629 }; + assign n2125 = 64'hd8d8d8d8fad8d8d8 >> { n5544_1, n5538, n5545, Ng611, n5546, Ng1315 }; + assign n5544_1 = 4'h8 >> { n5514_1, n5539_1 }; + assign n5545 = 16'h0001 >> { n5529_1, n5531, n5533, n5537 }; + assign n5546 = 4'h1 >> { n4556, n4564 }; + assign n2120 = 64'hd8d8d8d8fad8d8d8 >> { n5544_1, n5538, n5545, Ng608, n5546, Pg5648 }; + assign n2115 = 64'hd8d8d8d8fad8d8d8 >> { n5544_1, n5538, n5545, Ng605, n5546, Pg5629 }; + assign n6568 = 64'h7fffff7f2aaaaa2a >> { Ng2658, n5409_1, Pg3229, n5407, n5406, n5550 }; + assign n5550 = 4'h8 >> { n6652_1, Ng1315 }; + assign n6563 = 64'h7fffff7f2aaaaa2a >> { Ng2660, n5409_1, Pg3229, n5407, n5406, n5552 }; + assign n5552 = 4'h8 >> { n6652_1, Pg5648 }; + assign n6558 = 64'h7fffff7f2aaaaa2a >> { Ng2659, n5409_1, Pg3229, n5407, n5406, n5554_1 }; + assign n5554_1 = 4'h8 >> { n6652_1, Pg5629 }; + assign n6553 = 8'hd8 >> { Ng2655, n5556, n5550 }; + assign n5556 = 16'h96be >> { n5412, n5409_1, Pg3229, n5406 }; + assign n6548 = 8'hd8 >> { Ng2657, n5556, n5552 }; + assign n6543 = 8'hd8 >> { Ng2656, n5556, n5554_1 }; + assign n6538 = 64'hfddfa88a75572002 >> { n5406, Ng2652, n5409_1, Pg3229, n5407, n5550 }; + assign n6533 = 64'hfddfa88a75572002 >> { n5406, Ng2654, n5409_1, Pg3229, n5407, n5552 }; + assign n6528 = 64'hfddfa88a75572002 >> { n5406, Ng2653, n5409_1, Pg3229, n5407, n5554_1 }; + assign n6523 = 8'hd8 >> { Ng2649, n5563, n5550 }; + assign n5563 = 32'd3433846021 >> { n5412, n5406, n5407, n5409_1, Pg3229 }; + assign n6518 = 8'hd8 >> { Ng2651, n5563, n5552 }; + assign n6513 = 8'hd8 >> { Ng2650, n5563, n5554_1 }; + assign n5956 = 8'h72 >> { Ng11589, n5570, n5567 }; + assign n5567 = 16'h888a >> { n5568, n5569_1, n4831, Ng853 }; + assign n5568 = 4'h2 >> { n4791, n4816 }; + assign n5569_1 = 32'd1 >> { Ng2900, Ng2896, Ng2908, Ng2892, Ng2903 }; + assign n5570 = 16'h8008 >> { n5573, Pg3229, n5571, n5572 }; + assign n5571 = 64'hdd0ddd0d0000dd0d >> { Ng11585, Pg6313, Ng11586, Ng853, Ng11584, Pg5437 }; + assign n5572 = 64'hdd0ddd0d0000dd0d >> { Ng11582, Pg6313, Ng11583, Ng853, Ng11581, Pg5437 }; + assign n5573 = 64'hdd0ddd0d0000dd0d >> { Ng11579, Pg6313, Ng11580, Ng853, Ng11578, Pg5437 }; + assign n5951 = 8'h72 >> { Ng11588, n5570, n5575 }; + assign n5575 = 16'h888a >> { n5568, n5569_1, n4831, Pg6313 }; + assign n5946 = 8'h72 >> { Ng11587, n5570, n5577 }; + assign n5577 = 16'h888a >> { n5568, n5569_1, n4831, Pg5437 }; + assign n5941 = 8'h72 >> { Ng11586, n5579_1, n5567 }; + assign n5579_1 = 16'h6941 >> { n5580, n5573, Pg3229, n5572 }; + assign n5580 = 64'hdd0ddd0d0000dd0d >> { Ng11588, Pg6313, Ng11589, Ng853, Ng11587, Pg5437 }; + assign n5936 = 8'h72 >> { Ng11585, n5579_1, n5575 }; + assign n5931 = 8'h72 >> { Ng11584, n5579_1, n5577 }; + assign n5926 = 8'hd8 >> { Ng11583, n5584_1, n5567 }; + assign n5584_1 = 16'heb41 >> { n5572, n5573, Pg3229, n5571 }; + assign n5921 = 8'hd8 >> { Ng11582, n5584_1, n5575 }; + assign n5916 = 8'hd8 >> { Ng11581, n5584_1, n5577 }; + assign n5911 = 8'hd8 >> { Ng11580, n5588, n5567 }; + assign n5588 = 32'd3315647941 >> { n5571, n5572, n5580, n5573, Pg3229 }; + assign n5906 = 8'hd8 >> { Ng11579, n5588, n5575 }; + assign n5901 = 8'hd8 >> { Ng11578, n5588, n5577 }; + assign n5066 = 64'h7fffff7f2aaaaa2a >> { Ng1964, n5445, Pg3229, n5443, n5442, n5592 }; + assign n5592 = 4'h8 >> { n5150_1, Ng1315 }; + assign n5061 = 64'h7fffff7f2aaaaa2a >> { Ng1966, n5445, Pg3229, n5443, n5442, n5594_1 }; + assign n5594_1 = 4'h8 >> { n5150_1, Pg5648 }; + assign n5056 = 64'h7fffff7f2aaaaa2a >> { Ng1965, n5445, Pg3229, n5443, n5442, n5596 }; + assign n5596 = 4'h8 >> { n5150_1, Pg5629 }; + assign n5051 = 8'h72 >> { Ng1961, n5598, n5592 }; + assign n5598 = 16'h6941 >> { n5447, n5445, Pg3229, n5443 }; + assign n5046 = 8'h72 >> { Ng1963, n5598, n5594_1 }; + assign n5041 = 8'h72 >> { Ng1962, n5598, n5596 }; + assign n5036 = 64'hfddfa88a75572002 >> { n5443, Ng1958, n5445, Pg3229, n5442, n5592 }; + assign n5031 = 64'hfddfa88a75572002 >> { n5443, Ng1960, n5445, Pg3229, n5442, n5594_1 }; + assign n5026 = 64'hfddfa88a75572002 >> { n5443, Ng1959, n5445, Pg3229, n5442, n5596 }; + assign n5021 = 8'hd8 >> { Ng1955, n5605, n5592 }; + assign n5605 = 32'd3433846021 >> { n5447, n5443, n5442, n5445, Pg3229 }; + assign n5016 = 8'hd8 >> { Ng1957, n5605, n5594_1 }; + assign n5011 = 8'hd8 >> { Ng1956, n5605, n5596 }; + assign n4454 = 8'h72 >> { Ng11562, n5611, n5609_1 }; + assign n5609_1 = 16'h888a >> { n5610, n5569_1, n4932, Ng853 }; + assign n5610 = 8'h02 >> { n4884, n4911, n4910 }; + assign n5611 = 16'h8008 >> { n5614_1, Pg3229, n5612, n5613 }; + assign n5612 = 64'hdd0ddd0d0000dd0d >> { Ng11558, Pg6313, Ng11559, Ng853, Ng11557, Pg5437 }; + assign n5613 = 64'hdd0ddd0d0000dd0d >> { Ng11555, Pg6313, Ng11556, Ng853, Ng11554, Pg5437 }; + assign n5614_1 = 64'hdd0ddd0d0000dd0d >> { Ng11552, Pg6313, Ng11553, Ng853, Ng11551, Pg5437 }; + assign n4449 = 8'h72 >> { Ng11561, n5611, n5616 }; + assign n5616 = 16'h888a >> { n5610, n5569_1, n4932, Pg6313 }; + assign n4444 = 8'h72 >> { Ng11560, n5611, n5618 }; + assign n5618 = 16'h888a >> { n5610, n5569_1, n4932, Pg5437 }; + assign n4439 = 8'h72 >> { Ng11559, n5620, n5609_1 }; + assign n5620 = 16'h6941 >> { n5621, n5614_1, Pg3229, n5613 }; + assign n5621 = 64'hdd0ddd0d0000dd0d >> { Ng11561, Pg6313, Ng11562, Ng853, Ng11560, Pg5437 }; + assign n4434 = 8'h72 >> { Ng11558, n5620, n5616 }; + assign n4429 = 8'h72 >> { Ng11557, n5620, n5618 }; + assign n4424 = 8'hd8 >> { Ng11556, n5625, n5609_1 }; + assign n5625 = 16'heb41 >> { n5613, n5614_1, Pg3229, n5612 }; + assign n4419 = 8'hd8 >> { Ng11555, n5625, n5616 }; + assign n4414 = 8'hd8 >> { Ng11554, n5625, n5618 }; + assign n4409 = 8'hd8 >> { Ng11553, n5629_1, n5609_1 }; + assign n5629_1 = 32'd3315647941 >> { n5612, n5613, n5621, n5614_1, Pg3229 }; + assign n4404 = 8'hd8 >> { Ng11552, n5629_1, n5616 }; + assign n4399 = 8'hd8 >> { Ng11551, n5629_1, n5618 }; + assign n3565 = 64'h7fffff7f2aaaaa2a >> { Ng1270, n5484_1, Pg3229, n5480, n5479_1, n5633 }; + assign n5633 = 4'h8 >> { n3649, Ng1315 }; + assign n3560 = 64'h7fffff7f2aaaaa2a >> { Ng1272, n5484_1, Pg3229, n5480, n5479_1, n5635 }; + assign n5635 = 4'h8 >> { n3649, Pg5648 }; + assign n3555 = 64'h7fffff7f2aaaaa2a >> { Ng1271, n5484_1, Pg3229, n5480, n5479_1, n5637 }; + assign n5637 = 4'h8 >> { n3649, Pg5629 }; + assign n3550 = 8'hd8 >> { Ng1267, n5639_1, n5633 }; + assign n5639_1 = 16'h96be >> { n5483, n5484_1, Pg3229, n5480 }; + assign n3545 = 8'hd8 >> { Ng1269, n5639_1, n5635 }; + assign n3540 = 8'hd8 >> { Ng1268, n5639_1, n5637 }; + assign n3535 = 64'hfddfa88a75572002 >> { n5480, Ng1264, n5484_1, Pg3229, n5479_1, n5633 }; + assign n3530 = 64'hfddfa88a75572002 >> { n5480, Ng1266, n5484_1, Pg3229, n5479_1, n5635 }; + assign n3525 = 64'hfddfa88a75572002 >> { n5480, Ng1265, n5484_1, Pg3229, n5479_1, n5637 }; + assign n3520 = 8'hd8 >> { Ng1261, n5646, n5633 }; + assign n5646 = 32'd3433846021 >> { n5483, n5480, n5479_1, n5484_1, Pg3229 }; + assign n3515 = 8'hd8 >> { Ng1263, n5646, n5635 }; + assign n3510 = 8'hd8 >> { Ng1262, n5646, n5637 }; + assign n2953 = 8'h72 >> { Ng11535, n5652, n5650 }; + assign n5650 = 8'ha8 >> { n5651, n5031_1, Ng853 }; + assign n5651 = 16'h5551 >> { n5011_1, n4988, n5009, n5569_1 }; + assign n5652 = 16'h8008 >> { n5655, Pg3229, n5653, n5654_1 }; + assign n5653 = 64'hdd0ddd0d0000dd0d >> { Ng11531, Pg6313, Ng11532, Ng853, Ng11530, Pg5437 }; + assign n5654_1 = 64'hdd0ddd0d0000dd0d >> { Ng11528, Pg6313, Ng11529, Ng853, Ng11527, Pg5437 }; + assign n5655 = 64'hdd0ddd0d0000dd0d >> { Ng11525, Pg6313, Ng11526, Ng853, Ng11524, Pg5437 }; + assign n2948 = 8'h72 >> { Ng11534, n5652, n5657 }; + assign n5657 = 8'ha8 >> { n5651, n5031_1, Pg6313 }; + assign n2943 = 8'h72 >> { Ng11533, n5652, n5659_1 }; + assign n5659_1 = 8'ha8 >> { n5651, n5031_1, Pg5437 }; + assign n2938 = 8'h72 >> { Ng11532, n5661, n5650 }; + assign n5661 = 16'h6941 >> { n5662, n5655, Pg3229, n5654_1 }; + assign n5662 = 64'hdd0ddd0d0000dd0d >> { Ng11534, Pg6313, Ng11535, Ng853, Ng11533, Pg5437 }; + assign n2933 = 8'h72 >> { Ng11531, n5661, n5657 }; + assign n2928 = 8'h72 >> { Ng11530, n5661, n5659_1 }; + assign n2923 = 8'hd8 >> { Ng11529, n5666, n5650 }; + assign n5666 = 16'heb41 >> { n5654_1, n5655, Pg3229, n5653 }; + assign n2918 = 8'hd8 >> { Ng11528, n5666, n5657 }; + assign n2913 = 8'hd8 >> { Ng11527, n5666, n5659_1 }; + assign n2908 = 8'hd8 >> { Ng11526, n5670, n5650 }; + assign n5670 = 32'd3315647941 >> { n5653, n5654_1, n5662, n5655, Pg3229 }; + assign n2903 = 8'hd8 >> { Ng11525, n5670, n5657 }; + assign n2898 = 8'hd8 >> { Ng11524, n5670, n5659_1 }; + assign n2065 = 64'h7fffff7f2aaaaa2a >> { Ng584, n5523, Pg3229, n5519_1, n5518, n5674_1 }; + assign n5674_1 = 4'h8 >> { n2149, Ng1315 }; + assign n2060 = 64'h7fffff7f2aaaaa2a >> { Ng586, n5523, Pg3229, n5519_1, n5518, n5676 }; + assign n5676 = 4'h8 >> { n2149, Pg5648 }; + assign n2055 = 64'h7fffff7f2aaaaa2a >> { Ng585, n5523, Pg3229, n5519_1, n5518, n5678 }; + assign n5678 = 4'h8 >> { n2149, Pg5629 }; + assign n2050 = 8'hd8 >> { Ng581, n5680, n5674_1 }; + assign n5680 = 16'h96be >> { n5522, n5523, Pg3229, n5519_1 }; + assign n2045 = 8'hd8 >> { Ng583, n5680, n5676 }; + assign n2040_1 = 8'hd8 >> { Ng582, n5680, n5678 }; + assign n2035 = 64'hfddfa88a75572002 >> { n5519_1, Ng578, n5523, Pg3229, n5518, n5674_1 }; + assign n2030_1 = 64'hfddfa88a75572002 >> { n5519_1, Ng580, n5523, Pg3229, n5518, n5676 }; + assign n2025 = 64'hfddfa88a75572002 >> { n5519_1, Ng579, n5523, Pg3229, n5518, n5678 }; + assign n2020 = 8'hd8 >> { Ng575, n5687, n5674_1 }; + assign n5687 = 32'd3433846021 >> { n5522, n5519_1, n5518, n5523, Pg3229 }; + assign n2015 = 8'hd8 >> { Ng577, n5687, n5676 }; + assign n2010_1 = 8'hd8 >> { Ng576, n5687, n5678 }; + assign n1453_1 = 8'h72 >> { Ng11508, n5693, n5691 }; + assign n5691 = 16'h888a >> { n5692, n5569_1, n5137, Ng853 }; + assign n5692 = 4'h2 >> { n5114, n5117 }; + assign n5693 = 16'h8008 >> { n5696, Pg3229, n5694_1, n5695 }; + assign n5694_1 = 64'hdd0ddd0d0000dd0d >> { Ng11504, Pg6313, Ng11505, Ng853, Ng11503, Pg5437 }; + assign n5695 = 64'hdd0ddd0d0000dd0d >> { Ng11501, Pg6313, Ng11502, Ng853, Ng11500, Pg5437 }; + assign n5696 = 64'hdd0ddd0d0000dd0d >> { Ng11498, Pg6313, Ng11499, Ng853, Ng11497, Pg5437 }; + assign n1448 = 8'h72 >> { Ng11507, n5693, n5698 }; + assign n5698 = 16'h888a >> { n5692, n5569_1, n5137, Pg6313 }; + assign n1443 = 8'h72 >> { Ng11506, n5693, n5700 }; + assign n5700 = 16'h888a >> { n5692, n5569_1, n5137, Pg5437 }; + assign n1438 = 8'h72 >> { Ng11505, n5702, n5691 }; + assign n5702 = 16'h6941 >> { n5703, n5696, Pg3229, n5695 }; + assign n5703 = 64'hdd0ddd0d0000dd0d >> { Ng11507, Pg6313, Ng11508, Ng853, Ng11506, Pg5437 }; + assign n1433 = 8'h72 >> { Ng11504, n5702, n5698 }; + assign n1428 = 8'h72 >> { Ng11503, n5702, n5700 }; + assign n1423 = 8'hd8 >> { Ng11502, n5707, n5691 }; + assign n5707 = 16'heb41 >> { n5695, n5696, Pg3229, n5694_1 }; + assign n1418 = 8'hd8 >> { Ng11501, n5707, n5698 }; + assign n1413_1 = 8'hd8 >> { Ng11500, n5707, n5700 }; + assign n1408 = 8'hd8 >> { Ng11499, n5711, n5691 }; + assign n5711 = 32'd3315647941 >> { n5694_1, n5695, n5703, n5696, Pg3229 }; + assign n1403_1 = 8'hd8 >> { Ng11498, n5711, n5698 }; + assign n1398 = 8'hd8 >> { Ng11497, n5711, n5700 }; + assign n6031 = 8'hd8 >> { Ng2519, n5715, Ng853 }; + assign n5715 = 32'd1431393749 >> { n5718, n5720, n5716, Ng2257, n5719_1 }; + assign n5716 = 4'h2 >> { n5717, n5324_1 }; + assign n5717 = 64'hdd0ddd0d0000dd0d >> { Ng2255, Pg6313, Ng2253, Ng853, Ng2254, Pg5437 }; + assign n5718 = 64'h0000077707770777 >> { Pg6313, Ng2507, Ng853, Ng2510, Pg5437, Ng2504 }; + assign n5719_1 = 64'h0000077707770777 >> { Pg6313, Ng2516, Ng853, Ng2519, Pg5437, Ng2513 }; + assign n5720 = 64'hdd0ddd0d0000dd0d >> { Ng2524, Pg6313, Ng2522, Ng853, Ng2523, Pg5437 }; + assign n6026 = 8'hd8 >> { Ng2516, n5715, Pg6313 }; + assign n6021 = 8'hd8 >> { Ng2513, n5715, Pg5437 }; + assign n6016 = 8'h72 >> { Ng2510, n5724_1, Ng853 }; + assign n5724_1 = 8'h72 >> { n5718, n5716, Ng2257 }; + assign n6011 = 8'h72 >> { Ng2507, n5724_1, Pg6313 }; + assign n6006 = 8'h72 >> { Ng2504, n5724_1, Pg5437 }; + assign n4529 = 8'hd8 >> { Ng1825, n5728, Ng853 }; + assign n5728 = 32'd1431393749 >> { n5731, n5733, n5729_1, Ng2257, n5732 }; + assign n5729_1 = 4'h2 >> { n5730, n5335 }; + assign n5730 = 64'hdd0ddd0d0000dd0d >> { Ng1561, Pg6313, Ng1559, Ng853, Ng1560, Pg5437 }; + assign n5731 = 64'h0000077707770777 >> { Pg6313, Ng1813, Ng853, Ng1816, Pg5437, Ng1810 }; + assign n5732 = 64'h0000077707770777 >> { Pg6313, Ng1822, Ng853, Ng1825, Pg5437, Ng1819 }; + assign n5733 = 64'hdd0ddd0d0000dd0d >> { Ng1830, Pg6313, Ng1828, Ng853, Ng1829, Pg5437 }; + assign n4524 = 8'hd8 >> { Ng1822, n5728, Pg6313 }; + assign n4519 = 8'hd8 >> { Ng1819, n5728, Pg5437 }; + assign n4514 = 8'h72 >> { Ng1816, n5737, Ng853 }; + assign n5737 = 8'h72 >> { n5731, n5729_1, Ng2257 }; + assign n4509 = 8'h72 >> { Ng1813, n5737, Pg6313 }; + assign n4504 = 8'h72 >> { Ng1810, n5737, Pg5437 }; + assign n3028 = 8'hd8 >> { Ng1131, n5741, Ng853 }; + assign n5741 = 32'd1431393749 >> { n5744_1, n5746, n5742, Ng2257, n5745 }; + assign n5742 = 4'h2 >> { n5743, n5349_1 }; + assign n5743 = 64'hdd0ddd0d0000dd0d >> { Ng867, Pg6313, Ng865, Ng853, Ng866, Pg5437 }; + assign n5744_1 = 64'h0000077707770777 >> { Pg6313, Ng1119, Ng853, Ng1122, Pg5437, Ng1116 }; + assign n5745 = 64'h0000077707770777 >> { Pg6313, Ng1128, Ng853, Ng1131, Pg5437, Ng1125 }; + assign n5746 = 64'hdd0ddd0d0000dd0d >> { Ng1136, Pg6313, Ng1134, Ng853, Ng1135, Pg5437 }; + assign n3023 = 8'hd8 >> { Ng1128, n5741, Pg6313 }; + assign n3018 = 8'hd8 >> { Ng1125, n5741, Pg5437 }; + assign n3013 = 8'h72 >> { Ng1122, n5750, Ng853 }; + assign n5750 = 8'h72 >> { n5744_1, n5742, Ng2257 }; + assign n3008 = 8'h72 >> { Ng1119, n5750, Pg6313 }; + assign n3003 = 8'h72 >> { Ng1116, n5750, Pg5437 }; + assign n1528_1 = 8'hd8 >> { Ng444, n5754_1, Ng853 }; + assign n5754_1 = 32'd1431393749 >> { n5757, n5759_1, n5755, Ng2257, n5758 }; + assign n5755 = 4'h2 >> { n5756, n5364_1 }; + assign n5756 = 64'hdd0ddd0d0000dd0d >> { Ng179, Pg6313, Ng177, Ng853, Ng178, Pg5437 }; + assign n5757 = 64'h0000077707770777 >> { Pg6313, Ng432, Ng853, Ng435, Pg5437, Ng429 }; + assign n5758 = 64'h0000077707770777 >> { Pg6313, Ng441, Ng853, Ng444, Pg5437, Ng438 }; + assign n5759_1 = 64'hdd0ddd0d0000dd0d >> { Ng449, Pg6313, Ng447, Ng853, Ng448, Pg5437 }; + assign n1523 = 8'hd8 >> { Ng441, n5754_1, Pg6313 }; + assign n1518 = 8'hd8 >> { Ng438, n5754_1, Pg5437 }; + assign n1513 = 8'h72 >> { Ng435, n5763, Ng853 }; + assign n5763 = 8'h72 >> { n5757, n5755, Ng2257 }; + assign n1508_1 = 8'h72 >> { Ng432, n5763, Pg6313 }; + assign n1503_1 = 8'h72 >> { Ng429, n5763, Pg5437 }; + assign n6643 = 8'hd8 >> { Ng2571, n5767, Ng1315 }; + assign n5767 = 8'h80 >> { n4575, n4577, Ng2584 }; + assign n6638 = 8'hd8 >> { Ng2568, n5767, Pg5648 }; + assign n6633 = 8'hd8 >> { Ng2565, n5767, Pg5629 }; + assign n6121 = 16'h70f8 >> { n5771, Ng2477, Ng853, Ng2257 }; + assign n5771 = 4'h8 >> { n4814, n4815_1 }; + assign n6116_1 = 16'h70f8 >> { n5771, Ng2479, Pg6313, Ng2257 }; + assign n6111 = 16'h70f8 >> { n5771, Ng2478, Pg5437, Ng2257 }; + assign n5141 = 8'hd8 >> { Ng1877, n5775, Ng1315 }; + assign n5775 = 8'h80 >> { n4571, n4573, Ng1890 }; + assign n5136 = 8'hd8 >> { Ng1874, n5775, Pg5648 }; + assign n5131 = 8'hd8 >> { Ng1871, n5775, Pg5629 }; + assign n4619 = 32'd1895364856 >> { n4922, n4916_1, Ng1783, Ng853, Ng2257 }; + assign n4614 = 32'd1895364856 >> { n4922, n4916_1, Ng1785, Pg6313, Ng2257 }; + assign n4609_1 = 32'd1895364856 >> { n4922, n4916_1, Ng1784, Pg5437, Ng2257 }; + assign n3640 = 8'hd8 >> { Ng1183, n5782, Ng1315 }; + assign n5782 = 8'h80 >> { n4567, n4569_1, Ng1196 }; + assign n3635 = 8'hd8 >> { Ng1180, n5782, Pg5648 }; + assign n3630 = 8'hd8 >> { Ng1177, n5782, Pg5629 }; + assign n3118 = 16'h70f8 >> { n5786, Ng1089, Ng853, Ng2257 }; + assign n5786 = 4'h8 >> { n5358, n5016_1 }; + assign n3113 = 16'h70f8 >> { n5786, Ng1091, Pg6313, Ng2257 }; + assign n3108 = 16'h70f8 >> { n5786, Ng1090, Pg5437, Ng2257 }; + assign n2140 = 8'hd8 >> { Ng496, n5790, Ng1315 }; + assign n5790 = 8'h80 >> { n4563, n4565, Ng510 }; + assign n2135 = 8'hd8 >> { Ng493, n5790, Pg5648 }; + assign n2130 = 8'hd8 >> { Ng490, n5790, Pg5629 }; + assign n1618 = 16'h70f8 >> { n5794_1, Ng402, Ng853, Ng2257 }; + assign n5794_1 = 4'h8 >> { n6689, n5116_1 }; + assign n1613_1 = 16'h70f8 >> { n5794_1, Ng404, Pg6313, Ng2257 }; + assign n1608 = 16'h70f8 >> { n5794_1, Ng403, Pg5437, Ng2257 }; + assign n830 = 8'hd8 >> { Ng3099, n1987, Ng1315 }; + assign n825 = 8'hd8 >> { Ng3098, n1987, Pg5648 }; + assign n820 = 16'he444 >> { Ng544, Ng8284, Ng3097, Pg5629 }; + assign n7175 = 8'h06 >> { Pg3234, Ng2993, Ng13475 }; + assign n6961_1 = 64'haaaaeaaaaaaa2aaa >> { n6694, Ng2733, Ng1315, Ng2612, Ng2599, Ng2808 }; + assign n5802 = 64'h0660066006600000 >> { n4600, Ng2766, Ng2707, n4592, Ng2753, n4601 }; + assign n5803 = 64'h0000066006600660 >> { n4600, Ng2766, n4597, Ng2720, Ng2746, n4599_1 }; + assign n5804_1 = 64'hdd0ddd0d0000dd0d >> { Ng2804, Pg5648, Ng2803, Pg5629, Ng2802, Ng1315 }; + assign n6956_1 = 64'haaaaeaaaaaaa2aaa >> { n6694, Ng2733, Pg5648, Ng2612, Ng2599, Ng2810 }; + assign n6951_1 = 64'haaaaeaaaaaaa2aaa >> { n6694, Ng2733, Pg5629, Ng2612, Ng2599, Ng2809 }; + assign n5889 = 4'h8 >> { n5569_1, n5808 }; + assign n5808 = 64'h0000000000000008 >> { Ng2888, Ng2912, Ng2920, Ng2917, Ng2924, Ng2883 }; + assign n5684 = 8'h72 >> { Ng2253, n5324_1, n5810 }; + assign n5810 = 4'h8 >> { n5889, Ng853 }; + assign n5679 = 8'h72 >> { Ng2255, n5324_1, n5812 }; + assign n5812 = 4'h8 >> { n5889, Pg6313 }; + assign n5674 = 8'h72 >> { Ng2254, n5324_1, n5814_1 }; + assign n5814_1 = 4'h8 >> { n5889, Pg5437 }; + assign n5669 = 8'h72 >> { Ng2250, Ng2165, n5810 }; + assign n5664 = 8'h72 >> { Ng2252, Ng2165, n5812 }; + assign n5659 = 8'h72 >> { Ng2251, Ng2165, n5814_1 }; + assign n5654 = 8'h72 >> { Ng2247, Ng2170, n5810 }; + assign n5649 = 8'h72 >> { Ng2249, Ng2170, n5812 }; + assign n5644 = 8'h72 >> { Ng2248, Ng2170, n5814_1 }; + assign n5639 = 64'h444444444444e444 >> { Ng2190, Ng2195, Ng2185, Ng2200, Ng2244, n5810 }; + assign n5634 = 64'h444444444444e444 >> { Ng2190, Ng2195, Ng2185, Ng2200, Ng2246, n5812 }; + assign n5629 = 64'h444444444444e444 >> { Ng2190, Ng2195, Ng2185, Ng2200, Ng2245, n5814_1 }; + assign n5459 = 64'haaaaeaaaaaaa2aaa >> { n6697, Ng2039, Ng1315, Ng1918, Ng1905, Ng2114 }; + assign n5825 = 64'h0660066006600000 >> { n4636, Ng2072, Ng2052, n4642_1, Ng2020, n4638 }; + assign n5826 = 64'h0000066006600660 >> { n4636, Ng2072, n4640, Ng2059, Ng2026, n4634 }; + assign n5827 = 64'hdd0ddd0d0000dd0d >> { Ng2110, Pg5648, Ng2109, Pg5629, Ng2108, Ng1315 }; + assign n5454 = 64'haaaaeaaaaaaa2aaa >> { n6697, Ng2039, Pg5648, Ng1918, Ng1905, Ng2116 }; + assign n5449 = 64'haaaaeaaaaaaa2aaa >> { n6697, Ng2039, Pg5629, Ng1918, Ng1905, Ng2115 }; + assign n4194 = 8'h72 >> { Ng1559, n5335, n5810 }; + assign n4189 = 8'h72 >> { Ng1561, n5335, n5812 }; + assign n4184 = 8'h72 >> { Ng1560, n5335, n5814_1 }; + assign n4179 = 8'h72 >> { Ng1556, Ng1471, n5810 }; + assign n4174 = 8'h72 >> { Ng1558, Ng1471, n5812 }; + assign n4169 = 8'h72 >> { Ng1557, Ng1471, n5814_1 }; + assign n4164 = 8'h72 >> { Ng1553, Ng1476, n5810 }; + assign n4159 = 8'h72 >> { Ng1555, Ng1476, n5812 }; + assign n4154 = 8'h72 >> { Ng1554, Ng1476, n5814_1 }; + assign n4149 = 64'h444444444444e444 >> { Ng1496, Ng1501, Ng1491, Ng1506, Ng1550, n5810 }; + assign n4144 = 64'h444444444444e444 >> { Ng1496, Ng1501, Ng1491, Ng1506, Ng1552, n5812 }; + assign n4139 = 64'h444444444444e444 >> { Ng1496, Ng1501, Ng1491, Ng1506, Ng1551, n5814_1 }; + assign n3969 = 64'haaaaeaaaaaaa2aaa >> { n5843, Ng1345, Ng1315, Ng1224, Ng1211, Ng1420 }; + assign n5843 = 8'h08 >> { n5844_1, n4685, n5849_1 }; + assign n5844_1 = 64'h0008080000808000 >> { n4679, n4684, Ng1365, Ng1326, n5845, n5847 }; + assign n5845 = 32'd35653760 >> { n4678_1, n4683, Ng1319, Ng1358, n5846 }; + assign n5846 = 16'h1428 >> { n4686, n4687_1, Ng1332, Ng1372 }; + assign n5847 = 32'd35653760 >> { n4676, n4682_1, Ng1346, Ng1378, n5848 }; + assign n5848 = 16'h1428 >> { n4675, n4677, Ng1352, Ng1339 }; + assign n5849_1 = 64'hdd0ddd0d0000dd0d >> { Ng1416, Pg5648, Ng1415, Pg5629, Ng1414, Ng1315 }; + assign n3964 = 64'haaaaeaaaaaaa2aaa >> { n5843, Ng1345, Pg5648, Ng1224, Ng1211, Ng1422 }; + assign n3959 = 64'haaaaeaaaaaaa2aaa >> { n5843, Ng1345, Pg5629, Ng1224, Ng1211, Ng1421 }; + assign n2693 = 8'h72 >> { Ng865, n5349_1, n5810 }; + assign n2688 = 8'h72 >> { Ng867, n5349_1, n5812 }; + assign n2683 = 8'h72 >> { Ng866, n5349_1, n5814_1 }; + assign n2678 = 8'h72 >> { Ng862, Ng785, n5810 }; + assign n2673 = 8'h72 >> { Ng864, Ng785, n5812 }; + assign n2668 = 8'h72 >> { Ng863, Ng785, n5814_1 }; + assign n2663 = 8'h72 >> { Ng859, Ng789, n5810 }; + assign n2658 = 8'h72 >> { Ng861, Ng789, n5812 }; + assign n2653 = 8'h72 >> { Ng860, Ng789, n5814_1 }; + assign n2648 = 64'h444444444444e444 >> { Ng805, Ng809, Ng801, Ng813, Ng856, n5810 }; + assign n2643 = 64'h444444444444e444 >> { Ng805, Ng809, Ng801, Ng813, Ng858, n5812 }; + assign n2638 = 64'h444444444444e444 >> { Ng805, Ng809, Ng801, Ng813, Ng857, n5814_1 }; + assign n2458 = 64'haaaaeaaaaaaa2aaa >> { n5865, Ng659, Ng1315, Ng538, Ng525, Ng734 }; + assign n5865 = 8'h08 >> { n5866, n4720, n5871 }; + assign n5866 = 64'h0008080000808000 >> { n4725, n4727, Ng692, Ng686, n5869_1, n5867 }; + assign n5867 = 32'd35653760 >> { n4722_1, n4716, Ng660, Ng653, n5868 }; + assign n5868 = 16'h1428 >> { n4715, n4726_1, Ng646, Ng679 }; + assign n5869_1 = 32'd35653760 >> { n4723, n4717, Ng640, Ng666, n5870 }; + assign n5870 = 16'h1428 >> { n4724, n4719, Ng672, Ng633 }; + assign n5871 = 64'hdd0ddd0d0000dd0d >> { Ng730, Pg5648, Ng729, Pg5629, Ng728, Ng1315 }; + assign n2453 = 64'haaaaeaaaaaaa2aaa >> { n5865, Ng659, Pg5648, Ng538, Ng525, Ng736 }; + assign n2448 = 64'haaaaeaaaaaaa2aaa >> { n5865, Ng659, Pg5629, Ng538, Ng525, Ng735 }; + assign n1193 = 8'h72 >> { Ng177, n5364_1, n5810 }; + assign n1188 = 8'h72 >> { Ng179, n5364_1, n5812 }; + assign n1183 = 8'h72 >> { Ng178, n5364_1, n5814_1 }; + assign n1178_1 = 8'h72 >> { Ng174, Ng97, n5810 }; + assign n1173 = 8'h72 >> { Ng176, Ng97, n5812 }; + assign n1168 = 8'h72 >> { Ng175, Ng97, n5814_1 }; + assign n1163 = 8'h72 >> { Ng171, Ng101, n5810 }; + assign n1158 = 8'h72 >> { Ng173, Ng101, n5812 }; + assign n1153 = 8'h72 >> { Ng172, Ng101, n5814_1 }; + assign n1148 = 64'h444444444444e444 >> { Ng117, Ng121, Ng113, Ng125, Ng168, n5810 }; + assign n1143 = 64'h444444444444e444 >> { Ng117, Ng121, Ng113, Ng125, Ng170, n5812 }; + assign n1138 = 64'h444444444444e444 >> { Ng117, Ng121, Ng113, Ng125, Ng169, n5814_1 }; + assign n6598 = 16'h444e >> { n5418, n4556, Ng2676, Ng1315 }; + assign n6593 = 8'hd8 >> { Ng2673, n5888, Pg5648 }; + assign n5888 = 4'h1 >> { n4556, n5418 }; + assign n6588 = 8'hd8 >> { Ng2670, n5888, Pg5629 }; + assign n6583 = 16'h444e >> { n5428, n4556, Ng2667, Ng1315 }; + assign n6578 = 8'hd8 >> { Ng2664, n5892, Pg5648 }; + assign n5892 = 4'h1 >> { n4556, n5428 }; + assign n6573 = 8'hd8 >> { Ng2661, n5892, Pg5629 }; + assign n6701 = 8'h72 >> { Ng2380, Ng2366, Pg3229 }; + assign n5839 = 16'h26a6 >> { Ng2257, n5569_1, Ng853, Ng2160 }; + assign n5096 = 16'h444e >> { n5452, n4556, Ng1982, Ng1315 }; + assign n5091 = 8'hd8 >> { Ng1979, n5898, Pg5648 }; + assign n5898 = 4'h1 >> { n4556, n5452 }; + assign n5086 = 8'hd8 >> { Ng1976, n5898, Pg5629 }; + assign n5081 = 16'h444e >> { n5456, n4556, Ng1973, Ng1315 }; + assign n5076 = 8'hd8 >> { Ng1970, n5902, Pg5648 }; + assign n5902 = 4'h1 >> { n4556, n5456 }; + assign n5071 = 8'hd8 >> { Ng1967, n5902, Pg5629 }; + assign n5199 = 8'h72 >> { Ng1686, Ng1672, Pg3229 }; + assign n4349 = 16'h26a6 >> { Ng2257, n5569_1, Ng853, Ng1466 }; + assign n3595 = 16'h444e >> { n5496, n4556, Ng1288, Ng1315 }; + assign n3590 = 8'hd8 >> { Ng1285, n5908, Pg5648 }; + assign n5908 = 4'h1 >> { n4556, n5496 }; + assign n3585 = 8'hd8 >> { Ng1282, n5908, Pg5629 }; + assign n3580 = 16'h444e >> { n5500, n4556, Ng1279, Ng1315 }; + assign n3575 = 8'hd8 >> { Ng1276, n5912, Pg5648 }; + assign n5912 = 4'h1 >> { n4556, n5500 }; + assign n3570 = 8'hd8 >> { Ng1273, n5912, Pg5629 }; + assign n3698 = 8'h72 >> { Ng992, Ng978, Pg3229 }; + assign n2848 = 16'h26a6 >> { Ng2257, n5569_1, Ng853, Ng780 }; + assign n2095 = 16'h444e >> { n5535, n4556, Ng602, Ng1315 }; + assign n2090 = 8'hd8 >> { Ng599, n5918, Pg5648 }; + assign n5918 = 4'h1 >> { n4556, n5535 }; + assign n2085 = 8'hd8 >> { Ng596, n5918, Pg5629 }; + assign n2080 = 16'h444e >> { n5539_1, n4556, Ng593, Ng1315 }; + assign n2075 = 8'hd8 >> { Ng590, n5922, Pg5648 }; + assign n5922 = 4'h1 >> { n4556, n5539_1 }; + assign n2070 = 8'hd8 >> { Ng587, n5922, Pg5629 }; + assign n2198 = 8'h72 >> { Ng305, Ng291, Pg3229 }; + assign n1348_1 = 16'h26a6 >> { Ng2257, n5569_1, Ng853, Ng92 }; + assign n6414 = 8'hd8 >> { Ng11593, n5568, Pg5437 }; + assign n6436 = 8'hd8 >> { Ng2554, n4822, Ng853 }; + assign n6431_1 = 8'hd8 >> { Ng2553, n4822, Pg6313 }; + assign n6426 = 8'hd8 >> { Ng2552, n4822, Pg5437 }; + assign n6464 = 8'hd8 >> { Ng11595, n4831, Ng853 }; + assign n6460_1 = 8'hd8 >> { Ng11594, n4831, Pg6313 }; + assign n6456 = 8'hd8 >> { Ng11598, n4831, Pg5437 }; + assign n6422_1 = 8'hd8 >> { Ng11597, n5568, Ng853 }; + assign n6418 = 8'hd8 >> { Ng11596, n5568, Pg6313 }; + assign n4912 = 8'hd8 >> { Ng11566, n5610, Pg5437 }; + assign n4934 = 8'hd8 >> { Ng1860, n5343, Ng853 }; + assign n4929 = 8'hd8 >> { Ng1859, n5343, Pg6313 }; + assign n4924_1 = 8'hd8 >> { Ng1858, n5343, Pg5437 }; + assign n4962 = 8'hd8 >> { Ng11568, n4932, Ng853 }; + assign n4958_1 = 8'hd8 >> { Ng11567, n4932, Pg6313 }; + assign n4954 = 8'hd8 >> { Ng11571, n4932, Pg5437 }; + assign n4920 = 8'hd8 >> { Ng11570, n5610, Ng853 }; + assign n4916 = 8'hd8 >> { Ng11569, n5610, Pg6313 }; + assign n3411 = 32'd1145324772 >> { n5011_1, n4988, n5009, Ng11539, Pg5437 }; + assign n3433 = 8'hd8 >> { Ng1166, n5357, Ng853 }; + assign n3428 = 8'hd8 >> { Ng1165, n5357, Pg6313 }; + assign n3423 = 8'hd8 >> { Ng1164, n5357, Pg5437 }; + assign n3461 = 8'hd8 >> { Ng11541, n5031_1, Ng853 }; + assign n3457 = 8'hd8 >> { Ng11540, n5031_1, Pg6313 }; + assign n3453 = 8'hd8 >> { Ng11544, n5031_1, Pg5437 }; + assign n3419 = 32'd1145324772 >> { n5011_1, n4988, n5009, Ng11543, Ng853 }; + assign n3415 = 32'd1145324772 >> { n5011_1, n4988, n5009, Ng11542, Pg6313 }; + assign n1911 = 8'hd8 >> { Ng11512, n5692, Pg5437 }; + assign n1933 = 8'hd8 >> { Ng479, n5373, Ng853 }; + assign n1928 = 8'hd8 >> { Ng478, n5373, Pg6313 }; + assign n1923 = 8'hd8 >> { Ng477, n5373, Pg5437 }; + assign n1961 = 8'hd8 >> { Ng11514, n5137, Ng853 }; + assign n1957 = 8'hd8 >> { Ng11513, n5137, Pg6313 }; + assign n1953 = 8'hd8 >> { Ng11517, n5137, Pg5437 }; + assign n1919 = 8'hd8 >> { Ng11516, n5692, Ng853 }; + assign n1915 = 8'hd8 >> { Ng11515, n5692, Pg6313 }; + assign n6409 = 8'h72 >> { Ng2563, n5719_1, Ng853 }; + assign n6404 = 8'h72 >> { Ng2562, n5719_1, Pg6313 }; + assign n6399 = 8'h72 >> { Ng2561, n5719_1, Pg5437 }; + assign n6451 = 8'h72 >> { Ng2539, n6206, Ng853 }; + assign n6446 = 8'h72 >> { Ng2559, n6206, Pg6313 }; + assign n6441 = 8'h72 >> { Ng2555, n6206, Pg5437 }; + assign n5624 = 16'hf870 >> { n4778_1, Ng2238, Ng853, Ng2257 }; + assign n5619 = 16'hf870 >> { n4778_1, Ng2240, Pg6313, Ng2257 }; + assign n5614 = 16'hf870 >> { n4778_1, Ng2239, Pg5437, Ng2257 }; + assign n5609 = 16'hf870 >> { n4762_1, Ng2235, Ng853, Ng2257 }; + assign n5604 = 16'hf870 >> { n4762_1, Ng2237, Pg6313, Ng2257 }; + assign n5599 = 16'hf870 >> { n4762_1, Ng2236, Pg5437, Ng2257 }; + assign n5594 = 16'h70f8 >> { Ng2200, Ng2232, Ng853, Ng2257 }; + assign n5589 = 16'h70f8 >> { Ng2200, Ng2234, Pg6313, Ng2257 }; + assign n5584 = 16'h70f8 >> { Ng2200, Ng2233, Pg5437, Ng2257 }; + assign n5579 = 16'h70f8 >> { Ng2195, Ng2229, Ng853, Ng2257 }; + assign n5574 = 16'h70f8 >> { Ng2195, Ng2231, Pg6313, Ng2257 }; + assign n5569 = 16'h70f8 >> { Ng2195, Ng2230, Pg5437, Ng2257 }; + assign n5564 = 16'h70f8 >> { Ng2190, Ng2226, Ng853, Ng2257 }; + assign n5559 = 16'h70f8 >> { Ng2190, Ng2228, Pg6313, Ng2257 }; + assign n5554 = 16'h70f8 >> { Ng2190, Ng2227, Pg5437, Ng2257 }; + assign n5549 = 16'h70f8 >> { Ng2185, Ng2223, Ng853, Ng2257 }; + assign n5544 = 16'h70f8 >> { Ng2185, Ng2225, Pg6313, Ng2257 }; + assign n5539 = 16'h70f8 >> { Ng2185, Ng2224, Pg5437, Ng2257 }; + assign n5534 = 16'h70f8 >> { Ng2180, Ng2220, Ng853, Ng2257 }; + assign n5529 = 16'h70f8 >> { Ng2180, Ng2222, Pg6313, Ng2257 }; + assign n5524 = 16'h70f8 >> { Ng2180, Ng2221, Pg5437, Ng2257 }; + assign n5519 = 16'h70f8 >> { Ng2175, Ng2217, Ng853, Ng2257 }; + assign n5514 = 16'h70f8 >> { Ng2175, Ng2219, Pg6313, Ng2257 }; + assign n5509 = 16'h70f8 >> { Ng2175, Ng2218, Pg5437, Ng2257 }; + assign n5504 = 16'h70f8 >> { Ng2170, Ng2208, Ng853, Ng2257 }; + assign n5499 = 16'h70f8 >> { Ng2170, Ng2210, Pg6313, Ng2257 }; + assign n5494 = 16'h70f8 >> { Ng2170, Ng2209, Pg5437, Ng2257 }; + assign n5489 = 16'h70f8 >> { Ng2165, Ng2205, Ng853, Ng2257 }; + assign n5484 = 16'h70f8 >> { Ng2165, Ng2207, Pg6313, Ng2257 }; + assign n5479 = 16'h70f8 >> { Ng2165, Ng2206, Pg5437, Ng2257 }; + assign n4907 = 8'h72 >> { Ng1869, n5732, Ng853 }; + assign n4902 = 8'h72 >> { Ng1868, n5732, Pg6313 }; + assign n4897 = 8'h72 >> { Ng1867, n5732, Pg5437 }; + assign n4949 = 8'h72 >> { Ng1845, n4704, Ng853 }; + assign n4944 = 8'h72 >> { Ng1865, n4704, Pg6313 }; + assign n4939 = 8'h72 >> { Ng1861, n4704, Pg5437 }; + assign n4134 = 16'hf870 >> { n4864, Ng1544, Ng853, Ng2257 }; + assign n4129 = 16'hf870 >> { n4864, Ng1546, Pg6313, Ng2257 }; + assign n4124 = 16'hf870 >> { n4864, Ng1545, Pg5437, Ng2257 }; + assign n4119 = 16'hf870 >> { n4875, Ng1541, Ng853, Ng2257 }; + assign n4114 = 16'hf870 >> { n4875, Ng1543, Pg6313, Ng2257 }; + assign n4109 = 16'hf870 >> { n4875, Ng1542, Pg5437, Ng2257 }; + assign n4104 = 16'h70f8 >> { Ng1506, Ng1538, Ng853, Ng2257 }; + assign n4099 = 16'h70f8 >> { Ng1506, Ng1540, Pg6313, Ng2257 }; + assign n4094 = 16'h70f8 >> { Ng1506, Ng1539, Pg5437, Ng2257 }; + assign n4089 = 16'h70f8 >> { Ng1501, Ng1535, Ng853, Ng2257 }; + assign n4084 = 16'h70f8 >> { Ng1501, Ng1537, Pg6313, Ng2257 }; + assign n4079 = 16'h70f8 >> { Ng1501, Ng1536, Pg5437, Ng2257 }; + assign n4074 = 16'h70f8 >> { Ng1496, Ng1532, Ng853, Ng2257 }; + assign n4069 = 16'h70f8 >> { Ng1496, Ng1534, Pg6313, Ng2257 }; + assign n4064 = 16'h70f8 >> { Ng1496, Ng1533, Pg5437, Ng2257 }; + assign n4059 = 16'h70f8 >> { Ng1491, Ng1529, Ng853, Ng2257 }; + assign n4054 = 16'h70f8 >> { Ng1491, Ng1531, Pg6313, Ng2257 }; + assign n4049 = 16'h70f8 >> { Ng1491, Ng1530, Pg5437, Ng2257 }; + assign n4044 = 16'h70f8 >> { Ng1486, Ng1526, Ng853, Ng2257 }; + assign n4039 = 16'h70f8 >> { Ng1486, Ng1528, Pg6313, Ng2257 }; + assign n4034 = 16'h70f8 >> { Ng1486, Ng1527, Pg5437, Ng2257 }; + assign n4029 = 16'h70f8 >> { Ng1481, Ng1523, Ng853, Ng2257 }; + assign n4024 = 16'h70f8 >> { Ng1481, Ng1525, Pg6313, Ng2257 }; + assign n4019 = 16'h70f8 >> { Ng1481, Ng1524, Pg5437, Ng2257 }; + assign n4014 = 16'h70f8 >> { Ng1476, Ng1514, Ng853, Ng2257 }; + assign n4009 = 16'h70f8 >> { Ng1476, Ng1516, Pg6313, Ng2257 }; + assign n4004 = 16'h70f8 >> { Ng1476, Ng1515, Pg5437, Ng2257 }; + assign n3999 = 16'h70f8 >> { Ng1471, Ng1511, Ng853, Ng2257 }; + assign n3994 = 16'h70f8 >> { Ng1471, Ng1513, Pg6313, Ng2257 }; + assign n3989 = 16'h70f8 >> { Ng1471, Ng1512, Pg5437, Ng2257 }; + assign n3406 = 8'h72 >> { Ng1175, n5745, Ng853 }; + assign n3401 = 8'h72 >> { Ng1174, n5745, Pg6313 }; + assign n3396 = 8'h72 >> { Ng1173, n5745, Pg5437 }; + assign n3448 = 8'h72 >> { Ng1151, n3203, Ng853 }; + assign n3443 = 8'h72 >> { Ng1171, n3203, Pg6313 }; + assign n3438 = 8'h72 >> { Ng1167, n3203, Pg5437 }; + assign n2633 = 16'hf870 >> { n4968, Ng850, Ng853, Ng2257 }; + assign n2628 = 16'hf870 >> { n4968, Ng852, Pg6313, Ng2257 }; + assign n2623 = 16'hf870 >> { n4968, Ng851, Pg5437, Ng2257 }; + assign n2618 = 16'hf870 >> { n4984, Ng847, Ng853, Ng2257 }; + assign n2613 = 16'hf870 >> { n4984, Ng849, Pg6313, Ng2257 }; + assign n2608 = 16'hf870 >> { n4984, Ng848, Pg5437, Ng2257 }; + assign n2603 = 16'h70f8 >> { Ng813, Ng844, Ng853, Ng2257 }; + assign n2598 = 16'h70f8 >> { Ng813, Ng846, Pg6313, Ng2257 }; + assign n2593 = 16'h70f8 >> { Ng813, Ng845, Pg5437, Ng2257 }; + assign n2588 = 16'h70f8 >> { Ng809, Ng841, Ng853, Ng2257 }; + assign n2583 = 16'h70f8 >> { Ng809, Ng843, Pg6313, Ng2257 }; + assign n2578 = 16'h70f8 >> { Ng809, Ng842, Pg5437, Ng2257 }; + assign n2573 = 16'h70f8 >> { Ng805, Ng838, Ng853, Ng2257 }; + assign n2568 = 16'h70f8 >> { Ng805, Ng840, Pg6313, Ng2257 }; + assign n2563 = 16'h70f8 >> { Ng805, Ng839, Pg5437, Ng2257 }; + assign n2558 = 16'h70f8 >> { Ng801, Ng835, Ng853, Ng2257 }; + assign n2553 = 16'h70f8 >> { Ng801, Ng837, Pg6313, Ng2257 }; + assign n2548 = 16'h70f8 >> { Ng801, Ng836, Pg5437, Ng2257 }; + assign n2543 = 16'h70f8 >> { Ng797, Ng832, Ng853, Ng2257 }; + assign n2538 = 16'h70f8 >> { Ng797, Ng834, Pg6313, Ng2257 }; + assign n2533 = 16'h70f8 >> { Ng797, Ng833, Pg5437, Ng2257 }; + assign n2528 = 16'h70f8 >> { Ng793, Ng829, Ng853, Ng2257 }; + assign n2523 = 16'h70f8 >> { Ng793, Ng831, Pg6313, Ng2257 }; + assign n2518 = 16'h70f8 >> { Ng793, Ng830, Pg5437, Ng2257 }; + assign n2513 = 16'h70f8 >> { Ng789, Ng820, Ng853, Ng2257 }; + assign n2508 = 16'h70f8 >> { Ng789, Ng822, Pg6313, Ng2257 }; + assign n2503 = 16'h70f8 >> { Ng789, Ng821, Pg5437, Ng2257 }; + assign n2498 = 16'h70f8 >> { Ng785, Ng817, Ng853, Ng2257 }; + assign n2493 = 16'h70f8 >> { Ng785, Ng819, Pg6313, Ng2257 }; + assign n2488 = 16'h70f8 >> { Ng785, Ng818, Pg5437, Ng2257 }; + assign n1906 = 8'h72 >> { Ng488, n5758, Ng853 }; + assign n1901 = 8'h72 >> { Ng487, n5758, Pg6313 }; + assign n1896 = 8'h72 >> { Ng486, n5758, Pg5437 }; + assign n1948 = 8'h72 >> { Ng464, n1703, Ng853 }; + assign n1943 = 8'h72 >> { Ng484, n1703, Pg6313 }; + assign n1938 = 8'h72 >> { Ng480, n1703, Pg5437 }; + assign n1133 = 16'hf870 >> { n5065, Ng162, Ng853, Ng2257 }; + assign n1128 = 16'hf870 >> { n5065, Ng164, Pg6313, Ng2257 }; + assign n1123 = 16'hf870 >> { n5065, Ng163, Pg5437, Ng2257 }; + assign n1118 = 16'hf870 >> { n5078, Ng159, Ng853, Ng2257 }; + assign n1113 = 16'hf870 >> { n5078, Ng161, Pg6313, Ng2257 }; + assign n1108_1 = 16'hf870 >> { n5078, Ng160, Pg5437, Ng2257 }; + assign n1103 = 16'h70f8 >> { Ng125, Ng156, Ng853, Ng2257 }; + assign n1098 = 16'h70f8 >> { Ng125, Ng158, Pg6313, Ng2257 }; + assign n1093 = 16'h70f8 >> { Ng125, Ng157, Pg5437, Ng2257 }; + assign n1088 = 16'h70f8 >> { Ng121, Ng153, Ng853, Ng2257 }; + assign n1083 = 16'h70f8 >> { Ng121, Ng155, Pg6313, Ng2257 }; + assign n1078 = 16'h70f8 >> { Ng121, Ng154, Pg5437, Ng2257 }; + assign n1073 = 16'h70f8 >> { Ng117, Ng150, Ng853, Ng2257 }; + assign n1068 = 16'h70f8 >> { Ng117, Ng152, Pg6313, Ng2257 }; + assign n1063_1 = 16'h70f8 >> { Ng117, Ng151, Pg5437, Ng2257 }; + assign n1058 = 16'h70f8 >> { Ng113, Ng147, Ng853, Ng2257 }; + assign n1053_1 = 16'h70f8 >> { Ng113, Ng149, Pg6313, Ng2257 }; + assign n1048_1 = 16'h70f8 >> { Ng113, Ng148, Pg5437, Ng2257 }; + assign n1043 = 16'h70f8 >> { Ng109, Ng144, Ng853, Ng2257 }; + assign n1038 = 16'h70f8 >> { Ng109, Ng146, Pg6313, Ng2257 }; + assign n1033_1 = 16'h70f8 >> { Ng109, Ng145, Pg5437, Ng2257 }; + assign n1028 = 16'h70f8 >> { Ng105, Ng141, Ng853, Ng2257 }; + assign n1023 = 16'h70f8 >> { Ng105, Ng143, Pg6313, Ng2257 }; + assign n1018_1 = 16'h70f8 >> { Ng105, Ng142, Pg5437, Ng2257 }; + assign n1013 = 16'h70f8 >> { Ng101, Ng132, Ng853, Ng2257 }; + assign n1008 = 16'h70f8 >> { Ng101, Ng134, Pg6313, Ng2257 }; + assign n1003_1 = 16'h70f8 >> { Ng101, Ng133, Pg5437, Ng2257 }; + assign n998_1 = 16'h70f8 >> { Ng97, Ng129, Ng853, Ng2257 }; + assign n993 = 16'h70f8 >> { Ng97, Ng131, Pg6313, Ng2257 }; + assign n988 = 16'h70f8 >> { Ng97, Ng130, Pg5437, Ng2257 }; + assign n371 = 32'd4005446676 >> { Pg8096, Pg3231, Ng3139, n6107, Ng2879 }; + assign n6107 = 32'd2523490710 >> { n6108, Ng2953, Ng2947, Ng2944, Ng2941 }; + assign n6108 = 16'h9669 >> { Ng2959, Ng2956, Ng2938, Ng2935 }; + assign n755 = 32'd3715991592 >> { Ng13455, Pg3231, Ng3139, n6110, Ng2879 }; + assign n6110 = 32'd2523490710 >> { n6111_1, Ng2978, Ng2975, Ng2972, Ng2969 }; + assign n6111_1 = 16'h9669 >> { Ng2874, Ng2981, Ng2966, Ng2963 }; + assign n638 = 32'd3715991592 >> { Ng13439, Pg3231, Ng3139, n6107, Ng2879 }; + assign n382 = 32'd4005446676 >> { Pg7519, Pg3231, Ng3139, n6110, Ng2879 }; + assign n6946_1 = 16'hf870 >> { n4576, Ng2805, Ng1315, Ng2704 }; + assign n6941_1 = 8'hd8 >> { Ng2807, n4576, n6116 }; + assign n6116 = 4'h8 >> { Pg5648, Ng2704 }; + assign n6936_1 = 16'hf870 >> { n4576, Ng2806, Pg5629, Ng2704 }; + assign n6931_1 = 16'hf870 >> { n4577, Ng2802, Ng1315, Ng2704 }; + assign n6926_1 = 8'hd8 >> { Ng2804, n4577, n6116 }; + assign n6921 = 16'hf870 >> { n4577, Ng2803, Pg5629, Ng2704 }; + assign n6916 = 64'haaaa2aaaaaaaeaaa >> { Ng2766, Ng2733, Ng1315, Ng2612, Ng2599, Ng2799 }; + assign n6911 = 64'haaaa2aaaaaaaeaaa >> { Ng2766, Ng2733, Pg5648, Ng2612, Ng2599, Ng2801 }; + assign n6906 = 64'haaaa2aaaaaaaeaaa >> { Ng2766, Ng2733, Pg5629, Ng2612, Ng2599, Ng2800 }; + assign n6901 = 64'haaaa2aaaaaaaeaaa >> { Ng2760, Ng2733, Ng1315, Ng2612, Ng2599, Ng2796 }; + assign n6896 = 64'haaaa2aaaaaaaeaaa >> { Ng2760, Ng2733, Pg5648, Ng2612, Ng2599, Ng2798 }; + assign n6891 = 64'haaaa2aaaaaaaeaaa >> { Ng2760, Ng2733, Pg5629, Ng2612, Ng2599, Ng2797 }; + assign n6886 = 64'haaaa2aaaaaaaeaaa >> { Ng2753, Ng2733, Ng1315, Ng2612, Ng2599, Ng2793 }; + assign n6881 = 64'haaaa2aaaaaaaeaaa >> { Ng2753, Ng2733, Pg5648, Ng2612, Ng2599, Ng2795 }; + assign n6876 = 64'haaaa2aaaaaaaeaaa >> { Ng2753, Ng2733, Pg5629, Ng2612, Ng2599, Ng2794 }; + assign n6871 = 64'haaaa2aaaaaaaeaaa >> { Ng2740, Ng2733, Ng1315, Ng2612, Ng2599, Ng2790 }; + assign n6866 = 64'haaaa2aaaaaaaeaaa >> { Ng2740, Ng2733, Pg5648, Ng2612, Ng2599, Ng2792 }; + assign n6861 = 64'haaaa2aaaaaaaeaaa >> { Ng2740, Ng2733, Pg5629, Ng2612, Ng2599, Ng2791 }; + assign n6856 = 64'haaaa2aaaaaaaeaaa >> { Ng2746, Ng2733, Ng1315, Ng2612, Ng2599, Ng2787 }; + assign n6851 = 64'haaaa2aaaaaaaeaaa >> { Ng2746, Ng2733, Pg5648, Ng2612, Ng2599, Ng2789 }; + assign n6846 = 64'haaaa2aaaaaaaeaaa >> { Ng2746, Ng2733, Pg5629, Ng2612, Ng2599, Ng2788 }; + assign n6841 = 64'haaaa2aaaaaaaeaaa >> { Ng2734, Ng2733, Ng1315, Ng2612, Ng2599, Ng2784 }; + assign n6836 = 64'haaaa2aaaaaaaeaaa >> { Ng2734, Ng2733, Pg5648, Ng2612, Ng2599, Ng2786 }; + assign n6831 = 64'haaaa2aaaaaaaeaaa >> { Ng2734, Ng2733, Pg5629, Ng2612, Ng2599, Ng2785 }; + assign n6826 = 64'haaaa2aaaaaaaeaaa >> { Ng2720, Ng2733, Ng1315, Ng2612, Ng2599, Ng2781 }; + assign n6821 = 64'haaaa2aaaaaaaeaaa >> { Ng2720, Ng2733, Pg5648, Ng2612, Ng2599, Ng2783 }; + assign n6816 = 64'haaaa2aaaaaaaeaaa >> { Ng2720, Ng2733, Pg5629, Ng2612, Ng2599, Ng2782 }; + assign n6811 = 64'haaaa2aaaaaaaeaaa >> { Ng2727, Ng2733, Ng1315, Ng2612, Ng2599, Ng2778 }; + assign n6806 = 64'haaaa2aaaaaaaeaaa >> { Ng2727, Ng2733, Pg5648, Ng2612, Ng2599, Ng2780 }; + assign n6801 = 64'haaaa2aaaaaaaeaaa >> { Ng2727, Ng2733, Pg5629, Ng2612, Ng2599, Ng2779 }; + assign n6796 = 64'haaaa2aaaaaaaeaaa >> { Ng2707, Ng2733, Ng1315, Ng2612, Ng2599, Ng2775 }; + assign n6791 = 64'haaaa2aaaaaaaeaaa >> { Ng2707, Ng2733, Pg5648, Ng2612, Ng2599, Ng2777 }; + assign n6786 = 64'haaaa2aaaaaaaeaaa >> { Ng2707, Ng2733, Pg5629, Ng2612, Ng2599, Ng2776 }; + assign n6781 = 64'haaaa2aaaaaaaeaaa >> { Ng2714, Ng2733, Ng1315, Ng2612, Ng2599, Ng2772 }; + assign n6776 = 64'haaaa2aaaaaaaeaaa >> { Ng2714, Ng2733, Pg5648, Ng2612, Ng2599, Ng2774 }; + assign n6771 = 64'haaaa2aaaaaaaeaaa >> { Ng2714, Ng2733, Pg5629, Ng2612, Ng2599, Ng2773 }; + assign n5444 = 16'hf870 >> { n4572, Ng2111, Ng1315, Ng2010 }; + assign n5439 = 8'hd8 >> { Ng2113, n4572, n6153_1 }; + assign n6153_1 = 4'h8 >> { Pg5648, Ng2010 }; + assign n5434 = 16'hf870 >> { n4572, Ng2112, Pg5629, Ng2010 }; + assign n5429 = 16'hf870 >> { n4573, Ng2108, Ng1315, Ng2010 }; + assign n5424 = 8'hd8 >> { Ng2110, n4573, n6153_1 }; + assign n5419 = 16'hf870 >> { n4573, Ng2109, Pg5629, Ng2010 }; + assign n5414 = 64'haaaa2aaaaaaaeaaa >> { Ng2072, Ng2039, Ng1315, Ng1918, Ng1905, Ng2105 }; + assign n5409 = 64'haaaa2aaaaaaaeaaa >> { Ng2072, Ng2039, Pg5648, Ng1918, Ng1905, Ng2107 }; + assign n5404 = 64'haaaa2aaaaaaaeaaa >> { Ng2072, Ng2039, Pg5629, Ng1918, Ng1905, Ng2106 }; + assign n5399 = 64'haaaa2aaaaaaaeaaa >> { Ng2066, Ng2039, Ng1315, Ng1918, Ng1905, Ng2102 }; + assign n5394 = 64'haaaa2aaaaaaaeaaa >> { Ng2066, Ng2039, Pg5648, Ng1918, Ng1905, Ng2104 }; + assign n5389 = 64'haaaa2aaaaaaaeaaa >> { Ng2066, Ng2039, Pg5629, Ng1918, Ng1905, Ng2103 }; + assign n5384 = 64'haaaa2aaaaaaaeaaa >> { Ng2059, Ng2039, Ng1315, Ng1918, Ng1905, Ng2099 }; + assign n5379 = 64'haaaa2aaaaaaaeaaa >> { Ng2059, Ng2039, Pg5648, Ng1918, Ng1905, Ng2101 }; + assign n5374 = 64'haaaa2aaaaaaaeaaa >> { Ng2059, Ng2039, Pg5629, Ng1918, Ng1905, Ng2100 }; + assign n5369 = 64'haaaa2aaaaaaaeaaa >> { Ng2046, Ng2039, Ng1315, Ng1918, Ng1905, Ng2096 }; + assign n5364 = 64'haaaa2aaaaaaaeaaa >> { Ng2046, Ng2039, Pg5648, Ng1918, Ng1905, Ng2098 }; + assign n5359 = 64'haaaa2aaaaaaaeaaa >> { Ng2046, Ng2039, Pg5629, Ng1918, Ng1905, Ng2097 }; + assign n5354 = 64'haaaa2aaaaaaaeaaa >> { Ng2052, Ng2039, Ng1315, Ng1918, Ng1905, Ng2093 }; + assign n5349 = 64'haaaa2aaaaaaaeaaa >> { Ng2052, Ng2039, Pg5648, Ng1918, Ng1905, Ng2095 }; + assign n5344 = 64'haaaa2aaaaaaaeaaa >> { Ng2052, Ng2039, Pg5629, Ng1918, Ng1905, Ng2094 }; + assign n5339 = 64'haaaa2aaaaaaaeaaa >> { Ng2040, Ng2039, Ng1315, Ng1918, Ng1905, Ng2090 }; + assign n5334 = 64'haaaa2aaaaaaaeaaa >> { Ng2040, Ng2039, Pg5648, Ng1918, Ng1905, Ng2092 }; + assign n5329 = 64'haaaa2aaaaaaaeaaa >> { Ng2040, Ng2039, Pg5629, Ng1918, Ng1905, Ng2091 }; + assign n5324 = 64'haaaa2aaaaaaaeaaa >> { Ng2026, Ng2039, Ng1315, Ng1918, Ng1905, Ng2087 }; + assign n5319 = 64'haaaa2aaaaaaaeaaa >> { Ng2026, Ng2039, Pg5648, Ng1918, Ng1905, Ng2089 }; + assign n5314 = 64'haaaa2aaaaaaaeaaa >> { Ng2026, Ng2039, Pg5629, Ng1918, Ng1905, Ng2088 }; + assign n5309 = 64'haaaa2aaaaaaaeaaa >> { Ng2033, Ng2039, Ng1315, Ng1918, Ng1905, Ng2084 }; + assign n5304 = 64'haaaa2aaaaaaaeaaa >> { Ng2033, Ng2039, Pg5648, Ng1918, Ng1905, Ng2086 }; + assign n5299 = 64'haaaa2aaaaaaaeaaa >> { Ng2033, Ng2039, Pg5629, Ng1918, Ng1905, Ng2085 }; + assign n5294 = 64'haaaa2aaaaaaaeaaa >> { Ng2013, Ng2039, Ng1315, Ng1918, Ng1905, Ng2081 }; + assign n5289 = 64'haaaa2aaaaaaaeaaa >> { Ng2013, Ng2039, Pg5648, Ng1918, Ng1905, Ng2083 }; + assign n5284 = 64'haaaa2aaaaaaaeaaa >> { Ng2013, Ng2039, Pg5629, Ng1918, Ng1905, Ng2082 }; + assign n5279 = 64'haaaa2aaaaaaaeaaa >> { Ng2020, Ng2039, Ng1315, Ng1918, Ng1905, Ng2078 }; + assign n5274 = 64'haaaa2aaaaaaaeaaa >> { Ng2020, Ng2039, Pg5648, Ng1918, Ng1905, Ng2080 }; + assign n5269 = 64'haaaa2aaaaaaaeaaa >> { Ng2020, Ng2039, Pg5629, Ng1918, Ng1905, Ng2079 }; + assign n3954 = 16'hf870 >> { n4568, Ng1417, Ng1315, Ng1316 }; + assign n3949 = 8'hd8 >> { Ng1419, n4568, n6190 }; + assign n6190 = 4'h8 >> { Pg5648, Ng1316 }; + assign n3944 = 16'hf870 >> { n4568, Ng1418, Pg5629, Ng1316 }; + assign n3939 = 16'hf870 >> { n4569_1, Ng1414, Ng1315, Ng1316 }; + assign n3934 = 8'hd8 >> { Ng1416, n4569_1, n6190 }; + assign n3929 = 16'hf870 >> { n4569_1, Ng1415, Pg5629, Ng1316 }; + assign n3924 = 64'haaaa2aaaaaaaeaaa >> { Ng1378, Ng1345, Ng1315, Ng1224, Ng1211, Ng1411 }; + assign n3919 = 64'haaaa2aaaaaaaeaaa >> { Ng1378, Ng1345, Pg5648, Ng1224, Ng1211, Ng1413 }; + assign n3914 = 64'haaaa2aaaaaaaeaaa >> { Ng1378, Ng1345, Pg5629, Ng1224, Ng1211, Ng1412 }; + assign n3909 = 64'haaaa2aaaaaaaeaaa >> { Ng1372, Ng1345, Ng1315, Ng1224, Ng1211, Ng1408 }; + assign n3904 = 64'haaaa2aaaaaaaeaaa >> { Ng1372, Ng1345, Pg5648, Ng1224, Ng1211, Ng1410 }; + assign n3899 = 64'haaaa2aaaaaaaeaaa >> { Ng1372, Ng1345, Pg5629, Ng1224, Ng1211, Ng1409 }; + assign n3894 = 64'haaaa2aaaaaaaeaaa >> { Ng1365, Ng1345, Ng1315, Ng1224, Ng1211, Ng1405 }; + assign n3889 = 64'haaaa2aaaaaaaeaaa >> { Ng1365, Ng1345, Pg5648, Ng1224, Ng1211, Ng1407 }; + assign n3884 = 64'haaaa2aaaaaaaeaaa >> { Ng1365, Ng1345, Pg5629, Ng1224, Ng1211, Ng1406 }; + assign n3879 = 64'haaaa2aaaaaaaeaaa >> { Ng1352, Ng1345, Ng1315, Ng1224, Ng1211, Ng1402 }; + assign n3874 = 64'haaaa2aaaaaaaeaaa >> { Ng1352, Ng1345, Pg5648, Ng1224, Ng1211, Ng1404 }; + assign n3869 = 64'haaaa2aaaaaaaeaaa >> { Ng1352, Ng1345, Pg5629, Ng1224, Ng1211, Ng1403 }; + assign n3864 = 64'haaaa2aaaaaaaeaaa >> { Ng1358, Ng1345, Ng1315, Ng1224, Ng1211, Ng1399 }; + assign n3859 = 64'haaaa2aaaaaaaeaaa >> { Ng1358, Ng1345, Pg5648, Ng1224, Ng1211, Ng1401 }; + assign n3854 = 64'haaaa2aaaaaaaeaaa >> { Ng1358, Ng1345, Pg5629, Ng1224, Ng1211, Ng1400 }; + assign n3849 = 64'haaaa2aaaaaaaeaaa >> { Ng1346, Ng1345, Ng1315, Ng1224, Ng1211, Ng1396 }; + assign n3844 = 64'haaaa2aaaaaaaeaaa >> { Ng1346, Ng1345, Pg5648, Ng1224, Ng1211, Ng1398 }; + assign n3839 = 64'haaaa2aaaaaaaeaaa >> { Ng1346, Ng1345, Pg5629, Ng1224, Ng1211, Ng1397 }; + assign n3834 = 64'haaaa2aaaaaaaeaaa >> { Ng1332, Ng1345, Ng1315, Ng1224, Ng1211, Ng1393 }; + assign n3829 = 64'haaaa2aaaaaaaeaaa >> { Ng1332, Ng1345, Pg5648, Ng1224, Ng1211, Ng1395 }; + assign n3824 = 64'haaaa2aaaaaaaeaaa >> { Ng1332, Ng1345, Pg5629, Ng1224, Ng1211, Ng1394 }; + assign n3819 = 64'haaaa2aaaaaaaeaaa >> { Ng1339, Ng1345, Ng1315, Ng1224, Ng1211, Ng1390 }; + assign n3814 = 64'haaaa2aaaaaaaeaaa >> { Ng1339, Ng1345, Pg5648, Ng1224, Ng1211, Ng1392 }; + assign n3809 = 64'haaaa2aaaaaaaeaaa >> { Ng1339, Ng1345, Pg5629, Ng1224, Ng1211, Ng1391 }; + assign n3804 = 64'haaaa2aaaaaaaeaaa >> { Ng1319, Ng1345, Ng1315, Ng1224, Ng1211, Ng1387 }; + assign n3799 = 64'haaaa2aaaaaaaeaaa >> { Ng1319, Ng1345, Pg5648, Ng1224, Ng1211, Ng1389 }; + assign n3794 = 64'haaaa2aaaaaaaeaaa >> { Ng1319, Ng1345, Pg5629, Ng1224, Ng1211, Ng1388 }; + assign n3789 = 64'haaaa2aaaaaaaeaaa >> { Ng1326, Ng1345, Ng1315, Ng1224, Ng1211, Ng1384 }; + assign n3784 = 64'haaaa2aaaaaaaeaaa >> { Ng1326, Ng1345, Pg5648, Ng1224, Ng1211, Ng1386 }; + assign n3779 = 64'haaaa2aaaaaaaeaaa >> { Ng1326, Ng1345, Pg5629, Ng1224, Ng1211, Ng1385 }; + assign n2443 = 16'hf870 >> { n4564, Ng731, Ng1315, Ng630 }; + assign n2438 = 8'hd8 >> { Ng733, n4564, n6227 }; + assign n6227 = 4'h8 >> { Pg5648, Ng630 }; + assign n2433 = 16'hf870 >> { n4564, Ng732, Pg5629, Ng630 }; + assign n2428 = 16'hf870 >> { n4565, Ng728, Ng1315, Ng630 }; + assign n2423 = 8'hd8 >> { Ng730, n4565, n6227 }; + assign n2418 = 16'hf870 >> { n4565, Ng729, Pg5629, Ng630 }; + assign n2413 = 64'haaaa2aaaaaaaeaaa >> { Ng692, Ng659, Ng1315, Ng538, Ng525, Ng725 }; + assign n2408 = 64'haaaa2aaaaaaaeaaa >> { Ng692, Ng659, Pg5648, Ng538, Ng525, Ng727 }; + assign n2403 = 64'haaaa2aaaaaaaeaaa >> { Ng692, Ng659, Pg5629, Ng538, Ng525, Ng726 }; + assign n2398 = 64'haaaa2aaaaaaaeaaa >> { Ng686, Ng659, Ng1315, Ng538, Ng525, Ng722 }; + assign n2393 = 64'haaaa2aaaaaaaeaaa >> { Ng686, Ng659, Pg5648, Ng538, Ng525, Ng724 }; + assign n2388 = 64'haaaa2aaaaaaaeaaa >> { Ng686, Ng659, Pg5629, Ng538, Ng525, Ng723 }; + assign n2383 = 64'haaaa2aaaaaaaeaaa >> { Ng679, Ng659, Ng1315, Ng538, Ng525, Ng719 }; + assign n2378 = 64'haaaa2aaaaaaaeaaa >> { Ng679, Ng659, Pg5648, Ng538, Ng525, Ng721 }; + assign n2373 = 64'haaaa2aaaaaaaeaaa >> { Ng679, Ng659, Pg5629, Ng538, Ng525, Ng720 }; + assign n2368 = 64'haaaa2aaaaaaaeaaa >> { Ng666, Ng659, Ng1315, Ng538, Ng525, Ng716 }; + assign n2363 = 64'haaaa2aaaaaaaeaaa >> { Ng666, Ng659, Pg5648, Ng538, Ng525, Ng718 }; + assign n2358 = 64'haaaa2aaaaaaaeaaa >> { Ng666, Ng659, Pg5629, Ng538, Ng525, Ng717 }; + assign n2353 = 64'haaaa2aaaaaaaeaaa >> { Ng672, Ng659, Ng1315, Ng538, Ng525, Ng713 }; + assign n2348 = 64'haaaa2aaaaaaaeaaa >> { Ng672, Ng659, Pg5648, Ng538, Ng525, Ng715 }; + assign n2343 = 64'haaaa2aaaaaaaeaaa >> { Ng672, Ng659, Pg5629, Ng538, Ng525, Ng714 }; + assign n2338 = 64'haaaa2aaaaaaaeaaa >> { Ng660, Ng659, Ng1315, Ng538, Ng525, Ng710 }; + assign n2333 = 64'haaaa2aaaaaaaeaaa >> { Ng660, Ng659, Pg5648, Ng538, Ng525, Ng712 }; + assign n2328 = 64'haaaa2aaaaaaaeaaa >> { Ng660, Ng659, Pg5629, Ng538, Ng525, Ng711 }; + assign n2323 = 64'haaaa2aaaaaaaeaaa >> { Ng646, Ng659, Ng1315, Ng538, Ng525, Ng707 }; + assign n2318 = 64'haaaa2aaaaaaaeaaa >> { Ng646, Ng659, Pg5648, Ng538, Ng525, Ng709 }; + assign n2313 = 64'haaaa2aaaaaaaeaaa >> { Ng646, Ng659, Pg5629, Ng538, Ng525, Ng708 }; + assign n2308 = 64'haaaa2aaaaaaaeaaa >> { Ng653, Ng659, Ng1315, Ng538, Ng525, Ng704 }; + assign n2303 = 64'haaaa2aaaaaaaeaaa >> { Ng653, Ng659, Pg5648, Ng538, Ng525, Ng706 }; + assign n2298 = 64'haaaa2aaaaaaaeaaa >> { Ng653, Ng659, Pg5629, Ng538, Ng525, Ng705 }; + assign n2293 = 64'haaaa2aaaaaaaeaaa >> { Ng633, Ng659, Ng1315, Ng538, Ng525, Ng701 }; + assign n2288 = 64'haaaa2aaaaaaaeaaa >> { Ng633, Ng659, Pg5648, Ng538, Ng525, Ng703 }; + assign n2283 = 64'haaaa2aaaaaaaeaaa >> { Ng633, Ng659, Pg5629, Ng538, Ng525, Ng702 }; + assign n2278 = 64'haaaa2aaaaaaaeaaa >> { Ng640, Ng659, Ng1315, Ng538, Ng525, Ng698 }; + assign n2273 = 64'haaaa2aaaaaaaeaaa >> { Ng640, Ng659, Pg5648, Ng538, Ng525, Ng700 }; + assign n2268 = 64'haaaa2aaaaaaaeaaa >> { Ng640, Ng659, Pg5629, Ng538, Ng525, Ng699 }; + assign n405 = 8'hd8 >> { Ng2975, Pg4590, Ng2879 }; + assign n413 = 8'hd8 >> { Ng2978, Pg4323, Ng2879 }; + assign n425 = 8'hd8 >> { Ng2981, Pg4090, Ng2879 }; + assign n359 = 8'hd8 >> { Ng2874, Pg8251, Ng2879 }; + assign n409 = 8'hd8 >> { Ng2935, Pg4450, Ng2879 }; + assign n421 = 8'hd8 >> { Ng2938, Pg4200, Ng2879 }; + assign n433 = 8'hd8 >> { Ng2941, Pg3993, Ng2879 }; + assign n367 = 8'hd8 >> { Ng2944, Pg8175, Ng2879 }; + assign n375 = 8'hd8 >> { Ng2947, Pg8023, Ng2879 }; + assign n417 = 8'hd8 >> { Ng2953, Pg4321, Ng2879 }; + assign n429 = 8'hd8 >> { Ng2956, Pg4088, Ng2879 }; + assign n363 = 8'hd8 >> { Ng2959, Pg8249, Ng2879 }; + assign n386 = 8'hd8 >> { Ng2963, Pg7334, Ng2879 }; + assign n390 = 8'hd8 >> { Ng2966, Pg6895, Ng2879 }; + assign n394 = 8'hd8 >> { Ng2969, Pg6442, Ng2879 }; + assign n398 = 8'hd8 >> { Ng2972, Pg6225, Ng2879 }; + assign n770 = 8'he4 >> { Ng559, Ng3084, Ng1315 }; + assign n765 = 8'he4 >> { Ng559, Ng3211, Pg5648 }; + assign n760 = 8'he4 >> { Ng559, Ng3210, Pg5629 }; + assign n935 = 8'he4 >> { Ng8311, Ng3088, Ng1315 }; + assign n930 = 8'he4 >> { Ng8311, Ng3185, Pg5648 }; + assign n925 = 8'he4 >> { Ng8311, Ng3182, Pg5629 }; + assign n920 = 8'he4 >> { Ng8302, Ng3179, Ng1315 }; + assign n915 = 8'he4 >> { Ng8302, Ng3176, Pg5648 }; + assign n910 = 8'he4 >> { Ng8302, Ng3173, Pg5629 }; + assign n905 = 8'he4 >> { Ng8293, Ng3170, Ng1315 }; + assign n900 = 8'he4 >> { Ng8293, Ng3167, Pg5648 }; + assign n895 = 8'he4 >> { Ng8293, Ng3164, Pg5629 }; + assign n890 = 8'he4 >> { Ng8284, Ng3161, Ng1315 }; + assign n885 = 8'he4 >> { Ng8284, Ng3158, Pg5648 }; + assign n880 = 8'he4 >> { Ng8284, Ng3155, Pg5629 }; + assign n815 = 8'he4 >> { Ng2633, Ng3096, Ng1315 }; + assign n810 = 8'he4 >> { Ng2633, Ng3095, Pg5648 }; + assign n805 = 8'he4 >> { Ng2633, Ng3094, Pg5629 }; + assign n800 = 8'he4 >> { Ng1939, Ng3093, Ng1315 }; + assign n795 = 8'he4 >> { Ng1939, Ng3092, Pg5648 }; + assign n790 = 8'he4 >> { Ng1939, Ng3091, Pg5629 }; + assign n785 = 8'he4 >> { Ng1245, Ng3087, Ng1315 }; + assign n780 = 8'he4 >> { Ng1245, Ng3086, Pg5648 }; + assign n775 = 8'he4 >> { Ng1245, Ng3085, Pg5629 }; + assign n339_1 = 8'hd8 >> { Ng3056, Ng3074, Ng2987 }; + assign n331 = 8'hd8 >> { Ng3055, Ng3073, Ng2987 }; + assign n327 = 8'hd8 >> { Ng3053, Ng3072, Ng2987 }; + assign n323 = 8'hd8 >> { Ng3052, Ng3071, Ng2987 }; + assign n7238_1 = 8'hd8 >> { Ng3051, Ng3070, Ng2987 }; + assign n303 = 8'hd8 >> { Ng3050, Ng3069, Ng2987 }; + assign n307 = 8'hd8 >> { Ng3049, Ng3068, Ng2987 }; + assign n311 = 8'hd8 >> { Ng3048, Ng3067, Ng2987 }; + assign n315 = 8'hd8 >> { Ng3047, Ng3066, Ng2987 }; + assign n299 = 8'hd8 >> { Ng3046, Ng3065, Ng2987 }; + assign n295 = 8'hd8 >> { Ng3045, Ng3064, Ng2987 }; + assign n291 = 8'hd8 >> { Ng3044, Ng3063, Ng2987 }; + assign n287 = 8'hd8 >> { Ng3043, Ng3062, Ng2987 }; + assign n7248 = 8'hd8 >> { Ng3061, Ng2997, Ng2987 }; + assign n351 = 8'hd8 >> { Ng3060, Ng3078, Ng2987 }; + assign n343 = 8'hd8 >> { Ng3059, Ng3077, Ng2987 }; + assign n347 = 8'hd8 >> { Ng3058, Ng3076, Ng2987 }; + assign n335 = 8'hd8 >> { Ng3057, Ng3075, Ng2987 }; + assign n715 = 8'hd8 >> { Ng2200, Ng2874, Ng2879 }; + assign n725 = 8'hd8 >> { Ng2190, Ng2978, Ng2879 }; + assign n720 = 8'hd8 >> { Ng2195, Ng2981, Ng2879 }; + assign n730 = 8'hd8 >> { Ng2185, Ng2975, Ng2879 }; + assign n735 = 8'hd8 >> { Ng2180, Ng2972, Ng2879 }; + assign n740 = 8'hd8 >> { Ng2175, Ng2969, Ng2879 }; + assign n745 = 8'hd8 >> { Ng2170, Ng2966, Ng2879 }; + assign n750 = 8'hd8 >> { Ng2165, Ng2963, Ng2879 }; + assign n633 = 8'hd8 >> { Ng1471, Ng2935, Ng2879 }; + assign n628 = 8'hd8 >> { Ng1476, Ng2938, Ng2879 }; + assign n623 = 8'hd8 >> { Ng1481, Ng2941, Ng2879 }; + assign n618 = 8'hd8 >> { Ng1486, Ng2944, Ng2879 }; + assign n613 = 8'hd8 >> { Ng1491, Ng2947, Ng2879 }; + assign n608 = 8'hd8 >> { Ng1496, Ng2953, Ng2879 }; + assign n603 = 8'hd8 >> { Ng1501, Ng2956, Ng2879 }; + assign n598 = 8'hd8 >> { Ng1506, Ng2959, Ng2879 }; + assign n6711 = 8'hd8 >> { Ng2704, Ng2584, Ng1315 }; + assign n6327 = 8'hd8 >> { Ng2584, Ng2631, Ng1315 }; + assign n6322 = 8'h72 >> { Ng2631, Ng2628, Ng1315 }; + assign n5209 = 8'hd8 >> { Ng2010, Ng1890, Ng1315 }; + assign n4825 = 8'hd8 >> { Ng1890, Ng1937, Ng1315 }; + assign n4820 = 8'h72 >> { Ng1937, Ng1934, Ng1315 }; + assign n3719 = 8'hd8 >> { Ng1316, Ng1196, Ng1315 }; + assign n3324 = 8'hd8 >> { Ng1196, Ng1243, Ng1315 }; + assign n3319 = 8'h72 >> { Ng1243, Ng1240, Ng1315 }; + assign n2208 = 8'hd8 >> { Ng630, Ng510, Ng1315 }; + assign n1824 = 8'hd8 >> { Ng510, Ng557, Ng1315 }; + assign n1819 = 8'h72 >> { Ng557, Ng554, Ng1315 }; + assign n1978 = 64'hdd0ddd0d0000dd0d >> { Ng477, Pg5648, Ng479, Pg5629, Ng478, Ng1315 }; + assign n1992 = 64'hdd0ddd0d0000dd0d >> { Ng480, Pg5648, Ng464, Pg5629, Ng484, Ng1315 }; + assign n3478 = 64'hdd0ddd0d0000dd0d >> { Ng1164, Pg5648, Ng1166, Pg5629, Ng1165, Ng1315 }; + assign n2001 = 64'hdd0ddd0d0000dd0d >> { Ng486, Pg5648, Ng488, Pg5629, Ng487, Ng1315 }; + assign n3492 = 64'hdd0ddd0d0000dd0d >> { Ng1167, Pg5648, Ng1151, Pg5629, Ng1171, Ng1315 }; + assign n4979 = 64'hdd0ddd0d0000dd0d >> { Ng1858, Pg5648, Ng1860, Pg5629, Ng1859, Ng1315 }; + assign n3501 = 64'hdd0ddd0d0000dd0d >> { Ng1173, Pg5648, Ng1175, Pg5629, Ng1174, Ng1315 }; + assign n4993_1 = 64'hdd0ddd0d0000dd0d >> { Ng1861, Pg5648, Ng1845, Pg5629, Ng1865, Ng1315 }; + assign n6481 = 64'hdd0ddd0d0000dd0d >> { Ng2552, Pg5648, Ng2554, Pg5629, Ng2553, Ng1315 }; + assign n5002 = 64'hdd0ddd0d0000dd0d >> { Ng1867, Pg5648, Ng1869, Pg5629, Ng1868, Ng1315 }; + assign n6495_1 = 64'hdd0ddd0d0000dd0d >> { Ng2555, Pg5648, Ng2539, Pg5629, Ng2559, Ng1315 }; + assign n6504 = 64'hdd0ddd0d0000dd0d >> { Ng2561, Pg5648, Ng2563, Pg5629, Ng2562, Ng1315 }; + assign n437 = 4'h2 >> { Pg51, Ng13457 }; + assign n442 = 4'h2 >> { Pg51, Ng2817 }; + assign n447 = 4'he >> { Pg51, Ng2933 }; + assign n6991_1 = 4'he >> { Pg3234, Ng3079 }; + assign n2218 = 16'h2212 >> { Ng659, Ng1315, n6227, Ng640 }; + assign n3729 = 16'h2212 >> { Ng1345, Ng1315, n6190, Ng1326 }; + assign n5219 = 16'h2212 >> { Ng2039, Ng1315, n6153_1, Ng2020 }; + assign n6721 = 16'h2212 >> { Ng2733, Ng1315, n6116, Ng2714 }; + assign n452 = 8'h7d >> { Ng2883, Ng13457, n6369 }; + assign n6369 = 4'h1 >> { n6370, Pg8021 }; + assign n6370 = 32'd32768 >> { Ng2883, Ng2908, Ng2888, n6371, Ng13457 }; + assign n6371 = 16'h0008 >> { Ng2900, Ng2896, Ng2892, Ng2903 }; + assign n6981_1 = 4'h2 >> { Pg3234, Ng13475 }; + assign n6986_1 = 4'h2 >> { Pg3234, Ng3054 }; + assign n2223 = 32'd572658210 >> { Ng659, Ng1315, Ng640, n6227, Ng633 }; + assign n3734 = 32'd572658210 >> { Ng1345, Ng1315, Ng1326, n6190, Ng1319 }; + assign n5224 = 32'd572658210 >> { Ng2039, Ng1315, Ng2020, n6153_1, Ng2013 }; + assign n6726 = 32'd572658210 >> { Ng2733, Ng1315, Ng2714, n6116, Ng2707 }; + assign n487 = 64'hf6f6f6f6f6f6fef6 >> { Ng2924, Ng2917, Ng2920, Pg8021, n6370, Ng2912 }; + assign n7210 = 64'hf6f6f6f6f6f6fef6 >> { Ng3028, Ng3036, Ng3032, Pg3234, n6380, Ng3018 }; + assign n6380 = 4'h8 >> { n4557, Ng13475 }; + assign n457 = 16'h2888 >> { Ng2883, Ng13457, Ng2888, n6369 }; + assign n2463 = 64'h7070707072707070 >> { Ng659, Ng538, Ng525, Ng738, Ng630, Pg5629 }; + assign n2468 = 64'h7070707072707070 >> { Ng659, Ng538, Ng525, Ng739, Ng630, Pg5648 }; + assign n3974 = 64'h7070707072707070 >> { Ng1345, Ng1224, Ng1211, Ng1424, Ng1316, Pg5629 }; + assign n2473 = 64'h7070707072707070 >> { Ng659, Ng538, Ng525, Ng737, Ng630, Ng1315 }; + assign n3979 = 64'h7070707072707070 >> { Ng1345, Ng1224, Ng1211, Ng1425, Ng1316, Pg5648 }; + assign n5464 = 64'h7070707072707070 >> { Ng2039, Ng1918, Ng1905, Ng2118, Ng2010, Pg5629 }; + assign n3984 = 64'h7070707072707070 >> { Ng1345, Ng1224, Ng1211, Ng1423, Ng1316, Ng1315 }; + assign n5469 = 64'h7070707072707070 >> { Ng2039, Ng1918, Ng1905, Ng2119, Ng2010, Pg5648 }; + assign n6966_1 = 64'h7070707072707070 >> { Ng2733, Ng2612, Ng2599, Ng2812, Ng2704, Pg5629 }; + assign n5474 = 64'h7070707072707070 >> { Ng2039, Ng1918, Ng1905, Ng2117, Ng2010, Ng1315 }; + assign n6971_1 = 64'h7070707072707070 >> { Ng2733, Ng2612, Ng2599, Ng2813, Ng2704, Pg5648 }; + assign n6976_1 = 64'h7070707072707070 >> { Ng2733, Ng2612, Ng2599, Ng2811, Ng2704, Ng1315 }; + assign n2228 = 64'h2222222212222222 >> { Ng659, Ng1315, Ng633, Ng640, n6227, Ng653 }; + assign n3739 = 64'h2222222212222222 >> { Ng1345, Ng1315, Ng1319, Ng1326, n6190, Ng1339 }; + assign n7185 = 32'd680036488 >> { Ng2998, Ng2993, Ng13475, Ng3006, n6397 }; + assign n6397 = 4'h1 >> { n6380, Pg3234 }; + assign n5229 = 64'h2222222212222222 >> { Ng2039, Ng1315, Ng2013, Ng2020, n6153_1, Ng2033 }; + assign n6731 = 64'h2222222212222222 >> { Ng2733, Ng1315, Ng2707, Ng2714, n6116, Ng2727 }; + assign n492 = 32'd101057542 >> { Ng2924, Ng2920, Pg8021, Ng2917, n6401 }; + assign n6401 = 4'h8 >> { n6370, Ng2912 }; + assign n462 = 32'd680036488 >> { Ng2888, Ng2883, Ng13457, Ng2896, n6369 }; + assign n7215 = 32'd101057542 >> { Ng3036, Ng3032, Pg3234, Ng3028, n6404_1 }; + assign n6404_1 = 4'h8 >> { n6380, Ng3018 }; + assign n2233 = 8'h06 >> { n6227, n6406, Ng646 }; + assign n6406 = 32'd32768 >> { Ng659, Ng1315, Ng653, Ng633, Ng640 }; + assign n3744 = 8'h06 >> { n6190, n6408, Ng1332 }; + assign n6408 = 32'd32768 >> { Ng1345, Ng1315, Ng1339, Ng1319, Ng1326 }; + assign n5234 = 8'h06 >> { n6153_1, n6410, Ng2026 }; + assign n6410 = 32'd32768 >> { Ng2039, Ng1315, Ng2033, Ng2013, Ng2020 }; + assign n6736 = 8'h06 >> { n6116, n6412, Ng2720 }; + assign n6412 = 32'd32768 >> { Ng2733, Ng1315, Ng2727, Ng2707, Ng2714 }; + assign n7190 = 64'h2888888888888888 >> { Ng3006, Ng2998, Ng2993, Ng13475, Ng3002, n6397 }; + assign n7220 = 16'h1222 >> { n6404_1, Ng3028, Pg3234, Ng3036 }; + assign n467 = 64'h2888888888888888 >> { Ng2896, Ng2888, Ng2883, Ng13457, Ng2892, n6369 }; + assign n497 = 16'h1222 >> { n6401, Ng2917, Pg8021, Ng2924 }; + assign n1353_1 = 16'h1222 >> { n6418_1, Ng92, n6419, Ng88 }; + assign n6418_1 = 4'h2 >> { n5569_1, Ng853 }; + assign n6419 = 8'h80 >> { n5569_1, Ng853, Ng2257 }; + assign n2853 = 16'h1222 >> { n6418_1, Ng780, n6419, Ng776 }; + assign n4354 = 16'h1222 >> { n6418_1, Ng1466, n6419, Ng1462 }; + assign n5844 = 16'h1222 >> { n6418_1, Ng2160, n6419, Ng2156 }; + assign n2238 = 8'h06 >> { n6227, n6424, Ng660 }; + assign n6424 = 4'h8 >> { n6406, Ng646 }; + assign n3749 = 8'h06 >> { n6190, n6426_1, Ng1346 }; + assign n6426_1 = 4'h8 >> { n6408, Ng1332 }; + assign n7195 = 8'h28 >> { n6428, Ng3013, n6397 }; + assign n6428 = 32'd2147483648 >> { Ng3006, Ng3002, Ng2998, Ng2993, Ng13475 }; + assign n5239 = 8'h06 >> { n6153_1, n6430, Ng2040 }; + assign n6430 = 4'h8 >> { n6410, Ng2026 }; + assign n6741 = 8'h06 >> { n6116, n6432, Ng2734 }; + assign n6432 = 4'h8 >> { n6412, Ng2720 }; + assign n502 = 32'd304095778 >> { n6401, Ng2924, Ng2917, Pg8021, Ng2920 }; + assign n472 = 8'h28 >> { n6435, Ng2903, n6369 }; + assign n6435 = 32'd2147483648 >> { Ng2896, Ng2892, Ng2888, Ng2883, Ng13457 }; + assign n7225 = 32'd304095778 >> { n6404_1, Ng3028, Ng3036, Pg3234, Ng3032 }; + assign n1358 = 8'h06 >> { n6419, n6438, Ng83 }; + assign n6438 = 8'h80 >> { n6418_1, Ng92, Ng88 }; + assign n2858 = 32'd304226850 >> { n6418_1, Ng780, Ng776, n6419, Ng771 }; + assign n4359 = 32'd304226850 >> { n6418_1, Ng1466, Ng1462, n6419, Ng1457 }; + assign n5849 = 32'd304226850 >> { n6418_1, Ng2160, Ng2156, n6419, Ng2151 }; + assign n2243 = 16'h1222 >> { n6424, Ng660, n6227, Ng672 }; + assign n3754 = 16'h1222 >> { n6426_1, Ng1346, n6190, Ng1358 }; + assign n5244 = 16'h1222 >> { n6430, Ng2040, n6153_1, Ng2052 }; + assign n6746 = 16'h1222 >> { n6432, Ng2734, n6116, Ng2746 }; + assign n7200_1 = 16'h2888 >> { n6428, Ng3013, Ng3010, n6397 }; + assign n477 = 16'h2888 >> { n6435, Ng2903, Ng2900, n6369 }; + assign n1363 = 16'h1222 >> { n6438, Ng83, n6419, Ng79 }; + assign n2863 = 64'h1222222222222222 >> { n6418_1, Ng780, Ng776, Ng771, n6419, Ng767 }; + assign n4364 = 64'h1222222222222222 >> { n6418_1, Ng1466, Ng1462, Ng1457, n6419, Ng1453 }; + assign n5854 = 64'h1222222222222222 >> { n6418_1, Ng2160, Ng2156, Ng2151, n6419, Ng2147 }; + assign n2248 = 32'd304226850 >> { n6424, Ng660, Ng672, n6227, Ng666 }; + assign n3759 = 32'd304226850 >> { n6426_1, Ng1346, Ng1358, n6190, Ng1352 }; + assign n7205 = 32'd680036488 >> { n6428, Ng3013, Ng3010, Ng3024, n6397 }; + assign n5249 = 32'd304226850 >> { n6430, Ng2040, Ng2052, n6153_1, Ng2046 }; + assign n6751 = 32'd304226850 >> { n6432, Ng2734, Ng2746, n6116, Ng2740 }; + assign n482 = 32'd680036488 >> { n6435, Ng2900, Ng2903, Ng2908, n6369 }; + assign n1368_1 = 32'd304226850 >> { n6438, Ng83, Ng79, n6419, Ng74 }; + assign n2868 = 8'h06 >> { n6419, n6460, Ng762 }; + assign n6460 = 32'd2147483648 >> { n6418_1, Ng780, Ng776, Ng771, Ng767 }; + assign n4369 = 8'h06 >> { n6419, n6462, Ng1448 }; + assign n6462 = 32'd2147483648 >> { n6418_1, Ng1466, Ng1462, Ng1457, Ng1453 }; + assign n5859 = 8'h06 >> { n6419, n6464_1, Ng2142 }; + assign n6464_1 = 32'd2147483648 >> { n6418_1, Ng2160, Ng2156, Ng2151, Ng2147 }; + assign n2253 = 64'h1222222222222222 >> { n6424, Ng660, Ng672, Ng666, n6227, Ng679 }; + assign n3764 = 64'h1222222222222222 >> { n6426_1, Ng1346, Ng1358, Ng1352, n6190, Ng1365 }; + assign n5254 = 64'h1222222222222222 >> { n6430, Ng2040, Ng2052, Ng2046, n6153_1, Ng2059 }; + assign n6756 = 64'h1222222222222222 >> { n6432, Ng2734, Ng2746, Ng2740, n6116, Ng2753 }; + assign n1373 = 8'h06 >> { n6419, n6470, Ng70 }; + assign n6470 = 16'h8000 >> { n6438, Ng83, Ng79, Ng74 }; + assign n2873 = 8'h06 >> { n6419, n6472_1, Ng758 }; + assign n6472_1 = 4'h8 >> { n6460, Ng762 }; + assign n4374 = 8'h06 >> { n6419, n6474, Ng1444 }; + assign n6474 = 4'h8 >> { n6462, Ng1448 }; + assign n5864 = 8'h06 >> { n6419, n6476_1, Ng2138 }; + assign n6476_1 = 4'h8 >> { n6464_1, Ng2142 }; + assign n2258 = 8'h06 >> { n6227, n6478, Ng686 }; + assign n6478 = 32'd2147483648 >> { n6424, Ng660, Ng672, Ng679, Ng666 }; + assign n3769 = 8'h06 >> { n6190, n6480, Ng1372 }; + assign n6480 = 32'd2147483648 >> { n6426_1, Ng1346, Ng1358, Ng1365, Ng1352 }; + assign n5259 = 8'h06 >> { n6153_1, n6482, Ng2066 }; + assign n6482 = 32'd2147483648 >> { n6430, Ng2040, Ng2052, Ng2059, Ng2046 }; + assign n6761 = 8'h06 >> { n6116, n6484, Ng2760 }; + assign n6484 = 32'd2147483648 >> { n6432, Ng2734, Ng2746, Ng2753, Ng2740 }; + assign n1533 = 16'h7270 >> { n6486, Ng448, n6487, Pg5437 }; + assign n6486 = 16'h8002 >> { n5755, n5757, n5758, Ng2257 }; + assign n6487 = 32'd134217856 >> { n5755, n5758, n5757, n5759_1, Ng2257 }; + assign n1538 = 16'h7270 >> { n6486, Ng449, n6487, Pg6313 }; + assign n3033 = 16'h7270 >> { n6490, Ng1135, n6491, Pg5437 }; + assign n6490 = 16'h8002 >> { n5742, n5744_1, n5745, Ng2257 }; + assign n6491 = 32'd134217856 >> { n5742, n5745, n5744_1, n5746, Ng2257 }; + assign n1543 = 16'h7270 >> { n6486, Ng447, n6487, Ng853 }; + assign n3038 = 16'h7270 >> { n6490, Ng1136, n6491, Pg6313 }; + assign n4534 = 16'h7270 >> { n6495, Ng1829, n6496, Pg5437 }; + assign n6495 = 16'h8002 >> { n5729_1, n5731, n5732, Ng2257 }; + assign n6496 = 32'd134217856 >> { n5729_1, n5732, n5731, n5733, Ng2257 }; + assign n3043 = 16'h7270 >> { n6490, Ng1134, n6491, Ng853 }; + assign n4539 = 16'h7270 >> { n6495, Ng1830, n6496, Pg6313 }; + assign n6036 = 16'h7270 >> { n6500, Ng2523, n6501, Pg5437 }; + assign n6500 = 16'h8002 >> { n5716, n5718, n5719_1, Ng2257 }; + assign n6501 = 32'd134217856 >> { n5716, n5719_1, n5718, n5720, Ng2257 }; + assign n4544 = 16'h7270 >> { n6495, Ng1828, n6496, Ng853 }; + assign n6041 = 16'h7270 >> { n6500, Ng2524, n6501, Pg6313 }; + assign n6046 = 16'h7270 >> { n6500, Ng2522, n6501, Ng853 }; + assign n1378 = 16'h1222 >> { n6470, Ng70, n6419, Ng65 }; + assign n2878 = 16'h1222 >> { n6472_1, Ng758, n6419, Ng753 }; + assign n4379 = 16'h1222 >> { n6474, Ng1444, n6419, Ng1439 }; + assign n5869 = 16'h1222 >> { n6476_1, Ng2138, n6419, Ng2133 }; + assign n2263 = 16'h1222 >> { n6478, Ng686, n6227, Ng692 }; + assign n3774 = 16'h1222 >> { n6480, Ng1372, n6190, Ng1378 }; + assign n5264 = 16'h1222 >> { n6482, Ng2066, n6153_1, Ng2072 }; + assign n6766 = 16'h1222 >> { n6484, Ng2760, n6116, Ng2766 }; + assign n1383_1 = 32'd304226850 >> { n6470, Ng70, Ng65, n6419, Ng61 }; + assign n2883 = 32'd304226850 >> { n6472_1, Ng758, Ng753, n6419, Ng749 }; + assign n4384 = 32'd304226850 >> { n6474, Ng1444, Ng1439, n6419, Ng1435 }; + assign n5874 = 32'd304226850 >> { n6476_1, Ng2138, Ng2133, n6419, Ng2129 }; + assign n1488 = 16'h7270 >> { n6518_1, Ng427, n6519, Pg5437 }; + assign n6518_1 = 8'h08 >> { n5393, n5366, Ng2257 }; + assign n6519 = 16'h0008 >> { n5393, n5366, n5367, Ng2257 }; + assign n1493_1 = 16'h7270 >> { n6518_1, Ng428, n6519, Pg6313 }; + assign n2988 = 16'h7270 >> { n6522, Ng1114, n6523_1, Pg5437 }; + assign n6522 = 8'h80 >> { n5388, n5351, Ng2257 }; + assign n6523_1 = 16'h0080 >> { n5351, n5388, n5352, Ng2257 }; + assign n1498_1 = 16'h7270 >> { n6518_1, Ng426, n6519, Ng853 }; + assign n2993 = 16'h7270 >> { n6522, Ng1115, n6523_1, Pg6313 }; + assign n4489 = 64'haaeaaaeaaa2aaaaa >> { n5337, n5338, n5383, Pg5437, Ng2257, Ng1808 }; + assign n2998 = 16'h7270 >> { n6522, Ng1113, n6523_1, Ng853 }; + assign n4494 = 64'haaeaaaeaaa2aaaaa >> { n5337, n5338, n5383, Pg6313, Ng2257, Ng1809 }; + assign n5991 = 16'h7270 >> { n6530, Ng2502, n6531, Pg5437 }; + assign n6530 = 8'h80 >> { n5378, n5322, Ng2257 }; + assign n6531 = 16'h0080 >> { n5322, n5378, n5323, Ng2257 }; + assign n4499 = 64'haaeaaaeaaa2aaaaa >> { n5337, n5338, n5383, Ng853, Ng2257, Ng1807 }; + assign n5996 = 16'h7270 >> { n6530, Ng2503, n6531, Pg6313 }; + assign n6001 = 16'h7270 >> { n6530, Ng2501, n6531, Ng853 }; + assign n1388_1 = 64'h1222222222222222 >> { n6470, Ng70, Ng65, Ng61, n6419, Ng56 }; + assign n2888 = 64'h1222222222222222 >> { n6472_1, Ng758, Ng753, Ng749, n6419, Ng744 }; + assign n4389 = 64'h1222222222222222 >> { n6474, Ng1444, Ng1439, Ng1435, n6419, Ng1430 }; + assign n5879 = 64'h1222222222222222 >> { n6476_1, Ng2138, Ng2133, Ng2129, n6419, Ng2124 }; + assign n1393_1 = 4'h1 >> { n6540, n6419 }; + assign n6540 = 64'h9555555555555555 >> { n6470, Ng70, Ng65, Ng61, Ng56, Ng52 }; + assign n2893 = 4'h1 >> { n6542, n6419 }; + assign n6542 = 64'h9555555555555555 >> { n6472_1, Ng758, Ng753, Ng749, Ng744, Ng740 }; + assign n4394 = 4'h1 >> { n6544, n6419 }; + assign n6544 = 64'h9555555555555555 >> { n6474, Ng1444, Ng1439, Ng1435, Ng1430, Ng1426 }; + assign n5884 = 4'h1 >> { n6546, n6419 }; + assign n6546 = 64'h9555555555555555 >> { n6476_1, Ng2138, Ng2133, Ng2129, Ng2124, Ng2120 }; + assign n6547 = 64'h0000066006600000 >> { n4763, Ng2151, Ng2160, n4764, n4760, Ng2142 }; + assign n6548_1 = 64'h0000066006600000 >> { n4797, Ng2120, Ng2147, n4799, Ng2133, n4759 }; + assign n4714 = 16'h0777 >> { n4928, n4931, n6550, n6554 }; + assign n6550 = 64'h0008080000808000 >> { n4876, n4881, Ng1466, Ng1430, n6551, n6553_1 }; + assign n6551 = 32'd40 >> { n5610, n5569_1, n4860, Ng1435, n6552 }; + assign n6552 = 64'h0000066006600660 >> { n4861, Ng1462, n4866, Ng1453, n4878, Ng1448 }; + assign n6553_1 = 64'h0000666066606660 >> { n4865_1, Ng1426, n4861, Ng1462, Ng1457, n4874_1 }; + assign n6554 = 64'h0660066006600000 >> { n4865_1, Ng1426, Ng1444, n4863, Ng1439, n4879_1 }; + assign n3213 = 8'h15 >> { n5027, n5030, n6556 }; + assign n6556 = 64'h0008080000808000 >> { n4965, n4985, Ng744, Ng776, n6560, n6557 }; + assign n6557 = 64'h0008080000808000 >> { n4978, n4983, Ng771, Ng762, n6558_1, n5651 }; + assign n6558_1 = 32'd35653760 >> { n4971, n4981, Ng753, Ng758, n6559 }; + assign n6559 = 16'h1428 >> { n4969, n4980, Ng780, Ng740 }; + assign n6560 = 16'h1428 >> { n4966_1, n4970_1, Ng767, Ng749 }; + assign n6561 = 32'd35653760 >> { n5064, n5080, Ng65, Ng79, n6562 }; + assign n6562 = 64'h0000666066606660 >> { Ng61, n5070, n5066_1, Ng52, n5083, Ng74 }; + assign n6563_1 = 64'h0000666066606660 >> { Ng92, n5085, n5070, Ng61, Ng83, n5082 }; + assign n7243 = 8'h69 >> { n6565, n6566, Ng3083 }; + assign n6565 = 16'h9669 >> { Pg8268, Pg8269, Pg8274, Pg8275 }; + assign n6566 = 16'h6996 >> { Pg8270, Pg8271, Pg8273, Pg8272 }; + assign n7253 = 8'h69 >> { n6568_1, n6569, Ng2990 }; + assign n6568_1 = 16'h9669 >> { Pg8264, Pg8262, Pg8263, Pg8260 }; + assign n6569 = 16'h6996 >> { Pg8266, Pg8265, Pg8261, Pg8259 }; + assign n319 = 16'h9969 >> { Pg3231, Ng3120, n6565, n6566 }; + assign n355 = 16'h9969 >> { Pg3231, Ng3120, n6568_1, n6569 }; + assign n507 = 4'h9 >> { n6107, Ng2934 }; + assign n512 = 4'h9 >> { n6110, Ng2962 }; + assign Pg27380 = 2'h1 >> n983; + assign Pg26135 = 2'h1 >> n944; + assign Pg25435 = 2'h1 >> n953; + assign Pg24734 = 2'h1 >> n958_1; + assign n6706 = 2'h1 >> Ng2366; + assign n6696 = 2'h1 >> Ng2364; + assign n6691 = 2'h1 >> Ng2362; + assign n6686 = 2'h1 >> Ng2360; + assign n6681 = 2'h1 >> Ng2358; + assign n6676 = 2'h1 >> Ng2356; + assign n6671 = 2'h1 >> Ng2354; + assign n6666 = 2'h1 >> Ng2528; + assign n6661 = 2'h1 >> Ng2526; + assign n6189 = 2'h1 >> Ng2165; + assign n6180 = 2'h1 >> Ng2170; + assign n6171 = 2'h1 >> Ng2175; + assign n6162 = 2'h1 >> Ng2180; + assign n6153 = 2'h1 >> Ng2185; + assign n6144 = 2'h1 >> Ng2190; + assign n6135 = 2'h1 >> Ng2195; + assign n6126 = 2'h1 >> Ng2200; + assign n5204 = 2'h1 >> Ng1672; + assign n5194 = 2'h1 >> Ng1670; + assign n5189 = 2'h1 >> Ng1668; + assign n5184 = 2'h1 >> Ng1666; + assign n5179 = 2'h1 >> Ng1664; + assign n5174 = 2'h1 >> Ng1662; + assign n5169 = 2'h1 >> Ng1660; + assign n5164 = 2'h1 >> Ng1834; + assign n5159 = 2'h1 >> Ng1832; + assign n4687 = 2'h1 >> Ng1471; + assign n4678 = 2'h1 >> Ng1476; + assign n4669 = 2'h1 >> Ng1481; + assign n4660 = 2'h1 >> Ng1486; + assign n4651 = 2'h1 >> Ng1491; + assign n4642 = 2'h1 >> Ng1496; + assign n4633 = 2'h1 >> Ng1501; + assign n4624 = 2'h1 >> Ng1506; + assign n3703 = 2'h1 >> Ng978; + assign n3693 = 2'h1 >> Ng976; + assign n3688 = 2'h1 >> Ng974; + assign n3683 = 2'h1 >> Ng972; + assign n3678 = 2'h1 >> Ng970; + assign n3673 = 2'h1 >> Ng968; + assign n3668 = 2'h1 >> Ng966; + assign n3663 = 2'h1 >> Ng1140; + assign n3658 = 2'h1 >> Ng1138; + assign n3186 = 2'h1 >> Ng785; + assign n3177 = 2'h1 >> Ng789; + assign n3168 = 2'h1 >> Ng793; + assign n3159 = 2'h1 >> Ng797; + assign n3150 = 2'h1 >> Ng801; + assign n3141 = 2'h1 >> Ng805; + assign n3132 = 2'h1 >> Ng809; + assign n3123 = 2'h1 >> Ng813; + assign n2203 = 2'h1 >> Ng291; + assign n2193 = 2'h1 >> Ng289; + assign n2188 = 2'h1 >> Ng287; + assign n2183 = 2'h1 >> Ng285; + assign n2178 = 2'h1 >> Ng283; + assign n2173 = 2'h1 >> Ng281; + assign n2168 = 2'h1 >> Ng279; + assign n2163 = 2'h1 >> Ng453; + assign n2158 = 2'h1 >> Ng451; + assign n1686 = 2'h1 >> Ng97; + assign n1677 = 2'h1 >> Ng101; + assign n1668 = 2'h1 >> Ng105; + assign n1659 = 2'h1 >> Ng109; + assign n1650 = 2'h1 >> Ng113; + assign n1641 = 2'h1 >> Ng117; + assign n1632 = 2'h1 >> Ng121; + assign n1623 = 2'h1 >> Ng125; + assign n6646 = 64'h0901090119110901 >> { Ng185, n4526, n4529_1, Ng3120, Ng3147, Ng3110 }; + assign n983 = 64'h1111111111110111 >> { Ng3126, Ng3191, n6646, Ng3135, n4527, Pg25420 }; + assign n6648 = 16'h5d7f >> { Ng3179, Ng3182, Ng3139, n4531 }; + assign n6649 = 64'h0008000800080808 >> { n4525, n4536, Ng3135, Pg25420, n4535, n4532 }; + assign n6650 = 32'd176827050 >> { Ng3155, Ng3158, n4530, Ng3139, n6649 }; + assign n6651 = 64'hf777b333b333b333 >> { Ng3161, n4530, n4531, Ng3088, n6649, Ng3139 }; + assign Pg26149 = 16'h8ddd >> { n6650, n6648, n6651, Ng3120 }; + assign n6653 = 64'h0080000000800080 >> { n4525, Ng3128, n4537, n4538, n4539_1, n4540 }; + assign n6654 = 64'hf7b3d591e6a2c480 >> { Ng3210, Ng3084, Ng3211, Ng3085, Ng3139, Ng3120 }; + assign Pg26104 = 32'd4294440951 >> { n4530, n6654, Pg25420, n6709, n4541 }; + assign n6656_1 = 64'h6996966996696996 >> { n4589_1, n4590, n4597, n4598, n4599_1, n4601 }; + assign n6657 = 64'h9dafcdaf37af67af >> { n4602, n4604_1, n4586, Ng2631, n4576, Ng2584 }; + assign n7160 = 32'd2365951373 >> { n4610, Ng2610, Ng2584, n4611, n6657 }; + assign n6659 = 64'h99969699a9a6a6a9 >> { n4573, n4634, n4639, n4646_1, n4638, n4643 }; + assign n6660 = 16'h6996 >> { n4631, n4635, n4640, n4642_1 }; + assign n7125 = 32'd142671871 >> { n4647, n6659, n6660, n4629, Ng1890 }; + assign n6662 = 32'd3399117370 >> { n4648, n4638, n4629, n4573, Ng1937 }; + assign n7120 = 64'h45e545a001a101a0 >> { Ng1917, Ng1905, Ng1890, n6662, n4651_1, Ng1937 }; + assign n6664 = 64'h777daaaa2228aaaa >> { n4649, n4629, n4639, n4646_1, n4572, Ng1890 }; + assign n7115 = 64'h2274227400442274 >> { Ng1916, n4651_1, Ng1890, Ng1905, Ng1937, n6664 }; + assign n6666_1 = 64'hd7d7d7dd7777777d >> { n4690, n4673_1, n4676, Ng1196, n4568, n4671 }; + assign n7070 = 64'h8e8e0c8e8a8a008a >> { Ng1243, Ng1222, n4696, Ng1196, n6666_1, n4701 }; + assign n6668 = 64'h9669699628282828 >> { n4728, n4564, n4715, n4565, n4716, n4731 }; + assign n6669 = 64'h7777777d77d777dd >> { n4724, n4727, n4713, Ng510, n4564, n4728 }; + assign n7025 = 64'h8e8e0c8e8a8a008a >> { Ng557, Ng536, n4737, Ng510, n6669, n4740 }; + assign n6671_1 = 64'h373737373737bf37 >> { n4793, n4803, n4805, n4771, Ng2257, n4791 }; + assign n6672 = 64'h8820aa22a820aa22 >> { n4756, n6671_1, n4791, n4784, n4792, n4809 }; + assign n6673 = 64'hefefefefefefcdef >> { n4793, n4803, n4757, n4809, n4792, n4791 }; + assign n6674 = 32'd273682769 >> { n4909, n4886, n4884, n4892_1, n4910 }; + assign n6675 = 64'h0000099009900000 >> { Ng1491, n4903, n4901, Ng1496, n4864, n4907_1 }; + assign n6676_1 = 64'h0000800080008000 >> { n4897_1, Ng1481, n6675, n4913, n4914, n4915 }; + assign n6677 = 64'he4e44464f7e47764 >> { n4990, n4963, n5010, n4976, n5011_1, n4987 }; + assign n6678 = 64'h0100230021202320 >> { n4988, n4989, n6677, n5009, n5012, n5011_1 }; + assign n6679 = 64'h0000066006600000 >> { Ng797, n5007, n5003, Ng801, n5006_1, Ng805 }; + assign n6680 = 64'h0000000000004182 >> { n4986, n5008, Ng813, n5004, n4968, n5005 }; + assign n6681_1 = 32'd2147483648 >> { n6679, n6680, Ng2257, n4996, n5000 }; + assign n6682 = 64'he4e44464f7e47764 >> { n5106_1, n5062, n5113, n5075, n5114, n5087 }; + assign n6683 = 64'h2200222032103230 >> { n5112, n5089, n5117, n6682, n5115, n5114 }; + assign n6684 = 64'h727272727272fa72 >> { n4793, n4803, n4757, n4805, n4770_1, n4809 }; + assign n6685 = 64'h0101100011001100 >> { Ng2257, n6684, n4791, n4809, n4792, n4813 }; + assign n6686_1 = 32'd3998109262 >> { n4990, n4963, n5010, n4976, n5011_1 }; + assign n6687 = 64'h0101100011001100 >> { Ng2257, n6686_1, n4988, n5011_1, n5009, n5012 }; + assign n6688 = 64'h0000066006600000 >> { Ng117, n5099, n5098, Ng121, Ng125, n5093 }; + assign n6689 = 16'h8000 >> { n6688, n5094, n5178, n5179_1 }; + assign n6690 = 64'h2b3f01172a3f0017 >> { n5447, n5443, n5442, n5445, n5449_1, n5446 }; + assign n6691_1 = 64'h0001100101011111 >> { n6690, n5450, n5444_1, n5445, n5440, n5451 }; + assign n6692 = 64'h0008080000808000 >> { Ng2734, Ng2727, n4589_1, n4590, n5802, n5803 }; + assign n6693 = 64'h0000066006600000 >> { Ng2760, n4591, Ng2740, n4598, n4596, Ng2714 }; + assign n6694 = 16'h0888 >> { n6693, n6692, n4593, n5804_1 }; + assign n6695 = 64'h0008080000808000 >> { Ng2040, Ng2033, n4645, n4635, n5825, n5826 }; + assign n6696_1 = 64'h0000066006600000 >> { Ng2013, n4639, Ng2066, n4644, n4643, Ng2046 }; + assign n6697 = 16'h0888 >> { n6696_1, n6695, n4641, n5827 }; + assign n6698 = 64'h0000066006600000 >> { Ng2138, n4800, Ng2129, n4802_1, Ng2124, n4765 }; + assign n6699 = 64'h0000000000808000 >> { n5569_1, Ng2156, n4795, n6698, n6547, n6548_1 }; + assign n6216 = 8'h51 >> { n5568, n6699, n4830_1 }; + assign n6701_1 = 64'h0028002800280000 >> { Ng92, n5085, n5569_1, Ng88, n5069, n6563_1 }; + assign n6702 = 64'h0000066006600660 >> { Ng52, n5066_1, Ng70, n5067, Ng56, n5079 }; + assign n1713 = 32'd1431639381 >> { n5692, n6701_1, n6702, n6561, n5136_1 }; + assign n6704 = 32'd3205829909 >> { Ng3104, n4534_1, n4531, Ng3106, Ng3120 }; + assign n6705 = 64'h128852881a885a88 >> { Ng3100, Ng3098, Ng3139, n6704, n4530, Ng3120 }; + assign n6706_1 = 64'h0002000200020202 >> { Ng2991, Ng2992, n4527, Pg25420, n4536, n6653 }; + assign n944 = 16'h828a >> { Ng3099, Ng3139, n6705, n6706_1 }; + assign n6708 = 64'hd5c4c4c4d5808080 >> { Ng3095, Ng3091, n4534_1, Ng3096, n4531, Ng3139 }; + assign n6709 = 64'h0002020200aaaaaa >> { n4527, n6708, Ng3120, Ng2985, Ng2984, n4543 }; + assign n6710 = 64'ha22a2aa2f77f7ff7 >> { Ng2631, n4596, n4602, n6656_1, Ng2584, Ng8311 }; + assign n6711_1 = 64'h7dd77dd728827dd7 >> { n4607, n4606, n4576, n4604_1, n4605, Ng2631 }; + assign n7170 = 64'h0001000300000002 >> { Ng8311, n6711_1, Pg2637, Ng2633, n6490_1, n6710 }; + assign n6713 = 64'h6666666669966666 >> { n4713, n4728, n4724, n4726_1, n4732, n4734_1 }; + assign n7035 = 32'd2183725055 >> { n4735, n6713, n4730_1, n6668, Ng510 }; + assign n6715 = 64'he4e44464f7e47764 >> { n4886, n4858, n4885, n4871, n4911, n4883_1 }; + assign n6716_1 = 64'ha020a020a8a8a020 >> { n4884, n4910, n6674, n6715, n4911, n4912_1 }; + assign n7233 = Pg16496; + assign n7229 = Pg5388; + assign n6656 = Pg16437; + assign n6647_1 = Ng8311; + assign n6508 = Ng2632; + assign n6499 = Ng2623; + assign n6485_1 = Ng2617; + assign n6476 = Ng2609; + assign n6472 = Ng2602; + assign n6394 = Ng2642; + assign n6390 = Ng11595; + assign n6385 = Ng2640; + assign n6381 = Ng11594; + assign n6376 = Ng2648; + assign n6372 = Ng11598; + assign n6367 = Ng2646; + assign n6363_1 = Ng11597; + assign n6358_1 = Ng2644; + assign n6354 = Ng11596; + assign n6349_1 = Ng2638; + assign n6345_1 = Ng11593; + assign n6340 = Ng2597; + assign n6336_1 = Ng2587; + assign n6312 = Ng2472; + assign n6308 = Ng11589; + assign n6304 = Ng2470; + assign n6300 = Ng11588; + assign n6296 = Ng2462; + assign n6292 = Ng11587; + assign n6288 = Ng2457; + assign n6284 = Ng11586; + assign n6280 = Ng2455; + assign n6276 = Ng11585; + assign n6272 = Ng2447; + assign n6268 = Ng11584; + assign n6264 = Ng2442; + assign n6260 = Ng11583; + assign n6256 = Ng2440; + assign n6252 = Ng11582; + assign n6248 = Ng2432; + assign n6244_1 = Ng11581; + assign n6240 = Ng2427; + assign n6236 = Ng11580; + assign n6232 = Ng2425; + assign n6228 = Ng11579; + assign n6224 = Ng2417; + assign n6220 = Ng11578; + assign n6201 = Ng2365; + assign n6197 = Ng13455; + assign n6193 = Ng2363; + assign n6184 = Ng2361; + assign n6175 = Ng2359; + assign n6166 = Ng2357; + assign n6157 = Ng2355; + assign n6148 = Ng2529; + assign n6139 = Ng2527; + assign n6130 = Ng2525; + assign n5896 = Pg5549; + assign n5893_1 = Ng2256; + assign n5154 = Pg16399; + assign n5145_1 = Ng8302; + assign n5006 = Ng1938; + assign n4997 = Ng1929; + assign n4983_1 = Ng1923; + assign n4974 = Ng1915; + assign n4970 = Ng1908; + assign n4892 = Ng1948; + assign n4888_1 = Ng11568; + assign n4883 = Ng1946; + assign n4879 = Ng11567; + assign n4874 = Ng1954; + assign n4870 = Ng11571; + assign n4865 = Ng1952; + assign n4861_1 = Ng11570; + assign n4856_1 = Ng1950; + assign n4852 = Ng11569; + assign n4847 = Ng1944; + assign n4843 = Ng11566; + assign n4838_1 = Ng1903; + assign n4834_1 = Ng1893; + assign n4810 = Ng1778; + assign n4806 = Ng11562; + assign n4802 = Ng1776; + assign n4798 = Ng11561; + assign n4794 = Ng1768; + assign n4790 = Ng11560; + assign n4786 = Ng1763; + assign n4782 = Ng11559; + assign n4778 = Ng1761; + assign n4774 = Ng11558; + assign n4770 = Ng1753; + assign n4766 = Ng11557; + assign n4762 = Ng1748; + assign n4758 = Ng11556; + assign n4754 = Ng1746; + assign n4750 = Ng11555; + assign n4746 = Ng1738; + assign n4742_1 = Ng11554; + assign n4738 = Ng1733; + assign n4734 = Ng11553; + assign n4730 = Ng1731; + assign n4726 = Ng11552; + assign n4722 = Ng1723; + assign n4718 = Ng11551; + assign n4699 = Ng1671; + assign n4695 = Ng13439; + assign n4691 = Ng1669; + assign n4682 = Ng1667; + assign n4673 = Ng1665; + assign n4664 = Ng1663; + assign n4655 = Ng1661; + assign n4646 = Ng1835; + assign n4637 = Ng1833; + assign n4628 = Ng1831; + assign n3714 = Pg5648; + assign n3711 = Pg5629; + assign n3708 = Ng13475; + assign n3653 = Pg16355; + assign n3644 = Ng8293; + assign n3505 = Ng1244; + assign n3496 = Ng1235; + assign n3482 = Ng1229; + assign n3473 = Ng1221; + assign n3469 = Ng1214; + assign n3391 = Ng1254; + assign n3387 = Ng11541; + assign n3382 = Ng1252; + assign n3378 = Ng11540; + assign n3373 = Ng1260; + assign n3369 = Ng11544; + assign n3364 = Ng1258; + assign n3360 = Ng11543; + assign n3355 = Ng1256; + assign n3351 = Ng11542; + assign n3346 = Ng1250; + assign n3342 = Ng11539; + assign n3337 = Ng1209; + assign n3333 = Ng1199; + assign n3309 = Ng1084; + assign n3305 = Ng11535; + assign n3301 = Ng1082; + assign n3297 = Ng11534; + assign n3293 = Ng1074; + assign n3289 = Ng11533; + assign n3285 = Ng1069; + assign n3281 = Ng11532; + assign n3277 = Ng1067; + assign n3273 = Ng11531; + assign n3269 = Ng1059; + assign n3265 = Ng11530; + assign n3261 = Ng1054; + assign n3257 = Ng11529; + assign n3253 = Ng1052; + assign n3249 = Ng11528; + assign n3245 = Ng1044; + assign n3241 = Ng11527; + assign n3237 = Ng1039; + assign n3233 = Ng11526; + assign n3229 = Ng1037; + assign n3225 = Ng11525; + assign n3221 = Ng1029; + assign n3217 = Ng11524; + assign n3198 = Ng977; + assign n3194 = Ng13423; + assign n3190 = Ng975; + assign n3181 = Ng973; + assign n3172 = Ng971; + assign n3163 = Ng969; + assign n3154 = Ng967; + assign n3145 = Ng1141; + assign n3136 = Ng1139; + assign n3127 = Ng1137; + assign n2483 = Pg6313; + assign n2480 = Pg5437; + assign n2477 = Ng13457; + assign n2153 = Pg16297; + assign n2144 = Ng8284; + assign n2005 = Ng558; + assign n1996 = Ng549; + assign n1982 = Ng543; + assign n1973 = Ng535; + assign n1969 = Ng528; + assign n1891 = Ng568; + assign n1887 = Ng11514; + assign n1882 = Ng566; + assign n1878 = Ng11513; + assign n1873 = Ng574; + assign n1869 = Ng11517; + assign n1864 = Ng572; + assign n1860 = Ng11516; + assign n1855 = Ng570; + assign n1851 = Ng11515; + assign n1846 = Ng564; + assign n1842 = Ng11512; + assign n1837 = Ng523; + assign n1833_1 = Ng513; + assign n1809 = Ng397; + assign n1805 = Ng11508; + assign n1801 = Ng395; + assign n1797 = Ng11507; + assign n1793 = Ng387; + assign n1789 = Ng11506; + assign n1785 = Ng382; + assign n1781 = Ng11505; + assign n1777 = Ng380; + assign n1773 = Ng11504; + assign n1769 = Ng372; + assign n1765 = Ng11503; + assign n1761 = Ng367; + assign n1757 = Ng11502; + assign n1753 = Ng365; + assign n1749 = Ng11501; + assign n1745 = Ng357; + assign n1741 = Ng11500; + assign n1737 = Ng352; + assign n1733 = Ng11499; + assign n1729 = Ng350; + assign n1725 = Ng11498; + assign n1721 = Ng342; + assign n1717 = Ng11497; + assign n1698 = Ng290; + assign n1694 = Ng13407; + assign n1690 = Ng288; + assign n1681 = Ng286; + assign n1672 = Ng284; + assign n1663 = Ng282; + assign n1654 = Ng280; + assign n1645 = Ng454; + assign n1636 = Ng452; + assign n1627 = Ng450; + assign n978 = Pg26135; + assign n974 = Pg26149; + assign n970 = Pg27380; + assign n966 = Pg25435; + assign n962 = Pg26104; + assign n948 = Pg25420; + assign n939 = Pg24734; + assign n710 = Pg8096; + assign n706 = Pg4450; + assign n702 = Pg4200; + assign n698 = Pg3993; + assign n694_1 = Pg8175; + assign n690 = Pg8023; + assign n686 = Pg4321; + assign n682 = Pg4088; + assign n678 = Pg8249; + assign n674_1 = Pg7519; + assign n670 = Pg7334; + assign n666 = Pg6895; + assign n662 = Pg6442; + assign n658 = Pg6225; + assign n654 = Pg4590; + assign n650 = Pg4323; + assign n646 = Pg4090; + assign n642 = Pg8251; + assign n593 = Pg3213; + assign n589 = Pg3214; + assign n585 = Pg3215; + assign n581 = Pg3216; + assign n577 = Pg3217; + assign n573 = Pg3218; + assign n569 = Pg3219; + assign n565 = Pg3220; + assign n561 = Pg3232; + assign n557 = Pg3221; + assign n553 = Pg3222; + assign n549 = Pg3223; + assign n545 = Pg3224; + assign n541 = Pg3225; + assign n537 = Pg3226; + assign n533 = Pg3227; + assign n529 = Pg3228; + assign n525 = Pg3212; + assign n516 = Pg8021; + assign n401 = Pg3234; + assign n378 = Pg51; + assign Pg8167 = Pg6313; + assign Pg8106 = Pg5629; + assign Pg8087 = Pg5437; + assign Pg8082 = Pg6313; + assign Pg8030 = Pg5648; + assign Pg8012 = Pg5437; + assign Pg8007 = Pg6313; + assign Pg7961 = Pg5437; + assign Pg7956 = Pg6313; + assign Pg7909 = Pg5437; + assign Pg7487 = Pg5648; + assign Pg7425 = Pg5629; + assign Pg7390 = Pg5648; + assign Pg7357 = Pg5648; + assign Pg7302 = Pg5629; + assign Pg7264 = Pg6313; + assign Pg7229 = Pg5629; + assign Pg7194 = Pg5648; + assign Pg7161 = Pg5648; + assign Pg7084 = Pg6313; + assign Pg7052 = Pg5629; + assign Pg7014 = Pg6313; + assign Pg6979 = Pg5629; + assign Pg6944 = Pg5648; + assign Pg6911 = Pg5648; + assign Pg6837 = Pg5437; + assign Pg6782 = Pg6313; + assign Pg6750 = Pg5629; + assign Pg6712 = Pg6313; + assign Pg6677 = Pg5629; + assign Pg6642 = Pg5648; + assign Pg6573 = Pg5437; + assign Pg6518 = Pg6313; + assign Pg6485 = Pg5629; + assign Pg6447 = Pg6313; + assign Pg6368 = Pg5437; + assign Pg6231 = Pg5437; + assign Pg5796 = Pg5648; + assign Pg5747 = Pg5629; + assign Pg5738 = Pg5648; + assign Pg5695 = Pg5629; + assign Pg5686 = Pg5648; + assign Pg5657 = Pg5629; + assign Pg5637 = Pg5549; + assign Pg5612 = Pg5549; + assign Pg5595 = Pg5549; + assign Pg5555 = Pg5437; + assign Pg5511 = Pg5437; + assign Pg5472 = Pg5437; + assign Pg25442 = Pg25420; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act b/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act new file mode 100644 index 000000000..038bef6dc --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act @@ -0,0 +1,3643 @@ +clock 0.502000 0.493200 +Pg6753 0.493600 0.511200 +Pg6752 0.499000 0.497800 +Pg6751 0.501600 0.504600 +Pg6750 0.518000 0.497200 +Pg6749 0.497800 0.496800 +Pg6748 0.507000 0.501800 +Pg6747 0.508000 0.499200 +Pg6746 0.489200 0.506400 +Pg6745 0.496800 0.506000 +Pg6744 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a/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif b/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif new file mode 100644 index 000000000..a73a516f2 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif @@ -0,0 +1,9097 @@ +# Benchmark "s38584" written by ABC on Tue Mar 12 09:43:19 2019 +.model s38584 +.inputs clock Pg6753 Pg6752 Pg6751 Pg6750 Pg6749 Pg6748 Pg6747 Pg6746 \ + Pg6745 Pg6744 Pg135 Pg134 Pg127 Pg126 Pg125 Pg124 Pg120 Pg116 Pg115 Pg114 \ + Pg113 Pg100 Pg99 Pg92 Pg91 Pg90 Pg84 Pg73 Pg72 Pg64 Pg57 Pg56 Pg54 Pg53 \ + Pg44 Pg36 Pg35 Pg5 +.outputs Pg34972 Pg34956 Pg34927 Pg34925 Pg34923 Pg34921 Pg34919 Pg34917 \ + Pg34915 Pg34913 Pg34839 Pg34788 Pg34597 Pg34437 Pg34436 Pg34435 Pg34425 \ + Pg34383 Pg34240 Pg34239 Pg34238 Pg34237 Pg34236 Pg34235 Pg34234 Pg34233 \ + Pg34232 Pg34221 Pg34201 Pg33959 Pg33950 Pg33949 Pg33948 Pg33947 Pg33946 \ + Pg33945 Pg33935 Pg33894 Pg33874 Pg33659 Pg33636 Pg33533 Pg33435 Pg33079 \ + Pg32975 Pg32454 Pg32429 Pg32185 Pg31863 Pg31862 Pg31861 Pg31860 Pg31793 \ + Pg31665 Pg31656 Pg31521 Pg30332 Pg30331 Pg30330 Pg30329 Pg30327 Pg29221 \ + Pg29220 Pg29219 Pg29218 Pg29217 Pg29216 Pg29215 Pg29214 Pg29213 Pg29212 \ + Pg29211 Pg29210 Pg28753 Pg28042 Pg28041 Pg28030 Pg27831 Pg26877 Pg26876 \ + Pg26875 Pg26801 Pg25590 Pg25589 Pg25588 Pg25587 Pg25586 Pg25585 Pg25584 \ + Pg25583 Pg25582 Pg25259 Pg25219 Pg25167 Pg25114 Pg24185 Pg24184 Pg24183 \ + Pg24182 Pg24181 Pg24180 Pg24179 Pg24178 Pg24177 Pg24176 Pg24175 Pg24174 \ + Pg24173 Pg24172 Pg24171 Pg24170 Pg24169 Pg24168 Pg24167 Pg24166 Pg24165 \ + Pg24164 Pg24163 Pg24162 Pg24161 Pg24151 Pg23759 Pg23683 Pg23652 Pg23612 \ + Pg23190 Pg23002 Pg21727 Pg21698 Pg21292 Pg21270 Pg21245 Pg21176 Pg20901 \ + Pg20899 Pg20763 Pg20654 Pg20652 Pg20557 Pg20049 Pg19357 Pg19334 Pg18881 \ + Pg18101 Pg18100 Pg18099 Pg18098 Pg18097 Pg18096 Pg18095 Pg18094 Pg18092 \ + Pg17871 Pg17845 Pg17819 Pg17813 Pg17787 Pg17778 Pg17764 Pg17760 Pg17743 \ + Pg17739 Pg17722 Pg17715 Pg17711 Pg17688 Pg17685 Pg17678 Pg17674 Pg17649 \ + Pg17646 Pg17639 Pg17607 Pg17604 Pg17580 Pg17577 Pg17519 Pg17423 Pg17404 \ + Pg17400 Pg17320 Pg17316 Pg17291 Pg16955 Pg16924 Pg16874 Pg16775 Pg16748 \ + Pg16744 Pg16722 Pg16718 Pg16693 Pg16686 Pg16659 Pg16656 Pg16627 Pg16624 \ + Pg16603 Pg14828 Pg14779 Pg14749 Pg14738 Pg14705 Pg14694 Pg14673 Pg14662 \ + Pg14635 Pg14597 Pg14518 Pg14451 Pg14421 Pg14217 Pg14201 Pg14189 Pg14167 \ + Pg14147 Pg14125 Pg14096 Pg13966 Pg13926 Pg13906 Pg13895 Pg13881 Pg13865 \ + Pg13272 Pg13259 Pg13099 Pg13085 Pg13068 Pg13049 Pg13039 Pg12923 Pg12919 \ + Pg12833 Pg12832 Pg12470 Pg12422 Pg12368 Pg12350 Pg12300 Pg12238 Pg12184 \ + Pg11770 Pg11678 Pg11447 Pg11418 Pg11388 Pg11349 Pg10527 Pg10500 Pg10306 \ + Pg10122 Pg9817 Pg9743 Pg9741 Pg9682 Pg9680 Pg9617 Pg9615 Pg9555 Pg9553 \ + Pg9497 Pg9251 Pg9048 Pg9019 Pg8920 Pg8919 Pg8918 Pg8917 Pg8916 Pg8915 \ + Pg8870 Pg8839 Pg8789 Pg8788 Pg8787 Pg8786 Pg8785 Pg8784 Pg8783 Pg8719 \ + Pg8475 Pg8416 Pg8403 Pg8398 Pg8358 Pg8353 Pg8344 Pg8342 Pg8291 Pg8283 \ + Pg8279 Pg8277 Pg8235 Pg8215 Pg8178 Pg8132 Pg7946 Pg7916 Pg7540 Pg7260 \ + Pg7257 Pg7245 Pg7243 + +.latch n687_1 Pg19357 re clock 0 +.latch n691 Pg19334 re clock 0 +.latch n694 Pg17871 re clock 0 +.latch n697 Pg17845 re clock 0 +.latch n700 Pg17819 re clock 0 +.latch n703 Pg17813 re clock 0 +.latch n706 Pg17787 re clock 0 +.latch n709 Pg17778 re clock 0 +.latch n712_1 Pg17764 re clock 0 +.latch n715 Pg17760 re clock 0 +.latch n718 Pg17743 re clock 0 +.latch n721 Pg17739 re clock 0 +.latch n724 Pg17722 re clock 0 +.latch n727 Pg17715 re clock 0 +.latch n730 Pg17711 re clock 0 +.latch n733 Pg17688 re clock 0 +.latch n736 Pg17685 re clock 0 +.latch n739 Pg17678 re clock 0 +.latch n742 Pg17674 re clock 0 +.latch n745 Pg17649 re clock 0 +.latch n748 Pg17646 re clock 0 +.latch n751 Pg17639 re clock 0 +.latch n754 Pg17607 re clock 0 +.latch n757 Pg17604 re clock 0 +.latch n760 Pg17580 re clock 0 +.latch n763 Pg17577 re clock 0 +.latch n766 Pg17519 re clock 0 +.latch n769 Pg17423 re clock 0 +.latch n772 Pg17404 re clock 0 +.latch n775 Pg17400 re clock 0 +.latch n779 Pg17320 re clock 0 +.latch n782 Pg17316 re clock 0 +.latch n786 Pg17291 re clock 0 +.latch n789 Pg16955 re clock 0 +.latch n792 Pg16924 re clock 0 +.latch n795 Pg16874 re clock 0 +.latch n798 Pg16775 re clock 0 +.latch n801 Pg16748 re clock 0 +.latch n804 Pg16744 re clock 0 +.latch n807 Pg16722 re clock 0 +.latch n810 Pg16718 re clock 0 +.latch n813 Pg16693 re clock 0 +.latch n816 Pg16686 re clock 0 +.latch n819 Pg16659 re clock 0 +.latch n822 Pg16656 re clock 0 +.latch n825 Pg16627 re clock 0 +.latch n828 Pg16624 re clock 0 +.latch n831 Pg16603 re clock 0 +.latch n834 Pg14828 re clock 0 +.latch n837 Pg14779 re clock 0 +.latch n840 Pg14749 re clock 0 +.latch n843 Pg14738 re clock 0 +.latch n846 Pg14705 re clock 0 +.latch n849 Pg14694 re clock 0 +.latch n852 Pg14673 re clock 0 +.latch n855 Pg14662 re clock 0 +.latch n858 Pg14635 re clock 0 +.latch n861 Pg14597 re clock 0 +.latch n864 Pg14518 re clock 0 +.latch n867 Pg14451 re clock 0 +.latch n870 Pg14421 re clock 0 +.latch n873 Pg14217 re clock 0 +.latch n876 Pg14201 re clock 0 +.latch n880 Pg14189 re clock 0 +.latch n883 Pg14167 re clock 0 +.latch n886 Pg14147 re clock 0 +.latch n889 Pg14125 re clock 0 +.latch n892 Pg14096 re clock 0 +.latch n895 Pg13966 re clock 0 +.latch n898 Pg13926 re clock 0 +.latch n901 Pg13906 re clock 0 +.latch n904 Pg13895 re clock 0 +.latch n907 Pg13881 re clock 0 +.latch n910 Pg13865 re clock 0 +.latch n913 Pg13272 re clock 0 +.latch n916 Pg13259 re clock 0 +.latch n919 Pg13099 re clock 0 +.latch n922 Pg13085 re clock 0 +.latch n925 Pg13068 re clock 0 +.latch n928 Pg13049 re clock 0 +.latch n931 Pg13039 re clock 0 +.latch n935 Pg12923 re clock 0 +.latch n939 Pg12919 re clock 0 +.latch n943 Pg12832 re clock 0 +.latch n947 Pg12470 re clock 0 +.latch n951 Pg12422 re clock 0 +.latch n955 Pg12368 re clock 0 +.latch n959 Pg12350 re clock 0 +.latch n963 Pg12300 re clock 0 +.latch n967 Pg12238 re clock 0 +.latch n971 Pg12184 re clock 0 +.latch n975 Pg11770 re clock 0 +.latch n978 Pg11678 re clock 0 +.latch n982 Pg11447 re clock 0 +.latch n986 Pg11418 re clock 0 +.latch n990 Pg11388 re clock 0 +.latch n994 Pg11349 re clock 0 +.latch n998 Pg10527 re clock 0 +.latch n1002 Pg10500 re clock 0 +.latch n1006 Pg10306 re clock 0 +.latch n1010 Pg10122 re clock 0 +.latch n1014 Pg9817 re clock 0 +.latch n1018 Pg9743 re clock 0 +.latch n1022 Pg9741 re clock 0 +.latch n1026 Pg9682 re clock 0 +.latch n1030 Pg9680 re clock 0 +.latch n1034 Pg9617 re clock 0 +.latch n1038 Pg9615 re clock 0 +.latch n1042 Pg9555 re clock 0 +.latch n1046 Pg9553 re clock 0 +.latch n1050 Pg9497 re clock 0 +.latch n1054 Pg9251 re clock 0 +.latch n1057 Pg9048 re clock 0 +.latch n1061 Pg9019 re clock 0 +.latch n1064 Pg8920 re clock 0 +.latch n1067 Pg8919 re clock 0 +.latch n1070 Pg8918 re clock 0 +.latch n1073 Pg8917 re clock 0 +.latch n1076 Pg8916 re clock 0 +.latch n1079 Pg8915 re clock 0 +.latch n1082_1 Pg8870 re clock 0 +.latch n1086 Pg8839 re clock 0 +.latch n1089 Pg8789 re clock 0 +.latch n1092 Pg8788 re clock 0 +.latch n1095 Pg8787 re clock 0 +.latch n1098 Pg8786 re clock 0 +.latch n1101 Pg8785 re clock 0 +.latch n1104 Pg8784 re clock 0 +.latch n1107 Pg8783 re clock 0 +.latch n1111 Pg8719 re clock 0 +.latch n1114 Pg8475 re clock 0 +.latch n1117_1 Pg8416 re clock 0 +.latch n1121 Pg8398 re clock 0 +.latch n1125 Pg8358 re clock 0 +.latch n1129 Pg8344 re clock 0 +.latch n1133 Pg8342 re clock 0 +.latch n1137 Pg8291 re clock 0 +.latch n1141 Pg8279 re clock 0 +.latch n1145 Pg8277 re clock 0 +.latch n1149 Pg8215 re clock 0 +.latch n1153 Pg7946 re clock 0 +.latch n1157 Pg7916 re clock 0 +.latch n1161 Pg7540 re clock 0 +.latch n1165 Pg7260 re clock 0 +.latch n1169 Pg7257 re clock 0 +.latch n1173 Pg7245 re clock 0 +.latch n1177 Pg7243 re clock 0 +.latch n1181_1 Ng5057 re clock 0 +.latch n1186_1 Ng2771 re clock 0 +.latch n1191 Ng1882 re clock 0 +.latch n1196 Ng2299 re clock 0 +.latch n1201 Ng4040 re clock 0 +.latch n1206 Ng2547 re clock 0 +.latch n1210 Ng559 re clock 0 +.latch n1215 Ng3243 re clock 0 +.latch n1220 Ng452 re clock 0 +.latch n1225 Ng3542 re clock 0 +.latch n1230 Ng5232 re clock 0 +.latch n1235 Ng5813 re clock 0 +.latch n1240 Ng2907 re clock 0 +.latch n1245 Ng1744 re clock 0 +.latch n1250 Ng5909 re clock 0 +.latch n1255 Ng1802 re clock 0 +.latch n1260 Ng3554 re clock 0 +.latch n1265 Ng6219 re clock 0 +.latch n1270 Ng807 re clock 0 +.latch n1274 Ng6031 re clock 0 +.latch n1279 Ng847 re clock 0 +.latch n1284 Ng976 re clock 0 +.latch n1289 Ng4172 re clock 0 +.latch n1294 Ng4372 re clock 0 +.latch n1299 Ng3512 re clock 0 +.latch n1304 Ng749 re clock 0 +.latch n1309 Ng3490 re clock 0 +.latch n1313 Ng4235 re clock 0 +.latch n1318 Ng1600 re clock 0 +.latch n1323 Ng1714 re clock 0 +.latch n1328 Ng3155 re clock 0 +.latch n1333 Ng2236 re clock 0 +.latch n1338 Ng4555 re clock 0 +.latch n1343 Ng3698 re clock 0 +.latch n1348 Ng1736 re clock 0 +.latch n1353 Ng1968 re clock 0 +.latch n1358 Ng4621 re clock 0 +.latch n1363 Ng5607 re clock 0 +.latch n1368 Ng2657 re clock 0 +.latch n1373 Ng490 re clock 0 +.latch n1378 Ng311 re clock 0 +.latch n1383 Ng772 re clock 0 +.latch n1388 Ng5587 re clock 0 +.latch n1393 Ng6177 re clock 0 +.latch n1397 Ng6377 re clock 0 +.latch n1402 Ng3167 re clock 0 +.latch n1407 Ng5615 re clock 0 +.latch n1412 Ng4567 re clock 0 +.latch n1417 Ng3457 re clock 0 +.latch n1422 Ng6287 re clock 0 +.latch n1427 Ng2563 re clock 0 +.latch n1432 Ng4776 re clock 0 +.latch n1437 Ng4593 re clock 0 +.latch n1442 Ng6199 re clock 0 +.latch n1447_1 Ng2295 re clock 0 +.latch n1452 Ng1384 re clock 0 +.latch n1457_1 Ng1339 re clock 0 +.latch n1462 Ng5180 re clock 0 +.latch n1467_1 Ng2844 re clock 0 +.latch n1472 Ng1024 re clock 0 +.latch n1477_1 Ng5591 re clock 0 +.latch n1482 Ng3598 re clock 0 +.latch n1487 Ng4264 re clock 0 +.latch n1492 Ng767 re clock 0 +.latch n1497 Ng5853 re clock 0 +.latch n1502 Ng2089 re clock 0 +.latch n1507 Ng4933 re clock 0 +.latch n1512 Ng4521 re clock 0 +.latch n1517_1 Ng5507 re clock 0 +.latch n1522 Ng6291 re clock 0 +.latch n1527_1 Ng294 re clock 0 +.latch n1532 Ng5559 re clock 0 +.latch n1537 Ng3813 re clock 0 +.latch n1542 Ng562 re clock 0 +.latch n1547 Ng608 re clock 0 +.latch n1552 Ng1205 re clock 0 +.latch n1557 Ng3909 re clock 0 +.latch n1562 Ng6259 re clock 0 +.latch n1567_1 Ng5905 re clock 0 +.latch n1572 Ng921 re clock 0 +.latch n1577 Ng2955 re clock 0 +.latch n1582 Ng203 re clock 0 +.latch n1587 Ng1099 re clock 0 +.latch n1592 Ng4878 re clock 0 +.latch n1597 Ng5204 re clock 0 +.latch n1602 Ng3606 re clock 0 +.latch n1607 Ng1926 re clock 0 +.latch n1612 Ng6215 re clock 0 +.latch n1617 Ng3586 re clock 0 +.latch n1622 Ng291 re clock 0 +.latch n1627 Ng4674 re clock 0 +.latch n1632 Ng3570 re clock 0 +.latch n1637 Ng1862 re clock 0 +.latch n1642 Ng676 re clock 0 +.latch n1647 Ng843 re clock 0 +.latch n1652 Ng4332 re clock 0 +.latch n1657 Ng4153 re clock 0 +.latch n1662 Ng6336 re clock 0 +.latch n1667 Ng622 re clock 0 +.latch n1672 Ng3506 re clock 0 +.latch n1677 Ng4558 re clock 0 +.latch n1682 Ng3111 re clock 0 +.latch n1687 Pg21270 re clock 0 +.latch n1691 Ng26936 re clock 0 +.latch n1696 Ng939 re clock 0 +.latch n1701 Ng278 re clock 0 +.latch n1706 Ng4492 re clock 0 +.latch n1711 Ng4864 re clock 0 +.latch n1716 Ng1036 re clock 0 +.latch n1721 Pg21245 re clock 0 +.latch n1725 Ng1178 re clock 0 +.latch n1730 Ng3239 re clock 0 +.latch n1735 Ng718 re clock 0 +.latch n1740 Ng6195 re clock 0 +.latch n1745 Ng1135 re clock 0 +.latch n1750 Ng6395 re clock 0 +.latch n1755 Pg25219 re clock 0 +.latch n1759 Ng554 re clock 0 +.latch n1764 Ng496 re clock 0 +.latch n1769 Ng3853 re clock 0 +.latch n1774 Ng5134 re clock 0 +.latch n1779 Ng2485 re clock 0 +.latch n1784 Ng925 re clock 0 +.latch n1789 Ng48 re clock 0 +.latch n1794 Ng5555 re clock 0 +.latch n1799 Ng1798 re clock 0 +.latch n1804 Ng4076 re clock 0 +.latch n1809 Ng2941 re clock 0 +.latch n1814 Ng3905 re clock 0 +.latch n1819 Ng763 re clock 0 +.latch n1824 Ng6255 re clock 0 +.latch n1829 Ng4375 re clock 0 +.latch n1834 Ng4871 re clock 0 +.latch n1839 Ng4722 re clock 0 +.latch n1844 Ng590 re clock 0 +.latch n1849 Ng1632 re clock 0 +.latch n1853 Ng3100 re clock 0 +.latch n1858 Ng1495 re clock 0 +.latch n1863 Ng1437 re clock 0 +.latch n1868_1 Ng6154 re clock 0 +.latch n1872 Ng1579 re clock 0 +.latch n1877 Ng5567 re clock 0 +.latch n1882 Ng1752 re clock 0 +.latch n1887 Ng1917 re clock 0 +.latch n1892 Ng744 re clock 0 +.latch n1897 Ng4737 re clock 0 +.latch n1902 Pg8132 re clock 0 +.latch n1906 Ng6267 re clock 0 +.latch n1911 Ng1442 re clock 0 +.latch n1916 Ng5965 re clock 0 +.latch n1921 Ng4477 re clock 0 +.latch n1926 Ng4643 re clock 0 +.latch n1931 Ng5264 re clock 0 +.latch n1936 Ng2610 re clock 0 +.latch n1941 Ng5160 re clock 0 +.latch n1946 Ng5933 re clock 0 +.latch n1951 Ng1454 re clock 0 +.latch n1956 Ng753 re clock 0 +.latch n1961 Ng1296 re clock 0 +.latch n1966 Ng3151 re clock 0 +.latch n1971 Ng2980 re clock 0 +.latch n1976 Ng6727 re clock 0 +.latch n1981 Ng3530 re clock 0 +.latch n1986 Ng4104 re clock 0 +.latch n1991 Ng1532 re clock 0 +.latch n1996 Ng2177 re clock 0 +.latch n2001 Ng52 re clock 0 +.latch n2006 Ng4754 re clock 0 +.latch n2011 Ng1189 re clock 0 +.latch n2016 Ng2287 re clock 0 +.latch n2021 Ng4273 re clock 0 +.latch n2026 Ng1389 re clock 0 +.latch n2031 Ng1706 re clock 0 +.latch n2036 Ng5835 re clock 0 +.latch n2041 Ng1171 re clock 0 +.latch n2046 Ng4269 re clock 0 +.latch n2051 Ng2399 re clock 0 +.latch n2056 Ng4983 re clock 0 +.latch n2061 Ng5611 re clock 0 +.latch n2066 Ng4572 re clock 0 +.latch n2071 Ng3143 re clock 0 +.latch n2076 Ng2898 re clock 0 +.latch n2081 Ng3343 re clock 0 +.latch n2086 Ng3235 re clock 0 +.latch n2091 Ng4543 re clock 0 +.latch n2096 Ng3566 re clock 0 +.latch n2101 Ng4534 re clock 0 +.latch n2106 Ng4961 re clock 0 +.latch n2111_1 Ng4927 re clock 0 +.latch n2116_1 Ng2259 re clock 0 +.latch n2121 Ng2819 re clock 0 +.latch n2125 Ng5802 re clock 0 +.latch n2130 Ng2852 re clock 0 +.latch n2135 Ng417 re clock 0 +.latch n2140 Ng681 re clock 0 +.latch n2145 Ng437 re clock 0 +.latch n2150 Ng351 re clock 0 +.latch n2155 Ng5901 re clock 0 +.latch n2160 Ng2886 re clock 0 +.latch n2165 Ng3494 re clock 0 +.latch n2170 Ng5511 re clock 0 +.latch n2175 Ng3518 re clock 0 +.latch n2180 Ng1604 re clock 0 +.latch n2185 Ng5092 re clock 0 +.latch n2190 Ng4831 re clock 0 +.latch n2195 Ng4382 re clock 0 +.latch n2200 Ng6386 re clock 0 +.latch n2205 Ng479 re clock 0 +.latch n2210 Ng3965 re clock 0 +.latch n2215 Ng4749 re clock 0 +.latch n2220 Ng2008 re clock 0 +.latch n2224 Ng736 re clock 0 +.latch n2229 Ng3933 re clock 0 +.latch n2234 Ng222 re clock 0 +.latch n2239 Ng3050 re clock 0 +.latch n2244 Ng1052 re clock 0 +.latch n2249 Ng2122 re clock 0 +.latch n2254 Ng2465 re clock 0 +.latch n2259 Ng5889 re clock 0 +.latch n2264 Ng4495 re clock 0 +.latch n2269 Ng4653 re clock 0 +.latch n2274 Ng3179 re clock 0 +.latch n2279 Ng1728 re clock 0 +.latch n2284 Ng2433 re clock 0 +.latch n2289 Ng3835 re clock 0 +.latch n2294 Ng6187 re clock 0 +.latch n2299 Ng4917 re clock 0 +.latch n2304 Ng1070 re clock 0 +.latch n2309 Ng822 re clock 0 +.latch n2314 Ng914 re clock 0 +.latch n2318 Ng5339 re clock 0 +.latch n2323 Ng4164 re clock 0 +.latch n2328 Ng969 re clock 0 +.latch n2333 Ng2807 re clock 0 +.latch n2338 Ng4054 re clock 0 +.latch n2343 Ng6191 re clock 0 +.latch n2348 Ng5077 re clock 0 +.latch n2353 Ng5523 re clock 0 +.latch n2357 Ng3680 re clock 0 +.latch n2362 Ng6637 re clock 0 +.latch n2367 Ng174 re clock 0 +.latch n2372 Ng1682 re clock 0 +.latch n2377 Ng355 re clock 0 +.latch n2381 Ng1087 re clock 0 +.latch n2386 Ng1105 re clock 0 +.latch n2391 Ng2342 re clock 0 +.latch n2396 Ng6307 re clock 0 +.latch n2400 Ng3802 re clock 0 +.latch n2405 Ng6159 re clock 0 +.latch n2410 Ng2255 re clock 0 +.latch n2415 Ng2815 re clock 0 +.latch n2420 Ng911 re clock 0 +.latch n2425 Ng43 re clock 0 +.latch n2430 Ng1748 re clock 0 +.latch n2435 Ng5551 re clock 0 +.latch n2440 Ng3558 re clock 0 +.latch n2445 Ng5499 re clock 0 +.latch n2450 Ng2960 re clock 0 +.latch n2455 Ng3901 re clock 0 +.latch n2460 Ng4888 re clock 0 +.latch n2465 Ng6251 re clock 0 +.latch n2470 Ng1373 re clock 0 +.latch n2475 Ng157 re clock 0 +.latch n2480 Ng2783 re clock 0 +.latch n2484 Ng4281 re clock 0 +.latch n2489 Ng3574 re clock 0 +.latch n2494 Ng2112 re clock 0 +.latch n2499 Ng1283 re clock 0 +.latch n2504 Ng433 re clock 0 +.latch n2508 Ng4297 re clock 0 +.latch n2513 Ng758 re clock 0 +.latch n2518 Ng4639 re clock 0 +.latch n2523 Ng6537 re clock 0 +.latch n2528 Ng5543 re clock 0 +.latch n2533 Ng5961 re clock 0 +.latch n2538 Ng6243 re clock 0 +.latch n2543 Ng632 re clock 0 +.latch n2548 Ng3889 re clock 0 +.latch n2553 Ng3476 re clock 0 +.latch n2558 Ng1664 re clock 0 +.latch n2563 Ng1246 re clock 0 +.latch n2568 Ng6629 re clock 0 +.latch n2573 Ng246 re clock 0 +.latch n2578 Ng4049 re clock 0 +.latch n2583 Ng2932 re clock 0 +.latch n2588 Ng4575 re clock 0 +.latch n2593 Ng4098 re clock 0 +.latch n2598 Ng4498 re clock 0 +.latch n2603 Ng528 re clock 0 +.latch n2608 Ng16 re clock 0 +.latch n2613 Ng3139 re clock 0 +.latch n2618 Pg20901 re clock 0 +.latch n2622 Ng4584 re clock 0 +.latch n2627 Ng142 re clock 0 +.latch n2632 Ng5831 re clock 0 +.latch n2637 Ng239 re clock 0 +.latch n2642 Ng1216 re clock 0 +.latch n2647 Ng2848 re clock 0 +.latch n2652 Ng5022 re clock 0 +.latch n2657 Ng1030 re clock 0 +.latch n2662 Ng3231 re clock 0 +.latch n2666 Ng1430 re clock 0 +.latch n2670 Ng4452 re clock 0 +.latch n2675 Ng2241 re clock 0 +.latch n2680 Ng1564 re clock 0 +.latch n2684 Ng6148 re clock 0 +.latch n2689 Ng6649 re clock 0 +.latch n2694 Ng110 re clock 0 +.latch n2699 Ng225 re clock 0 +.latch n2704 Ng4486 re clock 0 +.latch n2709 Ng4504 re clock 0 +.latch n2714 Ng5873 re clock 0 +.latch n2719 Ng5037 re clock 0 +.latch n2724 Ng2319 re clock 0 +.latch n2729 Ng5495 re clock 0 +.latch n2734 Ng5208 re clock 0 +.latch n2739 Ng5579 re clock 0 +.latch n2744 Ng5869 re clock 0 +.latch n2749 Ng1589 re clock 0 +.latch n2754 Ng5752 re clock 0 +.latch n2759 Ng6279 re clock 0 +.latch n2764 Ng5917 re clock 0 +.latch n2769 Ng2975 re clock 0 +.latch n2774 Ng6167 re clock 0 +.latch n2779 Ng2599 re clock 0 +.latch n2784 Ng1448 re clock 0 +.latch n2789 Ng2370 re clock 0 +.latch n2794 Ng5164 re clock 0 +.latch n2798 Ng1333 re clock 0 +.latch n2803 Ng153 re clock 0 +.latch n2808 Ng6549 re clock 0 +.latch n2813 Ng4087 re clock 0 +.latch n2818 Ng4801 re clock 0 +.latch n2823 Ng2984 re clock 0 +.latch n2828_1 Ng3961 re clock 0 +.latch n2833 Ng962 re clock 0 +.latch n2838 Ng101 re clock 0 +.latch n2843 Ng6625 re clock 0 +.latch n2848 Ng51 re clock 0 +.latch n2853 Ng1018 re clock 0 +.latch n2858 Ng4045 re clock 0 +.latch n2863 Ng1467 re clock 0 +.latch n2868 Ng2461 re clock 0 +.latch n2873 Ng2756 re clock 0 +.latch n2878 Ng5990 re clock 0 +.latch n2883 Ng1256 re clock 0 +.latch n2888 Ng5029 re clock 0 +.latch n2893 Ng6519 re clock 0 +.latch n2898 Ng1816 re clock 0 +.latch n2903 Ng4369 re clock 0 +.latch n2908 Ng4578 re clock 0 +.latch n2913 Ng4459 re clock 0 +.latch n2918 Ng3831 re clock 0 +.latch n2923 Ng2514 re clock 0 +.latch n2928 Ng3288 re clock 0 +.latch n2933 Ng2403 re clock 0 +.latch n2938 Ng2145 re clock 0 +.latch n2943 Ng1700 re clock 0 +.latch n2948 Ng513 re clock 0 +.latch n2952 Ng2841 re clock 0 +.latch n2957 Ng5297 re clock 0 +.latch n2962 Ng2763 re clock 0 +.latch n2967 Ng4793 re clock 0 +.latch n2972 Ng952 re clock 0 +.latch n2977 Ng1263 re clock 0 +.latch n2982 Ng1950 re clock 0 +.latch n2987 Ng5138 re clock 0 +.latch n2992 Ng2307 re clock 0 +.latch n2996 Ng5109 re clock 0 +.latch n3001 Ng4664 re clock 0 +.latch n3006 Ng2223 re clock 0 +.latch n3011 Ng5808 re clock 0 +.latch n3016 Ng6645 re clock 0 +.latch n3021 Ng2016 re clock 0 +.latch n3026 Ng3873 re clock 0 +.latch n3031 Ng2315 re clock 0 +.latch n3036 Ng2811 re clock 0 +.latch n3041 Ng5957 re clock 0 +.latch n3046 Ng2047 re clock 0 +.latch n3051 Ng3869 re clock 0 +.latch n3056 Ng5575 re clock 0 +.latch n3061 Ng46 re clock 0 +.latch n3066 Ng3752 re clock 0 +.latch n3071 Ng3917 re clock 0 +.latch n3075_1 Ng1585 re clock 0 +.latch n3080 Ng4388 re clock 0 +.latch n3085 Ng6275 re clock 0 +.latch n3090 Ng6311 re clock 0 +.latch n3095 Ng1041 re clock 0 +.latch n3100 Ng2595 re clock 0 +.latch n3105 Ng2537 re clock 0 +.latch n3110 Pg21292 re clock 0 +.latch n3114 Ng4430 re clock 0 +.latch n3119 Ng4564 re clock 0 +.latch n3124 Ng4826 re clock 0 +.latch n3129 Ng6239 re clock 0 +.latch n3134 Ng232 re clock 0 +.latch n3139 Ng5268 re clock 0 +.latch n3144 Ng6545 re clock 0 +.latch n3149 Ng2417 re clock 0 +.latch n3154 Ng1772 re clock 0 +.latch n3159 Ng5052 re clock 0 +.latch n3164 Ng1890 re clock 0 +.latch n3169 Ng2629 re clock 0 +.latch n3174 Ng572 re clock 0 +.latch n3179 Ng2130 re clock 0 +.latch n3184 Ng4108 re clock 0 +.latch n3188 Ng4308 re clock 0 +.latch n3193 Ng475 re clock 0 +.latch n3197 Ng990 re clock 0 +.latch n3202 Ng45 re clock 0 +.latch n3207 Ng3990 re clock 0 +.latch n3212 Ng5881 re clock 0 +.latch n3217 Ng1992 re clock 0 +.latch n3222 Ng3171 re clock 0 +.latch n3227 Ng812 re clock 0 +.latch n3232 Ng832 re clock 0 +.latch n3237_1 Ng5897 re clock 0 +.latch n3242 Ng4571 re clock 0 +.latch n3246 Ng4455 re clock 0 +.latch n3251 Ng2902 re clock 0 +.latch n3256 Ng333 re clock 0 +.latch n3261 Ng168 re clock 0 +.latch n3266 Ng2823 re clock 0 +.latch n3271 Ng3684 re clock 0 +.latch n3276 Ng3639 re clock 0 +.latch n3281 Ng3338 re clock 0 +.latch n3286 Ng5406 re clock 0 +.latch n3291 Ng269 re clock 0 +.latch n3296 Ng401 re clock 0 +.latch n3301_1 Ng6040 re clock 0 +.latch n3306 Ng441 re clock 0 +.latch n3311_1 Ng3808 re clock 0 +.latch n3316 Ng10384 re clock 0 +.latch n3321_1 Ng3957 re clock 0 +.latch n3326 Ng4093 re clock 0 +.latch n3331 Ng1760 re clock 0 +.latch n3336_1 Ng160 re clock 0 +.latch n3341 Ng2279 re clock 0 +.latch n3346 Ng3498 re clock 0 +.latch n3351 Ng586 re clock 0 +.latch n3356 Ng2619 re clock 0 +.latch n3361 Ng1183 re clock 0 +.latch n3366 Ng1608 re clock 0 +.latch n3371 Ng1779 re clock 0 +.latch n3376 Ng2652 re clock 0 +.latch n3381 Ng2193 re clock 0 +.latch n3386 Ng2393 re clock 0 +.latch n3391 Ng661 re clock 0 +.latch n3396 Ng4950 re clock 0 +.latch n3401 Ng5535 re clock 0 +.latch n3406 Ng2834 re clock 0 +.latch n3411_1 Ng1361 re clock 0 +.latch n3416_1 Ng6235 re clock 0 +.latch n3421 Ng1146 re clock 0 +.latch n3426 Ng2625 re clock 0 +.latch n3431 Ng150 re clock 0 +.latch n3436 Ng1696 re clock 0 +.latch n3441 Ng6555 re clock 0 +.latch n3446 Ng3881 re clock 0 +.latch n3451 Ng6621 re clock 0 +.latch n3456 Ng3470 re clock 0 +.latch n3461 Ng3897 re clock 0 +.latch n3466 Ng518 re clock 0 +.latch n3471 Ng538 re clock 0 +.latch n3476 Ng2606 re clock 0 +.latch n3481 Ng1472 re clock 0 +.latch n3486 Ng542 re clock 0 +.latch n3491 Ng5188 re clock 0 +.latch n3496 Ng5689 re clock 0 +.latch n3501 Ng405 re clock 0 +.latch n3506 Ng5216 re clock 0 +.latch n3510 Ng6494 re clock 0 +.latch n3515_1 Ng4669 re clock 0 +.latch n3520 Ng996 re clock 0 +.latch n3525 Ng4531 re clock 0 +.latch n3530 Ng2860 re clock 0 +.latch n3535 Ng4743 re clock 0 +.latch n3540 Ng6593 re clock 0 +.latch n3544 Ng4411 re clock 0 +.latch n3549 Ng1413 re clock 0 +.latch n3553_1 Ng26960 re clock 0 +.latch n3557 Ng6641 re clock 0 +.latch n3562 Ng1936 re clock 0 +.latch n3567 Ng55 re clock 0 +.latch n3572 Ng504 re clock 0 +.latch n3577 Ng2587 re clock 0 +.latch n3582 Ng4480 re clock 0 +.latch n3587 Ng2311 re clock 0 +.latch n3592 Ng3602 re clock 0 +.latch n3597 Ng5571 re clock 0 +.latch n3602 Ng3578 re clock 0 +.latch n3607 Ng5827 re clock 0 +.latch n3612 Ng3582 re clock 0 +.latch n3617 Ng6271 re clock 0 +.latch n3622 Ng4688 re clock 0 +.latch n3627 Ng2380 re clock 0 +.latch n3632 Ng5196 re clock 0 +.latch n3637 Ng3227 re clock 0 +.latch n3642 Ng2020 re clock 0 +.latch n3647 Ng6541 re clock 0 +.latch n3652 Ng3203 re clock 0 +.latch n3657 Ng1668 re clock 0 +.latch n3662 Ng4760 re clock 0 +.latch n3667 Ng262 re clock 0 +.latch n3672 Ng1840 re clock 0 +.latch n3677 Ng5467 re clock 0 +.latch n3682 Ng460 re clock 0 +.latch n3687 Ng6209 re clock 0 +.latch n3692 Pg20763 re clock 0 +.latch n3696 Ng655 re clock 0 +.latch n3701 Ng3502 re clock 0 +.latch n3706 Ng2204 re clock 0 +.latch n3711 Ng5256 re clock 0 +.latch n3716 Ng4608 re clock 0 +.latch n3721 Ng794 re clock 0 +.latch n3725_1 Ng4423 re clock 0 +.latch n3730_1 Ng3689 re clock 0 +.latch n3734 Ng5685 re clock 0 +.latch n3739 Ng703 re clock 0 +.latch n3744 Ng862 re clock 0 +.latch n3749 Ng3247 re clock 0 +.latch n3754 Ng2040 re clock 0 +.latch n3759 Ng4146 re clock 0 +.latch n3764 Ng4633 re clock 0 +.latch n3769 Ng4732 re clock 0 +.latch n3774 Ng5817 re clock 0 +.latch n3779 Ng2351 re clock 0 +.latch n3784 Ng2648 re clock 0 +.latch n3789 Ng6736 re clock 0 +.latch n3794 Ng4944 re clock 0 +.latch n3799 Ng4072 re clock 0 +.latch n3803 Ng4443 re clock 0 +.latch n3808 Ng3466 re clock 0 +.latch n3813 Ng4116 re clock 0 +.latch n3818 Ng5041 re clock 0 +.latch n3823 Ng4434 re clock 0 +.latch n3828 Ng3827 re clock 0 +.latch n3833 Ng6500 re clock 0 +.latch n3838 Ng3133 re clock 0 +.latch n3843 Ng3333 re clock 0 +.latch n3847 Ng979 re clock 0 +.latch n3852 Ng4681 re clock 0 +.latch n3857 Ng298 re clock 0 +.latch n3862 Ng2667 re clock 0 +.latch n3867 Ng1894 re clock 0 +.latch n3872 Ng2988 re clock 0 +.latch n3877 Ng3538 re clock 0 +.latch n3882 Ng301 re clock 0 +.latch n3887 Ng341 re clock 0 +.latch n3892 Ng827 re clock 0 +.latch n3897 Ng2555 re clock 0 +.latch n3902 Ng5011 re clock 0 +.latch n3907 Ng199 re clock 0 +.latch n3912_1 Ng6523 re clock 0 +.latch n3917_1 Ng1526 re clock 0 +.latch n3922_1 Ng4601 re clock 0 +.latch n3927_1 Ng854 re clock 0 +.latch n3932_1 Ng1484 re clock 0 +.latch n3937 Ng4922 re clock 0 +.latch n3942 Ng5080 re clock 0 +.latch n3947_1 Ng5863 re clock 0 +.latch n3952 Ng4581 re clock 0 +.latch n3957 Ng2518 re clock 0 +.latch n3962_1 Ng2567 re clock 0 +.latch n3967 Ng568 re clock 0 +.latch n3972 Ng3263 re clock 0 +.latch n3977 Ng6613 re clock 0 +.latch n3982 Ng6044 re clock 0 +.latch n3987 Ng6444 re clock 0 +.latch n3992 Ng2965 re clock 0 +.latch n3997 Ng5857 re clock 0 +.latch n4002 Ng1616 re clock 0 +.latch n4007 Ng890 re clock 0 +.latch n4012 Ng3562 re clock 0 +.latch n4017 Ng1404 re clock 0 +.latch n4022 Ng3817 re clock 0 +.latch n4027 Ng93 re clock 0 +.latch n4032 Ng4501 re clock 0 +.latch n4037 Ng287 re clock 0 +.latch n4042 Ng2724 re clock 0 +.latch n4047 Ng4704 re clock 0 +.latch n4052 Ng22 re clock 0 +.latch n4057_1 Ng2878 re clock 0 +.latch n4062_1 Ng5220 re clock 0 +.latch n4067 Ng617 re clock 0 +.latch n4072 Ng316 re clock 0 +.latch n4077 Ng1277 re clock 0 +.latch n4082 Ng6513 re clock 0 +.latch n4087 Ng336 re clock 0 +.latch n4092 Ng2882 re clock 0 +.latch n4097 Ng933 re clock 0 +.latch n4102 Ng1906 re clock 0 +.latch n4107 Ng305 re clock 0 +.latch n4112 Ng8 re clock 0 +.latch n4117 Ng2799 re clock 0 +.latch n4122 Ng4912 re clock 0 +.latch n4127 Ng4157 re clock 0 +.latch n4132 Ng2541 re clock 0 +.latch n4137 Ng2153 re clock 0 +.latch n4142 Ng550 re clock 0 +.latch n4147_1 Ng255 re clock 0 +.latch n4152 Ng1945 re clock 0 +.latch n4157 Ng5240 re clock 0 +.latch n4162 Ng1478 re clock 0 +.latch n4167 Ng3863 re clock 0 +.latch n4172 Ng1959 re clock 0 +.latch n4177 Ng3480 re clock 0 +.latch n4182 Ng6653 re clock 0 +.latch n4187_1 Ng2864 re clock 0 +.latch n4192 Ng4894 re clock 0 +.latch n4197_1 Ng3857 re clock 0 +.latch n4202 Ng499 re clock 0 +.latch n4207 Ng1002 re clock 0 +.latch n4212 Ng776 re clock 0 +.latch n4216_1 Ng1236 re clock 0 +.latch n4221 Ng4646 re clock 0 +.latch n4226 Ng2476 re clock 0 +.latch n4231 Ng1657 re clock 0 +.latch n4236 Ng2375 re clock 0 +.latch n4241 Ng63 re clock 0 +.latch n4245 Ng358 re clock 0 +.latch n4250 Ng896 re clock 0 +.latch n4255 Ng283 re clock 0 +.latch n4260 Ng3161 re clock 0 +.latch n4265 Ng2384 re clock 0 +.latch n4270 Ng4616 re clock 0 +.latch n4275 Ng4561 re clock 0 +.latch n4280 Ng2024 re clock 0 +.latch n4284 Ng3451 re clock 0 +.latch n4289 Ng2795 re clock 0 +.latch n4294 Ng613 re clock 0 +.latch n4299 Ng4527 re clock 0 +.latch n4304 Ng1844 re clock 0 +.latch n4309 Ng5937 re clock 0 +.latch n4314 Ng4546 re clock 0 +.latch n4319 Ng2523 re clock 0 +.latch n4324 Ng2643 re clock 0 +.latch n4329 Ng1489 re clock 0 +.latch n4334 Ng2551 re clock 0 +.latch n4339 Ng5156 re clock 0 +.latch n4343 Pg23683 re clock 0 +.latch n4347 Ng1955 re clock 0 +.latch n4352 Ng6049 re clock 0 +.latch n4357 Ng2273 re clock 0 +.latch n4362 Ng4771 re clock 0 +.latch n4367 Ng6098 re clock 0 +.latch n4372 Ng3147 re clock 0 +.latch n4377 Ng3347 re clock 0 +.latch n4382 Ng2269 re clock 0 +.latch n4386 Ng191 re clock 0 +.latch n4391 Ng2712 re clock 0 +.latch n4396 Ng626 re clock 0 +.latch n4401 Ng2729 re clock 0 +.latch n4406 Ng5357 re clock 0 +.latch n4411 Ng4991 re clock 0 +.latch n4416 Ng4709 re clock 0 +.latch n4421 Ng2927 re clock 0 +.latch n4426 Ng4340 re clock 0 +.latch n4431 Ng5929 re clock 0 +.latch n4436 Ng4907 re clock 0 +.latch n4441 Ng4035 re clock 0 +.latch n4446 Ng2946 re clock 0 +.latch n4451 Ng918 re clock 0 +.latch n4456 Ng4082 re clock 0 +.latch n4461 Ng2036 re clock 0 +.latch n4466 Ng577 re clock 0 +.latch n4471 Ng1620 re clock 0 +.latch n4476 Ng2831 re clock 0 +.latch n4481 Ng667 re clock 0 +.latch n4486 Ng930 re clock 0 +.latch n4491 Ng3937 re clock 0 +.latch n4496 Ng817 re clock 0 +.latch n4501 Ng1249 re clock 0 +.latch n4506 Ng837 re clock 0 +.latch n4511 Ng599 re clock 0 +.latch n4516 Ng5475 re clock 0 +.latch n4521 Ng739 re clock 0 +.latch n4526 Ng5949 re clock 0 +.latch n4531 Ng6682 re clock 0 +.latch n4536 Ng904 re clock 0 +.latch n4541 Ng2873 re clock 0 +.latch n4546 Ng1854 re clock 0 +.latch n4551 Ng5084 re clock 0 +.latch n4556 Ng5603 re clock 0 +.latch n4561 Ng2495 re clock 0 +.latch n4566 Ng2437 re clock 0 +.latch n4571 Ng2102 re clock 0 +.latch n4576 Ng2208 re clock 0 +.latch n4581 Ng2579 re clock 0 +.latch n4586 Ng4064 re clock 0 +.latch n4591 Ng4899 re clock 0 +.latch n4596 Ng2719 re clock 0 +.latch n4601 Ng4785 re clock 0 +.latch n4606 Ng5583 re clock 0 +.latch n4611 Ng781 re clock 0 +.latch n4616 Ng6173 re clock 0 +.latch n4621 Ng2917 re clock 0 +.latch n4626 Ng686 re clock 0 +.latch n4631_1 Ng1252 re clock 0 +.latch n4636_1 Ng671 re clock 0 +.latch n4641 Ng2265 re clock 0 +.latch n4646 Ng6283 re clock 0 +.latch n4651 Ng5527 re clock 0 +.latch n4656 Ng4489 re clock 0 +.latch n4661 Ng1974 re clock 0 +.latch n4666 Ng1270 re clock 0 +.latch n4671 Ng4966 re clock 0 +.latch n4676 Ng6227 re clock 0 +.latch n4681 Ng3929 re clock 0 +.latch n4686 Ng5503 re clock 0 +.latch n4691 Ng4242 re clock 0 +.latch n4696 Ng5925 re clock 0 +.latch n4701 Ng1124 re clock 0 +.latch n4706 Ng4955 re clock 0 +.latch n4711 Ng5224 re clock 0 +.latch n4716 Ng2012 re clock 0 +.latch n4721 Ng6203 re clock 0 +.latch n4726 Ng5120 re clock 0 +.latch n4731 Ng2389 re clock 0 +.latch n4736 Ng4438 re clock 0 +.latch n4741 Ng2429 re clock 0 +.latch n4746_1 Ng2787 re clock 0 +.latch n4751 Ng1287 re clock 0 +.latch n4756_1 Ng2675 re clock 0 +.latch n4761 Pg18881 re clock 0 +.latch n4765 Ng4836 re clock 0 +.latch n4770 Ng1199 re clock 0 +.latch n4775 Ng5547 re clock 0 +.latch n4780 Ng2138 re clock 0 +.latch n4785 Ng2338 re clock 0 +.latch n4790 Ng6247 re clock 0 +.latch n4795 Ng2791 re clock 0 +.latch n4800 Ng3949 re clock 0 +.latch n4805 Ng1291 re clock 0 +.latch n4810 Ng5945 re clock 0 +.latch n4815 Ng5244 re clock 0 +.latch n4820 Ng2759 re clock 0 +.latch n4825 Ng6741 re clock 0 +.latch n4830 Ng785 re clock 0 +.latch n4835 Ng1259 re clock 0 +.latch n4840 Ng3484 re clock 0 +.latch n4845 Ng209 re clock 0 +.latch n4850 Ng6609 re clock 0 +.latch n4855 Ng5517 re clock 0 +.latch n4860 Ng2449 re clock 0 +.latch n4865 Ng2575 re clock 0 +.latch n4869 Ng65 re clock 0 +.latch n4874 Ng2715 re clock 0 +.latch n4879 Ng936 re clock 0 +.latch n4884 Ng2098 re clock 0 +.latch n4889 Ng4462 re clock 0 +.latch n4894 Ng604 re clock 0 +.latch n4899_1 Ng6589 re clock 0 +.latch n4904_1 Ng1886 re clock 0 +.latch n4909 Ng429 re clock 0 +.latch n4914 Ng1870 re clock 0 +.latch n4919 Ng4249 re clock 0 +.latch n4924 Ng1825 re clock 0 +.latch n4929 Ng1008 re clock 0 +.latch n4934 Ng4392 re clock 0 +.latch n4939_1 Ng3546 re clock 0 +.latch n4944_1 Ng5236 re clock 0 +.latch n4949 Ng1768 re clock 0 +.latch n4954 Ng4854 re clock 0 +.latch n4959 Ng3925 re clock 0 +.latch n4964 Ng6509 re clock 0 +.latch n4969 Ng732 re clock 0 +.latch n4974 Ng2504 re clock 0 +.latch n4978_1 Ng1322 re clock 0 +.latch n4983 Ng4520 re clock 0 +.latch n4988 Ng2185 re clock 0 +.latch n4993 Ng37 re clock 0 +.latch n4997_1 Ng4031 re clock 0 +.latch n5002_1 Ng2070 re clock 0 +.latch n5006 Pg8235 re clock 0 +.latch n5010 Ng4176 re clock 0 +.latch n5014 Ng4405 re clock 0 +.latch n5018 Ng872 re clock 0 +.latch n5023 Ng6181 re clock 0 +.latch n5028 Ng6381 re clock 0 +.latch n5033 Ng4765 re clock 0 +.latch n5038 Ng5563 re clock 0 +.latch n5043 Ng1395 re clock 0 +.latch n5048 Ng1913 re clock 0 +.latch n5053 Ng2331 re clock 0 +.latch n5058 Ng6263 re clock 0 +.latch n5063 Ng50 re clock 0 +.latch n5068 Ng3945 re clock 0 +.latch n5072 Ng347 re clock 0 +.latch n5077 Ng4473 re clock 0 +.latch n5082 Ng1266 re clock 0 +.latch n5087 Ng5489 re clock 0 +.latch n5092 Ng714 re clock 0 +.latch n5097 Ng2748 re clock 0 +.latch n5102 Ng5471 re clock 0 +.latch n5107 Ng4540 re clock 0 +.latch n5111_1 Ng6723 re clock 0 +.latch n5116_1 Ng6605 re clock 0 +.latch n5121_1 Ng2445 re clock 0 +.latch n5126_1 Ng2173 re clock 0 +.latch n5131_1 Ng2491 re clock 0 +.latch n5136 Ng4849 re clock 0 +.latch n5141_1 Ng2169 re clock 0 +.latch n5146_1 Ng2283 re clock 0 +.latch n5151 Ng6585 re clock 0 +.latch n5156_1 Pg20654 re clock 0 +.latch n5160 Ng2407 re clock 0 +.latch n5165 Ng2868 re clock 0 +.latch n5170 Ng2767 re clock 0 +.latch n5175 Ng1783 re clock 0 +.latch n5180 Ng1312 re clock 0 +.latch n5185 Ng5212 re clock 0 +.latch n5190 Ng4245 re clock 0 +.latch n5195 Ng645 re clock 0 +.latch n5199 Ng4291 re clock 0 +.latch n5204 Pg20899 re clock 0 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n6148_1 +0010-- 1 +01001- 1 +01010- 1 +01---0 1 +0-0--0 1 +.names n4665 Ng4681 Ng4646 Pg21245 Ng4831 Ng4674 n6149 +000--0 1 +11--1- 1 +1-11-- 1 +.names Ng4899 Ng4975 Ng4966 Ng4991 Ng4927 n6150 +000-- 0 +110-1 0 +---1- 0 +.names n4735 Ng4966 Ng4983 n6655 n4734 n6150 n6151 +1010-- 0 +11001- 0 +11010- 0 +11---0 0 +1-0--0 0 +.names n4736_1 n6151 n2066 +11 1 +.names Ng3990 Pg16659 Ng4054 Ng3961 Ng3953 n6153_1 +010-1 1 +10--- 1 +1-1-- 1 +1--0- 1 +.names Ng4054 Ng3937 Pg16775 Ng3921 Pg13966 n6154 +0--11 1 +111-- 1 +.names Pg11418 Ng4040 Ng3990 n4846 n6153_1 n6154 n6155 +000-0- 1 +001--0 1 +01-11- 1 +10-11- 1 +110-0- 1 +111--0 1 +--010- 1 +.names n6155 n4837 Ng3965 n4580 n6156 +100- 1 +10-0 1 +.names Ng6741 Pg17778 Ng6637 Pg14828 Ng6621 n6157 +0--11 1 +111-- 1 +.names Ng6682 Pg17688 Ng6741 Ng6645 Ng6653 n6158_1 +00--- 1 +0-1-- 1 +0--0- 1 +110-1 1 +.names Ng6727 Pg12470 Ng6682 n5000 n6158_1 n6157 n6159 +00-11- 1 +010--0 1 +011-0- 1 +100--0 1 +101-0- 1 +11-11- 1 +--110- 1 +.names n6159 n4989 Ng6657 n4999 n6160 +100- 1 +10-0 1 +.names Ng3352 Ng3288 n5010_1 n5009 Ng3239 Pg13865 n6161 +00--11 0 +10-0-- 0 +--0--- 0 +.names n5006_1 Ng3263 n5003 n5015 n5016 n6162 +0--0- 0 +0---0 0 +-11-- 0 +.names n6162 Ng3338 n6161 n5014_1 n5013 n5012 n6163_1 +101--- 1 +11-100 1 +.names Ng5703 Ng5689 Pg14635 Ng5587 Pg17678 Ng5603 n6164 +001--- 1 +0-11-- 1 +11--11 1 +.names Ng5689 n6164 Ng5644 n5333 n5334 Ng5595 n6165 +010--1 0 +111--- 0 +1--1-- 0 +1---1- 0 +.names n6165 n5327 Ng5689 n5336 n5335_1 n5332 n6166 +111--- 1 +11-000 1 +.names n5626 Ng48 n5627_1 Ng2860 n5641 Ng2864 n6167 +1111-- 0 +11--11 0 +.names n6167 n5646 n5639 n5642_1 Ng2922 Ng582 n6168_1 +1000-- 1 +100-0- 1 +10-0-0 1 +10--00 1 +.names Ng16 Ng50 Ng48 Ng4717 Ng1448 Ng1291 n6169 +011--- 1 +100-10 1 +1101-- 1 +.names n4052 Ng48 n5627_1 Ng5507 n5640 Ng3151 n6170 +101--- 1 +11--11 1 +1-11-- 1 +.names n5645 Ng48 n5627_1 Ng5853 n5640 Ng3502 n6171 +1111-- 0 +11--11 0 +.names n5655 n5657_1 n5656 n5654 n6172 +1000 1 +.names n6172 n4052 n5652_1 n5650 n5648 n6171 n3061 +10---- 0 +1-1111 0 +.names n5638 Ng2955 Ng51 n5641 Ng48 Ng2882 n6174 +110--- 1 +---111 1 +.names n5639 Ng586 Ng613 n5635 n5626 n6174 n6175 +11---- 0 +--11-- 0 +----11 0 +.names Ng48 Ng16 Ng50 Ng1291 Ng4927 Ng4172 n6176 +0101-- 1 +011-0- 1 +100--1 1 +.names n5645 Ng48 n5627_1 Ng6199 n5640 Ng3853 n6177 +1111-- 0 +11--11 0 +.names n5669 n5668 n5667_1 Ng956 n5666 n6178_1 +1000- 1 +100-0 1 +.names n6178_1 n4052 n5665 n5663 n5662_1 n6177 n3202 +10---- 0 +1-1111 0 +.names n5644 n5646 n5627_1 Ng4722 Ng4912 n5641 n6180 +1-11-- 0 +1---11 0 +-1---- 0 +.names n6203 n4052 n5673 n5671 n5670 n6180 n1789 +10---- 0 +1-1111 0 +.names n5638 Ng51 Ng2970 Pg21292 n5627_1 Ng48 n6182_1 +111--- 1 +---110 1 +.names Ng16 Ng48 Ng50 Ng2138 Ng4146 Ng1283 n6183 +010-1- 1 +0111-- 1 +100--1 1 +.names Ng518 Ng504 Ng528 Pg25259 n4866 n4783 n6184 +001--- 1 +00-1-- 1 +010-1- 1 +100--1 1 +.names Ng50 n5627_1 Ng2145 n5647_1 Ng52 Ng2704 n6185 +01---- 1 +1--111 1 +-11--- 1 +.names n6185 Ng16 Ng48 Ng50 Ng4157 Ng1287 n6186_1 +1011-- 0 +101-1- 0 +1100-1 0 +.names n5688 n5687_1 n4052 n5685 n5682_1 n6186_1 n2001 +100--- 0 +10-111 0 +.names n5634 n5646 n5626 Ng749 Pg20652 n5631 n6188 +1-11-- 0 +1---11 0 +-1---- 0 +.names Ng48 Ng16 Ng50 Ng2130 Ng1296 Ng4176 n6189 +010-0- 1 +100--1 1 +1011-- 1 +.names Ng2741 Ng2748 Ng2051 Ng2060 Ng1917 Ng1926 n6190 +01--10 1 +10---- 1 +1-10-- 1 +.names Ng2741 Ng2342 Ng2351 Ng2208 Ng2217 n6191_1 +0--10 1 +110-- 1 +.names Ng2756 Ng2748 n6190 n5247 n6191_1 Pg25167 n6192 +000--1 1 +011--- 1 +0-11-- 1 +10--1- 1 +.names n5696 n6192 n4373 n2694 +0-- 1 +-11 1 +.names Pg35 n6149 Ng4688 n4665 n6148_1 n6660 +10-0- 1 +111-- 1 +11--0 1 +.names n5644 n5641 Ng4907 n5645 n5629 n4193 n6195 +111--- 0 +---111 0 +.names n4052 n6170 n6169 n6195 Ng8 Pg53 n6196 +011--- 1 +0---10 1 +10-1-- 1 +1-01-- 1 +.names n6196 n4052 n6168_1 n5632_1 n5624 n4112 +00--- 0 +11111 0 +.names n6176 n5627_1 Ng50 Ng4737 n5644 n5641 n6198 +110--- 0 +1-1--1 0 +-1-01- 0 +.names n4052 n5661 Ng16 Pg53 n6198 n5646 n6199 +00---- 1 +0-10-- 1 +11--10 1 +.names n6199 n4052 n6175 n5659 n5658 n2608 +00--- 0 +11111 0 +.names Ng50 Ng1291 Ng1478 n5629 Ng1135 Ng947 n6201 +01---- 0 +0-0--- 0 +1--110 0 +.names Ng48 n5627_1 Ng50 Ng5160 n5640 Ng6545 n6202 +11-1-- 0 +1-0--- 0 +1---11 0 +-00--- 0 +.names n4052 Ng16 Ng50 n6202 n6201 n5676 n6203 +1010-- 0 +101-0- 0 +11011- 0 +-----1 0 +.names n5679 n6182_1 n5626 n5629 Pg35 Ng785 n6204 +10-0-- 1 +10--10 1 +1-0--- 1 +.names n5653 n5674 Ng604 n5629 Pg127 n5631 n6205_1 +1----- 0 +-11--- 0 +---111 0 +.names n6208 n4052 n5678 n5677_1 n6204 n6205_1 n2848 +10---- 0 +1-1111 0 +.names n5645 Ng48 n5640 Ng2697 n5641 Ng4249 n6207 +1111-- 0 +11--11 0 +.names n5680 n6207 n4052 n5627_1 n6183 n6208 +11-0- 1 +11--0 1 +1-0-- 1 +.names Ng518 Ng504 Ng2361 Ng2331 Ng2629 Ng2599 n6209 +0110-- 1 +10--10 1 +.names n4200 n6184 Ng528 n6209 Ng2227 Ng2197 n6210_1 +110--- 0 +11--10 0 +1-11-- 0 +.names n4383 n4812 Ng2495 n4568 Ng2465 n6211 +11--- 0 +--110 0 +.names n6211 n6210_1 n5717 +11 0 +.names n5645 Ng952 n5629 n5640 Ng2689 Ng48 n6213 +101--- 0 +1--111 0 +.names Ng48 n5641 n5645 Ng4253 n5626 Ng2878 n6214 +1111-- 0 +11--11 0 +.names n6213 n6214 n5639 n6189 n5627_1 Ng572 n6215_1 +1100-- 1 +110-0- 1 +11-0-0 1 +11--00 1 +.names n5691 n4052 n6188 n5690 n5689 n6215_1 n5063 +00---- 0 +0-1111 0 +.names Pg6753 Pg18092 +1 1 +.names Pg6748 Pg18094 +1 1 +.names Pg6749 Pg18095 +1 1 +.names Pg6750 Pg18096 +1 1 +.names Pg6747 Pg18097 +1 1 +.names Pg6744 Pg18098 +1 1 +.names Pg6745 Pg18099 +1 1 +.names Pg6751 Pg18100 +1 1 +.names Pg6746 Pg18101 +1 1 +.names Pg36 Pg21698 +1 1 +.names n4120 Pg23190 +1 1 +.names n4120 Pg24151 +1 1 +.names Pg53 Pg24161 +1 1 +.names Pg54 Pg24162 +1 1 +.names Pg56 Pg24163 +1 1 +.names Pg57 Pg24164 +1 1 +.names Pg64 Pg24165 +1 1 +.names Pg72 Pg24166 +1 1 +.names Pg73 Pg24167 +1 1 +.names Pg84 Pg24168 +1 1 +.names Pg90 Pg24169 +1 1 +.names Pg91 Pg24170 +1 1 +.names Pg92 Pg24171 +1 1 +.names Pg99 Pg24172 +1 1 +.names Pg100 Pg24173 +1 1 +.names Pg113 Pg24174 +1 1 +.names Pg114 Pg24175 +1 1 +.names Pg115 Pg24176 +1 1 +.names Pg116 Pg24177 +1 1 +.names Pg120 Pg24178 +1 1 +.names Pg124 Pg24179 +1 1 +.names Pg125 Pg24180 +1 1 +.names Pg126 Pg24181 +1 1 +.names Pg127 Pg24182 +1 1 +.names Pg134 Pg24183 +1 1 +.names Pg135 Pg24184 +1 1 +.names Pg44 Pg24185 +1 1 +.names n4120 Pg25582 +1 1 +.names n4120 Pg25583 +1 1 +.names n4120 Pg25584 +1 1 +.names n4120 Pg25585 +1 1 +.names n4120 Pg25586 +1 1 +.names n4120 Pg25587 +1 1 +.names n4120 Pg25588 +1 1 +.names n4120 Pg25589 +1 1 +.names n4120 Pg25590 +1 1 +.names Pg20049 Pg29210 +1 1 +.names Pg20763 Pg29211 +1 1 +.names Pg20899 Pg29212 +1 1 +.names Pg20557 Pg29213 +1 1 +.names Pg20652 Pg29214 +1 1 +.names Pg20901 Pg29215 +1 1 +.names Pg21176 Pg29216 +1 1 +.names Pg21270 Pg29217 +1 1 +.names Pg18881 Pg29218 +1 1 +.names Pg20654 Pg29219 +1 1 +.names Pg21245 Pg29220 +1 1 +.names Pg21292 Pg29221 +1 1 +.names Pg23002 Pg30327 +1 1 +.names Pg23612 Pg30329 +1 1 +.names Pg23652 Pg30330 +1 1 +.names Pg23759 Pg30331 +1 1 +.names Pg23683 Pg30332 +1 1 +.names Pg25114 Pg31860 +1 1 +.names Pg25219 Pg31861 +1 1 +.names Pg25259 Pg31862 +1 1 +.names Pg25167 Pg31863 +1 1 +.names n4120 Pg32429 +1 1 +.names n4120 Pg32454 +1 1 +.names Pg26801 Pg32975 +1 1 +.names Pg27831 Pg33533 +1 1 +.names n4120 Pg33945 +1 1 +.names n4120 Pg33946 +1 1 +.names n4120 Pg33947 +1 1 +.names n4120 Pg33948 +1 1 +.names n4120 Pg33949 +1 1 +.names n4120 Pg33950 +1 1 +.names Pg28753 Pg33959 +1 1 +.names n4120 Pg34232 +1 1 +.names n4120 Pg34233 +1 1 +.names n4120 Pg34234 +1 1 +.names n4120 Pg34235 +1 1 +.names n4120 Pg34236 +1 1 +.names n4120 Pg34237 +1 1 +.names n4120 Pg34238 +1 1 +.names n4120 Pg34239 +1 1 +.names n4120 Pg34240 +1 1 +.names Pg31521 Pg34435 +1 1 +.names Pg31656 Pg34436 +1 1 +.names Pg31665 Pg34437 +1 1 +.names n4120 Pg34597 +1 1 +.names Pg33894 Pg34788 +1 1 +.names Pg34839 Pg34956 +1 1 +.names Pg8132 Pg8178 +1 1 +.names Pg8235 Pg8283 +1 1 +.names Pg8353 Pg8403 +1 1 +.names Pg13099 n694 +1 1 +.names Pg13085 n697 +1 1 +.names Pg13068 n700 +1 1 +.names Pg13049 n703 +1 1 +.names Pg13039 n706 +1 1 +.names Pg14828 n709 +1 1 +.names Pg14749 n712_1 +1 1 +.names Pg14779 n715 +1 1 +.names Pg14705 n718 +1 1 +.names Pg14738 n721 +1 1 +.names Pg17688 n724 +1 1 +.names Pg14673 n727 +1 1 +.names Pg14694 n730 +1 1 +.names Pg17778 n733 +1 1 +.names Pg17649 n736 +1 1 +.names Pg14635 n739 +1 1 +.names Pg14662 n742 +1 1 +.names Pg17760 n745 +1 1 +.names Pg17607 n748 +1 1 +.names Pg14597 n751 +1 1 +.names Pg17739 n754 +1 1 +.names Pg17580 n757 +1 1 +.names Pg17711 n760 +1 1 +.names Pg17519 n763 +1 1 +.names Pg17674 n766 +1 1 +.names Pg17404 n769 +1 1 +.names Pg17320 n772 +1 1 +.names Pg17316 n775 +1 1 +.names Pg17291 n782 +1 1 +.names Pg14518 n789 +1 1 +.names Pg14451 n792 +1 1 +.names Pg14421 n795 +1 1 +.names Pg13966 n798 +1 1 +.names Pg13906 n801 +1 1 +.names Pg13926 n804 +1 1 +.names Pg13881 n807 +1 1 +.names Pg13895 n810 +1 1 +.names Pg16659 n813 +1 1 +.names Pg13865 n816 +1 1 +.names Pg16775 n819 +1 1 +.names Pg16627 n822 +1 1 +.names Pg16744 n825 +1 1 +.names Pg16603 n828 +1 1 +.names Pg16718 n831 +1 1 +.names Pg12470 n834 +1 1 +.names Pg12422 n837 +1 1 +.names Pg17871 n840 +1 1 +.names Pg12350 n843 +1 1 +.names Pg17845 n846 +1 1 +.names Pg12300 n849 +1 1 +.names Pg17819 n852 +1 1 +.names Pg12238 n855 +1 1 +.names Pg17813 n858 +1 1 +.names Pg17787 n861 +1 1 +.names Pg16693 n864 +1 1 +.names Pg16656 n867 +1 1 +.names Pg16624 n870 +1 1 +.names Pg14201 n873 +1 1 +.names Pg14189 n876 +1 1 +.names Pg14147 n883 +1 1 +.names Pg14125 n886 +1 1 +.names Pg14096 n889 +1 1 +.names Pg14217 n892 +1 1 +.names Pg11418 n895 +1 1 +.names Pg11388 n898 +1 1 +.names Pg16955 n901 +1 1 +.names Pg11349 n904 +1 1 +.names Pg16924 n907 +1 1 +.names Pg16874 n910 +1 1 +.names Pg19357 n913 +1 1 +.names Pg19334 n916 +1 1 +.names Pg17722 n919 +1 1 +.names Pg17685 n922 +1 1 +.names Pg17646 n925 +1 1 +.names Pg17604 n928 +1 1 +.names Pg17577 n931 +1 1 +.names Pg12184 n978 +1 1 +.names Pg12368 n1057 +1 1 +.names Pg8919 n1064 +1 1 +.names Pg8918 n1067 +1 1 +.names Pg8870 n1070 +1 1 +.names Pg8916 n1073 +1 1 +.names Pg8915 n1076 +1 1 +.names Pg11770 n1079 +1 1 +.names Pg8917 n1082_1 +1 1 +.names Pg8788 n1089 +1 1 +.names Pg8787 n1092 +1 1 +.names Pg8786 n1095 +1 1 +.names Pg8785 n1098 +1 1 +.names Pg8784 n1101 +1 1 +.names Pg8783 n1104 +1 1 +.names Pg11447 n1107 +1 1 +.names Pg7946 n1114 +1 1 +.names Pg7916 n1117_1 +1 1 +.names Pg9048 n1210 +1 1 +.names Pg17715 n1274 +1 1 +.names Pg8920 n1313 +1 1 +.names Ng4571 n1338 +1 1 +.names Pg17743 n1397 +1 1 +.names Pg8215 n1853 +1 1 +.names Pg10527 n1872 +1 1 +.names Ng26960 n1921 +1 1 +.names Pg9617 n2125 +1 1 +.names Pg11678 n2224 +1 1 +.names Pg17639 n2318 +1 1 +.names Pg16722 n2357 +1 1 +.names Pg17400 n2381 +1 1 +.names Pg8344 n2400 +1 1 +.names Pg8839 n2484 +1 1 +.names Pg10122 n2508 +1 1 +.names Pg17423 n2666 +1 1 +.names Pg7245 n2670 +1 1 +.names Pg9682 n2684 +1 1 +.names Pg8475 n2798 +1 1 +.names Ng26936 n2952 +1 1 +.names Pg9497 n2996 +1 1 +.names Pg12923 n3075_1 +1 1 +.names Pg9251 n3188 +1 1 +.names Pg8416 n3197 +1 1 +.names Ng6974 n3242 +1 1 +.names Ng26959 n3246 +1 1 +.names Pg9743 n3510 +1 1 +.names Pg7257 n3544 +1 1 +.names Ng10384 n3553_1 +1 1 +.names Pg10306 n3725_1 +1 1 +.names Pg17678 n3734 +1 1 +.names Pg7260 n3803 +1 1 +.names Pg13259 n3847 +1 1 +.names Pg10500 n4216_1 +1 1 +.names Pg8719 n4245 +1 1 +.names Pg8279 n4284 +1 1 +.names Pg12919 n4343 +1 1 +.names Pg8358 n4386 +1 1 +.names Pg18881 n4869 +1 1 +.names Pg13272 n4978_1 +1 1 +.names Ng6972 n4983 +1 1 +.names Pg16748 n4997_1 +1 1 +.names Pg8132 n5006 +1 1 +.names Pg7243 n5014 +1 1 +.names Pg14167 n5018 +1 1 +.names Pg7540 n5072 +1 1 +.names Pg17764 n5111_1 +1 1 +.names Pg9019 n5199 +1 1 +.names Pg8291 n5271 +1 1 +.names Pg33435 n5439 +1 1 +.names Pg8235 n5468 +1 1 +.names Ng26885 n5597 +1 1 +.names Pg8353 n5756 +1 1 +.names Ng4520 n5835 +1 1 +.names Pg33079 n5884_1 +1 1 +.names Pg9553 n5908 +1 1 +.names Pg16686 n6186 +1 1 +.names Pg8789 n6521 +1 1 +.names Pg9555 n6550 +1 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v b/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v new file mode 100644 index 000000000..12c6e159a --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v @@ -0,0 +1,9933 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module s38584(clock, Pg6753,/* Pg6752,*/ Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746, Pg6745, Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116, Pg115, Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72, Pg64, Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, Pg34972, Pg34956, Pg34927, Pg34925, Pg34923, Pg34921, Pg34919, Pg34917, Pg34915, Pg34913, Pg34839, Pg34788, Pg34597, Pg34437, Pg34436, Pg34435, Pg34425, Pg34383, Pg34240, Pg34239, Pg34238, Pg34237, Pg34236, Pg34235, Pg34234, Pg34233, Pg34232, Pg34221, Pg34201, Pg33959, Pg33950, Pg33949, Pg33948, Pg33947, Pg33946, Pg33945, Pg33935, Pg33894, Pg33874, Pg33659, Pg33636, Pg33533, Pg33435, Pg33079, Pg32975, Pg32454, Pg32429, Pg32185, Pg31863, Pg31862, Pg31861, Pg31860, Pg31793, Pg31665, Pg31656, Pg31521, Pg30332, Pg30331, Pg30330, Pg30329, Pg30327, Pg29221, Pg29220, Pg29219, Pg29218, Pg29217, Pg29216, Pg29215, Pg29214, Pg29213, Pg29212, Pg29211, Pg29210, Pg28753, Pg28042, Pg28041, Pg28030, Pg27831, Pg26877, Pg26876, Pg26875, Pg26801, Pg25590, Pg25589, Pg25588, Pg25587, Pg25586, Pg25585, Pg25584, Pg25583, Pg25582, Pg25259, Pg25219, Pg25167, Pg25114, Pg24185, Pg24184, Pg24183, Pg24182, Pg24181, Pg24180, Pg24179, Pg24178, Pg24177, Pg24176, Pg24175, Pg24174, Pg24173, Pg24172, Pg24171, Pg24170, Pg24169, Pg24168, Pg24167, Pg24166, Pg24165, Pg24164, Pg24163, Pg24162, Pg24161, Pg24151, Pg23759, Pg23683, Pg23652, Pg23612, Pg23190, Pg23002, Pg21727, Pg21698, Pg21292, Pg21270, Pg21245, Pg21176, Pg20901, Pg20899, Pg20763, Pg20654, Pg20652, Pg20557, Pg20049, Pg19357, Pg19334, Pg18881, Pg18101, Pg18100, Pg18099, Pg18098, Pg18097, Pg18096, Pg18095, Pg18094, Pg18092, Pg17871, Pg17845, Pg17819, Pg17813, Pg17787, Pg17778, Pg17764, Pg17760, Pg17743, Pg17739, Pg17722, Pg17715, Pg17711, Pg17688, Pg17685, Pg17678, Pg17674, Pg17649, Pg17646, Pg17639, Pg17607, Pg17604, Pg17580, Pg17577, Pg17519, Pg17423, Pg17404, Pg17400, Pg17320, Pg17316, Pg17291, Pg16955, Pg16924, Pg16874, Pg16775, Pg16748, Pg16744, Pg16722, Pg16718, Pg16693, Pg16686, Pg16659, Pg16656, Pg16627, Pg16624, Pg16603, Pg14828, Pg14779, Pg14749, Pg14738, Pg14705, Pg14694, Pg14673, Pg14662, Pg14635, Pg14597, Pg14518, Pg14451, Pg14421, Pg14217, Pg14201, Pg14189, Pg14167, Pg14147, Pg14125, Pg14096, Pg13966, Pg13926, Pg13906, Pg13895, Pg13881, Pg13865, Pg13272, Pg13259, Pg13099, Pg13085, Pg13068, Pg13049, Pg13039, Pg12923, Pg12919, Pg12833, Pg12832, Pg12470, Pg12422, Pg12368, Pg12350, Pg12300, Pg12238, Pg12184, Pg11770, Pg11678, Pg11447, Pg11418, Pg11388, Pg11349, Pg10527, Pg10500, Pg10306, Pg10122, Pg9817, Pg9743, Pg9741, Pg9682, Pg9680, Pg9617, Pg9615, Pg9555, Pg9553, Pg9497, Pg9251, Pg9048, Pg9019, Pg8920, Pg8919, Pg8918, Pg8917, Pg8916, Pg8915, Pg8870, Pg8839, Pg8789, Pg8788, Pg8787, Pg8786, Pg8785, Pg8784, Pg8783, Pg8719, Pg8475, Pg8416, Pg8403, Pg8398, Pg8358, Pg8353, Pg8344, Pg8342, Pg8291, Pg8283, Pg8279, Pg8277, Pg8235, Pg8215, Pg8178, Pg8132, Pg7946, Pg7916, Pg7540, Pg7260, Pg7257, Pg7245, Pg7243); + (* init = 1'h0 *) + reg Ng1002 = 1'h0; + (* init = 1'h0 *) + reg Ng1008 = 1'h0; + (* init = 1'h0 *) + reg Ng101 = 1'h0; + (* init = 1'h0 *) + reg Ng1018 = 1'h0; + (* init = 1'h0 *) + reg Ng1024 = 1'h0; + (* init = 1'h0 *) + reg Ng1030 = 1'h0; + (* init = 1'h0 *) + reg Ng1036 = 1'h0; + (* init = 1'h0 *) + reg Ng10384 = 1'h0; + (* init = 1'h0 *) + reg Ng1041 = 1'h0; + (* init = 1'h0 *) + reg Ng1046 = 1'h0; + (* init = 1'h0 *) + reg Ng1052 = 1'h0; + (* init = 1'h0 *) + reg Ng1061 = 1'h0; + (* init = 1'h0 *) + reg Ng1070 = 1'h0; + (* init = 1'h0 *) + reg Ng1087 = 1'h0; + (* init = 1'h0 *) + reg Ng1094 = 1'h0; + (* init = 1'h0 *) + reg Ng1099 = 1'h0; + (* init = 1'h0 *) + reg Ng110 = 1'h0; + (* init = 1'h0 *) + reg Ng1105 = 1'h0; + (* init = 1'h0 *) + reg Ng111 = 1'h0; + (* init = 1'h0 *) + reg Ng1111 = 1'h0; + (* init = 1'h0 *) + reg Ng112 = 1'h0; + (* init = 1'h0 *) + reg Ng1124 = 1'h0; + (* init = 1'h0 *) + reg Ng1129 = 1'h0; + (* init = 1'h0 *) + reg Ng1135 = 1'h0; + (* init = 1'h0 *) + reg Ng1141 = 1'h0; + (* init = 1'h0 *) + reg Ng1146 = 1'h0; + (* init = 1'h0 *) + reg Ng1152 = 1'h0; + (* init = 1'h0 *) + reg Ng1171 = 1'h0; + (* init = 1'h0 *) + reg Ng1178 = 1'h0; + (* init = 1'h0 *) + reg Ng1183 = 1'h0; + (* init = 1'h0 *) + reg Ng1189 = 1'h0; + (* init = 1'h0 *) + reg Ng1193 = 1'h0; + (* init = 1'h0 *) + reg Ng1199 = 1'h0; + (* init = 1'h0 *) + reg Ng1205 = 1'h0; + (* init = 1'h0 *) + reg Ng1211 = 1'h0; + (* init = 1'h0 *) + reg Ng1216 = 1'h0; + (* init = 1'h0 *) + reg Ng1221 = 1'h0; + (* init = 1'h0 *) + reg Ng1236 = 1'h0; + (* init = 1'h0 *) + reg Ng1246 = 1'h0; + (* init = 1'h0 *) + reg Ng1249 = 1'h0; + (* init = 1'h0 *) + reg Ng1252 = 1'h0; + (* init = 1'h0 *) + reg Ng1256 = 1'h0; + (* init = 1'h0 *) + reg Ng1259 = 1'h0; + (* init = 1'h0 *) + reg Ng1263 = 1'h0; + (* init = 1'h0 *) + reg Ng1266 = 1'h0; + (* init = 1'h0 *) + reg Ng1270 = 1'h0; + (* init = 1'h0 *) + reg Ng1274 = 1'h0; + (* init = 1'h0 *) + reg Ng1277 = 1'h0; + (* init = 1'h0 *) + reg Ng1280 = 1'h0; + (* init = 1'h0 *) + reg Ng1283 = 1'h0; + (* init = 1'h0 *) + reg Ng1287 = 1'h0; + (* init = 1'h0 *) + reg Ng1291 = 1'h0; + (* init = 1'h0 *) + reg Ng1296 = 1'h0; + (* init = 1'h0 *) + reg Ng1300 = 1'h0; + (* init = 1'h0 *) + reg Ng1306 = 1'h0; + (* init = 1'h0 *) + reg Ng1312 = 1'h0; + (* init = 1'h0 *) + reg Ng1319 = 1'h0; + (* init = 1'h0 *) + reg Ng1322 = 1'h0; + (* init = 1'h0 *) + reg Ng1333 = 1'h0; + (* init = 1'h0 *) + reg Ng1339 = 1'h0; + (* init = 1'h0 *) + reg Ng1345 = 1'h0; + (* init = 1'h0 *) + reg Ng1351 = 1'h0; + (* init = 1'h0 *) + reg Ng1361 = 1'h0; + (* init = 1'h0 *) + reg Ng1367 = 1'h0; + (* init = 1'h0 *) + reg Ng1373 = 1'h0; + (* init = 1'h0 *) + reg Ng1379 = 1'h0; + (* init = 1'h0 *) + reg Ng1384 = 1'h0; + (* init = 1'h0 *) + reg Ng1389 = 1'h0; + (* init = 1'h0 *) + reg Ng1395 = 1'h0; + (* init = 1'h0 *) + reg Ng1404 = 1'h0; + (* init = 1'h0 *) + reg Ng1413 = 1'h0; + (* init = 1'h0 *) + reg Ng142 = 1'h0; + (* init = 1'h0 *) + reg Ng1430 = 1'h0; + (* init = 1'h0 *) + reg Ng1437 = 1'h0; + (* init = 1'h0 *) + reg Ng1442 = 1'h0; + (* init = 1'h0 *) + reg Ng1448 = 1'h0; + (* init = 1'h0 *) + reg Ng1454 = 1'h0; + (* init = 1'h0 *) + reg Ng146 = 1'h0; + (* init = 1'h0 *) + reg Ng1467 = 1'h0; + (* init = 1'h0 *) + reg Ng1472 = 1'h0; + (* init = 1'h0 *) + reg Ng1478 = 1'h0; + (* init = 1'h0 *) + reg Ng1484 = 1'h0; + (* init = 1'h0 *) + reg Ng1489 = 1'h0; + (* init = 1'h0 *) + reg Ng1495 = 1'h0; + (* init = 1'h0 *) + reg Ng150 = 1'h0; + (* init = 1'h0 *) + reg Ng1514 = 1'h0; + (* init = 1'h0 *) + reg Ng1521 = 1'h0; + (* init = 1'h0 *) + reg Ng1526 = 1'h0; + (* init = 1'h0 *) + reg Ng153 = 1'h0; + (* init = 1'h0 *) + reg Ng1532 = 1'h0; + (* init = 1'h0 *) + reg Ng1536 = 1'h0; + (* init = 1'h0 *) + reg Ng1542 = 1'h0; + (* init = 1'h0 *) + reg Ng1548 = 1'h0; + (* init = 1'h0 *) + reg Ng1554 = 1'h0; + (* init = 1'h0 *) + reg Ng1559 = 1'h0; + (* init = 1'h0 *) + reg Ng1564 = 1'h0; + (* init = 1'h0 *) + reg Ng157 = 1'h0; + (* init = 1'h0 *) + reg Ng1579 = 1'h0; + (* init = 1'h0 *) + reg Ng1585 = 1'h0; + (* init = 1'h0 *) + reg Ng1589 = 1'h0; + (* init = 1'h0 *) + reg Ng1592 = 1'h0; + (* init = 1'h0 *) + reg Ng16 = 1'h0; + (* init = 1'h0 *) + reg Ng160 = 1'h0; + (* init = 1'h0 *) + reg Ng1600 = 1'h0; + (* init = 1'h0 *) + reg Ng1604 = 1'h0; + (* init = 1'h0 *) + reg Ng1608 = 1'h0; + (* init = 1'h0 *) + reg Ng1612 = 1'h0; + (* init = 1'h0 *) + reg Ng1616 = 1'h0; + (* init = 1'h0 *) + reg Ng1620 = 1'h0; + (* init = 1'h0 *) + reg Ng1624 = 1'h0; + (* init = 1'h0 *) + reg Ng1632 = 1'h0; + (* init = 1'h0 *) + reg Ng1636 = 1'h0; + (* init = 1'h0 *) + reg Ng164 = 1'h0; + (* init = 1'h0 *) + reg Ng1644 = 1'h0; + (* init = 1'h0 *) + reg Ng1648 = 1'h0; + (* init = 1'h0 *) + reg Ng1657 = 1'h0; + (* init = 1'h0 *) + reg Ng1664 = 1'h0; + (* init = 1'h0 *) + reg Ng1668 = 1'h0; + (* init = 1'h0 *) + reg Ng1677 = 1'h0; + (* init = 1'h0 *) + reg Ng168 = 1'h0; + (* init = 1'h0 *) + reg Ng1682 = 1'h0; + (* init = 1'h0 *) + reg Ng1687 = 1'h0; + (* init = 1'h0 *) + reg Ng1691 = 1'h0; + (* init = 1'h0 *) + reg Ng1696 = 1'h0; + (* init = 1'h0 *) + reg Ng1700 = 1'h0; + (* init = 1'h0 *) + reg Ng1706 = 1'h0; + (* init = 1'h0 *) + reg Ng1710 = 1'h0; + (* init = 1'h0 *) + reg Ng1714 = 1'h0; + (* init = 1'h0 *) + reg Ng1720 = 1'h0; + (* init = 1'h0 *) + reg Ng1724 = 1'h0; + (* init = 1'h0 *) + reg Ng1728 = 1'h0; + (* init = 1'h0 *) + reg Ng1736 = 1'h0; + (* init = 1'h0 *) + reg Ng174 = 1'h0; + (* init = 1'h0 *) + reg Ng1740 = 1'h0; + (* init = 1'h0 *) + reg Ng1744 = 1'h0; + (* init = 1'h0 *) + reg Ng1748 = 1'h0; + (* init = 1'h0 *) + reg Ng1752 = 1'h0; + (* init = 1'h0 *) + reg Ng1756 = 1'h0; + (* init = 1'h0 *) + reg Ng1760 = 1'h0; + (* init = 1'h0 *) + reg Ng1768 = 1'h0; + (* init = 1'h0 *) + reg Ng1772 = 1'h0; + (* init = 1'h0 *) + reg Ng1779 = 1'h0; + (* init = 1'h0 *) + reg Ng1783 = 1'h0; + (* init = 1'h0 *) + reg Ng1792 = 1'h0; + (* init = 1'h0 *) + reg Ng1798 = 1'h0; + (* init = 1'h0 *) + reg Ng1802 = 1'h0; + (* init = 1'h0 *) + reg Ng1811 = 1'h0; + (* init = 1'h0 *) + reg Ng1816 = 1'h0; + (* init = 1'h0 *) + reg Ng182 = 1'h0; + (* init = 1'h0 *) + reg Ng1821 = 1'h0; + (* init = 1'h0 *) + reg Ng1825 = 1'h0; + (* init = 1'h0 *) + reg Ng1830 = 1'h0; + (* init = 1'h0 *) + reg Ng1834 = 1'h0; + (* init = 1'h0 *) + reg Ng1840 = 1'h0; + (* init = 1'h0 *) + reg Ng1844 = 1'h0; + (* init = 1'h0 *) + reg Ng1848 = 1'h0; + (* init = 1'h0 *) + reg Ng1854 = 1'h0; + (* init = 1'h0 *) + reg Ng1858 = 1'h0; + (* init = 1'h0 *) + reg Ng1862 = 1'h0; + (* init = 1'h0 *) + reg Ng1870 = 1'h0; + (* init = 1'h0 *) + reg Ng1874 = 1'h0; + (* init = 1'h0 *) + reg Ng1878 = 1'h0; + (* init = 1'h0 *) + reg Ng1882 = 1'h0; + (* init = 1'h0 *) + reg Ng1886 = 1'h0; + (* init = 1'h0 *) + reg Ng1890 = 1'h0; + (* init = 1'h0 *) + reg Ng1894 = 1'h0; + (* init = 1'h0 *) + reg Ng1902 = 1'h0; + (* init = 1'h0 *) + reg Ng1906 = 1'h0; + (* init = 1'h0 *) + reg Ng191 = 1'h0; + (* init = 1'h0 *) + reg Ng1913 = 1'h0; + (* init = 1'h0 *) + reg Ng1917 = 1'h0; + (* init = 1'h0 *) + reg Ng1926 = 1'h0; + (* init = 1'h0 *) + reg Ng1932 = 1'h0; + (* init = 1'h0 *) + reg Ng1936 = 1'h0; + (* init = 1'h0 *) + reg Ng1945 = 1'h0; + (* init = 1'h0 *) + reg Ng1950 = 1'h0; + (* init = 1'h0 *) + reg Ng1955 = 1'h0; + (* init = 1'h0 *) + reg Ng1959 = 1'h0; + (* init = 1'h0 *) + reg Ng1964 = 1'h0; + (* init = 1'h0 *) + reg Ng1968 = 1'h0; + (* init = 1'h0 *) + reg Ng1974 = 1'h0; + (* init = 1'h0 *) + reg Ng1978 = 1'h0; + (* init = 1'h0 *) + reg Ng1982 = 1'h0; + (* init = 1'h0 *) + reg Ng1988 = 1'h0; + (* init = 1'h0 *) + reg Ng199 = 1'h0; + (* init = 1'h0 *) + reg Ng1992 = 1'h0; + (* init = 1'h0 *) + reg Ng1996 = 1'h0; + (* init = 1'h0 *) + reg Ng2004 = 1'h0; + (* init = 1'h0 *) + reg Ng2008 = 1'h0; + (* init = 1'h0 *) + reg Ng2012 = 1'h0; + (* init = 1'h0 *) + reg Ng2016 = 1'h0; + (* init = 1'h0 *) + reg Ng2020 = 1'h0; + (* init = 1'h0 *) + reg Ng2024 = 1'h0; + (* init = 1'h0 *) + reg Ng2028 = 1'h0; + (* init = 1'h0 *) + reg Ng203 = 1'h0; + (* init = 1'h0 *) + reg Ng2036 = 1'h0; + (* init = 1'h0 *) + reg Ng2040 = 1'h0; + (* init = 1'h0 *) + reg Ng2047 = 1'h0; + (* init = 1'h0 *) + reg Ng2051 = 1'h0; + (* init = 1'h0 *) + reg Ng2060 = 1'h0; + (* init = 1'h0 *) + reg Ng2066 = 1'h0; + (* init = 1'h0 *) + reg Ng2070 = 1'h0; + (* init = 1'h0 *) + reg Ng2079 = 1'h0; + (* init = 1'h0 *) + reg Ng2084 = 1'h0; + (* init = 1'h0 *) + reg Ng2089 = 1'h0; + (* init = 1'h0 *) + reg Ng209 = 1'h0; + (* init = 1'h0 *) + reg Ng2093 = 1'h0; + (* init = 1'h0 *) + reg Ng2098 = 1'h0; + (* init = 1'h0 *) + reg Ng2102 = 1'h0; + (* init = 1'h0 *) + reg Ng2108 = 1'h0; + (* init = 1'h0 *) + reg Ng2112 = 1'h0; + (* init = 1'h0 *) + reg Ng2116 = 1'h0; + (* init = 1'h0 *) + reg Ng2122 = 1'h0; + (* init = 1'h0 *) + reg Ng2126 = 1'h0; + (* init = 1'h0 *) + reg Ng2130 = 1'h0; + (* init = 1'h0 *) + reg Ng2138 = 1'h0; + (* init = 1'h0 *) + reg Ng2145 = 1'h0; + (* init = 1'h0 *) + reg Ng2153 = 1'h0; + (* init = 1'h0 *) + reg Ng2161 = 1'h0; + (* init = 1'h0 *) + reg Ng2165 = 1'h0; + (* init = 1'h0 *) + reg Ng2169 = 1'h0; + (* init = 1'h0 *) + reg Ng2173 = 1'h0; + (* init = 1'h0 *) + reg Ng2177 = 1'h0; + (* init = 1'h0 *) + reg Ng218 = 1'h0; + (* init = 1'h0 *) + reg Ng2181 = 1'h0; + (* init = 1'h0 *) + reg Ng2185 = 1'h0; + (* init = 1'h0 *) + reg Ng2193 = 1'h0; + (* init = 1'h0 *) + reg Ng2197 = 1'h0; + (* init = 1'h0 *) + reg Ng22 = 1'h0; + (* init = 1'h0 *) + reg Ng2204 = 1'h0; + (* init = 1'h0 *) + reg Ng2208 = 1'h0; + (* init = 1'h0 *) + reg Ng2217 = 1'h0; + (* init = 1'h0 *) + reg Ng222 = 1'h0; + (* init = 1'h0 *) + reg Ng2223 = 1'h0; + (* init = 1'h0 *) + reg Ng2227 = 1'h0; + (* init = 1'h0 *) + reg Ng2236 = 1'h0; + (* init = 1'h0 *) + reg Ng2241 = 1'h0; + (* init = 1'h0 *) + reg Ng2246 = 1'h0; + (* init = 1'h0 *) + reg Ng225 = 1'h0; + (* init = 1'h0 *) + reg Ng2250 = 1'h0; + (* init = 1'h0 *) + reg Ng2255 = 1'h0; + (* init = 1'h0 *) + reg Ng2259 = 1'h0; + (* init = 1'h0 *) + reg Ng2265 = 1'h0; + (* init = 1'h0 *) + reg Ng2269 = 1'h0; + (* init = 1'h0 *) + reg Ng2273 = 1'h0; + (* init = 1'h0 *) + reg Ng2279 = 1'h0; + (* init = 1'h0 *) + reg Ng2283 = 1'h0; + (* init = 1'h0 *) + reg Ng2287 = 1'h0; + (* init = 1'h0 *) + reg Ng2295 = 1'h0; + (* init = 1'h0 *) + reg Ng2299 = 1'h0; + (* init = 1'h0 *) + reg Ng2303 = 1'h0; + (* init = 1'h0 *) + reg Ng2307 = 1'h0; + (* init = 1'h0 *) + reg Ng2311 = 1'h0; + (* init = 1'h0 *) + reg Ng2315 = 1'h0; + (* init = 1'h0 *) + reg Ng2319 = 1'h0; + (* init = 1'h0 *) + reg Ng232 = 1'h0; + (* init = 1'h0 *) + reg Ng2327 = 1'h0; + (* init = 1'h0 *) + reg Ng2331 = 1'h0; + (* init = 1'h0 *) + reg Ng2338 = 1'h0; + (* init = 1'h0 *) + reg Ng2342 = 1'h0; + (* init = 1'h0 *) + reg Ng2351 = 1'h0; + (* init = 1'h0 *) + reg Ng2357 = 1'h0; + (* init = 1'h0 *) + reg Ng2361 = 1'h0; + (* init = 1'h0 *) + reg Ng2370 = 1'h0; + (* init = 1'h0 *) + reg Ng2375 = 1'h0; + (* init = 1'h0 *) + reg Ng2380 = 1'h0; + (* init = 1'h0 *) + reg Ng2384 = 1'h0; + (* init = 1'h0 *) + reg Ng2389 = 1'h0; + (* init = 1'h0 *) + reg Ng239 = 1'h0; + (* init = 1'h0 *) + reg Ng2393 = 1'h0; + (* init = 1'h0 *) + reg Ng2399 = 1'h0; + (* init = 1'h0 *) + reg Ng2403 = 1'h0; + (* init = 1'h0 *) + reg Ng2407 = 1'h0; + (* init = 1'h0 *) + reg Ng2413 = 1'h0; + (* init = 1'h0 *) + reg Ng2417 = 1'h0; + (* init = 1'h0 *) + reg Ng2421 = 1'h0; + (* init = 1'h0 *) + reg Ng2429 = 1'h0; + (* init = 1'h0 *) + reg Ng2433 = 1'h0; + (* init = 1'h0 *) + reg Ng2437 = 1'h0; + (* init = 1'h0 *) + reg Ng2441 = 1'h0; + (* init = 1'h0 *) + reg Ng2445 = 1'h0; + (* init = 1'h0 *) + reg Ng2449 = 1'h0; + (* init = 1'h0 *) + reg Ng2453 = 1'h0; + (* init = 1'h0 *) + reg Ng246 = 1'h0; + (* init = 1'h0 *) + reg Ng2461 = 1'h0; + (* init = 1'h0 *) + reg Ng2465 = 1'h0; + (* init = 1'h0 *) + reg Ng2472 = 1'h0; + (* init = 1'h0 *) + reg Ng2476 = 1'h0; + (* init = 1'h0 *) + reg Ng2485 = 1'h0; + (* init = 1'h0 *) + reg Ng2491 = 1'h0; + (* init = 1'h0 *) + reg Ng2495 = 1'h0; + (* init = 1'h0 *) + reg Ng2504 = 1'h0; + (* init = 1'h0 *) + reg Ng2509 = 1'h0; + (* init = 1'h0 *) + reg Ng2514 = 1'h0; + (* init = 1'h0 *) + reg Ng2518 = 1'h0; + (* init = 1'h0 *) + reg Ng2523 = 1'h0; + (* init = 1'h0 *) + reg Ng2527 = 1'h0; + (* init = 1'h0 *) + reg Ng2533 = 1'h0; + (* init = 1'h0 *) + reg Ng2537 = 1'h0; + (* init = 1'h0 *) + reg Ng2541 = 1'h0; + (* init = 1'h0 *) + reg Ng2547 = 1'h0; + (* init = 1'h0 *) + reg Ng255 = 1'h0; + (* init = 1'h0 *) + reg Ng2551 = 1'h0; + (* init = 1'h0 *) + reg Ng2555 = 1'h0; + (* init = 1'h0 *) + reg Ng2563 = 1'h0; + (* init = 1'h0 *) + reg Ng2567 = 1'h0; + (* init = 1'h0 *) + reg Ng2571 = 1'h0; + (* init = 1'h0 *) + reg Ng2575 = 1'h0; + (* init = 1'h0 *) + reg Ng2579 = 1'h0; + (* init = 1'h0 *) + reg Ng2583 = 1'h0; + (* init = 1'h0 *) + reg Ng2587 = 1'h0; + (* init = 1'h0 *) + reg Ng2595 = 1'h0; + (* init = 1'h0 *) + reg Ng2599 = 1'h0; + (* init = 1'h0 *) + reg Ng2606 = 1'h0; + (* init = 1'h0 *) + reg Ng2610 = 1'h0; + (* init = 1'h0 *) + reg Ng2619 = 1'h0; + (* init = 1'h0 *) + reg Ng262 = 1'h0; + (* init = 1'h0 *) + reg Ng2625 = 1'h0; + (* init = 1'h0 *) + reg Ng2629 = 1'h0; + (* init = 1'h0 *) + reg Ng2638 = 1'h0; + (* init = 1'h0 *) + reg Ng2643 = 1'h0; + (* init = 1'h0 *) + reg Ng2648 = 1'h0; + (* init = 1'h0 *) + reg Ng2652 = 1'h0; + (* init = 1'h0 *) + reg Ng2657 = 1'h0; + (* init = 1'h0 *) + reg Ng2661 = 1'h0; + (* init = 1'h0 *) + reg Ng2667 = 1'h0; + (* init = 1'h0 *) + reg Ng2671 = 1'h0; + (* init = 1'h0 *) + reg Ng2675 = 1'h0; + (* init = 1'h0 *) + reg Ng2681 = 1'h0; + (* init = 1'h0 *) + reg Ng2685 = 1'h0; + (* init = 1'h0 *) + reg Ng26885 = 1'h0; + (* init = 1'h0 *) + reg Ng2689 = 1'h0; + (* init = 1'h0 *) + reg Ng269 = 1'h0; + (* init = 1'h0 *) + reg Ng26936 = 1'h0; + (* init = 1'h0 *) + reg Ng26959 = 1'h0; + (* init = 1'h0 *) + reg Ng26960 = 1'h0; + (* init = 1'h0 *) + reg Ng2697 = 1'h0; + (* init = 1'h0 *) + reg Ng2704 = 1'h0; + (* init = 1'h0 *) + reg Ng2712 = 1'h0; + (* init = 1'h0 *) + reg Ng2715 = 1'h0; + (* init = 1'h0 *) + reg Ng2719 = 1'h0; + (* init = 1'h0 *) + reg Ng2724 = 1'h0; + (* init = 1'h0 *) + reg Ng2729 = 1'h0; + (* init = 1'h0 *) + reg Ng2735 = 1'h0; + (* init = 1'h0 *) + reg Ng2741 = 1'h0; + (* init = 1'h0 *) + reg Ng2748 = 1'h0; + (* init = 1'h0 *) + reg Ng2756 = 1'h0; + (* init = 1'h0 *) + reg Ng2759 = 1'h0; + (* init = 1'h0 *) + reg Ng2763 = 1'h0; + (* init = 1'h0 *) + reg Ng2767 = 1'h0; + (* init = 1'h0 *) + reg Ng2771 = 1'h0; + (* init = 1'h0 *) + reg Ng2775 = 1'h0; + (* init = 1'h0 *) + reg Ng2779 = 1'h0; + (* init = 1'h0 *) + reg Ng278 = 1'h0; + (* init = 1'h0 *) + reg Ng2783 = 1'h0; + (* init = 1'h0 *) + reg Ng2787 = 1'h0; + (* init = 1'h0 *) + reg Ng2791 = 1'h0; + (* init = 1'h0 *) + reg Ng2795 = 1'h0; + (* init = 1'h0 *) + reg Ng2799 = 1'h0; + (* init = 1'h0 *) + reg Ng2803 = 1'h0; + (* init = 1'h0 *) + reg Ng2807 = 1'h0; + (* init = 1'h0 *) + reg Ng2811 = 1'h0; + (* init = 1'h0 *) + reg Ng2815 = 1'h0; + (* init = 1'h0 *) + reg Ng2819 = 1'h0; + (* init = 1'h0 *) + reg Ng2823 = 1'h0; + (* init = 1'h0 *) + reg Ng2827 = 1'h0; + (* init = 1'h0 *) + reg Ng283 = 1'h0; + (* init = 1'h0 *) + reg Ng2831 = 1'h0; + (* init = 1'h0 *) + reg Ng2834 = 1'h0; + (* init = 1'h0 *) + reg Ng2841 = 1'h0; + (* init = 1'h0 *) + reg Ng2844 = 1'h0; + (* init = 1'h0 *) + reg Ng2848 = 1'h0; + (* init = 1'h0 *) + reg Ng2852 = 1'h0; + (* init = 1'h0 *) + reg Ng2856 = 1'h0; + (* init = 1'h0 *) + reg Ng2860 = 1'h0; + (* init = 1'h0 *) + reg Ng2864 = 1'h0; + (* init = 1'h0 *) + reg Ng2868 = 1'h0; + (* init = 1'h0 *) + reg Ng287 = 1'h0; + (* init = 1'h0 *) + reg Ng2873 = 1'h0; + (* init = 1'h0 *) + reg Ng2878 = 1'h0; + (* init = 1'h0 *) + reg Ng2882 = 1'h0; + (* init = 1'h0 *) + reg Ng2886 = 1'h0; + (* init = 1'h0 *) + reg Ng2890 = 1'h0; + (* init = 1'h0 *) + reg Ng2894 = 1'h0; + (* init = 1'h0 *) + reg Ng2898 = 1'h0; + (* init = 1'h0 *) + reg Ng2902 = 1'h0; + (* init = 1'h0 *) + reg Ng2907 = 1'h0; + (* init = 1'h0 *) + reg Ng291 = 1'h0; + (* init = 1'h0 *) + reg Ng2912 = 1'h0; + (* init = 1'h0 *) + reg Ng2917 = 1'h0; + (* init = 1'h0 *) + reg Ng2922 = 1'h0; + (* init = 1'h0 *) + reg Ng2927 = 1'h0; + (* init = 1'h0 *) + reg Ng2932 = 1'h0; + (* init = 1'h0 *) + reg Ng2936 = 1'h0; + (* init = 1'h0 *) + reg Ng294 = 1'h0; + (* init = 1'h0 *) + reg Ng2941 = 1'h0; + (* init = 1'h0 *) + reg Ng2946 = 1'h0; + (* init = 1'h0 *) + reg Ng2950 = 1'h0; + (* init = 1'h0 *) + reg Ng2955 = 1'h0; + (* init = 1'h0 *) + reg Ng2960 = 1'h0; + (* init = 1'h0 *) + reg Ng2965 = 1'h0; + (* init = 1'h0 *) + reg Ng2970 = 1'h0; + (* init = 1'h0 *) + reg Ng2975 = 1'h0; + (* init = 1'h0 *) + reg Ng298 = 1'h0; + (* init = 1'h0 *) + reg Ng2980 = 1'h0; + (* init = 1'h0 *) + reg Ng2984 = 1'h0; + (* init = 1'h0 *) + reg Ng2988 = 1'h0; + (* init = 1'h0 *) + reg Ng2994 = 1'h0; + (* init = 1'h0 *) + reg Ng2999 = 1'h0; + (* init = 1'h0 *) + reg Ng3003 = 1'h0; + (* init = 1'h0 *) + reg Ng301 = 1'h0; + (* init = 1'h0 *) + reg Ng305 = 1'h0; + (* init = 1'h0 *) + reg Ng3050 = 1'h0; + (* init = 1'h0 *) + reg Ng3100 = 1'h0; + (* init = 1'h0 *) + reg Ng3106 = 1'h0; + (* init = 1'h0 *) + reg Ng311 = 1'h0; + (* init = 1'h0 *) + reg Ng3111 = 1'h0; + (* init = 1'h0 *) + reg Ng3115 = 1'h0; + (* init = 1'h0 *) + reg Ng3119 = 1'h0; + (* init = 1'h0 *) + reg Ng3125 = 1'h0; + (* init = 1'h0 *) + reg Ng3129 = 1'h0; + (* init = 1'h0 *) + reg Ng3133 = 1'h0; + (* init = 1'h0 *) + reg Ng3139 = 1'h0; + (* init = 1'h0 *) + reg Ng3143 = 1'h0; + (* init = 1'h0 *) + reg Ng3147 = 1'h0; + (* init = 1'h0 *) + reg Ng3151 = 1'h0; + (* init = 1'h0 *) + reg Ng3155 = 1'h0; + (* init = 1'h0 *) + reg Ng316 = 1'h0; + (* init = 1'h0 *) + reg Ng3161 = 1'h0; + (* init = 1'h0 *) + reg Ng3167 = 1'h0; + (* init = 1'h0 *) + reg Ng3171 = 1'h0; + (* init = 1'h0 *) + reg Ng3179 = 1'h0; + (* init = 1'h0 *) + reg Ng3187 = 1'h0; + (* init = 1'h0 *) + reg Ng3191 = 1'h0; + (* init = 1'h0 *) + reg Ng3195 = 1'h0; + (* init = 1'h0 *) + reg Ng3199 = 1'h0; + (* init = 1'h0 *) + reg Ng3203 = 1'h0; + (* init = 1'h0 *) + reg Ng3207 = 1'h0; + (* init = 1'h0 *) + reg Ng3211 = 1'h0; + (* init = 1'h0 *) + reg Ng3215 = 1'h0; + (* init = 1'h0 *) + reg Ng3219 = 1'h0; + (* init = 1'h0 *) + reg Ng3223 = 1'h0; + (* init = 1'h0 *) + reg Ng3227 = 1'h0; + (* init = 1'h0 *) + reg Ng3231 = 1'h0; + (* init = 1'h0 *) + reg Ng3235 = 1'h0; + (* init = 1'h0 *) + reg Ng3239 = 1'h0; + (* init = 1'h0 *) + reg Ng324 = 1'h0; + (* init = 1'h0 *) + reg Ng3243 = 1'h0; + (* init = 1'h0 *) + reg Ng3247 = 1'h0; + (* init = 1'h0 *) + reg Ng3251 = 1'h0; + (* init = 1'h0 *) + reg Ng3255 = 1'h0; + (* init = 1'h0 *) + reg Ng3259 = 1'h0; + (* init = 1'h0 *) + reg Ng3263 = 1'h0; + (* init = 1'h0 *) + reg Ng3288 = 1'h0; + (* init = 1'h0 *) + reg Ng329 = 1'h0; + (* init = 1'h0 *) + reg Ng3329 = 1'h0; + (* init = 1'h0 *) + reg Ng333 = 1'h0; + (* init = 1'h0 *) + reg Ng3333 = 1'h0; + (* init = 1'h0 *) + reg Ng3338 = 1'h0; + (* init = 1'h0 *) + reg Ng3343 = 1'h0; + (* init = 1'h0 *) + reg Ng3347 = 1'h0; + (* init = 1'h0 *) + reg Ng3352 = 1'h0; + (* init = 1'h0 *) + reg Ng336 = 1'h0; + (* init = 1'h0 *) + reg Ng3401 = 1'h0; + (* init = 1'h0 *) + reg Ng341 = 1'h0; + (* init = 1'h0 *) + reg Ng3451 = 1'h0; + (* init = 1'h0 *) + reg Ng3457 = 1'h0; + (* init = 1'h0 *) + reg Ng3462 = 1'h0; + (* init = 1'h0 *) + reg Ng3466 = 1'h0; + (* init = 1'h0 *) + reg Ng347 = 1'h0; + (* init = 1'h0 *) + reg Ng3470 = 1'h0; + (* init = 1'h0 *) + reg Ng3476 = 1'h0; + (* init = 1'h0 *) + reg Ng3480 = 1'h0; + (* init = 1'h0 *) + reg Ng3484 = 1'h0; + (* init = 1'h0 *) + reg Ng3490 = 1'h0; + (* init = 1'h0 *) + reg Ng3494 = 1'h0; + (* init = 1'h0 *) + reg Ng3498 = 1'h0; + (* init = 1'h0 *) + reg Ng3502 = 1'h0; + (* init = 1'h0 *) + reg Ng3506 = 1'h0; + (* init = 1'h0 *) + reg Ng351 = 1'h0; + (* init = 1'h0 *) + reg Ng3512 = 1'h0; + (* init = 1'h0 *) + reg Ng3518 = 1'h0; + (* init = 1'h0 *) + reg Ng3522 = 1'h0; + (* init = 1'h0 *) + reg Ng3530 = 1'h0; + (* init = 1'h0 *) + reg Ng3538 = 1'h0; + (* init = 1'h0 *) + reg Ng3542 = 1'h0; + (* init = 1'h0 *) + reg Ng3546 = 1'h0; + (* init = 1'h0 *) + reg Ng355 = 1'h0; + (* init = 1'h0 *) + reg Ng3550 = 1'h0; + (* init = 1'h0 *) + reg Ng3554 = 1'h0; + (* init = 1'h0 *) + reg Ng3558 = 1'h0; + (* init = 1'h0 *) + reg Ng3562 = 1'h0; + (* init = 1'h0 *) + reg Ng3566 = 1'h0; + (* init = 1'h0 *) + reg Ng3570 = 1'h0; + (* init = 1'h0 *) + reg Ng3574 = 1'h0; + (* init = 1'h0 *) + reg Ng3578 = 1'h0; + (* init = 1'h0 *) + reg Ng358 = 1'h0; + (* init = 1'h0 *) + reg Ng3582 = 1'h0; + (* init = 1'h0 *) + reg Ng3586 = 1'h0; + (* init = 1'h0 *) + reg Ng3590 = 1'h0; + (* init = 1'h0 *) + reg Ng3594 = 1'h0; + (* init = 1'h0 *) + reg Ng3598 = 1'h0; + (* init = 1'h0 *) + reg Ng3602 = 1'h0; + (* init = 1'h0 *) + reg Ng3606 = 1'h0; + (* init = 1'h0 *) + reg Ng3610 = 1'h0; + (* init = 1'h0 *) + reg Ng3614 = 1'h0; + (* init = 1'h0 *) + reg Ng3639 = 1'h0; + (* init = 1'h0 *) + reg Ng3680 = 1'h0; + (* init = 1'h0 *) + reg Ng3684 = 1'h0; + (* init = 1'h0 *) + reg Ng3689 = 1'h0; + (* init = 1'h0 *) + reg Ng3694 = 1'h0; + (* init = 1'h0 *) + reg Ng3698 = 1'h0; + (* init = 1'h0 *) + reg Ng37 = 1'h0; + (* init = 1'h0 *) + reg Ng370 = 1'h0; + (* init = 1'h0 *) + reg Ng3703 = 1'h0; + (* init = 1'h0 *) + reg Ng3752 = 1'h0; + (* init = 1'h0 *) + reg Ng376 = 1'h0; + (* init = 1'h0 *) + reg Ng3802 = 1'h0; + (* init = 1'h0 *) + reg Ng3808 = 1'h0; + (* init = 1'h0 *) + reg Ng3813 = 1'h0; + (* init = 1'h0 *) + reg Ng3817 = 1'h0; + (* init = 1'h0 *) + reg Ng3821 = 1'h0; + (* init = 1'h0 *) + reg Ng3827 = 1'h0; + (* init = 1'h0 *) + reg Ng3831 = 1'h0; + (* init = 1'h0 *) + reg Ng3835 = 1'h0; + (* init = 1'h0 *) + reg Ng3841 = 1'h0; + (* init = 1'h0 *) + reg Ng3845 = 1'h0; + (* init = 1'h0 *) + reg Ng3849 = 1'h0; + (* init = 1'h0 *) + reg Ng385 = 1'h0; + (* init = 1'h0 *) + reg Ng3853 = 1'h0; + (* init = 1'h0 *) + reg Ng3857 = 1'h0; + (* init = 1'h0 *) + reg Ng3863 = 1'h0; + (* init = 1'h0 *) + reg Ng3869 = 1'h0; + (* init = 1'h0 *) + reg Ng3873 = 1'h0; + (* init = 1'h0 *) + reg Ng3881 = 1'h0; + (* init = 1'h0 *) + reg Ng3889 = 1'h0; + (* init = 1'h0 *) + reg Ng3893 = 1'h0; + (* init = 1'h0 *) + reg Ng3897 = 1'h0; + (* init = 1'h0 *) + reg Ng3901 = 1'h0; + (* init = 1'h0 *) + reg Ng3905 = 1'h0; + (* init = 1'h0 *) + reg Ng3909 = 1'h0; + (* init = 1'h0 *) + reg Ng3913 = 1'h0; + (* init = 1'h0 *) + reg Ng3917 = 1'h0; + (* init = 1'h0 *) + reg Ng392 = 1'h0; + (* init = 1'h0 *) + reg Ng3921 = 1'h0; + (* init = 1'h0 *) + reg Ng3925 = 1'h0; + (* init = 1'h0 *) + reg Ng3929 = 1'h0; + (* init = 1'h0 *) + reg Ng3933 = 1'h0; + (* init = 1'h0 *) + reg Ng3937 = 1'h0; + (* init = 1'h0 *) + reg Ng3941 = 1'h0; + (* init = 1'h0 *) + reg Ng3945 = 1'h0; + (* init = 1'h0 *) + reg Ng3949 = 1'h0; + (* init = 1'h0 *) + reg Ng3953 = 1'h0; + (* init = 1'h0 *) + reg Ng3957 = 1'h0; + (* init = 1'h0 *) + reg Ng3961 = 1'h0; + (* init = 1'h0 *) + reg Ng3965 = 1'h0; + (* init = 1'h0 *) + reg Ng3990 = 1'h0; + (* init = 1'h0 *) + reg Ng401 = 1'h0; + (* init = 1'h0 *) + reg Ng4031 = 1'h0; + (* init = 1'h0 *) + reg Ng4035 = 1'h0; + (* init = 1'h0 *) + reg Ng4040 = 1'h0; + (* init = 1'h0 *) + reg Ng4045 = 1'h0; + (* init = 1'h0 *) + reg Ng4049 = 1'h0; + (* init = 1'h0 *) + reg Ng405 = 1'h0; + (* init = 1'h0 *) + reg Ng4054 = 1'h0; + (* init = 1'h0 *) + reg Ng4057 = 1'h0; + (* init = 1'h0 *) + reg Ng4064 = 1'h0; + (* init = 1'h0 *) + reg Ng4072 = 1'h0; + (* init = 1'h0 *) + reg Ng4076 = 1'h0; + (* init = 1'h0 *) + reg Ng4082 = 1'h0; + (* init = 1'h0 *) + reg Ng4087 = 1'h0; + (* init = 1'h0 *) + reg Ng4093 = 1'h0; + (* init = 1'h0 *) + reg Ng4098 = 1'h0; + (* init = 1'h0 *) + reg Ng4104 = 1'h0; + (* init = 1'h0 *) + reg Ng4108 = 1'h0; + (* init = 1'h0 *) + reg Ng411 = 1'h0; + (* init = 1'h0 *) + reg Ng4112 = 1'h0; + (* init = 1'h0 *) + reg Ng4116 = 1'h0; + (* init = 1'h0 *) + reg Ng4119 = 1'h0; + (* init = 1'h0 *) + reg Ng4122 = 1'h0; + (* init = 1'h0 *) + reg Ng4125 = 1'h0; + (* init = 1'h0 *) + reg Ng4141 = 1'h0; + (* init = 1'h0 *) + reg Ng4145 = 1'h0; + (* init = 1'h0 *) + reg Ng4146 = 1'h0; + (* init = 1'h0 *) + reg Ng4153 = 1'h0; + (* init = 1'h0 *) + reg Ng4157 = 1'h0; + (* init = 1'h0 *) + reg Ng4164 = 1'h0; + (* init = 1'h0 *) + reg Ng417 = 1'h0; + (* init = 1'h0 *) + reg Ng4172 = 1'h0; + (* init = 1'h0 *) + reg Ng4176 = 1'h0; + (* init = 1'h0 *) + reg Ng4180 = 1'h0; + (* init = 1'h0 *) + reg Ng4235 = 1'h0; + (* init = 1'h0 *) + reg Ng4239 = 1'h0; + (* init = 1'h0 *) + reg Ng424 = 1'h0; + (* init = 1'h0 *) + reg Ng4242 = 1'h0; + (* init = 1'h0 *) + reg Ng4245 = 1'h0; + (* init = 1'h0 *) + reg Ng4249 = 1'h0; + (* init = 1'h0 *) + reg Ng4253 = 1'h0; + (* init = 1'h0 *) + reg Ng4258 = 1'h0; + (* init = 1'h0 *) + reg Ng4264 = 1'h0; + (* init = 1'h0 *) + reg Ng4269 = 1'h0; + (* init = 1'h0 *) + reg Ng4273 = 1'h0; + (* init = 1'h0 *) + reg Ng4281 = 1'h0; + (* init = 1'h0 *) + reg Ng4284 = 1'h0; + (* init = 1'h0 *) + reg Ng429 = 1'h0; + (* init = 1'h0 *) + reg Ng4291 = 1'h0; + (* init = 1'h0 *) + reg Ng4297 = 1'h0; + (* init = 1'h0 *) + reg Ng43 = 1'h0; + (* init = 1'h0 *) + reg Ng4300 = 1'h0; + (* init = 1'h0 *) + reg Ng4308 = 1'h0; + (* init = 1'h0 *) + reg Ng4311 = 1'h0; + (* init = 1'h0 *) + reg Ng4322 = 1'h0; + (* init = 1'h0 *) + reg Ng433 = 1'h0; + (* init = 1'h0 *) + reg Ng4332 = 1'h0; + (* init = 1'h0 *) + reg Ng4340 = 1'h0; + (* init = 1'h0 *) + reg Ng4349 = 1'h0; + (* init = 1'h0 *) + reg Ng4358 = 1'h0; + (* init = 1'h0 *) + reg Ng4366 = 1'h0; + (* init = 1'h0 *) + reg Ng4369 = 1'h0; + (* init = 1'h0 *) + reg Ng437 = 1'h0; + (* init = 1'h0 *) + reg Ng4372 = 1'h0; + (* init = 1'h0 *) + reg Ng4375 = 1'h0; + (* init = 1'h0 *) + reg Ng4382 = 1'h0; + (* init = 1'h0 *) + reg Ng4388 = 1'h0; + (* init = 1'h0 *) + reg Ng4392 = 1'h0; + (* init = 1'h0 *) + reg Ng4401 = 1'h0; + (* init = 1'h0 *) + reg Ng4405 = 1'h0; + (* init = 1'h0 *) + reg Ng441 = 1'h0; + (* init = 1'h0 *) + reg Ng4411 = 1'h0; + (* init = 1'h0 *) + reg Ng4417 = 1'h0; + (* init = 1'h0 *) + reg Ng4420 = 1'h0; + (* init = 1'h0 *) + reg Ng4423 = 1'h0; + (* init = 1'h0 *) + reg Ng4427 = 1'h0; + (* init = 1'h0 *) + reg Ng4430 = 1'h0; + (* init = 1'h0 *) + reg Ng4434 = 1'h0; + (* init = 1'h0 *) + reg Ng4438 = 1'h0; + (* init = 1'h0 *) + reg Ng4443 = 1'h0; + (* init = 1'h0 *) + reg Ng4452 = 1'h0; + (* init = 1'h0 *) + reg Ng4455 = 1'h0; + (* init = 1'h0 *) + reg Ng4459 = 1'h0; + (* init = 1'h0 *) + reg Ng446 = 1'h0; + (* init = 1'h0 *) + reg Ng4462 = 1'h0; + (* init = 1'h0 *) + reg Ng4473 = 1'h0; + (* init = 1'h0 *) + reg Ng4477 = 1'h0; + (* init = 1'h0 *) + reg Ng4480 = 1'h0; + (* init = 1'h0 *) + reg Ng4483 = 1'h0; + (* init = 1'h0 *) + reg Ng4486 = 1'h0; + (* init = 1'h0 *) + reg Ng4489 = 1'h0; + (* init = 1'h0 *) + reg Ng4492 = 1'h0; + (* init = 1'h0 *) + reg Ng4495 = 1'h0; + (* init = 1'h0 *) + reg Ng4498 = 1'h0; + (* init = 1'h0 *) + reg Ng45 = 1'h0; + (* init = 1'h0 *) + reg Ng4501 = 1'h0; + (* init = 1'h0 *) + reg Ng4504 = 1'h0; + (* init = 1'h0 *) + reg Ng4507 = 1'h0; + (* init = 1'h0 *) + reg Ng4512 = 1'h0; + (* init = 1'h0 *) + reg Ng4515 = 1'h0; + (* init = 1'h0 *) + reg Ng452 = 1'h0; + (* init = 1'h0 *) + reg Ng4520 = 1'h0; + (* init = 1'h0 *) + reg Ng4521 = 1'h0; + (* init = 1'h0 *) + reg Ng4527 = 1'h0; + (* init = 1'h0 *) + reg Ng4531 = 1'h0; + (* init = 1'h0 *) + reg Ng4534 = 1'h0; + (* init = 1'h0 *) + reg Ng4540 = 1'h0; + (* init = 1'h0 *) + reg Ng4543 = 1'h0; + (* init = 1'h0 *) + reg Ng4546 = 1'h0; + (* init = 1'h0 *) + reg Ng4549 = 1'h0; + (* init = 1'h0 *) + reg Ng4552 = 1'h0; + (* init = 1'h0 *) + reg Ng4555 = 1'h0; + (* init = 1'h0 *) + reg Ng4558 = 1'h0; + (* init = 1'h0 *) + reg Ng4561 = 1'h0; + (* init = 1'h0 *) + reg Ng4564 = 1'h0; + (* init = 1'h0 *) + reg Ng4567 = 1'h0; + (* init = 1'h0 *) + reg Ng4571 = 1'h0; + (* init = 1'h0 *) + reg Ng4572 = 1'h0; + (* init = 1'h0 *) + reg Ng4575 = 1'h0; + (* init = 1'h0 *) + reg Ng4578 = 1'h0; + (* init = 1'h0 *) + reg Ng4581 = 1'h0; + (* init = 1'h0 *) + reg Ng4584 = 1'h0; + (* init = 1'h0 *) + reg Ng4593 = 1'h0; + (* init = 1'h0 *) + reg Ng46 = 1'h0; + (* init = 1'h0 *) + reg Ng460 = 1'h0; + (* init = 1'h0 *) + reg Ng4601 = 1'h0; + (* init = 1'h0 *) + reg Ng4608 = 1'h0; + (* init = 1'h0 *) + reg Ng4616 = 1'h0; + (* init = 1'h0 *) + reg Ng4621 = 1'h0; + (* init = 1'h0 *) + reg Ng4628 = 1'h0; + (* init = 1'h0 *) + reg Ng4633 = 1'h0; + (* init = 1'h0 *) + reg Ng4639 = 1'h0; + (* init = 1'h0 *) + reg Ng4643 = 1'h0; + (* init = 1'h0 *) + reg Ng4646 = 1'h0; + (* init = 1'h0 *) + reg Ng4653 = 1'h0; + (* init = 1'h0 *) + reg Ng4659 = 1'h0; + (* init = 1'h0 *) + reg Ng4664 = 1'h0; + (* init = 1'h0 *) + reg Ng4669 = 1'h0; + (* init = 1'h0 *) + reg Ng4674 = 1'h0; + (* init = 1'h0 *) + reg Ng4681 = 1'h0; + (* init = 1'h0 *) + reg Ng4688 = 1'h0; + (* init = 1'h0 *) + reg Ng4698 = 1'h0; + (* init = 1'h0 *) + reg Ng4704 = 1'h0; + (* init = 1'h0 *) + reg Ng4709 = 1'h0; + (* init = 1'h0 *) + reg Ng4717 = 1'h0; + (* init = 1'h0 *) + reg Ng4722 = 1'h0; + (* init = 1'h0 *) + reg Ng4727 = 1'h0; + (* init = 1'h0 *) + reg Ng4732 = 1'h0; + (* init = 1'h0 *) + reg Ng4737 = 1'h0; + (* init = 1'h0 *) + reg Ng4743 = 1'h0; + (* init = 1'h0 *) + reg Ng4749 = 1'h0; + (* init = 1'h0 *) + reg Ng475 = 1'h0; + (* init = 1'h0 *) + reg Ng4754 = 1'h0; + (* init = 1'h0 *) + reg Ng4760 = 1'h0; + (* init = 1'h0 *) + reg Ng4765 = 1'h0; + (* init = 1'h0 *) + reg Ng4771 = 1'h0; + (* init = 1'h0 *) + reg Ng4776 = 1'h0; + (* init = 1'h0 *) + reg Ng4785 = 1'h0; + (* init = 1'h0 *) + reg Ng479 = 1'h0; + (* init = 1'h0 *) + reg Ng4793 = 1'h0; + (* init = 1'h0 *) + reg Ng48 = 1'h0; + (* init = 1'h0 *) + reg Ng4801 = 1'h0; + (* init = 1'h0 *) + reg Ng4818 = 1'h0; + (* init = 1'h0 *) + reg Ng482 = 1'h0; + (* init = 1'h0 *) + reg Ng4821 = 1'h0; + (* init = 1'h0 *) + reg Ng4826 = 1'h0; + (* init = 1'h0 *) + reg Ng4831 = 1'h0; + (* init = 1'h0 *) + reg Ng4836 = 1'h0; + (* init = 1'h0 *) + reg Ng4843 = 1'h0; + (* init = 1'h0 *) + reg Ng4849 = 1'h0; + (* init = 1'h0 *) + reg Ng4854 = 1'h0; + (* init = 1'h0 *) + reg Ng4859 = 1'h0; + (* init = 1'h0 *) + reg Ng4864 = 1'h0; + (* init = 1'h0 *) + reg Ng4871 = 1'h0; + (* init = 1'h0 *) + reg Ng4878 = 1'h0; + (* init = 1'h0 *) + reg Ng4888 = 1'h0; + (* init = 1'h0 *) + reg Ng4894 = 1'h0; + (* init = 1'h0 *) + reg Ng4899 = 1'h0; + (* init = 1'h0 *) + reg Ng490 = 1'h0; + (* init = 1'h0 *) + reg Ng4907 = 1'h0; + (* init = 1'h0 *) + reg Ng4912 = 1'h0; + (* init = 1'h0 *) + reg Ng4917 = 1'h0; + (* init = 1'h0 *) + reg Ng4922 = 1'h0; + (* init = 1'h0 *) + reg Ng4927 = 1'h0; + (* init = 1'h0 *) + reg Ng4933 = 1'h0; + (* init = 1'h0 *) + reg Ng4939 = 1'h0; + (* init = 1'h0 *) + reg Ng4944 = 1'h0; + (* init = 1'h0 *) + reg Ng4950 = 1'h0; + (* init = 1'h0 *) + reg Ng4955 = 1'h0; + (* init = 1'h0 *) + reg Ng496 = 1'h0; + (* init = 1'h0 *) + reg Ng4961 = 1'h0; + (* init = 1'h0 *) + reg Ng4966 = 1'h0; + (* init = 1'h0 *) + reg Ng4975 = 1'h0; + (* init = 1'h0 *) + reg Ng4983 = 1'h0; + (* init = 1'h0 *) + reg Ng499 = 1'h0; + (* init = 1'h0 *) + reg Ng4991 = 1'h0; + (* init = 1'h0 *) + reg Ng50 = 1'h0; + (* init = 1'h0 *) + reg Ng5011 = 1'h0; + (* init = 1'h0 *) + reg Ng5016 = 1'h0; + (* init = 1'h0 *) + reg Ng5022 = 1'h0; + (* init = 1'h0 *) + reg Ng5029 = 1'h0; + (* init = 1'h0 *) + reg Ng5033 = 1'h0; + (* init = 1'h0 *) + reg Ng5037 = 1'h0; + (* init = 1'h0 *) + reg Ng504 = 1'h0; + (* init = 1'h0 *) + reg Ng5041 = 1'h0; + (* init = 1'h0 *) + reg Ng5046 = 1'h0; + (* init = 1'h0 *) + reg Ng5052 = 1'h0; + (* init = 1'h0 *) + reg Ng5057 = 1'h0; + (* init = 1'h0 *) + reg Ng5062 = 1'h0; + (* init = 1'h0 *) + reg Ng5069 = 1'h0; + (* init = 1'h0 *) + reg Ng5073 = 1'h0; + (* init = 1'h0 *) + reg Ng5077 = 1'h0; + (* init = 1'h0 *) + reg Ng5080 = 1'h0; + (* init = 1'h0 *) + reg Ng5084 = 1'h0; + (* init = 1'h0 *) + reg Ng5092 = 1'h0; + (* init = 1'h0 *) + reg Ng5097 = 1'h0; + (* init = 1'h0 *) + reg Ng51 = 1'h0; + (* init = 1'h0 *) + reg Ng5109 = 1'h0; + (* init = 1'h0 *) + reg Ng5112 = 1'h0; + (* init = 1'h0 *) + reg Ng5115 = 1'h0; + (* init = 1'h0 *) + reg Ng5120 = 1'h0; + (* init = 1'h0 *) + reg Ng5124 = 1'h0; + (* init = 1'h0 *) + reg Ng5128 = 1'h0; + (* init = 1'h0 *) + reg Ng513 = 1'h0; + (* init = 1'h0 *) + reg Ng5134 = 1'h0; + (* init = 1'h0 *) + reg Ng5138 = 1'h0; + (* init = 1'h0 *) + reg Ng5142 = 1'h0; + (* init = 1'h0 *) + reg Ng5148 = 1'h0; + (* init = 1'h0 *) + reg Ng5152 = 1'h0; + (* init = 1'h0 *) + reg Ng5156 = 1'h0; + (* init = 1'h0 *) + reg Ng5160 = 1'h0; + (* init = 1'h0 *) + reg Ng5164 = 1'h0; + (* init = 1'h0 *) + reg Ng5170 = 1'h0; + (* init = 1'h0 *) + reg Ng5176 = 1'h0; + (* init = 1'h0 *) + reg Ng518 = 1'h0; + (* init = 1'h0 *) + reg Ng5180 = 1'h0; + (* init = 1'h0 *) + reg Ng5188 = 1'h0; + (* init = 1'h0 *) + reg Ng5196 = 1'h0; + (* init = 1'h0 *) + reg Ng52 = 1'h0; + (* init = 1'h0 *) + reg Ng5200 = 1'h0; + (* init = 1'h0 *) + reg Ng5204 = 1'h0; + (* init = 1'h0 *) + reg Ng5208 = 1'h0; + (* init = 1'h0 *) + reg Ng5212 = 1'h0; + (* init = 1'h0 *) + reg Ng5216 = 1'h0; + (* init = 1'h0 *) + reg Ng5220 = 1'h0; + (* init = 1'h0 *) + reg Ng5224 = 1'h0; + (* init = 1'h0 *) + reg Ng5228 = 1'h0; + (* init = 1'h0 *) + reg Ng5232 = 1'h0; + (* init = 1'h0 *) + reg Ng5236 = 1'h0; + (* init = 1'h0 *) + reg Ng5240 = 1'h0; + (* init = 1'h0 *) + reg Ng5244 = 1'h0; + (* init = 1'h0 *) + reg Ng5248 = 1'h0; + (* init = 1'h0 *) + reg Ng5252 = 1'h0; + (* init = 1'h0 *) + reg Ng5256 = 1'h0; + (* init = 1'h0 *) + reg Ng5260 = 1'h0; + (* init = 1'h0 *) + reg Ng5264 = 1'h0; + (* init = 1'h0 *) + reg Ng5268 = 1'h0; + (* init = 1'h0 *) + reg Ng5272 = 1'h0; + (* init = 1'h0 *) + reg Ng528 = 1'h0; + (* init = 1'h0 *) + reg Ng5297 = 1'h0; + (* init = 1'h0 *) + reg Ng5339 = 1'h0; + (* init = 1'h0 *) + reg Ng534 = 1'h0; + (* init = 1'h0 *) + reg Ng5348 = 1'h0; + (* init = 1'h0 *) + reg Ng5352 = 1'h0; + (* init = 1'h0 *) + reg Ng5357 = 1'h0; + (* init = 1'h0 *) + reg Ng538 = 1'h0; + (* init = 1'h0 *) + reg Ng5406 = 1'h0; + (* init = 1'h0 *) + reg Ng542 = 1'h0; + (* init = 1'h0 *) + reg Ng5456 = 1'h0; + (* init = 1'h0 *) + reg Ng546 = 1'h0; + (* init = 1'h0 *) + reg Ng5462 = 1'h0; + (* init = 1'h0 *) + reg Ng5467 = 1'h0; + (* init = 1'h0 *) + reg Ng5471 = 1'h0; + (* init = 1'h0 *) + reg Ng5475 = 1'h0; + (* init = 1'h0 *) + reg Ng5481 = 1'h0; + (* init = 1'h0 *) + reg Ng5485 = 1'h0; + (* init = 1'h0 *) + reg Ng5489 = 1'h0; + (* init = 1'h0 *) + reg Ng5495 = 1'h0; + (* init = 1'h0 *) + reg Ng5499 = 1'h0; + (* init = 1'h0 *) + reg Ng55 = 1'h0; + (* init = 1'h0 *) + reg Ng550 = 1'h0; + (* init = 1'h0 *) + reg Ng5503 = 1'h0; + (* init = 1'h0 *) + reg Ng5507 = 1'h0; + (* init = 1'h0 *) + reg Ng5511 = 1'h0; + (* init = 1'h0 *) + reg Ng5517 = 1'h0; + (* init = 1'h0 *) + reg Ng5523 = 1'h0; + (* init = 1'h0 *) + reg Ng5527 = 1'h0; + (* init = 1'h0 *) + reg Ng5535 = 1'h0; + (* init = 1'h0 *) + reg Ng554 = 1'h0; + (* init = 1'h0 *) + reg Ng5543 = 1'h0; + (* init = 1'h0 *) + reg Ng5547 = 1'h0; + (* init = 1'h0 *) + reg Ng5551 = 1'h0; + (* init = 1'h0 *) + reg Ng5555 = 1'h0; + (* init = 1'h0 *) + reg Ng5559 = 1'h0; + (* init = 1'h0 *) + reg Ng5563 = 1'h0; + (* init = 1'h0 *) + reg Ng5567 = 1'h0; + (* init = 1'h0 *) + reg Ng5571 = 1'h0; + (* init = 1'h0 *) + reg Ng5575 = 1'h0; + (* init = 1'h0 *) + reg Ng5579 = 1'h0; + (* init = 1'h0 *) + reg Ng5583 = 1'h0; + (* init = 1'h0 *) + reg Ng5587 = 1'h0; + (* init = 1'h0 *) + reg Ng559 = 1'h0; + (* init = 1'h0 *) + reg Ng5591 = 1'h0; + (* init = 1'h0 *) + reg Ng5595 = 1'h0; + (* init = 1'h0 *) + reg Ng5599 = 1'h0; + (* init = 1'h0 *) + reg Ng5603 = 1'h0; + (* init = 1'h0 *) + reg Ng5607 = 1'h0; + (* init = 1'h0 *) + reg Ng5611 = 1'h0; + (* init = 1'h0 *) + reg Ng5615 = 1'h0; + (* init = 1'h0 *) + reg Ng5619 = 1'h0; + (* init = 1'h0 *) + reg Ng562 = 1'h0; + (* init = 1'h0 *) + reg Ng5644 = 1'h0; + (* init = 1'h0 *) + reg Ng568 = 1'h0; + (* init = 1'h0 *) + reg Ng5685 = 1'h0; + (* init = 1'h0 *) + reg Ng5689 = 1'h0; + (* init = 1'h0 *) + reg Ng5694 = 1'h0; + (* init = 1'h0 *) + reg Ng5698 = 1'h0; + (* init = 1'h0 *) + reg Ng5703 = 1'h0; + (* init = 1'h0 *) + reg Ng572 = 1'h0; + (* init = 1'h0 *) + reg Ng5752 = 1'h0; + (* init = 1'h0 *) + reg Ng577 = 1'h0; + (* init = 1'h0 *) + reg Ng5802 = 1'h0; + (* init = 1'h0 *) + reg Ng5808 = 1'h0; + (* init = 1'h0 *) + reg Ng5813 = 1'h0; + (* init = 1'h0 *) + reg Ng5817 = 1'h0; + (* init = 1'h0 *) + reg Ng582 = 1'h0; + (* init = 1'h0 *) + reg Ng5821 = 1'h0; + (* init = 1'h0 *) + reg Ng5827 = 1'h0; + (* init = 1'h0 *) + reg Ng5831 = 1'h0; + (* init = 1'h0 *) + reg Ng5835 = 1'h0; + (* init = 1'h0 *) + reg Ng5841 = 1'h0; + (* init = 1'h0 *) + reg Ng5845 = 1'h0; + (* init = 1'h0 *) + reg Ng5849 = 1'h0; + (* init = 1'h0 *) + reg Ng5853 = 1'h0; + (* init = 1'h0 *) + reg Ng5857 = 1'h0; + (* init = 1'h0 *) + reg Ng586 = 1'h0; + (* init = 1'h0 *) + reg Ng5863 = 1'h0; + (* init = 1'h0 *) + reg Ng5869 = 1'h0; + (* init = 1'h0 *) + reg Ng5873 = 1'h0; + (* init = 1'h0 *) + reg Ng5881 = 1'h0; + (* init = 1'h0 *) + reg Ng5889 = 1'h0; + (* init = 1'h0 *) + reg Ng5893 = 1'h0; + (* init = 1'h0 *) + reg Ng5897 = 1'h0; + (* init = 1'h0 *) + reg Ng590 = 1'h0; + (* init = 1'h0 *) + reg Ng5901 = 1'h0; + (* init = 1'h0 *) + reg Ng5905 = 1'h0; + (* init = 1'h0 *) + reg Ng5909 = 1'h0; + (* init = 1'h0 *) + reg Ng5913 = 1'h0; + (* init = 1'h0 *) + reg Ng5917 = 1'h0; + (* init = 1'h0 *) + reg Ng5921 = 1'h0; + (* init = 1'h0 *) + reg Ng5925 = 1'h0; + (* init = 1'h0 *) + reg Ng5929 = 1'h0; + (* init = 1'h0 *) + reg Ng5933 = 1'h0; + (* init = 1'h0 *) + reg Ng5937 = 1'h0; + (* init = 1'h0 *) + reg Ng5941 = 1'h0; + (* init = 1'h0 *) + reg Ng5945 = 1'h0; + (* init = 1'h0 *) + reg Ng5949 = 1'h0; + (* init = 1'h0 *) + reg Ng595 = 1'h0; + (* init = 1'h0 *) + reg Ng5953 = 1'h0; + (* init = 1'h0 *) + reg Ng5957 = 1'h0; + (* init = 1'h0 *) + reg Ng5961 = 1'h0; + (* init = 1'h0 *) + reg Ng5965 = 1'h0; + (* init = 1'h0 *) + reg Ng599 = 1'h0; + (* init = 1'h0 *) + reg Ng5990 = 1'h0; + (* init = 1'h0 *) + reg Ng6031 = 1'h0; + (* init = 1'h0 *) + reg Ng6035 = 1'h0; + (* init = 1'h0 *) + reg Ng604 = 1'h0; + (* init = 1'h0 *) + reg Ng6040 = 1'h0; + (* init = 1'h0 *) + reg Ng6044 = 1'h0; + (* init = 1'h0 *) + reg Ng6049 = 1'h0; + (* init = 1'h0 *) + reg Ng608 = 1'h0; + (* init = 1'h0 *) + reg Ng6098 = 1'h0; + (* init = 1'h0 *) + reg Ng613 = 1'h0; + (* init = 1'h0 *) + reg Ng6148 = 1'h0; + (* init = 1'h0 *) + reg Ng6154 = 1'h0; + (* init = 1'h0 *) + reg Ng6159 = 1'h0; + (* init = 1'h0 *) + reg Ng6163 = 1'h0; + (* init = 1'h0 *) + reg Ng6167 = 1'h0; + (* init = 1'h0 *) + reg Ng617 = 1'h0; + (* init = 1'h0 *) + reg Ng6173 = 1'h0; + (* init = 1'h0 *) + reg Ng6177 = 1'h0; + (* init = 1'h0 *) + reg Ng6181 = 1'h0; + (* init = 1'h0 *) + reg Ng6187 = 1'h0; + (* init = 1'h0 *) + reg Ng6191 = 1'h0; + (* init = 1'h0 *) + reg Ng6195 = 1'h0; + (* init = 1'h0 *) + reg Ng6199 = 1'h0; + (* init = 1'h0 *) + reg Ng6203 = 1'h0; + (* init = 1'h0 *) + reg Ng6209 = 1'h0; + (* init = 1'h0 *) + reg Ng6215 = 1'h0; + (* init = 1'h0 *) + reg Ng6219 = 1'h0; + (* init = 1'h0 *) + reg Ng622 = 1'h0; + (* init = 1'h0 *) + reg Ng6227 = 1'h0; + (* init = 1'h0 *) + reg Ng6235 = 1'h0; + (* init = 1'h0 *) + reg Ng6239 = 1'h0; + (* init = 1'h0 *) + reg Ng6243 = 1'h0; + (* init = 1'h0 *) + reg Ng6247 = 1'h0; + (* init = 1'h0 *) + reg Ng6251 = 1'h0; + (* init = 1'h0 *) + reg Ng6255 = 1'h0; + (* init = 1'h0 *) + reg Ng6259 = 1'h0; + (* init = 1'h0 *) + reg Ng626 = 1'h0; + (* init = 1'h0 *) + reg Ng6263 = 1'h0; + (* init = 1'h0 *) + reg Ng6267 = 1'h0; + (* init = 1'h0 *) + reg Ng6271 = 1'h0; + (* init = 1'h0 *) + reg Ng6275 = 1'h0; + (* init = 1'h0 *) + reg Ng6279 = 1'h0; + (* init = 1'h0 *) + reg Ng6283 = 1'h0; + (* init = 1'h0 *) + reg Ng6287 = 1'h0; + (* init = 1'h0 *) + reg Ng6291 = 1'h0; + (* init = 1'h0 *) + reg Ng6295 = 1'h0; + (* init = 1'h0 *) + reg Ng6299 = 1'h0; + (* init = 1'h0 *) + reg Ng63 = 1'h0; + (* init = 1'h0 *) + reg Ng6303 = 1'h0; + (* init = 1'h0 *) + reg Ng6307 = 1'h0; + (* init = 1'h0 *) + reg Ng6311 = 1'h0; + (* init = 1'h0 *) + reg Ng632 = 1'h0; + (* init = 1'h0 *) + reg Ng6336 = 1'h0; + (* init = 1'h0 *) + reg Ng6377 = 1'h0; + (* init = 1'h0 *) + reg Ng6381 = 1'h0; + (* init = 1'h0 *) + reg Ng6386 = 1'h0; + (* init = 1'h0 *) + reg Ng6390 = 1'h0; + (* init = 1'h0 *) + reg Ng6395 = 1'h0; + (* init = 1'h0 *) + reg Ng6444 = 1'h0; + (* init = 1'h0 *) + reg Ng645 = 1'h0; + (* init = 1'h0 *) + reg Ng6494 = 1'h0; + (* init = 1'h0 *) + reg Ng65 = 1'h0; + (* init = 1'h0 *) + reg Ng650 = 1'h0; + (* init = 1'h0 *) + reg Ng6500 = 1'h0; + (* init = 1'h0 *) + reg Ng6505 = 1'h0; + (* init = 1'h0 *) + reg Ng6509 = 1'h0; + (* init = 1'h0 *) + reg Ng6513 = 1'h0; + (* init = 1'h0 *) + reg Ng6519 = 1'h0; + (* init = 1'h0 *) + reg Ng6523 = 1'h0; + (* init = 1'h0 *) + reg Ng6527 = 1'h0; + (* init = 1'h0 *) + reg Ng6533 = 1'h0; + (* init = 1'h0 *) + reg Ng6537 = 1'h0; + (* init = 1'h0 *) + reg Ng6541 = 1'h0; + (* init = 1'h0 *) + reg Ng6545 = 1'h0; + (* init = 1'h0 *) + reg Ng6549 = 1'h0; + (* init = 1'h0 *) + reg Ng655 = 1'h0; + (* init = 1'h0 *) + reg Ng6555 = 1'h0; + (* init = 1'h0 *) + reg Ng6561 = 1'h0; + (* init = 1'h0 *) + reg Ng6565 = 1'h0; + (* init = 1'h0 *) + reg Ng6573 = 1'h0; + (* init = 1'h0 *) + reg Ng6581 = 1'h0; + (* init = 1'h0 *) + reg Ng6585 = 1'h0; + (* init = 1'h0 *) + reg Ng6589 = 1'h0; + (* init = 1'h0 *) + reg Ng6593 = 1'h0; + (* init = 1'h0 *) + reg Ng6597 = 1'h0; + (* init = 1'h0 *) + reg Ng6601 = 1'h0; + (* init = 1'h0 *) + reg Ng6605 = 1'h0; + (* init = 1'h0 *) + reg Ng6609 = 1'h0; + (* init = 1'h0 *) + reg Ng661 = 1'h0; + (* init = 1'h0 *) + reg Ng6613 = 1'h0; + (* init = 1'h0 *) + reg Ng6617 = 1'h0; + (* init = 1'h0 *) + reg Ng6621 = 1'h0; + (* init = 1'h0 *) + reg Ng6625 = 1'h0; + (* init = 1'h0 *) + reg Ng6629 = 1'h0; + (* init = 1'h0 *) + reg Ng6633 = 1'h0; + (* init = 1'h0 *) + reg Ng6637 = 1'h0; + (* init = 1'h0 *) + reg Ng6641 = 1'h0; + (* init = 1'h0 *) + reg Ng6645 = 1'h0; + (* init = 1'h0 *) + reg Ng6649 = 1'h0; + (* init = 1'h0 *) + reg Ng6653 = 1'h0; + (* init = 1'h0 *) + reg Ng6657 = 1'h0; + (* init = 1'h0 *) + reg Ng667 = 1'h0; + (* init = 1'h0 *) + reg Ng6682 = 1'h0; + (* init = 1'h0 *) + reg Ng671 = 1'h0; + (* init = 1'h0 *) + reg Ng6723 = 1'h0; + (* init = 1'h0 *) + reg Ng6727 = 1'h0; + (* init = 1'h0 *) + reg Ng6732 = 1'h0; + (* init = 1'h0 *) + reg Ng6736 = 1'h0; + (* init = 1'h0 *) + reg Ng6741 = 1'h0; + (* init = 1'h0 *) + reg Ng676 = 1'h0; + (* init = 1'h0 *) + reg Ng681 = 1'h0; + (* init = 1'h0 *) + reg Ng686 = 1'h0; + (* init = 1'h0 *) + reg Ng691 = 1'h0; + (* init = 1'h0 *) + reg Ng6972 = 1'h0; + (* init = 1'h0 *) + reg Ng6974 = 1'h0; + (* init = 1'h0 *) + reg Ng699 = 1'h0; + (* init = 1'h0 *) + reg Ng703 = 1'h0; + (* init = 1'h0 *) + reg Ng71 = 1'h0; + (* init = 1'h0 *) + reg Ng714 = 1'h0; + (* init = 1'h0 *) + reg Ng718 = 1'h0; + (* init = 1'h0 *) + reg Ng723 = 1'h0; + (* init = 1'h0 *) + reg Ng728 = 1'h0; + (* init = 1'h0 *) + reg Ng732 = 1'h0; + (* init = 1'h0 *) + reg Ng736 = 1'h0; + (* init = 1'h0 *) + reg Ng739 = 1'h0; + (* init = 1'h0 *) + reg Ng744 = 1'h0; + (* init = 1'h0 *) + reg Ng749 = 1'h0; + (* init = 1'h0 *) + reg Ng753 = 1'h0; + (* init = 1'h0 *) + reg Ng758 = 1'h0; + (* init = 1'h0 *) + reg Ng763 = 1'h0; + (* init = 1'h0 *) + reg Ng767 = 1'h0; + (* init = 1'h0 *) + reg Ng772 = 1'h0; + (* init = 1'h0 *) + reg Ng776 = 1'h0; + (* init = 1'h0 *) + reg Ng781 = 1'h0; + (* init = 1'h0 *) + reg Ng785 = 1'h0; + (* init = 1'h0 *) + reg Ng790 = 1'h0; + (* init = 1'h0 *) + reg Ng794 = 1'h0; + (* init = 1'h0 *) + reg Ng8 = 1'h0; + (* init = 1'h0 *) + reg Ng807 = 1'h0; + (* init = 1'h0 *) + reg Ng812 = 1'h0; + (* init = 1'h0 *) + reg Ng817 = 1'h0; + (* init = 1'h0 *) + reg Ng822 = 1'h0; + (* init = 1'h0 *) + reg Ng827 = 1'h0; + (* init = 1'h0 *) + reg Ng832 = 1'h0; + (* init = 1'h0 *) + reg Ng837 = 1'h0; + (* init = 1'h0 *) + reg Ng843 = 1'h0; + (* init = 1'h0 *) + reg Ng847 = 1'h0; + (* init = 1'h0 *) + reg Ng85 = 1'h0; + (* init = 1'h0 *) + reg Ng854 = 1'h0; + (* init = 1'h0 *) + reg Ng862 = 1'h0; + (* init = 1'h0 *) + reg Ng872 = 1'h0; + (* init = 1'h0 *) + reg Ng890 = 1'h0; + (* init = 1'h0 *) + reg Ng896 = 1'h0; + (* init = 1'h0 *) + reg Ng904 = 1'h0; + (* init = 1'h0 *) + reg Ng907 = 1'h0; + (* init = 1'h0 *) + reg Ng911 = 1'h0; + (* init = 1'h0 *) + reg Ng914 = 1'h0; + (* init = 1'h0 *) + reg Ng918 = 1'h0; + (* init = 1'h0 *) + reg Ng921 = 1'h0; + (* init = 1'h0 *) + reg Ng925 = 1'h0; + (* init = 1'h0 *) + reg Ng93 = 1'h0; + (* init = 1'h0 *) + reg Ng930 = 1'h0; + (* init = 1'h0 *) + reg Ng933 = 1'h0; + (* init = 1'h0 *) + reg Ng936 = 1'h0; + (* init = 1'h0 *) + reg Ng939 = 1'h0; + (* init = 1'h0 *) + reg Ng943 = 1'h0; + (* init = 1'h0 *) + reg Ng947 = 1'h0; + (* init = 1'h0 *) + reg Ng952 = 1'h0; + (* init = 1'h0 *) + reg Ng956 = 1'h0; + (* init = 1'h0 *) + reg Ng962 = 1'h0; + (* init = 1'h0 *) + reg Ng969 = 1'h0; + (* init = 1'h0 *) + reg Ng976 = 1'h0; + (* init = 1'h0 *) + reg Ng979 = 1'h0; + (* init = 1'h0 *) + reg Ng990 = 1'h0; + (* init = 1'h0 *) + reg Ng996 = 1'h0; + input Pg100; + (* init = 1'h0 *) + output Pg10122; + reg Pg10122 = 1'h0; + (* init = 1'h0 *) + output Pg10306; + reg Pg10306 = 1'h0; + (* init = 1'h0 *) + output Pg10500; + reg Pg10500 = 1'h0; + (* init = 1'h0 *) + output Pg10527; + reg Pg10527 = 1'h0; + input Pg113; + (* init = 1'h0 *) + output Pg11349; + reg Pg11349 = 1'h0; + (* init = 1'h0 *) + output Pg11388; + reg Pg11388 = 1'h0; + input Pg114; + (* init = 1'h0 *) + output Pg11418; + reg Pg11418 = 1'h0; + (* init = 1'h0 *) + output Pg11447; + reg Pg11447 = 1'h0; + input Pg115; + input Pg116; + (* init = 1'h0 *) + output Pg11678; + reg Pg11678 = 1'h0; + (* init = 1'h0 *) + output Pg11770; + reg Pg11770 = 1'h0; + input Pg120; + (* init = 1'h0 *) + output Pg12184; + reg Pg12184 = 1'h0; + (* init = 1'h0 *) + output Pg12238; + reg Pg12238 = 1'h0; + (* init = 1'h0 *) + output Pg12300; + reg Pg12300 = 1'h0; + (* init = 1'h0 *) + output Pg12350; + reg Pg12350 = 1'h0; + (* init = 1'h0 *) + output Pg12368; + reg Pg12368 = 1'h0; + input Pg124; + (* init = 1'h0 *) + output Pg12422; + reg Pg12422 = 1'h0; + (* init = 1'h0 *) + output Pg12470; + reg Pg12470 = 1'h0; + input Pg125; + input Pg126; + input Pg127; + (* init = 1'h0 *) + output Pg12832; + reg Pg12832 = 1'h0; + output Pg12833; + (* init = 1'h0 *) + output Pg12919; + reg Pg12919 = 1'h0; + (* init = 1'h0 *) + output Pg12923; + reg Pg12923 = 1'h0; + (* init = 1'h0 *) + output Pg13039; + reg Pg13039 = 1'h0; + (* init = 1'h0 *) + output Pg13049; + reg Pg13049 = 1'h0; + (* init = 1'h0 *) + output Pg13068; + reg Pg13068 = 1'h0; + (* init = 1'h0 *) + output Pg13085; + reg Pg13085 = 1'h0; + (* init = 1'h0 *) + output Pg13099; + reg Pg13099 = 1'h0; + (* init = 1'h0 *) + output Pg13259; + reg Pg13259 = 1'h0; + (* init = 1'h0 *) + output Pg13272; + reg Pg13272 = 1'h0; + input Pg134; + input Pg135; + (* init = 1'h0 *) + output Pg13865; + reg Pg13865 = 1'h0; + (* init = 1'h0 *) + output Pg13881; + reg Pg13881 = 1'h0; + (* init = 1'h0 *) + output Pg13895; + reg Pg13895 = 1'h0; + (* init = 1'h0 *) + output Pg13906; + reg Pg13906 = 1'h0; + (* init = 1'h0 *) + output Pg13926; + reg Pg13926 = 1'h0; + (* init = 1'h0 *) + output Pg13966; + reg Pg13966 = 1'h0; + (* init = 1'h0 *) + output Pg14096; + reg Pg14096 = 1'h0; + (* init = 1'h0 *) + output Pg14125; + reg Pg14125 = 1'h0; + (* init = 1'h0 *) + output Pg14147; + reg Pg14147 = 1'h0; + (* init = 1'h0 *) + output Pg14167; + reg Pg14167 = 1'h0; + (* init = 1'h0 *) + output Pg14189; + reg Pg14189 = 1'h0; + (* init = 1'h0 *) + output Pg14201; + reg Pg14201 = 1'h0; + (* init = 1'h0 *) + output Pg14217; + reg Pg14217 = 1'h0; + (* init = 1'h0 *) + output Pg14421; + reg Pg14421 = 1'h0; + (* init = 1'h0 *) + output Pg14451; + reg Pg14451 = 1'h0; + (* init = 1'h0 *) + output Pg14518; + reg Pg14518 = 1'h0; + (* init = 1'h0 *) + output Pg14597; + reg Pg14597 = 1'h0; + (* init = 1'h0 *) + output Pg14635; + reg Pg14635 = 1'h0; + (* init = 1'h0 *) + output Pg14662; + reg Pg14662 = 1'h0; + (* init = 1'h0 *) + output Pg14673; + reg Pg14673 = 1'h0; + (* init = 1'h0 *) + output Pg14694; + reg Pg14694 = 1'h0; + (* init = 1'h0 *) + output Pg14705; + reg Pg14705 = 1'h0; + (* init = 1'h0 *) + output Pg14738; + reg Pg14738 = 1'h0; + (* init = 1'h0 *) + output Pg14749; + reg Pg14749 = 1'h0; + (* init = 1'h0 *) + output Pg14779; + reg Pg14779 = 1'h0; + (* init = 1'h0 *) + output Pg14828; + reg Pg14828 = 1'h0; + (* init = 1'h0 *) + output Pg16603; + reg Pg16603 = 1'h0; + (* init = 1'h0 *) + output Pg16624; + reg Pg16624 = 1'h0; + (* init = 1'h0 *) + output Pg16627; + reg Pg16627 = 1'h0; + (* init = 1'h0 *) + output Pg16656; + reg Pg16656 = 1'h0; + (* init = 1'h0 *) + output Pg16659; + reg Pg16659 = 1'h0; + (* init = 1'h0 *) + output Pg16686; + reg Pg16686 = 1'h0; + (* init = 1'h0 *) + output Pg16693; + reg Pg16693 = 1'h0; + (* init = 1'h0 *) + output Pg16718; + reg Pg16718 = 1'h0; + (* init = 1'h0 *) + output Pg16722; + reg Pg16722 = 1'h0; + (* init = 1'h0 *) + output Pg16744; + reg Pg16744 = 1'h0; + (* init = 1'h0 *) + output Pg16748; + reg Pg16748 = 1'h0; + (* init = 1'h0 *) + output Pg16775; + reg Pg16775 = 1'h0; + (* init = 1'h0 *) + output Pg16874; + reg Pg16874 = 1'h0; + (* init = 1'h0 *) + output Pg16924; + reg Pg16924 = 1'h0; + (* init = 1'h0 *) + output Pg16955; + reg Pg16955 = 1'h0; + (* init = 1'h0 *) + output Pg17291; + reg Pg17291 = 1'h0; + (* init = 1'h0 *) + output Pg17316; + reg Pg17316 = 1'h0; + (* init = 1'h0 *) + output Pg17320; + reg Pg17320 = 1'h0; + (* init = 1'h0 *) + output Pg17400; + reg Pg17400 = 1'h0; + (* init = 1'h0 *) + output Pg17404; + reg Pg17404 = 1'h0; + (* init = 1'h0 *) + output Pg17423; + reg Pg17423 = 1'h0; + (* init = 1'h0 *) + output Pg17519; + reg Pg17519 = 1'h0; + (* init = 1'h0 *) + output Pg17577; + reg Pg17577 = 1'h0; + (* init = 1'h0 *) + output Pg17580; + reg Pg17580 = 1'h0; + (* init = 1'h0 *) + output Pg17604; + reg Pg17604 = 1'h0; + (* init = 1'h0 *) + output Pg17607; + reg Pg17607 = 1'h0; + (* init = 1'h0 *) + output Pg17639; + reg Pg17639 = 1'h0; + (* init = 1'h0 *) + output Pg17646; + reg Pg17646 = 1'h0; + (* init = 1'h0 *) + output Pg17649; + reg Pg17649 = 1'h0; + (* init = 1'h0 *) + output Pg17674; + reg Pg17674 = 1'h0; + (* init = 1'h0 *) + output Pg17678; + reg Pg17678 = 1'h0; + (* init = 1'h0 *) + output Pg17685; + reg Pg17685 = 1'h0; + (* init = 1'h0 *) + output Pg17688; + reg Pg17688 = 1'h0; + (* init = 1'h0 *) + output Pg17711; + reg Pg17711 = 1'h0; + (* init = 1'h0 *) + output Pg17715; + reg Pg17715 = 1'h0; + (* init = 1'h0 *) + output Pg17722; + reg Pg17722 = 1'h0; + (* init = 1'h0 *) + output Pg17739; + reg Pg17739 = 1'h0; + (* init = 1'h0 *) + output Pg17743; + reg Pg17743 = 1'h0; + (* init = 1'h0 *) + output Pg17760; + reg Pg17760 = 1'h0; + (* init = 1'h0 *) + output Pg17764; + reg Pg17764 = 1'h0; + (* init = 1'h0 *) + output Pg17778; + reg Pg17778 = 1'h0; + (* init = 1'h0 *) + output Pg17787; + reg Pg17787 = 1'h0; + (* init = 1'h0 *) + output Pg17813; + reg Pg17813 = 1'h0; + (* init = 1'h0 *) + output Pg17819; + reg Pg17819 = 1'h0; + (* init = 1'h0 *) + output Pg17845; + reg Pg17845 = 1'h0; + (* init = 1'h0 *) + output Pg17871; + reg Pg17871 = 1'h0; + output Pg18092; + output Pg18094; + output Pg18095; + output Pg18096; + output Pg18097; + output Pg18098; + output Pg18099; + output Pg18100; + output Pg18101; + (* init = 1'h0 *) + output Pg18881; + reg Pg18881 = 1'h0; + (* init = 1'h0 *) + output Pg19334; + reg Pg19334 = 1'h0; + (* init = 1'h0 *) + output Pg19357; + reg Pg19357 = 1'h0; + (* init = 1'h0 *) + output Pg20049; + reg Pg20049 = 1'h0; + (* init = 1'h0 *) + output Pg20557; + reg Pg20557 = 1'h0; + (* init = 1'h0 *) + output Pg20652; + reg Pg20652 = 1'h0; + (* init = 1'h0 *) + output Pg20654; + reg Pg20654 = 1'h0; + (* init = 1'h0 *) + output Pg20763; + reg Pg20763 = 1'h0; + (* init = 1'h0 *) + output Pg20899; + reg Pg20899 = 1'h0; + (* init = 1'h0 *) + output Pg20901; + reg Pg20901 = 1'h0; + (* init = 1'h0 *) + output Pg21176; + reg Pg21176 = 1'h0; + (* init = 1'h0 *) + output Pg21245; + reg Pg21245 = 1'h0; + (* init = 1'h0 *) + output Pg21270; + reg Pg21270 = 1'h0; + (* init = 1'h0 *) + output Pg21292; + reg Pg21292 = 1'h0; + output Pg21698; + output Pg21727; + output Pg23002; + output Pg23190; + output Pg23612; + output Pg23652; + (* init = 1'h0 *) + output Pg23683; + reg Pg23683 = 1'h0; + output Pg23759; + output Pg24151; + output Pg24161; + output Pg24162; + output Pg24163; + output Pg24164; + output Pg24165; + output Pg24166; + output Pg24167; + output Pg24168; + output Pg24169; + output Pg24170; + output Pg24171; + output Pg24172; + output Pg24173; + output Pg24174; + output Pg24175; + output Pg24176; + output Pg24177; + output Pg24178; + output Pg24179; + output Pg24180; + output Pg24181; + output Pg24182; + output Pg24183; + output Pg24184; + output Pg24185; + output Pg25114; + output Pg25167; + (* init = 1'h0 *) + output Pg25219; + reg Pg25219 = 1'h0; + output Pg25259; + output Pg25582; + output Pg25583; + output Pg25584; + output Pg25585; + output Pg25586; + output Pg25587; + output Pg25588; + output Pg25589; + output Pg25590; + output Pg26801; + output Pg26875; + output Pg26876; + output Pg26877; + output Pg27831; + output Pg28030; + output Pg28041; + output Pg28042; + output Pg28753; + output Pg29210; + output Pg29211; + output Pg29212; + output Pg29213; + output Pg29214; + output Pg29215; + output Pg29216; + output Pg29217; + output Pg29218; + output Pg29219; + output Pg29220; + output Pg29221; + output Pg30327; + output Pg30329; + output Pg30330; + output Pg30331; + output Pg30332; + output Pg31521; + output Pg31656; + output Pg31665; + output Pg31793; + output Pg31860; + output Pg31861; + output Pg31862; + output Pg31863; + output Pg32185; + output Pg32429; + output Pg32454; + output Pg32975; + output Pg33079; + output Pg33435; + output Pg33533; + output Pg33636; + output Pg33659; + output Pg33874; + output Pg33894; + output Pg33935; + output Pg33945; + output Pg33946; + output Pg33947; + output Pg33948; + output Pg33949; + output Pg33950; + output Pg33959; + output Pg34201; + output Pg34221; + output Pg34232; + output Pg34233; + output Pg34234; + output Pg34235; + output Pg34236; + output Pg34237; + output Pg34238; + output Pg34239; + output Pg34240; + output Pg34383; + output Pg34425; + output Pg34435; + output Pg34436; + output Pg34437; + output Pg34597; + output Pg34788; + output Pg34839; + output Pg34913; + output Pg34915; + output Pg34917; + output Pg34919; + output Pg34921; + output Pg34923; + output Pg34925; + output Pg34927; + output Pg34956; + output Pg34972; + input Pg35; + input Pg36; + input Pg44; + input Pg5; + input Pg53; + input Pg54; + input Pg56; + input Pg57; + input Pg64; + input Pg6744; + input Pg6745; + input Pg6746; + input Pg6747; + input Pg6748; + input Pg6749; + input Pg6750; + input Pg6751; +// input Pg6752; + input Pg6753; + input Pg72; + (* init = 1'h0 *) + output Pg7243; + reg Pg7243 = 1'h0; + (* init = 1'h0 *) + output Pg7245; + reg Pg7245 = 1'h0; + (* init = 1'h0 *) + output Pg7257; + reg Pg7257 = 1'h0; + (* init = 1'h0 *) + output Pg7260; + reg Pg7260 = 1'h0; + input Pg73; + (* init = 1'h0 *) + output Pg7540; + reg Pg7540 = 1'h0; + (* init = 1'h0 *) + output Pg7916; + reg Pg7916 = 1'h0; + (* init = 1'h0 *) + output Pg7946; + reg Pg7946 = 1'h0; + (* init = 1'h0 *) + output Pg8132; + reg Pg8132 = 1'h0; + output Pg8178; + (* init = 1'h0 *) + output Pg8215; + reg Pg8215 = 1'h0; + (* init = 1'h0 *) + output Pg8235; + reg Pg8235 = 1'h0; + (* init = 1'h0 *) + output Pg8277; + reg Pg8277 = 1'h0; + (* init = 1'h0 *) + output Pg8279; + reg Pg8279 = 1'h0; + output Pg8283; + (* init = 1'h0 *) + output Pg8291; + reg Pg8291 = 1'h0; + (* init = 1'h0 *) + output Pg8342; + reg Pg8342 = 1'h0; + (* init = 1'h0 *) + output Pg8344; + reg Pg8344 = 1'h0; + (* init = 1'h0 *) + output Pg8353; + reg Pg8353 = 1'h0; + (* init = 1'h0 *) + output Pg8358; + reg Pg8358 = 1'h0; + (* init = 1'h0 *) + output Pg8398; + reg Pg8398 = 1'h0; + input Pg84; + output Pg8403; + (* init = 1'h0 *) + output Pg8416; + reg Pg8416 = 1'h0; + (* init = 1'h0 *) + output Pg8475; + reg Pg8475 = 1'h0; + (* init = 1'h0 *) + output Pg8719; + reg Pg8719 = 1'h0; + (* init = 1'h0 *) + output Pg8783; + reg Pg8783 = 1'h0; + (* init = 1'h0 *) + output Pg8784; + reg Pg8784 = 1'h0; + (* init = 1'h0 *) + output Pg8785; + reg Pg8785 = 1'h0; + (* init = 1'h0 *) + output Pg8786; + reg Pg8786 = 1'h0; + (* init = 1'h0 *) + output Pg8787; + reg Pg8787 = 1'h0; + (* init = 1'h0 *) + output Pg8788; + reg Pg8788 = 1'h0; + (* init = 1'h0 *) + output Pg8789; + reg Pg8789 = 1'h0; + (* init = 1'h0 *) + output Pg8839; + reg Pg8839 = 1'h0; + (* init = 1'h0 *) + output Pg8870; + reg Pg8870 = 1'h0; + (* init = 1'h0 *) + output Pg8915; + reg Pg8915 = 1'h0; + (* init = 1'h0 *) + output Pg8916; + reg Pg8916 = 1'h0; + (* init = 1'h0 *) + output Pg8917; + reg Pg8917 = 1'h0; + (* init = 1'h0 *) + output Pg8918; + reg Pg8918 = 1'h0; + (* init = 1'h0 *) + output Pg8919; + reg Pg8919 = 1'h0; + (* init = 1'h0 *) + output Pg8920; + reg Pg8920 = 1'h0; + input Pg90; + (* init = 1'h0 *) + output Pg9019; + reg Pg9019 = 1'h0; + (* init = 1'h0 *) + output Pg9048; + reg Pg9048 = 1'h0; + input Pg91; + input Pg92; + (* init = 1'h0 *) + output Pg9251; + reg Pg9251 = 1'h0; + (* init = 1'h0 *) + output Pg9497; + reg Pg9497 = 1'h0; + (* init = 1'h0 *) + output Pg9553; + reg Pg9553 = 1'h0; + (* init = 1'h0 *) + output Pg9555; + reg Pg9555 = 1'h0; + (* init = 1'h0 *) + output Pg9615; + reg Pg9615 = 1'h0; + (* init = 1'h0 *) + output Pg9617; + reg Pg9617 = 1'h0; + (* init = 1'h0 *) + output Pg9680; + reg Pg9680 = 1'h0; + (* init = 1'h0 *) + output Pg9682; + reg Pg9682 = 1'h0; + (* init = 1'h0 *) + output Pg9741; + reg Pg9741 = 1'h0; + (* init = 1'h0 *) + output Pg9743; + reg Pg9743 = 1'h0; + (* init = 1'h0 *) + output Pg9817; + reg Pg9817 = 1'h0; + input Pg99; + input clock; + wire n1002; + wire n1006; + wire n1010; + wire n1014; + wire n1018; + wire n1022; + wire n1026; + wire n1030; + wire n1034; + wire n1038; + wire n1042; + wire n1046; + wire n1050; + wire n1054; + wire n1057; + wire n1061; + wire n1064; + wire n1067; + wire n1070; + wire n1073; + wire n1076; + wire n1079; + wire n1082_1; + wire n1086; + wire n1089; + wire n1092; + wire n1095; + wire n1098; + wire n1101; + wire n1104; + wire n1107; + wire n1111; + wire n1114; + wire n1117_1; + wire n1121; + wire n1125; + wire n1129; + wire n1133; + wire n1137; + wire n1141; + wire n1145; + wire n1149; + wire n1153; + wire n1157; + wire n1161; + wire n1165; + wire n1169; + wire n1173; + wire n1177; + wire n1181_1; + wire n1186_1; + wire n1191; + wire n1196; + wire n1201; + wire n1206; + wire n1210; + wire n1215; + wire n1220; + wire n1225; + wire n1230; + wire n1235; + wire n1240; + wire n1245; + wire n1250; + wire n1255; + wire n1260; + wire n1265; + wire n1270; + wire n1274; + wire n1279; + wire n1284; + wire n1289; + wire n1294; + wire n1299; + wire n1304; + wire n1309; + wire n1313; + wire n1318; + wire n1323; + wire n1328; + wire n1333; + wire n1338; + wire n1343; + wire n1348; + wire n1353; + wire n1358; + wire n1363; + wire n1368; + wire n1373; + wire n1378; + wire n1383; + wire n1388; + wire n1393; + wire n1397; + wire n1402; + wire n1407; + wire n1412; + wire n1417; + wire n1422; + wire n1427; + wire n1432; + wire n1437; + wire n1442; + wire n1447_1; + wire n1452; + wire n1457_1; + wire n1462; + wire n1467_1; + wire n1472; + wire n1477_1; + wire n1482; + wire n1487; + wire n1492; + wire n1497; + wire n1502; + wire n1507; + wire n1512; + wire n1517_1; + wire n1522; + wire n1527_1; + wire n1532; + wire n1537; + wire n1542; + wire n1547; + wire n1552; + wire n1557; + wire n1562; + wire n1567_1; + wire n1572; + wire n1577; + wire n1582; + wire n1587; + wire n1592; + wire n1597; + wire n1602; + wire n1607; + wire n1612; + wire n1617; + wire n1622; + wire n1627; + wire n1632; + wire n1637; + wire n1642; + wire n1647; + wire n1652; + wire n1657; + wire n1662; + wire n1667; + wire n1672; + wire n1677; + wire n1682; + wire n1687; + wire n1691; + wire n1696; + wire n1701; + wire n1706; + wire n1711; + wire n1716; + wire n1721; + wire n1725; + wire n1730; + wire n1735; + wire n1740; + wire n1745; + wire n1750; + wire n1755; + wire n1759; + wire n1764; + wire n1769; + wire n1774; + wire n1779; + wire n1784; + wire n1789; + wire n1794; + wire n1799; + wire n1804; + wire n1809; + wire n1814; + wire n1819; + wire n1824; + wire n1829; + wire n1834; + wire n1839; + wire n1844; + wire n1849; + wire n1853; + wire n1858; + wire n1863; + wire n1868_1; + wire n1872; + wire n1877; + wire n1882; + wire n1887; + wire n1892; + wire n1897; + wire n1902; + wire n1906; + wire n1911; + wire n1916; + wire n1921; + wire n1926; + wire n1931; + wire n1936; + wire n1941; + wire n1946; + wire n1951; + wire n1956; + wire n1961; + wire n1966; + wire n1971; + wire n1976; + wire n1981; + wire n1986; + wire n1991; + wire n1996; + wire n2001; + wire n2006; + wire n2011; + wire n2016; + wire n2021; + wire n2026; + wire n2031; + wire n2036; + wire n2041; + wire n2046; + wire n2051; + wire n2056; + wire n2061; + wire n2066; + wire n2071; + wire n2076; + wire n2081; + wire n2086; + wire n2091; + wire n2096; + wire n2101; + wire n2106; + wire n2111_1; + wire n2116_1; + wire n2121; + wire n2125; + wire n2130; + wire n2135; + wire n2140; + wire n2145; + wire n2150; + wire n2155; + wire n2160; + wire n2165; + wire n2170; + wire n2175; + wire n2180; + wire n2185; + wire n2190; + wire n2195; + wire n2200; + wire n2205; + wire n2210; + wire n2215; + wire n2220; + wire n2224; + wire n2229; + wire n2234; + wire n2239; + wire n2244; + wire n2249; + wire n2254; + wire n2259; + wire n2264; + wire n2269; + wire n2274; + wire n2279; + wire n2284; + wire n2289; + wire n2294; + wire n2299; + wire n2304; + wire n2309; + wire n2314; + wire n2318; + wire n2323; + wire n2328; + wire n2333; + wire n2338; + wire n2343; + wire n2348; + wire n2353; + wire n2357; + wire n2362; + wire n2367; + wire n2372; + wire n2377; + wire n2381; + wire n2386; + wire n2391; + wire n2396; + wire n2400; + wire n2405; + wire n2410; + wire n2415; + wire n2420; + wire n2425; + wire n2430; + wire n2435; + wire n2440; + wire n2445; + wire n2450; + wire n2455; + wire n2460; + wire n2465; + wire n2470; + wire n2475; + wire n2480; + wire n2484; + wire n2489; + wire n2494; + wire n2499; + wire n2504; + wire n2508; + wire n2513; + wire n2518; + wire n2523; + wire n2528; + wire n2533; + wire n2538; + wire n2543; + wire n2548; + wire n2553; + wire n2558; + wire n2563; + wire n2568; + wire n2573; + wire n2578; + wire n2583; + wire n2588; + wire n2593; + wire n2598; + wire n2603; + wire n2608; + wire n2613; + wire n2618; + wire n2622; + wire n2627; + wire n2632; + wire n2637; + wire n2642; + wire n2647; + wire n2652; + wire n2657; + wire n2662; + wire n2666; + wire n2670; + wire n2675; + wire n2680; + wire n2684; + wire n2689; + wire n2694; + wire n2699; + wire n2704; + wire n2709; + wire n2714; + wire n2719; + wire n2724; + wire n2729; + wire n2734; + wire n2739; + wire n2744; + wire n2749; + wire n2754; + wire n2759; + wire n2764; + wire n2769; + wire n2774; + wire n2779; + wire n2784; + wire n2789; + wire n2794; + wire n2798; + wire n2803; + wire n2808; + wire n2813; + wire n2818; + wire n2823; + wire n2828_1; + wire n2833; + wire n2838; + wire n2843; + wire n2848; + wire n2853; + wire n2858; + wire n2863; + wire n2868; + wire n2873; + wire n2878; + wire n2883; + wire n2888; + wire n2893; + wire n2898; + wire n2903; + wire n2908; + wire n2913; + wire n2918; + wire n2923; + wire n2928; + wire n2933; + wire n2938; + wire n2943; + wire n2948; + wire n2952; + wire n2957; + wire n2962; + wire n2967; + wire n2972; + wire n2977; + wire n2982; + wire n2987; + wire n2992; + wire n2996; + wire n3001; + wire n3006; + wire n3011; + wire n3016; + wire n3021; + wire n3026; + wire n3031; + wire n3036; + wire n3041; + wire n3046; + wire n3051; + wire n3056; + wire n3061; + wire n3066; + wire n3071; + wire n3075_1; + wire n3080; + wire n3085; + wire n3090; + wire n3095; + wire n3100; + wire n3105; + wire n3110; + wire n3114; + wire n3119; + wire n3124; + wire n3129; + wire n3134; + wire n3139; + wire n3144; + wire n3149; + wire n3154; + wire n3159; + wire n3164; + wire n3169; + wire n3174; + wire n3179; + wire n3184; + wire n3188; + wire n3193; + wire n3197; + wire n3202; + wire n3207; + wire n3212; + wire n3217; + wire n3222; + wire n3227; + wire n3232; + wire n3237_1; + wire n3242; + wire n3246; + wire n3251; + wire n3256; + wire n3261; + wire n3266; + wire n3271; + wire n3276; + wire n3281; + wire n3286; + wire n3291; + wire n3296; + wire n3301_1; + wire n3306; + wire n3311_1; + wire n3316; + wire n3321_1; + wire n3326; + wire n3331; + wire n3336_1; + wire n3341; + wire n3346; + wire n3351; + wire n3356; + wire n3361; + wire n3366; + wire n3371; + wire n3376; + wire n3381; + wire n3386; + wire n3391; + wire n3396; + wire n3401; + wire n3406; + wire n3411_1; + wire n3416_1; + wire n3421; + wire n3426; + wire n3431; + wire n3436; + wire n3441; + wire n3446; + wire n3451; + wire n3456; + wire n3461; + wire n3466; + wire n3471; + wire n3476; + wire n3481; + wire n3486; + wire n3491; + wire n3496; + wire n3501; + wire n3506; + wire n3510; + wire n3515_1; + wire n3520; + wire n3525; + wire n3530; + wire n3535; + wire n3540; + wire n3544; + wire n3549; + wire n3553_1; + wire n3557; + wire n3562; + wire n3567; + wire n3572; + wire n3577; + wire n3582; + wire n3587; + wire n3592; + wire n3597; + wire n3602; + wire n3607; + wire n3612; + wire n3617; + wire n3622; + wire n3627; + wire n3632; + wire n3637; + wire n3642; + wire n3647; + wire n3652; + wire n3657; + wire n3662; + wire n3667; + wire n3672; + wire n3677; + wire n3682; + wire n3687; + wire n3692; + wire n3696; + wire n3701; + wire n3706; + wire n3711; + wire n3716; + wire n3721; + wire n3725_1; + wire n3730_1; + wire n3734; + wire n3739; + wire n3744; + wire n3749; + wire n3754; + wire n3759; + wire n3764; + wire n3769; + wire n3774; + wire n3779; + wire n3784; + wire n3789; + wire n3794; + wire n3799; + wire n3803; + wire n3808; + wire n3813; + wire n3818; + wire n3823; + wire n3828; + wire n3833; + wire n3838; + wire n3843; + wire n3847; + wire n3852; + wire n3857; + wire n3862; + wire n3867; + wire n3872; + wire n3877; + wire n3882; + wire n3887; + wire n3892; + wire n3897; + wire n3902; + wire n3907; + wire n3912_1; + wire n3917_1; + wire n3922_1; + wire n3927_1; + wire n3932_1; + wire n3937; + wire n3942; + wire n3947_1; + wire n3952; + wire n3957; + wire n3962_1; + wire n3967; + wire n3972; + wire n3977; + wire n3982; + wire n3987; + wire n3992; + wire n3997; + wire n4002; + wire n4007; + wire n4012; + wire n4017; + wire n4022; + wire n4027; + wire n4032; + wire n4037; + wire n4042; + wire n4047; + wire n4052; + wire n4057_1; + wire n4062_1; + wire n4067; + wire n4072; + wire n4077; + wire n4082; + wire n4087; + wire n4092; + wire n4097; + wire n4102; + wire n4107; + wire n4112; + wire n4117; + wire n4120; + wire n4122; + wire n4124; + wire n4127; + wire n4130; + wire n4131; + wire n4132; + wire n4132_1; + wire n4133; + wire n4135; + wire n4136; + wire n4137; + wire n4137_1; + wire n4138; + wire n4140; + wire n4141; + wire n4142; + wire n4142_1; + wire n4143; + wire n4145; + wire n4147; + wire n4147_1; + wire n4148; + wire n4149; + wire n4150; + wire n4151; + wire n4152; + wire n4152_1; + wire n4154; + wire n4155; + wire n4156; + wire n4157; + wire n4157_1; + wire n4159; + wire n4160; + wire n4161; + wire n4162; + wire n4162_1; + wire n4163; + wire n4164; + wire n4165; + wire n4166; + wire n4167; + wire n4167_1; + wire n4169; + wire n4170; + wire n4171; + wire n4172; + wire n4172_1; + wire n4173; + wire n4174; + wire n4175; + wire n4176; + wire n4177; + wire n4177_1; + wire n4178; + wire n4180; + wire n4181; + wire n4182; + wire n4183; + wire n4184; + wire n4185; + wire n4187; + wire n4187_1; + wire n4190; + wire n4191; + wire n4192; + wire n4192_1; + wire n4193; + wire n4194; + wire n4196; + wire n4197_1; + wire n4198; + wire n4199; + wire n4200; + wire n4202; + wire n4203; + wire n4204; + wire n4205; + wire n4207; + wire n4207_1; + wire n4208; + wire n4209; + wire n4210; + wire n4211; + wire n4212; + wire n4212_1; + wire n4213; + wire n4215; + wire n4216; + wire n4216_1; + wire n4220; + wire n4221; + wire n4221_1; + wire n4222; + wire n4223; + wire n4225; + wire n4226; + wire n4227; + wire n4228; + wire n4229; + wire n4230; + wire n4231; + wire n4231_1; + wire n4233; + wire n4235; + wire n4236; + wire n4236_1; + wire n4238; + wire n4239; + wire n4240; + wire n4241; + wire n4243; + wire n4245; + wire n4245_1; + wire n4246; + wire n4247; + wire n4249; + wire n4250; + wire n4250_1; + wire n4251; + wire n4254; + wire n4255; + wire n4256; + wire n4257; + wire n4258; + wire n4259; + wire n4260; + wire n4260_1; + wire n4262; + wire n4264; + wire n4265; + wire n4267; + wire n4268; + wire n4269; + wire n4270; + wire n4270_1; + wire n4271; + wire n4272; + wire n4273; + wire n4274; + wire n4275; + wire n4275_1; + wire n4276; + wire n4277; + wire n4278; + wire n4279; + wire n4280; + wire n4280_1; + wire n4281; + wire n4282; + wire n4283; + wire n4284; + wire n4284_1; + wire n4285; + wire n4287; + wire n4289; + wire n4289_1; + wire n4290; + wire n4291; + wire n4292; + wire n4293; + wire n4294; + wire n4294_1; + wire n4296; + wire n4297; + wire n4298; + wire n4299; + wire n4299_1; + wire n4300; + wire n4302; + wire n4303; + wire n4304; + wire n4304_1; + wire n4305; + wire n4306; + wire n4307; + wire n4309; + wire n4310; + wire n4312; + wire n4313; + wire n4314; + wire n4314_1; + wire n4317; + wire n4319; + wire n4320; + wire n4321; + wire n4323; + wire n4324; + wire n4325; + wire n4326; + wire n4329; + wire n4330; + wire n4333; + wire n4334; + wire n4334_1; + wire n4337; + wire n4339; + wire n4339_1; + wire n4340; + wire n4341; + wire n4342; + wire n4343; + wire n4343_1; + wire n4344; + wire n4345; + wire n4346; + wire n4347; + wire n4348; + wire n4350; + wire n4351; + wire n4352; + wire n4353; + wire n4354; + wire n4355; + wire n4356; + wire n4357; + wire n4358; + wire n4359; + wire n4361; + wire n4362; + wire n4363; + wire n4367; + wire n4367_1; + wire n4369; + wire n4371; + wire n4372; + wire n4372_1; + wire n4373; + wire n4374; + wire n4377; + wire n4377_1; + wire n4380; + wire n4382; + wire n4382_1; + wire n4383; + wire n4384; + wire n4386; + wire n4386_1; + wire n4387; + wire n4388; + wire n4389; + wire n4390; + wire n4391; + wire n4393; + wire n4395; + wire n4396; + wire n4397; + wire n4398; + wire n4399; + wire n4400; + wire n4401; + wire n4402; + wire n4406; + wire n4406_1; + wire n4407; + wire n4408; + wire n4409; + wire n4410; + wire n4411; + wire n4411_1; + wire n4412; + wire n4413; + wire n4414; + wire n4415; + wire n4416; + wire n4416_1; + wire n4418; + wire n4421; + wire n4421_1; + wire n4426; + wire n4426_1; + wire n4427; + wire n4428; + wire n4429; + wire n4431; + wire n4431_1; + wire n4432; + wire n4434; + wire n4436; + wire n4436_1; + wire n4437; + wire n4438; + wire n4440; + wire n4441; + wire n4442; + wire n4445; + wire n4446; + wire n4449; + wire n4450; + wire n4451; + wire n4453; + wire n4454; + wire n4456; + wire n4456_1; + wire n4457; + wire n4458; + wire n4459; + wire n4460; + wire n4461; + wire n4461_1; + wire n4462; + wire n4463; + wire n4464; + wire n4465; + wire n4466; + wire n4467; + wire n4469; + wire n4471; + wire n4471_1; + wire n4474; + wire n4476; + wire n4476_1; + wire n4479; + wire n4481; + wire n4482; + wire n4483; + wire n4486; + wire n4489; + wire n4490; + wire n4491; + wire n4492; + wire n4493; + wire n4494; + wire n4495; + wire n4496; + wire n4496_1; + wire n4498; + wire n4499; + wire n4501; + wire n4503; + wire n4504; + wire n4505; + wire n4506; + wire n4508; + wire n4509; + wire n4510; + wire n4511; + wire n4511_1; + wire n4513; + wire n4515; + wire n4516; + wire n4517; + wire n4520; + wire n4521; + wire n4522; + wire n4523; + wire n4524; + wire n4526; + wire n4527; + wire n4529; + wire n4531; + wire n4531_1; + wire n4535; + wire n4536; + wire n4537; + wire n4541; + wire n4541_1; + wire n4542; + wire n4543; + wire n4544; + wire n4545; + wire n4546; + wire n4546_1; + wire n4548; + wire n4550; + wire n4551; + wire n4552; + wire n4553; + wire n4554; + wire n4556; + wire n4556_1; + wire n4557; + wire n4558; + wire n4559; + wire n4560; + wire n4561; + wire n4561_1; + wire n4563; + wire n4565; + wire n4566; + wire n4566_1; + wire n4567; + wire n4568; + wire n4570; + wire n4571; + wire n4576; + wire n4576_1; + wire n4577; + wire n4578; + wire n4580; + wire n4581; + wire n4581_1; + wire n4584; + wire n4585; + wire n4586; + wire n4586_1; + wire n4587; + wire n4588; + wire n4590; + wire n4591; + wire n4593; + wire n4594; + wire n4596; + wire n4596_1; + wire n4598; + wire n4600; + wire n4601; + wire n4602; + wire n4604; + wire n4606; + wire n4606_1; + wire n4608; + wire n4610; + wire n4611; + wire n4612; + wire n4613; + wire n4616; + wire n4616_1; + wire n4618; + wire n4620; + wire n4621; + wire n4622; + wire n4625; + wire n4626; + wire n4627; + wire n4629; + wire n4630; + wire n4631_1; + wire n4632; + wire n4633; + wire n4634; + wire n4635; + wire n4636_1; + wire n4637; + wire n4639; + wire n4641; + wire n4644; + wire n4646; + wire n4646_1; + wire n4648; + wire n4650; + wire n4651; + wire n4652; + wire n4655; + wire n4656; + wire n4658; + wire n4660; + wire n4661; + wire n4661_1; + wire n4663; + wire n4664; + wire n4665; + wire n4666; + wire n4671; + wire n4672; + wire n4676; + wire n4676_1; + wire n4678; + wire n4681; + wire n4681_1; + wire n4685; + wire n4686; + wire n4688; + wire n4689; + wire n4690; + wire n4691; + wire n4691_1; + wire n4692; + wire n4694; + wire n4696; + wire n4696_1; + wire n4700; + wire n4701; + wire n4702; + wire n4705; + wire n4706; + wire n4706_1; + wire n4708; + wire n4710; + wire n4711; + wire n4711_1; + wire n4712; + wire n4713; + wire n4716; + wire n4718; + wire n4720; + wire n4721; + wire n4723; + wire n4725; + wire n4726; + wire n4726_1; + wire n4728; + wire n4730; + wire n4731; + wire n4733; + wire n4734; + wire n4735; + wire n4736; + wire n4736_1; + wire n4737; + wire n4740; + wire n4741; + wire n4742; + wire n4743; + wire n4745; + wire n4746_1; + wire n4748; + wire n4751; + wire n4751_1; + wire n4756; + wire n4756_1; + wire n4758; + wire n4760; + wire n4761; + wire n4762; + wire n4765; + wire n4765_1; + wire n4768; + wire n4770; + wire n4770_1; + wire n4772; + wire n4774; + wire n4775; + wire n4776; + wire n4777; + wire n4779; + wire n4780; + wire n4781; + wire n4782; + wire n4783; + wire n4785; + wire n4786; + wire n4788; + wire n4790; + wire n4791; + wire n4794; + wire n4795; + wire n4796; + wire n4797; + wire n4799; + wire n4800; + wire n4803; + wire n4805; + wire n4806; + wire n4810; + wire n4812; + wire n4815; + wire n4820; + wire n4825; + wire n4827; + wire n4830; + wire n4830_1; + wire n4834; + wire n4835; + wire n4837; + wire n4838; + wire n4839; + wire n4840; + wire n4840_1; + wire n4841; + wire n4842; + wire n4843; + wire n4844; + wire n4845; + wire n4845_1; + wire n4846; + wire n4848; + wire n4850; + wire n4851; + wire n4852; + wire n4854; + wire n4855; + wire n4858; + wire n4859; + wire n4860; + wire n4862; + wire n4864; + wire n4865; + wire n4865_1; + wire n4866; + wire n4869; + wire n4869_1; + wire n4872; + wire n4873; + wire n4874; + wire n4879; + wire n4879_1; + wire n4881; + wire n4884; + wire n4884_1; + wire n4886; + wire n4889; + wire n4890; + wire n4893; + wire n4894; + wire n4896; + wire n4897; + wire n4899; + wire n4899_1; + wire n4904; + wire n4904_1; + wire n4908; + wire n4909; + wire n4912; + wire n4913; + wire n4914; + wire n4915; + wire n4916; + wire n4917; + wire n4918; + wire n4919; + wire n4919_1; + wire n4921; + wire n4924; + wire n4925; + wire n4927; + wire n4929; + wire n4929_1; + wire n4932; + wire n4934; + wire n4934_1; + wire n4936; + wire n4938; + wire n4939_1; + wire n4940; + wire n4942; + wire n4944; + wire n4944_1; + wire n4947; + wire n4949; + wire n4949_1; + wire n4951; + wire n4952; + wire n4954; + wire n4959; + wire n4959_1; + wire n4960; + wire n4961; + wire n4963; + wire n4964; + wire n4965; + wire n4968; + wire n4969; + wire n4969_1; + wire n4971; + wire n4973; + wire n4974; + wire n4978_1; + wire n4980; + wire n4983; + wire n4983_1; + wire n4984; + wire n4986; + wire n4988; + wire n4989; + wire n4990; + wire n4991; + wire n4992; + wire n4993; + wire n4993_1; + wire n4994; + wire n4995; + wire n4996; + wire n4997; + wire n4997_1; + wire n4998; + wire n4999; + wire n5000; + wire n5001; + wire n5002_1; + wire n5003; + wire n5004; + wire n5006; + wire n5006_1; + wire n5007; + wire n5008; + wire n5009; + wire n5010; + wire n5010_1; + wire n5011; + wire n5012; + wire n5013; + wire n5014; + wire n5014_1; + wire n5015; + wire n5016; + wire n5018; + wire n5019; + wire n5023; + wire n5023_1; + wire n5027; + wire n5028; + wire n5031; + wire n5032; + wire n5033; + wire n5033_1; + wire n5037; + wire n5038; + wire n5039; + wire n5043; + wire n5043_1; + wire n5048; + wire n5050; + wire n5051; + wire n5053; + wire n5053_1; + wire n5056; + wire n5058; + wire n5063; + wire n5065; + wire n5066; + wire n5068; + wire n5069; + wire n5070; + wire n5071; + wire n5072; + wire n5073; + wire n5075; + wire n5077; + wire n5080; + wire n5082; + wire n5082_1; + wire n5083; + wire n5087; + wire n5087_1; + wire n5089; + wire n5092; + wire n5097; + wire n5098; + wire n5100; + wire n5102; + wire n5104; + wire n5106; + wire n5107; + wire n5111; + wire n5111_1; + wire n5113; + wire n5114; + wire n5116_1; + wire n5121_1; + wire n5122; + wire n5124; + wire n5126_1; + wire n5130; + wire n5131; + wire n5131_1; + wire n5136; + wire n5136_1; + wire n5137; + wire n5138; + wire n5140; + wire n5141_1; + wire n5142; + wire n5145; + wire n5146_1; + wire n5150; + wire n5151; + wire n5155; + wire n5156_1; + wire n5158; + wire n5160; + wire n5160_1; + wire n5163; + wire n5165; + wire n5166; + wire n5170; + wire n5172; + wire n5175; + wire n5179; + wire n5180; + wire n5182; + wire n5184; + wire n5185; + wire n5186; + wire n5189; + wire n5190; + wire n5193; + wire n5195; + wire n5195_1; + wire n5197; + wire n5199; + wire n5200; + wire n5201; + wire n5203; + wire n5204; + wire n5206; + wire n5208; + wire n5208_1; + wire n5210; + wire n5213; + wire n5214; + wire n5218; + wire n5218_1; + wire n5221; + wire n5223; + wire n5223_1; + wire n5226; + wire n5228; + wire n5228_1; + wire n5229; + wire n5232; + wire n5233; + wire n5234; + wire n5236; + wire n5238; + wire n5240; + wire n5243; + wire n5243_1; + wire n5245; + wire n5247; + wire n5248; + wire n5249; + wire n5251; + wire n5253; + wire n5254; + wire n5255; + wire n5256; + wire n5258; + wire n5258_1; + wire n5263; + wire n5263_1; + wire n5265; + wire n5266; + wire n5267; + wire n5269; + wire n5271; + wire n5271_1; + wire n5275; + wire n5276; + wire n5276_1; + wire n5280; + wire n5281; + wire n5283; + wire n5285; + wire n5286; + wire n5287; + wire n5289; + wire n5291; + wire n5292; + wire n5295; + wire n5296; + wire n5301; + wire n5301_1; + wire n5304; + wire n5305; + wire n5306; + wire n5306_1; + wire n5310; + wire n5311; + wire n5313; + wire n5315; + wire n5316; + wire n5320; + wire n5321; + wire n5323; + wire n5325; + wire n5326; + wire n5327; + wire n5328; + wire n5329; + wire n5330; + wire n5330_1; + wire n5331; + wire n5332; + wire n5333; + wire n5334; + wire n5335; + wire n5335_1; + wire n5336; + wire n5340; + wire n5341; + wire n5342; + wire n5343; + wire n5345; + wire n5345_1; + wire n5346; + wire n5347; + wire n5350; + wire n5355; + wire n5356; + wire n5357; + wire n5358; + wire n5360; + wire n5360_1; + wire n5363; + wire n5365; + wire n5365_1; + wire n5366; + wire n5369; + wire n5370; + wire n5371; + wire n5373; + wire n5375; + wire n5375_1; + wire n5377; + wire n5380; + wire n5382; + wire n5384; + wire n5385; + wire n5386; + wire n5389; + wire n5390; + wire n5392; + wire n5395; + wire n5397; + wire n5400; + wire n5400_1; + wire n5402; + wire n5404; + wire n5405; + wire n5408; + wire n5410; + wire n5415; + wire n5419; + wire n5420; + wire n5421; + wire n5424; + wire n5425; + wire n5426; + wire n5427; + wire n5428; + wire n5430; + wire n5430_1; + wire n5432; + wire n5434; + wire n5435; + wire n5437; + wire n5439; + wire n5439_1; + wire n5442; + wire n5444; + wire n5445; + wire n5447; + wire n5449; + wire n5452; + wire n5454; + wire n5457; + wire n5459; + wire n5459_1; + wire n5463; + wire n5464; + wire n5465; + wire n5467; + wire n5468; + wire n5470; + wire n5472; + wire n5473; + wire n5476; + wire n5477; + wire n5482; + wire n5482_1; + wire n5486; + wire n5487; + wire n5490; + wire n5492; + wire n5492_1; + wire n5494; + wire n5497; + wire n5498; + wire n5499; + wire n5501; + wire n5502; + wire n5507; + wire n5507_1; + wire n5509; + wire n5512; + wire n5514; + wire n5515; + wire n5516; + wire n5517; + wire n5517_1; + wire n5521; + wire n5522; + wire n5526; + wire n5527; + wire n5529; + wire n5531; + wire n5532; + wire n5534; + wire n5536; + wire n5537; + wire n5540; + wire n5542; + wire n5542_1; + wire n5543; + wire n5544; + wire n5547; + wire n5548; + wire n5550; + wire n5552; + wire n5554; + wire n5556; + wire n5557; + wire n5560; + wire n5562; + wire n5563; + wire n5567; + wire n5569; + wire n5572; + wire n5574; + wire n5576; + wire n5577; + wire n5578; + wire n5582; + wire n5586; + wire n5587; + wire n5592; + wire n5594; + wire n5596; + wire n5597; + wire n5598; + wire n5600; + wire n5602; + wire n5603; + wire n5606; + wire n5607; + wire n5609; + wire n5612; + wire n5613; + wire n5617; + wire n5618; + wire n5622; + wire n5622_1; + wire n5624; + wire n5625; + wire n5626; + wire n5627; + wire n5627_1; + wire n5628; + wire n5629; + wire n5630; + wire n5631; + wire n5632; + wire n5632_1; + wire n5633; + wire n5634; + wire n5635; + wire n5636; + wire n5637; + wire n5637_1; + wire n5638; + wire n5639; + wire n5640; + wire n5641; + wire n5642; + wire n5642_1; + wire n5644; + wire n5645; + wire n5646; + wire n5647; + wire n5647_1; + wire n5648; + wire n5649; + wire n5650; + wire n5651; + wire n5652; + wire n5652_1; + wire n5653; + wire n5654; + wire n5655; + wire n5656; + wire n5657; + wire n5657_1; + wire n5658; + wire n5659; + wire n5660; + wire n5661; + wire n5662; + wire n5662_1; + wire n5663; + wire n5664; + wire n5665; + wire n5666; + wire n5667; + wire n5667_1; + wire n5668; + wire n5669; + wire n5670; + wire n5671; + wire n5672; + wire n5672_1; + wire n5673; + wire n5674; + wire n5675; + wire n5676; + wire n5677; + wire n5677_1; + wire n5678; + wire n5679; + wire n5680; + wire n5681; + wire n5682; + wire n5682_1; + wire n5683; + wire n5684; + wire n5685; + wire n5686; + wire n5687; + wire n5687_1; + wire n5688; + wire n5689; + wire n5690; + wire n5691; + wire n5692; + wire n5694; + wire n5695; + wire n5696; + wire n5697; + wire n5698; + wire n5699; + wire n5700; + wire n5702; + wire n5702_1; + wire n5703; + wire n5704; + wire n5705; + wire n5707; + wire n5708; + wire n5710; + wire n5711; + wire n5712; + wire n5712_1; + wire n5713; + wire n5716; + wire n5717; + wire n5717_1; + wire n5718; + wire n5719; + wire n5720; + wire n5721; + wire n5722; + wire n5722_1; + wire n5723; + wire n5727; + wire n5732; + wire n5737; + wire n5742; + wire n5747; + wire n5752; + wire n5754; + wire n5755; + wire n5756; + wire n5756_1; + wire n5761; + wire n5766; + wire n5766_1; + wire n5768; + wire n5769; + wire n5771; + wire n5771_1; + wire n5773; + wire n5776; + wire n5781; + wire n5786; + wire n5786_1; + wire n5789; + wire n5791_1; + wire n5792; + wire n5795; + wire n5796_1; + wire n5800; + wire n5801_1; + wire n5806_1; + wire n5811_1; + wire n5816; + wire n5820; + wire n5821; + wire n5822; + wire n5824; + wire n5826; + wire n5826_1; + wire n5828; + wire n5830; + wire n5831; + wire n5835; + wire n5840; + wire n5841; + wire n5845; + wire n5850; + wire n5855; + wire n5856; + wire n5858; + wire n5860; + wire n5860_1; + wire n5864; + wire n5865; + wire n5870; + wire n5875; + wire n5880; + wire n5884_1; + wire n5889; + wire n5894; + wire n5899; + wire n5904; + wire n5908; + wire n5910; + wire n5913; + wire n5914; + wire n5917; + wire n5918; + wire n5923; + wire n5926; + wire n5928; + wire n5929; + wire n5932; + wire n5933; + wire n5935; + wire n5938; + wire n5938_1; + wire n5942; + wire n5943; + wire n5943_1; + wire n5945; + wire n5948; + wire n5948_1; + wire n5951; + wire n5953; + wire n5955; + wire n5956; + wire n5958; + wire n5963; + wire n5963_1; + wire n5964; + wire n5968; + wire n5973; + wire n5977; + wire n5978; + wire n5978_1; + wire n5983; + wire n5988; + wire n5993; + wire n5998_1; + wire n6003; + wire n6008_1; + wire n6013; + wire n6015; + wire n6018; + wire n6023; + wire n6024; + wire n6025; + wire n6028; + wire n6029; + wire n6030; + wire n6031; + wire n6033; + wire n6036; + wire n6038; + wire n6040; + wire n6043; + wire n6048; + wire n6049; + wire n6053; + wire n6058; + wire n6058_1; + wire n6063; + wire n6064; + wire n6068; + wire n6068_1; + wire n6073; + wire n6077; + wire n6078; + wire n6079; + wire n6083; + wire n6088; + wire n6090; + wire n6093; + wire n6096; + wire n6097; + wire n6098; + wire n6099; + wire n6102; + wire n6103; + wire n6103_1; + wire n6107; + wire n6108; + wire n6113; + wire n6115; + wire n6118; + wire n6123; + wire n6128; + wire n6132; + wire n6133; + wire n6133_1; + wire n6134; + wire n6135; + wire n6136; + wire n6137; + wire n6138; + wire n6138_1; + wire n6139; + wire n6140; + wire n6141; + wire n6142; + wire n6143; + wire n6143_1; + wire n6144; + wire n6145; + wire n6146; + wire n6147; + wire n6148; + wire n6148_1; + wire n6149; + wire n6150; + wire n6151; + wire n6153; + wire n6153_1; + wire n6154; + wire n6155; + wire n6156; + wire n6157; + wire n6158; + wire n6158_1; + wire n6159; + wire n6160; + wire n6161; + wire n6162; + wire n6163; + wire n6163_1; + wire n6164; + wire n6165; + wire n6166; + wire n6167; + wire n6168; + wire n6168_1; + wire n6169; + wire n6170; + wire n6171; + wire n6172; + wire n6173; + wire n6174; + wire n6175; + wire n6176; + wire n6177; + wire n6178; + wire n6178_1; + wire n6180; + wire n6182; + wire n6182_1; + wire n6183; + wire n6184; + wire n6185; + wire n6186; + wire n6186_1; + wire n6188; + wire n6189; + wire n6190; + wire n6191; + wire n6191_1; + wire n6192; + wire n6195; + wire n6196; + wire n6196_1; + wire n6198; + wire n6199; + wire n6200; + wire n6201; + wire n6202; + wire n6203; + wire n6204; + wire n6205; + wire n6205_1; + wire n6207; + wire n6208; + wire n6209; + wire n6210; + wire n6210_1; + wire n6211; + wire n6213; + wire n6214; + wire n6215; + wire n6215_1; + wire n6220; + wire n6225; + wire n6230_1; + wire n6235_1; + wire n6240_1; + wire n6245_1; + wire n6250_1; + wire n6255_1; + wire n6260_1; + wire n6265_1; + wire n6270_1; + wire n6275_1; + wire n6280; + wire n6285; + wire n6289_1; + wire n6294; + wire n6299; + wire n6304; + wire n6309; + wire n6314; + wire n6319; + wire n6324; + wire n6329; + wire n6334; + wire n6339; + wire n6344; + wire n6348; + wire n6353; + wire n6358; + wire n6363; + wire n6368; + wire n6373; + wire n6378; + wire n6383; + wire n6388; + wire n6393; + wire n6398; + wire n6403_1; + wire n6408; + wire n6412; + wire n6417_1; + wire n6422_1; + wire n6427_1; + wire n6432_1; + wire n6437_1; + wire n6442_1; + wire n6447_1; + wire n6452_1; + wire n6457_1; + wire n6462_1; + wire n6467_1; + wire n6472_1; + wire n6477_1; + wire n6482_1; + wire n6487_1; + wire n6492_1; + wire n6497_1; + wire n6502_1; + wire n6507_1; + wire n6512_1; + wire n6517_1; + wire n6521; + wire n6526; + wire n6531_1; + wire n6536_1; + wire n6541_1; + wire n6546_1; + wire n6550; + wire n6555; + wire n6560_1; + wire n6565_1; + wire n6570_1; + wire n6575_1; + wire n6580_1; + wire n6585_1; + wire n6590_1; + wire n6595_1; + wire n6600_1; + wire n6605_1; + wire n6610_1; + wire n6615_1; + wire n6620_1; + wire n6625; + wire n6630; + wire n6635; + wire n6640; + wire n6645; + wire n6650; + wire n6655; + wire n6660; + wire n687_1; + wire n691; + wire n694; + wire n697; + wire n700; + wire n703; + wire n706; + wire n709; + wire n712_1; + wire n715; + wire n718; + wire n721; + wire n724; + wire n727; + wire n730; + wire n733; + wire n736; + wire n739; + wire n742; + wire n745; + wire n748; + wire n751; + wire n754; + wire n757; + wire n760; + wire n763; + wire n766; + wire n769; + wire n772; + wire n775; + wire n779; + wire n782; + wire n786; + wire n789; + wire n792; + wire n795; + wire n798; + wire n801; + wire n804; + wire n807; + wire n810; + wire n813; + wire n816; + wire n819; + wire n822; + wire n825; + wire n828; + wire n831; + wire n834; + wire n837; + wire n840; + wire n843; + wire n846; + wire n849; + wire n852; + wire n855; + wire n858; + wire n861; + wire n864; + wire n867; + wire n870; + wire n873; + wire n876; + wire n880; + wire n883; + wire n886; + wire n889; + wire n892; + wire n895; + wire n898; + wire n901; + wire n904; + wire n907; + wire n910; + wire n913; + wire n916; + wire n919; + wire n922; + wire n925; + wire n928; + wire n931; + wire n935; + wire n939; + wire n943; + wire n947; + wire n951; + wire n955; + wire n959; + wire n963; + wire n967; + wire n971; + wire n975; + wire n978; + wire n982; + wire n986; + wire n990; + wire n994; + wire n998; + always @(posedge clock) + Pg19357 <= n687_1; + always @(posedge clock) + Pg17760 <= n715; + always @(posedge clock) + Pg10306 <= n1006; + always @(posedge clock) + Ng1319 <= n5380; + always @(posedge clock) + Ng2066 <= n5385; + always @(posedge clock) + Ng1152 <= n5390; + always @(posedge clock) + Ng5252 <= n5395; + always @(posedge clock) + Ng2165 <= n5400; + always @(posedge clock) + Ng2571 <= n5405; + always @(posedge clock) + Ng5176 <= n5410; + always @(posedge clock) + Ng1211 <= n5415; + always @(posedge clock) + Ng2827 <= n5420; + always @(posedge clock) + Ng4859 <= n5425; + always @(posedge clock) + Pg10122 <= n1010; + always @(posedge clock) + Ng424 <= n5430; + always @(posedge clock) + Ng1274 <= n5435; + always @(posedge clock) + Ng85 <= n5439; + always @(posedge clock) + Ng2803 <= n5444; + always @(posedge clock) + Ng1821 <= n5449; + always @(posedge clock) + Ng2509 <= n5454; + always @(posedge clock) + Ng5073 <= n5459; + always @(posedge clock) + Ng1280 <= n5464; + always @(posedge clock) + Pg8353 <= n5468; + always @(posedge clock) + Ng6633 <= n5472; + always @(posedge clock) + Pg9817 <= n1014; + always @(posedge clock) + Ng5124 <= n5477; + always @(posedge clock) + Ng6303 <= n5482; + always @(posedge clock) + Ng5069 <= n5487; + always @(posedge clock) + Ng2994 <= n5492; + always @(posedge clock) + Ng650 <= n5497; + always @(posedge clock) + Ng1636 <= n5502; + always @(posedge clock) + Ng3921 <= n5507; + always @(posedge clock) + Ng2093 <= n5512; + always @(posedge clock) + Ng6732 <= n5517; + always @(posedge clock) + Ng1306 <= n5522; + always @(posedge clock) + Pg9743 <= n1018; + always @(posedge clock) + Ng1061 <= n5527; + always @(posedge clock) + Ng3462 <= n5532; + always @(posedge clock) + Ng2181 <= n5537; + always @(posedge clock) + Ng956 <= n5542; + always @(posedge clock) + Ng1756 <= n5547; + always @(posedge clock) + Ng5849 <= n5552; + always @(posedge clock) + Ng4112 <= n5557; + always @(posedge clock) + Ng2685 <= n5562; + always @(posedge clock) + Ng2197 <= n5567; + always @(posedge clock) + Ng2421 <= n5572; + always @(posedge clock) + Pg9741 <= n1022; + always @(posedge clock) + Ng1046 <= n5577; + always @(posedge clock) + Ng482 <= n5582; + always @(posedge clock) + Ng4401 <= n5587; + always @(posedge clock) + Ng1514 <= n5592; + always @(posedge clock) + Ng329 <= n5597; + always @(posedge clock) + Ng6565 <= n5602; + always @(posedge clock) + Ng2950 <= n5607; + always @(posedge clock) + Ng1345 <= n5612; + always @(posedge clock) + Ng6533 <= n5617; + always @(posedge clock) + Ng4727 <= n5622; + always @(posedge clock) + Pg9682 <= n1026; + always @(posedge clock) + Ng1536 <= n5627; + always @(posedge clock) + Ng3941 <= n5632; + always @(posedge clock) + Ng370 <= n5637; + always @(posedge clock) + Ng5694 <= n5642; + always @(posedge clock) + Ng1858 <= n5647; + always @(posedge clock) + Ng446 <= n5652; + always @(posedge clock) + Ng3219 <= n5657; + always @(posedge clock) + Ng1811 <= n5662; + always @(posedge clock) + Ng6601 <= n5667; + always @(posedge clock) + Ng2441 <= n5672; + always @(posedge clock) + Pg9680 <= n1030; + always @(posedge clock) + Ng1874 <= n5677; + always @(posedge clock) + Ng4349 <= n5682; + always @(posedge clock) + Ng6581 <= n5687; + always @(posedge clock) + Ng6597 <= n5692; + always @(posedge clock) + Ng3610 <= n5697; + always @(posedge clock) + Ng2890 <= n5702; + always @(posedge clock) + Ng1978 <= n5707; + always @(posedge clock) + Ng1612 <= n5712; + always @(posedge clock) + Ng112 <= n5717; + always @(posedge clock) + Ng2856 <= n5722; + always @(posedge clock) + Pg9617 <= n1034; + always @(posedge clock) + Ng1982 <= n5727; + always @(posedge clock) + Ng5228 <= n5732; + always @(posedge clock) + Ng4119 <= n5737; + always @(posedge clock) + Ng6390 <= n5742; + always @(posedge clock) + Ng1542 <= n5747; + always @(posedge clock) + Ng4258 <= n5752; + always @(posedge clock) + Ng4818 <= n5756; + always @(posedge clock) + Ng5033 <= n5761; + always @(posedge clock) + Ng4717 <= n5766; + always @(posedge clock) + Ng1554 <= n5771; + always @(posedge clock) + Pg9615 <= n1038; + always @(posedge clock) + Ng3849 <= n5776; + always @(posedge clock) + Ng3199 <= n5781; + always @(posedge clock) + Ng5845 <= n5786_1; + always @(posedge clock) + Ng4975 <= n5791_1; + always @(posedge clock) + Ng790 <= n5796_1; + always @(posedge clock) + Ng5913 <= n5801_1; + always @(posedge clock) + Ng1902 <= n5806_1; + always @(posedge clock) + Ng6163 <= n5811_1; + always @(posedge clock) + Ng4125 <= n5816; + always @(posedge clock) + Ng4821 <= n5821; + always @(posedge clock) + Pg9555 <= n1042; + always @(posedge clock) + Ng4939 <= n5826; + always @(posedge clock) + Ng3207 <= n5831; + always @(posedge clock) + Ng4483 <= n5835; + always @(posedge clock) + Ng3259 <= n5840; + always @(posedge clock) + Ng5142 <= n5845; + always @(posedge clock) + Ng5248 <= n5850; + always @(posedge clock) + Ng2126 <= n5855; + always @(posedge clock) + Ng3694 <= n5860; + always @(posedge clock) + Ng5481 <= n5865; + always @(posedge clock) + Ng1964 <= n5870; + always @(posedge clock) + Pg17743 <= n718; + always @(posedge clock) + Pg9553 <= n1046; + always @(posedge clock) + Ng5097 <= n5875; + always @(posedge clock) + Ng3215 <= n5880; + always @(posedge clock) + Ng111 <= n5884_1; + always @(posedge clock) + Ng4427 <= n5889; + always @(posedge clock) + Ng2779 <= n5894; + always @(posedge clock) + Ng1720 <= n5899; + always @(posedge clock) + Ng1367 <= n5904; + always @(posedge clock) + Ng5112 <= n5908; + always @(posedge clock) + Ng4145 <= n5913; + always @(posedge clock) + Ng2161 <= n5918; + always @(posedge clock) + Pg9497 <= n1050; + always @(posedge clock) + Ng376 <= n5923; + always @(posedge clock) + Ng2361 <= n5928; + always @(posedge clock) + Ng582 <= n5933; + always @(posedge clock) + Ng2051 <= n5938; + always @(posedge clock) + Ng1193 <= n5943; + always @(posedge clock) + Ng2327 <= n5948; + always @(posedge clock) + Ng907 <= n5953; + always @(posedge clock) + Ng947 <= n5958; + always @(posedge clock) + Ng1834 <= n5963; + always @(posedge clock) + Ng3594 <= n5968; + always @(posedge clock) + Pg9251 <= n1054; + always @(posedge clock) + Ng2999 <= n5973; + always @(posedge clock) + Ng2303 <= n5978; + always @(posedge clock) + Ng699 <= n5983; + always @(posedge clock) + Ng723 <= n5988; + always @(posedge clock) + Ng5703 <= n5993; + always @(posedge clock) + Ng546 <= n5998_1; + always @(posedge clock) + Ng2472 <= n6003; + always @(posedge clock) + Ng5953 <= n6008_1; + always @(posedge clock) + Ng1740 <= n6013; + always @(posedge clock) + Ng3550 <= n6018; + always @(posedge clock) + Pg9048 <= n1057; + always @(posedge clock) + Ng3845 <= n6023; + always @(posedge clock) + Ng2116 <= n6028; + always @(posedge clock) + Ng3195 <= n6033; + always @(posedge clock) + Ng3913 <= n6038; + always @(posedge clock) + Ng1687 <= n6043; + always @(posedge clock) + Ng2681 <= n6048; + always @(posedge clock) + Ng2533 <= n6053; + always @(posedge clock) + Ng324 <= n6058; + always @(posedge clock) + Ng2697 <= n6063; + always @(posedge clock) + Ng4417 <= n6068; + always @(posedge clock) + Pg9019 <= n1061; + always @(posedge clock) + Ng6561 <= n6073; + always @(posedge clock) + Ng1141 <= n6078; + always @(posedge clock) + Ng2413 <= n6083; + always @(posedge clock) + Ng1710 <= n6088; + always @(posedge clock) + Ng6527 <= n6093; + always @(posedge clock) + Ng3255 <= n6098; + always @(posedge clock) + Ng1691 <= n6103; + always @(posedge clock) + Ng2936 <= n6108; + always @(posedge clock) + Ng5644 <= n6113; + always @(posedge clock) + Ng5152 <= n6118; + always @(posedge clock) + Pg8920 <= n1064; + always @(posedge clock) + Ng5352 <= n6123; + always @(posedge clock) + Ng2775 <= n6128; + always @(posedge clock) + Ng2922 <= n6133; + always @(posedge clock) + Ng1111 <= n6138; + always @(posedge clock) + Ng5893 <= n6143; + always @(posedge clock) + Ng6617 <= n6148; + always @(posedge clock) + Ng2060 <= n6153; + always @(posedge clock) + Ng4512 <= n6158; + always @(posedge clock) + Ng5599 <= n6163; + always @(posedge clock) + Ng3401 <= n6168; + always @(posedge clock) + Pg8919 <= n1067; + always @(posedge clock) + Ng4366 <= n6173; + always @(posedge clock) + Pg20652 <= n6178; + always @(posedge clock) + Ng3129 <= n6182; + always @(posedge clock) + Ng3329 <= n6186; + always @(posedge clock) + Ng5170 <= n6191; + always @(posedge clock) + Ng26959 <= n6196_1; + always @(posedge clock) + Ng5821 <= n6200; + always @(posedge clock) + Ng6299 <= n6205; + always @(posedge clock) + Ng2079 <= n6210; + always @(posedge clock) + Ng4698 <= n6215; + always @(posedge clock) + Pg8918 <= n1070; + always @(posedge clock) + Ng3703 <= n6220; + always @(posedge clock) + Ng1559 <= n6225; + always @(posedge clock) + Ng943 <= n6230_1; + always @(posedge clock) + Ng411 <= n6235_1; + always @(posedge clock) + Ng3953 <= n6240_1; + always @(posedge clock) + Ng2704 <= n6245_1; + always @(posedge clock) + Ng6035 <= n6250_1; + always @(posedge clock) + Ng1300 <= n6255_1; + always @(posedge clock) + Ng4057 <= n6260_1; + always @(posedge clock) + Ng5200 <= n6265_1; + always @(posedge clock) + Pg8917 <= n1073; + always @(posedge clock) + Ng4843 <= n6270_1; + always @(posedge clock) + Ng5046 <= n6275_1; + always @(posedge clock) + Ng2250 <= n6280; + always @(posedge clock) + Ng26885 <= n6285; + always @(posedge clock) + Ng4549 <= n6289_1; + always @(posedge clock) + Ng2453 <= n6294; + always @(posedge clock) + Ng5841 <= n6299; + always @(posedge clock) + Ng2912 <= n6304; + always @(posedge clock) + Ng2357 <= n6309; + always @(posedge clock) + Ng164 <= n6314; + always @(posedge clock) + Pg8916 <= n1076; + always @(posedge clock) + Ng4253 <= n6319; + always @(posedge clock) + Ng5016 <= n6324; + always @(posedge clock) + Ng3119 <= n6329; + always @(posedge clock) + Ng1351 <= n6334; + always @(posedge clock) + Ng1648 <= n6339; + always @(posedge clock) + Ng6972 <= n6344; + always @(posedge clock) + Ng5115 <= n6348; + always @(posedge clock) + Ng3352 <= n6353; + always @(posedge clock) + Ng6657 <= n6358; + always @(posedge clock) + Ng4552 <= n6363; + always @(posedge clock) + Pg17739 <= n721; + always @(posedge clock) + Pg8915 <= n1079; + always @(posedge clock) + Ng3893 <= n6368; + always @(posedge clock) + Ng3211 <= n6373; + always @(posedge clock) + Ng5595 <= n6378; + always @(posedge clock) + Ng3614 <= n6383; + always @(posedge clock) + Ng2894 <= n6388; + always @(posedge clock) + Ng3125 <= n6393; + always @(posedge clock) + Ng3821 <= n6398; + always @(posedge clock) + Ng4141 <= n6403_1; + always @(posedge clock) + Ng6974 <= n6408; + always @(posedge clock) + Ng5272 <= n6412; + always @(posedge clock) + Pg8870 <= n1082_1; + always @(posedge clock) + Ng2735 <= n6417_1; + always @(posedge clock) + Ng728 <= n6422_1; + always @(posedge clock) + Ng6295 <= n6427_1; + always @(posedge clock) + Ng2661 <= n6432_1; + always @(posedge clock) + Ng1988 <= n6437_1; + always @(posedge clock) + Ng5128 <= n6442_1; + always @(posedge clock) + Ng1548 <= n6447_1; + always @(posedge clock) + Ng3106 <= n6452_1; + always @(posedge clock) + Ng4659 <= n6457_1; + always @(posedge clock) + Ng4358 <= n6462_1; + always @(posedge clock) + Pg8839 <= n1086; + always @(posedge clock) + Ng1792 <= n6467_1; + always @(posedge clock) + Ng2084 <= n6472_1; + always @(posedge clock) + Ng3187 <= n6477_1; + always @(posedge clock) + Ng4311 <= n6482_1; + always @(posedge clock) + Ng2583 <= n6487_1; + always @(posedge clock) + Ng3003 <= n6492_1; + always @(posedge clock) + Ng1094 <= n6497_1; + always @(posedge clock) + Ng3841 <= n6502_1; + always @(posedge clock) + Ng4284 <= n6507_1; + always @(posedge clock) + Ng3191 <= n6512_1; + always @(posedge clock) + Pg8789 <= n1089; + always @(posedge clock) + Ng4239 <= n6517_1; + always @(posedge clock) + Ng4180 <= n6521; + always @(posedge clock) + Ng691 <= n6526; + always @(posedge clock) + Ng534 <= n6531_1; + always @(posedge clock) + Ng385 <= n6536_1; + always @(posedge clock) + Ng2004 <= n6541_1; + always @(posedge clock) + Ng2527 <= n6546_1; + always @(posedge clock) + Ng5456 <= n6550; + always @(posedge clock) + Ng4420 <= n6555; + always @(posedge clock) + Ng5148 <= n6560_1; + always @(posedge clock) + Pg8788 <= n1092; + always @(posedge clock) + Ng4507 <= n6565_1; + always @(posedge clock) + Ng5348 <= n6570_1; + always @(posedge clock) + Ng3223 <= n6575_1; + always @(posedge clock) + Ng2970 <= n6580_1; + always @(posedge clock) + Ng5698 <= n6585_1; + always @(posedge clock) + Ng5260 <= n6590_1; + always @(posedge clock) + Ng1521 <= n6595_1; + always @(posedge clock) + Ng3522 <= n6600_1; + always @(posedge clock) + Ng3115 <= n6605_1; + always @(posedge clock) + Ng3251 <= n6610_1; + always @(posedge clock) + Pg8787 <= n1095; + always @(posedge clock) + Ng4628 <= n6615_1; + always @(posedge clock) + Ng1996 <= n6620_1; + always @(posedge clock) + Ng4515 <= n6625; + always @(posedge clock) + Ng4300 <= n6630; + always @(posedge clock) + Ng1724 <= n6635; + always @(posedge clock) + Ng1379 <= n6640; + always @(posedge clock) + Ng1878 <= n6645; + always @(posedge clock) + Ng5619 <= n6650; + always @(posedge clock) + Ng71 <= n6655; + always @(posedge clock) + Pg20049 <= n6660; + always @(posedge clock) + Pg8786 <= n1098; + always @(posedge clock) + Pg8785 <= n1101; + always @(posedge clock) + Pg8784 <= n1104; + always @(posedge clock) + Pg8783 <= n1107; + always @(posedge clock) + Pg17722 <= n724; + always @(posedge clock) + Pg8719 <= n1111; + always @(posedge clock) + Pg8475 <= n1114; + always @(posedge clock) + Pg8416 <= n1117_1; + always @(posedge clock) + Pg8398 <= n1121; + always @(posedge clock) + Pg8358 <= n1125; + always @(posedge clock) + Pg8344 <= n1129; + always @(posedge clock) + Pg8342 <= n1133; + always @(posedge clock) + Pg8291 <= n1137; + always @(posedge clock) + Pg8279 <= n1141; + always @(posedge clock) + Pg8277 <= n1145; + always @(posedge clock) + Pg17715 <= n727; + always @(posedge clock) + Pg8215 <= n1149; + always @(posedge clock) + Pg7946 <= n1153; + always @(posedge clock) + Pg7916 <= n1157; + always @(posedge clock) + Pg7540 <= n1161; + always @(posedge clock) + Pg7260 <= n1165; + always @(posedge clock) + Pg7257 <= n1169; + always @(posedge clock) + Pg7245 <= n1173; + always @(posedge clock) + Pg7243 <= n1177; + always @(posedge clock) + Ng5057 <= n1181_1; + always @(posedge clock) + Ng2771 <= n1186_1; + always @(posedge clock) + Pg17711 <= n730; + always @(posedge clock) + Ng1882 <= n1191; + always @(posedge clock) + Ng2299 <= n1196; + always @(posedge clock) + Ng4040 <= n1201; + always @(posedge clock) + Ng2547 <= n1206; + always @(posedge clock) + Ng559 <= n1210; + always @(posedge clock) + Ng3243 <= n1215; + always @(posedge clock) + Ng452 <= n1220; + always @(posedge clock) + Ng3542 <= n1225; + always @(posedge clock) + Ng5232 <= n1230; + always @(posedge clock) + Ng5813 <= n1235; + always @(posedge clock) + Pg17688 <= n733; + always @(posedge clock) + Ng2907 <= n1240; + always @(posedge clock) + Ng1744 <= n1245; + always @(posedge clock) + Ng5909 <= n1250; + always @(posedge clock) + Ng1802 <= n1255; + always @(posedge clock) + Ng3554 <= n1260; + always @(posedge clock) + Ng6219 <= n1265; + always @(posedge clock) + Ng807 <= n1270; + always @(posedge clock) + Ng6031 <= n1274; + always @(posedge clock) + Ng847 <= n1279; + always @(posedge clock) + Ng976 <= n1284; + always @(posedge clock) + Pg17685 <= n736; + always @(posedge clock) + Ng4172 <= n1289; + always @(posedge clock) + Ng4372 <= n1294; + always @(posedge clock) + Ng3512 <= n1299; + always @(posedge clock) + Ng749 <= n1304; + always @(posedge clock) + Ng3490 <= n1309; + always @(posedge clock) + Ng4235 <= n1313; + always @(posedge clock) + Ng1600 <= n1318; + always @(posedge clock) + Ng1714 <= n1323; + always @(posedge clock) + Ng3155 <= n1328; + always @(posedge clock) + Ng2236 <= n1333; + always @(posedge clock) + Pg17678 <= n739; + always @(posedge clock) + Ng4555 <= n1338; + always @(posedge clock) + Ng3698 <= n1343; + always @(posedge clock) + Ng1736 <= n1348; + always @(posedge clock) + Ng1968 <= n1353; + always @(posedge clock) + Ng4621 <= n1358; + always @(posedge clock) + Ng5607 <= n1363; + always @(posedge clock) + Ng2657 <= n1368; + always @(posedge clock) + Ng490 <= n1373; + always @(posedge clock) + Ng311 <= n1378; + always @(posedge clock) + Ng772 <= n1383; + always @(posedge clock) + Pg17674 <= n742; + always @(posedge clock) + Ng5587 <= n1388; + always @(posedge clock) + Ng6177 <= n1393; + always @(posedge clock) + Ng6377 <= n1397; + always @(posedge clock) + Ng3167 <= n1402; + always @(posedge clock) + Ng5615 <= n1407; + always @(posedge clock) + Ng4567 <= n1412; + always @(posedge clock) + Ng3457 <= n1417; + always @(posedge clock) + Ng6287 <= n1422; + always @(posedge clock) + Ng2563 <= n1427; + always @(posedge clock) + Ng4776 <= n1432; + always @(posedge clock) + Pg19334 <= n691; + always @(posedge clock) + Pg17649 <= n745; + always @(posedge clock) + Ng4593 <= n1437; + always @(posedge clock) + Ng6199 <= n1442; + always @(posedge clock) + Ng2295 <= n1447_1; + always @(posedge clock) + Ng1384 <= n1452; + always @(posedge clock) + Ng1339 <= n1457_1; + always @(posedge clock) + Ng5180 <= n1462; + always @(posedge clock) + Ng2844 <= n1467_1; + always @(posedge clock) + Ng1024 <= n1472; + always @(posedge clock) + Ng5591 <= n1477_1; + always @(posedge clock) + Ng3598 <= n1482; + always @(posedge clock) + Pg17646 <= n748; + always @(posedge clock) + Ng4264 <= n1487; + always @(posedge clock) + Ng767 <= n1492; + always @(posedge clock) + Ng5853 <= n1497; + always @(posedge clock) + Ng2089 <= n1502; + always @(posedge clock) + Ng4933 <= n1507; + always @(posedge clock) + Ng4521 <= n1512; + always @(posedge clock) + Ng5507 <= n1517_1; + always @(posedge clock) + Ng6291 <= n1522; + always @(posedge clock) + Ng294 <= n1527_1; + always @(posedge clock) + Ng5559 <= n1532; + always @(posedge clock) + Pg17639 <= n751; + always @(posedge clock) + Ng3813 <= n1537; + always @(posedge clock) + Ng562 <= n1542; + always @(posedge clock) + Ng608 <= n1547; + always @(posedge clock) + Ng1205 <= n1552; + always @(posedge clock) + Ng3909 <= n1557; + always @(posedge clock) + Ng6259 <= n1562; + always @(posedge clock) + Ng5905 <= n1567_1; + always @(posedge clock) + Ng921 <= n1572; + always @(posedge clock) + Ng2955 <= n1577; + always @(posedge clock) + Ng203 <= n1582; + always @(posedge clock) + Pg17607 <= n754; + always @(posedge clock) + Ng1099 <= n1587; + always @(posedge clock) + Ng4878 <= n1592; + always @(posedge clock) + Ng5204 <= n1597; + always @(posedge clock) + Ng3606 <= n1602; + always @(posedge clock) + Ng1926 <= n1607; + always @(posedge clock) + Ng6215 <= n1612; + always @(posedge clock) + Ng3586 <= n1617; + always @(posedge clock) + Ng291 <= n1622; + always @(posedge clock) + Ng4674 <= n1627; + always @(posedge clock) + Ng3570 <= n1632; + always @(posedge clock) + Pg17604 <= n757; + always @(posedge clock) + Ng1862 <= n1637; + always @(posedge clock) + Ng676 <= n1642; + always @(posedge clock) + Ng843 <= n1647; + always @(posedge clock) + Ng4332 <= n1652; + always @(posedge clock) + Ng4153 <= n1657; + always @(posedge clock) + Ng6336 <= n1662; + always @(posedge clock) + Ng622 <= n1667; + always @(posedge clock) + Ng3506 <= n1672; + always @(posedge clock) + Ng4558 <= n1677; + always @(posedge clock) + Ng3111 <= n1682; + always @(posedge clock) + Pg17580 <= n760; + always @(posedge clock) + Pg21270 <= n1687; + always @(posedge clock) + Ng26936 <= n1691; + always @(posedge clock) + Ng939 <= n1696; + always @(posedge clock) + Ng278 <= n1701; + always @(posedge clock) + Ng4492 <= n1706; + always @(posedge clock) + Ng4864 <= n1711; + always @(posedge clock) + Ng1036 <= n1716; + always @(posedge clock) + Pg21245 <= n1721; + always @(posedge clock) + Ng1178 <= n1725; + always @(posedge clock) + Ng3239 <= n1730; + always @(posedge clock) + Pg17577 <= n763; + always @(posedge clock) + Ng718 <= n1735; + always @(posedge clock) + Ng6195 <= n1740; + always @(posedge clock) + Ng1135 <= n1745; + always @(posedge clock) + Ng6395 <= n1750; + always @(posedge clock) + Pg25219 <= n1755; + always @(posedge clock) + Ng554 <= n1759; + always @(posedge clock) + Ng496 <= n1764; + always @(posedge clock) + Ng3853 <= n1769; + always @(posedge clock) + Ng5134 <= n1774; + always @(posedge clock) + Ng2485 <= n1779; + always @(posedge clock) + Pg17519 <= n766; + always @(posedge clock) + Ng925 <= n1784; + always @(posedge clock) + Ng48 <= n1789; + always @(posedge clock) + Ng5555 <= n1794; + always @(posedge clock) + Ng1798 <= n1799; + always @(posedge clock) + Ng4076 <= n1804; + always @(posedge clock) + Ng2941 <= n1809; + always @(posedge clock) + Ng3905 <= n1814; + always @(posedge clock) + Ng763 <= n1819; + always @(posedge clock) + Ng6255 <= n1824; + always @(posedge clock) + Ng4375 <= n1829; + always @(posedge clock) + Pg17423 <= n769; + always @(posedge clock) + Ng4871 <= n1834; + always @(posedge clock) + Ng4722 <= n1839; + always @(posedge clock) + Ng590 <= n1844; + always @(posedge clock) + Ng1632 <= n1849; + always @(posedge clock) + Ng3100 <= n1853; + always @(posedge clock) + Ng1495 <= n1858; + always @(posedge clock) + Ng1437 <= n1863; + always @(posedge clock) + Ng6154 <= n1868_1; + always @(posedge clock) + Ng1579 <= n1872; + always @(posedge clock) + Ng5567 <= n1877; + always @(posedge clock) + Pg17404 <= n772; + always @(posedge clock) + Ng1752 <= n1882; + always @(posedge clock) + Ng1917 <= n1887; + always @(posedge clock) + Ng744 <= n1892; + always @(posedge clock) + Ng4737 <= n1897; + always @(posedge clock) + Pg8132 <= n1902; + always @(posedge clock) + Ng6267 <= n1906; + always @(posedge clock) + Ng1442 <= n1911; + always @(posedge clock) + Ng5965 <= n1916; + always @(posedge clock) + Ng4477 <= n1921; + always @(posedge clock) + Ng4643 <= n1926; + always @(posedge clock) + Pg17871 <= n694; + always @(posedge clock) + Pg17400 <= n775; + always @(posedge clock) + Ng5264 <= n1931; + always @(posedge clock) + Ng2610 <= n1936; + always @(posedge clock) + Ng5160 <= n1941; + always @(posedge clock) + Ng5933 <= n1946; + always @(posedge clock) + Ng1454 <= n1951; + always @(posedge clock) + Ng753 <= n1956; + always @(posedge clock) + Ng1296 <= n1961; + always @(posedge clock) + Ng3151 <= n1966; + always @(posedge clock) + Ng2980 <= n1971; + always @(posedge clock) + Ng6727 <= n1976; + always @(posedge clock) + Pg17320 <= n779; + always @(posedge clock) + Ng3530 <= n1981; + always @(posedge clock) + Ng4104 <= n1986; + always @(posedge clock) + Ng1532 <= n1991; + always @(posedge clock) + Ng2177 <= n1996; + always @(posedge clock) + Ng52 <= n2001; + always @(posedge clock) + Ng4754 <= n2006; + always @(posedge clock) + Ng1189 <= n2011; + always @(posedge clock) + Ng2287 <= n2016; + always @(posedge clock) + Ng4273 <= n2021; + always @(posedge clock) + Ng1389 <= n2026; + always @(posedge clock) + Pg17316 <= n782; + always @(posedge clock) + Ng1706 <= n2031; + always @(posedge clock) + Ng5835 <= n2036; + always @(posedge clock) + Ng1171 <= n2041; + always @(posedge clock) + Ng4269 <= n2046; + always @(posedge clock) + Ng2399 <= n2051; + always @(posedge clock) + Ng4983 <= n2056; + always @(posedge clock) + Ng5611 <= n2061; + always @(posedge clock) + Ng4572 <= n2066; + always @(posedge clock) + Ng3143 <= n2071; + always @(posedge clock) + Ng2898 <= n2076; + always @(posedge clock) + Pg17291 <= n786; + always @(posedge clock) + Ng3343 <= n2081; + always @(posedge clock) + Ng3235 <= n2086; + always @(posedge clock) + Ng4543 <= n2091; + always @(posedge clock) + Ng3566 <= n2096; + always @(posedge clock) + Ng4534 <= n2101; + always @(posedge clock) + Ng4961 <= n2106; + always @(posedge clock) + Ng4927 <= n2111_1; + always @(posedge clock) + Ng2259 <= n2116_1; + always @(posedge clock) + Ng2819 <= n2121; + always @(posedge clock) + Ng5802 <= n2125; + always @(posedge clock) + Pg16955 <= n789; + always @(posedge clock) + Ng2852 <= n2130; + always @(posedge clock) + Ng417 <= n2135; + always @(posedge clock) + Ng681 <= n2140; + always @(posedge clock) + Ng437 <= n2145; + always @(posedge clock) + Ng351 <= n2150; + always @(posedge clock) + Ng5901 <= n2155; + always @(posedge clock) + Ng2886 <= n2160; + always @(posedge clock) + Ng3494 <= n2165; + always @(posedge clock) + Ng5511 <= n2170; + always @(posedge clock) + Ng3518 <= n2175; + always @(posedge clock) + Pg16924 <= n792; + always @(posedge clock) + Ng1604 <= n2180; + always @(posedge clock) + Ng5092 <= n2185; + always @(posedge clock) + Ng4831 <= n2190; + always @(posedge clock) + Ng4382 <= n2195; + always @(posedge clock) + Ng6386 <= n2200; + always @(posedge clock) + Ng479 <= n2205; + always @(posedge clock) + Ng3965 <= n2210; + always @(posedge clock) + Ng4749 <= n2215; + always @(posedge clock) + Ng2008 <= n2220; + always @(posedge clock) + Ng736 <= n2224; + always @(posedge clock) + Pg16874 <= n795; + always @(posedge clock) + Ng3933 <= n2229; + always @(posedge clock) + Ng222 <= n2234; + always @(posedge clock) + Ng3050 <= n2239; + always @(posedge clock) + Ng1052 <= n2244; + always @(posedge clock) + Ng2122 <= n2249; + always @(posedge clock) + Ng2465 <= n2254; + always @(posedge clock) + Ng5889 <= n2259; + always @(posedge clock) + Ng4495 <= n2264; + always @(posedge clock) + Ng4653 <= n2269; + always @(posedge clock) + Ng3179 <= n2274; + always @(posedge clock) + Pg16775 <= n798; + always @(posedge clock) + Ng1728 <= n2279; + always @(posedge clock) + Ng2433 <= n2284; + always @(posedge clock) + Ng3835 <= n2289; + always @(posedge clock) + Ng6187 <= n2294; + always @(posedge clock) + Ng4917 <= n2299; + always @(posedge clock) + Ng1070 <= n2304; + always @(posedge clock) + Ng822 <= n2309; + always @(posedge clock) + Ng914 <= n2314; + always @(posedge clock) + Ng5339 <= n2318; + always @(posedge clock) + Ng4164 <= n2323; + always @(posedge clock) + Pg16748 <= n801; + always @(posedge clock) + Ng969 <= n2328; + always @(posedge clock) + Ng2807 <= n2333; + always @(posedge clock) + Ng4054 <= n2338; + always @(posedge clock) + Ng6191 <= n2343; + always @(posedge clock) + Ng5077 <= n2348; + always @(posedge clock) + Ng5523 <= n2353; + always @(posedge clock) + Ng3680 <= n2357; + always @(posedge clock) + Ng6637 <= n2362; + always @(posedge clock) + Ng174 <= n2367; + always @(posedge clock) + Ng1682 <= n2372; + always @(posedge clock) + Pg16744 <= n804; + always @(posedge clock) + Ng355 <= n2377; + always @(posedge clock) + Ng1087 <= n2381; + always @(posedge clock) + Ng1105 <= n2386; + always @(posedge clock) + Ng2342 <= n2391; + always @(posedge clock) + Ng6307 <= n2396; + always @(posedge clock) + Ng3802 <= n2400; + always @(posedge clock) + Ng6159 <= n2405; + always @(posedge clock) + Ng2255 <= n2410; + always @(posedge clock) + Ng2815 <= n2415; + always @(posedge clock) + Ng911 <= n2420; + always @(posedge clock) + Pg17845 <= n697; + always @(posedge clock) + Pg16722 <= n807; + always @(posedge clock) + Ng43 <= n2425; + always @(posedge clock) + Ng1748 <= n2430; + always @(posedge clock) + Ng5551 <= n2435; + always @(posedge clock) + Ng3558 <= n2440; + always @(posedge clock) + Ng5499 <= n2445; + always @(posedge clock) + Ng2960 <= n2450; + always @(posedge clock) + Ng3901 <= n2455; + always @(posedge clock) + Ng4888 <= n2460; + always @(posedge clock) + Ng6251 <= n2465; + always @(posedge clock) + Ng1373 <= n2470; + always @(posedge clock) + Pg16718 <= n810; + always @(posedge clock) + Ng157 <= n2475; + always @(posedge clock) + Ng2783 <= n2480; + always @(posedge clock) + Ng4281 <= n2484; + always @(posedge clock) + Ng3574 <= n2489; + always @(posedge clock) + Ng2112 <= n2494; + always @(posedge clock) + Ng1283 <= n2499; + always @(posedge clock) + Ng433 <= n2504; + always @(posedge clock) + Ng4297 <= n2508; + always @(posedge clock) + Ng758 <= n2513; + always @(posedge clock) + Ng4639 <= n2518; + always @(posedge clock) + Pg16693 <= n813; + always @(posedge clock) + Ng6537 <= n2523; + always @(posedge clock) + Ng5543 <= n2528; + always @(posedge clock) + Ng5961 <= n2533; + always @(posedge clock) + Ng6243 <= n2538; + always @(posedge clock) + Ng632 <= n2543; + always @(posedge clock) + Ng3889 <= n2548; + always @(posedge clock) + Ng3476 <= n2553; + always @(posedge clock) + Ng1664 <= n2558; + always @(posedge clock) + Ng1246 <= n2563; + always @(posedge clock) + Ng6629 <= n2568; + always @(posedge clock) + Pg16686 <= n816; + always @(posedge clock) + Ng246 <= n2573; + always @(posedge clock) + Ng4049 <= n2578; + always @(posedge clock) + Ng2932 <= n2583; + always @(posedge clock) + Ng4575 <= n2588; + always @(posedge clock) + Ng4098 <= n2593; + always @(posedge clock) + Ng4498 <= n2598; + always @(posedge clock) + Ng528 <= n2603; + always @(posedge clock) + Ng16 <= n2608; + always @(posedge clock) + Ng3139 <= n2613; + always @(posedge clock) + Pg20901 <= n2618; + always @(posedge clock) + Pg16659 <= n819; + always @(posedge clock) + Ng4584 <= n2622; + always @(posedge clock) + Ng142 <= n2627; + always @(posedge clock) + Ng5831 <= n2632; + always @(posedge clock) + Ng239 <= n2637; + always @(posedge clock) + Ng1216 <= n2642; + always @(posedge clock) + Ng2848 <= n2647; + always @(posedge clock) + Ng5022 <= n2652; + always @(posedge clock) + Ng1030 <= n2657; + always @(posedge clock) + Ng3231 <= n2662; + always @(posedge clock) + Ng1430 <= n2666; + always @(posedge clock) + Pg16656 <= n822; + always @(posedge clock) + Ng4452 <= n2670; + always @(posedge clock) + Ng2241 <= n2675; + always @(posedge clock) + Ng1564 <= n2680; + always @(posedge clock) + Ng6148 <= n2684; + always @(posedge clock) + Ng6649 <= n2689; + always @(posedge clock) + Ng110 <= n2694; + always @(posedge clock) + Ng225 <= n2699; + always @(posedge clock) + Ng4486 <= n2704; + always @(posedge clock) + Ng4504 <= n2709; + always @(posedge clock) + Ng5873 <= n2714; + always @(posedge clock) + Pg16627 <= n825; + always @(posedge clock) + Ng5037 <= n2719; + always @(posedge clock) + Ng2319 <= n2724; + always @(posedge clock) + Ng5495 <= n2729; + always @(posedge clock) + Ng5208 <= n2734; + always @(posedge clock) + Ng5579 <= n2739; + always @(posedge clock) + Ng5869 <= n2744; + always @(posedge clock) + Ng1589 <= n2749; + always @(posedge clock) + Ng5752 <= n2754; + always @(posedge clock) + Ng6279 <= n2759; + always @(posedge clock) + Ng5917 <= n2764; + always @(posedge clock) + Pg16624 <= n828; + always @(posedge clock) + Ng2975 <= n2769; + always @(posedge clock) + Ng6167 <= n2774; + always @(posedge clock) + Ng2599 <= n2779; + always @(posedge clock) + Ng1448 <= n2784; + always @(posedge clock) + Ng2370 <= n2789; + always @(posedge clock) + Ng5164 <= n2794; + always @(posedge clock) + Ng1333 <= n2798; + always @(posedge clock) + Ng153 <= n2803; + always @(posedge clock) + Ng6549 <= n2808; + always @(posedge clock) + Ng4087 <= n2813; + always @(posedge clock) + Pg16603 <= n831; + always @(posedge clock) + Ng4801 <= n2818; + always @(posedge clock) + Ng2984 <= n2823; + always @(posedge clock) + Ng3961 <= n2828_1; + always @(posedge clock) + Ng962 <= n2833; + always @(posedge clock) + Ng101 <= n2838; + always @(posedge clock) + Ng6625 <= n2843; + always @(posedge clock) + Ng51 <= n2848; + always @(posedge clock) + Ng1018 <= n2853; + always @(posedge clock) + Ng4045 <= n2858; + always @(posedge clock) + Ng1467 <= n2863; + always @(posedge clock) + Pg14828 <= n834; + always @(posedge clock) + Ng2461 <= n2868; + always @(posedge clock) + Ng2756 <= n2873; + always @(posedge clock) + Ng5990 <= n2878; + always @(posedge clock) + Ng1256 <= n2883; + always @(posedge clock) + Ng5029 <= n2888; + always @(posedge clock) + Ng6519 <= n2893; + always @(posedge clock) + Ng1816 <= n2898; + always @(posedge clock) + Ng4369 <= n2903; + always @(posedge clock) + Ng4578 <= n2908; + always @(posedge clock) + Ng4459 <= n2913; + always @(posedge clock) + Pg17819 <= n700; + always @(posedge clock) + Pg14779 <= n837; + always @(posedge clock) + Ng3831 <= n2918; + always @(posedge clock) + Ng2514 <= n2923; + always @(posedge clock) + Ng3288 <= n2928; + always @(posedge clock) + Ng2403 <= n2933; + always @(posedge clock) + Ng2145 <= n2938; + always @(posedge clock) + Ng1700 <= n2943; + always @(posedge clock) + Ng513 <= n2948; + always @(posedge clock) + Ng2841 <= n2952; + always @(posedge clock) + Ng5297 <= n2957; + always @(posedge clock) + Ng2763 <= n2962; + always @(posedge clock) + Pg14749 <= n840; + always @(posedge clock) + Ng4793 <= n2967; + always @(posedge clock) + Ng952 <= n2972; + always @(posedge clock) + Ng1263 <= n2977; + always @(posedge clock) + Ng1950 <= n2982; + always @(posedge clock) + Ng5138 <= n2987; + always @(posedge clock) + Ng2307 <= n2992; + always @(posedge clock) + Ng5109 <= n2996; + always @(posedge clock) + Ng4664 <= n3001; + always @(posedge clock) + Ng2223 <= n3006; + always @(posedge clock) + Ng5808 <= n3011; + always @(posedge clock) + Pg14738 <= n843; + always @(posedge clock) + Ng6645 <= n3016; + always @(posedge clock) + Ng2016 <= n3021; + always @(posedge clock) + Ng3873 <= n3026; + always @(posedge clock) + Ng2315 <= n3031; + always @(posedge clock) + Ng2811 <= n3036; + always @(posedge clock) + Ng5957 <= n3041; + always @(posedge clock) + Ng2047 <= n3046; + always @(posedge clock) + Ng3869 <= n3051; + always @(posedge clock) + Ng5575 <= n3056; + always @(posedge clock) + Ng46 <= n3061; + always @(posedge clock) + Pg14705 <= n846; + always @(posedge clock) + Ng3752 <= n3066; + always @(posedge clock) + Ng3917 <= n3071; + always @(posedge clock) + Ng1585 <= n3075_1; + always @(posedge clock) + Ng4388 <= n3080; + always @(posedge clock) + Ng6275 <= n3085; + always @(posedge clock) + Ng6311 <= n3090; + always @(posedge clock) + Ng1041 <= n3095; + always @(posedge clock) + Ng2595 <= n3100; + always @(posedge clock) + Ng2537 <= n3105; + always @(posedge clock) + Pg21292 <= n3110; + always @(posedge clock) + Pg14694 <= n849; + always @(posedge clock) + Ng4430 <= n3114; + always @(posedge clock) + Ng4564 <= n3119; + always @(posedge clock) + Ng4826 <= n3124; + always @(posedge clock) + Ng6239 <= n3129; + always @(posedge clock) + Ng232 <= n3134; + always @(posedge clock) + Ng5268 <= n3139; + always @(posedge clock) + Ng6545 <= n3144; + always @(posedge clock) + Ng2417 <= n3149; + always @(posedge clock) + Ng1772 <= n3154; + always @(posedge clock) + Ng5052 <= n3159; + always @(posedge clock) + Pg14673 <= n852; + always @(posedge clock) + Ng1890 <= n3164; + always @(posedge clock) + Ng2629 <= n3169; + always @(posedge clock) + Ng572 <= n3174; + always @(posedge clock) + Ng2130 <= n3179; + always @(posedge clock) + Ng4108 <= n3184; + always @(posedge clock) + Ng4308 <= n3188; + always @(posedge clock) + Ng475 <= n3193; + always @(posedge clock) + Ng990 <= n3197; + always @(posedge clock) + Ng45 <= n3202; + always @(posedge clock) + Ng3990 <= n3207; + always @(posedge clock) + Pg14662 <= n855; + always @(posedge clock) + Ng5881 <= n3212; + always @(posedge clock) + Ng1992 <= n3217; + always @(posedge clock) + Ng3171 <= n3222; + always @(posedge clock) + Ng812 <= n3227; + always @(posedge clock) + Ng832 <= n3232; + always @(posedge clock) + Ng5897 <= n3237_1; + always @(posedge clock) + Ng4571 <= n3242; + always @(posedge clock) + Ng4455 <= n3246; + always @(posedge clock) + Ng2902 <= n3251; + always @(posedge clock) + Ng333 <= n3256; + always @(posedge clock) + Pg14635 <= n858; + always @(posedge clock) + Ng168 <= n3261; + always @(posedge clock) + Ng2823 <= n3266; + always @(posedge clock) + Ng3684 <= n3271; + always @(posedge clock) + Ng3639 <= n3276; + always @(posedge clock) + Ng3338 <= n3281; + always @(posedge clock) + Ng5406 <= n3286; + always @(posedge clock) + Ng269 <= n3291; + always @(posedge clock) + Ng401 <= n3296; + always @(posedge clock) + Ng6040 <= n3301_1; + always @(posedge clock) + Ng441 <= n3306; + always @(posedge clock) + Pg14597 <= n861; + always @(posedge clock) + Ng3808 <= n3311_1; + always @(posedge clock) + Ng10384 <= n3316; + always @(posedge clock) + Ng3957 <= n3321_1; + always @(posedge clock) + Ng4093 <= n3326; + always @(posedge clock) + Ng1760 <= n3331; + always @(posedge clock) + Ng160 <= n3336_1; + always @(posedge clock) + Ng2279 <= n3341; + always @(posedge clock) + Ng3498 <= n3346; + always @(posedge clock) + Ng586 <= n3351; + always @(posedge clock) + Ng2619 <= n3356; + always @(posedge clock) + Pg14518 <= n864; + always @(posedge clock) + Ng1183 <= n3361; + always @(posedge clock) + Ng1608 <= n3366; + always @(posedge clock) + Ng1779 <= n3371; + always @(posedge clock) + Ng2652 <= n3376; + always @(posedge clock) + Ng2193 <= n3381; + always @(posedge clock) + Ng2393 <= n3386; + always @(posedge clock) + Ng661 <= n3391; + always @(posedge clock) + Ng4950 <= n3396; + always @(posedge clock) + Ng5535 <= n3401; + always @(posedge clock) + Ng2834 <= n3406; + always @(posedge clock) + Pg17813 <= n703; + always @(posedge clock) + Pg14451 <= n867; + always @(posedge clock) + Ng1361 <= n3411_1; + always @(posedge clock) + Ng6235 <= n3416_1; + always @(posedge clock) + Ng1146 <= n3421; + always @(posedge clock) + Ng2625 <= n3426; + always @(posedge clock) + Ng150 <= n3431; + always @(posedge clock) + Ng1696 <= n3436; + always @(posedge clock) + Ng6555 <= n3441; + always @(posedge clock) + Ng3881 <= n3446; + always @(posedge clock) + Ng6621 <= n3451; + always @(posedge clock) + Ng3470 <= n3456; + always @(posedge clock) + Pg14421 <= n870; + always @(posedge clock) + Ng3897 <= n3461; + always @(posedge clock) + Ng518 <= n3466; + always @(posedge clock) + Ng538 <= n3471; + always @(posedge clock) + Ng2606 <= n3476; + always @(posedge clock) + Ng1472 <= n3481; + always @(posedge clock) + Ng542 <= n3486; + always @(posedge clock) + Ng5188 <= n3491; + always @(posedge clock) + Ng5689 <= n3496; + always @(posedge clock) + Ng405 <= n3501; + always @(posedge clock) + Ng5216 <= n3506; + always @(posedge clock) + Pg14217 <= n873; + always @(posedge clock) + Ng6494 <= n3510; + always @(posedge clock) + Ng4669 <= n3515_1; + always @(posedge clock) + Ng996 <= n3520; + always @(posedge clock) + Ng4531 <= n3525; + always @(posedge clock) + Ng2860 <= n3530; + always @(posedge clock) + Ng4743 <= n3535; + always @(posedge clock) + Ng6593 <= n3540; + always @(posedge clock) + Ng4411 <= n3544; + always @(posedge clock) + Ng1413 <= n3549; + always @(posedge clock) + Ng26960 <= n3553_1; + always @(posedge clock) + Pg14201 <= n876; + always @(posedge clock) + Ng6641 <= n3557; + always @(posedge clock) + Ng1936 <= n3562; + always @(posedge clock) + Ng55 <= n3567; + always @(posedge clock) + Ng504 <= n3572; + always @(posedge clock) + Ng2587 <= n3577; + always @(posedge clock) + Ng4480 <= n3582; + always @(posedge clock) + Ng2311 <= n3587; + always @(posedge clock) + Ng3602 <= n3592; + always @(posedge clock) + Ng5571 <= n3597; + always @(posedge clock) + Ng3578 <= n3602; + always @(posedge clock) + Pg14189 <= n880; + always @(posedge clock) + Ng5827 <= n3607; + always @(posedge clock) + Ng3582 <= n3612; + always @(posedge clock) + Ng6271 <= n3617; + always @(posedge clock) + Ng4688 <= n3622; + always @(posedge clock) + Ng2380 <= n3627; + always @(posedge clock) + Ng5196 <= n3632; + always @(posedge clock) + Ng3227 <= n3637; + always @(posedge clock) + Ng2020 <= n3642; + always @(posedge clock) + Ng6541 <= n3647; + always @(posedge clock) + Ng3203 <= n3652; + always @(posedge clock) + Pg14167 <= n883; + always @(posedge clock) + Ng1668 <= n3657; + always @(posedge clock) + Ng4760 <= n3662; + always @(posedge clock) + Ng262 <= n3667; + always @(posedge clock) + Ng1840 <= n3672; + always @(posedge clock) + Ng5467 <= n3677; + always @(posedge clock) + Ng460 <= n3682; + always @(posedge clock) + Ng6209 <= n3687; + always @(posedge clock) + Pg20763 <= n3692; + always @(posedge clock) + Ng655 <= n3696; + always @(posedge clock) + Ng3502 <= n3701; + always @(posedge clock) + Pg14147 <= n886; + always @(posedge clock) + Ng2204 <= n3706; + always @(posedge clock) + Ng5256 <= n3711; + always @(posedge clock) + Ng4608 <= n3716; + always @(posedge clock) + Ng794 <= n3721; + always @(posedge clock) + Ng4423 <= n3725_1; + always @(posedge clock) + Ng3689 <= n3730_1; + always @(posedge clock) + Ng5685 <= n3734; + always @(posedge clock) + Ng703 <= n3739; + always @(posedge clock) + Ng862 <= n3744; + always @(posedge clock) + Ng3247 <= n3749; + always @(posedge clock) + Pg14125 <= n889; + always @(posedge clock) + Ng2040 <= n3754; + always @(posedge clock) + Ng4146 <= n3759; + always @(posedge clock) + Ng4633 <= n3764; + always @(posedge clock) + Ng4732 <= n3769; + always @(posedge clock) + Ng5817 <= n3774; + always @(posedge clock) + Ng2351 <= n3779; + always @(posedge clock) + Ng2648 <= n3784; + always @(posedge clock) + Ng6736 <= n3789; + always @(posedge clock) + Ng4944 <= n3794; + always @(posedge clock) + Ng4072 <= n3799; + always @(posedge clock) + Pg14096 <= n892; + always @(posedge clock) + Ng4443 <= n3803; + always @(posedge clock) + Ng3466 <= n3808; + always @(posedge clock) + Ng4116 <= n3813; + always @(posedge clock) + Ng5041 <= n3818; + always @(posedge clock) + Ng4434 <= n3823; + always @(posedge clock) + Ng3827 <= n3828; + always @(posedge clock) + Ng6500 <= n3833; + always @(posedge clock) + Ng3133 <= n3838; + always @(posedge clock) + Ng3333 <= n3843; + always @(posedge clock) + Ng979 <= n3847; + always @(posedge clock) + Pg13966 <= n895; + always @(posedge clock) + Ng4681 <= n3852; + always @(posedge clock) + Ng298 <= n3857; + always @(posedge clock) + Ng2667 <= n3862; + always @(posedge clock) + Ng1894 <= n3867; + always @(posedge clock) + Ng2988 <= n3872; + always @(posedge clock) + Ng3538 <= n3877; + always @(posedge clock) + Ng301 <= n3882; + always @(posedge clock) + Ng341 <= n3887; + always @(posedge clock) + Ng827 <= n3892; + always @(posedge clock) + Ng2555 <= n3897; + always @(posedge clock) + Pg17787 <= n706; + always @(posedge clock) + Pg13926 <= n898; + always @(posedge clock) + Ng5011 <= n3902; + always @(posedge clock) + Ng199 <= n3907; + always @(posedge clock) + Ng6523 <= n3912_1; + always @(posedge clock) + Ng1526 <= n3917_1; + always @(posedge clock) + Ng4601 <= n3922_1; + always @(posedge clock) + Ng854 <= n3927_1; + always @(posedge clock) + Ng1484 <= n3932_1; + always @(posedge clock) + Ng4922 <= n3937; + always @(posedge clock) + Ng5080 <= n3942; + always @(posedge clock) + Ng5863 <= n3947_1; + always @(posedge clock) + Pg13906 <= n901; + always @(posedge clock) + Ng4581 <= n3952; + always @(posedge clock) + Ng2518 <= n3957; + always @(posedge clock) + Ng2567 <= n3962_1; + always @(posedge clock) + Ng568 <= n3967; + always @(posedge clock) + Ng3263 <= n3972; + always @(posedge clock) + Ng6613 <= n3977; + always @(posedge clock) + Ng6044 <= n3982; + always @(posedge clock) + Ng6444 <= n3987; + always @(posedge clock) + Ng2965 <= n3992; + always @(posedge clock) + Ng5857 <= n3997; + always @(posedge clock) + Pg13895 <= n904; + always @(posedge clock) + Ng1616 <= n4002; + always @(posedge clock) + Ng890 <= n4007; + always @(posedge clock) + Ng3562 <= n4012; + always @(posedge clock) + Ng1404 <= n4017; + always @(posedge clock) + Ng3817 <= n4022; + always @(posedge clock) + Ng93 <= n4027; + always @(posedge clock) + Ng4501 <= n4032; + always @(posedge clock) + Ng287 <= n4037; + always @(posedge clock) + Ng2724 <= n4042; + always @(posedge clock) + Ng4704 <= n4047; + always @(posedge clock) + Pg13881 <= n907; + always @(posedge clock) + Ng22 <= n4052; + always @(posedge clock) + Ng2878 <= n4057_1; + always @(posedge clock) + Ng5220 <= n4062_1; + always @(posedge clock) + Ng617 <= n4067; + always @(posedge clock) + Ng316 <= n4072; + always @(posedge clock) + Ng1277 <= n4077; + always @(posedge clock) + Ng6513 <= n4082; + always @(posedge clock) + Ng336 <= n4087; + always @(posedge clock) + Ng2882 <= n4092; + always @(posedge clock) + Ng933 <= n4097; + always @(posedge clock) + Pg13865 <= n910; + always @(posedge clock) + Ng1906 <= n4102; + always @(posedge clock) + Ng305 <= n4107; + always @(posedge clock) + Ng8 <= n4112; + always @(posedge clock) + Ng2799 <= n4117; + always @(posedge clock) + Ng4912 <= n4122; + always @(posedge clock) + Ng4157 <= n4127; + always @(posedge clock) + Ng2541 <= n4132; + always @(posedge clock) + Ng2153 <= n4137; + always @(posedge clock) + Ng550 <= n4142; + always @(posedge clock) + Ng255 <= n4147_1; + always @(posedge clock) + Pg13272 <= n913; + always @(posedge clock) + Ng1945 <= n4152; + always @(posedge clock) + Ng5240 <= n4157; + always @(posedge clock) + Ng1478 <= n4162; + always @(posedge clock) + Ng3863 <= n4167; + always @(posedge clock) + Ng1959 <= n4172; + always @(posedge clock) + Ng3480 <= n4177; + always @(posedge clock) + Ng6653 <= n4182; + always @(posedge clock) + Ng2864 <= n4187_1; + always @(posedge clock) + Ng4894 <= n4192; + always @(posedge clock) + Ng3857 <= n4197_1; + always @(posedge clock) + Pg13259 <= n916; + always @(posedge clock) + Ng499 <= n4202; + always @(posedge clock) + Ng1002 <= n4207; + always @(posedge clock) + Ng776 <= n4212; + always @(posedge clock) + Ng1236 <= n4216_1; + always @(posedge clock) + Ng4646 <= n4221; + always @(posedge clock) + Ng2476 <= n4226; + always @(posedge clock) + Ng1657 <= n4231; + always @(posedge clock) + Ng2375 <= n4236; + always @(posedge clock) + Ng63 <= n4241; + always @(posedge clock) + Ng358 <= n4245; + always @(posedge clock) + Pg13099 <= n919; + always @(posedge clock) + Ng896 <= n4250; + always @(posedge clock) + Ng283 <= n4255; + always @(posedge clock) + Ng3161 <= n4260; + always @(posedge clock) + Ng2384 <= n4265; + always @(posedge clock) + Ng4616 <= n4270; + always @(posedge clock) + Ng4561 <= n4275; + always @(posedge clock) + Ng2024 <= n4280; + always @(posedge clock) + Ng3451 <= n4284; + always @(posedge clock) + Ng2795 <= n4289; + always @(posedge clock) + Ng613 <= n4294; + always @(posedge clock) + Pg13085 <= n922; + always @(posedge clock) + Ng4527 <= n4299; + always @(posedge clock) + Ng1844 <= n4304; + always @(posedge clock) + Ng5937 <= n4309; + always @(posedge clock) + Ng4546 <= n4314; + always @(posedge clock) + Ng2523 <= n4319; + always @(posedge clock) + Ng2643 <= n4324; + always @(posedge clock) + Ng1489 <= n4329; + always @(posedge clock) + Ng2551 <= n4334; + always @(posedge clock) + Ng5156 <= n4339; + always @(posedge clock) + Pg23683 <= n4343; + always @(posedge clock) + Pg13068 <= n925; + always @(posedge clock) + Ng1955 <= n4347; + always @(posedge clock) + Ng6049 <= n4352; + always @(posedge clock) + Ng2273 <= n4357; + always @(posedge clock) + Ng4771 <= n4362; + always @(posedge clock) + Ng6098 <= n4367; + always @(posedge clock) + Ng3147 <= n4372; + always @(posedge clock) + Ng3347 <= n4377; + always @(posedge clock) + Ng2269 <= n4382; + always @(posedge clock) + Ng191 <= n4386; + always @(posedge clock) + Ng2712 <= n4391; + always @(posedge clock) + Pg17778 <= n709; + always @(posedge clock) + Pg13049 <= n928; + always @(posedge clock) + Ng626 <= n4396; + always @(posedge clock) + Ng2729 <= n4401; + always @(posedge clock) + Ng5357 <= n4406; + always @(posedge clock) + Ng4991 <= n4411; + always @(posedge clock) + Ng4709 <= n4416; + always @(posedge clock) + Ng2927 <= n4421; + always @(posedge clock) + Ng4340 <= n4426; + always @(posedge clock) + Ng5929 <= n4431; + always @(posedge clock) + Ng4907 <= n4436; + always @(posedge clock) + Ng4035 <= n4441; + always @(posedge clock) + Pg13039 <= n931; + always @(posedge clock) + Ng2946 <= n4446; + always @(posedge clock) + Ng918 <= n4451; + always @(posedge clock) + Ng4082 <= n4456; + always @(posedge clock) + Ng2036 <= n4461; + always @(posedge clock) + Ng577 <= n4466; + always @(posedge clock) + Ng1620 <= n4471; + always @(posedge clock) + Ng2831 <= n4476; + always @(posedge clock) + Ng667 <= n4481; + always @(posedge clock) + Ng930 <= n4486; + always @(posedge clock) + Ng3937 <= n4491; + always @(posedge clock) + Pg12923 <= n935; + always @(posedge clock) + Ng817 <= n4496; + always @(posedge clock) + Ng1249 <= n4501; + always @(posedge clock) + Ng837 <= n4506; + always @(posedge clock) + Ng599 <= n4511; + always @(posedge clock) + Ng5475 <= n4516; + always @(posedge clock) + Ng739 <= n4521; + always @(posedge clock) + Ng5949 <= n4526; + always @(posedge clock) + Ng6682 <= n4531; + always @(posedge clock) + Ng904 <= n4536; + always @(posedge clock) + Ng2873 <= n4541; + always @(posedge clock) + Pg12919 <= n939; + always @(posedge clock) + Ng1854 <= n4546; + always @(posedge clock) + Ng5084 <= n4551; + always @(posedge clock) + Ng5603 <= n4556; + always @(posedge clock) + Ng2495 <= n4561; + always @(posedge clock) + Ng2437 <= n4566; + always @(posedge clock) + Ng2102 <= n4571; + always @(posedge clock) + Ng2208 <= n4576; + always @(posedge clock) + Ng2579 <= n4581; + always @(posedge clock) + Ng4064 <= n4586; + always @(posedge clock) + Ng4899 <= n4591; + always @(posedge clock) + Pg12832 <= n943; + always @(posedge clock) + Ng2719 <= n4596; + always @(posedge clock) + Ng4785 <= n4601; + always @(posedge clock) + Ng5583 <= n4606; + always @(posedge clock) + Ng781 <= n4611; + always @(posedge clock) + Ng6173 <= n4616; + always @(posedge clock) + Ng2917 <= n4621; + always @(posedge clock) + Ng686 <= n4626; + always @(posedge clock) + Ng1252 <= n4631_1; + always @(posedge clock) + Ng671 <= n4636_1; + always @(posedge clock) + Ng2265 <= n4641; + always @(posedge clock) + Pg12470 <= n947; + always @(posedge clock) + Ng6283 <= n4646; + always @(posedge clock) + Ng5527 <= n4651; + always @(posedge clock) + Ng4489 <= n4656; + always @(posedge clock) + Ng1974 <= n4661; + always @(posedge clock) + Ng1270 <= n4666; + always @(posedge clock) + Ng4966 <= n4671; + always @(posedge clock) + Ng6227 <= n4676; + always @(posedge clock) + Ng3929 <= n4681; + always @(posedge clock) + Ng5503 <= n4686; + always @(posedge clock) + Ng4242 <= n4691; + always @(posedge clock) + Pg12422 <= n951; + always @(posedge clock) + Ng5925 <= n4696; + always @(posedge clock) + Ng1124 <= n4701; + always @(posedge clock) + Ng4955 <= n4706; + always @(posedge clock) + Ng5224 <= n4711; + always @(posedge clock) + Ng2012 <= n4716; + always @(posedge clock) + Ng6203 <= n4721; + always @(posedge clock) + Ng5120 <= n4726; + always @(posedge clock) + Ng2389 <= n4731; + always @(posedge clock) + Ng4438 <= n4736; + always @(posedge clock) + Ng2429 <= n4741; + always @(posedge clock) + Pg12368 <= n955; + always @(posedge clock) + Ng2787 <= n4746_1; + always @(posedge clock) + Ng1287 <= n4751; + always @(posedge clock) + Ng2675 <= n4756_1; + always @(posedge clock) + Pg18881 <= n4761; + always @(posedge clock) + Ng4836 <= n4765; + always @(posedge clock) + Ng1199 <= n4770; + always @(posedge clock) + Ng5547 <= n4775; + always @(posedge clock) + Ng2138 <= n4780; + always @(posedge clock) + Ng2338 <= n4785; + always @(posedge clock) + Ng6247 <= n4790; + always @(posedge clock) + Pg12350 <= n959; + always @(posedge clock) + Ng2791 <= n4795; + always @(posedge clock) + Ng3949 <= n4800; + always @(posedge clock) + Ng1291 <= n4805; + always @(posedge clock) + Ng5945 <= n4810; + always @(posedge clock) + Ng5244 <= n4815; + always @(posedge clock) + Ng2759 <= n4820; + always @(posedge clock) + Ng6741 <= n4825; + always @(posedge clock) + Ng785 <= n4830; + always @(posedge clock) + Ng1259 <= n4835; + always @(posedge clock) + Ng3484 <= n4840; + always @(posedge clock) + Pg12300 <= n963; + always @(posedge clock) + Ng209 <= n4845; + always @(posedge clock) + Ng6609 <= n4850; + always @(posedge clock) + Ng5517 <= n4855; + always @(posedge clock) + Ng2449 <= n4860; + always @(posedge clock) + Ng2575 <= n4865; + always @(posedge clock) + Ng65 <= n4869; + always @(posedge clock) + Ng2715 <= n4874; + always @(posedge clock) + Ng936 <= n4879; + always @(posedge clock) + Ng2098 <= n4884; + always @(posedge clock) + Ng4462 <= n4889; + always @(posedge clock) + Pg17764 <= n712_1; + always @(posedge clock) + Pg12238 <= n967; + always @(posedge clock) + Ng604 <= n4894; + always @(posedge clock) + Ng6589 <= n4899_1; + always @(posedge clock) + Ng1886 <= n4904_1; + always @(posedge clock) + Ng429 <= n4909; + always @(posedge clock) + Ng1870 <= n4914; + always @(posedge clock) + Ng4249 <= n4919; + always @(posedge clock) + Ng1825 <= n4924; + always @(posedge clock) + Ng1008 <= n4929; + always @(posedge clock) + Ng4392 <= n4934; + always @(posedge clock) + Ng3546 <= n4939_1; + always @(posedge clock) + Pg12184 <= n971; + always @(posedge clock) + Ng5236 <= n4944_1; + always @(posedge clock) + Ng1768 <= n4949; + always @(posedge clock) + Ng4854 <= n4954; + always @(posedge clock) + Ng3925 <= n4959; + always @(posedge clock) + Ng6509 <= n4964; + always @(posedge clock) + Ng732 <= n4969; + always @(posedge clock) + Ng2504 <= n4974; + always @(posedge clock) + Ng1322 <= n4978_1; + always @(posedge clock) + Ng4520 <= n4983; + always @(posedge clock) + Ng2185 <= n4988; + always @(posedge clock) + Pg11770 <= n975; + always @(posedge clock) + Ng37 <= n4993; + always @(posedge clock) + Ng4031 <= n4997_1; + always @(posedge clock) + Ng2070 <= n5002_1; + always @(posedge clock) + Pg8235 <= n5006; + always @(posedge clock) + Ng4176 <= n5010; + always @(posedge clock) + Ng4405 <= n5014; + always @(posedge clock) + Ng872 <= n5018; + always @(posedge clock) + Ng6181 <= n5023; + always @(posedge clock) + Ng6381 <= n5028; + always @(posedge clock) + Ng4765 <= n5033; + always @(posedge clock) + Pg11678 <= n978; + always @(posedge clock) + Ng5563 <= n5038; + always @(posedge clock) + Ng1395 <= n5043; + always @(posedge clock) + Ng1913 <= n5048; + always @(posedge clock) + Ng2331 <= n5053; + always @(posedge clock) + Ng6263 <= n5058; + always @(posedge clock) + Ng50 <= n5063; + always @(posedge clock) + Ng3945 <= n5068; + always @(posedge clock) + Ng347 <= n5072; + always @(posedge clock) + Ng4473 <= n5077; + always @(posedge clock) + Ng1266 <= n5082; + always @(posedge clock) + Pg11447 <= n982; + always @(posedge clock) + Ng5489 <= n5087; + always @(posedge clock) + Ng714 <= n5092; + always @(posedge clock) + Ng2748 <= n5097; + always @(posedge clock) + Ng5471 <= n5102; + always @(posedge clock) + Ng4540 <= n5107; + always @(posedge clock) + Ng6723 <= n5111_1; + always @(posedge clock) + Ng6605 <= n5116_1; + always @(posedge clock) + Ng2445 <= n5121_1; + always @(posedge clock) + Ng2173 <= n5126_1; + always @(posedge clock) + Ng2491 <= n5131_1; + always @(posedge clock) + Pg11418 <= n986; + always @(posedge clock) + Ng4849 <= n5136; + always @(posedge clock) + Ng2169 <= n5141_1; + always @(posedge clock) + Ng2283 <= n5146_1; + always @(posedge clock) + Ng6585 <= n5151; + always @(posedge clock) + Pg20654 <= n5156_1; + always @(posedge clock) + Ng2407 <= n5160; + always @(posedge clock) + Ng2868 <= n5165; + always @(posedge clock) + Ng2767 <= n5170; + always @(posedge clock) + Ng1783 <= n5175; + always @(posedge clock) + Ng1312 <= n5180; + always @(posedge clock) + Pg11388 <= n990; + always @(posedge clock) + Ng5212 <= n5185; + always @(posedge clock) + Ng4245 <= n5190; + always @(posedge clock) + Ng645 <= n5195; + always @(posedge clock) + Ng4291 <= n5199; + always @(posedge clock) + Pg20899 <= n5204; + always @(posedge clock) + Ng182 <= n5208; + always @(posedge clock) + Ng1129 <= n5213; + always @(posedge clock) + Ng2227 <= n5218; + always @(posedge clock) + Ng2246 <= n5223; + always @(posedge clock) + Ng1830 <= n5228; + always @(posedge clock) + Pg11349 <= n994; + always @(posedge clock) + Ng3590 <= n5233; + always @(posedge clock) + Ng392 <= n5238; + always @(posedge clock) + Ng1592 <= n5243; + always @(posedge clock) + Ng6505 <= n5248; + always @(posedge clock) + Ng1221 <= n5253; + always @(posedge clock) + Ng5921 <= n5258; + always @(posedge clock) + Pg21176 <= n5263; + always @(posedge clock) + Ng146 <= n5267; + always @(posedge clock) + Ng218 <= n5271; + always @(posedge clock) + Ng1932 <= n5276; + always @(posedge clock) + Pg10527 <= n998; + always @(posedge clock) + Ng1624 <= n5281; + always @(posedge clock) + Ng5062 <= n5286; + always @(posedge clock) + Ng5462 <= n5291; + always @(posedge clock) + Ng2689 <= n5296; + always @(posedge clock) + Ng6573 <= n5301; + always @(posedge clock) + Ng1677 <= n5306; + always @(posedge clock) + Ng2028 <= n5311; + always @(posedge clock) + Ng2671 <= n5316; + always @(posedge clock) + Ng1848 <= n5321; + always @(posedge clock) + Pg20557 <= n5326; + always @(posedge clock) + Pg10500 <= n1002; + always @(posedge clock) + Ng5485 <= n5330; + always @(posedge clock) + Ng2741 <= n5335; + always @(posedge clock) + Ng2638 <= n5340; + always @(posedge clock) + Ng4122 <= n5345; + always @(posedge clock) + Ng4322 <= n5350; + always @(posedge clock) + Ng5941 <= n5355; + always @(posedge clock) + Ng2108 <= n5360; + always @(posedge clock) + Ng1644 <= n5365; + always @(posedge clock) + Ng595 <= n5370; + always @(posedge clock) + Ng2217 <= n5375; + assign Pg31521 = 64'h0101010101010100 >> { Ng4141, Ng4082, n4124, Ng4064, Ng4125, Ng4057 }; + assign n4124 = 32'd8 >> { Ng4093, Ng4098, Ng4087, Ng4112, Ng4076 }; + assign n6655 = 64'hfb73d951ea62c840 >> { Ng4888, Ng4944, Ng4955, Ng4933, Ng4975, Ng4899 }; + assign Pg33935 = 64'hf7f7f7fff7fff7ff >> { Ng37, Pg99, Pg134, n6655, Pg8353, Pg8235 }; + assign n2838 = 64'hfb73d951ea62c840 >> { Ng4698, Ng4743, Ng4765, Ng4754, Ng4709, Ng4785 }; + assign Pg33636 = 64'hf7f7f7fff7fff7ff >> { Ng37, Pg99, Pg134, n2838, Pg8353, Pg8235 }; + assign Pg31793 = 64'h044c4c4c044d5d5d >> { n4133, Pg35, Ng3817, Ng3115, n4130, n4132_1 }; + assign n4130 = 32'd131626 >> { Ng5124, Ng6163, Ng5471, Ng5817, n4131 }; + assign n4131 = 32'd16843025 >> { Ng6509, Ng3466, Pg35, Ng4420, Ng4427 }; + assign n4132_1 = 32'd2863311528 >> { Ng5471, Ng5817, Ng5124, Ng6163, Pg35 }; + assign n4133 = 32'd4276092928 >> { Pg35, Ng6509, Ng3466, Ng4420, Ng4427 }; + assign Pg26877 = 8'hfd >> { n4135, n4137_1, Pg35 }; + assign n4135 = 32'd2 >> { Ng2606, Ng2625, Ng2357, Ng2491, n4136 }; + assign n4136 = 16'h0001 >> { Ng2223, Ng2472, Ng2204, Ng2338 }; + assign n4137_1 = 8'h02 >> { Ng2047, Ng1932, n4138 }; + assign n4138 = 64'h0000000000000001 >> { Ng1913, Ng1798, Ng1664, Ng1779, Ng1644, Ng2066 }; + assign Pg26876 = 8'hfd >> { n4140, n4142_1, Pg35 }; + assign n4140 = 8'h02 >> { Ng2671, Ng2403, n4141 }; + assign n4141 = 64'h0000000000000001 >> { Ng2269, Ng2551, Ng2685, Ng2283, Ng2417, Ng2537 }; + assign n4142_1 = 8'h02 >> { Ng1858, Ng1844, n4143 }; + assign n4143 = 64'h0000000000000001 >> { Ng1710, Ng2126, Ng1724, Ng2112, Ng1992, Ng1978 }; + assign Pg26875 = 32'd1431655767 >> { Ng1696, Ng1964, Ng1830, Ng2098, n4145 }; + assign n4145 = 32'd2863311528 >> { Ng2657, Ng2389, Ng2255, Ng2523, Pg35 }; + assign n1181_1 = 64'h3a3a6a2a9a1aca0a >> { n4149, n4147, n4151, Pg35, Ng5057, Ng5052 }; + assign n4147 = 32'd2 >> { Ng5041, Ng5046, Ng5037, Ng5033, n4148 }; + assign n4148 = 8'h02 >> { Ng5016, Ng5029, Ng5022 }; + assign n4149 = 32'd2147483648 >> { n4150, Ng5041, Ng5046, Ng5037, Ng5033 }; + assign n4150 = 8'h80 >> { Ng5016, Ng5029, Ng5062 }; + assign n4151 = 32'd3187523583 >> { Ng5062, Ng5022, Ng5057, n4152_1, Ng5046 }; + assign n4152_1 = 8'h1b >> { Ng5041, Ng5052, Pg84 }; + assign n1186_1 = 16'h55d5 >> { n4155, Pg35, Ng2771, n4154 }; + assign n4154 = 64'haaff2a7fa2f72277 >> { Ng2767, Ng85, Ng2775, n4157_1, n4155, Pg35 }; + assign n4155 = 8'h02 >> { Ng2724, Ng2729, n4156 }; + assign n4156 = 16'h8000 >> { Ng2741, Ng2735, Ng2748, Ng2756 }; + assign n4157_1 = 16'h5444 >> { Pg99, Ng37, Pg134, Pg113 }; + assign n1191 = 32'd4157993680 >> { Ng1886, Ng1882, n4165, n4159, Pg35 }; + assign n4159 = 8'h08 >> { n4160, Ng1862, Ng1936 }; + assign n4160 = 16'h2202 >> { Ng947, Ng1129, n4161, n4163 }; + assign n4161 = 16'h2aaa >> { Ng1171, n4162_1, Ng1183, Pg17400 }; + assign n4162_1 = 64'h0000000000000008 >> { Ng1221, Ng1205, Ng1211, Ng1216, Ng1061, Ng979 }; + assign n4163 = 16'h5515 >> { Ng2145, Ng2138, Ng2130, n4164 }; + assign n4164 = 64'h00f700f700f700ff >> { Ng1008, Ng969, Pg134, Ng209, Ng691, Ng1193 }; + assign n4165 = 4'h2 >> { n4166, Pg35 }; + assign n4166 = 32'd1920073842 >> { Ng947, Ng1129, n4167_1, Pg23683, n4163 }; + assign n4167_1 = 4'h2 >> { n4164, Ng4180 }; + assign n1196 = 32'd4158838208 >> { Ng2299, Ng2380, n4175, n4169, Pg35 }; + assign n4169 = 8'h01 >> { n4170, Ng2361, Ng2287 }; + assign n4170 = 32'd572695074 >> { Ng1514, n4174, Ng1526, Pg17404, n4171 }; + assign n4171 = 64'h5151515100515151 >> { Ng2697, Ng2689, Ng2704, Ng1291, Ng1448, n4172_1 }; + assign n4172_1 = 16'h5515 >> { Ng209, n4173, Ng691, Pg134 }; + assign n4173 = 8'ha8 >> { Ng1312, Ng1351, Ng1536 }; + assign n4174 = 64'h0000000000000008 >> { Ng1564, Ng1548, Ng1559, Ng1554, Ng1322, Ng1404 }; + assign n4175 = 4'h2 >> { n4176, Pg35 }; + assign n4176 = 32'd3638034648 >> { Ng1291, Ng1448, n4178, Ng1585, n4177_1 }; + assign n4177_1 = 16'h5515 >> { Ng2697, Ng2689, Ng2704, n4172_1 }; + assign n4178 = 4'h2 >> { n4172_1, Ng4180 }; + assign n1215 = 32'd4157993680 >> { Ng3227, Ng3243, n4181, n4180, Pg35 }; + assign n4180 = 16'h0080 >> { Ng3155, Ng3171, Ng3161, Ng3179 }; + assign n4181 = 8'ha2 >> { Ng4284, Ng4180, Pg35 }; + assign n1225 = 64'h2aff00d52aaa0080 >> { Ng3546, Ng3542, n4185, n4183, n4184, Pg35 }; + assign n4183 = 8'h01 >> { Ng3518, Ng3512, Ng3506 }; + assign n4184 = 4'h2 >> { Ng3530, Ng3522 }; + assign n4185 = 8'h08 >> { Ng4284, Ng4180, Pg35 }; + assign n1230 = 32'd4159886800 >> { Ng5232, Ng5208, n4181, n4187, Pg35 }; + assign n4187 = 16'h0008 >> { Ng5180, Ng5170, Ng5164, Ng5188 }; + assign n1240 = 8'hd8 >> { Ng2984, Ng2907, Pg35 }; + assign n1245 = 32'd4157993680 >> { Ng1736, Ng1744, n4194, n4190, Pg35 }; + assign n4190 = 8'h02 >> { n4191, Ng1802, Ng1772 }; + assign n4191 = 64'h0202020222020202 >> { Ng1171, Ng1183, n4162_1, Pg17316, n4193, n4192_1 }; + assign n4192_1 = 16'h5515 >> { Ng2138, Ng2130, Ng2145, n4164 }; + assign n4193 = 4'h2 >> { Ng947, Ng1105 }; + assign n4194 = 32'd2695014570 >> { Pg23683, n4167_1, n4193, n4192_1, Pg35 }; + assign n1250 = 32'd4159886800 >> { Ng5909, Ng5913, n4181, n4196, Pg35 }; + assign n4196 = 32'd8 >> { Ng5869, Ng5857, Ng5863, Ng5873, Ng5881 }; + assign n1255 = 32'd3389712938 >> { n4198, Ng1802, Pg35, n4191, Ng1772 }; + assign n4198 = 8'h80 >> { n4199, n4157_1, Ng112 }; + assign n4199 = 16'h0008 >> { Ng528, Ng518, n4200, Ng504 }; + assign n4200 = 16'h9009 >> { Pg73, Ng490, Pg72, Ng482 }; + assign n1260 = 64'hff7fd555ff2ad500 >> { Ng3602, Ng3554, n4181, n4184, Ng3518, Pg35 }; + assign n1265 = 16'h0a6a >> { n4203, Pg35, Ng6219, Ng6215 }; + assign n4203 = 8'h08 >> { Ng4098, Ng4093, n4204 }; + assign n4204 = 16'h8000 >> { n4157_1, n4205, Ng4087, Ng43 }; + assign n4205 = 16'h9009 >> { Pg73, Ng4104, Ng4108, Pg72 }; + assign n1270 = 32'd1688268012 >> { Pg35, n4207_1, n4213, Ng794, Ng807 }; + assign n4207_1 = 64'h8000000000000000 >> { n4208, Ng785, Ng781, Ng776, Ng772, Ng790 }; + assign n4208 = 64'h8000000000000000 >> { n4209, Ng767, Ng763, Ng758, Ng749, Ng744 }; + assign n4209 = 64'h8000000080800080 >> { Pg12184, Ng736, Pg11678, n4212_1, Ng739, n4210 }; + assign n4210 = 64'h0000000000000002 >> { Ng528, Ng490, Ng482, Ng518, Ng499, n4211 }; + assign n4211 = 16'h0080 >> { Ng370, Ng385, Ng376, Ng358 }; + assign n4212_1 = 32'd8289918 >> { Ng554, Ng807, Ng718, Ng753, Ng655 }; + assign n4213 = 8'ha2 >> { Ng736, Pg11678, Pg35 }; + assign n1299 = 16'h0a6a >> { n4215, Pg35, Ng3512, Ng3506 }; + assign n4215 = 8'h80 >> { n4216, Ng4093, Ng4098 }; + assign n4216 = 16'h0080 >> { Ng4087, n4205, n4157_1, Ng43 }; + assign n1304 = 32'd1688268012 >> { Pg35, n4209, n4213, Ng744, Ng749 }; + assign Pg27831 = 16'haa2a >> { Ng1183, Ng1171, n4162_1, Pg17291 }; + assign n1318 = 32'd4157993680 >> { Ng1604, Ng1600, n4223, n4220, Pg35 }; + assign n4220 = 8'h02 >> { n4221_1, Ng1636, Ng1592 }; + assign n4221_1 = 16'h2022 >> { Ng1135, Ng947, Pg27831, n4222 }; + assign n4222 = 16'h5551 >> { Ng2138, Ng2145, Ng2130, n4164 }; + assign n4223 = 64'h8a028a02aaaa8a02 >> { Ng947, Ng1135, Pg23683, n4167_1, n4222, Pg35 }; + assign n1323 = 16'h7d28 >> { Ng1710, n4225, Ng1714, Pg35 }; + assign n4225 = 8'h01 >> { n4221_1, Ng1592, Ng1668 }; + assign n1333 = 64'hbb3b3b3b3b3b3b3b >> { n4228, Ng2185, Ng2165, Pg35, n4227, Ng2217 }; + assign n4227 = 16'hd5f7 >> { Ng2236, n4230, n4228, Pg35 }; + assign n4228 = 64'h1110111011111110 >> { Ng2803, n4229, Ng2729, Ng2724, Ng2719, Ng2715 }; + assign n4229 = 16'h0002 >> { Ng2741, Ng2748, Ng2756, Ng2735 }; + assign n4230 = 64'h8ccc8ccc88888ccc >> { Ng2185, Ng2173, Ng2208, Ng2181, n4231_1, Ng2217 }; + assign n4231_1 = 64'h8999abbb8dddafff >> { Ng2177, Ng2161, Ng2217, Ng2169, Ng2185, Ng2208 }; + assign n1348 = 32'd4157993680 >> { Ng1740, Ng1736, n4194, n4233, Pg35 }; + assign n4233 = 8'h02 >> { n4191, Ng1772, Ng1728 }; + assign n1353 = 16'h99b8 >> { Pg35, Ng1964, n4235, Ng1968 }; + assign n4235 = 16'h2aaa >> { Ng1926, n4236_1, Ng1894, Pg35 }; + assign n4236_1 = 64'h2220222022222220 >> { Ng2783, n4229, Ng2729, Ng2724, Ng2715, Ng2719 }; + assign n2518 = 8'h08 >> { Ng4639, Pg35, n4238 }; + assign n4238 = 4'h1 >> { n4239, Ng4643 }; + assign n4239 = 8'h8a >> { n4240, n4157_1, Ng65 }; + assign n4240 = 4'h1 >> { Pg73, Pg72 }; + assign n1358 = 16'h48aa >> { Pg35, Ng4621, n4238, Ng4639 }; + assign n1363 = 32'd4159886800 >> { Ng5607, Ng5591, n4181, n4243, Pg35 }; + assign n4243 = 16'h0080 >> { Ng5535, Ng5527, Ng5517, Ng5511 }; + assign n1368 = 64'h7faaff2a5580d500 >> { Ng2657, Ng2648, Ng2652, n4245_1, n4247, Pg35 }; + assign n4245_1 = 32'd2829626024 >> { Ng2819, n4229, Ng2729, Ng2724, n4246 }; + assign n4246 = 4'h8 >> { Ng2715, Ng2719 }; + assign n4247 = 4'h2 >> { Ng2587, Ng2610 }; + assign n1373 = 64'hfafa6acafafa4aca >> { Ng528, n4251, n4249, Pg35, Ng490, Ng482 }; + assign n4249 = 8'h08 >> { Ng513, Ng518, n4250_1 }; + assign n4250_1 = 8'h08 >> { Ng376, Ng385, Ng358 }; + assign n4251 = 4'h2 >> { Ng686, Ng667 }; + assign n1383 = 32'd1868975940 >> { n4213, Ng767, Pg35, n4208, Ng772 }; + assign n1388 = 32'd4159886800 >> { Ng5587, Ng5571, n4181, n4254, Pg35 }; + assign n4254 = 16'h0002 >> { Ng5527, Ng5535, Ng5511, Ng5517 }; + assign n1393 = 32'd4005446676 >> { Ng6177, Ng6167, Pg35, Ng6173, n4256 }; + assign n4256 = 8'h2a >> { n4259, n4257, Pg35 }; + assign n4257 = 32'd715827882 >> { Ng4765, n4258, Ng4785, Ng4709, Ng4688 }; + assign n4258 = 64'h0000000000008000 >> { Ng4801, Ng4793, Ng4659, Ng4653, Ng4669, Ng4776 }; + assign n4259 = 8'h80 >> { n4260_1, Ng6381, Pg17685 }; + assign n4260_1 = 4'h8 >> { Ng6336, Ng6395 }; + assign n1402 = 64'h00aa08aa08aa08aa >> { n4262, n4204, Pg35, Ng3167, Ng3155, Ng3161 }; + assign n4262 = 4'h2 >> { Ng4093, Ng4098 }; + assign n1407 = 32'd4159886800 >> { Ng5615, Ng5599, n4181, n4264, Pg35 }; + assign n4264 = 16'h8000 >> { Ng5527, Ng5535, Ng5517, Ng5511 }; + assign n1412 = 64'hf8f8f8f8f8f870f8 >> { Pg72, Ng4575, Pg73, Ng4543, Pg35, Ng4581 }; + assign n1417 = 32'd2943330914 >> { Ng3462, n4285, Pg35, Ng3457, n4284_1 }; + assign n4267 = 64'hffffcccc000a0008 >> { n4268, n4273, n4279, n4281, n4275_1, n4277 }; + assign n4268 = 16'h0008 >> { n4269, n4271, n4272, Ng3689 }; + assign n4269 = 32'd2860548224 >> { Ng3538, Pg14451, Ng3546, Ng3680, n4270_1 }; + assign n4270_1 = 4'h1 >> { Ng3703, Ng3639 }; + assign n4271 = 64'h2222200020002000 >> { Pg16924, Ng3566, Ng3542, Pg11388, Ng3639, Ng3703 }; + assign n4272 = 64'h5777dfffdfffdfff >> { Pg16722, Ng3598, Pg13881, Ng3582, Ng3703, Ng3639 }; + assign n4273 = 64'h0090909090909090 >> { Pg16627, n4270_1, Ng3602, n4274, Pg11388, Ng3689 }; + assign n4274 = 64'h5ddd7fff7fff7fff >> { Pg13926, Ng3570, Ng3586, Pg16744, Ng3703, Ng3639 }; + assign n4275_1 = 64'h0060606060606060 >> { Ng3578, n4270_1, Pg13926, n4276, Pg11388, Ng3689 }; + assign n4276 = 64'h9dddbfffbfffbfff >> { Pg16627, Ng3610, Pg16744, Ng3594, Ng3703, Ng3639 }; + assign n4277 = 64'h0e0c0f0d0f0d0f0d >> { Ng3590, Pg13881, n4278, Ng3689, Ng3639, Ng3703 }; + assign n4278 = 16'h0777 >> { Ng3606, Pg16722, Ng3554, Pg16656 }; + assign n4279 = 32'd2860548224 >> { Pg16924, Ng3574, Pg11388, Ng3558, n4280_1 }; + assign n4280_1 = 4'h8 >> { Ng3703, Ng3639 }; + assign n4281 = 64'h2222200020002000 >> { Pg14451, Ng3550, Ng3680, Ng3562, Ng3703, Ng3639 }; + assign n4282 = 32'd2863278762 >> { Ng4975, n4283, Ng4899, Ng4944, Ng4871 }; + assign n4283 = 64'h0000000000008000 >> { Ng4991, Ng4983, Ng4843, Ng4849, Ng4859, Ng4966 }; + assign n4284_1 = 32'd2324171272 >> { Ng3614, n4282, n4267, n4285, Pg35 }; + assign n4285 = 16'h8000 >> { n4282, n4280_1, Pg16656, Ng3689 }; + assign n1422 = 32'd791285000 >> { Ng6287, Ng6271, n4185, n4287, Pg35 }; + assign n4287 = 16'h0008 >> { Ng6219, Ng6203, Ng6209, Ng6227 }; + assign n1427 = 32'd4157993680 >> { Ng2567, Ng2563, n4292, n4289_1, Pg35 }; + assign n4289_1 = 8'h02 >> { n4290, Ng2599, Ng2555 }; + assign n4290 = 32'd572662434 >> { Ng1514, Ng1526, n4174, Ng1430, n4291 }; + assign n4291 = 64'h0051515151515151 >> { Ng2689, Ng2697, Ng2704, Ng1291, Ng1300, n4172_1 }; + assign n4292 = 4'h2 >> { n4293, Pg35 }; + assign n4293 = 32'd3840147684 >> { Ng1291, Ng1300, Ng1585, n4178, n4294_1 }; + assign n4294_1 = 16'h1555 >> { Ng2697, Ng2704, Ng2689, n4172_1 }; + assign n1432 = 64'h1f2f2f2f00202020 >> { Ng4801, n4299_1, Ng4793, Pg35, n4296, Ng4776 }; + assign n4296 = 8'h80 >> { n4297, n4157_1, Ng63 }; + assign n4297 = 4'h2 >> { Ng4311, n4298 }; + assign n4298 = 16'h9009 >> { Pg73, Ng4332, Pg72, Ng4322 }; + assign n4299_1 = 4'h8 >> { n4300, Ng4669 }; + assign n4300 = 8'h80 >> { Ng4688, Ng4653, Ng4659 }; + assign n1437 = 32'd797909632 >> { Ng4584, n4303, Pg35, Ng4593, n4302 }; + assign n4302 = 8'h15 >> { Ng4616, n4303, n4239 }; + assign n4303 = 16'h8000 >> { n4304_1, Ng4332, Ng4322, Ng4584 }; + assign n4304_1 = 4'h8 >> { n4305, n4307 }; + assign n4305 = 8'h80 >> { n4306, Ng4628, Ng4340 }; + assign n4306 = 4'h2 >> { Ng4639, Ng4621 }; + assign n4307 = 4'h8 >> { Ng4358, Ng4349 }; + assign n1442 = 4'h8 >> { Pg35, Ng6199 }; + assign n1447_1 = 32'd4159886800 >> { Ng2295, Ng2299, n4175, n4310, Pg35 }; + assign n4310 = 8'h02 >> { n4170, Ng2331, Ng2287 }; + assign n1452 = 32'd2099803424 >> { Ng1351, Ng1379, Ng1384, n4312, Pg35 }; + assign n4312 = 4'h1 >> { n4313, n4314_1 }; + assign n4313 = 4'h1 >> { Ng1322, Ng1333 }; + assign n4314_1 = 4'h9 >> { Ng1322, Ng1339 }; + assign n1457_1 = 8'hd8 >> { Ng1579, Pg12923, Pg35 }; + assign n1462 = 16'h0a6a >> { n4317, Pg35, Ng5180, Ng5176 }; + assign n4317 = 8'h02 >> { Ng4093, Ng4098, n4216 }; + assign n1467_1 = 8'hd8 >> { Ng2890, Ng2844, Pg35 }; + assign n1472 = 64'hccaaccaa60aac0aa >> { n4321, Ng1002, Pg35, n6132, Ng1024, Ng1018 }; + assign n4320 = 4'h9 >> { Ng979, Ng996 }; + assign n4321 = 4'h1 >> { Ng979, Ng990 }; + assign n1477_1 = 32'd4159886800 >> { Ng5591, Ng5575, n4181, n4323, Pg35 }; + assign n4323 = 16'h0008 >> { Ng5535, Ng5511, Ng5517, Ng5527 }; + assign n1482 = 32'd4157993680 >> { Ng3582, Ng3598, n4181, n4325, Pg35 }; + assign n4325 = 8'h02 >> { Ng3522, Ng3530, n4326 }; + assign n4326 = 4'h8 >> { Ng3512, Ng3506 }; + assign n5752 = 4'h2 >> { Ng4258, Pg35 }; + assign n1487 = 8'h6a >> { Pg35, Ng4264, Ng4258 }; + assign n1492 = 64'h78d878d8705078d8 >> { Ng736, Pg11678, n4330, Ng763, Ng767, Pg35 }; + assign n4330 = 16'h8000 >> { n4209, Ng758, Ng749, Ng744 }; + assign n1497 = 4'h8 >> { Pg35, Ng5853 }; + assign n1507 = 64'hff8a7702fd887500 >> { Ng4933, Ng71, Ng4939, n4334_1, n4333, Pg35 }; + assign n4333 = 32'd286265360 >> { Pg99, Ng37, Pg134, Ng4818, Pg8132 }; + assign n4334_1 = 32'd8 >> { Ng4975, Ng4899, Ng4991, Ng4983, Ng4966 }; + assign n1517_1 = 4'h8 >> { Pg35, Ng5507 }; + assign n1522 = 32'd4159886800 >> { Ng6291, Ng6275, n4181, n4337, Pg35 }; + assign n4337 = 16'h0080 >> { Ng6203, Ng6209, Ng6219, Ng6227 }; + assign n1527_1 = 32'd1868975940 >> { n4346, Ng291, Pg35, n4339_1, Ng294 }; + assign n4339_1 = 16'h8000 >> { n4340, Ng291, Ng283, Ng287 }; + assign n4340 = 16'h2022 >> { Ng278, n4342, n4344, n4341 }; + assign n4341 = 8'h2a >> { n4212_1, n4210, Ng691 }; + assign n4342 = 16'h0080 >> { Ng269, n4343_1, Ng232, Ng246 }; + assign n4343_1 = 16'h0008 >> { Ng255, Ng262, Ng239, Ng225 }; + assign n4344 = 8'h15 >> { Ng269, n4345, Ng278 }; + assign n4345 = 64'h0000000000000008 >> { Ng239, Ng225, Ng232, Ng246, Ng262, Ng255 }; + assign n4346 = 4'h8 >> { n4340, Pg35 }; + assign n1532 = 32'd791285000 >> { Ng5559, Ng5607, n4185, n4348, Pg35 }; + assign n4348 = 8'h08 >> { Ng5535, Ng5527, Ng5523 }; + assign n1542 = 32'd989870856 >> { Pg9048, Ng559, n4350, Pg35, n4351 }; + assign n4350 = 16'h8808 >> { Pg9048, Pg12368, Ng562, Pg20763 }; + assign n4351 = 64'h3f2a3f2a2a2a3f2a >> { Pg9048, Pg12368, Pg20763, Ng626, Ng632, Ng562 }; + assign n1547 = 32'd1934654296 >> { n4356, Ng604, n4353, Pg35, Ng608 }; + assign n4353 = 16'h8000 >> { n4354, Ng604, Ng599, Ng595 }; + assign n4354 = 64'h8000000000000000 >> { n4355, Ng590, Ng582, Ng577, Ng586, Ng572 }; + assign n4355 = 8'h08 >> { n4356, n4350, Ng568 }; + assign n4356 = 4'h2 >> { Ng559, Pg9048 }; + assign n1557 = 32'd4157993680 >> { Ng3913, Ng3909, n4181, n4358, Pg35 }; + assign n4358 = 8'h80 >> { n4359, Ng3881, Ng3873 }; + assign n4359 = 8'h01 >> { Ng3863, Ng3857, Ng3869 }; + assign n1562 = 32'd4159886800 >> { Ng6259, Ng6303, n4181, n4361, Pg35 }; + assign n4361 = 8'h08 >> { Ng6219, Ng6215, Ng6227 }; + assign n1567_1 = 32'd791285000 >> { Ng5905, Ng5953, n4185, n4363, Pg35 }; + assign n4363 = 8'h08 >> { Ng5881, Ng5873, Ng5869 }; + assign n4536 = 8'h08 >> { Ng904, Pg12919, Pg35 }; + assign n1572 = 16'h48aa >> { Pg35, Ng921, Pg12919, Ng904 }; + assign n1597 = 32'd4159886800 >> { Ng5204, Ng5256, n4181, n4367_1, Pg35 }; + assign n4367_1 = 8'h02 >> { Ng5188, Ng5180, Ng5176 }; + assign n1602 = 64'hff7fd555ff2ad500 >> { Ng3590, Ng3606, n4181, n4326, n4369, Pg35 }; + assign n4369 = 4'h2 >> { Ng3522, Ng3530 }; + assign n1607 = 64'hffeedfcefdecddcc >> { Ng1926, Ng1917, Ng1932, n4236_1, n4371, Pg35 }; + assign n4371 = 8'h80 >> { n4372_1, n4374, Ng110 }; + assign n4372_1 = 32'd128 >> { Ng2741, Ng2756, n4236_1, Ng2748, n4373 }; + assign n4373 = 16'h9009 >> { Pg73, Ng2763, Ng2759, Pg72 }; + assign n4374 = 4'h8 >> { n4157_1, Pg35 }; + assign n1612 = 32'd572662434 >> { n4203, Ng6215, Ng6203, Pg35, Ng6209 }; + assign n1617 = 32'd4157993680 >> { Ng3570, Ng3586, n4181, n4377_1, Pg35 }; + assign n4377_1 = 8'h08 >> { Ng3506, Ng3512, n4184 }; + assign n1622 = 32'd1220586154 >> { Pg35, Ng283, Ng291, n4340, Ng287 }; + assign n1632 = 32'd4157993680 >> { Ng3542, Ng3570, n4181, n4380, Pg35 }; + assign n4380 = 8'h08 >> { Ng3512, n4184, Ng3506 }; + assign n1637 = 64'haa020000aa020002 >> { Ng1906, Ng1862, n4160, Ng1936, n4382_1, Pg35 }; + assign n4382_1 = 8'h80 >> { n4383, n4157_1, Ng112 }; + assign n4383 = 8'h08 >> { Ng528, Ng504, n4384 }; + assign n4384 = 4'h8 >> { n4200, Ng518 }; + assign n1642 = 32'd1219149994 >> { n4387, Pg35, Ng676, n4386_1, Ng671 }; + assign n4386_1 = 8'h2a >> { n4389, n4387, Ng703 }; + assign n4387 = 64'h0000000000008000 >> { Ng504, Ng528, n4388, Ng490, Ng482, Ng499 }; + assign n4388 = 16'h8000 >> { Ng370, Ng385, Ng376, Ng358 }; + assign n4389 = 32'd2181038210 >> { Ng655, Ng718, Ng661, Ng728, n4390 }; + assign n4390 = 16'h0008 >> { Ng645, Ng650, Ng681, Ng699 }; + assign n1652 = 64'h060caaaa040caaaa >> { Ng4311, Pg35, n4304_1, n4239, Ng4332, Ng4322 }; + assign n1662 = 64'h0cac6cac6cac6cac >> { n4393, n4307, n4257, Pg35, Ng6395, Ng6336 }; + assign n4393 = 8'h80 >> { n4297, n4157_1, Ng93 }; + assign n1667 = 32'd711592650 >> { n4395, n4356, Pg35, Ng622, Ng617 }; + assign n4395 = 64'h8000000000000000 >> { n4354, Ng604, Ng599, Ng595, Ng608, Ng613 }; + assign n1687 = 8'hae >> { Pg35, Ng2834, n4397 }; + assign n4397 = 16'ha280 >> { n4399, n4400, n4398, Pg35 }; + assign n4398 = 64'h0000000000000001 >> { Ng2741, Ng2735, Ng2748, Ng2756, Ng2724, Ng2729 }; + assign n4399 = 64'hf7b3d591e6a2c480 >> { Ng2236, Ng2504, Ng2370, Ng2638, Ng2715, Ng2719 }; + assign n4400 = 64'h084c2a6e195d3b7f >> { Ng2803, Ng2815, Ng2807, Ng2819, Ng2715, Ng2719 }; + assign n1716 = 32'd2016458936 >> { n4402, n6132, Ng1030, Pg35, Ng1036 }; + assign n4402 = 32'd1360072977 >> { Ng1002, Ng1018, Ng1024, n6132, n4321 }; + assign Pg28753 = 32'd2863311402 >> { Ng4785, Ng4709, Ng4698, n4258, Ng4646 }; + assign Pg25114 = 4'h8 >> { Ng5297, Ng5357 }; + assign n1721 = 32'd1929007320 >> { Pg21245, n6136, Ng5272, Pg28753, Pg35 }; + assign n4406_1 = 64'hfdfdfdfdfdfd00fd >> { n4409, n4414, n4410, n4412, n4413, n4407 }; + assign n4407 = 64'h50d070f070f070f0 >> { Pg14597, Ng5240, n4408, Pg25219, Ng5357, Ng5297 }; + assign n4408 = 4'h8 >> { Ng5256, Pg17639 }; + assign n4409 = 32'd2860548224 >> { Pg12238, Ng5216, Ng5232, Pg17787, Pg25114 }; + assign n4410 = 64'h0e0c0f0d0f0d0f0d >> { Pg14597, Ng5248, n4411_1, Pg25219, Ng5357, Ng5297 }; + assign n4411_1 = 16'h0777 >> { Ng5220, Ng5339, Ng5208, Pg13039 }; + assign n4412 = 64'h1111100010001000 >> { Pg13039, Ng5196, Ng5204, Ng5339, Ng5357, Ng5297 }; + assign n4413 = 64'h2222200020002000 >> { Pg17787, Ng5224, Pg12238, Ng5200, Ng5297, Ng5357 }; + assign n4414 = 64'h2222200020002000 >> { Ng5212, Pg17577, Pg17639, Ng5264, Ng5297, Ng5357 }; + assign n4415 = 8'h80 >> { Pg25114, Pg25219, Pg17577 }; + assign n4416_1 = 64'h5ddd7fff7fff7fff >> { Pg14662, Ng5228, Pg17674, Ng5244, Ng5357, Ng5297 }; + assign n1730 = 32'd4159886800 >> { Ng3239, Ng3223, n4181, n4418, Pg35 }; + assign n4418 = 16'h0008 >> { Ng3171, Ng3155, Ng3161, Ng3179 }; + assign n1740 = 64'hfddddddd08888888 >> { n4181, Ng6219, Ng6215, Ng6227, n4185, Ng6195 }; + assign n1745 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1152, n4421_1, Ng1099, Ng1135, Ng1094 }; + assign n4421_1 = 8'h08 >> { Ng1183, Ng1171, Pg13259 }; + assign n1750 = 64'h75207d287d287d28 >> { n4307, n4393, Ng6390, Ng6395, n4257, Pg35 }; + assign n1759 = 64'heaeac0eac0eac0ea >> { n4207_1, Ng794, Pg35, Ng554, n4213, Ng807 }; + assign n1769 = 4'h8 >> { Pg35, Ng3853 }; + assign n1779 = 64'hffeedfcefdecddcc >> { Ng2485, Ng2476, Ng2491, n4429, n4426_1, Pg35 }; + assign n4426_1 = 8'h80 >> { n4427, n4374, Ng110 }; + assign n4427 = 8'h08 >> { Ng2741, n4429, n4428 }; + assign n4428 = 8'h80 >> { n4373, Ng2748, Ng2756 }; + assign n4429 = 64'h2220222022222220 >> { Ng2815, n4229, Ng2729, Ng2724, Ng2715, Ng2719 }; + assign n1784 = 64'h62c0aaaac0c0aaaa >> { n4431_1, Pg35, Ng914, Pg12919, Ng925, Ng918 }; + assign n4431_1 = 32'd2147483648 >> { n4432, Pg12919, Ng911, Ng907, Ng936 }; + assign n4432 = 4'h8 >> { Ng921, Ng904 }; + assign n1794 = 32'd4159886800 >> { Ng5555, Ng5559, n4181, n4434, Pg35 }; + assign n4434 = 32'd2 >> { Ng5527, Ng5517, Ng5511, Ng5523, Ng5535 }; + assign n1799 = 64'h7f552a00ffd5aa80 >> { n4438, Ng1783, Ng1798, n4436_1, n4157_1, Pg35 }; + assign n4436_1 = 32'd128 >> { Ng2748, Ng2756, Ng2741, n4437, n4373 }; + assign n4437 = 64'h2220222022222220 >> { Ng2775, n4229, Ng2729, Ng2724, Ng2719, Ng2715 }; + assign n4438 = 8'h59 >> { Ng1783, Ng1792, Ng110 }; + assign n1804 = 32'd2100887482 >> { Ng2841, Ng4082, n4440, Ng4076, Pg35 }; + assign n4440 = 16'h8000 >> { Ng4064, Ng4082, Ng4141, Ng4057 }; + assign n1814 = 32'd791285000 >> { Ng3905, Ng3953, n4185, n4442, Pg35 }; + assign n4442 = 8'h08 >> { Ng3881, Ng3873, Ng3869 }; + assign n1819 = 32'd1868975940 >> { n4213, Ng758, Pg35, n4330, Ng763 }; + assign n1824 = 32'd4159886800 >> { Ng6255, Ng6259, n4181, n4445, Pg35 }; + assign n4445 = 32'd8 >> { Ng6215, Ng6209, Ng6203, Ng6219, Ng6227 }; + assign n1829 = 8'hd8 >> { Ng4427, Ng4423, Pg35 }; + assign n1839 = 8'hd8 >> { Ng4717, Ng4722, Pg35 }; + assign n1844 = 32'd1886924984 >> { n4449, n4356, Ng582, Pg35, Ng590 }; + assign n4449 = 4'h8 >> { n4450, Ng577 }; + assign n4450 = 8'h80 >> { n4355, Ng586, Ng572 }; + assign Pg25167 = 4'h2 >> { Ng1657, Ng1648 }; + assign n1849 = 64'h7f552a00ffd5aa80 >> { n4454, Ng1612, Ng1632, n4453, Pg25167, Pg35 }; + assign n4453 = 64'h1110111011111110 >> { Ng2771, n4229, Ng2729, Ng2724, Ng2715, Ng2719 }; + assign n4454 = 4'h2 >> { Ng1592, Ng1636 }; + assign n1868_1 = 64'h5fd7dddd0a828888 >> { Ng6159, n4257, n4259, n6139, Ng6154, Pg35 }; + assign n4456_1 = 32'd1059727914 >> { n4460, n4459, n4259, Ng6311, n4457 }; + assign n4457 = 64'h0090909090909090 >> { Pg17760, n4260_1, Ng6283, n4458, Ng6381, Pg12422 }; + assign n4458 = 64'hceeedfffdfffdfff >> { Pg17649, Ng6299, Pg14779, Ng6267, Ng6395, Ng6336 }; + assign n4459 = 64'h6666666606666666 >> { Ng6395, Ng6336, Pg17649, Ng6307, Ng6381, Pg12422 }; + assign n4460 = 64'hceeedfffdfffdfff >> { Ng6275, Pg14779, Ng6291, Pg17760, Ng6336, Ng6395 }; + assign n4461_1 = 64'h1111100010001000 >> { Ng6235, Pg13085, Ng6377, Ng6243, Ng6336, Ng6395 }; + assign n4462 = 64'h2222200020002000 >> { Pg17845, Ng6263, Pg12422, Ng6239, Ng6336, Ng6395 }; + assign n4463 = 32'd2860548224 >> { Ng6255, Pg12422, Ng6271, Pg17845, n4260_1 }; + assign n4464 = 64'h2222200020002000 >> { Ng6303, Pg17743, Pg17685, Ng6251, Ng6336, Ng6395 }; + assign n4465 = 64'h2222200020002000 >> { Pg13085, Ng6247, Ng6259, Ng6377, Ng6395, Ng6336 }; + assign n1877 = 32'd4159886800 >> { Ng5567, Ng5611, n4181, n4467, Pg35 }; + assign n4467 = 8'h08 >> { Ng5527, Ng5535, Ng5523 }; + assign n1882 = 64'hfff75d55ffa25d00 >> { Ng1756, Ng1752, n4194, n4191, n4469, Pg35 }; + assign n4469 = 4'h2 >> { Ng1728, Ng1772 }; + assign n1892 = 64'h78d878d8505078d8 >> { Ng736, Pg11678, n4209, Ng739, Ng744, Pg35 }; + assign n4471_1 = 64'h00007e007e007e00 >> { Ng554, Ng807, n4210, Ng718, Ng753, Ng655 }; + assign n1897 = 8'hd8 >> { Ng4722, Ng4737, Pg35 }; + assign n1906 = 32'd4159886800 >> { Ng6267, Ng6239, n4181, n4474, Pg35 }; + assign n4474 = 16'h0008 >> { Ng6209, Ng6227, Ng6203, Ng6219 }; + assign n1916 = 32'd3840210404 >> { Pg35, Ng5961, Ng5965, n4181, n4476_1 }; + assign n4476_1 = 16'h2aaa >> { Ng5869, Ng5881, Ng5873, Pg35 }; + assign n1002 = 32'd4201830480 >> { Pg10500, Pg12919, Ng1246, Pg17400, Pg35 }; + assign n1931 = 32'd4159886800 >> { Ng5264, Ng5248, n4181, n4479, Pg35 }; + assign n4479 = 16'h0080 >> { Ng5180, Ng5188, Ng5164, Ng5170 }; + assign n1941 = 4'h8 >> { Pg35, Ng5160 }; + assign n1946 = 32'd4157993680 >> { Ng5917, Ng5933, n4181, n4482, Pg35 }; + assign n4482 = 8'h08 >> { Ng5857, n4483, Ng5863 }; + assign n4483 = 4'h1 >> { Ng5881, Ng5873 }; + assign n1961 = 16'hee4e >> { Ng1296, Ng1306, Ng1291, Pg35 }; + assign n1966 = 4'h8 >> { Pg35, Ng3151 }; + assign n1141 = 4'h8 >> { Pg35, Ng3530 }; + assign n1981 = 32'd101493418 >> { Pg35, Ng3518, n4215, Ng3530, Ng3522 }; + assign n1986 = 32'd2143614916 >> { n4489, Ng4108, Ng4104, Pg35, Ng2841 }; + assign n4489 = 8'h80 >> { n4490, Ng4093, Ng4098 }; + assign n4490 = 8'h80 >> { n4440, Ng4087, Ng4076 }; + assign n1996 = 32'd4158838208 >> { Ng2177, Ng2181, n4495, n4492, Pg35 }; + assign n4492 = 8'h02 >> { n4493, Ng2153, Ng2197 }; + assign n4493 = 32'd572695074 >> { Ng1526, Ng1514, n4174, Pg17320, n4494 }; + assign n4494 = 64'h5151515151510051 >> { Ng2697, Ng2704, Ng2689, Ng1291, Ng1478, n4172_1 }; + assign n4495 = 64'h8a028a02aaaa8a02 >> { Ng1291, Ng1478, Ng1585, n4178, n4496_1, Pg35 }; + assign n4496_1 = 16'h5551 >> { Ng2704, Ng2697, Ng2689, n4172_1 }; + assign n2016 = 64'haa020000aa020002 >> { Ng2331, Ng2287, n4170, Ng2361, n4498, Pg35 }; + assign n4498 = 8'h80 >> { n4499, n4157_1, Ng112 }; + assign n4499 = 16'h0080 >> { Ng518, Ng504, Ng528, n4200 }; + assign n2021 = 32'd1825352362 >> { Pg35, Ng4258, Ng4264, Ng4273, Ng4269 }; + assign n2026 = 32'd2016458936 >> { n4312, Ng1351, Ng1384, Pg35, Ng1389 }; + assign n2036 = 32'd2111645832 >> { Ng5831, n4503, n4504, Ng5835, Pg35 }; + assign n4503 = 32'd2863278762 >> { Ng4785, n4258, Ng4754, Ng4709, Ng4681 }; + assign n4504 = 8'h80 >> { n4505, Pg17646, Ng6035 }; + assign n4505 = 4'h8 >> { Ng5990, Ng6049 }; + assign n2046 = 16'h6caa >> { Pg35, Ng4258, Ng4269, Ng4264 }; + assign n2056 = 32'd1434255400 >> { Ng4818, n4508, n4510, Ng4983, Pg35 }; + assign n4508 = 8'h80 >> { n4509, n4157_1, Ng63 }; + assign n4509 = 4'h8 >> { n4298, Ng4311 }; + assign n4510 = 4'h8 >> { n4511_1, Ng4859 }; + assign n4511_1 = 8'h80 >> { Ng4849, Ng4843, Ng4878 }; + assign n2061 = 32'd4159886800 >> { Ng5611, Ng5595, n4181, n4513, Pg35 }; + assign n4513 = 16'h0080 >> { Ng5527, Ng5535, Ng5517, Ng5511 }; + assign n2071 = 32'd4101812280 >> { Ng3143, Ng3133, Ng3139, Pg35, n4515 }; + assign n4515 = 8'h80 >> { Ng3179, Ng3171, Ng3167 }; + assign n2086 = 32'd4159886800 >> { Ng3235, Ng3219, n4181, n4517, Pg35 }; + assign n4517 = 16'h0008 >> { Ng3179, Ng3155, Ng3161, Ng3171 }; + assign n2091 = 64'hf8f8f8f8f8f870f8 >> { Pg72, Ng4578, Pg73, Ng4540, Pg35, Ng4581 }; + assign n2096 = 32'd4159886800 >> { Ng3566, Ng3538, n4181, n4520, Pg35 }; + assign n4520 = 16'h0002 >> { Ng3522, Ng3530, Ng3512, Ng3506 }; + assign n2106 = 32'd2315291264 >> { n4523, Ng4961, n4522, n4524, Pg35 }; + assign n4522 = 32'd715827882 >> { Ng4955, n4283, Ng4975, Ng4899, Ng4878 }; + assign n4523 = 16'h569a >> { Ng4049, Ng4045, Ng4054, Ng3990 }; + assign n4524 = 32'd128 >> { Ng4975, Ng4991, Ng4899, Ng4983, Ng4966 }; + assign n2111_1 = 8'hd8 >> { Ng4912, Ng4927, Pg35 }; + assign n2116_1 = 16'h99b8 >> { Pg35, Ng2255, n4527, Ng2259 }; + assign n4527 = 16'h2aaa >> { Ng2185, n4228, Ng2217, Pg35 }; + assign n2121 = 64'h772a5508f7aad588 >> { Ng111, Ng2819, Ng2827, n4157_1, n4529, Pg35 }; + assign n4529 = 8'h80 >> { n4156, Ng2724, Ng2729 }; + assign n1169 = 32'd4005872836 >> { Ng4392, n4531_1, Ng4382, Ng4375, Pg35 }; + assign n4531_1 = 32'd1 >> { Ng4375, Ng4405, Ng4411, Pg7257, Pg7243 }; + assign n2130 = 8'hd8 >> { Ng2844, Ng2852, Pg35 }; + assign n2135 = 16'ha280 >> { Ng417, Ng446, n4388, Pg35 }; + assign n2155 = 32'd791285000 >> { Ng5901, Ng5905, n4185, n4535, Pg35 }; + assign n4535 = 32'd2 >> { Ng5873, Ng5869, Ng5857, Ng5863, Ng5881 }; + assign n2165 = 32'd4005446676 >> { Ng3494, Ng3484, Pg35, Ng3490, n4537 }; + assign n4537 = 16'h2aaa >> { Ng3518, Ng3522, Ng3530, Pg35 }; + assign n2175 = 32'd572662434 >> { n4215, Ng3518, Ng3506, Pg35, Ng3512 }; + assign n2180 = 32'd4158838208 >> { Ng1604, Ng1687, n4223, n4225, Pg35 }; + assign n2190 = 32'd1929007320 >> { Ng4831, n6143_1, Ng5965, n4503, Pg35 }; + assign n4541_1 = 32'd2860548224 >> { Pg17819, Ng5925, Ng5909, Pg12350, n4505 }; + assign n4542 = 64'h2222200020002000 >> { Pg17715, Ng5957, Ng5905, Pg17646, Ng5990, Ng6049 }; + assign n4543 = 64'h2222200020002000 >> { Ng5901, Pg13068, Ng5913, Ng6031, Ng6049, Ng5990 }; + assign n4544 = 64'hceeedfffdfffdfff >> { Pg14738, Ng5929, Pg17739, Ng5945, Ng5990, Ng6049 }; + assign n4545 = 64'h2222200020002000 >> { Pg12350, Ng5893, Ng5917, Pg17819, Ng5990, Ng6049 }; + assign n4546_1 = 64'h1111100010001000 >> { Pg13068, Ng5889, Ng6031, Ng5897, Ng5990, Ng6049 }; + assign n2195 = 64'hff75ff20ff7dff28 >> { n4531_1, Ng4388, n4548, Ng4375, Ng4382, Pg35 }; + assign n4548 = 16'h0008 >> { Ng4392, Ng4417, n4531_1, Pg35 }; + assign n2210 = 32'd4159886800 >> { Ng3965, Ng3961, n4181, n4550, Pg35 }; + assign n4550 = 8'h80 >> { Ng3881, Ng3873, Ng3869 }; + assign n2215 = 32'd2315291264 >> { n4553, Ng4749, n4552, n4554, Pg35 }; + assign n4552 = 32'd2863278762 >> { Ng4709, n4258, Ng4785, Ng4743, Ng4674 }; + assign n4553 = 16'h396c >> { Ng5694, Ng5698, Ng5644, Ng5703 }; + assign n4554 = 32'd8 >> { Ng4785, Ng4709, Ng4801, Ng4793, Ng4776 }; + assign n2220 = 32'd4158838208 >> { Ng2008, Ng2089, n4560, n4556_1, Pg35 }; + assign n4556_1 = 8'h01 >> { n4557, Ng1996, Ng2070 }; + assign n4557 = 16'h2022 >> { Ng956, Ng947, n4558, n4559 }; + assign n4558 = 16'haaa2 >> { Ng1183, Ng1171, n4162_1, Ng1087 }; + assign n4559 = 16'h1555 >> { Ng2145, Ng2130, Ng2138, n4164 }; + assign n4560 = 4'h2 >> { n4561_1, Pg35 }; + assign n4561_1 = 32'd3840147684 >> { Ng947, Ng956, Pg23683, n4167_1, n4559 }; + assign n2229 = 32'd4159886800 >> { Ng3933, Ng3917, n4181, n4563, Pg35 }; + assign n4563 = 16'h0002 >> { Ng3881, Ng3873, Ng3857, Ng3863 }; + assign n2254 = 64'hd850d850fa72d850 >> { n4567, Ng2421, Ng2465, Ng2472, n4565, Pg35 }; + assign n4565 = 32'd2720145954 >> { Ng1526, n4174, Ng1514, Pg17423, n4566_1 }; + assign n4566_1 = 64'h5151515100515151 >> { Ng2704, Ng2697, Ng2689, Ng1291, Ng1472, n4172_1 }; + assign n4567 = 8'h80 >> { n4568, n4157_1, Ng112 }; + assign n4568 = 8'h80 >> { n4384, Ng504, Ng528 }; + assign n2259 = 32'd789391880 >> { Ng5881, Ng5889, n4185, n4570, Pg35 }; + assign n4570 = 16'h0002 >> { Ng5869, Ng5857, Ng5863, n4483 }; + assign n2264 = 64'hf8f8f8f8f8f870f8 >> { Pg72, Ng4572, Pg73, Ng4480, Pg35, Ng4581 }; + assign n1149 = 4'h8 >> { Pg35, Ng3179 }; + assign n2274 = 64'h505078d878d878d8 >> { n4204, n4262, Ng3167, Ng3171, Ng3179, Pg35 }; + assign n2279 = 64'haa020000aa020002 >> { Ng1772, Ng1728, n4191, Ng1802, n4198, Pg35 }; + assign n2284 = 32'd4158838208 >> { Ng2433, Ng2514, n4577, n4576_1, Pg35 }; + assign n4576_1 = 8'h01 >> { n4565, Ng2421, Ng2495 }; + assign n4577 = 64'h8a028a02aaaa8a02 >> { Ng1291, Ng1472, Ng1585, n4178, n4578, Pg35 }; + assign n4578 = 16'h5515 >> { Ng2704, Ng2689, Ng2697, n4172_1 }; + assign n2289 = 32'd2111645832 >> { Ng3831, n4522, n4580, Ng3835, Pg35 }; + assign n4580 = 8'h80 >> { n4581_1, Pg16693, Ng4040 }; + assign n4581_1 = 4'h8 >> { Ng3990, Ng4054 }; + assign n2299 = 4'h8 >> { Pg35, Ng4917 }; + assign n2304 = 32'd111807658 >> { n4588, Pg35, n4584, Ng1070, Ng1199 }; + assign n4584 = 16'h22a2 >> { Ng1171, Ng1183, Ng1193, n4585 }; + assign n4585 = 16'h8808 >> { Ng969, n4586_1, n4587, Pg7916 }; + assign n4586_1 = 32'd357913941 >> { Ng1002, Ng1036, n4320, Ng1024, Ng1008 }; + assign n4587 = 8'h08 >> { Ng1189, Ng1178, Ng996 }; + assign n4588 = 16'h0008 >> { n4587, Ng1171, Ng1183, Pg7916 }; + assign n2309 = 64'h28888888f8f8f8f8 >> { Pg35, n4388, Ng817, Ng832, Ng822, n4590 }; + assign n4590 = 16'h22a2 >> { Ng812, Ng837, Ng847, Pg35 }; + assign n2314 = 32'd2069394256 >> { Pg12919, Ng911, n4431_1, Pg35, Ng914 }; + assign n2333 = 8'h5d >> { Pg35, Ng2815, n4593 }; + assign n4593 = 64'hddff5d7fd5f75577 >> { Ng2811, Ng111, Ng2807, n4157_1, n4594, Pg35 }; + assign n4594 = 8'h08 >> { Ng2729, Ng2724, n4156 }; + assign n2338 = 64'h75207d287d287d28 >> { n4307, n4596_1, Ng4049, Ng4054, n4522, Pg35 }; + assign n4596_1 = 8'h80 >> { n4509, n4157_1, Ng93 }; + assign n2343 = 32'd4005446676 >> { Ng6191, Ng6181, Pg35, Ng6187, n4598 }; + assign n4598 = 16'h2aaa >> { Ng6227, Ng6219, Ng6215, Pg35 }; + assign n2353 = 32'd572662434 >> { n4600, Ng5523, Ng5511, Pg35, Ng5517 }; + assign n4600 = 8'h02 >> { Ng4093, Ng4098, n4204 }; + assign n2362 = 32'd4159886800 >> { Ng6637, Ng6621, n4181, n4602, Pg35 }; + assign n4602 = 16'h0080 >> { Ng6549, Ng6565, Ng6555, Ng6573 }; + assign n2372 = 64'hdd88dd88d782d70a >> { n4221_1, Ng1592, Ng1668, n4604, Ng1682, Pg35 }; + assign n4604 = 32'd1313734734 >> { Ng947, Ng1135, Ng1246, n4167_1, n4222 }; + assign n2386 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1152, n4606_1, Ng1099, Ng1105, Ng1111 }; + assign n4606_1 = 8'h08 >> { Ng1171, Ng1183, Pg13259 }; + assign n2396 = 32'd4159886800 >> { Ng6307, Ng6291, n4181, n4608, Pg35 }; + assign n4608 = 16'h8000 >> { Ng6219, Ng6209, Ng6203, Ng6227 }; + assign n2410 = 32'd2096380080 >> { Ng2255, Ng2246, Ng2250, Pg35, n4610 }; + assign n4610 = 8'h08 >> { Ng2185, Ng2208, n4228 }; + assign n2415 = 8'h5d >> { Pg35, Ng2819, n4612 }; + assign n4612 = 64'hddff5d7fd5f75577 >> { Ng2823, Ng111, Ng2815, n4157_1, n4613, Pg35 }; + assign n4613 = 8'h08 >> { Ng2724, n4156, Ng2729 }; + assign n2420 = 64'h48c0c0c0aaaaaaaa >> { Pg35, n4432, Ng936, Ng911, Pg12919, Ng907 }; + assign n2430 = 32'd4157993680 >> { Ng1752, Ng1748, n4194, n4616_1, Pg35 }; + assign n4616_1 = 8'h08 >> { n4191, Ng1802, Ng1728 }; + assign n2435 = 32'd4159886800 >> { Ng5551, Ng5603, n4181, n4618, Pg35 }; + assign n4618 = 8'h02 >> { Ng5527, Ng5535, Ng5523 }; + assign n2440 = 32'd789391880 >> { Ng3562, Ng3558, n4185, n4620, Pg35 }; + assign n4620 = 8'h80 >> { n4183, Ng3522, Ng3530 }; + assign n2445 = 32'd4005446676 >> { Ng5499, Ng5489, Pg35, Ng5495, n4622 }; + assign n4622 = 16'h2aaa >> { Ng5523, Ng5527, Ng5535, Pg35 }; + assign n2450 = 8'hd8 >> { Ng2950, Ng2960, Pg35 }; + assign n2455 = 32'd4157993680 >> { Ng3905, Ng3901, n4181, n4625, Pg35 }; + assign n4625 = 8'h08 >> { Ng3873, Ng3881, n4359 }; + assign n2465 = 32'd791285000 >> { Ng6251, Ng6299, n4185, n4627, Pg35 }; + assign n4627 = 8'h08 >> { Ng6227, Ng6215, Ng6219 }; + assign n2470 = 32'd2099803424 >> { n4630, Ng1367, Ng1373, n4629, Pg35 }; + assign n4629 = 32'd1360072977 >> { Ng1345, Ng1367, Ng1361, n4630, n4313 }; + assign n4630 = 64'h0222222212323232 >> { Ng1389, Ng1361, Ng1373, Ng1351, Ng1312, n4314_1 }; + assign n2475 = 32'd1868975940 >> { n4635, Ng153, Pg35, n4632, Ng157 }; + assign n4632 = 16'h8000 >> { n4633, Ng153, Ng150, Ng164 }; + assign n4633 = 64'h0000000000000080 >> { Ng168, Ng174, Ng182, n4341, n4634, Ng146 }; + assign n4634 = 8'h08 >> { Ng513, Ng518, Ng203 }; + assign n4635 = 64'h0808080808080888 >> { Ng182, Ng168, Ng174, n4634, Pg35, n4341 }; + assign n2480 = 8'h5d >> { Pg35, Ng2787, n4637 }; + assign n4637 = 64'hddff5d7fd5f75577 >> { Ng2791, Ng85, Ng2783, n4157_1, n4613, Pg35 }; + assign n2489 = 32'd4157993680 >> { Ng3550, Ng3574, n4181, n4639, Pg35 }; + assign n4639 = 8'h08 >> { Ng3512, n4369, Ng3506 }; + assign n2494 = 32'd4101812280 >> { Ng2112, Ng2102, Ng2108, Pg35, n4556_1 }; + assign n2504 = 32'd4201830480 >> { Ng433, Ng269, Ng437, n4388, Pg35 }; + assign n2513 = 64'h64a0a0a0ecececec >> { Pg35, n4209, Ng744, n4213, Ng749, Ng758 }; + assign n2523 = 32'd4101812280 >> { Ng6537, Ng6527, Ng6533, Pg35, n4644 }; + assign n4644 = 8'h80 >> { Ng6573, Ng6565, Ng6561 }; + assign n2528 = 32'd791285000 >> { Ng5543, Ng5535, n4185, n4646_1, Pg35 }; + assign n4646_1 = 32'd1 >> { Ng5527, Ng5535, Ng5517, Ng5511, Ng5523 }; + assign n2533 = 32'd791285000 >> { Ng5961, Ng5945, n4185, n4648, Pg35 }; + assign n4648 = 16'h8000 >> { Ng5881, Ng5873, Ng5857, Ng5863 }; + assign n2538 = 32'd4159886800 >> { Ng6243, Ng6295, n4181, n4650, Pg35 }; + assign n4650 = 8'h02 >> { Ng6219, Ng6227, Ng6215 }; + assign n2543 = 32'd711592650 >> { n4652, n4356, Pg35, Ng632, Ng626 }; + assign n4652 = 8'h80 >> { n4395, Ng617, Ng622 }; + assign n2548 = 64'hf5f5f7f5e4e4c4e4 >> { n4181, Ng3873, n4359, Ng3889, Ng3881, Pg35 }; + assign n2558 = 64'hd7ddd2d88288d2d8 >> { Ng1664, Pg35, Ng1657, Ng1648, Ng110, n4655 }; + assign n4655 = 64'h0000000000000080 >> { Ng2741, Ng2748, Ng2756, n4374, n4453, n4373 }; + assign n2563 = 8'hd8 >> { Pg23683, Pg12919, Pg35 }; + assign n2568 = 32'd4159886800 >> { Ng6629, Ng6613, n4181, n4658, Pg35 }; + assign n4658 = 16'h0008 >> { Ng6573, Ng6549, Ng6555, Ng6565 }; + assign n2573 = 32'd4268940368 >> { Ng269, Pg14167, Ng246, n4661_1, n4660 }; + assign n4660 = 16'h555d >> { Ng896, Ng862, Ng890, Pg35 }; + assign n4661_1 = 16'h0008 >> { Ng896, Ng862, Pg35, Ng890 }; + assign n1165 = 32'd4005872836 >> { Ng4392, n4663, Ng4382, Ng4438, Pg35 }; + assign n4663 = 32'd1 >> { Ng4452, Ng4438, Ng4443, Pg7245, Pg7260 }; + assign n4664 = 64'h084c2a6e195d3b7f >> { Ng4722, Ng4732, Ng4717, Ng4727, Ng4785, Ng4709 }; + assign n4665 = 64'hf351f351f351e240 >> { Ng4681, Ng4646, Ng4821, Ng4826, Ng4688, Ng4674 }; + assign n2588 = 8'hae >> { Pg35, Pg20049, n6660 }; + assign n2593 = 32'd2143614916 >> { n4490, Ng4093, Ng4098, Pg35, Ng2841 }; + assign n2598 = 64'hf8f8f8f8f8f870f8 >> { Pg72, Pg20049, Pg73, Ng4495, Pg35, Ng4581 }; + assign n2622 = 64'h060c0c0caaaaaaaa >> { Pg35, n4304_1, Ng4322, n4239, Ng4584, Ng4332 }; + assign n2627 = 64'h64a0a0a0ecececec >> { Pg35, n4339_1, Ng294, n4346, Ng298, Ng142 }; + assign n2632 = 32'd4005446676 >> { Ng5831, Ng5821, Pg35, Ng5827, n4672 }; + assign n4672 = 8'h2a >> { n4504, n4503, Pg35 }; + assign n2637 = 32'd4268940368 >> { Ng262, Pg14125, Ng239, n4661_1, n4660 }; + assign n2657 = 32'd2099803424 >> { n6132, Ng1024, Ng1030, n4402, Pg35 }; + assign n2662 = 32'd4159886800 >> { Ng3231, Ng3215, n4181, n4676_1, Pg35 }; + assign n4676_1 = 16'h0002 >> { Ng3179, Ng3171, Ng3155, Ng3161 }; + assign n2675 = 64'hdd88dd88d782d70a >> { n4493, Ng2153, Ng2227, n4678, Ng2241, Pg35 }; + assign n4678 = 32'd1313734734 >> { Ng1291, Ng1478, Ng1589, n4178, n4496_1 }; + assign n2680 = 16'h6caa >> { Pg35, Ng1430, Ng1564, Ng1548 }; + assign n2689 = 32'd4159886800 >> { Ng6649, Ng6633, n4181, n4681_1, Pg35 }; + assign n4681_1 = 16'h0080 >> { Ng6565, Ng6573, Ng6555, Ng6549 }; + assign n2699 = 32'd4268940368 >> { Ng872, Pg14189, Ng225, n4661_1, n4660 }; + assign n2709 = 64'hf8f8f8f8f8f870f8 >> { Pg73, Pg20049, Pg72, Ng4501, Pg35, Ng4581 }; + assign n2714 = 16'h0a6a >> { n4685, Pg35, Ng5873, Ng5869 }; + assign n4685 = 8'h08 >> { Ng4098, Ng4093, n4216 }; + assign n2719 = 64'h3a3a6a2a9a1aca0a >> { n4150, n4148, n4151, Pg35, Ng5037, Ng5033 }; + assign n2724 = 64'hffeedfcefdecddcc >> { Ng2319, n4691_1, Ng2327, n4690, n4688, Pg35 }; + assign n4688 = 8'h80 >> { n4689, n4374, Ng110 }; + assign n4689 = 32'd32768 >> { Ng2748, n4373, Ng2741, n4690, Ng2756 }; + assign n4690 = 64'h2220222022222220 >> { Ng2807, n4229, Ng2729, Ng2724, Ng2719, Ng2715 }; + assign n4691_1 = 4'h1 >> { n4692, Ng2351 }; + assign n4692 = 4'h2 >> { Ng2319, Ng2342 }; + assign n2734 = 32'd791285000 >> { Ng5208, Ng5212, n4185, n4694, Pg35 }; + assign n4694 = 32'd2 >> { Ng5180, Ng5164, Ng5170, Ng5176, Ng5188 }; + assign n2739 = 32'd4159886800 >> { Ng5579, Ng5555, n4181, n4696_1, Pg35 }; + assign n4696_1 = 16'h0008 >> { Ng5527, Ng5517, Ng5535, Ng5511 }; + assign n2744 = 32'd572662434 >> { n4685, Ng5869, Ng5857, Pg35, Ng5863 }; + assign n2749 = 8'hd8 >> { Ng1585, Pg12923, Pg35 }; + assign n2759 = 32'd4159886800 >> { Ng6279, Ng6263, n4181, n4700, Pg35 }; + assign n4700 = 16'h0002 >> { Ng6219, Ng6203, Ng6227, Ng6209 }; + assign n2764 = 32'd4157993680 >> { Ng5889, Ng5917, n4181, n4702, Pg35 }; + assign n4702 = 8'h08 >> { Ng5863, Ng5857, n4483 }; + assign n2774 = 16'h99b8 >> { Pg35, Ng6163, n4598, Ng6167 }; + assign n2779 = 64'hd850d850fa72d850 >> { n4705, Ng2555, Ng2599, Ng2606, n4290, Pg35 }; + assign n4705 = 8'h80 >> { n4706_1, n4157_1, Ng112 }; + assign n4706_1 = 8'h08 >> { Ng504, n4384, Ng528 }; + assign n2784 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1495, n4708, Ng1442, Ng1448, Ng1454 }; + assign n4708 = 8'h08 >> { Ng1514, Ng1526, Pg13272 }; + assign n2789 = 8'hd5 >> { n4710, Ng2299, n4711_1 }; + assign n4710 = 8'h80 >> { n4690, Ng2319, Ng2351 }; + assign n4711_1 = 32'd2365959975 >> { Ng2370, n4712, Ng2351, n4690, Pg35 }; + assign n4712 = 64'h8ccc8ccc88888ccc >> { Ng2351, Ng2307, Ng2295, Ng2342, n4713, Ng2319 }; + assign n4713 = 64'h8a9b9b9b8adfdfdf >> { Ng2303, Ng2319, Ng2311, Ng2315, Ng2351, Ng2342 }; + assign n2803 = 64'h64a0a0a0ecececec >> { Pg35, n4633, Ng164, n4635, Ng150, Ng153 }; + assign n2813 = 32'd796954496 >> { n4440, Ng4076, Pg35, Ng4087, Ng2841 }; + assign n2818 = 64'h040caaaa060caaaa >> { Ng4776, Pg35, n4299_1, n4296, Ng4801, Ng4793 }; + assign n2828_1 = 32'd4159886800 >> { Ng3961, Ng3945, n4181, n4718, Pg35 }; + assign n4718 = 16'h8000 >> { Ng3881, Ng3873, Ng3863, Ng3857 }; + assign n2843 = 32'd4159886800 >> { Ng6625, Ng6609, n4181, n4720, Pg35 }; + assign n4720 = 16'h0002 >> { Ng6573, Ng6565, Ng6549, Ng6555 }; + assign n2853 = 32'd3099097136 >> { n4321, n6132, Ng1002, Pg35, Ng1018 }; + assign n2868 = 64'hf5ffb1bbe4eea0aa >> { Ng2441, Ng2461, Ng2465, Ng2421, Pg35, n4723 }; + assign n4723 = 16'h0080 >> { Ng2485, Pg35, n4429, Ng2476 }; + assign n2873 = 32'd2146904738 >> { Ng2748, n4725, Ng2756, Ng2841, Pg35 }; + assign n4725 = 8'h80 >> { n4726_1, Ng2741, Ng2748 }; + assign n4726_1 = 16'h8000 >> { n4246, Ng2735, Ng2724, Ng2729 }; + assign n2878 = 64'h0cac6cac6cac6cac >> { n4393, n4728, n4503, Pg35, Ng6049, Ng5990 }; + assign n4728 = 4'h2 >> { Ng4349, Ng4358 }; + assign n2883 = 32'd2069394256 >> { Pg12923, Ng1252, n4730, Pg35, Ng1256 }; + assign n4730 = 32'd2147483648 >> { Pg12923, Ng1252, Ng1266, Ng1249, Ng1280 }; + assign n2888 = 64'h3a3a6a2a9a1aca0a >> { Ng5062, Ng5022, n4151, Pg35, Ng5029, Ng5016 }; + assign n2898 = 64'hdd88dd88d782d70a >> { n4191, Ng1728, Ng1802, n4733, Ng1816, Pg35 }; + assign n4733 = 16'h3210 >> { Ng1246, n4167_1, n4193, n4192_1 }; + assign n4734 = 64'h084c2a6e195d3b7f >> { Ng4912, Ng4922, Ng4907, Ng4917, Ng4975, Ng4899 }; + assign n4735 = 16'h0001 >> { Ng4871, Ng4878, Ng4864, Ng4836 }; + assign n4736_1 = 64'haaaaa222a222a222 >> { Ng5011, Ng4836, Ng4871, Ng3684, n4737, Pg35 }; + assign n4737 = 32'd1162149957 >> { Ng3333, Ng4864, Ng4878, Ng4035, n4735 }; + assign n2908 = 8'hae >> { Pg35, Ng4572, n2066 }; + assign n2918 = 32'd4005446676 >> { Ng3831, Ng3821, Pg35, Ng3827, n4740 }; + assign n4740 = 8'h2a >> { n4580, n4522, Pg35 }; + assign n2928 = 64'h0cac6cac6cac6cac >> { n4596_1, n4743, n4742, Pg35, Ng3352, Ng3288 }; + assign n4742 = 32'd2863278762 >> { Ng4899, n4283, Ng4975, Ng4933, Ng4864 }; + assign n4743 = 4'h2 >> { Ng4358, Ng4349 }; + assign n2933 = 32'd4005446676 >> { Ng2403, Ng2393, Pg35, Ng2399, n4745 }; + assign n4745 = 16'haaa8 >> { Ng2287, n4170, Ng2361, Pg35 }; + assign n2938 = 8'hd8 >> { Ng2138, Ng2145, Pg35 }; + assign n2943 = 16'h99b8 >> { Pg35, Ng1696, n4748, Ng1700 }; + assign n4748 = 16'h2aaa >> { Ng1624, n4453, Ng1657, Pg35 }; + assign n2948 = 32'd1928483024 >> { Ng513, n4251, Ng504, n4250_1, Pg35 }; + assign n2957 = 64'h0cac6cac6cac6cac >> { n4393, n4751_1, Pg28753, Pg35, Ng5357, Ng5297 }; + assign n4751_1 = 4'h1 >> { Ng4358, Ng4349 }; + assign n2962 = 64'h7fc4f7c4f7c4f7c4 >> { n4725, Ng2756, Ng2759, Ng2763, Pg35, Ng2841 }; + assign n2967 = 32'd1434255400 >> { Ng4818, n4296, n4299_1, Ng4793, Pg35 }; + assign n2972 = 16'hee4e >> { Ng952, Ng962, Ng947, Pg35 }; + assign n2977 = 32'd1655357610 >> { n4756, Pg35, Pg12923, Ng1263, Ng1259 }; + assign n4756 = 4'h8 >> { n4730, Ng1256 }; + assign n2982 = 64'hdd88dd88d782d70a >> { n4160, Ng1862, Ng1936, n4758, Ng1950, Pg35 }; + assign n4758 = 32'd1920073842 >> { Ng947, Ng1129, n4167_1, Ng1246, n4163 }; + assign n2987 = 32'd4005446676 >> { Ng5138, Ng5128, Pg35, Ng5134, n4760 }; + assign n4760 = 8'h2a >> { n4415, Pg28753, Pg35 }; + assign n2992 = 32'd4159886800 >> { Ng2307, Ng2311, n4175, n4762, Pg35 }; + assign n4762 = 8'h08 >> { n4170, Ng2361, Ng2287 }; + assign n3001 = 64'h55750020557d0028 >> { Ng4669, Ng4659, n4296, Ng4664, n4300, Pg35 }; + assign n3006 = 64'hd7ddd2d88288d2d8 >> { Ng2223, Pg35, Ng2217, Ng2208, Ng110, n4765_1 }; + assign n4765_1 = 64'h0000000000008000 >> { Ng2741, Ng2748, n4373, n4374, n4228, Ng2756 }; + assign n3011 = 64'h5fd7dddd0a828888 >> { Ng5813, n4503, n4504, n6143_1, Ng5808, Pg35 }; + assign n3016 = 32'd4159886800 >> { Ng6645, Ng6629, n4181, n4768, Pg35 }; + assign n4768 = 16'h0080 >> { Ng6573, Ng6565, Ng6555, Ng6549 }; + assign n3021 = 32'd4159886800 >> { Ng2016, Ng2020, n4560, n4770_1, Pg35 }; + assign n4770_1 = 8'h08 >> { n4557, Ng1996, Ng2070 }; + assign n3026 = 16'h0a6a >> { n4772, Pg35, Ng3873, Ng3869 }; + assign n4772 = 8'h80 >> { n4204, Ng4093, Ng4098 }; + assign n3031 = 32'd4159886800 >> { Ng2315, Ng2303, n4175, n4774, Pg35 }; + assign n4774 = 8'h02 >> { n4170, Ng2331, Ng2361 }; + assign n3036 = 64'hf222f222fffff222 >> { Pg35, Ng2799, Ng2811, n4777, Ng2327, n4776 }; + assign n4776 = 16'h2220 >> { Ng2756, Ng2748, n4156, Pg35 }; + assign n4777 = 16'haaa2 >> { Ng2748, Ng2756, Ng2741, Pg35 }; + assign n3041 = 32'd4159886800 >> { Ng5957, Ng5941, n4181, n4779, Pg35 }; + assign n4779 = 16'h0080 >> { Ng5873, Ng5881, Ng5857, Ng5863 }; + assign n3046 = 64'hffd5aa807f552a00 >> { n4782, Ng1996, Ng2047, n4781, n4157_1, Pg35 }; + assign n4781 = 16'h0008 >> { Ng504, Ng528, n4384, n4558 }; + assign n4782 = 4'h6 >> { n4783, Ng112 }; + assign n4783 = 4'h2 >> { Ng2040, Ng2070 }; + assign n3051 = 32'd572662434 >> { n4772, Ng3869, Ng3857, Pg35, Ng3863 }; + assign n3056 = 32'd4159886800 >> { Ng5575, Ng5547, n4181, n4786, Pg35 }; + assign n4786 = 16'h0008 >> { Ng5535, Ng5517, Ng5527, Ng5511 }; + assign n3071 = 32'd4159886800 >> { Ng3917, Ng3889, n4181, n4788, Pg35 }; + assign n4788 = 16'h0002 >> { Ng3881, Ng3873, Ng3863, Ng3857 }; + assign n3080 = 32'd3940737762 >> { Ng4392, n4531_1, Ng4411, Pg35, Ng4401 }; + assign n3085 = 32'd4159886800 >> { Ng6275, Ng6255, n4181, n4791, Pg35 }; + assign n4791 = 16'h0080 >> { Ng6209, Ng6219, Ng6203, Ng6227 }; + assign n3090 = 32'd3840210404 >> { Pg35, Ng6307, Ng6311, n4181, n4598 }; + assign n3095 = 32'd2099803424 >> { Ng1008, Ng1036, Ng1041, n4794, Pg35 }; + assign n4794 = 4'h1 >> { n4321, n4320 }; + assign n3100 = 64'h7f552a00ffd5aa80 >> { n4797, Ng2575, Ng2595, n4245_1, n4796, Pg35 }; + assign n4796 = 4'h2 >> { Ng2619, Ng2610 }; + assign n4797 = 4'h2 >> { Ng2555, Ng2599 }; + assign n3105 = 32'd4005446676 >> { Ng2537, Ng2527, Pg35, Ng2533, n4799 }; + assign n4799 = 16'haaa8 >> { Ng2495, n4565, Ng2421, Pg35 }; + assign n3114 = 32'd3940737762 >> { Ng4392, n4663, Ng4443, Pg35, Ng4434 }; + assign n3124 = 32'd1929007320 >> { Ng4826, n6139, Ng6311, n4257, Pg35 }; + assign n3129 = 32'd791285000 >> { Ng6239, Ng6243, n4185, n4803, Pg35 }; + assign n4803 = 32'd2 >> { Ng6215, Ng6209, Ng6203, Ng6227, Ng6219 }; + assign n3134 = 32'd4268940368 >> { Ng255, Pg14217, Ng232, n4661_1, n4660 }; + assign n3139 = 32'd4159886800 >> { Ng5268, Ng5252, n4181, n4806, Pg35 }; + assign n4806 = 16'h8000 >> { Ng5188, Ng5180, Ng5164, Ng5170 }; + assign n3144 = 4'h8 >> { Pg35, Ng6545 }; + assign n3149 = 32'd4101812280 >> { Ng2417, Ng2407, Ng2413, Pg35, n4710 }; + assign n3154 = 64'hd850d850fa72d850 >> { n4198, Ng1728, Ng1772, Ng1779, n4191, Pg35 }; + assign n3159 = 64'h777d332877753320 >> { n4151, Ng5046, n4149, n4147, Ng5052, Pg35 }; + assign n3164 = 64'hf755a200ff5daa08 >> { n4166, Ng1878, Ng1890, n4160, n4812, Pg35 }; + assign n4812 = 4'h2 >> { Ng1906, Ng1936 }; + assign n3169 = 32'd3389712938 >> { n4705, Ng2629, Pg35, n4290, Ng2599 }; + assign n3174 = 32'd111807658 >> { n4350, Pg35, n4356, Ng572, Ng568 }; + assign n3179 = 4'h8 >> { Pg35, Ng2130 }; + assign n3184 = 32'd2100887482 >> { Ng2841, Ng4098, n4489, Ng4108, Pg35 }; + assign n3193 = 32'd4201830480 >> { Ng475, Ng246, Ng424, n4388, Pg35 }; + assign n955 = 4'h8 >> { Pg35, Pg64 }; + assign n971 = 8'hd8 >> { Ng753, Pg64, Pg35 }; + assign n3207 = 64'h0cac6cac6cac6cac >> { n4596_1, n4307, n4522, Pg35, Ng4054, Ng3990 }; + assign n1034 = 4'h8 >> { Pg35, Ng5881 }; + assign n3212 = 32'd101493418 >> { Pg35, Ng5869, n4685, Ng5881, Ng5873 }; + assign n3217 = 32'd4005446676 >> { Ng1992, Ng1982, Pg35, Ng1988, n4235 }; + assign n3222 = 32'd1147956332 >> { n4204, n4262, Ng3171, Ng3167, Pg35 }; + assign n3227 = 64'h48c0c0c0aaaaaaaa >> { Pg35, n4388, Ng847, Ng812, Ng837, Ng843 }; + assign n3232 = 32'd1219149994 >> { n4388, Pg35, Ng832, n4827, Ng817 }; + assign n4827 = 8'h5d >> { Ng812, Ng837, Ng847 }; + assign n3237_1 = 64'hff7fd555ff2ad500 >> { Ng5949, Ng5897, n4181, n4483, Ng5869, Pg35 }; + assign n3256 = 64'hf4f4f4f4f4f4f4f6 >> { Ng26885, Ng311, Ng305, n4830_1, Ng329, Pg35 }; + assign n4830_1 = 64'ha820a820a800a020 >> { Ng26885, Ng336, Ng305, Ng311, Ng324, Pg35 }; + assign n3266 = 64'hbfbb3f33afaa2f22 >> { Ng2811, Ng2823, n4776, Ng2461, Pg35, n4777 }; + assign n3271 = 32'd3705470684 >> { n4282, Ng3684, Ng3614, n4284_1, Pg35 }; + assign n3276 = 32'd111807658 >> { n4282, Pg35, n4834, Ng3639, Ng3703 }; + assign n4834 = 8'h80 >> { n4596_1, n4282, n4728 }; + assign n3291 = 32'd4268940368 >> { Ng239, Pg14147, Ng269, n4661_1, n4660 }; + assign n3311_1 = 64'h5fd7dddd0a828888 >> { Ng3813, n4522, n4580, n6156, Ng3808, Pg35 }; + assign n4837 = 32'd2004317959 >> { n4844, n4845_1, n4842, n4840_1, n4838 }; + assign n4838 = 32'd3657169915 >> { Ng3933, Pg13906, n4839, Ng4054, Ng3990 }; + assign n4839 = 16'h0777 >> { Ng3893, Pg11418, Ng3917, Pg16955 }; + assign n4840_1 = 64'h7060f0e0f0e0f0e0 >> { Pg16748, Ng3949, n4841, Ng4040, Ng4054, Ng3990 }; + assign n4841 = 16'h0777 >> { Ng3897, Ng4031, Ng3889, Pg14518 }; + assign n4842 = 64'h0e0c0f0d0f0d0f0d >> { Pg13906, Ng3941, n4843, Ng4040, Ng4054, Ng3990 }; + assign n4843 = 16'h0777 >> { Ng3901, Pg14518, Ng3913, Ng4031 }; + assign n4844 = 32'd2860548224 >> { Pg16955, Ng3925, Ng3909, Pg11418, n4581_1 }; + assign n4845_1 = 64'h2222200020002000 >> { Pg16748, Ng3957, Ng3905, Pg16693, Ng3990, Ng4054 }; + assign n4846 = 64'hceeedfffdfffdfff >> { Pg13966, Ng3929, Ng3945, Pg16775, Ng3990, Ng4054 }; + assign n3321_1 = 32'd4159886800 >> { Ng3957, Ng3941, n4181, n4848, Pg35 }; + assign n4848 = 16'h0080 >> { Ng3873, Ng3881, Ng3863, Ng3857 }; + assign n3326 = 32'd797909632 >> { Ng4087, n4490, Pg35, Ng4093, Ng2841 }; + assign n3331 = 16'hdfdd >> { Ng1768, Pg35, n4851, n4852 }; + assign n4851 = 8'h80 >> { n4436_1, n4374, Ng110 }; + assign n4852 = 32'd3590313463 >> { Ng1783, Ng1760, Ng1792, n4437, Pg35 }; + assign n3336_1 = 32'd1868975940 >> { n4635, Ng157, Pg35, n4854, Ng160 }; + assign n4854 = 32'd2147483648 >> { n4633, Ng153, Ng157, Ng150, Ng164 }; + assign n3346 = 64'hfddddddd08888888 >> { n4181, Ng3522, Ng3530, Ng3518, n4185, Ng3498 }; + assign n3351 = 32'd711592650 >> { n4355, n4356, Pg35, Ng586, Ng572 }; + assign n3356 = 64'hffeedfcefdecddcc >> { Ng2619, Ng2610, Ng2625, n4245_1, n4858, Pg35 }; + assign n4858 = 8'h80 >> { n4859, n4374, Ng110 }; + assign n4859 = 8'h80 >> { n4245_1, n4428, Ng2741 }; + assign n3361 = 32'd4202232536 >> { Pg7916, n4584, Ng1171, Ng1183, Pg35 }; + assign n3366 = 32'd4158838208 >> { Ng1608, Ng1600, n4223, n4862, Pg35 }; + assign n4862 = 8'h02 >> { n4221_1, Ng1668, Ng1636 }; + assign n3371 = 64'hffd5aa807f552a00 >> { n4865_1, Ng1728, Ng1779, n4864, n4157_1, Pg35 }; + assign n4864 = 32'd2290616456 >> { Ng1171, Ng1183, n4162_1, n4199, Pg17316 }; + assign n4865_1 = 4'h6 >> { n4866, Ng112 }; + assign n4866 = 4'h2 >> { Ng1772, Ng1802 }; + assign n3376 = 32'd3429674156 >> { n4245_1, n4247, Pg35, Ng2638, Ng2652 }; + assign n3381 = 64'hf5ffb1bbe4eea0aa >> { Ng2173, Ng2193, Ng2197, Ng2153, Pg35, n4869_1 }; + assign n4869_1 = 16'h0080 >> { Ng2217, Pg35, n4228, Ng2208 }; + assign n3386 = 16'h7d28 >> { Ng2389, n4710, Ng2393, Pg35 }; + assign n3396 = 32'd2315291264 >> { n4872, Ng4950, n4282, n4873, Pg35 }; + assign n4872 = 16'h569a >> { Ng3698, Ng3694, Ng3703, Ng3639 }; + assign n4873 = 32'd128 >> { Ng4899, Ng4991, Ng4975, Ng4983, Ng4966 }; + assign n1042 = 4'h8 >> { Pg35, Ng5535 }; + assign n3401 = 32'd101493418 >> { Pg35, Ng5523, n4600, Ng5535, Ng5527 }; + assign n3406 = 8'hae >> { Pg35, Ng2803, n4397 }; + assign n3411_1 = 32'd3099097136 >> { n4313, n4630, Ng1345, Pg35, Ng1361 }; + assign n3416_1 = 32'd791285000 >> { Ng6235, Ng6227, n4185, n4879_1, Pg35 }; + assign n4879_1 = 32'd1 >> { Ng6219, Ng6215, Ng6209, Ng6203, Ng6227 }; + assign n3426 = 64'h7f552a00ffd5aa80 >> { n4881, Ng2610, Ng2625, n4859, n4157_1, Pg35 }; + assign n4881 = 8'h59 >> { Ng2610, Ng2619, Ng110 }; + assign n3431 = 32'd1688268012 >> { Pg35, n4633, n4635, Ng164, Ng150 }; + assign n3436 = 64'h7faaff2a5580d500 >> { Ng1696, Ng1687, Ng1691, n4453, n4884_1, Pg35 }; + assign n4884_1 = 4'h2 >> { Ng1624, Ng1648 }; + assign n3441 = 16'h0a6a >> { n4886, Pg35, Ng6555, Ng6549 }; + assign n4886 = 4'h8 >> { n4216, n4262 }; + assign n1129 = 4'h8 >> { Pg35, Ng3881 }; + assign n3446 = 32'd101493418 >> { Pg35, Ng3869, n4772, Ng3881, Ng3873 }; + assign n3451 = 32'd4159886800 >> { Ng6621, Ng6601, n4181, n4890, Pg35 }; + assign n4890 = 16'h0080 >> { Ng6555, Ng6565, Ng6573, Ng6549 }; + assign n3456 = 16'h99b8 >> { Pg35, Ng3466, n4537, Ng3470 }; + assign n3461 = 32'd4159886800 >> { Ng3897, Ng3949, n4181, n4893, Pg35 }; + assign n4893 = 8'h02 >> { Ng3881, Ng3873, Ng3869 }; + assign n3466 = 32'd1928483024 >> { Ng518, n4251, Ng513, n4250_1, Pg35 }; + assign n3476 = 64'hffd5aa807f552a00 >> { n4897, Ng2555, Ng2606, n4896, n4157_1, Pg35 }; + assign n4896 = 32'd2290649096 >> { Ng1526, Ng1514, n4174, n4706_1, Ng1430 }; + assign n4897 = 8'ha6 >> { Ng2599, Ng2629, Ng112 }; + assign n3481 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1495, n4899, Ng1442, Ng1472, Ng1467 }; + assign n4899 = 8'h80 >> { Ng1514, Ng1526, Pg13272 }; + assign n3486 = 32'd2728591266 >> { Pg35, Ng546, Ng542, Ng691, n4213 }; + assign n1050 = 4'h8 >> { Pg35, Ng5188 }; + assign n3491 = 32'd101493418 >> { Pg35, Ng5176, n4317, Ng5188, Ng5180 }; + assign n3506 = 32'd791285000 >> { Ng5216, Ng5220, n4185, n4904, Pg35 }; + assign n4904 = 32'd8 >> { Ng5164, Ng5170, Ng5176, Ng5180, Ng5188 }; + assign n3515_1 = 32'd863698952 >> { Ng4664, n4296, n4300, Pg35, Ng4669 }; + assign n3520 = 8'hd8 >> { Ng1236, Pg12919, Pg35 }; + assign n3525 = 32'd1145369668 >> { Ng4340, Ng4643, n4908, Pg18881, Pg35 }; + assign n4908 = 32'd8 >> { Ng4311, Ng4332, Ng4322, Pg35, n4751_1 }; + assign n3530 = 8'hd8 >> { Ng2852, Ng2860, Pg35 }; + assign n3535 = 64'hff8a7702fd887500 >> { Ng4743, Ng101, Ng4749, n4554, n4333, Pg35 }; + assign n3540 = 32'd789391880 >> { Ng6597, Ng6593, n4185, n4912, Pg35 }; + assign n4912 = 8'h08 >> { Ng6565, Ng6573, n4913 }; + assign n4913 = 8'h01 >> { Ng6555, Ng6549, Ng6561 }; + assign n3549 = 32'd111807658 >> { n4919_1, Pg35, n4915, Ng1413, Ng1542 }; + assign n4915 = 16'h22a2 >> { Ng1514, Ng1526, Ng1536, n4916 }; + assign n4916 = 8'h08 >> { n4917, n4918, Pg7946 }; + assign n4917 = 64'h0111111111111111 >> { n4314_1, Ng1379, Ng1367, Ng1345, Ng1312, Ng1351 }; + assign n4918 = 8'h08 >> { Ng1532, Ng1521, Ng1339 }; + assign n4919_1 = 16'h0008 >> { n4918, Ng1514, Ng1526, Pg7946 }; + assign n3557 = 32'd4159886800 >> { Ng6641, Ng6625, n4181, n4921, Pg35 }; + assign n4921 = 16'h0008 >> { Ng6573, Ng6565, Ng6555, Ng6549 }; + assign n3562 = 32'd3103273072 >> { Ng1936, n4382_1, Ng1906, Pg35, n4160 }; + assign n3572 = 32'd4210219216 >> { Ng504, n4251, Ng499, n4250_1, Pg35 }; + assign n3577 = 64'hffeedfcefdecddcc >> { Ng2587, n4925, Ng2595, n4245_1, n4858, Pg35 }; + assign n4925 = 4'h1 >> { n4247, Ng2619 }; + assign n3582 = 64'hfad8fad87250fad8 >> { Pg20049, n4927, Ng4372, Ng4477, Ng4581, Pg35 }; + assign n4927 = 4'h8 >> { Pg73, Pg72 }; + assign n3587 = 8'h72 >> { Ng2315, n4929_1, Pg35 }; + assign n4929_1 = 32'd1432180049 >> { n4176, n4170, Ng2287, Ng2331, Ng2311 }; + assign n3592 = 64'hfdddf8885ddd0888 >> { n4181, Ng3586, n4184, n4326, Ng3602, Pg35 }; + assign n3597 = 32'd4159886800 >> { Ng5571, Ng5543, n4181, n4932, Pg35 }; + assign n4932 = 16'h0002 >> { Ng5527, Ng5535, Ng5517, Ng5511 }; + assign n3602 = 32'd4159886800 >> { Ng3578, Ng3558, n4181, n4934_1, Pg35 }; + assign n4934_1 = 16'h0080 >> { Ng3512, Ng3530, Ng3522, Ng3506 }; + assign n3612 = 32'd4159886800 >> { Ng3582, Ng3566, n4181, n4936, Pg35 }; + assign n4936 = 16'h0002 >> { Ng3522, Ng3530, Ng3506, Ng3512 }; + assign n3617 = 32'd4159886800 >> { Ng6271, Ng6247, n4181, n4938, Pg35 }; + assign n4938 = 16'h0008 >> { Ng6219, Ng6209, Ng6203, Ng6227 }; + assign n3632 = 32'd791285000 >> { Ng5196, Ng5188, n4185, n4940, Pg35 }; + assign n4940 = 32'd1 >> { Ng5188, Ng5180, Ng5164, Ng5170, Ng5176 }; + assign n3637 = 32'd791285000 >> { Ng3227, Ng3207, n4185, n4942, Pg35 }; + assign n4942 = 16'h0080 >> { Ng3161, Ng3171, Ng3179, Ng3155 }; + assign n3642 = 8'h72 >> { Ng2024, n4944, Pg35 }; + assign n4944 = 32'd1432180049 >> { n4561_1, n4557, Ng1996, Ng2040, Ng2020 }; + assign n3647 = 16'hf2d0 >> { n4185, n4181, n4644, Ng6541 }; + assign n3652 = 32'd4159886800 >> { Ng3203, Ng3251, n4181, n4947, Pg35 }; + assign n4947 = 8'h08 >> { Ng3179, Ng3171, Ng3167 }; + assign n3657 = 32'd3389712938 >> { n4949_1, Ng1668, Pg35, n4221_1, Ng1636 }; + assign n4949_1 = 64'h0000000000000080 >> { Ng504, Ng528, Ng518, n4200, n4157_1, Ng112 }; + assign n3662 = 32'd2315291264 >> { n4951, Ng4760, n4503, n4952, Pg35 }; + assign n4951 = 16'h569a >> { Ng6044, Ng6040, Ng6049, Ng5990 }; + assign n4952 = 32'd128 >> { Ng4709, Ng4801, Ng4785, Ng4793, Ng4776 }; + assign n3667 = 32'd4268940368 >> { Ng232, Pg14096, Ng262, n4661_1, n4660 }; + assign n3682 = 32'd4201830480 >> { Ng460, Ng246, Ng168, n4211, Pg35 }; + assign n3687 = 16'h0a6a >> { n4203, Pg35, Ng6209, Ng6203 }; + assign n3692 = 32'd4239187084 >> { Ng333, Pg20763, Pg35, Ng355, Ng351 }; + assign n3701 = 4'h8 >> { Pg35, Ng3502 }; + assign n3706 = 64'hffd5aa807f552a00 >> { n4961, Ng2153, Ng2204, n4959_1, n4157_1, Pg35 }; + assign n4959_1 = 32'd2290616456 >> { Ng1526, Ng1514, n4174, n4960, Pg17320 }; + assign n4960 = 16'h0008 >> { Ng504, Ng518, Ng528, n4200 }; + assign n4961 = 8'ha6 >> { Ng2197, Ng2227, Ng112 }; + assign n3711 = 32'd4159886800 >> { Ng5256, Ng5240, n4181, n4963, Pg35 }; + assign n4963 = 16'h0008 >> { Ng5188, Ng5180, Ng5164, Ng5170 }; + assign n3716 = 32'd797909632 >> { Ng4601, n4965, Pg35, Ng4608, n4302 }; + assign n4965 = 8'h80 >> { n4303, Ng4593, Ng4601 }; + assign n3721 = 32'd1868975940 >> { n4213, Ng790, Pg35, n4207_1, Ng794 }; + assign n3739 = 64'h7a58fa587250fa50 >> { n4969_1, n4968, Ng703, Ng847, n4388, Pg35 }; + assign n4968 = 8'h80 >> { Ng837, Ng812, Ng847 }; + assign n4969_1 = 8'h80 >> { Ng817, Ng822, Ng723 }; + assign n3749 = 32'd4159886800 >> { Ng3247, Ng3231, n4181, n4971, Pg35 }; + assign n4971 = 16'h0008 >> { Ng3179, Ng3171, Ng3161, Ng3155 }; + assign n3754 = 64'hd850d850fa72d850 >> { n4973, Ng1996, Ng2040, Ng2047, n4557, Pg35 }; + assign n4973 = 32'd128 >> { Ng504, Ng528, n4384, n4157_1, Ng112 }; + assign n3759 = 8'hd8 >> { Ng4176, Ng4146, Pg35 }; + assign n3764 = 64'h48c0c0c0aaaaaaaa >> { Pg35, Ng4639, Ng4621, Ng4633, n4238, Ng4628 }; + assign n3769 = 8'hd8 >> { Ng4727, Ng4732, Pg35 }; + assign n3774 = 32'd3203273796 >> { Ng5817, Pg35, Ng5813, Ng5808, n4672 }; + assign n3779 = 64'hffeedfcefdecddcc >> { Ng2351, Ng2342, Ng2357, n4690, n4688, Pg35 }; + assign n3799 = 64'h4e4e4e4e4e4e444e >> { Ng4141, Ng4082, n4980, Ng2841, Ng4125, Pg35 }; + assign n4980 = 32'd128 >> { Ng4064, Ng4057, Ng4087, Ng4076, n4262 }; + assign n3808 = 32'd2096380080 >> { Ng3466, Ng3462, Ng3457, Pg35, n4285 }; + assign n3813 = 32'd4201830480 >> { Ng4116, Ng4145, Ng4112, n4983_1, Pg35 }; + assign n4983_1 = 8'h08 >> { Ng4057, Ng4064, n4984 }; + assign n4984 = 64'h0000000000000001 >> { Ng4082, Ng4141, Ng4093, Ng4098, Ng4087, Ng4076 }; + assign n3818 = 32'd3615643394 >> { n4151, Ng5037, Ng5041, n4986, Pg35 }; + assign n4986 = 16'h67ef >> { n4150, n4148, Ng5037, Ng5033 }; + assign n3823 = 32'd2863327914 >> { Ng4392, Ng4430, Pg35, n4663, Ng4452 }; + assign n3833 = 64'h5fddd7dd0a888288 >> { Ng6505, n4999, n5001, n6160, Ng6500, Pg35 }; + assign n4989 = 32'd2004317959 >> { n4992, n4998, n4990, n4996, n4994 }; + assign n4990 = 64'h0e0c0f0d0f0d0f0d >> { Pg14749, Ng6633, n4991, Ng6727, Ng6741, Ng6682 }; + assign n4991 = 16'h0777 >> { Ng6723, Ng6605, Ng6593, Pg13099 }; + assign n4992 = 32'd2860548224 >> { Pg17871, Ng6617, Ng6601, Pg12470, n4993_1 }; + assign n4993_1 = 4'h8 >> { Ng6682, Ng6741 }; + assign n4994 = 32'd3707698942 >> { Ng6625, Pg14749, n4995, Ng6741, Ng6682 }; + assign n4995 = 16'h0777 >> { Ng6581, Pg13099, Ng6723, Ng6589 }; + assign n4996 = 64'h7050f0d0f0d0f0d0 >> { Pg17764, Ng6641, n4997, Ng6727, Ng6682, Ng6741 }; + assign n4997 = 16'h0777 >> { Ng6585, Pg12470, Ng6609, Pg17871 }; + assign n4998 = 64'h2222200020002000 >> { Ng6597, Pg17722, Ng6649, Pg17764, Ng6682, Ng6741 }; + assign n4999 = 8'h80 >> { n4993_1, Pg17722, Ng6727 }; + assign n5000 = 64'h5ddd7fff7fff7fff >> { Ng6613, Pg14828, Ng6629, Pg17778, Ng6741, Ng6682 }; + assign n5001 = 32'd2863311402 >> { Ng4975, Ng4899, Ng4888, n4283, Ng4836 }; + assign n3838 = 32'd2111645832 >> { Ng3129, n4742, n5003, Ng3133, Pg35 }; + assign n5003 = 8'h80 >> { n5004, Ng3338, Pg16624 }; + assign n5004 = 4'h8 >> { Ng3352, Ng3288 }; + assign n3843 = 32'd1929007320 >> { Ng3333, n6163_1, Ng3263, n4742, Pg35 }; + assign n5006_1 = 64'hc0d0e0f0e0f0e0f0 >> { Ng3219, Pg13895, n5008, n5007, Ng3352, Ng3288 }; + assign n5007 = 32'd161061273 >> { n5004, Ng3235, Pg16718, Ng3338, Pg11349 }; + assign n5008 = 4'h8 >> { Ng3251, Pg16603 }; + assign n5009 = 16'h0777 >> { Pg16686, Ng3255, Ng3203, Pg16624 }; + assign n5010_1 = 64'h1111133313331333 >> { Pg11349, Ng3207, Ng3223, Pg16874, n5011, n5004 }; + assign n5011 = 64'h2222200020002000 >> { Pg14421, Ng3199, Ng3329, Ng3211, Ng3352, Ng3288 }; + assign n5012 = 64'h2222200020002000 >> { Pg11349, Ng3191, Ng3215, Pg16874, Ng3288, Ng3352 }; + assign n5013 = 64'h1111100010001000 >> { Ng3187, Pg14421, Ng3329, Ng3195, Ng3352, Ng3288 }; + assign n5014_1 = 64'h5777dfffdfffdfff >> { Ng3247, Pg16686, Ng3231, Pg13865, Ng3352, Ng3288 }; + assign n5015 = 64'h6666666606666666 >> { Ng3288, Ng3352, Ng3243, Pg16718, Pg11349, Ng3338 }; + assign n5016 = 64'hcdddefffefffefff >> { Pg16603, Ng3259, Ng3227, Pg13895, Ng3352, Ng3288 }; + assign n3857 = 32'd1688268012 >> { Pg35, n4339_1, n4346, Ng294, Ng298 }; + assign n3867 = 16'hdfdd >> { Ng1902, Pg35, n4371, n5019 }; + assign n5019 = 32'd3590313463 >> { Ng1917, Ng1894, Ng1926, n4236_1, Pg35 }; + assign n3872 = 8'hd8 >> { Ng2994, Ng2988, Pg35 }; + assign n3877 = 64'hf5f5f7f5e4e4c4e4 >> { n4181, Ng3522, n4183, Ng3538, Ng3530, Pg35 }; + assign n3892 = 32'd797942400 >> { Ng822, n5023_1, Pg35, Ng827, n4827 }; + assign n5023_1 = 16'h8000 >> { n4388, Ng817, Ng832, Ng822 }; + assign n3897 = 64'haa020000aa020002 >> { Ng2599, Ng2555, n4290, n4705, Ng2629, Pg35 }; + assign n3902 = 32'd1929007320 >> { Ng5011, n6160, Ng6657, n5001, Pg35 }; + assign n3912_1 = 32'd4005446676 >> { Ng6523, Ng6513, Pg35, Ng6519, n5027 }; + assign n5027 = 8'h2a >> { n5001, n4999, Pg35 }; + assign n3917_1 = 32'd4202232536 >> { Pg7946, n4915, Ng1514, Ng1526, Pg35 }; + assign n3922_1 = 32'd1219149994 >> { n4303, Pg35, Ng4601, n4302, Ng4593 }; + assign n3932_1 = 64'h4f444f444f445f55 >> { Ng1489, Ng1442, Ng1472, Pg35, Ng1484, n5031 }; + assign n5031 = 32'd3579705215 >> { Ng1484, n5032, Ng1300, n5033_1, Pg35 }; + assign n5032 = 4'h2 >> { Ng1319, n4173 }; + assign n5033_1 = 8'h02 >> { Ng1514, Ng1526, Pg13272 }; + assign n3937 = 8'hd8 >> { Ng4917, Ng4922, Pg35 }; + assign n3947_1 = 16'h0a6a >> { n4685, Pg35, Ng5863, Ng5857 }; + assign n3957 = 32'd3429674156 >> { n4429, n5037, Pg35, Ng2504, Ng2518 }; + assign n5037 = 4'h2 >> { Ng2453, Ng2476 }; + assign n3962_1 = 32'd4158838208 >> { Ng2567, Ng2648, n4292, n5039, Pg35 }; + assign n5039 = 8'h01 >> { n4290, Ng2555, Ng2629 }; + assign n3967 = 32'd863699032 >> { Ng562, n4356, n4350, Pg35, Ng568 }; + assign n3972 = 32'd4159886800 >> { Ng3263, Ng3259, n4181, n4515, Pg35 }; + assign n3977 = 32'd4159886800 >> { Ng6613, Ng6585, n4181, n5043_1, Pg35 }; + assign n5043_1 = 16'h0008 >> { Ng6573, Ng6555, Ng6565, Ng6549 }; + assign n4002 = 64'hddfd88f8dd5d8808 >> { n4223, Ng1620, n4221_1, n4454, Ng1616, Pg35 }; + assign n4012 = 64'hff7fd555ff2ad500 >> { Ng3606, Ng3562, n4181, n4369, Ng3518, Pg35 }; + assign n4022 = 32'd3203273796 >> { Ng3817, Pg35, Ng3813, Ng3808, n4740 }; + assign n4032 = 64'hf8f8f8f8f8f870f8 >> { Pg73, Ng4572, Pg72, Ng4498, Pg35, Ng4581 }; + assign n4042 = 32'd1220586154 >> { Pg35, Ng2715, Ng2724, Ng2841, Ng2719 }; + assign n4047 = 32'd2315291264 >> { n5050, Ng4704, Pg28753, n5051, Pg35 }; + assign n5050 = 16'h569a >> { Ng5352, Ng5348, Ng5357, Ng5297 }; + assign n5051 = 32'd32768 >> { Ng4801, Ng4709, Ng4785, Ng4793, Ng4776 }; + assign n4062_1 = 32'd4159886800 >> { Ng5220, Ng5264, n4181, n5053_1, Pg35 }; + assign n5053_1 = 8'h08 >> { Ng5180, Ng5188, Ng5176 }; + assign n4067 = 32'd1934654296 >> { n4356, Ng613, n4395, Pg35, Ng617 }; + assign n4072 = 8'h72 >> { Ng324, n5056, Pg35 }; + assign n5056 = 8'h1b >> { Ng305, Ng311, Ng324 }; + assign n4082 = 16'h7d28 >> { Ng6509, n4644, Ng6513, Pg35 }; + assign n4087 = 32'd4008110626 >> { Ng336, Ng305, Ng324, Pg35, Ng311 }; + assign n4102 = 64'hd850d850fa72d850 >> { n4382_1, Ng1862, Ng1906, Ng1913, n4160, Pg35 }; + assign n4117 = 64'hbfbb3f33afaa2f22 >> { Pg20654, Ng2799, n4776, Ng2193, Pg35, n4777 }; + assign n4122 = 8'hd8 >> { Ng4907, Ng4912, Pg35 }; + assign n4127 = 8'hd8 >> { Ng4146, Ng4157, Pg35 }; + assign n4132 = 16'h99b8 >> { Pg35, Ng2537, n4799, Ng2541 }; + assign n4137 = 64'hf2002200f2022202 >> { Ng2197, Pg35, Ng2153, n4493, Ng2227, n5065 }; + assign n5065 = 4'h2 >> { n5066, Pg35 }; + assign n5066 = 8'h80 >> { n4960, n4157_1, Ng112 }; + assign n4147_1 = 32'd4268940368 >> { Ng225, Pg14201, Ng255, n4661_1, n4660 }; + assign n4152 = 16'h55d5 >> { n4236_1, Pg35, Ng1945, n5069 }; + assign n5069 = 64'h7353f353f353f353 >> { Ng1894, Ng1874, n5070, Pg35, Ng1926, n4236_1 }; + assign n5070 = 64'h8888c8ccc8ccc8cc >> { Ng1870, Ng1917, Ng1882, Ng1926, n5071, Ng1894 }; + assign n5071 = 64'h89998dddabbbafff >> { Ng1890, Ng1878, Ng1886, Ng1894, Ng1926, Ng1917 }; + assign n4157 = 32'd4159886800 >> { Ng5240, Ng5224, n4181, n5073, Pg35 }; + assign n5073 = 16'h0002 >> { Ng5188, Ng5180, Ng5164, Ng5170 }; + assign n4162 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1495, n5075, Ng1442, Ng1478, Ng1437 }; + assign n5075 = 8'h08 >> { Ng1526, Ng1514, Pg13272 }; + assign n4167 = 16'h0a6a >> { n4772, Pg35, Ng3863, Ng3857 }; + assign n4172 = 64'h6c6ccc6cacacacac >> { n4236_1, Ng1894, Ng1917, Pg35, Ng1945, Ng1959 }; + assign n4177 = 32'd4101812280 >> { Ng3480, Ng3470, Ng3476, Pg35, n4285 }; + assign n4182 = 32'd4159886800 >> { Ng6653, Ng6637, n4181, n5080, Pg35 }; + assign n5080 = 16'h8000 >> { Ng6573, Ng6565, Ng6555, Ng6549 }; + assign n4192 = 32'd2315291264 >> { n5082_1, Ng4894, n5001, n5083, Pg35 }; + assign n5082_1 = 16'h569a >> { Ng6736, Ng6732, Ng6741, Ng6682 }; + assign n5083 = 32'd32768 >> { Ng4991, Ng4899, Ng4975, Ng4983, Ng4966 }; + assign n4207 = 32'd3615675776 >> { n6132, Ng1008, n4321, Ng1002, Pg35 }; + assign n4212 = 32'd1688268012 >> { Pg35, n4208, n4213, Ng772, Ng776 }; + assign n4231 = 8'hd5 >> { n4655, Ng110, n5087_1 }; + assign n5087_1 = 32'd93136815 >> { Ng1657, Ng1648, Ng1664, n4453, Pg35 }; + assign n4236 = 64'hdd88dd88d782d70a >> { n4170, Ng2287, Ng2361, n5089, Ng2375, Pg35 }; + assign n5089 = 32'd3638034648 >> { Ng1291, Ng1448, n4178, Ng1589, n4177_1 }; + assign n4255 = 16'h44e4 >> { Ng283, n4340, Ng278, Pg35 }; + assign n4260 = 32'd1147956332 >> { n4204, n4262, Ng3161, Ng3155, Pg35 }; + assign n4265 = 32'd3429674156 >> { n4690, n4692, Pg35, Ng2370, Ng2384 }; + assign n4270 = 32'd3099111472 >> { Ng4616, n4965, Ng4608, Pg35, n4302 }; + assign n4280 = 64'hf755a200ff5daa08 >> { n4561_1, Ng2012, Ng2024, n4557, n4783, Pg35 }; + assign n4289 = 64'hf222f222fffff222 >> { Pg35, Ng2791, n4777, Ng2795, Ng2036, n4776 }; + assign n4294 = 64'h78d878d8705078d8 >> { Ng559, Pg9048, n4353, Ng608, Ng613, Pg35 }; + assign n4304 = 32'd4101812280 >> { Ng1844, Ng1834, Ng1840, Pg35, n5098 }; + assign n5098 = 8'h01 >> { n4191, Ng1802, Ng1728 }; + assign n4309 = 32'd4159886800 >> { Ng5937, Ng5921, n4181, n5100, Pg35 }; + assign n5100 = 16'h0008 >> { Ng5881, Ng5857, Ng5873, Ng5863 }; + assign n4314 = 64'hf8f8f8f8f8f870f8 >> { Pg73, Ng4578, Pg72, Ng4567, Pg35, Ng4581 }; + assign n4319 = 64'h7faaff2a5580d500 >> { Ng2523, Ng2514, Ng2518, n4429, n5037, Pg35 }; + assign n4324 = 64'hdd88dd88d782d70a >> { n4290, Ng2555, Ng2629, n5104, Ng2643, Pg35 }; + assign n5104 = 32'd3840147684 >> { Ng1291, Ng1300, Ng1589, n4178, n4294_1 }; + assign n4334 = 32'd4005446676 >> { Ng2551, Ng2541, Pg35, Ng2547, n5106 }; + assign n5106 = 16'h2aaa >> { Ng2453, n4429, Ng2485, Pg35 }; + assign Pg26801 = 8'h80 >> { Ng5188, Ng5180, Ng5176 }; + assign n4339 = 16'hf2d0 >> { n4185, n4181, Pg26801, Ng5156 }; + assign n4352 = 64'h75207d287d287d28 >> { n4728, n4393, Ng6044, Ng6049, n4503, Pg35 }; + assign n4357 = 16'h99b8 >> { Pg35, Ng2269, n5111, Ng2273 }; + assign n5111 = 16'haaa8 >> { Ng2227, n4493, Ng2153, Pg35 }; + assign n4362 = 32'd2315291264 >> { n5113, Ng4771, n4257, n5114, Pg35 }; + assign n5113 = 16'h569a >> { Ng6390, Ng6386, Ng6395, Ng6336 }; + assign n5114 = 32'd128 >> { Ng4785, Ng4801, Ng4709, Ng4793, Ng4776 }; + assign n4372 = 16'hf2d0 >> { n4185, n4181, n4515, Ng3147 }; + assign n4382 = 32'd4005446676 >> { Ng2269, Ng2259, Pg35, Ng2265, n5111 }; + assign n4396 = 32'd1934654296 >> { n4356, Ng622, n4652, Pg35, Ng626 }; + assign n4401 = 32'd2143614916 >> { n4246, Ng2724, Ng2729, Pg35, Ng2841 }; + assign n4406 = 64'h75207d287d287d28 >> { n4751_1, n4393, Ng5352, Ng5357, Pg28753, Pg35 }; + assign n4411 = 64'h040caaaa060caaaa >> { Ng4966, Pg35, n4510, n4508, Ng4991, Ng4983 }; + assign n4416 = 32'd923286280 >> { n5122, Ng4785, n4296, Pg35, Ng4709 }; + assign n5122 = 8'h80 >> { n4299_1, Ng4793, Ng4776 }; + assign n4431 = 32'd4159886800 >> { Ng5929, Ng5909, n4181, n5124, Pg35 }; + assign n5124 = 16'h0080 >> { Ng5863, Ng5873, Ng5857, Ng5881 }; + assign n4436 = 8'hd8 >> { Ng4922, Ng4907, Pg35 }; + assign n4441 = 32'd1929007320 >> { Ng4035, n6156, Ng3965, n4522, Pg35 }; + assign n4451 = 32'd1655357610 >> { n4431_1, Pg35, Pg12919, Ng918, Ng914 }; + assign n4456 = 64'h7fc4f7c4f7c4f7c4 >> { Ng4064, Ng4057, Ng4141, Ng4082, Pg35, Ng2841 }; + assign n4461 = 64'hfad8fad87250fad8 >> { Ng1996, Ng2040, Ng2036, Ng2016, n5130, Pg35 }; + assign n5130 = 8'h08 >> { Ng2060, Ng2051, n5131 }; + assign n5131 = 32'd2829626024 >> { Ng2787, n4229, Ng2729, Ng2724, n4246 }; + assign n4466 = 32'd1934654296 >> { n4356, Ng586, n4450, Pg35, Ng577 }; + assign Pg25259 = 4'h2 >> { Ng1636, Ng1668 }; + assign n4471 = 64'hfff75d55ffa25d00 >> { Ng1608, Ng1620, n4223, n4221_1, Pg25259, Pg35 }; + assign n4476 = 8'hae >> { Pg35, Ng2771, n5136_1 }; + assign n5136_1 = 16'ha280 >> { n5137, n5138, n4398, Pg35 }; + assign n5137 = 64'hf7b3d591e6a2c480 >> { Ng1677, Ng1945, Ng1811, Ng2079, Ng2715, Ng2719 }; + assign n5138 = 64'h014589cd2367abef >> { Ng2783, Ng2787, Ng2775, Ng2771, Ng2715, Ng2719 }; + assign n4486 = 32'd2069394256 >> { Pg12919, Ng925, n5140, Pg35, Ng930 }; + assign n5140 = 16'h8000 >> { n4431_1, Ng914, Ng918, Ng925 }; + assign n4491 = 32'd4159886800 >> { Ng3937, Ng3921, n4181, n5142, Pg35 }; + assign n5142 = 16'h0008 >> { Ng3881, Ng3857, Ng3863, Ng3873 }; + assign n4496 = 32'd1574242432 >> { Ng812, n4388, Ng817, n4827, Pg35 }; + assign n4506 = 64'heafa62f0aafa22f0 >> { Ng847, n5145, Pg35, Ng703, n4388, Ng837 }; + assign n5145 = 32'd2763306 >> { Ng812, Ng847, Ng832, Ng827, Pg35 }; + assign n4511 = 32'd711592650 >> { n4354, n4356, Pg35, Ng599, Ng595 }; + assign n4516 = 16'h99b8 >> { Pg35, Ng5471, n4622, Ng5475 }; + assign n4521 = 64'h7bbb00887b7b0048 >> { Pg12184, Ng736, Pg11678, n4471_1, Pg35, Ng739 }; + assign n4526 = 32'd4158838208 >> { Ng5949, Ng5933, n4181, n5150, Pg35 }; + assign n5150 = 8'h80 >> { n4483, Ng5857, Ng5863 }; + assign n4531 = 64'h0cac6cac6cac6cac >> { n4596_1, n4751_1, n5001, Pg35, Ng6741, Ng6682 }; + assign n4541 = 8'hd8 >> { Ng2868, Ng2873, Pg35 }; + assign n4551 = 64'hc6c6eec6c4c6eec6 >> { Ng5069, Ng5073, Ng5077, Ng5084, Ng5080, Pg35 }; + assign n4556 = 32'd4159886800 >> { Ng5603, Ng5587, n4181, n5155, Pg35 }; + assign n5155 = 16'h0008 >> { Ng5527, Ng5535, Ng5517, Ng5511 }; + assign n4561 = 32'd3389712938 >> { n4567, Ng2495, Pg35, n4565, Ng2465 }; + assign n4566 = 32'd4157993680 >> { Ng2429, Ng2437, n4577, n5158, Pg35 }; + assign n5158 = 8'h02 >> { n4565, Ng2495, Ng2465 }; + assign n4571 = 16'h99b8 >> { Pg35, Ng2098, n5160_1, Ng2102 }; + assign n5160_1 = 16'h2aaa >> { Ng2028, n5131, Ng2060, Pg35 }; + assign n4581 = 64'hf755a200ff5daa08 >> { n4293, Ng2583, Ng2579, n4290, n4797, Pg35 }; + assign n4591 = 32'd923286280 >> { n5163, Ng4975, n4508, Pg35, Ng4899 }; + assign n5163 = 8'h80 >> { n4510, Ng4983, Ng4966 }; + assign n4601 = 32'd863699032 >> { Ng4776, n4296, n5122, Pg35, Ng4785 }; + assign n4606 = 32'd4159886800 >> { Ng5583, Ng5563, n4181, n5166, Pg35 }; + assign n5166 = 16'h0080 >> { Ng5517, Ng5535, Ng5527, Ng5511 }; + assign n4611 = 64'h64a0a0a0ecececec >> { Pg35, n4208, Ng772, n4213, Ng776, Ng781 }; + assign n4626 = 64'hdc8cfcacfcacfcac >> { n4389, Ng703, Ng686, Pg35, Ng691, n4250_1 }; + assign n4631_1 = 64'h48c0c0c0aaaaaaaa >> { Pg35, Ng1266, Ng1249, Ng1252, Pg12923, Ng1280 }; + assign n4636_1 = 64'h5d5508005dd50880 >> { n4389, Ng667, Ng671, n4387, Ng703, Pg35 }; + assign n4646 = 32'd791285000 >> { Ng6283, Ng6267, n4185, n5172, Pg35 }; + assign n5172 = 16'h0008 >> { Ng6203, Ng6227, Ng6219, Ng6209 }; + assign n4651 = 16'h0a6a >> { n4600, Pg35, Ng5527, Ng5523 }; + assign n4666 = 64'h62c0aaaac0c0aaaa >> { n4756, Pg35, Ng1259, Pg12923, Ng1270, Ng1263 }; + assign n4671 = 64'h1f2f2f2f00202020 >> { Ng4991, n4510, Ng4983, Pg35, n4508, Ng4966 }; + assign n1026 = 4'h8 >> { Pg35, Ng6227 }; + assign n4676 = 32'd101493418 >> { Pg35, Ng6215, n4203, Ng6227, Ng6219 }; + assign n4681 = 32'd4159886800 >> { Ng3929, Ng3909, n4181, n5179, Pg35 }; + assign n5179 = 16'h0080 >> { Ng3863, Ng3873, Ng3881, Ng3857 }; + assign n4686 = 64'hfddddddd08888888 >> { n4181, Ng5527, Ng5535, Ng5523, n4185, Ng5503 }; + assign n4696 = 32'd4159886800 >> { Ng5925, Ng5901, n4181, n5182, Pg35 }; + assign n5182 = 16'h0008 >> { Ng5873, Ng5863, Ng5857, Ng5881 }; + assign n4711 = 32'd4159886800 >> { Ng5224, Ng5196, n4181, n5184, Pg35 }; + assign n5184 = 16'h0002 >> { Ng5188, Ng5180, Ng5170, Ng5164 }; + assign n4716 = 32'd4158838208 >> { Ng2012, Ng2004, n4560, n5186, Pg35 }; + assign n5186 = 8'h02 >> { n4557, Ng2070, Ng2040 }; + assign n4731 = 64'h7faaff2a5580d500 >> { Ng2389, Ng2380, Ng2384, n4690, n4692, Pg35 }; + assign n4741 = 32'd4157993680 >> { Ng2433, Ng2429, n4577, n5189, Pg35 }; + assign n5189 = 8'h02 >> { n4565, Ng2465, Ng2421 }; + assign n4746_1 = 64'h772a5508f7aad588 >> { Ng85, Ng2787, Ng2795, n4157_1, n4529, Pg35 }; + assign n4751 = 16'hee4e >> { Ng1287, n4173, Ng1283, Pg35 }; + assign n4756_1 = 16'h99b8 >> { Pg35, Ng2671, n5193, Ng2675 }; + assign n5193 = 16'haaa8 >> { Ng2629, n4290, Ng2555, Pg35 }; + assign n4761 = 64'hf222222222222222 >> { n5195_1, n4908, n4306, Ng4340, Pg35, Ng4358 }; + assign n5195_1 = 64'h0000000000000002 >> { Ng4584, Ng4616, Ng4593, Ng4601, Ng4608, Ng4633 }; + assign n4775 = 32'd791285000 >> { Ng5547, Ng5551, n4185, n5197, Pg35 }; + assign n5197 = 32'd2 >> { Ng5535, Ng5517, Ng5511, Ng5523, Ng5527 }; + assign n4780 = 8'hd8 >> { Ng2130, Ng2138, Pg35 }; + assign n4785 = 64'hffd5aa807f552a00 >> { n5201, Ng2287, Ng2338, n5200, n4157_1, Pg35 }; + assign n5200 = 32'd2282260616 >> { Ng1526, Ng1514, n4174, n4499, Pg17404 }; + assign n5201 = 8'ha6 >> { Ng2331, Ng2361, Ng112 }; + assign n4790 = 32'd4159886800 >> { Ng6247, Ng6251, n4181, n5203, Pg35 }; + assign n5203 = 32'd2 >> { Ng6219, Ng6215, Ng6209, Ng6203, Ng6227 }; + assign n4795 = 64'hf222f222fffff222 >> { Pg35, Ng2779, Ng2791, n4777, Ng1902, n4776 }; + assign n4800 = 32'd4159886800 >> { Ng3949, Ng3933, n4181, n5206, Pg35 }; + assign n5206 = 16'h0008 >> { Ng3881, Ng3873, Ng3863, Ng3857 }; + assign n4810 = 32'd4159886800 >> { Ng5945, Ng5929, n4181, n5208_1, Pg35 }; + assign n5208_1 = 16'h0080 >> { Ng5857, Ng5873, Ng5881, Ng5863 }; + assign n4815 = 32'd4159886800 >> { Ng5244, Ng5228, n4181, n5210, Pg35 }; + assign n5210 = 16'h0008 >> { Ng5188, Ng5164, Ng5180, Ng5170 }; + assign n4820 = 32'd2143614916 >> { n4725, Ng2756, Ng2759, Pg35, Ng2841 }; + assign n4825 = 64'h75207d287d287d28 >> { n4751_1, n4596_1, Ng6736, Ng6741, n5001, Pg35 }; + assign n4830 = 32'd1868975940 >> { n4213, Ng781, Pg35, n5214, Ng785 }; + assign n5214 = 16'h8000 >> { n4208, Ng781, Ng776, Ng772 }; + assign n4835 = 32'd1655357610 >> { n4730, Pg35, Pg12923, Ng1259, Ng1256 }; + assign n4840 = 16'h7d28 >> { Ng3480, n4285, Ng3484, Pg35 }; + assign n4850 = 32'd4159886800 >> { Ng6609, Ng6581, n4181, n5218_1, Pg35 }; + assign n5218_1 = 16'h0002 >> { Ng6573, Ng6565, Ng6555, Ng6549 }; + assign n4855 = 16'h0a6a >> { n4600, Pg35, Ng5517, Ng5511 }; + assign n4860 = 32'd4157993680 >> { Ng2437, Ng2449, n4577, n5221, Pg35 }; + assign n5221 = 8'h02 >> { n4565, Ng2465, Ng2495 }; + assign n4865 = 32'd4159886800 >> { Ng2575, Ng2579, n4292, n5223_1, Pg35 }; + assign n5223_1 = 8'h08 >> { n4290, Ng2555, Ng2629 }; + assign n4879 = 32'd1220586154 >> { Pg35, Ng904, Ng936, Pg12919, Ng921 }; + assign n4884 = 32'd2096380080 >> { Ng2098, Ng2089, Ng2093, Pg35, n5226 }; + assign n5226 = 8'h08 >> { Ng2028, Ng2051, n5131 }; + assign n4889 = 64'hf8f8f8f8d8f8f8f8 >> { Ng10384, Ng4643, Ng4462, Ng4473, n5228_1, Pg35 }; + assign n5228_1 = 8'h02 >> { n5229, Ng4477, Ng26960 }; + assign n5229 = 32'd2695013026 >> { Pg99, Ng37, Ng4507, Pg134, n4240 }; + assign n4894 = 64'h260caaaa0c0caaaa >> { n4354, Pg35, Ng595, n4356, Ng604, Ng599 }; + assign n4899_1 = 32'd4159886800 >> { Ng6589, Ng6641, n4181, n5232, Pg35 }; + assign n5232 = 8'h02 >> { Ng6573, Ng6565, Ng6561 }; + assign n4904_1 = 8'h72 >> { Ng1890, n5234, Pg35 }; + assign n5234 = 32'd1432180049 >> { n4166, n4160, Ng1862, Ng1906, Ng1886 }; + assign n4914 = 32'd4159886800 >> { Ng1870, Ng1874, n4165, n5236, Pg35 }; + assign n5236 = 8'h02 >> { n4160, Ng1906, Ng1862 }; + assign n4919 = 8'hd8 >> { Ng4253, Ng4249, Pg35 }; + assign n4924 = 64'h6c6ccc6cacacacac >> { n4437, Ng1760, Ng1783, Pg35, Ng1811, Ng1825 }; + assign n4929 = 32'd3301240516 >> { n5240, Ng1008, n4794, Ng969, Pg35 }; + assign n5240 = 32'd1426326532 >> { Ng1018, Ng1030, n4320, Ng1046, n4321 }; + assign n4934 = 16'h7528 >> { Ng4417, Ng4392, n4531_1, Pg35 }; + assign n4939_1 = 32'd4159886800 >> { Ng3546, Ng3598, n4181, n5243_1, Pg35 }; + assign n5243_1 = 8'h02 >> { Ng3522, Ng3530, Ng3518 }; + assign n4944_1 = 32'd4159886800 >> { Ng5236, Ng5216, n4181, n5245, Pg35 }; + assign n5245 = 16'h0080 >> { Ng5170, Ng5180, Ng5164, Ng5188 }; + assign n4949 = 64'h7f552a00ffd5aa80 >> { n4469, Ng1748, Ng1768, n4437, n5247, Pg35 }; + assign n5247 = 4'h2 >> { Ng1792, Ng1783 }; + assign n4954 = 32'd673775400 >> { Pg35, Ng4849, n4511_1, Ng4854, n5249 }; + assign n5249 = 8'h02 >> { n4508, n4510, Pg35 }; + assign n4959 = 32'd4159886800 >> { Ng3925, Ng3901, n4181, n5251, Pg35 }; + assign n5251 = 16'h0008 >> { Ng3873, Ng3863, Ng3881, Ng3857 }; + assign n4964 = 32'd3203273796 >> { Ng6509, Pg35, Ng6505, Ng6500, n5027 }; + assign n4974 = 64'hf2fa72fad0d850d8 >> { Ng2504, n5256, n5254, Ng2485, n4429, Pg35 }; + assign n5254 = 64'h8ccc8ccc04448ccc >> { Ng2453, Ng2429, Ng2485, Ng2437, n5255, Ng2476 }; + assign n5255 = 64'hd0d8d1ddf2faf3ff >> { Ng2445, Ng2441, Ng2449, Ng2485, Ng2476, Ng2453 }; + assign n5256 = 4'h8 >> { Ng2433, Ng2453 }; + assign n4988 = 8'hd5 >> { n4765_1, Ng110, n5258_1 }; + assign n5258_1 = 64'ha2f72277a2f70257 >> { Ng2208, Ng2217, Ng2193, n4228, Ng2185, Pg35 }; + assign n4993 = 8'hd8 >> { Ng2894, Ng37, Pg35 }; + assign n5002_1 = 32'd3389712938 >> { n4973, Ng2070, Pg35, n4557, Ng2040 }; + assign n5023 = 32'd2111645832 >> { Ng6177, n4257, n4259, Ng6181, Pg35 }; + assign n5038 = 32'd4159886800 >> { Ng5563, Ng5567, n4181, n5263_1, Pg35 }; + assign n5263_1 = 32'd8 >> { Ng5517, Ng5511, Ng5523, Ng5535, Ng5527 }; + assign n5048 = 64'hffd5aa807f552a00 >> { n5266, Ng1862, Ng1913, n5265, n4157_1, Pg35 }; + assign n5265 = 4'h8 >> { n4383, n4161 }; + assign n5266 = 4'h6 >> { n4812, Ng112 }; + assign n5053 = 64'hd850d850fa72d850 >> { n4498, Ng2287, Ng2331, Ng2338, n4170, Pg35 }; + assign n5058 = 32'd4159886800 >> { Ng6263, Ng6235, n4181, n5269, Pg35 }; + assign n5269 = 16'h0002 >> { Ng6219, Ng6209, Ng6227, Ng6203 }; + assign n5068 = 32'd4159886800 >> { Ng3945, Ng3929, n4181, n5271_1, Pg35 }; + assign n5271_1 = 16'h0080 >> { Ng3857, Ng3873, Ng3863, Ng3881 }; + assign n4501 = 8'h08 >> { Ng1249, Pg12923, Pg35 }; + assign n5082 = 16'h48aa >> { Pg35, Ng1266, Pg12923, Ng1249 }; + assign n5087 = 32'd2111645832 >> { Ng5485, n4552, n5275, Ng5489, Pg35 }; + assign n5275 = 8'h80 >> { n5276_1, Pg17604, Ng5689 }; + assign n5276_1 = 4'h8 >> { Ng5644, Ng5703 }; + assign n5092 = 64'h48c0c0c0aaaaaaaa >> { Pg35, n4387, Ng671, Ng714, n4386_1, Ng676 }; + assign n5097 = 32'd1219149994 >> { n4726_1, Pg35, Ng2748, Ng2841, Ng2741 }; + assign n5102 = 32'd3203273796 >> { Ng5471, Pg35, Ng5467, Ng5462, n5280 }; + assign n5280 = 8'h2a >> { n5275, n4552, Pg35 }; + assign n5107 = 64'hfad8fad87250fad8 >> { Ng4575, n4927, Ng4372, Ng4423, Ng4581, Pg35 }; + assign n5116_1 = 32'd4159886800 >> { Ng6605, Ng6649, n4181, n5283, Pg35 }; + assign n5283 = 8'h08 >> { Ng6565, Ng6573, Ng6561 }; + assign n5121_1 = 32'd4157993680 >> { Ng2449, Ng2445, n4577, n5285, Pg35 }; + assign n5285 = 8'h02 >> { n4565, Ng2421, Ng2465 }; + assign n5126_1 = 32'd4157993680 >> { Ng2177, Ng2173, n4495, n5287, Pg35 }; + assign n5287 = 8'h08 >> { n4493, Ng2153, Ng2227 }; + assign n5131_1 = 64'h7f552a00ffd5aa80 >> { n5289, Ng2476, Ng2491, n4427, n4157_1, Pg35 }; + assign n5289 = 8'h59 >> { Ng2476, Ng2485, Ng110 }; + assign n5136 = 32'd101493418 >> { Pg35, Ng4878, n4508, Ng4849, Ng4843 }; + assign n5141_1 = 32'd4158838208 >> { Ng2169, Ng2161, n4495, n5292, Pg35 }; + assign n5292 = 8'h02 >> { n4493, Ng2227, Ng2197 }; + assign n5146_1 = 32'd4005446676 >> { Ng2283, Ng2273, Pg35, Ng2279, n4527 }; + assign n5151 = 32'd789391880 >> { Ng6589, Ng6585, n4185, n5295, Pg35 }; + assign n5295 = 8'h08 >> { Ng6573, n4913, Ng6565 }; + assign n5156_1 = 8'hae >> { Pg35, Ng2831, n5136_1 }; + assign n5160 = 16'h99b8 >> { Pg35, Ng2403, n4745, Ng2407 }; + assign n5165 = 8'hd8 >> { Ng2988, Ng2868, Pg35 }; + assign n5170 = 64'hf222f222fffff222 >> { Pg35, Ng2763, Ng2767, n4777, Ng1632, n4776 }; + assign n5185 = 32'd791285000 >> { Ng5212, Ng5260, n4185, n5301_1, Pg35 }; + assign n5301_1 = 8'h08 >> { Ng5188, Ng5180, Ng5176 }; + assign n5190 = 8'hd8 >> { Ng4249, Ng4245, Pg35 }; + assign n5195 = 16'hf888 >> { n5306_1, Ng446, n5304, Ng645 }; + assign n5304 = 64'hf0d0f0d0f0d0d0d0 >> { Ng518, Ng499, Ng691, Pg35, n5305, n4211 }; + assign n5305 = 16'h5551 >> { Ng424, Ng411, Ng417, Ng691 }; + assign n5306_1 = 64'h0008000800080808 >> { Ng518, Ng499, Ng691, n5305, n4211, Pg35 }; + assign n5204 = 32'd4210219216 >> { Pg20899, Ng661, Ng728, n4387, Pg35 }; + assign n5208 = 32'd4201830480 >> { Ng182, Ng446, Ng405, n4211, Pg35 }; + assign n5213 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1152, n5310, Ng1099, Ng1129, Ng1124 }; + assign n5310 = 8'h80 >> { Ng1183, Ng1171, Pg13259 }; + assign n5218 = 32'd3389712938 >> { n5066, Ng2227, Pg35, n4493, Ng2197 }; + assign n5228 = 32'd2096380080 >> { Ng1830, Ng1821, Ng1825, Pg35, n5313 }; + assign n5313 = 8'h08 >> { Ng1760, Ng1783, n4437 }; + assign n5233 = 32'd4157993680 >> { Ng3574, Ng3590, n4181, n5315, Pg35 }; + assign n5315 = 8'h08 >> { Ng3506, Ng3512, n4369 }; + assign n5238 = 64'h72507250fad87250 >> { Ng703, Ng854, Ng392, Ng401, n4388, Pg35 }; + assign n5243 = 64'haa020000aa020002 >> { Ng1636, Ng1592, n4221_1, n4949_1, Ng1668, Pg35 }; + assign n5253 = 16'h6caa >> { Pg35, Ng1087, Ng1221, Ng1205 }; + assign n5258 = 32'd4159886800 >> { Ng5921, Ng5893, n4181, n5320, Pg35 }; + assign n5320 = 16'h0008 >> { Ng5881, Ng5863, Ng5857, Ng5873 }; + assign n5267 = 32'd673775400 >> { Pg35, Ng142, n4634, Ng146, n4635 }; + assign n5276 = 64'h7f552a00ffd5aa80 >> { n5323, Ng1917, Ng1932, n4372_1, n4157_1, Pg35 }; + assign n5323 = 8'h59 >> { Ng1917, Ng1926, Ng110 }; + assign n5281 = 8'hd5 >> { n4655, Ng110, n5325 }; + assign n5325 = 64'ha2f72277a2f70257 >> { Ng1648, Ng1657, Ng1632, n4453, Ng1624, Pg35 }; + assign n5291 = 64'h5fd7dddd0a828888 >> { Ng5467, n4552, n5275, n6166, Ng5462, Pg35 }; + assign n5327 = 32'd1059727914 >> { n5331, n5330_1, n5275, Ng5619, n5328 }; + assign n5328 = 64'h0090909090909090 >> { Pg17711, n5276_1, Ng5591, n5329, Ng5689, Pg12300 }; + assign n5329 = 64'hcdddefffefffefff >> { Ng5575, Pg14694, Ng5607, Pg17580, Ng5703, Ng5644 }; + assign n5330_1 = 64'h9dddbfffbfffbfff >> { Ng5599, Pg17711, Ng5615, Pg17580, Ng5644, Ng5703 }; + assign n5331 = 64'h6666666666660666 >> { Ng5644, Ng5703, Ng5583, Pg14694, Pg12300, Ng5689 }; + assign n5332 = 32'd2860548224 >> { Ng5563, Pg12300, Ng5579, Pg17813, n5276_1 }; + assign n5333 = 64'h2222200020002000 >> { Ng5547, Pg12300, Ng5571, Pg17813, Ng5644, Ng5703 }; + assign n5334 = 64'h1111100010001000 >> { Ng5543, Pg13049, Ng5551, Ng5685, Ng5703, Ng5644 }; + assign n5335_1 = 64'h2222200020002000 >> { Ng5685, Ng5567, Ng5555, Pg13049, Ng5703, Ng5644 }; + assign n5336 = 64'h2222200020002000 >> { Ng5611, Pg17678, Ng5559, Pg17604, Ng5644, Ng5703 }; + assign n5296 = 4'h8 >> { Pg35, Ng2689 }; + assign n1018 = 4'h8 >> { Pg35, Ng6573 }; + assign n5301 = 32'd101493418 >> { Pg35, Ng6561, n4886, Ng6573, Ng6565 }; + assign n5306 = 64'hbb3b3b3b3b3b3b3b >> { n4453, Ng1604, Ng1624, Pg35, n5341, Ng1657 }; + assign n5341 = 16'hd5f7 >> { Ng1677, n5342, n4453, Pg35 }; + assign n5342 = 64'hc8ccc8cc4044c8cc >> { Ng1648, Ng1608, Ng1612, Ng1624, n5343, Ng1657 }; + assign n5343 = 64'h9b9b119bdfdf55df >> { Ng1616, Ng1657, Ng1620, Ng1600, Ng1624, Ng1648 }; + assign n5311 = 16'hdfdd >> { Ng2036, Pg35, n5345_1, n5347 }; + assign n5345_1 = 8'h80 >> { n5346, n4374, Ng110 }; + assign n5346 = 32'd32768 >> { Ng2756, n4373, Ng2741, Ng2748, n5131 }; + assign n5347 = 32'd3590313463 >> { Ng2051, Ng2028, Ng2060, n5131, Pg35 }; + assign n5316 = 32'd4005446676 >> { Ng2671, Ng2661, Pg35, Ng2667, n5193 }; + assign n998 = 32'd4201830480 >> { Pg10527, Pg12923, Ng1589, Pg17423, Pg35 }; + assign n1177 = 64'h4e444e44eeee4e44 >> { Ng4382, Ng4375, n4531_1, Ng4392, Ng4411, Pg35 }; + assign n5321 = 16'h7d28 >> { Ng1844, n5098, Ng1848, Pg35 }; + assign n5326 = 32'd1825352362 >> { Pg35, Ng5084, Ng5092, Pg20557, Ng5097 }; + assign n5330 = 32'd4005446676 >> { Ng5485, Ng5475, Pg35, Ng5481, n5280 }; + assign n5335 = 32'd1574242432 >> { Ng2735, n4726_1, Ng2741, Ng2841, Pg35 }; + assign n5340 = 64'hf272fafaf050f8d8 >> { Ng2638, n5357, n5356, Ng2619, n4245_1, Pg35 }; + assign n5356 = 8'h80 >> { n4245_1, Ng2587, Ng2567 }; + assign n5357 = 64'h88888ccc8ccc8ccc >> { Ng2571, Ng2619, Ng2587, Ng2579, n5358, Ng2610 }; + assign n5358 = 64'h8eaeceee8fafcfff >> { Ng2575, Ng2583, Ng2563, Ng2610, Ng2587, Ng2619 }; + assign n5345 = 32'd4201830480 >> { Ng4122, Ng4145, Ng4119, n5360_1, Pg35 }; + assign n5360_1 = 8'h80 >> { n4984, Ng4064, Ng4057 }; + assign n5350 = 64'h37003b0837083b08 >> { Ng4332, n4304_1, Ng4311, n4239, Pg35, Ng4322 }; + assign n5355 = 32'd791285000 >> { Ng5941, Ng5925, n4185, n5363, Pg35 }; + assign n5363 = 16'h0008 >> { Ng5873, Ng5857, Ng5881, Ng5863 }; + assign n5365 = 64'hffd5aa807f552a00 >> { n5366, Ng1592, Ng1644, n5365_1, n4157_1, Pg35 }; + assign n5365_1 = 32'd8 >> { Ng504, Ng528, Ng518, n4200, Pg27831 }; + assign n5366 = 4'h6 >> { Pg25259, Ng112 }; + assign n5370 = 32'd1934654296 >> { n4356, Ng590, n4354, Pg35, Ng595 }; + assign n5375 = 8'hd5 >> { n4765_1, Ng110, n5369 }; + assign n5369 = 32'd93136815 >> { Ng2217, Ng2208, Ng2223, n4228, Pg35 }; + assign n5385 = 64'h7f552a00ffd5aa80 >> { n5371, Ng2051, Ng2066, n5346, n4157_1, Pg35 }; + assign n5371 = 8'h59 >> { Ng2051, Ng2060, Ng110 }; + assign n5395 = 32'd4159886800 >> { Ng5252, Ng5236, n4181, n5373, Pg35 }; + assign n5373 = 16'h0080 >> { Ng5164, Ng5180, Ng5188, Ng5170 }; + assign n5400 = 32'd4158838208 >> { Ng2165, Ng2246, n4495, n5375_1, Pg35 }; + assign n5375_1 = 8'h01 >> { n4493, Ng2153, Ng2227 }; + assign n5405 = 32'd4158838208 >> { Ng2571, Ng2563, n4292, n5377, Pg35 }; + assign n5377 = 8'h02 >> { n4290, Ng2629, Ng2599 }; + assign n5410 = 32'd572662434 >> { n4317, Ng5176, Ng5164, Pg35, Ng5170 }; + assign n5420 = 64'hf222f222fffff222 >> { Pg35, Ng2823, Ng2827, n4777, Ng2595, n4776 }; + assign n5425 = 32'd863698952 >> { Ng4854, n4508, n4511_1, Pg35, Ng4859 }; + assign n5435 = 32'd2069394256 >> { Pg12923, Ng1270, n5382, Pg35, Ng1274 }; + assign n5382 = 16'h8000 >> { n4756, Ng1259, Ng1263, Ng1270 }; + assign n5444 = 32'd3705470684 >> { n4155, Ng2803, Ng2807, n5384, Pg35 }; + assign n5384 = 32'd8390792 >> { Ng2799, Ng111, n4157_1, n4155, Pg35 }; + assign n5454 = 64'hdd88dd88d782d70a >> { n4565, Ng2421, Ng2495, n5386, Ng2509, Pg35 }; + assign n5386 = 32'd1313734734 >> { Ng1291, Ng1472, Ng1589, n4178, n4578 }; + assign n5464 = 32'd1220586154 >> { Pg35, Ng1249, Ng1280, Pg12923, Ng1266 }; + assign n5472 = 32'd791285000 >> { Ng6633, Ng6617, n4185, n5389, Pg35 }; + assign n5389 = 16'h0008 >> { Ng6565, Ng6549, Ng6555, Ng6573 }; + assign n5477 = 32'd3203273796 >> { Ng5124, Pg35, Ng5120, Ng5115, n4760 }; + assign n5482 = 32'd4159886800 >> { Ng6303, Ng6287, n4181, n5392, Pg35 }; + assign n5392 = 16'h0080 >> { Ng6219, Ng6209, Ng6203, Ng6227 }; + assign n5492 = 8'hd8 >> { Ng2999, Ng2994, Pg35 }; + assign n5497 = 32'd4224838336 >> { Ng699, Ng681, Ng650, n5304, n5306_1 }; + assign n5502 = 64'hd850d850fa72d850 >> { n4949_1, Ng1592, Ng1636, Ng1644, n4221_1, Pg35 }; + assign n5507 = 32'd4159886800 >> { Ng3921, Ng3893, n4181, n5397, Pg35 }; + assign n5397 = 16'h0008 >> { Ng3881, Ng3863, Ng3873, Ng3857 }; + assign n5512 = 64'h6c6ccc6cacacacac >> { n5131, Ng2028, Ng2051, Pg35, Ng2079, Ng2093 }; + assign n5527 = 64'h0c0c060caaaaaaaa >> { Pg35, n5400_1, Pg12919, Ng979, Ng1061, Ng1052 }; + assign n5400_1 = 8'h01 >> { Ng990, Pg7916, Pg19334 }; + assign n5537 = 32'd4158838208 >> { Ng2181, Ng2169, n4495, n5402, Pg35 }; + assign n5402 = 8'h02 >> { n4493, Ng2197, Ng2227 }; + assign n5542 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1152, n5404, Ng1099, Ng956, Ng1141 }; + assign n5404 = 8'h02 >> { Ng1183, Ng1171, Pg13259 }; + assign n5547 = 64'hfff75d55ffa25d00 >> { Ng1744, Ng1756, n4194, n4191, n4866, Pg35 }; + assign n5552 = 64'hfddddddd08888888 >> { n4181, Ng5881, Ng5873, Ng5869, n4185, Ng5849 }; + assign n5562 = 32'd4005446676 >> { Ng2685, Ng2675, Pg35, Ng2681, n5408 }; + assign n5408 = 16'h2aaa >> { Ng2619, n4245_1, Ng2587, Pg35 }; + assign n5567 = 64'hfd75b830b830b830 >> { n5065, Ng2153, Ng2197, Ng2204, Pg35, n4493 }; + assign n5572 = 64'haa020000aa020002 >> { Ng2465, Ng2421, n4565, n4567, Ng2495, Pg35 }; + assign n5577 = 32'd2016458936 >> { n4794, Ng1008, Ng1041, Pg35, Ng1046 }; + assign n5582 = 64'hfafa70d8fafa78d8 >> { Ng490, n4251, n4249, Ng528, Ng482, Pg35 }; + assign n5587 = 32'd2863327914 >> { Ng4392, Ng4388, Pg35, n4531_1, Ng4405 }; + assign n5602 = 16'h0a6a >> { n4886, Pg35, Ng6565, Ng6561 }; + assign n5607 = 8'hd8 >> { Ng2936, Ng2950, Pg35 }; + assign n5612 = 32'd3615675776 >> { n4630, Ng1351, n4313, Ng1345, Pg35 }; + assign n5622 = 4'h8 >> { Pg35, Ng4727 }; + assign n5632 = 32'd791285000 >> { Ng3941, Ng3925, n4185, n5419, Pg35 }; + assign n5419 = 16'h0008 >> { Ng3873, Ng3857, Ng3863, Ng3881 }; + assign n5647 = 32'd4101812280 >> { Ng1858, Ng1848, Ng1854, Pg35, n5421 }; + assign n5421 = 8'h80 >> { n4437, Ng1792, Ng1760 }; + assign n5652 = 32'd4268940368 >> { Ng246, Ng872, Ng446, n4661_1, n4660 }; + assign n5657 = 32'd4159886800 >> { Ng3219, Ng3191, n4181, n5424, Pg35 }; + assign n5424 = 16'h0008 >> { Ng3179, Ng3161, Ng3171, Ng3155 }; + assign n5662 = 64'hb333b333bbbbb333 >> { n4437, Ng1811, n5421, Ng1740, n5426, Pg35 }; + assign n5426 = 64'haf27af27a727af27 >> { Ng1760, Ng1748, n5427, Ng1792, n4437, Pg35 }; + assign n5427 = 32'd2429595888 >> { Ng1756, Ng1744, n5428, Ng1792, Ng1783 }; + assign n5428 = 16'h9dbf >> { Ng1752, Ng1736, Ng1783, Ng1760 }; + assign n5667 = 32'd789391880 >> { Ng6605, Ng6601, n4185, n5430_1, Pg35 }; + assign n5430_1 = 8'h80 >> { n4913, Ng6573, Ng6565 }; + assign n5672 = 32'd4157993680 >> { Ng2445, Ng2441, n4577, n5432, Pg35 }; + assign n5432 = 8'h08 >> { n4565, Ng2421, Ng2495 }; + assign n5677 = 32'd4158838208 >> { Ng1874, Ng1955, n4165, n5434, Pg35 }; + assign n5434 = 8'h01 >> { n4160, Ng1862, Ng1936 }; + assign n5687 = 64'hf5f5f7f5e4e4c4e4 >> { n4181, Ng6565, n4913, Ng6581, Ng6573, Pg35 }; + assign n5692 = 32'd4159886800 >> { Ng6597, Ng6645, n4181, n5437, Pg35 }; + assign n5437 = 8'h08 >> { Ng6573, Ng6565, Ng6561 }; + assign n5697 = 32'd4157993680 >> { Ng3594, Ng3610, n4181, n5439_1, Pg35 }; + assign n5439_1 = 8'h80 >> { n4326, Ng3522, Ng3530 }; + assign n5707 = 32'd4101812280 >> { Ng1978, Ng1968, Ng1974, Pg35, n5434 }; + assign n5712 = 32'd4157993680 >> { Ng1616, Ng1612, n4223, n5442, Pg35 }; + assign n5442 = 8'h08 >> { n4221_1, Ng1592, Ng1668 }; + assign n5727 = 16'h7d28 >> { Ng1978, n5434, Ng1982, Pg35 }; + assign n5732 = 32'd4159886800 >> { Ng5228, Ng5200, n4181, n5445, Pg35 }; + assign n5445 = 16'h0008 >> { Ng5188, Ng5170, Ng5164, Ng5180 }; + assign n5737 = 32'd4201830480 >> { Ng4119, Ng4145, Ng4116, n5447, Pg35 }; + assign n5447 = 8'h08 >> { Ng4064, n4984, Ng4057 }; + assign n5761 = 64'h777d332877753320 >> { n4151, Ng5029, n4150, n4148, Ng5033, Pg35 }; + assign n5766 = 8'hd8 >> { Ng4732, Ng4717, Pg35 }; + assign n5776 = 16'hf2d0 >> { n4185, n4181, n4550, Ng3849 }; + assign n5781 = 32'd4159886800 >> { Ng3199, Ng3203, n4181, n5452, Pg35 }; + assign n5452 = 32'd2 >> { Ng3171, Ng3161, Ng3155, Ng3167, Ng3179 }; + assign n5786_1 = 32'd4005446676 >> { Ng5845, Ng5835, Pg35, Ng5841, n4476_1 }; + assign n5791_1 = 32'd863699032 >> { Ng4966, n4508, n5163, Pg35, Ng4975 }; + assign n5796_1 = 64'h78d878d8705078d8 >> { Ng736, Pg11678, n5214, Ng785, Ng790, Pg35 }; + assign n5801_1 = 32'd4159886800 >> { Ng5913, Ng5957, n4181, n5457, Pg35 }; + assign n5457 = 8'h08 >> { Ng5873, Ng5881, Ng5869 }; + assign n5806_1 = 64'hf5ffb1bbe4eea0aa >> { Ng1882, Ng1902, Ng1906, Ng1862, Pg35, n5459_1 }; + assign n5459_1 = 16'h0080 >> { Ng1926, Pg35, n4236_1, Ng1917 }; + assign n5811_1 = 32'd3203273796 >> { Ng6163, Pg35, Ng6159, Ng6154, n4256 }; + assign n5821 = 32'd1929007320 >> { Ng4821, n6166, Ng5619, n4552, Pg35 }; + assign n5826 = 32'd2315291264 >> { n5463, Ng4939, n4742, n4334_1, Pg35 }; + assign n5463 = 16'h569a >> { Ng3347, Ng3343, Ng3352, Ng3288 }; + assign n5831 = 32'd4159886800 >> { Ng3207, Ng3211, n4181, n5465, Pg35 }; + assign n5465 = 32'd8 >> { Ng3161, Ng3155, Ng3167, Ng3171, Ng3179 }; + assign n5840 = 32'd4159886800 >> { Ng3259, Ng3243, n4181, n5467, Pg35 }; + assign n5467 = 16'h8000 >> { Ng3179, Ng3171, Ng3161, Ng3155 }; + assign n5845 = 32'd2111645832 >> { Ng5138, Pg28753, n4415, Ng5142, Pg35 }; + assign n5850 = 32'd791285000 >> { Ng5248, Ng5232, n4185, n5470, Pg35 }; + assign n5470 = 16'h0008 >> { Ng5180, Ng5164, Ng5188, Ng5170 }; + assign n5855 = 32'd4005446676 >> { Ng2126, Ng2116, Pg35, Ng2122, n5160_1 }; + assign n5870 = 32'd2096380080 >> { Ng1964, Ng1955, Ng1959, Pg35, n5473 }; + assign n5473 = 8'h08 >> { Ng1894, n4236_1, Ng1917 }; + assign n5875 = 16'h6caa >> { Pg35, Ng5084, Ng5097, Ng5092 }; + assign n5880 = 32'd4159886800 >> { Ng3215, Ng3187, n4181, n5476, Pg35 }; + assign n5476 = 16'h0002 >> { Ng3179, Ng3171, Ng3161, Ng3155 }; + assign n5889 = 32'd1860620012 >> { Ng4388, Ng4401, Ng4434, Ng4430, Pg35 }; + assign n5894 = 64'hf222f222fffff222 >> { Pg35, Ng2767, n4777, Ng2779, Ng1768, n4776 }; + assign n1173 = 64'h4e444e44eeee4e44 >> { Ng4382, Ng4438, n4663, Ng4392, Ng4443, Pg35 }; + assign n5904 = 64'hccaaccaa60aac0aa >> { n4313, Ng1345, Pg35, n4630, Ng1367, Ng1361 }; + assign n5918 = 32'd4157993680 >> { Ng2165, Ng2161, n4495, n5482_1, Pg35 }; + assign n5482_1 = 8'h02 >> { n4493, Ng2197, Ng2153 }; + assign n5928 = 32'd3389712938 >> { n4498, Ng2361, Pg35, n4170, Ng2331 }; + assign n5933 = 32'd711592650 >> { n4450, n4356, Pg35, Ng582, Ng577 }; + assign n5948 = 64'hf5ffb1bbe4eea0aa >> { Ng2307, Ng2327, Ng2331, Ng2287, Pg35, n5486 }; + assign n5486 = 16'h0080 >> { Ng2351, Pg35, Ng2342, n4690 }; + assign n5953 = 32'd1219149994 >> { n4432, Pg35, Ng907, Pg12919, Ng936 }; + assign n5963 = 16'h7d28 >> { Ng1830, n5421, Ng1834, Pg35 }; + assign n5968 = 32'd4159886800 >> { Ng3594, Ng3578, n4181, n5490, Pg35 }; + assign n5490 = 16'h0080 >> { Ng3506, Ng3530, Ng3512, Ng3522 }; + assign n5978 = 32'd4158838208 >> { Ng2303, Ng2295, n4175, n5492_1, Pg35 }; + assign n5492_1 = 8'h02 >> { n4170, Ng2361, Ng2331 }; + assign n5983 = 32'd3941269482 >> { Pg35, Ng681, n5494, Ng699, n5306_1 }; + assign n5494 = 4'h2 >> { n4388, Pg35 }; + assign n5988 = 32'd681635052 >> { Pg35, n5023_1, Ng723, Ng827, n4590 }; + assign n5993 = 64'h75207d287d287d28 >> { n4743, n4393, Ng5698, Ng5703, n4552, Pg35 }; + assign n6003 = 64'hffd5aa807f552a00 >> { n5499, Ng2421, Ng2472, n5498, n4157_1, Pg35 }; + assign n5498 = 32'd143165576 >> { Ng1526, Ng1514, n4174, n4568, Pg17423 }; + assign n5499 = 8'ha6 >> { Ng2465, Ng2495, Ng112 }; + assign n6008_1 = 32'd4159886800 >> { Ng5953, Ng5937, n4181, n5501, Pg35 }; + assign n5501 = 16'h0080 >> { Ng5881, Ng5873, Ng5857, Ng5863 }; + assign n6013 = 32'd4158838208 >> { Ng1740, Ng1821, n4194, n5098, Pg35 }; + assign n6018 = 64'h0ddd0888fddda888 >> { n4185, Ng3554, n4183, n4369, Ng3550, Pg35 }; + assign n6023 = 32'd4101812280 >> { Ng3845, Ng3835, Ng3841, Pg35, n4550 }; + assign n6028 = 16'h7d28 >> { Ng2112, n4556_1, Ng2116, Pg35 }; + assign n6033 = 32'd4159886800 >> { Ng3195, Ng3247, n4181, n5507_1, Pg35 }; + assign n5507_1 = 8'h02 >> { Ng3179, Ng3171, Ng3167 }; + assign n6038 = 32'd4159886800 >> { Ng3913, Ng3957, n4181, n5509, Pg35 }; + assign n5509 = 8'h08 >> { Ng3873, Ng3881, Ng3869 }; + assign n6063 = 8'hd8 >> { Ng2689, Ng2697, Pg35 }; + assign n6068 = 8'hd8 >> { Ng4382, n4157_1, Pg35 }; + assign n6073 = 32'd572662434 >> { n4886, Ng6561, Ng6549, Pg35, Ng6555 }; + assign n6078 = 64'h725072507250fad8 >> { n5517_1, n5514, Ng1141, Ng1129, n5404, Pg35 }; + assign n5514 = 4'h9 >> { n5515, Ng956 }; + assign n5515 = 4'h2 >> { Ng976, n5516 }; + assign n5516 = 8'ha8 >> { Ng1008, Ng969, Ng1193 }; + assign n5517_1 = 8'h54 >> { Ng1146, Ng1099, Ng1141 }; + assign n6088 = 32'd4101812280 >> { Ng1710, Ng1700, Ng1706, Pg35, n4225 }; + assign n6093 = 32'd2111645832 >> { Ng6523, n4999, n5001, Ng6527, Pg35 }; + assign n6098 = 32'd4159886800 >> { Ng3255, Ng3239, n4181, n5521, Pg35 }; + assign n5521 = 16'h0080 >> { Ng3171, Ng3179, Ng3161, Ng3155 }; + assign n6103 = 32'd3429674156 >> { n4453, n4884_1, Pg35, Ng1677, Ng1691 }; + assign n6108 = 8'hd8 >> { Ng2922, Ng2936, Pg35 }; + assign n6118 = 32'd4101812280 >> { Ng5152, Ng5142, Ng5148, Pg35, Pg26801 }; + assign n6128 = 32'd3705470684 >> { n4594, Ng2775, Ng2783, n5526, Pg35 }; + assign n5526 = 32'd8390792 >> { Ng2779, Ng85, n4157_1, n4594, Pg35 }; + assign n6133 = 8'hd8 >> { Ng2912, Ng2922, Pg35 }; + assign n6143 = 32'd791285000 >> { Ng5893, Ng5897, n4185, n5529, Pg35 }; + assign n5529 = 32'd2 >> { Ng5881, Ng5869, Ng5857, Ng5863, Ng5873 }; + assign n6148 = 32'd4159886800 >> { Ng6617, Ng6593, n4181, n5531, Pg35 }; + assign n5531 = 16'h0008 >> { Ng6565, Ng6555, Ng6573, Ng6549 }; + assign n6153 = 64'hffeedfcefdecddcc >> { Ng2060, Ng2051, Ng2066, n5131, n5345_1, Pg35 }; + assign n6163 = 32'd4159886800 >> { Ng5599, Ng5583, n4181, n5534, Pg35 }; + assign n5534 = 16'h0080 >> { Ng5511, Ng5535, Ng5517, Ng5527 }; + assign n6182 = 32'd4005446676 >> { Ng3129, Ng3119, Pg35, Ng3125, n5536 }; + assign n5536 = 8'h2a >> { n5003, n4742, Pg35 }; + assign n6191 = 16'h0a6a >> { n4317, Pg35, Ng5170, Ng5164 }; + assign n6200 = 16'h99b8 >> { Pg35, Ng5817, n4476_1, Ng5821 }; + assign n6205 = 32'd4159886800 >> { Ng6299, Ng6283, n4181, n5540, Pg35 }; + assign n5540 = 16'h0080 >> { Ng6227, Ng6209, Ng6203, Ng6219 }; + assign n6210 = 64'hf2fa72fad0d850d8 >> { Ng2079, n5544, n5542_1, Ng2060, n5131, Pg35 }; + assign n5542_1 = 64'hc8ccc8cc4044c8cc >> { Ng2051, Ng2012, Ng2016, Ng2028, n5543, Ng2060 }; + assign n5543 = 64'h9d9d159dbfbf15bf >> { Ng2004, Ng2060, Ng2024, Ng2020, Ng2028, Ng2051 }; + assign n5544 = 4'h8 >> { Ng2008, Ng2028 }; + assign n6220 = 32'd1965063464 >> { n4834, Ng3698, Ng3703, n4282, Pg35 }; + assign n6230_1 = 16'hee4e >> { Ng943, n5516, Ng939, Pg35 }; + assign n6235_1 = 32'd4201830480 >> { Ng411, n5548, Ng417, n4388, Pg35 }; + assign n5548 = 32'd102207135 >> { Ng401, Ng424, Ng437, Ng405, Ng392 }; + assign n6240_1 = 32'd4159886800 >> { Ng3953, Ng3937, n4181, n5550, Pg35 }; + assign n5550 = 16'h0080 >> { Ng3881, Ng3873, Ng3863, Ng3857 }; + assign n6245_1 = 8'hd8 >> { Ng2697, Ng2704, Pg35 }; + assign n6255_1 = 64'hcccc6cccaaaaaaaa >> { Pg35, Ng1495, n5033_1, Ng1442, Ng1300, Ng1484 }; + assign n6265_1 = 32'd4159886800 >> { Ng5200, Ng5204, n4181, n5554, Pg35 }; + assign n5554 = 32'd2 >> { Ng5188, Ng5164, Ng5170, Ng5176, Ng5180 }; + assign n6275_1 = 32'd3615643394 >> { n4151, Ng5041, n5556, Ng5046, Pg35 }; + assign n5556 = 32'd2122317567 >> { n4150, n4148, Ng5041, Ng5037, Ng5033 }; + assign n6280 = 64'h6c6ccc6cacacacac >> { n4228, Ng2185, Ng2208, Pg35, Ng2236, Ng2250 }; + assign n6289_1 = 64'hf8f8f8f8f8f870f8 >> { Pg73, Ng4575, Pg72, Ng4546, Pg35, Ng4581 }; + assign n6294 = 16'hdfdd >> { Ng2461, Pg35, n4426_1, n5560 }; + assign n5560 = 32'd3590313463 >> { Ng2476, Ng2453, Ng2485, n4429, Pg35 }; + assign n6304 = 8'hd8 >> { Ng2907, Ng2912, Pg35 }; + assign n6309 = 64'h7f552a00ffd5aa80 >> { n5563, Ng2342, Ng2357, n4689, n4157_1, Pg35 }; + assign n5563 = 8'h59 >> { Ng2342, Ng2351, Ng110 }; + assign n6314 = 32'd1868975940 >> { n4635, Ng146, Pg35, n4633, Ng164 }; + assign n6319 = 8'hd8 >> { Ng4300, Ng4253, Pg35 }; + assign n6324 = 32'd1920487512 >> { n4151, Ng5062, Ng5022, Ng5016, Pg35 }; + assign n6329 = 16'h7d28 >> { Ng3115, n4515, Ng3119, Pg35 }; + assign n6334 = 32'd3301240516 >> { n5569, Ng1351, n4312, Ng1312, Pg35 }; + assign n5569 = 32'd1426326532 >> { Ng1373, Ng1361, n4314_1, Ng1389, n4313 }; + assign n6348 = 64'h5fd7dddd0a828888 >> { Ng5120, Pg28753, n4415, n6136, Ng5115, Pg35 }; + assign n6353 = 64'h75207d287d287d28 >> { n4743, n4596_1, Ng3347, Ng3352, n4742, Pg35 }; + assign n6358 = 32'd4159886800 >> { Ng6657, Ng6653, n4181, n4644, Pg35 }; + assign n6368 = 32'd4157993680 >> { Ng3897, Ng3893, n4181, n5574, Pg35 }; + assign n5574 = 8'h08 >> { Ng3881, n4359, Ng3873 }; + assign n6373 = 32'd4159886800 >> { Ng3211, Ng3255, n4181, n5576, Pg35 }; + assign n5576 = 8'h08 >> { Ng3171, Ng3179, Ng3167 }; + assign n6378 = 32'd791285000 >> { Ng5595, Ng5579, n4185, n5578, Pg35 }; + assign n5578 = 16'h0008 >> { Ng5527, Ng5511, Ng5517, Ng5535 }; + assign n6383 = 32'd3840210404 >> { Pg35, Ng3610, Ng3614, n4181, n4537 }; + assign n6388 = 8'hd8 >> { Ng2860, Ng2894, Pg35 }; + assign n6398 = 16'h7d28 >> { Ng3817, n4550, Ng3821, Pg35 }; + assign n6403_1 = 32'd796954496 >> { Ng4064, Ng4057, Pg35, Ng4141, Ng2841 }; + assign n6412 = 32'd4159886800 >> { Ng5272, Ng5268, n4181, Pg26801, Pg35 }; + assign n6417_1 = 64'h7fc4f7c4f7c4f7c4 >> { n4246, Ng2724, Ng2729, Ng2735, Pg35, Ng2841 }; + assign n6427_1 = 32'd4159886800 >> { Ng6295, Ng6279, n4181, n5586, Pg35 }; + assign n5586 = 16'h0008 >> { Ng6219, Ng6227, Ng6203, Ng6209 }; + assign n6432_1 = 16'h99b8 >> { Pg35, Ng2657, n5408, Ng2661 }; + assign n6442_1 = 16'h7d28 >> { Ng5124, Pg26801, Ng5128, Pg35 }; + assign n6452_1 = 64'h5fd7dddd0a828888 >> { Ng3111, n4742, n5003, n6163_1, Ng3106, Pg35 }; + assign n6457_1 = 32'd101493418 >> { Pg35, Ng4688, n4296, Ng4659, Ng4653 }; + assign n6462_1 = 32'd111807658 >> { n4305, Pg35, n4239, Ng4358, Ng4349 }; + assign n6467_1 = 64'hffeedfcefdecddcc >> { Ng1792, Ng1783, Ng1798, n4437, n4851, Pg35 }; + assign n6472_1 = 64'hdd88dd88d782d70a >> { n4557, Ng1996, Ng2070, n5594, Ng2084, Pg35 }; + assign n5594 = 32'd3840147684 >> { Ng947, Ng956, Ng1246, n4167_1, n4559 }; + assign n6477_1 = 32'd791285000 >> { Ng3187, Ng3179, n4185, n5596, Pg35 }; + assign n5596 = 32'd1 >> { Ng3179, Ng3171, Ng3161, Ng3155, Ng3167 }; + assign n6487_1 = 32'd4159886800 >> { Ng2583, Ng2571, n4292, n5598, Pg35 }; + assign n5598 = 8'h02 >> { n4290, Ng2599, Ng2629 }; + assign n6512_1 = 32'd791285000 >> { Ng3191, Ng3195, n4185, n5600, Pg35 }; + assign n5600 = 32'd2 >> { Ng3179, Ng3161, Ng3155, Ng3167, Ng3171 }; + assign n6536_1 = 16'h6caa >> { Pg35, Ng358, Ng385, Ng376 }; + assign n6541_1 = 32'd4159886800 >> { Ng2004, Ng2008, n4560, n5603, Pg35 }; + assign n5603 = 8'h02 >> { n4557, Ng2040, Ng1996 }; + assign n6546_1 = 16'h99b8 >> { Pg35, Ng2523, n5106, Ng2527 }; + assign n6575_1 = 32'd4159886800 >> { Ng3223, Ng3199, n4181, n5606, Pg35 }; + assign n5606 = 16'h0008 >> { Ng3171, Ng3161, Ng3179, Ng3155 }; + assign n6580_1 = 8'hd8 >> { Ng2960, Ng2970, Pg35 }; + assign n6590_1 = 32'd4159886800 >> { Ng5260, Ng5244, n4181, n5609, Pg35 }; + assign n5609 = 16'h0080 >> { Ng5188, Ng5180, Ng5164, Ng5170 }; + assign n6600_1 = 16'h0a6a >> { n4215, Pg35, Ng3522, Ng3518 }; + assign n6605_1 = 32'd3203273796 >> { Ng3115, Pg35, Ng3111, Ng3106, n5536 }; + assign n6610_1 = 32'd4159886800 >> { Ng3251, Ng3235, n4181, n5613, Pg35 }; + assign n5613 = 16'h0080 >> { Ng3179, Ng3171, Ng3161, Ng3155 }; + assign n943 = 32'd1965063464 >> { Ng4417, Ng4455, Ng4392, n4531_1, Pg35 }; + assign n6615_1 = 32'd1220586154 >> { Pg35, Ng4639, Ng4628, n4238, Ng4621 }; + assign n6620_1 = 64'haa020000aa020002 >> { Ng2040, Ng1996, n4557, n4973, Ng2070, Pg35 }; + assign n6625 = 32'd3874244172 >> { Ng4515, n5618, Ng4521, Ng4527, Pg35 }; + assign n5618 = 16'h8000 >> { Ng4483, Ng4489, Ng4486, Ng4492 }; + assign n6635 = 32'd4005446676 >> { Ng1724, Ng1714, Pg35, Ng1720, n4748 }; + assign n6640 = 32'd2016458936 >> { n4629, n4630, Ng1373, Pg35, Ng1379 }; + assign n6645 = 32'd4158838208 >> { Ng1878, Ng1870, n4165, n5622_1, Pg35 }; + assign n5622_1 = 8'h02 >> { n4160, Ng1936, Ng1906 }; + assign n6650 = 32'd3840210404 >> { Pg35, Ng5615, Ng5619, n4181, n4622 }; + assign n5624 = 64'h0777077700000777 >> { Ng2994, n5630, Ng554, n5628, n5625, Ng546 }; + assign n5625 = 8'h08 >> { Ng48, n5627_1, n5626 }; + assign n5626 = 4'h1 >> { Ng50, Ng16 }; + assign n5627_1 = 32'd1 >> { Ng52, Ng51, Ng46, Ng45, Ng8 }; + assign n5628 = 4'h8 >> { n5626, n5629 }; + assign n5629 = 64'h0000000000000002 >> { Ng52, Ng46, Ng45, Ng8, Ng48, Ng51 }; + assign n5630 = 4'h8 >> { n5629, n5631 }; + assign n5631 = 4'h2 >> { Ng50, Ng16 }; + assign n5632_1 = 64'h0000077707770777 >> { n5637_1, Ng2927, n5635, Ng622, n5633, Ng767 }; + assign n5633 = 4'h8 >> { n5626, n5634 }; + assign n5634 = 64'h0000000000000008 >> { Ng46, Ng45, Ng8, Ng48, Ng52, Ng51 }; + assign n5635 = 4'h8 >> { n5627_1, n5636 }; + assign n5636 = 8'h02 >> { Ng48, Ng16, Ng50 }; + assign n5637_1 = 8'h08 >> { Ng51, n5638, n5626 }; + assign n5638 = 32'd32768 >> { Ng52, Ng46, Ng45, Ng8, Ng48 }; + assign n5639 = 4'h8 >> { n5636, n5640 }; + assign n5640 = 32'd2 >> { Ng51, Ng46, Ng45, Ng8, Ng52 }; + assign n5641 = 32'd2 >> { Ng52, Ng46, Ng45, Ng8, Ng51 }; + assign n5642_1 = 8'h80 >> { n5626, n5638, Ng51 }; + assign n4052 = 32'd2 >> { Pg57, Pg56, Pg53, Ng55, Pg54 }; + assign n5644 = 8'h08 >> { Ng48, Ng50, Ng16 }; + assign n5645 = 4'h2 >> { Ng16, Ng50 }; + assign n5646 = 64'h5555444044404440 >> { n5647_1, n5636, n5634, n5629, n5626, Pg35 }; + assign n5647_1 = 16'h0001 >> { Ng51, Ng46, Ng45, Ng8 }; + assign n5648 = 32'd1381653 >> { Ng2912, n5642_1, n5633, Ng772, n5649 }; + assign n5649 = 16'h8000 >> { n5626, n5627_1, Ng2852, Ng48 }; + assign n5650 = 64'h0000077707770777 >> { n5651, Ng2856, Ng626, n5635, n5630, Ng2999 }; + assign n5651 = 8'h80 >> { n5626, n5641, Ng48 }; + assign n5652_1 = 32'd1381653 >> { n5639, Ng590, n5637_1, Ng2917, n5653 }; + assign n5653 = 32'd1430274112 >> { n5636, n5647_1, n5626, n5634, Pg35 }; + assign n5654 = 64'h0000000000008000 >> { Ng1291, Ng48, n5631, n4052, Ng1472, n5627_1 }; + assign n5655 = 64'h77777fff7fff7fff >> { n5641, Ng4922, n5627_1, Ng4732, n4052, n5644 }; + assign n5656 = 64'h2222222222222202 >> { Pg57, Ng55, Pg56, Pg54, Pg53, Ng46 }; + assign n5657_1 = 32'd32768 >> { Ng947, n5629, n5645, Ng1129, n4052 }; + assign n5658 = 64'h0000077707770777 >> { Ng2868, n5630, Ng794, n5628, n5625, Ng534 }; + assign n5659 = 32'd2763306 >> { Ng2950, n5642_1, n5633, Ng758, n5660 }; + assign n5660 = 64'h9dddbfffbfffbfff >> { n5638, Ng51, n5634, Ng37, Ng16, Ng50 }; + assign n5661 = 64'h7f7f7fffff7fffff >> { Ng4300, Ng947, Ng48, n4052, n5641, n5645 }; + assign n5662_1 = 64'h0000077707770777 >> { n5642_1, Ng2907, n5635, Ng632, n5633, Ng776 }; + assign n5663 = 64'h0000077707770777 >> { n5664, Ng595, n5651, Ng2848, n5637_1, Ng2902 }; + assign n5664 = 8'h80 >> { n5647_1, n5636, Ng52 }; + assign n5665 = 64'h007700f7007f00ff >> { Ng538, Ng2844, n5653, Ng48, n5626, n5627_1 }; + assign n5666 = 16'h0080 >> { Ng947, n5629, n5645, n4052 }; + assign n5667_1 = 64'h0000000000008000 >> { Ng1291, Ng48, n5631, n4052, Ng1300, n5627_1 }; + assign n5668 = 64'h2222222222222202 >> { Pg57, Ng55, Pg56, Pg54, Pg53, Ng45 }; + assign n5669 = 64'h77777fff7fff7fff >> { n5641, Ng4917, n5627_1, Ng4727, n5644, n4052 }; + assign n5670 = 64'h0000077707770777 >> { n5630, Ng2988, Ng807, n5628, n5625, Ng542 }; + assign n5671 = 32'd2763306 >> { Ng2898, n5651, n5639, Ng577, n5672_1 }; + assign n5672_1 = 32'd4160223231 >> { Ng50, Ng2936, Ng16, n5638, Ng51 }; + assign n5673 = 32'd2763306 >> { n5674, Ng617, n5637_1, Ng2941, n5675 }; + assign n5674 = 8'h08 >> { Ng52, n5636, n5647_1 }; + assign n5675 = 64'h557f7f7f7f7f7f7f >> { Ng2894, Ng48, n5627_1, Ng763, n5634, n5626 }; + assign n5676 = 64'h4444444444444404 >> { Pg57, Ng55, Pg56, Pg54, Ng48, Pg53 }; + assign n5677_1 = 32'd125269879 >> { Pg92, n5631, n5634, Ng2975, n5637_1 }; + assign n5678 = 64'h7777777707777777 >> { Ng51, n5631, n5638, Ng2980, n5664, Ng568 }; + assign n5679 = 64'h557f7f7f7f7f7f7f >> { Ng48, Ng2886, n5641, Ng744, n5634, n5626 }; + assign n5680 = 32'd357913941 >> { n4052, Ng939, n5629, n5645, n5681 }; + assign n5681 = 64'h2222222222222202 >> { Pg57, Ng55, Pg56, Pg54, Pg53, Ng51 }; + assign n5682_1 = 64'h0008080800888888 >> { n5625, n5639, Ng562, Ng199, n5683, n5684 }; + assign n5683 = 32'd3757563903 >> { Ng2984, Ng51, Ng50, Ng16, n5638 }; + assign n5684 = 32'd1434419071 >> { n5631, Ng2890, n5626, Ng781, n5629 }; + assign n5685 = 16'h0222 >> { Ng599, n5635, n5646, n5686 }; + assign n5686 = 32'd4126670335 >> { Pg100, Ng739, Ng50, Ng16, n5634 }; + assign n5687_1 = 64'h2222222222222202 >> { Pg57, Ng55, Pg56, Pg54, Pg53, Ng52 }; + assign n5688 = 64'h7f7fff7f7fffffff >> { Ng943, Ng4245, Ng48, n4052, n5641, n5645 }; + assign n5689 = 64'h00000ddd0ddd0ddd >> { Ng2873, n5630, Ng790, n5628, Ng550, n5625 }; + assign n5690 = 64'h0000077707770777 >> { Ng2960, n5642_1, n5637_1, Ng2965, n5635, Ng608 }; + assign n5691 = 64'h4444444444444404 >> { Pg57, Ng55, Pg56, Pg54, Ng50, Pg53 }; + assign n4241 = 64'ha888200020002000 >> { n4510, n5083, n4299_1, n5051, Ng4311, n4298 }; + assign n4027 = 16'h028a >> { n5695, n5694, Ng4311, n4298 }; + assign n5694 = 64'h08194c5d2a3b6e7f >> { n5276_1, n4505, Pg25114, n4260_1, Ng4358, Ng4349 }; + assign n5695 = 64'h048c26ae159d37bf >> { n4993_1, n5004, n4581_1, n4280_1, Ng4358, Ng4349 }; + assign n5696 = 32'd2139053439 >> { Ng2485, Ng2476, n4796, Ng2741, n4428 }; + assign n3567 = 4'h9 >> { n5698, n5699 }; + assign n5698 = 16'h6996 >> { n4112, n3061, n3202, n1789 }; + assign n5699 = 32'd2523490710 >> { n2608, n2848, n2001, n5063, n5700 }; + assign n5700 = 8'ha2 >> { Pg56, Pg54, Ng55 }; + assign n2425 = 64'h04448ccc8ccc8ccc >> { n5704, n5705, n5703, n5702_1, n4205, Ng4087 }; + assign n5702_1 = 64'hcdefefefefefefef >> { Ng5869, Ng5881, Ng5873, Pg26801, Ng4098, Ng4093 }; + assign n5703 = 64'h57dfdfdfdfdfdfdf >> { Ng3518, Ng3522, Ng3530, n4644, Ng4093, Ng4098 }; + assign n5704 = 64'h6e7f7f7f7f7f7f7f >> { Ng5523, Ng5527, Ng5535, n4550, Ng4098, Ng4093 }; + assign n5705 = 64'h9dbfbfbfbfbfbfbf >> { Ng6227, Ng6219, Ng6215, n4515, Ng4098, Ng4093 }; + assign n1582 = 16'ha222 >> { Ng376, Pg8719, Pg35, Ng385 }; + assign n2823 = 64'hffffd55daaaa8008 >> { Ng2980, Ng2984, n5698, n5699, n5708, Pg35 }; + assign n5708 = 8'h01 >> { Pg54, Pg56, Pg53 }; + assign n1294 = 8'h72 >> { Ng4366, n5710, Pg35 }; + assign n5710 = 32'd69604663 >> { n5713, n4307, n5711, n4751_1, Ng4340 }; + assign n5711 = 64'h3727150577675545 >> { Ng4515, Ng4311, n5712_1, n4240, Ng4322, Ng4332 }; + assign n5712_1 = 4'h2 >> { Ng2994, Pg90 }; + assign n5713 = 64'h0011020021110221 >> { Ng4616, Ng4608, Ng4584, Ng4601, Pg135, Ng4593 }; + assign n3992 = 64'heeeeeeee4eeeeeee >> { Ng2965, Pg91, n4135, n4137_1, Ng2955, Pg35 }; + assign n1577 = 64'h4eeeeeeeeeeeeeee >> { n5723, n5716, n5721, n4140, Ng2941, Pg35 }; + assign n5716 = 16'h0008 >> { Ng3831, Ng3845, n5719, n5717_1 }; + assign n5717_1 = 8'h01 >> { n5718, Ng3143, Ng3129 }; + assign n5718 = 32'd2863311528 >> { Ng3480, Ng5152, Ng3494, Ng5138, Pg35 }; + assign n5719 = 16'h555d >> { Ng5831, Ng5845, n5720, Pg35 }; + assign n5720 = 64'h0000000000000001 >> { Ng6177, Ng6191, Ng5499, Ng6537, Ng6523, Ng5485 }; + assign n5721 = 16'h0008 >> { Ng2955, Ng2946, n4142_1, n5722_1 }; + assign n5722_1 = 32'd1 >> { n4145, Ng1830, Ng2098, Ng1696, Ng1964 }; + assign n5723 = 16'h0002 >> { Ng3115, Ng3817, n4132_1, n4131 }; + assign n1809 = 32'd4008636132 >> { Ng4153, Ng2941, Ng4072, Ng2927, Pg35 }; + assign n2769 = 32'd4008595182 >> { Ng2975, Ng962, Ng1306, Ng2965, Pg35 }; + assign n4421 = 32'd4008635982 >> { Ng2927, Ng2932, Pg44, Ng2917, Pg35 }; + assign n4621 = 32'd4008595182 >> { Ng2917, n4173, n5516, Ng2902, Pg35 }; + assign n3251 = 64'heeeeeeeeeeeeee4e >> { Ng301, Ng209, Ng2902, Ng691, Ng2970, Pg35 }; + assign n1971 = 16'heee4 >> { Ng55, Ng2980, Ng2886, Pg35 }; + assign n5702 = 16'hee4e >> { Ng2890, Pg44, Ng2873, Pg35 }; + assign n2160 = 16'heee4 >> { Ng2886, Ng2946, Ng2878, Pg35 }; + assign n4057_1 = 16'hee4e >> { Ng2878, Pg91, Ng2882, Pg35 }; + assign n4092 = 32'd4008595182 >> { Ng2882, n4137_1, n4135, Ng2898, Pg35 }; + assign n2076 = 16'hee4e >> { Ng2898, n5716, Ng2864, Pg35 }; + assign n4187_1 = 16'hee4e >> { Ng2864, n5723, Ng2856, Pg35 }; + assign n5722 = 32'd4008595182 >> { Ng2856, n4142_1, n4140, Ng2848, Pg35 }; + assign n2647 = 16'hee4e >> { Ng2848, n5722_1, Pg20652, Pg35 }; + assign n6630 = 16'heee4 >> { Ng4300, Ng4242, Ng4297, Pg35 }; + assign n5010 = 16'heee4 >> { Ng4176, Ng4072, Ng4172, Pg35 }; + assign n2499 = 16'heee4 >> { Ng1283, Ng1277, Ng1296, Pg35 }; + assign n1696 = 16'heee4 >> { Ng939, Ng933, Ng952, Pg35 }; + assign n6531_1 = 16'heee4 >> { Ng534, Ng301, Ng542, Pg35 }; + assign n5998_1 = 16'hee4e >> { Ng546, Ng691, Ng538, Pg35 }; + assign n3907 = 16'heee4 >> { Ng199, Ng222, Pg21292, Pg35 }; + assign n4142 = 16'hee4e >> { Ng550, Pg20899, Ng534, Pg35 }; + assign n6178 = 8'he4 >> { Pg20652, Ng37, Pg35 }; + assign n4805 = 4'h8 >> { Pg35, Ng1291 }; + assign n5958 = 4'h8 >> { Pg35, Ng947 }; + assign n3110 = 8'hd8 >> { Ng550, Pg21292, Pg35 }; + assign n6270_1 = 16'h0a6a >> { n4508, Pg35, Ng4843, Ng4878 }; + assign n2269 = 16'h0a6a >> { n4296, Pg35, Ng4653, Ng4688 }; + assign n4426 = 64'hf7fdfdfda2a8a8a8 >> { Ng4643, n4306, Ng4628, n4239, Ng4340, Pg35 }; + assign n4007 = 64'hfda8fda8dd885d08 >> { Ng890, n5754, Ng446, Ng896, Ng862, Pg35 }; + assign n5754 = 64'h7f7f7f7f7f7f777f >> { n5755, Ng703, Ng370, Ng385, Ng376, Pg8719 }; + assign n5755 = 16'h9998 >> { Ng691, n5756_1, n5548, Ng417 }; + assign n5756_1 = 64'hffd7ffd7eec6bb93 >> { Ng411, Ng174, Ng441, Ng452, Ng182, Ng392 }; + assign n4706 = 64'hff8a7702fd887500 >> { Ng4955, Ng71, Ng4961, n4524, n4333, Pg35 }; + assign n3794 = 64'hff8a7702fd887500 >> { Ng4944, Ng71, Ng4950, n4873, n4333, Pg35 }; + assign n2460 = 64'hff8a7702fd887500 >> { Ng4888, Ng71, Ng4894, n5083, n4333, Pg35 }; + assign n5033 = 64'hff8a7702fd887500 >> { Ng4765, Ng101, Ng4771, n5114, n4333, Pg35 }; + assign n2006 = 64'hff8a7702fd887500 >> { Ng4754, Ng101, Ng4760, n4952, n4333, Pg35 }; + assign n6215 = 64'hff8a7702fd887500 >> { Ng4698, Ng101, Ng4704, n5051, n4333, Pg35 }; + assign n5682 = 32'd1434255400 >> { Ng4340, n4239, n4305, Ng4349, Pg35 }; + assign n5077 = 64'hfda8ffaafda8fda8 >> { Ng4473, Ng4462, Ng4369, Ng4459, n5228_1, Pg35 }; + assign n1006 = 64'hd8fad8fad8fa5072 >> { n5618, Ng2988, n5766_1, Ng4492, n4240, Pg35 }; + assign n5766_1 = 4'h1 >> { Ng4581, Ng4512 }; + assign n2101 = 64'hd8d8d050fafaf272 >> { n5768, Ng2988, n5769, Ng4564, n4240, Pg35 }; + assign n5768 = 4'h1 >> { Ng4581, Ng4552 }; + assign n5769 = 8'h80 >> { Ng4558, Ng4555, Ng4561 }; + assign n1764 = 8'hd8 >> { Pg20901, n5771_1, Pg35 }; + assign n5771_1 = 32'd1934713408 >> { Ng269, Ng262, Ng255, Pg73, Pg72 }; + assign n2618 = 8'hd8 >> { Ng479, n5773, Pg35 }; + assign n5773 = 64'hf7b3d591e6a2c480 >> { Ng246, Ng239, Ng232, Ng225, Pg73, Pg72 }; + assign n6113 = 64'h0cac6cac6cac6cac >> { n4393, n4743, n4552, Pg35, Ng5703, Ng5644 }; + assign n6408 = 32'd4177031416 >> { Ng4575, n4240, Ng4552, Pg35, Ng4581 }; + assign n6344 = 64'hfad8fad87250fad8 >> { Pg20049, n4240, Ng4512, Ng4515, Ng4581, Pg35 }; + assign n3862 = 8'hd8 >> { Ng2661, Ng2667, n5193 }; + assign n3784 = 8'hd8 >> { Ng2643, Ng2648, n5193 }; + assign n6053 = 8'hd8 >> { Ng2527, Ng2533, n4799 }; + assign n2923 = 8'hd8 >> { Ng2509, Ng2514, n4799 }; + assign n2051 = 8'hd8 >> { Ng2393, Ng2399, n4745 }; + assign n3627 = 8'hd8 >> { Ng2375, Ng2380, n4745 }; + assign n4641 = 8'hd8 >> { Ng2259, Ng2265, n5111 }; + assign n5223 = 8'hd8 >> { Ng2241, Ng2246, n5111 }; + assign n5360 = 8'hd8 >> { Ng2102, Ng2108, n5786 }; + assign n5786 = 4'h2 >> { n4556_1, Pg35 }; + assign n1502 = 8'hd8 >> { Ng2084, Ng2089, n5786 }; + assign n4661 = 8'hd8 >> { Ng1968, Ng1974, n5789 }; + assign n5789 = 4'h2 >> { n5434, Pg35 }; + assign n4347 = 8'hd8 >> { Ng1950, Ng1955, n5789 }; + assign n3672 = 8'hd8 >> { Ng1834, Ng1840, n5792 }; + assign n5792 = 4'h2 >> { n5098, Pg35 }; + assign n5449 = 8'hd8 >> { Ng1816, Ng1821, n5792 }; + assign n2031 = 8'hd8 >> { Ng1700, Ng1706, n5795 }; + assign n5795 = 4'h2 >> { n4225, Pg35 }; + assign n6043 = 8'hd8 >> { Ng1682, Ng1687, n5795 }; + assign n2234 = 64'he444444444444444 >> { Ng142, n4339_1, Ng294, Ng298, Ng301, Pg35 }; + assign n4037 = 16'h48aa >> { Pg35, Ng287, n4340, Ng283 }; + assign n1657 = 32'd8585215 >> { n5800, Ng4146, Pg120, Pg126, Pg35 }; + assign n5800 = 32'd2854813565 >> { Ng4122, Ng4157, Pg114, Pg115, Pg35 }; + assign n6048 = 8'hd8 >> { Ng2675, Ng2681, n5408 }; + assign n1206 = 8'hd8 >> { Ng2541, Ng2547, n5106 }; + assign n6083 = 16'hf2d0 >> { Ng2413, Ng2407, n4710, Pg35 }; + assign n3341 = 8'hd8 >> { Ng2273, Ng2279, n4527 }; + assign n2249 = 8'hd8 >> { Ng2116, Ng2122, n5160_1 }; + assign n6437_1 = 8'hd8 >> { Ng1982, Ng1988, n4235 }; + assign n4546 = 16'hf2d0 >> { Ng1854, Ng1848, n5421, Pg35 }; + assign n5899 = 8'hd8 >> { Ng1714, Ng1720, n4748 }; + assign n5747 = 32'd1434255400 >> { Ng1536, n4915, n4919_1, Ng1542, Pg35 }; + assign n4770 = 32'd1434255400 >> { Ng1193, n4584, n4588, Ng1199, Pg35 }; + assign n2893 = 8'hd8 >> { Ng6513, Ng6519, n5027 }; + assign n4616 = 8'hd8 >> { Ng6167, Ng6173, n4256 }; + assign n3607 = 8'hd8 >> { Ng5821, Ng5827, n4672 }; + assign n5865 = 8'hd8 >> { Ng5475, Ng5481, n5280 }; + assign n1774 = 8'hd8 >> { Ng5128, Ng5134, n4760 }; + assign n3828 = 8'hd8 >> { Ng3821, Ng3827, n4740 }; + assign n2553 = 16'hf2d0 >> { Ng3476, Ng3470, n4285, Pg35 }; + assign n6393 = 8'hd8 >> { Ng3119, Ng3125, n5536 }; + assign n1951 = 8'hd8 >> { Ng1478, n5820, Pg35 }; + assign n5820 = 64'h6f006f006f006f60 >> { Ng1442, Ng1489, Ng1454, n4708, n5032, Ng1448 }; + assign n2863 = 8'hd8 >> { Ng1448, n5822, Pg35 }; + assign n5822 = 64'h6f006f006f006f60 >> { Ng1442, Ng1489, Ng1467, n4899, n5032, Ng1472 }; + assign n1863 = 64'hf7a25500f7a25580 >> { Ng1489, Ng1437, Ng1442, n5824, n5075, Pg35 }; + assign n5824 = 4'h6 >> { n5032, Ng1478 }; + assign n6138 = 8'hd8 >> { Ng1135, n5826_1, Pg35 }; + assign n5826_1 = 64'h6f006f006f006f60 >> { Ng1099, Ng1146, Ng1111, n4606_1, n5515, Ng1105 }; + assign n4701 = 8'hd8 >> { Ng1105, n5828, Pg35 }; + assign n5828 = 64'h6f006f006f006f60 >> { Ng1099, Ng1146, Ng1124, n5310, n5515, Ng1129 }; + assign n6497_1 = 64'hf7a25500f7a25580 >> { Ng1146, Ng1094, Ng1099, n5830, n4421_1, Pg35 }; + assign n5830 = 4'h6 >> { n5515, Ng1135 }; + assign n5487 = 32'd4008603374 >> { Ng5046, n4152_1, Ng5022, Pg35, Ng5057 }; + assign n5459 = 64'heeeeeeeeeeee4eee >> { Ng5057, n4152_1, Ng5046, Ng5062, Ng5069, Pg35 }; + assign n4299 = 32'd2108303530 >> { n5713, Pg35, n5618, Ng4527, Ng4521 }; + assign n5816 = 16'h44e4 >> { Ng4125, Ng26936, Ng2841, Pg35 }; + assign n5557 = 64'hdd88dd88dd88fd08 >> { Ng4064, Ng4057, Ng4145, n4984, Ng4112, Pg35 }; + assign n6422_1 = 8'hd8 >> { Ng661, Ng728, n5304 }; + assign n3391 = 8'hd8 >> { Ng718, Ng661, n5304 }; + assign n1735 = 8'hd8 >> { Ng655, Ng718, n5304 }; + assign n3696 = 8'hd8 >> { Ng650, Ng655, n5304 }; + assign n6526 = 8'h72 >> { Pg20899, n5841, Pg35 }; + assign n5841 = 32'd3040212341 >> { n4389, Ng714, n4250_1, Ng703, Ng691 }; + assign n2140 = 8'hd8 >> { Ng645, Ng681, n5304 }; + assign n1512 = 16'h4eee >> { Ng4581, Ng4531, Ng4512, Pg35 }; + assign n2903 = 8'hd8 >> { Ng4459, Ng4473, Pg35 }; + assign n3952 = 16'h444e >> { Ng10384, Ng4473, Ng4462, Pg35 }; + assign n4275 = 8'hd8 >> { Ng4558, Pg6749, Pg35 }; + assign n3119 = 8'hd8 >> { Ng4561, Pg6750, Pg35 }; + assign n1677 = 8'hd8 >> { Ng4555, Pg6748, Pg35 }; + assign n1706 = 8'hd8 >> { Ng4489, Pg6750, Pg35 }; + assign n4656 = 8'hd8 >> { Ng4486, Pg6749, Pg35 }; + assign n2704 = 8'hd8 >> { Ng4483, Pg6748, Pg35 }; + assign n2323 = 32'd4201830480 >> { Pg114, Pg116, Ng4153, Ng4157, Pg35 }; + assign n5913 = 32'd4201830480 >> { Pg120, Pg124, Ng4104, Ng4146, Pg35 }; + assign n4391 = 16'h44e4 >> { Ng2712, Ng26936, Ng2841, Pg35 }; + assign n5627 = 32'd3638098648 >> { n5856, Ng1536, Ng1532, n4916, Pg35 }; + assign n5856 = 8'h80 >> { n4919_1, Ng1542, Ng1413 }; + assign n4017 = 64'h0c0c060caaaaaaaa >> { Pg35, n5858, Pg12923, Ng1322, Ng1404, Ng1395 }; + assign n5858 = 8'h01 >> { Ng1333, Pg7946, Pg19357 }; + assign n5943 = 32'd3638098648 >> { n5860_1, Ng1193, Ng1189, n4585, Pg35 }; + assign n5860_1 = 8'h80 >> { n4588, Ng1199, Ng1070 }; + assign n3744 = 16'h66e2 >> { Ng896, Ng862, Pg35, Ng890 }; + assign n1956 = 16'hf2d0 >> { Ng753, Ng732, n4210, Pg35 }; + assign n2603 = 8'hd8 >> { Ng518, n5864, Pg35 }; + assign n5864 = 32'd67503622 >> { Ng482, Ng490, n4251, Ng528, n4249 }; + assign n2377 = 16'h6664 >> { Ng355, Ng333, Ng351, Pg35 }; + assign n2150 = 8'h64 >> { Pg7540, Ng347, Pg35 }; + assign n1161 = 8'h72 >> { Ng333, Ng347, Pg35 }; + assign n5263 = 32'd1145365572 >> { Ng341, n5056, Ng329, Pg20763, Pg35 }; + assign n3887 = 8'hd8 >> { Pg21176, Ng316, Pg35 }; + assign n6058 = 32'd3638098648 >> { Ng311, Ng324, Ng336, Ng305, Pg35 }; + assign n6285 = 16'heee4 >> { Ng311, Ng305, Ng316, Pg35 }; + assign n1378 = 8'hd8 >> { Ng305, Pg6744, Pg35 }; + assign n5248 = 16'hf2d0 >> { Ng6505, Ng6541, n4644, Pg35 }; + assign n5617 = 16'hf2d0 >> { Ng6533, Ng6527, n4644, Pg35 }; + assign n3987 = 32'd1918005840 >> { Pg9743, Ng6444, Ng6494, Pg9817, Pg35 }; + assign n1014 = 8'hd8 >> { Ng6444, Ng6727, Pg35 }; + assign n2405 = 8'hd8 >> { Ng6195, Ng6159, n4598 }; + assign n2294 = 8'hd8 >> { Ng6181, Ng6187, n4598 }; + assign n4367 = 32'd1918005840 >> { Pg9682, Ng6098, Ng6148, Pg9741, Pg35 }; + assign n1022 = 8'hd8 >> { Ng6098, Ng6381, Pg35 }; + assign n1235 = 8'hd8 >> { Ng5849, Ng5813, n4476_1 }; + assign n6299 = 8'hd8 >> { Ng5835, Ng5841, n4476_1 }; + assign n2754 = 32'd1918005840 >> { Pg9617, Ng5752, Ng5802, Pg9680, Pg35 }; + assign n1030 = 8'hd8 >> { Ng5752, Ng6035, Pg35 }; + assign n3677 = 8'hd8 >> { Ng5503, Ng5467, n4622 }; + assign n2729 = 8'hd8 >> { Ng5489, Ng5495, n4622 }; + assign n3286 = 32'd1918005840 >> { Pg9555, Ng5406, Ng5456, Pg9615, Pg35 }; + assign n1038 = 8'hd8 >> { Ng5406, Ng5689, Pg35 }; + assign n4726 = 16'hf2d0 >> { Ng5120, Ng5156, Pg26801, Pg35 }; + assign n6560_1 = 16'hf2d0 >> { Ng5148, Ng5142, Pg26801, Pg35 }; + assign n2652 = 32'd1918005840 >> { Pg9553, Ng5022, Ng5112, Pg9497, Pg35 }; + assign n5286 = 32'd1918005840 >> { Pg9497, Ng5062, Ng5109, Pg9553, Pg35 }; + assign n1046 = 8'hd8 >> { Ng5062, Pg25219, Pg35 }; + assign n6260_1 = 16'h48aa >> { Pg35, Ng4057, Ng2841, Ng4064 }; + assign n1537 = 16'hf2d0 >> { Ng3813, Ng3849, n4550, Pg35 }; + assign n6502_1 = 16'hf2d0 >> { Ng3841, Ng3835, n4550, Pg35 }; + assign n3066 = 32'd1918005840 >> { Pg8344, Ng3752, Ng3802, Pg8398, Pg35 }; + assign n1121 = 8'hd8 >> { Ng3752, Ng4040, Pg35 }; + assign n5532 = 8'hd8 >> { Ng3498, Ng3462, n4537 }; + assign n1309 = 8'hd8 >> { Ng3484, Ng3490, n4537 }; + assign n6168 = 32'd1918005840 >> { Pg8279, Ng3401, Ng3451, Pg8342, Pg35 }; + assign n1133 = 8'hd8 >> { Ng3401, Ng3689, Pg35 }; + assign n1682 = 16'hf2d0 >> { Ng3111, Ng3147, n4515, Pg35 }; + assign n2613 = 16'hf2d0 >> { Ng3139, Ng3133, n4515, Pg35 }; + assign n2239 = 32'd1918005840 >> { Pg8215, Ng3050, Ng3100, Pg8277, Pg35 }; + assign n1145 = 8'hd8 >> { Ng3050, Ng3338, Pg35 }; + assign n6225 = 64'h4cccaaaa6cccaaaa >> { Ng1554, Pg35, Ng1548, Ng1430, Ng1559, Ng1564 }; + assign n5771 = 64'h7bbbbbbb08888888 >> { Ng1559, Ng1564, Ng1548, Ng1430, Pg35, Ng1554 }; + assign n5522 = 8'h72 >> { Ng1521, n5910, Pg35 }; + assign n5910 = 32'd357946709 >> { Ng1339, Ng1514, Ng1526, Pg7946, Ng1306 }; + assign n2642 = 64'h4cccaaaa6cccaaaa >> { Ng1211, Pg35, Ng1205, Ng1087, Ng1216, Ng1221 }; + assign n5415 = 64'h7bbbbbbb08888888 >> { Ng1216, Ng1221, Ng1205, Ng1087, Pg35, Ng1211 }; + assign n2833 = 8'h72 >> { Ng1178, n5914, Pg35 }; + assign n5914 = 32'd357946709 >> { Ng996, Ng1183, Ng1171, Pg7916, Ng962 }; + assign n4481 = 16'hf2d0 >> { Ng667, Ng686, n4250_1, Pg35 }; + assign n1220 = 8'hd8 >> { Ng460, Ng452, n5917 }; + assign n5917 = 4'h2 >> { n4211, Pg35 }; + assign n2367 = 8'hd8 >> { Ng182, Ng174, n5917 }; + assign n3261 = 8'hd8 >> { Ng174, Ng168, n5917 }; + assign n5637 = 64'h7ddddddd28888888 >> { Ng358, Ng385, Ng376, Pg8719, Ng370, Pg35 }; + assign n5923 = 16'h7d28 >> { Ng370, Ng376, Ng358, Pg35 }; + assign n4845 = 64'h7faaff2a5580d500 >> { Ng209, Pg8358, Ng191, Ng218, Pg8291, Pg35 }; + assign n1125 = 64'h7f552a00ffd5aa80 >> { Ng191, Ng222, Pg8358, Ng218, Pg8291, Pg35 }; + assign n1137 = 8'h72 >> { Ng209, Ng218, Pg35 }; + assign n5517 = 64'h464e4e4e4e4e4e4e >> { n5926, Pg17688, Pg17778, Ng6736, Ng6727, Pg35 }; + assign n5926 = 4'h8 >> { Pg12470, Pg14828 }; + assign n1976 = 64'h7ddddddd28888888 >> { Ng6723, n5926, Pg17688, Pg17778, Ng6727, Pg35 }; + assign n2200 = 16'h262e >> { n5929, Ng6390, Pg35, Ng6381 }; + assign n5929 = 16'h8000 >> { Pg12422, Pg17760, Pg14779, Pg17649 }; + assign n5028 = 16'h7d28 >> { Ng6377, n5929, Ng6381, Pg35 }; + assign n3301_1 = 64'h464e4e4e4e4e4e4e >> { n5932, Pg17607, Pg17739, Ng6044, Ng6035, Pg35 }; + assign n5932 = 4'h8 >> { Pg12350, Pg14738 }; + assign n6250_1 = 64'h7ddddddd28888888 >> { Ng6031, n5932, Pg17607, Pg17739, Ng6035, Pg35 }; + assign n5642 = 64'h464e4e4e4e4e4e4e >> { Pg17711, n5935, Pg17580, Ng5698, Ng5689, Pg35 }; + assign n5935 = 4'h8 >> { Pg12300, Pg14694 }; + assign n3496 = 64'h7ddddddd28888888 >> { Ng5685, n5935, Pg17580, Pg17711, Ng5689, Pg35 }; + assign n6570_1 = 64'h464e4e4e4e4e4e4e >> { n5938_1, Pg17519, Pg17674, Ng5352, Pg25219, Pg35 }; + assign n5938_1 = 4'h8 >> { Pg12238, Pg14662 }; + assign n1755 = 64'h7ddddddd28888888 >> { Ng5339, n5938_1, Pg17519, Pg17674, Pg25219, Pg35 }; + assign n2583 = 8'h6a >> { Pg35, Pg9251, Ng4308 }; + assign n4691 = 64'h5fd77df50a8228a0 >> { Ng4235, Ng4145, Ng4164, n5942, Ng4253, Pg35 }; + assign n5942 = 32'd2576980361 >> { Pg8920, Pg8916, n5943_1, Ng4235, Pg8870 }; + assign n5943_1 = 32'd1 >> { Pg8917, Pg8918, Pg8919, Pg11770, Pg8915 }; + assign n2858 = 64'h464e4e4e4e4e4e4e >> { Pg16775, n5945, Pg16659, Ng4049, Ng4040, Pg35 }; + assign n5945 = 4'h8 >> { Pg11418, Pg13966 }; + assign n1201 = 64'h7ddddddd28888888 >> { Ng4031, n5945, Pg16659, Pg16775, Ng4040, Pg35 }; + assign n5860 = 16'h262e >> { n5948_1, Ng3698, Pg35, Ng3689 }; + assign n5948_1 = 16'h8000 >> { Pg11388, Pg16627, Pg13926, Pg16744 }; + assign n3730_1 = 16'h7d28 >> { Ng3680, n5948_1, Ng3689, Pg35 }; + assign n2081 = 16'h262e >> { n5951, Ng3347, Pg35, Ng3338 }; + assign n5951 = 16'h8000 >> { Pg11349, Pg16718, Pg13895, Pg16603 }; + assign n3281 = 16'h7d28 >> { Ng3329, n5951, Ng3338, Pg35 }; + assign n935 = 8'hd8 >> { Ng1554, Ng496, Pg35 }; + assign n1153 = 64'hbbbbbb5baaaaaa4a >> { Ng1339, Pg13272, Pg8475, n5858, Pg35, n5955 }; + assign n5955 = 16'h0880 >> { Ng1322, Ng1579, n5956, Pg35 }; + assign n5956 = 8'h02 >> { Ng1351, Ng1312, n4312 }; + assign n1991 = 32'd4201830480 >> { Ng1532, Ng1521, Ng1306, Pg7946, Pg35 }; + assign n6595_1 = 32'd4201830480 >> { Ng1521, Ng1339, Ng1526, Pg7946, Pg35 }; + assign n1911 = 16'hf2d0 >> { Ng1442, Ng1495, n5033_1, Pg35 }; + assign n1858 = 16'hf2d0 >> { Ng1495, Ng1489, n5033_1, Pg35 }; + assign n939 = 8'hd8 >> { Ng1211, Pg20901, Pg35 }; + assign n1157 = 64'hdddddd7d88888828 >> { Ng996, Pg13259, Pg8416, n5400_1, n5963_1, Pg35 }; + assign n5963_1 = 8'h28 >> { Ng979, Ng1236, n5964 }; + assign n5964 = 8'h02 >> { Ng969, Ng1008, n4794 }; + assign n2011 = 32'd4201830480 >> { Ng1189, Ng1178, Ng962, Pg7916, Pg35 }; + assign n1725 = 32'd4201830480 >> { Ng1178, Ng996, Ng1183, Pg7916, Pg35 }; + assign n1587 = 16'hf2d0 >> { Ng1099, Ng1152, n5404, Pg35 }; + assign n5390 = 16'hf2d0 >> { Ng1152, Ng1146, n5404, Pg35 }; + assign n1279 = 8'hd8 >> { Ng854, Ng847, n5494 }; + assign n3306 = 8'hd8 >> { Ng475, Ng441, n5494 }; + assign n2145 = 8'hd8 >> { Ng441, Ng437, n5494 }; + assign n4909 = 8'hd8 >> { Ng433, Ng429, n5494 }; + assign n3296 = 8'hd8 >> { Ng429, Ng401, n5494 }; + assign n5430 = 8'hd8 >> { Ng411, Ng424, n5494 }; + assign n3501 = 8'hd8 >> { Ng392, Ng405, n5494 }; + assign n982 = 8'hd8 >> { Ng2946, n5977, Pg35 }; + assign n5977 = 32'd1717986934 >> { Pg8783, Pg8788, n5978_1, Ng4180, Pg8786 }; + assign n5978_1 = 32'd1 >> { Pg8787, Pg8785, Pg8784, Pg11447, Pg8789 }; + assign n1010 = 16'h444e >> { Ng4297, Pg10122, Ng4239, Pg35 }; + assign n4446 = 8'h6a >> { Pg35, Pg9019, Ng4291 }; + assign n1061 = 8'h72 >> { Ng4284, Ng4291, Pg35 }; + assign n6507_1 = 8'h6a >> { Pg35, Pg8839, Ng4281 }; + assign n1086 = 8'h72 >> { Ng4245, Ng4281, Pg35 }; + assign n6517_1 = 8'h72 >> { Ng4273, Ng4239, Pg35 }; + assign n975 = 32'd1349703930 >> { Ng4164, Ng4145, Ng4180, Ng4253, Pg35 }; + assign n4736 = 4'h8 >> { Pg35, Ng4423 }; + assign n1887 = 32'd4289657770 >> { Ng1917, Ng1894, n4236_1, Pg35, n4371 }; + assign n5175 = 32'd4289657770 >> { Ng1783, Ng1760, n4437, Pg35, n4851 }; + assign n6339 = 64'hfff2f2f2ffd0d0d0 >> { Ng1648, Ng110, n4655, Ng1624, n4453, Pg35 }; + assign n4874 = 16'h4eee >> { Ng2715, Ng2841, Ng2712, Pg35 }; + assign n6158 = 32'd4177031416 >> { Ng4572, n4240, Ng4504, Pg35, Ng4581 }; + assign n1936 = 32'd4289657770 >> { Ng2610, Ng2587, n4245_1, Pg35, n4858 }; + assign n4226 = 32'd4289657770 >> { Ng2476, Ng2453, n4429, Pg35, n4426_1 }; + assign n2391 = 32'd4289657770 >> { Ng2342, Ng2319, n4690, Pg35, n4688 }; + assign n4576 = 64'hfff2f2f2ffd0d0d0 >> { Ng2208, Ng110, n4765_1, Ng2185, n4228, Pg35 }; + assign n5938 = 32'd4289657770 >> { Ng2051, Ng2028, n5131, Pg35, n5345_1 }; + assign n4586 = 16'h4eee >> { Ng2841, Ng4064, Ng4072, Pg35 }; + assign n4596 = 16'h7baa >> { Pg35, Ng2719, Ng2841, Ng2715 }; + assign n6363 = 32'd4177031416 >> { Ng4578, n4240, Ng4549, Pg35, Ng4581 }; + assign n6565_1 = 32'd4284348245 >> { Pg113, Ng4507, Ng4459, Ng4473, Pg35 }; + assign Pg34972 = 8'hd7 >> { n5698, n5699, Ng22 }; + assign Pg34839 = 8'ha2 >> { Ng4366, n4297, Ng4369 }; + assign Pg34927 = 4'hd >> { n2848, Ng22 }; + assign Pg34925 = 4'hd >> { n5063, Ng22 }; + assign Pg34923 = 4'hd >> { n2608, Ng22 }; + assign Pg34921 = 4'hd >> { n1789, Ng22 }; + assign Pg34919 = 4'hd >> { n4112, Ng22 }; + assign Pg34917 = 4'hd >> { n3061, Ng22 }; + assign Pg34915 = 4'hd >> { n2001, Ng22 }; + assign Pg34913 = 4'hd >> { n3202, Ng22 }; + assign Pg33894 = 16'haa2a >> { Ng528, n4200, Ng479, Ng890 }; + assign Pg31665 = 4'h7 >> { Pg113, Ng2868 }; + assign Pg31656 = 4'h7 >> { Pg113, Ng2873 }; + assign Pg34425 = 8'hf7 >> { n4027, n4298, n6015 }; + assign n6015 = 16'ha888 >> { Pg99, Ng37, Pg134, Pg113 }; + assign Pg34383 = 8'hf7 >> { n5717, n4200, n6015 }; + assign Pg34221 = 8'hf7 >> { n4241, n4298, n6015 }; + assign Pg34201 = 8'hf7 >> { n2694, n4373, n6015 }; + assign Pg33874 = 32'd3722436575 >> { Pg99, Ng37, Pg134, Pg18881, Ng4507 }; + assign Pg33659 = 8'hf7 >> { n2425, n4205, n6015 }; + assign Pg33435 = 64'h084c2a6e195d3b7f >> { Ng2771, Ng2783, Ng2775, Ng2787, Ng2724, Ng2729 }; + assign Pg33079 = 64'h084c2a6e195d3b7f >> { Ng2803, Ng2815, Ng2807, Ng2819, Ng2724, Ng2729 }; + assign Pg32185 = 16'h0888 >> { Ng2927, Ng2922, n6024, n6025 }; + assign n6024 = 64'h0000077707770777 >> { Ng2941, Ng2936, Ng2960, Ng2965, Ng2907, Ng2902 }; + assign n6025 = 64'h0000077707770777 >> { Ng2970, Ng2975, Ng2917, Ng2912, Ng2950, Ng2955 }; + assign Pg28042 = 8'hfd >> { Ng1306, Ng962, Pg35 }; + assign Pg28041 = 8'hfd >> { n5516, n4173, Pg35 }; + assign Pg28030 = 64'h888eeeee888ceeee >> { n6031, Pg35, Ng3831, Ng3845, n6029, n5719 }; + assign n6029 = 32'd2290649256 >> { Ng5831, Ng5845, n6030, n5720, n5717_1 }; + assign n6030 = 64'h000100010001111f >> { Ng6177, Ng6191, Ng5499, Ng5485, Ng6523, Ng6537 }; + assign n6031 = 64'h000100010001111f >> { Ng3143, Ng3129, Ng3494, Ng3480, Ng5138, Ng5152 }; + assign Pg21727 = 4'h2 >> { Pg35, Ng3003 }; + assign n1284 = 32'd4202347130 >> { Ng1052, Pg12919, Pg35, Pg19334, Ng1061 }; + assign n1289 = 8'ha8 >> { Ng4153, Ng4172, Pg35 }; + assign n959 = 16'h80a2 >> { Pg17739, Pg12350, Pg14738, n6036 }; + assign n6036 = 16'h0002 >> { Pg17646, Pg13068, Pg17607, Pg35 }; + assign n1328 = 32'd131586 >> { n4262, n4204, Ng3155, Ng3167, Pg35 }; + assign n1343 = 16'h2aaa >> { n5948_1, Pg35, Ng3689, Ng3694 }; + assign n963 = 16'h80a2 >> { Pg17711, Pg12300, Pg14694, n6040 }; + assign n6040 = 16'h0002 >> { Pg17604, Pg13049, Pg17580, Pg35 }; + assign n1592 = 8'h2a >> { Pg35, n4508, Ng4871 }; + assign n1627 = 8'h2a >> { Pg35, n4296, Ng4646 }; + assign n1647 = 32'd680045226 >> { Pg35, n4388, Ng847, Ng843, Ng837 }; + assign n1672 = 16'h0002 >> { n4215, Ng3518, Ng3506, Pg35 }; + assign n1701 = 8'h02 >> { n4342, n4344, Pg35 }; + assign n1711 = 8'h2a >> { Pg35, n4508, Ng4836 }; + assign n1834 = 8'h2a >> { Pg35, n4508, Ng4864 }; + assign n967 = 16'h80a2 >> { Pg17674, Pg12238, Pg14662, n6049 }; + assign n6049 = 16'h0002 >> { Pg13039, Pg17577, Pg17519, Pg35 }; + assign n1926 = 16'ha222 >> { n4306, n4238, Pg35, Ng4633 }; + assign n1054 = 4'h2 >> { Ng4308, Pg35 }; + assign n2041 = 16'haa28 >> { n4584, Ng1171, Pg7916, Pg35 }; + assign n2170 = 16'h0002 >> { n4600, Ng5511, Ng5523, Pg35 }; + assign n2205 = 32'd2290122752 >> { Ng168, Ng174, Ng182, Pg35, n4634 }; + assign n2244 = 32'd134742536 >> { n5400_1, Pg12919, Ng979, Ng1052, Pg35 }; + assign n1111 = 8'h02 >> { Ng358, Pg8719, Pg35 }; + assign n2328 = 64'ha080a080a080a2a2 >> { n6058_1, n4586_1, n4320, Ng969, n4321, Pg35 }; + assign n6058_1 = 32'd707439146 >> { n4320, Ng1046, Ng1030, Ng1018, Ng1008 }; + assign n2348 = 8'ha2 >> { Ng5069, Pg35, Ng5073 }; + assign n2578 = 64'h2aaaaaaaaaaaaaaa >> { Ng4040, Pg16659, Pg16775, Pg35, n5945, Ng4045 }; + assign n2794 = 16'h0002 >> { n4317, Ng5164, Ng5176, Pg35 }; + assign n2808 = 16'h0002 >> { n4886, Ng6549, Ng6561, Pg35 }; + assign n779 = 32'd2 >> { n6064, Pg17404, Pg17320, Pg17423, Pg35 }; + assign n6064 = 32'd32768 >> { n5956, Ng1564, Ng1548, Ng1554, Ng1430 }; + assign n2913 = 16'haa2a >> { n5228_1, Ng4462, Ng10384, Pg35 }; + assign n3316 = 32'd4294835709 >> { Ng4473, Ng10384, Ng4462, n5228_1, Pg35 }; + assign n951 = 16'h80a2 >> { Pg17760, Pg12422, Pg14779, n6068_1 }; + assign n6068_1 = 16'h0002 >> { Pg17685, Pg13085, Pg17649, Pg35 }; + assign n3421 = 32'd145262760 >> { Ng1152, Ng1099, n5404, Ng1146, Pg35 }; + assign n880 = 4'h8 >> { Pg35, Pg21176 }; + assign n3471 = 8'ha8 >> { Ng538, Ng209, Pg35 }; + assign n3622 = 8'h2a >> { Pg35, n4296, Ng4681 }; + assign n3789 = 64'h2aaaaaaaaaaaaaaa >> { Pg17688, Pg17778, n5926, Pg35, Ng6727, Ng6732 }; + assign n3852 = 8'h2a >> { Pg35, n4296, Ng4674 }; + assign n3882 = 8'h8a >> { Pg35, n4854, Ng160 }; + assign n786 = 32'd2 >> { n6077, Pg17400, Pg17316, Pg17291, Pg35 }; + assign n6077 = 32'd32768 >> { n5964, Ng1221, Ng1205, Ng1211, Ng1087 }; + assign n3927_1 = 16'h2a08 >> { Ng854, n5755, n6079, Pg35 }; + assign n6079 = 16'h0080 >> { Ng385, Ng370, Ng376, Pg8719 }; + assign n3942 = 32'd170560170 >> { Ng5069, Ng5073, Pg35, Ng5084, Ng5077 }; + assign n3982 = 64'h2aaaaaaaaaaaaaaa >> { Pg17607, Pg17739, n5932, Pg35, Ng6035, Ng6040 }; + assign n3997 = 16'h0002 >> { n4685, Ng5869, Ng5857, Pg35 }; + assign n4077 = 16'h22a2 >> { n4173, n5382, Pg35, Ng1274 }; + assign n4097 = 16'h22a2 >> { n5516, n5140, Pg35, Ng930 }; + assign n4107 = 4'h8 >> { Pg35, Pg6745 }; + assign n4197_1 = 16'h0002 >> { n4772, Ng3857, Ng3869, Pg35 }; + assign n4202 = 64'ha820a8a8a8a0a8a8 >> { Ng513, Ng518, n4251, Ng499, n4250_1, Pg35 }; + assign n4221 = 64'h0000000000000002 >> { n4296, n4299_1, Ng4646, Ng4681, Ng4674, Pg35 }; + assign n994 = 16'h80a2 >> { Pg16718, Pg11349, Pg13895, n6090 }; + assign n6090 = 16'h0002 >> { Pg16624, Pg14421, Pg16603, Pg35 }; + assign n4329 = 32'd145262760 >> { Ng1495, Ng1442, n5033_1, Ng1489, Pg35 }; + assign n4377 = 16'h2aaa >> { n5951, Pg35, Ng3338, Ng3343 }; + assign n4721 = 16'h0002 >> { n4203, Ng6215, Ng6203, Pg35 }; + assign n4765 = 16'h0002 >> { Ng4871, Ng4864, Ng4836, n5249 }; + assign n4969 = 16'h8828 >> { n4210, Ng732, n6096, Pg35 }; + assign n6096 = 16'h6996 >> { n6097, Ng255, Ng225, Ng232 }; + assign n6097 = 16'h6996 >> { Ng239, Ng269, Ng262, Ng246 }; + assign n986 = 16'h80a2 >> { Pg16775, Pg11418, Pg13966, n6099 }; + assign n6099 = 16'h0002 >> { Pg16693, Pg14518, Pg16659, Pg35 }; + assign n5043 = 32'd134742536 >> { n5858, Pg12923, Ng1322, Ng1395, Pg35 }; + assign n5180 = 64'h20202020202020aa >> { n6103_1, n4313, n6102, Ng1312, n4312, Pg35 }; + assign n6102 = 32'd707439146 >> { n4314_1, Ng1389, Ng1361, Ng1373, Ng1351 }; + assign n6103_1 = 32'd357913941 >> { Ng1367, Ng1345, n4314_1, Ng1379, Ng1351 }; + assign n5380 = 32'd4202347130 >> { Ng1395, Pg12923, Pg35, Pg19357, Ng1404 }; + assign n5592 = 16'haa28 >> { n4915, Ng1514, Pg7946, Pg35 }; + assign n947 = 16'h80a2 >> { Pg17778, Pg12470, Pg14828, n6107 }; + assign n6107 = 16'h0002 >> { Pg13099, Pg17722, Pg17688, Pg35 }; + assign n5742 = 16'h2aaa >> { n5929, Pg35, Ng6381, Ng6386 }; + assign n5973 = 8'ha8 >> { Ng2932, Ng2999, Pg35 }; + assign n6123 = 64'h2aaaaaaaaaaaaaaa >> { Pg17519, Pg17674, n5938_1, Pg35, Pg25219, Ng5348 }; + assign n6173 = 64'h2aaaaaaaaaaaaaaa >> { n4306, Ng4340, Ng4633, n4307, n5713, Pg35 }; + assign n6482_1 = 64'h0020002800280028 >> { Ng4322, Ng4332, n4239, Ng4311, n4304_1, Pg35 }; + assign n6585_1 = 64'h2aaaaaaaaaaaaaaa >> { Ng5689, Pg17580, Pg17711, Pg35, n5935, Ng5694 }; + assign n990 = 16'h80a2 >> { Pg16744, Pg11388, Pg13926, n6115 }; + assign n6115 = 16'h0002 >> { Pg14451, Pg16656, Pg16627, Pg35 }; + assign n6492_1 = 4'h2 >> { Pg35, Ng2975 }; + assign n6196_1 = 4'h2 >> { Pg35, Ng4392 }; + assign n6555 = 8'h6a >> { Pg35, Pg10306, Ng4534 }; + assign n4250 = 8'ha6 >> { Ng890, Pg35, Ng862 }; + assign n2185 = 8'h6a >> { Pg35, Ng5092, Ng5084 }; + assign n6447_1 = 8'h6a >> { Pg35, Ng1548, Ng1430 }; + assign n687_1 = 4'h6 >> { n5955, Ng1333 }; + assign n1552 = 8'h6a >> { Pg35, Ng1205, Ng1087 }; + assign n691 = 8'h6a >> { n5963_1, Pg35, Ng990 }; + assign n1902 = 4'h8 >> { Pg35, Pg113 }; + assign n1691 = 4'h8 >> { Pg35, Pg125 }; + assign Pg12833 = 2'h1 >> Pg5; + assign Pg23652 = 2'h1 >> Ng2834; + assign Pg23759 = 2'h1 >> Ng2831; + assign Pg23612 = 2'h1 >> Pg21292; + assign Pg23002 = 2'h1 >> Ng37; + assign n6132 = 64'h0222222212323232 >> { Ng1046, Ng1030, Ng1018, Ng1008, Ng969, n4320 }; + assign n6133_1 = 32'd1499287893 >> { Ng5268, Ng5260, Ng5357, Pg17519, Ng5297 }; + assign n6134 = 32'd3581968512 >> { Pg14662, Ng5236, Pg17674, Ng5252, Ng5357 }; + assign n6135 = 64'h9f9006009ff60666 >> { n6134, n4416_1, Ng5297, n6133_1, Pg25219, Pg12238 }; + assign n6136 = 16'h0222 >> { n4415, Ng5272, n4406_1, n6135 }; + assign n6137 = 64'hd898501050105010 >> { Pg17743, Ng6295, Ng6279, Pg14705, Ng6381, Ng6395 }; + assign n6138_1 = 64'h5151517b5555557f >> { Ng6287, n4462, n4461_1, Ng6336, n6137, Ng6381 }; + assign n6139 = 64'h8080808080808088 >> { n4463, n4464, n4465, Ng6381, n4456_1, n6138_1 }; + assign n6140 = 64'hd898501050105010 >> { Pg17715, Ng5949, Ng5933, Pg14673, Ng6035, Ng6049 }; + assign n6141 = 64'h0002000200021113 >> { n4543, n4542, n4545, n4546_1, n6146, Ng6035 }; + assign n6142 = 64'h2a007b002a007f00 >> { Ng5941, n4541_1, n6141, Ng5990, n6140, Ng6035 }; + assign n6143_1 = 8'h2a >> { n4504, Ng5965, n6142 }; + assign n6144 = 32'd2796462762 >> { Ng5953, Ng5961, Ng6049, Pg17607, Ng5990 }; + assign n6145 = 32'd3581968512 >> { Pg14738, Ng5921, Pg17739, Ng5937, Ng6049 }; + assign n6146 = 64'h99f00960fff66f66 >> { n4544, n6145, n6144, Ng5990, Ng6035, Pg12350 }; + assign n6147 = 32'd16122110 >> { Ng4737, Ng4801, Ng4776, Ng4785, Ng4709 }; + assign n6148_1 = 64'h0014041045554555 >> { n6147, n4664, n2838, Ng4793, Ng4776, n4665 }; + assign n6149 = 64'ha888a000a989a101 >> { Ng4674, Ng4831, Pg21245, Ng4646, Ng4681, n4665 }; + assign n6150 = 32'd16122110 >> { Ng4927, Ng4991, Ng4966, Ng4975, Ng4899 }; + assign n6151 = 64'hffd7f7df75557555 >> { n6150, n4734, n6655, Ng4983, Ng4966, n4735 }; + assign n2066 = 4'h8 >> { n6151, n4736_1 }; + assign n6153_1 = 32'd2796462762 >> { Ng3953, Ng3961, Ng4054, Pg16659, Ng3990 }; + assign n6154 = 32'd3581968512 >> { Pg13966, Ng3921, Pg16775, Ng3937, Ng4054 }; + assign n6155 = 64'h66000f09f6909f99 >> { n6154, n6153_1, n4846, Ng3990, Ng4040, Pg11418 }; + assign n6156 = 16'h0222 >> { n4580, Ng3965, n4837, n6155 }; + assign n6157 = 32'd3581968512 >> { Ng6621, Pg14828, Ng6637, Pg17778, Ng6741 }; + assign n6158_1 = 32'd1499287893 >> { Ng6653, Ng6645, Ng6741, Pg17688, Ng6682 }; + assign n6159 = 64'h9900f0609f06f666 >> { n6157, n6158_1, n5000, Ng6682, Pg12470, Ng6727 }; + assign n6160 = 16'h0222 >> { n4999, Ng6657, n4989, n6159 }; + assign n6161 = 64'he0c0f0d0f0d0f0d0 >> { Pg13865, Ng3239, n5009, n5010_1, Ng3288, Ng3352 }; + assign n6162 = 32'd1059727914 >> { n5016, n5015, n5003, Ng3263, n5006_1 }; + assign n6163_1 = 64'h202020202020a820 >> { n5012, n5013, n5014_1, n6161, Ng3338, n6162 }; + assign n6164 = 64'hd898501050105010 >> { Ng5603, Pg17678, Ng5587, Pg14635, Ng5689, Ng5703 }; + assign n6165 = 64'h5151517b5555557f >> { Ng5595, n5334, n5333, Ng5644, n6164, Ng5689 }; + assign n6166 = 64'h8080808080808088 >> { n5332, n5335_1, n5336, Ng5689, n5327, n6165 }; + assign n6167 = 64'h77777fff7fff7fff >> { Ng2864, n5641, Ng2860, n5627_1, Ng48, n5626 }; + assign n6168_1 = 64'h0002020200222222 >> { Ng582, Ng2922, n5642_1, n5639, n5646, n6167 }; + assign n6169 = 64'h484048404a424840 >> { Ng1291, Ng1448, Ng4717, Ng48, Ng50, Ng16 }; + assign n6170 = 64'ha8a8a020a020a020 >> { Ng3151, n5640, Ng5507, n5627_1, Ng48, n4052 }; + assign n6171 = 64'h77777fff7fff7fff >> { Ng3502, n5640, Ng5853, n5627_1, Ng48, n5645 }; + assign n6172 = 16'h0002 >> { n5654, n5656, n5657_1, n5655 }; + assign n3061 = 64'h5ddddddddddddddd >> { n6171, n5648, n5650, n5652_1, n4052, n6172 }; + assign n6174 = 64'hff08080808080808 >> { Ng2882, Ng48, n5641, Ng51, Ng2955, n5638 }; + assign n6175 = 64'h0000077707770777 >> { n6174, n5626, n5635, Ng613, Ng586, n5639 }; + assign n6176 = 64'h0602464204004440 >> { Ng4172, Ng4927, Ng1291, Ng50, Ng16, Ng48 }; + assign n6177 = 64'h77777fff7fff7fff >> { Ng3853, n5640, Ng6199, n5627_1, Ng48, n5645 }; + assign n6178_1 = 32'd131586 >> { n5666, Ng956, n5667_1, n5668, n5669 }; + assign n3202 = 64'h5ddddddddddddddd >> { n6177, n5662_1, n5663, n5665, n4052, n6178_1 }; + assign n6180 = 64'h1111133313331333 >> { n5641, Ng4912, Ng4722, n5627_1, n5646, n5644 }; + assign n1789 = 64'h5ddddddddddddddd >> { n6180, n5670, n5671, n5673, n4052, n6203 }; + assign n6182_1 = 64'h80808080ff808080 >> { Ng48, n5627_1, Pg21292, Ng2970, Ng51, n5638 }; + assign n6183 = 64'h4606420244044000 >> { Ng1283, Ng4146, Ng2138, Ng50, Ng48, Ng16 }; + assign n6184 = 64'h1716131215141110 >> { n4783, n4866, Pg25259, Ng528, Ng504, Ng518 }; + assign n6185 = 64'heec4c4c4c4c4c4c4 >> { Ng2704, Ng52, n5647_1, Ng2145, n5627_1, Ng50 }; + assign n6186_1 = 64'hdfd7dff7dfdfdfff >> { Ng1287, Ng4157, Ng50, Ng48, Ng16, n6185 }; + assign n2001 = 64'hddfdfdfdfdfdfdfd >> { n6186_1, n5682_1, n5685, n4052, n5687_1, n5688 }; + assign n6188 = 64'h1111133313331333 >> { n5631, Pg20652, Ng749, n5626, n5646, n5634 }; + assign n6189 = 64'h2202260620002404 >> { Ng4176, Ng1296, Ng2130, Ng50, Ng16, Ng48 }; + assign n6190 = 64'h22a222a266e622a2 >> { Ng1926, Ng1917, Ng2060, Ng2051, Ng2748, Ng2741 }; + assign n6191_1 = 32'd134765832 >> { Ng2217, Ng2208, Ng2351, Ng2342, Ng2741 }; + assign n6192 = 64'h7363514172625040 >> { Pg25167, n6191_1, n5247, n6190, Ng2748, Ng2756 }; + assign n2694 = 8'hd5 >> { n4373, n6192, n5696 }; + assign n6660 = 32'd2158135466 >> { n6148_1, n4665, Ng4688, n6149, Pg35 }; + assign n6195 = 64'h007f7f7f7f7f7f7f >> { n4193, n5629, n5645, Ng4907, n5641, n5644 }; + assign n6196 = 64'h6a406a407f556a40 >> { Pg53, Ng8, n6195, n6169, n6170, n4052 }; + assign n4112 = 32'd1861152494 >> { n5624, n5632_1, n6168_1, n4052, n6196 }; + assign n6198 = 64'h57135757f733f7f7 >> { n5641, n5644, Ng4737, Ng50, n5627_1, n6176 }; + assign n6199 = 64'h1151115199d91151 >> { n5646, n6198, Pg53, Ng16, n5661, n4052 }; + assign n2608 = 32'd1861152494 >> { n5658, n5659, n6175, n4052, n6199 }; + assign n6201 = 64'hbabababa10bababa >> { Ng947, Ng1135, n5629, Ng1478, Ng1291, Ng50 }; + assign n6202 = 64'h545474f474f474f4 >> { Ng6545, n5640, Ng5160, Ng50, n5627_1, Ng48 }; + assign n6203 = 64'h00000000f7dfdfdf >> { n5676, n6201, n6202, Ng50, Ng16, n4052 }; + assign n6204 = 64'h0a2a0a2a2a2a0a2a >> { Ng785, Pg35, n5629, n5626, n6182_1, n5679 }; + assign n6205_1 = 64'h0015151515151515 >> { n5631, Pg127, n5629, Ng604, n5674, n5653 }; + assign n2848 = 64'h5ddddddddddddddd >> { n6205_1, n6204, n5677_1, n5678, n4052, n6208 }; + assign n6207 = 64'h77777fff7fff7fff >> { Ng4249, n5641, Ng2697, n5640, Ng48, n5645 }; + assign n6208 = 32'd176851594 >> { n6183, n5627_1, n4052, n6207, n5680 }; + assign n6209 = 64'h0040004022620040 >> { Ng2599, Ng2629, Ng2331, Ng2361, Ng504, Ng518 }; + assign n6210_1 = 64'h57f757f7577757f7 >> { Ng2197, Ng2227, n6209, Ng528, n6184, n4200 }; + assign n6211 = 32'd2004289399 >> { Ng2465, n4568, Ng2495, n4812, n4383 }; + assign n5717 = 4'h7 >> { n6210_1, n6211 }; + assign n6213 = 64'h55dfdfdfdfdfdfdf >> { Ng48, Ng2689, n5640, n5629, Ng952, n5645 }; + assign n6214 = 64'h77777fff7fff7fff >> { Ng2878, n5626, Ng4253, n5645, n5641, Ng48 }; + assign n6215_1 = 64'h0008080800888888 >> { Ng572, n5627_1, n6189, n5639, n6214, n6213 }; + assign n5063 = 64'haeeeeeeeeeeeeeee >> { n6215_1, n5689, n5690, n6188, n4052, n5691 }; + assign n4120 = 1'h0; + assign n6550 = Pg9555; + assign n6521 = Pg8789; + assign n6186 = Pg16686; + assign n5908 = Pg9553; + assign n5884_1 = Pg33079; + assign n5835 = Ng4520; + assign n5756 = Pg8353; + assign n5597 = Ng26885; + assign n5468 = Pg8235; + assign n5439 = Pg33435; + assign n5271 = Pg8291; + assign n5199 = Pg9019; + assign n5111_1 = Pg17764; + assign n5072 = Pg7540; + assign n5018 = Pg14167; + assign n5014 = Pg7243; + assign n5006 = Pg8132; + assign n4997_1 = Pg16748; + assign n4983 = Ng6972; + assign n4978_1 = Pg13272; + assign n4869 = Pg18881; + assign n4386 = Pg8358; + assign n4343 = Pg12919; + assign n4284 = Pg8279; + assign n4245 = Pg8719; + assign n4216_1 = Pg10500; + assign n3847 = Pg13259; + assign n3803 = Pg7260; + assign n3734 = Pg17678; + assign n3725_1 = Pg10306; + assign n3553_1 = Ng10384; + assign n3544 = Pg7257; + assign n3510 = Pg9743; + assign n3246 = Ng26959; + assign n3242 = Ng6974; + assign n3197 = Pg8416; + assign n3188 = Pg9251; + assign n3075_1 = Pg12923; + assign n2996 = Pg9497; + assign n2952 = Ng26936; + assign n2798 = Pg8475; + assign n2684 = Pg9682; + assign n2670 = Pg7245; + assign n2666 = Pg17423; + assign n2508 = Pg10122; + assign n2484 = Pg8839; + assign n2400 = Pg8344; + assign n2381 = Pg17400; + assign n2357 = Pg16722; + assign n2318 = Pg17639; + assign n2224 = Pg11678; + assign n2125 = Pg9617; + assign n1921 = Ng26960; + assign n1872 = Pg10527; + assign n1853 = Pg8215; + assign n1397 = Pg17743; + assign n1338 = Ng4571; + assign n1313 = Pg8920; + assign n1274 = Pg17715; + assign n1210 = Pg9048; + assign n1117_1 = Pg7916; + assign n1114 = Pg7946; + assign n1107 = Pg11447; + assign n1104 = Pg8783; + assign n1101 = Pg8784; + assign n1098 = Pg8785; + assign n1095 = Pg8786; + assign n1092 = Pg8787; + assign n1089 = Pg8788; + assign n1082_1 = Pg8917; + assign n1079 = Pg11770; + assign n1076 = Pg8915; + assign n1073 = Pg8916; + assign n1070 = Pg8870; + assign n1067 = Pg8918; + assign n1064 = Pg8919; + assign n1057 = Pg12368; + assign n978 = Pg12184; + assign n931 = Pg17577; + assign n928 = Pg17604; + assign n925 = Pg17646; + assign n922 = Pg17685; + assign n919 = Pg17722; + assign n916 = Pg19334; + assign n913 = Pg19357; + assign n910 = Pg16874; + assign n907 = Pg16924; + assign n904 = Pg11349; + assign n901 = Pg16955; + assign n898 = Pg11388; + assign n895 = Pg11418; + assign n892 = Pg14217; + assign n889 = Pg14096; + assign n886 = Pg14125; + assign n883 = Pg14147; + assign n876 = Pg14189; + assign n873 = Pg14201; + assign n870 = Pg16624; + assign n867 = Pg16656; + assign n864 = Pg16693; + assign n861 = Pg17787; + assign n858 = Pg17813; + assign n855 = Pg12238; + assign n852 = Pg17819; + assign n849 = Pg12300; + assign n846 = Pg17845; + assign n843 = Pg12350; + assign n840 = Pg17871; + assign n837 = Pg12422; + assign n834 = Pg12470; + assign n831 = Pg16718; + assign n828 = Pg16603; + assign n825 = Pg16744; + assign n822 = Pg16627; + assign n819 = Pg16775; + assign n816 = Pg13865; + assign n813 = Pg16659; + assign n810 = Pg13895; + assign n807 = Pg13881; + assign n804 = Pg13926; + assign n801 = Pg13906; + assign n798 = Pg13966; + assign n795 = Pg14421; + assign n792 = Pg14451; + assign n789 = Pg14518; + assign n782 = Pg17291; + assign n775 = Pg17316; + assign n772 = Pg17320; + assign n769 = Pg17404; + assign n766 = Pg17674; + assign n763 = Pg17519; + assign n760 = Pg17711; + assign n757 = Pg17580; + assign n754 = Pg17739; + assign n751 = Pg14597; + assign n748 = Pg17607; + assign n745 = Pg17760; + assign n742 = Pg14662; + assign n739 = Pg14635; + assign n736 = Pg17649; + assign n733 = Pg17778; + assign n730 = Pg14694; + assign n727 = Pg14673; + assign n724 = Pg17688; + assign n721 = Pg14738; + assign n718 = Pg14705; + assign n715 = Pg14779; + assign n712_1 = Pg14749; + assign n709 = Pg14828; + assign n706 = Pg13039; + assign n703 = Pg13049; + assign n700 = Pg13068; + assign n697 = Pg13085; + assign n694 = Pg13099; + assign Pg8403 = Pg8353; + assign Pg8283 = Pg8235; + assign Pg8178 = Pg8132; + assign Pg34956 = Pg34839; + assign Pg34788 = Pg33894; + assign Pg34597 = n4120; + assign Pg34437 = Pg31665; + assign Pg34436 = Pg31656; + assign Pg34435 = Pg31521; + assign Pg34240 = n4120; + assign Pg34239 = n4120; + assign Pg34238 = n4120; + assign Pg34237 = n4120; + assign Pg34236 = n4120; + assign Pg34235 = n4120; + assign Pg34234 = n4120; + assign Pg34233 = n4120; + assign Pg34232 = n4120; + assign Pg33959 = Pg28753; + assign Pg33950 = n4120; + assign Pg33949 = n4120; + assign Pg33948 = n4120; + assign Pg33947 = n4120; + assign Pg33946 = n4120; + assign Pg33945 = n4120; + assign Pg33533 = Pg27831; + assign Pg32975 = Pg26801; + assign Pg32454 = n4120; + assign Pg32429 = n4120; + assign Pg31863 = Pg25167; + assign Pg31862 = Pg25259; + assign Pg31861 = Pg25219; + assign Pg31860 = Pg25114; + assign Pg30332 = Pg23683; + assign Pg30331 = Pg23759; + assign Pg30330 = Pg23652; + assign Pg30329 = Pg23612; + assign Pg30327 = Pg23002; + assign Pg29221 = Pg21292; + assign Pg29220 = Pg21245; + assign Pg29219 = Pg20654; + assign Pg29218 = Pg18881; + assign Pg29217 = Pg21270; + assign Pg29216 = Pg21176; + assign Pg29215 = Pg20901; + assign Pg29214 = Pg20652; + assign Pg29213 = Pg20557; + assign Pg29212 = Pg20899; + assign Pg29211 = Pg20763; + assign Pg29210 = Pg20049; + assign Pg25590 = n4120; + assign Pg25589 = n4120; + assign Pg25588 = n4120; + assign Pg25587 = n4120; + assign Pg25586 = n4120; + assign Pg25585 = n4120; + assign Pg25584 = n4120; + assign Pg25583 = n4120; + assign Pg25582 = n4120; + assign Pg24185 = Pg44; + assign Pg24184 = Pg135; + assign Pg24183 = Pg134; + assign Pg24182 = Pg127; + assign Pg24181 = Pg126; + assign Pg24180 = Pg125; + assign Pg24179 = Pg124; + assign Pg24178 = Pg120; + assign Pg24177 = Pg116; + assign Pg24176 = Pg115; + assign Pg24175 = Pg114; + assign Pg24174 = Pg113; + assign Pg24173 = Pg100; + assign Pg24172 = Pg99; + assign Pg24171 = Pg92; + assign Pg24170 = Pg91; + assign Pg24169 = Pg90; + assign Pg24168 = Pg84; + assign Pg24167 = Pg73; + assign Pg24166 = Pg72; + assign Pg24165 = Pg64; + assign Pg24164 = Pg57; + assign Pg24163 = Pg56; + assign Pg24162 = Pg54; + assign Pg24161 = Pg53; + assign Pg24151 = n4120; + assign Pg23190 = n4120; + assign Pg21698 = Pg36; + assign Pg18101 = Pg6746; + assign Pg18100 = Pg6751; + assign Pg18099 = Pg6745; + assign Pg18098 = Pg6744; + assign Pg18097 = Pg6747; + assign Pg18096 = Pg6750; + assign Pg18095 = Pg6749; + assign Pg18094 = Pg6748; + assign Pg18092 = Pg6753; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act b/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act new file mode 100644 index 000000000..bd0a435be --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act @@ -0,0 +1,644 @@ +i_0_ 0.498400 0.491000 +i_1_ 0.516600 0.502800 +i_2_ 0.500600 0.506800 +i_3_ 0.508600 0.507200 +i_4_ 0.509000 0.494000 +i_5_ 0.508600 0.490200 +i_6_ 0.502400 0.498400 +i_7_ 0.506200 0.493400 +i_8_ 0.488000 0.502400 +i_9_ 0.507000 0.499400 +i_10_ 0.485600 0.503800 +i_11_ 0.505200 0.499400 +i_12_ 0.496800 0.500000 +i_13_ 0.498600 0.506800 +i_14_ 0.505000 0.504200 +i_15_ 0.494600 0.491200 +i_16_ 0.495800 0.501200 +i_17_ 0.499600 0.495000 +i_18_ 0.507000 0.507000 +i_19_ 0.501400 0.504200 +i_20_ 0.484400 0.501200 +i_21_ 0.495000 0.497800 +i_22_ 0.502600 0.491200 +i_23_ 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a/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif b/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif new file mode 100644 index 000000000..b9fc267ea --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif @@ -0,0 +1,1752 @@ +# Benchmark "seq" written by ABC on Tue Mar 12 09:32:14 2019 +.model seq +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ + i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ \ + i_25_ i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ \ + i_37_ i_38_ i_39_ i_40_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ \ + o_12_ o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ \ + o_24_ o_25_ o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ +.names n592 n190 n185 n163 n119 n213 o_0_ +111110 0 +.names i_11_ i_15_ n81 n86 n91 i_17_ n80 +11-1-- 0 +11--10 0 +--1--- 0 +.names n85 n84 n82 n83 n81 +1110 1 +.names i_15_ i_9_ i_5_ i_7_ i_11_ i_12_ n82 +10001- 1 +1000-1 1 +.names i_17_ i_16_ n83 +11 1 +.names i_37_ i_39_ i_38_ i_34_ i_36_ i_35_ n84 +100000 1 +.names i_33_ i_31_ i_32_ n85 +100 1 +.names n87 n88 i_9_ n89 n90 n86 +1101- 1 +110-1 1 +.names i_5_ i_7_ n87 +00 1 +.names i_33_ i_31_ i_16_ i_32_ n88 +1000 1 +.names i_40_ i_38_ i_34_ i_36_ i_35_ n89 +10000 1 +.names i_39_ i_34_ i_36_ i_37_ i_35_ n90 +10000 1 +.names n87 n93 n92 i_9_ n91 +1110 1 +.names i_33_ i_31_ i_34_ i_32_ i_36_ i_35_ n92 +100000 1 +.names i_39_ i_38_ n93 +11 1 +.names i_15_ n96 n85 n84 n95 n94 +11111 1 +.names i_5_ i_7_ i_11_ i_12_ n95 +001- 1 +00-1 1 +.names i_17_ i_16_ n96 +00 1 +.names n99 i_36_ n100 n98 n97 +1000 1 +.names i_39_ i_38_ i_37_ n98 +001 0 +110 0 +.names i_34_ i_33_ i_32_ i_7_ i_35_ n99 +11000 1 +.names i_2_ i_3_ i_4_ i_1_ n100 +0000 1 +.names n103 n92 n102 n101 +110 1 +.names i_7_ i_5_ i_12_ i_11_ i_15_ n102 +1---- 1 +-1--- 1 +--111 1 +.names i_38_ i_39_ i_40_ i_37_ n103 +1100 1 +.names n88 n106 n87 i_9_ n105 n104 +11100 1 +.names i_36_ i_39_ i_37_ i_40_ i_38_ n105 +010-- 0 +0--10 0 +.names i_15_ i_12_ i_34_ i_35_ n106 +1100 1 +.names i_12_ i_11_ n107 +00 1 +.names i_33_ i_31_ i_34_ i_32_ n108 +1000 1 +.names i_13_ i_5_ i_7_ n109 +100 1 +.names i_35_ i_36_ i_37_ i_39_ i_38_ i_40_ n110 +0001-- 0 +00100- 0 +00--01 0 +.names i_33_ i_31_ i_34_ i_32_ i_35_ n111 +10000 1 +.names n91 n117 n116 n113 n115 i_17_ n112 +10---- 0 +1---10 0 +--11-- 0 +.names n87 i_12_ n114 i_24_ n113 +1110 1 +.names i_15_ i_35_ i_33_ i_34_ i_32_ n114 +11100 1 +.names i_15_ i_12_ n115 +11 1 +.names i_39_ i_38_ i_36_ i_37_ n116 +1100 1 +.names i_40_ i_37_ n117 +10 1 +.names n87 n114 i_22_ i_11_ i_12_ n118 +1101- 0 +110-1 0 +.names n145 n128 n158 n120 i_23_ n119 +110-1 1 +1110- 1 +.names n116 n122 n121 n126 i_12_ n120 +11--- 1 +1-110 1 +.names i_11_ n87 n121 +11 1 +.names i_21_ n125 n124 n123 n122 +1111 1 +.names i_35_ i_34_ n123 +10 1 +.names i_15_ i_5_ i_11_ i_12_ n124 +101- 1 +10-1 1 +.names i_33_ i_32_ i_7_ n125 +100 1 +.names n96 i_15_ n127 i_31_ i_32_ n126 +11100 1 +.names i_33_ i_34_ i_35_ n127 +100 1 +.names n135 n133 n129 n138 n141 n144 n128 +0000-- 1 +000-0- 1 +000--0 1 +.names n82 n131 i_18_ n132 n116 n129 +1101- 1 +110-1 1 +.names i_33_ i_34_ i_32_ n130 +100 1 +.names i_35_ i_33_ i_34_ i_32_ n131 +1100 1 +.names i_40_ i_35_ i_37_ i_39_ i_38_ i_36_ n132 +111000 1 +.names n114 i_12_ n87 i_24_ n134 n133 +11100 1 +.names i_36_ i_39_ i_38_ i_37_ i_40_ n134 +0000- 0 +000-1 0 +.names n82 n137 n136 n88 i_34_ n135 +11110 1 +.names i_38_ i_40_ n136 +10 1 +.names i_36_ i_37_ i_35_ n137 +000 1 +.names n140 n139 n138 +11 1 +.names i_15_ i_5_ i_7_ i_11_ i_12_ n139 +1001- 1 +100-1 1 +.names i_21_ i_22_ n140 +11 1 +.names i_40_ i_37_ n143 n142 n141 +1111 1 +.names i_39_ i_38_ i_36_ n142 +000 1 +.names i_35_ i_33_ i_34_ n143 +110 1 +.names i_24_ i_32_ n144 +10 1 +.names n155 n153 n149 n146 n145 +0000 1 +.names i_2_ n148 n130 n147 n146 +1110 1 +.names i_40_ i_36_ i_38_ i_39_ i_37_ i_35_ n147 +111010 0 +111100 0 +.names i_0_ i_7_ n148 +10 1 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n529 n241 n136 i_37_ n236 i_39_ n528 +0----- 0 +-1---- 0 +--1110 0 +.names n400 n212 n117 i_11_ n437 n529 +0---- 0 +-1111 0 +.names i_40_ i_39_ i_38_ i_37_ n207 n172 n530 +10011- 0 +11101- 0 +1111-1 0 +.names n284 i_5_ i_36_ n532 n244 i_15_ n531 +110-0- 1 +110--0 1 +1--1-- 1 +.names i_0_ i_36_ n100 i_37_ n93 n179 n532 +11101- 1 +1111-1 1 +.names n83 n268 n85 n84 n244 n533 +11--- 1 +1-110 1 +.names i_31_ i_15_ i_32_ n534 +000 1 +.names n96 n536 n268 n84 n85 n244 n535 +0-1--- 0 +0--110 0 +-0---- 0 +.names n108 n379 i_15_ n103 n220 n536 +110-- 0 +11-10 0 +.names n107 i_31_ n538 n537 +100 1 +.names i_36_ i_39_ i_37_ i_38_ i_35_ i_40_ n538 +0001-0 0 +00100- 0 +01000- 0 +010-01 0 +0--001 0 +.names n521 n540 n225 n522 i_40_ n539 +11--- 1 +1-110 1 +.names n434 n181 n282 n201 n540 +101- 1 +10-0 1 +.names n546 n542 n545 n142 n118 i_37_ n541 +001-1- 1 +001--0 1 +00-0-- 1 +.names n95 n543 n544 n542 +11- 1 +1-1 1 +.names i_23_ n103 n114 n223 n307 n270 n543 +011--- 1 +0--111 1 +.names i_15_ n256 n379 n96 n85 n544 +11111 1 +.names n113 n121 n114 i_24_ n545 +1--- 0 +-110 0 +.names n489 n116 n316 i_36_ n546 +01-- 1 +0-10 1 +.names n548 n342 n85 n212 n137 n547 +0---- 0 +-1111 0 +.names i_40_ n329 n208 n187 n548 +0--- 0 +-111 0 +.names n130 n239 i_38_ n148 n100 n549 +11110 1 +.names i_38_ i_39_ i_37_ n189 n199 n107 n550 +0101-0 0 +10010- 0 +101-1- 0 +1111-- 0 +.names n85 n552 n87 n210 i_34_ n297 n551 +11---- 1 +1-1100 1 +.names n553 n84 n256 n379 n552 +11-- 1 +1-11 1 +.names i_11_ n115 i_14_ i_5_ i_7_ n553 +11000 1 +.names n169 n556 n125 n555 n339 n167 n554 +00-0-- 1 +1-0--- 1 +1---10 1 +-00--- 1 +.names n342 n117 n131 n142 i_13_ n555 +11110 1 +.names n179 n111 n87 i_30_ i_29_ i_36_ n556 +111000 1 +.names i_37_ i_39_ i_38_ n200 i_40_ n189 n557 +0101-- 0 +100-11 0 +.names n560 n123 n479 n559 n430 n153 n558 +10-0-- 1 +110--0 1 +1-100- 1 +-0--1- 1 +.names n137 i_38_ n135 n474 n350 n201 n559 +10-1-- 1 +10--11 1 +111--- 1 +.names n125 n561 n343 n155 n560 +0--- 1 +-100 1 +.names i_40_ i_34_ i_38_ n223 i_39_ n150 n561 +0001-- 0 +000-11 0 +.names n138 n563 n397 i_25_ i_20_ o_10_ +10-1- 1 +10--1 1 +--0-- 1 +.names n170 n564 n305 i_24_ i_23_ n563 +000-- 1 +00-0- 1 +00--0 1 +.names n160 n123 n255 n161 n446 n564 +111-- 1 +11-1- 1 +11--1 1 +.names i_8_ n438 n171 n566 o_12_ +1110 1 +.names i_37_ n207 n136 n151 n172 n566 +0--11 0 +111-- 0 +.names n568 n572 n381 n575 n179 i_36_ n567 +000-0- 1 +000--1 1 +00-1-- 1 +.names n108 i_9_ n571 n569 n83 n570 n568 +101--- 1 +10-100 1 +.names i_15_ n107 n569 +10 1 +.names n174 i_38_ i_37_ i_16_ i_39_ i_40_ n570 +101-0- 0 +10-0-1 0 +1100-0 0 +11--1- 0 +1-001- 0 +.names n174 n93 n117 n571 +110 1 +.names n569 n573 n574 n251 n236 n140 n572 +11---- 1 +1-1--- 1 +1--110 1 +.names n96 n108 n426 n573 +110 1 +.names n131 n103 i_23_ i_36_ n574 +1100 1 +.names n111 i_28_ i_30_ i_29_ n575 +1011 0 +1100 0 +.names n577 i_36_ n320 n286 n236 n100 n576 +1----- 0 +-11--- 0 +---110 0 +.names n281 n188 n283 i_40_ i_38_ n577 +11100 1 +.names n579 n169 n150 n131 i_38_ n578 +1---- 0 +-1110 0 +.names n256 i_36_ n127 n292 i_39_ i_37_ n579 +111101 1 +111110 1 +.names n581 i_40_ i_38_ i_39_ i_9_ n220 n580 +10-0-- 1 +10--11 1 +1-0--- 1 +.names n582 i_37_ i_40_ i_39_ i_38_ n421 n581 +10000- 1 +10---1 1 +11001- 1 +1-11-1 1 +.names n415 i_7_ n582 +10 1 +.names i_38_ i_40_ i_39_ i_35_ n583 +1011 1 +1100 1 +.names i_15_ n244 i_39_ i_38_ n221 n117 n584 +11000- 1 +111101 1 +.names i_21_ n586 n203 i_24_ i_23_ n336 n585 +01---- 1 +0-1100 1 +.names n139 i_35_ n316 n160 n188 i_34_ n586 +111110 1 +.names i_35_ i_37_ i_39_ i_38_ i_36_ i_40_ n587 +100000 0 +10110- 0 +110001 0 +.names n589 n203 n162 i_23_ n336 o_31_ +0---- 1 +-1100 1 +.names n153 o_28_ n154 n574 n138 n113 n589 +0010-- 1 +001-0- 1 +00-0-0 1 +00--00 1 +.names n109 n110 n111 i_15_ n107 n108 n590 +1010-- 0 +10--11 0 +.names n97 n94 n104 n101 n116 n118 n591 +00000- 1 +0000-1 1 +.names n112 n591 n80 n590 n592 +1111 1 +.names i_33_ i_0_ i_34_ i_1_ i_4_ i_3_ n593 +1101-- 1 +110-1- 1 +110--1 1 +.names n593 n147 i_32_ i_7_ n594 +1000 1 +.names i_37_ i_39_ i_35_ i_40_ i_36_ i_38_ n595 +0011-1 0 +01101- 0 +011-10 0 +101001 0 +110111 0 +11110- 0 +.names n224 n595 i_37_ n222 n596 +111- 1 +11-0 1 +.names i_38_ i_39_ i_37_ i_34_ i_35_ i_40_ n597 +00001- 1 +00100- 1 +01000- 1 +011-01 1 +0-10-1 1 +0--001 1 +100-00 1 +11001- 1 +-10001 1 +.names n171 n107 n597 i_13_ i_5_ i_36_ n598 +111000 0 +.names n598 n226 n253 n247 n203 n599 +10--- 1 +1-000 1 +.names n230 n140 i_24_ n317 n315 n316 n600 +10--1- 0 +10---1 0 +1-01-- 0 +.names n309 n298 n278 n670 n294 n604 o_3_ +111100 0 +.names i_31_ n225 i_5_ i_32_ i_36_ n602 +10000 0 +.names n293 n107 i_11_ i_39_ i_38_ i_36_ n603 +10---- 1 +--1100 1 +.names n127 n602 n287 n290 n289 n603 n604 +10---- 1 +1-1--- 1 +1--111 1 +.names i_36_ i_35_ n197 i_39_ n242 n240 n605 +00---- 1 +111--1 1 +1-1-1- 1 +-0-1-- 1 +.names i_36_ i_37_ n289 n169 i_38_ n606 +0-111 1 +11--- 1 +.names n311 n310 n224 n130 n605 n606 n607 +111-0- 0 +111--0 0 +---0-- 0 +.names n180 i_40_ n349 n210 n231 i_37_ n608 +10--10 0 +1--1-- 0 +-01--- 0 +.names n337 n608 n675 n185 n672 n334 o_4_ +111110 0 +.names n157 n330 n178 n246 i_16_ i_17_ n610 +10---- 1 +--1100 1 +.names n326 n333 n327 i_17_ n171 n328 n611 +0-1--- 0 +0--110 0 +-1---- 0 +.names n329 n90 i_37_ n197 n180 i_39_ n612 +0-1--- 1 +110--- 1 +-01--- 1 +--0110 1 +.names i_13_ i_37_ n281 i_32_ n284 i_40_ n613 +00--11 1 +1110-- 1 +.names n342 n555 n613 i_39_ i_38_ i_36_ n614 +11---- 1 +1-1100 1 +.names i_38_ n90 n350 n180 i_37_ i_39_ n615 +011--- 0 +1--110 0 +.names n354 n615 n352 n351 i_40_ n111 n616 +1100-- 1 +1-0-0- 1 +-1-0-0 1 +----00 1 +.names n616 n370 n363 n620 n356 n376 o_6_ +111110 0 +.names n350 n84 n123 n166 i_39_ i_37_ n618 +11---- 1 +--1100 1 +.names n300 i_9_ i_15_ i_29_ n353 i_30_ n619 +110--- 1 +---100 1 +.names n361 n618 i_40_ n619 n111 n87 n620 +1----- 0 +-11--- 0 +---111 0 +.names n387 i_35_ n188 n316 n256 i_39_ n621 +1111-- 0 +111-11 0 +.names n267 n621 n624 n389 n130 n388 o_7_ +11100- 0 +1110-1 0 +.names i_39_ i_38_ i_40_ n232 n236 n382 n623 +011-1- 0 +011--1 0 +01-1-- 0 +1011-- 0 +.names n132 n387 n392 n623 n384 n380 n624 +0--100 1 +100--- 1 +.names i_37_ n169 n180 n239 i_40_ n107 n625 +0--111 1 +111--- 1 +.names i_37_ i_38_ n189 n625 i_39_ i_7_ n626 +0011-0 0 +001-0- 0 +11-1-- 0 +.names n626 n405 n402 i_39_ n403 o_16_ +1001- 0 +100-0 0 +.names i_39_ n189 i_40_ i_38_ i_37_ n404 n628 +011-0- 0 +0--111 0 +1101-- 0 +11--1- 0 +-1101- 0 +--0011 0 +.names n349 n417 n117 n123 n329 i_39_ n629 +1----- 0 +-1---- 0 +--1110 0 +.names n629 n412 n628 n418 n403 n630 +11100 1 +.names n636 i_39_ i_38_ i_37_ n450 i_40_ n631 +0001-- 1 +0110-1 1 +0---0- 1 +.names n451 n631 n435 n449 n444 n439 o_20_ +111000 0 +.names i_36_ n201 n196 n93 n117 i_34_ n633 +001--- 1 +1--110 1 +.names n438 i_32_ n282 n633 i_33_ i_35_ n634 +101--- 1 +10-110 1 +.names i_38_ i_39_ i_40_ i_37_ i_35_ i_13_ n635 +00001- 1 +0011-- 1 +00-011 1 +00-10- 1 +01-00- 1 +0-100- 1 +10000- 1 +1110-- 1 +.names n130 n453 n635 n107 i_7_ i_36_ n636 +11---- 1 +1-1100 1 +.names i_7_ i_34_ n458 n456 i_32_ n174 n637 +00-0-- 0 +00--10 0 +0-0--- 0 +.names n87 n454 n455 n150 n179 i_34_ n638 +11---- 1 +1-0--- 1 +1--110 1 +.names i_33_ n637 i_0_ n638 o_21_ +111- 0 +11-0 0 +.names i_37_ i_38_ i_40_ i_39_ n182 n100 n640 +00--1- 0 +010--- 0 +01-0-- 0 +100001 0 +1111-- 0 +.names n463 n640 i_37_ n174 n365 n197 n641 +001--- 1 +010--0 1 +0--0-- 1 +0---0- 1 +.names n475 n232 i_32_ n282 n151 n317 n642 +11--1- 0 +11---1 0 +1-01-- 0 +.names n483 n481 n480 n80 n478 n155 n643 +111100 1 +.names n492 n642 n643 i_7_ n238 o_25_ +1111- 0 +111-0 0 +.names n171 i_5_ n526 n527 i_6_ n530 n645 +110--- 0 +11-0-- 0 +1---10 0 +.names n650 n648 n528 n645 n678 o_34_ +11111 0 +.names i_35_ i_38_ i_39_ i_40_ i_37_ n291 n647 +000-1- 1 +001-0- 1 +00-1-- 1 +0-110- 1 +-1-0-1 1 +.names n533 n534 n647 i_33_ i_34_ i_36_ n648 +1----- 0 +-11100 0 +.names i_36_ n103 n150 n316 n221 i_5_ n649 +0---11 1 +11---- 1 +--11-- 1 +.names n130 i_9_ n535 n537 n649 i_35_ n650 +1--1-- 0 +1---10 0 +-10--- 0 +.names n180 i_39_ n117 n197 n196 n240 n651 +111--- 0 +1--110 0 +.names n658 n554 n483 n651 n184 n652 +11110 1 +.names n592 n558 n541 n652 n551 n656 o_5_ +111100 0 +.names n231 n180 n534 n250 n109 n142 n654 +11---- 1 +1-1110 1 +.names n142 i_40_ i_37_ n654 n118 n149 n655 +0----1 1 +1---0- 1 +-1---- 1 +--01-- 1 +.names n655 n550 n547 n549 n656 +0--- 0 +-110 0 +.names n281 n95 i_15_ i_39_ i_22_ i_21_ n657 +11110- 1 +1111-0 1 +.names i_32_ n557 n657 n293 n475 n282 n658 +0-11-- 0 +0---11 0 +-0---- 0 +.names n140 n277 n240 n196 n659 +00-- 0 +0-11 0 +.names n230 i_24_ n659 n208 n252 i_39_ n660 +10-1-- 0 +10--10 0 +1-0--- 0 +.names n578 n576 n660 n278 i_5_ n567 o_17_ +11111- 0 +1111-1 0 +.names n246 n584 i_37_ n583 n130 i_0_ n662 +10---- 1 +--1110 1 +.names n435 n580 n417 n662 i_7_ i_5_ o_22_ +1000-- 0 +100-1- 0 +100--0 0 +.names n160 n488 n139 n587 i_34_ i_22_ n664 +11---- 0 +1-1000 0 +.names n664 n585 n485 n155 o_30_ +1000 0 +.names n130 i_35_ n465 n464 n252 n421 n666 +10--10 0 +11-0-- 0 +1-0--- 0 +.names n681 n666 n466 n171 i_35_ n460 o_23_ +110-1- 0 +110--1 0 +11-0-- 0 +.names n208 n207 i_25_ n249 n124 i_22_ n668 +110--- 0 +---110 0 +.names n322 n324 n325 n323 n319 n169 n669 +0011-- 1 +001-0- 1 +00-1-0 1 +00--00 1 +.names n600 n669 n320 n171 n668 n318 n670 +1100-- 1 +110-10 1 +.names n246 n345 i_31_ n87 n297 n179 n671 +101--- 1 +1--111 1 +.names n347 n346 n238 n671 i_32_ i_7_ n672 +1100-- 1 +110-1- 1 +11-0-1 1 +11--11 1 +.names i_36_ i_37_ n131 n87 n332 i_39_ n673 +001100 0 +11---- 0 +.names i_40_ n612 i_38_ n673 i_37_ n183 n674 +100-1- 0 +110-0- 0 +1-000- 0 +1-0111 0 +.names n611 n674 n331 i_5_ i_31_ n610 n675 +1101-- 1 +110-0- 1 +110--0 1 +.names i_36_ i_37_ i_38_ i_39_ i_40_ i_35_ n676 +0000-0 1 +00-100 1 +0-110- 1 +11101- 1 +111--1 1 +.names n676 i_38_ n127 n286 i_33_ n192 n677 +10--1- 1 +11---1 1 +--11-- 1 +.names n531 n539 i_5_ n677 i_32_ i_0_ n678 +1----- 0 +-1---- 0 +--1100 0 +.names i_15_ n107 i_38_ i_9_ i_39_ i_16_ n679 +100--1 1 +10-1-- 1 +--11-- 1 +----0- 1 +.names n462 n130 n174 n679 i_5_ i_31_ n680 +10---- 1 +1-0--- 1 +1--100 1 +.names n641 n680 n459 n461 o_15_ n101 n681 +111000 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v b/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v new file mode 100644 index 000000000..90557242e --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v @@ -0,0 +1,1251 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module seq(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, i_39_, i_40_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, o_31_, o_32_, o_33_, o_34_); + input i_0_; + input i_10_; + input i_11_; + input i_12_; + input i_13_; + input i_14_; + input i_15_; + input i_16_; + input i_17_; + input i_18_; + input i_19_; + input i_1_; + input i_20_; + input i_21_; + input i_22_; + input i_23_; + input i_24_; + input i_25_; + input i_26_; + input i_27_; + input i_28_; + input i_29_; + input i_2_; + input i_30_; + input i_31_; + input i_32_; + input i_33_; + input i_34_; + input i_35_; + input i_36_; + input i_37_; + input i_38_; + input i_39_; + input i_3_; + input i_40_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + input i_9_; + wire n100; + wire n101; + wire n102; + wire n103; + wire n104; + wire n105; + wire n106; + wire n107; + wire n108; + wire n109; + wire n110; + wire n111; + wire n112; + wire n113; + wire n114; + wire n115; + wire n116; + wire n117; + wire n118; + wire n119; + wire n120; + wire n121; + wire n122; + wire n123; + wire n124; + wire n125; + wire n126; + wire n127; + wire n128; + wire n129; + wire n130; + wire n131; + wire n132; + wire n133; + wire n134; + wire n135; + wire n136; + wire n137; + wire n138; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n204; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n217; + wire n218; + wire n219; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n258; + wire n259; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n270; + wire n271; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n377; + wire n378; + wire n379; + wire n380; + wire n381; + wire n382; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n392; + wire n394; + wire n395; + wire n396; + wire n397; + wire n398; + wire n400; + wire n402; + wire n403; + wire n404; + wire n405; + wire n407; + wire n408; + wire n409; + wire n410; + wire n411; + wire n412; + wire n413; + wire n414; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n428; + wire n429; + wire n430; + wire n431; + wire n432; + wire n433; + wire n434; + wire n435; + wire n436; + wire n437; + wire n438; + wire n439; + wire n440; + wire n441; + wire n442; + wire n443; + wire n444; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n455; + wire n456; + wire n457; + wire n458; + wire n459; + wire n460; + wire n461; + wire n462; + wire n463; + wire n464; + wire n465; + wire n466; + wire n467; + wire n468; + wire n471; + wire n472; + wire n473; + wire n474; + wire n475; + wire n476; + wire n477; + wire n478; + wire n479; + wire n480; + wire n481; + wire n482; + wire n483; + wire n484; + wire n485; + wire n486; + wire n487; + wire n488; + wire n489; + wire n490; + wire n492; + wire n496; + wire n497; + wire n499; + wire n500; + wire n501; + wire n502; + wire n503; + wire n504; + wire n505; + wire n506; + wire n507; + wire n508; + wire n509; + wire n510; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n530; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n540; + wire n541; + wire n542; + wire n543; + wire n544; + wire n545; + wire n546; + wire n547; + wire n548; + wire n549; + wire n550; + wire n551; + wire n552; + wire n553; + wire n554; + wire n555; + wire n556; + wire n557; + wire n558; + wire n559; + wire n560; + wire n561; + wire n563; + wire n564; + wire n566; + wire n567; + wire n568; + wire n569; + wire n570; + wire n571; + wire n572; + wire n573; + wire n574; + wire n575; + wire n576; + wire n577; + wire n578; + wire n579; + wire n580; + wire n581; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n587; + wire n589; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n598; + wire n599; + wire n600; + wire n602; + wire n603; + wire n604; + wire n605; + wire n606; + wire n607; + wire n608; + wire n610; + wire n611; + wire n612; + wire n613; + wire n614; + wire n615; + wire n616; + wire n618; + wire n619; + wire n620; + wire n621; + wire n623; + wire n624; + wire n625; + wire n626; + wire n628; + wire n629; + wire n630; + wire n631; + wire n633; + wire n634; + wire n635; + wire n636; + wire n637; + wire n638; + wire n640; + wire n641; + wire n642; + wire n643; + wire n645; + wire n647; + wire n648; + wire n649; + wire n650; + wire n651; + wire n652; + wire n654; + wire n655; + wire n656; + wire n657; + wire n658; + wire n659; + wire n660; + wire n662; + wire n664; + wire n666; + wire n668; + wire n669; + wire n670; + wire n671; + wire n672; + wire n673; + wire n674; + wire n675; + wire n676; + wire n677; + wire n678; + wire n679; + wire n680; + wire n681; + wire n80; + wire n81; + wire n82; + wire n83; + wire n84; + wire n85; + wire n86; + wire n87; + wire n88; + wire n89; + wire n90; + wire n91; + wire n92; + wire n93; + wire n94; + wire n95; + wire n96; + wire n97; + wire n98; + wire n99; + output o_0_; + output o_10_; + output o_11_; + output o_12_; + output o_13_; + output o_14_; + output o_15_; + output o_16_; + output o_17_; + output o_18_; + output o_19_; + output o_1_; + output o_20_; + output o_21_; + output o_22_; + output o_23_; + output o_24_; + output o_25_; + output o_26_; + output o_27_; + output o_28_; + output o_29_; + output o_2_; + output o_30_; + output o_31_; + output o_32_; + output o_33_; + output o_34_; + output o_3_; + output o_4_; + output o_5_; + output o_6_; + output o_7_; + output o_8_; + output o_9_; + assign o_0_ = 64'hffffffff7fffffff >> { n213, n119, n163, n185, n190, n592 }; + assign n88 = 16'h0002 >> { i_32_, i_16_, i_31_, i_33_ }; + assign n178 = 4'h1 >> { i_7_, i_32_ }; + assign n179 = 8'h08 >> { i_39_, i_38_, i_40_ }; + assign n180 = 64'h0000000000000008 >> { i_35_, i_36_, i_7_, i_32_, i_33_, i_34_ }; + assign n181 = 64'hdffffffffffffff7 >> { i_35_, i_37_, i_36_, i_38_, i_34_, i_33_ }; + assign n182 = 16'h0008 >> { i_1_, i_3_, i_0_, i_2_ }; + assign n183 = 8'h80 >> { n107, n109, n131 }; + assign n184 = 32'd2147483648 >> { n107, n136, n108, n109, n137 }; + assign n185 = 32'd2863278762 >> { i_40_, n168, n189, i_39_, n186 }; + assign n186 = 64'h7d7d7d7d7dffffff >> { n183, n166, n131, i_38_, i_39_, n188 }; + assign n187 = 8'h02 >> { i_36_, i_34_, i_35_ }; + assign n89 = 32'd2 >> { i_35_, i_36_, i_34_, i_38_, i_40_ }; + assign n188 = 4'h1 >> { i_37_, i_36_ }; + assign n189 = 64'h0000000000000008 >> { i_35_, i_7_, i_32_, i_34_, i_33_, i_36_ }; + assign n190 = 32'd128 >> { n202, n211, n191, n204, n198 }; + assign n191 = 64'h0002ff020202ff02 >> { n197, n180, n196, n594, n193, n483 }; + assign n192 = 4'h2 >> { i_34_, i_33_ }; + assign n193 = 32'd128 >> { i_34_, i_22_, n160, n139, n132 }; + assign n194 = 64'h0000000000000008 >> { i_35_, i_36_, i_38_, i_40_, i_39_, i_37_ }; + assign n195 = 32'd66 >> { i_7_, i_5_, i_29_, i_30_, i_28_ }; + assign n196 = 4'h1 >> { i_37_, i_38_ }; + assign n197 = 8'h02 >> { i_1_, i_4_, i_0_ }; + assign n90 = 32'd2 >> { i_35_, i_37_, i_36_, i_34_, i_39_ }; + assign n198 = 64'h6e7f7f7f7f7f7f7f >> { i_11_, n189, n201, n199, i_38_, i_37_ }; + assign n199 = 4'h8 >> { n197, n200 }; + assign n200 = 64'h0000000000000080 >> { i_7_, i_32_, i_34_, i_36_, i_33_, i_35_ }; + assign n201 = 4'h8 >> { i_39_, i_40_ }; + assign n202 = 32'd526344 >> { i_18_, i_9_, i_19_, n139, n203 }; + assign n203 = 4'h8 >> { n130, n132 }; + assign n204 = 32'd2122219135 >> { n209, n206, n205, n136, n188 }; + assign n205 = 8'h08 >> { i_15_, n111, n109 }; + assign n206 = 32'd128 >> { i_26_, i_25_, n208, n125, n207 }; + assign n207 = 8'h08 >> { i_34_, i_36_, i_35_ }; + assign n91 = 16'h0080 >> { i_9_, n92, n93, n87 }; + assign n208 = 8'h01 >> { i_37_, i_38_, i_39_ }; + assign n209 = 4'h8 >> { n200, n210 }; + assign n210 = 16'h0008 >> { i_38_, i_40_, i_39_, i_37_ }; + assign n211 = 8'h80 >> { n117, n180, n212 }; + assign n212 = 4'h2 >> { i_38_, i_39_ }; + assign n213 = 8'h08 >> { n214, n124, n125 }; + assign n214 = 64'hdfdfd6dffffff6ff >> { n172, i_37_, n187, i_40_, i_38_, i_39_ }; + assign o_15_ = 4'h8 >> { i_7_, i_33_ }; + assign o_1_ = 32'd4160747511 >> { n130, n217, n254, n599, n228 }; + assign n217 = 32'd3120741002 >> { n226, n227, n225, n218, n596 }; + assign n92 = 64'h0000000000000002 >> { i_35_, i_36_, i_32_, i_34_, i_31_, i_33_ }; + assign n218 = 32'd1431655761 >> { i_14_, n221, i_5_, n115, n219 }; + assign n219 = 8'h02 >> { n220, n221, n124 }; + assign n220 = 4'h8 >> { i_11_, i_12_ }; + assign n221 = 8'h17 >> { i_16_, i_9_, i_17_ }; + assign n222 = 16'h0080 >> { i_11_, i_36_, n173, i_12_ }; + assign n223 = 8'h08 >> { i_36_, i_37_, i_35_ }; + assign n224 = 64'h7777777777770777 >> { n115, i_5_, n174, i_31_, n223, n212 }; + assign n225 = 8'h02 >> { i_38_, i_39_, i_37_ }; + assign n226 = 8'h01 >> { i_15_, i_5_, i_13_ }; + assign n227 = 64'hfffdfef8fffffef9 >> { i_40_, i_38_, i_35_, i_36_, i_37_, i_39_ }; + assign n93 = 4'h8 >> { i_38_, i_39_ }; + assign n228 = 32'd2155913856 >> { n265, n229, i_5_, n245, n234 }; + assign n229 = 32'd2004289399 >> { i_40_, n231, n232, n233, n230 }; + assign n230 = 8'h08 >> { i_36_, n124, n131 }; + assign n231 = 4'h2 >> { i_39_, i_38_ }; + assign n232 = 64'h0000000000000008 >> { i_35_, i_37_, i_36_, i_32_, i_33_, i_34_ }; + assign n233 = 16'h0008 >> { i_37_, i_39_, i_40_, i_24_ }; + assign n234 = 32'd1 >> { n235, n237, n238, n241, o_15_ }; + assign n235 = 16'h8000 >> { n93, n100, n117, n236 }; + assign n236 = 32'd8 >> { i_35_, i_36_, i_32_, i_33_, i_34_ }; + assign n237 = 64'h0000000000000008 >> { n225, i_36_, i_32_, i_5_, n127, i_31_ }; + assign n94 = 32'd2147483648 >> { n95, n84, n85, n96, i_15_ }; + assign n238 = 32'd2147483648 >> { n171, n239, n196, n240, i_34_ }; + assign n239 = 4'h2 >> { i_35_, i_36_ }; + assign n240 = 4'h1 >> { i_39_, i_40_ }; + assign n241 = 32'd32768 >> { n221, n242, n243, n244, i_15_ }; + assign n242 = 8'h80 >> { i_38_, i_39_, i_40_ }; + assign n243 = 64'h0000000000000002 >> { i_35_, i_37_, i_36_, i_32_, i_34_, i_33_ }; + assign n244 = 8'h80 >> { i_11_, i_12_, i_14_ }; + assign n245 = 16'h0080 >> { i_32_, n221, n246, i_31_ }; + assign n246 = 16'h0002 >> { i_35_, i_36_, i_34_, i_33_ }; + assign n247 = 4'h1 >> { n248, i_32_ }; + assign n95 = 16'h1110 >> { i_12_, i_11_, i_7_, i_5_ }; + assign n248 = 16'h0777 >> { n251, n250, n249, i_33_ }; + assign n249 = 64'h0000000000000080 >> { i_37_, i_36_, i_34_, i_35_, i_38_, i_39_ }; + assign n250 = 8'h02 >> { i_35_, i_36_, i_33_ }; + assign n251 = 16'h0080 >> { i_38_, i_37_, i_39_, i_40_ }; + assign n252 = 4'h2 >> { i_38_, i_40_ }; + assign n253 = 32'd128 >> { i_35_, i_40_, n231, n171, n188 }; + assign n254 = 32'd128 >> { n221, i_32_, n124, n255, n127 }; + assign n255 = 8'h80 >> { n188, n256, i_39_ }; + assign n256 = 4'h8 >> { i_38_, i_40_ }; + assign o_2_ = 32'd2004350839 >> { n277, n236, n100, n266, n258 }; + assign n96 = 4'h1 >> { i_16_, i_17_ }; + assign n258 = 64'h0000000200020002 >> { i_34_, n260, n262, n265, n259, n229 }; + assign n259 = 32'd1145328708 >> { i_32_, n179, n246, n260, n261 }; + assign n260 = 4'h8 >> { n171, n194 }; + assign n261 = 32'd4294967106 >> { i_31_, i_5_, i_29_, i_30_, i_28_ }; + assign n262 = 16'h0080 >> { n264, n242, n162, n263 }; + assign n263 = 4'h8 >> { n187, n160 }; + assign n264 = 64'hdddfdddfdddfffff >> { i_9_, i_18_, i_11_, i_12_, i_5_, i_15_ }; + assign n265 = 32'd2155905024 >> { i_25_, i_26_, n208, n171, n207 }; + assign n266 = 32'd8 >> { n274, n555, n392, n271, n267 }; + assign n267 = 32'd85267733 >> { n85, n84, n219, n268, o_15_ }; + assign n97 = 16'h0002 >> { n98, n100, i_36_, n99 }; + assign n268 = 8'h80 >> { n92, n93, n117 }; + assign n269 = 16'ha880 >> { i_9_, i_18_, i_19_, n124 }; + assign n270 = 32'd2 >> { i_32_, i_34_, i_38_, i_39_, i_33_ }; + assign n271 = 16'h1555 >> { n273, n171, n179, n272 }; + assign n272 = 16'h0888 >> { i_10_, i_27_, n130, n156 }; + assign n273 = 8'h02 >> { i_37_, i_34_, i_36_ }; + assign n274 = 64'h22222222a2222222 >> { i_39_, i_40_, n226, n275, n276, n130 }; + assign n275 = 8'h02 >> { i_37_, i_36_, i_35_ }; + assign n276 = 64'hfbdb7fdfdbfffff7 >> { i_40_, i_36_, i_39_, i_38_, i_37_, i_35_ }; + assign n277 = 16'hbdbf >> { i_40_, i_38_, i_39_, i_37_ }; + assign n80 = 64'h070f070f0707070f >> { i_17_, n91, n86, n81, i_15_, i_11_ }; + assign n98 = 8'he7 >> { i_37_, i_38_, i_39_ }; + assign n278 = 16'haa2a >> { i_24_, n230, n286, n279 }; + assign n279 = 64'h2200230122022303 >> { n225, n155, n100, n280, o_15_, n236 }; + assign n280 = 16'ha888 >> { n142, n281, n282, n283 }; + assign n281 = 8'h08 >> { i_35_, i_33_, i_34_ }; + assign n282 = 64'h0000000080000000 >> { i_34_, i_37_, i_36_, i_33_, i_35_, i_38_ }; + assign n283 = 64'h0000000000000080 >> { i_32_, i_1_, i_3_, i_0_, i_4_, i_2_ }; + assign n284 = 16'h0002 >> { i_35_, i_32_, i_34_, i_33_ }; + assign n285 = 8'h08 >> { i_37_, i_36_, i_38_ }; + assign n286 = 4'h2 >> { i_37_, n93 }; + assign n287 = 64'h4444444454444444 >> { n196, i_40_, n292, i_36_, n288, n291 }; + assign n99 = 32'd8 >> { i_35_, i_7_, i_32_, i_33_, i_34_ }; + assign n288 = 32'd128 >> { n231, i_36_, n290, n289, i_12_ }; + assign n289 = 4'h1 >> { i_5_, i_9_ }; + assign n290 = 8'h02 >> { i_32_, i_16_, i_15_ }; + assign n291 = 4'h1 >> { i_37_, i_39_ }; + assign n292 = 64'h4444444444444440 >> { i_4_, i_1_, i_3_, i_2_, i_0_, i_32_ }; + assign n293 = 4'h2 >> { i_36_, n252 }; + assign n294 = 64'h22222222222222a2 >> { i_5_, n297, i_36_, n179, n295, n284 }; + assign n295 = 32'd17895697 >> { i_39_, n168, n289, n296, n222 }; + assign n296 = 32'd128 >> { i_36_, i_17_, n93, n115, n289 }; + assign n297 = 8'h01 >> { i_29_, i_30_, i_28_ }; + assign n100 = 16'h0001 >> { i_1_, i_4_, i_3_, i_2_ }; + assign n298 = 64'h1101110111111101 >> { n308, n299, i_35_, n171, n304, n301 }; + assign n299 = 64'hfefeaeaefeffeeff >> { n300, i_12_, n161, i_15_, i_13_, i_5_ }; + assign n300 = 4'h2 >> { i_40_, n116 }; + assign n301 = 32'd2290657416 >> { n140, n302, n236, n303, n124 }; + assign n302 = 4'h8 >> { n252, i_37_ }; + assign n303 = 16'h0888 >> { i_23_, i_21_, n103, n131 }; + assign n304 = 64'h2020202022202020 >> { i_18_, n307, n305, n306, n107, n289 }; + assign n305 = 4'h8 >> { n171, n249 }; + assign n306 = 16'h8000 >> { n136, n291, n250, n290 }; + assign n307 = 4'h2 >> { i_21_, i_15_ }; + assign n101 = 8'h08 >> { n102, n92, n103 }; + assign n308 = 32'd32768 >> { n221, n242, n188, n244, i_15_ }; + assign n309 = 64'h1111111111110111 >> { n313, n220, n124, n171, n314, n607 }; + assign n310 = 64'h7777777777770777 >> { i_5_, i_14_, i_31_, n174, n223, n151 }; + assign n311 = 32'd17900339 >> { n210, n150, n252, n312, i_35_ }; + assign n312 = 64'h0000000000808000 >> { i_37_, i_39_, i_40_, i_38_, i_35_, i_36_ }; + assign n313 = 8'h51 >> { i_35_, n116, n84 }; + assign n314 = 32'd2863179944 >> { n240, n197, n136, n93, n232 }; + assign n315 = 4'h2 >> { i_38_, i_37_ }; + assign n316 = 8'h01 >> { i_38_, i_39_, i_40_ }; + assign n317 = 4'h1 >> { i_38_, i_39_ }; + assign n102 = 32'd4277071598 >> { i_15_, i_11_, i_12_, i_5_, i_7_ }; + assign n318 = 16'h0080 >> { i_17_, n289, n84, n115 }; + assign n319 = 16'h0008 >> { i_32_, i_5_, n115, n96 }; + assign n320 = 64'h0000000000008000 >> { n321, i_32_, n143, i_37_, n151, i_0_ }; + assign n321 = 16'h0008 >> { i_3_, i_2_, i_1_, i_4_ }; + assign n322 = 16'h0080 >> { i_39_, n236, i_37_, n252 }; + assign n323 = 16'h7d7f >> { n84, n93, n117, n250 }; + assign n324 = 16'h0080 >> { i_40_, n281, n283, n188 }; + assign n325 = 64'hddddffdfffdfffdf >> { n223, i_0_, i_5_, n315, i_34_, n171 }; + assign n326 = 32'd1431639381 >> { i_34_, n174, n93, n117, n84 }; + assign n327 = 64'h0000000000000080 >> { n96, n244, i_7_, n171, n124, i_9_ }; + assign n103 = 16'h0008 >> { i_37_, i_40_, i_39_, i_38_ }; + assign n328 = 64'hff7f7fff7f7f7fff >> { i_14_, i_11_, i_12_, i_15_, i_16_, n87 }; + assign n329 = 64'h0000000000000002 >> { i_7_, i_32_, i_15_, i_5_, i_13_, i_33_ }; + assign n330 = 64'hffffff18ffffff10 >> { i_40_, i_36_, i_35_, i_37_, i_39_, i_38_ }; + assign n331 = 16'h0080 >> { i_38_, n169, n197, n180 }; + assign n332 = 4'h2 >> { i_24_, i_15_ }; + assign n333 = 64'h0000000000008000 >> { i_7_, i_11_, i_36_, n284, n173, i_12_ }; + assign n334 = 16'ha888 >> { n187, n166, n335, n302 }; + assign n335 = 16'h0080 >> { n336, n263, n162, i_23_ }; + assign n336 = 32'd3722436607 >> { i_9_, i_18_, i_19_, i_7_, n124 }; + assign n337 = 64'h0100010001000101 >> { n343, n344, i_39_, n341, n614, n338 }; + assign n104 = 32'd128 >> { n105, i_9_, n87, n106, n88 }; + assign n338 = 32'd572695074 >> { n339, n136, i_39_, n340, n125 }; + assign n339 = 16'h1bbb >> { n197, n123, n207, i_37_ }; + assign n340 = 64'hcddd6fffefff6fff >> { n273, i_38_, i_37_, n187, i_39_, i_40_ }; + assign n341 = 64'h0000000000008000 >> { n264, i_7_, n144, n162, n255, n143 }; + assign n342 = 16'h0001 >> { i_7_, i_11_, i_12_, i_5_ }; + assign n343 = 16'h8808 >> { i_25_, i_26_, n196, n200 }; + assign n344 = 32'd526344 >> { i_10_, i_27_, i_7_, n284, n285 }; + assign n345 = 16'hddd5 >> { n83, i_9_, n115, n87 }; + assign n346 = 64'h0777777777777777 >> { n172, n166, n212, i_37_, n199, n179 }; + assign n347 = 16'h0ddd >> { n189, n251, n348, n260 }; + assign n105 = 32'd4227574523 >> { i_38_, i_40_, i_37_, i_39_, i_36_ }; + assign n348 = 16'h42ff >> { n87, i_29_, i_30_, i_28_ }; + assign n349 = 16'h0080 >> { i_36_, n168, n148, n131 }; + assign n350 = 64'h0000000000000002 >> { i_7_, i_32_, i_15_, i_5_, i_31_, i_33_ }; + assign n351 = 32'd32768 >> { i_37_, n212, n157, i_36_, i_11_ }; + assign n352 = 32'd134875138 >> { i_30_, i_29_, n353, i_28_, n87 }; + assign n353 = 8'h51 >> { i_36_, n179, n210 }; + assign n354 = 32'd1431639381 >> { n220, i_9_, n87, n300, n355 }; + assign n355 = 16'ha888 >> { n188, n173, n161, n342 }; + assign n356 = 64'h1111111101111111 >> { n336, n302, n360, n187, n359, n357 }; + assign n357 = 32'd2720145954 >> { i_37_, n172, n173, n358, n329 }; + assign n106 = 16'h0008 >> { i_35_, i_34_, i_12_, i_15_ }; + assign n358 = 64'hfffffffdd7dff7fd >> { i_36_, i_40_, i_39_, i_37_, i_38_, n123 }; + assign n359 = 64'h0202220200020220 >> { i_40_, i_37_, i_39_, i_38_, i_36_, n205 }; + assign n360 = 16'h8000 >> { n171, i_24_, i_22_, i_23_ }; + assign n361 = 64'h0000000228200802 >> { i_36_, i_40_, i_39_, i_37_, i_38_, n362 }; + assign n362 = 8'h08 >> { i_13_, n131, n342 }; + assign n363 = 64'h0000000800080008 >> { n369, n255, n364, n368, n367, n366 }; + assign n364 = 16'h8000 >> { n138, n365, n174, n251 }; + assign n365 = 4'h8 >> { n171, i_34_ }; + assign n366 = 64'hbf2abf3fbf2abf7f >> { i_37_, n344, i_39_, i_38_, n199, i_40_ }; + assign n367 = 32'd2004289399 >> { i_39_, n117, n183, n210, n189 }; + assign n107 = 4'h1 >> { i_11_, i_12_ }; + assign n368 = 64'h0000000000008000 >> { i_32_, i_13_, n251, n342, i_34_, n250 }; + assign n369 = 4'h8 >> { n99, n100 }; + assign n370 = 64'h4c4c4c4c4c4c444c >> { n264, i_7_, i_22_, n138, n372, n371 }; + assign n371 = 32'd142608384 >> { n138, i_38_, i_37_, n263, i_40_ }; + assign n372 = 32'd1162149957 >> { n375, n125, n138, n373, n374 }; + assign n373 = 64'h77777fff7fff7fff >> { n249, i_23_, n123, n208, i_24_, n171 }; + assign n374 = 16'h8000 >> { n123, n124, n125, n233 }; + assign n375 = 64'hfdfddd7fdfffdd7f >> { i_40_, i_38_, i_36_, i_39_, i_37_, n123 }; + assign n376 = 32'd2147516544 >> { n378, n377, n107, n108, n109 }; + assign n377 = 8'h80 >> { n174, n136, n291 }; + assign n81 = 16'h0080 >> { n83, n82, n84, n85 }; + assign n108 = 16'h0002 >> { i_32_, i_34_, i_31_, i_33_ }; + assign n378 = 32'd271798519 >> { n225, n379, i_38_, n174, i_40_ }; + assign n379 = 16'h0002 >> { i_35_, i_37_, i_36_, i_39_ }; + assign n380 = 64'h0000000000000008 >> { i_5_, i_29_, i_30_, i_28_, n111, n381 }; + assign n381 = 32'd8 >> { i_36_, i_38_, i_40_, i_39_, i_37_ }; + assign n382 = 64'h0000000000000008 >> { i_5_, i_29_, i_30_, i_28_, n383, n250 }; + assign n383 = 4'h1 >> { i_32_, i_31_ }; + assign n384 = 16'h8880 >> { n386, n385, n124, i_22_ }; + assign n385 = 64'h0000000000008000 >> { i_36_, i_32_, n252, n281, i_39_, i_21_ }; + assign n386 = 16'h8000 >> { n249, n160, i_21_, i_23_ }; + assign n387 = 16'h0080 >> { i_34_, n140, n160, n124 }; + assign n109 = 8'h02 >> { i_7_, i_5_, i_13_ }; + assign n388 = 64'h5555555515555555 >> { n264, i_24_, i_22_, n255, i_35_, n312 }; + assign n389 = 8'h08 >> { i_37_, n284, n222 }; + assign o_8_ = 32'd4277071598 >> { n179, i_37_, n236, o_15_, n389 }; + assign o_9_ = 8'hfd >> { n392, n380, n267 }; + assign n392 = 32'd2147483648 >> { n203, n269, n162, i_24_, i_23_ }; + assign o_11_ = 32'd4294440951 >> { n180, n179, n398, n394, n397 }; + assign n394 = 32'd3840341495 >> { n341, n255, n395, n84, n127 }; + assign n395 = 32'd3755868127 >> { n159, n396, i_17_, n220, n383 }; + assign n396 = 32'd4286545919 >> { i_11_, i_12_, n87, i_15_, i_16_ }; + assign n397 = 16'h5515 >> { i_37_, n180, n231, n211 }; + assign n110 = 64'hfeffeeeefefffeef >> { i_40_, i_38_, i_39_, i_37_, i_36_, i_35_ }; + assign n398 = 32'd2147483648 >> { n87, n174, n85, n179, n297 }; + assign o_13_ = 32'd1431688533 >> { i_37_, i_36_, i_35_, n270, n400 }; + assign n400 = 64'h00000000fff77fff >> { o_15_, i_38_, i_39_, i_40_, n188, n131 }; + assign o_14_ = 32'd3579139413 >> { n208, i_13_, n171, n207, n400 }; + assign n402 = 32'd2147483648 >> { n131, n150, n148, n321, n316 }; + assign n403 = 16'ha280 >> { n189, n404, i_40_, n168 }; + assign n404 = 4'h8 >> { n125, n187 }; + assign n405 = 16'h0080 >> { n147, n157, i_0_, n100 }; + assign o_18_ = 64'h7fffffff7fff7fff >> { n415, n419, n407, n422, n372, n630 }; + assign n407 = 16'h0001 >> { n408, n410, n331, n411 }; + assign n111 = 32'd2 >> { i_35_, i_32_, i_34_, i_31_, i_33_ }; + assign n408 = 32'd2827520136 >> { n197, n123, n168, n409, n125 }; + assign n409 = 8'h80 >> { n239, n196, n240 }; + assign n410 = 64'h020a0a0200080800 >> { i_38_, i_37_, i_39_, i_36_, i_40_, n369 }; + assign n411 = 64'h22a20a8222a20880 >> { n197, i_38_, i_40_, i_37_, i_39_, n180 }; + assign n412 = 64'haa66ae66ab66af67 >> { n414, n405, i_39_, n413, n117, n362 }; + assign n413 = 64'h0020202008282828 >> { i_11_, i_10_, i_27_, i_38_, i_40_, n189 }; + assign n414 = 32'd32768 >> { n416, n415, n87, i_38_, i_9_ }; + assign n415 = 32'd2 >> { i_35_, i_36_, i_34_, i_31_, i_33_ }; + assign n416 = 64'h7777777707777777 >> { i_40_, i_11_, i_12_, i_15_, i_37_, i_39_ }; + assign n417 = 8'h08 >> { i_7_, n246, i_32_ }; + assign n112 = 64'h0ddd0ddd05550ddd >> { i_17_, n115, n113, n116, n117, n91 }; + assign n418 = 32'd2290649256 >> { n136, n196, n263, n170, n138 }; + assign n419 = 64'hbdffa8ff99db88df >> { n348, i_37_, n420, i_40_, i_39_, i_38_ }; + assign n420 = 4'h8 >> { n421, n87 }; + assign n421 = 16'h2220 >> { i_9_, i_16_, n107, i_15_ }; + assign n422 = 16'h5551 >> { n425, n426, n192, n423 }; + assign n423 = 64'ha888888888888888 >> { n148, n321, n315, n131, n424, n240 }; + assign n424 = 64'h0000000000008008 >> { i_36_, i_31_, i_37_, i_38_, n87, n127 }; + assign n425 = 32'd4294967167 >> { i_7_, n221, i_11_, n115, i_14_ }; + assign n426 = 64'hffffffe7ffffffef >> { i_40_, i_36_, i_35_, i_37_, i_39_, i_38_ }; + assign o_19_ = 64'hb333b333bbbbb333 >> { n431, i_6_, n433, n540, n428, n178 }; + assign n113 = 16'h0080 >> { i_24_, n114, i_12_, n87 }; + assign n428 = 64'h88888ccc8ccc8ccc >> { n189, n225, n430, n369, n429, i_40_ }; + assign n429 = 64'hf7e7f7ffffe7ffff >> { n200, n404, i_37_, i_38_, i_39_, i_40_ }; + assign n430 = 4'h8 >> { n142, i_37_ }; + assign n431 = 32'd1431639381 >> { i_36_, n281, n168, n201, n432 }; + assign n432 = 32'd2860548224 >> { n201, n285, n252, n150, n143 }; + assign n433 = 16'h0008 >> { i_7_, i_3_, i_4_, n434 }; + assign n434 = 8'h02 >> { i_1_, i_2_, i_0_ }; + assign n435 = 64'h1111111101111111 >> { i_36_, n208, n157, i_5_, n634, n436 }; + assign n436 = 32'd2282227720 >> { n176, n143, n248, n178, i_5_ }; + assign n437 = 32'd8 >> { i_35_, i_32_, i_34_, i_33_, i_36_ }; + assign n114 = 32'd128 >> { i_32_, i_34_, i_33_, i_35_, i_15_ }; + assign n438 = 8'h02 >> { i_7_, i_0_, i_5_ }; + assign n439 = 64'h5454545454545554 >> { n440, i_12_, i_9_, n245, n442, i_7_ }; + assign n440 = 16'h1555 >> { i_39_, n136, n243, n441 }; + assign n441 = 32'd8 >> { n96, n98, i_34_, n171, n174 }; + assign n442 = 4'h1 >> { n326, n443 }; + assign n443 = 64'hff57ff7f7f577f7f >> { n220, i_9_, i_14_, i_16_, i_17_, n171 }; + assign n444 = 64'h2222222222220222 >> { n448, n447, n445, n248, i_15_, n178 }; + assign n445 = 32'd4294834165 >> { n98, n227, i_36_, i_40_, n192 }; + assign n446 = 32'd1 >> { i_37_, i_36_, i_38_, i_39_, i_40_ }; + assign n447 = 32'd2860548224 >> { n116, i_9_, n176, i_13_, n192 }; + assign n115 = 4'h8 >> { i_12_, i_15_ }; + assign n448 = 64'h0002000000220028 >> { i_37_, i_40_, i_36_, i_39_, i_38_, n127 }; + assign n449 = 64'h0010001011110010 >> { n440, i_9_, i_12_, n247, i_7_, i_11_ }; + assign n450 = 16'h8880 >> { i_31_, i_5_, n174, n157 }; + assign n451 = 32'd357913941 >> { n189, i_11_, n117, n212, n452 }; + assign n452 = 32'd128 >> { i_7_, i_32_, n246, n221, i_5_ }; + assign n453 = 64'h0008800000080000 >> { i_37_, i_39_, i_36_, i_40_, n438, i_38_ }; + assign n454 = 16'h8880 >> { i_36_, n169, n123, n168 }; + assign n455 = 64'hffffffffffffbffd >> { i_35_, i_37_, n201, i_36_, i_38_, i_34_ }; + assign n456 = 64'hfdfdfdfd55fdfdfd >> { i_0_, n150, n316, i_6_, n457, i_35_ }; + assign n457 = 32'd4294410239 >> { i_37_, i_38_, i_39_, i_36_, i_40_ }; + assign n116 = 16'h0008 >> { i_37_, i_36_, i_38_, i_39_ }; + assign n458 = 64'h3737373715373737 >> { i_6_, i_37_, n242, n409, i_32_, n172 }; + assign n459 = 4'h1 >> { n305, n170 }; + assign n460 = 32'd4290756541 >> { i_37_, i_39_, i_38_, i_40_, i_36_ }; + assign n461 = 32'd128 >> { i_35_, i_0_, n188, i_5_, n171 }; + assign n462 = 64'h7fffffff7fff7fff >> { i_36_, n151, n171, i_37_, n123, i_0_ }; + assign n463 = 32'd128 >> { i_32_, i_0_, n192, i_5_, n168 }; + assign n464 = 64'h6406ec8e7416fc9e >> { i_36_, n197, i_40_, i_39_, i_37_, i_38_ }; + assign n465 = 64'hb7f5bdb5b5b3b1bb >> { i_38_, i_39_, i_40_, i_35_, i_37_, i_36_ }; + assign n466 = 16'h22a2 >> { n421, n137, n467, i_38_ }; + assign n467 = 32'd3707698942 >> { n182, i_37_, n468, i_34_, i_35_ }; + assign n117 = 4'h2 >> { i_37_, i_40_ }; + assign n468 = 8'h15 >> { i_0_, i_36_, i_5_ }; + assign o_32_ = 8'h80 >> { n404, n168, n240 }; + assign o_24_ = 64'hffffffffffff7fff >> { n488, n490, n112, n484, n471, n477 }; + assign n471 = 32'd128 >> { o_32_, n473, n145, n476, n472 }; + assign n472 = 16'h1101 >> { i_7_, n238, n97, n594 }; + assign n473 = 8'h08 >> { i_35_, n142, n474 }; + assign n474 = 8'h80 >> { n171, n475, i_34_ }; + assign n475 = 64'h0000000000000080 >> { i_7_, i_1_, i_3_, i_0_, i_4_, i_2_ }; + assign n476 = 32'd2139051391 >> { i_32_, n282, n151, n232, n475 }; + assign n477 = 32'd32768 >> { n478, n80, n480, n481, n483 }; + assign n82 = 64'h0002000200020000 >> { i_12_, i_11_, i_7_, i_5_, i_9_, i_15_ }; + assign n118 = 32'd4160223231 >> { i_12_, i_11_, i_22_, n114, n87 }; + assign n478 = 32'd2290092032 >> { n176, n129, i_37_, n479, n123 }; + assign n479 = 64'h0000000800080808 >> { i_9_, i_18_, i_19_, i_21_, n139, n171 }; + assign n480 = 64'h5555555515555555 >> { n326, n96, i_15_, n95, n85, n135 }; + assign n481 = 32'd1431655701 >> { i_21_, i_23_, n203, n139, n482 }; + assign n482 = 32'd32768 >> { i_21_, n114, n446, i_11_, n87 }; + assign n483 = 32'd2004844415 >> { n179, n174, n194, n108, n195 }; + assign n484 = 32'd1 >> { n104, n133, n209, n485, n487 }; + assign n485 = 32'd2147483648 >> { n95, n250, n251, n486, i_34_ }; + assign n486 = 16'h0222 >> { i_21_, i_22_, i_32_, i_15_ }; + assign n487 = 32'd32768 >> { i_21_, n114, n446, i_12_, n87 }; + assign n119 = 32'd143130752 >> { i_23_, n120, n158, n128, n145 }; + assign n488 = 64'h22222222a2222222 >> { i_23_, n125, n123, n124, n489, n300 }; + assign n489 = 32'd4160223231 >> { i_12_, i_11_, i_21_, n114, n87 }; + assign n490 = 16'h5554 >> { n161, n116, n446, n118 }; + assign o_28_ = 32'd4223384507 >> { n317, n137, n474, n476, n155 }; + assign n492 = 32'd8 >> { n488, n490, n153, n112, n484 }; + assign o_26_ = 16'hddfd >> { i_39_, n149, n146, n472 }; + assign o_27_ = 32'd4294934527 >> { n478, n80, n492, n480, n481 }; + assign o_29_ = 8'hfd >> { n496, n209, n483 }; + assign n496 = 64'h0808080008000800 >> { n236, n251, n497, i_21_, i_22_, n139 }; + assign n497 = 32'd2290122880 >> { n196, n240, n103, n187, n160 }; + assign n120 = 32'd2290657416 >> { i_12_, n126, n121, n122, n116 }; + assign o_33_ = 64'hffffffffffffff7f >> { n499, n511, n514, n624, n503, n517 }; + assign n499 = 64'h222222222222222a >> { i_5_, i_31_, n378, i_15_, n500, n130 }; + assign n500 = 64'h4444444404444444 >> { i_37_, n226, i_35_, n316, n502, n501 }; + assign n501 = 32'd32768 >> { n264, n201, n275, i_24_, i_22_ }; + assign n502 = 64'hffdf7fffffdffff7 >> { i_35_, i_38_, i_40_, i_39_, i_37_, i_36_ }; + assign n503 = 64'h0000000000000080 >> { o_13_, n504, n505, n271, n507, n510 }; + assign n504 = 64'h0800080008080800 >> { i_36_, n201, n316, i_37_, i_35_, n387 }; + assign n505 = 16'h8880 >> { n225, n255, n246, n506 }; + assign n506 = 32'd128 >> { n244, i_5_, i_16_, n383, i_17_ }; + assign n507 = 64'h1111111111111101 >> { i_5_, i_31_, i_15_, n253, n509, n508 }; + assign n121 = 4'h8 >> { n87, i_11_ }; + assign n508 = 16'h0080 >> { n107, n117, n212, n437 }; + assign n509 = 64'h0000000000000080 >> { n277, i_5_, i_13_, n107, n171, n187 }; + assign n510 = 64'hdddddddd0ddddddd >> { i_40_, n100, n225, n236, i_33_, i_32_ }; + assign n511 = 64'h0202020222020202 >> { i_15_, n111, n103, n512, i_5_, i_9_ }; + assign n512 = 64'h677f6f7f67ffefff >> { n92, i_40_, n513, i_37_, i_39_, i_38_ }; + assign n513 = 16'h0008 >> { n96, i_14_, n383, n246 }; + assign n514 = 8'h02 >> { n515, i_5_, n107 }; + assign n515 = 64'haf27af27af27ab23 >> { n214, i_13_, i_31_, n516, n171, n377 }; + assign n516 = 32'd145358888 >> { i_40_, i_38_, i_37_, i_39_, n92 }; + assign n517 = 32'd33694210 >> { n203, n459, n226, n523, n518 }; + assign n122 = 16'h8000 >> { n123, n124, n125, i_21_ }; + assign n518 = 16'h5515 >> { n519, n171, i_6_, n520 }; + assign n519 = 32'd389488575 >> { n172, n252, n207, n256, i_37_ }; + assign n520 = 64'haa20202020202020 >> { n316, n522, i_35_, n434, n181, n521 }; + assign n521 = 8'h02 >> { i_32_, i_3_, i_4_ }; + assign n522 = 64'h0000000000008000 >> { i_34_, i_2_, i_36_, i_1_, i_0_, i_33_ }; + assign n523 = 64'h0202020002000200 >> { n103, n111, n524, n220, i_5_, i_9_ }; + assign n524 = 16'h0008 >> { n96, n525, n383, n127 }; + assign n525 = 16'hf6f7 >> { i_37_, i_36_, i_38_, i_39_ }; + assign n526 = 16'h0777 >> { n174, n251, n176, n123 }; + assign n527 = 64'hffffeffeeeefeeee >> { i_35_, i_37_, i_38_, i_39_, i_36_, i_34_ }; + assign n123 = 4'h2 >> { i_34_, i_35_ }; + assign n528 = 64'h2222222202222222 >> { i_39_, n236, i_37_, n136, n241, n529 }; + assign n529 = 32'd715827882 >> { n437, i_11_, n117, n212, n400 }; + assign n530 = 64'h7d7f7ffffd7fffff >> { n172, n207, i_37_, i_38_, i_39_, i_40_ }; + assign n531 = 64'haa00aa08aa08aa08 >> { i_15_, n244, n532, i_36_, i_5_, n284 }; + assign n532 = 64'h8080800000800000 >> { n179, n93, i_37_, n100, i_36_, i_0_ }; + assign n533 = 32'd2290657416 >> { n244, n84, n85, n268, n83 }; + assign n534 = 8'h01 >> { i_32_, i_15_, i_31_ }; + assign n535 = 64'h8c8c8c8c888c8c8c >> { n244, n85, n84, n268, n536, n96 }; + assign n536 = 32'd4160190455 >> { n220, n103, i_15_, n379, n108 }; + assign n537 = 8'h02 >> { n538, i_31_, n107 }; + assign n124 = 16'h2220 >> { i_12_, i_11_, i_5_, i_15_ }; + assign n538 = 64'hfffffbaafefffeeb >> { i_40_, i_35_, i_38_, i_37_, i_39_, i_36_ }; + assign n539 = 32'd2290657416 >> { i_40_, n522, n225, n540, n521 }; + assign n540 = 16'h2022 >> { n201, n282, n181, n434 }; + assign n541 = 64'h1011001110111011 >> { i_37_, n118, n142, n545, n542, n546 }; + assign n542 = 8'ha8 >> { n544, n543, n95 }; + assign n543 = 64'h5540404040404040 >> { n270, n307, n223, n114, n103, i_23_ }; + assign n544 = 32'd2147483648 >> { n85, n96, n379, n256, i_15_ }; + assign n545 = 16'h5515 >> { i_24_, n114, n121, n113 }; + assign n546 = 16'h4454 >> { i_36_, n316, n116, n489 }; + assign n547 = 32'd715827882 >> { n137, n212, n85, n342, n548 }; + assign n125 = 8'h02 >> { i_7_, i_32_, i_33_ }; + assign n548 = 16'h2aaa >> { n187, n208, n329, i_40_ }; + assign n549 = 32'd32768 >> { n100, n148, i_38_, n239, n130 }; + assign n550 = 64'h5fdf7dff5bdf79ff >> { n107, n199, n189, i_37_, i_39_, i_38_ }; + assign n551 = 64'h888888888888a888 >> { n297, i_34_, n210, n87, n552, n85 }; + assign n552 = 16'ha888 >> { n379, n256, n84, n553 }; + assign n553 = 32'd8 >> { i_7_, i_5_, i_14_, n115, i_11_ }; + assign n554 = 64'h0b1b0b1babbb0b1b >> { n167, n339, n555, n125, n556, n169 }; + assign n555 = 32'd32768 >> { i_13_, n142, n131, n117, n342 }; + assign n556 = 64'h0000000000000080 >> { i_36_, i_29_, i_30_, n87, n111, n179 }; + assign n557 = 64'hf9fdfbfffbfffbff >> { n189, i_40_, n200, i_38_, i_39_, i_37_ }; + assign n126 = 32'd128 >> { i_32_, i_31_, n127, i_15_, n96 }; + assign n558 = 64'h333300a23b3b08aa >> { n153, n430, n559, n479, n123, n560 }; + assign n559 = 64'ha2a2a280a280a280 >> { n201, n350, n474, n135, i_38_, n137 }; + assign n560 = 16'h555d >> { n155, n343, n561, n125 }; + assign n561 = 64'hfefefefffefffeff >> { n150, i_39_, n223, i_38_, i_34_, i_40_ }; + assign o_10_ = 32'd791621391 >> { i_20_, i_25_, n397, n563, n138 }; + assign n563 = 32'd17895697 >> { i_23_, i_24_, n305, n564, n170 }; + assign n564 = 32'd2290649216 >> { n446, n161, n255, n123, n160 }; + assign o_12_ = 16'h0080 >> { n566, n171, n438, i_8_ }; + assign n566 = 32'd712998783 >> { n172, n151, n136, n207, i_37_ }; + assign n567 = 64'h1101110111001101 >> { i_36_, n179, n575, n381, n572, n568 }; + assign n127 = 8'h02 >> { i_35_, i_34_, i_33_ }; + assign n568 = 64'h2020202020202220 >> { n570, n83, n569, n571, i_9_, n108 }; + assign n569 = 4'h2 >> { n107, i_15_ }; + assign n570 = 64'h7755dfdd7775dfd7 >> { i_40_, i_39_, i_16_, i_37_, i_38_, n174 }; + assign n571 = 8'h08 >> { n117, n93, n174 }; + assign n572 = 64'ha8a8a8a8aaa8a8a8 >> { n140, n236, n251, n574, n573, n569 }; + assign n573 = 8'h08 >> { n426, n108, n96 }; + assign n574 = 16'h0008 >> { i_36_, i_23_, n103, n131 }; + assign n575 = 16'hdff7 >> { i_29_, i_30_, i_28_, n111 }; + assign n576 = 64'h1515151500151515 >> { n100, n236, n286, n320, i_36_, n577 }; + assign n577 = 32'd128 >> { i_38_, i_40_, n283, n188, n281 }; + assign n83 = 4'h8 >> { i_16_, i_17_ }; + assign n128 = 64'h0001010101010101 >> { n144, n141, n138, n129, n133, n135 }; + assign n578 = 32'd1431639381 >> { i_38_, n131, n150, n169, n579 }; + assign n579 = 64'h0000800080000000 >> { i_37_, i_39_, n292, n127, i_36_, n256 }; + assign n580 = 64'h2a2a0a2a0a2a0a2a >> { n220, i_9_, i_39_, i_38_, i_40_, n581 }; + assign n581 = 64'ha22aa22200080002 >> { n421, i_38_, i_39_, i_40_, i_37_, n582 }; + assign n582 = 4'h2 >> { i_7_, n415 }; + assign n583 = 16'h2008 >> { i_35_, i_39_, i_40_, i_38_ }; + assign n584 = 64'h0000800800000008 >> { n117, n221, i_38_, i_39_, n244, i_15_ }; + assign n585 = 64'h4444444444445444 >> { n336, i_23_, i_24_, n203, n586, i_21_ }; + assign n586 = 64'h0000000080000000 >> { i_34_, n188, n160, n316, i_35_, n139 }; + assign n587 = 64'hffffdff7ffffdffd >> { i_40_, i_36_, i_38_, i_39_, i_37_, i_35_ }; + assign n129 = 32'd134744064 >> { n116, n132, i_18_, n131, n82 }; + assign o_31_ = 32'd1431655893 >> { n336, i_23_, n162, n203, n589 }; + assign n589 = 64'h0010101000111111 >> { n113, n138, n574, n154, o_28_, n153 }; + assign n590 = 64'hddddffdfffdfffdf >> { n108, n107, i_15_, n111, n110, n109 }; + assign n591 = 64'h0001000100000001 >> { n118, n116, n101, n104, n94, n97 }; + assign n592 = 16'h8000 >> { n590, n80, n591, n112 }; + assign n593 = 64'h0808080808080800 >> { i_3_, i_4_, i_1_, i_34_, i_0_, i_33_ }; + assign n594 = 16'h0002 >> { i_7_, i_32_, n147, n593 }; + assign n595 = 64'he7bf6fdfbfbf7fff >> { i_38_, i_36_, i_40_, i_35_, i_39_, i_37_ }; + assign n596 = 16'h8088 >> { n222, i_37_, n595, n224 }; + assign n597 = 64'h0059405d00090216 >> { i_40_, i_35_, i_34_, i_37_, i_39_, i_38_ }; + assign n130 = 8'h02 >> { i_32_, i_34_, i_33_ }; + assign n598 = 64'hffffffffffffff7f >> { i_36_, i_5_, i_13_, n597, n107, n171 }; + assign n599 = 32'd572662314 >> { n203, n247, n253, n226, n598 }; + assign n600 = 64'hd5ddd5ddd5ddf5ff >> { n316, n315, n317, i_24_, n140, n230 }; + assign o_3_ = 64'hffffffffffff7fff >> { n604, n294, n670, n278, n298, n309 }; + assign n602 = 32'd4294967293 >> { i_36_, i_32_, i_5_, n225, i_31_ }; + assign n603 = 64'h222222222222f222 >> { i_36_, i_38_, i_39_, i_11_, n107, n293 }; + assign n604 = 64'haaa2a2a2a2a2a2a2 >> { n603, n289, n290, n287, n602, n127 }; + assign n605 = 64'hb3b1b391b3b13311 >> { n240, n242, i_39_, n197, i_35_, i_36_ }; + assign n606 = 32'd3632826504 >> { i_38_, n169, n289, i_37_, i_36_ }; + assign n607 = 64'hff007f007f007f00 >> { n606, n605, n130, n224, n310, n311 }; + assign n131 = 16'h0008 >> { i_32_, i_34_, i_33_, i_35_ }; + assign n608 = 64'h45cf45cf45cd45cf >> { i_37_, n231, n210, n349, i_40_, n180 }; + assign o_4_ = 64'hffffffff7fffffff >> { n334, n672, n185, n675, n608, n337 }; + assign n610 = 64'h222222222222f222 >> { i_17_, i_16_, n246, n178, n330, n157 }; + assign n611 = 64'h2323232322232323 >> { n328, n171, i_17_, n327, n333, n326 }; + assign n612 = 64'h787878787f787878 >> { i_39_, n180, n197, i_37_, n90, n329 }; + assign n613 = 64'h1191008000800080 >> { i_40_, n284, i_32_, n281, i_37_, i_13_ }; + assign n614 = 64'h888888888888a888 >> { i_36_, i_38_, i_39_, n613, n555, n342 }; + assign n615 = 64'hbfbfbfbf15bfbfbf >> { i_39_, i_37_, n180, n350, n90, i_38_ }; + assign n616 = 64'h00080a0a00ccffff >> { n111, i_40_, n351, n352, n615, n354 }; + assign o_6_ = 64'hffffffff7fffffff >> { n376, n356, n620, n363, n370, n616 }; + assign n132 = 64'h0000000000000080 >> { i_36_, i_38_, i_39_, i_37_, i_35_, i_40_ }; + assign n618 = 64'h888888888888f888 >> { i_37_, i_39_, n166, n123, n84, n350 }; + assign n619 = 64'h080808080808ff08 >> { i_30_, n353, i_29_, i_15_, i_9_, n300 }; + assign n620 = 64'h0015151515151515 >> { n87, n111, n619, i_40_, n618, n361 }; + assign n621 = 64'h7f7f7fff7fff7fff >> { i_39_, n256, n316, n188, i_35_, n387 }; + assign o_7_ = 64'hff7fff7fffffff7f >> { n388, n130, n389, n624, n621, n267 }; + assign n623 = 64'h9bbf9bbf9bbf9bff >> { n382, n236, n232, i_40_, i_38_, i_39_ }; + assign n624 = 64'h0202020202025702 >> { n380, n384, n623, n392, n387, n132 }; + assign n625 = 64'hd580808080808080 >> { n107, i_40_, n239, n180, n169, i_37_ }; + assign n626 = 64'h77ff67ef67ff67ef >> { i_7_, i_39_, n625, n189, i_38_, i_37_ }; + assign o_16_ = 32'd4261412349 >> { n403, i_39_, n402, n405, n626 }; + assign n133 = 32'd128 >> { n134, i_24_, n87, i_12_, n114 }; + assign n628 = 64'h2230b7bf7737b7bf >> { n404, i_37_, i_38_, i_40_, n189, i_39_ }; + assign n629 = 64'h1111111101111111 >> { i_39_, n329, n123, n117, n417, n349 }; + assign n630 = 32'd128 >> { n403, n418, n628, n412, n629 }; + assign n631 = 64'h0140555501005555 >> { i_40_, n450, i_37_, i_38_, i_39_, n636 }; + assign o_20_ = 64'hffffffffffffff7f >> { n439, n444, n449, n435, n631, n451 }; + assign n633 = 64'h10101010ba101010 >> { i_34_, n117, n93, n196, n201, i_36_ }; + assign n634 = 64'h2020202022202020 >> { i_35_, i_33_, n633, n282, i_32_, n438 }; + assign n635 = 64'h109111d6108111d6 >> { i_13_, i_35_, i_37_, i_40_, i_39_, i_38_ }; + assign n636 = 64'h888888888888a888 >> { i_36_, i_7_, n107, n635, n453, n130 }; + assign n637 = 64'hfaeafaeaeaeafaea >> { n174, i_32_, n456, n458, i_34_, i_7_ }; + assign n134 = 32'd4278124542 >> { i_40_, i_37_, i_38_, i_39_, i_36_ }; + assign n638 = 64'h8a8a8a8aaa8a8a8a >> { i_34_, n179, n150, n455, n454, n87 }; + assign o_21_ = 16'h7f77 >> { n638, i_0_, n637, i_33_ }; + assign n640 = 64'h6aaa7bb96aaa7bbb >> { n100, n182, i_39_, i_40_, i_38_, i_37_ }; + assign n641 = 64'h1055555514555555 >> { n197, n365, n174, i_37_, n640, n463 }; + assign n642 = 64'h757775777577f5ff >> { n317, n151, n282, i_32_, n232, n475 }; + assign n643 = 64'h0000000000008000 >> { n155, n478, n80, n480, n481, n483 }; + assign o_25_ = 32'd2147450751 >> { n238, i_7_, n643, n642, n492 }; + assign n645 = 64'hf777f7775555f777 >> { n530, i_6_, n527, n526, i_5_, n171 }; + assign o_34_ = 32'd2147483647 >> { n678, n645, n528, n648, n650 }; + assign n647 = 64'h11cd51dc11015110 >> { n291, i_37_, i_40_, i_39_, i_38_, i_35_ }; + assign n135 = 32'd32768 >> { i_34_, n88, n136, n137, n82 }; + assign n648 = 64'h5555555555551555 >> { i_36_, i_34_, i_33_, n647, n534, n533 }; + assign n649 = 64'hfdddf888f888f888 >> { i_5_, n221, n316, n150, n103, i_36_ }; + assign n650 = 64'h51f351f3515151f3 >> { i_35_, n649, n537, n535, i_9_, n130 }; + assign n651 = 64'h7f7f7f7f557f7f7f >> { n240, n196, n197, n117, i_39_, n180 }; + assign n652 = 32'd32768 >> { n184, n651, n483, n554, n658 }; + assign o_5_ = 64'hffffffffffff7fff >> { n656, n551, n652, n541, n558, n592 }; + assign n654 = 64'h88888888a8888888 >> { n142, n109, n250, n534, n180, n231 }; + assign n655 = 64'hdfddffffcfccefee >> { n149, n118, n654, i_37_, i_40_, n142 }; + assign n656 = 16'haa2a >> { n549, n547, n550, n655 }; + assign n657 = 64'h0000800080008000 >> { i_21_, i_22_, i_39_, i_15_, n95, n281 }; + assign n136 = 4'h2 >> { i_40_, i_38_ }; + assign n658 = 64'h88888ccc8ccc8ccc >> { n282, n475, n293, n657, n557, i_32_ }; + assign n659 = 16'haeee >> { n196, n240, n277, n140 }; + assign n660 = 64'hd5f5d5f5d5d5d5f5 >> { i_39_, n252, n208, n659, i_24_, n230 }; + assign o_17_ = 64'h7fff7fff7fffffff >> { n567, i_5_, n278, n660, n576, n578 }; + assign n662 = 64'h22222222f2222222 >> { i_0_, n130, n583, i_37_, n584, n246 }; + assign o_22_ = 64'hfdfdfffdfdfdfdfd >> { i_5_, i_7_, n662, n417, n580, n435 }; + assign n664 = 64'h7777777777777757 >> { i_22_, i_34_, n587, n139, n488, n160 }; + assign o_30_ = 16'hfffd >> { n155, n485, n585, n664 }; + assign n666 = 64'hf575f575d555f575 >> { n421, n252, n464, n465, i_35_, n130 }; + assign o_23_ = 64'hf777f777f777ff77 >> { n460, i_35_, n171, n466, n666, n681 }; + assign n137 = 8'h01 >> { i_35_, i_37_, i_36_ }; + assign n668 = 64'hf7f7f7f700f7f7f7 >> { i_22_, n124, n249, i_25_, n207, n208 }; + assign n669 = 64'h1000101011001111 >> { n169, n319, n323, n325, n324, n322 }; + assign n670 = 64'h0008000808080008 >> { n318, n668, n171, n320, n669, n600 }; + assign n671 = 64'haa20202020202020 >> { n179, n297, n87, i_31_, n345, n246 }; + assign n672 = 64'h8888008808080008 >> { i_7_, i_32_, n671, n238, n346, n347 }; + assign n673 = 64'h7777777777776777 >> { i_39_, n332, n87, n131, i_37_, i_36_ }; + assign n674 = 64'hf5fdf7f5fdfdf7f5 >> { n183, i_37_, n673, i_38_, n612, i_40_ }; + assign n675 = 64'h0800080808080808 >> { n610, i_31_, i_5_, n331, n674, n611 }; + assign n676 = 64'h8080d08000815101 >> { i_35_, i_40_, i_39_, i_38_, i_37_, i_36_ }; + assign n677 = 64'hfaaaf888f222f000 >> { n192, i_33_, n286, n127, i_38_, n676 }; + assign n84 = 64'h0000000000000002 >> { i_35_, i_36_, i_34_, i_38_, i_39_, i_37_ }; + assign n138 = 4'h8 >> { n139, n140 }; + assign n678 = 64'h1111111111110111 >> { i_0_, i_32_, n677, i_5_, n539, n531 }; + assign n679 = 64'hf202fffff200ffff >> { i_16_, i_39_, i_9_, i_38_, n107, i_15_ }; + assign n680 = 64'h2a2a2a2a2a2aaa2a >> { i_31_, i_5_, n679, n174, n130, n462 }; + assign n681 = 64'h0000000000000080 >> { n101, o_15_, n461, n459, n680, n641 }; + assign n139 = 32'd33686016 >> { i_12_, i_11_, i_7_, i_5_, i_15_ }; + assign n140 = 4'h8 >> { i_22_, i_21_ }; + assign n141 = 16'h8000 >> { n142, n143, i_37_, i_40_ }; + assign n142 = 8'h01 >> { i_36_, i_38_, i_39_ }; + assign n143 = 8'h08 >> { i_34_, i_33_, i_35_ }; + assign n144 = 4'h2 >> { i_32_, i_24_ }; + assign n145 = 16'h0001 >> { n146, n149, n153, n155 }; + assign n146 = 16'h0080 >> { n147, n130, n148, i_2_ }; + assign n147 = 64'hffffffffff7f7fff >> { i_35_, i_37_, i_39_, i_38_, i_36_, i_40_ }; + assign n85 = 8'h02 >> { i_32_, i_31_, i_33_ }; + assign n148 = 4'h2 >> { i_7_, i_0_ }; + assign n149 = 16'h8000 >> { n131, n150, n151, n152 }; + assign n150 = 4'h8 >> { i_37_, i_36_ }; + assign n151 = 4'h1 >> { i_38_, i_40_ }; + assign n152 = 64'h4444444444440444 >> { i_3_, i_2_, i_4_, i_1_, i_0_, i_7_ }; + assign n153 = 32'd128 >> { n154, i_24_, n87, i_11_, n114 }; + assign n154 = 32'd4277600246 >> { i_40_, i_37_, i_36_, i_39_, i_38_ }; + assign n155 = 32'd32768 >> { i_40_, n157, n156, i_27_, i_10_ }; + assign n156 = 32'd8 >> { i_35_, i_37_, i_39_, i_38_, i_36_ }; + assign n157 = 16'h0002 >> { i_7_, i_32_, i_34_, i_33_ }; + assign n86 = 32'd134744064 >> { n90, n89, i_9_, n88, n87 }; + assign n158 = 16'hdddf >> { n159, n82, i_32_, n141 }; + assign n159 = 8'h08 >> { i_7_, n124, i_9_ }; + assign n160 = 8'h08 >> { i_32_, i_33_, i_24_ }; + assign n161 = 32'd8 >> { i_36_, i_38_, i_39_, i_37_, i_40_ }; + assign n162 = 4'h2 >> { i_21_, i_22_ }; + assign n163 = 32'd526344 >> { n183, n176, n184, n164, n177 }; + assign n164 = 64'h00aa01ab04ae05af >> { n268, n165, n109, n167, n175, n170 }; + assign n165 = 16'h8000 >> { n142, n123, n166, i_40_ }; + assign n166 = 64'h0000000000000008 >> { i_7_, i_32_, i_15_, i_5_, i_33_, i_13_ }; + assign n167 = 32'd32768 >> { i_36_, n168, n148, n169, n131 }; + assign n87 = 4'h1 >> { i_7_, i_5_ }; + assign n168 = 4'h8 >> { i_37_, i_38_ }; + assign n169 = 4'h2 >> { i_40_, i_39_ }; + assign n170 = 8'h80 >> { n171, n172, n173 }; + assign n171 = 4'h2 >> { i_32_, i_33_ }; + assign n172 = 8'h02 >> { i_35_, i_36_, i_34_ }; + assign n173 = 8'h08 >> { i_38_, i_39_, i_40_ }; + assign n174 = 4'h1 >> { i_35_, i_36_ }; + assign n175 = 32'd2147483648 >> { n87, n85, n96, i_12_, i_15_ }; + assign n176 = 4'h8 >> { n142, i_40_ }; + assign n177 = 32'd2004289399 >> { n181, n178, n182, n180, n179 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act b/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act new file mode 100644 index 000000000..ef37eb93f --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act @@ -0,0 +1,1340 @@ +i_0_ 0.511400 0.494800 +i_1_ 0.494200 0.508800 +i_2_ 0.505800 0.498800 +i_3_ 0.498000 0.499800 +i_4_ 0.499400 0.497800 +i_5_ 0.510600 0.486400 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0.994800 0.010295 +n1371 1.000000 0.000000 +n1372 0.998200 0.000001 +n1373 0.994600 0.000023 +n1374 0.999600 0.000000 +n1375 0.999000 0.000001 +n1376 0.992400 0.014977 +n1377 1.000000 0.000000 +n1378 1.000000 0.000000 +n1379 0.999600 0.000000 +n1380 0.999200 0.000000 +n1381 0.999800 0.006938 +n1382 0.998400 0.003191 +n1383 0.999800 0.008781 +n1384 0.999800 0.000000 +n1385 0.999200 0.000000 +n1386 0.999800 0.006288 +n1387 0.998000 0.003985 +n1388 0.997600 0.004797 diff --git a/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif b/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif new file mode 100644 index 000000000..e8d1be256 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif @@ -0,0 +1,4195 @@ +# Benchmark "spla" written by ABC on Tue Mar 12 09:33:19 2019 +.model spla +.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ + i_13_ i_14_ i_15_ +.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ \ + o_12_ o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ \ + o_24_ o_25_ o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ o_35_ \ + o_36_ o_37_ o_38_ o_39_ o_40_ o_41_ o_42_ o_43_ o_44_ o_45_ +.names n72 o_2_ i_7_ o_0_ +1-- 1 +-10 1 +.names n70 n67 i_8_ i_6_ o_2_ +1100 1 +.names n69 n68 n67 +11 1 +.names i_14_ i_13_ i_12_ n68 +000 1 +.names i_15_ i_10_ i_11_ i_9_ n69 +0000 1 +.names i_1_ n71 i_0_ i_2_ i_4_ n70 +11100 1 +.names i_5_ i_3_ n71 +10 1 +.names i_0_ i_1_ n72 +10 1 +.names i_0_ i_2_ o_2_ i_7_ i_1_ o_1_ +01--- 1 +10--0 1 +--11- 1 +.names o_11_ o_6_ o_3_ +00 0 +.names n98 n89 n76 n67 n97 o_6_ +11-1- 1 +11--0 1 +--0-- 1 +.names n77 n89 n93 n95 n94 n76 +10--- 1 +1-0-- 1 +1--10 1 +.names n91 n92 n89 n78 n93 n77 +00-1- 1 +00--0 1 +0-0-- 1 +.names n82 n87 n85 n79 n78 +1000 1 +.names n81 n80 n79 +11 1 +.names i_10_ i_15_ i_11_ i_9_ n80 +1000 1 +.names i_13_ i_14_ i_12_ n81 +100 1 +.names n68 n84 n83 n82 +0-- 1 +-00 1 +.names i_15_ i_10_ i_11_ i_9_ n83 +1100 1 +.names i_15_ i_9_ i_10_ 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n161 n1209 +01---1 1 +10---- 1 +1-0--- 1 +1--00- 1 +.names n68 n1209 n1208 n777 n758 n173 n1210 +011--- 0 +10---- 0 +1-0--- 0 +---1-- 0 +----11 0 +.names n792 n773 n764 n783 n173 n163 n1211 +0100-- 1 +010-0- 1 +01-0-0 1 +0---00 1 +.names n798 n797 n795 n756 n173 n187 n1212 +0000-- 1 +000-00 1 +.names n755 n374 n135 n245 n196 n1213 +0---- 1 +-1000 1 +.names n1213 n1212 n796 n313 n135 n769 n1214 +1100-- 1 +110--0 1 +11-00- 1 +.names n826 n344 n132 n808 n802 n758 n1215 +110--- 1 +11-110 1 +.names n1215 n824 n812 n810 n135 n828 n1216 +11110- 1 +1111-1 1 +.names n842 n841 n839 n183 n819 n498 o_16_ +0000-- 0 +000-00 0 +.names n816 n185 n132 n769 n758 n755 n1218 +10---- 1 +1--000 1 +-00--- 1 +.names n870 n859 n1222 n863 n868 n862 n1219 +111100 1 +.names n865 i_14_ i_13_ i_12_ n176 n126 n1220 +0----- 1 +-0-11- 1 +-1-01- 1 +-1-0-1 1 +--001- 1 +--11-1 1 +.names n186 n689 n866 n419 n287 n226 n1221 +0----- 1 +-10000 1 +.names n867 n864 n1221 n683 n1220 n185 n1222 +11100- 1 +1110-0 1 +.names n185 n575 n147 n576 n153 n137 n1223 +00---- 1 +0-1--- 1 +110100 1 +.names n452 n871 n726 n874 n571 n206 n1224 +111000 1 +.names n873 n1224 n185 n1223 n186 n118 n1225 +1100-- 1 +110-0- 1 +1111-1 1 +.names n943 n944 n945 n185 n928 n118 n1226 +1100-- 1 +110-11 1 +.names n1226 n1238 n934 n921 n942 n642 n1227 +111100 1 +.names n1227 n1360 n1385 n1376 n149 n973 o_35_ +11110- 0 +1111-1 0 +.names i_14_ n96 i_12_ i_13_ i_15_ n157 n1229 +011--- 0 +01-01- 0 +110-0- 0 +1-00-1 0 +-1-10- 0 +.names n149 n897 n896 n1229 n778 n153 n1230 +0----- 1 +-11100 1 +.names n185 n196 n552 n289 n149 n147 n1231 +0000-- 1 +00--0- 1 +0---00 1 +--00-0 1 +.names n1234 n1351 n881 n166 n882 n173 n1232 +1110-- 1 +111-00 1 +.names n885 n163 n654 n489 n135 n198 n1233 +000--- 1 +00--00 1 +0-00-- 1 +.names n886 n1233 n469 n139 n149 n418 n1234 +1100-- 1 +110-0- 1 +110--0 1 +.names n357 n638 n380 n150 n198 n196 n1235 +0100-- 1 +01---0 1 +0-000- 1 +0---00 1 +.names n364 n135 n817 n762 n420 n235 n1236 +00---- 1 +0-1000 1 +.names n196 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1 +.names n157 n135 n756 n465 n198 n593 n1266 +11-0-- 0 +1---10 0 +-11--- 0 +.names n668 n185 n576 n494 n478 n1267 +00--- 1 +0-110 1 +.names n1266 n1267 n135 n478 n1268 +110- 1 +11-0 1 +.names i_11_ i_10_ n778 i_9_ n276 i_15_ n1269 +11-0-- 0 +11--11 0 +--1--- 0 +.names n132 n866 n506 n419 n308 n287 n1270 +0----- 1 +-00000 1 +.names n1270 n811 n1040 n1039 n985 n797 n1271 +110000 1 +.names n1222 n1036 n1271 n135 n141 n268 n1272 +1110-- 1 +111-0- 1 +111--1 1 +.names n1053 n863 n290 n217 n265 n591 n1273 +1101-- 1 +110--1 1 +11-11- 1 +.names n1052 n1051 n1047 n1277 n922 n842 n1274 +111110 1 +.names n1279 n1043 n1274 n1273 n129 n363 n1275 +11110- 1 +1111-1 1 +.names n597 n831 n671 n85 o_18_ n245 n1276 +1100-- 1 +1-000- 1 +-1---0 1 +----00 1 +.names n1276 n132 n250 n290 n85 n1277 +10--- 1 +1-100 1 +.names n704 n424 n556 n611 n196 n132 n1278 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n1050 n1049 n1278 n321 n186 n422 n1279 +11110- 1 +1111-0 1 +.names n183 i_14_ i_15_ i_13_ i_12_ n162 n1280 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n1352 +11-- 0 +1-11 0 +.names n168 n246 n127 n150 n149 n135 n1353 +0000-- 1 +000-0- 1 +0--0-0 1 +0---00 1 +.names n816 n185 n149 n511 n755 n196 n1354 +100--- 1 +10-0-- 1 +1-0-0- 1 +1--00- 1 +-00--0 1 +.names n1235 n893 n892 n173 n512 n1355 +1110- 1 +111-0 1 +.names n556 n79 n231 n241 n196 n149 n1356 +0000-- 1 +000-0- 1 +---0-0 1 +----00 1 +.names n1241 n806 n783 n592 n185 n163 n1357 +1100-- 1 +11---0 1 +1-000- 1 +1---00 1 +.names n971 n972 n198 n970 n435 n175 n1358 +100--- 1 +10-100 1 +.names n1248 n1245 n968 n961 n618 n199 n1359 +111110 1 +.names n1243 n1358 n952 n1359 n192 n964 n1360 +111110 1 +.names n186 i_14_ i_12_ i_13_ n157 n141 n1361 +100--- 1 +10-0-- 1 +10--0- 1 +1111-0 1 +1-100- 1 +1---00 1 +.names n84 n120 n186 n985 n1361 n544 n1362 +111--- 0 +11---0 0 +--1-0- 0 +---1-- 0 +.names n986 n860 n141 n265 n81 n222 n1363 +100--- 1 +10-1-- 1 +10--00 1 +.names n1258 n1257 n1363 n898 n987 n1364 +1111- 1 +111-0 1 +.names n1264 n247 n421 n468 n159 n132 n1365 +1000-- 1 +100-0- 1 +1--0-0 1 +1---00 1 +.names n425 n350 n638 n380 n205 n203 n1366 +0010-- 1 +001--0 1 +00-00- 1 +0---00 1 +.names n1263 n1260 n1259 n1014 n1366 n1365 n1367 +111111 1 +.names n1265 n245 n176 n126 n174 n593 n1368 +100--- 1 +10--0- 1 +10---1 1 +1-00-- 1 +.names n756 n898 n778 n173 n163 n1369 +010-- 1 +01-0- 1 +0-0-0 1 +---00 1 +.names n1272 n1035 n1033 n1028 n1369 n1368 n1370 +111111 1 +.names n365 n163 n303 i_8_ o_14_ n334 n1371 +000--- 1 +00-0-- 1 +00--0- 1 +0-0--1 1 +.names n1318 n1312 n1144 n1141 n1138 n369 n1372 +111110 1 +.names n1311 n1372 n366 n1371 n344 n364 n1373 +111110 1 +.names n795 n755 n899 n796 n196 n135 n1374 +0010-- 1 +001--0 1 +00-00- 1 +0---00 1 +.names n1349 n1230 n879 n756 n173 n187 n1375 +1110-- 1 +111-00 1 +.names n1382 n1232 n900 n1375 n1374 n1376 +11111 1 +.names n564 n782 n98 n81 n160 n128 n1377 +1----- 0 +-1---- 0 +--1111 0 +.names n430 n550 n247 n196 n128 n418 n1378 +000-0- 1 +000--0 1 +0--0-- 1 +.names n1353 n1352 n1378 n1377 n895 n894 n1379 +111100 1 +.names n891 n890 n187 n135 n816 n773 n1380 +0000-- 1 +00--11 1 +.names n468 n135 n198 n421 n379 n247 n1381 +00---- 1 +0--000 1 +-00--- 1 +.names n1379 n1355 n1354 n889 n1381 n1380 n1382 +111111 1 +.names n470 n135 n187 n783 n592 n337 n1383 +00---- 1 +0--000 1 +-00--- 1 +.names n1356 n1239 n951 n946 n857 n587 n1384 +110000 1 +.names n1357 n1240 n948 n1384 n1383 n291 n1385 +111110 1 +.names n630 n490 n332 n186 n87 n159 n1386 +0000-- 1 +000-0- 1 +0---00 1 +---0-0 1 +.names n1252 n1251 n983 n979 n975 n835 n1387 +111111 1 +.names n1362 n1387 n1386 n265 n527 n1388 +1111- 1 +111-0 1 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v b/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v new file mode 100644 index 000000000..ade09c3bc --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v @@ -0,0 +1,2668 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module spla(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, o_41_, o_42_, o_43_, o_44_, o_45_); + input i_0_; + input i_10_; + input i_11_; + input i_12_; + input i_13_; + input i_14_; + input i_15_; + input i_1_; + input i_2_; + input i_3_; + input i_4_; + input i_5_; + input i_6_; + input i_7_; + input i_8_; + input i_9_; + wire n100; + wire n1000; + wire n1001; + wire n1002; + wire n1003; + wire n1004; + wire n1005; + wire n1006; + wire n1007; + wire n1008; + wire n1009; + wire n101; + wire n1010; + wire n1011; + wire n1012; + wire n1013; + wire n1014; + wire n1015; + wire n1016; + wire n1017; + wire n1018; + wire n1019; + wire n102; + wire n1020; + wire n1021; + wire n1022; + wire n1023; + wire n1024; + wire n1025; + wire n1026; + wire n1028; + wire n1029; + wire n103; + wire n1030; + wire n1031; + wire n1032; + wire n1033; + wire n1034; + wire n1035; + wire n1036; + wire n1037; + wire n1038; + wire n1039; + wire n104; + wire n1040; + wire n1041; + wire n1042; + wire n1043; + wire n1044; + wire n1045; + wire n1046; + wire n1047; + wire n1048; + wire n1049; + wire n105; + wire n1050; + wire n1051; + wire n1052; + wire n1053; + wire n1054; + wire n1055; + wire n1056; + wire n1057; + wire n1058; + wire n1059; + wire n1060; + wire n1061; + wire n1062; + wire n1063; + wire n1064; + wire n1065; + wire n1066; + wire n1067; + wire n1068; + wire n1069; + wire n107; + wire n1070; + wire n1071; + wire n1072; + wire n1073; + wire n1074; + wire n1075; + wire n1076; + wire n1077; + wire n1078; + wire n1079; + wire n108; + wire n1080; + wire n1081; + wire n1085; + wire n1086; + wire n1087; + wire n1088; + wire n1089; + wire n109; + wire n1090; + wire n1091; + wire n1092; + wire n1094; + wire n1097; + wire n110; + wire n1103; + wire n1104; + wire n1105; + wire n1106; + wire n1108; + wire n1109; + wire n111; + wire n1110; + wire n1112; + wire n1117; + wire n1118; + wire n1119; + wire n112; + wire n1120; + wire n1121; + wire n1122; + wire n1123; + wire n1124; + wire n1125; + wire n1126; + wire n1127; + wire n1128; + wire n1129; + wire n113; + wire n1130; + wire n1131; + wire n1132; + wire n1133; + wire n1134; + wire n1135; + wire n1136; + wire n1137; + wire n1138; + wire n1139; + wire n114; + wire n1140; + wire n1141; + wire n1142; + wire n1143; + wire n1144; + wire n1145; + wire n1146; + wire n1147; + wire n1148; + wire n1149; + wire n115; + wire n1150; + wire n1151; + wire n1152; + wire n1153; + wire n1154; + wire n1155; + wire n1156; + wire n1157; + wire n1158; + wire n1159; + wire n1160; + wire n1161; + wire n1162; + wire n1163; + wire n1164; + wire n1165; + wire n1166; + wire n1167; + wire n1168; + wire n1169; + wire n117; + wire n1170; + wire n1171; + wire n1172; + wire n1173; + wire n1174; + wire n1175; + wire n1176; + wire n1177; + wire n1178; + wire n1179; + wire n118; + wire n1180; + wire n1181; + wire n1182; + wire n1183; + wire n1184; + wire n1185; + wire n1186; + wire n1187; + wire n1188; + wire n1189; + wire n119; + wire n1190; + wire n1191; + wire n1192; + wire n1193; + wire n1194; + wire n1195; + wire n1196; + wire n1197; + wire n1198; + wire n1199; + wire n120; + wire n1200; + wire n1201; + wire n1202; + wire n1203; + wire n1204; + wire n1205; + wire n1206; + wire n1207; + wire n1208; + wire n1209; + wire n121; + wire n1210; + wire n1211; + wire n1212; + wire n1213; + wire n1214; + wire n1215; + wire n1216; + wire n1218; + wire n1219; + wire n122; + wire n1220; + wire n1221; + wire n1222; + wire n1223; + wire n1224; + wire n1225; + wire n1226; + wire n1227; + wire n1229; + wire n123; + wire n1230; + wire n1231; + wire n1232; + wire n1233; + wire n1234; + wire n1235; + wire n1236; + wire n1237; + wire n1238; + wire n1239; + wire n124; + wire n1240; + wire n1241; + wire n1242; + wire n1243; + wire n1244; + wire n1245; + wire n1246; + wire n1247; + wire n1248; + wire n1249; + wire n125; + wire n1251; + wire n1252; + wire n1253; + wire n1254; + wire n1255; + wire n1256; + wire n1257; + wire n1258; + wire n1259; + wire n126; + wire n1260; + wire n1261; + wire n1262; + wire n1263; + wire n1264; + wire n1265; + wire n1266; + wire n1267; + wire n1268; + wire n1269; + wire n127; + wire n1270; + wire n1271; + wire n1272; + wire n1273; + wire n1274; + wire n1275; + wire n1276; + wire n1277; + wire n1278; + wire n1279; + wire n128; + wire n1280; + wire n1281; + wire n1283; + wire n1284; + wire n1285; + wire n1286; + wire n1287; + wire n1288; + wire n1289; + wire n129; + wire n1290; + wire n1291; + wire n1292; + wire n1293; + wire n1294; + wire n1296; + wire n1297; + wire n1298; + wire n130; + wire n1300; + wire n1301; + wire n1302; + wire n1303; + wire n1304; + wire n1305; + wire n1306; + wire n1307; + wire n1308; + wire n1309; + wire n131; + wire n1310; + wire n1311; + wire n1312; + wire n1313; + wire n1314; + wire n1315; + wire n1316; + wire n1317; + wire n1318; + wire n1319; + wire n132; + wire n1320; + wire n1321; + wire n1322; + wire n1323; + wire n1324; + wire n1326; + wire n1327; + wire n1328; + wire n1329; + wire n133; + wire n1330; + wire n1331; + wire n1332; + wire n1333; + wire n1334; + wire n1335; + wire n1336; + wire n1337; + wire n1338; + wire n1339; + wire n134; + wire n1340; + wire n1341; + wire n1342; + wire n1343; + wire n1344; + wire n1346; + wire n1347; + wire n1348; + wire n1349; + wire n135; + wire n1350; + wire n1351; + wire n1352; + wire n1353; + wire n1354; + wire n1355; + wire n1356; + wire n1357; + wire n1358; + wire n1359; + wire n136; + wire n1360; + wire n1361; + wire n1362; + wire n1363; + wire n1364; + wire n1365; + wire n1366; + wire n1367; + wire n1368; + wire n1369; + wire n137; + wire n1370; + wire n1371; + wire n1372; + wire n1373; + wire n1374; + wire n1375; + wire n1376; + wire n1377; + wire n1378; + wire n1379; + wire n138; + wire n1380; + wire n1381; + wire n1382; + wire n1383; + wire n1384; + wire n1385; + wire n1386; + wire n1387; + wire n1388; + wire n139; + wire n140; + wire n141; + wire n142; + wire n143; + wire n144; + wire n145; + wire n146; + wire n147; + wire n148; + wire n149; + wire n150; + wire n151; + wire n152; + wire n153; + wire n154; + wire n155; + wire n156; + wire n157; + wire n158; + wire n159; + wire n160; + wire n161; + wire n162; + wire n163; + wire n164; + wire n165; + wire n166; + wire n167; + wire n168; + wire n169; + wire n170; + wire n171; + wire n172; + wire n173; + wire n174; + wire n175; + wire n176; + wire n177; + wire n178; + wire n179; + wire n180; + wire n181; + wire n182; + wire n183; + wire n184; + wire n185; + wire n186; + wire n187; + wire n188; + wire n189; + wire n190; + wire n191; + wire n192; + wire n193; + wire n194; + wire n195; + wire n196; + wire n197; + wire n198; + wire n199; + wire n200; + wire n201; + wire n202; + wire n203; + wire n205; + wire n206; + wire n207; + wire n208; + wire n209; + wire n210; + wire n211; + wire n212; + wire n213; + wire n214; + wire n215; + wire n216; + wire n217; + wire n218; + wire n220; + wire n221; + wire n222; + wire n223; + wire n224; + wire n225; + wire n226; + wire n227; + wire n228; + wire n229; + wire n230; + wire n231; + wire n232; + wire n233; + wire n234; + wire n235; + wire n236; + wire n237; + wire n238; + wire n239; + wire n240; + wire n241; + wire n242; + wire n243; + wire n244; + wire n245; + wire n246; + wire n247; + wire n248; + wire n249; + wire n250; + wire n251; + wire n252; + wire n253; + wire n254; + wire n255; + wire n256; + wire n257; + wire n258; + wire n259; + wire n260; + wire n261; + wire n262; + wire n263; + wire n264; + wire n265; + wire n266; + wire n267; + wire n268; + wire n269; + wire n270; + wire n272; + wire n273; + wire n274; + wire n275; + wire n276; + wire n277; + wire n278; + wire n279; + wire n280; + wire n281; + wire n282; + wire n283; + wire n284; + wire n285; + wire n286; + wire n287; + wire n288; + wire n289; + wire n290; + wire n291; + wire n292; + wire n293; + wire n294; + wire n295; + wire n296; + wire n297; + wire n298; + wire n299; + wire n300; + wire n301; + wire n302; + wire n303; + wire n304; + wire n305; + wire n306; + wire n307; + wire n308; + wire n309; + wire n310; + wire n311; + wire n312; + wire n313; + wire n314; + wire n315; + wire n316; + wire n317; + wire n318; + wire n319; + wire n320; + wire n321; + wire n322; + wire n323; + wire n324; + wire n325; + wire n326; + wire n327; + wire n328; + wire n329; + wire n330; + wire n331; + wire n332; + wire n333; + wire n334; + wire n335; + wire n336; + wire n337; + wire n338; + wire n339; + wire n340; + wire n341; + wire n342; + wire n343; + wire n344; + wire n345; + wire n346; + wire n347; + wire n348; + wire n349; + wire n350; + wire n351; + wire n352; + wire n353; + wire n354; + wire n355; + wire n356; + wire n357; + wire n358; + wire n359; + wire n360; + wire n361; + wire n362; + wire n363; + wire n364; + wire n365; + wire n366; + wire n367; + wire n368; + wire n369; + wire n370; + wire n371; + wire n372; + wire n373; + wire n374; + wire n375; + wire n376; + wire n377; + wire n378; + wire n379; + wire n380; + wire n381; + wire n382; + wire n383; + wire n384; + wire n385; + wire n386; + wire n387; + wire n388; + wire n389; + wire n390; + wire n391; + wire n392; + wire n393; + wire n394; + wire n395; + wire n396; + wire n397; + wire n398; + wire n399; + wire n400; + wire n401; + wire n402; + wire n403; + wire n404; + wire n405; + wire n406; + wire n407; + wire n408; + wire n409; + wire n410; + wire n411; + wire n412; + wire n413; + wire n414; + wire n415; + wire n416; + wire n417; + wire n418; + wire n419; + wire n420; + wire n421; + wire n422; + wire n423; + wire n424; + wire n425; + wire n426; + wire n427; + wire n428; + wire n429; + wire n430; + wire n431; + wire n432; + wire n433; + wire n434; + wire n435; + wire n436; + wire n437; + wire n438; + wire n439; + wire n440; + wire n441; + wire n442; + wire n443; + wire n444; + wire n445; + wire n446; + wire n447; + wire n448; + wire n449; + wire n450; + wire n451; + wire n452; + wire n453; + wire n454; + wire n455; + wire n456; + wire n457; + wire n458; + wire n459; + wire n460; + wire n461; + wire n462; + wire n463; + wire n464; + wire n465; + wire n466; + wire n467; + wire n468; + wire n469; + wire n470; + wire n471; + wire n472; + wire n473; + wire n474; + wire n475; + wire n476; + wire n477; + wire n478; + wire n479; + wire n480; + wire n481; + wire n482; + wire n483; + wire n484; + wire n485; + wire n486; + wire n487; + wire n488; + wire n489; + wire n490; + wire n491; + wire n492; + wire n493; + wire n494; + wire n495; + wire n496; + wire n497; + wire n498; + wire n499; + wire n500; + wire n501; + wire n502; + wire n503; + wire n504; + wire n505; + wire n506; + wire n507; + wire n508; + wire n509; + wire n510; + wire n511; + wire n512; + wire n513; + wire n514; + wire n515; + wire n516; + wire n517; + wire n518; + wire n519; + wire n520; + wire n521; + wire n522; + wire n523; + wire n524; + wire n525; + wire n526; + wire n527; + wire n528; + wire n529; + wire n530; + wire n531; + wire n532; + wire n533; + wire n534; + wire n535; + wire n536; + wire n537; + wire n538; + wire n539; + wire n540; + wire n541; + wire n542; + wire n543; + wire n544; + wire n545; + wire n546; + wire n548; + wire n549; + wire n550; + wire n551; + wire n552; + wire n553; + wire n554; + wire n555; + wire n556; + wire n557; + wire n558; + wire n559; + wire n560; + wire n561; + wire n562; + wire n563; + wire n564; + wire n565; + wire n566; + wire n567; + wire n568; + wire n569; + wire n570; + wire n571; + wire n572; + wire n573; + wire n574; + wire n575; + wire n576; + wire n577; + wire n578; + wire n579; + wire n580; + wire n581; + wire n582; + wire n583; + wire n584; + wire n585; + wire n586; + wire n587; + wire n588; + wire n589; + wire n590; + wire n591; + wire n592; + wire n593; + wire n594; + wire n595; + wire n596; + wire n597; + wire n598; + wire n599; + wire n600; + wire n601; + wire n602; + wire n603; + wire n604; + wire n605; + wire n606; + wire n607; + wire n608; + wire n609; + wire n610; + wire n611; + wire n612; + wire n613; + wire n614; + wire n615; + wire n616; + wire n617; + wire n618; + wire n619; + wire n620; + wire n621; + wire n622; + wire n623; + wire n624; + wire n625; + wire n626; + wire n627; + wire n628; + wire n629; + wire n630; + wire n631; + wire n632; + wire n633; + wire n634; + wire n635; + wire n636; + wire n637; + wire n638; + wire n639; + wire n640; + wire n641; + wire n642; + wire n643; + wire n644; + wire n645; + wire n646; + wire n647; + wire n648; + wire n649; + wire n650; + wire n651; + wire n652; + wire n653; + wire n654; + wire n655; + wire n656; + wire n657; + wire n658; + wire n659; + wire n660; + wire n661; + wire n662; + wire n663; + wire n664; + wire n665; + wire n666; + wire n667; + wire n668; + wire n669; + wire n67; + wire n670; + wire n671; + wire n672; + wire n673; + wire n674; + wire n675; + wire n676; + wire n677; + wire n678; + wire n679; + wire n68; + wire n680; + wire n681; + wire n682; + wire n683; + wire n684; + wire n685; + wire n686; + wire n687; + wire n688; + wire n689; + wire n69; + wire n690; + wire n691; + wire n692; + wire n693; + wire n694; + wire n695; + wire n696; + wire n697; + wire n698; + wire n699; + wire n70; + wire n700; + wire n701; + wire n702; + wire n703; + wire n704; + wire n705; + wire n706; + wire n707; + wire n708; + wire n709; + wire n71; + wire n710; + wire n711; + wire n712; + wire n713; + wire n714; + wire n715; + wire n717; + wire n718; + wire n719; + wire n72; + wire n720; + wire n721; + wire n722; + wire n723; + wire n724; + wire n725; + wire n726; + wire n727; + wire n728; + wire n729; + wire n730; + wire n731; + wire n732; + wire n733; + wire n734; + wire n735; + wire n736; + wire n737; + wire n738; + wire n739; + wire n740; + wire n741; + wire n742; + wire n743; + wire n744; + wire n745; + wire n746; + wire n747; + wire n748; + wire n749; + wire n750; + wire n751; + wire n752; + wire n753; + wire n754; + wire n755; + wire n756; + wire n757; + wire n758; + wire n759; + wire n76; + wire n760; + wire n761; + wire n762; + wire n763; + wire n764; + wire n765; + wire n766; + wire n767; + wire n768; + wire n769; + wire n77; + wire n770; + wire n771; + wire n772; + wire n773; + wire n774; + wire n775; + wire n776; + wire n777; + wire n778; + wire n779; + wire n78; + wire n780; + wire n781; + wire n782; + wire n783; + wire n784; + wire n785; + wire n786; + wire n787; + wire n788; + wire n789; + wire n79; + wire n790; + wire n791; + wire n792; + wire n793; + wire n794; + wire n795; + wire n796; + wire n797; + wire n798; + wire n799; + wire n80; + wire n800; + wire n802; + wire n803; + wire n804; + wire n805; + wire n806; + wire n807; + wire n808; + wire n809; + wire n81; + wire n810; + wire n811; + wire n812; + wire n813; + wire n814; + wire n815; + wire n816; + wire n817; + wire n818; + wire n819; + wire n82; + wire n820; + wire n821; + wire n822; + wire n823; + wire n824; + wire n825; + wire n826; + wire n827; + wire n828; + wire n829; + wire n83; + wire n830; + wire n831; + wire n832; + wire n834; + wire n835; + wire n836; + wire n837; + wire n838; + wire n839; + wire n84; + wire n840; + wire n841; + wire n842; + wire n844; + wire n845; + wire n846; + wire n848; + wire n849; + wire n85; + wire n850; + wire n851; + wire n852; + wire n855; + wire n856; + wire n857; + wire n858; + wire n859; + wire n86; + wire n860; + wire n861; + wire n862; + wire n863; + wire n864; + wire n865; + wire n866; + wire n867; + wire n868; + wire n869; + wire n87; + wire n870; + wire n871; + wire n872; + wire n873; + wire n874; + wire n875; + wire n876; + wire n878; + wire n879; + wire n88; + wire n880; + wire n881; + wire n882; + wire n883; + wire n884; + wire n885; + wire n886; + wire n887; + wire n888; + wire n889; + wire n89; + wire n890; + wire n891; + wire n892; + wire n893; + wire n894; + wire n895; + wire n896; + wire n897; + wire n898; + wire n899; + wire n90; + wire n900; + wire n901; + wire n902; + wire n903; + wire n904; + wire n905; + wire n906; + wire n907; + wire n908; + wire n909; + wire n91; + wire n910; + wire n911; + wire n912; + wire n913; + wire n914; + wire n915; + wire n916; + wire n917; + wire n918; + wire n919; + wire n92; + wire n920; + wire n921; + wire n922; + wire n923; + wire n924; + wire n925; + wire n926; + wire n927; + wire n928; + wire n929; + wire n93; + wire n930; + wire n931; + wire n932; + wire n933; + wire n934; + wire n935; + wire n936; + wire n937; + wire n938; + wire n939; + wire n94; + wire n940; + wire n941; + wire n942; + wire n943; + wire n944; + wire n945; + wire n946; + wire n947; + wire n948; + wire n949; + wire n95; + wire n950; + wire n951; + wire n952; + wire n953; + wire n954; + wire n955; + wire n956; + wire n957; + wire n958; + wire n959; + wire n96; + wire n960; + wire n961; + wire n962; + wire n963; + wire n964; + wire n965; + wire n966; + wire n967; + wire n968; + wire n969; + wire n97; + wire n970; + wire n971; + wire n972; + wire n973; + wire n974; + wire n975; + wire n976; + wire n977; + wire n978; + wire n979; + wire n98; + wire n980; + wire n981; + wire n982; + wire n983; + wire n984; + wire n985; + wire n986; + wire n987; + wire n988; + wire n989; + wire n990; + wire n991; + wire n992; + wire n993; + wire n994; + wire n995; + wire n996; + wire n997; + wire n998; + wire n999; + output o_0_; + output o_10_; + output o_11_; + output o_12_; + output o_13_; + output o_14_; + output o_15_; + output o_16_; + output o_17_; + output o_18_; + output o_19_; + output o_1_; + output o_20_; + output o_21_; + output o_22_; + output o_23_; + output o_24_; + output o_25_; + output o_26_; + output o_27_; + output o_28_; + output o_29_; + output o_2_; + output o_30_; + output o_31_; + output o_32_; + output o_33_; + output o_34_; + output o_35_; + output o_36_; + output o_37_; + output o_38_; + output o_39_; + output o_3_; + output o_40_; + output o_41_; + output o_42_; + output o_43_; + output o_44_; + output o_45_; + output o_4_; + output o_5_; + output o_6_; + output o_7_; + output o_8_; + output o_9_; + assign o_0_ = 8'hae >> { i_7_, o_2_, n72 }; + assign o_3_ = 4'he >> { o_6_, o_11_ }; + assign n164 = 8'h08 >> { i_6_, i_7_, i_8_ }; + assign n1064 = 32'd286331157 >> { n416, n119, n122, n174, n777 }; + assign n1065 = 64'h00011111000fffff >> { n174, n205, n333, n631, n551, n323 }; + assign n1066 = 32'd2155905024 >> { n966, n544, n1073, n1067, n1070 }; + assign n1067 = 64'h8000800000008000 >> { n585, n205, n584, n856, n1068, n1069 }; + assign n1068 = 16'h0ddd >> { n185, n758, n861, n186 }; + assign n1069 = 16'hbbab >> { n928, o_34_, n491, i_8_ }; + assign n1070 = 32'd269488145 >> { n360, n631, n278, n1071, n1072 }; + assign n1071 = 32'd2862785186 >> { n498, n222, n360, n118, n186 }; + assign n1072 = 32'd2863311522 >> { n471, n119, n420, n931, n203 }; + assign n1073 = 64'h0008000800080808 >> { n235, n389, n132, n1074, n1075, n1077 }; + assign n165 = 16'h0777 >> { n147, n149, n145, n156 }; + assign n1074 = 8'h51 >> { n159, n532, n938 }; + assign n1075 = 32'd707406506 >> { n161, n93, n327, n498, n1076 }; + assign n1076 = 32'd3149597627 >> { i_8_, n240, n559, n186, n807 }; + assign n1077 = 64'h044405550c4c0d5d >> { n132, n323, n559, n186, n217, n551 }; + assign n1078 = 8'h01 >> { n168, n169, n170 }; + assign n1079 = 32'd17109269 >> { n246, n203, n179, n303, n330 }; + assign n1080 = 8'ha2 >> { n931, n336, n443 }; + assign n1081 = 64'h0000000000000001 >> { n379, n119, n247, n380, n420, n471 }; + assign o_40_ = 64'h22222222f2222222 >> { i_7_, n89, n67, i_8_, i_6_, n876 }; + assign o_42_ = 4'hd >> { n497, n325 }; + assign n166 = 8'h08 >> { i_10_, i_11_, i_9_ }; + assign o_43_ = 8'h7f >> { n1298, n834, n1025 }; + assign n1085 = 64'haaaaaaaa2aaaaaaa >> { n511, n638, n838, n802, n896, n154 }; + assign n1086 = 64'h15373737153f3f3f >> { n84, n149, n83, n232, n154, n222 }; + assign n1087 = 16'h1101 >> { n869, n145, n662, n644 }; + assign n1088 = 32'd32768 >> { n992, n1044, n1089, n880, n580 }; + assign n1089 = 64'h02020002ffff00ff >> { n149, n1090, n145, n800, n755, n816 }; + assign n1090 = 32'd128 >> { n524, n755, n480, n1091, n1092 }; + assign n1091 = 64'h7ff8fff97ffeffff >> { n326, n166, i_15_, i_14_, i_12_, i_13_ }; + assign n1092 = 64'hba5cff5dba5cffff >> { n326, n498, i_15_, i_13_, i_12_, i_14_ }; + assign o_45_ = 32'd2139062271 >> { n1094, n95, n1225, n1216, n1348 }; + assign n167 = 16'h8000 >> { n98, n146, n120, n139 }; + assign n1094 = 64'hff77fff7ff7ffff7 >> { i_6_, i_5_, i_3_, i_4_, n216, n90 }; + assign o_8_ = 8'h02 >> { i_1_, i_0_, i_3_ }; + assign o_19_ = 16'h0080 >> { i_4_, i_3_, i_5_, n1097 }; + assign n1097 = 32'd32768 >> { i_2_, n103, i_1_, i_0_, n67 }; + assign o_20_ = 16'h0080 >> { i_5_, i_3_, n1097, i_4_ }; + assign o_21_ = 32'd4177066224 >> { n105, n98, n848, n846, n109 }; + assign o_24_ = 16'h8000 >> { n90, n155, i_3_, i_4_ }; + assign o_25_ = 16'h8000 >> { n90, n102, i_3_, i_4_ }; + assign o_26_ = 32'd4160747511 >> { n79, n1104, n1106, n1105, n1103 }; + assign n1103 = 32'd3149597627 >> { i_3_, n155, n72, n85, n1104 }; + assign n168 = 64'h8080800000800000 >> { n123, n120, i_15_, n96, n133, n98 }; + assign n1104 = 32'd131586 >> { n216, n89, n855, n849, n852 }; + assign n1105 = 32'd3149597627 >> { i_3_, n111, n72, n556, n1104 }; + assign n1106 = 32'd128 >> { n111, i_5_, i_3_, n90, i_4_ }; + assign o_27_ = 32'd4160747511 >> { n94, n1104, n1110, n1109, n1108 }; + assign n1108 = 32'd3149597627 >> { i_3_, n92, n72, n87, n1104 }; + assign n1109 = 32'd3149597627 >> { i_3_, n102, n72, n549, n1104 }; + assign n1110 = 32'd32768 >> { n111, n90, i_3_, i_5_, i_4_ }; + assign o_28_ = 16'h7f77 >> { n550, n1112, n1105, n1109 }; + assign n1112 = 4'h2 >> { n855, n1094 }; + assign o_29_ = 32'd1414856532 >> { n1112, n565, n94, n79, n1104 }; + assign n169 = 16'h8000 >> { n98, n123, n133, n124 }; + assign o_30_ = 32'd4160747511 >> { n379, n1112, o_34_, n1108, n1103 }; + assign o_31_ = 64'h8000a02008002020 >> { i_6_, i_5_, i_4_, i_7_, i_3_, n90 }; + assign o_41_ = 8'h80 >> { n70, n605, n134 }; + assign n1117 = 64'h0202020202020222 >> { n145, n159, n183, n119, n158, n165 }; + assign n1118 = 64'h0080008000808080 >> { n153, n181, n171, n172, n177, n1120 }; + assign n1119 = 64'ha8a08880a0a00080 >> { n123, n80, i_15_, n120, n166, n146 }; + assign n1120 = 64'h0000000100010001 >> { n103, n1119, n167, n168, n169, n170 }; + assign n1121 = 64'h5555777f777f777f >> { n123, n124, n128, n121, n120, n162 }; + assign n1122 = 64'h0000000000000001 >> { n119, n129, n130, n153, n156, n181 }; + assign n1123 = 64'h111111111111111f >> { n147, n150, n122, n137, n185, n186 }; + assign n170 = 16'h8000 >> { n93, n123, n148, n133 }; + assign n1124 = 64'h0022222200020202 >> { n1122, n189, n207, n185, n206, n1123 }; + assign n1125 = 32'd1434419071 >> { n83, n123, n80, n120, n98 }; + assign n1126 = 64'h0022202220222022 >> { n130, n93, n160, n1125, n214, n213 }; + assign n1127 = 64'h0000000000000080 >> { n210, n211, n212, n1126, n208, n209 }; + assign n1128 = 64'h5555555555555557 >> { n163, n179, n186, n196, n149, n246 }; + assign n1129 = 64'h0000000080000000 >> { n255, n1137, n1135, n256, n258, n259 }; + assign n1130 = 64'h0080008000808080 >> { n196, n240, n221, n1128, n1309, n1129 }; + assign n1131 = 64'h00011111000fffff >> { n229, n241, n196, n135, o_18_, n149 }; + assign n1132 = 64'h00011111000fffff >> { n111, n161, n232, n236, n246, n247 }; + assign n1133 = 64'h11011f0f1101ff0f >> { n105, n185, n1132, n146, n225, n242 }; + assign n171 = 4'h8 >> { n92, n146 }; + assign n1134 = 64'h4444444444444464 >> { n229, n242, n244, n250, n246, n132 }; + assign n1135 = 32'd2148040840 >> { n135, n132, n1134, n251, n253 }; + assign n1136 = 64'hfffefefeffaa0000 >> { n139, n69, n194, n159, n154, n196 }; + assign n1137 = 64'h0000077707770777 >> { n232, o_18_, n203, n247, n1136, n223 }; + assign n1138 = 64'h111f010f010f010f >> { n372, n374, n287, n324, n163, n149 }; + assign n1139 = 64'hff80808080808080 >> { n123, n151, n136, n120, n141, n164 }; + assign n1140 = 64'h0001010100ff55ff >> { n308, n149, n303, n196, n173, n135 }; + assign n1141 = 64'h0008000808080008 >> { n332, n347, n313, n362, n348, n1140 }; + assign n1142 = 64'h0001010100115555 >> { n162, n173, n350, n324, n320, n352 }; + assign n1143 = 64'h4444444444444446 >> { n147, n153, n156, n175, n358, n240 }; + assign n172 = 64'h0015151500373737 >> { n175, n138, n173, n162, n156, n174 }; + assign n1144 = 64'h0b0b000b09090009 >> { n300, n283, n361, n359, n240, n1143 }; + assign n1145 = 64'h0008000800080808 >> { n375, n376, n186, n394, n390, n410 }; + assign n1146 = 64'h8000000000000000 >> { n1145, n1322, n383, n387, n1149, n408 }; + assign n1147 = 64'h0202020202020222 >> { n196, n240, n194, n375, n381, n382 }; + assign n1148 = 64'h0202022200020022 >> { n400, n196, n183, n290, n407, n406 }; + assign n1149 = 32'd2147483648 >> { n1148, n395, n399, n1151, n402 }; + assign n1150 = 64'hfffffffffffffffd >> { n85, n282, n290, n323, n378, n400 }; + assign n1151 = 32'd1381653 >> { n379, n240, n1150, n132, n401 }; + assign n1152 = 32'd1431655767 >> { n289, n290, n323, n389, n149 }; + assign n1153 = 64'h0202020202020222 >> { n289, n361, n380, n145, n409, n1152 }; + assign n173 = 4'h8 >> { n105, n146 }; + assign n1154 = 64'h3133313311113133 >> { n414, n120, n86, n544, n546, n182 }; + assign n1155 = 64'h0000000000008000 >> { n461, n545, n452, n457, n1328, n448 }; + assign n1156 = 64'h0000000000000001 >> { n416, n417, n419, n422, n423, n424 }; + assign n1157 = 32'd287244559 >> { n1156, n135, n132, n420, n421 }; + assign n1158 = 64'haa88a888aa80a080 >> { n148, n83, n164, n124, n161, n133 }; + assign n1159 = 64'h0002000200020202 >> { n223, n418, n1158, n453, n455, n454 }; + assign n1160 = 64'h0000000000008000 >> { n292, n499, n495, n1165, n493, n500 }; + assign n1161 = 64'h0080008000808080 >> { n422, n490, n183, n481, n1160, n533 }; + assign n1162 = 64'h0002000202020002 >> { n468, n464, n240, n463, n469, n467 }; + assign n1163 = 64'h0008000a8888aaaa >> { n135, n132, n470, n471, n466, n1162 }; + assign o_6_ = 32'd2400161679 >> { n97, n67, n76, n89, n98 }; + assign n174 = 4'h8 >> { n93, n160 }; + assign n1164 = 64'hff80808080808080 >> { n136, n88, n418, n86, n103, n148 }; + assign n1165 = 64'h0001010100111111 >> { n1164, n198, n468, n146, n496, n497 }; + assign n1166 = 32'd1886908663 >> { n205, n511, n363, n157, n86 }; + assign n1167 = 64'h00ffffff00010101 >> { n372, n207, n512, n501, n502, n119 }; + assign n1168 = 64'h8000800000008000 >> { n513, n137, n1166, n503, n508, n1167 }; + assign n1169 = 64'h1555155515553777 >> { n183, n336, n157, n86, n163, n129 }; + assign n1170 = 64'h0000000000000002 >> { n517, n521, n528, n529, n530, n518 }; + assign n1171 = 64'h0000800080008000 >> { n478, n132, n1169, n514, n1170, n522 }; + assign n1172 = 32'd17895263 >> { n94, n132, n549, n312, n183 }; + assign n1173 = 64'h0002020200aaaaaa >> { n162, n196, n551, n558, n559, n555 }; + assign n175 = 4'h8 >> { n123, n176 }; + assign n1174 = 32'd2763306 >> { n132, n563, n79, n183, n560 }; + assign n1175 = 64'h0101000111ff00ff >> { n185, n82, n135, n558, n554, n562 }; + assign n1176 = 64'h0088000808880808 >> { n561, n377, n186, n562, n1175, n1174 }; + assign n1177 = 32'd1431655767 >> { n94, n79, n552, n565, n196 }; + assign n1178 = 64'h0001010100555555 >> { n173, n162, n554, n556, n558, n566 }; + assign n1179 = 64'h0080008000808080 >> { n551, n565, n174, n1178, n1181, n1177 }; + assign n1180 = 64'hfffffffffffffffe >> { n550, n551, n554, n556, n558, n562 }; + assign n1181 = 32'd1381653 >> { n559, n240, n132, n1180, n564 }; + assign n1182 = 64'ha2b3a2b30000a2b3 >> { n576, o_18_, n197, n604, n186, n480 }; + assign n1183 = 64'h0000008000800080 >> { n301, n194, n606, n601, n600, n607 }; + assign n176 = 16'h0080 >> { i_9_, i_11_, i_10_, i_15_ }; + assign n1184 = 64'h8000000000000000 >> { n1182, n192, n1183, n410, n1186, n1127 }; + assign n1185 = 64'h1111111f0101010f >> { n603, n196, n149, n163, n558, n242 }; + assign n1186 = 64'h222a222aaaaa222a >> { n240, n279, n222, n81, n88, n1185 }; + assign n1187 = 64'h44444ccc4ccc4ccc >> { n376, n161, n93, n380, n624, n133 }; + assign n1188 = 64'h8000000000000000 >> { n1187, n1337, n1340, n679, n690, n1305 }; + assign n1189 = 64'h080f080f080f888f >> { n185, n196, n84, n641, n377, n300 }; + assign n1190 = 32'd3452782029 >> { n370, n182, n641, n1189, n81 }; + assign n1191 = 64'h5555444044404440 >> { n111, n157, n84, n83, n102, n593 }; + assign n1192 = 64'h0000000100010001 >> { n160, n1191, n649, n650, n651, n652 }; + assign n1193 = 64'h8000000000000000 >> { n1192, n643, n645, n648, n653, n657 }; + assign n177 = 64'h0001010100111111 >> { n162, n147, n179, n150, n178, n180 }; + assign n1194 = 64'heaaac080c080c080 >> { n105, n146, n83, n136, n133, n176 }; + assign n1195 = 32'd65793 >> { n1194, n81, n662, n663, n664 }; + assign n1196 = 64'h40404a6a42624a6a >> { n157, n223, n84, n81, n151, n185 }; + assign n1197 = 64'h1010111100100011 >> { n300, n654, n557, n673, n672, n669 }; + assign n1198 = 64'h8080008080000080 >> { n678, n1196, n185, n674, n676, n1197 }; + assign n1199 = 64'h0004040400555555 >> { n244, n145, n556, n135, n272, n693 }; + assign n1200 = 64'h0080008880808088 >> { n435, o_14_, n163, n734, n731, n741 }; + assign n1201 = 64'h8000000000000000 >> { n107, n1199, n1200, n735, n739, n743 }; + assign n1202 = 64'hdcfcdcfc5454dcfc >> { n415, n182, n176, n483, n371, n86 }; + assign n1203 = 64'h0010101000551155 >> { n766, n198, n758, n532, n159, n757 }; + assign n178 = 16'h8000 >> { n84, n160, n123, n134 }; + assign n1204 = 64'h0000000000000008 >> { n759, n760, n763, n765, n761, n775 }; + assign n1205 = 64'h0001010100ffffff >> { n163, o_17_, n783, n755, n766, n556 }; + assign n1206 = 64'h0000008000800080 >> { n501, n179, n779, n780, n781, n791 }; + assign n1207 = 32'd2147483648 >> { n1205, n1206, n776, n784, n788 }; + assign n1208 = 64'h10bababababababa >> { n98, n128, n146, n88, i_14_, n68 }; + assign n1209 = 64'h6e6e6eee2a2a2aaa >> { n161, n111, n164, n148, n160, n68 }; + assign n1210 = 64'h0000009500950095 >> { n173, n758, n777, n1208, n1209, n68 }; + assign n1211 = 64'h0004040400445555 >> { n163, n173, n783, n764, n773, n792 }; + assign n1212 = 64'h0001000100010101 >> { n187, n173, n756, n795, n797, n798 }; + assign n1213 = 32'd1431655773 >> { n196, n245, n135, n374, n755 }; + assign n179 = 4'h8 >> { n98, n133 }; + assign n1214 = 64'h0008008808080888 >> { n769, n135, n313, n796, n1212, n1213 }; + assign n1215 = 64'h0808080888080808 >> { n758, n802, n808, n132, n344, n826 }; + assign n1216 = 64'h8000800000008000 >> { n828, n135, n810, n812, n824, n1215 }; + assign o_16_ = 64'hfffefffefffefefe >> { n498, n819, n183, n839, n841, n842 }; + assign n1218 = 64'h23232323232323ab >> { n755, n758, n769, n132, n185, n816 }; + assign n1219 = 64'h0000000000008000 >> { n862, n868, n863, n1222, n859, n870 }; + assign n1220 = 64'hf7dff5dd77df5555 >> { n126, n176, i_12_, i_13_, i_14_, n865 }; + assign n1221 = 64'h555555555555555d >> { n226, n287, n419, n866, n689, n186 }; + assign n1222 = 64'h0000008000800080 >> { n185, n1220, n683, n1221, n864, n867 }; + assign n1223 = 64'h5151515151515951 >> { n137, n153, n576, n147, n575, n185 }; + assign n180 = 16'h8000 >> { n88, n161, n146, n120 }; + assign n1224 = 64'h0000000000000080 >> { n206, n571, n874, n726, n871, n452 }; + assign n1225 = 64'h8008880800080808 >> { n118, n186, n1223, n185, n1224, n873 }; + assign n1226 = 64'h0808000800080008 >> { n118, n928, n185, n945, n944, n943 }; + assign n1227 = 64'h0000000000008000 >> { n642, n942, n921, n934, n1238, n1226 }; + assign o_35_ = 64'h7fff7fffffff7fff >> { n973, n149, n1376, n1385, n1360, n1227 }; + assign n1229 = 64'hbfb133b5bfbb33b7 >> { n157, i_15_, i_13_, i_12_, n96, i_14_ }; + assign n1230 = 64'h555555555555d555 >> { n153, n778, n1229, n896, n897, n149 }; + assign n1231 = 64'h00011111000f555f >> { n147, n149, n289, n552, n196, n185 }; + assign n1232 = 64'h0080008000808080 >> { n173, n882, n166, n881, n1351, n1234 }; + assign n1233 = 64'h0105010501051115 >> { n198, n135, n489, n654, n163, n885 }; + assign n181 = 4'h8 >> { n123, n182 }; + assign n1234 = 64'h0008080808080808 >> { n418, n149, n139, n469, n1233, n886 }; + assign n1235 = 64'h0004000544445555 >> { n196, n198, n150, n380, n638, n357 }; + assign n1236 = 64'h1111111111111151 >> { n235, n420, n762, n817, n135, n364 }; + assign n1237 = 64'h0001030300555757 >> { n149, n416, n179, n323, n551, n196 }; + assign n1238 = 16'h0888 >> { n236, n185, n1236, n1237 }; + assign n1239 = 64'h010f010f010f111f >> { n422, n424, n196, n185, n130, n129 }; + assign n1240 = 64'h000202020022aaaa >> { n185, n196, n290, n556, n79, n947 }; + assign n1241 = 64'h0105010501051115 >> { n179, n198, n337, n303, n163, n398 }; + assign n1242 = 64'h2000aa082002aaaa >> { n176, n126, i_14_, i_12_, i_13_, n958 }; + assign n1243 = 64'h2202020202020202 >> { n1242, n604, n804, n135, n841, n967 }; + assign n182 = 16'h0002 >> { i_9_, i_11_, i_10_, i_15_ }; + assign n1244 = 64'h0010101000551155 >> { n308, n163, n766, n373, n135, n770 }; + assign n1245 = 64'h0080008000808080 >> { n185, n196, n189, n1244, n969, n1195 }; + assign n1246 = 32'd2004844415 >> { n182, n123, n846, n133, n164 }; + assign n1247 = 64'h0000000000000002 >> { n214, n254, n365, n453, n659, n467 }; + assign n1248 = 32'd8421504 >> { n434, n149, n1247, n1246, n504 }; + assign n1249 = 64'h0008000a8888aaaa >> { n819, n205, n312, n183, n815, n814 }; + assign o_36_ = 32'd2147483647 >> { n1249, n1388, n1255, n1367, n1376 }; + assign n1251 = 64'h0111013305150537 >> { n433, n205, n162, n796, n174, n332 }; + assign n1252 = 64'h0000008000800080 >> { n489, n198, n666, n974, n977, n978 }; + assign n1253 = 64'h0001000100010101 >> { n174, n203, n440, n354, n170, n456 }; + assign n183 = 4'h8 >> { n161, n146 }; + assign n1254 = 64'h0008000800080808 >> { n138, n423, n132, n510, n1253, n1002 }; + assign n1255 = 64'h8000000000000000 >> { n1254, n1364, n994, n1003, n1005, n1009 }; + assign n1256 = 64'h0101010101010111 >> { n378, n417, n778, n132, n558, n242 }; + assign n1257 = 64'h2aaa2aaa2aaa3bbb >> { n186, n132, n418, n141, n174, n1256 }; + assign n1258 = 32'd128 >> { n988, n992, n990, n989, n993 }; + assign n1259 = 64'ha2a2a2a2a2a200a2 >> { n575, i_8_, n207, n816, n174, n1024 }; + assign n1260 = 64'h1111111111111151 >> { n380, n426, n565, n1023, n145, n1013 }; + assign n1261 = 64'h55555ddd5ddd5ddd >> { n161, n133, n103, n146, n265, n511 }; + assign n1262 = 64'h22220002ffff000f >> { n196, n773, n132, n987, n140, n464 }; + assign n1263 = 64'h0888088808888888 >> { n134, n161, n327, n96, n1262, n1261 }; + assign n76 = 32'd707439146 >> { n94, n95, n93, n89, n77 }; + assign n184 = 64'h0000077707770777 >> { n186, n156, n125, n187, n138, n185 }; + assign n1264 = 64'h0001000100010101 >> { n677, n755, n186, n651, n355, n455 }; + assign n1265 = 64'h0000000000008000 >> { n507, n1041, n1031, n1032, n1030, n1042 }; + assign n1266 = 64'h3f373f3715153f37 >> { n593, n198, n465, n756, n135, n157 }; + assign n1267 = 32'd286347537 >> { n478, n494, n576, n185, n668 }; + assign n1268 = 16'h0888 >> { n478, n135, n1267, n1266 }; + assign n1269 = 64'h07070f070f070f07 >> { i_15_, n276, i_9_, n778, i_10_, i_11_ }; + assign n1270 = 64'h5555555555555557 >> { n287, n308, n419, n506, n866, n132 }; + assign n1271 = 64'h0000000000000008 >> { n797, n985, n1039, n1040, n811, n1270 }; + assign n1272 = 64'h8080808000808080 >> { n268, n141, n135, n1271, n1036, n1222 }; + assign n1273 = 64'h8808080888000800 >> { n591, n265, n217, n290, n863, n1053 }; + assign n185 = 4'h8 >> { n133, n164 }; + assign n1274 = 64'h0000000080000000 >> { n842, n922, n1277, n1047, n1051, n1052 }; + assign n1275 = 64'h8000800000008000 >> { n363, n129, n1273, n1274, n1043, n1279 }; + assign n1276 = 64'h0008000accccffff >> { n245, o_18_, n85, n671, n831, n597 }; + assign n1277 = 32'd572662434 >> { n85, n290, n250, n132, n1276 }; + assign n1278 = 64'h0001010100555555 >> { n132, n196, n611, n556, n424, n704 }; + assign n1279 = 64'h0000800080008000 >> { n422, n186, n321, n1278, n1049, n1050 }; + assign n1280 = 64'hbefaeebeaaaaaaaa >> { n162, i_12_, i_13_, i_15_, i_14_, n183 }; + assign n1281 = 64'h0088008088888080 >> { n1280, n532, n498, n807, n1062, n1232 }; + assign o_38_ = 32'd2147483647 >> { n1281, n1285, n1066, n1255, n1370 }; + assign n1283 = 64'h0002002202020222 >> { n762, n185, n135, n420, n942, n1061 }; + assign n186 = 4'h8 >> { n161, n133 }; + assign n1284 = 64'h1115010501050105 >> { n567, n817, n179, n185, n416, n642 }; + assign n1285 = 64'h8000000000000000 >> { n1283, n1284, n1288, n1290, n1292, n1059 }; + assign n1286 = 64'h153f1515557f5555 >> { n163, n494, n416, i_14_, n121, n196 }; + assign n1287 = 64'h0002002202020222 >> { n135, n122, n119, n185, n396, n1054 }; + assign n1288 = 16'h0008 >> { n211, n364, n1286, n1287 }; + assign n1289 = 64'h80808080aa808080 >> { i_7_, n146, n551, n498, n327, i_8_ }; + assign n1290 = 64'h0080008880808888 >> { n1289, n173, i_6_, n938, n1055, n1056 }; + assign n1291 = 64'h000a0008ffffcccc >> { n185, n377, n323, n236, n932, n807 }; + assign n1292 = 64'h0008000808080008 >> { n235, n817, n135, n1057, n1291, n1058 }; + assign n1293 = 64'h0101010111010101 >> { n246, n888, n1081, n203, n292, n316 }; + assign n187 = 8'h08 >> { i_6_, n160, i_8_ }; + assign n1294 = 64'h0000000080000000 >> { n317, n887, n936, n1078, n1079, n1080 }; + assign o_39_ = 32'd4294440951 >> { n247, n179, n291, n1293, n1294 }; + assign n1296 = 64'h0080008080800080 >> { n229, n1007, n145, n427, n1033, n1153 }; + assign n1297 = 64'h8080008000800080 >> { n234, n822, n149, n786, n1086, n1087 }; + assign n1298 = 32'd32768 >> { n1085, n1296, n1297, n142, n1088 }; + assign o_44_ = 64'hfff7fff7fff7f7f7 >> { n105, n103, n146, o_16_, n1025, n1298 }; + assign n1300 = 64'h5551555155515559 >> { n159, n198, n145, n186, n217, n175 }; + assign n1301 = 64'h0000000000000080 >> { n199, n215, n218, n192, n1124, n1127 }; + assign n1302 = 64'h8000008080800080 >> { n130, n1300, n175, n1301, n200, n1305 }; + assign n1303 = 64'hffffaaa8aaa8aaa8 >> { n141, n161, n139, n126, n88, n136 }; + assign n188 = 64'h0000077707770777 >> { n129, n135, n125, n185, n132, n189 }; + assign n1304 = 64'h0080808080808080 >> { n133, n120, n1303, n188, n190, n1121 }; + assign n1305 = 64'h8000000000000000 >> { n1304, n117, n142, n184, n1117, n1118 }; + assign n1306 = 64'h0111055503130757 >> { n242, n174, n183, n235, n228, n162 }; + assign n1307 = 64'h0008080800aaffff >> { n135, n185, n226, n225, n230, n227 }; + assign n1308 = 64'h0000000080000000 >> { n238, n224, n239, n243, n1131, n1306 }; + assign n1309 = 64'h0000000080000000 >> { n220, n1307, n1308, n233, n248, n1133 }; + assign n1310 = 64'hf5ff757775777577 >> { n372, n300, n69, n370, n88, n123 }; + assign n1311 = 32'd32768 >> { n342, n318, n1310, n343, n1315 }; + assign n1312 = 64'h0001010100ff55ff >> { n320, n205, n350, n149, n174, n145 }; + assign n1313 = 64'h5777777777777777 >> { n80, n123, n155, i_8_, n1139, n133 }; + assign n189 = 4'h8 >> { n69, n120 }; + assign n1314 = 64'h0000000000000001 >> { n329, n330, n338, n339, n340, n341 }; + assign n1315 = 64'h8000800080000000 >> { n328, n279, n1313, n1314, n331, n335 }; + assign n1316 = 64'h7f7f7f7f557f7f7f >> { n268, n160, n103, n196, i_14_, n121 }; + assign n1317 = 64'h0000000000000001 >> { n351, n353, n354, n355, n356, n357 }; + assign n1318 = 32'd8421504 >> { n313, n281, n1316, n1317, n1142 }; + assign n1319 = 64'h0037373700151515 >> { n377, n149, n380, n281, n132, n376 }; + assign n1320 = 64'h0001000100010101 >> { n186, n203, n379, n163, n185, n149 }; + assign n1321 = 64'h0055575700010303 >> { n1320, n282, n154, n378, n379, n196 }; + assign n1322 = 8'h80 >> { n1321, n1147, n1319 }; + assign n1323 = 64'hf000f70070007700 >> { n373, n501, n462, n532, n86, n83 }; + assign n190 = 64'h0aaa0bbb0bbb0bbb >> { n140, n174, n125, n186, n173, n191 }; + assign n1324 = 64'h8000000080008000 >> { n420, n302, n1154, n1161, n1168, n1171 }; + assign o_7_ = 16'h7fff >> { n1323, n1324, n1155, n1302 }; + assign n1326 = 64'h0111055503130757 >> { n154, n424, n417, n162, n174, n436 }; + assign n1327 = 64'h0000000000008000 >> { n425, n445, n432, n444, n427, n447 }; + assign n1328 = 64'h0000800080008000 >> { n437, n240, n1327, n1326, n1157, n1332 }; + assign n1329 = 64'hffffeac8eac8eac8 >> { n157, n161, n164, n83, n136, n148 }; + assign n1330 = 64'h44444ccc4ccc4ccc >> { n418, n1329, n419, n136, n443, n133 }; + assign n1331 = 64'h000101010055ffff >> { n162, n183, n437, n426, n416, n420 }; + assign n1332 = 64'h0000000000008000 >> { n438, n442, n1330, n439, n441, n1331 }; + assign n1333 = 64'h0007050700371537 >> { n185, n550, n173, n553, n149, n554 }; + assign n191 = 64'hdfdfdfdfdfdf57df >> { i_9_, i_11_, n123, n120, i_15_, i_10_ }; + assign n1334 = 64'h0080008000808080 >> { n94, n552, n174, n1333, n1172, n1173 }; + assign n1335 = 64'h01010155030303ff >> { n87, n174, n196, n281, n289, n135 }; + assign n1336 = 64'h8000000000000000 >> { n392, n612, n616, n617, n625, n626 }; + assign n1337 = 32'd2147483648 >> { n1335, n1336, n618, n621, n1153 }; + assign n1338 = 64'h55557ff7fff77ff7 >> { n133, i_7_, i_8_, i_6_, n160, n654 }; + assign n1339 = 64'h0000000000000002 >> { n661, n665, n666, n667, n668, n1195 }; + assign n1340 = 64'h8000000000000000 >> { n1338, n627, n1339, n1190, n1193, n1198 }; + assign n1341 = 64'h1313131313135713 >> { n198, n336, n300, n556, n85, n183 }; + assign n1342 = 64'h0000000000008000 >> { n793, n799, n750, n767, n1203, n1204 }; + assign n1343 = 64'hc4ccc4cc4444c4cc >> { n544, n126, n69, n414, n1341, n68 }; + assign n192 = 64'h0808080808080888 >> { n197, n173, n135, n189, n195, n193 }; + assign n1344 = 64'h8000000000000000 >> { n1343, n533, n1202, n1207, n1211, n1342 }; + assign o_12_ = 16'h7fff >> { n1344, n718, n1146, n1214 }; + assign n1346 = 64'h80008080aa00ffff >> { n185, n186, n818, n817, n823, n809 }; + assign n1347 = 64'h0080000000800080 >> { n855, n95, n857, n1346, n856, n754 }; + assign n1348 = 64'h8080008000800080 >> { n514, n858, n207, n1347, n1218, n1219 }; + assign n1349 = 64'hc4c4c4c4c4c4d5c4 >> { n313, n135, n377, n898, n828, n163 }; + assign n1350 = 64'hdf5fdd1e96550000 >> { n187, n196, i_12_, i_15_, i_13_, i_14_ }; + assign n1351 = 64'h0000800080008000 >> { n166, n1350, n880, n883, n887, n1231 }; + assign n1352 = 16'h5777 >> { n98, n327, n882, n96 }; + assign n1353 = 64'h0001010100555555 >> { n135, n149, n150, n127, n246, n168 }; + assign n193 = 32'd89458551 >> { n194, n185, n175, n173, n181 }; + assign n1354 = 64'h02220aaa03230bab >> { n196, n755, n511, n149, n185, n816 }; + assign n1355 = 32'd8421504 >> { n512, n173, n892, n893, n1235 }; + assign n1356 = 64'h0001010100ffffff >> { n149, n196, n241, n231, n79, n556 }; + assign n1357 = 64'h0008000a8888aaaa >> { n163, n185, n592, n783, n806, n1241 }; + assign n1358 = 64'h0202020202022202 >> { n175, n435, n970, n198, n972, n971 }; + assign n1359 = 64'h0000000080000000 >> { n199, n618, n961, n968, n1245, n1248 }; + assign n1360 = 64'h0000000080000000 >> { n964, n192, n1359, n952, n1358, n1243 }; + assign n1361 = 64'h022222a28222aaaa >> { n141, n157, i_13_, i_12_, i_14_, n186 }; + assign n1362 = 64'h007f000f00770007 >> { n544, n1361, n985, n186, n120, n84 }; + assign n1363 = 64'h2202220222022222 >> { n222, n81, n265, n141, n860, n986 }; + assign n77 = 32'd352654613 >> { n93, n78, n89, n92, n91 }; + assign n194 = 4'h8 >> { n160, n136 }; + assign n1364 = 32'd2147516544 >> { n987, n898, n1363, n1257, n1258 }; + assign n1365 = 64'h0002020200aaaaaa >> { n132, n159, n468, n421, n247, n1264 }; + assign n1366 = 64'h0010001110105555 >> { n203, n205, n380, n638, n350, n425 }; + assign n1367 = 64'h8000000000000000 >> { n1365, n1366, n1014, n1259, n1260, n1263 }; + assign n1368 = 64'h222a222a020a222a >> { n593, n174, n126, n176, n245, n1265 }; + assign n1369 = 32'd71566847 >> { n163, n173, n778, n898, n756 }; + assign n1370 = 64'h8000000000000000 >> { n1368, n1369, n1028, n1033, n1035, n1272 }; + assign n1371 = 64'h0515151501111111 >> { n334, o_14_, i_8_, n303, n163, n365 }; + assign n1372 = 64'h0000000080000000 >> { n369, n1138, n1141, n1144, n1312, n1318 }; + assign n1373 = 64'h0000000080000000 >> { n364, n344, n1371, n366, n1372, n1311 }; + assign n195 = 32'd17764639 >> { n173, n125, n175, n149, n196 }; + assign n1374 = 64'h0010001110105555 >> { n135, n196, n796, n899, n755, n795 }; + assign n1375 = 64'h0080008000808080 >> { n187, n173, n756, n879, n1230, n1349 }; + assign n1376 = 32'd2147483648 >> { n1374, n1375, n900, n1232, n1382 }; + assign n1377 = 64'h0111111111111111 >> { n128, n160, n81, n98, n782, n564 }; + assign n1378 = 64'h0055015501550155 >> { n418, n128, n196, n247, n550, n430 }; + assign n1379 = 64'h0000000000008000 >> { n894, n895, n1377, n1378, n1352, n1353 }; + assign n1380 = 64'h1111000100010001 >> { n773, n816, n135, n187, n890, n891 }; + assign n1381 = 64'h1313131313131357 >> { n247, n379, n421, n198, n135, n468 }; + assign n1382 = 64'h8000000000000000 >> { n1380, n1381, n889, n1354, n1355, n1379 }; + assign n1383 = 64'h1313131313131357 >> { n337, n592, n783, n187, n135, n470 }; + assign n196 = 4'h8 >> { n98, n160 }; + assign n1384 = 64'h0000000000000008 >> { n587, n857, n946, n951, n1239, n1356 }; + assign n1385 = 64'h0000000080000000 >> { n291, n1383, n1384, n948, n1240, n1357 }; + assign n1386 = 64'h0001010100ff55ff >> { n159, n87, n186, n332, n490, n630 }; + assign n1387 = 64'h8000000000000000 >> { n835, n975, n979, n983, n1251, n1252 }; + assign n1388 = 32'd2147516544 >> { n527, n265, n1386, n1387, n1362 }; + assign n197 = 4'h8 >> { n146, n164 }; + assign n198 = 4'h8 >> { n105, n160 }; + assign n199 = 16'h8000 >> { n98, n146, n123, n182 }; + assign n200 = 64'h0002020200aaaaaa >> { n127, n189, n194, n154, n163, n201 }; + assign n201 = 64'h0002020200aaaaaa >> { n156, o_18_, n137, n163, n205, n202 }; + assign n202 = 64'h0000077707770777 >> { n125, n162, n119, n203, n159, n138 }; + assign n203 = 4'h8 >> { n93, n133 }; + assign n78 = 16'h0002 >> { n79, n85, n87, n82 }; + assign o_18_ = 4'h8 >> { n155, n160 }; + assign n205 = 4'h8 >> { n103, n160 }; + assign n206 = 64'haaaaaaaaaaaaaaa8 >> { n153, n127, n129, n138, n119, n186 }; + assign n207 = 4'h8 >> { n102, n133 }; + assign n208 = 64'h0001010100ffffff >> { n196, n119, n174, n189, n122, n147 }; + assign n209 = 32'd1936946039 >> { n153, n138, i_8_, o_18_, n150 }; + assign n210 = 16'h8000 >> { n93, n128, n160, n120 }; + assign n211 = 16'h8000 >> { n98, n160, n123, n157 }; + assign n212 = 16'h8000 >> { n98, n84, n160, n123 }; + assign n213 = 32'd2139062271 >> { n124, n148, n123, n93, n160 }; + assign n79 = 4'h8 >> { n80, n81 }; + assign n214 = 16'h8000 >> { n98, n160, n123, n182 }; + assign n215 = 32'd2290649256 >> { n216, i_6_, n160, n186, n181 }; + assign n216 = 4'h1 >> { i_7_, i_8_ }; + assign n217 = 8'h57 >> { n160, n146, n103 }; + assign n218 = 32'd2863311528 >> { n154, o_14_, n173, n203, n122 }; + assign o_14_ = 4'h8 >> { n111, n160 }; + assign n220 = 32'd4238911656 >> { n223, n69, n173, n197, n221 }; + assign n221 = 4'h8 >> { n182, n222 }; + assign n222 = 8'h02 >> { i_13_, i_14_, i_12_ }; + assign n223 = 8'h08 >> { i_12_, i_13_, i_14_ }; + assign n80 = 16'h0002 >> { i_9_, i_11_, i_15_, i_10_ }; + assign n224 = 64'h0000077707770777 >> { n194, n221, n225, n196, n149, n226 }; + assign n225 = 4'h8 >> { n126, n223 }; + assign n226 = 4'h8 >> { n176, n222 }; + assign n227 = 4'h1 >> { n228, n229 }; + assign n228 = 4'h8 >> { n139, n223 }; + assign n229 = 4'h8 >> { n148, n222 }; + assign n230 = 4'h1 >> { n231, n232 }; + assign n231 = 4'h8 >> { n83, n222 }; + assign n232 = 4'h8 >> { n88, n223 }; + assign n233 = 64'h0004040400555555 >> { n149, n145, n229, n231, n234, n237 }; + assign n81 = 8'h02 >> { i_12_, i_14_, i_13_ }; + assign n234 = 4'h1 >> { n235, n236 }; + assign n235 = 4'h8 >> { n124, n222 }; + assign n236 = 4'h8 >> { n121, n223 }; + assign n237 = 16'ha888 >> { n84, n222, n232, n154 }; + assign n238 = 8'h80 >> { n132, n69, n223 }; + assign n239 = 16'h777f >> { n240, n183, n84, n222 }; + assign n240 = 4'h8 >> { n92, n133 }; + assign n241 = 4'h8 >> { n80, n223 }; + assign n242 = 4'h8 >> { n157, n222 }; + assign n243 = 16'h0777 >> { n186, n244, n162, n236 }; + assign n82 = 8'h57 >> { n83, n84, n68 }; + assign n244 = 4'h8 >> { n141, n223 }; + assign n245 = 4'h8 >> { n111, n146 }; + assign n246 = 4'h8 >> { n128, n223 }; + assign n247 = 4'h8 >> { n151, n222 }; + assign n248 = 64'h020a020a020a222a >> { n228, n241, n162, n173, n244, n249 }; + assign n249 = 32'd320017239 >> { n135, n145, n225, n226, n186 }; + assign n250 = 16'h0777 >> { n222, n83, n80, n223 }; + assign n251 = 64'h0105010501051115 >> { n228, n236, n135, n132, n235, n252 }; + assign n252 = 16'h8000 >> { n133, n134, n176, n222 }; + assign n253 = 64'h0001ff110a0bff1b >> { n232, n135, n236, n247, n254, n132 }; + assign n83 = 16'h0008 >> { i_9_, i_11_, i_10_, i_15_ }; + assign n254 = 16'h8000 >> { n69, n133, n136, n223 }; + assign n255 = 64'hfefefefefefefe00 >> { n242, n244, n247, n149, n163, n196 }; + assign n256 = 64'h777f777f5555777f >> { n257, n84, n196, n145, n83, n222 }; + assign n257 = 8'h57 >> { n146, n160, n134 }; + assign n258 = 64'h00011111000fffff >> { n185, n225, n198, n132, n244, n246 }; + assign n259 = 64'h0105010511150105 >> { n242, n227, n185, n186, n221, n260 }; + assign n260 = 4'h2 >> { n261, n207 }; + assign n261 = 64'hfc42feeafd57ffff >> { n223, n222, i_11_, i_9_, i_10_, i_15_ }; + assign n262 = 64'h8000000000000000 >> { n263, n273, n284, n293, n305, n310 }; + assign n263 = 64'haaaa00aa02020002 >> { n272, n270, n130, n242, n247, n264 }; + assign o_2_ = 16'h0008 >> { i_6_, i_8_, n67, n70 }; + assign n84 = 16'h0008 >> { i_11_, i_10_, i_9_, i_15_ }; + assign n264 = 64'h0101000155550055 >> { n156, n265, n269, n198, n159, n266 }; + assign n265 = 4'h1 >> { n145, n174 }; + assign n266 = 4'h2 >> { n267, n174 }; + assign n267 = 16'h0ddd >> { n222, n83, n268, n80 }; + assign n268 = 8'h5d >> { i_13_, i_12_, i_14_ }; + assign n269 = 64'h0000000000000080 >> { i_11_, i_15_, i_12_, i_9_, i_10_, i_14_ }; + assign n270 = 16'h0001 >> { n183, n135, o_17_, n198 }; + assign o_17_ = 4'h8 >> { n102, n160 }; + assign n272 = 32'd3908954367 >> { n146, n160, i_7_, i_8_, i_6_ }; + assign n273 = 64'h0080008080800080 >> { o_18_, n279, n226, n277, n274, n280 }; + assign n85 = 4'h8 >> { n80, n86 }; + assign n274 = 32'd2728567466 >> { n150, n147, i_6_, n160, n275 }; + assign n275 = 32'd125269879 >> { n80, n276, n154, n179, n119 }; + assign n276 = 4'h2 >> { i_12_, i_14_ }; + assign n277 = 64'h7575757500757575 >> { n278, n276, n141, n279, n183, n231 }; + assign n278 = 16'h1357 >> { n146, n161, n93, n160 }; + assign n279 = 16'hbbab >> { i_7_, n146, n160, i_6_ }; + assign n280 = 64'h0777077700000777 >> { n283, n281, n129, n145, n159, n282 }; + assign n281 = 4'h8 >> { n88, n222 }; + assign n282 = 4'h8 >> { n86, n139 }; + assign n283 = 64'h2627aeafaeafaeaf >> { n133, i_8_, n146, n160, i_7_, i_6_ }; + assign n86 = 8'h02 >> { i_12_, i_13_, i_14_ }; + assign n284 = 64'h0000000200020002 >> { n246, n203, n291, n288, n292, n285 }; + assign n285 = 64'h0002020200aaaaaa >> { n122, n175, n163, n183, o_17_, n286 }; + assign n286 = 32'd5723991 >> { n242, n135, n287, n85, n162 }; + assign n287 = 4'h8 >> { n276, n126 }; + assign n288 = 16'h5554 >> { n229, n289, n290, n279 }; + assign n289 = 4'h8 >> { n139, n222 }; + assign n290 = 4'h8 >> { n80, n222 }; + assign n291 = 16'haaa2 >> { n130, n290, n267, n179 }; + assign n292 = 64'h8080800000800000 >> { n123, n120, i_15_, n96, n133, n93 }; + assign n293 = 16'h2202 >> { n304, n303, n294, n298 }; + assign n87 = 4'h8 >> { n88, n86 }; + assign n294 = 32'd2863311402 >> { n149, n135, n296, n295, n297 }; + assign n295 = 16'h0001 >> { n159, n173, n207, n183 }; + assign n296 = 64'hcccdeeefeeefeeef >> { n133, i_6_, n146, n160, i_8_, i_7_ }; + assign n297 = 4'h8 >> { n121, n123 }; + assign n298 = 32'd1162149957 >> { n300, n301, n235, n302, n299 }; + assign n299 = 16'haaa2 >> { n135, n197, n296, n181 }; + assign n300 = 32'd3125853179 >> { n160, i_6_, i_8_, n146, i_7_ }; + assign n301 = 4'h2 >> { n268, n69 }; + assign n302 = 32'd2290675679 >> { n160, i_8_, n146, i_7_, i_6_ }; + assign n303 = 4'h8 >> { n80, n123 }; + assign n88 = 16'h0002 >> { i_11_, i_10_, i_15_, i_9_ }; + assign n304 = 64'h8084a8acc0d5e8ff >> { n160, n133, n146, i_6_, i_8_, i_7_ }; + assign n305 = 32'd134776840 >> { o_17_, n296, n309, n112, n306 }; + assign n306 = 32'd286331217 >> { n171, n198, n300, n221, n307 }; + assign n307 = 16'haaa2 >> { n198, n207, n300, n308 }; + assign n308 = 4'h8 >> { n123, n126 }; + assign n309 = 4'h8 >> { n126, n222 }; + assign n310 = 64'h0000000100010001 >> { n247, n179, n316, n311, n315, n317 }; + assign n311 = 64'haaaaaaaaaaaaaaa8 >> { n183, n135, n186, n312, n313, n314 }; + assign n312 = 4'h8 >> { n160, n134 }; + assign n313 = 4'h8 >> { n146, n136 }; + assign n89 = 16'h0002 >> { i_3_, i_5_, i_4_, n90 }; + assign n314 = 4'h8 >> { n88, n123 }; + assign n315 = 32'd2290124936 >> { n279, n313, o_18_, n84, n222 }; + assign n316 = 16'haaa2 >> { n130, n290, n267, n203 }; + assign n317 = 32'd2155905024 >> { n222, n86, n128, n133, n98 }; + assign n318 = 64'h0000000800080008 >> { n324, n186, n322, n319, n321, n325 }; + assign n319 = 64'h2a822a0002820000 >> { n133, n160, i_7_, i_6_, i_8_, n320 }; + assign n320 = 4'h8 >> { n139, n123 }; + assign n321 = 16'h0777 >> { n203, n303, n162, n241 }; + assign n322 = 8'ha8 >> { n323, n122, n135 }; + assign n323 = 4'h8 >> { n121, n222 }; + assign n90 = 8'h02 >> { i_0_, i_2_, i_1_ }; + assign n324 = 4'h8 >> { n123, n141 }; + assign n325 = 32'd2678038527 >> { n96, n326, n327, i_7_, i_6_ }; + assign n326 = 8'h02 >> { i_9_, i_11_, i_10_ }; + assign n327 = 64'h0000000000000001 >> { i_1_, i_0_, i_3_, i_5_, i_4_, i_2_ }; + assign n328 = 8'h57 >> { n121, n128, n222 }; + assign n329 = 64'h8888008000800080 >> { n139, n86, n268, n88, n111, n146 }; + assign n330 = 16'h8000 >> { n155, n128, n123, n133 }; + assign n331 = 64'h0777077700000777 >> { n334, n198, n332, n205, n173, n333 }; + assign n332 = 4'h2 >> { n268, n88 }; + assign n333 = 4'h2 >> { n268, n121 }; + assign n91 = 8'h08 >> { i_4_, n71, n72 }; + assign n334 = 8'hab >> { n139, n121, n268 }; + assign n335 = 64'h0001010100ffffff >> { n163, n138, n336, n337, n297, n320 }; + assign n336 = 4'h8 >> { n155, n133 }; + assign n337 = 4'h2 >> { n268, n80 }; + assign n338 = 32'd134744064 >> { n134, n105, n268, n88, n160 }; + assign n339 = 64'h2222200020002000 >> { n161, n146, n105, n160, n268, n80 }; + assign n340 = 64'h8880808088008000 >> { n120, n88, n123, n128, n133, n164 }; + assign n341 = 64'h8880808088008000 >> { n222, n96, n123, n141, n134, n133 }; + assign n342 = 16'h2220 >> { n126, n141, n268, n205 }; + assign n343 = 64'h0001010100ffffff >> { n173, n132, n289, n156, n150, n147 }; + assign n92 = 4'h8 >> { i_7_, i_6_ }; + assign n344 = 16'h0222 >> { n314, n132, n346, n345 }; + assign n345 = 64'h0f7f7f7f07777777 >> { n268, n132, n126, n123, n141, n135 }; + assign n346 = 16'h8000 >> { n139, n123, n133, n136 }; + assign n347 = 8'h5d >> { n123, n268, n69 }; + assign n348 = 64'h0001010100555555 >> { n196, n205, n337, n138, n140, n349 }; + assign n349 = 16'h8000 >> { n105, n160, n139, n123 }; + assign n350 = 4'h8 >> { n128, n123 }; + assign n351 = 16'h8000 >> { n88, n146, n134, i_14_ }; + assign n352 = 16'h8000 >> { n128, n160, n161, i_14_ }; + assign n353 = 16'h0080 >> { n268, n160, n141, n105 }; + assign n93 = 8'h02 >> { i_7_, i_8_, i_6_ }; + assign n354 = 16'h0080 >> { n268, n160, n139, n103 }; + assign n355 = 16'h0080 >> { n268, n103, n160, n128 }; + assign n356 = 16'h8000 >> { n92, n128, n133, n222 }; + assign n357 = 16'h0080 >> { n268, n105, n160, n128 }; + assign n358 = 4'h8 >> { n69, n222 }; + assign n359 = 16'h4454 >> { n268, n126, n360, n278 }; + assign n360 = 4'h8 >> { n276, n121 }; + assign n361 = 4'h8 >> { n141, n222 }; + assign n362 = 64'haaaaaaaaaaaaaaa2 >> { n135, o_18_, n187, n149, n363, n350 }; + assign n363 = 16'h0777 >> { n161, n133, n103, n146 }; + assign n67 = 4'h8 >> { n68, n69 }; + assign n94 = 4'h8 >> { n88, n81 }; + assign n364 = 4'h8 >> { n198, n297 }; + assign n365 = 16'h0080 >> { n268, n105, n160, n69 }; + assign n366 = 16'h22a2 >> { n183, n279, n153, n367 }; + assign n367 = 16'h0777 >> { n196, n127, n368, n301 }; + assign n368 = 4'h8 >> { n146, n134 }; + assign n369 = 16'ha888 >> { n337, n159, n332, o_17_ }; + assign n370 = 16'h0002 >> { n368, n194, n197, n371 }; + assign n371 = 32'd572981767 >> { i_6_, n146, n160, n133, i_7_ }; + assign n372 = 4'h2 >> { n198, n373 }; + assign n373 = 16'h0777 >> { n105, n146, n98, n160 }; + assign n95 = 32'd4294966743 >> { i_12_, i_15_, i_13_, i_14_, n96 }; + assign n374 = 32'd16843025 >> { n216, n161, n160, n145, n185 }; + assign n375 = 4'h8 >> { n69, n86 }; + assign n376 = 4'h8 >> { n86, n126 }; + assign n377 = 8'h57 >> { n160, n146, n105 }; + assign n378 = 4'h8 >> { n86, n141 }; + assign n379 = 4'h8 >> { n86, n128 }; + assign n380 = 4'h8 >> { n128, n222 }; + assign n381 = 16'haaa8 >> { n309, n289, n290, n135 }; + assign n382 = 64'h0000077707770777 >> { n145, n323, n87, o_18_, n85, n173 }; + assign n383 = 64'h0002002202020222 >> { n376, n185, n196, n309, n384, n385 }; + assign n96 = 8'h08 >> { i_11_, i_9_, i_10_ }; + assign n384 = 64'h8808880880008800 >> { n146, i_7_, n160, i_6_, n358, i_8_ }; + assign n385 = 32'd1381653 >> { n149, n309, n358, n313, n386 }; + assign n386 = 32'd2155905024 >> { n164, n105, n69, n146, n86 }; + assign n387 = 32'd34218538 >> { n185, n85, n376, n135, n388 }; + assign n388 = 32'd5723991 >> { n309, n186, n378, n389, n162 }; + assign n389 = 4'h8 >> { n86, n121 }; + assign n390 = 32'd134742024 >> { n377, n309, n393, n392, n391 }; + assign n391 = 16'h0777 >> { n323, n183, n174, n282 }; + assign n392 = 8'h57 >> { n323, n361, n174 }; + assign n393 = 32'd2155905024 >> { n146, n160, n80, n93, n222 }; + assign n97 = 8'h57 >> { n88, n80, n68 }; + assign n394 = 4'h8 >> { n135, n282 }; + assign n395 = 32'd65793 >> { n281, n368, n396, n397, n398 }; + assign n396 = 4'h8 >> { n196, n323 }; + assign n397 = 4'h8 >> { n174, n380 }; + assign n398 = 16'h8000 >> { n98, n80, n86, n160 }; + assign n399 = 64'h00011111000fffff >> { n361, n378, n186, n173, n196, n185 }; + assign n400 = 8'h57 >> { n88, n121, n86 }; + assign n401 = 16'h8000 >> { n86, n121, n133, n136 }; + assign n402 = 32'd131586 >> { n173, n379, n404, n405, n403 }; + assign n403 = 64'h0000077707770777 >> { n196, n380, n361, n149, n368, n358 }; + assign n98 = 8'h08 >> { i_7_, i_6_, i_8_ }; + assign n404 = 16'h8000 >> { n98, n160, n139, n222 }; + assign n405 = 16'h8000 >> { n86, n128, n103, n146 }; + assign n406 = 64'h0015151500373737 >> { n196, n203, n380, n289, n174, n281 }; + assign n407 = 64'h8888800080008000 >> { n161, n146, n160, n134, n88, n222 }; + assign n408 = 32'd2763306 >> { n282, n185, n87, n135, n1153 }; + assign n409 = 8'ha8 >> { n281, n87, n154 }; + assign n410 = 16'h2022 >> { n186, n412, n411, n413 }; + assign n411 = 32'd2863311402 >> { n85, n290, n400, n328, n207 }; + assign n412 = 8'h01 >> { n361, n282, n358 }; + assign n413 = 64'h010f010f010f111f >> { n358, n375, n186, n185, n289, n281 }; + assign o_11_ = 32'd2400161679 >> { n97, n67, n100, n89, n105 }; + assign n414 = 8'h02 >> { n171, n194, n415 }; + assign n415 = 4'h2 >> { n197, n371 }; + assign n416 = 4'h8 >> { n124, n223 }; + assign n417 = 4'h8 >> { n157, n418 }; + assign n418 = 8'h08 >> { i_14_, i_13_, i_12_ }; + assign n419 = 4'h8 >> { n176, n418 }; + assign n420 = 4'h8 >> { n124, n418 }; + assign n421 = 4'h8 >> { n151, n418 }; + assign n422 = 4'h8 >> { n83, n418 }; + assign n423 = 4'h8 >> { n148, n418 }; + assign n100 = 64'h0111011111110111 >> { n94, n95, n103, n89, n104, n101 }; + assign n424 = 4'h8 >> { n83, n223 }; + assign n425 = 4'h8 >> { n174, n426 }; + assign n426 = 4'h8 >> { n151, n223 }; + assign n427 = 64'h2000202022002222 >> { n145, n149, n429, n428, n430, n431 }; + assign n428 = 32'd353703231 >> { n148, n151, n84, n418, n223 }; + assign n429 = 32'd17895263 >> { n418, n83, n223, n84, n124 }; + assign n430 = 16'h8000 >> { n98, n151, n146, n223 }; + assign n431 = 64'h7f7f7fff7fff7fff >> { n182, i_8_, n84, n155, n223, n146 }; + assign n432 = 64'h0111055503330777 >> { n196, n434, n174, n435, n171, n433 }; + assign n433 = 4'h8 >> { n84, n223 }; + assign n101 = 16'h88a8 >> { n78, n103, n102, n89 }; + assign n434 = 4'h8 >> { n182, n223 }; + assign n435 = 4'h8 >> { n176, n223 }; + assign n436 = 4'h8 >> { n157, n223 }; + assign n437 = 4'h8 >> { n84, n418 }; + assign n438 = 16'haaa8 >> { n421, n417, n424, n173 }; + assign n439 = 64'h000101010055ffff >> { n185, n186, n436, n440, n435, n419 }; + assign n440 = 4'h8 >> { n148, n223 }; + assign n441 = 64'h0111055503130757 >> { n440, n312, n196, n416, n433, n174 }; + assign n442 = 16'h8000 >> { n98, n83, n160, n223 }; + assign n443 = 64'h7f7f7fffff7fffff >> { n124, n148, i_8_, n155, n223, n133 }; + assign n102 = 4'h2 >> { i_6_, i_7_ }; + assign n444 = 32'd320017239 >> { n179, n149, n421, n440, n162 }; + assign n445 = 16'haaa8 >> { n173, n194, n197, n446 }; + assign n446 = 4'h8 >> { n182, n418 }; + assign n447 = 64'h0001010100ff11ff >> { n434, n149, n435, n194, n173, n196 }; + assign n448 = 64'h0202020202020222 >> { n196, n149, n163, n417, n451, n449 }; + assign n449 = 32'd353697813 >> { n257, n437, n203, n420, n450 }; + assign n450 = 32'd2290649256 >> { n216, i_6_, n160, n186, n434 }; + assign n451 = 16'haaa2 >> { n186, n145, n217, n424 }; + assign n452 = 16'h222a >> { n433, n446, n207, n1159 }; + assign n453 = 32'd2155905024 >> { n418, n223, n182, n133, n164 }; + assign n103 = 8'h01 >> { i_7_, i_6_, i_8_ }; + assign n454 = 32'd2139062271 >> { n83, n84, n133, n418, n102 }; + assign n455 = 16'h8000 >> { n151, n161, n133, n223 }; + assign n456 = 16'h8000 >> { n161, n148, n133, n223 }; + assign n457 = 64'h0002000200020202 >> { n163, n205, n436, n459, n458, n460 }; + assign n458 = 32'd2863311528 >> { o_14_, n145, n173, n203, n416 }; + assign n459 = 32'd2863311528 >> { n196, n186, n149, n163, n421 }; + assign n460 = 64'h00011111000fffff >> { n185, n446, n240, n196, n421, n417 }; + assign n461 = 64'haaaaaaaaaaaaaaa2 >> { n198, n159, n145, n186, n217, n435 }; + assign n462 = 64'h0080008000800000 >> { n480, n296, n472, n476, n1163, n474 }; + assign n463 = 16'h8000 >> { n133, n157, n136, i_14_ }; + assign n68 = 8'h01 >> { i_12_, i_13_, i_14_ }; + assign n104 = 16'h0002 >> { i_3_, i_5_, i_4_, n72 }; + assign n464 = 4'hd >> { n465, n157 }; + assign n465 = 8'hd5 >> { i_13_, i_12_, i_14_ }; + assign n466 = 32'd1280068701 >> { n84, n148, n120, n465, n176 }; + assign n467 = 32'd4160223231 >> { n176, n182, n465, n133, n136 }; + assign n468 = 4'h2 >> { n465, n151 }; + assign n469 = 16'h8000 >> { n120, n148, n133, n136 }; + assign n470 = 4'h2 >> { n465, n83 }; + assign n471 = 4'h2 >> { n465, n124 }; + assign n472 = 16'h8880 >> { n179, n473, n120, n148 }; + assign n473 = 4'h2 >> { n279, i_8_ }; + assign n105 = 8'h02 >> { i_7_, i_6_, i_8_ }; + assign n474 = 32'd286331217 >> { o_18_, n313, n279, n437, n475 }; + assign n475 = 16'h5554 >> { n421, n129, n417, n272 }; + assign n476 = 64'h4000550040405540 >> { n196, n478, n479, n300, n377, n477 }; + assign n477 = 64'ha2a2a2a2a2a2a200 >> { n124, n84, n83, n183, n371, n120 }; + assign n478 = 4'h8 >> { n120, n157 }; + assign n479 = 64'h9050df7f90d0ffff >> { n120, n418, i_11_, i_15_, i_9_, i_10_ }; + assign n480 = 8'h57 >> { n123, n223, n182 }; + assign n481 = 64'h0000000000000002 >> { n482, n484, n485, n486, n487, n488 }; + assign n482 = 8'h54 >> { n154, n174, n483 }; + assign n483 = 16'h5557 >> { n157, n151, n148, n86 }; + assign o_4_ = 4'h7 >> { n107, n112 }; + assign n484 = 4'h8 >> { n187, n470 }; + assign n485 = 8'ha8 >> { n417, n140, n135 }; + assign n486 = 16'ha888 >> { n276, n151, n127, n196 }; + assign n487 = 8'ha8 >> { n205, n163, n119 }; + assign n488 = 64'h0001001101010111 >> { n489, n135, n163, n490, n491, n492 }; + assign n489 = 4'h2 >> { n465, n148 }; + assign n490 = 4'h2 >> { n465, n84 }; + assign n491 = 16'h0080 >> { n465, n160, n124, n102 }; + assign n492 = 16'h0080 >> { n465, n161, n146, n83 }; + assign n493 = 32'd1465319511 >> { n494, n196, n468, n489, n173 }; + assign n107 = 64'hff007f00f7007700 >> { n95, n97, n108, i_8_, n111, n109 }; + assign n494 = 16'h0777 >> { n141, n120, n276, n157 }; + assign n495 = 64'h777077707770fff0 >> { n312, n171, n464, n377, n84, n120 }; + assign n496 = 16'h0080 >> { n465, n160, n161, n83 }; + assign n497 = 32'd673720320 >> { n498, n166, i_7_, i_6_, n327 }; + assign n498 = 8'h02 >> { i_9_, i_10_, i_11_ }; + assign n499 = 32'd2863311528 >> { n140, n433, n153, n127, o_14_ }; + assign n500 = 64'h1101550513035707 >> { n163, n489, n464, n159, n205, n468 }; + assign n501 = 4'h8 >> { n86, n124 }; + assign n502 = 4'h8 >> { n86, n176 }; + assign n503 = 16'h222a >> { n153, n433, n245, n504 }; + assign n108 = 64'h0515051515150515 >> { n94, n78, n103, n109, n102, n110 }; + assign n504 = 64'h0001010100111111 >> { n149, n135, n506, n502, n505, n507 }; + assign n505 = 16'h0080 >> { n465, n164, n182, n146 }; + assign n506 = 4'h8 >> { n120, n176 }; + assign n507 = 16'h0080 >> { n465, n164, n176, n160 }; + assign n508 = 32'd16843025 >> { n163, o_14_, n138, n510, n509 }; + assign n509 = 16'ha888 >> { n120, n124, n130, n336 }; + assign n510 = 64'h8008800080000000 >> { i_15_, i_14_, i_12_, i_13_, n203, n166 }; + assign n511 = 4'h8 >> { n86, n151 }; + assign n512 = 4'h8 >> { n151, n120 }; + assign n513 = 32'd649012783 >> { i_8_, n146, n160, i_7_, i_6_ }; + assign n109 = 16'h0008 >> { i_3_, i_5_, n90, i_4_ }; + assign n514 = 64'h0055045504550455 >> { n151, n276, n185, n127, n494, n515 }; + assign n515 = 32'd2862785186 >> { n86, n182, n478, n516, n207 }; + assign n516 = 16'h5557 >> { n124, n84, n83, n86 }; + assign n517 = 32'd2829625344 >> { n176, n148, n86, n120, n207 }; + assign n518 = 64'h0004000544445555 >> { n489, n179, n198, n135, n520, n519 }; + assign n519 = 16'h8000 >> { n98, n160, n120, n157 }; + assign n520 = 32'd3757539327 >> { i_15_, i_12_, i_13_, i_14_, n498 }; + assign n521 = 64'h8080008080000000 >> { n120, n276, i_15_, n98, n166, n160 }; + assign n522 = 32'd65793 >> { n471, n183, n526, n523, n525 }; + assign n523 = 16'haaa8 >> { n524, n138, n423, n179 }; + assign n110 = 16'h0008 >> { i_3_, i_5_, n72, i_4_ }; + assign n524 = 4'h8 >> { n86, n148 }; + assign n525 = 16'haaa8 >> { n490, n127, n489, n159 }; + assign n526 = 16'h2220 >> { n146, n160, i_7_, n527 }; + assign n527 = 4'h8 >> { n84, n86 }; + assign n528 = 32'd2829625504 >> { n161, n216, n145, n160, n125 }; + assign n529 = 8'h2a >> { n278, n217, n502 }; + assign n530 = 8'ha8 >> { n531, n512, n240 }; + assign n531 = 16'h0008 >> { i_15_, i_14_, i_13_, i_12_ }; + assign n532 = 4'h2 >> { n149, n296 }; + assign n533 = 64'h0000000800080008 >> { n543, n197, n534, n535, n536, n539 }; + assign n111 = 4'h1 >> { i_7_, i_6_ }; + assign n534 = 64'h8a888a888a880a00 >> { n166, n498, n501, i_8_, n531, n336 }; + assign n535 = 64'h0088808808888888 >> { i_10_, i_8_, i_11_, i_9_, n207, n531 }; + assign n536 = 64'h0055115500010101 >> { n537, n312, n527, n194, n171, n538 }; + assign n537 = 16'h0777 >> { n182, n86, n69, n418 }; + assign n538 = 8'h80 >> { n531, n133, n164 }; + assign n539 = 64'h7707770700007707 >> { n257, n540, n541, n183, n186, n542 }; + assign n540 = 4'h8 >> { n88, n418 }; + assign n541 = 16'h5557 >> { n88, n80, n121, n418 }; + assign n542 = 4'h8 >> { n126, n418 }; + assign n543 = 4'h8 >> { n69, n418 }; + assign n112 = 32'd134776840 >> { n94, n78, n113, n115, n114 }; + assign n544 = 8'h08 >> { n132, n372, n300 }; + assign n545 = 32'd2290649096 >> { n196, n159, n532, n120, n148 }; + assign n546 = 32'd4008635918 >> { n198, n171, n300, n446, n189 }; + assign o_9_ = 64'h7fffffffffffffff >> { n1373, n548, n568, n577, n1188, n1328 }; + assign n548 = 8'h80 >> { n1334, n1176, n1179 }; + assign n549 = 4'h8 >> { n68, n84 }; + assign n550 = 4'h8 >> { n68, n151 }; + assign n551 = 4'h8 >> { n81, n121 }; + assign n552 = 4'h8 >> { n81, n139 }; + assign n553 = 4'h8 >> { n81, n141 }; + assign n113 = 4'h8 >> { n109, n93 }; + assign n554 = 4'h8 >> { n68, n148 }; + assign n555 = 64'h00011111000fffff >> { n368, n162, n550, n556, n94, n557 }; + assign n556 = 4'h8 >> { n68, n83 }; + assign n557 = 4'h8 >> { n69, n81 }; + assign n558 = 4'h8 >> { n68, n157 }; + assign n559 = 4'h8 >> { n68, n124 }; + assign n560 = 32'd1465319511 >> { n377, n561, n553, n554, o_18_ }; + assign n561 = 4'h8 >> { n81, n126 }; + assign n562 = 4'h8 >> { n68, n176 }; + assign n563 = 4'h8 >> { n68, n182 }; + assign n69 = 16'h0001 >> { i_9_, i_11_, i_10_, i_15_ }; + assign n114 = 32'd125269879 >> { n72, i_4_, n71, n92, n109 }; + assign n564 = 16'h8000 >> { n68, n151, n133, n136 }; + assign n565 = 4'h8 >> { n81, n128 }; + assign n566 = 4'h2 >> { n567, n183 }; + assign n567 = 16'h0777 >> { n121, n81, n68, n124 }; + assign n568 = 64'h8000808088008888 >> { n185, n207, n575, n576, n1124, n569 }; + assign n569 = 64'h0008000808080008 >> { n79, n570, n185, n571, n574, n573 }; + assign n570 = 8'h01 >> { n94, n557, n563 }; + assign n571 = 4'h2 >> { n572, n186 }; + assign n572 = 64'h8caeddff80aad5ff >> { i_10_, n81, n68, i_9_, i_11_, i_15_ }; + assign n573 = 64'h00011111000fffff >> { n186, n185, n556, n551, n558, n554 }; + assign n115 = 32'd4160181751 >> { n95, n93, n97, n98, n109 }; + assign n574 = 64'h5555555555555557 >> { n549, n552, n559, n565, n550, n185 }; + assign n575 = 8'h15 >> { n418, n151, n269 }; + assign n576 = 16'h0777 >> { n157, n418, n276, n141 }; + assign n577 = 64'h0000000000008000 >> { n307, n610, n1184, n609, n1309, n578 }; + assign n578 = 32'd8 >> { n294, n579, n598, n594, n580 }; + assign n579 = 64'h8888888888880888 >> { n135, n149, n295, n296, n124, n81 }; + assign n580 = 64'h8000000000000000 >> { n581, n582, n583, n584, n586, n590 }; + assign n581 = 32'd5723991 >> { n149, n552, n553, n554, n145 }; + assign n582 = 64'h00011111000fffff >> { n145, n149, n79, n556, n565, n552 }; + assign n583 = 32'd1465319511 >> { n567, n149, n94, n549, n154 }; + assign o_5_ = 32'd2147483647 >> { n1302, n1130, n262, n1373, n1146 }; + assign n584 = 64'h0002020200ffffff >> { n145, n149, n122, n323, n551, n585 }; + assign n585 = 8'h57 >> { n123, n223, n124 }; + assign n586 = 32'd16842753 >> { n588, n145, n587, n199, n589 }; + assign n587 = 64'h8080800000800000 >> { n418, n276, i_15_, n146, n326, n98 }; + assign n588 = 16'h0777 >> { n148, n418, n276, n139 }; + assign n589 = 16'h0080 >> { n268, n128, n146, n155 }; + assign n590 = 64'h00022222000fffff >> { n145, n149, n565, n380, n592, n591 }; + assign n591 = 8'h57 >> { n123, n223, n83 }; + assign n592 = 4'h2 >> { n593, n83 }; + assign n593 = 8'hae >> { i_12_, i_13_, i_14_ }; + assign n117 = 32'd572695074 >> { n138, n191, n118, n132, n131 }; + assign n594 = 32'd3132799488 >> { n597, n304, n296, o_17_, n595 }; + assign n595 = 8'h08 >> { n309, n480, n596 }; + assign n596 = 8'h57 >> { n80, n126, n81 }; + assign n597 = 16'h0777 >> { n83, n81, n80, n123 }; + assign n598 = 8'h54 >> { n599, n301, n300 }; + assign n599 = 4'h2 >> { n593, n182 }; + assign n600 = 32'd1465319511 >> { n585, n173, n435, n175, n145 }; + assign n601 = 64'h0001010100111111 >> { o_18_, o_17_, n562, n332, n292, n602 }; + assign n602 = 16'h8000 >> { n84, n133, n223, i_7_ }; + assign n603 = 32'd3623346135 >> { i_12_, i_13_, i_14_, i_15_, n96 }; + assign n118 = 4'h1 >> { n119, n122 }; + assign n604 = 32'd3758088183 >> { i_13_, i_15_, i_12_, i_14_, n605 }; + assign n605 = 8'h01 >> { i_9_, i_11_, i_10_ }; + assign n606 = 32'd134785544 >> { n593, n148, n268, n139, n159 }; + assign n607 = 32'd1431336816 >> { n198, n363, n608, n132, n287 }; + assign n608 = 16'h111f >> { n123, n223, n83, n176 }; + assign n609 = 64'h0004040400555555 >> { n186, n185, n221, n242, n227, n260 }; + assign n610 = 16'haaa2 >> { n198, n207, n300, n611 }; + assign n611 = 4'h8 >> { n81, n176 }; + assign n612 = 32'd33685506 >> { n613, n132, n614, n401, n615 }; + assign n613 = 64'hff69fffdff69ffff >> { n222, n86, i_15_, i_9_, i_11_, i_10_ }; + assign n119 = 4'h8 >> { n120, n121 }; + assign n614 = 16'h8000 >> { n121, n133, n134, n222 }; + assign n615 = 64'h7fff7fff7f7f7fff >> { i_8_, n139, n128, n92, n133, n86 }; + assign n616 = 64'h0001010100111111 >> { n379, n185, n282, n173, n405, n398 }; + assign n617 = 64'h00080a0a00ccffff >> { n183, n378, n173, n290, n363, n400 }; + assign n618 = 32'd131586 >> { i_8_, n620, n386, n384, n619 }; + assign n619 = 64'h0111055503330777 >> { n376, n149, n313, n358, n309, n196 }; + assign n620 = 16'h8000 >> { n102, n133, n126, n222 }; + assign n621 = 64'h0000000000000008 >> { n396, n394, n397, n623, n622, n391 }; + assign n622 = 16'h0777 >> { n185, n376, n162, n389 }; + assign n623 = 4'h8 >> { n149, n361 }; + assign n120 = 8'h80 >> { i_12_, i_13_, i_14_ }; + assign n624 = 64'h00011111000fffff >> { n368, n196, n380, n290, n281, n358 }; + assign n625 = 64'h00011111000fffff >> { n361, n135, n85, n376, n185, n196 }; + assign n626 = 64'h1000101011001111 >> { n309, n620, i_8_, n377, n393, n407 }; + assign n627 = 64'h8000800080000000 >> { n278, n637, n632, n628, n639, n629 }; + assign n628 = 64'h151f151f050f151f >> { i_14_, n124, n240, n196, n611, n426 }; + assign n629 = 64'h00011111000fffff >> { n630, n631, n205, n173, n196, n313 }; + assign n630 = 4'h2 >> { n593, n84 }; + assign n631 = 4'h2 >> { n593, n124 }; + assign n632 = 32'd16843008 >> { n633, n373, n634, n635, n636 }; + assign n633 = 8'h57 >> { n157, n148, n223 }; + assign n121 = 16'h0002 >> { i_9_, i_10_, i_15_, i_11_ }; + assign n634 = 32'd2155905024 >> { n103, n98, n81, n146, n148 }; + assign n635 = 64'h8888800080008000 >> { n124, n223, n81, n128, n133, n136 }; + assign n636 = 64'h0800080008080800 >> { i_7_, n146, n160, i_6_, n128, n81 }; + assign n637 = 16'h0002 >> { n242, n558, n631, n638 }; + assign n638 = 16'h5557 >> { n418, n68, n222, n151 }; + assign n639 = 64'h0004000544445555 >> { n641, n198, n186, n132, n640, n642 }; + assign n640 = 8'hab >> { n84, n83, n593 }; + assign n641 = 4'h8 >> { n81, n157 }; + assign n642 = 32'd32768 >> { i_6_, n160, n124, n81, i_8_ }; + assign n643 = 64'h1515151500151515 >> { n593, n148, n205, n562, n145, n644 }; + assign n122 = 4'h8 >> { n123, n124 }; + assign n644 = 32'd134744064 >> { i_10_, i_11_, i_9_, n136, n327 }; + assign n645 = 32'd1390302175 >> { n647, n187, n336, n646, n423 }; + assign n646 = 4'h8 >> { n81, n83 }; + assign n647 = 16'h8000 >> { n81, n151, n161, n133 }; + assign n648 = 64'h00020003aaaaffff >> { n240, n198, n440, n435, n557, n638 }; + assign n649 = 16'h8000 >> { n81, n93, n151, n146 }; + assign n650 = 16'h8000 >> { n81, n84, n146, n134 }; + assign n651 = 16'h8000 >> { n81, n151, n103, n160 }; + assign n652 = 64'h0008000800080000 >> { n124, n148, n593, i_6_, n160, i_8_ }; + assign n653 = 64'h0001010100111111 >> { n154, n163, n654, n419, n655, n656 }; + assign n123 = 8'h08 >> { i_13_, i_12_, i_14_ }; + assign n654 = 4'h8 >> { n81, n148 }; + assign n655 = 16'h8000 >> { n98, n81, n84, n160 }; + assign n656 = 16'h8000 >> { n151, n105, n146, n223 }; + assign n657 = 64'h0011101101111111 >> { n599, n94, n171, i_8_, n659, n658 }; + assign n658 = 16'h0080 >> { n593, n161, n146, n83 }; + assign n659 = 16'h0080 >> { n593, n160, n182, n105 }; + assign n660 = 4'h8 >> { n81, n84 }; + assign n661 = 64'h0808080008080808 >> { n373, n198, o_17_, i_14_, i_12_, n176 }; + assign n662 = 8'h80 >> { n605, n136, n327 }; + assign n663 = 16'h8000 >> { n98, n81, n83, n146 }; + assign n70 = 32'd128 >> { i_4_, i_2_, i_0_, n71, i_1_ }; + assign n124 = 16'h0008 >> { i_9_, i_10_, i_11_, i_15_ }; + assign n664 = 16'h0080 >> { i_14_, n182, n136, n146 }; + assign n665 = 16'h0080 >> { n593, n157, n136, n133 }; + assign n666 = 16'h8000 >> { n81, n84, n133, n134 }; + assign n667 = 16'h8000 >> { n81, n133, n134, n176 }; + assign n668 = 16'h8000 >> { n81, n133, n157, n136 }; + assign n669 = 64'h8880888088888880 >> { n593, n84, n671, n670, n111, n146 }; + assign n670 = 64'h0000000000008000 >> { i_10_, i_14_, i_9_, i_15_, i_12_, i_11_ }; + assign n671 = 64'h0000000000000080 >> { i_9_, i_11_, i_14_, i_15_, i_12_, i_10_ }; + assign n672 = 64'h0808080808080800 >> { n176, n84, n83, n593, n216, n160 }; + assign n673 = 16'h111f >> { n160, n146, n93, n105 }; + assign n125 = 4'h8 >> { n120, n126 }; + assign n674 = 32'd1171211589 >> { n279, n183, n132, n675, n433 }; + assign n675 = 64'h5f577fffdf57ffff >> { n223, n81, i_15_, i_10_, i_11_, i_9_ }; + assign n676 = 32'd2324335311 >> { n551, n553, n205, n638, n283 }; + assign n677 = 4'h8 >> { n81, n151 }; + assign n678 = 64'h082e097f88ae89ff >> { n133, n146, n160, i_8_, i_6_, i_7_ }; + assign n679 = 64'h0002000200000002 >> { n689, n149, n687, n688, n680, n684 }; + assign n680 = 16'h5554 >> { n683, n196, n681, n682 }; + assign n681 = 64'h8808880880080000 >> { n146, n160, i_7_, i_6_, n557, i_8_ }; + assign n682 = 32'd353703231 >> { n126, n69, n68, n176, n81 }; + assign n683 = 16'h8000 >> { n81, n133, n126, n164 }; + assign n126 = 16'h0008 >> { i_9_, i_15_, i_10_, i_11_ }; + assign n684 = 8'h45 >> { n563, n685, n686 }; + assign n685 = 8'h01 >> { n173, n194, n197 }; + assign n686 = 16'h8000 >> { n68, n133, n182, n136 }; + assign n687 = 16'ha888 >> { n69, n276, n599, n196 }; + assign n688 = 4'h2 >> { n480, n198 }; + assign n689 = 16'h0777 >> { n126, n81, n68, n176 }; + assign n690 = 64'h0000000080000000 >> { n691, n1135, n692, n695, n708, n714 }; + assign n691 = 16'haa2a >> { n436, n595, n591, n135 }; + assign n692 = 64'h0202020202000202 >> { i_6_, n160, n694, n311, n693, n1159 }; + assign n693 = 64'haaaaaaaaaaaaaaa8 >> { n183, n135, n186, n312, n313, n660 }; + assign n127 = 4'h8 >> { n128, n120 }; + assign n694 = 32'd1465341951 >> { i_11_, i_10_, n223, n123, i_15_ }; + assign n695 = 64'h0080000000800080 >> { n336, n697, n696, n703, n705, n698 }; + assign n696 = 8'ha8 >> { n376, n85, n245 }; + assign n697 = 16'h0001 >> { n119, n130, n290, n420 }; + assign n698 = 64'h0001000100000001 >> { n377, n79, n699, n700, n701, n702 }; + assign n699 = 32'd2290122880 >> { n148, n418, n269, n93, n160 }; + assign n700 = 32'd134744064 >> { n146, n160, n593, n134, n84 }; + assign n701 = 64'h8080800000800000 >> { n418, n276, i_15_, n166, n98, n160 }; + assign n702 = 32'd2290122880 >> { n151, n222, n269, n133, n93 }; + assign n703 = 64'h4000404055005555 >> { n149, n179, n267, n638, n588, n704 }; + assign n128 = 16'h0008 >> { i_11_, i_15_, i_10_, i_9_ }; + assign n704 = 32'd134744064 >> { n146, n160, n268, n93, n80 }; + assign n705 = 64'hdd0ddd0d0000dd0d >> { n604, n240, n707, n196, n706, n183 }; + assign n706 = 16'h111f >> { n123, n223, n83, n124 }; + assign n707 = 32'd1426421511 >> { n222, n593, n83, n68, n151 }; + assign n708 = 64'h0100010001000101 >> { n154, o_17_, n576, n710, n712, n709 }; + assign n709 = 16'h5554 >> { n552, n290, n289, n283 }; + assign n710 = 16'haaa8 >> { n711, n125, n225, n162 }; + assign n711 = 4'h2 >> { n593, n176 }; + assign n712 = 4'h2 >> { n713, n203 }; + assign n713 = 64'hd3d755d7fbff5dff >> { n124, i_15_, n326, i_13_, i_12_, i_14_ }; + assign n129 = 4'h8 >> { n80, n120 }; + assign n714 = 16'hdd0d >> { n575, n196, n715, n179 }; + assign n715 = 8'h15 >> { n222, n96, n269 }; + assign o_10_ = 32'd2147483647 >> { n1130, n717, n718, n1201, n1340 }; + assign n717 = 32'd32768 >> { n461, n448, n452, n457, n1328 }; + assign n718 = 64'h8000000000000000 >> { n1334, n1176, n1179, n719, n725, n730 }; + assign n719 = 64'h0080008000000080 >> { n257, n549, n722, n724, n720, n723 }; + assign n720 = 64'h02020202020202aa >> { n163, n196, n149, n558, n550, n721 }; + assign n721 = 64'h0000077707770777 >> { n145, n551, n159, n554, n565, n149 }; + assign n722 = 8'ha8 >> { n552, n561, n135 }; + assign n723 = 64'h00011111000fffff >> { n79, n196, n556, n563, n198, n135 }; + assign n130 = 4'h8 >> { n83, n123 }; + assign n724 = 32'd353703231 >> { n163, n162, n94, n132, n562 }; + assign n725 = 64'h0008000000080008 >> { n563, n685, n681, n571, n729, n726 }; + assign n726 = 64'h22222222222222a2 >> { n549, n79, n556, n728, n185, n727 }; + assign n727 = 64'h00011111000fffff >> { n186, n185, n550, n565, n554, n558 }; + assign n728 = 32'd4025470447 >> { i_9_, n68, n81, i_10_, i_15_ }; + assign n729 = 64'h4444555500040005 >> { n682, n149, n196, n683, n689, n686 }; + assign n730 = 8'h80 >> { n581, n582, n583 }; + assign n731 = 64'h0008080800888888 >> { n79, n240, n433, n173, n733, n732 }; + assign n732 = 64'h7777777707777777 >> { i_14_, n176, i_12_, n162, n336, n231 }; + assign n733 = 32'd1465319511 >> { n279, n552, n196, n154, n422 }; + assign n131 = 32'd89458551 >> { n127, n132, n137, n119, n135 }; + assign n734 = 8'h01 >> { n228, n440, n426 }; + assign n735 = 32'd572662434 >> { n149, n196, n278, n423, n736 }; + assign n736 = 32'd16843025 >> { n135, n198, n436, n738, n737 }; + assign n737 = 8'ha8 >> { n420, n247, n179 }; + assign n738 = 8'ha8 >> { o_17_, n183, n416 }; + assign n739 = 64'h2020222200200022 >> { n270, n94, n424, n283, n579, n740 }; + assign n740 = 16'hdd0d >> { n278, n417, n513, n232 }; + assign n741 = 32'd286331217 >> { n203, o_14_, n278, n246, n742 }; + assign n742 = 32'd2863311522 >> { n562, n229, n426, n633, n159 }; + assign n743 = 8'h08 >> { n610, n746, n744 }; + assign n132 = 4'h8 >> { n133, n134 }; + assign n744 = 32'd2324299914 >> { n304, n646, n236, n302, n745 }; + assign n745 = 64'h0008000acccceeee >> { n434, o_17_, n197, n135, n596, n296 }; + assign n746 = 64'h1515151515155515 >> { n198, n171, n300, n223, n69, n747 }; + assign n747 = 64'hcdcdcdcdcdcdcd45 >> { n336, n183, n198, n748, n241, n300 }; + assign n748 = 16'h7707 >> { n593, n182, n126, n223 }; + assign n749 = 4'h8 >> { n68, n126 }; + assign n750 = 64'h2222002220200020 >> { n751, n753, n756, n272, n752, n754 }; + assign n751 = 32'd1 >> { n556, n379, n550, n378, n558 }; + assign n752 = 32'd2863311522 >> { n149, n135, n198, n373, n542 }; + assign n753 = 32'd1 >> { n162, o_18_, n132, n207, n154 }; + assign n133 = 64'h0000000000000008 >> { i_1_, i_0_, i_3_, i_2_, i_4_, i_5_ }; + assign n754 = 32'd17895263 >> { n749, n132, n755, n185, n186 }; + assign n755 = 4'h8 >> { n68, n128 }; + assign n756 = 4'h8 >> { n68, n141 }; + assign n757 = 32'd1414812672 >> { n222, n81, n88, n121, n217 }; + assign n758 = 4'h8 >> { n68, n139 }; + assign n759 = 16'ha888 >> { n139, n418, n378, n135 }; + assign n760 = 16'haaa8 >> { n162, n336, o_14_, n290 }; + assign n761 = 32'd1465319511 >> { n279, n282, n163, n173, n762 }; + assign n762 = 8'h02 >> { n68, i_14_, n121 }; + assign n763 = 8'h2a >> { n278, n217, n764 }; + assign n71 = 4'h2 >> { i_3_, i_5_ }; + assign n134 = 8'h08 >> { i_8_, i_6_, i_7_ }; + assign n764 = 8'h02 >> { n68, i_14_, n126 }; + assign n765 = 32'd2829625504 >> { n161, n216, n145, n160, n562 }; + assign n766 = 8'h02 >> { n68, i_14_, n69 }; + assign n767 = 64'h00200022a0a0a2a2 >> { n774, n159, n163, n773, n162, n768 }; + assign n768 = 64'h0001000100000001 >> { n257, n769, n317, n770, n771, n772 }; + assign n769 = 4'h8 >> { n68, n88 }; + assign n770 = 32'd2147483648 >> { n68, n92, n133, n126, i_8_ }; + assign n771 = 16'h8000 >> { n68, n133, n157, n136 }; + assign n772 = 32'd2155905024 >> { n164, n98, n160, n139, n68 }; + assign n773 = 16'h5557 >> { n418, n81, n222, n128 }; + assign n135 = 4'h8 >> { n133, n136 }; + assign n774 = 8'h02 >> { n68, i_14_, n139 }; + assign n775 = 64'h0008000accccffff >> { n549, n79, o_18_, n313, n296, n279 }; + assign n776 = 64'h0002020200aa22aa >> { n774, n162, n778, n173, n159, n1210 }; + assign n777 = 32'd128 >> { n68, i_14_, n161, n121, n160 }; + assign n778 = 8'h02 >> { n68, i_14_, n141 }; + assign n779 = 32'd2155905024 >> { i_10_, i_11_, i_9_, o_18_, n531 }; + assign n780 = 32'd125269879 >> { n141, n418, n154, n524, n336 }; + assign n781 = 16'h1115 >> { n205, n159, n756, n782 }; + assign n782 = 16'h8000 >> { n68, n128, n105, n160 }; + assign n783 = 8'h02 >> { n68, i_14_, n80 }; + assign n136 = 8'h80 >> { i_7_, i_6_, i_8_ }; + assign n784 = 64'h0808080808088808 >> { n778, n774, n773, n205, n786, n785 }; + assign n785 = 32'd1171211589 >> { n373, n198, n87, n513, n543 }; + assign n786 = 64'h0015151515151515 >> { i_9_, n134, n327, n758, n149, n787 }; + assign n787 = 32'd2155905024 >> { n139, n128, n146, n155, n418 }; + assign n788 = 32'd16843025 >> { n778, n764, n132, n790, n789 }; + assign n789 = 16'h22a2 >> { i_8_, n774, n773, n240 }; + assign n790 = 32'd2863311528 >> { n762, n758, n756, n766, n135 }; + assign n791 = 64'h00aaffff00020303 >> { n302, n758, n207, n559, n389, n296 }; + assign n792 = 16'h8880 >> { n198, n135, n80, n418 }; + assign n793 = 32'd1936946001 >> { n171, n198, n376, n794, n300 }; + assign n137 = 4'h8 >> { n88, n120 }; + assign n794 = 64'h0101010101011101 >> { n762, n774, n773, n198, n375, n563 }; + assign n795 = 16'h88a8 >> { n377, n778, n796, n473 }; + assign n796 = 8'h02 >> { n68, i_14_, n88 }; + assign n797 = 8'ha8 >> { n163, n135, n778 }; + assign n798 = 8'h51 >> { n196, n532, n541 }; + assign n799 = 32'd3149597627 >> { n800, n516, n97, n371, n183 }; + assign n800 = 4'h8 >> { n68, n121 }; + assign o_13_ = 16'h7fff >> { n1216, n829, n830, n832 }; + assign n802 = 32'd32768 >> { n769, n803, n805, n806, n807 }; + assign n803 = 16'h222a >> { n84, n124, n120, n804 }; + assign n138 = 4'h8 >> { n120, n139 }; + assign n804 = 32'd2113929085 >> { i_15_, i_13_, i_12_, i_14_, n605 }; + assign n805 = 64'ha801fbdfac21ffff >> { n498, n605, i_15_, i_12_, i_13_, i_14_ }; + assign n806 = 16'h0777 >> { n86, n83, n80, n418 }; + assign n807 = 16'h0777 >> { n121, n418, n86, n124 }; + assign n808 = 32'd8 >> { n79, n287, n800, n480, n809 }; + assign n809 = 32'd2113929087 >> { i_15_, i_13_, i_12_, i_14_, n166 }; + assign n810 = 64'h8080008080808080 >> { i_8_, n604, n240, n1135, n1163, n811 }; + assign n811 = 64'h5d5f5f5fdd5ddf7f >> { i_13_, n176, i_12_, n126, i_14_, n135 }; + assign n812 = 64'h8000000000000000 >> { n117, n1151, n1157, n813, n820, n821 }; + assign n813 = 64'h22222222a2222222 >> { n778, n818, n816, n817, n135, n814 }; + assign n139 = 16'h0008 >> { i_10_, i_15_, i_9_, i_11_ }; + assign n814 = 16'h0ddd >> { n489, n135, n815, n132 }; + assign n815 = 32'd4294902063 >> { i_14_, n88, n84, i_12_, i_13_ }; + assign n816 = 8'h01 >> { n350, n512, n677 }; + assign n817 = 32'd4261412733 >> { i_15_, i_13_, i_12_, i_14_, n498 }; + assign n818 = 32'd4261412733 >> { i_15_, i_13_, i_12_, i_14_, n819 }; + assign n819 = 8'h02 >> { i_11_, i_10_, i_9_ }; + assign n820 = 64'h0000000100010001 >> { n654, n135, n665, n666, n667, n668 }; + assign n821 = 32'd829759604 >> { n822, n132, n823, n749, n135 }; + assign n822 = 32'd1718613759 >> { n157, n141, i_13_, i_12_, i_14_ }; + assign n823 = 32'd1035959807 >> { n126, n176, i_12_, i_14_, i_13_ }; + assign n140 = 4'h8 >> { n120, n141 }; + assign n824 = 32'd2147516544 >> { n135, n803, n1181, n825, n788 }; + assign n825 = 64'hf777ff77f7f7f77f >> { i_13_, i_12_, i_15_, i_14_, n135, n166 }; + assign n826 = 32'd286331157 >> { n796, n189, n563, n135, n827 }; + assign n827 = 16'haaa8 >> { n783, n337, n592, n135 }; + assign n828 = 8'h01 >> { n332, n490, n630 }; + assign n829 = 64'h005d5d5d5d5d5d5d >> { n96, n327, n93, n755, n816, n132 }; + assign n830 = 16'h7707 >> { n831, n240, n135, n755 }; + assign n831 = 32'd2113929085 >> { i_15_, i_13_, i_12_, i_14_, n326 }; + assign n832 = 64'hf77ff77ff7fff77f >> { i_8_, i_9_, i_11_, i_10_, n155, n327 }; + assign o_15_ = 32'd4292203989 >> { n194, n605, n312, n819, n834 }; + assign n141 = 16'h0080 >> { i_15_, i_11_, i_10_, i_9_ }; + assign n834 = 8'h57 >> { n819, n605, n171 }; + assign n835 = 64'h0022202220222022 >> { n120, n84, n313, n838, n836, n837 }; + assign n836 = 64'h8808080080880808 >> { i_12_, i_15_, i_13_, i_14_, n819, n368 }; + assign n837 = 32'd16843025 >> { n153, n281, n368, n351, n650 }; + assign n838 = 16'h0777 >> { n84, n81, n88, n123 }; + assign n839 = 16'haaa2 >> { n358, n557, n840, n197 }; + assign n840 = 4'h1 >> { n182, n301 }; + assign n841 = 8'h8a >> { n804, n543, n197 }; + assign n842 = 4'h8 >> { n183, n326 }; + assign o_22_ = 32'd4177066224 >> { n105, n98, n844, n89, n846 }; + assign n142 = 32'd134776840 >> { n156, n143, n149, n144, n152 }; + assign n844 = 32'd32768 >> { n845, n71, n90, n134, i_4_ }; + assign n845 = 4'h2 >> { n94, n78 }; + assign n846 = 4'h8 >> { n68, n80 }; + assign o_23_ = 64'hffffffffffffff7f >> { n848, n101, n104, n850, n851, n77 }; + assign n848 = 4'h2 >> { n845, n849 }; + assign n849 = 16'h0080 >> { i_4_, n90, n134, n71 }; + assign n850 = 16'h8088 >> { n113, n845, n108, n114 }; + assign n851 = 32'd1423760604 >> { n89, n216, n78, n852, n94 }; + assign n852 = 64'hf7fff7f7fffff7ff >> { i_4_, i_7_, i_6_, i_8_, n71, n90 }; + assign o_34_ = 4'h8 >> { n133, i_7_ }; + assign n143 = 4'h1 >> { n129, n130 }; + assign o_32_ = 64'hffffffffffff7fff >> { n844, n876, n1225, n1216, n850, n1348 }; + assign n855 = 32'd128 >> { i_3_, i_5_, n90, n216, i_4_ }; + assign n856 = 64'h15373737153f3f3f >> { n81, n185, n120, n800, n186, n124 }; + assign n857 = 16'ha222 >> { n83, n120, n597, n185 }; + assign n858 = 8'h2a >> { n120, n84, n804 }; + assign n859 = 64'h0002000202020002 >> { n677, n861, n186, n860, n535, n830 }; + assign n860 = 8'ha8 >> { n641, n324, n186 }; + assign n861 = 8'h15 >> { n124, n120, n297 }; + assign n862 = 32'd2147483648 >> { n90, n111, i_3_, i_5_, i_4_ }; + assign n863 = 32'd353703231 >> { n512, n350, n846, n185, n186 }; + assign n72 = 4'h2 >> { i_1_, i_0_ }; + assign n144 = 32'd320017239 >> { n138, n147, n149, n145, n150 }; + assign n864 = 64'h577f7777df7f7f7f >> { n141, i_12_, i_13_, n157, i_14_, n186 }; + assign n865 = 32'd2930683839 >> { n157, i_12_, n141, i_13_, i_14_ }; + assign n866 = 4'h2 >> { n465, n176 }; + assign n867 = 64'h000101010055ffff >> { n186, n185, n175, n125, n542, n309 }; + assign n868 = 8'h2a >> { n869, n838, n185 }; + assign n869 = 32'd3874486015 >> { n157, n141, i_13_, i_14_, i_12_ }; + assign n870 = 64'hf7f77f7777ff7f7f >> { i_15_, i_12_, i_13_, i_14_, n185, n166 }; + assign n871 = 64'h222222222222222a >> { n129, n130, n181, n156, n185, n872 }; + assign n872 = 64'h010f010f010f111f >> { n122, n137, n185, n186, n150, n189 }; + assign n873 = 64'h0008000808080008 >> { n375, n412, n186, n411, n259, n413 }; + assign n145 = 4'h8 >> { n93, n146 }; + assign n874 = 64'haaaaaaaa2aaaaaaa >> { n758, n823, n831, n591, n875, n186 }; + assign n875 = 16'h0002 >> { n511, n524, n756, n480 }; + assign n876 = 64'h0000800080008000 >> { n95, n845, n71, n90, n216, i_4_ }; + assign o_33_ = 64'h7f7fff7f7f77ff77 >> { n849, n95, n878, n845, n100, n76 }; + assign n878 = 16'h0080 >> { i_4_, n90, n93, n71 }; + assign n879 = 64'h00011111000fffff >> { n778, n313, n796, n769, n135, n163 }; + assign n880 = 16'h777f >> { i_14_, i_15_, n149, n166 }; + assign n881 = 4'h8 >> { n825, n870 }; + assign n882 = 8'h80 >> { n102, n327, i_8_ }; + assign n883 = 64'h0000000000000001 >> { n404, n346, n349, n884, n521, n701 }; + assign n146 = 64'h0000000000000002 >> { i_1_, i_0_, i_3_, i_4_, i_2_, i_5_ }; + assign n884 = 16'h8000 >> { n160, n139, n123, n164 }; + assign n885 = 8'h80 >> { n98, n166, n327 }; + assign n886 = 64'h00020003aaaaffff >> { n758, n185, n149, n135, n187, n809 }; + assign n887 = 16'h555d >> { n147, n440, n888, n179 }; + assign n888 = 32'd2105507711 >> { i_15_, i_14_, i_12_, i_13_, n166 }; + assign n889 = 64'hdd0ddd0d0000dd0d >> { n575, n196, n603, n163, n715, n179 }; + assign n890 = 64'h0888888888888888 >> { i_15_, i_12_, i_13_, i_14_, n96, n173 }; + assign n891 = 16'ha222 >> { n96, n418, n715, n185 }; + assign n892 = 32'd56055639 >> { n151, n276, n185, n196, n127 }; + assign n893 = 64'h00011111000fffff >> { n755, n185, n550, n565, n163, n149 }; + assign n147 = 4'h8 >> { n123, n148 }; + assign n894 = 4'h8 >> { n163, n468 }; + assign n895 = 16'ha888 >> { n150, n207, n330, i_8_ }; + assign n896 = 4'h1 >> { n527, n540 }; + assign n897 = 16'hdd0d >> { n593, n157, n268, n141 }; + assign n898 = 4'h8 >> { n464, n897 }; + assign n899 = 16'h0008 >> { n332, n630, n896, n869 }; + assign n900 = 64'h8000000000000000 >> { n901, n910, n915, n916, n919, n920 }; + assign n901 = 64'h8000800080808000 >> { n157, n909, n377, n902, n906, n908 }; + assign n902 = 64'h0000000000000002 >> { n903, n353, n463, n668, n904, n905 }; + assign n903 = 16'h8000 >> { n123, n141, n133, n136 }; + assign n148 = 16'h0080 >> { i_10_, i_11_, i_9_, i_15_ }; + assign n904 = 16'h8000 >> { n68, n141, n136, n133 }; + assign n905 = 64'h77777fff7fff7fff >> { n133, n164, n98, n146, n123, n157 }; + assign n906 = 64'h00800088f0f0ffff >> { n185, n198, n907, n464, n494, n576 }; + assign n907 = 16'h8000 >> { n157, i_12_, i_13_, i_14_ }; + assign n908 = 32'd3587506389 >> { n822, n149, n897, n464, n173 }; + assign n909 = 32'd1035959807 >> { n141, n157, i_12_, i_14_, i_13_ }; + assign n910 = 64'h0008000800080808 >> { n149, n196, n433, n868, n913, n911 }; + assign n911 = 64'h00011111000fffff >> { n149, n196, n769, n314, n912, n436 }; + assign n912 = 8'h08 >> { i_14_, i_12_, n84 }; + assign n913 = 16'hab23 >> { n914, n196, n185, n865 }; + assign n149 = 4'h8 >> { n98, n146 }; + assign n914 = 32'd1465745277 >> { i_14_, i_13_, i_15_, i_12_, n819 }; + assign n915 = 64'h00ffffff00010101 >> { n818, n409, i_8_, n198, n173, n135 }; + assign n916 = 64'h0008080800888888 >> { n94, n185, n758, n196, n918, n917 }; + assign n917 = 32'd125269879 >> { n84, n120, n135, n232, n149 }; + assign n918 = 64'h0001010100555555 >> { n196, n549, n185, n281, n660, n665 }; + assign n919 = 64'h1515151500151515 >> { n268, n141, n135, n137, n149, n212 }; + assign n920 = 64'h00011111000fffff >> { n185, n149, n549, n94, n232, n796 }; + assign n921 = 64'h0080008000800000 >> { n377, n932, n933, n922, n929, n927 }; + assign n922 = 64'h0015151515151515 >> { i_8_, n749, n207, n925, n926, n923 }; + assign n923 = 4'h2 >> { n924, n187 }; + assign n150 = 4'h8 >> { n151, n123 }; + assign n924 = 32'd148638207 >> { n176, n126, i_13_, i_14_, i_12_ }; + assign n925 = 4'h8 >> { n136, n327 }; + assign n926 = 8'h08 >> { i_9_, i_11_, i_10_ }; + assign n927 = 64'h00080a0a00ccffff >> { n185, n149, n389, n323, n928, n807 }; + assign n928 = 4'h1 >> { n416, n420 }; + assign n929 = 64'h00800088a0a0aaaa >> { n196, n185, n140, n817, n464, n930 }; + assign n930 = 32'd4160181751 >> { n279, n762, n931, n336, i_8_ }; + assign n931 = 16'h0777 >> { n121, n418, n120, n124 }; + assign n932 = 8'h01 >> { n333, n471, n631 }; + assign n933 = 64'heaeaeac0aaaaaa80 >> { n196, n631, n471, n121, i_14_, n163 }; + assign n151 = 16'h0080 >> { i_11_, i_9_, i_10_, i_15_ }; + assign n934 = 64'h8000800000008000 >> { n567, n185, n939, n941, n935, n937 }; + assign n935 = 64'h0002020200aaaaaa >> { n489, n196, n907, n198, n135, n936 }; + assign n936 = 16'h5557 >> { n501, n119, n420, n179 }; + assign n937 = 64'h515151f351f351f3 >> { n327, n98, n925, n938, n173, n498 }; + assign n938 = 8'h15 >> { n124, n81, n297 }; + assign n939 = 64'h0002020200aaaaaa >> { n559, n882, n498, n149, n135, n940 }; + assign n940 = 64'h5055707770777077 >> { i_14_, n124, n196, n807, n360, n135 }; + assign n941 = 32'd3149597627 >> { n576, o_18_, i_8_, n163, n909 }; + assign n942 = 4'h2 >> { n234, n149 }; + assign n943 = 64'h00011111000fffff >> { n119, n122, n179, n196, n135, n149 }; + assign n152 = 32'd138087743 >> { n137, n149, n153, n145, n119 }; + assign n944 = 16'h7757 >> { i_14_, n124, n611, n196 }; + assign n945 = 8'ha8 >> { n389, n235, n185 }; + assign n946 = 64'h0808800888088080 >> { i_12_, i_13_, i_14_, i_15_, n173, n326 }; + assign n947 = 64'h0001010100555555 >> { n646, n149, n290, n198, n163, n442 }; + assign n948 = 32'd33694210 >> { n129, n591, n149, n949, n950 }; + assign n949 = 16'haaa2 >> { n85, n290, n250, n185 }; + assign n950 = 64'h000400054444ffff >> { n198, n196, n337, n783, n806, n592 }; + assign n951 = 32'd2155905024 >> { i_6_, i_7_, n326, n327, i_8_ }; + assign n952 = 64'h0808080888080808 >> { n769, n803, n840, n163, n954, n953 }; + assign n953 = 64'h0002000000020002 >> { n563, n685, n687, n688, n681, n729 }; + assign n153 = 4'h8 >> { n84, n123 }; + assign n954 = 32'd16842753 >> { n960, n313, n957, n955, n956 }; + assign n955 = 64'h8008888800808008 >> { i_14_, i_15_, i_12_, i_13_, n605, n194 }; + assign n956 = 64'haaaaa222a222a222 >> { n124, n120, n86, n182, n804, n185 }; + assign n957 = 64'heeeeeeee0eeeeeee >> { n800, n838, n958, n959, n149, n163 }; + assign n958 = 16'h0777 >> { n83, n120, n68, n80 }; + assign n959 = 32'd1718613759 >> { n176, n126, i_13_, i_12_, i_14_ }; + assign n960 = 64'h635667767bdfffff >> { n605, n819, i_13_, i_12_, i_15_, i_14_ }; + assign n961 = 32'd3477423429 >> { n963, n962, n173, n924, n185 }; + assign n962 = 32'd2242099123 >> { n126, i_13_, i_14_, n176, i_12_ }; + assign n963 = 32'd4259183959 >> { i_12_, i_15_, i_13_, i_14_, n605 }; + assign o_1_ = 32'd4098160230 >> { i_1_, i_7_, o_2_, i_2_, i_0_ }; + assign n154 = 4'h8 >> { n155, n146 }; + assign n964 = 32'd1431655761 >> { n749, n502, n506, n965, n372 }; + assign n965 = 16'h8000 >> { n858, n966, n537, n958 }; + assign n966 = 8'h15 >> { n124, n120, n800 }; + assign n967 = 4'h2 >> { n445, n447 }; + assign n968 = 4'h2 >> { n220, n224 }; + assign n969 = 32'd1162167759 >> { n135, n149, n313, n347, n303 }; + assign n970 = 4'h1 >> { n308, n611 }; + assign n971 = 64'h0008000accccffff >> { n173, n185, n85, n671, n823, n597 }; + assign n972 = 64'h8a8a8a8aaa8a8a8a >> { i_14_, n176, i_12_, n597, n542, n196 }; + assign n973 = 32'd2 >> { n122, n287, n419, n542, n802 }; + assign n155 = 4'h2 >> { i_7_, i_6_ }; + assign n974 = 64'h0057575757575757 >> { n134, n327, n819, n186, n159, n796 }; + assign n975 = 64'h0008000a8888aaaa >> { n145, n132, n94, n549, n464, n976 }; + assign n976 = 64'h00011111000fffff >> { n174, n232, n186, n145, n153, n630 }; + assign n977 = 32'd320017239 >> { n140, n314, n186, n132, n137 }; + assign n978 = 64'h00011111000fffff >> { n145, n186, n350, n512, n156, n137 }; + assign n979 = 64'h22222222222222a2 >> { n512, n912, n540, n980, n145, n981 }; + assign n980 = 32'd1 >> { n87, n153, n281, n433, n907 }; + assign n981 = 32'd3587560704 >> { n300, n818, n982, n822, n132 }; + assign n982 = 32'd4149608445 >> { i_14_, i_12_, i_13_, i_15_, n819 }; + assign n983 = 64'h1101550513035707 >> { n984, n630, n818, n186, n162, n490 }; + assign n156 = 4'h8 >> { n123, n157 }; + assign n984 = 8'h08 >> { i_8_, n160, n111 }; + assign n985 = 16'haa2a >> { n140, n464, n576, n174 }; + assign n986 = 32'd17895263 >> { n907, n174, n756, n186, n162 }; + assign n987 = 8'h02 >> { i_6_, i_8_, n160 }; + assign n988 = 32'd4008636128 >> { n159, n186, n205, n756, n778 }; + assign n989 = 64'haaaaffff00020003 >> { n909, n145, n174, n984, n159, n869 }; + assign n990 = 32'd1381653 >> { n244, n132, n641, n162, n991 }; + assign n991 = 32'd2147483648 >> { n134, n327, i_9_, i_11_, i_10_ }; + assign n992 = 64'ha8a82a0828002a00 >> { n141, i_13_, n157, i_12_, i_14_, n145 }; + assign n993 = 64'h008201ffffffffff >> { n162, n157, n141, i_12_, i_14_, i_13_ }; + assign n157 = 16'h8000 >> { i_9_, i_11_, i_10_, i_15_ }; + assign n994 = 64'h0000000000000008 >> { n995, n606, n998, n999, n996, n1000 }; + assign n995 = 32'd2290649096 >> { n203, n186, n265, n139, n418 }; + assign n996 = 32'd3708638469 >> { n363, n997, n145, n265, n524 }; + assign n997 = 16'h0001 >> { n320, n552, n554, n654 }; + assign n998 = 64'h8888008088088080 >> { i_15_, i_12_, i_14_, i_13_, n166, n186 }; + assign n999 = 16'heee0 >> { n774, n489, n132, n987 }; + assign n1000 = 32'd286331157 >> { n440, n229, n289, n145, n1001 }; + assign n1001 = 16'h8880 >> { n134, n161, n166, n327 }; + assign n1002 = 32'd17892863 >> { n174, n132, n229, n282, n228 }; + assign n1003 = 32'd34218538 >> { n554, n162, n205, n670, n1004 }; + assign n158 = 32'd2863311528 >> { n154, n163, n162, n159, n140 }; + assign n1004 = 32'd125269879 >> { n166, n327, n93, n758, n186 }; + assign n1005 = 64'h0002000200022222 >> { n282, n554, n132, n186, n1008, n1006 }; + assign n1006 = 64'hffff000f11110001 >> { n265, n1007, n132, n205, n138, n147 }; + assign n1007 = 4'h1 >> { n320, n654 }; + assign n1008 = 4'h2 >> { n588, n145 }; + assign n1009 = 64'h0002000202020002 >> { n758, n809, n159, n1010, n1011, n1012 }; + assign n1010 = 16'h5444 >> { n120, n148, n758, n296 }; + assign n1011 = 64'h0000888808000880 >> { i_15_, i_14_, i_12_, i_13_, n174, n166 }; + assign n1012 = 64'hf777f7777f77f77f >> { i_13_, i_14_, i_15_, i_12_, n162, n166 }; + assign n1013 = 16'haaa8 >> { n247, n550, n565, n186 }; + assign n159 = 4'h8 >> { n160, n161 }; + assign n1014 = 64'h8000000000000000 >> { n829, n1015, n1017, n1019, n1021, n1022 }; + assign n1015 = 64'h0202020222020202 >> { n269, n638, n773, n174, n1016, n941 }; + assign n1016 = 32'd2863311522 >> { n755, n512, n677, n638, n159 }; + assign n1017 = 64'h0000000200020002 >> { n907, n196, n210, n292, n352, n1018 }; + assign n1018 = 8'h57 >> { n247, n269, n203 }; + assign n1019 = 64'h02020002aaaa00aa >> { n132, n265, n150, n550, n379, n1020 }; + assign n1020 = 64'h5ddd7fff7fff7fff >> { i_12_, n186, n132, i_13_, i_14_, n128 }; + assign n1021 = 64'h0001010100ff55ff >> { n755, n162, n512, n174, n145, n984 }; + assign n1022 = 64'h00011111000fffff >> { n186, n468, n205, n132, n127, n150 }; + assign n1023 = 8'h2a >> { n418, n128, n603 }; + assign n160 = 64'h0000000000000002 >> { i_1_, i_0_, i_3_, i_5_, i_2_, i_4_ }; + assign n1024 = 16'he444 >> { n603, n1026, n1025, n162 }; + assign n1025 = 8'h15 >> { n350, n145, n649 }; + assign n1026 = 16'h82ff >> { n96, i_12_, i_13_, i_15_ }; + assign o_37_ = 64'h7fffffffffffffff >> { n1385, n1367, n1370, n1275, n1382, n1364 }; + assign n1028 = 64'hc040d500c0408000 >> { n1029, n173, n1268, n898, n909, n198 }; + assign n1029 = 16'h2202 >> { n822, n149, n903, n905 }; + assign n1030 = 16'h0777 >> { n196, n309, n140, n132 }; + assign n1031 = 64'h0002020200ffffff >> { n132, n135, n866, n125, n611, n464 }; + assign n1032 = 64'h1313131313131357 >> { n749, n125, n287, n174, n196, n175 }; + assign n1033 = 64'h8dcd054505450545 >> { n897, n1269, n1034, n154, n959, n149 }; + assign n161 = 8'h02 >> { i_6_, i_8_, i_7_ }; + assign n1034 = 64'haa8a8a8a8a8a8a8a >> { i_12_, i_14_, n157, n924, n866, n145 }; + assign n1035 = 64'h22222222222222a2 >> { n711, n308, n542, n865, n196, n821 }; + assign n1036 = 32'd2290616456 >> { i_8_, n749, n207, n1038, n1037 }; + assign n1037 = 64'h00020003aaaaffff >> { n198, n207, n866, n778, n756, n823 }; + assign n1038 = 32'd16843025 >> { n562, n764, n132, n665, n252 }; + assign n1039 = 64'h888888888888a888 >> { i_12_, i_14_, i_13_, n176, n126, n174 }; + assign n1040 = 16'hee0e >> { n866, n924, n159, n205 }; + assign n1041 = 64'hff00fe00fe00fe00 >> { i_8_, n561, o_18_, n506, n435, n502 }; + assign n1042 = 64'habababababab00ab >> { n959, i_6_, n160, n196, n185, n869 }; + assign n1043 = 64'h2022002220200020 >> { n296, n1023, n149, n806, n1046, n1044 }; + assign n162 = 4'h8 >> { n103, n146 }; + assign n1044 = 16'h22a2 >> { n512, n597, n145, n1045 }; + assign n1045 = 32'd88425797 >> { i_8_, n303, n154, n958, n663 }; + assign n1046 = 32'd2863311522 >> { n470, n556, n231, n831, n186 }; + assign n1047 = 64'h0002020200222222 >> { n556, n196, n755, n162, n316, n1048 }; + assign n1048 = 64'h0057575757575757 >> { n93, n327, n326, n984, n174, n592 }; + assign n1049 = 64'h0001010100555555 >> { n174, n132, n422, n424, n130, n496 }; + assign n1050 = 64'h0515073707370737 >> { n80, n276, n592, n159, n783, n186 }; + assign n1051 = 16'h8808 >> { n296, n79, n590, n830 }; + assign n1052 = 64'h0000ddd0ddd0ddd0 >> { n337, n987, n279, n958, n143, n132 }; + assign n1053 = 32'd196852667 >> { n326, n161, n327, n987, n597 }; + assign n163 = 4'h8 >> { n160, n164 }; + assign n1054 = 64'h00011111000fffff >> { n122, n149, n119, n323, n196, n179 }; + assign n1055 = 64'h7707770700007707 >> { n576, n196, n909, n163, n473, n762 }; + assign n1056 = 64'h0057575757575757 >> { n164, n327, n498, n631, n471, n163 }; + assign n1057 = 16'ha888 >> { n124, i_14_, n360, n135 }; + assign n1058 = 64'h0040004450505555 >> { n149, n179, n389, n931, n928, n945 }; + assign n1059 = 32'd134776840 >> { n551, n807, n196, n944, n1060 }; + assign n1060 = 16'h222a >> { n149, n135, n559, n518 }; + assign n1061 = 64'h0015151515151515 >> { i_8_, n749, n207, n925, n926, n923 }; + assign n1062 = 16'h222a >> { n159, n145, n119, n1063 }; + assign n1063 = 64'h0008000808080008 >> { n236, n118, n132, n614, n1064, n1065 }; +endmodule diff --git a/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act b/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act new file mode 100644 index 000000000..4e3fc1b01 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act @@ -0,0 +1,1077 @@ +clock 0.502200 0.500200 +tin_pv10_4_4_ 0.504600 0.504200 +tin_pv11_4_4_ 0.497600 0.505800 +tin_pv6_7_7_ 0.497600 0.493200 +tin_pv2_0_0_ 0.502000 0.501600 +tin_pv10_3_3_ 0.501400 0.505000 +tin_pv1_2_2_ 0.515400 0.505800 +tin_pv11_3_3_ 0.494000 0.509600 +tin_pv4_3_3_ 0.495200 0.493600 +tin_pv10_2_2_ 0.494000 0.509400 +tin_pv11_2_2_ 0.501400 0.491600 +tin_pv6_0_0_ 0.503000 0.498800 +tin_pv2_1_1_ 0.494400 0.491000 +tin_pv10_1_1_ 0.495400 0.498400 +tin_pv1_3_3_ 0.496200 0.493200 +preset_0_0_ 0.499400 0.488800 +tin_pv11_1_1_ 0.502000 0.497400 +tin_pv4_4_4_ 0.513400 0.511000 +tin_pready_0_0_ 0.498400 0.492800 +tin_pv10_0_0_ 0.506000 0.497800 +tin_pv11_0_0_ 0.487600 0.501600 +tin_pv6_1_1_ 0.501800 0.501400 +tin_pv2_2_2_ 0.502200 0.497200 +tin_pv1_4_4_ 0.508000 0.492600 +tin_pv4_5_5_ 0.497800 0.502600 +tin_pv6_2_2_ 0.495000 0.487000 +tin_pv2_3_3_ 0.499400 0.504600 +tin_pv1_5_5_ 0.504600 0.497800 +tin_pv4_6_6_ 0.503400 0.498800 +tin_pv6_3_3_ 0.503400 0.510800 +tin_pv2_4_4_ 0.493800 0.497400 +tin_pv1_6_6_ 0.487800 0.501200 +tin_pv4_7_7_ 0.502000 0.489200 +tin_pv6_4_4_ 0.505800 0.503000 +tin_pv2_5_5_ 0.497800 0.509800 +tin_pv1_7_7_ 0.502000 0.509000 +tin_pv4_0_0_ 0.509400 0.492000 +tin_pv6_5_5_ 0.492600 0.499600 +tin_pv2_6_6_ 0.493600 0.504800 +tin_pv10_7_7_ 0.491600 0.504200 +tin_pv1_0_0_ 0.490200 0.507200 +tin_pv11_7_7_ 0.493800 0.500600 +tin_pv4_1_1_ 0.496400 0.506000 +tin_pv10_6_6_ 0.507200 0.502000 +tin_pv11_6_6_ 0.497800 0.483800 +tin_pv6_6_6_ 0.511200 0.490800 +tin_pv2_7_7_ 0.504200 0.504800 +preset 0.502200 0.503600 +tin_pv10_5_5_ 0.503000 0.502200 +tin_pv1_1_1_ 0.486600 0.494800 +tin_pv11_5_5_ 0.500000 0.491800 +tin_pv4_2_2_ 0.508000 0.503000 +pdn 0.149400 0.298800 +n_n4142 0.000000 0.000000 +n_n3936 0.002600 0.002400 +n_n3574 0.000600 0.000400 +n_n3008 0.000000 0.000000 +n_n3726 0.000200 0.000400 +n_n3604 0.001000 0.000800 +n_n3144 0.259800 0.261200 +n_n3782 0.259800 0.261200 +n_n3067 0.259800 0.261200 +n_n4258 0.007400 0.006400 +n_n3225 0.000000 0.000000 +n_n3180 0.259800 0.261200 +n_n3274 0.259800 0.261200 +n_n3475 0.000600 0.000800 +n_n3687 0.000000 0.000000 +n_n3381 0.259800 0.261200 +n_n3098 0.000000 0.000000 +n_n4108 0.259800 0.261200 +n_n3497 0.000000 0.000000 +n_n3793 0.000000 0.000000 +n_n4316 0.001400 0.001200 +n_n4349 0.015800 0.013200 +n_n3029 0.259800 0.261200 +n_n3619 0.259800 0.261200 +n_n3264 0.259800 0.261200 +n_n3780 0.000000 0.000000 +ndn3_4 0.163000 0.161400 +n_n4114 0.259800 0.261200 +n_n3146 0.259800 0.261200 +n_n3511 0.090000 0.086800 +n_n3152 0.259800 0.261200 +n_n3833 1.000000 0.000000 +n_n4282 0.259800 0.261200 +n_n3305 0.259800 0.261200 +n_n4392 0.000000 0.000000 +n_n4224 0.020400 0.020400 +n_n3198 0.000200 0.000400 +n_n3204 0.259800 0.261200 +n_n3024 0.259800 0.261200 +n_n4139 0.259800 0.261200 +ndn3_15 0.000000 0.000000 +n_n3133 0.000000 0.000000 +n_n4074 0.000000 0.000000 +n_n3270 0.000000 0.000000 +n_n3858 0.087200 0.088000 +n_n3456 0.259800 0.261200 +n_n3521 0.259800 0.261200 +n_n3081 0.259800 0.261200 +n_n4381 0.000400 0.000400 +n_n3670 0.000000 0.000000 +n_n4211 0.002200 0.002000 +n_n3493 0.000000 0.000000 +n_n3495 0.000000 0.000000 +n_n3916 0.001400 0.001200 +n_n3195 0.259800 0.261200 +n_n3525 0.000000 0.000000 +n_n3729 0.000000 0.000000 +n_n3876 0.007800 0.006800 +ndn3_5 0.082200 0.080200 +n_n3549 0.000000 0.000000 +n_n3489 0.259800 0.261200 +n_n3764 0.000000 0.000000 +n_n3281 0.039800 0.037800 +n_n3707 0.999800 0.000400 +n_n3517 0.000000 0.000000 +n_n4160 0.024400 0.020800 +n_n4222 0.001400 0.001200 +n_n3012 0.000000 0.000000 +n_n4071 0.009200 0.009200 +n_n3372 0.259800 0.261200 +n_n3344 0.000000 0.000000 +n_n3688 0.000000 0.000000 +n_n3079 0.000000 0.000000 +n_n3313 0.000000 0.000000 +n_n3411 0.259800 0.261200 +n_n3231 0.000000 0.000000 +n_n3396 0.259800 0.261200 +n_n3432 0.259800 0.261200 +n_n3606 0.259800 0.261200 +n_n3733 0.000000 0.000000 +n_n3556 0.003800 0.003600 +n_n4040 0.000600 0.000400 +n_n3120 0.259800 0.261200 +n_n3221 0.000000 0.000000 +n_n3173 0.000000 0.000000 +n_n3851 0.000600 0.000400 +n_n3113 0.000000 0.000000 +n_n3242 0.000000 0.000000 +n_n3118 0.000000 0.000000 +n_n3376 0.000000 0.000000 +n_n4089 0.259800 0.261200 +n_n3044 0.000000 0.000000 +n_n3627 0.000000 0.000000 +n_n3035 0.005000 0.004000 +n_n3111 0.000000 0.000000 +n_n3321 0.259800 0.261200 +n_n3443 0.259800 0.261200 +n_n3215 0.259800 0.261200 +ndn3_10 0.002200 0.001600 +n_n4172 0.000000 0.000000 +nlc1_2 0.275200 0.281000 +n_n3590 0.259800 0.261200 +n_n4110 0.259800 0.261200 +n_n3576 0.000000 0.000000 +n_n4129 0.259800 0.261200 +n_n4189 0.000000 0.000000 +n_n4286 0.000000 0.000000 +n_n4383 0.022000 0.017600 +n_n3567 0.259800 0.261200 +n_n3892 0.014600 0.012400 +n_n3075 0.259800 0.261200 +n_n3354 0.149400 0.298800 +n_n3465 0.000000 0.000000 +ndn3_6 0.042000 0.037600 +n_n3617 0.259800 0.261200 +n_n4162 0.259800 0.261200 +n_n3207 0.000000 0.000000 +n_n4120 0.259800 0.261200 +n_n3065 0.259800 0.261200 +n_n4005 0.259800 0.261200 +n_n3266 0.259800 0.261200 +n_n4337 0.009400 0.008800 +n_n3600 0.259800 0.261200 +n_n3415 0.259800 0.261200 +n_n4243 0.000000 0.000000 +n_n3872 0.259800 0.261200 +n_n3648 0.259800 0.261200 +n_n3358 0.000000 0.000000 +n_n3350 0.259800 0.261200 +ndn3_7 0.023200 0.020000 +n_n3116 0.259800 0.261200 +n_n3583 0.000000 0.000000 +n_n3906 0.000000 0.000000 +n_n4131 0.259800 0.261200 +n_n3316 0.000000 0.000000 +n_n3061 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+n1793_1 0.000000 0.000000 +n1798_1 0.259800 0.020166 +n1803_1 0.259800 0.020166 +n1808_1 0.000200 0.000200 +n1813_1 0.000000 0.000000 +n1818_1 0.000000 0.000000 +n1823_1 0.000000 0.000000 +n1828_1 0.000000 0.000000 +n1833_1 0.018800 0.052799 +n1838_1 0.026200 0.053223 +n1843_1 0.259800 0.020166 +n1848_1 0.259800 0.020166 +n1853_1 0.000000 0.000000 +n1858_1 0.000000 0.000000 +n1863_1 0.007200 0.055133 +n1868_1 0.000000 0.000001 +n1873_1 0.007200 0.000000 +n1878_1 0.090600 0.003553 +n1883_1 0.259800 0.020166 +n1888_1 0.001000 0.126311 +n1890 0.001000 0.000798 +n1893_1 0.259800 0.020166 +n1898_1 1.000000 0.000000 +n1903_1 1.000000 0.000000 +n1908_1 0.259800 0.020166 +n1913_1 0.000000 0.000000 +n1918_1 0.004800 0.051680 +n1923_1 0.003000 0.051987 +n1928_1 0.000000 0.000000 +n1933_1 0.000000 0.000000 +n1938_1 0.000000 0.000000 +n1943_1 0.259800 0.020166 +n1948_1 0.000000 0.000000 +n1953_1 0.006200 0.053971 +n1958_1 0.000000 0.000000 +n1963_1 0.000000 0.000000 +n1968_1 0.000000 0.000000 +n1973_1 0.000000 0.250613 +n1978_1 0.042400 0.045210 +n1983_1 0.037200 0.044470 +n1988_1 0.000000 0.000000 +n1993_1 0.000000 0.000331 +n1998_1 0.000000 0.000000 +n2003_1 0.000000 0.000000 +n2008_1 0.000000 0.000000 +n2013_1 0.000000 0.000001 +n2018_1 0.259800 0.020166 +n2023_1 0.259800 0.020166 +n2033_1 0.003200 0.053748 +n2038_1 0.000000 0.000000 +n2043_1 0.000000 0.000000 +n2048_1 0.259800 0.020166 +n2053_1 0.000000 0.000000 +n2063_1 0.000000 0.000000 +n2068_1 0.000000 0.250439 +n2073_1 0.259800 0.020166 +n2078_1 0.999800 0.000000 +n1927 0.963200 0.000000 +n2083_1 0.259800 0.020166 +n2088_1 0.000000 0.000000 +n2093_1 0.020200 0.049524 +n2098 0.002200 0.000001 +n2103_1 0.259800 0.020166 +n2108_1 0.000600 0.000001 +n2113_1 0.000000 0.000000 +n2118_1 0.000000 0.000000 +n2123_1 0.000000 0.000000 +n2128_1 0.000000 0.000000 +n2133_1 0.079600 0.003082 +n2138_1 0.039400 0.047861 +n2143_1 0.000800 0.126326 +n1941 0.000600 0.000798 +n2148_1 0.000400 0.126343 +n1943 0.000400 0.000002 +n2153_1 0.000000 0.000000 +n2158_1 0.001000 0.000000 +n2163_1 0.259800 0.020166 +n2168_1 0.000000 0.246259 +n2173_1 0.000000 0.000000 +n2178_1 0.000400 0.000551 +n1950 0.000200 0.001681 +n2183_1 0.259800 0.020166 +n2188_1 0.259800 0.020166 +n2193_1 0.259800 0.020166 +n2198_1 0.000000 0.000000 +n2203_1 0.000000 0.000000 +n2208_1 0.000000 0.000001 +n2213_1 0.000000 0.000000 +n2218_1 0.000000 0.000000 +n2223_1 0.259800 0.020166 +n2228_1 0.259800 0.020166 +n2233_1 0.259800 0.020166 +n2238_1 0.000200 0.000995 +n2243_1 0.000200 0.250538 +n2248_1 0.999800 0.000000 +n2253_1 0.837000 0.028814 diff --git a/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif b/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif new file mode 100644 index 000000000..2c2432805 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif @@ -0,0 +1,2605 @@ +# Benchmark "tseng" written by ABC on Tue Mar 12 09:44:40 2019 +.model tseng +.inputs clock tin_pv10_4_4_ tin_pv11_4_4_ tin_pv6_7_7_ tin_pv2_0_0_ \ + tin_pv10_3_3_ tin_pv1_2_2_ tin_pv11_3_3_ tin_pv4_3_3_ tin_pv10_2_2_ \ + tin_pv11_2_2_ tin_pv6_0_0_ tin_pv2_1_1_ tin_pv10_1_1_ tin_pv1_3_3_ \ + preset_0_0_ tin_pv11_1_1_ tin_pv4_4_4_ tin_pready_0_0_ tin_pv10_0_0_ \ + tin_pv11_0_0_ tin_pv6_1_1_ tin_pv2_2_2_ tin_pv1_4_4_ tin_pv4_5_5_ \ + tin_pv6_2_2_ tin_pv2_3_3_ tin_pv1_5_5_ tin_pv4_6_6_ tin_pv6_3_3_ \ + tin_pv2_4_4_ tin_pv1_6_6_ tin_pv4_7_7_ tin_pv6_4_4_ tin_pv2_5_5_ \ + tin_pv1_7_7_ tin_pv4_0_0_ tin_pv6_5_5_ tin_pv2_6_6_ tin_pv10_7_7_ \ + tin_pv1_0_0_ tin_pv11_7_7_ tin_pv4_1_1_ tin_pv10_6_6_ tin_pv11_6_6_ \ + tin_pv6_6_6_ tin_pv2_7_7_ preset tin_pv10_5_5_ tin_pv1_1_1_ tin_pv11_5_5_ \ + tin_pv4_2_2_ +.outputs pv14_2_2_ pv12_3_3_ pv10_4_4_ pv7_5_5_ pv3_6_6_ pv15_2_2_ \ + pv13_3_3_ pv11_4_4_ pv6_7_7_ pv2_0_0_ pv14_1_1_ pv12_2_2_ pv10_3_3_ \ + pv9_0_0_ pv5_1_1_ pv1_2_2_ pv15_1_1_ pv13_2_2_ pv11_3_3_ pv8_2_2_ pv4_3_3_ \ + pv14_0_0_ pv12_1_1_ pv10_2_2_ pv7_6_6_ pv3_7_7_ pv15_0_0_ pv13_1_1_ \ + pv11_2_2_ pv6_0_0_ pv2_1_1_ pv12_0_0_ pv10_1_1_ pv9_1_1_ pv5_2_2_ pv1_3_3_ \ + pv13_0_0_ pv11_1_1_ pv8_3_3_ pv4_4_4_ pready_0_0_ pv10_0_0_ pv7_7_7_ \ + pv3_0_0_ pv11_0_0_ pv6_1_1_ pv2_2_2_ pv9_2_2_ pv5_3_3_ pv1_4_4_ pv8_4_4_ \ + pv4_5_5_ pv7_0_0_ pv3_1_1_ pv6_2_2_ pv2_3_3_ pv9_3_3_ pv5_4_4_ pv1_5_5_ \ + pv8_5_5_ pv4_6_6_ pv7_1_1_ pv3_2_2_ pv6_3_3_ pv2_4_4_ pv9_4_4_ pv5_5_5_ \ + pv1_6_6_ pv8_6_6_ pv4_7_7_ pv7_2_2_ pv3_3_3_ pv6_4_4_ pv2_5_5_ pv14_7_7_ \ + pv9_5_5_ pv5_6_6_ pv1_7_7_ pv15_7_7_ pv8_7_7_ pv4_0_0_ pv14_6_6_ pv12_7_7_ \ + pv7_3_3_ pv3_4_4_ pv15_6_6_ pv13_7_7_ pv6_5_5_ pv2_6_6_ pdn pv14_5_5_ \ + pv12_6_6_ pv10_7_7_ pv9_6_6_ pv5_7_7_ pv1_0_0_ pv15_5_5_ pv13_6_6_ \ + pv11_7_7_ pv8_0_0_ pv4_1_1_ pv14_4_4_ pv12_5_5_ pv10_6_6_ pv7_4_4_ \ + pv3_5_5_ pv15_4_4_ pv13_5_5_ pv11_6_6_ pv6_6_6_ pv2_7_7_ pv14_3_3_ \ + pv12_4_4_ pv10_5_5_ pv9_7_7_ pv5_0_0_ pv1_1_1_ pv15_3_3_ pv13_4_4_ \ + pv11_5_5_ pv8_1_1_ pv4_2_2_ + +.latch n349_1 pdn re clock 0 +.latch n353 n_n4142 re clock 0 +.latch n358 n_n3936 re clock 0 +.latch n363 n_n3574 re clock 0 +.latch n368 n_n3008 re clock 0 +.latch n373 n_n3726 re clock 0 +.latch n378 n_n3604 re clock 0 +.latch n383 n_n3144 re clock 0 +.latch n388 n_n3782 re clock 0 +.latch n393 n_n3067 re clock 0 +.latch n398 n_n4258 re clock 0 +.latch n403 n_n3225 re clock 0 +.latch n408 n_n3180 re clock 0 +.latch n413 n_n3274 re clock 0 +.latch n418 n_n3475 re clock 0 +.latch n423 n_n3687 re clock 0 +.latch n428 n_n3381 re clock 0 +.latch n433 n_n3098 re clock 0 +.latch n438 n_n4108 re clock 0 +.latch n443 n_n3497 re clock 0 +.latch n448 n_n3793 re clock 0 +.latch n453 n_n4316 re clock 0 +.latch n458 n_n4349 re clock 0 +.latch n463 n_n3029 re clock 0 +.latch n468 n_n3619 re clock 0 +.latch n473 n_n3264 re clock 0 +.latch n478 n_n3780 re clock 0 +.latch n483 ndn3_4 re clock 0 +.latch n488 n_n4114 re clock 0 +.latch n493 n_n3146 re clock 0 +.latch n498 n_n3511 re clock 0 +.latch n503 n_n3152 re clock 0 +.latch n508 n_n3833 re clock 0 +.latch n513 n_n4282 re clock 0 +.latch n518 n_n3305 re clock 0 +.latch n523 n_n4392 re clock 0 +.latch n528 n_n4224 re clock 0 +.latch n533 n_n3198 re clock 0 +.latch n538 n_n3204 re clock 0 +.latch n543 n_n3024 re clock 0 +.latch n548 n_n4139 re clock 0 +.latch n553 ndn3_15 re clock 0 +.latch n558 n_n3133 re clock 0 +.latch n563 n_n4074 re clock 0 +.latch n568 n_n3270 re clock 0 +.latch n573 n_n3858 re clock 0 +.latch n578 n_n3456 re clock 0 +.latch n583 n_n3521 re clock 0 +.latch n588 n_n3081 re clock 0 +.latch n593 n_n4381 re clock 0 +.latch n598 n_n3670 re clock 0 +.latch n603 n_n4211 re clock 0 +.latch n608 n_n3493 re clock 0 +.latch n613 n_n3495 re clock 0 +.latch n618 n_n3916 re clock 0 +.latch n623 n_n3195 re clock 0 +.latch n628 n_n3525 re clock 0 +.latch n633 n_n3729 re clock 0 +.latch n638 n_n3876 re clock 0 +.latch n643 ndn3_5 re clock 0 +.latch n648 n_n3549 re clock 0 +.latch n653 n_n3489 re clock 0 +.latch n658 n_n3764 re clock 0 +.latch n663 n_n3281 re clock 0 +.latch n668 n_n3707 re clock 0 +.latch n673 n_n3517 re clock 0 +.latch n678 n_n4160 re clock 0 +.latch n683 n_n4222 re clock 0 +.latch n688 n_n3012 re clock 0 +.latch n693 n_n4071 re clock 0 +.latch n698 n_n3372 re clock 0 +.latch n703 n_n3344 re clock 0 +.latch n708 n_n3688 re clock 0 +.latch n713 n_n3079 re clock 0 +.latch n718 n_n3313 re clock 0 +.latch n723 n_n3411 re clock 0 +.latch n728 n_n3231 re clock 0 +.latch n733 n_n3396 re clock 0 +.latch n738 n_n3432 re clock 0 +.latch n743 n_n3606 re clock 0 +.latch n748 n_n3733 re clock 0 +.latch n753 n_n3556 re clock 0 +.latch n758 n_n4040 re clock 0 +.latch n763 n_n3120 re clock 0 +.latch n768 n_n3221 re clock 0 +.latch n773 n_n3173 re clock 0 +.latch n778 n_n3851 re clock 0 +.latch n783 n_n3113 re clock 0 +.latch n788 n_n3242 re clock 0 +.latch n793 n_n3118 re clock 0 +.latch n798 n_n3376 re clock 0 +.latch n803 n_n4089 re clock 0 +.latch n808 n_n3044 re clock 0 +.latch n813 n_n3627 re clock 0 +.latch n818 n_n3035 re clock 0 +.latch n823 n_n3111 re clock 0 +.latch n828 n_n3321 re clock 0 +.latch n833 n_n3443 re clock 0 +.latch n838 n_n3215 re clock 0 +.latch n843 ndn3_10 re clock 0 +.latch n848 n_n4172 re clock 0 +.latch n853 nlc1_2 re clock 0 +.latch n858 n_n3590 re clock 0 +.latch n863 n_n4110 re clock 0 +.latch n868 n_n3576 re clock 0 +.latch n873 n_n4129 re clock 0 +.latch n878 n_n4189 re clock 0 +.latch n883 n_n4286 re clock 0 +.latch n888 n_n4383 re clock 0 +.latch n893 n_n3567 re clock 0 +.latch n898_1 n_n3892 re clock 0 +.latch n903_1 n_n3075 re clock 0 +.latch n908_1 n_n3354 re clock 0 +.latch n913_1 n_n3465 re clock 0 +.latch n918_1 ndn3_6 re clock 0 +.latch n923_1 n_n3617 re clock 0 +.latch n928_1 n_n4162 re clock 0 +.latch n933_1 n_n3207 re clock 0 +.latch n938_1 n_n4120 re clock 0 +.latch n943_1 n_n3065 re clock 0 +.latch n948_1 n_n4005 re clock 0 +.latch n953_1 n_n3266 re clock 0 +.latch n958_1 n_n4337 re clock 0 +.latch n963_1 n_n3600 re clock 0 +.latch n968_1 n_n3415 re clock 0 +.latch n973_1 n_n4243 re clock 0 +.latch n978_1 n_n3872 re clock 0 +.latch n983_1 n_n3648 re clock 0 +.latch n988_1 n_n3358 re clock 0 +.latch n993_1 n_n3350 re clock 0 +.latch n998_1 ndn3_7 re clock 0 +.latch n1003_1 n_n3116 re clock 0 +.latch n1008_1 n_n3583 re clock 0 +.latch n1013_1 n_n3906 re clock 0 +.latch n1018_1 n_n4131 re clock 0 +.latch n1023_1 n_n3316 re clock 0 +.latch n1028_1 n_n3061 re clock 0 +.latch n1033_1 n_n3048 re clock 0 +.latch n1038_1 n_n3886 re clock 0 +.latch n1043_1 n_n3919 re clock 0 +.latch n1048_1 n_n3128 re clock 0 +.latch n1053_1 n_n3995 re clock 0 +.latch n1058_1 n_n4213 re clock 0 +.latch n1063_1 n_n3761 re clock 0 +.latch n1068_1 ndn3_8 re clock 0 +.latch n1073_1 n_n3252 re clock 0 +.latch n1078_1 n_n4366 re clock 0 +.latch n1083_1 n_n3328 re clock 0 +.latch n1088_1 n_n3988 re clock 0 +.latch n1093_1 n_n3348 re clock 0 +.latch n1098_1 n_n3544 re clock 0 +.latch n1103_1 n_n3101 re clock 0 +.latch n1108_1 n_n4279 re clock 0 +.latch n1113_1 n_n3896 re clock 0 +.latch n1118_1 n_n3736 re clock 0 +.latch n1123_1 n_n4251 re clock 0 +.latch n1128_1 n_n3650 re clock 0 +.latch n1133_1 n_n3307 re clock 0 +.latch n1138_1 n_n4294 re clock 0 +.latch n1143_1 n_n4334 re clock 0 +.latch n1148_1 n_n3955 re clock 0 +.latch n1153_1 n_n4164 re clock 0 +.latch n1158_1 n_n3155 re clock 0 +.latch n1163_1 n_n3749 re clock 0 +.latch n1168_1 n_n4233 re clock 0 +.latch n1173_1 n_n4347 re clock 0 +.latch n1178_1 n_n3826 re clock 0 +.latch n1183_1 n_n3360 re clock 0 +.latch n1188_1 n_n3458 re clock 0 +.latch n1193_1 n_n3093 re clock 0 +.latch n1198_1 n_n3157 re clock 0 +.latch n1203_1 n_n3506 re clock 0 +.latch n1208_1 n_n3161 re clock 0 +.latch n1213_1 n_n3319 re clock 0 +.latch n1218_1 n_n3429 re clock 0 +.latch n1223_1 n_n3971 re clock 0 +.latch n1228_1 n_n3449 re clock 0 +.latch n1233_1 n_n4270 re clock 0 +.latch n1238_1 n_n4288 re clock 0 +.latch n1243_1 n_n3183 re clock 0 +.latch n1248_1 n_n3130 re clock 0 +.latch n1253_1 n_n4047 re clock 0 +.latch n1258 n_n3978 re clock 0 +.latch n1263_1 n_n3239 re clock 0 +.latch n1268_1 n_n4145 re clock 0 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n_n3408 re clock 0 +.latch n1418_1 n_n4229 re clock 0 +.latch n1423_1 n_n4201 re clock 0 +.latch n1428_1 n_n3339 re clock 0 +.latch n1433_1 n_n4362 re clock 0 +.latch n1438_1 n_n3483 re clock 0 +.latch n1443_1 n_n3557 re clock 0 +.latch n1448_1 n_n4185 re clock 0 +.latch n1453_1 n_n3069 re clock 0 +.latch n1458_1 n_n3643 re clock 0 +.latch n1463_1 n_n3404 re clock 0 +.latch n1468_1 n_n3057 re clock 0 +.latch n1473_1 n_n3020 re clock 0 +.latch n1478_1 n_n3828 re clock 0 +.latch n1483_1 n_n3631 re clock 0 +.latch n1488_1 n_n3138 re clock 0 +.latch n1493_1 nsr1_2 re clock 0 +.latch n1498_1 n_n4065 re clock 0 +.latch n1503_1 n_n3679 re clock 0 +.latch n1508_1 n_n3287 re clock 0 +.latch n1513_1 n_n4351 re clock 0 +.latch n1518_1 n_n4059 re clock 0 +.latch n1523_1 n_n3436 re clock 0 +.latch n1528_1 nen3_10 re clock 0 +.latch n1533_1 n_n3461 re clock 0 +.latch n1538_1 n_n4012 re clock 0 +.latch n1543_1 n_n3051 re clock 0 +.latch n1548_1 n_n3073 re clock 0 +.latch n1553_1 n_n3777 re clock 0 +.latch n1558_1 n_n3709 re clock 0 +.latch n1563_1 n_n3946 re clock 0 +.latch n1568_1 n_n3085 re clock 0 +.latch n1573_1 n_n3259 re clock 0 +.latch n1578_1 n_n3504 re clock 0 +.latch n1583_1 n_n4045 re clock 0 +.latch n1588_1 n_n3954 re clock 0 +.latch n1593_1 n_n3136 re clock 0 +.latch n1598_1 n_n4372 re clock 0 +.latch n1603_1 n_n4236 re clock 0 +.latch n1608_1 n_n3040 re clock 0 +.latch n1613_1 n_n3874 re clock 0 +.latch n1618_1 n_n3999 re clock 0 +.latch n1623_1 n_n3223 re clock 0 +.latch n1628_1 ndn1_34 re clock 0 +.latch n1633_1 n_n3743 re clock 0 +.latch n1638_1 n_n3657 re clock 0 +.latch n1643_1 n_n3213 re clock 0 +.latch n1648_1 n_n3095 re clock 0 +.latch n1653_1 n_n3663 re clock 0 +.latch n1658_1 n_n3724 re clock 0 +.latch n1663_1 n_n3038 re clock 0 +.latch n1668_1 n_n3370 re clock 0 +.latch n1673_1 n_n3624 re clock 0 +.latch n1678_1 n_n3578 re clock 0 +.latch n1683_1 n_n3713 re clock 0 +.latch n1688_1 n_n3089 re clock 0 +.latch n1693_1 n_n3211 re clock 0 +.latch n1698_1 n_n3367 re clock 0 +.latch n1703_1 n_n3434 re clock 0 +.latch n1708_1 n_n3126 re clock 0 +.latch n1713_1 n_n4192 re clock 0 +.latch n1718_1 n_n4136 re clock 0 +.latch n1723_1 n_n3053 re clock 0 +.latch n1728_1 n_n3938 re clock 0 +.latch n1733_1 n_n3769 re clock 0 +.latch n1738_1 n_n4390 re clock 0 +.latch n1743_1 nsr3_17 re clock 0 +.latch n1748_1 n_n3903 re clock 0 +.latch n1753_1 n_n3658 re clock 0 +.latch n1758_1 nrq3_11 re clock 0 +.latch n1763_1 n_n3818 re clock 0 +.latch n1768_1 n_n3533 re clock 0 +.latch n1773_1 n_n3463 re clock 0 +.latch n1778_1 n_n3175 re clock 0 +.latch n1783_1 n_n3055 re clock 0 +.latch n1788_1 n_n3202 re clock 0 +.latch n1793_1 n_n3385 re clock 0 +.latch n1798_1 n_n4077 re clock 0 +.latch n1803_1 n_n3142 re clock 0 +.latch n1808_1 n_n3901 re clock 0 +.latch n1813_1 n_n3934 re clock 0 +.latch n1818_1 n_n3823 re clock 0 +.latch n1823_1 n_n3722 re clock 0 +.latch n1828_1 n_n4309 re clock 0 +.latch n1833_1 n_n4159 re clock 0 +.latch n1838_1 n_n4330 re clock 0 +.latch n1843_1 n_n3836 re clock 0 +.latch n1848_1 n_n3470 re clock 0 +.latch n1853_1 n_n3331 re clock 0 +.latch n1858_1 n_n3883 re clock 0 +.latch n1863_1 n_n4299 re clock 0 +.latch n1868_1 n_n4157 re clock 0 +.latch n1873_1 ndn3_9 re clock 0 +.latch n1878_1 n_n3208 re clock 0 +.latch n1883_1 n_n3190 re clock 0 +.latch n1888_1 n_n4029 re clock 0 +.latch n1893_1 n_n3042 re clock 0 +.latch n1898_1 nsr3_14 re clock 0 +.latch n1903_1 n_n4151 re clock 0 +.latch n1908_1 n_n3188 re clock 0 +.latch n1913_1 n_n4303 re clock 0 +.latch n1918_1 n_n3250 re clock 0 +.latch n1923_1 n_n3170 re clock 0 +.latch n1928_1 n_n3758 re clock 0 +.latch n1933_1 n_n3910 re clock 0 +.latch n1938_1 n_n3108 re clock 0 +.latch n1943_1 n_n3150 re clock 0 +.latch n1948_1 n_n4320 re clock 0 +.latch n1953_1 n_n4360 re clock 0 +.latch n1958_1 n_n4247 re clock 0 +.latch n1963_1 n_n4199 re clock 0 +.latch n1968_1 n_n3966 re clock 0 +.latch n1973_1 n_n3766 re clock 0 +.latch n1978_1 n_n4021 re clock 0 +.latch n1983_1 n_n4062 re clock 0 +.latch n1988_1 n_n3514 re clock 0 +.latch n1993_1 n_n3572 re clock 0 +.latch n1998_1 n_n4166 re clock 0 +.latch n2003_1 n_n3976 re clock 0 +.latch n2008_1 n_n3394 re clock 0 +.latch n2013_1 n_n4095 re clock 0 +.latch n2018_1 n_n3863 re clock 0 +.latch n2023_1 n_n3720 re clock 0 +.latch n2028_1 ngfdn_3 re clock 0 +.latch n2033_1 n_n3756 re clock 0 +.latch n2038_1 n_n3667 re clock 0 +.latch n2043_1 n_n3342 re clock 0 +.latch n2048_1 n_n3529 re clock 0 +.latch n2053_1 n_n4209 re clock 0 +.latch n2058_1 n_n4324 re clock 0 +.latch n2063_1 n_n3337 re clock 0 +.latch n2068_1 n_n4227 re clock 0 +.latch n2073_1 n_n4153 re clock 0 +.latch n2078_1 n_n3831 re clock 0 +.latch n2083_1 n_n3233 re clock 0 +.latch n2088_1 n_n3413 re clock 0 +.latch n2093_1 n_n4182 re clock 0 +.latch n2098 n_n3841 re clock 0 +.latch n2103_1 n_n3441 re clock 0 +.latch n2108_1 n_n4026 re clock 0 +.latch n2113_1 n_n4342 re clock 0 +.latch n2118_1 n_n4102 re clock 0 +.latch n2123_1 n_n3277 re clock 0 +.latch n2128_1 n_n4180 re clock 0 +.latch n2133_1 n_n3878 re clock 0 +.latch n2138_1 n_n3931 re clock 0 +.latch n2143_1 n_n3845 re clock 0 +.latch n2148_1 n_n3865 re clock 0 +.latch n2153_1 n_n3486 re clock 0 +.latch n2158_1 n_n4056 re clock 0 +.latch n2163_1 n_n3674 re clock 0 +.latch n2168_1 n_n3959 re clock 0 +.latch n2173_1 n_n3608 re clock 0 +.latch n2178_1 n_n4080 re clock 0 +.latch n2183_1 n_n4018 re clock 0 +.latch n2188_1 n_n4354 re clock 0 +.latch n2193_1 n_n3797 re clock 0 +.latch n2198_1 n_n3739 re clock 0 +.latch n2203_1 n_n3646 re clock 0 +.latch n2208_1 n_n3099 re clock 0 +.latch n2213_1 n_n3537 re clock 0 +.latch n2218_1 n_n3806 re clock 0 +.latch n2223_1 n_n3087 re clock 0 +.latch n2228_1 n_n4105 re clock 0 +.latch n2233_1 n_n3262 re clock 0 +.latch n2238_1 n_n4125 re clock 0 +.latch n2243_1 n_n3814 re clock 0 +.latch n2248_1 n_n4093 re clock 0 +.latch n2253_1 nsr3_3 re clock 0 + +.names n_n3042 tin_pv10_4_4_ n_n4136 pv10_4_4_ +01- 1 +1-1 1 +.names n_n4120 tin_pv11_4_4_ n_n3966 pv11_4_4_ +01- 1 +1-1 1 +.names n_n4164 tin_pv6_7_7_ n_n3370 pv6_7_7_ +01- 1 +1-1 1 +.names n_n3211 tin_pv2_0_0_ n_n3910 pv2_0_0_ +01- 1 +1-1 1 +.names n_n4129 tin_pv10_3_3_ n_n3213 pv10_3_3_ +01- 1 +1-1 1 +.names n_n3470 tin_pv1_2_2_ n_n3537 pv1_2_2_ +01- 1 +1-1 1 +.names n_n3432 tin_pv11_3_3_ n_n3583 pv11_3_3_ +01- 1 +1-1 1 +.names n_n3489 tin_pv4_3_3_ n_n4309 pv4_3_3_ +01- 1 +1-1 1 +.names n_n3065 tin_pv10_2_2_ n_n3549 pv10_2_2_ +01- 1 +1-1 1 +.names n_n3152 tin_pv11_2_2_ n_n3823 pv11_2_2_ +01- 1 +1-1 1 +.names n_n3029 tin_pv6_0_0_ n_n3506 pv6_0_0_ +01- 1 +1-1 1 +.names n_n3999 tin_pv2_1_1_ n_n3646 pv2_1_1_ +01- 1 +1-1 1 +.names n_n3872 tin_pv10_1_1_ n_n3270 pv10_1_1_ +01- 1 +1-1 1 +.names n_n3441 tin_pv1_3_3_ n_n4180 pv1_3_3_ +01- 1 +1-1 1 +.names n_n4185 tin_pv11_1_1_ n_n4142 pv11_1_1_ +01- 1 +1-1 1 +.names n_n4110 tin_pv4_4_4_ n_n3627 pv4_4_4_ +01- 1 +1-1 1 +.names n_n4108 tin_pready_0_0_ n_n3354 pready_0_0_ +01- 1 +1-1 1 +.names n_n4282 tin_pv10_0_0_ n_n4209 pv10_0_0_ +01- 1 +1-1 1 +.names n_n3233 tin_pv11_0_0_ n_n3514 pv11_0_0_ +01- 1 +1-1 1 +.names n_n3144 tin_pv6_1_1_ n_n3952 pv6_1_1_ +01- 1 +1-1 1 +.names n_n4354 tin_pv2_2_2_ n_n3202 pv2_2_2_ +01- 1 +1-1 1 +.names n_n3863 tin_pv1_4_4_ n_n3806 pv1_4_4_ +01- 1 +1-1 1 +.names n_n3087 tin_pv4_5_5_ n_n3733 pv4_5_5_ +01- 1 +1-1 1 +.names n_n3307 tin_pv6_2_2_ n_n3138 pv6_2_2_ +01- 1 +1-1 1 +.names n_n3874 tin_pv2_3_3_ n_n3465 pv2_3_3_ +01- 1 +1-1 1 +.names n_n3101 tin_pv1_5_5_ n_n3313 pv1_5_5_ +01- 1 +1-1 1 +.names n_n3774 tin_pv4_6_6_ n_n3413 pv4_6_6_ +01- 1 +1-1 1 +.names n_n3204 tin_pv6_3_3_ n_n3486 pv6_3_3_ +01- 1 +1-1 1 +.names n_n3643 tin_pv2_4_4_ n_n3133 pv2_4_4_ +01- 1 +1-1 1 +.names n_n4018 tin_pv1_6_6_ n_n3118 pv1_6_6_ +01- 1 +1-1 1 +.names n_n4114 tin_pv4_7_7_ n_n4166 pv4_7_7_ +01- 1 +1-1 1 +.names n_n3093 tin_pv6_4_4_ n_n4065 pv6_4_4_ +01- 1 +1-1 1 +.names n_n4059 tin_pv2_5_5_ n_n3780 pv2_5_5_ +01- 1 +1-1 1 +.names n_n3544 tin_pv1_7_7_ n_n4199 pv1_7_7_ +01- 1 +1-1 1 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n1428_1 +01- 1 +0-1 1 +.names n1517 preset pv10_5_5_ n_n4362 n1433_1 +00-1 1 +101- 1 +.names n1388 n_n3483 n1799 n1414 n1412 n1438_1 +10111 1 +110-- 1 +11-0- 1 +11--0 1 +.names n_n4334 n1503 n_n4012 n1799 +10- 1 +1-1 1 +.names n1789 preset n1443_1 +10 1 +.names preset n1497 n_n4185 n1448_1 +01- 1 +0-1 1 +.names n1496 n_n3069 n1494 n_n3934 n1380 n1453_1 +11--- 1 +--110 1 +.names preset n1497 n_n3643 n1458_1 +01- 1 +0-1 1 +.names n_n3404 n1496 n1494 n_n4229 n1463_1 +11-- 1 +--11 1 +.names n_n3057 n1496 n1494 n_n4145 n1468_1 +11-- 1 +--11 1 +.names n1494 n1496 n_n3020 n_n4095 n_n4122 n_n3556 n1473_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names preset n1497 n_n3828 n1478_1 +01- 1 +0-1 1 +.names n1496 n_n3631 n1494 n_n3250 n_n3085 n1483_1 +11--- 1 +--111 1 +.names n_n3138 n1496 n_n3968 n1494 n1488_1 +11-- 1 +--11 1 +.names preset pdn n1498 ngfdn_3 n1493_1 +000- 0 +00-1 0 +.names n_n4065 n1496 n_n3922 n1494 n1498_1 +11-- 1 +--11 1 +.names n1496 n_n3679 n1494 n_n4366 n1380 n1503_1 +11--- 1 +--110 1 +.names n_n3287 n1496 n1494 n1406 n1508_1 +11-- 1 +--10 1 +.names n1533 preset n1794 n_n4351 n1513_1 +00-1 1 +101- 1 +.names preset n1497 n_n4059 n1518_1 +01- 1 +0-1 1 +.names n_n3436 n1496 n1494 n_n3898 n1523_1 +11-- 1 +--11 1 +.names ngfdn_3 preset nen3_10 ndn3_9 n1528_1 +001- 1 +00-1 1 +.names preset n1497 n_n3461 n1533_1 +01- 1 +0-1 1 +.names n1388 n_n4012 n1412 n1414 n1538_1 +1011 1 +110- 1 +11-0 1 +.names preset n1497 n_n3051 n1543_1 +01- 1 +0-1 1 +.names n1496 n_n3073 n1494 n_n4047 n1380 n1548_1 +11--- 1 +--110 1 +.names n_n3777 n1496 n1494 n_n3898 n1553_1 +11-- 1 +--11 1 +.names n_n3707 preset n1416 n_n3709 n1567 n1558_1 +101-- 1 +10-10 1 +.names n1517 preset pv10_2_2_ n_n3946 n1563_1 +00-1 1 +101- 1 +.names n1532 preset n1794 n_n3085 n1568_1 +00-1 1 +101- 1 +.names n_n3259 n1555 n1556 pv1_7_7_ n1573_1 +11-- 1 +--11 1 +.names preset n1497 n_n3504 n1578_1 +01- 1 +0-1 1 +.names n1379 preset n1788 n1583_1 +100 0 +.names n_n3954 preset n1594 n_n4349 n1596 n1384 n1588_1 +0-1--- 0 +10---1 0 +-0-10- 0 +.names n1496 n_n3136 n1494 n_n4324 n1380 n1593_1 +11--- 1 +--110 1 +.names n_n4372 n1496 n_n4383 n1494 n1598_1 +11-- 1 +--11 1 +.names n_n4236 n1496 n1494 n1408 n1603_1 +11-- 1 +--10 1 +.names preset n1497 n_n3040 n1608_1 +01- 1 +0-1 1 +.names preset n1497 n_n3874 n1613_1 +01- 1 +0-1 1 +.names preset n1497 n_n3999 n1618_1 +01- 1 +0-1 1 +.names n_n3223 n1496 n_n4122 n1494 n1623_1 +11-- 1 +--11 1 +.names ndn1_34 pdn preset n1628_1 +100 1 +.names n1517 preset pv10_1_1_ n_n3743 n1633_1 +00-1 1 +101- 1 +.names n1532 preset n1528 n_n3657 n1638_1 +00-1 1 +100- 1 +.names n_n3213 n1496 n_n4258 n1494 n1643_1 +11-- 1 +--11 1 +.names preset n1497 n_n3095 n1648_1 +01- 1 +0-1 1 +.names preset n1497 n_n3663 n1653_1 +01- 1 +0-1 1 +.names preset n1497 n_n3038 n1663_1 +01- 1 +0-1 1 +.names n_n3370 n1496 n_n4337 n1494 n1668_1 +11-- 1 +--11 1 +.names n1500 preset pv11_0_0_ n_n3624 n1673_1 +00-1 1 +101- 1 +.names n1500 preset pv11_4_4_ n_n3578 n1678_1 +00-1 1 +101- 1 +.names n1496 n_n3713 n1494 n_n4122 n_n3556 n1683_1 +11--- 1 +--111 1 +.names n1496 n_n3089 n1494 n_n4074 n_n3578 n1688_1 +11--- 1 +--111 1 +.names preset n1497 n_n3211 n1693_1 +01- 1 +0-1 1 +.names preset n1497 n_n3367 n1698_1 +01- 1 +0-1 1 +.names preset n1497 n_n3434 n1703_1 +01- 1 +0-1 1 +.names n1494 n1496 n_n3126 n_n4233 n_n3170 n_n3242 n1708_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names n1496 n_n4192 n1494 n_n3688 n_n3624 n1713_1 +11--- 1 +--111 1 +.names n_n4136 n1496 n_n3876 n1494 n1718_1 +11-- 1 +--11 1 +.names preset n1497 n_n3053 n1723_1 +01- 1 +0-1 1 +.names preset n1497 n_n3938 n1728_1 +01- 1 +0-1 1 +.names n_n3769 n1385 n_n4229 n1376 n1378 n1733_1 +0101- 1 +0110- 1 +1100- 1 +1111- 1 +1---1 1 +.names n1496 n_n4390 n1494 n_n3099 n_n3936 n1738_1 +11--- 1 +--111 1 +.names pdn preset nen3_10 nsr3_17 n1389 n1411 n1743_1 +001-0- 0 +001--1 0 +00-0-- 0 +.names preset n1497 n_n3903 n1748_1 +01- 1 +0-1 1 +.names n_n4045 preset n_n3658 n1383 n1512 n_n3604 n1753_1 +1010-- 1 +101--1 1 +10-11- 1 +.names preset ngfdn_3 nsr3_14 nrq3_11 n1758_1 +000- 1 +00-1 1 +.names n1416 preset n1864 n_n4258 n_n3818 n1414 n1763_1 +00--10 1 +10-1-- 1 +--1--- 1 +.names n1503 n_n3818 n1510 n1408 n1864 +1001 1 +1010 1 +1100 1 +1111 1 +.names n1545 preset pv6_3_3_ n_n3533 n1768_1 +00-1 1 +101- 1 +.names n_n3463 n1496 n1494 n_n4316 n1773_1 +11-- 1 +--11 1 +.names preset n1497 n_n3175 n1778_1 +01- 1 +0-1 1 +.names n_n3055 n1496 n_n3657 n1494 n1783_1 +11-- 1 +--11 1 +.names n1494 n1496 n_n3202 n_n3495 n_n4211 n_n3657 n1788_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names n1494 n1496 n_n3385 n_n4095 n_n4122 n_n3556 n1793_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names preset n1497 n_n4077 n1798_1 +01- 1 +0-1 1 +.names preset n1497 n_n3142 n1803_1 +01- 1 +0-1 1 +.names n_n3901 n1385 n_n4316 n1377 n1378 n1808_1 +0100- 1 +0111- 1 +1101- 1 +1110- 1 +1---1 1 +.names n_n3934 n1384 n_n3976 preset n1378 n1813_1 +0110- 1 +1100- 1 +1---1 1 +.names n1496 n_n3823 n_n4227 n1492 n1495 n1818_1 +11--- 1 +--110 1 +.names n_n3722 n1496 n_n4160 n1494 n1823_1 +11-- 1 +--11 1 +.names n_n4309 n1496 n_n4182 n1494 n1828_1 +11-- 1 +--11 1 +.names n1565 preset pv4_0_0_ n_n4159 n1833_1 +00-1 1 +101- 1 +.names n1565 preset pv4_4_4_ n_n4330 n1838_1 +00-1 1 +101- 1 +.names preset n1497 n_n3836 n1843_1 +01- 1 +0-1 1 +.names preset n1497 n_n3470 n1848_1 +01- 1 +0-1 1 +.names n_n3331 n1496 n_n4157 n1494 n1853_1 +11-- 1 +--11 1 +.names n_n3883 n1496 n_n3099 n1494 n1858_1 +11-- 1 +--11 1 +.names n1517 preset pv10_6_6_ n_n4299 n1863_1 +00-1 1 +101- 1 +.names n1532 preset n1750 n_n4157 n1868_1 +00-1 1 +101- 1 +.names ngfdn_3 preset ndn3_8 ndn3_9 n1873_1 +001- 1 +00-1 1 +.names n_n3208 n1555 n1556 pv1_1_1_ n1878_1 +11-- 1 +--11 1 +.names preset n1497 n_n3190 n1883_1 +01- 1 +0-1 1 +.names preset n1594 n_n4029 n1890 n_n3533 n1596 n1888_1 +0--1-- 1 +0---10 1 +-11--- 1 +.names n1384 n_n4029 n_n3954 n_n3955 n_n3845 n1890 +10100 1 +110-- 1 +11-1- 1 +11--1 1 +.names preset n1497 n_n3042 n1893_1 +01- 1 +0-1 1 +.names pdn preset nsr3_17 nsr3_14 n1380 n_n4045 n1898_1 +000-1- 0 +000--0 0 +00-0-- 0 +.names preset n_n4151 nsr1_2 nlc1_2 preset_0_0_ n1903_1 +1---- 1 +-1--- 1 +--100 1 +.names preset n1497 n_n3188 n1908_1 +01- 1 +0-1 1 +.names n1496 n_n4303 n1494 n_n3769 n1380 n1913_1 +11--- 1 +--110 1 +.names n1500 preset pv11_3_3_ n_n3250 n1918_1 +00-1 1 +101- 1 +.names n1500 preset pv11_7_7_ n_n3170 n1923_1 +00-1 1 +101- 1 +.names n_n3758 n1496 n1494 n_n3916 n1928_1 +11-- 1 +--11 1 +.names n1494 n1496 n_n3910 n_n3608 n_n3688 n_n3624 n1933_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names n1494 n1496 n_n3108 n_n4392 n_n3099 n_n3936 n1938_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names preset n1497 n_n3150 n1943_1 +01- 1 +0-1 1 +.names n_n4320 n1496 n_n3688 n1494 n1948_1 +11-- 1 +--11 1 +.names n1517 preset pv10_7_7_ n_n4360 n1953_1 +00-1 1 +101- 1 +.names n_n4247 n1496 n_n4362 n1494 n1958_1 +11-- 1 +--11 1 +.names n1496 n_n4199 n1494 n_n3170 n_n3242 n1963_1 +11--- 1 +--111 1 +.names n1496 n_n3966 n_n4275 n1492 n1495 n1968_1 +11--- 1 +--110 1 +.names n_n3766 preset n1413 n1414 n1416 n1973_1 +0011- 1 +100-0 1 +10-00 1 +.names n1614 preset pv2_4_4_ n_n4021 n1978_1 +00-1 1 +101- 1 +.names n1614 preset pv2_6_6_ n_n4062 n1983_1 +00-1 1 +101- 1 +.names n1496 n_n3514 n_n3814 n1492 n1495 n1988_1 +11--- 1 +--110 1 +.names n_n3572 n1496 n1494 n1407 n1993_1 +11-- 1 +--10 1 +.names n_n4166 n1496 n_n4270 n1494 n1998_1 +11-- 1 +--11 1 +.names n1531 preset n1626 n_n3976 n2003_1 +00-1 1 +101- 1 +.names n_n3394 n1496 n1494 n_n3841 n2008_1 +11-- 1 +--11 1 +.names n1533 preset n1757 n1758 n_n4095 n2013_1 +00--1 1 +1000- 1 +1011- 1 +.names preset n1497 n_n3863 n2018_1 +01- 1 +0-1 1 +.names preset n1497 n_n3720 n2023_1 +01- 1 +0-1 1 +.names n1517 preset pv10_0_0_ n_n3756 n2033_1 +00-1 1 +101- 1 +.names n1494 n1496 n_n3667 n_n3458 n_n4074 n_n3578 n2038_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names n_n3342 n1496 n_n4299 n1494 n2043_1 +11-- 1 +--11 1 +.names preset n1497 n_n3529 n2048_1 +01- 1 +0-1 1 +.names n_n4209 n1496 n_n3756 n1494 n2053_1 +11-- 1 +--11 1 +.names n1496 n_n3337 n1494 n_n4157 n_n3035 n2063_1 +11--- 1 +--111 1 +.names n1414 n_n4227 preset n_n3724 n_n3814 n1416 n2068_1 +010--0 1 +10011- 1 +1100-- 1 +110-0- 1 +.names preset n1497 n_n4153 n2073_1 +01- 1 +0-1 1 +.names n1616 n1927 n1642 n_n3831 n2078_1 +101- 0 +10-0 0 +.names n_n3831 n1617 n1495 n1927 +110 1 +.names preset n1497 n_n3233 n2083_1 +01- 1 +0-1 1 +.names n_n3413 n1496 n_n4251 n1494 n2088_1 +11-- 1 +--11 1 +.names n1565 preset pv4_3_3_ n_n4182 n2093_1 +00-1 1 +101- 1 +.names n1531 preset n1645 n_n3841 n2098 +00-1 1 +101- 1 +.names preset n1497 n_n3441 n2103_1 +01- 1 +0-1 1 +.names n1616 n_n4026 n_n3831 n1559 n2108_1 +11-- 1 +1-11 1 +.names n_n4342 n1496 n1494 n_n4229 n2113_1 +11-- 1 +--11 1 +.names n_n4102 n1496 n1494 n_n3841 n2118_1 +11-- 1 +--11 1 +.names n1494 n1496 n_n3277 n_n4288 n_n4157 n_n3035 n2123_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names n1496 n_n4180 n1494 n_n3250 n_n3085 n2128_1 +11--- 1 +--111 1 +.names n_n3878 n1555 n1556 pv1_0_0_ n2133_1 +11-- 1 +--11 1 +.names n1614 preset pv2_0_0_ n_n3931 n2138_1 +00-1 1 +101- 1 +.names preset n1594 n_n3845 n1941 n_n3968 n1596 n2143_1 +0--1-- 1 +0---10 1 +-11--- 1 +.names n1384 n_n3845 n_n3954 n_n3955 n1941 +1010 1 +110- 1 +11-1 1 +.names preset n1594 n_n3865 n1943 n_n3922 n1596 n2148_1 +0--1-- 1 +0---10 1 +-11--- 1 +.names n1384 n_n3865 n_n3954 n1599 n1943 +1011 1 +110- 1 +11-0 1 +.names n_n3486 n1496 n_n3533 n1494 n2153_1 +11-- 1 +--11 1 +.names n1788 preset n1379 n_n4056 n2158_1 +101- 1 +10-1 1 +.names preset n1497 n_n3674 n2163_1 +01- 1 +0-1 1 +.names preset n1414 n_n3959 n1407 n1416 n_n3756 n2168_1 +001-0- 1 +0100-- 1 +0111-- 1 +0---11 1 +.names n1533 preset n1626 n_n3608 n2173_1 +00-1 1 +101- 1 +.names n1416 preset n1950 n_n4299 n_n4080 n1414 n2178_1 +00--10 1 +10-1-- 1 +--1--- 1 +.names n1503 n_n4080 n1398 n_n3988 n1509 n1399 n1950 +10000- 1 +1000-0 1 +100-00 1 +10111- 1 +1011-1 1 +101-11 1 +11011- 1 +1101-1 1 +110-11 1 +11100- 1 +1110-0 1 +111-00 1 +.names preset n1497 n_n4018 n2183_1 +01- 1 +0-1 1 +.names preset n1497 n_n4354 n2188_1 +01- 1 +0-1 1 +.names preset n1497 n_n3797 n2193_1 +01- 1 +0-1 1 +.names n_n3739 n1496 n1494 n_n4316 n2198_1 +11-- 1 +--11 1 +.names n1494 n1496 n_n3646 n_n4392 n_n3099 n_n3936 n2203_1 +1--1-- 1 +1---11 1 +-11--- 1 +.names n1532 preset n1563 n_n3099 n2208_1 +00-1 1 +101- 1 +.names n1496 n_n3537 n1494 n_n4211 n_n3657 n2213_1 +11--- 1 +--111 1 +.names n1496 n_n3806 n1494 n_n4074 n_n3578 n2218_1 +11--- 1 +--111 1 +.names preset n1497 n_n3087 n2223_1 +01- 1 +0-1 1 +.names preset n1497 n_n4105 n2228_1 +01- 1 +0-1 1 +.names preset n1497 n_n3262 n2233_1 +01- 1 +0-1 1 +.names n_n4125 n1385 n_n4222 n_n3934 n_n3976 n1378 n2238_1 +01011- 1 +0110-- 1 +011-0- 1 +1100-- 1 +110-0- 1 +11111- 1 +1----1 1 +.names n_n3814 n1503 n1388 n2243_1 +01- 1 +101 1 +.names n1642 preset n1927 n2248_1 +100 0 +.names preset pdn n1551 n1498 nsr4_2 n2253_1 +000-- 0 +00-10 0 +.end diff --git a/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v b/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v new file mode 100644 index 000000000..302fb9924 --- /dev/null +++ b/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v @@ -0,0 +1,2871 @@ +/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ + +module tseng(clock, tin_pv10_4_4_, tin_pv11_4_4_, tin_pv6_7_7_, tin_pv2_0_0_, tin_pv10_3_3_, tin_pv1_2_2_, tin_pv11_3_3_, tin_pv4_3_3_, tin_pv10_2_2_, tin_pv11_2_2_, tin_pv6_0_0_, tin_pv2_1_1_, tin_pv10_1_1_, tin_pv1_3_3_, preset_0_0_, tin_pv11_1_1_, tin_pv4_4_4_, tin_pready_0_0_, tin_pv10_0_0_, tin_pv11_0_0_, tin_pv6_1_1_, tin_pv2_2_2_, tin_pv1_4_4_, tin_pv4_5_5_, tin_pv6_2_2_, tin_pv2_3_3_, tin_pv1_5_5_, tin_pv4_6_6_, tin_pv6_3_3_, tin_pv2_4_4_, tin_pv1_6_6_, tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_, tin_pv4_0_0_, tin_pv6_5_5_, tin_pv2_6_6_, tin_pv10_7_7_, tin_pv1_0_0_, tin_pv11_7_7_, tin_pv4_1_1_, tin_pv10_6_6_, tin_pv11_6_6_, tin_pv6_6_6_, tin_pv2_7_7_, preset, tin_pv10_5_5_, tin_pv1_1_1_, tin_pv11_5_5_, tin_pv4_2_2_, pv14_2_2_, pv12_3_3_, pv10_4_4_, pv7_5_5_, pv3_6_6_, pv15_2_2_, pv13_3_3_, pv11_4_4_, pv6_7_7_, pv2_0_0_, pv14_1_1_, pv12_2_2_, pv10_3_3_, pv9_0_0_, pv5_1_1_, pv1_2_2_, pv15_1_1_, pv13_2_2_, pv11_3_3_, pv8_2_2_, pv4_3_3_, pv14_0_0_, pv12_1_1_, pv10_2_2_, pv7_6_6_, pv3_7_7_, pv15_0_0_, pv13_1_1_, pv11_2_2_, pv6_0_0_, pv2_1_1_, pv12_0_0_, pv10_1_1_, pv9_1_1_, pv5_2_2_, pv1_3_3_, pv13_0_0_, pv11_1_1_, pv8_3_3_, pv4_4_4_, pready_0_0_, pv10_0_0_, pv7_7_7_, pv3_0_0_, pv11_0_0_, pv6_1_1_, pv2_2_2_, pv9_2_2_, pv5_3_3_, pv1_4_4_, pv8_4_4_, pv4_5_5_, pv7_0_0_, pv3_1_1_, pv6_2_2_, pv2_3_3_, pv9_3_3_, pv5_4_4_, pv1_5_5_, pv8_5_5_, pv4_6_6_, pv7_1_1_, pv3_2_2_, pv6_3_3_, pv2_4_4_, pv9_4_4_, pv5_5_5_, pv1_6_6_, pv8_6_6_, pv4_7_7_, pv7_2_2_, pv3_3_3_, pv6_4_4_, pv2_5_5_, pv14_7_7_, pv9_5_5_, pv5_6_6_, pv1_7_7_, pv15_7_7_, pv8_7_7_, pv4_0_0_, pv14_6_6_, pv12_7_7_, pv7_3_3_, pv3_4_4_, pv15_6_6_, pv13_7_7_, pv6_5_5_, pv2_6_6_, pdn, pv14_5_5_, pv12_6_6_, pv10_7_7_, pv9_6_6_, pv5_7_7_, pv1_0_0_, pv15_5_5_, pv13_6_6_, pv11_7_7_, pv8_0_0_, pv4_1_1_, pv14_4_4_, pv12_5_5_, pv10_6_6_, pv7_4_4_, pv3_5_5_, pv15_4_4_, pv13_5_5_, pv11_6_6_, pv6_6_6_, pv2_7_7_, pv14_3_3_, pv12_4_4_, pv10_5_5_, pv9_7_7_, pv5_0_0_, pv1_1_1_, pv15_3_3_, pv13_4_4_, pv11_5_5_, pv8_1_1_, pv4_2_2_); + input clock; + wire n1003_1; + wire n1008_1; + wire n1013_1; + wire n1018_1; + wire n1023_1; + wire n1028_1; + wire n1033_1; + wire n1038_1; + wire n1043_1; + wire n1048_1; + wire n1053_1; + wire n1058_1; + wire n1063_1; + wire n1068_1; + wire n1073_1; + wire n1078_1; + wire n1083_1; + wire n1088_1; + wire n1093_1; + wire n1098_1; + wire n1103_1; + wire n1108_1; + wire n1113_1; + wire n1118_1; + wire n1123_1; + wire n1128_1; + wire n1133_1; + wire n1138_1; + wire n1143_1; + wire n1148_1; + wire n1153_1; + wire n1158_1; + wire n1163_1; + wire n1168_1; + wire n1173_1; + wire n1178_1; + wire n1183_1; + wire n1188_1; + wire n1193_1; + wire n1198_1; + wire n1203_1; + wire n1208_1; + wire n1213_1; + wire n1218_1; + wire n1223_1; + wire n1228_1; + wire n1233_1; + wire n1238_1; + wire n1243_1; + wire n1248_1; + wire n1253_1; + wire n1258; + wire n1263_1; + wire n1268_1; + wire n1273_1; + wire n1278_1; + wire n1283_1; + wire n1288_1; + wire n1293_1; + wire n1298_1; + wire n1303_1; + wire n1308_1; + wire n1313_1; + wire n1318_1; + wire n1323_1; + wire n1328_1; + wire n1333_1; + wire n1338_1; + wire n1343_1; + wire n1348_1; + wire n1353_1; + wire n1358_1; + wire n1363_1; + wire n1368_1; + wire n1373; + wire n1373_1; + wire n1374; + wire n1375; + wire n1376; + wire n1377; + wire n1378; + wire n1378_1; + wire n1379; + wire n1380; + wire n1381; + wire n1382; + wire n1383; + wire n1383_1; + wire n1384; + wire n1385; + wire n1388; + wire n1388_1; + wire n1389; + wire n1390; + wire n1391; + wire n1392; + wire n1393; + wire n1393_1; + wire n1394; + wire n1395; + wire n1396; + wire n1397; + wire n1398; + wire n1398_1; + wire n1399; + wire n1400; + wire n1401; + wire n1402; + wire n1403; + wire n1403_1; + wire n1404; + wire n1405; + wire n1406; + wire n1407; + wire n1408; + wire n1408_1; + wire n1409; + wire n1410; + wire n1411; + wire n1412; + wire n1413; + wire n1413_1; + wire n1414; + wire n1416; + wire n1418; + wire n1418_1; + wire n1423_1; + wire n1428_1; + wire n1433_1; + wire n1438_1; + wire n1443_1; + wire n1448_1; + wire n1453_1; + wire n1458_1; + wire n1463_1; + wire n1468_1; + wire n1473_1; + wire n1478_1; + wire n1483_1; + wire n1488_1; + wire n1492; + wire n1493; + wire n1493_1; + wire n1494; + wire n1495; + wire n1496; + wire n1497; + wire n1498; + wire n1498_1; + wire n1500; + wire n1502; + wire n1503; + wire n1503_1; + wire n1504; + wire n1507; + wire n1508; + wire n1508_1; + wire n1509; + wire n1510; + wire n1512; + wire n1513_1; + wire n1517; + wire n1518_1; + wire n1523_1; + wire n1528; + wire n1528_1; + wire n1529; + wire n1530; + wire n1531; + wire n1532; + wire n1533; + wire n1533_1; + wire n1534; + wire n1535; + wire n1536; + wire n1537; + wire n1538; + wire n1538_1; + wire n1539; + wire n1540; + wire n1541; + wire n1542; + wire n1543; + wire n1543_1; + wire n1545; + wire n1548_1; + wire n1551; + wire n1553_1; + wire n1555; + wire n1556; + wire n1558_1; + wire n1559; + wire n1563; + wire n1563_1; + wire n1565; + wire n1567; + wire n1568; + wire n1568_1; + wire n1569; + wire n1570; + wire n1573_1; + wire n1578; + wire n1578_1; + wire n1579; + wire n1580; + wire n1581; + wire n1582; + wire n1583; + wire n1583_1; + wire n1584; + wire n1585; + wire n1586; + wire n1587; + wire n1588_1; + wire n1593_1; + wire n1594; + wire n1595; + wire n1596; + wire n1597; + wire n1598; + wire n1598_1; + wire n1599; + wire n1603_1; + wire n1608_1; + wire n1613_1; + wire n1614; + wire n1616; + wire n1617; + wire n1618_1; + wire n1623_1; + wire n1626; + wire n1628_1; + wire n1633_1; + wire n1637; + wire n1638_1; + wire n1642; + wire n1643_1; + wire n1645; + wire n1646; + wire n1647; + wire n1648; + wire n1648_1; + wire n1649; + wire n1650; + wire n1651; + wire n1652; + wire n1653; + wire n1653_1; + wire n1654; + wire n1655; + wire n1656; + wire n1657; + wire n1658_1; + wire n1663_1; + wire n1668_1; + wire n1673_1; + wire n1678_1; + wire n1683_1; + wire n1688_1; + wire n1693_1; + wire n1698_1; + wire n1703_1; + wire n1708_1; + wire n1712; + wire n1713_1; + wire n1718_1; + wire n1719; + wire n1723_1; + wire n1728_1; + wire n1731; + wire n1733_1; + wire n1738_1; + wire n1743_1; + wire n1748_1; + wire n1750; + wire n1753_1; + wire n1757; + wire n1758; + wire n1758_1; + wire n1763_1; + wire n1765; + wire n1768; + wire n1768_1; + wire n1769; + wire n1773_1; + wire n1778_1; + wire n1783_1; + wire n1788; + wire n1788_1; + wire n1789; + wire n1793_1; + wire n1794; + wire n1798_1; + wire n1799; + wire n1803_1; + wire n1808_1; + wire n1813_1; + wire n1818_1; + wire n1823_1; + wire n1828_1; + wire n1833_1; + wire n1838_1; + wire n1843_1; + wire n1848_1; + wire n1853_1; + wire n1858_1; + wire n1863_1; + wire n1864; + wire n1868_1; + wire n1873_1; + wire n1878_1; + wire n1883_1; + wire n1888_1; + wire n1890; + wire n1893_1; + wire n1898_1; + wire n1903_1; + wire n1908_1; + wire n1913_1; + wire n1918_1; + wire n1923_1; + wire n1927; + wire n1928_1; + wire n1933_1; + wire n1938_1; + wire n1941; + wire n1943; + wire n1943_1; + wire n1948_1; + wire n1950; + wire n1953_1; + wire n1958_1; + wire n1963_1; + wire n1968_1; + wire n1973_1; + wire n1978_1; + wire n1983_1; + wire n1988_1; + wire n1993_1; + wire n1998_1; + wire n2003_1; + wire n2008_1; + wire n2013_1; + wire n2018_1; + wire n2023_1; + wire n2028_1; + wire n2033_1; + wire n2038_1; + wire n2043_1; + wire n2048_1; + wire n2053_1; + wire n2058_1; + wire n2063_1; + wire n2068_1; + wire n2073_1; + wire n2078_1; + wire n2083_1; + wire n2088_1; + wire n2093_1; + wire n2098; + wire n2103_1; + wire n2108_1; + wire n2113_1; + wire n2118_1; + wire n2123_1; + wire n2128_1; + wire n2133_1; + wire n2138_1; + wire n2143_1; + wire n2148_1; + wire n2153_1; + wire n2158_1; + wire n2163_1; + wire n2168_1; + wire n2173_1; + wire n2178_1; + wire n2183_1; + wire n2188_1; + wire n2193_1; + wire n2198_1; + wire n2203_1; + wire n2208_1; + wire n2213_1; + wire n2218_1; + wire n2223_1; + wire n2228_1; + wire n2233_1; + wire n2238_1; + wire n2243_1; + wire n2248_1; + wire n2253_1; + wire n349_1; + wire n353; + wire n358; + wire n363; + wire n368; + wire n373; + wire n378; + wire n383; + wire n388; + wire n393; + wire n398; + wire n403; + wire n408; + wire n413; + wire n418; + wire n423; + wire n428; + wire n433; + wire n438; + wire n443; + wire n448; + wire n453; + wire n458; + wire n463; + wire n468; + wire n473; + wire n478; + wire n483; + wire n488; + wire n493; + wire n498; + wire n503; + wire n508; + wire n513; + wire n518; + wire n523; + wire n528; + wire n533; + wire n538; + wire n543; + wire n548; + wire n553; + wire n558; + wire n563; + wire n568; + wire n573; + wire n578; + wire n583; + wire n588; + wire n593; + wire n598; + wire n603; + wire n608; + wire n613; + wire n618; + wire n623; + wire n628; + wire n633; + wire n638; + wire n643; + wire n648; + wire n653; + wire n658; + wire n663; + wire n668; + wire n673; + wire n678; + wire n683; + wire n688; + wire n693; + wire n698; + wire n703; + wire n708; + wire n713; + wire n718; + wire n723; + wire n728; + wire n733; + wire n738; + wire n743; + wire n748; + wire n753; + wire n758; + wire n763; + wire n768; + wire n773; + wire n778; + wire n783; + wire n788; + wire n793; + wire n798; + wire n803; + wire n808; + wire n813; + wire n818; + wire n823; + wire n828; + wire n833; + wire n838; + wire n843; + wire n848; + wire n853; + wire n858; + wire n863; + wire n868; + wire n873; + wire n878; + wire n883; + wire n888; + wire n893; + wire n898_1; + wire n903_1; + wire n908_1; + wire n913_1; + wire n918_1; + wire n923_1; + wire n928_1; + wire n933_1; + wire n938_1; + wire n943_1; + wire n948_1; + wire n953_1; + wire n958_1; + wire n963_1; + wire n968_1; + wire n973_1; + wire n978_1; + wire n983_1; + wire n988_1; + wire n993_1; + wire n998_1; + (* init = 1'h0 *) + reg n_n3008 = 1'h0; + (* init = 1'h0 *) + reg n_n3012 = 1'h0; + (* init = 1'h0 *) + reg n_n3014 = 1'h0; + (* init = 1'h0 *) + reg n_n3020 = 1'h0; + (* init = 1'h0 *) + reg n_n3024 = 1'h0; + (* init = 1'h0 *) + reg n_n3029 = 1'h0; + (* init = 1'h0 *) + reg n_n3035 = 1'h0; + (* init = 1'h0 *) + reg n_n3038 = 1'h0; + (* init = 1'h0 *) + reg n_n3040 = 1'h0; + (* init = 1'h0 *) + reg n_n3042 = 1'h0; + (* init = 1'h0 *) + reg n_n3044 = 1'h0; + (* init = 1'h0 *) + reg n_n3048 = 1'h0; + (* init = 1'h0 *) + reg n_n3051 = 1'h0; + (* init = 1'h0 *) + reg n_n3053 = 1'h0; + (* init = 1'h0 *) + reg n_n3055 = 1'h0; + (* init = 1'h0 *) + reg n_n3057 = 1'h0; + (* init = 1'h0 *) + reg n_n3061 = 1'h0; + (* init = 1'h0 *) + reg n_n3065 = 1'h0; + (* init = 1'h0 *) + reg n_n3067 = 1'h0; + (* init = 1'h0 *) + reg n_n3069 = 1'h0; + (* init = 1'h0 *) + reg n_n3073 = 1'h0; + (* init = 1'h0 *) + reg n_n3075 = 1'h0; + (* init = 1'h0 *) + reg n_n3079 = 1'h0; + (* init = 1'h0 *) + reg n_n3081 = 1'h0; + (* init = 1'h0 *) + reg n_n3085 = 1'h0; + (* init = 1'h0 *) + reg n_n3087 = 1'h0; + (* init = 1'h0 *) + reg n_n3089 = 1'h0; + (* init = 1'h0 *) + reg n_n3091 = 1'h0; + (* init = 1'h0 *) + reg n_n3093 = 1'h0; + (* init = 1'h0 *) + reg n_n3095 = 1'h0; + (* init = 1'h0 *) + reg n_n3098 = 1'h0; + (* init = 1'h0 *) + reg n_n3099 = 1'h0; + (* init = 1'h0 *) + reg n_n3101 = 1'h0; + (* init = 1'h0 *) + reg n_n3108 = 1'h0; + (* init = 1'h0 *) + reg n_n3111 = 1'h0; + (* init = 1'h0 *) + reg n_n3113 = 1'h0; + (* init = 1'h0 *) + reg n_n3116 = 1'h0; + (* init = 1'h0 *) + reg n_n3118 = 1'h0; + (* init = 1'h0 *) + reg n_n3120 = 1'h0; + (* init = 1'h0 *) + reg n_n3126 = 1'h0; + (* init = 1'h0 *) + reg n_n3128 = 1'h0; + (* init = 1'h0 *) + reg n_n3130 = 1'h0; + (* init = 1'h0 *) + reg n_n3133 = 1'h0; + (* init = 1'h0 *) + reg n_n3136 = 1'h0; + (* init = 1'h0 *) + reg n_n3138 = 1'h0; + (* init = 1'h0 *) + reg n_n3142 = 1'h0; + (* init = 1'h0 *) + reg n_n3144 = 1'h0; + (* init = 1'h0 *) + reg n_n3146 = 1'h0; + (* init = 1'h0 *) + reg n_n3150 = 1'h0; + (* init = 1'h0 *) + reg n_n3152 = 1'h0; + (* init = 1'h0 *) + reg n_n3155 = 1'h0; + (* init = 1'h0 *) + reg n_n3157 = 1'h0; + (* init = 1'h0 *) + reg n_n3161 = 1'h0; + (* init = 1'h0 *) + reg n_n3170 = 1'h0; + (* init = 1'h0 *) + reg n_n3173 = 1'h0; + (* init = 1'h0 *) + reg n_n3175 = 1'h0; + (* init = 1'h0 *) + reg n_n3180 = 1'h0; + (* init = 1'h0 *) + reg n_n3183 = 1'h0; + (* init = 1'h0 *) + reg n_n3188 = 1'h0; + (* init = 1'h0 *) + reg n_n3190 = 1'h0; + (* init = 1'h0 *) + reg n_n3195 = 1'h0; + (* init = 1'h0 *) + reg n_n3198 = 1'h0; + (* init = 1'h0 *) + reg n_n3202 = 1'h0; + (* init = 1'h0 *) + reg n_n3204 = 1'h0; + (* init = 1'h0 *) + reg n_n3207 = 1'h0; + (* init = 1'h0 *) + reg n_n3208 = 1'h0; + (* init = 1'h0 *) + reg n_n3211 = 1'h0; + (* init = 1'h0 *) + reg n_n3213 = 1'h0; + (* init = 1'h0 *) + reg n_n3215 = 1'h0; + (* init = 1'h0 *) + reg n_n3221 = 1'h0; + (* init = 1'h0 *) + reg n_n3223 = 1'h0; + (* init = 1'h0 *) + reg n_n3225 = 1'h0; + (* init = 1'h0 *) + reg n_n3231 = 1'h0; + (* init = 1'h0 *) + reg n_n3233 = 1'h0; + (* init = 1'h0 *) + reg n_n3237 = 1'h0; + (* init = 1'h0 *) + reg n_n3239 = 1'h0; + (* init = 1'h0 *) + reg n_n3242 = 1'h0; + (* init = 1'h0 *) + reg n_n3250 = 1'h0; + (* init = 1'h0 *) + reg n_n3252 = 1'h0; + (* init = 1'h0 *) + reg n_n3259 = 1'h0; + (* init = 1'h0 *) + reg n_n3262 = 1'h0; + (* init = 1'h0 *) + reg n_n3264 = 1'h0; + (* init = 1'h0 *) + reg n_n3266 = 1'h0; + (* init = 1'h0 *) + reg n_n3270 = 1'h0; + (* init = 1'h0 *) + reg n_n3274 = 1'h0; + (* init = 1'h0 *) + reg n_n3277 = 1'h0; + (* init = 1'h0 *) + reg n_n3281 = 1'h0; + (* init = 1'h0 *) + reg n_n3287 = 1'h0; + (* init = 1'h0 *) + reg n_n3305 = 1'h0; + (* init = 1'h0 *) + reg n_n3307 = 1'h0; + (* init = 1'h0 *) + reg n_n3313 = 1'h0; + (* init = 1'h0 *) + reg n_n3316 = 1'h0; + (* init = 1'h0 *) + reg n_n3319 = 1'h0; + (* init = 1'h0 *) + reg n_n3321 = 1'h0; + (* init = 1'h0 *) + reg n_n3326 = 1'h0; + (* init = 1'h0 *) + reg n_n3328 = 1'h0; + (* init = 1'h0 *) + reg n_n3331 = 1'h0; + (* init = 1'h0 *) + reg n_n3337 = 1'h0; + (* init = 1'h0 *) + reg n_n3339 = 1'h0; + (* init = 1'h0 *) + reg n_n3342 = 1'h0; + (* init = 1'h0 *) + reg n_n3344 = 1'h0; + (* init = 1'h0 *) + reg n_n3348 = 1'h0; + (* init = 1'h0 *) + reg n_n3350 = 1'h0; + (* init = 1'h0 *) + reg n_n3354 = 1'h0; + (* init = 1'h0 *) + reg n_n3358 = 1'h0; + (* init = 1'h0 *) + reg n_n3360 = 1'h0; + (* init = 1'h0 *) + reg n_n3367 = 1'h0; + (* init = 1'h0 *) + reg n_n3370 = 1'h0; + (* init = 1'h0 *) + reg n_n3372 = 1'h0; + (* init = 1'h0 *) + reg n_n3376 = 1'h0; + (* init = 1'h0 *) + reg n_n3379 = 1'h0; + (* init = 1'h0 *) + reg n_n3381 = 1'h0; + (* init = 1'h0 *) + reg n_n3385 = 1'h0; + (* init = 1'h0 *) + reg n_n3394 = 1'h0; + (* init = 1'h0 *) + reg n_n3396 = 1'h0; + (* init = 1'h0 *) + reg n_n3404 = 1'h0; + (* init = 1'h0 *) + reg n_n3408 = 1'h0; + (* init = 1'h0 *) + reg n_n3411 = 1'h0; + (* init = 1'h0 *) + reg n_n3413 = 1'h0; + (* init = 1'h0 *) + reg n_n3415 = 1'h0; + (* init = 1'h0 *) + reg n_n3429 = 1'h0; + (* init = 1'h0 *) + reg n_n3432 = 1'h0; + (* init = 1'h0 *) + reg n_n3434 = 1'h0; + (* init = 1'h0 *) + reg n_n3436 = 1'h0; + (* init = 1'h0 *) + reg n_n3441 = 1'h0; + (* init = 1'h0 *) + reg n_n3443 = 1'h0; + (* init = 1'h0 *) + reg n_n3449 = 1'h0; + (* init = 1'h0 *) + reg n_n3451 = 1'h0; + (* init = 1'h0 *) + reg n_n3456 = 1'h0; + (* init = 1'h0 *) + reg n_n3458 = 1'h0; + (* init = 1'h0 *) + reg n_n3461 = 1'h0; + (* init = 1'h0 *) + reg n_n3463 = 1'h0; + (* init = 1'h0 *) + reg n_n3465 = 1'h0; + (* init = 1'h0 *) + reg n_n3470 = 1'h0; + (* init = 1'h0 *) + reg n_n3475 = 1'h0; + (* init = 1'h0 *) + reg n_n3483 = 1'h0; + (* init = 1'h0 *) + reg n_n3486 = 1'h0; + (* init = 1'h0 *) + reg n_n3489 = 1'h0; + (* init = 1'h0 *) + reg n_n3493 = 1'h0; + (* init = 1'h0 *) + reg n_n3495 = 1'h0; + (* init = 1'h0 *) + reg n_n3497 = 1'h0; + (* init = 1'h0 *) + reg n_n3504 = 1'h0; + (* init = 1'h0 *) + reg n_n3506 = 1'h0; + (* init = 1'h0 *) + reg n_n3511 = 1'h0; + (* init = 1'h0 *) + reg n_n3514 = 1'h0; + (* init = 1'h0 *) + reg n_n3517 = 1'h0; + (* init = 1'h0 *) + reg n_n3521 = 1'h0; + (* init = 1'h0 *) + reg n_n3525 = 1'h0; + (* init = 1'h0 *) + reg n_n3529 = 1'h0; + (* init = 1'h0 *) + reg n_n3533 = 1'h0; + (* init = 1'h0 *) + reg n_n3537 = 1'h0; + (* init = 1'h0 *) + reg n_n3544 = 1'h0; + (* init = 1'h0 *) + reg n_n3549 = 1'h0; + (* init = 1'h0 *) + reg n_n3551 = 1'h0; + (* init = 1'h0 *) + reg n_n3556 = 1'h0; + (* init = 1'h0 *) + reg n_n3557 = 1'h0; + (* init = 1'h0 *) + reg n_n3567 = 1'h0; + (* init = 1'h0 *) + reg n_n3570 = 1'h0; + (* init = 1'h0 *) + reg n_n3572 = 1'h0; + (* init = 1'h0 *) + reg n_n3574 = 1'h0; + (* init = 1'h0 *) + reg n_n3576 = 1'h0; + (* init = 1'h0 *) + reg n_n3578 = 1'h0; + (* init = 1'h0 *) + reg n_n3583 = 1'h0; + (* init = 1'h0 *) + reg n_n3590 = 1'h0; + (* init = 1'h0 *) + reg n_n3600 = 1'h0; + (* init = 1'h0 *) + reg n_n3604 = 1'h0; + (* init = 1'h0 *) + reg n_n3606 = 1'h0; + (* init = 1'h0 *) + reg n_n3608 = 1'h0; + (* init = 1'h0 *) + reg n_n3617 = 1'h0; + (* init = 1'h0 *) + reg n_n3619 = 1'h0; + (* init = 1'h0 *) + reg n_n3624 = 1'h0; + (* init = 1'h0 *) + reg n_n3627 = 1'h0; + (* init = 1'h0 *) + reg n_n3631 = 1'h0; + (* init = 1'h0 *) + reg n_n3643 = 1'h0; + (* init = 1'h0 *) + reg n_n3646 = 1'h0; + (* init = 1'h0 *) + reg n_n3648 = 1'h0; + (* init = 1'h0 *) + reg n_n3650 = 1'h0; + (* init = 1'h0 *) + reg n_n3657 = 1'h0; + (* init = 1'h0 *) + reg n_n3658 = 1'h0; + (* init = 1'h0 *) + reg n_n3663 = 1'h0; + (* init = 1'h0 *) + reg n_n3667 = 1'h0; + (* init = 1'h0 *) + reg n_n3670 = 1'h0; + (* init = 1'h0 *) + reg n_n3674 = 1'h0; + (* init = 1'h0 *) + reg n_n3679 = 1'h0; + (* init = 1'h0 *) + reg n_n3687 = 1'h0; + (* init = 1'h0 *) + reg n_n3688 = 1'h0; + (* init = 1'h0 *) + reg n_n3707 = 1'h0; + (* init = 1'h0 *) + reg n_n3709 = 1'h0; + (* init = 1'h0 *) + reg n_n3713 = 1'h0; + (* init = 1'h0 *) + reg n_n3720 = 1'h0; + (* init = 1'h0 *) + reg n_n3722 = 1'h0; + (* init = 1'h0 *) + reg n_n3724 = 1'h0; + (* init = 1'h0 *) + reg n_n3726 = 1'h0; + (* init = 1'h0 *) + reg n_n3729 = 1'h0; + (* init = 1'h0 *) + reg n_n3733 = 1'h0; + (* init = 1'h0 *) + reg n_n3736 = 1'h0; + (* init = 1'h0 *) + reg n_n3739 = 1'h0; + (* init = 1'h0 *) + reg n_n3743 = 1'h0; + (* init = 1'h0 *) + reg n_n3749 = 1'h0; + (* init = 1'h0 *) + reg n_n3756 = 1'h0; + (* init = 1'h0 *) + reg n_n3758 = 1'h0; + (* init = 1'h0 *) + reg n_n3761 = 1'h0; + (* init = 1'h0 *) + reg n_n3764 = 1'h0; + (* init = 1'h0 *) + reg n_n3766 = 1'h0; + (* init = 1'h0 *) + reg n_n3769 = 1'h0; + (* init = 1'h0 *) + reg n_n3774 = 1'h0; + (* init = 1'h0 *) + reg n_n3777 = 1'h0; + (* init = 1'h0 *) + reg n_n3780 = 1'h0; + (* init = 1'h0 *) + reg n_n3782 = 1'h0; + (* init = 1'h0 *) + reg n_n3793 = 1'h0; + (* init = 1'h0 *) + reg n_n3797 = 1'h0; + (* init = 1'h0 *) + reg n_n3806 = 1'h0; + (* init = 1'h0 *) + reg n_n3814 = 1'h0; + (* init = 1'h0 *) + reg n_n3818 = 1'h0; + (* init = 1'h0 *) + reg n_n3823 = 1'h0; + (* init = 1'h0 *) + reg n_n3826 = 1'h0; + (* init = 1'h0 *) + reg n_n3828 = 1'h0; + (* init = 1'h0 *) + reg n_n3831 = 1'h0; + (* init = 1'h0 *) + reg n_n3833 = 1'h0; + (* init = 1'h0 *) + reg n_n3836 = 1'h0; + (* init = 1'h0 *) + reg n_n3841 = 1'h0; + (* init = 1'h0 *) + reg n_n3845 = 1'h0; + (* init = 1'h0 *) + reg n_n3851 = 1'h0; + (* init = 1'h0 *) + reg n_n3854 = 1'h0; + (* init = 1'h0 *) + reg n_n3858 = 1'h0; + (* init = 1'h0 *) + reg n_n3863 = 1'h0; + (* init = 1'h0 *) + reg n_n3865 = 1'h0; + (* init = 1'h0 *) + reg n_n3872 = 1'h0; + (* init = 1'h0 *) + reg n_n3874 = 1'h0; + (* init = 1'h0 *) + reg n_n3876 = 1'h0; + (* init = 1'h0 *) + reg n_n3878 = 1'h0; + (* init = 1'h0 *) + reg n_n3883 = 1'h0; + (* init = 1'h0 *) + reg n_n3886 = 1'h0; + (* init = 1'h0 *) + reg n_n3890 = 1'h0; + (* init = 1'h0 *) + reg n_n3892 = 1'h0; + (* init = 1'h0 *) + reg n_n3896 = 1'h0; + (* init = 1'h0 *) + reg n_n3898 = 1'h0; + (* init = 1'h0 *) + reg n_n3901 = 1'h0; + (* init = 1'h0 *) + reg n_n3903 = 1'h0; + (* init = 1'h0 *) + reg n_n3906 = 1'h0; + (* init = 1'h0 *) + reg n_n3910 = 1'h0; + (* init = 1'h0 *) + reg n_n3916 = 1'h0; + (* init = 1'h0 *) + reg n_n3919 = 1'h0; + (* init = 1'h0 *) + reg n_n3922 = 1'h0; + (* init = 1'h0 *) + reg n_n3931 = 1'h0; + (* init = 1'h0 *) + reg n_n3934 = 1'h0; + (* init = 1'h0 *) + reg n_n3936 = 1'h0; + (* init = 1'h0 *) + reg n_n3938 = 1'h0; + (* init = 1'h0 *) + reg n_n3946 = 1'h0; + (* init = 1'h0 *) + reg n_n3952 = 1'h0; + (* init = 1'h0 *) + reg n_n3954 = 1'h0; + (* init = 1'h0 *) + reg n_n3955 = 1'h0; + (* init = 1'h0 *) + reg n_n3959 = 1'h0; + (* init = 1'h0 *) + reg n_n3966 = 1'h0; + (* init = 1'h0 *) + reg n_n3968 = 1'h0; + (* init = 1'h0 *) + reg n_n3971 = 1'h0; + (* init = 1'h0 *) + reg n_n3976 = 1'h0; + (* init = 1'h0 *) + reg n_n3978 = 1'h0; + (* init = 1'h0 *) + reg n_n3985 = 1'h0; + (* init = 1'h0 *) + reg n_n3988 = 1'h0; + (* init = 1'h0 *) + reg n_n3995 = 1'h0; + (* init = 1'h0 *) + reg n_n3999 = 1'h0; + (* init = 1'h0 *) + reg n_n4003 = 1'h0; + (* init = 1'h0 *) + reg n_n4005 = 1'h0; + (* init = 1'h0 *) + reg n_n4012 = 1'h0; + (* init = 1'h0 *) + reg n_n4018 = 1'h0; + (* init = 1'h0 *) + reg n_n4021 = 1'h0; + (* init = 1'h0 *) + reg n_n4026 = 1'h0; + (* init = 1'h0 *) + reg n_n4029 = 1'h0; + (* init = 1'h0 *) + reg n_n4037 = 1'h0; + (* init = 1'h0 *) + reg n_n4040 = 1'h0; + (* init = 1'h0 *) + reg n_n4045 = 1'h0; + (* init = 1'h0 *) + reg n_n4047 = 1'h0; + (* init = 1'h0 *) + reg n_n4052 = 1'h0; + (* init = 1'h0 *) + reg n_n4056 = 1'h0; + (* init = 1'h0 *) + reg n_n4057 = 1'h0; + (* init = 1'h0 *) + reg n_n4059 = 1'h0; + (* init = 1'h0 *) + reg n_n4062 = 1'h0; + (* init = 1'h0 *) + reg n_n4065 = 1'h0; + (* init = 1'h0 *) + reg n_n4067 = 1'h0; + (* init = 1'h0 *) + reg n_n4071 = 1'h0; + (* init = 1'h0 *) + reg n_n4074 = 1'h0; + (* init = 1'h0 *) + reg n_n4077 = 1'h0; + (* init = 1'h0 *) + reg n_n4080 = 1'h0; + (* init = 1'h0 *) + reg n_n4089 = 1'h0; + (* init = 1'h0 *) + reg n_n4093 = 1'h0; + (* init = 1'h0 *) + reg n_n4095 = 1'h0; + (* init = 1'h0 *) + reg n_n4099 = 1'h0; + (* init = 1'h0 *) + reg n_n4102 = 1'h0; + (* init = 1'h0 *) + reg n_n4105 = 1'h0; + (* init = 1'h0 *) + reg n_n4108 = 1'h0; + (* init = 1'h0 *) + reg n_n4110 = 1'h0; + (* init = 1'h0 *) + reg n_n4114 = 1'h0; + (* init = 1'h0 *) + reg n_n4120 = 1'h0; + (* init = 1'h0 *) + reg n_n4122 = 1'h0; + (* init = 1'h0 *) + reg n_n4125 = 1'h0; + (* init = 1'h0 *) + reg n_n4129 = 1'h0; + (* init = 1'h0 *) + reg n_n4131 = 1'h0; + (* init = 1'h0 *) + reg n_n4136 = 1'h0; + (* init = 1'h0 *) + reg n_n4139 = 1'h0; + (* init = 1'h0 *) + reg n_n4142 = 1'h0; + (* init = 1'h0 *) + reg n_n4145 = 1'h0; + (* init = 1'h0 *) + reg n_n4151 = 1'h0; + (* init = 1'h0 *) + reg n_n4153 = 1'h0; + (* init = 1'h0 *) + reg n_n4157 = 1'h0; + (* init = 1'h0 *) + reg n_n4159 = 1'h0; + (* init = 1'h0 *) + reg n_n4160 = 1'h0; + (* init = 1'h0 *) + reg n_n4162 = 1'h0; + (* init = 1'h0 *) + reg n_n4164 = 1'h0; + (* init = 1'h0 *) + reg n_n4166 = 1'h0; + (* init = 1'h0 *) + reg n_n4172 = 1'h0; + (* init = 1'h0 *) + reg n_n4180 = 1'h0; + (* init = 1'h0 *) + reg n_n4182 = 1'h0; + (* init = 1'h0 *) + reg n_n4185 = 1'h0; + (* init = 1'h0 *) + reg n_n4189 = 1'h0; + (* init = 1'h0 *) + reg n_n4192 = 1'h0; + (* init = 1'h0 *) + reg n_n4199 = 1'h0; + (* init = 1'h0 *) + reg n_n4201 = 1'h0; + (* init = 1'h0 *) + reg n_n4209 = 1'h0; + (* init = 1'h0 *) + reg n_n4211 = 1'h0; + (* init = 1'h0 *) + reg n_n4213 = 1'h0; + (* init = 1'h0 *) + reg n_n4222 = 1'h0; + (* init = 1'h0 *) + reg n_n4224 = 1'h0; + (* init = 1'h0 *) + reg n_n4227 = 1'h0; + (* init = 1'h0 *) + reg n_n4229 = 1'h0; + (* init = 1'h0 *) + reg n_n4233 = 1'h0; + (* init = 1'h0 *) + reg n_n4236 = 1'h0; + (* init = 1'h0 *) + reg n_n4241 = 1'h0; + (* init = 1'h0 *) + reg n_n4243 = 1'h0; + (* init = 1'h0 *) + reg n_n4247 = 1'h0; + (* init = 1'h0 *) + reg n_n4251 = 1'h0; + (* init = 1'h0 *) + reg n_n4258 = 1'h0; + (* init = 1'h0 *) + reg n_n4270 = 1'h0; + (* init = 1'h0 *) + reg n_n4275 = 1'h0; + (* init = 1'h0 *) + reg n_n4279 = 1'h0; + (* init = 1'h0 *) + reg n_n4282 = 1'h0; + (* init = 1'h0 *) + reg n_n4286 = 1'h0; + (* init = 1'h0 *) + reg n_n4288 = 1'h0; + (* init = 1'h0 *) + reg n_n4290 = 1'h0; + (* init = 1'h0 *) + reg n_n4294 = 1'h0; + (* init = 1'h0 *) + reg n_n4299 = 1'h0; + (* init = 1'h0 *) + reg n_n4303 = 1'h0; + (* init = 1'h0 *) + reg n_n4309 = 1'h0; + (* init = 1'h0 *) + reg n_n4316 = 1'h0; + (* init = 1'h0 *) + reg n_n4320 = 1'h0; + (* init = 1'h0 *) + reg n_n4324 = 1'h0; + (* init = 1'h0 *) + reg n_n4330 = 1'h0; + (* init = 1'h0 *) + reg n_n4334 = 1'h0; + (* init = 1'h0 *) + reg n_n4337 = 1'h0; + (* init = 1'h0 *) + reg n_n4342 = 1'h0; + (* init = 1'h0 *) + reg n_n4347 = 1'h0; + (* init = 1'h0 *) + reg n_n4349 = 1'h0; + (* init = 1'h0 *) + reg n_n4351 = 1'h0; + (* init = 1'h0 *) + reg n_n4354 = 1'h0; + (* init = 1'h0 *) + reg n_n4360 = 1'h0; + (* init = 1'h0 *) + reg n_n4362 = 1'h0; + (* init = 1'h0 *) + reg n_n4366 = 1'h0; + (* init = 1'h0 *) + reg n_n4372 = 1'h0; + (* init = 1'h0 *) + reg n_n4375 = 1'h0; + (* init = 1'h0 *) + reg n_n4381 = 1'h0; + (* init = 1'h0 *) + reg n_n4383 = 1'h0; + (* init = 1'h0 *) + reg n_n4390 = 1'h0; + (* init = 1'h0 *) + reg n_n4392 = 1'h0; + (* init = 1'h0 *) + reg ndn1_34 = 1'h0; + (* init = 1'h0 *) + reg ndn3_10 = 1'h0; + (* init = 1'h0 *) + reg ndn3_15 = 1'h0; + (* init = 1'h0 *) + reg ndn3_4 = 1'h0; + (* init = 1'h0 *) + reg ndn3_5 = 1'h0; + (* init = 1'h0 *) + reg ndn3_6 = 1'h0; + (* init = 1'h0 *) + reg ndn3_7 = 1'h0; + (* init = 1'h0 *) + reg ndn3_8 = 1'h0; + (* init = 1'h0 *) + reg ndn3_9 = 1'h0; + (* init = 1'h0 *) + reg nen3_10 = 1'h0; + (* init = 1'h0 *) + reg ngfdn_3 = 1'h0; + (* init = 1'h0 *) + reg nlc1_2 = 1'h0; + (* init = 1'h0 *) + reg nrq3_11 = 1'h0; + (* init = 1'h0 *) + reg nsr1_2 = 1'h0; + (* init = 1'h0 *) + reg nsr3_14 = 1'h0; + (* init = 1'h0 *) + reg nsr3_17 = 1'h0; + (* init = 1'h0 *) + reg nsr3_3 = 1'h0; + (* init = 1'h0 *) + reg nsr4_2 = 1'h0; + (* init = 1'h0 *) + output pdn; + reg pdn = 1'h0; + output pready_0_0_; + input preset; + input preset_0_0_; + output pv10_0_0_; + output pv10_1_1_; + output pv10_2_2_; + output pv10_3_3_; + output pv10_4_4_; + output pv10_5_5_; + output pv10_6_6_; + output pv10_7_7_; + output pv11_0_0_; + output pv11_1_1_; + output pv11_2_2_; + output pv11_3_3_; + output pv11_4_4_; + output pv11_5_5_; + output pv11_6_6_; + output pv11_7_7_; + output pv12_0_0_; + output pv12_1_1_; + output pv12_2_2_; + output pv12_3_3_; + output pv12_4_4_; + output pv12_5_5_; + output pv12_6_6_; + output pv12_7_7_; + output pv13_0_0_; + output pv13_1_1_; + output pv13_2_2_; + output pv13_3_3_; + output pv13_4_4_; + output pv13_5_5_; + output pv13_6_6_; + output pv13_7_7_; + output pv14_0_0_; + output pv14_1_1_; + output pv14_2_2_; + output pv14_3_3_; + output pv14_4_4_; + output pv14_5_5_; + output pv14_6_6_; + output pv14_7_7_; + output pv15_0_0_; + output pv15_1_1_; + output pv15_2_2_; + output pv15_3_3_; + output pv15_4_4_; + output pv15_5_5_; + output pv15_6_6_; + output pv15_7_7_; + output pv1_0_0_; + output pv1_1_1_; + output pv1_2_2_; + output pv1_3_3_; + output pv1_4_4_; + output pv1_5_5_; + output pv1_6_6_; + output pv1_7_7_; + output pv2_0_0_; + output pv2_1_1_; + output pv2_2_2_; + output pv2_3_3_; + output pv2_4_4_; + output pv2_5_5_; + output pv2_6_6_; + output pv2_7_7_; + output pv3_0_0_; + output pv3_1_1_; + output pv3_2_2_; + output pv3_3_3_; + output pv3_4_4_; + output pv3_5_5_; + output pv3_6_6_; + output pv3_7_7_; + output pv4_0_0_; + output pv4_1_1_; + output pv4_2_2_; + output pv4_3_3_; + output pv4_4_4_; + output pv4_5_5_; + output pv4_6_6_; + output pv4_7_7_; + output pv5_0_0_; + output pv5_1_1_; + output pv5_2_2_; + output pv5_3_3_; + output pv5_4_4_; + output pv5_5_5_; + output pv5_6_6_; + output pv5_7_7_; + output pv6_0_0_; + output pv6_1_1_; + output pv6_2_2_; + output pv6_3_3_; + output pv6_4_4_; + output pv6_5_5_; + output pv6_6_6_; + output pv6_7_7_; + output pv7_0_0_; + output pv7_1_1_; + output pv7_2_2_; + output pv7_3_3_; + output pv7_4_4_; + output pv7_5_5_; + output pv7_6_6_; + output pv7_7_7_; + output pv8_0_0_; + output pv8_1_1_; + output pv8_2_2_; + output pv8_3_3_; + output pv8_4_4_; + output pv8_5_5_; + output pv8_6_6_; + output pv8_7_7_; + output pv9_0_0_; + output pv9_1_1_; + output pv9_2_2_; + output pv9_3_3_; + output pv9_4_4_; + output pv9_5_5_; + output pv9_6_6_; + output pv9_7_7_; + input tin_pready_0_0_; + input tin_pv10_0_0_; + input tin_pv10_1_1_; + input tin_pv10_2_2_; + input tin_pv10_3_3_; + input tin_pv10_4_4_; + input tin_pv10_5_5_; + input tin_pv10_6_6_; + input tin_pv10_7_7_; + input tin_pv11_0_0_; + input tin_pv11_1_1_; + input tin_pv11_2_2_; + input tin_pv11_3_3_; + input tin_pv11_4_4_; + input tin_pv11_5_5_; + input tin_pv11_6_6_; + input tin_pv11_7_7_; + input tin_pv1_0_0_; + input tin_pv1_1_1_; + input tin_pv1_2_2_; + input tin_pv1_3_3_; + input tin_pv1_4_4_; + input tin_pv1_5_5_; + input tin_pv1_6_6_; + input tin_pv1_7_7_; + input tin_pv2_0_0_; + input tin_pv2_1_1_; + input tin_pv2_2_2_; + input tin_pv2_3_3_; + input tin_pv2_4_4_; + input tin_pv2_5_5_; + input tin_pv2_6_6_; + input tin_pv2_7_7_; + input tin_pv4_0_0_; + input tin_pv4_1_1_; + input tin_pv4_2_2_; + input tin_pv4_3_3_; + input tin_pv4_4_4_; + input tin_pv4_5_5_; + input tin_pv4_6_6_; + input tin_pv4_7_7_; + input tin_pv6_0_0_; + input tin_pv6_1_1_; + input tin_pv6_2_2_; + input tin_pv6_3_3_; + input tin_pv6_4_4_; + input tin_pv6_5_5_; + input tin_pv6_6_6_; + input tin_pv6_7_7_; + always @(posedge clock) + pdn <= n349_1; + always @(posedge clock) + n_n3067 <= n393; + always @(posedge clock) + ndn3_10 <= n843; + always @(posedge clock) + n_n4172 <= n848; + always @(posedge clock) + nlc1_2 <= n853; + always @(posedge clock) + n_n3590 <= n858; + always @(posedge clock) + n_n4110 <= n863; + always @(posedge clock) + n_n3576 <= n868; + always @(posedge clock) + n_n4129 <= n873; + always @(posedge clock) + n_n4189 <= n878; + always @(posedge clock) + n_n4286 <= n883; + always @(posedge clock) + n_n4383 <= n888; + always @(posedge clock) + n_n4258 <= n398; + always @(posedge clock) + n_n3567 <= n893; + always @(posedge clock) + n_n3892 <= n898_1; + always @(posedge clock) + n_n3075 <= n903_1; + always @(posedge clock) + n_n3354 <= n908_1; + always @(posedge clock) + n_n3465 <= n913_1; + always @(posedge clock) + ndn3_6 <= n918_1; + always @(posedge clock) + n_n3617 <= n923_1; + always @(posedge clock) + n_n4162 <= n928_1; + always @(posedge clock) + n_n3207 <= n933_1; + always @(posedge clock) + n_n4120 <= n938_1; + always @(posedge clock) + n_n3225 <= n403; + always @(posedge clock) + n_n3065 <= n943_1; + always @(posedge clock) + n_n4005 <= n948_1; + always @(posedge clock) + n_n3266 <= n953_1; + always @(posedge clock) + n_n4337 <= n958_1; + always @(posedge clock) + n_n3600 <= n963_1; + always @(posedge clock) + n_n3415 <= n968_1; + always @(posedge clock) + n_n4243 <= n973_1; + always @(posedge clock) + n_n3872 <= n978_1; + always @(posedge clock) + n_n3648 <= n983_1; + always @(posedge clock) + n_n3358 <= n988_1; + always @(posedge clock) + n_n3180 <= n408; + always @(posedge clock) + n_n3350 <= n993_1; + always @(posedge clock) + ndn3_7 <= n998_1; + always @(posedge clock) + n_n3116 <= n1003_1; + always @(posedge clock) + n_n3583 <= n1008_1; + always @(posedge clock) + n_n3906 <= n1013_1; + always @(posedge clock) + n_n4131 <= n1018_1; + always @(posedge clock) + n_n3316 <= n1023_1; + always @(posedge clock) + n_n3061 <= n1028_1; + always @(posedge clock) + n_n3048 <= n1033_1; + always @(posedge clock) + n_n3886 <= n1038_1; + always @(posedge clock) + n_n3274 <= n413; + always @(posedge clock) + n_n3919 <= n1043_1; + always @(posedge clock) + n_n3128 <= n1048_1; + always @(posedge clock) + n_n3995 <= n1053_1; + always @(posedge clock) + n_n4213 <= n1058_1; + always @(posedge clock) + n_n3761 <= n1063_1; + always @(posedge clock) + ndn3_8 <= n1068_1; + always @(posedge clock) + n_n3252 <= n1073_1; + always @(posedge clock) + n_n4366 <= n1078_1; + always @(posedge clock) + n_n3328 <= n1083_1; + always @(posedge clock) + n_n3988 <= n1088_1; + always @(posedge clock) + n_n3475 <= n418; + always @(posedge clock) + n_n3348 <= n1093_1; + always @(posedge clock) + n_n3544 <= n1098_1; + always @(posedge clock) + n_n3101 <= n1103_1; + always @(posedge clock) + n_n4279 <= n1108_1; + always @(posedge clock) + n_n3896 <= n1113_1; + always @(posedge clock) + n_n3736 <= n1118_1; + always @(posedge clock) + n_n4251 <= n1123_1; + always @(posedge clock) + n_n3650 <= n1128_1; + always @(posedge clock) + n_n3307 <= n1133_1; + always @(posedge clock) + n_n4294 <= n1138_1; + always @(posedge clock) + n_n3687 <= n423; + always @(posedge clock) + n_n4334 <= n1143_1; + always @(posedge clock) + n_n3955 <= n1148_1; + always @(posedge clock) + n_n4164 <= n1153_1; + always @(posedge clock) + n_n3155 <= n1158_1; + always @(posedge clock) + n_n3749 <= n1163_1; + always @(posedge clock) + n_n4233 <= n1168_1; + always @(posedge clock) + n_n4347 <= n1173_1; + always @(posedge clock) + n_n3826 <= n1178_1; + always @(posedge clock) + n_n3360 <= n1183_1; + always @(posedge clock) + n_n3458 <= n1188_1; + always @(posedge clock) + n_n3381 <= n428; + always @(posedge clock) + n_n3093 <= n1193_1; + always @(posedge clock) + n_n3157 <= n1198_1; + always @(posedge clock) + n_n3506 <= n1203_1; + always @(posedge clock) + n_n3161 <= n1208_1; + always @(posedge clock) + n_n3319 <= n1213_1; + always @(posedge clock) + n_n3429 <= n1218_1; + always @(posedge clock) + n_n3971 <= n1223_1; + always @(posedge clock) + n_n3449 <= n1228_1; + always @(posedge clock) + n_n4270 <= n1233_1; + always @(posedge clock) + n_n4288 <= n1238_1; + always @(posedge clock) + n_n3098 <= n433; + always @(posedge clock) + n_n3183 <= n1243_1; + always @(posedge clock) + n_n3130 <= n1248_1; + always @(posedge clock) + n_n4047 <= n1253_1; + always @(posedge clock) + n_n3978 <= n1258; + always @(posedge clock) + n_n3239 <= n1263_1; + always @(posedge clock) + n_n4145 <= n1268_1; + always @(posedge clock) + n_n3890 <= n1273_1; + always @(posedge clock) + n_n4003 <= n1278_1; + always @(posedge clock) + n_n3091 <= n1283_1; + always @(posedge clock) + n_n3985 <= n1288_1; + always @(posedge clock) + n_n4108 <= n438; + always @(posedge clock) + n_n3326 <= n1293_1; + always @(posedge clock) + n_n4052 <= n1298_1; + always @(posedge clock) + nsr4_2 <= n1303_1; + always @(posedge clock) + n_n4099 <= n1308_1; + always @(posedge clock) + n_n4375 <= n1313_1; + always @(posedge clock) + n_n4067 <= n1318_1; + always @(posedge clock) + n_n4290 <= n1323_1; + always @(posedge clock) + n_n3898 <= n1328_1; + always @(posedge clock) + n_n4122 <= n1333_1; + always @(posedge clock) + n_n3774 <= n1338_1; + always @(posedge clock) + n_n4142 <= n353; + always @(posedge clock) + n_n3497 <= n443; + always @(posedge clock) + n_n3014 <= n1343_1; + always @(posedge clock) + n_n4241 <= n1348_1; + always @(posedge clock) + n_n3952 <= n1353_1; + always @(posedge clock) + n_n3237 <= n1358_1; + always @(posedge clock) + n_n3968 <= n1363_1; + always @(posedge clock) + n_n3922 <= n1368_1; + always @(posedge clock) + n_n3551 <= n1373_1; + always @(posedge clock) + n_n3379 <= n1378_1; + always @(posedge clock) + n_n4275 <= n1383_1; + always @(posedge clock) + n_n3570 <= n1388_1; + always @(posedge clock) + n_n3793 <= n448; + always @(posedge clock) + n_n3854 <= n1393_1; + always @(posedge clock) + n_n4057 <= n1398_1; + always @(posedge clock) + n_n3451 <= n1403_1; + always @(posedge clock) + n_n4037 <= n1408_1; + always @(posedge clock) + n_n3408 <= n1413_1; + always @(posedge clock) + n_n4229 <= n1418_1; + always @(posedge clock) + n_n4201 <= n1423_1; + always @(posedge clock) + n_n3339 <= n1428_1; + always @(posedge clock) + n_n4362 <= n1433_1; + always @(posedge clock) + n_n3483 <= n1438_1; + always @(posedge clock) + n_n4316 <= n453; + always @(posedge clock) + n_n3557 <= n1443_1; + always @(posedge clock) + n_n4185 <= n1448_1; + always @(posedge clock) + n_n3069 <= n1453_1; + always @(posedge clock) + n_n3643 <= n1458_1; + always @(posedge clock) + n_n3404 <= n1463_1; + always @(posedge clock) + n_n3057 <= n1468_1; + always @(posedge clock) + n_n3020 <= n1473_1; + always @(posedge clock) + n_n3828 <= n1478_1; + always @(posedge clock) + n_n3631 <= n1483_1; + always @(posedge clock) + n_n3138 <= n1488_1; + always @(posedge clock) + n_n4349 <= n458; + always @(posedge clock) + nsr1_2 <= n1493_1; + always @(posedge clock) + n_n4065 <= n1498_1; + always @(posedge clock) + n_n3679 <= n1503_1; + always @(posedge clock) + n_n3287 <= n1508_1; + always @(posedge clock) + n_n4351 <= n1513_1; + always @(posedge clock) + n_n4059 <= n1518_1; + always @(posedge clock) + n_n3436 <= n1523_1; + always @(posedge clock) + nen3_10 <= n1528_1; + always @(posedge clock) + n_n3461 <= n1533_1; + always @(posedge clock) + n_n4012 <= n1538_1; + always @(posedge clock) + n_n3029 <= n463; + always @(posedge clock) + n_n3051 <= n1543_1; + always @(posedge clock) + n_n3073 <= n1548_1; + always @(posedge clock) + n_n3777 <= n1553_1; + always @(posedge clock) + n_n3709 <= n1558_1; + always @(posedge clock) + n_n3946 <= n1563_1; + always @(posedge clock) + n_n3085 <= n1568_1; + always @(posedge clock) + n_n3259 <= n1573_1; + always @(posedge clock) + n_n3504 <= n1578_1; + always @(posedge clock) + n_n4045 <= n1583_1; + always @(posedge clock) + n_n3954 <= n1588_1; + always @(posedge clock) + n_n3619 <= n468; + always @(posedge clock) + n_n3136 <= n1593_1; + always @(posedge clock) + n_n4372 <= n1598_1; + always @(posedge clock) + n_n4236 <= n1603_1; + always @(posedge clock) + n_n3040 <= n1608_1; + always @(posedge clock) + n_n3874 <= n1613_1; + always @(posedge clock) + n_n3999 <= n1618_1; + always @(posedge clock) + n_n3223 <= n1623_1; + always @(posedge clock) + ndn1_34 <= n1628_1; + always @(posedge clock) + n_n3743 <= n1633_1; + always @(posedge clock) + n_n3657 <= n1638_1; + always @(posedge clock) + n_n3264 <= n473; + always @(posedge clock) + n_n3213 <= n1643_1; + always @(posedge clock) + n_n3095 <= n1648_1; + always @(posedge clock) + n_n3663 <= n1653_1; + always @(posedge clock) + n_n3724 <= n1658_1; + always @(posedge clock) + n_n3038 <= n1663_1; + always @(posedge clock) + n_n3370 <= n1668_1; + always @(posedge clock) + n_n3624 <= n1673_1; + always @(posedge clock) + n_n3578 <= n1678_1; + always @(posedge clock) + n_n3713 <= n1683_1; + always @(posedge clock) + n_n3089 <= n1688_1; + always @(posedge clock) + n_n3780 <= n478; + always @(posedge clock) + n_n3211 <= n1693_1; + always @(posedge clock) + n_n3367 <= n1698_1; + always @(posedge clock) + n_n3434 <= n1703_1; + always @(posedge clock) + n_n3126 <= n1708_1; + always @(posedge clock) + n_n4192 <= n1713_1; + always @(posedge clock) + n_n4136 <= n1718_1; + always @(posedge clock) + n_n3053 <= n1723_1; + always @(posedge clock) + n_n3938 <= n1728_1; + always @(posedge clock) + n_n3769 <= n1733_1; + always @(posedge clock) + n_n4390 <= n1738_1; + always @(posedge clock) + ndn3_4 <= n483; + always @(posedge clock) + nsr3_17 <= n1743_1; + always @(posedge clock) + n_n3903 <= n1748_1; + always @(posedge clock) + n_n3658 <= n1753_1; + always @(posedge clock) + nrq3_11 <= n1758_1; + always @(posedge clock) + n_n3818 <= n1763_1; + always @(posedge clock) + n_n3533 <= n1768_1; + always @(posedge clock) + n_n3463 <= n1773_1; + always @(posedge clock) + n_n3175 <= n1778_1; + always @(posedge clock) + n_n3055 <= n1783_1; + always @(posedge clock) + n_n3202 <= n1788_1; + always @(posedge clock) + n_n4114 <= n488; + always @(posedge clock) + n_n3385 <= n1793_1; + always @(posedge clock) + n_n4077 <= n1798_1; + always @(posedge clock) + n_n3142 <= n1803_1; + always @(posedge clock) + n_n3901 <= n1808_1; + always @(posedge clock) + n_n3934 <= n1813_1; + always @(posedge clock) + n_n3823 <= n1818_1; + always @(posedge clock) + n_n3722 <= n1823_1; + always @(posedge clock) + n_n4309 <= n1828_1; + always @(posedge clock) + n_n4159 <= n1833_1; + always @(posedge clock) + n_n4330 <= n1838_1; + always @(posedge clock) + n_n3936 <= n358; + always @(posedge clock) + n_n3146 <= n493; + always @(posedge clock) + n_n3836 <= n1843_1; + always @(posedge clock) + n_n3470 <= n1848_1; + always @(posedge clock) + n_n3331 <= n1853_1; + always @(posedge clock) + n_n3883 <= n1858_1; + always @(posedge clock) + n_n4299 <= n1863_1; + always @(posedge clock) + n_n4157 <= n1868_1; + always @(posedge clock) + ndn3_9 <= n1873_1; + always @(posedge clock) + n_n3208 <= n1878_1; + always @(posedge clock) + n_n3190 <= n1883_1; + always @(posedge clock) + n_n4029 <= n1888_1; + always @(posedge clock) + n_n3511 <= n498; + always @(posedge clock) + n_n3042 <= n1893_1; + always @(posedge clock) + nsr3_14 <= n1898_1; + always @(posedge clock) + n_n4151 <= n1903_1; + always @(posedge clock) + n_n3188 <= n1908_1; + always @(posedge clock) + n_n4303 <= n1913_1; + always @(posedge clock) + n_n3250 <= n1918_1; + always @(posedge clock) + n_n3170 <= n1923_1; + always @(posedge clock) + n_n3758 <= n1928_1; + always @(posedge clock) + n_n3910 <= n1933_1; + always @(posedge clock) + n_n3108 <= n1938_1; + always @(posedge clock) + n_n3152 <= n503; + always @(posedge clock) + n_n3150 <= n1943_1; + always @(posedge clock) + n_n4320 <= n1948_1; + always @(posedge clock) + n_n4360 <= n1953_1; + always @(posedge clock) + n_n4247 <= n1958_1; + always @(posedge clock) + n_n4199 <= n1963_1; + always @(posedge clock) + n_n3966 <= n1968_1; + always @(posedge clock) + n_n3766 <= n1973_1; + always @(posedge clock) + n_n4021 <= n1978_1; + always @(posedge clock) + n_n4062 <= n1983_1; + always @(posedge clock) + n_n3514 <= n1988_1; + always @(posedge clock) + n_n3833 <= n508; + always @(posedge clock) + n_n3572 <= n1993_1; + always @(posedge clock) + n_n4166 <= n1998_1; + always @(posedge clock) + n_n3976 <= n2003_1; + always @(posedge clock) + n_n3394 <= n2008_1; + always @(posedge clock) + n_n4095 <= n2013_1; + always @(posedge clock) + n_n3863 <= n2018_1; + always @(posedge clock) + n_n3720 <= n2023_1; + always @(posedge clock) + ngfdn_3 <= n2028_1; + always @(posedge clock) + n_n3756 <= n2033_1; + always @(posedge clock) + n_n3667 <= n2038_1; + always @(posedge clock) + n_n4282 <= n513; + always @(posedge clock) + n_n3342 <= n2043_1; + always @(posedge clock) + n_n3529 <= n2048_1; + always @(posedge clock) + n_n4209 <= n2053_1; + always @(posedge clock) + n_n4324 <= n2058_1; + always @(posedge clock) + n_n3337 <= n2063_1; + always @(posedge clock) + n_n4227 <= n2068_1; + always @(posedge clock) + n_n4153 <= n2073_1; + always @(posedge clock) + n_n3831 <= n2078_1; + always @(posedge clock) + n_n3233 <= n2083_1; + always @(posedge clock) + n_n3413 <= n2088_1; + always @(posedge clock) + n_n3305 <= n518; + always @(posedge clock) + n_n4182 <= n2093_1; + always @(posedge clock) + n_n3841 <= n2098; + always @(posedge clock) + n_n3441 <= n2103_1; + always @(posedge clock) + n_n4026 <= n2108_1; + always @(posedge clock) + n_n4342 <= n2113_1; + always @(posedge clock) + n_n4102 <= n2118_1; + always @(posedge clock) + n_n3277 <= n2123_1; + always @(posedge clock) + n_n4180 <= n2128_1; + always @(posedge clock) + n_n3878 <= n2133_1; + always @(posedge clock) + n_n3931 <= n2138_1; + always @(posedge clock) + n_n4392 <= n523; + always @(posedge clock) + n_n3845 <= n2143_1; + always @(posedge clock) + n_n3865 <= n2148_1; + always @(posedge clock) + n_n3486 <= n2153_1; + always @(posedge clock) + n_n4056 <= n2158_1; + always @(posedge clock) + n_n3674 <= n2163_1; + always @(posedge clock) + n_n3959 <= n2168_1; + always @(posedge clock) + n_n3608 <= n2173_1; + always @(posedge clock) + n_n4080 <= n2178_1; + always @(posedge clock) + n_n4018 <= n2183_1; + always @(posedge clock) + n_n4354 <= n2188_1; + always @(posedge clock) + n_n4224 <= n528; + always @(posedge clock) + n_n3797 <= n2193_1; + always @(posedge clock) + n_n3739 <= n2198_1; + always @(posedge clock) + n_n3646 <= n2203_1; + always @(posedge clock) + n_n3099 <= n2208_1; + always @(posedge clock) + n_n3537 <= n2213_1; + always @(posedge clock) + n_n3806 <= n2218_1; + always @(posedge clock) + n_n3087 <= n2223_1; + always @(posedge clock) + n_n4105 <= n2228_1; + always @(posedge clock) + n_n3262 <= n2233_1; + always @(posedge clock) + n_n4125 <= n2238_1; + always @(posedge clock) + n_n3198 <= n533; + always @(posedge clock) + n_n3814 <= n2243_1; + always @(posedge clock) + n_n4093 <= n2248_1; + always @(posedge clock) + nsr3_3 <= n2253_1; + always @(posedge clock) + n_n3204 <= n538; + always @(posedge clock) + n_n3574 <= n363; + always @(posedge clock) + n_n3024 <= n543; + always @(posedge clock) + n_n4139 <= n548; + always @(posedge clock) + ndn3_15 <= n553; + always @(posedge clock) + n_n3133 <= n558; + always @(posedge clock) + n_n4074 <= n563; + always @(posedge clock) + n_n3270 <= n568; + always @(posedge clock) + n_n3858 <= n573; + always @(posedge clock) + n_n3456 <= n578; + always @(posedge clock) + n_n3521 <= n583; + always @(posedge clock) + n_n3081 <= n588; + always @(posedge clock) + n_n3008 <= n368; + always @(posedge clock) + n_n4381 <= n593; + always @(posedge clock) + n_n3670 <= n598; + always @(posedge clock) + n_n4211 <= n603; + always @(posedge clock) + n_n3493 <= n608; + always @(posedge clock) + n_n3495 <= n613; + always @(posedge clock) + n_n3916 <= n618; + always @(posedge clock) + n_n3195 <= n623; + always @(posedge clock) + n_n3525 <= n628; + always @(posedge clock) + n_n3729 <= n633; + always @(posedge clock) + n_n3876 <= n638; + always @(posedge clock) + n_n3726 <= n373; + always @(posedge clock) + ndn3_5 <= n643; + always @(posedge clock) + n_n3549 <= n648; + always @(posedge clock) + n_n3489 <= n653; + always @(posedge clock) + n_n3764 <= n658; + always @(posedge clock) + n_n3281 <= n663; + always @(posedge clock) + n_n3707 <= n668; + always @(posedge clock) + n_n3517 <= n673; + always @(posedge clock) + n_n4160 <= n678; + always @(posedge clock) + n_n4222 <= n683; + always @(posedge clock) + n_n3012 <= n688; + always @(posedge clock) + n_n3604 <= n378; + always @(posedge clock) + n_n4071 <= n693; + always @(posedge clock) + n_n3372 <= n698; + always @(posedge clock) + n_n3344 <= n703; + always @(posedge clock) + n_n3688 <= n708; + always @(posedge clock) + n_n3079 <= n713; + always @(posedge clock) + n_n3313 <= n718; + always @(posedge clock) + n_n3411 <= n723; + always @(posedge clock) + n_n3231 <= n728; + always @(posedge clock) + n_n3396 <= n733; + always @(posedge clock) + n_n3432 <= n738; + always @(posedge clock) + n_n3144 <= n383; + always @(posedge clock) + n_n3606 <= n743; + always @(posedge clock) + n_n3733 <= n748; + always @(posedge clock) + n_n3556 <= n753; + always @(posedge clock) + n_n4040 <= n758; + always @(posedge clock) + n_n3120 <= n763; + always @(posedge clock) + n_n3221 <= n768; + always @(posedge clock) + n_n3173 <= n773; + always @(posedge clock) + n_n3851 <= n778; + always @(posedge clock) + n_n3113 <= n783; + always @(posedge clock) + n_n3242 <= n788; + always @(posedge clock) + n_n3782 <= n388; + always @(posedge clock) + n_n3118 <= n793; + always @(posedge clock) + n_n3376 <= n798; + always @(posedge clock) + n_n4089 <= n803; + always @(posedge clock) + n_n3044 <= n808; + always @(posedge clock) + n_n3627 <= n813; + always @(posedge clock) + n_n3035 <= n818; + always @(posedge clock) + n_n3111 <= n823; + always @(posedge clock) + n_n3321 <= n828; + always @(posedge clock) + n_n3443 <= n833; + always @(posedge clock) + n_n3215 <= n838; + assign n2143_1 = 64'hd5c0d5c0d5d5d5c0 >> { n1596, n_n3968, n1941, n_n3845, n1594, preset }; + assign n1941 = 16'h8828 >> { n_n3955, n_n3954, n_n3845, n1384 }; + assign n2148_1 = 64'hd5c0d5c0d5d5d5c0 >> { n1596, n_n3922, n1943, n_n3865, n1594, preset }; + assign n1943 = 16'h2888 >> { n1599, n_n3954, n_n3865, n1384 }; + assign n2153_1 = 16'hf888 >> { n1494, n_n3533, n1496, n_n3486 }; + assign n2158_1 = 16'h2220 >> { n_n4056, n1379, preset, n1788 }; + assign n2163_1 = 8'h54 >> { n_n3674, n1497, preset }; + assign n2168_1 = 64'h5555501440045014 >> { n_n3756, n1416, n1407, n_n3959, n1414, preset }; + assign n2173_1 = 16'h3120 >> { n_n3608, n1626, preset, n1533 }; + assign n2178_1 = 64'hf2f0f2f0f3f1f2f0 >> { n1414, n_n4080, n_n4299, n1950, preset, n1416 }; + assign n1950 = 64'h2828288228828282 >> { n1399, n1509, n_n3988, n1398, n_n4080, n1503 }; + assign n2183_1 = 8'h54 >> { n_n4018, n1497, preset }; + assign n2188_1 = 8'h54 >> { n_n4354, n1497, preset }; + assign n2193_1 = 8'h54 >> { n_n3797, n1497, preset }; + assign n2198_1 = 16'hf888 >> { n_n4316, n1494, n1496, n_n3739 }; + assign n2203_1 = 64'heaeaeac0eac0eac0 >> { n_n3936, n_n3099, n_n4392, n_n3646, n1496, n1494 }; + assign n2208_1 = 16'h3120 >> { n_n3099, n1563, preset, n1532 }; + assign n2213_1 = 32'd4169697416 >> { n_n3657, n_n4211, n1494, n_n3537, n1496 }; + assign n2218_1 = 32'd4169697416 >> { n_n3578, n_n4074, n1494, n_n3806, n1496 }; + assign n2223_1 = 8'h54 >> { n_n3087, n1497, preset }; + assign n2228_1 = 8'h54 >> { n_n4105, n1497, preset }; + assign n2233_1 = 8'h54 >> { n_n3262, n1497, preset }; + assign n2238_1 = 64'haeeaeaea84484848 >> { n1378, n_n3976, n_n3934, n_n4222, n1385, n_n4125 }; + assign n2243_1 = 8'h64 >> { n1388, n1503, n_n3814 }; + assign n2248_1 = 8'hfd >> { n1927, preset, n1642 }; + assign n2253_1 = 32'd4278120190 >> { nsr4_2, n1498, n1551, pdn, preset }; + assign pv10_4_4_ = 8'he4 >> { n_n4136, tin_pv10_4_4_, n_n3042 }; + assign pv11_4_4_ = 8'he4 >> { n_n3966, tin_pv11_4_4_, n_n4120 }; + assign pv6_7_7_ = 8'he4 >> { n_n3370, tin_pv6_7_7_, n_n4164 }; + assign pv2_0_0_ = 8'he4 >> { n_n3910, tin_pv2_0_0_, n_n3211 }; + assign pv10_3_3_ = 8'he4 >> { n_n3213, tin_pv10_3_3_, n_n4129 }; + assign pv1_2_2_ = 8'he4 >> { n_n3537, tin_pv1_2_2_, n_n3470 }; + assign pv11_3_3_ = 8'he4 >> { n_n3583, tin_pv11_3_3_, n_n3432 }; + assign pv4_3_3_ = 8'he4 >> { n_n4309, tin_pv4_3_3_, n_n3489 }; + assign pv10_2_2_ = 8'he4 >> { n_n3549, tin_pv10_2_2_, n_n3065 }; + assign pv11_2_2_ = 8'he4 >> { n_n3823, tin_pv11_2_2_, n_n3152 }; + assign pv6_0_0_ = 8'he4 >> { n_n3506, tin_pv6_0_0_, n_n3029 }; + assign pv2_1_1_ = 8'he4 >> { n_n3646, tin_pv2_1_1_, n_n3999 }; + assign pv10_1_1_ = 8'he4 >> { n_n3270, tin_pv10_1_1_, n_n3872 }; + assign pv1_3_3_ = 8'he4 >> { n_n4180, tin_pv1_3_3_, n_n3441 }; + assign pv11_1_1_ = 8'he4 >> { n_n4142, tin_pv11_1_1_, n_n4185 }; + assign pv4_4_4_ = 8'he4 >> { n_n3627, tin_pv4_4_4_, n_n4110 }; + assign pready_0_0_ = 8'he4 >> { n_n3354, tin_pready_0_0_, n_n4108 }; + assign pv10_0_0_ = 8'he4 >> { n_n4209, tin_pv10_0_0_, n_n4282 }; + assign pv11_0_0_ = 8'he4 >> { n_n3514, tin_pv11_0_0_, n_n3233 }; + assign pv6_1_1_ = 8'he4 >> { n_n3952, tin_pv6_1_1_, n_n3144 }; + assign pv2_2_2_ = 8'he4 >> { n_n3202, tin_pv2_2_2_, n_n4354 }; + assign pv1_4_4_ = 8'he4 >> { n_n3806, tin_pv1_4_4_, n_n3863 }; + assign pv4_5_5_ = 8'he4 >> { n_n3733, tin_pv4_5_5_, n_n3087 }; + assign pv6_2_2_ = 8'he4 >> { n_n3138, tin_pv6_2_2_, n_n3307 }; + assign pv2_3_3_ = 8'he4 >> { n_n3465, tin_pv2_3_3_, n_n3874 }; + assign pv1_5_5_ = 8'he4 >> { n_n3313, tin_pv1_5_5_, n_n3101 }; + assign pv4_6_6_ = 8'he4 >> { n_n3413, tin_pv4_6_6_, n_n3774 }; + assign pv6_3_3_ = 8'he4 >> { n_n3486, tin_pv6_3_3_, n_n3204 }; + assign pv2_4_4_ = 8'he4 >> { n_n3133, tin_pv2_4_4_, n_n3643 }; + assign pv1_6_6_ = 8'he4 >> { n_n3118, tin_pv1_6_6_, n_n4018 }; + assign pv4_7_7_ = 8'he4 >> { n_n4166, tin_pv4_7_7_, n_n4114 }; + assign pv6_4_4_ = 8'he4 >> { n_n4065, tin_pv6_4_4_, n_n3093 }; + assign pv2_5_5_ = 8'he4 >> { n_n3780, tin_pv2_5_5_, n_n4059 }; + assign pv1_7_7_ = 8'he4 >> { n_n4199, tin_pv1_7_7_, n_n3544 }; + assign pv4_0_0_ = 8'he4 >> { n_n3517, tin_pv4_0_0_, n_n3826 }; + assign pv6_5_5_ = 8'he4 >> { n_n4189, tin_pv6_5_5_, n_n3348 }; + assign pv2_6_6_ = 8'he4 >> { n_n3385, tin_pv2_6_6_, n_n3120 }; + assign pv10_7_7_ = 8'he4 >> { n_n3225, tin_pv10_7_7_, n_n3521 }; + assign pv1_0_0_ = 8'he4 >> { n_n4192, tin_pv1_0_0_, n_n3551 }; + assign pv11_7_7_ = 8'he4 >> { n_n3376, tin_pv11_7_7_, n_n3360 }; + assign pv4_1_1_ = 8'he4 >> { n_n3722, tin_pv4_1_1_, n_n4089 }; + assign pv10_6_6_ = 8'he4 >> { n_n3342, tin_pv10_6_6_, n_n3570 }; + assign pv11_6_6_ = 8'he4 >> { n_n4279, tin_pv11_6_6_, n_n3504 }; + assign pv6_6_6_ = 8'he4 >> { n_n3429, tin_pv6_6_6_, n_n3836 }; + assign pv2_7_7_ = 8'he4 >> { n_n3126, tin_pv2_7_7_, n_n4131 }; + assign pv10_5_5_ = 8'he4 >> { n_n4247, tin_pv10_5_5_, n_n3381 }; + assign pv1_1_1_ = 8'he4 >> { n_n3183, tin_pv1_1_1_, n_n3215 }; + assign pv11_5_5_ = 8'he4 >> { n_n3207, tin_pv11_5_5_, n_n3081 }; + assign pv4_2_2_ = 8'he4 >> { n_n4372, tin_pv4_2_2_, n_n4347 }; + assign n418 = 16'hea48 >> { n1378, n1373, n1385, n_n3475 }; + assign n1373 = 16'h566a >> { n1374, n_n3898, n_n4366, n_n4145 }; + assign n1374 = 8'h8e >> { n1375, n_n4047, n_n3916 }; + assign n1375 = 8'h17 >> { n1376, n_n4229, n_n3769 }; + assign n1376 = 8'h8e >> { n1377, n_n4316, n_n3901 }; + assign n1377 = 16'h077f >> { n_n4125, n_n4222, n_n3976, n_n3934 }; + assign n1378 = 16'h1101 >> { n_n4056, n1379, n1384, preset }; + assign n1379 = 8'h08 >> { n1380, n1383, n_n4045 }; + assign n1380 = 16'h7222 >> { n1382, n1381, n_n3604, n_n3658 }; + assign n1381 = 16'h0001 >> { n_n3922, n_n3968, n_n4201, n_n3533 }; + assign n1382 = 16'h0001 >> { n_n4337, n_n4349, n_n4071, n_n3892 }; + assign n1383 = 4'h2 >> { nsr3_17, nsr3_14 }; + assign n1384 = 8'h08 >> { n_n3557, n_n4056, n_n4057 }; + assign n1385 = 4'h2 >> { preset, n1384 }; + assign n1078_1 = 32'd2934604872 >> { n1378, n1374, n_n3898, n1385, n_n4366 }; + assign n1143_1 = 32'd680036488 >> { n1412, n_n4012, n1414, n_n4334, n1388 }; + assign n1388 = 32'd1431639381 >> { n_n3709, n_n3831, n1389, n1409, preset }; + assign n1389 = 64'haaa8a88822202000 >> { n_n3833, n1390, n1397, n_n4360, n_n4067, n_n4093 }; + assign n1390 = 64'h9696969696966996 >> { n_n4251, n_n4224, n1396, n1391, n_n3841, n_n4270 }; + assign n1391 = 64'he7216300ff63e721 >> { n1392, n_n3898, n_n4145, n1396, n_n4251, n_n4224 }; + assign n1392 = 32'd18175871 >> { n1393, n1394, n1395, n_n4229, n_n3916 }; + assign n1393 = 32'd1431655766 >> { n_n4182, n_n4383, n_n4159, n_n4160, n_n4330 }; + assign n1394 = 16'h5556 >> { n_n4383, n_n4159, n_n4160, n_n4182 }; + assign n1395 = 64'hfe7e765654141000 >> { n_n4316, n_n4222, n_n3976, n_n4159, n_n4160, n_n4383 }; + assign n1396 = 32'd1 >> { n_n4330, n_n4182, n_n4383, n_n4159, n_n4160 }; + assign n1397 = 32'd2315841454 >> { n1398, n1399, n1402, n_n4362, n_n4299 }; + assign n1398 = 64'h6696969969666696 >> { n1392, n1396, n_n3898, n_n4224, n_n4145, n_n4251 }; + assign n1399 = 4'h9 >> { n1400, n_n3898 }; + assign n1400 = 64'h55565666666a6aaa >> { n1393, n1394, n1395, n_n4229, n_n3916, n1401 }; + assign n1401 = 64'h5555555555555556 >> { n_n4330, n_n4182, n_n4383, n_n4159, n_n4160, n_n4224 }; + assign n1402 = 32'd352419671 >> { n1403, n1404, n1408, n_n4258, n_n3876 }; + assign n1403 = 32'd1718184345 >> { n1394, n1395, n_n4229, n1393, n_n3916 }; + assign n1404 = 64'h0001010f0f1f1fff >> { n1405, n1406, n_n3743, n_n3946, n1407, n_n3756 }; + assign n1405 = 64'h9969996969669969 >> { n_n3976, n_n4159, n_n4222, n_n4160, n_n4316, n_n4383 }; + assign n1406 = 16'h9969 >> { n_n3976, n_n4159, n_n4222, n_n4160 }; + assign n1407 = 4'h9 >> { n_n3976, n_n4159 }; + assign n1408 = 8'h69 >> { n1394, n1395, n_n4229 }; + assign n1409 = 64'haaa8a88822202000 >> { n_n3851, n1390, n1397, n_n4360, n_n4026, n1410 }; + assign n1410 = 4'h8 >> { nsr3_17, nen3_10 }; + assign n1411 = 8'h02 >> { n_n3851, n_n4067, n_n4026 }; + assign n1412 = 8'h80 >> { n1413, n_n4275, n_n3766 }; + assign n1413 = 8'h80 >> { n_n3814, n_n4227, n_n3724 }; + assign n1414 = 8'h08 >> { n_n3198, n_n3709, n_n3707 }; + assign n1658_1 = 32'd34080268 >> { n1416, n_n3814, preset, n_n3724, n1414 }; + assign n1416 = 16'h0080 >> { n_n3709, n1389, n1409, n_n3831 }; + assign n2058_1 = 16'hae84 >> { n1378, n1418, n1385, n_n4324 }; + assign n1418 = 64'haaa9a955aa959555 >> { n1374, n_n3475, n_n4145, n_n3898, n_n4366, n_n3841 }; + assign pv14_2_2_ = 4'h8 >> { n_n4153, n_n3358 }; + assign pv12_3_3_ = 4'h8 >> { n_n3367, n_n3631 }; + assign pv7_5_5_ = 4'h8 >> { n_n3679, n_n3130 }; + assign pv3_6_6_ = 4'h8 >> { n_n3057, n_n3252 }; + assign pv15_2_2_ = 4'h8 >> { n_n4037, n_n3113 }; + assign pv13_3_3_ = 4'h8 >> { n_n3404, n_n3600 }; + assign pv14_1_1_ = 4'h8 >> { n_n3038, n_n3012 }; + assign pv12_2_2_ = 4'h8 >> { n_n3576, n_n3067 }; + assign pv9_0_0_ = 4'h8 >> { n_n3890, n_n3128 }; + assign pv5_1_1_ = 4'h8 >> { n_n3287, n_n3443 }; + assign pv15_1_1_ = 4'h8 >> { n_n3108, n_n3606 }; + assign pv13_2_2_ = 4'h8 >> { n_n3463, n_n3379 }; + assign pv8_2_2_ = 4'h8 >> { n_n3055, n_n3456 }; + assign pv14_0_0_ = 4'h8 >> { n_n3903, n_n3761 }; + assign pv12_1_1_ = 4'h8 >> { n_n4390, n_n3264 }; + assign pv7_6_6_ = 4'h8 >> { n_n3617, n_n3670 }; + assign pv3_7_7_ = 4'h8 >> { n_n4102, n_n3590 }; + assign pv15_0_0_ = 4'h8 >> { n_n3188, n_n4003 }; + assign pv13_1_1_ = 4'h8 >> { n_n3150, n_n3221 }; + assign pv12_0_0_ = 4'h8 >> { n_n3339, n_n3098 }; + assign pv9_1_1_ = 4'h8 >> { n_n3044, n_n3024 }; + assign pv5_2_2_ = 4'h8 >> { n_n3350, n_n4286 }; + assign pv13_0_0_ = 4'h8 >> { n_n3434, n_n3061 }; + assign pv8_3_3_ = 4'h8 >> { n_n3091, n_n3146 }; + assign pv7_7_7_ = 4'h8 >> { n_n4077, n_n3136 }; + assign pv3_0_0_ = 4'h8 >> { n_n3828, n_n3173 }; + assign pv9_2_2_ = 4'h8 >> { n_n3157, n_n3736 }; + assign pv5_3_3_ = 4'h8 >> { n_n4236, n_n3321 }; + assign pv8_4_4_ = 4'h8 >> { n_n3095, n_n3344 }; + assign pv7_0_0_ = 4'h8 >> { n_n3069, n_n3161 }; + assign pv3_1_1_ = 4'h8 >> { n_n3461, n_n3048 }; + assign pv9_3_3_ = 4'h8 >> { n_n3749, n_n3906 }; + assign pv5_4_4_ = 4'h8 >> { n_n4213, n_n3793 }; + assign pv8_5_5_ = 4'h8 >> { n_n3331, n_n3116 }; + assign pv7_1_1_ = 4'h8 >> { n_n3971, n_n3415 }; + assign pv3_2_2_ = 4'h8 >> { n_n3739, n_n3190 }; + assign pv9_4_4_ = 4'h8 >> { n_n3650, n_n3687 }; + assign pv5_5_5_ = 4'h8 >> { n_n3408, n_n3266 }; + assign pv8_6_6_ = 4'h8 >> { n_n3223, n_n3180 }; + assign pv7_2_2_ = 4'h8 >> { n_n4105, n_n3497 }; + assign pv3_3_3_ = 4'h8 >> { n_n4342, n_n3274 }; + assign pv14_7_7_ = 4'h8 >> { n_n4241, n_n3449 }; + assign pv9_5_5_ = 4'h8 >> { n_n4290, n_n3985 }; + assign pv5_6_6_ = 4'h8 >> { n_n3237, n_n3567 }; + assign pv15_7_7_ = 4'h8 >> { n_n3648, n_n3079 }; + assign pv8_7_7_ = 4'h8 >> { n_n3529, n_n3525 }; + assign pv14_6_6_ = 4'h8 >> { n_n3262, n_n3713 }; + assign pv12_7_7_ = 4'h8 >> { n_n3720, n_n3764 }; + assign pv7_3_3_ = 4'h8 >> { n_n4303, n_n3411 }; + assign pv3_4_4_ = 4'h8 >> { n_n4162, n_n3729 }; + assign pv15_6_6_ = 4'h8 >> { n_n3020, n_n4375 }; + assign pv13_7_7_ = 4'h8 >> { n_n3394, n_n3372 }; + assign pv14_5_5_ = 4'h8 >> { n_n3663, n_n3008 }; + assign pv12_6_6_ = 4'h8 >> { n_n3896, n_n3782 }; + assign pv9_6_6_ = 4'h8 >> { n_n3239, n_n4243 }; + assign pv5_7_7_ = 4'h8 >> { n_n4005, n_n3111 }; + assign pv15_5_5_ = 4'h8 >> { n_n3674, n_n3277 }; + assign pv13_6_6_ = 4'h8 >> { n_n3797, n_n3155 }; + assign pv8_0_0_ = 4'h8 >> { n_n4320, n_n3014 }; + assign pv14_4_4_ = 4'h8 >> { n_n3089, n_n3326 }; + assign pv12_5_5_ = 4'h8 >> { n_n3337, n_n3619 }; + assign pv7_4_4_ = 4'h8 >> { n_n3053, n_n3073 }; + assign pv3_5_5_ = 4'h8 >> { n_n3142, n_n3436 }; + assign pv15_4_4_ = 4'h8 >> { n_n3667, n_n3305 }; + assign pv13_5_5_ = 4'h8 >> { n_n3777, n_n4139 }; + assign pv14_3_3_ = 4'h8 >> { n_n3316, n_n3396 }; + assign pv12_4_4_ = 4'h8 >> { n_n3175, n_n3231 }; + assign pv9_7_7_ = 4'h8 >> { n_n3040, n_n3319 }; + assign pv5_0_0_ = 4'h8 >> { n_n3572, n_n3195 }; + assign pv15_3_3_ = 4'h8 >> { n_n3051, n_n4172 }; + assign pv13_4_4_ = 4'h8 >> { n_n3758, n_n3075 }; + assign pv8_1_1_ = 4'h8 >> { n_n3883, n_n3938 }; + assign n353 = 32'd2290677896 >> { n1495, n1492, n_n3724, n_n4142, n1496 }; + assign n1492 = 16'ha820 >> { n_n3833, n1493, n_n4067, n1494 }; + assign n1493 = 8'he8 >> { n1390, n1397, n_n4360 }; + assign n1494 = 64'h0002000300000001 >> { n_n4151, preset_0_0_, nsr1_2, preset, pdn, nlc1_2 }; + assign n1495 = 32'd18197439 >> { n_n3851, n1390, n1397, n_n4360, n_n4026 }; + assign n1496 = 4'h1 >> { n1497, preset }; + assign n1497 = 4'h1 >> { n1498, pdn }; + assign n1498 = 16'h8a02 >> { n_n4151, preset_0_0_, nlc1_2, nsr1_2 }; + assign n358 = 16'h3120 >> { n_n3936, pv11_1_1_, preset, n1500 }; + assign n1500 = 4'h2 >> { ndn3_9, ndn3_8 }; + assign n363 = 64'hf2f0f2f0f3f1f2f0 >> { n1414, n_n3574, n_n3743, n1502, preset, n1416 }; + assign n1502 = 16'h2882 >> { n1406, n1504, n_n3574, n1503 }; + assign n1503 = 4'h2 >> { preset, n1414 }; + assign n1504 = 8'h06 >> { n_n3959, n_n3976, n_n4159 }; + assign n368 = 32'd4169697416 >> { n_n3035, n_n4157, n1494, n_n3008, n1496 }; + assign n373 = 64'hf2f0f2f0f3f1f2f0 >> { n1414, n_n3726, n_n4360, n1507, preset, n1416 }; + assign n1507 = 8'h82 >> { n1390, n1508, n1503 }; + assign n1508 = 64'h99959555aaa9a999 >> { n1398, n1399, n1509, n_n3988, n_n4080, n_n3726 }; + assign n1509 = 32'd4276791424 >> { n1403, n1408, n1510, n_n3818, n_n4040 }; + assign n1510 = 32'd4021193224 >> { n1405, n1406, n1504, n_n3574, n_n3995 }; + assign n378 = 32'd1413760068 >> { n_n4045, n1383, n1512, n_n3604, preset }; + assign n1512 = 8'h15 >> { n1382, n1381, n_n3658 }; + assign n383 = 8'h54 >> { n_n3144, n1497, preset }; + assign n388 = 8'h54 >> { n_n3782, n1497, preset }; + assign n393 = 8'h54 >> { n_n3067, n1497, preset }; + assign n398 = 16'h3120 >> { n_n4258, pv10_3_3_, preset, n1517 }; + assign n1517 = 4'h2 >> { ndn3_8, ndn3_7 }; + assign n403 = 16'hf888 >> { n1494, n_n4360, n1496, n_n3225 }; + assign n408 = 8'h54 >> { n_n3180, n1497, preset }; + assign n413 = 8'h54 >> { n_n3274, n1497, preset }; + assign n423 = 16'hf888 >> { n1494, n_n3458, n1496, n_n3687 }; + assign n428 = 8'h54 >> { n_n3381, n1497, preset }; + assign n433 = 32'd4169697416 >> { n_n3624, n_n3688, n1494, n_n3098, n1496 }; + assign n438 = 32'd1347507285 >> { ndn1_34, n1498, n_n4108, pdn, preset }; + assign n443 = 32'd2290677896 >> { n1380, n_n3901, n1494, n_n3497, n1496 }; + assign n448 = 16'h88f8 >> { n1403, n1494, n1496, n_n3793 }; + assign n453 = 16'h1302 >> { n_n4316, n1528, preset, n1531 }; + assign n1528 = 32'd2523306390 >> { n1536, n1540, n1542, n1529, n1534 }; + assign n1529 = 16'haa2a >> { n1380, n1533, n_n3901, n1530 }; + assign n1530 = 16'h0ddd >> { n1531, n_n3978, n1405, n1532 }; + assign n1531 = 4'h2 >> { ndn3_10, nen3_10 }; + assign n1532 = 4'h2 >> { ngfdn_3, nrq3_11 }; + assign n1533 = 4'h2 >> { ndn3_15, ngfdn_3 }; + assign n1534 = 32'd1381653 >> { n1532, n_n4316, n1531, n_n3858, n1535 }; + assign n1535 = 8'h80 >> { n1533, n_n3657, n_n4211 }; + assign n1536 = 32'd286347537 >> { n1380, n1533, n_n3934, n1537, n1538 }; + assign n1537 = 16'h0ddd >> { n1531, n_n3931, n1407, n1532 }; + assign n1538 = 32'd1381653 >> { n1532, n_n3976, n1531, n_n3878, n1539 }; + assign n1539 = 16'h0080 >> { ndn3_15, n_n3688, ngfdn_3, n_n3624 }; + assign n1540 = 16'haa2a >> { n1380, n1533, n_n4125, n1541 }; + assign n1541 = 16'h0ddd >> { n1531, n_n3328, n1406, n1532 }; + assign n1542 = 16'h2aaa >> { n_n3099, n1533, n_n3936, n1543 }; + assign n1543 = 16'h0777 >> { n_n4222, n1532, n1531, n_n3208 }; + assign n458 = 16'h3120 >> { n_n4349, pv6_0_0_, preset, n1545 }; + assign n1545 = 4'h2 >> { ndn3_7, ndn3_6 }; + assign n463 = 8'h54 >> { n_n3029, n1497, preset }; + assign n468 = 8'h54 >> { n_n3619, n1497, preset }; + assign n473 = 8'h54 >> { n_n3264, n1497, preset }; + assign n478 = 64'heaeaeac0eac0eac0 >> { n_n3035, n_n4157, n_n4288, n_n3780, n1496, n1494 }; + assign n483 = 16'h1101 >> { ndn3_4, n1551, ngfdn_3, preset }; + assign n1551 = 8'h2a >> { n1498, pready_0_0_, nsr3_3 }; + assign n488 = 8'h54 >> { n_n4114, n1497, preset }; + assign n493 = 8'h54 >> { n_n3146, n1497, preset }; + assign n498 = 16'hf888 >> { pv1_5_5_, n1556, n1555, n_n3511 }; + assign n1555 = 8'h54 >> { ndn3_4, n1551, preset }; + assign n1556 = 8'h01 >> { n1551, preset, ndn3_4 }; + assign n503 = 8'h54 >> { n_n3152, n1497, preset }; + assign n508 = 8'hfe >> { n1559, n_n3833, preset }; + assign n1559 = 4'h8 >> { n1389, n1409 }; + assign n513 = 8'h54 >> { n_n4282, n1497, preset }; + assign n518 = 8'h54 >> { n_n3305, n1497, preset }; + assign n523 = 16'h3120 >> { n_n4392, n1563, preset, n1533 }; + assign n1563 = 8'h96 >> { n1536, n1540, n1542 }; + assign n528 = 16'h3120 >> { n_n4224, pv4_5_5_, preset, n1565 }; + assign n1565 = 4'h2 >> { ndn3_6, ndn3_5 }; + assign n533 = 4'h2 >> { preset, n1567 }; + assign n1567 = 16'h2a08 >> { n1568, n1390, n1508, n1414 }; + assign n1568 = 64'hb9971002bff71662 >> { n1569, n1398, n1509, n_n3988, n1399, n_n4080 }; + assign n1569 = 64'heffd4668e99d4008 >> { n1570, n1403, n1510, n_n3818, n1408, n_n4040 }; + assign n1570 = 64'hefe94640effd4668 >> { n_n3959, n1405, n1407, n_n3574, n1406, n_n3995 }; + assign n538 = 8'h54 >> { n_n3204, n1497, preset }; + assign n543 = 8'h54 >> { n_n3024, n1497, preset }; + assign n548 = 8'h54 >> { n_n4139, n1497, preset }; + assign n553 = 8'h02 >> { preset, ngfdn_3, ndn3_15 }; + assign n558 = 64'heaeaeac0eac0eac0 >> { n_n3578, n_n4074, n_n3458, n_n3133, n1496, n1494 }; + assign n2028_1 = 4'h2 >> { preset, n1532 }; + assign n563 = 16'h1302 >> { n_n4074, n1578, preset, n1532 }; + assign n1578 = 32'd2576782950 >> { n1581, n1583, n1586, n1579, n1584 }; + assign n1579 = 32'd4539717 >> { n_n4021, n1531, n1532, n1403, n1580 }; + assign n1580 = 8'h08 >> { n1380, n1533, n_n4047 }; + assign n1581 = 32'd4539717 >> { n_n3281, n1531, n1532, n1408, n1582 }; + assign n1582 = 8'h08 >> { n1380, n1533, n_n3769 }; + assign n1583 = 32'd3942547624 >> { n1529, n1536, n1540, n1542, n1534 }; + assign n1584 = 16'h2aaa >> { n_n4074, n1533, n_n3578, n1585 }; + assign n1585 = 16'h0777 >> { n_n3916, n1532, n1531, n_n3886 }; + assign n1586 = 16'h2aaa >> { n_n3250, n1533, n_n3085, n1587 }; + assign n1587 = 16'h0777 >> { n_n4229, n1532, n1531, n_n4294 }; + assign n568 = 16'hf888 >> { n1494, n_n3743, n1496, n_n3270 }; + assign n573 = 16'hf888 >> { pv1_2_2_, n1556, n1555, n_n3858 }; + assign n578 = 8'h54 >> { n_n3456, n1497, preset }; + assign n583 = 8'h54 >> { n_n3521, n1497, preset }; + assign n588 = 8'h54 >> { n_n3081, n1497, preset }; + assign n593 = 64'hd5c0d5c0d5d5d5c0 >> { n1596, n_n3892, n1597, n_n4381, n1594, preset }; + assign n1594 = 32'd1145324613 >> { n_n3493, n1380, n_n4045, n1595, preset }; + assign n1595 = 64'h5504554451005544 >> { n_n4056, n1383, n_n3493, n1380, n_n4045, n1384 }; + assign n1596 = 32'd4284333853 >> { n_n4056, n_n3493, n1383, n_n4045, n1380 }; + assign n1597 = 16'h8828 >> { n_n4052, n1598, n_n4381, n1384 }; + assign n1598 = 8'h08 >> { n_n3865, n1599, n_n3954 }; + assign n1599 = 8'h01 >> { n_n3845, n_n3955, n_n4029 }; + assign n598 = 32'd2290677896 >> { n1380, n_n3475, n1494, n_n3670, n1496 }; + assign n603 = 16'h3120 >> { n_n4211, pv11_2_2_, preset, n1500 }; + assign n608 = 32'd526344 >> { n1383, n1380, preset, n_n4045, n_n3493 }; + assign n613 = 16'h1302 >> { n_n3495, n1528, preset, n1533 }; + assign n618 = 16'h1302 >> { n_n3916, n1578, preset, n1531 }; + assign n623 = 8'h54 >> { n_n3195, n1497, preset }; + assign n628 = 16'hf888 >> { n1494, n_n3242, n1496, n_n3525 }; + assign n633 = 16'hf888 >> { n_n3916, n1494, n1496, n_n3729 }; + assign n638 = 16'h3120 >> { n_n3876, pv10_4_4_, preset, n1517 }; + assign n643 = 16'h1110 >> { ndn3_5, ndn3_4, preset, ngfdn_3 }; + assign n648 = 16'hf888 >> { n1494, n_n3946, n1496, n_n3549 }; + assign n653 = 8'h54 >> { n_n3489, n1497, preset }; + assign n658 = 32'd4169697416 >> { n_n3242, n_n3170, n1494, n_n3764, n1496 }; + assign n663 = 16'h3120 >> { n_n3281, pv2_3_3_, preset, n1614 }; + assign n1614 = 4'h2 >> { ndn3_5, ndn3_4 }; + assign n668 = 4'hd >> { n1617, n1616 }; + assign n1616 = 32'd67392772 >> { n1410, n_n4093, n1411, n1389, preset }; + assign n1617 = 32'd2315954730 >> { n1568, n1390, n1414, n1508, n_n3707 }; + assign n673 = 16'hf888 >> { n1494, n_n4159, n1496, n_n3517 }; + assign n678 = 16'h3120 >> { n_n4160, pv4_1_1_, preset, n1565 }; + assign n683 = 16'h3120 >> { n_n4222, n1563, preset, n1531 }; + assign n688 = 32'd4169697416 >> { n_n3936, n_n3099, n1494, n_n3012, n1496 }; + assign n693 = 16'h3120 >> { n_n4071, pv6_5_5_, preset, n1545 }; + assign n698 = 8'h54 >> { n_n3372, n1497, preset }; + assign n703 = 16'hf888 >> { n1494, n_n4074, n1496, n_n3344 }; + assign n708 = 16'h3120 >> { n_n3688, n1626, preset, n1532 }; + assign n1626 = 32'd1718003302 >> { n1380, n1533, n_n3934, n1537, n1538 }; + assign n713 = 64'heaeaeac0eac0eac0 >> { n_n3242, n_n3170, n_n4233, n_n3079, n1496, n1494 }; + assign n718 = 32'd4169697416 >> { n_n3035, n_n4157, n1494, n_n3313, n1496 }; + assign n723 = 8'h54 >> { n_n3411, n1497, preset }; + assign n728 = 32'd4169697416 >> { n_n3578, n_n4074, n1494, n_n3231, n1496 }; + assign n733 = 8'h54 >> { n_n3396, n1497, preset }; + assign n738 = 8'h54 >> { n_n3432, n1497, preset }; + assign n743 = 8'h54 >> { n_n3606, n1497, preset }; + assign n748 = 16'hf888 >> { n1494, n_n4224, n1496, n_n3733 }; + assign n753 = 16'h3120 >> { n_n3556, pv11_6_6_, preset, n1500 }; + assign n758 = 64'h5101554550005444 >> { n_n4040, n1637, n_n3876, n1416, n1414, preset }; + assign n1637 = 32'd1718184345 >> { n1408, n1510, n_n3818, n1403, n_n4040 }; + assign n763 = 8'h54 >> { n_n3120, n1497, preset }; + assign n768 = 16'hf888 >> { n_n4222, n1494, n1496, n_n3221 }; + assign n773 = 16'hf888 >> { n_n3976, n1494, n1496, n_n3173 }; + assign n778 = 64'h4444444454444444 >> { n_n4026, n_n3831, n1642, n1493, n_n3851, preset }; + assign n1642 = 8'h08 >> { n1411, n1389, n1410 }; + assign n783 = 64'heaeaeac0eac0eac0 >> { n_n3657, n_n4211, n_n3495, n_n3113, n1496, n1494 }; + assign n788 = 16'h3120 >> { n_n3242, n1645, preset, n1532 }; + assign n1645 = 64'h555656aa556a6aaa >> { n1646, n1650, n1654, n1652, n1656, n1647 }; + assign n1646 = 32'd4276791424 >> { n1579, n1581, n1583, n1586, n1584 }; + assign n1647 = 32'd1066768793 >> { n1532, n_n3841, n1390, n1648, n1649 }; + assign n1648 = 32'd2004289399 >> { n1380, n_n4324, n1533, n_n3451, n1531 }; + assign n1649 = 32'd125269879 >> { n_n3170, n1533, n_n3242, n_n3259, n1531 }; + assign n1650 = 8'h2a >> { n1532, n1398, n1651 }; + assign n1651 = 32'd2004289399 >> { n1380, n_n3475, n1533, n_n4062, n1531 }; + assign n1652 = 32'd4539717 >> { n_n3854, n1531, n1532, n1399, n1653 }; + assign n1653 = 8'h08 >> { n1380, n1533, n_n4366 }; + assign n1654 = 16'h2aaa >> { n_n4122, n1533, n_n3556, n1655 }; + assign n1655 = 16'h0777 >> { n_n4145, n1532, n1531, n_n3919 }; + assign n1656 = 8'h2a >> { n_n3898, n1532, n1657 }; + assign n1657 = 32'd125269879 >> { n_n4157, n1533, n_n3035, n_n3511, n1531 }; + assign n793 = 32'd4169697416 >> { n_n3556, n_n4122, n1494, n_n3118, n1496 }; + assign n798 = 32'd2290677896 >> { n1495, n1492, n_n3483, n_n3376, n1496 }; + assign n803 = 8'h54 >> { n_n4089, n1497, preset }; + assign n808 = 16'hf888 >> { n1494, n_n4392, n1496, n_n3044 }; + assign n813 = 16'hf888 >> { n1494, n_n4330, n1496, n_n3627 }; + assign n818 = 16'h3120 >> { n_n3035, pv11_5_5_, preset, n1500 }; + assign n823 = 16'hf222 >> { n1496, n_n3111, n1390, n1494 }; + assign n828 = 8'h54 >> { n_n3321, n1497, preset }; + assign n833 = 8'h54 >> { n_n3443, n1497, preset }; + assign n838 = 8'h54 >> { n_n3215, n1497, preset }; + assign n843 = 16'h1110 >> { ndn3_10, nen3_10, preset, ngfdn_3 }; + assign n848 = 64'heaeaeac0eac0eac0 >> { n_n3085, n_n3250, n_n4351, n_n4172, n1496, n1494 }; + assign n853 = 32'd269488400 >> { preset_0_0_, nsr1_2, nlc1_2, pdn, preset }; + assign n858 = 8'h54 >> { n_n3590, n1497, preset }; + assign n863 = 8'h54 >> { n_n4110, n1497, preset }; + assign n868 = 32'd4169697416 >> { n_n3657, n_n4211, n1494, n_n3576, n1496 }; + assign n873 = 8'h54 >> { n_n4129, n1497, preset }; + assign n878 = 16'hf888 >> { n1494, n_n4071, n1496, n_n4189 }; + assign n883 = 16'h88f8 >> { n1405, n1494, n1496, n_n4286 }; + assign n888 = 16'h3120 >> { n_n4383, pv4_2_2_, preset, n1565 }; + assign n349_1 = 4'h2 >> { preset, n1497 }; + assign n893 = 8'h54 >> { n_n3567, n1497, preset }; + assign n898_1 = 16'h3120 >> { n_n3892, pv6_6_6_, preset, n1545 }; + assign n903_1 = 8'h54 >> { n_n3075, n1497, preset }; + assign n908_1 = 32'd1145373701 >> { ndn1_34, n1498, pdn, n_n3354, preset }; + assign n913_1 = 64'heaeaeac0eac0eac0 >> { n_n3085, n_n3250, n_n4351, n_n3465, n1496, n1494 }; + assign n918_1 = 16'h1110 >> { ndn3_5, ndn3_6, preset, ngfdn_3 }; + assign n923_1 = 8'h54 >> { n_n3617, n1497, preset }; + assign n928_1 = 8'h54 >> { n_n4162, n1497, preset }; + assign n933_1 = 32'd2290677896 >> { n1495, n1492, n_n4012, n_n3207, n1496 }; + assign n938_1 = 8'h54 >> { n_n4120, n1497, preset }; + assign n943_1 = 8'h54 >> { n_n3065, n1497, preset }; + assign n948_1 = 8'h54 >> { n_n4005, n1497, preset }; + assign n953_1 = 8'h54 >> { n_n3266, n1497, preset }; + assign n958_1 = 16'h3120 >> { n_n4337, pv6_7_7_, preset, n1545 }; + assign n963_1 = 8'h54 >> { n_n3600, n1497, preset }; + assign n968_1 = 8'h54 >> { n_n3415, n1497, preset }; + assign n973_1 = 16'hf888 >> { n1494, n_n4095, n1496, n_n4243 }; + assign n978_1 = 8'h54 >> { n_n3872, n1497, preset }; + assign n983_1 = 8'h54 >> { n_n3648, n1497, preset }; + assign n988_1 = 32'd4169697416 >> { n_n3657, n_n4211, n1494, n_n3358, n1496 }; + assign n993_1 = 8'h54 >> { n_n3350, n1497, preset }; + assign n998_1 = 16'h1110 >> { ndn3_6, ndn3_7, ngfdn_3, preset }; + assign n1003_1 = 8'h54 >> { n_n3116, n1497, preset }; + assign n1008_1 = 32'd2290677896 >> { n1495, n1492, n_n3766, n_n3583, n1496 }; + assign n1013_1 = 16'hf888 >> { n1494, n_n4351, n1496, n_n3906 }; + assign n1018_1 = 8'h54 >> { n_n4131, n1497, preset }; + assign n1023_1 = 32'd4169697416 >> { n_n3085, n_n3250, n1494, n_n3316, n1496 }; + assign n1028_1 = 16'hf888 >> { n_n3976, n1494, n1496, n_n3061 }; + assign n1033_1 = 16'hf888 >> { n_n4222, n1494, n1496, n_n3048 }; + assign n1038_1 = 16'hf888 >> { pv1_4_4_, n1556, n1555, n_n3886 }; + assign n1043_1 = 16'hf888 >> { pv1_6_6_, n1556, n1555, n_n3919 }; + assign n1048_1 = 16'hf888 >> { n1494, n_n3608, n1496, n_n3128 }; + assign n1053_1 = 64'hf2f0f2f0f3f1f2f0 >> { n1414, n_n3995, n_n3946, n1712, preset, n1416 }; + assign n1712 = 64'h8228828228288228 >> { n1406, n1504, n_n3574, n1405, n_n3995, n1503 }; + assign n1058_1 = 8'h54 >> { n_n4213, n1497, preset }; + assign n1063_1 = 32'd4169697416 >> { n_n3624, n_n3688, n1494, n_n3761, n1496 }; + assign n1068_1 = 16'h1110 >> { ndn3_7, ndn3_8, preset, ngfdn_3 }; + assign n1073_1 = 8'h54 >> { n_n3252, n1497, preset }; + assign n1083_1 = 16'h3120 >> { n_n3328, pv2_1_1_, preset, n1614 }; + assign n1088_1 = 64'hf2f0f2f0f3f1f2f0 >> { n1414, n_n3988, n_n4362, n1719, preset, n1416 }; + assign n1719 = 16'h8228 >> { n1399, n1509, n_n3988, n1503 }; + assign n1093_1 = 8'h54 >> { n_n3348, n1497, preset }; + assign n1098_1 = 8'h54 >> { n_n3544, n1497, preset }; + assign n1103_1 = 8'h54 >> { n_n3101, n1497, preset }; + assign n1108_1 = 32'd2290677896 >> { n1495, n1492, n_n4334, n_n4279, n1496 }; + assign n1113_1 = 32'd4169697416 >> { n_n3556, n_n4122, n1494, n_n3896, n1496 }; + assign n1118_1 = 16'hf888 >> { n1494, n_n3495, n1496, n_n3736 }; + assign n1123_1 = 16'h3120 >> { n_n4251, pv4_6_6_, preset, n1565 }; + assign n1128_1 = 8'h54 >> { n_n3650, n1497, preset }; + assign n1133_1 = 8'h54 >> { n_n3307, n1497, preset }; + assign n1138_1 = 16'hf888 >> { pv1_3_3_, n1556, n1555, n_n4294 }; + assign n1148_1 = 64'h2031203131312031 >> { n1596, n_n4201, n1731, n_n3955, preset, n1595 }; + assign n1731 = 64'hb7b7b7b7b7b7b715 >> { n1380, n_n4045, n_n3493, n_n3954, n1384, n_n3955 }; + assign n1153_1 = 8'h54 >> { n_n4164, n1497, preset }; + assign n1158_1 = 16'hf888 >> { n_n4145, n1494, n1496, n_n3155 }; + assign n1163_1 = 8'h54 >> { n_n3749, n1497, preset }; + assign n1168_1 = 16'h3120 >> { n_n4233, n1645, preset, n1533 }; + assign n1173_1 = 8'h54 >> { n_n4347, n1497, preset }; + assign n1178_1 = 8'h54 >> { n_n3826, n1497, preset }; + assign n1183_1 = 8'h54 >> { n_n3360, n1497, preset }; + assign n1188_1 = 16'h1302 >> { n_n3458, n1578, preset, n1533 }; + assign n1193_1 = 8'h54 >> { n_n3093, n1497, preset }; + assign n1198_1 = 8'h54 >> { n_n3157, n1497, preset }; + assign n1203_1 = 16'hf888 >> { n1494, n_n4349, n1496, n_n3506 }; + assign n1208_1 = 8'h54 >> { n_n3161, n1497, preset }; + assign n1213_1 = 16'hf888 >> { n1494, n_n4233, n1496, n_n3319 }; + assign n1218_1 = 16'hf888 >> { n1494, n_n3892, n1496, n_n3429 }; + assign n1223_1 = 32'd2290677896 >> { n1380, n_n4125, n1494, n_n3971, n1496 }; + assign n1228_1 = 32'd4169697416 >> { n_n3242, n_n3170, n1494, n_n3449, n1496 }; + assign n1233_1 = 16'h3120 >> { n_n4270, pv4_7_7_, preset, n1565 }; + assign n1238_1 = 16'h3120 >> { n_n4288, n1750, preset, n1533 }; + assign n1750 = 8'h69 >> { n1646, n1652, n1656 }; + assign n1243_1 = 32'd4169697416 >> { n_n3936, n_n3099, n1494, n_n3183, n1496 }; + assign n1248_1 = 8'h54 >> { n_n3130, n1497, preset }; + assign n1253_1 = 32'd3937290372 >> { n1378, n1375, n_n3916, n1385, n_n4047 }; + assign n1258 = 16'h3120 >> { n_n3978, pv2_2_2_, preset, n1614 }; + assign n1263_1 = 8'h54 >> { n_n3239, n1497, preset }; + assign n1268_1 = 32'd823336962 >> { n_n4145, n1758, n1757, preset, n1531 }; + assign n1757 = 8'he8 >> { n1646, n1652, n1656 }; + assign n1758 = 4'h6 >> { n1650, n1654 }; + assign n1273_1 = 8'h54 >> { n_n3890, n1497, preset }; + assign n1278_1 = 64'heaeaeac0eac0eac0 >> { n_n3624, n_n3688, n_n3608, n_n4003, n1496, n1494 }; + assign n1283_1 = 16'hf888 >> { n1494, n_n3085, n1496, n_n3091 }; + assign n1288_1 = 16'hf888 >> { n1494, n_n4288, n1496, n_n3985 }; + assign n1293_1 = 8'h54 >> { n_n3326, n1497, preset }; + assign n1298_1 = 64'h2031203131312031 >> { n1596, n_n4071, n1765, n_n4052, preset, n1595 }; + assign n1765 = 64'hb7b7b7b7b7b7b715 >> { n1380, n_n4045, n_n3493, n1598, n1384, n_n4052 }; + assign n1303_1 = 8'hfe >> { preset, pdn, nsr4_2 }; + assign n1308_1 = 64'hd5c0d5c0d5d5d5c0 >> { n1596, n_n4337, n1768, n_n4099, n1594, preset }; + assign n1768 = 16'h2888 >> { n1598, n1769, n_n4099, n1384 }; + assign n1769 = 4'h1 >> { n_n4381, n_n4052 }; + assign n1313_1 = 8'h54 >> { n_n4375, n1497, preset }; + assign n1318_1 = 8'ha8 >> { n_n4067, n1559, n1616 }; + assign n1323_1 = 8'h54 >> { n_n4290, n1497, preset }; + assign n1328_1 = 16'h3120 >> { n_n3898, n1750, preset, n1531 }; + assign n1333_1 = 32'd823336962 >> { n_n4122, n1758, n1757, preset, n1532 }; + assign n1338_1 = 8'h54 >> { n_n3774, n1497, preset }; + assign n1343_1 = 8'h54 >> { n_n3014, n1497, preset }; + assign n1348_1 = 8'h54 >> { n_n4241, n1497, preset }; + assign n1353_1 = 16'hf888 >> { n1494, n_n4201, n1496, n_n3952 }; + assign n1358_1 = 16'hf888 >> { n1496, n_n3237, n1398, n1494 }; + assign n1363_1 = 16'h3120 >> { n_n3968, pv6_2_2_, preset, n1545 }; + assign n1368_1 = 16'h3120 >> { n_n3922, pv6_4_4_, preset, n1545 }; + assign n1373_1 = 8'h54 >> { n_n3551, n1497, preset }; + assign n1378_1 = 8'h54 >> { n_n3379, n1497, preset }; + assign n1383_1 = 64'h1020002012222222 >> { n1416, n1413, n_n3766, n1414, preset, n_n4275 }; + assign n1388_1 = 8'h54 >> { n_n3570, n1497, preset }; + assign n1393_1 = 16'h3120 >> { n_n3854, pv2_5_5_, preset, n1614 }; + assign n1398_1 = 32'd4294835709 >> { n1383, n1380, n1788, preset, n_n4045 }; + assign n1788 = 4'h2 >> { n1789, n_n4057 }; + assign n1789 = 64'h0000000000000080 >> { n_n3865, n_n3954, n_n4099, n1384, n1599, n1769 }; + assign n1403_1 = 16'h3120 >> { n_n3451, pv2_7_7_, preset, n1614 }; + assign n1408_1 = 8'h54 >> { n_n4037, n1497, preset }; + assign n1413_1 = 16'hf222 >> { n1496, n_n3408, n1399, n1494 }; + assign n1418_1 = 16'h3120 >> { n_n4229, n1794, preset, n1531 }; + assign n1794 = 8'h69 >> { n1581, n1583, n1586 }; + assign n1423_1 = 16'h3120 >> { n_n4201, pv6_1_1_, preset, n1545 }; + assign n1428_1 = 8'h54 >> { n_n3339, n1497, preset }; + assign n1433_1 = 16'h3120 >> { n_n4362, pv10_5_5_, preset, n1517 }; + assign n1438_1 = 32'd680036488 >> { n1412, n1414, n1799, n_n3483, n1388 }; + assign n1799 = 8'ha2 >> { n_n4012, n1503, n_n4334 }; + assign n1443_1 = 4'h2 >> { preset, n1789 }; + assign n1448_1 = 8'h54 >> { n_n4185, n1497, preset }; + assign n1453_1 = 32'd2290677896 >> { n1380, n_n3934, n1494, n_n3069, n1496 }; + assign n1458_1 = 8'h54 >> { n_n3643, n1497, preset }; + assign n1463_1 = 16'hf888 >> { n_n4229, n1494, n1496, n_n3404 }; + assign n1468_1 = 16'hf888 >> { n_n4145, n1494, n1496, n_n3057 }; + assign n1473_1 = 64'heaeaeac0eac0eac0 >> { n_n3556, n_n4122, n_n4095, n_n3020, n1496, n1494 }; + assign n1478_1 = 8'h54 >> { n_n3828, n1497, preset }; + assign n1483_1 = 32'd4169697416 >> { n_n3085, n_n3250, n1494, n_n3631, n1496 }; + assign n1488_1 = 16'hf888 >> { n1494, n_n3968, n1496, n_n3138 }; + assign n1493_1 = 16'heefe >> { ngfdn_3, n1498, pdn, preset }; + assign n1498_1 = 16'hf888 >> { n1494, n_n3922, n1496, n_n4065 }; + assign n1503_1 = 32'd2290677896 >> { n1380, n_n4366, n1494, n_n3679, n1496 }; + assign n1508_1 = 16'h88f8 >> { n1406, n1494, n1496, n_n3287 }; + assign n1513_1 = 16'h3120 >> { n_n4351, n1794, preset, n1533 }; + assign n1518_1 = 8'h54 >> { n_n4059, n1497, preset }; + assign n1523_1 = 16'hf888 >> { n_n3898, n1494, n1496, n_n3436 }; + assign n1528_1 = 16'h1110 >> { ndn3_9, nen3_10, preset, ngfdn_3 }; + assign n1533_1 = 8'h54 >> { n_n3461, n1497, preset }; + assign n1538_1 = 16'h2888 >> { n1414, n1412, n_n4012, n1388 }; + assign n1543_1 = 8'h54 >> { n_n3051, n1497, preset }; + assign n1548_1 = 32'd2290677896 >> { n1380, n_n4047, n1494, n_n3073, n1496 }; + assign n1553_1 = 16'hf888 >> { n_n3898, n1494, n1496, n_n3777 }; + assign n1558_1 = 32'd538976800 >> { n1567, n_n3709, n1416, preset, n_n3707 }; + assign n1563_1 = 16'h3120 >> { n_n3946, pv10_2_2_, preset, n1517 }; + assign n1568_1 = 16'h3120 >> { n_n3085, n1794, preset, n1532 }; + assign n1573_1 = 16'hf888 >> { pv1_7_7_, n1556, n1555, n_n3259 }; + assign n1578_1 = 8'h54 >> { n_n3504, n1497, preset }; + assign n1583_1 = 8'hfd >> { n1788, preset, n1379 }; + assign n1588_1 = 64'h8d8d8c8dafaf8caf >> { n1384, n1596, n_n4349, n1594, preset, n_n3954 }; + assign n1593_1 = 32'd2290677896 >> { n1380, n_n4324, n1494, n_n3136, n1496 }; + assign n1598_1 = 16'hf888 >> { n1494, n_n4383, n1496, n_n4372 }; + assign n1603_1 = 16'h88f8 >> { n1408, n1494, n1496, n_n4236 }; + assign n1608_1 = 8'h54 >> { n_n3040, n1497, preset }; + assign n1613_1 = 8'h54 >> { n_n3874, n1497, preset }; + assign n1618_1 = 8'h54 >> { n_n3999, n1497, preset }; + assign n1623_1 = 16'hf888 >> { n1494, n_n4122, n1496, n_n3223 }; + assign n1628_1 = 8'h02 >> { preset, pdn, ndn1_34 }; + assign n1633_1 = 16'h3120 >> { n_n3743, pv10_1_1_, preset, n1517 }; + assign n1638_1 = 16'h1302 >> { n_n3657, n1528, preset, n1532 }; + assign n1643_1 = 16'hf888 >> { n1494, n_n4258, n1496, n_n3213 }; + assign n1648_1 = 8'h54 >> { n_n3095, n1497, preset }; + assign n1653_1 = 8'h54 >> { n_n3663, n1497, preset }; + assign n1663_1 = 8'h54 >> { n_n3038, n1497, preset }; + assign n1668_1 = 16'hf888 >> { n1494, n_n4337, n1496, n_n3370 }; + assign n1673_1 = 16'h3120 >> { n_n3624, pv11_0_0_, preset, n1500 }; + assign n1678_1 = 16'h3120 >> { n_n3578, pv11_4_4_, preset, n1500 }; + assign n1683_1 = 32'd4169697416 >> { n_n3556, n_n4122, n1494, n_n3713, n1496 }; + assign n1688_1 = 32'd4169697416 >> { n_n3578, n_n4074, n1494, n_n3089, n1496 }; + assign n1693_1 = 8'h54 >> { n_n3211, n1497, preset }; + assign n1698_1 = 8'h54 >> { n_n3367, n1497, preset }; + assign n1703_1 = 8'h54 >> { n_n3434, n1497, preset }; + assign n1708_1 = 64'heaeaeac0eac0eac0 >> { n_n3242, n_n3170, n_n4233, n_n3126, n1496, n1494 }; + assign n1713_1 = 32'd4169697416 >> { n_n3624, n_n3688, n1494, n_n4192, n1496 }; + assign n1718_1 = 16'hf888 >> { n1494, n_n3876, n1496, n_n4136 }; + assign n1723_1 = 8'h54 >> { n_n3053, n1497, preset }; + assign n1728_1 = 8'h54 >> { n_n3938, n1497, preset }; + assign n1733_1 = 32'd2934604872 >> { n1378, n1376, n_n4229, n1385, n_n3769 }; + assign n1738_1 = 32'd4169697416 >> { n_n3936, n_n3099, n1494, n_n4390, n1496 }; + assign n1743_1 = 64'hefeeefeeffeeefee >> { n1411, n1389, nsr3_17, nen3_10, preset, pdn }; + assign n1748_1 = 8'h54 >> { n_n3903, n1497, preset }; + assign n1753_1 = 64'h2220202022200020 >> { n_n3604, n1512, n1383, n_n3658, preset, n_n4045 }; + assign n1758_1 = 16'h1101 >> { nrq3_11, nsr3_14, ngfdn_3, preset }; + assign n1763_1 = 64'hf2f0f2f0f3f1f2f0 >> { n1414, n_n3818, n_n4258, n1864, preset, n1416 }; + assign n1864 = 16'h8228 >> { n1408, n1510, n_n3818, n1503 }; + assign n1768_1 = 16'h3120 >> { n_n3533, pv6_3_3_, preset, n1545 }; + assign n1773_1 = 16'hf888 >> { n_n4316, n1494, n1496, n_n3463 }; + assign n1778_1 = 8'h54 >> { n_n3175, n1497, preset }; + assign n1783_1 = 16'hf888 >> { n1494, n_n3657, n1496, n_n3055 }; + assign n1788_1 = 64'heaeaeac0eac0eac0 >> { n_n3657, n_n4211, n_n3495, n_n3202, n1496, n1494 }; + assign n1793_1 = 64'heaeaeac0eac0eac0 >> { n_n3556, n_n4122, n_n4095, n_n3385, n1496, n1494 }; + assign n1798_1 = 8'h54 >> { n_n4077, n1497, preset }; + assign n1803_1 = 8'h54 >> { n_n3142, n1497, preset }; + assign n1808_1 = 32'd3937290372 >> { n1378, n1377, n_n4316, n1385, n_n3901 }; + assign n1813_1 = 32'd2867462216 >> { n1378, preset, n_n3976, n1384, n_n3934 }; + assign n1818_1 = 32'd2290677896 >> { n1495, n1492, n_n4227, n_n3823, n1496 }; + assign n1823_1 = 16'hf888 >> { n1494, n_n4160, n1496, n_n3722 }; + assign n1828_1 = 16'hf888 >> { n1494, n_n4182, n1496, n_n4309 }; + assign n1833_1 = 16'h3120 >> { n_n4159, pv4_0_0_, preset, n1565 }; + assign n1838_1 = 16'h3120 >> { n_n4330, pv4_4_4_, preset, n1565 }; + assign n1843_1 = 8'h54 >> { n_n3836, n1497, preset }; + assign n1848_1 = 8'h54 >> { n_n3470, n1497, preset }; + assign n1853_1 = 16'hf888 >> { n1494, n_n4157, n1496, n_n3331 }; + assign n1858_1 = 16'hf888 >> { n1494, n_n3099, n1496, n_n3883 }; + assign n1863_1 = 16'h3120 >> { n_n4299, pv10_6_6_, preset, n1517 }; + assign n1868_1 = 16'h3120 >> { n_n4157, n1750, preset, n1532 }; + assign n1873_1 = 16'h1110 >> { ndn3_9, ndn3_8, preset, ngfdn_3 }; + assign n1878_1 = 16'hf888 >> { pv1_1_1_, n1556, n1555, n_n3208 }; + assign n1883_1 = 8'h54 >> { n_n3190, n1497, preset }; + assign n1888_1 = 64'hd5c0d5c0d5d5d5c0 >> { n1596, n_n3533, n1890, n_n4029, n1594, preset }; + assign n1890 = 32'd2290649128 >> { n_n3845, n_n3955, n_n3954, n_n4029, n1384 }; + assign n1893_1 = 8'h54 >> { n_n3042, n1497, preset }; + assign n1898_1 = 64'hfeeeffeefeeefeee >> { n_n4045, n1380, nsr3_14, nsr3_17, preset, pdn }; + assign n1903_1 = 32'd4008636158 >> { preset_0_0_, nlc1_2, nsr1_2, n_n4151, preset }; + assign n1908_1 = 8'h54 >> { n_n3188, n1497, preset }; + assign n1913_1 = 32'd2290677896 >> { n1380, n_n3769, n1494, n_n4303, n1496 }; + assign n1918_1 = 16'h3120 >> { n_n3250, pv11_3_3_, preset, n1500 }; + assign n1923_1 = 16'h3120 >> { n_n3170, pv11_7_7_, preset, n1500 }; + assign n1928_1 = 16'hf888 >> { n_n3916, n1494, n1496, n_n3758 }; + assign n1933_1 = 64'heaeaeac0eac0eac0 >> { n_n3624, n_n3688, n_n3608, n_n3910, n1496, n1494 }; + assign n1938_1 = 64'heaeaeac0eac0eac0 >> { n_n3936, n_n3099, n_n4392, n_n3108, n1496, n1494 }; + assign n1943_1 = 8'h54 >> { n_n3150, n1497, preset }; + assign n1948_1 = 16'hf888 >> { n1494, n_n3688, n1496, n_n4320 }; + assign n1953_1 = 16'h3120 >> { n_n4360, pv10_7_7_, preset, n1517 }; + assign n1958_1 = 16'hf888 >> { n1494, n_n4362, n1496, n_n4247 }; + assign n1963_1 = 32'd4169697416 >> { n_n3242, n_n3170, n1494, n_n4199, n1496 }; + assign n1968_1 = 32'd2290677896 >> { n1495, n1492, n_n4275, n_n3966, n1496 }; + assign n1973_1 = 32'd268440098 >> { n1416, n1414, n1413, preset, n_n3766 }; + assign n1978_1 = 16'h3120 >> { n_n4021, pv2_4_4_, preset, n1614 }; + assign n1983_1 = 16'h3120 >> { n_n4062, pv2_6_6_, preset, n1614 }; + assign n1988_1 = 32'd2290677896 >> { n1495, n1492, n_n3814, n_n3514, n1496 }; + assign n1993_1 = 16'h88f8 >> { n1407, n1494, n1496, n_n3572 }; + assign n1998_1 = 16'hf888 >> { n1494, n_n4270, n1496, n_n4166 }; + assign n2003_1 = 16'h3120 >> { n_n3976, n1626, preset, n1531 }; + assign n2008_1 = 16'hf888 >> { n_n3841, n1494, n1496, n_n3394 }; + assign n2013_1 = 32'd823336962 >> { n_n4095, n1758, n1757, preset, n1533 }; + assign n2018_1 = 8'h54 >> { n_n3863, n1497, preset }; + assign n2023_1 = 8'h54 >> { n_n3720, n1497, preset }; + assign n2033_1 = 16'h3120 >> { n_n3756, pv10_0_0_, preset, n1517 }; + assign n2038_1 = 64'heaeaeac0eac0eac0 >> { n_n3578, n_n4074, n_n3458, n_n3667, n1496, n1494 }; + assign n2043_1 = 16'hf888 >> { n1494, n_n4299, n1496, n_n3342 }; + assign n2048_1 = 8'h54 >> { n_n3529, n1497, preset }; + assign n2053_1 = 16'hf888 >> { n1494, n_n3756, n1496, n_n4209 }; + assign n2063_1 = 32'd4169697416 >> { n_n3035, n_n4157, n1494, n_n3337, n1496 }; + assign n2068_1 = 64'h02080808060c0c0c >> { n1416, n_n3814, n_n3724, preset, n_n4227, n1414 }; + assign n2073_1 = 8'h54 >> { n_n4153, n1497, preset }; + assign n2078_1 = 16'hdfdd >> { n_n3831, n1642, n1927, n1616 }; + assign n1927 = 8'h08 >> { n1495, n1617, n_n3831 }; + assign n2083_1 = 8'h54 >> { n_n3233, n1497, preset }; + assign n2088_1 = 16'hf888 >> { n1494, n_n4251, n1496, n_n3413 }; + assign n2093_1 = 16'h3120 >> { n_n4182, pv4_3_3_, preset, n1565 }; + assign n2098 = 16'h3120 >> { n_n3841, n1645, preset, n1531 }; + assign n2103_1 = 8'h54 >> { n_n3441, n1497, preset }; + assign n2108_1 = 16'ha888 >> { n1559, n_n3831, n_n4026, n1616 }; + assign n2113_1 = 16'hf888 >> { n_n4229, n1494, n1496, n_n4342 }; + assign n2118_1 = 16'hf888 >> { n_n3841, n1494, n1496, n_n4102 }; + assign n2123_1 = 64'heaeaeac0eac0eac0 >> { n_n3035, n_n4157, n_n4288, n_n3277, n1496, n1494 }; + assign n2128_1 = 32'd4169697416 >> { n_n3085, n_n3250, n1494, n_n4180, n1496 }; + assign n2133_1 = 16'hf888 >> { pv1_0_0_, n1556, n1555, n_n3878 }; + assign n2138_1 = 16'h3120 >> { n_n3931, pv2_0_0_, preset, n1614 }; +endmodule diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf new file mode 100644 index 000000000..d3e44f288 --- /dev/null +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -0,0 +1,156 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml +#arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml + +[BENCHMARKS] +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif +#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif +#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif +#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif +#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif +#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif +#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif +#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif +#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif +#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif +#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif +#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif +#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif + +[SYNTHESIS_PARAM] +# Benchmark alu4 +bench0_top = alu4 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v +# Benchmark apex2 +bench1_top = apex2 +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v +# Benchmark apex4 +bench2_top = apex4 +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v +# Benchmark bigkey +bench3_top = bigkey +bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act +bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v +# Benchmark clma +bench4_top = clma +bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act +bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v +# Benchmark des +bench5_top = des +bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act +bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v +# Benchmark diffeq +bench6_top = diffeq +bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act +bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v +# Benchmark dsip +bench7_top = dsip +bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act +bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v +# Benchmark elliptic +bench8_top = elliptic +bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act +bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v +# Benchmark ex1010 +bench9_top = ex1010 +bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act +bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v +# Benchmark ex5p +bench10_top = ex5p +bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act +bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v +# Benchmark frisc +bench11_top = frisc +bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act +bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v +# Benchmark misex3 +bench12_top = misex3 +bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act +bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v +# Benchmark pdc +bench13_top = pdc +bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act +bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v +# Benchmark s298 +bench14_top = s298 +bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act +bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v +# Benchmark s38417 +bench15_top = s38417 +bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act +bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v +# Benchmark s38584 +bench16_top = s38584 +bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act +bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v +# Benchmark seq +bench17_top = seq +bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act +bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v +# Benchmark spla +bench18_top = spla +bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act +bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v +# Benchmark tseng +bench19_top = tseng +bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act +bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v + +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +##vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_verilog_explicit_mapping= +vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index 810e37dbd..14ca60752 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -278,7 +278,6 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp, check_file_handler(fp); print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----")); - fp << "initial begin" << std::endl; for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { /* We only cares blocks with configuration bits */ @@ -308,9 +307,8 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp, for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { config_data_values.push_back(bitstream_manager.bit_value(config_bit)); } - print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values); + print_verilog_wire_constant_values(fp, config_data_port, config_data_values); } - fp << "end" << std::endl; fp << "initial begin" << std::endl; From 2dff779005ace739def8c09bab8cdc1a8dc6dd19 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 31 Oct 2019 20:16:08 -0600 Subject: [PATCH 364/482] critical bug fixed for bitstream generation for offset truth tables --- .../vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp index ec700ca82..207124c12 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp @@ -291,6 +291,7 @@ bool lut_truth_table_use_on_set(const LutTruthTable& truth_table) { on_set = true; off_set = false; } + VTR_ASSERT(on_set == !off_set); return on_set; } @@ -464,9 +465,11 @@ std::vector build_single_output_lut_bitstream(const LutTruthTable& truth_t } /* Initial all the bits in the bitstream */ - if (true == on_set) { - lut_bitstream.resize(bitstream_size, false); - } else if (true == off_set) { + if (true == off_set) { + /* By default, the lut_bitstream is initialize for on_set + * For off set, it should be flipped + */ + lut_bitstream.clear(); lut_bitstream.resize(bitstream_size, true); } From d7098684638ce41bc8ce63d4a193687d66b8b43d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 31 Oct 2019 20:17:40 -0600 Subject: [PATCH 365/482] adding more regression tests which is quick run but very helpful for debugging --- .../tasks/multi_mode/config/task.conf | 58 +++++++++++++++++++ openfpga_flow/tasks/s298/config/task.conf | 58 +++++++++++++++++++ 2 files changed, 116 insertions(+) create mode 100644 openfpga_flow/tasks/multi_mode/config/task.conf create mode 100644 openfpga_flow/tasks/s298/config/task.conf diff --git a/openfpga_flow/tasks/multi_mode/config/task.conf b/openfpga_flow/tasks/multi_mode/config/task.conf new file mode 100644 index 000000000..5157bb235 --- /dev/null +++ b/openfpga_flow/tasks/multi_mode/config/task.conf @@ -0,0 +1,58 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = K4n4_test +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v +bench0_chan_width = 100 + +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_verilog_explicit_mapping= +#vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= diff --git a/openfpga_flow/tasks/s298/config/task.conf b/openfpga_flow/tasks/s298/config/task.conf new file mode 100644 index 000000000..dd45f883a --- /dev/null +++ b/openfpga_flow/tasks/s298/config/task.conf @@ -0,0 +1,58 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N6_sram_chain_FC_behavioral_verilog_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif + +[SYNTHESIS_PARAM] +bench0_top = s298 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v +bench0_chan_width = 100 + +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_verilog_explicit_mapping= +vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= From 531cc064fc908a8b88be2e4512dadc8c32daccd6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 10:47:40 -0600 Subject: [PATCH 366/482] bug fixing for formal top-level testbench --- .../tasks/mcnc_big20/config/task.conf | 6 +- .../verilog_formal_random_top_testbench.cpp | 58 +++++++++++++------ .../fpga_x2p/verilog/verilog_writer_utils.cpp | 27 +++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 5 ++ 4 files changed, 74 insertions(+), 22 deletions(-) diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index d3e44f288..50d2402b8 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -20,7 +20,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem #arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml [BENCHMARKS] -#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif #bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif #bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif @@ -34,8 +34,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem #bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif #bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif #bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif -bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif -#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif +#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif # Pass +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif # Multi-mode support fails to repack #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif #bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 777f55fd8..da24f7817 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -36,6 +36,7 @@ constexpr char* DEFAULT_CLOCK_NAME = "clk"; constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT"; constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT"; constexpr char* ERROR_COUNTER = "nb_error"; +constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start"; constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; /******************************************************************** @@ -279,23 +280,29 @@ void print_verilog_timeout_and_vcd(std::fstream& fp, fp << "\t\t$dumpvars(1, " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ");" << std::endl; fp << "\tend" << std::endl; - fp << "\tinitial begin" << std::endl; - fp << "\t\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; - fp << "\t\t$display(\"Simulation start\");" << std::endl; - print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); - fp << "\t\t#" << simulation_time << std::endl; - fp << "\t\tif(" << ERROR_COUNTER << " == 0) begin" << std::endl; - fp << "\t\t\t$display(\"Simulation Succeed\");" << std::endl; - fp << "\t\tend else begin" << std::endl; - fp << "\t\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << ERROR_COUNTER << ");" << std::endl; - fp << "\t\tend" << std::endl; - fp << "\t\t$finish;" << std::endl; - fp << "\tend" << std::endl; + /* Condition ends for the Icarus requirement */ + print_verilog_endif(fp); print_verilog_comment(fp, std::string("----- END Icarus requirement -------")); - /* Condition ends for the Icarus requirement */ - print_verilog_endif(fp); + /* Add an empty line as splitter */ + fp << std::endl; + + BasicPort sim_start_port(std::string(FORMAL_TB_SIM_START_PORT_NAME), 1); + + fp << "initial begin" << std::endl; + fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl; + fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; + fp << "\t$display(\"Simulation start\");" << std::endl; + print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); + fp << "\t#" << simulation_time << std::endl; + fp << "\tif(" << ERROR_COUNTER << " == 0) begin" << std::endl; + fp << "\t\t$display(\"Simulation Succeed\");" << std::endl; + fp << "\tend else begin" << std::endl; + fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << ERROR_COUNTER << ");" << std::endl; + fp << "\tend" << std::endl; + fp << "\t$finish;" << std::endl; + fp << "end" << std::endl; /* Add an empty line as splitter */ fp << std::endl; @@ -321,7 +328,19 @@ void print_verilog_top_random_testbench_check(std::fstream& fp, BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + print_verilog_comment(fp, std::string("----- Skip the first falling edge of clock, it is for initialization -------")); + + BasicPort sim_start_port(std::string(FORMAL_TB_SIM_START_PORT_NAME), 1); + + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, sim_start_port) << ";" << std::endl; + fp << std::endl; + fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; + fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl; + fp << "\t\t"; + print_verilog_register_connection(fp, sim_start_port, sim_start_port, true); + fp << "\t\tend else begin" << std::endl; + for (const t_logical_block& lb : L_logical_blocks) { /* Bypass non-I/O logical blocks ! */ if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { @@ -329,16 +348,17 @@ void print_verilog_top_random_testbench_check(std::fstream& fp, } if (VPACK_OUTPAD == lb.type){ - fp << "\t\tif(!(" << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX); + fp << "\t\t\tif(!(" << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX); fp << " === " << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX); fp << ") && !(" << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX); fp << " === 1'bx)) begin" << std::endl; - fp << "\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << " <= 1'b1;" << std::endl; - fp << "\t\tend else begin" << std::endl; - fp << "\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << "<= 1'b0;" << std::endl; - fp << "\t\tend" << std::endl; + fp << "\t\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << " <= 1'b1;" << std::endl; + fp << "\t\t\tend else begin" << std::endl; + fp << "\t\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << "<= 1'b0;" << std::endl; + fp << "\t\t\tend" << std::endl; } } + fp << "\t\tend" << std::endl; fp << "\tend" << std::endl; /* Add an empty line as splitter */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index b79af9f7b..69f774592 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -725,6 +725,33 @@ void print_verilog_wire_connection(std::fstream& fp, fp << ";" << std::endl; } +/******************************************************************** + * Generate a wire connection for two Verilog ports + * using "assign" syntax + *******************************************************************/ +void print_verilog_register_connection(std::fstream& fp, + const BasicPort& output_port, + const BasicPort& input_port, + const bool& inverted) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + /* Must check: the port width matches */ + VTR_ASSERT( input_port.get_width() == output_port.get_width() ); + + fp << "\t"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << " <= "; + + if (true == inverted) { + fp << "~"; + } + + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); + fp << ";" << std::endl; +} + + /******************************************************************** * Generate an instance of a buffer module * with given information about the input and output ports of instance diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index f64ea6ed7..d09e950de 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -101,6 +101,11 @@ void print_verilog_wire_connection(std::fstream& fp, const BasicPort& input_port, const bool& inverted); +void print_verilog_register_connection(std::fstream& fp, + const BasicPort& output_port, + const BasicPort& input_port, + const bool& inverted); + void print_verilog_buffer_instance(std::fstream& fp, ModuleManager& module_manager, const CircuitLibrary& circuit_lib, From 139ea8b3e3fbbcfd5bea71d222917eb7839c85b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 10:49:37 -0600 Subject: [PATCH 367/482] add s298 single mode arch to Travis --- .travis/script.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index 599c35adf..843189baf 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py single_mode blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3 +python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow tileable_routing explicit_verilog --maxthreads 4 end_section "OpenFPGA.TaskTun" From 49bfb3223c1651860d0741d996c35635639dd085 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 10:53:47 -0600 Subject: [PATCH 368/482] add compact routing to regression test --- .travis/script.sh | 2 +- .../tasks/compact_routing/config/task.conf | 59 +++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/tasks/compact_routing/config/task.conf diff --git a/.travis/script.sh b/.travis/script.sh index 843189baf..5c70628f4 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow tileable_routing explicit_verilog --maxthreads 4 +python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4 end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/compact_routing/config/task.conf b/openfpga_flow/tasks/compact_routing/config/task.conf new file mode 100644 index 000000000..44334b6bd --- /dev/null +++ b/openfpga_flow/tasks/compact_routing/config/task.conf @@ -0,0 +1,59 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v +bench0_chan_width = 300 + +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +##vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_verilog_explicit_mapping= +vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= + From a49010d2d3a82dfe12690493b9f37351d132734c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 11:09:35 -0600 Subject: [PATCH 369/482] reorganize the Travis regression test, temporarily shadow s298 --- .travis/script.sh | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index 5c70628f4..586e983e9 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,20 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4 +echo -e "Testing single-mode architectures"; +python3 openfpga_flow/scripts/run_fpga_task.py single_mode +#python3 openfpga_flow/scripts/run_fpga_task.py s298 + +echo -e "Testing multi-mode architectures"; +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4 + +echo -e "Testing compact routing techniques"; +python3 openfpga_flow/scripts/run_fpga_task.py compact_routing + +echo -e "Testing tileable architectures"; +python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing explicit_verilog + +echo -e "Testing Verilog generation with explicit port mapping "; +python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog + end_section "OpenFPGA.TaskTun" From de0be72634aacd864d77d1c52fb80c3d5c671493 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 13:25:29 -0600 Subject: [PATCH 370/482] try to make travis install latest iVerilog --- .travis.yml | 14 +------------- .travis/common.sh | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 13 deletions(-) diff --git a/.travis.yml b/.travis.yml index e433d4894..8697b0505 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,6 +9,7 @@ cache: - $TRAVIS_BUILD_DIR/ace2 - $TRAVIS_BUILD_DIR/libs - $HOME/.ccache + - $HOME/deps # Currently sudo is not required, NO ENV is used @@ -46,7 +47,6 @@ matrix: - gdb - git - gperf - - iverilog - libcairo2-dev - libevent-dev - libfontconfig1-dev @@ -86,18 +86,6 @@ before_install: - source .travis/common.sh install: - - DEPS_DIR="${HOME}/deps" - - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - - | - if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} - else - brew install cmake || brew upgrade cmake - fi - - cmake --version - cd - - .travis/install.sh diff --git a/.travis/common.sh b/.travis/common.sh index 1f39d6d50..b18667843 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -43,3 +43,29 @@ else export CXX=g++-8 fi +# Install necessary package which is not available on Travis CI +export DEPS_DIR="${HOME}/deps" +mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} + +# Install CMake +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} +else + brew install cmake || brew upgrade cmake +fi +cmake --version + +# Install latest iVerilog +# Install CMake +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + IVERILOG_URL="ftp://icarus.com/pub/eda/verilog/v10//verilog-10.3.tar.gz" + mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + echo ${PATH} +fi + + + From 32953b0292a1ae63fa82543d97fd34e78579b374 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 13:41:30 -0600 Subject: [PATCH 371/482] rework on Travis Scripts --- .travis/common.sh | 27 --------------------------- .travis/install.sh | 29 +++++++++++++++++++++++++++++ .travis/script.sh | 2 +- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/.travis/common.sh b/.travis/common.sh index b18667843..7f63d5d5f 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -42,30 +42,3 @@ else export CC=gcc-8 export CXX=g++-8 fi - -# Install necessary package which is not available on Travis CI -export DEPS_DIR="${HOME}/deps" -mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - -# Install CMake -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} -else - brew install cmake || brew upgrade cmake -fi -cmake --version - -# Install latest iVerilog -# Install CMake -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - IVERILOG_URL="ftp://icarus.com/pub/eda/verilog/v10//verilog-10.3.tar.gz" - mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 - export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} - echo ${PATH} -fi - - - diff --git a/.travis/install.sh b/.travis/install.sh index 16f848403..2235f9266 100755 --- a/.travis/install.sh +++ b/.travis/install.sh @@ -3,6 +3,35 @@ source .travis/common.sh set -e +# Install necessary package which is not available on Travis CI +export DEPS_DIR="${HOME}/deps" +mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} + +# Install CMake +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} +else + brew install cmake || brew upgrade cmake +fi + +cmake --version + +# Install latest iVerilog +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + IVERILOG_URL="ftp://icarus.com/pub/eda/verilog/v10//verilog-10.3.tar.gz" + mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + echo ${PATH} +fi + +iverilog --version + +# Go back to home directory +cd ${HOME} + # Git repo fixup #start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}" #set -x diff --git a/.travis/script.sh b/.travis/script.sh index 586e983e9..2c0425fa1 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -29,7 +29,7 @@ echo -e "Testing compact routing techniques"; python3 openfpga_flow/scripts/run_fpga_task.py compact_routing echo -e "Testing tileable architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing explicit_verilog +python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing echo -e "Testing Verilog generation with explicit port mapping "; python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog From b53a9b13bfb243a5ffdf5f5ee3b1f1d9e6e122a3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 14:03:55 -0600 Subject: [PATCH 372/482] update travis with installation --- .travis.yml | 1 - .travis/common.sh | 30 ++++++++++++++++++++++++++++++ .travis/install.sh | 29 ----------------------------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/.travis.yml b/.travis.yml index 8697b0505..26fc7a768 100644 --- a/.travis.yml +++ b/.travis.yml @@ -86,7 +86,6 @@ before_install: - source .travis/common.sh install: - - cd - - .travis/install.sh script: diff --git a/.travis/common.sh b/.travis/common.sh index 7f63d5d5f..c7c4a7cdd 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -42,3 +42,33 @@ else export CC=gcc-8 export CXX=g++-8 fi + +# Install necessary package which is not available on Travis CI +export DEPS_DIR="${HOME}/deps" +mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} + +# Install CMake +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} +else + brew install cmake || brew upgrade cmake +fi + +cmake --version + +# Install latest iVerilog +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + IVERILOG_URL="ftp://icarus.com/pub/eda/verilog/v10//verilog-10.3.tar.gz" + mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + echo ${PATH} +fi + +iverilog --version + +# Go back to home directory +cd ${HOME} + diff --git a/.travis/install.sh b/.travis/install.sh index 2235f9266..16f848403 100755 --- a/.travis/install.sh +++ b/.travis/install.sh @@ -3,35 +3,6 @@ source .travis/common.sh set -e -# Install necessary package which is not available on Travis CI -export DEPS_DIR="${HOME}/deps" -mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - -# Install CMake -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} -else - brew install cmake || brew upgrade cmake -fi - -cmake --version - -# Install latest iVerilog -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - IVERILOG_URL="ftp://icarus.com/pub/eda/verilog/v10//verilog-10.3.tar.gz" - mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 - export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} - echo ${PATH} -fi - -iverilog --version - -# Go back to home directory -cd ${HOME} - # Git repo fixup #start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}" #set -x From c2cef205a4d6343723a1b927ca0ab3ec42db147e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 14:52:42 -0600 Subject: [PATCH 373/482] update travis: try to compile iverilog through source --- .travis/common.sh | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/.travis/common.sh b/.travis/common.sh index c7c4a7cdd..11414c948 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -49,7 +49,7 @@ mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} # Install CMake if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake export PATH=${DEPS_DIR}/cmake/bin:${PATH} echo ${PATH} @@ -59,10 +59,16 @@ fi cmake --version -# Install latest iVerilog +# Install latest iVerilog. Since no deb is provided, compile from source codes if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - IVERILOG_URL="ftp://icarus.com/pub/eda/verilog/v10//verilog-10.3.tar.gz" + export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + cd iverlog-10.3 + sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin + ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin + make -j4 + make check + make install --prefix=${HOME}/iverilog-10.3/bin export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} echo ${PATH} fi @@ -70,5 +76,5 @@ fi iverilog --version # Go back to home directory -cd ${HOME} +cd - From 8c0d60abd600f3533642c0c908718956c9ff62d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 15:00:33 -0600 Subject: [PATCH 374/482] debugging travis --- .travis/common.sh | 34 ---------------------------------- .travis/install.sh | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 34 deletions(-) diff --git a/.travis/common.sh b/.travis/common.sh index 11414c948..a293cb00f 100644 --- a/.travis/common.sh +++ b/.travis/common.sh @@ -43,38 +43,4 @@ else export CXX=g++-8 fi -# Install necessary package which is not available on Travis CI -export DEPS_DIR="${HOME}/deps" -mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - -# Install CMake -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} -else - brew install cmake || brew upgrade cmake -fi - -cmake --version - -# Install latest iVerilog. Since no deb is provided, compile from source codes -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 - cd iverlog-10.3 - sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin - ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin - make -j4 - make check - make install --prefix=${HOME}/iverilog-10.3/bin - export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} - echo ${PATH} -fi - -iverilog --version - -# Go back to home directory -cd - diff --git a/.travis/install.sh b/.travis/install.sh index 16f848403..fd9e353f9 100755 --- a/.travis/install.sh +++ b/.travis/install.sh @@ -3,6 +3,42 @@ source .travis/common.sh set -e +# Install necessary package which is not available on Travis CI +export DEPS_DIR="${HOME}/deps" +mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} + +# Install CMake +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} +else + brew install cmake || brew upgrade cmake +fi + +cmake --version + +# Install latest iVerilog. Since no deb is provided, compile from source codes +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" + mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + cd iverlog-10.3 + sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin + ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin + make -j4 + make check + make install --prefix=${HOME}/iverilog-10.3/bin + export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + echo ${PATH} +fi + +iverilog --version + +# Go back to home directory +cd - + + # Git repo fixup #start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}" #set -x From 480478e5452015d890315f5d1e59c6b53d52e2c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 15:12:08 -0600 Subject: [PATCH 375/482] reorganizing travis --- .travis.yml | 30 ++++++++++++++++++++++++++++++ .travis/install.sh | 36 ------------------------------------ 2 files changed, 30 insertions(+), 36 deletions(-) diff --git a/.travis.yml b/.travis.yml index 26fc7a768..d4bfb426f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -86,6 +86,36 @@ before_install: - source .travis/common.sh install: +# Install necessary package which is not available on Travis CI + - DEPS_DIR="${HOME}/deps" + - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} +# Install CMake + - | + if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} + else + brew install cmake || brew upgrade cmake + fi + - cmake --version +# Install latest iVerilog. Since no deb is provided, compile from source codes + - | + if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" + mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + cd iverlog-10.3 + sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin + ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin + make -j4 + make check + make install --prefix=${HOME}/iverilog-10.3/bin + export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + echo ${PATH} + fi + - iverilog --version + - cd - - .travis/install.sh script: diff --git a/.travis/install.sh b/.travis/install.sh index fd9e353f9..16f848403 100755 --- a/.travis/install.sh +++ b/.travis/install.sh @@ -3,42 +3,6 @@ source .travis/common.sh set -e -# Install necessary package which is not available on Travis CI -export DEPS_DIR="${HOME}/deps" -mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - -# Install CMake -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} -else - brew install cmake || brew upgrade cmake -fi - -cmake --version - -# Install latest iVerilog. Since no deb is provided, compile from source codes -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 - cd iverlog-10.3 - sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin - ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin - make -j4 - make check - make install --prefix=${HOME}/iverilog-10.3/bin - export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} - echo ${PATH} -fi - -iverilog --version - -# Go back to home directory -cd - - - # Git repo fixup #start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}" #set -x From 000f93ffd739be907abb5e363afff6ea033f6a62 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 15:19:34 -0600 Subject: [PATCH 376/482] try to fix travis bugs --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index d4bfb426f..2e53c637a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -104,7 +104,7 @@ install: - | if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - mkdir iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 cd iverlog-10.3 sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin From b54bec1609760b00282b1a2b8f0c26dfffde6c46 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 15:23:38 -0600 Subject: [PATCH 377/482] streamline regression tes --- .travis/script.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/script.sh b/.travis/script.sh index 2c0425fa1..bbd72cec4 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -23,7 +23,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py single_mode #python3 openfpga_flow/scripts/run_fpga_task.py s298 echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 echo -e "Testing compact routing techniques"; python3 openfpga_flow/scripts/run_fpga_task.py compact_routing From d4fedb76d764bf45e59a939c37be29c1923881a5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 15:24:58 -0600 Subject: [PATCH 378/482] revert to default iverilog of Ubuntu 18.04 --- .travis.yml | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/.travis.yml b/.travis.yml index 2e53c637a..658431210 100644 --- a/.travis.yml +++ b/.travis.yml @@ -47,6 +47,7 @@ matrix: - gdb - git - gperf + - iverilog - libcairo2-dev - libevent-dev - libfontconfig1-dev @@ -101,19 +102,19 @@ install: fi - cmake --version # Install latest iVerilog. Since no deb is provided, compile from source codes - - | - if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 - cd iverlog-10.3 - sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin - ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin - make -j4 - make check - make install --prefix=${HOME}/iverilog-10.3/bin - export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} - echo ${PATH} - fi +# - | +# if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then +# IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" +# travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 +# cd iverlog-10.3 +# sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin +# ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin +# make -j4 +# make check +# make install --prefix=${HOME}/iverilog-10.3/bin +# export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} +# echo ${PATH} +# fi - iverilog --version - cd - - .travis/install.sh From b61b81b8d8081db92b0ebfa84878e2ed8e2d33bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 15:29:08 -0600 Subject: [PATCH 379/482] tuning iverilog version display --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 658431210..a3f13c7ca 100644 --- a/.travis.yml +++ b/.travis.yml @@ -115,7 +115,7 @@ install: # export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} # echo ${PATH} # fi - - iverilog --version + - iverilog -V - cd - - .travis/install.sh From 3ae841b80f4e51158c2fcafdd0553495492ef8d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 16:33:12 -0600 Subject: [PATCH 380/482] start refactoring auto-check top testbench generation --- .../verilog/verilog_autocheck_top_testbench.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h index 1e679bae1..a34deb5da 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h @@ -1,3 +1,11 @@ +#ifndef VERILOG_AUTOCHECK_TOP_TESTBENCH_H +#define VERILOG_AUTOCHECK_TOP_TESTBENCH_H + +#include +#include +#include "module_manager.h" +#include "bitstream_manager.h" +#include "circuit_library.h" void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, @@ -6,3 +14,20 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, t_syn_verilog_opts fpga_verilog_opts, t_spice verilog); +/* +void print_verilog_autocheck_top_testbench(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir, + const t_syn_verilog_opts& fpga_verilog_opts, + const t_spice_params& simulation_parameters); +*/ + +#endif From 5332588e827f43e65968b17c7e1408efc5eb4b03 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 16:36:29 -0600 Subject: [PATCH 381/482] retrying travis installation of iVerilog 10.3 --- .travis.yml | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.travis.yml b/.travis.yml index a3f13c7ca..b53e91cc0 100644 --- a/.travis.yml +++ b/.travis.yml @@ -94,7 +94,7 @@ install: - | if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake export PATH=${DEPS_DIR}/cmake/bin:${PATH} echo ${PATH} else @@ -102,19 +102,19 @@ install: fi - cmake --version # Install latest iVerilog. Since no deb is provided, compile from source codes -# - | -# if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then -# IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" -# travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 -# cd iverlog-10.3 -# sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin -# ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin -# make -j4 -# make check -# make install --prefix=${HOME}/iverilog-10.3/bin -# export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} -# echo ${PATH} -# fi + - | + if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" + mkdir -p iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 + cd iverlog-10.3 + sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin + ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin + make -j4 + make check + make install --prefix=${HOME}/iverilog-10.3/bin + export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + echo ${PATH} + fi - iverilog -V - cd - - .travis/install.sh From 2dc3a4eb1fc3368d55c240fcda9acc32c2c43dbf Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 17:03:21 -0600 Subject: [PATCH 382/482] fixing bugs in iVerilog installation --- .travis.yml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/.travis.yml b/.travis.yml index b53e91cc0..6ec2cd01a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -105,14 +105,15 @@ install: - | if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - mkdir -p iverilog-10.3 && travis_retry wget --no-check-certificate --quiet -O - ${IVERILOG_URL} | tar --strip-components=1 -xz -C iverilog-10.3 - cd iverlog-10.3 - sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10.3/bin - ./configure --prefix=${DEPS_DIR}/iverilog-10.3/bin + travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL} + tar -xzf v10_3.tar.gz + cd iverlog-10_3 + sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin + ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin make -j4 make check - make install --prefix=${HOME}/iverilog-10.3/bin - export PATH=${DEPS_DIR}/iverilog-10.3/bin:${PATH} + make install --prefix=${HOME}/iverilog-10_3/bin + export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH} echo ${PATH} fi - iverilog -V From 161664f2531d4bfe2d089a3df2ddcc80385b3c75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 17:24:06 -0600 Subject: [PATCH 383/482] try to comfort iverilog package extraction --- .travis.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 6ec2cd01a..fde4fc9c7 100644 --- a/.travis.yml +++ b/.travis.yml @@ -106,7 +106,8 @@ install: if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL} - tar -xzf v10_3.tar.gz + mkdir -p iverilog-10_3 + tar -xz v10_3.tar.gz cd iverlog-10_3 sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin From 9a37b66d53ca4fb404ff02aedc9232bffc54ea11 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 17:39:30 -0600 Subject: [PATCH 384/482] move installation to a script --- .travis.yml | 32 -------------------------------- .travis/install.sh | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 32 deletions(-) diff --git a/.travis.yml b/.travis.yml index fde4fc9c7..1a113ce92 100644 --- a/.travis.yml +++ b/.travis.yml @@ -87,38 +87,6 @@ before_install: - source .travis/common.sh install: -# Install necessary package which is not available on Travis CI - - DEPS_DIR="${HOME}/deps" - - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} -# Install CMake - - | - if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} - else - brew install cmake || brew upgrade cmake - fi - - cmake --version -# Install latest iVerilog. Since no deb is provided, compile from source codes - - | - if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL} - mkdir -p iverilog-10_3 - tar -xz v10_3.tar.gz - cd iverlog-10_3 - sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin - ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin - make -j4 - make check - make install --prefix=${HOME}/iverilog-10_3/bin - export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH} - echo ${PATH} - fi - - iverilog -V - - cd - - .travis/install.sh script: diff --git a/.travis/install.sh b/.travis/install.sh index 16f848403..49e14d11a 100755 --- a/.travis/install.sh +++ b/.travis/install.sh @@ -3,6 +3,39 @@ source .travis/common.sh set -e +# Install necessary package which is not available on Travis CI +export DEPS_DIR="${HOME}/deps" +mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} +# Install CMake +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} +else + brew install cmake || brew upgrade cmake +fi + cmake --version + +# Install latest iVerilog. Since no deb is provided, compile from source codes +if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" + travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL} + mkdir -p iverilog-10_3 + tar -xz v10_3.tar.gz + cd iverlog-10_3 + sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin + ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin + make -j4 + make check + make install --prefix=${HOME}/iverilog-10_3/bin + export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH} + echo ${PATH} +fi +iverilog -V +cd - + + # Git repo fixup #start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}" #set -x From 1d78725d4d32c6dde3cefe73cb7876da58182c30 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 17:48:17 -0600 Subject: [PATCH 385/482] add installation --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 1a113ce92..1e5153ed9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -87,7 +87,7 @@ before_install: - source .travis/common.sh install: - - .travis/install.sh + - source .travis/install.sh script: - .travis/script.sh From 4d4ef1113db08983048bfa66681243d5817765cd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 17:53:50 -0600 Subject: [PATCH 386/482] give up iverilog on travis --- .travis.yml | 13 ++++++++++ .travis/install.sh | 62 +++++++++++++++++++++++----------------------- 2 files changed, 44 insertions(+), 31 deletions(-) diff --git a/.travis.yml b/.travis.yml index 1e5153ed9..6ddea9783 100644 --- a/.travis.yml +++ b/.travis.yml @@ -87,6 +87,19 @@ before_install: - source .travis/common.sh install: + - DEPS_DIR="${HOME}/deps" + - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} + - | + if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} + else + brew install cmake || brew upgrade cmake + fi + - cmake --version + - cd - - source .travis/install.sh script: diff --git a/.travis/install.sh b/.travis/install.sh index 49e14d11a..27d1cad5b 100755 --- a/.travis/install.sh +++ b/.travis/install.sh @@ -3,37 +3,37 @@ source .travis/common.sh set -e -# Install necessary package which is not available on Travis CI -export DEPS_DIR="${HOME}/deps" -mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} -# Install CMake -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" - mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} -else - brew install cmake || brew upgrade cmake -fi - cmake --version - -# Install latest iVerilog. Since no deb is provided, compile from source codes -if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" - travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL} - mkdir -p iverilog-10_3 - tar -xz v10_3.tar.gz - cd iverlog-10_3 - sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin - ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin - make -j4 - make check - make install --prefix=${HOME}/iverilog-10_3/bin - export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH} - echo ${PATH} -fi -iverilog -V -cd - +## Install necessary package which is not available on Travis CI +#export DEPS_DIR="${HOME}/deps" +#mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} +## Install CMake +#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then +# export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" +# mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake +# export PATH=${DEPS_DIR}/cmake/bin:${PATH} +# echo ${PATH} +#else +# brew install cmake || brew upgrade cmake +#fi +# cmake --version +# +## Install latest iVerilog. Since no deb is provided, compile from source codes +#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then +# export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz" +# travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL} +# mkdir -p iverilog-10_3 +# tar -xz v10_3.tar.gz +# cd iverlog-10_3 +# sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin +# ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin +# make -j4 +# make check +# make install --prefix=${HOME}/iverilog-10_3/bin +# export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH} +# echo ${PATH} +#fi +#iverilog -V +#cd - # Git repo fixup From a0512e40b19d611cb3c8dbd1e56771e55136b2d5 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 18:20:00 -0600 Subject: [PATCH 387/482] Created intermidiate file for modelsim simulation --- .../verilog/simulation_info_writer.cpp | 85 +++++++++++++++++++ .../fpga_x2p/verilog/simulation_info_writer.h | 13 +++ .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 16 +++- 3 files changed, 110 insertions(+), 4 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp new file mode 100644 index 000000000..520376be0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -0,0 +1,85 @@ +/***********************************/ +/* Synthesizable Verilog Dumping */ +/* Xifan TANG, EPFL/LSI */ +/***********************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define MINI_CASE_SENSITIVE +#include "ini.h" + +/* Include vpr structs*/ +#include "util.h" +#include "physical_types.h" +#include "vpr_types.h" +#include "globals.h" +#include "rr_graph.h" +#include "vpr_utils.h" +#include "path_delay.h" +#include "stats.h" + +/* Include FPGA-SPICE utils */ +#include "linkedlist.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_globals.h" + +/* Include verilog utils */ +#include "verilog_global.h" +#include "verilog_utils.h" +#include "simulation_info_writer.h" + +// Infile Function +static float get_verilog_modelsim_simulation_time_period(const float &time_unit, + const int &num_prog_clock_cycles, + const float &prog_clock_period, + const int &num_op_clock_cycles, + const float &op_clock_period) +{ + float total_time_period = 0.; + + /* Take into account the prog_reset and reset cycles */ + total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period; + total_time_period = total_time_period / time_unit; + + return total_time_period; +} + +/***** Top-level function *****/ +void print_verilog_simulation_info(const int &num_operating_clock_cycles, + const std::string &verilog_dir_formatted, + const std::string &chomped_circuit_name, + const std::string &src_dir_path, + const size_t &num_program_clock_cycles, + const float &prog_clock_freq, + const float &op_clock_freq) +{ + mINI::INIStructure ini; + // std::map units_map; + // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; + // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; + + /* Compute simulation time period */ + float simulation_time_period = get_verilog_modelsim_simulation_time_period(1E-3, + num_program_clock_cycles, + 1. / prog_clock_freq, + num_operating_clock_cycles, + 1. / op_clock_freq); + + ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; + ini["SIMULATION_DECK"]["BENCHMARK "] = chomped_circuit_name; + ini["SIMULATION_DECK"]["TOP_TB"] = chomped_circuit_name + std::string("_top_formal_verification_random_tb"); + ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period); + ini["SIMULATION_DECK"]["UNIT "] = "ms"; + ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir_path); + ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); + ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(chomped_circuit_name + "_include_netlists.v"); + + mINI::INIFile file("SimulationDeckInfo.ini"); + file.generate(ini, true); +} \ No newline at end of file diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h new file mode 100644 index 000000000..46c178c17 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h @@ -0,0 +1,13 @@ +#ifndef VPR_API_H +#define VPR_API_H + +#include + +void print_verilog_simulation_info(const int &num_operating_clock_cycles, + const std::string &verilog_dir_formatted, + const std::string &chomped_circuit_name, + const std::string &src_dir_path, + const size_t &num_program_clock_cycles, + const float &prog_clock_freq, + const float &op_clock_freq); +#endif \ No newline at end of file diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index bb5af9ac5..998a8f2db 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -62,6 +62,7 @@ #include "verilog_formality_autodeck.h" #include "verilog_sdc_pb_types.h" #include "verilog_include_netlists.h" +#include "simulation_info_writer.h" #include "verilog_api.h" @@ -410,12 +411,12 @@ void vpr_fpga_verilog(ModuleManager& module_manager, dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, std::string(formal_verification_top_netlist_file_path + std::string(".bak")).c_str(), src_dir_path); /* TODO: new function: to be tested */ - print_verilog_preconfig_top_module(module_manager, bitstream_manager, + print_verilog_preconfig_top_module(module_manager, bitstream_manager, Arch.spice->circuit_lib, global_ports, L_logical_blocks, - device_size, L_grids, L_blocks, + device_size, L_grids, L_blocks, std::string(chomped_circuit_name), formal_verification_top_netlist_file_path, - std::string(src_dir_path)); - + std::string(src_dir_path)); + /* Output script for formality */ write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, fm_dir_path, @@ -430,6 +431,13 @@ void vpr_fpga_verilog(ModuleManager& module_manager, print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); + print_verilog_simulation_info(Arch.spice->spice_params.meas_params.sim_num_clock_cycle, + std::string(msim_dir_path), + std::string(chomped_circuit_name), + std::string(src_dir_path), + bitstream_manager.bits().size(), + Arch.spice->spice_params.stimulate_params.prog_clock_freq, + Arch.spice->spice_params.stimulate_params.op_clock_freq); } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { From 27005d6640f61d9364669ed7d24cef4a901c3d87 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 18:20:40 -0600 Subject: [PATCH 388/482] Added Modelsim Python Script --- openfpga_flow/misc/modelsim_proc.tcl | 71 ++++++++++++ openfpga_flow/misc/modelsim_runsim.tcl | 37 +++++++ openfpga_flow/scripts/run_modelsim.py | 148 +++++++++++++++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 openfpga_flow/misc/modelsim_proc.tcl create mode 100644 openfpga_flow/misc/modelsim_runsim.tcl create mode 100644 openfpga_flow/scripts/run_modelsim.py diff --git a/openfpga_flow/misc/modelsim_proc.tcl b/openfpga_flow/misc/modelsim_proc.tcl new file mode 100644 index 000000000..cede56af4 --- /dev/null +++ b/openfpga_flow/misc/modelsim_proc.tcl @@ -0,0 +1,71 @@ +proc create_project {projectname project_path} { + #Switch to the modelsim folder to create the project + set libname $projectname + set initfile /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini + project new $project_path/$projectname $projectname $libname $initfile 0 +} + +proc create_project_with_close {projectname modelsim_path} { + #Get the current project name + set project_env [project env] + if {$project_env eq ""} { + #If string empty (no project) + create_project $projectname $modelsim_path + } else { + #If string not empty (a project is loaded so clsoe it first) + project close + create_project $projectname $modelsim_path + } + } + +proc add_files_project {verilog_files} { + #Get the length of the list + set listlength [llength $verilog_files] + #Add the verilog files one by one + for {set x 0} {$x<$listlength} {incr x} { + project addfile [lindex $verilog_files $x] + } +} + +proc add_waves {top_tb} { + add wave -position insertpoint sim:/$top_tb/* +} +proc runsim {simtime unit} { + run $simtime $unit +} +#Top procedure to create enw project +proc top_create_new_project {projectname verilog_files modelsim_path simtime unit top_tb} { + #Create the project + create_project_with_close $projectname $modelsim_path + #Add the verilog files + add_files_project $verilog_files + #Compile all the files + set myFiles [project filenames] + foreach x $myFiles { + vlog +define+ENABLE_TIMING +define+ENABLE_SIGNAL_INITIALIZATION $x + } + #Start the simulation + vsim $projectname.$top_tb -voptargs=+acc + #Add the waves + add_waves top_tb + #run the simulation + runsim $simtime $unit + #Fit the window view + wave zoom full +} +#Top proc to recompile files and re run the simulation +proc top_rerun_sim {simtime unit top_tb} { + #Save actual format + set myLoc [pwd] + write format wave -window .main_pane.wave.interior.cs.body.pw.wf $myLoc/relaunch.do + quit -sim + #Compile updated verilog files + set myFiles [project filenames] + foreach x $myFiles { + vlog +define+ENABLE_TIMING +define+ENABLE_SIGNAL_INITIALIZATION $x + } + set projectname K4n4_test_fpga_msim + vsim $projectname.$top_tb -voptargs=+acc -do relaunch.do + #run the simulation + run $simtime $unit +} diff --git a/openfpga_flow/misc/modelsim_runsim.tcl b/openfpga_flow/misc/modelsim_runsim.tcl new file mode 100644 index 000000000..64578d883 --- /dev/null +++ b/openfpga_flow/misc/modelsim_runsim.tcl @@ -0,0 +1,37 @@ + +echo "==========================" +pwd +echo "==========================" + +set projectname ${PROJECTNAME} +set benchmark ${BENCHMARK} +set top_tb ${TOP_TB} +#in ms +set simtime ${SIMTIME} +set unit ${UNIT} + +#Path were both tcl script are located +set verilog_path ${VERILOG_PATH} +set project_path "${MODELSIM_PROJ_DIR}/msim_projects/" + +#Path were the verilog files are located +set verilog_path ${VERILOG_PATH} + +set verilog_files [list \ + ${VERILOG_PATH}${VERILOG_FILE1} \ + ${VERILOG_PATH}${VERILOG_FILE2} \ + ${VERILOG_PATH}fpga_defines.v + ] + +#Source the tcl script +source ${MODELSIM_PROJ_DIR}/${BENCHMARK}_autocheck_proc.tcl + +#Execute the top level procedure + +try { + top_create_new_project $$projectname $$verilog_files $$project_path $$simtime $$unit $$top_tb +} finally { + quit +} + +#Relaunch simulation diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py new file mode 100644 index 000000000..0ddbe118c --- /dev/null +++ b/openfpga_flow/scripts/run_modelsim.py @@ -0,0 +1,148 @@ +from string import Template +import sys +import os +import pprint +import argparse +import subprocess +import logging +from pprint import pprint +from configparser import ConfigParser + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configure logging system +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +logging.basicConfig(level=logging.INFO, stream=sys.stdout, + format='%(levelname)s (%(threadName)10s) - %(message)s') +logger = logging.getLogger('Modelsim_run_log') + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Parse commandline arguments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +parser = argparse.ArgumentParser() +parser.add_argument('files', nargs='+', + help="Pass SimulationDeckInfo generated by OpenFPGA flow") +parser.add_argument('--modelsim_proc_tmpl', type=str, + help="Modelsim proc template file") +parser.add_argument('--modelsim_runsim_tmpl', type=str, + help="Modelsim runsim template file") +parser.add_argument('--run_sim', action="store_true", + help="Execute generated script in formality") +parser.add_argument('--modelsim_proj_dir', + help="Provide modelsim project directory") +parser.add_argument('--modelsim_proj_name', + help="Provide modelsim project name") +parser.add_argument('--modelsim_ini', type=str, + default="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini", + help="Skip any confirmation") +parser.add_argument('--skip_prompt', action='store_true', + help='Skip any confirmation') +args = parser.parse_args() + +# Consider default formality script template +task_script_dir = os.path.dirname(os.path.abspath(__file__)) +if not args.modelsim_proc_tmpl: + args.modelsim_proc_tmpl = os.path.join(task_script_dir, os.pardir, + "misc", "modelsim_proc.tcl") +if not args.modelsim_runsim_tmpl: + args.modelsim_runsim_tmpl = os.path.join(task_script_dir, os.pardir, + "misc", "modelsim_runsim.tcl") + +args.modelsim_proc_tmpl = os.path.abspath(args.modelsim_proc_tmpl) +args.modelsim_runsim_tmpl = os.path.abspath(args.modelsim_runsim_tmpl) + + +def main(): + for eachFile in args.files: + eachFile = os.path.abspath(eachFile) + pDir = os.path.dirname(eachFile) + os.chdir(pDir) + + config = ConfigParser() + config.read(eachFile) + config = config["SIMULATION_DECK"] + + # Resolve project Modelsim project path + if not args.modelsim_proj_dir: + args.modelsim_run_dir = os.path.dirname(os.path.abspath(eachFile)) + args.modelsim_proj_dir = os.path.join( + args.modelsim_run_dir, "MMSIM2") + logger.info(f"Modelsim project dir not provide " + + f"using default {args.modelsim_proj_dir} directory") + if not args.skip_prompt: + input("Press Enter to continue, Ctrl+C to abort") + args.modelsim_proj_dir = os.path.abspath(args.modelsim_proj_dir) + config["MODELSIM_PROJ_DIR"] = args.modelsim_proj_dir + if not os.path.exists(args.modelsim_proj_dir): + os.makedirs(args.modelsim_proj_dir) + + # Resolve Modelsim Project name + if not args.modelsim_proj_name: + args.modelsim_proj_name = config["BENCHMARK"] + "_MMSIM" + logger.info(f"Modelsim project name not provide " + + f"using default {args.modelsim_proj_name} directory") + + if not args.skip_prompt: + input("Press Enter to continue, Ctrl+C to abort") + config["MODELSIM_PROJ_NAME"] = args.modelsim_proj_name + config["MODELSIM_INI"] = args.modelsim_ini + + # Modify the variables in config file here + config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0] + # pass + + # Write final template file + # Write runsim file + tmpl = Template(open(args.modelsim_runsim_tmpl, + encoding='utf-8').read()) + runsim_filename = os.path.join(args.modelsim_proj_dir, + "%s_runsim.tcl" % config['BENCHMARK']) + logger.info(f"Creating tcl script at : {runsim_filename}") + with open(runsim_filename, 'w', encoding='utf-8') as tclout: + tclout.write(tmpl.substitute(config)) + + # Write proc file + proc_filename = os.path.join(args.modelsim_proj_dir, + "%s_autocheck_proc.tcl" % config['BENCHMARK']) + logger.info(f"Creating tcl script at : {proc_filename}") + with open(proc_filename, 'w', encoding='utf-8') as tclout: + tclout.write(open(args.modelsim_proc_tmpl, + encoding='utf-8').read()) + + # Execute modelsim + if args.run_sim: + os.chdir(args.modelsim_run_dir) + print(args.modelsim_run_dir) + modelsim_run_cmd = ["vsim", "-c", "-do", runsim_filename] + run_command("ModelSim Run", "modelsim_run.log", + modelsim_run_cmd) + else: + logger.info("Created runsim and proc files") + logger.info(f"runsim_filename {runsim_filename}") + logger.info(f"proc_filename {proc_filename}") + + +def run_command(taskname, logfile, command, exit_if_fail=True): + # os.chdir(os.pardir) + logger.info("Launching %s " % taskname) + with open(logfile, 'w+') as output: + try: + output.write(os.getcwd() + "\n") + output.write(" ".join(command)+"\n") + process = subprocess.run(command, + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + universal_newlines=True) + output.write(process.stdout) + if process.returncode: + logger.error("%s run failed with returncode %d" % + (taskname, process.returncode)) + except (Exception, subprocess.CalledProcessError) as e: + logger.exception("failed to execute %s" % taskname) + return None + logger.info("%s is written in file %s" % (taskname, logfile)) + return process.stdout + + +if __name__ == "__main__": + main() From 595d2d3070b3cd8a2868385efc3a38cb31aabdaf Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 18:21:26 -0600 Subject: [PATCH 389/482] Simple argument shuffle --- openfpga_flow/scripts/run_fpga_flow.py | 3 ++- openfpga_flow/scripts/run_fpga_task.py | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 110a0f506..83850ffe4 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -711,7 +711,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command += ["--fpga_verilog_print_input_blif_testbench"] if args.vpr_fpga_verilog_print_autocheck_top_testbench: command += ["--fpga_verilog_print_autocheck_top_testbench", - args.top_module+"_output_verilog.v"] + # args.vpr_fpga_verilog_print_autocheck_top_testbench] + os.path.join(args.run_dir, args.top_module+"_output_verilog.v")] if args.vpr_fpga_verilog_include_timing: command += ["--fpga_verilog_include_timing"] if args.vpr_fpga_verilog_explicit_mapping: diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index a46c99e79..061ef1248 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -367,7 +367,7 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): if task_gc.getboolean("verilog_output"): command += ["--vpr_fpga_verilog"] - command += ["--vpr_fpga_verilog_dir", "."] + command += ["--vpr_fpga_verilog_dir", curr_job_dir] command += ["--vpr_fpga_x2p_rename_illegal_port"] # Add other paramters to pass From 370a5ed40875c47831fb65a869d2ce4473b012d0 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 18:22:40 -0600 Subject: [PATCH 390/482] Bug Fix: shifter ff.v include path to tcl script --- openfpga_flow/VerilogNetlists/ff.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v index 7e902c73a..bd556f936 100644 --- a/openfpga_flow/VerilogNetlists/ff.v +++ b/openfpga_flow/VerilogNetlists/ff.v @@ -5,7 +5,7 @@ // Coder : Xifan TANG //----------------------------------------------------- //------ Include defines: preproc flags ----- -`include "./SRC/fpga_defines.v" +// `include "./SRC/fpga_defines.v" module static_dff ( /* Global ports go first */ input set, // set input From dab66b8be79389e41b04080e10906195d4671f75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 19:49:50 -0600 Subject: [PATCH 391/482] start adding auto check cpp files --- .../verilog_autocheck_top_testbench.cpp | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp new file mode 100644 index 000000000..6f60b4d21 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp @@ -0,0 +1,89 @@ +/******************************************************************** + * This file includes functions that are used to create + * an auto-check top-level testbench for a FPGA fabric + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" + +#include "fpga_x2p_utils.h" + +#include "verilog_writer_utils.h" + +#include "verilog_autocheck_top_testbench.h" + +/******************************************************************** + * The top-level function to generate a testbench, in order to verify: + * 1. Configuration phase of the FPGA fabric, where the bitstream is + * loaded to the configuration protocol of the FPGA fabric + * 2. Operating phase of the FPGA fabric, where input stimuli are + * fed to the I/Os of the FPGA fabric + *******************************************************************/ +void print_verilog_autocheck_top_testbench(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir, + const t_syn_verilog_opts& fpga_verilog_opts, + const t_spice_params& simulation_parameters) { + vpr_printf(TIO_MESSAGE_INFO, + "Writing Autocheck Testbench for FPGA Top-level Verilog netlist for %s...", + circuit_name.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Generate a brief description on the Verilog file*/ + std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; + print_verilog_file_header(fp, title); + + /* Print preprocessing flags and external netlists */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Start of testbench */ + //dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); + + /* Call defined top-level module */ + //dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, + // circuit_name, is_explicit_mapping); + + /* Call defined benchmark */ + //dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name); + + /* Add stimuli for reset, set, clock and iopad signals */ + //dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog); + + /* Add output autocheck */ + //dump_verilog_top_auto_testbench_check(fp); + + /* Add Icarus requirement */ + //dump_verilog_timeout_and_vcd(fp, circuit_name , verilog, cur_sram_orgz_info); + + /* Testbench ends*/ + //fprintf(fp, "endmodule\n"); + + /* Close the file stream */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} From 3669a47d3b78aeb7b58b072d36442622c672af04 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 20:25:01 -0600 Subject: [PATCH 392/482] reworked the ini writer --- libs/external/libini/src/ini.h | 12 ++-- .../SRC/fpga_x2p/base/simulation_utils.cpp | 42 +++++++++++++ .../vpr/SRC/fpga_x2p/base/simulation_utils.h | 15 +++++ .../verilog/simulation_info_writer.cpp | 62 +++++-------------- .../fpga_x2p/verilog/simulation_info_writer.h | 6 +- .../verilog_formal_random_top_testbench.cpp | 19 ++---- .../vpr/SRC/fpga_x2p/verilog/verilog_global.h | 4 ++ 7 files changed, 91 insertions(+), 69 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h diff --git a/libs/external/libini/src/ini.h b/libs/external/libini/src/ini.h index cb323192f..3a2040ce1 100755 --- a/libs/external/libini/src/ini.h +++ b/libs/external/libini/src/ini.h @@ -126,7 +126,7 @@ const std::string endl = "\r\n"; #else const std::string endl = "\n"; #endif -}; // namespace INIStringUtil +} // namespace INIStringUtil template class INIMap @@ -321,7 +321,7 @@ inline PDataType parseLine(std::string line, T_ParseValues &parseData) } return PDataType::PDATA_UNKNOWN; } -}; // namespace INIParser +} // namespace INIParser class INIReader { @@ -650,8 +650,8 @@ private: public: bool prettyPrint = false; - INIWriter(std::string const &filename) - : filename(filename) + INIWriter(std::string const &file_name) + : filename(file_name) { } ~INIWriter() {} @@ -709,8 +709,8 @@ private: std::string filename; public: - INIFile(std::string const &filename) - : filename(filename) + INIFile(std::string const &file_name) + : filename(file_name) { } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp new file mode 100644 index 000000000..ebc5a2aa9 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp @@ -0,0 +1,42 @@ +/******************************************************************** + * This file include most utilized functions in generating simulations + * Note: function placed here MUST be generic enough for both SPICE + * and Verilog simulations! + *******************************************************************/ +#include + +#include "simulation_utils.h" + +/******************************************************************** + * Compute the time period for the simulation + *******************************************************************/ +int find_operating_phase_simulation_time(const int& factor, + const int& num_op_clock_cycles, + const float& op_clock_period, + const float& timescale) { + /* Take into account the prog_reset and reset cycles + * 1e9 is to change the unit to ns rather than second + */ + return (factor * num_op_clock_cycles * op_clock_period) / timescale; +} + +/******************************************************************** + * Find the the full time period of a simulation, including + * both the programming time and operating time + * This is a generic function that can be used to generate simulation + * time period for SPICE/Verilog simulators + *******************************************************************/ +float find_simulation_time_period(const float &time_unit, + const int &num_prog_clock_cycles, + const float &prog_clock_period, + const int &num_op_clock_cycles, + const float &op_clock_period) { + float total_time_period = 0.; + + /* Take into account the prog_reset and reset cycles */ + total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period; + total_time_period = total_time_period / time_unit; + + return total_time_period; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h new file mode 100644 index 000000000..545c634ee --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h @@ -0,0 +1,15 @@ +#ifndef SIMULATION_UTILS_H +#define SIMULATION_UTILS_H + +int find_operating_phase_simulation_time(const int& factor, + const int& num_op_clock_cycles, + const float& op_clock_period, + const float& timescale); + +float find_simulation_time_period(const float &time_unit, + const int &num_prog_clock_cycles, + const float &prog_clock_period, + const int &num_op_clock_cycles, + const float &op_clock_period); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 520376be0..67850403d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -1,75 +1,45 @@ -/***********************************/ -/* Synthesizable Verilog Dumping */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include +/********************************************************************* + * This function includes the writer for generating exchangeable + * information, in order to interface different simulators + ********************************************************************/ #include #include -#include -#include -#include #include #define MINI_CASE_SENSITIVE #include "ini.h" /* Include vpr structs*/ #include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" /* Include FPGA-SPICE utils */ -#include "linkedlist.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_globals.h" +#include "simulation_utils.h" /* Include verilog utils */ #include "verilog_global.h" -#include "verilog_utils.h" #include "simulation_info_writer.h" -// Infile Function -static float get_verilog_modelsim_simulation_time_period(const float &time_unit, - const int &num_prog_clock_cycles, - const float &prog_clock_period, - const int &num_op_clock_cycles, - const float &op_clock_period) -{ - float total_time_period = 0.; - - /* Take into account the prog_reset and reset cycles */ - total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period; - total_time_period = total_time_period / time_unit; - - return total_time_period; -} - -/***** Top-level function *****/ +/********************************************************************* + * Top-level function to write an ini file which contains exchangeable + * information, in order to interface different Verilog simulators + ********************************************************************/ void print_verilog_simulation_info(const int &num_operating_clock_cycles, const std::string &verilog_dir_formatted, const std::string &chomped_circuit_name, const std::string &src_dir_path, const size_t &num_program_clock_cycles, const float &prog_clock_freq, - const float &op_clock_freq) -{ + const float &op_clock_freq) { mINI::INIStructure ini; // std::map units_map; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; /* Compute simulation time period */ - float simulation_time_period = get_verilog_modelsim_simulation_time_period(1E-3, - num_program_clock_cycles, - 1. / prog_clock_freq, - num_operating_clock_cycles, - 1. / op_clock_freq); + float simulation_time_period = find_simulation_time_period(1E-3, + num_program_clock_cycles, + 1. / prog_clock_freq, + num_operating_clock_cycles, + 1. / op_clock_freq); ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; ini["SIMULATION_DECK"]["BENCHMARK "] = chomped_circuit_name; @@ -82,4 +52,4 @@ void print_verilog_simulation_info(const int &num_operating_clock_cycles, mINI::INIFile file("SimulationDeckInfo.ini"); file.generate(ini, true); -} \ No newline at end of file +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h index 46c178c17..feedb8e94 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h @@ -1,5 +1,5 @@ -#ifndef VPR_API_H -#define VPR_API_H +#ifndef SIMULATION_INFO_WRITER_H +#define SIMULATION_INFO_WRITER_H #include @@ -10,4 +10,4 @@ void print_verilog_simulation_info(const int &num_operating_clock_cycles, const size_t &num_program_clock_cycles, const float &prog_clock_freq, const float &op_clock_freq); -#endif \ No newline at end of file +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index da24f7817..4277487ea 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -17,6 +17,7 @@ /* Include VPR headers*/ /* Include FPGA-X2P headers*/ +#include "simulation_utils.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_benchmark_utils.h" @@ -245,18 +246,6 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * Compute the time period for the simulation - *******************************************************************/ -static -int get_simulation_time(const int& num_op_clock_cycles, - const float& op_clock_period) { - /* Take into account the prog_reset and reset cycles - * 1e9 is to change the unit to ns rather than second - */ - return (MAGIC_NUMBER_FOR_SIMULATION_TIME * num_op_clock_cycles * op_clock_period) / verilog_sim_timescale; -} - /******************************************************************** * Print Verilog codes to set up a timeout for the simulation * and dump the waveform to VCD files @@ -583,8 +572,10 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, print_verilog_top_random_testbench_check(fp, L_logical_blocks, clock_port_names); - int simulation_time = get_simulation_time(simulation_parameters.meas_params.sim_num_clock_cycle, - 1./simulation_parameters.stimulate_params.op_clock_freq); + int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME, + simulation_parameters.meas_params.sim_num_clock_cycle, + 1./simulation_parameters.stimulate_params.op_clock_freq, + verilog_sim_timescale); /* Add Icarus requirement */ print_verilog_timeout_and_vcd(fp, circuit_name, simulation_time); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h index 73d75b766..81b1b31a6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h @@ -2,6 +2,10 @@ #define VERILOG_GLOBAL_H /* global parameters for dumping synthesizable verilog */ +#include +#include "linkedlist.h" +#include "spice_types.h" + extern char* verilog_netlist_file_postfix; extern float verilog_sim_timescale; extern char* verilog_timing_preproc_flag; // the flag to enable timing definition during compilation From 550df19ee2fa12a4e6f8d57a41705310cb400b33 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 20:26:29 -0600 Subject: [PATCH 393/482] use a stable cmake now --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 6ddea9783..716fcb1d3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -91,7 +91,7 @@ install: - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - | if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz" + CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz" mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake export PATH=${DEPS_DIR}/cmake/bin:${PATH} echo ${PATH} From a9c02cd2a56d3fae085ef50ffce7bd4bae04206a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 20:32:40 -0600 Subject: [PATCH 394/482] fix errors in travis --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 716fcb1d3..9d68dc6f4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -92,7 +92,7 @@ install: - | if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz" - mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake export PATH=${DEPS_DIR}/cmake/bin:${PATH} echo ${PATH} else From a88080280398886f7a5911a10b5c6b8c3f692fd9 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 20:51:05 -0600 Subject: [PATCH 395/482] Bug Fix: Corrected read VPR stat filename --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 83850ffe4..06a52e6d7 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -625,7 +625,7 @@ def run_vpr(): args.top_module+"_fr_chan_width_vpr.txt") logger.info("Fixed routing channel successfully routed with %d width" % min_channel_width) - extract_vpr_stats(args.top_module+"_fr_chan_width.txt") + extract_vpr_stats(args.top_module+"_fr_chan_width_vpr.txt") else: extract_vpr_stats(args.top_module+"_min_chan_width.txt") if args.power: From f70f387f9f7c6448bcb9285985ab04760a3e1d19 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 20:51:49 -0600 Subject: [PATCH 396/482] minor tuning on ini compilation --- libs/external/libini/CMakeLists.txt | 5 +++-- .../fpga_x2p/verilog/simulation_info_writer.cpp | 14 +++++++------- .../SRC/fpga_x2p/verilog/simulation_info_writer.h | 14 +++++++------- 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/libs/external/libini/CMakeLists.txt b/libs/external/libini/CMakeLists.txt index 2730c6325..c09ff863b 100644 --- a/libs/external/libini/CMakeLists.txt +++ b/libs/external/libini/CMakeLists.txt @@ -7,6 +7,7 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) #Create the library add_library(libini STATIC - ${LIB_HEADERS}) + ${LIB_HEADERS}) + target_include_directories(libini PUBLIC ${LIB_INCLUDE_DIRS}) -set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX) \ No newline at end of file +set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 67850403d..21b11c08e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -22,13 +22,13 @@ * Top-level function to write an ini file which contains exchangeable * information, in order to interface different Verilog simulators ********************************************************************/ -void print_verilog_simulation_info(const int &num_operating_clock_cycles, - const std::string &verilog_dir_formatted, - const std::string &chomped_circuit_name, - const std::string &src_dir_path, - const size_t &num_program_clock_cycles, - const float &prog_clock_freq, - const float &op_clock_freq) { +void print_verilog_simulation_info(const int& num_operating_clock_cycles, + const std::string& verilog_dir_formatted, + const std::string& chomped_circuit_name, + const std::string& src_dir_path, + const size_t& num_program_clock_cycles, + const float& prog_clock_freq, + const float& op_clock_freq) { mINI::INIStructure ini; // std::map units_map; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h index feedb8e94..ce0798fdf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h @@ -3,11 +3,11 @@ #include -void print_verilog_simulation_info(const int &num_operating_clock_cycles, - const std::string &verilog_dir_formatted, - const std::string &chomped_circuit_name, - const std::string &src_dir_path, - const size_t &num_program_clock_cycles, - const float &prog_clock_freq, - const float &op_clock_freq); +void print_verilog_simulation_info(const int& num_operating_clock_cycles, + const std::string& verilog_dir_formatted, + const std::string& chomped_circuit_name, + const std::string& src_dir_path, + const size_t& num_program_clock_cycles, + const float& prog_clock_freq, + const float& op_clock_freq); #endif From e9ed64c92694be23405d31b8d0c8c7e8c8f8893b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 21:17:35 -0600 Subject: [PATCH 397/482] try to let cmake identify libini --- CMakeLists.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6f9964539..a6d51a7c3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -182,6 +182,13 @@ set_target_properties(libace ace LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2" RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2") +# Set output locations to be in the main source tree under the relevant folder +set_target_properties(libini + PROPERTIES + ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libs/external/libini" + LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libs/external/libini" + RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libs/external/libini") + # Set output locations to be in the main source tree under the relevant folder set_target_properties(libvtrutil PROPERTIES From 17f816effd216d571537f6805b60b91425f61ee3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 21:26:22 -0600 Subject: [PATCH 398/482] try to uncache libini --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 9d68dc6f4..88d4f25e2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,7 +7,7 @@ cache: - $TRAVIS_BUILD_DIR/abc - $TRAVIS_BUILD_DIR/yosys - $TRAVIS_BUILD_DIR/ace2 - - $TRAVIS_BUILD_DIR/libs +# - $TRAVIS_BUILD_DIR/libs - $HOME/.ccache - $HOME/deps From 495000c6494be4bf18d1ec1baf76ebc854e92a62 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 21:37:17 -0600 Subject: [PATCH 399/482] recover caching for libs --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 88d4f25e2..9d68dc6f4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,7 +7,7 @@ cache: - $TRAVIS_BUILD_DIR/abc - $TRAVIS_BUILD_DIR/yosys - $TRAVIS_BUILD_DIR/ace2 -# - $TRAVIS_BUILD_DIR/libs + - $TRAVIS_BUILD_DIR/libs - $HOME/.ccache - $HOME/deps From 5c8ca81645c2db583ffa6a7f61e51dff1f4d1f2a Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 23:06:33 -0600 Subject: [PATCH 400/482] Travis failure debug --- .travis/script.sh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index bbd72cec4..804d7303e 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,19 +19,19 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - echo -e "Testing single-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py single_mode -#python3 openfpga_flow/scripts/run_fpga_task.py s298 +python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug +#python3 openfpga_flow/scripts/run_fpga_task.py s298 -echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 +# echo -e "Testing multi-mode architectures"; +# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 -echo -e "Testing compact routing techniques"; -python3 openfpga_flow/scripts/run_fpga_task.py compact_routing +# echo -e "Testing compact routing techniques"; +# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing -echo -e "Testing tileable architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing +# echo -e "Testing tileable architectures"; +# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing -echo -e "Testing Verilog generation with explicit port mapping "; -python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog +# echo -e "Testing Verilog generation with explicit port mapping "; +# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog end_section "OpenFPGA.TaskTun" From 94b60b971468d181798535d673acd6e46fd61e8f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 23:12:56 -0600 Subject: [PATCH 401/482] Travis Test: Run 2 --- run_test.sh | 120 ++++++++++++++++++++++++++-------------------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/run_test.sh b/run_test.sh index 027a1bea4..b234523eb 100644 --- a/run_test.sh +++ b/run_test.sh @@ -18,14 +18,13 @@ # Test popular multi-mode architecture python3 openfpga_flow/scripts/run_fpga_flow.py \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ -./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +./openfpga_flow/benchmarks/test_modes/test_modes.blif \ --fpga_flow vpr_blif \ --top_module test_modes \ ---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +--activity_file ./openfpga_flow/benchmarks/test_modes/test_modes.act \ +--base_verilog ./openfpga_flow/benchmarks/test_modes/test_modes.v \ --power \ --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ -#--fix_route_chan_width 300 \ --min_route_chan_width 1.3 \ --vpr_fpga_verilog \ --vpr_fpga_verilog_dir . \ @@ -42,64 +41,65 @@ python3 openfpga_flow/scripts/run_fpga_flow.py \ --vpr_fpga_verilog_print_sdc_pnr \ --vpr_fpga_verilog_print_sdc_analysis \ --vpr_fpga_x2p_compact_routing_hierarchy \ ---end_flow_with_test +--end_flow_with_test \ +--vpr_fpga_verilog_print_modelsim_autodeck /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini -# Test Standard cell MUX2 -python3 openfpga_flow/scripts/run_fpga_flow.py \ -./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ -./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ ---fpga_flow vpr_blif \ ---top_module test_modes \ ---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ ---power \ ---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ -#--fix_route_chan_width 300 \ ---min_route_chan_width 1.3 \ ---vpr_fpga_verilog \ ---vpr_fpga_verilog_dir . \ ---vpr_fpga_x2p_rename_illegal_port \ ---vpr_fpga_verilog_include_icarus_simulator \ ---vpr_fpga_verilog_formal_verification_top_netlist \ ---vpr_fpga_verilog_include_timing \ ---vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ ---debug \ ---vpr_fpga_bitstream_generator \ ---vpr_fpga_verilog_print_user_defined_template \ ---vpr_fpga_verilog_print_report_timing_tcl \ ---vpr_fpga_verilog_print_sdc_pnr \ ---vpr_fpga_verilog_print_sdc_analysis \ ---vpr_fpga_x2p_compact_routing_hierarchy \ ---end_flow_with_test +# # Test Standard cell MUX2 +# python3 openfpga_flow/scripts/run_fpga_flow.py \ +# ./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ +# ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +# --fpga_flow vpr_blif \ +# --top_module test_modes \ +# --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +# --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +# --power \ +# --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +# #--fix_route_chan_width 300 \ +# --min_route_chan_width 1.3 \ +# --vpr_fpga_verilog \ +# --vpr_fpga_verilog_dir . \ +# --vpr_fpga_x2p_rename_illegal_port \ +# --vpr_fpga_verilog_include_icarus_simulator \ +# --vpr_fpga_verilog_formal_verification_top_netlist \ +# --vpr_fpga_verilog_include_timing \ +# --vpr_fpga_verilog_include_signal_init \ +# --vpr_fpga_verilog_print_autocheck_top_testbench \ +# --debug \ +# --vpr_fpga_bitstream_generator \ +# --vpr_fpga_verilog_print_user_defined_template \ +# --vpr_fpga_verilog_print_report_timing_tcl \ +# --vpr_fpga_verilog_print_sdc_pnr \ +# --vpr_fpga_verilog_print_sdc_analysis \ +# --vpr_fpga_x2p_compact_routing_hierarchy \ +# --end_flow_with_test -# Test local encoder feature -python3 openfpga_flow/scripts/run_fpga_flow.py \ -./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \ -./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ ---fpga_flow vpr_blif \ ---top_module test_modes \ ---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ ---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ ---power \ ---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ ---fix_route_chan_width 300 \ ---vpr_fpga_verilog \ ---vpr_fpga_verilog_dir . \ ---vpr_fpga_x2p_rename_illegal_port \ ---vpr_fpga_verilog_include_icarus_simulator \ ---vpr_fpga_verilog_formal_verification_top_netlist \ ---vpr_fpga_verilog_include_timing \ ---vpr_fpga_verilog_include_signal_init \ ---vpr_fpga_verilog_print_autocheck_top_testbench \ ---debug \ ---vpr_fpga_bitstream_generator \ ---vpr_fpga_verilog_print_user_defined_template \ ---vpr_fpga_verilog_print_report_timing_tcl \ ---vpr_fpga_verilog_print_sdc_pnr \ ---vpr_fpga_verilog_print_sdc_analysis \ ---vpr_fpga_x2p_compact_routing_hierarchy \ ---end_flow_with_test +# # Test local encoder feature +# python3 openfpga_flow/scripts/run_fpga_flow.py \ +# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \ +# ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ +# --fpga_flow vpr_blif \ +# --top_module test_modes \ +# --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ +# --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ +# --power \ +# --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ +# --fix_route_chan_width 300 \ +# --vpr_fpga_verilog \ +# --vpr_fpga_verilog_dir . \ +# --vpr_fpga_x2p_rename_illegal_port \ +# --vpr_fpga_verilog_include_icarus_simulator \ +# --vpr_fpga_verilog_formal_verification_top_netlist \ +# --vpr_fpga_verilog_include_timing \ +# --vpr_fpga_verilog_include_signal_init \ +# --vpr_fpga_verilog_print_autocheck_top_testbench \ +# --debug \ +# --vpr_fpga_bitstream_generator \ +# --vpr_fpga_verilog_print_user_defined_template \ +# --vpr_fpga_verilog_print_report_timing_tcl \ +# --vpr_fpga_verilog_print_sdc_pnr \ +# --vpr_fpga_verilog_print_sdc_analysis \ +# --vpr_fpga_x2p_compact_routing_hierarchy \ +# --end_flow_with_test # Test tileable routing feature #python3 openfpga_flow/scripts/run_fpga_flow.py \ From 5bae8fecde11bf489abfa52706451f2cc9c2ac05 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Nov 2019 23:26:08 -0600 Subject: [PATCH 402/482] add debugging mode to see why travis failed --- .travis/script.sh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index bbd72cec4..7c5aab29b 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,19 +19,19 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - echo -e "Testing single-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py single_mode +python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs #python3 openfpga_flow/scripts/run_fpga_task.py s298 echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 --debug --show_thread_logs echo -e "Testing compact routing techniques"; -python3 openfpga_flow/scripts/run_fpga_task.py compact_routing +python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs echo -e "Testing tileable architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing +python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs echo -e "Testing Verilog generation with explicit port mapping "; -python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog +python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs end_section "OpenFPGA.TaskTun" From 358e9892acab5f367c40024898c7017405afa9b7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 00:09:13 -0600 Subject: [PATCH 403/482] reduce some error message to warnings --- vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp | 9 ++++++--- vpr7_x2p/vpr/SRC/route/rr_graph.c | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 4ceab180e..5efabf0bc 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -579,14 +579,17 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE); /* If we have any errors, exit */ - vpr_printf(TIO_MESSAGE_INFO, - "Finished checking circuit library with %d errors!\n", - num_err); if (0 < num_err) { + vpr_printf(TIO_MESSAGE_INFO, + "Finished checking circuit library with %d errors!\n", + num_err); exit(1); } + vpr_printf(TIO_MESSAGE_INFO, + "Checking circuit library passed.\n"); + return; } diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.c b/vpr7_x2p/vpr/SRC/route/rr_graph.c index 1c9c01e18..c637473a4 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.c @@ -1920,7 +1920,7 @@ static void check_all_tracks_reach_pins(t_type_ptr type, for (itrack = 0; itrack < nodes_per_chan; itrack++) { if (num_conns_to_track[itrack] <= 0) { - vpr_printf(TIO_MESSAGE_ERROR, "check_all_tracks_reach_pins: Track %d does not connect to any CLB %ss.\n", + vpr_printf(TIO_MESSAGE_WARNING, "check_all_tracks_reach_pins: Track %d does not connect to any CLB %ss.\n", itrack, (ipin_or_opin == DRIVER ? "OPIN" : "IPIN")); } } From c3db8805999477a0f7dd764f344989d3a14a5ac1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 09:21:02 -0600 Subject: [PATCH 404/482] adding explicit file path to simulation info writer --- .../fpga_x2p/verilog/simulation_info_writer.cpp | 17 +++++++++-------- .../fpga_x2p/verilog/simulation_info_writer.h | 1 + vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 3 +++ 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 21b11c08e..93474da0b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -23,9 +23,10 @@ * information, in order to interface different Verilog simulators ********************************************************************/ void print_verilog_simulation_info(const int& num_operating_clock_cycles, - const std::string& verilog_dir_formatted, - const std::string& chomped_circuit_name, - const std::string& src_dir_path, + const std::string& parent_dir, + const std::string& verilog_dir, + const std::string& circuit_name, + const std::string& src_dir, const size_t& num_program_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq) { @@ -42,14 +43,14 @@ void print_verilog_simulation_info(const int& num_operating_clock_cycles, 1. / op_clock_freq); ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; - ini["SIMULATION_DECK"]["BENCHMARK "] = chomped_circuit_name; - ini["SIMULATION_DECK"]["TOP_TB"] = chomped_circuit_name + std::string("_top_formal_verification_random_tb"); + ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; + ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string("_top_formal_verification_random_tb"); ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period); ini["SIMULATION_DECK"]["UNIT "] = "ms"; - ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir_path); + ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); - ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(chomped_circuit_name + "_include_netlists.v"); + ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); - mINI::INIFile file("SimulationDeckInfo.ini"); + mINI::INIFile file(parent_dir + "SimulationDeckInfo.ini"); file.generate(ini, true); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h index ce0798fdf..6be4b8f47 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h @@ -4,6 +4,7 @@ #include void print_verilog_simulation_info(const int& num_operating_clock_cycles, + const std::string& parent_dir, const std::string& verilog_dir_formatted, const std::string& chomped_circuit_name, const std::string& src_dir_path, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 998a8f2db..74a680d6c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -431,7 +431,10 @@ void vpr_fpga_verilog(ModuleManager& module_manager, print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); + + /* Print exchangeable files which contains simulation settings */ print_verilog_simulation_info(Arch.spice->spice_params.meas_params.sim_num_clock_cycle, + std::string(format_dir_path(chomped_parent_dir)), std::string(msim_dir_path), std::string(chomped_circuit_name), std::string(src_dir_path), From d5d7450ce7b0433a7ba4a4994b41caf945b56eb7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 09:46:12 -0600 Subject: [PATCH 405/482] make simulation ini writing as an option --- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 1 + vpr7_x2p/vpr/SRC/base/OptionTokens.h | 1 + vpr7_x2p/vpr/SRC/base/ReadOptions.c | 2 ++ vpr7_x2p/vpr/SRC/base/SetupVPR.c | 5 +++++ vpr7_x2p/vpr/SRC/base/vpr_api.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 ++ 7 files changed, 13 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index 78b956ce3..cdf5eef91 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -100,6 +100,7 @@ struct s_TokenPair OptionBaseTokenList[] = { { "fpga_verilog_report_timing_rpt_path", OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH }, /* Specify the simulator path for Verilog netlists */ { "fpga_verilog_print_sdc_pnr", OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR }, /* Specify the simulator path for Verilog netlists */ { "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */ + { "fpga_verilog_print_simulation_ini", OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI }, /* Specify the simulator path for Verilog netlists */ /* Xifan Tang: Bitstream generator */ { "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */ // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index 46a44ac05..706a81b24 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -117,6 +117,7 @@ enum e_OptionBaseToken { OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH, OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR, OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS, + OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI, /* Xifan Tang: Bitstream generator */ OT_FPGA_BITSTREAM_GENERATOR, OT_FPGA_BITSTREAM_OUTPUT_FILE, diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 108e9d355..54c323f9c 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -559,6 +559,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { return Args; case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS: return Args; + case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI: + return Args; /* Xifan TANG: Bitstream generator */ case OT_FPGA_BITSTREAM_GENERATOR: return Args; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 5b0e90004..1cb3fba67 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1113,6 +1113,7 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->print_sdc_pnr = FALSE; syn_verilog_opts->print_sdc_analysis = FALSE; syn_verilog_opts->include_icarus_simulator = FALSE; + syn_verilog_opts->print_simulation_ini = FALSE; /* Turn on Syn_verilog options */ if (Options.Count[OT_FPGA_VERILOG_SYN]) { @@ -1183,6 +1184,10 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->print_sdc_analysis = TRUE; } + if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) { + syn_verilog_opts->print_simulation_ini = TRUE; + } + /* SynVerilog needs the input from spice modeling */ if (FALSE == arch->read_xml_spice) { arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 7d1730883..5148daa23 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -211,6 +211,7 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n"); /* Xifan Tang: Bitstream generator */ vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 7b87d664a..95ae3784c 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1281,6 +1281,7 @@ struct s_syn_verilog_opts { boolean print_report_timing_tcl; boolean print_sdc_pnr; boolean print_sdc_analysis; + boolean print_simulation_ini; }; /* Xifan TANG: bitstream generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 74a680d6c..192e3dc63 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -431,7 +431,9 @@ void vpr_fpga_verilog(ModuleManager& module_manager, print_verilog_random_top_testbench(std::string(chomped_circuit_name), random_top_testbench_file_path, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); + } + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ print_verilog_simulation_info(Arch.spice->spice_params.meas_params.sim_num_clock_cycle, std::string(format_dir_path(chomped_parent_dir)), From e1a7a2895af3c8d4a5cb49de55b702625d5505da Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 09:59:34 -0600 Subject: [PATCH 406/482] simulation ini file name can be customizable --- vpr7_x2p/vpr/SRC/base/ReadOptions.c | 2 +- vpr7_x2p/vpr/SRC/base/ReadOptions.h | 1 + vpr7_x2p/vpr/SRC/base/SetupVPR.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_api.c | 2 +- vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + .../SRC/fpga_x2p/verilog/simulation_info_writer.cpp | 13 +++++++++++-- .../SRC/fpga_x2p/verilog/simulation_info_writer.h | 9 +++++---- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 3 ++- 8 files changed, 23 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 54c323f9c..d2f692774 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -560,7 +560,7 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS: return Args; case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI: - return Args; + return ReadString(Args, &Options->fpga_verilog_simulation_ini_path); /* Xifan TANG: Bitstream generator */ case OT_FPGA_BITSTREAM_GENERATOR: return Args; diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.h b/vpr7_x2p/vpr/SRC/base/ReadOptions.h index a637f5792..a242ba0b1 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.h +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.h @@ -107,6 +107,7 @@ struct s_options { char* fpga_verilog_reference_benchmark_file; char* fpga_verilog_modelsim_ini_path; char* fpga_verilog_report_timing_path; + char* fpga_verilog_simulation_ini_path; /* Xifan TANG: Bitstream generator */ char* fpga_bitstream_file; }; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 1cb3fba67..56ec465d2 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1186,6 +1186,7 @@ static void SetupSynVerilogOpts(t_options Options, if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) { syn_verilog_opts->print_simulation_ini = TRUE; + syn_verilog_opts->simulation_ini_path = my_strdup(Options.fpga_verilog_simulation_ini_path); } /* SynVerilog needs the input from spice modeling */ diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 5148daa23..552a90b36 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -211,7 +211,7 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini \n"); /* Xifan Tang: Bitstream generator */ vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 95ae3784c..0c3491d8d 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1282,6 +1282,7 @@ struct s_syn_verilog_opts { boolean print_sdc_pnr; boolean print_sdc_analysis; boolean print_simulation_ini; + char* simulation_ini_path; }; /* Xifan TANG: bitstream generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 93474da0b..795bdc999 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -22,12 +22,13 @@ * Top-level function to write an ini file which contains exchangeable * information, in order to interface different Verilog simulators ********************************************************************/ -void print_verilog_simulation_info(const int& num_operating_clock_cycles, +void print_verilog_simulation_info(const std::string& simulation_ini_filename, const std::string& parent_dir, const std::string& verilog_dir, const std::string& circuit_name, const std::string& src_dir, const size_t& num_program_clock_cycles, + const int& num_operating_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq) { mINI::INIStructure ini; @@ -51,6 +52,14 @@ void print_verilog_simulation_info(const int& num_operating_clock_cycles, ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); - mINI::INIFile file(parent_dir + "SimulationDeckInfo.ini"); + /* Use default name if user does not provide one */ + std::string ini_fname; + if (true == simulation_ini_filename.empty()) { + ini_fname = parent_dir + std::string("SimulationDeckInfo.ini"); + } else { + ini_fname = simulation_ini_filename; + } + + mINI::INIFile file(ini_fname); file.generate(ini, true); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h index 6be4b8f47..646b6ab5b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h @@ -3,12 +3,13 @@ #include -void print_verilog_simulation_info(const int& num_operating_clock_cycles, +void print_verilog_simulation_info(const std::string& simulation_ini_filename, const std::string& parent_dir, - const std::string& verilog_dir_formatted, - const std::string& chomped_circuit_name, - const std::string& src_dir_path, + const std::string& verilog_dir, + const std::string& circuit_name, + const std::string& src_dir, const size_t& num_program_clock_cycles, + const int& num_operating_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 192e3dc63..21a794a62 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -435,12 +435,13 @@ void vpr_fpga_verilog(ModuleManager& module_manager, if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ - print_verilog_simulation_info(Arch.spice->spice_params.meas_params.sim_num_clock_cycle, + print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path), std::string(format_dir_path(chomped_parent_dir)), std::string(msim_dir_path), std::string(chomped_circuit_name), std::string(src_dir_path), bitstream_manager.bits().size(), + Arch.spice->spice_params.meas_params.sim_num_clock_cycle, Arch.spice->spice_params.stimulate_params.prog_clock_freq, Arch.spice->spice_params.stimulate_params.op_clock_freq); } From f042c35edfc1bf241d51e6f9047e26796f8b6891 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 1 Nov 2019 23:26:31 -0600 Subject: [PATCH 407/482] Travis Experiments Squashed --- .gitignore | 3 +- .travis.yml | 176 +++++++++++++++++++--------------------------- .travis/script.sh | 18 ++--- deploy_key.enc | Bin 0 -> 3248 bytes 4 files changed, 84 insertions(+), 113 deletions(-) create mode 100644 deploy_key.enc diff --git a/.gitignore b/.gitignore index fc6dbf3a5..dade84a47 100644 --- a/.gitignore +++ b/.gitignore @@ -44,4 +44,5 @@ fpga_flow/csv_rpts tmp/ build/ -message.txt \ No newline at end of file +message.txt +deploy_key \ No newline at end of file diff --git a/.travis.yml b/.travis.yml index 9d68dc6f4..f269bbd50 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,116 +1,86 @@ language: cpp - -# cache results - cache: directories: - - $TRAVIS_BUILD_DIR/abc - - $TRAVIS_BUILD_DIR/yosys - - $TRAVIS_BUILD_DIR/ace2 - - $TRAVIS_BUILD_DIR/libs - - $HOME/.ccache - - $HOME/deps - -# Currently sudo is not required, NO ENV is used - -# Supported Operating systems -#os: -# - linux -# - osx -# Create a matrix to branch the building environment + - "$TRAVIS_BUILD_DIR/abc" + - "$TRAVIS_BUILD_DIR/yosys" + - "$TRAVIS_BUILD_DIR/ace2" + - "$TRAVIS_BUILD_DIR/libs" + - "$HOME/.ccache" + - "$HOME/deps" matrix: include: - - os: linux - # Compiler is specified in ./travis/common.sh - sudo: false - dist: bionic - compiler: g++-8 - addons: - apt: - sources: - - ubuntu-toolchain-r-test # For newer GCC - - george-edison55-precise-backports # For cmake - packages: - - autoconf - - automake - - bash - - bison - - build-essential - - cmake - - ctags - - curl - - doxygen - - flex - - fontconfig - - g++-8 - - gcc-8 - - gdb - - git - - gperf - - iverilog - - libcairo2-dev - - libevent-dev - - libfontconfig1-dev - - liblist-moreutils-perl - - libncurses5-dev - - libx11-dev - - libxft-dev - - libxml++2.6-dev - - perl - - python - - texinfo - - time - - valgrind - - zip - - qt5-default -# - os: osx -# osx_image: xcode10.2 # we target latest MacOS Mojave -# sudo: true -# compiler: gcc-4.9 # Use clang instead of gcc in MacOS -# addons: -# homebrew: -# packages: -# - bison -# - cmake -# - ctags -# - flex -# - fontconfig -# - git -# - gcc@6 -# - gcc@4.9 -# - gawk -# - icarus-verilog -# - libxml++ -# - qt5 - + - os: linux + sudo: false + dist: bionic + compiler: g++-8 + addons: + apt: + sources: + - sourceline: ppa:ubuntu-toolchain-r/test + packages: + - autoconf + - automake + - bash + - bison + - build-essential + - cmake + - ctags + - curl + - doxygen + - flex + - fontconfig + - g++-8 + - gcc-8 + - gdb + - git + - gperf + - iverilog + - libcairo2-dev + - libevent-dev + - libfontconfig1-dev + - liblist-moreutils-perl + - libncurses5-dev + - libx11-dev + - libxft-dev + - libxml++2.6-dev + - perl + - python + - texinfo + - time + - valgrind + - zip + - qt5-default before_install: - - source .travis/common.sh - +- openssl aes-256-cbc -K $encrypted_6f6cf68308be_key -iv $encrypted_6f6cf68308be_iv -in deploy_key.enc -out ./deploy_key -d +- eval "$(ssh-agent -s)" +- chmod 600 ./deploy_key +- echo -e "Host $SERVER_IP_ADDRESS\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config +- ssh-add ./deploy_key +- ssh -o StrictHostKeyChecking=no -i ./deploy_key u1249762@lab1-1.eng.utah.edu pwd +- echo $TRAVIS_JOB_ID >> build_id.txt +- scp -o StrictHostKeyChecking=no -i ./deploy_key build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/build_id.txt +- source .travis/common.sh install: - - DEPS_DIR="${HOME}/deps" - - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} - - | - if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then - CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz" - mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake - export PATH=${DEPS_DIR}/cmake/bin:${PATH} - echo ${PATH} - else - brew install cmake || brew upgrade cmake - fi - - cmake --version - - cd - - - source .travis/install.sh - +- DEPS_DIR="${HOME}/deps" +- mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR} +- | + if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then + CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz" + mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake + export PATH=${DEPS_DIR}/cmake/bin:${PATH} + echo ${PATH} + else + brew install cmake || brew upgrade cmake + fi +- cmake --version +- cd - +- source .travis/install.sh script: - - .travis/script.sh - #- .travis/regression.sh - +- ".travis/script.sh" after_failure: - - .travis/after_failure.sh - +- ".travis/after_failure.sh" after_success: - - .travis/after_success.sh +- ".travis/after_success.sh" notifications: slack: secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw= diff --git a/.travis/script.sh b/.travis/script.sh index 804d7303e..9e17f36c3 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,19 +19,19 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - echo -e "Testing single-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug +python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs #python3 openfpga_flow/scripts/run_fpga_task.py s298 -# echo -e "Testing multi-mode architectures"; -# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 +echo -e "Testing multi-mode architectures"; +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 -# echo -e "Testing compact routing techniques"; -# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing +echo -e "Testing compact routing techniques"; +python3 openfpga_flow/scripts/run_fpga_task.py compact_routing -# echo -e "Testing tileable architectures"; -# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing +echo -e "Testing tileable architectures"; +python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing -# echo -e "Testing Verilog generation with explicit port mapping "; -# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog +echo -e "Testing Verilog generation with explicit port mapping "; +python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog end_section "OpenFPGA.TaskTun" diff --git a/deploy_key.enc b/deploy_key.enc new file mode 100644 index 0000000000000000000000000000000000000000..a5015fb2dd796bf4c4ec17b11224c01e3dff7b3a GIT binary patch literal 3248 zcmV;h3{Ue-4 z^zn5!R3pk&60OC`s%%G|eNcZmcKFMQ9D-&$NX#I$yKkw_vf%glAqT#K$<4p?LJaH` z5CR7w!pQBUUDRXmo}unCigZ?BkSaNw*L!)$R)ii!fW;{H!qk9%$rL&pyiN#Q@W;tj zr$jmn?GmS-%$}}vd%9Cw?uTc&?Ng4@mh&@=85oXCxH38qAj1yCm3|07vgZ=>f-?G7 z5whR1>QjO=6P)Hjcax-m`YwasZ2!a9O8QCZQG2>M`WBN#+0tQ99Cw^@3JcJ6B-%yrSnCw zIE%tG42wORZdQO?K(N3}jLysrUT~OP#U~BzEf7mwkJKRtIUX9Ju9|AFj#bFGb@ueT z{90@HJ%b>9{|XM-{Ccd2q~y7_Vh>+RFBWAmh^66>)>Pgk>0%EDip|m za(YL?Ev?T`0NT93g+aKT9$%H+EhmRH(6B3q>l9)RN6s1IyuD8badFvnCfVZzE7|lyg9W};fqw9Iq-8qZM5*X z{`KOp3na|SUJdadhnvkWd}!~H`2+*pD=>xABjmKFQ;6wV#m;nO)E<1BQMxi1GX8w6 zdy{PumT*ai_`qYZptl5E0!O}z*MYU8Fm-$@Nr*Y4p;6$iV48x#z%d^tr>Qm|1$e(E zYLOT?a_n{AV~#p3JSf)myt^z?${ba3dHX`3hP^G$q<@3F?(@(_m-TtVGct0Qlv1-- zrC2onKx2ftgp0zX1mFeKu3FhLEQlY8`87{oJc7gMnF~Z zI6+EsxJW8EI1l9*6(rOiEQm#R*@}SREuf|Cv1O_%y!0oZx`bS_AI>qrXpbLr1XS$T z3#|-(65rQEr}Zo>3y3bvC^+o^r=qhG<`Z7^cO7i+Bs=>^aJ};G=I8%Dc@X%8C%Z@e?pNju) zDI!`ti~qnZR3e=4Nhm^^=*W$9LNOM6m@Q41uXLBdP+o*pt_Fs{D?^m`u`)eD;s#4} z^6>$i9*E_Mla+B!Gwkgd-2JB)>=pKuvhlI$6#Rlyv0*(nV(H)n{B`b5nkj9;yZ7oN zVq$ybvwTRy6QC-+49%X`9ivFr)y_3cEM<5S&(=xHf#%5az6;Ih~Yg+ z9;z9$zsp*f6s5*YKBez##e!q!s7}jzihC?HJ?$ZI*O?eMjB*;$LRNd6z(T8Wid{jm zF9(J%fxJJ~%#BhAHq9pV^E-vNNnLRW!s6`c!Gm(@F9J+&eyh4qi;Lv62P_3S!P{ME zfq*l~;QWN|Lhc535q}-rJjoEDLDp+cgfBO10=iEoYM@SVhGkDjAg$!vkUBQ}H^Jyg z2{4^evp8dko}@k7<~6u6j{jz(?6*P*N9Qv_d|jR?o?#2%d_%h>tLU#%B;#U^y zIGnO!S~mZ*J1<(MpuNrUvoH~)7rvoj3Ntu0 zQPK?epDcRfp2rE?BPqHlW`D zyW0zP%aH3>x1}2&_R4Orn{V6aod_oxl`F=1A=(uYp$Z&vdqpiR39RahP$=Gqf@Ue$ z((}QT4)9yA*v93Y{+tPxG6|T>wn zXU=4gSaAFRTwgSs(a76arGhT+Sa{Jd>@U+`NPbIE#4f5$n>?~ylmJe4ivr^H35FNW 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1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 9d68dc6f4..431f5a02c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,7 +9,7 @@ cache: - $TRAVIS_BUILD_DIR/ace2 - $TRAVIS_BUILD_DIR/libs - $HOME/.ccache - - $HOME/deps +# - $HOME/deps # Currently sudo is not required, NO ENV is used From fc164abd4951c760ceb04b212c34bb5734f6cd98 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 16:35:32 -0600 Subject: [PATCH 409/482] remove unused variable in sim info writer --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp | 1 - vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h | 1 - vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 1 - 3 files changed, 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 795bdc999..11ab48b74 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -24,7 +24,6 @@ ********************************************************************/ void print_verilog_simulation_info(const std::string& simulation_ini_filename, const std::string& parent_dir, - const std::string& verilog_dir, const std::string& circuit_name, const std::string& src_dir, const size_t& num_program_clock_cycles, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h index 646b6ab5b..9644e2a63 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h @@ -5,7 +5,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, const std::string& parent_dir, - const std::string& verilog_dir, const std::string& circuit_name, const std::string& src_dir, const size_t& num_program_clock_cycles, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 21a794a62..c80264bf0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -437,7 +437,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, /* Print exchangeable files which contains simulation settings */ print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path), std::string(format_dir_path(chomped_parent_dir)), - std::string(msim_dir_path), std::string(chomped_circuit_name), std::string(src_dir_path), bitstream_manager.bits().size(), From 3ef978acccae5bc77ded02ff89a1e471096be5f0 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 2 Nov 2019 16:37:00 -0600 Subject: [PATCH 410/482] Updated Encrypt Key --- deploy_key.enc | Bin 3248 -> 3248 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/deploy_key.enc b/deploy_key.enc index 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zB2w>HbF(PGO-!uhoo3nc72mcce1L@0e<>K|Tl&nL0}tjmPm;NRvqCd^v_NyFvuIm} zPIEAgy44ipcUyo?Y*}XQ)QisPQk8MfvEB9D*l^O43Gj-n)Nw2c0i=Z0H6BA?#x=~| zr=}zGUf(IphrZ|n1ZI#Z>d7jT%Foj_?~c6$?g-_7?2ES%*aZ*2z%5&40A-O4DeRZ} z9od5E(Jl}k;FLkLt^sax)pKl%<5ISEfTsBv?H%OAIDMse@ErU}>`Ug;v8-+ss0z4z zNykkO1s&JyeMoBn=h$TZZxzcUwuxJJhM2Oig7W-r2;p(c9hocMb@Q1= z9+8)IJLBU_jFxKI`f;C}U6PgLNEXklG4m?&D-+?e@;8|yPYaL>0oH1Rtau@oc~#d$3N From cb74d120e775807a02ccfcbebc0c422a6c613a47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 17:31:05 -0600 Subject: [PATCH 411/482] shadow ini writer to help debugging --- vpr7_x2p/vpr/CMakeLists.txt | 8 ++--- .../verilog/simulation_info_writer.cpp | 11 +++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 +++- .../verilog/verilog_formality_autodeck.c | 32 +++++++++---------- 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/vpr7_x2p/vpr/CMakeLists.txt b/vpr7_x2p/vpr/CMakeLists.txt index 0fa11717e..81751b3d6 100644 --- a/vpr7_x2p/vpr/CMakeLists.txt +++ b/vpr7_x2p/vpr/CMakeLists.txt @@ -65,14 +65,14 @@ if (ENABLE_VPR_GRAPHIC_CXX_FLAG) libarchfpga X11 libvtrutil - readline - libini) + #libini + readline) else () target_link_libraries(libvpr libarchfpga libvtrutil - readline - libini) + #libini + readline) endif() #Create the executables diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index 11ab48b74..f486ecf05 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -5,8 +5,8 @@ #include #include #include -#define MINI_CASE_SENSITIVE -#include "ini.h" +//#define MINI_CASE_SENSITIVE +//#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -30,7 +30,9 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, const int& num_operating_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq) { + /* mINI::INIStructure ini; + */ // std::map units_map; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; @@ -41,7 +43,7 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, 1. / prog_clock_freq, num_operating_clock_cycles, 1. / op_clock_freq); - + /* ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string("_top_formal_verification_random_tb"); @@ -50,6 +52,7 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); + */ /* Use default name if user does not provide one */ std::string ini_fname; @@ -59,6 +62,8 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini_fname = simulation_ini_filename; } + /* mINI::INIFile file(ini_fname); file.generate(ini, true); + */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index c80264bf0..8991680a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -418,11 +418,13 @@ void vpr_fpga_verilog(ModuleManager& module_manager, std::string(src_dir_path)); /* Output script for formality */ + /* write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, fm_dir_path, src_dir_path, chomped_circuit_name, *(Arch.spice)); + */ /* Print out top-level testbench using random vectors */ std::string random_top_testbench_file_path = std::string(src_dir_path) @@ -432,9 +434,10 @@ void vpr_fpga_verilog(ModuleManager& module_manager, std::string(src_dir_path), L_logical_blocks, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); } - + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ + /* print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path), std::string(format_dir_path(chomped_parent_dir)), std::string(chomped_circuit_name), @@ -443,6 +446,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager, Arch.spice->spice_params.meas_params.sim_num_clock_cycle, Arch.spice->spice_params.stimulate_params.prog_clock_freq, Arch.spice->spice_params.stimulate_params.op_clock_freq); + */ } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index 33f587a75..1ffa58bea 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -10,8 +10,8 @@ #include #include #include -#define MINI_CASE_SENSITIVE -#include "ini.h" +//#define MINI_CASE_SENSITIVE +//#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -41,7 +41,7 @@ #include "verilog_routing.h" #include "verilog_tcl_utils.h" -mINI::INIStructure ini; +//mINI::INIStructure ini; static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){ int i, j; @@ -80,7 +80,7 @@ static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chompe inst_name, gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node)); sprintf(INI_lbl, "%s_reg", pb->name); - ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; + //ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; } //free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp return; @@ -199,11 +199,11 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, /* Load Verilog benchmark as reference */ fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path); - ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; + //ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; /* Set reference top */ fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name); - ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; + //ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; /* Load generated verilog as implemnetation */ fprintf(fp, "read_verilog -container i -libname WORK -05 { "); @@ -213,7 +213,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, sprintf(WriteBuffer, "%s%s%s", src_dir_formatted, chomped_circuit_name, verilog_top_postfix); sprintf(INI_lbl, "impl_netlist_%02d",FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; fprintf(fp, "%s%s%s ", src_dir_formatted, chomped_circuit_name, @@ -221,7 +221,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, chomped_circuit_name, formal_verification_verilog_file_postfix); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; init_include_user_defined_verilog_netlists(spice); // formality_include_user_defined_verilog_netlists(fp, spice); @@ -232,7 +232,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, assert(NULL != spice.include_netlists[i].path); fprintf(fp, "%s ", spice.include_netlists[i].path); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; + //ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; spice.include_netlists[i].included = 1; } else { assert(1 == spice.include_netlists[i].included); @@ -246,7 +246,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_rr_dir_name, routing_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fprintf(fp, "%s%s%s ", src_dir_formatted, default_lb_dir_name, @@ -255,7 +255,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_lb_dir_name, logic_block_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fprintf(fp, "%s%s%s ", src_dir_formatted, default_submodule_dir_name, @@ -264,7 +264,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_submodule_dir_name, submodule_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; fprintf(fp, "}\n"); /* Set implementation top */ @@ -272,7 +272,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, formal_verification_top_postfix)); sprintf(WriteBuffer, "%s", my_strcat(chomped_circuit_name, formal_verification_top_postfix)); - ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; + //ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; /* Run matching */ fprintf(fp, "match\n"); @@ -299,7 +299,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); sprintf(INI_lbl, "%s", original_output_name); - ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; + //ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; } } } @@ -309,7 +309,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, /* Script END */ fclose(fp); - mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); - file.generate(ini, true); + //mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); + //file.generate(ini, true); return; } From 644ca4f0a4cf2a46330f49cb0e0c7b63bf3e8c66 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 17:49:22 -0600 Subject: [PATCH 412/482] add vpr test run in Travis --- .travis/script.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis/script.sh b/.travis/script.sh index 7c5aab29b..cca32dcce 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,6 +18,8 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - +./vpr7_x2p/vpr/vpr ./openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif --net_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.net --place_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.place --route_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.route --full_stats --nodisp --activity_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act --power --tech_properties ./openfpga_flow/tech/PTM_45nm/45nm.xml --fpga_x2p_compact_routing_hierarchy --fpga_verilog --fpga_verilog_dir ./verilog --fpga_verilog_print_autocheck_top_testbench K4n4_test_output_verilog.v --fpga_verilog_include_timing --fpga_verilog_explicit_mapping --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --fpga_verilog_print_sdc_pnr --fpga_verilog_print_user_defined_template --fpga_verilog_print_sdc_analysis --fpga_bitstream_generator --fpga_x2p_rename_illegal_port + echo -e "Testing single-mode architectures"; python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs #python3 openfpga_flow/scripts/run_fpga_task.py s298 From d14be73825da01c5e107a6e68ad794c4cee91d2f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 2 Nov 2019 17:51:30 -0600 Subject: [PATCH 413/482] Added backup option in travis failure --- .travis.yml | 9 +++++---- .travis/after_failure.sh | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index f269bbd50..17b66e798 100644 --- a/.travis.yml +++ b/.travis.yml @@ -54,11 +54,12 @@ before_install: - openssl aes-256-cbc -K $encrypted_6f6cf68308be_key -iv $encrypted_6f6cf68308be_iv -in deploy_key.enc -out ./deploy_key -d - eval "$(ssh-agent -s)" - chmod 600 ./deploy_key -- echo -e "Host $SERVER_IP_ADDRESS\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config -- ssh-add ./deploy_key -- ssh -o StrictHostKeyChecking=no -i ./deploy_key u1249762@lab1-1.eng.utah.edu pwd +- cp $TRAVIS_BUILD_DIR/deploy_key ~/.ssh/id_rsa +- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config +- ssh u1249762@lab1-1.eng.utah.edu pwd +- ssh u1249762@lab1-1.eng.utah.edu "mkdir /var/tmp/travis_bc/$TRAVIS_JOB_ID" - echo $TRAVIS_JOB_ID >> build_id.txt -- scp -o StrictHostKeyChecking=no -i ./deploy_key build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/build_id.txt +- scp build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/ - source .travis/common.sh install: - DEPS_DIR="${HOME}/deps" diff --git a/.travis/after_failure.sh b/.travis/after_failure.sh index 95f8bd80c..fbbbda957 100755 --- a/.travis/after_failure.sh +++ b/.travis/after_failure.sh @@ -9,4 +9,7 @@ travis_fold end after_failure.1 start_section "failure.tail" "${RED}Failure output...${NC}" tail -n 1000 output.log +echo "Failed uploading files to LNIS Server" +scp -qCr $TRAVIS_BUILD_DIR/openfpga_flow/tasks/ u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/ +scp output.log u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/ end_section "failure.tail" From 3ad2a93539e943faf4f6a84e8ca428a2c0e984b7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 18:20:25 -0600 Subject: [PATCH 414/482] start bring back ini writer bit by bit --- .travis/script.sh | 2 -- vpr7_x2p/vpr/CMakeLists.txt | 4 ++-- .../SRC/fpga_x2p/verilog/simulation_info_writer.cpp | 10 ++-------- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 -- 4 files changed, 4 insertions(+), 14 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index cca32dcce..7c5aab29b 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,8 +18,6 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -./vpr7_x2p/vpr/vpr ./openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif --net_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.net --place_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.place --route_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.route --full_stats --nodisp --activity_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act --power --tech_properties ./openfpga_flow/tech/PTM_45nm/45nm.xml --fpga_x2p_compact_routing_hierarchy --fpga_verilog --fpga_verilog_dir ./verilog --fpga_verilog_print_autocheck_top_testbench K4n4_test_output_verilog.v --fpga_verilog_include_timing --fpga_verilog_explicit_mapping --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --fpga_verilog_print_sdc_pnr --fpga_verilog_print_user_defined_template --fpga_verilog_print_sdc_analysis --fpga_bitstream_generator --fpga_x2p_rename_illegal_port - echo -e "Testing single-mode architectures"; python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs #python3 openfpga_flow/scripts/run_fpga_task.py s298 diff --git a/vpr7_x2p/vpr/CMakeLists.txt b/vpr7_x2p/vpr/CMakeLists.txt index 81751b3d6..2e70b82fa 100644 --- a/vpr7_x2p/vpr/CMakeLists.txt +++ b/vpr7_x2p/vpr/CMakeLists.txt @@ -65,13 +65,13 @@ if (ENABLE_VPR_GRAPHIC_CXX_FLAG) libarchfpga X11 libvtrutil - #libini + libini readline) else () target_link_libraries(libvpr libarchfpga libvtrutil - #libini + libini readline) endif() diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index f486ecf05..aa59a003b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -5,8 +5,8 @@ #include #include #include -//#define MINI_CASE_SENSITIVE -//#include "ini.h" +#define MINI_CASE_SENSITIVE +#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -30,9 +30,7 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, const int& num_operating_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq) { - /* mINI::INIStructure ini; - */ // std::map units_map; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; @@ -43,7 +41,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, 1. / prog_clock_freq, num_operating_clock_cycles, 1. / op_clock_freq); - /* ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string("_top_formal_verification_random_tb"); @@ -52,7 +49,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); - */ /* Use default name if user does not provide one */ std::string ini_fname; @@ -62,8 +58,6 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini_fname = simulation_ini_filename; } - /* mINI::INIFile file(ini_fname); file.generate(ini, true); - */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 8991680a8..074fb557b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -437,7 +437,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ - /* print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path), std::string(format_dir_path(chomped_parent_dir)), std::string(chomped_circuit_name), @@ -446,7 +445,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, Arch.spice->spice_params.meas_params.sim_num_clock_cycle, Arch.spice->spice_params.stimulate_params.prog_clock_freq, Arch.spice->spice_params.stimulate_params.op_clock_freq); - */ } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { From c6817261244d2e177053ccaca64c52a8290ddff6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 18:33:05 -0600 Subject: [PATCH 415/482] try to enlarge write buffers in ini writer, but these codes should be fully reworked --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 -- .../vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 074fb557b..4c1c4a223 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -418,13 +418,11 @@ void vpr_fpga_verilog(ModuleManager& module_manager, std::string(src_dir_path)); /* Output script for formality */ - /* write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, fm_dir_path, src_dir_path, chomped_circuit_name, *(Arch.spice)); - */ /* Print out top-level testbench using random vectors */ std::string random_top_testbench_file_path = std::string(src_dir_path) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index 1ffa58bea..7e28655fd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -177,8 +177,8 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, char* formality_script_file_name = NULL; char* benchmark_path = NULL; char* original_output_name = NULL; - char WriteBuffer[200]; - char INI_lbl[20]; + char WriteBuffer[4096]; + char INI_lbl[4096]; /* int output_length; */ /* int pos; */ FILE* fp = NULL; From c80cbfe8c9464eb60a63134c9e5af1a1a3733325 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 2 Nov 2019 17:55:36 -0600 Subject: [PATCH 416/482] Removed files after regression test --- .travis.yml | 2 +- .travis/script.sh | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 17b66e798..d4f2d90ad 100644 --- a/.travis.yml +++ b/.travis.yml @@ -55,7 +55,7 @@ before_install: - eval "$(ssh-agent -s)" - chmod 600 ./deploy_key - cp $TRAVIS_BUILD_DIR/deploy_key ~/.ssh/id_rsa -- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config +- echo -e "Host *\n StrictHostKeyChecking no\n" >> ~/.ssh/config - ssh u1249762@lab1-1.eng.utah.edu pwd - ssh u1249762@lab1-1.eng.utah.edu "mkdir /var/tmp/travis_bc/$TRAVIS_JOB_ID" - echo $TRAVIS_JOB_ID >> build_id.txt diff --git a/.travis/script.sh b/.travis/script.sh index 9e17f36c3..09187ef2a 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,19 +19,24 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - echo -e "Testing single-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py single_mode +python3 openfpga_flow/scripts/run_fpga_task.py single_mode --remove_run_dir all #python3 openfpga_flow/scripts/run_fpga_task.py s298 echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 2 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --remove_run_dir all echo -e "Testing compact routing techniques"; python3 openfpga_flow/scripts/run_fpga_task.py compact_routing +python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --remove_run_dir all echo -e "Testing tileable architectures"; python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing +python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --remove_run_dir all echo -e "Testing Verilog generation with explicit port mapping "; python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog +python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --remove_run_dir all end_section "OpenFPGA.TaskTun" From 05a830de1bd57635303262fb32fcd7277032f549 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 18:56:54 -0600 Subject: [PATCH 417/482] bring ini writer for formality scripts back --- .../verilog/verilog_formality_autodeck.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c index 7e28655fd..0052ab079 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formality_autodeck.c @@ -10,8 +10,8 @@ #include #include #include -//#define MINI_CASE_SENSITIVE -//#include "ini.h" +#define MINI_CASE_SENSITIVE +#include "ini.h" /* Include vpr structs*/ #include "util.h" @@ -41,7 +41,7 @@ #include "verilog_routing.h" #include "verilog_tcl_utils.h" -//mINI::INIStructure ini; +mINI::INIStructure ini; static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chomped_circuit_name, char* inst_name){ int i, j; @@ -80,7 +80,7 @@ static void searching_used_latch(FILE *fp, t_pb * pb, int pb_index, char* chompe inst_name, gen_verilog_one_pb_graph_node_full_name_in_hierarchy(node)); sprintf(INI_lbl, "%s_reg", pb->name); - //ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; + ini["REGISTER_MATCH"][INI_lbl] = WriteBuffer; } //free(tmp); //Looks like is the cause of a double free, once free executated next iteration as no value in tmp return; @@ -199,11 +199,11 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, /* Load Verilog benchmark as reference */ fprintf(fp, "read_verilog -container r -libname WORK -05 { %s }\n", benchmark_path); - //ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; + ini["BENCHMARK_INFO"]["benchmark_netlist "] = benchmark_path; /* Set reference top */ fprintf(fp, "set_top r:/WORK/%s\n", chomped_circuit_name); - //ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; + ini["BENCHMARK_INFO"]["src_top_module "] = chomped_circuit_name; /* Load generated verilog as implemnetation */ fprintf(fp, "read_verilog -container i -libname WORK -05 { "); @@ -213,7 +213,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, sprintf(WriteBuffer, "%s%s%s", src_dir_formatted, chomped_circuit_name, verilog_top_postfix); sprintf(INI_lbl, "impl_netlist_%02d",FileCounter++); - //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; fprintf(fp, "%s%s%s ", src_dir_formatted, chomped_circuit_name, @@ -221,7 +221,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, sprintf(WriteBuffer, "%s%s%s\n", src_dir_formatted, chomped_circuit_name, formal_verification_verilog_file_postfix); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; init_include_user_defined_verilog_netlists(spice); // formality_include_user_defined_verilog_netlists(fp, spice); @@ -232,7 +232,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, assert(NULL != spice.include_netlists[i].path); fprintf(fp, "%s ", spice.include_netlists[i].path); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - //ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; + ini["FPGA_INFO"][INI_lbl] = spice.include_netlists[i].path; spice.include_netlists[i].included = 1; } else { assert(1 == spice.include_netlists[i].included); @@ -246,7 +246,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_rr_dir_name, routing_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fprintf(fp, "%s%s%s ", src_dir_formatted, default_lb_dir_name, @@ -255,7 +255,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_lb_dir_name, logic_block_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fprintf(fp, "%s%s%s ", src_dir_formatted, default_submodule_dir_name, @@ -264,7 +264,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, default_submodule_dir_name, submodule_verilog_file_name); sprintf(INI_lbl, "impl_netlist_%02d", FileCounter++); - //ini["FPGA_INFO"][INI_lbl] = WriteBuffer; + ini["FPGA_INFO"][INI_lbl] = WriteBuffer; fprintf(fp, "}\n"); /* Set implementation top */ @@ -272,7 +272,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, formal_verification_top_postfix)); sprintf(WriteBuffer, "%s", my_strcat(chomped_circuit_name, formal_verification_top_postfix)); - //ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; + ini["FPGA_INFO"]["impl_top_module"] = WriteBuffer; /* Run matching */ fprintf(fp, "match\n"); @@ -299,7 +299,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, my_strcat(logical_block[iblock].name, formal_verification_top_module_port_postfix)); sprintf(INI_lbl, "%s", original_output_name); - //ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; + ini["PORT_MATCHING"][INI_lbl] = WriteBuffer; } } } @@ -309,7 +309,7 @@ void write_formality_script (t_syn_verilog_opts fpga_verilog_opts, /* Script END */ fclose(fp); - //mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); - //file.generate(ini, true); + mINI::INIFile file(my_strcat(formality_script_file_name,".ini")); + file.generate(ini, true); return; } From dc241e6c03b778c278c5d1310295d61685db905e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 2 Nov 2019 23:03:47 -0600 Subject: [PATCH 418/482] add explicit port mapping support in testbenches; remove dangling ports in benchmarks --- .../benchmarks/mcnc_big20/apex2/apex2.act | 1 - .../benchmarks/mcnc_big20/apex2/apex2.blif | 2 +- .../benchmarks/mcnc_big20/apex2/apex2.v | 3 +- .../tasks/mcnc_big20/config/task.conf | 23 ++++++----- .../verilog_formal_random_top_testbench.cpp | 40 +++++++++++++++---- 5 files changed, 48 insertions(+), 21 deletions(-) diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act index 9bc344191..b91e3bfa6 100644 --- a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act +++ b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act @@ -13,7 +13,6 @@ i_11_ 0.495600 0.504600 i_12_ 0.502800 0.507600 i_13_ 0.494600 0.500600 i_14_ 0.504800 0.502800 -i_15_ 0.487600 0.495200 i_16_ 0.504000 0.505200 i_17_ 0.497400 0.512600 i_18_ 0.502200 0.502200 diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif index 7ba78bd10..69f1a70c6 100644 --- a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif +++ b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif @@ -1,7 +1,7 @@ # Benchmark "apex2" written by ABC on Tue Mar 12 09:34:21 2019 .model apex2 .inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ - i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ \ + i_13_ i_14_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ \ i_25_ i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ \ i_37_ i_38_ .outputs o_0_ o_1_ o_2_ diff --git a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v index b1e082d06..5a7719ec8 100644 --- a/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v +++ b/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v @@ -1,13 +1,12 @@ /* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */ -module apex2(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, o_0_, o_1_, o_2_); +module apex2(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, o_0_, o_1_, o_2_); input i_0_; input i_10_; input i_11_; input i_12_; input i_13_; input i_14_; - input i_15_; input i_16_; input i_17_; input i_18_; diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index 50d2402b8..ef31fe375 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -15,13 +15,16 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml #arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml -#arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +# Pass +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +# Fail, due to port does not match, i_15_ is dangling #bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif +# To be tested #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif #bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif #bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif @@ -34,8 +37,10 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif #bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif #bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif #bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif -#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif # Pass -#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif # Multi-mode support fails to repack +# Pass +#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif +# Multi-mode support fails to repack +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif #bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif @@ -147,10 +152,10 @@ vpr_fpga_verilog_include_signal_init= vpr_fpga_verilog_print_autocheck_top_testbench= vpr_fpga_bitstream_generator= vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_verilog_explicit_mapping= vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= +#end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 4277487ea..9f08f33f6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -182,8 +182,11 @@ static void print_verilog_random_testbench_instance(std::fstream& fp, const std::string& module_name, const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, const std::string& output_port_postfix, - const std::vector& L_logical_blocks) { + const std::vector& L_logical_blocks, + const bool& use_explicit_port_map) { /* Validate the file stream */ check_file_handler(fp); @@ -202,10 +205,24 @@ void print_verilog_random_testbench_instance(std::fstream& fp, } /* Input port follows the logical block name while output port requires a special postfix */ if (VPACK_INPAD == lb.type){ - fp << "\t\t" << std::string(lb.name); + fp << "\t\t"; + if (true == use_explicit_port_map) { + fp << "." << std::string(lb.name) << module_input_port_postfix << "("; + } + fp << std::string(lb.name); + if (true == use_explicit_port_map) { + fp << ")"; + } } else { VTR_ASSERT_SAFE(VPACK_OUTPAD == lb.type); - fp << "\t\t" << std::string(lb.name) << output_port_postfix; + fp << "\t\t"; + if (true == use_explicit_port_map) { + fp << "." << std::string(lb.name) << module_output_port_postfix << "("; + } + fp << std::string(lb.name) << output_port_postfix; + if (true == use_explicit_port_map) { + fp << ")"; + } } /* Update the counter */ port_counter++; @@ -213,8 +230,6 @@ void print_verilog_random_testbench_instance(std::fstream& fp, fp << "\t);" << std::endl; } - - /******************************************************************** * Instanciate the input benchmark module *******************************************************************/ @@ -230,9 +245,15 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); + /* Do NOT use explicit port mapping here: + * VPR added a prefix of "out_" to the output ports of input benchmark + */ print_verilog_random_testbench_instance(fp, reference_verilog_top_name, std::string(BENCHMARK_INSTANCE_NAME), - std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks); + std::string(), + std::string(), + std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks, + false); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -389,10 +410,13 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------")); - + /* Always use explicit port mapping */ print_verilog_random_testbench_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)), std::string(FPGA_INSTANCE_NAME), - std::string(FPGA_PORT_POSTFIX), L_logical_blocks); + std::string(formal_verification_top_module_port_postfix), + std::string(formal_verification_top_module_port_postfix), + std::string(FPGA_PORT_POSTFIX), L_logical_blocks, + true); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); From 0ec465d4e195f6ba58cf479110a05f4940b1437c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Nov 2019 17:41:29 -0700 Subject: [PATCH 419/482] refactoring auto-check top Verilog testbench --- .../tasks/mcnc_big20/config/task.conf | 7 +- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 46 +++-- .../verilog/verilog_autocheck_top_testbench.c | 2 +- .../verilog_autocheck_top_testbench.cpp | 89 --------- .../verilog/verilog_autocheck_top_testbench.h | 23 +-- .../verilog_formal_random_top_testbench.cpp | 80 ++------ .../verilog/verilog_preconfig_top_module.cpp | 121 +----------- .../verilog/verilog_testbench_utils.cpp | 178 ++++++++++++++++++ .../verilog/verilog_testbench_utils.h | 35 ++++ .../fpga_x2p/verilog/verilog_top_testbench.c | 2 +- .../fpga_x2p/verilog/verilog_top_testbench.h | 28 ++- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 130 +++++++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 21 +++ 13 files changed, 447 insertions(+), 315 deletions(-) delete mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index ef31fe375..05961d06b 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -22,11 +22,12 @@ arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_til [BENCHMARKS] # Pass #bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif -# Fail, due to port does not match, i_15_ is dangling +# Pass, but port does not match, i_15_ is dangling #bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif -# To be tested +# Pass #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif -#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif +# To be tested #bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif #bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif #bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 4c1c4a223..73270144c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -152,14 +152,10 @@ void vpr_fpga_verilog(ModuleManager& module_manager, char* fm_dir_path = NULL; char* top_netlist_file = NULL; char* top_netlist_path = NULL; - char* top_testbench_file_name = NULL; - char* top_testbench_file_path = NULL; char* blif_testbench_file_name = NULL; char* blif_testbench_file_path = NULL; char* bitstream_file_name = NULL; char* bitstream_file_path = NULL; - char* autocheck_top_testbench_file_name = NULL; - char* autocheck_top_testbench_file_path = NULL; char* chomped_parent_dir = NULL; char* chomped_circuit_name = NULL; @@ -390,19 +386,31 @@ void vpr_fpga_verilog(ModuleManager& module_manager, my_free(bitstream_file_path); } - /* dump verilog testbench only for top-level: ONLY valid when bitstream is generated! */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench) { - top_testbench_file_name = my_strcat(chomped_circuit_name, top_testbench_verilog_file_postfix); - top_testbench_file_path = my_strcat(src_dir_path, top_testbench_file_name); - dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path, - src_dir_path, *(Arch.spice)); - /* Free */ - my_free(top_testbench_file_name); - my_free(top_testbench_file_path); - } - + /* Collect global ports from the circuit library + * TODO: move outside this function + */ std::vector global_ports = find_circuit_library_global_ports(Arch.spice->circuit_lib); + /* dump verilog testbench only for top-level: ONLY valid when bitstream is generated! */ + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench) { + std::string top_testbench_file_path = std::string(src_dir_path) + + std::string(chomped_circuit_name) + + std::string(top_testbench_verilog_file_postfix); + /* TODO: this is an old function, to be shadowed */ + dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path.c_str(), + src_dir_path, *(Arch.spice)); + /* TODO: new function: to be tested */ + print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, + sram_verilog_orgz_info->type, + Arch.spice->circuit_lib, global_ports, + L_logical_blocks, device_size, L_grids, L_blocks, + std::string(chomped_circuit_name), + std::string(top_testbench_file_path + std::string(".bak")), + std::string(src_dir_path), + std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), + Arch.spice->spice_params); + } + if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) { std::string formal_verification_top_netlist_file_path = std::string(src_dir_path) + std::string(chomped_circuit_name) @@ -446,10 +454,12 @@ void vpr_fpga_verilog(ModuleManager& module_manager, } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { - autocheck_top_testbench_file_name = my_strcat(chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix); - autocheck_top_testbench_file_path = my_strcat(src_dir_path, autocheck_top_testbench_file_name); + std::string autocheck_top_testbench_file_path = std::string(src_dir_path) + + std::string(chomped_circuit_name) + + std::string(autocheck_top_testbench_verilog_file_postfix); + /* TODO: this is an old function, to be shadowed */ dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, - autocheck_top_testbench_file_path, src_dir_path, + autocheck_top_testbench_file_path.c_str(), src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c index e3c234c08..2cb7bf089 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c @@ -348,7 +348,7 @@ void dump_verilog_top_auto_testbench_check(FILE* fp){ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, - char* top_netlist_name, + const char* top_netlist_name, char* verilog_dir_path, t_syn_verilog_opts fpga_verilog_opts, t_spice verilog) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp deleted file mode 100644 index 6f60b4d21..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to create - * an auto-check top-level testbench for a FPGA fabric - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" - -#include "fpga_x2p_utils.h" - -#include "verilog_writer_utils.h" - -#include "verilog_autocheck_top_testbench.h" - -/******************************************************************** - * The top-level function to generate a testbench, in order to verify: - * 1. Configuration phase of the FPGA fabric, where the bitstream is - * loaded to the configuration protocol of the FPGA fabric - * 2. Operating phase of the FPGA fabric, where input stimuli are - * fed to the I/Os of the FPGA fabric - *******************************************************************/ -void print_verilog_autocheck_top_testbench(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir, - const t_syn_verilog_opts& fpga_verilog_opts, - const t_spice_params& simulation_parameters) { - vpr_printf(TIO_MESSAGE_INFO, - "Writing Autocheck Testbench for FPGA Top-level Verilog netlist for %s...", - circuit_name.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Generate a brief description on the Verilog file*/ - std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; - print_verilog_file_header(fp, title); - - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Start of testbench */ - //dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); - - /* Call defined top-level module */ - //dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, - // circuit_name, is_explicit_mapping); - - /* Call defined benchmark */ - //dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name); - - /* Add stimuli for reset, set, clock and iopad signals */ - //dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog); - - /* Add output autocheck */ - //dump_verilog_top_auto_testbench_check(fp); - - /* Add Icarus requirement */ - //dump_verilog_timeout_and_vcd(fp, circuit_name , verilog, cur_sram_orgz_info); - - /* Testbench ends*/ - //fprintf(fp, "endmodule\n"); - - /* Close the file stream */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h index a34deb5da..4b9f09d62 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h @@ -1,33 +1,12 @@ #ifndef VERILOG_AUTOCHECK_TOP_TESTBENCH_H #define VERILOG_AUTOCHECK_TOP_TESTBENCH_H -#include -#include -#include "module_manager.h" -#include "bitstream_manager.h" -#include "circuit_library.h" void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, - char* top_netlist_name, + const char* top_netlist_name, char* verilog_dir_path, t_syn_verilog_opts fpga_verilog_opts, t_spice verilog); -/* -void print_verilog_autocheck_top_testbench(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir, - const t_syn_verilog_opts& fpga_verilog_opts, - const t_spice_params& simulation_parameters); -*/ - #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 9f08f33f6..78f14b07b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -24,6 +24,7 @@ /* Include FPGA Verilog headers*/ #include "verilog_global.h" #include "verilog_writer_utils.h" +#include "verilog_testbench_utils.h" #include "verilog_formal_random_top_testbench.h" /******************************************************************** @@ -175,61 +176,6 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * Instanciate the FPGA fabric module - *******************************************************************/ -static -void print_verilog_random_testbench_instance(std::fstream& fp, - const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& output_port_postfix, - const std::vector& L_logical_blocks, - const bool& use_explicit_port_map) { - - /* Validate the file stream */ - check_file_handler(fp); - - fp << "\t" << module_name << " " << instance_name << "(" << std::endl; - - size_t port_counter = 0; - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - /* The first port does not need a comma */ - if(0 < port_counter){ - fp << "," << std::endl; - } - /* Input port follows the logical block name while output port requires a special postfix */ - if (VPACK_INPAD == lb.type){ - fp << "\t\t"; - if (true == use_explicit_port_map) { - fp << "." << std::string(lb.name) << module_input_port_postfix << "("; - } - fp << std::string(lb.name); - if (true == use_explicit_port_map) { - fp << ")"; - } - } else { - VTR_ASSERT_SAFE(VPACK_OUTPAD == lb.type); - fp << "\t\t"; - if (true == use_explicit_port_map) { - fp << "." << std::string(lb.name) << module_output_port_postfix << "("; - } - fp << std::string(lb.name) << output_port_postfix; - if (true == use_explicit_port_map) { - fp << ")"; - } - } - /* Update the counter */ - port_counter++; - } - fp << "\t);" << std::endl; -} - /******************************************************************** * Instanciate the input benchmark module *******************************************************************/ @@ -248,12 +194,12 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, /* Do NOT use explicit port mapping here: * VPR added a prefix of "out_" to the output ports of input benchmark */ - print_verilog_random_testbench_instance(fp, reference_verilog_top_name, - std::string(BENCHMARK_INSTANCE_NAME), - std::string(), - std::string(), - std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks, - false); + print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name, + std::string(BENCHMARK_INSTANCE_NAME), + std::string(), + std::string(), + std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks, + false); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -411,12 +357,12 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------")); /* Always use explicit port mapping */ - print_verilog_random_testbench_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)), - std::string(FPGA_INSTANCE_NAME), - std::string(formal_verification_top_module_port_postfix), - std::string(formal_verification_top_module_port_postfix), - std::string(FPGA_PORT_POSTFIX), L_logical_blocks, - true); + print_verilog_testbench_benchmark_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)), + std::string(FPGA_INSTANCE_NAME), + std::string(formal_verification_top_module_port_postfix), + std::string(formal_verification_top_module_port_postfix), + std::string(FPGA_PORT_POSTFIX), L_logical_blocks, + true); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index 14ca60752..6f0b7b43e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -17,6 +17,7 @@ #include "verilog_global.h" #include "verilog_writer_utils.h" +#include "verilog_testbench_utils.h" #include "verilog_preconfig_top_module.h" /******************************************************************** @@ -89,31 +90,6 @@ void print_verilog_preconfig_top_module_internal_wires(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * Print an instance of the FPGA top-level module - *******************************************************************/ -static -void print_verilog_preconfig_top_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Include defined top-level module */ - print_verilog_comment(fp, std::string("----- FPGA top-level module to be capsulated -----")); - - /* Create an empty port-to-port name mapping, because we use default names */ - std::map port2port_name_map; - - /* Use explicit port mapping for a clean instanciation */ - print_verilog_module_instance(fp, module_manager, top_module, - std::string(formal_verification_top_module_uut_name), - port2port_name_map, true); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - /******************************************************************** * Connect global ports of FPGA top module to constants except: * 1. operating clock, which should be wired to the clock port of @@ -180,90 +156,6 @@ void print_verilog_preconfig_top_module_connect_global_ports(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * This function adds stimuli to I/Os of FPGA fabric - * 1. For mapped I/Os, this function will wire them to the input ports - * of the pre-configured FPGA top module - * 2. For unmapped I/Os, this function will assign a constant value - * by default - *******************************************************************/ -static -void print_verilog_preconfig_top_module_connect_ios(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks) { - /* Validate the file stream */ - check_file_handler(fp); - - /* In this function, we support only 1 type of I/Os */ - VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size()); - BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0]; - - /* Keep tracking which I/Os have been used */ - std::vector io_used(module_io_port.get_width(), false); - - /* See if this I/O should be wired to a benchmark input/output */ - /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs - * This brings convenience to checking functionality - */ - print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); - for (const t_logical_block& io_lb : L_logical_blocks) { - /* We only care I/O logical blocks !*/ - if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) { - continue; - } - - /* Find the index of the mapped GPIO in top-level FPGA fabric */ - size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks); - - /* Ensure that IO index is in range */ - BasicPort module_mapped_io_port = module_io_port; - /* Set the port pin index */ - VTR_ASSERT(io_index < module_mapped_io_port.get_width()); - module_mapped_io_port.set_width(io_index, io_index); - - /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 */ - BasicPort benchmark_io_port(std::string(std::string(io_lb.name)+ std::string(formal_verification_top_module_port_postfix)), 1); - - print_verilog_comment(fp, std::string("----- Blif Benchmark inout " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); - if (VPACK_INPAD == io_lb.type) { - print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); - } else { - VTR_ASSERT(VPACK_OUTPAD == io_lb.type); - print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); - } - - /* Mark this I/O has been used/wired */ - io_used[io_index] = true; - } - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Wire the unused iopads to a constant */ - print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----")); - for (size_t io_index = 0; io_index < io_used.size(); ++io_index) { - /* Bypass used iopads */ - if (true == io_used[io_index]) { - continue; - } - - /* Wire to a contant */ - BasicPort module_unused_io_port = module_io_port; - /* Set the port pin index */ - module_unused_io_port.set_width(io_index, io_index); - - std::vector default_values(module_unused_io_port.get_width(), verilog_default_signal_init_value); - print_verilog_wire_constant_values(fp, module_unused_io_port, default_values); - } - - /* Add an empty line as a splitter */ - fp << std::endl; -} - /******************************************************************** * Impose the bitstream on the configuration memories * This function uses 'assign' syntax to impost the bitstream at mem port @@ -514,7 +406,8 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, print_verilog_preconfig_top_module_internal_wires(fp, module_manager, top_module); /* Instanciate FPGA top-level module */ - print_verilog_preconfig_top_instance(fp, module_manager, top_module); + print_verilog_testbench_fpga_instance(fp, module_manager, top_module, + std::string(formal_verification_top_module_uut_name)); /* Find clock ports in benchmark */ std::vector benchmark_clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); @@ -525,9 +418,11 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, benchmark_clock_port_names); /* Connect I/Os to benchmark I/Os or constant driver */ - print_verilog_preconfig_top_module_connect_ios(fp, module_manager, top_module, - L_logical_blocks, device_size, L_grids, - L_blocks); + print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module, + L_logical_blocks, device_size, L_grids, + L_blocks, + std::string(formal_verification_top_module_port_postfix), + (size_t)verilog_default_signal_init_value); /* Assign FPGA internal SRAM/Memory ports to bitstream values */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp new file mode 100644 index 000000000..c1784ab26 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp @@ -0,0 +1,178 @@ +/******************************************************************** + * This file includes most utilized functions that are used to create + * Verilog testbenches + * + * Note: please do NOT use global variables in this file + * so that we can make it free to use anywhere + *******************************************************************/ +#include "vtr_assert.h" +#include "device_port.h" + +#include "fpga_x2p_utils.h" +#include "fpga_x2p_benchmark_utils.h" + +#include "verilog_writer_utils.h" +#include "verilog_testbench_utils.h" + +/******************************************************************** + * Print an instance of the FPGA top-level module + *******************************************************************/ +void print_verilog_testbench_fpga_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const std::string& top_instance_name) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Include defined top-level module */ + print_verilog_comment(fp, std::string("----- FPGA top-level module to be capsulated -----")); + + /* Create an empty port-to-port name mapping, because we use default names */ + std::map port2port_name_map; + + /* Use explicit port mapping for a clean instanciation */ + print_verilog_module_instance(fp, module_manager, top_module, + top_instance_name, + port2port_name_map, true); + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Instanciate the input benchmark module + *******************************************************************/ +void print_verilog_testbench_benchmark_instance(std::fstream& fp, + const std::string& module_name, + const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, + const std::string& output_port_postfix, + const std::vector& L_logical_blocks, + const bool& use_explicit_port_map) { + /* Validate the file stream */ + check_file_handler(fp); + + fp << "\t" << module_name << " " << instance_name << "(" << std::endl; + + size_t port_counter = 0; + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + /* The first port does not need a comma */ + if(0 < port_counter){ + fp << "," << std::endl; + } + /* Input port follows the logical block name while output port requires a special postfix */ + if (VPACK_INPAD == lb.type){ + fp << "\t\t"; + if (true == use_explicit_port_map) { + fp << "." << std::string(lb.name) << module_input_port_postfix << "("; + } + fp << std::string(lb.name); + if (true == use_explicit_port_map) { + fp << ")"; + } + } else { + VTR_ASSERT_SAFE(VPACK_OUTPAD == lb.type); + fp << "\t\t"; + if (true == use_explicit_port_map) { + fp << "." << std::string(lb.name) << module_output_port_postfix << "("; + } + fp << std::string(lb.name) << output_port_postfix; + if (true == use_explicit_port_map) { + fp << ")"; + } + } + /* Update the counter */ + port_counter++; + } + fp << "\t);" << std::endl; +} + +/******************************************************************** + * This function adds stimuli to I/Os of FPGA fabric + * 1. For mapped I/Os, this function will wire them to the input ports + * of the pre-configured FPGA top module + * 2. For unmapped I/Os, this function will assign a constant value + * by default + *******************************************************************/ +void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& io_port_name_postfix, + const size_t& unused_io_value) { + /* Validate the file stream */ + check_file_handler(fp); + + /* In this function, we support only 1 type of I/Os */ + VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size()); + BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0]; + + /* Keep tracking which I/Os have been used */ + std::vector io_used(module_io_port.get_width(), false); + + /* See if this I/O should be wired to a benchmark input/output */ + /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs + * This brings convenience to checking functionality + */ + print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); + for (const t_logical_block& io_lb : L_logical_blocks) { + /* We only care I/O logical blocks !*/ + if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) { + continue; + } + + /* Find the index of the mapped GPIO in top-level FPGA fabric */ + size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks); + + /* Ensure that IO index is in range */ + BasicPort module_mapped_io_port = module_io_port; + /* Set the port pin index */ + VTR_ASSERT(io_index < module_mapped_io_port.get_width()); + module_mapped_io_port.set_width(io_index, io_index); + + /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 */ + BasicPort benchmark_io_port(std::string(std::string(io_lb.name)+ io_port_name_postfix), 1); + + print_verilog_comment(fp, std::string("----- Blif Benchmark inout " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); + if (VPACK_INPAD == io_lb.type) { + print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); + } else { + VTR_ASSERT(VPACK_OUTPAD == io_lb.type); + print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); + } + + /* Mark this I/O has been used/wired */ + io_used[io_index] = true; + } + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Wire the unused iopads to a constant */ + print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----")); + for (size_t io_index = 0; io_index < io_used.size(); ++io_index) { + /* Bypass used iopads */ + if (true == io_used[io_index]) { + continue; + } + + /* Wire to a contant */ + BasicPort module_unused_io_port = module_io_port; + /* Set the port pin index */ + module_unused_io_port.set_width(io_index, io_index); + + std::vector default_values(module_unused_io_port.get_width(), unused_io_value); + print_verilog_wire_constant_values(fp, module_unused_io_port, default_values); + } + + /* Add an empty line as a splitter */ + fp << std::endl; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h new file mode 100644 index 000000000..ffa7411eb --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h @@ -0,0 +1,35 @@ +#ifndef VERILOG_TESTBENCH_UTILS_H +#define VERILOG_TESTBENCH_UTILS_H + +/* Include header files which are used in the function declaration */ +#include +#include +#include +#include "module_manager.h" +#include "vpr_types.h" + +void print_verilog_testbench_fpga_instance(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const std::string& top_instance_name); + +void print_verilog_testbench_benchmark_instance(std::fstream& fp, + const std::string& module_name, + const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, + const std::string& output_port_postfix, + const std::vector& L_logical_blocks, + const bool& use_explicit_port_map); + +void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& io_port_name_postfix, + const size_t& unused_io_value); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c index 6671ec6e4..b1c628c99 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c @@ -1329,7 +1329,7 @@ void dump_verilog_input_blif_testbench_stimuli(FILE* fp, */ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, - char* top_netlist_name, + const char* top_netlist_name, char* verilog_dir_path, t_spice verilog) { FILE* fp = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h index caf107479..c570b6293 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h @@ -1,3 +1,27 @@ +#ifndef VERILOG_TOP_TESTBENCH +#define VERILOG_TOP_TESTBENCH + +#include +#include +#include "module_manager.h" +#include "bitstream_manager.h" +#include "circuit_library.h" + +void print_verilog_top_testbench(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, + const e_sram_orgz& sram_orgz_type, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir, + const std::string& reference_benchmark_file, + const t_spice_params& simulation_parameters); void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head, enum e_dump_verilog_port_type dump_port_type); @@ -15,7 +39,7 @@ void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, - char* top_netlist_name, + const char* top_netlist_name, char* verilog_dir_path, t_spice verilog); @@ -23,3 +47,5 @@ void dump_verilog_input_blif_testbench(char* circuit_name, char* top_netlist_name, char* verilog_dir_path, t_spice verilog); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 69f774592..d2593138b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -6,6 +6,8 @@ #include #include #include +#include + #include "vtr_assert.h" /* Device-level header files */ @@ -1210,3 +1212,131 @@ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, print_verilog_wire_connection(fp, mux_sram_output, formal_verification_port, false); } +/******************************************************************** + * Print stimuli for a pulse generation + * + * |<--- pulse width --->| + * +------ flip_value + * | + * initial_value ----------------------+ + * + *******************************************************************/ +void print_verilog_pulse_stimuli(std::fstream& fp, + const BasicPort& port, + const size_t& initial_value, + const float& pulse_width, + const size_t& flip_value) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Config_done signal: indicate when configuration is finished */ + fp << "initial" << std::endl; + fp << "\tbegin" << std::endl; + fp << "\t"; + std::vector initial_values(port.get_width(), initial_value); + print_verilog_wire_constant_values(fp, port, initial_values); + + /* if flip_value is the same as initial value, we do not need to flip the signal ! */ + if (flip_value != initial_value) { + fp << "\t" << "#" << std::setprecision(2) << pulse_width; + std::vector port_flip_values(port.get_width(), flip_value); + print_verilog_wire_constant_values(fp, port, port_flip_values); + } + + fp << "\tend" << std::endl; + + /* Print an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print stimuli for a pulse generation + * This function supports multiple signal switching under different pulse width + * + * |<-- wait condition -->| + * |<--- pulse width --->| + * +------ flip_values + * | + * initial_value ------- ... --------------------------------+ + * + *******************************************************************/ +void print_verilog_pulse_stimuli(std::fstream& fp, + const BasicPort& port, + const size_t& initial_value, + const std::vector& pulse_widths, + const std::vector& flip_values, + const std::string& wait_condition) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Config_done signal: indicate when configuration is finished */ + fp << "initial" << std::endl; + fp << "\tbegin" << std::endl; + fp << "\t"; + std::vector initial_values(port.get_width(), initial_value); + print_verilog_wire_constant_values(fp, port, initial_values); + + /* Set a wait condition if specified */ + if (false == wait_condition.empty()) { + fp << "\twait(" << wait_condition << ")" << std::endl; + } + + /* Number of flip conditions and values should match */ + VTR_ASSERT(flip_values.size() == pulse_widths.size()); + for (size_t ipulse = 0; ipulse < pulse_widths.size(); ++ipulse) { + fp << "\t" << "#" << std::setprecision(2) << pulse_widths[ipulse]; + std::vector port_flip_value(port.get_width(), flip_values[ipulse]); + print_verilog_wire_constant_values(fp, port, port_flip_value); + } + + fp << "\tend" << std::endl; + + /* Print an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print stimuli for a clock signal + * This function can support if the clock signal should wait for a period + * of time and then start + * pulse width + * |<----->| + * +-------+ +-------+ + * | | | | + * initial_value --- ... ---+ +-------+ +------ ... + * |<--wait_condition-->| + * + *******************************************************************/ +void print_verilog_clock_stimuli(std::fstream& fp, + const BasicPort& port, + const size_t& initial_value, + const float& pulse_width, + const std::string& wait_condition) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Config_done signal: indicate when configuration is finished */ + fp << "initial" << std::endl; + fp << "\tbegin" << std::endl; + fp << "\t"; + std::vector initial_values(port.get_width(), initial_value); + print_verilog_wire_constant_values(fp, port, initial_values); + fp << "\tend" << std::endl; + fp << "always"; + + /* Set a wait condition if specified */ + if (true == wait_condition.empty()) { + fp << std::endl; + } else { + fp << " wait(" << wait_condition << ")" << std::endl; + } + + fp << "\tbegin" << std::endl; + fp << "\t\t" << "#" << std::setprecision(2) << pulse_width; + print_verilog_wire_connection(fp, port, port, true); + fp << "\tend" << std::endl; + + /* Print an empty line as splitter */ + fp << std::endl; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index d09e950de..a1d57615a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -6,6 +6,8 @@ #ifndef VERILOG_WRITER_UTILS_H #define VERILOG_WRITER_UTILS_H +#include +#include #include #include "verilog_global.h" #include "device_port.h" @@ -143,4 +145,23 @@ void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, const size_t& num_conf_bits, const BasicPort& fm_config_bus); +void print_verilog_pulse_stimuli(std::fstream& fp, + const BasicPort& port, + const size_t& initial_value, + const float& pulse_width, + const size_t& flip_value); + +void print_verilog_pulse_stimuli(std::fstream& fp, + const BasicPort& port, + const size_t& initial_value, + const std::vector& pulse_widths, + const std::vector& flip_values, + const std::string& wait_condition); + +void print_verilog_clock_stimuli(std::fstream& fp, + const BasicPort& port, + const size_t& initial_value, + const float& pulse_width, + const std::string& wait_condition); + #endif From 1fb29df1e2e1c8cc4b00146ea7cbed7b4f3b5ec8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Nov 2019 17:58:18 -0700 Subject: [PATCH 420/482] cleaning verilog file lines --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 73270144c..1037106b0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -399,16 +399,6 @@ void vpr_fpga_verilog(ModuleManager& module_manager, /* TODO: this is an old function, to be shadowed */ dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path.c_str(), src_dir_path, *(Arch.spice)); - /* TODO: new function: to be tested */ - print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, - sram_verilog_orgz_info->type, - Arch.spice->circuit_lib, global_ports, - L_logical_blocks, device_size, L_grids, L_blocks, - std::string(chomped_circuit_name), - std::string(top_testbench_file_path + std::string(".bak")), - std::string(src_dir_path), - std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), - Arch.spice->spice_params); } if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) { @@ -461,6 +451,16 @@ void vpr_fpga_verilog(ModuleManager& module_manager, dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, autocheck_top_testbench_file_path.c_str(), src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); + /* TODO: new function: to be tested */ + print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, + sram_verilog_orgz_info->type, + Arch.spice->circuit_lib, global_ports, + L_logical_blocks, device_size, L_grids, L_blocks, + std::string(chomped_circuit_name), + std::string(autocheck_top_testbench_file_path + std::string(".bak")), + std::string(src_dir_path), + std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), + Arch.spice->spice_params); } /* Output Modelsim Autodeck scripts */ From 3e9968d2f08c9c52492e39cde660ce3116faef95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Nov 2019 18:59:54 -0700 Subject: [PATCH 421/482] keep refactoring top-level testbench with auto-check features --- .../verilog_formal_random_top_testbench.cpp | 168 +--- .../verilog/verilog_testbench_utils.cpp | 158 +++- .../verilog/verilog_testbench_utils.h | 22 + .../verilog/verilog_top_testbench.cpp | 829 ++++++++++++++++++ 4 files changed, 1025 insertions(+), 152 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 78f14b07b..362992bc2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -41,22 +41,6 @@ constexpr char* ERROR_COUNTER = "nb_error"; constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start"; constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; -/******************************************************************** - * Generate the clock port name to be used in this testbench - * - * Restrictions: - * Assume this is a single clock benchmark - *******************************************************************/ -static -BasicPort generate_verilog_top_clock_port(const std::vector& clock_port_names) { - if (0 == clock_port_names.size()) { - return BasicPort(std::string(DEFAULT_CLOCK_NAME), 1); - } - - VTR_ASSERT(1 == clock_port_names.size()); - return BasicPort(clock_port_names[0], 1); -} - /******************************************************************** * Print the module ports for the Verilog testbench * using random vectors @@ -97,7 +81,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, * The clock is used for counting and synchronizing input stimulus */ if (0 == clock_port_names.size()) { - BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); print_verilog_comment(fp, std::string("----- Default clock port is added here since benchmark does not contain one -------")); fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, clock_port) << ";" << std::endl; } @@ -213,137 +197,6 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * Print Verilog codes to set up a timeout for the simulation - * and dump the waveform to VCD files - * - * Note that: these codes are tuned for Icarus simulator!!! - *******************************************************************/ -static -void print_verilog_timeout_and_vcd(std::fstream& fp, - const std::string& circuit_name, - const int& simulation_time) { - /* Validate the file stream */ - check_file_handler(fp); - - /* The following verilog codes are tuned for Icarus */ - print_verilog_preprocessing_flag(fp, std::string(icarus_simulator_flag)); - - print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------")); - - fp << "\tinitial begin" << std::endl; - fp << "\t\t$dumpfile(\"" << circuit_name << "_formal.vcd\");" << std::endl; - fp << "\t\t$dumpvars(1, " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ");" << std::endl; - fp << "\tend" << std::endl; - - /* Condition ends for the Icarus requirement */ - print_verilog_endif(fp); - - print_verilog_comment(fp, std::string("----- END Icarus requirement -------")); - - /* Add an empty line as splitter */ - fp << std::endl; - - BasicPort sim_start_port(std::string(FORMAL_TB_SIM_START_PORT_NAME), 1); - - fp << "initial begin" << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl; - fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; - fp << "\t$display(\"Simulation start\");" << std::endl; - print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); - fp << "\t#" << simulation_time << std::endl; - fp << "\tif(" << ERROR_COUNTER << " == 0) begin" << std::endl; - fp << "\t\t$display(\"Simulation Succeed\");" << std::endl; - fp << "\tend else begin" << std::endl; - fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << ERROR_COUNTER << ");" << std::endl; - fp << "\tend" << std::endl; - fp << "\t$finish;" << std::endl; - fp << "end" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print Verilog codes to check the equivalence of output vectors - * - * Restriction: this function only supports single clock benchmarks! - *******************************************************************/ -static -void print_verilog_top_random_testbench_check(std::fstream& fp, - const std::vector& L_logical_blocks, - const std::vector& clock_port_names) { - - /* Validate the file stream */ - check_file_handler(fp); - - /* Add output autocheck conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); - - print_verilog_comment(fp, std::string("----- Begin checking output vectors -------")); - - BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); - - print_verilog_comment(fp, std::string("----- Skip the first falling edge of clock, it is for initialization -------")); - - BasicPort sim_start_port(std::string(FORMAL_TB_SIM_START_PORT_NAME), 1); - - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, sim_start_port) << ";" << std::endl; - fp << std::endl; - - fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; - fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl; - fp << "\t\t"; - print_verilog_register_connection(fp, sim_start_port, sim_start_port, true); - fp << "\t\tend else begin" << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - if (VPACK_OUTPAD == lb.type){ - fp << "\t\t\tif(!(" << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX); - fp << " === " << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX); - fp << ") && !(" << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX); - fp << " === 1'bx)) begin" << std::endl; - fp << "\t\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << " <= 1'b1;" << std::endl; - fp << "\t\t\tend else begin" << std::endl; - fp << "\t\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << "<= 1'b0;" << std::endl; - fp << "\t\t\tend" << std::endl; - } - } - fp << "\t\tend" << std::endl; - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - fp << "\talways@(posedge " << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << ") begin" << std::endl; - fp << "\t\tif(" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << ") begin" << std::endl; - fp << "\t\t\t" << ERROR_COUNTER << " = " << ERROR_COUNTER << " + 1;" << std::endl; - fp << "\t\t\t$display(\"Mismatch on " << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX) << " at time = " << std::string("%t") << "\", $realtime);" << std::endl; - fp << "\t\tend" << std::endl; - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; - } - - /* Condition ends */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; -} - /******************************************************************** * Instanciate the FPGA fabric module *******************************************************************/ @@ -385,7 +238,7 @@ void print_verilog_top_random_stimuli(std::fstream& fp, fp << "\tinitial begin" << std::endl; /* Create clock stimuli */ - BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names); + BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; fp << "\t\twhile(1) begin" << std::endl; fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; @@ -540,7 +393,14 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, /* Add stimuli for reset, set, clock and iopad signals */ print_verilog_top_random_stimuli(fp, simulation_parameters, L_logical_blocks, clock_port_names); - print_verilog_top_random_testbench_check(fp, L_logical_blocks, clock_port_names); + print_verilog_testbench_check(fp, + std::string(autochecked_simulation_flag), + std::string(FORMAL_TB_SIM_START_PORT_NAME), + std::string(BENCHMARK_PORT_POSTFIX), + std::string(FPGA_PORT_POSTFIX), + std::string(CHECKFLAG_PORT_POSTFIX), + std::string(ERROR_COUNTER), + L_logical_blocks, clock_port_names, std::string(DEFAULT_CLOCK_NAME)); int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME, simulation_parameters.meas_params.sim_num_clock_cycle, @@ -548,7 +408,13 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, verilog_sim_timescale); /* Add Icarus requirement */ - print_verilog_timeout_and_vcd(fp, circuit_name, simulation_time); + print_verilog_timeout_and_vcd(fp, + std::string(icarus_simulator_flag), + std::string(circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)), + std::string(circuit_name + std::string("_formal.vcd")), + std::string(FORMAL_TB_SIM_START_PORT_NAME), + std::string(ERROR_COUNTER), + simulation_time); /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp index c1784ab26..d0b5e6b78 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp @@ -2,7 +2,7 @@ * This file includes most utilized functions that are used to create * Verilog testbenches * - * Note: please do NOT use global variables in this file + * Note: please try to avoid using global variables in this file * so that we can make it free to use anywhere *******************************************************************/ #include "vtr_assert.h" @@ -176,3 +176,159 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, /* Add an empty line as a splitter */ fp << std::endl; } + +/******************************************************************** + * Print Verilog codes to set up a timeout for the simulation + * and dump the waveform to VCD files + * + * Note that: these codes are tuned for Icarus simulator!!! + *******************************************************************/ +void print_verilog_timeout_and_vcd(std::fstream& fp, + const std::string& icarus_preprocessing_flag, + const std::string& module_name, + const std::string& vcd_fname, + const std::string& simulation_start_counter_name, + const std::string& error_counter_name, + const int& simulation_time) { + /* Validate the file stream */ + check_file_handler(fp); + + /* The following verilog codes are tuned for Icarus */ + print_verilog_preprocessing_flag(fp, icarus_preprocessing_flag); + + print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------")); + + fp << "\tinitial begin" << std::endl; + fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; + fp << "\t\t$dumpvars(1, " << module_name << ");" << std::endl; + fp << "\tend" << std::endl; + + /* Condition ends for the Icarus requirement */ + print_verilog_endif(fp); + + print_verilog_comment(fp, std::string("----- END Icarus requirement -------")); + + /* Add an empty line as splitter */ + fp << std::endl; + + BasicPort sim_start_port(simulation_start_counter_name, 1); + + fp << "initial begin" << std::endl; + fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl; + fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; + fp << "\t$display(\"Simulation start\");" << std::endl; + print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); + fp << "\t#" << simulation_time << std::endl; + fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl; + fp << "\t\t$display(\"Simulation Succeed\");" << std::endl; + fp << "\tend else begin" << std::endl; + fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl; + fp << "\tend" << std::endl; + fp << "\t$finish;" << std::endl; + fp << "end" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Generate the clock port name to be used in this testbench + * + * Restrictions: + * Assume this is a single clock benchmark + *******************************************************************/ +BasicPort generate_verilog_testbench_clock_port(const std::vector& clock_port_names, + const std::string& default_clock_name) { + if (0 == clock_port_names.size()) { + return BasicPort(default_clock_name, 1); + } + + VTR_ASSERT(1 == clock_port_names.size()); + return BasicPort(clock_port_names[0], 1); +} + +/******************************************************************** + * Print Verilog codes to check the equivalence of output vectors + * + * Restriction: this function only supports single clock benchmarks! + *******************************************************************/ +void print_verilog_testbench_check(std::fstream& fp, + const std::string& autochecked_preprocessing_flag, + const std::string& simulation_start_counter_name, + const std::string& benchmark_port_postfix, + const std::string& fpga_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& error_counter_name, + const std::vector& L_logical_blocks, + const std::vector& clock_port_names, + const std::string& default_clock_name) { + + /* Validate the file stream */ + check_file_handler(fp); + + /* Add output autocheck conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag); + + print_verilog_comment(fp, std::string("----- Begin checking output vectors -------")); + + BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); + + print_verilog_comment(fp, std::string("----- Skip the first falling edge of clock, it is for initialization -------")); + + BasicPort sim_start_port(simulation_start_counter_name, 1); + + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, sim_start_port) << ";" << std::endl; + fp << std::endl; + + fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; + fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl; + fp << "\t\t"; + print_verilog_register_connection(fp, sim_start_port, sim_start_port, true); + fp << "\t\tend else begin" << std::endl; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + if (VPACK_OUTPAD == lb.type){ + fp << "\t\t\tif(!(" << std::string(lb.name) << fpga_port_postfix; + fp << " === " << std::string(lb.name) << benchmark_port_postfix; + fp << ") && !(" << std::string(lb.name) << benchmark_port_postfix; + fp << " === 1'bx)) begin" << std::endl; + fp << "\t\t\t\t" << std::string(lb.name) << check_flag_port_postfix << " <= 1'b1;" << std::endl; + fp << "\t\t\tend else begin" << std::endl; + fp << "\t\t\t\t" << std::string(lb.name) << check_flag_port_postfix << "<= 1'b0;" << std::endl; + fp << "\t\t\tend" << std::endl; + } + } + fp << "\t\tend" << std::endl; + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + fp << "\talways@(posedge " << std::string(lb.name) << check_flag_port_postfix << ") begin" << std::endl; + fp << "\t\tif(" << std::string(lb.name) << check_flag_port_postfix << ") begin" << std::endl; + fp << "\t\t\t" << error_counter_name << " = " << error_counter_name << " + 1;" << std::endl; + fp << "\t\t\t$display(\"Mismatch on " << std::string(lb.name) << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl; + fp << "\t\tend" << std::endl; + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + } + + /* Condition ends */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h index ffa7411eb..b344bee5f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h @@ -32,4 +32,26 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, const std::string& io_port_name_postfix, const size_t& unused_io_value); +void print_verilog_timeout_and_vcd(std::fstream& fp, + const std::string& icarus_preprocessing_flag, + const std::string& module_name, + const std::string& vcd_fname, + const std::string& simulation_start_counter_name, + const std::string& error_counter_name, + const int& simulation_time); + +BasicPort generate_verilog_testbench_clock_port(const std::vector& clock_port_names, + const std::string& default_clock_name); + +void print_verilog_testbench_check(std::fstream& fp, + const std::string& autochecked_preprocessing_flag, + const std::string& simulation_start_counter_name, + const std::string& benchmark_port_postfix, + const std::string& fpga_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& error_counter_name, + const std::vector& L_logical_blocks, + const std::vector& clock_port_names, + const std::string& default_clock_name); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp new file mode 100644 index 000000000..febbf37a0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -0,0 +1,829 @@ +/******************************************************************** + * This file includes functions that are used to create + * an auto-check top-level testbench for a FPGA fabric + *******************************************************************/ +#include +#include +#include +#include + +#include "vtr_assert.h" +#include "device_port.h" +#include "util.h" + +#include "bitstream_manager_utils.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "simulation_utils.h" +#include "fpga_x2p_benchmark_utils.h" + +#include "verilog_global.h" +#include "verilog_writer_utils.h" +#include "verilog_testbench_utils.h" +#include "verilog_top_testbench.h" + +/******************************************************************** + * Local variables used only in this file + *******************************************************************/ +constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT"; +constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT"; +constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark"; +constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_verification"; + +constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag"; + +constexpr char* TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME = "cc_in"; +constexpr char* TOP_TESTBENCH_CONFIG_CHAIN_TAIL_PORT_NAME = "cc_out"; +constexpr char* TOP_TESTBENCH_CC_PROG_TASK_NAME = "prog_cycle_task"; + +constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start"; + +constexpr int TOP_TESTBENCH_MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; +constexpr char* TOP_TESTBENCH_ERROR_COUNTER = "nb_error"; + +/******************************************************************** + * Print local wires for configuration chain protocols + *******************************************************************/ +static +void print_verilog_top_testbench_config_chain_port(std::fstream& fp) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Print the head of configuraion-chains here */ + print_verilog_comment(fp, std::string("---- Configuration-chain head -----")); + BasicPort config_chain_head_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_head_port) << ";" << std::endl; + + /* Print the tail of configuration-chains here */ + print_verilog_comment(fp, std::string("---- Configuration-chain tail -----")); + BasicPort config_chain_tail_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_TAIL_PORT_NAME), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_tail_port) << ";" << std::endl; +} + +/******************************************************************** + * Print local wires for different types of configuration protocols + *******************************************************************/ +static +void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, + const e_sram_orgz& sram_orgz_type) { + switch(sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* TODO */ + break; + case SPICE_SRAM_SCAN_CHAIN: + print_verilog_top_testbench_config_chain_port(fp); + break; + case SPICE_SRAM_MEMORY_BANK: + /* TODO */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * Wire the global ports of FPGA fabric to local wires + *******************************************************************/ +static +void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----")); + + /* Connect global clock ports to operating or programming clock signal */ + for (const CircuitPortId& model_global_port : global_ports) { + if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(model_global_port)) { + continue; + } + /* Reach here, it means we have a global clock to deal with: + * 1. if the port is identified as a programming clock, + * connect it to the local wire of programming clock + * 2. if the port is identified as an operating clock + * connect it to the local wire of operating clock + */ + /* Find the module port */ + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + + BasicPort stimuli_clock_port; + if (true == circuit_lib.port_is_prog(model_global_port)) { + stimuli_clock_port.set_name(std::string(top_tb_prog_clock_port_name)); + stimuli_clock_port.set_width(1); + } else { + VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); + stimuli_clock_port.set_name(std::string(top_tb_op_clock_port_name)); + stimuli_clock_port.set_width(1); + } + /* Wire the port to the input stimuli: + * The wiring will be inverted if the default value of the global port is 1 + * Otherwise, the wiring will not be inverted! + */ + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_clock_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } + + /* Connect global configuration done ports to configuration done signal */ + for (const CircuitPortId& model_global_port : global_ports) { + /* Bypass clock signals, they have been processed */ + if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { + continue; + } + if (false == circuit_lib.port_is_config_enable(model_global_port)) { + continue; + } + /* Reach here, it means we have a configuration done port to deal with */ + /* Find the module port */ + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + + BasicPort stimuli_config_done_port(std::string(top_tb_config_done_port_name), 1); + /* Wire the port to the input stimuli: + * The wiring will be inverted if the default value of the global port is 1 + * Otherwise, the wiring will not be inverted! + */ + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_config_done_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } + + /* Connect global reset ports to operating or programming reset signal */ + for (const CircuitPortId& model_global_port : global_ports) { + /* Bypass clock signals, they have been processed */ + if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { + continue; + } + /* Bypass config_done signals, they have been processed */ + if (true == circuit_lib.port_is_config_enable(model_global_port)) { + continue; + } + + if (false == circuit_lib.port_is_reset(model_global_port)) { + continue; + } + /* Reach here, it means we have a reset port to deal with */ + /* Find the module port */ + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + + BasicPort stimuli_reset_port; + if (true == circuit_lib.port_is_prog(model_global_port)) { + stimuli_reset_port.set_name(std::string(top_tb_prog_reset_port_name)); + stimuli_reset_port.set_width(1); + } else { + VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); + stimuli_reset_port.set_name(std::string(top_tb_reset_port_name)); + stimuli_reset_port.set_width(1); + } + /* Wire the port to the input stimuli: + * The wiring will be inverted if the default value of the global port is 1 + * Otherwise, the wiring will not be inverted! + */ + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_reset_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } + + /* Connect global set ports to operating or programming set signal */ + for (const CircuitPortId& model_global_port : global_ports) { + /* Bypass clock signals, they have been processed */ + if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { + continue; + } + /* Bypass config_done signals, they have been processed */ + if (true == circuit_lib.port_is_config_enable(model_global_port)) { + continue; + } + + /* Bypass reset signals, they have been processed */ + if (true == circuit_lib.port_is_reset(model_global_port)) { + continue; + } + + if (false == circuit_lib.port_is_set(model_global_port)) { + continue; + } + /* Reach here, it means we have a set port to deal with */ + /* Find the module port */ + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + + BasicPort stimuli_set_port; + if (true == circuit_lib.port_is_prog(model_global_port)) { + stimuli_set_port.set_name(std::string(top_tb_prog_set_port_name)); + stimuli_set_port.set_width(1); + } else { + VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); + stimuli_set_port.set_name(std::string(top_tb_set_port_name)); + stimuli_set_port.set_width(1); + } + /* Wire the port to the input stimuli: + * The wiring will be inverted if the default value of the global port is 1 + * Otherwise, the wiring will not be inverted! + */ + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_set_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } + + /* For the rest of global ports, wire them to constant signals */ + for (const CircuitPortId& model_global_port : global_ports) { + /* Bypass clock signals, they have been processed */ + if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { + continue; + } + /* Bypass config_done signals, they have been processed */ + if (true == circuit_lib.port_is_config_enable(model_global_port)) { + continue; + } + + /* Bypass reset signals, they have been processed */ + if (true == circuit_lib.port_is_reset(model_global_port)) { + continue; + } + + /* Bypass set signals, they have been processed */ + if (true == circuit_lib.port_is_set(model_global_port)) { + continue; + } + + /* Reach here, it means we have a port to deal with */ + /* Find the module port and wire it to constant values */ + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + + BasicPort module_port = module_manager.module_port(top_module, module_global_port); + std::vector default_values(module_port.get_width(), circuit_lib.port_default_value(model_global_port)); + print_verilog_wire_constant_values(fp, module_port, default_values); + } + + print_verilog_comment(fp, std::string("----- End connecting global ports of FPGA fabric to stimuli -----")); +} + +/******************************************************************** + * This function prints the top testbench module declaration + * and internal wires/port declaration + * Ports can be classified in two categories: + * 1. General-purpose ports, which are datapath I/Os, clock signals + * for the FPGA fabric and input benchmark + * 2. Fabric-featured ports, which are required by configuration + * protocols. + * Due the difference in configuration protocols, the internal + * wires and ports will be different: + * (a) configuration-chain: we will have two ports, + * a head and a tail for the configuration chain, + * in addition to the regular ports. + * (b) memory-decoders: we will have a few ports to drive + * address lines for decoders and a bit input port to feed + * configuration bits + *******************************************************************/ +static +void print_verilog_top_testbench_ports(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const e_sram_orgz& sram_orgz_type, + const std::string& circuit_name){ + /* Validate the file stream */ + check_file_handler(fp); + + /* Print module definition */ + fp << "module " << circuit_name << std::string(modelsim_autocheck_testbench_module_postfix); + fp << " (" << std::endl; + + /* Print regular local wires: + * 1. global ports, i.e., reset, set and clock signals + * 2. datapath I/O signals + */ + /* Global ports of top-level module */ + print_verilog_comment(fp, std::string("----- Local wires for global ports of FPGA fabric -----")); + for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_REG, module_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Datapath I/Os of top-level module */ + print_verilog_comment(fp, std::string("----- Local wires for I/Os of FPGA fabric -----")); + for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) { + fp << generate_verilog_port(VERILOG_PORT_REG, module_port) << ";" << std::endl; + } + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Add local wires/registers that drive stimulus + * We create these general purpose ports here, + * and then wire them to the ports of FPGA fabric depending on their usage + */ + /* Configuration done port */ + BasicPort config_done_port(std::string(top_tb_config_done_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, config_done_port) << ";" << std::endl; + + /* Programming clock */ + BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_WIRE, prog_clock_port) << ";" << std::endl; + BasicPort prog_clock_register_port(std::string(std::string(top_tb_prog_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, prog_clock_register_port) << ";" << std::endl; + + /* Operating clock */ + BasicPort op_clock_port(std::string(top_tb_op_clock_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_WIRE, op_clock_port) << ";" << std::endl; + BasicPort op_clock_register_port(std::string(std::string(top_tb_op_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, op_clock_register_port) << ";" << std::endl; + + /* Programming set and reset */ + BasicPort prog_reset_port(std::string(top_tb_prog_reset_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, prog_reset_port) << ";" << std::endl; + BasicPort prog_set_port(std::string(top_tb_prog_set_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, prog_set_port) << ";" << std::endl; + + /* Global set and reset */ + BasicPort reset_port(std::string(top_tb_reset_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, reset_port) << ";" << std::endl; + BasicPort set_port(std::string(top_tb_set_port_name), 1); + fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; + + /* Configuration ports depend on the organization of SRAMs */ + print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type); + + /* Instantiate an integer to count the number of error and + * determine if the simulation succeed or failed + */ + print_verilog_comment(fp, std::string("----- Error counter -----")); + fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 0;" << std::endl; +} + +/******************************************************************** + * Instanciate the input benchmark module + *******************************************************************/ +static +void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, + const std::string& reference_verilog_top_name, + const std::vector& L_logical_blocks) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); + + print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); + + /* Do NOT use explicit port mapping here: + * VPR added a prefix of "out_" to the output ports of input benchmark + */ + print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name, + std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME), + std::string(), + std::string(), + std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), L_logical_blocks, + false); + + print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Condition ends for the benchmark instanciation */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print tasks (processes) in Verilog format, + * which is very useful in generating stimuli for each clock cycle + * This function is tuned for configuration-chain manipulation: + * During each programming cycle, we feed the input of scan chain with a memory bit + *******************************************************************/ +static +void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fstream& fp) { + + /* Validate the file stream */ + check_file_handler(fp); + + BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); + BasicPort cc_head_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME), 1); + BasicPort cc_head_value(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME) + std::string("_val"), 1); + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Feed the scan-chain input at each falling edge of programming clock + * It aims at avoid racing the programming clock (scan-chain data changes at the rising edge). + */ + print_verilog_comment(fp, std::string("----- Task: input values during a programming clock cycle -----")); + fp << "task " << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_INPUT, cc_head_value) << ";" << std::endl; + fp << "\tbegin" << std::endl; + fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; + fp << "\t\t"; + print_verilog_wire_connection(fp, cc_head_port, cc_head_value, false); + fp << "\tend" << std::endl; + fp << "endtask" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; +} + +/******************************************************************** + * Print tasks, which is very useful in generating stimuli for each clock cycle + *******************************************************************/ +static +void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp, + const e_sram_orgz& sram_orgz_type) { + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + break; + case SPICE_SRAM_SCAN_CHAIN: + print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp); + break; + case SPICE_SRAM_MEMORY_BANK: + /* TODO: + dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(cur_sram_orgz_info, fp); + */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * Print generatic input stimuli for the top testbench + * include: + * 1. configuration done signal + * 2. programming clock + * 3. operating clock + * 4. programming reset signal + * 5. programming set signal + * 6. reset signal + * 7. set signal + *******************************************************************/ +static +void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, + const size_t& num_config_clock_cycles, + const float& prog_clock_period, + const float& op_clock_period, + const float& timescale) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Number of clock cycles in configuration phase: " + std::to_string(num_config_clock_cycles) + " -----")); + + BasicPort config_done_port(std::string(top_tb_config_done_port_name), 1); + + BasicPort op_clock_port(std::string(top_tb_op_clock_port_name), 1); + BasicPort op_clock_register_port(std::string(std::string(top_tb_op_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); + + BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); + BasicPort prog_clock_register_port(std::string(std::string(top_tb_prog_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); + + BasicPort prog_reset_port(std::string(top_tb_prog_reset_port_name), 1); + BasicPort prog_set_port(std::string(top_tb_prog_set_port_name), 1); + + BasicPort reset_port(std::string(top_tb_reset_port_name), 1); + BasicPort set_port(std::string(top_tb_set_port_name), 1); + + /* Generate stimuli waveform for configuration done signals */ + print_verilog_comment(fp, "----- Begin configuration done signal generation -----"); + print_verilog_pulse_stimuli(fp, config_done_port, + 0, /* Initial value */ + num_config_clock_cycles * prog_clock_period / timescale, 1); + print_verilog_comment(fp, "----- End configuration done signal generation -----"); + fp << std::endl; + + /* Generate stimuli waveform for programming clock signals */ + print_verilog_comment(fp, "----- Begin raw programming clock signal generation -----"); + print_verilog_clock_stimuli(fp, prog_clock_register_port, + 0, /* Initial value */ + 0.5 * prog_clock_period / timescale, + std::string()); + print_verilog_comment(fp, "----- End raw programming clock signal generation -----"); + fp << std::endl; + + /* Programming clock should be only enabled during programming phase. + * When configuration is done (config_done is enabled), programming clock should be always zero. + */ + print_verilog_comment(fp, std::string("----- Actual programming clock is triggered only when " + config_done_port.get_name() + " and " + prog_reset_port.get_name() + " are disabled -----")); + fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port); + fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_register_port); + fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ")"; + fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_reset_port) << ")"; + fp << ";" << std::endl; + + fp << std::endl; + + /* Generate stimuli waveform for operating clock signals */ + print_verilog_comment(fp, "----- Begin raw operating clock signal generation -----"); + print_verilog_clock_stimuli(fp, op_clock_register_port, + 0, /* Initial value */ + 0.5 * op_clock_period / timescale, + std::string("~" + reset_port.get_name())); + print_verilog_comment(fp, "----- End raw operating clock signal generation -----"); + + /* Operation clock should be enabled after programming phase finishes. + * Before configuration is done (config_done is enabled), operation clock should be always zero. + */ + print_verilog_comment(fp, std::string("----- Actual operating clock is triggered only when " + config_done_port.get_name() + " is enabled -----")); + fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_port); + fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_register_port); + fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ")"; + fp << ";" << std::endl; + + fp << std::endl; + + /* Reset signal for configuration circuit: + * only enable during the first clock cycle in programming phase + */ + print_verilog_comment(fp, "----- Begin programming reset signal generation -----"); + print_verilog_pulse_stimuli(fp, prog_reset_port, + 1, /* Initial value */ + prog_clock_period / timescale, 0); + print_verilog_comment(fp, "----- End programming reset signal generation -----"); + + fp << std::endl; + + /* Programming set signal for configuration circuit : always disabled */ + print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----"); + print_verilog_pulse_stimuli(fp, prog_set_port, + 0, /* Initial value */ + prog_clock_period / timescale, 0); + print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----"); + + fp << std::endl; + + /* Operating reset signals: only enabled during the first clock cycle in operation phase */ + std::vector reset_pulse_widths; + reset_pulse_widths.push_back(op_clock_period / timescale); + reset_pulse_widths.push_back(2 * op_clock_period / timescale); + + std::vector reset_flip_values; + reset_flip_values.push_back(1); + reset_flip_values.push_back(0); + + print_verilog_comment(fp, "----- Begin operating reset signal generation -----"); + print_verilog_comment(fp, "----- Reset signal is enabled until the first clock cycle in operation phase -----"); + print_verilog_pulse_stimuli(fp, reset_port, + 1, + reset_pulse_widths, + reset_flip_values, + config_done_port.get_name()); + print_verilog_comment(fp, "----- End operating reset signal generation -----"); + + /* Operating set signal for configuration circuit : always disabled */ + print_verilog_comment(fp, "----- Begin operating set signal generation: always disabled -----"); + print_verilog_pulse_stimuli(fp, set_port, + 0, /* Initial value */ + op_clock_period / timescale, 0); + print_verilog_comment(fp, "----- End operating set signal generation: always disabled -----"); + + fp << std::endl; +} + +/******************************************************************** + * Print stimulus for a FPGA fabric with a configuration chain protocol + * where configuration bits are programming in serial (one by one) + * Task list: + * 1. For clock signal, we should create voltage waveforms for two types of clock signals: + * a. operation clock + * b. programming clock + * 2. For Set/Reset, we reset the chip after programming phase ends + * and before operation phase starts + * 3. For input/output clb nets (mapped to I/O grids), + * we should create voltage waveforms only after programming phase + *******************************************************************/ +static +void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Initial value should be the first configuration bits + * In the rest of programming cycles, + * configuration bits are fed at the falling edge of programming clock. + * We do not care the value of scan_chain head during the first programming cycle + * It is reset anyway + */ + BasicPort config_chain_head_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME), 1); + std::vector initial_values(config_chain_head_port.get_width(), 0); + + print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); + fp << "initial" << std::endl; + fp << "\tbegin" << std::endl; + print_verilog_comment(fp, "----- Configuration chain default input -----"); + fp << "\t"; + print_verilog_wire_constant_values(fp, config_chain_head_port, initial_values); + fp << std::endl; + + /* Attention: the configuration chain protcol requires the last configuration bit is fed first + * We will visit the fabric bitstream in a reverse way + */ + std::vector cc_bitstream = fabric_bitstream; + std::reverse(cc_bitstream.begin(), cc_bitstream.end()); + for (const ConfigBitId& bit_id : cc_bitstream) { + fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME); + fp << "(1'b" << (size_t)bitstream_manager.bit_value(bit_id) << ");" << std::endl; + } + fp << "\tend" << std::endl; + print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); +} + +/******************************************************************** + * Generate the stimuli for the top-level testbench + * The simulation consists of two phases: configuration phase and operation phase + * Configuration bits are loaded serially. + * This is actually what we do for a physical FPGA + *******************************************************************/ +static +void print_verilog_top_testbench_bitstream(std::fstream& fp, + const e_sram_orgz& sram_orgz_type, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream) { + /* Branch on the type of configuration protocol */ + switch (sram_orgz_type) { + case SPICE_SRAM_STANDALONE: + /* TODO */ + break; + case SPICE_SRAM_SCAN_CHAIN: + print_verilog_top_testbench_configuration_chain_bitstream(fp, bitstream_manager, fabric_bitstream); + break; + case SPICE_SRAM_MEMORY_BANK: + /* TODO */ + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid SRAM organization type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * The top-level function to generate a testbench, in order to verify: + * 1. Configuration phase of the FPGA fabric, where the bitstream is + * loaded to the configuration protocol of the FPGA fabric + * 2. Operating phase of the FPGA fabric, where input stimuli are + * fed to the I/Os of the FPGA fabric + * +----------+ + * | FPGA | +------------+ + * +----->| Fabric |------>| | + * | | | | | + * | +----------+ | | + * | | Output | + * random_input_vectors -----+ | Vector |---->Functional correct? + * | | Comparator | + * | +-----------+ | | + * | | Input | | | + * +----->| Benchmark |----->| | + * +-----------+ +------------+ + * + *******************************************************************/ +void print_verilog_top_testbench(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const std::vector& fabric_bitstream, + const e_sram_orgz& sram_orgz_type, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const std::string& circuit_name, + const std::string& verilog_fname, + const std::string& verilog_dir, + const std::string& reference_benchmark_file, + const t_spice_params& simulation_parameters) { + vpr_printf(TIO_MESSAGE_INFO, + "Writing Autocheck Testbench for FPGA Top-level Verilog netlist for %s...", + circuit_name.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Generate a brief description on the Verilog file*/ + std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; + print_verilog_file_header(fp, title); + + /* Print preprocessing flags and external netlists */ + print_verilog_include_defines_preproc_file(fp, verilog_dir); + + /* Include reference benchmark file */ + print_verilog_include_netlist(fp, reference_benchmark_file); + + /* Find the top_module */ + ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + + /* Start of testbench */ + //dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); + print_verilog_top_testbench_ports(fp, module_manager, top_module, + sram_orgz_type, circuit_name); + + /* Find the clock period */ + float prog_clock_period = (1./simulation_parameters.stimulate_params.prog_clock_freq); + float op_clock_period = (1./simulation_parameters.stimulate_params.op_clock_freq); + /* Estimate the number of configuration clock cycles + * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it. + * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle + */ + size_t num_config_clock_cycles = 1 + fabric_bitstream.size(); + + /* Generate stimuli for general control signals */ + print_verilog_top_testbench_generic_stimulus(fp, + num_config_clock_cycles, + prog_clock_period, + op_clock_period, + verilog_sim_timescale); + + /* Generate stimuli for global ports or connect them to existed signals */ + print_verilog_top_testbench_global_ports_stimuli(fp, + module_manager, top_module, + circuit_lib, global_ports); + + /* Instanciate FPGA top-level module */ + print_verilog_testbench_fpga_instance(fp, module_manager, top_module, + std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME)); + + /* Connect I/Os to benchmark I/Os or constant driver */ + print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module, + L_logical_blocks, device_size, L_grids, + L_blocks, + std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), + (size_t)verilog_default_signal_init_value); + + /* Instanciate input benchmark */ + print_verilog_top_testbench_benchmark_instance(fp, + circuit_name, + L_logical_blocks); + + /* Print tasks used for loading bitstreams */ + print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type); + + /* load bitstream to FPGA fabric in a configuration phase */ + print_verilog_top_testbench_bitstream(fp, sram_orgz_type, + bitstream_manager, fabric_bitstream); + + /* Preparation: find all the clock ports */ + std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); + + /* Add output autocheck */ + print_verilog_testbench_check(fp, + std::string(autochecked_simulation_flag), + std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), + std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), + std::string(TOP_TESTBENCH_ERROR_COUNTER), + L_logical_blocks, clock_port_names, std::string(top_tb_op_clock_port_name)); + + /* Find simulation time */ + float simulation_time = find_simulation_time_period(verilog_sim_timescale, + num_config_clock_cycles, + 1./simulation_parameters.stimulate_params.prog_clock_freq, + simulation_parameters.meas_params.sim_num_clock_cycle, + 1./simulation_parameters.stimulate_params.op_clock_freq); + + + /* Add Icarus requirement */ + print_verilog_timeout_and_vcd(fp, + std::string(icarus_simulator_flag), + std::string(circuit_name + std::string(modelsim_autocheck_testbench_module_postfix)), + std::string(circuit_name + std::string("_formal.vcd")), + std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), + std::string(TOP_TESTBENCH_ERROR_COUNTER), + (int)simulation_time); + + + /* Testbench ends*/ + print_verilog_module_end(fp, std::string(circuit_name) + std::string(modelsim_autocheck_testbench_module_postfix)); + + /* Close the file stream */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} From d7bbae76a4bd5360e8a177ccfc5cbdc5b7b6ace7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Nov 2019 20:20:14 -0700 Subject: [PATCH 422/482] adding stimuli to benchmark inputs in top-level testbench --- .../verilog_formal_random_top_testbench.cpp | 103 +----------------- .../verilog/verilog_testbench_utils.cpp | 103 ++++++++++++++++++ .../verilog/verilog_testbench_utils.h | 7 ++ .../verilog/verilog_top_testbench.cpp | 5 + 4 files changed, 118 insertions(+), 100 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 362992bc2..880c06ad5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -223,105 +223,6 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, fp << std::endl; } -/******************************************************************** - * Generate random stimulus for the input ports - *******************************************************************/ -static -void print_verilog_top_random_stimuli(std::fstream& fp, - const t_spice_params& simulation_parameters, - const std::vector& L_logical_blocks, - const std::vector& clock_port_names) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Initialization -------")); - - fp << "\tinitial begin" << std::endl; - /* Create clock stimuli */ - BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; - fp << "\t\twhile(1) begin" << std::endl; - fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; - fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); - fp << " <= !"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); - fp << ";" << std::endl; - fp << "\t\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - /* Clock ports will be initialized later */ - if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { - fp << "\t\t" << std::string(lb.name) << " <= 1'b0;" << std::endl; - } - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Set 0 to registers for checking flags */ - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + std::string(CHECKFLAG_PORT_POSTFIX)), 1); - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; - } - - fp << "\tend" << std::endl; - /* Finish initialization */ - - /* Add an empty line as splitter */ - fp << std::endl; - - // Not ready yet to determine if input is reset -/* - fprintf(fp, "//----- Reset Stimulis\n"); - fprintf(fp, " initial begin\n"); - fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " while(1) begin\n"); - fprintf(fp, " #%.3f\n", (rand() % 15) + 0.5); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " #%.3f\n", (rand() % 10000) + 200); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " end\n"); - fprintf(fp, " end\n\n"); -*/ - - print_verilog_comment(fp, std::string("----- Input Stimulus -------")); - fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - /* Clock ports will be initialized later */ - if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { - fp << "\t\t" << std::string(lb.name) << " <= $random;" << std::endl; - } - } - - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - /********************************************************************* * Top-level function in this file: * Create a Verilog testbench using random input vectors @@ -391,7 +292,9 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, L_logical_blocks); /* Add stimuli for reset, set, clock and iopad signals */ - print_verilog_top_random_stimuli(fp, simulation_parameters, L_logical_blocks, clock_port_names); + print_verilog_testbench_random_stimuli(fp, simulation_parameters, L_logical_blocks, + std::string(CHECKFLAG_PORT_POSTFIX), + clock_port_names, std::string(DEFAULT_CLOCK_NAME)); print_verilog_testbench_check(fp, std::string(autochecked_simulation_flag), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp index d0b5e6b78..926e247d5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp @@ -5,6 +5,8 @@ * Note: please try to avoid using global variables in this file * so that we can make it free to use anywhere *******************************************************************/ +#include + #include "vtr_assert.h" #include "device_port.h" @@ -332,3 +334,104 @@ void print_verilog_testbench_check(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; } + +/******************************************************************** + * Generate random stimulus for the input ports + *******************************************************************/ +void print_verilog_testbench_random_stimuli(std::fstream& fp, + const t_spice_params& simulation_parameters, + const std::vector& L_logical_blocks, + const std::string& check_flag_port_postfix, + const std::vector& clock_port_names, + const std::string& default_clock_name) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Initialization -------")); + + fp << "\tinitial begin" << std::endl; + /* Create clock stimuli */ + BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; + fp << "\t\twhile(1) begin" << std::endl; + fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; + fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << " <= !"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); + fp << ";" << std::endl; + fp << "\t\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + /* Clock ports will be initialized later */ + if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { + fp << "\t\t" << std::string(lb.name) << " <= 1'b0;" << std::endl; + } + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Set 0 to registers for checking flags */ + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + check_flag_port_postfix), 1); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; + } + + fp << "\tend" << std::endl; + /* Finish initialization */ + + /* Add an empty line as splitter */ + fp << std::endl; + + // Not ready yet to determine if input is reset +/* + fprintf(fp, "//----- Reset Stimulis\n"); + fprintf(fp, " initial begin\n"); + fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " while(1) begin\n"); + fprintf(fp, " #%.3f\n", (rand() % 15) + 0.5); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " #%.3f\n", (rand() % 10000) + 200); + fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); + fprintf(fp, " end\n"); + fprintf(fp, " end\n\n"); +*/ + + print_verilog_comment(fp, std::string("----- Input Stimulus -------")); + fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; + + for (const t_logical_block& lb : L_logical_blocks) { + /* Bypass non-I/O logical blocks ! */ + if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { + continue; + } + + /* Clock ports will be initialized later */ + if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { + fp << "\t\t" << std::string(lb.name) << " <= $random;" << std::endl; + } + } + + fp << "\tend" << std::endl; + + /* Add an empty line as splitter */ + fp << std::endl; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h index b344bee5f..729d28a27 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h @@ -54,4 +54,11 @@ void print_verilog_testbench_check(std::fstream& fp, const std::vector& clock_port_names, const std::string& default_clock_name); +void print_verilog_testbench_random_stimuli(std::fstream& fp, + const t_spice_params& simulation_parameters, + const std::vector& L_logical_blocks, + const std::string& check_flag_port_postfix, + const std::vector& clock_port_names, + const std::string& default_clock_name); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp index febbf37a0..8a13a7433 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -785,6 +785,11 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Preparation: find all the clock ports */ std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); + /* Add stimuli for reset, set, clock and iopad signals */ + print_verilog_testbench_random_stimuli(fp, simulation_parameters, L_logical_blocks, + std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), + clock_port_names, std::string(top_tb_op_clock_port_name)); + /* Add output autocheck */ print_verilog_testbench_check(fp, std::string(autochecked_simulation_flag), From 3274a49779e85f8c36c5db297fb7d521ab1e1337 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 4 Nov 2019 12:08:36 -0700 Subject: [PATCH 423/482] fine tuning top testbench and getting ready for testing --- .../verilog_formal_random_top_testbench.cpp | 10 +++- .../verilog/verilog_preconfig_top_module.cpp | 1 + .../verilog/verilog_testbench_utils.cpp | 56 ++++++++++++++----- .../verilog/verilog_testbench_utils.h | 11 ++-- .../verilog/verilog_top_testbench.cpp | 44 ++++++++++----- .../fpga_x2p/verilog/verilog_writer_utils.cpp | 38 +++++++++---- 6 files changed, 114 insertions(+), 46 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 880c06ad5..a18659eef 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -291,10 +291,14 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, /* Call defined benchmark */ print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, L_logical_blocks); + /* Find clock port to be used */ + BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); + /* Add stimuli for reset, set, clock and iopad signals */ - print_verilog_testbench_random_stimuli(fp, simulation_parameters, L_logical_blocks, - std::string(CHECKFLAG_PORT_POSTFIX), - clock_port_names, std::string(DEFAULT_CLOCK_NAME)); + print_verilog_testbench_clock_stimuli(fp, simulation_parameters, + clock_port); + print_verilog_testbench_random_stimuli(fp, L_logical_blocks, + std::string(CHECKFLAG_PORT_POSTFIX), clock_port); print_verilog_testbench_check(fp, std::string(autochecked_simulation_flag), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index 6f0b7b43e..9147cc053 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -422,6 +422,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, L_logical_blocks, device_size, L_grids, L_blocks, std::string(formal_verification_top_module_port_postfix), + std::string(formal_verification_top_module_port_postfix), (size_t)verilog_default_signal_init_value); /* Assign FPGA internal SRAM/Memory ports to bitstream values */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp index 926e247d5..7d519d543 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp @@ -108,7 +108,8 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, const vtr::Point& device_size, const std::vector>& L_grids, const std::vector& L_blocks, - const std::string& io_port_name_postfix, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, const size_t& unused_io_value) { /* Validate the file stream */ check_file_handler(fp); @@ -140,14 +141,21 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, VTR_ASSERT(io_index < module_mapped_io_port.get_width()); module_mapped_io_port.set_width(io_index, io_index); - /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 */ - BasicPort benchmark_io_port(std::string(std::string(io_lb.name)+ io_port_name_postfix), 1); - - print_verilog_comment(fp, std::string("----- Blif Benchmark inout " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); + /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 + * In addition, the input and output ports may have different postfix in naming + * due to verification context! Here, we give full customization on naming + */ + BasicPort benchmark_io_port; if (VPACK_INPAD == io_lb.type) { + benchmark_io_port.set_name(std::string(std::string(io_lb.name) + io_input_port_name_postfix)); + benchmark_io_port.set_width(1); + print_verilog_comment(fp, std::string("----- Blif Benchmark input " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); } else { VTR_ASSERT(VPACK_OUTPAD == io_lb.type); + benchmark_io_port.set_name(std::string(std::string(io_lb.name) + io_output_port_name_postfix)); + benchmark_io_port.set_width(1); + print_verilog_comment(fp, std::string("----- Blif Benchmark output " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); } @@ -336,33 +344,51 @@ void print_verilog_testbench_check(std::fstream& fp, } /******************************************************************** - * Generate random stimulus for the input ports + * Generate random stimulus for the clock port + * This function is designed to drive the clock port of a benchmark module + * If there is no clock port found, we will give a default clock name + * In such case, this clock will not be wired to the benchmark module + * but be only used as a synchronizer in verification *******************************************************************/ -void print_verilog_testbench_random_stimuli(std::fstream& fp, - const t_spice_params& simulation_parameters, - const std::vector& L_logical_blocks, - const std::string& check_flag_port_postfix, - const std::vector& clock_port_names, - const std::string& default_clock_name) { +void print_verilog_testbench_clock_stimuli(std::fstream& fp, + const t_spice_params& simulation_parameters, + const BasicPort& clock_port) { /* Validate the file stream */ check_file_handler(fp); - print_verilog_comment(fp, std::string("----- Initialization -------")); + print_verilog_comment(fp, std::string("----- Clock Initialization -------")); fp << "\tinitial begin" << std::endl; /* Create clock stimuli */ - BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; fp << "\t\twhile(1) begin" << std::endl; - fp << "\t\t\t#" << std::setprecision(2) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; + fp << "\t\t\t#" << std::setprecision(10) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); fp << " <= !"; fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); fp << ";" << std::endl; fp << "\t\tend" << std::endl; + fp << "\tend" << std::endl; + /* Add an empty line as splitter */ fp << std::endl; +} + +/******************************************************************** + * Generate random stimulus for the input ports (non-clock signals) + * For clock signals, please use print_verilog_testbench_clock_stimuli + *******************************************************************/ +void print_verilog_testbench_random_stimuli(std::fstream& fp, + const std::vector& L_logical_blocks, + const std::string& check_flag_port_postfix, + const BasicPort& clock_port) { + /* Validate the file stream */ + check_file_handler(fp); + + print_verilog_comment(fp, std::string("----- Input Initialization -------")); + + fp << "\tinitial begin" << std::endl; for (const t_logical_block& lb : L_logical_blocks) { /* Bypass non-I/O logical blocks ! */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h index 729d28a27..3c67f6eaa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h @@ -29,7 +29,8 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, const vtr::Point& device_size, const std::vector>& L_grids, const std::vector& L_blocks, - const std::string& io_port_name_postfix, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, const size_t& unused_io_value); void print_verilog_timeout_and_vcd(std::fstream& fp, @@ -54,11 +55,13 @@ void print_verilog_testbench_check(std::fstream& fp, const std::vector& clock_port_names, const std::string& default_clock_name); +void print_verilog_testbench_clock_stimuli(std::fstream& fp, + const t_spice_params& simulation_parameters, + const BasicPort& clock_port); + void print_verilog_testbench_random_stimuli(std::fstream& fp, - const t_spice_params& simulation_parameters, const std::vector& L_logical_blocks, const std::string& check_flag_port_postfix, - const std::vector& clock_port_names, - const std::string& default_clock_name); + const BasicPort& clock_port); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp index 8a13a7433..f10aecc3d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -29,12 +29,10 @@ constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT"; constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT"; constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark"; -constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_verification"; +constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga"; constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag"; -constexpr char* TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME = "cc_in"; -constexpr char* TOP_TESTBENCH_CONFIG_CHAIN_TAIL_PORT_NAME = "cc_out"; constexpr char* TOP_TESTBENCH_CC_PROG_TASK_NAME = "prog_cycle_task"; constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start"; @@ -52,13 +50,13 @@ void print_verilog_top_testbench_config_chain_port(std::fstream& fp) { /* Print the head of configuraion-chains here */ print_verilog_comment(fp, std::string("---- Configuration-chain head -----")); - BasicPort config_chain_head_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME), 1); + BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1); fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_head_port) << ";" << std::endl; /* Print the tail of configuration-chains here */ print_verilog_comment(fp, std::string("---- Configuration-chain tail -----")); - BasicPort config_chain_tail_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_TAIL_PORT_NAME), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_tail_port) << ";" << std::endl; + BasicPort config_chain_tail_port(generate_configuration_chain_tail_name(), 1); + fp << generate_verilog_port(VERILOG_PORT_WIRE, config_chain_tail_port) << ";" << std::endl; } /******************************************************************** @@ -411,8 +409,8 @@ void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fs check_file_handler(fp); BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); - BasicPort cc_head_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME), 1); - BasicPort cc_head_value(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME) + std::string("_val"), 1); + BasicPort cc_head_port(generate_configuration_chain_head_name(), 1); + BasicPort cc_head_value(generate_configuration_chain_head_name() + std::string("_val"), 1); /* Add an empty line as splitter */ fp << std::endl; @@ -425,8 +423,12 @@ void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fs fp << generate_verilog_port(VERILOG_PORT_INPUT, cc_head_value) << ";" << std::endl; fp << "\tbegin" << std::endl; fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; - fp << "\t\t"; - print_verilog_wire_connection(fp, cc_head_port, cc_head_value, false); + fp << "\t\t\t"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_port); + fp << " = "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_value); + fp << ";" << std::endl; + fp << "\tend" << std::endl; fp << "endtask" << std::endl; @@ -499,7 +501,7 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, print_verilog_comment(fp, "----- Begin configuration done signal generation -----"); print_verilog_pulse_stimuli(fp, config_done_port, 0, /* Initial value */ - num_config_clock_cycles * prog_clock_period / timescale, 1); + num_config_clock_cycles * prog_clock_period / timescale, 0); print_verilog_comment(fp, "----- End configuration done signal generation -----"); fp << std::endl; @@ -616,7 +618,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, * We do not care the value of scan_chain head during the first programming cycle * It is reset anyway */ - BasicPort config_chain_head_port(std::string(TOP_TESTBENCH_CONFIG_CHAIN_HEAD_PORT_NAME), 1); + BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1); std::vector initial_values(config_chain_head_port.get_width(), 0); print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); @@ -636,6 +638,19 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME); fp << "(1'b" << (size_t)bitstream_manager.bit_value(bit_id) << ");" << std::endl; } + + /* Raise the flag of configuration done when bitstream loading is complete */ + BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); + fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; + + BasicPort config_done_port(std::string(top_tb_config_done_port_name), 1); + fp << "\t\t\t"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); + fp << " <= "; + std::vector config_done_enable_values(config_done_port.get_width(), 1); + fp << generate_verilog_constant_values(config_done_enable_values); + fp << ";" << std::endl; + fp << "\tend" << std::endl; print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } @@ -767,6 +782,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module, L_logical_blocks, device_size, L_grids, L_blocks, + std::string(), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), (size_t)verilog_default_signal_init_value); @@ -786,9 +802,9 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); /* Add stimuli for reset, set, clock and iopad signals */ - print_verilog_testbench_random_stimuli(fp, simulation_parameters, L_logical_blocks, + print_verilog_testbench_random_stimuli(fp, L_logical_blocks, std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - clock_port_names, std::string(top_tb_op_clock_port_name)); + BasicPort(std::string(top_tb_op_clock_port_name), 1)); /* Add output autocheck */ print_verilog_testbench_check(fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index d2593138b..20f7c6dd0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -1234,13 +1234,17 @@ void print_verilog_pulse_stimuli(std::fstream& fp, fp << "\tbegin" << std::endl; fp << "\t"; std::vector initial_values(port.get_width(), initial_value); - print_verilog_wire_constant_values(fp, port, initial_values); + fp << "\t"; + fp << generate_verilog_port_constant_values(port, initial_values); + fp << ";" << std::endl; /* if flip_value is the same as initial value, we do not need to flip the signal ! */ if (flip_value != initial_value) { - fp << "\t" << "#" << std::setprecision(2) << pulse_width; + fp << "\t" << "#" << std::setprecision(10) << pulse_width; std::vector port_flip_values(port.get_width(), flip_value); - print_verilog_wire_constant_values(fp, port, port_flip_values); + fp << "\t"; + fp << generate_verilog_port_constant_values(port, port_flip_values); + fp << ";" << std::endl; } fp << "\tend" << std::endl; @@ -1274,7 +1278,9 @@ void print_verilog_pulse_stimuli(std::fstream& fp, fp << "\tbegin" << std::endl; fp << "\t"; std::vector initial_values(port.get_width(), initial_value); - print_verilog_wire_constant_values(fp, port, initial_values); + fp << "\t"; + fp << generate_verilog_port_constant_values(port, initial_values); + fp << ";" << std::endl; /* Set a wait condition if specified */ if (false == wait_condition.empty()) { @@ -1284,9 +1290,11 @@ void print_verilog_pulse_stimuli(std::fstream& fp, /* Number of flip conditions and values should match */ VTR_ASSERT(flip_values.size() == pulse_widths.size()); for (size_t ipulse = 0; ipulse < pulse_widths.size(); ++ipulse) { - fp << "\t" << "#" << std::setprecision(2) << pulse_widths[ipulse]; + fp << "\t" << "#" << std::setprecision(10) << pulse_widths[ipulse]; std::vector port_flip_value(port.get_width(), flip_values[ipulse]); - print_verilog_wire_constant_values(fp, port, port_flip_value); + fp << "\t"; + fp << generate_verilog_port_constant_values(port, port_flip_value); + fp << ";" << std::endl; } fp << "\tend" << std::endl; @@ -1318,9 +1326,12 @@ void print_verilog_clock_stimuli(std::fstream& fp, /* Config_done signal: indicate when configuration is finished */ fp << "initial" << std::endl; fp << "\tbegin" << std::endl; - fp << "\t"; + std::vector initial_values(port.get_width(), initial_value); - print_verilog_wire_constant_values(fp, port, initial_values); + fp << "\t\t"; + fp << generate_verilog_port_constant_values(port, initial_values); + fp << ";" << std::endl; + fp << "\tend" << std::endl; fp << "always"; @@ -1332,8 +1343,15 @@ void print_verilog_clock_stimuli(std::fstream& fp, } fp << "\tbegin" << std::endl; - fp << "\t\t" << "#" << std::setprecision(2) << pulse_width; - print_verilog_wire_connection(fp, port, port, true); + fp << "\t\t" << "#" << std::setprecision(10) << pulse_width; + + fp << "\t"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, port); + fp << " = "; + fp << "~"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, port); + fp << ";" << std::endl; + fp << "\tend" << std::endl; /* Print an empty line as splitter */ From 69bc858e62fca08730798a52fd6dedf436d45e28 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 4 Nov 2019 15:35:04 -0700 Subject: [PATCH 424/482] bring autocheck top testbench back to simulation deck, start testing --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 5 +- .../verilog_formal_random_top_testbench.cpp | 89 ++------------- .../verilog/verilog_include_netlists.c | 22 ++-- .../verilog/verilog_testbench_utils.cpp | 101 ++++++++++++++++++ .../verilog/verilog_testbench_utils.h | 7 ++ .../verilog/verilog_top_testbench.cpp | 25 +++-- .../fpga_x2p/verilog/verilog_top_testbench.h | 1 - 7 files changed, 150 insertions(+), 100 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 1037106b0..eb6eadcca 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -448,18 +448,19 @@ void vpr_fpga_verilog(ModuleManager& module_manager, + std::string(chomped_circuit_name) + std::string(autocheck_top_testbench_verilog_file_postfix); /* TODO: this is an old function, to be shadowed */ + /* dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, autocheck_top_testbench_file_path.c_str(), src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice)); + */ /* TODO: new function: to be tested */ print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, sram_verilog_orgz_info->type, Arch.spice->circuit_lib, global_ports, L_logical_blocks, device_size, L_grids, L_blocks, std::string(chomped_circuit_name), - std::string(autocheck_top_testbench_file_path + std::string(".bak")), + autocheck_top_testbench_file_path, std::string(src_dir_path), - std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), Arch.spice->spice_params); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index a18659eef..26b86d7a1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -61,94 +61,21 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, /* Print the declaration for the module */ fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl; - /* Instantiate register for inputs stimulis */ - print_verilog_comment(fp, std::string("----- Shared inputs -------")); - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_INPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort input_port(std::string(lb.name), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - /* Create a clock port if the benchmark does not have one! * The clock is used for counting and synchronizing input stimulus */ - if (0 == clock_port_names.size()) { - BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); - print_verilog_comment(fp, std::string("----- Default clock port is added here since benchmark does not contain one -------")); - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, clock_port) << ";" << std::endl; - } + BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); + print_verilog_comment(fp, std::string("----- Default clock port is added here since benchmark does not contain one -------")); + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, clock_port) << ";" << std::endl; /* Add an empty line as splitter */ fp << std::endl; - /* Instantiate wires for FPGA fabric outputs */ - print_verilog_comment(fp, std::string("----- FPGA fabric outputs -------")); - - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + std::string(FPGA_PORT_POSTFIX)), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Instantiate wire for benchmark output */ - print_verilog_comment(fp, std::string("----- Benchmark outputs -------")); - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + std::string(BENCHMARK_PORT_POSTFIX)), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Instantiate register for output comparison */ - print_verilog_comment(fp, std::string("----- Output vectors checking flags -------")); - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + std::string(CHECKFLAG_PORT_POSTFIX)), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; + print_verilog_testbench_shared_ports(fp, L_logical_blocks, + std::string(BENCHMARK_PORT_POSTFIX), + std::string(FPGA_PORT_POSTFIX), + std::string(CHECKFLAG_PORT_POSTFIX), + std::string(autochecked_simulation_flag)); /* Instantiate an integer to count the number of error * and determine if the simulation succeed or failed diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c index 19f6bbc50..1f2d6c3b3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c @@ -90,26 +90,36 @@ void write_include_netlists (char* src_dir_formatted, */ fprintf(fp, "`include \"%s%s\"\n", src_dir_formatted, generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix)).c_str()); + fprintf(fp, "\n"); + fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, + fprintf(fp, "\t`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, formal_verification_verilog_file_postfix); - fprintf(fp, " `ifdef %s\n", formal_simulation_flag); - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, + fprintf(fp, "\t`ifdef %s\n", formal_simulation_flag); + fprintf(fp, "\t\t`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, random_top_testbench_verilog_file_postfix); - fprintf(fp, " `endif\n"); - fprintf(fp, "`elsif %s\n", initial_simulation_flag); + fprintf(fp, " \t`endif\n"); + fprintf(fp, "`endif\n"); + + fprintf(fp, "\n"); + + fprintf(fp, "`ifdef %s\n", autochecked_simulation_flag); + /* TODO: bring these testbench onboard when it is ready fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, top_testbench_verilog_file_postfix); fprintf(fp, "`elsif %s\n", autochecked_simulation_flag); + */ fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix); - */ fprintf(fp, "`endif\n"); + + fprintf(fp, "\n"); + fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, default_rr_dir_name, routing_verilog_file_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp index 7d519d543..ee2a80ea6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp @@ -461,3 +461,104 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Print Verilog declaration of shared ports appear in testbenches + * which are + * 1. the shared input ports (registers) to drive both + * FPGA fabric and benchmark instance + * 2. the output ports (wires) for both FPGA fabric and benchmark instance + * 3. the checking flag ports to evaluate if outputs matches under the + * same input vectors + *******************************************************************/ +void print_verilog_testbench_shared_ports(std::fstream& fp, + const std::vector& L_logical_blocks, + const std::string& benchmark_output_port_postfix, + const std::string& fpga_output_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& autocheck_preprocessing_flag) { + /* Validate the file stream */ + check_file_handler(fp); + + + /* Instantiate register for inputs stimulis */ + print_verilog_comment(fp, std::string("----- Shared inputs -------")); + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_INPAD != lb.type) { + continue; + } + + /* Skip clocks because they are handled in another function */ + if (TRUE == lb.is_clock) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort input_port(std::string(lb.name), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate wires for FPGA fabric outputs */ + print_verilog_comment(fp, std::string("----- FPGA fabric outputs -------")); + + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + fpga_output_port_postfix), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ + print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag)); + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate wire for benchmark output */ + print_verilog_comment(fp, std::string("----- Benchmark outputs -------")); + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + benchmark_output_port_postfix), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Instantiate register for output comparison */ + print_verilog_comment(fp, std::string("----- Output vectors checking flags -------")); + for (const t_logical_block& lb : L_logical_blocks) { + /* We care only those logic blocks which are input I/Os */ + if (VPACK_OUTPAD != lb.type) { + continue; + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(std::string(lb.name) + check_flag_port_postfix), 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl; + } + + /* Add an empty line as splitter */ + fp << std::endl; + + /* Condition ends for the benchmark instanciation */ + print_verilog_endif(fp); + + /* Add an empty line as splitter */ + fp << std::endl; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h index 3c67f6eaa..0bbb1bc53 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h @@ -64,4 +64,11 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, const std::string& check_flag_port_postfix, const BasicPort& clock_port); +void print_verilog_testbench_shared_ports(std::fstream& fp, + const std::vector& L_logical_blocks, + const std::string& benchmark_output_port_postfix, + const std::string& fpga_output_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& autocheck_preprocessing_flag); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp index f10aecc3d..e5c89dd8f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -288,6 +288,7 @@ static void print_verilog_top_testbench_ports(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, + const std::vector& L_logical_blocks, const e_sram_orgz& sram_orgz_type, const std::string& circuit_name){ /* Validate the file stream */ @@ -295,7 +296,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Print module definition */ fp << "module " << circuit_name << std::string(modelsim_autocheck_testbench_module_postfix); - fp << " (" << std::endl; + fp << ";" << std::endl; /* Print regular local wires: * 1. global ports, i.e., reset, set and clock signals @@ -304,7 +305,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Global ports of top-level module */ print_verilog_comment(fp, std::string("----- Local wires for global ports of FPGA fabric -----")); for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_REG, module_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; } /* Add an empty line as a splitter */ fp << std::endl; @@ -312,7 +313,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Datapath I/Os of top-level module */ print_verilog_comment(fp, std::string("----- Local wires for I/Os of FPGA fabric -----")); for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_REG, module_port) << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; } /* Add an empty line as a splitter */ fp << std::endl; @@ -352,6 +353,12 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Configuration ports depend on the organization of SRAMs */ print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type); + print_verilog_testbench_shared_ports(fp, L_logical_blocks, + std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), + std::string(autochecked_simulation_flag)); + /* Instantiate an integer to count the number of error and * determine if the simulation succeed or failed */ @@ -625,8 +632,10 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, fp << "initial" << std::endl; fp << "\tbegin" << std::endl; print_verilog_comment(fp, "----- Configuration chain default input -----"); - fp << "\t"; - print_verilog_wire_constant_values(fp, config_chain_head_port, initial_values); + fp << "\t\t"; + fp << generate_verilog_port_constant_values(config_chain_head_port, initial_values); + fp << ";"; + fp << std::endl; /* Attention: the configuration chain protcol requires the last configuration bit is fed first @@ -718,7 +727,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const std::string& circuit_name, const std::string& verilog_fname, const std::string& verilog_dir, - const std::string& reference_benchmark_file, const t_spice_params& simulation_parameters) { vpr_printf(TIO_MESSAGE_INFO, "Writing Autocheck Testbench for FPGA Top-level Verilog netlist for %s...", @@ -741,16 +749,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Print preprocessing flags and external netlists */ print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Include reference benchmark file */ - print_verilog_include_netlist(fp, reference_benchmark_file); - /* Find the top_module */ ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); /* Start of testbench */ //dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); - print_verilog_top_testbench_ports(fp, module_manager, top_module, + print_verilog_top_testbench_ports(fp, module_manager, top_module, L_logical_blocks, sram_orgz_type, circuit_name); /* Find the clock period */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h index c570b6293..ab4a7f955 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h @@ -20,7 +20,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const std::string& circuit_name, const std::string& verilog_fname, const std::string& verilog_dir, - const std::string& reference_benchmark_file, const t_spice_params& simulation_parameters); void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head, From 5d507ae8ee87b1e144c937bb56bd6a0150313126 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 4 Nov 2019 18:05:50 -0700 Subject: [PATCH 425/482] bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!! --- .../fpga_x2p/base/module_manager_utils.cpp | 29 +++++++ .../SRC/fpga_x2p/base/module_manager_utils.h | 3 + .../module_builder/build_memory_modules.cpp | 62 +++++++++++---- .../verilog/verilog_include_netlists.c | 2 +- .../verilog/verilog_module_writer.cpp | 76 +++++++++++++++++++ .../verilog/verilog_top_testbench.cpp | 2 +- 6 files changed, 159 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index 7fe3bf2df..cabd6ba00 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -304,6 +304,35 @@ bool module_net_is_local_wire(const ModuleManager& module_manager, return true; } +/******************************************************************** + * Identify if a net is an output short connection inside a module: + * The short connection is defined as the direct connection + * between two outputs port of the module + * + * module + * +-----------------------------+ + * | + * src------>+--------------->|--->outputA + * | | + * | | + * +--------------->|--->outputB + * +-----------------------------+ + + *******************************************************************/ +bool module_net_include_output_short_connection(const ModuleManager& module_manager, + const ModuleId& module_id, const ModuleNetId& module_net) { + /* Check all the sink modules of the net */ + size_t contain_num_module_output = 0; + for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { + if (module_id == sink_module) { + contain_num_module_output++; + } + } + + /* If we have found more than 1 module outputs, it indicated output short connection! */ + return (1 < contain_num_module_output); +} + /******************************************************************** * Identify if a net is a local short connection inside a module: * The short connection is defined as the direct connection diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h index 5156e7af2..a44abbfc4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h @@ -50,6 +50,9 @@ void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, bool module_net_is_local_wire(const ModuleManager& module_manager, const ModuleId& module_id, const ModuleNetId& module_net); +bool module_net_include_output_short_connection(const ModuleManager& module_manager, + const ModuleId& module_id, const ModuleNetId& module_net); + bool module_net_include_local_short_connection(const ModuleManager& module_manager, const ModuleId& module_id, const ModuleNetId& module_net); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index 02dca4351..718b47cdb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -106,16 +106,20 @@ void add_module_output_nets_to_mem_modules(ModuleManager& module_manager, * j-th pin of output port of the i-th child module is wired to the j + i*W -th * pin of output port of the memory module, where W is the size of port * 3. It assumes fixed port name for output ports + * + * We cache the module nets that have been created because they will be used later ********************************************************************/ static -void add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, - const ModuleId& mem_module, - const std::string& mem_module_output_name, - const CircuitLibrary& circuit_lib, - const CircuitPortId& circuit_port, - const ModuleId& child_module, - const size_t& child_index, - const size_t& child_instance) { +std::vector add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, + const ModuleId& mem_module, + const std::string& mem_module_output_name, + const CircuitLibrary& circuit_lib, + const CircuitPortId& circuit_port, + const ModuleId& child_module, + const size_t& child_index, + const size_t& child_instance) { + std::vector module_nets; + /* Wire inputs of parent module to inputs of child modules */ ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(circuit_port)); ModulePortId sink_port_id = module_manager.find_module_port(mem_module, mem_module_output_name); @@ -128,7 +132,12 @@ void add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, /* Sink node of the input net is the input of sram module */ size_t sink_pin_id = child_index * circuit_lib.port_size(circuit_port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id]; module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id); + + /* Cache the nets */ + module_nets.push_back(net); } + + return module_nets; } /******************************************************************** @@ -155,9 +164,13 @@ void add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, static void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, const ModuleId& parent_module, + const std::vector& output_nets, const CircuitLibrary& circuit_lib, const CircuitPortId& model_input_port, const CircuitPortId& model_output_port) { + /* Counter for the nets */ + size_t net_counter = 0; + for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { ModuleId net_src_module_id; size_t net_src_instance_id; @@ -203,11 +216,21 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, /* Create a net for each pin */ for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { /* Create a net and add source and sink to it */ - ModuleNetId net = module_manager.create_module_net(parent_module); + ModuleNetId net; + if (0 == mem_index) { + net = module_manager.create_module_net(parent_module); + } else { + net = output_nets[net_counter]; + } /* Add net source */ module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); /* Add net sink */ module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + + /* Update net counter */ + if (0 < mem_index) { + net_counter++; + } } } @@ -237,12 +260,17 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, /* Create a net for each pin */ for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { /* Create a net and add source and sink to it */ - ModuleNetId net = module_manager.create_module_net(parent_module); + ModuleNetId net = output_nets[net_counter]; /* Add net source */ module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); /* Add net sink */ module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); + + /* Update net counter */ + net_counter++; } + + VTR_ASSERT(net_counter == output_nets.size()); } /********************************************************************* @@ -381,6 +409,9 @@ void build_memory_chain_module(ModuleManager& module_manager, /* Find the sram module in the module manager */ ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); + /* Cache the output nets for non-inverted data output */ + std::vector mem_output_nets; + /* Instanciate each submodule */ for (size_t i = 0; i < num_mems; ++i) { size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); @@ -396,13 +427,18 @@ void build_memory_chain_module(ModuleManager& module_manager, VTR_ASSERT( 1 == iport); port_name = generate_configuration_chain_inverted_data_out_name(); } - add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, port_name, circuit_lib, sram_output_ports[iport], - sram_mem_module, i, sram_mem_instance); + std::vector output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, + port_name, circuit_lib, sram_output_ports[iport], + sram_mem_module, i, sram_mem_instance); + /* Cache only for regular data outputs */ + if (0 == iport) { + mem_output_nets.insert(mem_output_nets.end(), output_nets.begin(), output_nets.end()); + } } } /* Build module nets to wire the configuration chain */ - add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, + add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, mem_output_nets, circuit_lib, sram_input_ports[0], sram_output_ports[0]); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c index 1f2d6c3b3..642ac9310 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c @@ -113,7 +113,7 @@ void write_include_netlists (char* src_dir_formatted, top_testbench_verilog_file_postfix); fprintf(fp, "`elsif %s\n", autochecked_simulation_flag); */ - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, + fprintf(fp, "\t`include \"%s%s%s\"\n", src_dir_formatted, chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix); fprintf(fp, "`endif\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index 2a495e91a..3a4bebcf8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -169,6 +169,50 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu return local_wires; } +/******************************************************************** + * Print a Verilog wire connection + * We search all the sinks of the net, + * if we find a module output, we try to find the next module output + * among the sinks of the net + * For each module output (except the first one), we print a wire connection + *******************************************************************/ +static +void print_verilog_module_output_short_connection(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const ModuleNetId& module_net) { + /* Ensure a valid file stream */ + check_file_handler(fp); + + bool first_port = true; + BasicPort src_port; + + /* We have found a module input, now check all the sink modules of the net */ + for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) { + ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink]; + if (module_id != sink_module) { + continue; + } + + /* Find the sink port and pin information */ + ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink]; + size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink]; + BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin); + + /* For the first module output, this is the source port, we do nothing and go to the next */ + if (true == first_port) { + src_port = sink_port; + /* Flip the flag */ + first_port = false; + continue; + } + + /* We need to print a wire connection here */ + print_verilog_wire_connection(fp, sink_port, src_port, false); + } +} + + /******************************************************************** * Print a Verilog wire connection * We search all the sources of the net, @@ -242,6 +286,36 @@ void print_verilog_module_local_short_connections(std::fstream& fp, } } +/******************************************************************** + * Print output short connections inside a Verilog module + * The output short connection is defined as the direct connection + * between two output ports of the module + * This type of connection is not covered when printing Verilog instances + * Therefore, they are covered in this function + * + * module + * +-----------------------------+ + * | + * src------>+--------------->|--->outputA + * | | + * | | + * +--------------->|--->outputB + * +-----------------------------+ + *******************************************************************/ +static +void print_verilog_module_output_short_connections(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id) { + /* Local wires come from the child modules */ + for (ModuleNetId module_net : module_manager.module_nets(module_id)) { + /* We only care the nets that indicate short connections */ + if (false == module_net_include_output_short_connection(module_manager, module_id, module_net)) { + continue; + } + print_verilog_module_output_short_connection(fp, module_manager, module_id, module_net); + } +} + /******************************************************************** * Write a Verilog instance to a file * This function will name the input and output connections to @@ -372,6 +446,8 @@ void write_verilog_module_to_file(std::fstream& fp, /* Print local connection (from module inputs to output! */ print_verilog_module_local_short_connections(fp, module_manager, module_id); + + print_verilog_module_output_short_connections(fp, module_manager, module_id); /* Print an empty line as splitter */ fp << std::endl; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp index e5c89dd8f..644df5246 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -547,7 +547,7 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, print_verilog_comment(fp, std::string("----- Actual operating clock is triggered only when " + config_done_port.get_name() + " is enabled -----")); fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_port); fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_register_port); - fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ")"; + fp << " & " << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); fp << ";" << std::endl; fp << std::endl; From ebab0e91ef7c0e058f2d6fc5a8afa1921035f524 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 4 Nov 2019 20:55:30 -0700 Subject: [PATCH 426/482] refactored include netlist writer --- .../libarchfpga/SRC/circuit_library_utils.cpp | 23 ++++ .../libarchfpga/SRC/circuit_library_utils.h | 2 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 9 ++ .../verilog_formal_random_top_testbench.cpp | 2 - .../verilog/verilog_include_netlists.cpp | 106 ++++++++++++++++++ .../verilog/verilog_include_netlists.h | 8 ++ .../fpga_x2p/verilog/verilog_writer_utils.cpp | 2 - 7 files changed, 148 insertions(+), 4 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp index cb7641b0a..7c3a24d94 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -240,3 +240,26 @@ std::vector find_circuit_library_global_ports(const CircuitLibrar return global_ports; } + +/******************************************************************** + * A generic function to find all the unique user-defined + * Verilog netlists in a circuit library + * Netlists with same names will be considered as one + *******************************************************************/ +std::vector find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib) { + std::vector netlists; + + for (const CircuitModelId& model : circuit_lib.models()) { + /* Skip empty netlist names */ + if (true == circuit_lib.model_verilog_netlist(model).empty()) { + continue; + } + /* See if the netlist name is already in the list */ + std::vector::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_verilog_netlist(model)); + if (it == netlists.end()) { + netlists.push_back(circuit_lib.model_verilog_netlist(model)); + } + } + + return netlists; +} diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h index c0c8251c7..056777c61 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h @@ -29,4 +29,6 @@ size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, std::vector find_circuit_library_global_ports(const CircuitLibrary& circuit_lib); +std::vector find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index eb6eadcca..6716cb1e4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -505,9 +505,18 @@ void vpr_fpga_verilog(ModuleManager& module_manager, sram_verilog_orgz_info->type); } + /* TODO: this is an old function, to be shadowed */ + /* write_include_netlists(src_dir_path, chomped_circuit_name, *(Arch.spice) ); + */ + + /* TODO: new function: to be tested */ + print_include_netlists(std::string(src_dir_path), + std::string(chomped_circuit_name), + std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), + Arch.spice->circuit_lib); vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules()); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp index 26b86d7a1..b52d41d43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp @@ -204,8 +204,6 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(defines_verilog_simulation_file_name))); - print_verilog_include_netlist(fp, std::string(fpga_verilog_opts.reference_verilog_benchmark_file)); - /* Preparation: find all the clock ports */ std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp new file mode 100644 index 000000000..814c97705 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp @@ -0,0 +1,106 @@ +/******************************************************************** + * This file includes functions that are used to generate Verilog files + * or code blocks, with a focus on + * `include user-defined or auto-generated netlists in Verilog format + *******************************************************************/ +#include + +#include "vtr_assert.h" + +#include "circuit_library_utils.h" + +#include "fpga_x2p_utils.h" +#include "fpga_x2p_naming.h" + +#include "verilog_writer_utils.h" +#include "verilog_include_netlists.h" + +/******************************************************************** + * Local constant variables + *******************************************************************/ +constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; + +/******************************************************************** + * Print a file that includes all the netlists that have been generated + * and user-defined. + * Some netlists are open to compile under specific preprocessing flags + *******************************************************************/ +void print_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& reference_benchmark_file, + const CircuitLibrary& circuit_lib) { + std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Print the title */ + print_verilog_file_header(fp, std::string("Netlist Summary")); + + /* Print preprocessing flags */ + print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----")); + print_verilog_include_netlist(fp, std::string(src_dir + std::string(defines_verilog_file_name))); + fp << std::endl; + + print_verilog_comment(fp, std::string("------ Include simulation defines -----")); + print_verilog_include_netlist(fp, src_dir + std::string(defines_verilog_simulation_file_name)); + fp << std::endl; + + /* Include all the user-defined netlists */ + for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) { + print_verilog_include_netlist(fp, user_defined_netlist); + } + + /* Include all the primitive modules */ + print_verilog_include_netlist(fp, src_dir + std::string(default_submodule_dir_name) + std::string(submodule_verilog_file_name)); + fp << std::endl; + + /* Include all the CLB, heterogeneous block modules */ + print_verilog_include_netlist(fp, src_dir + std::string(default_lb_dir_name) + std::string(logic_block_verilog_file_name)); + fp << std::endl; + + /* Include all the routing architecture modules */ + print_verilog_include_netlist(fp, src_dir + std::string(default_rr_dir_name) + std::string(routing_verilog_file_name)); + fp << std::endl; + + /* Include FPGA top module */ + print_verilog_include_netlist(fp, src_dir + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix))); + fp << std::endl; + + /* Include reference benchmark netlist only when auto-check flag is enabled */ + print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); + fp << "\t"; + print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); + print_verilog_endif(fp); + fp << std::endl; + + /* Include formal verification netlists only when formal verification flag is enable */ + print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); + fp << "\t"; + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(formal_verification_verilog_file_postfix)); + + /* Include formal verification testbench only when formal simulation flag is enabled */ + fp << "\t"; + print_verilog_preprocessing_flag(fp, std::string(formal_simulation_flag)); + fp << "\t\t"; + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(random_top_testbench_verilog_file_postfix)); + fp << "\t"; + print_verilog_endif(fp); + + print_verilog_endif(fp); + fp << std::endl; + + /* Include top-level testbench only when auto-check flag is enabled */ + print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); + fp << "\t"; + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(autocheck_top_testbench_verilog_file_postfix)); + print_verilog_endif(fp); + fp << std::endl; + + /* Close the file stream */ + fp.close(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h index 85659c56a..e0a92a2de 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h @@ -1,6 +1,14 @@ #ifndef VERILOG_INCLUDE_NETLISTS_H #define VERILOG_INCLUDE_NETLISTS_H +#include +#include "circuit_library.h" + +void print_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& reference_benchmark_file, + const CircuitLibrary& circuit_lib); + void write_include_netlists (char* src_dir_formatted, char* chomped_circuit_name, t_spice spice); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 20f7c6dd0..e210a68e0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -52,9 +52,7 @@ void print_verilog_include_netlist(std::fstream& fp, const std::string& netlist_name) { check_file_handler(fp); - fp << "//------ Include external netlist: " << netlist_name << " -----" << std::endl; fp << "`include \"" << netlist_name << "\"" << std::endl; - fp << "//------ End include external netlist: " << netlist_name << " -----" << std::endl; } /************************************************ From aaaf7a0d19f3ee6e409068928ad89042a8f533aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 4 Nov 2019 21:06:14 -0700 Subject: [PATCH 427/482] remove legacy codes in writing include netlists --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 9 +- .../verilog/verilog_include_netlists.c | 141 ------------------ .../verilog/verilog_include_netlists.h | 4 - 3 files changed, 1 insertion(+), 153 deletions(-) delete mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 6716cb1e4..a8f9c5020 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -505,14 +505,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager, sram_verilog_orgz_info->type); } - /* TODO: this is an old function, to be shadowed */ - /* - write_include_netlists(src_dir_path, - chomped_circuit_name, - *(Arch.spice) ); - */ - - /* TODO: new function: to be tested */ + /* Print a Verilog file including all the netlists that have been generated */ print_include_netlists(std::string(src_dir_path), std::string(chomped_circuit_name), std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c deleted file mode 100644 index 642ac9310..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.c +++ /dev/null @@ -1,141 +0,0 @@ -// Formality runsim -// Need to declare formality_script_name_postfix = "formality_script.tcl"; -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" - -/* Include FPGA-SPICE utils */ -#include "linkedlist.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_naming.h" - -/* Include verilog utils */ -#include "verilog_global.h" -#include "verilog_utils.h" - -#include "verilog_include_netlists.h" - -static -void include_netlists_include_user_defined_verilog_netlists(FILE* fp, - t_spice spice) { - int i; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid File Handler!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Include user-defined sub-circuit netlist */ - for (i = 0; i < spice.num_include_netlist; i++) { - if (0 == spice.include_netlists[i].included) { - assert(NULL != spice.include_netlists[i].path); - fprintf(fp, "`include \"%s\"\n", spice.include_netlists[i].path); - spice.include_netlists[i].included = 1; - } else { - assert(1 == spice.include_netlists[i].included); - } - } - - return; -} - -void write_include_netlists (char* src_dir_formatted, - char* chomped_circuit_name, - t_spice spice){ - - char* include_netlists_file_name = NULL; -/* int output_length; */ -/* int pos; */ - FILE* fp = NULL; - - include_netlists_file_name = my_strcat(src_dir_formatted, my_strcat(chomped_circuit_name, "_include_netlists.v")); - fp = fopen(include_netlists_file_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create formality script %s", - __FILE__, __LINE__, include_netlists_file_name); - exit(1); - } - - /* Print the title */ - dump_verilog_file_header(fp, "Netlists Summary"); - - /* Print preprocessing flags */ - verilog_include_defines_preproc_file(fp, src_dir_formatted); - verilog_include_simulation_defines_file(fp, src_dir_formatted); - - /* - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, - chomped_circuit_name, - verilog_top_postfix); - */ - fprintf(fp, "`include \"%s%s\"\n", src_dir_formatted, - generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix)).c_str()); - fprintf(fp, "\n"); - - fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); - fprintf(fp, "\t`include \"%s%s%s\"\n", src_dir_formatted, - chomped_circuit_name, - formal_verification_verilog_file_postfix); - fprintf(fp, "\t`ifdef %s\n", formal_simulation_flag); - fprintf(fp, "\t\t`include \"%s%s%s\"\n", src_dir_formatted, - chomped_circuit_name, - random_top_testbench_verilog_file_postfix); - fprintf(fp, " \t`endif\n"); - fprintf(fp, "`endif\n"); - - fprintf(fp, "\n"); - - fprintf(fp, "`ifdef %s\n", autochecked_simulation_flag); - - /* TODO: bring these testbench onboard when it is ready - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, - chomped_circuit_name, - top_testbench_verilog_file_postfix); - fprintf(fp, "`elsif %s\n", autochecked_simulation_flag); - */ - fprintf(fp, "\t`include \"%s%s%s\"\n", src_dir_formatted, - chomped_circuit_name, - autocheck_top_testbench_verilog_file_postfix); - fprintf(fp, "`endif\n"); - - fprintf(fp, "\n"); - - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, - default_rr_dir_name, - routing_verilog_file_name); - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, - default_lb_dir_name, - logic_block_verilog_file_name); - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, - default_submodule_dir_name, - submodule_verilog_file_name); - fprintf(fp, "`include \"%s%s%s\"\n", src_dir_formatted, - default_submodule_dir_name, - config_peripheral_verilog_file_name); - init_include_user_defined_verilog_netlists(spice); - include_netlists_include_user_defined_verilog_netlists(fp, spice); - - fclose(fp); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h index e0a92a2de..6b43a44d5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h @@ -9,8 +9,4 @@ void print_include_netlists(const std::string& src_dir, const std::string& reference_benchmark_file, const CircuitLibrary& circuit_lib); -void write_include_netlists (char* src_dir_formatted, - char* chomped_circuit_name, - t_spice spice); - #endif From 8ef9e994d80e5ffe6b439a9b6c1f5d42a2d67fd0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 12:18:23 -0700 Subject: [PATCH 428/482] rename source files to be what they are actually doing --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- ...og_include_netlists.cpp => verilog_auxiliary_netlists.cpp} | 2 +- ...erilog_include_netlists.h => verilog_auxiliary_netlists.h} | 4 ++-- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) rename vpr7_x2p/vpr/SRC/fpga_x2p/verilog/{verilog_include_netlists.cpp => verilog_auxiliary_netlists.cpp} (99%) rename vpr7_x2p/vpr/SRC/fpga_x2p/verilog/{verilog_include_netlists.h => verilog_auxiliary_netlists.h} (80%) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a8f9c5020..4df691a77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -61,7 +61,7 @@ #include "verilog_sdc.h" #include "verilog_formality_autodeck.h" #include "verilog_sdc_pb_types.h" -#include "verilog_include_netlists.h" +#include "verilog_auxiliary_netlists.h" #include "simulation_info_writer.h" #include "verilog_api.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp similarity index 99% rename from vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp index 814c97705..4e2597fdf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp @@ -13,7 +13,7 @@ #include "fpga_x2p_naming.h" #include "verilog_writer_utils.h" -#include "verilog_include_netlists.h" +#include "verilog_auxiliary_netlists.h" /******************************************************************** * Local constant variables diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h similarity index 80% rename from vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h index 6b43a44d5..fca4b1c26 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_include_netlists.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h @@ -1,5 +1,5 @@ -#ifndef VERILOG_INCLUDE_NETLISTS_H -#define VERILOG_INCLUDE_NETLISTS_H +#ifndef VERILOG_AUXILIARY_NETLISTS_H +#define VERILOG_AUXILIARY_NETLISTS_H #include #include "circuit_library.h" diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 0bdad0ee8..47b5fa027 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -283,7 +283,7 @@ void dump_verilog_defines_preproc(char* subckt_dir, if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create Verilog netlist %s", + "(FILE:%s,LINE[%d]) Failure in create Verilog netlist %s", __FILE__, __LINE__, fname); exit(1); } From 13f2d33d37462fa0df41879f8eef1a1db804deeb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 12:41:43 -0700 Subject: [PATCH 429/482] refactored fpga_define.v generation Please enter the commit message for your changes. Lines starting --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 +++ .../verilog/verilog_auxiliary_netlists.cpp | 49 +++++++++++++++++++ .../verilog/verilog_auxiliary_netlists.h | 4 ++ .../fpga_x2p/verilog/verilog_writer_utils.cpp | 11 +++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 4 ++ 5 files changed, 74 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 4df691a77..5df87ef8c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -264,8 +264,14 @@ void vpr_fpga_verilog(ModuleManager& module_manager, init_pb_types_num_iopads(); /* init_grids_num_mode_bits(); */ + /* TODO: This is the old function, which will be deprecated when refactoring is done */ + /* dump_verilog_defines_preproc(src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + */ + + print_verilog_preprocessing_flags_netlist(std::string(src_dir_path), + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); dump_verilog_simulation_preproc(src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp index 4e2597fdf..4607e1b16 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp @@ -12,6 +12,7 @@ #include "fpga_x2p_utils.h" #include "fpga_x2p_naming.h" +#include "verilog_global.h" #include "verilog_writer_utils.h" #include "verilog_auxiliary_netlists.h" @@ -104,3 +105,51 @@ void print_include_netlists(const std::string& src_dir, /* Close the file stream */ fp.close(); } + +/******************************************************************** + * Print a Verilog file containing preprocessing flags + * which are used enable/disable some features in FPGA Verilog modules + *******************************************************************/ +void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, + const t_syn_verilog_opts& fpga_verilog_opts) { + + std::string verilog_fname = src_dir + std::string(defines_verilog_file_name); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Print the title */ + print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules")); + + /* To enable timing */ + if (TRUE == fpga_verilog_opts.include_timing) { + print_verilog_define_flag(fp, std::string(verilog_timing_preproc_flag), 1); + fp << std::endl; + } + + /* To enable timing */ + if (TRUE == fpga_verilog_opts.include_signal_init) { + print_verilog_define_flag(fp, std::string(verilog_signal_init_preproc_flag), 1); + fp << std::endl; + } + + /* To enable formal verfication flag */ + if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) { + print_verilog_define_flag(fp, std::string(verilog_formal_verification_preproc_flag), 1); + fp << std::endl; + } + + /* To enable functional verfication with Icarus */ + if (TRUE == fpga_verilog_opts.include_icarus_simulator) { + print_verilog_define_flag(fp, std::string(icarus_simulator_flag), 1); + fp << std::endl; + } + + /* Close the file stream */ + fp.close(); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h index fca4b1c26..0d0037c3f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h @@ -3,10 +3,14 @@ #include #include "circuit_library.h" +#include "vpr_types.h" void print_include_netlists(const std::string& src_dir, const std::string& circuit_name, const std::string& reference_benchmark_file, const CircuitLibrary& circuit_lib); +void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, + const t_syn_verilog_opts& fpga_verilog_opts); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index e210a68e0..51ddd8107 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -55,6 +55,17 @@ void print_verilog_include_netlist(std::fstream& fp, fp << "`include \"" << netlist_name << "\"" << std::endl; } +/******************************************************************** + * Print Verilog codes to define a preprocessing flag + *******************************************************************/ +void print_verilog_define_flag(std::fstream& fp, + const std::string& flag_name, + const int& flag_value) { + check_file_handler(fp); + + fp << "`define " << flag_name << " " << flag_value << std::endl; +} + /************************************************ * Generate include files for a Verilog netlist ***********************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index a1d57615a..977ae037b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -26,6 +26,10 @@ void print_verilog_file_header(std::fstream& fp, void print_verilog_include_netlist(std::fstream& fp, const std::string& netlist_name); +void print_verilog_define_flag(std::fstream& fp, + const std::string& flag_name, + const int& flag_value); + void print_verilog_include_defines_preproc_file(std::fstream& fp, const std::string& verilog_dir); From 66047e4a451c0786f70ed6447f61bd8d19622b2a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 13:45:11 -0700 Subject: [PATCH 430/482] refactoring Verilog simulation flag generations --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 11 ++- .../verilog/verilog_auxiliary_netlists.cpp | 40 ++++++++++ .../verilog/verilog_auxiliary_netlists.h | 3 + .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 74 ------------------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 - 5 files changed, 48 insertions(+), 83 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 5df87ef8c..a92e8b598 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -264,17 +264,16 @@ void vpr_fpga_verilog(ModuleManager& module_manager, init_pb_types_num_iopads(); /* init_grids_num_mode_bits(); */ - /* TODO: This is the old function, which will be deprecated when refactoring is done */ - /* - dump_verilog_defines_preproc(src_dir_path, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); - */ - + /* Print Verilog files containing preprocessing flags */ print_verilog_preprocessing_flags_netlist(std::string(src_dir_path), vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + print_verilog_simulation_preprocessing_flags(std::string(src_dir_path), + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + /* dump_verilog_simulation_preproc(src_dir_path, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); + */ /* Generate primitive Verilog modules, which are corner stones of FPGA fabric * Note that this function MUST be called before Verilog generation of diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp index 4607e1b16..0aa47d8a6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp @@ -153,3 +153,43 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, fp.close(); } +/******************************************************************** + * Print a Verilog file containing simulation-related preprocessing flags + *******************************************************************/ +void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, + const t_syn_verilog_opts& fpga_verilog_opts) { + + std::string verilog_fname = src_dir + std::string(defines_verilog_simulation_file_name); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_handler(fp); + + /* Print the title */ + print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); + + /* To enable manualy checked simulation */ + if (TRUE == fpga_verilog_opts.print_top_testbench) { + print_verilog_define_flag(fp, std::string(initial_simulation_flag), 1); + fp << std::endl; + } + + /* To enable auto-checked simulation */ + if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) { + print_verilog_define_flag(fp, std::string(autochecked_simulation_flag), 1); + fp << std::endl; + } + + /* To enable pre-configured FPGA simulation */ + if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) { + print_verilog_define_flag(fp, std::string(formal_simulation_flag), 1); + fp << std::endl; + } + + + /* Close the file stream */ + fp.close(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h index 0d0037c3f..0a56690cd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h @@ -13,4 +13,7 @@ void print_include_netlists(const std::string& src_dir, void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, const t_syn_verilog_opts& fpga_verilog_opts); +void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, + const t_syn_verilog_opts& fpga_verilog_opts); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 47b5fa027..319c5447b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -164,45 +164,6 @@ void dump_verilog_file_header(FILE* fp, return; } -/* Dump preproc */ -void dump_verilog_preproc(FILE* fp, - t_syn_verilog_opts fpga_verilog_opts, - enum e_verilog_tb_type verilog_tb_type) { - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); - exit(1); - } - - /* To enable timing */ - if (TRUE == fpga_verilog_opts.include_timing) { - fprintf(fp, "`define %s 1\n", verilog_timing_preproc_flag); - fprintf(fp, "\n"); - } - - /* To enable timing */ - if (TRUE == fpga_verilog_opts.include_signal_init) { - fprintf(fp, "`define %s 1\n", verilog_signal_init_preproc_flag); - fprintf(fp, "\n"); - } - - /* To enable formal verfication flag */ - if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) { - fprintf(fp, "`define %s 1\n", - verilog_formal_verification_preproc_flag); // the flag to enable formal verification during compilation - fprintf(fp, "\n"); - } - - /* To enable functional verfication with Icarus */ - if (TRUE == fpga_verilog_opts.include_icarus_simulator) { - fprintf(fp, "`define %s 1\n", - icarus_simulator_flag); // the flag to enable formal verification during compilation - fprintf(fp, "\n"); - } - - return; -} - void dump_simulation_preproc(FILE* fp, t_syn_verilog_opts fpga_verilog_opts, enum e_verilog_tb_type verilog_tb_type) { @@ -268,41 +229,6 @@ void dump_verilog_simulation_preproc(char* subckt_dir, return; } -void dump_verilog_defines_preproc(char* subckt_dir, - t_syn_verilog_opts fpga_verilog_opts) { - /* Create a file handler */ - FILE* fp = NULL; - char* file_description = NULL; - char* fname = NULL; - - fname = my_strcat(subckt_dir, - defines_verilog_file_name); - - /* Create a file*/ - fp = fopen(fname, "w"); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Failure in create Verilog netlist %s", - __FILE__, __LINE__, fname); - exit(1); - } - - /* Generate the descriptions*/ - file_description = "Preproc Flags"; - dump_verilog_file_header(fp, file_description); - - /* Dump the defines preproc flags*/ - dump_verilog_preproc(fp, fpga_verilog_opts, VERILOG_TB_TOP); - - fclose(fp); - - /* Free */ - my_free(fname); - - return; -} - void verilog_include_defines_preproc_file(FILE* fp, char* verilog_dir) { char* temp_include_file_path = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 1fac4fff5..2e5ec3e9c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -22,9 +22,6 @@ void dump_simulation_preproc(FILE* fp, void dump_verilog_simulation_preproc(char* subckt_dir, t_syn_verilog_opts fpga_verilog_opts); -void dump_verilog_defines_preproc(char* subckt_dir, - t_syn_verilog_opts fpga_verilog_opts); - void verilog_include_simulation_defines_file(FILE* fp, char* formatted_verilog_dir); From 2fbb88d25b355a48a9d7398eb7e2d3826085b07d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 13:52:42 -0700 Subject: [PATCH 431/482] remove legacy codes --- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 65 ------------------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 10 --- 2 files changed, 75 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 319c5447b..7fe8eedbe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -164,71 +164,6 @@ void dump_verilog_file_header(FILE* fp, return; } -void dump_simulation_preproc(FILE* fp, - t_syn_verilog_opts fpga_verilog_opts, - enum e_verilog_tb_type verilog_tb_type) { - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); - exit(1); - } - - /* To enable manualy checked simulation */ - if (TRUE == fpga_verilog_opts.print_top_testbench) { - fprintf(fp, "`define %s 1\n", initial_simulation_flag); - fprintf(fp, "\n"); - } - - /* To enable auto-checked simulation */ - if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) { - fprintf(fp, "`define %s 1\n", autochecked_simulation_flag); - fprintf(fp, "\n"); - } - - /* To enable pre-configured FPGA simulation */ - if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) { - fprintf(fp, "`define %s 1\n", formal_simulation_flag); - fprintf(fp, "\n"); - } - - return; -} - -void dump_verilog_simulation_preproc(char* subckt_dir, - t_syn_verilog_opts fpga_verilog_opts) { - /* Create a file handler */ - FILE* fp = NULL; - char* file_description = NULL; - char* fname = NULL; - - fname = my_strcat(subckt_dir, - defines_verilog_simulation_file_name); - - /* Create a file*/ - fp = fopen(fname, "w"); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create Verilog netlist %s", - __FILE__, __LINE__, fname); - exit(1); - } - - /* Generate the descriptions*/ - file_description = "Simulation Flags"; - dump_verilog_file_header(fp, file_description); - - /* Dump the defines preproc flags*/ - dump_simulation_preproc(fp, fpga_verilog_opts, VERILOG_TB_TOP); - - fclose(fp); - - /* Free */ - my_free(fname); - - return; -} - void verilog_include_defines_preproc_file(FILE* fp, char* verilog_dir) { char* temp_include_file_path = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 2e5ec3e9c..30a4d8863 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -15,16 +15,6 @@ void dump_verilog_preproc(FILE* fp, t_syn_verilog_opts fpga_verilog_opts, enum e_verilog_tb_type verilog_tb_type); -void dump_simulation_preproc(FILE* fp, - t_syn_verilog_opts fpga_verilog_opts, - enum e_verilog_tb_type verilog_tb_type); - -void dump_verilog_simulation_preproc(char* subckt_dir, - t_syn_verilog_opts fpga_verilog_opts); - -void verilog_include_simulation_defines_file(FILE* fp, - char* formatted_verilog_dir); - void verilog_include_defines_preproc_file(FILE* fp, char* formatted_verilog_dir); From a308a13d7cb087f9041cdf9db7b411dfe56030d4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 15:41:59 -0700 Subject: [PATCH 432/482] use prefix instead of lib_name when building modules, then use lib_name for standard cell modules --- openfpga_flow/VerilogNetlists/ff.v | 8 +-- ...m_chain_FC_behavioral_verilog_template.xml | 4 +- .../k6_N10_sram_chain_HC_1IO_template.xml | 4 +- ...m_chain_HC_behavioral_verilog_template.xml | 4 +- ...0_sram_chain_HC_local_encoder_template.xml | 4 +- ...C_non_lut_intermediate_buffer_template.xml | 4 +- .../k6_N10_sram_chain_HC_template.xml | 4 +- ...k6_N10_sram_chain_HC_tileable_template.xml | 4 +- ...k6_N10_sram_chain_HC_tree_mux_template.xml | 4 +- .../libarchfpga/SRC/check_circuit_library.cpp | 12 ++-- .../libarchfpga/SRC/circuit_library_utils.cpp | 2 +- .../vpr/SRC/fpga_x2p/base/module_manager.cpp | 9 +++ .../vpr/SRC/fpga_x2p/base/module_manager.h | 2 + .../fpga_x2p/base/module_manager_utils.cpp | 14 ++--- .../module_builder/build_device_module.cpp | 9 +++ .../build_essential_modules.cpp | 39 ++++++++++++- .../module_builder/build_essential_modules.h | 3 + .../module_builder/build_grid_modules.cpp | 10 ++-- .../module_builder/build_lut_modules.cpp | 36 ++++++------ .../module_builder/build_memory_modules.cpp | 34 +++++------ .../module_builder/build_mux_modules.cpp | 56 +++++++++---------- .../module_builder/build_routing_modules.cpp | 8 +-- .../build_top_module_directs.cpp | 4 +- .../module_builder/build_wire_modules.cpp | 2 +- .../verilog/verilog_essential_gates.cpp | 36 ++++++------ .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 34 +++++------ .../verilog/verilog_preconfig_top_module.cpp | 2 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../verilog/verilog_top_testbench.cpp | 10 ++-- 29 files changed, 212 insertions(+), 152 deletions(-) diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v index bd556f936..f0097019e 100644 --- a/openfpga_flow/VerilogNetlists/ff.v +++ b/openfpga_flow/VerilogNetlists/ff.v @@ -76,9 +76,9 @@ endmodule //End Of Module static_dff //----------------------------------------------------- module sc_dff_compact ( /* Global ports go first */ -input pReset, // Reset input +input reset, // Reset input //input set, // set input -input prog_clk, // Clock Input +input clk, // Clock Input /* Local ports follow */ input D, // Data Input output Q, // Q output @@ -88,8 +88,8 @@ output Qb // Q output reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge prog_clk or posedge pReset /*or posedge set*/) -if (pReset) begin +always @ ( posedge clk or posedge reset /*or posedge set*/) +if (reset) begin q_reg <= 1'b0; //end else if (set) begin // q_reg <= 1'b1; diff --git a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml index 29badf323..0c932d704 100644 --- a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml +++ b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml @@ -321,12 +321,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml index fa32d4e41..9af75ba69 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml @@ -379,12 +379,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml index 4d26f30ad..f22464011 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml @@ -379,12 +379,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml index 48e1503c7..fd4ef33fb 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml @@ -379,12 +379,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml index ff9d23ac1..7b20e6ff9 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml @@ -377,12 +377,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index fa32d4e41..9af75ba69 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -379,12 +379,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml index ce1615d0b..4cea2b20c 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml @@ -379,12 +379,12 @@ - + - + diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml index c362da80c..078a876da 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml @@ -379,12 +379,12 @@ - + - + diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 5efabf0bc..bf70df367 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -410,7 +410,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { for (size_t iport = 0; iport < global_ports.size() - 1; ++iport) { for (size_t jport = iport + 1; jport < global_ports.size(); ++jport) { /* Bypass those do not share the same name */ - if (0 != circuit_lib.port_lib_name(global_ports[iport]).compare(circuit_lib.port_lib_name(global_ports[jport]))) { + if (0 != circuit_lib.port_prefix(global_ports[iport]).compare(circuit_lib.port_prefix(global_ports[jport]))) { continue; } @@ -421,7 +421,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { if (circuit_lib.port_default_value(global_ports[iport]) != circuit_lib.port_default_value(global_ports[jport])) { vpr_printf(TIO_MESSAGE_ERROR, "Global ports %s from circuit model %s and %s share the same name but have different dfefault values(%lu and %lu)!\n", - circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.port_prefix(global_ports[iport]).c_str(), circuit_lib.model_name(iport_parent_model).c_str(), circuit_lib.model_name(jport_parent_model).c_str(), circuit_lib.port_default_value(global_ports[iport]), @@ -433,7 +433,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { if (circuit_lib.port_is_reset(global_ports[iport]) != circuit_lib.port_is_reset(global_ports[jport])) { vpr_printf(TIO_MESSAGE_ERROR, "Global ports %s from circuit model %s and %s share the same name but have different is_reset attributes!\n", - circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.port_prefix(global_ports[iport]).c_str(), circuit_lib.model_name(iport_parent_model).c_str(), circuit_lib.model_name(jport_parent_model).c_str() ); @@ -442,7 +442,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { if (circuit_lib.port_is_set(global_ports[iport]) != circuit_lib.port_is_set(global_ports[jport])) { vpr_printf(TIO_MESSAGE_ERROR, "Global ports %s from circuit model %s and %s share the same name but have different is_set attributes!\n", - circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.port_prefix(global_ports[iport]).c_str(), circuit_lib.model_name(iport_parent_model).c_str(), circuit_lib.model_name(jport_parent_model).c_str() ); @@ -451,7 +451,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { if (circuit_lib.port_is_config_enable(global_ports[iport]) != circuit_lib.port_is_config_enable(global_ports[jport])) { vpr_printf(TIO_MESSAGE_ERROR, "Global ports %s from circuit model %s and %s share the same name but have different is_config_enable attributes!\n", - circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.port_prefix(global_ports[iport]).c_str(), circuit_lib.model_name(iport_parent_model).c_str(), circuit_lib.model_name(jport_parent_model).c_str() ); @@ -460,7 +460,7 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { if (circuit_lib.port_is_prog(global_ports[iport]) != circuit_lib.port_is_prog(global_ports[jport])) { vpr_printf(TIO_MESSAGE_ERROR, "Global ports %s from circuit model %s and %s share the same name but have different is_prog attributes!\n", - circuit_lib.port_lib_name(global_ports[iport]).c_str(), + circuit_lib.port_prefix(global_ports[iport]).c_str(), circuit_lib.model_name(iport_parent_model).c_str(), circuit_lib.model_name(jport_parent_model).c_str() ); diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp index 7c3a24d94..22145b38f 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp @@ -226,7 +226,7 @@ std::vector find_circuit_library_global_ports(const CircuitLibrar /* Check if a same port with the same name has already been in the list */ bool add_to_list = true; for (const auto& global_port : global_ports) { - if (0 == circuit_lib.port_lib_name(port).compare(circuit_lib.port_lib_name(global_port))) { + if (0 == circuit_lib.port_prefix(port).compare(circuit_lib.port_prefix(global_port))) { /* Same name, skip list update */ add_to_list = false; break; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp index bdd636071..3b6b0a6f0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp @@ -462,6 +462,15 @@ ModulePortId ModuleManager::add_port(const ModuleId& module, return port; } +/* Set a name for a module port */ +void ModuleManager::set_module_port_name(const ModuleId& module, const ModulePortId& module_port, + const std::string& port_name) { + /* Validate the id of module port */ + VTR_ASSERT( valid_module_port_id(module, module_port) ); + + ports_[module][module_port].set_name(port_name); +} + /* Set a name for a module */ void ModuleManager::set_module_name(const ModuleId& module, const std::string& name) { /* Validate the id of module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h index 1efcd0d24..ac7096fd3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h @@ -127,6 +127,8 @@ class ModuleManager { /* Add a port to a module */ ModulePortId add_port(const ModuleId& module, const BasicPort& port_info, const enum e_module_port_type& port_type); + /* Set a name for a module port */ + void set_module_port_name(const ModuleId& module, const ModulePortId& module_port, const std::string& port_name); /* Set a name for a module */ void set_module_name(const ModuleId& module, const std::string& name); /* Set a port to be a wire */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp index cabd6ba00..f8c79a238 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp @@ -36,7 +36,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Add ports */ /* Find global ports and add one by one */ for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) { - BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); } @@ -56,7 +56,7 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, /* Input ports (ignore all the global ports when searching the circuit_lib */ for (const auto& kv : port_type2type_map) { for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { - BasicPort port_info(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(module, port_info, kv.second); } } @@ -397,7 +397,7 @@ void add_primitive_pb_type_module_nets(ModuleManager& module_manager, BasicPort src_port = module_manager.module_port(pb_type_module, src_module_port_id); /* Get the des module port id */ - std::string des_module_port_name = circuit_lib.port_lib_name(pb_type_port->circuit_model_port); + std::string des_module_port_name = circuit_lib.port_prefix(pb_type_port->circuit_model_port); ModulePortId des_module_port_id = module_manager.find_module_port(child_module, des_module_port_name); VTR_ASSERT(ModulePortId::INVALID() != des_module_port_id); BasicPort des_port = module_manager.module_port(child_module, des_module_port_id); @@ -558,11 +558,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man std::vector logic_model_sram_port_names; /* Regular sram port goes first */ for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { - logic_model_sram_port_names.push_back(circuit_lib.port_lib_name(regular_sram_port)); + logic_model_sram_port_names.push_back(circuit_lib.port_prefix(regular_sram_port)); } /* Mode-select sram port goes first */ for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { - logic_model_sram_port_names.push_back(circuit_lib.port_lib_name(mode_select_sram_port)); + logic_model_sram_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port)); } /* Find the port ids in the memory */ std::vector logic_module_sram_port_ids; @@ -594,11 +594,11 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man std::vector logic_model_sramb_port_names; /* Regular sram port goes first */ for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { - logic_model_sramb_port_names.push_back(circuit_lib.port_lib_name(regular_sram_port) + std::string("_inv")); + logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string("_inv")); } /* Mode-select sram port goes first */ for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { - logic_model_sramb_port_names.push_back(circuit_lib.port_lib_name(mode_select_sram_port) + std::string("_inv")); + logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string("_inv")); } /* Find the port ids in the memory */ std::vector logic_module_sramb_port_ids; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp index 49b904257..772ee8f57 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp @@ -132,6 +132,15 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); + /* Now a critical correction has to be done! + * In the module construction, we always use prefix of ports because they are binded + * to the ports in architecture description (logic blocks etc.) + * To interface with standard cell, we should + * rename the ports of primitive modules using lib_name instead of prefix + * (which have no children and are probably linked to a standard cell!) + */ + rename_primitive_module_port_names(module_manager, arch.spice->circuit_lib); + /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index a474ab26c..ca2b17a1b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -232,7 +232,7 @@ void build_user_defined_modules(ModuleManager& module_manager, VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); } @@ -288,3 +288,40 @@ void build_constant_generator_modules(ModuleManager& module_manager) { "took %.2g seconds\n", run_time_sec); } + +/********************************************************************* + * This function will rename the ports of primitive modules + * using lib_name instead of prefix + * Primitive modules are defined as those modules in the module manager + * which have user defined netlists + ********************************************************************/ +void rename_primitive_module_port_names(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib) { + for (const CircuitModelId& model : circuit_lib.models()) { + /* We only care about user-defined models */ + if ( (true == circuit_lib.model_verilog_netlist(model).empty()) + && (true == circuit_lib.model_verilog_netlist(model).empty()) ) { + continue; + } + /* Skip Routing channel wire models because they need a different name. Do it later */ + if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { + continue; + } + /* Find the module in module manager */ + ModuleId module = module_manager.find_module(circuit_lib.model_name(model)); + /* We must find one! */ + VTR_ASSERT(true == module_manager.valid_module_id(module)); + + /* Rename all the ports to use lib_name! */ + for (const CircuitPortId& model_port : circuit_lib.model_ports(model)) { + /* Find the module port in module manager. We used prefix when creating the ports */ + ModulePortId module_port = module_manager.find_module_port(module, circuit_lib.port_prefix(model_port)); + /* We must find one! */ + VTR_ASSERT(true == module_manager.valid_module_port_id(module, module_port)); + /* Name it with lib_name */ + module_manager.set_module_port_name(module, module_port, circuit_lib.port_lib_name(model_port)); + } + } +} + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h index 34200f68b..417f265b6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h @@ -13,4 +13,7 @@ void build_user_defined_modules(ModuleManager& module_manager, void build_constant_generator_modules(ModuleManager& module_manager); +void rename_primitive_module_port_names(ModuleManager& module_manager, + const CircuitLibrary& circuit_lib); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 57eca34e7..b298c22c1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -369,7 +369,7 @@ void build_primitive_block_module(ModuleManager& module_manager, for (auto port : primitive_model_inout_ports) { BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port)); ModulePortId primitive_gpio_port_id = module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GPIO_PORT); - ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_lib_name(port)); + ModulePortId logic_gpio_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(port)); BasicPort logic_gpio_port = module_manager.module_port(logic_module, logic_gpio_port_id); VTR_ASSERT(logic_gpio_port.get_width() == module_port.get_width()); @@ -530,7 +530,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* First net is to connect input of src_pb_graph_node to input of the wire module */ add_module_pb_graph_pin2pin_net(module_manager, pb_module, wire_module, wire_instance, - circuit_lib.port_lib_name(interc_model_inputs[0]), + circuit_lib.port_prefix(interc_model_inputs[0]), 0, /* wire input port has only 1 pin */ module_name_prefix, src_pb_graph_pin, @@ -539,7 +539,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ add_module_pb_graph_pin2pin_net(module_manager, pb_module, wire_module, wire_instance, - circuit_lib.port_lib_name(interc_model_outputs[0]), + circuit_lib.port_prefix(interc_model_outputs[0]), 0, /* wire output port has only 1 pin */ module_name_prefix, des_pb_graph_pin, @@ -610,7 +610,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Add a net, set its source and sink */ add_module_pb_graph_pin2pin_net(module_manager, pb_module, mux_module, mux_instance, - circuit_lib.port_lib_name(interc_model_inputs[0]), + circuit_lib.port_prefix(interc_model_inputs[0]), mux_input_pin_id, module_name_prefix, src_pb_graph_pin, @@ -623,7 +623,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Add a net to wire the output of the multiplexer to des_pb_graph_pin */ add_module_pb_graph_pin2pin_net(module_manager, pb_module, mux_module, mux_instance, - circuit_lib.port_lib_name(interc_model_outputs[0]), + circuit_lib.port_prefix(interc_model_outputs[0]), 0, /* MUX should have only 1 pin in its output port */ module_name_prefix, des_pb_graph_pin, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp index 75795bd50..3122cf178 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp @@ -82,36 +82,36 @@ void build_lut_module(ModuleManager& module_manager, /* Add each global port */ for (const auto& port : lut_global_ports) { /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(lut_module, global_port, ModuleManager::MODULE_GLOBAL_PORT); } /* Add each input port */ for (const auto& port : lut_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort input_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(lut_module, input_port, ModuleManager::MODULE_INPUT_PORT); /* Set the port to be wire-connection */ module_manager.set_port_is_wire(lut_module, input_port.get_name(), true); } /* Add each output port */ for (const auto& port : lut_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort output_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(lut_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); /* Set the port to be wire-connection */ module_manager.set_port_is_wire(lut_module, output_port.get_name(), true); } /* Add each regular (not mode select) SRAM port */ for (const auto& port : lut_regular_sram_ports) { - BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); + BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port)); module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); } /* Add each mode-select SRAM port */ for (const auto& port : lut_mode_select_sram_ports) { - BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port)); + BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port)); module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); } @@ -149,7 +149,7 @@ void build_lut_module(ModuleManager& module_manager, std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]); size_t mode_select_port_lsb = 0; for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { - ModulePortId lut_module_input_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(lut_input_ports[0])); + ModulePortId lut_module_input_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_input_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_input_port_id)); /* Create a module net for the connection */ @@ -222,13 +222,13 @@ void build_lut_module(ModuleManager& module_manager, ModuleNetId gate_sram_net = module_manager.create_module_net(lut_module); /* Find the module port id of the SRAM port of LUT module */ - ModulePortId lut_module_mode_select_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(lut_mode_select_sram_ports[0])); + ModulePortId lut_module_mode_select_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_mode_select_sram_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_mode_select_port_id)); /* Set the source of the net to an mode-select SRAM port of the LUT module */ module_manager.add_module_net_source(lut_module, gate_sram_net, lut_module, 0, lut_module_mode_select_port_id, mode_select_port_lsb); /* Find the module port id of the SRAM port of LUT module */ - ModulePortId gate_module_input0_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_lib_name(gate_input_ports[0])); + ModulePortId gate_module_input0_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_input_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input0_port_id)); /* Set the sink of the net to an input[0] port of the gate module */ VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input0_port_id).get_width()); @@ -237,7 +237,7 @@ void build_lut_module(ModuleManager& module_manager, } /* Use the existing net to connect to the input[1] port of the gate module */ - ModulePortId gate_module_input1_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_lib_name(gate_input_ports[1])); + ModulePortId gate_module_input1_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_input_ports[1])); VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input1_port_id)); VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input1_port_id).get_width()); for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input1_port_id).pins()) { @@ -246,7 +246,7 @@ void build_lut_module(ModuleManager& module_manager, /* Create a module net for the output connection */ ModuleNetId gate_output_net = module_manager.create_module_net(lut_module); - ModulePortId gate_module_output_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_lib_name(gate_output_ports[0])); + ModulePortId gate_module_output_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_output_port_id)); BasicPort gate_module_output_port = module_manager.module_port(gate_module, gate_module_output_port_id); VTR_ASSERT(1 == gate_module_output_port.get_width()); @@ -326,7 +326,7 @@ void build_lut_module(ModuleManager& module_manager, * 3. Data input of LUT MUX module to SRAM port of LUT * 4. Data output of LUT MUX module to output ports of LUT */ - ModulePortId lut_mux_sram_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_lib_name(lut_regular_sram_ports[0])); + ModulePortId lut_mux_sram_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(lut_regular_sram_ports[0])); BasicPort lut_mux_sram_port = module_manager.module_port(lut_mux_module, lut_mux_sram_port_id); VTR_ASSERT(lut_mux_sram_port.get_width() == lut_mux_sram_nets.size()); /* Wire the port to lut_mux_sram_net */ @@ -334,7 +334,7 @@ void build_lut_module(ModuleManager& module_manager, module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin); } - ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_lib_name(lut_regular_sram_ports[0]) + "_inv")); + ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + "_inv")); BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id); VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size()); /* Wire the port to lut_mux_sram_net */ @@ -351,9 +351,9 @@ void build_lut_module(ModuleManager& module_manager, * | * net */ - ModulePortId lut_sram_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(lut_regular_sram_ports[0])); + ModulePortId lut_sram_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_regular_sram_ports[0])); BasicPort lut_sram_port = module_manager.module_port(lut_module, lut_sram_port_id); - ModulePortId lut_mux_input_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_lib_name(lut_input_ports[0])); + ModulePortId lut_mux_input_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(lut_input_ports[0])); BasicPort lut_mux_input_port = module_manager.module_port(lut_mux_module, lut_mux_input_port_id); VTR_ASSERT(lut_mux_input_port.get_width() == lut_sram_port.get_width()); /* Wire the port to lut_mux_sram_net */ @@ -364,9 +364,9 @@ void build_lut_module(ModuleManager& module_manager, } for (const auto& port : lut_output_ports) { - ModulePortId lut_output_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_lib_name(port)); + ModulePortId lut_output_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(port)); BasicPort lut_output_port = module_manager.module_port(lut_module, lut_output_port_id); - ModulePortId lut_mux_output_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_lib_name(port)); + ModulePortId lut_mux_output_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(port)); BasicPort lut_mux_output_port = module_manager.module_port(lut_mux_module, lut_mux_output_port_id); VTR_ASSERT(lut_mux_output_port.get_width() == lut_output_port.get_width()); /* Wire the port to lut_mux_sram_net */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index 718b47cdb..a4a33bed2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -48,8 +48,8 @@ void add_module_input_nets_to_mem_modules(ModuleManager& module_manager, const size_t& child_instance) { /* Wire inputs of parent module to inputs of child modules */ for (const auto& port : circuit_ports) { - ModulePortId src_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_lib_name(port)); - ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(port)); + ModulePortId src_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port)); + ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port)); for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(mem_module); /* Source pin is shifted by the number of memories */ @@ -82,8 +82,8 @@ void add_module_output_nets_to_mem_modules(ModuleManager& module_manager, const size_t& child_instance) { /* Wire inputs of parent module to inputs of child modules */ for (const auto& port : circuit_ports) { - ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(port)); - ModulePortId sink_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_lib_name(port)); + ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port)); + ModulePortId sink_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port)); for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(mem_module); /* Source pin is shifted by the number of memories */ @@ -121,7 +121,7 @@ std::vector add_module_output_nets_to_chain_mem_modules(ModuleManag std::vector module_nets; /* Wire inputs of parent module to inputs of child modules */ - ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_lib_name(circuit_port)); + ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(circuit_port)); ModulePortId sink_port_id = module_manager.find_module_port(mem_module, mem_module_output_name); for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) { ModuleNetId net = module_manager.create_module_net(mem_module); @@ -188,19 +188,19 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ - std::string sink_port_name = circuit_lib.port_lib_name(model_input_port); + std::string sink_port_name = circuit_lib.port_prefix(model_input_port); net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); } else { /* Find the port name of previous memory module */ - std::string src_port_name = circuit_lib.port_lib_name(model_output_port); + std::string src_port_name = circuit_lib.port_prefix(model_output_port); net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1]; net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); /* Find the port name of next memory module */ - std::string sink_port_name = circuit_lib.port_lib_name(model_input_port); + std::string sink_port_name = circuit_lib.port_prefix(model_input_port); net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); @@ -239,7 +239,7 @@ void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, * net sink is the configuration chain tail of the primitive module */ /* Find the port name of previous memory module */ - std::string src_port_name = circuit_lib.port_lib_name(model_output_port); + std::string src_port_name = circuit_lib.port_prefix(model_output_port); ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back(); ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); @@ -311,12 +311,12 @@ void build_memory_standalone_module(ModuleManager& module_manager, /* Add each input port */ for (const auto& port : sram_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_mems); + BasicPort input_port(circuit_lib.port_prefix(port), num_mems); module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT); } /* Add each output port: port width should match the number of memories */ for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_mems); + BasicPort output_port(circuit_lib.port_prefix(port), num_mems); module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); } @@ -500,29 +500,29 @@ void build_memory_bank_module(ModuleManager& module_manager, /* Add module ports: the ports come from the SRAM modules */ /* Add each input port */ for (const auto& port : sram_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + BasicPort input_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT); } /* Add each output port: port width should match the number of memories */ for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); } /* Add each output port: port width should match the number of memories */ for (const auto& port : sram_bl_ports) { - BasicPort bl_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + BasicPort bl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT); } for (const auto& port : sram_blb_ports) { - BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + BasicPort blb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); module_manager.add_port(mem_module, blb_port, ModuleManager::MODULE_INPUT_PORT); } for (const auto& port : sram_wl_ports) { - BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + BasicPort wl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT); } for (const auto& port : sram_wlb_ports) { - BasicPort wlb_port(circuit_lib.port_lib_name(port), num_mems * circuit_lib.port_size(port)); + BasicPort wlb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); module_manager.add_port(mem_module, wlb_port, ModuleManager::MODULE_INPUT_PORT); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 529f1e760..3d550d9ee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -74,25 +74,25 @@ void build_cmos_mux_branch_body(ModuleManager& module_manager, /* Find the module ports of tgate module */ /* Input port is the data path input of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_input = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_input_ports[0])); + ModulePortId tgate_module_input = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_input)); BasicPort tgate_module_input_port = module_manager.module_port(tgate_module_id, tgate_module_input); VTR_ASSERT(1 == tgate_module_input_port.get_width()); /* Mem port is the memory of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_mem = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_input_ports[1])); + ModulePortId tgate_module_mem = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[1])); VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem)); BasicPort tgate_module_mem_port = module_manager.module_port(tgate_module_id, tgate_module_mem); VTR_ASSERT(1 == tgate_module_mem_port.get_width()); /* Mem inv port is the inverted memory of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_mem_inv = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_input_ports[2])); + ModulePortId tgate_module_mem_inv = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[2])); VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem_inv)); BasicPort tgate_module_mem_inv_port = module_manager.module_port(tgate_module_id, tgate_module_mem_inv); VTR_ASSERT(1 == tgate_module_mem_inv_port.get_width()); /* Output port is the data path output of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_output = module_manager.find_module_port(tgate_module_id, circuit_lib.port_lib_name(tgate_output_ports[0])); + ModulePortId tgate_module_output = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_output)); BasicPort tgate_module_output_port = module_manager.module_port(tgate_module_id, tgate_module_output); VTR_ASSERT(1 == tgate_module_output_port.get_width()); @@ -300,26 +300,26 @@ void build_rram_mux_branch_module(ModuleManager& module_manager, std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true, true); for (const auto& port : prog_enable_ports) { /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(mux_module, global_port, ModuleManager::MODULE_GLOBAL_PORT); } /* Add each input port */ - BasicPort input_port(circuit_lib.port_lib_name(mux_input_ports[0]), num_inputs); + BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs); module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); /* Add each output port */ - BasicPort output_port(circuit_lib.port_lib_name(mux_output_ports[0]), num_outputs); + BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs); module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); /* Add RRAM programming ports, * RRAM MUXes require one more pair of BLB and WL * to configure the memories. See schematic for details */ - BasicPort blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), num_mems + 1); + BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1); module_manager.add_port(mux_module, blb_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort wl_port(circuit_lib.port_lib_name(mux_wl_ports[0]), num_mems + 1); + BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1); module_manager.add_port(mux_module, wl_port, ModuleManager::MODULE_INPUT_PORT); /* Note: we do not generate the internal structure of the ReRAM-based MUX @@ -398,20 +398,20 @@ void build_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_man std::vector std_cell_module_input_ports; /* Input 0 port is the first data path input of the tgate, whose size must be 1 ! */ for (size_t port_id = 0; port_id < 2; ++port_id) { - std_cell_module_inputs.push_back(module_manager.find_module_port(std_cell_module_id, circuit_lib.port_lib_name(std_cell_input_ports[port_id]))); + std_cell_module_inputs.push_back(module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_input_ports[port_id]))); VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_inputs[port_id])); std_cell_module_input_ports.push_back(module_manager.module_port(std_cell_module_id, std_cell_module_inputs[port_id])); VTR_ASSERT(1 == std_cell_module_input_ports[port_id].get_width()); } /* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */ - ModulePortId std_cell_module_mem = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_lib_name(std_cell_input_ports[2])); + ModulePortId std_cell_module_mem = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_input_ports[2])); VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_mem)); BasicPort std_cell_module_mem_port = module_manager.module_port(std_cell_module_id, std_cell_module_mem); VTR_ASSERT(1 == std_cell_module_mem_port.get_width()); /* Output port is the data path output of the standard cell MUX2, whose size must be 1 ! */ - ModulePortId std_cell_module_output = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_lib_name(std_cell_output_ports[0])); + ModulePortId std_cell_module_output = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_output)); BasicPort std_cell_module_output_port = module_manager.module_port(std_cell_module_id, std_cell_module_output); VTR_ASSERT(1 == std_cell_module_output_port.get_width()); @@ -745,7 +745,7 @@ vtr::vector build_mux_module_input_buffers(ModuleManage VTR_ASSERT(1 == mux_input_ports.size()); /* Get the input port from MUX module */ - ModulePortId module_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_input_ports[0])); + ModulePortId module_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_input_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); /* Get the port from module */ BasicPort module_input_port = module_manager.module_port(mux_module, module_input_port_id); @@ -860,7 +860,7 @@ vtr::vector build_mux_module_output_buffers(ModuleMana /* Iterate over all the outputs in the MUX module */ for (const auto& output_port : mux_output_ports) { /* Get the output port from MUX module */ - ModulePortId module_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(output_port)); + ModulePortId module_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(output_port)); VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); /* Get the port from module */ BasicPort module_output_port = module_manager.module_port(mux_module, module_output_port_id); @@ -968,7 +968,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag /* Add mem and mem_inv nets here */ size_t mem_net_cnt = 0; for (const auto& port : mux_sram_ports) { - ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(port)); + ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(port)); BasicPort mem_port = module_manager.module_port(mux_module, mem_port_id); for (const size_t& pin : mem_port.pins()) { MuxMemId mem_id = MuxMemId(mem_net_cnt); @@ -983,7 +983,7 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag /* Add mem and mem_inv nets here */ size_t mem_inv_net_cnt = 0; for (const auto& port : mux_sram_ports) { - ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_lib_name(port) + "_inv")); + ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + "_inv")); BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id); for (const size_t& pin : mem_inv_port.pins()) { MuxMemId mem_id = MuxMemId(mem_inv_net_cnt); @@ -1003,9 +1003,9 @@ void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manag BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ - ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0])); - ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_sram_ports[0]) + "_inv"); - BasicPort lvl_addr_port(circuit_lib.port_lib_name(mux_sram_ports[0]), 0); + ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0])); + ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + "_inv"); + BasicPort lvl_addr_port(circuit_lib.port_prefix(mux_sram_ports[0]), 0); BasicPort lvl_data_port(decoder_data_port.get_name(), 0); BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); @@ -1161,7 +1161,7 @@ void build_cmos_mux_module(ModuleManager& module_manager, */ size_t input_port_cnt = 0; for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + BasicPort input_port(circuit_lib.port_prefix(port), num_inputs); module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); /* Update counter */ input_port_cnt++; @@ -1173,7 +1173,7 @@ void build_cmos_mux_module(ModuleManager& module_manager, vtr::vector mux_input_nets = build_mux_module_input_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph); for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + BasicPort output_port(circuit_lib.port_prefix(port), num_outputs); if (SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) { output_port.set_width(circuit_lib.port_size(port)); } @@ -1185,9 +1185,9 @@ void build_cmos_mux_module(ModuleManager& module_manager, size_t sram_port_cnt = 0; for (const auto& port : mux_sram_ports) { - BasicPort mem_port(circuit_lib.port_lib_name(port), num_mems); + BasicPort mem_port(circuit_lib.port_prefix(port), num_mems); module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), num_mems); + BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), num_mems); module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); /* Update counter */ sram_port_cnt++; @@ -1305,13 +1305,13 @@ void build_rram_mux_module(ModuleManager& module_manager, /* Add each global port */ for (const auto& port : mux_global_ports) { /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } /* Add each input port */ size_t input_port_cnt = 0; for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + BasicPort input_port(circuit_lib.port_prefix(port), num_inputs); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); /* Update counter */ input_port_cnt++; @@ -1320,7 +1320,7 @@ void build_rram_mux_module(ModuleManager& module_manager, VTR_ASSERT(1 == input_port_cnt); for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + BasicPort output_port(circuit_lib.port_prefix(port), num_outputs); if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { output_port.set_width(circuit_lib.port_size(port)); } @@ -1332,7 +1332,7 @@ void build_rram_mux_module(ModuleManager& module_manager, /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level * So, the actual port width of BLB should be added by the number of levels of the MUX graph */ - BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + BasicPort blb_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); } @@ -1341,7 +1341,7 @@ void build_rram_mux_module(ModuleManager& module_manager, /* IMPORTANT: RRAM-based MUX has an additional WL pin per level * So, the actual port width of WL should be added by the number of levels of the MUX graph */ - BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + BasicPort wl_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 94de58fea..04842a5cc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -259,7 +259,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager, std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); VTR_ASSERT(1 == mux_model_input_ports.size()); /* Find the module port id of the input port */ - ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_input_ports[0])); + ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); @@ -278,7 +278,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager, std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); VTR_ASSERT(1 == mux_model_output_ports.size()); /* Use the port name convention in the circuit library */ - ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_output_ports[0])); + ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); ModulePortId sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); @@ -733,7 +733,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); VTR_ASSERT(1 == mux_model_input_ports.size()); /* Find the module port id of the input port */ - ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_input_ports[0])); + ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); @@ -752,7 +752,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); VTR_ASSERT(1 == mux_model_output_ports.size()); /* Use the port name convention in the circuit library */ - ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_lib_name(mux_model_output_ports[0])); + ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, grids, cur_rr_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp index 536ab15c8..dafce007b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp @@ -92,13 +92,13 @@ void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, /* Find inputs and outputs of the direct circuit module */ std::vector direct_input_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_INPUT, true); VTR_ASSERT(1 == direct_input_ports.size()); - ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_input_ports[0])); + ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_prefix(direct_input_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_input_port_id)); VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_input_port_id).get_width()); std::vector direct_output_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); VTR_ASSERT(1 == direct_output_ports.size()); - ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_lib_name(direct_output_ports[0])); + ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_prefix(direct_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id)); VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width()); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp index f338110c8..6a064fa37 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp @@ -93,7 +93,7 @@ void build_routing_wire_module(ModuleManager& module_manager, ModuleId wire_module = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model, wire_subckt_name); /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); module_manager.add_port(wire_module, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 13cd62ada..5f116f4a0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -40,7 +40,7 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----")); /* Create a sensitive list */ - fp << "\treg " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; + fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; fp << "\talways @(" << std::endl; /* Power-gate port first*/ @@ -49,9 +49,9 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, if (0 < &power_gate_port - &power_gate_ports[0]) { fp << ","; } - fp << circuit_lib.port_lib_name(power_gate_port); + fp << circuit_lib.port_prefix(power_gate_port); } - fp << circuit_lib.port_lib_name(input_port) << ") begin" << std::endl; + fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; /* Dump the case of power-gated */ fp << "\t\tif ("; @@ -71,14 +71,14 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_lib_name(power_gate_port) << "[" << power_gate_pin << "])"; + fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])"; port_cnt++; /* Update port counter*/ } } fp << ") begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = "; + fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -93,12 +93,12 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; + fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; fp << "\t\tend else begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_lib_name(output_port) << "_reg = 1'bz;" << std::endl; + fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl; fp << "\t\tend" << std::endl; fp << "\tend" << std::endl; - fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = " << circuit_lib.port_lib_name(output_port) << "_reg;" << std::endl; + fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; } /************************************************ @@ -116,7 +116,7 @@ void print_verilog_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); - fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " === 1'bz)? $random : "; + fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -131,7 +131,7 @@ void print_verilog_invbuf_body(std::fstream& fp, fp << "~"; } - fp << circuit_lib.port_lib_name(input_port) << ";" << std::endl; + fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; } /************************************************ @@ -282,8 +282,8 @@ void print_verilog_passgate_module(ModuleManager& module_manager, /* Dump logics: we propagate input to the output when the gate is '1' * the input is blocked from output when the gate is '0' */ - fp << "\tassign " << circuit_lib.port_lib_name(output_ports[0]) << " = "; - fp << circuit_lib.port_lib_name(input_ports[1]) << " ? " << circuit_lib.port_lib_name(input_ports[0]); + fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = "; + fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]); fp << " : 1'bz;" << std::endl; /* Print timing info */ @@ -329,7 +329,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp, for (const auto& output_port : output_ports) { for (const auto& output_pin : circuit_lib.pins(output_port)) { - BasicPort output_port_info(circuit_lib.port_lib_name(output_port), output_pin, output_pin); + BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin); fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info); fp << " = "; @@ -341,7 +341,7 @@ void print_verilog_and_or_gate_body(std::fstream& fp, fp << " " << gate_verilog_operator << " "; } - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), input_pin, input_pin); + BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin); fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); /* Increment the counter for port */ @@ -413,10 +413,10 @@ void print_verilog_mux2_gate_body(std::fstream& fp, * the third input is the select port */ fp << "\tassign "; - BasicPort out_port_info(circuit_lib.port_lib_name(output_ports[0]), 0, 0); - BasicPort sel_port_info(circuit_lib.port_lib_name(input_ports[2]), 0, 0); - BasicPort in0_port_info(circuit_lib.port_lib_name(input_ports[0]), 0, 0); - BasicPort in1_port_info(circuit_lib.port_lib_name(input_ports[1]), 0, 0); + BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0); + BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0); + BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0); + BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0); fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info); fp << " = "; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 7fd71767d..06c2e1f4c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -538,18 +538,18 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(module_id)); /* Find each input port */ - BasicPort input_port(circuit_lib.port_lib_name(mux_input_ports[0]), num_inputs); + BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs); /* Find each output port */ - BasicPort output_port(circuit_lib.port_lib_name(mux_output_ports[0]), num_outputs); + BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs); /* Find RRAM programming ports, * RRAM MUXes require one more pair of BLB and WL * to configure the memories. See schematic for details */ - BasicPort blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), num_mems + 1); + BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1); - BasicPort wl_port(circuit_lib.port_lib_name(mux_wl_ports[0]), num_mems + 1); + BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1); /* dump module definition + ports */ print_verilog_module_declaration(fp, module_manager, module_id); @@ -633,7 +633,7 @@ void generate_verilog_cmos_mux_module_input_buffers(ModuleManager& module_manage VTR_ASSERT(1 == mux_input_ports.size()); /* Get the input port from MUX module */ - ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(mux_input_ports[0])); + ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(mux_input_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); /* Get the port from module */ BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); @@ -721,7 +721,7 @@ void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manag /* Iterate over all the outputs in the MUX module */ for (const auto& output_port : mux_output_ports) { /* Get the output port from MUX module */ - ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(output_port)); + ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(output_port)); VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); /* Get the port from module */ BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); @@ -918,7 +918,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu for (const auto& mem : mems) { /* Generate the port info of each mem node: */ - BasicPort branch_node_blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), size_t(mem), size_t(mem)); + BasicPort branch_node_blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), size_t(mem), size_t(mem)); branch_node_blb_ports.push_back(branch_node_blb_port); } /* Every stage, we have an additonal BLB and WL in controlling purpose @@ -930,7 +930,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu * * output_node_level is always larger than the mem_level by 1 */ - branch_node_blb_ports.push_back(BasicPort(circuit_lib.port_lib_name(mux_blb_ports[0]), + branch_node_blb_ports.push_back(BasicPort(circuit_lib.port_prefix(mux_blb_ports[0]), mux_graph.num_memory_bits() + output_node_level - 1, mux_graph.num_memory_bits() + output_node_level - 1) ); @@ -949,7 +949,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu } /* Link nodes to BLB ports for the branch module */ - ModulePortId module_blb_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_lib_name(mux_blb_ports[0])); + ModulePortId module_blb_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_prefix(mux_blb_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_blb_port_id); /* Get the port from module */ BasicPort module_blb_port = module_manager.module_port(branch_module_id, module_blb_port_id); @@ -959,7 +959,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu for (const auto& mem : mems) { /* Generate the port info of each mem node: */ - BasicPort branch_node_blb_port(circuit_lib.port_lib_name(mux_wl_ports[0]), size_t(mem), size_t(mem)); + BasicPort branch_node_blb_port(circuit_lib.port_prefix(mux_wl_ports[0]), size_t(mem), size_t(mem)); branch_node_wl_ports.push_back(branch_node_blb_port); } /* Every stage, we have an additonal BLB and WL in controlling purpose @@ -971,7 +971,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu * * output_node_level is always larger than the mem_level by 1 */ - branch_node_wl_ports.push_back(BasicPort(circuit_lib.port_lib_name(mux_wl_ports[0]), + branch_node_wl_ports.push_back(BasicPort(circuit_lib.port_prefix(mux_wl_ports[0]), mux_graph.num_memory_bits() + output_node_level - 1, mux_graph.num_memory_bits() + output_node_level - 1) ); @@ -990,7 +990,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu } /* Link nodes to BLB ports for the branch module */ - ModulePortId module_wl_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_lib_name(mux_wl_ports[0])); + ModulePortId module_wl_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_prefix(mux_wl_ports[0])); VTR_ASSERT(ModulePortId::INVALID() != module_wl_port_id); /* Get the port from module */ BasicPort module_wl_port = module_manager.module_port(branch_module_id, module_wl_port_id); @@ -1107,13 +1107,13 @@ void generate_verilog_rram_mux_module(ModuleManager& module_manager, /* Add each global port */ for (const auto& port : mux_global_ports) { /* Configure each global port */ - BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port)); + BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); } /* Add each input port */ size_t input_port_cnt = 0; for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs); + BasicPort input_port(circuit_lib.port_prefix(port), num_inputs); module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); /* Update counter */ input_port_cnt++; @@ -1122,7 +1122,7 @@ void generate_verilog_rram_mux_module(ModuleManager& module_manager, VTR_ASSERT(1 == input_port_cnt); for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs); + BasicPort output_port(circuit_lib.port_prefix(port), num_outputs); if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { output_port.set_width(circuit_lib.port_size(port)); } @@ -1134,7 +1134,7 @@ void generate_verilog_rram_mux_module(ModuleManager& module_manager, /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level * So, the actual port width of BLB should be added by the number of levels of the MUX graph */ - BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + BasicPort blb_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); } @@ -1143,7 +1143,7 @@ void generate_verilog_rram_mux_module(ModuleManager& module_manager, /* IMPORTANT: RRAM-based MUX has an additional WL pin per level * So, the actual port width of WL should be added by the number of levels of the MUX graph */ - BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels()); + BasicPort wl_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index 9147cc053..4e955cc7f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -120,7 +120,7 @@ void print_verilog_preconfig_top_module_connect_global_ports(std::fstream& fp, CircuitPortId linked_circuit_port_id = CircuitPortId::INVALID(); /* Find the circuit port with the same name */ for (const CircuitPortId& circuit_port_id : global_ports) { - if (0 != module_global_port.get_name().compare(circuit_lib.port_lib_name(circuit_port_id))) { + if (0 != module_global_port.get_name().compare(circuit_lib.port_prefix(circuit_port_id))) { continue; } linked_circuit_port_id = circuit_port_id; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index a4199308d..202fae1a0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3134,7 +3134,7 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager, VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); + BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp index 644df5246..4fcebf6c4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -109,7 +109,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * connect it to the local wire of operating clock */ /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); BasicPort stimuli_clock_port; @@ -141,7 +141,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, } /* Reach here, it means we have a configuration done port to deal with */ /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); BasicPort stimuli_config_done_port(std::string(top_tb_config_done_port_name), 1); @@ -170,7 +170,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, } /* Reach here, it means we have a reset port to deal with */ /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); BasicPort stimuli_reset_port; @@ -212,7 +212,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, } /* Reach here, it means we have a set port to deal with */ /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); BasicPort stimuli_set_port; @@ -256,7 +256,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, /* Reach here, it means we have a port to deal with */ /* Find the module port and wire it to constant values */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_lib_name(model_global_port)); + ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); BasicPort module_port = module_manager.module_port(top_module, module_global_port); From 696d4a95224eb4a2111c88e15274de4139428ee5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 16:10:00 -0700 Subject: [PATCH 433/482] remove useless channel wire module generation --- .../build_essential_modules.cpp | 27 ----- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 63 +---------- .../vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp | 104 +----------------- .../vpr/SRC/fpga_x2p/verilog/verilog_wire.h | 1 - 4 files changed, 5 insertions(+), 190 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index ca2b17a1b..8ebe2ab0e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -209,33 +209,6 @@ void build_user_defined_modules(ModuleManager& module_manager, add_circuit_model_to_module_manager(module_manager, circuit_lib, model); } - /* Register the routing channel wires */ - for (const auto& seg : routing_segments) { - VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); - VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); - /* We care only user-defined circuit models */ - if ( (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) - && (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) ) { - continue; - } - /* Give a unique name for subckt of wire_model of segment, - * circuit_model name is unique, and segment id is unique as well - */ - std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); - - /* Find the output port*/ - std::vector output_ports = circuit_lib.model_ports_by_type(seg.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Make sure the port size is what we want */ - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); - module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 202fae1a0..a792ed4ae 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3085,8 +3085,7 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, ********************************************************************/ static void add_user_defined_verilog_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& routing_segments) { + const CircuitLibrary& circuit_lib) { /* Iterate over Verilog modules */ for (const auto& model : circuit_lib.models()) { /* We only care about user-defined models */ @@ -3106,37 +3105,6 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager, add_circuit_model_to_module_manager(module_manager, circuit_lib, model); } } - - /* Register the routing channel wires */ - for (const auto& seg : routing_segments) { - VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); - VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); - /* We care only user-defined circuit models */ - if (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) { - continue; - } - /* Give a unique name for subckt of wire_model of segment, - * circuit_model name is unique, and segment id is unique as well - */ - std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - - /* Try to find the module in the module manager, - * If not found, create a Verilog Module based on the circuit model, - * and add to module manager */ - if (ModuleId::INVALID() != module_manager.find_module(segment_wire_subckt_name)) { - continue; - } - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); - - /* Find the output port*/ - std::vector output_ports = circuit_lib.model_ports_by_type(seg.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Make sure the port size is what we want */ - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); - module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); - } } /* Print a template for a user-defined circuit model @@ -3186,7 +3154,6 @@ void print_one_verilog_template_module(const ModuleManager& module_manager, static void print_verilog_submodule_templates(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - const std::vector& routing_segments, const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name); @@ -3220,22 +3187,6 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager, print_one_verilog_template_module(module_manager, fp, circuit_lib.model_name(model)); } - /* Register the routing channel wires */ - for (const auto& seg : routing_segments) { - VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); - VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); - /* We care only user-defined circuit models */ - if (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) { - continue; - } - /* Give a unique name for subckt of wire_model of segment, - * circuit_model name is unique, and segment id is unique as well - */ - std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - /* Print a Verilog template for the circuit model */ - print_one_verilog_template_module(module_manager, fp, segment_wire_subckt_name); - } - /* close file stream */ fp.close(); @@ -3255,18 +3206,12 @@ void dump_verilog_submodules(ModuleManager& module_manager, t_det_routing_arch* routing_arch, t_syn_verilog_opts fpga_verilog_opts) { - /* Create a vector of segments. TODO: should come from DeviceContext */ - std::vector L_segment_vec; - for (int i = 0; i < Arch.num_segments; ++i) { - L_segment_vec.push_back(Arch.Segments[i]); - } - /* TODO: Register all the user-defined modules in the module manager * This should be done prior to other steps in this function, * because they will be instanciated by other primitive modules */ vpr_printf(TIO_MESSAGE_INFO, "Registering user-defined modules...\n"); - add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib, L_segment_vec); + add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib); print_verilog_submodule_essentials(module_manager, std::string(verilog_dir), @@ -3299,7 +3244,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, fpga_verilog_opts.dump_explicit_verilog); /* 3. Hardwires */ - print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); + print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 4. Memories */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n"); @@ -3311,7 +3256,7 @@ void dump_verilog_submodules(ModuleManager& module_manager, /* 5. Dump template for all the modules */ if (TRUE == fpga_verilog_opts.print_user_defined_template) { - print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, L_segment_vec, std::string(verilog_dir), std::string(submodule_dir)); + print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); } /* Create a header file to include all the subckts */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp index b8b9443bc..1efe6d6cb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp @@ -90,92 +90,10 @@ void print_verilog_wire_module(ModuleManager& module_manager, } /******************************************************************** - * Print a Verilog module of a routing track wire segment - * Routing track wire, which is 1-input and dual output - * This type of wires are used in the global routing architecture. - * One of the output is wired to another Switch block multiplexer, - * while the mid-output is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * + * Top-level function to print wire modules *******************************************************************/ -static -void print_verilog_routing_wire_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& wire_model, - const std::string& wire_subckt_name) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Make sure the port size is what we want */ - VTR_ASSERT (1 == input_ports.size()); - VTR_ASSERT (1 == output_ports.size()); - VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId wire_module = module_manager.find_module(wire_subckt_name); - VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); - - /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); - ModulePortId module_mid_output_port_id = module_manager.find_module_port(wire_module, module_mid_output_port.get_name()); - VTR_ASSERT(ModulePortId::INVALID() != module_mid_output_port_id); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, wire_module); - /* Finish dumping ports */ - - /* Print the internal logic of Verilog module */ - /* Find the input port of the module */ - ModulePortId module_input_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(input_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - BasicPort module_input_port = module_manager.module_port(wire_module, module_input_port_id); - - /* Find the output port of the module */ - ModulePortId module_output_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(output_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - BasicPort module_output_port = module_manager.module_port(wire_module, module_output_port_id); - - /* Print wire declaration for the inputs and outputs */ - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_output_port) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_mid_output_port) << ";" << std::endl; - - /* Direct shortcut */ - print_verilog_wire_connection(fp, module_output_port, module_input_port, false); - print_verilog_wire_connection(fp, module_mid_output_port, module_input_port, false); - - /* Print timing info */ - print_verilog_submodule_timing(fp, circuit_lib, wire_model); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(wire_model)); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - void print_verilog_submodule_wires(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - std::vector routing_segments, const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + wires_verilog_file_name); @@ -205,26 +123,6 @@ void print_verilog_submodule_wires(ModuleManager& module_manager, print_verilog_wire_module(module_manager, circuit_lib, fp, model); } print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----")); - - /* Create wire models for routing segments*/ - print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for routing track wires -----")); - - for (const auto& seg : routing_segments) { - VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); - VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); - /* Bypass user-defined circuit models */ - if (!circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) { - continue; - } - /* Give a unique name for subckt of wire_model of segment, - * circuit_model name is unique, and segment id is unique as well - */ - std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - - /* Print a Verilog module */ - print_verilog_routing_wire_module(module_manager, circuit_lib, fp, seg.circuit_model, segment_wire_subckt_name); - } - print_verilog_comment(fp, std::string("----- END Verilog modules for routing track wires -----")); /* Close the file stream */ fp.close(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h index 1d4fc7c71..e45cf483a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h @@ -16,7 +16,6 @@ void print_verilog_submodule_wires(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - std::vector routing_segments, const std::string& verilog_dir, const std::string& submodule_dir); From 7952d134b99192fc996b177e75ef01edfb227320 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 16:24:39 -0700 Subject: [PATCH 434/482] add tree-like mux test case to regression test --- .travis/script.sh | 3 + .../tasks/blif_vpr_flow/config/task.conf | 2 - .../tasks/tree_like_mux/config/task.conf | 59 +++++++++++++++++++ 3 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/tasks/tree_like_mux/config/task.conf diff --git a/.travis/script.sh b/.travis/script.sh index 7c5aab29b..33391d502 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -25,6 +25,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread echo -e "Testing multi-mode architectures"; python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 --debug --show_thread_logs +echo -e "Testing tree-like multiplexer architectures"; +python3 openfpga_flow/scripts/run_fpga_task.py tree_like_mux --maxthreads 4 --debug --show_thread_logs + echo -e "Testing compact routing techniques"; python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index 152fcd6be..67f291319 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -15,14 +15,12 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] -# arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml #arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml -#arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif diff --git a/openfpga_flow/tasks/tree_like_mux/config/task.conf b/openfpga_flow/tasks/tree_like_mux/config/task.conf new file mode 100644 index 000000000..e98e69a14 --- /dev/null +++ b/openfpga_flow/tasks/tree_like_mux/config/task.conf @@ -0,0 +1,59 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v +bench0_chan_width = 300 + +#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] +#fix_route_chan_width=300 +#vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_include_timing= +#vpr_fpga_verilog_include_signal_init= +#vpr_fpga_verilog_print_autocheck_top_testbench= +#vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +##vpr_fpga_x2p_compact_routing_hierarchy= +#end_flow_with_test= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_verilog_print_sdc_pnr= +vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_verilog_explicit_mapping= +vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= + From 00280b835ebee5c1dabc9b5ef05fdd5920461f32 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 16:31:42 -0700 Subject: [PATCH 435/482] reorganize regression tests --- .travis/script.sh | 5 +- .../tasks/blif_vpr_flow/config/task.conf | 64 ------------------- .../tasks/multi_mode/config/task.conf | 22 ++++--- .../tasks/tree_like_mux/config/task.conf | 59 ----------------- 4 files changed, 15 insertions(+), 135 deletions(-) delete mode 100644 openfpga_flow/tasks/blif_vpr_flow/config/task.conf delete mode 100644 openfpga_flow/tasks/tree_like_mux/config/task.conf diff --git a/.travis/script.sh b/.travis/script.sh index 33391d502..dc0f1f18a 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -23,10 +23,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread #python3 openfpga_flow/scripts/run_fpga_task.py s298 echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 --debug --show_thread_logs - -echo -e "Testing tree-like multiplexer architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tree_like_mux --maxthreads 4 --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs echo -e "Testing compact routing techniques"; python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf deleted file mode 100644 index 67f291319..000000000 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ /dev/null @@ -1,64 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml -arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml -arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml -arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml -#arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_verilog_explicit_mapping= -#vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - diff --git a/openfpga_flow/tasks/multi_mode/config/task.conf b/openfpga_flow/tasks/multi_mode/config/task.conf index 5157bb235..51ff24dbd 100644 --- a/openfpga_flow/tasks/multi_mode/config/task.conf +++ b/openfpga_flow/tasks/multi_mode/config/task.conf @@ -15,16 +15,21 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml +arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif [SYNTHESIS_PARAM] -bench0_top = K4n4_test -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v -bench0_chan_width = 100 +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v +bench0_chan_width = 300 #[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] #fix_route_chan_width=300 @@ -38,10 +43,10 @@ bench0_chan_width = 100 #vpr_fpga_verilog_print_report_timing_tcl= #vpr_fpga_verilog_print_sdc_pnr= #vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= +##vpr_fpga_x2p_compact_routing_hierarchy= #end_flow_with_test= -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] min_route_chan_width=1.3 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= @@ -56,3 +61,4 @@ vpr_fpga_verilog_print_sdc_analysis= #vpr_fpga_verilog_explicit_mapping= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= + diff --git a/openfpga_flow/tasks/tree_like_mux/config/task.conf b/openfpga_flow/tasks/tree_like_mux/config/task.conf deleted file mode 100644 index e98e69a14..000000000 --- a/openfpga_flow/tasks/tree_like_mux/config/task.conf +++ /dev/null @@ -1,59 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - From aa56d950738cdf50f1b8977c44a8f9a12856f341 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 17:19:57 -0700 Subject: [PATCH 436/482] bug fixed for using standard cells --- .../module_builder/build_device_module.cpp | 10 +-- .../build_essential_modules.cpp | 13 ++-- .../module_builder/build_essential_modules.h | 3 +- .../module_builder/build_wire_modules.cpp | 65 +------------------ .../module_builder/build_wire_modules.h | 3 +- 5 files changed, 14 insertions(+), 80 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp index 772ee8f57..24c0e8c7d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp @@ -75,12 +75,6 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, arch.sram_inf.verilog_sram_inf_orgz->spice_model); config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, sram_model); - /* Create a vector of segments. TODO: should come from DeviceContext */ - std::vector L_segment_vec; - for (int i = 0; i < arch.num_segments; ++i) { - L_segment_vec.push_back(arch.Segments[i]); - } - /* Add constant generator modules: VDD and GND */ build_constant_generator_modules(module_manager); @@ -88,7 +82,7 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, * This should be done prior to other steps in this function, * because they will be instanciated by other primitive modules */ - build_user_defined_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); + build_user_defined_modules(module_manager, arch.spice->circuit_lib); /* Build elmentary modules */ build_essential_modules(module_manager, arch.spice->circuit_lib); @@ -103,7 +97,7 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, build_lut_modules(module_manager, arch.spice->circuit_lib); /* Build wire modules */ - build_wire_modules(module_manager, arch.spice->circuit_lib, L_segment_vec); + build_wire_modules(module_manager, arch.spice->circuit_lib); /* Build memory modules */ build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 8ebe2ab0e..1769b9d31 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -155,6 +155,12 @@ void build_essential_modules(ModuleManager& module_manager, "Building essential (inverter/buffer/logic gate) modules..."); for (const auto& circuit_model : circuit_lib.models()) { + /* We only care about user-defined models */ + if ( (false == circuit_lib.model_verilog_netlist(circuit_model).empty()) + && (false == circuit_lib.model_spice_netlist(circuit_model).empty()) ) { + continue; + } + if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { build_invbuf_module(module_manager, circuit_lib, circuit_model); continue; @@ -184,8 +190,7 @@ void build_essential_modules(ModuleManager& module_manager, * to the module_manager ********************************************************************/ void build_user_defined_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& routing_segments) { + const CircuitLibrary& circuit_lib) { /* Start time count */ clock_t t_start = clock(); @@ -196,7 +201,7 @@ void build_user_defined_modules(ModuleManager& module_manager, for (const auto& model : circuit_lib.models()) { /* We only care about user-defined models */ if ( (true == circuit_lib.model_verilog_netlist(model).empty()) - && (true == circuit_lib.model_verilog_netlist(model).empty()) ) { + && (true == circuit_lib.model_spice_netlist(model).empty()) ) { continue; } /* Skip Routing channel wire models because they need a different name. Do it later */ @@ -273,7 +278,7 @@ void rename_primitive_module_port_names(ModuleManager& module_manager, for (const CircuitModelId& model : circuit_lib.models()) { /* We only care about user-defined models */ if ( (true == circuit_lib.model_verilog_netlist(model).empty()) - && (true == circuit_lib.model_verilog_netlist(model).empty()) ) { + && (true == circuit_lib.model_spice_netlist(model).empty()) ) { continue; } /* Skip Routing channel wire models because they need a different name. Do it later */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h index 417f265b6..703d8a285 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h @@ -8,8 +8,7 @@ void build_essential_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib); void build_user_defined_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& routing_segments); + const CircuitLibrary& circuit_lib); void build_constant_generator_modules(ModuleManager& module_manager); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp index 6a064fa37..fd7527b6d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp @@ -52,51 +52,6 @@ void build_wire_module(ModuleManager& module_manager, add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); } -/******************************************************************** - * Build module of a routing track wire segment - * Routing track wire, which is 1-input and dual output - * This type of wires are used in the global routing architecture. - * One of the output is wired to another Switch block multiplexer, - * while the mid-output is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * - *******************************************************************/ -static -void build_routing_wire_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& wire_model, - const std::string& wire_subckt_name) { - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Make sure the port size is what we want */ - VTR_ASSERT (1 == input_ports.size()); - VTR_ASSERT (1 == output_ports.size()); - VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId wire_module = add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model, wire_subckt_name); - - /* Add a mid-output port to the module */ - BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_prefix(output_ports[0])), circuit_lib.port_size(output_ports[0])); - module_manager.add_port(wire_module, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); -} - /******************************************************************** * This function will only create wire modules with a number of * ports that are defined by users. @@ -104,8 +59,7 @@ void build_routing_wire_module(ModuleManager& module_manager, * by Verilog/SPICE writers *******************************************************************/ void build_wire_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::vector routing_segments) { + const CircuitLibrary& circuit_lib) { /* Start time count */ clock_t t_start = clock(); @@ -122,23 +76,6 @@ void build_wire_modules(ModuleManager& module_manager, build_wire_module(module_manager, circuit_lib, wire_model); } - for (const auto& seg : routing_segments) { - VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model); - VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model)); - /* Bypass user-defined circuit models */ - if ( (!circuit_lib.model_spice_netlist(seg.circuit_model).empty()) - && (!circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) ) { - continue; - } - /* Give a unique name for subckt of wire_model of segment, - * circuit_model name is unique, and segment id is unique as well - */ - std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]); - - /* Print a Verilog module */ - build_routing_wire_module(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); - } - /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h index a68eb22b0..193071526 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h @@ -14,7 +14,6 @@ #include "module_manager.h" void build_wire_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::vector routing_segments); + const CircuitLibrary& circuit_lib); #endif From 227fb9a1a573d806f981d4cd0a6a4ffdf41fc994 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 17:32:05 -0700 Subject: [PATCH 437/482] clean up the support for std cells --- .../SRC/fpga_x2p/module_builder/build_essential_modules.cpp | 6 +++--- .../fpga_x2p/module_builder/build_module_graph_utils.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 1769b9d31..9bb471710 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -155,9 +155,9 @@ void build_essential_modules(ModuleManager& module_manager, "Building essential (inverter/buffer/logic gate) modules..."); for (const auto& circuit_model : circuit_lib.models()) { - /* We only care about user-defined models */ - if ( (false == circuit_lib.model_verilog_netlist(circuit_model).empty()) - && (false == circuit_lib.model_spice_netlist(circuit_model).empty()) ) { + /* Add essential modules upon on demand: only when it is not yet in the module library */ + ModuleId module = module_manager.find_module(circuit_lib.model_name(circuit_model)); + if (true == module_manager.valid_module_id(module)) { continue; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp index 241b5f631..fc710a20d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp @@ -28,7 +28,7 @@ ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manage VTR_ASSERT(1 == model_ports.size()); /* Find the input and output module ports */ - ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_lib_name(model_ports[0])); + ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id)); return module_port_id; From 066962fbb99a8405003f8b92e59308d61fd4c3c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 17:41:21 -0700 Subject: [PATCH 438/482] bug fixed for clb2clb direct connection --- .../SRC/fpga_x2p/module_builder/build_top_module_directs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp index dafce007b..6179e4d4c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp @@ -102,7 +102,7 @@ void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id)); VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width()); - for (size_t pin_id : src_clb_port.pins()) { + for (size_t pin_id = 0; pin_id < src_clb_port.pins().size(); ++pin_id) { /* Generate the pin name of source port/pin in the grid */ size_t src_pin_height = find_grid_pin_height(grids, src_clb_coord, src_clb_port.pins()[pin_id]); e_side src_pin_grid_side = find_grid_pin_side(device_size, grids, src_clb_coord, src_pin_height, src_clb_port.pins()[pin_id]); From 6c04b8d9591e8371101d892e020c764774bbe580 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 20:24:03 -0700 Subject: [PATCH 439/482] bug fixing for heterogeneous FPGAs --- .../vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp | 8 ++++---- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index a8a5d66e9..683b5138d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -684,16 +684,16 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, * FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist() */ if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) { - if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) || (true != rr_gsb.is_cb_exist(cb_type))) { continue; } } if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) { - const RRGSB& adjancent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); - if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) - || (true != adjancent_gsb.is_cb_exist(cb_type))) { + const RRGSB& adjacent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); + if ( (TRUE != is_cb_exist(cb_type, adjacent_gsb.get_cb_x(cb_type), adjacent_gsb.get_cb_y(cb_type))) + || (true != adjacent_gsb.is_cb_exist(cb_type))) { continue; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 2c995e864..12afb3a2e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -4064,7 +4064,7 @@ void print_verilog_flatten_connection_block_modules(ModuleManager& module_manage * We will skip those modules */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if ( (TRUE != is_cb_exist(CHANX, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) || (true != rr_gsb.is_cb_exist(cb_type))) { continue; } From aac4ccb279395c6bc7af94d5e7980eba5d7855aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Nov 2019 11:19:17 -0700 Subject: [PATCH 440/482] fixing bug for heterogeneous FPGAs --- .../fpga_x2p/base/fpga_x2p_unique_routing.c | 16 ++++++++++++++ .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp | 21 +++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/rr_blocks_utils.h | 3 +++ .../bitstream/build_routing_bitstream.cpp | 8 +++++-- .../module_builder/build_routing_modules.cpp | 3 +-- .../module_builder/build_top_module.cpp | 19 +++++++++-------- .../build_top_module_memory.cpp | 9 ++++++-- .../SRC/fpga_x2p/verilog/verilog_tcl_utils.c | 11 ++++++++-- 8 files changed, 73 insertions(+), 17 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 4385cd5f7..e8ac5a4e4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1119,6 +1119,22 @@ RRGSB build_rr_gsb(DeviceCoordinator& device_range, if (0 == rr_gsb.get_chan_width(chan_side)) { continue; } + /* For bottom side: Skip IPIN collection if the offset of the grid is not zero! + * (it means this CB is in the middle of a grid (whose height > 1) + * + * | | | | + * | | | | + * | Grid | | Grid | + * +------------+ | | + * IPIN nodes IPIN nodes + * exist do NOT exist + */ + if ((BOTTOM == ipin_rr_node_grid_side) && (0 < grid[ix][iy].offset)) { + continue; + } + if ((TOP == ipin_rr_node_grid_side) && (grid[ix][iy].offset != grid[ix][iy].type->height - 1)) { + continue; + } /* Collect IPIN rr_nodes*/ temp_ipin_rr_node = get_grid_side_pin_rr_nodes(&(num_temp_ipin_rr_nodes), IPIN, ix, iy, ipin_rr_node_grid_side, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp index 9cd735aeb..4066c3a63 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp @@ -334,4 +334,25 @@ size_t find_switch_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_in return num_shared_conf_bits; } +/******************************************************************** + * Find if a X-direction or Y-direction Connection Block contains + * routing tracks only (zero configuration bits and routing multiplexers) + *******************************************************************/ +bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb, + const t_rr_type& cb_type) { + bool routing_track_only = true; + /* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */ + std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); + + for (size_t side = 0; side < cb_sides.size(); ++side) { + enum e_side cb_ipin_side = cb_sides[side]; + Side side_manager(cb_ipin_side); + if (0 < rr_gsb.get_num_ipin_nodes(cb_ipin_side)) { + routing_track_only = false; + break; + } + } + + return routing_track_only; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h index 711517a0c..59e8639ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h @@ -51,4 +51,7 @@ size_t find_switch_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_in const std::vector& rr_switches, const RRGSB& rr_gsb); +bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb, + const t_rr_type& cb_type); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp index c650d7704..5d2c558ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp @@ -10,6 +10,7 @@ #include "vtr_assert.h" #include "util.h" #include "mux_utils.h" +#include "rr_blocks_utils.h" #include "fpga_x2p_reserved_words.h" #include "fpga_x2p_types.h" #include "fpga_x2p_naming.h" @@ -318,8 +319,11 @@ void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, * Some of them do NOT exist due to heterogeneous blocks (height > 1) * We will skip those modules */ - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { + if (false == rr_gsb.is_cb_exist(cb_type)) { + continue; + } + /* Skip if the cb does not contain any configuration bits! */ + if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) { continue; } /* Create a block for the bitstream which corresponds to the Switch block */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 04842a5cc..35fd4a296 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -1044,8 +1044,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager, * We will skip those modules */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { + if (false == rr_gsb.is_cb_exist(cb_type)) { continue; } build_connection_block_module(module_manager, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index 683b5138d..a8e3543e5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -11,6 +11,7 @@ #include "vpr_types.h" #include "globals.h" +#include "rr_blocks_utils.h" #include "fpga_x2p_reserved_words.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" @@ -311,9 +312,7 @@ std::vector> add_top_module_connection_block_instances(Modul */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - const DeviceCoordinator cb_coordinator = rr_gsb.get_cb_coordinator(cb_type); - if ( (TRUE != is_cb_exist(cb_type, cb_coordinator.get_x(), cb_coordinator.get_y())) - || (true != rr_gsb.is_cb_exist(cb_type))) { + if ( false == rr_gsb.is_cb_exist(cb_type) ) { continue; } /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ @@ -522,8 +521,12 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); /* Skip those Connection blocks that do not exist */ - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { + if (false == rr_gsb.is_cb_exist(cb_type)) { + return; + } + + /* Skip if the cb does not contain any configuration bits! */ + if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) { return; } @@ -684,16 +687,14 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, * FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist() */ if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) { - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { + if ( false == rr_gsb.is_cb_exist(cb_type)) { continue; } } if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) { const RRGSB& adjacent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); - if ( (TRUE != is_cb_exist(cb_type, adjacent_gsb.get_cb_x(cb_type), adjacent_gsb.get_cb_y(cb_type))) - || (true != adjacent_gsb.is_cb_exist(cb_type))) { + if ( false == adjacent_gsb.is_cb_exist(cb_type)) { continue; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp index e795ab7ad..4042febd7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp @@ -4,6 +4,7 @@ *******************************************************************/ #include "vtr_assert.h" +#include "rr_blocks_utils.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_naming.h" @@ -31,8 +32,12 @@ void organize_top_module_tile_cb_modules(ModuleManager& module_manager, const t_rr_type& cb_type, const bool& compact_routing_hierarchy) { /* If the CB does not exist, we can skip addition */ - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { + if ( false == rr_gsb.is_cb_exist(cb_type)) { + return; + } + + /* Skip if the cb does not contain any configuration bits! */ + if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) { return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index c3df4ed95..7fa1b51e6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -354,8 +354,11 @@ t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node, */ assert (src_rr_node->xlow == src_rr_node->xhigh); next_cb_x = src_rr_node->xlow; - assert (end_rr_node->ylow == end_rr_node->yhigh); - next_cb_y = end_rr_node->ylow; + /* Heterogeneous blocks may have ylow != yhigh */ + if (IPIN != end_rr_node->type) { + assert (end_rr_node->ylow == end_rr_node->yhigh); + } + next_cb_y = end_rr_node->yhigh; /* Side will be either on RIGHT or LEFT */ ipin_side[0] = LEFT; ipin_side[1] = RIGHT; @@ -372,6 +375,7 @@ t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node, } /* Double check if src_rr_node is in the IN_PORT list */ + /* TODO: this part should be refactored! node_exist = 0; for (iside = 0; iside < num_chan_sides; iside++) { if (OPEN != get_rr_node_index_in_cb_info( src_rr_node, @@ -381,8 +385,10 @@ t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node, } } assert (0 < node_exist); + */ /* Double check if end_rr_node is in the OUT_PORT list */ + /* TODO: this part should be refactored! node_exist = 0; for (iside = 0; iside < num_ipin_sides; iside++) { if (OPEN != get_rr_node_index_in_cb_info( end_rr_node, @@ -392,6 +398,7 @@ t_cb* get_chan_rr_node_ending_cb(t_rr_node* src_rr_node, } } assert (0 < node_exist); + */ return next_cb; } From 0e620f35a4eff1237a9ba64acb51bbf93a94d4f0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Nov 2019 11:45:28 -0700 Subject: [PATCH 441/482] bug fixed for MUX2 std cells, avoid duplicated module writing --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 06c2e1f4c..69eea6452 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -582,6 +582,13 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, /* Multiplexers built with different technology is in different organization */ switch (circuit_lib.design_tech_type(mux_model)) { case SPICE_MODEL_DESIGN_CMOS: + /* Skip module writing if the branch subckt is a standard cell! */ + if (true == circuit_lib.valid_model_id(circuit_lib.model(module_name))) { + /* This model must be a MUX2 gate */ + VTR_ASSERT(SPICE_MODEL_GATE == circuit_lib.model_type(circuit_lib.model(module_name))); + VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(circuit_lib.model(module_name))); + break; + } if (true == circuit_lib.dump_structural_verilog(mux_model)) { /* Structural verilog can be easily generated by module writer */ ModuleId mux_module = module_manager.find_module(module_name); From 09eb373a6e20dd99304d248c696ee7505fcf6c4a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Nov 2019 12:21:20 -0700 Subject: [PATCH 442/482] bug fixing for autocheck top testbench where clock port is not default names --- openfpga_flow/VerilogNetlists/dpram_32x1024.v | 56 +++++++++++++++++++ .../verilog/verilog_top_testbench.cpp | 36 ++++++++++-- 2 files changed, 87 insertions(+), 5 deletions(-) create mode 100644 openfpga_flow/VerilogNetlists/dpram_32x1024.v diff --git a/openfpga_flow/VerilogNetlists/dpram_32x1024.v b/openfpga_flow/VerilogNetlists/dpram_32x1024.v new file mode 100644 index 000000000..404548a95 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/dpram_32x1024.v @@ -0,0 +1,56 @@ +//----------------------------------------------------- +// Design Name : dual_port_ram_32x1024 +// File Name : dpram_32x1024.v +// Function : Dual port RAM 32x1024 +// Coder : Aurelien Alacchi +//----------------------------------------------------- + +module dual_port_ram_32x1024 ( + input clk, + input wen, + input ren, + input[0:9] waddr, + input[0:9] raddr, + input[0:31] d_in, + output[0:31] d_out ); + + dual_port_sram_32x1024 memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (d_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .d_out (d_out) ); + +endmodule + +module dual_port_sram_32x1024 ( + input wclk, + input wen, + input[0:9] waddr, + input[0:31] data_in, + input rclk, + input ren, + input[0:9] raddr, + output[0:31] d_out ); + + reg[0:31] ram[0:1023]; + reg[0:31] internal; + + assign d_out = internal; + + always @(negedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(negedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp index 4fcebf6c4..9f801c44a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp @@ -289,6 +289,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, const std::vector& L_logical_blocks, + const std::vector& clock_port_names, const e_sram_orgz& sram_orgz_type, const std::string& circuit_name){ /* Validate the file stream */ @@ -353,6 +354,31 @@ void print_verilog_top_testbench_ports(std::fstream& fp, /* Configuration ports depend on the organization of SRAMs */ print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type); + /* Create a clock port if the benchmark have one but not in the default name! + * We will wire the clock directly to the operating clock directly + */ + for (const std::string clock_port_name : clock_port_names) { + if (0 == clock_port_name.compare(op_clock_port.get_name())) { + continue; + } + /* Ensure the clock port name is not a duplication of global ports of the FPGA module */ + bool print_clock_port = true; + for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { + if (0 == clock_port_name.compare(module_port.get_name())) { + print_clock_port = false; + } + } + if (false == print_clock_port) { + continue; + } + + /* Print the clock and wire it to op_clock */ + print_verilog_comment(fp, std::string("----- Create a clock for benchmark and wire it to op_clock -------")); + BasicPort clock_port(clock_port_name, 1); + fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, clock_port) << ";" << std::endl; + print_verilog_wire_connection(fp, clock_port, op_clock_port, false); + } + print_verilog_testbench_shared_ports(fp, L_logical_blocks, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), @@ -753,9 +779,12 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + /* Preparation: find all the clock ports */ + std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); + /* Start of testbench */ - //dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); - print_verilog_top_testbench_ports(fp, module_manager, top_module, L_logical_blocks, + print_verilog_top_testbench_ports(fp, module_manager, top_module, + L_logical_blocks, clock_port_names, sram_orgz_type, circuit_name); /* Find the clock period */ @@ -803,9 +832,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, print_verilog_top_testbench_bitstream(fp, sram_orgz_type, bitstream_manager, fabric_bitstream); - /* Preparation: find all the clock ports */ - std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); - /* Add stimuli for reset, set, clock and iopad signals */ print_verilog_testbench_random_stimuli(fp, L_logical_blocks, std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), From 4ea5756be6a2366da98f2eb98b925a853d410e56 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Nov 2019 16:06:47 -0700 Subject: [PATCH 443/482] bug fixed for std cell MUX2 architecture and add the case to regression tests --- openfpga_flow/VerilogNetlists/mux2.v | 53 + ...10_sram_chain_HC_stdcell_mux2_template.xml | 1030 +++++++++++++++++ .../tasks/multi_mode/config/task.conf | 13 +- .../vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp | 5 +- 4 files changed, 1094 insertions(+), 7 deletions(-) create mode 100644 openfpga_flow/VerilogNetlists/mux2.v create mode 100644 openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml diff --git a/openfpga_flow/VerilogNetlists/mux2.v b/openfpga_flow/VerilogNetlists/mux2.v new file mode 100644 index 000000000..b539b7a69 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/mux2.v @@ -0,0 +1,53 @@ +//----------------------------------------------------- +// Design Name : MUX2 +// File Name : mux2.v +// Function : Standard cell (static gate) implementation +// of 2-input multiplexers +// Coder : Xifan Tang +//----------------------------------------------------- + +module MUX2( + input A, // Data input 0 + input B, // Data input 1 + input S0, // Select port + output Y // Data output + ); + + assign Y = S0 ? B : A; + +// Note: +// MUX2 appears will appear in LUTs, routing multiplexers, +// being a component in combinational loops +// To help convergence in simulation +// i.e., to avoid the X (undetermined) signals, +// the following timing constraints and signal initialization +// has to be added! + +`ifdef ENABLE_TIMING +// ------ BEGIN Pin-to-pin Timing constraints ----- + specify + (A => Y) = (0.001, 0.001); + (B => Y) = (0.001, 0.001); + (S0 => Y) = (0.001, 0.001); + endspecify +// ------ END Pin-to-pin Timing constraints ----- +`endif + +`ifdef ENABLE_SIGNAL_INITIALIZATION +// ------ BEGIN driver initialization ----- + initial begin + `ifdef ENABLE_FORMAL_VERIFICATION + $deposit(A, 1'b0); + $deposit(B, 1'b0); + $deposit(S0, 1'b0); + `else + $deposit(A, $random); + $deposit(B, $random); + $deposit(S0, $random); + `endif + + end +// ------ END driver initialization ----- +`endif + +endmodule diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml new file mode 100644 index 000000000..410edebcf --- /dev/null +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml @@ -0,0 +1,1030 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/multi_mode/config/task.conf b/openfpga_flow/tasks/multi_mode/config/task.conf index 51ff24dbd..18f471cf7 100644 --- a/openfpga_flow/tasks/multi_mode/config/task.conf +++ b/openfpga_flow/tasks/multi_mode/config/task.conf @@ -15,12 +15,13 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml -arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml -arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml -arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml -arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml +arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml +arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index 69eea6452..a52018ff3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -1192,7 +1192,10 @@ void generate_verilog_mux_module(ModuleManager& module_manager, ModuleId mux_module = module_manager.find_module(module_name); VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); write_verilog_module_to_file(fp, module_manager, mux_module, - use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model)); + ( use_explicit_port_map + || circuit_lib.dump_explicit_port_map(mux_model) + || circuit_lib.dump_explicit_port_map(circuit_lib.pass_gate_logic_model(mux_model)) ) + ); /* Add an empty line as a splitter */ fp << std::endl; break; From 56b4ee008e2a57b00aa6986a125960247af66f80 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Nov 2019 17:45:11 -0700 Subject: [PATCH 444/482] add test for heterogeneous FPGA and fix bugs --- .../{dpram_32x1024.v => dpram.v} | 0 .../k6_N10_sram_chain_HC_DPRAM_template.xml | 32 ++--- .../pipelined_8bit_adder.act | 95 +++++++++++++ .../pipelined_8bit_adder.blif | 126 ++++++++++++++++++ .../pipelined_8bit_adder.v | 99 ++++++++++++++ .../heterogeneous_dpram/config/task.conf | 43 ++++++ .../base/fpga_x2p_backannotate_utils.c | 4 + 7 files changed, 383 insertions(+), 16 deletions(-) rename openfpga_flow/VerilogNetlists/{dpram_32x1024.v => dpram.v} (100%) create mode 100644 openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act create mode 100644 openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif create mode 100644 openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v create mode 100644 openfpga_flow/tasks/heterogeneous_dpram/config/task.conf diff --git a/openfpga_flow/VerilogNetlists/dpram_32x1024.v b/openfpga_flow/VerilogNetlists/dpram.v similarity index 100% rename from openfpga_flow/VerilogNetlists/dpram_32x1024.v rename to openfpga_flow/VerilogNetlists/dpram.v diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml index 10cd18ddd..103152e31 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -146,7 +146,7 @@ - + @@ -163,8 +163,8 @@ - - + + @@ -344,14 +344,14 @@ - + - - + + @@ -386,17 +386,17 @@ - + - + - + @@ -421,7 +421,7 @@ - + @@ -613,7 +613,7 @@ - + @@ -631,7 +631,7 @@ - + @@ -674,13 +674,13 @@ - - + memory_dp.d_in - memory_dp.clk memory_dp.wen memory_dp.waddr + memory_dp.clk memory_dp.wen memory_dp.waddr memory_dp.d_out memory_dp.ren memory_dp.raddr - + diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act new file mode 100644 index 000000000..d8c59ec70 --- /dev/null +++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act @@ -0,0 +1,95 @@ +clk 0.5 0.2 +wen 0.5 0.2 +wen_st0 0.5 0.2 +wen_st1 0.5 0.2 +ren 0.5 0.2 +raddr_0_ 0.5 0.2 +raddr_1_ 0.5 0.2 +raddr_2_ 0.5 0.2 +raddr_3_ 0.5 0.2 +raddr_4_ 0.5 0.2 +raddr_5_ 0.5 0.2 +waddr_0_ 0.5 0.2 +waddr_1_ 0.5 0.2 +waddr_2_ 0.5 0.2 +waddr_3_ 0.5 0.2 +waddr_4_ 0.5 0.2 +waddr_5_ 0.5 0.2 +waddr_st0_0_ 0.5 0.2 +waddr_st0_1_ 0.5 0.2 +waddr_st0_2_ 0.5 0.2 +waddr_st0_3_ 0.5 0.2 +waddr_st0_4_ 0.5 0.2 +waddr_st0_5_ 0.5 0.2 +waddr_st1_0_ 0.5 0.2 +waddr_st1_1_ 0.5 0.2 +waddr_st1_2_ 0.5 0.2 +waddr_st1_3_ 0.5 0.2 +waddr_st1_4_ 0.5 0.2 +waddr_st1_5_ 0.5 0.2 +a_0_ 0.5 0.2 +a_1_ 0.5 0.2 +a_2_ 0.5 0.2 +a_3_ 0.5 0.2 +a_4_ 0.5 0.2 +a_5_ 0.5 0.2 +a_6_ 0.5 0.2 +a_st0_0_ 0.5 0.2 +a_st0_1_ 0.5 0.2 +a_st0_2_ 0.5 0.2 +a_st0_3_ 0.5 0.2 +a_st0_4_ 0.5 0.2 +a_st0_5_ 0.5 0.2 +a_st0_6_ 0.5 0.2 +a_st1_0_ 0.5 0.2 +a_st1_1_ 0.5 0.2 +a_st1_2_ 0.5 0.2 +a_st1_3_ 0.5 0.2 +a_st1_4_ 0.5 0.2 +a_st1_5_ 0.5 0.2 +a_st1_6_ 0.5 0.2 +b_0_ 0.5 0.2 +b_1_ 0.5 0.2 +b_2_ 0.5 0.2 +b_3_ 0.5 0.2 +b_4_ 0.5 0.2 +b_5_ 0.5 0.2 +b_6_ 0.5 0.2 +b_st0_0_ 0.5 0.2 +b_st0_1_ 0.5 0.2 +b_st0_2_ 0.5 0.2 +b_st0_3_ 0.5 0.2 +b_st0_4_ 0.5 0.2 +b_st0_5_ 0.5 0.2 +b_st0_6_ 0.5 0.2 +b_st1_0_ 0.5 0.2 +b_st1_1_ 0.5 0.2 +b_st1_2_ 0.5 0.2 +b_st1_3_ 0.5 0.2 +b_st1_4_ 0.5 0.2 +b_st1_5_ 0.5 0.2 +b_st1_6_ 0.5 0.2 +q_0_ 0.5 0.2 +q_1_ 0.5 0.2 +q_2_ 0.5 0.2 +q_3_ 0.5 0.2 +q_4_ 0.5 0.2 +q_5_ 0.5 0.2 +q_6_ 0.5 0.2 +q_7_ 0.5 0.2 +AplusB_0_ 0.5 0.2 +AplusB_1_ 0.5 0.2 +AplusB_2_ 0.5 0.2 +AplusB_3_ 0.5 0.2 +AplusB_4_ 0.5 0.2 +AplusB_5_ 0.5 0.2 +AplusB_6_ 0.5 0.2 +AplusB_7_ 0.5 0.2 +cint01 0.5 0.2 +cint02 0.5 0.2 +cint03 0.5 0.2 +cint04 0.5 0.2 +cint05 0.5 0.2 +cint06 0.5 0.2 +cint07 0.5 0.2 +zero00 0 0 diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif new file mode 100644 index 000000000..4ec6b2a99 --- /dev/null +++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif @@ -0,0 +1,126 @@ +# Benchmark pipelined_32b_adder +.model pipelined_32b_adder +.inputs clk wen ren raddr_0_ raddr_1_ raddr_2_ raddr_3_ raddr_4_ raddr_5_ waddr_0_ waddr_1_ waddr_2_ waddr_3_ waddr_4_ waddr_5_ a_0_ a_1_ a_2_ a_3_ a_4_ a_5_ a_6_ b_0_ b_1_ b_2_ b_3_ b_4_ b_5_ b_6_ +.outputs q_0_ q_1_ q_2_ q_3_ q_4_ q_5_ q_6_ q_7_ + +# Start pipeline +# Pipeline a +.subckt shift D=a_0_ clk=clk Q=a_st0_0_ +.subckt shift D=a_st0_0_ clk=clk Q=a_st1_0_ +.subckt shift D=a_1_ clk=clk Q=a_st0_1_ +.subckt shift D=a_st0_1_ clk=clk Q=a_st1_1_ +.subckt shift D=a_2_ clk=clk Q=a_st0_2_ +.subckt shift D=a_st0_2_ clk=clk Q=a_st1_2_ +.subckt shift D=a_3_ clk=clk Q=a_st0_3_ +.subckt shift D=a_st0_3_ clk=clk Q=a_st1_3_ +.subckt shift D=a_4_ clk=clk Q=a_st0_4_ +.subckt shift D=a_st0_4_ clk=clk Q=a_st1_4_ +.subckt shift D=a_5_ clk=clk Q=a_st0_5_ +.subckt shift D=a_st0_5_ clk=clk Q=a_st1_5_ +.subckt shift D=a_6_ clk=clk Q=a_st0_6_ +.subckt shift D=a_st0_6_ clk=clk Q=a_st1_6_ + +# Pipeline b +.subckt shift D=b_0_ clk=clk Q=b_st0_0_ +.subckt shift D=b_st0_0_ clk=clk Q=b_st1_0_ +.subckt shift D=b_1_ clk=clk Q=b_st0_1_ +.subckt shift D=b_st0_1_ clk=clk Q=b_st1_1_ +.subckt shift D=b_2_ clk=clk Q=b_st0_2_ +.subckt shift D=b_st0_2_ clk=clk Q=b_st1_2_ +.subckt shift D=b_3_ clk=clk Q=b_st0_3_ +.subckt shift D=b_st0_3_ clk=clk Q=b_st1_3_ +.subckt shift D=b_4_ clk=clk Q=b_st0_4_ +.subckt shift D=b_st0_4_ clk=clk Q=b_st1_4_ +.subckt shift D=b_5_ clk=clk Q=b_st0_5_ +.subckt shift D=b_st0_5_ clk=clk Q=b_st1_5_ +.subckt shift D=b_6_ clk=clk Q=b_st0_6_ +.subckt shift D=b_st0_6_ clk=clk Q=b_st1_6_ + +# Pipeline waddr +.subckt shift D=waddr_0_ clk=clk Q=waddr_st0_0_ +.subckt shift D=waddr_st0_0_ clk=clk Q=waddr_st1_0_ +.subckt shift D=waddr_1_ clk=clk Q=waddr_st0_1_ +.subckt shift D=waddr_st0_1_ clk=clk Q=waddr_st1_1_ +.subckt shift D=waddr_2_ clk=clk Q=waddr_st0_2_ +.subckt shift D=waddr_st0_2_ clk=clk Q=waddr_st1_2_ +.subckt shift D=waddr_3_ clk=clk Q=waddr_st0_3_ +.subckt shift D=waddr_st0_3_ clk=clk Q=waddr_st1_3_ +.subckt shift D=waddr_4_ clk=clk Q=waddr_st0_4_ +.subckt shift D=waddr_st0_4_ clk=clk Q=waddr_st1_4_ +.subckt shift D=waddr_5_ clk=clk Q=waddr_st0_5_ +.subckt shift D=waddr_st0_5_ clk=clk Q=waddr_st1_5_ +# Pipeline wen +.subckt shift D=wen clk=clk Q=wen_st0 +.subckt shift D=wen_st0 clk=clk Q=wen_st1 +# End pipeline + +# Start adder +.subckt adder a=a_st1_0_ b=b_st1_0_ cin=zero00 cout=cint01 sumout=AplusB_0_ +.subckt adder a=a_st1_1_ b=b_st1_1_ cin=cint01 cout=cint02 sumout=AplusB_1_ +.subckt adder a=a_st1_2_ b=b_st1_2_ cin=cint02 cout=cint03 sumout=AplusB_2_ +.subckt adder a=a_st1_3_ b=b_st1_3_ cin=cint03 cout=cint04 sumout=AplusB_3_ +.subckt adder a=a_st1_4_ b=b_st1_4_ cin=cint04 cout=cint05 sumout=AplusB_4_ +.subckt adder a=a_st1_5_ b=b_st1_5_ cin=cint05 cout=cint06 sumout=AplusB_5_ +.subckt adder a=a_st1_6_ b=b_st1_6_ cin=cint06 cout=cint07 sumout=AplusB_6_ +.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB_7_ +# End adder + +# Start DPRAM +.subckt dual_port_ram_32x1024 clk=clk wen=wen_st1 ren=ren \ +waddr[0]=waddr_st1_0_ waddr[1]=waddr_st1_1_ waddr[2]=waddr_st1_2_ waddr[3]=waddr_st1_3_ waddr[4]=waddr_st1_4_ \ +waddr[5]=waddr_st1_5_ waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 \ +raddr[0]=raddr_0_ raddr[1]=raddr_1_ raddr[2]=raddr_2_ raddr[3]=raddr_3_ raddr[4]=raddr_4_ raddr[5]=raddr_5_ \ +raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 \ +d_in[0]=AplusB_0_ d_in[1]=AplusB_1_ d_in[2]=AplusB_2_ d_in[3]=AplusB_3_ d_in[4]=AplusB_4_ d_in[5]=AplusB_5_ \ +d_in[6]=AplusB_6_ d_in[7]=AplusB_7_ d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \ +d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \ +d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \ +d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \ +d_in[30]=zero00 d_in[31]=zero00 \ +d_out[0]=q_0_ d_out[1]=q_1_ d_out[2]=q_2_ d_out[3]=q_3_ d_out[4]=q_4_ d_out[5]=q_5_ \ +d_out[6]=q_6_ d_out[7]=q_7_ d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \ +d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \ +d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \ +d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \ +d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn +# End DPRAM + +# Start global variable +.names zero00 +0 +# End global variable + + +.end + +# Start blackbox definition +.model dual_port_ram_32x1024 +.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ + waddr[6] waddr[7] waddr[8] raddr[0] raddr[1] raddr[2] \ + raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] \ + d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ + d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \ + d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \ + d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] +.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \ + d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \ + d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \ + d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \ + d_out[28] d_out[29] d_out[30] d_out[31] +.blackbox +.end + + +.model adder +.inputs a b cin +.outputs cout sumout +.blackbox +.end + + +.model shift +.inputs D clk +.outputs Q +.blackbox +.end +# End blackbox definition diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v new file mode 100644 index 000000000..549ef735a --- /dev/null +++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v @@ -0,0 +1,99 @@ +// // +// ERI summit demo-benchmark // +// pipelined_8b_adder.v // +// by Aurelien // +// // +///////////////////////////////////// +//----------------------------------------------------- +// Design Name : pipelined_8bit_adder +// File Name : pipelined_8bit_adder.v +// Function : Pipelined 8-bit adders, whose sum and carry outputs +// are cached in a memory +// Coder : Aurelien Alacchi +//----------------------------------------------------- + +`timescale 1 ns/ 1 ps + +// To match the port definition in BLIF format, so that we can do verification +// Each input/output bus is expanded here. +// In future, we should be able to support buses in verification! + +module pipelined_8bit_adder( + input clk, + input ren, + input wen, + input raddr_0_, + input raddr_1_, + input raddr_2_, + input raddr_3_, + input raddr_4_, + input raddr_5_, + input waddr_0_, + input waddr_1_, + input waddr_2_, + input waddr_3_, + input waddr_4_, + input waddr_5_, + input a_0_, + input a_1_, + input a_2_, + input a_3_, + input a_4_, + input a_5_, + input a_6_, + input b_0_, + input b_1_, + input b_2_, + input b_3_, + input b_4_, + input b_5_, + input b_6_, + output q_0_, + output q_1_, + output q_2_, + output q_3_, + output q_4_, + output q_5_, + output q_6_, + output q_7_); + + wire [5:0] raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ }; + wire [5:0] waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ }; + wire [6:0] a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ }; + wire [6:0] b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ }; + wire [7:0] q = { q_7_, q_6_, q_5_, q_4_, q_3_, q_2_, q_1_, q_0_ }; + + reg[7:0] ram[63:0]; + reg[6:0] a_st0; + reg[6:0] a_st1; + reg[6:0] b_st0; + reg[6:0] b_st1; + reg[8:0] waddr_st0; + reg[8:0] waddr_st1; + reg wen_st0; + reg wen_st1; + reg[7:0] q_int; + + wire[7:0] AplusB; + + assign AplusB = a_st1 + b_st1; + assign q = q_int; + + always@(posedge clk) begin + waddr_st0 <= waddr; + waddr_st1 <= waddr_st0; + a_st0 <= a; + a_st1 <= a_st0; + b_st0 <= b; + b_st1 <= b_st0; + wen_st0 <= wen; + wen_st1 <= wen_st0; + if(wen_st1) begin + ram[waddr_st1] <= AplusB; + end + if(ren) begin + q_int <= ram[raddr]; + end + end + +endmodule diff --git a/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf b/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf new file mode 100644 index 000000000..b567b74e0 --- /dev/null +++ b/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif + +[SYNTHESIS_PARAM] +bench0_top = pipelined_8bit_adder +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v +bench0_chan_width = 100 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +min_route_chan_width=1.3 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +#vpr_fpga_verilog_print_user_defined_template= +#vpr_fpga_verilog_print_report_timing_tcl= +#vpr_fpga_verilog_print_sdc_pnr= +#vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_verilog_explicit_mapping= +vpr_fpga_x2p_compact_routing_hierarchy= +end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c index b8e8e8112..5b7abd0bb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c @@ -1480,6 +1480,10 @@ void update_one_grid_pack_net_num(int x, int y) { assert ((NULL != type) && (EMPTY_TYPE != type) && (IO_TYPE != type)); + /* Bypass grids whose offset is larger than 0 ! They have been processed! */ + if (0 < grid[x][y].offset) { + return; + } for (iblk = 0; iblk < grid[x][y].usage; iblk++) { blk_id = grid[x][y].blocks[iblk]; From d391983e8c0127ed794c4dde4ab012682e73264e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 7 Nov 2019 14:57:46 -0700 Subject: [PATCH 445/482] passing regression test on dpram benchmarks --- openfpga_flow/VerilogNetlists/dpram.v | 26 +- .../k6_N10_sram_chain_HC_DPRAM_template.xml | 48 ++-- .../pipelined_8bit_adder.blif | 6 +- .../pipelined_8bit_adder.v | 30 +- ...ipelined_8bit_adder_formal_random_top_tb.v | 267 ++++++++++++++++++ 5 files changed, 326 insertions(+), 51 deletions(-) create mode 100644 openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v diff --git a/openfpga_flow/VerilogNetlists/dpram.v b/openfpga_flow/VerilogNetlists/dpram.v index 404548a95..45bdbecc0 100644 --- a/openfpga_flow/VerilogNetlists/dpram.v +++ b/openfpga_flow/VerilogNetlists/dpram.v @@ -1,20 +1,20 @@ //----------------------------------------------------- -// Design Name : dual_port_ram_32x1024 -// File Name : dpram_32x1024.v -// Function : Dual port RAM 32x1024 +// Design Name : dual_port_ram_32x512 +// File Name : dpram.v +// Function : Dual port RAM 32x512 // Coder : Aurelien Alacchi //----------------------------------------------------- -module dual_port_ram_32x1024 ( +module dual_port_ram_32x512 ( input clk, input wen, input ren, - input[0:9] waddr, - input[0:9] raddr, + input[0:8] waddr, + input[0:8] raddr, input[0:31] d_in, output[0:31] d_out ); - dual_port_sram_32x1024 memory_0 ( + dual_port_sram_32x512 memory_0 ( .wclk (clk), .wen (wen), .waddr (waddr), @@ -26,28 +26,28 @@ module dual_port_ram_32x1024 ( endmodule -module dual_port_sram_32x1024 ( +module dual_port_sram_32x512 ( input wclk, input wen, - input[0:9] waddr, + input[0:8] waddr, input[0:31] data_in, input rclk, input ren, - input[0:9] raddr, + input[0:8] raddr, output[0:31] d_out ); - reg[0:31] ram[0:1023]; + reg[0:31] ram[0:511]; reg[0:31] internal; assign d_out = internal; - always @(negedge wclk) begin + always @(posedge wclk) begin if(wen) begin ram[waddr] <= data_in; end end - always @(negedge rclk) begin + always @(posedge rclk) begin if(ren) begin internal <= ram[raddr]; end diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml index 103152e31..b053a80cd 100644 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -146,7 +146,7 @@ - + @@ -421,16 +421,16 @@ - + - - - + + + - + @@ -615,29 +615,29 @@ - - - + + + - + - - - + + + - + - - - - + + + + - - + + @@ -647,8 +647,8 @@ - - + + @@ -656,8 +656,8 @@ - - + + diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif index 4ec6b2a99..a76ccdef5 100644 --- a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif +++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif @@ -66,7 +66,7 @@ # End adder # Start DPRAM -.subckt dual_port_ram_32x1024 clk=clk wen=wen_st1 ren=ren \ +.subckt dual_port_ram_32x512 clk=clk wen=wen_st1 ren=ren \ waddr[0]=waddr_st1_0_ waddr[1]=waddr_st1_1_ waddr[2]=waddr_st1_2_ waddr[3]=waddr_st1_3_ waddr[4]=waddr_st1_4_ \ waddr[5]=waddr_st1_5_ waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 \ raddr[0]=raddr_0_ raddr[1]=raddr_1_ raddr[2]=raddr_2_ raddr[3]=raddr_3_ raddr[4]=raddr_4_ raddr[5]=raddr_5_ \ @@ -94,8 +94,8 @@ d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=un .end # Start blackbox definition -.model dual_port_ram_32x1024 -.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ +.model dual_port_ram_32x512 +.inputs clk ren wen waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ waddr[6] waddr[7] waddr[8] raddr[0] raddr[1] raddr[2] \ raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] \ d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v index 549ef735a..c963eb22f 100644 --- a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v +++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v @@ -1,9 +1,3 @@ -// // -// ERI summit demo-benchmark // -// pipelined_8b_adder.v // -// by Aurelien // -// // -///////////////////////////////////// //----------------------------------------------------- // Design Name : pipelined_8bit_adder // File Name : pipelined_8bit_adder.v @@ -57,11 +51,25 @@ module pipelined_8bit_adder( output q_6_, output q_7_); - wire [5:0] raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ }; - wire [5:0] waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ }; - wire [6:0] a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ }; - wire [6:0] b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ }; - wire [7:0] q = { q_7_, q_6_, q_5_, q_4_, q_3_, q_2_, q_1_, q_0_ }; + wire [5:0] raddr; + wire [5:0] waddr; + wire [6:0] a; + wire [6:0] b; + wire [7:0] q; + + + assign raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ }; + assign waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ }; + assign a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ }; + assign b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ }; + assign q_7_ = q[7]; + assign q_6_ = q[6]; + assign q_5_ = q[5]; + assign q_4_ = q[4]; + assign q_3_ = q[3]; + assign q_2_ = q[2]; + assign q_1_ = q[1]; + assign q_0_ = q[0]; reg[7:0] ram[63:0]; reg[6:0] a_st0; diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v new file mode 100644 index 000000000..4276260c2 --- /dev/null +++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v @@ -0,0 +1,267 @@ +//----------------------------------------------------- +// Design Name : pipelined_8bit_adder_top_formal_verification_random_tb +// File Name : pipelined_8bit_adder.v +// Function : Testbench for pipelined 8-bit adders, whose sum and carry outputs +// are cached in a dual-port memory. +// This testbench will do a verification of FPGA implementation +// of the pipelined 8-bit adders against the reference +// (original) Verilog netlist +// To provide a practical testing, this testbench will : +// - Instantiate a pre-programmed FPGA and the proper +// benchmark +// - Load memories with random values +// - Randomly write and read from the memories +// - Watch for any difference between FPGA and Benchmark +// outputs, after memories are fully loaded +// +// PLEASE USE this testbench instead of the auto-generated test +// benches when performing verification! +// Coder : Aurelien Alacchi and Xifan Tang +//----------------------------------------------------- + +`timescale 1 ns/ 100 ps + +module pipelined_8bit_adder_top_formal_verification_random_tb(); + reg clk; + reg[5:0] raddr; + reg[5:0] waddr; + reg ren; + reg wen; + reg[6:0] a; + reg[6:0] b; + wire[7:0] q_gfpga; + wire[7:0] q_bench; + reg[7:0] q_flag; + + pipelined_8bit_adder_top_formal_verification DUT( + .clk_fm (clk), + .ren_fm (ren), + .wen_fm (wen), + .raddr_0__fm (raddr[0]), + .raddr_1__fm (raddr[1]), + .raddr_2__fm (raddr[2]), + .raddr_3__fm (raddr[3]), + .raddr_4__fm (raddr[4]), + .raddr_5__fm (raddr[5]), + .waddr_0__fm (waddr[0]), + .waddr_1__fm (waddr[1]), + .waddr_2__fm (waddr[2]), + .waddr_3__fm (waddr[3]), + .waddr_4__fm (waddr[4]), + .waddr_5__fm (waddr[5]), + .a_0__fm (a[0]), + .a_1__fm (a[1]), + .a_2__fm (a[2]), + .a_3__fm (a[3]), + .a_4__fm (a[4]), + .a_5__fm (a[5]), + .a_6__fm (a[6]), + .b_0__fm (b[0]), + .b_1__fm (b[1]), + .b_2__fm (b[2]), + .b_3__fm (b[3]), + .b_4__fm (b[4]), + .b_5__fm (b[5]), + .b_6__fm (b[6]), + .out_q_0__fm (q_gfpga[0]), + .out_q_1__fm (q_gfpga[1]), + .out_q_2__fm (q_gfpga[2]), + .out_q_3__fm (q_gfpga[3]), + .out_q_4__fm (q_gfpga[4]), + .out_q_5__fm (q_gfpga[5]), + .out_q_6__fm (q_gfpga[6]), + .out_q_7__fm (q_gfpga[7]) + ); + + pipelined_8bit_adder ref0( + .clk (clk), + .ren (ren), + .wen (wen), + .raddr_0_ (raddr[0]), + .raddr_1_ (raddr[1]), + .raddr_2_ (raddr[2]), + .raddr_3_ (raddr[3]), + .raddr_4_ (raddr[4]), + .raddr_5_ (raddr[5]), + .waddr_0_ (waddr[0]), + .waddr_1_ (waddr[1]), + .waddr_2_ (waddr[2]), + .waddr_3_ (waddr[3]), + .waddr_4_ (waddr[4]), + .waddr_5_ (waddr[5]), + .a_0_ (a[0]), + .a_1_ (a[1]), + .a_2_ (a[2]), + .a_3_ (a[3]), + .a_4_ (a[4]), + .a_5_ (a[5]), + .a_6_ (a[6]), + .b_0_ (b[0]), + .b_1_ (b[1]), + .b_2_ (b[2]), + .b_3_ (b[3]), + .b_4_ (b[4]), + .b_5_ (b[5]), + .b_6_ (b[6]), + .q_0_ (q_bench[0]), + .q_1_ (q_bench[1]), + .q_2_ (q_bench[2]), + .q_3_ (q_bench[3]), + .q_4_ (q_bench[4]), + .q_5_ (q_bench[5]), + .q_6_ (q_bench[6]), + .q_7_ (q_bench[7]) + ); + + integer nb_error = 0; + integer count = 0; + integer lim_max = 64 - 1; + integer write_complete = 0; + +//----- Initialization + initial begin + clk <= 1'b0; + a <= 7'h00; + b <= 7'h00; + wen <= 1'b0; + ren <= 1'b0; + waddr <= 6'h00; + raddr <= 6'h00; + while(1) begin + #2.5 + clk <= !clk; + end + end + +//----- Input Stimulis + always@(negedge clk) begin + if(write_complete == 0) begin + wen <= 1'b1; + ren <= 1'b0; + count <= count + 1; + waddr <= waddr + 1; + if(count == lim_max) begin + write_complete = 1; + end + end else begin + wen <= $random; + ren <= $random; + waddr <= $random; + raddr <= $random; + end + a <= $random; + b <= $random; + end + + + always@(negedge clk) begin + if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin + q_flag[0] <= 1'b1; + end else begin + q_flag[0] <= 1'b0; + end + if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin + q_flag[1] <= 1'b1; + end else begin + q_flag[1] <= 1'b0; + end + if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin + q_flag[2] <= 1'b1; + end else begin + q_flag[2] <= 1'b0; + end + if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin + q_flag[3] <= 1'b1; + end else begin + q_flag[3] <= 1'b0; + end + if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin + q_flag[4] <= 1'b1; + end else begin + q_flag[4] <= 1'b0; + end + if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin + q_flag[5] <= 1'b1; + end else begin + q_flag[5] <= 1'b0; + end + if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin + q_flag[6] <= 1'b1; + end else begin + q_flag[6] <= 1'b0; + end + if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin + q_flag[7] <= 1'b1; + end else begin + q_flag[7] <= 1'b0; + end + end + + + always@(posedge q_flag[0]) begin + if(q_flag[0]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[0] at time = %t", $realtime); + end + end + always@(posedge q_flag[1]) begin + if(q_flag[1]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[1] at time = %t", $realtime); + end + end + always@(posedge q_flag[2]) begin + if(q_flag[2]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[2] at time = %t", $realtime); + end + end + always@(posedge q_flag[3]) begin + if(q_flag[3]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[3] at time = %t", $realtime); + end + end + always@(posedge q_flag[4]) begin + if(q_flag[4]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[4] at time = %t", $realtime); + end + end + always@(posedge q_flag[5]) begin + if(q_flag[5]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[5] at time = %t", $realtime); + end + end + always@(posedge q_flag[6]) begin + if(q_flag[6]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[6] at time = %t", $realtime); + end + end + always@(posedge q_flag[7]) begin + if(q_flag[7]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[7] at time = %t", $realtime); + end + end + + initial begin + $dumpfile("pipelined_8bit_adder_formal.vcd"); + $dumpvars(1, pipelined_8bit_adder_top_formal_verification_random_tb); + end + + initial begin + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); + #1500 // Can be changed by the user for his need + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; + end + +endmodule From 14e7744feea229468d1f8e37d7fded6811ecf981 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 7 Nov 2019 22:20:48 -0700 Subject: [PATCH 446/482] start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 25 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 2 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 65 ------- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp | 135 +++++++++++++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 18 +- .../vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp | 158 ++++++++++++++++++ .../vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h | 15 ++ vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp | 34 ++++ vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h | 13 ++ vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp | 92 ++++++++++ vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h | 43 +++++ .../vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h | 10 ++ .../vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp | 52 ++++++ .../vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h | 13 ++ .../fpga_x2p/verilog/verilog_writer_utils.cpp | 2 +- 15 files changed, 606 insertions(+), 71 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 4665bc0bb..966a8cb5d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -24,9 +24,11 @@ /* Include spice support headers*/ #include "linkedlist.h" +#include "circuit_library_utils.h" #include "fpga_x2p_utils.h" #include "fpga_x2p_backannotate_utils.h" #include "fpga_x2p_setup.h" +#include "fpga_x2p_naming.h" #include "mux_library_builder.h" #include "build_device_module.h" @@ -36,6 +38,7 @@ #include "spice_api.h" #include "verilog_api.h" +#include "sdc_api.h" #include "fpga_bitstream.h" #include "fpga_x2p_reserved_words.h" @@ -139,6 +142,28 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); } + + /* Run SDC Generator */ + std::string src_dir = find_path_dir_name(std::string(vpr_setup.FileNameOpts.CircuitName)); + + /* Use current directory if there is not dir path given */ + if (true == src_dir.empty()) { + src_dir = std::string("./"); + } else { + src_dir = format_dir_path(src_dir); + } + SdcOption sdc_options(format_dir_path(src_dir + std::string(FPGA_X2P_DEFAULT_SDC_DIR))); + sdc_options.set_generate_sdc_pnr(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr); + sdc_options.set_generate_sdc_analysis(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis); + + if (true == sdc_options.generate_sdc()) { + std::vector global_ports = find_circuit_library_global_ports(Arch.spice->circuit_lib); + /* TODO: the critical path delay unit should be explicit! */ + fpga_sdc_generator(sdc_options, + Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, + Arch.spice->circuit_lib, global_ports); + } + /* Xifan Tang: Bitstream Generator */ if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index ece002039..56f3c627d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -13,6 +13,8 @@ #include "circuit_library.h" #include "vpr_types.h" +constexpr char* FPGA_X2P_DEFAULT_SDC_DIR = "SDC"; + std::string generate_mux_node_name(const size_t& node_level, const bool& add_buffer_postfix); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 9f73bc651..e61a4defb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -85,26 +85,6 @@ char* format_dir_path(char* dir_path) { return ret; } -/************************************************ - * Format a path of directory: - * 1. Replace "\" with "/" - * 2. add a "/" if the string does not end with a "/" - ***********************************************/ -std::string format_dir_path(const std::string& dir_path) { - std::string ret = dir_path; - - /* Replace "\" with "/" */ - std::replace(ret.begin(), ret.end(), '\\', '/'); - - /* Complete the string with a "/" if it does not end with that */ - if ('/' != ret.back()) { - ret.push_back('/'); - } - - return ret; -} - - int try_access_file(char* file_path) { /* F_OK checks existence and also R_OK, W_OK, X_OK, * for readable, writable, excutable @@ -251,18 +231,6 @@ char* chomp_file_name_postfix(char* file_name) { return ret; } -void check_file_handler(std::fstream& fp) { - /* Make sure we have a valid file handler*/ - /* Print out debugging information for if the file is not opened/created properly */ - if (!fp.is_open() || !fp.good()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create file!\n", - __FILE__, __LINE__); - exit(1); - } -} - - /* Print SRAM bits, typically in a comment line */ void fprint_commented_sram_bits(FILE* fp, int num_sram_bits, int* sram_bits) { @@ -633,21 +601,6 @@ char* my_ito1hot(int in_int, int bin_len) { return ret; } -/* Convert an integer to an one-hot encoding integer array */ -std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len) { - /* Make sure we do not have any overflow! */ - VTR_ASSERT ( (in_int <= bin_len) ); - - /* Initialize */ - std::vector ret(bin_len, 0); - - if (bin_len == in_int) { - return ret; /* all zero case */ - } - ret[in_int] = 1; /* Keep a good sequence of bits */ - - return ret; -} /* Converter an integer to a binary string */ int* my_itobin_int(int in_int, int bin_len) { @@ -669,24 +622,6 @@ int* my_itobin_int(int in_int, int bin_len) { return ret; } -/* Converter an integer to a binary vector */ -std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len) { - std::vector ret(bin_len, 0); - - /* Make sure we do not have any overflow! */ - VTR_ASSERT ( (in_int < pow(2., bin_len)) ); - - size_t temp = in_int; - for (size_t i = 0; i < bin_len; i++) { - if (1 == temp % 2) { - ret[i] = 1; /* Keep a good sequence of bits */ - } - temp = temp / 2; - } - - return ret; -} - /* Converter an integer to a binary string */ char* my_itobin(int in_int, int bin_len) { char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp new file mode 100644 index 000000000..1f49526f0 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp @@ -0,0 +1,135 @@ +/******************************************************************** + * Most utilized functions in FPGA X2P framework + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "fpga_x2p_utils.h" + +/******************************************************************** + * Format a directory path: + * 1. Replace "\" with "/" + * 2. add a "/" if the string does not end with a "/" + *******************************************************************/ +std::string format_dir_path(const std::string& dir_path_to_format) { + std::string formatted_dir_path = dir_path_to_format; + + char illegal_back_slash = '\\'; + char legal_back_slash = '/'; + +#ifdef _WIN32 +/* For windows OS, replace any '/' with '\' */ + char illegal_back_slash = '/'; + char legal_back_slash = '\\'; +#endif + + /* Replace "\" with "/" */ + std::replace(formatted_dir_path.begin(), formatted_dir_path.end(), illegal_back_slash, legal_back_slash); + + /* Add a back slash the string is not ended like this! */ + if (legal_back_slash != formatted_dir_path.back()) { + formatted_dir_path.push_back(legal_back_slash); + } + + return formatted_dir_path; +} + +/******************************************************************** + * Extract full file name from a full path of file + * For example: / + * This function will return + ********************************************************************/ +std::string find_path_file_name(const std::string& file_name) { + + char back_slash = '/'; + +#ifdef _WIN32 +/* For windows OS, replace any '/' with '\' */ + char back_slash = '\\'; +#endif + + /* Find the last '/' in the string and return the left part */ + size_t found = file_name.rfind(back_slash); + if (found != std::string::npos) { + return file_name.substr(found + 1); + } + /* Not found, return an empty string */ + return std::string(); +} + +/******************************************************************** + * Extract full directory path from a full path of file + * For example: / + * This function will return + ********************************************************************/ +std::string find_path_dir_name(const std::string& file_name) { + + char back_slash = '/'; + +#ifdef _WIN32 +/* For windows OS, replace any '/' with '\' */ + char back_slash = '\\'; +#endif + + /* Find the last '/' in the string and return the left part */ + size_t found = file_name.rfind(back_slash); + if (found != std::string::npos) { + return file_name.substr(0, found); + } + /* Not found, return an empty string */ + return std::string(); +} + +/******************************************************************** + * Check if the file stream is valid + ********************************************************************/ +void check_file_handler(std::fstream& fp) { + /* Make sure we have a valid file handler*/ + /* Print out debugging information for if the file is not opened/created properly */ + if (!fp.is_open() || !fp.good()) { + vpr_printf(TIO_MESSAGE_ERROR, + "(FILE:%s,LINE[%d])Failure in create file!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * Convert an integer to an one-hot encoding integer array + ********************************************************************/ +std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len) { + /* Make sure we do not have any overflow! */ + VTR_ASSERT ( (in_int <= bin_len) ); + + /* Initialize */ + std::vector ret(bin_len, 0); + + if (bin_len == in_int) { + return ret; /* all zero case */ + } + ret[in_int] = 1; /* Keep a good sequence of bits */ + + return ret; +} + +/******************************************************************** + * Converter an integer to a binary vector + ********************************************************************/ +std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len) { + std::vector ret(bin_len, 0); + + /* Make sure we do not have any overflow! */ + VTR_ASSERT ( (in_int < pow(2., bin_len)) ); + + size_t temp = in_int; + for (size_t i = 0; i < bin_len; i++) { + if (1 == temp % 2) { + ret[i] = 1; /* Keep a good sequence of bits */ + } + temp = temp / 2; + } + + return ret; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index 114d2d604..4ad93fc2b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -3,16 +3,28 @@ #include #include +#include #include "my_free_fwd.h" #include "rr_blocks_naming.h" +std::string format_dir_path(const std::string& dir_path_to_format); + void check_file_handler(std::fstream& fp); +std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len); + +std::string find_path_dir_name(const std::string& file_name); + +std::string find_path_file_name(const std::string& file_name); + +std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len); + +/* Old functions */ + char* my_gettime(); char* format_dir_path(char* dir_path); /* TODO: TO BE REMOVED !!! */ -std::string format_dir_path(const std::string& dir_path); int try_access_file(char* file_path); @@ -66,14 +78,10 @@ t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, char* my_ito1hot(int in_int, int bin_len); -std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len); - char* my_itobin(int in_int, int bin_len); int* my_itobin_int(int in_int, int bin_len); -std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len); - char* my_itoa(int input); char* fpga_spice_create_one_subckt_filename(const char* file_name_prefix, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp new file mode 100644 index 000000000..d2f41e023 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp @@ -0,0 +1,158 @@ +/******************************************************************** + * This file includes functions that print SDC (Synopsys Design Constraint) + * files in physical design tools, i.e., Place & Route (PnR) tools + * The SDC files are used to constrain the physical design for each module + * in FPGA fabric, such as Configurable Logic Blocks (CLBs), + * Heterogeneous blocks, Switch Blocks (SBs) and Connection Blocks (CBs) + * + * Note that this is different from the SDC to constrain VPR Place&Route + * engine! These SDCs are designed for PnR to generate FPGA layouts!!! + *******************************************************************/ +#include +#include +#include + +#include "vtr_assert.h" +#include "device_port.h" + +#include "util.h" + +#include "fpga_x2p_utils.h" + +#include "sdc_writer_naming.h" +#include "sdc_writer_utils.h" +#include "pnr_sdc_writer.h" + +/******************************************************************** + * Local variables + *******************************************************************/ +constexpr float SDC_FIXED_PROG_CLOCK_PERIOD = 100; +constexpr float SDC_FIXED_CLOCK_PERIOD = 10; + +/******************************************************************** + * Print a SDC file to constrain the global ports of FPGA fabric + * in particular clock ports + * + * For programming clock, we give a fixed period, while for operating + * clock, we constrain with critical path delay + *******************************************************************/ +static +void print_pnr_sdc_global_ports(const std::string& sdc_dir, + const float& critical_path_delay, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + + /* Create the file name for Verilog netlist */ + std::string sdc_fname(sdc_dir + std::string(SDC_CLOCK_FILE_NAME)); + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constraining clocks for P&R flow: %s ...", + sdc_fname.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Clock contraints for PnR")); + + /* Get clock port from the global port */ + for (const CircuitPortId& clock_port : global_ports) { + if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) { + continue; + } + /* Reach here, it means a clock port and we need print constraints */ + float clock_period = critical_path_delay; + + /* For programming clock, we give a fixed period */ + if (true == circuit_lib.port_is_prog(clock_port)) { + clock_period = SDC_FIXED_PROG_CLOCK_PERIOD; + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Create programmable clock " << std::endl; + fp << "##################################################" << std::endl; + } else { + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Create clock " << std::endl; + fp << "##################################################" << std::endl; + } + + for (const size_t& pin : circuit_lib.pins(clock_port)) { + BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin); + + fp << "create_clock "; + fp << generate_sdc_port(port_to_constrain) << "-period "; + fp << std::setprecision(10) << clock_period; + fp << " -waveform {0 "; + fp << std::setprecision(10) << clock_period / 2; + fp << "}" << std::endl; + + fp << std::endl; + } + } + + /* For non-clock port from the global port: give a fixed period */ + for (const CircuitPortId& global_port : global_ports) { + if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) { + continue; + } + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Constrain other global ports " << std::endl; + fp << "##################################################" << std::endl; + + /* Reach here, it means a non-clock global port and we need print constraints */ + float clock_period = SDC_FIXED_CLOCK_PERIOD; + for (const size_t& pin : circuit_lib.pins(global_port)) { + BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin); + fp << "create_clock "; + fp << generate_sdc_port(port_to_constrain) << "-period "; + fp << std::setprecision(10) << clock_period; + fp << " -waveform {0 "; + fp << std::setprecision(10) << clock_period / 2; + fp << "} "; + fp << "[list [get_ports { " << generate_sdc_port(port_to_constrain) << "}]]" << std::endl; + + fp << "set_drive 0 " << generate_sdc_port(port_to_constrain) << std::endl; + + fp << std::endl; + } + } + + /* Close file handler */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Top-level function to print a number of SDC files in different purpose + * This function will generate files upon the options provided by users + * 1. Design constraints for CLBs + * 2. Design constraints for Switch Blocks + * 3. Design constraints for Connection Blocks + * 4. Design constraints for breaking the combinational loops in FPGA fabric + *******************************************************************/ +void print_pnr_sdc(const SdcOption& sdc_options, + const float& critical_path_delay, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + + /* Part 1. Constrain global ports */ + if (true == sdc_options.constrain_global_port()) { + print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports); + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h new file mode 100644 index 000000000..8b0b4496a --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h @@ -0,0 +1,15 @@ +#ifndef PNR_SDC_WRITER_H +#define PNR_SDC_WRITER_H + +#include +#include "vtr_geometry.h" +#include "vpr_types.h" +#include "rr_blocks.h" +#include "sdc_option.h" + +void print_pnr_sdc(const SdcOption& sdc_options, + const float& critical_path_delay, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp new file mode 100644 index 000000000..8162f9ff1 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp @@ -0,0 +1,34 @@ +/******************************************************************** + * Useful APIs for SDC generator + *******************************************************************/ +#include +#include "pnr_sdc_writer.h" + +#include "sdc_api.h" + +/******************************************************************** + * Top-level function to launch SDC generator + *******************************************************************/ +void fpga_sdc_generator(const SdcOption& sdc_options, + const float& critical_path_delay, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + vpr_printf(TIO_MESSAGE_INFO, + "SDC generator starts..."); + + /* Start time count */ + clock_t t_start = clock(); + + if (true == sdc_options.generate_sdc_pnr()) { + print_pnr_sdc(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports); + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "SDC generation took %g seconds\n", + run_time_sec); + +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h new file mode 100644 index 000000000..fe630963e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h @@ -0,0 +1,13 @@ +#ifndef SDC_API_H +#define SDC_API_H + +#include +#include "sdc_option.h" +#include "circuit_library.h" + +void fpga_sdc_generator(const SdcOption& sdc_options, + const float& critical_path_delay, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp new file mode 100644 index 000000000..ca9753b5d --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp @@ -0,0 +1,92 @@ +/******************************************************************** + * Member functions for a data structure which includes all the options for the SDC generator + ********************************************************************/ +#include "sdc_option.h" + +/******************************************************************** + * Public Constructors + ********************************************************************/ +SdcOption::SdcOption(const std::string& sdc_dir) { + sdc_dir_ = sdc_dir; + constrain_global_port_ = true; + constrain_grid_ = true; + constrain_sb_ = true; + constrain_cb_ = true; + break_loop_ = true; +} + + +/******************************************************************** + * Public accessors + ********************************************************************/ +std::string SdcOption::sdc_dir() const { + return sdc_dir_; +} + +bool SdcOption::generate_sdc() const { + return generate_sdc_pnr_ && generate_sdc_analysis_; +} + +bool SdcOption::generate_sdc_pnr() const { + return generate_sdc_pnr_; +} + +bool SdcOption::generate_sdc_analysis() const { + return generate_sdc_analysis_; +} + +bool SdcOption::constrain_global_port() const { + return constrain_global_port_; +} + +bool SdcOption::constrain_grid() const { + return constrain_grid_; +} + +bool SdcOption::constrain_sb() const { + return constrain_sb_; +} + +bool SdcOption::constrain_cb() const { + return constrain_cb_; +} + +bool SdcOption::break_loop() const { + return break_loop_; +} + +/******************************************************************** + * Public mutators + ********************************************************************/ +void SdcOption::set_sdc_dir(const std::string& sdc_dir) { + sdc_dir_ = sdc_dir; +} + +void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) { + generate_sdc_pnr_ = generate_sdc_pnr; +} + +void SdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) { + generate_sdc_analysis_ = generate_sdc_analysis; +} + +void SdcOption::set_constrain_global_port(const bool& constrain_global_port) { + constrain_global_port_ = constrain_global_port; +} + +void SdcOption::set_constrain_grid(const bool& constrain_grid) { + constrain_grid_ = constrain_grid; +} + +void SdcOption::set_constrain_sb(const bool& constrain_sb) { + constrain_sb_ = constrain_sb; +} + +void SdcOption::set_constrain_cb(const bool& constrain_cb) { + constrain_cb_ = constrain_cb; +} + +void SdcOption::set_break_loop(const bool& break_loop) { + break_loop_ = break_loop; +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h new file mode 100644 index 000000000..244ffc796 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h @@ -0,0 +1,43 @@ +#ifndef SDC_OPTION_H +#define SDC_OPTION_H + +/******************************************************************** + * A data structure to include all the options for the SDC generator + ********************************************************************/ + +#include + +class SdcOption { + public: /* Public Constructors */ + SdcOption(const std::string& sdc_dir); + public: /* Public accessors */ + std::string sdc_dir() const; + bool generate_sdc() const; + bool generate_sdc_pnr() const; + bool generate_sdc_analysis() const; + bool constrain_global_port() const; + bool constrain_grid() const; + bool constrain_sb() const; + bool constrain_cb() const; + bool break_loop() const; + public: /* Public mutators */ + void set_sdc_dir(const std::string& sdc_dir); + void set_generate_sdc_pnr(const bool& generate_sdc_pnr); + void set_generate_sdc_analysis(const bool& generate_sdc_analysis); + void set_constrain_global_port(const bool& constrain_global_port); + void set_constrain_grid(const bool& constrain_grid); + void set_constrain_sb(const bool& constrain_sb); + void set_constrain_cb(const bool& constrain_cb); + void set_break_loop(const bool& break_loop); + private: /* Internal data */ + std::string sdc_dir_; + bool generate_sdc_pnr_; + bool constrain_global_port_; + bool constrain_grid_; + bool constrain_sb_; + bool constrain_cb_; + bool break_loop_; + bool generate_sdc_analysis_; +}; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h new file mode 100644 index 000000000..0fdb2f2b7 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h @@ -0,0 +1,10 @@ +#ifndef SDC_WRITER_NAMING_H +#define SDC_WRITER_NAMING_H + +constexpr char* SDC_CLOCK_FILE_NAME = "clb_clock.sdc"; +constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc"; +constexpr char* SDC_BREAK_COMB_LOOP_FILE_NAME = "break_loop.sdc"; +constexpr char* SDC_CB_FILE_NAME = "cb.sdc"; +constexpr char* SDC_SB_FILE_NAME = "sb.sdc"; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp new file mode 100644 index 000000000..12ef60b6b --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp @@ -0,0 +1,52 @@ +/******************************************************************** + * This file include most utilized functions to be used in SDC writers + *******************************************************************/ +#include +#include + +#include "fpga_x2p_utils.h" + +#include "sdc_writer_utils.h" + +/******************************************************************** + * Write a head (description) in SDC file + *******************************************************************/ +void print_sdc_file_header(std::fstream& fp, + const std::string& usage) { + + check_file_handler(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << "#############################################" << std::endl; + fp << "#\tSynopsys Design Constraints (SDC)" << std::endl; + fp << "#\tFor FPGA fabric " << std::endl; + fp << "#\tDescription: " << usage << std::endl; + fp << "#\tAuthor: Xifan TANG " << std::endl; + fp << "#\tOrganization: University of Utah " << std::endl; + fp << "#\tDate: " << std::ctime(&end_time); + fp << "#############################################" << std::endl; + fp << std::endl; +} + + +/******************************************************************** + * Write a port in SDC format + *******************************************************************/ +std::string generate_sdc_port(const BasicPort& port) { + std::string sdc_line; + + std::string size_str = "[" + std::to_string(port.get_lsb()) + ":" + std::to_string(port.get_msb()) + "]"; + + /* Only connection require a format of [:] + * others require a format of [:] + */ + /* When LSB == MSB, we can use a simplified format []*/ + if ( 1 == port.get_width()) { + size_str = "[" + std::to_string(port.get_lsb()) + "]"; + } + sdc_line = port.get_name() + size_str; + + return sdc_line; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h new file mode 100644 index 000000000..b3d916f57 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h @@ -0,0 +1,13 @@ +#ifndef SDC_WRITER_UTILS_H +#define SDC_WRITER_UTILS_H + +#include +#include +#include "device_port.h" + +void print_sdc_file_header(std::fstream& fp, + const std::string& usage); + +std::string generate_sdc_port(const BasicPort& port); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 51ddd8107..41766444b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -42,7 +42,7 @@ void print_verilog_file_header(std::fstream& fp, fp << "//-------------------------------------------" << std::endl; fp << "//----- Time scale -----" << std::endl; fp << "`timescale 1ns / 1ps" << std::endl; - fp << "\n"; + fp << std::endl; } /******************************************************************** From 35e718b32dc639c0ac4aec2b4deebb1130f7ae9c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 8 Nov 2019 10:20:12 -0700 Subject: [PATCH 447/482] rename backend sdc generator to be backend assistant --- .../fpga_x2p/{sdc => backend_assistant}/pnr_sdc_writer.cpp | 0 .../SRC/fpga_x2p/{sdc => backend_assistant}/pnr_sdc_writer.h | 0 .../vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_api.cpp | 0 .../vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_api.h | 0 .../SRC/fpga_x2p/{sdc => backend_assistant}/sdc_option.cpp | 0 .../vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_option.h | 0 .../fpga_x2p/{sdc => backend_assistant}/sdc_writer_naming.h | 0 .../fpga_x2p/{sdc => backend_assistant}/sdc_writer_utils.cpp | 0 .../fpga_x2p/{sdc => backend_assistant}/sdc_writer_utils.h | 0 vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 4 +--- 10 files changed, 1 insertion(+), 3 deletions(-) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/pnr_sdc_writer.cpp (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/pnr_sdc_writer.h (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_api.cpp (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_api.h (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_option.cpp (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_option.h (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_writer_naming.h (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_writer_utils.cpp (100%) rename vpr7_x2p/vpr/SRC/fpga_x2p/{sdc => backend_assistant}/sdc_writer_utils.h (100%) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/pnr_sdc_writer.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_api.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_option.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_naming.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.cpp rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h similarity index 100% rename from vpr7_x2p/vpr/SRC/fpga_x2p/sdc/sdc_writer_utils.h rename to vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 966a8cb5d..403ba8bee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -147,9 +147,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, std::string src_dir = find_path_dir_name(std::string(vpr_setup.FileNameOpts.CircuitName)); /* Use current directory if there is not dir path given */ - if (true == src_dir.empty()) { - src_dir = std::string("./"); - } else { + if (false == src_dir.empty()) { src_dir = format_dir_path(src_dir); } SdcOption sdc_options(format_dir_path(src_dir + std::string(FPGA_X2P_DEFAULT_SDC_DIR))); From 33b3705ced99c9230200fd0c7ae4e241a2621fcb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 8 Nov 2019 11:15:35 -0700 Subject: [PATCH 448/482] refactoring disable outputs sdc generation --- .../backend_assistant/pnr_sdc_writer.cpp | 64 ++++++++++++++++++- .../fpga_x2p/backend_assistant/sdc_option.cpp | 55 ++++++++++++---- .../fpga_x2p/backend_assistant/sdc_option.h | 13 ++-- .../backend_assistant/sdc_writer_naming.h | 4 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- 5 files changed, 117 insertions(+), 21 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index d2f41e023..746f7a4a3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -43,7 +43,7 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir, const std::vector& global_ports) { /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_CLOCK_FILE_NAME)); + std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME)); vpr_printf(TIO_MESSAGE_INFO, "Generating SDC for constraining clocks for P&R flow: %s ...", @@ -138,6 +138,47 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir, run_time_sec); } +/******************************************************************** + * Break combintational loops in FPGA fabric, which mainly come from: + * 1. Configurable memory cells. + * To handle this, we disable the outputs of memory cells + * 2. Loops of multiplexers. + * To handle this, we disable the outputs of routing multiplexers + *******************************************************************/ +static +void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir) { + + /* Create the file name for Verilog netlist */ + std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME)); + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for disable configurable memory outputs for P&R flow: %s ...", + sdc_fname.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("disable configurable memory outputs for PnR")); + + /* Close file handler */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + /******************************************************************** * Top-level function to print a number of SDC files in different purpose * This function will generate files upon the options provided by users @@ -155,4 +196,25 @@ void print_pnr_sdc(const SdcOption& sdc_options, if (true == sdc_options.constrain_global_port()) { print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports); } + + /* Part 2. Output Design Constraints to disable outputs of memory cells */ + if (true == sdc_options.constrain_configurable_memory_outputs()) { + print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir()); + } + + /* 2. Break loops from Multiplexer Output */ + /* + if (TRUE == sdc_opts.break_loops_mux) { + verilog_generate_sdc_break_loop_mux(fp, num_switch, switches, spice, routing_arch); + } + */ + + /* TODO: 3. Break loops from any SB output */ + /* + if (TRUE == sdc_opts.compact_routing_hierarchy) { + verilog_generate_sdc_break_loop_sb(fp, LL_device_rr_gsb); + } else { + verilog_generate_sdc_break_loop_sb(fp, LL_nx, LL_ny); + } + */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp index ca9753b5d..088266337 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp @@ -8,14 +8,15 @@ ********************************************************************/ SdcOption::SdcOption(const std::string& sdc_dir) { sdc_dir_ = sdc_dir; - constrain_global_port_ = true; - constrain_grid_ = true; - constrain_sb_ = true; - constrain_cb_ = true; - break_loop_ = true; + constrain_global_port_ = false; + constrain_grid_ = false; + constrain_sb_ = false; + constrain_cb_ = false; + constrain_configurable_memory_outputs_ = false; + constrain_routing_multiplexer_outputs_ = false; + constrain_switch_block_outputs_ = false; } - /******************************************************************** * Public accessors ********************************************************************/ @@ -24,11 +25,17 @@ std::string SdcOption::sdc_dir() const { } bool SdcOption::generate_sdc() const { - return generate_sdc_pnr_ && generate_sdc_analysis_; + return generate_sdc_pnr() && generate_sdc_analysis_; } bool SdcOption::generate_sdc_pnr() const { - return generate_sdc_pnr_; + return constrain_global_port_ + || constrain_grid_ + || constrain_sb_ + || constrain_cb_ + || constrain_configurable_memory_outputs_ + || constrain_routing_multiplexer_outputs_ + || constrain_switch_block_outputs_; } bool SdcOption::generate_sdc_analysis() const { @@ -51,8 +58,16 @@ bool SdcOption::constrain_cb() const { return constrain_cb_; } -bool SdcOption::break_loop() const { - return break_loop_; +bool SdcOption::constrain_configurable_memory_outputs() const { + return constrain_configurable_memory_outputs_; +} + +bool SdcOption::constrain_routing_multiplexer_outputs() const { + return constrain_routing_multiplexer_outputs_; +} + +bool SdcOption::constrain_switch_block_outputs() const { + return constrain_switch_block_outputs_; } /******************************************************************** @@ -63,7 +78,13 @@ void SdcOption::set_sdc_dir(const std::string& sdc_dir) { } void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) { - generate_sdc_pnr_ = generate_sdc_pnr; + constrain_global_port_ = generate_sdc_pnr; + constrain_grid_ = generate_sdc_pnr; + constrain_sb_ = generate_sdc_pnr; + constrain_cb_ = generate_sdc_pnr; + constrain_configurable_memory_outputs_ = generate_sdc_pnr; + constrain_routing_multiplexer_outputs_ = generate_sdc_pnr; + constrain_switch_block_outputs_ = generate_sdc_pnr; } void SdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) { @@ -86,7 +107,15 @@ void SdcOption::set_constrain_cb(const bool& constrain_cb) { constrain_cb_ = constrain_cb; } -void SdcOption::set_break_loop(const bool& break_loop) { - break_loop_ = break_loop; +void SdcOption::set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs) { + constrain_configurable_memory_outputs_ = constrain_config_mem_outputs; +} + +void SdcOption::set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs) { + constrain_routing_multiplexer_outputs_ = constrain_routing_mux_outputs; +} + +void SdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_outputs) { + constrain_switch_block_outputs_ = constrain_sb_outputs; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h index 244ffc796..ee6192830 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h @@ -19,7 +19,9 @@ class SdcOption { bool constrain_grid() const; bool constrain_sb() const; bool constrain_cb() const; - bool break_loop() const; + bool constrain_configurable_memory_outputs() const; + bool constrain_routing_multiplexer_outputs() const; + bool constrain_switch_block_outputs() const; public: /* Public mutators */ void set_sdc_dir(const std::string& sdc_dir); void set_generate_sdc_pnr(const bool& generate_sdc_pnr); @@ -28,15 +30,18 @@ class SdcOption { void set_constrain_grid(const bool& constrain_grid); void set_constrain_sb(const bool& constrain_sb); void set_constrain_cb(const bool& constrain_cb); - void set_break_loop(const bool& break_loop); + void set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs); + void set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs); + void set_constrain_switch_block_outputs(const bool& constrain_sb_outputs); private: /* Internal data */ std::string sdc_dir_; - bool generate_sdc_pnr_; bool constrain_global_port_; bool constrain_grid_; bool constrain_sb_; bool constrain_cb_; - bool break_loop_; + bool constrain_configurable_memory_outputs_; + bool constrain_routing_multiplexer_outputs_; + bool constrain_switch_block_outputs_; bool generate_sdc_analysis_; }; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h index 0fdb2f2b7..7b9df4804 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h @@ -1,9 +1,9 @@ #ifndef SDC_WRITER_NAMING_H #define SDC_WRITER_NAMING_H -constexpr char* SDC_CLOCK_FILE_NAME = "clb_clock.sdc"; +constexpr char* SDC_GLOBAL_PORTS_FILE_NAME = "global_ports.sdc"; constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc"; -constexpr char* SDC_BREAK_COMB_LOOP_FILE_NAME = "break_loop.sdc"; +constexpr char* SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME = "disable_configurable_memory_outputs.sdc"; constexpr char* SDC_CB_FILE_NAME = "cb.sdc"; constexpr char* SDC_SB_FILE_NAME = "sb.sdc"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 403ba8bee..dabd837a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -151,7 +151,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, src_dir = format_dir_path(src_dir); } SdcOption sdc_options(format_dir_path(src_dir + std::string(FPGA_X2P_DEFAULT_SDC_DIR))); - sdc_options.set_generate_sdc_pnr(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr); + sdc_options.set_generate_sdc_pnr(FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr); sdc_options.set_generate_sdc_analysis(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis); if (true == sdc_options.generate_sdc()) { From ea7c981c8529607ddcf47ffde67fb3a593eb9142 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 8 Nov 2019 15:01:30 -0700 Subject: [PATCH 449/482] critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer --- .../bitstream/build_routing_bitstream.cpp | 6 +-- .../module_builder/build_routing_modules.cpp | 2 +- .../verilog/verilog_module_writer.cpp | 46 +++++++++++-------- 3 files changed, 32 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp index 5d2c558ad..48c4a0504 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp @@ -248,7 +248,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager /* No bitstream generation required by a special direct connection*/ } else if (1 < src_rr_node->fan_in) { /* Create the block denoting the memory instances that drives this node in Switch Block */ - std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), src_rr_node->ptc_num, std::string("")); + std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string("")); ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block); /* This is a routing multiplexer! Generate bitstream */ @@ -380,13 +380,13 @@ void build_routing_bitstream(BitstreamManager& bitstream_manager, * To organize the bitstream in blocks, we create a block for each connection block * and give names which are same as they are in top-level module managers */ - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-directionConnection blocks ...\n"); + vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-direction Connection blocks ...\n"); build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb, CHANX); - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-directionConnection blocks ...\n"); + vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-direction Connection blocks ...\n"); build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 35fd4a296..c460f45b4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -780,7 +780,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, /* Give an instance name: this name should be consistent with the block name given in bitstream manager, * If you want to bind the bitstream generation to modules */ - std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), cur_rr_node->ptc_num, std::string("")); + std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string("")); module_manager.set_child_instance_name(cb_module, mem_module, mem_instance_id, mem_instance_name); /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp index 3a4bebcf8..0b89a87e2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp @@ -95,9 +95,9 @@ BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manag * to write up local wire declaration in Verilog format *******************************************************************/ static -std::vector find_verilog_module_local_wires(const ModuleManager& module_manager, - const ModuleId& module_id) { - std::vector local_wires; +std::map> find_verilog_module_local_wires(const ModuleManager& module_manager, + const ModuleId& module_id) { + std::map> local_wires; /* Local wires come from the child modules */ for (ModuleNetId module_net : module_manager.module_nets(module_id)) { @@ -119,20 +119,28 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu } /* Find the name for this local wire */ BasicPort local_wire_candidate = generate_verilog_port_for_module_net(module_manager, module_id, module_net); - /* Try to find a port in the list that can absorb the current local wire */ + /* Cache the net name, try to find it in the cache. + * If you can find one, it means this port may be mergeable, try to do merging. If merge fail, add to the local wire list + * If you cannot find one, it means that this port is not mergeable, add to the local wire list immediately. + */ + std::map>::iterator it = local_wires.find(local_wire_candidate.get_name()); bool merged = false; - for (BasicPort& local_wire : local_wires) { - /* check if the candidate can be combined to an existing local wire */ - if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) { - /* Merge the ports */ - local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate); - merged = true; - break; - } + if (it != local_wires.end()) { + /* Try to merge to one the port in the list that can absorb the current local wire */ + for (BasicPort& local_wire : local_wires[local_wire_candidate.get_name()]) { + /* check if the candidate can be combined to an existing local wire */ + if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) { + /* Merge the ports */ + local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate); + merged = true; + break; + } + } } - /* If not merged, push the port to the list */ + + /* If not merged/not found in the cache, push the port to the list */ if (false == merged) { - local_wires.push_back(local_wire_candidate); + local_wires[local_wire_candidate.get_name()].push_back(local_wire_candidate); } } @@ -161,7 +169,7 @@ std::vector find_verilog_module_local_wires(const ModuleManager& modu instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()), *std::max_element(undriven_pins.begin(), undriven_pins.end())); - local_wires.push_back(instance_port); + local_wires[instance_port.get_name()].push_back(instance_port); } } } @@ -436,9 +444,11 @@ void write_verilog_module_to_file(std::fstream& fp, fp << std::endl; /* Print internal wires */ - std::vector local_wires = find_verilog_module_local_wires(module_manager, module_id); - for (BasicPort local_wire : local_wires) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl; + std::map> local_wires = find_verilog_module_local_wires(module_manager, module_id); + for (std::pair> port_group : local_wires) { + for (const BasicPort& local_wire : port_group.second) { + fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl; + } } /* Print an empty line as splitter */ From e273c00c9d76512265b3ca5316b4e0934fb4362c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 8 Nov 2019 17:38:07 -0700 Subject: [PATCH 450/482] add refactored disable timing for memory cells --- .../backend_assistant/pnr_sdc_writer.cpp | 73 ++++++++++++++++++- .../backend_assistant/pnr_sdc_writer.h | 2 + .../fpga_x2p/backend_assistant/sdc_api.cpp | 4 +- .../SRC/fpga_x2p/backend_assistant/sdc_api.h | 2 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 4 +- 5 files changed, 77 insertions(+), 8 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index 746f7a4a3..042efac5e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -17,6 +17,7 @@ #include "util.h" +#include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" #include "sdc_writer_naming.h" @@ -139,14 +140,70 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir, } /******************************************************************** - * Break combintational loops in FPGA fabric, which mainly come from: + * Print SDC commands to disable outputs of all the configurable memory modules + * in a given module + * This function will be executed in a recursive way, + * using a Depth-First Search (DFS) strategy + * It will iterate over all the configurable children under each module + * and print a SDC command to disable its outputs + *******************************************************************/ +static +void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_module_path) { + + /* For each configurable child, we will go one level down in priority */ + for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) { + std::string child_module_path = parent_module_path; + ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index]; + size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index]; + if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) { + /* Give a default name __ */ + child_module_path += module_manager.module_name(child_module_id); + child_module_path += "_"; + child_module_path += std::to_string(child_instance_id); + child_module_path += "_"; + } else { + child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id); + } + child_module_path = format_dir_path(child_module_path); + + rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, + child_module_id, + child_module_path); + } + + /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */ + if (0 < module_manager.configurable_children(parent_module).size()) { + return; + } + + /* Validate file stream */ + check_file_handler(fp); + + /* Disable timing for each output port of this module */ + for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) { + for (const size_t& pin : output_port.pins()) { + BasicPort output_pin(output_port.get_name(), pin, pin); + fp << "set_disable_timing "; + fp << parent_module_path << generate_sdc_port(output_pin); + fp << std::endl; + } + } +} + +/******************************************************************** + * Break combinational loops in FPGA fabric, which mainly come from: * 1. Configurable memory cells. * To handle this, we disable the outputs of memory cells * 2. Loops of multiplexers. * To handle this, we disable the outputs of routing multiplexers *******************************************************************/ static -void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir) { +void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir, + const ModuleManager& module_manager, + const ModuleId& top_module) { /* Create the file name for Verilog netlist */ std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME)); @@ -165,7 +222,11 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_ check_file_handler(fp); /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("disable configurable memory outputs for PnR")); + print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR")); + + /* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */ + rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, top_module, + format_dir_path(module_manager.module_name(top_module))); /* Close file handler */ fp.close(); @@ -190,6 +251,7 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_ void print_pnr_sdc(const SdcOption& sdc_options, const float& critical_path_delay, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, const std::vector& global_ports) { /* Part 1. Constrain global ports */ @@ -199,7 +261,10 @@ void print_pnr_sdc(const SdcOption& sdc_options, /* Part 2. Output Design Constraints to disable outputs of memory cells */ if (true == sdc_options.constrain_configurable_memory_outputs()) { - print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir()); + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.find_module(top_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module); } /* 2. Break loops from Multiplexer Output */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h index 8b0b4496a..492a18873 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h @@ -5,11 +5,13 @@ #include "vtr_geometry.h" #include "vpr_types.h" #include "rr_blocks.h" +#include "module_manager.h" #include "sdc_option.h" void print_pnr_sdc(const SdcOption& sdc_options, const float& critical_path_delay, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, const std::vector& global_ports); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index 8162f9ff1..f6d46561b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -12,6 +12,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, const std::vector& global_ports) { vpr_printf(TIO_MESSAGE_INFO, "SDC generator starts..."); @@ -20,7 +21,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options, clock_t t_start = clock(); if (true == sdc_options.generate_sdc_pnr()) { - print_pnr_sdc(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports); + print_pnr_sdc(sdc_options, critical_path_delay, circuit_lib, module_manager, global_ports); } /* End time count */ @@ -30,5 +31,4 @@ void fpga_sdc_generator(const SdcOption& sdc_options, vpr_printf(TIO_MESSAGE_INFO, "SDC generation took %g seconds\n", run_time_sec); - } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h index fe630963e..fbd9960d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h @@ -4,10 +4,12 @@ #include #include "sdc_option.h" #include "circuit_library.h" +#include "module_manager.h" void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, const std::vector& global_ports); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index dabd837a8..ccecccabd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -151,7 +151,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, src_dir = format_dir_path(src_dir); } SdcOption sdc_options(format_dir_path(src_dir + std::string(FPGA_X2P_DEFAULT_SDC_DIR))); - sdc_options.set_generate_sdc_pnr(FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr); + sdc_options.set_generate_sdc_pnr(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr); sdc_options.set_generate_sdc_analysis(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis); if (true == sdc_options.generate_sdc()) { @@ -159,7 +159,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* TODO: the critical path delay unit should be explicit! */ fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, - Arch.spice->circuit_lib, global_ports); + Arch.spice->circuit_lib, module_manager, global_ports); } /* Xifan Tang: Bitstream Generator */ From be574b0d45ee93c609db9cc9289315638cc26aea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 8 Nov 2019 19:05:05 -0700 Subject: [PATCH 451/482] refactored disable routing mux outputs --- .../backend_assistant/pnr_sdc_writer.cpp | 91 ++++++++++++++++--- .../backend_assistant/pnr_sdc_writer.h | 3 + .../fpga_x2p/backend_assistant/sdc_api.cpp | 3 +- .../SRC/fpga_x2p/backend_assistant/sdc_api.h | 2 + .../backend_assistant/sdc_writer_naming.h | 1 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 1 + 6 files changed, 88 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index 042efac5e..1fb4ebeaa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -16,6 +16,7 @@ #include "device_port.h" #include "util.h" +#include "mux_utils.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" @@ -194,11 +195,9 @@ void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& f } /******************************************************************** - * Break combinational loops in FPGA fabric, which mainly come from: - * 1. Configurable memory cells. - * To handle this, we disable the outputs of memory cells - * 2. Loops of multiplexers. - * To handle this, we disable the outputs of routing multiplexers + * Break combinational loops in FPGA fabric, which mainly come from + * configurable memory cells. + * To handle this, we disable the outputs of memory cells *******************************************************************/ static void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir, @@ -240,6 +239,72 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_ run_time_sec); } +/******************************************************************** + * Break combinational loops in FPGA fabric, which mainly come from + * loops of multiplexers. + * To handle this, we disable the timing at outputs of routing multiplexers + *******************************************************************/ +static +void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir, + const MuxLibrary& mux_lib, + const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager) { + /* Create the file name for Verilog netlist */ + std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME)); + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for disable routing multiplexer outputs for P&R flow: %s ...", + sdc_fname.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR")); + + /* Iterate over the MUX modules */ + for (const MuxId& mux_id : mux_lib.muxes()) { + const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id); + + /* Skip LUTs, we only care about multiplexers here */ + if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { + continue; + } + + const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, + find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), + std::string("")); + /* Find the module name in module manager */ + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); + + /* Disable the timing for the output ports */ + for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) { + fp << "set_disable_timing [get_pins -filter \"name =~ " << output_port.get_name() << "*\" "; + fp << "-of [get_cells -hier -filter \"ref_lib_cell_name == " << mux_module_name << "\"]]" << std::endl; + fp << std::endl; + } + } + + /* Close file handler */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + /******************************************************************** * Top-level function to print a number of SDC files in different purpose * This function will generate files upon the options provided by users @@ -250,6 +315,7 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_ *******************************************************************/ void print_pnr_sdc(const SdcOption& sdc_options, const float& critical_path_delay, + const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const std::vector& global_ports) { @@ -259,20 +325,21 @@ void print_pnr_sdc(const SdcOption& sdc_options, print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports); } + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = module_manager.find_module(top_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + /* Part 2. Output Design Constraints to disable outputs of memory cells */ if (true == sdc_options.constrain_configurable_memory_outputs()) { - std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.find_module(top_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module); } /* 2. Break loops from Multiplexer Output */ - /* - if (TRUE == sdc_opts.break_loops_mux) { - verilog_generate_sdc_break_loop_mux(fp, num_switch, switches, spice, routing_arch); + if (true == sdc_options.constrain_routing_multiplexer_outputs()) { + print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(), + mux_lib, circuit_lib, + module_manager); } - */ /* TODO: 3. Break loops from any SB output */ /* diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h index 492a18873..6923320a6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h @@ -6,10 +6,13 @@ #include "vpr_types.h" #include "rr_blocks.h" #include "module_manager.h" +#include "mux_library.h" +#include "circuit_library.h" #include "sdc_option.h" void print_pnr_sdc(const SdcOption& sdc_options, const float& critical_path_delay, + const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const std::vector& global_ports); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index f6d46561b..99a981df8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -11,6 +11,7 @@ *******************************************************************/ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, + const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const std::vector& global_ports) { @@ -21,7 +22,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options, clock_t t_start = clock(); if (true == sdc_options.generate_sdc_pnr()) { - print_pnr_sdc(sdc_options, critical_path_delay, circuit_lib, module_manager, global_ports); + print_pnr_sdc(sdc_options, critical_path_delay, mux_lib, circuit_lib, module_manager, global_ports); } /* End time count */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h index fbd9960d8..e0f64fafd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h @@ -4,10 +4,12 @@ #include #include "sdc_option.h" #include "circuit_library.h" +#include "mux_library.h" #include "module_manager.h" void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, + const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const std::vector& global_ports); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h index 7b9df4804..7371835a8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h @@ -4,6 +4,7 @@ constexpr char* SDC_GLOBAL_PORTS_FILE_NAME = "global_ports.sdc"; constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc"; constexpr char* SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME = "disable_configurable_memory_outputs.sdc"; +constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer_outputs.sdc"; constexpr char* SDC_CB_FILE_NAME = "cb.sdc"; constexpr char* SDC_SB_FILE_NAME = "sb.sdc"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index ccecccabd..8c1f6b5e2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -159,6 +159,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* TODO: the critical path delay unit should be explicit! */ fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, + mux_lib, Arch.spice->circuit_lib, module_manager, global_ports); } From 4b5ecc516bb9127e89ce6650fb47f43c5cd0e204 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 9 Nov 2019 10:52:15 -0700 Subject: [PATCH 452/482] refactored SDC SB constrain generation --- .../backend_assistant/pnr_sdc_writer.cpp | 389 +++++++++++++++++- .../backend_assistant/pnr_sdc_writer.h | 8 +- .../fpga_x2p/backend_assistant/sdc_api.cpp | 14 +- .../SRC/fpga_x2p/backend_assistant/sdc_api.h | 8 +- .../backend_assistant/sdc_writer_naming.h | 4 +- .../backend_assistant/sdc_writer_utils.cpp | 29 ++ .../backend_assistant/sdc_writer_utils.h | 8 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 6 +- .../build_routing_module_utils.cpp | 219 ++++++++++ .../build_routing_module_utils.h | 49 +++ .../module_builder/build_routing_modules.cpp | 213 +--------- 11 files changed, 715 insertions(+), 232 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index 1fb4ebeaa..a693d0c2c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -21,6 +21,8 @@ #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" +#include "build_routing_module_utils.h" + #include "sdc_writer_naming.h" #include "sdc_writer_utils.h" #include "pnr_sdc_writer.h" @@ -305,6 +307,327 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir, run_time_sec); } +/******************************************************************** + * Break combinational loops in FPGA fabric, which mainly come from + * loops of multiplexers. + * To handle this, we disable the timing at outputs of Switch blocks + * This function is designed for flatten routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::string& sdc_dir, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb) { + /* Create the file name for Verilog netlist */ + std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME)); + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for disable Switch Block outputs for P&R flow: %s ...", + sdc_fname.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR")); + + /* Get the range of SB array */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + /* Go for each SB */ + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); + + ModuleId sb_module = module_manager.find_module(sb_instance_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Disable the outputs of the module */ + for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) { + fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl; + fp << std::endl; + } + } + } + + /* Close file handler */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Break combinational loops in FPGA fabric, which mainly come from + * loops of multiplexers. + * To handle this, we disable the timing at outputs of Switch blocks + * This function is designed for compact routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir, + const ModuleManager& module_manager, + const ModuleId& top_module, + const DeviceRRGSB& L_device_rr_gsb) { + /* Create the file name for Verilog netlist */ + std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME)); + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for disable Switch Block outputs for P&R flow: %s ...", + sdc_fname.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR")); + + /* Build unique switch block modules */ + for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb); + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); + + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Find all the instances in the top-level module */ + for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) { + std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id); + /* Disable the outputs of the module */ + for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) { + fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl; + fp << std::endl; + } + } + } + + /* Close file handler */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Find the timing constraints between the inputs and outputs of a routing + * multiplexer in a Switch Block + *******************************************************************/ +static +float find_pnr_sdc_switch_tmax(const t_switch_inf& switch_inf) { + return switch_inf.R * switch_inf.Cout + switch_inf.Tdel; +} + +/******************************************************************** + * Set timing constraints between the inputs and outputs of a routing + * multiplexer in a Switch Block + *******************************************************************/ +static +void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const std::vector& switches, + const e_side& output_node_side, + t_rr_node* output_rr_node) { + /* Validate file stream */ + check_file_handler(fp); + + VTR_ASSERT( ( CHANX == output_rr_node->type ) + || ( CHANY == output_rr_node->type )); + + /* Find the module port corresponding to the output rr_node */ + ModulePortId module_output_port = find_switch_block_module_chan_port(module_manager, + sb_module, + rr_gsb, + output_node_side, + output_rr_node, + OUT_PORT); + + /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ + std::vector input_rr_nodes; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); + } + + std::vector module_input_ports = find_switch_block_module_input_ports(module_manager, + sb_module, + rr_gsb, + grids, + input_rr_nodes); + + /* Find timing constraints for each path (edge) */ + std::map switch_delays; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + /* Get the switch delay */ + int switch_id = output_rr_node->drive_switches[iedge]; + switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); + } + + /* Find the starting points */ + for (const ModulePortId& module_input_port : module_input_ports) { + /* Constrain a path */ + print_pnr_sdc_constrain_module_port2port_timing(fp, + module_manager, sb_module, + module_input_port, module_output_port, + switch_delays[module_input_port]); + } +} + +/******************************************************************** + * Set timing constraints between the inputs and outputs of SBs, + * which are connected by routing multiplexers with the given delays + * specified in architectural XML file + * + * To enable block by block timing constraining, we generate the SDC + * file for each unique SB module + *******************************************************************/ +static +void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const RRGSB& rr_gsb) { + + /* Create the file name for Verilog netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + /* Validate file stream */ + check_file_handler(fp); + + std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " outputs for PnR")); + + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + t_rr_node* chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); + /* We only care the output port and it should indicate a SB mux */ + if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + /* Constrain thru wires */ + if (false != rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { + continue; + } + /* This is a MUX, constrain all the paths from an input to an output */ + print_pnr_sdc_constrain_sb_mux_timing(fp, + module_manager, sb_module, + rr_gsb, + grids, switches, + side_manager.get_side(), + chan_rr_node); + } + } + + /* Close file handler */ + fp.close(); +} + +/******************************************************************** + * Print SDC timing constraints for Switch blocks + * This function is designed for flatten routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Switch Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + /* Get the range of SB array */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + /* Go for each SB */ + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + print_pnr_sdc_constrain_sb_timing(sdc_dir, + module_manager, + grids, switches, + rr_gsb); + } + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Break combinational loops in FPGA fabric, which mainly come from + * loops of multiplexers. + * To handle this, we disable the timing at outputs of Switch blocks + * This function is designed for compact routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Switch Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb); + print_pnr_sdc_constrain_sb_timing(sdc_dir, + module_manager, + grids, switches, + rr_gsb); + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + /******************************************************************** * Top-level function to print a number of SDC files in different purpose * This function will generate files upon the options provided by users @@ -315,12 +638,16 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir, *******************************************************************/ void print_pnr_sdc(const SdcOption& sdc_options, const float& critical_path_delay, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb, + const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const ModuleManager& module_manager, - const std::vector& global_ports) { + const std::vector& global_ports, + const bool& compact_routing_hierarchy) { - /* Part 1. Constrain global ports */ + /* Constrain global ports */ if (true == sdc_options.constrain_global_port()) { print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports); } @@ -329,24 +656,66 @@ void print_pnr_sdc(const SdcOption& sdc_options, ModuleId top_module = module_manager.find_module(top_module_name); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - /* Part 2. Output Design Constraints to disable outputs of memory cells */ + /* Output Design Constraints to disable outputs of memory cells */ if (true == sdc_options.constrain_configurable_memory_outputs()) { print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module); } - /* 2. Break loops from Multiplexer Output */ + /* Break loops from Multiplexer Output */ if (true == sdc_options.constrain_routing_multiplexer_outputs()) { print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(), mux_lib, circuit_lib, module_manager); } - /* TODO: 3. Break loops from any SB output */ + /* Break loops from any SB output */ + if (true == sdc_options.constrain_switch_block_outputs()) { + if (true == compact_routing_hierarchy) { + print_pnr_sdc_compact_routing_disable_switch_block_outputs(sdc_options.sdc_dir(), + module_manager, top_module, + L_device_rr_gsb); + } else { + VTR_ASSERT_SAFE (false == compact_routing_hierarchy); + print_pnr_sdc_flatten_routing_disable_switch_block_outputs(sdc_options.sdc_dir(), + module_manager, + L_device_rr_gsb); + } + } + + /* Output routing constraints for Switch Blocks */ + if (true == sdc_options.constrain_sb()) { + if (true == compact_routing_hierarchy) { + print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(), + module_manager, + grids, switches, + L_device_rr_gsb); + } else { + VTR_ASSERT_SAFE (false == compact_routing_hierarchy); + print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(), + module_manager, + grids, switches, + L_device_rr_gsb); + } + } + + /* TODO: Output routing constraints for Connection Blocks */ /* - if (TRUE == sdc_opts.compact_routing_hierarchy) { - verilog_generate_sdc_break_loop_sb(fp, LL_device_rr_gsb); - } else { - verilog_generate_sdc_break_loop_sb(fp, LL_nx, LL_ny); + if (true == sdc_options.constrain_cb()) { + if (true == compact_routing_hierarchy) { + verilog_generate_sdc_constrain_cbs(sdc_opts, LL_nx, LL_ny, LL_device_rr_gsb); + } else { + VTR_ASSERT_SAFE (false == compact_routing_hierarchy); + verilog_generate_sdc_constrain_cbs(sdc_opts, + LL_nx, LL_ny); + } + } + */ + + /* TODO: Output routing constraints for Programmable blocks */ + /* + if (true == sdc_options.constrain_grid()) { + verilog_generate_sdc_constrain_pb_types(cur_sram_orgz_info, + sdc_dir); } */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h index 6923320a6..6b618b2df 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h @@ -12,9 +12,13 @@ void print_pnr_sdc(const SdcOption& sdc_options, const float& critical_path_delay, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb, + const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const ModuleManager& module_manager, - const std::vector& global_ports); + const std::vector& global_ports, + const bool& compact_routing_hierarchy); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index 99a981df8..690e456c5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -11,10 +11,14 @@ *******************************************************************/ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb, + const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const ModuleManager& module_manager, - const std::vector& global_ports) { + const std::vector& global_ports, + const bool& compact_routing_hierarchy) { vpr_printf(TIO_MESSAGE_INFO, "SDC generator starts..."); @@ -22,7 +26,11 @@ void fpga_sdc_generator(const SdcOption& sdc_options, clock_t t_start = clock(); if (true == sdc_options.generate_sdc_pnr()) { - print_pnr_sdc(sdc_options, critical_path_delay, mux_lib, circuit_lib, module_manager, global_ports); + print_pnr_sdc(sdc_options, critical_path_delay, + grids, switches, L_device_rr_gsb, + module_manager, mux_lib, + circuit_lib, global_ports, + compact_routing_hierarchy); } /* End time count */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h index e0f64fafd..d53dc201a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h @@ -9,9 +9,13 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb, + const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const ModuleManager& module_manager, - const std::vector& global_ports); + const std::vector& global_ports, + const bool& compact_routing_hierarchy); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h index 7371835a8..e479f95d3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h @@ -1,11 +1,13 @@ #ifndef SDC_WRITER_NAMING_H #define SDC_WRITER_NAMING_H +constexpr char* SDC_FILE_NAME_POSTFIX = ".sdc"; + constexpr char* SDC_GLOBAL_PORTS_FILE_NAME = "global_ports.sdc"; constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc"; constexpr char* SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME = "disable_configurable_memory_outputs.sdc"; constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer_outputs.sdc"; +constexpr char* SDC_DISABLE_SB_OUTPUTS_FILE_NAME = "disable_sb_outputs.sdc"; constexpr char* SDC_CB_FILE_NAME = "cb.sdc"; -constexpr char* SDC_SB_FILE_NAME = "sb.sdc"; #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp index 12ef60b6b..6a74c290d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp @@ -3,6 +3,7 @@ *******************************************************************/ #include #include +#include #include "fpga_x2p_utils.h" @@ -50,3 +51,31 @@ std::string generate_sdc_port(const BasicPort& port) { return sdc_line; } + +/******************************************************************** + * Constrain a path between two ports of a module with a given timing value + *******************************************************************/ +void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const ModulePortId& module_input_port_id, + const ModulePortId& module_output_port_id, + const float& tmax) { + /* Validate file stream */ + check_file_handler(fp); + + fp << "set_max_delay"; + + fp << " -from "; + fp << module_manager.module_name(module_id) << "/"; + fp << generate_sdc_port(module_manager.module_port(module_id, module_input_port_id)); + + fp << " -to "; + + fp << module_manager.module_name(module_id) << "/"; + fp << generate_sdc_port(module_manager.module_port(module_id, module_output_port_id)); + + fp << " " << std::setprecision(10) << tmax; + + fp << std::endl; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h index b3d916f57..d4c2ae860 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h @@ -4,10 +4,18 @@ #include #include #include "device_port.h" +#include "module_manager.h" void print_sdc_file_header(std::fstream& fp, const std::string& usage); std::string generate_sdc_port(const BasicPort& port); +void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& module_id, + const ModulePortId& module_input_port_id, + const ModulePortId& module_output_port_id, + const float& tmax); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 8c1f6b5e2..a254d4824 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -159,8 +159,10 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* TODO: the critical path delay unit should be explicit! */ fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, - mux_lib, - Arch.spice->circuit_lib, module_manager, global_ports); + grids, rr_switches, device_rr_gsb, + module_manager, mux_lib, + Arch.spice->circuit_lib, global_ports, + TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); } /* Xifan Tang: Bitstream Generator */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp new file mode 100644 index 000000000..a81eb567f --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp @@ -0,0 +1,219 @@ +/******************************************************************** + * This file includes most utilized functions that are used to build modules + * for global routing architecture of a FPGA fabric + * Covering: + * 1. Connection blocks + * 2. Switch blocks + *******************************************************************/ +#include "vtr_assert.h" +#include "vtr_geometry.h" +#include "device_coordinator.h" + +#include "fpga_x2p_naming.h" + +#include "build_routing_module_utils.h" + +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ +ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const PORTS& cur_rr_node_direction) { + /* Get the index in sb_info of cur_rr_node */ + int index = rr_gsb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); + /* Make sure this node is included in this sb_info */ + VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); + + DeviceCoordinator chan_rr_node_coordinator = rr_gsb.get_side_block_coordinator(chan_side); + + vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); + std::string chan_port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(chan_side, index)->type, + chan_port_coord, index, + rr_gsb.get_chan_node_direction(chan_side, index)); + + /* Must find a valid port id in the Switch Block module */ + ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, chan_port_id)); + return chan_port_id; +} + +/********************************************************************* + * Generate an input port for routing multiplexer inside the switch block + * In addition to give the Routing Resource node of the input + * Users should provide the side of input, which is different case by case: + * 1. When the input is a pin of a CLB/Logic Block, the input_side should + * be the side of the node on its grid! + * For example, the input pin is on the top side of a switch block + * but on the right side of a switch block + * +--------+ + * | | + * | Grid |---+ + * | | | + * +--------+ v input_pin + * +----------------+ + * | Switch Block | + * +----------------+ + * 2. When the input is a routing track, the input_side should be + * the side of the node locating on the switch block + ********************************************************************/ +ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const e_side& input_side, + t_rr_node* input_rr_node) { + /* Deposit an invalid value */ + ModulePortId input_port_id = ModulePortId::INVALID(); + /* Generate the input port object */ + switch (input_rr_node->type) { + /* case SOURCE: */ + case OPIN: { + /* Find the coordinator (grid_x and grid_y) for the input port */ + vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); + std::string input_port_name = generate_grid_side_port_name(grids, + input_port_coord, + input_side, + input_rr_node->ptc_num); + /* Must find a valid port id in the Switch Block module */ + input_port_id = module_manager.find_module_port(sb_module, input_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port_id)); + break; + } + case CHANX: + case CHANY: { + input_port_id = find_switch_block_module_chan_port(module_manager, sb_module, + rr_gsb, input_side, input_rr_node, IN_PORT); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + return input_port_id; +} + +/********************************************************************* + * Generate a list of input ports for routing multiplexer inside the switch block + ********************************************************************/ +std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const std::vector& input_rr_nodes) { + std::vector input_ports; + + for (auto input_rr_node : input_rr_nodes) { + enum e_side input_pin_side = NUM_SIDES; + switch (input_rr_node->type) { + case OPIN: + input_pin_side = rr_gsb.get_opin_node_grid_side(input_rr_node); + break; + case CHANX: + case CHANY: { + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_gsb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); + VTR_ASSERT(NUM_SIDES != input_pin_side); + break; + } + default: /* SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, input_rr_node)); + } + + return input_ports; +} + +/********************************************************************* + * Generate an input port for routing multiplexer inside the connection block + * which is the middle output of a routing track + ********************************************************************/ +ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + t_rr_node* chan_rr_node) { + ModulePortId input_port_id; + /* Generate the input port object */ + switch (chan_rr_node->type) { + case CHANX: + case CHANY: { + /* Create port description for the routing track middle output */ + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); + /* Create a port description for the middle output */ + std::string input_port_name = generate_routing_track_port_name(cb_type, + port_coord, chan_node_track_id, + IN_PORT); + /* Must find a valid port id in the Switch Block module */ + input_port_id = module_manager.find_module_port(cb_module, input_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id)); + break; + } + default: /* OPIN, SOURCE, IPIN, SINK are invalid*/ + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", + __FILE__, __LINE__); + exit(1); + } + + return input_port_id; +} + +/********************************************************************* + * Generate a port for a routing track of a swtich block + ********************************************************************/ +ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + t_rr_node* src_rr_node) { + + /* Ensure the src_rr_node is an input pin of a CLB */ + VTR_ASSERT(IPIN == src_rr_node->type); + /* Create port description for input pin of a CLB */ + vtr::Point port_coord(src_rr_node->xlow, src_rr_node->ylow); + /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ + enum e_side cb_ipin_side = NUM_SIDES; + int cb_ipin_index = -1; + rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); + /* We need to be sure that drive_rr_node is part of the CB */ + VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); + std::string port_name = generate_grid_side_port_name(grids, + port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, cb_ipin_index), + rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); + + /* Must find a valid port id in the Switch Block module */ + ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, ipin_port_id)); + return ipin_port_id; +} + +/********************************************************************* + * Generate a list of routing track middle output ports + * for routing multiplexer inside the connection block + ********************************************************************/ +std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector& input_rr_nodes) { + std::vector input_ports; + + for (auto input_rr_node : input_rr_nodes) { + input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, input_rr_node)); + } + + return input_ports; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h new file mode 100644 index 000000000..aa423b12e --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h @@ -0,0 +1,49 @@ +#ifndef BUILD_ROUTING_MODULE_UTILS_H +#define BUILD_ROUTING_MODULE_UTILS_H + +#include +#include "rr_blocks.h" +#include "module_manager.h" +#include "sides.h" +#include "vpr_types.h" + +ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const e_side& chan_side, + t_rr_node* cur_rr_node, + const PORTS& cur_rr_node_direction); + +ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const e_side& input_side, + t_rr_node* input_rr_node); + +std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const std::vector& input_rr_nodes); + +ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + t_rr_node* chan_rr_node); + +ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + t_rr_node* src_rr_node); + + +std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector& input_rr_nodes); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index c460f45b4..d2b5b4464 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -21,135 +21,11 @@ #include "fpga_x2p_utils.h" #include "module_manager_utils.h" #include "build_module_graph_utils.h" +#include "build_routing_module_utils.h" #include "build_routing_modules.h" #include "verilog_global.h" -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ -static -ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const PORTS& cur_rr_node_direction) { - /* Get the index in sb_info of cur_rr_node */ - int index = rr_gsb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); - /* Make sure this node is included in this sb_info */ - VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); - - DeviceCoordinator chan_rr_node_coordinator = rr_gsb.get_side_block_coordinator(chan_side); - - vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); - std::string chan_port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(chan_side, index)->type, - chan_port_coord, index, - rr_gsb.get_chan_node_direction(chan_side, index)); - - /* Must find a valid port id in the Switch Block module */ - ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, chan_port_id)); - return chan_port_id; -} - -/********************************************************************* - * Generate an input port for routing multiplexer inside the switch block - * In addition to give the Routing Resource node of the input - * Users should provide the side of input, which is different case by case: - * 1. When the input is a pin of a CLB/Logic Block, the input_side should - * be the side of the node on its grid! - * For example, the input pin is on the top side of a switch block - * but on the right side of a switch block - * +--------+ - * | | - * | Grid |---+ - * | | | - * +--------+ v input_pin - * +----------------+ - * | Switch Block | - * +----------------+ - * 2. When the input is a routing track, the input_side should be - * the side of the node locating on the switch block - ********************************************************************/ -static -ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const std::vector>& grids, - const e_side& input_side, - t_rr_node* input_rr_node) { - /* Deposit an invalid value */ - ModulePortId input_port_id = ModulePortId::INVALID(); - /* Generate the input port object */ - switch (input_rr_node->type) { - /* case SOURCE: */ - case OPIN: { - /* Find the coordinator (grid_x and grid_y) for the input port */ - vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); - std::string input_port_name = generate_grid_side_port_name(grids, - input_port_coord, - input_side, - input_rr_node->ptc_num); - /* Must find a valid port id in the Switch Block module */ - input_port_id = module_manager.find_module_port(sb_module, input_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port_id)); - break; - } - case CHANX: - case CHANY: { - input_port_id = find_switch_block_module_chan_port(module_manager, sb_module, - rr_gsb, input_side, input_rr_node, IN_PORT); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - return input_port_id; -} - -/********************************************************************* - * Generate a list of input ports for routing multiplexer inside the switch block - ********************************************************************/ -static -std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const std::vector>& grids, - const std::vector& input_rr_nodes) { - std::vector input_ports; - - for (auto input_rr_node : input_rr_nodes) { - enum e_side input_pin_side = NUM_SIDES; - switch (input_rr_node->type) { - case OPIN: - input_pin_side = rr_gsb.get_opin_node_grid_side(input_rr_node); - break; - case CHANX: - case CHANY: { - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_gsb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); - VTR_ASSERT(NUM_SIDES != input_pin_side); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, input_rr_node)); - } - - return input_ports; -} - - /********************************************************************* * Generate a short interconneciton in switch box * There are two cases should be noticed. @@ -550,93 +426,6 @@ void build_switch_block_module(ModuleManager& module_manager, } } -/********************************************************************* - * Generate an input port for routing multiplexer inside the connection block - * which is the middle output of a routing track - ********************************************************************/ -static -ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - t_rr_node* chan_rr_node) { - ModulePortId input_port_id; - /* Generate the input port object */ - switch (chan_rr_node->type) { - case CHANX: - case CHANY: { - /* Create port description for the routing track middle output */ - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); - /* Create a port description for the middle output */ - std::string input_port_name = generate_routing_track_port_name(cb_type, - port_coord, chan_node_track_id, - IN_PORT); - /* Must find a valid port id in the Switch Block module */ - input_port_id = module_manager.find_module_port(cb_module, input_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id)); - break; - } - default: /* OPIN, SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - return input_port_id; -} - -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ -static -ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const std::vector>& grids, - t_rr_node* src_rr_node) { - - /* Ensure the src_rr_node is an input pin of a CLB */ - VTR_ASSERT(IPIN == src_rr_node->type); - /* Create port description for input pin of a CLB */ - vtr::Point port_coord(src_rr_node->xlow, src_rr_node->ylow); - /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - enum e_side cb_ipin_side = NUM_SIDES; - int cb_ipin_index = -1; - rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); - /* We need to be sure that drive_rr_node is part of the CB */ - VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); - std::string port_name = generate_grid_side_port_name(grids, - port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, cb_ipin_index), - rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); - - /* Must find a valid port id in the Switch Block module */ - ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, ipin_port_id)); - return ipin_port_id; -} - -/********************************************************************* - * Generate a list of routing track middle output ports - * for routing multiplexer inside the connection block - ********************************************************************/ -static -std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector& input_rr_nodes) { - std::vector input_ports; - - for (auto input_rr_node : input_rr_nodes) { - input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, input_rr_node)); - } - - return input_ports; -} - /********************************************************************* * Print a short interconneciton in connection ********************************************************************/ From a7f2a61d0d964ceea35872a2de97f24843a4477f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 9 Nov 2019 11:42:38 -0700 Subject: [PATCH 453/482] refactored CB SDC generation --- .../backend_assistant/pnr_sdc_writer.cpp | 244 +++++++++++++++++- .../build_routing_module_utils.h | 1 - 2 files changed, 234 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index a693d0c2c..70b8f00ab 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -527,7 +527,7 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " outputs for PnR")); + print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR")); for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { Side side_manager(side); @@ -594,9 +594,7 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di } /******************************************************************** - * Break combinational loops in FPGA fabric, which mainly come from - * loops of multiplexers. - * To handle this, we disable the timing at outputs of Switch blocks + * Print SDC timing constraints for Switch blocks * This function is designed for compact routing hierarchy *******************************************************************/ static @@ -628,6 +626,227 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di run_time_sec); } +/******************************************************************** + * Set timing constraints between the inputs and outputs of a routing + * multiplexer in a Connection Block + *******************************************************************/ +static +void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector>& grids, + const std::vector& switches, + t_rr_node* output_rr_node) { + /* Validate file stream */ + check_file_handler(fp); + + VTR_ASSERT(IPIN == output_rr_node->type); + + /* Find the module port corresponding to the output rr_node */ + ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, + cb_module, + rr_gsb, + grids, output_rr_node); + + /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ + std::vector input_rr_nodes; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); + } + + std::vector module_input_ports = find_connection_block_module_input_ports(module_manager, + cb_module, + rr_gsb, + cb_type, + input_rr_nodes); + + /* Find timing constraints for each path (edge) */ + std::map switch_delays; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + /* Get the switch delay */ + int switch_id = output_rr_node->drive_switches[iedge]; + switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); + } + + /* Find the starting points */ + for (const ModulePortId& module_input_port : module_input_ports) { + /* Constrain a path */ + print_pnr_sdc_constrain_module_port2port_timing(fp, + module_manager, cb_module, + module_input_port, module_output_port, + switch_delays[module_input_port]); + } +} + + +/******************************************************************** + * Print SDC timing constraints for a Connection block + * This function is designed for compact routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector>& grids, + const std::vector& switches) { + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + + /* Find the module name and create a SDC file for it */ + std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + /* Validate file stream */ + check_file_handler(fp); + + std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate); + ModuleId cb_module = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR")); + + std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); + + for (size_t side = 0; side < cb_sides.size(); ++side) { + enum e_side cb_ipin_side = cb_sides[side]; + Side side_manager(cb_ipin_side); + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + t_rr_node* ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + print_pnr_sdc_constrain_cb_mux_timing(fp, + module_manager, cb_module, + rr_gsb, cb_type, + grids, switches, + ipin_rr_node); + } + } + + /* Close file handler */ + fp.close(); +} + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and print SDC file for each of them + *******************************************************************/ +static +void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& grids, + const std::vector& switches, + const t_rr_type& cb_type) { + /* Build unique X-direction connection block modules */ + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + if (false == rr_gsb.is_cb_exist(cb_type)) { + continue; + } + print_pnr_sdc_constrain_cb_timing(sdc_dir, + module_manager, + rr_gsb, + cb_type, + grids, switches); + + } + } +} + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and print SDC file for each of them + *******************************************************************/ +static +void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& grids, + const std::vector& switches) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Connection Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, + L_device_rr_gsb, + grids, + switches, + CHANX); + + print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, + L_device_rr_gsb, + grids, + switches, + CHANY); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Print SDC timing constraints for Connection blocks + * This function is designed for compact routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Connection Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + /* Print SDC for unique X-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); + print_pnr_sdc_constrain_cb_timing(sdc_dir, + module_manager, + unique_mirror, + CHANX, + grids, switches); + } + + /* Print SDC for unique Y-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); + print_pnr_sdc_constrain_cb_timing(sdc_dir, + module_manager, + unique_mirror, + CHANY, + grids, switches); + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + /******************************************************************** * Top-level function to print a number of SDC files in different purpose * This function will generate files upon the options provided by users @@ -698,18 +917,23 @@ void print_pnr_sdc(const SdcOption& sdc_options, } } - /* TODO: Output routing constraints for Connection Blocks */ - /* + /* Output routing constraints for Connection Blocks */ if (true == sdc_options.constrain_cb()) { if (true == compact_routing_hierarchy) { - verilog_generate_sdc_constrain_cbs(sdc_opts, LL_nx, LL_ny, LL_device_rr_gsb); + print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(), + module_manager, + grids, + switches, + L_device_rr_gsb); } else { VTR_ASSERT_SAFE (false == compact_routing_hierarchy); - verilog_generate_sdc_constrain_cbs(sdc_opts, - LL_nx, LL_ny); + print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(), + module_manager, + L_device_rr_gsb, + grids, + switches); } } - */ /* TODO: Output routing constraints for Programmable blocks */ /* diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h index aa423b12e..db684ea0a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h @@ -39,7 +39,6 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_ const std::vector>& grids, t_rr_node* src_rr_node); - std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, const ModuleId& cb_module, const RRGSB& rr_gsb, From d226d18d40332d01492861bc25aff091b841256f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 9 Nov 2019 11:54:05 -0700 Subject: [PATCH 454/482] move SDC generator for routing modules to an independent source file --- .../pnr_sdc_routing_writer.cpp | 440 ++++++++++++++++++ .../pnr_sdc_routing_writer.h | 34 ++ .../backend_assistant/pnr_sdc_writer.cpp | 420 +---------------- 3 files changed, 475 insertions(+), 419 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp new file mode 100644 index 000000000..9fbe46b4c --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp @@ -0,0 +1,440 @@ +/******************************************************************** + * This file includes functions that print SDC (Synopsys Design Constraint) + * files in physical design tools, i.e., Place & Route (PnR) tools + * The SDC files are used to constrain the physical design for each routing modules + * in FPGA fabric, such as Switch Blocks (SBs) and Connection Blocks (CBs) + * + * Note that this is different from the SDC to constrain VPR Place&Route + * engine! These SDCs are designed for PnR to generate FPGA layouts!!! + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "device_port.h" + +#include "util.h" +#include "mux_utils.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +#include "build_routing_module_utils.h" + +#include "sdc_writer_naming.h" +#include "sdc_writer_utils.h" +#include "pnr_sdc_routing_writer.h" + +/******************************************************************** + * Find the timing constraints between the inputs and outputs of a routing + * multiplexer in a Switch Block + *******************************************************************/ +static +float find_pnr_sdc_switch_tmax(const t_switch_inf& switch_inf) { + return switch_inf.R * switch_inf.Cout + switch_inf.Tdel; +} + +/******************************************************************** + * Set timing constraints between the inputs and outputs of a routing + * multiplexer in a Switch Block + *******************************************************************/ +static +void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& sb_module, + const RRGSB& rr_gsb, + const std::vector>& grids, + const std::vector& switches, + const e_side& output_node_side, + t_rr_node* output_rr_node) { + /* Validate file stream */ + check_file_handler(fp); + + VTR_ASSERT( ( CHANX == output_rr_node->type ) + || ( CHANY == output_rr_node->type )); + + /* Find the module port corresponding to the output rr_node */ + ModulePortId module_output_port = find_switch_block_module_chan_port(module_manager, + sb_module, + rr_gsb, + output_node_side, + output_rr_node, + OUT_PORT); + + /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ + std::vector input_rr_nodes; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); + } + + std::vector module_input_ports = find_switch_block_module_input_ports(module_manager, + sb_module, + rr_gsb, + grids, + input_rr_nodes); + + /* Find timing constraints for each path (edge) */ + std::map switch_delays; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + /* Get the switch delay */ + int switch_id = output_rr_node->drive_switches[iedge]; + switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); + } + + /* Find the starting points */ + for (const ModulePortId& module_input_port : module_input_ports) { + /* Constrain a path */ + print_pnr_sdc_constrain_module_port2port_timing(fp, + module_manager, sb_module, + module_input_port, module_output_port, + switch_delays[module_input_port]); + } +} + +/******************************************************************** + * Set timing constraints between the inputs and outputs of SBs, + * which are connected by routing multiplexers with the given delays + * specified in architectural XML file + * + * To enable block by block timing constraining, we generate the SDC + * file for each unique SB module + *******************************************************************/ +static +void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const RRGSB& rr_gsb) { + + /* Create the file name for Verilog netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + /* Validate file stream */ + check_file_handler(fp); + + std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR")); + + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + t_rr_node* chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); + /* We only care the output port and it should indicate a SB mux */ + if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + /* Constrain thru wires */ + if (false != rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { + continue; + } + /* This is a MUX, constrain all the paths from an input to an output */ + print_pnr_sdc_constrain_sb_mux_timing(fp, + module_manager, sb_module, + rr_gsb, + grids, switches, + side_manager.get_side(), + chan_rr_node); + } + } + + /* Close file handler */ + fp.close(); +} + +/******************************************************************** + * Print SDC timing constraints for Switch blocks + * This function is designed for flatten routing hierarchy + *******************************************************************/ +void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Switch Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + /* Get the range of SB array */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + /* Go for each SB */ + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + print_pnr_sdc_constrain_sb_timing(sdc_dir, + module_manager, + grids, switches, + rr_gsb); + } + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Print SDC timing constraints for Switch blocks + * This function is designed for compact routing hierarchy + *******************************************************************/ +void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Switch Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { + const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb); + print_pnr_sdc_constrain_sb_timing(sdc_dir, + module_manager, + grids, switches, + rr_gsb); + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Set timing constraints between the inputs and outputs of a routing + * multiplexer in a Connection Block + *******************************************************************/ +static +void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& cb_module, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector>& grids, + const std::vector& switches, + t_rr_node* output_rr_node) { + /* Validate file stream */ + check_file_handler(fp); + + VTR_ASSERT(IPIN == output_rr_node->type); + + /* Find the module port corresponding to the output rr_node */ + ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, + cb_module, + rr_gsb, + grids, output_rr_node); + + /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ + std::vector input_rr_nodes; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); + } + + std::vector module_input_ports = find_connection_block_module_input_ports(module_manager, + cb_module, + rr_gsb, + cb_type, + input_rr_nodes); + + /* Find timing constraints for each path (edge) */ + std::map switch_delays; + for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + /* Get the switch delay */ + int switch_id = output_rr_node->drive_switches[iedge]; + switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); + } + + /* Find the starting points */ + for (const ModulePortId& module_input_port : module_input_ports) { + /* Constrain a path */ + print_pnr_sdc_constrain_module_port2port_timing(fp, + module_manager, cb_module, + module_input_port, module_output_port, + switch_delays[module_input_port]); + } +} + + +/******************************************************************** + * Print SDC timing constraints for a Connection block + * This function is designed for compact routing hierarchy + *******************************************************************/ +static +void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const std::vector>& grids, + const std::vector& switches) { + /* Create the netlist */ + vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + + /* Find the module name and create a SDC file for it */ + std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + /* Validate file stream */ + check_file_handler(fp); + + std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate); + ModuleId cb_module = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR")); + + std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); + + for (size_t side = 0; side < cb_sides.size(); ++side) { + enum e_side cb_ipin_side = cb_sides[side]; + Side side_manager(cb_ipin_side); + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + t_rr_node* ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + print_pnr_sdc_constrain_cb_mux_timing(fp, + module_manager, cb_module, + rr_gsb, cb_type, + grids, switches, + ipin_rr_node); + } + } + + /* Close file handler */ + fp.close(); +} + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and print SDC file for each of them + *******************************************************************/ +static +void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& grids, + const std::vector& switches, + const t_rr_type& cb_type) { + /* Build unique X-direction connection block modules */ + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + if (false == rr_gsb.is_cb_exist(cb_type)) { + continue; + } + print_pnr_sdc_constrain_cb_timing(sdc_dir, + module_manager, + rr_gsb, + cb_type, + grids, switches); + + } + } +} + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and print SDC file for each of them + *******************************************************************/ +void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& grids, + const std::vector& switches) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Connection Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, + L_device_rr_gsb, + grids, + switches, + CHANX); + + print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, + L_device_rr_gsb, + grids, + switches, + CHANY); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + +/******************************************************************** + * Print SDC timing constraints for Connection blocks + * This function is designed for compact routing hierarchy + *******************************************************************/ +void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb) { + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constrain Connection Block timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + /* Print SDC for unique X-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); + print_pnr_sdc_constrain_cb_timing(sdc_dir, + module_manager, + unique_mirror, + CHANX, + grids, switches); + } + + /* Print SDC for unique Y-direction connection block modules */ + for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); + print_pnr_sdc_constrain_cb_timing(sdc_dir, + module_manager, + unique_mirror, + CHANY, + grids, switches); + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h new file mode 100644 index 000000000..c28bfbe26 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h @@ -0,0 +1,34 @@ +#ifndef PNR_SDC_ROUTING_WRITER_H +#define PNR_SDC_ROUTING_WRITER_H + +#include +#include +#include "module_manager.h" +#include "rr_blocks.h" +#include "vpr_types.h" + +void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb); + +void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb); + +void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector>& grids, + const std::vector& switches); + +void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + const std::vector>& grids, + const std::vector& switches, + const DeviceRRGSB& L_device_rr_gsb); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index 70b8f00ab..fcc9f2b2b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -21,10 +21,9 @@ #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" -#include "build_routing_module_utils.h" - #include "sdc_writer_naming.h" #include "sdc_writer_utils.h" +#include "pnr_sdc_routing_writer.h" #include "pnr_sdc_writer.h" /******************************************************************** @@ -430,423 +429,6 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin run_time_sec); } -/******************************************************************** - * Find the timing constraints between the inputs and outputs of a routing - * multiplexer in a Switch Block - *******************************************************************/ -static -float find_pnr_sdc_switch_tmax(const t_switch_inf& switch_inf) { - return switch_inf.R * switch_inf.Cout + switch_inf.Tdel; -} - -/******************************************************************** - * Set timing constraints between the inputs and outputs of a routing - * multiplexer in a Switch Block - *******************************************************************/ -static -void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const std::vector>& grids, - const std::vector& switches, - const e_side& output_node_side, - t_rr_node* output_rr_node) { - /* Validate file stream */ - check_file_handler(fp); - - VTR_ASSERT( ( CHANX == output_rr_node->type ) - || ( CHANY == output_rr_node->type )); - - /* Find the module port corresponding to the output rr_node */ - ModulePortId module_output_port = find_switch_block_module_chan_port(module_manager, - sb_module, - rr_gsb, - output_node_side, - output_rr_node, - OUT_PORT); - - /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ - std::vector input_rr_nodes; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); - } - - std::vector module_input_ports = find_switch_block_module_input_ports(module_manager, - sb_module, - rr_gsb, - grids, - input_rr_nodes); - - /* Find timing constraints for each path (edge) */ - std::map switch_delays; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - /* Get the switch delay */ - int switch_id = output_rr_node->drive_switches[iedge]; - switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); - } - - /* Find the starting points */ - for (const ModulePortId& module_input_port : module_input_ports) { - /* Constrain a path */ - print_pnr_sdc_constrain_module_port2port_timing(fp, - module_manager, sb_module, - module_input_port, module_output_port, - switch_delays[module_input_port]); - } -} - -/******************************************************************** - * Set timing constraints between the inputs and outputs of SBs, - * which are connected by routing multiplexers with the given delays - * specified in architectural XML file - * - * To enable block by block timing constraining, we generate the SDC - * file for each unique SB module - *******************************************************************/ -static -void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector>& grids, - const std::vector& switches, - const RRGSB& rr_gsb) { - - /* Create the file name for Verilog netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - /* Validate file stream */ - check_file_handler(fp); - - std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR")); - - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - t_rr_node* chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); - /* We only care the output port and it should indicate a SB mux */ - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - /* Constrain thru wires */ - if (false != rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { - continue; - } - /* This is a MUX, constrain all the paths from an input to an output */ - print_pnr_sdc_constrain_sb_mux_timing(fp, - module_manager, sb_module, - rr_gsb, - grids, switches, - side_manager.get_side(), - chan_rr_node); - } - } - - /* Close file handler */ - fp.close(); -} - -/******************************************************************** - * Print SDC timing constraints for Switch blocks - * This function is designed for flatten routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector>& grids, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Switch Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - /* Get the range of SB array */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - /* Go for each SB */ - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - print_pnr_sdc_constrain_sb_timing(sdc_dir, - module_manager, - grids, switches, - rr_gsb); - } - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Print SDC timing constraints for Switch blocks - * This function is designed for compact routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector>& grids, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Switch Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb); - print_pnr_sdc_constrain_sb_timing(sdc_dir, - module_manager, - grids, switches, - rr_gsb); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Set timing constraints between the inputs and outputs of a routing - * multiplexer in a Connection Block - *******************************************************************/ -static -void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector>& grids, - const std::vector& switches, - t_rr_node* output_rr_node) { - /* Validate file stream */ - check_file_handler(fp); - - VTR_ASSERT(IPIN == output_rr_node->type); - - /* Find the module port corresponding to the output rr_node */ - ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, - cb_module, - rr_gsb, - grids, output_rr_node); - - /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ - std::vector input_rr_nodes; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); - } - - std::vector module_input_ports = find_connection_block_module_input_ports(module_manager, - cb_module, - rr_gsb, - cb_type, - input_rr_nodes); - - /* Find timing constraints for each path (edge) */ - std::map switch_delays; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - /* Get the switch delay */ - int switch_id = output_rr_node->drive_switches[iedge]; - switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); - } - - /* Find the starting points */ - for (const ModulePortId& module_input_port : module_input_ports) { - /* Constrain a path */ - print_pnr_sdc_constrain_module_port2port_timing(fp, - module_manager, cb_module, - module_input_port, module_output_port, - switch_delays[module_input_port]); - } -} - - -/******************************************************************** - * Print SDC timing constraints for a Connection block - * This function is designed for compact routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector>& grids, - const std::vector& switches) { - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - - /* Find the module name and create a SDC file for it */ - std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - /* Validate file stream */ - check_file_handler(fp); - - std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate); - ModuleId cb_module = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR")); - - std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); - - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - Side side_manager(cb_ipin_side); - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - t_rr_node* ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - print_pnr_sdc_constrain_cb_mux_timing(fp, - module_manager, cb_module, - rr_gsb, cb_type, - grids, switches, - ipin_rr_node); - } - } - - /* Close file handler */ - fp.close(); -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and print SDC file for each of them - *******************************************************************/ -static -void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& grids, - const std::vector& switches, - const t_rr_type& cb_type) { - /* Build unique X-direction connection block modules */ - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if (false == rr_gsb.is_cb_exist(cb_type)) { - continue; - } - print_pnr_sdc_constrain_cb_timing(sdc_dir, - module_manager, - rr_gsb, - cb_type, - grids, switches); - - } - } -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and print SDC file for each of them - *******************************************************************/ -static -void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& grids, - const std::vector& switches) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Connection Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, - L_device_rr_gsb, - grids, - switches, - CHANX); - - print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, - L_device_rr_gsb, - grids, - switches, - CHANY); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Print SDC timing constraints for Connection blocks - * This function is designed for compact routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector>& grids, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Connection Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - /* Print SDC for unique X-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); - print_pnr_sdc_constrain_cb_timing(sdc_dir, - module_manager, - unique_mirror, - CHANX, - grids, switches); - } - - /* Print SDC for unique Y-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); - print_pnr_sdc_constrain_cb_timing(sdc_dir, - module_manager, - unique_mirror, - CHANY, - grids, switches); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - /******************************************************************** * Top-level function to print a number of SDC files in different purpose * This function will generate files upon the options provided by users From bcd823726354c85e47746689b00f10d25f7a181c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 9 Nov 2019 20:57:54 -0700 Subject: [PATCH 455/482] refactored grid PnR SDC generator --- .../backend_assistant/pnr_sdc_grid_writer.cpp | 361 ++++++++++++++++++ .../backend_assistant/pnr_sdc_grid_writer.h | 11 + .../pnr_sdc_routing_writer.cpp | 10 +- .../backend_assistant/pnr_sdc_writer.cpp | 9 +- .../backend_assistant/sdc_writer_utils.cpp | 44 ++- .../backend_assistant/sdc_writer_utils.h | 10 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- 7 files changed, 424 insertions(+), 23 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp new file mode 100644 index 000000000..8032daca4 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp @@ -0,0 +1,361 @@ +/******************************************************************** + * This file includes functions that print SDC (Synopsys Design Constraint) + * files in physical design tools, i.e., Place & Route (PnR) tools + * The SDC files are used to constrain the physical design for each grid + * (CLBs, heterogeneous blocks etc.) + * + * Note that this is different from the SDC to constrain VPR Place&Route + * engine! These SDCs are designed for PnR to generate FPGA layouts!!! + *******************************************************************/ +#include +#include + +#include "vtr_assert.h" +#include "device_port.h" + +#include "util.h" +#include "mux_utils.h" + +#include "fpga_x2p_reserved_words.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" + +#include "sdc_writer_naming.h" +#include "sdc_writer_utils.h" +#include "pnr_sdc_grid_writer.h" + +#include "globals.h" + +/******************************************************************** + * Print pin-to-pin timing constraints for a given interconnection + * at an output port of a pb_graph node + *******************************************************************/ +static +void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const e_side& border_side, + t_pb_graph_pin* des_pb_graph_pin, + t_mode* physical_mode) { + + /* Validate file stream */ + check_file_handler(fp); + + /* 1. identify pin interconnection type, + * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) + * 3. Print SDC timing constraints + */ + int fan_in = 0; + t_interconnect* cur_interc = NULL; + find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); + if ((NULL == cur_interc) || (0 == fan_in)) { + /* No interconnection matched */ + return; + } + + /* Print pin-to-pin SDC contraint here */ + /* For more than one mode defined, the direct interc has more than one input_edge , + * We need to find which edge is connected the pin we want + */ + for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { + if (cur_interc != des_pb_graph_pin->input_edges[iedge]->interconnect) { + continue; + } + + /* Source pin, node, pb_type*/ + t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; + t_pb_graph_node* src_pb_graph_node = src_pb_graph_pin->parent_node; + /* Des pin, node, pb_type */ + t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node; + + /* Find the src module in module manager */ + std::string src_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string src_module_name = generate_physical_block_module_name(src_module_name_prefix, src_pb_graph_pin->parent_node->pb_type); + ModuleId src_module = module_manager.find_module(src_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(src_module)); + + ModulePortId src_module_port_id = module_manager.find_module_port(src_module, generate_pb_type_port_name(src_pb_graph_pin->port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(src_module, src_module_port_id)); + + /* Generate the name of the des instance name + * If des module is not the parent module, it is a child module. + * We should find the instance id + */ + std::string src_instance_name = src_module_name; + if (parent_module != src_module) { + src_instance_name = module_manager.module_name(parent_module) + std::string("/"); + /* Instance id is actually the placement index */ + size_t instance_id = src_pb_graph_node->placement_index; + if (true == module_manager.instance_name(parent_module, src_module, instance_id).empty()) { + src_instance_name += src_module_name; + src_instance_name += "_"; + src_instance_name += std::to_string(instance_id); + src_instance_name += "_"; + } else { + src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id); + } + } + + /* Generate src port information */ + BasicPort src_port = module_manager.module_port(src_module, src_module_port_id); + src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number); + + /* Find the des module in module manager */ + std::string des_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string des_module_name = generate_physical_block_module_name(des_module_name_prefix, des_pb_graph_pin->parent_node->pb_type); + ModuleId des_module = module_manager.find_module(des_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(des_module)); + ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port)); + VTR_ASSERT(true == module_manager.valid_module_port_id(des_module, des_module_port_id)); + + /* Generate the name of the des instance name + * If des module is not the parent module, it is a child module. + * We should find the instance id + */ + std::string des_instance_name = des_module_name; + if (parent_module != des_module) { + des_instance_name = module_manager.module_name(parent_module) + std::string("/"); + /* Instance id is actually the placement index */ + size_t instance_id = des_pb_graph_node->placement_index; + if (true == module_manager.instance_name(parent_module, des_module, instance_id).empty()) { + des_instance_name += des_module_name; + des_instance_name += "_"; + des_instance_name += std::to_string(instance_id); + des_instance_name += "_"; + } else { + des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id); + } + } + + /* Generate des port information */ + BasicPort des_port = module_manager.module_port(des_module, des_module_port_id); + des_port.set_width(des_pb_graph_pin->pin_number, des_pb_graph_pin->pin_number); + + /* Print a SDC timing constraint */ + print_pnr_sdc_constrain_max_delay(fp, + src_instance_name, + generate_sdc_port(src_port), + des_instance_name, + generate_sdc_port(des_port), + des_pb_graph_pin->input_edges[iedge]->delay_max); + } +} + +/******************************************************************** + * Print port-to-port timing constraints which source from + * an output port of a pb_graph node + *******************************************************************/ +static +void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const e_side& border_side, + t_pb_graph_node* des_pb_graph_node, + const e_spice_pb_port_type& pb_port_type, + t_mode* physical_mode) { + /* Validate file stream */ + check_file_handler(fp); + + switch (pb_port_type) { + case SPICE_PB_PORT_INPUT: { + for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { + /* If this is a idle block, we set 0 to the selected edge*/ + /* Get the selected edge of current pin*/ + print_pnr_sdc_constrain_pb_pin_interc_timing(fp, module_manager, parent_module, border_side, + &(des_pb_graph_node->input_pins[iport][ipin]), + physical_mode); + } + } + break; + } + case SPICE_PB_PORT_OUTPUT: { + for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { + print_pnr_sdc_constrain_pb_pin_interc_timing(fp, module_manager, parent_module, border_side, + &(des_pb_graph_node->output_pins[iport][ipin]), + physical_mode); + } + } + break; + } + case SPICE_PB_PORT_CLOCK: { + /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */ + break; + } + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid pb port type!\n", + __FILE__, __LINE__); + exit(1); + } +} + +/******************************************************************** + * This function will generate a SDC file for each pb_type, + * constraining the pin-to-pin timing between + * 1. input port of parent_pb_graph_node and input port of child_pb_graph_nodes + * 2. output port of parent_pb_graph_node and output port of child_pb_graph_nodes + * 3. output port of child_pb_graph_node and input port of child_pb_graph_nodes + *******************************************************************/ +static +void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + t_pb_graph_node* parent_pb_graph_node, + const int& physical_mode_index, + const e_side& border_side) { + + /* Get the pb_type definition related to the node */ + t_pb_type* physical_pb_type = parent_pb_graph_node->pb_type; + std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); + + /* Find the pb module in module manager */ + ModuleId pb_module = module_manager.find_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); + + /* Create the file name for SDC */ + std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX)); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR")); + + t_mode* physical_mode = &(parent_pb_graph_node->pb_type->modes[physical_mode_index]); + + /* We check output_pins of cur_pb_graph_node and its the input_edges + * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node + * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins + * /|\ + * | + * input_pins, edges, output_pins + */ + print_pnr_sdc_constrain_pb_interc_timing(fp, module_manager, pb_module, border_side, + parent_pb_graph_node, + SPICE_PB_PORT_OUTPUT, + physical_mode); + + /* We check input_pins of child_pb_graph_node and its the input_edges + * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node + * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins + * /|\ + * | + * input_pins, edges, output_pins + */ + for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) { + for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) { + t_pb_graph_node* child_pb_graph_node = &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb]); + /* For each child_pb_graph_node input pins*/ + print_pnr_sdc_constrain_pb_interc_timing(fp, module_manager, pb_module, border_side, + child_pb_graph_node, + SPICE_PB_PORT_INPUT, + physical_mode); + /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */ + } + } + + /* Close file handler */ + fp.close(); +} + +/******************************************************************** + * Recursively print SDC timing constraints for a pb_type + * This function will generate a SDC file for each pb_type, + * constraining the pin-to-pin timing + *******************************************************************/ +static +void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir, + const ModuleManager& module_manager, + t_pb_graph_node* parent_pb_graph_node, + const e_side& border_side) { + /* Validate pb_graph node */ + if (NULL == parent_pb_graph_node) { + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d]) Invalid parent_pb_graph_node.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Get the pb_type */ + t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type; + + /* No need to constrain the primitive node */ + if (TRUE == is_primitive_pb_type(parent_pb_type)) { + return; + } + + /* Note we only go through the graph through the physical modes. + * which we build the modules + */ + int physical_mode_index = find_pb_type_physical_mode_index((*parent_pb_type)); + + /* Write a SDC file for this pb_type */ + print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir, module_manager, + parent_pb_graph_node, physical_mode_index, + border_side); + + /* Go recursively to the lower level in the pb_graph + * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type + */ + for (int ipb = 0; ipb < parent_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { + rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, + &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), + border_side); + } +} + +/******************************************************************** + * Top-level function to print timing constraints for pb_types + *******************************************************************/ +void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, + const ModuleManager& module_manager) { + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for constraining grid timing for P&R flow..."); + + /* Start time count */ + clock_t t_start = clock(); + + for (int itype = 0; itype < num_types; itype++) { + /* Bypass EMPTY types */ + if (EMPTY_TYPE == &type_descriptors[itype]) { + continue; + } + + /* For IO_TYPE, we have four types of I/Os */ + if (IO_TYPE == &type_descriptors[itype]) { + /* Special for I/O block, generate one module for each border side */ + for (int iside = 0; iside < NUM_SIDES; iside++) { + Side side_manager(iside); + rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, + type_descriptors[itype].pb_graph_head, + side_manager.get_side()); + } + } else if (FILL_TYPE == &type_descriptors[itype]) { + /* For CLB */ + rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, + type_descriptors[itype].pb_graph_head, + NUM_SIDES); + } else { + /* For heterogenenous blocks */ + rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, + type_descriptors[itype].pb_graph_head, + NUM_SIDES); + } + } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h new file mode 100644 index 000000000..d27b292ef --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h @@ -0,0 +1,11 @@ +#ifndef PNR_SDC_GRID_WRITER_H +#define PNR_SDC_GRID_WRITER_H + +#include +#include +#include "vpr_types.h" + +void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, + const ModuleManager& module_manager); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp index 9fbe46b4c..13bc17d1c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp @@ -85,8 +85,9 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, for (const ModulePortId& module_input_port : module_input_ports) { /* Constrain a path */ print_pnr_sdc_constrain_module_port2port_timing(fp, - module_manager, sb_module, - module_input_port, module_output_port, + module_manager, + sb_module, module_input_port, + sb_module, module_output_port, switch_delays[module_input_port]); } } @@ -267,8 +268,9 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, for (const ModulePortId& module_input_port : module_input_ports) { /* Constrain a path */ print_pnr_sdc_constrain_module_port2port_timing(fp, - module_manager, cb_module, - module_input_port, module_output_port, + module_manager, + cb_module, module_input_port, + cb_module, module_output_port, switch_delays[module_input_port]); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index fcc9f2b2b..b5f58bf90 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -24,6 +24,7 @@ #include "sdc_writer_naming.h" #include "sdc_writer_utils.h" #include "pnr_sdc_routing_writer.h" +#include "pnr_sdc_grid_writer.h" #include "pnr_sdc_writer.h" /******************************************************************** @@ -517,11 +518,9 @@ void print_pnr_sdc(const SdcOption& sdc_options, } } - /* TODO: Output routing constraints for Programmable blocks */ - /* + /* Output Timing constraints for Programmable blocks */ if (true == sdc_options.constrain_grid()) { - verilog_generate_sdc_constrain_pb_types(cur_sram_orgz_info, - sdc_dir); + print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(), + module_manager); } - */ } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp index 6a74c290d..13e3e6ba0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp @@ -53,29 +53,49 @@ std::string generate_sdc_port(const BasicPort& port) { } /******************************************************************** - * Constrain a path between two ports of a module with a given timing value + * Constrain a path between two ports of a module with a given maximum timing value *******************************************************************/ -void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const ModulePortId& module_input_port_id, - const ModulePortId& module_output_port_id, - const float& tmax) { +void print_pnr_sdc_constrain_max_delay(std::fstream& fp, + const std::string& src_instance_name, + const std::string& src_port_name, + const std::string& des_instance_name, + const std::string& des_port_name, + const float& delay) { /* Validate file stream */ check_file_handler(fp); fp << "set_max_delay"; fp << " -from "; - fp << module_manager.module_name(module_id) << "/"; - fp << generate_sdc_port(module_manager.module_port(module_id, module_input_port_id)); + fp << src_instance_name << "/"; + fp << src_port_name; fp << " -to "; - fp << module_manager.module_name(module_id) << "/"; - fp << generate_sdc_port(module_manager.module_port(module_id, module_output_port_id)); + fp << des_instance_name << "/"; + fp << des_port_name; - fp << " " << std::setprecision(10) << tmax; + fp << " " << std::setprecision(10) << delay; fp << std::endl; } + +/******************************************************************** + * Constrain a path between two ports of a module with a given timing value + * Note: this function uses set_max_delay !!! + *******************************************************************/ +void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& input_parent_module_id, + const ModulePortId& module_input_port_id, + const ModuleId& output_parent_module_id, + const ModulePortId& module_output_port_id, + const float& tmax) { + print_pnr_sdc_constrain_max_delay(fp, + module_manager.module_name(input_parent_module_id), + generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)), + module_manager.module_name(output_parent_module_id), + generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)), + tmax); + +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h index d4c2ae860..25684ca96 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h @@ -11,10 +11,18 @@ void print_sdc_file_header(std::fstream& fp, std::string generate_sdc_port(const BasicPort& port); +void print_pnr_sdc_constrain_max_delay(std::fstream& fp, + const std::string& src_instance_name, + const std::string& src_port_name, + const std::string& des_instance_name, + const std::string& des_port_name, + const float& delay); + void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& module_id, + const ModuleId& input_parent_module_id, const ModulePortId& module_input_port_id, + const ModuleId& output_parent_module_id, const ModulePortId& module_output_port_id, const float& tmax); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index a254d4824..8fa4709f1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -159,7 +159,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* TODO: the critical path delay unit should be explicit! */ fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, - grids, rr_switches, device_rr_gsb, + grids, rr_switches, device_rr_gsb, module_manager, mux_lib, Arch.spice->circuit_lib, global_ports, TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); From 1f368abfbeb7c2368a4c4aac388293ed6f636bf0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Nov 2019 15:40:54 -0700 Subject: [PATCH 456/482] refactoring analysis SDC generation --- .../backend_assistant/analysis_sdc_writer.cpp | 260 ++++++++++++++++++ .../backend_assistant/analysis_sdc_writer.h | 22 ++ .../fpga_x2p/backend_assistant/sdc_api.cpp | 15 + .../SRC/fpga_x2p/backend_assistant/sdc_api.h | 4 + .../backend_assistant/sdc_writer_naming.h | 2 + .../backend_assistant/sdc_writer_utils.cpp | 71 +++++ .../backend_assistant/sdc_writer_utils.h | 13 + vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 1 + 8 files changed, 388 insertions(+) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp new file mode 100644 index 000000000..4a5fe91c3 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -0,0 +1,260 @@ +/******************************************************************** + * This file includes functions that are used to output a SDC file + * that constrain a FPGA fabric (P&Red netlist) using a benchmark + *******************************************************************/ +#include +#include +#include + +#include "vtr_assert.h" +#include "device_port.h" + +#include "util.h" +#include "mux_utils.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" +#include "fpga_x2p_benchmark_utils.h" + +#include "sdc_writer_naming.h" +#include "sdc_writer_utils.h" + +#include "analysis_sdc_writer.h" + +/******************************************************************** + * Generate SDC constaints for inputs and outputs + * We consider the top module in formal verification purpose here + * which is easier + *******************************************************************/ +static +void print_analysis_sdc_io_delays(std::fstream& fp, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const float& critical_path_delay) { + /* Validate the file stream */ + check_file_handler(fp); + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Create clock " << std::endl; + fp << "##################################################" << std::endl; + + /* Get clock port from the global port */ + std::vector operating_clock_ports; + for (const CircuitPortId& clock_port : global_ports) { + if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) { + continue; + } + /* We only constrain operating clock here! */ + if (true == circuit_lib.port_is_prog(clock_port)) { + continue; + } + + /* Update the operating port list */ + operating_clock_ports.push_back(BasicPort(circuit_lib.port_prefix(clock_port), circuit_lib.port_size(clock_port))); + } + + for (const BasicPort& operating_clock_port : operating_clock_ports) { + /* Reach here, it means a clock port and we need print constraints */ + fp << "create_clock "; + fp << generate_sdc_port(operating_clock_port); + fp << " -period " << std::setprecision(10) << critical_path_delay; + fp << " -waveform {0 " << std::setprecision(10) << critical_path_delay / 2 << "}"; + fp << std::endl; + + /* Add an empty line as a splitter */ + fp << std::endl; + } + + /* There should be only one operating clock! + * TODO: this should be changed when developing multi-clock support!!! + */ + VTR_ASSERT(1 == operating_clock_ports.size()); + + /* In this function, we support only 1 type of I/Os */ + VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size()); + BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0]; + + /* Keep tracking which I/Os have been used */ + std::vector io_used(module_io_port.get_width(), false); + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Create input and output delays for used I/Os " << std::endl; + fp << "##################################################" << std::endl; + + for (const t_logical_block& io_lb : L_logical_blocks) { + /* We only care I/O logical blocks !*/ + if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) { + continue; + } + + /* clock net or constant generator should be disabled in timing analysis */ + if (TRUE == io_lb.is_clock) { + continue; + } + + /* Find the index of the mapped GPIO in top-level FPGA fabric */ + size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks); + + /* Ensure that IO index is in range */ + BasicPort module_mapped_io_port = module_io_port; + /* Set the port pin index */ + VTR_ASSERT(io_index < module_mapped_io_port.get_width()); + module_mapped_io_port.set_width(io_index, io_index); + + /* For input I/O, we set an input delay constraint correlated to the operating clock + * For output I/O, we set an output delay constraint correlated to the operating clock + */ + if (VPACK_INPAD == io_lb.type) { + print_sdc_set_port_input_delay(fp, module_mapped_io_port, + operating_clock_ports[0], critical_path_delay); + } else { + VTR_ASSERT(VPACK_OUTPAD == io_lb.type); + print_sdc_set_port_output_delay(fp, module_mapped_io_port, + operating_clock_ports[0], critical_path_delay); + } + + /* Mark this I/O has been used/wired */ + io_used[io_index] = true; + } + + /* Add an empty line as a splitter */ + fp << std::endl; + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Disable timing for unused I/Os " << std::endl; + fp << "##################################################" << std::endl; + + /* Wire the unused iopads to a constant */ + for (size_t io_index = 0; io_index < io_used.size(); ++io_index) { + /* Bypass used iopads */ + if (true == io_used[io_index]) { + continue; + } + + /* Wire to a contant */ + BasicPort module_unused_io_port = module_io_port; + /* Set the port pin index */ + module_unused_io_port.set_width(io_index, io_index); + print_sdc_disable_port_timing(fp, module_unused_io_port); + } + + /* Add an empty line as a splitter */ + fp << std::endl; +} + +/******************************************************************** + * Top-level function outputs a SDC file + * that constrain a FPGA fabric (P&Red netlist) using a benchmark + *******************************************************************/ +void print_analysis_sdc(const std::string& sdc_dir, + const float& critical_path_delay, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const bool& compact_routing_hierarchy) { + /* Create the file name for Verilog netlist */ + std::string sdc_fname(sdc_dir + std::string(SDC_ANALYSIS_FILE_NAME)); + + vpr_printf(TIO_MESSAGE_INFO, + "Generating SDC for Timing/Power analysis on the mapped FPGA: %s ...", + sdc_fname.c_str()); + + /* Start time count */ + clock_t t_start = clock(); + + /* Create the file stream */ + std::fstream fp; + fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); + + /* Validate file stream */ + check_file_handler(fp); + + /* Generate the descriptions*/ + print_sdc_file_header(fp, std::string("Constrain for Timing/Power analysis on the mapped FPGA")); + + /* Find the top_module */ + ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + + /* Create clock and set I/O ports with input/output delays */ + print_analysis_sdc_io_delays(fp, + L_logical_blocks, device_size, L_grids, L_blocks, + module_manager, top_module, + circuit_lib, global_ports, + critical_path_delay); + + /* TODO: Disable the timing for global ports */ + /* + verilog_generate_sdc_disable_global_ports(fp); + */ + + /* TODO: Disable the timing for configuration cells */ + /* + verilog_generate_sdc_disable_sram_orgz(fp, cur_sram_orgz_info); + */ + + /* TODO: Disable timing for un-used resources */ + /* Apply to Routing Channels */ + /* + if (TRUE == compact_routing_hierarchy) { + verilog_generate_sdc_disable_unused_routing_channels(fp, LL_nx, LL_ny); + } else { + verilog_generate_sdc_disable_unused_routing_channels(fp, LL_nx, LL_ny, + LL_num_rr_nodes, LL_rr_node, + LL_rr_node_indices); + } + */ + + /* TODO: Apply to Connection blocks */ + /* + if (TRUE == compact_routing_hierarchy) { + verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny, LL_device_rr_gsb); + verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny, LL_device_rr_gsb); + } else { + verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny); + verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny); + } + */ + + /* TODO: Apply to Switch blocks */ + /* + if (TRUE == compact_routing_hierarchy) { + verilog_generate_sdc_disable_unused_sbs(fp); + verilog_generate_sdc_disable_unused_sbs_muxs(fp); + } else { + verilog_generate_sdc_disable_unused_sbs(fp, LL_nx, LL_ny); + verilog_generate_sdc_disable_unused_sbs_muxs(fp, LL_nx, LL_ny); + } + */ + + /* TODO: Apply to Grids */ + /* + verilog_generate_sdc_disable_unused_grids(fp, LL_nx, LL_ny, LL_grid, LL_block); + verilog_generate_sdc_disable_unused_grids_muxs(fp, LL_nx, LL_ny, LL_grid, LL_block); + */ + + /* Close file handler */ + fp.close(); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h new file mode 100644 index 000000000..252c76c71 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h @@ -0,0 +1,22 @@ +#ifndef ANALYSIS_SDC_WRITER_H +#define ANALYSIS_SDC_WRITER_H + +#include +#include "vpr_types.h" +#include "rr_blocks.h" +#include "module_manager.h" +#include "bitstream_manager.h" + +void print_analysis_sdc(const std::string& sdc_dir, + const float& critical_path_delay, + const DeviceRRGSB& L_device_rr_gsb, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports, + const bool& compact_routing_hierarchy); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index 690e456c5..bf9f17858 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -3,6 +3,7 @@ *******************************************************************/ #include #include "pnr_sdc_writer.h" +#include "analysis_sdc_writer.h" #include "sdc_api.h" @@ -14,6 +15,10 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const std::vector>& grids, const std::vector& switches, const DeviceRRGSB& L_device_rr_gsb, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, @@ -33,6 +38,16 @@ void fpga_sdc_generator(const SdcOption& sdc_options, compact_routing_hierarchy); } + if (true == sdc_options.generate_sdc_analysis()) { + print_analysis_sdc(sdc_options.sdc_dir(), + critical_path_delay, + L_device_rr_gsb, + L_logical_blocks, device_size, L_grids, L_blocks, + module_manager, + circuit_lib, global_ports, + compact_routing_hierarchy); + } + /* End time count */ clock_t t_end = clock(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h index d53dc201a..02874e3a3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h @@ -12,6 +12,10 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const std::vector>& grids, const std::vector& switches, const DeviceRRGSB& L_device_rr_gsb, + const std::vector& L_logical_blocks, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, const ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h index e479f95d3..9a9f3af29 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h @@ -10,4 +10,6 @@ constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer constexpr char* SDC_DISABLE_SB_OUTPUTS_FILE_NAME = "disable_sb_outputs.sdc"; constexpr char* SDC_CB_FILE_NAME = "cb.sdc"; +constexpr char* SDC_ANALYSIS_FILE_NAME = "fpga_top_analysis.sdc"; + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp index 13e3e6ba0..0613cac7a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp @@ -99,3 +99,74 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, tmax); } + +/******************************************************************** + * Disable timing for a port + *******************************************************************/ +void print_sdc_disable_port_timing(std::fstream& fp, + const BasicPort& port) { + /* Validate file stream */ + check_file_handler(fp); + + fp << "set_disable_timing "; + + fp << generate_sdc_port(port); + + fp << std::endl; +} + +/******************************************************************** + * Set the input delay for a port in SDC format + * Note that the input delay will be bounded by a clock port + *******************************************************************/ +void print_sdc_set_port_input_delay(std::fstream& fp, + const BasicPort& port, + const BasicPort& clock_port, + const float& delay) { + /* Validate file stream */ + check_file_handler(fp); + + fp << "set_input_delay "; + + fp << "-clock "; + + fp << generate_sdc_port(clock_port); + + fp << " -max "; + + fp << std::setprecision(10) << delay; + + fp << " "; + + fp << generate_sdc_port(port); + + fp << std::endl; +} + +/******************************************************************** + * Set the output delay for a port in SDC format + * Note that the output delay will be bounded by a clock port + *******************************************************************/ +void print_sdc_set_port_output_delay(std::fstream& fp, + const BasicPort& port, + const BasicPort& clock_port, + const float& delay) { + /* Validate file stream */ + check_file_handler(fp); + + fp << "set_output_delay "; + + fp << "-clock "; + + fp << generate_sdc_port(clock_port); + + fp << " -max "; + + fp << std::setprecision(10) << delay; + + fp << " "; + + fp << generate_sdc_port(port); + + fp << std::endl; +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h index 25684ca96..9483f0379 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h @@ -26,4 +26,17 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, const ModulePortId& module_output_port_id, const float& tmax); +void print_sdc_disable_port_timing(std::fstream& fp, + const BasicPort& port); + +void print_sdc_set_port_input_delay(std::fstream& fp, + const BasicPort& port, + const BasicPort& clock_port, + const float& delay); + +void print_sdc_set_port_output_delay(std::fstream& fp, + const BasicPort& port, + const BasicPort& clock_port, + const float& delay); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 8fa4709f1..edff64348 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -160,6 +160,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, grids, rr_switches, device_rr_gsb, + L_logical_blocks, device_size, grids, L_blocks, module_manager, mux_lib, Arch.spice->circuit_lib, global_ports, TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); From 67b3b25bea66f3e971060e487e3b0128f3fb9c78 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Nov 2019 16:08:49 -0700 Subject: [PATCH 457/482] refactoring analysis sdc generation --- .../backend_assistant/analysis_sdc_writer.cpp | 64 +++++++++++++------ .../backend_assistant/pnr_sdc_writer.cpp | 55 +--------------- .../backend_assistant/sdc_memory_utils.cpp | 62 ++++++++++++++++++ .../backend_assistant/sdc_memory_utils.h | 13 ++++ 4 files changed, 120 insertions(+), 74 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index 4a5fe91c3..a85a2ae3d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -18,6 +18,7 @@ #include "sdc_writer_naming.h" #include "sdc_writer_utils.h" +#include "sdc_memory_utils.h" #include "analysis_sdc_writer.h" @@ -56,8 +57,9 @@ void print_analysis_sdc_io_delays(std::fstream& fp, continue; } - /* Update the operating port list */ - operating_clock_ports.push_back(BasicPort(circuit_lib.port_prefix(clock_port), circuit_lib.port_size(clock_port))); + /* Find the module port and Update the operating port list */ + ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(clock_port)); + operating_clock_ports.push_back(module_manager.module_port(top_module, module_port)); } for (const BasicPort& operating_clock_port : operating_clock_ports) { @@ -151,6 +153,37 @@ void print_analysis_sdc_io_delays(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Disable the timing for all the global port except the operating clock ports + *******************************************************************/ +static +void print_analysis_sdc_disable_global_ports(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Validate file stream */ + check_file_handler(fp); + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Disable timing for global ports " << std::endl; + fp << "##################################################" << std::endl; + + for (const CircuitPortId& global_port : global_ports) { + /* Skip operating clock here! */ + if ( (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) + && (false == circuit_lib.port_is_prog(global_port)) ) { + continue; + } + + ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port)); + BasicPort port_to_disable = module_manager.module_port(top_module, module_port); + + print_sdc_disable_port_timing(fp, port_to_disable); + } +} + /******************************************************************** * Top-level function outputs a SDC file * that constrain a FPGA fabric (P&Red netlist) using a benchmark @@ -197,27 +230,18 @@ void print_analysis_sdc(const std::string& sdc_dir, circuit_lib, global_ports, critical_path_delay); - /* TODO: Disable the timing for global ports */ - /* - verilog_generate_sdc_disable_global_ports(fp); - */ + /* Disable the timing for global ports */ + print_analysis_sdc_disable_global_ports(fp, + module_manager, top_module, + circuit_lib, global_ports); + + /* Disable the timing for configuration cells */ + rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, + module_manager, top_module, + format_dir_path(module_manager.module_name(top_module))); - /* TODO: Disable the timing for configuration cells */ - /* - verilog_generate_sdc_disable_sram_orgz(fp, cur_sram_orgz_info); - */ /* TODO: Disable timing for un-used resources */ - /* Apply to Routing Channels */ - /* - if (TRUE == compact_routing_hierarchy) { - verilog_generate_sdc_disable_unused_routing_channels(fp, LL_nx, LL_ny); - } else { - verilog_generate_sdc_disable_unused_routing_channels(fp, LL_nx, LL_ny, - LL_num_rr_nodes, LL_rr_node, - LL_rr_node_indices); - } - */ /* TODO: Apply to Connection blocks */ /* diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp index b5f58bf90..771e4ba22 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp @@ -23,6 +23,7 @@ #include "sdc_writer_naming.h" #include "sdc_writer_utils.h" +#include "sdc_memory_utils.h" #include "pnr_sdc_routing_writer.h" #include "pnr_sdc_grid_writer.h" #include "pnr_sdc_writer.h" @@ -142,60 +143,6 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir, run_time_sec); } -/******************************************************************** - * Print SDC commands to disable outputs of all the configurable memory modules - * in a given module - * This function will be executed in a recursive way, - * using a Depth-First Search (DFS) strategy - * It will iterate over all the configurable children under each module - * and print a SDC command to disable its outputs - *******************************************************************/ -static -void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_module_path) { - - /* For each configurable child, we will go one level down in priority */ - for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) { - std::string child_module_path = parent_module_path; - ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index]; - size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index]; - if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) { - /* Give a default name __ */ - child_module_path += module_manager.module_name(child_module_id); - child_module_path += "_"; - child_module_path += std::to_string(child_instance_id); - child_module_path += "_"; - } else { - child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id); - } - child_module_path = format_dir_path(child_module_path); - - rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, - child_module_id, - child_module_path); - } - - /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */ - if (0 < module_manager.configurable_children(parent_module).size()) { - return; - } - - /* Validate file stream */ - check_file_handler(fp); - - /* Disable timing for each output port of this module */ - for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) { - for (const size_t& pin : output_port.pins()) { - BasicPort output_pin(output_port.get_name(), pin, pin); - fp << "set_disable_timing "; - fp << parent_module_path << generate_sdc_port(output_pin); - fp << std::endl; - } - } -} - /******************************************************************** * Break combinational loops in FPGA fabric, which mainly come from * configurable memory cells. diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp new file mode 100644 index 000000000..6df5ede5f --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp @@ -0,0 +1,62 @@ +/******************************************************************** + * Most utilized function used to constrain memory cells in FPGA + * fabric using SDC commands + *******************************************************************/ +#include "fpga_x2p_utils.h" +#include "sdc_writer_utils.h" + +#include "sdc_memory_utils.h" + +/******************************************************************** + * Print SDC commands to disable outputs of all the configurable memory modules + * in a given module + * This function will be executed in a recursive way, + * using a Depth-First Search (DFS) strategy + * It will iterate over all the configurable children under each module + * and print a SDC command to disable its outputs + *******************************************************************/ +void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_module_path) { + + /* For each configurable child, we will go one level down in priority */ + for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) { + std::string child_module_path = parent_module_path; + ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index]; + size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index]; + if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) { + /* Give a default name __ */ + child_module_path += module_manager.module_name(child_module_id); + child_module_path += "_"; + child_module_path += std::to_string(child_instance_id); + child_module_path += "_"; + } else { + child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id); + } + child_module_path = format_dir_path(child_module_path); + + rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, + child_module_id, + child_module_path); + } + + /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */ + if (0 < module_manager.configurable_children(parent_module).size()) { + return; + } + + /* Validate file stream */ + check_file_handler(fp); + + /* Disable timing for each output port of this module */ + for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) { + for (const size_t& pin : output_port.pins()) { + BasicPort output_pin(output_port.get_name(), pin, pin); + fp << "set_disable_timing "; + fp << parent_module_path << generate_sdc_port(output_pin); + fp << std::endl; + } + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h new file mode 100644 index 000000000..9ce57d6d8 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h @@ -0,0 +1,13 @@ +#ifndef SDC_MEMORY_UTILS_H +#define SDC_MEMORY_UTILS_H + +#include +#include +#include "module_manager.h" + +void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_module_path); + +#endif From 3d711823e53f9c31abd78834badbad82b09ee76c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Nov 2019 18:15:13 -0700 Subject: [PATCH 458/482] refactoring SDC generator for unused CBs --- .../analysis_sdc_routing_writer.cpp | 240 ++++++++++++++++++ .../analysis_sdc_routing_writer.h | 15 ++ .../backend_assistant/analysis_sdc_writer.cpp | 21 +- .../fpga_x2p/backend_assistant/sdc_api.cpp | 2 +- 4 files changed, 263 insertions(+), 15 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp new file mode 100644 index 000000000..93cf918ce --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp @@ -0,0 +1,240 @@ +/******************************************************************** + * This file includes functions that are used to output a SDC file + * that constrain routing modules of a FPGA fabric (P&Red netlist) + * using a benchmark + *******************************************************************/ +#include "vtr_assert.h" +#include "device_port.h" + +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + + +#include "sdc_writer_utils.h" +#include "analysis_sdc_routing_writer.h" + +#include "globals.h" + +/******************************************************************** + * Identify if a node should be disabled during analysis SDC generation + *******************************************************************/ +static +bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { + /* Conditions to enable timing analysis for a node + * 1st condition: it have a valid vpack_net_number + * 2nd condition: it is not an parasitic net + * 3rd condition: it is not a global net + */ + if ( (OPEN != cur_rr_node->vpack_net_num) + && (FALSE == cur_rr_node->is_parasitic_net) + && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_global) + && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_const_gen) ){ + return false; + } + return true; +} + +/******************************************************************** + * This function will disable + * 1. all the unused port (unmapped by a benchmark) of a connection block + * 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers + * in a connection block + *******************************************************************/ +static +void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, + const std::vector>& grids, + const DeviceRRGSB& L_device_rr_gsb, + const ModuleManager& module_manager, + const RRGSB& rr_gsb, + const t_rr_type& cb_type, + const bool& compact_routing_hierarchy) { + /* Validate file stream */ + check_file_handler(fp); + + vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + + std::string cb_instance_name = generate_connection_block_module_name(cb_type, gsb_coordinate); + + /* If we use the compact routing hierarchy, we need to find the module name !*/ + vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + if (true == compact_routing_hierarchy) { + DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + /* Note: use GSB coordinate when inquire for unique modules!!! */ + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); + cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); + } + + std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); + + ModuleId cb_module = module_manager.find_module(cb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Disable timing for Connection block " << cb_module_name << std::endl; + fp << "##################################################" << std::endl; + + /* Disable all the input port (routing tracks), which are not used by benchmark */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + t_rr_node* chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack); + /* Check if this node is used by benchmark */ + if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) { + continue; + } + + /* Disable both input of the routing track if it is not used! */ + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + port_coord.set_x(unique_mirror.get_cb_x(cb_type)); + port_coord.set_y(unique_mirror.get_cb_y(cb_type)); + } + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + IN_PORT); + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); + + fp << "set_disable_timing "; + fp << cb_instance_name << "/"; + fp << generate_sdc_port(module_manager.module_port(cb_module, module_port)); + fp << std::endl; + } + + /* Disable all the output port (routing tracks), which are not used by benchmark */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + t_rr_node* chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack); + /* Check if this node is used by benchmark */ + if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) { + continue; + } + + /* Disable both input of the routing track if it is not used! */ + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + port_coord.set_x(unique_mirror.get_cb_x(cb_type)); + port_coord.set_y(unique_mirror.get_cb_y(cb_type)); + } + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + OUT_PORT); + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); + + fp << "set_disable_timing "; + fp << cb_instance_name << "/"; + fp << generate_sdc_port(module_manager.module_port(cb_module, module_port)); + fp << std::endl; + } + + /* Disable all the output port (grid input pins), which are not used by benchmark */ + std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); + + for (size_t side = 0; side < cb_sides.size(); ++side) { + enum e_side cb_ipin_side = cb_sides[side]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) { + continue; + } + if (0 == ipin_node->fan_in) { + continue; + } + vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); + std::string port_name = generate_grid_side_port_name(grids, + port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), + ipin_node->ptc_num); + + /* Find the port in unique mirror! */ + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + t_rr_node* unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); + port_coord.set_x(unique_mirror_ipin_node->xlow); + port_coord.set_y(unique_mirror_ipin_node->ylow); + port_name = generate_grid_side_port_name(grids, + port_coord, + unique_mirror.get_ipin_node_grid_side(cb_ipin_side, inode), + unique_mirror_ipin_node->ptc_num); + } + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); + + fp << "set_disable_timing "; + fp << cb_instance_name << "/"; + fp << generate_sdc_port(module_manager.module_port(cb_module, module_port)); + fp << std::endl; + } + } + + /* TODO: Disable all the unused inputs of routing multiplexers, which are not used by benchmark */ +} + + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and disable unused ports for each of them + *******************************************************************/ +static +void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, + const std::vector>& grids, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const t_rr_type& cb_type, + const bool& compact_routing_hierarchy) { + /* Build unique X-direction connection block modules */ + DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + if (false == rr_gsb.is_cb_exist(cb_type)) { + continue; + } + + print_analysis_sdc_disable_cb_unused_resources(fp, grids, L_device_rr_gsb, + module_manager, + rr_gsb, + cb_type, + compact_routing_hierarchy); + } + } +} + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and disable unused ports for each of them + *******************************************************************/ +void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, + const std::vector>& grids, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy) { + + print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager, + L_device_rr_gsb, + CHANX, compact_routing_hierarchy); + + print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager, + L_device_rr_gsb, + CHANY, compact_routing_hierarchy); +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h new file mode 100644 index 000000000..21154b1d8 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h @@ -0,0 +1,15 @@ +#ifndef ANALYSIS_SDC_ROUTING_WRITER_H +#define ANALYSIS_SDC_ROUTING_WRITER_H + +#include +#include +#include "module_manager.h" +#include "rr_blocks.h" +#include "vpr_types.h" + +void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, + const std::vector>& grids, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy); +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index a85a2ae3d..351d3a74a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -20,6 +20,7 @@ #include "sdc_writer_utils.h" #include "sdc_memory_utils.h" +#include "analysis_sdc_routing_writer.h" #include "analysis_sdc_writer.h" /******************************************************************** @@ -241,20 +242,12 @@ void print_analysis_sdc(const std::string& sdc_dir, format_dir_path(module_manager.module_name(top_module))); - /* TODO: Disable timing for un-used resources */ + /* TODO: Disable timing for unused routing resources in connection blocks */ + print_analysis_sdc_disable_unused_cbs(fp, L_grids, module_manager, + L_device_rr_gsb, + compact_routing_hierarchy); - /* TODO: Apply to Connection blocks */ - /* - if (TRUE == compact_routing_hierarchy) { - verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny, LL_device_rr_gsb); - verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny, LL_device_rr_gsb); - } else { - verilog_generate_sdc_disable_unused_cbs(fp, LL_nx, LL_ny); - verilog_generate_sdc_disable_unused_cbs_muxs(fp, LL_nx, LL_ny); - } - */ - - /* TODO: Apply to Switch blocks */ + /* TODO: Disable timing for unused routing resources in switch blocks */ /* if (TRUE == compact_routing_hierarchy) { verilog_generate_sdc_disable_unused_sbs(fp); @@ -265,7 +258,7 @@ void print_analysis_sdc(const std::string& sdc_dir, } */ - /* TODO: Apply to Grids */ + /* TODO: Disable timing for unused routing resources in grids (programmable blocks) */ /* verilog_generate_sdc_disable_unused_grids(fp, LL_nx, LL_ny, LL_grid, LL_block); verilog_generate_sdc_disable_unused_grids_muxs(fp, LL_nx, LL_ny, LL_grid, LL_block); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index bf9f17858..a8c76c6d6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -25,7 +25,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const std::vector& global_ports, const bool& compact_routing_hierarchy) { vpr_printf(TIO_MESSAGE_INFO, - "SDC generator starts..."); + "SDC generator starts...\n"); /* Start time count */ clock_t t_start = clock(); From 8e8e59b0ca367c803547677954fe33ca798d9145 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Nov 2019 19:42:30 -0700 Subject: [PATCH 459/482] give specific name to mux so that we can bind it to SDC generator --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp | 71 +++++++++++++++++++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h | 14 ++++ .../fpga_x2p/base/fpga_x2p_reserved_words.h | 4 ++ .../module_builder/build_grid_modules.cpp | 5 ++ .../module_builder/build_routing_modules.cpp | 12 ++++ 5 files changed, 106 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index a90a301e2..72bc59994 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -758,6 +758,25 @@ std::string generate_grid_block_module_name(const std::string& prefix, return module_name; } +/********************************************************************* + * Generate the instance name for a programmable routing multiplexer module + * in a Switch Block + * To keep a unique name in each module and also consider unique routing modules, + * please do NOT include any coordinates in the naming!!! + * Consider only relative coordinate, such as side! + ********************************************************************/ +std::string generate_sb_mux_instance_name(const std::string& prefix, + const e_side& sb_side, + const size_t& track_id, + const std::string& postfix) { + std::string instance_name(prefix); + instance_name += Side(sb_side).to_string(); + instance_name += std::string("_track_") + std::to_string(track_id); + instance_name += postfix; + + return instance_name; +} + /********************************************************************* * Generate the instance name for a configurable memory module in a Switch Block * To keep a unique name in each module and also consider unique routing modules, @@ -776,6 +795,26 @@ std::string generate_sb_memory_instance_name(const std::string& prefix, return instance_name; } +/********************************************************************* + * Generate the instance name for a programmable routing multiplexer module + * in a Connection Block + * To keep a unique name in each module and also consider unique routing modules, + * please do NOT include any coordinates in the naming!!! + * Consider only relative coordinate, such as side! + ********************************************************************/ +std::string generate_cb_mux_instance_name(const std::string& prefix, + const e_side& cb_side, + const size_t& pin_id, + const std::string& postfix) { + std::string instance_name(prefix); + + instance_name += Side(cb_side).to_string(); + instance_name += std::string("_ipin_") + std::to_string(pin_id); + instance_name += postfix; + + return instance_name; +} + /********************************************************************* * Generate the instance name for a configurable memory module in a Connection Block * To keep a unique name in each module and also consider unique routing modules, @@ -795,6 +834,38 @@ std::string generate_cb_memory_instance_name(const std::string& prefix, return instance_name; } +/********************************************************************* + * Generate the instance name for a programmable routing multiplexer + * module in a physical block of a grid + * To guarentee a unique name for pb_graph pin, + * the instance name includes the index of parent node + * as well as the port name and pin index of this pin + * + * Exceptions: + * For OUTPUT ports, due to hierarchical module organization, + * their parent nodes will be uniquified + * So, we should not add any index here + ********************************************************************/ +std::string generate_pb_mux_instance_name(const std::string& prefix, + t_pb_graph_pin* pb_graph_pin, + const std::string& postfix) { + std::string instance_name(prefix); + instance_name += std::string(pb_graph_pin->parent_node->pb_type->name); + + if (IN_PORT == pb_graph_pin->port->type) { + instance_name += std::string("_"); + instance_name += std::to_string(pb_graph_pin->parent_node->placement_index); + } + + instance_name += std::string("_"); + instance_name += std::string(pb_graph_pin->port->name); + instance_name += std::string("_"); + instance_name += std::to_string(pb_graph_pin->pin_number); + instance_name += postfix; + + return instance_name; +} + /********************************************************************* * Generate the instance name for a configurable memory module in a * physical block of a grid diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index 56f3c627d..83e84af3b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -78,16 +78,30 @@ std::string generate_switch_block_module_name(const vtr::Point& coordina std::string generate_connection_block_module_name(const t_rr_type& cb_type, const vtr::Point& coordinate); +std::string generate_sb_mux_instance_name(const std::string& prefix, + const e_side& sb_side, + const size_t& track_id, + const std::string& postfix); + std::string generate_sb_memory_instance_name(const std::string& prefix, const e_side& sb_side, const size_t& track_id, const std::string& postfix); +std::string generate_cb_mux_instance_name(const std::string& prefix, + const e_side& cb_side, + const size_t& pin_id, + const std::string& postfix); + std::string generate_cb_memory_instance_name(const std::string& prefix, const e_side& cb_side, const size_t& pin_id, const std::string& postfix); +std::string generate_pb_mux_instance_name(const std::string& prefix, + t_pb_graph_pin* pb_graph_pin, + const std::string& postfix); + std::string generate_pb_memory_instance_name(const std::string& prefix, t_pb_graph_pin* pb_graph_pin, const std::string& postfix); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h index face6ad8f..c334feef1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h @@ -16,6 +16,10 @@ constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; constexpr char* MEMORY_MODULE_POSTFIX = "_mem"; +/* Multiplexer naming constant strings */ +constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_"; +constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; +constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; /* Bitstream file strings */ constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml"; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index b298c22c1..e23ec60f9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -559,6 +559,11 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Instanciate the MUX */ size_t mux_instance = module_manager.num_instance(pb_module, mux_module); module_manager.add_child_module(pb_module, mux_module); + /* Give an instance name: this name should be consistent with the block name given in SDC generator, + * If you want to bind the SDC generation to modules + */ + std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); + module_manager.set_child_instance_name(pb_module, mux_module, mux_instance, mux_instance_name); /* Instanciate a memory module for the MUX */ std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index d2b5b4464..b43baa0f4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -128,6 +128,12 @@ void build_switch_block_mux_module(ModuleManager& module_manager, /* Instanciate the MUX Module */ module_manager.add_child_module(sb_module, mux_module); + /* Give an instance name: this name should be consistent with the block name given in SDC manager, + * If you want to bind the SDC generation to modules + */ + std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, chan_side, chan_node_id, std::string("")); + module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name); + /* Generate input ports that are wired to the input bus of the routing multiplexer */ std::vector sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_gsb, grids, drive_rr_nodes); @@ -515,6 +521,12 @@ void build_connection_block_mux_module(ModuleManager& module_manager, size_t mux_instance_id = module_manager.num_instance(cb_module, mux_module); module_manager.add_child_module(cb_module, mux_module); + /* Give an instance name: this name should be consistent with the block name given in SDC manager, + * If you want to bind the SDC generation to modules + */ + std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string("")); + module_manager.set_child_instance_name(cb_module, mux_module, mux_instance_id, mux_instance_name); + /* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */ std::vector cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_gsb, cb_type, drive_rr_nodes); From a849522be9d4111bf32fe5785f729e548ecfb578 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Nov 2019 20:15:16 -0700 Subject: [PATCH 460/482] refactored CB SDC analysis generation --- .../analysis_sdc_routing_writer.cpp | 115 ++++++++++++++++-- .../analysis_sdc_routing_writer.h | 3 + .../backend_assistant/analysis_sdc_writer.cpp | 6 +- .../backend_assistant/analysis_sdc_writer.h | 2 + .../fpga_x2p/backend_assistant/sdc_api.cpp | 8 +- .../SRC/fpga_x2p/backend_assistant/sdc_api.h | 3 +- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- 7 files changed, 126 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp index 93cf918ce..d092dc3cf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp @@ -6,9 +6,10 @@ #include "vtr_assert.h" #include "device_port.h" +#include "fpga_x2p_reserved_words.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" - +#include "fpga_x2p_types.h" #include "sdc_writer_utils.h" #include "analysis_sdc_routing_writer.h" @@ -43,8 +44,11 @@ bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { static void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, const std::vector>& grids, - const DeviceRRGSB& L_device_rr_gsb, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const CircuitLibrary& circuit_lib, const RRGSB& rr_gsb, const t_rr_type& cb_type, const bool& compact_routing_hierarchy) { @@ -182,6 +186,96 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, } /* TODO: Disable all the unused inputs of routing multiplexers, which are not used by benchmark */ + for (size_t side = 0; side < cb_sides.size(); ++side) { + enum e_side cb_ipin_side = cb_sides[side]; + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { + t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) { + continue; + } + if (0 == ipin_node->fan_in) { + continue; + } + vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); + std::string port_name = generate_grid_side_port_name(grids, + port_coord, + rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), + ipin_node->ptc_num); + + /* Find the port in unique mirror! */ + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + t_rr_node* unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); + port_coord.set_x(unique_mirror_ipin_node->xlow); + port_coord.set_y(unique_mirror_ipin_node->ylow); + port_name = generate_grid_side_port_name(grids, + port_coord, + unique_mirror.get_ipin_node_grid_side(cb_ipin_side, inode), + unique_mirror_ipin_node->ptc_num); + } + + /* These codes are exactly same in build_routing_modules.cpp + * If you wish to change the naming rules, please change build_routing_modules.cpp as well + * so that consistency remains + */ + /* Build a vector of driver rr_nodes */ + std::vector drive_rr_nodes; + for (int jnode = 0; jnode < ipin_node->num_drive_rr_nodes; jnode++) { + drive_rr_nodes.push_back(ipin_node->drive_rr_nodes[jnode]); + } + + int switch_index = ipin_node->drive_switches[DEFAULT_SWITCH_ID]; + + /* Get the circuit model id of the routing multiplexer */ + CircuitModelId mux_model = rr_switches[switch_index].circuit_model; + + /* Find the input size of the implementation of a routing multiplexer */ + size_t datapath_mux_size = drive_rr_nodes.size(); + + /* Find the module name of the multiplexer and try to find it in the module manager */ + std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); + ModuleId mux_module = module_manager.find_module(mux_module_name); + VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + + /* Find the MUX instance that drives the IPIN! */ + std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string("")); + + /* Make sure this instance name exists! */ + size_t instance_id = module_manager.instance_id(cb_module, mux_module, mux_instance_name); + VTR_ASSERT(instance_id < module_manager.num_instance(cb_module, mux_module)); + + /* Find the MUX input port from model to module */ + std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); + VTR_ASSERT(1 == mux_model_input_ports.size()); + /* Find the module port id of the input port */ + ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); + VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); + BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); + + /* Find out which routing path is used in this MUX */ + int path_id = DEFAULT_PATH_ID; + for (size_t jnode = 0; jnode < drive_rr_nodes.size(); ++jnode) { + if (drive_rr_nodes[jnode] == &(L_rr_node[ipin_node->prev_node])) { + path_id = (int)jnode; + break; + } + } + + for (const size_t& pin : mux_input_port.pins()) { + if ((size_t)path_id == pin) { + continue; /* For used pin, skip disable timing */ + } + /* Get the input id that is used! Disable the unused inputs! */ + fp << "set_disable_timing "; + fp << cb_instance_name << "/"; + fp << mux_instance_name << "/"; + fp << generate_sdc_port(BasicPort(mux_input_port.get_name(), pin, pin)); + fp << std::endl; + } + } + } } @@ -192,7 +286,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, static void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const DeviceRRGSB& L_device_rr_gsb, const t_rr_type& cb_type, const bool& compact_routing_hierarchy) { @@ -210,8 +307,9 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, continue; } - print_analysis_sdc_disable_cb_unused_resources(fp, grids, L_device_rr_gsb, + print_analysis_sdc_disable_cb_unused_resources(fp, grids, rr_switches, L_rr_node, module_manager, + L_device_rr_gsb, circuit_lib, rr_gsb, cb_type, compact_routing_hierarchy); @@ -225,16 +323,19 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, *******************************************************************/ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const DeviceRRGSB& L_device_rr_gsb, const bool& compact_routing_hierarchy) { - print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager, - L_device_rr_gsb, + print_analysis_sdc_disable_unused_cb_ports(fp, grids, rr_switches, L_rr_node, module_manager, + circuit_lib, L_device_rr_gsb, CHANX, compact_routing_hierarchy); - print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager, - L_device_rr_gsb, + print_analysis_sdc_disable_unused_cb_ports(fp, grids, rr_switches, L_rr_node, module_manager, + circuit_lib, L_device_rr_gsb, CHANY, compact_routing_hierarchy); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h index 21154b1d8..d05fcf226 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h @@ -9,7 +9,10 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const std::vector>& grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const DeviceRRGSB& L_device_rr_gsb, const bool& compact_routing_hierarchy); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index 351d3a74a..1ee475e16 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -195,6 +195,8 @@ void print_analysis_sdc(const std::string& sdc_dir, const std::vector& L_logical_blocks, const vtr::Point& device_size, const std::vector>& L_grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const std::vector& L_blocks, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, @@ -243,7 +245,9 @@ void print_analysis_sdc(const std::string& sdc_dir, /* TODO: Disable timing for unused routing resources in connection blocks */ - print_analysis_sdc_disable_unused_cbs(fp, L_grids, module_manager, + print_analysis_sdc_disable_unused_cbs(fp, L_grids, rr_switches, L_rr_node, + module_manager, + circuit_lib, L_device_rr_gsb, compact_routing_hierarchy); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h index 252c76c71..aeb55247d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h @@ -13,6 +13,8 @@ void print_analysis_sdc(const std::string& sdc_dir, const std::vector& L_logical_blocks, const vtr::Point& device_size, const std::vector>& L_grids, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const std::vector& L_blocks, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index a8c76c6d6..e3666051a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -13,7 +13,8 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, const std::vector>& grids, - const std::vector& switches, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb, const std::vector& L_logical_blocks, const vtr::Point& device_size, @@ -32,7 +33,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options, if (true == sdc_options.generate_sdc_pnr()) { print_pnr_sdc(sdc_options, critical_path_delay, - grids, switches, L_device_rr_gsb, + grids, rr_switches, L_device_rr_gsb, module_manager, mux_lib, circuit_lib, global_ports, compact_routing_hierarchy); @@ -42,7 +43,8 @@ void fpga_sdc_generator(const SdcOption& sdc_options, print_analysis_sdc(sdc_options.sdc_dir(), critical_path_delay, L_device_rr_gsb, - L_logical_blocks, device_size, L_grids, L_blocks, + L_logical_blocks, device_size, L_grids, rr_switches, L_rr_node, + L_blocks, module_manager, circuit_lib, global_ports, compact_routing_hierarchy); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h index 02874e3a3..51f0beb64 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h @@ -10,7 +10,8 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, const std::vector>& grids, - const std::vector& switches, + const std::vector& rr_switches, + t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb, const std::vector& L_logical_blocks, const vtr::Point& device_size, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index edff64348..0a2ba84cf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -159,7 +159,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* TODO: the critical path delay unit should be explicit! */ fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, - grids, rr_switches, device_rr_gsb, + grids, rr_switches, rr_node, device_rr_gsb, L_logical_blocks, device_size, grids, L_blocks, module_manager, mux_lib, Arch.spice->circuit_lib, global_ports, From 876733f052ddaeb1c056e458be3b54832e48b246 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Nov 2019 21:15:34 -0700 Subject: [PATCH 461/482] now we use module manager to generate analysis SDC, being independent from VPR structures --- .../analysis_sdc_routing_writer.cpp | 177 +++++++++--------- .../analysis_sdc_routing_writer.h | 3 - .../backend_assistant/analysis_sdc_writer.cpp | 5 +- .../backend_assistant/analysis_sdc_writer.h | 2 - .../fpga_x2p/backend_assistant/sdc_api.cpp | 3 +- .../SRC/fpga_x2p/backend_assistant/sdc_api.h | 1 - vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c | 2 +- 7 files changed, 88 insertions(+), 105 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp index d092dc3cf..48a798aab 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp @@ -3,6 +3,8 @@ * that constrain routing modules of a FPGA fabric (P&Red netlist) * using a benchmark *******************************************************************/ +#include + #include "vtr_assert.h" #include "device_port.h" @@ -44,11 +46,8 @@ bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { static void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, const std::vector>& grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, const ModuleManager& module_manager, const DeviceRRGSB& L_device_rr_gsb, - const CircuitLibrary& circuit_lib, const RRGSB& rr_gsb, const t_rr_type& cb_type, const bool& compact_routing_hierarchy) { @@ -141,6 +140,9 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, fp << std::endl; } + /* Build a map between mux_instance name and net_num */ + std::map mux_instance_to_net_map; + /* Disable all the output port (grid input pins), which are not used by benchmark */ std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); @@ -154,6 +156,11 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, if (0 == ipin_node->fan_in) { continue; } + + /* Find the MUX instance that drives the IPIN! */ + std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string("")); + mux_instance_to_net_map[mux_instance_name] = ipin_node->vpack_net_num; + vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); std::string port_name = generate_grid_side_port_name(grids, port_coord, @@ -185,100 +192,92 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, } } - /* TODO: Disable all the unused inputs of routing multiplexers, which are not used by benchmark */ - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) { - continue; - } - if (0 == ipin_node->fan_in) { - continue; - } - vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); - std::string port_name = generate_grid_side_port_name(grids, - port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), - ipin_node->ptc_num); + /* Disable all the unused inputs of routing multiplexers, which are not used by benchmark + * Here, we start from each input of the Connection Blocks, and traverse forward to the sink + * port of the module net whose source is the input + * We will find the instance name which is the parent of the sink port, and search the + * net id through the instance_name_to_net_map + * The the net id does not match the net id of this input, we will disable the sink port! + * + * cb_module + * +----------------------- + * | MUX instance A + * | +----------- + * input_port--->|--+---x-->| sink port (disable!) + * | | +---------- + * | | MUX instance B + * | | +---------- + * | +------>| sink port (do not disable!) + */ + for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { + t_rr_node* chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack); - /* Find the port in unique mirror! */ - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - t_rr_node* unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); - port_coord.set_x(unique_mirror_ipin_node->xlow); - port_coord.set_y(unique_mirror_ipin_node->ylow); - port_name = generate_grid_side_port_name(grids, - port_coord, - unique_mirror.get_ipin_node_grid_side(cb_ipin_side, inode), - unique_mirror_ipin_node->ptc_num); - } + /* Disable both input of the routing track if it is not used! */ + vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); + port_coord.set_x(unique_mirror.get_cb_x(cb_type)); + port_coord.set_y(unique_mirror.get_cb_y(cb_type)); + } + std::string port_name = generate_routing_track_port_name(cb_type, + port_coord, itrack, + OUT_PORT); - /* These codes are exactly same in build_routing_modules.cpp - * If you wish to change the naming rules, please change build_routing_modules.cpp as well - * so that consistency remains - */ - /* Build a vector of driver rr_nodes */ - std::vector drive_rr_nodes; - for (int jnode = 0; jnode < ipin_node->num_drive_rr_nodes; jnode++) { - drive_rr_nodes.push_back(ipin_node->drive_rr_nodes[jnode]); - } - - int switch_index = ipin_node->drive_switches[DEFAULT_SWITCH_ID]; - - /* Get the circuit model id of the routing multiplexer */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); - /* Find the MUX instance that drives the IPIN! */ - std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string("")); + /* Find the module net which sources from this port! */ + for (const size_t& pin : module_manager.module_port(cb_module, module_port).pins()) { + ModuleNetId module_net = module_manager.module_instance_port_net(cb_module, cb_module, 0, module_port, pin); + VTR_ASSERT(true == module_manager.valid_module_net_id(cb_module, module_net)); - /* Make sure this instance name exists! */ - size_t instance_id = module_manager.instance_id(cb_module, mux_module, mux_instance_name); - VTR_ASSERT(instance_id < module_manager.num_instance(cb_module, mux_module)); + /* Touch each sink of the net! */ + for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(cb_module, module_net)) { + ModuleId sink_module = module_manager.net_sink_modules(cb_module, module_net)[sink_id]; + size_t sink_instance = module_manager.net_sink_instances(cb_module, module_net)[sink_id]; - /* Find the MUX input port from model to module */ - std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == mux_model_input_ports.size()); - /* Find the module port id of the input port */ - ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); - BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); - - /* Find out which routing path is used in this MUX */ - int path_id = DEFAULT_PATH_ID; - for (size_t jnode = 0; jnode < drive_rr_nodes.size(); ++jnode) { - if (drive_rr_nodes[jnode] == &(L_rr_node[ipin_node->prev_node])) { - path_id = (int)jnode; - break; + /* Skip when sink module is the cb module, + * the output ports of cb modules have been disabled/enabled already! + */ + if (sink_module == cb_module) { + continue; } - } - for (const size_t& pin : mux_input_port.pins()) { - if ((size_t)path_id == pin) { - continue; /* For used pin, skip disable timing */ + std::string sink_instance_name = module_manager.instance_name(cb_module, sink_module, sink_instance); + bool disable_timing = false; + /* Check if this node is used by benchmark */ + if (true == is_rr_node_to_be_disable_for_analysis(chan_node)) { + /* Disable all the sinks! */ + disable_timing = true; + } else { + /* See if the net id matches. If does not match, we should disable! */ + if (chan_node->vpack_net_num != mux_instance_to_net_map[sink_instance_name]) { + disable_timing = true; + } } + + /* Time to write SDC command to disable timing or not */ + if (false == disable_timing) { + continue; + } + + BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(cb_module, module_net)[sink_id]); + sink_port.set_width(module_manager.net_sink_pins(cb_module, module_net)[sink_id], + module_manager.net_sink_pins(cb_module, module_net)[sink_id]); /* Get the input id that is used! Disable the unused inputs! */ fp << "set_disable_timing "; fp << cb_instance_name << "/"; - fp << mux_instance_name << "/"; - fp << generate_sdc_port(BasicPort(mux_input_port.get_name(), pin, pin)); + fp << sink_instance_name << "/"; + fp << generate_sdc_port(sink_port); fp << std::endl; } } } } - /******************************************************************** * Iterate over all the connection blocks in a device * and disable unused ports for each of them @@ -286,10 +285,7 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, static void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, const std::vector>& grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const DeviceRRGSB& L_device_rr_gsb, const t_rr_type& cb_type, const bool& compact_routing_hierarchy) { @@ -307,9 +303,9 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, continue; } - print_analysis_sdc_disable_cb_unused_resources(fp, grids, rr_switches, L_rr_node, + print_analysis_sdc_disable_cb_unused_resources(fp, grids, module_manager, - L_device_rr_gsb, circuit_lib, + L_device_rr_gsb, rr_gsb, cb_type, compact_routing_hierarchy); @@ -323,19 +319,16 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, *******************************************************************/ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const std::vector>& grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const DeviceRRGSB& L_device_rr_gsb, const bool& compact_routing_hierarchy) { - print_analysis_sdc_disable_unused_cb_ports(fp, grids, rr_switches, L_rr_node, module_manager, - circuit_lib, L_device_rr_gsb, + print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager, + L_device_rr_gsb, CHANX, compact_routing_hierarchy); - print_analysis_sdc_disable_unused_cb_ports(fp, grids, rr_switches, L_rr_node, module_manager, - circuit_lib, L_device_rr_gsb, + print_analysis_sdc_disable_unused_cb_ports(fp, grids, module_manager, + L_device_rr_gsb, CHANY, compact_routing_hierarchy); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h index d05fcf226..21154b1d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h @@ -9,10 +9,7 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const std::vector>& grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const DeviceRRGSB& L_device_rr_gsb, const bool& compact_routing_hierarchy); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index 1ee475e16..5d2a15b7a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -195,8 +195,6 @@ void print_analysis_sdc(const std::string& sdc_dir, const std::vector& L_logical_blocks, const vtr::Point& device_size, const std::vector>& L_grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, const std::vector& L_blocks, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, @@ -245,9 +243,8 @@ void print_analysis_sdc(const std::string& sdc_dir, /* TODO: Disable timing for unused routing resources in connection blocks */ - print_analysis_sdc_disable_unused_cbs(fp, L_grids, rr_switches, L_rr_node, + print_analysis_sdc_disable_unused_cbs(fp, L_grids, module_manager, - circuit_lib, L_device_rr_gsb, compact_routing_hierarchy); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h index aeb55247d..252c76c71 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h @@ -13,8 +13,6 @@ void print_analysis_sdc(const std::string& sdc_dir, const std::vector& L_logical_blocks, const vtr::Point& device_size, const std::vector>& L_grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, const std::vector& L_blocks, const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp index e3666051a..83683db1f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp @@ -14,7 +14,6 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, const std::vector>& grids, const std::vector& rr_switches, - t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb, const std::vector& L_logical_blocks, const vtr::Point& device_size, @@ -43,7 +42,7 @@ void fpga_sdc_generator(const SdcOption& sdc_options, print_analysis_sdc(sdc_options.sdc_dir(), critical_path_delay, L_device_rr_gsb, - L_logical_blocks, device_size, L_grids, rr_switches, L_rr_node, + L_logical_blocks, device_size, L_grids, L_blocks, module_manager, circuit_lib, global_ports, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h index 51f0beb64..402d65bed 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h @@ -11,7 +11,6 @@ void fpga_sdc_generator(const SdcOption& sdc_options, const float& critical_path_delay, const std::vector>& grids, const std::vector& rr_switches, - t_rr_node* L_rr_node, const DeviceRRGSB& L_device_rr_gsb, const std::vector& L_logical_blocks, const vtr::Point& device_size, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c index 0a2ba84cf..edff64348 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c @@ -159,7 +159,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, /* TODO: the critical path delay unit should be explicit! */ fpga_sdc_generator(sdc_options, Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, - grids, rr_switches, rr_node, device_rr_gsb, + grids, rr_switches, device_rr_gsb, L_logical_blocks, device_size, grids, L_blocks, module_manager, mux_lib, Arch.spice->circuit_lib, global_ports, From 5f219b428cf3d623a79d9e27ea39419f4d1fa6d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 11 Nov 2019 19:24:39 -0700 Subject: [PATCH 462/482] refactored analysis SDC generation for switch blocks --- .../analysis_sdc_routing_writer.cpp | 411 +++++++++++++++--- .../analysis_sdc_routing_writer.h | 7 + .../backend_assistant/analysis_sdc_writer.cpp | 17 +- 3 files changed, 374 insertions(+), 61 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp index 48a798aab..312696456 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp @@ -37,6 +37,84 @@ bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { return true; } +/******************************************************************** + * Disable all the unused inputs of routing multiplexers, which are not used by benchmark + * Here, we start from each input of a routing module, and traverse forward to the sink + * port of the module net whose source is the input + * We will find the instance name which is the parent of the sink port, and search the + * net id through the instance_name_to_net_map + * The the net id does not match the net id of this input, we will disable the sink port! + * + * parent_module + * +----------------------- + * | MUX instance A + * | +----------- + * input_port--->|--+---x-->| sink port (disable! net_id = Y) + * (net_id = X) | | +---------- + * | | MUX instance B + * | | +---------- + * | +------>| sink port (do not disable! net_id = X) + * + *******************************************************************/ +static +void disable_analysis_module_input_port_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModulePortId& module_input_port, + t_rr_node* input_rr_node, + const std::map mux_instance_to_net_map) { + /* Validate file stream */ + check_file_handler(fp); + + /* Find the module net which sources from this port! */ + for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) { + ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, pin); + VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net)); + + /* Touch each sink of the net! */ + for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) { + ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; + size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; + + /* Skip when sink module is the parent module, + * the output ports of parent modules have been disabled/enabled already! + */ + if (sink_module == parent_module) { + continue; + } + + std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance); + bool disable_timing = false; + /* Check if this node is used by benchmark */ + if (true == is_rr_node_to_be_disable_for_analysis(input_rr_node)) { + /* Disable all the sinks! */ + disable_timing = true; + } else { + /* See if the net id matches. If does not match, we should disable! */ + if (input_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) { + disable_timing = true; + } + } + + /* Time to write SDC command to disable timing or not */ + if (false == disable_timing) { + continue; + } + + BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]); + sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id], + module_manager.net_sink_pins(parent_module, module_net)[sink_id]); + /* Get the input id that is used! Disable the unused inputs! */ + fp << "set_disable_timing "; + fp << parent_instance_name << "/"; + fp << sink_instance_name << "/"; + fp << generate_sdc_port(sink_port); + fp << std::endl; + } + } +} + /******************************************************************** * This function will disable * 1. all the unused port (unmapped by a benchmark) of a connection block @@ -150,6 +228,11 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, enum e_side cb_ipin_side = cb_sides[side]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); + + /* Find the MUX instance that drives the IPIN! */ + std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string("")); + mux_instance_to_net_map[mux_instance_name] = ipin_node->vpack_net_num; + if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) { continue; } @@ -157,10 +240,6 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, continue; } - /* Find the MUX instance that drives the IPIN! */ - std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string("")); - mux_instance_to_net_map[mux_instance_name] = ipin_node->vpack_net_num; - vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); std::string port_name = generate_grid_side_port_name(grids, port_coord, @@ -229,52 +308,12 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); - /* Find the module net which sources from this port! */ - for (const size_t& pin : module_manager.module_port(cb_module, module_port).pins()) { - ModuleNetId module_net = module_manager.module_instance_port_net(cb_module, cb_module, 0, module_port, pin); - VTR_ASSERT(true == module_manager.valid_module_net_id(cb_module, module_net)); - - /* Touch each sink of the net! */ - for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(cb_module, module_net)) { - ModuleId sink_module = module_manager.net_sink_modules(cb_module, module_net)[sink_id]; - size_t sink_instance = module_manager.net_sink_instances(cb_module, module_net)[sink_id]; - - /* Skip when sink module is the cb module, - * the output ports of cb modules have been disabled/enabled already! - */ - if (sink_module == cb_module) { - continue; - } - - std::string sink_instance_name = module_manager.instance_name(cb_module, sink_module, sink_instance); - bool disable_timing = false; - /* Check if this node is used by benchmark */ - if (true == is_rr_node_to_be_disable_for_analysis(chan_node)) { - /* Disable all the sinks! */ - disable_timing = true; - } else { - /* See if the net id matches. If does not match, we should disable! */ - if (chan_node->vpack_net_num != mux_instance_to_net_map[sink_instance_name]) { - disable_timing = true; - } - } - - /* Time to write SDC command to disable timing or not */ - if (false == disable_timing) { - continue; - } - - BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(cb_module, module_net)[sink_id]); - sink_port.set_width(module_manager.net_sink_pins(cb_module, module_net)[sink_id], - module_manager.net_sink_pins(cb_module, module_net)[sink_id]); - /* Get the input id that is used! Disable the unused inputs! */ - fp << "set_disable_timing "; - fp << cb_instance_name << "/"; - fp << sink_instance_name << "/"; - fp << generate_sdc_port(sink_port); - fp << std::endl; - } - } + disable_analysis_module_input_port_net_sinks(fp, + module_manager, cb_module, + cb_instance_name, + module_port, + chan_node, + mux_instance_to_net_map); } } @@ -332,3 +371,275 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, CHANY, compact_routing_hierarchy); } +/******************************************************************** + * This function will disable + * 1. all the unused port (unmapped by a benchmark) of a switch block + * 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers + * in a switch block + *******************************************************************/ +static +void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, + const std::vector>& grids, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const RRGSB& rr_gsb, + const bool& compact_routing_hierarchy) { + /* Validate file stream */ + check_file_handler(fp); + + vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + + std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); + + /* If we use the compact routing hierarchy, we need to find the module name !*/ + vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); + if (true == compact_routing_hierarchy) { + DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + /* Note: use GSB coordinate when inquire for unique modules!!! */ + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + sb_coordinate.set_x(unique_mirror.get_sb_x()); + sb_coordinate.set_y(unique_mirror.get_sb_y()); + } + + std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); + + ModuleId sb_module = module_manager.find_module(sb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); + + /* Print comments */ + fp << "##################################################" << std::endl; + fp << "# Disable timing for Switch block " << sb_module_name << std::endl; + fp << "##################################################" << std::endl; + + /* Build a map between mux_instance name and net_num */ + std::map mux_instance_to_net_map; + + /* Disable all the input/output port (routing tracks), which are not used by benchmark */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + DeviceCoordinator port_coordinate = rr_gsb.get_side_block_coordinator(side_manager.get_side()); + + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); + + vtr::Point port_coord(port_coordinate.get_x(), port_coordinate.get_y()); + std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side()); + port_coord.set_x(unique_port_coordinate.get_x()); + port_coord.set_y(unique_port_coordinate.get_y()); + port_name = generate_routing_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); + } + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); + + /* Cache the net name for routing tracks which are outputs of the switch block */ + if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + /* Generate the name of mux instance related to this output node */ + std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, side_manager.get_side(), itrack, std::string("")); + mux_instance_to_net_map[mux_instance_name] = chan_node->vpack_net_num; + } + + /* Check if this node is used by benchmark */ + if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) { + continue; + } + + fp << "set_disable_timing "; + fp << sb_instance_name << "/"; + fp << generate_sdc_port(module_manager.module_port(sb_module, module_port)); + fp << std::endl; + } + } + + /* Disable all the input port (grid output pins), which are not used by benchmark */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + t_rr_node* opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode); + vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + + std::string port_name = generate_grid_side_port_name(grids, port_coord, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + opin_node->ptc_num); + + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow); + port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow); + + port_name = generate_grid_side_port_name(grids, port_coord, + unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); + } + + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); + + /* Check if this node is used by benchmark */ + if (false == is_rr_node_to_be_disable_for_analysis(opin_node)) { + continue; + } + + fp << "set_disable_timing "; + fp << sb_instance_name << "/"; + fp << generate_sdc_port(module_manager.module_port(sb_module, module_port)); + fp << std::endl; + } + } + + /* Disable all the unused inputs of routing multiplexers, which are not used by benchmark + * Here, we start from each input of the Switch Blocks, and traverse forward to the sink + * port of the module net whose source is the input + * We will find the instance name which is the parent of the sink port, and search the + * net id through the instance_name_to_net_map + * The the net id does not match the net id of this input, we will disable the sink port! + * + * sb_module + * +----------------------- + * | MUX instance A + * | +----------- + * input_port--->|--+---x-->| sink port (disable! net_id = Y) + * (net_id = X) | | +---------- + * | | MUX instance B + * | | +---------- + * | +------>| sink port (do not disable! net_id = X) + * + * Because the input ports of a SB module come from + * 1. Grid output pins + * 2. routing tracks + * We will walk through these ports and do conditionally disable_timing + */ + + /* Iterate over input ports coming from grid output pins */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { + t_rr_node* opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode); + vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); + + std::string port_name = generate_grid_side_port_name(grids, port_coord, + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + opin_node->ptc_num); + + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow); + port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow); + + port_name = generate_grid_side_port_name(grids, port_coord, + unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); + } + + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); + + disable_analysis_module_input_port_net_sinks(fp, module_manager, + sb_module, + sb_instance_name, + module_port, + opin_node, + mux_instance_to_net_map); + } + } + + /* Iterate over input ports coming from routing tracks */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + Side side_manager(side); + DeviceCoordinator port_coordinate = rr_gsb.get_side_block_coordinator(side_manager.get_side()); + + for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { + /* Skip output ports, they have already been disabled or not */ + if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + + t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); + + vtr::Point port_coord(port_coordinate.get_x(), port_coordinate.get_y()); + std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + + if (true == compact_routing_hierarchy) { + /* Note: use GSB coordinate when inquire for unique modules!!! */ + DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); + const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); + DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side()); + port_coord.set_x(unique_port_coordinate.get_x()); + port_coord.set_y(unique_port_coordinate.get_y()); + + port_name = generate_routing_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, + port_coord, itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); + } + + + /* Ensure we have this port in the module! */ + ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); + + disable_analysis_module_input_port_net_sinks(fp, module_manager, + sb_module, + sb_instance_name, + module_port, + chan_node, + mux_instance_to_net_map); + } + } +} + + +/******************************************************************** + * Iterate over all the connection blocks in a device + * and disable unused ports for each of them + *******************************************************************/ +void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, + const std::vector>& grids, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy) { + + /* Build unique X-direction connection block modules */ + DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); + + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + /* Check if the connection block exists in the device! + * Some of them do NOT exist due to heterogeneous blocks (height > 1) + * We will skip those modules + */ + const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); + + print_analysis_sdc_disable_sb_unused_resources(fp, grids, + module_manager, + L_device_rr_gsb, + rr_gsb, + compact_routing_hierarchy); + } + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h index 21154b1d8..4b8fcc033 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h @@ -12,4 +12,11 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const ModuleManager& module_manager, const DeviceRRGSB& L_device_rr_gsb, const bool& compact_routing_hierarchy); + +void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, + const std::vector>& grids, + const ModuleManager& module_manager, + const DeviceRRGSB& L_device_rr_gsb, + const bool& compact_routing_hierarchy); + #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index 5d2a15b7a..41200c354 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -242,22 +242,17 @@ void print_analysis_sdc(const std::string& sdc_dir, format_dir_path(module_manager.module_name(top_module))); - /* TODO: Disable timing for unused routing resources in connection blocks */ + /* Disable timing for unused routing resources in connection blocks */ print_analysis_sdc_disable_unused_cbs(fp, L_grids, module_manager, L_device_rr_gsb, compact_routing_hierarchy); - /* TODO: Disable timing for unused routing resources in switch blocks */ - /* - if (TRUE == compact_routing_hierarchy) { - verilog_generate_sdc_disable_unused_sbs(fp); - verilog_generate_sdc_disable_unused_sbs_muxs(fp); - } else { - verilog_generate_sdc_disable_unused_sbs(fp, LL_nx, LL_ny); - verilog_generate_sdc_disable_unused_sbs_muxs(fp, LL_nx, LL_ny); - } - */ + /* Disable timing for unused routing resources in switch blocks */ + print_analysis_sdc_disable_unused_sbs(fp, L_grids, + module_manager, + L_device_rr_gsb, + compact_routing_hierarchy); /* TODO: Disable timing for unused routing resources in grids (programmable blocks) */ /* From 8a57a29d2d4aaf35c130d5120ce2dac36d614270 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 11 Nov 2019 22:38:11 -0700 Subject: [PATCH 463/482] refactoring analysis SDC generation for grids --- .../analysis_sdc_grid_writer.cpp | 200 ++++++++++++++++++ .../analysis_sdc_grid_writer.h | 16 ++ .../backend_assistant/analysis_sdc_writer.cpp | 6 +- 3 files changed, 218 insertions(+), 4 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp new file mode 100644 index 000000000..90a58c91c --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp @@ -0,0 +1,200 @@ +/******************************************************************** + * This file includes functions that are used to write SDC commands + * to disable unused ports of grids, such as Configurable Logic Block + * (CLBs), heterogeneous blocks, etc. + *******************************************************************/ +#include "vtr_assert.h" + +#include "fpga_x2p_reserved_words.h" +#include "fpga_x2p_naming.h" +#include "fpga_x2p_utils.h" + +#include "analysis_sdc_grid_writer.h" + +#include "globals.h" + +/******************************************************************** + * Disable the timing for a fully unused grid! + * This is very straightforward! + * Just walk through each pb_type and disable all the ports using wildcards + *******************************************************************/ +static +void print_analysis_sdc_disable_unused_pb_type(std::fstream& fp, + t_type_ptr grid_type, + const vtr::Point& grid_coordinate, + const ModuleManager& module_manager, + const size_t& grid_z, + const e_side& border_side) { + /* Check code: if this is an IO block, the border side MUST be valid */ + if (IO_TYPE == grid_type) { + VTR_ASSERT(NUM_SIDES != border_side); + } + + /* Find an unique name to the grid instane + * Note: this must be consistent with the instance name we used in build_top_module()!!! + */ + std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); + std::string grid_instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side, grid_coordinate); + + /* Find an unique name to the pb instance in this grid + * Note: this must be consistent with the instance name we used in build_grid_module()!!! + */ + std::string pb_module_name_prefix(GRID_MODULE_NAME_PREFIX); + std::string pb_instance_name = generate_grid_physical_block_instance_name(pb_module_name_prefix, grid_type->pb_graph_head->pb_type, border_side, grid_z); + + /* Print comments */ + fp << "#######################################" << std::endl; + fp << "# Disable Timing for unused grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; + fp << "#######################################" << std::endl; + + /* Disable everything under this level using wildcard */ + fp << "set_disable_timing "; + fp << grid_instance_name; + fp << "/"; + fp << pb_instance_name; + fp << "/*"; + fp << std::endl; + + /* TODO: Go recursively through the pb_graph hierarchy, and disable all the ports level by level */ + /* + rec_verilog_generate_sdc_disable_unused_pb_types(fp, prefix, + cur_grid_type->pb_type); + */ +} + +/******************************************************************** + * Disable the timing for a fully unused grid! + * This is very straightforward! + * Just walk through each pb_type and disable all the ports using wildcards + *******************************************************************/ +static +void print_analysis_sdc_disable_unused_grid(std::fstream& fp, + const vtr::Point& grid_coordinate, + const std::vector>& L_grids, + const std::vector& L_blocks, + const ModuleManager& module_manager, + const e_side& border_side) { + /* Validate file stream */ + check_file_handler(fp); + + t_type_ptr type = L_grids[grid_coordinate.x()][grid_coordinate.y()].type; + /* Bypass conditions for grids : + * 1. EMPTY type, which is by nature unused + * 2. Offset > 0, which has already been processed when offset = 0 + */ + if ( (NULL == type) + || (EMPTY_TYPE == type) + || (0 == L_grids[grid_coordinate.x()][grid_coordinate.y()].offset) ) { + return; + } + + /* Now we need to find the usage of this grid */ + std::vector grid_usage(type->capacity, false); + + /* Print comments */ + fp << "#######################################" << std::endl; + fp << "# Disable Timing for grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "]" << std::endl; + fp << "#######################################" << std::endl; + + /* For used grid, find the unused rr_node in the local rr_graph + * and then disable each port which is not used + * as well as the unused inputs of routing multiplexers! + */ + for (int iblk = 0; iblk < L_grids[grid_coordinate.x()][grid_coordinate.y()].usage; ++iblk) { + int blk_id = L_grids[grid_coordinate.x()][grid_coordinate.y()].blocks[iblk]; + VTR_ASSERT( (OPEN < L_blocks[blk_id].z) && (L_blocks[blk_id].z < type->capacity) ); + /* Mark the grid_usage */ + grid_usage[L_blocks[blk_id].z] = true; + /* TODO: + verilog_generate_sdc_disable_one_unused_block(fp, &(L_blocks[blk_id])); + */ + } + + /* For unused grid, disable all the pins in the physical_pb_type */ + for (int iblk = 0; iblk < type->capacity; ++iblk) { + /* Bypass used blocks */ + if (true == grid_usage[iblk]) { + continue; + } + print_analysis_sdc_disable_unused_pb_type(fp, type, grid_coordinate, module_manager, iblk, border_side); + } +} + +/******************************************************************** + * Top-level function writes SDC commands to disable unused ports + * of grids, such as Configurable Logic Block (CLBs), heterogeneous blocks, etc. + * + * This function will iterate over all the grids available in the FPGA fabric + * It will disable the timing analysis for + * 1. Grids, which are totally not used (no logic has been mapped to) + * 2. Unused part of grids, including the ports, inputs of routing multiplexers + * + * Note that it is a must to disable the unused inputs of routing multiplexers + * because it will cause unexpected paths in timing analysis + * For example: + * +---------------------+ + * inputA (net0) ------->| | + * | Routing multiplexer |----> output (net0) + * inputB (net1) ------->| | + * +---------------------+ + * + * During timing analysis, the path from inputA to output should be considered + * while the path from inputB to output should NOT be considered!!! + * + *******************************************************************/ +void print_analysis_sdc_disable_unused_grids(std::fstream& fp, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const ModuleManager& module_manager) { + /* TODO: disable inputs of multiplexers + verilog_generate_sdc_disable_unused_grids_muxs(fp, LL_nx, LL_ny, LL_grid, LL_block); + */ + + /* Process unused core grids */ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE != L_grids[ix][iy].type); + + print_analysis_sdc_disable_unused_grid(fp, vtr::Point(ix, iy), + L_grids, L_blocks, module_manager, NUM_SIDES); + } + } + + /* Instanciate I/O grids */ + /* Create the coordinate range for each side of FPGA fabric */ + std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; + std::map>> io_coordinates; + + /* TOP side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); + } + + /* RIGHT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); + } + + /* BOTTOM side*/ + for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { + io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); + } + + /* LEFT side */ + for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { + io_coordinates[LEFT].push_back(vtr::Point(0, iy)); + } + + /* Add instances of I/O grids to top_module */ + for (const e_side& io_side : io_sides) { + for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { + /* We should not meet any I/O grid */ + VTR_ASSERT(IO_TYPE == L_grids[io_coordinate.x()][io_coordinate.y()].type); + + print_analysis_sdc_disable_unused_grid(fp, io_coordinate, + L_grids, L_blocks, module_manager, io_side); + } + } +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h new file mode 100644 index 000000000..a198cc129 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h @@ -0,0 +1,16 @@ +#ifndef ANALYSIS_SDC_GRID_WRITER_H +#define ANALYSIS_SDC_GRID_WRITER_H + +#include +#include +#include "vtr_geometry.h" +#include "vpr_types.h" +#include "module_manager.h" + +void print_analysis_sdc_disable_unused_grids(std::fstream& fp, + const vtr::Point& device_size, + const std::vector>& L_grids, + const std::vector& L_blocks, + const ModuleManager& module_manager); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index 41200c354..8aed25fc0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -20,6 +20,7 @@ #include "sdc_writer_utils.h" #include "sdc_memory_utils.h" +#include "analysis_sdc_grid_writer.h" #include "analysis_sdc_routing_writer.h" #include "analysis_sdc_writer.h" @@ -255,10 +256,7 @@ void print_analysis_sdc(const std::string& sdc_dir, compact_routing_hierarchy); /* TODO: Disable timing for unused routing resources in grids (programmable blocks) */ - /* - verilog_generate_sdc_disable_unused_grids(fp, LL_nx, LL_ny, LL_grid, LL_block); - verilog_generate_sdc_disable_unused_grids_muxs(fp, LL_nx, LL_ny, LL_grid, LL_block); - */ + print_analysis_sdc_disable_unused_grids(fp, device_size, L_grids, L_blocks, module_manager); /* Close file handler */ fp.close(); From 6c58a4dd9226a2892f88af0b8dfb1fad708f4649 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 12 Nov 2019 10:01:17 -0700 Subject: [PATCH 464/482] refactored unused grid block SDC analysis generation --- .../analysis_sdc_grid_writer.cpp | 124 +++++++++++++----- .../module_builder/build_grid_modules.cpp | 2 +- 2 files changed, 93 insertions(+), 33 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp index 90a58c91c..2a491f129 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp @@ -8,58 +8,107 @@ #include "fpga_x2p_reserved_words.h" #include "fpga_x2p_naming.h" #include "fpga_x2p_utils.h" +#include "fpga_x2p_pbtypes_utils.h" #include "analysis_sdc_grid_writer.h" #include "globals.h" +/******************************************************************** + * Recursively visit all the pb_types in the hierarchy + * and disable all the ports + * + * Note: it is a must to disable all the ports in all the child pb_types! + * This can prohibit timing analyzer to consider any FF-to-FF path or + * combinatinal path inside an unused grid, when finding critical paths!!! + *******************************************************************/ +static +void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& hierarchy_name, + t_pb_graph_node* physical_pb_graph_node, + const e_side& border_side) { + t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + /* Disable all the ports of current module (parent_module)! + * Hierarchy name already includes the instance name of parent_module + */ + fp << "set_disable_timing "; + fp << hierarchy_name; + fp << "/*"; + fp << std::endl; + + /* Return if this is the primitive pb_type */ + if (TRUE == is_primitive_pb_type(physical_pb_type)) { + return; + } + + /* Go recursively */ + int physical_mode_index = find_pb_type_physical_mode_index(*physical_pb_type); + + /* Disable all the ports by iterating over its instance in the parent module */ + for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { + /* Generate the name of the Verilog module for this child */ + std::string child_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string child_module_name = generate_physical_block_module_name(child_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); + + ModuleId child_module = module_manager.find_module(child_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(child_module)); + + /* Each child may exist multiple times in the hierarchy*/ + for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { + std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]); + /* Must have a valid instance name!!! */ + VTR_ASSERT(false == child_instance_name.empty()); + + std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/"); + + rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, module_manager, child_module, hierarchy_name, + &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]), + border_side); + } + } +} + /******************************************************************** * Disable the timing for a fully unused grid! * This is very straightforward! * Just walk through each pb_type and disable all the ports using wildcards *******************************************************************/ static -void print_analysis_sdc_disable_unused_pb_type(std::fstream& fp, - t_type_ptr grid_type, - const vtr::Point& grid_coordinate, - const ModuleManager& module_manager, - const size_t& grid_z, - const e_side& border_side) { +void print_analysis_sdc_disable_unused_pb_block(std::fstream& fp, + t_type_ptr grid_type, + const vtr::Point& grid_coordinate, + const ModuleManager& module_manager, + const std::string& grid_instance_name, + const size_t& grid_z, + const e_side& border_side) { /* Check code: if this is an IO block, the border side MUST be valid */ if (IO_TYPE == grid_type) { VTR_ASSERT(NUM_SIDES != border_side); } - /* Find an unique name to the grid instane - * Note: this must be consistent with the instance name we used in build_top_module()!!! - */ - std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string grid_instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side, grid_coordinate); - /* Find an unique name to the pb instance in this grid * Note: this must be consistent with the instance name we used in build_grid_module()!!! */ + /* TODO: validate that the instance name is used in module manager!!! */ std::string pb_module_name_prefix(GRID_MODULE_NAME_PREFIX); + std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, grid_type->pb_graph_head->pb_type, border_side); std::string pb_instance_name = generate_grid_physical_block_instance_name(pb_module_name_prefix, grid_type->pb_graph_head->pb_type, border_side, grid_z); + ModuleId pb_module = module_manager.find_module(pb_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); + /* Print comments */ fp << "#######################################" << std::endl; fp << "# Disable Timing for unused grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; fp << "#######################################" << std::endl; - - /* Disable everything under this level using wildcard */ - fp << "set_disable_timing "; - fp << grid_instance_name; - fp << "/"; - fp << pb_instance_name; - fp << "/*"; - fp << std::endl; - /* TODO: Go recursively through the pb_graph hierarchy, and disable all the ports level by level */ - /* - rec_verilog_generate_sdc_disable_unused_pb_types(fp, prefix, - cur_grid_type->pb_type); - */ + std::string hierarchy_name = grid_instance_name + std::string("/") + pb_instance_name + std::string("/"); + + /* Go recursively through the pb_graph hierarchy, and disable all the ports level by level */ + rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, module_manager, pb_module, hierarchy_name, grid_type->pb_graph_head, border_side); } /******************************************************************** @@ -77,19 +126,30 @@ void print_analysis_sdc_disable_unused_grid(std::fstream& fp, /* Validate file stream */ check_file_handler(fp); - t_type_ptr type = L_grids[grid_coordinate.x()][grid_coordinate.y()].type; + t_type_ptr grid_type = L_grids[grid_coordinate.x()][grid_coordinate.y()].type; /* Bypass conditions for grids : * 1. EMPTY type, which is by nature unused * 2. Offset > 0, which has already been processed when offset = 0 */ - if ( (NULL == type) - || (EMPTY_TYPE == type) + if ( (NULL == grid_type) + || (EMPTY_TYPE == grid_type) || (0 == L_grids[grid_coordinate.x()][grid_coordinate.y()].offset) ) { return; } + /* Find an unique name to the grid instane + * Note: this must be consistent with the instance name we used in build_top_module()!!! + */ + /* TODO: validate that the instance name is used in module manager!!! */ + std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); + std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); + std::string grid_instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side, grid_coordinate); + + ModuleId grid_module = module_manager.find_module(grid_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); + /* Now we need to find the usage of this grid */ - std::vector grid_usage(type->capacity, false); + std::vector grid_usage(grid_type->capacity, false); /* Print comments */ fp << "#######################################" << std::endl; @@ -102,7 +162,7 @@ void print_analysis_sdc_disable_unused_grid(std::fstream& fp, */ for (int iblk = 0; iblk < L_grids[grid_coordinate.x()][grid_coordinate.y()].usage; ++iblk) { int blk_id = L_grids[grid_coordinate.x()][grid_coordinate.y()].blocks[iblk]; - VTR_ASSERT( (OPEN < L_blocks[blk_id].z) && (L_blocks[blk_id].z < type->capacity) ); + VTR_ASSERT( (OPEN < L_blocks[blk_id].z) && (L_blocks[blk_id].z < grid_type->capacity) ); /* Mark the grid_usage */ grid_usage[L_blocks[blk_id].z] = true; /* TODO: @@ -111,12 +171,12 @@ void print_analysis_sdc_disable_unused_grid(std::fstream& fp, } /* For unused grid, disable all the pins in the physical_pb_type */ - for (int iblk = 0; iblk < type->capacity; ++iblk) { + for (int iblk = 0; iblk < grid_type->capacity; ++iblk) { /* Bypass used blocks */ if (true == grid_usage[iblk]) { continue; } - print_analysis_sdc_disable_unused_pb_type(fp, type, grid_coordinate, module_manager, iblk, border_side); + print_analysis_sdc_disable_unused_pb_block(fp, grid_type, grid_coordinate, module_manager, grid_instance_name, iblk, border_side); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index e23ec60f9..a05d6abf7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -926,7 +926,7 @@ void rec_build_physical_block_modules(ModuleManager& module_manager, /* Add the memory module as a child of primitive module */ module_manager.add_child_module(pb_module, child_pb_module); - /* Set an instance name to bind to a block in bitstream generation */ + /* Set an instance name to bind to a block in bitstream generation and SDC generation! */ std::string child_pb_instance_name = generate_physical_block_instance_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild]), inst); module_manager.set_child_instance_name(pb_module, child_pb_module, child_instance_id, child_pb_instance_name); From d84cd662874c59ee884f80752aac9fe1da993702 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 12 Nov 2019 22:18:13 -0700 Subject: [PATCH 465/482] refactored analysis SDC generator for grids --- .../analysis_sdc_grid_writer.cpp | 387 +++++++++++++++++- .../analysis_sdc_routing_writer.cpp | 98 +---- .../backend_assistant/analysis_sdc_writer.cpp | 2 +- .../analysis_sdc_writer_utils.cpp | 235 +++++++++++ .../analysis_sdc_writer_utils.h | 40 ++ .../module_builder/build_grid_modules.cpp | 6 +- 6 files changed, 653 insertions(+), 115 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp index 2a491f129..235e99bee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp @@ -10,6 +10,8 @@ #include "fpga_x2p_utils.h" #include "fpga_x2p_pbtypes_utils.h" +#include "sdc_writer_utils.h" +#include "analysis_sdc_writer_utils.h" #include "analysis_sdc_grid_writer.h" #include "globals.h" @@ -30,6 +32,9 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp, t_pb_graph_node* physical_pb_graph_node, const e_side& border_side) { t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + /* Validate file stream */ + check_file_handler(fp); /* Disable all the ports of current module (parent_module)! * Hierarchy name already includes the instance name of parent_module @@ -72,23 +77,366 @@ void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp, } /******************************************************************** + * Disable an unused pin of a pb_graph_node (parent_module) + *******************************************************************/ +static +void disable_pb_graph_node_unused_pin(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& hierarchy_name, + const t_pb_graph_pin& pb_graph_pin, + t_phy_pb* block_physical_pb) { + /* Validate file stream */ + check_file_handler(fp); + + int rr_node_index = pb_graph_pin.rr_node_index_physical_pb; + + /* Identify if the net has been used or not */ + if (false == is_rr_node_to_be_disable_for_analysis(&(block_physical_pb->rr_graph->rr_node[rr_node_index]))) { + /* Used pin; Nothing to do */ + return; + } + /* Reach here, it means that this pin is not used. Disable timing analysis for the pin */ + /* Find the module port by name */ + std::string module_port_name = generate_pb_type_port_name(pb_graph_pin.port); + ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port)); + BasicPort port_to_disable = module_manager.module_port(parent_module, module_port); + port_to_disable.set_width(pb_graph_pin.pin_number, pb_graph_pin.pin_number); + + fp << "set_disable_timing "; + fp << hierarchy_name; + fp << "/"; + fp << generate_sdc_port(port_to_disable); + fp << std::endl; +} + +/******************************************************************** + * Disable unused input ports and output ports of this pb_graph_node (parent_module) + * This function will iterate over all the input pins, output pins + * of the physical_pb_graph_node, and check if they are mapped + * For unused pins, we will find the port in parent_module + * and then print SDC commands to disable them + *******************************************************************/ +static +void disable_pb_graph_node_unused_pins(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& hierarchy_name, + t_pb_graph_node* physical_pb_graph_node, + t_phy_pb* block_physical_pb) { + + /* Disable unused input pins */ + for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { + disable_pb_graph_node_unused_pin(fp, module_manager, parent_module, + hierarchy_name, + physical_pb_graph_node->input_pins[iport][ipin], + block_physical_pb); + } + } + + /* Disable unused output pins */ + for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { + disable_pb_graph_node_unused_pin(fp, module_manager, parent_module, + hierarchy_name, + physical_pb_graph_node->output_pins[iport][ipin], + block_physical_pb); + } + } + + /* Disable unused clock pins */ + for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { + disable_pb_graph_node_unused_pin(fp, module_manager, parent_module, + hierarchy_name, + physical_pb_graph_node->clock_pins[iport][ipin], + block_physical_pb); + } + } +} + +/******************************************************************** + * Disable unused inputs of routing multiplexers of this pb_graph_node + * This function will first cache the nets for each input and output pins + * and store the results in a mux_name-to-net mapping + *******************************************************************/ +static +void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& hierarchy_name, + t_pb_graph_node* physical_pb_graph_node, + t_phy_pb* block_physical_pb, + const e_side& border_side) { + t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + int physical_mode_index = find_pb_type_physical_mode_index(*physical_pb_type); + + std::map mux_instance_to_net_map; + + /* Cache the nets for each input pins of each child pb_graph_node */ + for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { + for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { + + t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]); + + /* Cache the nets for input pins of the child pb_graph_node */ + for (int iport = 0; iport < child_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ++ipin) { + int rr_node_index = child_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; + /* Generate the mux name */ + std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(child_pb_graph_node->input_pins[iport][ipin]), std::string("")); + /* Cache the net */ + mux_instance_to_net_map[mux_instance_name] = block_physical_pb->rr_graph->rr_node[rr_node_index].vpack_net_num; + } + } + + /* Cache the nets for clock pins of the child pb_graph_node */ + for (int iport = 0; iport < child_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ++ipin) { + int rr_node_index = child_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; + /* Generate the mux name */ + std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(child_pb_graph_node->clock_pins[iport][ipin]), std::string("")); + /* Cache the net */ + mux_instance_to_net_map[mux_instance_name] = block_physical_pb->rr_graph->rr_node[rr_node_index].vpack_net_num; + } + } + + } + } + + /* Cache the nets for each output pins of this pb_graph_node */ + for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { + int rr_node_index = physical_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; + /* Generate the mux name */ + std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(physical_pb_graph_node->output_pins[iport][ipin]), std::string("")); + /* Cache the net */ + mux_instance_to_net_map[mux_instance_name] = block_physical_pb->rr_graph->rr_node[rr_node_index].vpack_net_num; + } + } + + /* Now disable unused inputs of routing multiplexers, by tracing from input pins of the parent_module */ + for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { + /* Find the module port by name */ + std::string module_port_name = generate_pb_type_port_name(physical_pb_graph_node->input_pins[iport][ipin].port); + ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port)); + + int rr_node_index = physical_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; + t_rr_node* input_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); + + disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module, + hierarchy_name, + module_port, ipin, + input_rr_node, + mux_instance_to_net_map); + } + } + + for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) { + for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { + /* Find the module port by name */ + std::string module_port_name = generate_pb_type_port_name(physical_pb_graph_node->clock_pins[iport][ipin].port); + ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port)); + + int rr_node_index = physical_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; + t_rr_node* input_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); + + disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module, + hierarchy_name, + module_port, ipin, + input_rr_node, + mux_instance_to_net_map); + } + } + + /* Now disable unused inputs of routing multiplexers, by tracing from output pins of the child_module */ + for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { + /* Generate the name of the Verilog module for this child */ + std::string child_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string child_module_name = generate_physical_block_module_name(child_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); + + ModuleId child_module = module_manager.find_module(child_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(child_module)); + + for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { + + t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]); + + for (int iport = 0; iport < child_pb_graph_node->num_output_ports; ++iport) { + for (int ipin = 0; ipin < child_pb_graph_node->num_output_pins[iport]; ++ipin) { + /* Find the module port by name */ + std::string module_port_name = generate_pb_type_port_name(child_pb_graph_node->output_pins[iport][ipin].port); + ModulePortId module_port = module_manager.find_module_port(child_module, module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, module_port)); + + int rr_node_index = child_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; + t_rr_node* output_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); + + disable_analysis_module_output_pin_net_sinks(fp, module_manager, parent_module, + hierarchy_name, + child_module, inst, + module_port, ipin, + output_rr_node, + mux_instance_to_net_map); + } + } + } + } +} + +/******************************************************************** + * Recursively visit all the pb_types in the hierarchy + * and disable all the unused resources, including: + * 1. input ports + * 2. output ports + * 3. unused inputs of routing multiplexers + * + * As this function is executed in a recursive way. + * To avoid repeated disable timing for ports, during each run of this function, + * only the unused input ports, output ports of the parent module will be disabled. + * In addition, we will cache all the net ids mapped to the input ports of + * child modules, and the net ids mapped to the output ports of parent module. + * As such, we can trace from + * 1. the input ports of parent module to disable unused inputs of routing multiplexer + * which drives the inputs of child modules + * + * Parent_module + * +--------------------------------------------- + * | MUX child_module + * | +-------------+ +-------- + * input_pin0(netA) --->|-------->| Routing |------>| + * input_pin1(netB) --->|----x--->| Multiplexer | netA | + * | +-------------+ | + * | | + * + * 2. the output ports of child module to disable unused inputs of routing multiplexer + * which drives the outputs of parent modules + * + * Case 1: + * parent_module + * --------------------------------------+ + * child_module | + * -------------+ | + * | +-------------+ | + * output_pin0 (netA) |--->| Routing |----->|----> + * output_pin1 (netB) |-x->| Multiplexer | netA | + * | +-------------+ | + * + * Case 2: + * + * Parent_module + * +--------------------------------------------- + * | + * | +--------------------------------------------+ + * | | MUX child_module | + * | | +-------------+ +-----------+ | + * | +--->| Routing |------>| | | + * input_pin0(netA) --->|----x--->| Multiplexer | netA | output_pin|-----+ + * | +-------------+ | | netA + * | | | + * + * + * Note: it is a must to disable all the ports in all the child pb_types! + * This can prohibit timing analyzer to consider any FF-to-FF path or + * combinatinal path inside an unused grid, when finding critical paths!!! + *******************************************************************/ +static +void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& hierarchy_name, + t_pb_graph_node* physical_pb_graph_node, + t_phy_pb* block_physical_pb, + const e_side& border_side) { + t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; + + /* Disable unused input ports and output ports of this pb_graph_node (parent_module) */ + disable_pb_graph_node_unused_pins(fp, module_manager, parent_module, + hierarchy_name, physical_pb_graph_node, block_physical_pb); + + /* Return if this is the primitive pb_type + * Note: this must return before we disable any unused inputs of routing multiplexer! + * This is due to that primitive pb_type does NOT contain any routing multiplexers inside!!! + */ + if (TRUE == is_primitive_pb_type(physical_pb_type)) { + return; + } + + /* Disable unused inputs of routing multiplexers of this pb_graph_node */ + disable_pb_graph_node_unused_mux_inputs(fp, module_manager, parent_module, + hierarchy_name, physical_pb_graph_node, block_physical_pb, + border_side); + + + int physical_mode_index = find_pb_type_physical_mode_index(*physical_pb_type); + + /* Disable all the ports by iterating over its instance in the parent module */ + for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { + /* Generate the name of the Verilog module for this child */ + std::string child_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); + std::string child_module_name = generate_physical_block_module_name(child_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); + + ModuleId child_module = module_manager.find_module(child_module_name); + VTR_ASSERT(true == module_manager.valid_module_id(child_module)); + + /* Each child may exist multiple times in the hierarchy*/ + for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { + std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]); + /* Must have a valid instance name!!! */ + VTR_ASSERT(false == child_instance_name.empty()); + + std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/"); + + rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, module_manager, child_module, hierarchy_name, + &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]), + block_physical_pb, border_side); + } + } +} + +/******************************************************************** + * This function can work in two differnt modes: + * 1. For partially unused pb blocks + * --------------------------------- + * Disable the timing for only unused resources in a physical block + * We have to walk through pb_graph node, port by port and pin by pin. + * Identify which pins have not been used, and then disable the timing + * for these ports. + * Plus, for input ports, we will trace the routing multiplexers + * and disable the timing for unused inputs. + * + * 2. For fully unused pb_blocks + * ----------------------------- * Disable the timing for a fully unused grid! * This is very straightforward! * Just walk through each pb_type and disable all the ports using wildcards *******************************************************************/ static -void print_analysis_sdc_disable_unused_pb_block(std::fstream& fp, - t_type_ptr grid_type, - const vtr::Point& grid_coordinate, - const ModuleManager& module_manager, - const std::string& grid_instance_name, - const size_t& grid_z, - const e_side& border_side) { +void print_analysis_sdc_disable_pb_block_unused_resources(std::fstream& fp, + t_type_ptr grid_type, + const vtr::Point& grid_coordinate, + const ModuleManager& module_manager, + const std::string& grid_instance_name, + const size_t& grid_z, + const e_side& border_side, + t_phy_pb* block_physical_pb, + const bool& unused_block) { /* Check code: if this is an IO block, the border side MUST be valid */ if (IO_TYPE == grid_type) { VTR_ASSERT(NUM_SIDES != border_side); } + /* If the block is partially unused, we should have a physical pb */ + if (false == unused_block) { + VTR_ASSERT(NULL != block_physical_pb); + } + /* Find an unique name to the pb instance in this grid * Note: this must be consistent with the instance name we used in build_grid_module()!!! */ @@ -102,13 +450,25 @@ void print_analysis_sdc_disable_unused_pb_block(std::fstream& fp, /* Print comments */ fp << "#######################################" << std::endl; - fp << "# Disable Timing for unused grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; + + if (true == unused_block) { + fp << "# Disable Timing for unused grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; + } else { + VTR_ASSERT_SAFE(false == unused_block); + fp << "# Disable Timing for unused resources in grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; + } + fp << "#######################################" << std::endl; std::string hierarchy_name = grid_instance_name + std::string("/") + pb_instance_name + std::string("/"); /* Go recursively through the pb_graph hierarchy, and disable all the ports level by level */ - rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, module_manager, pb_module, hierarchy_name, grid_type->pb_graph_head, border_side); + if (true == unused_block) { + rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, module_manager, pb_module, hierarchy_name, grid_type->pb_graph_head, border_side); + } else { + VTR_ASSERT_SAFE(false == unused_block); + rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, module_manager, pb_module, hierarchy_name, grid_type->pb_graph_head, block_physical_pb, border_side); + } } /******************************************************************** @@ -133,7 +493,7 @@ void print_analysis_sdc_disable_unused_grid(std::fstream& fp, */ if ( (NULL == grid_type) || (EMPTY_TYPE == grid_type) - || (0 == L_grids[grid_coordinate.x()][grid_coordinate.y()].offset) ) { + || (0 < L_grids[grid_coordinate.x()][grid_coordinate.y()].offset) ) { return; } @@ -168,6 +528,8 @@ void print_analysis_sdc_disable_unused_grid(std::fstream& fp, /* TODO: verilog_generate_sdc_disable_one_unused_block(fp, &(L_blocks[blk_id])); */ + t_phy_pb* block_phy_pb = (t_phy_pb*) L_blocks[blk_id].phy_pb; + print_analysis_sdc_disable_pb_block_unused_resources(fp, grid_type, grid_coordinate, module_manager, grid_instance_name, iblk, border_side, block_phy_pb, false); } /* For unused grid, disable all the pins in the physical_pb_type */ @@ -176,7 +538,7 @@ void print_analysis_sdc_disable_unused_grid(std::fstream& fp, if (true == grid_usage[iblk]) { continue; } - print_analysis_sdc_disable_unused_pb_block(fp, grid_type, grid_coordinate, module_manager, grid_instance_name, iblk, border_side); + print_analysis_sdc_disable_pb_block_unused_resources(fp, grid_type, grid_coordinate, module_manager, grid_instance_name, iblk, border_side, NULL, true); } } @@ -207,9 +569,6 @@ void print_analysis_sdc_disable_unused_grids(std::fstream& fp, const std::vector>& L_grids, const std::vector& L_blocks, const ModuleManager& module_manager) { - /* TODO: disable inputs of multiplexers - verilog_generate_sdc_disable_unused_grids_muxs(fp, LL_nx, LL_ny, LL_grid, LL_block); - */ /* Process unused core grids */ for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp index 312696456..0509c08de 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp @@ -14,107 +14,11 @@ #include "fpga_x2p_types.h" #include "sdc_writer_utils.h" +#include "analysis_sdc_writer_utils.h" #include "analysis_sdc_routing_writer.h" #include "globals.h" -/******************************************************************** - * Identify if a node should be disabled during analysis SDC generation - *******************************************************************/ -static -bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { - /* Conditions to enable timing analysis for a node - * 1st condition: it have a valid vpack_net_number - * 2nd condition: it is not an parasitic net - * 3rd condition: it is not a global net - */ - if ( (OPEN != cur_rr_node->vpack_net_num) - && (FALSE == cur_rr_node->is_parasitic_net) - && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_global) - && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_const_gen) ){ - return false; - } - return true; -} - -/******************************************************************** - * Disable all the unused inputs of routing multiplexers, which are not used by benchmark - * Here, we start from each input of a routing module, and traverse forward to the sink - * port of the module net whose source is the input - * We will find the instance name which is the parent of the sink port, and search the - * net id through the instance_name_to_net_map - * The the net id does not match the net id of this input, we will disable the sink port! - * - * parent_module - * +----------------------- - * | MUX instance A - * | +----------- - * input_port--->|--+---x-->| sink port (disable! net_id = Y) - * (net_id = X) | | +---------- - * | | MUX instance B - * | | +---------- - * | +------>| sink port (do not disable! net_id = X) - * - *******************************************************************/ -static -void disable_analysis_module_input_port_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModulePortId& module_input_port, - t_rr_node* input_rr_node, - const std::map mux_instance_to_net_map) { - /* Validate file stream */ - check_file_handler(fp); - - /* Find the module net which sources from this port! */ - for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) { - ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, pin); - VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net)); - - /* Touch each sink of the net! */ - for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) { - ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; - size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; - - /* Skip when sink module is the parent module, - * the output ports of parent modules have been disabled/enabled already! - */ - if (sink_module == parent_module) { - continue; - } - - std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance); - bool disable_timing = false; - /* Check if this node is used by benchmark */ - if (true == is_rr_node_to_be_disable_for_analysis(input_rr_node)) { - /* Disable all the sinks! */ - disable_timing = true; - } else { - /* See if the net id matches. If does not match, we should disable! */ - if (input_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) { - disable_timing = true; - } - } - - /* Time to write SDC command to disable timing or not */ - if (false == disable_timing) { - continue; - } - - BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]); - sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id], - module_manager.net_sink_pins(parent_module, module_net)[sink_id]); - /* Get the input id that is used! Disable the unused inputs! */ - fp << "set_disable_timing "; - fp << parent_instance_name << "/"; - fp << sink_instance_name << "/"; - fp << generate_sdc_port(sink_port); - fp << std::endl; - } - } -} - /******************************************************************** * This function will disable * 1. all the unused port (unmapped by a benchmark) of a connection block diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp index 8aed25fc0..d4297d8dc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp @@ -255,7 +255,7 @@ void print_analysis_sdc(const std::string& sdc_dir, L_device_rr_gsb, compact_routing_hierarchy); - /* TODO: Disable timing for unused routing resources in grids (programmable blocks) */ + /* Disable timing for unused routing resources in grids (programmable blocks) */ print_analysis_sdc_disable_unused_grids(fp, device_size, L_grids, L_blocks, module_manager); /* Close file handler */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp new file mode 100644 index 000000000..3c2885fd3 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp @@ -0,0 +1,235 @@ +/******************************************************************** + * This file includes most utilized functions + * that are used to output a SDC file + * in order to constrain a FPGA fabric (P&Red netlist) mapped to a benchmark + *******************************************************************/ +#include "vtr_assert.h" + +#include "fpga_x2p_utils.h" + +#include "sdc_writer_utils.h" +#include "analysis_sdc_writer_utils.h" + +#include "globals.h" + +/******************************************************************** + * Identify if a node should be disabled during analysis SDC generation + *******************************************************************/ +bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { + /* Conditions to enable timing analysis for a node + * 1st condition: it have a valid vpack_net_number + * 2nd condition: it is not an parasitic net + * 3rd condition: it is not a global net + */ + if ( (OPEN != cur_rr_node->vpack_net_num) + && (FALSE == cur_rr_node->is_parasitic_net) + && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_global) + && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_const_gen) ){ + return false; + } + return true; +} + +/******************************************************************** + * Disable all the unused inputs of routing multiplexers, which are not used by benchmark + * Here, we start from each input of a routing module, and traverse forward to the sink + * port of the module net whose source is the input + * We will find the instance name which is the parent of the sink port, and search the + * net id through the instance_name_to_net_map + * The the net id does not match the net id of this input, we will disable the sink port! + * + * parent_module + * +----------------------- + * | MUX instance A + * | +----------- + * input_port--->|--+---x-->| sink port (disable! net_id = Y) + * (net_id = X) | | +---------- + * | | MUX instance B + * | | +---------- + * | +------>| sink port (do not disable! net_id = X) + * + *******************************************************************/ +void disable_analysis_module_input_pin_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModulePortId& module_input_port, + const size_t& module_input_pin, + t_rr_node* input_rr_node, + const std::map mux_instance_to_net_map) { + /* Validate file stream */ + check_file_handler(fp); + + /* Find the module net which sources from this port! */ + ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, module_input_pin); + VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net)); + + /* Touch each sink of the net! */ + for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) { + ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; + size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; + + /* Skip when sink module is the parent module, + * the output ports of parent modules have been disabled/enabled already! + */ + if (sink_module == parent_module) { + continue; + } + + std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance); + bool disable_timing = false; + /* Check if this node is used by benchmark */ + if (true == is_rr_node_to_be_disable_for_analysis(input_rr_node)) { + /* Disable all the sinks! */ + disable_timing = true; + } else { + std::map::const_iterator it = mux_instance_to_net_map.find(sink_instance_name); + if (it != mux_instance_to_net_map.end()) { + /* See if the net id matches. If does not match, we should disable! */ + if (input_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) { + disable_timing = true; + } + } + } + + /* Time to write SDC command to disable timing or not */ + if (false == disable_timing) { + continue; + } + + BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]); + sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id], + module_manager.net_sink_pins(parent_module, module_net)[sink_id]); + /* Get the input id that is used! Disable the unused inputs! */ + fp << "set_disable_timing "; + fp << parent_instance_name << "/"; + fp << sink_instance_name << "/"; + fp << generate_sdc_port(sink_port); + fp << std::endl; + } +} + + +/******************************************************************** + * Disable all the unused inputs of routing multiplexers, which are not used by benchmark + * Here, we start from each input of a routing module, and traverse forward to the sink + * port of the module net whose source is the input + * We will find the instance name which is the parent of the sink port, and search the + * net id through the instance_name_to_net_map + * The the net id does not match the net id of this input, we will disable the sink port! + * + * parent_module + * +----------------------- + * | MUX instance A + * | +----------- + * input_port--->|--+---x-->| sink port (disable! net_id = Y) + * (net_id = X) | | +---------- + * | | MUX instance B + * | | +---------- + * | +------>| sink port (do not disable! net_id = X) + * + *******************************************************************/ +void disable_analysis_module_input_port_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModulePortId& module_input_port, + t_rr_node* input_rr_node, + const std::map mux_instance_to_net_map) { + /* Validate file stream */ + check_file_handler(fp); + + /* Find the module net which sources from this port! */ + for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) { + disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module, + parent_instance_name, + module_input_port, pin, + input_rr_node, + mux_instance_to_net_map); + } +} + +/******************************************************************** + * Disable all the unused inputs of routing multiplexers, which are not used by benchmark + * Here, we start from each output of a child module, and traverse forward to the sink + * port of the module net whose source is the input + * We will find the instance name which is the parent of the sink port, and search the + * net id through the instance_name_to_net_map + * The the net id does not match the net id of this input, we will disable the sink port! + * + * Parent_module + * +--------------------------------------------- + * | + * | +--------------------------------------------+ + * | | MUX child_module | + * | | +-------------+ +-----------+ | + * | +--->| Routing |------>| | | + * input_pin0(netA) --->|----x--->| Multiplexer | netA | output_pin|-----+ + * | +-------------+ | | netA + * | | | + * + + * + *******************************************************************/ +void disable_analysis_module_output_pin_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModuleId& child_module, + const size_t& child_instance, + const ModulePortId& child_module_port, + const size_t& child_module_pin, + t_rr_node* output_rr_node, + const std::map mux_instance_to_net_map) { + /* Validate file stream */ + check_file_handler(fp); + + /* Find the module net which sources from this port! */ + ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, child_module, child_instance, child_module_port, child_module_pin); + VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net)); + + /* Touch each sink of the net! */ + for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) { + ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; + size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; + + /* Skip when sink module is the parent module, + * the output ports of parent modules have been disabled/enabled already! + */ + if (sink_module == parent_module) { + continue; + } + + std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance); + bool disable_timing = false; + /* Check if this node is used by benchmark */ + if (true == is_rr_node_to_be_disable_for_analysis(output_rr_node)) { + /* Disable all the sinks! */ + disable_timing = true; + } else { + std::map::const_iterator it = mux_instance_to_net_map.find(sink_instance_name); + if (it != mux_instance_to_net_map.end()) { + /* See if the net id matches. If does not match, we should disable! */ + if (output_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) { + disable_timing = true; + } + } + } + + /* Time to write SDC command to disable timing or not */ + if (false == disable_timing) { + continue; + } + + BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]); + sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id], + module_manager.net_sink_pins(parent_module, module_net)[sink_id]); + /* Get the input id that is used! Disable the unused inputs! */ + fp << "set_disable_timing "; + fp << parent_instance_name << "/"; + fp << sink_instance_name << "/"; + fp << generate_sdc_port(sink_port); + fp << std::endl; + } +} + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h new file mode 100644 index 000000000..7b5ff9348 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h @@ -0,0 +1,40 @@ +#ifndef ANALYSIS_SDC_WRITER_UTILS_H +#define ANALYSIS_SDC_WRITER_UTILS_H + +#include +#include +#include +#include "module_manager.h" +#include "vpr_types.h" + +bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node); + +void disable_analysis_module_input_pin_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModulePortId& module_input_port, + const size_t& module_input_pin, + t_rr_node* input_rr_node, + const std::map mux_instance_to_net_map); + +void disable_analysis_module_input_port_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModulePortId& module_input_port, + t_rr_node* input_rr_node, + const std::map mux_instance_to_net_map) ; + +void disable_analysis_module_output_pin_net_sinks(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const std::string& parent_instance_name, + const ModuleId& child_module, + const size_t& child_instance, + const ModulePortId& child_module_port, + const size_t& child_module_pin, + t_rr_node* output_rr_node, + const std::map mux_instance_to_net_map); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index a05d6abf7..f6a940d85 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -483,7 +483,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, } /* Initialize the interconnection type that will be physically implemented in module */ - enum e_interconnect verilog_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); + enum e_interconnect interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); /* Find input ports of the wire module */ std::vector interc_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ @@ -497,7 +497,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Branch on the type of physical implementation, * We add instances of programmable interconnection */ - switch (verilog_interc_type) { + switch (interc_type) { case DIRECT_INTERC: { /* Ensure direct interc has only one fan-in */ VTR_ASSERT(1 == fan_in); @@ -521,7 +521,7 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager, /* Get the instance id and add an instance of wire */ size_t wire_instance = module_manager.num_instance(pb_module, wire_module); module_manager.add_child_module(pb_module, wire_module); - + /* Ensure input and output ports of the wire model has only 1 pin respectively */ VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0])); VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); From 1291b99d66b95309538941e9f1c7079403d85a5b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 13 Nov 2019 12:55:57 -0700 Subject: [PATCH 466/482] now make ini file generation more flexible: user can specify a name or use the default name --- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 1 + vpr7_x2p/vpr/SRC/base/OptionTokens.h | 1 + vpr7_x2p/vpr/SRC/base/ReadOptions.c | 2 + vpr7_x2p/vpr/SRC/base/SetupVPR.c | 6 ++- vpr7_x2p/vpr/SRC/base/vpr_api.c | 3 +- .../verilog/simulation_info_writer.cpp | 41 ++++++++++++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 ++- 7 files changed, 47 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index cdf5eef91..b8ef5c44a 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -101,6 +101,7 @@ struct s_TokenPair OptionBaseTokenList[] = { { "fpga_verilog_print_sdc_pnr", OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR }, /* Specify the simulator path for Verilog netlists */ { "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */ { "fpga_verilog_print_simulation_ini", OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI }, /* Specify the simulator path for Verilog netlists */ + { "fpga_verilog_simulation_ini_file", OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE }, /* Specify the simulator path for Verilog netlists */ /* Xifan Tang: Bitstream generator */ { "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */ // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index 706a81b24..5b20ef1cd 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -118,6 +118,7 @@ enum e_OptionBaseToken { OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR, OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS, OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI, + OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE, /* Xifan Tang: Bitstream generator */ OT_FPGA_BITSTREAM_GENERATOR, OT_FPGA_BITSTREAM_OUTPUT_FILE, diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index d2f692774..e51dcf530 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -560,6 +560,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS: return Args; case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI: + return Args; + case OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE: return ReadString(Args, &Options->fpga_verilog_simulation_ini_path); /* Xifan TANG: Bitstream generator */ case OT_FPGA_BITSTREAM_GENERATOR: diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 56ec465d2..f1443c4f7 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1114,6 +1114,7 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->print_sdc_analysis = FALSE; syn_verilog_opts->include_icarus_simulator = FALSE; syn_verilog_opts->print_simulation_ini = FALSE; + syn_verilog_opts->simulation_ini_path = NULL; /* Turn on Syn_verilog options */ if (Options.Count[OT_FPGA_VERILOG_SYN]) { @@ -1186,7 +1187,10 @@ static void SetupSynVerilogOpts(t_options Options, if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) { syn_verilog_opts->print_simulation_ini = TRUE; - syn_verilog_opts->simulation_ini_path = my_strdup(Options.fpga_verilog_simulation_ini_path); + + if (Options.Count[OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE]) { + syn_verilog_opts->simulation_ini_path = my_strdup(Options.fpga_verilog_simulation_ini_path); + } } /* SynVerilog needs the input from spice modeling */ diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 552a90b36..3b2471a72 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -211,7 +211,8 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini \n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_simulation_ini_file \n"); /* Xifan Tang: Bitstream generator */ vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp index aa59a003b..e2b347f84 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp @@ -2,8 +2,8 @@ * This function includes the writer for generating exchangeable * information, in order to interface different simulators ********************************************************************/ -#include -#include +#include +#include #include #define MINI_CASE_SENSITIVE #include "ini.h" @@ -18,6 +18,11 @@ #include "verilog_global.h" #include "simulation_info_writer.h" +/********************************************************************* + * Local Variable + ********************************************************************/ +constexpr char* DEFAULT_SIMULATION_INI_FILE_NAME = "simulation_deck_info.ini"; + /********************************************************************* * Top-level function to write an ini file which contains exchangeable * information, in order to interface different Verilog simulators @@ -30,6 +35,22 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, const int& num_operating_clock_cycles, const float& prog_clock_freq, const float& op_clock_freq) { + + /* Start time count */ + clock_t t_start = clock(); + + /* Use default name if user does not provide one */ + std::string ini_fname; + if (true == simulation_ini_filename.empty()) { + ini_fname = parent_dir + std::string(DEFAULT_SIMULATION_INI_FILE_NAME); + } else { + ini_fname = simulation_ini_filename; + } + + vpr_printf(TIO_MESSAGE_INFO, + "Writing exchangeable file containing simulation information: %s...", + ini_fname.c_str()); + mINI::INIStructure ini; // std::map units_map; // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; @@ -50,14 +71,14 @@ void print_verilog_simulation_info(const std::string& simulation_ini_filename, ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); - /* Use default name if user does not provide one */ - std::string ini_fname; - if (true == simulation_ini_filename.empty()) { - ini_fname = parent_dir + std::string("SimulationDeckInfo.ini"); - } else { - ini_fname = simulation_ini_filename; - } - mINI::INIFile file(ini_fname); file.generate(ini, true); + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a92e8b598..57e742fe7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -438,7 +438,11 @@ void vpr_fpga_verilog(ModuleManager& module_manager, if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { /* Print exchangeable files which contains simulation settings */ - print_verilog_simulation_info(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path), + std::string simulation_ini_file_name; + if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path) { + simulation_ini_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path); + } + print_verilog_simulation_info(simulation_ini_file_name, std::string(format_dir_path(chomped_parent_dir)), std::string(chomped_circuit_name), std::string(src_dir_path), From 0c2ad5ab5e1c5317ae166d2e1f07edc46c0700dc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 13 Nov 2019 20:45:41 -0700 Subject: [PATCH 467/482] critical bug fixed for some corner cases --- .../backend_assistant/analysis_sdc_grid_writer.cpp | 5 +++++ .../backend_assistant/pnr_sdc_routing_writer.cpp | 10 ++++++++++ .../fpga_x2p/module_builder/build_routing_modules.cpp | 2 +- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c | 6 +++++- 4 files changed, 21 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp index 235e99bee..9eac8c52a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp @@ -278,6 +278,11 @@ void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp, int rr_node_index = child_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; t_rr_node* output_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); + /* Corner case: if the rr node has no fan-out we will skip this pin */ + if (0 == output_rr_node->num_edges) { + continue; + } + disable_analysis_module_output_pin_net_sinks(fp, module_manager, parent_module, hierarchy_name, child_module, inst, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp index 13bc17d1c..1efc9279c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp @@ -237,6 +237,15 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, check_file_handler(fp); VTR_ASSERT(IPIN == output_rr_node->type); + + /* We have OPINs since we may have direct connections: + * These connections should be handled by other functions in the compact_netlist.c + * So we just return here for OPINs + */ + if ( (1 == output_rr_node->num_drive_rr_nodes) + && (OPIN == output_rr_node->drive_rr_nodes[0]->type) ) { + return; + } /* Find the module port corresponding to the output rr_node */ ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, @@ -247,6 +256,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ std::vector input_rr_nodes; for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { + /* Skip OPINs which should be handled in direct connection */ input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index b43baa0f4..fcd0f93d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -446,7 +446,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager, /* Ensure we have only one 1 driver node */ VTR_ASSERT_SAFE(1 == src_rr_node->fan_in); - /* Find the driver node */ + /* Find the driver node */ t_rr_node* drive_rr_node = src_rr_node->drive_rr_nodes[0]; /* We have OPINs since we may have direct connections: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 57e742fe7..9047cb473 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -515,9 +515,13 @@ void vpr_fpga_verilog(ModuleManager& module_manager, } /* Print a Verilog file including all the netlists that have been generated */ + std::string ref_verilog_benchmark_file_name; + if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file) { + ref_verilog_benchmark_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file); + } print_include_netlists(std::string(src_dir_path), std::string(chomped_circuit_name), - std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file), + ref_verilog_benchmark_file_name, Arch.spice->circuit_lib); vpr_printf(TIO_MESSAGE_INFO, "Outputted %lu Verilog modules in total.\n", module_manager.num_modules()); From 4df6402241081be24bec92c7a0d09dc8d735ffc5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 15 Nov 2019 14:23:03 -0700 Subject: [PATCH 468/482] add python script for batch simulations --- openfpga_flow/scripts/run_simulation_task.py | 71 +++++++++++++++++++ .../tasks/single_mode/config/task.conf | 1 + 2 files changed, 72 insertions(+) create mode 100644 openfpga_flow/scripts/run_simulation_task.py diff --git a/openfpga_flow/scripts/run_simulation_task.py b/openfpga_flow/scripts/run_simulation_task.py new file mode 100644 index 000000000..ad1e5f863 --- /dev/null +++ b/openfpga_flow/scripts/run_simulation_task.py @@ -0,0 +1,71 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Script Name : regression.py +# Description : This script designed to run: +# openfpga_flow tasks +# run_{simulator}.py +# Args : python3 regression.py --help +# Author : Aurelien Alacchi +# Email : aurelien.alacchi@utah.edu +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +import os +import sys +import shutil +import time +from datetime import timedelta +import shlex +import argparse +from configparser import ConfigParser, ExtendedInterpolation +import logging +import glob +import subprocess +import threading +import csv +from string import Template +import pprint +from importlib import util +from collections import OrderedDict + +modelsim="modelsim" +vcs="vcs" +formality="formality" +modelsim_file="simulation_deck_info.ini" +ini_list="" + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Parse commandline arguments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +parser = argparse.ArgumentParser() +parser.add_argument('tasks', nargs='+') +parser.add_argument('--maxthreads', type=int, default=2, + help="Number of fpga_flow threads to run default = 2," + + "Typically <= Number of processors on the system") +parser.add_argument('--simulator', type=str, default=modelsim, + help="Simulator to use. Set at \"" + modelsim + "\" by default. Can also be \"" + vcs + "\" or \"" + formality + "\"") +args = parser.parse_args() + + +args.tasks=str(args.tasks).strip('[]') +#print(args.tasks) +#print(args.maxthreads) + +command="python3 openfpga_flow/scripts/run_fpga_task.py " + args.tasks + " --maxthreads " + str(args.maxthreads) + " --debug --show_thread_logs" + +print(command) + +os.system(command) + +if(args.simulator == modelsim): + command="python3 openfpga_flow/scripts/run_modelsim.py" + os.system("grep \"INFO - Run directory :\" openfpga_flow/tasks/" + args.tasks + "/latest/*.log > paths_ini.txt") + arguments = " --skip_prompt --run_sim"; + fp = open("paths_ini.txt") + line = fp.readline() + while line: + ini_list= ini_list + line + modelsim_file + line = fp.readline() + ini_list = ini_list.replace("INFO - Run directory :", "") + ini_list = ini_list.replace("\n", "/") + fp.close() + print(command + ini_list + arguments) + os.system(command + ini_list + arguments) diff --git a/openfpga_flow/tasks/single_mode/config/task.conf b/openfpga_flow/tasks/single_mode/config/task.conf index 4d721002b..e3e2d3e8c 100644 --- a/openfpga_flow/tasks/single_mode/config/task.conf +++ b/openfpga_flow/tasks/single_mode/config/task.conf @@ -55,4 +55,5 @@ vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_verilog_explicit_mapping= vpr_fpga_x2p_compact_routing_hierarchy= +#vpr_fpga_verilog_print_simulation_ini= end_flow_with_test= From 333d10c94ce103f511917b9bafc725c2880238d2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 15 Nov 2019 14:26:57 -0700 Subject: [PATCH 469/482] Added vpr_fpga_verilog_print_simulation_ini option --- openfpga_flow/scripts/run_fpga_flow.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 06a52e6d7..04634071f 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -191,9 +191,8 @@ VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true", VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb', action="store_true", help="Print testbench" + "for input blif file in Verilog Generator") -VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str, - help="Print modelsim " + - "simulation script", metavar="") +VeriPar.add_argument('--vpr_fpga_verilog_print_simulation_ini', action="store_true", + help="Create simulation INI file") VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true", help="Explicit Mapping") @@ -721,9 +720,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command += ["--fpga_verilog_include_signal_init"] if args.vpr_fpga_verilog_formal_verification_top_netlist: command += ["--fpga_verilog_print_formal_verification_top_netlist"] - if args.vpr_fpga_verilog_print_modelsim_autodeck: - command += ["--fpga_verilog_print_modelsim_autodeck", - args.vpr_fpga_verilog_print_modelsim_autodeck] + if args.vpr_fpga_verilog_print_simulation_ini: + command += ["--fpga_verilog_print_simulation_ini"] if args.vpr_fpga_verilog_include_icarus_simulator: command += ["--fpga_verilog_include_icarus_simulator"] if args.vpr_fpga_verilog_print_report_timing_tcl: From f52eaef622175403f761aad6c872a3552b9947da Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 15 Nov 2019 14:35:15 -0700 Subject: [PATCH 470/482] Updated flow script and skipped travis upload on failure test setup. --- openfpga_flow/scripts/run_fpga_flow.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 06a52e6d7..04634071f 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -191,9 +191,8 @@ VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true", VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb', action="store_true", help="Print testbench" + "for input blif file in Verilog Generator") -VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str, - help="Print modelsim " + - "simulation script", metavar="") +VeriPar.add_argument('--vpr_fpga_verilog_print_simulation_ini', action="store_true", + help="Create simulation INI file") VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true", help="Explicit Mapping") @@ -721,9 +720,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command += ["--fpga_verilog_include_signal_init"] if args.vpr_fpga_verilog_formal_verification_top_netlist: command += ["--fpga_verilog_print_formal_verification_top_netlist"] - if args.vpr_fpga_verilog_print_modelsim_autodeck: - command += ["--fpga_verilog_print_modelsim_autodeck", - args.vpr_fpga_verilog_print_modelsim_autodeck] + if args.vpr_fpga_verilog_print_simulation_ini: + command += ["--fpga_verilog_print_simulation_ini"] if args.vpr_fpga_verilog_include_icarus_simulator: command += ["--fpga_verilog_include_icarus_simulator"] if args.vpr_fpga_verilog_print_report_timing_tcl: From f05aede868b4f088f66944ae336f7b516f17f1ab Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 15 Nov 2019 23:23:15 -0700 Subject: [PATCH 471/482] Added task support for modelsim script --- openfpga_flow/misc/modelsim_proc.tcl | 2 +- openfpga_flow/scripts/run_modelsim.py | 84 ++++++++++++++++++++++++--- 2 files changed, 76 insertions(+), 10 deletions(-) diff --git a/openfpga_flow/misc/modelsim_proc.tcl b/openfpga_flow/misc/modelsim_proc.tcl index cede56af4..69972b764 100644 --- a/openfpga_flow/misc/modelsim_proc.tcl +++ b/openfpga_flow/misc/modelsim_proc.tcl @@ -47,7 +47,7 @@ proc top_create_new_project {projectname verilog_files modelsim_path simtime uni #Start the simulation vsim $projectname.$top_tb -voptargs=+acc #Add the waves - add_waves top_tb + add_waves $top_tb #run the simulation runsim $simtime $unit #Fit the window view diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py index 0ddbe118c..2f4ac5fc4 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_modelsim.py @@ -1,12 +1,12 @@ from string import Template import sys import os -import pprint +import re +import glob import argparse import subprocess import logging -from pprint import pprint -from configparser import ConfigParser +from configparser import ConfigParser, ExtendedInterpolation # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system @@ -20,7 +20,8 @@ logger = logging.getLogger('Modelsim_run_log') # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = parser = argparse.ArgumentParser() parser.add_argument('files', nargs='+', - help="Pass SimulationDeckInfo generated by OpenFPGA flow") + help="Pass SimulationDeckInfo generated by OpenFPGA flow" + + " or pass taskname ") parser.add_argument('--modelsim_proc_tmpl', type=str, help="Modelsim proc template file") parser.add_argument('--modelsim_runsim_tmpl', type=str, @@ -36,9 +37,32 @@ parser.add_argument('--modelsim_ini', type=str, help="Skip any confirmation") parser.add_argument('--skip_prompt', action='store_true', help='Skip any confirmation') +parser.add_argument('--ini_filename', type=str, + default="simulation_deck_info.ini", + help='default INI filename in in fun dir') args = parser.parse_args() -# Consider default formality script template +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Read script configuration file +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +task_script_dir = os.path.dirname(os.path.abspath(__file__)) +script_env_vars = ({"PATH": { + "OPENFPGA_FLOW_PATH": task_script_dir, + "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"), + "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"), + "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"), + "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"), + "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"), + "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, + os.pardir))}}) +config = ConfigParser(interpolation=ExtendedInterpolation()) +config.read_dict(script_env_vars) +config.read_file(open(os.path.join(task_script_dir, 'run_fpga_task.conf'))) +gc = config["GENERAL CONFIGURATION"] + +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Load default templates for modelsim +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = task_script_dir = os.path.dirname(os.path.abspath(__file__)) if not args.modelsim_proc_tmpl: args.modelsim_proc_tmpl = os.path.join(task_script_dir, os.pardir, @@ -52,7 +76,49 @@ args.modelsim_runsim_tmpl = os.path.abspath(args.modelsim_runsim_tmpl) def main(): - for eachFile in args.files: + if os.path.isfile(args.files[0]): + run_modelsim(args.files) + else: + # Check if task directory exists and consistent + taskname = args.files[0] + task_run = "latest" + if len(args.files) > 1: + task_run = f"run{int(args.files[1]):03}" + + temp_dir = os.path.join(gc["task_dir"], taskname) + if not os.path.isdir(temp_dir): + clean_up_and_exit("Task directory [%s] not found" % temp_dir) + temp_dir = os.path.join(gc["task_dir"], taskname, task_run) + if not os.path.isdir(temp_dir): + clean_up_and_exit("Task run directory [%s] not found" % temp_dir) + + logfile = os.path.join(gc["task_dir"], taskname, task_run, "*.log") + logfiles = glob.glob(logfile) + if not len(logfiles): + clean_up_and_exit("No successful run found in [%s]" % temp_dir) + + task_ini_files = [] + for eachfile in logfiles: + with open(eachfile) as fp: + run_dir = [re.findall(r'^INFO.*Run directory : (.*)$', line) + for line in open(eachfile)] + run_dir = filter(bool, run_dir) + for each_run in run_dir: + INIfile = os.path.join(each_run[0], args.ini_filename) + if os.path.isfile(INIfile): + task_ini_files.append(INIfile) + logger.info(f"Found {len(task_ini_files)} INI files") + run_modelsim(task_ini_files) + + +def clean_up_and_exit(msg): + logger.error(msg) + logger.error("Exiting . . . . . .") + exit(1) + + +def run_modelsim(files): + for eachFile in files: eachFile = os.path.abspath(eachFile) pDir = os.path.dirname(eachFile) os.chdir(pDir) @@ -111,10 +177,10 @@ def main(): # Execute modelsim if args.run_sim: os.chdir(args.modelsim_run_dir) - print(args.modelsim_run_dir) modelsim_run_cmd = ["vsim", "-c", "-do", runsim_filename] - run_command("ModelSim Run", "modelsim_run.log", - modelsim_run_cmd) + out = run_command("ModelSim Run", "modelsim_run.log", + modelsim_run_cmd) + logger.info(re.findall(r"(.*Errors.*Warning.*)", out)) else: logger.info("Created runsim and proc files") logger.info(f"runsim_filename {runsim_filename}") From 373dbe0718483ce5c773f41de5d8c645a7993a04 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 16 Nov 2019 01:06:09 -0700 Subject: [PATCH 472/482] First draft for multithreaded Modelsim simulation --- openfpga_flow/scripts/run_modelsim.py | 130 ++++++++++++++++++-------- 1 file changed, 93 insertions(+), 37 deletions(-) diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py index 2f4ac5fc4..cfbd76270 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_modelsim.py @@ -3,6 +3,9 @@ import sys import os import re import glob +import time +import threading +from datetime import timedelta import argparse import subprocess import logging @@ -11,6 +14,7 @@ from configparser import ConfigParser, ExtendedInterpolation # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configure logging system # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +FILE_LOG_FORMAT = '%(levelname)s (%(threadName)10s) - %(message)s' logging.basicConfig(level=logging.INFO, stream=sys.stdout, format='%(levelname)s (%(threadName)10s) - %(message)s') logger = logging.getLogger('Modelsim_run_log') @@ -22,6 +26,11 @@ parser = argparse.ArgumentParser() parser.add_argument('files', nargs='+', help="Pass SimulationDeckInfo generated by OpenFPGA flow" + " or pass taskname ") +parser.add_argument('--maxthreads', type=int, default=2, + help="Number of fpga_flow threads to run default = 2," + + "Typically <= Number of processors on the system") +parser.add_argument('--debug', action="store_true", + help="Run script in debug mode") parser.add_argument('--modelsim_proc_tmpl', type=str, help="Modelsim proc template file") parser.add_argument('--modelsim_runsim_tmpl', type=str, @@ -77,7 +86,7 @@ args.modelsim_runsim_tmpl = os.path.abspath(args.modelsim_runsim_tmpl) def main(): if os.path.isfile(args.files[0]): - run_modelsim(args.files) + create_tcl_script(args.files) else: # Check if task directory exists and consistent taskname = args.files[0] @@ -92,7 +101,17 @@ def main(): if not os.path.isdir(temp_dir): clean_up_and_exit("Task run directory [%s] not found" % temp_dir) - logfile = os.path.join(gc["task_dir"], taskname, task_run, "*.log") + # = = = = = = = Create a current script log file handler = = = = + logfile_path = os.path.join(gc["task_dir"], + taskname, task_run, "modelsim_run.log") + logfilefh = logging.FileHandler(logfile_path, "w") + logfilefh.setFormatter(logging.Formatter(FILE_LOG_FORMAT)) + logger.addHandler(logfilefh) + logger.info("Created log file at %s" % logfile_path) + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + # = = = = Read Task log file and extract run directory = = = + logfile = os.path.join(gc["task_dir"], taskname, task_run, "*_out.log") logfiles = glob.glob(logfile) if not len(logfiles): clean_up_and_exit("No successful run found in [%s]" % temp_dir) @@ -108,7 +127,7 @@ def main(): if os.path.isfile(INIfile): task_ini_files.append(INIfile) logger.info(f"Found {len(task_ini_files)} INI files") - run_modelsim(task_ini_files) + create_tcl_script(task_ini_files) def clean_up_and_exit(msg): @@ -117,7 +136,8 @@ def clean_up_and_exit(msg): exit(1) -def run_modelsim(files): +def create_tcl_script(files): + runsim_files = [] for eachFile in files: eachFile = os.path.abspath(eachFile) pDir = os.path.dirname(eachFile) @@ -173,42 +193,78 @@ def run_modelsim(files): with open(proc_filename, 'w', encoding='utf-8') as tclout: tclout.write(open(args.modelsim_proc_tmpl, encoding='utf-8').read()) - - # Execute modelsim - if args.run_sim: - os.chdir(args.modelsim_run_dir) - modelsim_run_cmd = ["vsim", "-c", "-do", runsim_filename] - out = run_command("ModelSim Run", "modelsim_run.log", - modelsim_run_cmd) - logger.info(re.findall(r"(.*Errors.*Warning.*)", out)) - else: - logger.info("Created runsim and proc files") - logger.info(f"runsim_filename {runsim_filename}") - logger.info(f"proc_filename {proc_filename}") + runsim_files.append({ + "modelsim_run_dir": args.modelsim_run_dir, + "runsim_filename": runsim_filename, + "status" :False, + "finished" : True + }) + # Execute modelsim + if args.run_sim: + thread_sema = threading.Semaphore(args.maxthreads) + logger.info("Launching %d parallel threads" % args.maxthreads) + thread_list = [] + for thread_no, eachjob in enumerate(runsim_files): + t = threading.Thread(target=run_modelsim_thread, + name=f"Thread_{thread_no:d}", + args=(thread_sema, eachjob, runsim_files)) + t.start() + thread_list.append(t) + for eachthread in thread_list: + eachthread.join() + exit() + else: + logger.info("Created runsim and proc files") + logger.info(f"runsim_filename {runsim_filename}") + logger.info(f"proc_filename {proc_filename}") + from pprint import pprint + pprint(runsim_files) -def run_command(taskname, logfile, command, exit_if_fail=True): - # os.chdir(os.pardir) - logger.info("Launching %s " % taskname) - with open(logfile, 'w+') as output: +def run_modelsim_thread(s, eachJob, job_list): + os.chdir(eachJob["modelsim_run_dir"]) + with s: + thread_name = threading.currentThread().getName() + eachJob["starttime"] = time.time() try: - output.write(os.getcwd() + "\n") - output.write(" ".join(command)+"\n") - process = subprocess.run(command, - check=True, - stdout=subprocess.PIPE, - stderr=subprocess.PIPE, - universal_newlines=True) - output.write(process.stdout) - if process.returncode: - logger.error("%s run failed with returncode %d" % - (taskname, process.returncode)) - except (Exception, subprocess.CalledProcessError) as e: - logger.exception("failed to execute %s" % taskname) - return None - logger.info("%s is written in file %s" % (taskname, logfile)) - return process.stdout - + logfile = "%s_modelsim.log" % thread_name + with open(logfile, 'w+') as output: + output.write("* "*20 + '\n') + output.write("RunDirectory : %s\n" % os.getcwd()) + command = ["vsim", "-c", "-do", eachJob["runsim_filename"]] + output.write(" ".join(command) + '\n') + output.write("* "*20 + '\n') + logger.info("Running modelsim with [%s]" % " ".join(command)) + process = subprocess.Popen(command, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + universal_newlines=True) + for line in process.stdout: + if "Errors" in line: + logger.debug(line.strip()) + sys.stdout.buffer.flush() + output.write(line) + process.wait() + if process.returncode: + raise subprocess.CalledProcessError(0, " ".join(command)) + eachJob["status"] = True + except: + logger.exception("Failed to execute openfpga flow - " + + eachJob["name"]) + if not args.continue_on_fail: + os._exit(1) + eachJob["endtime"] = time.time() + timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) + timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \ + else str(timediff) + logger.info("%s Finished with returncode %d, Time Taken %s " % + (thread_name, process.returncode, timestr)) + eachJob["finished"] = True + no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list]) + logger.info("***** %d runs pending *****" % (no_of_finished_job)) if __name__ == "__main__": + if args.debug: + logger.info("Setting loggger in debug mode") + logger.setLevel(logging.DEBUG) main() From 00ec36c1af79aea1f436082d4a0f36f6570fbd14 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 16 Nov 2019 13:18:13 -0700 Subject: [PATCH 473/482] Added Modelsim error check in log --- openfpga_flow/scripts/run_modelsim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py index cfbd76270..173ff8494 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_modelsim.py @@ -241,7 +241,7 @@ def run_modelsim_thread(s, eachJob, job_list): universal_newlines=True) for line in process.stdout: if "Errors" in line: - logger.debug(line.strip()) + logger.info(line.strip()) sys.stdout.buffer.flush() output.write(line) process.wait() From cb1c7a8030bf8d42c38f156eba0203ae6d5f63be Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 16 Nov 2019 13:19:00 -0700 Subject: [PATCH 474/482] Added OpenFPGA bash function utility --- openfpga.sh | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100755 openfpga.sh diff --git a/openfpga.sh b/openfpga.sh new file mode 100755 index 000000000..fdf591a7c --- /dev/null +++ b/openfpga.sh @@ -0,0 +1,56 @@ +#!/bin/bash +#title : openfpga.sh +#description : This script provides shortcut commands +# for several simple operations in OpenFPGA project +#author : Ganesh Gore +#============================================================================== + +export OPENFPGA_PATH="$(pwd)" +export OPENFPGA_TASK_PATH="$(pwd)/openfpga_flow/tasks" + +# This function checks the path and +# raises warning if the command is not executing +# inside current OpendFPGA folder +check_execution_path (){ + if [[ $1 != *"${OPENFPGA_PATH}"* ]]; then + echo -e "\e[33mCommand is not executed from configured OPNEFPGA directory\e[0m" + fi +} + +# lists all the configure task in task directory +list-tasks () { + check_execution_path "$(pwd)" + ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{printf("%-4s | %s %-3s | ", $5, $6, $7) ;system("basename " $9)}' +} + +# Switch directory to root of OpenFPGA +goto-root () { + cd $OPENFPGA_PATH +} + +# Changes directory to task directory [goto_task ] +goto-task () { + if [ -z $1 ]; then + echo "requires task name goto_task " + return + fi + goto_path=$OPENFPGA_TASK_PATH/$1 + run_num="latest" + if [ ! -d $goto_path ]; then echo "Task directory not found"; return; fi + if [[ $2 == '^[0-9]+$' ]] ; then + echo "Second argumetn provided" + if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)" else run_num="latest" fi + if [ ! -d "$goto_path/$run_num" ]; then run_num="latest" fi + fi + if [ ! -d $goto_path/$run_num ]; then + echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m"; + else + cd $goto_path/$run_num + fi +} + +# Clears enviroment variables and fucntions +unset_openfpga (){ + unset -v OPENFPGA_PATH + unset -f list-tasks goto-task goto-root >/dev/null 2>&1 +} \ No newline at end of file From bfb03af2c811f4a9411d9ca288a1c4a0030a1ea2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 16 Nov 2019 15:52:32 -0700 Subject: [PATCH 475/482] Added run-task and run-flow functions --- openfpga.sh | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/openfpga.sh b/openfpga.sh index fdf591a7c..e44b22f82 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -6,7 +6,9 @@ #============================================================================== export OPENFPGA_PATH="$(pwd)" +export OPENFPGA_SCRIPT_PATH="$(pwd)/openfpga_flow/scripts" export OPENFPGA_TASK_PATH="$(pwd)/openfpga_flow/tasks" +if [ -z $PYTHON_EXEC ]; then export PYTHON_EXEC="python3"; fi # This function checks the path and # raises warning if the command is not executing @@ -17,6 +19,14 @@ check_execution_path (){ fi } +run-task () { + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" +} + +run-flow () { + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_flow.py "$@" +} + # lists all the configure task in task directory list-tasks () { check_execution_path "$(pwd)" @@ -35,22 +45,30 @@ goto-task () { return fi goto_path=$OPENFPGA_TASK_PATH/$1 - run_num="latest" + run_num="" if [ ! -d $goto_path ]; then echo "Task directory not found"; return; fi - if [[ $2 == '^[0-9]+$' ]] ; then - echo "Second argumetn provided" - if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)" else run_num="latest" fi - if [ ! -d "$goto_path/$run_num" ]; then run_num="latest" fi + if [[ "$2" =~ '^[0-9]+$' ]] ; then + if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)"; else run_num="latest"; fi + if [ ! -d "$goto_path/$run_num" ]; then run_num="latest"; fi fi if [ ! -d $goto_path/$run_num ]; then - echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m"; + echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m" else + echo "Switching current dirctory to" $goto_path/$run_num cd $goto_path/$run_num fi } # Clears enviroment variables and fucntions -unset_openfpga (){ +unset-openfpga (){ unset -v OPENFPGA_PATH - unset -f list-tasks goto-task goto-root >/dev/null 2>&1 -} \ No newline at end of file + unset -f list-tasks run-task run-flow goto-task goto-root >/dev/null 2>&1 +} + +# Allow autocompletion of task +if [[ $(ps -p $$ -oargs=) == *"zsh"* ]]; then + autoload -U +X bashcompinit; bashcompinit; +fi +TaskList=$(ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{system("basename " $9)}' | awk '{printf("%s ",$1)}') +complete -W "${TaskList}" goto-task +complete -W "${TaskList}" run-task \ No newline at end of file From a13f406918f315cf5ba4a0390256d34930c98cc8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Nov 2019 18:00:55 -0700 Subject: [PATCH 476/482] tweaking mcnc_big20 task run for modelsim --- .../tasks/mcnc_big20/config/task.conf | 42 ++++++++++--------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index 05961d06b..58ed4c714 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -21,31 +21,31 @@ arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_til [BENCHMARKS] # Pass -#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif # Pass, but port does not match, i_15_ is dangling -#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif # Pass -#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif # To be tested -#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif -#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif -#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif -#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif -#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif -#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif -#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif -#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif -#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif -#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif +bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif +bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif +bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif +bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif +bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif +bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif # Pass -#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif -# Multi-mode support fails to repack +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif +# Multi-mode support fails to repack, skip this now #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif -#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif -#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif -#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif -#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif +bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif +bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif +bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif +bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif [SYNTHESIS_PARAM] # Benchmark alu4 @@ -146,7 +146,7 @@ bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tsen [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= +#vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_include_timing= vpr_fpga_verilog_include_signal_init= @@ -158,5 +158,7 @@ vpr_fpga_verilog_print_user_defined_template= #vpr_fpga_verilog_print_sdc_analysis= vpr_fpga_verilog_explicit_mapping= vpr_fpga_x2p_compact_routing_hierarchy= +# If you wish to run Modelsim verification in batch, turn on the ini file outputting +vpr_fpga_verilog_print_simulation_ini= #end_flow_with_test= From 6bb11918dce056f5679a831f148b403bcac3cc4b Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 16 Nov 2019 19:10:04 -0700 Subject: [PATCH 477/482] Updated modelsim and collected result --- openfpga.sh | 7 ++- openfpga_flow/scripts/run_fpga_flow.py | 2 +- openfpga_flow/scripts/run_fpga_task.py | 2 +- openfpga_flow/scripts/run_modelsim.py | 83 +++++++++++++++++--------- 4 files changed, 63 insertions(+), 31 deletions(-) diff --git a/openfpga.sh b/openfpga.sh index e44b22f82..0ef6ec876 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -23,6 +23,10 @@ run-task () { $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" } +run-modelsim () { + $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_modelsim.py "$@" +} + run-flow () { $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_flow.py "$@" } @@ -71,4 +75,5 @@ if [[ $(ps -p $$ -oargs=) == *"zsh"* ]]; then fi TaskList=$(ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{system("basename " $9)}' | awk '{printf("%s ",$1)}') complete -W "${TaskList}" goto-task -complete -W "${TaskList}" run-task \ No newline at end of file +complete -W "${TaskList}" run-task +complete -W "${TaskList}" run-modelsim \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 04634071f..f02877917 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -4,7 +4,7 @@ # OpensFPGA project. # Args : python3 run_fpga_flow.py --help # Author : Ganesh Gore -# Email : ganeshgore@utah.edu +# Email : ganesh.gore@utah.edu # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = import os diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 061ef1248..bcb4b6a44 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -5,7 +5,7 @@ # Combination of architecture, benchmark and script paramters # Args : python3 run_fpga_task.py --help # Author : Ganesh Gore -# Email : ganeshgore@utah.edu +# Email : ganesh.gore@utah.edu # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = import os diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py index 173ff8494..077b84e61 100644 --- a/openfpga_flow/scripts/run_modelsim.py +++ b/openfpga_flow/scripts/run_modelsim.py @@ -2,6 +2,7 @@ from string import Template import sys import os import re +import csv import glob import time import threading @@ -37,8 +38,6 @@ parser.add_argument('--modelsim_runsim_tmpl', type=str, help="Modelsim runsim template file") parser.add_argument('--run_sim', action="store_true", help="Execute generated script in formality") -parser.add_argument('--modelsim_proj_dir', - help="Provide modelsim project directory") parser.add_argument('--modelsim_proj_name', help="Provide modelsim project name") parser.add_argument('--modelsim_ini', type=str, @@ -104,6 +103,8 @@ def main(): # = = = = = = = Create a current script log file handler = = = = logfile_path = os.path.join(gc["task_dir"], taskname, task_run, "modelsim_run.log") + resultfile_path = os.path.join(gc["task_dir"], + taskname, task_run, "modelsim_result.csv") logfilefh = logging.FileHandler(logfile_path, "w") logfilefh.setFormatter(logging.Formatter(FILE_LOG_FORMAT)) logger.addHandler(logfilefh) @@ -127,7 +128,8 @@ def main(): if os.path.isfile(INIfile): task_ini_files.append(INIfile) logger.info(f"Found {len(task_ini_files)} INI files") - create_tcl_script(task_ini_files) + results = create_tcl_script(task_ini_files) + collect_result(resultfile_path, results) def clean_up_and_exit(msg): @@ -148,56 +150,56 @@ def create_tcl_script(files): config = config["SIMULATION_DECK"] # Resolve project Modelsim project path - if not args.modelsim_proj_dir: - args.modelsim_run_dir = os.path.dirname(os.path.abspath(eachFile)) - args.modelsim_proj_dir = os.path.join( - args.modelsim_run_dir, "MMSIM2") - logger.info(f"Modelsim project dir not provide " + - f"using default {args.modelsim_proj_dir} directory") - if not args.skip_prompt: - input("Press Enter to continue, Ctrl+C to abort") - args.modelsim_proj_dir = os.path.abspath(args.modelsim_proj_dir) - config["MODELSIM_PROJ_DIR"] = args.modelsim_proj_dir - if not os.path.exists(args.modelsim_proj_dir): - os.makedirs(args.modelsim_proj_dir) + args.modelsim_run_dir = os.path.dirname(os.path.abspath(eachFile)) + modelsim_proj_dir = os.path.join( + args.modelsim_run_dir, "MMSIM2") + logger.info(f"Modelsim project dir not provide " + + f"using default {modelsim_proj_dir} directory") + + modelsim_proj_dir = os.path.abspath(modelsim_proj_dir) + config["MODELSIM_PROJ_DIR"] = modelsim_proj_dir + if not os.path.exists(modelsim_proj_dir): + os.makedirs(modelsim_proj_dir) # Resolve Modelsim Project name - if not args.modelsim_proj_name: - args.modelsim_proj_name = config["BENCHMARK"] + "_MMSIM" - logger.info(f"Modelsim project name not provide " + - f"using default {args.modelsim_proj_name} directory") + args.modelsim_proj_name = config["BENCHMARK"] + "_MMSIM" + logger.info(f"Modelsim project name not provide " + + f"using default {args.modelsim_proj_name} directory") - if not args.skip_prompt: - input("Press Enter to continue, Ctrl+C to abort") config["MODELSIM_PROJ_NAME"] = args.modelsim_proj_name config["MODELSIM_INI"] = args.modelsim_ini # Modify the variables in config file here config["TOP_TB"] = os.path.splitext(config["TOP_TB"])[0] - # pass # Write final template file # Write runsim file tmpl = Template(open(args.modelsim_runsim_tmpl, encoding='utf-8').read()) - runsim_filename = os.path.join(args.modelsim_proj_dir, + runsim_filename = os.path.join(modelsim_proj_dir, "%s_runsim.tcl" % config['BENCHMARK']) logger.info(f"Creating tcl script at : {runsim_filename}") with open(runsim_filename, 'w', encoding='utf-8') as tclout: tclout.write(tmpl.substitute(config)) # Write proc file - proc_filename = os.path.join(args.modelsim_proj_dir, + proc_filename = os.path.join(modelsim_proj_dir, "%s_autocheck_proc.tcl" % config['BENCHMARK']) logger.info(f"Creating tcl script at : {proc_filename}") with open(proc_filename, 'w', encoding='utf-8') as tclout: tclout.write(open(args.modelsim_proc_tmpl, encoding='utf-8').read()) runsim_files.append({ + "ini_file": eachFile, "modelsim_run_dir": args.modelsim_run_dir, "runsim_filename": runsim_filename, - "status" :False, - "finished" : True + "run_complete" :False, + "status": False, + "finished" : True, + "starttime" : 0, + "endtime" : 0, + "Errors": 0, + "Warnings" : 0 }) # Execute modelsim if args.run_sim: @@ -212,7 +214,7 @@ def create_tcl_script(files): thread_list.append(t) for eachthread in thread_list: eachthread.join() - exit() + return runsim_files else: logger.info("Created runsim and proc files") logger.info(f"runsim_filename {runsim_filename}") @@ -226,8 +228,12 @@ def run_modelsim_thread(s, eachJob, job_list): with s: thread_name = threading.currentThread().getName() eachJob["starttime"] = time.time() + eachJob["Errors"] = 0 + eachJob["Warnings"]= 0 try: logfile = "%s_modelsim.log" % thread_name + eachJob["logfile"] = "" + \ + os.path.relpath(logfile, gc["task_dir"]) with open(logfile, 'w+') as output: output.write("* "*20 + '\n') output.write("RunDirectory : %s\n" % os.getcwd()) @@ -242,12 +248,17 @@ def run_modelsim_thread(s, eachJob, job_list): for line in process.stdout: if "Errors" in line: logger.info(line.strip()) + e,w = re.match("# .*: ([0-9].*), .*: ([0-9].*)", line).groups() + eachJob["Errors"] += int(e) + eachJob["Warnings"] += int(w) sys.stdout.buffer.flush() output.write(line) process.wait() if process.returncode: raise subprocess.CalledProcessError(0, " ".join(command)) - eachJob["status"] = True + eachJob["run_complete"] = True + if not eachJob["Errors"]: + eachJob["status"] = True except: logger.exception("Failed to execute openfpga flow - " + eachJob["name"]) @@ -257,12 +268,28 @@ def run_modelsim_thread(s, eachJob, job_list): timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"])) timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \ else str(timediff) + eachJob["exectime"] = timestr logger.info("%s Finished with returncode %d, Time Taken %s " % (thread_name, process.returncode, timestr)) eachJob["finished"] = True no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list]) logger.info("***** %d runs pending *****" % (no_of_finished_job)) +def collect_result(result_file, result_obj): + colnames = ["status", "Errors", "Warnings", "run_complete", "exectime", "finished", "logfile"] + if len(result_obj): + with open(result_file, 'w', newline='') as csvfile: + writer = csv.DictWriter( + csvfile, extrasaction='ignore', fieldnames=colnames) + writer.writeheader() + for eachResult in result_obj: + writer.writerow(eachResult) + logger.info("= = = ="*10) + passed_jobs = [ each["status"] for each in result_obj ] + logger.info(f"Passed Jobs %d/%d", len(passed_jobs), len(result_obj)) + logger.info(f"Result file stored at {result_file}") + logger.info("= = = ="*10) + if __name__ == "__main__": if args.debug: logger.info("Setting loggger in debug mode") From 96733f9ea87c30494cd3ccb1dcb00268764dd00b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Nov 2019 22:34:03 -0700 Subject: [PATCH 478/482] add minor comments in task file for modelsim regression tests --- openfpga_flow/tasks/mcnc_big20/config/task.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index 58ed4c714..da190286e 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -160,5 +160,6 @@ vpr_fpga_verilog_explicit_mapping= vpr_fpga_x2p_compact_routing_hierarchy= # If you wish to run Modelsim verification in batch, turn on the ini file outputting vpr_fpga_verilog_print_simulation_ini= +# If you wish to run Modelsim verification in batch, turn off running iVerilog at the end of the flow #end_flow_with_test= From 8cc72536d11a07240320ad55d9a5bb9e4d0ba19a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 22 Nov 2019 15:54:14 -0700 Subject: [PATCH 479/482] minor bug fixing --- vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index bf70df367..e6f49a1c0 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -208,8 +208,8 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& num_ports_to_check, CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], - ports.size()); + ports.size(), + CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)]); num_err++; } for (const auto& port : ports) { From 4d62dc1c3e69c964db2760df486a1741ccd40e42 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 27 Nov 2019 14:40:39 -0700 Subject: [PATCH 480/482] Upgrade to yosys-0.9 --- yosys/.clang-format | 13 + yosys/.dockerignore | 13 + yosys/.editorconfig | 7 + yosys/.github/issue_template.md | 24 + yosys/.gitignore | 13 + yosys/.travis.yml | 168 ++++- yosys/.travis/build-and-test.sh | 51 ++ yosys/.travis/common.sh | 15 + yosys/.travis/deploy-after-success.sh | 6 + yosys/.travis/setup.sh | 63 ++ yosys/Brewfile | 1 + yosys/CHANGELOG | 119 +++- yosys/CMakeLists.txt | 103 --- yosys/COPYING | 2 +- yosys/Dockerfile | 33 + yosys/Makefile | 103 ++- yosys/README | 451 ------------- yosys/README.md | 21 +- yosys/abc.rc | 174 ----- yosys/backends/aiger/aiger.cc | 4 +- yosys/backends/blif/blif.cc | 26 +- yosys/backends/btor/btor.cc | 38 +- yosys/backends/ilang/ilang_backend.cc | 6 + yosys/backends/json/json.cc | 9 + yosys/backends/protobuf/protobuf.cc | 1 + yosys/backends/smt2/smtio.py | 7 +- yosys/backends/verilog/verilog_backend.cc | 14 +- yosys/frontends/aiger/aigerparse.cc | 607 +++++++++--------- yosys/frontends/aiger/aigerparse.h | 1 + yosys/frontends/ast/ast.cc | 28 +- yosys/frontends/ast/ast.h | 13 +- yosys/frontends/ast/genrtlil.cc | 68 +- yosys/frontends/ilang/ilang_parser.y | 13 +- yosys/frontends/json/jsonparse.cc | 24 + yosys/frontends/verific/verific.cc | 11 + yosys/frontends/verilog/const2ast.cc | 28 +- yosys/frontends/verilog/verilog_frontend.cc | 10 +- yosys/frontends/verilog/verilog_lexer.l | 11 +- yosys/frontends/verilog/verilog_parser.y | 189 +++--- yosys/kernel/log.cc | 22 +- yosys/kernel/log.h | 1 + yosys/kernel/register.cc | 1 + yosys/kernel/rtlil.cc | 29 +- yosys/kernel/rtlil.h | 3 +- yosys/kernel/yosys.cc | 6 +- yosys/kernel/yosys.h | 4 + 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--- /dev/null +++ b/yosys/.clang-format @@ -0,0 +1,13 @@ +# Default Linux style +BasedOnStyle: LLVM +IndentWidth: 8 +UseTab: Always +BreakBeforeBraces: Linux +AllowShortIfStatementsOnASingleLine: false +IndentCaseLabels: false + +# From CodingReadme +TabWidth: 8 +ContinuationIndentWidth: 2 +ColumnLimit: 150 +# BreakBeforeBraces: Linux diff --git a/yosys/.dockerignore b/yosys/.dockerignore new file mode 100644 index 000000000..9910e9954 --- /dev/null +++ b/yosys/.dockerignore @@ -0,0 +1,13 @@ +.editorconfig +.gitignore +.gitmodules +.github +.git +Dockerfile +README.md +manual +CodingReadme +CodeOfConduct +.travis +.travis.yml + diff --git a/yosys/.editorconfig b/yosys/.editorconfig new file mode 100644 index 000000000..4d6f5ef7a --- /dev/null +++ b/yosys/.editorconfig @@ -0,0 +1,7 @@ +root = true + +[*] +indent_style = tab +indent_size = tab +trim_trailing_whitespace = true +insert_final_newline = true diff --git a/yosys/.github/issue_template.md b/yosys/.github/issue_template.md new file mode 100644 index 000000000..5a0723c3e --- /dev/null +++ b/yosys/.github/issue_template.md @@ -0,0 +1,24 @@ +## Steps to reproduce the issue + +*Provide instructions for reproducing the issue. Make sure to include +all necessary source files. (You can simply drag&drop a .zip file into +the issue editor.)* + +Also, make sure that the issue is actually reproducable in current git +master of Yosys. + +See https://stackoverflow.com/help/mcve for some information on how to +create a Minimal, Complete, and Verifiable example (MCVE). + +Please do not waste our time with issues that lack sufficient information +to reproduce the issue easily. We will simply close those issues. + +Contact https://www.symbioticeda.com/ if you need commercial support for Yosys. + +## Expected behavior + +*Please describe the behavior you would have expected from the tool.* + +## Actual behavior + +*Please describe how the behavior you see differs from the expected behavior.* diff --git a/yosys/.gitignore b/yosys/.gitignore index 93e28cd6c..76f53cd06 100644 --- a/yosys/.gitignore +++ b/yosys/.gitignore @@ -1,6 +1,10 @@ *.o *.d .*.swp +*.gch +*.gcda +*.gcno +__pycache__ /.cproject /.project /.settings @@ -9,6 +13,8 @@ /qtcreator.config /qtcreator.creator /qtcreator.creator.user +/coverage.info +/coverage_html /Makefile.conf /abc /viz.js @@ -19,11 +25,18 @@ /yosys-abc.exe /yosys-config /yosys-smtbmc +/yosys-smtbmc.exe +/yosys-smtbmc-script.py /yosys-filterlib /yosys-filterlib.exe +/kernel/*.pyh +/kernel/python_wrappers.cc /kernel/version_*.cc /share /yosys-win32-mxebin-* /yosys-win32-vcxsrc-* /yosysjs-* /libyosys.so +/tests/unit/bintest/ +/tests/unit/objtest/ +/tests/ystests diff --git a/yosys/.travis.yml b/yosys/.travis.yml index 9f0cc06e7..c253b2ff7 100644 --- a/yosys/.travis.yml +++ b/yosys/.travis.yml @@ -1,34 +1,140 @@ sudo: false -script: make && make test language: cpp -addons: - apt: - sources: - - ubuntu-toolchain-r-test - packages: - - gperf - - build-essential - - clang - - bison - - flex - - libreadline-dev - - gawk - - tcl-dev - - libffi-dev - - git - - mercurial - - graphviz - - xdot - - pkg-config - - python - - g++-4.8 + +cache: + ccache: true + directories: + - ~/.local-bin + + +env: + global: + - MAKEFLAGS="-j 2" + +matrix: + include: + # Latest gcc-4.8, earliest version supported by Travis + - os: linux + addons: + apt: + packages: + - g++-4.8 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - graphviz + - xdot + - pkg-config + - python + - python3 + - libboost-system-dev + - libboost-python-dev + - libboost-filesystem-dev + env: + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" + + # Latest gcc supported on Travis Linux + - os: linux + addons: + apt: + sources: + - ubuntu-toolchain-r-test + packages: + - g++-9 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - graphviz + - xdot + - pkg-config + - python + - python3 + - libboost-system-dev + - libboost-python-dev + - libboost-filesystem-dev + env: + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9" + + # Clang which ships on Trusty Linux + - os: linux + addons: + apt: + sources: + - ubuntu-toolchain-r-test + - llvm-toolchain-precise-3.8 + packages: + - clang-3.8 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - graphviz + - xdot + - pkg-config + - python + - python3 + - libboost-system-dev + - libboost-python-dev + - libboost-filesystem-dev + env: + - MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8" + + # Latest clang supported by Travis Linux + - os: linux + addons: + apt: + sources: + - llvm-toolchain-xenial-8 + packages: + - clang-8 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - graphviz + - xdot + - pkg-config + - python + - python3 + - libboost-system-dev + - libboost-python-dev + - libboost-filesystem-dev + env: + - MATRIX_EVAL="CONFIG=clang && CC=clang-8 && CXX=clang++-8" + +# # Latest clang on Mac OS X +# - os: osx +# osx_image: xcode9.4 +# env: +# - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++" + before_install: - - if [ "$CXX" = "g++" ]; then export CXX="g++-4.8" CC="gcc-4.8"; fi - - git clone git://github.com/steveicarus/iverilog.git - - (cd iverilog && autoconf && ./configure --prefix=$HOME/iverilog && make && make install) - - export PATH=$PATH:$HOME/iverilog/bin -compiler: -# - clang - - gcc -os: - - linux + - ./.travis/setup.sh + +script: + - ./.travis/build-and-test.sh + +after_success: + - ./.travis/deploy-after-success.sh diff --git a/yosys/.travis/build-and-test.sh b/yosys/.travis/build-and-test.sh new file mode 100755 index 000000000..b8c35041d --- /dev/null +++ b/yosys/.travis/build-and-test.sh @@ -0,0 +1,51 @@ +#! /bin/bash + +set -e + +source .travis/common.sh + +########################################################################## + +echo +echo 'Configuring...' && echo -en 'travis_fold:start:script.configure\\r' +echo + +if [ "$CONFIG" = "gcc" ]; then + echo "Configuring for gcc." + make config-gcc +elif [ "$CONFIG" = "clang" ]; then + echo "Configuring for clang." + make config-clang +fi + +echo +echo -en 'travis_fold:end:script.configure\\r' +echo + +########################################################################## + +echo +echo 'Building...' && echo -en 'travis_fold:start:script.build\\r' +echo + +make + +echo +echo -en 'travis_fold:end:script.build\\r' +echo + +########################################################################## + +./yosys tests/simple/fiedler-cooley.v + +echo +echo 'Testing...' && echo -en 'travis_fold:start:script.test\\r' +echo + +make test + +echo +echo -en 'travis_fold:end:script.test\\r' +echo + +########################################################################## diff --git a/yosys/.travis/common.sh b/yosys/.travis/common.sh new file mode 100644 index 000000000..8eecc4c09 --- /dev/null +++ b/yosys/.travis/common.sh @@ -0,0 +1,15 @@ +#! /bin/bash + +# Setup the CC / CXX from the matrix config +eval "${MATRIX_EVAL}" + +# Look for location binaries first +export PATH="$HOME/.local-bin/bin:$PATH" + +# OS X specific common setup +if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then + export PATH="/usr/local/opt/ccache/libexec:$PATH" +fi + +# Parallel builds! +MAKEFLAGS="-j 2" diff --git a/yosys/.travis/deploy-after-success.sh b/yosys/.travis/deploy-after-success.sh new file mode 100755 index 000000000..d64e95244 --- /dev/null +++ b/yosys/.travis/deploy-after-success.sh @@ -0,0 +1,6 @@ +#! /bin/bash + +set -x +set -e + +# FIXME: Upload the build results somewhere... diff --git a/yosys/.travis/setup.sh b/yosys/.travis/setup.sh new file mode 100755 index 000000000..02879b974 --- /dev/null +++ b/yosys/.travis/setup.sh @@ -0,0 +1,63 @@ +#! /bin/bash + +set -e + +source .travis/common.sh + +########################################################################## + +# Output status information. +( + set +e + set -x + git status + git branch -v + git log -n 5 --graph + git log --format=oneline -n 20 --graph +) +echo +echo -en 'travis_fold:end:before_install.git\\r' +echo + +########################################################################## + +# Mac OS X specific setup. +if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then + ( + echo + echo 'Setting up brew...' && echo -en 'travis_fold:start:before_install.brew\\r' + echo + brew update + brew tap Homebrew/bundle + brew bundle + brew install ccache + echo + echo -en 'travis_fold:end:before_install.brew\\r' + echo + ) +fi + +########################################################################## + +# Install iverilog +( + if [ ! -e ~/.local-bin/bin/iverilog ]; then + echo + echo 'Building iverilog...' && echo -en 'travis_fold:start:before_install.iverilog\\r' + echo + mkdir -p ~/.local-src + mkdir -p ~/.local-bin + cd ~/.local-src + git clone git://github.com/steveicarus/iverilog.git + cd iverilog + autoconf + CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin + make + make install + echo + echo -en 'travis_fold:end:before_install.iverilog\\r' + echo + fi +) + +########################################################################## diff --git a/yosys/Brewfile b/yosys/Brewfile index 0c58ce161..4ffe50e86 100644 --- a/yosys/Brewfile +++ b/yosys/Brewfile @@ -6,3 +6,4 @@ brew "git" brew "graphviz" brew "pkg-config" brew "python3" +brew "tcl-tk" diff --git a/yosys/CHANGELOG b/yosys/CHANGELOG index 36b64e111..afbcffa26 100644 --- a/yosys/CHANGELOG +++ b/yosys/CHANGELOG @@ -3,21 +3,124 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.8 .. Yosys 0.8-dev +Yosys 0.8 .. Yosys 0.9 -------------------------- * Various - - Added $changed support to read_verilog + - Many bugfixes and small improvements + - Added support for SystemVerilog interfaces and modports - Added "write_edif -attrprop" - - Added "ice40_unlut" pass - Added "opt_lut" pass - - Added "synth_ice40 -relut" - - Added "synth_ice40 -noabc" - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass - - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - Added "flowmap" LUT mapping pass + - Added "rename -wire" to rename cells based on the wires they drive + - Added "bugpoint" for creating minimised testcases + - Added "write_edif -gndvccy" + - "write_verilog" to escape Verilog keywords + - Fixed sign handling of real constants + - "write_verilog" to write initial statement for initial flop state + - Added pmgen pattern matcher generator + - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_ + - Added "setundef -params" to replace undefined cell parameters + - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines + - Fixed handling of defparam when default_nettype is none + - Fixed "wreduce" flipflop handling + - Fixed FIRRTL to Verilog process instance subfield assignment + - Added "write_verilog -siminit" + - Several fixes and improvements for mem2reg memories + - Fixed handling of task output ports in clocked always blocks + - Improved handling of and-with-1 and or-with-0 in "opt_expr" + - Added "read_aiger" frontend + - Added "mutate" pass + - Added "hdlname" attribute + - Added "rename -output" + - Added "read_ilang -lib" + - Improved "proc" full_case detection and handling + - Added "whitebox" and "lib_whitebox" attributes + - Added "read_verilog -nowb", "flatten -wb" and "wbflip" + - Added Python bindings and support for Python plug-ins + - Added "pmux2shiftx" + - Added log_debug framework for reduced default verbosity + - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires + - Added "peepopt" peephole optimisation pass using pmgen + - Added approximate support for SystemVerilog "var" keyword + - Added parsing of "specify" blocks into $specrule and $specify[23] + - Added support for attributes on parameters and localparams + - Added support for parsing attributes on port connections + - Added "wreduce -keepdc" + - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff" + - Added Verilog wand/wor wire type support + - Added support for elaboration system tasks + - Added "muxcover -mux{4,8,16}=" + - Added "muxcover -dmux=" + - Added "muxcover -nopartial" + - Added "muxpack" pass + - Added "pmux2shiftx -norange" + - Added support for "~" in filename parsing + - Added "read_verilog -pwires" feature to turn parameters into wires + - Fixed sign extension of unsized constants with 'bx and 'bz MSB + - Fixed genvar to be a signed type + - Added support for attributes on case rules + - Added "upto" and "offset" to JSON frontend and backend + - Several liberty file parser improvements + - Fixed handling of more complex BRAM patterns + - Add "write_aiger -I -O -B" + * Formal Verification + - Added $changed support to read_verilog + - Added "read_verilog -noassert -noassume -assert-assumes" + - Added btor ops for $mul, $div, $mod and $concat + - Added yosys-smtbmc support for btor witnesses + - Added "supercover" pass + - Fixed $global_clock handling vs autowire + - Added $dffsr support to "async2sync" + - Added "fmcombine" pass + - Added memory init support in "write_btor" + - Added "cutpoint" pass + - Changed "ne" to "neq" in btor2 output + - Added support for SVA "final" keyword + - Added "fmcombine -initeq -anyeq" + - Added timescale and generated-by header to yosys-smtbmc vcd output + - Improved BTOR2 handling of undriven wires + + * Verific support + - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports + - Improved support for asymmetric memories + - Added "verific -chparam" + - Fixed "verific -extnets" for more complex situations + - Added "read -verific" and "read -noverific" + - Added "hierarchy -chparam" + + * New back-ends + - Added initial Anlogic support + - Added initial SmartFusion2 and IGLOO2 support + + * ECP5 support + - Added "synth_ecp5 -nowidelut" + - Added BRAM inference support to "synth_ecp5" + - Added support for transforming Diamond IO and flipflop primitives + + * iCE40 support + - Added "ice40_unlut" pass + - Added "synth_ice40 -relut" + - Added "synth_ice40 -noabc" + - Added "synth_ice40 -dffe_min_ce_use" + - Added DSP inference support using pmgen + - Added support for initialising BRAM primitives from a file + - Added iCE40 Ultra RGB LED driver cells + + * Xilinx support + - Use "write_edif -pvector bra" for Xilinx EDIF files + - Fixes for VPR place and route support with "synth_xilinx" + - Added more cell simulation models + - Added "synth_xilinx -family" + - Added "stat -tech xilinx" to estimate logic cell usage + - Added "synth_xilinx -nocarry" + - Added "synth_xilinx -nowidelut" + - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) + - Added support for mapping RAM32X1D Yosys 0.7 .. Yosys 0.8 ---------------------- @@ -30,7 +133,7 @@ Yosys 0.7 .. Yosys 0.8 - Added "write_verilog -decimal" - Added "scc -set_attr" - Added "verilog_defines" command - - Remeber defines from one read_verilog to next + - Remember defines from one read_verilog to next - Added support for hierarchical defparam - Added FIRRTL back-end - Improved ABC default scripts @@ -39,7 +142,7 @@ Yosys 0.7 .. Yosys 0.8 - Added Verilog $rtoi and $itor support - Added "check -initdrv" - Added "read_blif -wideports" - - Added support for systemVerilog "++" and "--" operators + - Added support for SystemVerilog "++" and "--" operators - Added support for SystemVerilog unique, unique0, and priority case - Added "write_edif" options for edif "flavors" - Added support for resetall compiler directive diff --git a/yosys/CMakeLists.txt b/yosys/CMakeLists.txt deleted file mode 100644 index 9ec574964..000000000 --- a/yosys/CMakeLists.txt +++ /dev/null @@ -1,103 +0,0 @@ -cmake_minimum_required(VERSION 3.3.0) - -include(CMakeParseArguments) - -project(yosys) - -# Version number -set(YOSYS_VERSION_MAJOR 0.7) -set(YOSYS_VERSION_MINOR 0) -set(YOSYS_VERSION_PATCH 0) - -# Options to enable/disable dependencies -option(YOSYS_ENABLE_TCL, "Enable TCL parser integrated in yosys" ON) -option(YOSYS_ENABLE_ABC, "Enable ABC library integrated in yosys" ON) -option(YOSYS_ENABLE_PLUGINS, "Enable plug-in in yosys" ON) -option(YOSYS_ENABLE_READLINE, "Enable readline library in yosys" ON) -option(YOSYS_ENABLE_VERIFIC, "Enable verification library in yosys" OFF) -option(YOSYS_ENABLE_COVER, "Enable coverage test in yosys" ON) -option(YOSYS_ENABLE_LIBYOSYS, "Enable static library compiled yosys" OFF) -option(YOSYS_ENABLE_GPROF, "Enable profiling in compiled yosys" OFF) -option(YOSYS_ENABLE_NDEBUG, "Enable non-debugging feature in compiled yosys" OFF) - -# -## Search and link dependent packages -## We need readline to compile -if (YOSYS_ENABLE_READLINE) - find_package(Readline REQUIRED) -endif() -# -######################### -## # -## Compiler Flags Setup # -## # -######################### -# -## Compiler flag configuration checks -include(CheckCCompilerFlag) -include(CheckCXXCompilerFlag) -# -## Required Compiler Standard -#set(CMAKE_CXX_STANDARD 11) # need at least c+11 standard -#set(CMAKE_CXX_STANDARD_REQUIRED ON) -# -## Set warning flags -#set(WARN_FLAGS_TO_CHECK "") # checklist of warning flags -#set(WARN_FLAGS "") # actual warning flags to be added during compilation -## Add warning flags depending on options -#if (YOSYS_ENABLE_NDEBUG) -# set(WARN_FLAGS_TO_CHECK, ${WARN_FLAGS_TO_CHECK}, "-O3") -#endif() -# -# -##Collect the source files -#file(GLOB_RECURSE EXEC_YOSYS kernel/yosys.cc) -#file(GLOB_RECURSE LIB_SOURCES kernel/*.cc) -#file(GLOB_RECURSE LIB_HEADERS kernel/*.h) -#files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) -# -## Use c++ compiler for c source files -#set_source_files_properties(${LIB_SOURCES} PROPERTIES LANGUAGE CXX) -#set_source_files_properties(${EXEC_SOURCES} PROPERTIES LANGUAGE CXX) -#set_source_files_properties(${EXEC_SOURCES_SHELL} PROPERTIES LANGUAGE CXX) -# -##Build the library -#add_library(libyosys STATIC -# ${LIB_HEADERS} -# ${LIB_SOURCES}) -# -## add header files to be included -#target_include_directories(libyosys PUBLIC ${LIB_INCLUDE_DIRS}) -#set_target_properties(libyosys PROPERTIES PREFIX "") #Avoid extra 'lib' prefix#Create the executable -# -##Specify link-time dependancies -#target_link_libraries(libyosys -# readline) -# -## Build targets -## 1. yosys -#add_executable(yosys ${EXEC_SOURCES}) -#target_link_libraries(vpr -# libyosys) -# 2. yosys-config - -# run makefile provided, we pass-on the options to the local make file -add_custom_target( - yosys ALL - COMMAND - $(MAKE) - #CC=${CMAKE_C_COMPILER} - #CXX=${CMAKE_CXX_COMPILER} - #LD=${CMAKE_CXX_COMPILER} - #ENABLE_TCL=${YOSYS_ENABLE_TCL} - #ENABLE_ABC=${YOSYS_ENABLE_ABC} - #ENABLE_PLUGINS=${YOSYS_ENABLE_PLUGINS} - #ENABLE_READLINE=${YOSYS_ENABLE_READLINE} - #ENABLE_VERIFIC=${YOSYS_ENABLE_VERIFIC} - #ENABLE_COVER=${YOSYS_ENABLE_COVER} - #ENABLE_LIBYOSYS=${YOSYS_ENABLE_LIBYOSYS} - #ENABLE_GPROF=${YOSYS_ENABLE_GPROF} - #ENABLE_NDEBUG=${YOSYS_ENABLE_NDEBUG} - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMENT "Compile Yosys with given Makefile" -) diff --git a/yosys/COPYING b/yosys/COPYING index a121cdfe9..0839088c3 100644 --- a/yosys/COPYING +++ b/yosys/COPYING @@ -1,4 +1,4 @@ -Copyright (C) 2012 - 2018 Clifford Wolf +Copyright (C) 2012 - 2019 Clifford Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above diff --git a/yosys/Dockerfile b/yosys/Dockerfile new file mode 100644 index 000000000..3c7188d82 --- /dev/null +++ b/yosys/Dockerfile @@ -0,0 +1,33 @@ +FROM ubuntu:18.04 as builder +LABEL author="Abdelrahman Hosny " +ENV DEBIAN_FRONTEND=noninteractive +RUN apt-get update && apt-get install -y build-essential \ + clang \ + bison \ + flex \ + libreadline-dev \ + gawk \ + tcl-dev \ + libffi-dev \ + git \ + pkg-config \ + python3 && \ + rm -rf /var/lib/apt/lists +COPY . / +RUN make && \ + make install + +FROM ubuntu:18.04 +ENV DEBIAN_FRONTEND=noninteractive +RUN apt-get update && apt-get install -y libreadline-dev tcl-dev + +COPY --from=builder /yosys /build/yosys +COPY --from=builder /yosys-abc /build/yosys-abc +COPY --from=builder /yosys-config /build/yosys-config +COPY --from=builder /yosys-filterlib /build/yosys-filterlib +COPY --from=builder /yosys-smtbmc /build/yosys-smtbmc + +ENV PATH /build:$PATH +RUN useradd -m yosys +USER yosys +ENTRYPOINT ["yosys"] diff --git a/yosys/Makefile b/yosys/Makefile index bf0f1ca0c..a67315415 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -1,7 +1,8 @@ -# CONFIG := clang -CONFIG := gcc +CONFIG := clang +# CONFIG := gcc # CONFIG := gcc-4.8 +# CONFIG := afl-gcc # CONFIG := emcc # CONFIG := mxe # CONFIG := msys2 @@ -21,12 +22,6 @@ ENABLE_PROTOBUF := 0 # python wrappers ENABLE_PYOSYS := 0 -PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" -PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) -PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"") -PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) -PYTHON_PREFIX := `$(PYTHON_EXECUTABLE)-config --prefix` -PYTHON_DESTDIR := $(PYTHON_PREFIX)/lib/python$(PYTHON_VERSION)/site-packages # other configuration flags ENABLE_GCOV := 0 @@ -51,6 +46,10 @@ OS := $(shell uname -s) PREFIX ?= /usr/local INSTALL_SUDO := +ifneq ($(wildcard Makefile.conf),) +include Makefile.conf +endif + BINDIR := $(PREFIX)/bin LIBDIR := $(PREFIX)/lib DATDIR := $(PREFIX)/share/yosys @@ -90,6 +89,11 @@ PLUGIN_LDFLAGS += -undefined dynamic_lookup # homebrew search paths ifneq ($(shell which brew),) BREW_PREFIX := $(shell brew --prefix)/opt +$(info $$BREW_PREFIX is [${BREW_PREFIX}]) +ifeq ($(ENABLE_PYOSYS),1) +CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost +LDFLAGS += -L$(BREW_PREFIX)/boost/lib +endif CXXFLAGS += -I$(BREW_PREFIX)/readline/include LDFLAGS += -L$(BREW_PREFIX)/readline/lib PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH) @@ -110,7 +114,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; }) +YOSYS_VER := 0.9 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o @@ -139,6 +143,21 @@ $(info $(subst $$--$$,$(newline),$(shell sed 's,^,[Makefile.conf] ,; s,$$,$$--$$ include Makefile.conf endif +ifeq ($(ENABLE_PYOSYS),1) +PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" +PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) +PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"") +PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) +PYTHON_PREFIX := $(shell $(PYTHON_EXECUTABLE)-config --prefix) +PYTHON_DESTDIR := $(PYTHON_PREFIX)/lib/python$(PYTHON_VERSION)/site-packages + +# Reload Makefile.conf to override python specific variables if defined +ifneq ($(wildcard Makefile.conf),) +include Makefile.conf +endif + +endif + ifeq ($(CONFIG),clang) CXX = clang LD = clang++ @@ -186,6 +205,12 @@ LD = gcc-4.8 CXXFLAGS += -std=c++11 -Os ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" +else ifeq ($(CONFIG),afl-gcc) +CXX = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc +LD = AFL_QUIET=1 AFL_HARDEN=1 afl-gcc +CXXFLAGS += -std=c++11 -Os +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" + else ifeq ($(CONFIG),cygwin) CXX = gcc LD = gcc @@ -237,7 +262,8 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc" +# TODO: Try to solve pthread linking issue in more appropriate way +ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" LDFLAGS="-Wl,--allow-multiple-definition" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc" EXE = .exe else ifeq ($(CONFIG),msys2) @@ -273,30 +299,51 @@ endif ifeq ($(ENABLE_PYOSYS),1) #Detect name of boost_python library. Some distros usbe boost_python-py, other boost_python, some only use the major version number, some a concatenation of major and minor version numbers +ifeq ($(OS), Darwin) +BOOST_PYTHON_LIB ?= $(shell \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \ + if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(shell $(PYTHON_EXECUTABLE)-config --ldflags) -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ + echo ""; fi; fi; fi; fi;) +else BOOST_PYTHON_LIB ?= $(shell \ if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_VERSION))"; else \ if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python-py$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_VERSION))"; else \ if echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null `$(PYTHON_EXECUTABLE)-config --libs` -lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION)) - > /dev/null 2>&1; then echo "-lboost_python$(subst .,,$(PYTHON_MAJOR_VERSION))"; else \ echo ""; fi; fi; fi; fi;) +endif ifeq ($(BOOST_PYTHON_LIB),) $(error BOOST_PYTHON_LIB could not be detected. Please define manualy) endif +ifeq ($(OS), Darwin) ifeq ($(PYTHON_MAJOR_VERSION),3) -LDLIBS += `$(PYTHON_EXECUTABLE)-config --libs` $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem -CXXFLAGS += `$(PYTHON_EXECUTABLE)-config --includes` -D WITH_PYTHON +LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --ldflags) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem +CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON else -LDLIBS += `$(PYTHON_EXECUTABLE)-config --libs` $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem -CXXFLAGS += `$(PYTHON_EXECUTABLE)-config --includes` -D WITH_PYTHON +LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --ldflags) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem +CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON +endif +else +ifeq ($(PYTHON_MAJOR_VERSION),3) +LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem +CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON +else +LDLIBS += $(shell $(PYTHON_EXECUTABLE)-config --libs) $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem +CXXFLAGS += $(shell $(PYTHON_EXECUTABLE)-config --includes) -DWITH_PYTHON +endif endif +ifeq ($(ENABLE_PYOSYS),1) PY_WRAPPER_FILE = kernel/python_wrappers OBJS += $(PY_WRAPPER_FILE).o PY_GEN_SCRIPT= py_wrap_generator PY_WRAP_INCLUDES := $(shell python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).print_includes()") endif +endif ifeq ($(ENABLE_READLINE),1) CXXFLAGS += -DYOSYS_ENABLE_READLINE @@ -350,7 +397,7 @@ endif ifeq ($(CONFIG),mxe) CXXFLAGS += -DYOSYS_ENABLE_TCL -LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz +LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz -luserenv else CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL ifeq ($(OS), FreeBSD) @@ -541,7 +588,11 @@ yosys$(EXE): $(OBJS) $(P) $(LD) -o yosys$(EXE) $(LDFLAGS) $(OBJS) $(LDLIBS) libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) +ifeq ($(OS), Darwin) + $(P) $(LD) -o libyosys.so -shared -Wl,-install_name,libyosys.so $(LDFLAGS) $^ $(LDLIBS) +else $(P) $(LD) -o libyosys.so -shared -Wl,-soname,libyosys.so $(LDFLAGS) $^ $(LDLIBS) +endif %.o: %.cc $(Q) mkdir -p $(dir $@) @@ -551,9 +602,11 @@ libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) $(Q) mkdir -p $(dir $@) $(P) cat $< | grep -E -v "#[ ]*(include|error)" | $(LD) -x c++ -o $@ -E -P - +ifeq ($(ENABLE_PYOSYS),1) $(PY_WRAPPER_FILE).cc: misc/$(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES) $(Q) mkdir -p $(dir $@) $(P) python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).gen_wrappers(\"$(PY_WRAPPER_FILE).cc\")" +endif %.o: %.cpp $(Q) mkdir -p $(dir $@) @@ -616,6 +669,12 @@ else SEEDOPT="" endif +ifneq ($(ABCEXTERNAL),) +ABCOPT="-A $(ABCEXTERNAL)" +else +ABCOPT="" +endif + test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/simple && bash run-test.sh $(SEEDOPT) +cd tests/hana && bash run-test.sh $(SEEDOPT) @@ -624,13 +683,14 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/share && bash run-test.sh $(SEEDOPT) +cd tests/fsm && bash run-test.sh $(SEEDOPT) +cd tests/techmap && bash run-test.sh - +cd tests/memories && bash run-test.sh $(SEEDOPT) + +cd tests/memories && bash run-test.sh $(ABCOPT) $(SEEDOPT) +cd tests/bram && bash run-test.sh $(SEEDOPT) +cd tests/various && bash run-test.sh +cd tests/sat && bash run-test.sh +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) +cd tests/opt && bash run-test.sh - +cd tests/aiger && bash run-test.sh + +cd tests/aiger && bash run-test.sh $(ABCOPT) + +cd tests/arch && bash run-test.sh @echo "" @echo " Passed \"make test\"." @echo "" @@ -651,7 +711,7 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS) ystests: $(TARGETS) $(EXTRA_TARGETS) rm -rf tests/ystests - git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests + git clone -b yosys-0.9-rc https://github.com/YosysHQ/yosys-tests.git tests/ystests +$(MAKE) PATH="$$PWD:$$PATH" -C tests/ystests @echo "" @echo " Finished \"make ystests\"." @@ -788,6 +848,9 @@ config-gcc-static: clean config-gcc-4.8: clean echo 'CONFIG := gcc-4.8' > Makefile.conf +config-afl-gcc: clean + echo 'CONFIG := afl-gcc' > Makefile.conf + config-emcc: clean echo 'CONFIG := emcc' > Makefile.conf echo 'ENABLE_TCL := 0' >> Makefile.conf @@ -801,9 +864,11 @@ config-mxe: clean config-msys2: clean echo 'CONFIG := msys2' > Makefile.conf + echo 'ENABLE_PLUGINS := 0' >> Makefile.conf config-msys2-64: clean echo 'CONFIG := msys2-64' > Makefile.conf + echo 'ENABLE_PLUGINS := 0' >> Makefile.conf config-cygwin: clean echo 'CONFIG := cygwin' > Makefile.conf @@ -834,5 +899,5 @@ echo-git-rev: -include techlibs/*/*.d .PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator coverage vcxsrc mxebin -.PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo +.PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-afl-gcc config-gprof config-sudo diff --git a/yosys/README b/yosys/README deleted file mode 100644 index 8e43d4446..000000000 --- a/yosys/README +++ /dev/null @@ -1,451 +0,0 @@ - - /-----------------------------------------------------------------------------\ - | | - | yosys -- Yosys Open SYnthesis Suite | - | | - | Copyright (C) 2012 - 2016 Clifford Wolf | - | | - | Permission to use, copy, modify, and/or distribute this software for any | - | purpose with or without fee is hereby granted, provided that the above | - | copyright notice and this permission notice appear in all copies. | - | | - | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | - | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | - | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | - | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | - | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | - | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | - | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | - | | - \-----------------------------------------------------------------------------/ - - -yosys -- Yosys Open SYnthesis Suite -=================================== - -This is a framework for RTL synthesis tools. It currently has -extensive Verilog-2005 support and provides a basic set of -synthesis algorithms for various application domains. - -Yosys can be adapted to perform any synthesis job by combining -the existing passes (algorithms) using synthesis scripts and -adding additional passes as needed by extending the yosys C++ -code base. - -Yosys is free software licensed under the ISC license (a GPL -compatible license that is similar in terms to the MIT license -or the 2-clause BSD license). - - -Web Site -======== - -More information and documentation can be found on the Yosys web site: - - http://www.clifford.at/yosys/ - - -Getting Started -=============== - -You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is -recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. -TCL, readline and libffi are optional (see ENABLE_* settings in Makefile). -Xdot (graphviz) is used by the "show" command in yosys to display schematics. -For example on Ubuntu Linux 16.04 LTS the following commands will install all -prerequisites for building yosys: - - $ sudo apt-get install build-essential clang bison flex \ - libreadline-dev gawk tcl-dev libffi-dev git mercurial \ - graphviz xdot pkg-config python3 - -There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well -as a source distribution for Visual Studio. Visit the Yosys download page for -more information: - - http://www.clifford.at/yosys/download.html - -To configure the build system to use a specific compiler, use one of - - $ make config-clang - $ make config-gcc - -For other compilers and build configurations it might be -necessary to make some changes to the config section of the -Makefile. - - $ vi Makefile ..or.. - $ vi Makefile.conf - -To build Yosys simply type 'make' in this directory. - - $ make - $ make test - $ sudo make install - -Note that this also downloads, builds and installs ABC (using yosys-abc -as executable name). - -Yosys can be used with the interactive command shell, with -synthesis scripts or with command line arguments. Let's perform -a simple synthesis job using the interactive command shell: - - $ ./yosys - yosys> - -the command "help" can be used to print a list of all available -commands and "help " to print details on the specified command: - - yosys> help help - -reading the design using the Verilog frontend: - - yosys> read_verilog tests/simple/fiedler-cooley.v - -writing the design to the console in yosys's internal format: - - yosys> write_ilang - -elaborate design hierarchy: - - yosys> hierarchy - -convert processes ("always" blocks) to netlist elements and perform -some simple optimizations: - - yosys> proc; opt - -display design netlist using xdot: - - yosys> show - -the same thing using 'gv' as postscript viewer: - - yosys> show -format ps -viewer gv - -translating netlist to gate logic and perform some simple optimizations: - - yosys> techmap; opt - -write design netlist to a new Verilog file: - - yosys> write_verilog synth.v - -a similar synthesis can be performed using yosys command line options only: - - $ ./yosys -o synth.v -p hierarchy -p proc -p opt \ - -p techmap -p opt tests/simple/fiedler-cooley.v - -or using a simple synthesis script: - - $ cat synth.ys - read_verilog tests/simple/fiedler-cooley.v - hierarchy; proc; opt; techmap; opt - write_verilog synth.v - - $ ./yosys synth.ys - -It is also possible to only have the synthesis commands but not the read/write -commands in the synthesis script: - - $ cat synth.ys - hierarchy; proc; opt; techmap; opt - - $ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys - -The following very basic synthesis script should work well with all designs: - - # check design hierarchy - hierarchy - - # translate processes (always blocks) - proc; opt - - # detect and optimize FSM encodings - fsm; opt - - # implement memories (arrays) - memory; opt - - # convert to gate logic - techmap; opt - -If ABC is enabled in the Yosys build configuration and a cell library is given -in the liberty file mycells.lib, the following synthesis script will synthesize -for the given cell library: - - # the high-level stuff - hierarchy; proc; fsm; opt; memory; opt - - # mapping to internal cell library - techmap; opt - - # mapping flip-flops to mycells.lib - dfflibmap -liberty mycells.lib - - # mapping logic to mycells.lib - abc -liberty mycells.lib - - # cleanup - clean - -If you do not have a liberty file but want to test this synthesis script, -you can use the file examples/cmos/cmos_cells.lib from the yosys sources. - -Liberty file downloads for and information about free and open ASIC standard -cell libraries can be found here: - - http://www.vlsitechnology.org/html/libraries.html - http://www.vlsitechnology.org/synopsys/vsclib013.lib - -The command "synth" provides a good default synthesis script (see "help synth"). -If possible a synthesis script should borrow from "synth". For example: - - # the high-level stuff - hierarchy - synth -run coarse - - # mapping to internal cells - techmap; opt -fast - dfflibmap -liberty mycells.lib - abc -liberty mycells.lib - clean - -Yosys is under construction. A more detailed documentation will follow. - - -Unsupported Verilog-2005 Features -================================= - -The following Verilog-2005 features are not supported by -yosys and there are currently no plans to add support -for them: - -- Non-synthesizable language features as defined in - IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 - -- The "tri", "triand", "trior", "wand" and "wor" net types - -- The "config" keyword and library map files - -- The "disable", "primitive" and "specify" statements - -- Latched logic (is synthesized as logic with feedback loops) - - -Verilog Attributes and non-standard features -============================================ - -- The 'full_case' attribute on case statements is supported - (also the non-standard "// synopsys full_case" directive) - -- The 'parallel_case' attribute on case statements is supported - (also the non-standard "// synopsys parallel_case" directive) - -- The "// synopsys translate_off" and "// synopsys translate_on" - directives are also supported (but the use of `ifdef .. `endif - is strongly recommended instead). - -- The "nomem2reg" attribute on modules or arrays prohibits the - automatic early conversion of arrays to separate registers. This - is potentially dangerous. Usually the front-end has good reasons - for converting an array to a list of registers. Prohibiting this - step will likely result in incorrect synthesis results. - -- The "mem2reg" attribute on modules or arrays forces the early - conversion of arrays to separate registers. - -- The "nomeminit" attribute on modules or arrays prohibits the - creation of initialized memories. This effectively puts "mem2reg" - on all memories that are written to in an "initial" block and - are not ROMs. - -- The "nolatches" attribute on modules or always-blocks - prohibits the generation of logic-loops for latches. Instead - all not explicitly assigned values default to x-bits. This does - not affect clocked storage elements such as flip-flops. - -- The "nosync" attribute on registers prohibits the generation of a - storage element. The register itself will always have all bits set - to 'x' (undefined). The variable may only be used as blocking assigned - temporary variable within an always block. This is mostly used internally - by yosys to synthesize Verilog functions and access arrays. - -- The "onehot" attribute on wires mark them as onehot state register. This - is used for example for memory port sharing and set by the fsm_map pass. - -- The "blackbox" attribute on modules is used to mark empty stub modules - that have the same ports as the real thing but do not contain information - on the internal configuration. This modules are only used by the synthesis - passes to identify input and output ports of cells. The Verilog backend - also does not output blackbox modules on default. - -- The "keep" attribute on cells and wires is used to mark objects that should - never be removed by the optimizer. This is used for example for cells that - have hidden connections that are not part of the netlist, such as IO pads. - Setting the "keep" attribute on a module has the same effect as setting it - on all instances of the module. - -- The "keep_hierarchy" attribute on cells and modules keeps the "flatten" - command from flattening the indicated cells and modules. - -- The "init" attribute on wires is set by the frontend when a register is - initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis - to add the necessary reset logic. - -- The "top" attribute on a module marks this module as the top of the - design hierarchy. The "hierarchy" command sets this attribute when called - with "-top". Other commands, such as "flatten" and various backends - use this attribute to determine the top module. - -- The "src" attribute is set on cells and wires created by to the string - ":" by the HDL front-end and is then carried - through the synthesis. When entities are combined, a new |-separated - string is created that contains all the string from the original entities. - -- In addition to the (* ... *) attribute syntax, yosys supports - the non-standard {* ... *} attribute syntax to set default attributes - for everything that comes after the {* ... *} statement. (Reset - by adding an empty {* *} statement.) - -- In module parameter and port declarations, and cell port and parameter - lists, a trailing comma is ignored. This simplifies writing verilog code - generators a bit in some cases. - -- Modules can be declared with "module mod_name(...);" (with three dots - instead of a list of module ports). With this syntax it is sufficient - to simply declare a module port as 'input' or 'output' in the module - body. - -- When defining a macro with `define, all text between triple double quotes - is interpreted as macro body, even if it contains unescaped newlines. The - tipple double quotes are removed from the macro body. For example: - - `define MY_MACRO(a, b) """ - assign a = 23; - assign b = 42; - """ - -- The attribute "via_celltype" can be used to implement a Verilog task or - function by instantiating the specified cell type. The value is the name - of the cell type to use. For functions the name of the output port can - be specified by appending it to the cell type separated by a whitespace. - The body of the task or function is unused in this case and can be used - to specify a behavioral model of the cell type for simulation. For example: - - module my_add3(A, B, C, Y); - parameter WIDTH = 8; - input [WIDTH-1:0] A, B, C; - output [WIDTH-1:0] Y; - ... - endmodule - - module top; - ... - (* via_celltype = "my_add3 Y" *) - (* via_celltype_defparam_WIDTH = 32 *) - function [31:0] add3; - input [31:0] A, B, C; - begin - add3 = A + B + C; - end - endfunction - ... - endmodule - -- A limited subset of DPI-C functions is supported. The plugin mechanism - (see "help plugin") can be used to load .so files with implementations - of DPI-C routines. As a non-standard extension it is possible to specify - a plugin alias using the ":" syntax. for example: - - module dpitest; - import "DPI-C" function foo:round = real my_round (real); - parameter real r = my_round(12.345); - endmodule - - $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - -- Sized constants (the syntax 's?[bodh]) support constant - expressions as . If the expression is not a simple identifier, it - must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 - -- The system tasks $finish and $display are supported in initial blocks - in an unconditional context (only if/case statements on parameters - and constant values). The intended use for this is synthesis-time DRC. - - -Non-standard or SystemVerilog features for formal verification -============================================================== - -- Support for "assert", "assume", and "restrict" is enabled when - read_verilog is called with -formal. - -- The system task $initstate evaluates to 1 in the initial state and - to 0 otherwise. - -- The system task $anyconst evaluates to any constant value. - -- The system task $anyseq evaluates to any value, possibly a different - value in each cycle. - -- The SystemVerilog tasks $past, $stable, $rose and $fell are supported - in any clocked block. - -- The syntax @($global_clock) can be used to create FFs that have no - explicit clock input ($ff cells). - - -Supported features from SystemVerilog -===================================== - -When read_verilog is called with -sv, it accepts some language features -from SystemVerilog: - -- The "assert" statement from SystemVerilog is supported in its most basic - form. In module context: "assert property ();" and within an - always block: "assert();". It is transformed to a $assert cell. - -- The "assume" and "restrict" statements from SystemVerilog are also - supported. The same limitations as with the "assert" statement apply. - -- The keywords "always_comb", "always_ff" and "always_latch", "logic" and - "bit" are supported. - -- SystemVerilog packages are supported. Once a SystemVerilog file is read - into a design with "read_verilog", all its packages are available to - SystemVerilog files being read into the same design afterwards. - - -Building the documentation -========================== - -Note that there is no need to build the manual if you just want to read it. -Simply download the PDF from http://www.clifford.at/yosys/documentation.html -instead. - -On Ubuntu, texlive needs these packages to be able to build the manual: - - sudo apt-get install texlive-binaries - sudo apt-get install texlive-science # install algorithm2e.sty - sudo apt-get install texlive-bibtex-extra # gets multibib.sty - sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty - sudo apt-get install texlive-publishers # IEEEtran.cls - -Also the non-free font luximono should be installed, there is unfortunately -no Ubuntu package for this so it should be installed separately using -`getnonfreefonts`: - - wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts - sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script - getnonfreefonts luximono # installs to /home/user/texmf - -Then execute, from the root of the repository: - - make manual - -Notes: - -- To run `make manual` you need to have installed yosys with `make install`, - otherwise it will fail on finding `kernel/yosys.h` while building - `PRESENTATION_Prog`. - diff --git a/yosys/README.md b/yosys/README.md index efb74ef4e..5132332a5 100644 --- a/yosys/README.md +++ b/yosys/README.md @@ -1,7 +1,7 @@ ``` yosys -- Yosys Open SYnthesis Suite -Copyright (C) 2012 - 2018 Clifford Wolf +Copyright (C) 2012 - 2019 Clifford Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above @@ -69,11 +69,14 @@ prerequisites for building yosys: graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev -Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: +Similarily, on Mac OS X Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle + +or MacPorts: + $ sudo port install bison flex readline gawk libffi \ - git graphviz pkgconfig python36 boost + git graphviz pkgconfig python36 boost tcl On FreeBSD use the following command to install all prerequisites: @@ -257,7 +260,7 @@ for them: - Non-synthesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 -- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types +- The ``tri``, ``triand`` and ``trior`` net types - The ``config`` and ``disable`` keywords and library map files @@ -350,6 +353,14 @@ Verilog Attributes and non-standard features through the synthesis. When entities are combined, a new |-separated string is created that contains all the string from the original entities. +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + +- The ``parameter`` and ``localparam`` attributes are used to mark wires + that represent module parameters or localparams (when the HDL front-end + is run in -pwires mode). + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset @@ -413,7 +424,7 @@ Verilog Attributes and non-standard features $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``'s?[bodh]``) support constant - expressions as . If the expression is not a simple identifier, it + expressions as ````. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in diff --git a/yosys/abc.rc b/yosys/abc.rc deleted file mode 100644 index 64e78950f..000000000 --- a/yosys/abc.rc +++ /dev/null @@ -1,174 +0,0 @@ -# global parameters -set check # checks intermediate networks -#set checkfio # prints warnings when fanins/fanouts are duplicated -set checkread # checks new networks after reading from file -set backup # saves backup networks retrived by "undo" and "recall" -set savesteps 1 # sets the maximum number of backup networks to save -set progressbar # display the progress bar - -# program names for internal calls -set dotwin dot.exe -set dotunix dot -set gsviewwin gsview32.exe -set gsviewunix gv -set siswin sis.exe -set sisunix sis -set mvsiswin mvsis.exe -set mvsisunix mvsis -set capowin MetaPl-Capo10.1-Win32.exe -set capounix MetaPl-Capo10.1 -set gnuplotwin wgnuplot.exe -set gnuplotunix gnuplot - -# standard aliases -alias b balance -alias cl cleanup -alias clp collapse -alias esd ext_seq_dcs -alias f fraig -alias fs fraig_sweep -alias fsto fraig_store -alias fres fraig_restore -alias ft fraig_trust -alias lp lutpack -alias pd print_dsd -alias pex print_exdc -d -alias pf print_factor -alias pfan print_fanio -alias pl print_level -alias pio print_io -alias pk print_kmap -alias ps print_stats -alias psu print_supp -alias psy print_symm -alias pun print_unate -alias q quit -alias r read -alias r3 retime -M 3 -alias r3f retime -M 3 -f -alias r3b retime -M 3 -b -alias ren renode -alias rh read_hie -alias rl read_blif -alias rb read_bench -alias ret retime -alias rp read_pla -alias rt read_truth -alias rv read_verilog -alias rvl read_verlib -alias rsup read_super mcnc5_old.super -alias rlib read_library -alias rlibc read_library cadence.genlib -alias rw rewrite -alias rwz rewrite -z -alias rf refactor -alias rfz refactor -z -alias re restructure -alias rez restructure -z -alias rs resub -alias rsz resub -z -alias sa set autoexec ps -alias scl scleanup -alias sif if -s -alias so source -x -alias st strash -alias sw sweep -alias ssw ssweep -alias tr0 trace_start -alias tr1 trace_check -alias trt "r c.blif; st; tr0; b; tr1" -alias u undo -alias w write -alias wa write_aiger -alias wb write_bench -alias wc write_cnf -alias wh write_hie -alias wl write_blif -alias wp write_pla -alias wv write_verilog - -# standard scripts -alias share "b; ren -s; fx; b" -alias sharedsd "b; ren -b; dsd -g; sw; fx; b" -alias resyn "b; rw; rwz; b; rwz; b" -alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b" -alias resyn2a "b; rw; b; rw; rwz; b; rwz; b" -alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b" -alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l" -alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l" -alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore" -alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore" -alias rwsat "st; rw -l; b -l; rw -l; rf -l" -alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l" -alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000" - -# resubstitution scripts for the IWLS paper -alias src_rw "st; rw -l; rwz -l; rwz -l" -alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l" -alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l" -alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b" -alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l" - -# experimental implementation of don't-cares -alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b" -alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l" - -# minimizing for FF literals -alias fflitmin "compress2rs; ren; sop; ps -f" - -# temporaries -#alias t "rvl th/lib.v; rvv th/t2.v" -#alias t "so c/pure_sat/test.c" -#alias t "r c/14/csat_998.bench; st; ps" -#alias t0 "r res.blif; aig; mfs" -#alias t "r res2.blif; aig; mfs" - -#alias tt "r a/quip_opt/nut_001_opt.blif" -#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif" -#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v" - -alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps" - -alias qs1 "qvar -I 96 -u; ps; qbf -P 96" -alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96" -alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96" -alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96" -alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96" -alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96" -alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96" -alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96" -alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96" -alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96" - -alias chnew "st; haig_start; resyn2; haig_use" -alias chnewrs "st; haig_start; resyn2rs; haig_use" - -alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps" -alias trec "rec_start; r c.blif; st; rec_add; rec_use" -alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use" -alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use" -alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use" -alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use" -alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use" -alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use" -alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use" - -#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec" -alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec" -alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec" -alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec" - -#alias t "r c.blif; st; wc c.cnf" -#alias t "r test/dsdmap6.blif; lutpack -vw; cec" -#alias t "r i10_if4.blif; lp" -#alias t1 "r pj1_if4.blif; lp" -#alias t2 "r pj1_if6.blif; lp" -#alias t "r pj/pj1.blif; st; dfraig -v" -#alias t "r c/16/csat_2.bench; st; dfraig -C 100 -v -r" -#alias t "r c/16/csat_147.bench; st; dfraig -C 10 -v -r" -#alias t "r i10.blif; st; ps; csweep; ps; cec" -#alias t "r c/5/csat_777.bench; st; csweep -v" -#alias t "r i10.blif; st; drw -v" -alias t "r c.blif; st; drf" - - diff --git a/yosys/backends/aiger/aiger.cc b/yosys/backends/aiger/aiger.cc index dfe506c66..6863b40fa 100644 --- a/yosys/backends/aiger/aiger.cc +++ b/yosys/backends/aiger/aiger.cc @@ -89,7 +89,8 @@ struct AigerWriter aig_map[bit] = mkgate(a0, a1); } else if (alias_map.count(bit)) { - aig_map[bit] = bit2aig(alias_map.at(bit)); + int a = bit2aig(alias_map.at(bit)); + aig_map[bit] = a; } if (bit == State::Sx || bit == State::Sz) @@ -776,6 +777,7 @@ struct AigerBackend : public Backend { writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode); if (!map_filename.empty()) { + rewrite_filename(filename); std::ofstream mapf; mapf.open(map_filename.c_str(), std::ofstream::trunc); if (mapf.fail()) diff --git a/yosys/backends/blif/blif.cc b/yosys/backends/blif/blif.cc index b6dbd84cb..a1761b662 100644 --- a/yosys/backends/blif/blif.cc +++ b/yosys/backends/blif/blif.cc @@ -409,12 +409,26 @@ struct BlifDumper f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type)); for (auto &conn : cell->connections()) - for (int i = 0; i < conn.second.size(); i++) { - if (conn.second.size() == 1) - f << stringf(" %s", cstr(conn.first)); - else - f << stringf(" %s[%d]", cstr(conn.first), i); - f << stringf("=%s", cstr(conn.second.extract(i, 1))); + { + if (conn.second.size() == 1) { + f << stringf(" %s=%s", cstr(conn.first), cstr(conn.second[0])); + continue; + } + + Module *m = design->module(cell->type); + Wire *w = m ? m->wire(conn.first) : nullptr; + + if (w == nullptr) { + for (int i = 0; i < GetSize(conn.second); i++) + f << stringf(" %s[%d]=%s", cstr(conn.first), i, cstr(conn.second[i])); + } else { + for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) { + SigBit sig(w, i); + f << stringf(" %s[%d]=%s", cstr(conn.first), sig.wire->upto ? + sig.wire->start_offset+sig.wire->width-sig.offset-1 : + sig.wire->start_offset+sig.offset, cstr(conn.second[i])); + } + } } f << stringf("\n"); diff --git a/yosys/backends/btor/btor.cc b/yosys/backends/btor/btor.cc index 91f238fa5..a507b120b 100644 --- a/yosys/backends/btor/btor.cc +++ b/yosys/backends/btor/btor.cc @@ -17,6 +17,11 @@ * */ +// [[CITE]] Btor2 , BtorMC and Boolector 3.0 +// Aina Niemetz, Mathias Preiner, Clifford Wolf, Armin Biere +// Computer Aided Verification - 30th International Conference, CAV 2018 +// https://cs.stanford.edu/people/niemetz/publication/2018/niemetzpreinerwolfbiere-cav18/ + #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" @@ -129,7 +134,13 @@ struct BtorWorker void export_cell(Cell *cell) { - log_assert(cell_recursion_guard.count(cell) == 0); + if (cell_recursion_guard.count(cell)) { + string cell_list; + for (auto c : cell_recursion_guard) + cell_list += stringf("\n %s", log_id(c)); + log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str()); + } + cell_recursion_guard.insert(cell); btorf_push(log_id(cell)); @@ -869,9 +880,28 @@ struct BtorWorker else { if (bit_cell.count(bit) == 0) - log_error("No driver for signal bit %s.\n", log_signal(bit)); - export_cell(bit_cell.at(bit)); - log_assert(bit_nid.count(bit)); + { + SigSpec s = bit; + + while (i+GetSize(s) < GetSize(sig) && sig[i+GetSize(s)].wire != nullptr && + bit_cell.count(sig[i+GetSize(s)]) == 0) + s.append(sig[i+GetSize(s)]); + + log_warning("No driver for signal %s.\n", log_signal(s)); + + int sid = get_bv_sid(GetSize(s)); + int nid = next_nid++; + btorf("%d input %d %s\n", nid, sid); + nid_width[nid] = GetSize(s); + + i += GetSize(s)-1; + continue; + } + else + { + export_cell(bit_cell.at(bit)); + log_assert(bit_nid.count(bit)); + } } } diff --git a/yosys/backends/ilang/ilang_backend.cc b/yosys/backends/ilang/ilang_backend.cc index 04d1ee311..313af7d5c 100644 --- a/yosys/backends/ilang/ilang_backend.cc +++ b/yosys/backends/ilang/ilang_backend.cc @@ -204,6 +204,11 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { + for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) { + f << stringf("%s attribute %s ", indent.c_str(), ait->first.c_str()); + dump_const(f, ait->second); + f << stringf("\n"); + } f << stringf("%s case ", indent.c_str()); for (size_t i = 0; i < (*it)->compare.size(); i++) { if (i > 0) @@ -483,6 +488,7 @@ struct DumpPass : public Pass { std::stringstream buf; if (!filename.empty()) { + rewrite_filename(filename); std::ofstream *ff = new std::ofstream; ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc); if (ff->fail()) { diff --git a/yosys/backends/json/json.cc b/yosys/backends/json/json.cc index f5c687981..dda4dfedd 100644 --- a/yosys/backends/json/json.cc +++ b/yosys/backends/json/json.cc @@ -126,6 +126,10 @@ struct JsonWriter f << stringf("%s\n", first ? "" : ","); f << stringf(" %s: {\n", get_name(n).c_str()); f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output"); + if (w->start_offset) + f << stringf(" \"offset\": %d,\n", w->start_offset); + if (w->upto) + f << stringf(" \"upto\": 1,\n"); f << stringf(" \"bits\": %s\n", get_bits(w).c_str()); f << stringf(" }"); first = false; @@ -189,6 +193,10 @@ struct JsonWriter f << stringf(" %s: {\n", get_name(w->name).c_str()); f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0"); f << stringf(" \"bits\": %s,\n", get_bits(w).c_str()); + if (w->start_offset) + f << stringf(" \"offset\": %d,\n", w->start_offset); + if (w->upto) + f << stringf(" \"upto\": 1,\n"); f << stringf(" \"attributes\": {"); write_parameters(w->attributes); f << stringf("\n }\n"); @@ -525,6 +533,7 @@ struct JsonPass : public Pass { std::stringstream buf; if (!filename.empty()) { + rewrite_filename(filename); std::ofstream *ff = new std::ofstream; ff->open(filename.c_str(), std::ofstream::trunc); if (ff->fail()) { diff --git a/yosys/backends/protobuf/protobuf.cc b/yosys/backends/protobuf/protobuf.cc index 549fc73ae..fff110bb0 100644 --- a/yosys/backends/protobuf/protobuf.cc +++ b/yosys/backends/protobuf/protobuf.cc @@ -336,6 +336,7 @@ struct ProtobufPass : public Pass { std::stringstream buf; if (!filename.empty()) { + rewrite_filename(filename); std::ofstream *ff = new std::ofstream; ff->open(filename.c_str(), std::ofstream::trunc); if (ff->fail()) { diff --git a/yosys/backends/smt2/smtio.py b/yosys/backends/smt2/smtio.py index ab20a4af2..ae7968a1b 100644 --- a/yosys/backends/smt2/smtio.py +++ b/yosys/backends/smt2/smtio.py @@ -1023,6 +1023,8 @@ class MkVcd: assert t >= self.t if t != self.t: if self.t == -1: + print("$version Generated by Yosys-SMTBMC $end", file=self.f) + print("$timescale 1ns $end", file=self.f) print("$var integer 32 t smt_step $end", file=self.f) print("$var event 1 ! smt_clock $end", file=self.f) @@ -1041,7 +1043,10 @@ class MkVcd: scope = scope[:-1] while uipath[:-1] != scope: - print("$scope module %s $end" % uipath[len(scope)], file=self.f) + scopename = uipath[len(scope)] + if scopename.startswith("$"): + scopename = "\\" + scopename + print("$scope module %s $end" % scopename, file=self.f) scope.append(uipath[len(scope)]) if path in self.clocks and self.clocks[path][1] == "event": diff --git a/yosys/backends/verilog/verilog_backend.cc b/yosys/backends/verilog/verilog_backend.cc index 827af5d85..087c6fec6 100644 --- a/yosys/backends/verilog/verilog_backend.cc +++ b/yosys/backends/verilog/verilog_backend.cc @@ -364,20 +364,22 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) } } -void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false) +void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false, bool as_comment = false) { if (noattr) return; + if (attr2comment) + as_comment = true; for (auto it = attributes.begin(); it != attributes.end(); ++it) { - f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str()); + f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = "); if (modattr && (it->second == Const(0, 1) || it->second == Const(0))) f << stringf(" 0 "); else if (modattr && (it->second == Const(1, 1) || it->second == Const(1))) f << stringf(" 1 "); else - dump_const(f, it->second, -1, 0, false, attr2comment); - f << stringf(" %s%c", attr2comment ? "*/" : "*)", term); + dump_const(f, it->second, -1, 0, false, as_comment); + f << stringf(" %s%c", as_comment ? "*/" : "*)", term); } } @@ -1492,12 +1494,14 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw return; } + dump_attributes(f, indent, sw->attributes); f << stringf("%s" "casez (", indent.c_str()); dump_sigspec(f, sw->signal); f << stringf(")\n"); bool got_default = false; for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { + dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { if (got_default) continue; @@ -1662,7 +1666,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } } - dump_attributes(f, indent, module->attributes, '\n', true); + dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { diff --git a/yosys/frontends/aiger/aigerparse.cc b/yosys/frontends/aiger/aigerparse.cc index 38348cd65..68552fd06 100644 --- a/yosys/frontends/aiger/aigerparse.cc +++ b/yosys/frontends/aiger/aigerparse.cc @@ -34,354 +34,389 @@ YOSYS_NAMESPACE_BEGIN AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name) - : design(design), f(f), clk_name(clk_name) + : design(design), f(f), clk_name(clk_name) { - module = new RTLIL::Module; - module->name = module_name; - if (design->module(module->name)) - log_error("Duplicate definition of module %s!\n", log_id(module->name)); + module = new RTLIL::Module; + module->name = module_name; + if (design->module(module->name)) + log_error("Duplicate definition of module %s!\n", log_id(module->name)); } void AigerReader::parse_aiger() { - std::string header; - f >> header; - if (header != "aag" && header != "aig") - log_error("Unsupported AIGER file!\n"); + std::string header; + f >> header; + if (header != "aag" && header != "aig") + log_error("Unsupported AIGER file!\n"); - // Parse rest of header - if (!(f >> M >> I >> L >> O >> A)) - log_error("Invalid AIGER header\n"); + // Parse rest of header + if (!(f >> M >> I >> L >> O >> A)) + log_error("Invalid AIGER header\n"); - // Optional values - B = C = J = F = 0; - if (f.peek() != ' ') goto end_of_header; - if (!(f >> B)) log_error("Invalid AIGER header\n"); - if (f.peek() != ' ') goto end_of_header; - if (!(f >> C)) log_error("Invalid AIGER header\n"); - if (f.peek() != ' ') goto end_of_header; - if (!(f >> J)) log_error("Invalid AIGER header\n"); - if (f.peek() != ' ') goto end_of_header; - if (!(f >> F)) log_error("Invalid AIGER header\n"); + // Optional values + B = C = J = F = 0; + if (f.peek() != ' ') goto end_of_header; + if (!(f >> B)) log_error("Invalid AIGER header\n"); + if (f.peek() != ' ') goto end_of_header; + if (!(f >> C)) log_error("Invalid AIGER header\n"); + if (f.peek() != ' ') goto end_of_header; + if (!(f >> J)) log_error("Invalid AIGER header\n"); + if (f.peek() != ' ') goto end_of_header; + if (!(f >> F)) log_error("Invalid AIGER header\n"); end_of_header: - std::string line; - std::getline(f, line); // Ignore up to start of next line, as standard - // says anything that follows could be used for - // optional sections + std::string line; + std::getline(f, line); // Ignore up to start of next line, as standard + // says anything that follows could be used for + // optional sections - log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F); + log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F); - line_count = 1; + line_count = 1; - if (header == "aag") - parse_aiger_ascii(); - else if (header == "aig") - parse_aiger_binary(); - else - log_abort(); + if (header == "aag") + parse_aiger_ascii(); + else if (header == "aig") + parse_aiger_binary(); + else + log_abort(); - // Parse footer (symbol table, comments, etc.) - unsigned l1; - std::string s; - for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) { - if (c == 'i' || c == 'l' || c == 'o') { - f.ignore(1); - if (!(f >> l1 >> s)) - log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count); + RTLIL::Wire* n0 = module->wire("\\n0"); + if (n0) + module->connect(n0, RTLIL::S0); - if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) - log_error("Line %u has invalid symbol position!\n", line_count); + for (unsigned i = 0; i < outputs.size(); ++i) { + RTLIL::Wire *wire = outputs[i]; + if (wire->port_input) { + RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o"); + o_wire->port_output = true; + wire->port_output = false; + module->connect(o_wire, wire); + outputs[i] = o_wire; + } + } - RTLIL::Wire* wire; - if (c == 'i') wire = inputs[l1]; - else if (c == 'l') wire = latches[l1]; - else if (c == 'o') wire = outputs[l1]; - else log_abort(); + // Parse footer (symbol table, comments, etc.) + unsigned l1; + std::string s; + for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) { + if (c == 'i' || c == 'l' || c == 'o' || c == 'b') { + f.ignore(1); + if (!(f >> l1 >> s)) + log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count); - module->rename(wire, stringf("\\%s", s.c_str())); - } - else if (c == 'b' || c == 'j' || c == 'f') { - // TODO - } - else if (c == 'c') { - f.ignore(1); - if (f.peek() == '\n') - break; - // Else constraint (TODO) - } - else - log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); - std::getline(f, line); // Ignore up to start of next line - } + if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) + log_error("Line %u has invalid symbol position!\n", line_count); - module->fixup_ports(); - design->add(module); + RTLIL::Wire* wire; + if (c == 'i') wire = inputs[l1]; + else if (c == 'l') wire = latches[l1]; + else if (c == 'o') wire = outputs[l1]; + else if (c == 'b') wire = bad_properties[l1]; + else log_abort(); + + module->rename(wire, stringf("\\%s", s.c_str())); + } + else if (c == 'j' || c == 'f') { + // TODO + } + else if (c == 'c') { + f.ignore(1); + if (f.peek() == '\n') + break; + // Else constraint (TODO) + } + else + log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); + std::getline(f, line); // Ignore up to start of next line + } + + module->fixup_ports(); + design->add(module); } static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal) { - const unsigned variable = literal >> 1; - const bool invert = literal & 1; - RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix? - RTLIL::Wire *wire = module->wire(wire_name); - if (wire) return wire; - log_debug("Creating %s\n", wire_name.c_str()); - wire = module->addWire(wire_name); - if (!invert) return wire; - RTLIL::IdString wire_inv_name(stringf("\\n%d", variable)); - RTLIL::Wire *wire_inv = module->wire(wire_inv_name); - if (wire_inv) { - if (module->cell(wire_inv_name)) return wire; - } - else { - log_debug("Creating %s\n", wire_inv_name.c_str()); - wire_inv = module->addWire(wire_inv_name); - } + const unsigned variable = literal >> 1; + const bool invert = literal & 1; + RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix? + RTLIL::Wire *wire = module->wire(wire_name); + if (wire) return wire; + log_debug("Creating %s\n", wire_name.c_str()); + wire = module->addWire(wire_name); + if (!invert) return wire; + RTLIL::IdString wire_inv_name(stringf("\\n%d", variable)); + RTLIL::Wire *wire_inv = module->wire(wire_inv_name); + if (wire_inv) { + if (module->cell(wire_inv_name)) return wire; + } + else { + log_debug("Creating %s\n", wire_inv_name.c_str()); + wire_inv = module->addWire(wire_inv_name); + } - log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); - module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix? + log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); + module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix? - return wire; + return wire; } void AigerReader::parse_aiger_ascii() { - std::string line; - std::stringstream ss; + std::string line; + std::stringstream ss; - unsigned l1, l2, l3; + unsigned l1, l2, l3; - // Parse inputs - for (unsigned i = 0; i < I; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as an input!\n", line_count); - log_debug("%d is an input\n", l1); - log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted? - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_input = true; - inputs.push_back(wire); - } + // Parse inputs + for (unsigned i = 1; i <= I; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as an input!\n", line_count); + log_debug("%d is an input\n", l1); + log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted? + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_input = true; + inputs.push_back(wire); + } - // Parse latches - RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - clk_wire = module->wire(clk_name); - log_assert(!clk_wire); - log_debug("Creating %s\n", clk_name.c_str()); - clk_wire = module->addWire(clk_name); - clk_wire->port_input = true; - } - for (unsigned i = 0; i < L; ++i, ++line_count) { - if (!(f >> l1 >> l2)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); - log_debug("%d %d is a latch\n", l1, l2); - log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted? - RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); + // Parse latches + RTLIL::Wire *clk_wire = nullptr; + if (L > 0) { + clk_wire = module->wire(clk_name); + log_assert(!clk_wire); + log_debug("Creating %s\n", clk_name.c_str()); + clk_wire = module->addWire(clk_name); + clk_wire->port_input = true; + } + for (unsigned i = 0; i < L; ++i, ++line_count) { + if (!(f >> l1 >> l2)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); + log_debug("%d %d is a latch\n", l1, l2); + log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted? + RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); + module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); - // Reset logic is optional in AIGER 1.9 - if (f.peek() == ' ') { - if (!(f >> l3)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); + // Reset logic is optional in AIGER 1.9 + if (f.peek() == ' ') { + if (!(f >> l3)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); - if (l3 == 0 || l3 == 1) - q_wire->attributes["\\init"] = RTLIL::Const(l3); - else if (l3 == l1) { - //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); - } - else - log_error("Line %u has invalid reset literal for latch!\n", line_count); - } - else { - // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = RTLIL::Const(0); - } - latches.push_back(q_wire); - } + if (l3 == 0) + q_wire->attributes["\\init"] = RTLIL::S0; + else if (l3 == 1) + q_wire->attributes["\\init"] = RTLIL::S1; + else if (l3 == l1) { + //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); + } + else + log_error("Line %u has invalid reset literal for latch!\n", line_count); + } + else { + // AIGER latches are assumed to be initialized to zero + q_wire->attributes["\\init"] = RTLIL::S0; + } + latches.push_back(q_wire); + } - // Parse outputs - for (unsigned i = 0; i < O; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as an output!\n", line_count); + // Parse outputs + for (unsigned i = 0; i < O; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as an output!\n", line_count); - log_debug("%d is an output\n", l1); - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_output = true; - outputs.push_back(wire); - } - std::getline(f, line); // Ignore up to start of next line + log_debug("%d is an output\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + outputs.push_back(wire); + } - // TODO: Parse bad state properties - for (unsigned i = 0; i < B; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // Parse bad properties + for (unsigned i = 0; i < B; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); - // TODO: Parse invariant constraints - for (unsigned i = 0; i < C; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + log_debug("%d is a bad state property\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + bad_properties.push_back(wire); + } - // TODO: Parse justice properties - for (unsigned i = 0; i < J; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse invariant constraints + for (unsigned i = 0; i < C; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse fairness constraints - for (unsigned i = 0; i < F; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse justice properties + for (unsigned i = 0; i < J; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // Parse AND - for (unsigned i = 0; i < A; ++i) { - if (!(f >> l1 >> l2 >> l3)) - log_error("Line %u cannot be interpreted as an AND!\n", line_count); + // TODO: Parse fairness constraints + for (unsigned i = 0; i < F; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - log_debug("%d %d %d is an AND\n", l1, l2, l3); - log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? - RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); - RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire); - } - std::getline(f, line); // Ignore up to start of next line + // Parse AND + for (unsigned i = 0; i < A; ++i) { + if (!(f >> l1 >> l2 >> l3)) + log_error("Line %u cannot be interpreted as an AND!\n", line_count); + + log_debug("%d %d %d is an AND\n", l1, l2, l3); + log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? + RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); + RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); + module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire); + } + std::getline(f, line); // Ignore up to start of next line } static unsigned parse_next_delta_literal(std::istream &f, unsigned ref) { - unsigned x = 0, i = 0; - unsigned char ch; - while ((ch = f.get()) & 0x80) - x |= (ch & 0x7f) << (7 * i++); - return ref - (x | (ch << (7 * i))); + unsigned x = 0, i = 0; + unsigned char ch; + while ((ch = f.get()) & 0x80) + x |= (ch & 0x7f) << (7 * i++); + return ref - (x | (ch << (7 * i))); } void AigerReader::parse_aiger_binary() { - unsigned l1, l2, l3; - std::string line; + unsigned l1, l2, l3; + std::string line; - // Parse inputs - for (unsigned i = 1; i <= I; ++i) { - RTLIL::Wire *wire = createWireIfNotExists(module, i << 1); - wire->port_input = true; - inputs.push_back(wire); - } + // Parse inputs + for (unsigned i = 1; i <= I; ++i) { + RTLIL::Wire *wire = createWireIfNotExists(module, i << 1); + wire->port_input = true; + inputs.push_back(wire); + } - // Parse latches - RTLIL::Wire *clk_wire = nullptr; - if (L > 0) { - clk_wire = module->wire(clk_name); - log_assert(!clk_wire); - log_debug("Creating %s\n", clk_name.c_str()); - clk_wire = module->addWire(clk_name); - clk_wire->port_input = true; - } - l1 = (I+1) * 2; - for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) { - if (!(f >> l2)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); - log_debug("%d %d is a latch\n", l1, l2); - RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); + // Parse latches + RTLIL::Wire *clk_wire = nullptr; + if (L > 0) { + clk_wire = module->wire(clk_name); + log_assert(!clk_wire); + log_debug("Creating %s\n", clk_name.c_str()); + clk_wire = module->addWire(clk_name); + clk_wire->port_input = true; + } + l1 = (I+1) * 2; + for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) { + if (!(f >> l2)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); + log_debug("%d %d is a latch\n", l1, l2); + RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + module->addDff(NEW_ID, clk_wire, d_wire, q_wire); - // Reset logic is optional in AIGER 1.9 - if (f.peek() == ' ') { - if (!(f >> l3)) - log_error("Line %u cannot be interpreted as a latch!\n", line_count); + // Reset logic is optional in AIGER 1.9 + if (f.peek() == ' ') { + if (!(f >> l3)) + log_error("Line %u cannot be interpreted as a latch!\n", line_count); - if (l3 == 0 || l3 == 1) - q_wire->attributes["\\init"] = RTLIL::Const(l3); - else if (l3 == l1) { - //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); - } - else - log_error("Line %u has invalid reset literal for latch!\n", line_count); - } - else { - // AIGER latches are assumed to be initialized to zero - q_wire->attributes["\\init"] = RTLIL::Const(0); - } - latches.push_back(q_wire); - } + if (l3 == 0) + q_wire->attributes["\\init"] = RTLIL::S0; + else if (l3 == 1) + q_wire->attributes["\\init"] = RTLIL::S1; + else if (l3 == l1) { + //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx); + } + else + log_error("Line %u has invalid reset literal for latch!\n", line_count); + } + else { + // AIGER latches are assumed to be initialized to zero + q_wire->attributes["\\init"] = RTLIL::S0; + } + latches.push_back(q_wire); + } - // Parse outputs - for (unsigned i = 0; i < O; ++i, ++line_count) { - if (!(f >> l1)) - log_error("Line %u cannot be interpreted as an output!\n", line_count); + // Parse outputs + for (unsigned i = 0; i < O; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as an output!\n", line_count); - log_debug("%d is an output\n", l1); - RTLIL::Wire *wire = createWireIfNotExists(module, l1); - wire->port_output = true; - outputs.push_back(wire); - } - std::getline(f, line); // Ignore up to start of next line + log_debug("%d is an output\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + outputs.push_back(wire); + } + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse bad state properties - for (unsigned i = 0; i < B; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // Parse bad properties + for (unsigned i = 0; i < B; ++i, ++line_count) { + if (!(f >> l1)) + log_error("Line %u cannot be interpreted as a bad state property!\n", line_count); - // TODO: Parse invariant constraints - for (unsigned i = 0; i < C; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + log_debug("%d is a bad state property\n", l1); + RTLIL::Wire *wire = createWireIfNotExists(module, l1); + wire->port_output = true; + bad_properties.push_back(wire); + } + if (B > 0) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse justice properties - for (unsigned i = 0; i < J; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse invariant constraints + for (unsigned i = 0; i < C; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // TODO: Parse fairness constraints - for (unsigned i = 0; i < F; ++i, ++line_count) - std::getline(f, line); // Ignore up to start of next line + // TODO: Parse justice properties + for (unsigned i = 0; i < J; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - // Parse AND - l1 = (I+L+1) << 1; - for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) { - l2 = parse_next_delta_literal(f, l1); - l3 = parse_next_delta_literal(f, l2); + // TODO: Parse fairness constraints + for (unsigned i = 0; i < F; ++i, ++line_count) + std::getline(f, line); // Ignore up to start of next line - log_debug("%d %d %d is an AND\n", l1, l2, l3); - log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? - RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); - RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); - RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); + // Parse AND + l1 = (I+L+1) << 1; + for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) { + l2 = parse_next_delta_literal(f, l1); + l3 = parse_next_delta_literal(f, l2); - RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_"); - and_cell->setPort("\\A", i1_wire); - and_cell->setPort("\\B", i2_wire); - and_cell->setPort("\\Y", o_wire); - } + log_debug("%d %d %d is an AND\n", l1, l2, l3); + log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted? + RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); + RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); + RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); + + RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_"); + and_cell->setPort("\\A", i1_wire); + and_cell->setPort("\\B", i2_wire); + and_cell->setPort("\\Y", o_wire); + } } struct AigerFrontend : public Frontend { - AigerFrontend() : Frontend("aiger", "read AIGER file") { } - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" read_aiger [options] [filename]\n"); - log("\n"); - log("Load module from an AIGER file into the current design.\n"); - log("\n"); - log(" -module_name \n"); - log(" Name of module to be created (default: )" + AigerFrontend() : Frontend("aiger", "read AIGER file") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" read_aiger [options] [filename]\n"); + log("\n"); + log("Load module from an AIGER file into the current design.\n"); + log("\n"); + log(" -module_name \n"); + log(" Name of module to be created (default: " #ifdef _WIN32 - "top" // FIXME + "top" // FIXME #else - "" + "" #endif - ")\n"); - log("\n"); - log(" -clk_name \n"); - log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); - log(" this name (default: clk)\n"); - log("\n"); - } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing AIGER frontend.\n"); + ")\n"); + log("\n"); + log(" -clk_name \n"); + log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); + log(" this name (default: clk)\n"); + log("\n"); + } + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing AIGER frontend.\n"); - RTLIL::IdString clk_name = "\\clk"; - RTLIL::IdString module_name; + RTLIL::IdString clk_name = "\\clk"; + RTLIL::IdString module_name; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -398,19 +433,19 @@ struct AigerFrontend : public Frontend { } extra_args(f, filename, args, argidx); - if (module_name.empty()) { + if (module_name.empty()) { #ifdef _WIN32 - module_name = "top"; // FIXME: basename equivalent on Win32? + module_name = "top"; // FIXME: basename equivalent on Win32? #else - char* bn = strdup(filename.c_str()); - module_name = RTLIL::escape_id(bn); - free(bn); + char* bn = strdup(filename.c_str()); + module_name = RTLIL::escape_id(bn); + free(bn); #endif - } + } - AigerReader reader(design, *f, module_name, clk_name); + AigerReader reader(design, *f, module_name, clk_name); reader.parse_aiger(); - } + } } AigerFrontend; YOSYS_NAMESPACE_END diff --git a/yosys/frontends/aiger/aigerparse.h b/yosys/frontends/aiger/aigerparse.h index c49cd152d..0e3719cc4 100644 --- a/yosys/frontends/aiger/aigerparse.h +++ b/yosys/frontends/aiger/aigerparse.h @@ -39,6 +39,7 @@ struct AigerReader std::vector inputs; std::vector latches; std::vector outputs; + std::vector bad_properties; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name); void parse_aiger(); diff --git a/yosys/frontends/ast/ast.cc b/yosys/frontends/ast/ast.cc index 5623541b2..3d066af53 100644 --- a/yosys/frontends/ast/ast.cc +++ b/yosys/frontends/ast/ast.cc @@ -46,7 +46,7 @@ namespace AST { // instantiate global variables (private API) namespace AST_INTERNAL { bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; - bool flag_nomem2reg, flag_mem2reg, flag_noblackbox, flag_lib, flag_nowb, flag_noopt, flag_icells, flag_autowire; + bool flag_nomem2reg, flag_mem2reg, flag_noblackbox, flag_lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_autowire; AstNode *current_ast, *current_ast_mod; std::map current_scope; const dict *genRTLIL_subst_ptr = NULL; @@ -154,6 +154,7 @@ std::string AST::type2str(AstNodeType type) X(AST_GENIF) X(AST_GENCASE) X(AST_GENBLOCK) + X(AST_TECALL) X(AST_POSEDGE) X(AST_NEGEDGE) X(AST_EDGE) @@ -194,6 +195,9 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch is_logic = false; is_signed = false; is_string = false; + is_wand = false; + is_wor = false; + is_unsized = false; was_checked = false; range_valid = false; range_swapped = false; @@ -722,7 +726,7 @@ AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width) } // create an AST node for a constant (using a bit vector as value) -AstNode *AstNode::mkconst_bits(const std::vector &v, bool is_signed) +AstNode *AstNode::mkconst_bits(const std::vector &v, bool is_signed, bool is_unsized) { AstNode *node = new AstNode(AST_CONSTANT); node->is_signed = is_signed; @@ -736,9 +740,15 @@ AstNode *AstNode::mkconst_bits(const std::vector &v, bool is_signe node->range_valid = true; node->range_left = node->bits.size()-1; node->range_right = 0; + node->is_unsized = is_unsized; return node; } +AstNode *AstNode::mkconst_bits(const std::vector &v, bool is_signed) +{ + return mkconst_bits(v, is_signed, false); +} + // create an AST node for a constant (using a string in bit vector form as value) AstNode *AstNode::mkconst_str(const std::vector &v) { @@ -775,6 +785,14 @@ bool AstNode::bits_only_01() const return true; } +RTLIL::Const AstNode::bitsAsUnsizedConst(int width) +{ + RTLIL::State extbit = bits.back(); + while (width > int(bits.size())) + bits.push_back(extbit); + return RTLIL::Const(bits); +} + RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed) { std::vector bits = this->bits; @@ -1094,6 +1112,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast current_module->nowb = flag_nowb; current_module->noopt = flag_noopt; current_module->icells = flag_icells; + current_module->pwires = flag_pwires; current_module->autowire = flag_autowire; current_module->fixup_ports(); @@ -1108,7 +1127,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast // create AstModule instances for all modules in the AST tree and add them to 'design' void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, - bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) + bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; @@ -1126,6 +1145,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump flag_nowb = nowb; flag_noopt = noopt; flag_icells = icells; + flag_pwires = pwires; flag_autowire = autowire; log_assert(current_ast->type == AST_DESIGN); @@ -1462,6 +1482,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dictlib = lib; new_mod->noopt = noopt; new_mod->icells = icells; + new_mod->pwires = pwires; new_mod->autowire = autowire; return new_mod; diff --git a/yosys/frontends/ast/ast.h b/yosys/frontends/ast/ast.h index 281cbe086..54b2fb319 100644 --- a/yosys/frontends/ast/ast.h +++ b/yosys/frontends/ast/ast.h @@ -137,7 +137,8 @@ namespace AST AST_GENIF, AST_GENCASE, AST_GENBLOCK, - + AST_TECALL, + AST_POSEDGE, AST_NEGEDGE, AST_EDGE, @@ -173,7 +174,7 @@ namespace AST // node content - most of it is unused in most node types std::string str; std::vector bits; - bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked; + bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized; int port_id, range_left, range_right; uint32_t integer; double realvalue; @@ -262,6 +263,7 @@ namespace AST // helper functions for creating AST nodes for constants static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32); + static AstNode *mkconst_bits(const std::vector &v, bool is_signed, bool is_unsized); static AstNode *mkconst_bits(const std::vector &v, bool is_signed); static AstNode *mkconst_str(const std::vector &v); static AstNode *mkconst_str(const std::string &str); @@ -269,6 +271,7 @@ namespace AST // helper function for creating sign-extended const objects RTLIL::Const bitsAsConst(int width, bool is_signed); RTLIL::Const bitsAsConst(int width = -1); + RTLIL::Const bitsAsUnsizedConst(int width); RTLIL::Const asAttrConst(); RTLIL::Const asParaConst(); uint64_t asInt(bool is_signed); @@ -283,13 +286,13 @@ namespace AST // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, - bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); + bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions struct AstModule : RTLIL::Module { AstNode *ast; - bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, autowire; + bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire; ~AstModule() YS_OVERRIDE; RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail) YS_OVERRIDE; RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, dict modports, bool mayfail) YS_OVERRIDE; @@ -322,7 +325,7 @@ namespace AST_INTERNAL { // internal state variables extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit; - extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; + extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map current_scope; extern const dict *genRTLIL_subst_ptr; diff --git a/yosys/frontends/ast/genrtlil.cc b/yosys/frontends/ast/genrtlil.cc index 379fed641..571ddd988 100644 --- a/yosys/frontends/ast/genrtlil.cc +++ b/yosys/frontends/ast/genrtlil.cc @@ -504,6 +504,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::CaseRule *backup_case = current_case; current_case = new RTLIL::CaseRule; + current_case->attributes["\\src"] = stringf("%s:%d", child->filename.c_str(), child->linenum); last_generated_case = current_case; addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue); for (auto node : child->children) { @@ -853,7 +854,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_FUNCTION: case AST_DPI_FUNCTION: case AST_AUTOWIRE: - case AST_LOCALPARAM: case AST_DEFPARAM: case AST_GENVAR: case AST_GENFOR: @@ -895,6 +895,26 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // remember the parameter, needed for example in techmap case AST_PARAMETER: current_module->avail_parameters.insert(str); + /* fall through */ + case AST_LOCALPARAM: + if (flag_pwires) + { + if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT) + log_file_error(filename, linenum, "Parameter `%s' with non-constant value!\n", str.c_str()); + + RTLIL::Const val = children[0]->bitsAsConst(); + RTLIL::Wire *wire = current_module->addWire(str, GetSize(val)); + current_module->connect(wire, val); + + wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1; + + for (auto &attr : attributes) { + if (attr.second->type != AST_CONSTANT) + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + wire->attributes[attr.first] = attr.second->asAttrConst(); + } + } break; // create an RTLIL::Wire for an AST_WIRE node @@ -904,7 +924,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!range_valid) log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str()); - log_assert(range_left >= range_right || (range_left == -1 && range_right == 0)); + if (!(range_left >= range_right || (range_left == -1 && range_right == 0))) + log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -919,6 +940,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } + + if (is_wand) wire->set_bool_attribute("\\wand"); + if (is_wor) wire->set_bool_attribute("\\wor"); } break; @@ -963,8 +987,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) detectSignWidth(width_hint, sign_hint); is_signed = sign_hint; - if (type == AST_CONSTANT) - return RTLIL::SigSpec(bitsAsConst()); + if (type == AST_CONSTANT) { + if (is_unsized) { + return RTLIL::SigSpec(bitsAsUnsizedConst(width_hint)); + } else { + return RTLIL::SigSpec(bitsAsConst()); + } + } RTLIL::SigSpec sig = realAsConst(width_hint); log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); @@ -1566,6 +1595,37 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) delete always; } break; + case AST_TECALL: { + int sz = children.size(); + if (str == "$info") { + if (sz > 0) + log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_info(filename, linenum, "\n"); + } else if (str == "$warning") { + if (sz > 0) + log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_warning(filename, linenum, "\n"); + } else if (str == "$error") { + if (sz > 0) + log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str()); + else + log_file_error(filename, linenum, "\n"); + } else if (str == "$fatal") { + // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish() + // if no parameter is given, default value is 1 + // dollar_finish(sz ? children[0] : 1); + // perhaps create & use log_file_fatal() + if (sz > 0) + log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str()); + else + log_file_error(filename, linenum, "FATAL.\n"); + } else { + log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str()); + } + } break; + case AST_FCALL: { if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") { diff --git a/yosys/frontends/ilang/ilang_parser.y b/yosys/frontends/ilang/ilang_parser.y index 44c99906a..b4b9693da 100644 --- a/yosys/frontends/ilang/ilang_parser.y +++ b/yosys/frontends/ilang/ilang_parser.y @@ -282,14 +282,14 @@ proc_stmt: } case_body sync_list TOK_END EOL; switch_stmt: - attr_list TOK_SWITCH sigspec EOL { + TOK_SWITCH sigspec EOL { RTLIL::SwitchRule *rule = new RTLIL::SwitchRule; - rule->signal = *$3; + rule->signal = *$2; rule->attributes = attrbuf; switch_stack.back()->push_back(rule); attrbuf.clear(); - delete $3; - } switch_body TOK_END EOL; + delete $2; + } attr_list switch_body TOK_END EOL; attr_list: /* empty */ | @@ -298,9 +298,11 @@ attr_list: switch_body: switch_body TOK_CASE { RTLIL::CaseRule *rule = new RTLIL::CaseRule; + rule->attributes = attrbuf; switch_stack.back()->back()->cases.push_back(rule); switch_stack.push_back(&rule->switches); case_stack.push_back(rule); + attrbuf.clear(); } compare_list EOL case_body { switch_stack.pop_back(); case_stack.pop_back(); @@ -319,12 +321,15 @@ compare_list: /* empty */; case_body: + case_body attr_stmt | case_body switch_stmt | case_body assign_stmt | /* empty */; assign_stmt: TOK_ASSIGN sigspec sigspec EOL { + if (attrbuf.size() != 0) + rtlil_frontend_ilang_yyerror("dangling attribute"); case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3)); delete $2; delete $3; diff --git a/yosys/frontends/json/jsonparse.cc b/yosys/frontends/json/jsonparse.cc index 82361ea9b..f5ae8eb72 100644 --- a/yosys/frontends/json/jsonparse.cc +++ b/yosys/frontends/json/jsonparse.cc @@ -292,6 +292,18 @@ void json_import(Design *design, string &modname, JsonNode *node) if (port_wire == nullptr) port_wire = module->addWire(port_name, GetSize(port_bits_node->data_array)); + if (port_node->data_dict.count("upto") != 0) { + JsonNode *val = port_node->data_dict.at("upto"); + if (val->type == 'N') + port_wire->upto = val->data_number != 0; + } + + if (port_node->data_dict.count("offset") != 0) { + JsonNode *val = port_node->data_dict.at("offset"); + if (val->type == 'N') + port_wire->start_offset = val->data_number; + } + if (port_direction_node->data_string == "input") { port_wire->port_input = true; } else @@ -372,6 +384,18 @@ void json_import(Design *design, string &modname, JsonNode *node) if (wire == nullptr) wire = module->addWire(net_name, GetSize(bits_node->data_array)); + if (net_node->data_dict.count("upto") != 0) { + JsonNode *val = net_node->data_dict.at("upto"); + if (val->type == 'N') + wire->upto = val->data_number != 0; + } + + if (net_node->data_dict.count("offset") != 0) { + JsonNode *val = net_node->data_dict.at("offset"); + if (val->type == 'N') + wire->start_offset = val->data_number; + } + for (int i = 0; i < GetSize(bits_node->data_array); i++) { JsonNode *bitval_node = bits_node->data_array.at(i); diff --git a/yosys/frontends/verific/verific.cc b/yosys/frontends/verific/verific.cc index 21a1bbbbe..2bf99e58e 100644 --- a/yosys/frontends/verific/verific.cc +++ b/yosys/frontends/verific/verific.cc @@ -48,6 +48,14 @@ USING_YOSYS_NAMESPACE #include "VhdlUnits.h" #include "VeriLibrary.h" +#ifndef SYMBIOTIC_VERIFIC_API_VERSION +# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." +#endif + +#if SYMBIOTIC_VERIFIC_API_VERSION < 1 +# error "Please update your version of Symbiotic EDA flavored Verific." +#endif + #ifdef __clang__ #pragma clang diagnostic pop #endif @@ -2016,6 +2024,9 @@ struct VerificPass : public Pass { // WARNING: instantiating unknown module 'XYZ' (VERI-1063) Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + // https://github.com/YosysHQ/yosys/issues/1055 + RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + #ifndef DB_PRESERVE_INITIAL_VALUE # warning Verific was built without DB_PRESERVE_INITIAL_VALUE. #endif diff --git a/yosys/frontends/verilog/const2ast.cc b/yosys/frontends/verilog/const2ast.cc index 7848c626d..f6a17b242 100644 --- a/yosys/frontends/verilog/const2ast.cc +++ b/yosys/frontends/verilog/const2ast.cc @@ -71,7 +71,7 @@ static int my_ilog2(int x) } // parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?') -static void my_strtobin(std::vector &data, const char *str, int len_in_bits, int base, char case_type) +static void my_strtobin(std::vector &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized) { // all digits in string (MSB at index 0) std::vector digits; @@ -129,6 +129,9 @@ static void my_strtobin(std::vector &data, const char *str, int le return; } + if (is_unsized && (len > len_in_bits)) + log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len); + for (len = len - 1; len >= 0; len--) if (data[len] == RTLIL::S1) break; @@ -150,7 +153,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { if (warn_z) { AstNode *ret = const2ast(code, case_type); - if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) + if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num()); return ret; @@ -186,7 +189,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn // Simple base-10 integer if (*endptr == 0) { std::vector data; - my_strtobin(data, str, -1, 10, case_type); + my_strtobin(data, str, -1, 10, case_type, false); if (data.back() == RTLIL::S1) data.push_back(RTLIL::S0); return AstNode::mkconst_bits(data, true); @@ -201,6 +204,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { std::vector data; bool is_signed = false; + bool is_unsized = len_in_bits < 0; if (*(endptr+1) == 's') { is_signed = true; endptr++; @@ -209,28 +213,34 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { case 'b': case 'B': - my_strtobin(data, endptr+2, len_in_bits, 2, case_type); + my_strtobin(data, endptr+2, len_in_bits, 2, case_type, is_unsized); break; case 'o': case 'O': - my_strtobin(data, endptr+2, len_in_bits, 8, case_type); + my_strtobin(data, endptr+2, len_in_bits, 8, case_type, is_unsized); break; case 'd': case 'D': - my_strtobin(data, endptr+2, len_in_bits, 10, case_type); + my_strtobin(data, endptr+2, len_in_bits, 10, case_type, is_unsized); break; case 'h': case 'H': - my_strtobin(data, endptr+2, len_in_bits, 16, case_type); + my_strtobin(data, endptr+2, len_in_bits, 16, case_type, is_unsized); break; default: - return NULL; + char next_char = char(tolower(*(endptr+1))); + if (next_char == '0' || next_char == '1' || next_char == 'x' || next_char == 'z') { + is_unsized = true; + my_strtobin(data, endptr+1, 1, 2, case_type, is_unsized); + } else { + return NULL; + } } if (len_in_bits < 0) { if (is_signed && data.back() == RTLIL::S1) data.push_back(RTLIL::S0); } - return AstNode::mkconst_bits(data, is_signed); + return AstNode::mkconst_bits(data, is_signed, is_unsized); } return NULL; diff --git a/yosys/frontends/verilog/verilog_frontend.cc b/yosys/frontends/verilog/verilog_frontend.cc index 01e589efb..0e2bead6f 100644 --- a/yosys/frontends/verilog/verilog_frontend.cc +++ b/yosys/frontends/verilog/verilog_frontend.cc @@ -168,6 +168,9 @@ struct VerilogFrontend : public Frontend { log(" -icells\n"); log(" interpret cell types starting with '$' as internal cell types\n"); log("\n"); + log(" -pwires\n"); + log(" add a wire for each module parameter\n"); + log("\n"); log(" -nooverwrite\n"); log(" ignore re-definitions of modules. (the default behavior is to\n"); log(" create an error message if the existing module is not a black box\n"); @@ -228,6 +231,7 @@ struct VerilogFrontend : public Frontend { bool flag_nodpi = false; bool flag_noopt = false; bool flag_icells = false; + bool flag_pwires = false; bool flag_nooverwrite = false; bool flag_overwrite = false; bool flag_defer = false; @@ -368,6 +372,10 @@ struct VerilogFrontend : public Frontend { flag_icells = true; continue; } + if (arg == "-pwires") { + flag_pwires = true; + continue; + } if (arg == "-ignore_redef" || arg == "-nooverwrite") { flag_nooverwrite = true; flag_overwrite = false; @@ -458,7 +466,7 @@ struct VerilogFrontend : public Frontend { error_on_dpi_function(current_ast); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, - flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); + flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; diff --git a/yosys/frontends/verilog/verilog_lexer.l b/yosys/frontends/verilog/verilog_lexer.l index 142d05d45..951d9c66f 100644 --- a/yosys/frontends/verilog/verilog_lexer.l +++ b/yosys/frontends/verilog/verilog_lexer.l @@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some global state.. its a mess) */ [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] { + if (!strcmp(yytext, "default")) + return TOK_DEFAULT; frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); return TOK_SVA_LABEL; } @@ -218,6 +220,8 @@ YOSYS_NAMESPACE_END "output" { return TOK_OUTPUT; } "inout" { return TOK_INOUT; } "wire" { return TOK_WIRE; } +"wor" { return TOK_WOR; } +"wand" { return TOK_WAND; } "reg" { return TOK_REG; } "integer" { return TOK_INTEGER; } "signed" { return TOK_SIGNED; } @@ -232,7 +236,7 @@ YOSYS_NAMESPACE_END return TOK_CONSTVAL; } -[0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ { +[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ { frontend_verilog_yylval.string = new std::string(yytext); return TOK_CONSTVAL; } @@ -309,6 +313,11 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } +"$"(info|warning|error|fatal) { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_MSG_TASKS; +} + "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } diff --git a/yosys/frontends/verilog/verilog_parser.y b/yosys/frontends/verilog/verilog_parser.y index 132468f0c..0fec445fa 100644 --- a/yosys/frontends/verilog/verilog_parser.y +++ b/yosys/frontends/verilog/verilog_parser.y @@ -133,13 +133,13 @@ struct specify_rise_fall { } %token TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE -%token TOK_SVA_LABEL TOK_SPECIFY_OPER +%token TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_MSG_TASKS %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR -%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC +%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC @@ -319,15 +319,17 @@ module_para_list: single_module_para: /* empty */ | - TOK_PARAMETER { + attr TOK_PARAMETER { if (astbuf1) delete astbuf1; astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + append_attr(astbuf1, $1); } param_signed param_integer param_range single_param_decl | - TOK_LOCALPARAM { + attr TOK_LOCALPARAM { if (astbuf1) delete astbuf1; astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + append_attr(astbuf1, $1); } param_signed param_integer param_range single_param_decl | single_param_decl; @@ -345,7 +347,13 @@ module_arg_opt_assignment: if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { AstNode *wire = new AstNode(AST_IDENTIFIER); wire->str = ast_stack.back()->children.back()->str; - if (ast_stack.back()->children.back()->is_reg) + if (ast_stack.back()->children.back()->is_input) { + AstNode *n = ast_stack.back()->children.back(); + if (n->attributes.count("\\defaultvalue")) + delete n->attributes.at("\\defaultvalue"); + n->attributes["\\defaultvalue"] = $2; + } else + if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic) ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); else ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); @@ -485,6 +493,12 @@ wire_type_token_io: wire_type_token: TOK_WIRE { } | + TOK_WOR { + astbuf3->is_wor = true; + } | + TOK_WAND { + astbuf3->is_wand = true; + } | TOK_REG { astbuf3->is_reg = true; } | @@ -503,6 +517,7 @@ wire_type_token: TOK_GENVAR { astbuf3->type = AST_GENVAR; astbuf3->is_reg = true; + astbuf3->is_signed = true; astbuf3->range_left = 31; astbuf3->range_right = 0; } | @@ -1006,13 +1021,8 @@ list_of_specparam_assignments: specparam_assignment: ignspec_id '=' constant_mintypmax_expression ; -/* -pulsestyle_declaration : - ; - -showcancelled_declaration : - ; -*/ +ignspec_opt_cond: + TOK_IF '(' ignspec_expr ')' | /* empty */; path_declaration : simple_path_declaration ';' @@ -1021,8 +1031,8 @@ path_declaration : ; simple_path_declaration : - parallel_path_description '=' path_delay_value | - full_path_description '=' path_delay_value + ignspec_opt_cond parallel_path_description '=' path_delay_value | + ignspec_opt_cond full_path_description '=' path_delay_value ; path_delay_value : @@ -1032,32 +1042,20 @@ path_delay_value : ; list_of_path_delay_extra_expressions : -/* - t_path_delay_expression - | trise_path_delay_expression ',' tfall_path_delay_expression - | trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression - | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ',' - tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression - | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ',' - tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ',' - t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' - tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression -*/ - ',' path_delay_expression - | ',' path_delay_expression ',' path_delay_expression - | ',' path_delay_expression ',' path_delay_expression ',' - path_delay_expression ',' path_delay_expression ',' path_delay_expression - | ',' path_delay_expression ',' path_delay_expression ',' - path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' - path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' - path_delay_expression ',' path_delay_expression ',' path_delay_expression - ; + ',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions; + +specify_edge_identifier : + TOK_POSEDGE | TOK_NEGEDGE ; parallel_path_description : - '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; + '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' | + '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' | + '(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ; full_path_description : - '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ; + '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' | + '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' | + '(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ; // This was broken into 2 rules to solve shift/reduce conflicts list_of_path_inputs : @@ -1097,56 +1095,6 @@ system_timing_args : system_timing_arg | system_timing_args ',' system_timing_arg ; -/* -t_path_delay_expression : - path_delay_expression; - -trise_path_delay_expression : - path_delay_expression; - -tfall_path_delay_expression : - path_delay_expression; - -tz_path_delay_expression : - path_delay_expression; - -t01_path_delay_expression : - path_delay_expression; - -t10_path_delay_expression : - path_delay_expression; - -t0z_path_delay_expression : - path_delay_expression; - -tz1_path_delay_expression : - path_delay_expression; - -t1z_path_delay_expression : - path_delay_expression; - -tz0_path_delay_expression : - path_delay_expression; - -t0x_path_delay_expression : - path_delay_expression; - -tx1_path_delay_expression : - path_delay_expression; - -t1x_path_delay_expression : - path_delay_expression; - -tx0_path_delay_expression : - path_delay_expression; - -txz_path_delay_expression : - path_delay_expression; - -tzx_path_delay_expression : - path_delay_expression; -*/ - path_delay_expression : ignspec_constant_expression; @@ -1205,6 +1153,7 @@ param_decl: attr TOK_PARAMETER { astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + append_attr(astbuf1, $1); } param_signed param_integer param_real param_range param_decl_list ';' { delete astbuf1; }; @@ -1213,6 +1162,7 @@ localparam_decl: attr TOK_LOCALPARAM { astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); + append_attr(astbuf1, $1); } param_signed param_integer param_real param_range param_decl_list ';' { delete astbuf1; }; @@ -1354,7 +1304,12 @@ wire_name_and_opt_assign: wire_name '=' expr { AstNode *wire = new AstNode(AST_IDENTIFIER); wire->str = ast_stack.back()->children.back()->str; - if (astbuf1->is_reg) + if (astbuf1->is_input) { + if (astbuf1->attributes.count("\\defaultvalue")) + delete astbuf1->attributes.at("\\defaultvalue"); + astbuf1->attributes["\\defaultvalue"] = $3; + } else + if (astbuf1->is_reg || astbuf1->is_logic) ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3)))); else ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3)); @@ -1379,7 +1334,13 @@ wire_name: node->children.push_back(rng); } node->type = AST_MEMORY; - node->children.push_back($2); + auto *rangeNode = $2; + if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { + // SV array size [n], rewrite as [n-1:0] + rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); + rangeNode->children.push_back(AstNode::mkconst_int(0, false)); + } + node->children.push_back(rangeNode); } if (current_function_or_task == NULL) { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { @@ -1526,27 +1487,40 @@ cell_port_list_rules: cell_port | cell_port_list_rules ',' cell_port; cell_port: - /* empty */ { + attr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); + free_attr($1); } | - expr { + attr expr { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); - node->children.push_back($1); + node->children.push_back($2); + free_attr($1); } | - '.' TOK_ID '(' expr ')' { + attr '.' TOK_ID '(' expr ')' { AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; + node->str = *$3; astbuf2->children.push_back(node); - node->children.push_back($4); - delete $2; + node->children.push_back($5); + delete $3; + free_attr($1); } | - '.' TOK_ID '(' ')' { + attr '.' TOK_ID '(' ')' { AstNode *node = new AstNode(AST_ARGUMENT); - node->str = *$2; + node->str = *$3; astbuf2->children.push_back(node); - delete $2; + delete $3; + free_attr($1); + } | + attr '.' TOK_ID { + AstNode *node = new AstNode(AST_ARGUMENT); + node->str = *$3; + astbuf2->children.push_back(node); + node->children.push_back(new AstNode(AST_IDENTIFIER)); + node->children.back()->str = *$3; + delete $3; + free_attr($1); }; always_stmt: @@ -1862,6 +1836,16 @@ behavioral_stmt: } opt_arg_list ';'{ ast_stack.pop_back(); } | + TOK_MSG_TASKS attr { + AstNode *node = new AstNode(AST_TCALL); + node->str = *$1; + delete $1; + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + append_attr(node, $2); + } opt_arg_list ';'{ + ast_stack.pop_back(); + } | attr TOK_BEGIN opt_label { AstNode *node = new AstNode(AST_BLOCK); ast_stack.back()->children.push_back(node); @@ -2157,6 +2141,15 @@ gen_stmt: if ($6 != NULL) delete $6; ast_stack.pop_back(); + } | + TOK_MSG_TASKS { + AstNode *node = new AstNode(AST_TECALL); + node->str = *$1; + delete $1; + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } opt_arg_list ';'{ + ast_stack.pop_back(); }; gen_stmt_block: diff --git a/yosys/kernel/log.cc b/yosys/kernel/log.cc index 9a9104e26..a7820950c 100644 --- a/yosys/kernel/log.cc +++ b/yosys/kernel/log.cc @@ -230,6 +230,9 @@ static void logv_warning_with_prefix(const char *prefix, } else { + int bak_log_make_debug = log_make_debug; + log_make_debug = 0; + for (auto &re : log_werror_regexes) if (std::regex_search(message, re)) log_error("%s", message.c_str()); @@ -254,6 +257,7 @@ static void logv_warning_with_prefix(const char *prefix, } log_warnings_count++; + log_make_debug = bak_log_make_debug; } } @@ -273,11 +277,22 @@ void log_file_warning(const std::string &filename, int lineno, va_list ap; va_start(ap, format); std::string prefix = stringf("%s:%d: Warning: ", - filename.c_str(), lineno); + filename.c_str(), lineno); logv_warning_with_prefix(prefix.c_str(), format, ap); va_end(ap); } +void log_file_info(const std::string &filename, int lineno, + const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string fmt = stringf("%s:%d: Info: %s", + filename.c_str(), lineno, format); + logv(fmt.c_str(), ap); + va_end(ap); +} + YS_ATTRIBUTE(noreturn) static void logv_error_with_prefix(const char *prefix, const char *format, va_list ap) @@ -285,6 +300,9 @@ static void logv_error_with_prefix(const char *prefix, #ifdef EMSCRIPTEN auto backup_log_files = log_files; #endif + int bak_log_make_debug = log_make_debug; + log_make_debug = 0; + log_suppressed(); if (log_errfile != NULL) log_files.push_back(log_errfile); @@ -298,6 +316,8 @@ static void logv_error_with_prefix(const char *prefix, log("%s%s", prefix, log_last_error.c_str()); log_flush(); + log_make_debug = bak_log_make_debug; + if (log_error_atexit) log_error_atexit(); diff --git a/yosys/kernel/log.h b/yosys/kernel/log.h index e6afae716..3e1facae8 100644 --- a/yosys/kernel/log.h +++ b/yosys/kernel/log.h @@ -80,6 +80,7 @@ void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); // Log with filename to report a problem in a source file. void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); +void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); diff --git a/yosys/kernel/register.cc b/yosys/kernel/register.cc index 71eb6b187..26da96b95 100644 --- a/yosys/kernel/register.cc +++ b/yosys/kernel/register.cc @@ -545,6 +545,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectoropen(filename.c_str(), std::ofstream::trunc); yosys_output_files.insert(filename); diff --git a/yosys/kernel/rtlil.cc b/yosys/kernel/rtlil.cc index 790ba52a3..a09f4a0d1 100644 --- a/yosys/kernel/rtlil.cc +++ b/yosys/kernel/rtlil.cc @@ -1381,7 +1381,34 @@ void RTLIL::Module::check() for (auto &it : processes) { log_assert(it.first == it.second->name); log_assert(!it.first.empty()); - // FIXME: More checks here.. + log_assert(it.second->root_case.compare.empty()); + std::vector all_cases = {&it.second->root_case}; + for (size_t i = 0; i < all_cases.size(); i++) { + for (auto &switch_it : all_cases[i]->switches) { + for (auto &case_it : switch_it->cases) { + for (auto &compare_it : case_it->compare) { + log_assert(switch_it->signal.size() == compare_it.size()); + } + all_cases.push_back(case_it); + } + } + } + for (auto &sync_it : it.second->syncs) { + switch (sync_it->type) { + case SyncType::ST0: + case SyncType::ST1: + case SyncType::STp: + case SyncType::STn: + case SyncType::STe: + log_assert(!sync_it->signal.empty()); + break; + case SyncType::STa: + case SyncType::STg: + case SyncType::STi: + log_assert(sync_it->signal.empty()); + break; + } + } } for (auto &it : connections_) { diff --git a/yosys/kernel/rtlil.h b/yosys/kernel/rtlil.h index 81ca93dce..7b7367fba 100644 --- a/yosys/kernel/rtlil.h +++ b/yosys/kernel/rtlil.h @@ -601,6 +601,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default; RTLIL::SigChunk extract(int offset, int length) const; + inline int size() const { return width; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; @@ -1314,7 +1315,7 @@ public: #endif }; -struct RTLIL::CaseRule +struct RTLIL::CaseRule : public RTLIL::AttrObject { std::vector compare; std::vector actions; diff --git a/yosys/kernel/yosys.cc b/yosys/kernel/yosys.cc index 377572fc2..69a141768 100644 --- a/yosys/kernel/yosys.cc +++ b/yosys/kernel/yosys.cc @@ -129,7 +129,7 @@ void yosys_banner() log(" | |\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); log(" | |\n"); - log(" | Copyright (C) 2012 - 2018 Clifford Wolf |\n"); + log(" | Copyright (C) 2012 - 2019 Clifford Wolf |\n"); log(" | |\n"); log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); log(" | purpose with or without fee is hereby granted, provided that the above |\n"); @@ -651,6 +651,10 @@ void rewrite_filename(std::string &filename) filename = filename.substr(1, GetSize(filename)-2); if (filename.substr(0, 2) == "+/") filename = proc_share_dirname() + filename.substr(2); +#ifndef _WIN32 + if (filename.substr(0, 2) == "~/") + filename = filename.replace(0, 1, getenv("HOME")); +#endif } #ifdef YOSYS_ENABLE_TCL diff --git a/yosys/kernel/yosys.h b/yosys/kernel/yosys.h index c7b671724..730efe825 100644 --- a/yosys/kernel/yosys.h +++ b/yosys/kernel/yosys.h @@ -87,6 +87,10 @@ extern int Tcl_EvalFile(Tcl_Interp *interp, const char *fileName); extern void Tcl_Finalize(void); extern int Tcl_GetCommandInfo(Tcl_Interp *interp, const char *cmdName, Tcl_CmdInfo *infoPtr); extern const char *Tcl_GetStringResult(Tcl_Interp *interp); +extern Tcl_Obj *Tcl_NewStringObj(const char *bytes, int length); +extern Tcl_Obj *Tcl_NewIntObj(int intValue); +extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]); +extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags); # endif #endif diff --git a/yosys/manual/CHAPTER_Overview.tex b/yosys/manual/CHAPTER_Overview.tex index 2feb0f1cb..3009bf2c0 100644 --- a/yosys/manual/CHAPTER_Overview.tex +++ b/yosys/manual/CHAPTER_Overview.tex @@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition -(signal and edge-type) and zero or more assignments (RTLIL::SigSig). +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or +more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a @@ -350,6 +351,18 @@ and this bit is a one (the second ``1'').} for {\tt \textbackslash{}reset == 1} sets {\tt \$0\textbackslash{}q[0:0]} to the value of {\tt \textbackslash{}d} if {\tt \textbackslash{}enable} is active (lines $6 \dots 11$). +A case can specify zero or more compare values that will determine whether it matches. Each of the compare values +must be the exact same width as the control signal. When more than one compare value is specified, the case matches +if any of them matches the control signal; when zero compare values are specified, the case always matches (i.e. +it is the default case). + +A switch prioritizes cases from first to last: multiple cases can match, but only the first matched case becomes +active. This normally synthesizes to a priority encoder. The {\tt parallel\_case} attribute allows passes to assume +that no more than one case will match, and {\tt full\_case} attribute allows passes to assume that exactly one +case will match; if these invariants are ever dynamically violated, the behavior is undefined. These attributes +are useful when an invariant invisible to the synthesizer causes the control signal to never take certain +bit patterns. + The lines $13 \dots 16$ then cause {\tt \textbackslash{}q} to be updated whenever there is a positive clock edge on {\tt \textbackslash{}clock} or {\tt \textbackslash{}reset}. diff --git a/yosys/misc/launcher.c b/yosys/misc/launcher.c index 157d68cf3..e0d8208f1 100644 --- a/yosys/misc/launcher.c +++ b/yosys/misc/launcher.c @@ -61,6 +61,7 @@ SOFTWARE. */ #include #include #include +#include int child_pid=0; @@ -338,7 +339,7 @@ int run(int argc, char **argv, int is_gui) { if (is_gui) { /* Use exec, we don't need to wait for the GUI to finish */ - execv(ptr, (const char * const *)(newargs)); + execv(ptr, (char * const *)(newargs)); return fail("Could not exec %s", ptr); /* shouldn't get here! */ } diff --git a/yosys/misc/py_wrap_generator.py b/yosys/misc/py_wrap_generator.py index 09f934040..66d661fa1 100644 --- a/yosys/misc/py_wrap_generator.py +++ b/yosys/misc/py_wrap_generator.py @@ -779,6 +779,9 @@ class WClass: #if self.link_type != link_types.pointer: text += "\n\t\tstatic " + self.name + "* get_py_obj(" + long_name + "* ref)\n\t\t{" + text += "\n\t\t\tif(ref == nullptr){" + text += "\n\t\t\t\tthrow std::runtime_error(\"" + self.name + " does not exist.\");" + text += "\n\t\t\t}" text += "\n\t\t\t" + self.name + "* ret = (" + self.name + "*)malloc(sizeof(" + self.name + "));" if self.link_type == link_types.pointer: text += "\n\t\t\tret->ref_obj = ref;" @@ -2026,7 +2029,6 @@ def gen_wrappers(filename, debug_level_ = 0): #include #include #include -#include USING_YOSYS_NAMESPACE @@ -2060,7 +2062,6 @@ namespace YOSYS_PYTHON { Yosys::log_streams.push_back(&std::cout); Yosys::log_error_stderr = true; Yosys::yosys_setup(); - Yosys::yosys_banner(); } } diff --git a/yosys/passes/cmds/blackbox.cc b/yosys/passes/cmds/blackbox.cc index 6094f8f16..d09ed872e 100644 --- a/yosys/passes/cmds/blackbox.cc +++ b/yosys/passes/cmds/blackbox.cc @@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct BlackboxPass : public Pass { - BlackboxPass() : Pass("blackbox", "change type of cells in the design") { } + BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/yosys/passes/cmds/setundef.cc b/yosys/passes/cmds/setundef.cc index f6949c820..3eedc86b8 100644 --- a/yosys/passes/cmds/setundef.cc +++ b/yosys/passes/cmds/setundef.cc @@ -393,44 +393,112 @@ struct SetundefPass : public Pass { ffbits.insert(bit); } - for (auto wire : module->wires()) + auto process_initwires = [&]() { - if (!wire->attributes.count("\\init")) - continue; + dict wire_weights; - for (auto bit : sigmap(wire)) - ffbits.erase(bit); - - initwires.insert(wire); - } - - for (int wire_types = 0; wire_types < 2; wire_types++) - for (auto wire : module->wires()) + for (auto wire : initwires) { - if (wire->name[0] == (wire_types ? '\\' : '$')) - next_wire: - continue; + int weight = 0; for (auto bit : sigmap(wire)) - if (!ffbits.count(bit)) - goto next_wire; + weight += ffbits.count(bit) ? +1 : -1; - for (auto bit : sigmap(wire)) - ffbits.erase(bit); - - initwires.insert(wire); + wire_weights[wire] = weight; } - for (auto wire : initwires) - { - Const &initval = wire->attributes["\\init"]; + initwires.sort([&](Wire *a, Wire *b) { return wire_weights.at(a) > wire_weights.at(b); }); - for (int i = 0; i < GetSize(wire); i++) - if (GetSize(initval) <= i) - initval.bits.push_back(worker.next_bit()); - else if (initval.bits[i] == State::Sx) - initval.bits[i] = worker.next_bit(); + for (auto wire : initwires) + { + Const &initval = wire->attributes["\\init"]; + initval.bits.resize(GetSize(wire), State::Sx); + + for (int i = 0; i < GetSize(wire); i++) { + SigBit bit = sigmap(SigBit(wire, i)); + if (initval[i] == State::Sx && ffbits.count(bit)) { + initval[i] = worker.next_bit(); + ffbits.erase(bit); + } + } + + if (initval.is_fully_undef()) + wire->attributes.erase("\\init"); + } + + initwires.clear(); + }; + + for (int wire_types = 0; wire_types < 2; wire_types++) + { + // prioritize wires that already have an init attribute + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + if (!wire->attributes.count("\\init")) + continue; + + Const &initval = wire->attributes["\\init"]; + initval.bits.resize(GetSize(wire), State::Sx); + + if (initval.is_fully_undef()) { + wire->attributes.erase("\\init"); + continue; + } + + for (int i = 0; i < GetSize(wire); i++) + if (initval[i] != State::Sx) + ffbits.erase(sigmap(SigBit(wire, i))); + + initwires.insert(wire); + } + + process_initwires(); + } + + // next consider wires that completely contain bits to be initialized + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + for (auto bit : sigmap(wire)) + if (!ffbits.count(bit)) + goto next_wire; + + initwires.insert(wire); + + next_wire: + continue; + } + + process_initwires(); + } + + // finally use whatever wire we can find. + if (!ffbits.empty()) + { + for (auto wire : module->wires()) + { + if (wire->name[0] == (wire_types ? '\\' : '$')) + continue; + + for (auto bit : sigmap(wire)) + if (ffbits.count(bit)) + initwires.insert(wire); + } + + process_initwires(); + } } + + log_assert(ffbits.empty()); } module->rewrite_sigspecs(worker); diff --git a/yosys/passes/cmds/stat.cc b/yosys/passes/cmds/stat.cc index d22685b62..27c5fb60c 100644 --- a/yosys/passes/cmds/stat.cc +++ b/yosys/passes/cmds/stat.cc @@ -285,8 +285,8 @@ struct StatPass : public Pass { log(" use cell area information from the provided liberty file\n"); log("\n"); log(" -tech \n"); - log(" print area estemate for the specified technology. Corrently supported\n"); - log(" calues for : xilinx\n"); + log(" print area estemate for the specified technology. Currently supported\n"); + log(" values for : xilinx\n"); log("\n"); log(" -width\n"); log(" annotate internal cell types with their word width.\n"); diff --git a/yosys/passes/cmds/tee.cc b/yosys/passes/cmds/tee.cc index ee96ace86..1a44bdaec 100644 --- a/yosys/passes/cmds/tee.cc +++ b/yosys/passes/cmds/tee.cc @@ -52,7 +52,9 @@ struct TeePass : public Pass { void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector backup_log_files, files_to_close; + std::vector backup_log_streams; int backup_log_verbose_level = log_verbose_level; + backup_log_streams = log_streams; backup_log_files = log_files; size_t argidx; @@ -60,6 +62,7 @@ struct TeePass : public Pass { { if (args[argidx] == "-q" && files_to_close.empty()) { log_files.clear(); + log_streams.clear(); continue; } if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { @@ -89,6 +92,7 @@ struct TeePass : public Pass { for (auto cf : files_to_close) fclose(cf); log_files = backup_log_files; + log_streams = backup_log_streams; throw; } @@ -97,6 +101,7 @@ struct TeePass : public Pass { log_verbose_level = backup_log_verbose_level; log_files = backup_log_files; + log_streams = backup_log_streams; } } TeePass; diff --git a/yosys/passes/cmds/write_file.cc b/yosys/passes/cmds/write_file.cc index 9613b462b..64a762d7c 100644 --- a/yosys/passes/cmds/write_file.cc +++ b/yosys/passes/cmds/write_file.cc @@ -62,7 +62,7 @@ struct WriteFileFrontend : public Frontend { if (argidx < args.size() && args[argidx].rfind("-", 0) != 0) output_filename = args[argidx++]; else - log_cmd_error("Missing putput filename.\n"); + log_cmd_error("Missing output filename.\n"); extra_args(f, filename, args, argidx); diff --git a/yosys/passes/hierarchy/hierarchy.cc b/yosys/passes/hierarchy/hierarchy.cc index 72bc2e133..213437c01 100644 --- a/yosys/passes/hierarchy/hierarchy.cc +++ b/yosys/passes/hierarchy/hierarchy.cc @@ -562,7 +562,8 @@ struct HierarchyPass : public Pass { log("In parametric designs, a module might exists in several variations with\n"); log("different parameter values. This pass looks at all modules in the current\n"); log("design an re-runs the language frontends for the parametric modules as\n"); - log("needed.\n"); + log("needed. It also resolves assignments to wired logic data types (wand/wor),\n"); + log("resolves positional module parameters, unroll array instances, and more.\n"); log("\n"); log(" -check\n"); log(" also check the design hierarchy. this generates an error when\n"); @@ -590,6 +591,9 @@ struct HierarchyPass : public Pass { log(" module instances when the width does not match the module port. This\n"); log(" option disables this behavior.\n"); log("\n"); + log(" -nodefaults\n"); + log(" do not resolve input port default values\n"); + log("\n"); log(" -nokeep_asserts\n"); log(" per default this pass sets the \"keep\" attribute on all modules\n"); log(" that directly or indirectly contain one or more formal properties.\n"); @@ -644,6 +648,7 @@ struct HierarchyPass : public Pass { bool generate_mode = false; bool keep_positionals = false; bool keep_portwidths = false; + bool nodefaults = false; bool nokeep_asserts = false; std::vector generate_cells; std::vector generate_ports; @@ -711,6 +716,10 @@ struct HierarchyPass : public Pass { keep_portwidths = true; continue; } + if (args[argidx] == "-nodefaults") { + nodefaults = true; + continue; + } if (args[argidx] == "-nokeep_asserts") { nokeep_asserts = true; continue; @@ -939,66 +948,212 @@ struct HierarchyPass : public Pass { } } + if (!nodefaults) + { + dict> defaults_db; + + for (auto module : design->modules()) + for (auto wire : module->wires()) + if (wire->port_input && wire->attributes.count("\\defaultvalue")) + defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); + + for (auto module : design->modules()) + for (auto cell : module->cells()) + { + if (defaults_db.count(cell->type) == 0) + continue; + + if (keep_positionals) { + bool found_positionals = false; + for (auto &conn : cell->connections()) + if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') + found_positionals = true; + if (found_positionals) + continue; + } + + for (auto &it : defaults_db.at(cell->type)) + if (!cell->hasPort(it.first)) + cell->setPort(it.first, it.second); + } + } + std::set blackbox_derivatives; std::vector design_modules = design->modules(); for (auto module : design_modules) - for (auto cell : module->cells()) { - Module *m = design->module(cell->type); + pool wand_wor_index; + dict wand_map, wor_map; + vector new_connections; - if (m == nullptr) - continue; - - if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { - IdString new_m_name = m->derive(design, cell->parameters, true); - if (new_m_name.empty()) - continue; - if (new_m_name != m->name) { - m = design->module(new_m_name); - blackbox_derivatives.insert(m); + for (auto wire : module->wires()) + { + if (wire->get_bool_attribute("\\wand")) { + wand_map[wire] = SigSpec(); + wand_wor_index.insert(wire); + } + if (wire->get_bool_attribute("\\wor")) { + wor_map[wire] = SigSpec(); + wand_wor_index.insert(wire); } } - for (auto &conn : cell->connections()) + for (auto &conn : module->connections()) { - Wire *w = m->wire(conn.first); + SigSig new_conn; + int cursor = 0; - if (w == nullptr || w->port_id == 0) - continue; - - if (GetSize(conn.second) == 0) - continue; - - SigSpec sig = conn.second; - - if (!keep_portwidths && GetSize(w) != GetSize(conn.second)) + for (auto c : conn.first.chunks()) { - if (GetSize(w) < GetSize(conn.second)) - { - int n = GetSize(conn.second) - GetSize(w); - if (!w->port_input && w->port_output) - module->connect(sig.extract(GetSize(w), n), Const(0, n)); - sig.remove(GetSize(w), n); + Wire *w = c.wire; + SigSpec rhs = conn.second.extract(cursor, GetSize(c)); + + if (wand_wor_index.count(w) == 0) { + new_conn.first.append(c); + new_conn.second.append(rhs); + } else { + if (wand_map.count(w)) { + SigSpec sig = SigSpec(State::S1, GetSize(w)); + sig.replace(c.offset, rhs); + wand_map.at(w).append(sig); + } else { + SigSpec sig = SigSpec(State::S0, GetSize(w)); + sig.replace(c.offset, rhs); + wor_map.at(w).append(sig); + } } - else + cursor += GetSize(c); + } + new_connections.push_back(new_conn); + } + module->new_connections(new_connections); + + for (auto cell : module->cells()) + { + if (!cell->known()) + continue; + + for (auto &conn : cell->connections()) + { + if (!cell->output(conn.first)) + continue; + + SigSpec new_sig; + bool update_port = false; + + for (auto c : conn.second.chunks()) { - int n = GetSize(w) - GetSize(conn.second); - if (w->port_input && !w->port_output) - sig.append(Const(0, n)); - else - sig.append(module->addWire(NEW_ID, n)); + Wire *w = c.wire; + + if (wand_wor_index.count(w) == 0) { + new_sig.append(c); + continue; + } + + Wire *t = module->addWire(NEW_ID, GetSize(c)); + new_sig.append(t); + update_port = true; + + if (wand_map.count(w)) { + SigSpec sig = SigSpec(State::S1, GetSize(w)); + sig.replace(c.offset, t); + wand_map.at(w).append(sig); + } else { + SigSpec sig = SigSpec(State::S0, GetSize(w)); + sig.replace(c.offset, t); + wor_map.at(w).append(sig); + } } - if (!conn.second.is_fully_const() || !w->port_input || w->port_output) - log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell), - log_id(conn.first), GetSize(conn.second), GetSize(sig)); - cell->setPort(conn.first, sig); + if (update_port) + cell->setPort(conn.first, new_sig); + } + } + + for (auto w : wand_wor_index) + { + bool wand = wand_map.count(w); + SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w); + + if (GetSize(sigs) == 0) + continue; + + if (GetSize(w) == 1) { + if (wand) + module->addReduceAnd(NEW_ID, sigs, w); + else + module->addReduceOr(NEW_ID, sigs, w); + continue; } - if (w->port_output && !w->port_input && sig.has_const()) - log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", - log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig)); + SigSpec s = sigs.extract(0, GetSize(w)); + for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) { + if (wand) + s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w))); + else + s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w))); + } + module->connect(w, s); + } + + for (auto cell : module->cells()) + { + Module *m = design->module(cell->type); + + if (m == nullptr) + continue; + + if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { + IdString new_m_name = m->derive(design, cell->parameters, true); + if (new_m_name.empty()) + continue; + if (new_m_name != m->name) { + m = design->module(new_m_name); + blackbox_derivatives.insert(m); + } + } + + for (auto &conn : cell->connections()) + { + Wire *w = m->wire(conn.first); + + if (w == nullptr || w->port_id == 0) + continue; + + if (GetSize(conn.second) == 0) + continue; + + SigSpec sig = conn.second; + + if (!keep_portwidths && GetSize(w) != GetSize(conn.second)) + { + if (GetSize(w) < GetSize(conn.second)) + { + int n = GetSize(conn.second) - GetSize(w); + if (!w->port_input && w->port_output) + module->connect(sig.extract(GetSize(w), n), Const(0, n)); + sig.remove(GetSize(w), n); + } + else + { + int n = GetSize(w) - GetSize(conn.second); + if (w->port_input && !w->port_output) + sig.append(Const(0, n)); + else + sig.append(module->addWire(NEW_ID, n)); + } + + if (!conn.second.is_fully_const() || !w->port_input || w->port_output) + log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell), + log_id(conn.first), GetSize(conn.second), GetSize(sig)); + cell->setPort(conn.first, sig); + } + + if (w->port_output && !w->port_input && sig.has_const()) + log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", + log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig)); + } } } diff --git a/yosys/passes/memory/memory_dff.cc b/yosys/passes/memory/memory_dff.cc index 220d29295..32b97f27a 100644 --- a/yosys/passes/memory/memory_dff.cc +++ b/yosys/passes/memory/memory_dff.cc @@ -17,6 +17,7 @@ * */ +#include #include "kernel/yosys.h" #include "kernel/sigtools.h" @@ -182,20 +183,27 @@ struct MemoryDffWorker if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)) { - bool enable_invert = mux_cells_a.count(sig_data) != 0; - Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); - SigSpec check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); + RTLIL::SigSpec en; + std::vector check_q; + + do { + bool enable_invert = mux_cells_a.count(sig_data) != 0; + Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); + check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"))); + sig_data = sigmap(mux->getPort("\\Y")); + en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); - sig_data = sigmap(mux->getPort("\\Y")); for (auto bit : sig_data) if (sigbit_users_count[bit] > 1) goto skip_ff_after_read_merging; - if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q) + if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && + std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; })) { disconnect_dff(sig_data); cell->setPort("\\CLK", clk_data); - cell->setPort("\\EN", enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); + cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en); cell->setPort("\\DATA", sig_data); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); diff --git a/yosys/passes/opt/Makefile.inc b/yosys/passes/opt/Makefile.inc index 337fee9e4..ea3646330 100644 --- a/yosys/passes/opt/Makefile.inc +++ b/yosys/passes/opt/Makefile.inc @@ -14,5 +14,6 @@ OBJS += passes/opt/opt_demorgan.o OBJS += passes/opt/rmports.o OBJS += passes/opt/opt_lut.o OBJS += passes/opt/pmux2shiftx.o +OBJS += passes/opt/muxpack.o endif diff --git a/yosys/passes/opt/muxpack.cc b/yosys/passes/opt/muxpack.cc new file mode 100644 index 000000000..6697d6ca1 --- /dev/null +++ b/yosys/passes/opt/muxpack.cc @@ -0,0 +1,368 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct ExclusiveDatabase +{ + Module *module; + const SigMap &sigmap; + + dict>> sig_cmp_prev; + + ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap) + { + SigSpec const_sig, nonconst_sig; + SigBit y_port; + pool reduce_or; + for (auto cell : module->cells()) { + if (cell->type == "$eq") { + nonconst_sig = sigmap(cell->getPort("\\A")); + const_sig = sigmap(cell->getPort("\\B")); + if (!const_sig.is_fully_const()) { + if (!nonconst_sig.is_fully_const()) + continue; + std::swap(nonconst_sig, const_sig); + } + y_port = sigmap(cell->getPort("\\Y")); + } + else if (cell->type == "$logic_not") { + nonconst_sig = sigmap(cell->getPort("\\A")); + const_sig = Const(RTLIL::S0, GetSize(nonconst_sig)); + y_port = sigmap(cell->getPort("\\Y")); + } + else if (cell->type == "$reduce_or") { + reduce_or.insert(cell); + continue; + } + else continue; + + log_assert(!nonconst_sig.empty()); + log_assert(!const_sig.empty()); + sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::vector{const_sig.as_const()}); + } + + for (auto cell : reduce_or) { + nonconst_sig = SigSpec(); + std::vector values; + SigSpec a_port = sigmap(cell->getPort("\\A")); + for (auto bit : a_port) { + auto it = sig_cmp_prev.find(bit); + if (it == sig_cmp_prev.end()) { + nonconst_sig = SigSpec(); + break; + } + if (nonconst_sig.empty()) + nonconst_sig = it->second.first; + else if (nonconst_sig != it->second.first) { + nonconst_sig = SigSpec(); + break; + } + for (auto value : it->second.second) + values.push_back(value); + } + if (nonconst_sig.empty()) + continue; + y_port = sigmap(cell->getPort("\\Y")); + sig_cmp_prev[y_port] = std::make_pair(nonconst_sig,std::move(values)); + } + } + + bool query(const SigSpec &sig) const + { + SigSpec nonconst_sig; + pool const_values; + + for (auto bit : sig.bits()) { + auto it = sig_cmp_prev.find(bit); + if (it == sig_cmp_prev.end()) + return false; + + if (nonconst_sig.empty()) + nonconst_sig = it->second.first; + else if (nonconst_sig != it->second.first) + return false; + + for (auto value : it->second.second) + if (!const_values.insert(value).second) + return false; + } + + return true; + } +}; + + +struct MuxpackWorker +{ + Module *module; + SigMap sigmap; + + int mux_count, pmux_count; + + pool remove_cells; + + dict sig_chain_next; + dict sig_chain_prev; + pool sigbit_with_non_chain_users; + pool chain_start_cells; + pool candidate_cells; + + ExclusiveDatabase excl_db; + + void make_sig_chain_next_prev() + { + for (auto wire : module->wires()) + { + if (wire->port_output || wire->get_bool_attribute("\\keep")) { + for (auto bit : sigmap(wire)) + sigbit_with_non_chain_users.insert(bit); + } + } + + for (auto cell : module->cells()) + { + if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep")) + { + SigSpec a_sig = sigmap(cell->getPort("\\A")); + SigSpec b_sig; + if (cell->type == "$mux") + b_sig = sigmap(cell->getPort("\\B")); + SigSpec y_sig = sigmap(cell->getPort("\\Y")); + + if (sig_chain_next.count(a_sig)) + for (auto a_bit : a_sig.bits()) + sigbit_with_non_chain_users.insert(a_bit); + else { + sig_chain_next[a_sig] = cell; + candidate_cells.insert(cell); + } + + if (!b_sig.empty()) { + if (sig_chain_next.count(b_sig)) + for (auto b_bit : b_sig.bits()) + sigbit_with_non_chain_users.insert(b_bit); + else { + sig_chain_next[b_sig] = cell; + candidate_cells.insert(cell); + } + } + + sig_chain_prev[y_sig] = cell; + continue; + } + + for (auto conn : cell->connections()) + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + sigbit_with_non_chain_users.insert(bit); + } + } + + void find_chain_start_cells() + { + for (auto cell : candidate_cells) + { + log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type)); + + SigSpec a_sig = sigmap(cell->getPort("\\A")); + if (cell->type == "$mux") { + SigSpec b_sig = sigmap(cell->getPort("\\B")); + if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1) + goto start_cell; + + if (!sig_chain_prev.count(a_sig)) + a_sig = b_sig; + } + else if (cell->type == "$pmux") { + if (!sig_chain_prev.count(a_sig)) + goto start_cell; + } + else log_abort(); + + for (auto bit : a_sig.bits()) + if (sigbit_with_non_chain_users.count(bit)) + goto start_cell; + + { + Cell *prev_cell = sig_chain_prev.at(a_sig); + log_assert(prev_cell); + SigSpec s_sig = sigmap(cell->getPort("\\S")); + s_sig.append(sigmap(prev_cell->getPort("\\S"))); + if (!excl_db.query(s_sig)) + goto start_cell; + } + + continue; + + start_cell: + chain_start_cells.insert(cell); + } + } + + vector create_chain(Cell *start_cell) + { + vector chain; + + Cell *c = start_cell; + while (c != nullptr) + { + chain.push_back(c); + + SigSpec y_sig = sigmap(c->getPort("\\Y")); + + if (sig_chain_next.count(y_sig) == 0) + break; + + c = sig_chain_next.at(y_sig); + if (chain_start_cells.count(c) != 0) + break; + } + + return chain; + } + + void process_chain(vector &chain) + { + if (GetSize(chain) < 2) + return; + + int cursor = 0; + while (cursor < GetSize(chain)) + { + int cases = GetSize(chain) - cursor; + + Cell *first_cell = chain[cursor]; + dict taps_dict; + + if (cases < 2) { + cursor++; + continue; + } + + Cell *last_cell = chain[cursor+cases-1]; + + log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n", + log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases); + + mux_count += cases; + pmux_count += 1; + + first_cell->type = "$pmux"; + SigSpec b_sig = first_cell->getPort("\\B"); + SigSpec s_sig = first_cell->getPort("\\S"); + + for (int i = 1; i < cases; i++) { + Cell* prev_cell = chain[cursor+i-1]; + Cell* cursor_cell = chain[cursor+i]; + if (sigmap(prev_cell->getPort("\\Y")) == sigmap(cursor_cell->getPort("\\A"))) { + b_sig.append(cursor_cell->getPort("\\B")); + s_sig.append(cursor_cell->getPort("\\S")); + } + else { + log_assert(cursor_cell->type == "$mux"); + b_sig.append(cursor_cell->getPort("\\A")); + s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S"))); + } + remove_cells.insert(cursor_cell); + } + + first_cell->setPort("\\B", b_sig); + first_cell->setPort("\\S", s_sig); + first_cell->setParam("\\S_WIDTH", GetSize(s_sig)); + first_cell->setPort("\\Y", last_cell->getPort("\\Y")); + + cursor += cases; + } + } + + void cleanup() + { + for (auto cell : remove_cells) + module->remove(cell); + + remove_cells.clear(); + sig_chain_next.clear(); + sig_chain_prev.clear(); + chain_start_cells.clear(); + candidate_cells.clear(); + } + + MuxpackWorker(Module *module) : + module(module), sigmap(module), mux_count(0), pmux_count(0), excl_db(module, sigmap) + { + make_sig_chain_next_prev(); + find_chain_start_cells(); + + for (auto c : chain_start_cells) { + vector chain = create_chain(c); + process_chain(chain); + } + + cleanup(); + } +}; + +struct MuxpackPass : public Pass { + MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" muxpack [selection]\n"); + log("\n"); + log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n"); + log("constructs) and $mux cells (e.g. those created by if-else constructs) into\n"); + log("$pmux cells.\n"); + log("\n"); + log("This optimisation is conservative --- it will only pack $mux or $pmux cells\n"); + log("whose select lines are driven by '$eq' cells with other such cells if it can be\n"); + log("certain that their select inputs are mutually exclusive.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + int mux_count = 0; + int pmux_count = 0; + + for (auto module : design->selected_modules()) { + MuxpackWorker worker(module); + mux_count += worker.mux_count; + pmux_count += worker.pmux_count; + } + + log("Converted %d (p)mux cells into %d pmux cells.\n", mux_count, pmux_count); + } +} MuxpackPass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/passes/opt/opt_clean.cc b/yosys/passes/opt/opt_clean.cc index bf8020169..a8a8e0bc7 100644 --- a/yosys/passes/opt/opt_clean.cc +++ b/yosys/passes/opt/opt_clean.cc @@ -106,7 +106,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (raw_bit.wire == nullptr) continue; auto bit = sigmap(raw_bit); - if (bit.wire == nullptr) + if (bit.wire == nullptr && ct_all.cell_known(cell->type)) driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict " "for %s between cell %s.%s and constant %s in %s: Resolved using constant.", log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module))); @@ -319,14 +319,15 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase("\\init"); if (GetSize(wire) == 0) { - // delete zero-width wires - goto delete_this_wire; + // delete zero-width wires, unless they are module ports + if (wire->port_id == 0) + goto delete_this_wire; } else if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) { // do not delete anything with "keep" or module ports or initialized wires } else - if (!purge_mode && check_public_name(wire->name)) { - // do not get rid of public names unless in purge mode + if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) { + // do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased } else if (!raw_used_signals.check_any(s1)) { // delete wires that aren't used by anything directly @@ -479,7 +480,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool std::vector delcells; for (auto cell : module->cells()) - if (cell->type.in("$pos", "$_BUF_")) { + if (cell->type.in("$pos", "$_BUF_") && !cell->has_keep_attr()) { bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool(); RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec y = cell->getPort("\\Y"); diff --git a/yosys/passes/opt/opt_lut.cc b/yosys/passes/opt/opt_lut.cc index 26855fd70..dda10ec17 100644 --- a/yosys/passes/opt/opt_lut.cc +++ b/yosys/passes/opt/opt_lut.cc @@ -81,7 +81,7 @@ struct OptLutWorker } } - log("Number of LUTs: %8zu\n", luts.size()); + log("Number of LUTs: %8d\n", GetSize(luts)); for (int arity = 1; arity <= max_arity; arity++) { if (arity_counts[arity]) @@ -353,14 +353,14 @@ struct OptLutWorker int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size(); if (lutA_dlogic_inputs.size()) - log(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size()); + log(" Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs)); else log(" Cell A is a %d-LUT. ", lutA_arity); if (lutB_dlogic_inputs.size()) - log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size()); + log("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs)); else log("Cell B is a %d-LUT.\n", lutB_arity); - log(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity); + log(" Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity); const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B; int combine_mask = 0; diff --git a/yosys/passes/opt/opt_rmdff.cc b/yosys/passes/opt/opt_rmdff.cc index e8570f0eb..eeb992a3e 100644 --- a/yosys/passes/opt/opt_rmdff.cc +++ b/yosys/passes/opt/opt_rmdff.cc @@ -260,8 +260,8 @@ delete_dlatch: bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) { - RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r; - RTLIL::Const val_cp, val_rp, val_rv; + RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e; + RTLIL::Const val_cp, val_rp, val_rv, val_ep; if (dff->type == "$_FF_") { sig_d = dff->getPort("\\D"); @@ -285,6 +285,16 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } + else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" && + (dff->type[7] == 'N' || dff->type[7] == 'P') && + (dff->type[8] == 'N' || dff->type[8] == 'P')) { + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\C"); + sig_e = dff->getPort("\\E"); + val_cp = RTLIL::Const(dff->type[7] == 'P', 1); + val_ep = RTLIL::Const(dff->type[8] == 'P', 1); + } else if (dff->type == "$ff") { sig_d = dff->getPort("\\D"); sig_q = dff->getPort("\\Q"); @@ -295,6 +305,14 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_c = dff->getPort("\\CLK"); val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); } + else if (dff->type == "$dffe") { + sig_e = dff->getPort("\\EN"); + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\CLK"); + val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); + val_ep = RTLIL::Const(dff->parameters["\\EN_POLARITY"].as_bool(), 1); + } else if (dff->type == "$adff") { sig_d = dff->getPort("\\D"); sig_q = dff->getPort("\\Q"); @@ -337,39 +355,60 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } + // If clock is driven by a constant and (i) no reset signal + // (ii) Q has no initial value + // (iii) initial value is same as reset value if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) { if (val_rv.bits.size() == 0) val_rv = val_init; + // Q is permanently reset value or initial value mod->connect(sig_q, val_rv); goto delete_dff; } + // If D is fully undefined and reset signal present and (i) Q has no initial value + // (ii) initial value is same as reset value if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) { + // Q is permanently reset value mod->connect(sig_q, val_rv); goto delete_dff; } + // If D is fully undefined and no reset signal and Q has an initial value if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { + // Q is permanently initial value mod->connect(sig_q, val_init); goto delete_dff; } + // If D is fully constant and (i) no reset signal + // (ii) reset value is same as constant D + // and (a) has no initial value + // (b) initial value same as constant D if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { + // Q is permanently D mod->connect(sig_q, sig_d); goto delete_dff; } + // If D input is same as Q output and (i) no reset signal + // (ii) no initial signal + // (iii) initial value is same as reset value if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) { + // Q is permanently reset value or initial value if (sig_r.size()) mod->connect(sig_q, val_rv); - if (has_init) + else if (has_init) mod->connect(sig_q, val_init); goto delete_dff; } + // If reset signal is present, and is fully constant if (!sig_r.empty() && sig_r.is_fully_const()) { + // If reset value is permanently active or if reset is undefined if (sig_r == val_rp || sig_r.is_fully_undef()) { + // Q is permanently reset value mod->connect(sig_q, val_rv); goto delete_dff; } @@ -389,6 +428,30 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) dff->unsetPort("\\R"); } + // If enable signal is present, and is fully constant + if (!sig_e.empty() && sig_e.is_fully_const()) + { + // If enable value is permanently inactive + if (sig_e != val_ep) { + // Q is permanently initial value + mod->connect(sig_q, val_init); + goto delete_dff; + } + + log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); + + if (dff->type == "$dffe") { + dff->type = "$dff"; + dff->unsetPort("\\EN"); + dff->unsetParam("\\EN_POLARITY"); + return true; + } + + log_assert(dff->type.substr(0,7) == "$_DFFE_"); + dff->type = stringf("$_DFF_%c_", + dff->type[7]); + dff->unsetPort("\\E"); + } + return false; delete_dff: @@ -489,7 +552,8 @@ struct OptRmdffPass : public Pass { if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_", "$_DFF_PN0_", "$_DFF_PN1_", "$_DFF_PP0_", "$_DFF_PP1_", - "$ff", "$dff", "$adff")) + "$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_", + "$ff", "$dff", "$dffe", "$adff")) dff_list.push_back(cell->name); if (cell->type.in("$dlatch", "$_DLATCH_P_", "$_DLATCH_N_")) diff --git a/yosys/passes/opt/pmux2shiftx.cc b/yosys/passes/opt/pmux2shiftx.cc index 29870f510..65d8b8f32 100644 --- a/yosys/passes/opt/pmux2shiftx.cc +++ b/yosys/passes/opt/pmux2shiftx.cc @@ -221,6 +221,9 @@ struct Pmux2ShiftxPass : public Pass { log(" select strategy for one-hot encoded control signals\n"); log(" default: pmux\n"); log("\n"); + log(" -norange\n"); + log(" disable $sub inference for \"range decoders\"\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { @@ -230,6 +233,7 @@ struct Pmux2ShiftxPass : public Pass { bool optimize_onehot = true; bool verbose = false; bool verbose_onehot = false; + bool norange = false; log_header(design, "Executing PMUX2SHIFTX pass.\n"); @@ -270,6 +274,10 @@ struct Pmux2ShiftxPass : public Pass { verbose_onehot = true; continue; } + if (args[argidx] == "-norange") { + norange = true; + continue; + } break; } extra_args(args, argidx, design); @@ -559,7 +567,7 @@ struct Pmux2ShiftxPass : public Pass { int this_inv_delta = this_maxval - this_minval; bool this_inv = false; - if (this_delta != this_inv_delta) + if (!norange && this_delta != this_inv_delta) this_inv = this_inv_delta < this_delta; else if (this_maxval != this_inv_maxval) this_inv = this_inv_maxval < this_maxval; @@ -574,7 +582,7 @@ struct Pmux2ShiftxPass : public Pass { if (best_src_col < 0) this_is_better = true; - else if (this_delta != best_delta) + else if (!norange && this_delta != best_delta) this_is_better = this_delta < best_delta; else if (this_maxval != best_maxval) this_is_better = this_maxval < best_maxval; @@ -656,7 +664,7 @@ struct Pmux2ShiftxPass : public Pass { // check density percentages Const offset(State::S0, GetSize(sig)); - if (absolute_density < min_density && range_density >= min_density) + if (!norange && absolute_density < min_density && range_density >= min_density) { offset = Const(min_choice, GetSize(sig)); log(" offset: %s\n", log_signal(offset)); diff --git a/yosys/passes/opt/rmports.cc b/yosys/passes/opt/rmports.cc index fc1596ebf..32363dd68 100644 --- a/yosys/passes/opt/rmports.cc +++ b/yosys/passes/opt/rmports.cc @@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass { wire->port_output = false; wire->port_id = 0; } - log("Removed %zu unused ports.\n", unused_ports.size()); + log("Removed %d unused ports.\n", GetSize(unused_ports)); // Re-number all of the wires that DO have ports still on them for(size_t i=0; iports.size(); i++) diff --git a/yosys/passes/pmgen/peepopt_shiftmul.pmg b/yosys/passes/pmgen/peepopt_shiftmul.pmg index fe861b728..6adab4e5f 100644 --- a/yosys/passes/pmgen/peepopt_shiftmul.pmg +++ b/yosys/passes/pmgen/peepopt_shiftmul.pmg @@ -1,4 +1,7 @@ pattern shiftmul +// +// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] +// state shamt @@ -49,12 +52,16 @@ code if (GetSize(port(shift, \Y)) > const_factor) reject; + int factor_bits = ceil_log2(const_factor); + SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); + + if (GetSize(shamt) < factor_bits+GetSize(mul_din)) + reject; + did_something = true; log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); - int new_const_factor_log2 = ceil_log2(const_factor); - int new_const_factor = 1 << new_const_factor_log2; - + int new_const_factor = 1 << factor_bits; SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec old_a = port(shift, \A), new_a; int trunc = 0; @@ -73,7 +80,7 @@ code if (trunc > 0) new_a.remove(GetSize(new_a)-trunc, trunc); - SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)}; + SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; if (param(shift, \B_SIGNED).as_bool()) new_b.append(State::S0); diff --git a/yosys/passes/proc/proc_mux.cc b/yosys/passes/proc/proc_mux.cc index aac0b121c..d029282fd 100644 --- a/yosys/passes/proc/proc_mux.cc +++ b/yosys/passes/proc/proc_mux.cc @@ -144,7 +144,13 @@ struct SnippetSwCache } }; -RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SwitchRule *sw, bool ifxmode) +void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs) +{ + cell->attributes = sw->attributes; + cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src")); +} + +RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { std::stringstream sstr; sstr << "$procmux$" << (autoidx++); @@ -173,7 +179,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s { // create compare cell RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq"); - eq_cell->attributes = sw->attributes; + apply_attrs(eq_cell, sw, cs); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); @@ -199,7 +205,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s // reduce cmp vector to one logic signal RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); - any_cell->attributes = sw->attributes; + apply_attrs(any_cell, sw, cs); any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); @@ -212,7 +218,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s return RTLIL::SigSpec(ctrl_wire); } -RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode) +RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { log_assert(when_signal.size() == else_signal.size()); @@ -224,7 +230,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s return when_signal; // compare results - RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode); + RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode); if (ctrl_sig.size() == 0) return when_signal; log_assert(ctrl_sig.size() == 1); @@ -234,7 +240,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s // create the multiplexer itself RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); - mux_cell->attributes = sw->attributes; + apply_attrs(mux_cell, sw, cs); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->setPort("\\A", else_signal); @@ -246,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s return RTLIL::SigSpec(result_wire); } -void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, bool ifxmode) +void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { log_assert(last_mux_cell != NULL); log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size()); @@ -254,7 +260,7 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve if (when_signal == last_mux_cell->getPort("\\A")) return; - RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, ifxmode); + RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode); log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; @@ -395,9 +401,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d RTLIL::CaseRule *cs2 = sw->cases[case_idx]; RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val, ifxmode); if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1]) - append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, ifxmode); + append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, cs2, ifxmode); else - result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, ifxmode); + result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, cs2, ifxmode); } } diff --git a/yosys/passes/sat/assertpmux.cc b/yosys/passes/sat/assertpmux.cc index 509cb0ba9..3b432c461 100644 --- a/yosys/passes/sat/assertpmux.cc +++ b/yosys/passes/sat/assertpmux.cc @@ -180,7 +180,7 @@ struct AssertpmuxWorker }; struct AssertpmuxPass : public Pass { - AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { } + AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -195,8 +195,8 @@ struct AssertpmuxPass : public Pass { log("\n"); log(" -always\n"); log(" usually the $pmux condition is only checked when the $pmux output\n"); - log(" is used be the mux tree it drives. this option will deactivate this\n"); - log(" additional constrained and check the $pmux condition always.\n"); + log(" is used by the mux tree it drives. this option will deactivate this\n"); + log(" additional constraint and check the $pmux condition always.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE diff --git a/yosys/passes/sat/cutpoint.cc b/yosys/passes/sat/cutpoint.cc index 048aec7f3..b4549bc39 100644 --- a/yosys/passes/sat/cutpoint.cc +++ b/yosys/passes/sat/cutpoint.cc @@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct CutpointPass : public Pass { - CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { } + CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/yosys/passes/sat/fmcombine.cc b/yosys/passes/sat/fmcombine.cc index f64d99dc2..00c098542 100644 --- a/yosys/passes/sat/fmcombine.cc +++ b/yosys/passes/sat/fmcombine.cc @@ -332,7 +332,7 @@ struct FmcombinePass : public Pass { gate_cell = module->cell(gate_name); if (gate_cell == nullptr) - log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gate_name), log_id(module)); + log_cmd_error("Gate cell %s not found in module %s.\n", log_id(gate_name), log_id(module)); } else { @@ -351,7 +351,7 @@ struct FmcombinePass : public Pass { if (!gold_cell->parameters.empty()) log_cmd_error("Gold cell has unresolved instance parameters.\n"); if (!gate_cell->parameters.empty()) - log_cmd_error("Gold cell has unresolved instance parameters.\n"); + log_cmd_error("Gate cell has unresolved instance parameters.\n"); FmcombineWorker worker(design, gold_cell->type, opts); worker.generate(); diff --git a/yosys/passes/sat/sat.cc b/yosys/passes/sat/sat.cc index cbba738f0..e4654d835 100644 --- a/yosys/passes/sat/sat.cc +++ b/yosys/passes/sat/sat.cc @@ -659,6 +659,7 @@ struct SatHelper void dump_model_to_vcd(std::string vcd_file_name) { + rewrite_filename(vcd_file_name); FILE *f = fopen(vcd_file_name.c_str(), "w"); if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); @@ -761,6 +762,7 @@ struct SatHelper void dump_model_to_json(std::string json_file_name) { + rewrite_filename(json_file_name); FILE *f = fopen(json_file_name.c_str(), "w"); if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno)); @@ -1505,6 +1507,7 @@ struct SatPass : public Pass { { if (!cnf_file_name.empty()) { + rewrite_filename(cnf_file_name); FILE *f = fopen(cnf_file_name.c_str(), "w"); if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); @@ -1608,6 +1611,7 @@ struct SatPass : public Pass { if (!cnf_file_name.empty()) { + rewrite_filename(cnf_file_name); FILE *f = fopen(cnf_file_name.c_str(), "w"); if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); diff --git a/yosys/passes/sat/sim.cc b/yosys/passes/sat/sim.cc index 53e248adf..4c3022c70 100644 --- a/yosys/passes/sat/sim.cc +++ b/yosys/passes/sat/sim.cc @@ -88,6 +88,8 @@ struct SimInstance SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) : shared(shared), module(module), instance(instance), parent(parent), sigmap(module) { + log_assert(module); + if (parent) { log_assert(parent->children.count(instance) == 0); parent->children[instance] = this; @@ -848,6 +850,9 @@ struct SimPass : public Pass { if (design->full_selection()) { top_mod = design->top_module(); + + if (!top_mod) + log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n"); } else { auto mods = design->selected_whole_modules(); if (GetSize(mods) != 1) diff --git a/yosys/passes/techmap/abc.cc b/yosys/passes/techmap/abc.cc index 5b19d84fb..bf05c68e7 100644 --- a/yosys/passes/techmap/abc.cc +++ b/yosys/passes/techmap/abc.cc @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include diff --git a/yosys/passes/techmap/flowmap.cc b/yosys/passes/techmap/flowmap.cc index f5892a60e..96d0df5f8 100644 --- a/yosys/passes/techmap/flowmap.cc +++ b/yosys/passes/techmap/flowmap.cc @@ -783,7 +783,7 @@ struct FlowmapWorker int depth = 0; for (auto label : labels) depth = max(depth, label.second); - log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth); + log("Mapped to %d LUTs with maximum depth %d.\n", GetSize(lut_nodes), depth); if (debug) { @@ -1195,7 +1195,7 @@ struct FlowmapWorker bool relax_depth_for_bound(bool first, int depth_bound, dict> &lut_critical_outputs) { - size_t initial_count = lut_nodes.size(); + int initial_count = GetSize(lut_nodes); for (auto node : lut_nodes) { @@ -1215,7 +1215,7 @@ struct FlowmapWorker if (potentials.empty()) { - log(" Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count); + log(" Relaxed to %d (+%d) LUTs.\n", GetSize(lut_nodes), GetSize(lut_nodes) - initial_count); if (!first && break_num == 1) { log(" Design fully relaxed.\n"); @@ -1419,9 +1419,9 @@ struct FlowmapWorker lut_area += lut_table.size(); if ((int)input_nodes.size() >= minlut) - log(" Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut)); + log(" Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut)); else - log(" Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut); + log(" Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut); } for (auto node : mapped_nodes) diff --git a/yosys/passes/techmap/muxcover.cc b/yosys/passes/techmap/muxcover.cc index 12da9ed0c..c84cfc39a 100644 --- a/yosys/passes/techmap/muxcover.cc +++ b/yosys/passes/techmap/muxcover.cc @@ -23,6 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +#define COST_DMUX 90 #define COST_MUX2 100 #define COST_MUX4 220 #define COST_MUX8 460 @@ -57,6 +58,13 @@ struct MuxcoverWorker bool use_mux8; bool use_mux16; bool nodecode; + bool nopartial; + + int cost_dmux; + int cost_mux2; + int cost_mux4; + int cost_mux8; + int cost_mux16; MuxcoverWorker(Module *module) : module(module), sigmap(module) { @@ -64,9 +72,32 @@ struct MuxcoverWorker use_mux8 = false; use_mux16 = false; nodecode = false; + nopartial = false; + cost_dmux = COST_DMUX; + cost_mux2 = COST_MUX2; + cost_mux4 = COST_MUX4; + cost_mux8 = COST_MUX8; + cost_mux16 = COST_MUX16; decode_mux_counter = 0; } + bool xcmp(std::initializer_list list) + { + auto cursor = list.begin(), end = list.end(); + log_assert(cursor != end); + SigBit tmp = *(cursor++); + while (cursor != end) { + SigBit bit = *(cursor++); + if (bit == State::Sx) + continue; + if (tmp == State::Sx) + tmp = bit; + if (bit != tmp) + return false; + } + return true; + } + void treeify() { pool roots; @@ -124,13 +155,22 @@ struct MuxcoverWorker log(" Finished treeification: Found %d trees.\n", GetSize(tree_list)); } - bool follow_muxtree(SigBit &ret_bit, tree_t &tree, SigBit bit, const char *path) + bool follow_muxtree(SigBit &ret_bit, tree_t &tree, SigBit bit, const char *path, bool first_layer = true) { if (*path) { - if (tree.muxes.count(bit) == 0) - return false; + if (tree.muxes.count(bit) == 0) { + if (first_layer || nopartial) + return false; + while (path[0] && path[1]) + path++; + if (path[0] == 'S') + ret_bit = State::Sx; + else + ret_bit = bit; + return true; + } char port_name[3] = {'\\', *path, 0}; - return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1); + return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1, false); } else { ret_bit = bit; return true; @@ -139,7 +179,7 @@ struct MuxcoverWorker int prepare_decode_mux(SigBit &A, SigBit B, SigBit sel, SigBit bit) { - if (A == B) + if (A == B || sel == State::Sx) return 0; tuple key(A, B, sel); @@ -157,7 +197,10 @@ struct MuxcoverWorker if (std::get<2>(entry)) return 0; - return COST_MUX2 / GetSize(std::get<1>(entry)); + if (A == State::Sx || B == State::Sx) + return 0; + + return cost_dmux / GetSize(std::get<1>(entry)); } void implement_decode_mux(SigBit ctrl_bit) @@ -174,9 +217,32 @@ struct MuxcoverWorker implement_decode_mux(std::get<0>(key)); implement_decode_mux(std::get<1>(key)); - module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit); + if (std::get<0>(key) == State::Sx) { + module->addBufGate(NEW_ID, std::get<1>(key), ctrl_bit); + } else if (std::get<1>(key) == State::Sx) { + module->addBufGate(NEW_ID, std::get<0>(key), ctrl_bit); + } else { + module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit); + decode_mux_counter++; + } std::get<2>(entry) = true; - decode_mux_counter++; + } + + void find_best_covers(tree_t &tree, const vector &bits) + { + for (auto bit : bits) + find_best_cover(tree, bit); + } + + int sum_best_covers(tree_t &tree, const vector &bits) + { + int sum = 0; + for (auto bit : pool(bits.begin(), bits.end())) { + int cost = tree.newmuxes.at(bit).cost; + log_debug(" Best cost for %s: %d\n", log_signal(bit), cost); + sum += cost; + } + return sum; } int find_best_cover(tree_t &tree, SigBit bit) @@ -209,9 +275,13 @@ struct MuxcoverWorker mux.inputs.push_back(B); mux.selects.push_back(S1); - mux.cost += COST_MUX2; - mux.cost += find_best_cover(tree, A); - mux.cost += find_best_cover(tree, B); + find_best_covers(tree, mux.inputs); + log_debug(" Decode cost for mux2 at %s: %d\n", log_signal(bit), mux.cost); + + mux.cost += cost_mux2; + mux.cost += sum_best_covers(tree, mux.inputs); + + log_debug(" Cost of mux2 at %s: %d\n", log_signal(bit), mux.cost); best_mux = mux; } @@ -229,7 +299,7 @@ struct MuxcoverWorker ok = ok && follow_muxtree(S2, tree, bit, "BS"); if (nodecode) - ok = ok && S1 == S2; + ok = ok && xcmp({S1, S2}); ok = ok && follow_muxtree(T1, tree, bit, "S"); @@ -247,13 +317,15 @@ struct MuxcoverWorker mux.selects.push_back(S1); mux.selects.push_back(T1); - mux.cost += COST_MUX4; - mux.cost += find_best_cover(tree, A); - mux.cost += find_best_cover(tree, B); - mux.cost += find_best_cover(tree, C); - mux.cost += find_best_cover(tree, D); + find_best_covers(tree, mux.inputs); + log_debug(" Decode cost for mux4 at %s: %d\n", log_signal(bit), mux.cost); - if (best_mux.cost > mux.cost) + mux.cost += cost_mux4; + mux.cost += sum_best_covers(tree, mux.inputs); + + log_debug(" Cost of mux4 at %s: %d\n", log_signal(bit), mux.cost); + + if (best_mux.cost >= mux.cost) best_mux = mux; } } @@ -277,13 +349,13 @@ struct MuxcoverWorker ok = ok && follow_muxtree(S4, tree, bit, "BBS"); if (nodecode) - ok = ok && S1 == S2 && S2 == S3 && S3 == S4; + ok = ok && xcmp({S1, S2, S3, S4}); ok = ok && follow_muxtree(T1, tree, bit, "AS"); ok = ok && follow_muxtree(T2, tree, bit, "BS"); if (nodecode) - ok = ok && T1 == T2; + ok = ok && xcmp({T1, T2}); ok = ok && follow_muxtree(U1, tree, bit, "S"); @@ -310,17 +382,15 @@ struct MuxcoverWorker mux.selects.push_back(T1); mux.selects.push_back(U1); - mux.cost += COST_MUX8; - mux.cost += find_best_cover(tree, A); - mux.cost += find_best_cover(tree, B); - mux.cost += find_best_cover(tree, C); - mux.cost += find_best_cover(tree, D); - mux.cost += find_best_cover(tree, E); - mux.cost += find_best_cover(tree, F); - mux.cost += find_best_cover(tree, G); - mux.cost += find_best_cover(tree, H); + find_best_covers(tree, mux.inputs); + log_debug(" Decode cost for mux8 at %s: %d\n", log_signal(bit), mux.cost); - if (best_mux.cost > mux.cost) + mux.cost += cost_mux8; + mux.cost += sum_best_covers(tree, mux.inputs); + + log_debug(" Cost of mux8 at %s: %d\n", log_signal(bit), mux.cost); + + if (best_mux.cost >= mux.cost) best_mux = mux; } } @@ -356,7 +426,7 @@ struct MuxcoverWorker ok = ok && follow_muxtree(S8, tree, bit, "BBBS"); if (nodecode) - ok = ok && S1 == S2 && S2 == S3 && S3 == S4 && S4 == S5 && S5 == S6 && S6 == S7 && S7 == S8; + ok = ok && xcmp({S1, S2, S3, S4, S5, S6, S7, S8}); ok = ok && follow_muxtree(T1, tree, bit, "AAS"); ok = ok && follow_muxtree(T2, tree, bit, "ABS"); @@ -364,13 +434,13 @@ struct MuxcoverWorker ok = ok && follow_muxtree(T4, tree, bit, "BBS"); if (nodecode) - ok = ok && T1 == T2 && T2 == T3 && T3 == T4; + ok = ok && xcmp({T1, T2, T3, T4}); ok = ok && follow_muxtree(U1, tree, bit, "AS"); ok = ok && follow_muxtree(U2, tree, bit, "BS"); if (nodecode) - ok = ok && U1 == U2; + ok = ok && xcmp({U1, U2}); ok = ok && follow_muxtree(V1, tree, bit, "S"); @@ -414,25 +484,15 @@ struct MuxcoverWorker mux.selects.push_back(U1); mux.selects.push_back(V1); - mux.cost += COST_MUX16; - mux.cost += find_best_cover(tree, A); - mux.cost += find_best_cover(tree, B); - mux.cost += find_best_cover(tree, C); - mux.cost += find_best_cover(tree, D); - mux.cost += find_best_cover(tree, E); - mux.cost += find_best_cover(tree, F); - mux.cost += find_best_cover(tree, G); - mux.cost += find_best_cover(tree, H); - mux.cost += find_best_cover(tree, I); - mux.cost += find_best_cover(tree, J); - mux.cost += find_best_cover(tree, K); - mux.cost += find_best_cover(tree, L); - mux.cost += find_best_cover(tree, M); - mux.cost += find_best_cover(tree, N); - mux.cost += find_best_cover(tree, O); - mux.cost += find_best_cover(tree, P); + find_best_covers(tree, mux.inputs); + log_debug(" Decode cost for mux16 at %s: %d\n", log_signal(bit), mux.cost); - if (best_mux.cost > mux.cost) + mux.cost += cost_mux16; + mux.cost += sum_best_covers(tree, mux.inputs); + + log_debug(" Cost of mux16 at %s: %d\n", log_signal(bit), mux.cost); + + if (best_mux.cost >= mux.cost) best_mux = mux; } } @@ -528,6 +588,7 @@ struct MuxcoverWorker void treecover(tree_t &tree) { int count_muxes_by_type[4] = {0, 0, 0, 0}; + log_debug(" Searching for best cover for tree at %s.\n", log_signal(tree.root)); find_best_cover(tree, tree.root); implement_best_cover(tree, tree.root, count_muxes_by_type); log(" Replaced tree at %s: %d MUX2, %d MUX4, %d MUX8, %d MUX16\n", log_signal(tree.root), @@ -544,12 +605,13 @@ struct MuxcoverWorker log(" Covering trees:\n"); - // pre-fill cache of decoder muxes - if (!nodecode) + if (!nodecode) { + log_debug(" Populating cache of decoder muxes.\n"); for (auto &tree : tree_list) { find_best_cover(tree, tree.root); tree.newmuxes.clear(); } + } for (auto &tree : tree_list) treecover(tree); @@ -569,15 +631,25 @@ struct MuxcoverPass : public Pass { log("\n"); log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n"); log("\n"); - log(" -mux4, -mux8, -mux16\n"); - log(" Use the specified types of MUXes. If none of those options are used,\n"); - log(" the effect is the same as if all of them where used.\n"); + log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n"); + log(" Use the specified types of MUXes (with optional integer costs). If none\n"); + log(" of these options are given, the effect is the same as if all of them are.\n"); + log(" Default costs: $_MUX_ = %d, $_MUX4_ = %d,\n", COST_MUX2, COST_MUX4); + log(" $_MUX8_ = %d, $_MUX16_ = %d\n", COST_MUX8, COST_MUX16); + log("\n"); + log(" -dmux=cost\n"); + log(" Use the specified cost for $_MUX_ cells used in decoders.\n"); + log(" Default cost: %d\n", COST_DMUX); log("\n"); log(" -nodecode\n"); log(" Do not insert decoder logic. This reduces the number of possible\n"); log(" substitutions, but guarantees that the resulting circuit is not\n"); log(" less efficient than the original circuit.\n"); log("\n"); + log(" -nopartial\n"); + log(" Do not consider mappings that use $_MUX_ to select from less\n"); + log(" than different signals.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { @@ -587,26 +659,52 @@ struct MuxcoverPass : public Pass { bool use_mux8 = false; bool use_mux16 = false; bool nodecode = false; + bool nopartial = false; + int cost_dmux = COST_DMUX; + int cost_mux4 = COST_MUX4; + int cost_mux8 = COST_MUX8; + int cost_mux16 = COST_MUX16; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-mux4") { + const auto &arg = args[argidx]; + if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") { use_mux4 = true; + if (arg.size() > 5) { + if (arg[5] != '=') break; + cost_mux4 = atoi(arg.substr(6).c_str()); + } continue; } - if (args[argidx] == "-mux8") { + if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") { use_mux8 = true; + if (arg.size() > 5) { + if (arg[5] != '=') break; + cost_mux8 = atoi(arg.substr(6).c_str()); + } continue; } - if (args[argidx] == "-mux16") { + if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") { use_mux16 = true; + if (arg.size() > 6) { + if (arg[6] != '=') break; + cost_mux16 = atoi(arg.substr(7).c_str()); + } continue; } - if (args[argidx] == "-nodecode") { + if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") { + cost_dmux = atoi(arg.substr(6).c_str()); + continue; + } + if (arg == "-nodecode") { nodecode = true; continue; } + if (arg == "-nopartial") { + nopartial = true; + continue; + } break; } extra_args(args, argidx, design); @@ -623,7 +721,12 @@ struct MuxcoverPass : public Pass { worker.use_mux4 = use_mux4; worker.use_mux8 = use_mux8; worker.use_mux16 = use_mux16; + worker.cost_dmux = cost_dmux; + worker.cost_mux4 = cost_mux4; + worker.cost_mux8 = cost_mux8; + worker.cost_mux16 = cost_mux16; worker.nodecode = nodecode; + worker.nopartial = nopartial; worker.run(); } } diff --git a/yosys/passes/techmap/shregmap.cc b/yosys/passes/techmap/shregmap.cc index 75eedfbcc..004ab1eb9 100644 --- a/yosys/passes/techmap/shregmap.cc +++ b/yosys/passes/techmap/shregmap.cc @@ -293,10 +293,22 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - if (sigbit_chain_next.count(d_bit)) { + auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); + if (!r.second) { + // Insertion not successful means that d_bit is already + // connected to another register, thus mark it as a + // non chain user ... sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; + // ... and clone d_bit into another wire, and use that + // wire as a different key in the d_bit-to-cell dictionary + // so that it can be identified as another chain + // (omitting this common flop) + // Link: https://github.com/YosysHQ/yosys/pull/1085 + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigmap.add(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; @@ -605,6 +617,11 @@ struct ShregmapPass : public Pass { log("\n"); log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); + log(" this option also implies -clkpol pos -zinit\n"); + log("\n"); + log(" -tech xilinx\n"); + log(" map to xilinx dynamic-length shift registers.\n"); + log(" this option also implies -params -init\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE diff --git a/yosys/techlibs/anlogic/anlogic_determine_init.cc b/yosys/techlibs/anlogic/anlogic_determine_init.cc index 34b1d4f8a..c4089dac2 100644 --- a/yosys/techlibs/anlogic/anlogic_determine_init.cc +++ b/yosys/techlibs/anlogic/anlogic_determine_init.cc @@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass { } } } - log_header(design, "Updated %lu cells with determined init value.\n", cnt); + log_header(design, "Updated %d cells with determined init value.\n", cnt); } } AnlogicDetermineInitPass; diff --git a/yosys/techlibs/anlogic/anlogic_eqn.cc b/yosys/techlibs/anlogic/anlogic_eqn.cc index 741bf04cc..070d39a20 100644 --- a/yosys/techlibs/anlogic/anlogic_eqn.cc +++ b/yosys/techlibs/anlogic/anlogic_eqn.cc @@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass { } } } - log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt); + log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt); } } AnlogicEqnPass; diff --git a/yosys/techlibs/ecp5/arith_map.v b/yosys/techlibs/ecp5/arith_map.v index eb7947601..17bde0497 100644 --- a/yosys/techlibs/ecp5/arith_map.v +++ b/yosys/techlibs/ecp5/arith_map.v @@ -50,20 +50,21 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH2-1:0] AA = A_buf; wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH2-1:0] BX = B_buf; wire [Y_WIDTH2-1:0] C = {CO, CI}; wire [Y_WIDTH2-1:0] FCO, Y1; genvar i; generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice CCU2C #( - .INIT0(16'b0110011010101010), - .INIT1(16'b0110011010101010), + .INIT0(16'b1001011010101010), + .INIT1(16'b1001011010101010), .INJECT1_0("NO"), .INJECT1_1("NO") ) ccu2c_i ( .CIN(C[i]), - .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), - .A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1), .S0(Y[i]), .S1(Y1[i]), .COUT(FCO[i]) ); diff --git a/yosys/techlibs/ecp5/cells_map.v b/yosys/techlibs/ecp5/cells_map.v index 6ab4b69f2..a90d5e034 100644 --- a/yosys/techlibs/ecp5/cells_map.v +++ b/yosys/techlibs/ecp5/cells_map.v @@ -47,8 +47,59 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED" module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -// For Diamond compatibility, FIXME: add all Diamond flipflop mappings +// TODO: Diamond flip-flops +// module FD1P3AX(); endmodule +// module FD1P3AY(); endmodule +// module FD1P3BX(); endmodule +// module FD1P3DX(); endmodule +// module FD1P3IX(); endmodule +// module FD1P3JX(); endmodule +// module FD1S3AX(); endmodule +// module FD1S3AY(); endmodule module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule +module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule +// module FL1P3AY(); endmodule +// module FL1P3AZ(); endmodule +// module FL1P3BX(); endmodule +// module FL1P3DX(); endmodule +// module FL1P3IY(); endmodule +// module FL1P3JY(); endmodule +// module FL1S3AX(); endmodule +// module FL1S3AY(); endmodule + +// Diamond I/O buffers +module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule +module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule +module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule +module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule + +// Diamond I/O registers +module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +// TODO: Diamond I/O latches +// module IFS1S1B(input PD, D, SCLK, output Q); endmodule +// module IFS1S1D(input CD, D, SCLK, output Q); endmodule +// module IFS1S1I(input PD, D, SCLK, output Q); endmodule +// module IFS1S1J(input CD, D, SCLK, output Q); endmodule `ifndef NO_LUT module \$lut (A, Y); diff --git a/yosys/techlibs/ecp5/cells_sim.v b/yosys/techlibs/ecp5/cells_sim.v index 1e4002ee0..07fadfa10 100644 --- a/yosys/techlibs/ecp5/cells_sim.v +++ b/yosys/techlibs/ecp5/cells_sim.v @@ -250,18 +250,6 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); endgenerate endmodule -// --------------------------------------- - -module OBZ(input I, T, output O); -assign O = T ? 1'bz : I; -endmodule - -// --------------------------------------- - -module IB(input I, output O); -assign O = I; -endmodule - // --------------------------------------- (* keep *) module TRELLIS_IO( @@ -293,19 +281,6 @@ endmodule // --------------------------------------- -module OB(input I, output O); -assign O = I; -endmodule - -// --------------------------------------- - -module BB(input I, T, output O, inout B); -assign B = T ? 1'bz : I; -assign O = B; -endmodule - -// --------------------------------------- - module INV(input A, output Z); assign Z = !A; endmodule @@ -558,19 +533,56 @@ module DP16KD( parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; endmodule -// For Diamond compatibility, FIXME: add all Diamond flipflop mappings -module FD1S3BX(input PD, D, CK, output Q); - TRELLIS_FF #( - .GSR("DISABLED"), - .CEMUX("1"), - .CLKMUX("CLK"), - .LSRMUX("LSR"), - .REGSET("SET"), - .SRMODE("ASYNC") - ) tff_i ( - .CLK(CK), - .LSR(PD), - .DI(D), - .Q(Q) - ); -endmodule +// TODO: Diamond flip-flops +// module FD1P3AX(); endmodule +// module FD1P3AY(); endmodule +// module FD1P3BX(); endmodule +// module FD1P3DX(); endmodule +// module FD1P3IX(); endmodule +// module FD1P3JX(); endmodule +// module FD1S3AX(); endmodule +// module FD1S3AY(); endmodule +module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule +module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule +// module FL1P3AY(); endmodule +// module FL1P3AZ(); endmodule +// module FL1P3BX(); endmodule +// module FL1P3DX(); endmodule +// module FL1P3IY(); endmodule +// module FL1P3JY(); endmodule +// module FL1S3AX(); endmodule +// module FL1S3AY(); endmodule + +// Diamond I/O buffers +module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule +module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule +module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule +module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I)); endmodule +module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule +module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule +module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule +module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule +module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule +module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) tio (.B(A), .O(Z)); endmodule +module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(Z), .I(A)); endmodule + +// Diamond I/O registers +module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +// TODO: Diamond I/O latches +// module IFS1S1B(input PD, D, SCLK, output Q); endmodule +// module IFS1S1D(input CD, D, SCLK, output Q); endmodule +// module IFS1S1I(input PD, D, SCLK, output Q); endmodule +// module IFS1S1J(input CD, D, SCLK, output Q); endmodule diff --git a/yosys/techlibs/ecp5/synth_ecp5.cc b/yosys/techlibs/ecp5/synth_ecp5.cc index c6e12248e..01222e55c 100644 --- a/yosys/techlibs/ecp5/synth_ecp5.cc +++ b/yosys/techlibs/ecp5/synth_ecp5.cc @@ -76,7 +76,7 @@ struct SynthEcp5Pass : public ScriptPass log(" -nodram\n"); log(" do not use distributed RAM cells in output netlist\n"); log("\n"); - log(" -nomux\n"); + log(" -nowidelut\n"); log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); log("\n"); log(" -abc2\n"); @@ -93,7 +93,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr; + bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, vpr; void clear_flags() YS_OVERRIDE { @@ -105,7 +105,7 @@ struct SynthEcp5Pass : public ScriptPass nodffe = false; nobram = false; nodram = false; - nomux = false; + nowidelut = false; flatten = true; retime = false; abc2 = false; @@ -172,8 +172,8 @@ struct SynthEcp5Pass : public ScriptPass nodram = true; continue; } - if (args[argidx] == "-nomux") { - nomux = true; + if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") { + nowidelut = true; continue; } if (args[argidx] == "-abc2") { @@ -264,7 +264,7 @@ struct SynthEcp5Pass : public ScriptPass run("abc", " (only if -abc2)"); } run("techmap -map +/ecp5/latches_map.v"); - if (nomux) + if (nowidelut) run("abc -lut 4 -dress"); else run("abc -lut 4:7 -dress"); diff --git a/yosys/techlibs/gowin/determine_init.cc b/yosys/techlibs/gowin/determine_init.cc index 991e5245a..d9a0880f6 100644 --- a/yosys/techlibs/gowin/determine_init.cc +++ b/yosys/techlibs/gowin/determine_init.cc @@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass { extra_args(args, args.size(), design); - size_t cnt = 0; + int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) @@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass { } } } - log_header(design, "Updated %lu cells with determined init value.\n", cnt); + log_header(design, "Updated %d cells with determined init value.\n", cnt); } } DetermineInitPass; diff --git a/yosys/techlibs/ice40/cells_sim.v b/yosys/techlibs/ice40/cells_sim.v index e89405b22..f9945b2b5 100644 --- a/yosys/techlibs/ice40/cells_sim.v +++ b/yosys/techlibs/ice40/cells_sim.v @@ -973,6 +973,30 @@ parameter RGB1_CURRENT = "0b000000"; parameter RGB2_CURRENT = "0b000000"; endmodule +(* blackbox *) +module SB_LED_DRV_CUR( + input EN, + output LEDPU +); +endmodule + +(* blackbox *) +module SB_RGB_DRV( + input RGBLEDEN, + input RGB0PWM, + input RGB1PWM, + input RGB2PWM, + input RGBPU, + output RGB0, + output RGB1, + output RGB2 +); +parameter CURRENT_MODE = "0b0"; +parameter RGB0_CURRENT = "0b000000"; +parameter RGB1_CURRENT = "0b000000"; +parameter RGB2_CURRENT = "0b000000"; +endmodule + (* blackbox *) module SB_I2C( input SBCLKI, diff --git a/yosys/techlibs/ice40/ice40_unlut.cc b/yosys/techlibs/ice40/ice40_unlut.cc index 2428a8e78..d16e6e6a3 100644 --- a/yosys/techlibs/ice40/ice40_unlut.cc +++ b/yosys/techlibs/ice40/ice40_unlut.cc @@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module) } struct Ice40UnlutPass : public Pass { - Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { } + Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| diff --git a/yosys/techlibs/xilinx/cells_sim.v b/yosys/techlibs/xilinx/cells_sim.v index 3a4540b83..f4598dcf4 100644 --- a/yosys/techlibs/xilinx/cells_sim.v +++ b/yosys/techlibs/xilinx/cells_sim.v @@ -278,6 +278,23 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +module RAM32X1D ( + output DPO, SPO, + input D, WCLK, WE, + input A0, A1, A2, A3, A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 +); + parameter INIT = 32'h0; + parameter IS_WCLK_INVERTED = 1'b0; + wire [4:0] a = {A4, A3, A2, A1, A0}; + wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}; + reg [31:0] mem = INIT; + assign SPO = mem[a]; + assign DPO = mem[dpra]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) if (WE) mem[a] <= D; +endmodule + module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, diff --git a/yosys/techlibs/xilinx/cells_xtra.sh b/yosys/techlibs/xilinx/cells_xtra.sh index 8e39b440d..83863bf0b 100644 --- a/yosys/techlibs/xilinx/cells_xtra.sh +++ b/yosys/techlibs/xilinx/cells_xtra.sh @@ -116,11 +116,11 @@ function xtract_cell_decl() xtract_cell_decl PS7 "(* keep *)" xtract_cell_decl PULLDOWN xtract_cell_decl PULLUP - xtract_cell_decl RAM128X1D + #xtract_cell_decl RAM128X1D xtract_cell_decl RAM128X1S xtract_cell_decl RAM256X1S xtract_cell_decl RAM32M - xtract_cell_decl RAM32X1D + #xtract_cell_decl RAM32X1D xtract_cell_decl RAM32X1S xtract_cell_decl RAM32X1S_1 xtract_cell_decl RAM32X2S diff --git a/yosys/techlibs/xilinx/cells_xtra.v b/yosys/techlibs/xilinx/cells_xtra.v index fbcc74682..6220da703 100644 --- a/yosys/techlibs/xilinx/cells_xtra.v +++ b/yosys/techlibs/xilinx/cells_xtra.v @@ -3655,17 +3655,6 @@ module PULLUP (...); output O; endmodule -module RAM128X1D (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input [6:0] A; - input [6:0] DPRA; - input D; - input WCLK; - input WE; -endmodule - module RAM128X1S (...); parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3705,13 +3694,6 @@ module RAM32M (...); input WE; endmodule -module RAM32X1D (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; -endmodule - module RAM32X1S (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; diff --git a/yosys/techlibs/xilinx/drams.txt b/yosys/techlibs/xilinx/drams.txt index 91632bcee..2613c206c 100644 --- a/yosys/techlibs/xilinx/drams.txt +++ b/yosys/techlibs/xilinx/drams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM64X1D init 1 abits 6 @@ -25,6 +38,13 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM64X1D min bits 5 min wports 1 diff --git a/yosys/techlibs/xilinx/drams_map.v b/yosys/techlibs/xilinx/drams_map.v index 47476b592..77041ca86 100644 --- a/yosys/techlibs/xilinx/drams_map.v +++ b/yosys/techlibs/xilinx/drams_map.v @@ -1,4 +1,38 @@ +module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [31:0] INIT = 32'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [4:0] A1ADDR; + output A1DATA; + + input [4:0] B1ADDR; + input B1DATA; + input B1EN; + + RAM32X1D #( + .INIT(INIT), + .IS_WCLK_INVERTED(!CLKPOL2) + ) _TECHMAP_REPLACE_ ( + .DPRA0(A1ADDR[0]), + .DPRA1(A1ADDR[1]), + .DPRA2(A1ADDR[2]), + .DPRA3(A1ADDR[3]), + .DPRA4(A1ADDR[4]), + .DPO(A1DATA), + + .A0(B1ADDR[0]), + .A1(B1ADDR[1]), + .A2(B1ADDR[2]), + .A3(B1ADDR[3]), + .A4(B1ADDR[4]), + .D(B1DATA), + .WCLK(CLK1), + .WE(B1EN) + ); +endmodule + module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); parameter [63:0] INIT = 64'bx; parameter CLKPOL2 = 1; diff --git a/yosys/techlibs/xilinx/synth_xilinx.cc b/yosys/techlibs/xilinx/synth_xilinx.cc index c20cac09b..7dc9915e9 100644 --- a/yosys/techlibs/xilinx/synth_xilinx.cc +++ b/yosys/techlibs/xilinx/synth_xilinx.cc @@ -42,8 +42,9 @@ struct SynthXilinxPass : public ScriptPass log(" -top \n"); log(" use the specified module as top module\n"); log("\n"); - log(" -arch {xcup|xcu|xc7|xc6s}\n"); + log(" -family {xcup|xcu|xc7|xc6s}\n"); log(" run synthesis for the specified Xilinx architecture\n"); + log(" generate the synthesis netlist for the specified family.\n"); log(" default: xc7\n"); log("\n"); log(" -edif \n"); @@ -67,6 +68,12 @@ struct SynthXilinxPass : public ScriptPass log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); + log(" -nocarry\n"); + log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -84,8 +91,8 @@ struct SynthXilinxPass : public ScriptPass log("\n"); } - std::string top_opt, edif_file, blif_file, arch; - bool flatten, retime, vpr, nobram, nodram, nosrl; + std::string top_opt, edif_file, blif_file, family; + bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut; void clear_flags() YS_OVERRIDE { @@ -98,7 +105,9 @@ struct SynthXilinxPass : public ScriptPass nobram = false; nodram = false; nosrl = false; - arch = "xc7"; + nocarry = false; + nowidelut = false; + family = "xc7"; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -113,8 +122,8 @@ struct SynthXilinxPass : public ScriptPass top_opt = "-top " + args[++argidx]; continue; } - if (args[argidx] == "-arch" && argidx+1 < args.size()) { - arch = args[++argidx]; + if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) { + family = args[++argidx]; continue; } if (args[argidx] == "-edif" && argidx+1 < args.size()) { @@ -141,6 +150,14 @@ struct SynthXilinxPass : public ScriptPass retime = true; continue; } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } + if (args[argidx] == "-nowidelut") { + nowidelut = true; + continue; + } if (args[argidx] == "-vpr") { vpr = true; continue; @@ -161,8 +178,8 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); - if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s") - log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str()); + if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s") + log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str()); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -229,11 +246,6 @@ struct SynthXilinxPass : public ScriptPass run("dff2dffe"); run("opt -full"); - if (!vpr || help_mode) - run("techmap -map +/xilinx/arith_map.v"); - else - run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -242,7 +254,15 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - run("techmap"); + if (help_mode) + run("techmap -map +/techmap.v [-map +/xilinx/arith_map.v]", "(skip if '-nocarry')"); + else if (!nocarry) { + if (!vpr) + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + else + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + } + run("opt -fast"); } @@ -253,7 +273,9 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (help_mode) - run("abc -luts 2:2,3,6:5,10,20 [-dff]"); + run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')"); + else if (nowidelut) + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run("clean"); diff --git a/yosys/tests/aiger/.gitignore b/yosys/tests/aiger/.gitignore index 073f46157..9a26bb8f4 100644 --- a/yosys/tests/aiger/.gitignore +++ b/yosys/tests/aiger/.gitignore @@ -1,2 +1 @@ -*.log -*.out +/*_ref.v diff --git a/yosys/tests/aiger/and.aig b/yosys/tests/aiger/and.aig deleted file mode 100644 index da0fa0719..000000000 --- a/yosys/tests/aiger/and.aig +++ /dev/null @@ -1,3 +0,0 @@ -aig 3 2 0 1 1 -6 - \ No newline at end of file diff --git a/yosys/tests/aiger/and.aag b/yosys/tests/aiger/and_.aag similarity index 55% rename from yosys/tests/aiger/and.aag rename to yosys/tests/aiger/and_.aag index d1ef2c5a5..cadd505f0 100644 --- a/yosys/tests/aiger/and.aag +++ b/yosys/tests/aiger/and_.aag @@ -3,3 +3,6 @@ aag 3 2 0 1 1 4 6 6 2 4 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/yosys/tests/aiger/and_.aig b/yosys/tests/aiger/and_.aig new file mode 100644 index 000000000..13c7a0c17 --- /dev/null +++ b/yosys/tests/aiger/and_.aig @@ -0,0 +1,5 @@ +aig 3 2 0 1 1 +6 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/yosys/tests/aiger/buffer.aag b/yosys/tests/aiger/buffer.aag index 94a6fb1ed..211106ed6 100644 --- a/yosys/tests/aiger/buffer.aag +++ b/yosys/tests/aiger/buffer.aag @@ -1,3 +1,5 @@ aag 1 1 0 1 0 2 2 +i0 pi0 +o0 po0 diff --git a/yosys/tests/aiger/buffer.aig b/yosys/tests/aiger/buffer.aig index 0c715fdeb..01df6f1cf 100644 --- a/yosys/tests/aiger/buffer.aig +++ b/yosys/tests/aiger/buffer.aig @@ -1,2 +1,4 @@ aig 1 1 0 1 0 2 +i0 pi0 +o0 po0 diff --git a/yosys/tests/aiger/cnt1.aag b/yosys/tests/aiger/cnt1.aag index ce4f28fcb..75598862c 100644 --- a/yosys/tests/aiger/cnt1.aag +++ b/yosys/tests/aiger/cnt1.aag @@ -1,3 +1,4 @@ aag 1 0 1 0 0 1 2 3 2 +b0 po0 diff --git a/yosys/tests/aiger/cnt1.aig b/yosys/tests/aiger/cnt1.aig index 8d0ba13b1..6fcf62522 100644 --- a/yosys/tests/aiger/cnt1.aig +++ b/yosys/tests/aiger/cnt1.aig @@ -1,3 +1,4 @@ aig 1 0 1 0 0 1 3 2 +b0 po0 diff --git a/yosys/tests/aiger/cnt1e.aag b/yosys/tests/aiger/cnt1e.aag index 6db3f0ffd..35cd5a482 100644 --- a/yosys/tests/aiger/cnt1e.aag +++ b/yosys/tests/aiger/cnt1e.aag @@ -6,3 +6,4 @@ aag 5 1 1 0 3 1 8 4 2 10 9 7 b0 AIGER_NEVER +i0 po0 diff --git a/yosys/tests/aiger/cnt1e.aig b/yosys/tests/aiger/cnt1e.aig index d8d159f11..7284dd42a 100644 --- a/yosys/tests/aiger/cnt1e.aig +++ b/yosys/tests/aiger/cnt1e.aig @@ -1,4 +1,5 @@ aig 5 1 1 0 3 1 10 4 -b0 AIGER_NEVER +i0 po0 +b0 AIGER_NEVER diff --git a/yosys/tests/aiger/false.aag b/yosys/tests/aiger/false.aag index 421e64a91..bab4a06a6 100644 --- a/yosys/tests/aiger/false.aag +++ b/yosys/tests/aiger/false.aag @@ -1,2 +1,3 @@ aag 0 0 0 1 0 0 +o0 po0 diff --git a/yosys/tests/aiger/false.aig b/yosys/tests/aiger/false.aig index ad7d039fa..4dc442d7b 100644 --- a/yosys/tests/aiger/false.aig +++ b/yosys/tests/aiger/false.aig @@ -1,2 +1,3 @@ aig 0 0 0 1 0 0 +o0 po0 diff --git a/yosys/tests/aiger/inverter.aag b/yosys/tests/aiger/inverter.aag index ff7c28542..428bad9e4 100644 --- a/yosys/tests/aiger/inverter.aag +++ b/yosys/tests/aiger/inverter.aag @@ -1,3 +1,5 @@ aag 1 1 0 1 0 2 3 +i0 pi0 +o0 po0 diff --git a/yosys/tests/aiger/inverter.aig b/yosys/tests/aiger/inverter.aig index 525d82392..5bec90ae3 100644 --- a/yosys/tests/aiger/inverter.aig +++ b/yosys/tests/aiger/inverter.aig @@ -1,2 +1,4 @@ aig 1 1 0 1 0 3 +i0 pi0 +o0 po0 diff --git a/yosys/tests/aiger/notcnt1e.aag b/yosys/tests/aiger/notcnt1e.aag index 141c864f7..2ed645d84 100644 --- a/yosys/tests/aiger/notcnt1e.aag +++ b/yosys/tests/aiger/notcnt1e.aag @@ -6,3 +6,4 @@ aag 5 1 1 0 3 1 8 4 2 10 9 7 b0 AIGER_NEVER +i0 pi0 diff --git a/yosys/tests/aiger/notcnt1e.aig b/yosys/tests/aiger/notcnt1e.aig index 7c85a7290..fd7e94508 100644 --- a/yosys/tests/aiger/notcnt1e.aig +++ b/yosys/tests/aiger/notcnt1e.aig @@ -1,4 +1,5 @@ aig 5 1 1 0 3 1 10 5 -b0 AIGER_NEVER +i0 pi0 +b0 AIGER_NEVER diff --git a/yosys/tests/aiger/or.aig b/yosys/tests/aiger/or.aig deleted file mode 100644 index 75c9e4480..000000000 --- a/yosys/tests/aiger/or.aig +++ /dev/null @@ -1,3 +0,0 @@ -aig 3 2 0 1 1 -7 - \ No newline at end of file diff --git a/yosys/tests/aiger/or.aag b/yosys/tests/aiger/or_.aag similarity index 55% rename from yosys/tests/aiger/or.aag rename to yosys/tests/aiger/or_.aag index f780e339f..0f619dba3 100644 --- a/yosys/tests/aiger/or.aag +++ b/yosys/tests/aiger/or_.aag @@ -3,3 +3,6 @@ aag 3 2 0 1 1 4 7 6 3 5 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/yosys/tests/aiger/or_.aig b/yosys/tests/aiger/or_.aig new file mode 100644 index 000000000..051687512 --- /dev/null +++ b/yosys/tests/aiger/or_.aig @@ -0,0 +1,5 @@ +aig 3 2 0 1 1 +7 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/yosys/tests/aiger/run-test.sh b/yosys/tests/aiger/run-test.sh index e0a34f023..deaf48a3d 100755 --- a/yosys/tests/aiger/run-test.sh +++ b/yosys/tests/aiger/run-test.sh @@ -1,24 +1,54 @@ #!/bin/bash +set -e + OPTIND=1 -seed="" # default to no seed specified -while getopts "S:" opt +abcprog="../../yosys-abc" # default to built-in version of abc +while getopts "A:" opt do case "$opt" in - S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space - seed="SEED=$arg" ;; + A) abcprog="$OPTARG" ;; esac done shift "$((OPTIND-1))" -# check for Icarus Verilog -if ! which iverilog > /dev/null ; then - echo "$0: Error: Icarus Verilog 'iverilog' not found." - exit 1 -fi +# NB: *.aag and *.aig must contain a symbol table naming the primary +# inputs and outputs, otherwise ABC and Yosys will name them +# arbitrarily (and inconsistently with each other). -echo "===== AAG ======" -${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" +for aag in *.aag; do + # Since ABC cannot read *.aag, read the *.aig instead + # (which would have been created by the reference aig2aig utility, + # available from http://fmv.jku.at/aiger/) + echo "Checking $aag." + $abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" + ../../yosys -qp " +read_verilog ${aag%.*}_ref.v +prep +design -stash gold +read_aiger -clk_name clock $aag +prep +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 16 miter +" +done -echo "===== AIG ======" -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger" +for aig in *.aig; do + echo "Checking $aig." + $abcprog -q "read -c $aig; write ${aig%.*}_ref.v" + ../../yosys -qp " +read_verilog ${aig%.*}_ref.v +prep +design -stash gold +read_aiger -clk_name clock $aig +prep +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 16 miter +" +done diff --git a/yosys/tests/aiger/toggle.aag b/yosys/tests/aiger/toggle.aag index 09651012d..b1a1582d7 100644 --- a/yosys/tests/aiger/toggle.aag +++ b/yosys/tests/aiger/toggle.aag @@ -2,3 +2,5 @@ aag 1 0 1 2 0 2 3 2 3 +o0 po0 +o1 po1 diff --git a/yosys/tests/aiger/toggle.aig b/yosys/tests/aiger/toggle.aig index b69e21aaf..68b41763f 100644 --- a/yosys/tests/aiger/toggle.aig +++ b/yosys/tests/aiger/toggle.aig @@ -2,3 +2,5 @@ aig 1 0 1 2 0 3 2 3 +o0 po0 +o1 po1 diff --git a/yosys/tests/aiger/true.aag b/yosys/tests/aiger/true.aag index 366893648..66a9eab46 100644 --- a/yosys/tests/aiger/true.aag +++ b/yosys/tests/aiger/true.aag @@ -1,2 +1,3 @@ aag 0 0 0 1 0 1 +o0 po0 diff --git a/yosys/tests/aiger/true.aig b/yosys/tests/aiger/true.aig index 10086f389..f9bad6000 100644 --- a/yosys/tests/aiger/true.aig +++ b/yosys/tests/aiger/true.aig @@ -1,2 +1,3 @@ aig 0 0 0 1 0 1 +o0 po0 diff --git a/yosys/tests/arch/run-test.sh b/yosys/tests/arch/run-test.sh new file mode 100755 index 000000000..5292d1615 --- /dev/null +++ b/yosys/tests/arch/run-test.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -e + +echo "Running syntax check on arch sim models" +for arch in ../../techlibs/*; do + find $arch -name cells_sim.v | while read path; do + echo -n "Test $path ->" + iverilog -t null -I$arch $path + echo " ok" + done +done + +for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do + echo -n "Test $path ->" + iverilog -t null $path + echo " ok" +done diff --git a/yosys/tests/memories/issue00335.v b/yosys/tests/memories/issue00335.v new file mode 100644 index 000000000..f3b6e5dfe --- /dev/null +++ b/yosys/tests/memories/issue00335.v @@ -0,0 +1,28 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk + +module ram2 (input clk, + input sel, + input we, + input [SIZE-1:0] adr, + input [63:0] dat_i, + output reg [63:0] dat_o); + parameter SIZE = 5; // Address size + + reg [63:0] mem [0:(1 << SIZE)-1]; + integer i; + + initial begin + for (i = 0; i < (1<= 0; i = i-1) begin + assign o[i] = 1'b0; + end +endgenerate +endmodule diff --git a/yosys/tests/simple/implicit_ports.v b/yosys/tests/simple/implicit_ports.v new file mode 100644 index 000000000..8b0a6f386 --- /dev/null +++ b/yosys/tests/simple/implicit_ports.v @@ -0,0 +1,16 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); + wire cin = 1; + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule diff --git a/yosys/tests/simple/peepopt.v b/yosys/tests/simple/peepopt.v index b27b9fe57..1bf427897 100644 --- a/yosys/tests/simple/peepopt.v +++ b/yosys/tests/simple/peepopt.v @@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in assign o = i[s*W+:W]; endmodule +module peepopt_shiftmul_1 (output y, input [2:0] w); +assign y = 1'b1 >> (w * (3'b110)); +endmodule + module peepopt_muldiv_0(input [1:0] i, output [1:0] o); wire [3:0] t; assign t = i * 3; diff --git a/yosys/tests/simple/run-test.sh b/yosys/tests/simple/run-test.sh index aaa1cf940..967ac49f2 100755 --- a/yosys/tests/simple/run-test.sh +++ b/yosys/tests/simple/run-test.sh @@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then exit 1 fi -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v +shopt -s nullglob +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v} diff --git a/yosys/tests/simple/wandwor.v b/yosys/tests/simple/wandwor.v new file mode 100644 index 000000000..34404aa26 --- /dev/null +++ b/yosys/tests/simple/wandwor.v @@ -0,0 +1,36 @@ +module wandwor_test0 (A, B, C, D, X, Y, Z); + input A, B, C, D; + output wor X; + output wand Y; + output Z; + + assign X = A, X = B, Y = C, Y = D; + foo foo_0 (C, D, X); + foo foo_1 (A, B, Y); + foo foo_2 (X, Y, Z); +endmodule + +module wandwor_test1 (A, B, C, D, X, Y, Z); + input [3:0] A, B, C, D; + output wor [3:0] X; + output wand [3:0] Y; + output Z; + + bar bar_inst ( + .I0({A, B}), + .I1({B, A}), + .O({X, Y}) + ); + + assign X = C, X = D; + assign Y = C, Y = D; + assign Z = ^{X,Y}; +endmodule + +module foo(input I0, I1, output O); + assign O = I0 ^ I1; +endmodule + +module bar(input [7:0] I0, I1, output [7:0] O); + assign O = I0 + I1; +endmodule diff --git a/yosys/tests/tools/autotest.sh b/yosys/tests/tools/autotest.sh index 920474a84..4d3478628 100755 --- a/yosys/tests/tools/autotest.sh +++ b/yosys/tests/tools/autotest.sh @@ -23,12 +23,13 @@ warn_iverilog_git=false # The tests are skipped if firrtl2verilog is the empty string (the default). firrtl2verilog="" xfirrtl="../xfirrtl" +abcprog="$toolsdir/../../yosys-abc" if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi -while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do +while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do case "$opt" in x) use_xsim=true ;; @@ -65,6 +66,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do include_opts="$include_opts -I $OPTARG" xinclude_opts="$xinclude_opts -i $OPTARG" minclude_opts="$minclude_opts +incdir+$OPTARG" ;; + A) + abcprog="$OPTARG" ;; -) case "${OPTARG}" in xfirrtl) @@ -89,6 +92,12 @@ done compile_and_run() { exe="$1"; output="$2"; shift 2 + if [ "${2##*.}" == "sv" ]; then + language_gen="-g2012" + else + language_gen="-g2005" + fi + if $use_modelsim; then altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) /opt/altera/$altver/modelsim_ase/bin/vlib work @@ -99,7 +108,7 @@ compile_and_run() { /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@" /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench else - iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" + iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" vvp -n "$exe" fi } @@ -110,7 +119,7 @@ for fn do bn=${fn%.*} ext=${fn##*.} - if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then + if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then echo "Invalid argument: $fn" >&2 exit 1 fi @@ -123,6 +132,10 @@ do echo -n "Test: $bn " fi + if [ "$ext" == sv ]; then + frontend="$frontend -sv" + fi + rm -f ${bn}.{err,log,skip} mkdir -p ${bn}.out rm -rf ${bn}.out/* @@ -131,22 +144,25 @@ do cd ${bn}.out fn=$(basename $fn) bn=$(basename $bn) + refext=v rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} + elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then + $abcprog -c "read_aiger ../${fn}; write ${bn}_ref.${refext}" else - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} - frontend="verilog -noblackbox" + refext=$ext + cp ../${fn} ${bn}_ref.${refext} fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v + "$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} else cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi - compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \ + compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \ "$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi @@ -163,25 +179,25 @@ do test_count=$(( test_count + 1 )) } - if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then + if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.${refext}; then touch ../${bn}.skip return fi if [ -n "$scriptfiles" ]; then - test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles + test_passes -f "$frontend $include_opts" ${bn}_ref.${refext} $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${refext} elif [ "$frontend" = "verific" ]; then - test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -all; opt; memory;;" elif [ "$frontend" = "verific_gates" ]; then - test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v - test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${refext} + test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext} if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then - "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v + "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.${refext} $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v fi diff --git a/yosys/tests/various/.gitignore b/yosys/tests/various/.gitignore index 397b4a762..7b3e8c68e 100644 --- a/yosys/tests/various/.gitignore +++ b/yosys/tests/various/.gitignore @@ -1 +1,2 @@ -*.log +/*.log +/*.out diff --git a/yosys/tests/various/attrib05_port_conn.v b/yosys/tests/various/attrib05_port_conn.v new file mode 100644 index 000000000..e20e66319 --- /dev/null +++ b/yosys/tests/various/attrib05_port_conn.v @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); +endmodule + diff --git a/yosys/tests/various/attrib05_port_conn.ys b/yosys/tests/various/attrib05_port_conn.ys new file mode 100644 index 000000000..27a016733 --- /dev/null +++ b/yosys/tests/various/attrib05_port_conn.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib05_port_conn.v diff --git a/yosys/tests/various/attrib07_func_call.v b/yosys/tests/various/attrib07_func_call.v new file mode 100644 index 000000000..f55ef2316 --- /dev/null +++ b/yosys/tests/various/attrib07_func_call.v @@ -0,0 +1,21 @@ +function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + +endfunction + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + +endmodule + diff --git a/yosys/tests/various/attrib07_func_call.ys b/yosys/tests/various/attrib07_func_call.ys new file mode 100644 index 000000000..774827651 --- /dev/null +++ b/yosys/tests/various/attrib07_func_call.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib07_func_call.v diff --git a/yosys/tests/various/elab_sys_tasks.sv b/yosys/tests/various/elab_sys_tasks.sv new file mode 100644 index 000000000..774d85b32 --- /dev/null +++ b/yosys/tests/various/elab_sys_tasks.sv @@ -0,0 +1,30 @@ +module test; +localparam X=1; +genvar i; +generate +if (X == 1) + $info("X is 1"); +if (X == 1) + $warning("X is 1"); +else + $error("X is not 1"); +case (X) + 1: $info("X is 1 in a case statement"); +endcase +//case (X-1) +// 1: $warn("X is 2"); +// default: $warn("X might be anything in a case statement"); +//endcase +for (i = 0; i < 3; i = i + 1) +begin + case(i) + 0: $info; + 1: $warning; + default: $info("default case statemnent"); + endcase +end + +$info("This is a standalone $info(). Next $info has no parameters"); +$info; +endgenerate +endmodule diff --git a/yosys/tests/various/elab_sys_tasks.ys b/yosys/tests/various/elab_sys_tasks.ys new file mode 100644 index 000000000..45bee3a60 --- /dev/null +++ b/yosys/tests/various/elab_sys_tasks.ys @@ -0,0 +1 @@ +read_verilog -sv elab_sys_tasks.sv diff --git a/yosys/tests/various/muxcover.ys b/yosys/tests/various/muxcover.ys index 7ac460f13..67e9625e6 100644 --- a/yosys/tests/various/muxcover.ys +++ b/yosys/tests/various/muxcover.ys @@ -13,7 +13,7 @@ read_verilog -formal < (Q : D)) = (1, 2:3:4); +`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS + if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); +`endif endspecify endmodule @@ -28,3 +30,10 @@ module test2 ( (B => Q) = 1.5; endspecify endmodule + +module issue01144(input clk, d, output q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule diff --git a/yosys/tests/various/specify.ys b/yosys/tests/various/specify.ys index a5ca07219..00597e1e2 100644 --- a/yosys/tests/various/specify.ys +++ b/yosys/tests/various/specify.ys @@ -54,3 +54,5 @@ equiv_struct equiv_induct -seq 5 equiv_status -assert design -reset + +read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v From 1c7fdac3f2ecb5edc95a1744a25989107556ed23 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 27 Nov 2019 14:42:18 -0700 Subject: [PATCH 481/482] add CMakefile for yosys --- yosys/CMakeLists.txt | 103 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 yosys/CMakeLists.txt diff --git a/yosys/CMakeLists.txt b/yosys/CMakeLists.txt new file mode 100644 index 000000000..9ec574964 --- /dev/null +++ b/yosys/CMakeLists.txt @@ -0,0 +1,103 @@ +cmake_minimum_required(VERSION 3.3.0) + +include(CMakeParseArguments) + +project(yosys) + +# Version number +set(YOSYS_VERSION_MAJOR 0.7) +set(YOSYS_VERSION_MINOR 0) +set(YOSYS_VERSION_PATCH 0) + +# Options to enable/disable dependencies +option(YOSYS_ENABLE_TCL, "Enable TCL parser integrated in yosys" ON) +option(YOSYS_ENABLE_ABC, "Enable ABC library integrated in yosys" ON) +option(YOSYS_ENABLE_PLUGINS, "Enable plug-in in yosys" ON) +option(YOSYS_ENABLE_READLINE, "Enable readline library in yosys" ON) +option(YOSYS_ENABLE_VERIFIC, "Enable verification library in yosys" OFF) +option(YOSYS_ENABLE_COVER, "Enable coverage test in yosys" ON) +option(YOSYS_ENABLE_LIBYOSYS, "Enable static library compiled yosys" OFF) +option(YOSYS_ENABLE_GPROF, "Enable profiling in compiled yosys" OFF) +option(YOSYS_ENABLE_NDEBUG, "Enable non-debugging feature in compiled yosys" OFF) + +# +## Search and link dependent packages +## We need readline to compile +if (YOSYS_ENABLE_READLINE) + find_package(Readline REQUIRED) +endif() +# +######################### +## # +## Compiler Flags Setup # +## # +######################### +# +## Compiler flag configuration checks +include(CheckCCompilerFlag) +include(CheckCXXCompilerFlag) +# +## Required Compiler Standard +#set(CMAKE_CXX_STANDARD 11) # need at least c+11 standard +#set(CMAKE_CXX_STANDARD_REQUIRED ON) +# +## Set warning flags +#set(WARN_FLAGS_TO_CHECK "") # checklist of warning flags +#set(WARN_FLAGS "") # actual warning flags to be added during compilation +## Add warning flags depending on options +#if (YOSYS_ENABLE_NDEBUG) +# set(WARN_FLAGS_TO_CHECK, ${WARN_FLAGS_TO_CHECK}, "-O3") +#endif() +# +# +##Collect the source files +#file(GLOB_RECURSE EXEC_YOSYS kernel/yosys.cc) +#file(GLOB_RECURSE LIB_SOURCES kernel/*.cc) +#file(GLOB_RECURSE LIB_HEADERS kernel/*.h) +#files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) +# +## Use c++ compiler for c source files +#set_source_files_properties(${LIB_SOURCES} PROPERTIES LANGUAGE CXX) +#set_source_files_properties(${EXEC_SOURCES} PROPERTIES LANGUAGE CXX) +#set_source_files_properties(${EXEC_SOURCES_SHELL} PROPERTIES LANGUAGE CXX) +# +##Build the library +#add_library(libyosys STATIC +# ${LIB_HEADERS} +# ${LIB_SOURCES}) +# +## add header files to be included +#target_include_directories(libyosys PUBLIC ${LIB_INCLUDE_DIRS}) +#set_target_properties(libyosys PROPERTIES PREFIX "") #Avoid extra 'lib' prefix#Create the executable +# +##Specify link-time dependancies +#target_link_libraries(libyosys +# readline) +# +## Build targets +## 1. yosys +#add_executable(yosys ${EXEC_SOURCES}) +#target_link_libraries(vpr +# libyosys) +# 2. yosys-config + +# run makefile provided, we pass-on the options to the local make file +add_custom_target( + yosys ALL + COMMAND + $(MAKE) + #CC=${CMAKE_C_COMPILER} + #CXX=${CMAKE_CXX_COMPILER} + #LD=${CMAKE_CXX_COMPILER} + #ENABLE_TCL=${YOSYS_ENABLE_TCL} + #ENABLE_ABC=${YOSYS_ENABLE_ABC} + #ENABLE_PLUGINS=${YOSYS_ENABLE_PLUGINS} + #ENABLE_READLINE=${YOSYS_ENABLE_READLINE} + #ENABLE_VERIFIC=${YOSYS_ENABLE_VERIFIC} + #ENABLE_COVER=${YOSYS_ENABLE_COVER} + #ENABLE_LIBYOSYS=${YOSYS_ENABLE_LIBYOSYS} + #ENABLE_GPROF=${YOSYS_ENABLE_GPROF} + #ENABLE_NDEBUG=${YOSYS_ENABLE_NDEBUG} + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMENT "Compile Yosys with given Makefile" +) From 5b4ddfb3ceca210fcdbccb1a63589b9df8c3efa5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 27 Nov 2019 14:42:47 -0700 Subject: [PATCH 482/482] use adapt yosys Makefile for OpenFPGA framework --- yosys/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/yosys/Makefile b/yosys/Makefile index a67315415..3c1f51e7e 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -1,6 +1,6 @@ -CONFIG := clang -# CONFIG := gcc +# CONFIG := clang +CONFIG := gcc # CONFIG := gcc-4.8 # CONFIG := afl-gcc # CONFIG := emcc @@ -9,7 +9,7 @@ CONFIG := clang # CONFIG := msys2-64 # features (the more the better) -ENABLE_TCL := 1 +ENABLE_TCL := 0 ENABLE_ABC := 1 ENABLE_GLOB := 1 ENABLE_PLUGINS := 1